diff --git a/.gitignore b/.gitignore index c2a029f..3339a25 100644 --- a/.gitignore +++ b/.gitignore @@ -275,4 +275,7 @@ doc/build .vscode/.browse.c_cpp.db* .vscode/c_cpp_properties.json .vscode/launch.json -.vscode/ipch \ No newline at end of file +.vscode/ipch +.vscode/.cortex-debug.registers.state.json +.vscode/.cortex-debug.peripherals.state.json +.vscode/settings.json diff --git a/.travis.yml b/.travis.yml index a4a9889..97b0ce8 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,64 +1,102 @@ - matrix: - include: - # Test build for Linux platform - - language: cpp - os: linux - addons: - apt: - sources: - - ubuntu-toolchain-r-test - packages: - - g++-7 - - python3.7 - env: - - MATRIX_EVAL="CC=gcc-7 && CXX=g++-7" - cache: - directories: - git: - depth: false - quiet: true - - before_install: - - eval "${MATRIX_EVAL}" - - install: - - script: - - mkdir -p build - - cd build - - cmake .. - - make - - # Test build for PlatformIO based projects - - language: python - python: - - "3.8" - cache: - directories: - - "~/.platformio" - env: - - PLATFORMIO_EXTRA_SCRIPTS=pre:/tmp/scripts/custom_hwids.py - install: - - pip install -U platformio - - platformio update - script: - # PRE scripts have to be copied manually as "platformio ci does not care about it" - - mkdir -p /tmp/scripts - - cp examples/knx-usb/custom_hwids.py /tmp/scripts - - # Enable verbose output of platformio - #- platformio settings set force_verbose yes - - - echo "-------";echo "Compiling example knx-usb";echo "--------"; - - platformio ci --lib="." --project-conf=examples/knx-usb/platformio-ci.ini examples/knx-usb/src/main.cpp - - - echo "-------";echo "Compiling example knx-demo";echo "--------"; - - platformio ci --lib="." --project-conf=examples/knx-demo/platformio-ci.ini examples/knx-demo/knx-demo.ino - - - echo "-------";echo "Compiling example knx-demo-coupler";echo "--------"; - - platformio ci --lib="." --project-conf=examples/knx-demo-coupler/platformio-ci.ini examples/knx-demo-coupler/knx-demo-coupler.ino - -notifications: - email: - on_success: change - on_failure: change + matrix: + include: + # Test build for Linux platform + - language: cpp + dist: focal + os: linux + addons: + apt: + sources: + - ubuntu-toolchain-r-test + packages: + - g++-7 + - python3.8 + env: + - MATRIX_EVAL="CC=gcc-7 && CXX=g++-7" + cache: + directories: + git: + depth: false + quiet: true + + before_install: + - eval "${MATRIX_EVAL}" + + install: + + script: + - mkdir -p build + - cd build + - cmake .. + - cmake --build . + + # Test build for CC13x0 platform + - language: cpp + dist: focal + os: linux + addons: + apt: + sources: + packages: + - cmake + - binutils-arm-none-eabi + - gcc-arm-none-eabi + - libnewlib-arm-none-eabi + - libstdc++-arm-none-eabi-newlib + env: + - MATRIX_EVAL="CC=arm-none-eabi-gcc && CXX=arm-none-eabi-g++" + cache: + directories: + git: + depth: false + quiet: true + + before_install: + - eval "${MATRIX_EVAL}" + + install: + + before_script: + - arm-none-eabi-gcc --version + + script: + - echo "building knx-cc1310" + - cd examples/knx-cc1310 + - mkdir -p build + - cd build + - cmake -DCMAKE_BUILD_TYPE=Debug .. + - cmake --build . + + # Test build for PlatformIO based projects + - language: python + python: + - "3.8" + cache: + directories: + - "~/.platformio" + env: + - PLATFORMIO_EXTRA_SCRIPTS=pre:/tmp/scripts/custom_hwids.py + install: + - pip install -U platformio + - platformio update + script: + # PRE scripts have to be copied manually as "platformio ci does not care about it" + - mkdir -p /tmp/scripts + - cp examples/knx-usb/custom_hwids.py /tmp/scripts + + # Enable verbose output of platformio + #- platformio settings set force_verbose yes + + - echo "-------";echo "Compiling example knx-usb";echo "--------"; + - platformio ci --lib="." --project-conf=examples/knx-usb/platformio-ci.ini examples/knx-usb/src/main.cpp + + - echo "-------";echo "Compiling example knx-demo";echo "--------"; + - platformio ci --lib="." --project-conf=examples/knx-demo/platformio-ci.ini examples/knx-demo/knx-demo.ino + + - echo "-------";echo "Compiling example knx-demo-coupler";echo "--------"; + - platformio ci --lib="." --project-conf=examples/knx-demo-coupler/platformio-ci.ini examples/knx-demo-coupler/knx-demo-coupler.ino + +notifications: + email: + on_success: change + on_failure: change diff --git a/.vscode/settings.json b/.vscode/settings.json deleted file mode 100644 index bef847b..0000000 --- a/.vscode/settings.json +++ /dev/null @@ -1,4 +0,0 @@ -{ - "cmake.sourceDirectory": "${workspaceFolder}/.", - "C_Cpp.default.configurationProvider": "ms-vscode.cmake-tools" -} \ No newline at end of file diff --git a/examples/knx-cc1310/Board.h b/examples/knx-cc1310/Board.h new file mode 100644 index 0000000..eef0f0a --- /dev/null +++ b/examples/knx-cc1310/Board.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BOARD_H +#define __BOARD_H + +#define Board_CC1310_LAUNCHXL + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define Board_initGeneral() Board_init() /* deprecated */ + +#include "CC1310_LAUNCHXL.h" + +#define Board_shutDownExtFlash() CC1310_LAUNCHXL_shutDownExtFlash() +#define Board_wakeUpExtFlash() CC1310_LAUNCHXL_wakeUpExtFlash() + +/* These #defines allow us to reuse TI-RTOS across other device families */ + +#define Board_ADC0 CC1310_LAUNCHXL_ADC0 +#define Board_ADC1 CC1310_LAUNCHXL_ADC1 + +#define Board_ADCBUF0 CC1310_LAUNCHXL_ADCBUF0 +#define Board_ADCBUF0CHANNEL0 CC1310_LAUNCHXL_ADCBUF0CHANNEL0 +#define Board_ADCBUF0CHANNEL1 CC1310_LAUNCHXL_ADCBUF0CHANNEL1 + +#define Board_CRYPTO0 CC1310_LAUNCHXL_CRYPTO0 +#define Board_AESCCM0 CC1310_LAUNCHXL_AESCCM0 +#define Board_AESGCM0 CC1310_LAUNCHXL_AESGCM0 +#define Board_AESCBC0 CC1310_LAUNCHXL_AESCBC0 +#define Board_AESCTR0 CC1310_LAUNCHXL_AESCTR0 +#define Board_AESECB0 CC1310_LAUNCHXL_AESECB0 +#define Board_AESCTRDRBG0 CC1310_LAUNCHXL_AESCTRDRBG0 +#define Board_TRNG0 CC1310_LAUNCHXL_TRNG0 + +#define Board_DIO0 CC1310_LAUNCHXL_DIO0 +#define Board_DIO1 CC1310_LAUNCHXL_DIO1 +#define Board_DIO12 CC1310_LAUNCHXL_DIO12 +#define Board_DIO15 CC1310_LAUNCHXL_DIO15 +#define Board_DIO16_TDO CC1310_LAUNCHXL_DIO16_TDO +#define Board_DIO17_TDI CC1310_LAUNCHXL_DIO17_TDI +#define Board_DIO21 CC1310_LAUNCHXL_DIO21 +#define Board_DIO22 CC1310_LAUNCHXL_DIO22 + +#define Board_GPIO_BUTTON0 CC1310_LAUNCHXL_GPIO_S1 +#define Board_GPIO_BUTTON1 CC1310_LAUNCHXL_GPIO_S2 +#define Board_GPIO_BTN1 CC1310_LAUNCHXL_GPIO_S1 +#define Board_GPIO_BTN2 CC1310_LAUNCHXL_GPIO_S2 +#define Board_GPIO_LED0 CC1310_LAUNCHXL_GPIO_LED_RED +#define Board_GPIO_LED1 CC1310_LAUNCHXL_GPIO_LED_GREEN +#define Board_GPIO_RLED CC1310_LAUNCHXL_GPIO_LED_RED +#define Board_GPIO_GLED CC1310_LAUNCHXL_GPIO_LED_GREEN +#define Board_GPIO_LED_ON CC1310_LAUNCHXL_GPIO_LED_ON +#define Board_GPIO_LED_OFF CC1310_LAUNCHXL_GPIO_LED_OFF +#define Board_GPIO_TMP116_EN CC1310_LAUNCHXL_GPIO_TMP116_EN + +#define Board_GPTIMER0A CC1310_LAUNCHXL_GPTIMER0A +#define Board_GPTIMER0B CC1310_LAUNCHXL_GPTIMER0B +#define Board_GPTIMER1A CC1310_LAUNCHXL_GPTIMER1A +#define Board_GPTIMER1B CC1310_LAUNCHXL_GPTIMER1B +#define Board_GPTIMER2A CC1310_LAUNCHXL_GPTIMER2A +#define Board_GPTIMER2B CC1310_LAUNCHXL_GPTIMER2B +#define Board_GPTIMER3A CC1310_LAUNCHXL_GPTIMER3A +#define Board_GPTIMER3B CC1310_LAUNCHXL_GPTIMER3B + +#define Board_I2C0 CC1310_LAUNCHXL_I2C0 +#define Board_I2C_TMP CC1310_LAUNCHXL_I2C0 + +#define Board_I2S0 CC1310_LAUNCHXL_I2S0 +#define Board_I2S_ADO CC1310_LAUNCHXL_I2S_ADO +#define Board_I2S_ADI CC1310_LAUNCHXL_I2S_ADI +#define Board_I2S_BCLK CC1310_LAUNCHXL_I2S_BCLK +#define Board_I2S_MCLK CC1310_LAUNCHXL_I2S_MCLK +#define Board_I2S_WCLK CC1310_LAUNCHXL_I2S_WCLK + +#define Board_NVSINTERNAL CC1310_LAUNCHXL_NVSCC26XX0 +#define Board_NVSEXTERNAL CC1310_LAUNCHXL_NVSSPI25X0 + +#define Board_PIN_BUTTON0 CC1310_LAUNCHXL_PIN_BTN1 +#define Board_PIN_BUTTON1 CC1310_LAUNCHXL_PIN_BTN2 +#define Board_PIN_BTN1 CC1310_LAUNCHXL_PIN_BTN1 +#define Board_PIN_BTN2 CC1310_LAUNCHXL_PIN_BTN2 +#define Board_PIN_LED0 CC1310_LAUNCHXL_PIN_RLED +#define Board_PIN_LED1 CC1310_LAUNCHXL_PIN_GLED +#define Board_PIN_LED2 CC1310_LAUNCHXL_PIN_RLED +#define Board_PIN_RLED CC1310_LAUNCHXL_PIN_RLED +#define Board_PIN_GLED CC1310_LAUNCHXL_PIN_GLED + +#define Board_PWM0 CC1310_LAUNCHXL_PWM0 +#define Board_PWM1 CC1310_LAUNCHXL_PWM1 +#define Board_PWM2 CC1310_LAUNCHXL_PWM2 +#define Board_PWM3 CC1310_LAUNCHXL_PWM3 +#define Board_PWM4 CC1310_LAUNCHXL_PWM4 +#define Board_PWM5 CC1310_LAUNCHXL_PWM5 +#define Board_PWM6 CC1310_LAUNCHXL_PWM6 +#define Board_PWM7 CC1310_LAUNCHXL_PWM7 + +#define Board_SD0 CC1310_LAUNCHXL_SDSPI0 + +#define Board_SPI0 CC1310_LAUNCHXL_SPI0 +#define Board_SPI1 CC1310_LAUNCHXL_SPI1 +#define Board_SPI_FLASH_CS CC1310_LAUNCHXL_SPI_FLASH_CS +#define Board_FLASH_CS_ON 0 +#define Board_FLASH_CS_OFF 1 + +#define Board_SPI_MASTER CC1310_LAUNCHXL_SPI0 +#define Board_SPI_SLAVE CC1310_LAUNCHXL_SPI0 +#define Board_SPI_MASTER_READY CC1310_LAUNCHXL_SPI_MASTER_READY +#define Board_SPI_SLAVE_READY CC1310_LAUNCHXL_SPI_SLAVE_READY + +#define Board_UART0 CC1310_LAUNCHXL_UART0 + +#define Board_WATCHDOG0 CC1310_LAUNCHXL_WATCHDOG0 + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H */ diff --git a/examples/knx-cc1310/CC1310_LAUNCHXL.c b/examples/knx-cc1310/CC1310_LAUNCHXL.c new file mode 100644 index 0000000..0486ee4 --- /dev/null +++ b/examples/knx-cc1310/CC1310_LAUNCHXL.c @@ -0,0 +1,962 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ====================== CC1310_LAUNCHXL.c =================================== + * This file is responsible for setting up the board specific items for the + * CC1310_LAUNCHXL board. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include "CC1310_LAUNCHXL.h" + +/* + * =============================== ADCBuf =============================== + */ +#include +#include + +ADCBufCC26XX_Object adcBufCC26xxObjects[CC1310_LAUNCHXL_ADCBUFCOUNT]; + +/* + * This table converts a virtual adc channel into a dio and internal analogue + * input signal. This table is necessary for the functioning of the adcBuf + * driver. Comment out unused entries to save flash. Dio and internal signal + * pairs are hardwired. Do not remap them in the table. You may reorder entire + * entries. The mapping of dio and internal signals is package dependent. + */ +const ADCBufCC26XX_AdcChannelLutEntry ADCBufCC26XX_adcChannelLut[CC1310_LAUNCHXL_ADCBUF0CHANNELCOUNT] = { + {CC1310_LAUNCHXL_DIO23_ANALOG, ADC_COMPB_IN_AUXIO7}, + {CC1310_LAUNCHXL_DIO24_ANALOG, ADC_COMPB_IN_AUXIO6}, + {CC1310_LAUNCHXL_DIO25_ANALOG, ADC_COMPB_IN_AUXIO5}, + {CC1310_LAUNCHXL_DIO26_ANALOG, ADC_COMPB_IN_AUXIO4}, + {CC1310_LAUNCHXL_DIO27_ANALOG, ADC_COMPB_IN_AUXIO3}, + {CC1310_LAUNCHXL_DIO28_ANALOG, ADC_COMPB_IN_AUXIO2}, + {CC1310_LAUNCHXL_DIO29_ANALOG, ADC_COMPB_IN_AUXIO1}, + {CC1310_LAUNCHXL_DIO30_ANALOG, ADC_COMPB_IN_AUXIO0}, + {PIN_UNASSIGNED, ADC_COMPB_IN_VDDS}, + {PIN_UNASSIGNED, ADC_COMPB_IN_DCOUPL}, + {PIN_UNASSIGNED, ADC_COMPB_IN_VSS}, +}; + +const ADCBufCC26XX_HWAttrs adcBufCC26xxHWAttrs[CC1310_LAUNCHXL_ADCBUFCOUNT] = { + { + .intPriority = ~0, + .swiPriority = 0, + .adcChannelLut = ADCBufCC26XX_adcChannelLut, + } +}; + +const ADCBuf_Config ADCBuf_config[CC1310_LAUNCHXL_ADCBUFCOUNT] = { + { + &ADCBufCC26XX_fxnTable, + &adcBufCC26xxObjects[CC1310_LAUNCHXL_ADCBUF0], + &adcBufCC26xxHWAttrs[CC1310_LAUNCHXL_ADCBUF0] + }, +}; + +const uint_least8_t ADCBuf_count = CC1310_LAUNCHXL_ADCBUFCOUNT; + +/* + * =============================== ADC =============================== + */ +#include +#include + +ADCCC26XX_Object adcCC26xxObjects[CC1310_LAUNCHXL_ADCCOUNT]; + + +const ADCCC26XX_HWAttrs adcCC26xxHWAttrs[CC1310_LAUNCHXL_ADCCOUNT] = { + { + .adcDIO = CC1310_LAUNCHXL_DIO23_ANALOG, + .adcCompBInput = ADC_COMPB_IN_AUXIO7, + .refSource = ADCCC26XX_FIXED_REFERENCE, + .samplingDuration = ADCCC26XX_SAMPLING_DURATION_2P7_US, + .inputScalingEnabled = true, + .triggerSource = ADCCC26XX_TRIGGER_MANUAL, + .returnAdjustedVal = false + }, + { + .adcDIO = CC1310_LAUNCHXL_DIO24_ANALOG, + .adcCompBInput = ADC_COMPB_IN_AUXIO6, + .refSource = ADCCC26XX_FIXED_REFERENCE, + .samplingDuration = ADCCC26XX_SAMPLING_DURATION_2P7_US, + .inputScalingEnabled = true, + .triggerSource = ADCCC26XX_TRIGGER_MANUAL, + .returnAdjustedVal = false + }, + { + .adcDIO = CC1310_LAUNCHXL_DIO25_ANALOG, + .adcCompBInput = ADC_COMPB_IN_AUXIO5, + .refSource = ADCCC26XX_FIXED_REFERENCE, + .samplingDuration = ADCCC26XX_SAMPLING_DURATION_2P7_US, + .inputScalingEnabled = true, + .triggerSource = ADCCC26XX_TRIGGER_MANUAL, + .returnAdjustedVal = false + }, + { + .adcDIO = CC1310_LAUNCHXL_DIO26_ANALOG, + .adcCompBInput = ADC_COMPB_IN_AUXIO4, + .refSource = ADCCC26XX_FIXED_REFERENCE, + .samplingDuration = ADCCC26XX_SAMPLING_DURATION_2P7_US, + .inputScalingEnabled = true, + .triggerSource = ADCCC26XX_TRIGGER_MANUAL, + .returnAdjustedVal = false + }, + { + .adcDIO = CC1310_LAUNCHXL_DIO27_ANALOG, + .adcCompBInput = ADC_COMPB_IN_AUXIO3, + .refSource = ADCCC26XX_FIXED_REFERENCE, + .samplingDuration = ADCCC26XX_SAMPLING_DURATION_2P7_US, + .inputScalingEnabled = true, + .triggerSource = ADCCC26XX_TRIGGER_MANUAL, + .returnAdjustedVal = false + }, + { + .adcDIO = CC1310_LAUNCHXL_DIO28_ANALOG, + .adcCompBInput = ADC_COMPB_IN_AUXIO2, + .refSource = ADCCC26XX_FIXED_REFERENCE, + .samplingDuration = ADCCC26XX_SAMPLING_DURATION_2P7_US, + .inputScalingEnabled = true, + .triggerSource = ADCCC26XX_TRIGGER_MANUAL, + .returnAdjustedVal = false + }, + { + .adcDIO = CC1310_LAUNCHXL_DIO29_ANALOG, + .adcCompBInput = ADC_COMPB_IN_AUXIO1, + .refSource = ADCCC26XX_FIXED_REFERENCE, + .samplingDuration = ADCCC26XX_SAMPLING_DURATION_2P7_US, + .inputScalingEnabled = true, + .triggerSource = ADCCC26XX_TRIGGER_MANUAL, + .returnAdjustedVal = false + }, + { + .adcDIO = CC1310_LAUNCHXL_DIO30_ANALOG, + .adcCompBInput = ADC_COMPB_IN_AUXIO0, + .refSource = ADCCC26XX_FIXED_REFERENCE, + .samplingDuration = ADCCC26XX_SAMPLING_DURATION_10P9_MS, + .inputScalingEnabled = true, + .triggerSource = ADCCC26XX_TRIGGER_MANUAL, + .returnAdjustedVal = false + }, + { + .adcDIO = PIN_UNASSIGNED, + .adcCompBInput = ADC_COMPB_IN_DCOUPL, + .refSource = ADCCC26XX_FIXED_REFERENCE, + .samplingDuration = ADCCC26XX_SAMPLING_DURATION_2P7_US, + .inputScalingEnabled = true, + .triggerSource = ADCCC26XX_TRIGGER_MANUAL, + .returnAdjustedVal = false + }, + { + .adcDIO = PIN_UNASSIGNED, + .adcCompBInput = ADC_COMPB_IN_VSS, + .refSource = ADCCC26XX_FIXED_REFERENCE, + .samplingDuration = ADCCC26XX_SAMPLING_DURATION_2P7_US, + .inputScalingEnabled = true, + .triggerSource = ADCCC26XX_TRIGGER_MANUAL, + .returnAdjustedVal = false + }, + { + .adcDIO = PIN_UNASSIGNED, + .adcCompBInput = ADC_COMPB_IN_VDDS, + .refSource = ADCCC26XX_FIXED_REFERENCE, + .samplingDuration = ADCCC26XX_SAMPLING_DURATION_2P7_US, + .inputScalingEnabled = true, + .triggerSource = ADCCC26XX_TRIGGER_MANUAL, + .returnAdjustedVal = false + } +}; + +const ADC_Config ADC_config[CC1310_LAUNCHXL_ADCCOUNT] = { + {&ADCCC26XX_fxnTable, &adcCC26xxObjects[CC1310_LAUNCHXL_ADC0], &adcCC26xxHWAttrs[CC1310_LAUNCHXL_ADC0]}, + {&ADCCC26XX_fxnTable, &adcCC26xxObjects[CC1310_LAUNCHXL_ADC1], &adcCC26xxHWAttrs[CC1310_LAUNCHXL_ADC1]}, + {&ADCCC26XX_fxnTable, &adcCC26xxObjects[CC1310_LAUNCHXL_ADC2], &adcCC26xxHWAttrs[CC1310_LAUNCHXL_ADC2]}, + {&ADCCC26XX_fxnTable, &adcCC26xxObjects[CC1310_LAUNCHXL_ADC3], &adcCC26xxHWAttrs[CC1310_LAUNCHXL_ADC3]}, + {&ADCCC26XX_fxnTable, &adcCC26xxObjects[CC1310_LAUNCHXL_ADC4], &adcCC26xxHWAttrs[CC1310_LAUNCHXL_ADC4]}, + {&ADCCC26XX_fxnTable, &adcCC26xxObjects[CC1310_LAUNCHXL_ADC5], &adcCC26xxHWAttrs[CC1310_LAUNCHXL_ADC5]}, + {&ADCCC26XX_fxnTable, &adcCC26xxObjects[CC1310_LAUNCHXL_ADC6], &adcCC26xxHWAttrs[CC1310_LAUNCHXL_ADC6]}, + {&ADCCC26XX_fxnTable, &adcCC26xxObjects[CC1310_LAUNCHXL_ADC7], &adcCC26xxHWAttrs[CC1310_LAUNCHXL_ADC7]}, + {&ADCCC26XX_fxnTable, &adcCC26xxObjects[CC1310_LAUNCHXL_ADCDCOUPL], &adcCC26xxHWAttrs[CC1310_LAUNCHXL_ADCDCOUPL]}, + {&ADCCC26XX_fxnTable, &adcCC26xxObjects[CC1310_LAUNCHXL_ADCVSS], &adcCC26xxHWAttrs[CC1310_LAUNCHXL_ADCVSS]}, + {&ADCCC26XX_fxnTable, &adcCC26xxObjects[CC1310_LAUNCHXL_ADCVDDS], &adcCC26xxHWAttrs[CC1310_LAUNCHXL_ADCVDDS]}, +}; + +const uint_least8_t ADC_count = CC1310_LAUNCHXL_ADCCOUNT; + +/* + * =============================== Crypto =============================== + */ +#include + +CryptoCC26XX_Object cryptoCC26XXObjects[CC1310_LAUNCHXL_CRYPTOCOUNT]; + +const CryptoCC26XX_HWAttrs cryptoCC26XXHWAttrs[CC1310_LAUNCHXL_CRYPTOCOUNT] = { + { + .baseAddr = CRYPTO_BASE, + .powerMngrId = PowerCC26XX_PERIPH_CRYPTO, + .intNum = INT_CRYPTO_RESULT_AVAIL_IRQ, + .intPriority = ~0, + } +}; + +const CryptoCC26XX_Config CryptoCC26XX_config[CC1310_LAUNCHXL_CRYPTOCOUNT] = { + { + .object = &cryptoCC26XXObjects[CC1310_LAUNCHXL_CRYPTO0], + .hwAttrs = &cryptoCC26XXHWAttrs[CC1310_LAUNCHXL_CRYPTO0] + } +}; + +/* + * =============================== AESCCM =============================== + */ +#include +#include + +AESCCMCC26XX_Object aesccmCC26XXObjects[CC1310_LAUNCHXL_AESCCMCOUNT]; + +const AESCCMCC26XX_HWAttrs aesccmCC26XXHWAttrs[CC1310_LAUNCHXL_AESCCMCOUNT] = { + { + .intPriority = ~0, + } +}; + +const AESCCM_Config AESCCM_config[CC1310_LAUNCHXL_AESCCMCOUNT] = { + { + .object = &aesccmCC26XXObjects[CC1310_LAUNCHXL_AESCCM0], + .hwAttrs = &aesccmCC26XXHWAttrs[CC1310_LAUNCHXL_AESCCM0] + }, +}; + +const uint_least8_t AESCCM_count = CC1310_LAUNCHXL_AESCCMCOUNT; + + +/* + * =============================== AESGCM =============================== + */ +#include +#include + +AESGCMCC26XX_Object aesgcmCC26XXObjects[CC1310_LAUNCHXL_AESGCMCOUNT]; + +const AESGCMCC26XX_HWAttrs aesgcmCC26XXHWAttrs[CC1310_LAUNCHXL_AESGCMCOUNT] = { + { + .intPriority = ~0, + } +}; + +const AESGCM_Config AESGCM_config[CC1310_LAUNCHXL_AESGCMCOUNT] = { + { + .object = &aesgcmCC26XXObjects[CC1310_LAUNCHXL_AESGCM0], + .hwAttrs = &aesgcmCC26XXHWAttrs[CC1310_LAUNCHXL_AESGCM0] + }, +}; + +const uint_least8_t AESGCM_count = CC1310_LAUNCHXL_AESGCMCOUNT; + +/* + * =============================== AESCBC =============================== + */ +#include +#include + +AESCBCCC26XX_Object aescbcCC26XXObjects[CC1310_LAUNCHXL_AESCBCCOUNT]; + +const AESCBCCC26XX_HWAttrs aescbcCC26XXHWAttrs[CC1310_LAUNCHXL_AESCBCCOUNT] = { + { + .intPriority = ~0, + } +}; + +const AESCBC_Config AESCBC_config[CC1310_LAUNCHXL_AESCBCCOUNT] = { + { + .object = &aescbcCC26XXObjects[CC1310_LAUNCHXL_AESCBC0], + .hwAttrs = &aescbcCC26XXHWAttrs[CC1310_LAUNCHXL_AESCBC0] + }, +}; + +const uint_least8_t AESCBC_count = CC1310_LAUNCHXL_AESCBCCOUNT; + +/* + * =============================== AESCTR =============================== + */ +#include +#include + +AESCTRCC26XX_Object aesctrCC26XXObjects[CC1310_LAUNCHXL_AESCTRCOUNT]; + +const AESCTRCC26XX_HWAttrs aesctrCC26XXHWAttrs[CC1310_LAUNCHXL_AESCTRCOUNT] = { + { + .intPriority = ~0, + } +}; + +const AESCTR_Config AESCTR_config[CC1310_LAUNCHXL_AESCTRCOUNT] = { + { + .object = &aesctrCC26XXObjects[CC1310_LAUNCHXL_AESCTR0], + .hwAttrs = &aesctrCC26XXHWAttrs[CC1310_LAUNCHXL_AESCTR0] + }, +}; + +const uint_least8_t AESCTR_count = CC1310_LAUNCHXL_AESCTRCOUNT; + +/* + * =============================== AESECB =============================== + */ +#include +#include + +AESECBCC26XX_Object aesecbCC26XXObjects[CC1310_LAUNCHXL_AESECBCOUNT]; + +const AESECBCC26XX_HWAttrs aesecbCC26XXHWAttrs[CC1310_LAUNCHXL_AESECBCOUNT] = { + { + .intPriority = ~0, + } +}; + +const AESECB_Config AESECB_config[CC1310_LAUNCHXL_AESECBCOUNT] = { + { + .object = &aesecbCC26XXObjects[CC1310_LAUNCHXL_AESECB0], + .hwAttrs = &aesecbCC26XXHWAttrs[CC1310_LAUNCHXL_AESECB0] + }, +}; + +const uint_least8_t AESECB_count = CC1310_LAUNCHXL_AESECBCOUNT; + +/* + * =============================== AESCTRDRBG =============================== + */ +#include +#include + +AESCTRDRBGXX_Object aesctrdrbgXXObjects[CC1310_LAUNCHXL_AESCTRDRBGCOUNT]; + +const AESCTRDRBGXX_HWAttrs aesctrdrbgXXHWAttrs[CC1310_LAUNCHXL_AESCTRDRBGCOUNT] = { + { + .aesctrIndex = CC1310_LAUNCHXL_AESCTR0, + } +}; + +const AESCTRDRBG_Config AESCTRDRBG_config[CC1310_LAUNCHXL_AESCTRDRBGCOUNT] = { + { + .object = &aesctrdrbgXXObjects[CC1310_LAUNCHXL_AESCTRDRBG0], + .hwAttrs = &aesctrdrbgXXHWAttrs[CC1310_LAUNCHXL_AESCTRDRBG0] + }, +}; + +const uint_least8_t AESCTRDRBG_count = CC1310_LAUNCHXL_AESCTRDRBGCOUNT; + +/* + * =============================== TRNG =============================== + */ +#include +#include + +TRNGCC26XX_Object trngCC26XXObjects[CC1310_LAUNCHXL_TRNGCOUNT]; + +const TRNGCC26XX_HWAttrs trngCC26X2HWAttrs[CC1310_LAUNCHXL_TRNGCOUNT] = { + { + .intPriority = ~0, + .swiPriority = 0, + .samplesPerCycle = 240000, + } +}; + +const TRNG_Config TRNG_config[CC1310_LAUNCHXL_TRNGCOUNT] = { + { + .object = &trngCC26XXObjects[CC1310_LAUNCHXL_TRNG0], + .hwAttrs = &trngCC26X2HWAttrs[CC1310_LAUNCHXL_TRNG0] + }, +}; + +const uint_least8_t TRNG_count = CC1310_LAUNCHXL_TRNGCOUNT; + +/* + * =============================== GPIO =============================== + */ +#include +#include + +/* + * Array of Pin configurations + * NOTE: The order of the pin configurations must coincide with what was + * defined in CC1310_LAUNCHXL.h + * NOTE: Pins not used for interrupts should be placed at the end of the + * array. Callback entries can be omitted from callbacks array to + * reduce memory usage. + */ +GPIO_PinConfig gpioPinConfigs[] = { + /* Input pins */ + GPIOCC26XX_DIO_13 | GPIO_DO_NOT_CONFIG, /* Button 0 */ + GPIOCC26XX_DIO_14 | GPIO_DO_NOT_CONFIG, /* Button 1 */ + + GPIOCC26XX_DIO_15 | GPIO_DO_NOT_CONFIG, /* CC1310_LAUNCHXL_SPI_MASTER_READY */ + GPIOCC26XX_DIO_21 | GPIO_DO_NOT_CONFIG, /* CC1310_LAUNCHXL_SPI_SLAVE_READY */ + + /* Output pins */ + GPIOCC26XX_DIO_07 | GPIO_DO_NOT_CONFIG, /* Green LED */ + GPIOCC26XX_DIO_06 | GPIO_DO_NOT_CONFIG, /* Red LED */ + GPIOCC26XX_DIO_30 | GPIO_DO_NOT_CONFIG, /* TMP116_EN */ + + /* SPI Flash CSN */ + GPIOCC26XX_DIO_20 | GPIO_DO_NOT_CONFIG, + + /* SD CS */ + GPIOCC26XX_DIO_21 | GPIO_DO_NOT_CONFIG, + + /* Sharp Display - GPIO configurations will be done in the Display files */ + GPIOCC26XX_DIO_24 | GPIO_DO_NOT_CONFIG, /* SPI chip select */ + GPIOCC26XX_DIO_22 | GPIO_DO_NOT_CONFIG, /* LCD power control */ + GPIOCC26XX_DIO_23 | GPIO_DO_NOT_CONFIG, /*LCD enable */ + +}; + +/* + * Array of callback function pointers + * NOTE: The order of the pin configurations must coincide with what was + * defined in CC1310_LAUNCH.h + * NOTE: Pins not used for interrupts can be omitted from callbacks array to + * reduce memory usage (if placed at end of gpioPinConfigs array). + */ +GPIO_CallbackFxn gpioCallbackFunctions[] = { + NULL, /* Button 0 */ + NULL, /* Button 1 */ + NULL, /* CC1310_LAUNCHXL_SPI_MASTER_READY */ + NULL, /* CC1310_LAUNCHXL_SPI_SLAVE_READY */ +}; + +const GPIOCC26XX_Config GPIOCC26XX_config = { + .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, + .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, + .numberOfPinConfigs = CC1310_LAUNCHXL_GPIOCOUNT, + .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), + .intPriority = (~0) +}; + +/* + * =============================== GPTimer =============================== + * Remove unused entries to reduce flash usage both in Board.c and Board.h + */ +#include + +GPTimerCC26XX_Object gptimerCC26XXObjects[CC1310_LAUNCHXL_GPTIMERCOUNT]; + +const GPTimerCC26XX_HWAttrs gptimerCC26xxHWAttrs[CC1310_LAUNCHXL_GPTIMERPARTSCOUNT] = { + { .baseAddr = GPT0_BASE, .intNum = INT_GPT0A, .intPriority = (~0), .powerMngrId = PowerCC26XX_PERIPH_GPT0, .pinMux = GPT_PIN_0A, }, + { .baseAddr = GPT0_BASE, .intNum = INT_GPT0B, .intPriority = (~0), .powerMngrId = PowerCC26XX_PERIPH_GPT0, .pinMux = GPT_PIN_0B, }, + { .baseAddr = GPT1_BASE, .intNum = INT_GPT1A, .intPriority = (~0), .powerMngrId = PowerCC26XX_PERIPH_GPT1, .pinMux = GPT_PIN_1A, }, + { .baseAddr = GPT1_BASE, .intNum = INT_GPT1B, .intPriority = (~0), .powerMngrId = PowerCC26XX_PERIPH_GPT1, .pinMux = GPT_PIN_1B, }, + { .baseAddr = GPT2_BASE, .intNum = INT_GPT2A, .intPriority = (~0), .powerMngrId = PowerCC26XX_PERIPH_GPT2, .pinMux = GPT_PIN_2A, }, + { .baseAddr = GPT2_BASE, .intNum = INT_GPT2B, .intPriority = (~0), .powerMngrId = PowerCC26XX_PERIPH_GPT2, .pinMux = GPT_PIN_2B, }, + { .baseAddr = GPT3_BASE, .intNum = INT_GPT3A, .intPriority = (~0), .powerMngrId = PowerCC26XX_PERIPH_GPT3, .pinMux = GPT_PIN_3A, }, + { .baseAddr = GPT3_BASE, .intNum = INT_GPT3B, .intPriority = (~0), .powerMngrId = PowerCC26XX_PERIPH_GPT3, .pinMux = GPT_PIN_3B, }, +}; + +const GPTimerCC26XX_Config GPTimerCC26XX_config[CC1310_LAUNCHXL_GPTIMERPARTSCOUNT] = { + { &gptimerCC26XXObjects[CC1310_LAUNCHXL_GPTIMER0], &gptimerCC26xxHWAttrs[CC1310_LAUNCHXL_GPTIMER0A], GPT_A }, + { &gptimerCC26XXObjects[CC1310_LAUNCHXL_GPTIMER0], &gptimerCC26xxHWAttrs[CC1310_LAUNCHXL_GPTIMER0B], GPT_B }, + { &gptimerCC26XXObjects[CC1310_LAUNCHXL_GPTIMER1], &gptimerCC26xxHWAttrs[CC1310_LAUNCHXL_GPTIMER1A], GPT_A }, + { &gptimerCC26XXObjects[CC1310_LAUNCHXL_GPTIMER1], &gptimerCC26xxHWAttrs[CC1310_LAUNCHXL_GPTIMER1B], GPT_B }, + { &gptimerCC26XXObjects[CC1310_LAUNCHXL_GPTIMER2], &gptimerCC26xxHWAttrs[CC1310_LAUNCHXL_GPTIMER2A], GPT_A }, + { &gptimerCC26XXObjects[CC1310_LAUNCHXL_GPTIMER2], &gptimerCC26xxHWAttrs[CC1310_LAUNCHXL_GPTIMER2B], GPT_B }, + { &gptimerCC26XXObjects[CC1310_LAUNCHXL_GPTIMER3], &gptimerCC26xxHWAttrs[CC1310_LAUNCHXL_GPTIMER3A], GPT_A }, + { &gptimerCC26XXObjects[CC1310_LAUNCHXL_GPTIMER3], &gptimerCC26xxHWAttrs[CC1310_LAUNCHXL_GPTIMER3B], GPT_B }, +}; + +/* + * =============================== I2C =============================== +*/ +#include +#include + +I2CCC26XX_Object i2cCC26xxObjects[CC1310_LAUNCHXL_I2CCOUNT]; + +const I2CCC26XX_HWAttrsV1 i2cCC26xxHWAttrs[CC1310_LAUNCHXL_I2CCOUNT] = { + { + .baseAddr = I2C0_BASE, + .powerMngrId = PowerCC26XX_PERIPH_I2C0, + .intNum = INT_I2C_IRQ, + .intPriority = ~0, + .swiPriority = 0, + .sdaPin = CC1310_LAUNCHXL_I2C0_SDA0, + .sclPin = CC1310_LAUNCHXL_I2C0_SCL0, + } +}; + +const I2C_Config I2C_config[CC1310_LAUNCHXL_I2CCOUNT] = { + { + .fxnTablePtr = &I2CCC26XX_fxnTable, + .object = &i2cCC26xxObjects[CC1310_LAUNCHXL_I2C0], + .hwAttrs = &i2cCC26xxHWAttrs[CC1310_LAUNCHXL_I2C0] + } +}; + +const uint_least8_t I2C_count = CC1310_LAUNCHXL_I2CCOUNT; + +/* + * =============================== I2S =============================== +*/ +#include +#include + +I2SCC26XX_Object i2sCC26XXObjects[CC1310_LAUNCHXL_I2SCOUNT]; + +const I2SCC26XX_HWAttrs i2sCC26XXHWAttrs[CC1310_LAUNCHXL_I2SCOUNT] = { + { + .pinSD1 = CC1310_LAUNCHXL_I2S_ADI, + .pinSD0 = CC1310_LAUNCHXL_I2S_ADO, + .pinSCK = CC1310_LAUNCHXL_I2S_BCLK, + .pinMCLK = CC1310_LAUNCHXL_I2S_MCLK, + .pinWS = CC1310_LAUNCHXL_I2S_WCLK, + .intPriority = ~0, + } +}; + +const I2S_Config I2S_config[CC1310_LAUNCHXL_I2SCOUNT] = { + { + .object = &i2sCC26XXObjects[CC1310_LAUNCHXL_I2S0], + .hwAttrs = &i2sCC26XXHWAttrs[CC1310_LAUNCHXL_I2S0] + }, +}; + +const uint_least8_t I2S_count = CC1310_LAUNCHXL_I2SCOUNT; + +/* + * =============================== NVS =============================== + */ +#include +#include +#include + +#define NVS_REGIONS_BASE 0x1A000 +#define SECTORSIZE 0x1000 +#define REGIONSIZE (SECTORSIZE * 1) + +#ifndef Board_EXCLUDE_NVS_INTERNAL_FLASH + +/* + * Reserve flash sectors for NVS driver use by placing an uninitialized byte + * array at the desired flash address. + */ +#if defined(__TI_COMPILER_VERSION__) + +/* + * Place uninitialized array at NVS_REGIONS_BASE + */ +#pragma LOCATION(flashBuf, NVS_REGIONS_BASE); +#pragma NOINIT(flashBuf); +static char flashBuf[REGIONSIZE]; + +#elif defined(__IAR_SYSTEMS_ICC__) + +/* + * Place uninitialized array at NVS_REGIONS_BASE + */ +static __no_init char flashBuf[REGIONSIZE] @ NVS_REGIONS_BASE; + +#elif defined(__GNUC__) + +/* + * Place the flash buffers in the .nvs section created in the gcc linker file. + * The .nvs section enforces alignment on a sector boundary but may + * be placed anywhere in flash memory. If desired the .nvs section can be set + * to a fixed address by changing the following in the gcc linker file: + * + * .nvs (FIXED_FLASH_ADDR) (NOLOAD) : AT (FIXED_FLASH_ADDR) { + * *(.nvs) + * } > REGION_TEXT + */ +__attribute__ ((section (".nvs"))) +static char flashBuf[REGIONSIZE]; + +#endif + +/* Allocate objects for NVS Internal Regions */ +NVSCC26XX_Object nvsCC26xxObjects[1]; + +/* Hardware attributes for NVS Internal Regions */ +const NVSCC26XX_HWAttrs nvsCC26xxHWAttrs[1] = { + { + .regionBase = (void *)flashBuf, + .regionSize = REGIONSIZE, + }, +}; + +#endif /* Board_EXCLUDE_NVS_INTERNAL_FLASH */ + +#ifndef Board_EXCLUDE_NVS_EXTERNAL_FLASH + +#define SPISECTORSIZE 0x1000 +#define SPIREGIONSIZE (SPISECTORSIZE * 32) +#define VERIFYBUFSIZE 64 + +static uint8_t verifyBuf[VERIFYBUFSIZE]; + +/* Allocate objects for NVS External Regions */ +NVSSPI25X_Object nvsSPI25XObjects[1]; + +/* Hardware attributes for NVS External Regions */ +const NVSSPI25X_HWAttrs nvsSPI25XHWAttrs[1] = { + { + .regionBaseOffset = 0, + .regionSize = SPIREGIONSIZE, + .sectorSize = SPISECTORSIZE, + .verifyBuf = verifyBuf, + .verifyBufSize = VERIFYBUFSIZE, + .spiHandle = NULL, + .spiIndex = 0, + .spiBitRate = 4000000, + .spiCsnGpioIndex = CC1310_LAUNCHXL_GPIO_SPI_FLASH_CS, + .statusPollDelayUs = 100, + }, +}; + +#endif /* Board_EXCLUDE_NVS_EXTERNAL_FLASH */ + +/* NVS Region index 0 and 1 refer to NVS and NVS SPI respectively */ +const NVS_Config NVS_config[CC1310_LAUNCHXL_NVSCOUNT] = { +#ifndef Board_EXCLUDE_NVS_INTERNAL_FLASH + { + .fxnTablePtr = &NVSCC26XX_fxnTable, + .object = &nvsCC26xxObjects[0], + .hwAttrs = &nvsCC26xxHWAttrs[0], + }, +#endif +#ifndef Board_EXCLUDE_NVS_EXTERNAL_FLASH + { + .fxnTablePtr = &NVSSPI25X_fxnTable, + .object = &nvsSPI25XObjects[0], + .hwAttrs = &nvsSPI25XHWAttrs[0], + }, +#endif +}; + +const uint_least8_t NVS_count = CC1310_LAUNCHXL_NVSCOUNT; + +/* + * =============================== PIN =============================== + */ +#include +#include + +const PIN_Config BoardGpioInitTable[] = { + + CC1310_LAUNCHXL_PIN_RLED | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_DRVSTR_MAX, /* LED initially off */ + CC1310_LAUNCHXL_PIN_GLED | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_DRVSTR_MAX, /* LED initially off */ + CC1310_LAUNCHXL_PIN_BTN1 | PIN_INPUT_EN | PIN_PULLUP | PIN_IRQ_BOTHEDGES | PIN_HYSTERESIS, /* Button is active low */ + CC1310_LAUNCHXL_PIN_BTN2 | PIN_INPUT_EN | PIN_PULLUP | PIN_IRQ_BOTHEDGES | PIN_HYSTERESIS, /* Button is active low */ + CC1310_LAUNCHXL_SPI_FLASH_CS | PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH | PIN_PUSHPULL | PIN_DRVSTR_MIN, /* External flash chip select */ + CC1310_LAUNCHXL_UART_RX | PIN_INPUT_EN | PIN_PULLDOWN, /* UART RX via debugger back channel */ + CC1310_LAUNCHXL_UART_TX | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, /* UART TX via debugger back channel */ + CC1310_LAUNCHXL_SPI0_MOSI | PIN_INPUT_EN | PIN_PULLDOWN, /* SPI master out - slave in */ + CC1310_LAUNCHXL_SPI0_MISO | PIN_INPUT_EN | PIN_PULLDOWN, /* SPI master in - slave out */ + CC1310_LAUNCHXL_SPI0_CLK | PIN_INPUT_EN | PIN_PULLDOWN, /* SPI clock */ + + PIN_TERMINATE +}; + +const PINCC26XX_HWAttrs PINCC26XX_hwAttrs = { + .intPriority = ~0, + .swiPriority = 0 +}; + +/* + * =============================== Power =============================== + */ +#include +#include + +const PowerCC26XX_Config PowerCC26XX_config = { + .policyInitFxn = NULL, + .policyFxn = &PowerCC26XX_standbyPolicy, + .calibrateFxn = &PowerCC26XX_calibrate, + .enablePolicy = true, + .calibrateRCOSC_LF = true, + .calibrateRCOSC_HF = true, +}; + +/* + * =============================== PWM =============================== + * Remove unused entries to reduce flash usage both in Board.c and Board.h + */ +#include +#include + +PWMTimerCC26XX_Object pwmtimerCC26xxObjects[CC1310_LAUNCHXL_PWMCOUNT]; + +const PWMTimerCC26XX_HwAttrs pwmtimerCC26xxHWAttrs[CC1310_LAUNCHXL_PWMCOUNT] = { + { .pwmPin = CC1310_LAUNCHXL_PWMPIN0, .gpTimerUnit = CC1310_LAUNCHXL_GPTIMER0A }, + { .pwmPin = CC1310_LAUNCHXL_PWMPIN1, .gpTimerUnit = CC1310_LAUNCHXL_GPTIMER0B }, + { .pwmPin = CC1310_LAUNCHXL_PWMPIN2, .gpTimerUnit = CC1310_LAUNCHXL_GPTIMER1A }, + { .pwmPin = CC1310_LAUNCHXL_PWMPIN3, .gpTimerUnit = CC1310_LAUNCHXL_GPTIMER1B }, + { .pwmPin = CC1310_LAUNCHXL_PWMPIN4, .gpTimerUnit = CC1310_LAUNCHXL_GPTIMER2A }, + { .pwmPin = CC1310_LAUNCHXL_PWMPIN5, .gpTimerUnit = CC1310_LAUNCHXL_GPTIMER2B }, + { .pwmPin = CC1310_LAUNCHXL_PWMPIN6, .gpTimerUnit = CC1310_LAUNCHXL_GPTIMER3A }, + { .pwmPin = CC1310_LAUNCHXL_PWMPIN7, .gpTimerUnit = CC1310_LAUNCHXL_GPTIMER3B }, +}; + +const PWM_Config PWM_config[CC1310_LAUNCHXL_PWMCOUNT] = { + { &PWMTimerCC26XX_fxnTable, &pwmtimerCC26xxObjects[CC1310_LAUNCHXL_PWM0], &pwmtimerCC26xxHWAttrs[CC1310_LAUNCHXL_PWM0] }, + { &PWMTimerCC26XX_fxnTable, &pwmtimerCC26xxObjects[CC1310_LAUNCHXL_PWM1], &pwmtimerCC26xxHWAttrs[CC1310_LAUNCHXL_PWM1] }, + { &PWMTimerCC26XX_fxnTable, &pwmtimerCC26xxObjects[CC1310_LAUNCHXL_PWM2], &pwmtimerCC26xxHWAttrs[CC1310_LAUNCHXL_PWM2] }, + { &PWMTimerCC26XX_fxnTable, &pwmtimerCC26xxObjects[CC1310_LAUNCHXL_PWM3], &pwmtimerCC26xxHWAttrs[CC1310_LAUNCHXL_PWM3] }, + { &PWMTimerCC26XX_fxnTable, &pwmtimerCC26xxObjects[CC1310_LAUNCHXL_PWM4], &pwmtimerCC26xxHWAttrs[CC1310_LAUNCHXL_PWM4] }, + { &PWMTimerCC26XX_fxnTable, &pwmtimerCC26xxObjects[CC1310_LAUNCHXL_PWM5], &pwmtimerCC26xxHWAttrs[CC1310_LAUNCHXL_PWM5] }, + { &PWMTimerCC26XX_fxnTable, &pwmtimerCC26xxObjects[CC1310_LAUNCHXL_PWM6], &pwmtimerCC26xxHWAttrs[CC1310_LAUNCHXL_PWM6] }, + { &PWMTimerCC26XX_fxnTable, &pwmtimerCC26xxObjects[CC1310_LAUNCHXL_PWM7], &pwmtimerCC26xxHWAttrs[CC1310_LAUNCHXL_PWM7] }, +}; + +const uint_least8_t PWM_count = CC1310_LAUNCHXL_PWMCOUNT; + +/* + * =============================== RF Driver =============================== + */ +#include + +const RFCC26XX_HWAttrsV2 RFCC26XX_hwAttrs = { + .hwiPriority = ~0, /* Lowest HWI priority */ + .swiPriority = 0, /* Lowest SWI priority */ + .xoscHfAlwaysNeeded = true, /* Keep XOSC dependency while in standby */ + .globalCallback = NULL, /* No board specific callback */ + .globalEventMask = 0 /* No events subscribed to */ +}; + +/* + * =============================== SD =============================== + */ +#include +#include + +SDSPI_Object sdspiObjects[CC1310_LAUNCHXL_SDCOUNT]; + +const SDSPI_HWAttrs sdspiHWAttrs[CC1310_LAUNCHXL_SDCOUNT] = { + { + .spiIndex = CC1310_LAUNCHXL_SPI0, + .spiCsGpioIndex = CC1310_LAUNCHXL_SDSPI_CS + } +}; + +const SD_Config SD_config[CC1310_LAUNCHXL_SDCOUNT] = { + { + .fxnTablePtr = &SDSPI_fxnTable, + .object = &sdspiObjects[CC1310_LAUNCHXL_SDSPI0], + .hwAttrs = &sdspiHWAttrs[CC1310_LAUNCHXL_SDSPI0] + }, +}; + +const uint_least8_t SD_count = CC1310_LAUNCHXL_SDCOUNT; + +/* + * =============================== SPI DMA =============================== + */ +#include +#include + +SPICC26XXDMA_Object spiCC26XXDMAObjects[CC1310_LAUNCHXL_SPICOUNT]; + +/* + * NOTE: The SPI instances below can be used by the SD driver to communicate + * with a SD card via SPI. The 'defaultTxBufValue' fields below are set to 0xFF + * to satisfy the SDSPI driver requirement. + */ +const SPICC26XXDMA_HWAttrsV1 spiCC26XXDMAHWAttrs[CC1310_LAUNCHXL_SPICOUNT] = { + { + .baseAddr = SSI0_BASE, + .intNum = INT_SSI0_COMB, + .intPriority = ~0, + .swiPriority = 0, + .powerMngrId = PowerCC26XX_PERIPH_SSI0, + .defaultTxBufValue = 0xFF, + .rxChannelBitMask = 1< +#include + +UARTCC26XX_Object uartCC26XXObjects[CC1310_LAUNCHXL_UARTCOUNT]; + +uint8_t uartCC26XXRingBuffer[CC1310_LAUNCHXL_UARTCOUNT][32]; + +const UARTCC26XX_HWAttrsV2 uartCC26XXHWAttrs[CC1310_LAUNCHXL_UARTCOUNT] = { + { + .baseAddr = UART0_BASE, + .powerMngrId = PowerCC26XX_PERIPH_UART0, + .intNum = INT_UART0_COMB, + .intPriority = ~0, + .swiPriority = 0, + .txPin = CC1310_LAUNCHXL_UART_TX, + .rxPin = CC1310_LAUNCHXL_UART_RX, + .ctsPin = PIN_UNASSIGNED, + .rtsPin = PIN_UNASSIGNED, + .ringBufPtr = uartCC26XXRingBuffer[CC1310_LAUNCHXL_UART0], + .ringBufSize = sizeof(uartCC26XXRingBuffer[CC1310_LAUNCHXL_UART0]), + .txIntFifoThr = UARTCC26XX_FIFO_THRESHOLD_1_8, + .rxIntFifoThr = UARTCC26XX_FIFO_THRESHOLD_4_8, + .errorFxn = NULL + } +}; + +const UART_Config UART_config[CC1310_LAUNCHXL_UARTCOUNT] = { + { + .fxnTablePtr = &UARTCC26XX_fxnTable, + .object = &uartCC26XXObjects[CC1310_LAUNCHXL_UART0], + .hwAttrs = &uartCC26XXHWAttrs[CC1310_LAUNCHXL_UART0] + }, +}; + +const uint_least8_t UART_count = CC1310_LAUNCHXL_UARTCOUNT; + +/* + * =============================== UDMA =============================== + */ +#include + +UDMACC26XX_Object udmaObjects[CC1310_LAUNCHXL_UDMACOUNT]; + +const UDMACC26XX_HWAttrs udmaHWAttrs[CC1310_LAUNCHXL_UDMACOUNT] = { + { + .baseAddr = UDMA0_BASE, + .powerMngrId = PowerCC26XX_PERIPH_UDMA, + .intNum = INT_DMA_ERR, + .intPriority = ~0 + } +}; + +const UDMACC26XX_Config UDMACC26XX_config[CC1310_LAUNCHXL_UDMACOUNT] = { + { + .object = &udmaObjects[CC1310_LAUNCHXL_UDMA0], + .hwAttrs = &udmaHWAttrs[CC1310_LAUNCHXL_UDMA0] + }, +}; + +/* + * =============================== Watchdog =============================== + */ +#include +#include + +WatchdogCC26XX_Object watchdogCC26XXObjects[CC1310_LAUNCHXL_WATCHDOGCOUNT]; + +const WatchdogCC26XX_HWAttrs watchdogCC26XXHWAttrs[CC1310_LAUNCHXL_WATCHDOGCOUNT] = { + { + .baseAddr = WDT_BASE, + .reloadValue = 1000 /* Reload value in milliseconds */ + }, +}; + +const Watchdog_Config Watchdog_config[CC1310_LAUNCHXL_WATCHDOGCOUNT] = { + { + .fxnTablePtr = &WatchdogCC26XX_fxnTable, + .object = &watchdogCC26XXObjects[CC1310_LAUNCHXL_WATCHDOG0], + .hwAttrs = &watchdogCC26XXHWAttrs[CC1310_LAUNCHXL_WATCHDOG0] + }, +}; + +const uint_least8_t Watchdog_count = CC1310_LAUNCHXL_WATCHDOGCOUNT; + +/* + * Board-specific initialization function to disable external flash. + * This function is defined in the file CC1310_LAUNCHXL_fxns.c + */ +extern void Board_initHook(void); + +/* + * ======== CC1310_LAUNCHXL_initGeneral ======== + */ +void CC1310_LAUNCHXL_initGeneral(void) +{ + Power_init(); + + if (PIN_init(BoardGpioInitTable) != PIN_SUCCESS) { + /* Error with PIN_init */ + while (1); + } + + /* Perform board-specific initialization */ + Board_initHook(); +} + +/* + * ======== Board_init ======== + */ +void Board_init(void) +{ + CC1310_LAUNCHXL_initGeneral(); +} diff --git a/examples/knx-cc1310/CC1310_LAUNCHXL.h b/examples/knx-cc1310/CC1310_LAUNCHXL.h new file mode 100644 index 0000000..737e448 --- /dev/null +++ b/examples/knx-cc1310/CC1310_LAUNCHXL.h @@ -0,0 +1,451 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CC1310_LAUNCHXL.h + * + * @brief CC1310 LaunchPad Board Specific header file. + * + * The CC1310_LAUNCHXL header file should be included in an application as + * follows: + * @code + * #include "CC1310_LAUNCHXL.h" + * @endcode + * + * ============================================================================ + */ +#ifndef __CC1310_LAUNCHXL_BOARD_H__ +#define __CC1310_LAUNCHXL_BOARD_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include +#include + +/* Externs */ +extern const PIN_Config BoardGpioInitTable[]; + +/* Defines */ +#define CC1310_LAUNCHXL + +/* Mapping of pins to board signals using general board aliases + * + */ + +/* Analog capable DIOs */ +#define CC1310_LAUNCHXL_DIO23_ANALOG IOID_23 +#define CC1310_LAUNCHXL_DIO24_ANALOG IOID_24 +#define CC1310_LAUNCHXL_DIO25_ANALOG IOID_25 +#define CC1310_LAUNCHXL_DIO26_ANALOG IOID_26 +#define CC1310_LAUNCHXL_DIO27_ANALOG IOID_27 +#define CC1310_LAUNCHXL_DIO28_ANALOG IOID_28 +#define CC1310_LAUNCHXL_DIO29_ANALOG IOID_29 +#define CC1310_LAUNCHXL_DIO30_ANALOG IOID_30 + +/* Digital IOs */ +#define CC1310_LAUNCHXL_DIO0 IOID_0 +#define CC1310_LAUNCHXL_DIO1 IOID_1 +#define CC1310_LAUNCHXL_DIO12 IOID_12 +#define CC1310_LAUNCHXL_DIO15 IOID_15 +#define CC1310_LAUNCHXL_DIO16_TDO IOID_16 +#define CC1310_LAUNCHXL_DIO17_TDI IOID_17 +#define CC1310_LAUNCHXL_DIO21 IOID_21 +#define CC1310_LAUNCHXL_DIO22 IOID_22 + +/* Discrete Inputs */ +#define CC1310_LAUNCHXL_PIN_BTN1 IOID_13 +#define CC1310_LAUNCHXL_PIN_BTN2 IOID_14 + +/* GPIO */ +#define CC1310_LAUNCHXL_GPIO_LED_ON 1 +#define CC1310_LAUNCHXL_GPIO_LED_OFF 0 + +/* I2C */ +#define CC1310_LAUNCHXL_I2C0_SCL0 IOID_4 +#define CC1310_LAUNCHXL_I2C0_SDA0 IOID_5 + +/* I2S */ +#define CC1310_LAUNCHXL_I2S_ADO IOID_25 +#define CC1310_LAUNCHXL_I2S_ADI IOID_26 +#define CC1310_LAUNCHXL_I2S_BCLK IOID_27 +#define CC1310_LAUNCHXL_I2S_MCLK PIN_UNASSIGNED +#define CC1310_LAUNCHXL_I2S_WCLK IOID_28 + +/* LEDs */ +#define CC1310_LAUNCHXL_PIN_LED_ON 1 +#define CC1310_LAUNCHXL_PIN_LED_OFF 0 +#define CC1310_LAUNCHXL_PIN_RLED IOID_6 +#define CC1310_LAUNCHXL_PIN_GLED IOID_7 + +/* PWM Outputs */ +#define CC1310_LAUNCHXL_PWMPIN0 CC1310_LAUNCHXL_PIN_RLED +#define CC1310_LAUNCHXL_PWMPIN1 CC1310_LAUNCHXL_PIN_GLED +#define CC1310_LAUNCHXL_PWMPIN2 PIN_UNASSIGNED +#define CC1310_LAUNCHXL_PWMPIN3 PIN_UNASSIGNED +#define CC1310_LAUNCHXL_PWMPIN4 PIN_UNASSIGNED +#define CC1310_LAUNCHXL_PWMPIN5 PIN_UNASSIGNED +#define CC1310_LAUNCHXL_PWMPIN6 PIN_UNASSIGNED +#define CC1310_LAUNCHXL_PWMPIN7 PIN_UNASSIGNED + +/* SPI */ +#define CC1310_LAUNCHXL_SPI_FLASH_CS IOID_20 +#define CC1310_LAUNCHXL_FLASH_CS_ON 0 +#define CC1310_LAUNCHXL_FLASH_CS_OFF 1 + +/* SPI Board */ +#define CC1310_LAUNCHXL_SPI0_MISO IOID_8 /* RF1.20 */ +#define CC1310_LAUNCHXL_SPI0_MOSI IOID_9 /* RF1.18 */ +#define CC1310_LAUNCHXL_SPI0_CLK IOID_10 /* RF1.16 */ +#define CC1310_LAUNCHXL_SPI0_CSN IOID_11 +#define CC1310_LAUNCHXL_SPI1_MISO PIN_UNASSIGNED +#define CC1310_LAUNCHXL_SPI1_MOSI PIN_UNASSIGNED +#define CC1310_LAUNCHXL_SPI1_CLK PIN_UNASSIGNED +#define CC1310_LAUNCHXL_SPI1_CSN PIN_UNASSIGNED + +/* UART Board */ +#define CC1310_LAUNCHXL_UART_RX IOID_2 /* RXD */ +#define CC1310_LAUNCHXL_UART_TX IOID_3 /* TXD */ +#define CC1310_LAUNCHXL_UART_CTS IOID_19 /* CTS */ +#define CC1310_LAUNCHXL_UART_RTS IOID_18 /* RTS */ + +/*! + * @brief Initialize the general board specific settings + * + * This function initializes the general board specific settings. + */ +void CC1310_LAUNCHXL_initGeneral(void); + +/*! + * @brief Turn off the external flash on LaunchPads + * + */ +void CC1310_LAUNCHXL_shutDownExtFlash(void); + +/*! + * @brief Wake up the external flash present on the board files + * + * This function toggles the chip select for the amount of time needed + * to wake the chip up. + */ +void CC1310_LAUNCHXL_wakeUpExtFlash(void); + +/*! + * @def CC1310_LAUNCHXL_ADCBufName + * @brief Enum of ADCBufs + */ +typedef enum CC1310_LAUNCHXL_ADCBufName { + CC1310_LAUNCHXL_ADCBUF0 = 0, + + CC1310_LAUNCHXL_ADCBUFCOUNT +} CC1310_LAUNCHXL_ADCBufName; + +/*! + * @def CC1310_LAUNCHXL_ADCBuf0SourceName + * @brief Enum of ADCBuf channels + */ +typedef enum CC1310_LAUNCHXL_ADCBuf0ChannelName { + CC1310_LAUNCHXL_ADCBUF0CHANNEL0 = 0, + CC1310_LAUNCHXL_ADCBUF0CHANNEL1, + CC1310_LAUNCHXL_ADCBUF0CHANNEL2, + CC1310_LAUNCHXL_ADCBUF0CHANNEL3, + CC1310_LAUNCHXL_ADCBUF0CHANNEL4, + CC1310_LAUNCHXL_ADCBUF0CHANNEL5, + CC1310_LAUNCHXL_ADCBUF0CHANNEL6, + CC1310_LAUNCHXL_ADCBUF0CHANNEL7, + CC1310_LAUNCHXL_ADCBUF0CHANNELVDDS, + CC1310_LAUNCHXL_ADCBUF0CHANNELDCOUPL, + CC1310_LAUNCHXL_ADCBUF0CHANNELVSS, + + CC1310_LAUNCHXL_ADCBUF0CHANNELCOUNT +} CC1310_LAUNCHXL_ADCBuf0ChannelName; + +/*! + * @def CC1310_LAUNCHXL_ADCName + * @brief Enum of ADCs + */ +typedef enum CC1310_LAUNCHXL_ADCName { + CC1310_LAUNCHXL_ADC0 = 0, + CC1310_LAUNCHXL_ADC1, + CC1310_LAUNCHXL_ADC2, + CC1310_LAUNCHXL_ADC3, + CC1310_LAUNCHXL_ADC4, + CC1310_LAUNCHXL_ADC5, + CC1310_LAUNCHXL_ADC6, + CC1310_LAUNCHXL_ADC7, + CC1310_LAUNCHXL_ADCDCOUPL, + CC1310_LAUNCHXL_ADCVSS, + CC1310_LAUNCHXL_ADCVDDS, + + CC1310_LAUNCHXL_ADCCOUNT +} CC1310_LAUNCHXL_ADCName; + +/*! + * @def CC1310_LAUNCHXL_CryptoName + * @brief Enum of Crypto names + */ +typedef enum CC1310_LAUNCHXL_CryptoName { + CC1310_LAUNCHXL_CRYPTO0 = 0, + + CC1310_LAUNCHXL_CRYPTOCOUNT +} CC1310_LAUNCHXL_CryptoName; + +/*! + * @def CC1310_LAUNCHXL_AESCCMName + * @brief Enum of AESCCM names + */ +typedef enum CC1310_LAUNCHXL_AESCCMName { + CC1310_LAUNCHXL_AESCCM0 = 0, + + CC1310_LAUNCHXL_AESCCMCOUNT +} CC1310_LAUNCHXL_AESCCMName; + +/*! + * @def CC1310_LAUNCHXL_AESGCMName + * @brief Enum of AESGCM names + */ +typedef enum CC1310_LAUNCHXL_AESGCMName { + CC1310_LAUNCHXL_AESGCM0 = 0, + + CC1310_LAUNCHXL_AESGCMCOUNT +} CC1310_LAUNCHXL_AESGCMName; + +/*! + * @def CC1310_LAUNCHXL_AESCBCName + * @brief Enum of AESCBC names + */ +typedef enum CC1310_LAUNCHXL_AESCBCName { + CC1310_LAUNCHXL_AESCBC0 = 0, + + CC1310_LAUNCHXL_AESCBCCOUNT +} CC1310_LAUNCHXL_AESCBCName; + +/*! + * @def CC1310_LAUNCHXL_AESCTRName + * @brief Enum of AESCTR names + */ +typedef enum CC1310_LAUNCHXL_AESCTRName { + CC1310_LAUNCHXL_AESCTR0 = 0, + + CC1310_LAUNCHXL_AESCTRCOUNT +} CC1310_LAUNCHXL_AESCTRName; + +/*! + * @def CC1310_LAUNCHXL_AESECBName + * @brief Enum of AESECB names + */ +typedef enum CC1310_LAUNCHXL_AESECBName { + CC1310_LAUNCHXL_AESECB0 = 0, + + CC1310_LAUNCHXL_AESECBCOUNT +} CC1310_LAUNCHXL_AESECBName; + +/*! + * @def CC1310_LAUNCHXL_AESCTRDRBGName + * @brief Enum of AESCTRDRBG names + */ +typedef enum CC1310_LAUNCHXL_AESCTRDRBGName { + CC1310_LAUNCHXL_AESCTRDRBG0 = 0, + + CC1310_LAUNCHXL_AESCTRDRBGCOUNT +} CC1310_LAUNCHXL_AESCTRDRBGName; + +/*! + * @def CC1310_LAUNCHXL_TRNGName + * @brief Enum of TRNG names + */ +typedef enum CC1310_LAUNCHXL_TRNGName { + CC1310_LAUNCHXL_TRNG0 = 0, + + CC1310_LAUNCHXL_TRNGCOUNT +} CC1310_LAUNCHXL_TRNGName; + +/*! + * @def CC1310_LAUNCHXL_GPIOName + * @brief Enum of GPIO names + */ +typedef enum CC1310_LAUNCHXL_GPIOName { + CC1310_LAUNCHXL_GPIO_S1 = 0, + CC1310_LAUNCHXL_GPIO_S2, + CC1310_LAUNCHXL_SPI_MASTER_READY, + CC1310_LAUNCHXL_SPI_SLAVE_READY, + CC1310_LAUNCHXL_GPIO_LED_GREEN, + CC1310_LAUNCHXL_GPIO_LED_RED, + CC1310_LAUNCHXL_GPIO_TMP116_EN, + CC1310_LAUNCHXL_GPIO_SPI_FLASH_CS, + CC1310_LAUNCHXL_SDSPI_CS, + CC1310_LAUNCHXL_GPIO_LCD_CS, + CC1310_LAUNCHXL_GPIO_LCD_POWER, + CC1310_LAUNCHXL_GPIO_LCD_ENABLE, + CC1310_LAUNCHXL_GPIOCOUNT +} CC1310_LAUNCHXL_GPIOName; + +/*! + * @def CC1310_LAUNCHXL_GPTimerName + * @brief Enum of GPTimer parts + */ +typedef enum CC1310_LAUNCHXL_GPTimerName { + CC1310_LAUNCHXL_GPTIMER0A = 0, + CC1310_LAUNCHXL_GPTIMER0B, + CC1310_LAUNCHXL_GPTIMER1A, + CC1310_LAUNCHXL_GPTIMER1B, + CC1310_LAUNCHXL_GPTIMER2A, + CC1310_LAUNCHXL_GPTIMER2B, + CC1310_LAUNCHXL_GPTIMER3A, + CC1310_LAUNCHXL_GPTIMER3B, + + CC1310_LAUNCHXL_GPTIMERPARTSCOUNT +} CC1310_LAUNCHXL_GPTimerName; + +/*! + * @def CC1310_LAUNCHXL_GPTimers + * @brief Enum of GPTimers + */ +typedef enum CC1310_LAUNCHXL_GPTimers { + CC1310_LAUNCHXL_GPTIMER0 = 0, + CC1310_LAUNCHXL_GPTIMER1, + CC1310_LAUNCHXL_GPTIMER2, + CC1310_LAUNCHXL_GPTIMER3, + + CC1310_LAUNCHXL_GPTIMERCOUNT +} CC1310_LAUNCHXL_GPTimers; + +/*! + * @def CC1310_LAUNCHXL_I2CName + * @brief Enum of I2C names + */ +typedef enum CC1310_LAUNCHXL_I2CName { + CC1310_LAUNCHXL_I2C0 = 0, + + CC1310_LAUNCHXL_I2CCOUNT +} CC1310_LAUNCHXL_I2CName; + +/*! + * @def CC1310_LAUNCHXL_I2SName + * @brief Enum of I2S names + */ +typedef enum CC1310_LAUNCHXL_I2SName { + CC1310_LAUNCHXL_I2S0 = 0, + + CC1310_LAUNCHXL_I2SCOUNT +} CC1310_LAUNCHXL_I2SName; + +/*! + * @def CC1310_LAUNCHXL_NVSName + * @brief Enum of NVS names + */ +typedef enum CC1310_LAUNCHXL_NVSName { +#ifndef Board_EXCLUDE_NVS_INTERNAL_FLASH + CC1310_LAUNCHXL_NVSCC26XX0 = 0, +#endif +#ifndef Board_EXCLUDE_NVS_EXTERNAL_FLASH + CC1310_LAUNCHXL_NVSSPI25X0, +#endif + + CC1310_LAUNCHXL_NVSCOUNT +} CC1310_LAUNCHXL_NVSName; + +/*! + * @def CC1310_LAUNCHXL_PWM + * @brief Enum of PWM outputs + */ +typedef enum CC1310_LAUNCHXL_PWMName { + CC1310_LAUNCHXL_PWM0 = 0, + CC1310_LAUNCHXL_PWM1, + CC1310_LAUNCHXL_PWM2, + CC1310_LAUNCHXL_PWM3, + CC1310_LAUNCHXL_PWM4, + CC1310_LAUNCHXL_PWM5, + CC1310_LAUNCHXL_PWM6, + CC1310_LAUNCHXL_PWM7, + + CC1310_LAUNCHXL_PWMCOUNT +} CC1310_LAUNCHXL_PWMName; + +/*! + * @def CC1310_LAUNCHXL_SDName + * @brief Enum of SD names + */ +typedef enum CC1310_LAUNCHXL_SDName { + CC1310_LAUNCHXL_SDSPI0 = 0, + + CC1310_LAUNCHXL_SDCOUNT +} CC1310_LAUNCHXL_SDName; + +/*! + * @def CC1310_LAUNCHXL_SPIName + * @brief Enum of SPI names + */ +typedef enum CC1310_LAUNCHXL_SPIName { + CC1310_LAUNCHXL_SPI0 = 0, + CC1310_LAUNCHXL_SPI1, + + CC1310_LAUNCHXL_SPICOUNT +} CC1310_LAUNCHXL_SPIName; + +/*! + * @def CC1310_LAUNCHXL_UARTName + * @brief Enum of UARTs + */ +typedef enum CC1310_LAUNCHXL_UARTName { + CC1310_LAUNCHXL_UART0 = 0, + + CC1310_LAUNCHXL_UARTCOUNT +} CC1310_LAUNCHXL_UARTName; + +/*! + * @def CC1310_LAUNCHXL_UDMAName + * @brief Enum of DMA buffers + */ +typedef enum CC1310_LAUNCHXL_UDMAName { + CC1310_LAUNCHXL_UDMA0 = 0, + + CC1310_LAUNCHXL_UDMACOUNT +} CC1310_LAUNCHXL_UDMAName; + +/*! + * @def CC1310_LAUNCHXL_WatchdogName + * @brief Enum of Watchdogs + */ +typedef enum CC1310_LAUNCHXL_WatchdogName { + CC1310_LAUNCHXL_WATCHDOG0 = 0, + + CC1310_LAUNCHXL_WATCHDOGCOUNT +} CC1310_LAUNCHXL_WatchdogName; + + +#ifdef __cplusplus +} +#endif + +#endif /* __CC1310_LAUNCHXL_BOARD_H__ */ diff --git a/examples/knx-cc1310/CC1310_LAUNCHXL_NoRTOS.lds b/examples/knx-cc1310/CC1310_LAUNCHXL_NoRTOS.lds new file mode 100644 index 0000000..f06e608 --- /dev/null +++ b/examples/knx-cc1310/CC1310_LAUNCHXL_NoRTOS.lds @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== CC1310_LAUNCHXL_NoRTOS.lds ======== + * Default Linker script for the Texas Instruments CC1310 + */ + +STACKSIZE = 4096+1024; +HEAPSIZE = 4096; + +MEMORY +{ + FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x0001ffa8 + /* + * Customer Configuration Area and Bootloader Backdoor configuration in + * flash, 40 bytes + */ + FLASH_CCFG (RX) : ORIGIN = 0x0001ffa8, LENGTH = 0x00000058 + SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00005000 +} + +REGION_ALIAS("REGION_TEXT", FLASH); +REGION_ALIAS("REGION_BSS", SRAM); +REGION_ALIAS("REGION_DATA", SRAM); +REGION_ALIAS("REGION_STACK", SRAM); +REGION_ALIAS("REGION_HEAP", SRAM); +REGION_ALIAS("REGION_ARM_EXIDX", FLASH); +REGION_ALIAS("REGION_ARM_EXTAB", FLASH); + +SECTIONS { + + PROVIDE (_resetVecs_base_address = + DEFINED(_resetVecs_base_address) ? _resetVecs_base_address : 0x0); + + .resetVecs (_resetVecs_base_address) : AT (_resetVecs_base_address) { + KEEP (*(.resetVecs)) + } > REGION_TEXT + + .ramVecs (NOLOAD) : ALIGN(1024){ + KEEP (*(.ramVecs)) + } > REGION_DATA + + /* + * UDMACC26XX_CONFIG_BASE below must match UDMACC26XX_CONFIG_BASE defined + * by ti/drivers/dma/UDMACC26XX.h + * The user is allowed to change UDMACC26XX_CONFIG_BASE to move it away from + * the default address 0x2000_0400, but remember it must be 1024 bytes aligned. + */ + UDMACC26XX_CONFIG_BASE = 0x20000400; + + /* + * Define absolute addresses for the DMA channels. + * DMA channels must always be allocated at a fixed offset from the DMA base address. + * --------- DO NOT MODIFY ----------- + */ + DMA_SPI0_RX_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x30); + DMA_SPI0_TX_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x40); + DMA_ADC_PRI_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x70); + DMA_GPT0A_PRI_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x90); + DMA_SPI1_RX_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x100); + DMA_SPI1_TX_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x110); + DMA_ADC_ALT_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x270); + DMA_GPT0A_ALT_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x290); + + /* + * Allocate SPI0, SPI1, ADC, and GPTimer0 DMA descriptors at absolute addresses. + * --------- DO NOT MODIFY ----------- + */ + UDMACC26XX_dmaSpi0RxControlTableEntry_is_placed = 0; + .dmaSpi0RxControlTableEntry DMA_SPI0_RX_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_SPI0_RX_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaSpi0RxControlTableEntry)} > REGION_DATA + + UDMACC26XX_dmaSpi0TxControlTableEntry_is_placed = 0; + .dmaSpi0TxControlTableEntry DMA_SPI0_TX_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_SPI0_TX_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaSpi0TxControlTableEntry)} > REGION_DATA + + UDMACC26XX_dmaADCPriControlTableEntry_is_placed = 0; + .dmaADCPriControlTableEntry DMA_ADC_PRI_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_ADC_PRI_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaADCPriControlTableEntry)} > REGION_DATA + + UDMACC26XX_dmaGPT0APriControlTableEntry_is_placed = 0; + .dmaGPT0APriControlTableEntry DMA_GPT0A_PRI_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_GPT0A_PRI_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaGPT0APriControlTableEntry)} > REGION_DATA + + UDMACC26XX_dmaSpi1RxControlTableEntry_is_placed = 0; + .dmaSpi1RxControlTableEntry DMA_SPI1_RX_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_SPI1_RX_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaSpi1RxControlTableEntry)} > REGION_DATA + + UDMACC26XX_dmaSpi1TxControlTableEntry_is_placed = 0; + .dmaSpi1TxControlTableEntry DMA_SPI1_TX_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_SPI1_TX_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaSpi1TxControlTableEntry)} > REGION_DATA + + UDMACC26XX_dmaADCAltControlTableEntry_is_placed = 0; + .dmaADCAltControlTableEntry DMA_ADC_ALT_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_ADC_ALT_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaADCAltControlTableEntry)} > REGION_DATA + + UDMACC26XX_dmaGPT0AAltControlTableEntry_is_placed = 0; + .dmaGPT0AAltControlTableEntry DMA_GPT0A_ALT_CONTROL_TABLE_ENTRY_ADDRESS (NOLOAD) : AT (DMA_GPT0A_ALT_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaGPT0AAltControlTableEntry)} > REGION_DATA + + .text : { + CREATE_OBJECT_SYMBOLS + *(.text) + *(.text.*) + . = ALIGN(0x4); + KEEP (*(.ctors)) + . = ALIGN(0x4); + KEEP (*(.dtors)) + . = ALIGN(0x4); + __init_array_start = .; + KEEP (*(.init_array*)) + __init_array_end = .; + *(.init) + *(.fini*) + } > REGION_TEXT AT> REGION_TEXT + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : { + *(.rodata) + *(.rodata.*) + } > REGION_TEXT AT> REGION_TEXT + + .data : ALIGN(4) { + __data_load__ = LOADADDR (.data); + __data_start__ = .; + *(.data) + *(.data.*) + . = ALIGN (4); + __data_end__ = .; + } > REGION_DATA AT> REGION_TEXT + + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX + + .ARM.extab : { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB + + .nvs (NOLOAD) : ALIGN(0x1000) { + *(.nvs) + } > REGION_TEXT + + .ccfg : { + KEEP (*(.ccfg)) + } > FLASH_CCFG AT> FLASH_CCFG + + .bss : { + __bss_start__ = .; + *(.shbss) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN (4); + __bss_end__ = .; + } > REGION_BSS AT> REGION_BSS + + .heap : { + __heap_start__ = .; + end = __heap_start__; + _end = end; + __end = end; + . = . + HEAPSIZE; + KEEP(*(.heap)) + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > REGION_HEAP AT> REGION_HEAP + + .stack (NOLOAD) : ALIGN(0x8) { + _stack = .; + __stack = .; + KEEP(*(.stack)) + . += STACKSIZE; + _stack_end = .; + __stack_end = .; + } > REGION_STACK AT> REGION_STACK +} diff --git a/examples/knx-cc1310/CC1310_LAUNCHXL_fxns.c b/examples/knx-cc1310/CC1310_LAUNCHXL_fxns.c new file mode 100644 index 0000000..a2df3a4 --- /dev/null +++ b/examples/knx-cc1310/CC1310_LAUNCHXL_fxns.c @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== CC1310_LAUNCHXL_fxns.c ======== + * This file contains the board-specific initialization functions. + */ + +#include +#include +#include + +#include +#include + +#include + +#include + + +/* + * ======== CC1310_LAUNCHXL_sendExtFlashByte ======== + */ +void CC1310_LAUNCHXL_sendExtFlashByte(PIN_Handle pinHandle, uint8_t byte) +{ + uint8_t i; + + /* SPI Flash CS */ + PIN_setOutputValue(pinHandle, IOID_20, 0); + + for (i = 0; i < 8; i++) { + PIN_setOutputValue(pinHandle, IOID_10, 0); /* SPI Flash CLK */ + + /* SPI Flash MOSI */ + PIN_setOutputValue(pinHandle, IOID_9, (byte >> (7 - i)) & 0x01); + PIN_setOutputValue(pinHandle, IOID_10, 1); /* SPI Flash CLK */ + + /* + * Waste a few cycles to keep the CLK high for at + * least 45% of the period. + * 3 cycles per loop: 8 loops @ 48 Mhz = 0.5 us. + */ + CPUdelay(8); + } + + PIN_setOutputValue(pinHandle, IOID_10, 0); /* CLK */ + PIN_setOutputValue(pinHandle, IOID_20, 1); /* CS */ + + /* + * Keep CS high at least 40 us + * 3 cycles per loop: 700 loops @ 48 Mhz ~= 44 us + */ + CPUdelay(700); +} + +/* + * ======== CC1310_LAUNCHXL_wakeUpExtFlash ======== + */ +void CC1310_LAUNCHXL_wakeUpExtFlash(void) +{ + PIN_Config extFlashPinTable[] = { + /* SPI Flash CS */ + IOID_20 | PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH | PIN_PUSHPULL | + PIN_INPUT_DIS | PIN_DRVSTR_MED, + PIN_TERMINATE + }; + PIN_State extFlashPinState; + PIN_Handle extFlashPinHandle = PIN_open(&extFlashPinState, extFlashPinTable); + + /* + * To wake up we need to toggle the chip select at + * least 20 ns and ten wait at least 35 us. + */ + + /* Toggle chip select for ~20ns to wake ext. flash */ + PIN_setOutputValue(extFlashPinHandle, IOID_20, 0); + /* 3 cycles per loop: 1 loop @ 48 Mhz ~= 62 ns */ + CPUdelay(1); + PIN_setOutputValue(extFlashPinHandle, IOID_20, 1); + /* 3 cycles per loop: 560 loops @ 48 Mhz ~= 35 us */ + CPUdelay(560); + + PIN_close(extFlashPinHandle); +} + +/* + * ======== CC1310_LAUNCHXL_shutDownExtFlash ======== + */ +void CC1310_LAUNCHXL_shutDownExtFlash(void) +{ + /* + * To be sure we are putting the flash into sleep and not waking it, + * we first have to make a wake up call + */ + CC1310_LAUNCHXL_wakeUpExtFlash(); + + PIN_Config extFlashPinTable[] = { + /* SPI Flash CS*/ + IOID_20 | PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH | PIN_PUSHPULL | + PIN_INPUT_DIS | PIN_DRVSTR_MED, + /* SPI Flash CLK */ + IOID_10 | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | + PIN_INPUT_DIS | PIN_DRVSTR_MED, + /* SPI Flash MOSI */ + IOID_9 | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | + PIN_INPUT_DIS | PIN_DRVSTR_MED, + /* SPI Flash MISO */ + IOID_8 | PIN_INPUT_EN | PIN_PULLDOWN, + PIN_TERMINATE + }; + PIN_State extFlashPinState; + PIN_Handle extFlashPinHandle = PIN_open(&extFlashPinState, extFlashPinTable); + + uint8_t extFlashShutdown = 0xB9; + + CC1310_LAUNCHXL_sendExtFlashByte(extFlashPinHandle, extFlashShutdown); + + PIN_close(extFlashPinHandle); +} + +/* + * ======== Board_initHook ======== + * Called by Board_init() to perform board-specific initialization. + */ +void Board_initHook() +{ + CC1310_LAUNCHXL_shutDownExtFlash(); +} diff --git a/examples/knx-cc1310/CMakeLists.txt b/examples/knx-cc1310/CMakeLists.txt new file mode 100644 index 0000000..87e0f37 --- /dev/null +++ b/examples/knx-cc1310/CMakeLists.txt @@ -0,0 +1,210 @@ +## +## KNX for CC1310 +## + +cmake_minimum_required(VERSION 3.12) + +if(NOT DEFINED CMAKE_TOOLCHAIN_FILE) + set(CMAKE_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/cmake/toolchain-arm-none-eabi.cmake") +endif() + +project(knx-cc1310 C CXX ASM) + +# Generate a "compile_commands.json" file containing the exact compiler calls for all translation units of the project in machine-readable form. +# Useful for C/CPP extension of VS code +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Use _ROOT variables for locating in find_path, find_package, etc. +cmake_policy(SET CMP0074 NEW) + +# Append current directory to CMAKE_MODULE_PATH for making device specific cmake modules visible +list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_LIST_DIR}/cmake) +message("CMAKE_MODULE_PATH: ${CMAKE_MODULE_PATH}") + +# Configure Toolchain for CC13xx +set(LINKER_SCRIPT "${CMAKE_CURRENT_SOURCE_DIR}/CC1310_LAUNCHXL_NoRTOS.lds") +include(cc13xx) + +set(SimpleLinkCC13X0SDKnortos_ROOT "${CMAKE_CURRENT_SOURCE_DIR}/coresdk_cc13xx_cc26xx") +message("SimpleLinkCC13X0SDKnortos_ROOT: ${SimpleLinkCC13X0SDKnortos_ROOT}") + +# Find dependencies +find_package(SimpleLinkCC13X0SDKnortos REQUIRED) + +# +# Target +# + +set(${PROJECT_NAME}_SOURCES + ../../src/knx/address_table_object.cpp + ../../src/knx/address_table_object.h + ../../src/knx/aes.c + ../../src/knx/aes.h + ../../src/knx/aes.hpp + ../../src/knx/apdu.cpp + ../../src/knx/apdu.h + ../../src/knx/application_layer.cpp + ../../src/knx/application_layer.h + ../../src/knx/application_program_object.cpp + ../../src/knx/application_program_object.h + ../../src/knx/association_table_object.cpp + ../../src/knx/association_table_object.h + ../../src/knx/bau.cpp + ../../src/knx/bau.h + ../../src/knx/bau07B0.cpp + ../../src/knx/bau07B0.h + ../../src/knx/bau091A.cpp + ../../src/knx/bau091A.h + ../../src/knx/bau27B0.cpp + ../../src/knx/bau27B0.h + ../../src/knx/bau2920.cpp + ../../src/knx/bau2920.h + ../../src/knx/bau57B0.cpp + ../../src/knx/bau57B0.h + ../../src/knx/bau_systemB.cpp + ../../src/knx/bau_systemB.h + ../../src/knx/bau_systemB_device.cpp + ../../src/knx/bau_systemB_device.h + ../../src/knx/bau_systemB_coupler.cpp + ../../src/knx/bau_systemB_coupler.h + ../../src/knx/bits.cpp + ../../src/knx/bits.h + ../../src/knx/callback_property.h + ../../src/knx/cemi_frame.cpp + ../../src/knx/cemi_frame.h + ../../src/knx/cemi_server.cpp + ../../src/knx/cemi_server.h + ../../src/knx/cemi_server_object.cpp + ../../src/knx/cemi_server_object.h + ../../src/knx/config.h + ../../src/knx/data_link_layer.cpp + ../../src/knx/data_link_layer.h + ../../src/knx/data_property.cpp + ../../src/knx/data_property.h + ../../src/knx/device_object.cpp + ../../src/knx/device_object.h + ../../src/knx/dpt.cpp + ../../src/knx/dpt.h + ../../src/knx/dptconvert.cpp + ../../src/knx/dptconvert.h + ../../src/knx/function_property.h + ../../src/knx/group_object.cpp + ../../src/knx/group_object.h + ../../src/knx/group_object_table_object.cpp + ../../src/knx/group_object_table_object.h + ../../src/knx/interface_object.cpp + ../../src/knx/interface_object.h + ../../src/knx/ip_data_link_layer.cpp + ../../src/knx/ip_data_link_layer.h + ../../src/knx/ip_parameter_object.cpp + ../../src/knx/ip_parameter_object.h + ../../src/knx/knx_ip_device_information_dib.cpp + ../../src/knx/knx_ip_device_information_dib.h + ../../src/knx/knx_ip_dib.cpp + ../../src/knx/knx_ip_dib.h + ../../src/knx/knx_ip_frame.cpp + ../../src/knx/knx_ip_frame.h + ../../src/knx/knx_ip_routing_indication.cpp + ../../src/knx/knx_ip_routing_indication.h + ../../src/knx/knx_ip_search_request.cpp + ../../src/knx/knx_ip_search_request.h + ../../src/knx/knx_ip_search_response.cpp + ../../src/knx/knx_ip_search_response.h + ../../src/knx/knx_ip_supported_service_dib.cpp + ../../src/knx/knx_ip_supported_service_dib.h + ../../src/knx/ip_host_protocol_address_information.cpp + ../../src/knx/ip_host_protocol_address_information.h + ../../src/knx/knx_types.h + ../../src/knx/knx_value.cpp + ../../src/knx/knx_value.h + ../../src/knx/memory.cpp + ../../src/knx/memory.h + ../../src/knx/network_layer.cpp + ../../src/knx/network_layer.h + ../../src/knx/network_layer_coupler.cpp + ../../src/knx/network_layer_coupler.h + ../../src/knx/network_layer_device.cpp + ../../src/knx/network_layer_device.h + ../../src/knx/network_layer_entity.cpp + ../../src/knx/network_layer_entity.h + ../../src/knx/npdu.cpp + ../../src/knx/npdu.h + ../../src/knx/platform.cpp + ../../src/knx/platform.h + ../../src/knx/property.cpp + ../../src/knx/property.h + ../../src/knx/rf_data_link_layer.cpp + ../../src/knx/rf_data_link_layer.h + ../../src/knx/rf_medium_object.cpp + ../../src/knx/rf_medium_object.h + ../../src/knx/rf_physical_layer_cc1310.cpp + ../../src/knx/rf_physical_layer_cc1310.h + ../../src/knx/rf_physical_layer.h + ../../src/knx/router_object.cpp + ../../src/knx/router_object.h + ../../src/knx/secure_application_layer.cpp + ../../src/knx/secure_application_layer.h + ../../src/knx/security_interface_object.cpp + ../../src/knx/security_interface_object.h + ../../src/knx/simple_map.h + ../../src/knx/save_restore.h + ../../src/knx/table_object.cpp + ../../src/knx/table_object.h + ../../src/knx/tpdu.cpp + ../../src/knx/tpdu.h + ../../src/knx/tpuart_data_link_layer.cpp + ../../src/knx/tpuart_data_link_layer.h + ../../src/knx/transport_layer.cpp + ../../src/knx/transport_layer.h + ../../src/knx/usb_tunnel_interface.cpp + ../../src/knx/usb_tunnel_interface.h + ../../src/knx_facade.cpp + ../../src/knx_facade.h + ../../src/cc1310_platform.cpp + ../../src/knx_facade.cpp + ./RTT/SEGGER_RTT_Conf.h + ./RTT/SEGGER_RTT_printf.c + ./RTT/SEGGER_RTT.c + ./RTT/SEGGER_RTT.h + ./RTT/SEGGER_RTT_ASM_ARMv7M.S + ./smartrf_settings/smartrf_settings.c + ./smartrf_settings/smartrf_settings.h + ./CC1310_LAUNCHXL_fxns.c + ./CC1310_LAUNCHXL.c + ./CC1310_LAUNCHXL.h + ./knx_wrapper.cpp + ./knx_wrapper.h + ./ccfg.c + ./main_nortos.c + ./startup_cc13xx_cc26xx_gcc.c +) + +include_directories( + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/../../src + ${CMAKE_CURRENT_SOURCE_DIR}/../../src/knx + ${CMAKE_CURRENT_SOURCE_DIR}/RTT + ${SimpleLinkCC13X0SDK_INCLUDE_DIRS} +) + +add_definitions(-DMASK_VERSION=0x27B0 -Wno-unknown-pragmas) + +add_executable(${PROJECT_NAME} + ${${PROJECT_NAME}_SOURCES} +) + +target_link_libraries(${PROJECT_NAME} + -Wl,--start-group + ${SimpleLinkCC13X0SDK_drivers_cc13x0_LIBRARY} + ${SimpleLinkCC13X0SDK_dpl_cc13x0_LIBRARY} + ${SimpleLinkCC13X0SDK_driverlib_LIBRARY} + ${SimpleLinkCC13X0SDK_rf_singleMode_cc13x0_LIBRARY} + -Wl,--end-group + gcc + m + nosys + c +) + +target_compile_definitions(${PROJECT_NAME} PUBLIC -DDeviceFamily_CC13X0 -DRF_SINGLEMODE -DKNX_FLASH_SIZE=2048) + diff --git a/examples/knx-cc1310/README.md b/examples/knx-cc1310/README.md new file mode 100644 index 0000000..e3005ef --- /dev/null +++ b/examples/knx-cc1310/README.md @@ -0,0 +1,13 @@ +Example for Texas Instruments LaunchPad LAUNCHXL-CC1310 +=== + +Requirements: + * Texas Instruments LaunchPad [LAUNCHXL-CC1310](https://www.ti.com/tool/LAUNCHXL-CC1310) + * Optional: Segger J-Link + +Button0 (BTN-1, DIO13): Programming Mode on/off +Button1 (BTN-2, DIO14): Press and hold while starting the board to erase the flash +LED0 (RED, DIO6): Programming mode +LED1 (GREEN, DIO7): If flashing with 500ms together with LED0 a fatal error occured and the system is halted + + diff --git a/examples/knx-cc1310/RTT/SEGGER_RTT.c b/examples/knx-cc1310/RTT/SEGGER_RTT.c new file mode 100644 index 0000000..afbc311 --- /dev/null +++ b/examples/knx-cc1310/RTT/SEGGER_RTT.c @@ -0,0 +1,2025 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2019 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT.c +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 19464 $ + +Additional information: + Type "int" is assumed to be 32-bits in size + H->T Host to target communication + T->H Target to host communication + + RTT channel 0 is always present and reserved for Terminal usage. + Name is fixed to "Terminal" + + Effective buffer size: SizeOfBuffer - 1 + + WrOff == RdOff: Buffer is empty + WrOff == (RdOff - 1): Buffer is full + WrOff > RdOff: Free space includes wrap-around + WrOff < RdOff: Used space includes wrap-around + (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0): + Buffer full and wrap-around after next byte + + +---------------------------------------------------------------------- +*/ + +#include "SEGGER_RTT.h" + +#include // for memcpy + +/********************************************************************* +* +* Configuration, default values +* +********************************************************************** +*/ + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP 1024 // Size of the buffer for terminal output of target, up to host +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN 16 // Size of the buffer for terminal input to target from host (Usually keyboard input) +#endif + +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS 2 // Number of up-buffers (T->H) available on this target +#endif + +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 2 // Number of down-buffers (H->T) available on this target +#endif + +#ifndef SEGGER_RTT_BUFFER_SECTION + #if defined(SEGGER_RTT_SECTION) + #define SEGGER_RTT_BUFFER_SECTION SEGGER_RTT_SECTION + #endif +#endif + +#ifndef SEGGER_RTT_ALIGNMENT + #define SEGGER_RTT_ALIGNMENT 0 +#endif + +#ifndef SEGGER_RTT_BUFFER_ALIGNMENT + #define SEGGER_RTT_BUFFER_ALIGNMENT 0 +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP +#endif + +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() +#endif + +#ifndef STRLEN + #define STRLEN(a) strlen((a)) +#endif + +#ifndef STRCPY + #define STRCPY(pDest, pSrc, NumBytes) strcpy((pDest), (pSrc)) +#endif + +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP + #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 +#endif + +#ifndef SEGGER_RTT_MEMCPY + #ifdef MEMCPY + #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) MEMCPY((pDest), (pSrc), (NumBytes)) + #else + #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) memcpy((pDest), (pSrc), (NumBytes)) + #endif +#endif + +#ifndef MIN + #define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef MAX + #define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +// +// For some environments, NULL may not be defined until certain headers are included +// +#ifndef NULL + #define NULL 0 +#endif + +/********************************************************************* +* +* Defines, fixed +* +********************************************************************** +*/ +#if (defined __ICCARM__) || (defined __ICCRX__) + #define RTT_PRAGMA(P) _Pragma(#P) +#endif + +#if SEGGER_RTT_ALIGNMENT || SEGGER_RTT_BUFFER_ALIGNMENT + #if (defined __GNUC__) + #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) + #elif (defined __ICCARM__) || (defined __ICCRX__) + #define PRAGMA(A) _Pragma(#A) +#define SEGGER_RTT_ALIGN(Var, Alignment) RTT_PRAGMA(data_alignment=Alignment) \ + Var + #elif (defined __CC_ARM) + #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) + #else + #error "Alignment not supported for this compiler." + #endif +#else + #define SEGGER_RTT_ALIGN(Var, Alignment) Var +#endif + +#if defined(SEGGER_RTT_SECTION) || defined (SEGGER_RTT_BUFFER_SECTION) + #if (defined __GNUC__) + #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section))) Var + #elif (defined __ICCARM__) || (defined __ICCRX__) +#define SEGGER_RTT_PUT_SECTION(Var, Section) RTT_PRAGMA(location=Section) \ + Var + #elif (defined __CC_ARM) + #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section), zero_init)) Var + #else + #error "Section placement not supported for this compiler." + #endif +#else + #define SEGGER_RTT_PUT_SECTION(Var, Section) Var +#endif + + +#if SEGGER_RTT_ALIGNMENT + #define SEGGER_RTT_CB_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_ALIGNMENT) +#else + #define SEGGER_RTT_CB_ALIGN(Var) Var +#endif + +#if SEGGER_RTT_BUFFER_ALIGNMENT + #define SEGGER_RTT_BUFFER_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_BUFFER_ALIGNMENT) +#else + #define SEGGER_RTT_BUFFER_ALIGN(Var) Var +#endif + + +#if defined(SEGGER_RTT_SECTION) + #define SEGGER_RTT_PUT_CB_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_SECTION) +#else + #define SEGGER_RTT_PUT_CB_SECTION(Var) Var +#endif + +#if defined(SEGGER_RTT_BUFFER_SECTION) + #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_BUFFER_SECTION) +#else + #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) Var +#endif + +/********************************************************************* +* +* Static const data +* +********************************************************************** +*/ + +static unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; + +/********************************************************************* +* +* Static data +* +********************************************************************** +*/ +// +// RTT Control Block and allocate buffers for channel 0 +// +SEGGER_RTT_PUT_CB_SECTION(SEGGER_RTT_CB_ALIGN(SEGGER_RTT_CB _SEGGER_RTT)); + +SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer [BUFFER_SIZE_UP])); +SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[BUFFER_SIZE_DOWN])); + +static unsigned char _ActiveTerminal; + +/********************************************************************* +* +* Static functions +* +********************************************************************** +*/ + +/********************************************************************* +* +* _DoInit() +* +* Function description +* Initializes the control block an buffers. +* May only be called via INIT() to avoid overriding settings. +* +*/ +#define INIT() do { \ + if (_SEGGER_RTT.acID[0] == '\0') { _DoInit(); } \ + } while (0) +static void _DoInit(void) { + SEGGER_RTT_CB* p; + // + // Initialize control block + // + p = &_SEGGER_RTT; + p->MaxNumUpBuffers = SEGGER_RTT_MAX_NUM_UP_BUFFERS; + p->MaxNumDownBuffers = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS; + // + // Initialize up buffer 0 + // + p->aUp[0].sName = "Terminal"; + p->aUp[0].pBuffer = _acUpBuffer; + p->aUp[0].SizeOfBuffer = sizeof(_acUpBuffer); + p->aUp[0].RdOff = 0u; + p->aUp[0].WrOff = 0u; + p->aUp[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Initialize down buffer 0 + // + p->aDown[0].sName = "Terminal"; + p->aDown[0].pBuffer = _acDownBuffer; + p->aDown[0].SizeOfBuffer = sizeof(_acDownBuffer); + p->aDown[0].RdOff = 0u; + p->aDown[0].WrOff = 0u; + p->aDown[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Finish initialization of the control block. + // Copy Id string in three steps to make sure "SEGGER RTT" is not found + // in initializer memory (usually flash) by J-Link + // + STRCPY(&p->acID[7], "RTT", 9); + RTT__DMB(); + STRCPY(&p->acID[0], "SEGGER", 7); + RTT__DMB(); + p->acID[6] = ' '; + RTT__DMB(); +} + +/********************************************************************* +* +* _WriteBlocking() +* +* Function description +* Stores a specified number of characters in SEGGER RTT ring buffer +* and updates the associated write pointer which is periodically +* read by the host. +* The caller is responsible for managing the write chunk sizes as +* _WriteBlocking() will block until all data has been posted successfully. +* +* Parameters +* pRing Ring buffer to post to. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* >= 0 - Number of bytes written into buffer. +*/ +static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) { + unsigned NumBytesToWrite; + unsigned NumBytesWritten; + unsigned RdOff; + unsigned WrOff; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + char* pDst; +#endif + // + // Write data to buffer and handle wrap-around if necessary + // + NumBytesWritten = 0u; + WrOff = pRing->WrOff; + do { + RdOff = pRing->RdOff; // May be changed by host (debug probe) in the meantime + if (RdOff > WrOff) { + NumBytesToWrite = RdOff - WrOff - 1u; + } else { + NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u); + } + NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff)); // Number of bytes that can be written until buffer wrap-around + NumBytesToWrite = MIN(NumBytesToWrite, NumBytes); +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + WrOff; + NumBytesWritten += NumBytesToWrite; + NumBytes -= NumBytesToWrite; + WrOff += NumBytesToWrite; + while (NumBytesToWrite--) { + *pDst++ = *pBuffer++; + }; +#else + SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pBuffer, NumBytesToWrite); + NumBytesWritten += NumBytesToWrite; + pBuffer += NumBytesToWrite; + NumBytes -= NumBytesToWrite; + WrOff += NumBytesToWrite; +#endif + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0u; + } + RTT__DMB(); + pRing->WrOff = WrOff; + } while (NumBytes); + // + return NumBytesWritten; +} + +/********************************************************************* +* +* _WriteNoCheck() +* +* Function description +* Stores a specified number of characters in SEGGER RTT ring buffer +* and updates the associated write pointer which is periodically +* read by the host. +* It is callers responsibility to make sure data actually fits in buffer. +* +* Parameters +* pRing Ring buffer to post to. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Notes +* (1) If there might not be enough space in the "Up"-buffer, call _WriteBlocking +*/ +static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) { + unsigned NumBytesAtOnce; + unsigned WrOff; + unsigned Rem; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + char* pDst; +#endif + + WrOff = pRing->WrOff; + Rem = pRing->SizeOfBuffer - WrOff; + if (Rem > NumBytes) { + // + // All data fits before wrap around + // +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + WrOff; + WrOff += NumBytes; + while (NumBytes--) { + *pDst++ = *pData++; + }; + RTT__DMB(); + pRing->WrOff = WrOff; +#else + SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pData, NumBytes); + RTT__DMB(); + pRing->WrOff = WrOff + NumBytes; +#endif + } else { + // + // We reach the end of the buffer, so need to wrap around + // +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + WrOff; + NumBytesAtOnce = Rem; + while (NumBytesAtOnce--) { + *pDst++ = *pData++; + }; + pDst = pRing->pBuffer; + NumBytesAtOnce = NumBytes - Rem; + while (NumBytesAtOnce--) { + *pDst++ = *pData++; + }; + RTT__DMB(); + pRing->WrOff = NumBytes - Rem; +#else + NumBytesAtOnce = Rem; + SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pData, NumBytesAtOnce); + NumBytesAtOnce = NumBytes - Rem; + SEGGER_RTT_MEMCPY(pRing->pBuffer, pData + Rem, NumBytesAtOnce); + RTT__DMB(); + pRing->WrOff = NumBytesAtOnce; +#endif + } +} + +/********************************************************************* +* +* _PostTerminalSwitch() +* +* Function description +* Switch terminal to the given terminal ID. It is the caller's +* responsibility to ensure the terminal ID is correct and there is +* enough space in the buffer for this to complete successfully. +* +* Parameters +* pRing Ring buffer to post to. +* TerminalId Terminal ID to switch to. +*/ +static void _PostTerminalSwitch(SEGGER_RTT_BUFFER_UP* pRing, unsigned char TerminalId) { + unsigned char ac[2]; + + ac[0] = 0xFFu; + ac[1] = _aTerminalId[TerminalId]; // Caller made already sure that TerminalId does not exceed our terminal limit + _WriteBlocking(pRing, (const char*)ac, 2u); +} + +/********************************************************************* +* +* _GetAvailWriteSpace() +* +* Function description +* Returns the number of bytes that can be written to the ring +* buffer without blocking. +* +* Parameters +* pRing Ring buffer to check. +* +* Return value +* Number of bytes that are free in the buffer. +*/ +static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) { + unsigned RdOff; + unsigned WrOff; + unsigned r; + // + // Avoid warnings regarding volatile access order. It's not a problem + // in this case, but dampen compiler enthusiasm. + // + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + if (RdOff <= WrOff) { + r = pRing->SizeOfBuffer - 1u - WrOff + RdOff; + } else { + r = RdOff - WrOff - 1u; + } + return r; +} + +/********************************************************************* +* +* Public code +* +********************************************************************** +*/ +/********************************************************************* +* +* SEGGER_RTT_ReadUpBufferNoLock() +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the application. +* Do not lock against interrupts and multiple access. +* Used to do the same operation that J-Link does, to transfer +* RTT data via other channels, such as TCP/IP or UART. +* +* Parameters +* BufferIndex Index of Up-buffer to be used. +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +* +* Additional information +* This function must not be called when J-Link might also do RTT. +*/ +unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { + unsigned NumBytesRem; + unsigned NumBytesRead; + unsigned RdOff; + unsigned WrOff; + unsigned char* pBuffer; + SEGGER_RTT_BUFFER_UP* pRing; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + const char* pSrc; +#endif + // + INIT(); + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + pBuffer = (unsigned char*)pData; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + NumBytesRead = 0u; + // + // Read from current read position to wrap-around of buffer, first + // + if (RdOff > WrOff) { + NumBytesRem = pRing->SizeOfBuffer - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pSrc = pRing->pBuffer + RdOff; + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + // + // Handle wrap-around of buffer + // + if (RdOff == pRing->SizeOfBuffer) { + RdOff = 0u; + } + } + // + // Read remaining items of buffer + // + NumBytesRem = WrOff - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + if (NumBytesRem > 0u) { +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pSrc = pRing->pBuffer + RdOff; + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + } + // + // Update read offset of buffer + // + if (NumBytesRead) { + pRing->RdOff = RdOff; + } + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_ReadNoLock() +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the host. +* Do not lock against interrupts and multiple access. +* +* Parameters +* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +*/ +unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { + unsigned NumBytesRem; + unsigned NumBytesRead; + unsigned RdOff; + unsigned WrOff; + unsigned char* pBuffer; + SEGGER_RTT_BUFFER_DOWN* pRing; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + const char* pSrc; +#endif + // + INIT(); + pRing = &_SEGGER_RTT.aDown[BufferIndex]; + pBuffer = (unsigned char*)pData; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + NumBytesRead = 0u; + // + // Read from current read position to wrap-around of buffer, first + // + if (RdOff > WrOff) { + NumBytesRem = pRing->SizeOfBuffer - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pSrc = pRing->pBuffer + RdOff; + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + // + // Handle wrap-around of buffer + // + if (RdOff == pRing->SizeOfBuffer) { + RdOff = 0u; + } + } + // + // Read remaining items of buffer + // + NumBytesRem = WrOff - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + if (NumBytesRem > 0u) { +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pSrc = pRing->pBuffer + RdOff; + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + } + if (NumBytesRead) { + pRing->RdOff = RdOff; + } + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_ReadUpBuffer +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the application. +* Used to do the same operation that J-Link does, to transfer +* RTT data via other channels, such as TCP/IP or UART. +* +* Parameters +* BufferIndex Index of Up-buffer to be used. +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +* +* Additional information +* This function must not be called when J-Link might also do RTT. +* This function locks against all other RTT operations. I.e. during +* the read operation, writing is also locked. +* If only one consumer reads from the up buffer, +* call sEGGER_RTT_ReadUpBufferNoLock() instead. +*/ +unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { + unsigned NumBytesRead; + // + SEGGER_RTT_LOCK(); + // + // Call the non-locking read function + // + NumBytesRead = SEGGER_RTT_ReadUpBufferNoLock(BufferIndex, pBuffer, BufferSize); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_Read +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the host. +* +* Parameters +* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +*/ +unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { + unsigned NumBytesRead; + // + SEGGER_RTT_LOCK(); + // + // Call the non-locking read function + // + NumBytesRead = SEGGER_RTT_ReadNoLock(BufferIndex, pBuffer, BufferSize); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteWithOverwriteNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block. +* SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application +* and overwrites data if the data does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, data is overwritten. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +* (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link +* connection reads RTT data. +*/ +void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + char* pDst; +#endif + + pData = (const char *)pBuffer; + // + // Get "to-host" ring buffer and copy some elements into local variables. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + // + // Check if we will overwrite data and need to adjust the RdOff. + // + if (pRing->WrOff == pRing->RdOff) { + Avail = pRing->SizeOfBuffer - 1u; + } else if ( pRing->WrOff < pRing->RdOff) { + Avail = pRing->RdOff - pRing->WrOff - 1u; + } else { + Avail = pRing->RdOff - pRing->WrOff - 1u + pRing->SizeOfBuffer; + } + if (NumBytes > Avail) { + pRing->RdOff += (NumBytes - Avail); + while (pRing->RdOff >= pRing->SizeOfBuffer) { + pRing->RdOff -= pRing->SizeOfBuffer; + } + } + // + // Write all data, no need to check the RdOff, but possibly handle multiple wrap-arounds + // + Avail = pRing->SizeOfBuffer - pRing->WrOff; + do { + if (Avail > NumBytes) { + // + // Last round + // +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + pRing->WrOff; + Avail = NumBytes; + while (NumBytes--) { + *pDst++ = *pData++; + }; + RTT__DMB(); + pRing->WrOff += Avail; +#else + SEGGER_RTT_MEMCPY(pRing->pBuffer + pRing->WrOff, pData, NumBytes); + RTT__DMB(); + pRing->WrOff += NumBytes; +#endif + break; + } else { + // + // Wrap-around necessary, write until wrap-around and reset WrOff + // +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + pRing->WrOff; + NumBytes -= Avail; + while (Avail--) { + *pDst++ = *pData++; + }; + RTT__DMB(); + pRing->WrOff = 0; +#else + SEGGER_RTT_MEMCPY(pRing->pBuffer + pRing->WrOff, pData, Avail); + pData += Avail; + RTT__DMB(); + pRing->WrOff = 0; + NumBytes -= Avail; +#endif + Avail = (pRing->SizeOfBuffer - 1); + } + } while (NumBytes); +} + +/********************************************************************* +* +* SEGGER_RTT_WriteSkipNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* SEGGER_RTT_WriteSkipNoLock does not lock the application and +* skips all data, if the data does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* MUST be > 0!!! +* This is done for performance reasons, so no initial check has do be done. +* +* Return value +* 1: Data has been copied +* 0: No space, data has not been copied +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, all data is dropped. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ +#if (RTT_USE_ASM == 0) +unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + unsigned RdOff; + unsigned WrOff; + unsigned Rem; + // + // Cases: + // 1) RdOff <= WrOff => Space until wrap-around is sufficient + // 2) RdOff <= WrOff => Space after wrap-around needed (copy in 2 chunks) + // 3) RdOff < WrOff => No space in buf + // 4) RdOff > WrOff => Space is sufficient + // 5) RdOff > WrOff => No space in buf + // + // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough + // + pData = (const char *)pBuffer; + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + if (RdOff <= WrOff) { // Case 1), 2) or 3) + Avail = pRing->SizeOfBuffer - WrOff - 1u; // Space until wrap-around (assume 1 byte not usable for case that RdOff == 0) + if (Avail >= NumBytes) { // Case 1)? +CopyStraight: + memcpy(pRing->pBuffer + WrOff, pData, NumBytes); + RTT__DMB(); + pRing->WrOff = WrOff + NumBytes; + return 1; + } + Avail += RdOff; // Space incl. wrap-around + if (Avail >= NumBytes) { // Case 2? => If not, we have case 3) (does not fit) + Rem = pRing->SizeOfBuffer - WrOff; // Space until end of buffer + memcpy(pRing->pBuffer + WrOff, pData, Rem); // Copy 1st chunk + NumBytes -= Rem; + // + // Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could not be used + // But 2nd check (considering space until wrap-around and until RdOff) revealed that RdOff is not 0, so we can use the last element + // In this case, we may use a copy straight until buffer end anyway without needing to copy 2 chunks + // Therefore, check if 2nd memcpy is necessary at all + // + if (NumBytes) { + memcpy(pRing->pBuffer, pData + Rem, NumBytes); + } + RTT__DMB(); + pRing->WrOff = NumBytes; + return 1; + } + } else { // Potential case 4) + Avail = RdOff - WrOff - 1u; + if (Avail >= NumBytes) { // Case 4)? => If not, we have case 5) (does not fit) + goto CopyStraight; + } + } + return 0; // No space in buffer +} +#endif + +/********************************************************************* +* +* SEGGER_RTT_WriteDownBufferNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block inside a buffer. +* SEGGER_RTT_WriteDownBufferNoLock does not lock the application. +* Used to do the same operation that J-Link does, to transfer +* RTT data from other channels, such as TCP/IP or UART. +* +* Parameters +* BufferIndex Index of "Down"-buffer to be used. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Down"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +* +* Additional information +* This function must not be called when J-Link might also do RTT. +*/ +unsigned SEGGER_RTT_WriteDownBufferNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + unsigned Avail; + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + + pData = (const char *)pBuffer; + // + // Get "to-target" ring buffer. + // It is save to cast that to a "to-host" buffer. Up and Down buffer differ in volatility of offsets that might be modified by J-Link. + // + pRing = (SEGGER_RTT_BUFFER_UP*)&_SEGGER_RTT.aDown[BufferIndex]; + // + // How we output depends upon the mode... + // + switch (pRing->Flags) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother. + // + Avail = _GetAvailWriteSpace(pRing); + if (Avail < NumBytes) { + Status = 0u; + } else { + Status = NumBytes; + _WriteNoCheck(pRing, pData, NumBytes); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode, trim to what we can output without blocking. + // + Avail = _GetAvailWriteSpace(pRing); + Status = Avail < NumBytes ? Avail : NumBytes; + _WriteNoCheck(pRing, pData, Status); + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + Status = _WriteBlocking(pRing, pData, NumBytes); + break; + default: + Status = 0u; + break; + } + // + // Finish up. + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* SEGGER_RTT_WriteNoLock does not lock the application. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ +unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + unsigned Avail; + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + + pData = (const char *)pBuffer; + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + // + // How we output depends upon the mode... + // + switch (pRing->Flags) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother. + // + Avail = _GetAvailWriteSpace(pRing); + if (Avail < NumBytes) { + Status = 0u; + } else { + Status = NumBytes; + _WriteNoCheck(pRing, pData, NumBytes); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode, trim to what we can output without blocking. + // + Avail = _GetAvailWriteSpace(pRing); + Status = Avail < NumBytes ? Avail : NumBytes; + _WriteNoCheck(pRing, pData, Status); + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + Status = _WriteBlocking(pRing, pData, NumBytes); + break; + default: + Status = 0u; + break; + } + // + // Finish up. + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteDownBuffer +* +* Function description +* Stores a specified number of characters in SEGGER RTT control block in a buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Down"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* +* Additional information +* This function must not be called when J-Link might also do RTT. +* This function locks against all other RTT operations. I.e. during +* the write operation, writing from the application is also locked. +* If only one consumer writes to the down buffer, +* call SEGGER_RTT_WriteDownBufferNoLock() instead. +*/ +unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Call the non-locking write function + // + Status = SEGGER_RTT_WriteDownBufferNoLock(BufferIndex, pBuffer, NumBytes); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_Write +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +*/ +unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Call the non-locking write function + // + Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteString +* +* Function description +* Stores string in SEGGER RTT control block. +* This data is read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* s Pointer to string. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* (2) String passed to this function has to be \0 terminated +* (3) \0 termination character is *not* stored in RTT buffer +*/ +unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char* s) { + unsigned Len; + + Len = STRLEN(s); + return SEGGER_RTT_Write(BufferIndex, s, Len); +} + +/********************************************************************* +* +* SEGGER_RTT_PutCharSkipNoLock +* +* Function description +* Stores a single character/byte in SEGGER RTT buffer. +* SEGGER_RTT_PutCharSkipNoLock does not lock the application and +* skips the byte, if it does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* c Byte to be stored. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, the character is dropped. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ + +unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned WrOff; + unsigned Status; + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0; + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) { + pRing->pBuffer[pRing->WrOff] = c; + RTT__DMB(); + pRing->WrOff = WrOff; + Status = 1; + } else { + Status = 0; + } + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_PutCharSkip +* +* Function description +* Stores a single character/byte in SEGGER RTT buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* c Byte to be stored. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, the character is dropped. +*/ + +unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned WrOff; + unsigned Status; + // + // Prepare + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0; + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) { + pRing->pBuffer[pRing->WrOff] = c; + RTT__DMB(); + pRing->WrOff = WrOff; + Status = 1; + } else { + Status = 0; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return Status; +} + + /********************************************************************* +* +* SEGGER_RTT_PutChar +* +* Function description +* Stores a single character/byte in SEGGER RTT buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* c Byte to be stored. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +*/ + +unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned WrOff; + unsigned Status; + // + // Prepare + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0; + } + // + // Wait for free space if mode is set to blocking + // + if (pRing->Flags == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { + while (WrOff == pRing->RdOff) { + ; + } + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) { + pRing->pBuffer[pRing->WrOff] = c; + RTT__DMB(); + pRing->WrOff = WrOff; + Status = 1; + } else { + Status = 0; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_GetKey +* +* Function description +* Reads one character from the SEGGER RTT buffer. +* Host has previously stored data there. +* +* Return value +* < 0 - No character available (buffer empty). +* >= 0 - Character which has been read. (Possible values: 0 - 255) +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0. +*/ +int SEGGER_RTT_GetKey(void) { + char c; + int r; + + r = (int)SEGGER_RTT_Read(0u, &c, 1u); + if (r == 1) { + r = (int)(unsigned char)c; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_WaitKey +* +* Function description +* Waits until at least one character is avaible in the SEGGER RTT buffer. +* Once a character is available, it is read and this function returns. +* +* Return value +* >=0 - Character which has been read. +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0 +* (2) This function is blocking if no character is present in RTT buffer +*/ +int SEGGER_RTT_WaitKey(void) { + int r; + + do { + r = SEGGER_RTT_GetKey(); + } while (r < 0); + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_HasKey +* +* Function description +* Checks if at least one character for reading is available in the SEGGER RTT buffer. +* +* Return value +* == 0 - No characters are available to read. +* == 1 - At least one character is available. +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0 +*/ +int SEGGER_RTT_HasKey(void) { + unsigned RdOff; + int r; + + INIT(); + RdOff = _SEGGER_RTT.aDown[0].RdOff; + if (RdOff != _SEGGER_RTT.aDown[0].WrOff) { + r = 1; + } else { + r = 0; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_HasData +* +* Function description +* Check if there is data from the host in the given buffer. +* +* Return value: +* ==0: No data +* !=0: Data in buffer +* +*/ +unsigned SEGGER_RTT_HasData(unsigned BufferIndex) { + SEGGER_RTT_BUFFER_DOWN* pRing; + unsigned v; + + pRing = &_SEGGER_RTT.aDown[BufferIndex]; + v = pRing->WrOff; + return v - pRing->RdOff; +} + +/********************************************************************* +* +* SEGGER_RTT_HasDataUp +* +* Function description +* Check if there is data remaining to be sent in the given buffer. +* +* Return value: +* ==0: No data +* !=0: Data in buffer +* +*/ +unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned v; + + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + v = pRing->RdOff; + return pRing->WrOff - v; +} + +/********************************************************************* +* +* SEGGER_RTT_AllocDownBuffer +* +* Function description +* Run-time configuration of the next down-buffer (H->T). +* The next buffer, which is not used yet is configured. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. Buffer Index +* < 0 - Error +*/ +int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int BufferIndex; + + INIT(); + SEGGER_RTT_LOCK(); + BufferIndex = 0; + do { + if (_SEGGER_RTT.aDown[BufferIndex].pBuffer == NULL) { + break; + } + BufferIndex++; + } while (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers); + if (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers) { + _SEGGER_RTT.aDown[BufferIndex].sName = sName; + _SEGGER_RTT.aDown[BufferIndex].pBuffer = (char*)pBuffer; + _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aDown[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aDown[BufferIndex].WrOff = 0u; + _SEGGER_RTT.aDown[BufferIndex].Flags = Flags; + RTT__DMB(); + } else { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(); + return BufferIndex; +} + +/********************************************************************* +* +* SEGGER_RTT_AllocUpBuffer +* +* Function description +* Run-time configuration of the next up-buffer (T->H). +* The next buffer, which is not used yet is configured. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. Buffer Index +* < 0 - Error +*/ +int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int BufferIndex; + + INIT(); + SEGGER_RTT_LOCK(); + BufferIndex = 0; + do { + if (_SEGGER_RTT.aUp[BufferIndex].pBuffer == NULL) { + break; + } + BufferIndex++; + } while (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers); + if (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers) { + _SEGGER_RTT.aUp[BufferIndex].sName = sName; + _SEGGER_RTT.aUp[BufferIndex].pBuffer = (char*)pBuffer; + _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aUp[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aUp[BufferIndex].WrOff = 0u; + _SEGGER_RTT.aUp[BufferIndex].Flags = Flags; + RTT__DMB(); + } else { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(); + return BufferIndex; +} + +/********************************************************************* +* +* SEGGER_RTT_ConfigUpBuffer +* +* Function description +* Run-time configuration of a specific up-buffer (T->H). +* Buffer to be configured is specified by index. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* BufferIndex Index of the buffer to configure. +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. +* < 0 - Error +* +* Additional information +* Buffer 0 is configured on compile-time. +* May only be called once per buffer. +* Buffer name and flags can be reconfigured using the appropriate functions. +*/ +int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) { + SEGGER_RTT_LOCK(); + if (BufferIndex > 0u) { + _SEGGER_RTT.aUp[BufferIndex].sName = sName; + _SEGGER_RTT.aUp[BufferIndex].pBuffer = (char*)pBuffer; + _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aUp[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aUp[BufferIndex].WrOff = 0u; + } + _SEGGER_RTT.aUp[BufferIndex].Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_ConfigDownBuffer +* +* Function description +* Run-time configuration of a specific down-buffer (H->T). +* Buffer to be configured is specified by index. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* BufferIndex Index of the buffer to configure. +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 O.K. +* < 0 Error +* +* Additional information +* Buffer 0 is configured on compile-time. +* May only be called once per buffer. +* Buffer name and flags can be reconfigured using the appropriate functions. +*/ +int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) { + SEGGER_RTT_LOCK(); + if (BufferIndex > 0u) { + _SEGGER_RTT.aDown[BufferIndex].sName = sName; + _SEGGER_RTT.aDown[BufferIndex].pBuffer = (char*)pBuffer; + _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aDown[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aDown[BufferIndex].WrOff = 0u; + } + _SEGGER_RTT.aDown[BufferIndex].Flags = Flags; + RTT__DMB(); + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetNameUpBuffer +* +* Function description +* Run-time configuration of a specific up-buffer name (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* sName Pointer to a constant name string. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) { + SEGGER_RTT_LOCK(); + _SEGGER_RTT.aUp[BufferIndex].sName = sName; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetNameDownBuffer +* +* Function description +* Run-time configuration of a specific Down-buffer name (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* sName Pointer to a constant name string. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) { + SEGGER_RTT_LOCK(); + _SEGGER_RTT.aDown[BufferIndex].sName = sName; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetFlagsUpBuffer +* +* Function description +* Run-time configuration of specific up-buffer flags (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer. +* Flags Flags to set for the buffer. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) { + SEGGER_RTT_LOCK(); + _SEGGER_RTT.aUp[BufferIndex].Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetFlagsDownBuffer +* +* Function description +* Run-time configuration of specific Down-buffer flags (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* Flags Flags to set for the buffer. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) { + SEGGER_RTT_LOCK(); + _SEGGER_RTT.aDown[BufferIndex].Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_Init +* +* Function description +* Initializes the RTT Control Block. +* Should be used in RAM targets, at start of the application. +* +*/ +void SEGGER_RTT_Init (void) { + _DoInit(); +} + +/********************************************************************* +* +* SEGGER_RTT_SetTerminal +* +* Function description +* Sets the terminal to be used for output on channel 0. +* +* Parameters +* TerminalId Index of the terminal. +* +* Return value +* >= 0 O.K. +* < 0 Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id) +*/ +int SEGGER_RTT_SetTerminal (unsigned char TerminalId) { + unsigned char ac[2]; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + int r; + // + INIT(); + // + r = 0; + ac[0] = 0xFFu; + if (TerminalId < sizeof(_aTerminalId)) { // We only support a certain number of channels + ac[1] = _aTerminalId[TerminalId]; + pRing = &_SEGGER_RTT.aUp[0]; // Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed + SEGGER_RTT_LOCK(); // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing + if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { + _ActiveTerminal = TerminalId; + _WriteBlocking(pRing, (const char*)ac, 2u); + } else { // Skipping mode or trim mode? => We cannot trim this command so handling is the same for both modes + Avail = _GetAvailWriteSpace(pRing); + if (Avail >= 2) { + _ActiveTerminal = TerminalId; // Only change active terminal in case of success + _WriteNoCheck(pRing, (const char*)ac, 2u); + } else { + r = -1; + } + } + SEGGER_RTT_UNLOCK(); + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_TerminalOut +* +* Function description +* Writes a string to the given terminal +* without changing the terminal for channel 0. +* +* Parameters +* TerminalId Index of the terminal. +* s String to be printed on the terminal. +* +* Return value +* >= 0 - Number of bytes written. +* < 0 - Error. +* +*/ +int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s) { + int Status; + unsigned FragLen; + unsigned Avail; + SEGGER_RTT_BUFFER_UP* pRing; + // + INIT(); + // + // Validate terminal ID. + // + if (TerminalId < (char)sizeof(_aTerminalId)) { // We only support a certain number of channels + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[0]; + // + // Need to be able to change terminal, write data, change back. + // Compute the fixed and variable sizes. + // + FragLen = STRLEN(s); + // + // How we output depends upon the mode... + // + SEGGER_RTT_LOCK(); + Avail = _GetAvailWriteSpace(pRing); + switch (pRing->Flags & SEGGER_RTT_MODE_MASK) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother switching terminals at all. + // + if (Avail < (FragLen + 4u)) { + Status = 0; + } else { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode and there is not enough space for everything, + // trim the output but always include the terminal switch. If no room + // for terminal switch, skip that totally. + // + if (Avail < 4u) { + Status = -1; + } else { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, (FragLen < (Avail - 4u)) ? FragLen : (Avail - 4u)); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + break; + default: + Status = -1; + break; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + } else { + Status = -1; + } + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_GetAvailWriteSpace +* +* Function description +* Returns the number of bytes available in the ring buffer. +* +* Parameters +* BufferIndex Index of the up buffer. +* +* Return value +* Number of bytes that are free in the selected up buffer. +*/ +unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex){ + return _GetAvailWriteSpace(&_SEGGER_RTT.aUp[BufferIndex]); +} + + +/********************************************************************* +* +* SEGGER_RTT_GetBytesInBuffer() +* +* Function description +* Returns the number of bytes currently used in the up buffer. +* +* Parameters +* BufferIndex Index of the up buffer. +* +* Return value +* Number of bytes that are used in the buffer. +*/ +unsigned SEGGER_RTT_GetBytesInBuffer(unsigned BufferIndex) { + unsigned RdOff; + unsigned WrOff; + unsigned r; + // + // Avoid warnings regarding volatile access order. It's not a problem + // in this case, but dampen compiler enthusiasm. + // + RdOff = _SEGGER_RTT.aUp[BufferIndex].RdOff; + WrOff = _SEGGER_RTT.aUp[BufferIndex].WrOff; + if (RdOff <= WrOff) { + r = WrOff - RdOff; + } else { + r = _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer - (WrOff - RdOff); + } + return r; +} + +/*************************** End of file ****************************/ diff --git a/examples/knx-cc1310/RTT/SEGGER_RTT.h b/examples/knx-cc1310/RTT/SEGGER_RTT.h new file mode 100644 index 0000000..2e83f3f --- /dev/null +++ b/examples/knx-cc1310/RTT/SEGGER_RTT.h @@ -0,0 +1,372 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2019 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT.h +Purpose : Implementation of SEGGER real-time transfer which allows + real-time communication on targets which support debugger + memory accesses while the CPU is running. +Revision: $Rev: 20159 $ +---------------------------------------------------------------------- +*/ + +#ifndef SEGGER_RTT_H +#define SEGGER_RTT_H + +#include "SEGGER_RTT_Conf.h" + + + +/********************************************************************* +* +* Defines, defaults +* +********************************************************************** +*/ +#ifndef RTT_USE_ASM + #if (defined __SES_ARM) // SEGGER Embedded Studio + #define _CC_HAS_RTT_ASM_SUPPORT 1 + #elif (defined __CROSSWORKS_ARM) // Rowley Crossworks + #define _CC_HAS_RTT_ASM_SUPPORT 1 + #elif (defined __ARMCC_VERSION) + #define _CC_HAS_RTT_ASM_SUPPORT 0 + #elif (defined __GNUC__) // GCC + #define _CC_HAS_RTT_ASM_SUPPORT 1 + #elif (defined __clang__) // Clang compiler + #define _CC_HAS_RTT_ASM_SUPPORT 1 + #elif ((defined __IASMARM__) || (defined __ICCARM__)) // IAR assembler/compiler + #define _CC_HAS_RTT_ASM_SUPPORT 1 + #else + #define _CC_HAS_RTT_ASM_SUPPORT 0 + #endif + #if ((defined __IASMARM__) || (defined __ICCARM__)) // IAR assembler/compiler + // + // IAR assembler / compiler + // + #if (defined __ARM7M__) // Needed for old versions that do not know the define yet + #if (__CORE__ == __ARM7M__) // Cortex-M3 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #endif + #endif + #if (defined __ARM7EM__) // Needed for old versions that do not know the define yet + #if (__CORE__ == __ARM7EM__) // Cortex-M4/M7 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm("DMB"); + #endif + #endif + #if (defined __ARM8M_BASELINE__) // Needed for old versions that do not know the define yet + #if (__CORE__ == __ARM8M_BASELINE__) // Cortex-M23 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm("DMB"); + #endif + #endif + #if (defined __ARM8M_MAINLINE__) // Needed for old versions that do not know the define yet + #if (__CORE__ == __ARM8M_MAINLINE__) // Cortex-M33 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm("DMB"); + #endif + #endif + #else + // + // GCC / Clang + // + #if (defined __ARM_ARCH_7M__) // Cortex-M3 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #else + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #endif + #endif + // + // If IDE and core support the ASM version, enable ASM version by default + // + #ifndef _CORE_HAS_RTT_ASM_SUPPORT + #define _CORE_HAS_RTT_ASM_SUPPORT 0 // Default for unknown cores + #endif + #if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT) + #define RTT_USE_ASM (1) + #else + #define RTT_USE_ASM (0) + #endif +#endif + +// +// We need to know if a DMB is needed to make sure that on Cortex-M7 etc. +// the order of accesses to the ring buffers is guaranteed +// Needed for: Cortex-M7, Cortex-M23, Cortex-M33 +// +#ifndef _CORE_NEEDS_DMB + #define _CORE_NEEDS_DMB 0 +#endif + +#ifndef RTT__DMB + #if _CORE_NEEDS_DMB + #error "Don't know how to place inline assembly for DMB" + #else + #define RTT__DMB() + #endif +#endif + +#ifndef SEGGER_RTT_ASM // defined when SEGGER_RTT.h is included from assembly file +#include +#include + +/********************************************************************* +* +* Defines, fixed +* +********************************************************************** +*/ + +/********************************************************************* +* +* Types +* +********************************************************************** +*/ + +// +// Description for a circular buffer (also called "ring buffer") +// which is used as up-buffer (T->H) +// +typedef struct { + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + unsigned WrOff; // Position of next item to be written by either target. + volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. + unsigned Flags; // Contains configuration flags +} SEGGER_RTT_BUFFER_UP; + +// +// Description for a circular buffer (also called "ring buffer") +// which is used as down-buffer (H->T) +// +typedef struct { + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. + unsigned RdOff; // Position of next item to be read by target (down-buffer). + unsigned Flags; // Contains configuration flags +} SEGGER_RTT_BUFFER_DOWN; + +// +// RTT control block which describes the number of buffers available +// as well as the configuration for each buffer +// +// +typedef struct { + char acID[16]; // Initialized to "SEGGER RTT" + int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) + int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) + SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host + SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target +} SEGGER_RTT_CB; + +/********************************************************************* +* +* Global data +* +********************************************************************** +*/ +extern SEGGER_RTT_CB _SEGGER_RTT; + +/********************************************************************* +* +* RTT API functions +* +********************************************************************** +*/ +#ifdef __cplusplus + extern "C" { +#endif +int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_GetKey (void); +unsigned SEGGER_RTT_HasData (unsigned BufferIndex); +int SEGGER_RTT_HasKey (void); +unsigned SEGGER_RTT_HasDataUp (unsigned BufferIndex); +void SEGGER_RTT_Init (void); +unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); +unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); +int SEGGER_RTT_SetNameDownBuffer (unsigned BufferIndex, const char* sName); +int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName); +int SEGGER_RTT_SetFlagsDownBuffer (unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_SetFlagsUpBuffer (unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_WaitKey (void); +unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_ASM_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s); +void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_PutChar (unsigned BufferIndex, char c); +unsigned SEGGER_RTT_PutCharSkip (unsigned BufferIndex, char c); +unsigned SEGGER_RTT_PutCharSkipNoLock (unsigned BufferIndex, char c); +unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex); +unsigned SEGGER_RTT_GetBytesInBuffer (unsigned BufferIndex); +// +// Function macro for performance optimization +// +#define SEGGER_RTT_HASDATA(n) (_SEGGER_RTT.aDown[n].WrOff - _SEGGER_RTT.aDown[n].RdOff) + +#if RTT_USE_ASM + #define SEGGER_RTT_WriteSkipNoLock SEGGER_RTT_ASM_WriteSkipNoLock +#endif + +/********************************************************************* +* +* RTT transfer functions to send RTT data via other channels. +* +********************************************************************** +*/ +unsigned SEGGER_RTT_ReadUpBuffer (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); +unsigned SEGGER_RTT_ReadUpBufferNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); +unsigned SEGGER_RTT_WriteDownBuffer (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteDownBufferNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); + +#define SEGGER_RTT_HASDATA_UP(n) (_SEGGER_RTT.aUp[n].WrOff - _SEGGER_RTT.aUp[n].RdOff) + +/********************************************************************* +* +* RTT "Terminal" API functions +* +********************************************************************** +*/ +int SEGGER_RTT_SetTerminal (unsigned char TerminalId); +int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s); + +/********************************************************************* +* +* RTT printf functions (require SEGGER_RTT_printf.c) +* +********************************************************************** +*/ +int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...); +int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList); + +#ifdef __cplusplus + } +#endif + +#endif // ifndef(SEGGER_RTT_ASM) + +/********************************************************************* +* +* Defines +* +********************************************************************** +*/ + +// +// Operating modes. Define behavior if buffer is full (not enough space for entire message) +// +#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0) // Skip. Do not block, output nothing. (Default) +#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1) // Trim: Do not block, output as much as fits. +#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2) // Block: Wait until there is space in the buffer. +#define SEGGER_RTT_MODE_MASK (3) + +// +// Control sequences, based on ANSI. +// Can be used to control color, and clear the screen +// +#define RTT_CTRL_RESET "\x1B[0m" // Reset to default colors +#define RTT_CTRL_CLEAR "\x1B[2J" // Clear screen, reposition cursor to top left + +#define RTT_CTRL_TEXT_BLACK "\x1B[2;30m" +#define RTT_CTRL_TEXT_RED "\x1B[2;31m" +#define RTT_CTRL_TEXT_GREEN "\x1B[2;32m" +#define RTT_CTRL_TEXT_YELLOW "\x1B[2;33m" +#define RTT_CTRL_TEXT_BLUE "\x1B[2;34m" +#define RTT_CTRL_TEXT_MAGENTA "\x1B[2;35m" +#define RTT_CTRL_TEXT_CYAN "\x1B[2;36m" +#define RTT_CTRL_TEXT_WHITE "\x1B[2;37m" + +#define RTT_CTRL_TEXT_BRIGHT_BLACK "\x1B[1;30m" +#define RTT_CTRL_TEXT_BRIGHT_RED "\x1B[1;31m" +#define RTT_CTRL_TEXT_BRIGHT_GREEN "\x1B[1;32m" +#define RTT_CTRL_TEXT_BRIGHT_YELLOW "\x1B[1;33m" +#define RTT_CTRL_TEXT_BRIGHT_BLUE "\x1B[1;34m" +#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "\x1B[1;35m" +#define RTT_CTRL_TEXT_BRIGHT_CYAN "\x1B[1;36m" +#define RTT_CTRL_TEXT_BRIGHT_WHITE "\x1B[1;37m" + +#define RTT_CTRL_BG_BLACK "\x1B[24;40m" +#define RTT_CTRL_BG_RED "\x1B[24;41m" +#define RTT_CTRL_BG_GREEN "\x1B[24;42m" +#define RTT_CTRL_BG_YELLOW "\x1B[24;43m" +#define RTT_CTRL_BG_BLUE "\x1B[24;44m" +#define RTT_CTRL_BG_MAGENTA "\x1B[24;45m" +#define RTT_CTRL_BG_CYAN "\x1B[24;46m" +#define RTT_CTRL_BG_WHITE "\x1B[24;47m" + +#define RTT_CTRL_BG_BRIGHT_BLACK "\x1B[4;40m" +#define RTT_CTRL_BG_BRIGHT_RED "\x1B[4;41m" +#define RTT_CTRL_BG_BRIGHT_GREEN "\x1B[4;42m" +#define RTT_CTRL_BG_BRIGHT_YELLOW "\x1B[4;43m" +#define RTT_CTRL_BG_BRIGHT_BLUE "\x1B[4;44m" +#define RTT_CTRL_BG_BRIGHT_MAGENTA "\x1B[4;45m" +#define RTT_CTRL_BG_BRIGHT_CYAN "\x1B[4;46m" +#define RTT_CTRL_BG_BRIGHT_WHITE "\x1B[4;47m" + + +#endif + +/*************************** End of file ****************************/ diff --git a/examples/knx-cc1310/RTT/SEGGER_RTT_ASM_ARMv7M.S b/examples/knx-cc1310/RTT/SEGGER_RTT_ASM_ARMv7M.S new file mode 100644 index 0000000..3369132 --- /dev/null +++ b/examples/knx-cc1310/RTT/SEGGER_RTT_ASM_ARMv7M.S @@ -0,0 +1,241 @@ +/********************************************************************* +* (c) SEGGER Microcontroller GmbH * +* The Embedded Experts * +* www.segger.com * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : SEGGER_RTT_ASM_ARMv7M.S +Purpose : Assembler implementation of RTT functions for ARMv7M + +Additional information: + This module is written to be assembler-independent and works with + GCC and clang (Embedded Studio) and IAR. +*/ + +#define SEGGER_RTT_ASM // Used to control processed input from header file +#include "SEGGER_RTT.h" + +/********************************************************************* +* +* Defines, fixed +* +********************************************************************** +*/ +#define _CCIAR 0 +#define _CCCLANG 1 + +#if (defined __SES_ARM) || (defined __GNUC__) || (defined __clang__) + #define _CC_TYPE _CCCLANG + #define _PUB_SYM .global + #define _EXT_SYM .extern + #define _END .end + #define _WEAK .weak + #define _THUMB_FUNC .thumb_func + #define _THUMB_CODE .code 16 + #define _WORD .word + #define _SECTION(Sect, Type, AlignExp) .section Sect ##, "ax" + #define _ALIGN(Exp) .align Exp + #define _PLACE_LITS .ltorg + #define _DATA_SECT_START + #define _C_STARTUP _start + #define _STACK_END __stack_end__ + #define _RAMFUNC + // + // .text => Link to flash + // .fast => Link to RAM + // OtherSect => Usually link to RAM + // Alignment is 2^x + // +#elif defined (__IASMARM__) + #define _CC_TYPE _CCIAR + #define _PUB_SYM PUBLIC + #define _EXT_SYM EXTERN + #define _END END + #define _WEAK _WEAK + #define _THUMB_FUNC + #define _THUMB_CODE THUMB + #define _WORD DCD + #define _SECTION(Sect, Type, AlignExp) SECTION Sect ## : ## Type ## :REORDER:NOROOT ## (AlignExp) + #define _ALIGN(Exp) alignrom Exp + #define _PLACE_LITS + #define _DATA_SECT_START DATA + #define _C_STARTUP __iar_program_start + #define _STACK_END sfe(CSTACK) + #define _RAMFUNC SECTION_TYPE SHT_PROGBITS, SHF_WRITE | SHF_EXECINSTR + // + // .text => Link to flash + // .textrw => Link to RAM + // OtherSect => Usually link to RAM + // NOROOT => Allows linker to throw away the function, if not referenced + // Alignment is 2^x + // +#endif + +#if (_CC_TYPE == _CCIAR) + NAME SEGGER_RTT_ASM_ARMv7M +#else + .syntax unified +#endif + +#if defined (RTT_USE_ASM) && (RTT_USE_ASM == 1) + #define SHT_PROGBITS 0x1 + +/********************************************************************* +* +* Public / external symbols +* +********************************************************************** +*/ + + _EXT_SYM __aeabi_memcpy + _EXT_SYM __aeabi_memcpy4 + _EXT_SYM _SEGGER_RTT + + _PUB_SYM SEGGER_RTT_ASM_WriteSkipNoLock + +/********************************************************************* +* +* SEGGER_RTT_WriteSkipNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* SEGGER_RTT_WriteSkipNoLock does not lock the application and +* skips all data, if the data does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* MUST be > 0!!! +* This is done for performance reasons, so no initial check has do be done. +* +* Return value +* 1: Data has been copied +* 0: No space, data has not been copied +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, all data is dropped. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ + _SECTION(.text, CODE, 2) + _ALIGN(2) + _THUMB_FUNC +SEGGER_RTT_ASM_WriteSkipNoLock: // unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pData, unsigned NumBytes) { + // + // Cases: + // 1) RdOff <= WrOff => Space until wrap-around is sufficient + // 2) RdOff <= WrOff => Space after wrap-around needed (copy in 2 chunks) + // 3) RdOff < WrOff => No space in buf + // 4) RdOff > WrOff => Space is sufficient + // 5) RdOff > WrOff => No space in buf + // + // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough + // + // Register usage: + // R0 Temporary needed as RdOff, register later on + // R1 pData + // R2 + // R3 register. Hold free for subroutine calls + // R4 + // R5 pRing->pBuffer + // R6 pRing (Points to active struct SEGGER_RTT_BUFFER_DOWN) + // R7 WrOff + // + PUSH {R4-R7} + ADD R3,R0,R0, LSL #+1 + LDR.W R0,=_SEGGER_RTT // pRing = &_SEGGER_RTT.aUp[BufferIndex]; + ADD R0,R0,R3, LSL #+3 + ADD R6,R0,#+24 + LDR R0,[R6, #+16] // RdOff = pRing->RdOff; + LDR R7,[R6, #+12] // WrOff = pRing->WrOff; + LDR R5,[R6, #+4] // pRing->pBuffer + CMP R7,R0 + BCC.N _CheckCase4 // if (RdOff <= WrOff) { => Case 1), 2) or 3) + // + // Handling for case 1, later on identical to case 4 + // + LDR R3,[R6, #+8] // Avail = pRing->SizeOfBuffer - WrOff - 1u; => Space until wrap-around (assume 1 byte not usable for case that RdOff == 0) + SUBS R4,R3,R7 // (Used in case we jump into case 2 afterwards) + SUBS R3,R4,#+1 // + CMP R3,R2 + BCC.N _CheckCase2 // if (Avail >= NumBytes) { => Case 1)? +_Case4: + ADDS R5,R7,R5 // pBuffer += WrOff + ADDS R0,R2,R7 // v = WrOff + NumBytes + // + // 2x unrolling for the copy loop that is used most of the time + // This is a special optimization for small SystemView packets and makes them even faster + // + _ALIGN(2) +_LoopCopyStraight: // memcpy(pRing->pBuffer + WrOff, pData, NumBytes); + LDRB R3,[R1], #+1 + STRB R3,[R5], #+1 // *pDest++ = *pSrc++ + SUBS R2,R2,#+1 + BEQ _CSDone + LDRB R3,[R1], #+1 + STRB R3,[R5], #+1 // *pDest++ = *pSrc++ + SUBS R2,R2,#+1 + BNE _LoopCopyStraight +_CSDone: +#if _CORE_NEEDS_DMB // Do not slow down cores that do not need a DMB instruction here + DMB // Cortex-M7 may delay memory writes and also change the order in which the writes happen. Therefore, make sure that all buffer writes are finished, before updating the in the struct +#endif + STR R0,[R6, #+12] // pRing->WrOff = WrOff + NumBytes; + MOVS R0,#+1 + POP {R4-R7} + BX LR // Return 1 +_CheckCase2: + ADDS R0,R0,R3 // Avail += RdOff; => Space incl. wrap-around + CMP R0,R2 + BCC.N _Case3 // if (Avail >= NumBytes) { => Case 2? => If not, we have case 3) (does not fit) + // + // Handling for case 2 + // + ADDS R0,R7,R5 // v = pRing->pBuffer + WrOff => Do not change pRing->pBuffer here because 2nd chunk needs org. value + SUBS R2,R2,R4 // NumBytes -= Rem; (Rem = pRing->SizeOfBuffer - WrOff; => Space until end of buffer) +_LoopCopyBeforeWrapAround: // memcpy(pRing->pBuffer + WrOff, pData, Rem); => Copy 1st chunk + LDRB R3,[R1], #+1 + STRB R3,[R0], #+1 // *pDest++ = *pSrc++ + SUBS R4,R4,#+1 + BNE _LoopCopyBeforeWrapAround + // + // Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could not be used + // But 2nd check (considering space until wrap-around and until RdOff) revealed that RdOff is not 0, so we can use the last element + // In this case, we may use a copy straight until buffer end anyway without needing to copy 2 chunks + // Therefore, check if 2nd memcpy is necessary at all + // + ADDS R4,R2,#+0 // Save (needed as counter in loop but must be written to after the loop). Also use this inst to update the flags to skip 2nd loop if possible + BEQ.N _No2ChunkNeeded // if (NumBytes) { +_LoopCopyAfterWrapAround: // memcpy(pRing->pBuffer, pData + Rem, NumBytes); + LDRB R3,[R1], #+1 // pData already points to the next src byte due to copy loop increment before this loop + STRB R3,[R5], #+1 // *pDest++ = *pSrc++ + SUBS R2,R2,#+1 + BNE _LoopCopyAfterWrapAround +_No2ChunkNeeded: +#if _CORE_NEEDS_DMB // Do not slow down cores that do not need a DMB instruction here + DMB // Cortex-M7 may delay memory writes and also change the order in which the writes happen. Therefore, make sure that all buffer writes are finished, before updating the in the struct +#endif + STR R4,[R6, #+12] // pRing->WrOff = NumBytes; => Must be written after copying data because J-Link may read control block asynchronously while writing into buffer + MOVS R0,#+1 + POP {R4-R7} + BX LR // Return 1 +_CheckCase4: + SUBS R0,R0,R7 + SUBS R0,R0,#+1 // Avail = RdOff - WrOff - 1u; + CMP R0,R2 + BCS.N _Case4 // if (Avail >= NumBytes) { => Case 4) == 1) ? => If not, we have case 5) == 3) (does not fit) +_Case3: + MOVS R0,#+0 + POP {R4-R7} + BX LR // Return 0 + _PLACE_LITS + +#endif // defined (RTT_USE_ASM) && (RTT_USE_ASM == 1) + _END + +/*************************** End of file ****************************/ diff --git a/examples/knx-cc1310/RTT/SEGGER_RTT_Conf.h b/examples/knx-cc1310/RTT/SEGGER_RTT_Conf.h new file mode 100644 index 0000000..5e79d7e --- /dev/null +++ b/examples/knx-cc1310/RTT/SEGGER_RTT_Conf.h @@ -0,0 +1,384 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2019 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT_Conf.h +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 18601 $ + +*/ + +#ifndef SEGGER_RTT_CONF_H +#define SEGGER_RTT_CONF_H + +#ifdef __IAR_SYSTEMS_ICC__ + #include +#endif + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) +#endif + +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) +#endif + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) +#endif + +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE + #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) +#endif + +/********************************************************************* +* +* RTT memcpy configuration +* +* memcpy() is good for large amounts of data, +* but the overhead is big for small amounts, which are usually stored via RTT. +* With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. +* +* SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. +* This is may be required with memory access restrictions, +* such as on Cortex-A devices with MMU. +*/ +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP + #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop +#endif +// +// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets +// +//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) +// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) +//#endif + +// +// Target is not allowed to perform other RTT operations while string still has not been stored completely. +// Otherwise we would probably end up with a mixed string in the buffer. +// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. +// +// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. +// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. +// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. +// (Higher priority = lower priority number) +// Default value for embOS: 128u +// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC +// or define SEGGER_RTT_LOCK() to completely disable interrupts. +// +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) +#endif + +/********************************************************************* +* +* RTT lock configuration for SEGGER Embedded Studio, +* Rowley CrossStudio and GCC +*/ +#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) + #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + __asm volatile ("mrs %0, primask \n\t" \ + "movs r1, $1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (LockState) \ + : \ + : "r1" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (LockState) \ + : \ + ); \ + } + #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + __asm volatile ("mrs %0, basepri \n\t" \ + "mov r1, %1 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r" (LockState) \ + : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ + : "r1" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ + : \ + : "r" (LockState) \ + : \ + ); \ + } + + #elif defined(__ARM_ARCH_7A__) + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (LockState) \ + : \ + : "r1" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (LockState) \ + : "r0", "r1" \ + ); \ + } + #elif defined(__riscv) || defined(__riscv_xlen) + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + __asm volatile ("csrr %0, mstatus \n\t" \ + "csrci mstatus, 8 \n\t" \ + "andi %0, %0, 8 \n\t" \ + : "=r" (LockState) \ + : \ + : \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ + "or %0, %0, a1 \n\t" \ + "csrs mstatus, %0 \n\t" \ + : \ + : "r" (LockState) \ + : "a1" \ + ); \ + } + #else + #define SEGGER_RTT_LOCK() + #define SEGGER_RTT_UNLOCK() + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR EWARM +*/ +#ifdef __ICCARM__ + #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(LockState); \ + } + #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ + (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + LockState = __get_BASEPRI(); \ + __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() __set_BASEPRI(LockState); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR RX +*/ +#ifdef __ICCRX__ + #define SEGGER_RTT_LOCK() { \ + unsigned long LockState; \ + LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR RL78 +*/ +#ifdef __ICCRL78__ + #define SEGGER_RTT_LOCK() { \ + __istate_t LockState; \ + LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for KEIL ARM +*/ +#ifdef __CC_ARM + #if (defined __TARGET_ARCH_6S_M) + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + register unsigned char PRIMASK __asm( "primask"); \ + LockState = PRIMASK; \ + PRIMASK = 1u; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() PRIMASK = LockState; \ + __schedule_barrier(); \ + } + #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + register unsigned char BASEPRI __asm( "basepri"); \ + LockState = BASEPRI; \ + BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() BASEPRI = LockState; \ + __schedule_barrier(); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for TI ARM +*/ +#ifdef __TI_ARM__ + #if defined (__TI_ARM_V6M0__) + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(LockState); \ + } + #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(LockState); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for CCRX +*/ +#ifdef __RX + #define SEGGER_RTT_LOCK() { \ + unsigned long LockState; \ + LockState = get_psw() & 0x010000; \ + clrpsw_i(); + + #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for embOS Simulation on Windows +* (Can also be used for generic RTT locking with embOS) +*/ +#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) + +void OS_SIM_EnterCriticalSection(void); +void OS_SIM_LeaveCriticalSection(void); + +#define SEGGER_RTT_LOCK() { \ + OS_SIM_EnterCriticalSection(); + +#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration fallback +*/ +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) +#endif + +#endif +/*************************** End of file ****************************/ diff --git a/examples/knx-cc1310/RTT/SEGGER_RTT_Syscalls_GCC.c b/examples/knx-cc1310/RTT/SEGGER_RTT_Syscalls_GCC.c new file mode 100644 index 0000000..15307c7 --- /dev/null +++ b/examples/knx-cc1310/RTT/SEGGER_RTT_Syscalls_GCC.c @@ -0,0 +1,120 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2019 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT_Syscalls_GCC.c +Purpose : Low-level functions for using printf() via RTT in GCC. + To use RTT for printf output, include this file in your + application. +Revision: $Rev: 20159 $ +---------------------------------------------------------------------- +*/ +#if (defined __GNUC__) && !(defined __SES_ARM) && !(defined __CROSSWORKS_ARM) && !(defined __ARMCC_VERSION) && !(defined __CC_ARM) + +#include // required for _write_r +#include "SEGGER_RTT.h" + + +/********************************************************************* +* +* Types +* +********************************************************************** +*/ +// +// If necessary define the _reent struct +// to match the one passed by the used standard library. +// +struct _reent; + +/********************************************************************* +* +* Function prototypes +* +********************************************************************** +*/ +int _write(int file, char *ptr, int len); +int _write_r(struct _reent *r, int file, const void *ptr, size_t len); + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ + +/********************************************************************* +* +* _write() +* +* Function description +* Low-level write function. +* libc subroutines will use this system routine for output to all files, +* including stdout. +* Write data via RTT. +*/ +int _write(int file, char *ptr, int len) { + (void) file; /* Not used, avoid warning */ + SEGGER_RTT_Write(0, ptr, len); + return len; +} + +/********************************************************************* +* +* _write_r() +* +* Function description +* Low-level reentrant write function. +* libc subroutines will use this system routine for output to all files, +* including stdout. +* Write data via RTT. +*/ +int _write_r(struct _reent *r, int file, const void *ptr, size_t len) { + (void) file; /* Not used, avoid warning */ + (void) r; /* Not used, avoid warning */ + SEGGER_RTT_Write(0, ptr, len); + return len; +} + +#endif +/****** End Of File *************************************************/ diff --git a/examples/knx-cc1310/RTT/SEGGER_RTT_printf.c b/examples/knx-cc1310/RTT/SEGGER_RTT_printf.c new file mode 100644 index 0000000..4c996b4 --- /dev/null +++ b/examples/knx-cc1310/RTT/SEGGER_RTT_printf.c @@ -0,0 +1,500 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2019 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT_printf.c +Purpose : Replacement for printf to write formatted data via RTT +Revision: $Rev: 17697 $ +---------------------------------------------------------------------- +*/ +#include "SEGGER_RTT.h" +#include "SEGGER_RTT_Conf.h" + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE + #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64) +#endif + +#include +#include + + +#define FORMAT_FLAG_LEFT_JUSTIFY (1u << 0) +#define FORMAT_FLAG_PAD_ZERO (1u << 1) +#define FORMAT_FLAG_PRINT_SIGN (1u << 2) +#define FORMAT_FLAG_ALTERNATE (1u << 3) + +/********************************************************************* +* +* Types +* +********************************************************************** +*/ + +typedef struct { + char* pBuffer; + unsigned BufferSize; + unsigned Cnt; + + int ReturnValue; + + unsigned RTTBufferIndex; +} SEGGER_RTT_PRINTF_DESC; + +/********************************************************************* +* +* Function prototypes +* +********************************************************************** +*/ + +/********************************************************************* +* +* Static code +* +********************************************************************** +*/ +/********************************************************************* +* +* _StoreChar +*/ +static void _StoreChar(SEGGER_RTT_PRINTF_DESC * p, char c) { + unsigned Cnt; + + Cnt = p->Cnt; + if ((Cnt + 1u) <= p->BufferSize) { + *(p->pBuffer + Cnt) = c; + p->Cnt = Cnt + 1u; + p->ReturnValue++; + } + // + // Write part of string, when the buffer is full + // + if (p->Cnt == p->BufferSize) { + if (SEGGER_RTT_Write(p->RTTBufferIndex, p->pBuffer, p->Cnt) != p->Cnt) { + p->ReturnValue = -1; + } else { + p->Cnt = 0u; + } + } +} + +/********************************************************************* +* +* _PrintUnsigned +*/ +static void _PrintUnsigned(SEGGER_RTT_PRINTF_DESC * pBufferDesc, unsigned v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) { + static const char _aV2C[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; + unsigned Div; + unsigned Digit; + unsigned Number; + unsigned Width; + char c; + + Number = v; + Digit = 1u; + // + // Get actual field width + // + Width = 1u; + while (Number >= Base) { + Number = (Number / Base); + Width++; + } + if (NumDigits > Width) { + Width = NumDigits; + } + // + // Print leading chars if necessary + // + if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) { + if (FieldWidth != 0u) { + if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && (NumDigits == 0u)) { + c = '0'; + } else { + c = ' '; + } + while ((FieldWidth != 0u) && (Width < FieldWidth)) { + FieldWidth--; + _StoreChar(pBufferDesc, c); + if (pBufferDesc->ReturnValue < 0) { + break; + } + } + } + } + if (pBufferDesc->ReturnValue >= 0) { + // + // Compute Digit. + // Loop until Digit has the value of the highest digit required. + // Example: If the output is 345 (Base 10), loop 2 times until Digit is 100. + // + while (1) { + if (NumDigits > 1u) { // User specified a min number of digits to print? => Make sure we loop at least that often, before checking anything else (> 1 check avoids problems with NumDigits being signed / unsigned) + NumDigits--; + } else { + Div = v / Digit; + if (Div < Base) { // Is our divider big enough to extract the highest digit from value? => Done + break; + } + } + Digit *= Base; + } + // + // Output digits + // + do { + Div = v / Digit; + v -= Div * Digit; + _StoreChar(pBufferDesc, _aV2C[Div]); + if (pBufferDesc->ReturnValue < 0) { + break; + } + Digit /= Base; + } while (Digit); + // + // Print trailing spaces if necessary + // + if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == FORMAT_FLAG_LEFT_JUSTIFY) { + if (FieldWidth != 0u) { + while ((FieldWidth != 0u) && (Width < FieldWidth)) { + FieldWidth--; + _StoreChar(pBufferDesc, ' '); + if (pBufferDesc->ReturnValue < 0) { + break; + } + } + } + } + } +} + +/********************************************************************* +* +* _PrintInt +*/ +static void _PrintInt(SEGGER_RTT_PRINTF_DESC * pBufferDesc, int v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) { + unsigned Width; + int Number; + + Number = (v < 0) ? -v : v; + + // + // Get actual field width + // + Width = 1u; + while (Number >= (int)Base) { + Number = (Number / (int)Base); + Width++; + } + if (NumDigits > Width) { + Width = NumDigits; + } + if ((FieldWidth > 0u) && ((v < 0) || ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN))) { + FieldWidth--; + } + + // + // Print leading spaces if necessary + // + if ((((FormatFlags & FORMAT_FLAG_PAD_ZERO) == 0u) || (NumDigits != 0u)) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u)) { + if (FieldWidth != 0u) { + while ((FieldWidth != 0u) && (Width < FieldWidth)) { + FieldWidth--; + _StoreChar(pBufferDesc, ' '); + if (pBufferDesc->ReturnValue < 0) { + break; + } + } + } + } + // + // Print sign if necessary + // + if (pBufferDesc->ReturnValue >= 0) { + if (v < 0) { + v = -v; + _StoreChar(pBufferDesc, '-'); + } else if ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN) { + _StoreChar(pBufferDesc, '+'); + } else { + + } + if (pBufferDesc->ReturnValue >= 0) { + // + // Print leading zeros if necessary + // + if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) && (NumDigits == 0u)) { + if (FieldWidth != 0u) { + while ((FieldWidth != 0u) && (Width < FieldWidth)) { + FieldWidth--; + _StoreChar(pBufferDesc, '0'); + if (pBufferDesc->ReturnValue < 0) { + break; + } + } + } + } + if (pBufferDesc->ReturnValue >= 0) { + // + // Print number without sign + // + _PrintUnsigned(pBufferDesc, (unsigned)v, Base, NumDigits, FieldWidth, FormatFlags); + } + } + } +} + +/********************************************************************* +* +* Public code +* +********************************************************************** +*/ +/********************************************************************* +* +* SEGGER_RTT_vprintf +* +* Function description +* Stores a formatted string in SEGGER RTT control block. +* This data is read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used. (e.g. 0 for "Terminal") +* sFormat Pointer to format string +* pParamList Pointer to the list of arguments for the format string +* +* Return values +* >= 0: Number of bytes which have been stored in the "Up"-buffer. +* < 0: Error +*/ +int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList) { + char c; + SEGGER_RTT_PRINTF_DESC BufferDesc; + int v; + unsigned NumDigits; + unsigned FormatFlags; + unsigned FieldWidth; + char acBuffer[SEGGER_RTT_PRINTF_BUFFER_SIZE]; + + BufferDesc.pBuffer = acBuffer; + BufferDesc.BufferSize = SEGGER_RTT_PRINTF_BUFFER_SIZE; + BufferDesc.Cnt = 0u; + BufferDesc.RTTBufferIndex = BufferIndex; + BufferDesc.ReturnValue = 0; + + do { + c = *sFormat; + sFormat++; + if (c == 0u) { + break; + } + if (c == '%') { + // + // Filter out flags + // + FormatFlags = 0u; + v = 1; + do { + c = *sFormat; + switch (c) { + case '-': FormatFlags |= FORMAT_FLAG_LEFT_JUSTIFY; sFormat++; break; + case '0': FormatFlags |= FORMAT_FLAG_PAD_ZERO; sFormat++; break; + case '+': FormatFlags |= FORMAT_FLAG_PRINT_SIGN; sFormat++; break; + case '#': FormatFlags |= FORMAT_FLAG_ALTERNATE; sFormat++; break; + default: v = 0; break; + } + } while (v); + // + // filter out field with + // + FieldWidth = 0u; + do { + c = *sFormat; + if ((c < '0') || (c > '9')) { + break; + } + sFormat++; + FieldWidth = (FieldWidth * 10u) + ((unsigned)c - '0'); + } while (1); + + // + // Filter out precision (number of digits to display) + // + NumDigits = 0u; + c = *sFormat; + if (c == '.') { + sFormat++; + do { + c = *sFormat; + if ((c < '0') || (c > '9')) { + break; + } + sFormat++; + NumDigits = NumDigits * 10u + ((unsigned)c - '0'); + } while (1); + } + // + // Filter out length modifier + // + c = *sFormat; + do { + if ((c == 'l') || (c == 'h')) { + sFormat++; + c = *sFormat; + } else { + break; + } + } while (1); + // + // Handle specifiers + // + switch (c) { + case 'c': { + char c0; + v = va_arg(*pParamList, int); + c0 = (char)v; + _StoreChar(&BufferDesc, c0); + break; + } + case 'd': + v = va_arg(*pParamList, int); + _PrintInt(&BufferDesc, v, 10u, NumDigits, FieldWidth, FormatFlags); + break; + case 'u': + v = va_arg(*pParamList, int); + _PrintUnsigned(&BufferDesc, (unsigned)v, 10u, NumDigits, FieldWidth, FormatFlags); + break; + case 'x': + case 'X': + v = va_arg(*pParamList, int); + _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, NumDigits, FieldWidth, FormatFlags); + break; + case 's': + { + const char * s = va_arg(*pParamList, const char *); + do { + c = *s; + s++; + if (c == '\0') { + break; + } + _StoreChar(&BufferDesc, c); + } while (BufferDesc.ReturnValue >= 0); + } + break; + case 'p': + v = va_arg(*pParamList, int); + _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, 8u, 8u, 0u); + break; + case '%': + _StoreChar(&BufferDesc, '%'); + break; + default: + break; + } + sFormat++; + } else { + _StoreChar(&BufferDesc, c); + } + } while (BufferDesc.ReturnValue >= 0); + + if (BufferDesc.ReturnValue > 0) { + // + // Write remaining data, if any + // + if (BufferDesc.Cnt != 0u) { + SEGGER_RTT_Write(BufferIndex, acBuffer, BufferDesc.Cnt); + } + BufferDesc.ReturnValue += (int)BufferDesc.Cnt; + } + return BufferDesc.ReturnValue; +} + +/********************************************************************* +* +* SEGGER_RTT_printf +* +* Function description +* Stores a formatted string in SEGGER RTT control block. +* This data is read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used. (e.g. 0 for "Terminal") +* sFormat Pointer to format string, followed by the arguments for conversion +* +* Return values +* >= 0: Number of bytes which have been stored in the "Up"-buffer. +* < 0: Error +* +* Notes +* (1) Conversion specifications have following syntax: +* %[flags][FieldWidth][.Precision]ConversionSpecifier +* (2) Supported flags: +* -: Left justify within the field width +* +: Always print sign extension for signed conversions +* 0: Pad with 0 instead of spaces. Ignored when using '-'-flag or precision +* Supported conversion specifiers: +* c: Print the argument as one char +* d: Print the argument as a signed integer +* u: Print the argument as an unsigned integer +* x: Print the argument as an hexadecimal integer +* s: Print the string pointed to by the argument +* p: Print the argument as an 8-digit hexadecimal integer. (Argument shall be a pointer to void.) +*/ +int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...) { + int r; + va_list ParamList; + + va_start(ParamList, sFormat); + r = SEGGER_RTT_vprintf(BufferIndex, sFormat, &ParamList); + va_end(ParamList); + return r; +} +/*************************** End of file ****************************/ diff --git a/examples/knx-cc1310/build.sh b/examples/knx-cc1310/build.sh new file mode 100755 index 0000000..a327825 --- /dev/null +++ b/examples/knx-cc1310/build.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +[ -d build ] || mkdir build + +cd build + +#create Makefile +cmake -DCMAKE_BUILD_TYPE=Debug .. + +#Run make +cmake --build . -j4 diff --git a/examples/knx-cc1310/ccfg.c b/examples/knx-cc1310/ccfg.c new file mode 100644 index 0000000..399e626 --- /dev/null +++ b/examples/knx-cc1310/ccfg.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== ccfg.c ======== + * Customer Configuration for CC26xx and CC13xx devices. This file is used to + * configure Boot ROM, start-up code, and SW radio behaviour. + * + * By default, driverlib startup_files/ccfg.c settings are used. However, if + * changes are required there are two means to do so: + * + * 1. Remove this file and copy driverlib's startup_files/ccfg.c file in + * its place. Make all changes to the file. Changes made are local to + * the project and will not affect other projects. + * + * 2. Perform changes to driverlib startup_files/ccfg.c file. Changes + * made to this file will be applied to all projects. This file must + * remain unmodified. + */ + +/*---------------------------------------------------------------------------*/ +/** + * \name ROM Bootloader configuration + * + * Enable/Disable the ROM bootloader in your image, if the board supports it. + * Look in Board.h to choose the DIO and corresponding level that will cause + * the chip to enter bootloader mode. + * @{ + */ +#ifndef CCFG_CONF_ROM_BOOTLOADER_ENABLE +#define CCFG_CONF_ROM_BOOTLOADER_ENABLE 0 +#endif + +#if CCFG_CONF_ROM_BOOTLOADER_ENABLE +#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 +#define SET_CCFG_BL_CONFIG_BL_LEVEL 0x00 +#if defined(CCFG_CONF_BL_PIN_NUMBER) +#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER CCFG_CONF_BL_PIN_NUMBER +#endif +#define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 +#endif /* CCFG_CONF_ROM_BOOTLOADER_ENABLE */ +/** @} */ + +#include +#include DeviceFamily_constructPath(startup_files/ccfg.c) diff --git a/examples/knx-cc1310/cmake/FindSimpleLinkCC13X0SDKnortos.cmake b/examples/knx-cc1310/cmake/FindSimpleLinkCC13X0SDKnortos.cmake new file mode 100644 index 0000000..6570ff6 --- /dev/null +++ b/examples/knx-cc1310/cmake/FindSimpleLinkCC13X0SDKnortos.cmake @@ -0,0 +1,85 @@ +## Derived from this project: https://github.com/jobroe/cmake-arm-embedded +## +## MIT License +## +## Copyright (c) 2018 Johannes Bruder +## +## Permission is hereby granted, free of charge, to any person obtaining a copy +## of this software and associated documentation files (the "Software"), to deal +## in the Software without restriction, including without limitation the rights +## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +## copies of the Software, and to permit persons to whom the Software is +## furnished to do so, subject to the following conditions: +## +## The above copyright notice and this permission notice shall be included in all +## copies or substantial portions of the Software. +## +## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +## SOFTWARE. + +## +## Find TI's SimpleLink CC13X0 SDK +## + +include(FindPackageHandleStandardArgs) + +find_path(SimpleLinkCC13X0SDK_DEVICES_DIR NAMES "DeviceFamily.h" PATH_SUFFIXES "source/ti/devices") + +# Add suffix when looking for libraries +list(APPEND CMAKE_FIND_LIBRARY_SUFFIXES "am3g" "lib") + +# Find TI's drivers lib +find_library(SimpleLinkCC13X0SDK_drivers_cc13x0_LIBRARY + NAMES drivers_cc13x0.am3g + PATH_SUFFIXES "source/ti/drivers/lib" +) + +# Find cc13x0 radio single mode lib +find_library(SimpleLinkCC13X0SDK_rf_singleMode_cc13x0_LIBRARY + NAMES rf_singleMode_cc13x0.am3g + PATH_SUFFIXES "source/ti/drivers/rf/lib" +) + +# Find cc13x0 radio multi mode lib +find_library(SimpleLinkCC13X0SDK_rf_multiMode_cc13x0_LIBRARY + NAMES rf_multiMode_cc13x0.am3g + PATH_SUFFIXES "source/ti/drivers/rf/lib" +) + +# Find driver porting layer (NoRTOS) lib +find_library(SimpleLinkCC13X0SDK_dpl_cc13x0_LIBRARY + NAMES nortos_cc13x0.am3g + PATH_SUFFIXES "kernel/nortos/lib" +) + +# Find Driverlib +find_library(SimpleLinkCC13X0SDK_driverlib_LIBRARY + NAMES driverlib.lib + PATH_SUFFIXES "source/ti/devices/cc13x0/driverlib/bin/gcc" +) + +set(SimpleLinkCC13X0SDK_INCLUDE_DIRS + "${SimpleLinkCC13X0SDK_DEVICES_DIR}/../.." + "${SimpleLinkCC13X0SDK_DEVICES_DIR}/../../../kernel/nortos" +) + +# Handle arguments and set SimpleLinkCC13X0SDK_FOUND to TRUE if all listed variables are TRUE +find_package_handle_standard_args(SimpleLinkCC13X0SDK DEFAULT_MSG + SimpleLinkCC13X0SDK_drivers_cc13x0_LIBRARY + SimpleLinkCC13X0SDK_rf_singleMode_cc13x0_LIBRARY + SimpleLinkCC13X0SDK_dpl_cc13x0_LIBRARY + SimpleLinkCC13X0SDK_driverlib_LIBRARY + SimpleLinkCC13X0SDK_INCLUDE_DIRS +) + +set(SimpleLinkCC13X0SDK_LIBRARIES + ${SimpleLinkCC13X0SDK_drivers_cc13x0_LIBRARY} + ${SimpleLinkCC13X0SDK_rf_singleMode_cc13x0_LIBRARY} + ${SimpleLinkCC13X0SDK_dpl_cc13x0_LIBRARY} + ${SimpleLinkCC13X0SDK_driverlib_LIBRARY} +) diff --git a/examples/knx-cc1310/cmake/binutils-arm-none-eabi.cmake b/examples/knx-cc1310/cmake/binutils-arm-none-eabi.cmake new file mode 100644 index 0000000..39c4715 --- /dev/null +++ b/examples/knx-cc1310/cmake/binutils-arm-none-eabi.cmake @@ -0,0 +1,36 @@ +## +## Author: Johannes Bruder +## License: See LICENSE.TXT file included in the project +## +## CMake arm-none-eabi binutils integration and helper functions +## + + +#--------------------------------------------------------------------------------------- +# Set tools +#--------------------------------------------------------------------------------------- +set(CMAKE_OBJCOPY ${TOOLCHAIN_BIN_DIR}/${TOOLCHAIN}-objcopy${TOOLCHAIN_EXT}) +set(CMAKE_OBJDUMP ${TOOLCHAIN_BIN_DIR}/${TOOLCHAIN}-objdump${TOOLCHAIN_EXT}) +set(CMAKE_SIZE ${TOOLCHAIN_BIN_DIR}/${TOOLCHAIN}-size${TOOLCHAIN_EXT}) + + +#--------------------------------------------------------------------------------------- +# Prints the section sizes +#--------------------------------------------------------------------------------------- +function(print_section_sizes TARGET) + add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_SIZE} ${TARGET}) +endfunction() + +#--------------------------------------------------------------------------------------- +# Creates output in hex format +#--------------------------------------------------------------------------------------- +function(create_hex_output TARGET) + add_custom_target(${TARGET}.hex ALL DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Oihex ${TARGET} ${TARGET}.hex) +endfunction() + +#--------------------------------------------------------------------------------------- +# Creates output in binary format +#--------------------------------------------------------------------------------------- +function(create_bin_output TARGET) + add_custom_target(${TARGET}.bin ALL DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Obinary ${TARGET} ${TARGET}.bin) +endfunction() diff --git a/examples/knx-cc1310/cmake/cc13xx.cmake b/examples/knx-cc1310/cmake/cc13xx.cmake new file mode 100644 index 0000000..b8cf1ec --- /dev/null +++ b/examples/knx-cc1310/cmake/cc13xx.cmake @@ -0,0 +1,46 @@ +## Derived from this project: https://github.com/jobroe/cmake-arm-embedded +## +## MIT License +## +## Copyright (c) 2018 Johannes Bruder +## +## Permission is hereby granted, free of charge, to any person obtaining a copy +## of this software and associated documentation files (the "Software"), to deal +## in the Software without restriction, including without limitation the rights +## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +## copies of the Software, and to permit persons to whom the Software is +## furnished to do so, subject to the following conditions: +## +## The above copyright notice and this permission notice shall be included in all +## copies or substantial portions of the Software. +## +## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +## SOFTWARE. + +## +## CC13xx target specific CMake file +## + +if(NOT DEFINED LINKER_SCRIPT) + message(FATAL_ERROR "No linker script defined") +endif(NOT DEFINED LINKER_SCRIPT) +message("Linker script: ${LINKER_SCRIPT}") + +#--------------------------------------------------------------------------------------- +# Set target specific compiler/linker flags +#--------------------------------------------------------------------------------------- + +# Object build Options +set(OBJECT_GEN_FLAGS "-mcpu=cortex-m3") + +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${OBJECT_GEN_FLAGS}" CACHE INTERNAL "C Compiler options") +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${OBJECT_GEN_FLAGS}" CACHE INTERNAL "C++ Compiler options") +set(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} ${OBJECT_GEN_FLAGS}" CACHE INTERNAL "ASM Compiler options") + +# Linker flags +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -eresetISR -T${LINKER_SCRIPT} -nostartfiles" CACHE INTERNAL "Linker options") diff --git a/examples/knx-cc1310/cmake/toolchain-arm-none-eabi.cmake b/examples/knx-cc1310/cmake/toolchain-arm-none-eabi.cmake new file mode 100644 index 0000000..3a6ed6a --- /dev/null +++ b/examples/knx-cc1310/cmake/toolchain-arm-none-eabi.cmake @@ -0,0 +1,120 @@ +## Derived from this project: https://github.com/jobroe/cmake-arm-embedded +## +## MIT License +## +## Copyright (c) 2018 Johannes Bruder +## +## Permission is hereby granted, free of charge, to any person obtaining a copy +## of this software and associated documentation files (the "Software"), to deal +## in the Software without restriction, including without limitation the rights +## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +## copies of the Software, and to permit persons to whom the Software is +## furnished to do so, subject to the following conditions: +## +## The above copyright notice and this permission notice shall be included in all +## copies or substantial portions of the Software. +## +## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +## SOFTWARE. + +## +## CMake arm-none-eabi toolchain file +## + +# Target definition +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR ARM) + +#--------------------------------------------------------------------------------------- +# Set toolchain paths +#--------------------------------------------------------------------------------------- +set(TOOLCHAIN arm-none-eabi) +if(NOT DEFINED TOOLCHAIN_PREFIX) + if(CMAKE_HOST_SYSTEM_NAME STREQUAL Linux) + set(TOOLCHAIN_PREFIX "/usr") + elseif(CMAKE_HOST_SYSTEM_NAME STREQUAL Darwin) + set(TOOLCHAIN_PREFIX "/usr/local") + elseif(CMAKE_HOST_SYSTEM_NAME STREQUAL Windows) + message(STATUS "Please specify the TOOLCHAIN_PREFIX !\n For example: -DTOOLCHAIN_PREFIX=\"C:/Program Files/GNU Tools ARM Embedded\" ") + else() + set(TOOLCHAIN_PREFIX "/usr") + message(STATUS "No TOOLCHAIN_PREFIX specified, using default: " ${TOOLCHAIN_PREFIX}) + endif() +endif() +set(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_PREFIX}/bin) +set(TOOLCHAIN_INC_DIR ${TOOLCHAIN_PREFIX}/${TOOLCHAIN}/include) +set(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_PREFIX}/${TOOLCHAIN}/lib) + +# Set system depended extensions +if(WIN32) + set(TOOLCHAIN_EXT ".exe" ) +else() + set(TOOLCHAIN_EXT "" ) +endif() + +# Perform compiler test with static library +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) + +#--------------------------------------------------------------------------------------- +# Set compiler/linker flags +#--------------------------------------------------------------------------------------- + +# Object build options +# -O0 No optimizations, reduce compilation time and make debugging produce the expected results. +# -mthumb Generat thumb instructions. +# -fno-builtin Do not use built-in functions provided by GCC. +# -Wall Print only standard warnings, for all use Wextra +# -ffunction-sections Place each function item into its own section in the output file. +# -fdata-sections Place each data item into its own section in the output file. +# -fomit-frame-pointer Omit the frame pointer in functions that don’t need one. +# -mabi=aapcs Defines enums to be a variable sized type. +set(OBJECT_GEN_FLAGS "-O0 -mthumb -fno-builtin -Wall -ffunction-sections -fdata-sections -fomit-frame-pointer -mabi=aapcs") + +set(CMAKE_C_FLAGS "${OBJECT_GEN_FLAGS} -std=gnu99 " CACHE INTERNAL "C Compiler options") +set(CMAKE_CXX_FLAGS "${OBJECT_GEN_FLAGS} -std=c++11 -fno-threadsafe-statics -fno-rtti -fno-exceptions" CACHE INTERNAL "C++ Compiler options") +set(CMAKE_ASM_FLAGS "${OBJECT_GEN_FLAGS} -x assembler-with-cpp " CACHE INTERNAL "ASM Compiler options") + + +# -Wl,--gc-sections Perform the dead code elimination. +# --specs=nano.specs Link with newlib-nano. +# --specs=nosys.specs No syscalls, provide empty implementations for the POSIX system calls. +set(CMAKE_EXE_LINKER_FLAGS "-Wl,--gc-sections --specs=nano.specs --specs=nosys.specs -mthumb -mabi=aapcs -Wl,-Map=${CMAKE_PROJECT_NAME}.map" CACHE INTERNAL "Linker options") + +#--------------------------------------------------------------------------------------- +# Set debug/release build configuration Options +#--------------------------------------------------------------------------------------- + +# Options for DEBUG build +# -Og Enables optimizations that do not interfere with debugging. +# -g Produce debugging information in the operating system’s native format. +set(CMAKE_C_FLAGS_DEBUG "-Og -g -gstrict-dwarf" CACHE INTERNAL "C Compiler options for debug build type") +set(CMAKE_CXX_FLAGS_DEBUG "-Og -g -gstrict-dwarf" CACHE INTERNAL "C++ Compiler options for debug build type") +set(CMAKE_ASM_FLAGS_DEBUG "-g -gstrict-dwarf" CACHE INTERNAL "ASM Compiler options for debug build type") +set(CMAKE_EXE_LINKER_FLAGS_DEBUG "" CACHE INTERNAL "Linker options for debug build type") + +# Options for RELEASE build +# -Os Optimize for size. -Os enables all -O2 optimizations. +# -flto Runs the standard link-time optimizer. +set(CMAKE_C_FLAGS_RELEASE "-Os -flto" CACHE INTERNAL "C Compiler options for release build type") +set(CMAKE_CXX_FLAGS_RELEASE "-Os -flto" CACHE INTERNAL "C++ Compiler options for release build type") +set(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "ASM Compiler options for release build type") +set(CMAKE_EXE_LINKER_FLAGS_RELEASE "-flto" CACHE INTERNAL "Linker options for release build type") + + +#--------------------------------------------------------------------------------------- +# Set compilers +#--------------------------------------------------------------------------------------- +set(CMAKE_C_COMPILER ${TOOLCHAIN_BIN_DIR}/${TOOLCHAIN}-gcc${TOOLCHAIN_EXT} CACHE INTERNAL "C Compiler") +set(CMAKE_CXX_COMPILER ${TOOLCHAIN_BIN_DIR}/${TOOLCHAIN}-g++${TOOLCHAIN_EXT} CACHE INTERNAL "C++ Compiler") +set(CMAKE_ASM_COMPILER ${TOOLCHAIN_BIN_DIR}/${TOOLCHAIN}-gcc${TOOLCHAIN_EXT} CACHE INTERNAL "ASM Compiler") + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/LICENSE b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/LICENSE new file mode 100644 index 0000000..4b67fdf --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/LICENSE @@ -0,0 +1,31 @@ +BSD-3-Clause +------------------ +Copyright (c) 2018-2019, Texas Instruments Incorporated +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. + +Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution. + +Neither the name of Texas Instruments Incorporated nor the names of +its contributors may be used to endorse or promote products derived +from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/NoRTOS.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/NoRTOS.c new file mode 100644 index 0000000..f087ffc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/NoRTOS.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== NoRTOS.c ======== + */ + +#include +#include +#include + +#include "NoRTOS.h" + +/* + * ======== NoRTOS_getConfig ======== + */ +void NoRTOS_getConfig(NoRTOS_Config *cfg) +{ + cfg->idleCallback = SemaphoreP_defaultParams.callback; + cfg->clockTickPeriod = ClockP_tickPeriod; + cfg->swiIntNum = HwiP_swiPIntNum; +} + +/* + * ======== NoRTOS_config ======== + */ +void NoRTOS_setConfig(NoRTOS_Config *cfg) +{ + HwiP_disable(); + + SemaphoreP_defaultParams.callback = cfg->idleCallback; + ClockP_tickPeriod = cfg->clockTickPeriod; + HwiP_swiPIntNum = cfg->swiIntNum; +} + +/* + * ======== NoRTOS_start ======== + */ +void NoRTOS_start() +{ + HwiP_enable(); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/NoRTOS.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/NoRTOS.h new file mode 100644 index 0000000..e5ebebb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/NoRTOS.h @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file NoRTOS.h + * + * @brief NoRTOS framework module + * + * The NoRTOS header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * + * The NoRTOS framework module controls various aspects of the application's + * behavior with respect to the TI Driver interfaces that are used by the + * application. + * + * Some TI Drivers make use of an internal Clock module that offers timing + * services to the drivers, based on a Clock "tick" which operates at a + * frequency based on a configured period. This period can be configured + * per application requirements through the NoRTOS module, although the + * default setting might be required by certain TI Drivers that assume a + * certain Clock tick frequency. + * + * Some TI Drivers make use of an internal Swi (Software interrupt) module + * that offers a scheduling paradigm that lies between an application's + * 'main' thread and hardware interrupts. The internal Swi implementation + * utilizes a software-triggered-only hardware interrupt for achieving this + * mid-level scheduling paradigm. This hardware interrupt can be configured + * per application requirements through the NoRTOS module, although the + * default setting is likely what should be used. + * + * Some TI Drivers will "suspend" the application's operation until a certain + * event occurs. When an application is running in the NoRTOS framework + * there are no other "threads" to run when the 'main' thread becomes + * suspended, which in essence implies that the application has entered an + * 'idle' mode. An 'idle callback' function is called when this 'idle' mode + * has been entered. This callback function can be configured per the + * application requirements through the NoRTOS module, although the default + * setting is likely what should be used. + * + * # Usage # + * + * The NoRTOS module contains the following APIs: + * - NoRTOS_getConfig(): Retrieve the current NoRTOS configuration values. + * - NoRTOS_setConfig(): Set NoRTOS configuration values. + * - NoRTOS_start(): Enable NoRTOS system operation (required). + * + * ### NoRTOS Framework Configuration # + * + * The NoRTOS framework utilizes a few settings that the application should + * be able to control so as to accommodate the unique needs of the + * application or the system upon which the application runs. It is expected + * that the default values of these settings will suffice for the majority of + * applications using the NoRTOS framework. These default values should be + * of no concern to most applications since the aspects they control are + * internal to the TI Drivers' operation, but system requirements or other + * code that is being integrated with the application could require different + * values. The NoRTOS configuration functions offer this capability to the + * application. Please refer to the documentation for the NoRTOS_Config + * structure for details on each configuration element. + * + * ### Starting the NoRTOS framework operation # + * + * Realtime systems often require precise timing when enabling certain + * aspects of the system. If some part of the system is enabled too early + * then other parts of the system may not operate correctly. Certain system + * elements need to be setup and initialized before other elements will + * operate correctly. + * + * The NoRTOS_start() API allows the application to control when the system + * as a whole should be "started". NoRTOS_start() *must* be called for + * the system to start, and should be called after all TI Driver and + * peripheral initialization has been performed. + * + * ### Example usage # + * + * @code + * #include + + * int main(int argc, char *argv[]) + * { + * NoRTOS_Config cfg; + * + * // Get current values of all configuration settings + * NoRTOS_getConfig(&cfg); + * + * // Change config settings we want to change while leaving other + * // settings at their default values ... + * + * // Change system "tick" frequency to 10,000 Hz + * cfg.clockTickPeriod = 100; + * + * // Change interrupt used for Swi scheduling to 11 (SVCall) + * cfg.swiIntNum = 11; + * + * // Affect the changes + * NoRTOS_setConfig(&cfg); + * + * `perform board and driver initialization`; + * + * // Start NoRTOS + * NoRTOS_start(); + * + * // Call mainThread function + * mainThread(NULL); + * } + * @endcode + * + ******************************************************************************* + */ + +/*! + * @brief NoRTOS framework global configuration + * + * The NoRTOS_Config structure contains a set of values utilized by the + * NoRTOS framework. + * + * The NoRTOS_getConfig() API can be used to retrieve the current settings. + * When changing one or more of these settings, a NoRTOS_Config structure + * should first be populated with the current settings by calling + * NoRTOS_getConfig(), after which the particular setting(s) that needs to be + * changed should be set and given to the NoRTOS framework by calling + * NoRTOS_setConfig(). + */ +typedef struct _NoRTOS_Config { + /*! Function that is called when a TI Driver "suspends" its operation */ + void (*idleCallback)(void); + + /*! Period of the internal Clock module's periodic "tick" (microsecs) */ + uint32_t clockTickPeriod; + + /*! Hardware interrupt posted by software to achieve the Swi (Software + interrupt) scheduling paradigm */ + int swiIntNum; +} NoRTOS_Config; + +/*! + * @brief Function to retrieve current NoRTOS configuration values + * + * @param cfg Pointer to a NoRTOS_Config structure in which to store + * the current configuration values + */ +void NoRTOS_getConfig(NoRTOS_Config *cfg); + +/*! + * @brief Function to set or modify NoRTOS configuration values + * + * @param cfg Pointer to a NoRTOS_Config structure from which NoRTOS + * configuration values are set + */ +void NoRTOS_setConfig(NoRTOS_Config *cfg); + +/* + * @brief Function to call for enabling NoRTOS system operation + */ +void NoRTOS_start(); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/ClockPTimer_nortos.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/ClockPTimer_nortos.c new file mode 100644 index 0000000..ab59508 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/ClockPTimer_nortos.c @@ -0,0 +1,687 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ClockPTimer_nortos.c ======== + */ + +#include + +#include + +#include +#include +#include +#include + +#include "QueueP.h" +#include "TimerP.h" + +#define CPU_CLOCK_HZ ((uint32_t)48000000) +#define SYSTICK_FREQ 1000 + +typedef struct _ClockP_Module_State { + QueueP_Obj clockQ; + volatile uint32_t ticks; + SwiP_Struct swiStruct; + SwiP_Handle swi; + TimerP_Struct timerStruct; + TimerP_Handle timer; + volatile unsigned int numTickSkip; + uint32_t nextScheduledTick; + uint32_t maxSkippable; + bool inWorkFunc; + bool startDuringWorkFunc; + bool ticking; +} ClockP_Module_State; + +typedef struct _ClockP_Obj { + QueueP_Elem elem; + uint32_t timeout; + uint32_t currTimeout; + uint32_t period; + volatile bool active; + ClockP_Fxn fxn; + uintptr_t arg; +} ClockP_Obj; + +static ClockP_Module_State ClockP_module; +static bool ClockP_initialized = false; +static ClockP_Params ClockP_defaultParams = { + .startFlag = false, + .period = 0, + .arg = 0, +}; + + +/* + * Set the default clock period to 10 microseconds for CC13XX and + * CC26XX devices, 1 msec for all other devices. + */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) || \ + (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) +uint32_t ClockP_tickPeriod = 10; +#else +uint32_t ClockP_tickPeriod = 1000; +#endif + +void ClockP_workFuncDynamic(uintptr_t arg0, uintptr_t arg1); +void ClockP_doTick(); + +static void sleepTicks(uint32_t ticks); + +static TimerP_FreqHz timerFreq; +static uint32_t usecsPerTimerTick; + +/* + * ======== ClockP_Params_init ======== + */ +void ClockP_Params_init(ClockP_Params *params) +{ + /* structure copy */ + *params = ClockP_defaultParams; +} + +/* + * ======== ClockP_startup ======== + */ +void ClockP_startup(void) +{ + SwiP_Params swiParams; + TimerP_Params timerParams; + + if (!ClockP_initialized) { + QueueP_init(&ClockP_module.clockQ); + ClockP_module.ticks = 0; + ClockP_module.numTickSkip = 1; + ClockP_module.nextScheduledTick = 1; + ClockP_module.maxSkippable = 0; + ClockP_module.inWorkFunc = false; + ClockP_module.startDuringWorkFunc = false; + ClockP_module.ticking = false; + + SwiP_Params_init(&swiParams); + swiParams.priority = ~0; /* max priority */ + ClockP_module.swi = SwiP_construct(&ClockP_module.swiStruct, + (SwiP_Fxn)ClockP_workFuncDynamic, + &swiParams); + + TimerP_Params_init(&timerParams); + timerParams.period = ClockP_tickPeriod; + ClockP_module.timer = TimerP_construct(&ClockP_module.timerStruct, + (TimerP_Fxn)ClockP_doTick, + &timerParams); + + /* get the max ticks that can be skipped by the timer */ + ClockP_module.maxSkippable = TimerP_getMaxTicks(ClockP_module.timer); + + /* Used for ClockP_usleep() */ + TimerP_getFreq(ClockP_module.timer, &timerFreq); + usecsPerTimerTick = 1000000 / timerFreq.lo; + + ClockP_initialized = true; + } +} + +/* + * ======== ClockP_getTicks ======== + */ +uint32_t ClockP_getTicks(void) +{ + uint32_t ticks; + uintptr_t hwiKey; + + hwiKey = HwiP_disable(); + + /* do not ask Timer to save NOW */ + ticks = TimerP_getCurrentTick(ClockP_module.timer, false); + + HwiP_restore(hwiKey); + + return (ticks); +} + +/* + * ======== ClockP_getTicksUntilInterrupt ======== + */ +uint32_t ClockP_getTicksUntilInterrupt(void) +{ + uint32_t ticks; + uint32_t current; + uintptr_t key; + + key = HwiP_disable(); + + /* do not ask Timer to save NOW */ + current = TimerP_getCurrentTick(ClockP_module.timer, false); + + ticks = ClockP_module.nextScheduledTick - current; + + /* clamp value to zero if nextScheduledTick is less than current */ + if (ticks > ClockP_module.maxSkippable) { + ticks = 0; + } + + HwiP_restore(key); + + return (ticks); +} + +/* + * ======== ClockP_scheduleNextTick ======== + * Must be called with global interrupts disabled! + */ +void ClockP_scheduleNextTick(uint32_t deltaTicks, uint32_t absTick) +{ + /* now reprogram the timer for the new period and next interrupt */ + TimerP_setNextTick(ClockP_module.timer, deltaTicks); + + /* remember this */ + ClockP_module.numTickSkip = deltaTicks; + ClockP_module.nextScheduledTick = absTick; +} + +/* + * ======== ClockP_walkQueueDynamic ======== + * Walk the Clock Queue for TickMode_DYNAMIC, optionally servicing a + * specific tick + */ +uint32_t ClockP_walkQueueDynamic(bool service, uint32_t thisTick) +{ + uint32_t distance = ~0; + QueueP_Handle clockQ; + QueueP_Elem *elem; + ClockP_Obj *obj; + uint32_t delta; + + /* Traverse clock queue */ + clockQ = &ClockP_module.clockQ; + elem = (QueueP_Elem *)QueueP_head(clockQ); + + while (elem != (QueueP_Elem *)(clockQ)) { + + obj = (ClockP_Obj *)elem; + elem = (QueueP_Elem *)QueueP_next(elem); + + /* if the object is active ... */ + if (obj->active == true) { + + /* optionally service if tick matches timeout */ + if (service == true) { + + /* if this object is timing out update its state */ + if (obj->currTimeout == thisTick) { + + if (obj->period == 0) { /* oneshot? */ + /* mark object idle */ + obj->active = false; + } + else { /* periodic */ + /* refresh timeout */ + obj->currTimeout += obj->period; + } + + /* call handler */ + obj->fxn(obj->arg); + } + } + + /* if object still active update distance to soonest tick */ + if (obj->active == true) { + + delta = obj->currTimeout - thisTick; + + /* if this is the soonest tick update distance to soonest */ + if (delta < distance) { + distance = delta; + } + + } + } + } + + return (distance); +} + +/* + * ======== ClockP_workFuncDynamic ======== + * Service Clock Queue for TickMode_DYNAMIC + */ +void ClockP_workFuncDynamic(uintptr_t arg0, uintptr_t arg1) +{ + uint32_t distance; + uint32_t serviceTick, serviceDelta; + uint32_t ticksToService; + unsigned int skippable; + uint32_t nowTick, nowDelta, nextTick; + uintptr_t hwiKey; + + hwiKey = HwiP_disable(); + + /* get current tick count, signal Timer to save corresponding NOW info */ + nowTick = TimerP_getCurrentTick(ClockP_module.timer, true); + + /* set flags while actively servicing queue */ + ClockP_module.inWorkFunc = true; + ClockP_module.startDuringWorkFunc = false; + + /* determine first tick expiration to service (the anticipated next tick) */ + serviceTick = ClockP_module.nextScheduledTick; + ticksToService = nowTick - serviceTick; + + /* + * if now hasn't caught up to nextScheduledTick, + * a spurious interrupt has probably occurred. + * ignore for now... + */ + + serviceDelta = serviceTick - ClockP_module.ticks; + nowDelta = nowTick - ClockP_module.ticks; + if (serviceDelta > nowDelta) { + ClockP_module.inWorkFunc = false; + HwiP_restore(hwiKey); + return; + } + + HwiP_restore(hwiKey); + + distance = 0; + + /* walk queue until catch up to current tick count */ + while (ticksToService >= distance) { + serviceTick = serviceTick + distance; + ticksToService -= distance; + distance = ClockP_walkQueueDynamic(true, serviceTick); + } + + /* now determine next needed tick and setup timer for that tick ... */ + hwiKey = HwiP_disable(); + + /* if ClockP_start() during processing of Q, re-walk to update distance */ + if (ClockP_module.startDuringWorkFunc == true) { + distance = ClockP_walkQueueDynamic(false, serviceTick); + } + + /* if no active timeouts then skip the maximum supported by the timer */ + if (distance == ~0) { + skippable = ClockP_module.maxSkippable; + nextTick = serviceTick + skippable; + } + /* else, finalize how many ticks can skip */ + else { + skippable = distance - ticksToService; + if (skippable > ClockP_module.maxSkippable) { + skippable = ClockP_module.maxSkippable; + } + nextTick = serviceTick + skippable; + } + + /* reprogram timer for next expected tick */ + ClockP_scheduleNextTick(skippable, nextTick); + + ClockP_module.ticking = true; + ClockP_module.inWorkFunc = false; + ClockP_module.ticks = serviceTick; + + HwiP_restore(hwiKey); +} + +/* + * ======== ClockP_doTick ======== + */ +void ClockP_doTick() +{ + SwiP_post(ClockP_module.swi); +} + +/* + * ======== ClockP_construct ======== + */ +ClockP_Handle ClockP_construct(ClockP_Struct *handle, ClockP_Fxn fxn, + uint32_t timeout, ClockP_Params *params) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + if (handle == NULL) { + return NULL; + } + + ClockP_startup(); + + if (params == NULL) { + params = &ClockP_defaultParams; + } + + obj->period = params->period; + obj->timeout = timeout; + obj->fxn = fxn; + obj->arg = params->arg; + obj->active = false; + + /* + * Clock object is always placed on Clock work Q + */ + QueueP_put(&ClockP_module.clockQ, &obj->elem); + + if (params->startFlag) { + ClockP_start(obj); + } + + return ((ClockP_Handle)handle); +} + +/* + * ======== ClockP_add ======== + */ +void ClockP_add(ClockP_Struct *handle, ClockP_Fxn fxn, + uint32_t timeout, uintptr_t arg) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + obj->period = 0; + obj->timeout = timeout; + obj->fxn = fxn; + obj->arg = arg; + obj->active = false; + + /* + * Clock object is always placed on Clock work Q + */ + QueueP_put(&ClockP_module.clockQ, &obj->elem); +} + +/* + * ======== ClockP_create ======== + */ +ClockP_Handle ClockP_create(ClockP_Fxn clkFxn, uint32_t timeout, + ClockP_Params *params) +{ + ClockP_Handle handle; + + handle = (ClockP_Handle)malloc(sizeof(ClockP_Obj)); + + /* ClockP_construct will check handle for NULL, no need here */ + handle = ClockP_construct((ClockP_Struct *)handle, clkFxn, timeout, + params); + + return (handle); +} + +/* + * ======== ClockP_destruct ======== + */ +void ClockP_destruct(ClockP_Struct *clk) +{ + ClockP_Obj *obj = (ClockP_Obj *)clk; + uintptr_t key; + + key = HwiP_disable(); + QueueP_remove(&obj->elem); + HwiP_restore(key); +} + +/* + * ======== ClockP_delete ======== + */ +void ClockP_delete(ClockP_Handle handle) +{ + ClockP_destruct((ClockP_Struct *)handle); + + free(handle); +} + +/* + * ======== ClockP_start ======== + * Set the Clock object's currTimeout value and set its active flag + * to true. + */ +void ClockP_start(ClockP_Handle handle) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + uintptr_t key = HwiP_disable(); + + uint32_t nowTick, nowDelta; + uint32_t scheduledTick, scheduledDelta; + uint32_t remainingTicks; + bool objectServiced = false; + + /* now see if need this new timeout before next scheduled tick ... */ + /* wait till after first tick */ + if ((ClockP_module.ticking == true) && + /* if Clock is NOT currently processing its Q */ + (ClockP_module.inWorkFunc == false)) { + + /* + * get virtual current tick count, + * signal Timer to save corresponding NOW info + */ + nowTick = TimerP_getCurrentTick(ClockP_module.timer, true); + + nowDelta = nowTick - ClockP_module.ticks; + scheduledDelta = ClockP_module.nextScheduledTick - ClockP_module.ticks; + + if (nowDelta <= scheduledDelta) { + objectServiced = true; + + /* start new Clock object */ + obj->currTimeout = nowTick + obj->timeout; + obj->active = true; + + /* get the next scheduled tick */ + scheduledTick = ClockP_module.nextScheduledTick; + + /* how many ticks until scheduled tick? */ + remainingTicks = scheduledTick - nowTick; + + if (obj->timeout < remainingTicks) { + ClockP_scheduleNextTick(obj->timeout, obj->currTimeout); + } + } + } + + if (objectServiced == false) { + /* + * get virtual current tick count, + * DO NOT (!) signal Timer to save corresponding NOW info + */ + nowTick = ClockP_getTicks(); + + /* start new Clock object */ + obj->currTimeout = nowTick + obj->timeout; + obj->active = true; + + if (ClockP_module.inWorkFunc == true) { + ClockP_module.startDuringWorkFunc = true; + } + } + + HwiP_restore(key); +} + +/* + * ======== ClockP_stop ======== + * remove and clear Clock object's queue elem from clockQ + */ +void ClockP_stop(ClockP_Handle handle) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + obj->active = false; +} + +/* + * ======== ClockP_setTimeout ======== + */ +void ClockP_setTimeout(ClockP_Handle handle, uint32_t timeout) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + obj->timeout = timeout; +} + +/* + * ======== ClockP_getTimeout ======== + */ +uint32_t ClockP_getTimeout(ClockP_Handle handle) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + if (obj->active == true) { + return (obj->currTimeout - ClockP_getTicks()); + } + else { + return (obj->timeout); + } +} + +/* + * ======== ClockP_isActive ======== + */ +bool ClockP_isActive(ClockP_Handle handle) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + return (obj->active); +} + +/* + * ======== ClockP_getCpuFreq ======== + */ +void ClockP_getCpuFreq(ClockP_FreqHz *freq) +{ + freq->lo = (uint32_t)CPU_CLOCK_HZ; + freq->hi = 0; +} + +/* + * ======== ClockP_getSystemTickPeriod ======== + */ +uint32_t ClockP_getSystemTickPeriod(void) +{ + return (ClockP_tickPeriod); +} + +/* + * ======== ClockP_getSystemTicks ======== + */ +uint32_t ClockP_getSystemTicks(void) +{ + uint32_t ticks; + uintptr_t key; + + ClockP_startup(); + + key = HwiP_disable(); + + /* + * Needs to be called with interrupts disabled, at least for + * MSP432, where ticks is computed based on the number of timer + * counter rollovers and the value of the timer counter register. + */ + ticks = TimerP_getCurrentTick(ClockP_module.timer, false); + + HwiP_restore(key); + + return (ticks); +} + +/* + * ======== ClockP_sleep ======== + */ +void ClockP_sleep(uint32_t sec) +{ + uint64_t ticksToSleep; + + ClockP_startup(); + + ticksToSleep = ((uint64_t)sec * (uint64_t)1000000) / (uint64_t)ClockP_tickPeriod; + sleepTicks((uint32_t)ticksToSleep); +} + +/* + * ======== ClockP_usleep ======== + */ +void ClockP_usleep(uint32_t usec) +{ + uint64_t curTick, endTick; + uint32_t ticksToSleep; + + ClockP_startup(); + + curTick = TimerP_getCount64(ClockP_module.timer); + + /* Make sure we sleep at least one tick if usec > 0 */ + endTick = curTick + (usec + usecsPerTimerTick - 1) / usecsPerTimerTick; + + /* + * If usec > ClockP_tickPeriod, sleep for the appropriate number + * of clock ticks. + */ + if (usec >= ClockP_tickPeriod) { + ticksToSleep = usec / ClockP_tickPeriod; + sleepTicks(ticksToSleep); + } + + curTick = TimerP_getCount64(ClockP_module.timer); + while (curTick < endTick) { + curTick = TimerP_getCount64(ClockP_module.timer);; + } +} + +/* + * ======== ClockP_staticObjectSize ======== + * Internal function for testing that ClockP_Struct is large enough + * to hold ClockP object. + */ +size_t ClockP_staticObjectSize(void) +{ + return (sizeof(ClockP_Obj)); +} + +/* + * ======== sleepTicks ======== + * Sleep for a given number of ClockP ticks. + */ +static void sleepTicks(uint32_t ticks) +{ + SemaphoreP_Struct semStruct; + SemaphoreP_Handle sem; + + if (ticks > 0) { + /* + * Construct a semaphore with 0 count that will never be posted. + * We will timeout pending on this semaphore. + */ + sem = SemaphoreP_construct(&semStruct, 0, NULL); + SemaphoreP_pend(sem, ticks); + SemaphoreP_destruct(&semStruct); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/DebugP_nortos.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/DebugP_nortos.c new file mode 100644 index 0000000..595af6d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/DebugP_nortos.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2016-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== DebugP_nortos.c ======== + */ + +#include +#include + +/* + * ======== _DebugP_assert ======== + */ +void _DebugP_assert(int expression, const char *file, int line) +{ + if (!expression) + { + printf("ASSERT ERROR: line num %d: file %s\n\r",line, file); + while(1); + } +} +/* + * ======== DebugP_log0 ======== + */ +void DebugP_log0(const char *format) +{ + //printf(format); +} + +/* + * ======== DebugP_log1 ======== + */ +void DebugP_log1(const char *format, uintptr_t p1) +{ + //printf(format, p1); +} + +/* + * ======== DebugP_log2 ======== + */ +void DebugP_log2(const char *format, uintptr_t p1, uintptr_t p2) +{ + //printf(format, p1, p2); +} +/* + * ======== DebugP_log3 ======== + */ +void DebugP_log3(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3) +{ + //printf(format, p1, p2, p3); +} +/* + * ======== DebugP_log4 ======== + */ +void DebugP_log4(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3, uintptr_t p4) +{ + //printf(format, p1, p2, p3, p4); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/HwiPCC26XX_nortos.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/HwiPCC26XX_nortos.c new file mode 100644 index 0000000..fcfa4ff --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/HwiPCC26XX_nortos.c @@ -0,0 +1,385 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== HwiPCC26XX_nortos.c ======== + */ + +#include +#include + +#include +#include + +/* driverlib header files */ +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_cpu_scs.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/rom.h) + +typedef struct _HwiP_Obj { + uint32_t intNum; + HwiP_Fxn fxn; + uintptr_t arg; +} HwiP_Obj; + +typedef struct _Hwi_NVIC { + uint32_t RES_00; + uint32_t ICTR; + uint32_t RES_08; + uint32_t RES_0C; + uint32_t STCSR; + uint32_t STRVR; + uint32_t STCVR; + uint32_t STCALIB; + uint32_t RES_20[56]; + uint32_t ISER[8]; + uint32_t RES_120[24]; + uint32_t ICER[8]; + uint32_t RES_1A0[24]; + uint32_t ISPR[8]; + uint32_t RES_220[24]; + uint32_t ICPR[8]; + uint32_t RES_2A0[24]; + uint32_t IABR[8]; + uint32_t RES_320[56]; + uint8_t IPR[240]; + uint32_t RES_4F0[516]; + uint32_t CPUIDBR; + uint32_t ICSR; + uint32_t VTOR; + uint32_t AIRCR; + uint32_t SCR; + uint32_t CCR; + uint8_t SHPR[12]; + uint32_t SHCSR; + uint8_t MMFSR; + uint8_t BFSR; + uint16_t UFSR; + uint32_t HFSR; + uint32_t DFSR; + uint32_t MMAR; + uint32_t BFAR; + uint32_t AFSR; + uint32_t PFR0; + uint32_t PFR1; + uint32_t DFR0; + uint32_t AFR0; + uint32_t MMFR0; + uint32_t MMFR1; + uint32_t MMFR2; + uint32_t MMFR3; + uint32_t ISAR0; + uint32_t ISAR1; + uint32_t ISAR2; + uint32_t ISAR3; + uint32_t ISAR4; + uint32_t RES_D74[5]; + uint32_t CPACR; + uint32_t RES_D8C[93]; + uint32_t STI; + uint32_t RES_F04[12]; + uint32_t FPCCR; + uint32_t FPCAR; + uint32_t FPDSCR; + uint32_t MVFR0; + uint32_t MVFR1; + uint32_t RES_F48[34]; + uint32_t PID4; + uint32_t PID5; + uint32_t PID6; + uint32_t PID7; + uint32_t PID0; + uint32_t PID1; + uint32_t PID2; + uint32_t PID3; + uint32_t CID0; + uint32_t CID1; + uint32_t CID2; + uint32_t CID3; +} Hwi_NVIC; + +static Hwi_NVIC *Hwi_nvic = (Hwi_NVIC *)0xE000E000; + +static HwiP_Obj* HwiP_dispatchTable[NUM_INTERRUPTS] = { + 0 +}; + +int HwiP_swiPIntNum = INT_PENDSV; + + +/* + * ======== HwiP_enable ======== + */ +void HwiP_enable(void) +{ + IntMasterEnable(); +} + +/* + * ======== HwiP_disable ======== + */ +uintptr_t HwiP_disable(void) +{ + return (IntMasterDisable()); +} + +/* + * ======== HwiP_restore ======== + */ +void HwiP_restore(uintptr_t alreadyDisabled) +{ + if (!alreadyDisabled) { + IntMasterEnable(); + } +} + +/* + * ======== HwiP_clearInterrupt ======== + */ +void HwiP_clearInterrupt(int interruptNum) +{ + IntPendClear((uint32_t)interruptNum); +} + +/* + * ======== HwiP_destruct ======== + */ +void HwiP_destruct(HwiP_Struct *handle) +{ + HwiP_Obj *obj = (HwiP_Obj *)handle; + + IntDisable(obj->intNum); + IntUnregister(obj->intNum); +} + +/* + * ======== HwiP_delete ======== + */ +void HwiP_delete(HwiP_Handle handle) +{ + HwiP_destruct((HwiP_Struct *)handle); + + free(handle); +} + +/* + * ======== HwiP_disableInterrupt ======== + */ +void HwiP_disableInterrupt(int interruptNum) +{ + IntDisable((uint32_t)interruptNum); +} + +/* + * ======== HwiP_dispatch ======== + */ +static void HwiP_dispatch(void) +{ + /* Determine which interrupt has fired */ + uint32_t intNum = (Hwi_nvic->ICSR & 0x000000ff); + HwiP_Obj* obj = HwiP_dispatchTable[intNum]; + if (obj) { + (obj->fxn)(obj->arg); + } +} + +/* + * ======== HwiP_enableInterrupt ======== + */ +void HwiP_enableInterrupt(int interruptNum) +{ + IntEnable((uint32_t)interruptNum); +} + +/* + * ======== HwiP_construct ======== + */ +HwiP_Handle HwiP_construct(HwiP_Struct *handle, int interruptNum, + HwiP_Fxn hwiFxn, HwiP_Params *params) +{ + HwiP_Params defaultParams; + HwiP_Obj *obj = (HwiP_Obj *)handle; + + if (handle != NULL) { + if (params == NULL) { + params = &defaultParams; + HwiP_Params_init(&defaultParams); + } + + if ((params->priority & 0xFF) == 0xFF) { + /* SwiP_nortos.c uses INT_PRI_LEVEL7 as its scheduler */ + params->priority = INT_PRI_LEVEL6; + } + + if (interruptNum != HwiP_swiPIntNum && + params->priority == INT_PRI_LEVEL7) { + DebugP_log0("HwiP_construct: can't use reserved INT_PRI_LEVEL7"); + + handle = NULL; + } + else { + HwiP_dispatchTable[interruptNum] = obj; + obj->fxn = hwiFxn; + obj->arg = params->arg; + obj->intNum = (uint32_t)interruptNum; + + IntRegister((uint32_t)interruptNum, HwiP_dispatch); + IntPrioritySet((uint32_t)interruptNum, (uint8_t)params->priority); + + if (params->enableInt) { + IntEnable((uint32_t)interruptNum); + } + } + } + + return ((HwiP_Handle)handle); +} + +/* + * ======== HwiP_create ======== + */ +HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, HwiP_Params *params) +{ + HwiP_Handle handle; + HwiP_Handle retHandle; + + handle = (HwiP_Handle)malloc(sizeof(HwiP_Obj)); + + /* + * Even though HwiP_construct will check handle for NULL and not do + * anything, we should check it here so that we can know afterwards + * that construct failed with non-NULL pointer and that we need to + * free the handle. + */ + if (handle != NULL) { + retHandle = HwiP_construct((HwiP_Struct *)handle, interruptNum, hwiFxn, + params); + if (retHandle == NULL) { + free(handle); + handle = NULL; + } + } + + return (handle); +} + +/* + * ======== HwiP_Params_init ======== + */ +void HwiP_Params_init(HwiP_Params *params) +{ + if (params != NULL) { + params->arg = 0; + params->priority = (~0); + params->enableInt = true; + } +} + +/* + * ======== HwiP_plug ======== + */ +void HwiP_plug(int interruptNum, void *fxn) +{ + IntRegister((uint32_t)interruptNum, (void (*)(void))fxn); +} + +/* + * ======== HwiP_setFunc ======== + */ +void HwiP_setFunc(HwiP_Handle hwiP, HwiP_Fxn fxn, uintptr_t arg) +{ + HwiP_Obj *obj = (HwiP_Obj *)hwiP; + + uintptr_t key = HwiP_disable(); + + obj->fxn = fxn; + obj->arg = arg; + + HwiP_restore(key); +} + +/* + * ======== HwiP_post ======== + */ +void HwiP_post(int interruptNum) +{ + IntPendSet((uint32_t)interruptNum); +} + +/* + * ======== HwiP_inISR ======== + */ +bool HwiP_inISR(void) +{ + bool stat; + + if ((Hwi_nvic->ICSR & CPU_SCS_ICSR_VECTACTIVE_M) == 0) { + stat = false; + } + else { + stat = true; + } + + return (stat); +} + +/* + * ======== HwiP_inSwi ======== + */ +bool HwiP_inSwi(void) +{ + uint32_t intNum = Hwi_nvic->ICSR & 0x000000ff; + if (intNum == HwiP_swiPIntNum) { + /* Currently in a Swi */ + return (true); + } + + return (false); +} + +/* + * ======== HwiP_setPri ======== + */ +void HwiP_setPriority(int interruptNum, uint32_t priority) +{ + IntPrioritySet((uint32_t)interruptNum, (uint8_t)priority); +} + +/* + * ======== HwiP_staticObjectSize ======== + */ +size_t HwiP_staticObjectSize(void) +{ + return (sizeof(HwiP_Obj)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/MutexP_nortos.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/MutexP_nortos.c new file mode 100644 index 0000000..d5de176 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/MutexP_nortos.c @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2016-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== MutexP_nortos.c ======== + */ + +#include +#include + +#include +#include + +typedef struct _MutexP_Config { + uint32_t dummy; +} MutexP_Config; + +/* + * ======== MutexP_construct ======== + */ +MutexP_Handle MutexP_construct(MutexP_Struct *handle, MutexP_Params *params) +{ + return ((MutexP_Handle)handle); +} + +/* + * ======== MutexP_create ======== + */ +MutexP_Handle MutexP_create(MutexP_Params *params) +{ + MutexP_Config *pMutex; + + //dynamically allocating memory for the mutex struct + pMutex = (MutexP_Config *)malloc(sizeof(MutexP_Config)); + + pMutex = (MutexP_Config *)MutexP_construct((MutexP_Struct *)pMutex, params); + + return ((MutexP_Handle)pMutex); +} + +/* + * ======== MutexP_destruct ======== + */ +void MutexP_destruct(MutexP_Struct *handle) +{ +} + +/* + * ======== MutexP_delete ======== + */ +void MutexP_delete(MutexP_Handle handle) +{ + if (handle != NULL) { + MutexP_destruct((MutexP_Struct *)handle); + free(handle); + } +} + +/* + * ======== MutexP_lock ======== + */ +uintptr_t MutexP_lock(MutexP_Handle handle) +{ + return (0); +} + +/* + * ======== MutexP_Params_init ======== + */ +void MutexP_Params_init(MutexP_Params *params) +{ + return; +} + +/* + * ======== MutexP_unlock ======== + */ +void MutexP_unlock(MutexP_Handle handle, uintptr_t key) +{ + return; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/PowerCC26X2_nortos.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/PowerCC26X2_nortos.c new file mode 100644 index 0000000..659f849 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/PowerCC26X2_nortos.c @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC26X2_nortos.c ======== + */ + +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/osc.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/vims.h) + +extern PowerCC26X2_ModuleState PowerCC26X2_module; + +static uintptr_t PowerCC26X2_swiKey; + +/* + * ======== PowerCC26XX_standbyPolicy ======== + */ +void PowerCC26XX_standbyPolicy() +{ + bool justIdle = true; + uint32_t constraints; + uint32_t ticks, time; + uintptr_t key; + + /* disable interrupts */ + key = HwiP_disable(); + + /* + * Check if the Power policy has been disabled since we last checked. + * Since we're in this policy function already, the policy must have + * been enabled (with a valid policyFxn) when we were called, but + * could have been disbled to short-circuit this function. + * SemaphoreP_post() does this purposely (see comments in there). + */ + if (!PowerCC26X2_module.enablePolicy) { + HwiP_restore(key); + + return; + } + + /* check operating conditions, optimally choose DCDC versus GLDO */ + SysCtrl_DCDC_VoltageConditionalControl(); + + /* query the declared constraints */ + constraints = Power_getConstraintMask(); + + /* do quick check to see if only WFI allowed; if yes, do it now */ + if ((constraints & + ((1 << PowerCC26XX_DISALLOW_STANDBY) | + (1 << PowerCC26XX_DISALLOW_IDLE))) == + ((1 << PowerCC26XX_DISALLOW_STANDBY) | + (1 << PowerCC26XX_DISALLOW_IDLE))) { + PRCMSleep(); + } + /* + * check if any sleep modes are allowed for automatic activation + */ + else { + /* check if we are allowed to go to standby */ + if ((constraints & (1 << PowerCC26XX_DISALLOW_STANDBY)) == 0) { + /* + * Check how many ticks until the next scheduled wakeup. A value of + * zero indicates a wakeup will occur as the current Clock tick + * period expires; a very large value indicates a very large number + * of Clock tick periods will occur before the next scheduled + * wakeup. + */ + ticks = ClockP_getTicksUntilInterrupt(); + + /* convert ticks to usec */ + time = ticks * ClockP_tickPeriod; + + /* check if can go to STANDBY */ + if (time > Power_getTransitionLatency(PowerCC26XX_STANDBY, + Power_TOTAL)) { + + /* schedule the wakeup event */ + ticks -= PowerCC26X2_WAKEDELAYSTANDBY / ClockP_tickPeriod; + ClockP_setTimeout(ClockP_handle((ClockP_Struct *) + &PowerCC26X2_module.clockObj), ticks); + ClockP_start(ClockP_handle((ClockP_Struct *) + &PowerCC26X2_module.clockObj)); + + /* go to standby mode */ + Power_sleep(PowerCC26XX_STANDBY); + ClockP_stop(ClockP_handle((ClockP_Struct *) + &PowerCC26X2_module.clockObj)); + justIdle = false; + } + } + + /* idle if allowed */ + if (justIdle) { + + /* + * Power off the CPU domain; VIMS will power down if SYSBUS is + * powered down, and SYSBUS will power down if there are no + * dependencies + * NOTE: if radio driver is active it must force SYSBUS enable to + * allow access to the bus and SRAM + */ + if ((constraints & (1 << PowerCC26XX_DISALLOW_IDLE)) == 0) { + uint32_t modeVIMS; + /* 1. Get the current VIMS mode */ + do { + modeVIMS = VIMSModeGet(VIMS_BASE); + } while (modeVIMS == VIMS_MODE_CHANGING); + + /* 2. Configure flash to remain on in IDLE or not and keep + * VIMS powered on if it is configured as GPRAM + * 3. Always keep cache retention ON in IDLE + * 4. Turn off the CPU power domain + * 5. Ensure any possible outstanding AON writes complete + * 6. Enter IDLE + */ + if ((constraints & (1 << PowerCC26XX_NEED_FLASH_IN_IDLE)) || + (modeVIMS == VIMS_MODE_DISABLED)) { + SysCtrlIdle(VIMS_ON_BUS_ON_MODE); + } + else { + SysCtrlIdle(VIMS_ON_CPU_ON_MODE); + } + + /* 7. Make sure MCU and AON are in sync after wakeup */ + SysCtrlAonUpdate(); + } + else { + PRCMSleep(); + } + } + } + + /* re-enable interrupts */ + HwiP_restore(key); +} + +/* + * ======== PowerCC26XX_schedulerDisable ======== + */ +void PowerCC26XX_schedulerDisable() +{ + PowerCC26X2_swiKey = SwiP_disable(); +} + +/* + * ======== PowerCC26XX_schedulerRestore ======== + */ +void PowerCC26XX_schedulerRestore() +{ + SwiP_restore(PowerCC26X2_swiKey); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/PowerCC26XX_nortos.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/PowerCC26XX_nortos.c new file mode 100644 index 0000000..04d5013 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/PowerCC26XX_nortos.c @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC26XX_nortos.c ======== + */ + +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/osc.h) +#include DeviceFamily_constructPath(driverlib/aon_wuc.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/vims.h) + +extern PowerCC26XX_ModuleState PowerCC26XX_module; +extern const PowerCC26XX_Config PowerCC26XX_config; + +static uintptr_t PowerCC26XX_swiKey; + + +/* + * ======== PowerCC26XX_standbyPolicy ======== + */ +void PowerCC26XX_standbyPolicy() +{ + bool justIdle = true; + uint32_t constraints; + uint32_t ticks; + uint32_t time; + uintptr_t key; + + /* disable interrupts */ + key = HwiP_disable(); + + /* + * Check if the Power policy has been disabled since we last checked. + * Since we're in this policy function already, the policy must have + * been enabled (with a valid policyFxn) when we were called, but + * could have been disbled to short-circuit this function. + * SemaphoreP_post() does this purposely (see comments in there). + */ + if (!PowerCC26XX_module.enablePolicy) { + HwiP_restore(key); + + return; + } + + /* check operating conditions, optimally choose DCDC versus GLDO */ + SysCtrl_DCDC_VoltageConditionalControl(); + + /* query the declared constraints */ + constraints = Power_getConstraintMask(); + + /* do quick check to see if only WFI allowed; if yes, do it now */ + if ((constraints & + ((1 << PowerCC26XX_DISALLOW_STANDBY) | (1 << PowerCC26XX_DISALLOW_IDLE))) == + ((1 << PowerCC26XX_DISALLOW_STANDBY) | (1 << PowerCC26XX_DISALLOW_IDLE))) { + PRCMSleep(); + } + /* + * check if any sleep modes are allowed for automatic activation + */ + else { + /* check if we are allowed to go to standby */ + if ((constraints & (1 << PowerCC26XX_DISALLOW_STANDBY)) == 0) { + /* + * Check how many ticks until the next scheduled wakeup. A value of + * zero indicates a wakeup will occur as the current Clock tick + * period expires; a very large value indicates a very large number + * of Clock tick periods will occur before the next scheduled + * wakeup. + */ + ticks = ClockP_getTicksUntilInterrupt(); + + /* convert ticks to usec */ + time = ticks * ClockP_tickPeriod; + + /* check if can go to STANDBY */ + if (time > Power_getTransitionLatency(PowerCC26XX_STANDBY, Power_TOTAL)) { + + /* schedule the wakeup event */ + ticks -= PowerCC26XX_WAKEDELAYSTANDBY / ClockP_tickPeriod; + + if (PowerCC26XX_config.enableMaxStandbyDuration) { + /* Schedule an early wakeup if requested. */ + if (ticks > PowerCC26XX_config.maxStandbyDuration) { + ticks = PowerCC26XX_config.maxStandbyDuration; + } + } + + ClockP_setTimeout(ClockP_handle((ClockP_Struct *)&PowerCC26XX_module.clockObj), ticks); + ClockP_start(ClockP_handle((ClockP_Struct *)&PowerCC26XX_module.clockObj)); + + /* go to standby mode */ + Power_sleep(PowerCC26XX_STANDBY); + ClockP_stop(ClockP_handle((ClockP_Struct *)&PowerCC26XX_module.clockObj)); + justIdle = false; + } + } + + /* idle if allowed */ + if (justIdle) { + + /* + * Power off the CPU domain; VIMS will power down if SYSBUS is + * powered down, and SYSBUS will power down if there are no + * dependencies + * NOTE: if radio driver is active it must force SYSBUS enable to + * allow access to the bus and SRAM + */ + if ((constraints & (1 << PowerCC26XX_DISALLOW_IDLE)) == 0) { + uint32_t modeVIMS; + /* 1. Get the current VIMS mode */ + do { + modeVIMS = VIMSModeGet(VIMS_BASE); + } while (modeVIMS == VIMS_MODE_CHANGING); + + /* 2. Configure flash to remain on in IDLE or not and keep VIMS powered on if it is configured as GPRAM */ + if ((constraints & (1 << PowerCC26XX_NEED_FLASH_IN_IDLE)) || + (modeVIMS == VIMS_MODE_DISABLED)) { + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) |= PRCM_PDCTL1VIMS_ON; + } + else { + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) &= ~PRCM_PDCTL1VIMS_ON; + } + + /* 3. Always keep cache retention ON in IDLE */ + PRCMCacheRetentionEnable(); + /* 4. Turn off the CPU power domain */ + PRCMPowerDomainOff(PRCM_DOMAIN_CPU); + /* 5. Ensure any possible outstanding AON writes complete */ + SysCtrlAonSync(); + + /* 6. Enter IDLE */ + PRCMDeepSleep(); + + /* 7. Make sure MCU and AON are in sync after wakeup */ + SysCtrlAonUpdate(); + } + else { + PRCMSleep(); + } + } + } + + /* re-enable interrupts */ + HwiP_restore(key); +} + +/* + * ======== PowerCC26XX_schedulerDisable ======== + */ +void PowerCC26XX_schedulerDisable() +{ + PowerCC26XX_swiKey = SwiP_disable(); +} + +/* + * ======== PowerCC26XX_schedulerRestore ======== + */ +void PowerCC26XX_schedulerRestore() +{ + SwiP_restore(PowerCC26XX_swiKey); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/QueueP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/QueueP.h new file mode 100644 index 0000000..276c3d3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/QueueP.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== QueueP.h ======== + */ + +typedef struct _QueueP_Elem { + struct _QueueP_Elem *volatile next; + struct _QueueP_Elem *volatile prev; +} QueueP_Elem; + +typedef struct _QueueP_Obj { + QueueP_Elem elem; +} QueueP_Obj; + +typedef QueueP_Obj *QueueP_Handle; + +void QueueP_init(QueueP_Obj *obj); +uintptr_t QueueP_head(QueueP_Obj *obj); +uintptr_t QueueP_next(QueueP_Elem *qelem); +uintptr_t QueueP_prev(QueueP_Elem *qelem); +uintptr_t QueueP_get(QueueP_Obj *obj); +void QueueP_put(QueueP_Obj *obj, QueueP_Elem *elem); +void QueueP_remove(QueueP_Elem *qelem) ; +bool QueueP_empty(QueueP_Obj *obj); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/QueueP_nortos.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/QueueP_nortos.c new file mode 100644 index 0000000..95d6f50 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/QueueP_nortos.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== QueueP_nortos.c ======== + */ + +#include +#include "QueueP.h" + +/* + * ======== QueueP_init ======== + */ +void QueueP_init(QueueP_Obj *obj) +{ + obj->elem.next = obj->elem.prev = &(obj->elem); +} + +/* + * ======== QueueP_empty ======== + */ +bool QueueP_empty(QueueP_Obj *obj) +{ + return (obj->elem.next == &(obj->elem)); +} + +/* + * ======== QueueP_get ======== + */ +uintptr_t QueueP_get(QueueP_Obj *obj) +{ + QueueP_Elem *elem; + uintptr_t key; + + key = HwiP_disable(); + + elem = obj->elem.next; + + obj->elem.next = elem->next; + elem->next->prev = &(obj->elem); + + HwiP_restore(key); + + return ((uintptr_t)elem); + +} + +/* + * ======== QueueP_getTail ======== + */ +uintptr_t QueueP_getTail(QueueP_Obj *obj) +{ + QueueP_Elem *elem; + uintptr_t key; + + key = HwiP_disable(); + + elem = obj->elem.prev; + + obj->elem.prev = elem->prev; + elem->prev->next = &(obj->elem); + + HwiP_restore(key); + + return ((uintptr_t)elem); + +} + +/* + * ======== QueueP_head ======== + */ +uintptr_t QueueP_head(QueueP_Obj *obj) +{ + return ((uintptr_t)(obj->elem.next)); +} + +/* + * ======== elemClear ======== + */ +void QueueP_elemClear(QueueP_Elem *qelem) +{ + qelem->next = qelem->prev = qelem; +} + +/* + * ======== insert ======== + */ +void QueueP_insert(QueueP_Elem *qelem, QueueP_Elem *elem) +{ + QueueP_put((QueueP_Obj *)qelem, elem); +} + +/* + * ======== next ======== + */ +uintptr_t QueueP_next(QueueP_Elem *qelem) +{ + return ((uintptr_t)qelem->next); +} + +/* + * ======== QueueP_prev ======== + */ +uintptr_t QueueP_prev(QueueP_Elem *qelem) +{ + return ((uintptr_t)qelem->prev); +} + +/* + * ======== QueueP_put ======== + */ +void QueueP_put(QueueP_Obj *obj, QueueP_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->next = &(obj->elem); + elem->prev = obj->elem.prev; + obj->elem.prev->next = elem; + obj->elem.prev = elem; + + HwiP_restore(key); +} + +/* + * ======== QueueP_putHead ======== + */ +void QueueP_putHead(QueueP_Obj *obj, QueueP_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->prev = &(obj->elem); + elem->next = obj->elem.next; + obj->elem.next->prev = elem; + obj->elem.next = elem; + + HwiP_restore(key); +} + +/* + * ======== QueueP_remove ======== + */ +void QueueP_remove(QueueP_Elem *qelem) +{ +#if defined(__IAR_SYSTEMS_ICC__) + QueueP_Elem *temp; + temp = qelem->next; + qelem->prev->next = temp; + temp = qelem->prev; + qelem->next->prev = temp; +#else + qelem->prev->next = qelem->next; + qelem->next->prev = qelem->prev; +#endif +} + +/* + * ======== isQueued ======== + */ +bool QueueP_isQueued(QueueP_Elem *qelem) +{ + if ((qelem->prev == qelem) && (qelem->next == qelem)) { + return (false); + } + else { + return (true); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/SemaphoreP_nortos.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/SemaphoreP_nortos.c new file mode 100644 index 0000000..ef662d6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/SemaphoreP_nortos.c @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2016-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== SemaphoreP_nortos.c ======== + */ + +#include +#include + +#include +#include +#include +#include + +#define MAXCOUNT 0xffff + + +typedef struct _SemaphoreP_Obj { + SemaphoreP_Params params; + uint32_t maxCount; + volatile uint32_t count; +} SemaphoreP_Obj; + +static bool pendInProgress = false; +static bool doEnablePolicy = false; +static bool SemaphoreP_initialized = false; + +SemaphoreP_Params SemaphoreP_defaultParams = { + .mode = SemaphoreP_Mode_COUNTING, + .callback = Power_idleFunc, +}; + +extern void ClockP_startup(void); +extern void ClockP_add(ClockP_Struct *handle, ClockP_Fxn fxn, + uint32_t timeout, uintptr_t arg); + +/* + * ClockP objects need a fxn, but we don't need to do anything in the fxn + * since we just use the Clock_isActive status to determine if it's still + * running or not. + */ +void clkFxn(uintptr_t arg) +{ +} + +/* + * ======== SemaphoreP_construct ======== + */ +SemaphoreP_Handle SemaphoreP_construct(SemaphoreP_Struct *handle, + unsigned int count, SemaphoreP_Params *params) +{ + SemaphoreP_Obj *pSemaphore = (SemaphoreP_Obj *)handle; + + if (!SemaphoreP_initialized) { + ClockP_startup(); + + SemaphoreP_initialized = true; + } + + if (handle != NULL) { + if (params == NULL) { + params = &(pSemaphore->params); + SemaphoreP_Params_init(params); + } + else { + pSemaphore->params.mode = params->mode; + pSemaphore->params.callback = params->callback; + } + + /* check if the semaphore is binary or counting */ + if (params->mode == SemaphoreP_Mode_COUNTING) { + pSemaphore->count = count; + pSemaphore->maxCount = MAXCOUNT; + } + else { + pSemaphore->maxCount = 1; + if (count != 0) { + pSemaphore->count = 1; + } + else { + pSemaphore->count = 0; + } + } + } + + return ((SemaphoreP_Handle)handle); +} + +/* + * ======== SemaphoreP_constructBinary ======== + */ +SemaphoreP_Handle SemaphoreP_constructBinary(SemaphoreP_Struct *handle, + unsigned int count) +{ + SemaphoreP_Params params; + + SemaphoreP_Params_init(¶ms); + params.mode = SemaphoreP_Mode_BINARY; + + return (SemaphoreP_construct(handle, count, ¶ms)); +} + +/* + * ======== SemaphoreP_create ======== + */ +SemaphoreP_Handle SemaphoreP_create(unsigned int count, + SemaphoreP_Params *params) +{ + SemaphoreP_Handle handle; + + handle = (SemaphoreP_Handle)malloc(sizeof(SemaphoreP_Obj)); + + /* SemaphoreP_construct will check handle for NULL, no need here */ + handle = SemaphoreP_construct((SemaphoreP_Struct *)handle, count, params); + + return (handle); +} + +/* + * ======== SemaphoreP_createBinary ======== + */ +SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count) +{ + SemaphoreP_Params params; + + SemaphoreP_Params_init(¶ms); + params.mode = SemaphoreP_Mode_BINARY; + + return (SemaphoreP_create(count, ¶ms)); +} + +/* + * ======== SemaphoreP_createBinaryCallback ======== + */ +SemaphoreP_Handle SemaphoreP_createBinaryCallback(unsigned int count, + void (*callback)(void)) +{ + SemaphoreP_Params params; + + SemaphoreP_Params_init(¶ms); + params.mode = SemaphoreP_Mode_BINARY; + params.callback = callback; + + return (SemaphoreP_create(count, ¶ms)); +} + +/* + * ======== SemaphoreP_destruct ======== + */ +void SemaphoreP_destruct(SemaphoreP_Struct *handle) +{ +} + +/* + * ======== SemaphoreP_delete ======== + */ +void SemaphoreP_delete(SemaphoreP_Handle handle) +{ + SemaphoreP_destruct((SemaphoreP_Struct *)handle); + + free(handle); +} + +/* + * ======== SemaphoreP_Params_init ======== + */ +void SemaphoreP_Params_init(SemaphoreP_Params *params) +{ + *params = SemaphoreP_defaultParams; +} + +/* + * ======== SemaphoreP_pend ======== + */ +SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout) +{ + SemaphoreP_Obj *pSemaphore = (SemaphoreP_Obj *)handle; + SemaphoreP_Status status; + ClockP_Struct clockStruct; + uintptr_t key; + + /* + * Always add Clock (but don't start) so that ClockP_isActive() below + * is valid. It's OK to add a Clock even when timeout is 0 or forever + * (but it is not OK to start it). + */ + ClockP_add(&clockStruct, clkFxn, timeout, (uintptr_t)NULL); + + if ((timeout != 0) && (timeout != SemaphoreP_WAIT_FOREVER)) { + ClockP_start((ClockP_Handle)&clockStruct); + } + + key = HwiP_disable(); + + pendInProgress = true; + + while ((pSemaphore->count == 0) && + ((timeout == SemaphoreP_WAIT_FOREVER) || + ClockP_isActive((ClockP_Handle)&clockStruct))) { + + HwiP_restore(key); + + /* Call the registered callback */ + if (pSemaphore->params.callback != NULL) { + pSemaphore->params.callback(); + } + + if (doEnablePolicy) { + Power_enablePolicy(); + doEnablePolicy = false; + } + + key = HwiP_disable(); + } + + pendInProgress = false; + + if (pSemaphore->count > 0) { + (pSemaphore->count)--; + status = SemaphoreP_OK; + } + else { + status = SemaphoreP_TIMEOUT; + } + + HwiP_restore(key); + + ClockP_destruct(&clockStruct); + + return (status); +} + +/* + * ======== SemaphoreP_post ======== + */ +void SemaphoreP_post(SemaphoreP_Handle handle) +{ + SemaphoreP_Obj *pSemaphore = (SemaphoreP_Obj *)handle; + uintptr_t key; + + key = HwiP_disable(); + + if (pSemaphore->count < pSemaphore->maxCount) { + (pSemaphore->count)++; + } + + if (HwiP_inISR() && pendInProgress && !doEnablePolicy) { + /* short-circuit potential policy invocation */ + doEnablePolicy = Power_disablePolicy(); + } + + HwiP_restore(key); +} + +/* + * ======== SemaphoreP_staticObjectSize ======== + * Internal function used by DPL tests to check that SemaphoreP_Struct + * is large enough to hold OS SemaphoreP object. + */ +size_t SemaphoreP_staticObjectSize(void) +{ + return (sizeof(SemaphoreP_Obj)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/SwiP_nortos.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/SwiP_nortos.c new file mode 100644 index 0000000..a908e7d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/SwiP_nortos.c @@ -0,0 +1,461 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== SwiP_nortos.c ======== + */ + +#include +#include +#include +#include + +#include +#include + +#include "QueueP.h" + +/* Lowest priority interrupt */ +#define INT_PRI_LEVEL7 0xe0 + +#define NUMPRI 4 + +typedef enum { + SwiP_State_Idle = 0, + SwiP_State_Posted, + SwiP_State_Running, + SwiP_State_Interrupted +} SwiP_State; + +typedef uint32_t SwiP_LockState; + +enum { + SwiP_LockState_Locked, + SwiP_LockState_Unlocked +}; + +typedef struct SwiP_Obj { + QueueP_Elem elem; + QueueP_Handle readyList; + SwiP_Params params; + SwiP_Fxn fxn; + uint32_t trigger; + uint32_t state; +} SwiP_Obj; + + +extern bool HwiP_inSwi(void); + +static void SwiP_handleHwi(); + +static const SwiP_Params SwiP_defaultParams = { + .arg0 = (uintptr_t) NULL, + .arg1 = (uintptr_t) NULL, + .priority = ~0, /* max priority */ + .trigger = 0, +}; + +static volatile int SwiP_readyMask; +static volatile SwiP_LockState SwiP_lockState; +static volatile uint32_t SwiP_currentTrigger; +static volatile bool SwiP_schedulerRunning; +static volatile bool SwiP_initialized = false; +static HwiP_Struct SwiP_hwiStruct; +static QueueP_Obj SwiP_readyList[NUMPRI]; + +/* don't call with n == 0 */ +static int maxbit(int n) +{ + int mask = 1 << (NUMPRI - 1); + int max = NUMPRI - 1; + + while (mask) { + if (n & mask) { + return max; + } + max--; + mask >>= 1; + } + + return 0; +} + +/* + * ======== SwiP_Params_init ======== + */ +void SwiP_Params_init(SwiP_Params *params) +{ + /* structure copy */ + *params = SwiP_defaultParams; +} + +/* + * ======== SwiP_construct ======== + */ +SwiP_Handle SwiP_construct(SwiP_Struct *handle, SwiP_Fxn swiFxn, + SwiP_Params *params) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + HwiP_Params hwiParams; + uintptr_t hwiKey; + uint32_t priority; + int i; + + if (handle != NULL) { + hwiKey = HwiP_disable(); + + if (SwiP_initialized == false) { + for (i = 0; i < NUMPRI; i++) { + QueueP_init(&SwiP_readyList[i]); + } + SwiP_readyMask = 0; + SwiP_currentTrigger = 0; + SwiP_lockState = SwiP_LockState_Unlocked; + SwiP_schedulerRunning = false; + + HwiP_Params_init(&hwiParams); + hwiParams.priority = INT_PRI_LEVEL7; // use the lowest priority + HwiP_construct(&SwiP_hwiStruct, HwiP_swiPIntNum, SwiP_handleHwi, + &hwiParams); + + SwiP_initialized = true; + } + + HwiP_restore(hwiKey); + + if (params == NULL) { + params = (SwiP_Params *)&SwiP_defaultParams; + } + + if (params->priority == (~0)) { + priority = NUMPRI - 1; + } + else { + priority = params->priority; + } + + if (priority >= NUMPRI) { + return NULL; + } + else { + QueueP_init((QueueP_Obj *)&swi->elem); + swi->params = *params; + swi->params.priority = priority; + swi->fxn = swiFxn; + swi->trigger = swi->params.trigger; + swi->state = SwiP_State_Idle; + swi->readyList = &SwiP_readyList[priority]; + } + } + + return ((SwiP_Handle)swi); +} + +/* + * ======== SwiP_create ======== + */ +SwiP_Handle SwiP_create(SwiP_Fxn swiFxn, SwiP_Params *params) +{ + SwiP_Handle handle; + SwiP_Handle retHandle; + + handle = (SwiP_Handle)malloc(sizeof(SwiP_Obj)); + + /* + * Even though SwiP_construct will check handle for NULL and not do + * anything, we should check it here so that we can know afterwards + * that construct failed with non-NULL pointer and that we need to + * free the handle. + */ + if (handle != NULL) { + retHandle = SwiP_construct((SwiP_Struct *)handle, swiFxn, params); + if (retHandle == NULL) { + free(handle); + handle = NULL; + } + } + + return (handle); +} + +/* + * ======== SwiP_destruct ======== + */ +void SwiP_destruct(SwiP_Struct *handle) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + uintptr_t hwiKey = HwiP_disable(); + + /* if on SwiP_readyList, remove it */ + QueueP_remove(&swi->elem); + if (QueueP_empty(swi->readyList)) { + SwiP_readyMask &= ~(1 << swi->params.priority); + } + + HwiP_restore(hwiKey); +} + +/* + * ======== SwiP_delete ======== + */ +void SwiP_delete(SwiP_Handle handle) +{ + SwiP_destruct((SwiP_Struct *)handle); + + free(handle); +} + +/* + * ======== SwiP_disable ======== + */ +uintptr_t SwiP_disable(void) +{ + uintptr_t previousHwiState = HwiP_disable(); + + SwiP_LockState previousLockState = SwiP_lockState; + SwiP_lockState = SwiP_LockState_Locked; + + HwiP_restore(previousHwiState); + + return previousLockState; +} + +/* + * This is a non-preemptive fixed-priority scheduler implementation. + * It runs with interrupts disabled, but enables them for each swi. + */ +void SwiP_dispatch(uintptr_t hwiKey) +{ + SwiP_Obj *swi; + int maxpri; + + while (SwiP_readyMask && (SwiP_lockState == SwiP_LockState_Unlocked)) { + maxpri = maxbit(SwiP_readyMask); + swi = (SwiP_Obj *)QueueP_get(&SwiP_readyList[maxpri]); + + if (QueueP_empty(&SwiP_readyList[maxpri])) { + SwiP_readyMask &= ~(1 << maxpri); + } + + /* + * Prepare the swi for execution. The trigger has to be saved + * because the swi might re-post itself with another trigger value. + */ + swi->state = SwiP_State_Running; + SwiP_currentTrigger = swi->trigger; + swi->trigger = swi->params.trigger; + + /* run the swi with interrupts enabled */ + HwiP_restore(hwiKey); + swi->fxn(swi->params.arg0, swi->params.arg1); + hwiKey = HwiP_disable(); + + /* If the swi didn't get re-posted, set it to idle now */ + if (swi->state == SwiP_State_Running) { + swi->state = SwiP_State_Idle; + } + } + + /* Scheduler was set to running immediately after posting the interrupt */ + SwiP_schedulerRunning = false; +} + +static void SwiP_handleHwi() +{ + uintptr_t hwiKey = HwiP_disable(); + + SwiP_dispatch(hwiKey); + + HwiP_restore(hwiKey); +} + +/* + * ======== SwiP_getTrigger ======== + */ +uint32_t SwiP_getTrigger() +{ + return (SwiP_currentTrigger); +} + +/* + * ======== SwiP_andn ======== + */ +void SwiP_andn(SwiP_Handle handle, uint32_t mask) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + uintptr_t hwiKey = HwiP_disable(); + + if (swi->trigger != 0) { + swi->trigger &= ~mask; + if (swi->trigger == 0) { + HwiP_restore(hwiKey); + SwiP_post(swi); + + return; + } + } + + HwiP_restore(hwiKey); +} + +/* + * ======== SwiP_dec ======== + */ +void SwiP_dec(SwiP_Handle handle) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + uintptr_t hwiKey = HwiP_disable(); + + if (swi->trigger != 0) { + swi->trigger -= 1; + if (swi->trigger == 0) { + HwiP_restore(hwiKey); + SwiP_post(swi); + + return; + } + } + + HwiP_restore(hwiKey); +} + +/* + * ======== SwiP_inc ======== + */ +void SwiP_inc(SwiP_Handle handle) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + uintptr_t hwiKey = HwiP_disable(); + + swi->trigger += 1; + + HwiP_restore(hwiKey); + SwiP_post(swi); +} + + +/* + * ======== SwiP_inISR ======== + */ +bool SwiP_inISR(void) +{ + return (HwiP_inSwi()); +} + +/* + * ======== SwiP_or ======== + */ +void SwiP_or(SwiP_Handle handle, uint32_t mask) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + uintptr_t hwiKey = HwiP_disable(); + + swi->trigger |= mask; + + HwiP_restore(hwiKey); + SwiP_post(swi); +} + +/* + * ======== SwiP_post ======== + */ +void SwiP_post(SwiP_Handle handle) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + uintptr_t hwiKey = HwiP_disable(); + + /* (Re-)post an swi only once */ + if (swi->state != SwiP_State_Posted) { + swi->state = SwiP_State_Posted; + + QueueP_put(&SwiP_readyList[swi->params.priority], + (QueueP_Elem *)&swi->elem); + SwiP_readyMask |= 1 << swi->params.priority; + } + + /* Activate the scheduler when not already running */ + if ((SwiP_schedulerRunning == false) && + (SwiP_lockState == SwiP_LockState_Unlocked)) { + HwiP_post(HwiP_swiPIntNum); + /* Set the scheduler into running state to avoid double posts */ + SwiP_schedulerRunning = true; + } + + HwiP_restore(hwiKey); +} + +/* + * ======== SwiP_restore ======== + */ +void SwiP_restore(uintptr_t key) +{ + uintptr_t hwiKey = HwiP_disable(); + + SwiP_lockState = key; + + /* Determine whether the scheduler needs to run */ + if (SwiP_readyMask && (key == SwiP_LockState_Unlocked) && + (SwiP_schedulerRunning == false)) { + HwiP_post(HwiP_swiPIntNum); + /* Set the scheduler into running state to avoid double posts */ + SwiP_schedulerRunning = true; + } + + HwiP_restore(hwiKey); +} + +/* + * ======== SwiP_setPriority ======== + */ +void SwiP_setPriority(SwiP_Handle handle, uint32_t priority) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + + if (priority == (~0)) { + priority = NUMPRI - 1; /* map ~0 to maxpri */ + } + + if (priority >= NUMPRI) { + return; /* noop, don't change the priority to bogus value */ + } + + swi->params.priority = priority; + + swi->readyList = &SwiP_readyList[priority]; +} + +/* + * ======== SwiP_staticObjectSize ======== + */ +size_t SwiP_staticObjectSize(void) +{ + return (sizeof(SwiP_Obj)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/SystemP_nortos.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/SystemP_nortos.c new file mode 100644 index 0000000..dc6e06f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/SystemP_nortos.c @@ -0,0 +1,416 @@ +/* + * Copyright (c) 2016-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== SystemP_nortos.c ======== + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* ----------------------------------------------------------------------------- + * Constants and macros + * ----------------------------------------------------------------------------- + */ +#ifndef MIN +# define MIN(n, m) (((n) > (m)) ? (m) : (n)) +#endif + +/* + * ======== OUTMAX ======== + * The maximum length of the output of a base 8 number produced by formatNum + * plus 5 to accomodate the decimal point and 4 digits after the decimal + * point. + */ +#define OUTMAX ((32 + 2) / 3 + 5) +#define PTRZPAD 8 +#define MAXARGS 5 + +/* ---------------------------------------------------------------------------- + * Type definitions + * ---------------------------------------------------------------------------- + */ +/* ParseData */ +typedef struct ParseData { + int width; + bool lFlag; + bool lJust; + int precis; + int len; + int zpad; + char *end; + char *ptr; +} ParseData; + +/* + * Maximum sized (un)signed integer that we'll format. + */ +typedef uint32_t UIntMax; +typedef int32_t IntMax; + +static int doPrint(char *buf, size_t n, const char *fmt, va_list va); +static char *formatNum(char *ptr, UIntMax un, int zpad, int base); +static void putChar(char **bufp, char c, size_t *n); + +/* + * ======== SystemP_snprintf ======== + */ +int SystemP_snprintf(char *buf, size_t n, const char *format,...) +{ + va_list args; + int ret; + + va_start(args, format); + ret = doPrint(buf, n, format, args); + va_end(args); + + return (ret); +} + +/* + * ======== SystemP_snprintf_va ======== + */ +int SystemP_vsnprintf(char *buf, size_t n, const char *format, + va_list va) +{ + int ret; + + ret = doPrint(buf, n, format, va); + return (ret); +} + +/* + * ======== doPrint ======== + */ +static int doPrint(char *buf, size_t n, const char *fmt, va_list va) +{ + ParseData parse; + int base; + char c; + int res = 0; + char outbuf[OUTMAX]; + + if (fmt == (char *)NULL) { + return (res); + } + + while ((c = *fmt++) != '\0') { + if (c != '%') { + putChar(&buf, c, &n); + res++; + } + else { + c = *fmt++; + /* check for - flag (pad on right) */ + if (c == '-') { + parse.lJust = true; + c = *fmt++; + } + else { + parse.lJust = false; + } + /* check for leading 0 pad */ + if (c == '0') { + parse.zpad = 1; + c = *fmt++; + } + else { + parse.zpad = 0; + } + + /* allow optional field width/precision specification */ + parse.width = 0; + parse.precis = -1; + + /* note: dont use isdigit (very large for C30) */ + if (c == '*') { + /* Width is specified in argument, not in format string */ + parse.width = (int)va_arg(va, int); + + c = *fmt++; + if (parse.width < 0) { + parse.lJust = true; + parse.width = -parse.width; + } + } + else { + while (c >= '0' && c <= '9') { + parse.width = parse.width * 10 + c - '0'; + c = *fmt++; + } + } + + /* allow optional field precision specification */ + if (c == '.') { + parse.precis = 0; + c = *fmt++; + if (c == '*') { + /* Width specified in argument, not in format string */ + parse.precis = (int)va_arg(va, int); + + if (parse.precis < 0) { + parse.precis = 0; + } + c = *fmt++; + } + else { + while (c >= '0' && c <= '9') { + parse.precis = parse.precis * 10 + c - '0'; + c = *fmt++; + } + } + } + + /* setup for leading zero padding */ + if (parse.zpad) { + parse.zpad = parse.width; + } + + /* check for presence of l flag (e.g., %ld) */ + if (c == 'l' || c == 'L') { + parse.lFlag = true; + c = *fmt++; + } + else { + parse.lFlag = false; + } + + parse.ptr = outbuf; + parse.end = outbuf + OUTMAX; + parse.len = 0; + + if (c == 'd' || c == 'i') { + /* signed decimal */ + IntMax val = (IntMax)va_arg(va, int32_t); + + if (parse.precis > parse.zpad) { + parse.zpad = parse.precis; + } + parse.ptr = formatNum(parse.end, val, parse.zpad, -10); + parse.len = parse.end - parse.ptr; + } + /* use comma operator to optimize code generation! */ + else if (((base = 10), (c == 'u')) || /* unsigned decimal */ + ((base = 16), (c == 'x')) || /* unsigned hex */ + ((base = 8), (c == 'o'))) { /* unsigned octal */ + + UIntMax val = (UIntMax)va_arg(va, uint32_t); + + if (parse.precis > parse.zpad) { + parse.zpad = parse.precis; + } + parse.ptr = formatNum(parse.end, val, parse.zpad, base); + parse.len = parse.end - parse.ptr; + } + else if ((base = 16), (c == 'p')) { + parse.zpad = PTRZPAD; /* ptrs are 0 padded */ + parse.ptr = formatNum( + parse.end, + (UIntMax)va_arg(va, uint32_t), + parse.zpad, base); + *(--parse.ptr) = '@'; + parse.len = parse.end - parse.ptr; + } + else if (c == 'c') { + /* character */ + *parse.ptr = (char)va_arg(va, int); + parse.len = 1; + } + else if (c == 's') { + /* string */ + parse.ptr = (char *)va_arg(va, void *); + + /* substitute (null) for NULL pointer */ + if (parse.ptr == (char *)NULL) { + parse.ptr = "(null)"; + } + parse.len = strlen(parse.ptr); + if (parse.precis != -1 && parse.precis < parse.len) { + parse.len = parse.precis; + } + } + else if (c == 'f') { + double d, tmp; + bool negative = false; + uint32_t fract; + + d = va_arg(va, double); + + if (d < 0.0) { + d = -d; + negative = true; + parse.zpad--; + } + + /* + * Assumes four digits after decimal point. We are using a + * temporary double variable to force double-precision + * computations without using --fp_mode=strict flag. + * See the description of that flag in the compiler's doc + * for a further explanation. + */ + tmp = (d - (int32_t)d) * 1e4; + fract = (uint32_t)tmp; + + parse.ptr = formatNum(parse.end, fract, 4, 10); + *(--parse.ptr) = '.'; + + parse.len = parse.end - parse.ptr; + /* format integer part (right to left!) */ + parse.ptr = formatNum(parse.ptr, (int32_t)d, + parse.zpad - parse.len, 10); + if (negative) { + *(--parse.ptr) = '-'; + } + + parse.len = parse.end - parse.ptr; + } + else { + putChar(&buf, c, &n); + res++; + continue; + } + + /* compute number of characters left in field */ + parse.width -= parse.len; + + if (!parse.lJust) { + /* pad with blanks on left */ + while (--parse.width >= 0) { + putChar(&buf, ' ', &n); + res++; + } + } + + /* output number, character or string */ + while (parse.len--) { + putChar(&buf, *parse.ptr++, &n); + res++; + } + /* pad with blanks on right */ + if (parse.lJust) { + while (--parse.width >= 0) { + putChar(&buf, ' ', &n); + res++; + } + } + } /* if */ + } /* while */ + + if (buf) { + *buf = '\0'; + } + + return (res); +} + + +/* + * ======== formatNum ======== + * Internal function + * + * Format unsigned long number in specified base, returning pointer to + * converted output. + * + * Note: ptr points PAST end of the buffer, and is decremented as digits + * are converted from right to left! + * + * Note: base is negative if n is signed else n unsigned! + * + * ptr - Pointer to the end of the working buffer where the string version + * of the number will be placed. + * un - The unsigned number to be formated + * base - The base to format the number into. TODO - signed? + */ +static char *formatNum(char *ptr, UIntMax un, int zpad, int base) +{ + int i = 0; + char sign = 0; + + UIntMax n; + n = un; + + if (base < 0) { + /* handle signed long case */ + base = -base; + if ((IntMax)n < 0) { + n = -(IntMax)n; + + /* account for sign '-': ok since zpad is signed */ + --zpad; + sign = '-'; + } + } + + /* compute digits in number from right to left */ + do { + *(--ptr) = "0123456789abcdef"[(int)(n % base)]; + n = n / base; + ++i; + } while (n); + + /* pad with leading 0s on left */ + while (i < zpad) { + *(--ptr) = '0'; + ++i; + } + + /* add sign indicator */ + if (sign) { + *(--ptr) = sign; + } + return (ptr); +} + +/* + * ======== putChar ======== + * Write character `c` to the buffer and the buffer pointer. + * + * Keeps track of the number of characters written into the buffer by + * modifying bufsize `n`. Atmost, `n` - 1 characters are written. + */ +static void putChar(char **bufp, char c, size_t *n) +{ + /* if the size == 1, don't write so we can '\0' terminate buffer */ + if ((*n) <= 1) { + return; + } + + /* decrement n to keep track of the number of chars written */ + (*n)--; + *((*bufp)++) = c; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/TimerP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/TimerP.h new file mode 100644 index 0000000..526a9cf --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/TimerP.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== TimerP.h ======== + */ + +typedef void *TimerP_Handle; +typedef void (*TimerP_Fxn)(uintptr_t arg); + +#define TimerP_STRUCT_SIZE 60 + +typedef enum { + TimerP_Status_INUSE, + TimerP_Status_FREE, +} TimerP_Status; + +typedef enum { + TimerP_StartMode_AUTO, + TimerP_StartMode_USER, +} TimerP_StartMode; + +typedef struct _TimerP_FreqHz { + uint32_t hi; + uint32_t lo; +} TimerP_FreqHz; + +typedef struct _TimerP_Params { + TimerP_StartMode startMode; + uintptr_t arg; + uint32_t period; /* in microseconds */ +} TimerP_Params; + +typedef union _TimerP_Struct { + uint64_t dummy; + char data[TimerP_STRUCT_SIZE]; +} TimerP_Struct; + +void TimerP_Params_init(TimerP_Params *params); +TimerP_Handle TimerP_construct(TimerP_Struct *handle, TimerP_Fxn timerFxn, TimerP_Params *params); +TimerP_Handle TimerP_create(TimerP_Fxn timerFxn, TimerP_Params *params); +void TimerP_getFreq(TimerP_Handle handle, TimerP_FreqHz *freq); +uint32_t TimerP_getMaxTicks(TimerP_Handle handle); +void TimerP_setThreshold(TimerP_Handle handle, uint32_t next, bool wrap); +void TimerP_setNextTick(TimerP_Handle handle, uint32_t ticks); +void TimerP_startup(); +void TimerP_start(TimerP_Handle handle); +void TimerP_stop(TimerP_Handle handle); +void TimerP_setPeriod(TimerP_Handle handle, uint32_t period); +uint64_t TimerP_getCount64(TimerP_Handle handle); +void TimerP_dynamicStub(uintptr_t arg); +uint32_t TimerP_getCurrentTick(TimerP_Handle handle, bool saveFlag); +void TimerP_initDevice(TimerP_Handle handle); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/TimerPCC26XX_nortos.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/TimerPCC26XX_nortos.c new file mode 100644 index 0000000..e73cd99 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/TimerPCC26XX_nortos.c @@ -0,0 +1,385 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== TimerPCC26XX_nortos.c ======== + */ + +#include + +#include +#include DeviceFamily_constructPath(driverlib/aon_rtc.h) +#include DeviceFamily_constructPath(driverlib/aon_event.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) + +#include +#include "TimerP.h" + +#define COMPARE_MARGIN 4 + +#define MAX_SKIP (0x7E9000000000) /* 32400 seconds (9 hours) */ +#define TIMER_FREQ 65536 + +typedef struct _TimerP_Obj { + TimerP_StartMode startMode; + uint32_t period; + uintptr_t arg; + HwiP_Fxn tickFxn; + TimerP_FreqHz frequency; + uint64_t period64; + uint64_t savedCurrCount; + uint64_t prevThreshold; + uint64_t nextThreshold; +} TimerP_Obj; + +static bool TimerP_initialized = false; +static TimerP_Obj *TimerP_handle; +static HwiP_Struct TimerP_hwiStruct; +//static unsigned int TimerP_availMask = 0x7; + +static TimerP_Params TimerP_defaultParams = { + .startMode = TimerP_StartMode_AUTO, + .arg = 0, + .period = 10, +}; + + +/* + * ======== TimerP_Params_init ======== + */ +void TimerP_Params_init(TimerP_Params *params) +{ + /* structure copy */ + *params = TimerP_defaultParams; +} + +/* + * ======== TimerP_construct ======== + */ +TimerP_Handle TimerP_construct(TimerP_Struct *handle, TimerP_Fxn timerFxn, TimerP_Params *params) +{ + TimerP_Obj *obj = (TimerP_Obj *)handle; + uintptr_t hwiKey; + + if (handle != NULL) { + hwiKey = HwiP_disable(); + + if (!TimerP_initialized) { + HwiP_Params hwiParams; + + HwiP_Params_init(&hwiParams); + hwiParams.priority = INT_PRI_LEVEL4; + HwiP_construct(&TimerP_hwiStruct, INT_AON_RTC_COMB, + TimerP_dynamicStub, &hwiParams); + + TimerP_handle = (TimerP_Obj *)handle; + + TimerP_initDevice(TimerP_handle); + + TimerP_initialized = true; + } + + HwiP_restore(hwiKey); + + if (params == NULL) { + params = (TimerP_Params *)&TimerP_defaultParams; + } + + obj->startMode = params->startMode; + obj->arg = params->arg; + obj->tickFxn = timerFxn; + obj->frequency.lo = TIMER_FREQ; + obj->frequency.hi = 0; + obj->period = (0x100000000UL * params->period) / 1000000U; + obj->period64 = obj->period; + obj->savedCurrCount = 0; + obj->prevThreshold = obj->period; + obj->nextThreshold = obj->period; + + TimerP_startup(); + } + + return ((TimerP_Handle)handle); +} + +/* + * ======== TimerP_create ======== + */ +TimerP_Handle TimerP_create(TimerP_Fxn timerFxn, TimerP_Params *params) +{ + TimerP_Handle handle; + + handle = (TimerP_Handle)malloc(sizeof(TimerP_Obj)); + + /* TimerP_construct will check handle for NULL, no need here */ + handle = TimerP_construct((TimerP_Struct *)handle, timerFxn, params); + + return (handle); +} + +/* + * ======== TimerP_getMaxTicks ======== + */ +uint32_t TimerP_getMaxTicks(TimerP_Handle handle) +{ + TimerP_Obj *obj = (TimerP_Obj *)handle; + uint32_t ticks; + uint64_t temp; + + temp = (uint64_t)(MAX_SKIP) / obj->period64; + + /* clip value to Clock tick count limit of 32-bits */ + if (temp > 0xFFFFFFFF) { + ticks = 0xFFFFFFFF; + } + else { + ticks = (uint32_t)temp; + } + + return (ticks); +} + +/* + * ======== TimerP_setThreshold ======== + */ +void TimerP_setThreshold(TimerP_Handle handle, uint32_t next, bool wrap) +{ + uint32_t now; + + /* get the current RTC count corresponding to compare window */ + now = AONRTCCurrentCompareValueGet(); + + /* else if next is too soon, set at least one RTC tick in future */ + /* assume next never be more than half the maximum 32 bit count value */ + if ((next - now) > (uint32_t)0x80000000) { + /* now is past next */ + next = now + COMPARE_MARGIN; + } + else if ((now + COMPARE_MARGIN - next) < (uint32_t)0x80000000) { + if (next < now + COMPARE_MARGIN) { + next = now + COMPARE_MARGIN; + } + } + + /* set next compare threshold in RTC */ + AONRTCCompareValueSet(AON_RTC_CH0, next); +} + +/* + * ======== TimerP_setNextTick ======== + */ +void TimerP_setNextTick(TimerP_Handle handle, uint32_t ticks) +{ + TimerP_Obj *obj = (TimerP_Obj *)handle; + bool wrap = false; + uint32_t next; + uint64_t newThreshold; + + /* calculate new 64-bit RTC count for next interrupt */ + newThreshold = obj->savedCurrCount + (uint64_t)ticks * obj->period64; + + /* isolate the new 32-bit compare value to write to RTC */ + next = (uint32_t)(newThreshold >> 16); + + /* set the compare threshold at the RTC */ + TimerP_setThreshold(obj, next, wrap); + + /* save the threshold for next interrupt */ + obj->prevThreshold = newThreshold; +} + +/* + * ======== TimerP_startup ======== + * Here after call to main(). Called from BIOS_start(). + */ +void TimerP_startup() +{ + TimerP_Obj *obj; + + obj = TimerP_handle; + /* if timer was statically created/constructed */ + if (obj != NULL) { + if (obj->startMode == TimerP_StartMode_AUTO) { + TimerP_start(obj); + } + } +} + +/* + * ======== TimerP_start ======== + * + * 1. HwiP_disable() + * 2. Reset the RTC + * 3. Clear any RTC events + * 4. Set first compare threshold (per configured period) + * 5. Enable the compare channel + * 6. Enable the RTC to start it ticking + * 7. HwiP_restore() + * + */ +void TimerP_start(TimerP_Handle handle) +{ + TimerP_Obj *obj = (TimerP_Obj *)handle; + uint32_t compare; + uintptr_t key; + + key = HwiP_disable(); + + /* reset timer */ + AONRTCReset(); + AONRTCEventClear(AON_RTC_CH0); + IntPendClear(INT_AON_RTC_COMB); + + /* + * set the compare register to the counter start value plus one period. + * For a very small period round up to interrupt upon 4th RTC tick + */ + if (obj->period < 0x40000) { + compare = 0x4; /* 4 * 15.5us ~= 62us */ + } + /* else, interrupt on first period expiration */ + else { + compare = obj->period >> 16; + } + + /* set the compare value at the RTC */ + AONRTCCompareValueSet(AON_RTC_CH0, compare); + + /* enable compare channel 0 */ + AONEventMcuWakeUpSet(AON_EVENT_MCU_WU0, AON_EVENT_RTC0); + AONRTCChannelEnable(AON_RTC_CH0); + AONRTCCombinedEventConfig(AON_RTC_CH0); + + /* start timer */ + AONRTCEnable(); + + HwiP_restore(key); +} + +/* + * ======== TimerP_stop ======== + */ +void TimerP_stop(TimerP_Handle handle) +{ + TimerP_Obj *obj = (TimerP_Obj *)handle; + /* not implemented for this timer */ + obj->savedCurrCount = 0; +} + +/* + * ======== TimerP_setPeriod ======== + * + * 1. Stop timer + * 2. Set period value in timer obj + * + */ +void TimerP_setPeriod(TimerP_Handle handle, uint32_t period) +{ + TimerP_Obj *obj = (TimerP_Obj *)handle; + obj->period = period; +} + +/* + * ======== TimerP_getCount64 ======== + */ +uint64_t TimerP_getCount64(TimerP_Handle handle) +{ + return(AONRTCCurrent64BitValueGet()); +} + +/* + * ======== TimerP_getFreq ======== + */ +void TimerP_getFreq(TimerP_Handle handle, TimerP_FreqHz *freq) +{ + freq->lo = TIMER_FREQ; + freq->hi = 0; +} + +/* + * ======== TimerP_dynamicStub ======== + */ +void TimerP_dynamicStub(uintptr_t arg) +{ + TimerP_Obj *obj; + + obj = TimerP_handle; + + /* clear the RTC event */ + AONRTCEventClear(AON_RTC_CH0); + + /* call the tick function */ + obj->tickFxn(obj->arg); +} + +/* + * ======== TimerP_getCurrentTick ======== + * Used by the Clock module for TickMode_DYNAMIC to query the corresponding + * Clock tick, as derived from the current timer count. + */ +uint32_t TimerP_getCurrentTick(TimerP_Handle handle, bool saveFlag) +{ + TimerP_Obj *obj = (TimerP_Obj *)handle; + uint64_t tick, currCount; + + currCount = (uint64_t)TimerP_getCount64(obj); + + tick = currCount / obj->period64; + + if (saveFlag != 0) { + /* + * to avoid accumulating drift, make currCount be an integer + * multiple of timer periods + */ + currCount = tick * obj->period64; + obj->savedCurrCount = currCount; + } + + return ((uint32_t)tick); +} + +/* ======== TimerP_initDevice ======== + * Disable and reset the RTC. + */ +void TimerP_initDevice(TimerP_Handle handle) +{ + AONRTCDisable(); + AONRTCReset(); + + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC) = 1; + /* read sync register to complete reset */ + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); + + AONRTCEventClear(AON_RTC_CH0); + IntPendClear(INT_AON_RTC_COMB); + + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/posix_sleep.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/posix_sleep.c new file mode 100644 index 0000000..dd25ad0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/posix_sleep.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== posix_sleep.c ======== + */ + +#include + +/* + * ======== sleep ======== + */ +void sleep(uint32_t sec) +{ + ClockP_sleep(sec); +} + +/* + * ======== usleep ======== + */ +void usleep(uint32_t usec) +{ + ClockP_usleep(usec); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc13x0.am3g b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc13x0.am3g new file mode 100644 index 0000000..1bf5d0e Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc13x0.am3g differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc13x0.arm3 b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc13x0.arm3 new file mode 100644 index 0000000..495592f Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc13x0.arm3 differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc13x2.am4fg b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc13x2.am4fg new file mode 100644 index 0000000..3b19569 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc13x2.am4fg differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc13x2.arm4f b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc13x2.arm4f new file mode 100644 index 0000000..9936462 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc13x2.arm4f differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc26x0.am3g b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc26x0.am3g new file mode 100644 index 0000000..2000e0f Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc26x0.am3g differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc26x0.arm3 b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc26x0.arm3 new file mode 100644 index 0000000..995a603 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc26x0.arm3 differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc26x2.am4fg b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc26x2.am4fg new file mode 100644 index 0000000..3e59487 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc26x2.am4fg differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc26x2.arm4f b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc26x2.arm4f new file mode 100644 index 0000000..0f5bae0 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/lib/nortos_cc26x2.arm4f differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/posix/sys/types.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/posix/sys/types.h new file mode 100644 index 0000000..217edc0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/posix/sys/types.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== sys/types.h ======== + */ + +#ifndef nortos_posix_sys_types__include +#define nortos_posix_sys_types__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + + +#if !defined(__GNUC__) || defined(__ti__) +/* + * ssize_t is a signed size_t. It is the return type for mqueue + * receive functions, so we need to define it for TI and IAR. + */ +typedef long int ssize_t; + +typedef uint32_t clockid_t; +typedef unsigned long useconds_t; +typedef unsigned long timer_t; + +#else +#include <../include/sys/types.h> +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/posix/unistd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/posix/unistd.h new file mode 100644 index 0000000..d66fc05 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/posix/unistd.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== unistd.h ======== + */ + +#ifndef nortos_posix_unistd__include +#define nortos_posix_unistd__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sys/types.h" + +extern unsigned sleep(unsigned seconds); +extern int usleep(useconds_t useconds); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/startup/startup_cc13xx_cc26xx_gcc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/startup/startup_cc13xx_cc26xx_gcc.c new file mode 100644 index 0000000..6a00426 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/startup/startup_cc13xx_cc26xx_gcc.c @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +//***************************************************************************** +// +// Check if compiler is GNU Compiler +// +//***************************************************************************** +#if !(defined(__GNUC__)) +#error "startup_cc13xx_cc26xx_gcc.c: Unsupported compiler!" +#endif + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/setup.h) + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void resetISR(void); +static void nmiISR(void); +static void faultISR(void); +static void defaultHandler(void); +static void busFaultHandler(void); + +//***************************************************************************** +// +// External declaration for the reset handler that is to be called when the +// processor is started +// +//***************************************************************************** +extern void _c_int00(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +//***************************************************************************** +// +// linker variable that marks the top of stack. +// +//***************************************************************************** +extern unsigned long _stack_end; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".resetVecs"))) __attribute__ ((used)) +static void (* const resetVectors[16])(void) = +{ + (void (*)(void))((uint32_t)&_stack_end), + // The initial stack pointer + resetISR, // The reset handler + nmiISR, // The NMI handler + faultISR, // The hard fault handler + defaultHandler, // The MPU fault handler + busFaultHandler, // The bus fault handler + defaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + defaultHandler, // SVCall handler + defaultHandler, // Debug monitor handler + 0, // Reserved + defaultHandler, // The PendSV handler + defaultHandler // The SysTick handler +}; + +__attribute__ ((section(".ramVecs"))) +static unsigned long ramVectors[50]; + +//***************************************************************************** +// +// The following are arrays of pointers to constructor functions that need to +// be called during startup to initialize global objects. +// +//***************************************************************************** +extern void (*__init_array_start []) (void); +extern void (*__init_array_end []) (void); + +//***************************************************************************** +// +// The following global variable is required for C++ support. +// +//***************************************************************************** +void * __dso_handle = (void *) &__dso_handle; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern uint32_t __bss_start__, __bss_end__; +extern uint32_t __data_load__, __data_start__, __data_end__; + +// +//***************************************************************************** +// +// Initialize the .data and .bss sections and copy the first 16 vectors from +// the read-only/reset table to the runtime RAM table. Fill the remaining +// vectors with a stub. This vector table will be updated at runtime. +// +//***************************************************************************** +// +void localProgramStart(void) +{ + uint32_t * bs; + uint32_t * be; + uint32_t * dl; + uint32_t * ds; + uint32_t * de; + uint32_t count; + uint32_t i; + +#if defined (__ARM_ARCH_7EM__) && defined(__VFP_FP__) && !defined(__SOFTFP__) + volatile uint32_t * pui32Cpacr = (uint32_t *) 0xE000ED88; + + /* Enable Coprocessor Access Control (CPAC) */ + *pui32Cpacr |= (0xF << 20); +#endif + + IntMasterDisable(); + + /* Final trim of device */ + SetupTrimDevice(); + + /* initiailize .bss to zero */ + bs = & __bss_start__; + be = & __bss_end__; + while (bs < be) { + *bs = 0; + bs++; + } + + /* relocate the .data section */ + dl = & __data_load__; + ds = & __data_start__; + de = & __data_end__; + if (dl != ds) { + while (ds < de) { + *ds = *dl; + dl++; + ds++; + } + } + + /* Run any constructors */ + count = (uint32_t)(__init_array_end - __init_array_start); + for (i = 0; i < count; i++) { + __init_array_start[i](); + } + + /* Copy from reset vector table into RAM vector table */ + memcpy(ramVectors, resetVectors, 16*4); + + /* fill remaining vectors with default handler */ + for (i=16; i < 50; i++) { + ramVectors[i] = (unsigned long)defaultHandler; + } + + /* Call the application's entry point. */ + main(); + + /* If we ever return signal Error */ + faultISR(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void __attribute__((naked)) resetISR(void) +{ + __asm__ __volatile__ ( + " movw r0, #:lower16:resetVectors\n" + " movt r0, #:upper16:resetVectors\n" + " ldr r0, [r0]\n" + " mov sp, r0\n" + " bl localProgramStart" + ); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +nmiISR(void) +{ + /* Enter an infinite loop. */ + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +faultISR(void) +{ + /* Enter an infinite loop. */ + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** + +static void +busFaultHandler(void) +{ + /* Enter an infinite loop. */ + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +defaultHandler(void) +{ + /* Enter an infinite loop. */ + while(1) + { + } +} + +//***************************************************************************** +// +// This function is called by __libc_fini_array which gets called when exit() +// is called. In order to support exit(), an empty _fini() stub function is +// required. +// +//***************************************************************************** +void _fini(void) +{ + /* Function body left empty intentionally */ +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/startup/startup_cc13xx_cc26xx_iar.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/startup/startup_cc13xx_cc26xx_iar.c new file mode 100644 index 0000000..c1ce6c9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/startup/startup_cc13xx_cc26xx_iar.c @@ -0,0 +1,306 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +//***************************************************************************** +// +// Check if compiler is IAR +// +//***************************************************************************** +#if !(defined(__IAR_SYSTEMS_ICC__)) +#error "startup_cc13xx_cc26xx_iar.c: Unsupported compiler!" +#endif + + +// We need intrinsic functions for IAR (if used in source code) +#include +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/setup.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) + + +//***************************************************************************** +// +//! Forward declaration of the reset ISR and the default fault handlers. +// +//***************************************************************************** +static void nmiISR( void ); +static void faultISR( void ); +static void intDefaultHandler( void ); +extern int main( void ); + +extern void MPUFaultIntHandler( void ); +extern void BusFaultIntHandler( void ); +extern void UsageFaultIntHandler( void ); +extern void SVCallIntHandler( void ); +extern void DebugMonIntHandler( void ); +extern void PendSVIntHandler( void ); +extern void SysTickIntHandler( void ); +extern void GPIOIntHandler( void ); +extern void I2CIntHandler( void ); +extern void RFCCPE1IntHandler( void ); +extern void AONRTCIntHandler( void ); +extern void UART0IntHandler( void ); +extern void AUXSWEvent0IntHandler( void ); +extern void SSI0IntHandler( void ); +extern void SSI1IntHandler( void ); +extern void RFCCPE0IntHandler( void ); +extern void RFCHardwareIntHandler( void ); +extern void RFCCmdAckIntHandler( void ); +extern void I2SIntHandler( void ); +extern void AUXSWEvent1IntHandler( void ); +extern void WatchdogIntHandler( void ); +extern void Timer0AIntHandler( void ); +extern void Timer0BIntHandler( void ); +extern void Timer1AIntHandler( void ); +extern void Timer1BIntHandler( void ); +extern void Timer2AIntHandler( void ); +extern void Timer2BIntHandler( void ); +extern void Timer3AIntHandler( void ); +extern void Timer3BIntHandler( void ); +extern void CryptoIntHandler( void ); +extern void uDMAIntHandler( void ); +extern void uDMAErrIntHandler( void ); +extern void FlashIntHandler( void ); +extern void SWEvent0IntHandler( void ); +extern void AUXCombEventIntHandler( void ); +extern void AONProgIntHandler( void ); +extern void DynProgIntHandler( void ); +extern void AUXCompAIntHandler( void ); +extern void AUXADCIntHandler( void ); +extern void TRNGIntHandler( void ); + +// Default interrupt handlers +#pragma weak MPUFaultIntHandler = intDefaultHandler +#pragma weak BusFaultIntHandler = intDefaultHandler +#pragma weak UsageFaultIntHandler = intDefaultHandler +#pragma weak SVCallIntHandler = intDefaultHandler +#pragma weak DebugMonIntHandler = intDefaultHandler +#pragma weak PendSVIntHandler = intDefaultHandler +#pragma weak SysTickIntHandler = intDefaultHandler +#pragma weak GPIOIntHandler = intDefaultHandler +#pragma weak I2CIntHandler = intDefaultHandler +#pragma weak RFCCPE1IntHandler = intDefaultHandler +#pragma weak AONRTCIntHandler = intDefaultHandler +#pragma weak UART0IntHandler = intDefaultHandler +#pragma weak AUXSWEvent0IntHandler = intDefaultHandler +#pragma weak SSI0IntHandler = intDefaultHandler +#pragma weak SSI1IntHandler = intDefaultHandler +#pragma weak RFCCPE0IntHandler = intDefaultHandler +#pragma weak RFCHardwareIntHandler = intDefaultHandler +#pragma weak RFCCmdAckIntHandler = intDefaultHandler +#pragma weak I2SIntHandler = intDefaultHandler +#pragma weak AUXSWEvent1IntHandler = intDefaultHandler +#pragma weak WatchdogIntHandler = intDefaultHandler +#pragma weak Timer0AIntHandler = intDefaultHandler +#pragma weak Timer0BIntHandler = intDefaultHandler +#pragma weak Timer1AIntHandler = intDefaultHandler +#pragma weak Timer1BIntHandler = intDefaultHandler +#pragma weak Timer2AIntHandler = intDefaultHandler +#pragma weak Timer2BIntHandler = intDefaultHandler +#pragma weak Timer3AIntHandler = intDefaultHandler +#pragma weak Timer3BIntHandler = intDefaultHandler +#pragma weak CryptoIntHandler = intDefaultHandler +#pragma weak uDMAIntHandler = intDefaultHandler +#pragma weak uDMAErrIntHandler = intDefaultHandler +#pragma weak FlashIntHandler = intDefaultHandler +#pragma weak SWEvent0IntHandler = intDefaultHandler +#pragma weak AUXCombEventIntHandler = intDefaultHandler +#pragma weak AONProgIntHandler = intDefaultHandler +#pragma weak DynProgIntHandler = intDefaultHandler +#pragma weak AUXCompAIntHandler = intDefaultHandler +#pragma weak AUXADCIntHandler = intDefaultHandler +#pragma weak TRNGIntHandler = intDefaultHandler + +//***************************************************************************** +// +//! The entry point for the application startup code. +// +//***************************************************************************** +extern void __iar_program_start(void); + +//***************************************************************************** +// +//! Get stack start (highest address) symbol from linker file. +// +//***************************************************************************** +extern const void* STACK_TOP; + +// It is required to place something in the CSTACK segment to get the stack +// check feature in IAR to work as expected +__root static void* dummy_stack @ ".stack"; + + +//***************************************************************************** +// +//! The vector table. Note that the proper constructs must be placed on this to +//! ensure that it ends up at physical address 0x0000.0000 or at the start of +//! the program if located at a start address other than 0. +// +//***************************************************************************** +__root void (* const __vector_table[])(void) @ ".intvec" = +{ + (void (*)(void))&STACK_TOP, // 0 The initial stack pointer + __iar_program_start, // 1 The reset handler + nmiISR, // 2 The NMI handler + faultISR, // 3 The hard fault handler + MPUFaultIntHandler, // 4 The MPU fault handler + BusFaultIntHandler, // 5 The bus fault handler + UsageFaultIntHandler, // 6 The usage fault handler + 0, // 7 Reserved + 0, // 8 Reserved + 0, // 9 Reserved + 0, // 10 Reserved + SVCallIntHandler, // 11 SVCall handler + DebugMonIntHandler, // 12 Debug monitor handler + 0, // 13 Reserved + PendSVIntHandler, // 14 The PendSV handler + SysTickIntHandler, // 15 The SysTick handler + //--- External interrupts --- + GPIOIntHandler, // 16 AON edge detect + I2CIntHandler, // 17 I2C + RFCCPE1IntHandler, // 18 RF Core Command & Packet Engine 1 + intDefaultHandler, // 19 Reserved + AONRTCIntHandler, // 20 AON RTC + UART0IntHandler, // 21 UART0 Rx and Tx + AUXSWEvent0IntHandler, // 22 AUX software event 0 + SSI0IntHandler, // 23 SSI0 Rx and Tx + SSI1IntHandler, // 24 SSI1 Rx and Tx + RFCCPE0IntHandler, // 25 RF Core Command & Packet Engine 0 + RFCHardwareIntHandler, // 26 RF Core Hardware + RFCCmdAckIntHandler, // 27 RF Core Command Acknowledge + I2SIntHandler, // 28 I2S + AUXSWEvent1IntHandler, // 29 AUX software event 1 + WatchdogIntHandler, // 30 Watchdog timer + Timer0AIntHandler, // 31 Timer 0 subtimer A + Timer0BIntHandler, // 32 Timer 0 subtimer B + Timer1AIntHandler, // 33 Timer 1 subtimer A + Timer1BIntHandler, // 34 Timer 1 subtimer B + Timer2AIntHandler, // 35 Timer 2 subtimer A + Timer2BIntHandler, // 36 Timer 2 subtimer B + Timer3AIntHandler, // 37 Timer 3 subtimer A + Timer3BIntHandler, // 38 Timer 3 subtimer B + CryptoIntHandler, // 39 Crypto Core Result available + uDMAIntHandler, // 40 uDMA Software + uDMAErrIntHandler, // 41 uDMA Error + FlashIntHandler, // 42 Flash controller + SWEvent0IntHandler, // 43 Software Event 0 + AUXCombEventIntHandler, // 44 AUX combined event + AONProgIntHandler, // 45 AON programmable 0 + DynProgIntHandler, // 46 Dynamic Programmable interrupt + // source (Default: PRCM) + AUXCompAIntHandler, // 47 AUX Comparator A + AUXADCIntHandler, // 48 AUX ADC new sample or ADC DMA + // done, ADC underflow, ADC overflow + TRNGIntHandler // 49 TRNG event +}; + + +//***************************************************************************** +// +// This function is called by __iar_program_start() early in the boot sequence. +// Copy the first 16 vectors from the read-only/reset table to the runtime +// RAM table. Fill the remaining vectors with a stub. This vector table will +// be updated at runtime. +// +//***************************************************************************** +int __low_level_init(void) +{ + IntMasterDisable(); + + // + // Final trim of device + // + SetupTrimDevice(); + + /*==================================*/ + /* Choose if segment initialization */ + /* should be done or not. */ + /* Return: 0 to omit seg_init */ + /* 1 to run seg_init */ + /*==================================*/ + return 1; +} + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives a NMI. This +//! simply enters an infinite loop, preserving the system state for examination +//! by a debugger. +// +//***************************************************************************** +static void +nmiISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives a fault +//! interrupt. This simply enters an infinite loop, preserving the system state +//! for examination by a debugger. +// +//***************************************************************************** +static void +faultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives an unexpected +//! interrupt. This simply enters an infinite loop, preserving the system state +//! for examination by a debugger. +// +//***************************************************************************** +static void +intDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/DeviceFamily.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/DeviceFamily.h new file mode 100644 index 0000000..68ecb2f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/DeviceFamily.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file DeviceFamily.h + * + * @brief Infrastructure to select correct driverlib path and identify devices + * + * This module enables the selection of the correct driverlib path for the current + * device. It also facilitates the use of per-device conditional compilation + * to enable minor variations in drivers between devices. + * + * In order to use this functionality, DeviceFamily_XYZ must be defined as one of + * the supported values. The DeviceFamily_ID and DeviceFamily_DIRECTORY defines + * are set based on DeviceFamily_XYZ. + */ + +#ifndef ti_devices_DeviceFamily__include +#define ti_devices_DeviceFamily__include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * DeviceFamily_ID_XYZ values. + * + * DeviceFamily_ID may be used in the preprocessor for conditional compilation. + * DeviceFamily_ID is set to one of these values based on the top level + * DeviceFamily_XYZ define. + */ +#define DeviceFamily_ID_CC13X0 1 +#define DeviceFamily_ID_CC26X0 2 +#define DeviceFamily_ID_CC26X0R2 3 +#define DeviceFamily_ID_CC13X2 4 +#define DeviceFamily_ID_CC26X2 5 +#define DeviceFamily_ID_CC3200 8 +#define DeviceFamily_ID_CC3220 9 +#define DeviceFamily_ID_MSP432P401x 10 +#define DeviceFamily_ID_MSP432P4x1xI 11 +#define DeviceFamily_ID_MSP432P4x1xT 12 +#define DeviceFamily_ID_MSP432E401Y 13 +#define DeviceFamily_ID_MSP432E411Y 14 +#define DeviceFamily_ID_MTL 15 + +/* + * DeviceFamily_PARENT_XYZ values. + * + * DeviceFamily_PARENT may be used in the preprocessor for conditional + * compilation. DeviceFamily_PARENT is set to one of these values based + * on the top-level DeviceFamily_XYZ define. + */ +#define DeviceFamily_PARENT_CC13X0_CC26X0 1 +#define DeviceFamily_PARENT_CC13X2_CC26X2 2 +#define DeviceFamily_PARENT_MSP432P401R 3 +#define DeviceFamily_PARENT_MSP432P4111 4 +#define DeviceFamily_PARENT_MTL 5 +#define DeviceFamily_PARENT_MSP432E4X1Y 6 + +/* + * Lookup table that sets DeviceFamily_ID, DeviceFamily_DIRECTORY, and + * DeviceFamily_PARENT based on the DeviceFamily_XYZ define. + * If DeviceFamily_XYZ is undefined, a compiler error is thrown. If + * multiple DeviceFamily_XYZ are defined, the first one encountered is used. + */ +#if defined(DeviceFamily_CC13X0) + #define DeviceFamily_ID DeviceFamily_ID_CC13X0 + #define DeviceFamily_DIRECTORY cc13x0 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 + +#elif defined(DeviceFamily_CC13X2) + #define DeviceFamily_ID DeviceFamily_ID_CC13X2 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC26X0) + #define DeviceFamily_ID DeviceFamily_ID_CC26X0 + #define DeviceFamily_DIRECTORY cc26x0 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 + +#elif defined(DeviceFamily_CC26X0R2) + #define DeviceFamily_ID DeviceFamily_ID_CC26X0R2 + #define DeviceFamily_DIRECTORY cc26x0r2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 + +#elif defined(DeviceFamily_CC26X2) + #define DeviceFamily_ID DeviceFamily_ID_CC26X2 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC3200) + #define DeviceFamily_ID DeviceFamily_ID_CC3200 + #define DeviceFamily_DIRECTORY cc32xx + +#elif defined(DeviceFamily_CC3220) + #define DeviceFamily_ID DeviceFamily_ID_CC3220 + #define DeviceFamily_DIRECTORY cc32xx + +#elif defined(DeviceFamily_MSP432P401x) || defined(__MSP432P401R__) + #define DeviceFamily_ID DeviceFamily_ID_MSP432P401x + #define DeviceFamily_DIRECTORY msp432p4xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P401R + #if !defined(__MSP432P401R__) + #define __MSP432P401R__ + #endif + +#elif defined(DeviceFamily_MSP432P4x1xI) + #define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xI + #define DeviceFamily_DIRECTORY msp432p4xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 + #if !defined(__MSP432P4111__) + #define __MSP432P4111__ + #endif + +#elif defined(DeviceFamily_MSP432P4x1xT) + #define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xT + #define DeviceFamily_DIRECTORY msp432p4xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 + #if !defined(__MSP432P4111__) + #define __MSP432P4111__ + #endif + +#elif defined(DeviceFamily_MSP432E401Y) + #define DeviceFamily_ID DeviceFamily_ID_MSP432E401Y + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432E4X1Y + #define DeviceFamily_DIRECTORY msp432e4 + #if !defined(__MSP432E401Y__) + #define __MSP432E401Y__ + #endif + +#elif defined(DeviceFamily_MSP432E411Y) + #define DeviceFamily_ID DeviceFamily_ID_MSP432E411Y + #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432E4X1Y + #define DeviceFamily_DIRECTORY msp432e4 + #if !defined(__MSP432E411Y__) + #define __MSP432E411Y__ + #endif +#elif defined(DeviceFamily_MTL) + #define DeviceFamily_ID DeviceFamily_ID_MTL + #define DeviceFamily_DIRECTORY mtxx + #if !defined(__MTL__) + #define __MTL__ + #endif +#else + #error "DeviceFamily_XYZ undefined. You must define a DeviceFamily_XYZ!" +#endif + +/* Ensure that only one DeviceFamily was specified */ +#if (defined(DeviceFamily_CC13X0) + defined(DeviceFamily_CC13X2) \ + + defined(DeviceFamily_CC26X0) + defined(DeviceFamily_CC26X0R2) \ + + defined(DeviceFamily_CC26X2) \ + + defined(DeviceFamily_CC3200) + defined(DeviceFamily_CC3220) \ + + defined(DeviceFamily_MSP432P401x) + defined(DeviceFamily_MSP432P4x1xI) \ + + defined(DeviceFamily_MSP432P4x1xT) + defined(DeviceFamily_MSP432E401Y) \ + + defined(DeviceFamily_MSP432E411Y) \ + + defined(DeviceFamily_MTL) \ + ) > 1 + #error More then one DeviceFamily has been defined! +#endif + +/*! + * @brief Macro to include correct driverlib path. + * + * @pre DeviceFamily_XYZ which sets DeviceFamily_DIRECTORY must be defined + * first. + * + * @param x A token containing the path of the file to include based on + * the root device folder. The preceding forward slash must be + * omitted. For example: + * - #include DeviceFamily_constructPath(inc/hw_memmap.h) + * - #include DeviceFamily_constructPath(driverlib/ssi.h) + * + * @return Returns an include path. + * + */ +#define DeviceFamily_constructPath(x) + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_DeviceFamily__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi.c new file mode 100644 index 0000000..47ecc7f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi.c @@ -0,0 +1,73 @@ +/****************************************************************************** +* Filename: adi.c +* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) +* Revision: 47706 +* +* Description: Driver for the ADI interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aux_smph.h" +#include "adi.h" +#include "cpu.h" + + +//***************************************************************************** +// +// SafeHapiVoid() and SafeHapiAuxAdiSelect() +// Common wrapper functions for the Hapi functions needing workaround for the +// "bus arbitration" issue. +// +//***************************************************************************** +void SafeHapiVoid( FPTR_VOID_VOID_T fPtr ) +{ + bool bIrqEnabled = ( ! CPUcpsid() ); + while ( ! HWREG( AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 )); + fPtr(); + HWREG( AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 ) = 1; + if ( bIrqEnabled ) { + CPUcpsie(); + } +} + +void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ) +{ + bool bIrqEnabled = ( ! CPUcpsid() ); + while ( ! HWREG( AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 )); + fPtr( ut8Signal ); + HWREG( AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 ) = 1; + if ( bIrqEnabled ) { + CPUcpsie(); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi.h new file mode 100644 index 0000000..a204232 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi.h @@ -0,0 +1,861 @@ +/****************************************************************************** +* Filename: adi.h +* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) +* Revision: 47706 +* +* Description: Defines and prototypes for the ADI master interface. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup analog_group +//! @{ +//! \addtogroup adi_api +//! @{ +// +//***************************************************************************** + +#ifndef __ADI_H__ +#define __ADI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_uart.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_adi.h" +#include "debug.h" +#include "ddi.h" + +//***************************************************************************** +// +// Number of registers in the ADI slave +// +//***************************************************************************** +#define ADI_SLAVE_REGS 16 + + +//***************************************************************************** +// +// Defines that is used to control the ADI slave and master +// +//***************************************************************************** +#define ADI_PROTECT 0x00000080 +#define ADI_ACK 0x00000001 +#define ADI_SYNC 0x00000000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! \brief Checks an ADI base address. +//! +//! This function determines if an ADI port base address is valid. +//! +//! \param ui32Base is the base address of the ADI port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise +// +//***************************************************************************** +static bool +ADIBaseValid(uint32_t ui32Base) +{ + return(ui32Base == ADI2_BASE || ui32Base == ADI3_BASE || + ui32Base == AUX_ADI4_BASE); +} +#endif + + + + + +//***************************************************************************** +// +//! \brief Write an 8 bit value to a register in an ADI slave. +//! +//! This function will write a value to a single register in the analog domain. +//! The access to the registers in the analog domain is either 8, 16, or 32 bit +//! aligned. You can only do 16 bit access on registers 0-1 / 2-3, etc. Similarly +//! 32 bit accesses are always performed on register 0-3 / 4-7, etc. Addresses +//! for the registers and values being written to the registers will be +//! truncated according to this access scheme. +//! +//! \note This operation is write only for the specified register. No +//! previous value of the register will be kept (i.e. this is NOT +//! read-modify-write on the register). +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the register to write. +//! \param ui8Val is the 8 bit value to write to the register. +//! +//! \return None +//! +//! \sa ADI16RegWrite(), ADI32RegWrite() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Write the value to the register. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32Reg, ui8Val, 1); + } else { + HWREGB(ui32Base + ui32Reg) = ui8Val; + } +} + +//***************************************************************************** +// +//! \brief Write a 16 bit value to 2 registers in the ADI slave. +//! +//! This function will write a value to 2 consecutive registers in the analog +//! domain. The access to the registers in the analog domain is either 8, 16 +//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3, +//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7, +//! etc. Addresses for the registers and values being written +//! to the registers will be truncated according to this access scheme. +//! +//! \note The byte addressing bit will be ignored, to ensure 16 bit access +//! to the ADI slave. +//! +//! \note This operation is write only for the specified register. No +//! previous value of the register will be kept (i.e. this is NOT +//! read-modify-write on the register). +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the register to write. +//! \param ui16Val is the 16 bit value to write to the register. +//! +//! \return None +//! +//! \sa ADI8RegWrite(), ADI32RegWrite() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16RegWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint16_t ui16Val) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Write the value to the register. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + (ui32Reg & 0xFE), ui16Val, 2); + } else { + HWREGH(ui32Base + (ui32Reg & 0xFE)) = ui16Val; + } +} + +//***************************************************************************** +// +//! \brief Write a 32 bit value to 4 registers in the ADI slave. +//! +//! This function will write a value to 4 consecutive registers in the analog +//! domain. The access to the registers in the analog domain is either 8, 16 +//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3, +//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7, +//! etc. Addresses for the registers and values being written +//! to the registers will be truncated according to this access scheme. +//! +//! \note The byte and half word addressing bits will be ignored, to ensure +//! 32 bit access to the ADI slave. +//! +//! \note This operation is write only for the specified register. No +//! previous value of the register will be kept (i.e. this is NOT +//! read-modify-write on the register). +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the register to write. +//! \param ui32Val is the 32 bit value to write to the register. +//! +//! \return None +//! +//! \sa ADI8RegWrite(), ADI16RegWrite() +// +//***************************************************************************** +__STATIC_INLINE void +ADI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Write the value to the register. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + (ui32Reg & 0xFC), ui32Val, 4); + } else { + HWREG(ui32Base + (ui32Reg & 0xFC)) = ui32Val; + } +} + +//***************************************************************************** +// +//! \brief Read the value of an 8 bit register in the ADI slave. +//! +//! This function will read an 8 bit register in the analog domain and return +//! the value as the lower 8 bits of an \c uint32_t. The access to the +//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can +//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses +//! are always performed on register 0-3 / 4-7, etc. Addresses for the +//! registers and values being written to the registers will be truncated +//! according to this access scheme. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the 8 bit register to read. +//! +//! \return Returns the 8 bit value of the analog register in the least +//! significant byte of the \c uint32_t. +//! +//! \sa ADI16RegRead(), ADI32RegRead() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ADI8RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Read the register and return the value. + if (ui32Base==AUX_ADI4_BASE) { + return AuxAdiDdiSafeRead(ui32Base + ui32Reg, 1); + } else { + return(HWREGB(ui32Base + ui32Reg)); + } +} + +//***************************************************************************** +// +//! \brief Read the value in a 16 bit register. +//! +//! This function will read 2 x 8 bit registers in the analog domain and return +//! the value as the lower 16 bits of an \c uint32_t. The access to the +//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can +//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses +//! are always performed on register 0-3 / 4-7, etc. Addresses for the +//! registers and values being written to the registers will be truncated +//! according to this access scheme. +//! +//! \note The byte addressing bit will be ignored, to ensure 16 bit access +//! to the ADI slave. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the 16 bit register to read. +//! +//! \return Returns the 16 bit value of the 2 analog register in the 2 least +//! significant bytes of the \c uint32_t. +//! +//! \sa ADI8RegRead(), ADI32RegRead() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ADI16RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Read the registers and return the value. + if (ui32Base==AUX_ADI4_BASE) { + return AuxAdiDdiSafeRead(ui32Base + (ui32Reg & 0xFE), 2); + } else { + return(HWREGH(ui32Base + (ui32Reg & 0xFE))); + } +} + +//***************************************************************************** +// +//! \brief Read the value in a 32 bit register. +//! +//! This function will read 4 x 8 bit registers in the analog domain and return +//! the value as an \c uint32_t. The access to the registers in the analog +//! domain is either 8, 16 or 32 bit aligned. You can only do 16 bit access on +//! registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always performed on +//! register 0-3 / 4-7, etc. Addresses for the registers and values being +//! written to the registers will be truncated according to this access scheme. +//! +//! \note The byte and half word addressing bits will be ignored, to ensure +//! 32 bit access to the ADI slave. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the 32 bit register to read. +//! +//! \return Returns the 32 bit value of the 4 analog registers. +//! +//! \sa ADI8RegRead(), ADI16RegRead() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ADI32RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Read the registers and return the value. + if (ui32Base==AUX_ADI4_BASE) { + return AuxAdiDdiSafeRead(ui32Base + (ui32Reg & 0xFC), 4); + } else { + return(HWREG(ui32Base + (ui32Reg & 0xFC))); + } +} + +//***************************************************************************** +// +//! \brief Set specific bits in a single 8 bit ADI register. +//! +//! This function will set bits in a single register in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in a specific 8 bit register in the +//! ADI slave. Only bits in the selected register are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui8Val is the 8 bit one-hot encoded value specifying which +//! bits to set in the register. +//! +//! \return None +//! +//! \sa ADI16BitsSet(), ADI32BitsSet() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_SET; + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + ui32Reg, ui8Val, 1); + } else { + HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val; + } +} + +//***************************************************************************** +// +//! \brief Set specific bits in 2 x 8 bit ADI slave registers. +//! +//! This function will set bits in 2 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in 2 consecutive 8 bit registers in the +//! ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui16Val is the 16 bit one-hot encoded value specifying which +//! bits to set in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsSet(), ADI32BitsSet() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_SET; + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + (ui32Reg & 0xFE), ui16Val, 2); + } else { + HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val; + } +} + +//***************************************************************************** +// +//! \brief Set specific bits in 4 x 8 bit ADI slave registers. +//! +//! This function will set bits in 4 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in 4 consecutive 8 bit registers in the +//! ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to set in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsSet(), ADI16BitsSet() +// +//***************************************************************************** +__STATIC_INLINE void +ADI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_SET; + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + (ui32Reg & 0xFC), ui32Val, 4); + } else { + HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val; + } +} + +//***************************************************************************** +// +//! \brief Clear specific bits in an 8 bit ADI register. +//! +//! This function will clear bits in a register in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to clear bits in a specific 8 bit register in +//! the ADI slave. Only bits in the selected register are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui8Val is the 8 bit one-hot encoded value specifying which +//! bits to clear in the register. +//! +//! \return None +//! +//! \sa ADI16BitsClear(), ADI32BitsClear() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_CLR; + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + ui32Reg, ui8Val, 1); + } else { + HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val; + } +} + +//***************************************************************************** +// +//! \brief Clear specific bits in two 8 bit ADI register. +//! +//! This function will clear bits in 2 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to clear bits in 2 consecutive 8 bit registers in +//! the ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui16Val is the 16 bit one-hot encoded value specifying which +//! bits to clear in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsClear(), ADI32BitsClear() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_CLR; + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + (ui32Reg & 0xFE), ui16Val, 2); + } else { + HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val; + } +} + +//***************************************************************************** +// +//! \brief Clear specific bits in four 8 bit ADI register. +//! +//! This function will clear bits in 4 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to clear bits in 4 consecutive 8 bit registers in +//! the ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to clear in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsClear(), ADI16BitsClear() +// +//***************************************************************************** +__STATIC_INLINE void +ADI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_CLR; + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + (ui32Reg & 0xFC), ui32Val, 4); + } else { + HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val; + } +} + +//***************************************************************************** +// +//! \brief Set a value on any 4 bits inside an 8 bit register in the ADI slave. +//! +//! This function allows halfbyte (4 bit) access to the ADI slave registers. +//! The parameter \c bWriteHigh determines whether to write to the lower +//! or higher part of the 8 bit register. +//! +//! Use this function to write any value in the range 0-3 bits aligned on a +//! half byte boundary. Fx. for writing the value 0b101 to bits 1 to 3 the +//! \c ui8Val = 0xA and the \c ui8Mask = 0xE. Bit 0 will not be affected by +//! the operation, as the corresponding bit is not set in the \c ui8Mask. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the ADI port. +//! \param ui32Reg is the Least Significant Register in the ADI slave that +//! will be affected by the write operation. +//! \param bWriteHigh defines which part of the register to write in. +//! - \c true: Write upper half byte of register. +//! - \c false: Write lower half byte of register. +//! \param ui8Mask is the mask defining which of the 4 bits that should be +//! overwritten. The mask must be defined in the lower half of the 8 bits of +//! the parameter. +//! \param ui8Val is the value to write. The value must be defined in the lower +//! half of the 8 bits of the parameter. +//! +//! \return None +//! +//! \sa ADI8SetValBit(), ADI16SetValBit +// +//***************************************************************************** +__STATIC_INLINE void +ADI4SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh, + uint8_t ui8Mask, uint8_t ui8Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + ASSERT(!(ui8Val & 0xF0)); + ASSERT(!(ui8Mask & 0xF0)); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_MASK4B + (ui32Reg << 1) + (bWriteHigh ? 1 : 0); + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset, (ui8Mask << 4) | ui8Val, 1); + } else { + HWREGB(ui32Base + ui32RegOffset) = (ui8Mask << 4) | ui8Val; + } +} + +//***************************************************************************** +// +//! \brief Set a value on any bits inside an 8 bit register in the ADI slave. +//! +//! This function allows byte (8 bit) access to the ADI slave registers. +//! +//! Use this function to write any value in the range 0-7 bits aligned on a +//! byte boundary. Fx. for writing the value 0b101 to bits 1 and 3 the +//! \c ui16Val = 0x0A and the \c ui16Mask = 0x0E. Bits 0 and 5-7 will not be affected +//! by the operation, as the corresponding bits are not set in the +//! \c ui16Mask. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the ADI port. +//! \param ui32Reg is the Least Significant Register in the ADI slave that +//! will be affected by the write operation. +//! \param ui16Mask is the mask defining which of the 8 bit that should be +//! overwritten. The mask must be defined in the lower half of the 16 bits. +//! \param ui16Val is the value to write. The value must be defined in the lower +//! half of the 16 bits. +//! +//! \return None +//! +//! \sa ADI4SetValBit(), ADI16SetValBit() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Mask, + uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + ASSERT(!(ui16Val & 0xFF00)); + ASSERT(!(ui16Mask & 0xFF00)); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_MASK8B + (ui32Reg << 1); + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset, (ui16Mask << 8) | ui16Val, 2); + } else { + HWREGH(ui32Base + ui32RegOffset) = (ui16Mask << 8) | ui16Val; + } +} + +//***************************************************************************** +// +//! \brief Set a value on any bits inside an 2 x 8 bit register aligned on a +//! half-word (byte) boundary in the ADI slave. +//! +//! This function allows 2 byte (16 bit) access to the ADI slave registers. +//! +//! Use this function to write any value in the range 0-15 bits aligned on a +//! half-word (byte) boundary. Fx. for writing the value 0b101 to bits 1 and 3 the +//! \c ui32Val = 0x000A and the \c ui32Mask = 0x000E. Bits 0 and 5-15 will not +//! be affected by the operation, as the corresponding bits are not set +//! in the \c ui32Mask. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the ADI port. +//! \param ui32Reg is the Least Significant Register in the ADI slave that +//! will be affected by the write operation. +//! \param ui32Mask is the mask defining which of the 16 bit that should be +//! overwritten. The mask must be defined in the lower half of the 32 bits. +//! \param ui32Val is the value to write. The value must be defined in the lower +//! half of the 32 bits. +//! +//! \return None +//! +//! \sa ADI4SetValBit(), ADI8SetValBit() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, + uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + ASSERT(!(ui32Val & 0xFFFF0000)); + ASSERT(!(ui32Mask & 0xFFFF0000)); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_MASK16B + ((ui32Reg << 1) & 0xFC); + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset, (ui32Mask << 16) | ui32Val, 4); + } else { + HWREG(ui32Base + ui32RegOffset) = (ui32Mask << 16) | ui32Val; + } +} + +//***************************************************************************** +// +// SafeHapiVoid() and SafeHapiAuxAdiSelect() +// Common wrapper functions for the Hapi functions needing workaround for the +// "bus arbitration" issue. +// +//***************************************************************************** +void SafeHapiVoid( FPTR_VOID_VOID_T fPtr ); +void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ADI_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi_doc.h new file mode 100644 index 0000000..5543464 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi_doc.h @@ -0,0 +1,68 @@ +/****************************************************************************** +* Filename: adi_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup adi_api +//! @{ +//! \section sec_adi Introduction +//! \n +//! +//! \section sec_adi_api API +//! +//! The API functions can be grouped like this: +//! +//! Write: +//! - Direct (all bits): +//! - \ref ADI8RegWrite() +//! - \ref ADI16RegWrite() +//! - \ref ADI32RegWrite() +//! - Set individual bits: +//! - \ref ADI8BitsSet() +//! - \ref ADI16BitsSet() +//! - \ref ADI32BitsSet() +//! - Clear individual bits: +//! - \ref ADI8BitsClear() +//! - \ref ADI16BitsClear() +//! - \ref ADI32BitsClear() +//! - Masked: +//! - \ref ADI4SetValBit() +//! - \ref ADI8SetValBit() +//! - \ref ADI16SetValBit() +//! +//! Read: +//! - \ref ADI8RegRead() +//! - \ref ADI16RegRead() +//! - \ref ADI32RegRead() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aes.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aes.c new file mode 100644 index 0000000..4b2c0b5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aes.c @@ -0,0 +1,372 @@ + +/****************************************************************************** +* Filename: crypto.c +* Revised: 2019-01-25 13:11:50 +0100 (Fri, 25 Jan 2019) +* Revision: 54285 +* +* Description: Driver for the aes functions of the crypto module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aes.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AESStartDMAOperation + #define AESStartDMAOperation NOROM_AESStartDMAOperation + #undef AESSetInitializationVector + #define AESSetInitializationVector NOROM_AESSetInitializationVector + #undef AESWriteCCMInitializationVector + #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector + #undef AESReadTag + #define AESReadTag NOROM_AESReadTag + #undef AESVerifyTag + #define AESVerifyTag NOROM_AESVerifyTag + #undef AESWriteToKeyStore + #define AESWriteToKeyStore NOROM_AESWriteToKeyStore + #undef AESReadFromKeyStore + #define AESReadFromKeyStore NOROM_AESReadFromKeyStore + #undef AESWaitForIRQFlags + #define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags + #undef AESConfigureCCMCtrl + #define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl +#endif + + + +//***************************************************************************** +// +// Load the initialization vector. +// +//***************************************************************************** +void AESSetInitializationVector(const uint32_t *initializationVector) +{ + // Write initialization vector to the aes registers + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = initializationVector[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = initializationVector[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = initializationVector[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = initializationVector[3]; +} + +//***************************************************************************** +// +// Start a crypto DMA operation. +// +//***************************************************************************** +void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) +{ + if (channel0Length && channel0Addr) { + // We actually want to perform an operation. Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; // This might need AES_IRQEN_DMA_IN_DONE as well + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; + } + + if (channel1Length && channel1Addr) { + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; + } +} + +//***************************************************************************** +// +// Poll the IRQ status register and return. +// +//***************************************************************************** +uint32_t AESWaitForIRQFlags(uint32_t irqFlags) +{ + uint32_t irqTrigger = 0; + // Wait for the DMA operation to complete. Add a delay to make sure we are + // not flooding the bus with requests too much. + do { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | + CRYPTO_IRQSTAT_RESULT_AVAIL_M | + CRYPTO_IRQSTAT_DMA_BUS_ERR_M | + CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M))); + + // Save the IRQ trigger source + irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags; + + // Clear IRQ flags + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqTrigger; + + return irqTrigger; +} + +//***************************************************************************** +// +// Transfer a key from CM3 memory to a key store location. +// +//***************************************************************************** +uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea) +{ + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + ASSERT((aesKeyLength == AES_128_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_192_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_256_KEY_LENGTH_BYTES)); + + uint32_t keySize = 0; + + switch (aesKeyLength) { + case AES_128_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_128_BIT; + break; + case AES_192_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_192_BIT; + break; + case AES_256_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_256_BIT; + break; + } + + // Clear any previously written key at the keyLocation + AESInvalidateKey(keyStoreArea); + + // Disable the external interrupt to stop the interrupt form propagating + // from the module to the System CPU. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE_M | CRYPTO_IRQEN_RESULT_AVAIL_M; + + // Configure master control module. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_KEY_STORE; + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQCLR_RESULT_AVAIL); + + // Configure the size of keys contained within the key store + // Do not write to the register if the correct key size is already set. + // Writing to this register causes all current keys to be invalidated. + uint32_t keyStoreKeySize = HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE); + if (keySize != keyStoreKeySize) { + HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = keySize; + } + + // Enable key to write (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = 1 << keyStoreArea; + + // Total key length in bytes (16 for 1 x 128-bit key and 32 for 1 x 256-bit key). + AESStartDMAOperation(aesKey, aesKeyLength, 0, 0); + + // Wait for the DMA operation to complete. + uint32_t irqTrigger = AESWaitForIRQFlags(CRYPTO_IRQCLR_RESULT_AVAIL | CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQSTAT_DMA_BUS_ERR | CRYPTO_IRQSTAT_KEY_ST_WR_ERR); + + // Re-enable interrupts globally. + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // If we had a bus error or the key is not in the CRYPTO_O_KEYWRITTENAREA, return an error. + if ((irqTrigger & (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M)) || !(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + // There was an error in writing to the keyStore. + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +//***************************************************************************** +// +// Transfer a key from the keyStoreArea to the internal buffer of the module. +// +//***************************************************************************** +uint32_t AESReadFromKeyStore(uint32_t keyStoreArea) +{ + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + // Check if there is a valid key in the specified keyStoreArea + if (!(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + return AES_KEYSTORE_AREA_INVALID; + } + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = keyStoreArea; + + // Wait until key is loaded to the AES module. + // We cannot simply poll the IRQ status as only an error is communicated through + // the IRQ status and not the completion of the transfer. + do { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY_M)); + + // Check for keyStore read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M)) { + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +//***************************************************************************** +// +// Read the tag after a completed CCM, GCM, or CBC-MAC operation. +// +//***************************************************************************** +uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength) +{ + // The intermediate array is used instead of a caller-provided one + // to enable a simple API with no unintuitive alignment or size requirements. + // This is a trade-off of stack-depth vs ease-of-use that came out on the + // ease-of-use side. + uint32_t computedTag[AES_BLOCK_SIZE / sizeof(uint32_t)]; + + // Wait until the computed tag is ready. + while (!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M)); + + // Read computed tag out from the HW registers + // Need to read out all 128 bits in four reads to correctly clear CRYPTO_AESCTL_SAVED_CONTEXT_RDY flag + computedTag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); + computedTag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); + computedTag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); + computedTag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); + + memcpy(tag, computedTag, tagLength); + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Verify the provided tag against the computed tag after a completed CCM or +// GCM operation. +// +//***************************************************************************** +uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength) +{ + uint32_t resultStatus; + // The intermediate array is allocated on the stack to ensure users do not + // point the tag they provide and the one computed at the same location. + // That would cause memcmp to compare an array against itself. We could add + // a check that verifies that the arrays are not the same. If we did that and + // modified AESReadTag to just copy all 128 bits into a provided array, + // we could save 16 bytes of stack space while making the API much more + // complicated. + uint8_t computedTag[AES_BLOCK_SIZE]; + + resultStatus = AESReadTag(computedTag, tagLength); + + if (resultStatus != AES_SUCCESS) { + return resultStatus; + } + + resultStatus = memcmp(computedTag, tag, tagLength); + + if (resultStatus != 0) { + return AES_TAG_VERIFICATION_FAILED; + } + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Configure the AES module for CCM mode +// +//***************************************************************************** +void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt) +{ + uint32_t ctrlVal = 0; + + ctrlVal = ((15 - nonceLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if ( macLength >= 2 ) { + ctrlVal |= ((( macLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); + } + ctrlVal |= CRYPTO_AESCTL_CCM | + CRYPTO_AESCTL_CTR | + CRYPTO_AESCTL_SAVE_CONTEXT | + CRYPTO_AESCTL_CTR_WIDTH_128_BIT; + ctrlVal |= encrypt ? CRYPTO_AESCTL_DIR : 0; + + AESSetCtrl(ctrlVal); +} + +//***************************************************************************** +// +// Configure an IV for CCM mode of operation +// +//***************************************************************************** +void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength) +{ + union { + uint32_t word[4]; + uint8_t byte[16]; + } initializationVector = {{0}}; + + initializationVector.byte[0] = 15 - nonceLength - 1; + + memcpy(&(initializationVector.byte[1]), nonce, nonceLength); + + AESSetInitializationVector(initializationVector.word); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aes.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aes.h new file mode 100644 index 0000000..eb199a4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aes.h @@ -0,0 +1,843 @@ +/****************************************************************************** +* Filename: aes.h +* Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019) +* Revision: 54287 +* +* Description: AES header file. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup aes_api +//! @{ +// +//***************************************************************************** + +#ifndef __AES_H__ +#define __AES_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_crypto.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AESStartDMAOperation NOROM_AESStartDMAOperation + #define AESSetInitializationVector NOROM_AESSetInitializationVector + #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector + #define AESReadTag NOROM_AESReadTag + #define AESVerifyTag NOROM_AESVerifyTag + #define AESWriteToKeyStore NOROM_AESWriteToKeyStore + #define AESReadFromKeyStore NOROM_AESReadFromKeyStore + #define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags + #define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl +#endif + + +//***************************************************************************** +// +// Values that can be passed to AESIntEnable, AESIntDisable, and AESIntClear +// as the intFlags parameter, and returned from AESIntStatus. +// Only AES_DMA_IN_DONE and AES_RESULT_RDY are routed to the NVIC. Check each +// function to see if it supports other interrupt status flags. +// +//***************************************************************************** +#define AES_DMA_IN_DONE CRYPTO_IRQEN_DMA_IN_DONE_M +#define AES_RESULT_RDY CRYPTO_IRQEN_RESULT_AVAIL_M +#define AES_DMA_BUS_ERR CRYPTO_IRQCLR_DMA_BUS_ERR_M +#define AES_KEY_ST_WR_ERR CRYPTO_IRQCLR_KEY_ST_WR_ERR_M +#define AES_KEY_ST_RD_ERR CRYPTO_IRQCLR_KEY_ST_RD_ERR_M + + +//***************************************************************************** +// +// General constants +// +//***************************************************************************** + +// AES module return codes +#define AES_SUCCESS 0 +#define AES_KEYSTORE_ERROR 1 +#define AES_KEYSTORE_AREA_INVALID 2 +#define AES_DMA_BUSY 3 +#define AES_DMA_ERROR 4 +#define AES_TAG_NOT_READY 5 +#define AES_TAG_VERIFICATION_FAILED 6 + +// Key store module defines +#define AES_IV_LENGTH_BYTES 16 +#define AES_TAG_LENGTH_BYTES 16 +#define AES_128_KEY_LENGTH_BYTES (128 / 8) +#define AES_192_KEY_LENGTH_BYTES (192 / 8) +#define AES_256_KEY_LENGTH_BYTES (256 / 8) + +#define AES_BLOCK_SIZE 16 + +// DMA status codes +#define AES_DMA_CHANNEL0_ACTIVE CRYPTO_DMASTAT_CH0_ACT_M +#define AES_DMA_CHANNEL1_ACTIVE CRYPTO_DMASTAT_CH1_ACT_M +#define AES_DMA_PORT_ERROR CRYPTO_DMASTAT_PORT_ERR_M + +// Crypto module operation types +#define AES_ALGSEL_AES CRYPTO_ALGSEL_AES_M +#define AES_ALGSEL_KEY_STORE CRYPTO_ALGSEL_KEY_STORE_M +#define AES_ALGSEL_TAG CRYPTO_ALGSEL_TAG_M + + +//***************************************************************************** +// +// For 128-bit keys, all 8 key area locations from 0 to 7 are valid. +// A 256-bit key requires two consecutive Key Area locations. The base key area +// may be odd. Do not attempt to write a 256-bit key to AES_KEY_AREA_7. +// +//***************************************************************************** +#define AES_KEY_AREA_0 0 +#define AES_KEY_AREA_1 1 +#define AES_KEY_AREA_2 2 +#define AES_KEY_AREA_3 3 +#define AES_KEY_AREA_4 4 +#define AES_KEY_AREA_5 5 +#define AES_KEY_AREA_6 6 +#define AES_KEY_AREA_7 7 + +//***************************************************************************** +// +// Defines for the AES-CTR mode counter width +// +//***************************************************************************** +#define AES_CTR_WIDTH_32 0x0 +#define AES_CTR_WIDTH_64 0x1 +#define AES_CTR_WIDTH_96 0x2 +#define AES_CTR_WIDTH_128 0x3 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Start a crypto DMA operation +//! +//! Enable the crypto DMA channels, configure the channel addresses, +//! and set the length of the data transfer. +//! Setting the length of the data transfer automatically starts the +//! transfer. It is also used by the hardware module as a signal to +//! begin the encryption, decryption, or MAC operation. +//! +//! \param [in] channel0Addr A pointer to the address channel 0 shall use. +//! +//! \param [in] channel0Length Length of the data in bytes to be read from or +//! written to at channel0Addr. Set to 0 to not set up +//! this channel. Permitted ranges are mode dependent +//! and displayed below. +//! - ECB: [16] +//! - CBC: [1, sizeof(RAM)] +//! - CBC-MAC: [1, sizeof(RAM)] +//! - CCM: [1, sizeof(RAM)] +//! +//! \param [out] channel1Addr A pointer to the address channel 1 shall use. +//! +//! \param [in] channel1Length Length of the data in bytes to be read from or +//! written to at channel1Addr. Set to 0 to not set up +//! this channel.Permitted ranges are mode dependent +//! and displayed below. +//! - ECB: [16] +//! - CBC: [1, sizeof(RAM)] +//! - CBC-MAC: [1, sizeof(RAM)] +//! - CCM: [1, sizeof(RAM)] +//! +//! \return None +// +//***************************************************************************** +extern void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length); + +//***************************************************************************** +// +//! \brief Write the initialization vector (IV) to the crypto module. +//! +//! Depending on the mode of operation, the tag must be constructed +//! differently: +//! - CBC: No special care must be taken. Any 128-bit IV +//! (initialization vector) will suffice. +//! - CBC-MAC: IV's must be all 0's. +//! - CCM: Only 12 and 13 byte IV's are permitted. See code +//! below for formatting. +//! \code +//! uint8_t initVectorLength = 12; // Could also be 13 +//! +//! union { +//! uint32_t word[4]; +//! uint8_t byte[16]; +//! } initVector; +//! +//! uint8_t initVectorUnformatted[initVectorLength]; +//! +//! // This is the same field length value that is written to the ctrl register +//! initVector.byte[0] = L - 1; +//! +//! memcpy(&initVector.byte[1], initVectorUnformatted, initVectorLength); +//! +//! // Fill the remaining bytes with zeros +//! for (initVectorLength++; initVectorLength < sizeof(initVector.byte); initVectorLength++) { +//! initVector.byte[initVectorLength] = 0; +//! } +//! \endcode +//! +//! \param [in] initializationVector Pointer to an array with four 32-bit elements +//! to be used as initialization vector. +//! Elements of array must be word aligned in memory. +//! +//! \return None +// +//***************************************************************************** +extern void AESSetInitializationVector(const uint32_t *initializationVector); + +//***************************************************************************** +// +//! \brief Generate and load the initialization vector for a CCM operation. +//! +//! +//! \param [in] nonce Pointer to a nonce of length \c nonceLength. +//! +//! \param [in] nonceLength Number of bytes to copy from \c nonce when creating +//! the CCM IV. The L-value is also derived from it. +//! +//! \return None +// +//***************************************************************************** +extern void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength); + +//***************************************************************************** +// +//! \brief Read the tag out from the crypto module. +//! +//! This function copies the \c tagLength bytes from the tag calculated by the +//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag. +//! +//! \param [out] tag Pointer to an array of \c tagLength bytes. +//! +//! \param [in] tagLength Number of bytes to copy to \c tag. +//! +//! \return Returns a status code depending on the result of the transfer. +//! - \ref AES_TAG_NOT_READY if the tag is not ready yet +//! - \ref AES_SUCCESS otherwise +// +//***************************************************************************** +extern uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength); + +//***************************************************************************** +// +//! \brief Verifies the provided \c tag against calculated one +//! +//! This function compares the provided tag against the tag calculated by the +//! crypto module during the last CCM, GCM, or CBC-MAC +//! +//! This function copies the \c tagLength bytes from the tag calculated by the +//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag. +//! +//! \param [in] tag Pointer to an array of \c tagLength bytes. +//! +//! \param [in] tagLength Number of bytes to compare. +//! +//! \return Returns a status code depending on the result of the transfer. +//! - \ref AES_TAG_VERIFICATION_FAILED if the verification failed +//! - \ref AES_SUCCESS otherwise +// +//***************************************************************************** +extern uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength); + +//***************************************************************************** +// +//! \brief Transfer a key from main memory to a key area within the key store. +//! +//! The crypto DMA transfers the key and function does not return until +//! the operation completes. +//! The keyStore can only contain valid keys of one \c aesKeyLength at +//! any one point in time. The keyStore cannot contain both 128-bit and +//! 256-bit keys simultaneously. When a key of a different \c aesKeyLength +//! from the previous \c aesKeyLength is loaded, all previous keys are +//! invalidated. +//! +//! \param [in] aesKey Pointer to key. Does not need to be word-aligned. +//! +//! \param [in] aesKeyLength The key size in bytes. Currently, 128-bit, 192-bit, +//! and 256-bit keys are supported. +//! - \ref AES_128_KEY_LENGTH_BYTES +//! - \ref AES_192_KEY_LENGTH_BYTES +//! - \ref AES_256_KEY_LENGTH_BYTES +//! +//! \param [in] keyStoreArea The key store area to transfer the key to. +//! When using 128-bit keys, only the specified key store +//! area will be occupied. +//! When using 256-bit or 192-bit keys, two consecutive key areas +//! are used to store the key. +//! - \ref AES_KEY_AREA_0 +//! - \ref AES_KEY_AREA_1 +//! - \ref AES_KEY_AREA_2 +//! - \ref AES_KEY_AREA_3 +//! - \ref AES_KEY_AREA_4 +//! - \ref AES_KEY_AREA_5 +//! - \ref AES_KEY_AREA_6 +//! - \ref AES_KEY_AREA_7 +//! +//! When using 256-bit or 192-bit keys, the 8 \c keyStoreArea's are +//! split into four sets of two. Selecting any \c keyStoreArea automatically +//! occupies the second \c keyStoreArea of the tuples below: +//! +//! - (\ref AES_KEY_AREA_0, \ref AES_KEY_AREA_1) +//! - (\ref AES_KEY_AREA_2, \ref AES_KEY_AREA_3) +//! - (\ref AES_KEY_AREA_4, \ref AES_KEY_AREA_5) +//! - (\ref AES_KEY_AREA_6, \ref AES_KEY_AREA_7) +//! +//! For example: if \c keyStoreArea == \ref AES_KEY_AREA_2, +//! both \ref AES_KEY_AREA_2 and \ref AES_KEY_AREA_3 are occupied. +//! If \c keyStoreArea == \ref AES_KEY_AREA_5, both \ref AES_KEY_AREA_4 and \ref AES_KEY_AREA_5 are occupied. +//! +//! \return Returns a status code depending on the result of the transfer. +//! If there was an error in the read process itself, an error is +//! returned. +//! Otherwise, a success code is returned. +//! - \ref AES_KEYSTORE_ERROR +//! - \ref AES_SUCCESS +//! +//! \sa AESReadFromKeyStore +// +//***************************************************************************** +extern uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea); + +//***************************************************************************** +// +//! \brief Transfer a key from key store area to the internal buffers within +//! the hardware module. +//! +//! The function polls until the transfer is complete. +//! +//! \param [in] keyStoreArea The key store area to transfer the key from. When using +//! 256-bit keys, either of the occupied key areas may be +//! specified to load the key. There is no need to specify +//! the length of the key here as the key store keeps track +//! of how long a key associated with any valid key area is +//! and where is starts. +//! - \ref AES_KEY_AREA_0 +//! - \ref AES_KEY_AREA_1 +//! - \ref AES_KEY_AREA_2 +//! - \ref AES_KEY_AREA_3 +//! - \ref AES_KEY_AREA_4 +//! - \ref AES_KEY_AREA_5 +//! - \ref AES_KEY_AREA_6 +//! - \ref AES_KEY_AREA_7 +//! +//! \return Returns a status code depending on the result of the transfer. +//! When specifying a \c keyStoreArea value without a valid key in it an +//! error is returned. +//! If there was an error in the read process itself, an error is +//! returned. +//! Otherwise, a success code is returned. +//! - \ref AES_KEYSTORE_AREA_INVALID +//! - \ref AES_KEYSTORE_ERROR +//! - \ref AES_SUCCESS +//! +//! \sa AESWriteToKeyStore +// +//***************************************************************************** +extern uint32_t AESReadFromKeyStore(uint32_t keyStoreArea); + + +//***************************************************************************** +// +//! \brief Poll the interrupt status register and clear when done. +//! +//! This function polls until one of the bits in the \c irqFlags is +//! asserted. Only \ref AES_DMA_IN_DONE and \ref AES_RESULT_RDY can actually +//! trigger the interrupt line. That means that one of those should +//! always be included in \c irqFlags and will always be returned together +//! with any error codes. +//! +//! \param [in] irqFlags IRQ flags to poll and mask that the status register will be +//! masked with. May consist of any bitwise OR of the flags +//! below that includes at least one of +//! \ref AES_DMA_IN_DONE or \ref AES_RESULT_RDY : +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! - \ref AES_DMA_BUS_ERR +//! - \ref AES_KEY_ST_WR_ERR +//! - \ref AES_KEY_ST_RD_ERR +//! +//! \return Returns the IRQ status register masked with \c irqFlags. May be any +//! bitwise OR of the following masks: +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! - \ref AES_DMA_BUS_ERR +//! - \ref AES_KEY_ST_WR_ERR +//! - \ref AES_KEY_ST_RD_ERR +// +//***************************************************************************** +extern uint32_t AESWaitForIRQFlags(uint32_t irqFlags); + +//***************************************************************************** +// +//! \brief Configure AES engine for CCM operation. +//! +//! \param [in] nonceLength Length of the nonce. Must be <= 14. +//! +//! \param [in] macLength Length of the MAC. Must be <= 16. +//! +//! \param [in] encrypt Whether to set up an encrypt or decrypt operation. +//! - true: encrypt +//! - false: decrypt +//! +//! \return None +// +//***************************************************************************** +extern void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt); + +//***************************************************************************** +// +//! \brief Invalidate a key in the key store +//! +//! \param [in] keyStoreArea is the entry in the key store to invalidate. This +//! permanently deletes the key from the key store. +//! - \ref AES_KEY_AREA_0 +//! - \ref AES_KEY_AREA_1 +//! - \ref AES_KEY_AREA_2 +//! - \ref AES_KEY_AREA_3 +//! - \ref AES_KEY_AREA_4 +//! - \ref AES_KEY_AREA_5 +//! - \ref AES_KEY_AREA_6 +//! - \ref AES_KEY_AREA_7 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESInvalidateKey(uint32_t keyStoreArea) +{ + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + // Clear any previously written key at the key location + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << keyStoreArea); +} + +//***************************************************************************** +// +//! \brief Select type of operation +//! +//! \param [in] algorithm Flags that specify which type of operation the crypto +//! module shall perform. The flags are mutually exclusive. +//! - 0 : Reset the module +//! - \ref AES_ALGSEL_AES +//! - \ref AES_ALGSEL_TAG +//! - \ref AES_ALGSEL_KEY_STORE +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESSelectAlgorithm(uint32_t algorithm) +{ + ASSERT((algorithm == AES_ALGSEL_AES) || + (algorithm == AES_ALGSEL_AES | AES_ALGSEL_TAG) || + (algorithm == AES_ALGSEL_KEY_STORE)); + + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm; +} + +//***************************************************************************** +// +//! \brief Set up the next crypto module operation. +//! +//! The function uses a bitwise OR of the fields within the CRYPTO_O_AESCTL +//! register. The relevant field names have the format: +//! - CRYPTO_AESCTL_[field name] +//! +//! \param [in] ctrlMask Specifies which register fields shall be set. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESSetCtrl(uint32_t ctrlMask) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ctrlMask; +} + +//***************************************************************************** +// +//! \brief Specify length of the crypto operation. +//! +//! Despite specifying it here, the crypto DMA must still be +//! set up with the correct data length. +//! +//! \param [in] length Data length in bytes. If this +//! value is set to 0, only authentication of the AAD is +//! performed in CCM-mode and AESWriteAuthLength() must be set to +//! >0. +//! Range depends on the mode: +//! - ECB: [16] +//! - CBC: [1, sizeof(RAM)] +//! - CBC-MAC: [1, sizeof(RAM)] +//! - CCM: [0, sizeof(RAM)] +//! +//! \return None +//! +//! \sa AESWriteAuthLength +// +//***************************************************************************** +__STATIC_INLINE void AESSetDataLength(uint32_t length) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = length; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; +} + +//***************************************************************************** +// +//! \brief Specify the length of the additional authentication data (AAD). +//! +//! Despite specifying it here, the crypto DMA must still be set up with +//! the correct AAD length. +//! +//! \param [in] length Specifies how long the AAD is in a CCM operation. In CCM mode, +//! set this to 0 if no AAD is required. If set to 0, +//! AESWriteDataLength() must be set to >0. +//! Range depends on the mode: +//! - ECB: Do not call. +//! - CBC: [0] +//! - CBC-MAC: [0] +//! - CCM: [0, sizeof(RAM)] +//! +//! \return None +//! +//! \sa AESWriteDataLength +// +//***************************************************************************** +__STATIC_INLINE void AESSetAuthLength(uint32_t length) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = length; +} + +//***************************************************************************** +// +//! \brief Reset the accelerator and cancel ongoing operations +//! +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESReset(void) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_SWRESET) = 0x00000001; +} + +//***************************************************************************** +// +//! \brief Enable individual crypto interrupt sources. +//! +//! This function enables the indicated crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESIntEnable(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & AES_DMA_IN_DONE) || + (intFlags & AES_RESULT_RDY)); + + // Using level interrupt. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; + + // Enable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; +} + +//***************************************************************************** +// +//! \brief Disable individual crypto interrupt sources. +//! +//! This function disables the indicated crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESIntDisable(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & AES_DMA_IN_DONE) || + (intFlags & AES_RESULT_RDY)); + + // Disable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; +} + +//***************************************************************************** +// +//! \brief Get the current masked interrupt status. +//! +//! This function returns the masked interrupt status of the crypto module. +//! +//! \return Returns the status of the masked lines when enabled: +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +// +//***************************************************************************** +__STATIC_INLINE uint32_t AESIntStatusMasked(void) +{ + uint32_t mask; + + // Return the masked interrupt status + mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); + return(mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); +} + +//***************************************************************************** +// +//! \brief Get the current raw interrupt status. +//! +//! This function returns the raw interrupt status of the crypto module. +//! It returns both the status of the lines routed to the NVIC as well as the +//! error flags. +//! +//! \return Returns the raw interrupt status: +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! - \ref AES_DMA_BUS_ERR +//! - \ref AES_KEY_ST_WR_ERR +//! - \ref AES_KEY_ST_RD_ERR +// +//***************************************************************************** +__STATIC_INLINE uint32_t AESIntStatusRaw(void) +{ + // Return either the raw interrupt status + return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); +} + +//***************************************************************************** +// +//! \brief Clear crypto interrupt sources. +//! +//! The specified crypto interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in the module until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! +//! \param [in] intFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESIntClear(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & AES_DMA_IN_DONE) || + (intFlags & AES_RESULT_RDY)); + + // Clear the requested interrupt sources, + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = intFlags; +} + +//***************************************************************************** +// +//! \brief Register an interrupt handler for a crypto interrupt. +//! +//! This function does the actual registering of the interrupt handler. This +//! function enables the global interrupt in the interrupt controller; specific +//! crypto interrupts must be enabled via \ref AESIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param handlerFxn is a pointer to the function to be called when the +//! crypto interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void AESIntRegister(void (*handlerFxn)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, handlerFxn); + + // Enable the crypto interrupt. + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregister an interrupt handler for a crypto interrupt. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler called when a crypto interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void AESIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AESStartDMAOperation + #undef AESStartDMAOperation + #define AESStartDMAOperation ROM_AESStartDMAOperation + #endif + #ifdef ROM_AESSetInitializationVector + #undef AESSetInitializationVector + #define AESSetInitializationVector ROM_AESSetInitializationVector + #endif + #ifdef ROM_AESWriteCCMInitializationVector + #undef AESWriteCCMInitializationVector + #define AESWriteCCMInitializationVector ROM_AESWriteCCMInitializationVector + #endif + #ifdef ROM_AESReadTag + #undef AESReadTag + #define AESReadTag ROM_AESReadTag + #endif + #ifdef ROM_AESVerifyTag + #undef AESVerifyTag + #define AESVerifyTag ROM_AESVerifyTag + #endif + #ifdef ROM_AESWriteToKeyStore + #undef AESWriteToKeyStore + #define AESWriteToKeyStore ROM_AESWriteToKeyStore + #endif + #ifdef ROM_AESReadFromKeyStore + #undef AESReadFromKeyStore + #define AESReadFromKeyStore ROM_AESReadFromKeyStore + #endif + #ifdef ROM_AESWaitForIRQFlags + #undef AESWaitForIRQFlags + #define AESWaitForIRQFlags ROM_AESWaitForIRQFlags + #endif + #ifdef ROM_AESConfigureCCMCtrl + #undef AESConfigureCCMCtrl + #define AESConfigureCCMCtrl ROM_AESConfigureCCMCtrl + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AES_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_batmon.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_batmon.c new file mode 100644 index 0000000..e5037dc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_batmon.c @@ -0,0 +1,80 @@ +/****************************************************************************** +* Filename: aon_batmon.c +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Driver for the AON Battery and Temperature Monitor +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_batmon.h" +#include "../inc/hw_fcfg1.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONBatMonTemperatureGetDegC + #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC +#endif + +//***************************************************************************** +// +// AONBatMonTemperatureGetDegC() +// Returns sign extended temperature in Deg C (-256 .. +255) +// +//***************************************************************************** +int32_t +AONBatMonTemperatureGetDegC( void ) +{ + int32_t signedTemp ; // Signed extended temperature with 8 fractional bits + int32_t tempCorrection ; // Voltage dependent temp correction with 8 fractional bits + int8_t voltageSlope ; // Signed byte value representing the TEMP slope with battery voltage, in degrees C/V, with 4 fractional bits. + + // Shift left then right to sign extend the BATMON_TEMP field + signedTemp = ((((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_TEMP )) + << ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )) + >> ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )); + + // Typecasting voltageSlope to int8_t prior to assignment in order to make sure sign extension works properly + // Using byte read (HWREGB) in order to make more efficient code since voltageSlope is assigned to bits[7:0] of FCFG1_O_MISC_TRIM + voltageSlope = ((int8_t)HWREGB( FCFG1_BASE + FCFG1_O_MISC_TRIM )); + tempCorrection = (( voltageSlope * (((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT )) - 0x300 )) >> 4 ); + + return ((( signedTemp - tempCorrection ) + 0x80 ) >> 8 ); +} + + +// See aon_batmon.h for implementation of remaining functions diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_batmon.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_batmon.h new file mode 100644 index 0000000..ce7d323 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_batmon.h @@ -0,0 +1,306 @@ +/****************************************************************************** +* Filename: aon_batmon.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the AON Battery and Temperature +* Monitor +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonbatmon_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_BATMON_H__ +#define __AON_BATMON_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_batmon.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC +#endif + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enable the temperature and battery monitoring. +//! +//! This function will enable the measurements of the temperature and the +//! battery voltage. +//! +//! To speed up the measurement of the levels the measurement can be enabled +//! before configuring the battery and temperature settings. When all of the +//! AON_BATMON registers are configured, the calculation of the voltage and +//! temperature values can be enabled (the measurement will now take +//! effect/propagate to other blocks). +//! +//! It is possible to enable both at the same time, after the AON_BATMON +//! registers are configured, but then the first values will be ready at a +//! later point compared to the scenario above. +//! +//! \note Temperature and battery voltage measurements are not done in +//! parallel. The measurement cycle is controlled by a hardware Finite State +//! Machine. First the temperature and then the battery voltage each taking +//! one cycle to complete. However, if the comparator measuring the battery +//! voltage detects a change on the reference value, a new measurement of the +//! battery voltage only is performed immediately after. This has no impact on +//! the cycle count. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONBatMonEnable(void) +{ + // Enable the measurements. + HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = + AON_BATMON_CTL_CALC_EN | + AON_BATMON_CTL_MEAS_EN; +} + +//***************************************************************************** +// +//! \brief Disable the temperature and battery monitoring. +//! +//! This function will disable the measurements of the temperature and the +//! battery voltage. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONBatMonDisable(void) +{ + // Disable the measurements. + HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = 0; +} + + +//***************************************************************************** +// +//! \brief Get the current temperature measurement as a signed value in Deg Celsius. +//! +//! This function returns an calibrated and rounded value in degree Celsius. +//! The temperature measurements are updated every cycle. +//! +//! \note The temperature drifts slightly depending on the battery voltage. +//! This function compensates for this drift and returns a calibrated temperature. +//! +//! \note Use the function AONBatMonNewTempMeasureReady() to test for a new measurement. +//! +//! \return Returns signed integer part of temperature in Deg C (-256 .. +255) +//! +//! \sa AONBatMonNewTempMeasureReady() +// +//***************************************************************************** +extern int32_t AONBatMonTemperatureGetDegC( void ); + +//***************************************************************************** +// +//! \brief Get the battery monitor measurement. +//! +//! This function will return the current battery monitor measurement. +//! The battery voltage measurements are updated every cycle. +//! +//! \note The returned value is NOT sign-extended! +//! +//! \note Use the function \ref AONBatMonNewBatteryMeasureReady() to test for +//! a change in measurement. +//! +//! \return Returns the current battery monitor value of the battery voltage +//! measurement in a format size <3.8> in units of volt. +//! +//! \sa AONBatMonNewBatteryMeasureReady() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONBatMonBatteryVoltageGet(void) +{ + uint32_t ui32CurrentBattery; + + ui32CurrentBattery = HWREG(AON_BATMON_BASE + AON_BATMON_O_BAT); + + // Return the current battery voltage measurement. + return (ui32CurrentBattery >> AON_BATMON_BAT_FRAC_S); +} + +//***************************************************************************** +// +//! \brief Check if battery monitor measurement has changed. +//! +//! This function checks if a new battery monitor value is available. If the +//! measurement value has \b changed since last clear the function returns \c true. +//! +//! If the measurement has changed the function will automatically clear the +//! status bit. +//! +//! \note It is always possible to read out the current value of the +//! battery level using AONBatMonBatteryVoltageGet() but this function can be +//! used to check if the measurement has changed. +//! +//! \return Returns \c true if the measurement value has changed and \c false +//! otherwise. +//! +//! \sa AONBatMonNewTempMeasureReady(), AONBatMonBatteryVoltageGet() +// +//***************************************************************************** +__STATIC_INLINE bool +AONBatMonNewBatteryMeasureReady(void) +{ + bool bStatus; + + // Check the status bit. + bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) & + AON_BATMON_BATUPD_STAT ? true : false; + + // Clear status bit if set. + if(bStatus) + { + HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) = 1; + } + + // Return status. + return (bStatus); +} + +//***************************************************************************** +// +//! \brief Check if temperature monitor measurement has changed. +//! +//! This function checks if a new temperature value is available. If the +//! measurement value has \b changed since last clear the function returns \c true. +//! +//! If the measurement has changed the function will automatically clear the +//! status bit. +//! +//! \note It is always possible to read out the current value of the +//! temperature using \ref AONBatMonTemperatureGetDegC() +//! but this function can be used to check if the measurement has changed. +//! +//! \return Returns \c true if the measurement value has changed and \c false +//! otherwise. +//! +//! \sa AONBatMonNewBatteryMeasureReady(), AONBatMonTemperatureGetDegC() +// +//***************************************************************************** +__STATIC_INLINE bool +AONBatMonNewTempMeasureReady(void) +{ + bool bStatus; + + // Check the status bit. + bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) & + AON_BATMON_TEMPUPD_STAT ? true : false; + + // Clear status bit if set. + if(bStatus) + { + HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) = 1; + } + + // Return status. + return (bStatus); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONBatMonTemperatureGetDegC + #undef AONBatMonTemperatureGetDegC + #define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_BATMON_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event.c new file mode 100644 index 0000000..0e1559b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event.c @@ -0,0 +1,299 @@ +/****************************************************************************** +* Filename: aon_event.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the AON Event fabric. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_event.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONEventMcuWakeUpSet + #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet + #undef AONEventMcuWakeUpGet + #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet + #undef AONEventAuxWakeUpSet + #define AONEventAuxWakeUpSet NOROM_AONEventAuxWakeUpSet + #undef AONEventAuxWakeUpGet + #define AONEventAuxWakeUpGet NOROM_AONEventAuxWakeUpGet + #undef AONEventMcuSet + #define AONEventMcuSet NOROM_AONEventMcuSet + #undef AONEventMcuGet + #define AONEventMcuGet NOROM_AONEventMcuGet +#endif + +//***************************************************************************** +// +// Select event source for the specified MCU wakeup programmable event +// +//***************************************************************************** +void +AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT((ui32MCUWUEvent == AON_EVENT_MCU_WU0) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU1) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU2) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU3)); + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL); + + if(ui32MCUWUEvent == AON_EVENT_MCU_WU0) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU0_EV_S; + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU1) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU1_EV_S; + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU2) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU2_EV_S; + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU3) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU3_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU3_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) = ui32Ctrl; +} + +//***************************************************************************** +// +// Get event source for the specified MCU wakeup programmable event +// +//***************************************************************************** +uint32_t +AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent) +{ + uint32_t ui32EventSrc; + + // Check the arguments. + ASSERT((ui32MCUWUEvent == AON_EVENT_MCU_WU0) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU1) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU2) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU3)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL); + + if(ui32MCUWUEvent == AON_EVENT_MCU_WU0) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU0_EV_M) >> + AON_EVENT_MCUWUSEL_WU0_EV_S); + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU1) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU1_EV_M) >> + AON_EVENT_MCUWUSEL_WU1_EV_S); + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU2) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU2_EV_M) >> + AON_EVENT_MCUWUSEL_WU2_EV_S); + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU3) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU3_EV_M) >> + AON_EVENT_MCUWUSEL_WU3_EV_S); + } + + // Should never get to this statement, but suppress warning. + ASSERT(0); + return(0); +} + +//***************************************************************************** +// +// Select event source for the specified AUX wakeup programmable event +// +//***************************************************************************** +void +AONEventAuxWakeUpSet(uint32_t ui32AUXWUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT((ui32AUXWUEvent == AON_EVENT_AUX_WU0) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU1) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU2)); + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL); + + if(ui32AUXWUEvent == AON_EVENT_AUX_WU0) + { + ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU0_EV_S; + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU1) + { + ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU1_EV_S; + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU2) + { + ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU2_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL) = ui32Ctrl; +} + +//***************************************************************************** +// +// Get event source for the specified AUX wakeup programmable event +// +//***************************************************************************** +uint32_t +AONEventAuxWakeUpGet(uint32_t ui32AUXWUEvent) +{ + uint32_t ui32EventSrc; + + // Check the arguments. + ASSERT((ui32AUXWUEvent == AON_EVENT_AUX_WU0) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU1) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU2)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL); + + if(ui32AUXWUEvent == AON_EVENT_AUX_WU0) + { + return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU0_EV_M) >> + AON_EVENT_AUXWUSEL_WU0_EV_S); + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU1) + { + return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU1_EV_M) >> + AON_EVENT_AUXWUSEL_WU1_EV_S); + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU2) + { + return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU2_EV_M) >> + AON_EVENT_AUXWUSEL_WU2_EV_S); + } + + // Should never get to this statement, but suppress warning. + ASSERT(0); + return(0); +} + +//***************************************************************************** +// +// Select event source for the specified programmable event forwarded to the +// MCU event fabric +// +//***************************************************************************** +void +AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL) = ui32Ctrl; +} + +//***************************************************************************** +// +// Get source for the specified programmable event forwarded to the MCU event +// fabric. +// +//***************************************************************************** +uint32_t +AONEventMcuGet(uint32_t ui32MCUEvent) +{ + uint32_t ui32EventSrc; + + // Check the arguments. + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S); + } + + // Should never get to this statement, but suppress warning. + ASSERT(0); + return(0); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event.h new file mode 100644 index 0000000..cdceba4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event.h @@ -0,0 +1,620 @@ +/****************************************************************************** +* Filename: aon_event.h +* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) +* Revision: 49506 +* +* Description: Defines and prototypes for the AON Event fabric. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonevent_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_EVENT_H__ +#define __AON_EVENT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_device.h" +#include "../inc/hw_aon_event.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet + #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet + #define AONEventAuxWakeUpSet NOROM_AONEventAuxWakeUpSet + #define AONEventAuxWakeUpGet NOROM_AONEventAuxWakeUpGet + #define AONEventMcuSet NOROM_AONEventMcuSet + #define AONEventMcuGet NOROM_AONEventMcuGet +#endif + +//***************************************************************************** +// +// Event sources for the event AON fabric. +// Note: Events are level-triggered active high +// +//***************************************************************************** +// AON_EVENT_DIO0 // Edge detect on DIO0. See hw_device.h +// ... // ... +// AON_EVENT_DIO31 // Edge detect on DIO31. See hw_device.h +#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC. + // Event ID 33 is reserved for future use + // Event ID 34 is reserved for future use +#define AON_EVENT_RTC_CH0 35 // RTC channel 0 +#define AON_EVENT_RTC_CH1 36 // RTC channel 1 +#define AON_EVENT_RTC_CH2 37 // RTC channel 2 +#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event +#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event +#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event +#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event +#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +#define AON_EVENT_JTAG 43 // JTAG generated event +#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0 +#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1 +#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2 +#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX) +#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX) +#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed +#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out +#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event +#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event +#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event +#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event +#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +#define AON_EVENT_AUX_COMPB_ASYNC_N 56 // Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B + // Event ID 57-62 is reserved for future use +#define AON_EVENT_NONE 63 // No event, always low + +// Keeping backward compatibility until major revision number is incremented +#define AON_EVENT_RTC0 ( AON_EVENT_RTC_CH0 ) + +//***************************************************************************** +// +// Values that can be passed to AONEventMCUWakeUpSet() and returned +// by AONEventMCUWakeUpGet(). +// +//***************************************************************************** +#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0 +#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1 +#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2 +#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3 + +//***************************************************************************** +// +// Values that can be passed to AONEventAuxWakeUpSet() and AONEventAuxWakeUpGet() +// +//***************************************************************************** +#define AON_EVENT_AUX_WU0 0 // Programmable AUX wake-up event 0 +#define AON_EVENT_AUX_WU1 1 // Programmable AUX wake-up event 1 +#define AON_EVENT_AUX_WU2 2 // Programmable AUX wake-up event 2 + +//***************************************************************************** +// +// Values that can be passed to AONEventMcuSet() and AONEventMcuGet() +// +//***************************************************************************** +#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3) +#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3) +#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3) + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Select event source for the specified MCU wake-up programmable event. +//! +//! The AON event fabric has several programmable events that can wake up the MCU. +//! +//! \note The programmable event sources are effectively OR'ed together +//! to form a single wake-up event. +//! +//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources. +//! - \ref AON_EVENT_MCU_WU0 +//! - \ref AON_EVENT_MCU_WU1 +//! - \ref AON_EVENT_MCU_WU2 +//! - \ref AON_EVENT_MCU_WU3 +//! \param ui32EventSrc is an event source for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventMcuWakeUpGet() +// +//***************************************************************************** +extern void AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, + uint32_t ui32EventSrc); + +//***************************************************************************** +// +//! \brief Get event source for the specified MCU wake-up programmable event. +//! +//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources. +//! - \ref AON_EVENT_MCU_WU0 +//! - \ref AON_EVENT_MCU_WU1 +//! - \ref AON_EVENT_MCU_WU2 +//! - \ref AON_EVENT_MCU_WU3 +//! +//! \return Returns the event source for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventMcuWakeUpSet() +// +//***************************************************************************** +extern uint32_t AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent); + +//***************************************************************************** +// +//! \brief Select event source for the specified AUX wake-up programmable event. +//! +//! The AON event fabric has a total of three programmable events that can +//! wake-up the AUX domain. +//! +//! \note The three programmable event sources are effectively OR'ed together +//! to form a single wake-up event. +//! +//! \param ui32AUXWUEvent is one of three programmable AUX wake-up event sources. +//! - \ref AON_EVENT_AUX_WU0 +//! - \ref AON_EVENT_AUX_WU1 +//! - \ref AON_EVENT_AUX_WU2 +//! \param ui32EventSrc is an event sources for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventAuxWakeUpGet() +// +//***************************************************************************** +extern void AONEventAuxWakeUpSet(uint32_t ui32AUXWUEvent, + uint32_t ui32EventSrc); + +//***************************************************************************** +// +//! \brief Get event source for the specified AUX wake-up programmable event. +//! +//! The AON event fabric has a total of three programmable events that can +//! wake-up the AUX domain. +//! +//! \param ui32AUXWUEvent is one of three programmable AUX wake-up event sources. +//! - \ref AON_EVENT_AUX_WU0 +//! - \ref AON_EVENT_AUX_WU1 +//! - \ref AON_EVENT_AUX_WU2 +//! +//! \return Returns the event source for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventAuxWakeUpSet() +// +//***************************************************************************** +extern uint32_t AONEventAuxWakeUpGet(uint32_t ui32AUXWUEvent); + +//***************************************************************************** +// +//! \brief Select event source for the specified programmable event forwarded to the +//! MCU event fabric. +//! +//! The AON event fabric has a total of three programmable events that can +//! be forwarded to the MCU event fabric. +//! +//! \note The three programmable event sources are forwarded to the MCU Event +//! Fabric as: +//! - AON_PROG0 +//! - AON_PROG1 +//! - AON_PROG2 +//! +//! \param ui32MCUEvent is one of three programmable events forwarded to the +//! MCU event fabric. +//! - \ref AON_EVENT_MCU_EVENT0 +//! - \ref AON_EVENT_MCU_EVENT1 +//! - \ref AON_EVENT_MCU_EVENT2 +//! \param ui32EventSrc is an event source for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventMcuGet() +// +//***************************************************************************** +extern void AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc); + +//***************************************************************************** +// +//! \brief Get source for the specified programmable event forwarded to the MCU event +//! fabric. +//! +//! The AON event fabric has a total of three programmable events that can +//! be forwarded to the MCU event fabric. +//! +//! \param ui32MCUEvent is one of three programmable events forwarded to the +//! MCU event fabric. +//! - \ref AON_EVENT_MCU_EVENT0 +//! - \ref AON_EVENT_MCU_EVENT1 +//! - \ref AON_EVENT_MCU_EVENT2 +//! +//! \return Returns the event source for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventMcuSet() +// +//***************************************************************************** +extern uint32_t AONEventMcuGet(uint32_t ui32MCUEvent); + +//***************************************************************************** +// +//! \brief Select event source forwarded to AON Real Time Clock (RTC). +//! +//! A programmable event can be forwarded to the AON real time clock +//! for triggering a capture event on RTC channel 1. +//! +//! \param ui32EventSrc is an event source for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventRtcGet() +// +//***************************************************************************** +__STATIC_INLINE void +AONEventRtcSet(uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL); + ui32Ctrl &= ~(AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S; + + HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL) = ui32Ctrl; +} + +//***************************************************************************** +// +//! \brief Get event source forwarded to AON Real Time Clock (RTC). +//! +//! A programmable event can be forwarded to the AON real time clock +//! for triggering a capture event on RTC channel 1. +//! +//! \return Returns the event source to the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventRtcSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONEventRtcGet(void) +{ + uint32_t ui32EventSrc; + + // Return the active event. + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL); + + return ((ui32EventSrc & AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M) >> + AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONEventMcuWakeUpSet + #undef AONEventMcuWakeUpSet + #define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet + #endif + #ifdef ROM_AONEventMcuWakeUpGet + #undef AONEventMcuWakeUpGet + #define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet + #endif + #ifdef ROM_AONEventAuxWakeUpSet + #undef AONEventAuxWakeUpSet + #define AONEventAuxWakeUpSet ROM_AONEventAuxWakeUpSet + #endif + #ifdef ROM_AONEventAuxWakeUpGet + #undef AONEventAuxWakeUpGet + #define AONEventAuxWakeUpGet ROM_AONEventAuxWakeUpGet + #endif + #ifdef ROM_AONEventMcuSet + #undef AONEventMcuSet + #define AONEventMcuSet ROM_AONEventMcuSet + #endif + #ifdef ROM_AONEventMcuGet + #undef AONEventMcuGet + #define AONEventMcuGet ROM_AONEventMcuGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_EVENT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event_doc.h new file mode 100644 index 0000000..e1fcea8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event_doc.h @@ -0,0 +1,61 @@ +/****************************************************************************** +* Filename: aon_event_doc.h +* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) +* Revision: 49506 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonevent_api +//! @{ +//! \section sec_aonevent Introduction +//! +//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and +//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers +//! to the AON event fabric. For more information on MCU event fabric, see [MCU event API](@ref event_api). +//! +//! The AON event fabric is a configurable combinatorial router between AON event sources and event +//! subscribers in both AON and MCU domains. The API to control the AON event fabric configuration +//! can be grouped based on the event subscriber to configure: +//! +//! - Wake-up events. +//! - MCU wake-up event +//! - @ref AONEventMcuWakeUpSet() +//! - @ref AONEventMcuWakeUpGet() +//! - AUX wake-up event +//! - @ref AONEventAuxWakeUpSet() +//! - @ref AONEventAuxWakeUpGet() +//! - AON RTC receives a single programmable event line from the AON event fabric. For more information, see [AON RTC API](@ref aonrtc_api). +//! - @ref AONEventRtcSet() +//! - @ref AONEventRtcGet() +//! - MCU event fabric receives a number of programmable event lines from the AON event fabric. For more information, see [MCU event API](@ref event_api). +//! - @ref AONEventMcuSet() +//! - @ref AONEventMcuGet() +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc.c new file mode 100644 index 0000000..d4475b7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc.c @@ -0,0 +1,39 @@ +/****************************************************************************** +* Filename: aon_ioc.c +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Driver for the AON IO Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_ioc.h" diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc.h new file mode 100644 index 0000000..513e0e2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc.h @@ -0,0 +1,292 @@ +/****************************************************************************** +* Filename: aon_ioc.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the AON IO Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonioc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_IOC_H__ +#define __AON_IOC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_ioc.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the drive strength +// +//***************************************************************************** +#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength +#define AONIOC_DRV_STR_2 0x00000001 +#define AONIOC_DRV_STR_3 0x00000003 +#define AONIOC_DRV_STR_4 0x00000002 +#define AONIOC_DRV_STR_5 0x00000006 +#define AONIOC_DRV_STR_6 0x00000007 +#define AONIOC_DRV_STR_7 0x00000005 +#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength + +#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN) +#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED) +#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX) + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure drive strength values for the manual drive strength options. +//! +//! This function defines the general drive strength settings for the non-AUTO +//! drive strength options in the MCU IOC. Consequently, if all IOs are using the +//! automatic drive strength option this function has no effect. +//! +//! Changing the drive strength values affects all current modes (Low-Current, +//! High-Current, and Extended-Current). Current mode for individual IOs is set in +//! MCU IOC by \ref IOCIODrvStrengthSet(). +//! +//! \note Values are Gray encoded. Simply incrementing values to increase drive +//! strength will not work. +//! +//! \param ui32DriveLevel +//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. Default value is selected +//! to give minimum 2/4/8 mA @3.3V for Low-Current mode, High-Current mode, +//! and Extended-Current mode respectively. +//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. Default value is selected +//! to give minimum 2/4/8 mA @2.5V for Low-Current mode, High-Current mode, +//! and Extended-Current mode respectively. +//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. Default value is selected +//! to give minimum 2/4/8 mA @1.8V for Low-Current mode, High-Current mode, +//! and Extended-Current mode respectively. +//! \param ui32DriveStrength sets the value used by IOs configured as non-AUTO drive strength in MCU IOC. +//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength +//! - \ref AONIOC_DRV_STR_2 +//! - \ref AONIOC_DRV_STR_3 +//! - \ref AONIOC_DRV_STR_4 +//! - \ref AONIOC_DRV_STR_5 +//! - \ref AONIOC_DRV_STR_6 +//! - \ref AONIOC_DRV_STR_7 +//! - \ref AONIOC_DRV_STR_8 : Highest drive strength +//! +//! \return None +//! +//! \sa \ref AONIOCDriveStrengthGet(), \ref IOCIODrvStrengthSet() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOCDriveStrengthSet(uint32_t ui32DriveLevel, uint32_t ui32DriveStrength) +{ + ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) || + (ui32DriveLevel == AONIOC_DRV_LVL_MED) || + (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); + ASSERT((ui32DriveStrength == AONIOC_DRV_STR_1) || + (ui32DriveStrength == AONIOC_DRV_STR_2) || + (ui32DriveStrength == AONIOC_DRV_STR_3) || + (ui32DriveStrength == AONIOC_DRV_STR_4) || + (ui32DriveStrength == AONIOC_DRV_STR_5) || + (ui32DriveStrength == AONIOC_DRV_STR_6) || + (ui32DriveStrength == AONIOC_DRV_STR_7) || + (ui32DriveStrength == AONIOC_DRV_STR_8)); + + // Set the drive strength. + HWREG(AON_IOC_BASE + ui32DriveLevel) = ui32DriveStrength; +} + +//***************************************************************************** +// +//! \brief Get a specific drive level setting for all IOs. +//! +//! Use this function to read the drive strength setting for a specific +//! IO drive level. +//! +//! \note Values are Gray encoded. +//! +//! \param ui32DriveLevel is the specific drive level to get the setting for. +//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. +//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. +//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. +//! +//! \return Returns the requested drive strength level setting for all IOs. +//! Possible values are: +//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength +//! - \ref AONIOC_DRV_STR_2 +//! - \ref AONIOC_DRV_STR_3 +//! - \ref AONIOC_DRV_STR_4 +//! - \ref AONIOC_DRV_STR_5 +//! - \ref AONIOC_DRV_STR_6 +//! - \ref AONIOC_DRV_STR_7 +//! - \ref AONIOC_DRV_STR_8 : Highest drive strength +//! +//! \sa AONIOCDriveStrengthSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONIOCDriveStrengthGet(uint32_t ui32DriveLevel) +{ + // Check the arguments. + ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) || + (ui32DriveLevel == AONIOC_DRV_LVL_MED) || + (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); + + // Return the drive strength value. + return( HWREG(AON_IOC_BASE + ui32DriveLevel) ); +} + +//***************************************************************************** +// +//! \brief Freeze the IOs. +//! +//! To retain the values of the output IOs during a powerdown/shutdown of the +//! device all IO latches in the AON domain should be frozen in their current +//! state. This ensures that software can regain control of the IOs after a +//! reboot without the IOs first falling back to the default values (i.e. input +//! and no pull). +//! +//! \return None +//! +//! \sa AONIOCFreezeDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOCFreezeEnable(void) +{ + // Set the AON IO latches as static. + HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = 0x0; +} + +//***************************************************************************** +// +//! \brief Un-freeze the IOs. +//! +//! When rebooting the chip after it has entered powerdown/shutdown mode, the +//! software can regain control of the IOs by setting the IO latches as +//! transparent. The IOs should not be unfrozen before software has restored +//! the functionality of the IO. +//! +//! \return None +//! +//! \sa AONIOCFreezeEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOCFreezeDisable(void) +{ + // Set the AON IOC latches as transparent. + HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = AON_IOC_IOCLATCH_EN; +} + +//***************************************************************************** +// +//! \brief Disable the 32kHz clock output. +//! +//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality +//! in the IOC is bypassed. Therefore, the programmer needs to call this +//! function to disable the clock output. +//! +//! \return None +//! +//! \sa AONIOC32kHzOutputEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOC32kHzOutputDisable(void) +{ + // Disable the LF clock output. + HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = AON_IOC_CLK32KCTL_OE_N; +} + +//***************************************************************************** +// +//! \brief Enable the 32kHz clock output. +//! +//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality +//! in the IOC is bypassed. Therefore, the programmer needs to call this +//! function to enable the clock output. +//! +//! \return None +//! +//! \sa AONIOC32kHzOutputDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOC32kHzOutputEnable(void) +{ + // Enable the LF clock output. + HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = 0x0; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_IOC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc_doc.h new file mode 100644 index 0000000..7fe0e93 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc_doc.h @@ -0,0 +1,65 @@ +/****************************************************************************** +* Filename: aon_ioc_doc.h +* Revised: 2016-03-30 11:01:30 +0200 (Wed, 30 Mar 2016) +* Revision: 45969 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonioc_api +//! @{ +//! \section sec_aonioc Introduction +//! +//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO). +//! The IOC consists of two APIs: +//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it. +//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc. +//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is +//! routed to a DIO for external use. +//! +//! For more information on the MCU IOC see the [IOC API](\ref ioc_api). +//! +//! \section sec_aonioc_api API +//! +//! The API functions can be grouped like this: +//! +//! Freeze IOs while MCU domain is powered down: +//! - \ref AONIOCFreezeEnable() +//! - \ref AONIOCFreezeDisable() +//! +//! Output LF clock to a DIO: +//! - \ref AONIOC32kHzOutputEnable() +//! - \ref AONIOC32kHzOutputDisable() +//! +//! Configure the value of drive strength for the three manual MCU IOC settings (MIN, MED, MAX): +//! - \ref AONIOCDriveStrengthSet() +//! - \ref AONIOCDriveStrengthGet() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc.c new file mode 100644 index 0000000..98821e1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc.c @@ -0,0 +1,102 @@ +/****************************************************************************** +* Filename: aon_rtc.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the AON RTC. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_rtc.h" +#include "cpu.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONRTCCurrentCompareValueGet + #define AONRTCCurrentCompareValueGet NOROM_AONRTCCurrentCompareValueGet + #undef AONRTCCurrent64BitValueGet + #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet +#endif + + +//***************************************************************************** +// +// Get the current value of the RTC counter in a format compatible to the compare registers. +// +//***************************************************************************** +uint32_t +AONRTCCurrentCompareValueGet( void ) +{ + uint32_t ui32CurrentSec ; + uint32_t ui32CurrentSubSec ; + uint32_t ui32SecondSecRead ; + + // Reading SEC both before and after SUBSEC in order to detect if SEC incremented while reading SUBSEC + // If SEC incremented, we can't be sure which SEC the SUBSEC belongs to, so repeating the sequence then. + do { + ui32CurrentSec = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + ui32CurrentSubSec = HWREG( AON_RTC_BASE + AON_RTC_O_SUBSEC ); + ui32SecondSecRead = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + } while ( ui32CurrentSec != ui32SecondSecRead ); + + return (( ui32CurrentSec << 16 ) | ( ui32CurrentSubSec >> 16 )); +} + +//***************************************************************************** +// +// Get the current 64-bit value of the RTC counter. +// +//***************************************************************************** +uint64_t +AONRTCCurrent64BitValueGet( void ) +{ + union { + uint64_t returnValue ; + uint32_t secAndSubSec[ 2 ] ; + } currentRtc ; + uint32_t ui32SecondSecRead ; + + // Reading SEC both before and after SUBSEC in order to detect if SEC incremented while reading SUBSEC + // If SEC incremented, we can't be sure which SEC the SUBSEC belongs to, so repeating the sequence then. + do { + currentRtc.secAndSubSec[ 1 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + currentRtc.secAndSubSec[ 0 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SUBSEC ); + ui32SecondSecRead = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + } while ( currentRtc.secAndSubSec[ 1 ] != ui32SecondSecRead ); + + return ( currentRtc.returnValue ); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc.h new file mode 100644 index 0000000..eb98dec --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc.h @@ -0,0 +1,936 @@ +/****************************************************************************** +* Filename: aon_rtc.h +* Revised: 2017-08-16 15:13:43 +0200 (Wed, 16 Aug 2017) +* Revision: 49593 +* +* Description: Defines and prototypes for the AON RTC +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonrtc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_RTC_H__ +#define __AON_RTC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_rtc.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONRTCCurrentCompareValueGet NOROM_AONRTCCurrentCompareValueGet + #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet +#endif + +//***************************************************************************** +// +// Values that can be passed to most of the AON_RTC APIs as the ui32Channel +// parameter. +// +//***************************************************************************** +#define AON_RTC_CH_NONE 0x0 // RTC No channel +#define AON_RTC_CH0 0x1 // RTC Channel 0 +#define AON_RTC_CH1 0x2 // RTC Channel 1 +#define AON_RTC_CH2 0x4 // RTC Channel 2 +#define AON_RTC_ACTIVE 0x8 // RTC Active + +//***************************************************************************** +// +// Values that can be passed to AONRTCConfigDelay as the ui32Delay parameter. +// +//***************************************************************************** +#define AON_RTC_CONFIG_DELAY_NODELAY 0 // NO DELAY +#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle +#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles +#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles +#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles +#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles +#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles +#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles +#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles +#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles +#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles +#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles +#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles +#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles + +//***************************************************************************** +// +// Values that can be passed to AONRTCSetModeCH1 as the ui32Mode +// parameter. +// +//***************************************************************************** +#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode +#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode + +//***************************************************************************** +// +// Values that can be passed to AONRTCSetModeCH2 as the ui32Mode +// parameter. +// +//***************************************************************************** +#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode +#define AON_RTC_MODE_CH2_NORMALCOMPARE 0 // Normal compare mode + +//***************************************************************************** +// +// Mutliplication factor for converting from seconds to corresponding time in +// the "CompareValue" format. +// The factor correspond to the compare value format described in the registers +// \ref AON_RTC_O_CH0CMP, \ref AON_RTC_O_CH1CMP and \ref AON_RTC_O_CH2CMP. +// Example1: +// 4 milliseconds in CompareValue format can be written like this: +// ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT )) +// Example2: +// 4 seconds in CompareValue format can be written like this: +// ( 4 * FACTOR_SEC_TO_COMP_VAL_FORMAT ) +// +//***************************************************************************** +#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enable the RTC. +//! +//! Enable the AON Real Time Clock. +//! +//! \note Event generation for each of the three channels must also be enabled +//! using the function AONRTCChannelEnable(). +//! +//! \return None +//! +//! \sa AONRTCChannelEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCEnable(void) +{ + // Enable RTC. + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disable the RTC. +//! +//! Disable the AON Real Time Clock. +//! +//! \note Event generation for each of the three channels can also be disabled +//! using the function AONRTCChannelDisable(). +//! +//! \return None +//! +//! \sa AONRTCChannelDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCDisable(void) +{ + // Disable RTC + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Reset the RTC. +//! +//! Reset the AON Real Time Clock. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCReset(void) +{ + // Reset RTC. + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_RESET_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Check if the RTC is active (enabled). +//! +//! \return Returns the status of the RTC. +//! - false : RTC is disabled +//! - true : RTC is enabled +// +//***************************************************************************** +__STATIC_INLINE bool +AONRTCActive(void) +{ + // Read if RTC is enabled + return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN)); +} + +//***************************************************************************** +// +//! \brief Check if an RTC channel is active (enabled). +//! +//! \param ui32Channel specifies the RTC channel to check status of. +//! Parameter must be one (and only one) of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return Returns the status of the requested channel: +//! - false : Channel is disabled +//! - true : Channel is enabled +// +//***************************************************************************** +__STATIC_INLINE bool +AONRTCChannelActive(uint32_t ui32Channel) +{ + uint32_t uint32Status = 0; + + if(ui32Channel & AON_RTC_CH0) + { + uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN); + } + + if(ui32Channel & AON_RTC_CH1) + { + uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN); + } + + if(ui32Channel & AON_RTC_CH2) + { + uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN); + } + + return(uint32Status); +} + +//***************************************************************************** +// +//! \brief Configure Event Delay for the RTC. +//! +//! Each event from the three individual channels can generate a delayed +//! event. The delay time for these events is set using this function. +//! The delay is measured in clock cycles. +//! +//! \note There is only one delay setting shared for all three channels. +//! +//! \param ui32Delay specifies the delay time for delayed events. +//! Parameter must be one of the following: +//! - \ref AON_RTC_CONFIG_DELAY_NODELAY +//! - \ref AON_RTC_CONFIG_DELAY_1 +//! - \ref AON_RTC_CONFIG_DELAY_2 +//! - \ref AON_RTC_CONFIG_DELAY_4 +//! - \ref AON_RTC_CONFIG_DELAY_8 +//! - \ref AON_RTC_CONFIG_DELAY_16 +//! - \ref AON_RTC_CONFIG_DELAY_32 +//! - \ref AON_RTC_CONFIG_DELAY_48 +//! - \ref AON_RTC_CONFIG_DELAY_64 +//! - \ref AON_RTC_CONFIG_DELAY_80 +//! - \ref AON_RTC_CONFIG_DELAY_96 +//! - \ref AON_RTC_CONFIG_DELAY_112 +//! - \ref AON_RTC_CONFIG_DELAY_128 +//! - \ref AON_RTC_CONFIG_DELAY_144 +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCDelayConfig(uint32_t ui32Delay) +{ + uint32_t ui32Cfg; + + // Check the arguments. + ASSERT(ui32Delay <= AON_RTC_CONFIG_DELAY_144); + + + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg &= ~(AON_RTC_CTL_EV_DELAY_M); + ui32Cfg |= (ui32Delay << AON_RTC_CTL_EV_DELAY_S); + + HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg; +} + +//***************************************************************************** +// +//! \brief Configure the source of the combined event. +//! +//! A combined delayed event can be generated from a combination of the three +//! delayed events. Delayed events form the specified channels are OR'ed +//! together to generate the combined event. +//! +//! \param ui32Channels specifies the channels that are to be used for +//! generating the combined event. +//! The parameter must be the bitwise OR of any of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! - \ref AON_RTC_CH_NONE +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCCombinedEventConfig(uint32_t ui32Channels) +{ + uint32_t ui32Cfg; + + // Check the arguments. + ASSERT( (ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) || + (ui32Channels == AON_RTC_CH_NONE) ); + + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg &= ~(AON_RTC_CTL_COMB_EV_MASK_M); + ui32Cfg |= (ui32Channels << AON_RTC_CTL_COMB_EV_MASK_S); + + HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg; +} + +//***************************************************************************** +// +//! \brief Clear event from a specified channel. +//! +//! In case of an active event from the specified channel, the event +//! will be cleared (de-asserted). +//! +//! \param ui32Channel clears the event from one or more RTC channels: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCEventClear(uint32_t ui32Channel) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH0; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH1; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH2; + } +} + +//***************************************************************************** +// +//! \brief Get event status for a specified channel. +//! +//! In case of an active event from the specified channel, +//! this call will return \c true otherwise \c false. +//! +//! \param ui32Channel specifies the channel from which to query the event state. +//! The parameter must be one (and only one) of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return Returns \c true if an event has occurred for the given channel, +//! otherwise \c false. +// +//***************************************************************************** +__STATIC_INLINE bool +AONRTCEventGet(uint32_t ui32Channel) +{ + uint32_t uint32Event = 0; + + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH0_BITN); + } + + if(ui32Channel & AON_RTC_CH1) + { + uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH1_BITN); + } + + if(ui32Channel & AON_RTC_CH2) + { + uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH2_BITN); + } + + return(uint32Event); +} + +//***************************************************************************** +// +//! \brief Get integer part (seconds) of RTC free-running timer. +//! +//! Get the value in seconds of RTC free-running timer, i.e. the integer part. +//! The fractional part is returned from a call to AONRTCFractionGet(). +//! +//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead +//! of this function if the <16.16> format is sufficient. +//! +//! \note To read a consistent pair of integer and fractional parts, +//! \ref AONRTCSecGet() must be called first to trigger latching of the +//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts +//! must be disabled to ensure that these operations are performed atomically. +//! +//! \return Returns the integer part of RTC free running timer. +//! +//! \sa \ref AONRTCFractionGet() \ref AONRTCCurrentCompareValueGet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCSecGet(void) +{ + // The following read gets the seconds, but also latches the fractional + // part. + return(HWREG(AON_RTC_BASE + AON_RTC_O_SEC)); +} + +//***************************************************************************** +// +//! \brief Get fractional part (sub-seconds) of RTC free-running timer. +//! +//! Get the value of the fractional part of RTC free-running timer, i.e. the +//! sub-second part. +//! +//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead +//! of this function if the <16.16> format is sufficient. +//! +//! \note To read a consistent pair of integer and fractional parts, +//! \ref AONRTCSecGet() must be called first to trigger latching of the +//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts +//! must be disabled to ensure that these operations are performed atomically. +//! +//! \return Returns the fractional part of RTC free running timer. +//! +//! \sa \ref AONRTCSecGet() \ref AONRTCCurrentCompareValueGet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCFractionGet(void) +{ + // Note1: It is recommended to use AON RTCCurrentCompareValueGet() instead + // of this function if the <16.16> format is sufficient. + // Note2: AONRTCSecGet() must be called before this function to get a + // consistent reading. + // Note3: Interrupts must be disabled between the call to AONRTCSecGet() and this + // call since there are interrupt functions that reads AON_RTC_O_SEC + return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC)); +} + +//***************************************************************************** +// +//! \brief Get the sub second increment of the RTC. +//! +//! Get the value of the sub-second increment which is added to the RTC +//! absolute time on every clock tick. +//! +//! \note For a precise and temperature independent LF clock (e.g. an LF XTAL) +//! this value would stay the same across temperature. For temperatue +//! dependent clock sources like an RC oscillator, this value will change +//! over time if the application includes functionality for doing temperature +//! compensation of the RTC clock source. The default value corresponds to a +//! LF clock frequency of exactly 32.768 kHz. +//! +//! \return Returns the sub-second increment of the RTC added to the overall +//! value on every RTC clock tick. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCSubSecIncrGet(void) +{ + return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSECINC)); +} + +//***************************************************************************** +// +//! \brief Set operational mode of channel 1. +//! +//! Set the operational mode of channel 1. It can be capture or compare mode. +//! In capture mode, an external event causes the value of the free running +//! counter to be stored, to remember the time of the event. +//! +//! \note The default mode is compare. +//! +//! \param ui32Mode specifies the mode for channel 1. +//! The parameter must be one of the following: +//! - \ref AON_RTC_MODE_CH1_CAPTURE +//! - \ref AON_RTC_MODE_CH1_COMPARE +//! +//! \return None +//! +//! \sa AONRTCModeCh1Get() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCModeCh1Set(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == AON_RTC_MODE_CH1_CAPTURE) || + (ui32Mode == AON_RTC_MODE_CH1_COMPARE)); + + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN) = ui32Mode; +} + +//***************************************************************************** +// +//! \brief Get operational mode of channel 1. +//! +//! Get the operational mode of channel 1. It can be capture or compare mode. +//! In capture mode, an external event causes the value of the free running +//! counter to be stored, to remember the time of the event. +//! +//! \return Returns the operational mode of channel 1, one of: +//! - \ref AON_RTC_MODE_CH1_CAPTURE +//! - \ref AON_RTC_MODE_CH1_COMPARE +//! +//! \sa AONRTCModeCh1Set() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCModeCh1Get(void) +{ + return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN)); +} + +//***************************************************************************** +// +//! \brief Set operational mode of channel 2. +//! +//! Set the operational mode of channel 2. It can be in continuous compare +//! mode or normal compare mode. +//! In continuous mode, a value is automatically incremented to the channel 2 +//! compare register, upon a channel 2 compare event. This allows channel 2 to +//! generate a series of completely equidistant events. +//! The increment value is set by the AONRTCIncValueCh2Set() call. +//! +//! \note The default mode is normal compare. +//! +//! \param ui32Mode specifies the mode for channel 2. +//! The parameter must be one of the following: +//! - \ref AON_RTC_MODE_CH2_CONTINUOUS +//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE +//! +//! \return None +//! +//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCModeCh2Set(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) || + (ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE)); + + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN) = ui32Mode; +} + +//***************************************************************************** +// +//! \brief Get operational mode of channel 2. +//! +//! Get the operational mode of channel 2. It can be in continuous compare +//! mode or normal compare mode. +//! In continuous mode, a value is automatically incremented to the channel 2 +//! compare register, upon a channel 2 compare event. This allows channel 2 to +//! generate a series of completely equidistant events. +//! The increment value is set by the AONRTCIncValueCh2Set() call. +//! +//! \return Returns the operational mode of channel 2, i.e. one of: +//! - \ref AON_RTC_MODE_CH2_CONTINUOUS +//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE +//! +//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCModeCh2Get(void) +{ + return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN)); +} + +//***************************************************************************** +// +//! \brief Enable event operation for the specified channel. +//! +//! Enable the event generation for the specified channel. +//! +//! \note The RTC free running clock must also be enabled globally using the +//! AONRTCEnable() call. +//! +//! \param ui32Channel specifies one or more channels to enable: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return None +//! +//! \sa AONRTCEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCChannelEnable(uint32_t ui32Channel) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 1; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 1; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 1; + } +} + +//***************************************************************************** +// +//! \brief Disable event operation for the specified channel. +//! +//! Disable the event generation for the specified channel. +//! +//! \note The RTC free running clock can also be disabled globally using the +//! AONRTCDisable() call. +//! +//! \param ui32Channel specifies one or more channels to disable: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return None +//! +//! \sa AONRTCDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCChannelDisable(uint32_t ui32Channel) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 0; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 0; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 0; + } +} + +//***************************************************************************** +// +//! \brief Set the compare value for the given channel. +//! +//! Set compare value for the specified channel. +//! +//! The format of the compare value is a 16 bit integer and 16 bit fractional +//! format <16 sec.16 subsec>. The current value of the RTC counter +//! can be retrieved in a format compatible to the compare register using +//! \ref AONRTCCurrentCompareValueGet() +//! +//! \param ui32Channel specifies one or more channels to set compare value for: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! \param ui32CompValue is the compare value to set for the specified channel. +//! - Format: <16 sec.16 subsec> +//! +//! \return None +//! +//! \sa AONRTCCurrentCompareValueGet() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCCompareValueSet(uint32_t ui32Channel, uint32_t ui32CompValue) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP) = ui32CompValue; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP) = ui32CompValue; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP) = ui32CompValue; + } +} + +//***************************************************************************** +// +//! \brief Get the compare value for the given channel. +//! +//! Get compare value for the specified channel. +//! +//! \param ui32Channel specifies a channel. +//! The parameter must be one (and only one) of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return Returns the stored compare value for the given channel. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCCompareValueGet(uint32_t ui32Channel) +{ + uint32_t ui32Value = 0; + + // Check the arguments + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP); + } + + if(ui32Channel & AON_RTC_CH1) + { + ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP); + } + + if(ui32Channel & AON_RTC_CH2) + { + ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP); + } + + return(ui32Value); +} + +//***************************************************************************** +// +//! \brief Get the current value of the RTC counter in a format that matches +//! RTC compare values. +//! +//! The compare value registers contains 16 integer and 16 fractional bits. +//! This function will return the current value of the RTC counter in an +//! identical format. +//! +//! \note Reading SEC both before and after SUBSEC in order to detect if SEC +//! incremented while reading SUBSEC. If SEC incremented, we can't be sure +//! which SEC the SUBSEC belongs to, so repeating the sequence then. +//! +//! \return Returns the current value of the RTC counter in a <16.16> format +//! (SEC[15:0].SUBSEC[31:16]). +//! +//! \sa \ref AONRTCCompareValueSet() +// +//***************************************************************************** +extern uint32_t AONRTCCurrentCompareValueGet(void); + +//***************************************************************************** +// +//! \brief Get the current 64-bit value of the RTC counter. +//! +//! \note Reading SEC both before and after SUBSEC in order to detect if SEC +//! incremented while reading SUBSEC. If SEC incremented, we can't be sure +//! which SEC the SUBSEC belongs to, so repeating the sequence then. +//! +//! \return Returns the current value of the RTC counter in a 64-bits format +//! (SEC[31:0].SUBSEC[31:0]). +// +//***************************************************************************** +extern uint64_t AONRTCCurrent64BitValueGet(void); + +//***************************************************************************** +// +//! \brief Set the channel 2 increment value when operating in continuous mode. +//! +//! Set the channel 2 increment value when operating in continuous mode. +//! The specified value is automatically incremented to the channel 2 compare +//! register, upon a channel 2 compare event. This allows channel 2 to generate +//! a series of completely equidistant events. +//! +//! \param ui32IncValue is the increment value when operating in continuous mode. +//! +//! \return None +//! +//! \sa AONRTCIncValueCh2Get() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCIncValueCh2Set(uint32_t ui32IncValue) +{ + HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC) = ui32IncValue; +} + +//***************************************************************************** +// +//! \brief Get the channel2 increment value when operating in continuous mode. +//! +//! Get the channel 2 increment value, when channel 2 is operating in +//! continuous mode. +//! This value is automatically incremented to the channel 2 compare +//! register, upon a channel 2 compare event. This allows channel 2 to +//! generate a series of completely equidistant events. +//! +//! \return Returns the channel 2 increment value when operating in continuous +//! mode. +//! +//! \sa AONRTCIncValueCh2Set() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCIncValueCh2Get(void) +{ + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC)); +} + +//***************************************************************************** +// +//! \brief Get the channel 1 capture value. +//! +//! Get the channel 1 capture value. +//! The upper 16 bits of the returned value is the lower 16 bits of the +//! integer part of the RTC timer. The lower 16 bits of the returned part +//! is the upper 16 bits of the fractional part. +//! +//! \return Returns the channel 1 capture value. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCCaptureValueCh1Get(void) +{ + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH1CAPT)); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONRTCCurrentCompareValueGet + #undef AONRTCCurrentCompareValueGet + #define AONRTCCurrentCompareValueGet ROM_AONRTCCurrentCompareValueGet + #endif + #ifdef ROM_AONRTCCurrent64BitValueGet + #undef AONRTCCurrent64BitValueGet + #define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_RTC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc_doc.h new file mode 100644 index 0000000..b3c142b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc_doc.h @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: aon_rtc_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonrtc_api +//! @{ +//! \section sec_aonrtc Introduction +//! +//! \note If using TI-RTOS then only TI-RTOS is allowed to configure the RTC timer! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_wuc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_wuc.c new file mode 100644 index 0000000..290945e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_wuc.c @@ -0,0 +1,224 @@ +/****************************************************************************** +* Filename: aon_wuc.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the AON Wake-Up Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_wuc.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONWUCAuxReset + #define AONWUCAuxReset NOROM_AONWUCAuxReset + #undef AONWUCRechargeCtrlConfigSet + #define AONWUCRechargeCtrlConfigSet NOROM_AONWUCRechargeCtrlConfigSet + #undef AONWUCOscConfig + #define AONWUCOscConfig NOROM_AONWUCOscConfig +#endif + + +//***************************************************************************** +// +//! Reset the AUX domain +// +//***************************************************************************** +void +AONWUCAuxReset(void) +{ + // Reset the AUX domain. +// HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) |= AON_WUC_AUXCTL_RESET_REQ; // ROM version + HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_RESET_REQ_BITN) = 1; + + // Wait for AON interface to be in sync. + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); + + // De-assert reset on the AUX domain. +// HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) &= ~AON_WUC_AUXCTL_RESET_REQ; // ROM version + HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_RESET_REQ_BITN) = 0; + + // Wait for AON interface to be in sync. + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! Configure the recharge controller +// +//***************************************************************************** +void +AONWUCRechargeCtrlConfigSet(bool bAdaptEnable, uint32_t ui32AdaptRate, + uint32_t ui32Period, uint32_t ui32MaxPeriod) +{ + uint32_t ui32Shift; + uint32_t ui32C1; + uint32_t ui32C2; + uint32_t ui32Reg; + uint32_t ui32Exponent; + uint32_t ui32MaxExponent; + uint32_t ui32Mantissa; + uint32_t ui32MaxMantissa; + + // Check the arguments. + ASSERT((ui32AdaptRate >= RC_RATE_MIN) || + (ui32AdaptRate <= RC_RATE_MAX)); + + ui32C1 = 0; + ui32C2 = 0; + ui32Shift = 9; + + // Clear the previous values. + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG); + ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M | + AON_WUC_RECHARGECFG_ADAPTIVE_EN_M | AON_WUC_RECHARGECFG_PER_M_M | + AON_WUC_RECHARGECFG_PER_E_M | AON_WUC_RECHARGECFG_C1_M | + AON_WUC_RECHARGECFG_C2_M); + + // Check if the recharge controller adaptation algorithm should be active. + if(bAdaptEnable) + { + // Calculate adaptation parameters. + while(ui32AdaptRate) + { + if(ui32AdaptRate & (1 << ui32Shift)) + { + if(!ui32C1) + { + ui32C1 = ui32Shift; + } + else if(!ui32C2) + { + if((2 * ui32AdaptRate) > ((uint32_t)(3 << ui32Shift))) + { + ui32C2 = ui32Shift + 1; + } + else + { + ui32C2 = ui32Shift; + } + } + else + { + break; + } + ui32AdaptRate &= ~(1 << ui32Shift); + } + ui32Shift--; + } + if(!ui32C2) + { + ui32C2 = ui32C1 = ui32C1 - 1; + } + + ui32C1 = 10 - ui32C1; + ui32C2 = 10 - ui32C2; + + // Update the recharge rate parameters. + ui32Reg &= ~(AON_WUC_RECHARGECFG_C1_M | AON_WUC_RECHARGECFG_C2_M); + ui32Reg |= (ui32C1 << AON_WUC_RECHARGECFG_C1_S) | + (ui32C2 << AON_WUC_RECHARGECFG_C2_S) | + AON_WUC_RECHARGECFG_ADAPTIVE_EN_M; + } + + // Resolve the period into an exponent and mantissa. + ui32Period = (ui32Period >> 4); + ui32Exponent = 0; + while(ui32Period > (AON_WUC_RECHARGECFG_PER_M_M >> AON_WUC_RECHARGECFG_PER_M_S)) + { + ui32Period >>= 1; + ui32Exponent++; + } + ui32Mantissa = ui32Period; + + // Resolve the max period into an exponent and mantissa. + ui32MaxPeriod = (ui32MaxPeriod >> 4); + ui32MaxExponent = 0; + while(ui32MaxPeriod > (AON_WUC_RECHARGECFG_MAX_PER_M_M >> AON_WUC_RECHARGECFG_MAX_PER_M_S)) + { + ui32MaxPeriod >>= 1; + ui32MaxExponent++; + } + ui32MaxMantissa = ui32MaxPeriod; + + // Configure the controller. + ui32Reg |= ((ui32MaxMantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) | + (ui32MaxExponent << AON_WUC_RECHARGECFG_MAX_PER_E_S) | + (ui32Mantissa << AON_WUC_RECHARGECFG_PER_M_S) | + (ui32Exponent << AON_WUC_RECHARGECFG_PER_E_S)); + HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg; + +} + +//***************************************************************************** +// +//! Configure the interval for oscillator amplitude calibration +// +//***************************************************************************** +void +AONWUCOscConfig(uint32_t ui32Period) +{ + uint32_t ui32Mantissa; + uint32_t ui32Exponent; + uint32_t ui32Reg; + + // Resolve the period into a exponent and mantissa. + ui32Period = (ui32Period >> 4); + ui32Exponent = 0; + while(ui32Period > (AON_WUC_OSCCFG_PER_M_M >> AON_WUC_OSCCFG_PER_M_S)) + { + ui32Period >>= 1; + ui32Exponent++; + } + ui32Mantissa = ui32Period; + + // Update the period for the oscillator amplitude calibration. + HWREG(AON_WUC_BASE + AON_WUC_O_OSCCFG) = + (ui32Mantissa << AON_WUC_OSCCFG_PER_M_S) | + (ui32Exponent << AON_WUC_OSCCFG_PER_E_S); + + // Set the maximum recharge period equal to the oscillator amplitude + // calibration period. + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG); + ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M); + ui32Reg |= ((ui32Mantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) | + (ui32Exponent << AON_WUC_RECHARGECFG_MAX_PER_E_S)); + + // Write the configuration. + HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_wuc.h new file mode 100644 index 0000000..bb8dd13 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_wuc.h @@ -0,0 +1,838 @@ +/****************************************************************************** +* Filename: aon_wuc.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Defines and prototypes for the AON Wake-Up Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonwuc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_WUC_H__ +#define __AON_WUC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_aon_rtc.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONWUCAuxReset NOROM_AONWUCAuxReset + #define AONWUCRechargeCtrlConfigSet NOROM_AONWUCRechargeCtrlConfigSet + #define AONWUCOscConfig NOROM_AONWUCOscConfig +#endif + +//***************************************************************************** +// +// Defines the possible clock source for the MCU and AUX domain. +// +//***************************************************************************** +#define AONWUC_CLOCK_SRC_HF 0x00000003 // System clock high frequency - + // 48 MHz. +#define AONWUC_CLOCK_SRC_LF 0x00000001 // System clock low frequency - + // 32 kHz. +#define AONWUC_NO_CLOCK 0x00000000 // System clock low frequency - + // 32 kHz. + +//***************************************************************************** +// +// Defines the possible clock division factors for the AUX domain. +// +//***************************************************************************** +#define AUX_CLOCK_DIV_2 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 ) +#define AUX_CLOCK_DIV_4 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 ) +#define AUX_CLOCK_DIV_8 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 ) +#define AUX_CLOCK_DIV_16 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 ) +#define AUX_CLOCK_DIV_32 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 ) +#define AUX_CLOCK_DIV_64 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 ) +#define AUX_CLOCK_DIV_128 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 ) +#define AUX_CLOCK_DIV_256 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 ) +#define AUX_CLOCK_DIV_UNUSED ( AON_WUC_AUXCLK_SCLK_HF_DIV_M + ( 1 << AON_WUC_AUXCLK_SCLK_HF_DIV_S )) +#define AUX_CLOCK_DIV_M ( AON_WUC_AUXCLK_SCLK_HF_DIV_M ) + +//***************************************************************************** +// +// Defines used for configuring the power-off and wake up procedure. +// +//***************************************************************************** +#define MCU_VIRT_PWOFF_DISABLE 0x00000000 +#define MCU_VIRT_PWOFF_ENABLE 0x00020000 +#define MCU_IMM_WAKE_UP 0x00000000 +#define MCU_FIXED_WAKE_UP 0x00010000 +#define AUX_VIRT_PWOFF_DISABLE 0x00000000 +#define AUX_VIRT_PWOFF_ENABLE 0x00020000 +#define AUX_IMM_WAKE_UP 0x00000000 +#define AUX_FIXED_WAKE_UP 0x00010000 + +//***************************************************************************** +// +// Defines that can be be used to enable/disable the entire SRAM and the +// retention on the SRAM in both the MCU and the AUX domain. +// +//***************************************************************************** +#define MCU_RAM0_RETENTION 0x00000001 +#define MCU_RAM1_RETENTION 0x00000002 +#define MCU_RAM2_RETENTION 0x00000004 +#define MCU_RAM3_RETENTION 0x00000008 +#define MCU_RAM_BLOCK_RETENTION 0x0000000F +#define MCU_AUX_RET_ENABLE 0x00000001 + +//***************************************************************************** +// +// Defines for different wake up modes for AUX domain which can be set using +// AONWUCAuxWakeUpEvent() . +// +//***************************************************************************** +#define AONWUC_AUX_WAKEUP 0x00000001 +#define AONWUC_AUX_ALLOW_SLEEP 0x00000000 + +//***************************************************************************** +// +// Defines for all the different power modes available through +// AONWUCPowerStatusGet() . +// +//***************************************************************************** +#define AONWUC_OSC_GBIAS_REQ 0x00400000 // OSC is requesting GBias +#define AONWUC_AUX_GBIAS_REQ 0x00200000 // AUX is requesting GBias +#define AONWUC_MCU_GBIAS_REQ 0x00100000 // MCU is requesting GBias +#define AONWUC_OSC_BGAP_REQ 0x00040000 // OSC is requesting BGap +#define AONWUC_AUX_BGAP_REQ 0x00020000 // AUX is requesting BGap +#define AONWUC_MCU_BGAP_REQ 0x00010000 // MCU is requesting BGap +#define AONWUC_GBIAS_ON 0x00002000 // Global Bias is on +#define AONWUC_BGAP_ON 0x00001000 // Band Gap is on +#define AONWUC_AUX_POWER_DOWN 0x00000200 // AUX is in powerdown mode +#define AONWUC_MCU_POWER_DOWN 0x00000100 // MCU is in powerdown mode +#define AONWUC_JTAG_POWER_ON 0x00000040 // JTAG is powered on +#define AONWUC_AUX_POWER_ON 0x00000020 // AUX is powered on +#define AONWUC_MCU_POWER_ON 0x00000010 // MCU is powered on +#define AONWUC_SPLY_POWER_DOWN 0x00000001 // Power supply is in power down + + +//***************************************************************************** +// +// RAM repair status bits. Values are returned by AOXWUCRamRepairStatusGet() . +// +//***************************************************************************** +#define MCU_RAMREPAIR_DONE 0x00000001 +#define AUX_RAMREPAIR_DONE 0x00000002 + +//***************************************************************************** + +//***************************************************************************** +#define RC_RATE_MAX 768 // Maximum recharge rate for the + // recharge controller. +#define RC_RATE_MIN 2 // Minimum recharge rate for the + // recharge controller. + +//***************************************************************************** +#define AONWUC_MCU_RESET_SRC 0x00000002 // MCU reset source can be SW or + // JTAG +#define AONWUC_MCU_WARM_RESET 0x00000001 // MCU reset type and can be warm + // or not warm. + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure the power down clock for the MCU domain. +//! +//! Use this function to control which one of the clock sources that +//! is fed into the MCU domain when the system is in standby mode. When the +//! power is back in Active mode the clock source will automatically switch to +//! \ref AONWUC_CLOCK_SRC_HF. +//! +//! Each clock is fed 'as is' into the MCU domain, since the MCU domain +//! contains internal clock dividers controllable through the PRCM. +//! +//! \param ui32ClkSrc is the clock source for the MCU domain when in power +//! down. Values available as clock source: +//! - \ref AONWUC_NO_CLOCK +//! - \ref AONWUC_CLOCK_SRC_LF +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCMcuPowerDownConfig(uint32_t ui32ClkSrc) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT((ui32ClkSrc == AONWUC_NO_CLOCK) || + (ui32ClkSrc == AONWUC_CLOCK_SRC_LF)); + + // Set the clock source for the MCU domain when in power down. + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_MCUCLK); + ui32Reg &= ~AON_WUC_MCUCLK_PWR_DWN_SRC_M; + HWREG(AON_WUC_BASE + AON_WUC_O_MCUCLK) = ui32Reg | + (ui32ClkSrc << + AON_WUC_MCUCLK_PWR_DWN_SRC_S); +} + +//***************************************************************************** +// +//! \brief Configure the power down mode for the MCU domain. +//! +//! The parameter \c ui32Mode determines the power down mode of the MCU Voltage +//! Domain. When the AON WUC receives a request to power off the MCU domain it +//! can choose to power off completely or use a virtual power-off. In a virtual +//! power-off, reset is asserted and the clock is stopped but the power to the +//! domain is kept on. +//! +//! \param ui32Mode defines the power down mode of the MCU domain. +//! Allowed values for setting the virtual power-off are: +//! - \ref MCU_VIRT_PWOFF_DISABLE +//! - \ref MCU_VIRT_PWOFF_ENABLE +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCMcuPowerOffConfig(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == MCU_VIRT_PWOFF_ENABLE) || + (ui32Mode == MCU_VIRT_PWOFF_DISABLE)); + + // Set the powerdown mode. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_MCUCFG, AON_WUC_MCUCFG_VIRT_OFF_BITN) = (ui32Mode != 0); +} + +//***************************************************************************** +// +//! \brief Configure the wake-up procedure for the MCU domain. +//! +//! The MCU domain can wake up using two different procedures. Either it wakes +//! up immediately following the triggering event or wake-up is forced to +//! happen a fixed number of 32 KHz clocks following the triggering +//! event. The last can be used to compensate for any variable delays caused +//! by other activities going on at the time of wakeup (such as a recharge +//! event, etc.). +//! +//! \param ui32WakeUp determines the timing of the MCU wake up procedure. +//! - \ref MCU_IMM_WAKE_UP +//! - \ref MCU_FIXED_WAKE_UP +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCMcuWakeUpConfig(uint32_t ui32WakeUp) +{ + // Check the arguments. + ASSERT((ui32WakeUp == MCU_IMM_WAKE_UP) || + (ui32WakeUp == MCU_FIXED_WAKE_UP)); + + // Configure the wake up procedure. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_MCUCFG, AON_WUC_MCUCFG_FIXED_WU_EN_BITN) = (ui32WakeUp != 0); +} + +//***************************************************************************** +// +//! \brief Configure the retention on the block RAM in the MCU domain. +//! +//! MCU SRAM is partitioned into 4 banks of 1k x 32 each. The SRAM supports +//! retention on all 4 blocks. The retention on the SRAM can be turned on and +//! off. Use this function to enable the retention on the individual blocks. +//! +//! If a block is not represented in the parameter \c ui32Retention then the +//! the retention will be disabled for that block. +//! +//! \note Retention on the SRAM is not enabled by default. If retention is +//! turned off on all RAM blocks then the SRAM is powered off when it would +//! otherwise be put in retention mode. +//! +//! \param ui32Retention defines which RAM blocks to enable/disable retention on. +//! To enable retention on individual parts of the RAM use a bitwise OR'ed +//! combination of: +//! - \ref MCU_RAM0_RETENTION +//! - \ref MCU_RAM1_RETENTION +//! - \ref MCU_RAM2_RETENTION +//! - \ref MCU_RAM3_RETENTION +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCMcuSRamConfig(uint32_t ui32Retention) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32Retention & MCU_RAM_BLOCK_RETENTION); + ASSERT(!(ui32Retention & ~MCU_RAM_BLOCK_RETENTION)); + + // Configure the retention. + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_MCUCFG) & ~MCU_RAM_BLOCK_RETENTION; + ui32Reg |= ui32Retention; + HWREG(AON_WUC_BASE + AON_WUC_O_MCUCFG) = ui32Reg; +} + + +//***************************************************************************** +// +//! \brief Return the clock configuration for the AUX domain. +//! +//! The AUX domain does not have a local clock divider, so the AON WUC contains +//! a dedicated clock divider for AUX domain. Use this function to +//! get the setting of the clock divider. +//! +//! \return Return the clock configuration. Enumerated return values are: +//! - \ref AUX_CLOCK_DIV_2 +//! - \ref AUX_CLOCK_DIV_4 +//! - \ref AUX_CLOCK_DIV_8 +//! - \ref AUX_CLOCK_DIV_16 +//! - \ref AUX_CLOCK_DIV_32 +//! - \ref AUX_CLOCK_DIV_64 +//! - \ref AUX_CLOCK_DIV_128 +//! - \ref AUX_CLOCK_DIV_256 +//! +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONWUCAuxClockConfigGet(void) +{ + // Return the clock divider value. + return ((HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) & + AON_WUC_AUXCLK_SCLK_HF_DIV_M) >> + AON_WUC_AUXCLK_SCLK_HF_DIV_S); +} + +//***************************************************************************** +// +//! \brief Configure the power down mode for the AUX domain. +//! +//! Use this function to control which one of the clock sources that +//! is fed into the MCU domain when it is in Power Down mode. When the Power +//! is back in active mode the clock source will automatically switch to +//! \ref AONWUC_CLOCK_SRC_HF. +//! +//! Each clock is fed 'as is' into the AUX domain, since the AUX domain +//! contains internal clock dividers controllable through the PRCM. +//! +//! \param ui32ClkSrc is the clock source for the AUX domain when in power down. +//! - \ref AONWUC_NO_CLOCK +//! - \ref AONWUC_CLOCK_SRC_LF +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCAuxPowerDownConfig(uint32_t ui32ClkSrc) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT((ui32ClkSrc == AONWUC_NO_CLOCK) || + (ui32ClkSrc == AONWUC_CLOCK_SRC_LF)); + + // Set the clock source for the AUX domain when in power down. + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK); + ui32Reg &= ~AON_WUC_AUXCLK_PWR_DWN_SRC_M; + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg | + (ui32ClkSrc << + AON_WUC_AUXCLK_PWR_DWN_SRC_S); +} + + +//***************************************************************************** +// +//! \brief Configure the retention on the AUX SRAM. +//! +//! The AUX SRAM contains only one block which supports retention. The retention +//! on the SRAM can be turned on and off. Use this function to enable/disable +//! the retention on the entire RAM. +//! +//! \param ui32Retention either enables or disables AUX SRAM retention. +//! - 0 : Disable retention. +//! - 1 : Enable retention. +//! +//! \note Retention on the SRAM is not enabled by default. If retention is +//! turned off then the SRAM is powered off when it would otherwise be put in +//! retention mode. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCAuxSRamConfig(uint32_t ui32Retention) +{ + // Enable/disable the retention. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCFG, AON_WUC_AUXCFG_RAM_RET_EN_BITN) = ui32Retention; +} + +//***************************************************************************** +// +//! \brief Control the wake up procedure of the AUX domain. +//! +//! The AUX domain can be woken in two different modes. In both modes power +//! is turned on. In one mode a software event is generated for the +//! Sensor Controller and it is allowed to start processing. The second mode will +//! just force power on the Sensor Controller. If System CPU requires exclusive access +//! to the AUX domain resources, it is advised to ensure that the image in +//! the Sensor Controller memory is declared invalid. This can be achieved by +//! calling AONWUCAuxImageInvalid(). +//! +//! \note Any writes to the AON interface must pass a 32 kHz clock boundary, +//! and is therefore relatively slow. To ensure that a given write is +//! complete the value of the register can be read back after write. +// +//! \note When accessing the AUX domain from the System CPU, it is advised always to +//! have set the AUX in at least \ref AONWUC_AUX_WAKEUP. This overwrites any +//! instruction from the Sensor Controller and ensures that the AUX domain +//! is on so it won't leave the System CPU hanging. +//! +//! \param ui32Mode is the wake up mode for the AUX domain. +//! - \ref AONWUC_AUX_WAKEUP +//! - \ref AONWUC_AUX_ALLOW_SLEEP +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCAuxWakeupEvent(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == AONWUC_AUX_WAKEUP) || + (ui32Mode == AONWUC_AUX_ALLOW_SLEEP)); + + // Wake up the AUX domain. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_AUX_FORCE_ON_BITN) = ui32Mode; +} + +//***************************************************************************** +// +//! \brief Reset the AUX domain. +//! +//! Use this function to reset the entire AUX domain. The write to the AON_WUC +//! module must pass an 32 kHz clock boundary. By reading the +//! AON_RTC_O_SYNC register after each write, it is guaranteed that the AON +//! interface will be in sync and that both the assert and the de-assert of the +//! reset signal to AUX will propagate. +//! +//! \note This requires two writes and two reads on a 32 kHz clock boundary. +//! +//! \return None +// +//***************************************************************************** +extern void AONWUCAuxReset(void); + +//***************************************************************************** +// +//! \brief Tells the Sensor Controller that the image in memory is valid. +//! +//! Use this function to tell the sensor controller that the image in memory is +//! valid, and it is allowed to start executing the program. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCAuxImageValid(void) +{ + // Tell the Sensor Controller that the image in memory is valid. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_SCE_RUN_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Tells the Sensor Controller that the image in memory is invalid. +//! +//! Use this function to tell the sensor controller that the image in memory is +//! invalid. Sensor Controller might wake up, but it will stay idle. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCAuxImageInvalid(void) +{ + // Tell the Sensor Controller that the image in memory is invalid. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_SCE_RUN_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Get the power status of the device. +//! +//! The Always On (AON) domain is the only part of the device which is truly +//! "ALWAYS ON". The power status for the other device can always be read from +//! this status register. +//! +//! Possible power modes for the different parts of the device are: +//! +//! \return Returns the current power status of the device as a bitwise OR'ed +//! combination of these values: +//! - \ref AONWUC_AUX_POWER_DOWN +//! - \ref AONWUC_AUX_POWER_ON +//! - \ref AONWUC_JTAG_POWER_ON +//! - \ref AONWUC_MCU_POWER_ON +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONWUCPowerStatusGet(void) +{ + // Return the power status. + return (HWREG(AON_WUC_BASE + AON_WUC_O_PWRSTAT)); +} + +//***************************************************************************** +// +//! \brief Enable shut-down of the device. +//! +//! Use this function to enable shut-down of the device. This will force all I/O values to +//! be latched - possibly enabling I/O wakeup - then all internal power +//! supplies are turned off, effectively putting the device into shut-down mode. +//! +//! \note No action will take place before the System CPU is put to deep sleep. +//! +//! \note The shut-down command is ignored if the JTAG interface has been +//! activated. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCShutDownEnable(void) +{ + // Ensure the JTAG domain is turned off; + // otherwise MCU domain can't be turned off. + HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0; + + // Enable shutdown of the device. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_CTL0, AON_WUC_CTL0_PWR_DWN_DIS_BITN) = 0; + HWREG(AON_WUC_BASE + AON_WUC_O_SHUTDOWN) = AON_WUC_SHUTDOWN_EN; +} + +//***************************************************************************** +// +//! \brief Enable power down mode on AUX and MCU domain. +//! +//! Use this function to enable powerdown on the AUX and MCU domain. +//! +//! \note The powerdown command is ignored if the JTAG interface has been +//! activated. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCDomainPowerDownEnable(void) +{ + // Ensure the JTAG domain is turned off; + // otherwise MCU domain can't be turned off. + HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0; + + // Enable power down mode. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_CTL0, AON_WUC_CTL0_PWR_DWN_DIS_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Use this function to disable power down mode of the MCU and AUX domain. +//! +//! Disabling powerdown on the MCU and/or AUX will put the domains in a +//! virtual power down when requesting to be powered down. Logic is the same +//! but power is kept on. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCDomainPowerDownDisable(void) +{ + // Disable power down mode. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_CTL0, AON_WUC_CTL0_PWR_DWN_DIS_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Use this function to clear specific status bits. +//! +//! Use this function to clear the bits that are set in the AON WUC status +//! register. This register requires a write 1 to clear. +//! +//! AON Wake Up Controller TAP can request a total/full Flash erase. If so, +//! the corresponding status bits will be set in the status register and can +//! be read using \ref AONWUCMcuResetStatusGet() or cleared using this function. The reset +//! source and type give information about what and how the latest reset +//! was performed. Access to these bits are identical to the flash erase +//! bits. +//! +//! \param ui32Status defines in a one-hot encoding which bits to clear in the +//! status register. Use OR'ed combinations of the following: +//! - \ref AONWUC_MCU_RESET_SRC +//! - \ref AONWUC_MCU_WARM_RESET +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCMcuResetClear(uint32_t ui32Status) +{ + // Check the arguments. + ASSERT((ui32Status & AONWUC_MCU_RESET_SRC) || + (ui32Status & AONWUC_MCU_WARM_RESET)); + + // Clear the status bits. + HWREG(AON_WUC_BASE + AON_WUC_O_CTL1) = ui32Status; +} + +//***************************************************************************** +// +//! \brief Return the reset status. +//! +//! This function returns the value of the AON_WUC_O_CTL1 register. +//! +//! \return Returns the status from the AON WUC. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONWUCMcuResetStatusGet(void) +{ + // Return the current status. + return (HWREG(AON_WUC_BASE + AON_WUC_O_CTL1)); +} + +//***************************************************************************** +// +//! \brief Configure the recharge controller. +//! +//! The parameter \c bAdaptEnable is used to enable or disable the adaptive +//! algorithm for the recharge controller. +//! The adaptive algorithm for the recharge controller is defined as +//! +/*! +\verbatim + + New_Period = Period * (1 + (AdaptRate / 1024) ) + + AdaptRate + ----------- = ( 2^(-C1) + 2^(-C2) ) + 1024 + +\endverbatim +*/ +//! +//! Where C1 is between 1 and 10 and C2 is between 2 and 10. The \c ui32AdaptRate +//! must be a number between 2 and 768 (\ref RC_RATE_MIN and \ref RC_RATE_MAX) +//! resulting in an adaptive rate between 0.2% and 75%. +//! +//! The \c ui32Period is the number of 32 KHz clocks between two recharges. The +//! length of the interval is defined by the formula: +//! +/*! +\verbatim + + Period = ({ulMantissa,5'b1111} << ui32Exponent) + +\endverbatim +*/ +//! +//! \note The maximum number of recharge cycles is required when enabling the +//! adaptive recharge algorithm. +//! +//! \note The maximum period between two recharges should never exceed the +//! period between two oscillator amplitude calibrations which is configured +//! using AONWUCOscConfig(). +//! +//! \param bAdaptEnable enables the adaptation algorithm for the controller. +//! \param ui32AdaptRate determines the adjustment value for the adoption +//! algorithm. +//! \param ui32Period determines the number of clock cycles between each +//! activation of the recharge controller. +//! \param ui32MaxPeriod determines the maximum number of clock cycles between +//! each activation of the recharge controller. +//! +//! \return None +// +//***************************************************************************** +extern void AONWUCRechargeCtrlConfigSet(bool bAdaptEnable, + uint32_t ui32AdaptRate, + uint32_t ui32Period, + uint32_t ui32MaxPeriod); + +//***************************************************************************** +// +//! \brief Get the current configuration of the recharge controller. +//! +//! This function returns the value of the register AON_WUC_O_RECHARGECFG. +//! +//! \return Returns the current configuration of the recharge controller. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONWUCRechargeCtrlConfigGet(void) +{ + // Return the current configuration. + return(HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG)); +} + +//***************************************************************************** +// +//! \brief Configure the interval for oscillator amplitude calibration. +//! +//! Use this function to set the number of 32 kHz clocks between oscillator +//! amplitude calibrations. +//! +//! The value of the interval is defined by the formula: +//! +/*! +\verbatim + + Period = ({ulMantissa,5'b1111} << ui32Exponent) + +\endverbatim +*/ +//! +//! \note When this counter expires an oscillator amplitude calibration is +//! triggered immediately in Active mode. When this counter expires in +//! Powerdown mode an internal flag is set that causes GBIAS to turn on +//! together with BGAP when the next recharge occurs, at the same time +//! triggering the oscillator amplitude calibration as well as a recharge of +//! the uLDO reference voltage. +//! +//! \note The oscillator amplitude calibration is performed at the same time +//! as the recharge for the uLDO reference voltage. So the maximum period +//! between each recharge operation should not exceed the number of clock +//! cycles for the amplitude calibration. +//! +//! \param ui32Period is the number of 32 kHz clock cycles in each interval. +//! +//! \return None +// +//***************************************************************************** +extern void AONWUCOscConfig(uint32_t ui32Period); + +//***************************************************************************** +// +//! \brief Request power off of the JTAG domain. +//! +//! The JTAG domain is automatically powered up on if a debugger is connected. +//! If a debugger is not connected this function can be used to power off the +//! JTAG domain. +//! +//! \note Achieving the lowest power modes (shutdown/powerdown) requires the +//! JTAG domain to be turned off. In general the JTAG domain should never be +//! powered in production code. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCJtagPowerOff(void) +{ + // Request the power off of the Jtag domain + HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0; +} + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONWUCAuxReset + #undef AONWUCAuxReset + #define AONWUCAuxReset ROM_AONWUCAuxReset + #endif + #ifdef ROM_AONWUCRechargeCtrlConfigSet + #undef AONWUCRechargeCtrlConfigSet + #define AONWUCRechargeCtrlConfigSet ROM_AONWUCRechargeCtrlConfigSet + #endif + #ifdef ROM_AONWUCOscConfig + #undef AONWUCOscConfig + #define AONWUCOscConfig ROM_AONWUCOscConfig + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_WUC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_adc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_adc.c new file mode 100644 index 0000000..1a2d51f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_adc.c @@ -0,0 +1,337 @@ +/****************************************************************************** +* Filename: aux_adc.c +* Revised: 2017-11-20 14:31:35 +0100 (Mon, 20 Nov 2017) +* Revision: 50315 +* +* Description: Driver for the AUX Time to Digital Converter interface. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_adc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aux_wuc.h" +#include "../inc/hw_fcfg1.h" +#include "adi.h" +#include "event.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXADCDisable + #define AUXADCDisable NOROM_AUXADCDisable + #undef AUXADCEnableAsync + #define AUXADCEnableAsync NOROM_AUXADCEnableAsync + #undef AUXADCEnableSync + #define AUXADCEnableSync NOROM_AUXADCEnableSync + #undef AUXADCDisableInputScaling + #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling + #undef AUXADCFlushFifo + #define AUXADCFlushFifo NOROM_AUXADCFlushFifo + #undef AUXADCReadFifo + #define AUXADCReadFifo NOROM_AUXADCReadFifo + #undef AUXADCPopFifo + #define AUXADCPopFifo NOROM_AUXADCPopFifo + #undef AUXADCGetAdjustmentGain + #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain + #undef AUXADCGetAdjustmentOffset + #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset + #undef AUXADCValueToMicrovolts + #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts + #undef AUXADCMicrovoltsToValue + #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue + #undef AUXADCAdjustValueForGainAndOffset + #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset + #undef AUXADCUnadjustValueForGainAndOffset + #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset +#endif + +//***************************************************************************** +// +// Disables the ADC +// +//***************************************************************************** +void +AUXADCDisable(void) +{ + // Disable the ADC reference + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, ADI_4_AUX_ADCREF0_EN_M | ADI_4_AUX_ADCREF0_REF_ON_IDLE_M | ADI_4_AUX_ADCREF0_SRC_M); + + // Assert reset and disable the ADC + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M | ADI_4_AUX_ADC0_SMPL_MODE_M | ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M); + + // Ensure that scaling is enabled by default before next use of the ADC + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); + + // Flush the FIFO before disabling the clocks + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) + + // Disable the ADC clock (no need to wait since IOB_WUC_ADCCLKCTL_ACK goes low immediately) + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = 0; + + // Disable the ADC data interface + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = 0; +} + +//***************************************************************************** +// +// Enables the ADC for asynchronous operation +// +//***************************************************************************** +void +AUXADCEnableAsync(uint32_t refSource, uint32_t trigger) +{ + // Enable the ADC reference, with the following options: + // - SRC: Set when using relative reference + // - REF_ON_IDLE: Always cleared since there is no idle state in asynchronous operation + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, refSource | ADI_4_AUX_ADCREF0_EN_M); + + // Enable the ADC clock + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = AUX_WUC_ADCCLKCTL_REQ_M; + while (!(HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) & AUX_WUC_ADCCLKCTL_ACK_M)); + + // Enable the ADC data interface + if (trigger == AUXADC_TRIGGER_MANUAL) { + // Manual trigger: No need to configure event routing from GPT + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 | AUX_ANAIF_ADCCTL_CMD_EN; + } else { + // GPT trigger: Configure event routing via MCU_EV to the AUX domain + HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; + } + + // Configure the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_SMPL_MODE_M); + + // Release reset and enable the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); +} + +//***************************************************************************** +// +// Enables the ADC for synchronous operation +// +//***************************************************************************** +void +AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger) +{ + // Enable the ADC reference, with the following options: + // - SRC: Set when using relative reference + // - REF_ON_IDLE: Set when using fixed reference and sample time < 21.3 us + uint8_t adcref0 = refSource | ADI_4_AUX_ADCREF0_EN_M; + if (!refSource && (sampleTime < AUXADC_SAMPLE_TIME_21P3_US)) { + adcref0 |= ADI_4_AUX_ADCREF0_REF_ON_IDLE_M; + } + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, adcref0); + + // Enable the ADC clock + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = AUX_WUC_ADCCLKCTL_REQ_M; + while (!(HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) & AUX_WUC_ADCCLKCTL_ACK_M)); + + // Enable the ADC data interface + if (trigger == AUXADC_TRIGGER_MANUAL) { + // Manual trigger: No need to configure event routing from GPT + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 | AUX_ANAIF_ADCCTL_CMD_EN; + } else { + // GPT trigger: Configure event routing via MCU_EV to the AUX domain + HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; + } + + // Configure the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, sampleTime << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S); + + // Release reset and enable the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); +} + +//***************************************************************************** +// +// Disables scaling of the ADC input +// +//***************************************************************************** +void +AUXADCDisableInputScaling(void) +{ + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); +} + +//***************************************************************************** +// +// Flushes the ADC FIFO +// +//***************************************************************************** +void +AUXADCFlushFifo(void) +{ + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) +} + +//***************************************************************************** +// +// Waits for and returns the first sample in the ADC FIFO +// +//***************************************************************************** +uint32_t +AUXADCReadFifo(void) { + + // Wait until there is at least one sample in the FIFO + while (HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT) & AUX_ANAIF_ADCFIFOSTAT_EMPTY_M); + + // Return the first sample from the FIFO + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +//***************************************************************************** +// +// Returns the first sample in the ADC FIFO, without waiting +// +//***************************************************************************** +uint32_t +AUXADCPopFifo(void) { + + // Return the first sample from the FIFO. If the FIFO is empty, this + // generates ADC FIFO underflow + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +//***************************************************************************** +// +// Returns the gain value used when adjusting for ADC gain/offset +// +//***************************************************************************** +int32_t +AUXADCGetAdjustmentGain(uint32_t refSource) +{ + int32_t gain; + if (refSource == AUXADC_REF_FIXED) { + // AUXADC_REF_FIXED ==> ABS_GAIN + gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_ABS_GAIN) & FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S; + } else { + // AUXADC_REF_VDDS_REL ==> REL_GAIN + gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_REL_GAIN) & FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S; + } + return gain; +} + +//***************************************************************************** +// +// Returns the offset value used when adjusting for ADC gain/offset +// +//***************************************************************************** +int32_t +AUXADCGetAdjustmentOffset(uint32_t refSource) +{ + int8_t offset; + if ( refSource == AUXADC_REF_FIXED ) { + // AUXADC_REF_FIXED ==> ABS_OFFSET + offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S; + } else { + // AUXADC_REF_VDDS_REL ==> REL_OFFSET + offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S; + } + return offset; +} + +//***************************************************************************** +// +// Converts an "ideal" ADC value to microvolts +// +//***************************************************************************** +int32_t +AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue) +{ + // Chop off 4 bits during calculations to avoid 32-bit overflow + fixedRefVoltage >>= 4; + return (((adcValue * fixedRefVoltage) + 2047) / 4095) << 4; +} + +//***************************************************************************** +// +// Converts a number of microvolts to corresponding "ideal" ADC value +// +//***************************************************************************** +int32_t +AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts) +{ + // Chop off 4 bits during calculations to avoid 32-bit overflow + fixedRefVoltage >>= 4; + microvolts >>= 4; + return ((microvolts * 4095) + (fixedRefVoltage / 2)) / fixedRefVoltage; +} + +//***************************************************************************** +// +// Performs ADC value gain and offset adjustment +// +//***************************************************************************** +int32_t +AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) +{ + // Apply gain and offset adjustment + adcValue = (((adcValue + offset) * gain) + 16384) / 32768; + + // Saturate + if (adcValue < 0) { + return 0; + } else if (adcValue > 4095) { + return 4095; + } else { + return adcValue; + } +} + +//***************************************************************************** +// +// Performs the inverse of the ADC value gain and offset adjustment +// +//***************************************************************************** +int32_t +AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) +{ + // Apply inverse gain and offset adjustment + adcValue = (((adcValue * 32768) + (gain / 2)) / gain) - offset; + + // Saturate + if (adcValue < 0) { + return 0; + } else if (adcValue > 4095) { + return 4095; + } else { + return adcValue; + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_adc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_adc.h new file mode 100644 index 0000000..55631d7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_adc.h @@ -0,0 +1,590 @@ +/****************************************************************************** +* Filename: aux_adc.h +* Revised: 2018-02-07 09:45:39 +0100 (Wed, 07 Feb 2018) +* Revision: 51437 +* +* Description: Defines and prototypes for the AUX Analog-to-Digital +* Converter +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxadc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_ADC_H__ +#define __AUX_ADC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_event.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_4_aux.h" +#include "../inc/hw_aux_anaif.h" +#include "rom.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXADCDisable NOROM_AUXADCDisable + #define AUXADCEnableAsync NOROM_AUXADCEnableAsync + #define AUXADCEnableSync NOROM_AUXADCEnableSync + #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling + #define AUXADCFlushFifo NOROM_AUXADCFlushFifo + #define AUXADCReadFifo NOROM_AUXADCReadFifo + #define AUXADCPopFifo NOROM_AUXADCPopFifo + #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain + #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset + #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts + #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue + #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset + #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset +#endif + +//***************************************************************************** +// +// Defines for ADC reference sources. +// +//***************************************************************************** +#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S) +#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S) + +//***************************************************************************** +// +// Defines for the ADC FIFO status bits. +// +//***************************************************************************** +#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M) +#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M) +#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M) +#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M) +#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M) + +//***************************************************************************** +// +// Defines for supported ADC triggers. +// +//***************************************************************************** +#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE) +#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A) +#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B) +#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A) +#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B) +#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A) +#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B) +#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A) +#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B) + +//***************************************************************************** +// +// Defines for ADC sampling type for synchronous operation. +// +//***************************************************************************** +#define AUXADC_SAMPLE_TIME_2P7_US 3 +#define AUXADC_SAMPLE_TIME_5P3_US 4 +#define AUXADC_SAMPLE_TIME_10P6_US 5 +#define AUXADC_SAMPLE_TIME_21P3_US 6 +#define AUXADC_SAMPLE_TIME_42P6_US 7 +#define AUXADC_SAMPLE_TIME_85P3_US 8 +#define AUXADC_SAMPLE_TIME_170_US 9 +#define AUXADC_SAMPLE_TIME_341_US 10 +#define AUXADC_SAMPLE_TIME_682_US 11 +#define AUXADC_SAMPLE_TIME_1P37_MS 12 +#define AUXADC_SAMPLE_TIME_2P73_MS 13 +#define AUXADC_SAMPLE_TIME_5P46_MS 14 +#define AUXADC_SAMPLE_TIME_10P9_MS 15 + +//***************************************************************************** +// +// Equivalent voltages for fixed ADC reference, in microvolts. +// +//***************************************************************************** +#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000 +#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500 + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + + +//***************************************************************************** +// +//! \brief Disables the ADC. +//! +//! This function must be called: +//! - Before re-enabling the ADC using \ref AUXADCEnableAsync() or +//! \ref AUXADCEnableSync() +//! - Before entering system standby +// +//***************************************************************************** +extern void AUXADCDisable(void); + +//***************************************************************************** +// +//! \brief Enables the ADC for asynchronous operation. +//! +//! In asynchronous operation, the ADC samples continuously between +//! conversions. +//! +//! The ADC trigger starts the conversion. Note that the first conversion may +//! be invalid if the sampling period is too short. +//! +//! ADC input scaling is enabled by default after device reset, and is also re- +//! enabled by \ref AUXADCDisable(). To disable input scaling, call +//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableAsync(). +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! \param trigger +//! ADC conversion trigger: +//! - \ref AUXADC_TRIGGER_MANUAL +//! - \ref AUXADC_TRIGGER_GPT0A +//! - \ref AUXADC_TRIGGER_GPT0B +//! - \ref AUXADC_TRIGGER_GPT1A +//! - \ref AUXADC_TRIGGER_GPT1B +//! - \ref AUXADC_TRIGGER_GPT2A +//! - \ref AUXADC_TRIGGER_GPT2B +//! - \ref AUXADC_TRIGGER_GPT3A +//! - \ref AUXADC_TRIGGER_GPT3B +// +//***************************************************************************** +extern void AUXADCEnableAsync(uint32_t refSource, uint32_t trigger); + +//***************************************************************************** +// +//! \brief Enables the ADC for synchronous operation. +//! +//! In synchronous operation, the ADC is idle between a conversion and +//! subsequent samplings. +//! +//! The ADC trigger starts sampling with specified duration, followed by the +//! conversion. Note that the first conversion may be invalid if the initial +//! sampling period is too short. +//! +//! ADC input scaling is enabled by default after device reset, and is also re- +//! enabled by \ref AUXADCDisable(). To disable input scaling, call +//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableSync(). +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! \param sampleTime +//! ADC sampling time: +//! - \ref AUXADC_SAMPLE_TIME_2P7_US +//! - \ref AUXADC_SAMPLE_TIME_5P3_US +//! - \ref AUXADC_SAMPLE_TIME_10P6_US +//! - \ref AUXADC_SAMPLE_TIME_21P3_US +//! - \ref AUXADC_SAMPLE_TIME_42P6_US +//! - \ref AUXADC_SAMPLE_TIME_85P3_US +//! - \ref AUXADC_SAMPLE_TIME_170_US +//! - \ref AUXADC_SAMPLE_TIME_341_US +//! - \ref AUXADC_SAMPLE_TIME_682_US +//! - \ref AUXADC_SAMPLE_TIME_1P37_MS +//! - \ref AUXADC_SAMPLE_TIME_2P73_MS +//! - \ref AUXADC_SAMPLE_TIME_5P46_MS +//! - \ref AUXADC_SAMPLE_TIME_10P9_MS +//! \param trigger +//! ADC conversion trigger: +//! - \ref AUXADC_TRIGGER_MANUAL +//! - \ref AUXADC_TRIGGER_GPT0A +//! - \ref AUXADC_TRIGGER_GPT0B +//! - \ref AUXADC_TRIGGER_GPT1A +//! - \ref AUXADC_TRIGGER_GPT1B +//! - \ref AUXADC_TRIGGER_GPT2A +//! - \ref AUXADC_TRIGGER_GPT2B +//! - \ref AUXADC_TRIGGER_GPT3A +//! - \ref AUXADC_TRIGGER_GPT3B +// +//***************************************************************************** +extern void AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger); + +//***************************************************************************** +// +//! \brief Disables scaling of the ADC input. +//! +//! By default, the ADC operates internally on a version of the input signal +//! that has been scaled down by a factor 1408 / 4095. This function +//! disables that scaling, allowing for a trade-off between dynamic range and +//! and resolution. +//! +//! \note This function must only be called while the ADC is disabled, before +//! calling \ref AUXADCEnableSync() or \ref AUXADCEnableAsync(). +//! \note Different input maximum ratings apply when input scaling is disabled. +//! Violating these may damage the device. +// +//***************************************************************************** +extern void AUXADCDisableInputScaling(void); + +//***************************************************************************** +// +//! \brief Flushes the ADC FIFO. +//! +//! This empties the FIFO and clears the underflow/overflow flags. +//! +//! Note: This function must only be called while the ADC is enabled. +// +//***************************************************************************** +extern void AUXADCFlushFifo(void); + +//***************************************************************************** +// +//! \brief Generates a single manual ADC trigger. +//! +//! For synchronous mode, the trigger starts sampling followed by conversion. +//! For asynchronous mode, the trigger starts conversion. +// +//***************************************************************************** +__STATIC_INLINE void +AUXADCGenManualTrigger(void) +{ + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCTRIG) = 0; +} + +//***************************************************************************** +// +//! \brief Returns flags indicating the status of the ADC FIFO. +//! +//! The flags indicate FIFO empty, full and almost full, and whether +//! overflow/underflow has occurred. +//! +//! \return +//! A combination (bitwise OR) of the following flags: +//! - \ref AUXADC_FIFO_EMPTY_M +//! - \ref AUXADC_FIFO_ALMOST_FULL_M +//! - \ref AUXADC_FIFO_FULL_M +//! - \ref AUXADC_FIFO_UNDERFLOW_M +//! - \ref AUXADC_FIFO_OVERFLOW_M +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXADCGetFifoStatus(void) +{ + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT); +} + +//***************************************************************************** +// +//! \brief Waits for and returns the first sample in the ADC FIFO. +//! +//! This function waits until there is at least one sample in the ADC FIFO. It +//! then pops and returns the first sample from the FIFO. +//! +//! \note This procedure will deadlock if called without setting up ADC trigger +//! generation in advance. The trigger can either be manual or periodical +//! (using a GPT). +//! +//! \return The first (12-bit) sample from the ADC FIFO +// +//***************************************************************************** +extern uint32_t AUXADCReadFifo(void); + +//***************************************************************************** +// +//! \brief Returns the first sample in the ADC FIFO, without waiting. +//! +//! This function does not wait, and must only be called when there is at least +//! one sample in the ADC FIFO. Otherwise the call will generate FIFO underflow +//! (\ref AUXADC_FIFO_UNDERFLOW_M). +//! +//! \return The first (12-bit) sample from the ADC FIFO, or an undefined value +//! if the FIFO is empty +// +//***************************************************************************** +extern uint32_t AUXADCPopFifo(void); + +//***************************************************************************** +// +//! \brief Selects internal or external input for the ADC. +//! +//! Note that calling this function also selects the same input for AUX_COMPB. +//! +//! \param input +//! Internal/external input selection: +//! - \ref ADC_COMPB_IN_DCOUPL +//! - \ref ADC_COMPB_IN_VSS +//! - \ref ADC_COMPB_IN_VDDS +//! - \ref ADC_COMPB_IN_AUXIO7 +//! - \ref ADC_COMPB_IN_AUXIO6 +//! - \ref ADC_COMPB_IN_AUXIO5 +//! - \ref ADC_COMPB_IN_AUXIO4 +//! - \ref ADC_COMPB_IN_AUXIO3 +//! - \ref ADC_COMPB_IN_AUXIO2 +//! - \ref ADC_COMPB_IN_AUXIO1 +//! - \ref ADC_COMPB_IN_AUXIO0 +// +//***************************************************************************** +__STATIC_INLINE void +AUXADCSelectInput(uint32_t input) +{ + HapiSelectADCCompBInput(input); +} + +//***************************************************************************** +// +//! \brief Returns the gain value used when adjusting for ADC gain/offset. +//! +//! The function returns the gain value to be used with +//! \ref AUXADCAdjustValueForGainAndOffset() or +//! \ref AUXADCUnadjustValueForGainAndOffset(). The gain value is found during +//! chip manufacturing and is stored in the factory configuration, FCFG1. +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! +//! \return +//! The gain value to be used in adjustments +// +//***************************************************************************** +extern int32_t AUXADCGetAdjustmentGain(uint32_t refSource); + +//***************************************************************************** +// +//! \brief Returns the offset value used when adjusting for ADC gain/offset. +//! +//! The function returns the offset value to be used with +//! \ref AUXADCAdjustValueForGainAndOffset() or +//! \ref AUXADCUnadjustValueForGainAndOffset(). The offset value is found +//! during chip manufacturing and is stored in the factory configuration, +//! FCFG1. +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! +//! \return +//! The offset value to be used in adjustments +// +//***************************************************************************** +extern int32_t AUXADCGetAdjustmentOffset(uint32_t refSource); + +//***************************************************************************** +// +//! \brief Converts an "adjusted" ADC value to microvolts. +//! +//! This function can only be used when measuring with fixed ADC reference +//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for +//! whether the sampled ADC input is scaled down before conversion or not. +//! +//! \param fixedRefVoltage +//! Fixed reference voltage, in microvolts +//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal) +//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input +//! \param adcValue +//! The ADC value +//! +//! \return +//! The corresponding number of microvolts +// +//***************************************************************************** +extern int32_t AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue); + +//***************************************************************************** +// +//! \brief Converts a number of microvolts to corresponding "adjusted" ADC value. +//! +//! This function can only be used when measuring with fixed ADC reference +//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for +//! whether the sampled ADC input is scaled down before conversion or not. +//! +//! \param fixedRefVoltage +//! Fixed reference voltage, in microvolts +//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal) +//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input +//! \param microvolts +//! The number of microvolts +//! +//! \return +//! The corresponding expected ADC value (adjusted for ADC gain/offset) +// +//***************************************************************************** +extern int32_t AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts); + +//***************************************************************************** +// +//! \brief Performs ADC value gain and offset adjustment. +//! +//! This function takes a measured ADC value compensates for the internal gain +//! and offset in the ADC. +//! +//! \param adcValue +//! 12-bit ADC unadjusted value +//! \param gain +//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain() +//! \param offset +//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset() +//! +//! \return +//! 12-bit ADC adjusted value +// +//***************************************************************************** +extern int32_t AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset); + +//***************************************************************************** +// +//! \brief Performs the inverse of the ADC value gain and offset adjustment. +//! +//! This function finds the expected measured ADC value, without gain and +//! offset compensation, for a given "ideal" ADC value. The function can for +//! example be used to find ADC value thresholds to be used in Sensor +//! Controller task configurations. +//! +//! \param adcValue +//! 12-bit ADC adjusted value +//! \param gain +//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain() +//! \param offset +//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset() +//! +//! \return +//! 12-bit ADC unadjusted value +// +//***************************************************************************** +extern int32_t AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXADCDisable + #undef AUXADCDisable + #define AUXADCDisable ROM_AUXADCDisable + #endif + #ifdef ROM_AUXADCEnableAsync + #undef AUXADCEnableAsync + #define AUXADCEnableAsync ROM_AUXADCEnableAsync + #endif + #ifdef ROM_AUXADCEnableSync + #undef AUXADCEnableSync + #define AUXADCEnableSync ROM_AUXADCEnableSync + #endif + #ifdef ROM_AUXADCDisableInputScaling + #undef AUXADCDisableInputScaling + #define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling + #endif + #ifdef ROM_AUXADCFlushFifo + #undef AUXADCFlushFifo + #define AUXADCFlushFifo ROM_AUXADCFlushFifo + #endif + #ifdef ROM_AUXADCReadFifo + #undef AUXADCReadFifo + #define AUXADCReadFifo ROM_AUXADCReadFifo + #endif + #ifdef ROM_AUXADCPopFifo + #undef AUXADCPopFifo + #define AUXADCPopFifo ROM_AUXADCPopFifo + #endif + #ifdef ROM_AUXADCGetAdjustmentGain + #undef AUXADCGetAdjustmentGain + #define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain + #endif + #ifdef ROM_AUXADCGetAdjustmentOffset + #undef AUXADCGetAdjustmentOffset + #define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset + #endif + #ifdef ROM_AUXADCValueToMicrovolts + #undef AUXADCValueToMicrovolts + #define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts + #endif + #ifdef ROM_AUXADCMicrovoltsToValue + #undef AUXADCMicrovoltsToValue + #define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue + #endif + #ifdef ROM_AUXADCAdjustValueForGainAndOffset + #undef AUXADCAdjustValueForGainAndOffset + #define AUXADCAdjustValueForGainAndOffset ROM_AUXADCAdjustValueForGainAndOffset + #endif + #ifdef ROM_AUXADCUnadjustValueForGainAndOffset + #undef AUXADCUnadjustValueForGainAndOffset + #define AUXADCUnadjustValueForGainAndOffset ROM_AUXADCUnadjustValueForGainAndOffset + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_ADC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_smph.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_smph.c new file mode 100644 index 0000000..76dc0b1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_smph.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: aux_smph.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the AUX Semaphore. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_smph.h" + +// See aux_smph.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_smph.h new file mode 100644 index 0000000..4ff1314 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_smph.h @@ -0,0 +1,258 @@ +/****************************************************************************** +* Filename: aux_smph.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the AUX Semaphore +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxsmph_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_SMPH_H__ +#define __AUX_SMPH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_aux_smph.h" +#include "../inc/hw_memmap.h" +#include "debug.h" + +//***************************************************************************** +// +// General constants and defines +// +//***************************************************************************** +#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed + +//***************************************************************************** +// +// Values that can be passed to AUXSMPHAcquire and AUXSMPHRelease +// as the ui32Semaphore parameter. +// +//***************************************************************************** +#define AUX_SMPH_0 0 // AUX Semaphore 0 +#define AUX_SMPH_1 1 // AUX Semaphore 1 +#define AUX_SMPH_2 2 // AUX Semaphore 2 +#define AUX_SMPH_3 3 // AUX Semaphore 3 +#define AUX_SMPH_4 4 // AUX Semaphore 4 +#define AUX_SMPH_5 5 // AUX Semaphore 5 +#define AUX_SMPH_6 6 // AUX Semaphore 6 +#define AUX_SMPH_7 7 // AUX Semaphore 7 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Acquire an AUX semaphore. +//! +//! This function acquires the given AUX semaphore, blocking the call until +//! the semaphore is available. +//! +//! \note The semaphore can also be acquired by the dedicated Sensor Controller. +//! The System CPU master can thus be competing for the shared resource, i.e. +//! the specified semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref AUX_SMPH_0 +//! - \ref AUX_SMPH_1 +//! - \ref AUX_SMPH_2 +//! - \ref AUX_SMPH_3 +//! - \ref AUX_SMPH_4 +//! - \ref AUX_SMPH_5 +//! - \ref AUX_SMPH_6 +//! - \ref AUX_SMPH_7 +//! +//! \return None +//! +//! \sa AUXSMPHTryAcquire(), AUXSMPHRelease() +// +//***************************************************************************** +__STATIC_INLINE void +AUXSMPHAcquire(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == AUX_SMPH_0) || + (ui32Semaphore == AUX_SMPH_1) || + (ui32Semaphore == AUX_SMPH_2) || + (ui32Semaphore == AUX_SMPH_3) || + (ui32Semaphore == AUX_SMPH_4) || + (ui32Semaphore == AUX_SMPH_5) || + (ui32Semaphore == AUX_SMPH_6) || + (ui32Semaphore == AUX_SMPH_7)); + + // Wait for semaphore to be released such that it can be claimed + // Semaphore register reads 1 when lock was acquired otherwise 0 + // (i.e. AUX_SMPH_CLAIMED). + while(HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) == + AUX_SMPH_CLAIMED) + { + } +} + +//***************************************************************************** +// +//! \brief Try to acquire an AUX semaphore. +//! +//! This function tries to acquire the given AUX semaphore, if the semaphore +//! could not be claimed the function returns false. +//! +//! \note The semaphore can also be acquired by the dedicated Sensor Controller. +//! The System CPU master can thus be competing for the shared resource, i.e. +//! the specified semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref AUX_SMPH_0 +//! - \ref AUX_SMPH_1 +//! - \ref AUX_SMPH_2 +//! - \ref AUX_SMPH_3 +//! - \ref AUX_SMPH_4 +//! - \ref AUX_SMPH_5 +//! - \ref AUX_SMPH_6 +//! - \ref AUX_SMPH_7 +//! +//! \return Returns true if semaphore was acquired, false otherwise +//! +//! \sa AUXSMPHAcquire(), AUXSMPHRelease() +// +//***************************************************************************** +__STATIC_INLINE bool +AUXSMPHTryAcquire(uint32_t ui32Semaphore) +{ + uint32_t ui32SemaReg; + + // Check the arguments. + ASSERT((ui32Semaphore == AUX_SMPH_0) || + (ui32Semaphore == AUX_SMPH_1) || + (ui32Semaphore == AUX_SMPH_2) || + (ui32Semaphore == AUX_SMPH_3) || + (ui32Semaphore == AUX_SMPH_4) || + (ui32Semaphore == AUX_SMPH_5) || + (ui32Semaphore == AUX_SMPH_6) || + (ui32Semaphore == AUX_SMPH_7)); + + // AUX Semaphore register reads 1 if lock was acquired + // (i.e. SMPH_FREE when read) but subsequent reads will read 0. + ui32SemaReg = HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore); + + return (ui32SemaReg == AUX_SMPH_FREE); +} + +//***************************************************************************** +// +//! \brief Release an AUX semaphore by System CPU master. +//! +//! This function releases the given AUX semaphore. +//! +//! \note It is up to the application to provide the convention for clearing +//! semaphore. +//! +//! \note The semaphore can also be acquired by the dedicated Sensor Controller. +//! The System CPU master can thus be competing for the shared resource, i.e. +//! the specified semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref AUX_SMPH_0 +//! - \ref AUX_SMPH_1 +//! - \ref AUX_SMPH_2 +//! - \ref AUX_SMPH_3 +//! - \ref AUX_SMPH_4 +//! - \ref AUX_SMPH_5 +//! - \ref AUX_SMPH_6 +//! - \ref AUX_SMPH_7 +//! +//! \return None +//! +//! \sa AUXSMPHAcquire(), AUXSMPHTryAcquire() +// +//***************************************************************************** +__STATIC_INLINE void +AUXSMPHRelease(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == AUX_SMPH_0) || + (ui32Semaphore == AUX_SMPH_1) || + (ui32Semaphore == AUX_SMPH_2) || + (ui32Semaphore == AUX_SMPH_3) || + (ui32Semaphore == AUX_SMPH_4) || + (ui32Semaphore == AUX_SMPH_5) || + (ui32Semaphore == AUX_SMPH_6) || + (ui32Semaphore == AUX_SMPH_7)); + + // No check before release. It is up to the application to provide the + // conventions for who and when a semaphore can be released. + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) = + AUX_SMPH_FREE; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_SMPH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_tdc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_tdc.c new file mode 100644 index 0000000..4e6993e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_tdc.c @@ -0,0 +1,111 @@ +/****************************************************************************** +* Filename: aux_tdc.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the AUX Time to Digital Converter interface. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_tdc.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXTDCConfigSet + #define AUXTDCConfigSet NOROM_AUXTDCConfigSet + #undef AUXTDCMeasurementDone + #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone +#endif + +//***************************************************************************** +// +// Configure the operation of the AUX TDC +// +//***************************************************************************** +void +AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, + uint32_t ui32StopCondition) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Make sure the AUX TDC is in the idle state before changing the + // configuration. + while(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + } + + // Clear previous results. + HWREG(ui32Base + AUX_TDC_O_CTL) = 0x0; + + // Change the configuration. + HWREG(ui32Base + AUX_TDC_O_TRIGSRC) = ui32StartCondition | ui32StopCondition; +} + +//***************************************************************************** +// +// Check if the AUX TDC is done measuring +// +//***************************************************************************** +uint32_t +AUXTDCMeasurementDone(uint32_t ui32Base) +{ + uint32_t ui32Reg; + uint32_t ui32Status; + + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is done measuring. + ui32Reg = HWREG(ui32Base + AUX_TDC_O_STAT); + if(ui32Reg & AUX_TDC_STAT_DONE) + { + ui32Status = AUX_TDC_DONE; + } + else if(ui32Reg & AUX_TDC_STAT_SAT) + { + ui32Status = AUX_TDC_TIMEOUT; + } + else + { + ui32Status = AUX_TDC_BUSY; + } + + // Return the status. + return (ui32Status); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_tdc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_tdc.h new file mode 100644 index 0000000..a8f567f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_tdc.h @@ -0,0 +1,776 @@ +/****************************************************************************** +* Filename: aux_tdc.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Defines and prototypes for the AUX Time-to-Digital Converter +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxtdc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_TDC_H__ +#define __AUX_TDC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aux_tdc.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXTDCConfigSet NOROM_AUXTDCConfigSet + #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone +#endif + +//***************************************************************************** +// +// Defines for the status of a AUX TDC measurement. +// +//***************************************************************************** +#define AUX_TDC_BUSY 0x00000001 +#define AUX_TDC_TIMEOUT 0x00000002 +#define AUX_TDC_DONE 0x00000004 + +//***************************************************************************** +// +// Defines for the control of a AUX TDC. +// +//***************************************************************************** +#define AUX_TDC_RUNSYNC 0x00000001 +#define AUX_TDC_RUN 0x00000002 +#define AUX_TDC_ABORT 0x00000003 + +//***************************************************************************** +// +// Defines for possible states of the TDC internal state machine. +// +//***************************************************************************** +#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START) +#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN) +#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE) +#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT) +#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP) +#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN) +#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT) +#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR) +#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE) +#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL) +#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP) + +//***************************************************************************** +// +// Defines for controlling the AUX TDC. Values can be passed to AUXTDCConfigSet(). +// +//***************************************************************************** +#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event +#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event + +#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0) +#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1) +#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2) +#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3) +#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4) +#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5) +#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6) +#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7) +#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8) +#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9) +#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10) +#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11) +#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12) +#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13) +#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14) +#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15) +#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE) +#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL) +#define AUXTDC_STOP_AON_PROG_WU (AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU) +#define AUXTDC_STOP_AON_SW (AUX_TDC_TRIGSRC_STOP_SRC_AON_SW) +#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET) +#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0) +#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1) +#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE) +#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE) +#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV) +#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV) +#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2) +#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA) +#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB) +#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF) +#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV) + +#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event +#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event + +#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0) +#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1) +#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2) +#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3) +#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4) +#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5) +#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6) +#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7) +#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8) +#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9) +#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10) +#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11) +#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12) +#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13) +#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14) +#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15) +#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_ADC_DONE) +#define AUXTDC_START_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL) +#define AUXTDC_START_AON_PROG_WU (AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU) +#define AUXTDC_START_AON_SW (AUX_TDC_TRIGSRC_START_SRC_AON_SW) +#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET) +#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX0) +#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX1) +#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE) +#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_TDC_PRE) +#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV) +#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV) +#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2) +#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA) +#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB) +#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF) +#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV) + +//***************************************************************************** +// +// Defines for the possible saturation values set using AUXTDCLimitSet(). +// +//***************************************************************************** +#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12) +#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13) +#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14) +#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15) +#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16) +#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17) +#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18) +#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19) +#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20) +#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21) +#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22) +#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23) +#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24) +#define AUXTDC_NUM_SAT_VALS 16 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! \brief Checks an AUX TDC base address. +//! +//! This function determines if a AUX TDC port base address is valid. +//! +//! \param ui32Base is the base address of the AUX TDC port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +AUXTDCBaseValid(uint32_t ui32Base) +{ + return(ui32Base == AUX_TDC_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Get the status of the AUX TDC internal state machine. +//! +//! This function will return the current state of the AUX TDC internal state +//! machine. +//! \param ui32Base is base address of the AUX TDC +//! +//! \return Returns the current state of the state machine. +//! Possible states for the state machine are: +//! - \ref AUXTDC_WAIT_START +//! - \ref AUXTDC_WAIT_START_CNTEN +//! - \ref AUXTDC_IDLE +//! - \ref AUXTDC_CLRCNT +//! - \ref AUXTDC_WAIT_STOP +//! - \ref AUXTDC_WAIT_STOP_CNTDOWN +//! - \ref AUXTDC_GETRESULTS +//! - \ref AUXTDC_POR +//! - \ref AUXTDC_WAIT_CLRCNT_DONE +//! - \ref AUXTDC_START_FALL +//! - \ref AUXTDC_FORCE_STOP. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCStatusGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the status value for the correct ADI Slave. + return((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) >> + AUX_TDC_STAT_STATE_S); +} + +//***************************************************************************** +// +//! \brief Configure the operation of the AUX TDC. +//! +//! Use this function to configure the start and stop event for the AUX TDC. +//! +//! The \c ui32StartCondition must be a bitwise OR of the start event and the +//! polarity of the start event. The start events are: +//! - \ref AUXTDC_START_AUXIO0 +//! - \ref AUXTDC_START_AUXIO1 +//! - \ref AUXTDC_START_AUXIO2 +//! - \ref AUXTDC_START_AUXIO3 +//! - \ref AUXTDC_START_AUXIO4 +//! - \ref AUXTDC_START_AUXIO5 +//! - \ref AUXTDC_START_AUXIO6 +//! - \ref AUXTDC_START_AUXIO7 +//! - \ref AUXTDC_START_AUXIO8 +//! - \ref AUXTDC_START_AUXIO9 +//! - \ref AUXTDC_START_AUXIO10 +//! - \ref AUXTDC_START_AUXIO11 +//! - \ref AUXTDC_START_AUXIO12 +//! - \ref AUXTDC_START_AUXIO13 +//! - \ref AUXTDC_START_AUXIO14 +//! - \ref AUXTDC_START_AUXIO15 +//! - \ref AUXTDC_START_ADC_DONE +//! - \ref AUXTDC_START_ADC_FIFO_ALMOST_FULL +//! - \ref AUXTDC_START_AON_PROG_WU +//! - \ref AUXTDC_START_AON_SW +//! - \ref AUXTDC_START_ISRC_RESET +//! - \ref AUXTDC_START_OBSMUX0 +//! - \ref AUXTDC_START_OBSMUX1 +//! - \ref AUXTDC_START_SMPH_AUTOTAKE_DONE +//! - \ref AUXTDC_START_TDC_PRE +//! - \ref AUXTDC_START_TIMER0_EV +//! - \ref AUXTDC_START_TIMER1_EV +//! - \ref AUXTDC_START_AON_RTC_CH2 +//! - \ref AUXTDC_START_AUX_COMPA +//! - \ref AUXTDC_START_AUX_COMPB +//! - \ref AUXTDC_START_ACLK_REF +//! - \ref AUXTDC_START_MCU_EV +//! +//! The polarity of the start event is either rising \ref AUXTDC_STARTPOL_RIS +//! or falling \ref AUXTDC_STARTPOL_FALL. +//! +//! The \c ui32StopCondition must be a bitwise OR of the stop event and the +//! polarity of the stop event. The stop events are: +//! - \ref AUXTDC_STOP_AUXIO0 +//! - \ref AUXTDC_STOP_AUXIO1 +//! - \ref AUXTDC_STOP_AUXIO2 +//! - \ref AUXTDC_STOP_AUXIO3 +//! - \ref AUXTDC_STOP_AUXIO4 +//! - \ref AUXTDC_STOP_AUXIO5 +//! - \ref AUXTDC_STOP_AUXIO6 +//! - \ref AUXTDC_STOP_AUXIO7 +//! - \ref AUXTDC_STOP_AUXIO8 +//! - \ref AUXTDC_STOP_AUXIO9 +//! - \ref AUXTDC_STOP_AUXIO10 +//! - \ref AUXTDC_STOP_AUXIO11 +//! - \ref AUXTDC_STOP_AUXIO12 +//! - \ref AUXTDC_STOP_AUXIO13 +//! - \ref AUXTDC_STOP_AUXIO14 +//! - \ref AUXTDC_STOP_AUXIO15 +//! - \ref AUXTDC_STOP_ADC_DONE +//! - \ref AUXTDC_STOP_ADC_FIFO_ALMOST_FULL +//! - \ref AUXTDC_STOP_AON_PROG_WU +//! - \ref AUXTDC_STOP_AON_SW +//! - \ref AUXTDC_STOP_ISRC_RESET +//! - \ref AUXTDC_STOP_OBSMUX0 +//! - \ref AUXTDC_STOP_OBSMUX1 +//! - \ref AUXTDC_STOP_SMPH_AUTOTAKE_DONE +//! - \ref AUXTDC_STOP_TDC_PRE +//! - \ref AUXTDC_STOP_TIMER0_EV +//! - \ref AUXTDC_STOP_TIMER1_EV +//! - \ref AUXTDC_STOP_AON_RTC_CH2 +//! - \ref AUXTDC_STOP_AUX_COMPA +//! - \ref AUXTDC_STOP_AUX_COMPB +//! - \ref AUXTDC_STOP_ACLK_REF +//! - \ref AUXTDC_STOP_MCU_EV +//! +//! The polarity of the stop event is either rising \ref AUXTDC_STOPPOL_RIS +//! or falling \ref AUXTDC_STOPPOL_FALL. +//! +//! \note The AUX TDC should only be configured when the AUX TDC is in the Idle +//! state. To ensure that software does not lock up, it is recommended to +//! ensure that the AUX TDC is actually in idle when calling \ref AUXTDCConfigSet(). +//! This can be tested using \ref AUXTDCIdle(). +//! +//! \param ui32Base is base address of the AUX TDC. +//! \param ui32StartCondition is AUX TDC a bitwise OR of a start event and polarity. +//! \param ui32StopCondition is AUX TDC a bitwise OR of a stop event and polarity. +//! +//! \return None +//! +//! \sa \ref AUXTDCConfigSet(), \ref AUXTDCIdle() +// +//***************************************************************************** +extern void AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, + uint32_t ui32StopCondition); + +//***************************************************************************** +// +//! \brief Check if the AUX TDC is in idle mode. +//! +//! This function can be used to check whether the AUX TDC internal state +//! machine is in idle mode. This is required before setting the polarity +//! of the start and stop event. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return Returns \c true if state machine is in idle and returns \c false +//! if the state machine is in any other state. +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCIdle(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in the Idle state. + return (((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE) ? true : false); +} + +//***************************************************************************** +// +//! \brief Enable the AUX TDC for a measurement. +//! +//! This function is used for arming the AUX TDC to begin a measurement as +//! soon as the start condition is met. There are two run modes: +//! - \ref AUX_TDC_RUNSYNC will wait for a falling event of the start pulse before +//! starting measurement on next rising edge of start. This guarantees an edge +//! triggered start and is recommended for frequency measurements. If the +//! first falling edge is close to the start command it may be missed, but +//! the TDC shall catch later falling edges and in any case guarantee a +//! measurement start synchronous to the rising edge of the start event. +//! - The \ref AUX_TDC_RUN is asynchronous start and asynchronous stop mode. Using +//! this a TDC measurement may start immediately if start is high and hence it +//! may not give precise edge to edge measurements. This mode is only +//! recommended when start pulse is guaranteed to arrive at least 7 clock +//! periods after command. +//! +//! \note The AUX TDC should be configured and in Idle mode before calling this +//! function. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! \param ui32RunMode is the run mode for the AUX TDC. +//! - \ref AUX_TDC_RUNSYNC : Synchronous run mode. +//! - \ref AUX_TDC_RUN : Asynchronous run mode. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AUXTDCEnable(uint32_t ui32Base, uint32_t ui32RunMode) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + ASSERT((ui32RunMode == AUX_TDC_RUN) || + (ui32RunMode == AUX_TDC_RUNSYNC)); + + // Enable the AUX TDC. + HWREG(ui32Base + AUX_TDC_O_CTL) = ui32RunMode; +} + +//***************************************************************************** +// +//! \brief Force the AUX TDC back to Idle mode. +//! +//! This function will force the AUX TDC in Idle mode. The internal state +//! machine will not go directly to Idle mode, so it is left to the programmer to +//! ensure that the state machine is in Idle mode before doing any new +//! configuration. This can be checked using \ref AUXTDCIdle(). +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return None +//! +//! \sa \ref AUXTDCIdle() +// +//***************************************************************************** +__STATIC_INLINE void +AUXTDCIdleForce(uint32_t ui32Base) +{ + // Check the arguments + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Abort operation of AUX TDC and force into Idle mode. + HWREG(ui32Base + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_ABORT; +} + +//***************************************************************************** +// +//! \brief Check if the AUX TDC is done measuring. +//! +//! This function can be used to check whether the AUX TDC has finished a +//! measurement. The AUX TDC may have completed a measurement for two reasons. +//! Either it finish successfully \ref AUX_TDC_DONE or it failed due to a timeout +//! \ref AUX_TDC_TIMEOUT. If the AUX TDC is still measuring it this function +//! will return \ref AUX_TDC_BUSY. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return Returns the current status of a measurement: +//! - \ref AUX_TDC_DONE : An AUX TDC measurement finished successfully. +//! - \ref AUX_TDC_TIMEOUT : An AUX TDC measurement failed due to timeout. +//! - \ref AUX_TDC_BUSY : An AUX TDC measurement is being performed. +// +//***************************************************************************** +extern uint32_t AUXTDCMeasurementDone(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Get the value of the latest measurement. +//! +//! This function is used for retrieving the value of the latest measurement +//! performed by the AUX TDC. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return Returns the result of the latest measurement. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCMeasurementGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the measurement. + return (HWREG(ui32Base + AUX_TDC_O_RESULT)); +} + +//***************************************************************************** +// +//! \brief Set the saturation limit of the measurement. +//! +//! This function is used to set a saturation limit for the event accumulation +//! register. The saturation limit is defined as a bit width of the +//! accumulation register and therefore increases in power of 2. +//! +//! \param ui32Base is base address of the AUX TDC. +//! \param ui32Limit is the saturation limit. +//! - \ref AUXTDC_SAT_4096 +//! - \ref AUXTDC_SAT_8192 +//! - \ref AUXTDC_SAT_16384 +//! - \ref AUXTDC_SAT_32768 +//! - \ref AUXTDC_SAT_65536 +//! - \ref AUXTDC_SAT_131072 +//! - \ref AUXTDC_SAT_262144 +//! - \ref AUXTDC_SAT_524288 +//! - \ref AUXTDC_SAT_1048576 +//! - \ref AUXTDC_SAT_2097152 +//! - \ref AUXTDC_SAT_4194304 +//! - \ref AUXTDC_SAT_8388608 +//! - \ref AUXTDC_SAT_16777216 (default) +//! +//! \return None +//! +//! \note The actual value of the accumulation register might increase slightly beyond +//! the saturation value before the saturation takes effect. +//! +//! \sa \ref AUXTDCLimitGet() +// +//***************************************************************************** +__STATIC_INLINE void +AUXTDCLimitSet(uint32_t ui32Base, uint32_t ui32Limit) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + ASSERT(ui32Limit < AUXTDC_NUM_SAT_VALS); + + // Set the saturation limit. + HWREG(ui32Base + AUX_TDC_O_SATCFG) = ui32Limit; +} + +//***************************************************************************** +// +//! \brief Get the saturation limit of the measurement. +//! +//! This function is used to retrieve the current saturation for the +//! accumulator register. +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns the saturation limit. +//! - \ref AUXTDC_SAT_4096 +//! - \ref AUXTDC_SAT_8192 +//! - \ref AUXTDC_SAT_16384 +//! - \ref AUXTDC_SAT_32768 +//! - \ref AUXTDC_SAT_65536 +//! - \ref AUXTDC_SAT_131072 +//! - \ref AUXTDC_SAT_262144 +//! - \ref AUXTDC_SAT_524288 +//! - \ref AUXTDC_SAT_1048576 +//! - \ref AUXTDC_SAT_2097152 +//! - \ref AUXTDC_SAT_4194304 +//! - \ref AUXTDC_SAT_8388608 +//! - \ref AUXTDC_SAT_16777216 +//! +//! \sa \ref AUXTDCLimitSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCLimitGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the saturation limit. + return (HWREG(ui32Base + AUX_TDC_O_SATCFG)); +} + +//***************************************************************************** +// +//! \brief Enables the counter if possible. +//! +//! This function can be used to enable the AUX TDC stop/compare event counter. +//! The counter can be used to measure multiple periods of a clock signal. +//! For each stop/compare event the counter will be decremented by one and +//! the measurement will continue running until the value of the counter +//! reaches 0. The current value of the counter can be read using +//! \ref AUXTDCCounterGet(). The reset value of the counter can be set using +//! \ref AUXTDCCounterSet(). +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns \c true if the counter was successfully enabled. If the +//! AUX TDC is not in Idle mode, the counter can not be enabled, and the +//! return value will be \c false. +//! +//! \sa \ref AUXTDCCounterGet(), \ref AUXTDCCounterSet() +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCCounterEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in idle mode. If not in Idle mode, the counter + // will not be enabled. + if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + return false; + } + + // Enable the counter. + HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = AUX_TDC_TRIGCNTCFG_EN; + + // Counter successfully enabled. + return true; +} + +//***************************************************************************** +// +//! \brief Disables the counter if possible. +//! +//! This function can be used to disable the AUX TDC stop/compare event counter. +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns \c true if the counter was successfully disabled. If the +//! AUX TDC is not in Idle mode, the counter can not be disabled, and the +//! return value will be \c false. +//! +//! \sa \ref AUXTDCCounterEnable() for more information on how to use the counter. +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCCounterDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in Idle mode. If not in Idle mode, the counter + // will not be disabled. + if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + return false; + } + + // Disable the counter. + HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = 0; + + // Counter successfully disabled. + return true; +} + +//***************************************************************************** +// +//! \brief Set the reset number of counter compare/stop event to ignore before taking +//! a measurement. +//! +//! This function loads the reset value of the counter with the specified +//! number of events to ignore. A reset in this context means the counter +//! has been disabled and then enabled. +//! +//! \param ui32Base is base address of the AUX TDC. +//! \param ui32Events is the number of compare/stop events to load into the +//! counter. +//! +//! \return Returns \c true if the counter was successfully updated. If the +//! AUX TDC is not in Idle mode, the counter can not be updated, and the +//! return value will be \c false. +//! +//! \sa \ref AUXTDCCounterEnable() +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCCounterSet(uint32_t ui32Base, uint32_t ui32Events) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in idle mode. If not in idle mode, the counter + // will not be disabled. + if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + return false; + } + + // Update the reset counter value. + HWREG(ui32Base + AUX_TDC_O_TRIGCNTLOAD) = ui32Events; + + // Counter successfully updated. + return true; +} + +//***************************************************************************** +// +//! \brief Get the current number of counter compare/stop event to ignore before +//! taking a measurement. +//! +//! This function returns the current value of compare/stop events before +//! a measurement is registered. This value is decremented by one for each +//! registered compare/stop event and will always be less than or equal the +//! reset value of the counter set using \ref AUXTDCCounterSet(). +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns the current value of compare/stop events ignored before a +//! measurement is performed. +//! +//! \sa \ref AUXTDCCounterEnable(). +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCCounterGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the current counter value. + return (HWREG(ui32Base + AUX_TDC_O_TRIGCNT)); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXTDCConfigSet + #undef AUXTDCConfigSet + #define AUXTDCConfigSet ROM_AUXTDCConfigSet + #endif + #ifdef ROM_AUXTDCMeasurementDone + #undef AUXTDCMeasurementDone + #define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_TDC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_timer.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_timer.c new file mode 100644 index 0000000..0055159 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_timer.c @@ -0,0 +1,251 @@ +/****************************************************************************** +* Filename: aux_timer.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the AUX Timer Module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_timer.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXTimerConfigure + #define AUXTimerConfigure NOROM_AUXTimerConfigure + #undef AUXTimerStart + #define AUXTimerStart NOROM_AUXTimerStart + #undef AUXTimerStop + #define AUXTimerStop NOROM_AUXTimerStop + #undef AUXTimerPrescaleSet + #define AUXTimerPrescaleSet NOROM_AUXTimerPrescaleSet + #undef AUXTimerPrescaleGet + #define AUXTimerPrescaleGet NOROM_AUXTimerPrescaleGet +#endif + +//***************************************************************************** +// +// Configure AUX timer +// +//***************************************************************************** +void +AUXTimerConfigure(uint32_t ui32Timer, uint32_t ui32Config) +{ + uint32_t ui32Val; + + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + + // Configure Timer 0. + if(ui32Timer & AUX_TIMER_0) + { + // Stop timer 0. + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = 0; + + // Set mode. + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); + ui32Val &= ~(AUX_TIMER_T0CFG_MODE_M | AUX_TIMER_T0CFG_RELOAD_M); + ui32Val |= (ui32Config & (AUX_TIMER_T0CFG_MODE_M | + AUX_TIMER_T0CFG_RELOAD_M)); + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; + + // If edge counter, set rising/falling edge and tick source. + if(ui32Config & AUX_TIMER_T0CFG_MODE_M) + { + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); + ui32Val &= ~(AUX_TIMER_T0CFG_TICK_SRC_POL_M | + AUX_TIMER_T0CFG_TICK_SRC_M); + + // Set edge polarity. + if(ui32Config & AUX_TIMER_CFG_FALLING_EDGE) + { + ui32Val |= AUX_TIMER_T0CFG_TICK_SRC_POL; + } + + // Set tick source. + ui32Val |= (ui32Config & AUX_TIMER_T0CFG_TICK_SRC_M); + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; + } + } + + // Configure Timer 1. + if(ui32Timer & AUX_TIMER_1) + { + // Stop timer 1. + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = 0; + + // Set mode. + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); + ui32Val &= ~(AUX_TIMER_T1CFG_MODE_M | AUX_TIMER_T1CFG_RELOAD_M); + ui32Val |= ((ui32Config) & (AUX_TIMER_T1CFG_MODE_M | + AUX_TIMER_T1CFG_RELOAD_M)); + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; + + // If edge counter, set rising/falling edge and tick source. + if(ui32Config & AUX_TIMER_T1CFG_MODE) + { + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); + ui32Val &= ~(AUX_TIMER_T1CFG_TICK_SRC_POL_M | + AUX_TIMER_T1CFG_TICK_SRC_M); + + // Set edge polarity. + if(ui32Config & AUX_TIMER_CFG_FALLING_EDGE) + { + ui32Val |= AUX_TIMER_T1CFG_TICK_SRC_POL; + } + + // Set tick source. + ui32Val |= (ui32Config & AUX_TIMER_T1CFG_TICK_SRC_M); + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; + } + } +} + +//***************************************************************************** +// +// Start AUX timer +// +//***************************************************************************** +void +AUXTimerStart(uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || + (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + + if(ui32Timer & AUX_TIMER_0) + { + // Start timer 0. + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = AUX_TIMER_T0CTL_EN; + } + if(ui32Timer & AUX_TIMER_1) + { + // Start timer 1. + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = AUX_TIMER_T1CTL_EN; + } +} + +//***************************************************************************** +// +// Stop AUX timer +// +//***************************************************************************** +void +AUXTimerStop(uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || + (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + + if(ui32Timer & AUX_TIMER_0) + { + // Stop timer 0. + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = 0; + } + if(ui32Timer & AUX_TIMER_1) + { + // Stop timer 1. + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = 0; + } +} + +//***************************************************************************** +// +// Set AUX timer prescale value +// +//***************************************************************************** +void +AUXTimerPrescaleSet(uint32_t ui32Timer, uint32_t ui32PrescaleDiv) +{ + uint32_t ui32Val; + + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + ASSERT(ui32PrescaleDiv <= AUX_TIMER_PRESCALE_DIV_32768); + + if(ui32Timer & AUX_TIMER_0) + { + // Set timer 0 prescale value. + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); + ui32Val &= ~AUX_TIMER_T0CFG_PRE_M; + ui32Val |= ui32PrescaleDiv << AUX_TIMER_T0CFG_PRE_S; + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; + } + if(ui32Timer & AUX_TIMER_1) + { + // Set timer 1 prescale value. + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); + ui32Val &= ~AUX_TIMER_T1CFG_PRE_M; + ui32Val |= ui32PrescaleDiv << AUX_TIMER_T1CFG_PRE_S; + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; + } +} + +//***************************************************************************** +// +// Get AUX timer prescale value +// +//***************************************************************************** +uint32_t +AUXTimerPrescaleGet(uint32_t ui32Timer) +{ + uint32_t ui32Val; + uint32_t ui32PrescaleDiv; + + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); + + ui32Val = (HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG)); + if(ui32Timer & AUX_TIMER_0) + { + // Get timer 0 prescale value. + ui32PrescaleDiv = + (ui32Val & AUX_TIMER_T0CFG_PRE_M) >> AUX_TIMER_T0CFG_PRE_S; + } + else + { + // Get timer 1 prescale value. + ui32PrescaleDiv = + (ui32Val & AUX_TIMER_T1CFG_PRE_M) >> AUX_TIMER_T1CFG_PRE_S; + } + + return(ui32PrescaleDiv); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_timer.h new file mode 100644 index 0000000..b3266dd --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_timer.h @@ -0,0 +1,482 @@ +/****************************************************************************** +* Filename: aux_timer.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Defines and prototypes for the AUX Timer +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxtimer_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_TIMER_H__ +#define __AUX_TIMER_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aux_timer.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXTimerConfigure NOROM_AUXTimerConfigure + #define AUXTimerStart NOROM_AUXTimerStart + #define AUXTimerStop NOROM_AUXTimerStop + #define AUXTimerPrescaleSet NOROM_AUXTimerPrescaleSet + #define AUXTimerPrescaleGet NOROM_AUXTimerPrescaleGet +#endif + +//***************************************************************************** +// +// Values that can be passed to AUXTimerConfigure(). +// +//***************************************************************************** +#define AUX_TIMER_CFG_ONE_SHOT (AUX_TIMER_T0CFG_RELOAD_MAN) // One-shot timer mode +#define AUX_TIMER_CFG_PERIODIC (AUX_TIMER_T0CFG_RELOAD_CONT) // Period timer mode +#define AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_MAN) | (AUX_TIMER_T0CFG_MODE_TICK)) // One-shot timer with edge count +#define AUX_TIMER_CFG_PERIODIC_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_CONT) | (AUX_TIMER_T0CFG_MODE_TICK)) // Periodic timer with edge count +#define AUX_TIMER_CFG_RISING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_RISE) // Count rising edges (used with edge count mode) +#define AUX_TIMER_CFG_FALLING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_FALL) // Count falling edges (used with edge count mode) + +#define AUX_TIMER_CFG_TICK_SRC_RTC_EVENT (AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV) // AON wake-up event +#define AUX_TIMER_CFG_TICK_SRC_CMP_A (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA) // Comparator A +#define AUX_TIMER_CFG_TICK_SRC_CMP_B (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB) // Comparator B +#define AUX_TIMER_CFG_TICK_SRC_TDCDONE (AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE) // TDC Done +#define AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT (AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV) // Timer 0 event +#define AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT (AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV) // Timer 1 event +#define AUX_TIMER_CFG_TICK_SRC_SMPH_RELEASE (AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE) // Semaphore release +#define AUX_TIMER_CFG_TICK_SRC_ADC_DONE (AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE) // ADC done +#define AUX_TIMER_CFG_TICK_SRC_RTC_4KHZ (AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ) +#define AUX_TIMER_CFG_TICK_SRC_OBSMUX0 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0) +#define AUX_TIMER_CFG_TICK_SRC_OBSMUX1 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1) +#define AUX_TIMER_CFG_TICK_SRC_AON_SW (AUX_TIMER_T0CFG_TICK_SRC_AON_SW) +#define AUX_TIMER_CFG_TICK_SRC_AON_PROG_WU (AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU) +#define AUX_TIMER_CFG_TICK_SRC_AIO0 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO0) // AIO_DAT[ 0] +#define AUX_TIMER_CFG_TICK_SRC_AIO1 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO1) // AIO_DAT[ 1] +#define AUX_TIMER_CFG_TICK_SRC_AIO2 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO2) // AIO_DAT[ 2] +#define AUX_TIMER_CFG_TICK_SRC_AIO3 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO3) // AIO_DAT[ 3] +#define AUX_TIMER_CFG_TICK_SRC_AIO4 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO4) // AIO_DAT[ 4] +#define AUX_TIMER_CFG_TICK_SRC_AIO5 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO5) // AIO_DAT[ 5] +#define AUX_TIMER_CFG_TICK_SRC_AIO6 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO6) // AIO_DAT[ 6] +#define AUX_TIMER_CFG_TICK_SRC_AIO7 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO7) // AIO_DAT[ 7] +#define AUX_TIMER_CFG_TICK_SRC_AIO8 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO8) // AIO_DAT[ 8] +#define AUX_TIMER_CFG_TICK_SRC_AIO9 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO9) // AIO_DAT[ 9] +#define AUX_TIMER_CFG_TICK_SRC_AIO10 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO10) // AIO_DAT[10] +#define AUX_TIMER_CFG_TICK_SRC_AIO11 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO11) // AIO_DAT[11] +#define AUX_TIMER_CFG_TICK_SRC_AIO12 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO12) // AIO_DAT[12] +#define AUX_TIMER_CFG_TICK_SRC_AIO13 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO13) // AIO_DAT[13] +#define AUX_TIMER_CFG_TICK_SRC_AIO14 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO14) // AIO_DAT[14] +#define AUX_TIMER_CFG_TICK_SRC_AIO15 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO15) // AIO_DAT[15] +#define AUX_TIMER_CFG_TICK_SRC_ACLK_REF (AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF) // ACLK_REF_i +#define AUX_TIMER_CFG_TICK_SRC_MCU_EVENT (AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT) // MCU event +#define AUX_TIMER_CFG_TICK_SRC_ADC_IRQ (AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ) // DMA done + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ui32Timer +// parameter. +// +//***************************************************************************** +#define AUX_TIMER_0 0x0000FFFF // AUX Timer 0 +#define AUX_TIMER_1 0x00FF0000 // AUX Timer 1 +#define AUX_TIMER_BOTH 0x00FFFFFF // AUX Timer Both 0 and 1 + +//***************************************************************************** +// +// Values that can be passed to AUXTimerPrescaleSet and returned from +// AUXTimerPrescaleGet. +// +//***************************************************************************** +#define AUX_TIMER_PRESCALE_DIV_1 0x00000000 // Prescale division ratio 1 +#define AUX_TIMER_PRESCALE_DIV_2 0x00000001 // Prescale division ratio 2 +#define AUX_TIMER_PRESCALE_DIV_4 0x00000002 // Prescale division ratio 4 +#define AUX_TIMER_PRESCALE_DIV_8 0x00000003 // Prescale division ratio 8 +#define AUX_TIMER_PRESCALE_DIV_16 0x00000004 // Prescale division ratio 16 +#define AUX_TIMER_PRESCALE_DIV_32 0x00000005 // Prescale division ratio 32 +#define AUX_TIMER_PRESCALE_DIV_64 0x00000006 // Prescale division ratio 64 +#define AUX_TIMER_PRESCALE_DIV_128 0x00000007 // Prescale division ratio 128 +#define AUX_TIMER_PRESCALE_DIV_256 0x00000008 // Prescale division ratio 256 +#define AUX_TIMER_PRESCALE_DIV_512 0x00000009 // Prescale division ratio 512 +#define AUX_TIMER_PRESCALE_DIV_1028 0x0000000A // Prescale div. ratio 1028 +#define AUX_TIMER_PRESCALE_DIV_2048 0x0000000B // Prescale div. ratio 2048 +#define AUX_TIMER_PRESCALE_DIV_4096 0x0000000C // Prescale div. ratio 4096 +#define AUX_TIMER_PRESCALE_DIV_8192 0x0000000D // Prescale div. ratio 8192 +#define AUX_TIMER_PRESCALE_DIV_16384 0x0000000E // Prescale div. ratio 16384 +#define AUX_TIMER_PRESCALE_DIV_32768 0x0000000F // Prescale div. ratio 32768 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure AUX timer. +//! +//! This call configures the AUX timer selected by the \c ui32Timer. +//! The timer module is disabled before being configured and is left in the +//! disabled state. +//! +//! The configuration is specified in \c ui32Config as one of the following +//! values: +//! - \ref AUX_TIMER_CFG_ONE_SHOT : One-shot timer. +//! - \ref AUX_TIMER_CFG_PERIODIC : Periodic timer. +//! - \ref AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT : One-shot edge counter. +//! - \ref AUX_TIMER_CFG_PERIODIC_EDGE_COUNT : Periodic edge counter. +//! +//! When configured as timer, the counter is incremented based on the AUX clock +//! after the prescaler. The prescale division ratio is set +//! using \ref AUXTimerPrescaleSet(). +//! +//! When configured as an edge counter the counter is incremented only on edges +//! of the selected event. +//! The polarity of the event is selected by: +//! - \ref AUX_TIMER_CFG_RISING_EDGE : rising edge trigger +//! - \ref AUX_TIMER_CFG_FALLING_EDGE : falling edge trigger +//! +//! The event source is selected as one of the following defines: +//! - \ref AUX_TIMER_CFG_TICK_SRC_RTC_EVENT +//! - \ref AUX_TIMER_CFG_TICK_SRC_CMP_A +//! - \ref AUX_TIMER_CFG_TICK_SRC_CMP_B +//! - \ref AUX_TIMER_CFG_TICK_SRC_TDCDONE +//! - \ref AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT +//! - \ref AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT +//! - \ref AUX_TIMER_CFG_TICK_SRC_SMPH_RELEASE +//! - \ref AUX_TIMER_CFG_TICK_SRC_ADC_DONE +//! - \ref AUX_TIMER_CFG_TICK_SRC_RTC_4KHZ +//! - \ref AUX_TIMER_CFG_TICK_SRC_OBSMUX0 +//! - \ref AUX_TIMER_CFG_TICK_SRC_OBSMUX1 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AON_SW +//! - \ref AUX_TIMER_CFG_TICK_SRC_AON_PROG_WU +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO0 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO1 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO2 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO3 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO4 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO5 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO6 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO7 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO8 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO9 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO10 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO11 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO12 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO13 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO14 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO15 +//! - \ref AUX_TIMER_CFG_TICK_SRC_ACLK_REF +//! - \ref AUX_TIMER_CFG_TICK_SRC_MCU_EVENT +//! - \ref AUX_TIMER_CFG_TICK_SRC_ADC_IRQ +//! +//! The mode, event polarity and event source are configured by setting the +//! \c ui32Config parameter as the bitwise OR of the various settings. +//! Example: (\ref AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT | +//! \ref AUX_TIMER_CFG_RISING_EDGE | +//! \ref AUX_TIMER_CFG_TICK_SRC_RTC_EVENT). +//! +//! \note When used as an edge counter the prescaler should be set to +//! \ref AUX_TIMER_PRESCALE_DIV_1. +//! +//! \note A timer can not trigger itself thus timer 0 can \b not use +//! \ref AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT and timer 1 can \b not use +//! \ref AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT. +//! +//! \param ui32Timer is the timer to configure. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! - \ref AUX_TIMER_BOTH +//! \param ui32Config is the timer configuration. +//! +//! \return None +//! +//! \sa \ref AUXTimerPrescaleSet() +// +//***************************************************************************** +extern void AUXTimerConfigure(uint32_t ui32Timer, uint32_t ui32Config); + +//***************************************************************************** +// +//! \brief Start AUX timer(s). +//! +//! This call starts the selected AUX timer(s). +//! +//! \note The counter will start counting up from zero. +//! +//! \param ui32Timer is the timer to start. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! - \ref AUX_TIMER_BOTH +//! +//! \return None +//! +//! \sa \ref AUXTimerStop() +// +//***************************************************************************** +extern void AUXTimerStart(uint32_t ui32Timer); + +//***************************************************************************** +// +//! \brief Stop AUX timer(s). +//! +//! This call stops the selected AUX timer(s). +//! +//! \param ui32Timer is the timer to stop. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! - \ref AUX_TIMER_BOTH +//! +//! \return None +//! +//! \sa \ref AUXTimerStart() +// +//***************************************************************************** +extern void AUXTimerStop(uint32_t ui32Timer); + +//***************************************************************************** +// +//! \brief Set AUX timer target value. +//! +//! The timer counts from zero to the target value. When target value is +//! reached an event is generated. +//! +//! \param ui32Timer is the timer to set the target value for. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! \param ui32Target is the timer target value. +//! - For \ref AUX_TIMER_0 the target value must be an integer in the range 0..65535 (16 bit). +//! - For \ref AUX_TIMER_1 the target value must be an integer in the range 0..255 (8 bit). +//! +//! \return None +//! +//! \sa \ref AUXTimerTargetValGet() +// +//***************************************************************************** +__STATIC_INLINE void +AUXTimerTargetValSet(uint32_t ui32Timer, uint32_t ui32Target) +{ + uint32_t ui32Addr; + + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); + ASSERT(((ui32Timer & AUX_TIMER_0) && (ui32Target <= 65535)) || + ((ui32Timer & AUX_TIMER_1) && (ui32Target <= 255))); + + ui32Addr = (ui32Timer & AUX_TIMER_0) ? + (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : + (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET); + + HWREG(ui32Addr) = ui32Target; +} + +//***************************************************************************** +// +//! \brief Get AUX timer target value. +//! +//! The timer counts from zero to the target value. When target value is +//! reached an event is generated. This function returns the programmed target +//! value for the specified timer. +//! +//! \param ui32Timer is the timer to get the target value from. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! +//! \return Returns target value for the specified timer +//! +//! \sa \ref AUXTimerTargetValSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTimerTargetValGet(uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); + + return(HWREG((ui32Timer & AUX_TIMER_0) ? + (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : + (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET))); +} + +//***************************************************************************** +// +//! \brief Set AUX timer prescale value. +//! +//! When configured as timer, the counter is incremented based on the AUX clock +//! after the prescaler. +//! +//! \note Setting prescale value is \b not advised when the timer is running. +//! +//! \note When timer is used as an edge counter the prescaler should be +//! set to \ref AUX_TIMER_PRESCALE_DIV_1. +//! +//! \param ui32Timer is the timer to set the prescale on. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! - \ref AUX_TIMER_BOTH +//! \param ui32PrescaleDiv is the prescaler division ratio. +//! - \ref AUX_TIMER_PRESCALE_DIV_1 : Prescale division ratio 1 +//! - \ref AUX_TIMER_PRESCALE_DIV_2 : Prescale division ratio 2 +//! - \ref AUX_TIMER_PRESCALE_DIV_4 : Prescale division ratio 4 +//! - \ref AUX_TIMER_PRESCALE_DIV_16 : Prescale division ratio 16 +//! - \ref AUX_TIMER_PRESCALE_DIV_32 : Prescale division ratio 32 +//! - \ref AUX_TIMER_PRESCALE_DIV_64 : Prescale division ratio 64 +//! - \ref AUX_TIMER_PRESCALE_DIV_128 : Prescale division ratio 128 +//! - \ref AUX_TIMER_PRESCALE_DIV_256 : Prescale division ratio 256 +//! - \ref AUX_TIMER_PRESCALE_DIV_1028 : Prescale division ratio 1028 +//! - \ref AUX_TIMER_PRESCALE_DIV_2048 : Prescale division ratio 2048 +//! - \ref AUX_TIMER_PRESCALE_DIV_4096 : Prescale division ratio 4096 +//! - \ref AUX_TIMER_PRESCALE_DIV_8192 : Prescale division ratio 8192 +//! - \ref AUX_TIMER_PRESCALE_DIV_16384 : Prescale division ratio 16384 +//! - \ref AUX_TIMER_PRESCALE_DIV_32768 : Prescale division ratio 32768 +//! +//! \return None +//! +//! \sa \ref AUXTimerPrescaleGet() +// +//***************************************************************************** +extern void AUXTimerPrescaleSet(uint32_t ui32Timer, uint32_t ui32PrescaleDiv); + +//***************************************************************************** +// +//! \brief Get AUX timer prescale value. +//! +//! When configured as timer, the counter is incremented based on the AUX clock +//! after the prescaler. This call returns the setting of the prescale divide +//! ratio for the specified timer. +//! +//! \param ui32Timer is the timer to get the prescale value from. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! +//! \return Returns the prescaler division ratio as one of the following values: +//! - \ref AUX_TIMER_PRESCALE_DIV_1 : Prescale division ratio 1 +//! - \ref AUX_TIMER_PRESCALE_DIV_2 : Prescale division ratio 2 +//! - \ref AUX_TIMER_PRESCALE_DIV_4 : Prescale division ratio 4 +//! - \ref AUX_TIMER_PRESCALE_DIV_16 : Prescale division ratio 16 +//! - \ref AUX_TIMER_PRESCALE_DIV_32 : Prescale division ratio 32 +//! - \ref AUX_TIMER_PRESCALE_DIV_64 : Prescale division ratio 64 +//! - \ref AUX_TIMER_PRESCALE_DIV_128 : Prescale division ratio 128 +//! - \ref AUX_TIMER_PRESCALE_DIV_256 : Prescale division ratio 256 +//! - \ref AUX_TIMER_PRESCALE_DIV_1028 : Prescale division ratio 1028 +//! - \ref AUX_TIMER_PRESCALE_DIV_2048 : Prescale division ratio 2048 +//! - \ref AUX_TIMER_PRESCALE_DIV_4096 : Prescale division ratio 4096 +//! - \ref AUX_TIMER_PRESCALE_DIV_8192 : Prescale division ratio 8192 +//! - \ref AUX_TIMER_PRESCALE_DIV_16384 : Prescale division ratio 16384 +//! - \ref AUX_TIMER_PRESCALE_DIV_32768 : Prescale division ratio 32768 +//! +//! \sa \ref AUXTimerPrescaleSet() +// +//***************************************************************************** +extern uint32_t AUXTimerPrescaleGet(uint32_t ui32Timer); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXTimerConfigure + #undef AUXTimerConfigure + #define AUXTimerConfigure ROM_AUXTimerConfigure + #endif + #ifdef ROM_AUXTimerStart + #undef AUXTimerStart + #define AUXTimerStart ROM_AUXTimerStart + #endif + #ifdef ROM_AUXTimerStop + #undef AUXTimerStop + #define AUXTimerStop ROM_AUXTimerStop + #endif + #ifdef ROM_AUXTimerPrescaleSet + #undef AUXTimerPrescaleSet + #define AUXTimerPrescaleSet ROM_AUXTimerPrescaleSet + #endif + #ifdef ROM_AUXTimerPrescaleGet + #undef AUXTimerPrescaleGet + #define AUXTimerPrescaleGet ROM_AUXTimerPrescaleGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_TIMER_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_wuc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_wuc.c new file mode 100644 index 0000000..b893e52 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_wuc.c @@ -0,0 +1,283 @@ +/****************************************************************************** +* Filename: aux_wuc.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the AUX Wakeup Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_wuc.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXWUCClockEnable + #define AUXWUCClockEnable NOROM_AUXWUCClockEnable + #undef AUXWUCClockDisable + #define AUXWUCClockDisable NOROM_AUXWUCClockDisable + #undef AUXWUCClockStatus + #define AUXWUCClockStatus NOROM_AUXWUCClockStatus + #undef AUXWUCPowerCtrl + #define AUXWUCPowerCtrl NOROM_AUXWUCPowerCtrl +#endif + +//**************************************************************************** +// +//! Enable clocks for peripherals in the AUX domain +// +//**************************************************************************** +void +AUXWUCClockEnable(uint32_t ui32Clocks) +{ + // Check the arguments. + ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || + (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || + (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || + (ui32Clocks & AUX_WUC_ANAIF_CLOCK) || + (ui32Clocks & AUX_WUC_TIMER_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || + (ui32Clocks & AUX_WUC_SMPH_CLOCK) || + (ui32Clocks & AUX_WUC_TDC_CLOCK) || + (ui32Clocks & AUX_WUC_ADC_CLOCK) || + (ui32Clocks & AUX_WUC_REF_CLOCK)); + + // Enable some of the clocks in the clock register. + HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) |= (ui32Clocks & + AUX_WUC_MODCLK_MASK); + + // Check the rest. + if(ui32Clocks & AUX_WUC_ADC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = + AUX_WUC_ADCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_TDC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) = + AUX_WUC_TDCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_REF_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = + AUX_WUC_REFCLKCTL_REQ; + } +} + +//**************************************************************************** +// +//! Disable clocks for peripherals in the AUX domain +// +//**************************************************************************** +void +AUXWUCClockDisable(uint32_t ui32Clocks) +{ + // Check the arguments. + ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || + (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || + (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || + (ui32Clocks & AUX_WUC_ANAIF_CLOCK) || + (ui32Clocks & AUX_WUC_TIMER_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || + (ui32Clocks & AUX_WUC_SMPH_CLOCK) || + (ui32Clocks & AUX_WUC_TDC_CLOCK) || + (ui32Clocks & AUX_WUC_ADC_CLOCK) || + (ui32Clocks & AUX_WUC_REF_CLOCK)); + + // Disable some of the clocks in the clock register. + HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) &= ~(ui32Clocks & + AUX_WUC_MODCLK_MASK); + + // Check the rest. + if(ui32Clocks & AUX_WUC_ADC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) &= + ~AUX_WUC_ADCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_TDC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) &= + ~AUX_WUC_TDCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_REF_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) &= + ~AUX_WUC_REFCLKCTL_REQ; + } +} + +//**************************************************************************** +// +//! Get the status of a clock +// +//**************************************************************************** +uint32_t +AUXWUCClockStatus(uint32_t ui32Clocks) +{ + bool bClockStatus; + uint32_t ui32ClockRegister; + + // Check the arguments. + ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || + (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || + (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || + (ui32Clocks & AUX_WUC_ANAIF_CLOCK) || + (ui32Clocks & AUX_WUC_TIMER_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || + (ui32Clocks & AUX_WUC_SMPH_CLOCK) || + (ui32Clocks & AUX_WUC_TDC_CLOCK) || + (ui32Clocks & AUX_WUC_ADC_CLOCK) || + (ui32Clocks & AUX_WUC_REF_CLOCK)); + + bClockStatus = true; + + // Read the status registers. + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0); + + // Check all requested clocks + if(ui32Clocks & AUX_WUC_ADI_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AUX_ADI4 ? + true : false); + } + if(ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AUX_DDI0_OSC ? + true : false); + } + if(ui32Clocks & AUX_WUC_TDCIF_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_TDC ? + true : false); + } + if(ui32Clocks & AUX_WUC_ANAIF_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_ANAIF ? + true : false); + } + if(ui32Clocks & AUX_WUC_TIMER_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_TIMER ? + true : false); + } + if(ui32Clocks & AUX_WUC_AIODIO0_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AIODIO0 ? + true : false); + } + if(ui32Clocks & AUX_WUC_AIODIO1_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AIODIO1 ? + true : false); + } + if(ui32Clocks & AUX_WUC_SMPH_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_SMPH ? + true : false); + } + if(ui32Clocks & AUX_WUC_ADC_CLOCK) + { + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL); + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_ADCCLKCTL_ACK ? + true : false); + } + if(ui32Clocks & AUX_WUC_TDC_CLOCK) + { + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL); + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_TDCCLKCTL_ACK ? + true : false); + } + if(ui32Clocks & AUX_WUC_REF_CLOCK) + { + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL); + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_REFCLKCTL_ACK ? + true : false); + } + + // Return the clock status. + return bClockStatus ? AUX_WUC_CLOCK_READY : AUX_WUC_CLOCK_OFF; +} + +//**************************************************************************** +// +//! Control the power to the AUX domain +// +//**************************************************************************** +void +AUXWUCPowerCtrl(uint32_t ui32PowerMode) +{ + // Check the arguments. + ASSERT((ui32PowerMode == AUX_WUC_POWER_OFF) || + (ui32PowerMode == AUX_WUC_POWER_DOWN) || + (ui32PowerMode == AUX_WUC_POWER_ACTIVE)); + + // Power on/off. + if(ui32PowerMode == AUX_WUC_POWER_OFF) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWROFFREQ) = AUX_WUC_PWROFFREQ_REQ; + HWREG(AUX_WUC_BASE + AUX_WUC_O_MCUBUSCTL) = AUX_WUC_MCUBUSCTL_DISCONNECT_REQ; + return; + } + else + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWROFFREQ) = 0x0; + } + + // Power down/active. + if(ui32PowerMode == AUX_WUC_POWER_DOWN) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWRDWNREQ) = AUX_WUC_PWRDWNREQ_REQ; + HWREG(AUX_WUC_BASE + AUX_WUC_O_MCUBUSCTL) = AUX_WUC_MCUBUSCTL_DISCONNECT_REQ; + } + else + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWRDWNREQ) = 0x0; + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_wuc.h new file mode 100644 index 0000000..532d1e9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_wuc.h @@ -0,0 +1,347 @@ +/****************************************************************************** +* Filename: aon_wuc.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Defines and prototypes for the AUX Wakeup Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//**************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxwuc_api +//! @{ +// +//**************************************************************************** + +#ifndef __AUX_WUC_H__ +#define __AUX_WUC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aux_wuc.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXWUCClockEnable NOROM_AUXWUCClockEnable + #define AUXWUCClockDisable NOROM_AUXWUCClockDisable + #define AUXWUCClockStatus NOROM_AUXWUCClockStatus + #define AUXWUCPowerCtrl NOROM_AUXWUCPowerCtrl +#endif + +//***************************************************************************** +// +// Defines for the AUX power control. +// +//***************************************************************************** +#define AUX_WUC_POWER_OFF 0x00000001 +#define AUX_WUC_POWER_DOWN 0x00000002 +#define AUX_WUC_POWER_ACTIVE 0x00000004 + +//***************************************************************************** +// +// Defines for the AUX peripherals clock control. +// +//***************************************************************************** +#define AUX_WUC_SMPH_CLOCK (AUX_WUC_MODCLKEN0_SMPH_EN) +#define AUX_WUC_AIODIO0_CLOCK (AUX_WUC_MODCLKEN0_AIODIO0_EN) +#define AUX_WUC_AIODIO1_CLOCK (AUX_WUC_MODCLKEN0_AIODIO1_EN) +#define AUX_WUC_TIMER_CLOCK (AUX_WUC_MODCLKEN0_TIMER_EN) +#define AUX_WUC_ANAIF_CLOCK (AUX_WUC_MODCLKEN0_ANAIF_EN) +#define AUX_WUC_TDCIF_CLOCK (AUX_WUC_MODCLKEN0_TDC_EN) +#define AUX_WUC_OSCCTRL_CLOCK (AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN) +#define AUX_WUC_ADI_CLOCK (AUX_WUC_MODCLKEN0_AUX_ADI4_EN) +#define AUX_WUC_MODCLK_MASK 0x000000FF + +#define AUX_WUC_TDC_CLOCK 0x00000100 +#define AUX_WUC_ADC_CLOCK 0x00000200 +#define AUX_WUC_REF_CLOCK 0x00000400 + +#define AUX_WUC_CLOCK_OFF 0x00000000 +#define AUX_WUC_CLOCK_UNSTABLE 0x00000001 +#define AUX_WUC_CLOCK_READY 0x00000011 + +#define AUX_WUC_CLOCK_HIFREQ 0x00000000 +#define AUX_WUC_CLOCK_LOFREQ 0x00000001 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//**************************************************************************** +// +//! \brief Enable clocks for peripherals in the AUX domain. +//! +//! Use this function to enable specific clocks in the AUX domain. +//! +//! \param ui32Clocks is a bitmap of clocks to enable. +//! Use a bitwise OR combination of the following values: +//! - \ref AUX_WUC_ADI_CLOCK +//! - \ref AUX_WUC_OSCCTRL_CLOCK +//! - \ref AUX_WUC_TDCIF_CLOCK +//! - \ref AUX_WUC_ANAIF_CLOCK +//! - \ref AUX_WUC_TIMER_CLOCK +//! - \ref AUX_WUC_AIODIO0_CLOCK +//! - \ref AUX_WUC_AIODIO1_CLOCK +//! - \ref AUX_WUC_SMPH_CLOCK +//! - \ref AUX_WUC_TDC_CLOCK +//! - \ref AUX_WUC_ADC_CLOCK +//! - \ref AUX_WUC_REF_CLOCK +//! +//! \return None +//! +//! \sa \ref AUXWUCClockDisable() +// +//**************************************************************************** +extern void AUXWUCClockEnable(uint32_t ui32Clocks); + +//**************************************************************************** +// +//! \brief Disable clocks for peripherals in the AUX domain. +//! +//! Use this function to enable specific clocks in the AUX domain. +//! +//! \param ui32Clocks a bitmap of clocks to disable. +//! Use a bitwise OR combination of the following values: +//! - \ref AUX_WUC_ADI_CLOCK +//! - \ref AUX_WUC_OSCCTRL_CLOCK +//! - \ref AUX_WUC_TDCIF_CLOCK +//! - \ref AUX_WUC_ANAIF_CLOCK +//! - \ref AUX_WUC_TIMER_CLOCK +//! - \ref AUX_WUC_AIODIO0_CLOCK +//! - \ref AUX_WUC_AIODIO1_CLOCK +//! - \ref AUX_WUC_SMPH_CLOCK +//! - \ref AUX_WUC_TDC_CLOCK +//! - \ref AUX_WUC_ADC_CLOCK +//! - \ref AUX_WUC_REF_CLOCK +//! +//! \return None +//! +//! \sa \ref AUXWUCClockEnable() +// +//**************************************************************************** +extern void AUXWUCClockDisable(uint32_t ui32Clocks); + +//**************************************************************************** +// +//! \brief Get the status of a clock. +//! +//! Use this function to poll the status of a specific clock in the AUX +//! domain. +//! +//! \param ui32Clocks is the clock for which to return status. +//! - \ref AUX_WUC_ADI_CLOCK +//! - \ref AUX_WUC_OSCCTRL_CLOCK +//! - \ref AUX_WUC_TDCIF_CLOCK +//! - \ref AUX_WUC_ANAIF_CLOCK +//! - \ref AUX_WUC_TIMER_CLOCK +//! - \ref AUX_WUC_AIODIO0_CLOCK +//! - \ref AUX_WUC_AIODIO1_CLOCK +//! - \ref AUX_WUC_SMPH_CLOCK +//! - \ref AUX_WUC_TDC_CLOCK +//! - \ref AUX_WUC_ADC_CLOCK +//! - \ref AUX_WUC_REF_CLOCK +//! +//! \return Returns the status of the clock as one of two states: +//! - \ref AUX_WUC_CLOCK_OFF +//! - \ref AUX_WUC_CLOCK_READY +// +//**************************************************************************** +extern uint32_t AUXWUCClockStatus(uint32_t ui32Clocks); + +//**************************************************************************** +// +//! \brief Request a high or low frequency clock source. +//! +//! Using this function it is possible to make a request to the System +//! Control to use a high or low frequency clock as clock source for the AUX +//! domain. +//! +//! \note A low frequency clock is always 32 kHz, while a high frequency clock +//! is really a large span of frequencies determined by the clock source (High +//! Frequency or Medium Frequency) and the setting for the clock divider for +//! the AUX domain in the System Control. +//! +//! \param ui32ClockFreq determines the clock source frequency. +//! - \ref AUX_WUC_CLOCK_LOFREQ : Request low frequency clock source for AUX domain. +//! - \ref AUX_WUC_CLOCK_HIFREQ : Request high frequency clock source for AUX domain. +//! +//! \return +// +//**************************************************************************** +__STATIC_INLINE void +AUXWUCClockFreqReq(uint32_t ui32ClockFreq) +{ + // Check the arguments. + ASSERT((ui32ClockFreq == AUX_WUC_CLOCK_HIFREQ) || + (ui32ClockFreq == AUX_WUC_CLOCK_LOFREQ)); + + // Set the request + HWREG(AUX_WUC_BASE + AUX_WUC_O_CLKLFREQ) = ui32ClockFreq; +} + +//**************************************************************************** +// +//! \brief Control the power to the AUX domain. +//! +//! Use this function to set the power mode of the entire AUX domain. +//! +//! \param ui32PowerMode control the desired power mode for the AUX domain. +//! The domain has three different power modes: +//! - \ref AUX_WUC_POWER_OFF +//! - \ref AUX_WUC_POWER_DOWN +//! - \ref AUX_WUC_POWER_ACTIVE +//! +//! \return None +// +//**************************************************************************** +extern void AUXWUCPowerCtrl(uint32_t ui32PowerMode); + +//***************************************************************************** +// +//! \brief Freeze the AUX IOs. +//! +//! To retain the values of the output IOs during a powerdown of the AUX domain +//! all IO latches in the AUX domain should be frozen in their current state. +//! This ensures that software can regain control of the IOs after a powerdown +//! without the IOs first falling back to the default values (i.e. input and +//! pull-up). +//! +//! \return None +//! +//! \sa AUXWUCFreezeDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AUXWUCFreezeEnable(void) +{ + // Set the AUX WUC latches as static. + HWREG(AUX_WUC_BASE + AUX_WUC_O_AUXIOLATCH) = 0x0; +} + +//***************************************************************************** +// +//! \brief Unfreeze the AUX IOs. +//! +//! When restarting the AUX domain after it has entered powerdown mode, the +//! software can regain control of the IOs by setting the IO latches as +//! transparent. +//! +//! \note The IOs should not be unfrozen before software has restored +//! the functionality of the IO. +//! +//! \return None +//! +//! \sa AUXWUCFreezeEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AUXWUCFreezeDisable(void) +{ + // Set the AUX WUC latches as transparent. + HWREG(AUX_WUC_BASE + AUX_WUC_O_AUXIOLATCH) = AUX_WUC_AUXIOLATCH_EN; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXWUCClockEnable + #undef AUXWUCClockEnable + #define AUXWUCClockEnable ROM_AUXWUCClockEnable + #endif + #ifdef ROM_AUXWUCClockDisable + #undef AUXWUCClockDisable + #define AUXWUCClockDisable ROM_AUXWUCClockDisable + #endif + #ifdef ROM_AUXWUCClockStatus + #undef AUXWUCClockStatus + #define AUXWUCClockStatus ROM_AUXWUCClockStatus + #endif + #ifdef ROM_AUXWUCPowerCtrl + #undef AUXWUCPowerCtrl + #define AUXWUCPowerCtrl ROM_AUXWUCPowerCtrl + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_WUC_H__ + +//**************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//**************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/bin/gcc/driverlib.lib b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/bin/gcc/driverlib.lib new file mode 100644 index 0000000..3c94f5a Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/bin/gcc/driverlib.lib differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/bin/iar/driverlib.lib b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/bin/iar/driverlib.lib new file mode 100644 index 0000000..4cd5fc9 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/bin/iar/driverlib.lib differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread.c new file mode 100644 index 0000000..c50f42f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: ccfgread.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: API for reading CCFG. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ccfgread.h" + +// See ccfgread.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread.h new file mode 100644 index 0000000..e3397e9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread.h @@ -0,0 +1,187 @@ +/****************************************************************************** +* Filename: ccfgread.h +* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) +* Revision: 47152 +* +* Description: API for reading CCFG. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup ccfgread_api +//! @{ +// +//***************************************************************************** + +#ifndef __CCFGREAD_H__ +#define __CCFGREAD_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ccfg.h" + +//***************************************************************************** +// +// General constants and defines +// +//***************************************************************************** + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Read DIS_GPRAM from CCFG. +//! +//! \return Value of CCFG field CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM +// +//***************************************************************************** +__STATIC_INLINE bool +CCFGRead_DIS_GPRAM( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) >> + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) ; +} + +//***************************************************************************** +// +//! \brief Read EXT_LF_CLK_DIO from CCFG. +//! +//! \return Value of CCFG field CCFG_EXT_LF_CLK_DIO +// +//***************************************************************************** +__STATIC_INLINE bool +CCFGRead_EXT_LF_CLK_DIO( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ) & + CCFG_EXT_LF_CLK_DIO_M ) >> + CCFG_EXT_LF_CLK_DIO_S ) ; +} + +//***************************************************************************** +// +// Defines the possible values returned from CCFGRead_SCLK_LF_OPTION() +// +//***************************************************************************** +#define CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_RCOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) + +//***************************************************************************** +// +//! \brief Read SCLK_LF_OPTION from CCFG. +//! +//! \return Returns the value of the CCFG field CCFG_MODE_CONF_SCLK_LF_OPTION field. +//! Returns one of the following: +//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF +//! - \ref CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF +//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_LF +//! - \ref CCFGREAD_SCLK_LF_OPTION_RCOSC_LF +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CCFGRead_SCLK_LF_OPTION( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & + CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> + CCFG_MODE_CONF_SCLK_LF_OPTION_S ) ; +} + +//***************************************************************************** +// +// Defines the possible values returned from CCFGRead_XOSC_FREQ() +// +//***************************************************************************** +#define CCFGREAD_XOSC_FREQ_24M ( CCFG_MODE_CONF_XOSC_FREQ_24M >> CCFG_MODE_CONF_XOSC_FREQ_S ) +#define CCFGREAD_XOSC_FREQ_48M ( CCFG_MODE_CONF_XOSC_FREQ_48M >> CCFG_MODE_CONF_XOSC_FREQ_S ) +#define CCFGREAD_XOSC_FREQ_HPOSC ( CCFG_MODE_CONF_XOSC_FREQ_HPOSC >> CCFG_MODE_CONF_XOSC_FREQ_S ) + +//***************************************************************************** +// +//! \brief Read XOSC_FREQ setting CCFG. +//! +//! \return Returns the value of the CCFG_MODE_CONF_XOSC_FREQ field. +//! Returns one of the following: +//! - \ref CCFGREAD_XOSC_FREQ_24M +//! - \ref CCFGREAD_XOSC_FREQ_48M +//! - \ref CCFGREAD_XOSC_FREQ_HPOSC +//! +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CCFGRead_XOSC_FREQ( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & + CCFG_MODE_CONF_XOSC_FREQ_M ) >> + CCFG_MODE_CONF_XOSC_FREQ_S ) ; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_SMPH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread_doc.h new file mode 100644 index 0000000..f3175fb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread_doc.h @@ -0,0 +1,51 @@ +/****************************************************************************** +* Filename: ccfgread_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup ccfgread_api +//! @{ +//! \section sec_ccfgread Introduction +//! +//! The values of customer configuration (CCFG) settings in flash are determined by ccfg.c and typically +//! a user application does not need to read these CCFG values as they are used mainly during ROM boot +//! and device trimming. However, a subset of the CCFG settings need to be read by application +//! code thus DriverLib provides this API to allow easy read access to these specific settings. +//! +//! The remaining settings not accessible through this API can of course be read directly at the CCFG +//! addresses in the flash (starting at CCFG_BASE) using the HWREG macro and the provided defines. +//! CCFG settings are documented as part of the register descriptions in the CPU memory map. +//! +//! \note CCFG settings are located in flash and should be considered read-only from an application +//! point-of-view. +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/chipinfo.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/chipinfo.c new file mode 100644 index 0000000..712d986 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/chipinfo.c @@ -0,0 +1,187 @@ +/****************************************************************************** +* Filename: chipinfo.c +* Revised: 2018-08-17 09:28:06 +0200 (Fri, 17 Aug 2018) +* Revision: 52354 +* +* Description: Collection of functions returning chip information. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "chipinfo.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef ChipInfo_GetSupportedProtocol_BV + #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV + #undef ChipInfo_GetPackageType + #define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType + #undef ChipInfo_GetChipType + #define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType + #undef ChipInfo_GetChipFamily + #define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily + #undef ChipInfo_GetHwRevision + #define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision + #undef ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated + #define ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated +#endif + +//***************************************************************************** +// +// ChipInfo_GetSupportedProtocol_BV() +// +//***************************************************************************** +ProtocolBitVector_t +ChipInfo_GetSupportedProtocol_BV( void ) +{ + return ((ProtocolBitVector_t)( HWREG( PRCM_BASE + 0x1D4 ) & 0x0E )); +} + +//***************************************************************************** +// +// ChipInfo_GetPackageType() +// +//***************************************************************************** +PackageType_t +ChipInfo_GetPackageType( void ) +{ + PackageType_t packType = (PackageType_t)(( + HWREG( FCFG1_BASE + FCFG1_O_USER_ID ) & + FCFG1_USER_ID_PKG_M ) >> + FCFG1_USER_ID_PKG_S ) ; + + if (( packType < PACKAGE_4x4 ) || + ( packType > PACKAGE_7x7_Q1 ) ) + { + packType = PACKAGE_Unknown; + } + + return ( packType ); +} + +//***************************************************************************** +// +// ChipInfo_GetChipFamily() +// +//***************************************************************************** +ChipFamily_t +ChipInfo_GetChipFamily( void ) +{ + uint32_t waferId ; + ChipFamily_t chipFam = FAMILY_Unknown ; + + waferId = (( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) & + FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M ) >> + FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S ) ; + + if ( waferId == 0xB9BE ) { + chipFam = FAMILY_CC13x0 ; + } + + return ( chipFam ); +} + +//***************************************************************************** +// +// ChipInfo_GetChipType() +// +//***************************************************************************** +ChipType_t +ChipInfo_GetChipType( void ) +{ + ChipType_t chipType = CHIP_TYPE_Unknown ; + ChipFamily_t chipFam = ChipInfo_GetChipFamily() ; + uint32_t fcfg1UserId = ChipInfo_GetUserId() ; + uint32_t fcfg1Protocol = (( fcfg1UserId & FCFG1_USER_ID_PROTOCOL_M ) >> + FCFG1_USER_ID_PROTOCOL_S ) ; + + if ( chipFam == FAMILY_CC13x0 ) { + switch ( fcfg1Protocol ) { + case 0x8 : + chipType = CHIP_TYPE_CC1310 ; + break; + case 0xF : + chipType = CHIP_TYPE_CC1350 ; + break; + } + } + + return ( chipType ); +} + +//***************************************************************************** +// +// ChipInfo_GetHwRevision() +// +//***************************************************************************** +HwRevision_t +ChipInfo_GetHwRevision( void ) +{ + HwRevision_t hwRev = HWREV_Unknown ; + uint32_t fcfg1Rev = ChipInfo_GetDeviceIdHwRevCode() ; + uint32_t minorHwRev = ChipInfo_GetMinorHwRev() ; + ChipFamily_t chipFam = ChipInfo_GetChipFamily() ; + + if ( chipFam == FAMILY_CC13x0 ) { + switch ( fcfg1Rev ) { + case 0 : // CC13x0 PG1.0 + hwRev = HWREV_1_0; + break; + case 2 : // CC13x0 PG2.0 (or later) + hwRev = (HwRevision_t)(((uint32_t)HWREV_2_0 ) + minorHwRev ); + break; + } + } + + return ( hwRev ); +} + +//***************************************************************************** +// ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated() +//***************************************************************************** +void +ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated( void ) +{ + if (( ! ChipInfo_ChipFamilyIs_CC13x0() ) || + ( ! ChipInfo_HwRevisionIs_GTEQ_2_0() ) ) + { + while(1) + { + // This driverlib version is for CC13x0 PG2.0 and later. + // Do nothing - stay here forever + } + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/chipinfo.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/chipinfo.h new file mode 100644 index 0000000..38dd113 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/chipinfo.h @@ -0,0 +1,685 @@ +/****************************************************************************** +* Filename: chipinfo.h +* Revised: 2018-06-18 10:26:12 +0200 (Mon, 18 Jun 2018) +* Revision: 52189 +* +* Description: Collection of functions returning chip information. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup ChipInfo +//! @{ +// +//***************************************************************************** + +#ifndef __CHIP_INFO_H__ +#define __CHIP_INFO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_fcfg1.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV + #define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType + #define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType + #define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily + #define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision + #define ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated +#endif + +//***************************************************************************** +// +//! \brief Enumeration identifying the protocols supported. +//! +//! \note +//! This is a bit vector enumeration that indicates supported protocols. +//! E.g: 0x06 means that the chip supports both BLE and IEEE 802.15.4 +// +//***************************************************************************** +typedef enum { + PROTOCOL_Unknown = 0 , //!< None of the known protocols are supported. + PROTOCOLBIT_BLE = 0x02, //!< Bit[1] set, indicates that Bluetooth Low Energy is supported. + PROTOCOLBIT_IEEE_802_15_4 = 0x04, //!< Bit[2] set, indicates that IEEE 802.15.4 is supported. + PROTOCOLBIT_Proprietary = 0x08 //!< Bit[3] set, indicates that proprietary protocols are supported. +} ProtocolBitVector_t; + +//***************************************************************************** +// +//! \brief Returns bit vector showing supported protocols. +//! +//! \return +//! Returns \ref ProtocolBitVector_t which is a bit vector indicating supported protocols. +// +//***************************************************************************** +extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV( void ); + +//***************************************************************************** +// +//! \brief Returns true if the chip supports the BLE protocol. +//! +//! \return +//! Returns \c true if supporting the BLE protocol, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_SupportsBLE( void ) +{ + return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_BLE ) != 0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if the chip supports the IEEE 802.15.4 protocol. +//! +//! \return +//! Returns \c true if supporting the IEEE 802.15.4 protocol, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_SupportsIEEE_802_15_4( void ) +{ + return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_IEEE_802_15_4 ) != 0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if the chip supports proprietary protocols. +//! +//! \return +//! Returns \c true if supporting proprietary protocols, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_SupportsPROPRIETARY( void ) +{ + return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_Proprietary ) != 0 ); +} + +//***************************************************************************** +// +//! \brief Package type enumeration +//! +//! \note +//! Packages available for a specific device are shown in the device datasheet. +// +//***************************************************************************** +typedef enum { + PACKAGE_Unknown = -1, //!< -1 means that current package type is unknown. + PACKAGE_4x4 = 0, //!< 0 means that this is a 4x4 mm QFN (RHB) package. + PACKAGE_5x5 = 1, //!< 1 means that this is a 5x5 mm QFN (RSM) package. + PACKAGE_7x7 = 2, //!< 2 means that this is a 7x7 mm QFN (RGZ) package. + PACKAGE_WAFER = 3, //!< 3 means that this is a wafer sale package (naked die). + PACKAGE_WCSP = 4, //!< 4 means that this is a 2.7x2.7 mm WCSP (YFV). + PACKAGE_7x7_Q1 = 5 //!< 5 means that this is a 7x7 mm QFN package with Wettable Flanks. +} PackageType_t; + +//***************************************************************************** +// +//! \brief Returns package type. +//! +//! \return +//! Returns \ref PackageType_t +// +//***************************************************************************** +extern PackageType_t ChipInfo_GetPackageType( void ); + +//***************************************************************************** +// +//! \brief Returns true if this is a 4x4mm chip. +//! +//! \return +//! Returns \c true if this is a 4x4mm chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs4x4( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_4x4 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a 5x5mm chip. +//! +//! \return +//! Returns \c true if this is a 5x5mm chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs5x5( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_5x5 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a 7x7mm chip. +//! +//! \return +//! Returns \c true if this is a 7x7mm chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs7x7( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_7x7 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a wafer sale chip (naked die). +//! +//! \return +//! Returns \c true if this is a wafer sale chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIsWAFER( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_WAFER ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a WCSP chip (flip chip). +//! +//! \return +//! Returns \c true if this is a WCSP chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIsWCSP( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_WCSP ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a 7x7 Q1 chip. +//! +//! \return +//! Returns \c true if this is a 7x7 Q1 chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs7x7Q1( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_7x7_Q1 ); +} + +//***************************************************************************** +// +//! \brief Returns the internal chip HW revision code. +//! +//! \return +//! Returns the internal chip HW revision code (in range 0-15) +//***************************************************************************** +__STATIC_INLINE uint32_t +ChipInfo_GetDeviceIdHwRevCode( void ) +{ + // Returns HwRevCode = FCFG1_O_ICEPICK_DEVICE_ID[31:28] + return ( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) >> 28 ); +} + +//***************************************************************************** +// +//! \brief Returns minor hardware revision number +//! +//! The minor revision number is set to 0 for the first market released chip +//! and thereafter incremented by 1 for each minor hardware change. +//! +//! \return +//! Returns the minor hardware revision number (in range 0-127) +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ChipInfo_GetMinorHwRev( void ) +{ + uint32_t minorRev = (( HWREG( FCFG1_BASE + FCFG1_O_MISC_CONF_1 ) & + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M ) >> + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S ) ; + + if ( minorRev >= 0x80 ) { + minorRev = 0; + } + + return( minorRev ); +} + +//***************************************************************************** +// +//! \brief Returns the 32 bits USER_ID field +//! +//! How to decode the USER_ID filed is described in the Technical Reference Manual (TRM) +//! +//! \return +//! Returns the 32 bits USER_ID field +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ChipInfo_GetUserId( void ) +{ + return ( HWREG( FCFG1_BASE + FCFG1_O_USER_ID )); +} + +//***************************************************************************** +// +//! \brief Chip type enumeration +// +//***************************************************************************** +typedef enum { + CHIP_TYPE_Unknown = -1, //!< -1 means that the chip type is unknown. + CHIP_TYPE_CC1310 = 0, //!< 0 means that this is a CC1310 chip. + CHIP_TYPE_CC1350 = 1, //!< 1 means that this is a CC1350 chip. + CHIP_TYPE_CC2620 = 2, //!< 2 means that this is a CC2620 chip. + CHIP_TYPE_CC2630 = 3, //!< 3 means that this is a CC2630 chip. + CHIP_TYPE_CC2640 = 4, //!< 4 means that this is a CC2640 chip. + CHIP_TYPE_CC2650 = 5, //!< 5 means that this is a CC2650 chip. + CHIP_TYPE_CUSTOM_0 = 6, //!< 6 means that this is a CUSTOM_0 chip. + CHIP_TYPE_CUSTOM_1 = 7, //!< 7 means that this is a CUSTOM_1 chip. + CHIP_TYPE_CC2640R2 = 8, //!< 8 means that this is a CC2640R2 chip. + CHIP_TYPE_CC2642 = 9, //!< 9 means that this is a CC2642 chip. + CHIP_TYPE_unused = 10,//!< 10 unused value + CHIP_TYPE_CC2652 = 11,//!< 11 means that this is a CC2652 chip. + CHIP_TYPE_CC1312 = 12,//!< 12 means that this is a CC1312 chip. + CHIP_TYPE_CC1352 = 13,//!< 13 means that this is a CC1352 chip. + CHIP_TYPE_CC1352P = 14 //!< 14 means that this is a CC1352P chip. +} ChipType_t; + +//***************************************************************************** +// +//! \brief Returns chip type. +//! +//! \return +//! Returns \ref ChipType_t +// +//***************************************************************************** +extern ChipType_t ChipInfo_GetChipType( void ); + +//***************************************************************************** +// +//! \brief Chip family enumeration +// +//***************************************************************************** +typedef enum { + FAMILY_Unknown = -1, //!< -1 means that the chip's family member is unknown. + FAMILY_CC26x0 = 0, //!< 0 means that the chip is a CC26x0 family member. + FAMILY_CC13x0 = 1, //!< 1 means that the chip is a CC13x0 family member. + FAMILY_CC26x1 = 2, //!< 2 means that the chip is a CC26x1 family member. + FAMILY_CC26x0R2 = 3, //!< 3 means that the chip is a CC26x0R2 family (new ROM contents). + FAMILY_CC13x2_CC26x2 = 4 //!< 4 means that the chip is a CC13x2, CC26x2 family member. +} ChipFamily_t; + +//***************************************************************************** +// +//! \brief Returns chip family member. +//! +//! \return +//! Returns \ref ChipFamily_t +// +//***************************************************************************** +extern ChipFamily_t ChipInfo_GetChipFamily( void ); + +//***************************************************************************** +// +// Options for the define THIS_DRIVERLIB_BUILD +// +//***************************************************************************** +#define DRIVERLIB_BUILD_CC26X0 0 //!< 0 is the driverlib build ID for the cc26x0 driverlib. +#define DRIVERLIB_BUILD_CC13X0 1 //!< 1 is the driverlib build ID for the cc13x0 driverlib. +#define DRIVERLIB_BUILD_CC26X1 2 //!< 2 is the driverlib build ID for the cc26x1 driverlib. +#define DRIVERLIB_BUILD_CC26X0R2 3 //!< 3 is the driverlib build ID for the cc26x0r2 driverlib. +#define DRIVERLIB_BUILD_CC13X2_CC26X2 4 //!< 4 is the driverlib build ID for the cc13x2_cc26x2 driverlib. + +//***************************************************************************** +// +//! \brief Define THIS_DRIVERLIB_BUILD, identifying current driverlib build ID. +//! +//! This driverlib build identifier can be useful for compile time checking/optimization (supporting C preprocessor expressions). +// +//***************************************************************************** +#define THIS_DRIVERLIB_BUILD DRIVERLIB_BUILD_CC13X0 + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC13x0 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC13x0 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC13x0( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC13x0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC26x0 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC26x0 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC26x0( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC26x0R2 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC26x0R2 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC26x0R2( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0R2 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC26x1 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC26x1 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC26x1( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC26x1 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC13x2, CC26x2 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC13x2, CC26x2 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC13x2_CC26x2( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC13x2_CC26x2 ); +} + +//***************************************************************************** +// +//! \brief HW revision enumeration. +// +//***************************************************************************** +typedef enum { + HWREV_Unknown = -1, //!< -1 means that the chip's HW revision is unknown. + HWREV_1_0 = 10, //!< 10 means that the chip's HW revision is 1.0 + HWREV_1_1 = 11, //!< 11 means that the chip's HW revision is 1.1 + HWREV_2_0 = 20, //!< 20 means that the chip's HW revision is 2.0 + HWREV_2_1 = 21, //!< 21 means that the chip's HW revision is 2.1 + HWREV_2_2 = 22, //!< 22 means that the chip's HW revision is 2.2 + HWREV_2_3 = 23, //!< 23 means that the chip's HW revision is 2.3 + HWREV_2_4 = 24 //!< 24 means that the chip's HW revision is 2.4 +} HwRevision_t; + +//***************************************************************************** +// +//! \brief Returns chip HW revision. +//! +//! \return +//! Returns \ref HwRevision_t +// +//***************************************************************************** +extern HwRevision_t ChipInfo_GetHwRevision( void ); + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 1.0. +//! +//! \return +//! Returns \c true if HW revision for this chip is 1.0, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_1_0( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_1_0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.0. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.0, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_2_0( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_2_0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.0 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.0 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_0( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.1. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.1, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_2_1( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_2_1 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.1 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.1 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_1( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_1 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.2. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.2, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_2_2( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_2_2 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.2 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.2 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_2( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_2 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.3 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.3 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_3( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_3 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.4 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.4 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_4( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_4 ); +} + +//***************************************************************************** +// +//! \brief Verifies that current chip is CC13x0 HwRev 2.0 or later and never returns if violated. +//! +//! \return None +// +//***************************************************************************** +extern void ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated( void ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_ChipInfo_GetSupportedProtocol_BV + #undef ChipInfo_GetSupportedProtocol_BV + #define ChipInfo_GetSupportedProtocol_BV ROM_ChipInfo_GetSupportedProtocol_BV + #endif + #ifdef ROM_ChipInfo_GetPackageType + #undef ChipInfo_GetPackageType + #define ChipInfo_GetPackageType ROM_ChipInfo_GetPackageType + #endif + #ifdef ROM_ChipInfo_GetChipType + #undef ChipInfo_GetChipType + #define ChipInfo_GetChipType ROM_ChipInfo_GetChipType + #endif + #ifdef ROM_ChipInfo_GetChipFamily + #undef ChipInfo_GetChipFamily + #define ChipInfo_GetChipFamily ROM_ChipInfo_GetChipFamily + #endif + #ifdef ROM_ChipInfo_GetHwRevision + #undef ChipInfo_GetHwRevision + #define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision + #endif + #ifdef ROM_ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated + #undef ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated + #define ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated ROM_ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CHIP_INFO_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu.c new file mode 100644 index 0000000..293767d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu.c @@ -0,0 +1,396 @@ +/****************************************************************************** +* Filename: cpu.c +* Revised: 2018-05-08 10:04:01 +0200 (Tue, 08 May 2018) +* Revision: 51972 +* +* Description: Instruction wrappers for special CPU instructions needed by +* the drivers. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "cpu.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef CPUcpsid + #define CPUcpsid NOROM_CPUcpsid + #undef CPUprimask + #define CPUprimask NOROM_CPUprimask + #undef CPUcpsie + #define CPUcpsie NOROM_CPUcpsie + #undef CPUbasepriGet + #define CPUbasepriGet NOROM_CPUbasepriGet + #undef CPUdelay + #define CPUdelay NOROM_CPUdelay +#endif + +//***************************************************************************** +// +// Disable all external interrupts +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUcpsid(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + mrs r0, PRIMASK; + cpsid i; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUcpsid(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK and disable interrupts + __asm volatile (" mrs %0, PRIMASK\n" + " cpsid i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif + +//***************************************************************************** +// +// Get the current interrupt state +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUprimask(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUprimask(void) +{ + // Read PRIMASK. + __asm(" mrs r0, PRIMASK\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUprimask(void) +{ + // Read PRIMASK. + mrs r0, PRIMASK; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUprimask(void) +{ + // Read PRIMASK. + __asm(" mrs r0, PRIMASK\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUprimask(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK + __asm volatile (" mrs %0, PRIMASK\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif + +//***************************************************************************** +// +// Enable all external interrupts +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUcpsie(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + mrs r0, PRIMASK; + cpsie i; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUcpsie(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK and enable interrupts. + __asm volatile (" mrs %0, PRIMASK\n" + " cpsie i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif + +//***************************************************************************** +// +// Get the interrupt priority disable level +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUbasepriGet(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUbasepriGet(void) +{ + // Read BASEPRI. + __asm(" mrs r0, BASEPRI\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUbasepriGet(void) +{ + // Read BASEPRI. + mrs r0, BASEPRI; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUbasepriGet(void) +{ + // Read BASEPRI. + __asm(" mrs r0, BASEPRI\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUbasepriGet(void) +{ + uint32_t ui32Ret; + + // Read BASEPRI. + __asm volatile (" mrs %0, BASEPRI\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif +//***************************************************************************** +// +// Provide a small delay +// +//***************************************************************************** +#if defined(DOXYGEN) +void +CPUdelay(uint32_t ui32Count) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +void +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times + __asm("CPUdelay:\n" + " subs r0, #1\n" + " bne.n CPUdelay\n" + " bx lr"); +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm void +CPUdelay(uint32_t ui32Count) +{ + // Delay the specified number of times (3 cycles pr. loop) +CPUdel + subs r0, #1; + bne CPUdel; + bx lr; +} +#elif defined(__TI_COMPILER_VERSION__) + // For CCS implement this function in pure assembly. This prevents the TI + // compiler from doing funny things with the optimizer. + + // Loop the specified number of times +__asm(" .sect \".text:NOROM_CPUdelay\"\n" + " .clink\n" + " .thumbfunc NOROM_CPUdelay\n" + " .thumb\n" + " .global NOROM_CPUdelay\n" + "NOROM_CPUdelay:\n" + " subs r0, #1\n" + " bne.n NOROM_CPUdelay\n" + " bx lr\n"); +#else +// GCC +void __attribute__((naked)) +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times + __asm volatile ("%=: subs %0, #1\n" + " bne %=b\n" + " bx lr\n" + : /* No output */ + : "r" (ui32Count) + ); +} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu.h new file mode 100644 index 0000000..e2b0561 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu.h @@ -0,0 +1,466 @@ +/****************************************************************************** +* Filename: cpu.h +* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) +* Revision: 52111 +* +* Description: Defines and prototypes for the CPU instruction wrapper +* functions. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup cpu_api +//! @{ +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_cpu_scs.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define CPUcpsid NOROM_CPUcpsid + #define CPUprimask NOROM_CPUprimask + #define CPUcpsie NOROM_CPUcpsie + #define CPUbasepriGet NOROM_CPUbasepriGet + #define CPUdelay NOROM_CPUdelay +#endif + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Disable all external interrupts. +//! +//! Use this function to disable all system interrupts. This function is +//! implemented as a wrapper function for the CPSID instruction. +//! +//! \return Returns the state of \b PRIMASK on entry +// +//***************************************************************************** +extern uint32_t CPUcpsid(void); + +//***************************************************************************** +// +//! \brief Get the current interrupt state. +//! +//! Use this function to retrieve the current state of the interrupts. This +//! function is implemented as a wrapper function returning the state of +//! PRIMASK. +//! +//! \return Returns the state of the \b PRIMASK (indicating whether interrupts +//! are enabled or disabled). +// +//***************************************************************************** +extern uint32_t CPUprimask(void); + +//***************************************************************************** +// +//! \brief Enable all external interrupts. +//! +//! Use this function to enable all system interrupts. This function is +//! implemented as a wrapper function for the CPSIE instruction. +//! +//! \return Returns the state of \b PRIMASK on entry. +// +//***************************************************************************** +extern uint32_t CPUcpsie(void); + +//***************************************************************************** +// +//! \brief Get the interrupt priority disable level. +//! +//! Use this function to get the level of priority that will disable +//! interrupts with a lower priority level. +//! +//! \return Returns the value of the \b BASEPRI register. +// +//***************************************************************************** +extern uint32_t CPUbasepriGet(void); + +//***************************************************************************** +// +//! \brief Provide a small non-zero delay using a simple loop counter. +//! +//! This function provides means for generating a constant length delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! \note It is not recommended using this function for long delays. +//! +//! Notice that interrupts can affect the delay if not manually disabled in advance. +//! +//! The delay depends on where code resides and the path for code fetching: +//! - Code in flash, cache enabled, prefetch enabled : 4 cycles per loop (Default) +//! - Code in flash, cache enabled, prefetch disabled : 5 cycles per loop +//! - Code in flash, cache disabled : 7 cycles per loop +//! - Code in SRAM : 6 cycles per loop +//! - Code in GPRAM : 3 cycles per loop +//! +//! \note If using an RTOS, consider using RTOS provided delay functions because +//! these will not block task scheduling and will potentially save power. +//! +//! Calculate delay count based on the wanted delay in microseconds (us): +//! - ui32Count = [delay in us] * [CPU clock in MHz] / [cycles per loop] +//! +//! Example: 250 us delay with code in flash and with cache and prefetch enabled: +//! - ui32Count = 250 * 48 / 4 = 3000 +//! +//! \param ui32Count is the number of delay loop iterations to perform. Number must be greater than zero. +//! +//! \return None +// +//***************************************************************************** +extern void CPUdelay(uint32_t ui32Count); + +//***************************************************************************** +// +//! \brief Wait for interrupt. +//! +//! Use this function to let the System CPU wait for the next interrupt. This +//! function is implemented as a wrapper function for the WFI instruction. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUwfi(void) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUwfi(void) +{ + // Wait for the next interrupt. + __asm(" wfi\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUwfi(void) +{ + // Wait for the next interrupt. + wfi; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUwfi(void) +{ + // Wait for the next interrupt. + __asm(" wfi\n"); +} +#else +__STATIC_INLINE void __attribute__((always_inline)) +CPUwfi(void) +{ + // Wait for the next interrupt. + __asm volatile (" wfi\n"); +} +#endif + +//***************************************************************************** +// +//! \brief Wait for event. +//! +//! Use this function to let the System CPU wait for the next event. This +//! function is implemented as a wrapper function for the WFE instruction. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUwfe(void) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUwfe(void) +{ + // Wait for the next event. + __asm(" wfe\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUwfe(void) +{ + // Wait for the next event. + wfe; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUwfe(void) +{ + // Wait for the next event. + __asm(" wfe\n"); +} +#else +__STATIC_INLINE void __attribute__((always_inline)) +CPUwfe(void) +{ + // Wait for the next event. + __asm volatile (" wfe\n"); +} +#endif + +//***************************************************************************** +// +//! \brief Send event. +//! +//! Use this function to let the System CPU send an event. This function is +//! implemented as a wrapper function for the SEV instruction. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUsev(void) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUsev(void) +{ + // Send event. + __asm(" sev\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUsev(void) +{ + // Send event. + sev; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUsev(void) +{ + // Send event. + __asm(" sev\n"); +} +#else +__STATIC_INLINE void __attribute__((always_inline)) +CPUsev(void) +{ + // Send event. + __asm volatile (" sev\n"); +} +#endif + + +//***************************************************************************** +// +//! \brief Update the interrupt priority disable level. +//! +//! Use this function to change the level of priority that will disable +//! interrupts with a lower priority level. +//! +//! \param ui32NewBasepri is the new basis priority level to set. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + __asm(" msr BASEPRI, r0\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + msr BASEPRI, r0; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + __asm(" msr BASEPRI, r0\n"); +} +#else +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wattributes" +__STATIC_INLINE void __attribute__ ((naked)) +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + __asm volatile (" msr BASEPRI, %0\n" + " bx lr\n" + : /* No output */ + : "r" (ui32NewBasepri) + ); +} +#pragma GCC diagnostic pop +#endif + +//***************************************************************************** +// +//! \brief Disable CPU write buffering (recommended for debug purpose only). +//! +//! This function helps debugging "bus fault crashes". +//! Disables write buffer use during default memory map accesses. +//! +//! This causes all bus faults to be precise bus faults but decreases the +//! performance of the processor because the stores to memory have to complete +//! before the next instruction can be executed. +//! +//! \return None +//! +//! \sa \ref CPU_WriteBufferEnable() +// +//***************************************************************************** +__STATIC_INLINE void +CPU_WriteBufferDisable( void ) +{ + HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1; +} + +//***************************************************************************** +// +//! \brief Enable CPU write buffering (default setting). +//! +//! Re-enables write buffer during default memory map accesses if +//! \ref CPU_WriteBufferDisable() has been used for bus fault debugging. +//! +//! \return None +//! +//! \sa \ref CPU_WriteBufferDisable() +// +//***************************************************************************** +__STATIC_INLINE void +CPU_WriteBufferEnable( void ) +{ + HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_CPUcpsid + #undef CPUcpsid + #define CPUcpsid ROM_CPUcpsid + #endif + #ifdef ROM_CPUprimask + #undef CPUprimask + #define CPUprimask ROM_CPUprimask + #endif + #ifdef ROM_CPUcpsie + #undef CPUcpsie + #define CPUcpsie ROM_CPUcpsie + #endif + #ifdef ROM_CPUbasepriGet + #undef CPUbasepriGet + #define CPUbasepriGet ROM_CPUbasepriGet + #endif + #ifdef ROM_CPUdelay + #undef CPUdelay + #define CPUdelay ROM_CPUdelay + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CPU_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu_doc.h new file mode 100644 index 0000000..7f17aa3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu_doc.h @@ -0,0 +1,44 @@ +/****************************************************************************** +* Filename: cpu_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup cpu_api +//! @{ +//! \section sec_cpu Introduction +//! +//! The CPU API provides a set of functions performing very low-level control of the system CPU. +//! All functions in this API are written in assembler in order to either access special registers +//! or avoid any compiler optimizations. Each function exists in several compiler specific versions: +//! One version for each supported compiler. +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/crypto.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/crypto.c new file mode 100644 index 0000000..d6617a2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/crypto.c @@ -0,0 +1,943 @@ +/****************************************************************************** +* Filename: crypto.c +* Revised: 2017-12-20 16:40:03 +0100 (Wed, 20 Dec 2017) +* Revision: 50869 +* +* Description: Driver for the Crypto module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "crypto.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef CRYPTOAesLoadKey + #define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey + #undef CRYPTOAesCbc + #define CRYPTOAesCbc NOROM_CRYPTOAesCbc + #undef CRYPTOAesCbcStatus + #define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus + #undef CRYPTOAesEcb + #define CRYPTOAesEcb NOROM_CRYPTOAesEcb + #undef CRYPTOAesEcbStatus + #define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus + #undef CRYPTOCcmAuthEncrypt + #define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt + #undef CRYPTOCcmAuthEncryptStatus + #define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus + #undef CRYPTOCcmAuthEncryptResultGet + #define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet + #undef CRYPTOCcmInvAuthDecrypt + #define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt + #undef CRYPTOCcmInvAuthDecryptStatus + #define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus + #undef CRYPTOCcmInvAuthDecryptResultGet + #define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet + #undef CRYPTODmaEnable + #define CRYPTODmaEnable NOROM_CRYPTODmaEnable + #undef CRYPTODmaDisable + #define CRYPTODmaDisable NOROM_CRYPTODmaDisable +#endif + +//***************************************************************************** +// +// Write the key into the Key Ram. +// +//***************************************************************************** +uint32_t +CRYPTOAesLoadKey(uint32_t *pui32AesKey, + uint32_t ui32KeyLocation) +{ + uint32_t returnStatus = AES_KEYSTORE_READ_ERROR; + + // Check the arguments. + ASSERT((ui32KeyLocation == CRYPTO_KEY_AREA_0) | + (ui32KeyLocation == CRYPTO_KEY_AREA_1) | + (ui32KeyLocation == CRYPTO_KEY_AREA_2) | + (ui32KeyLocation == CRYPTO_KEY_AREA_3) | + (ui32KeyLocation == CRYPTO_KEY_AREA_4) | + (ui32KeyLocation == CRYPTO_KEY_AREA_5) | + (ui32KeyLocation == CRYPTO_KEY_AREA_6) | + (ui32KeyLocation == CRYPTO_KEY_AREA_7)); + + // Disable the external interrupt to stop the interrupt form propagating + // from the module to the System CPU. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Clear any previously written key at the keyLocation + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << ui32KeyLocation); + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | + CRYPTO_IRQEN_RESULT_AVAIL; + + // Configure master control module. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_ALGSEL, CRYPTO_ALGSEL_KEY_STORE_BITN) = 1; + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Configure key store module for 128 bit operation. + // Do not write to the register if the correct key size is already set. + // Writing to this register causes all current keys to be invalidated. + if (HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) != KEY_STORE_SIZE_128) { + HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = KEY_STORE_SIZE_128; + } + + // Enable keys to write (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = (0x00000001 << ui32KeyLocation); + + // Enable Crypto DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the key in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32AesKey; + + // Total key length in bytes (e.g. 16 for 1 x 128-bit key). + // Writing the length of the key enables the DMA operation. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = KEY_BLENGTH; + + // Wait for the DMA operation to complete. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & + (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | + CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M | + CRYPTO_IRQSTAT_DMA_IN_DONE | + CRYPTO_IRQSTAT_RESULT_AVAIL_M))); + + // Check for errors in DMA and key store. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & + (CRYPTO_IRQSTAT_DMA_BUS_ERR | + CRYPTO_IRQSTAT_KEY_ST_WR_ERR)) == 0) + { + // Acknowledge/clear the interrupt and disable the master control. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + + // Check key status, return success if key valid. + if(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (0x00000001 << ui32KeyLocation)) + { + returnStatus = AES_SUCCESS; + } + } + + // Return status. + return returnStatus; +} + +//***************************************************************************** +// +// Start an AES-CBC operation (encryption or decryption). +// +//***************************************************************************** +uint32_t +CRYPTOAesCbc(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32MsgLength, + uint32_t *pui32Nonce, uint32_t ui32KeyLocation, + bool bEncrypt, bool bIntEnable) +{ + uint32_t ui32CtrlVal; + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; + + // Clear any outstanding interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Wait for interrupt lines from module to be cleared + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); + + // If using interrupts clear any pending interrupts and enable interrupts + // for the Crypto module. + if(bIntEnable) + { + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + // Configure Master Control module. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; + + //Wait until key is loaded to the AES module. + do + { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); + + // Check for Key store Read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) + { + return (AES_KEYSTORE_READ_ERROR); + } + + // Write initialization vector. + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = pui32Nonce[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = pui32Nonce[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = pui32Nonce[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = pui32Nonce[3]; + + // Configure AES engine for AES-CBC with 128-bit key size. + ui32CtrlVal = (CRYPTO_AESCTL_SAVE_CONTEXT | CRYPTO_AESCTL_CBC); + if(bEncrypt) + { + ui32CtrlVal |= CRYPTO_AES128_ENCRYPT; + } + else + { + ui32CtrlVal |= CRYPTO_AES128_DECRYPT; + } + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; + + // Write the length of the crypto block (plain text). + // Low and high part (high part is assumed to be always 0). + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32MsgLength; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; + HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = 0; + + // Enable Crypto DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the input data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn; + + // Input data length in bytes, equal to the message. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32MsgLength; + + // Enable Crypto DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Set up the address and length of the output data. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut; + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32MsgLength; + + // Return success + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Check the result of an AES CBC operation +// +//***************************************************************************** +uint32_t +CRYPTOAesCbcStatus(void) +{ + return(CRYPTOAesEcbStatus()); +} + +//***************************************************************************** +// +// Start an AES-ECB operation (encryption or decryption). +// +//***************************************************************************** +uint32_t +CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, + uint32_t ui32KeyLocation, bool bEncrypt, + bool bIntEnable) +{ + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; + + // Clear any outstanding interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Wait for interrupt lines from module to be cleared + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); + + // If using interrupts clear any pending interrupts and enable interrupts + // for the Crypto module. + if(bIntEnable) + { + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + // Configure Master Control module. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; + + //Wait until key is loaded to the AES module. + do + { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); + + // Check for Key store Read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) + { + return (AES_KEYSTORE_READ_ERROR); + } + + // Configure AES engine (program AES-ECB-128 encryption and no + // initialization vector - IV). + if(bEncrypt) + { + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_ENCRYPT; + } + else + { + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_DECRYPT; + } + + // Write the length of the data. + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = AES_ECB_LENGTH; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; + + // Enable Crypto DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the input data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn; + + // Input data length in bytes, equal to the message. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = AES_ECB_LENGTH; + + // Enable Crypto DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Set up the address and length of the output data. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut; + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = AES_ECB_LENGTH; + + // Return success + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Check the result of an AES ECB operation +// +//***************************************************************************** +uint32_t +CRYPTOAesEcbStatus(void) +{ + uint32_t ui32Status; + + // Get the current DMA status. + ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); + + // Check if DMA is still busy. + if(ui32Status & CRYPTO_DMA_BSY) + { + return (AES_DMA_BSY); + } + + // Check the status of the DMA operation - return error if not success. + if(ui32Status & CRYPTO_DMA_BUS_ERROR) + { + return (AES_DMA_BUS_ERROR); + } + + // Operation successful - disable interrupt and return success. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + return (AES_SUCCESS); +} + +//***************************************************************************** +// +// Start CCM operation +// +//***************************************************************************** +uint32_t +CRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength , + uint32_t *pui32Nonce, uint32_t *pui32PlainText, + uint32_t ui32PlainTextLength, uint32_t *pui32Header, + uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, + uint32_t ui32FieldLength, bool bIntEnable) +{ + uint32_t ui32CtrlVal; + uint32_t i; + uint32_t *pui32CipherText; + union { + uint32_t w[4]; + uint8_t b[16]; + } ui8InitVec; + + // Input address for the encryption engine is the same as the output. + pui32CipherText = pui32PlainText; + + // Disable global interrupt, enable local interrupt and clear any pending + // interrupts. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | + CRYPTO_IRQEN_RESULT_AVAIL; + + // Configure master control module for AES operation. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; + + // Wait until key is loaded to the AES module. + do + { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); + + // Check for Key store Read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) + { + return (AES_KEYSTORE_READ_ERROR); + } + + // Prepare the initialization vector (IV), + // Length of Nonce l(n) = 15 - ui32FieldLength. + ui8InitVec.b[0] = ui32FieldLength - 1; + for(i = 0; i < 12; i++) + { + ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i]; + } + if(ui32FieldLength == 2) + { + ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12]; + } + else + { + ui8InitVec.b[13] = 0; + } + ui8InitVec.b[14] = 0; + ui8InitVec.b[15] = 0; + + // Write initialization vector. + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3]; + + // Configure AES engine. + ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if ( ui32AuthLength >= 2 ) { + ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); + } + ui32CtrlVal |= CRYPTO_AESCTL_CCM; + ui32CtrlVal |= CRYPTO_AESCTL_CTR; + ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT; + ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S); + ui32CtrlVal |= (1 << CRYPTO_AESCTL_DIR_S); + ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S); + + // Write the configuration for 128 bit AES-CCM. + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; + + // Write the length of the crypto block (plain text). + // Low and high part (high part is assumed to be always 0). + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32PlainTextLength; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; + + // Write the length of the header field. + // Also called AAD - Additional Authentication Data. + HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength; + + // Check if any header information (AAD). + // If so configure the DMA controller to fetch the header. + if(ui32HeaderLength != 0) + { + // Enable DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Register the base address of the header (AAD). + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header; + + // Header length in bytes (may be non-block size aligned). + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength; + + // Wait for completion of the header data transfer, DMA_IN_DONE. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE)); + + // Check for DMA errors. + if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR) + { + return AES_DMA_BUS_ERROR; + } + } + + // Clear interrupt status. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Wait for interrupt lines from module to be cleared + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); + + // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only + // want interrupt to trigger once RESULT_AVAIL occurs. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE; + + + // Is using interrupts enable globally. + if(bIntEnable) + { + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + // Enable interrupts locally. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; + + // Perform encryption if requested. + if(bEncrypt) + { + // Enable DMA channel 0 + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = + (uint32_t)pui32PlainText; + + // Enable DMA channel 1 + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = + (uint32_t)pui32CipherText; + + // Payload data length in bytes, equal to the plaintext length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32PlainTextLength; + // Output data length in bytes, equal to the plaintext length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32PlainTextLength; + } + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Check the result of an AES CCM operation. +// +//***************************************************************************** +uint32_t +CRYPTOCcmAuthEncryptStatus(void) +{ + uint32_t ui32Status; + + // Get the current DMA status. + ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); + + // Check if DMA is still busy. + if(ui32Status & CRYPTO_DMA_BSY) + { + return (AES_DMA_BSY); + } + + // Check the status of the DMA operation - return error if not success. + if(ui32Status & CRYPTO_DMA_BUS_ERROR) + { + return (AES_DMA_BUS_ERROR); + } + + // Operation successful - disable interrupt and return success. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + return (AES_SUCCESS); +} + +//***************************************************************************** +// +// Get the result of an AES-CCM operation +// +//***************************************************************************** +uint32_t +CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, uint32_t *pui32CcmTag) +{ + uint32_t volatile ui32Tag[4]; + uint32_t ui32Idx; + + // Result has already been copied to the output buffer by DMA + // Disable master control. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + + // Read tag - wait for the context ready bit. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & + CRYPTO_AESCTL_SAVED_CONTEXT_RDY)); + + // Read the Tag registers. + ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); + ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); + ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); + ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); + + for(ui32Idx = 0; ui32Idx < ui32TagLength ; ui32Idx++) + { + *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx); + } + + // Operation successful - clear interrupt status. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Start a CCM Decryption and Inverse Authentication operation. +// +//***************************************************************************** +uint32_t +CRYPTOCcmInvAuthDecrypt(bool bDecrypt, uint32_t ui32AuthLength, + uint32_t *pui32Nonce, uint32_t *pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t *pui32Header, uint32_t ui32HeaderLength, + uint32_t ui32KeyLocation, + uint32_t ui32FieldLength, bool bIntEnable) +{ + uint32_t ui32CtrlVal; + uint32_t i; + uint32_t *pui32PlainText; + uint32_t ui32CryptoBlockLength; + union { + uint32_t w[4]; + uint8_t b[16]; + } ui8InitVec; + + // Input address for the encryption engine is the same as the output. + pui32PlainText = pui32CipherText; + + // Disable global interrupt, enable local interrupt and clear any pending. + // interrupts. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | + CRYPTO_IRQEN_RESULT_AVAIL; + + // Configure master control module for AES operation. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; + + // Wait until key is loaded to the AES module. + do + { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); + + // Check for Key store Read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) + { + return (AES_KEYSTORE_READ_ERROR); + } + + // Prepare the initialization vector (IV), + // Length of Nonce l(n) = 15 - ui32FieldLength. + ui8InitVec.b[0] = ui32FieldLength - 1; + for(i = 0; i < 12; i++) + { + ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i]; + } + if(ui32FieldLength == 2) + { + ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12]; + } + else + { + ui8InitVec.b[13] = 0; + } + ui8InitVec.b[14] = 0; + ui8InitVec.b[15] = 0; + + // Write initialization vector. + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3]; + + // Configure AES engine + ui32CryptoBlockLength = ui32CipherTextLength - ui32AuthLength; + ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if ( ui32AuthLength >= 2 ) { + ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); + } + ui32CtrlVal |= CRYPTO_AESCTL_CCM; + ui32CtrlVal |= CRYPTO_AESCTL_CTR; + ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT; + ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S); + ui32CtrlVal |= (0 << CRYPTO_AESCTL_DIR_S); + ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S); + + // Write the configuration for 128 bit AES-CCM. + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; + + // Write the length of the crypto block (plain text). + // Low and high part (high part is assumed to be always 0). + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32CryptoBlockLength; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; + + // Write the length of the header field. + // Also called AAD - Additional Authentication Data. + HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength; + + // Check if any header information (AAD). + // If so configure the DMA controller to fetch the header. + if(ui32HeaderLength != 0) + { + // Enable DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Register the base address of the header (AAD). + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header; + + // Header length in bytes (may be non-block size aligned). + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength; + + // Wait for completion of the header data transfer, DMA_IN_DONE. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE)); + + // Check for DMA errors. + if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR) + { + return AES_DMA_BUS_ERROR; + } + } + + // Clear interrupt status. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Wait for interrupt lines from module to be cleared + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); + + // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only + // want interrupt to trigger once RESULT_AVAIL occurs. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE; + + // Is using interrupts - clear and enable globally. + if(bIntEnable) + { + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; + + // Perform decryption if requested. + if(bDecrypt) + { + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = + (uint32_t)pui32CipherText; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32CryptoBlockLength; + + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = + (uint32_t)pui32PlainText; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32CryptoBlockLength; + } + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Checks CCM decrypt and Inverse Authentication result. +// +//***************************************************************************** +uint32_t +CRYPTOCcmInvAuthDecryptStatus(void) +{ + uint32_t ui32Status; + + // Get the current DMA status. + ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); + + // Check if DMA is still busy. + if(ui32Status & CRYPTO_DMA_BSY) + { + return (AES_DMA_BSY); + } + + // Check the status of the DMA operation - return error if not success. + if(ui32Status & CRYPTO_DMA_BUS_ERROR) + { + return (AES_DMA_BUS_ERROR); + } + + // Operation successful - disable interrupt and return success + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + return (AES_SUCCESS); +} + +//***************************************************************************** +// +// Get the result of the CCM operation. +// +//***************************************************************************** +uint32_t +CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength, + uint32_t *pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t *pui32CcmTag) +{ + uint32_t volatile ui32Tag[4]; + uint32_t ui32TagIndex; + uint32_t i; + uint32_t ui32Idx; + + ui32TagIndex = ui32CipherTextLength - ui32AuthLength; + + // Result has already been copied to the output buffer by DMA + // Disable master control. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + + // Read tag - wait for the context ready bit. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & + CRYPTO_AESCTL_SAVED_CONTEXT_RDY)); + + // Read the Tag registers. + ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); + ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); + ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); + ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); + + for(ui32Idx = 0; ui32Idx < ui32AuthLength ; ui32Idx++) + { + *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx); + } + + // Operation successful - clear interrupt status. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Verify the Tag. + for(i = 0; i < ui32AuthLength; i++) + { + if(*((uint8_t *)pui32CcmTag + i) != + (*((uint8_t *)pui32CipherText + ui32TagIndex + i))) + { + return CCM_AUTHENTICATION_FAILED; + } + } + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Enable Crypto DMA operation +// +//***************************************************************************** +void +CRYPTODmaEnable(uint32_t ui32Channels) +{ + // Check the arguments. + ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) | + (ui32Channels & CRYPTO_DMA_CHAN1)); + + // Enable the selected channels, + if(ui32Channels & CRYPTO_DMA_CHAN0) + { + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + } + if(ui32Channels & CRYPTO_DMA_CHAN1) + { + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + } +} + +//***************************************************************************** +// +// Disable Crypto DMA operation +// +//***************************************************************************** +void +CRYPTODmaDisable(uint32_t ui32Channels) +{ + // Check the arguments. + ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) | + (ui32Channels & CRYPTO_DMA_CHAN1)); + + // Enable the selected channels. + if(ui32Channels & CRYPTO_DMA_CHAN0) + { + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 0; + } + if(ui32Channels & CRYPTO_DMA_CHAN1) + { + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 0; + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/crypto.h new file mode 100644 index 0000000..bb411ec --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/crypto.h @@ -0,0 +1,856 @@ +/****************************************************************************** +* Filename: crypto.h +* Revised: 2018-01-12 18:46:31 +0100 (Fri, 12 Jan 2018) +* Revision: 51161 +* +* Description: AES header file. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup crypto_api +//! @{ +// +//***************************************************************************** + +#ifndef __CRYPTO_H__ +#define __CRYPTO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_crypto.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey + #define CRYPTOAesCbc NOROM_CRYPTOAesCbc + #define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus + #define CRYPTOAesEcb NOROM_CRYPTOAesEcb + #define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus + #define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt + #define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus + #define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet + #define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt + #define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus + #define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet + #define CRYPTODmaEnable NOROM_CRYPTODmaEnable + #define CRYPTODmaDisable NOROM_CRYPTODmaDisable +#endif + +//***************************************************************************** +// +// Length of AES Electronic Code Book (ECB) block in bytes +// +//***************************************************************************** +#define AES_ECB_LENGTH 16 + +//***************************************************************************** +// +// Values that can be passed to CryptoIntEnable, CryptoIntDisable, and CryptoIntClear +// as the ui32IntFlags parameter, and returned from CryptoIntStatus. +// +//***************************************************************************** +#define CRYPTO_DMA_IN_DONE 0x00000002 // DMA done interrupt mask +#define CRYPTO_RESULT_RDY 0x00000001 // Result ready interrupt mask +#define CRYPTO_DMA_BUS_ERR 0x80000000 // DMA Bus error +#define CRYPTO_KEY_ST_WR_ERR 0x40000000 // Key Store Write failed +#define CRYPTO_KEY_ST_RD_ERR 0x20000000 // Key Store Read failed + +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 // Crypto Level interrupt enabled +#define CRYPTO_IRQTYPE_PULSE 0x00000000 // Crypto pulse interrupt enabled + +#define CRYPTO_DMA_CHAN0 0x00000001 // Crypto DMA Channel 0 +#define CRYPTO_DMA_CHAN1 0x00000002 // Crypto DMA Channel 1 + +#define CRYPTO_AES128_ENCRYPT 0x0000000C // +#define CRYPTO_AES128_DECRYPT 0x00000008 // + +#define CRYPTO_DMA_READY 0x00000000 // DMA ready +#define CRYPTO_DMA_BSY 0x00000003 // DMA busy +#define CRYPTO_DMA_BUS_ERROR 0x00020000 // DMA encountered bus error + +//***************************************************************************** +// +// General constants +// +//***************************************************************************** + +// AES module return codes +#define AES_SUCCESS 0 +#define AES_KEYSTORE_READ_ERROR 1 +#define AES_KEYSTORE_WRITE_ERROR 2 +#define AES_DMA_BUS_ERROR 3 +#define CCM_AUTHENTICATION_FAILED 4 +#define AES_ECB_TEST_ERROR 8 +#define AES_NULL_ERROR 9 +#define AES_CCM_TEST_ERROR 10 +#define AES_DMA_BSY 11 + +// Key store module defines +#define STATE_BLENGTH 16 // Number of bytes in State +#define KEY_BLENGTH 16 // Number of bytes in Key +#define KEY_EXP_LENGTH 176 // Nb * (Nr+1) * 4 + +#define KEY_STORE_SIZE_128 0x00000001 +#define KEY_STORE_SIZE_192 0x00000002 +#define KEY_STORE_SIZE_256 0x00000003 +#define KEY_STORE_SIZE_BITS 0x00000003 + +//***************************************************************************** +// +// For 128 bit key all 8 Key Area locations from 0 to 8 are valid +// However for 192 bit and 256 bit keys, only even Key Areas 0, 2, 4, 6 +// are valid. +// +//***************************************************************************** +#define CRYPTO_KEY_AREA_0 0 +#define CRYPTO_KEY_AREA_1 1 +#define CRYPTO_KEY_AREA_2 2 +#define CRYPTO_KEY_AREA_3 3 +#define CRYPTO_KEY_AREA_4 4 +#define CRYPTO_KEY_AREA_5 5 +#define CRYPTO_KEY_AREA_6 6 +#define CRYPTO_KEY_AREA_7 7 + +//***************************************************************************** +// +// Defines for the current AES operation +// +//***************************************************************************** +#define CRYPTO_AES_NONE 0 +#define CRYPTO_AES_KEYL0AD 1 +#define CRYPTO_AES_ECB 2 +#define CRYPTO_AES_CCM 3 +#define CRYPTO_AES_RNG 4 +#define CRYPTO_AES_CBC 5 + +//***************************************************************************** +// +// Defines for the AES-CTR mode counter width +// +//***************************************************************************** +#define CRYPTO_AES_CTR_32 0x0 +#define CRYPTO_AES_CTR_64 0x1 +#define CRYPTO_AES_CTR_96 0x2 +#define CRYPTO_AES_CTR_128 0x3 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Write the key into the Key Ram. +//! +//! The \c ui32KeyLocation parameter is an enumerated type which specifies +//! the Key Ram location in which the key is stored. +//! +//! The pointer \c pui8AesKey has the address where the Key is stored. +//! +//! \param pui32AesKey is a pointer to an AES Key. +//! \param ui32KeyLocation is the location of the key in Key RAM. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! +//! \return Returns status of the function: +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +// +//***************************************************************************** +extern uint32_t CRYPTOAesLoadKey(uint32_t *pui32AesKey, + uint32_t ui32KeyLocation); + +//***************************************************************************** +// +//! \brief Start an AES-CBC operation (encryption or decryption). +//! +//! The function starts an AES CBC mode encrypt or decrypt operation. +//! End operation can be detected by enabling interrupt or by polling +//! CRYPTOAesCbcStatus(). Result of operation is returned by CRYPTOAesCbcStatus(). +//! +//! \param pui32MsgIn is a pointer to the input data. +//! \param pui32MsgOut is a pointer to the output data. +//! \param ui32MsgLength is the length in bytes of the input data. +//! \param pui32Nonce is a pointer to 16-byte Nonce. +//! \param ui32KeyLocation is the location of the key in Key RAM. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! \param bEncrypt is set \c true to encrypt or set \c false to decrypt. +//! \param bIntEnable is set \c true to enable Crypto interrupts or \c false to +//! disable Crypto interrupt. +//! +//! \return Returns status of the AES-CBC operation: +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +//! +//! \sa \ref CRYPTOAesCbcStatus() +// +//***************************************************************************** +extern uint32_t CRYPTOAesCbc(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, + uint32_t ui32MsgLength, uint32_t *pui32Nonce, + uint32_t ui32KeyLocation, bool bEncrypt, + bool bIntEnable); + +//***************************************************************************** +// +//! \brief Check the result of an AES CBC operation. +//! +//! This function should be called after \ref CRYPTOAesCbc() function to +//! check if the AES CBC operation was successful. +//! +//! \return Returns the status of the AES CBC operation: +//! - \ref AES_SUCCESS : Successful. +//! - \ref AES_DMA_BUS_ERROR : Failed. +//! - \ref AES_DMA_BSY : Operation is ongoing. +//! +//! \sa \ref CRYPTOAesCbc() +// +//***************************************************************************** +extern uint32_t CRYPTOAesCbcStatus(void); + +//***************************************************************************** +// +//! \brief Start an AES-ECB operation (encryption or decryption). +//! +//! The \c ui32KeyLocation parameter is an enumerated type which specifies +//! the Key Ram location in which the key is stored. +//! +//! \param pui32MsgIn is a pointer to the input data. +//! \param pui32MsgOut is a pointer to the output data. +//! \param ui32KeyLocation is the location of the key in Key RAM. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! \param bEncrypt is set \c true to encrypt or set \c false to decrypt. +//! \param bIntEnable is set \c true to enable Crypto interrupts or \c false to +//! disable Crypto interrupt. +//! +//! \return Returns status of the AES-ECB operation: +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +//! +//! \sa \ref CRYPTOAesEcbStatus() +// +//***************************************************************************** +extern uint32_t CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, + uint32_t ui32KeyLocation, bool bEncrypt, + bool bIntEnable); + +//***************************************************************************** +// +//! \brief Check the result of an AES ECB operation. +//! +//! This function should be called after \ref CRYPTOAesEcb() function to +//! check if the AES ECB operation was successful. +//! +//! \return Returns the status of the AES ECB operation: +//! - \ref AES_SUCCESS : Successful. +//! - \ref AES_DMA_BUS_ERROR : Failed. +//! - \ref AES_DMA_BSY : Operation is ongoing. +//! +//! \sa \ref CRYPTOAesEcb() +// +//***************************************************************************** +extern uint32_t CRYPTOAesEcbStatus(void); + +//***************************************************************************** +// +//! \brief Finish the encryption operation by resetting the operation mode. +//! +//! This function should be called after \ref CRYPTOAesEcbStatus() has reported +//! that the operation is finished successfully. +//! +//! \return None +//! +//! \sa \ref CRYPTOAesEcbStatus() +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOAesEcbFinish(void) +{ + // Result has already been copied to the output buffer by DMA. + // Disable master control/DMA clock and clear the operating mode. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000; +} + +//***************************************************************************** +// +//! \brief Finish the encryption operation by resetting the operation mode. +//! +//! This function should be called after \ref CRYPTOAesCbcStatus() has reported +//! that the operation is finished successfully. +//! +//! \return None +//! +//! \sa \ref CRYPTOAesCbcStatus() +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOAesCbcFinish(void) +{ + // Result has already been copied to the output buffer by DMA. + // Disable master control/DMA clock and clear the operating mode. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000; +} + +//***************************************************************************** +// +//! \brief Start CCM operation. +//! +//! The \c ui32KeyLocation is an enumerated type which specifies the Key Ram +//! location in which the key is stored. +//! +//! \param bEncrypt determines whether to run encryption or not. +//! \param ui32AuthLength is the length of the authentication field - +//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. +//! \param pui32Nonce is a pointer to 13-byte or 12-byte Nonce (Number used once). +//! \param pui32PlainText is a pointer to the octet string input message. +//! \param ui32PlainTextLength is the length of the message. +//! \param pui32Header is the length of the header (Additional Authentication +//! Data or AAD). +//! \param ui32HeaderLength is the length of the header in octets. +//! \param ui32KeyLocation is the location in Key RAM where the key is stored. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! \param ui32FieldLength is the size of the length field (2 or 3). +//! \param bIntEnable enables interrupts. +//! +//! \return Returns the status of the CCM operation +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +//! - \ref AES_DMA_BUS_ERROR +//! +//! \sa \ref CRYPTOCcmAuthEncryptStatus() +// +//***************************************************************************** +extern uint32_t CRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength, + uint32_t *pui32Nonce, + uint32_t *pui32PlainText, + uint32_t ui32PlainTextLength, + uint32_t *pui32Header, + uint32_t ui32HeaderLength, + uint32_t ui32KeyLocation, + uint32_t ui32FieldLength, + bool bIntEnable); + +//***************************************************************************** +// +//! \brief Check the result of an AES CCM operation. +//! +//! This function should be called after \ref CRYPTOCcmAuthEncrypt() function to check +//! if the AES CCM operation was successful. +//! +//! \return Returns the status of the AES CCM operation: +//! - \ref AES_SUCCESS : Successful. +//! - \ref AES_DMA_BUS_ERROR : Failed. +//! - \ref AES_DMA_BSY : Operation is ongoing. +//! +//! \sa \ref CRYPTOCcmAuthEncrypt() +// +//***************************************************************************** +extern uint32_t CRYPTOCcmAuthEncryptStatus(void); + +//***************************************************************************** +// +//! \brief Get the result of an AES CCM operation. +//! +//! This function should be called after \ref CRYPTOCcmAuthEncryptStatus(). +//! +//! \param ui32TagLength is length of the Tag. +//! \param pui32CcmTag is the location of the authentication Tag. +//! +//! \return Returns \ref AES_SUCCESS if successful. +//! +//! \sa \ref CRYPTOCcmAuthEncryptStatus() +// +//***************************************************************************** +extern uint32_t CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, + uint32_t *pui32CcmTag); + +//***************************************************************************** +// +//! \brief Start a CCM Decryption and Inverse Authentication operation. +//! +//! The \c ui32KeyLocation is an enumerated type which specifies the Key Ram +//! location in which the key is stored. +//! +//! \param bDecrypt determines whether to run decryption or not. +//! \param ui32AuthLength is the length of the authentication field - +//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. +//! \param pui32Nonce is a pointer to 13-byte or 12-byte Nonce (Number used once). +//! \param pui32CipherText is a pointer to the octet string encrypted message. +//! \param ui32CipherTextLength is the length of the encrypted message. +//! \param pui32Header is the length of the header (Additional Authentication +//! Data or AAD). +//! \param ui32HeaderLength is the length of the header in octets. +//! \param ui32KeyLocation is the location in Key RAM where the key is stored. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! \param ui32FieldLength is the size of the length field (2 or 3). +//! \param bIntEnable enables interrupts. +//! +//! \return Returns the status of the operation: +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +//! - \ref AES_DMA_BUS_ERROR +// +//***************************************************************************** +extern uint32_t CRYPTOCcmInvAuthDecrypt(bool bDecrypt, uint32_t ui32AuthLength, + uint32_t *pui32Nonce, + uint32_t *pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t *pui32Header, + uint32_t ui32HeaderLength, + uint32_t ui32KeyLocation, + uint32_t ui32FieldLength, + bool bIntEnable); + +//***************************************************************************** +// +//! \brief Checks CCM decrypt and Inverse Authentication result. +//! +//! \return Returns status of operation: +//! - \ref AES_SUCCESS : Operation was successful. +//! - \ref AES_DMA_BSY : Operation is busy. +//! - \ref AES_DMA_BUS_ERROR : An error is encountered. +// +//***************************************************************************** +extern uint32_t CRYPTOCcmInvAuthDecryptStatus(void); + +//***************************************************************************** +// +//! \brief Get the result of the CCM operation. +//! +//! \param ui32AuthLength is the length of the authentication field - +//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. +//! \param pui32CipherText is a pointer to the octet string encrypted message. +//! \param ui32CipherTextLength is the length of the encrypted message. +//! \param pui32CcmTag is the location of the authentication Tag. +//! +//! \return Returns AES_SUCCESS if successful. +// +//***************************************************************************** +extern uint32_t CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength, + uint32_t *pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t *pui32CcmTag); + +//***************************************************************************** +// +//! \brief Get the current status of the Crypto DMA controller. +//! +//! This function is used to poll the Crypto DMA controller to check if it is +//! ready for a new operation or if an error has occurred. +//! +//! The \ref CRYPTO_DMA_BUS_ERROR can also be caught using the crypto event +//! handler. +//! +//! \return Returns the current status of the DMA controller: +//! - \ref CRYPTO_DMA_READY : DMA ready for a new operation +//! - \ref CRYPTO_DMA_BSY : DMA is busy +//! - \ref CRYPTO_DMA_BUS_ERROR : DMA Bus error +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CRYPTODmaStatus(void) +{ + // Return the value of the status register. + return (HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT)); +} + +//***************************************************************************** +// +//! \brief Enable Crypto DMA operation. +//! +//! The specified Crypto DMA channels are enabled. +//! +//! \param ui32Channels is a bitwise OR of the channels to enable. +//! - \ref CRYPTO_DMA_CHAN0 +//! - \ref CRYPTO_DMA_CHAN1 +//! +//! \return None +// +//***************************************************************************** +extern void CRYPTODmaEnable(uint32_t ui32Channels); + +//***************************************************************************** +// +//! \brief Disable Crypto DMA operation. +//! +//! The specified Crypto DMA channels are disabled. +//! +//! \param ui32Channels is a bitwise OR of the channels to disable. +//! - \ref CRYPTO_DMA_CHAN0 +//! - \ref CRYPTO_DMA_CHAN1 +//! +//! \return None +// +//***************************************************************************** +extern void CRYPTODmaDisable(uint32_t ui32Channels); + +//***************************************************************************** +// +//! \brief Enables individual Crypto interrupt sources. +//! +//! This function enables the indicated Crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref CRYPTO_DMA_IN_DONE +//! - \ref CRYPTO_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntEnable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) | + (ui32IntFlags & CRYPTO_RESULT_RDY)); + + // Using level interrupt. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + + // Enable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual CRYPTO interrupt sources. +//! +//! This function disables the indicated Crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref CRYPTO_DMA_IN_DONE +//! - \ref CRYPTO_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntDisable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) | + (ui32IntFlags & CRYPTO_RESULT_RDY)); + + // Disable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the specified Crypto. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param bMasked whether to use raw or masked interrupt status: +//! - \c false : Raw interrupt status is required. +//! - \c true : Masked interrupt status is required. +//! +//! \return Returns the current interrupt status: +//! - \ref CRYPTO_DMA_IN_DONE +//! - \ref CRYPTO_RESULT_RDY +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CRYPTOIntStatus(bool bMasked) +{ + uint32_t ui32Mask; + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + ui32Mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); + return(ui32Mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); + } + else + { + return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & 0x00000003); + } +} + +//***************************************************************************** +// +//! \brief Clears Crypto interrupt sources. +//! +//! The specified Crypto interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref CRYPTO_DMA_IN_DONE +//! - \ref CRYPTO_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntClear(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) | + (ui32IntFlags & CRYPTO_RESULT_RDY)); + + // Clear the requested interrupt sources, + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for a Crypto interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific UART interrupts must be enabled via \ref CRYPTOIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, pfnHandler); + + // Enable the UART interrupt. + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a Crypto interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a Crypto interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntUnregister(void) +{ + // Disable the interrupt. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_CRYPTOAesLoadKey + #undef CRYPTOAesLoadKey + #define CRYPTOAesLoadKey ROM_CRYPTOAesLoadKey + #endif + #ifdef ROM_CRYPTOAesCbc + #undef CRYPTOAesCbc + #define CRYPTOAesCbc ROM_CRYPTOAesCbc + #endif + #ifdef ROM_CRYPTOAesCbcStatus + #undef CRYPTOAesCbcStatus + #define CRYPTOAesCbcStatus ROM_CRYPTOAesCbcStatus + #endif + #ifdef ROM_CRYPTOAesEcb + #undef CRYPTOAesEcb + #define CRYPTOAesEcb ROM_CRYPTOAesEcb + #endif + #ifdef ROM_CRYPTOAesEcbStatus + #undef CRYPTOAesEcbStatus + #define CRYPTOAesEcbStatus ROM_CRYPTOAesEcbStatus + #endif + #ifdef ROM_CRYPTOCcmAuthEncrypt + #undef CRYPTOCcmAuthEncrypt + #define CRYPTOCcmAuthEncrypt ROM_CRYPTOCcmAuthEncrypt + #endif + #ifdef ROM_CRYPTOCcmAuthEncryptStatus + #undef CRYPTOCcmAuthEncryptStatus + #define CRYPTOCcmAuthEncryptStatus ROM_CRYPTOCcmAuthEncryptStatus + #endif + #ifdef ROM_CRYPTOCcmAuthEncryptResultGet + #undef CRYPTOCcmAuthEncryptResultGet + #define CRYPTOCcmAuthEncryptResultGet ROM_CRYPTOCcmAuthEncryptResultGet + #endif + #ifdef ROM_CRYPTOCcmInvAuthDecrypt + #undef CRYPTOCcmInvAuthDecrypt + #define CRYPTOCcmInvAuthDecrypt ROM_CRYPTOCcmInvAuthDecrypt + #endif + #ifdef ROM_CRYPTOCcmInvAuthDecryptStatus + #undef CRYPTOCcmInvAuthDecryptStatus + #define CRYPTOCcmInvAuthDecryptStatus ROM_CRYPTOCcmInvAuthDecryptStatus + #endif + #ifdef ROM_CRYPTOCcmInvAuthDecryptResultGet + #undef CRYPTOCcmInvAuthDecryptResultGet + #define CRYPTOCcmInvAuthDecryptResultGet ROM_CRYPTOCcmInvAuthDecryptResultGet + #endif + #ifdef ROM_CRYPTODmaEnable + #undef CRYPTODmaEnable + #define CRYPTODmaEnable ROM_CRYPTODmaEnable + #endif + #ifdef ROM_CRYPTODmaDisable + #undef CRYPTODmaDisable + #define CRYPTODmaDisable ROM_CRYPTODmaDisable + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CRYPTO_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi.c new file mode 100644 index 0000000..274a69c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi.c @@ -0,0 +1,214 @@ +/****************************************************************************** +* Filename: ddi.c +* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) +* Revision: 52111 +* +* Description: Driver for the DDI master interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ddi.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef DDI32RegWrite + #define DDI32RegWrite NOROM_DDI32RegWrite + #undef DDI16BitWrite + #define DDI16BitWrite NOROM_DDI16BitWrite + #undef DDI16BitfieldWrite + #define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite + #undef DDI16BitRead + #define DDI16BitRead NOROM_DDI16BitRead + #undef DDI16BitfieldRead + #define DDI16BitfieldRead NOROM_DDI16BitfieldRead +#endif + +//***************************************************************************** +// +// Write a 32 bit value to a register in the DDI slave. +// +//***************************************************************************** +void +DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Val) +{ + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Write the value to the register. + AuxAdiDdiSafeWrite(ui32Base + ui32Reg, ui32Val, 4); +} + +//***************************************************************************** +// +// Write a single bit using a 16-bit maskable write +// +//***************************************************************************** +void +DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32WrData) +{ + uint32_t ui32RegAddr; + uint32_t ui32Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(!((ui32Mask & 0xFFFF0000) ^ (ui32Mask & 0x0000FFFF))); + ASSERT(!(ui32WrData & 0xFFFF0000)); + + // DDI 16-bit target is on 32-bit boundary so double offset + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // Adjust for target bit in high half of the word. + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 4; + ui32Mask >>= 16; + } + + // Write mask if data is not zero (to set mask bit), else write '0'. + ui32Data = ui32WrData ? ui32Mask : 0x0; + + // Update the register. + AuxAdiDdiSafeWrite(ui32RegAddr, (ui32Mask << 16) | ui32Data, 4); +} + +//***************************************************************************** +// +// Write a bit field via the DDI using 16-bit maskable write +// +//***************************************************************************** +void +DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift, + uint16_t ui32Data) +{ + uint32_t ui32RegAddr; + uint32_t ui32WrData; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // 16-bit target is on 32-bit boundary so double offset. + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // Adjust for target bit in high half of the word. + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 4; + ui32Mask = ui32Mask >> 16; + } + + // Shift data in to position. + ui32WrData = ui32Data << ui32Shift; + + // Write data. + AuxAdiDdiSafeWrite(ui32RegAddr, (ui32Mask << 16) | ui32WrData, 4); +} + +//***************************************************************************** +// +// Read a bit via the DDI using 16-bit READ. +// +//***************************************************************************** +uint16_t +DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask) +{ + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // Calculate the address of the register. + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // Adjust for target bit in high half of the word. + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // Read a halfword on the DDI interface. + ui16Data = AuxAdiDdiSafeRead(ui32RegAddr, 2); + + // Mask data. + ui16Data = ui16Data & ui32Mask; + + // Return masked data. + return(ui16Data); +} + +//***************************************************************************** +// +// Read a bit field via the DDI using 16-bit read. +// +//***************************************************************************** +uint16_t +DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift) +{ + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // Calculate the register address. + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // Adjust for target bit in high half of the word. + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // Read the register. + ui16Data = AuxAdiDdiSafeRead(ui32RegAddr, 2); + + // Mask data and shift into place. + ui16Data &= ui32Mask; + ui16Data >>= ui32Shift; + + // Return data. + return(ui16Data); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi.h new file mode 100644 index 0000000..e3b63a0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi.h @@ -0,0 +1,559 @@ +/****************************************************************************** +* Filename: ddi.h +* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) +* Revision: 52111 +* +* Description: Defines and prototypes for the DDI master interface. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup analog_group +//! @{ +//! \addtogroup ddi_api +//! @{ +// +//***************************************************************************** + +#ifndef __DDI_H__ +#define __DDI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ddi.h" +#include "../inc/hw_aux_smph.h" +#include "debug.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define DDI32RegWrite NOROM_DDI32RegWrite + #define DDI16BitWrite NOROM_DDI16BitWrite + #define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite + #define DDI16BitRead NOROM_DDI16BitRead + #define DDI16BitfieldRead NOROM_DDI16BitfieldRead +#endif + +//***************************************************************************** +// +// Number of register in the DDI slave +// +//***************************************************************************** +#define DDI_SLAVE_REGS 64 + + +//***************************************************************************** +// +// Defines that is used to control the ADI slave and master +// +//***************************************************************************** +#define DDI_PROTECT 0x00000080 +#define DDI_ACK 0x00000001 +#define DDI_SYNC 0x00000000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + + +//***************************************************************************** +// +// Helper functions +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Safely write to AUX ADI/DDI interfaces using a semaphore. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param nAddr is the register address. +//! \param nData is the data to write to the register. +//! \param nSize is the register access size in bytes. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AuxAdiDdiSafeWrite(uint32_t nAddr, uint32_t nData, uint32_t nSize) +{ + // Disable interrupts and remember whether to re-enable + bool bIrqEnabled = !CPUcpsid(); + // Acquire semaphore for accessing ADI/DDI in AUX, perform access, release semaphore + while (!HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0)); + switch (nSize) { + case 1: HWREGB(nAddr) = (uint8_t)nData; break; + case 2: HWREGH(nAddr) = (uint16_t)nData; break; + case 4: default: HWREG(nAddr) = nData; break; + } + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0) = 1; + // Restore interrupt enable + if (bIrqEnabled) { + CPUcpsie(); + } +} + +//***************************************************************************** +// +//! \brief Safely read from AUX ADI/DDI interfaces using a semaphore. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param nAddr is the register address. +//! \param nSize is the register access size in bytes. +//! +//! \return Returns the data read. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AuxAdiDdiSafeRead(uint32_t nAddr, uint32_t nSize) +{ + uint32_t nRet; + // Disable interrupts and remember whether to re-enable + bool bIrqEnabled = !CPUcpsid(); + // Acquire semaphore for accessing ADI/DDI in AUX, perform access, release semaphore + while (!HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0)); + switch (nSize) { + case 1: nRet = HWREGB(nAddr); break; + case 2: nRet = HWREGH(nAddr); break; + case 4: default: nRet = HWREG(nAddr); break; + } + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0) = 1; + // Restore interrupt enable + if (bIrqEnabled) { + CPUcpsie(); + } + return nRet; +} + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Check a DDI base address. +//! +//! This function determines if a DDI port base address is valid. +//! +//! \param ui32Base is the base address of the DDI port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +//! +//! \endinternal +// +//***************************************************************************** +static bool +DDIBaseValid(uint32_t ui32Base) +{ + return(ui32Base == AUX_DDI0_OSC_BASE); +} +#endif + + +//***************************************************************************** +// +//! \brief Read the value in a 32 bit register. +//! +//! This function will read a register in the analog domain and return +//! the value as an \c uint32_t. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the 32 bit register to read. +//! +//! \return Returns the 32 bit value of the analog register. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +DDI32RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Read the register and return the value. + return AuxAdiDdiSafeRead(ui32Base + ui32Reg, 4); +} + +//***************************************************************************** +// +//! \brief Set specific bits in a DDI slave register. +//! +//! This function will set bits in a register in the analog domain. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in specific register in the +//! DDI slave. Only bits in the selected register are affected by the +//! operation. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to set in the register. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_SET; + + // Set the selected bits. + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + ui32Reg, ui32Val, 4); +} + +//***************************************************************************** +// +//! \brief Clear specific bits in a 32 bit DDI register. +//! +//! This function will clear bits in a register in the analog domain. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to clear in the register. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_CLR; + + // Clear the selected bits. + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + ui32Reg, ui32Val, 4); +} + +//***************************************************************************** +// +//! \brief Set a value on any 8 bits inside a 32 bit register in the DDI slave. +//! +//! This function allows byte (8 bit access) to the DDI slave registers. +//! +//! Use this function to write any value in the range 0-7 bits aligned on a +//! byte boundary. For example, for writing the value 0b101 to bits 1-3 set +//! ui16Val = 0x0A and ui16Mask = 0x0E. Bits 0 and 5-7 will +//! not be affected by the operation, as long as the corresponding bits are +//! not set in the \c ui16Mask. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is the Least Significant Register in the DDI slave that +//! will be affected by the write operation. +//! \param ui32Byte is the byte number to access within the 32 bit register. +//! \param ui16Mask is the mask defining which of the 8 bits that should be +//! overwritten. The mask must be defined in the lower half of the 16 bits. +//! \param ui16Val is the value to write. The value must be defined in the lower +//! half of the 16 bits. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Byte, + uint16_t ui16Mask, uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + ASSERT(!(ui16Val & 0xFF00)); + ASSERT(!(ui16Mask & 0xFF00)); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_MASK8B + (ui32Reg << 1) + (ui32Byte << 1); + + // Set the selected bits. + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset, (ui16Mask << 8) | ui16Val, 2); +} + +//***************************************************************************** +// +//! \brief Set a value on any 16 bits inside a 32 bit register aligned on a +//! half-word boundary in the DDI slave. +//! +//! This function allows 16 bit masked access to the DDI slave registers. +//! +//! Use this function to write any value in the range 0-15 bits aligned on a +//! half-word boundary. For example, for writing the value 0b101 to bits 1-3 set +//! ui32Val = 0x000A and ui32Mask = 0x000E. Bits 0 and 5-15 will not be +//! affected by the operation, as long as the corresponding bits are not set +//! in the \c ui32Mask. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param bWriteHigh defines which part of the register to write in. +//! \param ui32Mask is the mask defining which of the 16 bit that should be +//! overwritten. The mask must be defined in the lower half of the 32 bits. +//! \param ui32Val is the value to write. The value must be defined in the lower +//! half of the 32 bits. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh, + uint32_t ui32Mask, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + ASSERT(!(ui32Val & 0xFFFF0000)); + ASSERT(!(ui32Mask & 0xFFFF0000)); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_MASK16B + (ui32Reg << 1) + (bWriteHigh ? 4 : 0); + + // Set the selected bits. + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset, (ui32Mask << 16) | ui32Val, 4); +} + +//***************************************************************************** +// +//! \brief Write a 32 bit value to a register in the DDI slave. +//! +//! This function will write a value to a register in the analog +//! domain. +//! +//! \note This operation is write only for the specified register. No +//! conservation of the previous value of the register will be kept (i.e. this +//! is NOT read-modify-write on the register). +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the register to write. +//! \param ui32Val is the 32 bit value to write to the register. +//! +//! \return None +// +//***************************************************************************** +extern void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val); + +//***************************************************************************** +// +//! \brief Write a single bit using a 16-bit maskable write. +//! +//! A '1' is written to the bit if \c ui32WrData is non-zero, else a '0' is written. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param ui32Mask is the mask defining which of the 16 bit that should be overwritten. +//! \param ui32WrData is the value to write. The value must be defined in the lower half of the 32 bits. +//! +//! \return None +// +//***************************************************************************** +extern void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32WrData); + + +//***************************************************************************** +// +//! \brief Write a bit field via the DDI using 16-bit maskable write. +//! +//! Requires that entire bit field is within the half word boundary. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten. +//! \param ui32Shift is the shift value for the bit field. +//! \param ui32Data is the data aligned to bit 0. +//! +//! \return None +// +//***************************************************************************** +extern void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift, + uint16_t ui32Data); + +//***************************************************************************** +// +//! \brief Read a bit via the DDI using 16-bit read. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the DDI module. +//! \param ui32Reg is the register to read. +//! \param ui32Mask defines the bit which should be read. +//! +//! \return Returns a zero if bit selected by mask is '0'. Else returns the mask. +// +//***************************************************************************** +extern uint16_t DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask); + +//***************************************************************************** +// +//! \brief Read a bit field via the DDI using 16-bit read. +//! +//! Requires that entire bit field is within the half word boundary. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten. +//! \param ui32Shift defines the required shift of the data to align with bit 0. +//! +//! \return Returns data aligned to bit 0. +// +//***************************************************************************** +extern uint16_t DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_DDI32RegWrite + #undef DDI32RegWrite + #define DDI32RegWrite ROM_DDI32RegWrite + #endif + #ifdef ROM_DDI16BitWrite + #undef DDI16BitWrite + #define DDI16BitWrite ROM_DDI16BitWrite + #endif + #ifdef ROM_DDI16BitfieldWrite + #undef DDI16BitfieldWrite + #define DDI16BitfieldWrite ROM_DDI16BitfieldWrite + #endif + #ifdef ROM_DDI16BitRead + #undef DDI16BitRead + #define DDI16BitRead ROM_DDI16BitRead + #endif + #ifdef ROM_DDI16BitfieldRead + #undef DDI16BitfieldRead + #define DDI16BitfieldRead ROM_DDI16BitfieldRead + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DDI_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi_doc.h new file mode 100644 index 0000000..1c96d73 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi_doc.h @@ -0,0 +1,70 @@ +/****************************************************************************** +* Filename: ddi_doc.h +* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) +* Revision: 47080 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup ddi_api +//! @{ +//! \section sec_ddi Introduction +//! \n +//! +//! \section sec_ddi_api API +//! +//! The API functions can be grouped like this: +//! +//! Write: +//! - Direct (all bits): +//! - \ref DDI32RegWrite() +//! - Set individual bits: +//! - \ref DDI32BitsSet() +//! - Clear individual bits: +//! - \ref DDI32BitsClear() +//! - Masked: +//! - \ref DDI8SetValBit() +//! - \ref DDI16SetValBit() +//! - Special functions using masked write: +//! - \ref DDI16BitWrite() +//! - \ref DDI16BitfieldWrite() +//! +//! Read: +//! - Direct (all bits): +//! - \ref DDI32RegRead() +//! - Special functions using masked read: +//! - \ref DDI16BitRead() +//! - \ref DDI16BitfieldRead() +//! +//! AUX access using semaphores (used by both ADI and DDI APIs when necessary): +//! - \ref AuxAdiDdiSafeRead() +//! - \ref AuxAdiDdiSafeWrite() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/debug.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/debug.c new file mode 100644 index 0000000..5626638 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/debug.c @@ -0,0 +1,57 @@ +/****************************************************************************** +* Filename: debug.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the Debug functionality (NB. This is a stub which +* should never be included in a release). +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include +#include "../inc/hw_types.h" +#include "debug.h" + +//***************************************************************************** +// +// Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted. +// +//***************************************************************************** +void +__error__(char *pcFilename, uint32_t ui32Line) +{ + // Error catching. + // User can implement custom error handling for failing ASSERTs. + // Setting breakpoint here allows tracing of the failing ASSERT. + while( true ); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/debug.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/debug.h new file mode 100644 index 0000000..704fd5c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/debug.h @@ -0,0 +1,84 @@ +/****************************************************************************** +* Filename: debug.h +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Macros for assisting debug of the driver library. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup debug_api +//! @{ +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +//! Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted. +// +//***************************************************************************** +extern void __error__(char *pcFilename, uint32_t ui32Line); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DRIVERLIB_DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } + +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/driverlib_release.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/driverlib_release.c new file mode 100644 index 0000000..ca51532 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/driverlib_release.c @@ -0,0 +1,45 @@ +/****************************************************************************** +* Filename: driverlib_release.c +* Revised: $Date: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) $ +* Revision: $Revision: 47152 $ +* +* Description: Provides macros for ensuring that a specfic release of +* DriverLib is used. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#include "../driverlib/driverlib_release.h" + + + + +/// Declare the current DriverLib release +DRIVERLIB_DECLARE_RELEASE(0, 54539); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/driverlib_release.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/driverlib_release.h new file mode 100644 index 0000000..b7a0434 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/driverlib_release.h @@ -0,0 +1,156 @@ +/****************************************************************************** +* Filename: driverlib_release.h +* Revised: $Date: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015) $ +* Revision: $Revision: 44151 $ +* +* Description: Provides macros for ensuring that a specfic release of +* DriverLib is used. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup driverlib_release_api +//! @{ +// +//***************************************************************************** + +#ifndef __DRIVERLIB_RELEASE_H__ +#define __DRIVERLIB_RELEASE_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + + + + +/// DriverLib release group number +#define DRIVERLIB_RELEASE_GROUP 0 +/// DriverLib release build number +#define DRIVERLIB_RELEASE_BUILD 54539 + + + + +//***************************************************************************** +// +//! This macro is called internally from within DriverLib to declare the +//! DriverLib release locking object: +//! \param group is the DriverLib release group number. +//! \param build is the DriverLib release build number. +//! +//! This macro shall not be called in the application unless the intention is +//! to bypass the release locking (at own risk). +// +//***************************************************************************** +#define DRIVERLIB_DECLARE_RELEASE(group, build) \ + const volatile uint8_t driverlib_release_##group##_##build + +/// External declaration of the DriverLib release locking object +extern DRIVERLIB_DECLARE_RELEASE(0, 54539); + + + + +//***************************************************************************** +// +//! This macro shall be called once from within a function of a precompiled +//! software deliverable to lock the deliverable to a specific DriverLib +//! release. It is essential that the call is made from code that is not +//! optimized away. +//! +//! This macro locks to a specific DriverLib release: +//! \param group is the DriverLib release group number. +//! \param build is the DriverLib release build number. +//! +//! If attempting to use the precompiled deliverable with a different release +//! of DriverLib, a linker error will be produced, stating that +//! "driverlib_release_xx_yyyyy is undefined" or similar. +//! +//! To override the check, for example when upgrading DriverLib but not the +//! precompiled deliverables, or when mixing precompiled deliverables, +//! application developers may (at own risk) declare the missing DriverLib +//! release using the \ref DRIVERLIB_DECLARE_RELEASE() macro. +// +//***************************************************************************** +#define DRIVERLIB_ASSERT_RELEASE(group, build) \ + (driverlib_release_##group##_##build) + + + + +//***************************************************************************** +// +//! This macro shall be called once from within a function of a precompiled +//! software deliverable to lock the deliverable to a specific DriverLib +//! release. It is essential that the call is made from code that is not +//! optimized away. +//! +//! This macro locks to the current DriverLib release used at compile-time. +//! +//! If attempting to use the precompiled deliverable with a different release +//! of DriverLib, a linker error will be produced, stating that +//! "driverlib_release_xx_yyyyy is undefined" or similar. +//! +//! To override the check, for example when upgrading DriverLib but not the +//! precompiled deliverables, or when mixing precompiled deliverables, +//! application developers may (at own risk) declare the missing DriverLib +//! release using the \ref DRIVERLIB_DECLARE_RELEASE() macro. +// +//***************************************************************************** +#define DRIVERLIB_ASSERT_CURR_RELEASE() \ + DRIVERLIB_ASSERT_RELEASE(0, 54539) + + + + +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_RELEASE_H__ + + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event.c new file mode 100644 index 0000000..0d44d43 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: event.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the Event Fabric. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "event.h" + +// See event.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event.h new file mode 100644 index 0000000..2f84902 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event.h @@ -0,0 +1,267 @@ +/****************************************************************************** +* Filename: event.h +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Defines and prototypes for the Event Handler. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup event_api +//! @{ +// +//***************************************************************************** + +#ifndef __EVENT_H__ +#define __EVENT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_event.h" +#include "debug.h" + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Connects an event to an event subscriber via Event Fabric. +//! +//! This function connects event sources to event subscribers. +//! +//! It is not possible to read event status in this module (except software events). +//! Event status must be read in the module that contains the event source. How a +//! specific event subscriber reacts to an event is configured and documented in +//! the respective modules. +//! +//! For a full list of configurable and constant mapped event sources to event +//! subscribers see the register descriptions for +//! Event Fabric. +//! +//! Defines for event subscriber argument (\c ui32EventSubscriber) have the format: +//! - \ti_code{EVENT_O_[subscriber_name]} +//! +//! Defines for event source argument (\c ui32EventSource) must have the +//! following format where valid \c event_enum values are found in the +//! register description : +//! - \ti_code{EVENT_[subscriber_name]_EV_[event_enum]} +//! +//! Examples of valid defines for \c ui32EventSource: +//! - EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE +//! - EVENT_RFCSEL9_EV_AUX_COMPA +//! - EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD +//! +//! \note Each event subscriber can only receive a sub-set of the event sources! +//! +//! \note Switching the event source is not glitch free, so it is imperative +//! that the subscriber is disabled for interrupts when switching the event +//! source. The behavior is undefined if not disabled. +//! +//! \param ui32EventSubscriber is the \b configurable event subscriber to receive the event. +//! Click the event subscriber to see the list of valid event sources in the +//! register description. +//! - EVENT_O_CPUIRQSEL30 : System CPU interrupt 30 +//! - EVENT_O_RFCSEL9 : RF Core event 9 +//! - EVENT_O_GPT0ACAPTSEL : GPT 0A capture event +//! - EVENT_O_GPT0BCAPTSEL : GPT 0B capture event +//! - EVENT_O_GPT1ACAPTSEL : GPT 1A capture event +//! - EVENT_O_GPT1BCAPTSEL : GPT 1B capture event +//! - EVENT_O_GPT2ACAPTSEL : GPT 2A capture event +//! - EVENT_O_GPT2BCAPTSEL : GPT 2B capture event +//! - EVENT_O_GPT3ACAPTSEL : GPT 3A capture event +//! - EVENT_O_GPT3BCAPTSEL : GPT 3B capture event +//! - EVENT_O_UDMACH9SSEL : uDMA channel 9 single request +//! - EVENT_O_UDMACH9BSEL : uDMA channel 9 burst request +//! - EVENT_O_UDMACH10SSEL : uDMA channel 10 single request +//! - EVENT_O_UDMACH10BSEL : uDMA channel 10 burst request +//! - EVENT_O_UDMACH11SSEL : uDMA channel 11 single request +//! - EVENT_O_UDMACH11BSEL : uDMA channel 11 burst request +//! - EVENT_O_UDMACH12SSEL : uDMA channel 12 single request +//! - EVENT_O_UDMACH12BSEL : uDMA channel 12 burst request +//! - EVENT_O_UDMACH14BSEL : uDMA channel 14 single request +//! - EVENT_O_AUXSEL0 : AUX +//! - EVENT_O_I2SSTMPSEL0 : I2S +//! - EVENT_O_FRZSEL0 : Freeze modules (some modules can freeze on CPU Halt) +//! \param ui32EventSource is the specific event that must be acted upon. +//! - Format: \ti_code{EVENT_[subscriber_name]_EV_[event_enum]} (see explanation above) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +EventRegister(uint32_t ui32EventSubscriber, uint32_t ui32EventSource) +{ + // Check the arguments. + ASSERT(( ui32EventSubscriber == EVENT_O_CPUIRQSEL30 ) || + ( ui32EventSubscriber == EVENT_O_RFCSEL9 ) || + ( ui32EventSubscriber == EVENT_O_GPT0ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT0BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT1ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT1BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT2ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT2BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT3ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT3BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH9SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH9BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH10SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH10BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH11SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH11BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH12SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH12BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH14BSEL ) || + ( ui32EventSubscriber == EVENT_O_AUXSEL0 ) || + ( ui32EventSubscriber == EVENT_O_I2SSTMPSEL0 ) || + ( ui32EventSubscriber == EVENT_O_FRZSEL0 ) ); + + // Map the event source to the event subscriber + HWREG(EVENT_BASE + ui32EventSubscriber) = ui32EventSource; +} + +//***************************************************************************** +// +//! \brief Sets software event. +//! +//! Setting a software event triggers the event if the value was 0 before. +//! +//! \note The software event must be cleared manually after the event has +//! triggered the event subscriber. +//! +//! \param ui32SwEvent is the software event number. +//! - 0 : SW Event 0 +//! - 1 : SW Event 1 +//! - 2 : SW Event 2 +//! - 3 : SW Event 3 +//! +//! \return None +//! +//! \sa \ref EventSwEventClear() +// +//***************************************************************************** +__STATIC_INLINE void +EventSwEventSet(uint32_t ui32SwEvent) +{ + // Check the arguments. + ASSERT( ui32SwEvent <= 3 ); + + // Each software event is byte accessible + HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 1; +} + +//***************************************************************************** +// +//! \brief Clears software event. +//! +//! \param ui32SwEvent is the software event number. +//! - 0 : SW Event 0 +//! - 1 : SW Event 1 +//! - 2 : SW Event 2 +//! - 3 : SW Event 3 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +EventSwEventClear(uint32_t ui32SwEvent) +{ + // Check the arguments. + ASSERT( ui32SwEvent <= 3 ); + + // Each software event is byte accessible + HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 0; +} + +//***************************************************************************** +// +//! \brief Gets software event status. +//! +//! \param ui32SwEvent is the software event number. +//! - 0 : SW Event 0 +//! - 1 : SW Event 1 +//! - 2 : SW Event 2 +//! - 3 : SW Event 3 +//! +//! \return Returns current value of requested software event. +//! - 0 : Software event is de-asserted. +//! - 1 : Software event is asserted. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +EventSwEventGet(uint32_t ui32SwEvent) +{ + // Check the arguments. + ASSERT( ui32SwEvent <= 3 ); + + // Each software event is byte accessible + return( HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent)); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __EVENT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event_doc.h new file mode 100644 index 0000000..a17b238 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event_doc.h @@ -0,0 +1,58 @@ +/****************************************************************************** +* Filename: event_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup event_api +//! @{ +//! \section sec_event Introduction +//! +//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and +//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers +//! to the AON event fabric. For more information on AON event fabric, see [AON event API](@ref aonevent_api). +//! +//! The MCU event fabric is a combinational router between event sources and event subscribers. Most +//! event subscribers have statically routed event sources but several event subscribers have +//! configurable event sources which is configured in the MCU event fabric through this API. Although +//! configurable only a subset of event sources are available to each of the configurable event subscribers. +//! This is explained in more details in the function @ref EventRegister() which does all the event routing +//! configuration. +//! +//! MCU event fabric also contains four software events which allow software to trigger certain event +//! subscribers. Each of the four software events is an independent event source which must be set and +//! cleared in the MCU event fabric through the functions: +//! - @ref EventSwEventSet() +//! - @ref EventSwEventClear() +//! - @ref EventSwEventGet() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/flash.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/flash.c new file mode 100644 index 0000000..5fcd34d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/flash.c @@ -0,0 +1,672 @@ +/****************************************************************************** +* Filename: flash.c +* Revised: 2017-10-30 13:37:49 +0100 (Mon, 30 Oct 2017) +* Revision: 50105 +* +* Description: Driver for on chip Flash. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "flash.h" +#include "rom.h" +#include "chipinfo.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef FlashPowerModeSet + #define FlashPowerModeSet NOROM_FlashPowerModeSet + #undef FlashPowerModeGet + #define FlashPowerModeGet NOROM_FlashPowerModeGet + #undef FlashProtectionSet + #define FlashProtectionSet NOROM_FlashProtectionSet + #undef FlashProtectionGet + #define FlashProtectionGet NOROM_FlashProtectionGet + #undef FlashProtectionSave + #define FlashProtectionSave NOROM_FlashProtectionSave + #undef FlashSectorErase + #define FlashSectorErase NOROM_FlashSectorErase + #undef FlashProgram + #define FlashProgram NOROM_FlashProgram + #undef FlashEfuseReadRow + #define FlashEfuseReadRow NOROM_FlashEfuseReadRow + #undef FlashDisableSectorsForWrite + #define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite +#endif + + +//***************************************************************************** +// +// Defines for accesses to the security control in the customer configuration +// area in flash top sector. +// +//***************************************************************************** +#define CCFG_OFFSET_SECURITY CCFG_O_BL_CONFIG +#define CCFG_OFFSET_SECT_PROT CCFG_O_CCFG_PROT_31_0 +#define CCFG_SIZE_SECURITY 0x00000014 +#define CCFG_SIZE_SECT_PROT 0x00000004 + +//***************************************************************************** +// +// Default values for security control in customer configuration area in flash +// top sector. +// +//***************************************************************************** +const uint8_t g_pui8CcfgDefaultSec[] = {0xFF, 0xFF, 0xFF, 0xC5, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xC5, 0xFF, 0xFF, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF + }; + +typedef uint32_t (* FlashPrgPointer_t) (uint8_t *, uint32_t, uint32_t); + +typedef uint32_t (* FlashSectorErasePointer_t) (uint32_t); + +//***************************************************************************** +// +// Function prototypes for static functions +// +//***************************************************************************** +static void SetReadMode(void); + +//***************************************************************************** +// +// Set power mode +// +//***************************************************************************** +void +FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, + uint32_t ui32PumpGracePeriod) +{ + // Check the arguments. + ASSERT(ui32PowerMode == FLASH_PWR_ACTIVE_MODE || + ui32PowerMode == FLASH_PWR_OFF_MODE || + ui32PowerMode == FLASH_PWR_DEEP_STDBY_MODE); + ASSERT(ui32BankGracePeriod <= 0xFF); + ASSERT(ui32PumpGracePeriod <= 0xFFFF); + + switch(ui32PowerMode) + { + case FLASH_PWR_ACTIVE_MODE: + // Set bank power mode to ACTIVE. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = + (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_ACTIVE; + + // Set charge pump power mode to ACTIVE mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) = + (HWREG(FLASH_BASE + FLASH_O_FPAC1) & ~FLASH_FPAC1_PUMPPWR_M) | (1 << FLASH_FPAC1_PUMPPWR_S); + break; + + case FLASH_PWR_OFF_MODE: + // Set bank grace period. + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // Set pump grace period. + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // Set bank power mode to SLEEP. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= ~FLASH_FBFALLBACK_BANKPWR0_M; + + // Set charge pump power mode to SLEEP mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M; + break; + + case FLASH_PWR_DEEP_STDBY_MODE: + // Set bank grace period. + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // Set pump grace period. + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // Set bank power mode to DEEP STANDBY mode. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = + (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_DEEP_STDBY; + + // Set charge pump power mode to STANDBY mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) |= FLASH_FPAC1_PUMPPWR_M; + break; + } +} + +//***************************************************************************** +// +// Get current configured power mode +// +//***************************************************************************** +uint32_t +FlashPowerModeGet(void) +{ + uint32_t ui32PowerMode; + uint32_t ui32BankPwrMode; + + ui32BankPwrMode = HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + FLASH_FBFALLBACK_BANKPWR0_M; + + if(ui32BankPwrMode == FBFALLBACK_SLEEP) + { + ui32PowerMode = FLASH_PWR_OFF_MODE; + } + else if(ui32BankPwrMode == FBFALLBACK_DEEP_STDBY) + { + ui32PowerMode = FLASH_PWR_DEEP_STDBY_MODE; + } + else + { + ui32PowerMode = FLASH_PWR_ACTIVE_MODE; + } + + // Return power mode. + return(ui32PowerMode); +} + +//***************************************************************************** +// +// Set sector protection +// +//***************************************************************************** +void +FlashProtectionSet(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode) +{ + uint32_t ui32SectorNumber; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(ui32ProtectMode == FLASH_WRITE_PROTECT) + { + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / + FlashSectorSizeGet(); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + if(ui32SectorNumber <= 31) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber); + } + else if(ui32SectorNumber <= 63) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |= + (1 << (ui32SectorNumber & 0x1F)); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |= + (1 << (ui32SectorNumber & 0x1F)); + } + + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } +} + +//***************************************************************************** +// +// Get sector protection +// +//***************************************************************************** +uint32_t +FlashProtectionGet(uint32_t ui32SectorAddress) +{ + uint32_t ui32SectorProtect; + uint32_t ui32SectorNumber; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + ui32SectorProtect = FLASH_NO_PROTECT; + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + + if(ui32SectorNumber <= 31) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + else if(ui32SectorNumber <= 63) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) & + (1 << (ui32SectorNumber & 0x1F))) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) & + (1 << (ui32SectorNumber & 0x1F)))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + + return(ui32SectorProtect); +} + +//***************************************************************************** +// +// Save sector protection to make it permanent +// +//***************************************************************************** +uint32_t +FlashProtectionSave(uint32_t ui32SectorAddress) +{ + uint32_t ui32ErrorReturn; + uint32_t ui32SectorNumber; + uint32_t ui32CcfgSectorAddr; + uint32_t ui32ProgBuf; + + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(FlashProtectionGet(ui32SectorAddress) == FLASH_WRITE_PROTECT) + { + // Find sector number for specified sector. + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + ui32CcfgSectorAddr = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); + + // Adjust CCFG address to the 32-bit CCFG word holding the + // protect-bit for the specified sector. + ui32CcfgSectorAddr += (((ui32SectorNumber >> 5) * 4) + CCFG_OFFSET_SECT_PROT); + + // Find value to program by setting the protect-bit which + // corresponds to specified sector number, to 0. + // Leave other protect-bits unchanged. + ui32ProgBuf = (~(1 << (ui32SectorNumber & 0x1F))) & + *(uint32_t *)ui32CcfgSectorAddr; + + ui32ErrorReturn = FlashProgram((uint8_t*)&ui32ProgBuf, ui32CcfgSectorAddr, + CCFG_SIZE_SECT_PROT); + } + + // Return status. + return(ui32ErrorReturn); +} + +//***************************************************************************** +// +// Erase a flash sector +// +//***************************************************************************** +uint32_t +FlashSectorErase(uint32_t ui32SectorAddress) +{ + uint32_t ui32ErrorReturn; + FlashSectorErasePointer_t FuncPointer; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + // Call ROM function that handles the actual erase operation + FuncPointer = (uint32_t (*)(uint32_t)) (ROM_API_FLASH_TABLE[5]); + ui32ErrorReturn = FuncPointer(ui32SectorAddress); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); + +} + + +//***************************************************************************** +// +// Programs unprotected main bank flash sectors +// +//***************************************************************************** +uint32_t +FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) +{ + uint32_t ui32ErrorReturn; + FlashPrgPointer_t FuncPointer; + + // Check the arguments. + ASSERT((ui32Address + ui32Count) <= (FLASHMEM_BASE + FlashSizeGet())); + + // Call ROM function that handles the actual program operation + FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ROM_API_FLASH_TABLE[6]); + ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); + +} + +//***************************************************************************** +// +// Reads efuse data from specified row +// +//***************************************************************************** +bool +FlashEfuseReadRow(uint32_t *pui32EfuseData, uint32_t ui32RowAddress) +{ + bool bStatus; + + // Make sure the clock for the efuse is enabled + HWREG(FLASH_BASE + FLASH_O_CFG) &= ~FLASH_CFG_DIS_EFUSECLK; + + // Set timing for EFUSE read operations. + HWREG(FLASH_BASE + FLASH_O_EFUSEREAD) |= ((5 << FLASH_EFUSEREAD_READCLOCK_S) & + FLASH_EFUSEREAD_READCLOCK_M); + + // Clear status register. + HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) = 0; + + // Select the FuseROM block 0. + HWREG(FLASH_BASE + FLASH_O_EFUSEADDR) = 0x00000000; + + // Start the read operation. + HWREG(FLASH_BASE + FLASH_O_EFUSE) = + (DUMPWORD_INSTR << FLASH_EFUSE_INSTRUCTION_S) | + (ui32RowAddress & FLASH_EFUSE_DUMPWORD_M); + + // Wait for operation to finish. + while(!(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_DONE)) + { + } + + // Check if error reported. + if(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_CODE_M) + { + // Set error status. + bStatus = 1; + + // Clear data. + *pui32EfuseData = 0; + } + else + { + // Set ok status. + bStatus = 0; + + // No error. Get data from data register. + *pui32EfuseData = HWREG(FLASH_BASE + FLASH_O_DATALOWER); + } + + // Disable the efuse clock to conserve power + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_EFUSECLK; + + // Return the data. + return(bStatus); +} + + +//***************************************************************************** +// +// Disables all sectors for erase and programming on the active bank +// +//***************************************************************************** +void +FlashDisableSectorsForWrite(void) +{ + // Configure flash back to read mode + SetReadMode(); + + // Disable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + // Disable all sectors for erase and programming. + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; + + // Enable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Protect sectors from sector erase. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \internal +//! Used to set flash in read mode. +//! +//! Flash is configured with values loaded from OTP dependent on the current +//! regulator mode. +//! +//! \return None. +// +//***************************************************************************** +static void +SetReadMode(void) +{ + uint32_t ui32TrimValue; + uint32_t ui32Value; + + // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + // VIN_AT_X and VIN_BY_PASS for read mode + if(HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL) & + AON_SYSCTL_PWRCTL_EXT_REG_MODE) + { + // Select trim values for external regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 4). + // Configure DIS_IDLE (OTP offset 0x308 bit 3). + ui32Value |= ((ui32TrimValue & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // Wait for disabled sample and hold functionality to be stable. + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 2:0) + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } + else + { + // Select trim values for internal regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 12). + // Configure DIS_IDLE (OTP offset 0x308 bit 11). + ui32Value |= ((ui32TrimValue & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // Wait for disabled sample and hold functionality to be stable. + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 10:8) + ui32Value = (((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S); + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} + +//***************************************************************************** +// +// HAPI Flash program function +// +//***************************************************************************** +uint32_t +MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer, uint32_t ui32Address, + uint32_t ui32Count) +{ + uint32_t ui32ErrorReturn; + FlashPrgPointer_t FuncPointer; + uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (5 * 4)); + + // Call ROM function + FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ui32RomAddr); + ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); +} + +//***************************************************************************** +// +// HAPI Flash sector erase function +// +//***************************************************************************** +uint32_t +MemBusWrkAroundHapiEraseSector(uint32_t ui32Address) +{ + uint32_t ui32ErrorReturn; + + FlashSectorErasePointer_t FuncPointer; + uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (3 * 4)); + + // Call ROM function + FuncPointer = (uint32_t (*)(uint32_t)) (ui32RomAddr); + ui32ErrorReturn = FuncPointer(ui32Address); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/flash.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/flash.h new file mode 100644 index 0000000..75b7da4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/flash.h @@ -0,0 +1,817 @@ +/****************************************************************************** +* Filename: flash.h +* Revised: 2017-11-02 16:09:32 +0100 (Thu, 02 Nov 2017) +* Revision: 50166 +* +* Description: Defines and prototypes for the Flash driver. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_flash.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aon_sysctl.h" +#include "../inc/hw_fcfg1.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define FlashPowerModeSet NOROM_FlashPowerModeSet + #define FlashPowerModeGet NOROM_FlashPowerModeGet + #define FlashProtectionSet NOROM_FlashProtectionSet + #define FlashProtectionGet NOROM_FlashProtectionGet + #define FlashProtectionSave NOROM_FlashProtectionSave + #define FlashSectorErase NOROM_FlashSectorErase + #define FlashProgram NOROM_FlashProgram + #define FlashEfuseReadRow NOROM_FlashEfuseReadRow + #define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite +#endif + +//***************************************************************************** +// +// Values that can be returned from the API functions +// +//***************************************************************************** +#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully +#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy +#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready +#define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH \ + 0x00000003 // Incorrect parameter value +#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed + +//***************************************************************************** +// +// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and +// returned from FlashIntStatus(). +// +//***************************************************************************** +#define FLASH_INT_FSM_DONE 0x00400000 // FSM Done Interrupt Mask +#define FLASH_INT_RV 0x00010000 // Read Verify error Interrupt Mask + +//***************************************************************************** +// +// Values passed to FlashSetPowerMode() and returned from FlashGetPowerMode(). +// +//***************************************************************************** +#define FLASH_PWR_ACTIVE_MODE 0x00000000 +#define FLASH_PWR_OFF_MODE 0x00000001 +#define FLASH_PWR_DEEP_STDBY_MODE \ + 0x00000002 + +//***************************************************************************** +// +// Values passed to FlashSetProtection() and returned from FlashGetProtection(). +// +//***************************************************************************** +#define FLASH_NO_PROTECT 0x00000000 // Sector not protected +#define FLASH_WRITE_PROTECT 0x00000001 // Sector erase and program + // protected + +//***************************************************************************** +// +// Define used by the flash programming and erase functions +// +//***************************************************************************** +#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE) + +//***************************************************************************** +// +// Define used for access to factory configuration area. +// +//***************************************************************************** +#define FCFG1_OFFSET 0x1000 + +//***************************************************************************** +// +// Define for the clock frequency input to the flash module in number of MHz +// +//***************************************************************************** +#define FLASH_MODULE_CLK_FREQ 48 + +//***************************************************************************** +// +//! \brief Defined values for Flash State Machine commands +// +//***************************************************************************** +typedef enum +{ + FAPI_PROGRAM_DATA = 0x0002, //!< Program data. + FAPI_ERASE_SECTOR = 0x0006, //!< Erase sector. + FAPI_ERASE_BANK = 0x0008, //!< Erase bank. + FAPI_VALIDATE_SECTOR = 0x000E, //!< Validate sector. + FAPI_CLEAR_STATUS = 0x0010, //!< Clear status. + FAPI_PROGRAM_RESUME = 0x0014, //!< Program resume. + FAPI_ERASE_RESUME = 0x0016, //!< Erase resume. + FAPI_CLEAR_MORE = 0x0018, //!< Clear more. + FAPI_PROGRAM_SECTOR = 0x0020, //!< Program sector. + FAPI_ERASE_OTP = 0x0030 //!< Erase OTP. +} tFlashStateCommandsType; + +//***************************************************************************** +// +// Defines for values written to the FLASH_O_FSM_WR_ENA register +// +//***************************************************************************** +#define FSM_REG_WRT_ENABLE 5 +#define FSM_REG_WRT_DISABLE 2 + +//***************************************************************************** +// +// Defines for the bank power mode field the FLASH_O_FBFALLBACK register +// +//***************************************************************************** +#define FBFALLBACK_SLEEP 0 +#define FBFALLBACK_DEEP_STDBY 1 +#define FBFALLBACK_ACTIVE 3 + +//***************************************************************************** +// +// Defines for the bank grace period and pump grace period +// +//***************************************************************************** +#define FLASH_BAGP 0x14 +#define FLASH_PAGP 0x14 + +//***************************************************************************** +// +// Defines used by the FlashProgramPattern() function +// +//***************************************************************************** +#define PATTERN_BITS 0x20 // No of bits in data pattern to program + +//***************************************************************************** +// +// Defines for the FW flag bits in the FLASH_O_FWFLAG register +// +//***************************************************************************** +#define FW_WRT_TRIMMED 0x00000001 + +//***************************************************************************** +// +// Defines used by the flash programming functions +// +//***************************************************************************** +typedef volatile uint8_t tFwpWriteByte; +#define FWPWRITE_BYTE_ADDRESS ((tFwpWriteByte *)((FLASH_BASE + FLASH_O_FWPWRITE0))) + +//***************************************************************************** +// +// Define for efuse instruction +// +//***************************************************************************** +#define DUMPWORD_INSTR 0x04 + +//***************************************************************************** +// +// Define for FSM command execution +// +//***************************************************************************** +#define FLASH_CMD_EXEC 0x15 + +//***************************************************************************** +// +//! \brief Get size of a flash sector in number of bytes. +//! +//! This function will return the size of a flash sector in number of bytes. +//! +//! \return Returns size of a flash sector in number of bytes. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashSectorSizeGet(void) +{ + uint32_t ui32SectorSizeInKbyte; + + ui32SectorSizeInKbyte = (HWREG(FLASH_BASE + FLASH_O_FCFG_B0_SSIZE0) & + FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M) >> + FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S; + + // Return flash sector size in number of bytes. + return(ui32SectorSizeInKbyte * 1024); +} + +//***************************************************************************** +// +//! \brief Get the size of the flash. +//! +//! This function returns the size of the flash main bank in number of bytes. +//! +//! \return Returns the flash size in number of bytes. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashSizeGet(void) +{ + uint32_t ui32NoOfSectors; + + // Get number of flash sectors + ui32NoOfSectors = (HWREG(FLASH_BASE + FLASH_O_FLASH_SIZE) & + FLASH_FLASH_SIZE_SECTORS_M) >> + FLASH_FLASH_SIZE_SECTORS_S; + + // Return flash size in number of bytes + return(ui32NoOfSectors * FlashSectorSizeGet()); +} + +//***************************************************************************** +// +//! \brief Set power mode. +//! +//! This function will set the specified power mode. +//! +//! Any access to the bank causes a reload of the specified bank grace period +//! input value into the bank down counter. After the last access to the +//! flash bank, the down counter delays from 0 to 255 prescaled HCLK clock +//! cycles before putting the bank into one of the fallback power modes as +//! determined by \c ui32PowerMode. This value must be greater than 1 when the +//! fallback mode is not \ref FLASH_PWR_ACTIVE_MODE. +//! +//! Note: The prescaled clock used for the down counter is a clock divided by +//! 16 from input HCLK. The \c ui32BankGracePeriod parameter is ignored if +//! \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE. +//! Any access to flash memory causes the pump grace period down counter to +//! reload with value of \c ui32PumpGracePeriod. After the bank has gone to sleep, +//! the down counter delays this number of prescaled HCLK clock cycles before +//! entering one of the charge pump fallback power modes as determined by +//! \c ui32PowerMode. The prescaled clock used for the pump grace period down +//! counter is a clock divided by 16 from input HCLK. This parameter is ignored +//! if \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE. +//! +//! Changing the power mode of the flash module must be a part within a +//! device power mode transition requiring configuration of multiple modules. +//! Refer to documents describing the device power modes. +//! +//! \param ui32PowerMode is the wanted power mode. +//! The defined flash power modes are: +//! - \ref FLASH_PWR_ACTIVE_MODE +//! - \ref FLASH_PWR_OFF_MODE +//! - \ref FLASH_PWR_DEEP_STDBY_MODE +//! \param ui32BankGracePeriod is the starting count value for the bank grace +//! period down counter. +//! \param ui32PumpGracePeriod is the starting count value for the pump grace +//! period down counter. +//! +//! \return None +// +//***************************************************************************** +extern void FlashPowerModeSet(uint32_t ui32PowerMode, + uint32_t ui32BankGracePeriod, + uint32_t ui32PumpGracePeriod); + +//***************************************************************************** +// +//! \brief Get current configured power mode. +//! +//! This function will return the current configured power mode. +//! +//! \return Returns the current configured power mode. +//! The defined power modes are: +//! - \ref FLASH_PWR_ACTIVE_MODE +//! - \ref FLASH_PWR_OFF_MODE +//! - \ref FLASH_PWR_DEEP_STDBY_MODE +// +//***************************************************************************** +extern uint32_t FlashPowerModeGet(void); + +//***************************************************************************** +// +//! \brief Set sector protection. +//! +//! This function will set the specified protection on specified flash bank +//! sector. A sector can either have no protection or have write protection +//! which guards for both program and erase of that sector. +//! Sector protection can only be changed from \ref FLASH_NO_PROTECT to +//! \ref FLASH_WRITE_PROTECT! After write protecting a sector this sector can +//! only be set back to unprotected by a device reset. +//! +//! \param ui32SectorAddress is the start address of the sector to protect. +//! \param ui32ProtectMode is the enumerated sector protection mode. +//! - \ref FLASH_NO_PROTECT +//! - \ref FLASH_WRITE_PROTECT +//! +//! \return None +// +//***************************************************************************** +extern void FlashProtectionSet(uint32_t ui32SectorAddress, + uint32_t ui32ProtectMode); + +//***************************************************************************** +// +//! \brief Get sector protection. +//! +//! This return the protection mode for the specified flash bank sector. +//! +//! \param ui32SectorAddress is the start address of the desired sector. +//! +//! \return Returns the sector protection: +//! - \ref FLASH_NO_PROTECT +//! - \ref FLASH_WRITE_PROTECT +// +//***************************************************************************** +extern uint32_t FlashProtectionGet(uint32_t ui32SectorAddress); + +//***************************************************************************** +// +//! \brief Save sector protection to make it permanent. +//! +//! This function will save the current protection mode for the specified +//! flash bank sector. +//! +//! This function must only be executed from ROM or SRAM. +//! +//! \note A write protected sector will become permanent write +//! protected!! A device reset will not change the write protection! +//! +//! \param ui32SectorAddress is the start address of the sector to be protected. +//! +//! \return Returns the status of the sector protection: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_FSM_ERROR : An erase error is encountered. +// +//***************************************************************************** +extern uint32_t FlashProtectionSave(uint32_t ui32SectorAddress); + +//***************************************************************************** +// +//! \brief Checks if the Flash state machine has detected an error. +//! +//! This function returns the status of the Flash State Machine indicating if +//! an error is detected or not. Primary use is to check if an Erase or +//! Program operation has failed. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. This function must be called from ROM or +//! SRAM while any part of the flash is being programmed or erased. +//! +//! \return Returns status of Flash state machine: +//! - \ref FAPI_STATUS_FSM_ERROR +//! - \ref FAPI_STATUS_SUCCESS +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashCheckFsmForError(void) +{ + if(HWREG(FLASH_BASE + FLASH_O_FMSTAT) & FLASH_FMSTAT_CSTAT) + { + return(FAPI_STATUS_FSM_ERROR); + } + else + { + return(FAPI_STATUS_SUCCESS); + } +} + +//***************************************************************************** +// +//! \brief Checks if the Flash state machine is ready. +//! +//! This function returns the status of the Flash State Machine indicating if +//! it is ready to accept a new command or not. Primary use is to check if an +//! Erase or Program operation has finished. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. This function must be called from ROM or +//! SRAMh while any part of the flash is being programmed or erased. +//! +//! \return Returns readiness status of Flash state machine: +//! - \ref FAPI_STATUS_FSM_READY +//! - \ref FAPI_STATUS_FSM_BUSY +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashCheckFsmForReady(void) +{ + if(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_BUSY) + { + return(FAPI_STATUS_FSM_BUSY); + } + else + { + return(FAPI_STATUS_FSM_READY); + } +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the flash interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific FLASH interrupts must be enabled via \ref FlashIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the flash +//! interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_FLASH, pfnHandler); + + // Enable the flash interrupt. + IntEnable(INT_FLASH); +} + +//***************************************************************************** +// +//! \brief Unregisters the interrupt handler for the flash interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a FLASH interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntUnregister(void) +{ + // Disable the interrupts. + IntDisable(INT_FLASH); + + // Unregister the interrupt handler. + IntUnregister(INT_FLASH); +} + +//***************************************************************************** +// +//! \brief Enables flash controller interrupt sources. +//! +//! This function enables the flash controller interrupt sources. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt. +//! - \ref FLASH_INT_RV : Read verify error interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntEnable(uint32_t ui32IntFlags) +{ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= ui32IntFlags; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \brief Disables individual flash controller interrupt sources. +//! +//! This function disables the flash controller interrupt sources. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt. +//! - \ref FLASH_INT_RV : Read verify error interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntDisable(uint32_t ui32IntFlags) +{ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~ui32IntFlags; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the Flash. +//! +//! \return Returns the current interrupt status as values described in +//! \ref FlashIntEnable(). +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashIntStatus(void) +{ + uint32_t ui32IntFlags; + + ui32IntFlags = 0; + + // Check if FSM_DONE interrupt status is set. + if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_FSM_DONE) + { + ui32IntFlags = FLASH_INT_FSM_DONE; + } + + // Check if RVF_INT interrupt status is set. + if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_RVF_INT) + { + ui32IntFlags |= FLASH_INT_RV; + } + + return(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Clears flash controller interrupt source. +//! +//! The flash controller interrupt source is cleared, so that it no longer +//! asserts. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared. +//! Can be any of: +//! - \ref FLASH_INT_FSM_DONE +//! - \ref FLASH_INT_RV +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntClear(uint32_t ui32IntFlags) +{ + uint32_t ui32TempVal; + + ui32TempVal = 0; + + if(ui32IntFlags & FLASH_INT_FSM_DONE) + { + ui32TempVal = FLASH_FEDACSTAT_FSM_DONE; + } + + if(ui32IntFlags & FLASH_INT_RV) + { + ui32TempVal |= FLASH_FEDACSTAT_RVF_INT; + } + + // Clear the flash interrupt source. + HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) = ui32TempVal; +} + +//***************************************************************************** +// +//! \brief Erase a flash sector. +//! +//! This function will erase the specified flash sector. The function will +//! not return until the flash sector has been erased or an error condition +//! occurred. If flash top sector is erased the function will program the +//! the device security data bytes with default values. The device security +//! data located in the customer configuration area of the flash top sector, +//! must have valid values at all times. These values affect the configuration +//! of the device during boot. +//! +//! \warning Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. The application must disable interrupts that have +//! interrupt routines in flash. This function calls a ROM function which handles the +//! actual program operation. +//! +//! \param ui32SectorAddress is the starting address in flash of the sector to be +//! erased. +//! +//! \return Returns the status of the sector erase: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Invalid argument. +//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered. +// +//***************************************************************************** +extern uint32_t FlashSectorErase(uint32_t ui32SectorAddress); + + +//***************************************************************************** +// +//! \brief Programs unprotected flash sectors in the main bank. +//! +//! This function programs a sequence of bytes into the on-chip flash. +//! Programming each location consists of the result of an AND operation +//! of the new data and the existing data; in other words bits that contain +//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed +//! to 1. Therefore, a byte can be programmed multiple times as long as these +//! rules are followed; if a program operation attempts to change a 0 bit to +//! a 1 bit, that bit will not have its value changed. +//! +//! This function does not return until the data has been programmed or a +//! programming error occurs. +//! +//! \note It is recommended to disable cache and line buffer before programming the +//! flash. Cache and line buffer are not automatically updated if a flash program +//! causes a mismatch between new flash content and old content in cache and +//! line buffer. Remember to enable cache and line buffer when the program +//! operation completes. See \ref VIMSModeSafeSet(), \ref VIMSLineBufDisable(), +//! and \ref VIMSLineBufEnable() for more information. +//! +//! \warning Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. The application must disable interrupts that have +//! interrupt routines in flash. This function calls a ROM function which handles the +//! actual program operation. +//! +//! The \c pui8DataBuffer pointer can not point to flash. +//! +//! \param pui8DataBuffer is a pointer to the data to be programmed. +//! \param ui32Address is the starting address in flash to be programmed. +//! \param ui32Count is the number of bytes to be programmed. +//! +//! \return Returns status of the flash programming: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Too many bytes were requested. +//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered. +// +//***************************************************************************** +extern uint32_t FlashProgram(uint8_t *pui8DataBuffer, + uint32_t ui32Address, uint32_t ui32Count); + +//***************************************************************************** +// +//! \brief Reads efuse data from specified row. +//! +//! This function will read one efuse row. +//! It is assumed that any previous efuse operation has finished. +//! +//! \param pui32EfuseData is pointer to variable to be updated with efuse data. +//! \param ui32RowAddress is the efuse row number to be read. First row is row +//! number 0. +//! +//! \return Returns the status of the efuse read operation. +//! - \c false : OK status. +//! - \c true : Error status +// +//***************************************************************************** +extern bool FlashEfuseReadRow(uint32_t *pui32EfuseData, + uint32_t ui32RowAddress); + +//***************************************************************************** +// +//! \brief Disables all sectors for erase and programming on the active bank. +//! +//! This function disables all sectors for erase and programming on the active +//! bank and enables the Idle Reading Power reduction mode if no low power +//! mode is configured. Furthermore, an additional level of protection from +//! erase is enabled. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. +//! +//! \return None +// +//***************************************************************************** +extern void FlashDisableSectorsForWrite(void); + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_FlashPowerModeSet + #undef FlashPowerModeSet + #define FlashPowerModeSet ROM_FlashPowerModeSet + #endif + #ifdef ROM_FlashPowerModeGet + #undef FlashPowerModeGet + #define FlashPowerModeGet ROM_FlashPowerModeGet + #endif + #ifdef ROM_FlashProtectionSet + #undef FlashProtectionSet + #define FlashProtectionSet ROM_FlashProtectionSet + #endif + #ifdef ROM_FlashProtectionGet + #undef FlashProtectionGet + #define FlashProtectionGet ROM_FlashProtectionGet + #endif + #ifdef ROM_FlashProtectionSave + #undef FlashProtectionSave + #define FlashProtectionSave ROM_FlashProtectionSave + #endif + #ifdef ROM_FlashSectorErase + #undef FlashSectorErase + #define FlashSectorErase ROM_FlashSectorErase + #endif + #ifdef ROM_FlashProgram + #undef FlashProgram + #define FlashProgram ROM_FlashProgram + #endif + #ifdef ROM_FlashEfuseReadRow + #undef FlashEfuseReadRow + #define FlashEfuseReadRow ROM_FlashEfuseReadRow + #endif + #ifdef ROM_FlashDisableSectorsForWrite + #undef FlashDisableSectorsForWrite + #define FlashDisableSectorsForWrite ROM_FlashDisableSectorsForWrite + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio.c new file mode 100644 index 0000000..fcc316a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: gpio.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the GPIO +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "gpio.h" + +// see gpio.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio.h new file mode 100644 index 0000000..9a4bf16 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio.h @@ -0,0 +1,643 @@ +/****************************************************************************** +* Filename: gpio.h +* Revised: 2018-05-02 11:11:40 +0200 (Wed, 02 May 2018) +* Revision: 51951 +* +* Description: Defines and prototypes for the GPIO. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup gpio_api +//! @{ +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_gpio.h" +#include "debug.h" + +//***************************************************************************** +// +// Check for legal range of variable dioNumber +// +//***************************************************************************** +#ifdef DRIVERLIB_DEBUG +#include "../inc/hw_fcfg1.h" +#include "chipinfo.h" + +static bool +dioNumberLegal( uint32_t dioNumber ) +{ + uint32_t ioCount = + (( HWREG( FCFG1_BASE + FCFG1_O_IOCONF ) & + FCFG1_IOCONF_GPIO_CNT_M ) >> + FCFG1_IOCONF_GPIO_CNT_S ) ; + + // CC13x2 + CC26x2 + if ( ChipInfo_ChipFamilyIs_CC13x2_CC26x2() ) + { + return ( (dioNumber >= (31 - ioCount)) && (dioNumber < 31) ) + } + // Special handling of CC13x0 7x7, where IO_CNT = 30 and legal range is 1..30 + // for all other chips legal range is 0..(dioNumber-1) + else if (( ioCount == 30 ) && ChipInfo_ChipFamilyIs_CC13x0() ) + { + return (( dioNumber > 0 ) && ( dioNumber <= ioCount )); + } + else + { + return ( dioNumber < ioCount ); + } + +} +#endif + +//***************************************************************************** +// +// The following values define the bit field for the GPIO DIOs. +// +//***************************************************************************** +#define GPIO_DIO_0_MASK 0x00000001 // GPIO DIO 0 mask +#define GPIO_DIO_1_MASK 0x00000002 // GPIO DIO 1 mask +#define GPIO_DIO_2_MASK 0x00000004 // GPIO DIO 2 mask +#define GPIO_DIO_3_MASK 0x00000008 // GPIO DIO 3 mask +#define GPIO_DIO_4_MASK 0x00000010 // GPIO DIO 4 mask +#define GPIO_DIO_5_MASK 0x00000020 // GPIO DIO 5 mask +#define GPIO_DIO_6_MASK 0x00000040 // GPIO DIO 6 mask +#define GPIO_DIO_7_MASK 0x00000080 // GPIO DIO 7 mask +#define GPIO_DIO_8_MASK 0x00000100 // GPIO DIO 8 mask +#define GPIO_DIO_9_MASK 0x00000200 // GPIO DIO 9 mask +#define GPIO_DIO_10_MASK 0x00000400 // GPIO DIO 10 mask +#define GPIO_DIO_11_MASK 0x00000800 // GPIO DIO 11 mask +#define GPIO_DIO_12_MASK 0x00001000 // GPIO DIO 12 mask +#define GPIO_DIO_13_MASK 0x00002000 // GPIO DIO 13 mask +#define GPIO_DIO_14_MASK 0x00004000 // GPIO DIO 14 mask +#define GPIO_DIO_15_MASK 0x00008000 // GPIO DIO 15 mask +#define GPIO_DIO_16_MASK 0x00010000 // GPIO DIO 16 mask +#define GPIO_DIO_17_MASK 0x00020000 // GPIO DIO 17 mask +#define GPIO_DIO_18_MASK 0x00040000 // GPIO DIO 18 mask +#define GPIO_DIO_19_MASK 0x00080000 // GPIO DIO 19 mask +#define GPIO_DIO_20_MASK 0x00100000 // GPIO DIO 20 mask +#define GPIO_DIO_21_MASK 0x00200000 // GPIO DIO 21 mask +#define GPIO_DIO_22_MASK 0x00400000 // GPIO DIO 22 mask +#define GPIO_DIO_23_MASK 0x00800000 // GPIO DIO 23 mask +#define GPIO_DIO_24_MASK 0x01000000 // GPIO DIO 24 mask +#define GPIO_DIO_25_MASK 0x02000000 // GPIO DIO 25 mask +#define GPIO_DIO_26_MASK 0x04000000 // GPIO DIO 26 mask +#define GPIO_DIO_27_MASK 0x08000000 // GPIO DIO 27 mask +#define GPIO_DIO_28_MASK 0x10000000 // GPIO DIO 28 mask +#define GPIO_DIO_29_MASK 0x20000000 // GPIO DIO 29 mask +#define GPIO_DIO_30_MASK 0x40000000 // GPIO DIO 30 mask +#define GPIO_DIO_31_MASK 0x80000000 // GPIO DIO 31 mask +#define GPIO_DIO_ALL_MASK 0xFFFFFFFF // GPIO all DIOs mask + +//***************************************************************************** +// +// Define constants that shall be passed as the outputEnableValue parameter to +// GPIO_setOutputEnableDio() and will be returned from the function +// GPIO_getOutputEnableDio(). +// +//***************************************************************************** +#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled +#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Reads a specific DIO. +//! +//! \param dioNumber specifies the DIO to read (0-31). +//! +//! \return Returns 0 or 1 reflecting the input value of the specified DIO. +//! +//! \sa \ref GPIO_readMultiDio(), \ref GPIO_writeDio(), \ref GPIO_writeMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_readDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Return the input value from the specified DIO. + return (( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) >> dioNumber ) & 1 ); +} + +//***************************************************************************** +// +//! \brief Reads the input value for the specified DIOs. +//! +//! This function returns the input value for multiple DIOs. +//! The value returned is not shifted and hence matches the corresponding dioMask bits. +//! +//! \param dioMask is the bit-mask representation of the DIOs to read. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return Returns a bit vector reflecting the input value of the corresponding DIOs. +//! - 0 : Corresponding DIO is low. +//! - 1 : Corresponding DIO is high. +//! +//! \sa \ref GPIO_readDio(), \ref GPIO_writeDio(), \ref GPIO_writeMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_readMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Return the input value from the specified DIOs. + return ( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) & dioMask ); +} + +//***************************************************************************** +// +//! \brief Writes a value to a specific DIO. +//! +//! \param dioNumber specifies the DIO to update (0-31). +//! \param value specifies the value to write +//! - 0 : Logic zero (low) +//! - 1 : Logic one (high) +//! +//! \return None +//! +//! \sa \ref GPIO_writeMultiDio(), \ref GPIO_readDio(), \ref GPIO_readMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_writeDio( uint32_t dioNumber, uint32_t value ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + ASSERT(( value == 0 ) || ( value == 1 )); + + // Write 0 or 1 to the byte indexed DOUT map + HWREGB( GPIO_BASE + dioNumber ) = value; +} + +//***************************************************************************** +// +//! \brief Writes masked data to the specified DIOs. +//! +//! Enables for writing multiple bits simultaneously. +//! The value to write must be shifted so it matches the corresponding dioMask bits. +//! +//! \note Note that this is a read-modify-write operation and hence not atomic. +//! +//! \param dioMask is the bit-mask representation of the DIOs to write. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! \param bitVectoredValue holds the value to be written to the corresponding DIO-bits. +//! +//! \return None +//! +//! \sa \ref GPIO_writeDio(), \ref GPIO_readDio(), \ref GPIO_readMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_writeMultiDio( uint32_t dioMask, uint32_t bitVectoredValue ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) = + ( HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) & ~dioMask ) | + ( bitVectoredValue & dioMask ); +} + +//***************************************************************************** +// +//! \brief Sets a specific DIO to 1 (high). +//! +//! \param dioNumber specifies the DIO to set (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_setMultiDio(), \ref GPIO_clearDio(), \ref GPIO_clearMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Set the specified DIO. + HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +//! \brief Sets the specified DIOs to 1 (high). +//! +//! \param dioMask is the bit-mask representation of the DIOs to set. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return None +//! +//! \sa \ref GPIO_setDio(), \ref GPIO_clearDio(), \ref GPIO_clearMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Set the DIOs. + HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = dioMask; +} + +//***************************************************************************** +// +//! \brief Clears a specific DIO to 0 (low). +//! +//! \param dioNumber specifies the DIO to clear (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_clearMultiDio(), \ref GPIO_setDio(), \ref GPIO_setMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Clear the specified DIO. + HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +//! \brief Clears the specified DIOs to 0 (low). +//! +//! \param dioMask is the bit-mask representation of the DIOs to clear. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return None +//! +//! \sa \ref GPIO_clearDio(), \ref GPIO_setDio(), \ref GPIO_setMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Clear the DIOs. + HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = dioMask; +} + +//***************************************************************************** +// +//! \brief Toggles a specific DIO. +//! +//! \param dioNumber specifies the DIO to toggle (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_toggleMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_toggleDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Toggle the specified DIO. + HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +//! \brief Toggles the specified DIOs. +//! +//! \param dioMask is the bit-mask representation of the DIOs to toggle. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return None +//! +//! \sa \ref GPIO_toggleDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_toggleMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Toggle the DIOs. + HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = dioMask; +} + +//***************************************************************************** +// +//! \brief Gets the output enable status of a specific DIO. +//! +//! This function returns the output enable status for the specified DIO. +//! The DIO can be configured as either input or output under software control. +//! +//! \param dioNumber specifies the DIO to get the output enable setting from (0-31). +//! +//! \return Returns one of the enumerated data types (0 or 1): +//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled. +//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled. +//! +//! \sa \ref GPIO_getOutputEnableMultiDio(), \ref GPIO_setOutputEnableDio(), \ref GPIO_setOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getOutputEnableDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Return the output enable status for the specified DIO. + return (( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) >> dioNumber ) & 1 ); +} + +//***************************************************************************** +// +//! \brief Gets the output enable setting of the specified DIOs. +//! +//! This function returns the output enable setting for multiple DIOs. +//! The value returned is not shifted and hence matches the corresponding dioMask bits. +//! +//! \param dioMask is the bit-mask representation of the DIOs to return the output enable settings from. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return Returns the output enable setting for multiple DIOs as a bit vector corresponding to the dioMask bits. +//! - 0 : Corresponding DIO is configured with output disabled. +//! - 1 : Corresponding DIO is configured with output enabled. +//! +//! \sa \ref GPIO_getOutputEnableDio(), \ref GPIO_setOutputEnableDio(), \ref GPIO_setOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getOutputEnableMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Return the output enable value for the specified DIOs. + return ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & dioMask ); +} + +//***************************************************************************** +// +//! \brief Sets output enable of a specific DIO. +//! +//! This function sets the GPIO output enable bit for the specified DIO. +//! The DIO can be configured as either input or output under software control. +//! +//! \param dioNumber specifies the DIO to configure (0-31). +//! \param outputEnableValue specifies the output enable setting of the specified DIO: +//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled. +//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled. +//! +//! \return None +//! +//! \sa \ref GPIO_setOutputEnableMultiDio(), \ref GPIO_getOutputEnableDio(), \ref GPIO_getOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setOutputEnableDio( uint32_t dioNumber, uint32_t outputEnableValue ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + ASSERT(( outputEnableValue == GPIO_OUTPUT_DISABLE ) || + ( outputEnableValue == GPIO_OUTPUT_ENABLE ) ); + + // Update the output enable bit for the specified DIO. + HWREGBITW( GPIO_BASE + GPIO_O_DOE31_0, dioNumber ) = outputEnableValue; +} + +//***************************************************************************** +// +//! \brief Configures the output enable setting for all specified DIOs. +//! +//! This function configures the output enable setting for the specified DIOs. +//! The output enable setting must be shifted so it matches the corresponding dioMask bits. +//! The DIOs can be configured as either an input or output under software control. +//! +//! \note Note that this is a read-modify-write operation and hence not atomic. +//! +//! \param dioMask is the bit-mask representation of the DIOs on which to configure the +//! output enable setting. The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! \param bitVectoredOutputEnable holds the output enable setting the corresponding DIO-bits: +//! - 0 : Corresponding DIO is configured with output disabled. +//! - 1 : Corresponding DIO is configured with output enabled. +//! +//! \return None +//! +//! \sa \ref GPIO_setOutputEnableDio(), \ref GPIO_getOutputEnableDio(), \ref GPIO_getOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setOutputEnableMultiDio( uint32_t dioMask, uint32_t bitVectoredOutputEnable ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) = + ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & ~dioMask ) | + ( bitVectoredOutputEnable & dioMask ); +} + +//***************************************************************************** +// +//! \brief Gets the event status of a specific DIO. +//! +//! \param dioNumber specifies the DIO to get the event status from (0-31). +//! +//! \return Returns the current event status on the specified DIO. +//! - 0 : Non-triggered event. +//! - 1 : Triggered event. +//! +//! \sa \ref GPIO_getEventMultiDio(), \ref GPIO_clearEventDio(), \ref GPIO_clearEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getEventDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Return the event status for the specified DIO. + return (( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) >> dioNumber ) & 1 ); +} + +//***************************************************************************** +// +//! \brief Gets the event status of the specified DIOs. +//! +//! This function returns the event status for multiple DIOs. +//! The value returned is not shifted and hence matches the corresponding dioMask bits. +//! +//! \param dioMask is the bit-mask representation of the DIOs to get the +//! event status from (0-31). +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return Returns a bit vector with the current event status corresponding to the specified DIOs. +//! - 0 : Corresponding DIO has no triggered event. +//! - 1 : Corresponding DIO has a triggered event. +//! +//! \sa \ref GPIO_getEventDio(), \ref GPIO_clearEventDio(), \ref GPIO_clearEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getEventMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Return the event status for the specified DIO. + return ( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) & dioMask ); +} + +//***************************************************************************** +// +//! \brief Clears the IO event status of a specific DIO. +//! +//! \param dioNumber specifies the DIO on which to clear the event status (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_clearEventMultiDio(), \ref GPIO_getEventDio(), \ref GPIO_getEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearEventDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Clear the event status for the specified DIO. + HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +//! \brief Clears the IO event status on the specified DIOs. +//! +//! \param dioMask is the bit-mask representation of the DIOs on which to +//! clear the events status. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return None +//! +//! \sa \ref GPIO_clearEventDio(), \ref GPIO_getEventDio(), \ref GPIO_getEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearEventMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Clear the event status for the specified DIOs. + HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = dioMask; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio_doc.h new file mode 100644 index 0000000..b4548af --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio_doc.h @@ -0,0 +1,90 @@ +/****************************************************************************** +* Filename: gpio_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup gpio_api +//! @{ +//! \section sec_gpio Introduction +//! +//! The GPIO module allows software to control the pins of the device directly if the IOC module has +//! been configured to route the GPIO signal to a physical pin (called DIO). Alternatively, pins can +//! be hardware controlled by other peripheral modules. For more information about the IOC module, +//! how to configure physical pins, and how to select between software controlled and hardware controlled, +//! see the [IOC API](\ref ioc_api). +//! +//! The System CPU can access the GPIO module to read the value of any DIO of the device and if the IOC +//! module has been configured such that one or more DIOs are GPIO controlled (software controlled) the +//! System CPU can write these DIOs through the GPIO module. +//! +//! The IOC module can also be configured to generate events on edge detection and these events can be +//! read and cleared in the GPIO module by the System CPU. +//! +//! \section sec_gpio_api API +//! +//! The API functions can be grouped like this: +//! +//! Set and get direction of DIO (output enable): +//! - \ref GPIO_setOutputEnableDio() +//! - \ref GPIO_setOutputEnableMultiDio() +//! - \ref GPIO_getOutputEnableDio() +//! - \ref GPIO_getOutputEnableMultiDio() +//! +//! Write DIO (requires IOC to be configured for GPIO usage): +//! - \ref GPIO_writeDio() +//! - \ref GPIO_writeMultiDio() +//! +//! Set, clear, or toggle DIO (requires IOC to be configured for GPIO usage): +//! - \ref GPIO_setDio() +//! - \ref GPIO_setMultiDio() +//! - \ref GPIO_clearDio() +//! - \ref GPIO_clearMultiDio() +//! - \ref GPIO_toggleDio() +//! - \ref GPIO_toggleMultiDio() +//! +//! Read DIO (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC): +//! - \ref GPIO_readDio() +//! - \ref GPIO_readMultiDio() +//! +//! Read or clear events (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC): +//! - \ref GPIO_getEventDio() +//! - \ref GPIO_getEventMultiDio() +//! - \ref GPIO_clearEventDio() +//! - \ref GPIO_clearEventMultiDio() +//! +//! The [IOC API](\ref ioc_api) provides two functions for easy configuration of DIOs as GPIO enabled using +//! typical settings. They also serve as examples on how to configure the IOC and GPIO modules for GPIO usage: +//! - \ref IOCPinTypeGpioInput() +//! - \ref IOCPinTypeGpioOutput() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_analog_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_analog_doc.h new file mode 100644 index 0000000..d6346b3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_analog_doc.h @@ -0,0 +1,107 @@ +/****************************************************************************** +* Filename: group_analog_doc.h +* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) +* Revision: 47080 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup analog_group +//! @{ +//! \section sec_analog Introduction +//! +//! Access to registers in the analog domain of the device goes through master modules controlling slave +//! modules which contain the actual registers. The master module is located in the digital domain of the +//! device. The interfaces between master and slave modules are called ADI (Analog-to-Digital Interface) +//! and DDI (Digital-to-Digital Interface) depending on the type of module to access and thus the slave +//! modules are referred to as ADI slave and DDI slave. +//! +//! The ADI and DDI APIs provide access to these registers: +//! - ADI_2_REFSYS : Reference System for generating reference voltages and reference currents. +//! - Reference system control +//! - SOC LDO control +//! - ADI_3_REFSYS : Reference System for generating reference voltages and reference currents. +//! - Reference system control +//! - DC/DC control +//! - ADI_4_AUX : Controlling analog peripherals of AUX. +//! - Multiplexers +//! - Current source +//! - Comparators +//! - ADCs +//! - DDI_0_OSC : Controlling the oscillators (via AUX domain) +//! +//! The register descriptions of CPU memory map document the ADI/DDI masters. The register descriptions of +//! analog memory map document the ADI/DDI slaves. The ADI/DDI APIs allow the programmer to focus on the +//! slave registers of interest without being concerned with the ADI/DDI master part of the interface. +//! +//! Although the ADI/DDI APIs make the master "transparent" it can be useful to know a few details about +//! the ADI/DDI protocol and how the master handles transactions as it can affect how the system CPU performs. +//! - ADI protocol uses 8-bit write bus compared to 32-bit write bus in DDI. ADI protocol uses 4-bit read +//! bus compared to 16-bit read bus in DDI. Hence a 32-bit read from an ADI register is translated into 8 +//! transactions in the ADI protocol. +//! - One transaction on the ADI/DDI protocol takes several clock cycles for the master to complete. +//! - Access to AUX ADI/DDI requires use of a semaphore. This is handled automatically by DriverLib which uses +//! \ref AuxAdiDdiSafeWrite() and \ref AuxAdiDdiSafeRead() whenever AUX is accessed. +//! - ADI slave registers are 8-bit wide. +//! - DDI slave registers are 32-bit wide. +//! - ADI/DDI master supports multiple data width accesses seen from the system CPU +//! (however, not all bit width accesses are supported by the APIs): +//! - Read: 8, 16, 32-bit +//! - Write +//! - Direct (write, set, clear): 8, 16, 32-bit +//! - Masked: 4, 8, 16-bit +//! +//! Making posted/buffered writes from the system CPU (default) to the ADI/DDI allows the system CPU to continue +//! while the ADI/DDI master handles the transactions on the ADI/DDI protocol. If using non-posted/non-buffered +//! writes the system CPU will wait for ADI/DDI master to complete the transactions to the slave before continuing +//! execution. +//! +//! Reading from ADI/DDI requires that all transactions on the ADI/DDI protocol have completed before the system CPU +//! receives the response thus the programmer must understand that the response time depends on the number of bytes +//! read. However, due to the 'set', 'clear' and 'masked write' features of the ADI/DDI most writes can be done +//! without the typical read-modify-write sequence thus reducing the need for reads to a minimum. +//! +//! Consequently, if making posted/buffered writes then the written value will not take effect in the +//! analog domain until some point later in time. An alternative to non-posted/non-buffered writes - in order to make +//! sure a written value has taken effect - is to read from the same ADI/DDI as the write as this will keep the system CPU +//! waiting until both the write and the read have completed. +//! +//! \note +//! Do NOT use masked write when writing bit fields spanning the "masked write boundary" i.e. the widest possible +//! masked write that the protocol supports (ADI = 4 bits, DDI = 16 bits). This will put the device into a +//! temporary state - which is potentially harmful to the device - as the bit field will be written over two transactions. +//! Thus to use masked writes: +//! - For ADI the bit field(s) must be within bit 0 to 3 (REG[3:0]) or bit 4 to 7 (REG[7:4]). +//! - For DDI the bit field(s) must be within bit 0 to 15 (REG[15:0]) or bit 16 to 31 (REG[31:16]). +//! +//! \note +//! If masked write is not allowed, a regular read-modify-write is necessary. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aon_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aon_doc.h new file mode 100644 index 0000000..c5056d9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aon_doc.h @@ -0,0 +1,76 @@ +/****************************************************************************** +* Filename: group_aon_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aon_group +//! @{ +//! \section sec_aon Introduction +//! +//! The Always-ON (AON) voltage domain contains the AUX power domain, AON power domain, and JTAG power domain. +//! The AON API includes functions to access the AON power domain. For functions accessing the AUX power domain +//! see the [AUX API](@ref aux_group). +//! +//! The AON power domain contains circuitry that is always enabled, except for the shutdown mode +//! (digital supply is off), and the AON power domain is clocked at 32-kHz. +//! +//! The AON API accesses the AON registers through a common module called AON Interface (AON IF) which handles the +//! actual transactions towards the much slower AON registers. Because accessing AON can cause a significant +//! delay in terms of system CPU clock cycles it is important to understand the basics about how the AON IF +//! operates. The following list describes a few of the most relevant properties of the AON IF seen from the system CPU: +//! - \ti_bold{Shadow registers}: The system CPU actually accesses a set of "shadow registers" which are being synchronized to the AON registers +//! by the AON IF every AON clock cycle. +//! - Writing an AON register via AON IF can take up to one AON clock cycle before taking effect in the AON domain. However, the system CPU can +//! continue executing without waiting for this. +//! - The AON IF supports multiple writes within the same AON clock cycle thus several registers/bit fields can be synchronized simultaneously. +//! - Reading from AON IF returns the value from last time the shadow registers were synchronized (if no writes to AON IF have occurred since) +//! thus the value can be up to one AON clock cycle old. +//! - Reading from AON IF after a write (but before synchronization has happened) will return the value from the shadow register +//! and not the last value from the AON register. Thus doing multiple read-modify-writes within one AON clock cycle is supported. +//! - \ti_bold{Read delay}: Due to an asynchronous interface to the AON IF, reading AON registers will generate a few wait cycles thus stalling +//! the system CPU until the read completes. There is no delay on writes to AON IF if using posted/buffered writes. +//! - \ti_bold{Synchronizing}: If it is required that a write to AON takes effect before continuing code execution it is possible to do a conditional "wait for +//! synchronization" by calling \ref SysCtrlAonSync(). This will wait for any pending writes to synchronize. +//! - \ti_bold{Updating}: It is also possible to do an unconditional "wait for synchronization", in case a new read +//! value is required, by calling \ref SysCtrlAonUpdate(). This is typically used after wake-up to make sure the AON IF has been +//! synchronized at least once before reading the values. +//! +//! Below are a few guidelines to write efficient code for AON access based on the properties of the interface to the AON registers. +//! - Avoid synchronizing unless required by the application. If synchronization is needed then try to group/arrange AON writes to +//! minimize the number of required synchronizations. +//! - If modifying several bit fields within a single AON register it is slightly faster to do a single read, modify the bit fields, +//! and then write it back rather than doing multiple independent read-modify-writes (due to the read delay). +//! - Using posted/buffered writes to AON (default) lets the system CPU continue execution immediately. Using non-posted/non-buffered +//! writes will generate a delay similar to a read access. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aux_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aux_doc.h new file mode 100644 index 0000000..63ddcfd --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aux_doc.h @@ -0,0 +1,58 @@ +/****************************************************************************** +* Filename: group_aux_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aux_group +//! @{ +//! \section sec_aux Introduction +//! +//! The AUX is a collective description of all the analog peripherals (ADC, comparators, and current source) and +//! the digital modules in the AUX power domain (AUX_PD) such as the sensor controller, timers, time-to-digital +//! converter, etc. AUX_PD is located within the AON voltage domain of the device. +//! +//! The sensor controller has the ability to +//! do its own power and clock management of AUX_PD, independently of the MCU domain. The sensor +//! controller can also continue doing tasks while the MCU subsystem is powered down, but with limited +//! resources compared to the larger MCU domain. +//! +//! The AUX power domain is connected to the MCU system through an asynchronous interface, ensuring +//! that all modules connected to the AUX bus are accessible from the system CPU. +//! Accessing the analog peripherals from the system CPU must be done by using TI-provided +//! drivers to ensure proper control of power management. +//! +//! \note To ease development of program code running on the sensor controller, TI provides a tool +//! chain for writing software for the controller, Sensor Controller Studio (SCS), which is a fully +//! integrated tool consisting of an IDE, compiler, assembler, and linker. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c.c new file mode 100644 index 0000000..0b52735 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c.c @@ -0,0 +1,172 @@ +/****************************************************************************** +* Filename: i2c.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the I2C module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "i2c.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef I2CMasterInitExpClk + #define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk + #undef I2CMasterErr + #define I2CMasterErr NOROM_I2CMasterErr + #undef I2CIntRegister + #define I2CIntRegister NOROM_I2CIntRegister + #undef I2CIntUnregister + #define I2CIntUnregister NOROM_I2CIntUnregister +#endif + +//***************************************************************************** +// +// Initializes the I2C Master block +// +//***************************************************************************** +void +I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast) +{ + uint32_t ui32SCLFreq; + uint32_t ui32TPR; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Must enable the device before doing anything else. + I2CMasterEnable(I2C0_BASE); + + // Get the desired SCL speed. + if(bFast == true) + { + ui32SCLFreq = 400000; + } + else + { + ui32SCLFreq = 100000; + } + + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biased to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / (2 * 10 * ui32SCLFreq)) - 1; + HWREG(I2C0_BASE + I2C_O_MTPR) = ui32TPR; +} + +//***************************************************************************** +// +// Gets the error status of the I2C Master module +// +//***************************************************************************** +uint32_t +I2CMasterErr(uint32_t ui32Base) +{ + uint32_t ui32Err; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the raw error state. + ui32Err = HWREG(I2C0_BASE + I2C_O_MSTAT); + + // If the I2C master is busy, then all the other status bits are invalid, + // and there is no error to report. + if(ui32Err & I2C_MSTAT_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // Check for errors. + if(ui32Err & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST)) + { + return(ui32Err & (I2C_MSTAT_ARBLST | I2C_MSTAT_DATACK_N | I2C_MSTAT_ADRACK_N)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} + +//***************************************************************************** +// +// Registers an interrupt handler for the I2C module +// +//***************************************************************************** +void +I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the interrupt number. + ui32Int = INT_I2C_IRQ; + + // Register the interrupt handler, returning an error if an error occurs. + IntRegister(ui32Int, pfnHandler); + + // Enable the I2C interrupt. + IntEnable(ui32Int); +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for the I2C module +// +//***************************************************************************** +void +I2CIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the interrupt number. + ui32Int = INT_I2C_IRQ; + + // Disable the interrupt. + IntDisable(ui32Int); + + // Unregister the interrupt handler. + IntUnregister(ui32Int); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c.h new file mode 100644 index 0000000..d1e2969 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c.h @@ -0,0 +1,974 @@ +/****************************************************************************** +* Filename: i2c.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and prototypes for the I2C. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup i2c_api +//! @{ +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_i2c.h" +#include "../inc/hw_sysctl.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk + #define I2CMasterErr NOROM_I2CMasterErr + #define I2CIntRegister NOROM_I2CIntRegister + #define I2CIntUnregister NOROM_I2CIntUnregister +#endif + +//***************************************************************************** +// +// I2C Master commands +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START \ + 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 + +//***************************************************************************** +// +// I2C Master error status +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte + +//***************************************************************************** +// +// I2C Slave interrupts +// +//***************************************************************************** +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an I2C base address. +//! +//! This function determines if a I2C port base address is valid. +//! +//! \param ui32Base is the base address of the I2C port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise +// +//***************************************************************************** +static bool +I2CBaseValid(uint32_t ui32Base) +{ + return(ui32Base == I2C0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Initializes the I2C Master block. +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master, and will have enabled the I2C Master block. +//! +//! If the parameter \c bFast is \c true, then the master block will be set up +//! to transfer data at 400 kbps; otherwise, it will be set up to transfer data +//! at 100 kbps. +//! +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32I2CClk is the rate of the clock supplied to the I2C module. +//! \param bFast set up for fast data transfers. +//! +//! \return None +// +//***************************************************************************** +extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast); + +//***************************************************************************** +// +//! \brief Controls the state of the I2C Master module. +//! +//! This function is used to control the state of the Master module send and +//! receive operations. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32Cmd is the command to be issued by the I2C Master module +//! The parameter can be one of the following values: +//! - \ref I2C_MASTER_CMD_SINGLE_SEND +//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE +//! - \ref I2C_MASTER_CMD_BURST_SEND_START +//! - \ref I2C_MASTER_CMD_BURST_SEND_CONT +//! - \ref I2C_MASTER_CMD_BURST_SEND_FINISH +//! - \ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) || + // (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || -> Equal to SINGLE_SEND + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP)); + + // Send the command. + HWREG(I2C0_BASE + I2C_O_MCTRL) = ui32Cmd; + + // Delay minimum four cycles in order to ensure that the I2C_O_MSTAT + // register has been correctly updated before function exit + CPUdelay(2); +} + +//***************************************************************************** +// +//! \brief Sets the address that the I2C Master will place on the bus. +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. When the \e bReceive parameter is set +//! to \b true, the address will indicate that the I2C Master is initiating a +//! read from the slave; otherwise the address will indicate that the I2C +//! Master is initiating a write to the slave. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8SlaveAddr is a 7-bit slave address +//! \param bReceive flag indicates the type of communication with the slave. +//! - \c true : I2C Master is initiating a read from the slave. +//! - \c false : I2C Master is initiating a write to the slave. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, + bool bReceive) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // Set the address of the slave with which the master will communicate. + HWREG(I2C0_BASE + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; +} + +//***************************************************************************** +// +//! \brief Enables the I2C Master block. +//! +//! This will enable operation of the I2C Master block. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Enable the clock for the master. + HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 1; + + // Enable the master block. + HWREG(I2C0_BASE + I2C_O_MCTRL) = I2C_MCTRL_RUN; +} + +//***************************************************************************** +// +//! \brief Disables the I2C master block. +//! +//! This will disable operation of the I2C master block. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Disable the master block. + HWREG(I2C0_BASE + I2C_O_MCTRL) = 0; + + // Disable the clock for the master. + HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C Master is busy. +//! +//! This function returns an indication of whether or not the I2C Master is +//! busy transmitting or receiving data. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns status of I2C Master: +//! - \c true : I2C Master is busy. +//! - \c false : I2C Master is not busy. +// +//***************************************************************************** +__STATIC_INLINE bool +I2CMasterBusy(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return the busy status. + if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C bus is busy. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function can be used in a multi-master environment to determine if +//! another master is currently using the bus. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns status of the I2C bus: +//! - \c true : I2C bus is busy. +//! - \c false : I2C bus is not busy. +// +//***************************************************************************** +__STATIC_INLINE bool +I2CMasterBusBusy(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return the bus busy status. + if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSBSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Master. +//! +//! This function reads a byte of data from the I2C Master Data Register. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns the byte received from by the I2C Master, cast as an +//! uint32_t. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CMasterDataGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Read a byte. + return(HWREG(I2C0_BASE + I2C_O_MDR)); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the I2C Master. +//! +//! This function will place the supplied data into I2C Master Data Register. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8Data is the data to be transmitted by the I2C Master +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Write the byte. + HWREG(I2C0_BASE + I2C_O_MDR) = ui8Data; +} + +//***************************************************************************** +// +//! \brief Gets the error status of the I2C Master module. +//! +//! This function is used to obtain the error status of the Master module send +//! and receive operations. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns the error status of the Master module: +//! - \ref I2C_MASTER_ERR_NONE +//! - \ref I2C_MASTER_ERR_ADDR_ACK +//! - \ref I2C_MASTER_ERR_DATA_ACK +//! - \ref I2C_MASTER_ERR_ARB_LOST +// +//***************************************************************************** +extern uint32_t I2CMasterErr(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables the I2C Master interrupt. +//! +//! Enables the I2C Master interrupt source. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterIntEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Enable the master interrupt. + HWREG(I2C0_BASE + I2C_O_MIMR) = I2C_MIMR_IM; +} + +//***************************************************************************** +// +//! \brief Disables the I2C Master interrupt. +//! +//! Disables the I2C Master interrupt source. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterIntDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Disable the master interrupt. + HWREG(I2C0_BASE + I2C_O_MIMR) = 0; +} + +//***************************************************************************** +// +//! \brief Clears I2C Master interrupt sources. +//! +//! The I2C Master interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterIntClear(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Clear the I2C master interrupt source. + HWREG(I2C0_BASE + I2C_O_MICR) = I2C_MICR_IC; +} + +//***************************************************************************** +// +//! \brief Gets the current I2C Master interrupt status. +//! +//! This returns the interrupt status for the I2C Master module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param bMasked selects either raw or masked interrupt status. +//! - \c false : Raw interrupt status is requested. +//! - \c true : Masked interrupt status is requested. +//! +//! \return Returns the current interrupt status. +//! - \c true : Active. +//! - \c false : Not active. +// +//***************************************************************************** +__STATIC_INLINE bool +I2CMasterIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return((HWREG(I2C0_BASE + I2C_O_MMIS)) ? true : false); + } + else + { + return((HWREG(I2C0_BASE + I2C_O_MRIS)) ? true : false); + } +} + +//***************************************************************************** +// +//! \brief Enables the I2C Slave block. +//! +//! This will enable operation of the I2C Slave block. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Enable the clock to the slave block. + HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 1; + + // Enable the slave. + HWREG(I2C0_BASE + I2C_O_SCTL) = I2C_SCTL_DA; +} + +//***************************************************************************** +// +//! \brief Initializes the I2C Slave block. +//! +//! This function initializes operation of the I2C Slave block. Upon +//! successful initialization of the I2C blocks, this function will have set +//! the slave address and have enabled the I2C Slave block. +//! +//! The parameter \c ui8SlaveAddr is the value that will be compared against the +//! slave address sent by an I2C master. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8SlaveAddr is the 7-bit slave address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // Must enable the device before doing anything else. + I2CSlaveEnable(I2C0_BASE); + + // Set up the slave address. + HWREG(I2C0_BASE + I2C_O_SOAR) = ui8SlaveAddr; +} + +//***************************************************************************** +// +//! \brief Sets the I2C slave address. +//! +//! This function writes the specified slave address. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8SlaveAddr is the 7-bit slave address +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8SlaveAddr) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // Set up the primary slave address. + HWREG(I2C0_BASE + I2C_O_SOAR) = ui8SlaveAddr; +} + +//***************************************************************************** +// +//! \brief Disables the I2C slave block. +//! +//! This will disable operation of the I2C slave block. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Disable the slave. + HWREG(I2C0_BASE + I2C_O_SCTL) = 0x0; + + // Disable the clock to the slave block. + HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Gets the I2C Slave module status. +//! +//! This function will return the action requested from a master, if any. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return Returns the status of the I2C Slave module: +//! - \ref I2C_SLAVE_ACT_NONE : No action has been requested of the I2C Slave module. +//! - \ref I2C_SLAVE_ACT_RREQ : An I2C master has sent data to the I2C Slave module. +//! - \ref I2C_SLAVE_ACT_TREQ : An I2C master has requested that the I2C Slave module send data. +//! - \ref I2C_SLAVE_ACT_RREQ_FBR : An I2C master has sent data to the I2C slave +//! and the first byte following the slave's own address has been received. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CSlaveStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return the slave status. + return(HWREG(I2C0_BASE + I2C_O_SSTAT)); +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Slave. +//! +//! This function reads a byte of data from the I2C Slave Data Register. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return Returns the byte received from by the I2C Slave, cast as an +//! uint32_t. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CSlaveDataGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Read a byte. + return(HWREG(I2C0_BASE + I2C_O_SDR)); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the I2C Slave. +//! +//! This function will place the supplied data into I2C Slave Data Register. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8Data data to be transmitted from the I2C Slave. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Write the byte. + HWREG(I2C0_BASE + I2C_O_SDR) = ui8Data; +} + +//***************************************************************************** +// +//! \brief Enables individual I2C Slave interrupt sources. +//! +//! Enables the indicated I2C Slave interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is the bit mask of the slave interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + uint32_t ui32Val; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START | + I2C_SLAVE_INT_DATA)); + + // Enable the slave interrupt. + ui32Val = HWREG(I2C0_BASE + I2C_O_SIMR); + ui32Val |= ui32IntFlags; + HWREG(I2C0_BASE + I2C_O_SIMR) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Disables individual I2C Slave interrupt sources. +//! +//! Disables the indicated I2C Slave interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + uint32_t ui32Val; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START | + I2C_SLAVE_INT_DATA)); + + // Disable the slave interrupt. + ui32Val = HWREG(I2C0_BASE + I2C_O_SIMR); + ui32Val &= ~ui32IntFlags; + HWREG(I2C0_BASE + I2C_O_SIMR) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Clears I2C Slave interrupt sources. +//! +//! The specified I2C Slave interrupt sources are cleared, so that they no +//! longer assert. This must be done in the interrupt handler to keep it from +//! being called again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Clear the I2C slave interrupt source. + HWREG(I2C0_BASE + I2C_O_SICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current I2C Slave interrupt status. +//! +//! This returns the interrupt status for the I2C Slave module. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param bMasked selects either raw or masked interrupt status. +//! - \c false : Raw interrupt status is requested. +//! - \c true : Masked interrupt status is requested. +//! +//! \return Returns the current interrupt status as an OR'ed combination of: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return(HWREG(I2C0_BASE + I2C_O_SMIS)); + } + else + { + return(HWREG(I2C0_BASE + I2C_O_SRIS)); + } +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the I2C module in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific I2C interrupts must be enabled via \ref I2CMasterIntEnable() and +//! \ref I2CSlaveIntEnable(). If necessary, it is the interrupt handler's +//! responsibility to clear the interrupt source via \ref I2CMasterIntClear() and +//! \ref I2CSlaveIntClear(). +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param pfnHandler is a pointer to the function to be called when the +//! I2C interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the I2C module in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when an I2C interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler no longer is called. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! \return None +//! +//! \sa \brief IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void I2CIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_I2CMasterInitExpClk + #undef I2CMasterInitExpClk + #define I2CMasterInitExpClk ROM_I2CMasterInitExpClk + #endif + #ifdef ROM_I2CMasterErr + #undef I2CMasterErr + #define I2CMasterErr ROM_I2CMasterErr + #endif + #ifdef ROM_I2CIntRegister + #undef I2CIntRegister + #define I2CIntRegister ROM_I2CIntRegister + #endif + #ifdef ROM_I2CIntUnregister + #undef I2CIntUnregister + #define I2CIntUnregister ROM_I2CIntUnregister + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c_doc.h new file mode 100644 index 0000000..c339318 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c_doc.h @@ -0,0 +1,162 @@ +/****************************************************************************** +* Filename: i2c_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup i2c_api +//! @{ +//! \section sec_i2c Introduction +//! +//! The Inter-Integrated Circuit (\i2c) API provides a set of functions for using +//! the \ti_device \i2c master and slave module. Functions are provided to perform +//! the following actions: +//! - Initialize the \i2c module. +//! - Send and receive data. +//! - Obtain status. +//! - Manage interrupts for the \i2c module. +//! +//! The \i2c master and slave module provide the ability to communicate to other IC +//! devices over an \i2c bus. The \i2c bus is specified to support devices that can +//! both transmit and receive (write and read) data. Also, devices on the \i2c bus +//! can be designated as either a master or a slave. The \ti_device \i2c module +//! supports both sending and receiving data as either a master or a slave, and also +//! support the simultaneous operation as both a master and a slave. Finally, the +//! \ti_device \i2c module can operate at two speeds: standard (100 kb/s) and fast +//! (400 kb/s). +//! +//! The master and slave \i2c module can generate interrupts. The \i2c master +//! module generates interrupts when a transmit or receive operation +//! completes (or aborts due to an error). +//! The \i2c slave module can generate interrupts when data is +//! sent or requested by a master and when a START or STOP condition is present. +//! +//! \section sec_i2c_master Master Operations +//! +//! When using this API to drive the \i2c master module, the user must first +//! initialize the \i2c master module with a call to \ref I2CMasterInitExpClk(). This +//! function sets the bus speed and enables the master module. +//! +//! The user may transmit or receive data after the successful initialization of +//! the \i2c master module. Data is transferred by first setting the slave address +//! using \ref I2CMasterSlaveAddrSet(). This function is also used to define whether +//! the transfer is a send (a write to the slave from the master) or a receive (a +//! read from the slave by the master). Then, if connected to an \i2c bus that has +//! multiple masters, the \ti_device \i2c master must first call \ref I2CMasterBusBusy() +//! before trying to initiate the desired transaction. After determining that +//! the bus is not busy, if trying to send data, the user must call the +//! \ref I2CMasterDataPut() function. The transaction can then be initiated on the bus +//! by calling the \ref I2CMasterControl() function with any of the following commands: +//! - \ref I2C_MASTER_CMD_SINGLE_SEND +//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE +//! - \ref I2C_MASTER_CMD_BURST_SEND_START +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START +//! +//! Any of these commands result in the master arbitrating for the bus, +//! driving the start sequence onto the bus, and sending the slave address and +//! direction bit across the bus. The remainder of the transaction can then be +//! driven using either a polling or interrupt-driven method. +//! +//! For the single send and receive cases, the polling method involves looping +//! on the return from \ref I2CMasterBusy(). Once the function indicates that the \i2c +//! master is no longer busy, the bus transaction is complete and can be +//! checked for errors using \ref I2CMasterErr(). If there are no errors, then the data +//! has been sent or is ready to be read using \ref I2CMasterDataGet(). For the burst +//! send and receive cases, the polling method also involves calling the +//! \ref I2CMasterControl() function for each byte transmitted or received +//! (using either the \ref I2C_MASTER_CMD_BURST_SEND_CONT or \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! commands), and for the last byte sent or received (using either the +//! \ref I2C_MASTER_CMD_BURST_SEND_FINISH or \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! commands). +//! +//! If any error is detected during the burst transfer, +//! the appropriate stop command (\ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP or +//! \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) should be used to call the +//! \ref I2CMasterControl() function. +//! +//! For the interrupt-driven transaction, the user must register an interrupt +//! handler for the \i2c devices and enable the \i2c master interrupt; the interrupt +//! occurs when the master is no longer busy. +//! +//! \section sec_i2c_slave Slave Operations +//! +//! When using this API to drive the \i2c slave module, the user must first +//! initialize the \i2c slave module with a call to \ref I2CSlaveInit(). This function +//! enables the \i2c slave module and initializes the address of the slave. After the +//! initialization completes, the user may poll the slave status using +//! \ref I2CSlaveStatus() to determine if a master requested a send or receive +//! operation. Depending on the type of operation requested, the user can call +//! \ref I2CSlaveDataPut() or \ref I2CSlaveDataGet() to complete the transaction. +//! Alternatively, the \i2c slave can handle transactions using an interrupt handler +//! registered with \ref I2CIntRegister(), and by enabling the \i2c slave interrupt. +//! +//! \section sec_i2c_api API +//! +//! The \i2c API is broken into three groups of functions: +//! those that handle status and initialization, those that +//! deal with sending and receiving data, and those that deal with +//! interrupts. +//! +//! Status and initialization functions for the \i2c module are: +//! - \ref I2CMasterInitExpClk() +//! - \ref I2CMasterEnable() +//! - \ref I2CMasterDisable() +//! - \ref I2CMasterBusBusy() +//! - \ref I2CMasterBusy() +//! - \ref I2CMasterErr() +//! - \ref I2CSlaveInit() +//! - \ref I2CSlaveEnable() +//! - \ref I2CSlaveDisable() +//! - \ref I2CSlaveStatus() +//! +//! Sending and receiving data from the \i2c module is handled by the following functions: +//! - \ref I2CMasterSlaveAddrSet() +//! - \ref I2CSlaveAddressSet() +//! - \ref I2CMasterControl() +//! - \ref I2CMasterDataGet() +//! - \ref I2CMasterDataPut() +//! - \ref I2CSlaveDataGet() +//! - \ref I2CSlaveDataPut() +//! +//! The \i2c master and slave interrupts are handled by the following functions: +//! - \ref I2CIntRegister() +//! - \ref I2CIntUnregister() +//! - \ref I2CMasterIntEnable() +//! - \ref I2CMasterIntDisable() +//! - \ref I2CMasterIntClear() +//! - \ref I2CMasterIntStatus() +//! - \ref I2CSlaveIntEnable() +//! - \ref I2CSlaveIntDisable() +//! - \ref I2CSlaveIntClear() +//! - \ref I2CSlaveIntStatus() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s.c new file mode 100644 index 0000000..55e935f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s.c @@ -0,0 +1,349 @@ +/****************************************************************************** +* Filename: i2s.c +* Revised: 2017-05-08 12:18:04 +0200 (Mon, 08 May 2017) +* Revision: 48924 +* +* Description: Driver for the I2S. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "i2s.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef I2SEnable + #define I2SEnable NOROM_I2SEnable + #undef I2SAudioFormatConfigure + #define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure + #undef I2SChannelConfigure + #define I2SChannelConfigure NOROM_I2SChannelConfigure + #undef I2SBufferConfig + #define I2SBufferConfig NOROM_I2SBufferConfig + #undef I2SPointerUpdate + #define I2SPointerUpdate NOROM_I2SPointerUpdate + #undef I2SPointerSet + #define I2SPointerSet NOROM_I2SPointerSet + #undef I2SSampleStampConfigure + #define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure + #undef I2SSampleStampGet + #define I2SSampleStampGet NOROM_I2SSampleStampGet +#endif + +//***************************************************************************** +// +// Global pointer to the current I2S data structure +// +//***************************************************************************** +I2SControlTable *g_pControlTable; + +//***************************************************************************** +// +// Enables the I2S module for operation +// +//***************************************************************************** +void +I2SEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Make sure the control table pointer is setup to a memory location. + if(!(g_pControlTable)) + { + return; + } + + // Write the address to the first input/output buffer. + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InBase; + g_pControlTable->ui32InOffset = 0; + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = g_pControlTable->ui32OutBase; + g_pControlTable->ui32OutOffset = 0; + + // Enable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = (uint32_t)g_pControlTable->ui16DMABufSize - 1; +} + +//***************************************************************************** +// +// Configures the I2S module +// +//***************************************************************************** +void +I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg, + uint32_t ui32BitClkDelay) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui32BitClkDelay <= 255); + + // Save the length of the audio words stored in memory. + g_pControlTable->ui16MemLen = (ui32FmtCfg & I2S_MEM_LENGTH_24) ? 24 : 16; + + // Write the configuration. + HWREG(I2S0_BASE + I2S_O_AIFFMTCFG) = ui32FmtCfg | (ui32BitClkDelay << I2S_AIFFMTCFG_DATA_DELAY_S); +} + +//**************************************************************************** +// +// Setup the audio channel configuration +// +//**************************************************************************** +void +I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg, + uint32_t ui32Chan1Cfg) +{ + uint32_t ui32InChan; + uint32_t ui32OutChan; + uint32_t ui32ChanMask; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui32Chan0Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK)) + ASSERT(ui32Chan1Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK)) + + ui32InChan = 0; + ui32OutChan = 0; + + // Configure input/output channels. + HWREG(I2S0_BASE + I2S_O_AIFDIRCFG) = ( + (( ui32Chan0Cfg << I2S_AIFDIRCFG_AD0_S) & I2S_AIFDIRCFG_AD0_M ) | + (( ui32Chan1Cfg << I2S_AIFDIRCFG_AD1_S) & I2S_AIFDIRCFG_AD1_M ) ); + + // Configure the valid channel mask. + HWREG(I2S0_BASE + I2S_O_AIFWMASK0) = (ui32Chan0Cfg >> 8) & I2S_AIFWMASK0_MASK_M; + HWREG(I2S0_BASE + I2S_O_AIFWMASK1) = (ui32Chan1Cfg >> 8) & I2S_AIFWMASK1_MASK_M; + + // Resolve and save the number of input and output channels. + ui32ChanMask = (ui32Chan0Cfg & I2S_CHAN_CFG_MASK) >> 8; + if(ui32Chan0Cfg & I2S_LINE_INPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32InChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + + } + else if(ui32Chan0Cfg & I2S_LINE_OUTPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32OutChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + } + + ui32ChanMask = (ui32Chan1Cfg & I2S_CHAN_CFG_MASK) >> 8; + if(ui32Chan1Cfg & I2S_LINE_INPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32InChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + } + else if(ui32Chan1Cfg & I2S_LINE_OUTPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32OutChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + } + + g_pControlTable->ui8InChan = (uint8_t)ui32InChan; + g_pControlTable->ui8OutChan = (uint8_t)ui32OutChan; +} + +//**************************************************************************** +// +// Set the input buffer pointers +// +//**************************************************************************** +void +I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase, + uint32_t ui32OutBufBase, uint16_t ui16DMABufSize, + uint16_t ui16ChanBufSize) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui16DMABufSize > 0); + + // Setup the input data pointer and buffer sizes. + g_pControlTable->ui16DMABufSize = ui16DMABufSize; + g_pControlTable->ui16ChBufSize = ui16ChanBufSize; + g_pControlTable->ui32InBase = ui32InBufBase; + g_pControlTable->ui32OutBase = ui32OutBufBase; +} + +//**************************************************************************** +// +// Set the buffer pointers +// +//**************************************************************************** +void +I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Update the next input/output pointer with the correct address. + if(bInput == true) + { + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = (uint32_t)pNextPointer; + } + else + { + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = (uint32_t)pNextPointer; + } +} + +//**************************************************************************** +// +// Update the buffer pointers +// +//**************************************************************************** +void +I2SPointerUpdate(uint32_t ui32Base, bool bInput) +{ + uint32_t ui32NextPtr; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Update the next input/output pointer with the correct address. + if(bInput == true) + { + ui32NextPtr = (g_pControlTable->ui8InChan * + (g_pControlTable->ui16MemLen >> 3)) * + g_pControlTable->ui16DMABufSize; + g_pControlTable->ui32InOffset = ((g_pControlTable->ui32InOffset + + ui32NextPtr) % + g_pControlTable->ui16ChBufSize); + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InOffset + + g_pControlTable->ui32InBase; + } + else + { + ui32NextPtr = (g_pControlTable->ui8OutChan * + (g_pControlTable->ui16MemLen >> 3)) * + g_pControlTable->ui16DMABufSize; + g_pControlTable->ui32OutOffset = ((g_pControlTable->ui32OutOffset + + ui32NextPtr) % + g_pControlTable->ui16ChBufSize); + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = + g_pControlTable->ui32OutOffset + + g_pControlTable->ui32OutBase; + } +} + +//***************************************************************************** +// +// Configure the sample stamp generator +// +//***************************************************************************** +void +I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, bool bOutput) +{ + uint32_t ui32Trigger; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + ui32Trigger = HWREG(I2S0_BASE + I2S_O_STMPWCNT); + ui32Trigger = (ui32Trigger + 2) % g_pControlTable->ui16ChBufSize; + + // Setup the sample stamp trigger for input streams. + if(bInput) + { + HWREG(I2S0_BASE + I2S_O_STMPINTRIG) = ui32Trigger; + } + + // Setup the sample stamp trigger for output streams. + if(bOutput) + { + HWREG(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui32Trigger; + } + +} + +//***************************************************************************** +// +// Get the current value of a sample stamp counter +// +//***************************************************************************** +uint32_t +I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel) +{ + uint32_t ui32FrameClkCnt; + uint32_t ui32SysClkCnt; + uint32_t ui32PeriodSysClkCnt; + uint32_t ui32SampleStamp; + + // Get the number of Frame clock counts since last stamp. + ui32FrameClkCnt = HWREG(I2S0_BASE + I2S_O_STMPWCNTCAPT0); + + // Get the number of system clock ticks since last frame clock edge. + ui32SysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXCNTCAPT0); + + // Get the number system clock ticks in the last frame clock period. + ui32PeriodSysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXPER); + + // Calculate the sample stamp. + ui32SampleStamp = (ui32SysClkCnt << 16) / ui32PeriodSysClkCnt; + ui32SampleStamp = (ui32SampleStamp > I2S_STMP_SATURATION) ? + I2S_STMP_SATURATION : ui32SampleStamp; + ui32SampleStamp |= (ui32FrameClkCnt << 16); + + return (ui32SampleStamp); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s.h new file mode 100644 index 0000000..ab50cd6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s.h @@ -0,0 +1,1359 @@ +/****************************************************************************** +* Filename: i2s.h +* Revised: 2018-11-16 11:16:53 +0100 (Fri, 16 Nov 2018) +* Revision: 53356 +* +* Description: Defines and prototypes for the I2S. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//**************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup i2s_api +//! @{ +// +//**************************************************************************** + +#ifndef __I2S_H__ +#define __I2S_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_i2s.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define I2SEnable NOROM_I2SEnable + #define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure + #define I2SChannelConfigure NOROM_I2SChannelConfigure + #define I2SBufferConfig NOROM_I2SBufferConfig + #define I2SPointerUpdate NOROM_I2SPointerUpdate + #define I2SPointerSet NOROM_I2SPointerSet + #define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure + #define I2SSampleStampGet NOROM_I2SSampleStampGet +#endif + +//***************************************************************************** +// +//! \brief A structure that defines an audio control table. Note: Memory for this +//! structure \b must be initialized by user application. See detailed description! +//! +//! \deprecated This structure will be removed in a future release. +//! +//! These fields are used by the I2S and normally it is not necessary for +//! software to directly read or write fields in the table. +//! +//! \note The control table must be defined by the user as a global variable and +//! the global pointer must then be assigned the address of the control table +//! inside a user function (but before calling any I2S-function). +//! +/*! +\verbatim + I2SControlTable g_controlTable; // Define global + g_pControlTable = &g_controlTable; // Assign pointer (inside a function) +\endverbatim +*/ +//! +// +//***************************************************************************** +#ifndef DEPRECATED +typedef struct +{ + uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples. + uint16_t ui16ChBufSize; //!< Size of Channel buffer. + uint8_t ui8InChan; //!< Input Channel. + uint8_t ui8OutChan; //!< Output Channel. + uint16_t ui16MemLen; //!< Length of the audio words stored in memory. + uint32_t ui32InBase; //!< Base address of the input buffer. + uint32_t ui32InOffset; //!< Value of the current input pointer offset. + uint32_t ui32OutBase; //!< Base address of the output buffer. + uint32_t ui32OutOffset; //!< Value of the current output pointer offset. +} I2SControlTable; +#endif + +//***************************************************************************** +// +// Declare global pointer to the I2S data structure. +// +// The control table must be defined by the user as a global variable and the +// global pointer must then be assigned the address of the control table: +// +// I2SControlTable g_controlTable; +// g_pControlTable = &g_controlTable; +// +//***************************************************************************** +#ifndef DEPRECATED +extern I2SControlTable *g_pControlTable; +#endif + +//***************************************************************************** +// +// Defines for the I2S DMA buffer sizes +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_DMA_BUF_SIZE_64 0x00000040 +#define I2S_DMA_BUF_SIZE_128 0x00000080 +#define I2S_DMA_BUF_SIZE_256 0x00000100 +#endif + +//***************************************************************************** +// +// Defines for the I2S audio clock configuration +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_EXT_WCLK 0x00000001 +#define I2S_INT_WCLK 0x00000002 +#define I2S_INVERT_WCLK 0x00000004 +#define I2S_NORMAL_WCLK 0x00000000 +#endif + +//***************************************************************************** +// +// Defines for the audio data line input/output configuration +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_LINE_UNUSED 0x00000000 +#define I2S_LINE_INPUT 0x00000001 +#define I2S_LINE_OUTPUT 0x00000002 +#define I2S_LINE_MASK 0x00000003 +#endif + +//***************************************************************************** +// +// Defines for activating an audio channel. +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_CHAN0_ACT 0x00000100 +#define I2S_CHAN1_ACT 0x00000200 +#define I2S_CHAN2_ACT 0x00000400 +#define I2S_CHAN3_ACT 0x00000800 +#define I2S_CHAN4_ACT 0x00001000 +#define I2S_CHAN5_ACT 0x00002000 +#define I2S_CHAN6_ACT 0x00004000 +#define I2S_CHAN7_ACT 0x00008000 +#define I2S_MONO_MODE 0x00000100 +#define I2S_STEREO_MODE 0x00000300 +#define I2S_CHAN_CFG_MASK 0x0000FF00 +#endif + +#define I2S_CHAN0_MASK 0x00000001 +#define I2S_CHAN1_MASK 0x00000002 +#define I2S_CHAN2_MASK 0x00000004 +#define I2S_CHAN3_MASK 0x00000008 +#define I2S_CHAN4_MASK 0x00000010 +#define I2S_CHAN5_MASK 0x00000020 +#define I2S_CHAN6_MASK 0x00000040 +#define I2S_CHAN7_MASK 0x00000080 + +//***************************************************************************** +// +// Defines for the audio format configuration +// +//***************************************************************************** +#define I2S_MEM_LENGTH_16 0x00000000 // 16 bit size of word in memory +#define I2S_MEM_LENGTH_24 0x00000080 // 24 bit size of word in memory +#define I2S_POS_EDGE 0x00000040 // Sample on positive edge +#define I2S_NEG_EDGE 0x00000000 // Sample on negative edge +#define I2S_DUAL_PHASE_FMT 0x00000020 // Dual Phased audio format +#define I2S_SINGLE_PHASE_FMT 0x00000000 // Single Phased audio format +#define I2S_WORD_LENGTH_8 0x00000008 // Word length is 8 bits +#define I2S_WORD_LENGTH_16 0x00000010 // Word length is 16 bits +#define I2S_WORD_LENGTH_24 0x00000018 // Word length is 24 bits + +//***************************************************************************** +// +// Defines for the sample stamp counters +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_STMP0 0x00000001 // Sample stamp counter channel 0 +#define I2S_STMP1 0x00000002 // Sample stamp counter channel 1 +#endif +#define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when + // calculating the sample stamp + +//***************************************************************************** +// +// Defines for the interrupt +// +//***************************************************************************** +#define I2S_INT_DMA_IN 0x00000020 // DMA output buffer full interrupt +#define I2S_INT_DMA_OUT 0x00000010 // DMA input buffer empty interrupt +#define I2S_INT_TIMEOUT 0x00000008 // Word Clock Timeout +#define I2S_INT_BUS_ERR 0x00000004 // DMA Bus error +#define I2S_INT_WCLK_ERR 0x00000002 // Word Clock error +#define I2S_INT_PTR_ERR 0x00000001 // Data pointer error (DMA data was not updated in time). +#define I2S_INT_ALL 0x0000003F // All interrupts + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an I2S base address. +//! +//! This function determines if an I2S port base address is valid. +//! +//! \param ui32Base is the base address of the I2S port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +I2SBaseValid(uint32_t ui32Base) +{ + return(ui32Base == I2S0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Enables the I2S module for operation. +//! +//! \deprecated This function will be removed in a future release. +//! +//! \note The module should only be enabled after configuration. When the +//! module is disabled, no data or clocks will be generated on the I2S signals. +//! +//! \note Immediately after enabling the module the programmer should update +//! the DMA data pointer registers using \ref I2SPointerUpdate() to ensure a new +//! pointer is written before the DMA transfer completes. Failure to update +//! the pointer in time will result in an \ref I2S_INT_PTR_ERR. +//! +//! \param ui32Base is the I2S module base address. +//! +//! \return None +// +//***************************************************************************** +#ifndef DEPRECATED +extern void I2SEnable(uint32_t ui32Base); +#endif + +//***************************************************************************** +// +//! \brief Disables the I2S module for operation. +//! +//! \deprecated This function will be removed in a future release. +//! +//! This function will immediately disable the I2S module. To ensure that +//! all buffer operations are completed before shutting down, the correct +//! procedure is: +//! 1. Do not update the data pointers using \ref I2SPointerUpdate(). +//! 2. Await next interrupt resulting in \ref I2S_INT_PTR_ERR. +//! 3. Disable the I2S using \ref I2SDisable() and clear the pointer error using +//! \ref I2SIntClear(). +//! 4. Disable bit clock source (done externally). +//! +//! \param ui32Base is the I2S module base address. +//! +//! \return None +// +//***************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x0; +} +#endif + +//***************************************************************************** +// +//! \brief Configures the I2S module. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The word length defines the size of the word transmitted on the data +//! lines. For single phased formats \c I2S_WORD_LENGTH_x is the exact number +//! of bits per word. In dual phased format this is the maximum number of bits +//! per word. The size is set using \ref I2S_WORD_LENGTH_8, +//! \ref I2S_WORD_LENGTH_16 or \ref I2S_WORD_LENGTH_24. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui32FmtCfg is the bitwise OR of several options: +//! - Sample size: +//! - \ref I2S_MEM_LENGTH_16 +//! - \ref I2S_MEM_LENGTH_24 +//! - Clock edge sampling: +//! - \ref I2S_POS_EDGE +//! - \ref I2S_NEG_EDGE +//! - Phase: +//! - \ref I2S_DUAL_PHASE_FMT +//! - \ref I2S_SINGLE_PHASE_FMT +//! - Word length: +//! - \ref I2S_WORD_LENGTH_8 +//! - \ref I2S_WORD_LENGTH_16 +//! - \ref I2S_WORD_LENGTH_24 +//! \param ui32BitClkDelay defines the bit clock delay by setting the number of bit clock periods between the +//! positive word clock edge and the MSB of the first word in a phase. The bit +//! clock delay is determined by the ratio between the bit clock and the frame +//! clock and the chosen audio format. The bit clock delay \b must be configured +//! depending on the chosen audio format: +//! - 0 : Left Justified Format (LJF). +//! - 1 : I2S and DSP format. +//! - 2-255 : Right Justified format (RJF). +//! +//! \return None +//! +//! \sa \ref I2SChannelConfigure() +// +//***************************************************************************** +#ifndef DEPRECATED +extern void I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg, + uint32_t ui32BitClkDelay); +#endif + +//**************************************************************************** +// +//! \brief Setup the audio channel configuration. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The channel configuration is a bitwise OR of the input/output mode of each +//! data line and the active audio channels within a specific audio frame. +//! +//! Setting up the input/output mode use one of: +//! - \ref I2S_LINE_UNUSED +//! - \ref I2S_LINE_INPUT +//! - \ref I2S_LINE_OUTPUT +//! +//! For dual phased audio (LJF,RJF,I2S) only mono and stereo modes are allowed. +//! For single phased audio format (DSP) up to 8 active channels are allowed +//! on a single data line. For setting up the active channels in a frame use: +//! - Single phased, use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_ACT +//! - \ref I2S_CHAN1_ACT +//! - \ref I2S_CHAN2_ACT +//! - \ref I2S_CHAN3_ACT +//! - \ref I2S_CHAN4_ACT +//! - \ref I2S_CHAN5_ACT +//! - \ref I2S_CHAN6_ACT +//! - \ref I2S_CHAN7_ACT +//! - Dual phased, use one of: +//! - \ref I2S_MONO_MODE (same as \ref I2S_CHAN0_ACT) +//! - \ref I2S_STEREO_MODE (same as \ref I2S_CHAN0_ACT | \ref I2S_CHAN1_ACT) +//! +//! \note The audio format and the clock configuration should be set using +//! \ref I2SAudioFormatConfigure() +//! +//! \param ui32Base is base address of the I2S module. +//! \param ui32Chan0Cfg defines the channel configuration for data line 0. +//! \param ui32Chan1Cfg defines the channel configuration for data line 1. +//! +//! \return None +//! +//! \sa \ref I2SAudioFormatConfigure() +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg, + uint32_t ui32Chan1Cfg); +#endif + +//**************************************************************************** +// +//! \brief Configure the I2S frame clock. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Configure I2S clock to be either internal or external and either normal +//! or inverted. +//! +//! \note The bit clock configuration is done externally, but the internal/ +//! external setting must match what is chosen internally in the I2S module +//! for the frame clock. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32ClkConfig is the clock configuration parameter. Bitwise OR'ed +//! combination of clock source and clock polarity: +//! - Clock source: +//! - \ref I2S_EXT_WCLK : External clock. +//! - \ref I2S_INT_WCLK : Internal clock. +//! - Clock polarity: +//! - \ref I2S_NORMAL_WCLK : Normal clock. +//! - \ref I2S_INVERT_WCLK : Inverted clock. +//! +//! \return None +// +//**************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup register WCLK Source. + HWREG(I2S0_BASE + I2S_O_AIFWCLKSRC) = ui32ClkConfig & + (I2S_AIFWCLKSRC_WCLK_INV_M | + I2S_AIFWCLKSRC_WCLK_SRC_M); +} +#endif + +//**************************************************************************** +// +//! \brief Set the input buffer pointers. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will +//! occur and all outputs will be disabled. +//! +//! \note At startup the next data pointer should be +//! written just before and just after calling the \ref I2SEnable(). +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32InBufBase is the address of the input buffer. +//! \param ui32OutBufBase is the address of the output buffer. +//! \param ui16DMABufSize is the size of the DMA buffers. Must be greater than 0! +//! \param ui16ChanBufSize is the size of the channel buffers. +//! +//! \return None +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase, + uint32_t ui32OutBufBase, uint16_t ui16DMABufSize, + uint16_t ui16ChanBufSize); +#endif + +//**************************************************************************** +// +//! \brief Update the buffer pointers. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur +//! and all outputs will be disabled. Nothing is preventing the pointers from +//! being identical, but this function relies on both pointers (input or +//! output pointers) are pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param bInput determines whether to update input or output pointer. +//! - \c true : Update input pointer. +//! - \c false : Update output pointer +//! +//! \return None +//! +//! \sa \ref I2SPointerSet() +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SPointerUpdate(uint32_t ui32Base, bool bInput); +#endif + +//**************************************************************************** +// +//! \brief Set a buffer pointer (input or output) directly. +//! +//! \deprecated This function will be removed in a future release. +//! +//! This function allows bypassing of the pointers in the global control table. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur +//! and all outputs will be disabled. Nothing is preventing the pointers from +//! being identical, but this function relies on both pointers (input or +//! output pointers) are pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param bInput determines whether to update input or output pointer. +//! - \c true : Update input pointer. +//! - \c false : Update output pointer +//! \param pNextPointer is a void pointer to user defined buffer. +//! +//! \return None +//! +//! \sa \ref I2SPointerUpdate() +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer); +#endif + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for an I2S interrupt in the dynamic interrupt table. +//! +//! \deprecated This function will be removed in a future release. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific I2S interrupts must be enabled via \ref I2SIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param pfnHandler is a pointer to the function to be called when the +//! I2S interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Register the interrupt handler. + IntRegister(INT_I2S_IRQ, pfnHandler); + + // Enable the I2S interrupt. + IntEnable(INT_I2S_IRQ); +} +#endif + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a I2S interrupt in the dynamic interrupt table. +//! +//! \deprecated This function will be removed in a future release. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when an I2S interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \param ui32Base is the base address of the I2S port. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SIntUnregister(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the interrupt. + IntDisable(INT_I2S_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_I2S_IRQ); +} +#endif + +//***************************************************************************** +// +//! \brief Configure the sample stamp generator. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param bInput enables triggering of the sample stamp generator on input. +//! \param bOutput enables triggering of the sample stamp generator on output. +//! +//! \return None +// +//***************************************************************************** +#ifndef DEPRECATED +extern void I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, + bool bOutput); +#endif + +//***************************************************************************** +// +//! \brief Enables individual I2S interrupt sources. +//! +//! This function enables the indicated I2S interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2S port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +//! - \ref I2S_INT_ALL (covers all the above) +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +I2SIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(I2S0_BASE + I2S_O_IRQMASK) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual I2S interrupt sources. +//! +//! This function disables the indicated I2S interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2S port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +//! - \ref I2S_INT_ALL (covers all the above) +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +I2SIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(I2S0_BASE + I2S_O_IRQMASK) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the specified I2S. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the I2S port +//! \param bMasked selects between raw and masked interrupt status: +//! - \c false : Raw interrupt status is required. +//! - \c true : Masked interrupt status is required. +//! +//! \return Returns the current interrupt status as a vector of: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2SIntStatus(uint32_t ui32Base, bool bMasked) +{ + uint32_t ui32Mask; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + ui32Mask = HWREG(I2S0_BASE + I2S_O_IRQFLAGS); + return(ui32Mask & HWREG(I2S0_BASE + I2S_O_IRQMASK)); + } + else + { + return(HWREG(I2S0_BASE + I2S_O_IRQFLAGS)); + } +} + +//***************************************************************************** +// +//! \brief Clears I2S interrupt sources. +//! +//! The specified I2S interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the I2S port. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +//! - \ref I2S_INT_ALL (covers all the above) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Clear the requested interrupt sources. + HWREG(I2S0_BASE + I2S_O_IRQCLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Enable the Sample Stamp generator. +//! +//! Use this function to enable the sample stamp generators. +//! +//! \note It is the user's responsibility to ensure that the sample stamp +//! generator is properly configured before it is enabled. It is the setting +//! of the Input and Output triggers configured using \ref I2SSampleStampConfigure() +//! that triggers the start point of the audio streams. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Set the enable bit. + HWREG(I2S0_BASE + I2S_O_STMPCTL) = I2S_STMPCTL_STMP_EN; +} + +//***************************************************************************** +// +//! \brief Disable the Sample Stamp generator. +//! +//! Use this function to disable the sample stamp generators. When the sample +//! stamp generator is disabled, the clock counters are automatically cleared. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Clear the enable bit. + HWREG(I2S0_BASE + I2S_O_STMPCTL) = 0; + +} + +//***************************************************************************** +// +//! \brief Get the current value of a sample stamp counter. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32Channel is the sample stamp counter to sample +//! +//! \return Returns the current value of the selected sample stamp channel. +// +//***************************************************************************** +extern uint32_t I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel); + +//***************************************************************************** +// +//! \brief Starts the I2S. +//! +//! I2S must be configured before it is started. +//! +//! \note Immediately after enabling the module the programmer must update +//! the DMA data pointer registers using \ref I2SInPointerSet() and +//! \ref I2SOutPointerSet() to ensure a new pointer is written before the DMA +//! transfer completes. Failure to update the pointer in time will result in +//! an \ref I2S_INT_PTR_ERR. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui8FixDMALength is the length of the DMA buffer: this will allow +//! the DMA to read ui8FixDMALength between to pointer refreshes. +//! +//! \return None +//! +//! \sa \ref I2SStop() +// +//***************************************************************************** +__STATIC_INLINE void I2SStart(uint32_t ui32Base, uint8_t ui8FixDMALength) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Enable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = ui8FixDMALength; +} + +//***************************************************************************** +// +//! \brief Stops the I2S module for operation. +//! +//! This function will immediately disable the I2S module. To ensure that +//! all buffer operations are completed before shutting down, the correct +//! procedure is: +//! 1. Do not update the data pointers using \ref I2SInPointerSet() and +//! \ref I2SOutPointerSet(). +//! 2. Await that values returned by \ref I2SInPointerNextGet(), +//! \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and \ref I2SOutPointerGet() +//! are zero. +//! 3. Disable the I2S using \ref I2SStop() and clear the pointer +//! error using \ref I2SIntClear(). +//! 4. Disable bit clock source (done externally). +//! +//! \param ui32Base is the I2S module base address. +//! +//! \return None +//! +//! \sa \ref I2SStart() +// +//***************************************************************************** +__STATIC_INLINE void I2SStop(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x00; +} + +//***************************************************************************** +// +//! \brief Configure the serial format of the I2S module. +//! +//! The word length defines the size of the word transmitted on the data +//! lines. For single phased formats \c ui8BitsPerSample is the exact number +//! of bits per word. In dual phased format this is the maximum number of bits +//! per word. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui8iDataDelay is the number of BCLK periods between the first WCLK +//! edge and the MSB of the first audio channel data transferred during +//! the phase. +//! \param ui8iMemory24Bits selects if the samples in memory are coded on 16 bits +//! or 24 bits. Possible values are: +//! - \ref I2S_MEM_LENGTH_16 +//! - \ref I2S_MEM_LENGTH_24 +//! \param ui8iSamplingEdge selects if sampling on falling or rising edges. +//! Possible values are: +//! - \ref I2S_NEG_EDGE +//! - \ref I2S_POS_EDGE +//! \param boolDualPhase must be set to true for dual phase and to false for +//! single phase and user-defined phase. +//! \param ui8BitsPerSample is the number of bits transmitted for each sample. +//! If this number does not match with the memory length selected +//! (16 bits or24 bits), samples will be truncated or padded. +//! \param ui16transmissionDelay is the number of WCLK periods before the first +//! transmission. +//! +//! \return None +//! +//! \sa \ref I2SFrameConfigure() +// +//***************************************************************************** +__STATIC_INLINE void +I2SFormatConfigure(uint32_t ui32Base, + uint8_t ui8iDataDelay, + uint8_t ui8iMemory24Bits, + uint8_t ui8iSamplingEdge, + bool boolDualPhase, + uint8_t ui8BitsPerSample, + uint16_t ui16transmissionDelay) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui8BitsPerSample <= I2S_AIFFMTCFG_WORD_LEN_MAX); + ASSERT(ui8BitsPerSample >= I2S_AIFFMTCFG_WORD_LEN_MIN); + + // Setup register AIFFMTCFG Source. + HWREGH(I2S0_BASE + I2S_O_AIFFMTCFG) = + (ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) | + (ui8iMemory24Bits << I2S_AIFFMTCFG_MEM_LEN_24_S) | + (ui8iSamplingEdge << I2S_AIFFMTCFG_SMPL_EDGE_S ) | + (boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) | + (ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S ); + + // Number of WCLK periods before the first read / write + HWREGH(I2S0_BASE + I2S_O_STMPWPER) = ui16transmissionDelay; +} + +//**************************************************************************** +// +//! \brief Setup the two interfaces SD0 and SD1 (also called AD0 and AD1). +//! +//! This function sets interface's direction and activated channels. +//! +//! \param ui32Base is base address of the I2S module. +//! \param ui8StatusAD0 defines the usage of AD0 +//! 0x00: AD0 is disabled +//! 0x01, AD0 is an input +//! 0x02, AD0 is an output +//! \param ui8ChanAD0 defines the channel mask for AD0. +//! Use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_MASK +//! - \ref I2S_CHAN1_MASK +//! - \ref I2S_CHAN2_MASK +//! - \ref I2S_CHAN3_MASK +//! - \ref I2S_CHAN4_MASK +//! - \ref I2S_CHAN5_MASK +//! - \ref I2S_CHAN6_MASK +//! - \ref I2S_CHAN7_MASK +//! \param ui8StatusAD1 defines the usage of AD1 +//! 0x00: AD1 is disabled +//! 0x10, AD1 is an input +//! 0x20, AD1 is an output +//! \param ui8ChanAD1 defines the channel mask for AD1. +//! Use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_MASK +//! - \ref I2S_CHAN1_MASK +//! - \ref I2S_CHAN2_MASK +//! - \ref I2S_CHAN3_MASK +//! - \ref I2S_CHAN4_MASK +//! - \ref I2S_CHAN5_MASK +//! - \ref I2S_CHAN6_MASK +//! - \ref I2S_CHAN7_MASK +//! +//! \return None +//! +//! \sa \ref I2SFormatConfigure() +// +//**************************************************************************** +__STATIC_INLINE void +I2SFrameConfigure(uint32_t ui32Base, + uint8_t ui8StatusAD0, uint8_t ui8ChanAD0, + uint8_t ui8StatusAD1, uint8_t ui8ChanAD1) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Configure input/output channels. + HWREGB(I2S0_BASE + I2S_O_AIFDIRCFG) = (ui8StatusAD0 | ui8StatusAD1); + + // Configure the valid channel mask. + HWREGB(I2S0_BASE + I2S_O_AIFWMASK0) = ui8ChanAD0; + HWREGB(I2S0_BASE + I2S_O_AIFWMASK1) = ui8ChanAD1; +} + +//**************************************************************************** +// +//! \brief Configure the I2S frame clock (also called WCLK or WS). +//! +//! Configure WCLK clock to be either internal (master) or external (slave). +//! Configure WCLK clock either normal or inverted. +//! +//! \note The bit clock configuration is done externally, but the internal/ +//! external setting must match what is chosen internally in the I2S module +//! for the frame clock. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param boolMaster false: the device is a slave (external clock) +//! true: the device is a master (internal clock) +//! \param boolWCLKInvert false: WCLK is not inverted +//! true: WCLK is internally inverted +//! +//! \return None +// +//**************************************************************************** +__STATIC_INLINE void +I2SWclkConfigure(uint32_t ui32Base, + bool boolMaster, + bool boolWCLKInvert) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui8ClkSource < I2S_AIFWCLKSRC_WCLK_SRC_RESERVED); + + // if(boolMaster == 0) then ui8ClkSource = 1 + // if(boolMaster == 1) then ui8ClkSource = 2 + uint8_t ui8ClkSource = (uint8_t)boolMaster + 0x01; + + // Setup register WCLK Source. + HWREGB(I2S0_BASE + I2S_O_AIFWCLKSRC) = + ((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) | + (boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S )); +} + +//**************************************************************************** +// +//! \brief Set the input buffer pointer. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR +//! will occur and all inputs and outputs will be disabled. +//! This function relies on pointer is pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32NextPointer is the adress of the data +//! +//! \return None +//! +//! \sa \ref I2SOutPointerSet() +// +//**************************************************************************** +__STATIC_INLINE void +I2SInPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = ui32NextPointer; +} + +//**************************************************************************** +// +//! \brief Set the output buffer pointer. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR +//! will occur and all inputs and outputs will be disabled. +//! This function relies on pointer is pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32NextPointer is the adress of the data +//! +//! \return None +//! +//! \sa \ref I2SInPointerSet() +// +//**************************************************************************** +__STATIC_INLINE void +I2SOutPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = ui32NextPointer; +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR NEXT IN register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR NEXT IN. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SInPointerNextGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT)); +} + + +//**************************************************************************** +// +//! \brief Get value stored in PTR NEXT OUT register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR NEXT OUT. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SOutPointerNextGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT)); +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR IN register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR IN. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SInPointerGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFINPTR)); +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR OUT register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR OUT. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SOutPointerGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTR)); +} + +//***************************************************************************** +// +//! \brief Configure the IN sample stamp generator. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui16TrigValue value used to set the trigger. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampInConfigure(uint32_t ui32Base, uint16_t ui16TrigValue) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup the sample stamp trigger for input streams. + HWREGH(I2S0_BASE + I2S_O_STMPINTRIG) = ui16TrigValue; +} + +//***************************************************************************** +// +//! \brief Configure the OUT sample stamp generator. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui16TrigValue value used to set the trigger. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampOutConfigure(uint32_t ui32Base, uint16_t ui16TrigValue) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup the sample stamp trigger for output streams. + HWREGH(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui16TrigValue; +} + +//***************************************************************************** +// +//! \brief Add the specified value to the WCLK count. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param i16Value is the offset to add to the counter (this value can be negative) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SWclkCounterConfigure(uint32_t ui32Base, int16_t i16Value) +{ + uint16_t ui16MinusValue; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + if (i16Value >= 0) + { + HWREGH(I2S0_BASE + I2S_O_STMPWADD) = i16Value; + } + else + { + ui16MinusValue = (uint16_t)(-i16Value); + HWREGH(I2S0_BASE + I2S_O_STMPWADD) = HWREGH(I2S0_BASE + I2S_O_STMPWPER) - ui16MinusValue; + } +} + +//***************************************************************************** +// +//! \brief Reset the WCLK count. +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SWclkCounterReset(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREGH(I2S0_BASE + I2S_O_STMPWSET) = 0; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_I2SEnable + #undef I2SEnable + #define I2SEnable ROM_I2SEnable + #endif + #ifdef ROM_I2SAudioFormatConfigure + #undef I2SAudioFormatConfigure + #define I2SAudioFormatConfigure ROM_I2SAudioFormatConfigure + #endif + #ifdef ROM_I2SChannelConfigure + #undef I2SChannelConfigure + #define I2SChannelConfigure ROM_I2SChannelConfigure + #endif + #ifdef ROM_I2SBufferConfig + #undef I2SBufferConfig + #define I2SBufferConfig ROM_I2SBufferConfig + #endif + #ifdef ROM_I2SPointerUpdate + #undef I2SPointerUpdate + #define I2SPointerUpdate ROM_I2SPointerUpdate + #endif + #ifdef ROM_I2SPointerSet + #undef I2SPointerSet + #define I2SPointerSet ROM_I2SPointerSet + #endif + #ifdef ROM_I2SSampleStampConfigure + #undef I2SSampleStampConfigure + #define I2SSampleStampConfigure ROM_I2SSampleStampConfigure + #endif + #ifdef ROM_I2SSampleStampGet + #undef I2SSampleStampGet + #define I2SSampleStampGet ROM_I2SSampleStampGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2S_H__ + +//**************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//**************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s_doc.h new file mode 100644 index 0000000..27ddceb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s_doc.h @@ -0,0 +1,141 @@ +/****************************************************************************** +* Filename: i2s_doc.h +* Revised: $$ +* Revision: $$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup i2s_api +//! @{ +//! \section sec_i2s Introduction +//! +//! The I2S API provides a set of functions for using the I2S module. +//! This module provides a standardized serial interface to transfer +//! audio samples from and to external audio devices such as a codec, +//! DAC, or ADC. +//! +//! The I2S module has the following features: +//! - Audio clock signals are internally generated by the PRCM module +//! or externally by another device. +//! - One or two data pins, which can be configured independently as +//! input or output +//! - Various data formats according to the settings of the module +//! - Up to two channels per data pin for dual phase formats and up +//! to eight channels per data pin for single phase formats +//! - DMA with double-buffered pointers +//! - Error detection for DMA and audio clock signal integrity +//! - A Samplestamp generator that allows maintaining of constant +//! audio latency +//! +//! The I2S module is configured through the functions \ref I2SFormatConfigure(), +//! \ref I2SFrameConfigure() and \ref I2SWclkConfigure(). +//! Transfers are enabled using \ref I2SStart(). Transfers are disabled using +//! \ref I2SStop(). Please note that a specific procedure exists in order +//! to disable transfers without losing data (refer to \ref I2SStop()). +//! +//! Data are transmitted using the two double-buffered pointers. +//! For each interface, two registers are set with the address of the data to +//! transfer. These registers are named INPTR and INPTRNEXT for the input +//! interface and OUTPTR and OUTPTRNEXT for the output. When PTR is consumed, +//! the hardware copies the content of PTRNEXT into PTR and the next transfer +//! begins. +//! The address of the next value to write or to read in memory (i.e. to receive +//! or to send out) is set using \ref I2SInPointerSet() and \ref I2SOutPointerSet(). +//! The values contented by INPTRNEXT, OUTPTRNEXT, INPTR and OUTPTR can be read using +//! \ref I2SInPointerNextGet(), \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and +//! \ref I2SOutPointerGet() functions. +//! +//! Interrupts can help the user to refresh pointers on time. Interrupts can also +//! be used to detect I2S errors. \ref I2SIntEnable() and \ref I2SIntDisable() +//! activate and deactivate interrupt(s). Interrupt status can be read through +//! \ref I2SIntStatus() and a pending interrupt can be acquitted by +//! \ref I2SIntClear() function. +//! +//! The sample stamps generator can be configured to slightly delay the +//! emission or the reception of the data (based on the number of WCLK +//! cycles) using \ref I2SSampleStampInConfigure(), \ref I2SSampleStampOutConfigure(), +//! \ref I2SWclkCounterReset() and \ref I2SWclkCounterConfigure(). The current sample stamp +//! can be computed using \ref I2SSampleStampGet(). +//! To finish, the sample stamps generator can be enable and disable using +//! the following functions: \ref I2SSampleStampEnable() and +//! \ref I2SSampleStampDisable(). +//! The sample stamps generator must be enabled prior to any transfer. +//! +//! Note: Other functions contained in the PRCM API are required to handle I2S. +//! +//! \section sec_i2s_api API +//! +//! Two APIs are coexisting. +//! It is recommended to only use the new API as the old one is deprecated and +//! will be removed soon. +//! +//! New API: +//! Functions to perform I2S configuration: +//! - \ref I2SStart() +//! - \ref I2SStop() +//! - \ref I2SFormatConfigure() +//! - \ref I2SFrameConfigure() +//! - \ref I2SWclkConfigure() +//! +//! Functions to perform transfers: +//! - \ref I2SInPointerSet() +//! - \ref I2SOutPointerSet() +//! - \ref I2SInPointerGet() +//! - \ref I2SOutPointerGet() +//! - \ref I2SInPointerNextGet() +//! - \ref I2SOutPointerNextGet() +//! +//! Functions to handle interruptions: +//! - \ref I2SIntEnable() +//! - \ref I2SIntDisable() +//! - \ref I2SIntStatus() +//! - \ref I2SIntClear() +//! +//! Functions to handle sample stamps +//! - \ref I2SSampleStampEnable() +//! - \ref I2SSampleStampDisable() +//! - \ref I2SSampleStampInConfigure() +//! - \ref I2SSampleStampOutConfigure() +//! - \ref I2SSampleStampGet() +//! - \ref I2SWclkCounterConfigure() +//! - \ref I2SWclkCounterReset() +//! +//! Old API: +//! \ref I2SEnable(), \ref I2SDisable(), \ref I2SAudioFormatConfigure(), +//! \ref I2SChannelConfigure(), \ref I2SClockConfigure(), +//! \ref I2SBufferConfig(), \ref I2SIntEnable(), \ref I2SIntDisable(), +//! \ref I2SIntStatus(), \ref I2SIntClear(), \ref I2SSampleStampEnable(), +//! \ref I2SSampleStampDisable(), \ref I2SSampleStampGet(), +//! \ref I2SPointerSet (), \ref I2SPointerUpdate(), +//! \ref I2SSampleStampConfigure(), \ref I2SIntRegister(), +//! \ref I2SIntUnregister() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt.c new file mode 100644 index 0000000..b902690 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt.c @@ -0,0 +1,469 @@ +/****************************************************************************** +* Filename: interrupt.c +* Revised: 2017-05-19 11:31:39 +0200 (Fri, 19 May 2017) +* Revision: 49017 +* +* Description: Driver for the NVIC Interrupt Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "interrupt.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef IntRegister + #define IntRegister NOROM_IntRegister + #undef IntUnregister + #define IntUnregister NOROM_IntUnregister + #undef IntPriorityGroupingSet + #define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet + #undef IntPriorityGroupingGet + #define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet + #undef IntPrioritySet + #define IntPrioritySet NOROM_IntPrioritySet + #undef IntPriorityGet + #define IntPriorityGet NOROM_IntPriorityGet + #undef IntEnable + #define IntEnable NOROM_IntEnable + #undef IntDisable + #define IntDisable NOROM_IntDisable + #undef IntPendSet + #define IntPendSet NOROM_IntPendSet + #undef IntPendGet + #define IntPendGet NOROM_IntPendGet + #undef IntPendClear + #define IntPendClear NOROM_IntPendClear +#endif + +//***************************************************************************** +// +//! This is a mapping between priority grouping encodings and the number of +//! preemption priority bits. +// +//***************************************************************************** +static const uint32_t g_pui32Priority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; + +//***************************************************************************** +// +//! This is a mapping between interrupt number and the register that contains +//! the priority encoding for that interrupt. +// +//***************************************************************************** +static const uint32_t g_pui32Regs[] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13 +}; + +//***************************************************************************** +// +//! \brief The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts should be disabled before unregistering the +//! corresponding handler, this should never be called. +//! +//! \return None +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // Go into an infinite loop. + while(1) + { + } +} + +//***************************************************************************** +// +//! \brief Global pointer to the (dynamic) interrupt vector table when placed in SRAM. +//! +//! Interrupt vector table is placed at "vtable_ram" defined in the linker file +//! provided by Texas Instruments. By default, this is at the beginning of SRAM. +//! +//! \note See \ti_code{interrupt.c} for compiler specific implementation! +// +//***************************************************************************** +#if defined(DOXYGEN) +// Dummy void pointer used as placeholder to generate Doxygen documentation. +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma data_alignment=256 +static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ ".vtable_ram"; +#elif defined(__TI_COMPILER_VERSION__) +#pragma DATA_ALIGN(g_pfnRAMVectors, 256) +#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable_ram") +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#elif defined (__CC_ARM) +static __attribute__((section("vtable_ram"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256))); +#else +static __attribute__((section("vtable_ram"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256))); +#endif + +//***************************************************************************** +// +// Registers a function to be called when an interrupt occurs. +// +//***************************************************************************** +void +IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)) +{ + uint32_t ui32Idx, ui32Value; + + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Make sure that the RAM vector table is correctly aligned. + ASSERT(((uint32_t)g_pfnRAMVectors & 0x000000ff) == 0); + + // See if the RAM vector table has been initialized. + if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors) + { + // Copy the vector table from the beginning of FLASH to the RAM vector + // table. + ui32Value = HWREG(NVIC_VTABLE); + for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++) + { + g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) + + ui32Value); + } + + // Point NVIC at the RAM vector table. + HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors; + } + + // Save the interrupt handler. + g_pfnRAMVectors[ui32Interrupt] = pfnHandler; +} + +//***************************************************************************** +// +// Unregisters the function to be called when an interrupt occurs. +// +//***************************************************************************** +void +IntUnregister(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Reset the interrupt handler. + g_pfnRAMVectors[ui32Interrupt] = IntDefaultHandler; +} + +//***************************************************************************** +// +// Sets the priority grouping of the interrupt controller. +// +//***************************************************************************** +void +IntPriorityGroupingSet(uint32_t ui32Bits) +{ + // Check the arguments. + ASSERT(ui32Bits < NUM_PRIORITY); + + // Set the priority grouping. + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; +} + +//***************************************************************************** +// +// Gets the priority grouping of the interrupt controller +// +//***************************************************************************** +uint32_t +IntPriorityGroupingGet(void) +{ + uint32_t ui32Loop, ui32Value; + + // Read the priority grouping. + ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // Loop through the priority grouping values. + for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++) + { + // Stop looping if this value matches. + if(ui32Value == g_pui32Priority[ui32Loop]) + { + break; + } + } + + // Return the number of priority bits. + return(ui32Loop); +} + +//***************************************************************************** +// +// Sets the priority of an interrupt +// +//***************************************************************************** +void +IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority) +{ + uint32_t ui32Temp; + + // Check the arguments. + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + ASSERT(ui8Priority <= INT_PRI_LEVEL7); + + // Set the interrupt priority. + ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); + ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3))); + ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3)); + HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; +} + +//***************************************************************************** +// +// Gets the priority of an interrupt +// +//***************************************************************************** +int32_t +IntPriorityGet(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + + // Return the interrupt priority. + return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) & + 0xFF); +} + +//***************************************************************************** +// +// Enables an interrupt +// +//***************************************************************************** +void +IntEnable(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to enable. + if(ui32Interrupt == INT_MEMMANAGE_FAULT) + { + // Enable the MemManage interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ui32Interrupt == INT_BUS_FAULT) + { + // Enable the bus fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ui32Interrupt == INT_USAGE_FAULT) + { + // Enable the usage fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Enable the System Tick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Enable the general interrupt. + HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Enable the general interrupt. + HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48); + } +} + +//***************************************************************************** +// +// Disables an interrupt +// +//***************************************************************************** +void +IntDisable(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to disable. + if(ui32Interrupt == INT_MEMMANAGE_FAULT) + { + // Disable the MemManage interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ui32Interrupt == INT_BUS_FAULT) + { + // Disable the bus fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ui32Interrupt == INT_USAGE_FAULT) + { + // Disable the usage fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Disable the System Tick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Disable the general interrupt. + HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Disable the general interrupt. + HWREG(NVIC_DIS1) = 1 << (ui32Interrupt - 48); + } +} + +//***************************************************************************** +// +// Pends an interrupt +// +//***************************************************************************** +void +IntPendSet(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to pend. + if(ui32Interrupt == INT_NMI_FAULT) + { + // Pend the NMI interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; + } + else if(ui32Interrupt == INT_PENDSV) + { + // Pend the PendSV interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Pend the SysTick interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Pend the general interrupt. + HWREG(NVIC_PEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Pend the general interrupt. + HWREG(NVIC_PEND1) = 1 << (ui32Interrupt - 48); + } +} + +//***************************************************************************** +// +// Query whether an interrupt is pending +// +//***************************************************************************** +bool +IntPendGet(uint32_t ui32Interrupt) +{ + uint32_t ui32IntPending; + + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Assume no interrupts are pending. + ui32IntPending = 0; + + // The lower 16 IRQ vectors are unsupported by this function + if (ui32Interrupt < 16) + { + + return 0; + } + + // Subtract lower 16 irq vectors + ui32Interrupt -= 16; + + // Check if the interrupt is pending + ui32IntPending = HWREG(NVIC_PEND0 + (ui32Interrupt / 32)); + ui32IntPending &= (1 << (ui32Interrupt & 31)); + + return ui32IntPending ? true : false; +} + +//***************************************************************************** +// +// Unpends an interrupt +// +//***************************************************************************** +void +IntPendClear(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to unpend. + if(ui32Interrupt == INT_PENDSV) + { + // Unpend the PendSV interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Unpend the SysTick interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Unpend the general interrupt. + HWREG(NVIC_UNPEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Unpend the general interrupt. + HWREG(NVIC_UNPEND1) = 1 << (ui32Interrupt - 48); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt.h new file mode 100644 index 0000000..3cb3969 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt.h @@ -0,0 +1,702 @@ +/****************************************************************************** +* Filename: interrupt.h +* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) +* Revision: 50272 +* +* Description: Defines and prototypes for the NVIC Interrupt Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_types.h" +#include "../inc/hw_nvic.h" +#include "debug.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define IntRegister NOROM_IntRegister + #define IntUnregister NOROM_IntUnregister + #define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet + #define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet + #define IntPrioritySet NOROM_IntPrioritySet + #define IntPriorityGet NOROM_IntPriorityGet + #define IntEnable NOROM_IntEnable + #define IntDisable NOROM_IntDisable + #define IntPendSet NOROM_IntPendSet + #define IntPendGet NOROM_IntPendGet + #define IntPendClear NOROM_IntPendClear +#endif + +//***************************************************************************** +// +// Macro to generate an interrupt priority mask based on the number of bits +// of priority supported by the hardware. For CC26xx the number of priority +// bit is 3 as defined in hw_types.h. The priority mask is +// defined as +// +// INT_PRIORITY_MASK = ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) +// +//***************************************************************************** +#define INT_PRIORITY_MASK 0x000000E0 +#define INT_PRI_LEVEL0 0x00000000 +#define INT_PRI_LEVEL1 0x00000020 +#define INT_PRI_LEVEL2 0x00000040 +#define INT_PRI_LEVEL3 0x00000060 +#define INT_PRI_LEVEL4 0x00000080 +#define INT_PRI_LEVEL5 0x000000A0 +#define INT_PRI_LEVEL6 0x000000C0 +#define INT_PRI_LEVEL7 0x000000E0 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Registers a function as an interrupt handler in the dynamic vector table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function writes a function pointer to the dynamic interrupt vector table +//! in SRAM to register the function as an interrupt handler (ISR). When the corresponding +//! interrupt occurs, and it has been enabled (see \ref IntEnable()), the function +//! pointer is fetched from the dynamic vector table, and the System CPU will +//! execute the interrupt handler. +//! +//! \note The first call to this function (directly or indirectly via a peripheral +//! driver interrupt register function) copies the interrupt vector table from +//! Flash to SRAM. NVIC uses the static vector table (in Flash) until this function +//! is called. +//! +//! \param ui32Interrupt specifies the index in the vector table to modify. +//! - System exceptions (vectors 0 to 15): +//! - INT_NMI_FAULT +//! - INT_HARD_FAULT +//! - INT_MEMMANAGE_FAULT +//! - INT_BUS_FAULT +//! - INT_USAGE_FAULT +//! - INT_SVCALL +//! - INT_DEBUG +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts (vectors >15): +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_SPIS_COMB +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_SSI1_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! \param pfnHandler is a pointer to the function to register as interrupt handler. +//! +//! \return None. +//! +//! \sa \ref IntUnregister(), \ref IntEnable() +// +//***************************************************************************** +extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler in the dynamic vector table. +//! +//! This function removes an interrupt handler from the dynamic vector table and +//! replaces it with the default interrupt handler \ref IntDefaultHandler(). +//! +//! \note Remember to disable the interrupt before removing its interrupt handler +//! from the vector table. +//! +//! \param ui32Interrupt specifies the index in the vector table to modify. +//! - See \ref IntRegister() for list of valid arguments. +//! +//! \return None. +//! +//! \sa \ref IntRegister(), \ref IntDisable() +// +//***************************************************************************** +extern void IntUnregister(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Sets the priority grouping of the interrupt controller. +//! +//! This function specifies the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! Three bits are available for hardware interrupt prioritization thus priority +//! grouping values of three through seven have the same effect. +//! +//! \param ui32Bits specifies the number of bits of preemptable priority. +//! - 0 : No pre-emption priority, eight bits of subpriority. +//! - 1 : One bit of pre-emption priority, seven bits of subpriority +//! - 2 : Two bits of pre-emption priority, six bits of subpriority +//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority +//! +//! \return None +//! +//! \sa \ref IntPrioritySet() +// +//***************************************************************************** +extern void IntPriorityGroupingSet(uint32_t ui32Bits); + +//***************************************************************************** +// +//! \brief Gets the priority grouping of the interrupt controller. +//! +//! This function returns the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! \return Returns the number of bits of preemptable priority. +//! - 0 : No pre-emption priority, eight bits of subpriority. +//! - 1 : One bit of pre-emption priority, seven bits of subpriority +//! - 2 : Two bits of pre-emption priority, six bits of subpriority +//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority +// +//***************************************************************************** +extern uint32_t IntPriorityGroupingGet(void); + +//***************************************************************************** +// +//! \brief Sets the priority of an interrupt. +//! +//! This function sets the priority of an interrupt, including system exceptions. +//! When multiple interrupts are asserted simultaneously, the ones with the highest +//! priority are processed before the lower priority interrupts. Smaller numbers +//! correspond to higher interrupt priorities thus priority 0 is the highest +//! interrupt priority. +//! +//! \warning This function does not support setting priority of interrupt vectors +//! one through three which are: +//! - 1: Reset handler +//! - 2: NMI handler +//! - 3: Hard fault handler +//! +//! \param ui32Interrupt specifies the index in the vector table to change priority for. +//! - System exceptions: +//! - INT_MEMMANAGE_FAULT +//! - INT_BUS_FAULT +//! - INT_USAGE_FAULT +//! - INT_SVCALL +//! - INT_DEBUG +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_SPIS_COMB +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_SSI1_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! \param ui8Priority specifies the priority of the interrupt. +//! - \ref INT_PRI_LEVEL0 : Highest priority. +//! - \ref INT_PRI_LEVEL1 +//! - \ref INT_PRI_LEVEL2 +//! - \ref INT_PRI_LEVEL3 +//! - \ref INT_PRI_LEVEL4 +//! - \ref INT_PRI_LEVEL5 +//! - \ref INT_PRI_LEVEL6 +//! - \ref INT_PRI_LEVEL7 : Lowest priority. +//! +//! \return None +//! +//! \sa \ref IntPriorityGroupingSet() +// +//***************************************************************************** +extern void IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority); + +//***************************************************************************** +// +//! \brief Gets the priority of an interrupt. +//! +//! This function gets the priority of an interrupt. +//! +//! \warning This function does not support getting priority of interrupt vectors +//! one through three which are: +//! - 1: Reset handler +//! - 2: NMI handler +//! - 3: Hard fault handler +//! +//! \param ui32Interrupt specifies the index in the vector table to read priority of. +//! - See \ref IntPrioritySet() for list of valid arguments. +//! +//! \return Returns the interrupt priority: +//! - \ref INT_PRI_LEVEL0 : Highest priority. +//! - \ref INT_PRI_LEVEL1 +//! - \ref INT_PRI_LEVEL2 +//! - \ref INT_PRI_LEVEL3 +//! - \ref INT_PRI_LEVEL4 +//! - \ref INT_PRI_LEVEL5 +//! - \ref INT_PRI_LEVEL6 +//! - \ref INT_PRI_LEVEL7 : Lowest priority. +// +//***************************************************************************** +extern int32_t IntPriorityGet(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Enables an interrupt or system exception. +//! +//! This function enables the specified interrupt in the interrupt controller. +//! +//! \note If a fault condition occurs while the corresponding system exception +//! is disabled, the fault is treated as a Hard Fault. +//! +//! \param ui32Interrupt specifies the index in the vector table to enable. +//! - System exceptions: +//! - INT_MEMMANAGE_FAULT +//! - INT_BUS_FAULT +//! - INT_USAGE_FAULT +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_SPIS_COMB +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_SSI1_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! +//! \return None +//! +//! \sa \ref IntDisable() +// +//***************************************************************************** +extern void IntEnable(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Disables an interrupt or system exception. +//! +//! This function disables the specified interrupt in the interrupt controller. +//! +//! \param ui32Interrupt specifies the index in the vector table to disable. +//! - See \ref IntEnable() for list of valid arguments. +//! +//! \return None +//! +//! \sa \ref IntEnable() +// +//***************************************************************************** +extern void IntDisable(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Pends an interrupt. +//! +//! This function pends the specified interrupt in the interrupt controller. +//! This causes the interrupt controller to execute the corresponding interrupt +//! handler at the next available time, based on the current interrupt state +//! priorities. +//! +//! This interrupt controller automatically clears the pending interrupt once the +//! interrupt handler is executed. +//! +//! \param ui32Interrupt specifies the index in the vector table to pend. +//! - System exceptions: +//! - INT_NMI_FAULT +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_SPIS_COMB +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_SSI1_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! +//! \return None +//! +//! \sa \ref IntEnable() +// +//***************************************************************************** +extern void IntPendSet(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Checks if an interrupt is pending. +//! +//! This function checks the interrupt controller to see if an interrupt is pending. +//! +//! The interrupt must be enabled in order for the corresponding interrupt handler +//! to be executed, so an interrupt can be pending waiting to be enabled or waiting +//! for an interrupt of higher priority to be done executing. +//! +//! \note This function does not support reading pending status for system exceptions +//! (vector table indexes <16). +//! +//! \param ui32Interrupt specifies the index in the vector table to check pending +//! status for. +//! - See \ref IntPendSet() for list of valid arguments (except system exceptions). +//! +//! \return Returns: +//! - \c true : Specified interrupt is pending. +//! - \c false : Specified interrupt is not pending. +// +//***************************************************************************** +extern bool IntPendGet(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Unpends an interrupt. +//! +//! This function unpends the specified interrupt in the interrupt controller. +//! This causes any previously generated interrupts that have not been handled yet +//! (due to higher priority interrupts or the interrupt no having been enabled +//! yet) to be discarded. +//! +//! \note It is not possible to unpend the NMI because it takes effect +//! immediately when being pended. +//! +//! \param ui32Interrupt specifies the index in the vector table to unpend. +//! - See \ref IntPendSet() for list of valid arguments (except NMI). +//! +//! \return None +// +//***************************************************************************** +extern void IntPendClear(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Enables the CPU interrupt. +//! +//! Allows the CPU to respond to interrupts. +//! +//! \return Returns: +//! - \c true : Interrupts were disabled and are now enabled. +//! - \c false : Interrupts were already enabled when the function was called. +// +//***************************************************************************** +__STATIC_INLINE bool +IntMasterEnable(void) +{ + // Enable CPU interrupts. + return(CPUcpsie()); +} + +//***************************************************************************** +// +//! \brief Disables the CPU interrupts with configurable priority. +//! +//! Prevents the CPU from receiving interrupts except NMI and hard fault. This +//! does not affect the set of interrupts enabled in the interrupt controller; +//! it just gates the interrupt from the interrupt controller to the CPU. +//! +//! \return Returns: +//! - \c true : Interrupts were already disabled when the function was called. +//! - \c false : Interrupts were enabled and are now disabled. +// +//***************************************************************************** +__STATIC_INLINE bool +IntMasterDisable(void) +{ + // Disable CPU interrupts. + return(CPUcpsid()); +} + +//***************************************************************************** +// +//! \brief Sets the priority masking level. +//! +//! This function sets the interrupt priority masking level so that all +//! interrupts at the specified or lesser priority level are masked. This +//! can be used to globally disable a set of interrupts with priority below +//! a predetermined threshold. A value of 0 disables priority +//! masking. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 will allow interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! The device supports priority levels 0 through 7. +//! +//! \param ui32PriorityMask is the priority level that will be masked. +//! - 0 : Disable priority masking. +//! - 1 : Allow priority 0 interrupts, mask interrupts with priority 1-7. +//! - 2 : Allow priority 0-1 interrupts, mask interrupts with priority 2-7. +//! - 3 : Allow priority 0-2 interrupts, mask interrupts with priority 3-7. +//! - 4 : Allow priority 0-3 interrupts, mask interrupts with priority 4-7. +//! - 5 : Allow priority 0-4 interrupts, mask interrupts with priority 5-7. +//! - 6 : Allow priority 0-5 interrupts, mask interrupts with priority 6-7. +//! - 7 : Allow priority 0-6 interrupts, mask interrupts with priority 7. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +IntPriorityMaskSet(uint32_t ui32PriorityMask) +{ + CPUbasepriSet(ui32PriorityMask); +} + +//***************************************************************************** +// +//! \brief Gets the priority masking level. +//! +//! This function gets the current setting of the interrupt priority masking +//! level. The value returned is the priority level such that all interrupts +//! of that and lesser priority are masked. A value of 0 means that priority +//! masking is disabled. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 will allow interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! +//! \return Returns the value of the interrupt priority level mask. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +IntPriorityMaskGet(void) +{ + return(CPUbasepriGet()); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_IntRegister + #undef IntRegister + #define IntRegister ROM_IntRegister + #endif + #ifdef ROM_IntUnregister + #undef IntUnregister + #define IntUnregister ROM_IntUnregister + #endif + #ifdef ROM_IntPriorityGroupingSet + #undef IntPriorityGroupingSet + #define IntPriorityGroupingSet ROM_IntPriorityGroupingSet + #endif + #ifdef ROM_IntPriorityGroupingGet + #undef IntPriorityGroupingGet + #define IntPriorityGroupingGet ROM_IntPriorityGroupingGet + #endif + #ifdef ROM_IntPrioritySet + #undef IntPrioritySet + #define IntPrioritySet ROM_IntPrioritySet + #endif + #ifdef ROM_IntPriorityGet + #undef IntPriorityGet + #define IntPriorityGet ROM_IntPriorityGet + #endif + #ifdef ROM_IntEnable + #undef IntEnable + #define IntEnable ROM_IntEnable + #endif + #ifdef ROM_IntDisable + #undef IntDisable + #define IntDisable ROM_IntDisable + #endif + #ifdef ROM_IntPendSet + #undef IntPendSet + #define IntPendSet ROM_IntPendSet + #endif + #ifdef ROM_IntPendGet + #undef IntPendGet + #define IntPendGet ROM_IntPendGet + #endif + #ifdef ROM_IntPendClear + #undef IntPendClear + #define IntPendClear ROM_IntPendClear + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt_doc.h new file mode 100644 index 0000000..ff02174 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt_doc.h @@ -0,0 +1,162 @@ +/****************************************************************************** +* Filename: interrupt_doc.h +* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) +* Revision: 50272 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup interrupt_api +//! @{ +//! \section sec_interrupt Introduction +//! +//! The interrupt controller API provides a set of functions for dealing with the +//! Nested Vectored Interrupt Controller (NVIC). Functions are provided to enable +//! and disable interrupts, register interrupt handlers, and set the priority of +//! interrupts. +//! +//! The event sources that trigger the interrupt lines in the NVIC are controlled by +//! the MCU event fabric. All event sources are statically connected to the NVIC interrupt lines +//! except one which is programmable. For more information about the MCU event fabric, see the +//! [MCU event fabric API](\ref event_api). +//! +//! \section sec_interrupt_api API +//! +//! Interrupts and system exceptions must be individually enabled and disabled through: +//! - \ref IntEnable() +//! - \ref IntDisable() +//! +//! The global CPU interrupt can be enabled and disabled with the following functions: +//! - \ref IntMasterEnable() +//! - \ref IntMasterDisable() +//! +//! This does not affect the individual interrupt enable states. Masking of the CPU +//! interrupt can be used as a simple critical section (only an NMI can interrupt the +//! CPU while the CPU interrupt is disabled), although masking the CPU +//! interrupt can increase the interrupt response time. +//! +//! It is possible to access the NVIC to see if any interrupts are pending and manually +//! clear pending interrupts which have not yet been serviced or set a specific interrupt as +//! pending to be handled based on its priority. Pending interrupts are cleared automatically +//! when the interrupt is accepted and executed. However, the event source which caused the +//! interrupt might need to be cleared manually to avoid re-triggering the corresponding interrupt. +//! The functions to read, clear, and set pending interrupts are: +//! - \ref IntPendGet() +//! - \ref IntPendClear() +//! - \ref IntPendSet() +//! +//! The interrupt prioritization in the NVIC allows handling of higher priority interrupts +//! before lower priority interrupts, as well as allowing preemption of lower priority interrupt +//! handlers by higher priority interrupts. +//! The device supports eight priority levels from 0 to 7 with 0 being the highest priority. +//! The priority of each interrupt source can be set and examined using: +//! - \ref IntPrioritySet() +//! - \ref IntPriorityGet() +//! +//! Interrupts can be masked based on their priority such that interrupts with the same or lower +//! priority than the mask are effectively disabled. This can be configured with: +//! - \ref IntPriorityMaskSet() +//! - \ref IntPriorityMaskGet() +//! +//! Subprioritization is also possible. Instead of having three bits of preemptable +//! prioritization (eight levels), the NVIC can be configured for 3 - M bits of +//! preemptable prioritization and M bits of subpriority. In this scheme, two +//! interrupts with the same preemptable prioritization but different subpriorities +//! do not cause a preemption. Instead, tail chaining is used to process +//! the two interrupts back-to-back. +//! If two interrupts with the same priority (and subpriority if so configured) are +//! asserted at the same time, the one with the lower interrupt number is +//! processed first. +//! Subprioritization is handled by: +//! - \ref IntPriorityGroupingSet() +//! - \ref IntPriorityGroupingGet() +//! +//! \section sec_interrupt_table Interrupt Vector Table +//! +//! The interrupt vector table can be configured in one of two ways: +//! - Statically (at compile time): Vector table is placed in Flash and each entry has a fixed +//! pointer to an interrupt handler (ISR). +//! - Dynamically (at runtime): Vector table is placed in SRAM and each entry can be changed +//! (registered or unregistered) at runtime. This allows a single interrupt to trigger different +//! interrupt handlers (ISRs) depending on which interrupt handler is registered at the time the +//! System CPU responds to the interrupt. +//! +//! When configured, the interrupts must be explicitly enabled in the NVIC through \ref IntEnable() +//! before the CPU can respond to the interrupt (in addition to any interrupt enabling required +//! within the peripheral). +//! +//! \subsection sec_interrupt_table_static Static Vector Table +//! +//! Static registration of interrupt handlers is accomplished by editing the interrupt handler +//! table in the startup code of the application. Texas Instruments provides startup files for +//! each supported compiler ( \ti_code{startup_.c} ) and these startup files include +//! a default static interrupt vector table. +//! All entries, except ResetISR, are declared as \c extern with weak assignment to a default +//! interrupt handler. This allows the user to declare and define a function (in the user's code) +//! with the same name as an entry in the vector table. At compile time, the linker then replaces +//! the pointer to the default interrupt handler in the vector table with the pointer to the +//! interrupt handler defined by the user. +//! +//! Statically configuring the interrupt table provides the fastest interrupt response time +//! because the stacking operation (a write to SRAM on the data bus) is performed in parallel +//! with the interrupt handler table fetch (a read from Flash on the instruction bus), as well +//! as the prefetch of the interrupt handler (assuming it is also in Flash). +//! +//! \subsection sec_interrupt_table_dynamic Dynamic Vector Table +//! +//! Alternatively, interrupts can be registered in the vector table at runtime, thus dynamically. +//! The dynamic vector table is placed in SRAM and the code can then modify the pointers to +//! interrupt handlers throughout the application. +//! +//! DriverLib uses these two functions to modify the dynamic vector table: +//! - \ref IntRegister() : Write a pointer to an interrupt handler into the vector table. +//! - \ref IntUnregister() : Write pointer to default interrupt handler into the vector table. +//! +//! \note First call to \ref IntRegister() initializes the vector table in SRAM by copying the +//! static vector table from Flash and forcing the NVIC to use the dynamic vector table from +//! this point forward. If using the dynamic vector table it is highly recommended to +//! initialize it during the setup phase of the application. The NVIC uses the static vector +//! table in Flash until the application initializes the dynamic vector table in SRAM. +//! +//! Runtime configuration of interrupts adds a small latency to the interrupt response time +//! because the stacking operation (a write to SRAM on the data bus) and the interrupt handler +//! fetch from the vector table (a read from SRAM on the instruction bus) must be performed +//! sequentially. +//! +//! The dynamic vector table, \ref g_pfnRAMVectors, is placed in SRAM in the section called +//! \c vtable_ram which is a section defined in the linker file. By default the linker file +//! places this section at the start of the SRAM but this is configurable by the user. +//! +//! \warning Runtime configuration of interrupt handlers requires that the interrupt +//! handler table is placed on a 256-byte boundary in SRAM (typically, this is +//! at the beginning of SRAM). Failure to do so results in an incorrect vector +//! address being fetched in response to an interrupt. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc.c new file mode 100644 index 0000000..769d864 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc.c @@ -0,0 +1,645 @@ +/****************************************************************************** +* Filename: ioc.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the IOC. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ioc.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef IOCPortConfigureSet + #define IOCPortConfigureSet NOROM_IOCPortConfigureSet + #undef IOCPortConfigureGet + #define IOCPortConfigureGet NOROM_IOCPortConfigureGet + #undef IOCIOShutdownSet + #define IOCIOShutdownSet NOROM_IOCIOShutdownSet + #undef IOCIOModeSet + #define IOCIOModeSet NOROM_IOCIOModeSet + #undef IOCIOIntSet + #define IOCIOIntSet NOROM_IOCIOIntSet + #undef IOCIOPortPullSet + #define IOCIOPortPullSet NOROM_IOCIOPortPullSet + #undef IOCIOHystSet + #define IOCIOHystSet NOROM_IOCIOHystSet + #undef IOCIOInputSet + #define IOCIOInputSet NOROM_IOCIOInputSet + #undef IOCIOSlewCtrlSet + #define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet + #undef IOCIODrvStrengthSet + #define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet + #undef IOCIOPortIdSet + #define IOCIOPortIdSet NOROM_IOCIOPortIdSet + #undef IOCIntEnable + #define IOCIntEnable NOROM_IOCIntEnable + #undef IOCIntDisable + #define IOCIntDisable NOROM_IOCIntDisable + #undef IOCPinTypeGpioInput + #define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput + #undef IOCPinTypeGpioOutput + #define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput + #undef IOCPinTypeUart + #define IOCPinTypeUart NOROM_IOCPinTypeUart + #undef IOCPinTypeSsiMaster + #define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster + #undef IOCPinTypeSsiSlave + #define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave + #undef IOCPinTypeI2c + #define IOCPinTypeI2c NOROM_IOCPinTypeI2c + #undef IOCPinTypeAux + #define IOCPinTypeAux NOROM_IOCPinTypeAux +#endif + +//***************************************************************************** +// +// Set the configuration of an IO port +// +//***************************************************************************** +void +IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, + uint32_t ui32IOConfig) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the port. + HWREG(ui32Reg) = ui32IOConfig | ui32PortId; +} + +//***************************************************************************** +// +// Get the configuration of an IO port +// +//***************************************************************************** +uint32_t +IOCPortConfigureGet(uint32_t ui32IOId) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Return the IO configuration. + return HWREG(ui32Reg); +} + +//***************************************************************************** +// +// Set wake-up on an IO port +// +//***************************************************************************** +void +IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) || + (ui32IOShutdown == IOC_WAKE_ON_LOW) || + (ui32IOShutdown == IOC_WAKE_ON_HIGH)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_WU_CFG_M; + HWREG(ui32Reg) = ui32Config | ui32IOShutdown; +} + + +//***************************************************************************** +// +// Set the IO Mode of an IO Port +// +//***************************************************************************** +void +IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) || + (ui32IOMode == IOC_IOMODE_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_INV)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_IOMODE_M; + HWREG(ui32Reg) = ui32Config | ui32IOMode; +} + +//***************************************************************************** +// +// Setup interrupt detection on an IO Port +// +//***************************************************************************** +void +IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Int == IOC_INT_ENABLE) || + (ui32Int == IOC_INT_DISABLE)); + ASSERT((ui32EdgeDet == IOC_NO_EDGE) || + (ui32EdgeDet == IOC_FALLING_EDGE) || + (ui32EdgeDet == IOC_RISING_EDGE) || + (ui32EdgeDet == IOC_BOTH_EDGES)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_EDGE_IRQ_EN | IOC_IOCFG0_EDGE_DET_M); + HWREG(ui32IOReg) = ui32Config | ((ui32Int ? IOC_IOCFG0_EDGE_IRQ_EN : 0) | ui32EdgeDet); +} + +//***************************************************************************** +// +// Set the pull on an IO port +// +//***************************************************************************** +void +IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the argument. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Pull == IOC_NO_IOPULL) || + (ui32Pull == IOC_IOPULL_UP) || + (ui32Pull == IOC_IOPULL_DOWN)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PULL_CTL_M; + HWREG(ui32IOReg) = ui32Config | ui32Pull; +} + +//***************************************************************************** +// +// Configure hysteresis on and IO port +// +//***************************************************************************** +void +IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Hysteresis == IOC_HYST_ENABLE) || + (ui32Hysteresis == IOC_HYST_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_HYST_EN; + HWREG(ui32IOReg) = ui32Config | ui32Hysteresis; +} + +//***************************************************************************** +// +// Enable/disable IO port as input +// +//***************************************************************************** +void +IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Input == IOC_INPUT_ENABLE) || + (ui32Input == IOC_INPUT_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_IE; + HWREG(ui32IOReg) = ui32Config | ui32Input; +} + +//***************************************************************************** +// +// Enable/disable the slew control on an IO port +// +//***************************************************************************** +void +IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32SlewEnable == IOC_SLEW_ENABLE) || + (ui32SlewEnable == IOC_SLEW_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_SLEW_RED; + HWREG(ui32IOReg) = ui32Config | ui32SlewEnable; +} + +//***************************************************************************** +// +// Configure the drive strength and maximum current of an IO port +// +//***************************************************************************** +void +IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, + uint32_t ui32DrvStrength) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOCurrent == IOC_CURRENT_2MA) || + (ui32IOCurrent == IOC_CURRENT_4MA) || + (ui32IOCurrent == IOC_CURRENT_8MA)); + ASSERT((ui32DrvStrength == IOC_STRENGTH_MIN) || + (ui32DrvStrength == IOC_STRENGTH_MAX) || + (ui32DrvStrength == IOC_STRENGTH_MED) || + (ui32DrvStrength == IOC_STRENGTH_AUTO)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_IOCURR_M | IOC_IOCFG0_IOSTR_M); + HWREG(ui32IOReg) = ui32Config | (ui32IOCurrent | ui32DrvStrength); +} + +//***************************************************************************** +// +// Setup the Port ID for this IO +// +//***************************************************************************** +void +IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PORT_ID_M; + HWREG(ui32IOReg) = ui32Config | ui32PortId; +} + +//***************************************************************************** +// +// Enables individual IO edge detect interrupt +// +//***************************************************************************** +void +IOCIntEnable(uint32_t ui32IOId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Enable the specified interrupt. + ui32Config = HWREG(ui32IOReg); + ui32Config |= IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} + +//***************************************************************************** +// +// Disables individual IO edge interrupt sources +// +//***************************************************************************** +void +IOCIntDisable(uint32_t ui32IOId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Disable the specified interrupt. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} + +//***************************************************************************** +// +// Setup an IO for standard GPIO input +// +//***************************************************************************** +void +IOCPinTypeGpioInput(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Setup the IO for standard input. + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_INPUT); + + // Enable input mode in the GPIO module. + GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_DISABLE); +} + +//***************************************************************************** +// +// Setup an IO for standard GPIO output +// +//***************************************************************************** +void +IOCPinTypeGpioOutput(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Setup the IO for standard input. + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_OUTPUT); + + // Enable output mode in the GPIO module. + GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_ENABLE); +} + +//***************************************************************************** +// +// Configure a set of IOs for standard UART peripheral control +// +//***************************************************************************** +void +IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, + uint32_t ui32Cts, uint32_t ui32Rts) +{ + // Check the arguments. + ASSERT(ui32Base == UART0_BASE); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Cts <= IOID_31) || (ui32Cts == IOID_UNUSED)); + ASSERT((ui32Rts <= IOID_31) || (ui32Rts == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_UART0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_UART0_TX, IOC_STD_OUTPUT); + } + if(ui32Cts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Cts, IOC_PORT_MCU_UART0_CTS, IOC_STD_INPUT); + } + if(ui32Rts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rts, IOC_PORT_MCU_UART0_RTS, IOC_STD_OUTPUT); + } +} + +//***************************************************************************** +// +// Configure a set of IOs for standard SSI peripheral master control +// +//***************************************************************************** +void +IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // Check the arguments. + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_OUTPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_OUTPUT); + } + } +} + +//***************************************************************************** +// +// Configure a set of IOs for standard SSI peripheral slave control +// +//***************************************************************************** +void +IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // Check the arguments. + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_INPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_INPUT); + } + } +} + +//***************************************************************************** +// +// Configure a set of IOs for standard I2C peripheral control +// +//***************************************************************************** +void +IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk) +{ + uint32_t ui32IOConfig; + + // Check the arguments. + ASSERT((ui32Data <= IOID_31) || (ui32Data == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Define the IO configuration parameters. + ui32IOConfig = IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_IOPULL_UP | + IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | + IOC_INT_DISABLE | IOC_IOMODE_OPEN_DRAIN_NORMAL | + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE; + + // Setup the IOs in the desired configuration. + IOCPortConfigureSet(ui32Data, IOC_PORT_MCU_I2C_MSSDA, ui32IOConfig); + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_I2C_MSSCL, ui32IOConfig); +} + + +//***************************************************************************** +// +// Configure an IO for AUX control +// +//***************************************************************************** +void +IOCPinTypeAux(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT((ui32IOId <= IOID_31) || (ui32IOId == IOID_UNUSED)); + + // Setup the IO. + IOCPortConfigureSet(ui32IOId, IOC_PORT_AUX_IO, IOC_STD_INPUT); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc.h new file mode 100644 index 0000000..1b852a8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc.h @@ -0,0 +1,1154 @@ +/****************************************************************************** +* Filename: ioc.h +* Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) +* Revision: 50156 +* +* Description: Defines and prototypes for the IO Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup ioc_api +//! @{ +// +//***************************************************************************** + +#ifndef __IOC_H__ +#define __IOC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ioc.h" +#include "../inc/hw_ints.h" +#include "interrupt.h" +#include "debug.h" +#include "gpio.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define IOCPortConfigureSet NOROM_IOCPortConfigureSet + #define IOCPortConfigureGet NOROM_IOCPortConfigureGet + #define IOCIOShutdownSet NOROM_IOCIOShutdownSet + #define IOCIOModeSet NOROM_IOCIOModeSet + #define IOCIOIntSet NOROM_IOCIOIntSet + #define IOCIOPortPullSet NOROM_IOCIOPortPullSet + #define IOCIOHystSet NOROM_IOCIOHystSet + #define IOCIOInputSet NOROM_IOCIOInputSet + #define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet + #define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet + #define IOCIOPortIdSet NOROM_IOCIOPortIdSet + #define IOCIntEnable NOROM_IOCIntEnable + #define IOCIntDisable NOROM_IOCIntDisable + #define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput + #define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput + #define IOCPinTypeUart NOROM_IOCPinTypeUart + #define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster + #define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave + #define IOCPinTypeI2c NOROM_IOCPinTypeI2c + #define IOCPinTypeAux NOROM_IOCPinTypeAux +#endif + +//***************************************************************************** +// +// Number of IOs (max. total of 32) +// +//***************************************************************************** +#define NUM_IO_MAX 32 + +//***************************************************************************** +// +// The following fields are IO Id for the IOC module +// +//***************************************************************************** +#define IOID_0 0x00000000 // IO Id 0 +#define IOID_1 0x00000001 // IO Id 1 +#define IOID_2 0x00000002 // IO Id 2 +#define IOID_3 0x00000003 // IO Id 3 +#define IOID_4 0x00000004 // IO Id 4 +#define IOID_5 0x00000005 // IO Id 5 +#define IOID_6 0x00000006 // IO Id 6 +#define IOID_7 0x00000007 // IO Id 7 +#define IOID_8 0x00000008 // IO Id 8 +#define IOID_9 0x00000009 // IO Id 9 +#define IOID_10 0x0000000A // IO Id 10 +#define IOID_11 0x0000000B // IO Id 11 +#define IOID_12 0x0000000C // IO Id 12 +#define IOID_13 0x0000000D // IO Id 13 +#define IOID_14 0x0000000E // IO Id 14 +#define IOID_15 0x0000000F // IO Id 15 +#define IOID_16 0x00000010 // IO Id 16 +#define IOID_17 0x00000011 // IO Id 17 +#define IOID_18 0x00000012 // IO Id 18 +#define IOID_19 0x00000013 // IO Id 19 +#define IOID_20 0x00000014 // IO Id 20 +#define IOID_21 0x00000015 // IO Id 21 +#define IOID_22 0x00000016 // IO Id 22 +#define IOID_23 0x00000017 // IO Id 23 +#define IOID_24 0x00000018 // IO Id 24 +#define IOID_25 0x00000019 // IO Id 25 +#define IOID_26 0x0000001A // IO Id 26 +#define IOID_27 0x0000001B // IO Id 27 +#define IOID_28 0x0000001C // IO Id 28 +#define IOID_29 0x0000001D // IO Id 29 +#define IOID_30 0x0000001E // IO Id 30 +#define IOID_31 0x0000001F // IO Id 31 +#define IOID_UNUSED 0xFFFFFFFF // Unused IO Id + +#define IOC_IOID_MASK 0x000000FF // IOC IO Id bit mask + +//***************************************************************************** +// +// Number of IO ports +// +//***************************************************************************** +#define NUM_IO_PORTS 56 + +//***************************************************************************** +// +// IOC Peripheral Port Mapping +// +//***************************************************************************** +#define IOC_PORT_GPIO 0x00000000 // Default general purpose IO usage +#define IOC_PORT_AON_CLK32K 0x00000007 // AON External 32kHz clock +#define IOC_PORT_AUX_IO 0x00000008 // AUX IO Pin +#define IOC_PORT_MCU_SSI0_RX 0x00000009 // MCU SSI0 Receive Pin +#define IOC_PORT_MCU_SSI0_TX 0x0000000A // MCU SSI0 Transmit Pin +#define IOC_PORT_MCU_SSI0_FSS 0x0000000B // MCU SSI0 FSS Pin +#define IOC_PORT_MCU_SSI0_CLK 0x0000000C // MCU SSI0 Clock Pin +#define IOC_PORT_MCU_I2C_MSSDA 0x0000000D // MCU I2C Data Pin +#define IOC_PORT_MCU_I2C_MSSCL 0x0000000E // MCU I2C Clock Pin +#define IOC_PORT_MCU_UART0_RX 0x0000000F // MCU UART0 Receive Pin +#define IOC_PORT_MCU_UART0_TX 0x00000010 // MCU UART0 Transmit Pin +#define IOC_PORT_MCU_UART0_CTS 0x00000011 // MCU UART0 Clear To Send Pin +#define IOC_PORT_MCU_UART0_RTS 0x00000012 // MCU UART0 Request To Send Pin +#define IOC_PORT_MCU_PORT_EVENT0 0x00000017 // MCU PORT EVENT 0 +#define IOC_PORT_MCU_PORT_EVENT1 0x00000018 // MCU PORT EVENT 1 +#define IOC_PORT_MCU_PORT_EVENT2 0x00000019 // MCU PORT EVENT 2 +#define IOC_PORT_MCU_PORT_EVENT3 0x0000001A // MCU PORT EVENT 3 +#define IOC_PORT_MCU_PORT_EVENT4 0x0000001B // MCU PORT EVENT 4 +#define IOC_PORT_MCU_PORT_EVENT5 0x0000001C // MCU PORT EVENT 5 +#define IOC_PORT_MCU_PORT_EVENT6 0x0000001D // MCU PORT EVENT 6 +#define IOC_PORT_MCU_PORT_EVENT7 0x0000001E // MCU PORT EVENT 7 +#define IOC_PORT_MCU_SWV 0x00000020 // Serial Wire Viewer +#define IOC_PORT_MCU_SSI1_RX 0x00000021 // MCU SSI1 Receive Pin +#define IOC_PORT_MCU_SSI1_TX 0x00000022 // MCU SSI1 Transmit Pin +#define IOC_PORT_MCU_SSI1_FSS 0x00000023 // MCU SSI1 FSS Pin +#define IOC_PORT_MCU_SSI1_CLK 0x00000024 // MCU SSI1 Clock Pin +#define IOC_PORT_MCU_I2S_AD0 0x00000025 // MCU I2S Data Pin 0 +#define IOC_PORT_MCU_I2S_AD1 0x00000026 // MCU I2S Data Pin 1 +#define IOC_PORT_MCU_I2S_WCLK 0x00000027 // MCU I2S Frame/Word Clock +#define IOC_PORT_MCU_I2S_BCLK 0x00000028 // MCU I2S Bit Clock +#define IOC_PORT_MCU_I2S_MCLK 0x00000029 // MCU I2S Master clock 2 +#define IOC_PORT_RFC_TRC 0x0000002E // RF Core Tracer +#define IOC_PORT_RFC_GPO0 0x0000002F // RC Core Data Out Pin 0 +#define IOC_PORT_RFC_GPO1 0x00000030 // RC Core Data Out Pin 1 +#define IOC_PORT_RFC_GPO2 0x00000031 // RC Core Data Out Pin 2 +#define IOC_PORT_RFC_GPO3 0x00000032 // RC Core Data Out Pin 3 +#define IOC_PORT_RFC_GPI0 0x00000033 // RC Core Data In Pin 0 +#define IOC_PORT_RFC_GPI1 0x00000034 // RC Core Data In Pin 1 +#define IOC_PORT_RFC_SMI_DL_OUT 0x00000035 // RF Core SMI Data Link Out +#define IOC_PORT_RFC_SMI_DL_IN 0x00000036 // RF Core SMI Data Link in +#define IOC_PORT_RFC_SMI_CL_OUT 0x00000037 // RF Core SMI Command Link Out +#define IOC_PORT_RFC_SMI_CL_IN 0x00000038 // RF Core SMI Command Link In + +//***************************************************************************** +// +// Defines for enabling/disabling an IO +// +//***************************************************************************** +#define IOC_SLEW_ENABLE 0x00001000 +#define IOC_SLEW_DISABLE 0x00000000 +#define IOC_INPUT_ENABLE 0x20000000 +#define IOC_INPUT_DISABLE 0x00000000 +#define IOC_HYST_ENABLE 0x40000000 +#define IOC_HYST_DISABLE 0x00000000 + +//***************************************************************************** +// +// Defines that can be used to set the shutdown mode of an IO +// +//***************************************************************************** +#define IOC_NO_WAKE_UP 0x00000000 +#define IOC_WAKE_ON_LOW 0x10000000 +#define IOC_WAKE_ON_HIGH 0x18000000 + +//***************************************************************************** +// +// Defines that can be used to set the IO Mode of an IO +// +//***************************************************************************** +#define IOC_IOMODE_NORMAL 0x00000000 // Normal Input/Output +#define IOC_IOMODE_INV 0x01000000 // Inverted Input/Output +#define IOC_IOMODE_OPEN_DRAIN_NORMAL \ + 0x04000000 // Open Drain, Normal Input/Output +#define IOC_IOMODE_OPEN_DRAIN_INV \ + 0x05000000 // Open Drain, Inverted + // Input/Output +#define IOC_IOMODE_OPEN_SRC_NORMAL \ + 0x06000000 // Open Source, Normal Input/Output +#define IOC_IOMODE_OPEN_SRC_INV \ + 0x07000000 // Open Source, Inverted + // Input/Output + +//***************************************************************************** +// +// Defines that can be used to set the edge detection on an IO +// +//***************************************************************************** +#define IOC_NO_EDGE 0x00000000 // No edge detection +#define IOC_FALLING_EDGE 0x00010000 // Edge detection on falling edge +#define IOC_RISING_EDGE 0x00020000 // Edge detection on rising edge +#define IOC_BOTH_EDGES 0x00030000 // Edge detection on both edges +#define IOC_INT_ENABLE 0x00040000 // Enable interrupt on edge detect +#define IOC_INT_DISABLE 0x00000000 // Disable interrupt on edge detect +#define IOC_INT_M 0x00070000 // Int config mask + +//***************************************************************************** +// +// Defines that be used to set pull on an IO +// +//***************************************************************************** +#define IOC_NO_IOPULL 0x00006000 // No IO pull +#define IOC_IOPULL_UP 0x00004000 // Pull up +#define IOC_IOPULL_DOWN 0x00002000 // Pull down +#define IOC_IOPULL_M 0x00006000 // Pull config mask +#define IOC_IOPULL_M 0x00006000 + +//***************************************************************************** +// +// Defines that can be used to select the drive strength of an IO +// +//***************************************************************************** +#define IOC_CURRENT_2MA 0x00000000 // 2mA drive strength +#define IOC_CURRENT_4MA 0x00000400 // 4mA drive strength +#define IOC_CURRENT_8MA 0x00000800 // 4 or 8mA drive strength + +#define IOC_STRENGTH_AUTO 0x00000000 // Automatic Drive Strength + // (2/4/8 mA @ VVDS) +#define IOC_STRENGTH_MAX 0x00000300 // Maximum Drive Strength + // (2/4/8 mA @ 1.8V) +#define IOC_STRENGTH_MED 0x00000200 // Medium Drive Strength + // (2/4/8 mA @ 2.5V) +#define IOC_STRENGTH_MIN 0x00000100 // Minimum Drive Strength + // (2/4/8 mA @ 3.3V) + +//***************************************************************************** +// +// Defines for standard IO setup +// +//***************************************************************************** +#define IOC_STD_INPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE ) +#define IOC_STD_OUTPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_DISABLE ) + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Set the configuration of an IO port. +//! +//! This function is used to configure the functionality of an IO. +//! +//! The \c ui32IOId parameter specifies which IO to configure. +//! +//! The \c ui32PortId parameter specifies which functional peripheral to hook +//! up to this IO. +//! +//! The \c ui32IOConfig parameter consists of a bitwise OR'ed value of all +//! the available configuration modes +//! +//! \note All IO Ports are tied to a specific functionality in a sub module +//! except for the \ref IOC_PORT_AUX_IO. Each of the IOs in the AUX domain are +//! hardcoded to a specific IO. When enabling one or more pins for the AUX +//! domain, they should all be configured to using \ref IOC_PORT_AUX_IO. +//! +//! \param ui32IOId defines the IO to configure and must be one of the following: +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32PortId selects the functional IO port to connect. +//! The available IO ports are: +//! - \ref IOC_PORT_GPIO +//! - \ref IOC_PORT_AON_CLK32K +//! - \ref IOC_PORT_AUX_IO +//! - \ref IOC_PORT_MCU_SSI0_RX +//! - \ref IOC_PORT_MCU_SSI0_TX +//! - \ref IOC_PORT_MCU_SSI0_FSS +//! - \ref IOC_PORT_MCU_SSI0_CLK +//! - \ref IOC_PORT_MCU_I2C_MSSDA +//! - \ref IOC_PORT_MCU_I2C_MSSCL +//! - \ref IOC_PORT_MCU_UART0_RX +//! - \ref IOC_PORT_MCU_UART0_TX +//! - \ref IOC_PORT_MCU_UART0_CTS +//! - \ref IOC_PORT_MCU_UART0_RTS +//! - \ref IOC_PORT_MCU_PORT_EVENT0 +//! - \ref IOC_PORT_MCU_PORT_EVENT1 +//! - \ref IOC_PORT_MCU_PORT_EVENT2 +//! - \ref IOC_PORT_MCU_PORT_EVENT3 +//! - \ref IOC_PORT_MCU_PORT_EVENT4 +//! - \ref IOC_PORT_MCU_PORT_EVENT5 +//! - \ref IOC_PORT_MCU_PORT_EVENT6 +//! - \ref IOC_PORT_MCU_PORT_EVENT7 +//! - \ref IOC_PORT_MCU_SWV +//! - \ref IOC_PORT_MCU_SSI1_RX +//! - \ref IOC_PORT_MCU_SSI1_TX +//! - \ref IOC_PORT_MCU_SSI1_FSS +//! - \ref IOC_PORT_MCU_SSI1_CLK +//! - \ref IOC_PORT_MCU_I2S_AD0 +//! - \ref IOC_PORT_MCU_I2S_AD1 +//! - \ref IOC_PORT_MCU_I2S_WCLK +//! - \ref IOC_PORT_MCU_I2S_BCLK +//! - \ref IOC_PORT_MCU_I2S_MCLK +//! - \ref IOC_PORT_RFC_TRC +//! - \ref IOC_PORT_RFC_GPO0 +//! - \ref IOC_PORT_RFC_GPO1 +//! - \ref IOC_PORT_RFC_GPO2 +//! - \ref IOC_PORT_RFC_GPO3 +//! - \ref IOC_PORT_RFC_GPI0 +//! - \ref IOC_PORT_RFC_GPI1 +//! \param ui32IOConfig is the IO configuration consisting of +//! the bitwise OR of all configuration modes: +//! - Input/output mode: +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_IOMODE_INV +//! - \ref IOC_IOMODE_OPEN_DRAIN_NORMAL +//! - \ref IOC_IOMODE_OPEN_DRAIN_INV +//! - \ref IOC_IOMODE_OPEN_SRC_NORMAL +//! - \ref IOC_IOMODE_OPEN_SRC_INV +//! - Wake-up mode (from shutdown): +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_WAKE_ON_LOW +//! - \ref IOC_WAKE_ON_HIGH +//! - Edge detection mode: +//! - \ref IOC_NO_EDGE +//! - \ref IOC_FALLING_EDGE +//! - \ref IOC_RISING_EDGE +//! - \ref IOC_BOTH_EDGES +//! - Interrupt mode on edge detection: +//! - \ref IOC_INT_ENABLE +//! - \ref IOC_INT_DISABLE +//! - Pull mode: +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_IOPULL_UP +//! - \ref IOC_IOPULL_DOWN +//! - Input mode: +//! - \ref IOC_INPUT_ENABLE +//! - \ref IOC_INPUT_DISABLE +//! - Hysteresis mode: +//! - \ref IOC_HYST_ENABLE +//! - \ref IOC_HYST_DISABLE +//! - Slew rate reduction mode: +//! - \ref IOC_SLEW_ENABLE +//! - \ref IOC_SLEW_DISABLE +//! - Current mode (see \ref IOCIODrvStrengthSet() for more details): +//! - \ref IOC_CURRENT_2MA : Low-Current mode. Min 2 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_4MA : High-Current mode. Min 4 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_8MA : Extended-Current mode. Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - Drive strength mode: +//! - \ref IOC_STRENGTH_AUTO : Automatic drive strength based on battery voltage. +//! - \ref IOC_STRENGTH_MAX : Maximum drive strength, used for low supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MED : Medium drive strength, used for medium supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MIN : Minimum drive strength, used for high supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! +//! \return None +// +//***************************************************************************** +extern void IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, + uint32_t ui32IOConfig); + +//***************************************************************************** +// +//! \brief Get the configuration of an IO port. +//! +//! This function is used for getting the configuration of an IO. +//! +//! Each IO port has a dedicated register for setting up the IO. This function +//! returns the current configuration for the given IO. +//! +//! \param ui32IOId selects the IO to return the configuration for. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return Returns the IO Port configuration. +//! See \ref IOCPortConfigureSet() for configuration options. +// +//***************************************************************************** +extern uint32_t IOCPortConfigureGet(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Set wake-up mode from shutdown on an IO port. +//! +//! This function is used to set the wake-up mode from shutdown of an IO. +//! +//! IO must be configured as input in order for wakeup to work. See \ref IOCIOInputSet(). +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32IOShutdown enables wake-up from shutdown on LOW/HIGH by this IO port. +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_WAKE_ON_LOW +//! - \ref IOC_WAKE_ON_HIGH +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown); + + +//***************************************************************************** +// +//! \brief Set the IO Mode of an IO Port. +//! +//! This function is used to set the input/output mode of an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32IOMode sets the port IO Mode. +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_IOMODE_INV +//! - \ref IOC_IOMODE_OPEN_DRAIN_NORMAL +//! - \ref IOC_IOMODE_OPEN_DRAIN_INV +//! - \ref IOC_IOMODE_OPEN_SRC_NORMAL +//! - \ref IOC_IOMODE_OPEN_SRC_INV +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode); + +//***************************************************************************** +// +//! \brief Setup edge detection and interrupt generation on an IO Port. +//! +//! This function is used to setup the edge detection and interrupt generation on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Int enables/disables interrupt generation on this IO port. +//! - \ref IOC_INT_ENABLE +//! - \ref IOC_INT_DISABLE +//! \param ui32EdgeDet enables/disables edge detection events on this IO port. +//! - \ref IOC_NO_EDGE +//! - \ref IOC_FALLING_EDGE +//! - \ref IOC_RISING_EDGE +//! - \ref IOC_BOTH_EDGES +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, + uint32_t ui32EdgeDet); + +//***************************************************************************** +// +//! \brief Set the pull on an IO port. +//! +//! This function is used to configure the pull on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Pull enables/disables pull on this IO port. +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_IOPULL_UP +//! - \ref IOC_IOPULL_DOWN +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull); + +//***************************************************************************** +// +//! \brief Configure hysteresis on and IO port. +//! +//! This function is used to enable/disable hysteresis on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Hysteresis enable/disable input hysteresis on IO. +//! - \ref IOC_HYST_ENABLE +//! - \ref IOC_HYST_DISABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis); + +//***************************************************************************** +// +//! \brief Enable/disable IO port as input. +//! +//! This function is used to enable/disable input on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Input enable/disable input on IO. +//! - \ref IOC_INPUT_ENABLE +//! - \ref IOC_INPUT_DISABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input); + +//***************************************************************************** +// +//! \brief Configure slew rate on an IO port. +//! +//! This function is used to enable/disable reduced slew rate on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32SlewEnable enables/disables reduced slew rate on an output. +//! - \ref IOC_SLEW_ENABLE +//! - \ref IOC_SLEW_DISABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable); + +//***************************************************************************** +// +//! \brief Configure the drive strength source and current mode of an IO port. +//! +//! The drive strength of an IO is configured by a combination of multiple settings +//! in several modules. The drive strength source \ti_code{ui32DrvStrength} is used for controlling +//! drive strength at different supply levels. When set to AUTO the battery monitor +//! (BATMON) adjusts the drive strength to compensate for changes in supply voltage +//! in order to keep IO current constant. Alternatively, drive strength source can +//! be controlled manually by selecting one of three options each of which is configurable +//! in the AON IOC by \ref AONIOCDriveStrengthSet(). +//! +//! Each drive strength source has three current modes: Low-Current (LC), High-Current (HC), and +//! Extended-Current (EC), and typically drive strength doubles when selecting a higher mode. +//! I.e. EC = 2 x HC = 4 x LC. +//! +//! \note Not all IOs support Extended-Current mode. See datasheet for more information +//! on the specific device. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32IOCurrent selects the IO current mode. +//! - \ref IOC_CURRENT_2MA : Low-Current mode. Min 2 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_4MA : High-Current mode. Min 4 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_8MA : Extended-Current mode. Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! \param ui32DrvStrength sets the source for drive strength control of the IO port. +//! - \ref IOC_STRENGTH_AUTO : Automatic drive strength based on battery voltage. +//! - \ref IOC_STRENGTH_MAX : Maximum drive strength, used for low supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MED : Medium drive strength, used for medium supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MIN : Minimum drive strength, used for high supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! +//! \return None +// +//***************************************************************************** +extern void IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, + uint32_t ui32DrvStrength); + +//***************************************************************************** +// +//! \brief Setup the Port ID for this IO. +//! +//! The \c ui32PortId specifies which functional peripheral to hook up to this +//! IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32PortId selects the port to map to the IO. +//! - \ref IOC_PORT_GPIO +//! - \ref IOC_PORT_AON_CLK32K +//! - \ref IOC_PORT_AUX_IO +//! - \ref IOC_PORT_MCU_SSI0_RX +//! - \ref IOC_PORT_MCU_SSI0_TX +//! - \ref IOC_PORT_MCU_SSI0_FSS +//! - \ref IOC_PORT_MCU_SSI0_CLK +//! - \ref IOC_PORT_MCU_I2C_MSSDA +//! - \ref IOC_PORT_MCU_I2C_MSSCL +//! - \ref IOC_PORT_MCU_UART0_RX +//! - \ref IOC_PORT_MCU_UART0_TX +//! - \ref IOC_PORT_MCU_UART0_CTS +//! - \ref IOC_PORT_MCU_UART0_RTS +//! - \ref IOC_PORT_MCU_PORT_EVENT0 +//! - \ref IOC_PORT_MCU_PORT_EVENT1 +//! - \ref IOC_PORT_MCU_PORT_EVENT2 +//! - \ref IOC_PORT_MCU_PORT_EVENT3 +//! - \ref IOC_PORT_MCU_PORT_EVENT4 +//! - \ref IOC_PORT_MCU_PORT_EVENT5 +//! - \ref IOC_PORT_MCU_PORT_EVENT6 +//! - \ref IOC_PORT_MCU_PORT_EVENT7 +//! - \ref IOC_PORT_MCU_SWV +//! - \ref IOC_PORT_MCU_SSI1_RX +//! - \ref IOC_PORT_MCU_SSI1_TX +//! - \ref IOC_PORT_MCU_SSI1_FSS +//! - \ref IOC_PORT_MCU_SSI1_CLK +//! - \ref IOC_PORT_MCU_I2S_AD0 +//! - \ref IOC_PORT_MCU_I2S_AD1 +//! - \ref IOC_PORT_MCU_I2S_WCLK +//! - \ref IOC_PORT_MCU_I2S_BCLK +//! - \ref IOC_PORT_MCU_I2S_MCLK +//! - \ref IOC_PORT_RFC_TRC +//! - \ref IOC_PORT_RFC_GPO0 +//! - \ref IOC_PORT_RFC_GPO1 +//! - \ref IOC_PORT_RFC_GPO2 +//! - \ref IOC_PORT_RFC_GPO3 +//! - \ref IOC_PORT_RFC_GPI0 +//! - \ref IOC_PORT_RFC_GPI1 +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId); + +//***************************************************************************** +// +//! \brief Register an interrupt handler for an IO edge interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific IO interrupts must be enabled via \ref IOCIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! IOC interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +IOCIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_AON_GPIO_EDGE, pfnHandler); + + // Enable the IO edge interrupt. + IntEnable(INT_AON_GPIO_EDGE); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a IO edge interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when an IO edge interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +IOCIntUnregister(void) +{ + // Disable the interrupts. + IntDisable(INT_AON_GPIO_EDGE); + + // Unregister the interrupt handler. + IntUnregister(INT_AON_GPIO_EDGE); +} + +//***************************************************************************** +// +//! \brief Enables individual IO edge detect interrupt. +//! +//! This function enables the indicated IO edge interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IOId is the IO to enable edge detect interrupt for. +//! +//! \return None +// +//***************************************************************************** +extern void IOCIntEnable(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Disables individual IO edge interrupt sources. +//! +//! This function disables the indicated IO edge interrupt source. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IOId is the IO edge interrupt source to be disabled. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +extern void IOCIntDisable(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Clears the IO edge interrupt source. +//! +//! The specified IO edge interrupt source is cleared, so that it no longer +//! asserts. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IOId is the IO causing the interrupt. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +IOCIntClear(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Clear the requested interrupt source by clearing the event. + GPIO_clearEventDio(ui32IOId); +} + +//***************************************************************************** +// +//! \brief Returns the status of the IO interrupts. +//! +//! \param ui32IOId is the IO to get the status for. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE uint32_t +IOCIntStatus(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the event status. + return (GPIO_getEventDio(ui32IOId)); +} + + +//***************************************************************************** +// +//! \brief Setup an IO for standard GPIO input. +//! +//! Setup an IO for standard GPIO input with the following configuration: +//! - Port ID: +//! - \ref IOC_PORT_GPIO +//! - Configuration: +//! - \ref IOC_CURRENT_2MA +//! - \ref IOC_STRENGTH_AUTO +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_SLEW_DISABLE +//! - \ref IOC_HYST_DISABLE +//! - \ref IOC_NO_EDGE +//! - \ref IOC_INT_DISABLE +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_INPUT_ENABLE +//! +//! \param ui32IOId is the IO to setup for GPIO input +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeGpioInput(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Setup an IO for standard GPIO output. +//! +//! Setup an IO for standard GPIO output with the following configuration: +//! - Port ID: +//! - \ref IOC_PORT_GPIO +//! - Configuration: +//! - \ref IOC_CURRENT_2MA +//! - \ref IOC_STRENGTH_AUTO +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_SLEW_DISABLE +//! - \ref IOC_HYST_DISABLE +//! - \ref IOC_NO_EDGE +//! - \ref IOC_INT_DISABLE +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_INPUT_DISABLE +//! +//! \param ui32IOId is the IO to setup for GPIO output +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeGpioOutput(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard UART peripheral control. +//! +//! The UART pins must be properly configured for the UART peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s). Other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! \note If a UART pin is not intended to be used, then the parameter in the +//! function should be \ref IOID_UNUSED. +//! +//! \param ui32Base is the base address of the UART module. +//! \param ui32Rx is the IO Id of the IO to use as UART Receive. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Tx is the IO Id of the IO to use as UART Transmit. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Cts is the IO Id of the IO to use for UART Clear to send. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Rts is the IO Id of the IO to use for UART Request to send. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Cts, + uint32_t ui32Rts); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard SSI peripheral master control. +//! +//! \param ui32Base is the base address of the SSI module to connect to the IOs +//! \param ui32Rx is the IO to connect to the SSI MISO line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Tx is the IO to connect to the SSI MOSI line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Fss is the IO to connect to the SSI FSS line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Clk is the IO to connect to the SSI Clock output line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard SSI peripheral slave control. +//! +//! \param ui32Base is the base address of the SSI module to connect to the IOs +//! \param ui32Rx is the IO to connect to the SSI MOSI line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Tx is the IO to connect to the SSI MISO line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Fss is the IO to connect to the SSI FSS line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Clk is the IO to connect to the SSI Clock input line. +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard I2C peripheral control. +//! +//! \param ui32Base is the base address of the I2C module to connect to the IOs +//! \param ui32Data is the I2C data line +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Clk is the I2C input clock +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, + uint32_t ui32Clk); + + +//***************************************************************************** +// +//! \brief Configure an IO for AUX control. +//! +//! Use this function to enable AUX to control a specific IO. Please note, that +//! when using AUX to control the IO, the input/output control in the IOC is +//! bypassed and completely controlled by AUX, so enabling or disabling input +//! in the IOC has no effect. +//! +//! \note The IOs available for AUX control can vary from device to device. +//! +//! \param ui32IOId is the IO to setup for AUX usage. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeAux(uint32_t ui32IOId); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_IOCPortConfigureSet + #undef IOCPortConfigureSet + #define IOCPortConfigureSet ROM_IOCPortConfigureSet + #endif + #ifdef ROM_IOCPortConfigureGet + #undef IOCPortConfigureGet + #define IOCPortConfigureGet ROM_IOCPortConfigureGet + #endif + #ifdef ROM_IOCIOShutdownSet + #undef IOCIOShutdownSet + #define IOCIOShutdownSet ROM_IOCIOShutdownSet + #endif + #ifdef ROM_IOCIOModeSet + #undef IOCIOModeSet + #define IOCIOModeSet ROM_IOCIOModeSet + #endif + #ifdef ROM_IOCIOIntSet + #undef IOCIOIntSet + #define IOCIOIntSet ROM_IOCIOIntSet + #endif + #ifdef ROM_IOCIOPortPullSet + #undef IOCIOPortPullSet + #define IOCIOPortPullSet ROM_IOCIOPortPullSet + #endif + #ifdef ROM_IOCIOHystSet + #undef IOCIOHystSet + #define IOCIOHystSet ROM_IOCIOHystSet + #endif + #ifdef ROM_IOCIOInputSet + #undef IOCIOInputSet + #define IOCIOInputSet ROM_IOCIOInputSet + #endif + #ifdef ROM_IOCIOSlewCtrlSet + #undef IOCIOSlewCtrlSet + #define IOCIOSlewCtrlSet ROM_IOCIOSlewCtrlSet + #endif + #ifdef ROM_IOCIODrvStrengthSet + #undef IOCIODrvStrengthSet + #define IOCIODrvStrengthSet ROM_IOCIODrvStrengthSet + #endif + #ifdef ROM_IOCIOPortIdSet + #undef IOCIOPortIdSet + #define IOCIOPortIdSet ROM_IOCIOPortIdSet + #endif + #ifdef ROM_IOCIntEnable + #undef IOCIntEnable + #define IOCIntEnable ROM_IOCIntEnable + #endif + #ifdef ROM_IOCIntDisable + #undef IOCIntDisable + #define IOCIntDisable ROM_IOCIntDisable + #endif + #ifdef ROM_IOCPinTypeGpioInput + #undef IOCPinTypeGpioInput + #define IOCPinTypeGpioInput ROM_IOCPinTypeGpioInput + #endif + #ifdef ROM_IOCPinTypeGpioOutput + #undef IOCPinTypeGpioOutput + #define IOCPinTypeGpioOutput ROM_IOCPinTypeGpioOutput + #endif + #ifdef ROM_IOCPinTypeUart + #undef IOCPinTypeUart + #define IOCPinTypeUart ROM_IOCPinTypeUart + #endif + #ifdef ROM_IOCPinTypeSsiMaster + #undef IOCPinTypeSsiMaster + #define IOCPinTypeSsiMaster ROM_IOCPinTypeSsiMaster + #endif + #ifdef ROM_IOCPinTypeSsiSlave + #undef IOCPinTypeSsiSlave + #define IOCPinTypeSsiSlave ROM_IOCPinTypeSsiSlave + #endif + #ifdef ROM_IOCPinTypeI2c + #undef IOCPinTypeI2c + #define IOCPinTypeI2c ROM_IOCPinTypeI2c + #endif + #ifdef ROM_IOCPinTypeAux + #undef IOCPinTypeAux + #define IOCPinTypeAux ROM_IOCPinTypeAux + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __IOC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc_doc.h new file mode 100644 index 0000000..cd35eff --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc_doc.h @@ -0,0 +1,92 @@ +/****************************************************************************** +* Filename: ioc_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup ioc_api +//! @{ +//! \section sec_ioc Introduction +//! +//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO). +//! The IOC consists of two APIs: +//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it. +//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc. +//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is +//! routed to a DIO for external use. +//! +//! For more information on the AON IOC see the [AON IOC API](\ref aonioc_api). +//! +//! \note The output driver of a DIO is not configured by the IOC API (except for drive strength); instead, it is controlled by the +//! peripheral module which is selected to control the DIO. +//! +//! A DIO is considered "software controlled" if it is configured for GPIO control which allows the +//! System CPU to set the value of the DIO via the [GPIO API](\ref gpio_api). Alternatively, a DIO +//! can be "hardware controlled" if it is controlled by other modules than GPIO. +//! +//! \section sec_ioc_api API +//! +//! The API functions can be grouped like this: +//! +//! Configure all settings at the same time: +//! - \ref IOCPortConfigureSet() +//! - \ref IOCPortConfigureGet() +//! +//! Configure individual settings: +//! - \ref IOCIODrvStrengthSet() +//! - \ref IOCIOHystSet() +//! - \ref IOCIOInputSet() +//! - \ref IOCIOIntSet() +//! - \ref IOCIOModeSet() +//! - \ref IOCIOPortIdSet() +//! - \ref IOCIOPortPullSet() +//! - \ref IOCIOShutdownSet() +//! - \ref IOCIOSlewCtrlSet() +//! +//! Handle edge detection events: +//! - \ref IOCIntEnable() +//! - \ref IOCIntDisable() +//! - \ref IOCIntClear() +//! - \ref IOCIntStatus() +//! - \ref IOCIntRegister() +//! - \ref IOCIntUnregister() +//! +//! Configure IOCs for typical use cases (can also be used as example code): +//! - \ref IOCPinTypeAux() +//! - \ref IOCPinTypeGpioInput() +//! - \ref IOCPinTypeGpioOutput() +//! - \ref IOCPinTypeI2c() +//! - \ref IOCPinTypeSsiMaster() +//! - \ref IOCPinTypeSsiSlave() +//! - \ref IOCPinTypeUart() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/osc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/osc.c new file mode 100644 index 0000000..a695408 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/osc.c @@ -0,0 +1,468 @@ +/****************************************************************************** +* Filename: osc.c +* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) +* Revision: 54539 +* +* Description: Driver for setting up the system Oscillators +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_fcfg1.h" +#include "aon_batmon.h" +#include "aon_rtc.h" +#include "osc.h" +#include "setup_rom.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef OSCClockSourceSet + #define OSCClockSourceSet NOROM_OSCClockSourceSet + #undef OSCClockSourceGet + #define OSCClockSourceGet NOROM_OSCClockSourceGet + #undef OSCHF_GetStartupTime + #define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime + #undef OSCHF_TurnOnXosc + #define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc + #undef OSCHF_AttemptToSwitchToXosc + #define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc + #undef OSCHF_SwitchToRcOscTurnOffXosc + #define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc + #undef OSCHF_DebugGetCrystalAmplitude + #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude + #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude + #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #undef OSC_HPOSCRelativeFrequencyOffsetGet + #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet + #undef OSC_AdjustXoscHfCapArray + #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray + #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert +#endif + + +//***************************************************************************** +// +// OSCHF switch time calculator defines and globals +// +//***************************************************************************** + +#define RTC_CV_TO_MS(x) (( 1000 * ( x )) >> 16 ) +#define RTC_CV_TO_US(x) (( 1000000 * ( x )) >> 16 ) + +typedef struct { + uint32_t previousStartupTimeInUs ; + uint32_t timeXoscOff_CV ; + uint32_t timeXoscOn_CV ; + uint32_t timeXoscStable_CV ; + int32_t tempXoscOff ; +} OscHfGlobals_t; + +static OscHfGlobals_t oscHfGlobals; + +//***************************************************************************** +// +// Configure the oscillator input to the a source clock. +// +//***************************************************************************** +void +OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc) +{ + // Check the arguments. + ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || + (ui32SrcClk & OSC_SRC_CLK_MF) || + (ui32SrcClk & OSC_SRC_CLK_HF)); + ASSERT((ui32Osc == OSC_RCOSC_HF) || + (ui32Osc == OSC_RCOSC_LF) || + (ui32Osc == OSC_XOSC_HF) || + (ui32Osc == OSC_XOSC_LF)); + + // Request the high frequency source clock (using 24 MHz XTAL) + if(ui32SrcClk & OSC_SRC_CLK_HF) + { + // Enable the HF XTAL as HF clock source + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S, + ui32Osc); + } + + // Configure the medium frequency source clock + if(ui32SrcClk & OSC_SRC_CLK_MF) + { + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_S, + ui32Osc); + } + + // Configure the low frequency source clock. + if(ui32SrcClk & OSC_SRC_CLK_LF) + { + // Change the clock source. + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S, + ui32Osc); + } +} + +//***************************************************************************** +// +// Get the source clock settings +// +//***************************************************************************** +uint32_t +OSCClockSourceGet(uint32_t ui32SrcClk) +{ + uint32_t ui32ClockSource; + + // Check the arguments. + ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || + (ui32SrcClk & OSC_SRC_CLK_HF)); + + // Return the source for the selected clock. + if(ui32SrcClk == OSC_SRC_CLK_LF) + { + ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_SCLK_LF_SRC_M, + DDI_0_OSC_STAT0_SCLK_LF_SRC_S); + } + else + { + ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_SCLK_HF_SRC_M, + DDI_0_OSC_STAT0_SCLK_HF_SRC_S); + } + return (ui32ClockSource); +} + +//***************************************************************************** +// +// Returns maximum startup time (in microseconds) of XOSC_HF +// +//***************************************************************************** +uint32_t +OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ) +{ + uint32_t deltaTimeSinceXoscOnInMs ; + int32_t deltaTempSinceXoscOn ; + uint32_t newStartupTimeInUs ; + + deltaTimeSinceXoscOnInMs = RTC_CV_TO_MS( AONRTCCurrentCompareValueGet() - oscHfGlobals.timeXoscOn_CV ); + deltaTempSinceXoscOn = AONBatMonTemperatureGetDegC() - oscHfGlobals.tempXoscOff; + + if ( deltaTempSinceXoscOn < 0 ) { + deltaTempSinceXoscOn = -deltaTempSinceXoscOn; + } + + if ( (( timeUntilWakeupInMs + deltaTimeSinceXoscOnInMs ) > 3000 ) || + ( deltaTempSinceXoscOn > 5 ) || + ( oscHfGlobals.timeXoscStable_CV < oscHfGlobals.timeXoscOn_CV ) || + ( oscHfGlobals.previousStartupTimeInUs == 0 ) ) + { + newStartupTimeInUs = 2000; + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) { + newStartupTimeInUs = (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & + CCFG_MODE_CONF_1_XOSC_MAX_START_M ) >> + CCFG_MODE_CONF_1_XOSC_MAX_START_S ) * 125; + // Note: CCFG startup time is "in units of 100us" adding 25% margin results in *125 + } + } else { + newStartupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV ); + newStartupTimeInUs += ( newStartupTimeInUs >> 2 ); // Add 25 percent margin + if ( newStartupTimeInUs < oscHfGlobals.previousStartupTimeInUs ) { + newStartupTimeInUs = oscHfGlobals.previousStartupTimeInUs; + } + } + + if ( newStartupTimeInUs < 200 ) { + newStartupTimeInUs = 200; + } + if ( newStartupTimeInUs > 4000 ) { + newStartupTimeInUs = 4000; + } + return ( newStartupTimeInUs ); +} + + +//***************************************************************************** +// +// Turns on XOSC_HF (but without switching to XOSC_HF) +// +//***************************************************************************** +void +OSCHF_TurnOnXosc( void ) +{ +#if ( defined( ROM_OSCClockSourceSet )) + ROM_OSCClockSourceSet( OSC_SRC_CLK_HF | OSC_SRC_CLK_MF, OSC_XOSC_HF ); +#else + OSCClockSourceSet( OSC_SRC_CLK_HF | OSC_SRC_CLK_MF, OSC_XOSC_HF ); +#endif + oscHfGlobals.timeXoscOn_CV = AONRTCCurrentCompareValueGet(); +} + + +//***************************************************************************** +// +// Switch to XOSC_HF if XOSC_HF is ready. +// +//***************************************************************************** +bool +OSCHF_AttemptToSwitchToXosc( void ) +{ + uint32_t startupTimeInUs; + uint32_t prevLimmit25InUs; + +#if ( defined( ROM_OSCClockSourceGet )) + if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF ) +#else + if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF ) +#endif + { + // Already on XOSC - nothing to do + return ( 1 ); + } + if ( OSCHfSourceReady()) { + OSCHfSourceSwitch(); + + // Store startup time, but limit to 25 percent reduction each time. + oscHfGlobals.timeXoscStable_CV = AONRTCCurrentCompareValueGet(); + startupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV ); + prevLimmit25InUs = oscHfGlobals.previousStartupTimeInUs; + prevLimmit25InUs -= ( prevLimmit25InUs >> 2 ); // 25 percent margin + oscHfGlobals.previousStartupTimeInUs = startupTimeInUs; + if ( prevLimmit25InUs > startupTimeInUs ) { + oscHfGlobals.previousStartupTimeInUs = prevLimmit25InUs; + } + return ( 1 ); + } + return ( 0 ); +} + + +//***************************************************************************** +// +// Switch to RCOSC_HF and turn off XOSC_HF +// +//***************************************************************************** +void +OSCHF_SwitchToRcOscTurnOffXosc( void ) +{ + // Set SCLK_HF and SCLK_MF to RCOSC_HF without checking + // Doing this anyway to keep HF and MF in sync +#if ( defined( ROM_OSCClockSourceSet )) + ROM_OSCClockSourceSet( OSC_SRC_CLK_HF | OSC_SRC_CLK_MF, OSC_RCOSC_HF ); +#else + OSCClockSourceSet( OSC_SRC_CLK_HF | OSC_SRC_CLK_MF, OSC_RCOSC_HF ); +#endif + + // Do the switching if not already running on RCOSC_HF +#if ( defined( ROM_OSCClockSourceGet )) + if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF ) +#else + if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF ) +#endif + { + OSCHfSourceSwitch(); + } + + oscHfGlobals.timeXoscOff_CV = AONRTCCurrentCompareValueGet(); + oscHfGlobals.tempXoscOff = AONBatMonTemperatureGetDegC(); +} + +//***************************************************************************** +// +// Adjust the XOSC HF cap array relative to the factory setting +// +//***************************************************************************** +void +OSC_AdjustXoscHfCapArray( int32_t capArrDelta ) +{ + // read the MODE_CONF register in CCFG + uint32_t ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + // Clear CAP_MODE and the CAPARRAY_DELATA field + ccfg_ModeConfReg &= ~( CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M | CCFG_MODE_CONF_XOSC_CAP_MOD_M ); + // Insert new delta value + ccfg_ModeConfReg |= ((((uint32_t)capArrDelta) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) & CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ); + // Update the HW register with the new delta value + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg )); +} + +//***************************************************************************** +// +// Calculate the temperature dependent relative frequency offset of HPOSC +// +//***************************************************************************** +int32_t +OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ) +{ + // Estimate HPOSC frequency, using temperature and curve fitting parameters + + uint32_t fitParams = HWREG( FCFG1_BASE + FCFG1_O_FREQ_OFFSET ); + // Extract the P0,P1,P2 params, and sign extend them via shifting up/down + int32_t paramP0 = (((int32_t)( fitParams << ( 32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S ))) + >> ( 32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W )); + int32_t paramP1 = (((int32_t)( fitParams << ( 32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S ))) + >> ( 32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W )); + int32_t paramP2 = (((int32_t)( fitParams << ( 32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S ))) + >> ( 32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W )); + + uint32_t fitParP3 = HWREG( FCFG1_BASE + FCFG1_O_MISC_CONF_2 ); + // Extract the P3 param, and sign extend via shifting up/down + int32_t paramP3 = (((int32_t)( fitParP3 << ( 32 - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S ))) + >> ( 32 - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W )); + + // Now we can find the HPOSC freq offset, given as a signed variable d, expressed by: + // + // F_HPOSC = F_nom * (1 + d/(2^22)) , where: F_HPOSC = HPOSC frequency + // F_nom = nominal clock source frequency (e.g. 48.000 MHz) + // d = describes relative freq offset + + // We can estimate the d variable, using temperature compensation parameters: + // + // d = P0 + P1*(t - T0) + P2*(t - T0)^2 + P3*(t - T0)^3, where: P0,P1,P2,P3 are curve fitting parameters from FCFG1 + // t = current temperature (from temp sensor) in deg C + // T0 = 27 deg C (fixed temperature constant) + int32_t tempDelta = (tempDegC - 27); + int32_t tempDeltaX2 = tempDelta * tempDelta; + int32_t d = paramP0 + ((tempDelta*paramP1)>>3) + ((tempDeltaX2*paramP2)>>10) + ((tempDeltaX2*tempDelta*paramP3)>>18); + + return ( d ); +} + +//***************************************************************************** +// +// Converts the relative frequency offset of HPOSC to the RF Core parameter format. +// +//***************************************************************************** +int16_t +OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ) +{ + // The input argument, hereby referred to simply as "d", describes the frequency offset + // of the HPOSC relative to the nominal frequency in this way: + // + // F_HPOSC = F_nom * (1 + d/(2^22)) + // + // But for use by the radio, to compensate the frequency error, we need to find the + // frequency offset "rfcFreqOffset" defined in the following format: + // + // F_nom = F_HPOSC * (1 + rfCoreFreqOffset/(2^22)) + // + // To derive "rfCoreFreqOffset" from "d" we combine the two above equations and get: + // + // (1 + rfCoreFreqOffset/(2^22)) = (1 + d/(2^22))^-1 + // + // Which can be rewritten into: + // + // rfCoreFreqOffset = -d*(2^22) / ((2^22) + d) + // + // = -d * [ 1 / (1 + d/(2^22)) ] + // + // To avoid doing a 64-bit division due to the (1 + d/(2^22))^-1 expression, + // we can use Taylor series (Maclaurin series) to approximate it: + // + // 1 / (1 - x) ~= 1 + x + x^2 + x^3 + x^4 + ... etc (Maclaurin series) + // + // In our case, we have x = - d/(2^22), and we only include up to the first + // order term of the series, as the second order term ((d^2)/(2^44)) is very small: + // + // freqError ~= -d + d^2/(2^22) (+ small approximation error) + // + // The approximation error is negligible for our use. + + int32_t rfCoreFreqOffset = -HPOSC_RelFreqOffset + (( HPOSC_RelFreqOffset * HPOSC_RelFreqOffset ) >> 22 ); + + return ( rfCoreFreqOffset ); +} + +//***************************************************************************** +// +// Get crystal amplitude (assuming crystal is running). +// +//***************************************************************************** +uint32_t +OSCHF_DebugGetCrystalAmplitude( void ) +{ + uint32_t oscCfgRegCopy ; + uint32_t startTime ; + uint32_t deltaTime ; + uint32_t ampValue ; + + // The specified method is as follows: + // 1. Set minimum interval between oscillator amplitude calibrations. + // (Done by setting PER_M=0 and PER_E=1) + // 2. Wait approximately 4 milliseconds in order to measure over a + // moderately large number of calibrations. + // 3. Read out the crystal amplitude value from the peek detector. + // 4. Restore original oscillator amplitude calibrations interval. + // 5. Return crystal amplitude value converted to millivolt. + oscCfgRegCopy = HWREG( AON_WUC_BASE + AON_WUC_O_OSCCFG ); + HWREG( AON_WUC_BASE + AON_WUC_O_OSCCFG ) = ( 1 << AON_WUC_OSCCFG_PER_E_S ); + startTime = AONRTCCurrentCompareValueGet(); + do { + deltaTime = AONRTCCurrentCompareValueGet() - startTime; + } while ( deltaTime < ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT ))); + ampValue = ( HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_STAT1 ) & + DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M ) >> + DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S ; + HWREG( AON_WUC_BASE + AON_WUC_O_OSCCFG ) = oscCfgRegCopy; + + return ( ampValue * 15 ); +} + +//***************************************************************************** +// +// Get the expected average crystal amplitude. +// +//***************************************************************************** +uint32_t +OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ) +{ + uint32_t ampCompTh1 ; + uint32_t highThreshold ; + uint32_t lowThreshold ; + + ampCompTh1 = HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_AMPCOMPTH1 ); + highThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M ) >> + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S ; + lowThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M ) >> + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S ; + + return ((( highThreshold + lowThreshold ) * 15 ) >> 1 ); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/osc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/osc.h new file mode 100644 index 0000000..4281a96 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/osc.h @@ -0,0 +1,562 @@ +/****************************************************************************** +* Filename: osc.h +* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) +* Revision: 54539 +* +* Description: Defines and prototypes for the system oscillator control. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup osc_api +//! @{ +// +//***************************************************************************** + +#ifndef __OSC_H__ +#define __OSC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ddi.h" +#include "../inc/hw_ddi_0_osc.h" +#include "rom.h" +#include "ddi.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define OSCClockSourceSet NOROM_OSCClockSourceSet + #define OSCClockSourceGet NOROM_OSCClockSourceGet + #define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime + #define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc + #define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc + #define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc + #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude + #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet + #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray + #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert +#endif + +//***************************************************************************** +// +// Defines for the High Frequency XTAL Power mode +// +//***************************************************************************** +#define LOW_POWER_XOSC 1 +#define HIGH_POWER_XOSC 0 + +//***************************************************************************** +// +// Defines for the High Frequency XTAL Power mode +// +//***************************************************************************** +#define OSC_SRC_CLK_HF 0x00000001 +#define OSC_SRC_CLK_MF 0x00000002 +#define OSC_SRC_CLK_LF 0x00000004 + +#define OSC_RCOSC_HF 0x00000000 +#define OSC_XOSC_HF 0x00000001 +#define OSC_RCOSC_LF 0x00000002 +#define OSC_XOSC_LF 0x00000003 + +#define SCLK_HF_RCOSC_HF 0 +#define SCLK_HF_XOSC_HF 1 + +#define SCLK_MF_RCOSC_HF 0 +#define SCLK_MF_XOSC_HF 1 + +#define SCLK_LF_FROM_RCOSC_HF 0 +#define SCLK_LF_FROM_XOSC_HF 1 +#define SCLK_LF_FROM_RCOSC_LF 2 +#define SCLK_LF_FROM_XOSC_LF 3 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Set Power Mode for High Frequency XTAL Oscillator. +//! +//! \param ui32Mode is the power mode for the HF XTAL. +//! - \ref LOW_POWER_XOSC +//! - \ref HIGH_POWER_XOSC +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +OSCXHfPowerModeSet(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == LOW_POWER_XOSC) || + (ui32Mode == HIGH_POWER_XOSC)); + + // Change the power mode. + DDI16BitWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE, + ui32Mode); +} + +//***************************************************************************** +// +//! \brief Enables OSC clock loss event detection. +//! +//! Enables the clock loss event flag to be raised if a clock loss is detected. +//! +//! \note OSC clock loss event must be disabled before SCLK_LF clock source is +//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the +//! change is confirmed (by calling \ref OSCClockSourceGet()). +//! +//! \return None +//! +//! \sa \ref OSCClockLossEventDisable() +// +//***************************************************************************** +__STATIC_INLINE void +OSCClockLossEventEnable( void ) +{ + DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 1 ); +} + +//***************************************************************************** +// +//! \brief Disables OSC clock loss event detection. +//! +//! Disabling the OSC clock loss event does also clear the clock loss event flag. +//! +//! \note OSC clock loss event must be disabled before SCLK_LF clock source is +//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the +//! change is confirmed (by calling \ref OSCClockSourceGet()). +//! +//! \return None +//! +//! \sa \ref OSCClockLossEventEnable() +// +//***************************************************************************** +__STATIC_INLINE void +OSCClockLossEventDisable( void ) +{ + DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 0 ); +} + +//***************************************************************************** +// +//! \brief Configure the oscillator input to the a source clock. +//! +//! Use this function to set the oscillator source for one or more of the +//! system source clocks. +//! +//! When selecting the high frequency clock source (OSC_SRC_CLK_HF), this function will not do +//! the actual switch. Enabling the high frequency XTAL can take several hundred +//! micro seconds, so the actual switch is done in a separate function, \ref OSCHfSourceSwitch(), +//! leaving System CPU free to perform other tasks as the XTAL starts up. +//! +//! \note The High Frequency (\ref OSC_SRC_CLK_HF) and Medium Frequency +//! (\ref OSC_SRC_CLK_MF) can only be derived from the high frequency +//! oscillator. The Low Frequency source clock (\ref OSC_SRC_CLK_LF) can be +//! derived from all 4 oscillators. +//! +//! \note If enabling \ref OSC_XOSC_LF it is not safe to go to powerdown/shutdown +//! until the LF clock is running which can be checked using \ref OSCClockSourceGet(). +//! +//! \note Clock loss reset generation must be disabled before SCLK_LF (\ref OSC_SRC_CLK_LF) +//! clock source is changed and remain disabled until the change is confirmed. +//! +//! \param ui32SrcClk is the source clocks to configure. +//! - \ref OSC_SRC_CLK_HF +//! - \ref OSC_SRC_CLK_MF +//! - \ref OSC_SRC_CLK_LF +//! \param ui32Osc is the oscillator that drives the source clock. +//! - \ref OSC_RCOSC_HF +//! - \ref OSC_XOSC_HF +//! - \ref OSC_RCOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF) +//! - \ref OSC_XOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF) +//! +//! \sa \ref OSCClockSourceGet(), \ref OSCHfSourceSwitch() +//! +//! \return None +// +//***************************************************************************** +extern void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc); + +//***************************************************************************** +// +//! \brief Get the source clock settings. +//! +//! Use this function to get the oscillator source for one of the system source +//! clocks. +//! +//! \param ui32SrcClk is the source clock to check. +//! - \ref OSC_SRC_CLK_HF +//! - \ref OSC_SRC_CLK_MF +//! - \ref OSC_SRC_CLK_LF +//! +//! \return Returns the type of oscillator that drives the clock source. +//! - \ref OSC_RCOSC_HF +//! - \ref OSC_XOSC_HF +//! - \ref OSC_RCOSC_LF +//! - \ref OSC_XOSC_LF +//! +//! \sa \ref OSCClockSourceSet(), \ref OSCHfSourceSwitch() +// +//***************************************************************************** +extern uint32_t OSCClockSourceGet(uint32_t ui32SrcClk); + +//***************************************************************************** +// +//! \brief Check if the HF clock source is ready to be switched. +//! +//! If a request to switch the HF clock source has been made, this function +//! can be used to check if the clock source is ready to be switched. +//! +//! Once the HF clock source is ready the switch can be performed by calling +//! the \ref OSCHfSourceSwitch() +//! +//! \return Returns status of HF clock source: +//! - \c true : HF clock source is ready. +//! - \c false : HF clock source is \b not ready. +// +//***************************************************************************** +__STATIC_INLINE bool +OSCHfSourceReady(void) +{ + // Return the readiness of the HF clock source + return (DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M, + DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S)) ? + true : false; +} + +//***************************************************************************** +// +//! \brief Switch the high frequency clock. +//! +//! When switching the HF clock source the clock period might be prolonged +//! leaving the clock 'stuck-at' high or low for a few cycles. To ensure that +//! this does not coincide with a read access to the Flash, potentially +//! freezing the device, the HF clock source switch must be executed from ROM. +//! +//! \note This function will not return until the clock source has been +//! switched. It is left to the programmer to ensure, that there is a pending +//! request for a HF clock source switch before this function is called. +//! +//! \return None +//! +//! \sa \ref OSCClockSourceSet() +// +//***************************************************************************** +__STATIC_INLINE void +OSCHfSourceSwitch(void) +{ + // Switch the HF clock source + HapiHFSourceSafeSwitch(); +} + +//***************************************************************************** +// +//! \brief Returns maximum startup time (in microseconds) of XOSC_HF. +//! +//! The startup time depends on several factors. This function calculates the +//! maximum startup time based on statistical information. +//! +//! \param timeUntilWakeupInMs indicates how long time (milliseconds) to the +//! startup will occur. +//! +//! \return Time margin to use in microseconds. +// +//***************************************************************************** +extern uint32_t OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ); + +//***************************************************************************** +// +//! \brief Turns on XOSC_HF (but without switching to XOSC_HF). +//! +//! This function simply indicates the need for XOSC_HF to the hardware which +//! initiates the XOSC_HF startup. +//! +//! \return None +// +//***************************************************************************** +extern void OSCHF_TurnOnXosc( void ); + +//***************************************************************************** +// +//! \brief Switch to XOSC_HF if XOSC_HF is ready. +//! +//! This is a non-blocking function checking if the XOSC_HF is ready and +//! performs the switching if ready. The function is somewhat blocking in the +//! case where switching is performed. +//! +//! \return Returns status of the XOSC_HF switching: +//! - \c true : Switching to XOSC_HF has occurred. +//! - \c false : Switching has not occurred. +// +//***************************************************************************** +extern bool OSCHF_AttemptToSwitchToXosc( void ); + +//***************************************************************************** +// +//! \brief Switch to RCOSC_HF and turn off XOSC_HF. +//! +//! This operation takes approximately 50 microseconds (can be shorter if +//! RCOSC_HF already was running). +//! +//! \return None +// +//***************************************************************************** +extern void OSCHF_SwitchToRcOscTurnOffXosc( void ); + +//***************************************************************************** +// +//! \brief Get crystal amplitude (assuming crystal is running). +//! +//! \note This is a debug function only. +//! It is hence not recommended to call this function in normal operation. +//! +//! This function uses an on-chip ADC and peak detector for reading the crystal +//! amplitude. The measurement time is set to 4 milliseconds and this function +//! does not return before the measurement is done. +//! +//! Expected value is \ref OSCHF_DebugGetExpectedAverageCrystalAmplitude +/- 50 millivolt. +//! +//! \return Returns crystal amplitude in millivolt. +//! +//! \sa OSCHF_DebugGetExpectedAverageCrystalAmplitude() +// +//***************************************************************************** +extern uint32_t OSCHF_DebugGetCrystalAmplitude( void ); + +//***************************************************************************** +// +//! \brief Get the expected average crystal amplitude. +//! +//! \note This is a debug function only. +//! It is hence not recommended to call this function in normal operation. +//! +//! This function read the configured high and low thresholds and returns +//! the mean value converted to millivolt. +//! +//! \return Returns expected average crystal amplitude in millivolt. +//! +//! \sa OSCHF_DebugGetCrystalAmplitude() +// +//***************************************************************************** +extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ); + +//***************************************************************************** +// +//! \brief Calculate the temperature dependent relative frequency offset of HPOSC +//! +//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature. +//! The frequency offset from the nominal value can be predicted based on +//! second order linear interpolation using coefficients measured in chip +//! production and stored as factory configuration parameters. +//! +//! This function calculates the relative frequency offset, defined as: +//! 
+//!     F_HPOSC = F_nom * (1 + d/(2^22))
+//!
+//! where +//! - F_HPOSC is the current HPOSC frequency. +//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. +//! - d is the relative frequency offset (the value returned). +//! +//! By knowing the relative frequency offset it is then possible to compensate +//! any timing related values accordingly. +//! +//! \param tempDegC is the chip temperature in degrees Celsius. Use the +//! function \ref AONBatMonTemperatureGetDegC() to get current chip temperature. +//! +//! \return Returns the relative frequency offset parameter d. +//! +//! \sa OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(), AONBatMonTemperatureGetDegC() +// +//***************************************************************************** +extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ); + +//***************************************************************************** +// +//! \brief Adjust the XOSC HF cap array relative to the factory setting +//! +//! The cap array factory setting (FCFG) can be converted to a number in the range 0 - 63. +//! Both this function and the customer configuration (CCFG) setting can apply a delta to the FCFG setting. +//! The CCFG setting is automatically applied at boot time (See ../startup_files/ccfg.c). +//! Calling this function will discard the CCFG setting and adjust relative to the FCFG setting. +//! +//! \note Adjusted value will not take effect before XOSC_HF is stopped and restarted +//! +//! \param capArrDelta specifies number of step to adjust the cap array relative to the factory setting. +//! +//! \return None +// +//***************************************************************************** +extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta ); + +//***************************************************************************** +// +//! \brief Converts the relative frequency offset of HPOSC to the RF Core parameter format. +//! +//! The HPOSC (High Precision Oscillator) clock is used by the RF Core. +//! To compensate for a frequency offset in the frequency of the clock source, +//! a frequency offset parameter can be provided as part of the radio configuration +//! override setting list to enable compensation of the RF synthesizer frequency, +//! symbol timing, and radio timer to still achieve correct frequencies. +//! +//! The RF Core takes a relative frequency offset parameter defined differently +//! compared to the relative frequency offset parameter returned from function +//! \ref OSC_HPOSCRelativeFrequencyOffsetGet() and thus needs to be converted: +//! 
+//!     F_nom = F_HPOSC * (1 + RfCoreRelFreqOffset/(2^22))
+//!
+//! where +//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. +//! - F_HPOSC is the current HPOSC frequency. +//! - RfCoreRelFreqOffset is the relative frequency offset in the "RF Core" format (the value returned). +//! +//! \param HPOSC_RelFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet() +//! +//! \return Returns the relative frequency offset in RF Core format. +//! +//! \sa OSC_HPOSCRelativeFrequencyOffsetGet() +// +//***************************************************************************** +extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_OSCClockSourceSet + #undef OSCClockSourceSet + #define OSCClockSourceSet ROM_OSCClockSourceSet + #endif + #ifdef ROM_OSCClockSourceGet + #undef OSCClockSourceGet + #define OSCClockSourceGet ROM_OSCClockSourceGet + #endif + #ifdef ROM_OSCHF_GetStartupTime + #undef OSCHF_GetStartupTime + #define OSCHF_GetStartupTime ROM_OSCHF_GetStartupTime + #endif + #ifdef ROM_OSCHF_TurnOnXosc + #undef OSCHF_TurnOnXosc + #define OSCHF_TurnOnXosc ROM_OSCHF_TurnOnXosc + #endif + #ifdef ROM_OSCHF_AttemptToSwitchToXosc + #undef OSCHF_AttemptToSwitchToXosc + #define OSCHF_AttemptToSwitchToXosc ROM_OSCHF_AttemptToSwitchToXosc + #endif + #ifdef ROM_OSCHF_SwitchToRcOscTurnOffXosc + #undef OSCHF_SwitchToRcOscTurnOffXosc + #define OSCHF_SwitchToRcOscTurnOffXosc ROM_OSCHF_SwitchToRcOscTurnOffXosc + #endif + #ifdef ROM_OSCHF_DebugGetCrystalAmplitude + #undef OSCHF_DebugGetCrystalAmplitude + #define OSCHF_DebugGetCrystalAmplitude ROM_OSCHF_DebugGetCrystalAmplitude + #endif + #ifdef ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude + #define OSCHF_DebugGetExpectedAverageCrystalAmplitude ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #endif + #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetGet + #undef OSC_HPOSCRelativeFrequencyOffsetGet + #define OSC_HPOSCRelativeFrequencyOffsetGet ROM_OSC_HPOSCRelativeFrequencyOffsetGet + #endif + #ifdef ROM_OSC_AdjustXoscHfCapArray + #undef OSC_AdjustXoscHfCapArray + #define OSC_AdjustXoscHfCapArray ROM_OSC_AdjustXoscHfCapArray + #endif + #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __OSC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/prcm.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/prcm.c new file mode 100644 index 0000000..232c96c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/prcm.c @@ -0,0 +1,652 @@ +/****************************************************************************** +* Filename: prcm.c +* Revised: 2018-10-18 17:33:32 +0200 (Thu, 18 Oct 2018) +* Revision: 52954 +* +* Description: Driver for the PRCM. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "prcm.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef PRCMInfClockConfigureSet + #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet + #undef PRCMInfClockConfigureGet + #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet + #undef PRCMAudioClockConfigSet + #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet + #undef PRCMAudioClockConfigSetOverride + #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride + #undef PRCMAudioClockInternalSource + #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource + #undef PRCMAudioClockExternalSource + #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource + #undef PRCMPowerDomainOn + #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn + #undef PRCMPowerDomainOff + #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff + #undef PRCMPeripheralRunEnable + #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable + #undef PRCMPeripheralRunDisable + #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable + #undef PRCMPeripheralSleepEnable + #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable + #undef PRCMPeripheralSleepDisable + #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable + #undef PRCMPeripheralDeepSleepEnable + #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable + #undef PRCMPeripheralDeepSleepDisable + #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable + #undef PRCMPowerDomainStatus + #define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus + #undef PRCMDeepSleep + #define PRCMDeepSleep NOROM_PRCMDeepSleep +#endif + + +//***************************************************************************** +// +// Arrays that maps the "peripheral set" number (which is stored in +// bits[11:8] of the PRCM_PERIPH_* defines) to the PRCM register that +// contains the relevant bit for that peripheral. +// +//***************************************************************************** + +// Run mode registers +static const uint32_t g_pui32RCGCRegs[] = +{ + PRCM_O_GPTCLKGR , // Index 0 + PRCM_O_SSICLKGR , // Index 1 + PRCM_O_UARTCLKGR , // Index 2 + PRCM_O_I2CCLKGR , // Index 3 + PRCM_O_SECDMACLKGR , // Index 4 + PRCM_O_GPIOCLKGR , // Index 5 + PRCM_O_I2SCLKGR // Index 6 +}; + +// Sleep mode registers +static const uint32_t g_pui32SCGCRegs[] = +{ + PRCM_O_GPTCLKGS , // Index 0 + PRCM_O_SSICLKGS , // Index 1 + PRCM_O_UARTCLKGS , // Index 2 + PRCM_O_I2CCLKGS , // Index 3 + PRCM_O_SECDMACLKGS , // Index 4 + PRCM_O_GPIOCLKGS , // Index 5 + PRCM_O_I2SCLKGS // Index 6 +}; + +// Deep sleep mode registers +static const uint32_t g_pui32DCGCRegs[] = +{ + PRCM_O_GPTCLKGDS , // Index 0 + PRCM_O_SSICLKGDS , // Index 1 + PRCM_O_UARTCLKGDS , // Index 2 + PRCM_O_I2CCLKGDS , // Index 3 + PRCM_O_SECDMACLKGDS , // Index 4 + PRCM_O_GPIOCLKGDS , // Index 5 + PRCM_O_I2SCLKGDS // Index 6 +}; + +//***************************************************************************** +// +// This macro extracts the array index out of the peripheral number +// +//***************************************************************************** +#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf) + +//***************************************************************************** +// +// This macro extracts the peripheral instance number and generates bit mask +// +//***************************************************************************** +#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0x1f)) + + +//***************************************************************************** +// +// Configure the infrastructure clock. +// +//***************************************************************************** +void +PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode) +{ + uint32_t ui32Divisor; + + // Check the arguments. + ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || + (ui32ClkDiv == PRCM_CLOCK_DIV_2) || + (ui32ClkDiv == PRCM_CLOCK_DIV_8) || + (ui32ClkDiv == PRCM_CLOCK_DIV_32)); + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32Divisor = 0; + + // Find the correct division factor. + if(ui32ClkDiv == PRCM_CLOCK_DIV_1) + { + ui32Divisor = 0x0; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_2) + { + ui32Divisor = 0x1; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_8) + { + ui32Divisor = 0x2; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_32) + { + ui32Divisor = 0x3; + } + + // Determine the correct power mode set the division factor accordingly. + if(ui32PowerMode == PRCM_RUN_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor; + } +} + +//***************************************************************************** +// +// Use this function to get the infrastructure clock configuration +// +//***************************************************************************** +uint32_t +PRCMInfClockConfigureGet(uint32_t ui32PowerMode) +{ + uint32_t ui32ClkDiv; + uint32_t ui32Divisor; + + // Check the arguments. + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32ClkDiv = 0; + ui32Divisor = 0; + + // Determine the correct power mode. + if(ui32PowerMode == PRCM_RUN_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR); + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS); + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS); + } + + // Find the correct division factor. + if(ui32ClkDiv == 0x0) + { + ui32Divisor = PRCM_CLOCK_DIV_1; + } + else if(ui32ClkDiv == 0x1) + { + ui32Divisor = PRCM_CLOCK_DIV_2; + } + else if(ui32ClkDiv == 0x2) + { + ui32Divisor = PRCM_CLOCK_DIV_8; + } + else if(ui32ClkDiv == 0x3) + { + ui32Divisor = PRCM_CLOCK_DIV_32; + } + + // Return the clock division factor. + return ui32Divisor; +} + + +//***************************************************************************** +// +// Configure the audio clock generation +// +//***************************************************************************** +void +PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate) +{ + uint32_t ui32Reg; + uint32_t ui32MstDiv; + uint32_t ui32BitDiv; + uint32_t ui32WordDiv; + + // Check the arguments. + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) || + (ui32SampleRate == I2S_SAMPLE_RATE_24K) || + (ui32SampleRate == I2S_SAMPLE_RATE_32K) || + (ui32SampleRate == I2S_SAMPLE_RATE_48K)); + + ui32MstDiv = 0; + ui32BitDiv = 0; + ui32WordDiv = 0; + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Define the clock division factors for the audio interface. + switch(ui32SampleRate) + { + case I2S_SAMPLE_RATE_16K : + ui32MstDiv = 6; + ui32BitDiv = 60; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_24K : + ui32MstDiv = 4; + ui32BitDiv = 40; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_32K : + ui32MstDiv = 3; + ui32BitDiv = 30; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_48K : + ui32MstDiv = 2; + ui32BitDiv = 20; + ui32WordDiv = 25; + break; + } + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity. + ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} + +//***************************************************************************** +// +// Configure the audio clock generation with manual setting of clock divider. +// +//***************************************************************************** +void +PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, + uint32_t ui32BitDiv, uint32_t ui32WordDiv) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity. + ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} + +//***************************************************************************** +// +// Configure the audio clocks for I2S module +// +//***************************************************************************** +void +PRCMAudioClockConfigOverride(uint8_t ui8SamplingEdge, + uint8_t ui8WCLKPhase, + uint32_t ui32MstDiv, + uint32_t ui32BitDiv, + uint32_t ui32WordDiv) +{ + // Check the arguments. + ASSERT( ui8BitsPerSample == PRCM_WCLK_SINGLE_PHASE + || ui8BitsPerSample == PRCM_WCLK_DUAL_PHASE + || ui8BitsPerSample == PRCM_WCLK_USER_DEF); + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui8WCLKPhase) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity and enable it. + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = (ui8SamplingEdge << PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S) | + (ui8WCLKPhase << PRCM_I2SCLKCTL_WCLK_PHASE_S ) | + (1 << PRCM_I2SCLKCTL_EN_S ); +} + +//***************************************************************************** +// +// Configure the clocks as "internally generated". +// +//***************************************************************************** +void PRCMAudioClockInternalSource(void) +{ + HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 1; +} + +//***************************************************************************** +// +// Configure the clocks as "externally generated". +// +//***************************************************************************** +void PRCMAudioClockExternalSource(void) +{ + HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 0; +} + +//***************************************************************************** +// +// Turn power on in power domains in the MCU domain +// +//***************************************************************************** +void +PRCMPowerDomainOn(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Assert the request to power on the right domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 1; + // The PDCTL1RFC access is meant to "be used by RFC in autonomous mode", but keeping + // it for compatibility on already ROM'ed products (since this is a ROM function). + // RFC power domain is on if ( PRCM_O_PDCTL0RFC || PRCM_O_PDCTL1RFC ). + HWREG(PRCM_BASE + PRCM_O_PDCTL1RFC ) = 1; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 1; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 1; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 1; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 1; + } +} + +//***************************************************************************** +// +// Turn off a specific power domain +// +//***************************************************************************** +void +PRCMPowerDomainOff(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Assert the request to power off the right domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 0; + // The PDCTL1RFC access is meant to "be used by RFC in autonomous mode", but keeping + // it for compatibility on already ROM'ed products (since this is a ROM function). + // RFC power domain is on if ( PRCM_O_PDCTL0RFC || PRCM_O_PDCTL1RFC ). + HWREG(PRCM_BASE + PRCM_O_PDCTL1RFC ) = 0; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 0; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 0; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 0; + } +} + +//***************************************************************************** +// +// Enables a peripheral in Run mode +// +//***************************************************************************** +void +PRCMPeripheralRunEnable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable module in Run Mode. + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Disables a peripheral in Run mode +// +//***************************************************************************** +void +PRCMPeripheralRunDisable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable module in Run Mode. + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Enables a peripheral in sleep mode +// +//***************************************************************************** +void +PRCMPeripheralSleepEnable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable this peripheral in sleep mode. + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Disables a peripheral in sleep mode +// +//***************************************************************************** +void +PRCMPeripheralSleepDisable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable this peripheral in sleep mode + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Enables a peripheral in deep-sleep mode +// +//***************************************************************************** +void +PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable this peripheral in deep-sleep mode. + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Disables a peripheral in deep-sleep mode +// +//***************************************************************************** +void +PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable this peripheral in Deep Sleep mode. + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Get the status for a specific power domain +// +//***************************************************************************** +uint32_t +PRCMPowerDomainStatus(uint32_t ui32Domains) +{ + bool bStatus; + uint32_t ui32StatusRegister0; + uint32_t ui32StatusRegister1; + + // Check the arguments. + ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE | + PRCM_DOMAIN_SERIAL | + PRCM_DOMAIN_PERIPH))); + + bStatus = true; + ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0); + ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1); + + // Return the correct power status. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + bStatus = bStatus && + ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) || + (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON)); + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON); + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON); + } + + // Return the status. + return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF); +} + +//***************************************************************************** +// +// Put the processor into deep-sleep mode +// +//***************************************************************************** +void +PRCMDeepSleep(void) +{ + // Enable deep-sleep. + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // Wait for an interrupt. + CPUwfi(); + + // Disable deep-sleep so that a future sleep will work correctly. + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/prcm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/prcm.h new file mode 100644 index 0000000..663afd1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/prcm.h @@ -0,0 +1,1252 @@ +/****************************************************************************** +* Filename: prcm.h +* Revised: 2018-10-23 10:19:14 +0200 (Tue, 23 Oct 2018) +* Revision: 52979 +* +* Description: Defines and prototypes for the PRCM +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup prcm_api +//! @{ +// +//***************************************************************************** + +#ifndef __PRCM_H__ +#define __PRCM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_aon_rtc.h" +#include "interrupt.h" +#include "debug.h" +#include "cpu.h" + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet + #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet + #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet + #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride + #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource + #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource + #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn + #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff + #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable + #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable + #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable + #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable + #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable + #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable + #define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus + #define PRCMDeepSleep NOROM_PRCMDeepSleep +#endif + +//***************************************************************************** +// +// Defines for the different System CPU power modes. +// +//***************************************************************************** +#define PRCM_RUN_MODE 0x00000001 +#define PRCM_SLEEP_MODE 0x00000002 +#define PRCM_DEEP_SLEEP_MODE 0x00000004 + +//***************************************************************************** +// +// Defines used for setting the clock division factors +// +//***************************************************************************** +#define PRCM_CLOCK_DIV_1 PRCM_GPTCLKDIV_RATIO_DIV1 +#define PRCM_CLOCK_DIV_2 PRCM_GPTCLKDIV_RATIO_DIV2 +#define PRCM_CLOCK_DIV_4 PRCM_GPTCLKDIV_RATIO_DIV4 +#define PRCM_CLOCK_DIV_8 PRCM_GPTCLKDIV_RATIO_DIV8 +#define PRCM_CLOCK_DIV_16 PRCM_GPTCLKDIV_RATIO_DIV16 +#define PRCM_CLOCK_DIV_32 PRCM_GPTCLKDIV_RATIO_DIV32 +#define PRCM_CLOCK_DIV_64 PRCM_GPTCLKDIV_RATIO_DIV64 +#define PRCM_CLOCK_DIV_128 PRCM_GPTCLKDIV_RATIO_DIV128 +#define PRCM_CLOCK_DIV_256 PRCM_GPTCLKDIV_RATIO_DIV256 + +//***************************************************************************** +// +// Defines used for enabling and disabling domains and memories in the MCU +// domain +// +//***************************************************************************** +#define PRCM_DOMAIN_RFCORE 0x00000001 // RF Core domain ID for + // clock/power control. +#define PRCM_DOMAIN_SERIAL 0x00000002 // Serial domain ID for + // clock/power control. +#define PRCM_DOMAIN_PERIPH 0x00000004 // Peripheral domain ID for + // clock/power control. +#define PRCM_DOMAIN_SYSBUS 0x00000008 // Bus domain ID for clock/power + // control. +#define PRCM_DOMAIN_VIMS 0x00000010 // VIMS domain ID for clock/power + // control. +#define PRCM_DOMAIN_CPU 0x00000020 // CPU domain ID for clock/power + // control. +#define PRCM_DOMAIN_TIMER 0x00000040 // GPT domain ID for clock + // control. +#define PRCM_DOMAIN_CLKCTRL 0x00000080 // Clock Control domain ID for + // clock/power control. +#define PRCM_DOMAIN_MCU 0x00000100 // Reset control for entire MCU + // domain. +#define PRCM_DOMAIN_POWER_OFF 0x00000002 // The domain is powered off +#define PRCM_DOMAIN_POWER_ON 0x00000001 // The domain is powered on +#define PRCM_DOMAIN_POWER_DOWN_READY \ + 0x00000000 // The domain is ready to be + // powered down. + +//***************************************************************************** +// +// Defines for setting up the audio interface in the I2S module. +// +//***************************************************************************** +#define PRCM_WCLK_NEG_EDGE 0x00000008 +#define PRCM_WCLK_POS_EDGE 0x00000000 +#define PRCM_WCLK_SINGLE_PHASE 0x00000000 +#define PRCM_WCLK_DUAL_PHASE 0x00000002 +#define PRCM_WCLK_USER_DEF 0x00000004 +#define PRCM_I2S_WCLK_NEG_EDGE 0 +#define PRCM_I2S_WCLK_POS_EDGE 1 +#define PRCM_I2S_WCLK_SINGLE_PHASE 0 +#define PRCM_I2S_WCLK_DUAL_PHASE 1 +#define PRCM_I2S_WCLK_USER_DEF 2 + +#define I2S_SAMPLE_RATE_16K 0x00000001 +#define I2S_SAMPLE_RATE_24K 0x00000002 +#define I2S_SAMPLE_RATE_32K 0x00000004 +#define I2S_SAMPLE_RATE_48K 0x00000008 + +//***************************************************************************** +// +// Defines used for enabling and disabling peripheral modules in the MCU domain +// bits[11:8] Defines the index into the register offset constant tables: +// g_pui32RCGCRegs, g_pui32SCGCRegs and g_pui32DCGCRegs +// bits[4:0] Defines the bit position within the register pointet on in [11:8] +// +//***************************************************************************** +#define PRCM_PERIPH_TIMER0 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S )) // Peripheral ID for GPT module 0 +#define PRCM_PERIPH_TIMER1 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for GPT module 1 +#define PRCM_PERIPH_TIMER2 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 2 )) // Peripheral ID for GPT module 2 +#define PRCM_PERIPH_TIMER3 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 3 )) // Peripheral ID for GPT module 3 +#define PRCM_PERIPH_SSI0 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S )) // Peripheral ID for SSI module 0 +#define PRCM_PERIPH_SSI1 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S + 1 )) // Peripheral ID for SSI module 1 +#define PRCM_PERIPH_UART0 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S )) // Peripheral ID for UART module 0 +#define PRCM_PERIPH_I2C0 ( 0x00000300 | ( PRCM_I2CCLKGR_CLK_EN_S )) // Peripheral ID for I2C module 0 +#define PRCM_PERIPH_CRYPTO ( 0x00000400 | ( PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S )) // Peripheral ID for CRYPTO module +#define PRCM_PERIPH_TRNG ( 0x00000400 | ( PRCM_SECDMACLKGR_TRNG_CLK_EN_S )) // Peripheral ID for TRNG module +#define PRCM_PERIPH_UDMA ( 0x00000400 | ( PRCM_SECDMACLKGR_DMA_CLK_EN_S )) // Peripheral ID for UDMA module +#define PRCM_PERIPH_GPIO ( 0x00000500 | ( PRCM_GPIOCLKGR_CLK_EN_S )) // Peripheral ID for GPIO module +#define PRCM_PERIPH_I2S ( 0x00000600 | ( PRCM_I2SCLKGR_CLK_EN_S )) // Peripheral ID for I2S module + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \brief Checks a peripheral identifier. +//! +//! This function determines if a peripheral identifier is valid. +//! +//! \param ui32Peripheral is the peripheral identifier. +//! +//! \return Returns status of peripheral identifier: +//! - \b true : Peripheral identifier is valid. +//! - \b false : Peripheral identifier is invalid. +// +//***************************************************************************** +static bool +PRCMPeripheralValid(uint32_t ui32Peripheral) +{ + return((ui32Peripheral == PRCM_PERIPH_TIMER0) || + (ui32Peripheral == PRCM_PERIPH_TIMER1) || + (ui32Peripheral == PRCM_PERIPH_TIMER2) || + (ui32Peripheral == PRCM_PERIPH_TIMER3) || + (ui32Peripheral == PRCM_PERIPH_SSI0) || + (ui32Peripheral == PRCM_PERIPH_SSI1) || + (ui32Peripheral == PRCM_PERIPH_UART0) || + (ui32Peripheral == PRCM_PERIPH_I2C0) || + (ui32Peripheral == PRCM_PERIPH_CRYPTO) || + (ui32Peripheral == PRCM_PERIPH_TRNG) || + (ui32Peripheral == PRCM_PERIPH_UDMA) || + (ui32Peripheral == PRCM_PERIPH_GPIO) || + (ui32Peripheral == PRCM_PERIPH_I2S)); +} +#endif + +//***************************************************************************** +// +//! \brief Configure the infrastructure clock. +//! +//! Each System CPU power mode has its own infrastructure clock division factor. This +//! function can be used for setting up the division factor for the +//! infrastructure clock in the available power modes for the System CPU. The +//! infrastructure clock is used for all internal logic in the PRCM, and is +//! always running as long as power is on in the MCU voltage domain. +//! This can be enabled and disabled from the AON Wake Up Controller. +//! +//! \note If source clock is 48 MHz, minimum clock divider is \ref PRCM_CLOCK_DIV_2. +//! +//! \param ui32ClkDiv determines the division ratio for the infrastructure +//! clock when the device is in the specified mode. +//! Allowed division factors for all three System CPU power modes are: +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_32 +//! \param ui32PowerMode determines the System CPU operation mode for which to +//! modify the clock division factor. +//! The three allowed power modes are: +//! - \ref PRCM_RUN_MODE +//! - \ref PRCM_SLEEP_MODE +//! - \ref PRCM_DEEP_SLEEP_MODE +//! +//! \return None +// +//***************************************************************************** +extern void PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, + uint32_t ui32PowerMode); + +//***************************************************************************** +// +//! \brief Use this function to get the infrastructure clock configuration. +//! +//! \param ui32PowerMode determines which System CPU power mode to return the +//! infrastructure clock division ratio for. +//! The three allowed power modes are: +//! - \ref PRCM_RUN_MODE +//! - \ref PRCM_SLEEP_MODE +//! - \ref PRCM_DEEP_SLEEP_MODE +//! +//! \return Returns the infrastructure clock division factor for the specified +//! power mode. +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_32 +//! +//! \sa \ref PRCMInfClockConfigureSet(). +// +//***************************************************************************** +extern uint32_t PRCMInfClockConfigureGet(uint32_t ui32PowerMode); + +//***************************************************************************** +// +//! \brief Request a power off of the MCU voltage domain. +//! +//! Use this function to request a power off of the entire MCU voltage domain. +//! This request will have no affect until deepsleep mode is requested. +//! +//! \return None +//! +//! \sa \ref PRCMDeepSleep(), \ref PRCMMcuPowerOffCancel() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMMcuPowerOff(void) +{ + // Assert the power off request signal. + HWREGBITW(PRCM_BASE + PRCM_O_VDCTL, PRCM_VDCTL_MCU_VD_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Cancel a request for a power off of the MCU voltage domain. +//! +//! Use this function to cancel a request for power off of the entire MCU +//! voltage domain. This could be relevant if a transition to power down is +//! regretted and an application must backtrack. +//! +//! \return None +//! +//! \sa \ref PRCMDeepSleep(), \ref PRCMMcuPowerOff() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMMcuPowerOffCancel(void) +{ + // Assert the power off request signal. + HWREGBITW(PRCM_BASE + PRCM_O_VDCTL, PRCM_VDCTL_MCU_VD_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Assert or de-assert a request for the uLDO. +//! +//! Use this function to request to switch to the micro Low Voltage Dropout +//! regulator (uLDO). The uLDO has a much lower capacity for supplying power +//! to the system. It is therefore imperative and solely the programmers +//! responsibility to ensure that a sufficient amount of peripheral modules +//! have been turned of before requesting a switch to the uLDO. +//! +//! \note Asserting this bit has no effect until: +//! 1. FLASH has accepted to be powered down +//! 2. Deepsleep must be asserted +//! +//! \param ui32Enable +//! - 0 : Disable uLDO request +//! - 1 : Enable uLDO request +//! +//! \return None +//! +//! \sa \ref PRCMDeepSleep() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMMcuUldoConfigure(uint32_t ui32Enable) +{ + // Enable or disable the uLDO request signal. + HWREGBITW(PRCM_BASE + PRCM_O_VDCTL, PRCM_VDCTL_ULDO_BITN) = ui32Enable; +} + +//***************************************************************************** +// +//! \brief Setup the clock division factor for the GP-Timer domain. +//! +//! Use this function to set up the clock division factor on the GP-Timer. +//! +//! The division rate will be constant and ungated for Run / Sleep / DeepSleep mode when +//! it is slower than PRCM_GPTCLKDIV_RATIO setting. +//! When set faster than PRCM_GPTCLKDIV_RATIO setting PRCM_GPTCLKDIV_RATIO will be used. +//! Note that the register will contain the written content even though the setting is +//! faster than PRCM_GPTCLKDIV_RATIO setting. +//! +//! \note For change to take effect, \ref PRCMLoadSet() needs to be called +//! +//! \param clkDiv is the division factor to set. +//! The argument must be only one of the following values: +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_4 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_16 +//! - \ref PRCM_CLOCK_DIV_32 +//! - \ref PRCM_CLOCK_DIV_64 +//! - \ref PRCM_CLOCK_DIV_128 +//! - \ref PRCM_CLOCK_DIV_256 +//! +//! \return None +//! +//! \sa \ref PRCMGPTimerClockDivisionGet() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMGPTimerClockDivisionSet( uint32_t clkDiv ) +{ + ASSERT( clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256 ); + + HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ) = clkDiv; +} + +//***************************************************************************** +// +//! \brief Get the clock division factor for the GP-Timer domain. +//! +//! Use this function to get the clock division factor set for the GP-Timer. +//! +//! \return Returns one of the following values: +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_4 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_16 +//! - \ref PRCM_CLOCK_DIV_32 +//! - \ref PRCM_CLOCK_DIV_64 +//! - \ref PRCM_CLOCK_DIV_128 +//! - \ref PRCM_CLOCK_DIV_256 +//! +//! \sa \ref PRCMGPTimerClockDivisionSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +PRCMGPTimerClockDivisionGet( void ) +{ + return ( HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV )); +} + + +//***************************************************************************** +// +//! \brief Enable the audio clock generation. +//! +//! Use this function to enable the audio clock generation. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMAudioClockEnable(void) +{ + // Enable the audio clock generation. + HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disable the audio clock generation. +//! +//! Use this function to disable the audio clock generation. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMAudioClockDisable(void) +{ + // Disable the audio clock generation + HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Configure the audio clock generation. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Use this function to set the sample rate when using internal audio clock +//! generation for the I2S module. +//! +//! \note While other clocks are possible, the stability of the four sample +//! rates defined here are only guaranteed if the clock input to the I2S module +//! is 48MHz. +//! +//! \param ui32ClkConfig is the audio clock configuration. +//! The parameter is a bitwise OR'ed value consisting of: +//! - Phase +//! - \ref PRCM_WCLK_SINGLE_PHASE +//! - \ref PRCM_WCLK_DUAL_PHASE +//! - Clock polarity +//! - \ref PRCM_WCLK_NEG_EDGE +//! - \ref PRCM_WCLK_POS_EDGE +//! \param ui32SampleRate is the desired audio clock sample rate. +//! The supported sample rate configurations are: +//! - \ref I2S_SAMPLE_RATE_16K +//! - \ref I2S_SAMPLE_RATE_24K +//! - \ref I2S_SAMPLE_RATE_32K +//! - \ref I2S_SAMPLE_RATE_48K +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockConfigSetOverride() +// +//***************************************************************************** +#ifndef DEPRECATED +extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, + uint32_t ui32SampleRate); +#endif + +//***************************************************************************** +// +//! \brief Configure the audio clock generation with manual setting of clock divider. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Use this function to set the audio clock divider values manually. +//! +//! \note See hardware documentation before setting audio clock dividers manually. +//! +//! \param ui32ClkConfig is the audio clock configuration. +//! The parameter is a bitwise OR'ed value consisting of: +//! - Phase +//! - \ref PRCM_WCLK_SINGLE_PHASE +//! - \ref PRCM_WCLK_DUAL_PHASE +//! - Clock polarity +//! - \ref PRCM_WCLK_NEG_EDGE +//! - \ref PRCM_WCLK_POS_EDGE +//! \param ui32MstDiv is the desired master clock divider. +//! \param ui32WordDiv is the desired word clock divider. +//! \param ui32BitDiv is the desired bit clock divider. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockConfigSet() +// +//***************************************************************************** +#ifndef DEPRECATED +extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, + uint32_t ui32BitDiv, uint32_t ui32WordDiv); +#endif + +//***************************************************************************** +// +//! \brief Configure the audio clocks for I2S module. +//! +//! \note See hardware documentation before setting audio clock dividers. +//! This is user's responsability to provide valid clock dividers. +//! +//! \param ui8SamplingEdge Define the clock polarity: +//! - \ref PRCM_I2S_WCLK_NEG_EDGE +//! - \ref PRCM_I2S_WCLK_POS_EDGE +//! \param ui8WCLKPhase Define I2S phase used +//! - PRCM_I2S_WCLK_SINGLE_PHASE +//! - PRCM_I2S_WCLK_DUAL_PHASE +//! - PRCM_I2S_WCLK_USER_DEF +//! \param ui32MstDiv is the desired master clock divider. +//! \param ui32BitDiv is the desired bit clock divider. +//! \param ui32WordDiv is the desired word clock divider. +//! +//! \return None +//! +//***************************************************************************** +extern void PRCMAudioClockConfigOverride + (uint8_t ui8SamplingEdge, + uint8_t ui8WCLKPhase, + uint32_t ui32MstDiv, + uint32_t ui32BitDiv, + uint32_t ui32WordDiv); + +//***************************************************************************** +// +//! \brief Configure the audio clocks to be internally generated. +//! +//! Use this function to set the audio clocks as internal. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockExternalSource() +// +//***************************************************************************** +extern void PRCMAudioClockInternalSource(void); + +//***************************************************************************** +// +//! \brief Configure the audio clocks to be externally generated. +//! +//! Use this function to set the audio clocks as external. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockInternalSource() +// +//***************************************************************************** +extern void PRCMAudioClockExternalSource(void); + +//***************************************************************************** +// +//! \brief Use this function to synchronize the load settings. +//! +//! Most of the clock settings in the PRCM module should be updated +//! synchronously. This is ensured by the implementation of a load registers +//! that, when written to, will let the previous written update values for all +//! the relevant registers propagate through to hardware. +//! +//! The functions that require a synchronization of the clock settings are: +//! - \ref PRCMAudioClockConfigSet() +//! - \ref PRCMAudioClockConfigSetOverride() +//! - \ref PRCMAudioClockDisable() +//! - \ref PRCMDomainEnable() +//! - \ref PRCMDomainDisable() +//! - \ref PRCMPeripheralRunEnable() +//! - \ref PRCMPeripheralRunDisable() +//! - \ref PRCMPeripheralSleepEnable() +//! - \ref PRCMPeripheralSleepDisable() +//! - \ref PRCMPeripheralDeepSleepEnable() +//! - \ref PRCMPeripheralDeepSleepDisable() +//! +//! \return None +//! +//! \sa \ref PRCMLoadGet() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMLoadSet(void) +{ + // Enable the update of all load related registers. + HWREG(PRCM_NONBUF_BASE + PRCM_O_CLKLOADCTL) = PRCM_CLKLOADCTL_LOAD; +} + +//***************************************************************************** +// +//! \brief Check if any of the load sensitive register has been updated. +//! +//! \return Returns status of the load sensitive register: +//! - \c true : No registers have changed since the last load. +//! - \c false : Any register has changed. +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +__STATIC_INLINE bool +PRCMLoadGet(void) +{ + // Return the load status. + return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? + true : false); +} + +//***************************************************************************** +// +//! \brief Enable clock domains in the MCU voltage domain. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \note Clocks will only be running if the domain is powered. +//! +//! \param ui32Domains is a bit mask containing the clock domains to enable. +//! The independent clock domains inside the MCU voltage domain which can be +//! configured are: +//! - \ref PRCM_DOMAIN_RFCORE +//! - \ref PRCM_DOMAIN_VIMS +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMDomainEnable(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Enable the clock domain(s). + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = PRCM_RFCCLKG_CLK_EN; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = PRCM_VIMSCLKG_CLK_EN_M; + } +} + +//***************************************************************************** +// +//! \brief Disable clock domains in the MCU voltage domain. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \note Clocks will only be running if the domain is powered. +//! +//! \param ui32Domains is a bit mask containing the clock domains to disable. +//! The independent clock domains inside the MCU voltage domain are: +//! - \ref PRCM_DOMAIN_RFCORE +//! - \ref PRCM_DOMAIN_VIMS +//! +//! \return None +//! +//! \sa PRCMDomainEnable() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMDomainDisable(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Disable the power domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = 0x0; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = 0x0; + } +} + +//***************************************************************************** +// +//! \brief Turn power on in power domains in the MCU domain. +//! +//! Use this function to turn on power domains inside the MCU voltage domain. +//! +//! Power on and power off request has different implications for the +//! different power domains. +//! - RF Core power domain: +//! - Power On : Domain is on or in the process of turning on. +//! - Power Off : Domain is powered down when System CPU is in deep sleep. The third +//! option for the RF Core is to power down when the it is idle. +//! This can be set using \b PRCMRfPowerDownWhenIdle() +//! - SERIAL power domain: +//! - Power on : Domain is powered on. +//! - Power off : Domain is powered off. +//! - PERIPHERIAL power domain: +//! - Power on : Domain is powered on. +//! - Power off : Domain is powered off. +//! - VIMS power domain: +//! - Power On : Domain is powered if Bus domain is powered. +//! - Power Off : Domain is only powered when CPU domain is on. +//! - BUS power domain: +//! - Power On : Domain is on. +//! - Power Off : Domain is on if requested by RF Core or if CPU domain is on. +//! - CPU power domain: +//! - Power On : Domain is on. +//! - Power Off : Domain is powering down if System CPU is idle. This will also +//! initiate a power down of the SRAM and BUS power domains, unless +//! RF Core is requesting them to be on. +//! +//! \note After a call to this function the status of the power domain should +//! be checked using either \ref PRCMPowerDomainStatus(). +//! Any write operation to a power domain which is still not operational can +//! result in unexpected behavior. +//! +//! \param ui32Domains determines which power domains to turn on. +//! The domains that can be turned on/off are: +//! - \b PRCM_DOMAIN_RFCORE : RF Core +//! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 +//! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 +//! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM +//! - \b PRCM_DOMAIN_SYSBUS +//! - \b PRCM_DOMAIN_CPU +//! +//! \return None +// +//***************************************************************************** +extern void PRCMPowerDomainOn(uint32_t ui32Domains); + +//***************************************************************************** +// +//! \brief Turn off a specific power domain. +//! +//! Use this function to power down domains inside the MCU voltage domain. +//! +//! \note For specifics regarding on/off configuration please see +//! \ref PRCMPowerDomainOn(). +//! +//! \param ui32Domains determines which domain to request a power down for. +//! The domains that can be turned on/off are: +//! - \b PRCM_DOMAIN_RFCORE : RF Core +//! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 +//! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 +//! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM +//! - \b PRCM_DOMAIN_SYSBUS +//! - \b PRCM_DOMAIN_CPU +//! +//! \return None +// +//***************************************************************************** +extern void PRCMPowerDomainOff(uint32_t ui32Domains); + +//***************************************************************************** +// +//! \brief Configure RF core to power down when idle. +//! +//! Use this function to configure the RF core to power down when Idle. This +//! is handled automatically in hardware if the RF Core reports that it is +//! idle. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMRfPowerDownWhenIdle(void) +{ + // Configure the RF power domain. + HWREGBITW(PRCM_BASE + PRCM_O_PDCTL0RFC, PRCM_PDCTL0RFC_ON_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Enables a peripheral in Run mode. +//! +//! Peripherals are enabled with this function. At power-up, some peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! \note The actual enabling of the peripheral may be delayed until some +//! time after this function returns. Care should be taken to ensure that the +//! peripheral is not accessed until it is enabled. +//! When enabling Timers always make sure that the division factor for the +//! \b PERBUSCPUCLK is set. This will guarantee that the timers run at a +//! continuous rate even if the \b SYSBUSCLK is gated. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to enable. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralRunEnable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Disables a peripheral in Run mode +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \note The actual disabling of the peripheral may be delayed until some +//! time after this function returns. Care should be taken by the user to +//! ensure that the peripheral is not accessed in this interval as this might +//! cause the system to hang. +//! +//! \param ui32Peripheral is the peripheral to disable. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralRunDisable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Enables a peripheral in sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into sleep mode. Since the clocking configuration of the device does +//! not change, any peripheral can safely continue operating while the +//! processor is in sleep mode, and can therefore wake the processor from sleep +//! mode. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to enable in sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralSleepEnable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Disables a peripheral in sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into sleep mode. Disabling peripherals while in sleep mode helps to lower +//! the current draw of the device. If enabled (via \ref PRCMPeripheralRunEnable()), +//! the peripheral will automatically resume operation when the processor +//! leaves sleep mode, maintaining its entire state from before sleep mode was +//! entered. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to disable in sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralSleepDisable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Enables a peripheral in deep-sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into deep-sleep mode. Since the clocking configuration of the device +//! may change, not all peripherals can safely continue operating while the +//! processor is in sleep mode. This in turn depends on the chosen power mode. +//! It is the responsibility of the caller to make sensible choices. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to enable in deep-sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Disables a peripheral in deep-sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps +//! to lower the current draw of the device, and can keep peripherals that +//! require a particular clock frequency from operating when the clock changes +//! as a result of entering deep-sleep mode. If enabled (via +//! \ref PRCMPeripheralRunEnable()), the peripheral will automatically resume +//! operation when the processor leaves deep-sleep mode, maintaining its entire +//! state from before deep-sleep mode was entered. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to disable in deep-sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Get the status for a specific power domain. +//! +//! Use this function to retrieve the current power status of one or more +//! power domains. +//! +//! \param ui32Domains determines which domain to get the power status for. +//! The parameter must be an OR'ed combination of one or several of: +//! - \ref PRCM_DOMAIN_RFCORE : RF Core. +//! - \ref PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 +//! - \ref PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 +//! +//! \return Returns status of the requested domains: +//! - \ref PRCM_DOMAIN_POWER_ON : The specified domains are \b all powered up. +//! This status is unconditional and the powered up status is guaranteed. +//! - \ref PRCM_DOMAIN_POWER_OFF : Any of the domains are powered down. +// +//***************************************************************************** +extern uint32_t PRCMPowerDomainStatus(uint32_t ui32Domains); + +//***************************************************************************** +// +//! \brief Return the access status of the RF Core. +//! +//! Use this function to check if the RF Core is on and ready to be accessed. +//! Accessing register or memories that are not powered and clocked will +//! cause a bus fault. +//! +//! \return Returns access status of the RF Core. +//! - \c true : RF Core can be accessed. +//! - \c false : RF Core domain is not ready for access. +// +//***************************************************************************** +__STATIC_INLINE bool +PRCMRfReady(void) +{ + // Return the ready status of the RF Core. + return ((HWREG(PRCM_BASE + PRCM_O_PDSTAT1RFC) & + PRCM_PDSTAT1RFC_ON) ? true : false); +} + + +//***************************************************************************** +// +//! \brief Put the processor into sleep mode. +//! +//! This function places the processor into sleep mode; it does not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via PRCMPeripheralSleepEnable() continue to operate and can wake up the +//! processor. +//! +//! \return None +//! +//! \sa \ref PRCMPeripheralSleepEnable() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMSleep(void) +{ + // Wait for an interrupt. + CPUwfi(); +} + +//***************************************************************************** +// +//! \brief Put the processor into deep-sleep mode. +//! +//! This function places the processor into deep-sleep mode; it does not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via \ref PRCMPeripheralDeepSleepEnable() continue to operate and can wake up +//! the processor. +//! +//! \return None +//! +//! \sa \ref PRCMPeripheralDeepSleepEnable() +// +//***************************************************************************** +extern void PRCMDeepSleep(void); + +//***************************************************************************** +// +//! \brief Enable CACHE RAM retention +//! +//! Enables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMCacheRetentionEnable( void ) +{ + HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) |= PRCM_RAMRETEN_VIMS_M; +} + +//***************************************************************************** +// +//! \brief Disable CACHE RAM retention +//! +//! Disables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMCacheRetentionDisable( void ) +{ + HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) &= ~PRCM_RAMRETEN_VIMS_M; +} + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_PRCMInfClockConfigureSet + #undef PRCMInfClockConfigureSet + #define PRCMInfClockConfigureSet ROM_PRCMInfClockConfigureSet + #endif + #ifdef ROM_PRCMInfClockConfigureGet + #undef PRCMInfClockConfigureGet + #define PRCMInfClockConfigureGet ROM_PRCMInfClockConfigureGet + #endif + #ifdef ROM_PRCMAudioClockConfigSet + #undef PRCMAudioClockConfigSet + #define PRCMAudioClockConfigSet ROM_PRCMAudioClockConfigSet + #endif + #ifdef ROM_PRCMAudioClockConfigSetOverride + #undef PRCMAudioClockConfigSetOverride + #define PRCMAudioClockConfigSetOverride ROM_PRCMAudioClockConfigSetOverride + #endif + #ifdef ROM_PRCMAudioClockInternalSource + #undef PRCMAudioClockInternalSource + #define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource + #endif + #ifdef ROM_PRCMAudioClockExternalSource + #undef PRCMAudioClockExternalSource + #define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource + #endif + #ifdef ROM_PRCMPowerDomainOn + #undef PRCMPowerDomainOn + #define PRCMPowerDomainOn ROM_PRCMPowerDomainOn + #endif + #ifdef ROM_PRCMPowerDomainOff + #undef PRCMPowerDomainOff + #define PRCMPowerDomainOff ROM_PRCMPowerDomainOff + #endif + #ifdef ROM_PRCMPeripheralRunEnable + #undef PRCMPeripheralRunEnable + #define PRCMPeripheralRunEnable ROM_PRCMPeripheralRunEnable + #endif + #ifdef ROM_PRCMPeripheralRunDisable + #undef PRCMPeripheralRunDisable + #define PRCMPeripheralRunDisable ROM_PRCMPeripheralRunDisable + #endif + #ifdef ROM_PRCMPeripheralSleepEnable + #undef PRCMPeripheralSleepEnable + #define PRCMPeripheralSleepEnable ROM_PRCMPeripheralSleepEnable + #endif + #ifdef ROM_PRCMPeripheralSleepDisable + #undef PRCMPeripheralSleepDisable + #define PRCMPeripheralSleepDisable ROM_PRCMPeripheralSleepDisable + #endif + #ifdef ROM_PRCMPeripheralDeepSleepEnable + #undef PRCMPeripheralDeepSleepEnable + #define PRCMPeripheralDeepSleepEnable ROM_PRCMPeripheralDeepSleepEnable + #endif + #ifdef ROM_PRCMPeripheralDeepSleepDisable + #undef PRCMPeripheralDeepSleepDisable + #define PRCMPeripheralDeepSleepDisable ROM_PRCMPeripheralDeepSleepDisable + #endif + #ifdef ROM_PRCMPowerDomainStatus + #undef PRCMPowerDomainStatus + #define PRCMPowerDomainStatus ROM_PRCMPowerDomainStatus + #endif + #ifdef ROM_PRCMDeepSleep + #undef PRCMDeepSleep + #define PRCMDeepSleep ROM_PRCMDeepSleep + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PRCM_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/pwr_ctrl.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/pwr_ctrl.c new file mode 100644 index 0000000..18289c5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/pwr_ctrl.c @@ -0,0 +1,80 @@ +/****************************************************************************** +* Filename: pwr_ctrl.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Power Control driver. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "pwr_ctrl.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef PowerCtrlSourceSet + #define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet +#endif + + +//***************************************************************************** +// +// Set (Request) the main power source +// +//***************************************************************************** +void +PowerCtrlSourceSet(uint32_t ui32PowerConfig) +{ + // Check the arguments. + ASSERT((ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) || + (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) || + (ui32PowerConfig == PWRCTRL_PWRSRC_ULDO)); + + // Configure the power. + if(ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) { + HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL) |= + (AON_SYSCTL_PWRCTL_DCDC_EN | AON_SYSCTL_PWRCTL_DCDC_ACTIVE); + } + else if (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) + { + HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL) &= + ~(AON_SYSCTL_PWRCTL_DCDC_EN | AON_SYSCTL_PWRCTL_DCDC_ACTIVE); + } + else + { + PRCMMcuUldoConfigure(true); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/pwr_ctrl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/pwr_ctrl.h new file mode 100644 index 0000000..4cbff1b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/pwr_ctrl.h @@ -0,0 +1,296 @@ +/****************************************************************************** +* Filename: pwr_ctrl.h +* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) +* Revision: 50165 +* +* Description: Defines and prototypes for the System Power Control. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup pwrctrl_api +//! @{ +// +//***************************************************************************** + +#ifndef __PWR_CTRL_H__ +#define __PWR_CTRL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_aon_sysctl.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_adi_2_refsys.h" +#include "debug.h" +#include "interrupt.h" +#include "osc.h" +#include "cpu.h" +#include "prcm.h" +#include "aon_ioc.h" +#include "adi.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet +#endif + +//***************************************************************************** +// +// Defines for the system power states +// +//***************************************************************************** +#define PWRCTRL_ACTIVE 0x00000001 +#define PWRCTRL_STANDBY 0x00000002 +#define PWRCTRL_POWER_DOWN 0x00000004 +#define PWRCTRL_SHUTDOWN 0x00000008 + +//***************************************************************************** +// +// Defines for the power configuration in the AON System Control 1.2 V +// +//***************************************************************************** +#define PWRCTRL_IOSEG3_ENABLE 0x00000800 +#define PWRCTRL_IOSEG2_ENABLE 0x00000400 +#define PWRCTRL_IOSEG3_DISABLE 0x00000200 +#define PWRCTRL_IOSEG2_DISABLE 0x00000100 +#define PWRCTRL_PWRSRC_DCDC 0x00000001 +#define PWRCTRL_PWRSRC_GLDO 0x00000000 +#define PWRCTRL_PWRSRC_ULDO 0x00000002 + +//***************************************************************************** +// +// The following are defines for the various reset source for the device. +// +//***************************************************************************** +#define PWRCTRL_RST_POWER_ON 0x00000000 // Reset by power on +#define PWRCTRL_RST_PIN 0x00000001 // Pin reset +#define PWRCTRL_RST_VDDS_BOD 0x00000002 // VDDS Brown Out Detect +#define PWRCTRL_RST_VDD_BOD 0x00000003 // VDD Brown Out Detect +#define PWRCTRL_RST_VDDR_BOD 0x00000004 // VDDR Brown Out Detect +#define PWRCTRL_RST_CLK_LOSS 0x00000005 // Clock loss Reset +#define PWRCTRL_RST_SW_PIN 0x00000006 // SYSRESET or pin reset +#define PWRCTRL_RST_WARM 0x00000007 // Reset via PRCM warm reset request + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Set (Request) the main power source. +//! +//! \note The system will never allow a switch to the \ref PWRCTRL_PWRSRC_ULDO +//! when in active mode. This is only allowed when the system is in lower power +//! mode where no code is executing and no peripherals are active. +//! Assuming that there is an external capacitor available for the +//! \ref PWRCTRL_PWRSRC_DCDC the system can dynamically switch back and forth +//! between the two when in active mode. +//! +//! \note The system will automatically switch to the GLDO / DCDC when waking +//! up from a low power mode. +//! +//! \param ui32PowerConfig is a bitmask indicating the target power source. +//! - \ref PWRCTRL_PWRSRC_DCDC +//! - \ref PWRCTRL_PWRSRC_GLDO +//! - \ref PWRCTRL_PWRSRC_ULDO +//! +//! \return None +// +//***************************************************************************** +extern void PowerCtrlSourceSet(uint32_t ui32PowerConfig); + +//***************************************************************************** +// +//! \brief Get the main power source. +//! +//! Use this function to retrieve the current active power source. +//! +//! When the System CPU is active it can never be powered by uLDO as this +//! is too weak a power source. +//! +//! \note Using the DCDC power supply requires an external inductor. +//! +//! \return Returns the main power source. +//! - \ref PWRCTRL_PWRSRC_DCDC +//! - \ref PWRCTRL_PWRSRC_GLDO +// +//***************************************************************************** +__STATIC_INLINE uint32_t +PowerCtrlSourceGet(void) +{ + uint32_t ui32PowerConfig; + + // Return the current power source + ui32PowerConfig = HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL); + if(ui32PowerConfig & AON_SYSCTL_PWRCTL_DCDC_ACTIVE) + { + return (PWRCTRL_PWRSRC_DCDC); + } + else + { + return (PWRCTRL_PWRSRC_GLDO); + } +} + +//***************************************************************************** +// +//! \brief OBSOLETE: Get the last known reset source of the system. +//! +//! \deprecated This function will be removed in a future release. +//! Use \ref SysCtrlResetSourceGet() instead. +//! +//! This function returns reset source but does not cover if waking up from shutdown. +//! This function can be seen as a subset of function \ref SysCtrlResetSourceGet() +//! and will be removed in a future release. +//! +//! \return Returns one of the known reset values. +//! The possible reset sources are: +//! - \ref PWRCTRL_RST_POWER_ON +//! - \ref PWRCTRL_RST_PIN +//! - \ref PWRCTRL_RST_VDDS_BOD +//! - \ref PWRCTRL_RST_VDD_BOD +//! - \ref PWRCTRL_RST_VDDR_BOD +//! - \ref PWRCTRL_RST_CLK_LOSS +//! - \ref PWRCTRL_RST_SW_PIN +//! - \ref PWRCTRL_RST_WARM +//! +//! \sa \ref SysCtrlResetSourceGet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +PowerCtrlResetSourceGet(void) +{ + // Get the reset source. + return (( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) & + AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> + AON_SYSCTL_RESETCTL_RESET_SRC_S ) ; +} + +//***************************************************************************** +// +//! \brief Enables pad sleep in order to latch device outputs before shutdown. +//! +//! \return None +//! +//! \sa \ref PowerCtrlPadSleepDisable() +// +//***************************************************************************** +__STATIC_INLINE void +PowerCtrlPadSleepEnable(void) +{ + HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_SLEEPCTL) = 0; + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! \brief Disables pad sleep in order to unlatch device outputs after wakeup from shutdown. +//! +//! This function must be called by the application after the device wakes up +//! from shutdown. +//! +//! \return None +//! +//! \sa \ref PowerCtrlPadSleepEnable() +// +//***************************************************************************** +__STATIC_INLINE void +PowerCtrlPadSleepDisable(void) +{ + HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_SLEEPCTL) = 1; + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_PowerCtrlSourceSet + #undef PowerCtrlSourceSet + #define PowerCtrlSourceSet ROM_PowerCtrlSourceSet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PWR_CTRL_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_cmd.h new file mode 100644 index 0000000..2dabdcb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_cmd.h @@ -0,0 +1,1129 @@ +/****************************************************************************** +* Filename: rf_ble_cmd.h +* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) +* Revision: 18052 +* +* Description: CC13x0 API for Bluetooth Low Energy commands +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __BLE_CMD_H +#define __BLE_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup ble_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_bleRadioOp_s rfc_bleRadioOp_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s rfc_CMD_BLE_SLAVE_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s rfc_CMD_BLE_MASTER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_s rfc_CMD_BLE_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s rfc_CMD_BLE_ADV_DIR_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s rfc_CMD_BLE_ADV_NC_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s rfc_CMD_BLE_ADV_SCAN_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s rfc_CMD_BLE_SCANNER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s rfc_CMD_BLE_INITIATOR_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s rfc_CMD_BLE_GENERIC_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s rfc_CMD_BLE_TX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s rfc_CMD_BLE_ADV_PAYLOAD_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s rfc_CMD_BLE5_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_bleMasterSlavePar_s rfc_bleMasterSlavePar_t; +typedef struct __RFC_STRUCT rfc_bleMasterPar_s rfc_bleMasterPar_t; +typedef struct __RFC_STRUCT rfc_bleSlavePar_s rfc_bleSlavePar_t; +typedef struct __RFC_STRUCT rfc_bleAdvPar_s rfc_bleAdvPar_t; +typedef struct __RFC_STRUCT rfc_bleScannerPar_s rfc_bleScannerPar_t; +typedef struct __RFC_STRUCT rfc_bleInitiatorPar_s rfc_bleInitiatorPar_t; +typedef struct __RFC_STRUCT rfc_bleGenericRxPar_s rfc_bleGenericRxPar_t; +typedef struct __RFC_STRUCT rfc_bleTxTestPar_s rfc_bleTxTestPar_t; +typedef struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s rfc_bleMasterSlaveOutput_t; +typedef struct __RFC_STRUCT rfc_bleAdvOutput_s rfc_bleAdvOutput_t; +typedef struct __RFC_STRUCT rfc_bleScannerOutput_s rfc_bleScannerOutput_t; +typedef struct __RFC_STRUCT rfc_bleInitiatorOutput_s rfc_bleInitiatorOutput_t; +typedef struct __RFC_STRUCT rfc_bleGenericRxOutput_s rfc_bleGenericRxOutput_t; +typedef struct __RFC_STRUCT rfc_bleTxTestOutput_s rfc_bleTxTestOutput_t; +typedef struct __RFC_STRUCT rfc_bleWhiteListEntry_s rfc_bleWhiteListEntry_t; +typedef struct __RFC_STRUCT rfc_bleRxStatus_s rfc_bleRxStatus_t; + +//! \addtogroup bleRadioOp +//! @{ +struct __RFC_STRUCT rfc_bleRadioOp_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + uint8_t* pParams; //!< Pointer to command specific parameter structure + uint8_t* pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_SLAVE +//! @{ +#define CMD_BLE_SLAVE 0x1801 +//! BLE Slave Command +struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s { + uint16_t commandNo; //!< The command ID number 0x1801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleSlavePar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_MASTER +//! @{ +#define CMD_BLE_MASTER 0x1802 +//! BLE Master Command +struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s { + uint16_t commandNo; //!< The command ID number 0x1802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleMasterPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV +//! @{ +#define CMD_BLE_ADV 0x1803 +//! BLE Connectable Undirected Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_s { + uint16_t commandNo; //!< The command ID number 0x1803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_DIR +//! @{ +#define CMD_BLE_ADV_DIR 0x1804 +//! BLE Connectable Directed Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s { + uint16_t commandNo; //!< The command ID number 0x1804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_NC +//! @{ +#define CMD_BLE_ADV_NC 0x1805 +//! BLE Non-Connectable Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s { + uint16_t commandNo; //!< The command ID number 0x1805 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_SCAN +//! @{ +#define CMD_BLE_ADV_SCAN 0x1806 +//! BLE Scannable Undirected Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s { + uint16_t commandNo; //!< The command ID number 0x1806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_SCANNER +//! @{ +#define CMD_BLE_SCANNER 0x1807 +//! BLE Scanner Command +struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s { + uint16_t commandNo; //!< The command ID number 0x1807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleScannerPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleScannerOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_INITIATOR +//! @{ +#define CMD_BLE_INITIATOR 0x1808 +//! BLE Initiator Command +struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s { + uint16_t commandNo; //!< The command ID number 0x1808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleInitiatorPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleInitiatorOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_GENERIC_RX +//! @{ +#define CMD_BLE_GENERIC_RX 0x1809 +//! BLE Generic Receiver Command +struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s { + uint16_t commandNo; //!< The command ID number 0x1809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleGenericRxPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleGenericRxOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_TX_TEST +//! @{ +#define CMD_BLE_TX_TEST 0x180A +//! BLE PHY Test Transmitter Command +struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x180A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleTxTestPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleTxTestOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_PAYLOAD +//! @{ +#define CMD_BLE_ADV_PAYLOAD 0x1001 +//! BLE Update Advertising Payload Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s { + uint16_t commandNo; //!< The command ID number 0x1001 + uint8_t payloadType; //!< \brief 0: Advertising data
+ //!< 1: Scan response data + uint8_t newLen; //!< Length of the new payload + uint8_t* pNewData; //!< Pointer to the buffer containing the new data + rfc_bleAdvPar_t *pParams; //!< Pointer to the parameter structure to update +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_RADIO_SETUP +//! @{ +#define CMD_BLE5_RADIO_SETUP 0x1820 +//! Define only for compatibility with CC26XXR2F family. Command will result in error if sent. +struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s { + uint8_t dummy0; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleMasterSlavePar +//! @{ +struct __RFC_STRUCT rfc_bleMasterSlavePar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleMasterPar +//! @{ +//! Parameter structure for master (CMD_BLE_MASTER) + +struct __RFC_STRUCT rfc_bleMasterPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleSlavePar +//! @{ +//! Parameter structure for slave (CMD_BLE_SLAVE) + +struct __RFC_STRUCT rfc_bleSlavePar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first + //!< receive operation + uint16_t __dummy0; + uint8_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleAdvPar +//! @{ +//! Parameter structure for advertiser (CMD_BLE_ADV*) + +struct __RFC_STRUCT rfc_bleAdvPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t advFilterPolicy:2; //!< \brief Advertiser filter policy
+ //!< 0: Process scan and connect requests from all devices
+ //!< 1: Process connect requests from all devices and only scan requests from + //!< devices that are in the white list
+ //!< 2: Process scan requests from all devices and only connect requests from + //!< devices that are in the white list
+ //!< 3: Process scan and connect requests only from devices in the white list + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType:1; //!< Directed advertiser: The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t :2; + uint8_t rpaMode:1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } advConfig; + uint8_t advLen; //!< Size of advertiser data + uint8_t scanRspLen; //!< Size of scan response data + uint8_t* pAdvData; //!< Pointer to buffer containing ADV*_IND data + uint8_t* pScanRspData; //!< Pointer to buffer containing SCAN_RSP data + uint16_t* pDeviceAddress; //!< Pointer to device address used for this device + rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list or peer address (directed advertiser) + uint16_t __dummy0; + uint8_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the advertiser event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< advertiser event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleScannerPar +//! @{ +//! Parameter structure for scanner (CMD_BLE_SCANNER) + +struct __RFC_STRUCT rfc_bleScannerPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t scanFilterPolicy:1; //!< \brief Scanning filter policy
+ //!< 0: Accept all advertisement packets
+ //!< 1: Accept only advertisement packets from devices where the advertiser's address + //!< is in the White list. + uint8_t bActiveScan:1; //!< \brief 0: Passive scan
+ //!< 1: Active scan + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t :1; + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t bAutoWlIgnore:1; //!< 1: Automatically set ignore bit in white list + uint8_t bEndOnRpt:1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
+ //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP + uint8_t rpaMode:1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } scanConfig; + uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure + uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth 4.0 spec + struct { + uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure + uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit + //!< not changed + uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not + //!< changed + } backoffPar; + uint8_t scanReqLen; //!< Size of scan request data + uint8_t* pScanReqData; //!< Pointer to buffer containing SCAN_REQ data + uint16_t* pDeviceAddress; //!< Pointer to device address used for this device + rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list + uint16_t __dummy0; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleInitiatorPar +//! @{ +//! Parameter structure for initiator (CMD_BLE_INITIATOR) + +struct __RFC_STRUCT rfc_bleInitiatorPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t bUseWhiteList:1; //!< \brief Initiator filter policy
+ //!< 0: Use specific peer address
+ //!< 1: Use white list + uint8_t bDynamicWinOffset:1; //!< \brief 0: No dynamic WinOffset insertion
+ //!< 1: Use dynamic WinOffset insertion + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType:1; //!< The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + } initConfig; + uint8_t __dummy0; + uint8_t connectReqLen; //!< Size of connect request data + uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_REQ + uint16_t* pDeviceAddress; //!< Pointer to device address used for this device + rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list or peer address + ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. + //!< Set to the calculated value if a connection is made and to the next possible connection + //!< time if not. + uint16_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleGenericRxPar +//! @{ +//! Parameter structure for generic Rx (CMD_BLE_GENERIC_RX) + +struct __RFC_STRUCT rfc_bleGenericRxPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue. May be NULL; if so, received packets are not stored + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + uint8_t bRepeat; //!< \brief 0: End operation after receiving a packet
+ //!< 1: Restart receiver after receiving a packet + uint16_t __dummy0; + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Rx operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleTxTestPar +//! @{ +//! Parameter structure for Tx test (CMD_BLE_TX_TEST) + +struct __RFC_STRUCT rfc_bleTxTestPar_s { + uint16_t numPackets; //!< \brief Number of packets to transmit
+ //!< 0: Transmit unlimited number of packets + uint8_t payloadLength; //!< The number of payload bytes in each packet. + uint8_t packetType; //!< \brief The packet type to be used, encoded according to the Bluetooth 4.0 spec, Volume 2, Part E, + //!< Section 7.8.29 + ratmr_t period; //!< Number of radio timer cycles between the start of each packet + struct { + uint8_t bOverrideDefault:1; //!< \brief 0: Use default packet encoding
+ //!< 1: Override packet contents + uint8_t bUsePrbs9:1; //!< \brief If bOverride is 1:
+ //!< 1: Use PRBS9 encoding of packet + uint8_t bUsePrbs15:1; //!< \brief If bOverride is 1:
+ //!< 1: Use PRBS15 encoding of packet + } config; + uint8_t byteVal; //!< If config.bOverride is 1, value of each byte to be sent + uint8_t __dummy0; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Test Tx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Test Tx operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleMasterSlaveOutput +//! @{ +//! Output structure for master and slave (CMD_BLE_MASTER and CMD_BLE_SLAVE) + +struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s { + uint8_t nTx; //!< \brief Total number of packets (including auto-empty and retransmissions) that have been + //!< transmitted + uint8_t nTxAck; //!< Total number of transmitted packets (including auto-empty) that have been ACK'ed + uint8_t nTxCtrl; //!< Number of unique LL control packets from the Tx queue that have been transmitted + uint8_t nTxCtrlAck; //!< Number of LL control packets from the Tx queue that have been finished (ACK'ed) + uint8_t nTxCtrlAckAck; //!< \brief Number of LL control packets that have been ACK'ed and where an ACK has been sent in + //!< response + uint8_t nTxRetrans; //!< Number of retransmissions that has been done + uint8_t nTxEntryDone; //!< Number of packets from the Tx queue that have been finished (ACK'ed) + uint8_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint8_t nRxCtrl; //!< Number of LL control packets that have been received with CRC OK and not ignored + uint8_t nRxCtrlAck; //!< \brief Number of LL control packets that have been received with CRC OK and not ignored, and + //!< then ACK'ed + uint8_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< \brief Number of packets that have been received with CRC OK and ignored due to repeated + //!< sequence number + uint8_t nRxEmpty; //!< Number of packets that have been received with CRC OK and no payload + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + struct { + uint8_t bTimeStampValid:1; //!< 1 if a valid time stamp has been written to timeStamp; 0 otherwise + uint8_t bLastCrcErr:1; //!< 1 if the last received packet had CRC error; 0 otherwise + uint8_t bLastIgnored:1; //!< 1 if the last received packet with CRC OK was ignored; 0 otherwise + uint8_t bLastEmpty:1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise + uint8_t bLastCtrl:1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise + uint8_t bLastMd:1; //!< 1 if the last received packet with CRC OK had MD = 1; 0 otherwise + uint8_t bLastAck:1; //!< \brief 1 if the last received packet with CRC OK was an ACK of a transmitted packet; + //!< 0 otherwise + } pktStatus; + ratmr_t timeStamp; //!< Slave operation: Time stamp of first received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleAdvOutput +//! @{ +//! Output structure for advertiser (CMD_BLE_ADV*) + +struct __RFC_STRUCT rfc_bleAdvOutput_s { + uint16_t nTxAdvInd; //!< Number of ADV*_IND packets completely transmitted + uint8_t nTxScanRsp; //!< Number of SCAN_RSP packets transmitted + uint8_t nRxScanReq; //!< Number of SCAN_REQ packets received OK and not ignored + uint8_t nRxConnectReq; //!< Number of CONNECT_REQ packets received OK and not ignored + uint8_t __dummy0; + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxIgnored; //!< Number of packets received with CRC OK, but ignored + uint8_t nRxBufFull; //!< Number of packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet + ratmr_t timeStamp; //!< Time stamp of the last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleScannerOutput +//! @{ +//! Output structure for scanner (CMD_BLE_SCANNER) + +struct __RFC_STRUCT rfc_bleScannerOutput_s { + uint16_t nTxScanReq; //!< Number of transmitted SCAN_REQ packets + uint16_t nBackedOffScanReq; //!< Number of SCAN_REQ packets not sent due to backoff procedure + uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint16_t nRxScanRspOk; //!< Number of SCAN_RSP packets received with CRC OK and not ignored + uint16_t nRxScanRspIgnored; //!< Number of SCAN_RSP packets received with CRC OK, but ignored + uint16_t nRxScanRspNok; //!< Number of SCAN_RSP packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + uint8_t nRxScanRspBufFull; //!< Number of SCAN_RSP packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last successfully received ADV*_IND packet that was not ignored +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleInitiatorOutput +//! @{ +//! Output structure for initiator (CMD_BLE_INITIATOR) + +struct __RFC_STRUCT rfc_bleInitiatorOutput_s { + uint8_t nTxConnectReq; //!< Number of transmitted CONNECT_REQ packets + uint8_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet + ratmr_t timeStamp; //!< Time stamp of the received ADV*_IND packet that caused transmission of CONNECT_REQ +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleGenericRxOutput +//! @{ +//! Output structure for generic Rx (CMD_BLE_GENERIC_RX) + +struct __RFC_STRUCT rfc_bleGenericRxOutput_s { + uint16_t nRxOk; //!< Number of packets received with CRC OK + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< The RSSI of the last received packet + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleTxTestOutput +//! @{ +//! Output structure for Tx test (CMD_BLE_TX_TEST) + +struct __RFC_STRUCT rfc_bleTxTestOutput_s { + uint16_t nTx; //!< Number of packets transmitted +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleWhiteListEntry +//! @{ +//! White list entry structure + +struct __RFC_STRUCT rfc_bleWhiteListEntry_s { + uint8_t size; //!< Number of while list entries. Used in the first entry of the list only + struct { + uint8_t bEnable:1; //!< 1 if the entry is in use, 0 if the entry is not in use + uint8_t addrType:1; //!< The type address in the entry -- public (0) or random (1) + uint8_t bWlIgn:1; //!< \brief 1 if the entry is to be ignored by a scanner, 0 otherwise. Used to mask out + //!< entries that have already been scanned and reported. + uint8_t :1; + uint8_t bIrkValid:1; //!< \brief 1 if a valid IRK exists, so that the entry is to be ignored by an initiator, + //!< 0 otherwise + } conf; + uint16_t address; //!< Least significant 16 bits of the address contained in the entry + uint32_t addressHi; //!< Most significant 32 bits of the address contained in the entry +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleRxStatus +//! @{ +//! Receive status byte that may be appended to message in receive buffer + +struct __RFC_STRUCT rfc_bleRxStatus_s { + struct { + uint8_t channel:6; //!< \brief The channel on which the packet was received, provided channel is in the range + //!< 0--39; otherwise 0x3F + uint8_t bIgnore:1; //!< 1 if the packet is marked as ignored, 0 otherwise + uint8_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_mailbox.h new file mode 100644 index 0000000..4158977 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_mailbox.h @@ -0,0 +1,68 @@ +/****************************************************************************** +* Filename: rf_ble_mailbox.h +* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) +* Revision: 18032 +* +* Description: Definitions for BLE interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _BLE_MAILBOX_H +#define _BLE_MAILBOX_H + +/// \name Radio operation status +///@{ +/// \name Operation finished normally +///@{ +#define BLE_DONE_OK 0x1400 ///< Operation ended normally +#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window +#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx +#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other) +#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_REQ received or transmitted +#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded +#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger +#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command +#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command +///@} +/// \name Operation finished with error +///@{ +#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter +#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator) +#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attemted when not in BLE mode +#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attemted without frequency synth configured +#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time +#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation +#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation +///@} +///@} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_common_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_common_cmd.h new file mode 100644 index 0000000..0495d1c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_common_cmd.h @@ -0,0 +1,933 @@ +/****************************************************************************** +* Filename: rf_common_cmd.h +* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) +* Revision: 18052 +* +* Description: CC13x0 API for common/generic commands +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __COMMON_CMD_H +#define __COMMON_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup common_cmd +//! @{ + +#include +#include "rf_mailbox.h" + +typedef struct __RFC_STRUCT rfc_command_s rfc_command_t; +typedef struct __RFC_STRUCT rfc_radioOp_s rfc_radioOp_t; +typedef struct __RFC_STRUCT rfc_CMD_NOP_s rfc_CMD_NOP_t; +typedef struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s rfc_CMD_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_s rfc_CMD_FS_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_OFF_s rfc_CMD_FS_OFF_t; +typedef struct __RFC_STRUCT rfc_CMD_RX_TEST_s rfc_CMD_RX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_TX_TEST_s rfc_CMD_TX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s rfc_CMD_SYNC_STOP_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s rfc_CMD_SYNC_START_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_COUNT_s rfc_CMD_COUNT_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s rfc_CMD_FS_POWERUP_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s rfc_CMD_FS_POWERDOWN_t; +typedef struct __RFC_STRUCT rfc_CMD_SCH_IMM_s rfc_CMD_SCH_IMM_t; +typedef struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s rfc_CMD_COUNT_BRANCH_t; +typedef struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s rfc_CMD_PATTERN_CHECK_t; +typedef struct __RFC_STRUCT rfc_CMD_ABORT_s rfc_CMD_ABORT_t; +typedef struct __RFC_STRUCT rfc_CMD_STOP_s rfc_CMD_STOP_t; +typedef struct __RFC_STRUCT rfc_CMD_GET_RSSI_s rfc_CMD_GET_RSSI_t; +typedef struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s rfc_CMD_UPDATE_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_TRIGGER_s rfc_CMD_TRIGGER_t; +typedef struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s rfc_CMD_GET_FW_INFO_t; +typedef struct __RFC_STRUCT rfc_CMD_START_RAT_s rfc_CMD_START_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_PING_s rfc_CMD_PING_t; +typedef struct __RFC_STRUCT rfc_CMD_READ_RFREG_s rfc_CMD_READ_RFREG_t; +typedef struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s rfc_CMD_ADD_DATA_ENTRY_t; +typedef struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s rfc_CMD_REMOVE_DATA_ENTRY_t; +typedef struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s rfc_CMD_FLUSH_QUEUE_t; +typedef struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s rfc_CMD_CLEAR_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s rfc_CMD_REMOVE_PENDING_ENTRIES_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s rfc_CMD_SET_RAT_CMP_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s rfc_CMD_SET_RAT_CPT_t; +typedef struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s rfc_CMD_DISABLE_RAT_CH_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s rfc_CMD_SET_RAT_OUTPUT_t; +typedef struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s rfc_CMD_ARM_RAT_CH_t; +typedef struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s rfc_CMD_DISARM_RAT_CH_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s rfc_CMD_SET_TX_POWER_t; +typedef struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s rfc_CMD_UPDATE_FS_t; +typedef struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s rfc_CMD_BUS_REQUEST_t; + +//! \addtogroup command +//! @{ +struct __RFC_STRUCT rfc_command_s { + uint16_t commandNo; //!< The command ID number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup radioOp +//! @{ +//! Common definition for radio operation commands + +struct __RFC_STRUCT rfc_radioOp_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_NOP +//! @{ +#define CMD_NOP 0x0801 +//! No Operation Command +struct __RFC_STRUCT rfc_CMD_NOP_s { + uint16_t commandNo; //!< The command ID number 0x0801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_RADIO_SETUP +//! @{ +#define CMD_RADIO_SETUP 0x0802 +//! Radio Setup Command for Pre-Defined Schemes +struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x0802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t mode; //!< \brief The main mode to use
+ //!< 0x00: BLE
+ //!< 0x01: IEEE 802.15.4
+ //!< 0x02: 2 Mbps GFSK
+ //!< 0x05: 5 Mbps coded 8-FSK
+ //!< 0xFF: Keep existing mode; update overrides only
+ //!< Others: Reserved + uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0 (equivalent to 2), 2, + //!< 5, 6, 10, 12, 15, and 30.
+ //!< Value of 0 or 2 only supported for CC1350 + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS +//! @{ +#define CMD_FS 0x0803 +//! Frequency Synthesizer Programming Command +struct __RFC_STRUCT rfc_CMD_FS_s { + uint16_t commandNo; //!< The command ID number 0x0803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to + struct { + uint8_t bTxMode:1; //!< \brief 0: Start synth in RX mode
+ //!< 1: Start synth in TX mode + uint8_t refFreq:6; //!< \brief 0: Use default reference frequency
+ //!< Others: Use reference frequency 24 MHz/refFreq + } synthConf; + uint8_t __dummy0; //!< Reserved, always write 0 + uint8_t __dummy1; //!< Reserved + uint8_t __dummy2; //!< Reserved + uint16_t __dummy3; //!< Reserved +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS_OFF +//! @{ +#define CMD_FS_OFF 0x0804 +//! Command for Turning off Frequency Synthesizer +struct __RFC_STRUCT rfc_CMD_FS_OFF_s { + uint16_t commandNo; //!< The command ID number 0x0804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_RX_TEST +//! @{ +#define CMD_RX_TEST 0x0807 +//! Receiver Test Command +struct __RFC_STRUCT rfc_CMD_RX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x0807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bEnaFifo:1; //!< \brief 0: Do not enable FIFO in modem, so that received data is not available
+ //!< 1: Enable FIFO in modem -- the data must be read out by the application + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bNoSync:1; //!< \brief 0: Run sync search as normal for the configured mode
+ //!< 1: Write correlation thresholds to the maximum value to avoid getting sync + } config; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for receiver + ratmr_t endTime; //!< Time to end the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_TX_TEST +//! @{ +#define CMD_TX_TEST 0x0808 +//! Transmitter Test Command +struct __RFC_STRUCT rfc_CMD_TX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x0808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bUseCw:1; //!< \brief 0: Send modulated signal
+ //!< 1: Send continuous wave + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t whitenMode:2; //!< \brief 0: No whitening
+ //!< 1: Default whitening
+ //!< 2: PRBS-15
+ //!< 3: PRBS-32 + } config; + uint8_t __dummy0; + uint16_t txWord; //!< Value to send to the modem before whitening + uint8_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for transmitter + ratmr_t endTime; //!< Time to end the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SYNC_STOP_RAT +//! @{ +#define CMD_SYNC_STOP_RAT 0x0809 +//! Synchronize and Stop Radio Timer Command +struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s { + uint16_t commandNo; //!< The command ID number 0x0809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The returned RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SYNC_START_RAT +//! @{ +#define CMD_SYNC_START_RAT 0x080A +//! Synchrously Start Radio Timer Command +struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s { + uint16_t commandNo; //!< The command ID number 0x080A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero. This parameter is returned by CMD_SYNC_STOP_RAT +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_COUNT +//! @{ +#define CMD_COUNT 0x080B +//! Counter Command +struct __RFC_STRUCT rfc_CMD_COUNT_s { + uint16_t commandNo; //!< The command ID number 0x080B + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS_POWERUP +//! @{ +#define CMD_FS_POWERUP 0x080C +//! Power up Frequency Syntheszier Command +struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s { + uint16_t commandNo; //!< The command ID number 0x080C + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS_POWERDOWN +//! @{ +#define CMD_FS_POWERDOWN 0x080D +//! Power down Frequency Syntheszier Command +struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s { + uint16_t commandNo; //!< The command ID number 0x080D + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SCH_IMM +//! @{ +#define CMD_SCH_IMM 0x0810 +//! Run Immidiate Command as Radio Operation Command +struct __RFC_STRUCT rfc_CMD_SCH_IMM_s { + uint16_t commandNo; //!< The command ID number 0x0810 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t cmdrVal; //!< Value as would be written to CMDR + uint32_t cmdstaVal; //!< Value as would be returned in CMDSTA +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_COUNT_BRANCH +//! @{ +#define CMD_COUNT_BRANCH 0x0812 +//! Counter Command with Branch of Command Chain +struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s { + uint16_t commandNo; //!< The command ID number 0x0812 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero + rfc_radioOp_t *pNextOpIfOk; //!< Pointer to next operation if counter did not expire +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PATTERN_CHECK +//! @{ +#define CMD_PATTERN_CHECK 0x0813 +//! Command for Checking a Value in Memory aginst a Pattern +struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s { + uint16_t commandNo; //!< The command ID number 0x0813 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t operation:2; //!< \brief Operation to perform
+ //!< 0: True if value == compareVal
+ //!< 1: True if value < compareVal
+ //!< 2: True if value > compareVal
+ //!< 3: Reserved + uint16_t bByteRev:1; //!< \brief If 1, interchange the four bytes of the value, so that they are read + //!< most-significant-byte-first. + uint16_t bBitRev:1; //!< If 1, perform bit reversal of the value + uint16_t signExtend:5; //!< \brief 0: Treat value and compareVal as unsigned
+ //!< 1--31: Treat value and compareVal as signed, where the value + //!< gives the number of the most significant bit in the signed number. + uint16_t bRxVal:1; //!< \brief 0: Use pValue as a pointer
+ //!< 1: Use pValue as a signed offset to the start of the last + //!< committed RX entry element + } patternOpt; //!< Options for comparison + rfc_radioOp_t *pNextOpIfOk; //!< Pointer to next operation if comparison result was true + uint8_t* pValue; //!< Pointer to read from, or offset from last RX entry if patternOpt.bRxVal == 1 + uint32_t mask; //!< Bit mask to apply before comparison + uint32_t compareVal; //!< Value to compare to +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_ABORT +//! @{ +#define CMD_ABORT 0x0401 +//! Abort Running Radio Operation Command +struct __RFC_STRUCT rfc_CMD_ABORT_s { + uint16_t commandNo; //!< The command ID number 0x0401 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_STOP +//! @{ +#define CMD_STOP 0x0402 +//! Stop Running Radio Operation Command Gracefully +struct __RFC_STRUCT rfc_CMD_STOP_s { + uint16_t commandNo; //!< The command ID number 0x0402 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_GET_RSSI +//! @{ +#define CMD_GET_RSSI 0x0403 +//! Read RSSI Command +struct __RFC_STRUCT rfc_CMD_GET_RSSI_s { + uint16_t commandNo; //!< The command ID number 0x0403 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_UPDATE_RADIO_SETUP +//! @{ +#define CMD_UPDATE_RADIO_SETUP 0x0001 +//! Update Radio Settings Command +struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x0001 + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_TRIGGER +//! @{ +#define CMD_TRIGGER 0x0404 +//! Generate Command Trigger +struct __RFC_STRUCT rfc_CMD_TRIGGER_s { + uint16_t commandNo; //!< The command ID number 0x0404 + uint8_t triggerNo; //!< Command trigger number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_GET_FW_INFO +//! @{ +#define CMD_GET_FW_INFO 0x0002 +//! Request Information on the RF Core ROM Firmware +struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s { + uint16_t commandNo; //!< The command ID number 0x0002 + uint16_t versionNo; //!< Firmware version number + uint16_t startOffset; //!< The start of free RAM + uint16_t freeRamSz; //!< The size of free RAM + uint16_t availRatCh; //!< Bitmap of available RAT channels +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_START_RAT +//! @{ +#define CMD_START_RAT 0x0405 +//! Asynchronously Start Radio Timer Command +struct __RFC_STRUCT rfc_CMD_START_RAT_s { + uint16_t commandNo; //!< The command ID number 0x0405 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PING +//! @{ +#define CMD_PING 0x0406 +//! Respond with Command ACK Only +struct __RFC_STRUCT rfc_CMD_PING_s { + uint16_t commandNo; //!< The command ID number 0x0406 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_READ_RFREG +//! @{ +#define CMD_READ_RFREG 0x0601 +//! Read RF Core Hardware Register +struct __RFC_STRUCT rfc_CMD_READ_RFREG_s { + uint16_t commandNo; //!< The command ID number 0x0601 + uint16_t address; //!< The offset from the start of the RF core HW register bank (0x40040000) + uint32_t value; //!< Returned value of the register +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_ADD_DATA_ENTRY +//! @{ +#define CMD_ADD_DATA_ENTRY 0x0005 +//! Add Data Entry to Queue +struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s { + uint16_t commandNo; //!< The command ID number 0x0005 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to which the entry will be added + uint8_t* pEntry; //!< Pointer to the entry +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_REMOVE_DATA_ENTRY +//! @{ +#define CMD_REMOVE_DATA_ENTRY 0x0006 +//! Remove First Data Entry from Queue +struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s { + uint16_t commandNo; //!< The command ID number 0x0006 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure from which the entry will be removed + uint8_t* pEntry; //!< Pointer to the entry that was removed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FLUSH_QUEUE +//! @{ +#define CMD_FLUSH_QUEUE 0x0007 +//! Flush Data Queue +struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s { + uint16_t commandNo; //!< The command ID number 0x0007 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_CLEAR_RX +//! @{ +#define CMD_CLEAR_RX 0x0008 +//! Clear all RX Queue Entries +struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s { + uint16_t commandNo; //!< The command ID number 0x0008 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be cleared +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_REMOVE_PENDING_ENTRIES +//! @{ +#define CMD_REMOVE_PENDING_ENTRIES 0x0009 +//! Remove Pending Entries from Queue +struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s { + uint16_t commandNo; //!< The command ID number 0x0009 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_RAT_CMP +//! @{ +#define CMD_SET_RAT_CMP 0x000A +//! Set Radio Timer Channel in Compare Mode +struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s { + uint16_t commandNo; //!< The command ID number 0x000A + uint8_t ratCh; //!< The radio timer channel number + uint8_t __dummy0; + ratmr_t compareTime; //!< The time at which the compare occurs +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_RAT_CPT +//! @{ +#define CMD_SET_RAT_CPT 0x0603 +//! Set Radio Timer Channel in Capture Mode +struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s { + uint16_t commandNo; //!< The command ID number 0x0603 + struct { + uint16_t :3; + uint16_t inputSrc:5; //!< Input source indicator + uint16_t ratCh:4; //!< The radio timer channel number + uint16_t bRepeated:1; //!< \brief 0: Single capture mode
+ //!< 1: Repeated capture mode + uint16_t inputMode:2; //!< \brief Input mode:
+ //!< 0: Capture on rising edge
+ //!< 1: Capture on falling edge
+ //!< 2: Capture on both edges
+ //!< 3: Reserved + } config; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_DISABLE_RAT_CH +//! @{ +#define CMD_DISABLE_RAT_CH 0x0408 +//! Disable Radio Timer Channel +struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s { + uint16_t commandNo; //!< The command ID number 0x0408 + uint8_t ratCh; //!< The radio timer channel number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_RAT_OUTPUT +//! @{ +#define CMD_SET_RAT_OUTPUT 0x0604 +//! Set Radio Timer Output to a Specified Mode +struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s { + uint16_t commandNo; //!< The command ID number 0x0604 + struct { + uint16_t :2; + uint16_t outputSel:3; //!< Output event indicator + uint16_t outputMode:3; //!< \brief 0: Set output line low as default; and pulse on event. Duration of pulse is one RF Core clock period (ca. 41.67 ns).
+ //!< 1: Set output line high on event
+ //!< 2: Set output line low on event
+ //!< 3: Toggle (invert) output line state on event
+ //!< 4: Immediately set output line to low (does not change upon event)
+ //!< 5: Immediately set output line to high (does not change upon event)
+ //!< Others: Reserved + uint16_t ratCh:4; //!< The radio timer channel number + } config; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_ARM_RAT_CH +//! @{ +#define CMD_ARM_RAT_CH 0x0409 +//! Arm Radio Timer Channel +struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s { + uint16_t commandNo; //!< The command ID number 0x0409 + uint8_t ratCh; //!< The radio timer channel number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_DISARM_RAT_CH +//! @{ +#define CMD_DISARM_RAT_CH 0x040A +//! Disarm Radio Timer Channel +struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s { + uint16_t commandNo; //!< The command ID number 0x040A + uint8_t ratCh; //!< The radio timer channel number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_TX_POWER +//! @{ +#define CMD_SET_TX_POWER 0x0010 +//! Set Transmit Power +struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s { + uint16_t commandNo; //!< The command ID number 0x0010 + uint16_t txPower; //!< New TX power setting +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_UPDATE_FS +//! @{ +#define CMD_UPDATE_FS 0x0011 +//! Set New Synthesizer Frequency without Recalibration +struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s { + uint16_t commandNo; //!< The command ID number 0x0011 + uint16_t __dummy0; + uint32_t __dummy1; + uint32_t __dummy2; + uint16_t __dummy3; + uint16_t frequency; //!< The frequency in MHz to tune to, compensated for LO divider setting + uint16_t fractFreq; //!< Fractional part of the frequency to tune to +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BUS_REQUEST +//! @{ +#define CMD_BUS_REQUEST 0x040E +//! Request System Bus to be Availbale +struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s { + uint16_t commandNo; //!< The command ID number 0x040E + uint8_t bSysBusNeeded; //!< \brief 0: System bus may sleep
+ //!< 1: System bus access needed +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_data_entry.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_data_entry.h new file mode 100644 index 0000000..026ba9d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_data_entry.h @@ -0,0 +1,219 @@ +/****************************************************************************** +* Filename: rf_data_entry.h +* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) +* Revision: 18052 +* +* Description: Definition of API for data exchange +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __DATA_ENTRY_H +#define __DATA_ENTRY_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup data_entry +//! @{ + +#include +#include "rf_mailbox.h" + +typedef struct __RFC_STRUCT rfc_dataEntry_s rfc_dataEntry_t; +typedef struct __RFC_STRUCT rfc_dataEntryGeneral_s rfc_dataEntryGeneral_t; +typedef struct __RFC_STRUCT rfc_dataEntryMulti_s rfc_dataEntryMulti_t; +typedef struct __RFC_STRUCT rfc_dataEntryPointer_s rfc_dataEntryPointer_t; +typedef struct __RFC_STRUCT rfc_dataEntryPartial_s rfc_dataEntryPartial_t; + +//! \addtogroup dataEntry +//! @{ +struct __RFC_STRUCT rfc_dataEntry_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryGeneral +//! @{ +//! General data entry structure (type = 0) + +struct __RFC_STRUCT rfc_dataEntryGeneral_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t data; //!< First byte of the data array to be received or transmitted +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryMulti +//! @{ +//! Multi-element data entry structure (type = 1) + +struct __RFC_STRUCT rfc_dataEntryMulti_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint16_t numElements; //!< Number of entry elements committed in the entry + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryPointer +//! @{ +//! Pointer data entry structure (type = 2) + +struct __RFC_STRUCT rfc_dataEntryPointer_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryPartial +//! @{ +//! Partial read data entry structure (type = 3) + +struct __RFC_STRUCT rfc_dataEntryPartial_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + struct { + uint16_t numElements:13; //!< Number of entry elements committed in the entry + uint16_t bEntryOpen:1; //!< 1 if the entry contains an element that is still open for appending data + uint16_t bFirstCont:1; //!< 1 if the first element is a continuation of the last packet from the previous entry + uint16_t bLastCont:1; //!< 1 if the packet in the last element continues in the next entry + } pktStatus; + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_cmd.h new file mode 100644 index 0000000..ce01015 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_cmd.h @@ -0,0 +1,210 @@ +/****************************************************************************** +* Filename: rf_hs_cmd.h +* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) +* Revision: 18052 +* +* Description: CC13x0 API for high-speed mode commands +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HS_CMD_H +#define __HS_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup hs_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_CMD_HS_TX_s rfc_CMD_HS_TX_t; +typedef struct __RFC_STRUCT rfc_CMD_HS_RX_s rfc_CMD_HS_RX_t; +typedef struct __RFC_STRUCT rfc_hsRxOutput_s rfc_hsRxOutput_t; +typedef struct __RFC_STRUCT rfc_hsRxStatus_s rfc_hsRxStatus_t; + +//! \addtogroup CMD_HS_TX +//! @{ +#define CMD_HS_TX 0x3841 +//! High-Speed Transmit Command +struct __RFC_STRUCT rfc_CMD_HS_TX_s { + uint16_t commandNo; //!< The command ID number 0x3841 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Transmit length as first half-word + uint8_t bCheckQAtEnd:1; //!< \brief 0: Always end with HS_DONE_OK when packet has been transmitted
+ //!< 1: Check if Tx queue is empty when packet has been transmitted + } pktConf; + uint8_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to Tx queue +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_HS_RX +//! @{ +#define CMD_HS_RX 0x3842 +//! High-Speed Receive Command +struct __RFC_STRUCT rfc_CMD_HS_RX_s { + uint16_t commandNo; //!< The command ID number 0x3842 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bUseCrc:1; //!< \brief 0: Do not receive or check CRC
+ //!< 1: Receive and check CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t addressMode:2; //!< \brief 0: No address check
+ //!< 1: Accept address0 and address1
+ //!< 2: Accept address0, address1, and 0x0000
+ //!< 3: Accept address0, address1, 0x0000, and 0xFFFF + } pktConf; + struct { + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bIncludeLen:1; //!< If 1, include the received length field in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise 3scard it + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConf; + uint16_t maxPktLen; //!< Packet length for fixed length; maximum packet length for variable length + uint16_t address0; //!< Address + uint16_t address1; //!< Address (set equal to address0 to accept only one address) + uint8_t __dummy0; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + rfc_hsRxOutput_t *pOutput; //!< Pointer to output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup hsRxOutput +//! @{ +//! Output structure for CMD_HS_RX + +struct __RFC_STRUCT rfc_hsRxOutput_s { + uint16_t nRxOk; //!< Number of packets that have been received with CRC OK + uint16_t nRxNok; //!< Number of packets that have been received with CRC error + uint16_t nRxAborted; //!< Number of packets not received due to illegal length or address mismatch + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + ratmr_t timeStamp; //!< Time stamp of last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup hsRxStatus +//! @{ +//! Receive status word that may be appended to message in receive buffer + +struct __RFC_STRUCT rfc_hsRxStatus_s { + struct { + uint16_t rssi:8; //!< RSSI of the received packet in dBm (signed) + uint16_t bCrcErr:1; //!< \brief 0: Packet received OK
+ //!< 1: Packet received with CRC error + uint16_t addressInd:2; //!< \brief 0: Received address0 (or no address check)
+ //!< 1: Received address1
+ //!< 2: Received address 0x0000
+ //!< 3: Received address 0xFFFF + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_mailbox.h new file mode 100644 index 0000000..2ad5bcd --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_mailbox.h @@ -0,0 +1,65 @@ +/****************************************************************************** +* Filename: rf_hs_mailbox.h +* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) +* Revision: 18032 +* +* Description: Definitions for high-speed mode radio interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _HS_MAILBOX_H +#define _HS_MAILBOX_H + +/// \name Radio operation status +///@{ +/// \name Operation finished normally +///@{ +#define HS_DONE_OK 0x3440 ///< Operation ended normally +#define HS_DONE_RXTIMEOUT 0x3441 ///< Operation stopped after end trigger while waiting for sync +#define HS_DONE_RXERR 0x3442 ///< Operation ended after CRC error +#define HS_DONE_TXBUF 0x3443 ///< Tx queue was empty at start of operation +#define HS_DONE_ENDED 0x3444 ///< Operation stopped after end trigger during reception +#define HS_DONE_STOPPED 0x3445 ///< Operation stopped after stop command +#define HS_DONE_ABORT 0x3446 ///< Operation aborted by abort command +///@} +/// \name Operation finished with error +///@{ +#define HS_ERROR_PAR 0x3840 ///< Illegal parameter +#define HS_ERROR_RXBUF 0x3841 ///< No available Rx buffer at the start of a packet +#define HS_ERROR_NO_SETUP 0x3842 ///< Radio was not set up in a compatible mode +#define HS_ERROR_NO_FS 0x3843 ///< Synth was not programmed when running Rx or Tx +#define HS_ERROR_RXOVF 0x3844 ///< Rx overflow observed during operation +#define HS_ERROR_TXUNF 0x3845 ///< Tx underflow observed during operation +///@} +///@} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_mailbox.h new file mode 100644 index 0000000..e22eef1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_mailbox.h @@ -0,0 +1,341 @@ +/****************************************************************************** +* Filename: rf_mailbox.h +* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) +* Revision: 18032 +* +* Description: Definitions for interface between system and radio CPU +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _MAILBOX_H +#define _MAILBOX_H + +#include +#include + + +/// \name RF mode values +/// Defines used to indicate mode of operation to radio core. +///@{ +#define RF_MODE_PROPRIETARY_SUB_1 0x00 +#define RF_MODE_BLE 0x01 +#define RF_MODE_IEEE_15_4 0x02 +#define RF_MODE_PROPRIETARY_2_4 0x03 +#define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4 +#define RF_MODE_MULTIPLE 0x05 +///@} + + +/// Type definition for RAT +typedef uint32_t ratmr_t; + + + +/// Type definition for a data queue +typedef struct { + uint8_t *pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue + uint8_t *pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue +} dataQueue_t; + + + +/// \name CPE interrupt definitions +/// Interrupt masks for the CPE interrupt in RDBELL. +///@{ +#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished +#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished +#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished +#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished +#define IRQN_TX_DONE 4 ///< Packet transmitted +#define IRQN_TX_ACK 5 ///< ACK packet transmitted +#define IRQN_TX_CTRL 6 ///< Control packet transmitted +#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet +#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet +#define IRQN_TX_RETRANS 9 ///< Packet retransmitted +#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished +#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete +#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored +#define IRQN_RX_NOK 17 ///< Packet received with CRC error +#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored +#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload +#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored +#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent +#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue +#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished +#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer +#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer +#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done +#define IRQN_RX_COLLISION_DETECTED 27 ///< A collision was indicated during packet reception +#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration +#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories +#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished + +#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed + +#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE) +#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE) +#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE) +#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE) + +#define IRQ_TX_DONE (1U << IRQN_TX_DONE) +#define IRQ_TX_ACK (1U << IRQN_TX_ACK) +#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL) +#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK) +#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK) +#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS) + +#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE) +#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED) + +#define IRQ_RX_OK (1U << IRQN_RX_OK) +#define IRQ_RX_NOK (1U << IRQN_RX_NOK) +#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED) +#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY) +#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL) +#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK) +#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL) +#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE) +#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN) +#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN) +#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED) +#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED) +#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK) +#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED) +#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE) +#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR) +///@} + + + +/// \name CMDSTA values +/// Values returned in result byte of CMDSTA +///@{ +#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed +#define CMDSTA_Done 0x01 ///< Command successfully parsed + +#define CMDSTA_IllegalPointer 0x81 ///< The pointer signaled in CMDR is not valid +#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown +#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the + ///< command is not a direct command +#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context + ///< where it is not supported +#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled + ///< while another operation was already running in the RF core +#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed + ///< on submission. +#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was + ///< not supported by the queue in its current state +#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry + ///< was busy +///@} + + + +/// \name Macros for sending direct commands +///@{ +/// Direct command with no parameter +#define CMDR_DIR_CMD(cmdId) (((cmdId) << 16) | 1) + +/// Direct command with 1-byte parameter +#define CMDR_DIR_CMD_1BYTE(cmdId, par) (((cmdId) << 16) | ((par) << 8) | 1) + +/// Direct command with 2-byte parameter +#define CMDR_DIR_CMD_2BYTE(cmdId, par) (((cmdId) << 16) | ((par) & 0xFFFC) | 1) + +///@} + + + +/// \name Definitions for trigger types +///@{ +#define TRIG_NOW 0 ///< Triggers immediately +#define TRIG_NEVER 1 ///< Never trigs +#define TRIG_ABSTIME 2 ///< Trigs at an absolute time +#define TRIG_REL_SUBMIT 3 ///< Trigs at a time relative to the command was submitted +#define TRIG_REL_START 4 ///< Trigs at a time relative to the command started +#define TRIG_REL_PREVSTART 5 ///< Trigs at a time relative to the previous command in the chain started +#define TRIG_REL_FIRSTSTART 6 ///< Trigs at a time relative to the first command in the chain started +#define TRIG_REL_PREVEND 7 ///< Trigs at a time relative to the previous command in the chain ended +#define TRIG_REL_EVT1 8 ///< Trigs at a time relative to the context defined "Event 1" +#define TRIG_REL_EVT2 9 ///< Trigs at a time relative to the context defined "Event 2" +#define TRIG_EXTERNAL 10 ///< Trigs at an external event to the radio timer +#define TRIG_PAST_BM 0x80 ///< Bitmask for setting pastTrig bit in order to trig immediately if + ///< trigger happened in the past +///@} + + +/// \name Definitions for conditional execution +///@{ +#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort) +#define COND_NEVER 1 ///< Never run next command +#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned + ///< False +#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned + ///< False +#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of + ///< commands if it returned False +#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next + ///< command if it returned False +///@} + + + +/// \name Radio operation status +///@{ +/// \name Operation not finished +///@{ +#define IDLE 0x0000 ///< Operation not started +#define PENDING 0x0001 ///< Start of command is pending +#define ACTIVE 0x0002 ///< Running +#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command +///@} +/// \name Operation finished normally +///@{ +#define DONE_OK 0x0400 ///< Operation ended normally +#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero +#define DONE_RXERR 0x0402 ///< Operation ended with CRC error +#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout +#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command +#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command +#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed +///@} +/// \name Operation finished with error +///@{ +#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past +#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter +#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation +#define ERROR_PAR 0x0803 ///< Error in a command specific parameter +#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation +#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio + ///< operation command +#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command +#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attemted without CMD_RADIO_SETUP +#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attemted without frequency synth configured +#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed +#define ERROR_TXUNF 0x080A ///< Tx underflow observed +#define ERROR_RXOVF 0x080B ///< Rx overflow observed +#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received +#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending +///@} +///@} + + +/// \name Data entry types +///@{ +#define DATA_ENTRY_TYPE_GEN 0 ///< General type: Tx entry or single element Rx entry +#define DATA_ENTRY_TYPE_MULTI 1 ///< Multi-element Rx entry type +#define DATA_ENTRY_TYPE_PTR 2 ///< Pointer entry type +#define DATA_ENTRY_TYPE_PARTIAL 3 ///< Partial read entry type +///@ + + +/// \name Data entry statuses +///@{ +#define DATA_ENTRY_PENDING 0 ///< Entry not yet used +#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU +#define DATA_ENTRY_BUSY 2 ///< Entry being updated +#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry +#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished +///@} + + + +/// \name Macros for RF register override +///@{ +/// Macro for ADI half-size value-mask combination +#define ADI_VAL_MASK(addr, mask, value) \ +(((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \ + ((((mask) & 0x0F) << 4) | ((value) & 0x0F))) +/// 32-bit write of 16-bit value +#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16)) +/// ADI register, full-size write +#define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \ +(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) +/// 2 ADI registers, full-size write +#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \ +(2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \ +(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) +/// ADI register, half-size read-modify-write +#define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \ +(((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) +/// 2 ADI registers, half-size read-modify-write +#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \ +(2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \ +(ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) + +/// 16-bit SW register as defined in radio_par_def.txt +#define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16)) +/// SW register as defined in radio_par_def.txt with added index (for use with registers > 16 bits). +#define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \ +(((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16)) +/// 8-bit SW register as defined in radio_par_def.txt +#define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \ +((uint32_t)(val) << 16)) +/// Two 8-bit SW registers as defined in radio_par_def.txt; the one given by field and the next byte. +#define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \ + (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24)) +#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \ +((uint32_t)(length) << 16) | (1U << 30)) +#define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \ +((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30)) +#define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \ +((uint32_t)(length) << 16) | (3U << 30)) +#define MCE_RFE_OVERRIDE(bMceRam, mceRomBank, mceMode, bRfeRam, rfeRomBank, rfeMode) \ + (7 | ((!!(bMceRam)) << 8) | (((mceRomBank) & 0x07) << 9) | ((!!(bRfeRam)) << 12) | (((rfeRomBank) & 0x07) << 13) | \ + (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24)) +#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \ + (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \ + (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \ + (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \ + (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \ + (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \ + (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \ + (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \ + (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \ + 0x09) << 4)) // Use illegal value for illegal address range +/// End of string for override register +#define END_OVERRIDE 0xFFFFFFFF + + +/// ADI address-value pair +#define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF)) +#define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value)) + +/// Low half-word +#define LOWORD(value) ((value) & 0xFFFF) +/// High half-word +#define HIWORD(value) ((value) >> 16) +///@} + + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_cmd.h new file mode 100644 index 0000000..1e9280f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_cmd.h @@ -0,0 +1,939 @@ +/****************************************************************************** +* Filename: rf_prop_cmd.h +* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) +* Revision: 18052 +* +* Description: CC13x0 API for Proprietary mode commands +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __PROP_CMD_H +#define __PROP_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup prop_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_carrierSense_s rfc_carrierSense_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_s rfc_CMD_PROP_TX_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_s rfc_CMD_PROP_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s rfc_CMD_PROP_TX_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s rfc_CMD_PROP_RX_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_CS_s rfc_CMD_PROP_CS_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s rfc_CMD_PROP_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s rfc_CMD_PROP_RADIO_DIV_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_SNIFF_s rfc_CMD_PROP_RX_SNIFF_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_SNIFF_s rfc_CMD_PROP_RX_ADV_SNIFF_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s rfc_CMD_PROP_SET_LEN_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s rfc_CMD_PROP_RESTART_RX_t; +typedef struct __RFC_STRUCT rfc_propRxOutput_s rfc_propRxOutput_t; +typedef struct __RFC_STRUCT rfc_propRxStatus_s rfc_propRxStatus_t; + +//! \addtogroup carrierSense +//! @{ +struct __RFC_STRUCT rfc_carrierSense_s { + struct { + uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion + uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct { + uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_TX +//! @{ +#define CMD_PROP_TX 0x3801 +//! Proprietary Mode Transmit Command +struct __RFC_STRUCT rfc_CMD_PROP_TX_s { + uint16_t commandNo; //!< The command ID number 0x3801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t :2; + uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Transmit length as first byte + } pktConf; + uint8_t pktLen; //!< Packet length + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX +//! @{ +#define CMD_PROP_RX 0x3802 +//! Proprietary Mode Receive Command +struct __RFC_STRUCT rfc_CMD_PROP_RX_s { + uint16_t commandNo; //!< The command ID number 0x3802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bChkAddress:1; //!< \brief 0: No address check
+ //!< 1: Check address + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord; //!< Sync word to listen for + uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + uint8_t address0; //!< Address + uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept + //!< 0x00 as well) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_TX_ADV +//! @{ +#define CMD_PROP_TX_ADV 0x3803 +//! Proprietary Mode Advanced Transmit Command +struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s { + uint16_t commandNo; //!< The command ID number 0x3803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t :2; + uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bCrcIncSw:1; //!< \brief 0:Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + } pktConf; + uint8_t numHdrBits; //!< Number of bits in header (0--32) + uint16_t pktLen; //!< Packet length. 0: Unlimited + struct { + uint8_t bExtTxTrig:1; //!< \brief 0: Start packet on a fixed time from the command start trigger
+ //!< 1: Start packet on an external trigger (input event to RAT) + uint8_t inputMode:2; //!< \brief Input mode if external trigger is used for TX start
+ //!< 0: Rising edge
+ //!< 1: Falling edge
+ //!< 2: Both edges
+ //!< 3: Reserved + uint8_t source:5; //!< RAT input event number used for capture if external trigger is used for TX start + } startConf; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } preTrigger; //!< Trigger for transition from preamble to sync word + ratmr_t preTime; //!< \brief Time used together with preTrigger for transition from preamble to sync + //!< word. If preTrigger.triggerType is set to "now", one preamble as + //!< configured in the setup will be sent. Otherwise, the preamble will be repeated until + //!< this trigger is observed. + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet, or TX queue for unlimited length +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX_ADV +//! @{ +#define CMD_PROP_RX_ADV 0x3804 +//! Proprietary Mode Advanced Receive Command +struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s { + uint16_t commandNo; //!< The command ID number 0x3804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bCrcIncSw:1; //!< \brief 0: Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord0; //!< Sync word to listen for + uint32_t syncWord1; //!< Alternative sync word if non-zero + uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + struct { + uint16_t numHdrBits:6; //!< Number of bits in header (0--32) + uint16_t lenPos:5; //!< Position of length field in header (0--31) + uint16_t numLenBits:5; //!< Number of bits in length field (0--16) + } hdrConf; + struct { + uint16_t addrType:1; //!< \brief 0: Address after header
+ //!< 1: Address in header + uint16_t addrSize:5; //!< \brief If addrType = 0: Address size in bytes
+ //!< If addrType = 1: Address size in bits + uint16_t addrPos:5; //!< \brief If addrType = 1: Bit position of address in header
+ //!< If addrType = 0: Non-zero to extend address with sync word identifier + uint16_t numAddr:5; //!< Number of addresses in address list + } addrConf; + int8_t lenOffset; //!< Signed value to add to length field + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + uint8_t* pAddr; //!< Pointer to address list + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_CS +//! @{ +#define CMD_PROP_CS 0x3805 +//! Carrier Sense Command +struct __RFC_STRUCT rfc_CMD_PROP_CS_s { + uint16_t commandNo; //!< The command ID number 0x3805 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOffIdle:1; //!< \brief 0: Keep synth running if command ends with channel Idle
+ //!< 1: Turn off synth if command ends with channel Idle + uint8_t bFsOffBusy:1; //!< \brief 0: Keep synth running if command ends with channel Busy
+ //!< 1: Turn off synth if command ends with channel Busy + } csFsConf; + uint8_t __dummy0; + struct { + uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion + uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct { + uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RADIO_SETUP +//! @{ +#define CMD_PROP_RADIO_SETUP 0x3806 +//! Proprietary Mode Radio Setup Command for 2.4 GHz (CC1350 Only) +struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x3806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t modType:3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< Others: Reserved + uint16_t deviation:13; //!< Deviation (250 Hz steps) + } modulation; + struct { + uint32_t preScale:4; //!< Prescaler value + uint32_t :4; + uint32_t rateWord:21; //!< Rate word + uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct { + uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct { + uint16_t nSwBits:6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode:4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 8: Long range mode
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t :1; + uint16_t whitenMode:3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RADIO_DIV_SETUP +//! @{ +#define CMD_PROP_RADIO_DIV_SETUP 0x3807 +//! Proprietary Mode Radio Setup Command for All Frequency Bands +struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x3807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t modType:3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< Others: Reserved + uint16_t deviation:13; //!< Deviation (250 Hz steps) + } modulation; + struct { + uint32_t preScale:4; //!< Prescaler value + uint32_t :4; + uint32_t rateWord:21; //!< Rate word + uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct { + uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct { + uint16_t nSwBits:6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode:4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 8: Long range mode
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t :1; + uint16_t whitenMode:3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters. + //!< For a single channel RF system, this should be set equal to the RF frequency used. + //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal + //!< to the center frequency of the frequency band used. + int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same + //!< intermediate frequency if supported, otherwise 0.
+ //!< 0x8000: Use default. + uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 2 (CC1350 only), 5, 6, 10, 12, 15, and 30 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX_SNIFF +//! @{ +#define CMD_PROP_RX_SNIFF 0x3808 +//! Proprietary Mode Receive Command with Sniff Mode +struct __RFC_STRUCT rfc_CMD_PROP_RX_SNIFF_s { + uint16_t commandNo; //!< The command ID number 0x3808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bChkAddress:1; //!< \brief 0: No address check
+ //!< 1: Check address + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord; //!< Sync word to listen for + uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + uint8_t address0; //!< Address + uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept + //!< 0x00 as well) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure + struct { + uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion + uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct { + uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX_ADV_SNIFF +//! @{ +#define CMD_PROP_RX_ADV_SNIFF 0x3809 +//! Proprietary Mode Advanced Receive Command with Sniff Mode +struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_SNIFF_s { + uint16_t commandNo; //!< The command ID number 0x3809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bCrcIncSw:1; //!< \brief 0: Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord0; //!< Sync word to listen for + uint32_t syncWord1; //!< Alternative sync word if non-zero + uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + struct { + uint16_t numHdrBits:6; //!< Number of bits in header (0--32) + uint16_t lenPos:5; //!< Position of length field in header (0--31) + uint16_t numLenBits:5; //!< Number of bits in length field (0--16) + } hdrConf; + struct { + uint16_t addrType:1; //!< \brief 0: Address after header
+ //!< 1: Address in header + uint16_t addrSize:5; //!< \brief If addrType = 0: Address size in bytes
+ //!< If addrType = 1: Address size in bits + uint16_t addrPos:5; //!< \brief If addrType = 1: Bit position of address in header
+ //!< If addrType = 0: Non-zero to extend address with sync word identifier + uint16_t numAddr:5; //!< Number of addresses in address list + } addrConf; + int8_t lenOffset; //!< Signed value to add to length field + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + uint8_t* pAddr; //!< Pointer to address list + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure + struct { + uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion + uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct { + uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_SET_LEN +//! @{ +#define CMD_PROP_SET_LEN 0x3401 +//! Set Packet Length Command +struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s { + uint16_t commandNo; //!< The command ID number 0x3401 + uint16_t rxLen; //!< Payload length to use +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RESTART_RX +//! @{ +#define CMD_PROP_RESTART_RX 0x3402 +//! Restart Packet Command +struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s { + uint16_t commandNo; //!< The command ID number 0x3402 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup propRxOutput +//! @{ +//! Output structure for RX operations + +struct __RFC_STRUCT rfc_propRxOutput_s { + uint16_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint16_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< Number of packets that have been received with CRC OK and ignored due to address mismatch + uint8_t nRxStopped; //!< Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1 + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + ratmr_t timeStamp; //!< Time stamp of last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup propRxStatus +//! @{ +//! Receive status byte that may be appended to message in receive buffer + +struct __RFC_STRUCT rfc_propRxStatus_s { + struct { + uint8_t addressInd:5; //!< Index of address found (0 if not applicable) + uint8_t syncWordId:1; //!< 0 for primary sync word, 1 for alternate sync word + uint8_t result:2; //!< \brief 0: Packet received correctly, not ignored
+ //!< 1: Packet received with CRC error
+ //!< 2: Packet received correctly, but can be ignored
+ //!< 3: Packet reception was aborted + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_mailbox.h new file mode 100644 index 0000000..7eb264b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_mailbox.h @@ -0,0 +1,71 @@ +/****************************************************************************** +* Filename: rf_prop_mailbox.h +* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) +* Revision: 18032 +* +* Description: Definitions for proprietary mode radio interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _PROP_MAILBOX_H +#define _PROP_MAILBOX_H + +/// \name Radio operation status +///@{ +/// \name Operation finished normally +///@{ +#define PROP_DONE_OK 0x3400 ///< Operation ended normally +#define PROP_DONE_RXTIMEOUT 0x3401 ///< Operation stopped after end trigger while waiting for sync +#define PROP_DONE_BREAK 0x3402 ///< Rx stopped due to timeout in the middle of a packet +#define PROP_DONE_ENDED 0x3403 ///< Operation stopped after end trigger during reception +#define PROP_DONE_STOPPED 0x3404 ///< Operation stopped after stop command +#define PROP_DONE_ABORT 0x3405 ///< Operation aborted by abort command +#define PROP_DONE_RXERR 0x3406 ///< Operation ended after receiving packet with CRC error +#define PROP_DONE_IDLE 0x3407 ///< Carrier sense operation ended because of idle channel +#define PROP_DONE_BUSY 0x3408 ///< Carrier sense operation ended because of busy channel +#define PROP_DONE_IDLETIMEOUT 0x3409 ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 1 +#define PROP_DONE_BUSYTIMEOUT 0x340A ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 0 + +///@} +/// \name Operation finished with error +///@{ +#define PROP_ERROR_PAR 0x3800 ///< Illegal parameter +#define PROP_ERROR_RXBUF 0x3801 ///< No available Rx buffer at the start of a packet +#define PROP_ERROR_RXFULL 0x3802 ///< Out of Rx buffer during reception in a partial read buffer +#define PROP_ERROR_NO_SETUP 0x3803 ///< Radio was not set up in proprietary mode +#define PROP_ERROR_NO_FS 0x3804 ///< Synth was not programmed when running Rx or Tx +#define PROP_ERROR_RXOVF 0x3805 ///< Rx overflow observed during operation +#define PROP_ERROR_TXUNF 0x3806 ///< Tx underflow observed during operation +///@} +///@} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rfc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rfc.c new file mode 100644 index 0000000..4c0258f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rfc.c @@ -0,0 +1,535 @@ +/****************************************************************************** +* Filename: rfc.c +* Revised: 2018-08-08 11:04:37 +0200 (Wed, 08 Aug 2018) +* Revision: 52334 +* +* Description: Driver for the RF Core. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "rfc.h" +#include "rf_mailbox.h" +#include + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef RFCCpeIntGetAndClear + #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear + #undef RFCDoorbellSendTo + #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo + #undef RFCSynthPowerDown + #define RFCSynthPowerDown NOROM_RFCSynthPowerDown + #undef RFCCpePatchReset + #define RFCCpePatchReset NOROM_RFCCpePatchReset + #undef RFCOverrideSearch + #define RFCOverrideSearch NOROM_RFCOverrideSearch + #undef RFCOverrideUpdate + #define RFCOverrideUpdate NOROM_RFCOverrideUpdate + #undef RFCHwIntGetAndClear + #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #undef RFCRfTrimRead + #define RFCRfTrimRead NOROM_RFCRfTrimRead + #undef RFCRfTrimSet + #define RFCRfTrimSet NOROM_RFCRfTrimSet + #undef RFCRTrim + #define RFCRTrim NOROM_RFCRTrim + #undef RFCAdi3VcoLdoVoltageMode + #define RFCAdi3VcoLdoVoltageMode NOROM_RFCAdi3VcoLdoVoltageMode +#endif + +// Definition of addresses and offsets +#define _CPERAM_START 0x21000000 +#define _PARSER_PATCH_TAB_OFFSET 0x0338 +#define _PATCH_TAB_OFFSET 0x0340 +#define _IRQPATCH_OFFSET 0x03BC +#define _PATCH_VEC_OFFSET 0x041C + +#define RFC_RTRIM_PATTERN 0x4038 +#define RFC_RTRIM_MASK 0xFFFF + +// Default interrupt table +static const uint16_t rfc_defaultIrqAddr[] = +{ + 0x3bc3, + 0x3a3d, + 0x3a5d, + 0x3a71, + 0x0aa1, + 0x3a8f, + 0x3b0f, + 0x09b3, + 0x5e49, + 0x0a85, + 0x3b2f, + 0x3b85, +}; + +//***************************************************************************** +// +// Get and clear CPE interrupt flags which match the provided bitmask +// +//***************************************************************************** +uint32_t +RFCCpeIntGetAndClear(uint32_t ui32Mask) +{ + // Read the CPE interrupt flags which match the provided bitmask + uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask; + + // Clear the interrupt flags + RFCCpeIntClear(ui32Ifg); + + // Return with the interrupt flags + return (ui32Ifg); +} + + +//***************************************************************************** +// +// Send a radio operation to the doorbell and wait for an acknowledgement +// +//***************************************************************************** +uint32_t +RFCDoorbellSendTo(uint32_t pOp) +{ + // Wait until the doorbell becomes available + while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) != 0); + RFCAckIntClear(); + + // Submit the command to the CM0 through the doorbell + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) = pOp; + + // Wait until the CM0 starts to parse the command + while(!HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG)); + RFCAckIntClear(); + + // Return with the content of status register + return(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDSTA)); +} + + +//***************************************************************************** +// +// Turn off the RF synthesizer. The radio will no longer respond to commands! +// +//***************************************************************************** +void +RFCSynthPowerDown(void) +{ + // Definition of reserved words + const uint32_t RFC_RESERVED0 = 0x40044108; + const uint32_t RFC_RESERVED1 = 0x40044114; + const uint32_t RFC_RESERVED2 = 0x4004410C; + const uint32_t RFC_RESERVED3 = 0x40044100; + + // Disable CPE clock, enable FSCA clock. + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = (HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) + & ~RFC_PWR_PWMCLKEN_CPE_M) | RFC_PWR_PWMCLKEN_FSCA_M; + + HWREG(RFC_RESERVED0) = 3; + HWREG(RFC_RESERVED1) = 0x1030; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED1) = 0x50; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED1) = 0x650; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED3) = 1; + +} + + +//***************************************************************************** +// +// Reset previously patched CPE RAM to a state where it can be patched again +// +//***************************************************************************** +void +RFCCpePatchReset(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_CPERAM_START + _PARSER_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *)(_CPERAM_START + _IRQPATCH_OFFSET); + + memset(pPatchTab, 0xFF, _IRQPATCH_OFFSET - _PARSER_PATCH_TAB_OFFSET); + + int i; + for (i = 0; i < sizeof(rfc_defaultIrqAddr)/sizeof(rfc_defaultIrqAddr[0]); i++) + { + pIrqPatch[i * 2 + 1] = rfc_defaultIrqAddr[i]; + } +} + + +//***************************************************************************** +// +// Function to search an override list for the provided pattern within the search depth. +// +//***************************************************************************** +uint8_t +RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth) +{ + // Search from start of the override list, to look for first override entry that matches search pattern + uint8_t override_index; + for(override_index = 0; (override_index < searchDepth) && (pOverride[override_index] != END_OVERRIDE); override_index++) + { + // Compare the value to the given pattern + if((pOverride[override_index] & mask) == pattern) + { + // Return with the index of override in case of match + return override_index; + } + } + + // Return with an invalid index + return 0xFF; +} + +//***************************************************************************** +// +// Update the override list based on values stored in FCFG1 +// +//***************************************************************************** +uint8_t +RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams) +{ + /* Handle RTrim values. */ + return RFCRTrim(pOpSetup); + +} + + +//***************************************************************************** +// +// Get and clear HW interrupt flags +// +//***************************************************************************** +uint32_t +RFCHwIntGetAndClear(uint32_t ui32Mask) +{ + // Read the CPE interrupt flags which match the provided bitmask + uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) & ui32Mask; + + // Clear the interupt flags + RFCHwIntClear(ui32Ifg); + + // Return with the interrupt flags + return (ui32Ifg); +} + + +//***************************************************************************** +// +// Read RF trim values from FCFG1 +// +//***************************************************************************** +void +RFCRfTrimRead(rfc_radioOp_t *pOpSetup, rfTrim_t* pRfTrim) +{ + // Definition of position and bitmask of divider value + const uint32_t CONFIG_MISC_ADC_DIVIDER = 27; + const uint32_t CONFIG_MISC_ADC_DIVIDER_BM = 0xF8000000U; + + // Local variable + int32_t divider; + + // Based on the type of setup command, decode the divider value + switch (pOpSetup->commandNo) + { + case CMD_RADIO_SETUP: // Use the loDivider value + divider = ((rfc_CMD_RADIO_SETUP_t *)pOpSetup)->loDivider; + break; + case CMD_PROP_RADIO_DIV_SETUP: // Use the loDivider value + divider = ((rfc_CMD_PROP_RADIO_DIV_SETUP_t *)pOpSetup)->loDivider; + break; + default: // Use 2.4 GHz by default + divider = 0; + break; + } + + // Read trim values from FCFG1 + pRfTrim->configIfAdc = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_IF_ADC); + switch (divider) + { + case 5: + pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV5); + pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV5); + pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV5) + & ~CONFIG_MISC_ADC_DIVIDER_BM) | (5U << CONFIG_MISC_ADC_DIVIDER); + break; + + case 6: + pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV6); + pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV6); + pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV6) + & ~CONFIG_MISC_ADC_DIVIDER_BM) | (6U << CONFIG_MISC_ADC_DIVIDER); + break; + + case 10: + pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV10); + pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV10); + pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV10) + & ~CONFIG_MISC_ADC_DIVIDER_BM) | (10U << CONFIG_MISC_ADC_DIVIDER); + break; + + case 12: + pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV12); + pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV12); + pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV12) + & ~CONFIG_MISC_ADC_DIVIDER_BM) | (12U << CONFIG_MISC_ADC_DIVIDER); + break; + + case 15: + pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV15); + pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV15); + pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV15) + & ~CONFIG_MISC_ADC_DIVIDER_BM) | (15U << CONFIG_MISC_ADC_DIVIDER); + break; + + case 30: + pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV30); + pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV30); + pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV30) + & ~CONFIG_MISC_ADC_DIVIDER_BM) | (30U << CONFIG_MISC_ADC_DIVIDER); + break; + + default: + pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND); + pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH); + // Make sure configMiscAdc is not 0 by setting an unused bit to 1 + pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC) + & ~CONFIG_MISC_ADC_DIVIDER_BM) | (2U << CONFIG_MISC_ADC_DIVIDER); + break; + } +} + + +//***************************************************************************** +// +// Write preloaded RF trim values to the CM0 +// +//***************************************************************************** +void +RFCRfTrimSet(rfTrim_t* pRfTrim) +{ + memcpy((void*)&HWREG(0x21000018), (void*)pRfTrim, sizeof(rfTrim_t)); +} + + +//***************************************************************************** +// +// Check Override RTrim vs FCFG RTrim +// +//***************************************************************************** +uint8_t +RFCRTrim(rfc_radioOp_t *pOpSetup) +{ + int32_t divider; + uint32_t fcfg1_rtrim; + uint32_t *pOverride; + int32_t override_index; + uint32_t override_value; + uint32_t override_rtrim = 0; + + // Based on the type of setup command, decode the divider and overrides + switch (pOpSetup->commandNo) + { + case CMD_RADIO_SETUP: + divider = ((rfc_CMD_RADIO_SETUP_t *)pOpSetup)->loDivider; + pOverride = ((rfc_CMD_RADIO_SETUP_t *)pOpSetup)->pRegOverride; + break; + case CMD_PROP_RADIO_SETUP: + divider = 2; + pOverride = ((rfc_CMD_PROP_RADIO_SETUP_t *)pOpSetup)->pRegOverride; + break; + case CMD_PROP_RADIO_DIV_SETUP: + divider = ((rfc_CMD_PROP_RADIO_DIV_SETUP_t *)pOpSetup)->loDivider; + pOverride = ((rfc_CMD_PROP_RADIO_DIV_SETUP_t *)pOpSetup)->pRegOverride; + break; + default: + return 1; + } + + if (pOverride == 0) + { + // There is no override list provided + return 1; + } + + // Search for an RTRIM value within the override list. + override_index = RFCOverrideSearch(pOverride, RFC_RTRIM_PATTERN, RFC_RTRIM_MASK, RFC_MAX_SEARCH_DEPTH); + + // If we found it, decode the value. + if(override_index < RFC_MAX_SEARCH_DEPTH) + { + override_value = pOverride[override_index]; + override_rtrim = (override_value & 0xF0000) >> 16; + } + else + { + // There is no RTRIM value within the first items of the override list + return 1; + } + + // Read trim from FCFG1 + switch (divider) + { + case 2: + fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC) + & FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_S; + break; + case 5: + // Legacy value + fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_MISC_OTP_DATA) + & FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_M) >> FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_S; + break; + case 6: + fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV6) + & FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_S; + break; + case 10: + fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV10) + & FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_S; + break; + case 12: + fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV12) + & FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_S; + break; + case 15: + fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV15) + & FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_S; + break; + case 30: + fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV30) + & FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_S; + break; + default: + fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC) + & FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_S; + break; + } + + // Check for value matching early device samples + if(fcfg1_rtrim == 0xF) + { + // Set to default value + switch (divider) + { + case 5: + case 10: + case 15: + case 30: + pOverride[override_index] = (override_value & 0xFFF0FFFF) | (0x7 << 16); + break; + case 2: + case 6: + case 12: + default: + pOverride[override_index] = (override_value & 0xFFF0FFFF) | (0x4 << 16); + break; + } + } + else + { + // Test Override vs FCFG1 limit. + if(override_rtrim >= fcfg1_rtrim) + { + ; // Do nothing + } + else + { + // Set override to FCFG1 limit value + pOverride[override_index] = (override_value & 0xFFF0FFFF) | (fcfg1_rtrim << 16); + } + } + + return 0; +} + + +//***************************************************************************** +// +// Function to set VCOLDO reference to voltage mode +// +//***************************************************************************** +void +RFCAdi3VcoLdoVoltageMode(bool bEnable) +{ + if (bEnable) + { + // First make sure the REFSYSCTL0 mux output is not further muxed out + HWREGB(0x40086200) = 0x0; + + // Set the REFSYSCTL0 mux as desired for VCOLDO voltage mode + HWREGB(ADI3_BASE + ADI_O_DIR + ADI_3_REFSYS_O_REFSYSCTL0) = ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V; + } + else + { + // Revert the mux override + HWREGB(ADI3_BASE + ADI_O_DIR + ADI_3_REFSYS_O_REFSYSCTL0) = ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC; + } +} + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef RFCCpeIntGetAndClear + #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear + #undef RFCDoorbellSendTo + #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo + #undef RFCSynthPowerDown + #define RFCSynthPowerDown NOROM_RFCSynthPowerDown + #undef RFCCpePatchReset + #define RFCCpePatchReset NOROM_RFCCpePatchReset + #undef RFCOverrideSearch + #define RFCOverrideSearch NOROM_RFCOverrideSearch + #undef RFCOverrideUpdate + #define RFCOverrideUpdate NOROM_RFCOverrideUpdate + #undef RFCHwIntGetAndClear + #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #undef RFCRfTrimRead + #define RFCRfTrimRead NOROM_RFCRfTrimRead + #undef RFCRfTrimSet + #define RFCRfTrimSet NOROM_RFCRfTrimSet + #undef RFCRTrim + #define RFCRTrim NOROM_RFCRTrim + #undef RFCAdi3VcoLdoVoltageMode + #define RFCAdi3VcoLdoVoltageMode NOROM_RFCAdi3VcoLdoVoltageMode +#endif + +// See rfc.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rfc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rfc.h new file mode 100644 index 0000000..6ad3a44 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rfc.h @@ -0,0 +1,483 @@ +/****************************************************************************** +* Filename: rfc.h +* Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018) +* Revision: 52338 +* +* Description: Defines and prototypes for the RF Core. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup rfc_api +//! @{ +// +//***************************************************************************** + +#ifndef __RFC_H__ +#define __RFC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_rfc_pwr.h" +#include "../inc/hw_rfc_dbell.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_adi.h" +#include "rf_common_cmd.h" +#include "rf_prop_cmd.h" +#include "rf_ble_cmd.h" + +// Definition of RFTRIM container +typedef struct { + uint32_t configIfAdc; + uint32_t configRfFrontend; + uint32_t configSynth; + uint32_t configMiscAdc; +} rfTrim_t; + +// Definition of maximum search depth used by the RFCOverrideUpdate function +#define RFC_MAX_SEARCH_DEPTH 5 + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear + #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo + #define RFCSynthPowerDown NOROM_RFCSynthPowerDown + #define RFCCpePatchReset NOROM_RFCCpePatchReset + #define RFCOverrideSearch NOROM_RFCOverrideSearch + #define RFCOverrideUpdate NOROM_RFCOverrideUpdate + #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #define RFCRfTrimRead NOROM_RFCRfTrimRead + #define RFCRfTrimSet NOROM_RFCRfTrimSet + #define RFCRTrim NOROM_RFCRTrim + #define RFCAdi3VcoLdoVoltageMode NOROM_RFCAdi3VcoLdoVoltageMode +#endif + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enable the RF core clocks. +//! +//! As soon as the RF core is started it will handle clock control +//! autonomously. No check should be performed to check the clocks. Instead +//! the radio can be ping'ed through the command interface. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +RFCClockEnable(void) +{ + // Enable basic clocks to get the CPE run + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM + | RFC_PWR_PWMCLKEN_CPE + | RFC_PWR_PWMCLKEN_RFC; +} + + +//***************************************************************************** +// +//! \brief Disable the RF core clocks. +//! +//! As soon as the RF core is started it will handle clock control +//! autonomously. No check should be performed to check the clocks. Instead +//! the radio can be ping'ed through the command interface. +//! +//! When disabling clocks it is the programmers responsibility that the +//! RF core clocks are safely gated. I.e. the RF core should be safely +//! 'parked'. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +RFCClockDisable(void) +{ + // Disable all clocks + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x0; +} + + +//***************************************************************************** +// +//! Clear HW interrupt flags +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpeIntClear(uint32_t ui32Mask) +{ + // Clear the masked pending interrupts. + do + { + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = ~ui32Mask; + }while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask); +} + + +//***************************************************************************** +// +//! Clear CPE interrupt flags. +// +//***************************************************************************** +__STATIC_INLINE void +RFCHwIntClear(uint32_t ui32Mask) +{ + // Clear the masked pending interrupts. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = ~ui32Mask; +} + + +//***************************************************************************** +// +//! Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector). +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe0IntSelect(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE0 IRQ. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) &= ~ui32Mask; +} + + +//***************************************************************************** +// +//! Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector). +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe1IntSelect(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE1 IRQ. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) |= ui32Mask; +} + + +//***************************************************************************** +// +//! Enable CPEx interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpeIntEnable(uint32_t ui32Mask) +{ + // Enable CPE interrupts from RF Core. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask; +} + + +//***************************************************************************** +// +//! Select, clear, and enable interrupt sources to CPE0. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe0IntSelectClearEnable(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE0 IRQ. + RFCCpe0IntSelect(ui32Mask); + + // Clear the masked interrupts. + RFCCpeIntClear(ui32Mask); + + // Enable the masked interrupts. + RFCCpeIntEnable(ui32Mask); +} + + +//***************************************************************************** +// +//! Select, clear, and enable interrupt sources to CPE1. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe1IntSelectClearEnable(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE1 IRQ. + RFCCpe1IntSelect(ui32Mask); + + // Clear the masked interrupts. + RFCCpeIntClear(ui32Mask); + + // Enable the masked interrupts. + RFCCpeIntEnable(ui32Mask); +} + + +//***************************************************************************** +// +//! Enable HW interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCHwIntEnable(uint32_t ui32Mask) +{ + // Enable the masked interrupts + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) |= ui32Mask; +} + + +//***************************************************************************** +// +//! Disable CPE interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpeIntDisable(uint32_t ui32Mask) +{ + // Disable the masked interrupts + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) &= ~ui32Mask; +} + + +//***************************************************************************** +// +//! Disable HW interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCHwIntDisable(uint32_t ui32Mask) +{ + // Disable the masked interrupts + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) &= ~ui32Mask; +} + + +//***************************************************************************** +// +//! Get and clear CPE interrupt flags. +// +//***************************************************************************** +extern uint32_t RFCCpeIntGetAndClear(uint32_t ui32Mask); + + +//***************************************************************************** +// +//! Clear ACK interrupt flag. +// +//***************************************************************************** +__STATIC_INLINE void +RFCAckIntClear(void) +{ + // Clear any pending interrupts. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0x0; +} + + +//***************************************************************************** +// +//! Send a radio operation to the doorbell and wait for an acknowledgment. +// +//***************************************************************************** +extern uint32_t RFCDoorbellSendTo(uint32_t pOp); + + +//***************************************************************************** +// +//! This function implements a fast way to turn off the synthesizer. +// +//***************************************************************************** +extern void RFCSynthPowerDown(void); + + +//***************************************************************************** +// +//! Reset previously patched CPE RAM to a state where it can be patched again. +// +//***************************************************************************** +extern void RFCCpePatchReset(void); + + +//***************************************************************************** +// +// Function to search an override list for the provided pattern within the search depth. +// +//***************************************************************************** +extern uint8_t RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth); + + +//***************************************************************************** +// +//! Function to update override list +// +//***************************************************************************** +extern uint8_t RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams); + + +//***************************************************************************** +// +//! Get and clear HW interrupt flags. +// +//***************************************************************************** +extern uint32_t RFCHwIntGetAndClear(uint32_t ui32Mask); + + +//***************************************************************************** +// +//! Get the type of currently selected PA. +// +//***************************************************************************** + + +//***************************************************************************** +// +//! Read RF trim from flash using CM3. +// +//***************************************************************************** +extern void RFCRfTrimRead(rfc_radioOp_t *pOpSetup, rfTrim_t* rfTrim); + + +//***************************************************************************** +// +//! Write preloaded RF trim values directly into CPE. +// +//***************************************************************************** +extern void RFCRfTrimSet(rfTrim_t* rfTrim); + + +//***************************************************************************** +// +//! Check Override RTrim vs FCFG RTrim. +// +//***************************************************************************** +extern uint8_t RFCRTrim(rfc_radioOp_t *pOpSetup); + + +//***************************************************************************** +// +//! Function to set VCOLDO reference to voltage mode. +// +//***************************************************************************** +extern void RFCAdi3VcoLdoVoltageMode(bool bEnable); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_RFCCpeIntGetAndClear + #undef RFCCpeIntGetAndClear + #define RFCCpeIntGetAndClear ROM_RFCCpeIntGetAndClear + #endif + #ifdef ROM_RFCDoorbellSendTo + #undef RFCDoorbellSendTo + #define RFCDoorbellSendTo ROM_RFCDoorbellSendTo + #endif + #ifdef ROM_RFCSynthPowerDown + #undef RFCSynthPowerDown + #define RFCSynthPowerDown ROM_RFCSynthPowerDown + #endif + #ifdef ROM_RFCCpePatchReset + #undef RFCCpePatchReset + #define RFCCpePatchReset ROM_RFCCpePatchReset + #endif + #ifdef ROM_RFCOverrideSearch + #undef RFCOverrideSearch + #define RFCOverrideSearch ROM_RFCOverrideSearch + #endif + #ifdef ROM_RFCOverrideUpdate + #undef RFCOverrideUpdate + #define RFCOverrideUpdate ROM_RFCOverrideUpdate + #endif + #ifdef ROM_RFCHwIntGetAndClear + #undef RFCHwIntGetAndClear + #define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear + #endif + #ifdef ROM_RFCRfTrimRead + #undef RFCRfTrimRead + #define RFCRfTrimRead ROM_RFCRfTrimRead + #endif + #ifdef ROM_RFCRfTrimSet + #undef RFCRfTrimSet + #define RFCRfTrimSet ROM_RFCRfTrimSet + #endif + #ifdef ROM_RFCRTrim + #undef RFCRTrim + #define RFCRTrim ROM_RFCRTrim + #endif + #ifdef ROM_RFCAdi3VcoLdoVoltageMode + #undef RFCAdi3VcoLdoVoltageMode + #define RFCAdi3VcoLdoVoltageMode ROM_RFCAdi3VcoLdoVoltageMode + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __RFC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom.h new file mode 100644 index 0000000..5206bd5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom.h @@ -0,0 +1,705 @@ +/****************************************************************************** +* Filename: rom.h +* Revised: 2018-11-02 13:54:49 +0100 (Fri, 02 Nov 2018) +* Revision: 53196 +* +* Description: Prototypes for the ROM utility functions. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ROM_H__ +#define __ROM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "../inc/hw_types.h" + +#ifndef __HAPI_H__ +#define __HAPI_H__ + +// Start address of the ROM hard API access table (located after the ROM FW rev field) +#define ROM_HAPI_TABLE_ADDR 0x10000048 + +// ROM Hard-API function interface types +typedef uint32_t (* FPTR_CRC32_T) ( uint8_t* /* pui8Data */,\ + uint32_t /* ui32ByteCount */,\ + uint32_t /* ui32RepeatCount */); + +typedef uint32_t (* FPTR_GETFLSIZE_T) ( void ); + +typedef uint32_t (* FPTR_GETCHIPID_T) ( void ); + +typedef uint32_t (* FPTR_RESERVED1_T) ( uint32_t ); + +typedef uint32_t (* FPTR_RESERVED2_T) ( void ); + +typedef uint32_t (* FPTR_RESERVED3_T) ( uint8_t* ,\ + uint32_t ,\ + uint32_t ); +typedef void (* FPTR_RESETDEV_T) ( void ); + +typedef uint32_t (* FPTR_FLETCHER32_T) ( uint16_t* /* pui16Data */,\ + uint16_t /* ui16WordCount */,\ + uint16_t /* ui16RepeatCount */); + +typedef uint32_t (* FPTR_MINVAL_T) ( uint32_t* /* ulpDataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef uint32_t (* FPTR_MAXVAL_T) ( uint32_t* /* pui32DataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef uint32_t (* FPTR_MEANVAL_T) ( uint32_t* /* pui32DataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef uint32_t (* FPTR_STDDVAL_T) ( uint32_t* /* pui32DataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef void (* FPTR_HFSOURCESAFESWITCH_T) ( void ); + +typedef void (* FPTR_RESERVED4_T) ( uint32_t ); + +typedef void (* FPTR_RESERVED5_T) ( uint32_t ); + +typedef void (* FPTR_COMPAIN_T) ( uint8_t /* ut8Signal */); + +typedef void (* FPTR_COMPAREF_T) ( uint8_t /* ut8Signal */); + +typedef void (* FPTR_ADCCOMPBIN_T) ( uint8_t /* ut8Signal */); + +typedef void (* FPTR_COMPBREF_T) ( uint8_t /* ut8Signal */); + +extern uint32_t MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer, + uint32_t ui32Address, + uint32_t ui32Count); + +extern uint32_t MemBusWrkAroundHapiEraseSector(uint32_t ui32Address); + +// ROM Hard-API access table type +typedef struct +{ + FPTR_CRC32_T Crc32; + FPTR_GETFLSIZE_T FlashGetSize; + FPTR_GETCHIPID_T GetChipId; + FPTR_RESERVED1_T ReservedLocation1; + FPTR_RESERVED2_T ReservedLocation2; + FPTR_RESERVED3_T ReservedLocation3; + FPTR_RESETDEV_T ResetDevice; + FPTR_FLETCHER32_T Fletcher32; + FPTR_MINVAL_T MinValue; + FPTR_MAXVAL_T MaxValue; + FPTR_MEANVAL_T MeanValue; + FPTR_STDDVAL_T StandDeviationValue; + FPTR_RESERVED4_T ReservedLocation4; + FPTR_RESERVED5_T ReservedLocation5; + FPTR_HFSOURCESAFESWITCH_T HFSourceSafeSwitch; + FPTR_COMPAIN_T SelectCompAInput; + FPTR_COMPAREF_T SelectCompARef; + FPTR_ADCCOMPBIN_T SelectADCCompBInput; + FPTR_COMPBREF_T SelectCompBRef; +} HARD_API_T; + +// Pointer to the ROM HAPI table +#define P_HARD_API ((HARD_API_T*) ROM_HAPI_TABLE_ADDR) + +// Add wrapper around the Hapi functions needing the "bus arbitration issue" workaround +extern void SafeHapiVoid( FPTR_VOID_VOID_T fPtr ); +extern void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ); + +#define HapiCrc32(a,b,c) P_HARD_API->Crc32(a,b,c) +#define HapiGetFlashSize() P_HARD_API->FlashGetSize() +#define HapiGetChipId() P_HARD_API->GetChipId() +#define HapiSectorErase(a) MemBusWrkAroundHapiEraseSector(a) +#define HapiProgramFlash(a,b,c) MemBusWrkAroundHapiProgramFlash(a,b,c) +#define HapiResetDevice() P_HARD_API->ResetDevice() +#define HapiFletcher32(a,b,c) P_HARD_API->Fletcher32(a,b,c) +#define HapiMinValue(a,b) P_HARD_API->MinValue(a,b) +#define HapiMaxValue(a,b) P_HARD_API->MaxValue(a,b) +#define HapiMeanValue(a,b) P_HARD_API->MeanValue(a,b) +#define HapiStandDeviationValue(a,b) P_HARD_API->StandDeviationValue(a,b) +#define HapiHFSourceSafeSwitch() SafeHapiVoid( P_HARD_API->HFSourceSafeSwitch ) +#define HapiSelectCompAInput(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectCompAInput , a ) +#define HapiSelectCompARef(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectCompARef , a ) +#define HapiSelectADCCompBInput(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectADCCompBInput, a ) +#define HapiSelectCompBRef(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectCompBRef , a ) + +// Defines for input parameter to the HapiSelectCompAInput function. +#define COMPA_IN_NC 0x00 +// Defines used in CC13x0/CC26x0 devices +#define COMPA_IN_AUXIO7 0x09 +#define COMPA_IN_AUXIO6 0x0A +#define COMPA_IN_AUXIO5 0x0B +#define COMPA_IN_AUXIO4 0x0C +#define COMPA_IN_AUXIO3 0x0D +#define COMPA_IN_AUXIO2 0x0E +#define COMPA_IN_AUXIO1 0x0F +#define COMPA_IN_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7 +#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6 +#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5 +#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4 +#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3 +#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2 +#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1 +#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0 + +// Defines for input parameter to the HapiSelectCompARef function. +#define COMPA_REF_NC 0x00 +#define COMPA_REF_DCOUPL 0x01 +#define COMPA_REF_VSS 0x02 +#define COMPA_REF_VDDS 0x03 +#define COMPA_REF_ADCVREFP 0x04 +// Defines used in CC13x0/CC26x0 devices +#define COMPA_REF_AUXIO7 0x09 +#define COMPA_REF_AUXIO6 0x0A +#define COMPA_REF_AUXIO5 0x0B +#define COMPA_REF_AUXIO4 0x0C +#define COMPA_REF_AUXIO3 0x0D +#define COMPA_REF_AUXIO2 0x0E +#define COMPA_REF_AUXIO1 0x0F +#define COMPA_REF_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7 +#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6 +#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5 +#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4 +#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3 +#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2 +#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1 +#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0 + +// Defines for input parameter to the HapiSelectADCCompBInput function. +#define ADC_COMPB_IN_NC 0x00 +#define ADC_COMPB_IN_DCOUPL 0x03 +#define ADC_COMPB_IN_VSS 0x04 +#define ADC_COMPB_IN_VDDS 0x05 +// Defines used in CC13x0/CC26x0 devices +#define ADC_COMPB_IN_AUXIO7 0x09 +#define ADC_COMPB_IN_AUXIO6 0x0A +#define ADC_COMPB_IN_AUXIO5 0x0B +#define ADC_COMPB_IN_AUXIO4 0x0C +#define ADC_COMPB_IN_AUXIO3 0x0D +#define ADC_COMPB_IN_AUXIO2 0x0E +#define ADC_COMPB_IN_AUXIO1 0x0F +#define ADC_COMPB_IN_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7 +#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6 +#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5 +#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4 +#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3 +#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2 +#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1 +#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0 + +// Defines for input parameter to the HapiSelectCompBRef function. +// The define values can not be changed! +#define COMPB_REF_NC 0x00 +#define COMPB_REF_DCOUPL 0x01 +#define COMPB_REF_VSS 0x02 +#define COMPB_REF_VDDS 0x03 + +#endif // __HAPI_H__ + +//***************************************************************************** +// +// Pointers to the main API tables. +// +//***************************************************************************** +#define ROM_API_TABLE ((uint32_t *) 0x10000180) +#define ROM_VERSION (ROM_API_TABLE[0]) + + +#define ROM_API_AON_EVENT_TABLE ((uint32_t*) (ROM_API_TABLE[1])) +#define ROM_API_AON_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[2])) +#define ROM_API_AON_RTC_TABLE ((uint32_t*) (ROM_API_TABLE[3])) +#define ROM_API_AON_WUC_TABLE ((uint32_t*) (ROM_API_TABLE[4])) +#define ROM_API_AUX_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[5])) +#define ROM_API_AUX_TDC_TABLE ((uint32_t*) (ROM_API_TABLE[6])) +#define ROM_API_AUX_TIMER_TABLE ((uint32_t*) (ROM_API_TABLE[7])) +#define ROM_API_AUX_WUC_TABLE ((uint32_t*) (ROM_API_TABLE[8])) +#define ROM_API_DDI_TABLE ((uint32_t*) (ROM_API_TABLE[9])) +#define ROM_API_FLASH_TABLE ((uint32_t*) (ROM_API_TABLE[10])) +#define ROM_API_I2C_TABLE ((uint32_t*) (ROM_API_TABLE[11])) +#define ROM_API_INTERRUPT_TABLE ((uint32_t*) (ROM_API_TABLE[12])) +#define ROM_API_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[13])) +#define ROM_API_PRCM_TABLE ((uint32_t*) (ROM_API_TABLE[14])) +#define ROM_API_SMPH_TABLE ((uint32_t*) (ROM_API_TABLE[15])) +#define ROM_API_SSI_TABLE ((uint32_t*) (ROM_API_TABLE[17])) +#define ROM_API_TIMER_TABLE ((uint32_t*) (ROM_API_TABLE[18])) +#define ROM_API_TRNG_TABLE ((uint32_t*) (ROM_API_TABLE[19])) +#define ROM_API_UART_TABLE ((uint32_t*) (ROM_API_TABLE[20])) +#define ROM_API_UDMA_TABLE ((uint32_t*) (ROM_API_TABLE[21])) +#define ROM_API_VIMS_TABLE ((uint32_t*) (ROM_API_TABLE[22])) + +// AON_EVENT FUNCTIONS +#define ROM_AONEventMcuWakeUpSet \ + ((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \ + ROM_API_AON_EVENT_TABLE[0]) + +#define ROM_AONEventMcuWakeUpGet \ + ((uint32_t (*)(uint32_t ui32MCUWUEvent)) \ + ROM_API_AON_EVENT_TABLE[1]) + +#define ROM_AONEventAuxWakeUpSet \ + ((void (*)(uint32_t ui32AUXWUEvent, uint32_t ui32EventSrc)) \ + ROM_API_AON_EVENT_TABLE[2]) + +#define ROM_AONEventAuxWakeUpGet \ + ((uint32_t (*)(uint32_t ui32AUXWUEvent)) \ + ROM_API_AON_EVENT_TABLE[3]) + +#define ROM_AONEventMcuSet \ + ((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \ + ROM_API_AON_EVENT_TABLE[4]) + +#define ROM_AONEventMcuGet \ + ((uint32_t (*)(uint32_t ui32MCUEvent)) \ + ROM_API_AON_EVENT_TABLE[5]) + + +// AON_WUC FUNCTIONS +#define ROM_AONWUCAuxReset \ + ((void (*)(void)) \ + ROM_API_AON_WUC_TABLE[3]) + +#define ROM_AONWUCRechargeCtrlConfigSet \ + ((void (*)(bool bAdaptEnable, uint32_t ui32AdaptRate, uint32_t ui32Period, uint32_t ui32MaxPeriod)) \ + ROM_API_AON_WUC_TABLE[4]) + +#define ROM_AONWUCOscConfig \ + ((void (*)(uint32_t ui32Period)) \ + ROM_API_AON_WUC_TABLE[5]) + + +// AUX_TDC FUNCTIONS +#define ROM_AUXTDCConfigSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \ + ROM_API_AUX_TDC_TABLE[0]) + +#define ROM_AUXTDCMeasurementDone \ + ((uint32_t (*)(uint32_t ui32Base)) \ + ROM_API_AUX_TDC_TABLE[1]) + + +// AUX_WUC FUNCTIONS +#define ROM_AUXWUCClockEnable \ + ((void (*)(uint32_t ui32Clocks)) \ + ROM_API_AUX_WUC_TABLE[0]) + +#define ROM_AUXWUCClockDisable \ + ((void (*)(uint32_t ui32Clocks)) \ + ROM_API_AUX_WUC_TABLE[1]) + +#define ROM_AUXWUCClockStatus \ + ((uint32_t (*)(uint32_t ui32Clocks)) \ + ROM_API_AUX_WUC_TABLE[2]) + +#define ROM_AUXWUCPowerCtrl \ + ((void (*)(uint32_t ui32PowerMode)) \ + ROM_API_AUX_WUC_TABLE[3]) + + +// DDI FUNCTIONS +#define ROM_DDI16BitWrite \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData)) \ + ROM_API_DDI_TABLE[0]) + +#define ROM_DDI16BitfieldWrite \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)) \ + ROM_API_DDI_TABLE[1]) + +#define ROM_DDI16BitRead \ + ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \ + ROM_API_DDI_TABLE[2]) + +#define ROM_DDI16BitfieldRead \ + ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \ + ROM_API_DDI_TABLE[3]) + + +// FLASH FUNCTIONS +#define ROM_FlashPowerModeGet \ + ((uint32_t (*)(void)) \ + ROM_API_FLASH_TABLE[1]) + +#define ROM_FlashProtectionSet \ + ((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \ + ROM_API_FLASH_TABLE[2]) + +#define ROM_FlashProtectionGet \ + ((uint32_t (*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[3]) + +#define ROM_FlashProtectionSave \ + ((uint32_t (*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[4]) + +#define ROM_FlashEfuseReadRow \ + ((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \ + ROM_API_FLASH_TABLE[8]) + +#define ROM_FlashDisableSectorsForWrite \ + ((void (*)(void)) \ + ROM_API_FLASH_TABLE[9]) + + +// I2C FUNCTIONS +#define ROM_I2CMasterInitExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \ + ROM_API_I2C_TABLE[0]) + +#define ROM_I2CMasterErr \ + ((uint32_t (*)(uint32_t ui32Base)) \ + ROM_API_I2C_TABLE[1]) + + +// INTERRUPT FUNCTIONS +#define ROM_IntPriorityGroupingSet \ + ((void (*)(uint32_t ui32Bits)) \ + ROM_API_INTERRUPT_TABLE[0]) + +#define ROM_IntPriorityGroupingGet \ + ((uint32_t (*)(void)) \ + ROM_API_INTERRUPT_TABLE[1]) + +#define ROM_IntPrioritySet \ + ((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \ + ROM_API_INTERRUPT_TABLE[2]) + +#define ROM_IntPriorityGet \ + ((int32_t (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[3]) + +#define ROM_IntEnable \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[4]) + +#define ROM_IntDisable \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[5]) + +#define ROM_IntPendSet \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[6]) + +#define ROM_IntPendGet \ + ((bool (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[7]) + +#define ROM_IntPendClear \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[8]) + + +// IOC FUNCTIONS +#define ROM_IOCPortConfigureSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \ + ROM_API_IOC_TABLE[0]) + +#define ROM_IOCPortConfigureGet \ + ((uint32_t (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[1]) + +#define ROM_IOCIOShutdownSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \ + ROM_API_IOC_TABLE[2]) + +#define ROM_IOCIOModeSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \ + ROM_API_IOC_TABLE[4]) + +#define ROM_IOCIOIntSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \ + ROM_API_IOC_TABLE[5]) + +#define ROM_IOCIOPortPullSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \ + ROM_API_IOC_TABLE[6]) + +#define ROM_IOCIOHystSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \ + ROM_API_IOC_TABLE[7]) + +#define ROM_IOCIOInputSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \ + ROM_API_IOC_TABLE[8]) + +#define ROM_IOCIOSlewCtrlSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \ + ROM_API_IOC_TABLE[9]) + +#define ROM_IOCIODrvStrengthSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \ + ROM_API_IOC_TABLE[10]) + +#define ROM_IOCIOPortIdSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \ + ROM_API_IOC_TABLE[11]) + +#define ROM_IOCIntEnable \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[12]) + +#define ROM_IOCIntDisable \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[13]) + +#define ROM_IOCPinTypeGpioInput \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[14]) + +#define ROM_IOCPinTypeGpioOutput \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[15]) + +#define ROM_IOCPinTypeUart \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \ + ROM_API_IOC_TABLE[16]) + +#define ROM_IOCPinTypeSsiMaster \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ + ROM_API_IOC_TABLE[17]) + +#define ROM_IOCPinTypeSsiSlave \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ + ROM_API_IOC_TABLE[18]) + +#define ROM_IOCPinTypeI2c \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \ + ROM_API_IOC_TABLE[19]) + +#define ROM_IOCPinTypeAux \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[21]) + + +// PRCM FUNCTIONS +#define ROM_PRCMInfClockConfigureSet \ + ((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \ + ROM_API_PRCM_TABLE[0]) + +#define ROM_PRCMInfClockConfigureGet \ + ((uint32_t (*)(uint32_t ui32PowerMode)) \ + ROM_API_PRCM_TABLE[1]) + +#define ROM_PRCMAudioClockConfigSet \ + ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \ + ROM_API_PRCM_TABLE[4]) + +#define ROM_PRCMPowerDomainOn \ + ((void (*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[5]) + +#define ROM_PRCMPowerDomainOff \ + ((void (*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[6]) + +#define ROM_PRCMPeripheralRunEnable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[7]) + +#define ROM_PRCMPeripheralRunDisable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[8]) + +#define ROM_PRCMPeripheralSleepEnable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[9]) + +#define ROM_PRCMPeripheralSleepDisable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[10]) + +#define ROM_PRCMPeripheralDeepSleepEnable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[11]) + +#define ROM_PRCMPeripheralDeepSleepDisable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[12]) + +#define ROM_PRCMPowerDomainStatus \ + ((uint32_t (*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[13]) + +#define ROM_PRCMDeepSleep \ + ((void (*)(void)) \ + ROM_API_PRCM_TABLE[14]) + + +// SMPH FUNCTIONS +#define ROM_SMPHAcquire \ + ((void (*)(uint32_t ui32Semaphore)) \ + ROM_API_SMPH_TABLE[0]) + + +// SSI FUNCTIONS +#define ROM_SSIConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \ + ROM_API_SSI_TABLE[0]) + +#define ROM_SSIDataPut \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \ + ROM_API_SSI_TABLE[1]) + +#define ROM_SSIDataPutNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \ + ROM_API_SSI_TABLE[2]) + +#define ROM_SSIDataGet \ + ((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ + ROM_API_SSI_TABLE[3]) + +#define ROM_SSIDataGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ + ROM_API_SSI_TABLE[4]) + + +// TIMER FUNCTIONS +#define ROM_TimerConfigure \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \ + ROM_API_TIMER_TABLE[0]) + +#define ROM_TimerLevelControl \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \ + ROM_API_TIMER_TABLE[1]) + +#define ROM_TimerStallControl \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \ + ROM_API_TIMER_TABLE[3]) + +#define ROM_TimerWaitOnTriggerControl \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \ + ROM_API_TIMER_TABLE[4]) + + +// TRNG FUNCTIONS +#define ROM_TRNGNumberGet \ + ((uint32_t (*)(uint32_t ui32Word)) \ + ROM_API_TRNG_TABLE[1]) + + +// UART FUNCTIONS +#define ROM_UARTFIFOLevelGet \ + ((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \ + ROM_API_UART_TABLE[0]) + +#define ROM_UARTConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \ + ROM_API_UART_TABLE[1]) + +#define ROM_UARTConfigGetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \ + ROM_API_UART_TABLE[2]) + +#define ROM_UARTDisable \ + ((void (*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[3]) + +#define ROM_UARTCharGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[4]) + +#define ROM_UARTCharGet \ + ((int32_t (*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[5]) + +#define ROM_UARTCharPutNonBlocking \ + ((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \ + ROM_API_UART_TABLE[6]) + +#define ROM_UARTCharPut \ + ((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \ + ROM_API_UART_TABLE[7]) + + +// UDMA FUNCTIONS +#define ROM_uDMAChannelAttributeEnable \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ + ROM_API_UDMA_TABLE[0]) + +#define ROM_uDMAChannelAttributeDisable \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ + ROM_API_UDMA_TABLE[1]) + +#define ROM_uDMAChannelAttributeGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ + ROM_API_UDMA_TABLE[2]) + +#define ROM_uDMAChannelControlSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \ + ROM_API_UDMA_TABLE[3]) + +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \ + ROM_API_UDMA_TABLE[5]) + +#define ROM_uDMAChannelSizeGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[6]) + +#define ROM_uDMAChannelModeGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[7]) + + +// VIMS FUNCTIONS +#define ROM_VIMSConfigure \ + ((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \ + ROM_API_VIMS_TABLE[0]) + +#define ROM_VIMSModeSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \ + ROM_API_VIMS_TABLE[1]) + + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ROM_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom_crypto.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom_crypto.c new file mode 100644 index 0000000..84a4c26 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom_crypto.c @@ -0,0 +1,306 @@ +/******************************************************************************* +* Filename: rom_crypto.c +* Revised: 2018-09-17 08:57:21 +0200 (Mon, 17 Sep 2018) +* Revision: 52619 +* +* Description: This is the implementation for the API to the AES, ECC and +* SHA256 functions built into ROM on the CC26xx. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +*******************************************************************************/ + +#include +#include "rom_crypto.h" + +///////////////////////////////////* AES-128 *////////////////////////////////// + +/* AES - ECB */ +typedef void(*aes_ecb_encrypt_t)(uint8_t *, uint16_t, uint8_t *); +aes_ecb_encrypt_t aes_ecb_encrypt = (aes_ecb_encrypt_t)(0x10018a99); + +typedef void(*aes_ecb_decrypt_t)(uint8_t *, uint16_t, uint8_t *); +aes_ecb_decrypt_t aes_ecb_decrypt= (aes_ecb_decrypt_t)(0x10018ac5); + +//***************************************************************************** +// AES_ECB_EncryptData +//***************************************************************************** +void +AES_ECB_EncryptData(uint8_t *text, uint16_t textLen, uint8_t *aesKey) +{ + aes_ecb_encrypt(text, textLen, aesKey); +} + +//***************************************************************************** +// AES_ECB_DecryptData +//***************************************************************************** +void +AES_ECB_DecryptData(uint8_t *text, uint16_t textLen, uint8_t *aesKey) +{ + aes_ecb_decrypt(text, textLen, aesKey); +} + +/* AES - CCM */ +typedef int8_t(*aes_ccm_encrypt_t)(uint8_t, uint8_t, uint8_t *, uint8_t *, + uint16_t, uint8_t *, uint16_t, uint8_t *, + uint8_t *, uint8_t); +aes_ccm_encrypt_t aes_ccm_encrypt = (aes_ccm_encrypt_t)(0x10018a19); + +typedef int8_t(*aes_ccm_decrypt_t)(uint8_t, uint8_t, uint8_t *, uint8_t *, + uint16_t, uint8_t *, uint16_t, uint8_t *, + uint8_t *, uint8_t); +aes_ccm_decrypt_t aes_ccm_decrypt= (aes_ccm_decrypt_t)(0x10018a35); + +//***************************************************************************** +// AES_CCM_EncryptData +//***************************************************************************** +int8_t +AES_CCM_EncryptData(uint8_t encryptFlag, uint8_t MACLen, uint8_t *nonce, + uint8_t *plainText, uint16_t textLen, + uint8_t *addDataBuf, uint16_t addBufLen, + uint8_t *aesKey, uint8_t *MAC, uint8_t ccmLVal) +{ + return aes_ccm_encrypt(encryptFlag, MACLen, nonce, plainText, textLen, + addDataBuf, addBufLen, aesKey, MAC, ccmLVal); +} + +//***************************************************************************** +// AES_CCM_DecryptData +//***************************************************************************** +int8_t +AES_CCM_DecryptData(uint8_t decryptFlag, uint8_t MACLen, uint8_t *nonce, + uint8_t *cipherText, uint16_t textLen, + uint8_t *addDataBuf, uint16_t addBufLen, + uint8_t *aesKey, uint8_t *MAC, uint8_t ccmLVal) +{ + return aes_ccm_decrypt(decryptFlag, MACLen, nonce, cipherText, textLen, + addDataBuf, addBufLen, aesKey, MAC, ccmLVal); + +} + +/* AES - CTR */ +typedef uint8_t(*aes_ctr_encrypt_t)(uint8_t *, uint16_t, uint8_t *, uint8_t *, + uint8_t *); +aes_ctr_encrypt_t aes_ctr_encrypt = (aes_ctr_encrypt_t)(0x100175ed); + +typedef uint8_t(*aes_ctr_decrypt_t)(uint8_t *, uint16_t, uint8_t *, uint8_t *, + uint8_t *); +aes_ctr_decrypt_t aes_ctr_decrypt= (aes_ctr_decrypt_t)(0x10017771); + +//***************************************************************************** +// AES_CTR_EncryptData +//***************************************************************************** +uint8_t +AES_CTR_EncryptData(uint8_t *plainText, uint16_t textLen, + uint8_t *aesKey, uint8_t *nonce, + uint8_t *initVector) +{ + return aes_ctr_encrypt(plainText, textLen, aesKey, nonce, initVector); +} + +//***************************************************************************** +// AES_CTR_DecryptData +//***************************************************************************** +uint8_t +AES_CTR_DecryptData(uint8_t *cipherText, uint16_t textLen, + uint8_t *aesKey, uint8_t *nonce, + uint8_t *initVector) +{ + return aes_ctr_decrypt(cipherText, textLen, aesKey, nonce, initVector); +} + +////////////////////////////////////* ECC *//////////////////////////////////// +#ifdef ECC_PRIME_NIST256_CURVE +//#define TEST_NIST256 +//#define PARAM_P NIST256_p; +#define PARAM_P 0x10018b0c; + +//#define PARAM_R NIST256_r; +#define PARAM_R 0x10018b30; + +//#define PARAM_A NIST256_a; +#define PARAM_A 0x10018b54; + +//#define PARAM_B NIST256_b; +#define PARAM_B 0x10018b78; + +//#define PARAM_GX NIST256_Gx; +#define PARAM_GX 0x10018b9c; + +//#define PARAM_GY NIST256_Gy; +#define PARAM_GY 0x10018bc0; + +#endif + + +//***************************************************************************** +// ECC_initialize +//***************************************************************************** +void +ECC_initialize(uint32_t *pWorkzone) +{ + // Initialize curve parameters + //data_p = (uint32_t *)PARAM_P; + *((uint32_t **)0x20004f48) = (uint32_t *)PARAM_P; + + //data_r = (uint32_t *)PARAM_R; + *((uint32_t **)0x20004f4c) = (uint32_t *)PARAM_R; + + //data_a = (uint32_t *)PARAM_A; + *((uint32_t **)0x20004f50) = (uint32_t *)PARAM_A; + + //data_b = (uint32_t *)PARAM_B; + *((uint32_t **)0x20004fa8) = (uint32_t *)PARAM_B; + + //data_Gx = (uint32_t *)PARAM_GX; + *((uint32_t **)0x20004fa0) = (uint32_t *)PARAM_GX; + + //data_Gy = (uint32_t *)PARAM_GY; + *((uint32_t **)0x20004fa4) = (uint32_t *)PARAM_GY; + + // Initialize window size + //win = (uint8_t) ECC_WINDOW_SIZE; + *((uint8_t *)0x20004f40) = (uint8_t) ECC_WINDOW_SIZE; + + // Initialize work zone + //workzone = (uint32_t *) pWorkzone; + *((uint32_t **)0x20004f44) = (uint32_t *) pWorkzone; +} + +typedef uint8_t(*ecc_keygen_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *); +ecc_keygen_t ecc_generatekey = (ecc_keygen_t)(0x10017dbd); + +typedef uint8_t(*ecdsa_sign_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdsa_sign_t ecc_ecdsa_sign = (ecdsa_sign_t)(0x10017969); + +typedef uint8_t(*ecdsa_verify_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdsa_verify_t ecc_ecdsa_verify = (ecdsa_verify_t)(0x10017b01); + +typedef uint8_t(*ecdh_computeSharedSecret_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdh_computeSharedSecret_t ecdh_computeSharedSecret = (ecdh_computeSharedSecret_t)(0x10017ded); + +//***************************************************************************** +// ECC_generateKey +//***************************************************************************** +uint8_t +ECC_generateKey(uint32_t *randString, uint32_t *privateKey, + uint32_t *publicKey_x, uint32_t *publicKey_y) +{ + return (uint8_t)ecc_generatekey((uint32_t*)randString, (uint32_t*)privateKey, + (uint32_t*)publicKey_x, (uint32_t*)publicKey_y); + +} + +//***************************************************************************** +// ECC_ECDSA_sign +//***************************************************************************** +uint8_t +ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString, + uint32_t *sign1, uint32_t *sign2) +{ + return (uint8_t)ecc_ecdsa_sign((uint32_t*)secretKey, (uint32_t*)text, (uint32_t*)randString, + (uint32_t*)sign1, (uint32_t*)sign2); +} + +//***************************************************************************** +// ECC_ECDSA_verify +//***************************************************************************** +uint8_t +ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y, + uint32_t *text, uint32_t *sign1, uint32_t *sign2) +{ + return (uint8_t)ecc_ecdsa_verify((uint32_t*)publicKey_x, (uint32_t*)publicKey_y, (uint32_t*)text, + (uint32_t*)sign1, (uint32_t*)sign2); +} + +//***************************************************************************** +// ECC_ECDH_computeSharedSecret +//***************************************************************************** +uint8_t +ECC_ECDH_computeSharedSecret(uint32_t *privateKey, uint32_t *publicKey_x, + uint32_t *publicKey_y, uint32_t *sharedSecret_x, + uint32_t *sharedSecret_y) +{ + return (uint8_t)ecdh_computeSharedSecret((uint32_t*)privateKey, (uint32_t*)publicKey_x, + (uint32_t*)publicKey_y, (uint32_t*)sharedSecret_x, + (uint32_t*)sharedSecret_y); +} + + +//////////////////////////////////* SHA-256 */////////////////////////////////// + +typedef uint8_t(*sha256_full_t)(SHA256_memory_t *, uint8_t *, uint8_t *, uint32_t); +sha256_full_t sha256_runfullalg = (sha256_full_t)(0x10018129); + +typedef uint8_t(*sha256_init_t)(SHA256_memory_t *); +sha256_init_t sha256_initialize = (sha256_init_t)(0x10017ffd); + +typedef uint8_t(*sha256_process_t)(SHA256_memory_t *, uint8_t *, uint32_t); +sha256_process_t sha256_execute = (sha256_process_t)(0x10018019); + +typedef uint8_t(*sha256_final_t)(SHA256_memory_t *, uint8_t *); +sha256_final_t sha256_output = (sha256_final_t)(0x10018089); + +//***************************************************************************** +// SHA256_runFullAlgorithm +//***************************************************************************** +uint8_t +SHA256_runFullAlgorithm(SHA256_memory_t *memory, uint8_t *pBufIn, + uint32_t bufLen, uint8_t *pBufOut) +{ + return (uint8_t)sha256_runfullalg(memory, pBufOut, pBufIn, bufLen); +} + +//***************************************************************************** +// SHA256_initialize +//***************************************************************************** +uint8_t +SHA256_initialize(SHA256_memory_t *memory) +{ + return (uint8_t)sha256_initialize(memory); +} + +//***************************************************************************** +// SHA256_execute +//***************************************************************************** +uint8_t +SHA256_execute(SHA256_memory_t *memory, uint8_t *pBufIn, uint32_t bufLen) +{ + return (uint8_t)sha256_execute(memory,pBufIn, bufLen); +} + +//***************************************************************************** +// SHA256_output +//***************************************************************************** +uint8_t +SHA256_output(SHA256_memory_t *memory, uint8_t *pBufOut) +{ + return (uint8_t)sha256_output(memory, pBufOut); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom_crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom_crypto.h new file mode 100644 index 0000000..cfec1db --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom_crypto.h @@ -0,0 +1,397 @@ +/****************************************************************************** +* Filename: rom_crypto.h +* Revised: 2018-09-17 09:24:56 +0200 (Mon, 17 Sep 2018) +* Revision: 52624 +* +* Description: This header file is the API to the crypto functions +* built into ROM on the CC13xx/CC26xx. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +*******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup rom_crypto_api +//! @{ +// +//***************************************************************************** + +#ifndef ROM_CRYPTO_H +#define ROM_CRYPTO_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +///////////////////////////////////* AES-128 *////////////////////////////////// + +//***************************************************************************** +/*! + * \brief Use a random 128 bit key to encrypt data with the AES. + * + * \param text Pointer to data to encrypt. + * \param textLen Length of text. + * \param aesKey Pointer to 128 bit key used to encrypt text. + * + * \return None + */ +//***************************************************************************** +extern void AES_ECB_EncryptData(uint8_t *text, uint16_t textLen, uint8_t *aesKey); + +//***************************************************************************** +/*! + * \brief Use a random 128 bit key to decrypt data with the AES. + * + * \param text Pointer to data to decrypt. + * \param textLen Length of text. + * \param aesKey Pointer to 128 bit key used to decrypt. This is the same key + * that was used to originally encrypt this data. + * + * \return None + */ +//***************************************************************************** +extern void AES_ECB_DecryptData(uint8_t *text, uint16_t textLen, uint8_t *aesKey); + +//***************************************************************************** +/*! + * \brief Authenticate and optionally encrypt message plainText. + * + * \param encryptFlag Encryption flag. + * - set to \c true for authentication with encryption. + * - set to \c false for authentication only. + * \param MACLen Length of MAC in bytes. + * \param nonce Pointer to random nonce. Nonce length = 15 - ccmLVal. + * \param plainText Pointer to text to encrypt, input and output. + * \param textLen Length of text to encrypt. + * \param addDataBuf Pointer to additional data for authentication + * \param addBufLen Additional authentication buffer length. + * \param aesKey Pointer to the AES key or key expansion buffer. + * \param MAC Pointer to 16 byte Message Authentication Code output buffer. + * \param ccmLVal CCM L value to be used. Values {2,3}. + * + * \return Zero when successful. + */ +//***************************************************************************** +extern int8_t AES_CCM_EncryptData(uint8_t encryptFlag, uint8_t MACLen, uint8_t *nonce, + uint8_t *plainText, uint16_t textLen, + uint8_t *addDataBuf, uint16_t addBufLen, + uint8_t *aesKey, uint8_t *MAC, uint8_t ccmLVal); + +//***************************************************************************** +/*! + * \brief Authenticate and optionally decrypt message cipherText. + * + * \param decryptFlag Decryption flag. + * - \c true for authentication with decryption. + * - \c false for authentication only. + * \param MACLen Length of MAC in bytes. + * \param nonce Pointer to random nonce. Nonce length = 15 - ccmLVal. + * \param cipherText Pointer to text to decrypt, input and output. + * \param textLen Length of text to decrypt. + * \param addDataBuf Pointer to additional data for authentication + * \param addBufLen Additional authentication buffer length. + * \param aesKey Pointer to the AES key or key expansion buffer. + * \param MAC Pointer to 16 byte Message Authentication Code output buffer. + * \param ccmLVal CCM L value to be used. Values {2,3}. + * + * \return Zero when Successful. + */ +//***************************************************************************** +extern int8_t AES_CCM_DecryptData(uint8_t decryptFlag, uint8_t MACLen, uint8_t *nonce, + uint8_t *cipherText, uint16_t textLen, + uint8_t *addDataBuf, uint16_t addBufLen, + uint8_t *aesKey, uint8_t *MAC, uint8_t ccmLVal); + +//***************************************************************************** +/*! + * \brief Encrypt plaintext using the AES key, nonce and initialization vector. + * + * \param plainText Pointer to text to encrypt. + * \param textLen Length of text. + * \param aesKey Pointer to 128 bit key used to encrypt text. + * \param nonce Pointer to 4 byte nonce. + * \param initVector Pointer to 8 byte random initialization vector. + * + * \return None + */ +//***************************************************************************** +extern uint8_t AES_CTR_EncryptData(uint8_t *plainText, uint16_t textLen, + uint8_t *aesKey, uint8_t *nonce, + uint8_t *initVector); + +//***************************************************************************** +/*! + * \brief Decrypt ciphertext using the AES key, nonce and initialization vector. + * + * \param cipherText Pointer to text to decrypt + * \param textLen Length of text. + * \param aesKey Pointer to 128 bit key used to encrypt text. + * \param nonce Pointer to 4 byte nonce. + * \param initVector Pointer to 8 byte random initialization vector. + * + * \return None + */ +//***************************************************************************** +extern uint8_t AES_CTR_DecryptData(uint8_t *cipherText, uint16_t textLen, + uint8_t *aesKey, uint8_t *nonce, + uint8_t *initVector); + +////////////////////////////////////* ECC *///////////////////////////////////// + +/* Window size, valid values are 2,3,4,5. + * Higher the value, faster the computation at the expense of memory usage. + * + * Recommended workzone size (in 4-byte words) + * Window size: 3, Workzone size: 275 + * + */ +#define ECC_WINDOW_SIZE 3 + +/* + * ECC Supported Curves, define one: + * ECC_PRIME_NIST256_CURVE + */ +#define ECC_PRIME_NIST256_CURVE + +/* + * ECC Return Status Flags. + */ +// Scalar multiplication status +#define ECC_MODULUS_EVEN 0xDC +#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2 +#define ECC_MODULUS_LENGTH_ZERO 0x08 +#define ECC_MODULUS_MSW_IS_ZERO 0x30 +#define ECC_SCALAR_TOO_LONG 0x35 +#define ECC_SCALAR_LENGTH_ZERO 0x53 +#define ECC_ORDER_TOO_LONG 0xC6 +#define ECC_ORDER_LENGTH_ZERO 0x6C +#define ECC_X_COORD_TOO_LONG 0x3C +#define ECC_X_COORD_LENGTH_ZERO 0xC3 +#define ECC_Y_COORD_TOO_LONG 0x65 +#define ECC_Y_COORD_LENGTH_ZERO 0x56 +#define ECC_A_COEF_TOO_LONG 0x5C +#define ECC_A_COEF_LENGTH_ZERO 0xC5 +#define ECC_BAD_WINDOW_SIZE 0x66 +#define ECC_SCALAR_MUL_OK 0x99 + +// ECDSA and ECDH status +#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28 +#define ECC_ORDER_EVEN 0x82 +#define ECC_ORDER_MSW_IS_ZERO 0x23 +#define ECC_ECC_KEY_TOO_LONG 0x25 +#define ECC_ECC_KEY_LENGTH_ZERO 0x52 +#define ECC_DIGEST_TOO_LONG 0x27 +#define ECC_DIGEST_LENGTH_ZERO 0x72 +#define ECC_ECDSA_SIGN_OK 0x32 +#define ECC_ECDSA_INVALID_SIGNATURE 0x5A +#define ECC_ECDSA_VALID_SIGNATURE 0xA5 +#define ECC_SIG_P1_TOO_LONG 0x11 +#define ECC_SIG_P1_LENGTH_ZERO 0x12 +#define ECC_SIG_P2_TOO_LONG 0x22 +#define ECC_SIG_P2_LENGTH_ZERO 0x21 + +#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK + +//***************************************************************************** +/*! + * \brief Pass pointer to ECC memory allocation to ECC engine. + * + * This function can be called again to point the ECC workzone at + * a different memory buffer. + * + * \param pWorkzone Pointer to memory allocated for computations, input. + * See description at beginning of ECC section for + * memory requirements. + * + * \return None + */ +//***************************************************************************** + extern void ECC_initialize(uint32_t *pWorkzone); + +//***************************************************************************** + /*! + * \brief Generate a key. + * + * This is used for both ECDH and ECDSA. + * + * \param randString Pointer to random string, input. + * \param privateKey Pointer to the private key, output. + * \param publicKey_x Pointer to public key X-coordinate, output. + * \param publicKey_y Pointer to public key Y-coordinate, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_generateKey(uint32_t *randString, uint32_t *privateKey, + uint32_t *publicKey_x, uint32_t *publicKey_y); + +//***************************************************************************** +/*! + * \brief Sign data. + * + * \param secretKey Pointer to the secret key, input. + * \param text Pointer to the message, input. + * \param randString Pointer to random string, input. + * \param sign1 Pointer to signature part 1, output. + * \param sign2 Pointer to signature part 2, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString, + uint32_t *sign1, uint32_t *sign2); + +//***************************************************************************** +/*! + * \brief Verify signature. + * + * \param publicKey_x Pointer to public key X-coordinate, input. + * \param publicKey_y Pointer to public key Y-coordinate, input. + * \param text Pointer to message data, input. + * \param sign1 Pointer to signature part 1, input. + * \param sign2 Pointer to signature part 2, input. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y, + uint32_t *text, uint32_t *sign1, uint32_t *sign2); + +//***************************************************************************** +/*! + * \brief Compute the shared secret. + * + * \param privateKey Pointer to private key, input. + * \param publicKey_x Pointer to public key X-coordinate, input. + * \param publicKey_y Pointer to public key Y-coordinate, input. + * \param sharedSecret_x Pointer to shared secret X-coordinate, output. + * \param sharedSecret_y Pointer to shared secret Y-coordinate, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDH_computeSharedSecret(uint32_t *privateKey, + uint32_t *publicKey_x, + uint32_t *publicKey_y, + uint32_t *sharedSecret_x, + uint32_t *sharedSecret_y); + + +///////////////////////////////////* SHA-256 *////////////////////////////////// + +//! \brief A SHA256_memory_t variable of this type must be allocated before running any +//! SHA256 functions. +typedef struct +{ + uint32_t state[8]; + uint32_t textLen[2]; + uint32_t W[16]; +} SHA256_memory_t; + +//***************************************************************************** +/*! + * \brief Perform SHA256 on the input data. + * + * The input and output buffer can point to the same memory. + * This is the equivalent of calling \ref SHA256_initialize(), + * \ref SHA256_execute() and \ref SHA256_output() sequentially. + * + * \param memory Pointer to memory for operations, input. + * \param pBufIn Pointer to input buffer, input. + * \param bufLen Length of input. + * \param pBufOut Pointer to output buffer, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t SHA256_runFullAlgorithm(SHA256_memory_t *memory, uint8_t *pBufIn, + uint32_t bufLen, uint8_t *pBufOut); + +//***************************************************************************** +/*! + * \brief Intializes the SHA256 engine. + * + * This function must be called once before all other SHA256 functions other than + * \ref SHA256_runFullAlgorithm(). + * + * \param workZone Pointer to memory for operations, input. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t SHA256_initialize(SHA256_memory_t *workZone); + +//***************************************************************************** +/*! + * \brief Perform SHA256. + * + * Must call \ref SHA256_output() to receive output from this operation. + * + * \param config Pointer to memory for operations, input. + * \param pBufIn Pointer to input text, input. + * \param bufLen Length of input, input. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t SHA256_execute(SHA256_memory_t *config, uint8_t *pBufIn, + uint32_t bufLen); + +//***************************************************************************** +/*! + * \brief Complete the process by passing the modified data back. + * + * \param memory Pointer to memory for operations, input. + * \param pBufOut Pointer to output buffer, output. Buffer must be at least 32 bytes long. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t SHA256_output(SHA256_memory_t *memory, uint8_t *pBufOut); + +#ifdef __cplusplus +} +#endif + +#endif /* ROM_CRYPTO_H */ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup.c new file mode 100644 index 0000000..1f2ff9a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup.c @@ -0,0 +1,352 @@ +/****************************************************************************** +* Filename: setup.c +* Revised: 2018-11-06 15:08:57 +0100 (Tue, 06 Nov 2018) +* Revision: 53239 +* +* Description: Setup file for CC13xx/CC26xx devices. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +// Hardware headers +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_2_refsys.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_aon_ioc.h" +#include "../inc/hw_aon_sysctl.h" +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_aux_wuc.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_flash.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_vims.h" +// Driverlib headers +#include "aon_wuc.h" +#include "aux_wuc.h" +#include "chipinfo.h" +#include "setup.h" +#include "setup_rom.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SetupTrimDevice + #define SetupTrimDevice NOROM_SetupTrimDevice +#endif + + + +//***************************************************************************** +// +// Defined CPU delay macro with microseconds as input +// Quick check shows: (To be further investigated) +// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 5 cycles +// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 1, there is 4 cycles +// At 24 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 3 cycles +// +//***************************************************************************** +#define CPU_DELAY_MICRO_SECONDS( x ) \ + CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 ) + + +//***************************************************************************** +// +// Function declarations +// +//***************************************************************************** +static void TrimAfterColdReset( void ); +static void TrimAfterColdResetWakeupFromShutDown( uint32_t ui32Fcfg1Revision ); +static void TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void ); + +//***************************************************************************** +// +// Perform the necessary trim of the device which is not done in boot code +// +// This function should only execute coming from ROM boot. The current +// implementation does not take soft reset into account. However, it does no +// damage to execute it again. It only consumes time. +// +//***************************************************************************** +void +SetupTrimDevice(void) +{ + uint32_t ui32Fcfg1Revision; + uint32_t ui32AonSysResetctl; + + // Get layout revision of the factory configuration area + // (Handle undefined revision as revision = 0) + ui32Fcfg1Revision = HWREG(FCFG1_BASE + FCFG1_O_FCFG1_REVISION); + if ( ui32Fcfg1Revision == 0xFFFFFFFF ) { + ui32Fcfg1Revision = 0; + } + + // This driverlib version and setup file is for CC13x0 PG2.0 and later. + // Halt if violated + ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated(); + + // Enable standby in flash bank + HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Clock must always be enabled for the semaphore module (due to ADI/DDI HW workaround) + HWREG( AUX_WUC_BASE + AUX_WUC_O_MODCLKEN1 ) = AUX_WUC_MODCLKEN1_SMPH; + + // Warm resets on CC13x0 and CC26x0 complicates software design because much of + // our software expect that initialization is done from a full system reset. + // This includes RTC setup, oscillator configuration and AUX setup. + // To ensure a full reset of the device is done when customers get e.g. a Watchdog + // reset, the following is set here: + HWREGBITW( PRCM_BASE + PRCM_O_WARMRESET, PRCM_WARMRESET_WR_TO_PINRESET_BITN ) = 1; + + // Select correct CACHE mode and set correct CACHE configuration +#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) + SetupSetCacheModeAccordingToCcfgSetting(); +#else + NOROM_SetupSetCacheModeAccordingToCcfgSetting(); +#endif + + // 1. Check for powerdown + // 2. Check for shutdown + // 3. Assume cold reset if none of the above. + // + // It is always assumed that the application will freeze the latches in + // AON_IOC when going to powerdown in order to retain the values on the IOs. + // + // NB. If this bit is not cleared before proceeding to powerdown, the IOs + // will all default to the reset configuration when restarting. + if( ! ( HWREGBITW( AON_IOC_BASE + AON_IOC_O_IOCLATCH, AON_IOC_IOCLATCH_EN_BITN ))) + { + // NB. This should be calling a ROM implementation of required trim and + // compensation + // e.g. TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown() + TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + } + // Check for shutdown + // + // When device is going to shutdown the hardware will automatically clear + // the SLEEPDIS bit in the SLEEP register in the AON_SYSCTL module. + // It is left for the application to assert this bit when waking back up, + // but not before the desired IO configuration has been re-established. + else if( ! ( HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_SLEEPCTL, AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN ))) + { + // NB. This should be calling a ROM implementation of required trim and + // compensation + // e.g. TrimAfterColdResetWakeupFromShutDown() --> + // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision); + TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + } + else + { + // Consider adding a check for soft reset to allow debugging to skip + // this section!!! + // + // NB. This should be calling a ROM implementation of required trim and + // compensation + // e.g. TrimAfterColdReset() --> + // TrimAfterColdResetWakeupFromShutDown() --> + // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown() + TrimAfterColdReset(); + TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision); + TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + + } + + // Set VIMS power domain control. + // PDCTL1VIMS = 0 ==> VIMS power domain is only powered when CPU power domain is powered + HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0; + + // Configure optimal wait time for flash FSM in cases where flash pump + // wakes up from sleep + HWREG(FLASH_BASE + FLASH_O_FPAC1) = (HWREG(FLASH_BASE + FLASH_O_FPAC1) & + ~FLASH_FPAC1_PSLEEPTDIS_M) | + (0x139<> + AON_SYSCTL_RESETCTL_BOOT_DET_0_S ) == 1 ) + { + ui32AonSysResetctl = ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) & + ~( AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M | + AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M )); + HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = ui32AonSysResetctl | AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M; + HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = ui32AonSysResetctl; + } + + // Make sure there are no ongoing VIMS mode change when leaving SetupTrimDevice() + // (There should typically be no wait time here, but need to be sure) + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for an eventual ongoing mode change to complete. + } +} + +//***************************************************************************** +// +//! \brief Trims to be applied when coming from POWER_DOWN (also called when +//! coming from SHUTDOWN and PIN_RESET). +//! +//! \return None +// +//***************************************************************************** +static void +TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void ) +{ + // Currently no specific trim for Powerdown +} + +//***************************************************************************** +// +//! \brief Trims to be applied when coming from SHUTDOWN (also called when +//! coming from PIN_RESET). +//! +//! \param ui32Fcfg1Revision +//! +//! \return None +// +//***************************************************************************** +static void +TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision) +{ + uint32_t ccfg_ModeConfReg ; + uint32_t mp1rev ; + + // Force AUX on and enable clocks + // + // No need to save the current status of the power/clock registers. + // At this point both AUX and AON should have been reset to 0x0. + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) = AON_WUC_AUXCTL_AUX_FORCE_ON; + + // Wait for power on on the AUX domain + while( ! ( HWREGBITW( AON_WUC_BASE + AON_WUC_O_PWRSTAT, AON_WUC_PWRSTAT_AUX_PD_ON_BITN ))); + + // Enable the clocks for AUX_DDI0_OSC and AUX_ADI4 + HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) = AUX_WUC_MODCLKEN0_AUX_DDI0_OSC | + AUX_WUC_MODCLKEN0_AUX_ADI4; + + // Check in CCFG for alternative DCDC setting + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) { + // ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19] (=ALT_DCDC_DITHER_EN) + // ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) = CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) + // Using a single 4-bit masked write since layout is equal for both source and destination + HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 | + ( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S )); + + } + + // + // Enable for JTAG to be powered down (will still be powered on if debugger is connected) + AONWUCJtagPowerOff(); + + // read the MODE_CONF register in CCFG + ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + + // First part of trim done after cold reset and wakeup from shutdown: + // -Configure cc13x0 boost mode. + // -Adjust the VDDR_TRIM_SLEEP value. + // -Configure DCDC. + SetupAfterColdResetWakeupFromShutDownCfg1( ccfg_ModeConfReg ); + + // Second part of trim done after cold reset and wakeup from shutdown: + // -Configure XOSC. +#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) + SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg ); +#else + NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg ); +#endif + + // Increased margin between digital supply voltage and VDD BOD during standby. + // VTRIM_UDIG: signed 4 bits value to be incremented by 2 (max = 7) + // VTRIM_BOD: unsigned 4 bits value to be decremented by 1 (min = 0) + // This applies to chips with mp1rev < 542 for cc13x0 and for mp1rev < 527 for cc26x0 + mp1rev = (( HWREG( FCFG1_BASE + FCFG1_O_TRIM_CAL_REVISION ) & FCFG1_TRIM_CAL_REVISION_MP1_M ) >> + FCFG1_TRIM_CAL_REVISION_MP1_S ) ; + if ( mp1rev < 542 ) { + uint32_t ldoTrimReg = HWREG( FCFG1_BASE + FCFG1_O_BAT_RC_LDO_TRIM ); + uint32_t vtrim_bod = (( ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M ) >> + FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_S ); // bit[27:24] unsigned + uint32_t vtrim_udig = (( ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M ) >> + FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_S ); // bit[19:16] signed but treated as unsigned + if ( vtrim_bod > 0 ) { + vtrim_bod -= 1; + } + if ( vtrim_udig != 7 ) { + if ( vtrim_udig == 6 ) { + vtrim_udig = 7; + } else { + vtrim_udig = (( vtrim_udig + 2 ) & 0xF ); + } + } + HWREGB( ADI2_BASE + ADI_2_REFSYS_O_SOCLDOCTL0 ) = + ( vtrim_udig << ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S ) | + ( vtrim_bod << ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S ) ; + } + + // Third part of trim done after cold reset and wakeup from shutdown: + // -Configure HPOSC. + // -Setup the LF clock. +#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) + SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg ); +#else + NOROM_SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg ); +#endif + + // Allow AUX to power down + AUXWUCPowerCtrl( AUX_WUC_POWER_DOWN ); + + // Leaving on AUX and clock for AUX_DDI0_OSC on but turn off clock for AUX_ADI4 + HWREG( AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0 ) = AUX_WUC_MODCLKEN0_AUX_DDI0_OSC; + + // Disable EFUSE clock + HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1; +} + + +//***************************************************************************** +// +//! \brief Trims to be applied when coming from PIN_RESET. +//! +//! \return None +// +//***************************************************************************** +static void +TrimAfterColdReset( void ) +{ + // Currently no specific trim for Cold Reset +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup.h new file mode 100644 index 0000000..496b17a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup.h @@ -0,0 +1,141 @@ +/****************************************************************************** +* Filename: setup.h +* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) +* Revision: 52993 +* +* Description: Prototypes and defines for the setup API. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup setup_api +//! @{ +// +//***************************************************************************** + +#ifndef __SETUP_H__ +#define __SETUP_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +// Hardware headers +#include "../inc/hw_types.h" +// Driverlib headers +// - None needed + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SetupTrimDevice NOROM_SetupTrimDevice +#endif + +//***************************************************************************** +// +//! \brief Performs the necessary trim of the device which is not done in ROM boot code. +//! +//! This function should only execute coming from ROM boot. +//! +//! The following is handled by this function: +//! - Checks if the driverlib variant used by the application is supported by the +//! device. Execution is halted in case of unsupported driverlib variant. +//! - Configures VIMS cache mode based on setting in CCFG. +//! - Configures functionalities like DCDC and XOSC dependent on startup modes like +//! cold reset, wakeup from shutdown and wakeup from from powerdown. +//! - Configures VIMS power domain control. +//! - Configures optimal wait time for flash FSM in cases where flash pump wakes up from sleep. +//! +//! \note The current implementation does not take soft reset into account. However, +//! it does no damage to execute it again. It only consumes time. +//! +//! \note This function is called by the compiler specific device startup codes +//! that are integrated in the SimpleLink SDKs for CC13xx/CC26XX devices. +//! +//! \return None +// +//***************************************************************************** +extern void SetupTrimDevice( void ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SetupTrimDevice + #undef SetupTrimDevice + #define SetupTrimDevice ROM_SetupTrimDevice + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SETUP_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_doc.h new file mode 100644 index 0000000..07ab97e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_doc.h @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: setup_doc.h +* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) +* Revision: 49096 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup setup_api +//! @{ +//! +//! This module contains functions for device setup which is not done in boot code. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom.c new file mode 100644 index 0000000..32ac613 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom.c @@ -0,0 +1,975 @@ +/****************************************************************************** +* Filename: setup_rom.c +* Revised: 2017-11-02 11:31:15 +0100 (Thu, 02 Nov 2017) +* Revision: 50143 +* +* Description: Setup file for CC13xx/CC26xx devices. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +// Hardware headers +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_2_refsys.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_adi_4_aux.h" +#include "../inc/hw_aon_batmon.h" +#include "../inc/hw_aon_sysctl.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ddi_0_osc.h" +#include "../inc/hw_fcfg1.h" +// Driverlib headers +#include "ddi.h" +#include "ioc.h" +#include "osc.h" +#include "sys_ctrl.h" +#include "setup_rom.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SetupAfterColdResetWakeupFromShutDownCfg1 + #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #undef SetupAfterColdResetWakeupFromShutDownCfg2 + #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #undef SetupAfterColdResetWakeupFromShutDownCfg3 + #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #undef SetupGetTrimForAdcShModeEn + #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn + #undef SetupGetTrimForAdcShVbufEn + #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn + #undef SetupGetTrimForAmpcompCtrl + #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl + #undef SetupGetTrimForAmpcompTh1 + #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 + #undef SetupGetTrimForAmpcompTh2 + #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 + #undef SetupGetTrimForAnabypassValue1 + #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 + #undef SetupGetTrimForDblrLoopFilterResetVoltage + #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage + #undef SetupGetTrimForRadcExtCfg + #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg + #undef SetupGetTrimForRcOscLfIBiasTrim + #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim + #undef SetupGetTrimForRcOscLfRtuneCtuneTrim + #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #undef SetupGetTrimForXoscHfCtl + #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl + #undef SetupGetTrimForXoscHfFastStart + #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart + #undef SetupGetTrimForXoscHfIbiastherm + #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm + #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #undef SetupSetCacheModeAccordingToCcfgSetting + #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting + #undef SetupSetAonRtcSubSecInc + #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc + #undef SetupSetVddrLevel + #define SetupSetVddrLevel NOROM_SetupSetVddrLevel +#endif + +//***************************************************************************** +// +// Function declarations +// +//***************************************************************************** +//***************************************************************************** +// +// SetupSetVddrLevel +// +//***************************************************************************** +void +SetupSetVddrLevel( uint32_t ccfg_ModeConfReg ) +{ + uint32_t newTrimRaw ; + int32_t targetTrim ; + int32_t currentTrim ; + int32_t deltaTrim ; + + // + // VDDS_BOD_LEVEL = 1 means that boost mode is selected + // - Step up VDDR_TRIM to FCFG1..VDDR_TRIM_HH + newTrimRaw = (( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) & + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >> + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ; + + targetTrim = SetupSignExtendVddrTrimValue( newTrimRaw ); + currentTrim = SetupSignExtendVddrTrimValue(( + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) >> + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) ; + + if ( currentTrim != targetTrim ) { + // Disable VDDR BOD + HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN ) = 0; + + while ( currentTrim != targetTrim ) { + deltaTrim = targetTrim - currentTrim; + if ( deltaTrim > 2 ) deltaTrim = 2; + if ( deltaTrim < -2 ) deltaTrim = -2; + currentTrim += deltaTrim; + + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait one SCLK_LF period + + HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_DCDCCTL0 * 2 )) = + ( ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M << 8 ) | (( currentTrim << + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) & + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) ; + + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ) = 1; // Force SCLK_LF period wait on next read + } + + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait one SCLK_LF period + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ) = 1; // Force SCLK_LF period wait on next read + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait one more SCLK_LF period before re-enabling VDDR BOD + HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN ) = 1; + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // And finally wait for VDDR_LOSS_EN setting to propagate + } +} + +//***************************************************************************** +// +// SetupAfterColdResetWakeupFromShutDownCfg1 +// +//***************************************************************************** +void +SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ) +{ + int32_t i32VddrSleepTrim; + int32_t i32VddrSleepDelta; + + // Check for CC13xx boost mode + // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode + if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) && + (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) ) { + // Set VDDS_BOD trim - using masked write {MASK8:DATA8} + // - TRIM_VDDS_BOD is bits[7:3] of ADI3..REFSYSCTL1 + // - Needs a positive transition on BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to + // latch new VDDS BOD. Set to 0 first to guarantee a positive transition. + HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; + // + // VDDS_BOD_LEVEL = 1 means that boost mode is selected + // - Max out the VDDS_BOD trim (=VDDS_BOD_POS_31) + HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) = + ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8 ) | + ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 ) ; + HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; + + SetupSetVddrLevel( ccfg_ModeConfReg ); + + i32VddrSleepTrim = SetupSignExtendVddrTrimValue(( + HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) & + FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M ) >> + FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S ) ; + } else + { + i32VddrSleepTrim = SetupSignExtendVddrTrimValue(( + HWREG( FCFG1_BASE + FCFG1_O_LDO_TRIM ) & + FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M ) >> + FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S ) ; + } + + // Adjust the VDDR_TRIM_SLEEP value with value adjustable by customer (CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA) + // Read and sign extend VddrSleepDelta (in range -8 to +7) + i32VddrSleepDelta = + (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ))) + >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W )); + // Calculate new VDDR sleep trim + i32VddrSleepTrim = ( i32VddrSleepTrim + i32VddrSleepDelta + 1 ); + if ( i32VddrSleepTrim > 21 ) i32VddrSleepTrim = 21; + if ( i32VddrSleepTrim < -10 ) i32VddrSleepTrim = -10; + // Write adjusted value using MASKED write (MASK8) + HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_DCDCCTL1 * 2 )) = (( ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M << 8 ) | + (( i32VddrSleepTrim << ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S ) & ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M )); + + // 1. + // Do not allow DCDC to be enabled if in external regulator mode. + // Preventing this by setting both the RECHARGE and the ACTIVE bits bit in the CCFG_MODE_CONF copy register (ccfg_ModeConfReg). + // + // 2. + // Adjusted battery monitor low limit in internal regulator mode. + // This is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode. + if ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE ) { + ccfg_ModeConfReg |= ( CCFG_MODE_CONF_DCDC_RECHARGE_M | CCFG_MODE_CONF_DCDC_ACTIVE_M ); + } else { + HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0; + } + + // set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE + // Note: Inverse polarity + HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL, AON_SYSCTL_PWRCTL_DCDC_EN_BITN ) = + ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_RECHARGE_S ) & 1 ) ^ 1 ); + + // set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE + // Note: Inverse polarity + HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL, AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN ) = + ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_ACTIVE_S ) & 1 ) ^ 1 ); +} + +//***************************************************************************** +// +// SetupAfterColdResetWakeupFromShutDownCfg2 +// +//***************************************************************************** +void +SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ) +{ + uint32_t ui32Trim; + + // Following sequence is required for using XOSCHF, if not included + // devices crashes when trying to switch to XOSCHF. + // + // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1 + // register + ui32Trim = SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg ); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim); + + // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and + // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register. + ui32Trim = SetupGetTrimForRcOscLfRtuneCtuneTrim(); + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL, + (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M | + DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M), + DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S, + ui32Trim); + + // Trim XOSCHF IBIAS THERM. Get and set trim value for the + // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other + // register bit fields are set to 0. + ui32Trim = SetupGetTrimForXoscHfIbiastherm(); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2, + ui32Trim< writing to bits[7:4] + ui32Trim = SetupGetTrimForAdcShModeEn( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = + ( 0x20 | ( ui32Trim << 1 )); + + // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance to FCFG1 setting + // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register + // Using MASK4 write + 1 => writing to bits[7:4] + ui32Trim = SetupGetTrimForAdcShVbufEn( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = + ( 0x10 | ( ui32Trim )); + + // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields + // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting. + // Remaining register bit fields are set to their reset values of 0. + ui32Trim = SetupGetTrimForXoscHfCtl(ui32Fcfg1Revision); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim); + + // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting + // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL) + // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4)) + // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and + // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000) + ui32Trim = SetupGetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) = + ( 0x60 | ( ui32Trim << 1 )); + + // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from + // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM + // This is DDI_0_OSC_O_ATESTCTL bit[7] + // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020)) + // Using MASK4 write + 1 => writing to bits[7:4] + ui32Trim = SetupGetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) = + ( 0x80 | ( ui32Trim << 3 )); + + // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and + // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write + // This can be simplified since the registers are packed together in the same + // order both in FCFG1 and in the HW register. + // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18] + // Using MASK8 write + 4 => writing to bits[23:16] + ui32Trim = SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision ); + HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) = + ( 0xFC00 | ( ui32Trim << 2 )); + + // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit + // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting. + // Remaining register bit fields are set to their reset values of 0. + ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim); + + // Setting FORCE_KICKSTART_EN (ref. CC26_V1_BUG00261). Should also be done for PG2 + // (This is bit 22 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_FORCE_KICKSTART_EN; +} + +//***************************************************************************** +// +// SetupAfterColdResetWakeupFromShutDownCfg3 +// +//***************************************************************************** +void +SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) +{ + uint32_t fcfg1OscConf; + uint32_t ui32Trim; + uint32_t currentHfClock; + uint32_t ccfgExtLfClk; + + // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC + switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) { + case 2 : + // XOSC source is a 48 MHz crystal + // Do nothing (since this is the reset setting) + break; + case 1 : + // XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, otherwise skip trimming and default to 24 MHz XOSC) + + fcfg1OscConf = HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ); + + if (( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION ) == 0 ) { + // This is a HPOSC chip, apply HPOSC settings + // Set bit DDI_0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_HPOSC_MODE_EN; + + // ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit) + // ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits) + // ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET = FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits) + // ADI_2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN (1 bit) + // ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits) + // ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP = FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits) + // ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS = FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit) + + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) & + ~( ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M | ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M ) ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S ) << ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M ) >> FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S ) << ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S ) ); + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) & ~( ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M ) ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S ) << ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S ) ); + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) & + ~( ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M | ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M | ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M | ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M )) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_FILTER_EN_M ) >> FCFG1_OSC_CONF_HPOSC_FILTER_EN_S ) << ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S ) << ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M ) >> FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S ) << ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M ) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S ) << ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S ) ); + break; + } + // Not a HPOSC chip - fall through to default + default : + // XOSC source is a 24 MHz crystal (default) + // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M; + break; + } + + // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO + // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used. + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) { + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS; + } + + // Clear DDI_0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 in DDI_0_OSC_O_CTL0. + // This is typically already 0 except on Lizard where it is set in ROM-boot + HWREG( AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN; + + // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1 + ui32Trim = SetupGetTrimForXoscHfFastStart(); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim ); + + // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION + switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) { + case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz) + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF ); + SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency + break; + case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT) + // Set SCLK_LF to use the same source as SCLK_HF + // Can be simplified a bit since possible return values for HF matches LF settings + currentHfClock = OSCClockSourceGet( OSC_SRC_CLK_HF ); + OSCClockSourceSet( OSC_SRC_CLK_LF, currentHfClock ); + while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != currentHfClock ) { + // Wait until switched + } + ccfgExtLfClk = HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ); + SetupSetAonRtcSubSecInc(( ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) >> CCFG_EXT_LF_CLK_RTC_INCREMENT_S ); + IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S, + IOC_PORT_AON_CLK32K, + IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis + // Set XOSC_LF in bypass mode to allow external 32 kHz clock + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS; + // Fall through to set XOSC_LF as SCLK_LF source + case 2 : // XOSC_LF -> SLCK_LF (32768 Hz) + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF ); + break; + default : // (=3) RCOSC_LF + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF ); + break; + } + + // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1 + HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) = + ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >> + FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) << + ADI_4_AUX_ADCREF1_VTRIM_S ) & + ADI_4_AUX_ADCREF1_VTRIM_M ); + + // Sync with AON + SysCtrlAonSync(); +} + +//***************************************************************************** +// +// SetupGetTrimForAnabypassValue1 +// +//***************************************************************************** +uint32_t +SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ) +{ + uint32_t ui32Fcfg1Value ; + uint32_t ui32XoscHfRow ; + uint32_t ui32XoscHfCol ; + uint32_t ui32TrimValue ; + + // Use device specific trim values located in factory configuration + // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in + // the ANABYPASS_VALUE1 register. Value for the other bit fields + // are set to 0. + + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP); + ui32XoscHfRow = (( ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S ); + ui32XoscHfCol = (( ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S ); + + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) { + // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation + // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg + // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by + // a define and sign extension must therefore be hard coded. + // ( A small test program is created verifying the code lines below: + // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c) + int32_t i32CustomerDeltaAdjust = + (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ))) + >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W )); + + while ( i32CustomerDeltaAdjust < 0 ) { + ui32XoscHfCol >>= 1; // COL 1 step down + if ( ui32XoscHfCol == 0 ) { // if COL below minimum + ui32XoscHfCol = 0xFFFF; // Set COL to maximum + ui32XoscHfRow >>= 1; // ROW 1 step down + if ( ui32XoscHfRow == 0 ) { // if ROW below minimum + ui32XoscHfRow = 1; // Set both ROW and COL + ui32XoscHfCol = 1; // to minimum + } + } + i32CustomerDeltaAdjust++; + } + while ( i32CustomerDeltaAdjust > 0 ) { + ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up + if ( ui32XoscHfCol > 0xFFFF ) { // if COL above maximum + ui32XoscHfCol = 1; // Set COL to minimum + ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up + if ( ui32XoscHfRow > 0xF ) { // if ROW above maximum + ui32XoscHfRow = 0xF; // Set both ROW and COL + ui32XoscHfCol = 0xFFFF; // to maximum + } + } + i32CustomerDeltaAdjust--; + } + } + + ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) | + ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) ); + + return (ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForRcOscLfRtuneCtuneTrim +// +//***************************************************************************** +uint32_t +SetupGetTrimForRcOscLfRtuneCtuneTrim( void ) +{ + uint32_t ui32TrimValue; + + // Use device specific trim values located in factory configuration + // area + ui32TrimValue = + ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<< + DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S; + + ui32TrimValue |= + ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<< + DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S; + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscHfIbiastherm +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscHfIbiastherm( void ) +{ + uint32_t ui32TrimValue; + + // Use device specific trim value located in factory configuration + // area + ui32TrimValue = + (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) & + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>> + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S; + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForAmpcompTh2 +// +//***************************************************************************** +uint32_t +SetupGetTrimForAmpcompTh2( void ) +{ + uint32_t ui32TrimValue; + uint32_t ui32Fcfg1Value; + + // Use device specific trim value located in factory configuration + // area. All defined register bit fields have corresponding trim + // value in the factory configuration area + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2); + ui32TrimValue = ((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>> + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<< + DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S; + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>> + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<< + DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<< + DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<< + DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S); + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForAmpcompTh1 +// +//***************************************************************************** +uint32_t +SetupGetTrimForAmpcompTh1( void ) +{ + uint32_t ui32TrimValue; + uint32_t ui32Fcfg1Value; + + // Use device specific trim values located in factory configuration + // area. All defined register bit fields have a corresponding trim + // value in the factory configuration area + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1); + ui32TrimValue = (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>> + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<< + DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S); + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForAmpcompCtrl +// +//***************************************************************************** +uint32_t +SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ) +{ + uint32_t ui32TrimValue ; + uint32_t ui32Fcfg1Value ; + uint32_t ibiasOffset ; + uint32_t ibiasInit ; + uint32_t modeConf1 ; + int32_t deltaAdjust ; + + // Use device specific trim values located in factory configuration + // area. Register bit fields without trim values in the factory + // configuration area will be set to the value of 0. + ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 ); + + ibiasOffset = ( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ; + ibiasInit = ( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ; + + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) { + // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG + modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ); + + // Both fields are signed 4-bit values. This is an assumption when doing the sign extension. + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W )); + deltaAdjust += (int32_t)ibiasOffset; + if ( deltaAdjust < 0 ) { + deltaAdjust = 0; + } + if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) { + deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ); + } + ibiasOffset = (uint32_t)deltaAdjust; + + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W )); + deltaAdjust += (int32_t)ibiasInit; + if ( deltaAdjust < 0 ) { + deltaAdjust = 0; + } + if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) { + deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ); + } + ibiasInit = (uint32_t)deltaAdjust; + } + ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) | + ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ; + + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>> + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<< + DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>> + FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<< + DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>> + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<< + DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S); + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + ui32TrimValue |= ((( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >> + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) << + DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S ); + } + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForDblrLoopFilterResetVoltage +// +//***************************************************************************** +uint32_t +SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ) +{ + uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) & + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >> + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S; + } + + return ( dblrLoopFilterResetVoltageValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForAdcShModeEn +// +//***************************************************************************** +uint32_t +SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForAdcShModeEnValue = 1; // Recommended default setting + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >> + FCFG1_OSC_CONF_ADC_SH_MODE_EN_S; + } + + return ( getTrimForAdcShModeEnValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForAdcShVbufEn +// +//***************************************************************************** +uint32_t +SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForAdcShVbufEnValue = 1; // Recommended default setting + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >> + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S; + } + + return ( getTrimForAdcShVbufEnValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscHfCtl +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForXoschfCtlValue = 0; // Recommended default setting + uint32_t fcfg1Data; + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); + getTrimForXoschfCtlValue = + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S); + + getTrimForXoschfCtlValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S); + + getTrimForXoschfCtlValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S); + } + + return ( getTrimForXoschfCtlValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscHfFastStart +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscHfFastStart( void ) +{ + uint32_t ui32XoscHfFastStartValue ; + + // Get value from FCFG1 + ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >> + FCFG1_OSC_CONF_XOSC_HF_FAST_START_S; + + return ( ui32XoscHfFastStartValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForRadcExtCfg +// +//***************************************************************************** +uint32_t +SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommended default setting + uint32_t fcfg1Data; + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); + getTrimForRadcExtCfgValue = + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >> + FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) << + DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S); + + getTrimForRadcExtCfgValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >> + FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) << + DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S); + + getTrimForRadcExtCfgValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >> + FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) << + DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S); + } + + return ( getTrimForRadcExtCfgValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForRcOscLfIBiasTrim +// +//***************************************************************************** +uint32_t +SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ) +{ + uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >> + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ; + } + + return ( trimForRcOscLfIBiasTrimValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ) +{ + uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M | + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >> + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ; + } + + return ( trimForXoscLfRegulatorAndCmirrwrRatioValue ); +} + +//***************************************************************************** +// +// SetupSetCacheModeAccordingToCcfgSetting +// +//***************************************************************************** +void +SetupSetCacheModeAccordingToCcfgSetting( void ) +{ + // - Make sure to enable aggressive VIMS clock gating for power optimization + // Only for PG2 devices. + // - Enable cache prefetch enable as default setting + // (Slightly higher power consumption, but higher CPU performance) + // - IF ( CCFG_..._DIS_GPRAM == 1 ) + // then: Enable cache (set cache mode = 1), even if set by ROM boot code + // (This is done because it's not set by boot code when running inside + // a debugger supporting the Halt In Boot (HIB) functionality). + // else: Set MODE_GPRAM if not already set (see inline comments as well) + uint32_t vimsCtlMode0 ; + + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for an eventual ongoing mode change to complete. + // (There should typically be no wait time here, but need to be sure) + } + + // Note that Mode=0 is equal to MODE_GPRAM + vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M ); + + + if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) { + // Enable cache (and hence disable GPRAM) + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE ); + } else if (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_GPRAM ) { + // GPRAM is enabled in CCFG but not selected + // Note: It is recommended to go via MODE_OFF when switching to MODE_GPRAM + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_OFF ); + while (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_OFF ) { + // Do nothing - wait for an eventual mode change to complete (This goes fast). + } + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + } else { + // Correct mode, but make sure PREF_EN and DYN_CG_EN always are set + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + } +} + +//***************************************************************************** +// +// SetupSetAonRtcSubSecInc +// +//***************************************************************************** +void +SetupSetAonRtcSubSecInc( uint32_t subSecInc ) +{ + // Loading a new RTCSUBSECINC value is done in 5 steps: + // 1. Write bit[15:0] of new SUBSECINC value to AUX_WUC_O_RTCSUBSECINC0 + // 2. Write bit[23:16] of new SUBSECINC value to AUX_WUC_O_RTCSUBSECINC1 + // 3. Set AUX_WUC_RTCSUBSECINCCTL_UPD_REQ + // 4. Wait for AUX_WUC_RTCSUBSECINCCTL_UPD_ACK + // 5. Clear AUX_WUC_RTCSUBSECINCCTL_UPD_REQ + HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC0 ) = (( subSecInc ) & AUX_WUC_RTCSUBSECINC0_INC15_0_M ); + HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_WUC_RTCSUBSECINC1_INC23_16_M ); + + HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL ) = AUX_WUC_RTCSUBSECINCCTL_UPD_REQ; + while( ! ( HWREGBITW( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL, AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN ))); + HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL ) = 0; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom.h new file mode 100644 index 0000000..43cfc38 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom.h @@ -0,0 +1,467 @@ +/****************************************************************************** +* Filename: setup_rom.h +* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) +* Revision: 52993 +* +* Description: Prototypes and defines for the setup API. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup setup_rom_api +//! @{ +// +//***************************************************************************** + +#ifndef __SETUP_ROM_H__ +#define __SETUP_ROM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +// Hardware headers +#include "../inc/hw_types.h" +// Driverlib headers +// - None needed + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn + #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn + #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl + #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 + #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 + #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 + #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage + #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg + #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim + #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl + #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart + #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm + #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting + #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc + #define SetupSetVddrLevel NOROM_SetupSetVddrLevel +#endif + +//***************************************************************************** +// +//! \brief First part of configuration required after cold reset and when waking up from shutdown. +//! +//! Configures the following based on settings in CCFG (Customer Configuration area: +//! - Boost mode for CC13xx devices +//! - Minimal VDDR voltage threshold used during sleep mode +//! - DCDC functionality: +//! - Selects if DCDC or GLDO regulator will be used for VDDR in active mode +//! - Selects if DCDC or GLDO regulator will be used for VDDR in sleep mode +//! +//! In addition the battery monitor low limit for internal regulator mode is set +//! to a hard coded value. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return None +// +//***************************************************************************** +extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Second part of configuration required after cold reset and when waking up from shutdown. +//! +//! Configures and trims functionalites required for use of XOSC_HF. +//! The configurations and trimmings are based on settings in FCFG1 (Factory +//! Configuration area) and partly on \c ccfg_ModeConfReg. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return None +// +//***************************************************************************** +extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Third part of configuration required after cold reset and when waking up from shutdown. +//! +//! Configures the following: +//! - XOSC source selection based on \c ccfg_ModeConfReg. If HPOSC is selected on a +//! HPOSC device the oscillator is configured based on settings in FCFG1 (Factory +//! Configuration area). +//! - Clock loss detection is disabled. Will be re-enabled by TIRTOS power driver. +//! - Duration of the XOSC_HF fast startup mode based on FCFG1 setting. +//! - SCLK_LF based on \c ccfg_ModeConfReg. +//! - Output voltage of ADC fixed reference based on FCFG1 setting. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return None +// +//***************************************************************************** +extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAmpcompTh1( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAmpcompTh2( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the +//! RCOSCLF_CTUNE_TRIM bit fields in the XOSCLF_RCOSCLF_CTRL register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscHfFastStart( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in +//! the ANABYPASS_VALUE2 register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscHfIbiastherm( void ); + +//***************************************************************************** +// +//! \brief Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet +//! spanning bits [5:0] in the returned value. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) +//! +//! \param ui32VddrTrimVal +//! +//! \return Returns Sign extended VDDR_TRIM setting. +// +//***************************************************************************** +__STATIC_INLINE int32_t +SetupSignExtendVddrTrimValue( uint32_t ui32VddrTrimVal ) +{ + // The VDDR trim value is 5 bits representing the range from -10 to +21 + // (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15) + int32_t i32SignedVddrVal = ui32VddrTrimVal; + if ( i32SignedVddrVal > 0x15 ) { + i32SignedVddrVal -= 0x20; + } + return ( i32SignedVddrVal ); +} + +//***************************************************************************** +// +//! \brief Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM) +//! +//! \return None +// +//***************************************************************************** +extern void SetupSetCacheModeAccordingToCcfgSetting( void ); + +//***************************************************************************** +// +//! \brief Doing the tricky stuff needed to enter new RTCSUBSECINC value +//! +//! \param subSecInc +//! +//! \return None +// +//***************************************************************************** +extern void SetupSetAonRtcSubSecInc( uint32_t subSecInc ); + +//***************************************************************************** +// +//! \brief Set VDDR boost mode (by setting VDDR_TRIM to FCFG1..VDDR_TRIM_HH and +//! setting VDDS_BOD to max). +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return None +// +//***************************************************************************** +extern void SetupSetVddrLevel( uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #undef SetupAfterColdResetWakeupFromShutDownCfg1 + #define SetupAfterColdResetWakeupFromShutDownCfg1 ROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #endif + #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #undef SetupAfterColdResetWakeupFromShutDownCfg2 + #define SetupAfterColdResetWakeupFromShutDownCfg2 ROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #endif + #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #undef SetupAfterColdResetWakeupFromShutDownCfg3 + #define SetupAfterColdResetWakeupFromShutDownCfg3 ROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #endif + #ifdef ROM_SetupGetTrimForAdcShModeEn + #undef SetupGetTrimForAdcShModeEn + #define SetupGetTrimForAdcShModeEn ROM_SetupGetTrimForAdcShModeEn + #endif + #ifdef ROM_SetupGetTrimForAdcShVbufEn + #undef SetupGetTrimForAdcShVbufEn + #define SetupGetTrimForAdcShVbufEn ROM_SetupGetTrimForAdcShVbufEn + #endif + #ifdef ROM_SetupGetTrimForAmpcompCtrl + #undef SetupGetTrimForAmpcompCtrl + #define SetupGetTrimForAmpcompCtrl ROM_SetupGetTrimForAmpcompCtrl + #endif + #ifdef ROM_SetupGetTrimForAmpcompTh1 + #undef SetupGetTrimForAmpcompTh1 + #define SetupGetTrimForAmpcompTh1 ROM_SetupGetTrimForAmpcompTh1 + #endif + #ifdef ROM_SetupGetTrimForAmpcompTh2 + #undef SetupGetTrimForAmpcompTh2 + #define SetupGetTrimForAmpcompTh2 ROM_SetupGetTrimForAmpcompTh2 + #endif + #ifdef ROM_SetupGetTrimForAnabypassValue1 + #undef SetupGetTrimForAnabypassValue1 + #define SetupGetTrimForAnabypassValue1 ROM_SetupGetTrimForAnabypassValue1 + #endif + #ifdef ROM_SetupGetTrimForDblrLoopFilterResetVoltage + #undef SetupGetTrimForDblrLoopFilterResetVoltage + #define SetupGetTrimForDblrLoopFilterResetVoltage ROM_SetupGetTrimForDblrLoopFilterResetVoltage + #endif + #ifdef ROM_SetupGetTrimForRadcExtCfg + #undef SetupGetTrimForRadcExtCfg + #define SetupGetTrimForRadcExtCfg ROM_SetupGetTrimForRadcExtCfg + #endif + #ifdef ROM_SetupGetTrimForRcOscLfIBiasTrim + #undef SetupGetTrimForRcOscLfIBiasTrim + #define SetupGetTrimForRcOscLfIBiasTrim ROM_SetupGetTrimForRcOscLfIBiasTrim + #endif + #ifdef ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #undef SetupGetTrimForRcOscLfRtuneCtuneTrim + #define SetupGetTrimForRcOscLfRtuneCtuneTrim ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #endif + #ifdef ROM_SetupGetTrimForXoscHfCtl + #undef SetupGetTrimForXoscHfCtl + #define SetupGetTrimForXoscHfCtl ROM_SetupGetTrimForXoscHfCtl + #endif + #ifdef ROM_SetupGetTrimForXoscHfFastStart + #undef SetupGetTrimForXoscHfFastStart + #define SetupGetTrimForXoscHfFastStart ROM_SetupGetTrimForXoscHfFastStart + #endif + #ifdef ROM_SetupGetTrimForXoscHfIbiastherm + #undef SetupGetTrimForXoscHfIbiastherm + #define SetupGetTrimForXoscHfIbiastherm ROM_SetupGetTrimForXoscHfIbiastherm + #endif + #ifdef ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #endif + #ifdef ROM_SetupSetCacheModeAccordingToCcfgSetting + #undef SetupSetCacheModeAccordingToCcfgSetting + #define SetupSetCacheModeAccordingToCcfgSetting ROM_SetupSetCacheModeAccordingToCcfgSetting + #endif + #ifdef ROM_SetupSetAonRtcSubSecInc + #undef SetupSetAonRtcSubSecInc + #define SetupSetAonRtcSubSecInc ROM_SetupSetAonRtcSubSecInc + #endif + #ifdef ROM_SetupSetVddrLevel + #undef SetupSetVddrLevel + #define SetupSetVddrLevel ROM_SetupSetVddrLevel + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SETUP_ROM_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom_doc.h new file mode 100644 index 0000000..bafcf07 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom_doc.h @@ -0,0 +1,44 @@ +/****************************************************************************** +* Filename: setup_rom_doc.h +* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) +* Revision: 49096 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup setup_rom_api +//! @{ +//! +//! This module contains functions from the Setup API which are likely to be in ROM. +//! +//! \note Do not use functions from this module directly! This module is only to be used by +//! SetupTrimDevice(). +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph.c new file mode 100644 index 0000000..84df1f3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph.c @@ -0,0 +1,101 @@ +/****************************************************************************** +* Filename: smph.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the MCU Semaphore. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "smph.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SMPHAcquire + #define SMPHAcquire NOROM_SMPHAcquire +#endif + +//***************************************************************************** +// +// Acquire a semaphore +// +//***************************************************************************** +void +SMPHAcquire(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // Wait for semaphore to be release such that it can be claimed + // Semaphore register reads 1 when lock was acquired otherwise 0 + // (i.e. SMPH_CLAIMED). + while(HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) == + SMPH_CLAIMED) + { + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph.h new file mode 100644 index 0000000..636979d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph.h @@ -0,0 +1,312 @@ +/****************************************************************************** +* Filename: smph.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the MCU Semaphore. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup mcusemaphore_api +//! @{ +// +//***************************************************************************** + +#ifndef __SMPH_H__ +#define __SMPH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_smph.h" +#include "../inc/hw_memmap.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SMPHAcquire NOROM_SMPHAcquire +#endif + +//***************************************************************************** +// +// General constants and defines +// +//***************************************************************************** +#define SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed + +//***************************************************************************** +// +// Values that can be passed to SMPHAcquire, SMPHTryAcquire and SMPHRelease +// as the ui32Semaphore parameter. +// +//***************************************************************************** +#define SMPH_0 0 // MCU Semaphore 0 +#define SMPH_1 1 // MCU Semaphore 1 +#define SMPH_2 2 // MCU Semaphore 2 +#define SMPH_3 3 // MCU Semaphore 3 +#define SMPH_4 4 // MCU Semaphore 4 +#define SMPH_5 5 // MCU Semaphore 5 +#define SMPH_6 6 // MCU Semaphore 6 +#define SMPH_7 7 // MCU Semaphore 7 +#define SMPH_8 8 // MCU Semaphore 8 +#define SMPH_9 9 // MCU Semaphore 9 +#define SMPH_10 10 // MCU Semaphore 10 +#define SMPH_11 11 // MCU Semaphore 11 +#define SMPH_12 12 // MCU Semaphore 12 +#define SMPH_13 13 // MCU Semaphore 13 +#define SMPH_14 14 // MCU Semaphore 14 +#define SMPH_15 15 // MCU Semaphore 15 +#define SMPH_16 16 // MCU Semaphore 16 +#define SMPH_17 17 // MCU Semaphore 17 +#define SMPH_18 18 // MCU Semaphore 18 +#define SMPH_19 19 // MCU Semaphore 19 +#define SMPH_20 20 // MCU Semaphore 20 +#define SMPH_21 21 // MCU Semaphore 21 +#define SMPH_22 22 // MCU Semaphore 22 +#define SMPH_23 23 // MCU Semaphore 23 +#define SMPH_24 24 // MCU Semaphore 24 +#define SMPH_25 25 // MCU Semaphore 25 +#define SMPH_26 26 // MCU Semaphore 26 +#define SMPH_27 27 // MCU Semaphore 27 +#define SMPH_28 28 // MCU Semaphore 28 +#define SMPH_29 29 // MCU Semaphore 29 +#define SMPH_30 30 // MCU Semaphore 30 +#define SMPH_31 31 // MCU Semaphore 31 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Acquire a semaphore. +//! +//! This function acquires the given semaphore, blocking the call until +//! the semaphore is available. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref SMPH_0 +//! - \ref SMPH_1 +//! - ... +//! - \ref SMPH_31 +//! +//! \return None +// +//***************************************************************************** +extern void SMPHAcquire(uint32_t ui32Semaphore); + +//***************************************************************************** +// +//! \brief Try to Acquire a semaphore. +//! +//! This function tries to acquire the given semaphore, if the semaphore +//! could not be claimed the function returns false. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref SMPH_0 +//! - \ref SMPH_1 +//! - ... +//! - \ref SMPH_31 +//! +//! \return Returns if a semaphore was acquired +//! - \c true : Semaphore acquired. +//! - \c false : Semaphore \b not acquired. +// +//***************************************************************************** +__STATIC_INLINE bool +SMPHTryAcquire(uint32_t ui32Semaphore) +{ + uint32_t ui32SemaReg; + + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // Semaphore register reads 1 if lock was acquired + // (i.e. SMPH_FREE). + ui32SemaReg = HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore); + + return (ui32SemaReg == SMPH_FREE); +} + +//***************************************************************************** +// +//! \brief Release a semaphore. +//! +//! This function releases the given semaphore. +//! +//! \note It is up to the application to provide the convention for clearing +//! semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref SMPH_0 +//! - \ref SMPH_1 +//! - ... +//! - \ref SMPH_31 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SMPHRelease(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // No check before release, it is up to the application to provide the + // conventions for who and when a semaphore can be released. + HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) = SMPH_FREE; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SMPHAcquire + #undef SMPHAcquire + #define SMPHAcquire ROM_SMPHAcquire + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SMPH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph_doc.h new file mode 100644 index 0000000..c66ef84 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph_doc.h @@ -0,0 +1,57 @@ +/****************************************************************************** +* Filename: smph_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup mcusemaphore_api +//! @{ +//! \section sec_mcusemaphore Introduction +//! +//! The MCU Semaphore offers 32 semaphores that each can be claimed and released in an atomic operation. +//! One and only one semaphore can be handled during a transaction. +//! +//! Claiming a semaphore causes subsequent claims/reads to return '0' (i.e. "not available"). +//! How the semaphores are used and respected is decided by software. +//! +//! \section sec_mcusemaphore_api API +//! +//! The API functions can be grouped like this: +//! +//! Semaphore acquire: +//! - \ref SMPHAcquire() +//! - \ref SMPHTryAcquire() +//! +//! Semaphore release: +//! - \ref SMPHRelease() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ssi.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ssi.c new file mode 100644 index 0000000..76fc8e7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ssi.c @@ -0,0 +1,253 @@ +/****************************************************************************** +* Filename: ssi.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for Synchronous Serial Interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ssi.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SSIConfigSetExpClk + #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk + #undef SSIDataPut + #define SSIDataPut NOROM_SSIDataPut + #undef SSIDataPutNonBlocking + #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking + #undef SSIDataGet + #define SSIDataGet NOROM_SSIDataGet + #undef SSIDataGetNonBlocking + #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking + #undef SSIIntRegister + #define SSIIntRegister NOROM_SSIIntRegister + #undef SSIIntUnregister + #define SSIIntUnregister NOROM_SSIIntUnregister +#endif + +//***************************************************************************** +// +// Configures the synchronous serial port +// +//***************************************************************************** +void +SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, uint32_t ui32DataWidth) +{ + uint32_t ui32MaxBitRate; + uint32_t ui32RegVal; + uint32_t ui32PreDiv; + uint32_t ui32SCR; + uint32_t ui32SPH_SPO; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || + (ui32Protocol == SSI_FRF_MOTO_MODE_1) || + (ui32Protocol == SSI_FRF_MOTO_MODE_2) || + (ui32Protocol == SSI_FRF_MOTO_MODE_3) || + (ui32Protocol == SSI_FRF_TI) || + (ui32Protocol == SSI_FRF_NMW)); + ASSERT((ui32Mode == SSI_MODE_MASTER) || + (ui32Mode == SSI_MODE_SLAVE) || + (ui32Mode == SSI_MODE_SLAVE_OD)); + ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) || + ((ui32Mode != SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 12)))); + ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); + ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); + + // Set the mode. + ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; + + // Set the clock predivider. + ui32MaxBitRate = ui32SSIClk / ui32BitRate; + ui32PreDiv = 0; + do + { + ui32PreDiv += 2; + ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; + } + while(ui32SCR > 255); + HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; + + // Set protocol and clock rate. + ui32SPH_SPO = (ui32Protocol & 3) << 6; + ui32Protocol &= SSI_CR0_FRF_M; + ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | (ui32DataWidth - 1); + HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; +} + +//***************************************************************************** +// +// Puts a data element into the SSI transmit FIFO +// +//***************************************************************************** +int32_t +SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // Check for space to write. + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ui32Base + SSI_O_DR) = ui32Data; + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +// Puts a data element into the SSI transmit FIFO +// +//***************************************************************************** +void +SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // Wait until there is space. + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // Write the data to the SSI. + HWREG(ui32Base + SSI_O_DR) = ui32Data; +} + +//***************************************************************************** +// +// Gets a data element from the SSI receive FIFO +// +//***************************************************************************** +void +SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Wait until there is data to be read. + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // Read data from SSI. + *pui32Data = HWREG(ui32Base + SSI_O_DR); +} + +//***************************************************************************** +// +// Gets a data element from the SSI receive FIFO +// +//***************************************************************************** +int32_t +SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Check for data to read. + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) + { + *pui32Data = HWREG(ui32Base + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +// Registers an interrupt handler for the synchronous serial port +// +//***************************************************************************** +void +SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Determine the interrupt number based on the SSI port. + ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB; + + // Register the interrupt handler. + IntRegister(ui32Int, pfnHandler); + + // Enable the synchronous serial port interrupt. + IntEnable(ui32Int); +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for the synchronous serial port +// +//***************************************************************************** +void +SSIIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Determine the interrupt number based on the SSI port. + ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB; + + // Disable the interrupt. + IntDisable(ui32Int); + + // Unregister the interrupt handler. + IntUnregister(ui32Int); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ssi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ssi.h new file mode 100644 index 0000000..87a9745 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ssi.h @@ -0,0 +1,700 @@ +/****************************************************************************** +* Filename: ssi.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and macros for the SSI. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup ssi_api +//! @{ +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "../inc/hw_ssi.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk + #define SSIDataPut NOROM_SSIDataPut + #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking + #define SSIDataGet NOROM_SSIDataGet + #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking + #define SSIIntRegister NOROM_SSIIntRegister + #define SSIIntUnregister NOROM_SSIIntUnregister +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ui32IntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half full or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or more +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that are returned from SSIStatus +// +//***************************************************************************** +#define SSI_RX_FULL 0x00000008 // Receive FIFO full +#define SSI_RX_NOT_EMPTY 0x00000004 // Receive FIFO not empty +#define SSI_TX_NOT_FULL 0x00000002 // Transmit FIFO not full +#define SSI_TX_EMPTY 0x00000001 // Transmit FIFO empty +#define SSI_STATUS_MASK 0x0000000F + +//***************************************************************************** +// +// Values that can be passed to SSIConfigSetExpClk. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). +// +//***************************************************************************** +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an SSI base address. +//! +//! This function determines if an SSI module base address is valid. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +SSIBaseValid(uint32_t ui32Base) +{ + return(ui32Base == SSI0_BASE || ui32Base == SSI1_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Configures the synchronous serial port. +//! +//! This function configures the synchronous serial port. It sets +//! the SSI protocol, mode of operation, bit rate, and data width. +//! +//! The \c ui32Protocol parameter defines the data frame format. The Motorola +//! frame formats imply the following polarity and phase configurations: +//! +//! 
+//! Polarity Phase       Mode
+//!   0       0   SSI_FRF_MOTO_MODE_0
+//!   0       1   SSI_FRF_MOTO_MODE_1
+//!   1       0   SSI_FRF_MOTO_MODE_2
+//!   1       1   SSI_FRF_MOTO_MODE_3
+//!
+//! +//! The \c ui32Mode parameter defines the operating mode of the SSI module. +//! The SSI module can operate as a master or slave; if a slave, the SSI can be +//! configured to disable output on its serial output line. +//! +//! The \c ui32BitRate parameter defines the bit rate for the SSI. This bit +//! rate must satisfy the following clock ratio criteria: +//! - Master mode : FSSI >= 2 * bit rate +//! - Slave mode : FSSI >= 12 * bit rate +//! +//! where FSSI is the frequency of the clock supplied to the SSI module. +//! +//! The \c ui32DataWidth parameter defines the width of the data transfers, and +//! can be a value between 4 and 16, inclusive. +//! +//! \note The peripheral clock is not necessarily the same as the processor clock. +//! The frequency of the peripheral clock is set by the system control. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32SSIClk is the rate of the clock supplied to the SSI module. +//! \param ui32Protocol specifies the data transfer protocol. +//! The parameter can be one of the following values: +//! - \ref SSI_FRF_MOTO_MODE_0 +//! - \ref SSI_FRF_MOTO_MODE_1 +//! - \ref SSI_FRF_MOTO_MODE_2 +//! - \ref SSI_FRF_MOTO_MODE_3 +//! - \ref SSI_FRF_TI +//! - \ref SSI_FRF_NMW. +//! \param ui32Mode specifies the mode of operation. +//! The parameter can be one of the following values: +//! - \ref SSI_MODE_MASTER +//! - \ref SSI_MODE_SLAVE +//! - \ref SSI_MODE_SLAVE_OD +//! \param ui32BitRate specifies the clock rate. +//! \param ui32DataWidth specifies number of bits transferred per frame. +//! Must be a value between 4 and 16, both included. +//! +//! \return None +// +//***************************************************************************** +extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, uint32_t ui32DataWidth); + +//***************************************************************************** +// +//! \brief Enables the synchronous serial port. +//! +//! This function enables operation of the synchronous serial port. The +//! synchronous serial port must be configured before it is enabled. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Read-modify-write the enable bit. + HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE; +} + +//***************************************************************************** +// +//! \brief Disables the synchronous serial port. +//! +//! This function disables operation of the synchronous serial port. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Read-modify-write the enable bit. + HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE); +} + +//***************************************************************************** +// +//! \brief Puts a data element into the SSI transmit FIFO. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module. +//! +//! \note The upper 32 - N bits of the \c ui32Data are discarded by the +//! hardware, where N is the data width as configured by \ref SSIConfigSetExpClk(). +//! For example, if the interface is configured for 8-bit data width, the upper +//! 24 bits of \c ui32Data are discarded. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32Data is the data to be transmitted over the SSI interface. +//! +//! \return None +// +//***************************************************************************** +extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data); + +//***************************************************************************** +// +//! \brief Puts a data element into the SSI transmit FIFO. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module. If there is no space in the FIFO, then this function +//! returns a zero. +//! +//! \note The upper 32 - N bits of the \c ui32Data are discarded by the hardware, +//! where N is the data width as configured by \ref SSIConfigSetExpClk(). For +//! example, if the interface is configured for 8-bit data width, the upper 24 +//! bits of \c ui32Data are discarded. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32Data is the data to be transmitted over the SSI interface. +//! +//! \return Returns the number of elements written to the SSI transmit FIFO. +// +//***************************************************************************** +extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data); + +//***************************************************************************** +// +//! \brief Gets a data element from the SSI receive FIFO. +//! +//! This function gets received data from the receive FIFO of the specified +//! SSI module and places that data into the location specified by the +//! \c pui32Data parameter. +//! +//! \note Only the lower N bits of the value written to \c pui32Data contain +//! valid data, where N is the data width as configured by +//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to +//! \c pui32Data contain valid data. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pui32Data is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! \return None +// +//***************************************************************************** +extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data); + +//***************************************************************************** +// +//! \brief Gets a data element from the SSI receive FIFO. +//! +//! This function gets received data from the receive FIFO of the specified SSI +//! module and places that data into the location specified by the \c ui32Data +//! parameter. If there is no data in the FIFO, then this function returns a +//! zero. +//! +//! \note Only the lower N bits of the value written to \c pui32Data contain +//! valid data, where N is the data width as configured by +//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to \c pui32Data +//! contain valid data. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pui32Data is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! \return Returns the number of elements read from the SSI receive FIFO. +// +//***************************************************************************** +extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data); + +//***************************************************************************** +// +//! \brief Determines whether the SSI transmitter is busy or not. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \c false is returned, then the transmit FIFO +//! is empty and all bits of the last transmitted word have left the hardware +//! shift register. +//! +//! \param ui32Base is the base address of the SSI port. +//! +//! \return Returns status of the SSI transmit buffer. +//! - \c true : SSI is transmitting. +//! - \c false : SSI transmissions are complete. +// +//***************************************************************************** +__STATIC_INLINE bool +SSIBusy(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Determine if the SSI is busy. + return((HWREG(ui32Base + SSI_O_SR) & SSI_SR_BSY) ? true : false); +} + +//***************************************************************************** +// +//! \brief Get the status of the SSI data buffers. +//! +//! This function is used to poll the status of the internal FIFOs in the SSI +//! module. The status of both TX and RX FIFO is returned. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return Returns the current status of the internal SSI data buffers. +//! The status is a bitwise OR'ed combination of: +//! - \ref SSI_RX_FULL : Receive FIFO full. +//! - \ref SSI_RX_NOT_EMPTY : Receive FIFO not empty. +//! - \ref SSI_TX_NOT_FULL : Transmit FIFO not full. +//! - \ref SSI_TX_EMPTY : Transmit FIFO empty. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SSIStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Return the status + return (HWREG(ui32Base + SSI_O_SR) & SSI_STATUS_MASK); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific SSI interrupts must be enabled via \ref SSIIntEnable(). If necessary, +//! it is the interrupt handler's responsibility to clear the interrupt source +//! via \ref SSIIntClear(). +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial port interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when a SSI +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void SSIIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables individual SSI interrupt sources. +//! +//! Enables the indicated SSI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. +//! - \ref SSI_TXFF +//! - \ref SSI_RXFF +//! - \ref SSI_RXTO +//! - \ref SSI_RXOR +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(ui32Base + SSI_O_IMSC) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual SSI interrupt sources. +//! +//! Disables the indicated SSI interrupt sources. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. +//! - \ref SSI_TXFF +//! - \ref SSI_RXFF +//! - \ref SSI_RXTO +//! - \ref SSI_RXOR +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(ui32Base + SSI_O_IMSC) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Clears SSI interrupt sources. +//! +//! The specified SSI interrupt sources are cleared so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupts from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter can consist of either or both of: +//! - \ref SSI_RXTO : Timeout interrupt. +//! - \ref SSI_RXOR : Overrun interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Clear the requested interrupt sources. + HWREG(ui32Base + SSI_O_ICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the SSI module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param bMasked selects either raw or masked interrupt. +//! \c false : Raw interrupt status is required. +//! \c true : Masked interrupt status is required. +//! +//! \return Returns the current interrupt status as an OR'ed combination of: +//! - \ref SSI_TXFF +//! - \ref SSI_RXFF +//! - \ref SSI_RXTO +//! - \ref SSI_RXOR +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SSIIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return(HWREG(ui32Base + SSI_O_MIS)); + } + else + { + return(HWREG(ui32Base + SSI_O_RIS)); + } +} + +//***************************************************************************** +// +//! \brief Enable SSI DMA operation. +//! +//! The specified SSI DMA features are enabled. The SSI can be +//! configured to use DMA for transmit and/or receive data transfers. +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the SSI. +//! +//! \param ui32Base is the base address of the SSI port. +//! \param ui32DMAFlags is a bit mask of the DMA features to enable. +//! The parameter is the bitwise OR of any of the following values: +//! - \ref SSI_DMA_RX : Enable DMA for receive. +//! - \ref SSI_DMA_TX : Enable DMA for transmit. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Set the requested bits in the SSI DMA control register. + HWREG(ui32Base + SSI_O_DMACR) |= ui32DMAFlags; +} + +//***************************************************************************** +// +//! \brief Disable SSI DMA operation. +//! +//! This function is used to disable SSI DMA features that were enabled +//! by \ref SSIDMAEnable(). The specified SSI DMA features are disabled. +//! +//! \param ui32Base is the base address of the SSI port. +//! \param ui32DMAFlags is a bit mask of the DMA features to disable. +//! The parameter is the bitwise OR of any of the following values: +//! - \ref SSI_DMA_RX : Disable DMA for receive. +//! - \ref SSI_DMA_TX : Disable DMA for transmit. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Clear the requested bits in the SSI DMA control register. + HWREG(ui32Base + SSI_O_DMACR) &= ~ui32DMAFlags; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SSIConfigSetExpClk + #undef SSIConfigSetExpClk + #define SSIConfigSetExpClk ROM_SSIConfigSetExpClk + #endif + #ifdef ROM_SSIDataPut + #undef SSIDataPut + #define SSIDataPut ROM_SSIDataPut + #endif + #ifdef ROM_SSIDataPutNonBlocking + #undef SSIDataPutNonBlocking + #define SSIDataPutNonBlocking ROM_SSIDataPutNonBlocking + #endif + #ifdef ROM_SSIDataGet + #undef SSIDataGet + #define SSIDataGet ROM_SSIDataGet + #endif + #ifdef ROM_SSIDataGetNonBlocking + #undef SSIDataGetNonBlocking + #define SSIDataGetNonBlocking ROM_SSIDataGetNonBlocking + #endif + #ifdef ROM_SSIIntRegister + #undef SSIIntRegister + #define SSIIntRegister ROM_SSIIntRegister + #endif + #ifdef ROM_SSIIntUnregister + #undef SSIIntUnregister + #define SSIIntUnregister ROM_SSIIntUnregister + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_chacha.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_chacha.c new file mode 100644 index 0000000..50f46c8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_chacha.c @@ -0,0 +1,121 @@ +/****************************************************************************** +* Filename: sw_chacha.c +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* +chacha-ref.c version 20080118 +D. J. Bernstein +Public domain. +*/ + +#define ECRYPT_LITTLE_ENDIAN + +#include "sw_ecrypt-sync.h" + +#define ROTATE(v,c) (ROTL32(v,c)) +#define XOR(v,w) ((v) ^ (w)) +#define PLUS(v,w) (U32V((v) + (w))) +#define PLUSONE(v) (PLUS((v),1)) + +#define QUARTERROUND(a,b,c,d) \ + x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]),16); \ + x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]),12); \ + x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]), 8); \ + x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]), 7); + +static void salsa20_wordtobyte(u8 output[64],const u32 input[16]) +{ + u32 x[16]; + int i; + + for (i = 0;i < 16;++i) x[i] = input[i]; + for (i = 8;i > 0;i -= 2) { + QUARTERROUND( 0, 4, 8,12) + QUARTERROUND( 1, 5, 9,13) + QUARTERROUND( 2, 6,10,14) + QUARTERROUND( 3, 7,11,15) + QUARTERROUND( 0, 5,10,15) + QUARTERROUND( 1, 6,11,12) + QUARTERROUND( 2, 7, 8,13) + QUARTERROUND( 3, 4, 9,14) + } + for (i = 0;i < 16;++i) x[i] = PLUS(x[i],input[i]); + for (i = 0;i < 16;++i) U32TO8_LITTLE(output + 4 * i,x[i]); +} + +void ECRYPT_init(void) +{ + return; +} + +static const char sigma[16] = "expand 32-byte k"; +static const char tau[16] = "expand 16-byte k"; + +void ECRYPT_keysetup(ECRYPT_ctx *x,const u8 *k,u32 kbits,u32 ivbits) +{ + const char *constants; + + x->input[4] = U8TO32_LITTLE(k + 0); + x->input[5] = U8TO32_LITTLE(k + 4); + x->input[6] = U8TO32_LITTLE(k + 8); + x->input[7] = U8TO32_LITTLE(k + 12); + if (kbits == 256) { /* recommended */ + k += 16; + constants = sigma; + } else { /* kbits == 128 */ + constants = tau; + } + x->input[8] = U8TO32_LITTLE(k + 0); + x->input[9] = U8TO32_LITTLE(k + 4); + x->input[10] = U8TO32_LITTLE(k + 8); + x->input[11] = U8TO32_LITTLE(k + 12); + x->input[0] = U8TO32_LITTLE(constants + 0); + x->input[1] = U8TO32_LITTLE(constants + 4); + x->input[2] = U8TO32_LITTLE(constants + 8); + x->input[3] = U8TO32_LITTLE(constants + 12); +} + +void ECRYPT_ivsetup(ECRYPT_ctx *x,const u8 *iv) +{ + x->input[12] = 0; + x->input[13] = 0; + x->input[14] = U8TO32_LITTLE(iv + 0); + x->input[15] = U8TO32_LITTLE(iv + 4); +} + +void ECRYPT_encrypt_bytes(ECRYPT_ctx *x,const u8 *m,u8 *c,u32 bytes) +{ + u8 output[64]; + int i; + + if (!bytes) return; + for (;;) { + salsa20_wordtobyte(output,x->input); + x->input[12] = PLUSONE(x->input[12]); + if (!x->input[12]) { + x->input[13] = PLUSONE(x->input[13]); + /* stopping at 2^70 bytes per nonce is user's responsibility */ + } + if (bytes <= 64) { + for (i = 0;i < bytes;++i) c[i] = m[i] ^ output[i]; + return; + } + for (i = 0;i < 64;++i) c[i] = m[i] ^ output[i]; + bytes -= 64; + c += 64; + m += 64; + } +} + +void ECRYPT_decrypt_bytes(ECRYPT_ctx *x,const u8 *c,u8 *m,u32 bytes) +{ + ECRYPT_encrypt_bytes(x,c,m,bytes); +} + +void ECRYPT_keystream_bytes(ECRYPT_ctx *x,u8 *stream,u32 bytes) +{ + u32 i; + for (i = 0;i < bytes;++i) stream[i] = 0; + ECRYPT_encrypt_bytes(x,stream,stream,bytes); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-config.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-config.h new file mode 100644 index 0000000..e8885f7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-config.h @@ -0,0 +1,279 @@ +/****************************************************************************** +* Filename: sw_ecrypt-config.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* ecrypt-config.h */ + +/* *** Normally, it should not be necessary to edit this file. *** */ + +#ifndef ECRYPT_CONFIG +#define ECRYPT_CONFIG + +/* ------------------------------------------------------------------------- */ + +/* Guess the endianness of the target architecture. */ + +/* + * The LITTLE endian machines: + */ +#if ( ! defined(ECRYPT_LITTLE_ENDIAN)) +#if defined(__ultrix) /* Older MIPS */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__alpha) /* Alpha */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_M_IX86) /* x86 (MSC, Borland) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_MSC_VER) /* x86 (surely MSC) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */ +#define ECRYPT_LITTLE_ENDIAN + +/* + * The BIG endian machines: + */ +#elif defined(sun) /* Newer Sparc's */ +#define ECRYPT_BIG_ENDIAN +#elif defined(__ppc__) /* PowerPC */ +#define ECRYPT_BIG_ENDIAN + +/* + * Finally machines with UNKNOWN endianness: + */ +#elif defined (_AIX) /* RS6000 */ +#define ECRYPT_UNKNOWN +#elif defined(__hpux) /* HP-PA */ +#define ECRYPT_UNKNOWN +#elif defined(__aux) /* 68K */ +#define ECRYPT_UNKNOWN +#elif defined(__dgux) /* 88K (but P6 in latest boxes) */ +#define ECRYPT_UNKNOWN +#elif defined(__sgi) /* Newer MIPS */ +#define ECRYPT_UNKNOWN +#else /* Any other processor */ +#define ECRYPT_UNKNOWN +#endif +#endif + +/* ------------------------------------------------------------------------- */ + +/* + * Find minimal-width types to store 8-bit, 16-bit, 32-bit, and 64-bit + * integers. + * + * Note: to enable 64-bit types on 32-bit compilers, it might be + * necessary to switch from ISO C90 mode to ISO C99 mode (e.g., gcc + * -std=c99). + */ + +#include + +/* --- check char --- */ + +#if (UCHAR_MAX / 0xFU > 0xFU) +#ifndef I8T +#define I8T char +#define U8C(v) (v##U) + +#if (UCHAR_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (UCHAR_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T char +#define U16C(v) (v##U) +#endif + +#if (UCHAR_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T char +#define U32C(v) (v##U) +#endif + +#if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T char +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check short --- */ + +#if (USHRT_MAX / 0xFU > 0xFU) +#ifndef I8T +#define I8T short +#define U8C(v) (v##U) + +#if (USHRT_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (USHRT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T short +#define U16C(v) (v##U) +#endif + +#if (USHRT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T short +#define U32C(v) (v##U) +#endif + +#if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T short +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check int --- */ + +#if (UINT_MAX / 0xFU > 0xFU) +#ifndef I8T +#define I8T int +#define U8C(v) (v##U) + +#if (ULONG_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (UINT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T int +#define U16C(v) (v##U) +#endif + +#if (UINT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T int +#define U32C(v) (v##U) +#endif + +#if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T int +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check long --- */ + +#if (ULONG_MAX / 0xFUL > 0xFUL) +#ifndef I8T +#define I8T long +#define U8C(v) (v##UL) + +#if (ULONG_MAX == 0xFFUL) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (ULONG_MAX / 0xFFUL > 0xFFUL) +#ifndef I16T +#define I16T long +#define U16C(v) (v##UL) +#endif + +#if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL) +#ifndef I32T +#define I32T long +#define U32C(v) (v##UL) +#endif + +#if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL) +#ifndef I64T +#define I64T long +#define U64C(v) (v##UL) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check long long --- */ + +#ifdef ULLONG_MAX + +#if (ULLONG_MAX / 0xFULL > 0xFULL) +#ifndef I8T +#define I8T long long +#define U8C(v) (v##ULL) + +#if (ULLONG_MAX == 0xFFULL) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (ULLONG_MAX / 0xFFULL > 0xFFULL) +#ifndef I16T +#define I16T long long +#define U16C(v) (v##ULL) +#endif + +#if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL) +#ifndef I32T +#define I32T long long +#define U32C(v) (v##ULL) +#endif + +#if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL) +#ifndef I64T +#define I64T long long +#define U64C(v) (v##ULL) +#endif + +#endif +#endif +#endif +#endif + +#endif + +/* --- check __int64 --- */ + +#ifdef _UI64_MAX + +#if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64) +#ifndef I64T +#define I64T __int64 +#define U64C(v) (v##ui64) +#endif + +#endif + +#endif + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-machine.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-machine.h new file mode 100644 index 0000000..4d2a2e5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-machine.h @@ -0,0 +1,51 @@ +/****************************************************************************** +* Filename: sw_ecrypt-machine.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* ecrypt-machine.h */ + +/* + * This file is included by 'ecrypt-portable.h'. It allows to override + * the default macros for specific platforms. Please carefully check + * the machine code generated by your compiler (with optimisations + * turned on) before deciding to edit this file. + */ + +/* ------------------------------------------------------------------------- */ + +#if (defined(ECRYPT_DEFAULT_ROT) && !defined(ECRYPT_MACHINE_ROT)) + +#define ECRYPT_MACHINE_ROT + +#if (defined(WIN32) && defined(_MSC_VER)) + +#undef ROTL32 +#undef ROTR32 +#undef ROTL64 +#undef ROTR64 + +#include + +#define ROTL32(v, n) _lrotl(v, n) +#define ROTR32(v, n) _lrotr(v, n) +#define ROTL64(v, n) _rotl64(v, n) +#define ROTR64(v, n) _rotr64(v, n) + +#endif + +#endif + +/* ------------------------------------------------------------------------- */ + +#if (defined(ECRYPT_DEFAULT_SWAP) && !defined(ECRYPT_MACHINE_SWAP)) + +#define ECRYPT_MACHINE_SWAP + +/* + * If you want to overwrite the default swap macros, put it here. And so on. + */ + +#endif + +/* ------------------------------------------------------------------------- */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-portable.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-portable.h new file mode 100644 index 0000000..8ce940d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-portable.h @@ -0,0 +1,308 @@ +/****************************************************************************** +* Filename: sw_ecrypt-portable.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* ecrypt-portable.h */ + +/* + * WARNING: the conversions defined below are implemented as macros, + * and should be used carefully. They should NOT be used with + * parameters which perform some action. E.g., the following two lines + * are not equivalent: + * + * 1) ++x; y = ROTL32(x, n); + * 2) y = ROTL32(++x, n); + */ + +/* + * *** Please do not edit this file. *** + * + * The default macros can be overridden for specific architectures by + * editing 'ecrypt-machine.h'. + */ + +#ifndef ECRYPT_PORTABLE +#define ECRYPT_PORTABLE + +#include "sw_ecrypt-config.h" + +/* ------------------------------------------------------------------------- */ + +/* + * The following types are defined (if available): + * + * u8: unsigned integer type, at least 8 bits + * u16: unsigned integer type, at least 16 bits + * u32: unsigned integer type, at least 32 bits + * u64: unsigned integer type, at least 64 bits + * + * s8, s16, s32, s64 -> signed counterparts of u8, u16, u32, u64 + * + * The selection of minimum-width integer types is taken care of by + * 'ecrypt-config.h'. Note: to enable 64-bit types on 32-bit + * compilers, it might be necessary to switch from ISO C90 mode to ISO + * C99 mode (e.g., gcc -std=c99). + */ + +#ifdef I8T +typedef signed I8T s8; +typedef unsigned I8T u8; +#endif + +#ifdef I16T +typedef signed I16T s16; +typedef unsigned I16T u16; +#endif + +#ifdef I32T +typedef signed I32T s32; +typedef unsigned I32T u32; +#endif + +#ifdef I64T +typedef signed I64T s64; +typedef unsigned I64T u64; +#endif + +/* + * The following macros are used to obtain exact-width results. + */ + +#define U8V(v) ((u8)(v) & U8C(0xFF)) +#define U16V(v) ((u16)(v) & U16C(0xFFFF)) +#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF)) +#define U64V(v) ((u64)(v) & U64C(0xFFFFFFFFFFFFFFFF)) + +/* ------------------------------------------------------------------------- */ + +/* + * The following macros return words with their bits rotated over n + * positions to the left/right. + */ + +#define ECRYPT_DEFAULT_ROT + +#define ROTL8(v, n) \ + (U8V((v) << (n)) | ((v) >> (8 - (n)))) + +#define ROTL16(v, n) \ + (U16V((v) << (n)) | ((v) >> (16 - (n)))) + +#define ROTL32(v, n) \ + (U32V((v) << (n)) | ((v) >> (32 - (n)))) + +#define ROTL64(v, n) \ + (U64V((v) << (n)) | ((v) >> (64 - (n)))) + +#define ROTR8(v, n) ROTL8(v, 8 - (n)) +#define ROTR16(v, n) ROTL16(v, 16 - (n)) +#define ROTR32(v, n) ROTL32(v, 32 - (n)) +#define ROTR64(v, n) ROTL64(v, 64 - (n)) + +#include "sw_ecrypt-machine.h" + +/* ------------------------------------------------------------------------- */ + +/* + * The following macros return a word with bytes in reverse order. + */ + +#define ECRYPT_DEFAULT_SWAP + +#define SWAP16(v) \ + ROTL16(v, 8) + +#define SWAP32(v) \ + ((ROTL32(v, 8) & U32C(0x00FF00FF)) | \ + (ROTL32(v, 24) & U32C(0xFF00FF00))) + +#ifdef ECRYPT_NATIVE64 +#define SWAP64(v) \ + ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | \ + (ROTL64(v, 24) & U64C(0x0000FF000000FF00)) | \ + (ROTL64(v, 40) & U64C(0x00FF000000FF0000)) | \ + (ROTL64(v, 56) & U64C(0xFF000000FF000000))) +#else +#define SWAP64(v) \ + (((u64)SWAP32(U32V(v)) << 32) | (u64)SWAP32(U32V(v >> 32))) +#endif + +#include "sw_ecrypt-machine.h" + +#define ECRYPT_DEFAULT_WTOW + +#ifdef ECRYPT_LITTLE_ENDIAN +#define U16TO16_LITTLE(v) (v) +#define U32TO32_LITTLE(v) (v) +#define U64TO64_LITTLE(v) (v) + +#define U16TO16_BIG(v) SWAP16(v) +#define U32TO32_BIG(v) SWAP32(v) +#define U64TO64_BIG(v) SWAP64(v) +#endif + +#ifdef ECRYPT_BIG_ENDIAN +#define U16TO16_LITTLE(v) SWAP16(v) +#define U32TO32_LITTLE(v) SWAP32(v) +#define U64TO64_LITTLE(v) SWAP64(v) + +#define U16TO16_BIG(v) (v) +#define U32TO32_BIG(v) (v) +#define U64TO64_BIG(v) (v) +#endif + +#include "sw_ecrypt-machine.h" + +/* + * The following macros load words from an array of bytes with + * different types of endianness, and vice versa. + */ + +#define ECRYPT_DEFAULT_BTOW + +#if (!defined(ECRYPT_UNKNOWN) && defined(ECRYPT_I8T_IS_BYTE)) + +#define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16*)(p))[0]) +#define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32*)(p))[0]) +#define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64*)(p))[0]) + +#define U8TO16_BIG(p) U16TO16_BIG(((u16*)(p))[0]) +#define U8TO32_BIG(p) U32TO32_BIG(((u32*)(p))[0]) +#define U8TO64_BIG(p) U64TO64_BIG(((u64*)(p))[0]) + +#define U16TO8_LITTLE(p, v) (((u16*)(p))[0] = U16TO16_LITTLE(v)) +#define U32TO8_LITTLE(p, v) (((u32*)(p))[0] = U32TO32_LITTLE(v)) +#define U64TO8_LITTLE(p, v) (((u64*)(p))[0] = U64TO64_LITTLE(v)) + +#define U16TO8_BIG(p, v) (((u16*)(p))[0] = U16TO16_BIG(v)) +#define U32TO8_BIG(p, v) (((u32*)(p))[0] = U32TO32_BIG(v)) +#define U64TO8_BIG(p, v) (((u64*)(p))[0] = U64TO64_BIG(v)) + +#else + +#define U8TO16_LITTLE(p) \ + (((u16)((p)[0]) ) | \ + ((u16)((p)[1]) << 8)) + +#define U8TO32_LITTLE(p) \ + (((u32)((p)[0]) ) | \ + ((u32)((p)[1]) << 8) | \ + ((u32)((p)[2]) << 16) | \ + ((u32)((p)[3]) << 24)) + +#ifdef ECRYPT_NATIVE64 +#define U8TO64_LITTLE(p) \ + (((u64)((p)[0]) ) | \ + ((u64)((p)[1]) << 8) | \ + ((u64)((p)[2]) << 16) | \ + ((u64)((p)[3]) << 24) | \ + ((u64)((p)[4]) << 32) | \ + ((u64)((p)[5]) << 40) | \ + ((u64)((p)[6]) << 48) | \ + ((u64)((p)[7]) << 56)) +#else +#define U8TO64_LITTLE(p) \ + ((u64)U8TO32_LITTLE(p) | ((u64)U8TO32_LITTLE((p) + 4) << 32)) +#endif + +#define U8TO16_BIG(p) \ + (((u16)((p)[0]) << 8) | \ + ((u16)((p)[1]) )) + +#define U8TO32_BIG(p) \ + (((u32)((p)[0]) << 24) | \ + ((u32)((p)[1]) << 16) | \ + ((u32)((p)[2]) << 8) | \ + ((u32)((p)[3]) )) + +#ifdef ECRYPT_NATIVE64 +#define U8TO64_BIG(p) \ + (((u64)((p)[0]) << 56) | \ + ((u64)((p)[1]) << 48) | \ + ((u64)((p)[2]) << 40) | \ + ((u64)((p)[3]) << 32) | \ + ((u64)((p)[4]) << 24) | \ + ((u64)((p)[5]) << 16) | \ + ((u64)((p)[6]) << 8) | \ + ((u64)((p)[7]) )) +#else +#define U8TO64_BIG(p) \ + (((u64)U8TO32_BIG(p) << 32) | (u64)U8TO32_BIG((p) + 4)) +#endif + +#define U16TO8_LITTLE(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + } while (0) + +#define U32TO8_LITTLE(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + (p)[2] = U8V((v) >> 16); \ + (p)[3] = U8V((v) >> 24); \ + } while (0) + +#ifdef ECRYPT_NATIVE64 +#define U64TO8_LITTLE(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + (p)[2] = U8V((v) >> 16); \ + (p)[3] = U8V((v) >> 24); \ + (p)[4] = U8V((v) >> 32); \ + (p)[5] = U8V((v) >> 40); \ + (p)[6] = U8V((v) >> 48); \ + (p)[7] = U8V((v) >> 56); \ + } while (0) +#else +#define U64TO8_LITTLE(p, v) \ + do { \ + U32TO8_LITTLE((p), U32V((v) )); \ + U32TO8_LITTLE((p) + 4, U32V((v) >> 32)); \ + } while (0) +#endif + +#define U16TO8_BIG(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + } while (0) + +#define U32TO8_BIG(p, v) \ + do { \ + (p)[0] = U8V((v) >> 24); \ + (p)[1] = U8V((v) >> 16); \ + (p)[2] = U8V((v) >> 8); \ + (p)[3] = U8V((v) ); \ + } while (0) + +#ifdef ECRYPT_NATIVE64 +#define U64TO8_BIG(p, v) \ + do { \ + (p)[0] = U8V((v) >> 56); \ + (p)[1] = U8V((v) >> 48); \ + (p)[2] = U8V((v) >> 40); \ + (p)[3] = U8V((v) >> 32); \ + (p)[4] = U8V((v) >> 24); \ + (p)[5] = U8V((v) >> 16); \ + (p)[6] = U8V((v) >> 8); \ + (p)[7] = U8V((v) ); \ + } while (0) +#else +#define U64TO8_BIG(p, v) \ + do { \ + U32TO8_BIG((p), U32V((v) >> 32)); \ + U32TO8_BIG((p) + 4, U32V((v) )); \ + } while (0) +#endif + +#endif + +#include "sw_ecrypt-machine.h" + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-sync.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-sync.h new file mode 100644 index 0000000..dddb384 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-sync.h @@ -0,0 +1,284 @@ +/****************************************************************************** +* Filename: sw_ecrypt-sync.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* ecrypt-sync.h */ + +/* + * Header file for synchronous stream ciphers without authentication + * mechanism. + * + * *** Please only edit parts marked with "[edit]". *** + */ + +#ifndef ECRYPT_SYNC +#define ECRYPT_SYNC + +#include "sw_ecrypt-portable.h" + +/* ------------------------------------------------------------------------- */ + +/* Cipher parameters */ + +/* + * The name of your cipher. + */ +#define ECRYPT_NAME "ChaCha8" +#define ECRYPT_PROFILE "_____" + +/* + * Specify which key and IV sizes are supported by your cipher. A user + * should be able to enumerate the supported sizes by running the + * following code: + * + * for (i = 0; ECRYPT_KEYSIZE(i) <= ECRYPT_MAXKEYSIZE; ++i) + * { + * keysize = ECRYPT_KEYSIZE(i); + * + * ... + * } + * + * All sizes are in bits. + */ + +#define ECRYPT_MAXKEYSIZE 256 /* [edit] */ +#define ECRYPT_KEYSIZE(i) (128 + (i)*128) /* [edit] */ + +#define ECRYPT_MAXIVSIZE 64 /* [edit] */ +#define ECRYPT_IVSIZE(i) (64 + (i)*64) /* [edit] */ + +/* ------------------------------------------------------------------------- */ + +/* Data structures */ + +/* + * ECRYPT_ctx is the structure containing the representation of the + * internal state of your cipher. + */ + +typedef struct +{ + u32 input[16]; /* could be compressed */ + /* + * [edit] + * + * Put here all state variable needed during the encryption process. + */ +} ECRYPT_ctx; + +/* ------------------------------------------------------------------------- */ + +/* Mandatory functions */ + +/* + * Key and message independent initialization. This function will be + * called once when the program starts (e.g., to build expanded S-box + * tables). + */ +void ECRYPT_init(void); + +/* + * Key setup. It is the user's responsibility to select the values of + * keysize and ivsize from the set of supported values specified + * above. + */ +void ECRYPT_keysetup( + ECRYPT_ctx* ctx, + const u8* key, + u32 keysize, /* Key size in bits. */ + u32 ivsize); /* IV size in bits. */ + +/* + * IV setup. After having called ECRYPT_keysetup(), the user is + * allowed to call ECRYPT_ivsetup() different times in order to + * encrypt/decrypt different messages with the same key but different + * IV's. + */ +void ECRYPT_ivsetup( + ECRYPT_ctx* ctx, + const u8* iv); + +/* + * Encryption/decryption of arbitrary length messages. + * + * For efficiency reasons, the API provides two types of + * encrypt/decrypt functions. The ECRYPT_encrypt_bytes() function + * (declared here) encrypts byte strings of arbitrary length, while + * the ECRYPT_encrypt_blocks() function (defined later) only accepts + * lengths which are multiples of ECRYPT_BLOCKLENGTH. + * + * The user is allowed to make multiple calls to + * ECRYPT_encrypt_blocks() to incrementally encrypt a long message, + * but he is NOT allowed to make additional encryption calls once he + * has called ECRYPT_encrypt_bytes() (unless he starts a new message + * of course). For example, this sequence of calls is acceptable: + * + * ECRYPT_keysetup(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_bytes(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_blocks(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_bytes(); + * + * The following sequence is not: + * + * ECRYPT_keysetup(); + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_bytes(); + * ECRYPT_encrypt_blocks(); + */ + +void ECRYPT_encrypt_bytes( + ECRYPT_ctx* ctx, + const u8* plaintext, + u8* ciphertext, + u32 msglen); /* Message length in bytes. */ + +void ECRYPT_decrypt_bytes( + ECRYPT_ctx* ctx, + const u8* ciphertext, + u8* plaintext, + u32 msglen); /* Message length in bytes. */ + +/* ------------------------------------------------------------------------- */ + +/* Optional features */ + +/* + * For testing purposes it can sometimes be useful to have a function + * which immediately generates keystream without having to provide it + * with a zero plaintext. If your cipher cannot provide this function + * (e.g., because it is not strictly a synchronous cipher), please + * reset the ECRYPT_GENERATES_KEYSTREAM flag. + */ + +#define ECRYPT_GENERATES_KEYSTREAM +#ifdef ECRYPT_GENERATES_KEYSTREAM + +void ECRYPT_keystream_bytes( + ECRYPT_ctx* ctx, + u8* keystream, + u32 length); /* Length of keystream in bytes. */ + +#endif + +/* ------------------------------------------------------------------------- */ + +/* Optional optimizations */ + +/* + * By default, the functions in this section are implemented using + * calls to functions declared above. However, you might want to + * implement them differently for performance reasons. + */ + +/* + * All-in-one encryption/decryption of (short) packets. + * + * The default definitions of these functions can be found in + * "ecrypt-sync.c". If you want to implement them differently, please + * undef the ECRYPT_USES_DEFAULT_ALL_IN_ONE flag. + */ +#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */ + +void ECRYPT_encrypt_packet( + ECRYPT_ctx* ctx, + const u8* iv, + const u8* plaintext, + u8* ciphertext, + u32 msglen); + +void ECRYPT_decrypt_packet( + ECRYPT_ctx* ctx, + const u8* iv, + const u8* ciphertext, + u8* plaintext, + u32 msglen); + +/* + * Encryption/decryption of blocks. + * + * By default, these functions are defined as macros. If you want to + * provide a different implementation, please undef the + * ECRYPT_USES_DEFAULT_BLOCK_MACROS flag and implement the functions + * declared below. + */ + +#define ECRYPT_BLOCKLENGTH 64 /* [edit] */ + +#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */ +#ifdef ECRYPT_USES_DEFAULT_BLOCK_MACROS + +#define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \ + ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, \ + (blocks) * ECRYPT_BLOCKLENGTH) + +#define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \ + ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, \ + (blocks) * ECRYPT_BLOCKLENGTH) + +#ifdef ECRYPT_GENERATES_KEYSTREAM + +#define ECRYPT_keystream_blocks(ctx, keystream, blocks) \ + ECRYPT_keystream_bytes(ctx, keystream, \ + (blocks) * ECRYPT_BLOCKLENGTH) + +#endif + +#else + +void ECRYPT_encrypt_blocks( + ECRYPT_ctx* ctx, + const u8* plaintext, + u8* ciphertext, + u32 blocks); /* Message length in blocks. */ + +void ECRYPT_decrypt_blocks( + ECRYPT_ctx* ctx, + const u8* ciphertext, + u8* plaintext, + u32 blocks); /* Message length in blocks. */ + +#ifdef ECRYPT_GENERATES_KEYSTREAM + +void ECRYPT_keystream_blocks( + ECRYPT_ctx* ctx, + const u8* keystream, + u32 blocks); /* Keystream length in blocks. */ + +#endif + +#endif + +/* + * If your cipher can be implemented in different ways, you can use + * the ECRYPT_VARIANT parameter to allow the user to choose between + * them at compile time (e.g., gcc -DECRYPT_VARIANT=3 ...). Please + * only use this possibility if you really think it could make a + * significant difference and keep the number of variants + * (ECRYPT_MAXVARIANT) as small as possible (definitely not more than + * 10). Note also that all variants should have exactly the same + * external interface (i.e., the same ECRYPT_BLOCKLENGTH, etc.). + */ +#define ECRYPT_MAXVARIANT 1 /* [edit] */ + +#ifndef ECRYPT_VARIANT +#define ECRYPT_VARIANT 1 +#endif + +#if (ECRYPT_VARIANT > ECRYPT_MAXVARIANT) +#error this variant does not exist +#endif + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna-32.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna-32.h new file mode 100644 index 0000000..2aa2eeb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna-32.h @@ -0,0 +1,223 @@ +/****************************************************************************** +* Filename: sw_poly1305-donna-32.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* + poly1305 implementation using 32 bit * 32 bit = 64 bit multiplication and 64 bit addition +*/ + +#if defined(_MSC_VER) + #define POLY1305_NOINLINE __declspec(noinline) +#elif defined(__GNUC__) + #define POLY1305_NOINLINE __attribute__((noinline)) +#else + #define POLY1305_NOINLINE +#endif + +#define poly1305_block_size 16 + +/* 17 + sizeof(size_t) + 14*sizeof(unsigned long) */ +typedef struct { + unsigned long r[5]; + unsigned long h[5]; + unsigned long pad[4]; + size_t leftover; + unsigned char buffer[poly1305_block_size]; + unsigned char final; +} poly1305_state_internal_t; + +/* interpret four 8 bit unsigned integers as a 32 bit unsigned integer in little endian */ +static unsigned long +U8TO32(const unsigned char *p) { + return + (((unsigned long)(p[0] & 0xff) ) | + ((unsigned long)(p[1] & 0xff) << 8) | + ((unsigned long)(p[2] & 0xff) << 16) | + ((unsigned long)(p[3] & 0xff) << 24)); +} + +/* store a 32 bit unsigned integer as four 8 bit unsigned integers in little endian */ +static void +U32TO8(unsigned char *p, unsigned long v) { + p[0] = (v ) & 0xff; + p[1] = (v >> 8) & 0xff; + p[2] = (v >> 16) & 0xff; + p[3] = (v >> 24) & 0xff; +} + +void +poly1305_init(poly1305_context *ctx, const unsigned char key[32]) { + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + + /* r &= 0xffffffc0ffffffc0ffffffc0fffffff */ + st->r[0] = (U8TO32(&key[ 0]) ) & 0x3ffffff; + st->r[1] = (U8TO32(&key[ 3]) >> 2) & 0x3ffff03; + st->r[2] = (U8TO32(&key[ 6]) >> 4) & 0x3ffc0ff; + st->r[3] = (U8TO32(&key[ 9]) >> 6) & 0x3f03fff; + st->r[4] = (U8TO32(&key[12]) >> 8) & 0x00fffff; + + /* h = 0 */ + st->h[0] = 0; + st->h[1] = 0; + st->h[2] = 0; + st->h[3] = 0; + st->h[4] = 0; + + /* save pad for later */ + st->pad[0] = U8TO32(&key[16]); + st->pad[1] = U8TO32(&key[20]); + st->pad[2] = U8TO32(&key[24]); + st->pad[3] = U8TO32(&key[28]); + + st->leftover = 0; + st->final = 0; +} + +static void +poly1305_blocks(poly1305_state_internal_t *st, const unsigned char *m, size_t bytes) { + const unsigned long hibit = (st->final) ? 0 : (1UL << 24); /* 1 << 128 */ + unsigned long r0,r1,r2,r3,r4; + unsigned long s1,s2,s3,s4; + unsigned long h0,h1,h2,h3,h4; + unsigned long long d0,d1,d2,d3,d4; + unsigned long c; + + r0 = st->r[0]; + r1 = st->r[1]; + r2 = st->r[2]; + r3 = st->r[3]; + r4 = st->r[4]; + + s1 = r1 * 5; + s2 = r2 * 5; + s3 = r3 * 5; + s4 = r4 * 5; + + h0 = st->h[0]; + h1 = st->h[1]; + h2 = st->h[2]; + h3 = st->h[3]; + h4 = st->h[4]; + + while (bytes >= poly1305_block_size) { + /* h += m[i] */ + h0 += (U8TO32(m+ 0) ) & 0x3ffffff; + h1 += (U8TO32(m+ 3) >> 2) & 0x3ffffff; + h2 += (U8TO32(m+ 6) >> 4) & 0x3ffffff; + h3 += (U8TO32(m+ 9) >> 6) & 0x3ffffff; + h4 += (U8TO32(m+12) >> 8) | hibit; + + /* h *= r */ + d0 = ((unsigned long long)h0 * r0) + ((unsigned long long)h1 * s4) + ((unsigned long long)h2 * s3) + ((unsigned long long)h3 * s2) + ((unsigned long long)h4 * s1); + d1 = ((unsigned long long)h0 * r1) + ((unsigned long long)h1 * r0) + ((unsigned long long)h2 * s4) + ((unsigned long long)h3 * s3) + ((unsigned long long)h4 * s2); + d2 = ((unsigned long long)h0 * r2) + ((unsigned long long)h1 * r1) + ((unsigned long long)h2 * r0) + ((unsigned long long)h3 * s4) + ((unsigned long long)h4 * s3); + d3 = ((unsigned long long)h0 * r3) + ((unsigned long long)h1 * r2) + ((unsigned long long)h2 * r1) + ((unsigned long long)h3 * r0) + ((unsigned long long)h4 * s4); + d4 = ((unsigned long long)h0 * r4) + ((unsigned long long)h1 * r3) + ((unsigned long long)h2 * r2) + ((unsigned long long)h3 * r1) + ((unsigned long long)h4 * r0); + + /* (partial) h %= p */ + c = (unsigned long)(d0 >> 26); h0 = (unsigned long)d0 & 0x3ffffff; + d1 += c; c = (unsigned long)(d1 >> 26); h1 = (unsigned long)d1 & 0x3ffffff; + d2 += c; c = (unsigned long)(d2 >> 26); h2 = (unsigned long)d2 & 0x3ffffff; + d3 += c; c = (unsigned long)(d3 >> 26); h3 = (unsigned long)d3 & 0x3ffffff; + d4 += c; c = (unsigned long)(d4 >> 26); h4 = (unsigned long)d4 & 0x3ffffff; + h0 += c * 5; c = (h0 >> 26); h0 = h0 & 0x3ffffff; + h1 += c; + + m += poly1305_block_size; + bytes -= poly1305_block_size; + } + + st->h[0] = h0; + st->h[1] = h1; + st->h[2] = h2; + st->h[3] = h3; + st->h[4] = h4; +} + +POLY1305_NOINLINE void +poly1305_finish(poly1305_context *ctx, unsigned char mac[16]) { + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + unsigned long h0,h1,h2,h3,h4,c; + unsigned long g0,g1,g2,g3,g4; + unsigned long long f; + unsigned long mask; + + /* process the remaining block */ + if (st->leftover) { + size_t i = st->leftover; + st->buffer[i++] = 1; + for (; i < poly1305_block_size; i++) + st->buffer[i] = 0; + st->final = 1; + poly1305_blocks(st, st->buffer, poly1305_block_size); + } + + /* fully carry h */ + h0 = st->h[0]; + h1 = st->h[1]; + h2 = st->h[2]; + h3 = st->h[3]; + h4 = st->h[4]; + + c = h1 >> 26; h1 = h1 & 0x3ffffff; + h2 += c; c = h2 >> 26; h2 = h2 & 0x3ffffff; + h3 += c; c = h3 >> 26; h3 = h3 & 0x3ffffff; + h4 += c; c = h4 >> 26; h4 = h4 & 0x3ffffff; + h0 += c * 5; c = h0 >> 26; h0 = h0 & 0x3ffffff; + h1 += c; + + /* compute h + -p */ + g0 = h0 + 5; c = g0 >> 26; g0 &= 0x3ffffff; + g1 = h1 + c; c = g1 >> 26; g1 &= 0x3ffffff; + g2 = h2 + c; c = g2 >> 26; g2 &= 0x3ffffff; + g3 = h3 + c; c = g3 >> 26; g3 &= 0x3ffffff; + g4 = h4 + c - (1UL << 26); + + /* select h if h < p, or h + -p if h >= p */ + mask = (g4 >> ((sizeof(unsigned long) * 8) - 1)) - 1; + g0 &= mask; + g1 &= mask; + g2 &= mask; + g3 &= mask; + g4 &= mask; + mask = ~mask; + h0 = (h0 & mask) | g0; + h1 = (h1 & mask) | g1; + h2 = (h2 & mask) | g2; + h3 = (h3 & mask) | g3; + h4 = (h4 & mask) | g4; + + /* h = h % (2^128) */ + h0 = ((h0 ) | (h1 << 26)) & 0xffffffff; + h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff; + h2 = ((h2 >> 12) | (h3 << 14)) & 0xffffffff; + h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff; + + /* mac = (h + pad) % (2^128) */ + f = (unsigned long long)h0 + st->pad[0] ; h0 = (unsigned long)f; + f = (unsigned long long)h1 + st->pad[1] + (f >> 32); h1 = (unsigned long)f; + f = (unsigned long long)h2 + st->pad[2] + (f >> 32); h2 = (unsigned long)f; + f = (unsigned long long)h3 + st->pad[3] + (f >> 32); h3 = (unsigned long)f; + + U32TO8(mac + 0, h0); + U32TO8(mac + 4, h1); + U32TO8(mac + 8, h2); + U32TO8(mac + 12, h3); + + /* zero out the state */ + st->h[0] = 0; + st->h[1] = 0; + st->h[2] = 0; + st->h[3] = 0; + st->h[4] = 0; + st->r[0] = 0; + st->r[1] = 0; + st->r[2] = 0; + st->r[3] = 0; + st->r[4] = 0; + st->pad[0] = 0; + st->pad[1] = 0; + st->pad[2] = 0; + st->pad[3] = 0; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna.c new file mode 100644 index 0000000..2c1680e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna.c @@ -0,0 +1,186 @@ +/****************************************************************************** +* Filename: sw_poly1305-donna.c +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ + +#include "sw_poly1305-donna.h" + +#include "sw_poly1305-donna-32.h" + +void +poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes) { + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + size_t i; + + /* handle leftover */ + if (st->leftover) { + size_t want = (poly1305_block_size - st->leftover); + if (want > bytes) + want = bytes; + for (i = 0; i < want; i++) + st->buffer[st->leftover + i] = m[i]; + bytes -= want; + m += want; + st->leftover += want; + if (st->leftover < poly1305_block_size) + return; + poly1305_blocks(st, st->buffer, poly1305_block_size); + st->leftover = 0; + } + + /* process full blocks */ + if (bytes >= poly1305_block_size) { + size_t want = (bytes & ~(poly1305_block_size - 1)); + poly1305_blocks(st, m, want); + m += want; + bytes -= want; + } + + /* store leftover */ + if (bytes) { + for (i = 0; i < bytes; i++) + st->buffer[st->leftover + i] = m[i]; + st->leftover += bytes; + } +} + +void +poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]) { + poly1305_context ctx; + poly1305_init(&ctx, key); + poly1305_update(&ctx, m, bytes); + poly1305_finish(&ctx, mac); +} + +int +poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]) { + size_t i; + unsigned int dif = 0; + for (i = 0; i < 16; i++) + dif |= (mac1[i] ^ mac2[i]); + dif = (dif - 1) >> ((sizeof(unsigned int) * 8) - 1); + return (dif & 1); +} + + +/* test a few basic operations */ +int +poly1305_power_on_self_test(void) { + /* example from nacl */ + static const unsigned char nacl_key[32] = { + 0xee,0xa6,0xa7,0x25,0x1c,0x1e,0x72,0x91, + 0x6d,0x11,0xc2,0xcb,0x21,0x4d,0x3c,0x25, + 0x25,0x39,0x12,0x1d,0x8e,0x23,0x4e,0x65, + 0x2d,0x65,0x1f,0xa4,0xc8,0xcf,0xf8,0x80 + }; + + static const unsigned char nacl_msg[131] = { + 0x8e,0x99,0x3b,0x9f,0x48,0x68,0x12,0x73, + 0xc2,0x96,0x50,0xba,0x32,0xfc,0x76,0xce, + 0x48,0x33,0x2e,0xa7,0x16,0x4d,0x96,0xa4, + 0x47,0x6f,0xb8,0xc5,0x31,0xa1,0x18,0x6a, + 0xc0,0xdf,0xc1,0x7c,0x98,0xdc,0xe8,0x7b, + 0x4d,0xa7,0xf0,0x11,0xec,0x48,0xc9,0x72, + 0x71,0xd2,0xc2,0x0f,0x9b,0x92,0x8f,0xe2, + 0x27,0x0d,0x6f,0xb8,0x63,0xd5,0x17,0x38, + 0xb4,0x8e,0xee,0xe3,0x14,0xa7,0xcc,0x8a, + 0xb9,0x32,0x16,0x45,0x48,0xe5,0x26,0xae, + 0x90,0x22,0x43,0x68,0x51,0x7a,0xcf,0xea, + 0xbd,0x6b,0xb3,0x73,0x2b,0xc0,0xe9,0xda, + 0x99,0x83,0x2b,0x61,0xca,0x01,0xb6,0xde, + 0x56,0x24,0x4a,0x9e,0x88,0xd5,0xf9,0xb3, + 0x79,0x73,0xf6,0x22,0xa4,0x3d,0x14,0xa6, + 0x59,0x9b,0x1f,0x65,0x4c,0xb4,0x5a,0x74, + 0xe3,0x55,0xa5 + }; + + static const unsigned char nacl_mac[16] = { + 0xf3,0xff,0xc7,0x70,0x3f,0x94,0x00,0xe5, + 0x2a,0x7d,0xfb,0x4b,0x3d,0x33,0x05,0xd9 + }; + + /* generates a final value of (2^130 - 2) == 3 */ + static const unsigned char wrap_key[32] = { + 0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + }; + + static const unsigned char wrap_msg[16] = { + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff + }; + + static const unsigned char wrap_mac[16] = { + 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + }; + + /* + mac of the macs of messages of length 0 to 256, where the key and messages + have all their values set to the length + */ + static const unsigned char total_key[32] = { + 0x01,0x02,0x03,0x04,0x05,0x06,0x07, + 0xff,0xfe,0xfd,0xfc,0xfb,0xfa,0xf9, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff + }; + + static const unsigned char total_mac[16] = { + 0x64,0xaf,0xe2,0xe8,0xd6,0xad,0x7b,0xbd, + 0xd2,0x87,0xf9,0x7c,0x44,0x62,0x3d,0x39 + }; + + poly1305_context ctx; + poly1305_context total_ctx; + unsigned char all_key[32]; + unsigned char all_msg[256]; + unsigned char mac[16]; + size_t i, j; + int result = 1; + + for (i = 0; i < sizeof(mac); i++) + mac[i] = 0; + poly1305_auth(mac, nacl_msg, sizeof(nacl_msg), nacl_key); + result &= poly1305_verify(nacl_mac, mac); + + for (i = 0; i < sizeof(mac); i++) + mac[i] = 0; + poly1305_init(&ctx, nacl_key); + poly1305_update(&ctx, nacl_msg + 0, 32); + poly1305_update(&ctx, nacl_msg + 32, 64); + poly1305_update(&ctx, nacl_msg + 96, 16); + poly1305_update(&ctx, nacl_msg + 112, 8); + poly1305_update(&ctx, nacl_msg + 120, 4); + poly1305_update(&ctx, nacl_msg + 124, 2); + poly1305_update(&ctx, nacl_msg + 126, 1); + poly1305_update(&ctx, nacl_msg + 127, 1); + poly1305_update(&ctx, nacl_msg + 128, 1); + poly1305_update(&ctx, nacl_msg + 129, 1); + poly1305_update(&ctx, nacl_msg + 130, 1); + poly1305_finish(&ctx, mac); + result &= poly1305_verify(nacl_mac, mac); + + for (i = 0; i < sizeof(mac); i++) + mac[i] = 0; + poly1305_auth(mac, wrap_msg, sizeof(wrap_msg), wrap_key); + result &= poly1305_verify(wrap_mac, mac); + + poly1305_init(&total_ctx, total_key); + for (i = 0; i < 256; i++) { + /* set key and message to 'i,i,i..' */ + for (j = 0; j < sizeof(all_key); j++) + all_key[j] = i; + for (j = 0; j < i; j++) + all_msg[j] = i; + poly1305_auth(mac, all_msg, i, all_key); + poly1305_update(&total_ctx, mac, 16); + } + poly1305_finish(&total_ctx, mac); + result &= poly1305_verify(total_mac, mac); + + return result; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna.h new file mode 100644 index 0000000..574efab --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna.h @@ -0,0 +1,25 @@ +/****************************************************************************** +* Filename: sw_poly1305-donna.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ + +#ifndef POLY1305_DONNA_H +#define POLY1305_DONNA_H + +#include + +typedef struct { + size_t aligner; + unsigned char opaque[136]; +} poly1305_context; + +void poly1305_init(poly1305_context *ctx, const unsigned char key[32]); +void poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes); +void poly1305_finish(poly1305_context *ctx, unsigned char mac[16]); +void poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]); + +int poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]); +int poly1305_power_on_self_test(void); + +#endif /* POLY1305_DONNA_H */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sys_ctrl.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sys_ctrl.c new file mode 100644 index 0000000..a4b53cf --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sys_ctrl.c @@ -0,0 +1,434 @@ +/****************************************************************************** +* Filename: sys_ctrl.c +* Revised: 2018-06-26 15:19:11 +0200 (Tue, 26 Jun 2018) +* Revision: 52220 +* +* Description: Driver for the System Control. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +// Hardware headers +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +// Driverlib headers +#include "aon_batmon.h" +#include "setup_rom.h" +#include "sys_ctrl.h" + + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SysCtrlSetRechargeBeforePowerDown + #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown + #undef SysCtrlAdjustRechargeAfterPowerDown + #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown + #undef SysCtrl_DCDC_VoltageConditionalControl + #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl + #undef SysCtrlResetSourceGet + #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet +#endif + +//***************************************************************************** +// +// Recharge calculator defines and globals +// +//***************************************************************************** + +#define PD_STATE_CACHE_RET 1 +#define PD_STATE_RFMEM_RET 2 +#define PD_STATE_XOSC_LPM 4 +#define PD_STATE_EXT_REG_MODE 8 + +typedef struct { + uint32_t pdTime ; + uint16_t pdRechargePeriod ; + uint8_t pdState ; + int8_t pdTemp ; +} PowerQualGlobals_t; + +static PowerQualGlobals_t powerQualGlobals; + + +//***************************************************************************** +// +// SysCtrlSetRechargeBeforePowerDown( xoscPowerMode ) +// +//***************************************************************************** +void +SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ) +{ + int32_t curTemp ; + int32_t shiftedTemp ; + int32_t deltaVddrSleepTrim ; + int32_t vddrTrimSleep ; + int32_t vddrTrimActve ; + int32_t diffVddrActiveSleep ; + uint32_t ccfg_ModeConfReg ; + uint32_t curState ; + uint32_t prcmRamRetention ; + uint32_t di ; + uint32_t dii ; + uint32_t ti ; + uint32_t cd ; + uint32_t cl ; + uint32_t load ; + uint32_t k ; + uint32_t vddrCap ; + uint32_t newRechargePeriod ; + uint32_t perE ; + uint32_t perM ; + const uint32_t * pLookupTable ; + + // If external regulator mode we shall: + // - Disable adaptive recharge (bit[31]=0) in AON_WUC_O_RECHARGECFG + // - Set recharge period to approximately 500 mS (perM=31, perE=5 => 0xFD) + // - Make sure you get a recalculation if leaving external regulator mode by setting powerQualGlobals.pdState accordingly + if ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE ) { + powerQualGlobals.pdState = PD_STATE_EXT_REG_MODE; + HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGECFG ) = 0x00A4FDFD; + return; + } + + //--- Spec. point 1 --- + curTemp = AONBatMonTemperatureGetDegC(); + curState = 0; + + // read the MODE_CONF register in CCFG + ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + // Get VDDR_TRIM_SLEEP_DELTA + 1 (sign extended) + deltaVddrSleepTrim = ((((int32_t) ccfg_ModeConfReg ) + << ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S )) + >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W )) + 1; + // Do temperature compensation if enabled + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC ) == 0 ) { + int32_t tcDelta = ( 62 - curTemp ) >> 3; + if ( tcDelta > 8 ) tcDelta = 8; + if ( tcDelta > deltaVddrSleepTrim ) deltaVddrSleepTrim = tcDelta; + } + if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) && + (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) ) + { + vddrTrimSleep = SetupSignExtendVddrTrimValue(( + HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) & + FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M ) >> + FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S ) ; + vddrTrimActve = SetupSignExtendVddrTrimValue(( + HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) & + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >> + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ; + } else + { + vddrTrimSleep = SetupSignExtendVddrTrimValue(( + HWREG( FCFG1_BASE + FCFG1_O_LDO_TRIM ) & + FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M ) >> + FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S ) ; + vddrTrimActve = SetupSignExtendVddrTrimValue(( + HWREG( FCFG1_BASE + FCFG1_O_SHDW_ANA_TRIM ) & + FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M ) >> + FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S ) ; + } + vddrTrimSleep += deltaVddrSleepTrim; + if ( vddrTrimSleep > 21 ) vddrTrimSleep = 21; + if ( vddrTrimSleep < -10 ) vddrTrimSleep = -10; + // Write adjusted value using MASKED write (MASK8) + HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_DCDCCTL1 * 2 )) = (( ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M << 8 ) | + (( vddrTrimSleep << ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S ) & ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M )); + + prcmRamRetention = HWREG( PRCM_BASE + PRCM_O_RAMRETEN ); + if ( prcmRamRetention & PRCM_RAMRETEN_VIMS_M ) { + curState |= PD_STATE_CACHE_RET; + } + if ( prcmRamRetention & PRCM_RAMRETEN_RFC ) { + curState |= PD_STATE_RFMEM_RET; + } + if ( xoscPowerMode != XOSC_IN_HIGH_POWER_MODE ) { + curState |= PD_STATE_XOSC_LPM; + } + + //--- Spec. point 2 --- + if ((( curTemp - powerQualGlobals.pdTemp ) >= 5 ) || ( curState != powerQualGlobals.pdState )) { + //--- Spec. point 3 --- + shiftedTemp = curTemp - 15; + + //--- Spec point 4 --- + //4. Check for external VDDR load option (may not be supported): ext_load = (VDDR_EXT_LOAD=0 in CCFG) + // Currently not implementing external load handling + // if ( __ccfg.ulModeConfig & MODE_CONF_VDDR_EXT_LOAD ) { + // } + + pLookupTable = (uint32_t *)( FCFG1_BASE + FCFG1_O_PWD_CURR_20C ); + + //--- Spec point 5 --- + di = 0; + ti = 0; + if ( shiftedTemp >= 0 ) { + //--- Spec point 5.a --- + shiftedTemp += ( shiftedTemp << 4 ); + + //--- Spec point 5.b --- + ti = ( shiftedTemp >> 8 ); + if ( ti > 7 ) { + ti = 7; + } + dii = ti; + if ( dii > 6 ) { + dii = 6; + } + + //--- Spec point 5.c --- + cd = pLookupTable[ dii + 1 ] - pLookupTable[ dii ]; + + //--- Spec point 5.d --- + di = cd & 0xFF; + + //--- Spec point 5.e --- + if ( curState & PD_STATE_XOSC_LPM ) { + di += (( cd >> 8 ) & 0xFF ); + } + if ( curState & PD_STATE_RFMEM_RET ) { + di += (( cd >> 16 ) & 0xFF ); + } + if ( curState & PD_STATE_CACHE_RET ) { + di += (( cd >> 24 ) & 0xFF ); + } + + //--- Spec point 5.f --- + // Currently not implementing external load handling + } + + //--- Spec. point 6 --- + cl = pLookupTable[ ti ]; + + //--- Spec. point 7 --- + load = cl & 0xFF; + + //--- Spec. point 8 --- + if ( curState & PD_STATE_XOSC_LPM ) { + load += (( cl >> 8 ) & 0xFF ); + } + if ( curState & PD_STATE_RFMEM_RET ) { + load += (( cl >> 16 ) & 0xFF ); + } + if ( curState & PD_STATE_CACHE_RET ) { + load += (( cl >> 24 ) & 0xFF ); + } + + //--- Spec. point 9 --- + load += ((( di * ( shiftedTemp - ( ti << 8 ))) + 128 ) >> 8 ); + + // Currently not implementing external load handling + // if ( __ccfg.ulModeConfig & MODE_CONF_VDDR_EXT_LOAD ) { + //--- Spec. point 10 --- + // } else { + //--- Spec. point 11 --- + diffVddrActiveSleep = ( vddrTrimActve - vddrTrimSleep ); + if ( diffVddrActiveSleep < 1 ) diffVddrActiveSleep = 1; + k = ( diffVddrActiveSleep * 52 ); + // } + + //--- Spec. point 12 --- + + vddrCap = ( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_CAP_M ) >> CCFG_MODE_CONF_VDDR_CAP_S; + newRechargePeriod = ( vddrCap * k ) / load; + if ( newRechargePeriod > 0xFFFF ) { + newRechargePeriod = 0xFFFF; + } + powerQualGlobals.pdRechargePeriod = newRechargePeriod; + + //--- Spec. point 13 --- + if ( curTemp > 127 ) curTemp = 127; + if ( curTemp < -128 ) curTemp = -128; + powerQualGlobals.pdTemp = curTemp; + powerQualGlobals.pdState = curState; + } + + powerQualGlobals.pdTime = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + + // Calculate PER_E and PER_M (based on powerQualGlobals.pdRechargePeriod) + // Round downwards but make sure PER_E=0 and PER_M=1 is the minimum possible setting. + // (assuming that powerQualGlobals.pdRechargePeriod always are <= 0xFFFF) + perE = 0; + perM = powerQualGlobals.pdRechargePeriod; + if ( perM < 31 ) { + perM = 31; + powerQualGlobals.pdRechargePeriod = 31; + } + while ( perM > 511 ) { + perM >>= 1; + perE += 1; + } + perM = ( perM - 15 ) >> 4; + + HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGECFG ) = + ( 0x80A4E700 ) | + ( perM << AON_WUC_RECHARGECFG_PER_M_S ) | + ( perE << AON_WUC_RECHARGECFG_PER_E_S ) ; + HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGESTAT ) = 0; +} + + +//***************************************************************************** +// +// SysCtrlAdjustRechargeAfterPowerDown() +// +//***************************************************************************** +void +SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ) +{ + int32_t curTemp ; + uint32_t longestRechargePeriod ; + uint32_t deltaTime ; + uint32_t newRechargePeriod ; + + //--- Spec. point 2 --- + longestRechargePeriod = ( HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGESTAT ) & + AON_WUC_RECHARGESTAT_MAX_USED_PER_M ) >> + AON_WUC_RECHARGESTAT_MAX_USED_PER_S ; + + if ( longestRechargePeriod != 0 ) { + //--- Spec. changed (originally point 1) --- + curTemp = AONBatMonTemperatureGetDegC(); + if ( curTemp < powerQualGlobals.pdTemp ) { + if ( curTemp < -128 ) { + curTemp = -128; + } + powerQualGlobals.pdTemp = curTemp; + } + + // Add some margin between the longest previous recharge period and the + // next initial recharge period. Since it is a fixed margin, it will have a + // higher impact as a fraction of the converged recharge period at higher temperatures + // where it is needed more due to higher leakage. + if (longestRechargePeriod > vddrRechargeMargin) { + longestRechargePeriod -= vddrRechargeMargin; + } + else { + longestRechargePeriod = 1; + } + + //--- Spec. point 4 --- + if ( longestRechargePeriod < powerQualGlobals.pdRechargePeriod ) { + powerQualGlobals.pdRechargePeriod = longestRechargePeriod; + } else { + //--- Spec. point 5 --- + deltaTime = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ) - powerQualGlobals.pdTime + 2; + if ( deltaTime > 31 ) { + deltaTime = 31; + } + newRechargePeriod = powerQualGlobals.pdRechargePeriod + (( longestRechargePeriod - powerQualGlobals.pdRechargePeriod ) >> (deltaTime>>1)); + if ( newRechargePeriod > 0xFFFF ) { + newRechargePeriod = 0xFFFF; + } + powerQualGlobals.pdRechargePeriod = newRechargePeriod; + } + } +} + + +//***************************************************************************** +// +// SysCtrl_DCDC_VoltageConditionalControl() +// +//***************************************************************************** +void +SysCtrl_DCDC_VoltageConditionalControl( void ) +{ + uint32_t batThreshold ; // Fractional format with 8 fractional bits. + uint32_t aonBatmonBat ; // Fractional format with 8 fractional bits. + uint32_t ccfg_ModeConfReg ; // Holds a copy of the CCFG_O_MODE_CONF register. + uint32_t aonSysctlPwrctl ; // Reflect whats read/written to the AON_SYSCTL_O_PWRCTL register. + + // We could potentially call this function before any battery voltage measurement + // is made/available. In that case we must make sure that we do not turn off the DCDC. + // This can be done by doing nothing as long as the battery voltage is 0 (Since the + // reset value of the battery voltage register is 0). + aonBatmonBat = HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT ); + if ( aonBatmonBat != 0 ) { + // Check if Voltage Conditional Control is enabled + // It is enabled if all the following are true: + // - DCDC in use (either in active or recharge mode), (in use if one of the corresponding CCFG bits are zero). + // - Alternative DCDC settings are enabled ( DIS_ALT_DCDC_SETTING == 0 ) + // - Not in external regulator mode ( EXT_REG_MODE == 0 ) + ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + + if (((( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) || + (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) ) && + (( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE ) == 0 ) && + (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) ) + { + aonSysctlPwrctl = HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ); + batThreshold = (((( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & + CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) >> + CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) + 28 ) << 4 ); + + if ( aonSysctlPwrctl & ( AON_SYSCTL_PWRCTL_DCDC_EN_M | AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M )) { + // DCDC is ON, check if it should be switched off + if ( aonBatmonBat < batThreshold ) { + aonSysctlPwrctl &= ~( AON_SYSCTL_PWRCTL_DCDC_EN_M | AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M ); + + HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) = aonSysctlPwrctl; + } + } else { + // DCDC is OFF, check if it should be switched on + if ( aonBatmonBat > batThreshold ) { + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) aonSysctlPwrctl |= AON_SYSCTL_PWRCTL_DCDC_EN_M ; + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) aonSysctlPwrctl |= AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M ; + + HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) = aonSysctlPwrctl; + } + } + } + } +} + + +//***************************************************************************** +// +// SysCtrlResetSourceGet() +// +//***************************************************************************** +uint32_t +SysCtrlResetSourceGet( void ) +{ + uint32_t aonSysctlResetCtl = HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ); + + if ( aonSysctlResetCtl & AON_SYSCTL_RESETCTL_WU_FROM_SD_M ) { + return ( RSTSRC_WAKEUP_FROM_SHUTDOWN ); + } else { + return (( aonSysctlResetCtl & AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> AON_SYSCTL_RESETCTL_RESET_SRC_S ) ; + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sys_ctrl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sys_ctrl.h new file mode 100644 index 0000000..02d3789 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sys_ctrl.h @@ -0,0 +1,418 @@ +/****************************************************************************** +* Filename: sys_ctrl.h +* Revised: 2018-09-17 14:58:51 +0200 (Mon, 17 Sep 2018) +* Revision: 52634 +* +* Description: Defines and prototypes for the System Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup sysctrl_api +//! @{ +// +//***************************************************************************** + +#ifndef __SYSCTRL_H__ +#define __SYSCTRL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_sysctl.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_aux_wuc.h" +#include "../inc/hw_aon_ioc.h" +#include "../inc/hw_ddi_0_osc.h" +#include "../inc/hw_rfc_pwr.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_aon_sysctl.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_fcfg1.h" +#include "interrupt.h" +#include "debug.h" +#include "pwr_ctrl.h" +#include "osc.h" +#include "prcm.h" +#include "aux_wuc.h" +#include "aon_wuc.h" +#include "adi.h" +#include "ddi.h" +#include "cpu.h" +#include "vims.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown + #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown + #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl + #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet +#endif + +//***************************************************************************** +// +// Defines for the settings of the main XOSC +// +//***************************************************************************** +#define SYSCTRL_SYSBUS_ON 0x00000001 +#define SYSCTRL_SYSBUS_OFF 0x00000000 + +//***************************************************************************** +// +// Defines for the different power modes of the System CPU +// +//***************************************************************************** +#define CPU_RUN 0x00000000 +#define CPU_SLEEP 0x00000001 +#define CPU_DEEP_SLEEP 0x00000002 + +//***************************************************************************** +// +// Defines for SysCtrlSetRechargeBeforePowerDown +// +//***************************************************************************** +#define XOSC_IN_HIGH_POWER_MODE 0 // When xosc_hf is in HIGH_POWER_XOSC +#define XOSC_IN_LOW_POWER_MODE 1 // When xosc_hf is in LOW_POWER_XOSC + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Get the CPU core clock frequency. +//! +//! Use this function to get the current clock frequency for the CPU. +//! +//! The CPU can run from 48 MHz and down to 750kHz. The frequency is defined +//! by the combined division factor of the SYSBUS and the CPU clock divider. +//! +//! \return Returns the current CPU core clock frequency. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SysCtrlClockGet( void ) +{ + // Return fixed clock speed + return( GET_MCU_CLOCK ); +} + +//***************************************************************************** +// +//! \brief Sync all accesses to the AON register interface. +//! +//! When this function returns, all writes to the AON register interface are +//! guaranteed to have propagated to hardware. The function will return +//! immediately if no AON writes are pending; otherwise, it will wait for the next +//! AON clock before returning. +//! +//! \return None +//! +//! \sa \ref SysCtrlAonUpdate() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlAonSync(void) +{ + // Sync the AON interface + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! \brief Update all interfaces to AON. +//! +//! When this function returns, at least 1 clock cycle has progressed on the +//! AON domain, so that any outstanding updates to and from the AON interface +//! is guaranteed to be in sync. +//! +//! \note This function should primarily be used after wakeup from sleep modes, +//! as it will guarantee that all shadow registers on the AON interface are updated +//! before reading any AON registers from the MCU domain. If a write has been +//! done to the AON interface it is sufficient to call the \ref SysCtrlAonSync(). +//! +//! \return None +//! +//! \sa \ref SysCtrlAonSync() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlAonUpdate(void) +{ + // Force a clock cycle on the AON interface to guarantee all registers are + // in sync. + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC) = 1; + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! \brief Set Recharge values before entering Power Down. +//! +//! This function shall be called just before entering Power Down. +//! It calculates an optimal and safe recharge setting of the adaptive recharge +//! controller. The results of previous setting are also taken into account. +//! +//! \note In order to make sure that the register writes are completed, \ref SysCtrlAonSync() +//! must be called before entering standby/power down. This is not done internally +//! in this function due to two reasons: +//! - 1) There might be other register writes that must be synchronized as well. +//! - 2) It is possible to save some time by doing other things before calling +//! \ref SysCtrlAonSync() since this call will not return before there are no +//! outstanding write requests between MCU and AON. +//! +//! \param xoscPowerMode (typically running in XOSC_IN_HIGH_POWER_MODE all the time). +//! - \ref XOSC_IN_HIGH_POWER_MODE : When xosc_hf is in HIGH_POWER_XOSC. +//! - \ref XOSC_IN_LOW_POWER_MODE : When xosc_hf is in LOW_POWER_XOSC. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ); + +//***************************************************************************** +// +//! \brief Adjust Recharge calculations to be used next. +//! +//! This function shall be called just after returning from Power Down. +//! +//! Reads the results from the adaptive recharge controller and current chip +//! temperature. This is used as additional information when calculating +//! optimal recharge controller settings next time (When +//! \ref SysCtrlSetRechargeBeforePowerDown() is called next time). +//! +//! \param vddrRechargeMargin margin in SCLK_LF periods to subtract from +//! previous longest recharge period experienced while in standby. +//! +//! \note +//! Special care must be taken to make sure that the AON registers read are +//! updated after the wakeup. Writing to an AON register and then calling +//! \ref SysCtrlAonSync() will handle this. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ); + +//***************************************************************************** +// +//! \brief Turns DCDC on or off depending of what is considered to be optimal usage. +//! +//! This function controls the DCDC only if both the following CCFG settings are \c true: +//! - DCDC is configured to be used. +//! - Alternative DCDC settings are defined and enabled. +//! +//! The DCDC is configured in accordance to the CCFG settings when turned on. +//! +//! This function should be called periodically. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrl_DCDC_VoltageConditionalControl( void ); + +//***************************************************************************** +// \name Return values from calling SysCtrlResetSourceGet() +//@{ +//***************************************************************************** +#define RSTSRC_PWR_ON (( AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_PIN_RESET (( AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_VDDS_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_VDDR_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_CLK_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_SYSRESET (( AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_WARMRESET (( AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_WAKEUP_FROM_SHUTDOWN ((( AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) + 1 ) +//@} + +//***************************************************************************** +// +//! \brief Returns the reset source (including "wakeup from shutdown"). +//! +//! In case of \ref RSTSRC_WAKEUP_FROM_SHUTDOWN the application is +//! responsible for unlatching the outputs (disable pad sleep). +//! See \ref PowerCtrlPadSleepDisable() for more information. +//! +//! \return Returns the reset source. +//! - \ref RSTSRC_PWR_ON +//! - \ref RSTSRC_PIN_RESET +//! - \ref RSTSRC_VDDS_LOSS +//! - \ref RSTSRC_VDDR_LOSS +//! - \ref RSTSRC_CLK_LOSS +//! - \ref RSTSRC_SYSRESET +//! - \ref RSTSRC_WARMRESET +//! - \ref RSTSRC_WAKEUP_FROM_SHUTDOWN +// +//***************************************************************************** +extern uint32_t SysCtrlResetSourceGet( void ); + +//***************************************************************************** +// +//! \brief Perform a full system reset. +//! +//! \return The chip will reset and hence never return from this call. +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlSystemReset( void ) +{ + // Disable CPU interrupts + CPUcpsid(); + // Write reset register + HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_SYSRESET_BITN ) = 1; + // Finally, wait until the above write propagates + while ( 1 ) { + // Do nothing, just wait for the reset (and never return from here) + } +} + +//***************************************************************************** +// +//! \brief Enables reset if OSC clock loss event is asserted. +//! +//! Clock loss circuit in analog domain must be enabled as well in order to +//! actually enable for a clock loss reset to occur +//! \ref OSCClockLossEventEnable(). +//! +//! \note This function shall typically not be called because the clock loss +//! reset functionality is controlled by the boot code (a factory configuration +//! defines whether it is set or not). +//! +//! \return None +//! +//! \sa \ref SysCtrlClockLossResetDisable(), \ref OSCClockLossEventEnable() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlClockLossResetEnable(void) +{ + // Set clock loss enable bit in AON_SYSCTRL using bit banding + HWREGBITW(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disables reset due to OSC clock loss event. +//! +//! \note This function shall typically not be called because the clock loss +//! reset functionality is controlled by the boot code (a factory configuration +//! defines whether it is set or not). +//! +//! \return None +//! +//! \sa \ref SysCtrlClockLossResetEnable() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlClockLossResetDisable(void) +{ + // Clear clock loss enable bit in AON_SYSCTRL using bit banding + HWREGBITW(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN) = 0; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SysCtrlSetRechargeBeforePowerDown + #undef SysCtrlSetRechargeBeforePowerDown + #define SysCtrlSetRechargeBeforePowerDown ROM_SysCtrlSetRechargeBeforePowerDown + #endif + #ifdef ROM_SysCtrlAdjustRechargeAfterPowerDown + #undef SysCtrlAdjustRechargeAfterPowerDown + #define SysCtrlAdjustRechargeAfterPowerDown ROM_SysCtrlAdjustRechargeAfterPowerDown + #endif + #ifdef ROM_SysCtrl_DCDC_VoltageConditionalControl + #undef SysCtrl_DCDC_VoltageConditionalControl + #define SysCtrl_DCDC_VoltageConditionalControl ROM_SysCtrl_DCDC_VoltageConditionalControl + #endif + #ifdef ROM_SysCtrlResetSourceGet + #undef SysCtrlResetSourceGet + #define SysCtrlResetSourceGet ROM_SysCtrlResetSourceGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTRL_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick.c new file mode 100644 index 0000000..29aa43b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: systick.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the SysTick timer in NVIC +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "systick.h" + +// See systick.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick.h new file mode 100644 index 0000000..735171d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick.h @@ -0,0 +1,287 @@ +/****************************************************************************** +* Filename: systick.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Prototypes for the SysTick driver. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_types.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// API Functions and Prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enables the SysTick counter. +//! +//! This will start the SysTick counter. If an interrupt handler has been +//! registered, it will be called when the SysTick counter rolls over. +//! +//! \note Calling this function will cause the SysTick counter to (re)commence +//! counting from its current value. The counter is not automatically reloaded +//! with the period as specified in a previous call to \ref SysTickPeriodSet(). If +//! an immediate reload is required, the NVIC_ST_CURRENT register must be +//! written to force this. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the supplied period on the next +//! clock. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickEnable(void) +{ + // Enable SysTick. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; +} + +//***************************************************************************** +// +//! \brief Disables the SysTick counter. +//! +//! This will stop the SysTick counter. If an interrupt handler has been +//! registered, it will no longer be called until SysTick is restarted. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickDisable(void) +{ + // Disable SysTick. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the SysTick interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler, returning an error if an error occurs. + IntRegister(INT_SYSTICK, pfnHandler); + + // Enable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! \brief Unregisters the interrupt handler for the SysTick interrupt in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntUnregister(void) +{ + // Disable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + + // Unregister the interrupt handler. + IntUnregister(INT_SYSTICK); +} + +//***************************************************************************** +// +//! \brief Enables the SysTick interrupt. +//! +//! This function will enable the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \note The SysTick interrupt handler does not need to clear the SysTick +//! interrupt source as this is done automatically by NVIC when the interrupt +//! handler is called. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntEnable(void) +{ + // Enable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! \brief Disables the SysTick interrupt. +//! +//! This function will disable the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntDisable(void) +{ + // Disable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); +} + +//***************************************************************************** +// +//! \brief Sets the period of the SysTick counter. +//! +//! This function sets the rate at which the SysTick counter wraps; this +//! equals to the number of processor clocks between interrupts. +//! +//! \note Calling this function does not cause the SysTick counter to reload +//! immediately. If an immediate reload is required, the NVIC_ST_CURRENT +//! register must be written. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the \c ui32Period supplied here +//! on the next clock after the SysTick is enabled. +//! +//! \param ui32Period is the number of clock ticks in each period of the +//! SysTick counter; must be between 1 and 16,777,216 (0x1000000), both included. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickPeriodSet(uint32_t ui32Period) +{ + // Check the arguments. + ASSERT((ui32Period > 0) && (ui32Period <= 16777216)); + + // Set the period of the SysTick counter. + HWREG(NVIC_ST_RELOAD) = ui32Period - 1; +} + +//***************************************************************************** +// +//! \brief Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps; this +//! equals to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SysTickPeriodGet(void) +{ + // Return the period of the SysTick counter. + return(HWREG(NVIC_ST_RELOAD) + 1); +} + +//***************************************************************************** +// +//! \brief Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter; this will +//! be a value between the (period - 1) and zero, both included. +//! +//! \return Returns the current value of the SysTick counter +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SysTickValueGet(void) +{ + // Return the current value of the SysTick counter. + return(HWREG(NVIC_ST_CURRENT)); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ + +//***************************************************************************** +// +//! Close the Doxygen group +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick_doc.h new file mode 100644 index 0000000..70848fc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick_doc.h @@ -0,0 +1,68 @@ +/****************************************************************************** +* Filename: systick_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup systick_api +//! @{ +//! \section sec_systick Introduction +//! +//! The system CPU includes a system timer, SysTick, integrated in the NVIC which provides a simple, 24-bit, +//! clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. +//! When enabled, the timer counts down on each clock from the reload value to 0, reloads (wraps) on +//! the next clock edge, then decrements on subsequent clocks. +//! +//! The SysTick counter runs on the system clock. If this clock signal is stopped for low-power mode, the +//! SysTick counter stops. +//! +//! When the processor is halted for debugging, the counter does not decrement. +//! +//! \section sec_systick_api API +//! +//! The API functions can be grouped like this: +//! +//! Configuration and status: +//! - \ref SysTickPeriodSet() +//! - \ref SysTickPeriodGet() +//! - \ref SysTickValueGet() +//! +//! Enable and disable: +//! - \ref SysTickEnable() +//! - \ref SysTickDisable() +//! +//! Interrupt configuration: +//! - \ref SysTickIntRegister() +//! - \ref SysTickIntUnregister() +//! - \ref SysTickIntEnable() +//! - \ref SysTickIntDisable() +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer.c new file mode 100644 index 0000000..86c484f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer.c @@ -0,0 +1,392 @@ +/****************************************************************************** +* Filename: timer.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the General Purpose Timer +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "timer.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef TimerConfigure + #define TimerConfigure NOROM_TimerConfigure + #undef TimerLevelControl + #define TimerLevelControl NOROM_TimerLevelControl + #undef TimerStallControl + #define TimerStallControl NOROM_TimerStallControl + #undef TimerWaitOnTriggerControl + #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl + #undef TimerIntRegister + #define TimerIntRegister NOROM_TimerIntRegister + #undef TimerIntUnregister + #define TimerIntUnregister NOROM_TimerIntUnregister + #undef TimerMatchUpdateMode + #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode + #undef TimerIntervalLoadMode + #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode +#endif + +//***************************************************************************** +// +//! \brief Gets the timer interrupt number. +//! +//! Given a timer base address, this function returns the corresponding +//! interrupt number. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return Returns a timer interrupt number, or -1 if \c ui32Base is invalid. +// +//***************************************************************************** +static uint32_t +TimerIntNumberGet(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // Loop through the table that maps timer base addresses to interrupt + // numbers. + switch(ui32Base) + { + case GPT0_BASE : + ui32Int = INT_GPT0A; + break; + case GPT1_BASE : + ui32Int = INT_GPT1A; + break; + case GPT2_BASE : + ui32Int = INT_GPT2A; + break; + case GPT3_BASE : + ui32Int = INT_GPT3A; + break; + default : + ui32Int = 0x0; + } + + // Return the interrupt number or (-1) if not base address is not matched. + return (ui32Int); +} + +//***************************************************************************** +// +// Configures the timer(s) +// +//***************************************************************************** +void +TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || + (ui32Config == TIMER_CFG_ONE_SHOT_UP) || + (ui32Config == TIMER_CFG_PERIODIC) || + (ui32Config == TIMER_CFG_PERIODIC_UP) || + ((ui32Config & 0xFF000000) == TIMER_CFG_SPLIT_PAIR)); + ASSERT(((ui32Config & 0xFF000000) != TIMER_CFG_SPLIT_PAIR) || + ((((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PWM)) && + (((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PWM)))); + + // Disable the timers. + HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); + + // Set the global timer configuration. + HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24; + + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE; + HWREG(ui32Base + GPT_O_TBMR) = + ((ui32Config >> 8) & 0xFF) | GPT_TBMR_TBPWMIE; +} + +//***************************************************************************** +// +// Controls the output level +// +//***************************************************************************** +void +TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the output levels as requested. + ui32Timer &= GPT_CTL_TAPWML | GPT_CTL_TBPWML; + HWREG(ui32Base + GPT_O_CTL) = (bInvert ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & + ~(ui32Timer))); +} + +//***************************************************************************** +// +// Controls the stall handling +// +//***************************************************************************** +void +TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the stall mode. + ui32Timer &= GPT_CTL_TASTALL | GPT_CTL_TBSTALL; + HWREG(ui32Base + GPT_O_CTL) = (bStall ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer))); +} + +//***************************************************************************** +// +// Controls the wait on trigger handling +// +//***************************************************************************** +void +TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the wait on trigger mode for timer A. + if(ui32Timer & TIMER_A) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAWOT; + } + else + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAWOT); + } + } + + // Set the wait on trigger mode for timer B. + if(ui32Timer & TIMER_B) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBWOT; + } + else + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBWOT); + } + } +} + +//***************************************************************************** +// +// Registers an interrupt handler for the timer interrupt +// +//***************************************************************************** +void +TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Get the interrupt number for this timer module. + ui32Int = TimerIntNumberGet(ui32Base); + + // Register an interrupt handler for timer A if requested. + if(ui32Timer & TIMER_A) + { + // Register the interrupt handler. + IntRegister(ui32Int, pfnHandler); + + // Enable the interrupt. + IntEnable(ui32Int); + } + + // Register an interrupt handler for timer B if requested. + if(ui32Timer & TIMER_B) + { + // Register the interrupt handler. + IntRegister(ui32Int + 1, pfnHandler); + + // Enable the interrupt. + IntEnable(ui32Int + 1); + } +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for the timer interrupt +// +//***************************************************************************** +void +TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Get the interrupt number for this timer module. + ui32Int = TimerIntNumberGet(ui32Base); + + // Unregister the interrupt handler for timer A if requested. + if(ui32Timer & TIMER_A) + { + // Disable the interrupt. + IntDisable(ui32Int); + + // Unregister the interrupt handler. + IntUnregister(ui32Int); + } + + // Unregister the interrupt handler for timer B if requested. + if(ui32Timer & TIMER_B) + { + // Disable the interrupt. + IntDisable(ui32Int + 1); + + // Unregister the interrupt handler. + IntUnregister(ui32Int + 1); + } +} + +//***************************************************************************** +// +// Sets the Match Register Update mode +// +//***************************************************************************** +void +TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); + ASSERT((ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) || (ui32Mode == TIMER_MATCHUPDATE_TIMEOUT)); + + // Set mode for timer A + if(ui32Timer & TIMER_A) + { + if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAMRSU); + } + else + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAMRSU; + } + } + + // Set mode for timer B + if(ui32Timer & TIMER_B) + { + if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBMRSU); + } + else + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBMRSU; + } + } +} + +//***************************************************************************** +// +// Sets the Interval Load mode +// +//***************************************************************************** +void +TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); + ASSERT((ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) || (ui32Mode == TIMER_INTERVALLOAD_TIMEOUT)); + + // Set mode for timer A + if(ui32Timer & TIMER_A) + { + if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAILD); + } + else + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAILD; + } + } + + // Set mode for timer B + if(ui32Timer & TIMER_B) + { + if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBILD); + } + else + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBILD; + } + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer.h new file mode 100644 index 0000000..da13074 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer.h @@ -0,0 +1,1176 @@ +/****************************************************************************** +* Filename: timer.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//**************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup timer_api +//! @{ +// +//**************************************************************************** + +#ifndef __GPT_H__ +#define __GPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_gpt.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define TimerConfigure NOROM_TimerConfigure + #define TimerLevelControl NOROM_TimerLevelControl + #define TimerStallControl NOROM_TimerStallControl + #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl + #define TimerIntRegister NOROM_TimerIntRegister + #define TimerIntUnregister NOROM_TimerIntUnregister + #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode + #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ui32Config parameter. +// +//***************************************************************************** +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ui32IntFlags parameter, and returned from +// TimerIntStatus. +// +//***************************************************************************** +#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ui32Event parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ui32Timer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000FF // Timer A +#define TIMER_B 0x0000FF00 // Timer B +#define TIMER_BOTH 0x0000FFFF // Timer Both + +//***************************************************************************** +// +// Values that can be passed to GPTSynchronize as the ui32Timers parameter +// +//***************************************************************************** +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B + +//***************************************************************************** +// +// Values that can be passed to TimerMatchUpdateMode +// +//***************************************************************************** +#define TIMER_MATCHUPDATE_NEXTCYCLE 0x00000000 // Apply match register on next cycle +#define TIMER_MATCHUPDATE_TIMEOUT 0x00000001 // Apply match register on next timeout + +//***************************************************************************** +// +// Values that can be passed to TimerIntervalLoad +// +//***************************************************************************** +#define TIMER_INTERVALLOAD_NEXTCYCLE 0x00000000 // Load TxR register with the value in the TxILR register on the next clock cycle +#define TIMER_INTERVALLOAD_TIMEOUT 0x00000001 // Load TxR register with the value in the TxILR register on next timeout + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks a timer base address. +//! +//! This function determines if a timer module base address is valid. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +TimerBaseValid(uint32_t ui32Base) +{ + return((ui32Base == GPT0_BASE) || (ui32Base == GPT1_BASE) || + (ui32Base == GPT2_BASE) || (ui32Base == GPT3_BASE)); +} +#endif + +//***************************************************************************** +// +//! \brief Enables the timer(s). +//! +//! This function enables operation of the timer module. The timer must be +//! configured before it is enabled. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to enable. Must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerEnable(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Enable the timer(s) module. + HWREG(ui32Base + GPT_O_CTL) |= ui32Timer & (GPT_CTL_TAEN | GPT_CTL_TBEN); +} + +//***************************************************************************** +// +//! \brief Disables the timer(s). +//! +//! This function disables operation of the timer module. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to disable. Must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerDisable(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Disable the timer module. + HWREG(ui32Base + GPT_O_CTL) &= ~(ui32Timer & + (GPT_CTL_TAEN | GPT_CTL_TBEN)); +} + +//***************************************************************************** +// +//! \brief Configures the timer(s). +//! +//! This function configures the operating mode of the timer(s). The timer +//! module is disabled before being configured and is left in the disabled +//! state. +//! +//! The timers are comprised of two 16-bit timers that can +//! operate independently or be concatenated to form a 32-bit timer. +//! +//! \note If the timers are used independently the length of timer can be +//! extended to 24 bit by use of an 8 bit prescale register set using +//! \ref TimerPrescaleSet(). +//! +//! When configuring for full-width timer \c ui32Config is set +//! as one of the following values: +//! - \ref TIMER_CFG_ONE_SHOT : Full-width one-shot timer. +//! - \ref TIMER_CFG_ONE_SHOT_UP : Full-width one-shot timer that counts up +//! instead of down. +//! - \ref TIMER_CFG_PERIODIC : Full-width periodic timer. +//! - \ref TIMER_CFG_PERIODIC_UP : Full-width periodic timer that counts up +//! instead of down. +//! +//! When configuring for a pair of half-width timers, each timer is separately +//! configured. The timers are configured by setting \c ui32Config to +//! the bitwise OR of one of each of the following three: +//! - Use half-width timers: +//! - \ref TIMER_CFG_SPLIT_PAIR +//! - Timer A: +//! - \ref TIMER_CFG_A_ONE_SHOT : Half-width one-shot timer +//! - \ref TIMER_CFG_A_ONE_SHOT_UP : Half-width one-shot timer that counts up +//! instead of down. +//! - \ref TIMER_CFG_A_PERIODIC : Half-width periodic timer +//! - \ref TIMER_CFG_A_PERIODIC_UP : Half-width periodic timer that counts up +//! instead of down. +//! - \ref TIMER_CFG_A_CAP_COUNT : Half-width edge count capture +//! - \ref TIMER_CFG_A_CAP_COUNT_UP : Half-width edge count capture that counts +//! up instead of down. +//! - \ref TIMER_CFG_A_CAP_TIME : Half-width edge time capture +//! - \ref TIMER_CFG_A_CAP_TIME_UP : Half-width edge time capture that counts up +//! instead of down. +//! - \ref TIMER_CFG_A_PWM : Half-width PWM output +//! - Timer B: +//! - Same as Timer A but using TIMER_CFG_B_* instead. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Config is the configuration for the timer. +//! +//! \return None +// +//***************************************************************************** +extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config); + +//***************************************************************************** +// +//! \brief Controls the output level. +//! +//! This function configures the PWM output level for the specified timer. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust. Must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param bInvert specifies the output level. +//! - \c true : Timer's output is active low. +//! - \c false : Timer's output is active high. +//! +//! \return None +// +//***************************************************************************** +extern void TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, + bool bInvert); + +//***************************************************************************** +// +//! \brief Controls the event type. +//! +//! This function configures the signal edge(s) that triggers the timer when +//! in capture mode. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Event specifies the type of event; must be one of: +//! - \ref TIMER_EVENT_POS_EDGE +//! - \ref TIMER_EVENT_NEG_EDGE +//! - \ref TIMER_EVENT_BOTH_EDGES +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerEventControl(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Event) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the event type. + ui32Timer &= GPT_CTL_TAEVENT_M | GPT_CTL_TBEVENT_M; + HWREG(ui32Base + GPT_O_CTL) = ((HWREG(ui32Base + GPT_O_CTL) & ~ui32Timer) | + (ui32Event & ui32Timer)); +} + +//***************************************************************************** +// +//! \brief Controls the stall handling. +//! +//! This function controls the stall response for the specified timer. If the +//! \e bStall parameter is \b true, then the timer stops counting if the +//! processor enters debug mode; otherwise the timer keeps running while in +//! debug mode. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param bStall specifies the response to a stall signal. +//! - \c true : Timer stops counting if the processor enters debug mode. +//! - \c false : Timer keeps running if the processor enters debug mode. +//! +//! \return None +// +//***************************************************************************** +extern void TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, + bool bStall); + +//***************************************************************************** +// +//! \brief Controls the wait on trigger handling. +//! +//! This function controls whether or not a timer waits for a trigger input to +//! start counting. When enabled, the previous timer in the trigger chain must +//! count to its timeout in order for this timer to start counting. Refer to +//! the part's data sheet for a description of the trigger chain. +//! +//! \note This function should not be used for Timer 0A or Wide Timer 0A. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param bWait specifies if the timer should wait for a trigger input. +//! - \c true : Wait for trigger. +//! - \c false : Do not wait for trigger. +//! +//! \return None +// +//***************************************************************************** +extern void TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, + bool bWait); + +//***************************************************************************** +// +//! \brief Set the timer prescale value. +//! +//! This function configures the value of the timer clock prescaler. The +//! prescaler is only operational when in half-width mode and is used to extend +//! the range of the half-width timer modes. +//! +//! When in one-shot or periodic down count modes, \b ui32Value defines the +//! prescaler for the timer counter. When acting as a true prescaler, the +//! prescaler counts down to 0 before the value in timer registers are incremented. +//! +//! In all other individual/split modes, \b ui32Value is a linear extension of +//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes +//! of the 16/32-bit timer. +//! +//! \note Because the prescaler counts down to 0 the timer division ratio equals +//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the timer prescale value which must be between 0 and 255 +//! (both included). +//! - 0 : Timer division ratio = 1 (disable prescaling). +//! - 1 : Timer division ratio = 2. +//! - ... +//! - 255 : Timer division ratio = 256. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + ASSERT(ui32Value < 256); + + // Set the timer A prescaler if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAPR) = ui32Value; + } + + // Set the timer B prescaler if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBPR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Get the timer prescale value. +//! +//! This function gets the value of the timer clock prescaler. The +//! prescaler is only operational when in half-width mode and is used to extend +//! the range of the half-width timer modes. +//! +//! When in one-shot or periodic down count modes, \b ui32Value defines the +//! prescaler for the timer counter. When acting as a true prescaler, the +//! prescaler counts down to 0 before the value in timer registers are incremented. +//! +//! In all other individual/split modes, \b ui32Value is a linear extension of +//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes +//! of the 16/32-bit timer. +//! +//! \note Because the prescaler counts down to 0 the timer division ratio equals +//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the value of the timer prescaler. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Return the appropriate prescale value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPR) : + HWREG(ui32Base + GPT_O_TBPR)); +} + +//***************************************************************************** +// +//! \brief Set the timer prescale match value. +//! +//! This function configures the value of the input clock prescaler match +//! value. When in a half-width mode that uses the counter match and the +//! prescaler, the prescale match effectively extends the range of the match. +//! The prescaler provides the least significant bits when counting down in +//! periodic and one-shot modes; in all other modes, the prescaler provides the +//! most significant bits. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the timer prescale match value which must be between 0 +//! and 255 (both included). +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + ASSERT(ui32Value < 256); + + // Set the timer A prescale match if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAPMR) = ui32Value; + } + + // Set the timer B prescale match if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBPMR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Get the timer prescale match value. +//! +//! This function gets the value of the input clock prescaler match value. +//! When in a half-width mode that uses the counter match and prescaler, the +//! prescale match effectively extends the range of the match. The prescaler +//! provides the least significant bits when counting down in periodic and +//! one-shot modes; in all other modes, the prescaler provides the most +//! significant bits. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the value of the timer prescale match. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate prescale match value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPMR) : + HWREG(ui32Base + GPT_O_TBPMR)); +} + +//***************************************************************************** +// +//! \brief Sets the timer load value. +//! +//! This function configures the timer load value; if the timer is running then +//! the value is immediately loaded into the timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the load value. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the timer A load value if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAILR) = ui32Value; + } + + // Set the timer B load value if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBILR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Gets the timer load value. +//! +//! This function gets the currently programmed interval load value for the +//! specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the load value for the timer +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate load value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAILR) : + HWREG(ui32Base + GPT_O_TBILR)); +} + +//***************************************************************************** +// +//! \brief Gets the current timer value. +//! +//! This function reads the current value of the specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate timer value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAR) : + HWREG(ui32Base + GPT_O_TBR)); +} + +//***************************************************************************** +// +//! \brief Sets the timer match value. +//! +//! This function configures the match value for a timer. This value is used +//! in capture count mode to determine when to interrupt the processor and in +//! PWM mode to determine the duty cycle of the output signal. Match interrupts +//! can also be generated in periodic and one-shot modes when the value of the +//! counter matches this register. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the match value. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the timer A match value if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAMATCHR) = ui32Value; + } + + // Set the timer B match value if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBMATCHR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Gets the timer match value. +//! +//! This function gets the match value for the specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return Returns the match value for the timer +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate match value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAMATCHR) : + HWREG(ui32Base + GPT_O_TBMATCHR)); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the timer interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific timer interrupts must be enabled via \ref TimerIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! \ref TimerIntClear(). +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s); must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param pfnHandler is a pointer to the function to be called when the timer +//! interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, + void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the timer interrupt in the dynamic interrupt table. +//! +//! This function unregisters the handler to be called when a timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s); must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer); + +//***************************************************************************** +// +//! \brief Enables individual timer interrupt sources. +//! +//! This function enables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter must be the bitwise OR of any combination of +//! the following: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(ui32Base + GPT_O_IMR) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual timer interrupt sources. +//! +//! This function disables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter must be the bitwise OR of any combination of +//! the following: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(ui32Base + GPT_O_IMR) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the timer module. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the timer module. +//! \param bMasked selects either raw or masked interrupt status: +//! - \c true : Masked interrupt. +//! - \c false : Raw interrupt. +//! +//! \return The current interrupt status, enumerated as a bit field of values: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + return(bMasked ? HWREG(ui32Base + GPT_O_MIS) : + HWREG(ui32Base + GPT_O_RIS)); +} + +//***************************************************************************** +// +//! \brief Clears timer interrupt sources. +//! +//! The specified timer interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter must be the bitwise OR of any combination of +//! the following: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Clear the requested interrupt sources. + HWREG(ui32Base + GPT_O_ICLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Synchronizes the counters in a set of timers. +//! +//! This function synchronizes the counters in a specified set of timers. +//! When a timer is running in half-width mode, each half can be included or +//! excluded in the synchronization event. When a timer is running in +//! full-width mode, only the A timer can be synchronized (specifying the B +//! timer has no effect). +//! +//! \param ui32Base is the base address of the timer module. This parameter must +//! be the base address of Timer0 (in other words, \b GPT0_BASE). +//! \param ui32Timers is the set of timers to synchronize. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TIMER_0A_SYNC +//! - \ref TIMER_0B_SYNC +//! - \ref TIMER_1A_SYNC +//! - \ref TIMER_1B_SYNC +//! - \ref TIMER_2A_SYNC +//! - \ref TIMER_2B_SYNC +//! - \ref TIMER_3A_SYNC +//! - \ref TIMER_3B_SYNC +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers) +{ + // Check the arguments. + ASSERT(ui32Base == GPT0_BASE); + + // Synchronize the specified timers. + HWREG(ui32Base + GPT_O_SYNC) = ui32Timers; +} + +//***************************************************************************** +// +//! \brief Enables AND'ing of the CCP outputs from Timer A and Timer B. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerCcpCombineEnable(uint32_t ui32Base) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + + // Set the bit + HWREG(ui32Base + GPT_O_ANDCCP) |= GPT_ANDCCP_CCP_AND_EN; +} + +//***************************************************************************** +// +//! \brief Disables AND'ing of the CCP outputs from Timer A and Timer B. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerCcpCombineDisable(uint32_t ui32Base) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + + // Clear the bit + HWREG(ui32Base + GPT_O_ANDCCP) &= ~(GPT_ANDCCP_CCP_AND_EN); +} + +//***************************************************************************** +// +//! \brief Sets the Match Register Update mode. +//! +//! This function controls when the Match Register value and Prescale Register value +//! are applied after writing these registers while a timer is enabled. +//! +//! \note If the timer is disabled when setting the update mode the Match Register +//! and Prescale Register values are applied immediately when enabling the timer. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to configure; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Mode sets the mode: +//! - \ref TIMER_MATCHUPDATE_NEXTCYCLE : Apply Match Register and Prescale Register on next clock +//! cycle after writing any of these registers. +//! - \ref TIMER_MATCHUPDATE_TIMEOUT : Apply Match Register and Prescale Register on next timeout +//! after writing any of these registers. +//! +//! \return None +// +//***************************************************************************** +extern void TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode); + +//***************************************************************************** +// +//! \brief Sets the Interval Load mode. +//! +//! This function controls when the Timer Register and Prescale Snap-shot (if used) +//! are updated. +//! +//! Timer Register (TAR/TBR) is updated when Interval Load Register (TAILR/TBILR) is written +//! and the Prescale Snap-shot (TAPS/TBPS) is updated when Prescale Register (TAPR/TBPR) is +//! written depending on the mode of operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to configure; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Mode sets the mode: +//! - \ref TIMER_INTERVALLOAD_NEXTCYCLE : Update Timer Register and Prescale Snap-shot on next clock +//! cycle after writing Interval Load Register or Prescale Register, respectively. +//! - \ref TIMER_INTERVALLOAD_TIMEOUT : Update Timer Register and Prescale Snap-shot on next timeout +//! after writing Interval Load Register or Prescale Register, respectively. +//! +//! \return None +// +//***************************************************************************** +extern void TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_TimerConfigure + #undef TimerConfigure + #define TimerConfigure ROM_TimerConfigure + #endif + #ifdef ROM_TimerLevelControl + #undef TimerLevelControl + #define TimerLevelControl ROM_TimerLevelControl + #endif + #ifdef ROM_TimerStallControl + #undef TimerStallControl + #define TimerStallControl ROM_TimerStallControl + #endif + #ifdef ROM_TimerWaitOnTriggerControl + #undef TimerWaitOnTriggerControl + #define TimerWaitOnTriggerControl ROM_TimerWaitOnTriggerControl + #endif + #ifdef ROM_TimerIntRegister + #undef TimerIntRegister + #define TimerIntRegister ROM_TimerIntRegister + #endif + #ifdef ROM_TimerIntUnregister + #undef TimerIntUnregister + #define TimerIntUnregister ROM_TimerIntUnregister + #endif + #ifdef ROM_TimerMatchUpdateMode + #undef TimerMatchUpdateMode + #define TimerMatchUpdateMode ROM_TimerMatchUpdateMode + #endif + #ifdef ROM_TimerIntervalLoadMode + #undef TimerIntervalLoadMode + #define TimerIntervalLoadMode ROM_TimerIntervalLoadMode + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer_doc.h new file mode 100644 index 0000000..d15c086 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer_doc.h @@ -0,0 +1,121 @@ +/****************************************************************************** +* Filename: timer_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup timer_api +//! @{ +//! \section sec_timer Introduction +//! +//! The timer API provides a set of functions for using the general-purpose timer module. +//! +//! The timer module contains four timer blocks with the following functional options: +//! - Operating modes: +//! - 16-bit with 8-bit prescaler or 32-bit programmable one-shot timer. +//! - 16-bit with 8-bit prescaler or 32-bit programmable periodic timer. +//! - Two capture compare PWM pins (CCP) for each 32-bit timer. +//! - 24-bit input-edge count or 24-bit time-capture modes. +//! - 24-bit PWM mode with software-programmable output inversion of the PWM signal. +//! - Count up or down. +//! - Daisy chaining of timer modules allows a single timer to initiate multiple timing events. +//! - Timer synchronization allows selected timers to start counting on the same clock cycle. +//! - User-enabled stalling when the System CPU asserts a CPU Halt flag during debug. +//! - Ability to determine the elapsed time between the assertion of the timer interrupt and +//! entry into the interrupt service routine. +//! +//! Each timer block provides two half-width timers/counters that can be configured +//! to operate independently as timers or event counters or to operate as a combined +//! full-width timer. +//! The timers provide 16-bit half-width timers and a 32-bit full-width timer. +//! For the purposes of this API, the two +//! half-width timers provided by a timer block are referred to as TimerA and +//! TimerB, and the full-width timer is referred to as TimerA. +//! +//! When in half-width mode, the timer can also be configured for event capture or +//! as a pulse width modulation (PWM) generator. When configured for event +//! capture, the timer acts as a counter. It can be configured to count either the +//! time between events or the events themselves. The type of event +//! being counted can be configured as a positive edge, a negative edge, or both +//! edges. When a timer is configured as a PWM generator, the input signal used to +//! capture events becomes an output signal, and the timer drives an +//! edge-aligned pulse onto that signal. +//! +//! Control is also provided over interrupt sources and events. Interrupts can be +//! generated to indicate that an event has been captured, or that a certain number +//! of events have been captured. Interrupts can also be generated when the timer +//! has counted down to 0 or when the timer matches a certain value. +//! +//! Timer configuration is handled by \ref TimerConfigure(), which performs the high +//! level setup of the timer module; that is, it is used to set up full- or +//! half-width modes, and to select between PWM, capture, and timer operations. +//! +//! \section sec_timer_api API +//! +//! The API functions can be grouped like this: +//! +//! Functions to perform timer control: +//! - \ref TimerConfigure() +//! - \ref TimerEnable() +//! - \ref TimerDisable() +//! - \ref TimerLevelControl() +//! - \ref TimerWaitOnTriggerControl() +//! - \ref TimerEventControl() +//! - \ref TimerStallControl() +//! - \ref TimerIntervalLoadMode() +//! - \ref TimerMatchUpdateMode() +//! - \ref TimerCcpCombineDisable() +//! - \ref TimerCcpCombineEnable() +//! +//! Functions to manage timer content: +//! - \ref TimerLoadSet() +//! - \ref TimerLoadGet() +//! - \ref TimerPrescaleSet() +//! - \ref TimerPrescaleGet() +//! - \ref TimerMatchSet() +//! - \ref TimerMatchGet() +//! - \ref TimerPrescaleMatchSet() +//! - \ref TimerPrescaleMatchGet() +//! - \ref TimerValueGet() +//! - \ref TimerSynchronize() +//! +//! Functions to manage the interrupt handler for the timer interrupt: +//! - \ref TimerIntRegister() +//! - \ref TimerIntUnregister() +//! +//! The individual interrupt sources within the timer module are managed with: +//! - \ref TimerIntEnable() +//! - \ref TimerIntDisable() +//! - \ref TimerIntStatus() +//! - \ref TimerIntClear() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/trng.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/trng.c new file mode 100644 index 0000000..7c1c4e1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/trng.c @@ -0,0 +1,112 @@ +/****************************************************************************** +* Filename: trng.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the TRNG module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "trng.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef TRNGConfigure + #define TRNGConfigure NOROM_TRNGConfigure + #undef TRNGNumberGet + #define TRNGNumberGet NOROM_TRNGNumberGet +#endif + +//***************************************************************************** +// +// Configure the true random number generator +// +//***************************************************************************** +void +TRNGConfigure(uint32_t ui32MinSamplesPerCycle, + uint32_t ui32MaxSamplesPerCycle, + uint32_t ui32ClocksPerSample) +{ + uint32_t ui32Val; + + // Make sure the TRNG is disabled. + ui32Val = HWREG(TRNG_BASE + TRNG_O_CTL) & ~TRNG_CTL_TRNG_EN; + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // Configure the startup number of samples. + ui32Val &= ~TRNG_CTL_STARTUP_CYCLES_M; + ui32Val |= ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CTL_STARTUP_CYCLES_S ) & TRNG_CTL_STARTUP_CYCLES_M ); + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // Configure the minimum and maximum number of samples pr generated number + // and the number of clocks per sample. + HWREG(TRNG_BASE + TRNG_O_CFG0) = ( + ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CFG0_MAX_REFILL_CYCLES_S ) & TRNG_CFG0_MAX_REFILL_CYCLES_M ) | + ((( ui32ClocksPerSample ) << TRNG_CFG0_SMPL_DIV_S ) & TRNG_CFG0_SMPL_DIV_M ) | + ((( ui32MinSamplesPerCycle >> 6 ) << TRNG_CFG0_MIN_REFILL_CYCLES_S ) & TRNG_CFG0_MIN_REFILL_CYCLES_M ) ); +} + +//***************************************************************************** +// +// Get a random number from the generator +// +//***************************************************************************** +uint32_t +TRNGNumberGet(uint32_t ui32Word) +{ + uint32_t ui32RandomNumber; + + // Check the arguments. + ASSERT((ui32Word == TRNG_HI_WORD) || + (ui32Word == TRNG_LOW_WORD)); + + // Return the right requested part of the generated number. + if(ui32Word == TRNG_HI_WORD) + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT1); + } + else + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT0); + } + + // Initiate generation of new number. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1; + + // Return the random number. + return ui32RandomNumber; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/trng.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/trng.h new file mode 100644 index 0000000..08a485b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/trng.h @@ -0,0 +1,451 @@ +/****************************************************************************** +* Filename: trng.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and prototypes for the true random number gen. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup trng_api +//! @{ +// +//***************************************************************************** + +#ifndef __TRNG_H__ +#define __TRNG_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_trng.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define TRNGConfigure NOROM_TRNGConfigure + #define TRNGNumberGet NOROM_TRNGNumberGet +#endif + +//***************************************************************************** +// +// +// +//***************************************************************************** +#define TRNG_NUMBER_READY 0x00000001 // +#define TRNG_FRO_SHUTDOWN 0x00000002 // +#define TRNG_NEED_CLOCK 0x80000000 // + +#define TRNG_HI_WORD 0x00000001 +#define TRNG_LOW_WORD 0x00000002 + +//***************************************************************************** +// +// API Function and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure the true random number generator. +//! +//! Use this function to set the minimum and maximum number of samples required +//! in each generation of a new random number. +//! +//! \param ui32MinSamplesPerCycle is the minimum number of samples per each +//! generated random number. Constraints: +//! - Value must be bigger than or equal to 2^6 and less than 2^14. +//! - The 6 LSBs of the argument are truncated. +//! - If the value is zero, the number of samples is fixed to the value determined +//! by ui32MaxSamplesPerCycle. To ensure same entropy in all generated random +//! numbers the value 0 should be used. +//! \param ui32MaxSamplesPerCycle is the maximum number of samples per each +//! generated random number. Constraints: +//! - Value must be between 2^8 and 2^24 (both included). +//! - The 8 LSBs of the argument are truncated. +//! - Value 0 and 2^24 both give the highest possible value. +//! \param ui32ClocksPerSample is the number of clock cycles for each time +//! a new sample is generated from the FROs. +//! - 0 : Every sample. +//! - 1 : Every second sample. +//! - ... +//! - 15 : Every 16. sample. +//! +//! \return None +// +//***************************************************************************** +extern void TRNGConfigure(uint32_t ui32MinSamplesPerCycle, + uint32_t ui32MaxSamplesPerCycle, + uint32_t ui32ClocksPerSample); + +//***************************************************************************** +// +//! \brief Enable the TRNG. +//! +//! Enable the TRNG to start preparing a random number. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGEnable(void) +{ + // Enable the TRNG. + HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disable the TRNG module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGDisable(void) +{ + // Enable the TRNG + HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Get a random number from the generator. +//! +//! Use this function to get either the high or low part of the 64 bit +//! generated number. +//! +//! \note Data from this register is only valid if the TRNG has produced a +//! number. Use \ref TRNGStatusGet() to poll the for status. After calling this +//! function a new random number will be generated. +//! +//! \param ui32Word determines if whether to return the high or low 32 bits. +//! - \ref TRNG_HI_WORD +//! - \ref TRNG_LOW_WORD +//! +//! \return Return either the high or low part of the 64 bit generated random +//! number. +// +//***************************************************************************** +extern uint32_t TRNGNumberGet(uint32_t ui32Word); + +//***************************************************************************** +// +//! \brief Get the status of the TRNG. +//! +//! Use this function to retrieve the status of the TRNG. +//! +//! \return Returns the current status of the TRNG module. +//! The returned status is a bitwise OR'ed combination of: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! - \ref TRNG_NEED_CLOCK +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TRNGStatusGet(void) +{ + // Return the status. + return (HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); +} + +//***************************************************************************** +// +//! \brief Reset the TRNG. +//! +//! Use this function to reset the TRNG module. Reset will be low for +//! approximately 5 clock cycles. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGReset(void) +{ + // Reset the TRNG. + HWREG(TRNG_BASE + TRNG_O_SWRESET) = 1; +} + +//***************************************************************************** +// +//! \brief Enables individual TRNG interrupt sources. +//! +//! This function enables the indicated TRNG interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntEnable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || + (ui32IntFlags & TRNG_FRO_SHUTDOWN)); + + // Enable the specified interrupts. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual TRNG interrupt sources. +//! +//! This function disables the indicated TRNG interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntDisable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || + (ui32IntFlags & TRNG_FRO_SHUTDOWN)); + + // Disable the specified interrupts. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status of the TRNG module. +//! +//! This function returns the interrupt status for the specified TRNG. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param bMasked selects either raw or masked interrupt status. +//! - \c true : Masked interrupt. +//! - \c false : Raw interrupt. +//! +//! \return Returns the current interrupt status, enumerated as: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TRNGIntStatus(bool bMasked) +{ + uint32_t ui32Mask; + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + ui32Mask = HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK); + return(ui32Mask & HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); + } + else + { + return(HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT) & 0x00000003); + } +} + +//***************************************************************************** +// +//! \brief Clears TRNG interrupt sources. +//! +//! The specified TRNG interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntClear(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || + (ui32IntFlags & TRNG_FRO_SHUTDOWN)); + + // Clear the requested interrupt sources. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for a TRNG interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific TRNG interrupts must be enabled via \ref TRNGIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! TRNG interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_TRNG_IRQ, pfnHandler); + + // Enable the TRNG interrupt. + IntEnable(INT_TRNG_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a TRNG interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a Crypto interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntUnregister(void) +{ + // Disable the interrupt. + IntDisable(INT_TRNG_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_TRNG_IRQ); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_TRNGConfigure + #undef TRNGConfigure + #define TRNGConfigure ROM_TRNGConfigure + #endif + #ifdef ROM_TRNGNumberGet + #undef TRNGNumberGet + #define TRNGNumberGet ROM_TRNGNumberGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __TRNG_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart.c new file mode 100644 index 0000000..589e928 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart.c @@ -0,0 +1,296 @@ +/****************************************************************************** +* Filename: uart.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the UART. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "uart.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef UARTFIFOLevelGet + #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet + #undef UARTConfigSetExpClk + #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk + #undef UARTConfigGetExpClk + #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk + #undef UARTDisable + #define UARTDisable NOROM_UARTDisable + #undef UARTCharGetNonBlocking + #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking + #undef UARTCharGet + #define UARTCharGet NOROM_UARTCharGet + #undef UARTCharPutNonBlocking + #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking + #undef UARTCharPut + #define UARTCharPut NOROM_UARTCharPut + #undef UARTIntRegister + #define UARTIntRegister NOROM_UARTIntRegister + #undef UARTIntUnregister + #define UARTIntUnregister NOROM_UARTIntUnregister +#endif + +//***************************************************************************** +// +// Gets the FIFO level at which interrupts are generated +// +//***************************************************************************** +void +UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel) +{ + uint32_t ui32Temp; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Read the FIFO level register. + ui32Temp = HWREG(ui32Base + UART_O_IFLS); + + // Extract the transmit and receive FIFO levels. + *pui32TxLevel = ui32Temp & UART_IFLS_TXSEL_M; + *pui32RxLevel = ui32Temp & UART_IFLS_RXSEL_M; +} + +//***************************************************************************** +// +// Sets the configuration of a UART +// +//***************************************************************************** +void +UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config) +{ + uint32_t ui32Div; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT(ui32Baud != 0); + + // Stop the UART. + UARTDisable(ui32Base); + + // Compute the fractional baud rate divider. + ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; + + // Set the baud rate. + HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; + HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; + + // Set parity, data length, and number of stop bits. + HWREG(ui32Base + UART_O_LCRH) = ui32Config; +} + +//***************************************************************************** +// +// Gets the current configuration of a UART +// +//***************************************************************************** +void +UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config) +{ + uint32_t ui32Int, ui32Frac; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Compute the baud rate. + ui32Int = HWREG(ui32Base + UART_O_IBRD); + ui32Frac = HWREG(ui32Base + UART_O_FBRD); + *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); + + // Get the parity, data length, and number of stop bits. + *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | + UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +// Disables transmitting and receiving +// +//***************************************************************************** +void +UARTDisable(uint32_t ui32Base) +{ + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait for end of TX. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) + { + } + + // Disable the FIFO. + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); + + // Disable the UART. + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +// Receives a character from the specified port +// +//***************************************************************************** +int32_t +UARTCharGetNonBlocking(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // See if there are any characters in the receive FIFO. + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) + { + // Read and return the next character. + return(HWREG(ui32Base + UART_O_DR)); + } + else + { + // There are no characters, so return a failure. + return(-1); + } +} + +//***************************************************************************** +// +// Waits for a character from the specified port +// +//***************************************************************************** +int32_t +UARTCharGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait until a char is available. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) + { + } + + // Now get the character. + return(HWREG(ui32Base + UART_O_DR)); +} + +//***************************************************************************** +// +// Sends a character to the specified port +// +//***************************************************************************** +bool +UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // See if there is space in the transmit FIFO. + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) + { + // Write this character to the transmit FIFO. + HWREG(ui32Base + UART_O_DR) = ui8Data; + + // Success. + return(true); + } + else + { + // There is no space in the transmit FIFO, so return a failure. + return(false); + } +} + +//***************************************************************************** +// +// Waits to send a character from the specified port +// +//***************************************************************************** +void +UARTCharPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait until space is available. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) + { + } + + // Send the char. + HWREG(ui32Base + UART_O_DR) = ui8Data; +} + +//***************************************************************************** +// +// Registers an interrupt handler for a UART interrupt +// +//***************************************************************************** +void +UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Register the interrupt handler. + IntRegister(INT_UART0_COMB, pfnHandler); + + // Enable the UART interrupt. + IntEnable(INT_UART0_COMB); +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for a UART interrupt +// +//***************************************************************************** +void +UARTIntUnregister(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Disable the interrupt. + IntDisable(INT_UART0_COMB); + + // Unregister the interrupt handler. + IntUnregister(INT_UART0_COMB); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart.h new file mode 100644 index 0000000..e9e71ca --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart.h @@ -0,0 +1,1091 @@ +/****************************************************************************** +* Filename: uart.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Defines and prototypes for the UART. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_uart.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet + #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk + #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk + #define UARTDisable NOROM_UARTDisable + #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking + #define UARTCharGet NOROM_UARTCharGet + #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking + #define UARTCharPut NOROM_UARTCharPut + #define UARTIntRegister NOROM_UARTIntRegister + #define UARTIntUnregister NOROM_UARTIntUnregister +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ui32IntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE ( UART_IMSC_OEIM ) // Overrun Error Interrupt Mask +#define UART_INT_BE ( UART_IMSC_BEIM ) // Break Error Interrupt Mask +#define UART_INT_PE ( UART_IMSC_PEIM ) // Parity Error Interrupt Mask +#define UART_INT_FE ( UART_IMSC_FEIM ) // Framing Error Interrupt Mask +#define UART_INT_RT ( UART_IMSC_RTIM ) // Receive Timeout Interrupt Mask +#define UART_INT_TX ( UART_IMSC_TXIM ) // Transmit Interrupt Mask +#define UART_INT_RX ( UART_IMSC_RXIM ) // Receive Interrupt Mask +#define UART_INT_CTS ( UART_IMSC_CTSMIM ) // CTS Modem Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter +// and returned by UARTConfigGetExpClk in the pui32Config parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ui32Parity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32TxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32RxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 + +//***************************************************************************** +// +// Values returned from the UARTBusy(). +// +//***************************************************************************** +#define UART_BUSY 0x00000001 +#define UART_IDLE 0x00000000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks a UART base address. +//! +//! This function determines if a UART port base address is valid. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +UARTBaseValid(uint32_t ui32Base) +{ + return(( ui32Base == UART0_BASE ) || ( ui32Base == UART0_NONBUF_BASE )); +} +#endif + +//***************************************************************************** +// +//! \brief Sets the type of parity. +//! +//! This function sets the type of parity to use for transmitting and expect +//! when receiving. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Parity specifies the type of parity to use. The last two allow +//! direct control of the parity bit; it is always either one or zero based on +//! the mode. +//! - \ref UART_CONFIG_PAR_NONE +//! - \ref UART_CONFIG_PAR_EVEN +//! - \ref UART_CONFIG_PAR_ODD +//! - \ref UART_CONFIG_PAR_ONE +//! - \ref UART_CONFIG_PAR_ZERO +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) || + (ui32Parity == UART_CONFIG_PAR_EVEN) || + (ui32Parity == UART_CONFIG_PAR_ODD) || + (ui32Parity == UART_CONFIG_PAR_ONE) || + (ui32Parity == UART_CONFIG_PAR_ZERO)); + + // Set the parity mode. + HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & + ~(UART_LCRH_SPS | UART_LCRH_EPS | + UART_LCRH_PEN)) | ui32Parity); +} + +//***************************************************************************** +// +//! \brief Gets the type of parity currently being used. +//! +//! This function gets the type of parity used for transmitting data and +//! expected when receiving data. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns the current parity settings, specified as one of: +//! - \ref UART_CONFIG_PAR_NONE +//! - \ref UART_CONFIG_PAR_EVEN +//! - \ref UART_CONFIG_PAR_ODD +//! - \ref UART_CONFIG_PAR_ONE +//! - \ref UART_CONFIG_PAR_ZERO +// +//***************************************************************************** +__STATIC_INLINE uint32_t +UARTParityModeGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the current parity setting + return(HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +//! \brief Sets the FIFO level at which interrupts are generated. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one of: +//! - \ref UART_FIFO_TX1_8 +//! - \ref UART_FIFO_TX2_8 +//! - \ref UART_FIFO_TX4_8 +//! - \ref UART_FIFO_TX6_8 +//! - \ref UART_FIFO_TX7_8 +//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of: +//! - \ref UART_FIFO_RX1_8 +//! - \ref UART_FIFO_RX2_8 +//! - \ref UART_FIFO_RX4_8 +//! - \ref UART_FIFO_RX6_8 +//! - \ref UART_FIFO_RX7_8 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, + uint32_t ui32RxLevel) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32TxLevel == UART_FIFO_TX1_8) || + (ui32TxLevel == UART_FIFO_TX2_8) || + (ui32TxLevel == UART_FIFO_TX4_8) || + (ui32TxLevel == UART_FIFO_TX6_8) || + (ui32TxLevel == UART_FIFO_TX7_8)); + ASSERT((ui32RxLevel == UART_FIFO_RX1_8) || + (ui32RxLevel == UART_FIFO_RX2_8) || + (ui32RxLevel == UART_FIFO_RX4_8) || + (ui32RxLevel == UART_FIFO_RX6_8) || + (ui32RxLevel == UART_FIFO_RX7_8)); + + // Set the FIFO interrupt levels. + HWREG(ui32Base + UART_O_IFLS) = ui32TxLevel | ui32RxLevel; +} + +//***************************************************************************** +// +//! \brief Gets the FIFO level at which interrupts are generated. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of: +//! - \ref UART_FIFO_TX1_8 +//! - \ref UART_FIFO_TX2_8 +//! - \ref UART_FIFO_TX4_8 +//! - \ref UART_FIFO_TX6_8 +//! - \ref UART_FIFO_TX7_8 +//! \param pui32RxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of: +//! - \ref UART_FIFO_RX1_8 +//! - \ref UART_FIFO_RX2_8 +//! - \ref UART_FIFO_RX4_8 +//! - \ref UART_FIFO_RX6_8 +//! - \ref UART_FIFO_RX7_8 +//! +//! \return None +// +//***************************************************************************** +extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel); + +//***************************************************************************** +// +//! \brief Sets the configuration of a UART. +//! +//! This function configures the UART for operation in the specified data +//! format. +//! +//! \note The peripheral clock is not necessarily the same as the processor +//! clock. The frequency of the peripheral clock is set by the system control. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param ui32Baud is the desired baud rate. +//! - Minimum baud rate: ui32Baud >= ceil(ui32UARTClk / 1,048,559.875) +//! - Maximum baud rate: ui32Baud <= floor(ui32UARTClk / 15.875) +//! \param ui32Config is the data format for the port. +//! The parameter is the bitwise OR of three values: +//! - Number of data bits +//! - \ref UART_CONFIG_WLEN_8 : 8 data bits per byte. +//! - \ref UART_CONFIG_WLEN_7 : 7 data bits per byte. +//! - \ref UART_CONFIG_WLEN_6 : 6 data bits per byte. +//! - \ref UART_CONFIG_WLEN_5 : 5 data bits per byte. +//! - Number of stop bits +//! - \ref UART_CONFIG_STOP_ONE : One stop bit. +//! - \ref UART_CONFIG_STOP_TWO : Two stop bits. +//! - Parity +//! - \ref UART_CONFIG_PAR_NONE +//! - \ref UART_CONFIG_PAR_EVEN +//! - \ref UART_CONFIG_PAR_ODD +//! - \ref UART_CONFIG_PAR_ONE +//! - \ref UART_CONFIG_PAR_ZERO +//! +//! \return None +// +//***************************************************************************** +extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config); + +//***************************************************************************** +// +//! \brief Gets the current configuration of a UART. +//! +//! The baud rate and data format for the UART is determined, given an +//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an "official" baud rate. The data format returned in +//! \c pui32Config is enumerated the same as the \c ui32Config parameter of +//! \ref UARTConfigSetExpClk(). +//! +//! \note The peripheral clock is not necessarily the same as the processor +//! clock. The frequency of the peripheral clock is set by the system control. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param pui32Baud is a pointer to storage for the baud rate. +//! \param pui32Config is a pointer to storage for the data format. +//! +//! \return None +// +//***************************************************************************** +extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config); + +//***************************************************************************** +// +//! \brief Enables transmitting and receiving. +//! +//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit +//! and receive FIFOs. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Enable the FIFO. + HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; + + // Enable RX, TX, and the UART. + HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +//! \brief Disables transmitting and receiving. +//! +//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of +//! transmission of the current character, and flushes the transmit FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +extern void UARTDisable(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables the transmit and receive FIFOs. +//! +//! This functions enables the transmit and receive FIFOs in the UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTFIFOEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Enable the FIFO. + HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; +} + +//***************************************************************************** +// +//! \brief Disables the transmit and receive FIFOs. +//! +//! This functions disables the transmit and receive FIFOs in the UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTFIFODisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Disable the FIFO. + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); +} + +//***************************************************************************** +// +//! \brief Determines if there are any characters in the receive FIFO. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns status of the receive FIFO. +//! - \c true : There is data in the receive FIFO. +//! - \c false : There is no data in the receive FIFO. +// +//***************************************************************************** +__STATIC_INLINE bool +UARTCharsAvail(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the availability of characters. + return((HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) ? false : true); +} + +//***************************************************************************** +// +//! \brief Determines if there is any space in the transmit FIFO. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns status of the transmit FIFO. +//! - \c true : There is space available in the transmit FIFO. +//! - \c false : There is no space available in the transmit FIFO. +// +//***************************************************************************** +__STATIC_INLINE bool +UARTSpaceAvail(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the availability of space. + return((HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) ? false : true); +} + +//***************************************************************************** +// +//! \brief Receives a character from the specified port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. +//! +//! \note The \ref UARTCharsAvail() function should be called before +//! attempting to call this function. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns the character read from the specified port, cast as an +//! \c int32_t. A \c -1 is returned if there are no characters present in the +//! receive FIFO. +//! +//! \sa \ref UARTCharsAvail() +// +//***************************************************************************** +extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Waits for a character from the specified port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. If there are no characters available, this function waits until a +//! character is received before returning. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns the character read from the specified port, cast as an +//! \c int32_t. +// +//***************************************************************************** +extern int32_t UARTCharGet(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Sends a character to the specified port. +//! +//! This function writes the character \c ui8Data to the transmit FIFO for the +//! specified port. This function does not block, so if there is no space +//! available, then a \c false is returned, and the application must retry the +//! function later. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui8Data is the character to be transmitted. +//! +//! \return Returns status of the character transmit. +//! - \c true : The character was successfully placed in the transmit FIFO. +//! - \c false : There was no space available in the transmit FIFO. Try again later. +// +//***************************************************************************** +extern bool UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data); + +//***************************************************************************** +// +//! \brief Waits to send a character from the specified port. +//! +//! This function sends the character \c ui8Data to the transmit FIFO for the +//! specified port. If there is no space available in the transmit FIFO, this +//! function waits until there is space available before returning. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui8Data is the character to be transmitted. +//! +//! \return None +// +//***************************************************************************** +extern void UARTCharPut(uint32_t ui32Base, uint8_t ui8Data); + +//***************************************************************************** +// +//! \brief Determines whether the UART transmitter is busy or not. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \c false is returned, the transmit FIFO is +//! empty and all bits of the last transmitted character, including all stop +//! bits, have left the hardware shift register. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns status of UART transmitter. +//! - \c true : UART is transmitting. +//! - \c false : All transmissions are complete. +// +//***************************************************************************** +__STATIC_INLINE bool +UARTBusy(uint32_t ui32Base) +{ + // Check the argument. + ASSERT(UARTBaseValid(ui32Base)); + + // Determine if the UART is busy. + return((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? + UART_BUSY : UART_IDLE); +} + +//***************************************************************************** +// +//! \brief Causes a BREAK to be sent. +//! +//! \note For proper transmission of a break +//! command, the break must be asserted for at least two complete frames. +//! +//! \param ui32Base is the base address of the UART port. +//! \param bBreakState controls the output level. +//! - \c true : Asserts a break condition on the UART. +//! - \c false : Removes the break condition. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTBreakCtl(uint32_t ui32Base, bool bBreakState) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Set the break condition as requested. + HWREG(ui32Base + UART_O_LCRH) = + (bBreakState ? + (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : + (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for a UART interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific UART interrupts must be enabled via \ref UARTIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \param ui32Base is the base address of the UART module. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a UART interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a UART interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \param ui32Base is the base address of the UART module. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void UARTIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables individual UART interrupt sources. +//! +//! This function enables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(ui32Base + UART_O_IMSC) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual UART interrupt sources. +//! +//! This function disables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(ui32Base + UART_O_IMSC) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the specified UART. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the UART port. +//! \param bMasked selects either raw or masked interrupt. +//! - \c true : Masked interrupt status is required. +//! - \c false : Raw interrupt status is required. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of: +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +UARTIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return(HWREG(ui32Base + UART_O_MIS)); + } + else + { + return(HWREG(ui32Base + UART_O_RIS)); + } +} + +//***************************************************************************** +// +//! \brief Clears UART interrupt sources. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments + ASSERT(UARTBaseValid(ui32Base)); + + // Clear the requested interrupt sources + HWREG(ui32Base + UART_O_ICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Enable UART DMA operation. +//! +//! The specified UART DMA features are enabled. The UART can be +//! configured to use DMA for transmit or receive, and to disable +//! receive if an error occurs. +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the UART. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32DMAFlags is a bit mask of the DMA features to enable. +//! The parameter is the bitwise OR of any of the following values: +//! - UART_DMA_RX : Enable DMA for receive. +//! - UART_DMA_TX : Enable DMA for transmit. +//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Set the requested bits in the UART DMA control register. + HWREG(ui32Base + UART_O_DMACTL) |= ui32DMAFlags; +} + +//***************************************************************************** +// +//! \brief Disable UART DMA operation. +//! +//! This function is used to disable UART DMA features that were enabled +//! by \ref UARTDMAEnable(). The specified UART DMA features are disabled. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32DMAFlags is a bit mask of the DMA features to disable. +//! The parameter is the bitwise OR of any of the following values: +//! - UART_DMA_RX : Enable DMA for receive. +//! - UART_DMA_TX : Enable DMA for transmit. +//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Clear the requested bits in the UART DMA control register. + HWREG(ui32Base + UART_O_DMACTL) &= ~ui32DMAFlags; +} + +//***************************************************************************** +// +//! \brief Gets current receiver errors. +//! +//! This function returns the current state of each of the 4 receiver error +//! sources. The returned errors are equivalent to the four error bits +//! returned via the previous call to \ref UARTCharGet() or \ref UARTCharGetNonBlocking() +//! with the exception that the overrun error is set immediately the overrun +//! occurs rather than when a character is next read. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns a bitwise OR combination of the receiver error flags: +//! - \ref UART_RXERROR_FRAMING +//! - \ref UART_RXERROR_PARITY +//! - \ref UART_RXERROR_BREAK +//! - \ref UART_RXERROR_OVERRUN +// +//***************************************************************************** +__STATIC_INLINE uint32_t +UARTRxErrorGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the current value of the receive status register. + return(HWREG(ui32Base + UART_O_RSR) & 0x0000000F); +} + +//***************************************************************************** +// +//! \brief Clears all reported receiver errors. +//! +//! This function is used to clear all receiver error conditions reported via +//! \ref UARTRxErrorGet(). If using the overrun, framing error, parity error or +//! break interrupts, this function must be called after clearing the interrupt +//! to ensure that later errors of the same type trigger another interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTRxErrorClear(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Any write to the Error Clear Register will clear all bits which are + // currently set. + HWREG(ui32Base + UART_O_ECR) = 0; +} + +//***************************************************************************** +// +//! \brief Enables hardware flow control for both CTS and RTS +//! +//! Hardware flow control is disabled by default. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTHwFlowControlEnable( uint32_t ui32Base ) +{ + // Check the arguments. + ASSERT( UARTBaseValid( ui32Base )); + + HWREG( ui32Base + UART_O_CTL ) |= ( UART_CTL_CTSEN | UART_CTL_RTSEN ); +} + +//***************************************************************************** +// +//! \brief Disables hardware flow control for both CTS and RTS +//! +//! Hardware flow control is disabled by default. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTHwFlowControlDisable( uint32_t ui32Base ) +{ + // Check the arguments. + ASSERT( UARTBaseValid( ui32Base )); + + HWREG( ui32Base + UART_O_CTL ) &= ~( UART_CTL_CTSEN | UART_CTL_RTSEN ); +} + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_UARTFIFOLevelGet + #undef UARTFIFOLevelGet + #define UARTFIFOLevelGet ROM_UARTFIFOLevelGet + #endif + #ifdef ROM_UARTConfigSetExpClk + #undef UARTConfigSetExpClk + #define UARTConfigSetExpClk ROM_UARTConfigSetExpClk + #endif + #ifdef ROM_UARTConfigGetExpClk + #undef UARTConfigGetExpClk + #define UARTConfigGetExpClk ROM_UARTConfigGetExpClk + #endif + #ifdef ROM_UARTDisable + #undef UARTDisable + #define UARTDisable ROM_UARTDisable + #endif + #ifdef ROM_UARTCharGetNonBlocking + #undef UARTCharGetNonBlocking + #define UARTCharGetNonBlocking ROM_UARTCharGetNonBlocking + #endif + #ifdef ROM_UARTCharGet + #undef UARTCharGet + #define UARTCharGet ROM_UARTCharGet + #endif + #ifdef ROM_UARTCharPutNonBlocking + #undef UARTCharPutNonBlocking + #define UARTCharPutNonBlocking ROM_UARTCharPutNonBlocking + #endif + #ifdef ROM_UARTCharPut + #undef UARTCharPut + #define UARTCharPut ROM_UARTCharPut + #endif + #ifdef ROM_UARTIntRegister + #undef UARTIntRegister + #define UARTIntRegister ROM_UARTIntRegister + #endif + #ifdef ROM_UARTIntUnregister + #undef UARTIntUnregister + #define UARTIntUnregister ROM_UARTIntUnregister + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart_doc.h new file mode 100644 index 0000000..ba77f94 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart_doc.h @@ -0,0 +1,107 @@ +/****************************************************************************** +* Filename: uart_doc.h +* Revised: 2018-02-09 15:45:36 +0100 (fr, 09 feb 2018) +* Revision: 51470 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +/*! +\addtogroup uart_api +@{ + +\section sec_uart_printf Use printf() + +DriverLib only supports writing a single character at a time to the UART buffer but it is +possible to utilize the library function \c printf by overriding a few of the functions used by +\c printf with a device specific definition. However, the implementation of \c printf is +compiler specific and requires different functions to be overridden depending on the compiler. + +Using \c printf can increase code size significantly but some compilers provide a highly optimized +and configurable implementation suitable for embedded systems which makes the code size increase +acceptable for most applications. See the compiler's documentation for details about how to +configure the \c printf library function. + +It is required that the application configures and enables the UART module before using \c printf +function. + +\subsection sec_uart_printf_ccs Code Composer Studio + +In Code Composer Studio the functions \c fputc and \c fputs must be overridden. + +\code{.c} +#include +#include + +#define PRINTF_UART UART0_BASE + +// Override 'fputc' function in order to use printf() to output to UART +int fputc(int _c, register FILE *_fp) +{ + UARTCharPut(PRINTF_UART, (uint8_t)_c); + return _c; +} + +// Override 'fputs' function in order to use printf() to output to UART +int fputs(const char *_ptr, register FILE *_fp) +{ + unsigned int i, len; + + len = strlen(_ptr); + + for(i=0 ; i +#include + +#define PRINTF_UART UART0_BASE + +// Override 'putchar' function in order to use printf() to output to UART. +int putchar(int data) +{ + UARTCharPut(PRINTF_UART, (uint8_t)data); + return data; +} +\endcode + +@} +*/ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/udma.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/udma.c new file mode 100644 index 0000000..0665a42 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/udma.c @@ -0,0 +1,448 @@ +/****************************************************************************** +* Filename: udma.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the uDMA controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "udma.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef uDMAChannelAttributeEnable + #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable + #undef uDMAChannelAttributeDisable + #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable + #undef uDMAChannelAttributeGet + #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet + #undef uDMAChannelControlSet + #define uDMAChannelControlSet NOROM_uDMAChannelControlSet + #undef uDMAChannelTransferSet + #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet + #undef uDMAChannelScatterGatherSet + #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet + #undef uDMAChannelSizeGet + #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet + #undef uDMAChannelModeGet + #define uDMAChannelModeGet NOROM_uDMAChannelModeGet +#endif + +//***************************************************************************** +// +// Enables attributes of a uDMA channel +// +//***************************************************************************** +void +uDMAChannelAttributeEnable(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32Attr) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Set the useburst bit for this channel if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_SETBURST) = 1 << ui32ChannelNum; + } + + // Set the alternate control select bit for this channel, + // if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // Set the high priority bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // Set the request mask bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_SETREQMASK) = 1 << ui32ChannelNum; + } +} + +//***************************************************************************** +// +// Disables attributes of an uDMA channel +// +//***************************************************************************** +void +uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32Attr) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Clear the useburst bit for this channel if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_CLEARBURST) = 1 << ui32ChannelNum; + } + + // Clear the alternate control select bit for this channel, if set in + // ululAttr. + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // Clear the high priority bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // Clear the request mask bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_CLEARREQMASK) = 1 << ui32ChannelNum; + } +} + +//***************************************************************************** +// +// Gets the enabled attributes of a uDMA channel +// +//***************************************************************************** +uint32_t +uDMAChannelAttributeGet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + uint32_t ui32Attr = 0; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Check to see if useburst bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETBURST) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_USEBURST; + } + + // Check to see if the alternate control bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_ALTSELECT; + } + + // Check to see if the high priority bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // Check to see if the request mask bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETREQMASK) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_REQMASK; + } + + // Return the configuration flags. + return(ui32Attr); +} + +//***************************************************************************** +// +// Sets the control parameters for a uDMA channel control structure +// +//***************************************************************************** +void +uDMAChannelControlSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, + uint32_t ui32Control) +{ + tDMAControlTable *pControlTable; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + pControlTable[ui32ChannelStructIndex].ui32Control = + ((pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_DST_INC_M | + UDMA_SRC_INC_M | + UDMA_SIZE_M | + UDMA_ARB_M | + UDMA_NEXT_USEBURST)) | + ui32Control); +} + +//***************************************************************************** +// +// Sets the transfer parameters for a uDMA channel control structure +// +//***************************************************************************** +void +uDMAChannelTransferSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, + uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, + uint32_t ui32TransferSize) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + uint32_t ui32Inc; + uint32_t ui32BufferBytes; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((uint32_t)pvSrcAddr >= SRAM_BASE); + ASSERT((uint32_t)pvDstAddr >= SRAM_BASE); + ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= UDMA_XFER_SIZE_MAX)); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off the mode and size + // fields. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // Adjust the mode if the alt control structure is selected. + if(ui32ChannelStructIndex & UDMA_ALT_SELECT) + { + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Mode |= UDMA_MODE_ALT_SELECT; + } + } + + // Set the transfer size and mode in the control word (but don't write the + // control word yet as it could kick off a transfer). + ui32Control |= ui32Mode | ((ui32TransferSize - 1) << UDMA_XFER_SIZE_S); + + // Get the address increment value for the source, from the control word. + ui32Inc = (ui32Control & UDMA_SRC_INC_M); + + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + if(ui32Inc != UDMA_SRC_INC_NONE) + { + ui32Inc = ui32Inc >> UDMA_SRC_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - (1 << ui32Inc)); + } + + // Load the source ending address into the control block. + pControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; + + // Get the address increment value for the destination, from the control + // word. + ui32Inc = ui32Control & UDMA_DST_INC_M; + + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + if(ui32Inc != UDMA_DST_INC_NONE) + { + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer needs to point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + pvDstAddr = + (void *)&pControlTable[ui32ChannelStructIndex | + UDMA_ALT_SELECT].ui32Spare; + } + // Not a scatter-gather transfer, calculate end pointer normally. + else + { + ui32Inc = ui32Inc >> UDMA_DST_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); + } + } + + // Load the destination ending address into the control block. + pControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; + + // Write the new control word value. + pControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; +} + +//***************************************************************************** +// +// Configures a uDMA channel for scatter-gather mode +// +//***************************************************************************** +void +uDMAChannelScatterGatherSet(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32TaskCount, void *pvTaskList, + uint32_t ui32IsPeriphSG) +{ + tDMAControlTable *pControlTable; + tDMAControlTable *pTaskTable; + + // Check the parameters. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(pvTaskList != 0); + ASSERT(ui32TaskCount <= UDMA_XFER_SIZE_MAX); + ASSERT(ui32TaskCount != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get a handy pointer to the task list. + pTaskTable = (tDMAControlTable *)pvTaskList; + + // Compute the ending address for the source pointer. This will be the + // last element of the last task in the task table. + pControlTable[ui32ChannelNum].pvSrcEndAddr = + &pTaskTable[ui32TaskCount - 1].ui32Spare; + + // Compute the ending address for the destination pointer. This will be + // the end of the alternate structure for this channel. + pControlTable[ui32ChannelNum].pvDstEndAddr = + &pControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; + + // Compute the control word. Most configurable items are fixed for + // scatter-gather. Item and increment sizes are all 32-bit and arb + // size must be 4. The count is the number of items in the task list + // times 4 (4 words per task). + pControlTable[ui32ChannelNum].ui32Control = + (UDMA_DST_INC_32 | UDMA_SRC_INC_32 | + UDMA_SIZE_32 | UDMA_ARB_4 | + (((ui32TaskCount * 4) - 1) << UDMA_XFER_SIZE_S) | + (ui32IsPeriphSG ? UDMA_MODE_PER_SCATTER_GATHER : + UDMA_MODE_MEM_SCATTER_GATHER)); + + // Scatter-gather operations can leave the alt bit set. So if doing + // back to back scatter-gather transfers, the second attempt may not + // work correctly because the alt bit is set. Therefore, clear the + // alt bit here to ensure that it is always cleared before a new SG + // transfer is started. + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + +} + +//***************************************************************************** +// +// Gets the current transfer size for a uDMA channel control structure +// +//***************************************************************************** +uint32_t +uDMAChannelSizeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off all but the size field + // and the mode field. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + (UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // If the size field and mode field are 0 then the transfer is finished + // and there are no more items to transfer. + if(ui32Control == 0) + { + return(0); + } + + // Otherwise, if either the size field or more field is non-zero, then + // not all the items have been transferred. + else + { + // Shift the size field and add one, then return to user. + return((ui32Control >> UDMA_XFER_SIZE_S) + 1); + } +} + +//***************************************************************************** +// +// Gets the transfer mode for a uDMA channel control structure +// +//***************************************************************************** +uint32_t +uDMAChannelModeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off all but the mode field. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + UDMA_MODE_M); + + // Check if scatter/gather mode, and if so, mask off the alt bit. + if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || + ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Control &= ~UDMA_MODE_ALT_SELECT; + } + + // Return the mode to the caller. + return(ui32Control); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/udma.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/udma.h new file mode 100644 index 0000000..443da6e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/udma.h @@ -0,0 +1,1240 @@ +/****************************************************************************** +* Filename: udma.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and prototypes for the uDMA controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup udma_api +//! @{ +// +//***************************************************************************** + +#ifndef __UDMA_H__ +#define __UDMA_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_udma.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable + #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable + #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet + #define uDMAChannelControlSet NOROM_uDMAChannelControlSet + #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet + #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet + #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet + #define uDMAChannelModeGet NOROM_uDMAChannelModeGet +#endif + +//***************************************************************************** +// +//! \brief A structure that defines an entry in the channel control table. +//! +//! These fields are used by the uDMA controller and normally it is not necessary for +//! software to directly read or write fields in the table. +// +//***************************************************************************** +typedef struct +{ + volatile void *pvSrcEndAddr; //!< The ending source address of the data transfer. + volatile void *pvDstEndAddr; //!< The ending destination address of the data transfer. + volatile uint32_t ui32Control; //!< The channel control mode. + volatile uint32_t ui32Spare; //!< An unused location. +} +tDMAControlTable; + +//***************************************************************************** +// +//! \brief A helper macro for building scatter-gather task table entries. +//! +//! This macro is intended to be used to help populate a table of uDMA tasks +//! for a scatter-gather transfer. This macro will calculate the values for +//! the fields of a task structure entry based on the input parameters. +//! +//! There are specific requirements for the values of each parameter. No +//! checking is done so it is up to the caller to ensure that correct values +//! are used for the parameters. +//! +//! This macro is intended to be used to initialize individual entries of +//! a structure of tDMAControlTable type, like this: +//! +/*! +\verbatim + tDMAControlTable MyTaskList[] = + { + uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, + UDMA_SRC_INC_8, MySourceBuf, + UDMA_DST_INC_8, MyDestBuf, + UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), + uDMATaskStructEntry(Task2Count, ... ), + } +\endverbatim +*/ +//! \param ui32TransferCount is the count of items to transfer for this task. +//! It must be in the range 1-1024. +//! \param ui32ItemSize is the bit size of the items to transfer for this task. +//! It must be one of: +//! - \ref UDMA_SIZE_8 +//! - \ref UDMA_SIZE_16 +//! - \ref UDMA_SIZE_32 +//! \param ui32SrcIncrement is the bit size increment for source data. +//! It must be one of: +//! - \ref UDMA_SRC_INC_8 +//! - \ref UDMA_SRC_INC_16 +//! - \ref UDMA_SRC_INC_32 +//! - \ref UDMA_SRC_INC_NONE +//! \param pvSrcAddr is the starting address of the data to transfer. +//! \param ui32DstIncrement is the bit size increment for destination data. +//! It must be one of: +//! - \ref UDMA_DST_INC_8 +//! - \ref UDMA_DST_INC_16 +//! - \ref UDMA_DST_INC_32 +//! - \ref UDMA_DST_INC_NONE +//! \param pvDstAddr is the starting address of the destination data. +//! \param ui32ArbSize is the arbitration size to use for the transfer task. +//! This is used to select the arbitration size in powers of 2, from 1 to 1024. +//! It must be one of: +//! - \ref UDMA_ARB_1 +//! - \ref UDMA_ARB_2 +//! - \ref UDMA_ARB_4 +//! - ... +//! - \ref UDMA_ARB_1024 +//! \param ui32Mode is the transfer mode for this task. +//! Note that normally all tasks will be one of the scatter-gather modes while the +//! last task is a task list will be AUTO or BASIC. +//! It must be one of: +//! - \ref UDMA_MODE_BASIC +//! - \ref UDMA_MODE_AUTO +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER +//! - \ref UDMA_MODE_PER_SCATTER_GATHER +//! +//! \return None (this is not a function) +// +//***************************************************************************** +#define uDMATaskStructEntry(ui32TransferCount, \ + ui32ItemSize, \ + ui32SrcIncrement, \ + pvSrcAddr, \ + ui32DstIncrement, \ + pvDstAddr, \ + ui32ArbSize, \ + ui32Mode) \ + { \ + (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : \ + ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \ + ((ui32SrcIncrement) >> 26)) - 1]))), \ + (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : \ + ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \ + ((ui32DstIncrement) >> 30)) - 1]))), \ + (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ + (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \ + ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ + ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ + (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \ + } + +//***************************************************************************** +// +// The hardware configured number of uDMA channels. +// +//***************************************************************************** +#define UDMA_NUM_CHANNELS 21 + +//***************************************************************************** +// +// The level of priority for the uDMA channels +// +//***************************************************************************** +#define UDMA_PRIORITY_LOW 0x00000000 +#define UDMA_PRIORITY_HIGH 0x00000001 + +//***************************************************************************** +// +// Flags that can be passed to uDMAChannelAttributeEnable(), +// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). +// +//***************************************************************************** +#define UDMA_ATTR_USEBURST 0x00000001 +#define UDMA_ATTR_ALTSELECT 0x00000002 +#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 +#define UDMA_ATTR_REQMASK 0x00000008 +#define UDMA_ATTR_ALL 0x0000000F + +//***************************************************************************** +// +// DMA control modes that can be passed to uDMAChannelModeSet() and returned +// uDMAChannelModeGet(). +// +//***************************************************************************** +#define UDMA_MODE_STOP 0x00000000 +#define UDMA_MODE_BASIC 0x00000001 +#define UDMA_MODE_AUTO 0x00000002 +#define UDMA_MODE_PINGPONG 0x00000003 +#define UDMA_MODE_MEM_SCATTER_GATHER \ + 0x00000004 +#define UDMA_MODE_PER_SCATTER_GATHER \ + 0x00000006 +#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_MODE_ALT_SELECT 0x00000001 + +//***************************************************************************** +// +// Channel configuration values that can be passed to uDMAControlSet(). +// +//***************************************************************************** +#define UDMA_DST_INC_8 0x00000000 +#define UDMA_DST_INC_16 0x40000000 +#define UDMA_DST_INC_32 0x80000000 +#define UDMA_DST_INC_NONE 0xC0000000 +#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment +#define UDMA_DST_INC_S 30 +#define UDMA_SRC_INC_8 0x00000000 +#define UDMA_SRC_INC_16 0x04000000 +#define UDMA_SRC_INC_32 0x08000000 +#define UDMA_SRC_INC_NONE 0x0c000000 +#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment +#define UDMA_SRC_INC_S 26 +#define UDMA_SIZE_8 0x00000000 +#define UDMA_SIZE_16 0x11000000 +#define UDMA_SIZE_32 0x22000000 +#define UDMA_SIZE_M 0x33000000 // Data Size +#define UDMA_SIZE_S 24 +#define UDMA_ARB_1 0x00000000 +#define UDMA_ARB_2 0x00004000 +#define UDMA_ARB_4 0x00008000 +#define UDMA_ARB_8 0x0000c000 +#define UDMA_ARB_16 0x00010000 +#define UDMA_ARB_32 0x00014000 +#define UDMA_ARB_64 0x00018000 +#define UDMA_ARB_128 0x0001c000 +#define UDMA_ARB_256 0x00020000 +#define UDMA_ARB_512 0x00024000 +#define UDMA_ARB_1024 0x00028000 +#define UDMA_ARB_M 0x0003C000 // Arbitration Size +#define UDMA_ARB_S 14 +#define UDMA_NEXT_USEBURST 0x00000008 +#define UDMA_XFER_SIZE_MAX 1024 +#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size +#define UDMA_XFER_SIZE_S 4 + +//***************************************************************************** +// +// Channel numbers to be passed to API functions that require a channel number +// ID. +// +//***************************************************************************** +#define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0 +#define UDMA_CHAN_UART0_RX 1 // UART0 RX Data +#define UDMA_CHAN_UART0_TX 2 // UART0 RX Data +#define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data +#define UDMA_CHAN_SSI0_TX 4 // SSI0 RX Data +#define UDMA_CHAN_AUX_ADC 7 // AUX ADC event +#define UDMA_CHAN_AUX_SW 8 // AUX Software event +#define UDMA_CHAN_TIMER0_A 9 // Timer0 A event +#define UDMA_CHAN_TIMER0_B 10 // Timer0 B event +#define UDMA_CHAN_TIMER1_A 11 +#define UDMA_CHAN_TIMER1_B 12 +#define UDMA_CHAN_AON_PROG2 13 +#define UDMA_CHAN_DMA_PROG 14 +#define UDMA_CHAN_AON_RTC 15 +#define UDMA_CHAN_SSI1_RX 16 +#define UDMA_CHAN_SSI1_TX 17 +#define UDMA_CHAN_SW_EVT1 18 +#define UDMA_CHAN_SW_EVT2 19 +#define UDMA_CHAN_SW_EVT3 20 + +//***************************************************************************** +// +// Flags to be OR'd with the channel ID to indicate if the primary or alternate +// control structure should be used. +// +//***************************************************************************** +#define UDMA_PRI_SELECT 0x00000000 +#define UDMA_ALT_SELECT 0x00000020 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks a uDMA base address. +//! +//! This function determines if a uDMA module base address is valid. +//! +//! \param ui32Base specifies the uDMA module base address. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +uDMABaseValid(uint32_t ui32Base) +{ + return(ui32Base == UDMA0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Enables the uDMA controller for use. +//! +//! This function enables the uDMA controller. The uDMA controller must be +//! enabled before it can be configured and used. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Set the master enable bit in the config register. + HWREG(ui32Base + UDMA_O_CFG) = UDMA_CFG_MASTERENABLE; +} + +//***************************************************************************** +// +//! \brief Disables the uDMA controller for use. +//! +//! This function disables the uDMA controller. Once disabled, the uDMA +//! controller will not operate until re-enabled with \ref uDMAEnable(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +uDMADisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Clear the master enable bit in the config register. + HWREG(ui32Base + UDMA_O_CFG) = 0; +} + +//***************************************************************************** +// +//! \brief Gets the uDMA error status. +//! +//! This function returns the uDMA error status. It should be called from +//! within the uDMA error interrupt handler to determine if a uDMA error +//! occurred. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Returns non-zero if a uDMA error is pending. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +uDMAErrorStatusGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Return the uDMA error status. + return(HWREG(ui32Base + UDMA_O_ERROR)); +} + +//***************************************************************************** +// +//! \brief Clears the uDMA error interrupt. +//! +//! This function clears a pending uDMA error interrupt. It should be called +//! from within the uDMA error interrupt handler to clear the interrupt. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAErrorStatusClear(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Clear the uDMA error interrupt. + HWREG(ui32Base + UDMA_O_ERROR) = UDMA_ERROR_STATUS; +} + +//***************************************************************************** +// +//! \brief Enables a uDMA channel for operation. +//! +//! This function enables a specific uDMA channel for use. This function must +//! be used to enable a channel before it can be used to perform a uDMA +//! transfer. +//! +//! When a uDMA transfer is completed, the channel will be automatically +//! disabled by the uDMA controller. Therefore, this function should be called +//! prior to starting up any new transfer. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number to enable. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelEnable(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the bit for this channel in the enable set register. + HWREG(ui32Base + UDMA_O_SETCHANNELEN) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Disables a uDMA channel for operation. +//! +//! This function disables a specific uDMA channel. Once disabled, a channel +//! will not respond to uDMA transfer requests until re-enabled via +//! \ref uDMAChannelEnable(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number to disable. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelDisable(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the bit for this channel in the enable clear register. + HWREG(ui32Base + UDMA_O_CLEARCHANNELEN) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Checks if a uDMA channel is enabled for operation. +//! +//! This function checks to see if a specific uDMA channel is enabled. This +//! can be used to check the status of a transfer, since the channel will +//! be automatically disabled at the end of a transfer. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number to check. +//! +//! \return Returns status of uDMA channel. +//! - \c true : Channel is enabled. +//! - \c false : Disabled. +// +//***************************************************************************** +__STATIC_INLINE bool +uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // AND the specified channel bit with the enable register, and return the + // result. + return((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ? + true : false); +} + +//***************************************************************************** +// +//! \brief Sets the base address for the channel control table. +//! +//! This function sets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. The table must be aligned on a 1024 byte boundary. The base +//! address must be set before any of the channel functions can be used. +//! Setting the base address of the primary control table will automatically +//! set the address for the alternate control table as the next memory +//! location after the primary control table. +//! +//! The size of the channel control table depends on the number of uDMA +//! channels, and which transfer modes are used. Refer to the introductory +//! text and the microcontroller datasheet for more information about the +//! channel control table. +//! +//! \note This register cannot be read when the controller is in the reset +//! state. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param pControlTable is a pointer to the 1024 byte aligned base address +//! of the uDMA channel control table. The address must be an absolute address +//! in system memory space. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAControlBaseSet(uint32_t ui32Base, void *pControlTable) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(((uint32_t)pControlTable & ~0x3FF) == + (uint32_t)pControlTable); + ASSERT((uint32_t)pControlTable >= SRAM_BASE); + + // Program the base address into the register. + HWREG(ui32Base + UDMA_O_CTRL) = (uint32_t)pControlTable; +} + +//***************************************************************************** +// +//! \brief Gets the base address for the channel control table. +//! +//! This function gets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Returns a pointer to the base address of the channel control table. +// +//***************************************************************************** +__STATIC_INLINE void * +uDMAControlBaseGet(uint32_t ui32Base) +{ + // Check the arguments. + + ASSERT(uDMABaseValid(ui32Base)); + // Read the current value of the control base register, and return it to + // the caller. + return((void *)HWREG(ui32Base + UDMA_O_CTRL)); +} + +//***************************************************************************** +// +//! \brief Gets the base address for the channel control table alternate structures. +//! +//! This function gets the base address of the second half of the channel +//! control table that holds the alternate control structures for each channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Returns a pointer to the base address of the second half of the +//! channel control table. +// +//***************************************************************************** +__STATIC_INLINE void * +uDMAControlAlternateBaseGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Read the current value of the control base register, and return it to + // the caller. + return((void *)HWREG(ui32Base + UDMA_O_ALTCTRL)); +} + +//***************************************************************************** +// +//! \brief Requests a uDMA channel to start a transfer. +//! +//! This function allows software to request a uDMA channel to begin a +//! transfer. This could be used for performing a memory to memory transfer, +//! or if for some reason a transfer needs to be initiated by software instead +//! of the peripheral associated with that channel. +//! +//! \note If the channel is a software channel and interrupts are used, then +//! the completion will be signaled on the uDMA dedicated interrupt. If a +//! peripheral channel is used, then the completion will be signaled on the +//! peripheral's interrupt. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number on which to request a uDMA +//! transfer. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelRequest(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the bit for this channel in the software uDMA request register. + HWREG(ui32Base + UDMA_O_SOFTREQ) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Enables attributes of a uDMA channel. +//! +//! This function is used to enable attributes of a uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel to configure. +//! \param ui32Attr is a combination of attributes for the channel. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelAttributeEnable(uint32_t ui32Base, + uint32_t ui32ChannelNum, + uint32_t ui32Attr); + +//***************************************************************************** +// +//! \brief Disables attributes of an uDMA channel. +//! +//! This function is used to disable attributes of a uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel to configure. +//! \param ui32Attr is a combination of attributes for the channel. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelAttributeDisable(uint32_t ui32Base, + uint32_t ui32ChannelNum, + uint32_t ui32Attr); + +//***************************************************************************** +// +//! \brief Gets the enabled attributes of a uDMA channel. +//! +//! This function returns a combination of flags representing the attributes of +//! the uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel to configure. +//! +//! \return Returns the bitwise OR of the attributes of the uDMA channel, which +//! can be any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +// +//***************************************************************************** +extern uint32_t uDMAChannelAttributeGet(uint32_t ui32Base, + uint32_t ui32ChannelNum); + +//***************************************************************************** +// +//! \brief Sets the control parameters for a uDMA channel control structure. +//! +//! This function is used to set control parameters for a uDMA transfer. These +//! are typically parameters that are not changed often. +//! +//! \note The address increment cannot be smaller than the data size. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT : Use primary data structure. +//! - \ref UDMA_ALT_SELECT : Use alternate data structure. +//! \param ui32Control is the bitwise OR of five values: +//! - Data size +//! - \ref UDMA_SIZE_8 : 8 bits. +//! - \ref UDMA_SIZE_16 : 16 bits. +//! - \ref UDMA_SIZE_32 : 32 bits. +//! - Source address increment +//! - \ref UDMA_SRC_INC_8 : 8 bits. +//! - \ref UDMA_SRC_INC_16 : 16 bits. +//! - \ref UDMA_SRC_INC_32 : 32 bits. +//! - \ref UDMA_SRC_INC_NONE : Non-incrementing. +//! - Destination address increment +//! - \ref UDMA_DST_INC_8 : 8 bits. +//! - \ref UDMA_DST_INC_16 : 16 bits. +//! - \ref UDMA_DST_INC_32 : 32 bits. +//! - \ref UDMA_DST_INC_NONE : Non-incrementing. +//! - Arbitration size. Determines how many items are transferred before +//! the uDMA controller re-arbitrates for the bus. In power of 2. +//! - \ref UDMA_ARB_1 +//! - \ref UDMA_ARB_2 +//! - \ref UDMA_ARB_4 +//! - \ref UDMA_ARB_8 +//! - ... +//! - \ref UDMA_ARB_1024 +//! - Force the channel to only respond to burst requests at the tail end of a scatter-gather transfer. +//! - \ref UDMA_NEXT_USEBURST +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelControlSet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex, + uint32_t ui32Control); + +//***************************************************************************** +// +//! \brief Sets the transfer parameters for a uDMA channel control structure. +//! +//! This function is used to set the parameters for a uDMA transfer. These are +//! typically parameters that are changed often. The function +//! \ref uDMAChannelControlSet() MUST be called at least once for this channel prior +//! to calling this function. +//! +//! The \c pvSrcAddr and \c pvDstAddr parameters are pointers to the first +//! location of the data to be transferred. These addresses should be aligned +//! according to the item size. The compiler will take care of this if the +//! pointers are pointing to storage of the appropriate data type. +//! +//! The two scatter/gather modes, MEMORY and PERIPHERAL, are actually different +//! depending on whether the primary or alternate control structure is +//! selected. This function will look for the \ref UDMA_PRI_SELECT and +//! \ref UDMA_ALT_SELECT flag along with the channel number and will set the +//! scatter/gather mode as appropriate for the primary or alternate control +//! structure. +//! +//! The channel must also be enabled using \ref uDMAChannelEnable() after calling +//! this function. The transfer will not begin until the channel has been set +//! up and enabled. Note that the channel is automatically disabled after the +//! transfer is completed, meaning that \ref uDMAChannelEnable() must be called +//! again after setting up the next transfer. +//! +//! \note Great care must be taken to not modify a channel control structure +//! that is in use or else the results will be unpredictable, including the +//! possibility of undesired data transfers to or from memory or peripherals. +//! For BASIC and AUTO modes, it is safe to make changes when the channel is +//! disabled, or the \ref uDMAChannelModeGet() returns \ref UDMA_MODE_STOP. For +//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the +//! primary or alternate control structure only when the other is being used. +//! The \ref uDMAChannelModeGet() function will return \ref UDMA_MODE_STOP when a +//! channel control structure is inactive and safe to modify. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT : Use primary data structure. +//! - \ref UDMA_ALT_SELECT : Use alternate data structure. +//! \param ui32Mode is the type of uDMA transfer. +//! The parameter should be one of the following values: +//! - \ref UDMA_MODE_STOP : Stops the uDMA transfer. The controller sets the mode +//! to this value at the end of a transfer. +//! - \ref UDMA_MODE_BASIC : Perform a basic transfer based on request. +//! - \ref UDMA_MODE_AUTO to perform a transfer that will always complete once +//! started even if request is removed. +//! - \ref UDMA_MODE_PINGPONG : Set up a transfer that switches between the +//! primary and alternate control structures for the channel. This allows +//! use of ping-pong buffering for uDMA transfers. +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER : Set up a memory scatter-gather transfer. +//! - \ref UDMA_MODE_PER_SCATTER_GATHER : Set up a peripheral scatter-gather transfer. +//! \param pvSrcAddr is the source address for the transfer. +//! \param pvDstAddr is the destination address for the transfer. +//! \param ui32TransferSize is the number of data items to transfer (\b NOT bytes). +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelTransferSet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex, + uint32_t ui32Mode, void *pvSrcAddr, + void *pvDstAddr, uint32_t ui32TransferSize); + +//***************************************************************************** +// +//! \brief Configures a uDMA channel for scatter-gather mode. +//! +//! This function is used to configure a channel for scatter-gather mode. +//! The caller must have already set up a task list, and pass a pointer to +//! the start of the task list as the \c pvTaskList parameter. +//! +//! The \c ui32TaskCount parameter is the count of tasks in the task list, not the +//! size of the task list. +//! +//! The flag \c bIsPeriphSG should be used to indicate +//! if the scatter-gather should be configured for a peripheral or memory +//! scatter-gather operation. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the uDMA channel number. +//! \param ui32TaskCount is the number of scatter-gather tasks to execute. +//! \param pvTaskList is a pointer to the beginning of the scatter-gather +//! task list. +//! \param ui32IsPeriphSG is a flag to indicate it is a peripheral +//! scatter-gather transfer (else it will be memory scatter-gather transfer) +//! +//! \return None +//! +//! \sa \ref uDMATaskStructEntry() +// +//***************************************************************************** +extern void uDMAChannelScatterGatherSet(uint32_t ui32Base, + uint32_t ui32ChannelNum, + uint32_t ui32TaskCount, + void *pvTaskList, + uint32_t ui32IsPeriphSG); + +//***************************************************************************** +// +//! \brief Gets the current transfer size for a uDMA channel control structure. +//! +//! This function is used to get the uDMA transfer size for a channel. The +//! transfer size is the number of items to transfer, where the size of an item +//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, +//! then the number of remaining items will be returned. If the transfer is +//! complete, then 0 will be returned. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT +//! - \ref UDMA_ALT_SELECT +//! +//! \return Returns the number of items remaining to transfer. +// +//***************************************************************************** +extern uint32_t uDMAChannelSizeGet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex); + +//***************************************************************************** +// +//! \brief Gets the transfer mode for a uDMA channel control structure. +//! +//! This function is used to get the transfer mode for the uDMA channel. It +//! can be used to query the status of a transfer on a channel. When the +//! transfer is complete the mode will be \ref UDMA_MODE_STOP. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT +//! - \ref UDMA_ALT_SELECT +//! +//! \return Returns the transfer mode of the specified channel and control +//! structure, which will be one of the following values: +//! - \ref UDMA_MODE_STOP +//! - \ref UDMA_MODE_BASIC +//! - \ref UDMA_MODE_AUTO +//! - \ref UDMA_MODE_PINGPONG +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER +//! - \ref UDMA_MODE_PER_SCATTER_GATHER +// +//***************************************************************************** +extern uint32_t uDMAChannelModeGet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex); + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the uDMA controller in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! \note The interrupt handler for uDMA is for transfer completion when the +//! software channel is used, and for error interrupts. The interrupts for each +//! peripheral channel are handled through the individual peripheral interrupt +//! handlers. +//! +//! \param ui32Base is the base address of the uDMA module. +//! \param ui32IntChannel specifies which uDMA interrupt is to be registered. +//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts +//! from the uDMA software channel. +//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error +//! interrupts. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntRegister(uint32_t ui32Base, uint32_t ui32IntChannel, + void (*pfnHandler)(void)) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(pfnHandler); + ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR)); + + // Register the interrupt handler. + IntRegister(ui32IntChannel, pfnHandler); + + // Enable the memory management fault. + IntEnable(ui32IntChannel); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the uDMA controller in the dynamic interrupt table. +//! +//! This function will disable and clear the handler to be called for the +//! specified uDMA interrupt. +//! +//! \param ui32Base is the base address of the uDMA module. +//! \param ui32IntChannel specifies which uDMA interrupt to unregister. +//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts +//! from the uDMA software channel. +//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error +//! interrupts. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntUnregister(uint32_t ui32Base, uint32_t ui32IntChannel) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR)); + + // Disable the interrupt. + IntDisable(ui32IntChannel); + + // Unregister the interrupt handler. + IntUnregister(ui32IntChannel); +} + +//***************************************************************************** +// +//! \brief Clears uDMA interrupt done status. +//! +//! Clears bits in the uDMA interrupt status register according to which bits +//! are set in \c ui32ChanMask. There is one bit for each channel. If a a bit +//! is set in \c ui32ChanMask, then that corresponding channel's interrupt +//! status will be cleared (if it was set). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntClear(uint32_t ui32Base, uint32_t ui32ChanMask) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Clear the requested bits in the uDMA interrupt status register. + HWREG(ui32Base + UDMA_O_REQDONE) = ui32ChanMask; +} + +//***************************************************************************** +// +//! \brief Get the uDMA interrupt status. +//! +//! This function returns the interrupt status for the specified UDMA. This +//! function does not differentiate between software or hardware activated +//! interrupts. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE uint32_t +uDMAIntStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Return the uDMA interrupt status register. + return (HWREG(ui32Base + UDMA_O_REQDONE)); +} + +//***************************************************************************** +// +//! \brief Enable interrupt on software event driven uDMA transfers. +//! +//! \note The main purpose of this function is to prevent propagation of uDMA +//! status signals to a peripheral, if a peripheral and a software event is +//! sharing the uDMA channel. If it is desired to initiate a transfer by +//! writing to a register inside the uDMA (this means a software driven +//! channel), then the uDMA status signals propagation need to be blocked to +//! the hardware peripherals. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32IntChannel identifies which uDMA interrupt to enable software +//! interrupts for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntSwEventEnable(uint32_t ui32Base, uint32_t ui32IntChannel) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS); + + // Enable the channel. + HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 1; +} + +//***************************************************************************** +// +//! \brief Disable interrupt on software event driven uDMA transfers. +//! +//! This register disables the blocking of the uDMA status signals propagation +//! to the hardware peripheral connected to the uDMA on the \c ui32IntChannel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32IntChannel identifies which uDMA interrupt to disable software +//! interrupts for. +//! +//! \return None +//! +//! \sa \ref uDMAIntSwEventEnable() +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntSwEventDisable(uint32_t ui32Base, uint32_t ui32IntChannel) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS); + + // Disable the SW channel. + HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 0; +} + +//***************************************************************************** +// +//! \brief Return the status of the uDMA module. +//! +//! \note This status register cannot be read when the controller is in the reset state. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Current status of the uDMA module. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +uDMAGetStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Read and return the status register. + return HWREG(ui32Base + UDMA_O_STATUS); +} + +//***************************************************************************** +// +//! \brief Set the priority of a uDMA channel. +//! +//! \note Writing 0 to a bit has no effect on the priority. To reset a channel +//! priority to the default value use \ref uDMAChannelPriorityClear(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is uDMA channel to set the priority for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelPrioritySet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the channel priority to high. + HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Get the priority of a uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum The uDMA channel to get the priority for. +//! +//! \return Returns one of: +//! - \ref UDMA_PRIORITY_HIGH +//! - \ref UDMA_PRIORITY_LOW +// +//***************************************************************************** +__STATIC_INLINE bool +uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Return the channel priority. + return(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ? + UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW); +} + +//***************************************************************************** +// +//! \brief Clear the priority of a uDMA channel. +//! +//! \note Writing 0 to a bit has no effect on the priority. To set a channel +//! priority to high use \ref uDMAChannelPrioritySet(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum The uDMA channel to clear the priority for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Clear the channel priority. + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_uDMAChannelAttributeEnable + #undef uDMAChannelAttributeEnable + #define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable + #endif + #ifdef ROM_uDMAChannelAttributeDisable + #undef uDMAChannelAttributeDisable + #define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable + #endif + #ifdef ROM_uDMAChannelAttributeGet + #undef uDMAChannelAttributeGet + #define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet + #endif + #ifdef ROM_uDMAChannelControlSet + #undef uDMAChannelControlSet + #define uDMAChannelControlSet ROM_uDMAChannelControlSet + #endif + #ifdef ROM_uDMAChannelTransferSet + #undef uDMAChannelTransferSet + #define uDMAChannelTransferSet ROM_uDMAChannelTransferSet + #endif + #ifdef ROM_uDMAChannelScatterGatherSet + #undef uDMAChannelScatterGatherSet + #define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet + #endif + #ifdef ROM_uDMAChannelSizeGet + #undef uDMAChannelSizeGet + #define uDMAChannelSizeGet ROM_uDMAChannelSizeGet + #endif + #ifdef ROM_uDMAChannelModeGet + #undef uDMAChannelModeGet + #define uDMAChannelModeGet ROM_uDMAChannelModeGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UDMA_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/vims.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/vims.c new file mode 100644 index 0000000..8acad07 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/vims.c @@ -0,0 +1,189 @@ +/****************************************************************************** +* Filename: vims.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the VIMS. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "vims.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef VIMSConfigure + #define VIMSConfigure NOROM_VIMSConfigure + #undef VIMSModeSet + #define VIMSModeSet NOROM_VIMSModeSet + #undef VIMSModeGet + #define VIMSModeGet NOROM_VIMSModeGet + #undef VIMSModeSafeSet + #define VIMSModeSafeSet NOROM_VIMSModeSafeSet +#endif + +//***************************************************************************** +// +// Configures the VIMS. +// +//***************************************************************************** +void +VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG); + if(bRoundRobin) + { + ui32Reg |= VIMS_CTL_ARB_CFG; + } + if(bPrefetch) + { + ui32Reg |= VIMS_CTL_PREF_EN; + } + + // Set the Arbitration and prefetch mode. + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +//***************************************************************************** +// +// Set the operational mode of the VIMS +// +//***************************************************************************** +void +VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ASSERT((ui32Mode == VIMS_MODE_DISABLED) || + (ui32Mode == VIMS_MODE_ENABLED) || + (ui32Mode == VIMS_MODE_OFF)); + + // Set the mode. + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~VIMS_CTL_MODE_M; + ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M); + + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +//***************************************************************************** +// +// Get the current operational mode of the VIMS. +// +//***************************************************************************** +uint32_t +VIMSModeGet(uint32_t ui32Base) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_STAT); + if(ui32Reg & VIMS_STAT_MODE_CHANGING) + { + return (VIMS_MODE_CHANGING); + } + else + { + return (ui32Reg & VIMS_STAT_MODE_M); + } +} + +//***************************************************************************** +// +// Safe setting of new VIMS mode +// - Function might be blocking +// - Can be called for any mode change (also if actually not changing mode) +// +//***************************************************************************** +void +VIMSModeSafeSet( uint32_t ui32Base, uint32_t ui32NewMode, bool blocking ) +{ + uint32_t currentMode; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + ASSERT((ui32NewMode == VIMS_MODE_DISABLED) || + (ui32NewMode == VIMS_MODE_ENABLED) || + (ui32NewMode == VIMS_MODE_OFF)); + + // Make sure that only the mode bits are set in the input parameter + // (done just for security since it is critical to the code flow) + ui32NewMode &= VIMS_CTL_MODE_M; + + // Wait for any pending change to complete and get current VIMS mode + // (This is a blocking point but will typically only be a blocking point + // only if mode is changed multiple times with blocking=0) + do { + currentMode = VIMSModeGet( ui32Base ); + } while ( currentMode == VIMS_MODE_CHANGING ); + + // First check that it actually is a mode change request + if ( ui32NewMode != currentMode ) { + // Due to a hw-problem it is strongly recommended to go via VIMS_MODE_OFF + // when leaving VIMS_MODE_ENABLED (=VIMS_CTL_MODE_CACHE) + // (And no need to go via OFF, if OFF is the final state and will be set later) + if (( currentMode == VIMS_CTL_MODE_CACHE ) && + ( ui32NewMode != VIMS_CTL_MODE_OFF ) ) + { + VIMSModeSet( ui32Base, VIMS_MODE_OFF ); + + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for change to complete. + // (Needed blocking point but it takes only some few cycles) + } + } + // Set new mode + VIMSModeSet( ui32Base, ui32NewMode ); + + // Wait for final mode change to complete - if blocking is requested + if ( blocking ) { + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for change to complete. + } + } + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/vims.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/vims.h new file mode 100644 index 0000000..9e6ecaf --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/vims.h @@ -0,0 +1,371 @@ +/****************************************************************************** +* Filename: vims.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the VIMS. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup vims_api +//! @{ +// +//***************************************************************************** + +#ifndef __VIMS_H__ +#define __VIMS_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_vims.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define VIMSConfigure NOROM_VIMSConfigure + #define VIMSModeSet NOROM_VIMSModeSet + #define VIMSModeGet NOROM_VIMSModeGet + #define VIMSModeSafeSet NOROM_VIMSModeSafeSet +#endif + +//***************************************************************************** +// +// Values that can be passed to VIMSModeSet() as the ui32IntFlags parameter, +// and returned from VIMSModeGet(). +// +//***************************************************************************** +#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE + // can not be changed at moment. +#define VIMS_MODE_DISABLED (VIMS_CTL_MODE_GPRAM) // Disabled mode (GPRAM enabled). +#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached. +#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \brief Checks a VIMS base address. +//! +//! This function determines if the VIMS base address is valid. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +VIMSBaseValid(uint32_t ui32Base) +{ + return(ui32Base == VIMS_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Configures the VIMS. +//! +//! This function sets general control settings of the VIMS system. +//! +//! \note The VIMS mode must be set using the \ref VIMSModeSet() call. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param bRoundRobin specifies the arbitration method. +//! - \c true : Round Robin arbitration between the two available read/write interfaces +//! (i.e. Icode/Dcode and Sysbus) is to be used. +//! - \c false : Strict arbitration will be used, where Icode/Dcode +//! is preferred over the Sysbus. +//! \param bPrefetch specifies if prefetching is to be used. +//! - \c true : Cache is to prefetch tag data for the following address. +//! - \c false : No prefetch. +//! +//! \return None +//! +//! \sa \ref VIMSModeSet() +// +//***************************************************************************** +extern void VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, + bool bPrefetch); + +//***************************************************************************** +// +//! \brief Set the operational mode of the VIMS. +//! +//! This function sets the operational mode of the VIMS. +//! +//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. +//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will not be operational. +//! Reads and writes to flash will be uncached. +//! After a short delay (approx. 1029 clock cycles) the VIMS will +//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). +//! +//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is +//! accessible: +//! The GP RAM will be accessible. +//! The Cache will not be operational. +//! Reads from flash will be uncached. +//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). +//! +//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will be operational for SYSCODE space. +//! Reads from flash in USERCODE space will be uncached. +//! +//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. +//! +//! \note The VIMS must be invalidated when switching mode. +//! This is done by setting VIMS_MODE_OFF before setting any new mode. +//! This is automatically handled in \ref VIMSModeSafeSet() +//! +//! \note It is highly recommended that the VIMS is put in disabled mode before +//! \b writing to flash, since the cache will not be updated nor invalidated +//! by flash writes. The line buffers should also be disabled when updating the +//! flash. Once \ref VIMSModeSet() is used to set the VIMS in +//! \ref VIMS_MODE_CHANGING mode, the user should check using +//! \ref VIMSModeGet() when the mode switches to \ref VIMS_MODE_DISABLED. Only when +//! the mode has changed the cache has been completely invalidated. +//! +//! \note Access from System Bus is never cached. Only access through ICODE +//! DCODE bus from the System CPU is cached. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param ui32Mode is the operational mode. +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! +//! \return None +//! +//! \sa \ref VIMSModeGet() and \ref VIMSModeSafeSet() +// +//***************************************************************************** +extern void VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode); + +//***************************************************************************** +// +//! \brief Get the current operational mode of the VIMS. +//! +//! This function returns the operational mode of the VIMS. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return Returns one of: +//! - \ref VIMS_MODE_CHANGING +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! +//! \sa \ref VIMSModeSet() +// +//***************************************************************************** +extern uint32_t VIMSModeGet(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Set the operational mode of the VIMS in a safe sequence. +//! +//! This function sets the operational mode of the VIMS in a safe sequence +//! +//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. +//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will not be operational (read/write to flash will be uncached). +//! After a short delay (approx. 1029 clock cycles) the VIMS will +//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). +//! +//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is +//! accessible: +//! The GP RAM will be accessible. +//! The Cache will not be operational. +//! Reads from flash will be uncached. +//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). +//! +//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will be operational for SYSCODE space. +//! Reads from flash in USERCODE space will be uncached. +//! +//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. +//! +//! \note The VIMS must be invalidated when switching mode. +//! This is done by setting VIMS_MODE_OFF before setting any new mode. +//! This is automatically handled in this function. +//! +//! \note It is highly recommended that the VIMS is put in disabled mode before +//! \b writing to flash, since the cache will not be updated nor invalidated +//! by flash writes. The line buffers should also be disabled when updating the +//! flash. +//! +//! \note Access from System Bus is never cached. Only access through ICODE +//! DCODE bus from the System CPU is cached. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param ui32NewMode is the new operational mode: +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! \param blocking shall be set to TRUE if further code execution shall be +//! blocked (delayed) until mode change is completed. +//! +//! \return None +//! +//! \sa \ref VIMSModeSet() and \ref VIMSModeGet() +// +//***************************************************************************** +extern void VIMSModeSafeSet( uint32_t ui32Base , + uint32_t ui32NewMode , + bool blocking ); + +//***************************************************************************** +// +//! \brief Disable VIMS linebuffers. +//! +//! Linebuffers should only be disabled when attempting to update the flash, to +//! ensure that the content of the buffers is not stale. As soon as flash is +//! updated the linebuffers should be reenabled. Failing to enable +//! will have a performance impact. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +VIMSLineBufDisable(uint32_t ui32Base) +{ + // Disable line buffers + HWREG(ui32Base + VIMS_O_CTL) |= VIMS_CTL_IDCODE_LB_DIS_M | + VIMS_CTL_SYSBUS_LB_DIS_M; +} + +//***************************************************************************** +// +//! \brief Enable VIMS linebuffers. +//! +//! Linebuffers should only be disabled when attempting to update the flash, to +//! ensure that the content of the buffers is not stale. As soon as flash is +//! updated the linebuffers should be reenabled. Failing to enable +//! will have a performance impact. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +VIMSLineBufEnable(uint32_t ui32Base) +{ + // Enable linebuffers + HWREG(ui32Base + VIMS_O_CTL) &= ~(VIMS_CTL_IDCODE_LB_DIS_M | + VIMS_CTL_SYSBUS_LB_DIS_M); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_VIMSConfigure + #undef VIMSConfigure + #define VIMSConfigure ROM_VIMSConfigure + #endif + #ifdef ROM_VIMSModeSet + #undef VIMSModeSet + #define VIMSModeSet ROM_VIMSModeSet + #endif + #ifdef ROM_VIMSModeGet + #undef VIMSModeGet + #define VIMSModeGet ROM_VIMSModeGet + #endif + #ifdef ROM_VIMSModeSafeSet + #undef VIMSModeSafeSet + #define VIMSModeSafeSet ROM_VIMSModeSafeSet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __VIMS_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog.c new file mode 100644 index 0000000..054febd --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: wdt.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the Watchdog Timer. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "watchdog.h" + +// See watchdog.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog.h new file mode 100644 index 0000000..373fb52 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog.h @@ -0,0 +1,520 @@ +/****************************************************************************** +* Filename: wdt.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and prototypes for the Watchdog Timer. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup wdt_api +//! @{ +// +//***************************************************************************** + +#ifndef __WDT_H__ +#define __WDT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_wdt.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//***************************************************************************** +#define WATCHDOG_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WATCHDOG_LOCK_LOCKED 0x00000001 // Locked +#define WATCHDOG_LOCK_UNLOCK 0x1ACCE551 // Unlocks the Watchdog Timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and +// WDT_MIS registers. +// +//***************************************************************************** +#define WATCHDOG_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The type of interrupt that can be generated by the watchdog. +// +//***************************************************************************** +#define WATCHDOG_INT_TYPE_INT 0x00000000 +#define WATCHDOG_INT_TYPE_NMI 0x00000004 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Determines if the watchdog timer is enabled. +//! +//! This function checks to see if the watchdog timer is enabled. +//! +//! \return Returns status of Watchdog Timer: +//! - \c true : Watchdog timer is enabled. +//! - \c false : Watchdog timer is disabled. +// +//***************************************************************************** +__STATIC_INLINE bool +WatchdogRunning(void) +{ + // See if the watchdog timer module is enabled, and return. + return((HWREG(WDT_BASE + WDT_O_CTL) & WDT_CTL_INTEN) ? true : false); +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer. +//! +//! This function enables the watchdog timer counter and interrupt. +//! +//! Once enabled, the watchdog interrupt can only be disabled by a hardware reset. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogEnable(void) +{ + // Enable the watchdog timer module. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTEN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer reset. +//! +//! This function enables the capability of the watchdog timer to issue a reset +//! to the processor after a second timeout condition. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogResetEnable(void) +{ + // Enable the watchdog reset. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disables the watchdog timer reset. +//! +//! This function disables the capability of the watchdog timer to issue a +//! reset to the processor after a second timeout condition. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogResetDisable(void) +{ + // Disable the watchdog reset. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer lock mechanism. +//! +//! This function locks out write access to the watchdog timer configuration +//! registers. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogLock(void) +{ + // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK + // register causes the lock to go into effect. + HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_LOCKED; +} + +//***************************************************************************** +// +//! \brief Disables the watchdog timer lock mechanism. +//! +//! This function enables write access to the watchdog timer configuration +//! registers. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogUnlock(void) +{ + // Unlock watchdog register writes. + HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_UNLOCK; +} + +//***************************************************************************** +// +//! \brief Gets the state of the watchdog timer lock mechanism. +//! +//! This function returns the lock state of the watchdog timer registers. +//! +//! \return Returns state of lock mechanism. +//! - \c true : Watchdog timer registers are locked. +//! - \c false : Registers are not locked. +// +//***************************************************************************** +__STATIC_INLINE bool +WatchdogLockState(void) +{ + // Get the lock state. + return((HWREG(WDT_BASE + WDT_O_LOCK) == WATCHDOG_LOCK_LOCKED) ? + true : false); +} + +//***************************************************************************** +// +//! \brief Sets the watchdog timer reload value. +//! +//! This function configures the value to load into the watchdog timer when the +//! count reaches zero for the first time; if the watchdog timer is running +//! when this function is called, then the value is immediately loaded into the +//! watchdog timer counter. If the \c ui32LoadVal parameter is 0, then an +//! interrupt is immediately generated. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \param ui32LoadVal is the load value for the watchdog timer. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock(), \ref WatchdogReloadGet() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogReloadSet(uint32_t ui32LoadVal) +{ + // Set the load register. + HWREG(WDT_BASE + WDT_O_LOAD) = ui32LoadVal; +} + +//***************************************************************************** +// +//! \brief Gets the watchdog timer reload value. +//! +//! This function gets the value that is loaded into the watchdog timer when +//! the count reaches zero for the first time. +//! +//! \return None +//! +//! \sa \ref WatchdogReloadSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +WatchdogReloadGet(void) +{ + // Get the load register. + return(HWREG(WDT_BASE + WDT_O_LOAD)); +} + +//***************************************************************************** +// +//! \brief Gets the current watchdog timer value. +//! +//! This function reads the current value of the watchdog timer. +//! +//! \return Returns the current value of the watchdog timer. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +WatchdogValueGet(void) +{ + // Get the current watchdog timer register value. + return(HWREG(WDT_BASE + WDT_O_VALUE)); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! The watchdog timer interrupt must be enabled via \ref WatchdogIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! \ref WatchdogIntClear(). +//! +//! \note This function registers the standard watchdog interrupt handler. To +//! register the NMI watchdog handler, use \ref IntRegister() to register the +//! handler for the \b INT_NMI_FAULT interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! watchdog timer interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_WDT_IRQ, pfnHandler); + + // Enable the watchdog timer interrupt. + IntEnable(INT_WDT_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. This +//! function clears the handler to be called when a watchdog timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \note This function registers the standard watchdog interrupt handler. To +//! register the NMI watchdog handler, use \ref IntRegister() to register the +//! handler for the \b INT_NMI_FAULT interrupt. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntUnregister(void) +{ + // Disable the interrupt. + IntDisable(INT_WDT_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_WDT_IRQ); +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer. +//! +//! This function enables the watchdog timer interrupt by calling \ref WatchdogEnable(). +//! +//! \return None +//! +//! \sa \ref WatchdogEnable() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntEnable(void) +{ + // Enable the Watchdog interrupt. + WatchdogEnable(); +} + +//***************************************************************************** +// +//! \brief Gets the current watchdog timer interrupt status. +//! +//! This function returns the interrupt status for the watchdog timer module. +//! +//! \return Returns the interrupt status. +//! - 1 : Watchdog time-out has occurred. +//! - 0 : Watchdog time-out has not occurred. +//! +//! \sa \ref WatchdogIntClear(); +// +//***************************************************************************** +__STATIC_INLINE uint32_t +WatchdogIntStatus(void) +{ + // Return either the interrupt status or the raw interrupt status as + // requested. + return(HWREG(WDT_BASE + WDT_O_RIS)); +} + +//***************************************************************************** +// +//! \brief Clears the watchdog timer interrupt. +//! +//! The watchdog timer interrupt source is cleared, so that it no longer +//! asserts. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntClear(void) +{ + // Clear the interrupt source. + HWREG(WDT_BASE + WDT_O_ICR) = WATCHDOG_INT_TIMEOUT; +} + +//***************************************************************************** +// +//! \brief Sets the type of interrupt generated by the watchdog. +//! +//! This function sets the type of interrupt that is generated if the watchdog +//! timer expires. +//! +//! When configured to generate an NMI, the watchdog interrupt must still be +//! enabled with \ref WatchdogIntEnable(), and it must still be cleared inside the +//! NMI handler with \ref WatchdogIntClear(). +//! +//! \param ui32Type is the type of interrupt to generate. +//! - \ref WATCHDOG_INT_TYPE_INT : Generate a standard interrupt (default). +//! - \ref WATCHDOG_INT_TYPE_NMI : Generate a non-maskable interrupt (NMI). +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntTypeSet(uint32_t ui32Type) +{ + // Check the arguments. + ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) || + (ui32Type == WATCHDOG_INT_TYPE_NMI)); + + // Set the interrupt type. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTTYPE_BITN) = (ui32Type == WATCHDOG_INT_TYPE_INT)? 0 : 1; +} + +//***************************************************************************** +// +//! \brief Enables stalling of the watchdog timer during debug events. +//! +//! This function allows the watchdog timer to stop counting when the processor +//! is stopped by the debugger. By doing so, the watchdog is prevented from +//! expiring and resetting the system (if reset is enabled). The watchdog instead expires +//! after the appropriate number of processor cycles have been executed while +//! debugging (or at the appropriate time after the processor has been +//! restarted). +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogStallEnable(void) +{ + // Enable timer stalling. + HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disables stalling of the watchdog timer during debug events. +//! +//! This function disables the debug mode stall of the watchdog timer. By +//! doing so, the watchdog timer continues to count regardless of the processor +//! debug state. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogStallDisable(void) +{ + // Disable timer stalling. + HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 0; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __WDT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog_doc.h new file mode 100644 index 0000000..877bab7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog_doc.h @@ -0,0 +1,121 @@ +/****************************************************************************** +* Filename: watchdog_doc.h +* Revised: 2018-02-09 15:45:36 +0100 (Fri, 09 Feb 2018) +* Revision: 51470 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup wdt_api +//! @{ +//! \section sec_wdt Introduction +//! +//! The Watchdog Timer (WDT) allows the application to regain control if the system stalls due to +//! unexpected software behavior. The WDT can generate a normal interrupt or a non-maskable interrupt +//! on the first time-out and a system reset on the following time-out if the application fails to +//! restart the WDT. +//! +//! WDT has the following features: +//! - 32-bit down counter with a configurable load register. +//! - Configurable interrupt generation logic with interrupt masking and optional NMI function. +//! - Optional reset generation. +//! - Register protection from runaway software (lock). +//! - User-enabled stalling when the system CPU asserts the CPU Halt flag during debug. +//! +//! The WDT runs at system HF clock divided by 32; however, when in powerdown it runs at +//! LF clock (32 kHz) - if the LF clock to the MCU domain is enabled. +//! +//! If application does not restart the WDT, using \ref WatchdogIntClear(), before a time-out: +//! - At the first time-out the WDT asserts the interrupt, reloads the 32-bit counter with the load +//! value, and resumes counting down from that value. +//! - If the WDT counts down to zero again before the application clears the interrupt, and the +//! reset signal has been enabled, the WDT asserts its reset signal to the system. +//! +//! \note By default, a "warm reset" triggers a pin reset and thus reboots the device. +//! +//! A reset caused by the WDT can be detected as a "warm reset" using \ref SysCtrlResetSourceGet(). +//! However, it is not possible to detect which of the warm reset sources that caused the reset. +//! +//! Typical use case: +//! - Use \ref WatchdogIntTypeSet() to select either standard interrupt or non-maskable interrupt on +//! first time-out. +//! - The application must implement an interrupt handler for the selected interrupt type. If +//! application uses the \e static vector table (see startup_.c) the interrupt +//! handlers for standard interrupt and non-maskable interrupt are named WatchdogIntHandler() +//! and NmiSR() respectively. For more information about \e static and \e dynamic vector table, +//! see \ref sec_interrupt_table. +//! - Use \ref WatchdogResetEnable() to enable reset on second time-out. +//! - Use \ref WatchdogReloadSet() to set (re)load value of the counter. +//! - Use \ref WatchdogEnable() to start the WDT counter. The WDT counts down from the load value. +//! - Use \ref WatchdogLock() to lock WDT configuration to prevent unintended re-configuration. +//! - Application must use \ref WatchdogIntClear() to restart the counter before WDT times out. +//! - If application does not restart the counter before it reaches zero (times out) the WDT asserts +//! the selected type of interrupt, reloads the counter, and starts counting down again. +//! - The interrupt handler triggered by the first time-out can be used to log debug information +//! or try to enter a safe "pre-reset" state in order to have a more graceful reset when the WDT +//! times out the second time. +//! - It is \b not recommended that the WDT interrupt handler clears the WDT interrupt and thus +//! reloads the WDT counter. This means that the WDT interrupt handler never returns. +//! - If the application does not clear the WDT interrupt and the WDT times out when the interrupt +//! is still asserted then WDT triggers a reset (if enabled). +//! +//! \section sec_wdt_api API +//! +//! The API functions can be grouped like this: +//! +//! Watchdog configuration: +//! - \ref WatchdogIntTypeSet() +//! - \ref WatchdogResetEnable() +//! - \ref WatchdogResetDisable() +//! - \ref WatchdogReloadSet() +//! - \ref WatchdogEnable() +//! +//! Status: +//! - \ref WatchdogRunning() +//! - \ref WatchdogValueGet() +//! - \ref WatchdogReloadGet() +//! - \ref WatchdogIntStatus() +//! +//! Interrupt configuration: +//! - \ref WatchdogIntEnable() +//! - \ref WatchdogIntClear() +//! - \ref WatchdogIntRegister() +//! - \ref WatchdogIntUnregister() +//! +//! Register protection: +//! - \ref WatchdogLock() +//! - \ref WatchdogLockState() +//! - \ref WatchdogUnlock() +//! +//! Stall configuration for debugging: +//! - \ref WatchdogStallDisable() +//! - \ref WatchdogStallEnable() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/asmdefs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/asmdefs.h new file mode 100644 index 0000000..1768b4c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/asmdefs.h @@ -0,0 +1,151 @@ +/****************************************************************************** +* Filename: asmdefs.h +* Revised: 2015-06-05 14:39:10 +0200 (Fri, 05 Jun 2015) +* Revision: 43803 +* +* Description: Macros to allow assembly code be portable among tool chains. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef __IAR_SYSTEMS_ICC__ + +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) +#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) + +// +// Assembler mnemonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data + +#endif // __IAR_SYSTEMS_ICC__ + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#if defined(__GNUC__) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler mnemonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // __GNUC__ + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#if defined(__CC_ARM) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 +#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 + +// +// Assembler mnemonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ + +#endif // __CC_ARM + + +#endif // __ASMDEF_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi.h new file mode 100644 index 0000000..d55fe0f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi.h @@ -0,0 +1,1182 @@ +/****************************************************************************** +* Filename: hw_adi.h +* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) +* Revision: 42365 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_H__ +#define __HW_ADI_H__ + +//***************************************************************************** +// +// This file contains macros for controlling the ADI master and +// accessing ADI slave registers via the ADI Master. +// There are 3 categories of macros in this file: +// - macros that provide an offset to a register +// located within the DDI Master itself. +// - macros that define bits or bitfields +// within the DDI Master Registers. +// - macros that provide an "instruction offset" +// that are used when accessing a ADI Slave. +// +// The macros that that provide ADI Master register offsets and +// define bits and bitfields for those registers are the typical +// macros that appear in most hw_.h header files. In +// the following example ADI_O_SLAVECONF is a macro for a +// register offset and ADI_SLAVECONF_WAITFORACK is a macro for +// a bit in that register. This example code will set the WAITFORACK +// bit in register ADI_O_SLAVECONF of the ADI Master. (Note: this +// access the Master not the Slave). +// +// HWREG(ADI3_BASE + ADI_O_SLAVECONF) |= ADI_SLAVECONF_WAITFORACK; +// +// The "instruction offset" macros are used to pass an instruction to +// the ADI Master when accessing ADI slave registers. These macros are +// only used when accessing ADI Slave Registers. (Remember ADI +// Master Registers are accessed normally). +// +// The instructions supported when accessing an ADI Slave Register follow: +// - Direct Access to an ADI Slave register. I.e. read or +// write the register. +// - Set the specified bits in a ADI Slave register. +// - Clear the specified bits in a ADI Slave register. +// - Mask write of 4 bits to the a ADI Slave register. +// - Mask write of 8 bits to the a ADI Slave register. +// - Mask write of 16 bits to the a ADI Slave register. +// +// Note: only the "Direct Access" offset should be used when reading +// a ADI Slave register. Only 4-bit reads are supported and 8 bits write are +// supported natively. If accessing wider bitfields, the read/write operation +// will be spread out over a number of transactions. This is hidden for the +// user, but can potentially be very timeconsuming. Especially of running +// on a slow clock. +// +// The generic format of using these macros for a read follows: +// // Read low 8-bits in ADI_SLAVE_OFF +// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); +// +// // Read high 8-bits in ADI_SLAVE_OFF (data[31:16]) +// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); +// +// Notes: In the above example: +// - ADI_MASTER_BASE is the base address of the ADI Master defined +// in the hw_memmap.h header file. +// - ADI_SLAVE_OFF is the ADI Slave offset defined in the +// hw_.h header file (e.g. hw_adi_3_refsys_top.h for the refsys +// module). +// - ADI_O_DIR is the "instruction offset" macro defined in this +// file that specifies the Direct Access instruction. +// +// Writes can use any of the "instruction macros". +// The following examples do a "direct write" to an ADI Slave register +// ADI_SLAVE_OFF using different size operands: +// +// // ---------- DIRECT WRITES ---------- +// // Write 32-bits aligned +// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x12345678; +// +// // Write 16-bits aligned to high 16-bits then low 16-bits +// // Add 2 to get to high 16-bits. +// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0xabcd; +// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0xef01; +// +// // Write each byte at ADI_SLAVE_OFF, one at a time. +// // Add 1,2,or 3 to get to bytes 1,2, or 3. +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x33; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 1) = 0x44; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0x55; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 3) = 0x66; +// +// // ---------- SET/CLR ---------- +// The set and clear functions behave similarly to eachother. Each +// can be performed on an 8-, 16-, or 32-bit operand. +// Examples follow: +// // Set all odd bits in a 32-bit words +// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_SET) = 0xaaaaaaaa; +// +// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand +// HWREG(DDI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_CLR) = 0x00ff0000; +// +// // Set even bits in byte 2 (data[23:16]) using 8-bit operand +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + 2 + ADI_O_CLR) = 0x55; +// +// // ---------- MASKED WRITES ---------- +// The mask writes are a bit different. They operate on nibbles, +// bytes, and 16-bit elements. Two operands are required; a 'mask' +// and 'data'; The operands are concatenated and written to the master. +// e.g. the mask and data are combined as follows for a 16 bit masked +// write: +// (mask << 16) | data; +// Examples follow: +// +// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). +// // Byte write is needed. +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_MASK4B01) = 0xf7; +// +// // Do an 4 bit masked write of 4 to data[7:4]). +// // Add 1 for next nibble +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + ADI_O_MASK4B01 + 1) = 0xf4; +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the ADI master instruction offsets. +// +//***************************************************************************** +#define ADI_O_DIR 0x00000000 // Offset for the direct access + // instruction +#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. +#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. +#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). + // Bits 7:4 are mask. Bits 3:0 are data. + // Requires 'byte' write. +#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). Bits 15:8 are + // mask. Bits 7:0 are data. Requires + // 'short' write. +#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). Bits 31:16 + // are mask. Bits 15:0 are data. + // Requires 'long' write. + +//***************************************************************************** +// +// The following are defines for the ADI register offsets. +// +//***************************************************************************** +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVESTAT register. +// +//***************************************************************************** +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ + // signal. Writing 0 to this bit + // forces a sync with slave, + // ensuring that req will be 0. It + // is recommended to write 0 to + // this register before power down + // of the master. +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK + // signal +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVECONF register. +// +//***************************************************************************** +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer + // accessible when this bit is set. + // (unless sticky_bit_overwrite is + // asserted on top module) +#define ADI_SLAVECONF_CONFLOCK_M \ + 0x00000080 +#define ADI_SLAVECONF_CONFLOCK_S 7 +#define ADI_SLAVECONF_WAITFORACK \ + 0x00000004 // A transaction on the ADI + // interface does not end until ack + // has been received from the slave + // when this bit is set. + +#define ADI_SLAVECONF_WAITFORACK_M \ + 0x00000004 +#define ADI_SLAVECONF_WAITFORACK_S 2 +#define ADI_SLAVECONF_ADICLKSPEED_M \ + 0x00000003 // Sets the period of an ADI + // transactions. All transactions + // takes an even number of clock + // cycles,- ADI clock rising edge + // occurs in the middle of the + // period. Data and ctrl to slave + // is set up in beginning of cycle, + // and data from slave is read in + // after the transaction 00: An ADI + // transaction takes 2 master clock + // cyclkes 01: An ADI transaction + // takes 4 master clock cycles 10: + // And ADI Transaction takes 8 + // master clock cycles 11: An ADI + // transaction takes 16 master + // clock cycles + +#define ADI_SLAVECONF_ADICLKSPEED_S 0 + +//***************************************************************************** +// +// The following are defines pseudo-magic numbers that should go away. +// New code should not use these registers and old code should be ported +// to not use these. +// +//***************************************************************************** +#define ADI_O_DIR03 0x00000000 // Direct access for adi byte + // offsets 0 to 3 +#define ADI_O_DIR47 0x00000004 // Direct access for adi byte + // offsets 4 to 7 +#define ADI_O_DIR811 0x00000008 // Direct access for adi byte + // offsets 8 to 11 +#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte + // offsets 12 to 15 +#define ADI_O_SET03 0x00000010 // Set register for ADI byte + // offsets 0 to 3 +#define ADI_O_SET47 0x00000014 // Set register for ADI byte + // offsets 4 to 7 +#define ADI_O_SET811 0x00000018 // Set register for ADI byte + // offsets 8 to 11 +#define ADI_O_SET1215 0x0000001C // Set register for ADI byte + // offsets 12 to 15 +#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte + // offsets 0 to 3 +#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte + // offsets 4 to 7 +#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte + // offsets 8 to 11 +#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte + // offsets 12 to 15 +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration + // register +#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI + // Registers at byte offsets 14 and + // 15 +#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI + // Registers at byte offsets 14 and + // 15 +#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI + // Registers at byte offsets 14 and + // 15 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR03 register. +// +//***************************************************************************** +#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 +#define ADI_DIR03_B3_S 24 +#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 +#define ADI_DIR03_B2_S 16 +#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 +#define ADI_DIR03_B1_S 8 +#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 +#define ADI_DIR03_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR47 register. +// +//***************************************************************************** +#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 +#define ADI_DIR47_B3_S 24 +#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 +#define ADI_DIR47_B2_S 16 +#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 +#define ADI_DIR47_B1_S 8 +#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 +#define ADI_DIR47_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR811 register. +// +//***************************************************************************** +#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register + // 11 +#define ADI_DIR811_B3_S 24 +#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register + // 10 +#define ADI_DIR811_B2_S 16 +#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 +#define ADI_DIR811_B1_S 8 +#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 +#define ADI_DIR811_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR1215 register. +// +//***************************************************************************** +#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register + // 15 +#define ADI_DIR1215_B3_S 24 +#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register + // 14 +#define ADI_DIR1215_B2_S 16 +#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register + // 13 +#define ADI_DIR1215_B1_S 8 +#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register + // 12 +#define ADI_DIR1215_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET03 register. +// +//***************************************************************************** +#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 3. Read returns 0. +#define ADI_SET03_S3_S 24 +#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 2. Read returns 0. +#define ADI_SET03_S2_S 16 +#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 1. Read returns 0. +#define ADI_SET03_S1_S 8 +#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 0. Read returns 0. +#define ADI_SET03_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET47 register. +// +//***************************************************************************** +#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 7. Read returns 0. +#define ADI_SET47_S3_S 24 +#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 6. Read returns 0. +#define ADI_SET47_S2_S 16 +#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 5. Read returns 0. +#define ADI_SET47_S1_S 8 +#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 4. Read returns 0. +#define ADI_SET47_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET811 register. +// +//***************************************************************************** +#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 11. Read returns 0. +#define ADI_SET811_S3_S 24 +#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 10. Read returns 0. +#define ADI_SET811_S2_S 16 +#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 9. Read returns 0. +#define ADI_SET811_S1_S 8 +#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 8. Read returns 0. +#define ADI_SET811_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET1215 register. +// +//***************************************************************************** +#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 15. Read returns 0. +#define ADI_SET1215_S3_S 24 +#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 14. Read returns 0. +#define ADI_SET1215_S2_S 16 +#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 13. Read returns 0. +#define ADI_SET1215_S1_S 8 +#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 12. Read returns 0. +#define ADI_SET1215_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR03 register. +// +//***************************************************************************** +#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 3 +#define ADI_CLR03_S3_S 24 +#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 2 +#define ADI_CLR03_S2_S 16 +#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 1 +#define ADI_CLR03_S1_S 8 +#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 0 +#define ADI_CLR03_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR47 register. +// +//***************************************************************************** +#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 7 +#define ADI_CLR47_S3_S 24 +#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 6 +#define ADI_CLR47_S2_S 16 +#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 5 +#define ADI_CLR47_S1_S 8 +#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 4 +#define ADI_CLR47_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR811 register. +// +//***************************************************************************** +#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 11 +#define ADI_CLR811_S3_S 24 +#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 10 +#define ADI_CLR811_S2_S 16 +#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 9 +#define ADI_CLR811_S1_S 8 +#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 8 +#define ADI_CLR811_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR1215 register. +// +//***************************************************************************** +#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 15 +#define ADI_CLR1215_S3_S 24 +#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 14 +#define ADI_CLR1215_S2_S 16 +#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 13 +#define ADI_CLR1215_S1_S 8 +#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 12 +#define ADI_CLR1215_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVESTAT register. +// +//***************************************************************************** +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ + // signal. Writing 0 to this bit + // forces a sync with slave, + // ensuring that req will be 0. It + // is recommended to write 0 to + // this register before power down + // of the master. +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK + // signal +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVECONF register. +// +//***************************************************************************** +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer + // accessible when this bit is set. + // (unless sticky_bit_overwrite is + // asserted on top module) +#define ADI_SLAVECONF_CONFLOCK_M \ + 0x00000080 +#define ADI_SLAVECONF_CONFLOCK_S 7 +#define ADI_SLAVECONF_WAITFORACK \ + 0x00000004 // A transaction on the ADI + // interface does not end until ack + // has been received from the slave + // when this bit is set. + +#define ADI_SLAVECONF_WAITFORACK_M \ + 0x00000004 +#define ADI_SLAVECONF_WAITFORACK_S 2 +#define ADI_SLAVECONF_ADICLKSPEED_M \ + 0x00000003 // Sets the period of an ADI + // transactions. All transactions + // takes an even number of clock + // cycles,- ADI clock rising edge + // occurs in the middle of the + // period. Data and ctrl to slave + // is set up in beginning of cycle, + // and data from slave is read in + // after the transaction 00: An ADI + // transaction takes 2 master clock + // cyclkes 01: An ADI transaction + // takes 4 master clock cycles 10: + // And ADI Transaction takes 8 + // master clock cycles 11: An ADI + // transaction takes 16 master + // clock cycles + +#define ADI_SLAVECONF_ADICLKSPEED_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B01 register. +// +//***************************************************************************** +#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 1 +#define ADI_MASK4B01_M1H_S 28 +#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 1, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B01_D1H_S 24 +#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 1 +#define ADI_MASK4B01_M1L_S 20 +#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 1, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B01_D1L_S 16 +#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 0 +#define ADI_MASK4B01_M0H_S 12 +#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 0, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B01_D0H_S 8 +#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 0 +#define ADI_MASK4B01_M0L_S 4 +#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 0, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B01_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B23 register. +// +//***************************************************************************** +#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 3 +#define ADI_MASK4B23_M1H_S 28 +#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 3, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B23_D1H_S 24 +#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 3 +#define ADI_MASK4B23_M1L_S 20 +#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 3, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B23_D1L_S 16 +#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 2 +#define ADI_MASK4B23_M0H_S 12 +#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 2, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B23_D0H_S 8 +#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 2 +#define ADI_MASK4B23_M0L_S 4 +#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 2, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B23_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B45 register. +// +//***************************************************************************** +#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 5 +#define ADI_MASK4B45_M1H_S 28 +#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 5, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B45_D1H_S 24 +#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 5 +#define ADI_MASK4B45_M1L_S 20 +#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 5, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B45_D1L_S 16 +#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 4 +#define ADI_MASK4B45_M0H_S 12 +#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 4, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B45_D0H_S 8 +#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 4 +#define ADI_MASK4B45_M0L_S 4 +#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 4, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B45_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B67 register. +// +//***************************************************************************** +#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 7 +#define ADI_MASK4B67_M1H_S 28 +#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 7, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B67_D1H_S 24 +#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 7 +#define ADI_MASK4B67_M1L_S 20 +#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 7, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B67_D1L_S 16 +#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 6 +#define ADI_MASK4B67_M0H_S 12 +#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 6, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B67_D0H_S 8 +#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 6 +#define ADI_MASK4B67_M0L_S 4 +#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 6, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B67_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B89 register. +// +//***************************************************************************** +#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 9 +#define ADI_MASK4B89_M1H_S 28 +#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 9, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B89_D1H_S 24 +#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 9 +#define ADI_MASK4B89_M1L_S 20 +#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 9, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B89_D1L_S 16 +#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 8 +#define ADI_MASK4B89_M0H_S 12 +#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 8, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B89_D0H_S 8 +#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 8 +#define ADI_MASK4B89_M0L_S 4 +#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 8, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B89_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1011 register. +// +//***************************************************************************** +#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 11 +#define ADI_MASK4B1011_M1H_S 28 +#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 11, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1011_D1H_S 24 +#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 11 +#define ADI_MASK4B1011_M1L_S 20 +#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 11, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1011_D1L_S 16 +#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 10 +#define ADI_MASK4B1011_M0H_S 12 +#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 10, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1011_D0H_S 8 +#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 10 +#define ADI_MASK4B1011_M0L_S 4 +#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 10, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1011_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1213 register. +// +//***************************************************************************** +#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 13 +#define ADI_MASK4B1213_M1H_S 28 +#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 13, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1213_D1H_S 24 +#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 13 +#define ADI_MASK4B1213_M1L_S 20 +#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 13, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1213_D1L_S 16 +#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 12 +#define ADI_MASK4B1213_M0H_S 12 +#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 12, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1213_D0H_S 8 +#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 12 +#define ADI_MASK4B1213_M0L_S 4 +#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 12, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1213_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1415 register. +// +//***************************************************************************** +#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 15 +#define ADI_MASK4B1415_M1H_S 28 +#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 15, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1415_D1H_S 24 +#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 15 +#define ADI_MASK4B1415_M1L_S 20 +#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 15, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1415_D1L_S 16 +#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 14 +#define ADI_MASK4B1415_M0H_S 12 +#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 14, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1415_D0H_S 8 +#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 14 +#define ADI_MASK4B1415_M0L_S 4 +#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 14, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1415_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B01 register. +// +//***************************************************************************** +#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 +#define ADI_MASK8B01_M1_S 24 +#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B01_D1_S 16 +#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 +#define ADI_MASK8B01_M0_S 8 +#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B01_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B23 register. +// +//***************************************************************************** +#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 +#define ADI_MASK8B23_M1_S 24 +#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B23_D1_S 16 +#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 +#define ADI_MASK8B23_M0_S 8 +#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B23_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B45 register. +// +//***************************************************************************** +#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 +#define ADI_MASK8B45_M1_S 24 +#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B45_D1_S 16 +#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 +#define ADI_MASK8B45_M0_S 8 +#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B45_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B67 register. +// +//***************************************************************************** +#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 +#define ADI_MASK8B67_M1_S 24 +#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B67_D1_S 16 +#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 +#define ADI_MASK8B67_M0_S 8 +#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B67_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B89 register. +// +//***************************************************************************** +#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 +#define ADI_MASK8B89_M1_S 24 +#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B89_D1_S 16 +#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 +#define ADI_MASK8B89_M0_S 8 +#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B89_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1011 register. +// +//***************************************************************************** +#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 +#define ADI_MASK8B1011_M1_S 24 +#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1011_D1_S 16 +#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 +#define ADI_MASK8B1011_M0_S 8 +#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1011_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1213 register. +// +//***************************************************************************** +#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 +#define ADI_MASK8B1213_M1_S 24 +#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1213_D1_S 16 +#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 +#define ADI_MASK8B1213_M0_S 8 +#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1213_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1415 register. +// +//***************************************************************************** +#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 +#define ADI_MASK8B1415_M1_S 24 +#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1415_D1_S 16 +#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 +#define ADI_MASK8B1415_M0_S 8 +#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1415_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B01 register. +// +//***************************************************************************** +#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 +#define ADI_MASK16B01_M_S 16 +#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at + // offsets 0 and 1, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B01_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B23 register. +// +//***************************************************************************** +#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 +#define ADI_MASK16B23_M_S 16 +#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at + // offsets 2 and 3, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B23_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B45 register. +// +//***************************************************************************** +#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 +#define ADI_MASK16B45_M_S 16 +#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at + // offsets 4 and 5, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B45_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B67 register. +// +//***************************************************************************** +#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 +#define ADI_MASK16B67_M_S 16 +#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at + // offsets 6 and 7, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B67_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B89 register. +// +//***************************************************************************** +#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 +#define ADI_MASK16B89_M_S 16 +#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at + // offsets 8 and 9, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B89_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1011 register. +// +//***************************************************************************** +#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 +#define ADI_MASK16B1011_M_S 16 +#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at + // offsets 10 and 11, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1011_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1213 register. +// +//***************************************************************************** +#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 +#define ADI_MASK16B1213_M_S 16 +#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at + // offsets 12 and 13, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1213_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1415 register. +// +//***************************************************************************** +#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 +#define ADI_MASK16B1415_M_S 16 +#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at + // offsets 14 and 15, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1415_D_S 0 + +#endif // __HW_ADI_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_2_refsys.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_2_refsys.h new file mode 100644 index 0000000..72ae2eb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_2_refsys.h @@ -0,0 +1,362 @@ +/****************************************************************************** +* Filename: hw_adi_2_refsys_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_2_REFSYS_H__ +#define __HW_ADI_2_REFSYS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_2_REFSYS component +// +//***************************************************************************** +// Internal +#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_REFSYSCTL0 +// +//***************************************************************************** +// Field: [4:0] TRIM_IREF +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL0 +// +//***************************************************************************** +// Field: [7:4] VTRIM_UDIG +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 + +// Field: [3:0] VTRIM_BOD +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL1 +// +//***************************************************************************** +// Field: [7:4] VTRIM_COARSE +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 + +// Field: [3:0] VTRIM_DIG +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL2 +// +//***************************************************************************** +// Field: [2:0] VTRIM_DELTA +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL3 +// +//***************************************************************************** +// Field: [7:6] ITRIM_DIGLDO_LOAD +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 + +// Field: [5:3] ITRIM_DIGLDO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BIAS_120P Internal. Only to be used through TI provided API. +// BIAS_100P Internal. Only to be used through TI provided API. +// BIAS_80P Internal. Only to be used through TI provided API. +// BIAS_60P Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 + +// Field: [2:0] ITRIM_UDIGLDO +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL4 +// +//***************************************************************************** +// Field: [6:5] UDIG_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 + +// Field: [4:2] DIG_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 + +// Field: [1] BIAS_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 + +// Field: [0] UDIG_LDO_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL5 +// +//***************************************************************************** +// Field: [3] IMON_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 + +// Field: [2:0] TESTSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDD_AON Internal. Only to be used through TI provided API. +// VREF_AMP Internal. Only to be used through TI provided API. +// ITEST Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL0 +// +//***************************************************************************** +// Field: [7] FILTER_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 + +// Field: [6:5] BIAS_RECHARGE_DLY +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// MIN_DLY_X8 Internal. Only to be used through TI provided API. +// MIN_DLY_X4 Internal. Only to be used through TI provided API. +// MIN_DLY_X2 Internal. Only to be used through TI provided API. +// MIN_DLY_X1 Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 + +// Field: [4:3] TUNE_CAP +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SHIFT_M108 Internal. Only to be used through TI provided API. +// SHIFT_M70 Internal. Only to be used through TI provided API. +// SHIFT_M35 Internal. Only to be used through TI provided API. +// SHIFT_0 Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 + +// Field: [2:1] SERIES_CAP +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 + +// Field: [0] DIV3_BYPASS +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// HPOSC_2520MHZ Internal. Only to be used through TI provided API. +// HPOSC_840MHZ Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL1 +// +//***************************************************************************** +// Field: [5] BIAS_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 + +// Field: [4] PWRDET_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 + +// Field: [3:0] BIAS_RES_SET +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL2 +// +//***************************************************************************** +// Field: [7] BIAS_HOLD_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 + +// Field: [6] TESTMUX_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 + +// Field: [5:4] ATEST_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 + +// Field: [3:0] CURRMIRR_RATIO +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 + + +#endif // __ADI_2_REFSYS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_3_refsys.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_3_refsys.h new file mode 100644 index 0000000..deedeba --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_3_refsys.h @@ -0,0 +1,481 @@ +/****************************************************************************** +* Filename: hw_adi_3_refsys_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_3_REFSYS_H__ +#define __HW_ADI_3_REFSYS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_3_REFSYS component +// +//***************************************************************************** +// Analog Test Control +#define ADI_3_REFSYS_O_SPARE0 0x00000001 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 + +// DCDC Control 0 +#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 + +// DCDC Control 1 +#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 + +// DCDC Control 2 +#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 + +// DCDC Control 3 +#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 + +// Internal +#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A + +// Internal +#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_SPARE0 +// +//***************************************************************************** +// Field: [7:0] SPARE0 +// +// Software should not rely on the value of a reserved. Writing any other value +// than the reset value may result in undefined behavior. +#define ADI_3_REFSYS_SPARE0_SPARE0_W 8 +#define ADI_3_REFSYS_SPARE0_SPARE0_M 0x000000FF +#define ADI_3_REFSYS_SPARE0_SPARE0_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL0 +// +//***************************************************************************** +// Field: [7:0] TESTCTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BMCOMPOUT Internal. Only to be used through TI provided API. +// VTEMP Internal. Only to be used through TI provided API. +// VREF0P8V Internal. Only to be used through TI provided API. +// VBGUNBUFF Internal. Only to be used through TI provided API. +// VBG Internal. Only to be used through TI provided API. +// IREF4U Internal. Only to be used through TI provided API. +// IVREF4U Internal. Only to be used through TI provided API. +// IPTAT2U Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL1 +// +//***************************************************************************** +// Field: [7:3] TRIM_VDDS_BOD +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// POS_27 Internal. Only to be used through TI provided API. +// POS_26 Internal. Only to be used through TI provided API. +// POS_25 Internal. Only to be used through TI provided API. +// POS_24 Internal. Only to be used through TI provided API. +// POS_31 Internal. Only to be used through TI provided API. +// POS_30 Internal. Only to be used through TI provided API. +// POS_29 Internal. Only to be used through TI provided API. +// POS_28 Internal. Only to be used through TI provided API. +// POS_19 Internal. Only to be used through TI provided API. +// POS_18 Internal. Only to be used through TI provided API. +// POS_17 Internal. Only to be used through TI provided API. +// POS_16 Internal. Only to be used through TI provided API. +// POS_23 Internal. Only to be used through TI provided API. +// POS_22 Internal. Only to be used through TI provided API. +// POS_21 Internal. Only to be used through TI provided API. +// POS_20 Internal. Only to be used through TI provided API. +// POS_11 Internal. Only to be used through TI provided API. +// POS_10 Internal. Only to be used through TI provided API. +// POS_9 Internal. Only to be used through TI provided API. +// POS_8 Internal. Only to be used through TI provided API. +// POS_15 Internal. Only to be used through TI provided API. +// POS_14 Internal. Only to be used through TI provided API. +// POS_13 Internal. Only to be used through TI provided API. +// POS_12 Internal. Only to be used through TI provided API. +// POS_3 Internal. Only to be used through TI provided API. +// POS_2 Internal. Only to be used through TI provided API. +// POS_1 Internal. Only to be used through TI provided API. +// POS_0 Internal. Only to be used through TI provided API. +// POS_7 Internal. Only to be used through TI provided API. +// POS_6 Internal. Only to be used through TI provided API. +// POS_5 Internal. Only to be used through TI provided API. +// POS_4 Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 + +// Field: [2] BATMON_COMP_TEST_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 + +// Field: [1:0] TESTCTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// IPTAT1U Internal. Only to be used through TI provided API. +// BMCOMPIN Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL2 +// +//***************************************************************************** +// Field: [7:4] TRIM_VREF +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 + +// Field: [1:0] TRIM_TSENSE +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL3 +// +//***************************************************************************** +// Field: [7] BOD_BG_TRIM_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 + +// Field: [6] VTEMP_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 + +// Field: [5:0] TRIM_VBG +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL0 +// +//***************************************************************************** +// Field: [7:5] GLDO_ISRC +// +// Set charge and re-charge current level. +// 2's complement encoding. +// +// 0x0: Default 11mA. +// 0x3: Max 15mA. +// 0x4: Max 5mA +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 + +// Field: [4:0] VDDR_TRIM +// +// Set the VDDR voltage. +// Proprietary encoding. +// +// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. +// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. +// Step size = 16mV +// +// 0x00: Default, about 1.63V. +// 0x05: Typical voltage after trim voltage 1.71V. +// 0x15: Max voltage 1.96V. +// 0x16: Min voltage 1.47V. +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL1 +// +//***************************************************************************** +// Field: [7:6] IPTAT_TRIM +// +// Trim GLDO bias current. +// Proprietary encoding. +// +// 0x0: Default +// 0x1: Increase GLDO bias by 1.3x. +// 0x2: Increase GLDO bias by 1.6x. +// 0x3: Decrease GLDO bias by 0.7x. +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 + +// Field: [5] VDDR_OK_HYST +// +// Increase the hysteresis for when VDDR is considered ok. +// +// 0: Hysteresis = 60mV +// 1: Hysteresis = 70mV +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 + +// Field: [4:0] VDDR_TRIM_SLEEP +// +// Set the min VDDR voltage threshold during sleep mode. +// Proprietary encoding. +// +// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. +// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. +// Step size = 16mV +// +// 0x00: Default, about 1.63V. +// 0x19: Typical voltage after trim voltage 1.52V. +// 0x15: Max voltage 1.96V. +// 0x16: Min voltage 1.47V. +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL2 +// +//***************************************************************************** +// Field: [6] TURNON_EA_SW +// +// Turn on erroramp switch +// +// 0: Erroramp Off (Default) +// 1: Erroramp On. Turns on GLDO error amp switch. +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 + +// Field: [5] TEST_VDDR +// +// Connect VDDR to ATEST bus +// +// 0: Not connected. +// 1: Connected +// +// Set TESTSEL = 0x0 first before setting this bit. +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 + +// Field: [4] BIAS_DIS +// +// Disable dummy bias current. +// +// 0: Dummy bias current on (Default) +// 1: Dummy bias current off +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 + +// Field: [3:0] TESTSEL +// +// Select signal for test bus, one hot. +// ENUMs: +// VDDROK VDDR_OK connected to test bus. +// IB1U 1uA bias current connected to test bus. +// PASSGATE Pass transistor gate voltage connected to test +// bus. +// ERRAMP_OUT Error amp output voltage connected to test bus. +// NC No signal connected to test bus. +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL4 +// +//***************************************************************************** +// Field: [7:6] DEADTIME_TRIM +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 + +// Field: [5:3] LOW_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 + +// Field: [2:0] HIGH_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL5 +// +//***************************************************************************** +// Field: [5] TESTN +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 + +// Field: [4] TESTP +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 + +// Field: [3] DITHER_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 + +// Field: [2:0] IPEAK +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 + + +#endif // __ADI_3_REFSYS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_4_aux.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_4_aux.h new file mode 100644 index 0000000..af14ac4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_4_aux.h @@ -0,0 +1,490 @@ +/****************************************************************************** +* Filename: hw_adi_4_aux_h +* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) +* Revision: 48904 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_4_AUX_H__ +#define __HW_ADI_4_AUX_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_4_AUX component +// +//***************************************************************************** +// Internal +#define ADI_4_AUX_O_MUX0 0x00000000 + +// Internal +#define ADI_4_AUX_O_MUX1 0x00000001 + +// Internal +#define ADI_4_AUX_O_MUX2 0x00000002 + +// Internal +#define ADI_4_AUX_O_MUX3 0x00000003 + +// Current Source +#define ADI_4_AUX_O_ISRC 0x00000004 + +// Comparator +#define ADI_4_AUX_O_COMP 0x00000005 + +// Internal +#define ADI_4_AUX_O_MUX4 0x00000007 + +// ADC Control 0 +#define ADI_4_AUX_O_ADC0 0x00000008 + +// ADC Control 1 +#define ADI_4_AUX_O_ADC1 0x00000009 + +// ADC Reference 0 +#define ADI_4_AUX_O_ADCREF0 0x0000000A + +// ADC Reference 1 +#define ADI_4_AUX_O_ADCREF1 0x0000000B + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX0 +// +//***************************************************************************** +// Field: [3:0] COMPA_REF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// ADCVREFP Internal. Only to be used through TI provided API. +// VDDS Internal. Only to be used through TI provided API. +// VSS Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX0_COMPA_REF_W 4 +#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F +#define ADI_4_AUX_MUX0_COMPA_REF_S 0 +#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008 +#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004 +#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002 +#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX1 +// +//***************************************************************************** +// Field: [7:0] COMPA_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO0 Internal. Only to be used through TI provided API. +// AUXIO1 Internal. Only to be used through TI provided API. +// AUXIO2 Internal. Only to be used through TI provided API. +// AUXIO3 Internal. Only to be used through TI provided API. +// AUXIO4 Internal. Only to be used through TI provided API. +// AUXIO5 Internal. Only to be used through TI provided API. +// AUXIO6 Internal. Only to be used through TI provided API. +// AUXIO7 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX1_COMPA_IN_W 8 +#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF +#define ADI_4_AUX_MUX1_COMPA_IN_S 0 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX2 +// +//***************************************************************************** +// Field: [7:3] ADCCOMPB_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDDS Internal. Only to be used through TI provided API. +// VSS Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// ATEST1 Internal. Only to be used through TI provided API. +// ATEST0 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000 + +// Field: [2:0] COMPB_REF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDDS Internal. Only to be used through TI provided API. +// VSS Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX2_COMPB_REF_W 3 +#define ADI_4_AUX_MUX2_COMPB_REF_M 0x00000007 +#define ADI_4_AUX_MUX2_COMPB_REF_S 0 +#define ADI_4_AUX_MUX2_COMPB_REF_VDDS 0x00000004 +#define ADI_4_AUX_MUX2_COMPB_REF_VSS 0x00000002 +#define ADI_4_AUX_MUX2_COMPB_REF_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX2_COMPB_REF_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX3 +// +//***************************************************************************** +// Field: [7:0] ADCCOMPB_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO0 Internal. Only to be used through TI provided API. +// AUXIO1 Internal. Only to be used through TI provided API. +// AUXIO2 Internal. Only to be used through TI provided API. +// AUXIO3 Internal. Only to be used through TI provided API. +// AUXIO4 Internal. Only to be used through TI provided API. +// AUXIO5 Internal. Only to be used through TI provided API. +// AUXIO6 Internal. Only to be used through TI provided API. +// AUXIO7 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ISRC +// +//***************************************************************************** +// Field: [7:2] TRIM +// +// Adjust current from current source. +// +// Output currents may be combined to get desired total current. +// ENUMs: +// 11P75U 11.75 uA +// 4P5U 4.5 uA +// 2P0U 2.0 uA +// 1P0U 1.0 uA +// 0P5U 0.5 uA +// 0P25U 0.25 uA +// NC No current connected +#define ADI_4_AUX_ISRC_TRIM_W 6 +#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC +#define ADI_4_AUX_ISRC_TRIM_S 2 +#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080 +#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040 +#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020 +#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010 +#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008 +#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004 +#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000 + +// Field: [0] EN +// +// Current source enable +#define ADI_4_AUX_ISRC_EN 0x00000001 +#define ADI_4_AUX_ISRC_EN_M 0x00000001 +#define ADI_4_AUX_ISRC_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_COMP +// +//***************************************************************************** +// Field: [7] COMPA_REF_RES_EN +// +// Enables 400kohm resistance from COMPA reference node to ground. Used with +// COMPA_REF_CURR_EN to generate voltage reference for cap-sense. +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7 + +// Field: [6] COMPA_REF_CURR_EN +// +// Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires +// ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for +// cap-sense. +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 + +// Field: [5:3] COMPB_TRIM +// +// COMPB voltage reference trim temperature coded: +// ENUMs: +// DIV4 Divide reference by 4 +// DIV3 Divide reference by 3 +// DIV2 Divide reference by 2 +// DIV1 No reference division +#define ADI_4_AUX_COMP_COMPB_TRIM_W 3 +#define ADI_4_AUX_COMP_COMPB_TRIM_M 0x00000038 +#define ADI_4_AUX_COMP_COMPB_TRIM_S 3 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV4 0x00000038 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV3 0x00000018 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV2 0x00000008 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV1 0x00000000 + +// Field: [2] COMPB_EN +// +// COMPB enable +#define ADI_4_AUX_COMP_COMPB_EN 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_S 2 + +// Field: [0] COMPA_EN +// +// COMPA enable +#define ADI_4_AUX_COMP_COMPA_EN 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX4 +// +//***************************************************************************** +// Field: [7:0] COMPA_REF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO0 Internal. Only to be used through TI provided API. +// AUXIO1 Internal. Only to be used through TI provided API. +// AUXIO2 Internal. Only to be used through TI provided API. +// AUXIO3 Internal. Only to be used through TI provided API. +// AUXIO4 Internal. Only to be used through TI provided API. +// AUXIO5 Internal. Only to be used through TI provided API. +// AUXIO6 Internal. Only to be used through TI provided API. +// AUXIO7 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX4_COMPA_REF_W 8 +#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF +#define ADI_4_AUX_MUX4_COMPA_REF_S 0 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADC0 +// +//***************************************************************************** +// Field: [7] SMPL_MODE +// +// ADC Sampling mode: +// +// 0: Synchronous mode +// 1: Asynchronous mode +// +// The ADC does a sample-and-hold before conversion. In synchronous mode the +// sampling starts when the ADC clock detects a rising edge on the trigger +// signal. Jitter/uncertainty will be inferred in the detection if the trigger +// signal originates from a domain that is asynchronous to the ADC clock. +// SMPL_CYCLE_EXP determines the the duration of sampling. +// Conversion starts immediately after sampling ends. +// +// In asynchronous mode the sampling is continuous when enabled. Sampling ends +// and conversion starts immediately with the rising edge of the trigger +// signal. Sampling restarts when the conversion has finished. +// Asynchronous mode is useful when it is important to avoid jitter in the +// sampling instant of an externally driven signal +#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_S 7 + +// Field: [6:3] SMPL_CYCLE_EXP +// +// Controls the sampling duration before conversion when the ADC is operated in +// synchronous mode (SMPL_MODE = 0). The setting has no effect in asynchronous +// mode. The sampling duration is given as 2^(SMPL_CYCLE_EXP + 1) / 6 us. +// ENUMs: +// 10P9_MS 65536x 6 MHz clock periods = 10.9ms +// 5P46_MS 32768x 6 MHz clock periods = 5.46ms +// 2P73_MS 16384x 6 MHz clock periods = 2.73ms +// 1P37_MS 8192x 6 MHz clock periods = 1.37ms +// 682_US 4096x 6 MHz clock periods = 682us +// 341_US 2048x 6 MHz clock periods = 341us +// 170_US 1024x 6 MHz clock periods = 170us +// 85P3_US 512x 6 MHz clock periods = 85.3us +// 42P6_US 256x 6 MHz clock periods = 42.6us +// 21P3_US 128x 6 MHz clock periods = 21.3us +// 10P6_US 64x 6 MHz clock periods = 10.6us +// 5P3_US 32x 6 MHz clock periods = 5.3us +// 2P7_US 16x 6 MHz clock periods = 2.7us +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018 + +// Field: [1] RESET_N +// +// Reset ADC digital subchip, active low. ADC must be reset every time it is +// reconfigured. +// +// 0: Reset +// 1: Normal operation +#define ADI_4_AUX_ADC0_RESET_N 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_S 1 + +// Field: [0] EN +// +// ADC Enable +// +// 0: Disable +// 1: Enable +#define ADI_4_AUX_ADC0_EN 0x00000001 +#define ADI_4_AUX_ADC0_EN_M 0x00000001 +#define ADI_4_AUX_ADC0_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADC1 +// +//***************************************************************************** +// Field: [0] SCALE_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADCREF0 +// +//***************************************************************************** +// Field: [6] REF_ON_IDLE +// +// Keep ADCREF powered up in IDLE state when ADC0.SMPL_MODE = 0. +// +// Set to 1 if ADC0.SMPL_CYCLE_EXP is less than 6 (21.3us sampling time) +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 + +// Field: [5] IOMUX +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_S 5 + +// Field: [4] EXT +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADCREF0_EXT 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_S 4 + +// Field: [3] SRC +// +// ADC reference source: +// +// 0: Fixed reference = 4.3V +// 1: Relative reference = VDDS +#define ADI_4_AUX_ADCREF0_SRC 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_S 3 + +// Field: [0] EN +// +// ADC reference module enable: +// +// 0: ADC reference module powered down +// 1: ADC reference module enabled +#define ADI_4_AUX_ADCREF0_EN 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_M 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADCREF1 +// +//***************************************************************************** +// Field: [5:0] VTRIM +// +// Trim output voltage of ADC fixed reference (64 steps, 2's complement). +// Applies only for ADCREF0.SRC = 0. +// +// Examples: +// 0x00 - nominal voltage 1.43V +// 0x01 - nominal + 0.4% 1.435V +// 0x3F - nominal - 0.4% 1.425V +// 0x1F - maximum voltage 1.6V +// 0x20 - minimum voltage 1.3V +#define ADI_4_AUX_ADCREF1_VTRIM_W 6 +#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F +#define ADI_4_AUX_ADCREF1_VTRIM_S 0 + + +#endif // __ADI_4_AUX__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_batmon.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_batmon.h new file mode 100644 index 0000000..f09256d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_batmon.h @@ -0,0 +1,340 @@ +/****************************************************************************** +* Filename: hw_aon_batmon_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_BATMON_H__ +#define __HW_AON_BATMON_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_BATMON component +// +//***************************************************************************** +// Internal +#define AON_BATMON_O_CTL 0x00000000 + +// Internal +#define AON_BATMON_O_MEASCFG 0x00000004 + +// Internal +#define AON_BATMON_O_TEMPP0 0x0000000C + +// Internal +#define AON_BATMON_O_TEMPP1 0x00000010 + +// Internal +#define AON_BATMON_O_TEMPP2 0x00000014 + +// Internal +#define AON_BATMON_O_BATMONP0 0x00000018 + +// Internal +#define AON_BATMON_O_BATMONP1 0x0000001C + +// Internal +#define AON_BATMON_O_IOSTRP0 0x00000020 + +// Internal +#define AON_BATMON_O_FLASHPUMPP0 0x00000024 + +// Last Measured Battery Voltage +#define AON_BATMON_O_BAT 0x00000028 + +// Battery Update +#define AON_BATMON_O_BATUPD 0x0000002C + +// Temperature +#define AON_BATMON_O_TEMP 0x00000030 + +// Temperature Update +#define AON_BATMON_O_TEMPUPD 0x00000034 + +//***************************************************************************** +// +// Register: AON_BATMON_O_CTL +// +//***************************************************************************** +// Field: [1] CALC_EN +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_CTL_CALC_EN 0x00000002 +#define AON_BATMON_CTL_CALC_EN_BITN 1 +#define AON_BATMON_CTL_CALC_EN_M 0x00000002 +#define AON_BATMON_CTL_CALC_EN_S 1 + +// Field: [0] MEAS_EN +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_CTL_MEAS_EN 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_BITN 0 +#define AON_BATMON_CTL_MEAS_EN_M 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_MEASCFG +// +//***************************************************************************** +// Field: [1:0] PER +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 32CYC Internal. Only to be used through TI provided API. +// 16CYC Internal. Only to be used through TI provided API. +// 8CYC Internal. Only to be used through TI provided API. +// CONT Internal. Only to be used through TI provided API. +#define AON_BATMON_MEASCFG_PER_W 2 +#define AON_BATMON_MEASCFG_PER_M 0x00000003 +#define AON_BATMON_MEASCFG_PER_S 0 +#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003 +#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002 +#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001 +#define AON_BATMON_MEASCFG_PER_CONT 0x00000000 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP0 +// +//***************************************************************************** +// Field: [7:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP0_CFG_W 8 +#define AON_BATMON_TEMPP0_CFG_M 0x000000FF +#define AON_BATMON_TEMPP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP1 +// +//***************************************************************************** +// Field: [5:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP1_CFG_W 6 +#define AON_BATMON_TEMPP1_CFG_M 0x0000003F +#define AON_BATMON_TEMPP1_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP2 +// +//***************************************************************************** +// Field: [4:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP2_CFG_W 5 +#define AON_BATMON_TEMPP2_CFG_M 0x0000001F +#define AON_BATMON_TEMPP2_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATMONP0 +// +//***************************************************************************** +// Field: [5:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_BATMONP0_CFG_W 6 +#define AON_BATMON_BATMONP0_CFG_M 0x0000003F +#define AON_BATMON_BATMONP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATMONP1 +// +//***************************************************************************** +// Field: [5:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_BATMONP1_CFG_W 6 +#define AON_BATMON_BATMONP1_CFG_M 0x0000003F +#define AON_BATMON_BATMONP1_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_IOSTRP0 +// +//***************************************************************************** +// Field: [5:4] CFG2 +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_IOSTRP0_CFG2_W 2 +#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030 +#define AON_BATMON_IOSTRP0_CFG2_S 4 + +// Field: [3:0] CFG1 +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_IOSTRP0_CFG1_W 4 +#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F +#define AON_BATMON_IOSTRP0_CFG1_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_FLASHPUMPP0 +// +//***************************************************************************** +// Field: [8] FALLB +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8 +#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_S 8 + +// Field: [7:6] HIGHLIM +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6 + +// Field: [5] LOWLIM +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5 + +// Field: [4] OVR +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4 +#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_S 4 + +// Field: [3:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_CFG_W 4 +#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F +#define AON_BATMON_FLASHPUMPP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BAT +// +//***************************************************************************** +// Field: [10:8] INT +// +// Integer part: +// +// 0x0: 0V + fractional part +// ... +// 0x3: 3V + fractional part +// 0x4: 4V + fractional part +#define AON_BATMON_BAT_INT_W 3 +#define AON_BATMON_BAT_INT_M 0x00000700 +#define AON_BATMON_BAT_INT_S 8 + +// Field: [7:0] FRAC +// +// Fractional part, standard binary fractional encoding. +// +// 0x00: .0V +// ... +// 0x20: 1/8 = .125V +// 0x40: 1/4 = .25V +// 0x80: 1/2 = .5V +// ... +// 0xA0: 1/2 + 1/8 = .625V +// ... +// 0xFF: Max +#define AON_BATMON_BAT_FRAC_W 8 +#define AON_BATMON_BAT_FRAC_M 0x000000FF +#define AON_BATMON_BAT_FRAC_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATUPD +// +//***************************************************************************** +// Field: [0] STAT +// +// +// 0: No update since last clear +// 1: New battery voltage is present. +// +// Write 1 to clear the status. +#define AON_BATMON_BATUPD_STAT 0x00000001 +#define AON_BATMON_BATUPD_STAT_BITN 0 +#define AON_BATMON_BATUPD_STAT_M 0x00000001 +#define AON_BATMON_BATUPD_STAT_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMP +// +//***************************************************************************** +// Field: [16:8] INT +// +// Integer part (signed) of temperature value. +// Total value = INTEGER + FRACTIONAL +// 2's complement encoding +// +// 0x100: Min value +// 0x1D8: -40C +// 0x1FF: -1C +// 0x00: 0C +// 0x1B: 27C +// 0x55: 85C +// 0xFF: Max value +#define AON_BATMON_TEMP_INT_W 9 +#define AON_BATMON_TEMP_INT_M 0x0001FF00 +#define AON_BATMON_TEMP_INT_S 8 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPUPD +// +//***************************************************************************** +// Field: [0] STAT +// +// +// 0: No update since last clear +// 1: New temperature is present. +// +// Write 1 to clear the status. +#define AON_BATMON_TEMPUPD_STAT 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_BITN 0 +#define AON_BATMON_TEMPUPD_STAT_M 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_S 0 + + +#endif // __AON_BATMON__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_event.h new file mode 100644 index 0000000..2896b81 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_event.h @@ -0,0 +1,1533 @@ +/****************************************************************************** +* Filename: hw_aon_event_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_EVENT_H__ +#define __HW_AON_EVENT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_EVENT component +// +//***************************************************************************** +// Wake-up Selector For MCU +#define AON_EVENT_O_MCUWUSEL 0x00000000 + +// Wake-up Selector For AUX +#define AON_EVENT_O_AUXWUSEL 0x00000004 + +// Event Selector For MCU Event Fabric +#define AON_EVENT_O_EVTOMCUSEL 0x00000008 + +// RTC Capture Event Selector For AON_RTC +#define AON_EVENT_O_RTCSEL 0x0000000C + +//***************************************************************************** +// +// Register: AON_EVENT_O_MCUWUSEL +// +//***************************************************************************** +// Field: [29:24] WU3_EV +// +// MCU Wakeup Source #3 +// +// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the +// MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_MCUWUSEL_WU3_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_S 24 +#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD31 0x1F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD30 0x1E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD29 0x1D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD28 0x1C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD27 0x1B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD26 0x1A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD25 0x19000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD24 0x18000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD23 0x17000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD22 0x16000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD21 0x15000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD20 0x14000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD19 0x13000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD18 0x12000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD17 0x11000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD16 0x10000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD15 0x0F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD14 0x0E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD13 0x0D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD12 0x0C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD11 0x0B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD10 0x0A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD9 0x09000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD8 0x08000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD7 0x07000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD6 0x06000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD5 0x05000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD4 0x04000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD3 0x03000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD2 0x02000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD1 0x01000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD0 0x00000000 + +// Field: [21:16] WU2_EV +// +// MCU Wakeup Source #2 +// +// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the +// MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_MCUWUSEL_WU2_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_S 16 +#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD31 0x001F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD30 0x001E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD29 0x001D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD28 0x001C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD27 0x001B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD26 0x001A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD25 0x00190000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD24 0x00180000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD23 0x00170000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD22 0x00160000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD21 0x00150000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD20 0x00140000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD19 0x00130000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD18 0x00120000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD17 0x00110000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD16 0x00100000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD15 0x000F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD14 0x000E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD13 0x000D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD12 0x000C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD11 0x000B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD10 0x000A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD9 0x00090000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD8 0x00080000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD7 0x00070000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD6 0x00060000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD5 0x00050000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD4 0x00040000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD3 0x00030000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD2 0x00020000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD1 0x00010000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD0 0x00000000 + +// Field: [13:8] WU1_EV +// +// MCU Wakeup Source #1 +// +// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the +// MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_MCUWUSEL_WU1_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_S 8 +#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD31 0x00001F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD30 0x00001E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD29 0x00001D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD28 0x00001C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD27 0x00001B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD26 0x00001A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD25 0x00001900 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD24 0x00001800 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD23 0x00001700 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD22 0x00001600 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD21 0x00001500 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD20 0x00001400 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD19 0x00001300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD18 0x00001200 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD17 0x00001100 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD16 0x00001000 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD15 0x00000F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD14 0x00000E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD13 0x00000D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD12 0x00000C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD11 0x00000B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD10 0x00000A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD9 0x00000900 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD8 0x00000800 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD7 0x00000700 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD6 0x00000600 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD5 0x00000500 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD4 0x00000400 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD3 0x00000300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD2 0x00000200 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD1 0x00000100 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD0 0x00000000 + +// Field: [5:0] WU0_EV +// +// MCU Wakeup Source #0 +// +// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the +// MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_MCUWUSEL_WU0_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_S 0 +#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD31 0x0000001F +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD30 0x0000001E +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD29 0x0000001D +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD28 0x0000001C +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD27 0x0000001B +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD26 0x0000001A +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD25 0x00000019 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD24 0x00000018 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD23 0x00000017 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD22 0x00000016 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD21 0x00000015 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD20 0x00000014 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD19 0x00000013 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD18 0x00000012 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD17 0x00000011 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD16 0x00000010 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD15 0x0000000F +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD14 0x0000000E +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD13 0x0000000D +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD12 0x0000000C +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD11 0x0000000B +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD10 0x0000000A +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD9 0x00000009 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD8 0x00000008 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD7 0x00000007 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD6 0x00000006 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD5 0x00000005 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD4 0x00000004 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD3 0x00000003 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD2 0x00000002 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD1 0x00000001 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD0 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_AUXWUSEL +// +//***************************************************************************** +// Field: [21:16] WU2_EV +// +// AUX Wakeup Source #2 +// +// AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the +// AUX domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_AUXWUSEL_WU2_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU2_EV_M 0x003F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_S 16 +#define AON_EVENT_AUXWUSEL_WU2_EV_NONE 0x003F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_JTAG 0x002B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD 0x00200000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD31 0x001F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD30 0x001E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD29 0x001D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD28 0x001C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD27 0x001B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD26 0x001A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD25 0x00190000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD24 0x00180000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD23 0x00170000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD22 0x00160000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD21 0x00150000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD20 0x00140000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD19 0x00130000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD18 0x00120000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD17 0x00110000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD16 0x00100000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD15 0x000F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD14 0x000E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD13 0x000D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD12 0x000C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD11 0x000B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD10 0x000A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD9 0x00090000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD8 0x00080000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD7 0x00070000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD6 0x00060000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD5 0x00050000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD4 0x00040000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD3 0x00030000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD2 0x00020000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD1 0x00010000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD0 0x00000000 + +// Field: [13:8] WU1_EV +// +// AUX Wakeup Source #1 +// +// AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the +// AUX domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_AUXWUSEL_WU1_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU1_EV_M 0x00003F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_S 8 +#define AON_EVENT_AUXWUSEL_WU1_EV_NONE 0x00003F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_JTAG 0x00002B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD 0x00002000 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD31 0x00001F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD30 0x00001E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD29 0x00001D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD28 0x00001C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD27 0x00001B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD26 0x00001A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD25 0x00001900 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD24 0x00001800 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD23 0x00001700 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD22 0x00001600 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD21 0x00001500 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD20 0x00001400 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD19 0x00001300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD18 0x00001200 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD17 0x00001100 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD16 0x00001000 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD15 0x00000F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD14 0x00000E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD13 0x00000D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD12 0x00000C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD11 0x00000B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD10 0x00000A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD9 0x00000900 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD8 0x00000800 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD7 0x00000700 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD6 0x00000600 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD5 0x00000500 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD4 0x00000400 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD3 0x00000300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD2 0x00000200 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD1 0x00000100 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD0 0x00000000 + +// Field: [5:0] WU0_EV +// +// AUX Wakeup Source #0 +// +// AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the +// AUX domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_AUXWUSEL_WU0_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU0_EV_M 0x0000003F +#define AON_EVENT_AUXWUSEL_WU0_EV_S 0 +#define AON_EVENT_AUXWUSEL_WU0_EV_NONE 0x0000003F +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_AUXWUSEL_WU0_EV_JTAG 0x0000002B +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD 0x00000020 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD31 0x0000001F +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD30 0x0000001E +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD29 0x0000001D +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD28 0x0000001C +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD27 0x0000001B +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD26 0x0000001A +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD25 0x00000019 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD24 0x00000018 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD23 0x00000017 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD22 0x00000016 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD21 0x00000015 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD20 0x00000014 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD19 0x00000013 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD18 0x00000012 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD17 0x00000011 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD16 0x00000010 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD15 0x0000000F +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD14 0x0000000E +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD13 0x0000000D +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD12 0x0000000C +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD11 0x0000000B +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD10 0x0000000A +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD9 0x00000009 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD8 0x00000008 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD7 0x00000007 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD6 0x00000006 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD5 0x00000005 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD4 0x00000004 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD3 0x00000003 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD2 0x00000002 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD1 0x00000001 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD0 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_EVTOMCUSEL +// +//***************************************************************************** +// Field: [21:16] AON_PROG2_EV +// +// Event selector for AON_PROG2 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG2 event. +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD31 0x001F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD30 0x001E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD29 0x001D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD28 0x001C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD27 0x001B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD26 0x001A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD25 0x00190000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD24 0x00180000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD23 0x00170000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD22 0x00160000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD21 0x00150000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD20 0x00140000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD19 0x00130000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD18 0x00120000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD17 0x00110000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD16 0x00100000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD15 0x000F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD14 0x000E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD13 0x000D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD12 0x000C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD11 0x000B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD10 0x000A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD9 0x00090000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD8 0x00080000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD7 0x00070000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD6 0x00060000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD5 0x00050000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD4 0x00040000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD3 0x00030000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD2 0x00020000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD1 0x00010000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD0 0x00000000 + +// Field: [13:8] AON_PROG1_EV +// +// Event selector for AON_PROG1 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG1 event. +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD31 0x00001F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD30 0x00001E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD29 0x00001D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD28 0x00001C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD27 0x00001B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD26 0x00001A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD25 0x00001900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD24 0x00001800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD23 0x00001700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD22 0x00001600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD21 0x00001500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD20 0x00001400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD19 0x00001300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD18 0x00001200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD17 0x00001100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD16 0x00001000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD15 0x00000F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD14 0x00000E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD13 0x00000D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD12 0x00000C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD11 0x00000B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD10 0x00000A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD9 0x00000900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD8 0x00000800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD7 0x00000700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD6 0x00000600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD5 0x00000500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD4 0x00000400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD3 0x00000300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD2 0x00000200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD1 0x00000100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD0 0x00000000 + +// Field: [5:0] AON_PROG0_EV +// +// Event selector for AON_PROG0 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG0 event. +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD31 0x0000001F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD30 0x0000001E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD29 0x0000001D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD28 0x0000001C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD27 0x0000001B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD26 0x0000001A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD25 0x00000019 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD24 0x00000018 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD23 0x00000017 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD22 0x00000016 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD21 0x00000015 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD20 0x00000014 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD19 0x00000013 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD18 0x00000012 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD17 0x00000011 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD16 0x00000010 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD15 0x0000000F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD14 0x0000000E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD13 0x0000000D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD12 0x0000000C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD11 0x0000000B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD10 0x0000000A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD9 0x00000009 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD8 0x00000008 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD7 0x00000007 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD6 0x00000006 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD5 0x00000005 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD4 0x00000004 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD3 0x00000003 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD2 0x00000002 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD1 0x00000001 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD0 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_RTCSEL +// +//***************************************************************************** +// Field: [5:0] RTC_CH1_CAPT_EV +// +// AON Event Source id# for RTCSEL event which is fed to AON_RTC. Please refer +// to AON_RTC:CH1CAPT +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD31 0x0000001F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD30 0x0000001E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD29 0x0000001D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD28 0x0000001C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD27 0x0000001B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD26 0x0000001A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD25 0x00000019 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD24 0x00000018 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD23 0x00000017 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD22 0x00000016 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD21 0x00000015 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD20 0x00000014 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD19 0x00000013 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD18 0x00000012 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD17 0x00000011 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD16 0x00000010 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD15 0x0000000F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD14 0x0000000E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD13 0x0000000D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD12 0x0000000C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD11 0x0000000B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD10 0x0000000A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD9 0x00000009 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD8 0x00000008 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD7 0x00000007 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD6 0x00000006 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD5 0x00000005 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD4 0x00000004 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD3 0x00000003 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD2 0x00000002 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD1 0x00000001 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD0 0x00000000 + + +#endif // __AON_EVENT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_ioc.h new file mode 100644 index 0000000..98ecbed --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_ioc.h @@ -0,0 +1,141 @@ +/****************************************************************************** +* Filename: hw_aon_ioc_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_IOC_H__ +#define __HW_AON_IOC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_IOC component +// +//***************************************************************************** +// Internal +#define AON_IOC_O_IOSTRMIN 0x00000000 + +// Internal +#define AON_IOC_O_IOSTRMED 0x00000004 + +// Internal +#define AON_IOC_O_IOSTRMAX 0x00000008 + +// IO Latch Control +#define AON_IOC_O_IOCLATCH 0x0000000C + +// SCLK_LF External Output Control +#define AON_IOC_O_CLK32KCTL 0x00000010 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMIN +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMED +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMED_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMED_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMAX +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOCLATCH +// +//***************************************************************************** +// Field: [0] EN +// +// Controls latches between MCU IOC and AON_IOC. +// +// The latches are transparent by default. +// +// They must be closed prior to power off the domain(s) controlling the IOs in +// order to preserve IO values on external pins. +// ENUMs: +// TRANSP Latches are transparent, meaning the value of the +// IO is directly controlled by the GPIO or +// peripheral value +// STATIC Latches are static, meaning the current value on +// the IO pin is frozen by latches and kept even +// if GPIO module or a peripheral module is turned +// off +#define AON_IOC_IOCLATCH_EN 0x00000001 +#define AON_IOC_IOCLATCH_EN_BITN 0 +#define AON_IOC_IOCLATCH_EN_M 0x00000001 +#define AON_IOC_IOCLATCH_EN_S 0 +#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001 +#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000 + +//***************************************************************************** +// +// Register: AON_IOC_O_CLK32KCTL +// +//***************************************************************************** +// Field: [0] OE_N +// +// 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (e.g. +// IOC:IOCFG0.PORT_ID) set to AON_CLK32K. +// 1: Output enable not active +#define AON_IOC_CLK32KCTL_OE_N 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_BITN 0 +#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_S 0 + + +#endif // __AON_IOC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_rtc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_rtc.h new file mode 100644 index 0000000..521504d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_rtc.h @@ -0,0 +1,508 @@ +/****************************************************************************** +* Filename: hw_aon_rtc_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_RTC_H__ +#define __HW_AON_RTC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_RTC component +// +//***************************************************************************** +// Control +#define AON_RTC_O_CTL 0x00000000 + +// Event Flags, RTC Status +#define AON_RTC_O_EVFLAGS 0x00000004 + +// Second Counter Value, Integer Part +#define AON_RTC_O_SEC 0x00000008 + +// Second Counter Value, Fractional Part +#define AON_RTC_O_SUBSEC 0x0000000C + +// Subseconds Increment +#define AON_RTC_O_SUBSECINC 0x00000010 + +// Channel Configuration +#define AON_RTC_O_CHCTL 0x00000014 + +// Channel 0 Compare Value +#define AON_RTC_O_CH0CMP 0x00000018 + +// Channel 1 Compare Value +#define AON_RTC_O_CH1CMP 0x0000001C + +// Channel 2 Compare Value +#define AON_RTC_O_CH2CMP 0x00000020 + +// Channel 2 Compare Value Auto-increment +#define AON_RTC_O_CH2CMPINC 0x00000024 + +// Channel 1 Capture Value +#define AON_RTC_O_CH1CAPT 0x00000028 + +// AON Synchronization +#define AON_RTC_O_SYNC 0x0000002C + +//***************************************************************************** +// +// Register: AON_RTC_O_CTL +// +//***************************************************************************** +// Field: [18:16] COMB_EV_MASK +// +// Eventmask selecting which delayed events that form the combined event. +// ENUMs: +// CH2 Use Channel 2 delayed event in combined event +// CH1 Use Channel 1 delayed event in combined event +// CH0 Use Channel 0 delayed event in combined event +// NONE No event is selected for combined event. +#define AON_RTC_CTL_COMB_EV_MASK_W 3 +#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 +#define AON_RTC_CTL_COMB_EV_MASK_S 16 +#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 +#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 +#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 +#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 + +// Field: [11:8] EV_DELAY +// +// Number of SCLK_LF clock cycles waited before generating delayed events. +// (Common setting for all RTC cannels) the delayed event is delayed +// ENUMs: +// D144 Delay by 144 clock cycles +// D128 Delay by 128 clock cycles +// D112 Delay by 112 clock cycles +// D96 Delay by 96 clock cycles +// D80 Delay by 80 clock cycles +// D64 Delay by 64 clock cycles +// D48 Delay by 48 clock cycles +// D32 Delay by 32 clock cycles +// D16 Delay by 16 clock cycles +// D8 Delay by 8 clock cycles +// D4 Delay by 4 clock cycles +// D2 Delay by 2 clock cycles +// D1 Delay by 1 clock cycles +// D0 No delay on delayed event +#define AON_RTC_CTL_EV_DELAY_W 4 +#define AON_RTC_CTL_EV_DELAY_M 0x00000F00 +#define AON_RTC_CTL_EV_DELAY_S 8 +#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 +#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 +#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 +#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 +#define AON_RTC_CTL_EV_DELAY_D80 0x00000900 +#define AON_RTC_CTL_EV_DELAY_D64 0x00000800 +#define AON_RTC_CTL_EV_DELAY_D48 0x00000700 +#define AON_RTC_CTL_EV_DELAY_D32 0x00000600 +#define AON_RTC_CTL_EV_DELAY_D16 0x00000500 +#define AON_RTC_CTL_EV_DELAY_D8 0x00000400 +#define AON_RTC_CTL_EV_DELAY_D4 0x00000300 +#define AON_RTC_CTL_EV_DELAY_D2 0x00000200 +#define AON_RTC_CTL_EV_DELAY_D1 0x00000100 +#define AON_RTC_CTL_EV_DELAY_D0 0x00000000 + +// Field: [7] RESET +// +// RTC Counter reset. +// +// Writing 1 to this bit will reset the RTC counter. +// +// This bit is cleared when reset takes effect +#define AON_RTC_CTL_RESET 0x00000080 +#define AON_RTC_CTL_RESET_BITN 7 +#define AON_RTC_CTL_RESET_M 0x00000080 +#define AON_RTC_CTL_RESET_S 7 + +// Field: [2] RTC_4KHZ_EN +// +// RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 +// which is used by AUX timer. +// +// 0: RTC_4KHZ signal is forced to 0 +// 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) +#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 +#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_S 2 + +// Field: [1] RTC_UPD_EN +// +// RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is +// SCLK_LF divided by 2 +// +// 0: RTC_UPD signal is forced to 0 +// 1: RTC_UPD signal is toggling @16 kHz +#define AON_RTC_CTL_RTC_UPD_EN 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_BITN 1 +#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_S 1 + +// Field: [0] EN +// +// Enable RTC counter +// +// 0: Halted (frozen) +// 1: Running +#define AON_RTC_CTL_EN 0x00000001 +#define AON_RTC_CTL_EN_BITN 0 +#define AON_RTC_CTL_EN_M 0x00000001 +#define AON_RTC_CTL_EN_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_EVFLAGS +// +//***************************************************************************** +// Field: [16] CH2 +// +// Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or +// passes the CH2CMP value. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH2CMP provided that the channel is enabled and the new value matches any +// time between next RTC value and 1 second in the past +// +// Writing 1 clears this flag. Note that a new event can not occur on this +// channel in first 2 SCLK_LF cycles after a clearance. +// +// AUX_SCE can read the flag through AUX_WUC:WUEVFLAGS.AON_RTC_CH2 and clear it +// using AUX_WUC:WUEVCLR.AON_RTC_CH2. +#define AON_RTC_EVFLAGS_CH2 0x00010000 +#define AON_RTC_EVFLAGS_CH2_BITN 16 +#define AON_RTC_EVFLAGS_CH2_M 0x00010000 +#define AON_RTC_EVFLAGS_CH2_S 16 + +// Field: [8] CH1 +// +// Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following: +// - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP +// value. +// - CHCTL.CH1_CAPT_EN = 1 and capture occurs. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH1CMP provided that the channel is enabled, in compare mode and the new +// value matches any time between next RTC value and 1 second in the past. +// +// Writing 1 clears this flag. Note that a new event can not occur on this +// channel in first 2 SCLK_LF cycles after a clearance. +#define AON_RTC_EVFLAGS_CH1 0x00000100 +#define AON_RTC_EVFLAGS_CH1_BITN 8 +#define AON_RTC_EVFLAGS_CH1_M 0x00000100 +#define AON_RTC_EVFLAGS_CH1_S 8 + +// Field: [0] CH0 +// +// Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or +// passes the CH0CMP value. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH0CMP provided that the channels is enabled and the new value matches any +// time between next RTC value and 1 second in the past. +// +// Writing 1 clears this flag. Note that a new event can not occur on this +// channel in first 2 SCLK_LF cycles after a clearance. +#define AON_RTC_EVFLAGS_CH0 0x00000001 +#define AON_RTC_EVFLAGS_CH0_BITN 0 +#define AON_RTC_EVFLAGS_CH0_M 0x00000001 +#define AON_RTC_EVFLAGS_CH0_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SEC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// Unsigned integer representing Real Time Clock in seconds. +// +// When reading this register the content of SUBSEC.VALUE is simultaneously +// latched. A consistent reading of the combined Real Time Clock can be +// obtained by first reading this register, then reading SUBSEC register. +#define AON_RTC_SEC_VALUE_W 32 +#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SEC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SUBSEC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// Unsigned integer representing Real Time Clock in fractions of a second +// (VALUE/2^32 seconds) at the time when SEC register was read. +// +// Examples : +// - 0x0000_0000 = 0.0 sec +// - 0x4000_0000 = 0.25 sec +// - 0x8000_0000 = 0.5 sec +// - 0xC000_0000 = 0.75 sec +#define AON_RTC_SUBSEC_VALUE_W 32 +#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SUBSEC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SUBSECINC +// +//***************************************************************************** +// Field: [23:0] VALUEINC +// +// This value compensates for a SCLK_LF clock which has an offset from 32768 +// Hz. +// +// The compensation value can be found as 2^38 / freq, where freq is SCLK_LF +// clock frequency in Hertz +// +// This value is added to SUBSEC.VALUE on every cycle, and carry of this is +// added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with +// SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a +// hidden 6-bit register that generates a carry into the above mentioned +// addition on overflow. +// The default value corresponds to incrementing by precisely 1/32768 of a +// second. +// +// NOTE: This register is read only. Modification of the register value must be +// done using registers AUX_WUC:RTCSUBSECINC1 , AUX_WUC:RTCSUBSECINC0 and +// AUX_WUC:RTCSUBSECINCCTL +#define AON_RTC_SUBSECINC_VALUEINC_W 24 +#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF +#define AON_RTC_SUBSECINC_VALUEINC_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CHCTL +// +//***************************************************************************** +// Field: [18] CH2_CONT_EN +// +// Set to enable continuous operation of Channel 2 +#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 +#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_S 18 + +// Field: [16] CH2_EN +// +// RTC Channel 2 Enable +// +// 0: Disable RTC Channel 2 +// 1: Enable RTC Channel 2 +#define AON_RTC_CHCTL_CH2_EN 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_BITN 16 +#define AON_RTC_CHCTL_CH2_EN_M 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_S 16 + +// Field: [9] CH1_CAPT_EN +// +// Set Channel 1 mode +// +// 0: Compare mode (default) +// 1: Capture mode +#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 +#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 + +// Field: [8] CH1_EN +// +// RTC Channel 1 Enable +// +// 0: Disable RTC Channel 1 +// 1: Enable RTC Channel 1 +#define AON_RTC_CHCTL_CH1_EN 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_BITN 8 +#define AON_RTC_CHCTL_CH1_EN_M 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_S 8 + +// Field: [0] CH0_EN +// +// RTC Channel 0 Enable +// +// 0: Disable RTC Channel 0 +// 1: Enable RTC Channel 0 +#define AON_RTC_CHCTL_CH0_EN 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_BITN 0 +#define AON_RTC_CHCTL_CH0_EN_M 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH0CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 0 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to 2 SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH0CMP_VALUE_W 32 +#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH0CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH1CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 1 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to 2 SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH1CMP_VALUE_W 32 +#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH1CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH2CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 2 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to 2 SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH2CMP_VALUE_W 32 +#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH2CMPINC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every +// channel 2 compare event. +#define AON_RTC_CH2CMPINC_VALUE_W 32 +#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMPINC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH1CAPT +// +//***************************************************************************** +// Field: [31:16] SEC +// +// Value of SEC.VALUE bits 15:0 at capture time. +#define AON_RTC_CH1CAPT_SEC_W 16 +#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 +#define AON_RTC_CH1CAPT_SEC_S 16 + +// Field: [15:0] SUBSEC +// +// Value of SUBSEC.VALUE bits 31:16 at capture time. +#define AON_RTC_CH1CAPT_SUBSEC_W 16 +#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF +#define AON_RTC_CH1CAPT_SUBSEC_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SYNC +// +//***************************************************************************** +// Field: [0] WBUSY +// +// This register will always return 0,- however it will not return the value +// until there are no outstanding write requests between MCU and AON +// +// Note: Writing to this register prior to reading will force a wait until next +// SCLK_LF edge. This is recommended for syncing read registers from AON when +// waking up from sleep +// Failure to do so may result in reading AON values from prior to going to +// sleep +#define AON_RTC_SYNC_WBUSY 0x00000001 +#define AON_RTC_SYNC_WBUSY_BITN 0 +#define AON_RTC_SYNC_WBUSY_M 0x00000001 +#define AON_RTC_SYNC_WBUSY_S 0 + + +#endif // __AON_RTC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_sysctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_sysctl.h new file mode 100644 index 0000000..c8352c1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_sysctl.h @@ -0,0 +1,348 @@ +/****************************************************************************** +* Filename: hw_aon_sysctl_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_SYSCTL_H__ +#define __HW_AON_SYSCTL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_SYSCTL component +// +//***************************************************************************** +// Power Management +#define AON_SYSCTL_O_PWRCTL 0x00000000 + +// Reset Management +#define AON_SYSCTL_O_RESETCTL 0x00000004 + +// Sleep Mode +#define AON_SYSCTL_O_SLEEPCTL 0x00000008 + +//***************************************************************************** +// +// Register: AON_SYSCTL_O_PWRCTL +// +//***************************************************************************** +// Field: [2] DCDC_ACTIVE +// +// Select to use DCDC regulator for VDDR in active mode +// +// 0: Use GLDO for regulation of VDDRin active mode. +// 1: Use DCDC for regulation of VDDRin active mode. +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE 0x00000004 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN 2 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_S 2 + +// Field: [1] EXT_REG_MODE +// +// Status of source for VDDRsupply: +// +// 0: DCDC/GLDO are generating VDDR +// 1: DCDC/GLDO are bypassed, external regulator supplies VDDR +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE 0x00000002 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_BITN 1 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_S 1 + +// Field: [0] DCDC_EN +// +// Select to use DCDC regulator during recharge of VDDR +// +// 0: Use GLDO for recharge of VDDR +// 1: Use DCDC for recharge of VDDR +// +// Note: This bitfield should be set to the same as DCDC_ACTIVE +#define AON_SYSCTL_PWRCTL_DCDC_EN 0x00000001 +#define AON_SYSCTL_PWRCTL_DCDC_EN_BITN 0 +#define AON_SYSCTL_PWRCTL_DCDC_EN_M 0x00000001 +#define AON_SYSCTL_PWRCTL_DCDC_EN_S 0 + +//***************************************************************************** +// +// Register: AON_SYSCTL_O_RESETCTL +// +//***************************************************************************** +// Field: [31] SYSRESET +// +// Cold reset register. Writing 1 to this bitfield will reset the entire chip +// and cause boot code to run again. +// +// 0: No effect +// 1: Generate system reset. Appears as SYSRESET in RESET_SRC. +#define AON_SYSCTL_RESETCTL_SYSRESET 0x80000000 +#define AON_SYSCTL_RESETCTL_SYSRESET_BITN 31 +#define AON_SYSCTL_RESETCTL_SYSRESET_M 0x80000000 +#define AON_SYSCTL_RESETCTL_SYSRESET_S 31 + +// Field: [25] BOOT_DET_1_CLR +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_S 25 + +// Field: [24] BOOT_DET_0_CLR +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_S 24 + +// Field: [17] BOOT_DET_1_SET +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_S 17 + +// Field: [16] BOOT_DET_0_SET +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_S 16 + +// Field: [15] WU_FROM_SD +// +// A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from +// SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin +// being forced low) +// +// Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup +// sources. +// +// 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC +// 1: A wakeup has occurred from SHUTDOWN +// +// Note: This flag can not be cleared and will therefor remain valid untill +// poweroff/reset +#define AON_SYSCTL_RESETCTL_WU_FROM_SD 0x00008000 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_BITN 15 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_M 0x00008000 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_S 15 + +// Field: [14] GPIO_WU_FROM_SD +// +// A wakeup from SHUTDOWN on an IO event has occurred +// +// Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup +// sources. +// +// 0: The wakeup did not occur from SHUTDOWN on an IO event +// 1: A wakeup from SHUTDOWN occurred from an IO event +// +// The case where WU_FROM_SD is asserted but this bitfield is not asserted will +// only occur in a debug session. The boot code will not proceed with wakeup +// from SHUTDOWN procedure until this bitfield is asserted as well. +// +// Note: This flag can not be cleared and will therefor remain valid untill +// poweroff/reset +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 + +// Field: [13] BOOT_DET_1 +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_1 0x00002000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_BITN 13 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_M 0x00002000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_S 13 + +// Field: [12] BOOT_DET_0 +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_0 0x00001000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_BITN 12 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_M 0x00001000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_S 12 + +// Field: [11] VDDS_LOSS_EN_OVR +// +// Override of VDDS_LOSS_EN +// +// 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN=1 +// 1: Brown out detect of VDDS generates system reset (regardless of +// VDDS_LOSS_EN) +// +// This bit can be locked +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR 0x00000800 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_BITN 11 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_M 0x00000800 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_S 11 + +// Field: [10] VDDR_LOSS_EN_OVR +// +// Override of VDDR_LOSS_EN +// +// 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN=1 +// 1: Brown out detect of VDDR generates system reset (regardless of +// VDDR_LOSS_EN) +// +// This bit can be locked +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR 0x00000400 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_BITN 10 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_M 0x00000400 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_S 10 + +// Field: [9] VDD_LOSS_EN_OVR +// +// Override of VDD_LOSS_EN +// +// 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN=1 +// 1: Brown out detect of VDD generates system reset (regardless of +// VDD_LOSS_EN) +// +// This bit can be locked +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR 0x00000200 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_BITN 9 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_M 0x00000200 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_S 9 + +// Field: [7] VDDS_LOSS_EN +// +// Controls reset generation in case VDDS is lost +// +// 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 +// 1: Brown out detect of VDDS generates system reset +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN 0x00000080 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_BITN 7 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000080 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_S 7 + +// Field: [6] VDDR_LOSS_EN +// +// Controls reset generation in case VDDR is lost +// +// 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 +// 1: Brown out detect of VDDR generates system reset +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN 0x00000040 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN 6 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000040 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_S 6 + +// Field: [5] VDD_LOSS_EN +// +// Controls reset generation in case VDD is lost +// +// 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 +// 1: Brown out detect of VDD generates system reset +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN 0x00000020 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_BITN 5 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_M 0x00000020 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_S 5 + +// Field: [4] CLK_LOSS_EN +// +// Controls reset generation in case SCLK_LF is lost. (provided that clock +// loss detection is enabled by DDI_0_OSC:CTL0.CLK_LOSS_EN) +// +// Note: Clock loss reset generation must be disabled before SCLK_LF clock +// source is changed in DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL and remain disabled +// untill the change is confirmed in DDI_0_OSC:STAT0.SCLK_LF_SRC. Failure to do +// so may result in a spurious system reset. Clock loss reset generation can be +// disabled through this bitfield or by clearing DDI_0_OSC:CTL0.CLK_LOSS_EN +// +// 0: Clock loss is ignored +// 1: Clock loss generates system reset +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN 0x00000010 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN 4 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_M 0x00000010 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_S 4 + +// Field: [3:1] RESET_SRC +// +// Shows the source of the last system reset: +// Occurrence of one of the reset sources may trigger several other reset +// sources as essential parts of the system are undergoing reset. This field +// will report the root cause of the reset (not the other resets that are +// consequence of the system reset). +// To support this feature the actual register is not captured before the reset +// source being released. If a new reset source is triggered, in a window of +// four 32 kHz periods after the previous has been released, this register +// may indicate Power on reset as source. +// ENUMs: +// WARMRESET Software reset via PRCM warm reset request +// SYSRESET Software reset via SYSRESET register +// CLK_LOSS Clock loss detect +// VDDR_LOSS Brown out detect on VDDR +// VDD_LOSS Brown out detect on VDD +// VDDS_LOSS Brown out detect on VDDS +// PIN_RESET Reset pin +// PWR_ON Power on reset +#define AON_SYSCTL_RESETCTL_RESET_SRC_W 3 +#define AON_SYSCTL_RESETCTL_RESET_SRC_M 0x0000000E +#define AON_SYSCTL_RESETCTL_RESET_SRC_S 1 +#define AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E +#define AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C +#define AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDD_LOSS 0x00000006 +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 +#define AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 +#define AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 + +//***************************************************************************** +// +// Register: AON_SYSCTL_O_SLEEPCTL +// +//***************************************************************************** +// Field: [0] IO_PAD_SLEEP_DIS +// +// Controls the I/O pad sleep mode. The boot code will set this bitfield +// automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is set +// ). +// +// 0: I/O pad sleep mode is enabled, ie all pads are latched and can not +// toggle. +// 1: I/O pad sleep mode is disabled +// +// Application software may want to reconfigure the state for all IO's before +// setting this bitfield upon waking up from a SHUTDOWN. +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 + + +#endif // __AON_SYSCTL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_wuc.h new file mode 100644 index 0000000..9642cae --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_wuc.h @@ -0,0 +1,674 @@ +/****************************************************************************** +* Filename: hw_aon_wuc_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_WUC_H__ +#define __HW_AON_WUC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_WUC component +// +//***************************************************************************** +// MCU Clock Management +#define AON_WUC_O_MCUCLK 0x00000000 + +// AUX Clock Management +#define AON_WUC_O_AUXCLK 0x00000004 + +// MCU Configuration +#define AON_WUC_O_MCUCFG 0x00000008 + +// AUX Configuration +#define AON_WUC_O_AUXCFG 0x0000000C + +// AUX Control +#define AON_WUC_O_AUXCTL 0x00000010 + +// Power Status +#define AON_WUC_O_PWRSTAT 0x00000014 + +// Shutdown Control +#define AON_WUC_O_SHUTDOWN 0x00000018 + +// Control 0 +#define AON_WUC_O_CTL0 0x00000020 + +// Control 1 +#define AON_WUC_O_CTL1 0x00000024 + +// Recharge Controller Configuration +#define AON_WUC_O_RECHARGECFG 0x00000030 + +// Recharge Controller Status +#define AON_WUC_O_RECHARGESTAT 0x00000034 + +// Oscillator Configuration +#define AON_WUC_O_OSCCFG 0x00000038 + +// JTAG Configuration +#define AON_WUC_O_JTAGCFG 0x00000040 + +// JTAG USERCODE +#define AON_WUC_O_JTAGUSERCODE 0x00000044 + +//***************************************************************************** +// +// Register: AON_WUC_O_MCUCLK +// +//***************************************************************************** +// Field: [2] RCOSC_HF_CAL_DONE +// +// MCU bootcode will set this bit when RCOSC_HF is calibrated. The FLASH can +// not be used until this bit is set. +// +// 1: RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up. +// 0: RCOSC_HF is not yet calibrated, ie FLASH must not assume that the SCLK_HF +// is safe +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE 0x00000004 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_BITN 2 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_M 0x00000004 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_S 2 + +// Field: [1:0] PWR_DWN_SRC +// +// Controls the clock source for the entire MCU domain while MCU is requesting +// powerdown. +// +// When MCU requests powerdown with SCLK_HF as source, then WUC will switch +// over to this clock source during powerdown, and automatically switch back to +// SCLK_HF when MCU is no longer requesting powerdown and system is back in +// active mode. +// ENUMs: +// SCLK_LF Use SCLK_LF in Powerdown +// NONE No clock in Powerdown +#define AON_WUC_MCUCLK_PWR_DWN_SRC_W 2 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_M 0x00000003 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_S 0 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_SCLK_LF 0x00000001 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AON_WUC_O_AUXCLK +// +//***************************************************************************** +// Field: [12:11] PWR_DWN_SRC +// +// When AUX requests powerdown with SCLK_HF as source, then WUC will switch +// over to this clock source during powerdown, and automatically switch back to +// SCLK_HF when AUX system is back in active mode +// ENUMs: +// SCLK_LF Use SCLK_LF in Powerdown +// NONE No clock in Powerdown +#define AON_WUC_AUXCLK_PWR_DWN_SRC_W 2 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_M 0x00001800 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_S 11 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_SCLK_LF 0x00000800 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_NONE 0x00000000 + +// Field: [10:8] SCLK_HF_DIV +// +// Select the AUX clock divider for SCLK_HF +// +// NB: It is not supported to change the AUX clock divider while SCLK_HF is +// active source for AUX +// ENUMs: +// DIV256 Divide by 256 +// DIV128 Divide by 128 +// DIV64 Divide by 64 +// DIV32 Divide by 32 +// DIV16 Divide by 16 +// DIV8 Divide by 8 +// DIV4 Divide by 4 +// DIV2 Divide by 2 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_W 3 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_M 0x00000700 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_S 8 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 0x00000700 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 0x00000600 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 0x00000500 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 0x00000400 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 0x00000300 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 0x00000200 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 0x00000100 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 0x00000000 + +// Field: [2:0] SRC +// +// Selects the clock source for AUX: +// +// NB: Switching the clock source is guaranteed to be glitchless +// ENUMs: +// SCLK_LF LF Clock (SCLK_LF) +// SCLK_HF HF Clock (SCLK_HF) +#define AON_WUC_AUXCLK_SRC_W 3 +#define AON_WUC_AUXCLK_SRC_M 0x00000007 +#define AON_WUC_AUXCLK_SRC_S 0 +#define AON_WUC_AUXCLK_SRC_SCLK_LF 0x00000004 +#define AON_WUC_AUXCLK_SRC_SCLK_HF 0x00000001 + +//***************************************************************************** +// +// Register: AON_WUC_O_MCUCFG +// +//***************************************************************************** +// Field: [17] VIRT_OFF +// +// Internal. Only to be used through TI provided API. +#define AON_WUC_MCUCFG_VIRT_OFF 0x00020000 +#define AON_WUC_MCUCFG_VIRT_OFF_BITN 17 +#define AON_WUC_MCUCFG_VIRT_OFF_M 0x00020000 +#define AON_WUC_MCUCFG_VIRT_OFF_S 17 + +// Field: [16] FIXED_WU_EN +// +// Internal. Only to be used through TI provided API. +#define AON_WUC_MCUCFG_FIXED_WU_EN 0x00010000 +#define AON_WUC_MCUCFG_FIXED_WU_EN_BITN 16 +#define AON_WUC_MCUCFG_FIXED_WU_EN_M 0x00010000 +#define AON_WUC_MCUCFG_FIXED_WU_EN_S 16 + +// Field: [3:0] SRAM_RET_EN +// +// MCU SRAM is partitioned into 4 banks . This register controls which of the +// banks that has retention during MCU power off +// ENUMs: +// RET_FULL Retention on for all banks (SRAM:BANK0, SRAM:BANK1 +// ,SRAM:BANK2 and SRAM:BANK3) +// RET_LEVEL3 Retention on for SRAM:BANK0, SRAM:BANK1 and +// SRAM:BANK2 +// RET_LEVEL2 Retention on for SRAM:BANK0 and SRAM:BANK1 +// RET_LEVEL1 Retention on for SRAM:BANK0 +// RET_NONE Retention is disabled +#define AON_WUC_MCUCFG_SRAM_RET_EN_W 4 +#define AON_WUC_MCUCFG_SRAM_RET_EN_M 0x0000000F +#define AON_WUC_MCUCFG_SRAM_RET_EN_S 0 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_FULL 0x0000000F +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL3 0x00000007 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL2 0x00000003 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL1 0x00000001 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AON_WUC_O_AUXCFG +// +//***************************************************************************** +// Field: [0] RAM_RET_EN +// +// This bit controls retention mode for the AUX_RAM:BANK0: +// +// 0: Retention is disabled +// 1: Retention is enabled +// +// NB: If retention is disabled, the AUX_RAM will be powered off when it would +// otherwise be put in retention mode +#define AON_WUC_AUXCFG_RAM_RET_EN 0x00000001 +#define AON_WUC_AUXCFG_RAM_RET_EN_BITN 0 +#define AON_WUC_AUXCFG_RAM_RET_EN_M 0x00000001 +#define AON_WUC_AUXCFG_RAM_RET_EN_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_AUXCTL +// +//***************************************************************************** +// Field: [31] RESET_REQ +// +// Reset request for AUX. Writing 1 to this register will assert reset to AUX. +// The reset will be held until the bit is cleared again. +// +// 0: AUX reset pin will be deasserted +// 1: AUX reset pin will be asserted +#define AON_WUC_AUXCTL_RESET_REQ 0x80000000 +#define AON_WUC_AUXCTL_RESET_REQ_BITN 31 +#define AON_WUC_AUXCTL_RESET_REQ_M 0x80000000 +#define AON_WUC_AUXCTL_RESET_REQ_S 31 + +// Field: [2] SCE_RUN_EN +// +// Enables (1) or disables (0) AUX_SCE execution. AUX_SCE execution will begin +// when AUX Domain is powered and either this or AUX_SCE:CTL.CLK_EN is set. +// +// Setting this bit will assure that AUX_SCE execution starts as soon as AUX +// power domain is woken up. ( AUX_SCE:CTL.CLK_EN will be reset to 0 if AUX +// power domain has been off) +// +// 0: AUX_SCE execution will be disabled if AUX_SCE:CTL.CLK_EN is 0 +// 1: AUX_SCE execution is enabled. +#define AON_WUC_AUXCTL_SCE_RUN_EN 0x00000004 +#define AON_WUC_AUXCTL_SCE_RUN_EN_BITN 2 +#define AON_WUC_AUXCTL_SCE_RUN_EN_M 0x00000004 +#define AON_WUC_AUXCTL_SCE_RUN_EN_S 2 + +// Field: [1] SWEV +// +// Writing 1 sets the software event to the AUX domain, which can be read +// through AUX_WUC:WUEVFLAGS.AON_SW. +// +// This event is normally cleared by AUX_SCE through the +// AUX_WUC:WUEVCLR.AON_SW. It can also be cleared by writing 0 to this +// register. +// +// Reading 0 means that there is no outstanding software event for AUX. +// +// Note that it can take up to 1,5 SCLK_LF clock cycles to clear the event from +// AUX. +#define AON_WUC_AUXCTL_SWEV 0x00000002 +#define AON_WUC_AUXCTL_SWEV_BITN 1 +#define AON_WUC_AUXCTL_SWEV_M 0x00000002 +#define AON_WUC_AUXCTL_SWEV_S 1 + +// Field: [0] AUX_FORCE_ON +// +// Forces the AUX domain into active mode, overriding the requests from +// AUX_WUC:PWROFFREQ, AUX_WUC:PWRDWNREQ and AUX_WUC:MCUBUSCTL. +// Note that an ongoing AUX_WUC:PWROFFREQ will complete before this bit will +// set the AUX domain into active mode. +// +// MCU must set this bit in order to access the AUX peripherals. +// The AUX domain status can be read from PWRSTAT.AUX_PD_ON +// +// 0: AUX is allowed to Power Off, Power Down or Disconnect. +// 1: AUX Power OFF, Power Down or Disconnect requests will be overruled +#define AON_WUC_AUXCTL_AUX_FORCE_ON 0x00000001 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_BITN 0 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_M 0x00000001 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_PWRSTAT +// +//***************************************************************************** +// Field: [9] AUX_PWR_DWN +// +// Indicates the AUX powerdown state when AUX domain is powered up. +// +// 0: Active mode +// 1: AUX Powerdown request has been granted +#define AON_WUC_PWRSTAT_AUX_PWR_DWN 0x00000200 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_BITN 9 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_M 0x00000200 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_S 9 + +// Field: [6] JTAG_PD_ON +// +// Indicates JTAG power state: +// +// 0: JTAG is powered off +// 1: JTAG is powered on +#define AON_WUC_PWRSTAT_JTAG_PD_ON 0x00000040 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_BITN 6 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_M 0x00000040 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_S 6 + +// Field: [5] AUX_PD_ON +// +// Indicates AUX power state: +// +// 0: AUX is not ready for use ( may be powered off or in power state +// transition ) +// 1: AUX is powered on, connected to bus and ready for use, +#define AON_WUC_PWRSTAT_AUX_PD_ON 0x00000020 +#define AON_WUC_PWRSTAT_AUX_PD_ON_BITN 5 +#define AON_WUC_PWRSTAT_AUX_PD_ON_M 0x00000020 +#define AON_WUC_PWRSTAT_AUX_PD_ON_S 5 + +// Field: [4] MCU_PD_ON +// +// Indicates MCU power state: +// +// 0: MCU Power sequencing is not yet finalized and MCU_AONIF registers may not +// be reliable +// 1: MCU Power sequencing is finalized and all MCU_AONIF registers are +// reliable +#define AON_WUC_PWRSTAT_MCU_PD_ON 0x00000010 +#define AON_WUC_PWRSTAT_MCU_PD_ON_BITN 4 +#define AON_WUC_PWRSTAT_MCU_PD_ON_M 0x00000010 +#define AON_WUC_PWRSTAT_MCU_PD_ON_S 4 + +// Field: [2] AUX_BUS_CONNECTED +// +// Indicates that AUX Bus is connected: +// +// 0: AUX bus is not connected +// 1: AUX bus is connected ( idle_ack = 0 ) +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED 0x00000004 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_BITN 2 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_M 0x00000004 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_S 2 + +// Field: [1] AUX_RESET_DONE +// +// Indicates Reset Done from AUX: +// +// 0: AUX is being reset +// 1: AUX reset is released +#define AON_WUC_PWRSTAT_AUX_RESET_DONE 0x00000002 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_BITN 1 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_M 0x00000002 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_S 1 + +//***************************************************************************** +// +// Register: AON_WUC_O_SHUTDOWN +// +//***************************************************************************** +// Field: [0] EN +// +// Writing a 1 to this bit forces a shutdown request to be registered and all +// I/O values to be latched - in the PAD ring, possibly enabling I/O wakeup. +// Writing 0 will cancel a registered shutdown request and open th I/O latches +// residing in the PAD ring. +// +// A registered shutdown request takes effect the next time power down +// conditions exists. At this time, the will not enter Powerdown mode, but +// instead it will turn off all internal powersupplies, effectively putting the +// device into Shutdown mode. +#define AON_WUC_SHUTDOWN_EN 0x00000001 +#define AON_WUC_SHUTDOWN_EN_BITN 0 +#define AON_WUC_SHUTDOWN_EN_M 0x00000001 +#define AON_WUC_SHUTDOWN_EN_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_CTL0 +// +//***************************************************************************** +// Field: [8] PWR_DWN_DIS +// +// Controls whether MCU and AUX requesting to be powered off will enable a +// transition to powerdown: +// +// 0: Enabled +// 1: Disabled +#define AON_WUC_CTL0_PWR_DWN_DIS 0x00000100 +#define AON_WUC_CTL0_PWR_DWN_DIS_BITN 8 +#define AON_WUC_CTL0_PWR_DWN_DIS_M 0x00000100 +#define AON_WUC_CTL0_PWR_DWN_DIS_S 8 + +// Field: [3] AUX_SRAM_ERASE +// +// Internal. Only to be used through TI provided API. +#define AON_WUC_CTL0_AUX_SRAM_ERASE 0x00000008 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_BITN 3 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_M 0x00000008 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_S 3 + +// Field: [2] MCU_SRAM_ERASE +// +// Internal. Only to be used through TI provided API. +#define AON_WUC_CTL0_MCU_SRAM_ERASE 0x00000004 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_BITN 2 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_M 0x00000004 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_S 2 + +//***************************************************************************** +// +// Register: AON_WUC_O_CTL1 +// +//***************************************************************************** +// Field: [1] MCU_RESET_SRC +// +// Indicates source of last MCU Voltage Domain warm reset request: +// +// 0: MCU SW reset +// 1: JTAG reset +// +// This bit can only be cleared by writing a 1 to it +#define AON_WUC_CTL1_MCU_RESET_SRC 0x00000002 +#define AON_WUC_CTL1_MCU_RESET_SRC_BITN 1 +#define AON_WUC_CTL1_MCU_RESET_SRC_M 0x00000002 +#define AON_WUC_CTL1_MCU_RESET_SRC_S 1 + +// Field: [0] MCU_WARM_RESET +// +// Indicates type of last MCU Voltage Domain reset: +// +// 0: Last MCU reset was not a warm reset +// 1: Last MCU reset was a warm reset (requested from MCU or JTAG as indicated +// in MCU_RESET_SRC) +// +// This bit can only be cleared by writing a 1 to it +#define AON_WUC_CTL1_MCU_WARM_RESET 0x00000001 +#define AON_WUC_CTL1_MCU_WARM_RESET_BITN 0 +#define AON_WUC_CTL1_MCU_WARM_RESET_M 0x00000001 +#define AON_WUC_CTL1_MCU_WARM_RESET_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_RECHARGECFG +// +//***************************************************************************** +// Field: [31] ADAPTIVE_EN +// +// Enable adaptive recharge +// +// Note: Recharge can be turned completely of by setting MAX_PER_E=7 and +// MAX_PER_M=31 and this bitfield to 0 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN 0x80000000 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_BITN 31 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_M 0x80000000 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_S 31 + +// Field: [23:20] C2 +// +// Gain factor for adaptive recharge algorithm +// +// period_new=period * ( 1+/-(2^-C1+2^-C2) ) +// Valid values for C2 is 2 to 10 +// +// Note: Rounding may cause adaptive recharge not to start for very small +// values of both Gain and Initial period. Criteria for algorithm to start is +// MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 +#define AON_WUC_RECHARGECFG_C2_W 4 +#define AON_WUC_RECHARGECFG_C2_M 0x00F00000 +#define AON_WUC_RECHARGECFG_C2_S 20 + +// Field: [19:16] C1 +// +// Gain factor for adaptive recharge algorithm +// +// period_new=period * ( 1+/-(2^-C1+2^-C2) ) +// Valid values for C1 is 1 to 10 +// +// Note: Rounding may cause adaptive recharge not to start for very small +// values of both Gain and Initial period. Criteria for algorithm to start is +// MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 +#define AON_WUC_RECHARGECFG_C1_W 4 +#define AON_WUC_RECHARGECFG_C1_M 0x000F0000 +#define AON_WUC_RECHARGECFG_C1_S 16 + +// Field: [15:11] MAX_PER_M +// +// This register defines the maximum period that the recharge algorithm can +// take, i.e. it defines the maximum number of cycles between 2 recharges. +// The maximum number of cycles is specified with a 5 bit mantissa and 3 bit +// exponent: +// MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E +// This field sets the mantissa of MAXCYCLES +#define AON_WUC_RECHARGECFG_MAX_PER_M_W 5 +#define AON_WUC_RECHARGECFG_MAX_PER_M_M 0x0000F800 +#define AON_WUC_RECHARGECFG_MAX_PER_M_S 11 + +// Field: [10:8] MAX_PER_E +// +// This register defines the maximum period that the recharge algorithm can +// take, i.e. it defines the maximum number of cycles between 2 recharges. +// The maximum number of cycles is specified with a 5 bit mantissa and 3 bit +// exponent: +// MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E +// This field sets the exponent MAXCYCLES +#define AON_WUC_RECHARGECFG_MAX_PER_E_W 3 +#define AON_WUC_RECHARGECFG_MAX_PER_E_M 0x00000700 +#define AON_WUC_RECHARGECFG_MAX_PER_E_S 8 + +// Field: [7:3] PER_M +// +// Number of 32 KHz clocks between activation of recharge controller +// For recharge algorithm, PERIOD is the initial period when entering powerdown +// mode. The adaptive recharge algorithm will not change this register +// PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 +// bit exponent: +// This field sets the Mantissa of the Period. +// PERIOD=(PER_M*16+15)*2^PER_E +#define AON_WUC_RECHARGECFG_PER_M_W 5 +#define AON_WUC_RECHARGECFG_PER_M_M 0x000000F8 +#define AON_WUC_RECHARGECFG_PER_M_S 3 + +// Field: [2:0] PER_E +// +// Number of 32 KHz clocks between activation of recharge controller +// For recharge algorithm, PERIOD is the initial period when entering powerdown +// mode. The adaptive recharge algorithm will not change this register +// PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 +// bit exponent: +// This field sets the Exponent of the Period. +// PERIOD=(PER_M*16+15)*2^PER_E +#define AON_WUC_RECHARGECFG_PER_E_W 3 +#define AON_WUC_RECHARGECFG_PER_E_M 0x00000007 +#define AON_WUC_RECHARGECFG_PER_E_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_RECHARGESTAT +// +//***************************************************************************** +// Field: [19:16] VDDR_SMPLS +// +// The last 4 VDDR samples, bit 0 being the newest. +// +// The register is being updated in every recharge period with a shift left, +// and bit 0 is updated with the last VDDR sample, ie a 1 is shiftet in in case +// VDDR > VDDR_threshold just before recharge starts. Otherwise a 0 will be +// shifted in. +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_W 4 +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_S 16 + +// Field: [15:0] MAX_USED_PER +// +// The maximum value of recharge period seen with VDDR>threshold. +// +// The VDDR voltage is compared against the threshold voltage at just before +// each recharge. If VDDR is above threshold, MAX_USED_PER is updated with max +// ( current recharge peride; MAX_USED_PER ) This way MAX_USED_PER can track +// the recharge period where VDDR is decharged to the threshold value. We can +// therefore use the value as an indication of the leakage current during +// recharge. +// +// This bitfield is cleared to 0 when writing this register. +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_W 16 +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_OSCCFG +// +//***************************************************************************** +// Field: [7:3] PER_M +// +// Number of 32 KHz clocks between oscillator amplitude calibrations. +// When this counter expires, an oscillator amplitude compensation is triggered +// immediately in Active mode. When this counter expires in Powerdown mode an +// internal flag is set such that the amplitude compensation is postponed until +// the next recharge occurs. +// +// The Period will effectively be a 16 bit value coded in a 5 bit mantissa and +// 3 bit exponent +// PERIOD=(PER_M*16+15)*2^PER_E +// This field sets the mantissa +// Note: Oscillator amplitude calibration is turned of when both this bitfield +// and PER_E are set to 0 +#define AON_WUC_OSCCFG_PER_M_W 5 +#define AON_WUC_OSCCFG_PER_M_M 0x000000F8 +#define AON_WUC_OSCCFG_PER_M_S 3 + +// Field: [2:0] PER_E +// +// Number of 32 KHz clocks between oscillator amplitude calibrations. +// When this counter expires, an oscillator amplitude compensation is triggered +// immediately in Active mode. When this counter expires in Powerdown mode an +// internal flag is set such that the amplitude compensation is postponed until +// the next recharge occurs. +// The Period will effectively be a 16 bit value coded in a 5 bit mantissa and +// 3 bit exponent +// PERIOD=(PER_M*16+15)*2^PER_E +// This field sets the exponent +// Note: Oscillator amplitude calibration is turned of when both PER_M and +// this bitfield are set to 0 +#define AON_WUC_OSCCFG_PER_E_W 3 +#define AON_WUC_OSCCFG_PER_E_M 0x00000007 +#define AON_WUC_OSCCFG_PER_E_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_JTAGCFG +// +//***************************************************************************** +// Field: [8] JTAG_PD_FORCE_ON +// +// Controls JTAG PowerDomain power state: +// +// 0: Controlled exclusively by debug subsystem. (JTAG Powerdomain will be +// powered off unless a debugger is attached) +// 1: JTAG Power Domain is forced on, independent of debug subsystem. +// +// NB: The reset value causes JTAG Power Domain to be powered on by default. +// Software must clear this bit to turn off the JTAG Power Domain +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_S 8 + +//***************************************************************************** +// +// Register: AON_WUC_O_JTAGUSERCODE +// +//***************************************************************************** +// Field: [31:0] USER_CODE +// +// 32-bit JTAG USERCODE register feeding main JTAG TAP +// NB: This field can be locked +#define AON_WUC_JTAGUSERCODE_USER_CODE_W 32 +#define AON_WUC_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF +#define AON_WUC_JTAGUSERCODE_USER_CODE_S 0 + + +#endif // __AON_WUC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_aiodio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_aiodio.h new file mode 100644 index 0000000..7d6b08f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_aiodio.h @@ -0,0 +1,481 @@ +/****************************************************************************** +* Filename: hw_aux_aiodio_h +* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) +* Revision: 49005 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_AIODIO_H__ +#define __HW_AUX_AIODIO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_AIODIO component +// +//***************************************************************************** +// General Purpose Input Output Data Out +#define AUX_AIODIO_O_GPIODOUT 0x00000000 + +// Input Output Mode +#define AUX_AIODIO_O_IOMODE 0x00000004 + +// General Purpose Input Output Data In +#define AUX_AIODIO_O_GPIODIN 0x00000008 + +// General Purpose Input Output Data Out Set +#define AUX_AIODIO_O_GPIODOUTSET 0x0000000C + +// General Purpose Input Output Data Out Clear +#define AUX_AIODIO_O_GPIODOUTCLR 0x00000010 + +// General Purpose Input Output Data Out Toggle +#define AUX_AIODIO_O_GPIODOUTTGL 0x00000014 + +// General Purpose Input Output Digital Input Enable +#define AUX_AIODIO_O_GPIODIE 0x00000018 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUT +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. +// Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. +#define AUX_AIODIO_GPIODOUT_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUT_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IOMODE +// +//***************************************************************************** +// Field: [15:14] IO7 +// +// Select mode for AUXIO[8i+7]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 7 is 0: +// AUXIO[8i+7] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 7 is 1: +// AUXIO[8i+7] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 7 is 0: +// AUXIO[8i+7] is driven low. +// +// When GPIODOUT bit 7 is 1: +// AUXIO[8i+7] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 7 is 0: +// AUXIO[8i+7] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 7 is 1: +// AUXIO[8i+7] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 7 drives +// AUXIO[8i+7]. +#define AUX_AIODIO_IOMODE_IO7_W 2 +#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_S 14 +#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 +#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 +#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 + +// Field: [13:12] IO6 +// +// Select mode for AUXIO[8i+6]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 6 is 0: +// AUXIO[8i+6] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 6 is 1: +// AUXIO[8i+6] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 6 is 0: +// AUXIO[8i+6] is driven low. +// +// When GPIODOUT bit 6 is 1: +// AUXIO[8i+6] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 6 is 0: +// AUXIO[8i+6] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 6 is 1: +// AUXIO[8i+6] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 6 drives +// AUXIO[8i+6]. +#define AUX_AIODIO_IOMODE_IO6_W 2 +#define AUX_AIODIO_IOMODE_IO6_M 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_S 12 +#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 +#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 +#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 + +// Field: [11:10] IO5 +// +// Select mode for AUXIO[8i+5]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 5 is 0: +// AUXIO[8i+5] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 5 is 1: +// AUXIO[8i+5] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 5 is 0: +// AUXIO[8i+5] is driven low. +// +// When GPIODOUT bit 5 is 1: +// AUXIO[8i+5] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 5 is 0: +// AUXIO[8i+5] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 5 is 1: +// AUXIO[8i+5] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 5 drives +// AUXIO[8i+5]. +#define AUX_AIODIO_IOMODE_IO5_W 2 +#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_S 10 +#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 +#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 +#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 + +// Field: [9:8] IO4 +// +// Select mode for AUXIO[8i+4]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 4 is 0: +// AUXIO[8i+4] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 4 is 1: +// AUXIO[8i+4] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 4 is 0: +// AUXIO[8i+4] is driven low. +// +// When GPIODOUT bit 4 is 1: +// AUXIO[8i+4] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 4 is 0: +// AUXIO[8i+4] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 4 is 1: +// AUXIO[8i+4] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 4 drives +// AUXIO[8i+4]. +#define AUX_AIODIO_IOMODE_IO4_W 2 +#define AUX_AIODIO_IOMODE_IO4_M 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_S 8 +#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 +#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 +#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 + +// Field: [7:6] IO3 +// +// Select mode for AUXIO[8i+3]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 3 is 0: +// AUXIO[8i+3] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 3 is 1: +// AUXIO[8i+3] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 3 is 0: +// AUXIO[8i+3] is driven low. +// +// When GPIODOUT bit 3 is 1: +// AUXIO[8i+3] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 3 is 0: +// AUXIO[8i+3] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 3 is 1: +// AUXIO[8i+3] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 3 drives +// AUXIO[8i+3]. +#define AUX_AIODIO_IOMODE_IO3_W 2 +#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_S 6 +#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 +#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 +#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 + +// Field: [5:4] IO2 +// +// Select mode for AUXIO[8i+2]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 2 is 0: +// AUXIO[8i+2] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 2 is 1: +// AUXIO[8i+2] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 2 is 0: +// AUXIO[8i+2] is driven low. +// +// When GPIODOUT bit 2 is 1: +// AUXIO[8i+2] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 2 is 0: +// AUXIO[8i+2] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 2 is 1: +// AUXIO[8i+2] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 2 drives +// AUXIO[8i+2]. +#define AUX_AIODIO_IOMODE_IO2_W 2 +#define AUX_AIODIO_IOMODE_IO2_M 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_S 4 +#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 +#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 +#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 + +// Field: [3:2] IO1 +// +// Select mode for AUXIO[8i+1]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 1 is 0: +// AUXIO[8i+1] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 1 is 1: +// AUXIO[8i+1] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 1 is 0: +// AUXIO[8i+1] is driven low. +// +// When GPIODOUT bit 1 is 1: +// AUXIO[8i+1] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 1 is 0: +// AUXIO[8i+1] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 1 is 1: +// AUXIO[8i+1] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 1 drives +// AUXIO[8i+1]. +#define AUX_AIODIO_IOMODE_IO1_W 2 +#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_S 2 +#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 +#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 +#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 + +// Field: [1:0] IO0 +// +// Select mode for AUXIO[8i+0]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 0 is 0: +// AUXIO[8i+0] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 0 is 1: +// AUXIO[8i+0] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 0 is 0: +// AUXIO[8i+0] is driven low. +// +// When GPIODOUT bit 0 is 1: +// AUXIO[8i+0] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 0 is 0: +// AUXIO[8i+0] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 0 is 1: +// AUXIO[8i+0] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 0 drives +// AUXIO[8i+0]. +#define AUX_AIODIO_IOMODE_IO0_W 2 +#define AUX_AIODIO_IOMODE_IO0_M 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_S 0 +#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 +#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 +#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODIN +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit +// n is set. Otherwise, bit n value is old. +#define AUX_AIODIO_GPIODIN_IO7_0_W 8 +#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIN_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTSET +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to set GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTCLR +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTTGL +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODIE +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to enable digital input buffer for +// AUXIO[8i+n]. +// Write 0 to bit index n in this bit vector to disable digital input buffer +// for AUXIO[8i+n]. +// +// You must enable the digital input buffer for AUXIO[8i+n] to read the pin +// value in GPIODIN. +// You must disable the digital input buffer for analog input or pins that +// float to avoid current leakage. +#define AUX_AIODIO_GPIODIE_IO7_0_W 8 +#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIE_IO7_0_S 0 + + +#endif // __AUX_AIODIO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_anaif.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_anaif.h new file mode 100644 index 0000000..f96db07 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_anaif.h @@ -0,0 +1,305 @@ +/****************************************************************************** +* Filename: hw_aux_anaif_h +* Revised: 2017-05-30 11:42:02 +0200 (Tue, 30 May 2017) +* Revision: 49074 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_ANAIF_H__ +#define __HW_AUX_ANAIF_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_ANAIF component +// +//***************************************************************************** +// ADC Control +#define AUX_ANAIF_O_ADCCTL 0x00000010 + +// ADC FIFO Status +#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 + +// ADC FIFO +#define AUX_ANAIF_O_ADCFIFO 0x00000018 + +// ADC Trigger +#define AUX_ANAIF_O_ADCTRIG 0x0000001C + +// Current Source Control +#define AUX_ANAIF_O_ISRCCTL 0x00000020 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCCTL +// +//***************************************************************************** +// Field: [13] START_POL +// +// Select active polarity for START_SRC event. +// ENUMs: +// FALL Set ADC trigger on falling edge of event source. +// RISE Set ADC trigger on rising edge of event source. +#define AUX_ANAIF_ADCCTL_START_POL 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_BITN 13 +#define AUX_ANAIF_ADCCTL_START_POL_M 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_S 13 +#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 + +// Field: [12:8] START_SRC +// +// Select ADC trigger event source from the asynchronous AUX event bus. +// +// Set START_SRC to NO_EVENT if you want to trigger the ADC manually through +// ADCTRIG.START. +// ENUMs: +// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ +// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// NO_EVENT1 No event. +// NO_EVENT0 No event. +// RESERVED1 Reserved - Do not use. +// RESERVED0 Reserved - Do not use. +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// TDC_DONE AUX_EVCTL:EVSTAT0.TDC_DONE +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_ANAIF_ADCCTL_START_SRC_W 5 +#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00001F00 +#define AUX_ANAIF_ADCCTL_START_SRC_S 8 +#define AUX_ANAIF_ADCCTL_START_SRC_ADC_IRQ 0x00001F00 +#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00001E00 +#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00001D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00001C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00001B00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00001A00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00001900 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00001800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00001700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00001600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00001500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00001400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00001300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00001200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00001100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00001000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000E00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_PROG_WU 0x00000C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_SW 0x00000B00 +#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT1 0x00000A00 +#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 0x00000900 +#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED1 0x00000800 +#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED0 0x00000700 +#define AUX_ANAIF_ADCCTL_START_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_ANAIF_ADCCTL_START_SRC_TIMER1_EV 0x00000500 +#define AUX_ANAIF_ADCCTL_START_SRC_TIMER0_EV 0x00000400 +#define AUX_ANAIF_ADCCTL_START_SRC_TDC_DONE 0x00000300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00000200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00000100 +#define AUX_ANAIF_ADCCTL_START_SRC_RTC_CH2_EV 0x00000000 + +// Field: [1:0] CMD +// +// ADC interface command. +// +// Non-enumerated values are not supported. The written value is returned when +// read. +// ENUMs: +// FLUSH Flush ADC FIFO. +// +// You must set CMD to EN or +// DIS after flush. +// +// System CPU must wait two +// clock cycles before it sets CMD to EN or DIS. +// EN Enable ADC interface. +// DIS Disable ADC interface. +#define AUX_ANAIF_ADCCTL_CMD_W 2 +#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_S 0 +#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 +#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCFIFOSTAT +// +//***************************************************************************** +// Field: [4] OVERFLOW +// +// FIFO overflow flag. +// +// 0: FIFO has not overflowed. +// 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. +// +// When the flag is set, the ADC FIFO write pointer is static. It is not +// possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 + +// Field: [3] UNDERFLOW +// +// FIFO underflow flag. +// +// 0: FIFO has not underflowed. +// 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. +// +// When the flag is set, the ADC FIFO read pointer is static. Read returns the +// previous sample that was read. Flush FIFO to clear the flag. +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 + +// Field: [2] FULL +// +// FIFO full flag. +// +// 0: FIFO is not full, there is less than 4 samples in the FIFO. +// 1: FIFO is full, there are 4 samples in the FIFO. +// +// When the flag is set, it is not possible to add more samples to the ADC +// FIFO. An attempt to add samples sets the OVERFLOW flag. +#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 + +// Field: [1] ALMOST_FULL +// +// FIFO almost full flag. +// +// 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL +// flag is also asserted in the latter case. +// 1: There are 3 samples in the FIFO, there is room for one more sample. +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 + +// Field: [0] EMPTY +// +// FIFO empty flag. +// +// 0: FIFO contains one or more samples. +// 1: FIFO is empty. +// +// When the flag is set, read returns the previous sample that was read and +// sets the UNDERFLOW flag. +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCFIFO +// +//***************************************************************************** +// Field: [11:0] DATA +// +// FIFO data. +// +// Read: +// Get oldest ADC sample from FIFO. +// +// Write: +// Write dummy sample to FIFO. This is useful for code development when you do +// not have real ADC samples. +#define AUX_ANAIF_ADCFIFO_DATA_W 12 +#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF +#define AUX_ANAIF_ADCFIFO_DATA_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCTRIG +// +//***************************************************************************** +// Field: [0] START +// +// Manual ADC trigger. +// +// 0: No effect. +// 1: Single ADC trigger. +// +// To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to +// avoid conflict with event-driven ADC trigger. +#define AUX_ANAIF_ADCTRIG_START 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_BITN 0 +#define AUX_ANAIF_ADCTRIG_START_M 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ISRCCTL +// +//***************************************************************************** +// Field: [0] RESET_N +// +// ISRC reset control. +// +// 0: ISRC drives 0 uA. +// 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. +#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 +#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_S 0 + + +#endif // __AUX_ANAIF__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_evctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_evctl.h new file mode 100644 index 0000000..0969dfc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_evctl.h @@ -0,0 +1,1852 @@ +/****************************************************************************** +* Filename: hw_aux_evctl_h +* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) +* Revision: 49005 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_EVCTL_H__ +#define __HW_AUX_EVCTL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_EVCTL component +// +//***************************************************************************** +// Vector Configuration 0 +#define AUX_EVCTL_O_VECCFG0 0x00000000 + +// Vector Configuration 1 +#define AUX_EVCTL_O_VECCFG1 0x00000004 + +// Sensor Controller Engine Wait Event Selection +#define AUX_EVCTL_O_SCEWEVSEL 0x00000008 + +// Events To AON Flags +#define AUX_EVCTL_O_EVTOAONFLAGS 0x0000000C + +// Events To AON Polarity +#define AUX_EVCTL_O_EVTOAONPOL 0x00000010 + +// Direct Memory Access Control +#define AUX_EVCTL_O_DMACTL 0x00000014 + +// Software Event Set +#define AUX_EVCTL_O_SWEVSET 0x00000018 + +// Event Status 0 +#define AUX_EVCTL_O_EVSTAT0 0x0000001C + +// Event Status 1 +#define AUX_EVCTL_O_EVSTAT1 0x00000020 + +// Event To MCU Polarity +#define AUX_EVCTL_O_EVTOMCUPOL 0x00000024 + +// Events to MCU Flags +#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000028 + +// Combined Event To MCU Mask +#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000002C + +// Vector Flags +#define AUX_EVCTL_O_VECFLAGS 0x00000034 + +// Events To MCU Flags Clear +#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038 + +// Events To AON Clear +#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000003C + +// Vector Flags Clear +#define AUX_EVCTL_O_VECFLAGSCLR 0x00000040 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_VECCFG0 +// +//***************************************************************************** +// Field: [14] VEC1_POL +// +// Vector 1 trigger event polarity. +// +// To manually trigger vector 1 execution: +// - AUX_SCE must sleep. +// - Set VEC1_EV to a known static value. +// - Toggle VEC1_POL twice. +// ENUMs: +// FALL Falling edge triggers vector 1 execution. +// RISE Rising edge triggers vector 1 execution. +#define AUX_EVCTL_VECCFG0_VEC1_POL 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_BITN 14 +#define AUX_EVCTL_VECCFG0_VEC1_POL_M 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_S 14 +#define AUX_EVCTL_VECCFG0_VEC1_POL_FALL 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_RISE 0x00000000 + +// Field: [13] VEC1_EN +// +// Vector 1 trigger enable. +// +// When enabled, VEC1_EV event with VEC1_POL polarity triggers a jump to vector +// # 1 when AUX_SCE sleeps. +// +// Lower vectors (0) have priority. +// ENUMs: +// EN Enable vector 1 trigger. +// DIS Disable vector 1 trigger. +#define AUX_EVCTL_VECCFG0_VEC1_EN 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_BITN 13 +#define AUX_EVCTL_VECCFG0_VEC1_EN_M 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_S 13 +#define AUX_EVCTL_VECCFG0_VEC1_EN_EN 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_DIS 0x00000000 + +// Field: [12:8] VEC1_EV +// +// Select vector 1 trigger source event. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_VECCFG0_VEC1_EV_W 5 +#define AUX_EVCTL_VECCFG0_VEC1_EV_M 0x00001F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_S 8 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_IRQ 0x00001F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_MCU_EV 0x00001E00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ACLK_REF 0x00001D00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO15 0x00001C00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO14 0x00001B00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO13 0x00001A00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO12 0x00001900 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO11 0x00001800 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO10 0x00001700 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO9 0x00001600 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO8 0x00001500 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO7 0x00001400 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO6 0x00001300 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO5 0x00001200 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO4 0x00001100 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO3 0x00001000 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO2 0x00000F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO1 0x00000E00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO0 0x00000D00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_PROG_WU 0x00000C00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_SW 0x00000B00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX1 0x00000A00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX0 0x00000900 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_DONE 0x00000700 +#define AUX_EVCTL_VECCFG0_VEC1_EV_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER1_EV 0x00000500 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER0_EV 0x00000400 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TDC_DONE 0x00000300 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPB 0x00000200 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPA 0x00000100 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_RTC_CH2 0x00000000 + +// Field: [6] VEC0_POL +// +// Vector 0 trigger event polarity. +// +// To manually trigger vector 0 execution: +// - AUX_SCE must sleep. +// - Set VEC0_EV to a known static value. +// - Toggle VEC0_POL twice. +// ENUMs: +// FALL Falling edge triggers vector 0 execution. +// RISE Rising edge triggers vector 0 execution. +#define AUX_EVCTL_VECCFG0_VEC0_POL 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_BITN 6 +#define AUX_EVCTL_VECCFG0_VEC0_POL_M 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_S 6 +#define AUX_EVCTL_VECCFG0_VEC0_POL_FALL 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_RISE 0x00000000 + +// Field: [5] VEC0_EN +// +// Vector 0 trigger enable. +// +// When enabled, VEC0_EV event with VEC0_POL polarity triggers a jump to vector +// # 0 when AUX_SCE sleeps. +// ENUMs: +// EN Enable vector 0 trigger. +// DIS Disable vector 0 trigger. +#define AUX_EVCTL_VECCFG0_VEC0_EN 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_BITN 5 +#define AUX_EVCTL_VECCFG0_VEC0_EN_M 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_S 5 +#define AUX_EVCTL_VECCFG0_VEC0_EN_EN 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_DIS 0x00000000 + +// Field: [4:0] VEC0_EV +// +// Select vector 0 trigger source event. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_VECCFG0_VEC0_EV_W 5 +#define AUX_EVCTL_VECCFG0_VEC0_EV_M 0x0000001F +#define AUX_EVCTL_VECCFG0_VEC0_EV_S 0 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_VECCFG0_VEC0_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_VECCFG0_VEC0_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_SW 0x0000000B +#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_VECCFG0_VEC0_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_VECCFG1 +// +//***************************************************************************** +// Field: [14] VEC3_POL +// +// Vector 3 trigger event polarity. +// +// To manually trigger vector 3 execution: +// - AUX_SCE must sleep. +// - Set VEC3_EV to a known static value. +// - Toggle VEC3_POL twice. +// ENUMs: +// FALL Falling edge triggers vector 3 execution. +// RISE Rising edge triggers vector 3 execution. +#define AUX_EVCTL_VECCFG1_VEC3_POL 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_BITN 14 +#define AUX_EVCTL_VECCFG1_VEC3_POL_M 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_S 14 +#define AUX_EVCTL_VECCFG1_VEC3_POL_FALL 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_RISE 0x00000000 + +// Field: [13] VEC3_EN +// +// Vector 3 trigger enable. +// +// When enabled, VEC3_EV event with VEC3_POL polarity triggers a jump to vector +// # 3 when AUX_SCE sleeps. +// +// Lower vectors (0, 1, and 2) have priority. +// ENUMs: +// EN Enable vector 3 trigger. +// DIS Disable vector 3 trigger. +#define AUX_EVCTL_VECCFG1_VEC3_EN 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_BITN 13 +#define AUX_EVCTL_VECCFG1_VEC3_EN_M 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_S 13 +#define AUX_EVCTL_VECCFG1_VEC3_EN_EN 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_DIS 0x00000000 + +// Field: [12:8] VEC3_EV +// +// Select vector 3 trigger source event. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_VECCFG1_VEC3_EV_W 5 +#define AUX_EVCTL_VECCFG1_VEC3_EV_M 0x00001F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_S 8 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_IRQ 0x00001F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_MCU_EV 0x00001E00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ACLK_REF 0x00001D00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO15 0x00001C00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO14 0x00001B00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO13 0x00001A00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO12 0x00001900 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO11 0x00001800 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO10 0x00001700 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO9 0x00001600 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO8 0x00001500 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO7 0x00001400 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO6 0x00001300 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO5 0x00001200 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO4 0x00001100 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO3 0x00001000 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO2 0x00000F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO1 0x00000E00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO0 0x00000D00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_PROG_WU 0x00000C00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_SW 0x00000B00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX1 0x00000A00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX0 0x00000900 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_DONE 0x00000700 +#define AUX_EVCTL_VECCFG1_VEC3_EV_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER1_EV 0x00000500 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER0_EV 0x00000400 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TDC_DONE 0x00000300 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPB 0x00000200 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPA 0x00000100 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_RTC_CH2 0x00000000 + +// Field: [6] VEC2_POL +// +// Vector 2 trigger event polarity. +// +// To manually trigger vector 2 execution: +// - AUX_SCE must sleep. +// - Set VEC2_EV to a known static value. +// - Toggle VEC2_POL twice. +// ENUMs: +// FALL Falling edge triggers vector 2 execution. +// RISE Rising edge triggers vector 2 execution. +#define AUX_EVCTL_VECCFG1_VEC2_POL 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_BITN 6 +#define AUX_EVCTL_VECCFG1_VEC2_POL_M 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_S 6 +#define AUX_EVCTL_VECCFG1_VEC2_POL_FALL 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_RISE 0x00000000 + +// Field: [5] VEC2_EN +// +// Vector 2 trigger enable. +// +// When enabled, VEC2_EV event with VEC2_POL polarity triggers a jump to vector +// # 2 when AUX_SCE sleeps. +// +// Lower vectors (0 and 1) have priority. +// ENUMs: +// EN Enable vector 2 trigger. +// DIS Disable vector 2 trigger. +#define AUX_EVCTL_VECCFG1_VEC2_EN 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_BITN 5 +#define AUX_EVCTL_VECCFG1_VEC2_EN_M 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_S 5 +#define AUX_EVCTL_VECCFG1_VEC2_EN_EN 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_DIS 0x00000000 + +// Field: [4:0] VEC2_EV +// +// Select vector 2 trigger source event. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_VECCFG1_VEC2_EV_W 5 +#define AUX_EVCTL_VECCFG1_VEC2_EV_M 0x0000001F +#define AUX_EVCTL_VECCFG1_VEC2_EV_S 0 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_VECCFG1_VEC2_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_VECCFG1_VEC2_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_SW 0x0000000B +#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_VECCFG1_VEC2_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_SCEWEVSEL +// +//***************************************************************************** +// Field: [4:0] WEV7_EV +// +// Select event source to connect to AUX_SCE:WUSTAT.EV_SIGNALS bit 7. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_W 5 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_M 0x0000001F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_S 0 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_SW 0x0000000B +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONFLAGS +// +//***************************************************************************** +// Field: [8] TIMER1_EV +// +// This event flag is set when level selected by EVTOAONPOL.TIMER1_EV occurs on +// EVSTAT0.TIMER1_EV. +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_S 8 + +// Field: [7] TIMER0_EV +// +// This event flag is set when level selected by EVTOAONPOL.TIMER0_EV occurs on +// EVSTAT0.TIMER0_EV. +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_S 7 + +// Field: [6] TDC_DONE +// +// This event flag is set when level selected by EVTOAONPOL.TDC_DONE occurs on +// EVSTAT0.TDC_DONE. +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_S 6 + +// Field: [5] ADC_DONE +// +// This event flag is set when level selected by EVTOAONPOL.ADC_DONE occurs on +// EVSTAT0.ADC_DONE. +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_S 5 + +// Field: [4] AUX_COMPB +// +// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on +// EVSTAT0.AUX_COMPB. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4 + +// Field: [3] AUX_COMPA +// +// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on +// EVSTAT0.AUX_COMPA. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3 + +// Field: [2] SWEV2 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV2. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV1. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV0. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONPOL +// +//***************************************************************************** +// Field: [8] TIMER1_EV +// +// Select the level of EVSTAT0.TIMER1_EV that sets EVTOAONFLAGS.TIMER1_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_LOW 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_HIGH 0x00000000 + +// Field: [7] TIMER0_EV +// +// Select the level of EVSTAT0.TIMER0_EV that sets EVTOAONFLAGS.TIMER0_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_LOW 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_HIGH 0x00000000 + +// Field: [6] TDC_DONE +// +// Select level of EVSTAT0.TDC_DONE that sets EVTOAONFLAGS.TDC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_HIGH 0x00000000 + +// Field: [5] ADC_DONE +// +// Select the level of EVSTAT0.ADC_DONE that sets EVTOAONFLAGS.ADC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_LOW 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_HIGH 0x00000000 + +// Field: [4] AUX_COMPB +// +// Select the edge of EVSTAT0.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB. +// ENUMs: +// LOW Falling edge +// HIGH Rising edge +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_LOW 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_HIGH 0x00000000 + +// Field: [3] AUX_COMPA +// +// Select the edge of EVSTAT0.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA. +// ENUMs: +// LOW Falling edge +// HIGH Rising edge +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_LOW 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_HIGH 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_DMACTL +// +//***************************************************************************** +// Field: [2] REQ_MODE +// +// UDMA0 Request mode +// ENUMs: +// SINGLE Single requests are generated on UDMA0 channel 7 +// when the condition configured in SEL is met. +// BURST Burst requests are generated on UDMA0 channel 7 +// when the condition configured in SEL is met. +#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_S 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000 + +// Field: [1] EN +// +// uDMA ADC interface enable. +// +// 0: Disable UDMA0 interface to ADC. +// 1: Enable UDMA0 interface to ADC. +#define AUX_EVCTL_DMACTL_EN 0x00000002 +#define AUX_EVCTL_DMACTL_EN_BITN 1 +#define AUX_EVCTL_DMACTL_EN_M 0x00000002 +#define AUX_EVCTL_DMACTL_EN_S 1 + +// Field: [0] SEL +// +// Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO +// data. +// ENUMs: +// FIFO_ALMOST_FULL UDMA0 trigger event will be generated when the ADC +// FIFO is almost full (3/4 full). +// FIFO_NOT_EMPTY UDMA0 trigger event will be generated when there +// are samples in the ADC FIFO. +#define AUX_EVCTL_DMACTL_SEL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_BITN 0 +#define AUX_EVCTL_DMACTL_SEL_M 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_S 0 +#define AUX_EVCTL_DMACTL_SEL_FIFO_ALMOST_FULL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_SWEVSET +// +//***************************************************************************** +// Field: [2] SWEV2 +// +// Software event flag 2. +// +// 0: No effect. +// 1: Set software event flag 2. +#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2 +#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// Software event flag 1. +// +// 0: No effect. +// 1: Set software event flag 1. +#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1 +#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// Software event flag 0. +// +// 0: No effect. +// 1: Set software event flag 0. +#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0 +#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT0 +// +//***************************************************************************** +// Field: [15] AUXIO2 +// +// AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 15 +#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO2_S 15 + +// Field: [14] AUXIO1 +// +// AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 14 +#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO1_S 14 + +// Field: [13] AUXIO0 +// +// AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 13 +#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO0_S 13 + +// Field: [12] AON_PROG_WU +// +// AON_EVENT:AUXWUSEL.WU2_EV OR AON_EVENT:AUXWUSEL.WU1_EV OR +// AON_EVENT:AUXWUSEL.WU0_EV +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU 0x00001000 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_BITN 12 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_M 0x00001000 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_S 12 + +// Field: [11] AON_SW +// +// AON_WUC:AUXCTL.SWEV +#define AUX_EVCTL_EVSTAT0_AON_SW 0x00000800 +#define AUX_EVCTL_EVSTAT0_AON_SW_BITN 11 +#define AUX_EVCTL_EVSTAT0_AON_SW_M 0x00000800 +#define AUX_EVCTL_EVSTAT0_AON_SW_S 11 + +// Field: [10] OBSMUX1 +// +// Observation input 1 from IOC. +// This event is configured by IOC:OBSAUXOUTPUT.SEL1. +#define AUX_EVCTL_EVSTAT0_OBSMUX1 0x00000400 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_BITN 10 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_M 0x00000400 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_S 10 + +// Field: [9] OBSMUX0 +// +// Observation input 0 from IOC. +// This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by +// IOC:OBSAUXOUTPUT.SEL_MISC. +#define AUX_EVCTL_EVSTAT0_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_S 9 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] ADC_DONE +// +// AUX_ANAIF ADC conversion done event. +#define AUX_EVCTL_EVSTAT0_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_S 7 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// See AUX_SMPH:AUTOTAKE.SMPH_ID for description. +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] TIMER1_EV +// +// AUX_TIMER1_EV event, see AUX_TIMER:T1TARGET for description. +#define AUX_EVCTL_EVSTAT0_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_S 5 + +// Field: [4] TIMER0_EV +// +// AUX_TIMER0_EV event, see AUX_TIMER:T0TARGET for description. +#define AUX_EVCTL_EVSTAT0_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_S 4 + +// Field: [3] TDC_DONE +// +// AUX_TDC:STAT.DONE +#define AUX_EVCTL_EVSTAT0_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// Comparator B output +#define AUX_EVCTL_EVSTAT0_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// Comparator A output +#define AUX_EVCTL_EVSTAT0_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_S 1 + +// Field: [0] AON_RTC_CH2 +// +// AON_RTC:EVFLAGS.CH2 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2 0x00000001 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_BITN 0 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_M 0x00000001 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT1 +// +//***************************************************************************** +// Field: [15] ADC_IRQ +// +// The logical function for this event is configurable. +// +// When DMACTL.EN = 1 : +// Event = UDMA0 Channel 7 done event OR +// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW +// +// When DMACTL.EN = 0 : +// Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR +// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW +// +// Bit 7 in UDMA0:DONEMASK must be 0. +#define AUX_EVCTL_EVSTAT1_ADC_IRQ 0x00008000 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_BITN 15 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_M 0x00008000 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_S 15 + +// Field: [14] MCU_EV +// +// Event from EVENT configured by EVENT:AUXSEL0. +#define AUX_EVCTL_EVSTAT1_MCU_EV 0x00004000 +#define AUX_EVCTL_EVSTAT1_MCU_EV_BITN 14 +#define AUX_EVCTL_EVSTAT1_MCU_EV_M 0x00004000 +#define AUX_EVCTL_EVSTAT1_MCU_EV_S 14 + +// Field: [13] ACLK_REF +// +// TDC reference clock. +// It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by +// AUX_WUC:REFCLKCTL.REQ. +#define AUX_EVCTL_EVSTAT1_ACLK_REF 0x00002000 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_BITN 13 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_M 0x00002000 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_S 13 + +// Field: [12] AUXIO15 +// +// AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT1_AUXIO15 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO15_BITN 12 +#define AUX_EVCTL_EVSTAT1_AUXIO15_M 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO15_S 12 + +// Field: [11] AUXIO14 +// +// AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT1_AUXIO14 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO14_BITN 11 +#define AUX_EVCTL_EVSTAT1_AUXIO14_M 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO14_S 11 + +// Field: [10] AUXIO13 +// +// AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT1_AUXIO13 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO13_BITN 10 +#define AUX_EVCTL_EVSTAT1_AUXIO13_M 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO13_S 10 + +// Field: [9] AUXIO12 +// +// AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT1_AUXIO12 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO12_BITN 9 +#define AUX_EVCTL_EVSTAT1_AUXIO12_M 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO12_S 9 + +// Field: [8] AUXIO11 +// +// AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT1_AUXIO11 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO11_BITN 8 +#define AUX_EVCTL_EVSTAT1_AUXIO11_M 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO11_S 8 + +// Field: [7] AUXIO10 +// +// AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT1_AUXIO10 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO10_BITN 7 +#define AUX_EVCTL_EVSTAT1_AUXIO10_M 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO10_S 7 + +// Field: [6] AUXIO9 +// +// AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT1_AUXIO9 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO9_BITN 6 +#define AUX_EVCTL_EVSTAT1_AUXIO9_M 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO9_S 6 + +// Field: [5] AUXIO8 +// +// AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT1_AUXIO8 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO8_BITN 5 +#define AUX_EVCTL_EVSTAT1_AUXIO8_M 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO8_S 5 + +// Field: [4] AUXIO7 +// +// AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT1_AUXIO7 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO7_BITN 4 +#define AUX_EVCTL_EVSTAT1_AUXIO7_M 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO7_S 4 + +// Field: [3] AUXIO6 +// +// AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT1_AUXIO6 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO6_BITN 3 +#define AUX_EVCTL_EVSTAT1_AUXIO6_M 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO6_S 3 + +// Field: [2] AUXIO5 +// +// AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT1_AUXIO5 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO5_BITN 2 +#define AUX_EVCTL_EVSTAT1_AUXIO5_M 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO5_S 2 + +// Field: [1] AUXIO4 +// +// AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT1_AUXIO4 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO4_BITN 1 +#define AUX_EVCTL_EVSTAT1_AUXIO4_M 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO4_S 1 + +// Field: [0] AUXIO3 +// +// AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT1_AUXIO3 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO3_BITN 0 +#define AUX_EVCTL_EVSTAT1_AUXIO3_M 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO3_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUPOL +// +//***************************************************************************** +// Field: [10] ADC_IRQ +// +// Select the event source level that sets EVTOMCUFLAGS.ADC_IRQ. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_LOW 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_HIGH 0x00000000 + +// Field: [9] OBSMUX0 +// +// Select the event source level that sets EVTOMCUFLAGS.OBSMUX0. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_LOW 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_HIGH 0x00000000 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// Select the event source level that sets EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_LOW 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000 + +// Field: [7] ADC_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.ADC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_LOW 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_HIGH 0x00000000 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_HIGH 0x00000000 + +// Field: [5] TIMER1_EV +// +// Select the event source level that sets EVTOMCUFLAGS.TIMER1_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_LOW 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_HIGH 0x00000000 + +// Field: [4] TIMER0_EV +// +// Select the event source level that sets EVTOMCUFLAGS.TIMER0_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_LOW 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_HIGH 0x00000000 + +// Field: [3] TDC_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.TDC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_LOW 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_HIGH 0x00000000 + +// Field: [2] AUX_COMPB +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_COMPB. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_LOW 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_HIGH 0x00000000 + +// Field: [1] AUX_COMPA +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_COMPA. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_LOW 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_HIGH 0x00000000 + +// Field: [0] AON_WU_EV +// +// Select the event source level that sets EVTOMCUFLAGS.AON_WU_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_LOW 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_HIGH 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUFLAGS +// +//***************************************************************************** +// Field: [10] ADC_IRQ +// +// This event flag is set when level selected by EVTOMCUPOL.ADC_IRQ occurs on +// EVSTAT0.ADC_IRQ. +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_S 10 + +// Field: [9] OBSMUX0 +// +// This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs +// on EVSTAT0.MCU_OBSMUX0. +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_S 9 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// This event flag is set when level selected by +// EVTOMCUPOL.ADC_FIFO_ALMOST_FULL occurs on EVSTAT0.ADC_FIFO_ALMOST_FULL. +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] ADC_DONE +// +// This event flag is set when level selected by EVTOMCUPOL.ADC_DONE occurs on +// EVSTAT0.ADC_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_S 7 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// This event flag is set when level selected by EVTOMCUPOL.SMPH_AUTOTAKE_DONE +// occurs on EVSTAT0.SMPH_AUTOTAKE_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] TIMER1_EV +// +// This event flag is set when level selected by EVTOMCUPOL.TIMER1_EV occurs on +// EVSTAT0.TIMER1_EV. +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_S 5 + +// Field: [4] TIMER0_EV +// +// This event flag is set when level selected by EVTOMCUPOL.TIMER0_EV occurs on +// EVSTAT0.TIMER0_EV. +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_S 4 + +// Field: [3] TDC_DONE +// +// This event flag is set when level selected by EVTOMCUPOL.TDC_DONE occurs on +// EVSTAT0.TDC_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on +// EVSTAT0.AUX_COMPB. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on +// EVSTAT0.AUX_COMPA. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1 + +// Field: [0] AON_WU_EV +// +// This event flag is set when level selected by EVTOMCUPOL.AON_WU_EV occurs on +// the reduction-OR of the AUX_EVCTL:EVSTAT0.RTC_CH2_EV, +// AUX_EVCTL:EVSTAT0.AON_SW, and AUX_EVCTL:EVSTAT0.AON_PROG_WU events. +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_COMBEVTOMCUMASK +// +//***************************************************************************** +// Field: [10] ADC_IRQ +// +// EVTOMCUFLAGS.ADC_IRQ contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_BITN 10 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_S 10 + +// Field: [9] OBSMUX0 +// +// EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_BITN 9 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_S 9 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] ADC_DONE +// +// EVTOMCUFLAGS.ADC_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_BITN 7 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_S 7 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] TIMER1_EV +// +// EVTOMCUFLAGS.TIMER1_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_BITN 5 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_S 5 + +// Field: [4] TIMER0_EV +// +// EVTOMCUFLAGS.TIMER0_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_BITN 4 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_S 4 + +// Field: [3] TDC_DONE +// +// EVTOMCUFLAGS.TDC_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_BITN 3 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event. +// +// 0: Exclude +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1 + +// Field: [0] AON_WU_EV +// +// EVTOMCUFLAGS.AON_WU_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_BITN 0 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_VECFLAGS +// +//***************************************************************************** +// Field: [3] VEC3 +// +// Vector flag 3. +// +// The vector flag is set if the edge selected VECCFG1.VEC3_POL occurs on the +// event selected in VECCFG1.VEC3_EV. +// +// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to +// VECFLAGSCLR.VEC3. +#define AUX_EVCTL_VECFLAGS_VEC3 0x00000008 +#define AUX_EVCTL_VECFLAGS_VEC3_BITN 3 +#define AUX_EVCTL_VECFLAGS_VEC3_M 0x00000008 +#define AUX_EVCTL_VECFLAGS_VEC3_S 3 + +// Field: [2] VEC2 +// +// Vector flag 2. +// +// The vector flag is set if the edge selected VECCFG1.VEC2_POL occurs on the +// event selected in VECCFG1.VEC2_EV. +// +// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to +// VECFLAGSCLR.VEC2. +#define AUX_EVCTL_VECFLAGS_VEC2 0x00000004 +#define AUX_EVCTL_VECFLAGS_VEC2_BITN 2 +#define AUX_EVCTL_VECFLAGS_VEC2_M 0x00000004 +#define AUX_EVCTL_VECFLAGS_VEC2_S 2 + +// Field: [1] VEC1 +// +// Vector flag 1. +// +// The vector flag is set if the edge selected VECCFG0.VEC1_POL occurs on the +// event selected in VECCFG0.VEC1_EV. +// +// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to +// VECFLAGSCLR.VEC1. +#define AUX_EVCTL_VECFLAGS_VEC1 0x00000002 +#define AUX_EVCTL_VECFLAGS_VEC1_BITN 1 +#define AUX_EVCTL_VECFLAGS_VEC1_M 0x00000002 +#define AUX_EVCTL_VECFLAGS_VEC1_S 1 + +// Field: [0] VEC0 +// +// Vector flag 0. +// +// The vector flag is set if the edge selected VECCFG0.VEC0_POL occurs on the +// event selected in VECCFG0.VEC0_EV. +// +// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to +// VECFLAGSCLR.VEC0. +#define AUX_EVCTL_VECFLAGS_VEC0 0x00000001 +#define AUX_EVCTL_VECFLAGS_VEC0_BITN 0 +#define AUX_EVCTL_VECFLAGS_VEC0_M 0x00000001 +#define AUX_EVCTL_VECFLAGS_VEC0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUFLAGSCLR +// +//***************************************************************************** +// Field: [10] ADC_IRQ +// +// Write 1 to clear EVTOMCUFLAGS.ADC_IRQ. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_S 10 + +// Field: [9] OBSMUX0 +// +// Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_S 9 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// Write 1 to clear EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] ADC_DONE +// +// Write 1 to clear EVTOMCUFLAGS.ADC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_S 7 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// Write 1 to clear EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] TIMER1_EV +// +// Write 1 to clear EVTOMCUFLAGS.TIMER1_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_S 5 + +// Field: [4] TIMER0_EV +// +// Write 1 to clear EVTOMCUFLAGS.TIMER0_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_S 4 + +// Field: [3] TDC_DONE +// +// Write 1 to clear EVTOMCUFLAGS.TDC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1 + +// Field: [0] AON_WU_EV +// +// Write 1 to clear EVTOMCUFLAGS.AON_WU_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONFLAGSCLR +// +//***************************************************************************** +// Field: [8] TIMER1_EV +// +// Write 1 to clear EVTOAONFLAGS.TIMER1_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_S 8 + +// Field: [7] TIMER0_EV +// +// Write 1 to clear EVTOAONFLAGS.TIMER0_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_S 7 + +// Field: [6] TDC_DONE +// +// Write 1 to clear EVTOAONFLAGS.TDC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_S 6 + +// Field: [5] ADC_DONE +// +// Write 1 to clear EVTOAONFLAGS.ADC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_S 5 + +// Field: [4] AUX_COMPB +// +// Write 1 to clear EVTOAONFLAGS.AUX_COMPB. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4 + +// Field: [3] AUX_COMPA +// +// Write 1 to clear EVTOAONFLAGS.AUX_COMPA. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3 + +// Field: [2] SWEV2 +// +// Write 1 to clear EVTOAONFLAGS.SWEV2. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// Write 1 to clear EVTOAONFLAGS.SWEV1. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// Write 1 to clear EVTOAONFLAGS.SWEV0. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_VECFLAGSCLR +// +//***************************************************************************** +// Field: [3] VEC3 +// +// Clear vector flag 3. +// +// 0: No effect. +// 1: Clear VECFLAGS.VEC3. +// +// Read value is 0. +#define AUX_EVCTL_VECFLAGSCLR_VEC3 0x00000008 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_BITN 3 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_M 0x00000008 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_S 3 + +// Field: [2] VEC2 +// +// Clear vector flag 2. +// +// 0: No effect. +// 1: Clear VECFLAGS.VEC2. +// +// Read value is 0. +#define AUX_EVCTL_VECFLAGSCLR_VEC2 0x00000004 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_BITN 2 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_M 0x00000004 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_S 2 + +// Field: [1] VEC1 +// +// Clear vector flag 1. +// +// 0: No effect. +// 1: Clear VECFLAGS.VEC1. +// +// Read value is 0. +#define AUX_EVCTL_VECFLAGSCLR_VEC1 0x00000002 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_BITN 1 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_M 0x00000002 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_S 1 + +// Field: [0] VEC0 +// +// Clear vector flag 0. +// +// 0: No effect. +// 1: Clear VECFLAGS.VEC0. +// +// Read value is 0. +#define AUX_EVCTL_VECFLAGSCLR_VEC0 0x00000001 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_BITN 0 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_M 0x00000001 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_S 0 + + +#endif // __AUX_EVCTL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_sce.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_sce.h new file mode 100644 index 0000000..002242a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_sce.h @@ -0,0 +1,381 @@ +/****************************************************************************** +* Filename: hw_aux_sce_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SCE_H__ +#define __HW_AUX_SCE_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SCE component +// +//***************************************************************************** +// Internal +#define AUX_SCE_O_CTL 0x00000000 + +// Internal +#define AUX_SCE_O_FETCHSTAT 0x00000004 + +// Internal +#define AUX_SCE_O_CPUSTAT 0x00000008 + +// Internal +#define AUX_SCE_O_WUSTAT 0x0000000C + +// Internal +#define AUX_SCE_O_REG1_0 0x00000010 + +// Internal +#define AUX_SCE_O_REG3_2 0x00000014 + +// Internal +#define AUX_SCE_O_REG5_4 0x00000018 + +// Internal +#define AUX_SCE_O_REG7_6 0x0000001C + +// Internal +#define AUX_SCE_O_LOOPADDR 0x00000020 + +// Internal +#define AUX_SCE_O_LOOPCNT 0x00000024 + +//***************************************************************************** +// +// Register: AUX_SCE_O_CTL +// +//***************************************************************************** +// Field: [31:24] FORCE_EV_LOW +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_EV_LOW_W 8 +#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000 +#define AUX_SCE_CTL_FORCE_EV_LOW_S 24 + +// Field: [23:16] FORCE_EV_HIGH +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8 +#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000 +#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16 + +// Field: [11:8] RESET_VECTOR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_RESET_VECTOR_W 4 +#define AUX_SCE_CTL_RESET_VECTOR_M 0x00000F00 +#define AUX_SCE_CTL_RESET_VECTOR_S 8 + +// Field: [6] DBG_FREEZE_EN +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6 +#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6 + +// Field: [5] FORCE_WU_LOW +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5 +#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_S 5 + +// Field: [4] FORCE_WU_HIGH +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4 +#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4 + +// Field: [3] RESTART +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_RESTART 0x00000008 +#define AUX_SCE_CTL_RESTART_BITN 3 +#define AUX_SCE_CTL_RESTART_M 0x00000008 +#define AUX_SCE_CTL_RESTART_S 3 + +// Field: [2] SINGLE_STEP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_SINGLE_STEP 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_BITN 2 +#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_S 2 + +// Field: [1] SUSPEND +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_SUSPEND 0x00000002 +#define AUX_SCE_CTL_SUSPEND_BITN 1 +#define AUX_SCE_CTL_SUSPEND_M 0x00000002 +#define AUX_SCE_CTL_SUSPEND_S 1 + +// Field: [0] CLK_EN +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_CLK_EN 0x00000001 +#define AUX_SCE_CTL_CLK_EN_BITN 0 +#define AUX_SCE_CTL_CLK_EN_M 0x00000001 +#define AUX_SCE_CTL_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_FETCHSTAT +// +//***************************************************************************** +// Field: [31:16] OPCODE +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_FETCHSTAT_OPCODE_W 16 +#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000 +#define AUX_SCE_FETCHSTAT_OPCODE_S 16 + +// Field: [15:0] PC +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_FETCHSTAT_PC_W 16 +#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF +#define AUX_SCE_FETCHSTAT_PC_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_CPUSTAT +// +//***************************************************************************** +// Field: [11] BUS_ERROR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11 +#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11 + +// Field: [10] SLEEP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_SLEEP 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_BITN 10 +#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_S 10 + +// Field: [9] WEV +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_WEV 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_BITN 9 +#define AUX_SCE_CPUSTAT_WEV_M 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_S 9 + +// Field: [8] SELF_STOP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_SELF_STOP 0x00000100 +#define AUX_SCE_CPUSTAT_SELF_STOP_BITN 8 +#define AUX_SCE_CPUSTAT_SELF_STOP_M 0x00000100 +#define AUX_SCE_CPUSTAT_SELF_STOP_S 8 + +// Field: [3] V_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3 +#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_S 3 + +// Field: [2] C_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2 +#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_S 2 + +// Field: [1] N_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1 +#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_S 1 + +// Field: [0] Z_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0 +#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_WUSTAT +// +//***************************************************************************** +// Field: [17:16] EXC_VECTOR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_EXC_VECTOR_W 2 +#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00030000 +#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16 + +// Field: [8] WU_SIGNAL +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8 +#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8 + +// Field: [7:0] EV_SIGNALS +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8 +#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF +#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG1_0 +// +//***************************************************************************** +// Field: [31:16] REG1 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG1_0_REG1_W 16 +#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000 +#define AUX_SCE_REG1_0_REG1_S 16 + +// Field: [15:0] REG0 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG1_0_REG0_W 16 +#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF +#define AUX_SCE_REG1_0_REG0_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG3_2 +// +//***************************************************************************** +// Field: [31:16] REG3 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG3_2_REG3_W 16 +#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000 +#define AUX_SCE_REG3_2_REG3_S 16 + +// Field: [15:0] REG2 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG3_2_REG2_W 16 +#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF +#define AUX_SCE_REG3_2_REG2_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG5_4 +// +//***************************************************************************** +// Field: [31:16] REG5 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG5_4_REG5_W 16 +#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000 +#define AUX_SCE_REG5_4_REG5_S 16 + +// Field: [15:0] REG4 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG5_4_REG4_W 16 +#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF +#define AUX_SCE_REG5_4_REG4_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG7_6 +// +//***************************************************************************** +// Field: [31:16] REG7 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG7_6_REG7_W 16 +#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000 +#define AUX_SCE_REG7_6_REG7_S 16 + +// Field: [15:0] REG6 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG7_6_REG6_W 16 +#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF +#define AUX_SCE_REG7_6_REG6_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_LOOPADDR +// +//***************************************************************************** +// Field: [31:16] STOP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPADDR_STOP_W 16 +#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000 +#define AUX_SCE_LOOPADDR_STOP_S 16 + +// Field: [15:0] START +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPADDR_START_W 16 +#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF +#define AUX_SCE_LOOPADDR_START_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_LOOPCNT +// +//***************************************************************************** +// Field: [7:0] ITER_LEFT +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8 +#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF +#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0 + + +#endif // __AUX_SCE__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_smph.h new file mode 100644 index 0000000..ec7fa57 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_smph.h @@ -0,0 +1,282 @@ +/****************************************************************************** +* Filename: hw_aux_smph_h +* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) +* Revision: 49005 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SMPH_H__ +#define __HW_AUX_SMPH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SMPH component +// +//***************************************************************************** +// Semaphore 0 +#define AUX_SMPH_O_SMPH0 0x00000000 + +// Semaphore 1 +#define AUX_SMPH_O_SMPH1 0x00000004 + +// Semaphore 2 +#define AUX_SMPH_O_SMPH2 0x00000008 + +// Semaphore 3 +#define AUX_SMPH_O_SMPH3 0x0000000C + +// Semaphore 4 +#define AUX_SMPH_O_SMPH4 0x00000010 + +// Semaphore 5 +#define AUX_SMPH_O_SMPH5 0x00000014 + +// Semaphore 6 +#define AUX_SMPH_O_SMPH6 0x00000018 + +// Semaphore 7 +#define AUX_SMPH_O_SMPH7 0x0000001C + +// Auto Take +#define AUX_SMPH_O_AUTOTAKE 0x00000020 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH0_STAT 0x00000001 +#define AUX_SMPH_SMPH0_STAT_BITN 0 +#define AUX_SMPH_SMPH0_STAT_M 0x00000001 +#define AUX_SMPH_SMPH0_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH1_STAT 0x00000001 +#define AUX_SMPH_SMPH1_STAT_BITN 0 +#define AUX_SMPH_SMPH1_STAT_M 0x00000001 +#define AUX_SMPH_SMPH1_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH2_STAT 0x00000001 +#define AUX_SMPH_SMPH2_STAT_BITN 0 +#define AUX_SMPH_SMPH2_STAT_M 0x00000001 +#define AUX_SMPH_SMPH2_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH3_STAT 0x00000001 +#define AUX_SMPH_SMPH3_STAT_BITN 0 +#define AUX_SMPH_SMPH3_STAT_M 0x00000001 +#define AUX_SMPH_SMPH3_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH4_STAT 0x00000001 +#define AUX_SMPH_SMPH4_STAT_BITN 0 +#define AUX_SMPH_SMPH4_STAT_M 0x00000001 +#define AUX_SMPH_SMPH4_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH5_STAT 0x00000001 +#define AUX_SMPH_SMPH5_STAT_BITN 0 +#define AUX_SMPH_SMPH5_STAT_M 0x00000001 +#define AUX_SMPH_SMPH5_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH6_STAT 0x00000001 +#define AUX_SMPH_SMPH6_STAT_BITN 0 +#define AUX_SMPH_SMPH6_STAT_M 0x00000001 +#define AUX_SMPH_SMPH6_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH7_STAT 0x00000001 +#define AUX_SMPH_SMPH7_STAT_BITN 0 +#define AUX_SMPH_SMPH7_STAT_M 0x00000001 +#define AUX_SMPH_SMPH7_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_AUTOTAKE +// +//***************************************************************************** +// Field: [2:0] SMPH_ID +// +// Write the semaphore ID,0x0-0x7, to SMPH_ID to request this semaphore until +// it is granted. +// +// When semaphore SMPH_ID is granted, event +// AUX_EVCTL:EVSTAT0.AUX_SMPH_AUTOTAKE_DONE becomes 1. +// +// The event becomes 0 when software releases the semaphore or writes a new +// value to SMPH_ID. +// +// To avoid corrupted semaphores: +// - Usage of this functionality must be restricted to one CPU core. +// - Software must wait until AUX_EVCTL:EVSTAT0.AUX_SMPH_AUTOTAKE_DONE is 1 +// before it writes a new value to SMPH_ID. +#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0 + + +#endif // __AUX_SMPH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_tdc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_tdc.h new file mode 100644 index 0000000..21d490e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_tdc.h @@ -0,0 +1,694 @@ +/****************************************************************************** +* Filename: hw_aux_tdc_h +* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) +* Revision: 49005 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_TDC_H__ +#define __HW_AUX_TDC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_TDC component +// +//***************************************************************************** +// Control +#define AUX_TDC_O_CTL 0x00000000 + +// Status +#define AUX_TDC_O_STAT 0x00000004 + +// Result +#define AUX_TDC_O_RESULT 0x00000008 + +// Saturation Configuration +#define AUX_TDC_O_SATCFG 0x0000000C + +// Trigger Source +#define AUX_TDC_O_TRIGSRC 0x00000010 + +// Trigger Counter +#define AUX_TDC_O_TRIGCNT 0x00000014 + +// Trigger Counter Load +#define AUX_TDC_O_TRIGCNTLOAD 0x00000018 + +// Trigger Counter Configuration +#define AUX_TDC_O_TRIGCNTCFG 0x0000001C + +// Prescaler Control +#define AUX_TDC_O_PRECTL 0x00000020 + +// Prescaler Counter +#define AUX_TDC_O_PRECNT 0x00000024 + +//***************************************************************************** +// +// Register: AUX_TDC_O_CTL +// +//***************************************************************************** +// Field: [1:0] CMD +// +// TDC commands. +// ENUMs: +// ABORT Force TDC state machine back to IDLE state. +// +// Never write this command +// while AUX_TDC:STAT.STATE equals CLR_CNT or +// WAIT_CLR_CNT_DONE. +// RUN Asynchronous counter start. +// +// The counter starts to +// count when the start event is high. To achieve +// precise edge-to-edge measurements you must +// ensure that the start event is low for at least +// 420 ns after you write this command. +// RUN_SYNC_START Synchronous counter start. +// +// The counter looks for the +// opposite edge of the selected start event +// before it starts to count when the selected +// edge occurs. This guarantees an edge-triggered +// start and is recommended for frequency +// measurements. +// CLR_RESULT Clear STAT.SAT, STAT.DONE, and RESULT.VALUE. +// +// This is not needed as +// prerequisite for a measurement. Reliable clear +// is only guaranteed from IDLE state. +#define AUX_TDC_CTL_CMD_W 2 +#define AUX_TDC_CTL_CMD_M 0x00000003 +#define AUX_TDC_CTL_CMD_S 0 +#define AUX_TDC_CTL_CMD_ABORT 0x00000003 +#define AUX_TDC_CTL_CMD_RUN 0x00000002 +#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 +#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_STAT +// +//***************************************************************************** +// Field: [7] SAT +// +// TDC measurement saturation flag. +// +// 0: Conversion has not saturated. +// 1: Conversion stopped due to saturation. +// +// This field is cleared when a new measurement is started or when CLR_RESULT +// is written to CTL.CMD. +#define AUX_TDC_STAT_SAT 0x00000080 +#define AUX_TDC_STAT_SAT_BITN 7 +#define AUX_TDC_STAT_SAT_M 0x00000080 +#define AUX_TDC_STAT_SAT_S 7 + +// Field: [6] DONE +// +// TDC measurement complete flag. +// +// 0: TDC measurement has not yet completed. +// 1: TDC measurement has completed. +// +// This field clears when a new TDC measurement starts or when you write +// CLR_RESULT to CTL.CMD. +#define AUX_TDC_STAT_DONE 0x00000040 +#define AUX_TDC_STAT_DONE_BITN 6 +#define AUX_TDC_STAT_DONE_M 0x00000040 +#define AUX_TDC_STAT_DONE_S 6 + +// Field: [5:0] STATE +// +// TDC state machine status. +// ENUMs: +// FORCE_STOP Current state is TDC_FORCESTOP. +// You wrote ABORT to +// CTL.CMD to abort the TDC measurement. +// START_FALL Current state is TDC_WAIT_STARTFALL. +// The fast-counter circuit +// waits for a falling edge on the start event. +// WAIT_CLR_CNT_DONE Current state is TDC_STATE_WAIT_CLRCNT_DONE. +// The state machine waits +// for fast-counter circuit to finish reset. +// POR Current state is TDC_STATE_POR. +// This is the reset state. +// GET_RESULT Current state is TDC_STATE_GETRESULTS. +// The state machine copies +// the counter value from the fast-counter +// circuit. +// WAIT_STOP_CNTDWN Current state is TDC_STATE_WAIT_STOPCNTDOWN. +// The fast-counter circuit +// looks for the stop condition. It will ignore a +// number of stop events configured in +// TRIGCNTLOAD.CNT. +// WAIT_STOP Current state is TDC_STATE_WAIT_STOP. +// The state machine waits +// for the fast-counter circuit to stop. +// CLR_CNT Current state is TDC_STATE_CLRCNT. The +// fast-counter circuit is reset. +// IDLE Current state is TDC_STATE_IDLE. +// This is the default state +// after reset and abortion. State will change +// when you write CTL.CMD to either RUN_SYNC_START +// or RUN. +// WAIT_START_STOP_CNT_EN Current state is TDC_STATE_WAIT_STARTSTOPCNTEN. +// The fast-counter circuit +// looks for the start condition. The state +// machine waits for the fast-counter to +// increment. +// WAIT_START Current state is TDC_STATE_WAIT_START. +// The fast-counter circuit +// looks for the start condition. The state +// machine waits for the fast-counter to +// increment. +#define AUX_TDC_STAT_STATE_W 6 +#define AUX_TDC_STAT_STATE_M 0x0000003F +#define AUX_TDC_STAT_STATE_S 0 +#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E +#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E +#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 +#define AUX_TDC_STAT_STATE_POR 0x0000000F +#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E +#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C +#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 +#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 +#define AUX_TDC_STAT_STATE_IDLE 0x00000006 +#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 +#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_RESULT +// +//***************************************************************************** +// Field: [24:0] VALUE +// +// TDC conversion result. +// +// The result of the TDC conversion is given in number of clock edges of the +// clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and +// falling edges are counted. +// +// If TDC counter saturates, VALUE is slightly higher than SATCFG.LIMIT, as it +// takes a non-zero time to stop the measurement. Hence, the maximum value of +// this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT +// to R24. +#define AUX_TDC_RESULT_VALUE_W 25 +#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF +#define AUX_TDC_RESULT_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_SATCFG +// +//***************************************************************************** +// Field: [3:0] LIMIT +// +// Saturation limit. +// +// The flag STAT.SAT is set when the TDC counter saturates. +// +// Values not enumerated are not supported +// ENUMs: +// R24 Result bit 24: TDC conversion saturates and stops +// when RESULT.VALUE[24] is set. +// R23 Result bit 23: TDC conversion saturates and stops +// when RESULT.VALUE[23] is set. +// R22 Result bit 22: TDC conversion saturates and stops +// when RESULT.VALUE[22] is set. +// R21 Result bit 21: TDC conversion saturates and stops +// when RESULT.VALUE[21] is set. +// R20 Result bit 20: TDC conversion saturates and stops +// when RESULT.VALUE[20] is set. +// R19 Result bit 19: TDC conversion saturates and stops +// when RESULT.VALUE[19] is set. +// R18 Result bit 18: TDC conversion saturates and stops +// when RESULT.VALUE[18] is set. +// R17 Result bit 17: TDC conversion saturates and stops +// when RESULT.VALUE[17] is set. +// R16 Result bit 16: TDC conversion saturates and stops +// when RESULT.VALUE[16] is set. +// R15 Result bit 15: TDC conversion saturates and stops +// when RESULT.VALUE[15] is set. +// R14 Result bit 14: TDC conversion saturates and stops +// when RESULT.VALUE[14] is set. +// R13 Result bit 13: TDC conversion saturates and stops +// when RESULT.VALUE[13] is set. +// R12 Result bit 12: TDC conversion saturates and stops +// when RESULT.VALUE[12] is set. +#define AUX_TDC_SATCFG_LIMIT_W 4 +#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_S 0 +#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E +#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D +#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C +#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B +#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A +#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 +#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 +#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 +#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 +#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 +#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 +#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGSRC +// +//***************************************************************************** +// Field: [13] STOP_POL +// +// Polarity of stop source. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// LOW TDC conversion stops when low level is detected. +// HIGH TDC conversion stops when high level is detected. +#define AUX_TDC_TRIGSRC_STOP_POL 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_BITN 13 +#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_S 13 +#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 + +// Field: [12:8] STOP_SRC +// +// Select stop source from the asynchronous AUX event bus. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// TDC_PRE Select TDC Prescaler event which is generated by +// configuration of PRECTL. +// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TDC_TRIGSRC_STOP_SRC_W 5 +#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00001F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_S 8 +#define AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE 0x00001F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00001E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00001D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00001C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00001B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00001A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00001900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00001800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00001700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00001600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00001500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00001400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00001300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00001200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00001100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00001000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_SW 0x00000B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1 0x00000A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0 0x00000900 +#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE 0x00000700 +#define AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV 0x00000500 +#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV 0x00000400 +#define AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET 0x00000300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00000200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00000100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00000000 + +// Field: [5] START_POL +// +// Polarity of start source. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// LOW TDC conversion starts when low level is detected. +// HIGH TDC conversion starts when high level is detected. +#define AUX_TDC_TRIGSRC_START_POL 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_BITN 5 +#define AUX_TDC_TRIGSRC_START_POL_M 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_S 5 +#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 + +// Field: [4:0] START_SRC +// +// Select start source from the asynchronous AUX event bus. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// TDC_PRE Select TDC Prescaler event which is generated by +// configuration of PRECTL. +// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TDC_TRIGSRC_START_SRC_W 5 +#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000001F +#define AUX_TDC_TRIGSRC_START_SRC_S 0 +#define AUX_TDC_TRIGSRC_START_SRC_TDC_PRE 0x0000001F +#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000001E +#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000001D +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000001C +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000001B +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000001A +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x00000019 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x00000018 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x00000017 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000016 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000015 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000014 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000013 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000012 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000011 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000010 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x0000000F +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x0000000E +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x0000000D +#define AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU 0x0000000C +#define AUX_TDC_TRIGSRC_START_SRC_AON_SW 0x0000000B +#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX1 0x0000000A +#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX0 0x00000009 +#define AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_TDC_TRIGSRC_START_SRC_ADC_DONE 0x00000007 +#define AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV 0x00000005 +#define AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV 0x00000004 +#define AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET 0x00000003 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x00000002 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x00000001 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNT +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. +// +// Read CNT to get the remaining number of stop events to ignore during a TDC +// measurement. +// +// Write CNT to update the remaining number of stop events to ignore during a +// TDC measurement. The TDC measurement ignores updates of CNT if there are no +// more stop events left to ignore. +// +// When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the +// start of the measurement. +#define AUX_TDC_TRIGCNT_CNT_W 16 +#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNT_CNT_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNTLOAD +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. +// +// To measure frequency of an event source: +// - Set start event equal to stop event. +// - Set CNT to number of periods to measure. Both 0 and 1 values measures a +// single event source period. +// +// To measure pulse width of an event source: +// - Set start event source equal to stop event source. +// - Select different polarity for start and stop event. +// - Set CNT to 0. +// +// To measure time from the start event to the Nth stop event when N > 1: +// - Select different start and stop event source. +// - Set CNT to (N-1). +// +// See the Technical Reference Manual for event timing requirements. +// +// When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start +// of the measurement. +#define AUX_TDC_TRIGCNTLOAD_CNT_W 16 +#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNTLOAD_CNT_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNTCFG +// +//***************************************************************************** +// Field: [0] EN +// +// Enable stop-counter. +// +// 0: Disable stop-counter. +// 1: Enable stop-counter. +// +// Change only while STAT.STATE is IDLE. +#define AUX_TDC_TRIGCNTCFG_EN 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_BITN 0 +#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_PRECTL +// +//***************************************************************************** +// Field: [7] RESET_N +// +// Prescaler reset. +// +// 0: Reset prescaler. +// 1: Release reset of prescaler. +// +// AUX_TDC_PRE event becomes 0 when you reset the prescaler. +#define AUX_TDC_PRECTL_RESET_N 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_BITN 7 +#define AUX_TDC_PRECTL_RESET_N_M 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_S 7 + +// Field: [6] RATIO +// +// Prescaler ratio. +// +// This controls how often the AUX_TDC_PRE event is generated by the prescaler. +// ENUMs: +// DIV64 Prescaler divides input by 64. +// +// AUX_TDC_PRE event has a +// rising edge for every 64 rising edges of the +// input. AUX_TDC_PRE event toggles on every 32nd +// rising edge of the input. +// DIV16 Prescaler divides input by 16. +// +// AUX_TDC_PRE event has a +// rising edge for every 16 rising edges of the +// input. AUX_TDC_PRE event toggles on every 8th +// rising edge of the input. +#define AUX_TDC_PRECTL_RATIO 0x00000040 +#define AUX_TDC_PRECTL_RATIO_BITN 6 +#define AUX_TDC_PRECTL_RATIO_M 0x00000040 +#define AUX_TDC_PRECTL_RATIO_S 6 +#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 +#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 + +// Field: [4:0] SRC +// +// Prescaler event source. +// +// Select an event from the asynchronous AUX event bus to connect to the +// prescaler input. +// +// Configure only while RESET_N is 0. +// ENUMs: +// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ +// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TDC_PRECTL_SRC_W 5 +#define AUX_TDC_PRECTL_SRC_M 0x0000001F +#define AUX_TDC_PRECTL_SRC_S 0 +#define AUX_TDC_PRECTL_SRC_ADC_IRQ 0x0000001F +#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000001E +#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000001D +#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000001C +#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000001B +#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000001A +#define AUX_TDC_PRECTL_SRC_AUXIO12 0x00000019 +#define AUX_TDC_PRECTL_SRC_AUXIO11 0x00000018 +#define AUX_TDC_PRECTL_SRC_AUXIO10 0x00000017 +#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000016 +#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000015 +#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000014 +#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000013 +#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000012 +#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000011 +#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000010 +#define AUX_TDC_PRECTL_SRC_AUXIO2 0x0000000F +#define AUX_TDC_PRECTL_SRC_AUXIO1 0x0000000E +#define AUX_TDC_PRECTL_SRC_AUXIO0 0x0000000D +#define AUX_TDC_PRECTL_SRC_AON_PROG_WU 0x0000000C +#define AUX_TDC_PRECTL_SRC_AON_SW 0x0000000B +#define AUX_TDC_PRECTL_SRC_OBSMUX1 0x0000000A +#define AUX_TDC_PRECTL_SRC_OBSMUX0 0x00000009 +#define AUX_TDC_PRECTL_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_TDC_PRECTL_SRC_ADC_DONE 0x00000007 +#define AUX_TDC_PRECTL_SRC_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_TDC_PRECTL_SRC_TIMER1_EV 0x00000005 +#define AUX_TDC_PRECTL_SRC_TIMER0_EV 0x00000004 +#define AUX_TDC_PRECTL_SRC_ISRC_RESET 0x00000003 +#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x00000002 +#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x00000001 +#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_PRECNT +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Prescaler counter value. +// +// Write a value to CNT to capture the value of the 16-bit prescaler counter +// into CNT. Read CNT to get the captured value. +// +// The read value gets 1 LSB uncertainty if the event source level rises when +// you release the reset. +// +// You must capture the prescaler counter value when the event source level is +// stable, either high or low: +// - Disable AUX I/O input buffer to clamp AUXIO event low. +// - Disable COMPA to clamp AUX_COMPA event low. +// The read value can in general get 1 LSB uncertainty when you gate the event +// source asynchronously. +// +// Please note the following: +// - The prescaler counter is reset to 2 by PRECTL.RESET_N. +// - The captured value is 2 when the number of rising edges on prescaler input +// is less than 3. Otherwise, captured value equals number of event pulses - 1. +#define AUX_TDC_PRECNT_CNT_W 16 +#define AUX_TDC_PRECNT_CNT_M 0x0000FFFF +#define AUX_TDC_PRECNT_CNT_S 0 + + +#endif // __AUX_TDC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_timer.h new file mode 100644 index 0000000..ad0aa1e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_timer.h @@ -0,0 +1,447 @@ +/****************************************************************************** +* Filename: hw_aux_timer_h +* Revised: 2017-05-22 18:50:33 +0200 (Mon, 22 May 2017) +* Revision: 49040 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_TIMER_H__ +#define __HW_AUX_TIMER_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_TIMER component +// +//***************************************************************************** +// Timer 0 Configuration +#define AUX_TIMER_O_T0CFG 0x00000000 + +// Timer 1 Configuration +#define AUX_TIMER_O_T1CFG 0x00000004 + +// Timer 0 Control +#define AUX_TIMER_O_T0CTL 0x00000008 + +// Timer 0 Target +#define AUX_TIMER_O_T0TARGET 0x0000000C + +// Timer 1 Target +#define AUX_TIMER_O_T1TARGET 0x00000010 + +// Timer 1 Control +#define AUX_TIMER_O_T1CTL 0x00000014 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T0CFG +// +//***************************************************************************** +// Field: [13] TICK_SRC_POL +// +// Tick source polarity for Timer 0. +// ENUMs: +// FALL Count on falling edges of TICK_SRC. +// RISE Count on rising edges of TICK_SRC. +#define AUX_TIMER_T0CFG_TICK_SRC_POL 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_BITN 13 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_M 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_S 13 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_FALL 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_RISE 0x00000000 + +// Field: [12:8] TICK_SRC +// +// Select Timer 0 tick source from the synchronous event bus. +// ENUMs: +// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ +// MCU_EVENT AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// RTC_4KHZ AON_RTC:SUBSEC.VALUE bit 19. +// AON_RTC:CTL.RTC_4KHZ_EN enables this event. +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TDC_DONE AUX_EVCTL:EVSTAT0.TDC_DONE +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TIMER_T0CFG_TICK_SRC_W 5 +#define AUX_TIMER_T0CFG_TICK_SRC_M 0x00001F00 +#define AUX_TIMER_T0CFG_TICK_SRC_S 8 +#define AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ 0x00001F00 +#define AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT 0x00001E00 +#define AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF 0x00001D00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO15 0x00001C00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO14 0x00001B00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO13 0x00001A00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO12 0x00001900 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO11 0x00001800 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO10 0x00001700 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO9 0x00001600 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO8 0x00001500 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO7 0x00001400 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO6 0x00001300 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO5 0x00001200 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO4 0x00001100 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO3 0x00001000 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO2 0x00000F00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO1 0x00000E00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO0 0x00000D00 +#define AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TIMER_T0CFG_TICK_SRC_AON_SW 0x00000B00 +#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1 0x00000A00 +#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0 0x00000900 +#define AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ 0x00000800 +#define AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE 0x00000700 +#define AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV 0x00000500 +#define AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE 0x00000300 +#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB 0x00000200 +#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA 0x00000100 +#define AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV 0x00000000 + +// Field: [7:4] PRE +// +// Prescaler division ratio is 2^PRE: +// +// 0x0: Divide by 1. +// 0x1: Divide by 2. +// 0x2: Divide by 4. +// ... +// 0xF: Divide by 32,768. +#define AUX_TIMER_T0CFG_PRE_W 4 +#define AUX_TIMER_T0CFG_PRE_M 0x000000F0 +#define AUX_TIMER_T0CFG_PRE_S 4 + +// Field: [1] MODE +// +// Timer 0 mode. +// +// Configure source for Timer 0 prescaler. +// ENUMs: +// TICK Use event set by TICK_SRC as source for prescaler. +// CLK Use AUX clock as source for prescaler. +#define AUX_TIMER_T0CFG_MODE 0x00000002 +#define AUX_TIMER_T0CFG_MODE_BITN 1 +#define AUX_TIMER_T0CFG_MODE_M 0x00000002 +#define AUX_TIMER_T0CFG_MODE_S 1 +#define AUX_TIMER_T0CFG_MODE_TICK 0x00000002 +#define AUX_TIMER_T0CFG_MODE_CLK 0x00000000 + +// Field: [0] RELOAD +// +// Timer 0 reload mode. +// ENUMs: +// CONT Continuous mode. +// +// Timer 0 restarts when the +// counter value becomes equal to or greater than +// ( T0TARGET.VALUE - 1). +// MAN Manual mode. +// +// Timer 0 stops and +// T0CTL.EN becomes 0 when the counter value +// becomes equal to or greater than +// T0TARGET.VALUE. +#define AUX_TIMER_T0CFG_RELOAD 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_BITN 0 +#define AUX_TIMER_T0CFG_RELOAD_M 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_S 0 +#define AUX_TIMER_T0CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_MAN 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T1CFG +// +//***************************************************************************** +// Field: [13] TICK_SRC_POL +// +// Tick source polarity for Timer 1. +// ENUMs: +// FALL Count on falling edges of TICK_SRC. +// RISE Count on rising edges of TICK_SRC. +#define AUX_TIMER_T1CFG_TICK_SRC_POL 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_BITN 13 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_M 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_S 13 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_FALL 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_RISE 0x00000000 + +// Field: [12:8] TICK_SRC +// +// Select Timer 1 tick source from the synchronous event bus. +// ENUMs: +// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ +// MCU_EVENT AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// RTC_4KHZ AON_RTC:SUBSEC.VALUE bit 19. +// AON_RTC:CTL.RTC_4KHZ_EN enables this event. +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// TDC_DONE AUX_EVCTL:EVSTAT0.TDC_DONE +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TIMER_T1CFG_TICK_SRC_W 5 +#define AUX_TIMER_T1CFG_TICK_SRC_M 0x00001F00 +#define AUX_TIMER_T1CFG_TICK_SRC_S 8 +#define AUX_TIMER_T1CFG_TICK_SRC_ADC_IRQ 0x00001F00 +#define AUX_TIMER_T1CFG_TICK_SRC_MCU_EVENT 0x00001E00 +#define AUX_TIMER_T1CFG_TICK_SRC_ACLK_REF 0x00001D00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO15 0x00001C00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO14 0x00001B00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO13 0x00001A00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO12 0x00001900 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO11 0x00001800 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO10 0x00001700 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO9 0x00001600 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO8 0x00001500 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO7 0x00001400 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO6 0x00001300 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO5 0x00001200 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO4 0x00001100 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO3 0x00001000 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO2 0x00000F00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO1 0x00000E00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO0 0x00000D00 +#define AUX_TIMER_T1CFG_TICK_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TIMER_T1CFG_TICK_SRC_AON_SW 0x00000B00 +#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX1 0x00000A00 +#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX0 0x00000900 +#define AUX_TIMER_T1CFG_TICK_SRC_RTC_4KHZ 0x00000800 +#define AUX_TIMER_T1CFG_TICK_SRC_ADC_DONE 0x00000700 +#define AUX_TIMER_T1CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV 0x00000400 +#define AUX_TIMER_T1CFG_TICK_SRC_TDC_DONE 0x00000300 +#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPB 0x00000200 +#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPA 0x00000100 +#define AUX_TIMER_T1CFG_TICK_SRC_RTC_CH2_EV 0x00000000 + +// Field: [7:4] PRE +// +// Prescaler division ratio is 2^PRE: +// +// 0x0: Divide by 1. +// 0x1: Divide by 2. +// 0x2: Divide by 4. +// ... +// 0xF: Divide by 32,768. +#define AUX_TIMER_T1CFG_PRE_W 4 +#define AUX_TIMER_T1CFG_PRE_M 0x000000F0 +#define AUX_TIMER_T1CFG_PRE_S 4 + +// Field: [1] MODE +// +// Timer 1 mode. +// +// Configure source for Timer 1 prescaler. +// ENUMs: +// TICK Use event set by TICK_SRC as source for prescaler. +// CLK Use AUX clock as source for prescaler. +#define AUX_TIMER_T1CFG_MODE 0x00000002 +#define AUX_TIMER_T1CFG_MODE_BITN 1 +#define AUX_TIMER_T1CFG_MODE_M 0x00000002 +#define AUX_TIMER_T1CFG_MODE_S 1 +#define AUX_TIMER_T1CFG_MODE_TICK 0x00000002 +#define AUX_TIMER_T1CFG_MODE_CLK 0x00000000 + +// Field: [0] RELOAD +// +// Timer 1 reload mode. +// ENUMs: +// CONT Continuous mode. +// +// Timer 1 restarts when the +// counter value becomes equal to or greater than +// ( T1TARGET.VALUE - 1). +// MAN Manual mode. +// +// Timer 1 stops and +// T1CTL.EN becomes 0 when the counter value +// becomes equal to or greater than +// T1TARGET.VALUE. +#define AUX_TIMER_T1CFG_RELOAD 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_BITN 0 +#define AUX_TIMER_T1CFG_RELOAD_M 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_S 0 +#define AUX_TIMER_T1CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_MAN 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T0CTL +// +//***************************************************************************** +// Field: [0] EN +// +// Timer 0 enable. +// +// 0: Disable Timer 0. +// 1: Enable Timer 0. +// +// The counter restarts from 0 when you enable Timer 0. +#define AUX_TIMER_T0CTL_EN 0x00000001 +#define AUX_TIMER_T0CTL_EN_BITN 0 +#define AUX_TIMER_T0CTL_EN_M 0x00000001 +#define AUX_TIMER_T0CTL_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T0TARGET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Timer 0 target value. +// +// Manual Reload Mode: +// - Timer 0 increments until the counter value becomes equal to or greater +// than VALUE. +// - AUX_TIMER0_EV pulses high for 1 AUX clock period when the counter value is +// equal to or greater than VALUE. +// +// Note: When VALUE is 0, Timer 0 counts to 1. AUX_TIMER0_EV pulses high for 1 +// AUX clock period. +// +// Continuous Reload Mode: +// - Timer 0 increments until the counter value becomes equal to or greater +// than ( VALUE - 1), then restarts from 0. +// - AUX_TIMER0_EV pulses high for 1 AUX clock period when the counter value is +// 0, except for when you enable the timer. +// +// Note: When VALUE is less than 2, Timer 0 counter value remains 0. +// AUX_TIMER0_EV goes high and remains high 1 AUX clock period after you enable +// the timer. +// +// +// It is allowed to update the VALUE while the timer runs. +#define AUX_TIMER_T0TARGET_VALUE_W 16 +#define AUX_TIMER_T0TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER_T0TARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T1TARGET +// +//***************************************************************************** +// Field: [7:0] VALUE +// +// Timer 1 target value. +// +// Manual Reload Mode: +// - Timer 1 increments until the counter value becomes equal to or greater +// than VALUE. +// - AUX_TIMER1_EV pulses high for 1 AUX clock period when the counter value is +// equal to or greater than VALUE. +// +// Note: When VALUE is 0, Timer 1 counts to 1. AUX_TIMER1_EV pulses high for 1 +// AUX clock period. +// +// Continuous Reload Mode: +// - Timer 1 increments until the counter value becomes equal to or greater +// than ( VALUE - 1), then restarts from 0. +// - AUX_TIMER1_EV pulses high for 1 AUX clock period when the counter value is +// 0, except for when you enable the timer. +// +// Note: When VALUE is less than 2, Timer 1 counter value remains 0. +// AUX_TIMER1_EV goes high and remains high 1 AUX clock period after you enable +// the timer. +// +// +// It is allowed to update the VALUE while the timer runs. +#define AUX_TIMER_T1TARGET_VALUE_W 8 +#define AUX_TIMER_T1TARGET_VALUE_M 0x000000FF +#define AUX_TIMER_T1TARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T1CTL +// +//***************************************************************************** +// Field: [0] EN +// +// Timer 1 enable. +// +// 0: Disable Timer 1. +// 1: Enable Timer 1. +// +// The counter restarts from 0 when you enable Timer 1. +#define AUX_TIMER_T1CTL_EN 0x00000001 +#define AUX_TIMER_T1CTL_EN_BITN 0 +#define AUX_TIMER_T1CTL_EN_M 0x00000001 +#define AUX_TIMER_T1CTL_EN_S 0 + + +#endif // __AUX_TIMER__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_wuc.h new file mode 100644 index 0000000..f7dd3b0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_wuc.h @@ -0,0 +1,705 @@ +/****************************************************************************** +* Filename: hw_aux_wuc_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_WUC_H__ +#define __HW_AUX_WUC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_WUC component +// +//***************************************************************************** +// Module Clock Enable +#define AUX_WUC_O_MODCLKEN0 0x00000000 + +// Power Off Request +#define AUX_WUC_O_PWROFFREQ 0x00000004 + +// Power Down Request +#define AUX_WUC_O_PWRDWNREQ 0x00000008 + +// Power Down Acknowledgment +#define AUX_WUC_O_PWRDWNACK 0x0000000C + +// Low Frequency Clock Request +#define AUX_WUC_O_CLKLFREQ 0x00000010 + +// Low Frequency Clock Acknowledgment +#define AUX_WUC_O_CLKLFACK 0x00000014 + +// Wake-up Event Flags +#define AUX_WUC_O_WUEVFLAGS 0x00000028 + +// Wake-up Event Clear +#define AUX_WUC_O_WUEVCLR 0x0000002C + +// ADC Clock Control +#define AUX_WUC_O_ADCCLKCTL 0x00000030 + +// TDC Clock Control +#define AUX_WUC_O_TDCCLKCTL 0x00000034 + +// Reference Clock Control +#define AUX_WUC_O_REFCLKCTL 0x00000038 + +// Real Time Counter Sub Second Increment 0 +#define AUX_WUC_O_RTCSUBSECINC0 0x0000003C + +// Real Time Counter Sub Second Increment 1 +#define AUX_WUC_O_RTCSUBSECINC1 0x00000040 + +// Real Time Counter Sub Second Increment Control +#define AUX_WUC_O_RTCSUBSECINCCTL 0x00000044 + +// MCU Bus Control +#define AUX_WUC_O_MCUBUSCTL 0x00000048 + +// MCU Bus Status +#define AUX_WUC_O_MCUBUSSTAT 0x0000004C + +// AON Domain Control Status +#define AUX_WUC_O_AONCTLSTAT 0x00000050 + +// AUX Input Output Latch +#define AUX_WUC_O_AUXIOLATCH 0x00000054 + +// Module Clock Enable 1 +#define AUX_WUC_O_MODCLKEN1 0x0000005C + +//***************************************************************************** +// +// Register: AUX_WUC_O_MODCLKEN0 +// +//***************************************************************************** +// Field: [7] AUX_ADI4 +// +// Enables (1) or disables (0) clock for AUX_ADI4. +// ENUMs: +// EN System CPU has requested clock for AUX_ADI4 +// DIS System CPU has not requested clock for AUX_ADI4 +#define AUX_WUC_MODCLKEN0_AUX_ADI4 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_BITN 7 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_M 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_S 7 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_EN 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_DIS 0x00000000 + +// Field: [6] AUX_DDI0_OSC +// +// Enables (1) or disables (0) clock for AUX_DDI0_OSC. +// ENUMs: +// EN System CPU has requested clock for AUX_DDI0_OSC +// DIS System CPU has not requested clock for +// AUX_DDI0_OSC +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_BITN 6 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_M 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_S 6 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_DIS 0x00000000 + +// Field: [5] TDC +// +// Enables (1) or disables (0) clock for AUX_TDCIF. +// +// Note that the TDC counter and reference clock sources must be requested +// separately using TDCCLKCTL and REFCLKCTL, respectively. +// ENUMs: +// EN System CPU has requested clock for TDC +// DIS System CPU has not requested clock for TDC +#define AUX_WUC_MODCLKEN0_TDC 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_BITN 5 +#define AUX_WUC_MODCLKEN0_TDC_M 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_S 5 +#define AUX_WUC_MODCLKEN0_TDC_EN 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_DIS 0x00000000 + +// Field: [4] ANAIF +// +// Enables (1) or disables (0) clock for AUX_ANAIF. +// +// Note that the ADC internal clock must be requested separately using +// ADCCLKCTL. +// ENUMs: +// EN System CPU has requested clock for ANAIF +// DIS System CPU has not requested clock for ANAIF +#define AUX_WUC_MODCLKEN0_ANAIF 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_BITN 4 +#define AUX_WUC_MODCLKEN0_ANAIF_M 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_S 4 +#define AUX_WUC_MODCLKEN0_ANAIF_EN 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_DIS 0x00000000 + +// Field: [3] TIMER +// +// Enables (1) or disables (0) clock for AUX_TIMER. +// ENUMs: +// EN System CPU has requested clock for TIMER +// DIS System CPU has not requested clock for TIMER +#define AUX_WUC_MODCLKEN0_TIMER 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_BITN 3 +#define AUX_WUC_MODCLKEN0_TIMER_M 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_S 3 +#define AUX_WUC_MODCLKEN0_TIMER_EN 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_DIS 0x00000000 + +// Field: [2] AIODIO1 +// +// Enables (1) or disables (0) clock for AUX_AIODIO1. +// ENUMs: +// EN System CPU has requested clock for AIODIO1 +// DIS System CPU has not requested clock for AIODIO1 +#define AUX_WUC_MODCLKEN0_AIODIO1 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_BITN 2 +#define AUX_WUC_MODCLKEN0_AIODIO1_M 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_S 2 +#define AUX_WUC_MODCLKEN0_AIODIO1_EN 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_DIS 0x00000000 + +// Field: [1] AIODIO0 +// +// Enables (1) or disables (0) clock for AUX_AIODIO0. +// ENUMs: +// EN System CPU has requested clock for AIODIO0 +// DIS System CPU has not requested clock for AIODIO0 +#define AUX_WUC_MODCLKEN0_AIODIO0 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_BITN 1 +#define AUX_WUC_MODCLKEN0_AIODIO0_M 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_S 1 +#define AUX_WUC_MODCLKEN0_AIODIO0_EN 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_DIS 0x00000000 + +// Field: [0] SMPH +// +// Enables (1) or disables (0) clock for AUX_SMPH. +// ENUMs: +// EN System CPU has requested clock for SMPH +// DIS System CPU has not requested clock for SMPH +#define AUX_WUC_MODCLKEN0_SMPH 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_BITN 0 +#define AUX_WUC_MODCLKEN0_SMPH_M 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_S 0 +#define AUX_WUC_MODCLKEN0_SMPH_EN 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_WUC_O_PWROFFREQ +// +//***************************************************************************** +// Field: [0] REQ +// +// Power off request +// +// 0: No action +// 1: Request to power down AUX. Once set, this bit shall not be cleared. The +// bit will be reset again when AUX is powered up again. +// +// The request will only happen if AONCTLSTAT.AUX_FORCE_ON = 0 and +// MCUBUSSTAT.DISCONNECTED=1. +#define AUX_WUC_PWROFFREQ_REQ 0x00000001 +#define AUX_WUC_PWROFFREQ_REQ_BITN 0 +#define AUX_WUC_PWROFFREQ_REQ_M 0x00000001 +#define AUX_WUC_PWROFFREQ_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_PWRDWNREQ +// +//***************************************************************************** +// Field: [0] REQ +// +// Power down request +// +// 0: Request for system to be in active mode +// 1: Request for system to be in power down mode +// +// When REQ is 1 one shall assume that the system is in power down, and that +// current supply is limited. When setting REQ = 0, one shall assume that the +// system is in power down until PWRDWNACK.ACK = 0 +#define AUX_WUC_PWRDWNREQ_REQ 0x00000001 +#define AUX_WUC_PWRDWNREQ_REQ_BITN 0 +#define AUX_WUC_PWRDWNREQ_REQ_M 0x00000001 +#define AUX_WUC_PWRDWNREQ_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_PWRDWNACK +// +//***************************************************************************** +// Field: [0] ACK +// +// Power down acknowledgment. Indicates whether the power down request given by +// PWRDWNREQ.REQ is captured by the AON domain or not +// +// 0: AUX can assume that the system is in active mode +// 1: The request for power down is acknowledged and the AUX must act like the +// system is in power down mode and power supply is limited +// +// The system CPU cannot use this bit since the bus bridge between MCU domain +// and AUX domain is always disconnected when this bit is set. For AUX_SCE use +// only +#define AUX_WUC_PWRDWNACK_ACK 0x00000001 +#define AUX_WUC_PWRDWNACK_ACK_BITN 0 +#define AUX_WUC_PWRDWNACK_ACK_M 0x00000001 +#define AUX_WUC_PWRDWNACK_ACK_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_CLKLFREQ +// +//***************************************************************************** +// Field: [0] REQ +// +// Low frequency request +// +// 0: Request clock frequency to be controlled by AON_WUC:AUXCLK and the system +// state +// 1: Request low frequency clock SCLK_LF as the clock source for AUX +// +// This bit must not be modified unless CLKLFACK.ACK matches the current value +#define AUX_WUC_CLKLFREQ_REQ 0x00000001 +#define AUX_WUC_CLKLFREQ_REQ_BITN 0 +#define AUX_WUC_CLKLFREQ_REQ_M 0x00000001 +#define AUX_WUC_CLKLFREQ_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_CLKLFACK +// +//***************************************************************************** +// Field: [0] ACK +// +// Acknowledgment of CLKLFREQ.REQ +// +// 0: Acknowledgement that clock frequency is controlled by AON_WUC:AUXCLK and +// the system state +// 1: Acknowledgement that the low frequency clock SCLK_LF is the clock source +// for AUX +#define AUX_WUC_CLKLFACK_ACK 0x00000001 +#define AUX_WUC_CLKLFACK_ACK_BITN 0 +#define AUX_WUC_CLKLFACK_ACK_M 0x00000001 +#define AUX_WUC_CLKLFACK_ACK_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_WUEVFLAGS +// +//***************************************************************************** +// Field: [2] AON_RTC_CH2 +// +// Indicates pending event from AON_RTC_CH2 compare. Note that this flag will +// be set whenever the AON_RTC_CH2 event happens, but that does not mean that +// this event is a wake-up event. To make the AON_RTC_CH2 a wake-up event for +// the AUX domain configure it as a wake-up event in AON_EVENT:AUXWUSEL.WU0_EV, +// AON_EVENT:AUXWUSEL.WU1_EV or AON_EVENT:AUXWUSEL.WU2_EV. +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2 0x00000004 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_BITN 2 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_M 0x00000004 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_S 2 + +// Field: [1] AON_SW +// +// Indicates pending event triggered by system CPU writing a 1 to +// AON_WUC:AUXCTL.SWEV. +#define AUX_WUC_WUEVFLAGS_AON_SW 0x00000002 +#define AUX_WUC_WUEVFLAGS_AON_SW_BITN 1 +#define AUX_WUC_WUEVFLAGS_AON_SW_M 0x00000002 +#define AUX_WUC_WUEVFLAGS_AON_SW_S 1 + +// Field: [0] AON_PROG_WU +// +// Indicates pending event triggered by the sources selected in +// AON_EVENT:AUXWUSEL.WU0_EV, AON_EVENT:AUXWUSEL.WU1_EV and +// AON_EVENT:AUXWUSEL.WU2_EV. +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU 0x00000001 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_BITN 0 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_M 0x00000001 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_WUEVCLR +// +//***************************************************************************** +// Field: [2] AON_RTC_CH2 +// +// Set to clear the WUEVFLAGS.AON_RTC_CH2 wake-up event. Note that if RTC +// channel 2 is also set as source for AON_PROG_WU this field can also clear +// WUEVFLAGS.AON_PROG_WU +// +// This bit must remain set until WUEVFLAGS.AON_RTC_CH2 returns to 0. +#define AUX_WUC_WUEVCLR_AON_RTC_CH2 0x00000004 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_BITN 2 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_M 0x00000004 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_S 2 + +// Field: [1] AON_SW +// +// Set to clear the WUEVFLAGS.AON_SW wake-up event. +// +// This bit must remain set until WUEVFLAGS.AON_SW returns to 0. +#define AUX_WUC_WUEVCLR_AON_SW 0x00000002 +#define AUX_WUC_WUEVCLR_AON_SW_BITN 1 +#define AUX_WUC_WUEVCLR_AON_SW_M 0x00000002 +#define AUX_WUC_WUEVCLR_AON_SW_S 1 + +// Field: [0] AON_PROG_WU +// +// Set to clear the WUEVFLAGS.AON_PROG_WU wake-up event. Note only if an IO +// event is selected as wake-up event, is it possible to use this field to +// clear the source. Other sources cannot be cleared using this field. +// +// The IO pin needs to be assigned to AUX in the IOC and the input enable for +// the pin needs to be set in AIODIO0 or AIODIO1 for this clearing to take +// effect. +// +// This bit must remain set until WUEVFLAGS.AON_PROG_WU returns to 0. +#define AUX_WUC_WUEVCLR_AON_PROG_WU 0x00000001 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_BITN 0 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_M 0x00000001 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_ADCCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// Acknowledges the last value written to REQ. +#define AUX_WUC_ADCCLKCTL_ACK 0x00000002 +#define AUX_WUC_ADCCLKCTL_ACK_BITN 1 +#define AUX_WUC_ADCCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_ADCCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// Enables(1) or disables (0) the ADC internal clock. +// +// This bit must not be modified unless ACK matches the current value. +#define AUX_WUC_ADCCLKCTL_REQ 0x00000001 +#define AUX_WUC_ADCCLKCTL_REQ_BITN 0 +#define AUX_WUC_ADCCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_ADCCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_TDCCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// Acknowledges the last value written to REQ. +#define AUX_WUC_TDCCLKCTL_ACK 0x00000002 +#define AUX_WUC_TDCCLKCTL_ACK_BITN 1 +#define AUX_WUC_TDCCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_TDCCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// Enables(1) or disables (0) the TDC counter clock source. +// +// This bit must not be modified unless ACK matches the current value. +#define AUX_WUC_TDCCLKCTL_REQ 0x00000001 +#define AUX_WUC_TDCCLKCTL_REQ_BITN 0 +#define AUX_WUC_TDCCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_TDCCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_REFCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// Acknowledges the last value written to REQ. +#define AUX_WUC_REFCLKCTL_ACK 0x00000002 +#define AUX_WUC_REFCLKCTL_ACK_BITN 1 +#define AUX_WUC_REFCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_REFCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// Enables(1) or disables (0) the TDC reference clock source. +// +// This bit must not be modified unless ACK matches the current value. +#define AUX_WUC_REFCLKCTL_REQ 0x00000001 +#define AUX_WUC_REFCLKCTL_REQ_BITN 0 +#define AUX_WUC_REFCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_REFCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_RTCSUBSECINC0 +// +//***************************************************************************** +// Field: [15:0] INC15_0 +// +// Bits 15:0 of the RTC sub-second increment value. +#define AUX_WUC_RTCSUBSECINC0_INC15_0_W 16 +#define AUX_WUC_RTCSUBSECINC0_INC15_0_M 0x0000FFFF +#define AUX_WUC_RTCSUBSECINC0_INC15_0_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_RTCSUBSECINC1 +// +//***************************************************************************** +// Field: [7:0] INC23_16 +// +// Bits 23:16 of the RTC sub-second increment value. +#define AUX_WUC_RTCSUBSECINC1_INC23_16_W 8 +#define AUX_WUC_RTCSUBSECINC1_INC23_16_M 0x000000FF +#define AUX_WUC_RTCSUBSECINC1_INC23_16_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_RTCSUBSECINCCTL +// +//***************************************************************************** +// Field: [1] UPD_ACK +// +// Acknowledgment of the UPD_REQ. +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK 0x00000002 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN 1 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_S 1 + +// Field: [0] UPD_REQ +// +// Signal that a new real time counter sub second increment value is available +// +// 0: New sub second increment is not available +// 1: New sub second increment is available +// +// This bit must not be modified unless UPD_ACK matches the current value. +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ 0x00000001 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_BITN 0 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_MCUBUSCTL +// +//***************************************************************************** +// Field: [0] DISCONNECT_REQ +// +// Requests the AUX domain bus to be disconnected from the MCU domain bus. The +// request has no effect when AON_WUC:AUX_CTL.AUX_FORCE_ON is set. +// +// The disconnection status can be monitored through MCUBUSSTAT. Note however +// that this register cannot be read by the system CPU while disconnected. +// +// It is recommended that this bit is set and remains set after initial +// power-up, and that the system CPU uses AON_WUC:AUX_CTL.AUX_FORCE_ON to +// connect/disconnect the bus. +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ 0x00000001 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_BITN 0 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_M 0x00000001 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_MCUBUSSTAT +// +//***************************************************************************** +// Field: [1] DISCONNECTED +// +// Indicates whether the AUX domain and MCU domain buses are currently +// disconnected (1) or connected (0). +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED 0x00000002 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_BITN 1 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_M 0x00000002 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_S 1 + +// Field: [0] DISCONNECT_ACK +// +// Acknowledges reception of the bus disconnection request, by matching the +// value of MCUBUSCTL.DISCONNECT_REQ. +// +// Note that if AON_WUC:AUXCTL.AUX_FORCE_ON = 1 a reconnect to the MCU domain +// bus will be made regardless of the state of MCUBUSCTL.DISCONNECT_REQ +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK 0x00000001 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_BITN 0 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_M 0x00000001 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_AONCTLSTAT +// +//***************************************************************************** +// Field: [1] AUX_FORCE_ON +// +// Status of AON_WUC:AUX_CTL.AUX_FORCE_ON. +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON 0x00000002 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_BITN 1 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_M 0x00000002 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_S 1 + +// Field: [0] SCE_RUN_EN +// +// Status of AON_WUC:AUX_CTL.SCE_RUN_EN. +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN 0x00000001 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_BITN 0 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_M 0x00000001 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_AUXIOLATCH +// +//***************************************************************************** +// Field: [0] EN +// +// Opens (1) or closes (0) the AUX_AIODIO0/AUX_AIODIO1 signal latching. +// +// At startup, set EN = TRANSP before configuring AUX_AIODIO0/AUX_AIODIO1 and +// subsequently selecting AUX mode in the AON_IOC. +// +// When powering off the AUX domain (using PWROFFREQ.REQ), set EN = STATIC in +// advance preserve the current state (mode and output value) of the I/O pins. +// ENUMs: +// TRANSP Latches are transparent ( open ) +// STATIC Latches are static ( closed ) +#define AUX_WUC_AUXIOLATCH_EN 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_BITN 0 +#define AUX_WUC_AUXIOLATCH_EN_M 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_S 0 +#define AUX_WUC_AUXIOLATCH_EN_TRANSP 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_STATIC 0x00000000 + +//***************************************************************************** +// +// Register: AUX_WUC_O_MODCLKEN1 +// +//***************************************************************************** +// Field: [7] AUX_ADI4 +// +// Enables (1) or disables (0) clock for AUX_ADI4. +// ENUMs: +// EN AUX_SCE has requested clock for AUX_ADI4 +// DIS AUX_SCE has not requested clock for AUX_ADI4 +#define AUX_WUC_MODCLKEN1_AUX_ADI4 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_BITN 7 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_M 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_S 7 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_EN 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_DIS 0x00000000 + +// Field: [6] AUX_DDI0_OSC +// +// Enables (1) or disables (0) clock for AUX_DDI0_OSC. +// ENUMs: +// EN AUX_SCE has requested clock for AUX_DDI0_OSC +// DIS AUX_SCE has not requested clock for AUX_DDI0_OSC +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_BITN 6 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_M 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_S 6 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_EN 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_DIS 0x00000000 + +// Field: [4] ANAIF +// +// Enables (1) or disables (0) clock for AUX_ANAIF. +// ENUMs: +// EN AUX_SCE has requested clock for ANAIF +// DIS AUX_SCE has not requested clock for ANAIF +#define AUX_WUC_MODCLKEN1_ANAIF 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_BITN 4 +#define AUX_WUC_MODCLKEN1_ANAIF_M 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_S 4 +#define AUX_WUC_MODCLKEN1_ANAIF_EN 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_DIS 0x00000000 + +// Field: [3] TIMER +// +// Enables (1) or disables (0) clock for AUX_TIMER. +// ENUMs: +// EN AUX_SCE has requested clock for TIMER +// DIS AUX_SCE has not requested clock for TIMER +#define AUX_WUC_MODCLKEN1_TIMER 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_BITN 3 +#define AUX_WUC_MODCLKEN1_TIMER_M 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_S 3 +#define AUX_WUC_MODCLKEN1_TIMER_EN 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_DIS 0x00000000 + +// Field: [2] AIODIO1 +// +// Enables (1) or disables (0) clock for AUX_AIODIO1. +// ENUMs: +// EN AUX_SCE has requested clock for AIODIO1 +// DIS AUX_SCE has not requested clock for AIODIO1 +#define AUX_WUC_MODCLKEN1_AIODIO1 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_BITN 2 +#define AUX_WUC_MODCLKEN1_AIODIO1_M 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_S 2 +#define AUX_WUC_MODCLKEN1_AIODIO1_EN 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_DIS 0x00000000 + +// Field: [1] AIODIO0 +// +// Enables (1) or disables (0) clock for AUX_AIODIO0. +// ENUMs: +// EN AUX_SCE has requested clock for AIODIO0 +// DIS AUX_SCE has not requested clock for AIODIO0 +#define AUX_WUC_MODCLKEN1_AIODIO0 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_BITN 1 +#define AUX_WUC_MODCLKEN1_AIODIO0_M 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_S 1 +#define AUX_WUC_MODCLKEN1_AIODIO0_EN 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_DIS 0x00000000 + +// Field: [0] SMPH +// +// Enables (1) or disables (0) clock for AUX_SMPH. +// ENUMs: +// EN AUX_SCE has requested clock for SMPH +// DIS AUX_SCE has not requested clock for SMPH +#define AUX_WUC_MODCLKEN1_SMPH 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_BITN 0 +#define AUX_WUC_MODCLKEN1_SMPH_M 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_S 0 +#define AUX_WUC_MODCLKEN1_SMPH_EN 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_DIS 0x00000000 + + +#endif // __AUX_WUC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg.h new file mode 100644 index 0000000..31b9b2a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg.h @@ -0,0 +1,1919 @@ +/****************************************************************************** +* Filename: hw_ccfg_h +* Revised: 2017-02-06 19:32:22 +0100 (Mon, 06 Feb 2017) +* Revision: 48408 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CCFG_H__ +#define __HW_CCFG_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CCFG component +// +//***************************************************************************** +// Extern LF clock configuration +#define CCFG_O_EXT_LF_CLK 0x00000FA8 + +// Mode Configuration 1 +#define CCFG_O_MODE_CONF_1 0x00000FAC + +// CCFG Size and Disable Flags +#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00000FB0 + +// Mode Configuration 0 +#define CCFG_O_MODE_CONF 0x00000FB4 + +// Voltage Load 0 +#define CCFG_O_VOLT_LOAD_0 0x00000FB8 + +// Voltage Load 1 +#define CCFG_O_VOLT_LOAD_1 0x00000FBC + +// Real Time Clock Offset +#define CCFG_O_RTC_OFFSET 0x00000FC0 + +// Frequency Offset +#define CCFG_O_FREQ_OFFSET 0x00000FC4 + +// IEEE MAC Address 0 +#define CCFG_O_IEEE_MAC_0 0x00000FC8 + +// IEEE MAC Address 1 +#define CCFG_O_IEEE_MAC_1 0x00000FCC + +// IEEE BLE Address 0 +#define CCFG_O_IEEE_BLE_0 0x00000FD0 + +// IEEE BLE Address 1 +#define CCFG_O_IEEE_BLE_1 0x00000FD4 + +// Bootloader Configuration +#define CCFG_O_BL_CONFIG 0x00000FD8 + +// Erase Configuration +#define CCFG_O_ERASE_CONF 0x00000FDC + +// TI Options +#define CCFG_O_CCFG_TI_OPTIONS 0x00000FE0 + +// Test Access Points Enable 0 +#define CCFG_O_CCFG_TAP_DAP_0 0x00000FE4 + +// Test Access Points Enable 1 +#define CCFG_O_CCFG_TAP_DAP_1 0x00000FE8 + +// Image Valid +#define CCFG_O_IMAGE_VALID_CONF 0x00000FEC + +// Protect Sectors 0-31 +#define CCFG_O_CCFG_PROT_31_0 0x00000FF0 + +// Protect Sectors 32-63 +#define CCFG_O_CCFG_PROT_63_32 0x00000FF4 + +// Protect Sectors 64-95 +#define CCFG_O_CCFG_PROT_95_64 0x00000FF8 + +// Protect Sectors 96-127 +#define CCFG_O_CCFG_PROT_127_96 0x00000FFC + +//***************************************************************************** +// +// Register: CCFG_O_EXT_LF_CLK +// +//***************************************************************************** +// Field: [31:24] DIO +// +// Unsigned integer, selecting the DIO to supply external 32kHz clock as +// SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO +// will be marked as reserved by the pin driver (TI-RTOS environment) and hence +// not selectable for other usage. +#define CCFG_EXT_LF_CLK_DIO_W 8 +#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 +#define CCFG_EXT_LF_CLK_DIO_S 24 + +// Field: [23:0] RTC_INCREMENT +// +// Unsigned integer, defining the input frequency of the external clock and is +// written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: +// EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: +// RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_MODE_CONF_1 +// +//***************************************************************************** +// Field: [23:20] ALT_DCDC_VMIN +// +// Minimum voltage for when DC/DC should be used if alternate DC/DC setting is +// enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). +// Voltage = (28 + ALT_DCDC_VMIN) / 16. +// 0: 1.75V +// 1: 1.8125V +// ... +// 14: 2.625V +// 15: 2.6875V +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 + +// Field: [19] ALT_DCDC_DITHER_EN +// +// Enable DC/DC dithering if alternate DC/DC setting is enabled +// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). +// 0: Dither disable +// 1: Dither enable +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 + +// Field: [18:16] ALT_DCDC_IPEAK +// +// Inductor peak current if alternate DC/DC setting is enabled +// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external +// inductor! +// Peak current = 31 + ( 4 * ALT_DCDC_IPEAK ) : +// 0: 31mA (min) +// ... +// 4: 47mA +// ... +// 7: 59mA (max) +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 + +// Field: [15:12] DELTA_IBIAS_INIT +// +// Signed delta value for IBIAS_INIT. Delta value only applies if +// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +// See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 + +// Field: [11:8] DELTA_IBIAS_OFFSET +// +// Signed delta value for IBIAS_OFFSET. Delta value only applies if +// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +// See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 + +// Field: [7:0] XOSC_MAX_START +// +// Unsigned value of maximum XOSC startup time (worst case) in units of 100us. +// Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 +#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF +#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_SIZE_AND_DIS_FLAGS +// +//***************************************************************************** +// Field: [31:16] SIZE_OF_CCFG +// +// Total size of CCFG in bytes. +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 + +// Field: [15:4] DISABLE_FLAGS +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 + +// Field: [3] DIS_TCXO +// +// Disable TCXO. +// 0: TCXO functionality enabled. +// 1: TCXO functionality disabled. +// Note: +// An external TCXO is required if DIS_TCXO = 0. +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 + +// Field: [2] DIS_GPRAM +// +// Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). +// 0: GPRAM is enabled and hence CACHE disabled. +// 1: GPRAM is disabled and instead CACHE is enabled (default). +// Notes: +// - Disabling CACHE will reduce CPU execution speed (up to 60%). +// - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if +// enabled. +// See: +// VIMS:CTL.MODE +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 + +// Field: [1] DIS_ALT_DCDC_SETTING +// +// Disable alternate DC/DC settings. +// 0: Enable alternate DC/DC settings. +// 1: Disable alternate DC/DC settings. +// See: +// MODE_CONF_1.ALT_DCDC_VMIN +// MODE_CONF_1.ALT_DCDC_DITHER_EN +// MODE_CONF_1.ALT_DCDC_IPEAK +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 + +// Field: [0] DIS_XOSC_OVR +// +// Disable XOSC override functionality. +// 0: Enable XOSC override functionality. +// 1: Disable XOSC override functionality. +// See: +// MODE_CONF_1.DELTA_IBIAS_INIT +// MODE_CONF_1.DELTA_IBIAS_OFFSET +// MODE_CONF_1.XOSC_MAX_START +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_MODE_CONF +// +//***************************************************************************** +// Field: [31:28] VDDR_TRIM_SLEEP_DELTA +// +// Signed delta value to apply to the +// VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H. +// 0x8 (-8) : Delta = -7 +// ... +// 0xF (-1) : Delta = 0 +// 0x0 (0) : Delta = +1 +// ... +// 0x7 (7) : Delta = +8 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 + +// Field: [27] DCDC_RECHARGE +// +// DC/DC during recharge in powerdown. +// 0: Use the DC/DC during recharge in powerdown. +// 1: Do not use the DC/DC during recharge in powerdown (default). +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 +#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 + +// Field: [26] DCDC_ACTIVE +// +// DC/DC in active mode. +// 0: Use the DC/DC during active mode. +// 1: Do not use the DC/DC during active mode (default). +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 +#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 + +// Field: [25] VDDR_EXT_LOAD +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 + +// Field: [24] VDDS_BOD_LEVEL +// +// VDDS BOD level. +// 0: VDDS BOD level is 2.0 V (necessary for maximum PA output power on +// CC13x0). +// 1: VDDS BOD level is 1.8 V (or 1.7 V for external regulator mode) (default). +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 + +// Field: [23:22] SCLK_LF_OPTION +// +// Select source for SCLK_LF. +// ENUMs: +// RCOSC_LF Low frequency RCOSC (default) +// XOSC_LF 32.768kHz low frequency XOSC +// EXTERNAL_LF External low frequency clock on DIO defined by +// EXT_LF_CLK.DIO. The RTC tick speed +// AON_RTC:SUBSECINC is updated to +// EXT_LF_CLK.RTC_INCREMENT (done in the +// trimDevice() xxWare boot function). External +// clock must always be running when the chip is +// in standby for VDDR recharge timing. +// XOSC_HF_DLF 31.25kHz clock derived from 24MHz XOSC (dividing +// by 768 in HW). The RTC tick speed +// [AON_RTC.SUBSECINC.*] is updated to 0x8637BD, +// corresponding to a 31.25kHz clock (done in the +// trimDevice() xxWare boot function). Standby +// power mode is not supported when using this +// clock source. +#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 + +// Field: [21] VDDR_TRIM_SLEEP_TC +// +// 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated +// 0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time +// standby mode is entered. This improves low-temperature RCOSC_LF frequency +// stability in standby mode. +// +// When temperature compensation is performed, the delta is calculates this +// way: +// Delta = max (delta, min(8, floor(62-temp)/8)) +// Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current +// temperature in degrees C. +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 + +// Field: [20] RTC_COMP +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_RTC_COMP 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_BITN 20 +#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_S 20 + +// Field: [19:18] XOSC_FREQ +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +// ENUMs: +// 24M 24 MHz XOSC_HF +// 48M 48 MHz XOSC_HF +// HPOSC HPOSC +#define CCFG_MODE_CONF_XOSC_FREQ_W 2 +#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_S 18 +#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 +#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 + +// Field: [17] XOSC_CAP_MOD +// +// Enable modification (delta) to XOSC cap-array. Value specified in +// XOSC_CAPARRAY_DELTA. +// 0: Apply cap-array delta +// 1: Do not apply cap-array delta (default) +#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 + +// Field: [16] HF_COMP +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_HF_COMP 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_BITN 16 +#define CCFG_MODE_CONF_HF_COMP_M 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_S 16 + +// Field: [15:8] XOSC_CAPARRAY_DELTA +// +// Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. +// Enabled by XOSC_CAP_MOD. +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 + +// Field: [7:0] VDDR_CAP +// +// Unsigned 8-bit integer, representing the minimum decoupling capacitance +// (worst case) on VDDR, in units of 100nF. This should take into account +// capacitor tolerance and voltage dependent capacitance variation. This bit +// affects the recharge period calculation when going into powerdown or +// standby. +// +// NOTE! If using the following functions this field must be configured (used +// by TI RTOS): +// SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() +#define CCFG_MODE_CONF_VDDR_CAP_W 8 +#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF +#define CCFG_MODE_CONF_VDDR_CAP_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_VOLT_LOAD_0 +// +//***************************************************************************** +// Field: [31:24] VDDR_EXT_TP45 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 + +// Field: [23:16] VDDR_EXT_TP25 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 + +// Field: [15:8] VDDR_EXT_TP5 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 + +// Field: [7:0] VDDR_EXT_TM15 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_VOLT_LOAD_1 +// +//***************************************************************************** +// Field: [31:24] VDDR_EXT_TP125 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 + +// Field: [23:16] VDDR_EXT_TP105 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 + +// Field: [15:8] VDDR_EXT_TP85 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 + +// Field: [7:0] VDDR_EXT_TP65 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_RTC_OFFSET +// +//***************************************************************************** +// Field: [31:16] RTC_COMP_P0 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 + +// Field: [15:8] RTC_COMP_P1 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 + +// Field: [7:0] RTC_COMP_P2 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF +#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_FREQ_OFFSET +// +//***************************************************************************** +// Field: [31:16] HF_COMP_P0 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 + +// Field: [15:8] HF_COMP_P1 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 + +// Field: [7:0] HF_COMP_P2 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF +#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_MAC_0 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[31:0] of the 64-bits custom IEEE MAC address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_MAC_0_ADDR_W 32 +#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_0_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_MAC_1 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[63:32] of the 64-bits custom IEEE MAC address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_MAC_1_ADDR_W 32 +#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_1_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_BLE_0 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[31:0] of the 64-bits custom IEEE BLE address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_BLE_0_ADDR_W 32 +#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_0_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_BLE_1 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[63:32] of the 64-bits custom IEEE BLE address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_BLE_1_ADDR_W 32 +#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_1_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_BL_CONFIG +// +//***************************************************************************** +// Field: [31:24] BOOTLOADER_ENABLE +// +// Bootloader enable. Boot loader can be accessed if +// IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and +// conditions for boot loader backdoor are met). +// 0xC5: Boot loader is enabled. +// Any other value: Boot loader is disabled. +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 + +// Field: [16] BL_LEVEL +// +// Sets the active level of the selected DIO number BL_PIN_NUMBER if boot +// loader backdoor is enabled by the BL_ENABLE field. +// 0: Active low. +// 1: Active high. +#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 +#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_S 16 + +// Field: [15:8] BL_PIN_NUMBER +// +// DIO number that is level checked if the boot loader backdoor is enabled by +// the BL_ENABLE field. +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 + +// Field: [7:0] BL_ENABLE +// +// Enables the boot loader backdoor. +// 0xC5: Boot loader backdoor is enabled. +// Any other value: Boot loader backdoor is disabled. +// +// NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader +// backdoor is enabled. +#define CCFG_BL_CONFIG_BL_ENABLE_W 8 +#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF +#define CCFG_BL_CONFIG_BL_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_ERASE_CONF +// +//***************************************************************************** +// Field: [8] CHIP_ERASE_DIS_N +// +// Chip erase. +// This bit controls if a chip erase requested through the JTAG WUC TAP will be +// ignored in a following boot caused by a reset of the MCU VD. +// A successful chip erase operation will force the content of the flash main +// bank back to the state as it was when delivered by TI. +// 0: Disable. Any chip erase request detected during boot will be ignored. +// 1: Enable. Any chip erase request detected during boot will be performed by +// the boot FW. +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 + +// Field: [0] BANK_ERASE_DIS_N +// +// Bank erase. +// This bit controls if the ROM serial boot loader will accept a received Bank +// Erase command (COMMAND_BANK_ERASE). +// A successful Bank Erase operation will erase all main bank sectors not +// protected by write protect configuration bits in CCFG. +// 0: Disable the boot loader bank erase function. +// 1: Enable the boot loader bank erase function. +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TI_OPTIONS +// +//***************************************************************************** +// Field: [7:0] TI_FA_ENABLE +// +// TI Failure Analysis. +// 0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) +// option with the unlock code. +// All other values: Disable the functionality of unlocking the TI FA option +// with the unlock code. +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TAP_DAP_0 +// +//***************************************************************************** +// Field: [23:16] CPU_DAP_ENABLE +// +// Enable CPU DAP. +// 0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM +// boot FW. +// Any other value: Main CPU DAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 + +// Field: [15:8] PRCM_TAP_ENABLE +// +// Enable PRCM TAP. +// 0xC5: PRCM TAP access is enabled during power-up/system-reset by ROM boot FW +// if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PRCM TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_S 8 + +// Field: [7:0] TEST_TAP_ENABLE +// +// Enable Test TAP. +// 0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW +// if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: TEST TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TAP_DAP_1 +// +//***************************************************************************** +// Field: [23:16] PBIST2_TAP_ENABLE +// +// Enable PBIST2 TAP. +// 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot +// FW if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PBIST2 TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 + +// Field: [15:8] PBIST1_TAP_ENABLE +// +// Enable PBIST1 TAP. +// 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot +// FW if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PBIST1 TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 + +// Field: [7:0] WUC_TAP_ENABLE +// +// Enable WUC TAP +// 0xC5: WUC TAP access is enabled during power-up/system-reset by ROM boot FW +// if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: WUC TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IMAGE_VALID_CONF +// +//***************************************************************************** +// Field: [31:0] IMAGE_VALID +// +// This field must have a value of 0x00000000 in order for enabling the boot +// sequence to transfer control to a flash image. +// A non-zero value forces the boot sequence to call the boot loader. +// +// For CC2640R2: +// This field must have the address value of the start of the flash vector +// table in order for enabling the boot sequence to transfer control to a flash +// image. +// Any illegal vector table start address value forces the boot sequence to +// call the boot loader. +// Note that if any other legal vector table start address value than 0x0 is +// selected the PRCM:WARMRESET.WR_TO_PINRESET must be set to 1. +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_31_0 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_31 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 + +// Field: [30] WRT_PROT_SEC_30 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 + +// Field: [29] WRT_PROT_SEC_29 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 + +// Field: [28] WRT_PROT_SEC_28 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 + +// Field: [27] WRT_PROT_SEC_27 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 + +// Field: [26] WRT_PROT_SEC_26 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 + +// Field: [25] WRT_PROT_SEC_25 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 + +// Field: [24] WRT_PROT_SEC_24 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 + +// Field: [23] WRT_PROT_SEC_23 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 + +// Field: [22] WRT_PROT_SEC_22 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 + +// Field: [21] WRT_PROT_SEC_21 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 + +// Field: [20] WRT_PROT_SEC_20 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 + +// Field: [19] WRT_PROT_SEC_19 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 + +// Field: [18] WRT_PROT_SEC_18 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 + +// Field: [17] WRT_PROT_SEC_17 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 + +// Field: [16] WRT_PROT_SEC_16 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 + +// Field: [15] WRT_PROT_SEC_15 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 + +// Field: [14] WRT_PROT_SEC_14 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 + +// Field: [13] WRT_PROT_SEC_13 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 + +// Field: [12] WRT_PROT_SEC_12 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 + +// Field: [11] WRT_PROT_SEC_11 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 + +// Field: [10] WRT_PROT_SEC_10 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 + +// Field: [9] WRT_PROT_SEC_9 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 + +// Field: [8] WRT_PROT_SEC_8 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 + +// Field: [7] WRT_PROT_SEC_7 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 + +// Field: [6] WRT_PROT_SEC_6 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 + +// Field: [5] WRT_PROT_SEC_5 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 + +// Field: [4] WRT_PROT_SEC_4 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 + +// Field: [3] WRT_PROT_SEC_3 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 + +// Field: [2] WRT_PROT_SEC_2 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 + +// Field: [1] WRT_PROT_SEC_1 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 + +// Field: [0] WRT_PROT_SEC_0 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_63_32 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_63 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 + +// Field: [30] WRT_PROT_SEC_62 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 + +// Field: [29] WRT_PROT_SEC_61 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 + +// Field: [28] WRT_PROT_SEC_60 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 + +// Field: [27] WRT_PROT_SEC_59 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 + +// Field: [26] WRT_PROT_SEC_58 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 + +// Field: [25] WRT_PROT_SEC_57 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 + +// Field: [24] WRT_PROT_SEC_56 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 + +// Field: [23] WRT_PROT_SEC_55 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 + +// Field: [22] WRT_PROT_SEC_54 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 + +// Field: [21] WRT_PROT_SEC_53 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 + +// Field: [20] WRT_PROT_SEC_52 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 + +// Field: [19] WRT_PROT_SEC_51 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 + +// Field: [18] WRT_PROT_SEC_50 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 + +// Field: [17] WRT_PROT_SEC_49 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 + +// Field: [16] WRT_PROT_SEC_48 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 + +// Field: [15] WRT_PROT_SEC_47 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 + +// Field: [14] WRT_PROT_SEC_46 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 + +// Field: [13] WRT_PROT_SEC_45 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 + +// Field: [12] WRT_PROT_SEC_44 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 + +// Field: [11] WRT_PROT_SEC_43 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 + +// Field: [10] WRT_PROT_SEC_42 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 + +// Field: [9] WRT_PROT_SEC_41 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 + +// Field: [8] WRT_PROT_SEC_40 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 + +// Field: [7] WRT_PROT_SEC_39 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 + +// Field: [6] WRT_PROT_SEC_38 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 + +// Field: [5] WRT_PROT_SEC_37 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 + +// Field: [4] WRT_PROT_SEC_36 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 + +// Field: [3] WRT_PROT_SEC_35 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 + +// Field: [2] WRT_PROT_SEC_34 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 + +// Field: [1] WRT_PROT_SEC_33 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 + +// Field: [0] WRT_PROT_SEC_32 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_95_64 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_95 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 + +// Field: [30] WRT_PROT_SEC_94 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 + +// Field: [29] WRT_PROT_SEC_93 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 + +// Field: [28] WRT_PROT_SEC_92 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 + +// Field: [27] WRT_PROT_SEC_91 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 + +// Field: [26] WRT_PROT_SEC_90 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 + +// Field: [25] WRT_PROT_SEC_89 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 + +// Field: [24] WRT_PROT_SEC_88 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 + +// Field: [23] WRT_PROT_SEC_87 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 + +// Field: [22] WRT_PROT_SEC_86 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 + +// Field: [21] WRT_PROT_SEC_85 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 + +// Field: [20] WRT_PROT_SEC_84 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 + +// Field: [19] WRT_PROT_SEC_83 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 + +// Field: [18] WRT_PROT_SEC_82 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 + +// Field: [17] WRT_PROT_SEC_81 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 + +// Field: [16] WRT_PROT_SEC_80 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 + +// Field: [15] WRT_PROT_SEC_79 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 + +// Field: [14] WRT_PROT_SEC_78 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 + +// Field: [13] WRT_PROT_SEC_77 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 + +// Field: [12] WRT_PROT_SEC_76 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 + +// Field: [11] WRT_PROT_SEC_75 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 + +// Field: [10] WRT_PROT_SEC_74 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 + +// Field: [9] WRT_PROT_SEC_73 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 + +// Field: [8] WRT_PROT_SEC_72 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 + +// Field: [7] WRT_PROT_SEC_71 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 + +// Field: [6] WRT_PROT_SEC_70 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 + +// Field: [5] WRT_PROT_SEC_69 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 + +// Field: [4] WRT_PROT_SEC_68 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 + +// Field: [3] WRT_PROT_SEC_67 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 + +// Field: [2] WRT_PROT_SEC_66 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 + +// Field: [1] WRT_PROT_SEC_65 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 + +// Field: [0] WRT_PROT_SEC_64 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_127_96 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_127 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 + +// Field: [30] WRT_PROT_SEC_126 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 + +// Field: [29] WRT_PROT_SEC_125 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 + +// Field: [28] WRT_PROT_SEC_124 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 + +// Field: [27] WRT_PROT_SEC_123 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 + +// Field: [26] WRT_PROT_SEC_122 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 + +// Field: [25] WRT_PROT_SEC_121 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 + +// Field: [24] WRT_PROT_SEC_120 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 + +// Field: [23] WRT_PROT_SEC_119 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 + +// Field: [22] WRT_PROT_SEC_118 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 + +// Field: [21] WRT_PROT_SEC_117 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 + +// Field: [20] WRT_PROT_SEC_116 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 + +// Field: [19] WRT_PROT_SEC_115 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 + +// Field: [18] WRT_PROT_SEC_114 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 + +// Field: [17] WRT_PROT_SEC_113 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 + +// Field: [16] WRT_PROT_SEC_112 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 + +// Field: [15] WRT_PROT_SEC_111 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 + +// Field: [14] WRT_PROT_SEC_110 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 + +// Field: [13] WRT_PROT_SEC_109 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 + +// Field: [12] WRT_PROT_SEC_108 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 + +// Field: [11] WRT_PROT_SEC_107 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 + +// Field: [10] WRT_PROT_SEC_106 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 + +// Field: [9] WRT_PROT_SEC_105 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 + +// Field: [8] WRT_PROT_SEC_104 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 + +// Field: [7] WRT_PROT_SEC_103 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 + +// Field: [6] WRT_PROT_SEC_102 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 + +// Field: [5] WRT_PROT_SEC_101 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 + +// Field: [4] WRT_PROT_SEC_100 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 + +// Field: [3] WRT_PROT_SEC_99 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 + +// Field: [2] WRT_PROT_SEC_98 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 + +// Field: [1] WRT_PROT_SEC_97 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 + +// Field: [0] WRT_PROT_SEC_96 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 + + +#endif // __CCFG__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg_simple_struct.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg_simple_struct.h new file mode 100644 index 0000000..12cfc01 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg_simple_struct.h @@ -0,0 +1,81 @@ +/****************************************************************************** +* Filename: hw_ccfg_simple_struct_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CCFG_SIMPLE_STRUCT_H__ +#define __HW_CCFG_SIMPLE_STRUCT_H__ + +//***************************************************************************** +// +// Customer configuration (ccfg) typedef. +// The implementation of this struct is required by device ROM boot code +// and must be placed at the end of flash. Do not modify this struct! +// +//***************************************************************************** +typedef struct +{ // Mapped to address + uint32_t CCFG_EXT_LF_CLK ; // 0x50003FA8 + uint32_t CCFG_MODE_CONF_1 ; // 0x50003FAC + uint32_t CCFG_SIZE_AND_DIS_FLAGS ; // 0x50003FB0 + uint32_t CCFG_MODE_CONF ; // 0x50003FB4 + uint32_t CCFG_VOLT_LOAD_0 ; // 0x50003FB8 + uint32_t CCFG_VOLT_LOAD_1 ; // 0x50003FBC + uint32_t CCFG_RTC_OFFSET ; // 0x50003FC0 + uint32_t CCFG_FREQ_OFFSET ; // 0x50003FC4 + uint32_t CCFG_IEEE_MAC_0 ; // 0x50003FC8 + uint32_t CCFG_IEEE_MAC_1 ; // 0x50003FCC + uint32_t CCFG_IEEE_BLE_0 ; // 0x50003FD0 + uint32_t CCFG_IEEE_BLE_1 ; // 0x50003FD4 + uint32_t CCFG_BL_CONFIG ; // 0x50003FD8 + uint32_t CCFG_ERASE_CONF ; // 0x50003FDC + uint32_t CCFG_CCFG_TI_OPTIONS ; // 0x50003FE0 + uint32_t CCFG_CCFG_TAP_DAP_0 ; // 0x50003FE4 + uint32_t CCFG_CCFG_TAP_DAP_1 ; // 0x50003FE8 + uint32_t CCFG_IMAGE_VALID_CONF ; // 0x50003FEC + uint32_t CCFG_CCFG_PROT_31_0 ; // 0x50003FF0 + uint32_t CCFG_CCFG_PROT_63_32 ; // 0x50003FF4 + uint32_t CCFG_CCFG_PROT_95_64 ; // 0x50003FF8 + uint32_t CCFG_CCFG_PROT_127_96 ; // 0x50003FFC +} ccfg_t; + +//***************************************************************************** +// +// Define the extern ccfg structure (__ccfg) +// +//***************************************************************************** +extern const ccfg_t __ccfg; + + +#endif // __HW_CCFG_SIMPLE_STRUCT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_chip_def.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_chip_def.h new file mode 100644 index 0000000..529cc02 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_chip_def.h @@ -0,0 +1,237 @@ +/****************************************************************************** +* Filename: hw_chip_def.h +* Revised: 2017-06-26 09:33:33 +0200 (Mon, 26 Jun 2017) +* Revision: 49227 +* +* Description: Defines for device properties. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup config_api +//! @{ +// +//***************************************************************************** + +#ifndef __HW_CHIP_DEF_H__ +#define __HW_CHIP_DEF_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Define CC_CHIP_ID code used in the following macros defined at the bottom: +// CC_GET_CHIP_FAMILY/DEVICE/PACKAGE/HWREV +// +//***************************************************************************** +/* CC2620F128 */ +#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21) + #define CC_CHIP_ID 0x26200720 +#elif defined(CC2620F128RHB_R20) || defined(CC2620F128RHB_R21) + #define CC_CHIP_ID 0x26200520 +#elif defined(CC2620F128RSM_R20) || defined(CC2620F128RSM_R21) + #define CC_CHIP_ID 0x26200420 +#elif defined(CC2620F128_R20) || defined(CC2620F128_R21) + #define CC_CHIP_ID 0x26200020 +#elif defined(CC2620F128RGZ_R22) || defined(CC2620F128RGZ) + #define CC_CHIP_ID 0x26200722 +#elif defined(CC2620F128RHB_R22) || defined(CC2620F128RHB) + #define CC_CHIP_ID 0x26200522 +#elif defined(CC2620F128RSM_R22) || defined(CC2620F128RSM) + #define CC_CHIP_ID 0x26200422 +#elif defined(CC2620F128_R22) || defined(CC2620F128) + #define CC_CHIP_ID 0x26200022 +/* CC2630F128 */ +#elif defined(CC2630F128RGZ_R20) || defined(CC2630F128RGZ_R21) + #define CC_CHIP_ID 0x26300720 +#elif defined(CC2630F128RHB_R20) || defined(CC2630F128RHB_R21) + #define CC_CHIP_ID 0x26300520 +#elif defined(CC2630F128RSM_R20) || defined(CC2630F128RSM_R21) + #define CC_CHIP_ID 0x26300420 +#elif defined(CC2630F128_R20) || defined(CC2630F128_R21) + #define CC_CHIP_ID 0x26300020 +#elif defined(CC2630F128RGZ_R22) || defined(CC2630F128RGZ) + #define CC_CHIP_ID 0x26300722 +#elif defined(CC2630F128RHB_R22) || defined(CC2630F128RHB) + #define CC_CHIP_ID 0x26300522 +#elif defined(CC2630F128RSM_R22) || defined(CC2630F128RSM) + #define CC_CHIP_ID 0x26300422 +#elif defined(CC2630F128_R22) || defined(CC2630F128) + #define CC_CHIP_ID 0x26300022 +/* CC2640F128 */ +#elif defined(CC2640F128RGZ_R20) || defined(CC2640F128RGZ_R21) + #define CC_CHIP_ID 0x26400720 +#elif defined(CC2640F128RHB_R20) || defined(CC2640F128RHB_R21) + #define CC_CHIP_ID 0x26400520 +#elif defined(CC2640F128RSM_R20) || defined(CC2640F128RSM_R21) + #define CC_CHIP_ID 0x26400420 +#elif defined(CC2640F128_R20) || defined(CC2640F128_R21) + #define CC_CHIP_ID 0x26400020 +#elif defined(CC2640F128RGZ_R22) || defined(CC2640F128RGZ) + #define CC_CHIP_ID 0x26400722 +#elif defined(CC2640F128RHB_R22) || defined(CC2640F128RHB) + #define CC_CHIP_ID 0x26400522 +#elif defined(CC2640F128RSM_R22) || defined(CC2640F128RSM) + #define CC_CHIP_ID 0x26400422 +#elif defined(CC2640F128_R22) || defined(CC2640F128) + #define CC_CHIP_ID 0x26400022 +/* CC2650F128 */ +#elif defined(CC2650F128RGZ_R20) || defined(CC2650F128RGZ_R21) + #define CC_CHIP_ID 0x26500720 +#elif defined(CC2650F128RHB_R20) || defined(CC2650F128RHB_R21) + #define CC_CHIP_ID 0x26500520 +#elif defined(CC2650F128RSM_R20) || defined(CC2650F128RSM_R21) + #define CC_CHIP_ID 0x26500420 +#elif defined(CC2650F128_R20) || defined(CC2650F128_R21) + #define CC_CHIP_ID 0x26500020 +#elif defined(CC2650F128RGZ_R22) || defined(CC2650F128RGZ) + #define CC_CHIP_ID 0x26500722 +#elif defined(CC2650F128RHB_R22) || defined(CC2650F128RHB) + #define CC_CHIP_ID 0x26500522 +#elif defined(CC2650F128RSM_R22) || defined(CC2650F128RSM) + #define CC_CHIP_ID 0x26500422 +#elif defined(CC2650F128_R22) || defined(CC2650F128) + #define CC_CHIP_ID 0x26500022 +/* CC2650L128 (OTP) */ +#elif defined(CC2650L128) + #define CC_CHIP_ID 0x26501710 +/* CC1310F128 */ +#elif defined(CC1310F128RGZ_R20) || defined(CC1310F128RGZ) + #define CC_CHIP_ID 0x13100720 +#elif defined(CC1310F128RHB_R20) || defined(CC1310F128RHB) + #define CC_CHIP_ID 0x13100520 +#elif defined(CC1310F128RSM_R20) || defined(CC1310F128RSM) + #define CC_CHIP_ID 0x13100420 +#elif defined(CC1310F128_R20) || defined(CC1310F128) + #define CC_CHIP_ID 0x13100020 +/* CC1350F128 */ +#elif defined(CC1350F128RGZ_R20) || defined(CC1350F128RGZ) + #define CC_CHIP_ID 0x13500720 +#elif defined(CC1350F128RHB_R20) || defined(CC1350F128RHB) + #define CC_CHIP_ID 0x13500520 +#elif defined(CC1350F128RSM_R20) || defined(CC1350F128RSM) + #define CC_CHIP_ID 0x13500420 +#elif defined(CC1350F128_R20) || defined(CC1350F128) + #define CC_CHIP_ID 0x13500020 +/* CC2640R2F */ +#elif defined(CC2640R2FRGZ_R25) || defined(CC2640R2FRGZ) + #define CC_CHIP_ID 0x26401710 +#elif defined(CC2640R2FRHB_R25) || defined(CC2640R2FRHB) + #define CC_CHIP_ID 0x26401510 +#elif defined(CC2640R2FRSM_R25) || defined(CC2640R2FRSM) + #define CC_CHIP_ID 0x26401410 +#elif defined(CC2640R2F_R25) || defined(CC2640R2F) + #define CC_CHIP_ID 0x26401010 +/* CC2652R1F */ +#elif defined(CC2652R1FRGZ_R10) || defined(CC2652R1FRGZ) + #define CC_CHIP_ID 0x26523710 +#elif defined(CC2652R1F_R10) || defined(CC2652R1F) + #define CC_CHIP_ID 0x26523010 +/* CC2644R1F */ +#elif defined(CC2644R1FRGZ_R10) || defined(CC2644R1FRGZ) + #define CC_CHIP_ID 0x26443710 +#elif defined(CC2644R1F_R10) || defined(CC2644R1F) + #define CC_CHIP_ID 0x26443010 +/* CC2642R1F */ +#elif defined(CC2642R1FRGZ_R10) || defined(CC2642R1FRGZ) + #define CC_CHIP_ID 0x26423710 +#elif defined(CC2642R1F_R10) || defined(CC2642R1F) + #define CC_CHIP_ID 0x26423010 +/* CC1354R1F */ +#elif defined(CC1354R1FRGZ_R10) || defined(CC1354R1FRGZ) + #define CC_CHIP_ID 0x13543710 +#elif defined(CC1354R1F_R10) || defined(CC1354R1F) + #define CC_CHIP_ID 0x13543010 +/* CC1352R1F */ +#elif defined(CC1352R1FRGZ_R10) || defined(CC1352R1FRGZ) + #define CC_CHIP_ID 0x13523710 +#elif defined(CC1352R1F_R10) || defined(CC1352R1F) + #define CC_CHIP_ID 0x13523010 +/* CC1312R1F */ +#elif defined(CC1312R1FRGZ_R10) || defined(CC1312R1FRGZ) + #define CC_CHIP_ID 0x13123710 +#elif defined(CC1312R1F_R10) || defined(CC1312R1F) + #define CC_CHIP_ID 0x13123010 +#endif + +#define CC_GET_CHIP_FAMILY 0x13 +#define CC_GET_CHIP_OPTION 0x0 +#define CC_GET_CHIP_HWREV 0x20 + +#ifdef CC_CHIP_ID + /* Define chip package only if specified */ + #if (CC_CHIP_ID & 0x00000F00) != 0 + #define CC_GET_CHIP_PACKAGE (((CC_CHIP_ID) & 0x00000F00) >> 8) + #endif + + /* Define chip device */ + #define CC_GET_CHIP_DEVICE (((CC_CHIP_ID) & 0xFFFF0000) >> 16) + + /* The chip family, option and package shall match the DriverLib release */ + #if (CC_GET_CHIP_FAMILY != ((CC_CHIP_ID & 0xFF000000) >> 24)) + #error "Specified chip family does not match DriverLib release" + #endif + #if (CC_GET_CHIP_OPTION != ((CC_CHIP_ID & 0x0000F000) >> 12)) + #error "Specified chip option does not match DriverLib release" + #endif + #if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0)) + #error "Specified chip hardware revision does not match DriverLib release" + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __HW_CHIP_DEF_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_dwt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_dwt.h new file mode 100644 index 0000000..1721748 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_dwt.h @@ -0,0 +1,856 @@ +/****************************************************************************** +* Filename: hw_cpu_dwt_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_DWT_H__ +#define __HW_CPU_DWT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_DWT component +// +//***************************************************************************** +// Control +#define CPU_DWT_O_CTRL 0x00000000 + +// Current PC Sampler Cycle Count +#define CPU_DWT_O_CYCCNT 0x00000004 + +// CPI Count +#define CPU_DWT_O_CPICNT 0x00000008 + +// Exception Overhead Count +#define CPU_DWT_O_EXCCNT 0x0000000C + +// Sleep Count +#define CPU_DWT_O_SLEEPCNT 0x00000010 + +// LSU Count +#define CPU_DWT_O_LSUCNT 0x00000014 + +// Fold Count +#define CPU_DWT_O_FOLDCNT 0x00000018 + +// Program Counter Sample +#define CPU_DWT_O_PCSR 0x0000001C + +// Comparator 0 +#define CPU_DWT_O_COMP0 0x00000020 + +// Mask 0 +#define CPU_DWT_O_MASK0 0x00000024 + +// Function 0 +#define CPU_DWT_O_FUNCTION0 0x00000028 + +// Comparator 1 +#define CPU_DWT_O_COMP1 0x00000030 + +// Mask 1 +#define CPU_DWT_O_MASK1 0x00000034 + +// Function 1 +#define CPU_DWT_O_FUNCTION1 0x00000038 + +// Comparator 2 +#define CPU_DWT_O_COMP2 0x00000040 + +// Mask 2 +#define CPU_DWT_O_MASK2 0x00000044 + +// Function 2 +#define CPU_DWT_O_FUNCTION2 0x00000048 + +// Comparator 3 +#define CPU_DWT_O_COMP3 0x00000050 + +// Mask 3 +#define CPU_DWT_O_MASK3 0x00000054 + +// Function 3 +#define CPU_DWT_O_FUNCTION3 0x00000058 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CTRL +// +//***************************************************************************** +// Field: [25] NOCYCCNT +// +// When set, CYCCNT is not supported. +#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 +#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_S 25 + +// Field: [24] NOPRFCNT +// +// When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. +#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 +#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_S 24 + +// Field: [22] CYCEVTENA +// +// Enables Cycle count event. Emits an event when the POSTCNT counter triggers +// it. See CYCTAP and POSTPRESET for details. This event is only emitted if +// PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. +// +// 0: Cycle count events disabled +// 1: Cycle count events enabled +#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 +#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_S 22 + +// Field: [21] FOLDEVTENA +// +// Enables Folded instruction count event. Emits an event when FOLDCNT +// overflows (every 256 cycles of folded instructions). A folded instruction is +// one that does not incur even one cycle to execute. For example, an IT +// instruction is folded away and so does not use up one cycle. +// +// 0: Folded instruction count events disabled. +// 1: Folded instruction count events enabled. +#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 +#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_S 21 + +// Field: [20] LSUEVTENA +// +// Enables LSU count event. Emits an event when LSUCNT overflows (every 256 +// cycles of LSU operation). LSU counts include all LSU costs after the initial +// cycle for the instruction. +// +// 0: LSU count events disabled. +// 1: LSU count events enabled. +#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 +#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_S 20 + +// Field: [19] SLEEPEVTENA +// +// Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 +// cycles that the processor is sleeping). +// +// 0: Sleep count events disabled. +// 1: Sleep count events enabled. +#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 +#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 + +// Field: [18] EXCEVTENA +// +// Enables Interrupt overhead event. Emits an event when EXCCNT overflows +// (every 256 cycles of interrupt overhead). +// +// 0x0: Interrupt overhead event disabled. +// 0x1: Interrupt overhead event enabled. +#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 +#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_S 18 + +// Field: [17] CPIEVTENA +// +// Enables CPI count event. Emits an event when CPICNT overflows (every 256 +// cycles of multi-cycle instructions). +// +// 0: CPI counter events disabled. +// 1: CPI counter events enabled. +#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 +#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_S 17 + +// Field: [16] EXCTRCENA +// +// Enables Interrupt event tracing. +// +// 0: Interrupt event trace disabled. +// 1: Interrupt event trace enabled. +#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 +#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_S 16 + +// Field: [12] PCSAMPLEENA +// +// Enables PC Sampling event. A PC sample event is emitted when the POSTCNT +// counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this +// bit overrides CYCEVTENA. +// +// 0: PC Sampling event disabled. +// 1: Sampling event enabled. +#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 +#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 + +// Field: [11:10] SYNCTAP +// +// Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA +// must also be enabled for this feature. +// Synchronization packets (if enabled) are generated on tap transitions (0 to1 +// or 1 to 0). +// ENUMs: +// BIT28 Tap at bit 28 of CYCCNT +// BIT26 Tap at bit 26 of CYCCNT +// BIT24 Tap at bit 24 of CYCCNT +// DIS Disabled. No synchronization packets +#define CPU_DWT_CTRL_SYNCTAP_W 2 +#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_S 10 +#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 +#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 +#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 + +// Field: [9] CYCTAP +// +// Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the +// selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the +// POSTCNT, post-scalar counter. That counter then counts down. On a bit change +// when post-scalar is 0, it triggers an event for PC sampling or cycle count +// event (see details in CYCEVTENA). +// ENUMs: +// BIT10 Selects bit [10] to tap +// BIT6 Selects bit [6] to tap +#define CPU_DWT_CTRL_CYCTAP 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BITN 9 +#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_S 9 +#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 + +// Field: [8:5] POSTCNT +// +// Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 +// to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it +// triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the +// value from POSTPRESET. +#define CPU_DWT_CTRL_POSTCNT_W 4 +#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 +#define CPU_DWT_CTRL_POSTCNT_S 5 + +// Field: [4:1] POSTPRESET +// +// Reload value for post-scalar counter POSTCNT. When 0, events are triggered +// on each tap change (a power of 2). If this field has a non-0 value, it forms +// a count-down value, to be reloaded into POSTCNT each time it reaches 0. For +// example, a value 1 in this register means an event is formed every other tap +// change. +#define CPU_DWT_CTRL_POSTPRESET_W 4 +#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E +#define CPU_DWT_CTRL_POSTPRESET_S 1 + +// Field: [0] CYCCNTENA +// +// Enable CYCCNT, allowing it to increment and generate synchronization and +// count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. +#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 +#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CYCCNT +// +//***************************************************************************** +// Field: [31:0] CYCCNT +// +// Current PC Sampler Cycle Counter count value. When enabled, this counter +// counts the number of core cycles, except when the core is halted. The cycle +// counter is a free running counter, counting upwards (this counter will not +// advance in power modes where free-running clock to CPU stops). It wraps +// around to 0 on overflow. The debugger must initialize this to 0 when first +// enabling. +#define CPU_DWT_CYCCNT_CYCCNT_W 32 +#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF +#define CPU_DWT_CYCCNT_CYCCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CPICNT +// +//***************************************************************************** +// Field: [7:0] CPICNT +// +// Current CPI counter value. Increments on the additional cycles (the first +// cycle is not counted) required to execute all instructions except those +// recorded by LSUCNT. This counter also increments on all instruction fetch +// stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter +// overflows. This counter initializes to 0 when it is enabled using +// CTRL.CPIEVTENA. +#define CPU_DWT_CPICNT_CPICNT_W 8 +#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF +#define CPU_DWT_CPICNT_CPICNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_EXCCNT +// +//***************************************************************************** +// Field: [7:0] EXCCNT +// +// Current interrupt overhead counter value. Counts the total cycles spent in +// interrupt processing (for example entry stacking, return unstacking, +// pre-emption). An event is emitted on counter overflow (every 256 cycles). +// This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. +#define CPU_DWT_EXCCNT_EXCCNT_W 8 +#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF +#define CPU_DWT_EXCCNT_EXCCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_SLEEPCNT +// +//***************************************************************************** +// Field: [7:0] SLEEPCNT +// +// Sleep counter. Counts the number of cycles during which the processor is +// sleeping. An event is emitted on counter overflow (every 256 cycles). This +// counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note +// that the sleep counter is clocked using CPU's free-running clock. In some +// power modes the free-running clock to CPU is gated to minimize power +// consumption. This means that the sleep counter will be invalid in these +// power modes. +#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 +#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF +#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_LSUCNT +// +//***************************************************************************** +// Field: [7:0] LSUCNT +// +// LSU counter. This counts the total number of cycles that the processor is +// processing an LSU operation. The initial execution cost of the instruction +// is not counted. For example, an LDR that takes two cycles to complete +// increments this counter one cycle. Equivalently, an LDR that stalls for two +// cycles (i.e. takes four cycles to execute), increments this counter three +// times. An event is emitted on counter overflow (every 256 cycles). This +// counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. +#define CPU_DWT_LSUCNT_LSUCNT_W 8 +#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF +#define CPU_DWT_LSUCNT_LSUCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FOLDCNT +// +//***************************************************************************** +// Field: [7:0] FOLDCNT +// +// This counts the total number folded instructions. This counter initializes +// to 0 when it is enabled using CTRL.FOLDEVTENA. +#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 +#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF +#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_PCSR +// +//***************************************************************************** +// Field: [31:0] EIASAMPLE +// +// Execution instruction address sample, or 0xFFFFFFFF if the core is halted. +#define CPU_DWT_PCSR_EIASAMPLE_W 32 +#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF +#define CPU_DWT_PCSR_EIASAMPLE_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP0 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler +// Counter (CYCCNT). +#define CPU_DWT_COMP0_COMP_W 32 +#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP0_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK0 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP0. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP0. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK0_MASK_W 4 +#define CPU_DWT_MASK0_MASK_M 0x0000000F +#define CPU_DWT_MASK0_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION0 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_S 24 + +// Field: [7] CYCMATCH +// +// This bit is only available in comparator 0. When set, COMP0 will compare +// against the cycle counter (CYCCNT). +#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 +#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION0_FUNCTION_W 4 +#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION0_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP1 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION1. +// Comparator 1 can also compare data values. So this register can contain +// reference values for data matching. +#define CPU_DWT_COMP1_COMP_W 32 +#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP1_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK1 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP1. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP1. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK1_MASK_W 4 +#define CPU_DWT_MASK1_MASK_M 0x0000000F +#define CPU_DWT_MASK1_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION1 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_S 24 + +// Field: [19:16] DATAVADDR1 +// +// Identity of a second linked address comparator for data value matching when +// DATAVMATCH == 1 and LNK1ENA == 1. +#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 +#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 + +// Field: [15:12] DATAVADDR0 +// +// Identity of a linked address comparator for data value matching when +// DATAVMATCH == 1. +#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 +#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 + +// Field: [11:10] DATAVSIZE +// +// Defines the size of the data in the COMP1 register that is to be matched: +// +// 0x0: Byte +// 0x1: Halfword +// 0x2: Word +// 0x3: Unpredictable. +#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 +#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 +#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 + +// Field: [9] LNK1ENA +// +// Read only bit-field only supported in comparator 1. +// +// 0: DATAVADDR1 not supported +// 1: DATAVADDR1 supported (enabled) +#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 +#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 + +// Field: [8] DATAVMATCH +// +// Data match feature: +// +// 0: Perform address comparison +// 1: Perform data value compare. The comparators given by DATAVADDR0 and +// DATAVADDR1 provide the address for the data comparison. The FUNCTION setting +// for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and +// those comparators only provide the address match for the data comparison. +// +// This bit is only available in comparator 1. +#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 +#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings: +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and +// DATAVADDR1 if DATAVMATCH is also set. The comparators given by DATAVADDR0 +// and DATAVADDR1 can then only perform address comparator matches for +// comparator 1 data matches. +// Note 4: If the data matching functionality is not included during +// implementation it is not possible to set DATAVADDR0, DATAVADDR1, or +// DATAVMATCH. This means that the data matching functionality is not available +// in the implementation. Test the availability of data matching by writing and +// reading DATAVMATCH. If it is not settable then data matching is unavailable. +// Note 5: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION1_FUNCTION_W 4 +#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION1_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP2 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION2. +#define CPU_DWT_COMP2_COMP_W 32 +#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP2_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK2 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP2. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP2. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK2_MASK_W 4 +#define CPU_DWT_MASK2_MASK_M 0x0000000F +#define CPU_DWT_MASK2_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION2 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_S 24 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION2_FUNCTION_W 4 +#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION2_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP3 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION3. +#define CPU_DWT_COMP3_COMP_W 32 +#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP3_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK3 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP3. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP3. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK3_MASK_W 4 +#define CPU_DWT_MASK3_MASK_M 0x0000000F +#define CPU_DWT_MASK3_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION3 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_S 24 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION3_FUNCTION_W 4 +#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION3_FUNCTION_S 0 + + +#endif // __CPU_DWT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_fpb.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_fpb.h new file mode 100644 index 0000000..f70d8bd --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_fpb.h @@ -0,0 +1,443 @@ +/****************************************************************************** +* Filename: hw_cpu_fpb_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_FPB_H__ +#define __HW_CPU_FPB_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_FPB component +// +//***************************************************************************** +// Control +#define CPU_FPB_O_CTRL 0x00000000 + +// Remap +#define CPU_FPB_O_REMAP 0x00000004 + +// Comparator 0 +#define CPU_FPB_O_COMP0 0x00000008 + +// Comparator 1 +#define CPU_FPB_O_COMP1 0x0000000C + +// Comparator 2 +#define CPU_FPB_O_COMP2 0x00000010 + +// Comparator 3 +#define CPU_FPB_O_COMP3 0x00000014 + +// Comparator 4 +#define CPU_FPB_O_COMP4 0x00000018 + +// Comparator 5 +#define CPU_FPB_O_COMP5 0x0000001C + +// Comparator 6 +#define CPU_FPB_O_COMP6 0x00000020 + +// Comparator 7 +#define CPU_FPB_O_COMP7 0x00000024 + +//***************************************************************************** +// +// Register: CPU_FPB_O_CTRL +// +//***************************************************************************** +// Field: [13:12] NUM_CODE2 +// +// Number of full banks of code comparators, sixteen comparators per bank. +// Where less than sixteen code comparators are provided, the bank count is +// zero, and the number present indicated by NUM_CODE1. This read only field +// contains 3'b000 to indicate 0 banks for Cortex-M processor. +#define CPU_FPB_CTRL_NUM_CODE2_W 2 +#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 +#define CPU_FPB_CTRL_NUM_CODE2_S 12 + +// Field: [11:8] NUM_LIT +// +// Number of literal slots field. +// +// 0x0: No literal slots +// 0x2: Two literal slots +#define CPU_FPB_CTRL_NUM_LIT_W 4 +#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 +#define CPU_FPB_CTRL_NUM_LIT_S 8 + +// Field: [7:4] NUM_CODE1 +// +// Number of code slots field. +// +// 0x0: No code slots +// 0x2: Two code slots +// 0x6: Six code slots +#define CPU_FPB_CTRL_NUM_CODE1_W 4 +#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 +#define CPU_FPB_CTRL_NUM_CODE1_S 4 + +// Field: [1] KEY +// +// Key field. In order to write to this register, this bit-field must be +// written to '1'. This bit always reads 0. +#define CPU_FPB_CTRL_KEY 0x00000002 +#define CPU_FPB_CTRL_KEY_BITN 1 +#define CPU_FPB_CTRL_KEY_M 0x00000002 +#define CPU_FPB_CTRL_KEY_S 1 + +// Field: [0] ENABLE +// +// Flash patch unit enable bit +// +// 0x0: Flash patch unit disabled +// 0x1: Flash patch unit enabled +#define CPU_FPB_CTRL_ENABLE 0x00000001 +#define CPU_FPB_CTRL_ENABLE_BITN 0 +#define CPU_FPB_CTRL_ENABLE_M 0x00000001 +#define CPU_FPB_CTRL_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_REMAP +// +//***************************************************************************** +// Field: [28:5] REMAP +// +// Remap base address field. +#define CPU_FPB_REMAP_REMAP_W 24 +#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 +#define CPU_FPB_REMAP_REMAP_S 5 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP0 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP0_REPLACE_W 2 +#define CPU_FPB_COMP0_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP0_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP0_COMP_W 27 +#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP0_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 0. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 0 disabled +// 0x1: Compare and remap for comparator 0 enabled +#define CPU_FPB_COMP0_ENABLE 0x00000001 +#define CPU_FPB_COMP0_ENABLE_BITN 0 +#define CPU_FPB_COMP0_ENABLE_M 0x00000001 +#define CPU_FPB_COMP0_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP1 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP1_REPLACE_W 2 +#define CPU_FPB_COMP1_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP1_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP1_COMP_W 27 +#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP1_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 1. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 1 disabled +// 0x1: Compare and remap for comparator 1 enabled +#define CPU_FPB_COMP1_ENABLE 0x00000001 +#define CPU_FPB_COMP1_ENABLE_BITN 0 +#define CPU_FPB_COMP1_ENABLE_M 0x00000001 +#define CPU_FPB_COMP1_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP2 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP2_REPLACE_W 2 +#define CPU_FPB_COMP2_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP2_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP2_COMP_W 27 +#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP2_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 2. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 2 disabled +// 0x1: Compare and remap for comparator 2 enabled +#define CPU_FPB_COMP2_ENABLE 0x00000001 +#define CPU_FPB_COMP2_ENABLE_BITN 0 +#define CPU_FPB_COMP2_ENABLE_M 0x00000001 +#define CPU_FPB_COMP2_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP3 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP3_REPLACE_W 2 +#define CPU_FPB_COMP3_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP3_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP3_COMP_W 27 +#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP3_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 3. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 3 disabled +// 0x1: Compare and remap for comparator 3 enabled +#define CPU_FPB_COMP3_ENABLE 0x00000001 +#define CPU_FPB_COMP3_ENABLE_BITN 0 +#define CPU_FPB_COMP3_ENABLE_M 0x00000001 +#define CPU_FPB_COMP3_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP4 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP4_REPLACE_W 2 +#define CPU_FPB_COMP4_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP4_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP4_COMP_W 27 +#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP4_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 4. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 4 disabled +// 0x1: Compare and remap for comparator 4 enabled +#define CPU_FPB_COMP4_ENABLE 0x00000001 +#define CPU_FPB_COMP4_ENABLE_BITN 0 +#define CPU_FPB_COMP4_ENABLE_M 0x00000001 +#define CPU_FPB_COMP4_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP5 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP5_REPLACE_W 2 +#define CPU_FPB_COMP5_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP5_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP5_COMP_W 27 +#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP5_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 5. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 5 disabled +// 0x1: Compare and remap for comparator 5 enabled +#define CPU_FPB_COMP5_ENABLE 0x00000001 +#define CPU_FPB_COMP5_ENABLE_BITN 0 +#define CPU_FPB_COMP5_ENABLE_M 0x00000001 +#define CPU_FPB_COMP5_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP6 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Comparator 6 is +// a literal comparator and the only supported setting is 0x0. Other settings +// will be ignored. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP6_REPLACE_W 2 +#define CPU_FPB_COMP6_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP6_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP6_COMP_W 27 +#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP6_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 6. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 6 disabled +// 0x1: Compare and remap for comparator 6 enabled +#define CPU_FPB_COMP6_ENABLE 0x00000001 +#define CPU_FPB_COMP6_ENABLE_BITN 0 +#define CPU_FPB_COMP6_ENABLE_M 0x00000001 +#define CPU_FPB_COMP6_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP7 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Comparator 7 is +// a literal comparator and the only supported setting is 0x0. Other settings +// will be ignored. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP7_REPLACE_W 2 +#define CPU_FPB_COMP7_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP7_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP7_COMP_W 27 +#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP7_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 7. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 7 disabled +// 0x1: Compare and remap for comparator 7 enabled +#define CPU_FPB_COMP7_ENABLE 0x00000001 +#define CPU_FPB_COMP7_ENABLE_BITN 0 +#define CPU_FPB_COMP7_ENABLE_M 0x00000001 +#define CPU_FPB_COMP7_ENABLE_S 0 + + +#endif // __CPU_FPB__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_itm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_itm.h new file mode 100644 index 0000000..9996da5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_itm.h @@ -0,0 +1,1122 @@ +/****************************************************************************** +* Filename: hw_cpu_itm_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_ITM_H__ +#define __HW_CPU_ITM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_ITM component +// +//***************************************************************************** +// Stimulus Port 0 +#define CPU_ITM_O_STIM0 0x00000000 + +// Stimulus Port 1 +#define CPU_ITM_O_STIM1 0x00000004 + +// Stimulus Port 2 +#define CPU_ITM_O_STIM2 0x00000008 + +// Stimulus Port 3 +#define CPU_ITM_O_STIM3 0x0000000C + +// Stimulus Port 4 +#define CPU_ITM_O_STIM4 0x00000010 + +// Stimulus Port 5 +#define CPU_ITM_O_STIM5 0x00000014 + +// Stimulus Port 6 +#define CPU_ITM_O_STIM6 0x00000018 + +// Stimulus Port 7 +#define CPU_ITM_O_STIM7 0x0000001C + +// Stimulus Port 8 +#define CPU_ITM_O_STIM8 0x00000020 + +// Stimulus Port 9 +#define CPU_ITM_O_STIM9 0x00000024 + +// Stimulus Port 10 +#define CPU_ITM_O_STIM10 0x00000028 + +// Stimulus Port 11 +#define CPU_ITM_O_STIM11 0x0000002C + +// Stimulus Port 12 +#define CPU_ITM_O_STIM12 0x00000030 + +// Stimulus Port 13 +#define CPU_ITM_O_STIM13 0x00000034 + +// Stimulus Port 14 +#define CPU_ITM_O_STIM14 0x00000038 + +// Stimulus Port 15 +#define CPU_ITM_O_STIM15 0x0000003C + +// Stimulus Port 16 +#define CPU_ITM_O_STIM16 0x00000040 + +// Stimulus Port 17 +#define CPU_ITM_O_STIM17 0x00000044 + +// Stimulus Port 18 +#define CPU_ITM_O_STIM18 0x00000048 + +// Stimulus Port 19 +#define CPU_ITM_O_STIM19 0x0000004C + +// Stimulus Port 20 +#define CPU_ITM_O_STIM20 0x00000050 + +// Stimulus Port 21 +#define CPU_ITM_O_STIM21 0x00000054 + +// Stimulus Port 22 +#define CPU_ITM_O_STIM22 0x00000058 + +// Stimulus Port 23 +#define CPU_ITM_O_STIM23 0x0000005C + +// Stimulus Port 24 +#define CPU_ITM_O_STIM24 0x00000060 + +// Stimulus Port 25 +#define CPU_ITM_O_STIM25 0x00000064 + +// Stimulus Port 26 +#define CPU_ITM_O_STIM26 0x00000068 + +// Stimulus Port 27 +#define CPU_ITM_O_STIM27 0x0000006C + +// Stimulus Port 28 +#define CPU_ITM_O_STIM28 0x00000070 + +// Stimulus Port 29 +#define CPU_ITM_O_STIM29 0x00000074 + +// Stimulus Port 30 +#define CPU_ITM_O_STIM30 0x00000078 + +// Stimulus Port 31 +#define CPU_ITM_O_STIM31 0x0000007C + +// Trace Enable +#define CPU_ITM_O_TER 0x00000E00 + +// Trace Privilege +#define CPU_ITM_O_TPR 0x00000E40 + +// Trace Control +#define CPU_ITM_O_TCR 0x00000E80 + +// Lock Access +#define CPU_ITM_O_LAR 0x00000FB0 + +// Lock Status +#define CPU_ITM_O_LSR 0x00000FB4 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM0 +// +//***************************************************************************** +// Field: [31:0] STIM0 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM0_STIM0_W 32 +#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF +#define CPU_ITM_STIM0_STIM0_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM1 +// +//***************************************************************************** +// Field: [31:0] STIM1 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM1_STIM1_W 32 +#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF +#define CPU_ITM_STIM1_STIM1_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM2 +// +//***************************************************************************** +// Field: [31:0] STIM2 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM2_STIM2_W 32 +#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF +#define CPU_ITM_STIM2_STIM2_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM3 +// +//***************************************************************************** +// Field: [31:0] STIM3 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM3_STIM3_W 32 +#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF +#define CPU_ITM_STIM3_STIM3_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM4 +// +//***************************************************************************** +// Field: [31:0] STIM4 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM4_STIM4_W 32 +#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF +#define CPU_ITM_STIM4_STIM4_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM5 +// +//***************************************************************************** +// Field: [31:0] STIM5 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM5_STIM5_W 32 +#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF +#define CPU_ITM_STIM5_STIM5_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM6 +// +//***************************************************************************** +// Field: [31:0] STIM6 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM6_STIM6_W 32 +#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF +#define CPU_ITM_STIM6_STIM6_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM7 +// +//***************************************************************************** +// Field: [31:0] STIM7 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM7_STIM7_W 32 +#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF +#define CPU_ITM_STIM7_STIM7_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM8 +// +//***************************************************************************** +// Field: [31:0] STIM8 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM8_STIM8_W 32 +#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF +#define CPU_ITM_STIM8_STIM8_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM9 +// +//***************************************************************************** +// Field: [31:0] STIM9 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM9_STIM9_W 32 +#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF +#define CPU_ITM_STIM9_STIM9_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM10 +// +//***************************************************************************** +// Field: [31:0] STIM10 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM10_STIM10_W 32 +#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF +#define CPU_ITM_STIM10_STIM10_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM11 +// +//***************************************************************************** +// Field: [31:0] STIM11 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM11_STIM11_W 32 +#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF +#define CPU_ITM_STIM11_STIM11_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM12 +// +//***************************************************************************** +// Field: [31:0] STIM12 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM12_STIM12_W 32 +#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF +#define CPU_ITM_STIM12_STIM12_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM13 +// +//***************************************************************************** +// Field: [31:0] STIM13 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM13_STIM13_W 32 +#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF +#define CPU_ITM_STIM13_STIM13_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM14 +// +//***************************************************************************** +// Field: [31:0] STIM14 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM14_STIM14_W 32 +#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF +#define CPU_ITM_STIM14_STIM14_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM15 +// +//***************************************************************************** +// Field: [31:0] STIM15 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM15_STIM15_W 32 +#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF +#define CPU_ITM_STIM15_STIM15_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM16 +// +//***************************************************************************** +// Field: [31:0] STIM16 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM16_STIM16_W 32 +#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF +#define CPU_ITM_STIM16_STIM16_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM17 +// +//***************************************************************************** +// Field: [31:0] STIM17 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM17_STIM17_W 32 +#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF +#define CPU_ITM_STIM17_STIM17_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM18 +// +//***************************************************************************** +// Field: [31:0] STIM18 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM18_STIM18_W 32 +#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF +#define CPU_ITM_STIM18_STIM18_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM19 +// +//***************************************************************************** +// Field: [31:0] STIM19 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM19_STIM19_W 32 +#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF +#define CPU_ITM_STIM19_STIM19_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM20 +// +//***************************************************************************** +// Field: [31:0] STIM20 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM20_STIM20_W 32 +#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF +#define CPU_ITM_STIM20_STIM20_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM21 +// +//***************************************************************************** +// Field: [31:0] STIM21 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM21_STIM21_W 32 +#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF +#define CPU_ITM_STIM21_STIM21_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM22 +// +//***************************************************************************** +// Field: [31:0] STIM22 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM22_STIM22_W 32 +#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF +#define CPU_ITM_STIM22_STIM22_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM23 +// +//***************************************************************************** +// Field: [31:0] STIM23 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM23_STIM23_W 32 +#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF +#define CPU_ITM_STIM23_STIM23_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM24 +// +//***************************************************************************** +// Field: [31:0] STIM24 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM24_STIM24_W 32 +#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF +#define CPU_ITM_STIM24_STIM24_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM25 +// +//***************************************************************************** +// Field: [31:0] STIM25 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM25_STIM25_W 32 +#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF +#define CPU_ITM_STIM25_STIM25_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM26 +// +//***************************************************************************** +// Field: [31:0] STIM26 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM26_STIM26_W 32 +#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF +#define CPU_ITM_STIM26_STIM26_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM27 +// +//***************************************************************************** +// Field: [31:0] STIM27 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM27_STIM27_W 32 +#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF +#define CPU_ITM_STIM27_STIM27_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM28 +// +//***************************************************************************** +// Field: [31:0] STIM28 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM28_STIM28_W 32 +#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF +#define CPU_ITM_STIM28_STIM28_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM29 +// +//***************************************************************************** +// Field: [31:0] STIM29 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM29_STIM29_W 32 +#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF +#define CPU_ITM_STIM29_STIM29_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM30 +// +//***************************************************************************** +// Field: [31:0] STIM30 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM30_STIM30_W 32 +#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF +#define CPU_ITM_STIM30_STIM30_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM31 +// +//***************************************************************************** +// Field: [31:0] STIM31 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM31_STIM31_W 32 +#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF +#define CPU_ITM_STIM31_STIM31_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TER +// +//***************************************************************************** +// Field: [31] STIMENA31 +// +// Bit mask to enable tracing on ITM stimulus port 31. +#define CPU_ITM_TER_STIMENA31 0x80000000 +#define CPU_ITM_TER_STIMENA31_BITN 31 +#define CPU_ITM_TER_STIMENA31_M 0x80000000 +#define CPU_ITM_TER_STIMENA31_S 31 + +// Field: [30] STIMENA30 +// +// Bit mask to enable tracing on ITM stimulus port 30. +#define CPU_ITM_TER_STIMENA30 0x40000000 +#define CPU_ITM_TER_STIMENA30_BITN 30 +#define CPU_ITM_TER_STIMENA30_M 0x40000000 +#define CPU_ITM_TER_STIMENA30_S 30 + +// Field: [29] STIMENA29 +// +// Bit mask to enable tracing on ITM stimulus port 29. +#define CPU_ITM_TER_STIMENA29 0x20000000 +#define CPU_ITM_TER_STIMENA29_BITN 29 +#define CPU_ITM_TER_STIMENA29_M 0x20000000 +#define CPU_ITM_TER_STIMENA29_S 29 + +// Field: [28] STIMENA28 +// +// Bit mask to enable tracing on ITM stimulus port 28. +#define CPU_ITM_TER_STIMENA28 0x10000000 +#define CPU_ITM_TER_STIMENA28_BITN 28 +#define CPU_ITM_TER_STIMENA28_M 0x10000000 +#define CPU_ITM_TER_STIMENA28_S 28 + +// Field: [27] STIMENA27 +// +// Bit mask to enable tracing on ITM stimulus port 27. +#define CPU_ITM_TER_STIMENA27 0x08000000 +#define CPU_ITM_TER_STIMENA27_BITN 27 +#define CPU_ITM_TER_STIMENA27_M 0x08000000 +#define CPU_ITM_TER_STIMENA27_S 27 + +// Field: [26] STIMENA26 +// +// Bit mask to enable tracing on ITM stimulus port 26. +#define CPU_ITM_TER_STIMENA26 0x04000000 +#define CPU_ITM_TER_STIMENA26_BITN 26 +#define CPU_ITM_TER_STIMENA26_M 0x04000000 +#define CPU_ITM_TER_STIMENA26_S 26 + +// Field: [25] STIMENA25 +// +// Bit mask to enable tracing on ITM stimulus port 25. +#define CPU_ITM_TER_STIMENA25 0x02000000 +#define CPU_ITM_TER_STIMENA25_BITN 25 +#define CPU_ITM_TER_STIMENA25_M 0x02000000 +#define CPU_ITM_TER_STIMENA25_S 25 + +// Field: [24] STIMENA24 +// +// Bit mask to enable tracing on ITM stimulus port 24. +#define CPU_ITM_TER_STIMENA24 0x01000000 +#define CPU_ITM_TER_STIMENA24_BITN 24 +#define CPU_ITM_TER_STIMENA24_M 0x01000000 +#define CPU_ITM_TER_STIMENA24_S 24 + +// Field: [23] STIMENA23 +// +// Bit mask to enable tracing on ITM stimulus port 23. +#define CPU_ITM_TER_STIMENA23 0x00800000 +#define CPU_ITM_TER_STIMENA23_BITN 23 +#define CPU_ITM_TER_STIMENA23_M 0x00800000 +#define CPU_ITM_TER_STIMENA23_S 23 + +// Field: [22] STIMENA22 +// +// Bit mask to enable tracing on ITM stimulus port 22. +#define CPU_ITM_TER_STIMENA22 0x00400000 +#define CPU_ITM_TER_STIMENA22_BITN 22 +#define CPU_ITM_TER_STIMENA22_M 0x00400000 +#define CPU_ITM_TER_STIMENA22_S 22 + +// Field: [21] STIMENA21 +// +// Bit mask to enable tracing on ITM stimulus port 21. +#define CPU_ITM_TER_STIMENA21 0x00200000 +#define CPU_ITM_TER_STIMENA21_BITN 21 +#define CPU_ITM_TER_STIMENA21_M 0x00200000 +#define CPU_ITM_TER_STIMENA21_S 21 + +// Field: [20] STIMENA20 +// +// Bit mask to enable tracing on ITM stimulus port 20. +#define CPU_ITM_TER_STIMENA20 0x00100000 +#define CPU_ITM_TER_STIMENA20_BITN 20 +#define CPU_ITM_TER_STIMENA20_M 0x00100000 +#define CPU_ITM_TER_STIMENA20_S 20 + +// Field: [19] STIMENA19 +// +// Bit mask to enable tracing on ITM stimulus port 19. +#define CPU_ITM_TER_STIMENA19 0x00080000 +#define CPU_ITM_TER_STIMENA19_BITN 19 +#define CPU_ITM_TER_STIMENA19_M 0x00080000 +#define CPU_ITM_TER_STIMENA19_S 19 + +// Field: [18] STIMENA18 +// +// Bit mask to enable tracing on ITM stimulus port 18. +#define CPU_ITM_TER_STIMENA18 0x00040000 +#define CPU_ITM_TER_STIMENA18_BITN 18 +#define CPU_ITM_TER_STIMENA18_M 0x00040000 +#define CPU_ITM_TER_STIMENA18_S 18 + +// Field: [17] STIMENA17 +// +// Bit mask to enable tracing on ITM stimulus port 17. +#define CPU_ITM_TER_STIMENA17 0x00020000 +#define CPU_ITM_TER_STIMENA17_BITN 17 +#define CPU_ITM_TER_STIMENA17_M 0x00020000 +#define CPU_ITM_TER_STIMENA17_S 17 + +// Field: [16] STIMENA16 +// +// Bit mask to enable tracing on ITM stimulus port 16. +#define CPU_ITM_TER_STIMENA16 0x00010000 +#define CPU_ITM_TER_STIMENA16_BITN 16 +#define CPU_ITM_TER_STIMENA16_M 0x00010000 +#define CPU_ITM_TER_STIMENA16_S 16 + +// Field: [15] STIMENA15 +// +// Bit mask to enable tracing on ITM stimulus port 15. +#define CPU_ITM_TER_STIMENA15 0x00008000 +#define CPU_ITM_TER_STIMENA15_BITN 15 +#define CPU_ITM_TER_STIMENA15_M 0x00008000 +#define CPU_ITM_TER_STIMENA15_S 15 + +// Field: [14] STIMENA14 +// +// Bit mask to enable tracing on ITM stimulus port 14. +#define CPU_ITM_TER_STIMENA14 0x00004000 +#define CPU_ITM_TER_STIMENA14_BITN 14 +#define CPU_ITM_TER_STIMENA14_M 0x00004000 +#define CPU_ITM_TER_STIMENA14_S 14 + +// Field: [13] STIMENA13 +// +// Bit mask to enable tracing on ITM stimulus port 13. +#define CPU_ITM_TER_STIMENA13 0x00002000 +#define CPU_ITM_TER_STIMENA13_BITN 13 +#define CPU_ITM_TER_STIMENA13_M 0x00002000 +#define CPU_ITM_TER_STIMENA13_S 13 + +// Field: [12] STIMENA12 +// +// Bit mask to enable tracing on ITM stimulus port 12. +#define CPU_ITM_TER_STIMENA12 0x00001000 +#define CPU_ITM_TER_STIMENA12_BITN 12 +#define CPU_ITM_TER_STIMENA12_M 0x00001000 +#define CPU_ITM_TER_STIMENA12_S 12 + +// Field: [11] STIMENA11 +// +// Bit mask to enable tracing on ITM stimulus port 11. +#define CPU_ITM_TER_STIMENA11 0x00000800 +#define CPU_ITM_TER_STIMENA11_BITN 11 +#define CPU_ITM_TER_STIMENA11_M 0x00000800 +#define CPU_ITM_TER_STIMENA11_S 11 + +// Field: [10] STIMENA10 +// +// Bit mask to enable tracing on ITM stimulus port 10. +#define CPU_ITM_TER_STIMENA10 0x00000400 +#define CPU_ITM_TER_STIMENA10_BITN 10 +#define CPU_ITM_TER_STIMENA10_M 0x00000400 +#define CPU_ITM_TER_STIMENA10_S 10 + +// Field: [9] STIMENA9 +// +// Bit mask to enable tracing on ITM stimulus port 9. +#define CPU_ITM_TER_STIMENA9 0x00000200 +#define CPU_ITM_TER_STIMENA9_BITN 9 +#define CPU_ITM_TER_STIMENA9_M 0x00000200 +#define CPU_ITM_TER_STIMENA9_S 9 + +// Field: [8] STIMENA8 +// +// Bit mask to enable tracing on ITM stimulus port 8. +#define CPU_ITM_TER_STIMENA8 0x00000100 +#define CPU_ITM_TER_STIMENA8_BITN 8 +#define CPU_ITM_TER_STIMENA8_M 0x00000100 +#define CPU_ITM_TER_STIMENA8_S 8 + +// Field: [7] STIMENA7 +// +// Bit mask to enable tracing on ITM stimulus port 7. +#define CPU_ITM_TER_STIMENA7 0x00000080 +#define CPU_ITM_TER_STIMENA7_BITN 7 +#define CPU_ITM_TER_STIMENA7_M 0x00000080 +#define CPU_ITM_TER_STIMENA7_S 7 + +// Field: [6] STIMENA6 +// +// Bit mask to enable tracing on ITM stimulus port 6. +#define CPU_ITM_TER_STIMENA6 0x00000040 +#define CPU_ITM_TER_STIMENA6_BITN 6 +#define CPU_ITM_TER_STIMENA6_M 0x00000040 +#define CPU_ITM_TER_STIMENA6_S 6 + +// Field: [5] STIMENA5 +// +// Bit mask to enable tracing on ITM stimulus port 5. +#define CPU_ITM_TER_STIMENA5 0x00000020 +#define CPU_ITM_TER_STIMENA5_BITN 5 +#define CPU_ITM_TER_STIMENA5_M 0x00000020 +#define CPU_ITM_TER_STIMENA5_S 5 + +// Field: [4] STIMENA4 +// +// Bit mask to enable tracing on ITM stimulus port 4. +#define CPU_ITM_TER_STIMENA4 0x00000010 +#define CPU_ITM_TER_STIMENA4_BITN 4 +#define CPU_ITM_TER_STIMENA4_M 0x00000010 +#define CPU_ITM_TER_STIMENA4_S 4 + +// Field: [3] STIMENA3 +// +// Bit mask to enable tracing on ITM stimulus port 3. +#define CPU_ITM_TER_STIMENA3 0x00000008 +#define CPU_ITM_TER_STIMENA3_BITN 3 +#define CPU_ITM_TER_STIMENA3_M 0x00000008 +#define CPU_ITM_TER_STIMENA3_S 3 + +// Field: [2] STIMENA2 +// +// Bit mask to enable tracing on ITM stimulus port 2. +#define CPU_ITM_TER_STIMENA2 0x00000004 +#define CPU_ITM_TER_STIMENA2_BITN 2 +#define CPU_ITM_TER_STIMENA2_M 0x00000004 +#define CPU_ITM_TER_STIMENA2_S 2 + +// Field: [1] STIMENA1 +// +// Bit mask to enable tracing on ITM stimulus port 1. +#define CPU_ITM_TER_STIMENA1 0x00000002 +#define CPU_ITM_TER_STIMENA1_BITN 1 +#define CPU_ITM_TER_STIMENA1_M 0x00000002 +#define CPU_ITM_TER_STIMENA1_S 1 + +// Field: [0] STIMENA0 +// +// Bit mask to enable tracing on ITM stimulus port 0. +#define CPU_ITM_TER_STIMENA0 0x00000001 +#define CPU_ITM_TER_STIMENA0_BITN 0 +#define CPU_ITM_TER_STIMENA0_M 0x00000001 +#define CPU_ITM_TER_STIMENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TPR +// +//***************************************************************************** +// Field: [3:0] PRIVMASK +// +// Bit mask to enable unprivileged (User) access to ITM stimulus ports: +// +// Bit [0] enables stimulus ports 0, 1, ..., and 7. +// Bit [1] enables stimulus ports 8, 9, ..., and 15. +// Bit [2] enables stimulus ports 16, 17, ..., and 23. +// Bit [3] enables stimulus ports 24, 25, ..., and 31. +// +// 0: User access allowed to stimulus ports +// 1: Privileged access only to stimulus ports +#define CPU_ITM_TPR_PRIVMASK_W 4 +#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F +#define CPU_ITM_TPR_PRIVMASK_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TCR +// +//***************************************************************************** +// Field: [23] BUSY +// +// Set when ITM events present and being drained. +#define CPU_ITM_TCR_BUSY 0x00800000 +#define CPU_ITM_TCR_BUSY_BITN 23 +#define CPU_ITM_TCR_BUSY_M 0x00800000 +#define CPU_ITM_TCR_BUSY_S 23 + +// Field: [22:16] ATBID +// +// Trace Bus ID for CoreSight system. Optional identifier for multi-source +// trace stream formatting. If multi-source trace is in use, this field must be +// written with a non-zero value. +#define CPU_ITM_TCR_ATBID_W 7 +#define CPU_ITM_TCR_ATBID_M 0x007F0000 +#define CPU_ITM_TCR_ATBID_S 16 + +// Field: [9:8] TSPRESCALE +// +// Timestamp prescaler +// ENUMs: +// DIV64 Divide by 64 +// DIV16 Divide by 16 +// DIV4 Divide by 4 +// NOPRESCALING No prescaling +#define CPU_ITM_TCR_TSPRESCALE_W 2 +#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_S 8 +#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 +#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 +#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 + +// Field: [4] SWOENA +// +// Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If +// TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of +// the timestamp counter. +// +// 0x0: Mode disabled. Timestamp counter uses system clock from the core and +// counts continuously. +// 0x1: Timestamp counter uses lineout (data related) clock from TPIU +// interface. The timestamp counter is held in reset while the output line is +// idle. +#define CPU_ITM_TCR_SWOENA 0x00000010 +#define CPU_ITM_TCR_SWOENA_BITN 4 +#define CPU_ITM_TCR_SWOENA_M 0x00000010 +#define CPU_ITM_TCR_SWOENA_S 4 + +// Field: [3] DWTENA +// +// Enables the DWT stimulus (hardware event packet emission to the TPIU from +// the DWT) +#define CPU_ITM_TCR_DWTENA 0x00000008 +#define CPU_ITM_TCR_DWTENA_BITN 3 +#define CPU_ITM_TCR_DWTENA_M 0x00000008 +#define CPU_ITM_TCR_DWTENA_S 3 + +// Field: [2] SYNCENA +// +// Enables synchronization packet transmission for a synchronous TPIU. +// CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization +// speed. +#define CPU_ITM_TCR_SYNCENA 0x00000004 +#define CPU_ITM_TCR_SYNCENA_BITN 2 +#define CPU_ITM_TCR_SYNCENA_M 0x00000004 +#define CPU_ITM_TCR_SYNCENA_S 2 + +// Field: [1] TSENA +// +// Enables differential timestamps. Differential timestamps are emitted when a +// packet is written to the FIFO with a non-zero timestamp counter, and when +// the timestamp counter overflows. Timestamps are emitted during idle times +// after a fixed number of two million cycles. This provides a time reference +// for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps +// are triggered by activity on the internal trace bus only. In this case there +// is no regular timestamp output when the ITM is idle. +#define CPU_ITM_TCR_TSENA 0x00000002 +#define CPU_ITM_TCR_TSENA_BITN 1 +#define CPU_ITM_TCR_TSENA_M 0x00000002 +#define CPU_ITM_TCR_TSENA_S 1 + +// Field: [0] ITMENA +// +// Enables ITM. This is the master enable, and must be set before ITM Stimulus +// and Trace Enable registers can be written. +#define CPU_ITM_TCR_ITMENA 0x00000001 +#define CPU_ITM_TCR_ITMENA_BITN 0 +#define CPU_ITM_TCR_ITMENA_M 0x00000001 +#define CPU_ITM_TCR_ITMENA_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_LAR +// +//***************************************************************************** +// Field: [31:0] LOCK_ACCESS +// +// A privileged write of 0xC5ACCE55 enables more write access to Control +// Registers TER, TPR and TCR. An invalid write removes write access. +#define CPU_ITM_LAR_LOCK_ACCESS_W 32 +#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF +#define CPU_ITM_LAR_LOCK_ACCESS_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_LSR +// +//***************************************************************************** +// Field: [2] BYTEACC +// +// Reads 0 which means 8-bit lock access is not be implemented. +#define CPU_ITM_LSR_BYTEACC 0x00000004 +#define CPU_ITM_LSR_BYTEACC_BITN 2 +#define CPU_ITM_LSR_BYTEACC_M 0x00000004 +#define CPU_ITM_LSR_BYTEACC_S 2 + +// Field: [1] ACCESS +// +// Write access to component is blocked. All writes are ignored, reads are +// permitted. +#define CPU_ITM_LSR_ACCESS 0x00000002 +#define CPU_ITM_LSR_ACCESS_BITN 1 +#define CPU_ITM_LSR_ACCESS_M 0x00000002 +#define CPU_ITM_LSR_ACCESS_S 1 + +// Field: [0] PRESENT +// +// Indicates that a lock mechanism exists for this component. +#define CPU_ITM_LSR_PRESENT 0x00000001 +#define CPU_ITM_LSR_PRESENT_BITN 0 +#define CPU_ITM_LSR_PRESENT_M 0x00000001 +#define CPU_ITM_LSR_PRESENT_S 0 + + +#endif // __CPU_ITM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_rom_table.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_rom_table.h new file mode 100644 index 0000000..43c9a9f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_rom_table.h @@ -0,0 +1,220 @@ +/****************************************************************************** +* Filename: hw_cpu_rom_table_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_ROM_TABLE_H__ +#define __HW_CPU_ROM_TABLE_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_ROM_TABLE component +// +//***************************************************************************** +// System Control Space Component +#define CPU_ROM_TABLE_O_SCS 0x00000000 + +// Data Watchpoint and Trace Component +#define CPU_ROM_TABLE_O_DWT 0x00000004 + +// Flash Patch and Breakpoint Component +#define CPU_ROM_TABLE_O_FPB 0x00000008 + +// Instrumentation Trace Component +#define CPU_ROM_TABLE_O_ITM 0x0000000C + +// Trace Port Interface Component +#define CPU_ROM_TABLE_O_TPIU 0x00000010 + +// Enhanced Trace Component +#define CPU_ROM_TABLE_O_ETM 0x00000014 + +// End Marker +#define CPU_ROM_TABLE_O_END 0x00000018 + +// System Memory Map Access for DAP +#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_SCS +// +//***************************************************************************** +// Field: [31:0] SCS +// +// Points to the SCS at 0xE000E000. +// (SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000. +#define CPU_ROM_TABLE_SCS_SCS_W 32 +#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF +#define CPU_ROM_TABLE_SCS_SCS_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_DWT +// +//***************************************************************************** +// Field: [31:1] DWT +// +// Points to the Data Watchpoint and Trace block at 0xE0001000. +// (2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000. +#define CPU_ROM_TABLE_DWT_DWT_W 31 +#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE +#define CPU_ROM_TABLE_DWT_DWT_S 1 + +// Field: [0] DWT_PRESENT +// +// 0: DWT is not present +// 1: DWT is present. +#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_FPB +// +//***************************************************************************** +// Field: [31:1] FPB +// +// Points to the Flash Patch and Breakpoint block at 0xE0002000. +// (2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000. +#define CPU_ROM_TABLE_FPB_FPB_W 31 +#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE +#define CPU_ROM_TABLE_FPB_FPB_S 1 + +// Field: [0] FPB_PRESENT +// +// 0: FPB is not present +// 1: FPB is present. +#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_ITM +// +//***************************************************************************** +// Field: [31:1] ITM +// +// Points to the Instrumentation Trace block at 0xE0000000. +// (2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000. +#define CPU_ROM_TABLE_ITM_ITM_W 31 +#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ITM_ITM_S 1 + +// Field: [0] ITM_PRESENT +// +// 0: ITM is not present +// 1: ITM is present. +#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_TPIU +// +//***************************************************************************** +// Field: [31:1] TPIU +// +// Points to the TPIU. TPIU is at 0xE0040000. +// (2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000. +#define CPU_ROM_TABLE_TPIU_TPIU_W 31 +#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE +#define CPU_ROM_TABLE_TPIU_TPIU_S 1 + +// Field: [0] TPIU_PRESENT +// +// 0: TPIU is not present +// 1: TPIU is present. +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_ETM +// +//***************************************************************************** +// Field: [31:1] ETM +// +// Points to the ETM. ETM is at 0xE0041000. +// (2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000. +#define CPU_ROM_TABLE_ETM_ETM_W 31 +#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ETM_ETM_S 1 + +// Field: [0] ETM_PRESENT +// +// 0: ETM is not present +// 1: ETM is present. +#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_END +// +//***************************************************************************** +// Field: [31:0] END +// +// End of the ROM table +#define CPU_ROM_TABLE_END_END_W 32 +#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF +#define CPU_ROM_TABLE_END_END_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_SYSTEM_ACCESS +// +//***************************************************************************** +// Field: [0] SYSTEM_ACCESS +// +// 1: The system memory map is accessible using the DAP +// 0: Only debug resources are accessible using the DAP +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 + + +#endif // __CPU_ROM_TABLE__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_scs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_scs.h new file mode 100644 index 0000000..c7fa660 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_scs.h @@ -0,0 +1,3885 @@ +/****************************************************************************** +* Filename: hw_cpu_scs_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_SCS_H__ +#define __HW_CPU_SCS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_SCS component +// +//***************************************************************************** +// Interrupt Control Type +#define CPU_SCS_O_ICTR 0x00000004 + +// Auxiliary Control +#define CPU_SCS_O_ACTLR 0x00000008 + +// SysTick Control and Status +#define CPU_SCS_O_STCSR 0x00000010 + +// SysTick Reload Value +#define CPU_SCS_O_STRVR 0x00000014 + +// SysTick Current Value +#define CPU_SCS_O_STCVR 0x00000018 + +// SysTick Calibration Value +#define CPU_SCS_O_STCR 0x0000001C + +// Irq 0 to 31 Set Enable +#define CPU_SCS_O_NVIC_ISER0 0x00000100 + +// Irq 32 to 63 Set Enable +#define CPU_SCS_O_NVIC_ISER1 0x00000104 + +// Irq 0 to 31 Clear Enable +#define CPU_SCS_O_NVIC_ICER0 0x00000180 + +// Irq 32 to 63 Clear Enable +#define CPU_SCS_O_NVIC_ICER1 0x00000184 + +// Irq 0 to 31 Set Pending +#define CPU_SCS_O_NVIC_ISPR0 0x00000200 + +// Irq 32 to 63 Set Pending +#define CPU_SCS_O_NVIC_ISPR1 0x00000204 + +// Irq 0 to 31 Clear Pending +#define CPU_SCS_O_NVIC_ICPR0 0x00000280 + +// Irq 32 to 63 Clear Pending +#define CPU_SCS_O_NVIC_ICPR1 0x00000284 + +// Irq 0 to 31 Active Bit +#define CPU_SCS_O_NVIC_IABR0 0x00000300 + +// Irq 32 to 63 Active Bit +#define CPU_SCS_O_NVIC_IABR1 0x00000304 + +// Irq 0 to 3 Priority +#define CPU_SCS_O_NVIC_IPR0 0x00000400 + +// Irq 4 to 7 Priority +#define CPU_SCS_O_NVIC_IPR1 0x00000404 + +// Irq 8 to 11 Priority +#define CPU_SCS_O_NVIC_IPR2 0x00000408 + +// Irq 12 to 15 Priority +#define CPU_SCS_O_NVIC_IPR3 0x0000040C + +// Irq 16 to 19 Priority +#define CPU_SCS_O_NVIC_IPR4 0x00000410 + +// Irq 20 to 23 Priority +#define CPU_SCS_O_NVIC_IPR5 0x00000414 + +// Irq 24 to 27 Priority +#define CPU_SCS_O_NVIC_IPR6 0x00000418 + +// Irq 28 to 31 Priority +#define CPU_SCS_O_NVIC_IPR7 0x0000041C + +// Irq 32 to 35 Priority +#define CPU_SCS_O_NVIC_IPR8 0x00000420 + +// CPUID Base +#define CPU_SCS_O_CPUID 0x00000D00 + +// Interrupt Control State +#define CPU_SCS_O_ICSR 0x00000D04 + +// Vector Table Offset +#define CPU_SCS_O_VTOR 0x00000D08 + +// Application Interrupt/Reset Control +#define CPU_SCS_O_AIRCR 0x00000D0C + +// System Control +#define CPU_SCS_O_SCR 0x00000D10 + +// Configuration Control +#define CPU_SCS_O_CCR 0x00000D14 + +// System Handlers 4-7 Priority +#define CPU_SCS_O_SHPR1 0x00000D18 + +// System Handlers 8-11 Priority +#define CPU_SCS_O_SHPR2 0x00000D1C + +// System Handlers 12-15 Priority +#define CPU_SCS_O_SHPR3 0x00000D20 + +// System Handler Control and State +#define CPU_SCS_O_SHCSR 0x00000D24 + +// Configurable Fault Status +#define CPU_SCS_O_CFSR 0x00000D28 + +// Hard Fault Status +#define CPU_SCS_O_HFSR 0x00000D2C + +// Debug Fault Status +#define CPU_SCS_O_DFSR 0x00000D30 + +// Mem Manage Fault Address +#define CPU_SCS_O_MMFAR 0x00000D34 + +// Bus Fault Address +#define CPU_SCS_O_BFAR 0x00000D38 + +// Auxiliary Fault Status +#define CPU_SCS_O_AFSR 0x00000D3C + +// Processor Feature 0 +#define CPU_SCS_O_ID_PFR0 0x00000D40 + +// Processor Feature 1 +#define CPU_SCS_O_ID_PFR1 0x00000D44 + +// Debug Feature 0 +#define CPU_SCS_O_ID_DFR0 0x00000D48 + +// Auxiliary Feature 0 +#define CPU_SCS_O_ID_AFR0 0x00000D4C + +// Memory Model Feature 0 +#define CPU_SCS_O_ID_MMFR0 0x00000D50 + +// Memory Model Feature 1 +#define CPU_SCS_O_ID_MMFR1 0x00000D54 + +// Memory Model Feature 2 +#define CPU_SCS_O_ID_MMFR2 0x00000D58 + +// Memory Model Feature 3 +#define CPU_SCS_O_ID_MMFR3 0x00000D5C + +// ISA Feature 0 +#define CPU_SCS_O_ID_ISAR0 0x00000D60 + +// ISA Feature 1 +#define CPU_SCS_O_ID_ISAR1 0x00000D64 + +// ISA Feature 2 +#define CPU_SCS_O_ID_ISAR2 0x00000D68 + +// ISA Feature 3 +#define CPU_SCS_O_ID_ISAR3 0x00000D6C + +// ISA Feature 4 +#define CPU_SCS_O_ID_ISAR4 0x00000D70 + +// Coprocessor Access Control +#define CPU_SCS_O_CPACR 0x00000D88 + +// Debug Halting Control and Status +#define CPU_SCS_O_DHCSR 0x00000DF0 + +// Deubg Core Register Selector +#define CPU_SCS_O_DCRSR 0x00000DF4 + +// Debug Core Register Data +#define CPU_SCS_O_DCRDR 0x00000DF8 + +// Debug Exception and Monitor Control +#define CPU_SCS_O_DEMCR 0x00000DFC + +// Software Trigger Interrupt +#define CPU_SCS_O_STIR 0x00000F00 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ICTR +// +//***************************************************************************** +// Field: [2:0] INTLINESNUM +// +// Total number of interrupt lines in groups of 32. +// +// 0: 0...32 +// 1: 33...64 +// 2: 65...96 +// 3: 97...128 +// 4: 129...160 +// 5: 161...192 +// 6: 193...224 +// 7: 225...256 +#define CPU_SCS_ICTR_INTLINESNUM_W 3 +#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 +#define CPU_SCS_ICTR_INTLINESNUM_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ACTLR +// +//***************************************************************************** +// Field: [2] DISFOLD +// +// Disables folding of IT instruction. +#define CPU_SCS_ACTLR_DISFOLD 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_BITN 2 +#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_S 2 + +// Field: [1] DISDEFWBUF +// +// Disables write buffer use during default memory map accesses. This causes +// all bus faults to be precise bus faults but decreases the performance of the +// processor because the stores to memory have to complete before the next +// instruction can be executed. +#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 +#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 + +// Field: [0] DISMCYCINT +// +// Disables interruption of multi-cycle instructions. This increases the +// interrupt latency of the processor becuase LDM/STM completes before +// interrupt stacking occurs. +#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 +#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCSR +// +//***************************************************************************** +// Field: [16] COUNTFLAG +// +// Returns 1 if timer counted to 0 since last time this was read. Clears on +// read by application of any part of the SysTick Control and Status Register. +// If read by the debugger using the DAP, this bit is cleared on read-only if +// the MasterType bit in the **AHB-AP** Control Register is set to 0. +// Otherwise, COUNTFLAG is not changed by the debugger read. +#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 +#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_S 16 + +// Field: [2] CLKSOURCE +// +// Clock source: +// +// 0: External reference clock. +// 1: Core clock +// +// External clock is not available in this device. Writes to this field will be +// ignored. +#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 +#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_S 2 + +// Field: [1] TICKINT +// +// 0: Counting down to zero does not pend the SysTick handler. Software can use +// COUNTFLAG to determine if the SysTick handler has ever counted to zero. +// 1: Counting down to zero pends the SysTick handler. +#define CPU_SCS_STCSR_TICKINT 0x00000002 +#define CPU_SCS_STCSR_TICKINT_BITN 1 +#define CPU_SCS_STCSR_TICKINT_M 0x00000002 +#define CPU_SCS_STCSR_TICKINT_S 1 + +// Field: [0] ENABLE +// +// Enable SysTick counter +// +// 0: Counter disabled +// 1: Counter operates in a multi-shot way. That is, counter loads with the +// Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it +// sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on +// TICKINT. It then loads STRVR.RELOAD again, and begins counting. +#define CPU_SCS_STCSR_ENABLE 0x00000001 +#define CPU_SCS_STCSR_ENABLE_BITN 0 +#define CPU_SCS_STCSR_ENABLE_M 0x00000001 +#define CPU_SCS_STCSR_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STRVR +// +//***************************************************************************** +// Field: [23:0] RELOAD +// +// Value to load into the SysTick Current Value Register STCVR.CURRENT when the +// counter reaches 0. +#define CPU_SCS_STRVR_RELOAD_W 24 +#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF +#define CPU_SCS_STRVR_RELOAD_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCVR +// +//***************************************************************************** +// Field: [23:0] CURRENT +// +// Current value at the time the register is accessed. No read-modify-write +// protection is provided, so change with care. Writing to it with any value +// clears the register to 0. Clearing this register also clears +// STCSR.COUNTFLAG. +#define CPU_SCS_STCVR_CURRENT_W 24 +#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF +#define CPU_SCS_STCVR_CURRENT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCR +// +//***************************************************************************** +// Field: [31] NOREF +// +// Reads as one. Indicates that no separate reference clock is provided. +#define CPU_SCS_STCR_NOREF 0x80000000 +#define CPU_SCS_STCR_NOREF_BITN 31 +#define CPU_SCS_STCR_NOREF_M 0x80000000 +#define CPU_SCS_STCR_NOREF_S 31 + +// Field: [30] SKEW +// +// Reads as one. The calibration value is not exactly 10ms because of clock +// frequency. This could affect its suitability as a software real time clock. +#define CPU_SCS_STCR_SKEW 0x40000000 +#define CPU_SCS_STCR_SKEW_BITN 30 +#define CPU_SCS_STCR_SKEW_M 0x40000000 +#define CPU_SCS_STCR_SKEW_S 30 + +// Field: [23:0] TENMS +// +// An optional Reload value to be used for 10ms (100Hz) timing, subject to +// system clock skew errors. The value read is valid only when core clock is at +// 48MHz. +#define CPU_SCS_STCR_TENMS_W 24 +#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF +#define CPU_SCS_STCR_TENMS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISER0 +// +//***************************************************************************** +// Field: [31] SETENA31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 +#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 + +// Field: [30] SETENA30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 +#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 + +// Field: [29] SETENA29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 +#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 + +// Field: [28] SETENA28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 +#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 + +// Field: [27] SETENA27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 +#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 + +// Field: [26] SETENA26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 +#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 + +// Field: [25] SETENA25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 +#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 + +// Field: [24] SETENA24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 +#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 + +// Field: [23] SETENA23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 +#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 + +// Field: [22] SETENA22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 +#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 + +// Field: [21] SETENA21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 +#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 + +// Field: [20] SETENA20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 +#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 + +// Field: [19] SETENA19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 +#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 + +// Field: [18] SETENA18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 +#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 + +// Field: [17] SETENA17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 +#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 + +// Field: [16] SETENA16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 +#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 + +// Field: [15] SETENA15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 +#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 + +// Field: [14] SETENA14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 +#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 + +// Field: [13] SETENA13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 +#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 + +// Field: [12] SETENA12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 +#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 + +// Field: [11] SETENA11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 +#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 + +// Field: [10] SETENA10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 +#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 + +// Field: [9] SETENA9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 +#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 + +// Field: [8] SETENA8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 +#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 + +// Field: [7] SETENA7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 +#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 + +// Field: [6] SETENA6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 +#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 + +// Field: [5] SETENA5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 +#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 + +// Field: [4] SETENA4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 +#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 + +// Field: [3] SETENA3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 +#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 + +// Field: [2] SETENA2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 +#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 + +// Field: [1] SETENA1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 +#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 + +// Field: [0] SETENA0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 +#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISER1 +// +//***************************************************************************** +// Field: [1] SETENA33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 +#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 + +// Field: [0] SETENA32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 +#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICER0 +// +//***************************************************************************** +// Field: [31] CLRENA31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 +#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 + +// Field: [30] CLRENA30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 +#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 + +// Field: [29] CLRENA29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 +#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 + +// Field: [28] CLRENA28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 +#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 + +// Field: [27] CLRENA27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 +#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 + +// Field: [26] CLRENA26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 +#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 + +// Field: [25] CLRENA25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 +#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 + +// Field: [24] CLRENA24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 +#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 + +// Field: [23] CLRENA23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 +#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 + +// Field: [22] CLRENA22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 +#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 + +// Field: [21] CLRENA21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 +#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 + +// Field: [20] CLRENA20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 +#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 + +// Field: [19] CLRENA19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 +#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 + +// Field: [18] CLRENA18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 +#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 + +// Field: [17] CLRENA17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 +#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 + +// Field: [16] CLRENA16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 +#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 + +// Field: [15] CLRENA15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 +#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 + +// Field: [14] CLRENA14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 +#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 + +// Field: [13] CLRENA13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 +#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 + +// Field: [12] CLRENA12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 +#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 + +// Field: [11] CLRENA11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 +#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 + +// Field: [10] CLRENA10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 +#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 + +// Field: [9] CLRENA9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 +#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 + +// Field: [8] CLRENA8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 +#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 + +// Field: [7] CLRENA7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 +#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 + +// Field: [6] CLRENA6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 +#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 + +// Field: [5] CLRENA5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 +#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 + +// Field: [4] CLRENA4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 +#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 + +// Field: [3] CLRENA3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 +#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 + +// Field: [2] CLRENA2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 +#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 + +// Field: [1] CLRENA1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 +#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 + +// Field: [0] CLRENA0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 +#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICER1 +// +//***************************************************************************** +// Field: [1] CLRENA33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 +#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 + +// Field: [0] CLRENA32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 +#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISPR0 +// +//***************************************************************************** +// Field: [31] SETPEND31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 + +// Field: [30] SETPEND30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 + +// Field: [29] SETPEND29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 + +// Field: [28] SETPEND28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 + +// Field: [27] SETPEND27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 + +// Field: [26] SETPEND26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 + +// Field: [25] SETPEND25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 + +// Field: [24] SETPEND24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 + +// Field: [23] SETPEND23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 + +// Field: [22] SETPEND22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 + +// Field: [21] SETPEND21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 + +// Field: [20] SETPEND20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 + +// Field: [19] SETPEND19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 + +// Field: [18] SETPEND18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 + +// Field: [17] SETPEND17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 + +// Field: [16] SETPEND16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 + +// Field: [15] SETPEND15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 + +// Field: [14] SETPEND14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 + +// Field: [13] SETPEND13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 + +// Field: [12] SETPEND12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 + +// Field: [11] SETPEND11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 + +// Field: [10] SETPEND10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 + +// Field: [9] SETPEND9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 + +// Field: [8] SETPEND8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 + +// Field: [7] SETPEND7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 + +// Field: [6] SETPEND6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 + +// Field: [5] SETPEND5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 + +// Field: [4] SETPEND4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 + +// Field: [3] SETPEND3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 + +// Field: [2] SETPEND2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 + +// Field: [1] SETPEND1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 + +// Field: [0] SETPEND0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISPR1 +// +//***************************************************************************** +// Field: [1] SETPEND33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 + +// Field: [0] SETPEND32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICPR0 +// +//***************************************************************************** +// Field: [31] CLRPEND31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 + +// Field: [30] CLRPEND30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 + +// Field: [29] CLRPEND29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 + +// Field: [28] CLRPEND28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 + +// Field: [27] CLRPEND27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 + +// Field: [26] CLRPEND26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 + +// Field: [25] CLRPEND25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 + +// Field: [24] CLRPEND24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 + +// Field: [23] CLRPEND23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 + +// Field: [22] CLRPEND22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 + +// Field: [21] CLRPEND21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 + +// Field: [20] CLRPEND20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 + +// Field: [19] CLRPEND19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 + +// Field: [18] CLRPEND18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 + +// Field: [17] CLRPEND17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 + +// Field: [16] CLRPEND16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 + +// Field: [15] CLRPEND15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 + +// Field: [14] CLRPEND14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 + +// Field: [13] CLRPEND13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 + +// Field: [12] CLRPEND12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 + +// Field: [11] CLRPEND11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 + +// Field: [10] CLRPEND10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 + +// Field: [9] CLRPEND9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 + +// Field: [8] CLRPEND8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 + +// Field: [7] CLRPEND7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 + +// Field: [6] CLRPEND6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 + +// Field: [5] CLRPEND5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 + +// Field: [4] CLRPEND4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 + +// Field: [3] CLRPEND3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 + +// Field: [2] CLRPEND2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 + +// Field: [1] CLRPEND1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 + +// Field: [0] CLRPEND0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICPR1 +// +//***************************************************************************** +// Field: [1] CLRPEND33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 + +// Field: [0] CLRPEND32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IABR0 +// +//***************************************************************************** +// Field: [31] ACTIVE31 +// +// Reading 0 from this bit implies that interrupt line 31 is not active. +// Reading 1 from this bit implies that the interrupt line 31 is active (See +// EVENT:CPUIRQSEL31.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 + +// Field: [30] ACTIVE30 +// +// Reading 0 from this bit implies that interrupt line 30 is not active. +// Reading 1 from this bit implies that the interrupt line 30 is active (See +// EVENT:CPUIRQSEL30.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 + +// Field: [29] ACTIVE29 +// +// Reading 0 from this bit implies that interrupt line 29 is not active. +// Reading 1 from this bit implies that the interrupt line 29 is active (See +// EVENT:CPUIRQSEL29.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 + +// Field: [28] ACTIVE28 +// +// Reading 0 from this bit implies that interrupt line 28 is not active. +// Reading 1 from this bit implies that the interrupt line 28 is active (See +// EVENT:CPUIRQSEL28.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 + +// Field: [27] ACTIVE27 +// +// Reading 0 from this bit implies that interrupt line 27 is not active. +// Reading 1 from this bit implies that the interrupt line 27 is active (See +// EVENT:CPUIRQSEL27.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 + +// Field: [26] ACTIVE26 +// +// Reading 0 from this bit implies that interrupt line 26 is not active. +// Reading 1 from this bit implies that the interrupt line 26 is active (See +// EVENT:CPUIRQSEL26.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 + +// Field: [25] ACTIVE25 +// +// Reading 0 from this bit implies that interrupt line 25 is not active. +// Reading 1 from this bit implies that the interrupt line 25 is active (See +// EVENT:CPUIRQSEL25.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 + +// Field: [24] ACTIVE24 +// +// Reading 0 from this bit implies that interrupt line 24 is not active. +// Reading 1 from this bit implies that the interrupt line 24 is active (See +// EVENT:CPUIRQSEL24.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 + +// Field: [23] ACTIVE23 +// +// Reading 0 from this bit implies that interrupt line 23 is not active. +// Reading 1 from this bit implies that the interrupt line 23 is active (See +// EVENT:CPUIRQSEL23.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 + +// Field: [22] ACTIVE22 +// +// Reading 0 from this bit implies that interrupt line 22 is not active. +// Reading 1 from this bit implies that the interrupt line 22 is active (See +// EVENT:CPUIRQSEL22.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 + +// Field: [21] ACTIVE21 +// +// Reading 0 from this bit implies that interrupt line 21 is not active. +// Reading 1 from this bit implies that the interrupt line 21 is active (See +// EVENT:CPUIRQSEL21.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 + +// Field: [20] ACTIVE20 +// +// Reading 0 from this bit implies that interrupt line 20 is not active. +// Reading 1 from this bit implies that the interrupt line 20 is active (See +// EVENT:CPUIRQSEL20.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 + +// Field: [19] ACTIVE19 +// +// Reading 0 from this bit implies that interrupt line 19 is not active. +// Reading 1 from this bit implies that the interrupt line 19 is active (See +// EVENT:CPUIRQSEL19.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 + +// Field: [18] ACTIVE18 +// +// Reading 0 from this bit implies that interrupt line 18 is not active. +// Reading 1 from this bit implies that the interrupt line 18 is active (See +// EVENT:CPUIRQSEL18.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 + +// Field: [17] ACTIVE17 +// +// Reading 0 from this bit implies that interrupt line 17 is not active. +// Reading 1 from this bit implies that the interrupt line 17 is active (See +// EVENT:CPUIRQSEL17.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 + +// Field: [16] ACTIVE16 +// +// Reading 0 from this bit implies that interrupt line 16 is not active. +// Reading 1 from this bit implies that the interrupt line 16 is active (See +// EVENT:CPUIRQSEL16.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 + +// Field: [15] ACTIVE15 +// +// Reading 0 from this bit implies that interrupt line 15 is not active. +// Reading 1 from this bit implies that the interrupt line 15 is active (See +// EVENT:CPUIRQSEL15.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 + +// Field: [14] ACTIVE14 +// +// Reading 0 from this bit implies that interrupt line 14 is not active. +// Reading 1 from this bit implies that the interrupt line 14 is active (See +// EVENT:CPUIRQSEL14.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 + +// Field: [13] ACTIVE13 +// +// Reading 0 from this bit implies that interrupt line 13 is not active. +// Reading 1 from this bit implies that the interrupt line 13 is active (See +// EVENT:CPUIRQSEL13.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 + +// Field: [12] ACTIVE12 +// +// Reading 0 from this bit implies that interrupt line 12 is not active. +// Reading 1 from this bit implies that the interrupt line 12 is active (See +// EVENT:CPUIRQSEL12.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 + +// Field: [11] ACTIVE11 +// +// Reading 0 from this bit implies that interrupt line 11 is not active. +// Reading 1 from this bit implies that the interrupt line 11 is active (See +// EVENT:CPUIRQSEL11.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 + +// Field: [10] ACTIVE10 +// +// Reading 0 from this bit implies that interrupt line 10 is not active. +// Reading 1 from this bit implies that the interrupt line 10 is active (See +// EVENT:CPUIRQSEL10.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 + +// Field: [9] ACTIVE9 +// +// Reading 0 from this bit implies that interrupt line 9 is not active. Reading +// 1 from this bit implies that the interrupt line 9 is active (See +// EVENT:CPUIRQSEL9.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 + +// Field: [8] ACTIVE8 +// +// Reading 0 from this bit implies that interrupt line 8 is not active. Reading +// 1 from this bit implies that the interrupt line 8 is active (See +// EVENT:CPUIRQSEL8.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 + +// Field: [7] ACTIVE7 +// +// Reading 0 from this bit implies that interrupt line 7 is not active. Reading +// 1 from this bit implies that the interrupt line 7 is active (See +// EVENT:CPUIRQSEL7.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 + +// Field: [6] ACTIVE6 +// +// Reading 0 from this bit implies that interrupt line 6 is not active. Reading +// 1 from this bit implies that the interrupt line 6 is active (See +// EVENT:CPUIRQSEL6.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 + +// Field: [5] ACTIVE5 +// +// Reading 0 from this bit implies that interrupt line 5 is not active. Reading +// 1 from this bit implies that the interrupt line 5 is active (See +// EVENT:CPUIRQSEL5.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 + +// Field: [4] ACTIVE4 +// +// Reading 0 from this bit implies that interrupt line 4 is not active. Reading +// 1 from this bit implies that the interrupt line 4 is active (See +// EVENT:CPUIRQSEL4.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 + +// Field: [3] ACTIVE3 +// +// Reading 0 from this bit implies that interrupt line 3 is not active. Reading +// 1 from this bit implies that the interrupt line 3 is active (See +// EVENT:CPUIRQSEL3.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 + +// Field: [2] ACTIVE2 +// +// Reading 0 from this bit implies that interrupt line 2 is not active. Reading +// 1 from this bit implies that the interrupt line 2 is active (See +// EVENT:CPUIRQSEL2.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 + +// Field: [1] ACTIVE1 +// +// Reading 0 from this bit implies that interrupt line 1 is not active. Reading +// 1 from this bit implies that the interrupt line 1 is active (See +// EVENT:CPUIRQSEL1.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 + +// Field: [0] ACTIVE0 +// +// Reading 0 from this bit implies that interrupt line 0 is not active. Reading +// 1 from this bit implies that the interrupt line 0 is active (See +// EVENT:CPUIRQSEL0.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IABR1 +// +//***************************************************************************** +// Field: [1] ACTIVE33 +// +// Reading 0 from this bit implies that interrupt line 33 is not active. +// Reading 1 from this bit implies that the interrupt line 33 is active (See +// EVENT:CPUIRQSEL33.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 + +// Field: [0] ACTIVE32 +// +// Reading 0 from this bit implies that interrupt line 32 is not active. +// Reading 1 from this bit implies that the interrupt line 32 is active (See +// EVENT:CPUIRQSEL32.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR0 +// +//***************************************************************************** +// Field: [31:24] PRI_3 +// +// Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 +#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 + +// Field: [23:16] PRI_2 +// +// Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 + +// Field: [15:8] PRI_1 +// +// Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 + +// Field: [7:0] PRI_0 +// +// Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF +#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR1 +// +//***************************************************************************** +// Field: [31:24] PRI_7 +// +// Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 +#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 + +// Field: [23:16] PRI_6 +// +// Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 + +// Field: [15:8] PRI_5 +// +// Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 + +// Field: [7:0] PRI_4 +// +// Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF +#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR2 +// +//***************************************************************************** +// Field: [31:24] PRI_11 +// +// Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 + +// Field: [23:16] PRI_10 +// +// Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 + +// Field: [15:8] PRI_9 +// +// Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 + +// Field: [7:0] PRI_8 +// +// Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF +#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR3 +// +//***************************************************************************** +// Field: [31:24] PRI_15 +// +// Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 + +// Field: [23:16] PRI_14 +// +// Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 + +// Field: [15:8] PRI_13 +// +// Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 + +// Field: [7:0] PRI_12 +// +// Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF +#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR4 +// +//***************************************************************************** +// Field: [31:24] PRI_19 +// +// Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 +#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 + +// Field: [23:16] PRI_18 +// +// Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 + +// Field: [15:8] PRI_17 +// +// Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 + +// Field: [7:0] PRI_16 +// +// Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF +#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR5 +// +//***************************************************************************** +// Field: [31:24] PRI_23 +// +// Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 +#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 + +// Field: [23:16] PRI_22 +// +// Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 + +// Field: [15:8] PRI_21 +// +// Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 + +// Field: [7:0] PRI_20 +// +// Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF +#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR6 +// +//***************************************************************************** +// Field: [31:24] PRI_27 +// +// Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 +#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 + +// Field: [23:16] PRI_26 +// +// Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 + +// Field: [15:8] PRI_25 +// +// Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 + +// Field: [7:0] PRI_24 +// +// Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF +#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR7 +// +//***************************************************************************** +// Field: [31:24] PRI_31 +// +// Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 +#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 + +// Field: [23:16] PRI_30 +// +// Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 + +// Field: [15:8] PRI_29 +// +// Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 + +// Field: [7:0] PRI_28 +// +// Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF +#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR8 +// +//***************************************************************************** +// Field: [15:8] PRI_33 +// +// Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 + +// Field: [7:0] PRI_32 +// +// Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF +#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CPUID +// +//***************************************************************************** +// Field: [31:24] IMPLEMENTER +// +// Implementor code. +#define CPU_SCS_CPUID_IMPLEMENTER_W 8 +#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 +#define CPU_SCS_CPUID_IMPLEMENTER_S 24 + +// Field: [23:20] VARIANT +// +// Implementation defined variant number. +#define CPU_SCS_CPUID_VARIANT_W 4 +#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 +#define CPU_SCS_CPUID_VARIANT_S 20 + +// Field: [19:16] CONSTANT +// +// Reads as 0xF +#define CPU_SCS_CPUID_CONSTANT_W 4 +#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 +#define CPU_SCS_CPUID_CONSTANT_S 16 + +// Field: [15:4] PARTNO +// +// Number of processor within family. +#define CPU_SCS_CPUID_PARTNO_W 12 +#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 +#define CPU_SCS_CPUID_PARTNO_S 4 + +// Field: [3:0] REVISION +// +// Implementation defined revision number. +#define CPU_SCS_CPUID_REVISION_W 4 +#define CPU_SCS_CPUID_REVISION_M 0x0000000F +#define CPU_SCS_CPUID_REVISION_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ICSR +// +//***************************************************************************** +// Field: [31] NMIPENDSET +// +// Set pending NMI bit. Setting this bit pends and activates an NMI. Because +// NMI is the highest-priority interrupt, it takes effect as soon as it +// registers. +// +// 0: No action +// 1: Set pending NMI +#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 +#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_S 31 + +// Field: [28] PENDSVSET +// +// Set pending pendSV bit. +// +// 0: No action +// 1: Set pending PendSV +#define CPU_SCS_ICSR_PENDSVSET 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_BITN 28 +#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_S 28 + +// Field: [27] PENDSVCLR +// +// Clear pending pendSV bit +// +// 0: No action +// 1: Clear pending pendSV +#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 +#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_S 27 + +// Field: [26] PENDSTSET +// +// Set a pending SysTick bit. +// +// 0: No action +// 1: Set pending SysTick +#define CPU_SCS_ICSR_PENDSTSET 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_BITN 26 +#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_S 26 + +// Field: [25] PENDSTCLR +// +// Clear pending SysTick bit +// +// 0: No action +// 1: Clear pending SysTick +#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 +#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_S 25 + +// Field: [23] ISRPREEMPT +// +// This field can only be used at debug time. It indicates that a pending +// interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, +// the interrupt is serviced. +// +// 0: A pending exception is not serviced. +// 1: A pending exception is serviced on exit from the debug halt state +#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 +#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_S 23 + +// Field: [22] ISRPENDING +// +// Interrupt pending flag. Excludes NMI and faults. +// +// 0x0: Interrupt not pending +// 0x1: Interrupt pending +#define CPU_SCS_ICSR_ISRPENDING 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_BITN 22 +#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_S 22 + +// Field: [17:12] VECTPENDING +// +// Pending ISR number field. This field contains the interrupt number of the +// highest priority pending ISR. +#define CPU_SCS_ICSR_VECTPENDING_W 6 +#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 +#define CPU_SCS_ICSR_VECTPENDING_S 12 + +// Field: [11] RETTOBASE +// +// Indicates whether there are preempted active exceptions: +// +// 0: There are preempted active exceptions to execute +// 1: There are no active exceptions, or the currently-executing exception is +// the only active exception. +#define CPU_SCS_ICSR_RETTOBASE 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_BITN 11 +#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_S 11 + +// Field: [8:0] VECTACTIVE +// +// Active ISR number field. Reset clears this field. +#define CPU_SCS_ICSR_VECTACTIVE_W 9 +#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF +#define CPU_SCS_ICSR_VECTACTIVE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_VTOR +// +//***************************************************************************** +// Field: [29:7] TBLOFF +// +// Bits 29 down to 7 of the vector table base offset. +#define CPU_SCS_VTOR_TBLOFF_W 23 +#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 +#define CPU_SCS_VTOR_TBLOFF_S 7 + +//***************************************************************************** +// +// Register: CPU_SCS_O_AIRCR +// +//***************************************************************************** +// Field: [31:16] VECTKEY +// +// Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. +// Otherwise the write value is ignored. Read always returns 0xFA05. +#define CPU_SCS_AIRCR_VECTKEY_W 16 +#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 +#define CPU_SCS_AIRCR_VECTKEY_S 16 + +// Field: [15] ENDIANESS +// +// Data endianness bit +// ENUMs: +// BIG Big endian +// LITTLE Little endian +#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 +#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_S 15 +#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 + +// Field: [10:8] PRIGROUP +// +// Interrupt priority grouping field. This field is a binary point position +// indicator for creating subpriorities for exceptions that share the same +// pre-emption level. It divides the PRI_n field in the Interrupt Priority +// Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption +// level and a subpriority level. The binary point is a left-of value. This +// means that the PRIGROUP value represents a point starting at the left of the +// Least Significant Bit (LSB). The lowest value might not be 0 depending on +// the number of bits allocated for priorities, and implementation choices. +#define CPU_SCS_AIRCR_PRIGROUP_W 3 +#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 +#define CPU_SCS_AIRCR_PRIGROUP_S 8 + +// Field: [2] SYSRESETREQ +// +// Requests a warm reset. Setting this bit does not prevent Halting Debug from +// running. +#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 +#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 + +// Field: [1] VECTCLRACTIVE +// +// Clears all active state information for active NMI, fault, and interrupts. +// It is the responsibility of the application to reinitialize the stack. This +// bit is for returning to a known state during debug. The bit self-clears. +// IPSR is not cleared by this operation. So, if used by an application, it +// must only be used at the base level of activation, or within a system +// handler whose active bit can be set. +#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 + +// Field: [0] VECTRESET +// +// System Reset bit. Resets the system, with the exception of debug components. +// This bit is reserved for debug use and can be written to 1 only when the +// core is halted. The bit self-clears. Writing this bit to 1 while core is not +// halted may result in unpredictable behavior. +#define CPU_SCS_AIRCR_VECTRESET 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_BITN 0 +#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SCR +// +//***************************************************************************** +// Field: [4] SEVONPEND +// +// Send Event on Pending bit: +// +// 0: Only enabled interrupts or events can wakeup the processor, disabled +// interrupts are excluded +// 1: Enabled events and all interrupts, including disabled interrupts, can +// wakeup the processor. +// +// When an event or interrupt enters pending state, the event signal wakes up +// the processor from WFE. If +// the processor is not waiting for an event, the event is registered and +// affects the next WFE. +// The processor also wakes up on execution of an SEV instruction. +#define CPU_SCS_SCR_SEVONPEND 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_BITN 4 +#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_S 4 + +// Field: [2] SLEEPDEEP +// +// Controls whether the processor uses sleep or deep sleep as its low power +// mode +// ENUMs: +// DEEPSLEEP Deep sleep +// SLEEP Sleep +#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 +#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_S 2 +#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 + +// Field: [1] SLEEPONEXIT +// +// Sleep on exit when returning from Handler mode to Thread mode. Enables +// interrupt driven applications to avoid returning to empty main application. +// +// 0: Do not sleep when returning to thread mode +// 1: Sleep on ISR exit +#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 +#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_S 1 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CCR +// +//***************************************************************************** +// Field: [9] STKALIGN +// +// Stack alignment bit. +// +// 0: Only 4-byte alignment is guaranteed for the SP used prior to the +// exception on exception entry. +// 1: On exception entry, the SP used prior to the exception is adjusted to be +// 8-byte aligned and the context to restore it is saved. The SP is restored on +// the associated exception return. +#define CPU_SCS_CCR_STKALIGN 0x00000200 +#define CPU_SCS_CCR_STKALIGN_BITN 9 +#define CPU_SCS_CCR_STKALIGN_M 0x00000200 +#define CPU_SCS_CCR_STKALIGN_S 9 + +// Field: [8] BFHFNMIGN +// +// Enables handlers with priority -1 or -2 to ignore data BusFaults caused by +// load and store instructions. This applies to the HardFault, NMI, and +// FAULTMASK escalated handlers: +// +// 0: Data BusFaults caused by load and store instructions cause a lock-up +// 1: Data BusFaults caused by load and store instructions are ignored. +// +// Set this bit to 1 only when the handler and its data are in absolutely safe +// memory. The normal use +// of this bit is to probe system devices and bridges to detect problems. +#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 +#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_S 8 + +// Field: [4] DIV_0_TRP +// +// Enables faulting or halting when the processor executes an SDIV or UDIV +// instruction with a divisor of 0: +// +// 0: Do not trap divide by 0. In this mode, a divide by zero returns a +// quotient of 0. +// 1: Trap divide by 0. The relevant Usage Fault Status Register bit is +// CFSR.DIVBYZERO. +#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 +#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_S 4 + +// Field: [3] UNALIGN_TRP +// +// Enables unaligned access traps: +// +// 0: Do not trap unaligned halfword and word accesses +// 1: Trap unaligned halfword and word accesses. The relevant Usage Fault +// Status Register bit is CFSR.UNALIGNED. +// +// If this bit is set to 1, an unaligned access generates a UsageFault. +// Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of +// the value in UNALIGN_TRP. +#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 +#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_S 3 + +// Field: [1] USERSETMPEND +// +// Enables unprivileged software access to STIR: +// +// 0: User code is not allowed to write to the Software Trigger Interrupt +// register (STIR). +// 1: User code can write the Software Trigger Interrupt register (STIR) to +// trigger (pend) a Main exception, which is associated with the Main stack +// pointer. +#define CPU_SCS_CCR_USERSETMPEND 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_BITN 1 +#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_S 1 + +// Field: [0] NONBASETHREDENA +// +// Indicates how the processor enters Thread mode: +// +// 0: Processor can enter Thread mode only when no exception is active. +// 1: Processor can enter Thread mode from any level using the appropriate +// return value (EXC_RETURN). +// +// Exception returns occur when one of the following instructions loads a value +// of 0xFXXXXXXX into the PC while in Handler mode: +// - POP/LDM which includes loading the PC. +// - LDR with PC as a destination. +// - BX with any register. +// The value written to the PC is intercepted and is referred to as the +// EXC_RETURN value. +#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 +#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR1 +// +//***************************************************************************** +// Field: [23:16] PRI_6 +// +// Priority of system handler 6. UsageFault +#define CPU_SCS_SHPR1_PRI_6_W 8 +#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_SHPR1_PRI_6_S 16 + +// Field: [15:8] PRI_5 +// +// Priority of system handler 5: BusFault +#define CPU_SCS_SHPR1_PRI_5_W 8 +#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_SHPR1_PRI_5_S 8 + +// Field: [7:0] PRI_4 +// +// Priority of system handler 4: MemManage +#define CPU_SCS_SHPR1_PRI_4_W 8 +#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF +#define CPU_SCS_SHPR1_PRI_4_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR2 +// +//***************************************************************************** +// Field: [31:24] PRI_11 +// +// Priority of system handler 11. SVCall +#define CPU_SCS_SHPR2_PRI_11_W 8 +#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_SHPR2_PRI_11_S 24 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR3 +// +//***************************************************************************** +// Field: [31:24] PRI_15 +// +// Priority of system handler 15. SysTick exception +#define CPU_SCS_SHPR3_PRI_15_W 8 +#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_SHPR3_PRI_15_S 24 + +// Field: [23:16] PRI_14 +// +// Priority of system handler 14. Pend SV +#define CPU_SCS_SHPR3_PRI_14_W 8 +#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_SHPR3_PRI_14_S 16 + +// Field: [7:0] PRI_12 +// +// Priority of system handler 12. Debug Monitor +#define CPU_SCS_SHPR3_PRI_12_W 8 +#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF +#define CPU_SCS_SHPR3_PRI_12_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHCSR +// +//***************************************************************************** +// Field: [18] USGFAULTENA +// +// Usage fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 +#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_S 18 +#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 + +// Field: [17] BUSFAULTENA +// +// Bus fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 + +// Field: [16] MEMFAULTENA +// +// MemManage fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 + +// Field: [15] SVCALLPENDED +// +// SVCall pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 + +// Field: [14] BUSFAULTPENDED +// +// BusFault pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [13] MEMFAULTPENDED +// +// MemManage exception pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [12] USGFAULTPENDED +// +// Usage fault pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [11] SYSTICKACT +// +// SysTick active flag. +// +// 0x0: Not active +// 0x1: Active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 +#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_S 11 +#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 + +// Field: [10] PENDSVACT +// +// PendSV active +// +// 0x0: Not active +// 0x1: Active +#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 +#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_S 10 + +// Field: [8] MONITORACT +// +// Debug monitor active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_MONITORACT 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_BITN 8 +#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_S 8 +#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 + +// Field: [7] SVCALLACT +// +// SVCall active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 +#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_S 7 +#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 + +// Field: [3] USGFAULTACT +// +// UsageFault exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 +#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_S 3 +#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 + +// Field: [1] BUSFAULTACT +// +// BusFault exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 + +// Field: [0] MEMFAULTACT +// +// MemManage exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CFSR +// +//***************************************************************************** +// Field: [25] DIVBYZERO +// +// When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is +// enabled and an SDIV or UDIV instruction is used with a divisor of 0, this +// fault occurs The instruction is executed and the return PC points to it. If +// CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. +#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 +#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_S 25 + +// Field: [24] UNALIGNED +// +// When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an +// unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD +// instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. +#define CPU_SCS_CFSR_UNALIGNED 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_BITN 24 +#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_S 24 + +// Field: [19] NOCP +// +// Attempt to use a coprocessor instruction. The processor does not support +// coprocessor instructions. +#define CPU_SCS_CFSR_NOCP 0x00080000 +#define CPU_SCS_CFSR_NOCP_BITN 19 +#define CPU_SCS_CFSR_NOCP_M 0x00080000 +#define CPU_SCS_CFSR_NOCP_S 19 + +// Field: [18] INVPC +// +// Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid +// context, invalid value. The return PC points to the instruction that tried +// to set the PC. +#define CPU_SCS_CFSR_INVPC 0x00040000 +#define CPU_SCS_CFSR_INVPC_BITN 18 +#define CPU_SCS_CFSR_INVPC_M 0x00040000 +#define CPU_SCS_CFSR_INVPC_S 18 + +// Field: [17] INVSTATE +// +// Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX +// type instruction has changed state). This includes state change after entry +// to or return from exception, as well as from inter-working instructions. +// Return PC points to faulting instruction, with the invalid state. +#define CPU_SCS_CFSR_INVSTATE 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_BITN 17 +#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_S 17 + +// Field: [16] UNDEFINSTR +// +// This bit is set when the processor attempts to execute an undefined +// instruction. This is an instruction that the processor cannot decode. The +// return PC points to the undefined instruction. +#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 +#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_S 16 + +// Field: [15] BFARVALID +// +// This bit is set if the Bus Fault Address Register (BFAR) contains a valid +// address. This is true after a bus fault where the address is known. Other +// faults can clear this bit, such as a Mem Manage fault occurring later. If a +// Bus fault occurs that is escalated to a Hard Fault because of priority, the +// Hard Fault handler must clear this bit. This prevents problems if returning +// to a stacked active Bus fault handler whose BFAR value has been overwritten. +#define CPU_SCS_CFSR_BFARVALID 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_BITN 15 +#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_S 15 + +// Field: [12] STKERR +// +// Stacking from exception has caused one or more bus faults. The SP is still +// adjusted and the values in the context area on the stack might be incorrect. +// BFAR is not written. +#define CPU_SCS_CFSR_STKERR 0x00001000 +#define CPU_SCS_CFSR_STKERR_BITN 12 +#define CPU_SCS_CFSR_STKERR_M 0x00001000 +#define CPU_SCS_CFSR_STKERR_S 12 + +// Field: [11] UNSTKERR +// +// Unstack from exception return has caused one or more bus faults. This is +// chained to the handler, so that the original return stack is still present. +// SP is not adjusted from failing return and new save is not performed. BFAR +// is not written. +#define CPU_SCS_CFSR_UNSTKERR 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_BITN 11 +#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_S 11 + +// Field: [10] IMPRECISERR +// +// Imprecise data bus error. It is a BusFault, but the Return PC is not related +// to the causing instruction. This is not a synchronous fault. So, if detected +// when the priority of the current activation is higher than the Bus Fault, it +// only pends. Bus fault activates when returning to a lower priority +// activation. If a precise fault occurs before returning to a lower priority +// exception, the handler detects both IMPRECISERR set and one of the precise +// fault status bits set at the same time. BFAR is not written. +#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 +#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_S 10 + +// Field: [9] PRECISERR +// +// Precise data bus error return. +#define CPU_SCS_CFSR_PRECISERR 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_BITN 9 +#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_S 9 + +// Field: [8] IBUSERR +// +// Instruction bus error flag. This flag is set by a prefetch error. The fault +// stops on the instruction, so if the error occurs under a branch shadow, no +// fault occurs. BFAR is not written. +#define CPU_SCS_CFSR_IBUSERR 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_BITN 8 +#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_S 8 + +// Field: [7] MMARVALID +// +// Memory Manage Address Register (MMFAR) address valid flag. A later-arriving +// fault, such as a bus fault, can clear a memory manage fault.. If a MemManage +// fault occurs that is escalated to a Hard Fault because of priority, the Hard +// Fault handler must clear this bit. This prevents problems on return to a +// stacked active MemManage handler whose MMFAR value has been overwritten. +#define CPU_SCS_CFSR_MMARVALID 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_BITN 7 +#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_S 7 + +// Field: [4] MSTKERR +// +// Stacking from exception has caused one or more access violations. The SP is +// still adjusted and the values in the context area on the stack might be +// incorrect. MMFAR is not written. +#define CPU_SCS_CFSR_MSTKERR 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_BITN 4 +#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_S 4 + +// Field: [3] MUNSTKERR +// +// Unstack from exception return has caused one or more access violations. This +// is chained to the handler, so that the original return stack is still +// present. SP is not adjusted from failing return and new save is not +// performed. MMFAR is not written. +#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 +#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_S 3 + +// Field: [1] DACCVIOL +// +// Data access violation flag. Attempting to load or store at a location that +// does not permit the operation sets this flag. The return PC points to the +// faulting instruction. This error loads MMFAR with the address of the +// attempted access. +#define CPU_SCS_CFSR_DACCVIOL 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_BITN 1 +#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_S 1 + +// Field: [0] IACCVIOL +// +// Instruction access violation flag. Attempting to fetch an instruction from a +// location that does not permit execution sets this flag. This occurs on any +// access to an XN region, even when the MPU is disabled or not present. The +// return PC points to the faulting instruction. MMFAR is not written. +#define CPU_SCS_CFSR_IACCVIOL 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_BITN 0 +#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_HFSR +// +//***************************************************************************** +// Field: [31] DEBUGEVT +// +// This bit is set if there is a fault related to debug. This is only possible +// when halting debug is not enabled. For monitor enabled debug, it only +// happens for BKPT when the current priority is higher than the monitor. When +// both halting and monitor debug are disabled, it only happens for debug +// events that are not ignored (minimally, BKPT). The Debug Fault Status +// Register is updated. +#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 +#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_S 31 + +// Field: [30] FORCED +// +// Hard Fault activated because a Configurable Fault was received and cannot +// activate because of priority or because the Configurable Fault is disabled. +// The Hard Fault handler then has to read the other fault status registers to +// determine cause. +#define CPU_SCS_HFSR_FORCED 0x40000000 +#define CPU_SCS_HFSR_FORCED_BITN 30 +#define CPU_SCS_HFSR_FORCED_M 0x40000000 +#define CPU_SCS_HFSR_FORCED_S 30 + +// Field: [1] VECTTBL +// +// This bit is set if there is a fault because of vector table read on +// exception processing (Bus Fault). This case is always a Hard Fault. The +// return PC points to the pre-empted instruction. +#define CPU_SCS_HFSR_VECTTBL 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_BITN 1 +#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_S 1 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DFSR +// +//***************************************************************************** +// Field: [4] EXTERNAL +// +// External debug request flag. The processor stops on next instruction +// boundary. +// +// 0x0: External debug request signal not asserted +// 0x1: External debug request signal asserted +#define CPU_SCS_DFSR_EXTERNAL 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_BITN 4 +#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_S 4 + +// Field: [3] VCATCH +// +// Vector catch flag. When this flag is set, a flag in one of the local fault +// status registers is also set to indicate the type of fault. +// +// 0x0: No vector catch occurred +// 0x1: Vector catch occurred +#define CPU_SCS_DFSR_VCATCH 0x00000008 +#define CPU_SCS_DFSR_VCATCH_BITN 3 +#define CPU_SCS_DFSR_VCATCH_M 0x00000008 +#define CPU_SCS_DFSR_VCATCH_S 3 + +// Field: [2] DWTTRAP +// +// Data Watchpoint and Trace (DWT) flag. The processor stops at the current +// instruction or at the next instruction. +// +// 0x0: No DWT match +// 0x1: DWT match +#define CPU_SCS_DFSR_DWTTRAP 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_BITN 2 +#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_S 2 + +// Field: [1] BKPT +// +// BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, +// and also by normal code. Return PC points to breakpoint containing +// instruction. +// +// 0x0: No BKPT instruction execution +// 0x1: BKPT instruction execution +#define CPU_SCS_DFSR_BKPT 0x00000002 +#define CPU_SCS_DFSR_BKPT_BITN 1 +#define CPU_SCS_DFSR_BKPT_M 0x00000002 +#define CPU_SCS_DFSR_BKPT_S 1 + +// Field: [0] HALTED +// +// Halt request flag. The processor is halted on the next instruction. +// +// 0x0: No halt request +// 0x1: Halt requested by NVIC, including step +#define CPU_SCS_DFSR_HALTED 0x00000001 +#define CPU_SCS_DFSR_HALTED_BITN 0 +#define CPU_SCS_DFSR_HALTED_M 0x00000001 +#define CPU_SCS_DFSR_HALTED_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MMFAR +// +//***************************************************************************** +// Field: [31:0] ADDRESS +// +// Mem Manage fault address field. +// This field is the data address of a faulted load or store attempt. When an +// unaligned access faults, the address is the actual address that faulted. +// Because an access can be split into multiple parts, each aligned, this +// address can be any offset in the range of the requested size. Flags +// CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination +// with CFSR.MMARVALIDindicate the cause of the fault. +#define CPU_SCS_MMFAR_ADDRESS_W 32 +#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_MMFAR_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_BFAR +// +//***************************************************************************** +// Field: [31:0] ADDRESS +// +// Bus fault address field. This field is the data address of a faulted load or +// store attempt. When an unaligned access faults, the address is the address +// requested by the instruction, even if that is not the address that faulted. +// Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and +// CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the +// fault. +#define CPU_SCS_BFAR_ADDRESS_W 32 +#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_BFAR_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_AFSR +// +//***************************************************************************** +// Field: [31:0] IMPDEF +// +// Implementation defined. The bits map directly onto the signal assignment to +// the auxiliary fault inputs. Tied to 0 +#define CPU_SCS_AFSR_IMPDEF_W 32 +#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF +#define CPU_SCS_AFSR_IMPDEF_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_PFR0 +// +//***************************************************************************** +// Field: [7:4] STATE1 +// +// State1 (T-bit == 1) +// +// 0x0: N/A +// 0x1: N/A +// 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit +// Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit +// instructions can be added using the appropriate instruction attribute, but +// other 32-bit basic instructions cannot.) +// 0x3: Thumb-2 encoding with all Thumb-2 basic instructions +#define CPU_SCS_ID_PFR0_STATE1_W 4 +#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 +#define CPU_SCS_ID_PFR0_STATE1_S 4 + +// Field: [3:0] STATE0 +// +// State0 (T-bit == 0) +// +// 0x0: No ARM encoding +// 0x1: N/A +#define CPU_SCS_ID_PFR0_STATE0_W 4 +#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F +#define CPU_SCS_ID_PFR0_STATE0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_PFR1 +// +//***************************************************************************** +// Field: [11:8] MICROCONTROLLER_PROGRAMMERS_MODEL +// +// Microcontroller programmer's model +// +// 0x0: Not supported +// 0x2: Two-stack support +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_DFR0 +// +//***************************************************************************** +// Field: [23:20] MICROCONTROLLER_DEBUG_MODEL +// +// Microcontroller Debug Model - memory mapped +// +// 0x0: Not supported +// 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_AFR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR2 +// +//***************************************************************************** +// Field: [24] WAIT_FOR_INTERRUPT_STALLING +// +// wait for interrupt stalling +// +// 0x0: Not supported +// 0x1: Wait for interrupt supported +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR4 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_CPACR +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_DHCSR +// +//***************************************************************************** +// Field: [25] S_RESET_ST +// +// Indicates that the core has been reset, or is now being reset, since the +// last time this bit was read. This a sticky bit that clears on read. So, +// reading twice and getting 1 then 0 means it was reset in the past. Reading +// twice and getting 1 both times means that it is being reset now (held in +// reset still). +// When writing to this register, 0 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 +#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_S 25 + +// Field: [24] S_RETIRE_ST +// +// Indicates that an instruction has completed since last read. This is a +// sticky bit that clears on read. This determines if the core is stalled on a +// load/store or fetch. +// When writing to this register, 0 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 +#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 + +// Field: [19] S_LOCKUP +// +// Reads as one if the core is running (not halted) and a lockup condition is +// present. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 +#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_S 19 + +// Field: [18] S_SLEEP +// +// Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must +// use C_HALT to gain control or wait for interrupt to wake-up. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 +#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_S 18 + +// Field: [17] S_HALT +// +// The core is in debug state when this bit is set. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_HALT 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_BITN 17 +#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_S 17 + +// Field: [16] S_REGRDY +// +// Register Read/Write on the Debug Core Register Selector register is +// available. Last transfer is complete. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 +#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_S 16 + +// Field: [5] C_SNAPSTALL +// +// If the core is stalled on a load/store operation the stall ceases and the +// instruction is forced to complete. This enables Halting debug to gain +// control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. +// The core reads S_RETIRE_ST as 0. This indicates that no instruction has +// advanced. This prevents misuse. The bus state is Unpredictable when this is +// used. S_RETIRE_ST can detect core stalls on load/store operations. +#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 +#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 + +// Field: [3] C_MASKINTS +// +// Mask interrupts when stepping or running in halted debug. This masking does +// not affect NMI, fault exceptions and SVC caused by execution of the +// instructions. This bit must only be modified when the processor is halted +// (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released +// (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must +// be separate). Modifying C_MASKINTS while the system is running with halting +// debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable +// behavior. +#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 +#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_S 3 + +// Field: [2] C_STEP +// +// Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. +// Must only be modified when the processor is halted (S_HALT == 1). +// Modifying C_STEP while the system is running with halting debug support +// enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. +#define CPU_SCS_DHCSR_C_STEP 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_BITN 2 +#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_S 2 + +// Field: [1] C_HALT +// +// Halts the core. This bit is set automatically when the core Halts. For +// example Breakpoint. This bit clears on core reset. +#define CPU_SCS_DHCSR_C_HALT 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_BITN 1 +#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_S 1 + +// Field: [0] C_DEBUGEN +// +// Enables debug. This can only be written by AHB-AP and not by the core. It is +// ignored when written by the core, which cannot set or clear it. The core +// must write a 1 to it when writing C_HALT to halt itself. +// The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when +// C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will +// be unknown to software when C_DEBUGEN = 0. +#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 +#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DCRSR +// +//***************************************************************************** +// Field: [16] REGWNR +// +// 1: Write +// 0: Read +#define CPU_SCS_DCRSR_REGWNR 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_BITN 16 +#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_S 16 + +// Field: [4:0] REGSEL +// +// Register select +// +// 0x00: R0 +// 0x01: R1 +// 0x02: R2 +// 0x03: R3 +// 0x04: R4 +// 0x05: R5 +// 0x06: R6 +// 0x07: R7 +// 0x08: R8 +// 0x09: R9 +// 0x0A: R10 +// 0x0B: R11 +// 0x0C: R12 +// 0x0D: Current SP +// 0x0E: LR +// 0x0F: DebugReturnAddress +// 0x10: XPSR/flags, execution state information, and exception number +// 0x11: MSP (Main SP) +// 0x12: PSP (Process SP) +// 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK +#define CPU_SCS_DCRSR_REGSEL_W 5 +#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F +#define CPU_SCS_DCRSR_REGSEL_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DCRDR +// +//***************************************************************************** +// Field: [31:0] DCRDR +// +// This register holds data for reading and writing registers to and from the +// processor. This is the data value written to the register selected by DCRSR. +// When the processor receives a request from DCRSR, this register is read or +// written by the processor using a normal load-store unit operation. If core +// register transfers are not being performed, software-based debug monitors +// can use this register for communication in non-halting debug. This enables +// flags and bits to acknowledge state and indicate if commands have been +// accepted to, replied to, or accepted and replied to. +#define CPU_SCS_DCRDR_DCRDR_W 32 +#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF +#define CPU_SCS_DCRDR_DCRDR_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DEMCR +// +//***************************************************************************** +// Field: [24] TRCENA +// +// This bit must be set to 1 to enable use of the trace and debug blocks: DWT, +// ITM, ETM and TPIU. This enables control of power usage unless tracing is +// required. The application can enable this, for ITM use, or use by a +// debugger. +#define CPU_SCS_DEMCR_TRCENA 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_BITN 24 +#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_S 24 + +// Field: [19] MON_REQ +// +// This enables the monitor to identify how it wakes up. This bit clears on a +// Core Reset. +// +// 0x0: Woken up by debug exception. +// 0x1: Woken up by MON_PEND +#define CPU_SCS_DEMCR_MON_REQ 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_BITN 19 +#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_S 19 + +// Field: [18] MON_STEP +// +// When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. +// This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped +// according to the priority of the monitor and settings of PRIMASK, FAULTMASK, +// or BASEPRI. +#define CPU_SCS_DEMCR_MON_STEP 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_BITN 18 +#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_S 18 + +// Field: [17] MON_PEND +// +// Pend the monitor to activate when priority permits. This can wake up the +// monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for +// Monitor debug. This register does not reset on a system reset. It is only +// reset by a power-on reset. Software in the reset handler or later, or by the +// DAP must enable the debug monitor. +#define CPU_SCS_DEMCR_MON_PEND 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_BITN 17 +#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_S 17 + +// Field: [16] MON_EN +// +// Enable the debug monitor. +// When enabled, the System handler priority register controls its priority +// level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN +// overrides this bit. Vector catching is semi-synchronous. When a matching +// event is seen, a Halt is requested. Because the processor can only halt on +// an instruction boundary, it must wait until the next instruction boundary. +// As a result, it stops on the first instruction of the exception handler. +// However, two special cases exist when a vector catch has triggered: 1. If a +// fault is taken during vectoring, vector read or stack push error, the halt +// occurs on the corresponding fault handler, for the vector error or stack +// push. 2. If a late arriving interrupt comes in during vectoring, it is not +// taken. That is, an implementation that supports the late arrival +// optimization must suppress it in this case. +#define CPU_SCS_DEMCR_MON_EN 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_BITN 16 +#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_S 16 + +// Field: [10] VC_HARDERR +// +// Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 +#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_S 10 + +// Field: [9] VC_INTERR +// +// Debug trap on a fault occurring during an exception entry or return +// sequence. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 +#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_S 9 + +// Field: [8] VC_BUSERR +// +// Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 +#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_S 8 + +// Field: [7] VC_STATERR +// +// Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is +// cleared. +#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 +#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_S 7 + +// Field: [6] VC_CHKERR +// +// Debug trap on Usage Fault enabled checking errors. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 +#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_S 6 + +// Field: [5] VC_NOCPERR +// +// Debug trap on a UsageFault access to a Coprocessor. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 +#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 + +// Field: [4] VC_MMERR +// +// Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is +// cleared. +#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 +#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_S 4 + +// Field: [0] VC_CORERESET +// +// Reset Vector Catch. Halt running system if Core reset occurs. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 +#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STIR +// +//***************************************************************************** +// Field: [8:0] INTID +// +// Interrupt ID field. Writing a value to this bit-field is the same as +// manually pending an interrupt by setting the corresponding interrupt bit in +// an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. +#define CPU_SCS_STIR_INTID_W 9 +#define CPU_SCS_STIR_INTID_M 0x000001FF +#define CPU_SCS_STIR_INTID_S 0 + + +#endif // __CPU_SCS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tiprop.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tiprop.h new file mode 100644 index 0000000..3b011f7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tiprop.h @@ -0,0 +1,83 @@ +/****************************************************************************** +* Filename: hw_cpu_tiprop_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_TIPROP_H__ +#define __HW_CPU_TIPROP_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_TIPROP component +// +//***************************************************************************** +// Internal +#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8 + +// Internal +#define CPU_TIPROP_O_DYN_CG 0x00000FFC + +//***************************************************************************** +// +// Register: CPU_TIPROP_O_TRACECLKMUX +// +//***************************************************************************** +// Field: [0] TRACECLK_N_SWV +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// TRACECLK Internal. Only to be used through TI provided API. +// SWV Internal. Only to be used through TI provided API. +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000 + +//***************************************************************************** +// +// Register: CPU_TIPROP_O_DYN_CG +// +//***************************************************************************** +// Field: [1:0] DYN_CG +// +// Internal. Only to be used through TI provided API. +#define CPU_TIPROP_DYN_CG_DYN_CG_W 2 +#define CPU_TIPROP_DYN_CG_DYN_CG_M 0x00000003 +#define CPU_TIPROP_DYN_CG_DYN_CG_S 0 + + +#endif // __CPU_TIPROP__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tpiu.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tpiu.h new file mode 100644 index 0000000..b91c2e8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tpiu.h @@ -0,0 +1,347 @@ +/****************************************************************************** +* Filename: hw_cpu_tpiu_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_TPIU_H__ +#define __HW_CPU_TPIU_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_TPIU component +// +//***************************************************************************** +// Supported Sync Port Sizes +#define CPU_TPIU_O_SSPSR 0x00000000 + +// Current Sync Port Size +#define CPU_TPIU_O_CSPSR 0x00000004 + +// Async Clock Prescaler +#define CPU_TPIU_O_ACPR 0x00000010 + +// Selected Pin Protocol +#define CPU_TPIU_O_SPPR 0x000000F0 + +// Formatter and Flush Status +#define CPU_TPIU_O_FFSR 0x00000300 + +// Formatter and Flush Control +#define CPU_TPIU_O_FFCR 0x00000304 + +// Formatter Synchronization Counter +#define CPU_TPIU_O_FSCR 0x00000308 + +// Claim Tag Mask +#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 + +// Claim Tag Set +#define CPU_TPIU_O_CLAIMSET 0x00000FA0 + +// Current Claim Tag +#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 + +// Claim Tag Clear +#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 + +// Device ID +#define CPU_TPIU_O_DEVID 0x00000FC8 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_SSPSR +// +//***************************************************************************** +// Field: [3] FOUR +// +// 4-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_FOUR 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_BITN 3 +#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_S 3 + +// Field: [2] THREE +// +// 3-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_THREE 0x00000004 +#define CPU_TPIU_SSPSR_THREE_BITN 2 +#define CPU_TPIU_SSPSR_THREE_M 0x00000004 +#define CPU_TPIU_SSPSR_THREE_S 2 + +// Field: [1] TWO +// +// 2-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_TWO 0x00000002 +#define CPU_TPIU_SSPSR_TWO_BITN 1 +#define CPU_TPIU_SSPSR_TWO_M 0x00000002 +#define CPU_TPIU_SSPSR_TWO_S 1 + +// Field: [0] ONE +// +// 1-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_ONE 0x00000001 +#define CPU_TPIU_SSPSR_ONE_BITN 0 +#define CPU_TPIU_SSPSR_ONE_M 0x00000001 +#define CPU_TPIU_SSPSR_ONE_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CSPSR +// +//***************************************************************************** +// Field: [3] FOUR +// +// 4-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_FOUR 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_BITN 3 +#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_S 3 + +// Field: [2] THREE +// +// 3-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_THREE 0x00000004 +#define CPU_TPIU_CSPSR_THREE_BITN 2 +#define CPU_TPIU_CSPSR_THREE_M 0x00000004 +#define CPU_TPIU_CSPSR_THREE_S 2 + +// Field: [1] TWO +// +// 2-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_TWO 0x00000002 +#define CPU_TPIU_CSPSR_TWO_BITN 1 +#define CPU_TPIU_CSPSR_TWO_M 0x00000002 +#define CPU_TPIU_CSPSR_TWO_S 1 + +// Field: [0] ONE +// +// 1-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_ONE 0x00000001 +#define CPU_TPIU_CSPSR_ONE_BITN 0 +#define CPU_TPIU_CSPSR_ONE_M 0x00000001 +#define CPU_TPIU_CSPSR_ONE_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_ACPR +// +//***************************************************************************** +// Field: [12:0] PRESCALER +// +// Divisor for input trace clock is (PRESCALER + 1). +#define CPU_TPIU_ACPR_PRESCALER_W 13 +#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF +#define CPU_TPIU_ACPR_PRESCALER_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_SPPR +// +//***************************************************************************** +// Field: [1:0] PROTOCOL +// +// Trace output protocol +// ENUMs: +// SWO_NRZ SerialWire Output (NRZ) +// SWO_MANCHESTER SerialWire Output (Manchester). This is the reset +// value. +// TRACEPORT TracePort mode +#define CPU_TPIU_SPPR_PROTOCOL_W 2 +#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 +#define CPU_TPIU_SPPR_PROTOCOL_S 0 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 +#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FFSR +// +//***************************************************************************** +// Field: [3] FTNONSTOP +// +// 0: Formatter can be stopped +// 1: Formatter cannot be stopped +#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 +#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_S 3 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FFCR +// +//***************************************************************************** +// Field: [8] TRIGIN +// +// Indicates that triggers are inserted when a trigger pin is asserted. +#define CPU_TPIU_FFCR_TRIGIN 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_BITN 8 +#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_S 8 + +// Field: [1] ENFCONT +// +// Enable continuous formatting: +// +// 0: Continuous formatting disabled +// 1: Continuous formatting enabled +#define CPU_TPIU_FFCR_ENFCONT 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_BITN 1 +#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_S 1 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FSCR +// +//***************************************************************************** +// Field: [31:0] FSCR +// +// The global synchronization trigger is generated by the Program Counter (PC) +// Sampler block. This means that there is no synchronization counter in the +// TPIU. +#define CPU_TPIU_FSCR_FSCR_W 32 +#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF +#define CPU_TPIU_FSCR_FSCR_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMMASK +// +//***************************************************************************** +// Field: [31:0] CLAIMMASK +// +// This register forms one half of the Claim Tag value. When reading this +// register returns the number of bits that can be set (each bit is considered +// separately): +// +// 0: This claim tag bit is not implemented +// 1: This claim tag bit is not implemented +// +// The behavior when writing to this register is described in CLAIMSET. +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMSET +// +//***************************************************************************** +// Field: [31:0] CLAIMSET +// +// This register forms one half of the Claim Tag value. Writing to this +// location allows individual bits to be set (each bit is considered +// separately): +// +// 0: No effect +// 1: Set this bit in the claim tag +// +// The behavior when reading from this location is described in CLAIMMASK. +#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 +#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMTAG +// +//***************************************************************************** +// Field: [31:0] CLAIMTAG +// +// This register forms one half of the Claim Tag value. Reading this register +// returns the current Claim Tag value. +// Reading CLAIMMASK determines how many bits from this register must be used. +// +// The behavior when writing to this register is described in CLAIMCLR. +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMCLR +// +//***************************************************************************** +// Field: [31:0] CLAIMCLR +// +// This register forms one half of the Claim Tag value. Writing to this +// location enables individual bits to be cleared (each bit is considered +// separately): +// +// 0: No effect +// 1: Clear this bit in the claim tag. +// +// The behavior when reading from this location is described in CLAIMTAG. +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_DEVID +// +//***************************************************************************** +// Field: [31:0] DEVID +// +// This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no +// ETM present. +#define CPU_TPIU_DEVID_DEVID_W 32 +#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF +#define CPU_TPIU_DEVID_DEVID_S 0 + + +#endif // __CPU_TPIU__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_crypto.h new file mode 100644 index 0000000..80bc5fc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_crypto.h @@ -0,0 +1,1914 @@ +/****************************************************************************** +* Filename: hw_crypto_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CRYPTO_H__ +#define __HW_CRYPTO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CRYPTO component +// +//***************************************************************************** +// DMA Channel 0 Control +#define CRYPTO_O_DMACH0CTL 0x00000000 + +// DMA Channel 0 External Address +#define CRYPTO_O_DMACH0EXTADDR 0x00000004 + +// DMA Channel 0 Length +#define CRYPTO_O_DMACH0LEN 0x0000000C + +// DMA Controller Status +#define CRYPTO_O_DMASTAT 0x00000018 + +// DMA Controller Software Reset +#define CRYPTO_O_DMASWRESET 0x0000001C + +// DMA Channel 1 Control +#define CRYPTO_O_DMACH1CTL 0x00000020 + +// DMA Channel 1 External Address +#define CRYPTO_O_DMACH1EXTADDR 0x00000024 + +// DMA Channel 1 Length +#define CRYPTO_O_DMACH1LEN 0x0000002C + +// DMA Controller Master Configuration +#define CRYPTO_O_DMABUSCFG 0x00000078 + +// DMA Controller Port Error +#define CRYPTO_O_DMAPORTERR 0x0000007C + +// DMA Controller Version +#define CRYPTO_O_DMAHWVER 0x000000FC + +// Key Write Area +#define CRYPTO_O_KEYWRITEAREA 0x00000400 + +// Key Written Area Status +#define CRYPTO_O_KEYWRITTENAREA 0x00000404 + +// Key Size +#define CRYPTO_O_KEYSIZE 0x00000408 + +// Key Read Area +#define CRYPTO_O_KEYREADAREA 0x0000040C + +// Clear AES_KEY2/GHASH Key +#define CRYPTO_O_AESKEY20 0x00000500 + +// Clear AES_KEY2/GHASH Key +#define CRYPTO_O_AESKEY21 0x00000504 + +// Clear AES_KEY2/GHASH Key +#define CRYPTO_O_AESKEY22 0x00000508 + +// Clear AES_KEY2/GHASH Key +#define CRYPTO_O_AESKEY23 0x0000050C + +// Clear AES_KEY3 +#define CRYPTO_O_AESKEY30 0x00000510 + +// Clear AES_KEY3 +#define CRYPTO_O_AESKEY31 0x00000514 + +// Clear AES_KEY3 +#define CRYPTO_O_AESKEY32 0x00000518 + +// Clear AES_KEY3 +#define CRYPTO_O_AESKEY33 0x0000051C + +// AES Initialization Vector +#define CRYPTO_O_AESIV0 0x00000540 + +// AES Initialization Vector +#define CRYPTO_O_AESIV1 0x00000544 + +// AES Initialization Vector +#define CRYPTO_O_AESIV2 0x00000548 + +// AES Initialization Vector +#define CRYPTO_O_AESIV3 0x0000054C + +// AES Input/Output Buffer Control +#define CRYPTO_O_AESCTL 0x00000550 + +// Crypto Data Length LSW +#define CRYPTO_O_AESDATALEN0 0x00000554 + +// Crypto Data Length MSW +#define CRYPTO_O_AESDATALEN1 0x00000558 + +// AES Authentication Length +#define CRYPTO_O_AESAUTHLEN 0x0000055C + +// Data Input/Output +#define CRYPTO_O_AESDATAOUT0 0x00000560 + +// AES Data Input/Output 0 +#define CRYPTO_O_AESDATAIN0 0x00000560 + +// AES Data Input/Output 3 +#define CRYPTO_O_AESDATAOUT1 0x00000564 + +// AES Data Input/Output 1 +#define CRYPTO_O_AESDATAIN1 0x00000564 + +// AES Data Input/Output 2 +#define CRYPTO_O_AESDATAOUT2 0x00000568 + +// AES Data Input/Output 2 +#define CRYPTO_O_AESDATAIN2 0x00000568 + +// AES Data Input/Output 3 +#define CRYPTO_O_AESDATAOUT3 0x0000056C + +// Data Input/Output +#define CRYPTO_O_AESDATAIN3 0x0000056C + +// AES Tag Output +#define CRYPTO_O_AESTAGOUT0 0x00000570 + +// AES Tag Output +#define CRYPTO_O_AESTAGOUT1 0x00000574 + +// AES Tag Output +#define CRYPTO_O_AESTAGOUT2 0x00000578 + +// AES Tag Output +#define CRYPTO_O_AESTAGOUT3 0x0000057C + +// Master Algorithm Select +#define CRYPTO_O_ALGSEL 0x00000700 + +// Master Protection Control +#define CRYPTO_O_DMAPROTCTL 0x00000704 + +// Software Reset +#define CRYPTO_O_SWRESET 0x00000740 + +// Control Interrupt Configuration +#define CRYPTO_O_IRQTYPE 0x00000780 + +// Interrupt Enable +#define CRYPTO_O_IRQEN 0x00000784 + +// Interrupt Clear +#define CRYPTO_O_IRQCLR 0x00000788 + +// Interrupt Set +#define CRYPTO_O_IRQSET 0x0000078C + +// Interrupt Status +#define CRYPTO_O_IRQSTAT 0x00000790 + +// CTRL Module Version +#define CRYPTO_O_HWVER 0x000007FC + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0CTL +// +//***************************************************************************** +// Field: [1] PRIO +// +// Channel priority: +// +// A channel with high priority will be served before a channel with low +// priority in cases with simultaneous access requests. If both channels have +// the same priority access of the channels to the external port is arbitrated +// using a Round Robin scheme. +// ENUMs: +// HIGH Priority high +// LOW Priority low +#define CRYPTO_DMACH0CTL_PRIO 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_BITN 1 +#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_S 1 +#define CRYPTO_DMACH0CTL_PRIO_HIGH 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_LOW 0x00000000 + +// Field: [0] EN +// +// DMA Channel 0 Control +// ENUMs: +// EN Channel enabled +// DIS Channel disabled +#define CRYPTO_DMACH0CTL_EN 0x00000001 +#define CRYPTO_DMACH0CTL_EN_BITN 0 +#define CRYPTO_DMACH0CTL_EN_M 0x00000001 +#define CRYPTO_DMACH0CTL_EN_S 0 +#define CRYPTO_DMACH0CTL_EN_EN 0x00000001 +#define CRYPTO_DMACH0CTL_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0EXTADDR +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Channel external address value. +// Holds the last updated external address after being sent to the master +// interface. +#define CRYPTO_DMACH0EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH0EXTADDR_ADDR_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0LEN +// +//***************************************************************************** +// Field: [15:0] LEN +// +// DMA transfer length in bytes. +// During configuration, this register contains the DMA transfer length in +// bytes. During operation, it contains the last updated value of the DMA +// transfer length after being sent to the master interface. +// Note: Writing a non-zero value to this register field starts the transfer if +// the channel is enabled by setting DMACH0CTL.EN. +#define CRYPTO_DMACH0LEN_LEN_W 16 +#define CRYPTO_DMACH0LEN_LEN_M 0x0000FFFF +#define CRYPTO_DMACH0LEN_LEN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMASTAT +// +//***************************************************************************** +// Field: [17] PORT_ERR +// +// Reflects possible transfer errors on the AHB port. +#define CRYPTO_DMASTAT_PORT_ERR 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_BITN 17 +#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_S 17 + +// Field: [1] CH1_ACTIVE +// +// This register field indicates if DMA channel 1 is active or not. +// 0: Not active +// 1: Active +#define CRYPTO_DMASTAT_CH1_ACTIVE 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACTIVE_BITN 1 +#define CRYPTO_DMASTAT_CH1_ACTIVE_M 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACTIVE_S 1 + +// Field: [0] CH0_ACTIVE +// +// This register field indicates if DMA channel 0 is active or not. +// 0: Not active +// 1: Active +#define CRYPTO_DMASTAT_CH0_ACTIVE 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACTIVE_BITN 0 +#define CRYPTO_DMASTAT_CH0_ACTIVE_M 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACTIVE_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMASWRESET +// +//***************************************************************************** +// Field: [0] RESET +// +// Software reset enable +// +// 0: Disable +// 1: Enable (self-cleared to zero). +// +// Note: Completion of the software reset must be checked in DMASTAT.CH0_ACTIVE +// and DMASTAT.CH1_ACTIVE. +#define CRYPTO_DMASWRESET_RESET 0x00000001 +#define CRYPTO_DMASWRESET_RESET_BITN 0 +#define CRYPTO_DMASWRESET_RESET_M 0x00000001 +#define CRYPTO_DMASWRESET_RESET_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1CTL +// +//***************************************************************************** +// Field: [1] PRIO +// +// Channel priority: +// +// A channel with high priority will be served before a channel with low +// priority in cases with simultaneous access requests. If both channels have +// the same priority access of the channels to the external port is arbitrated +// using a Round Robin scheme. +// ENUMs: +// HIGH Priority high +// LOW Priority low +#define CRYPTO_DMACH1CTL_PRIO 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_BITN 1 +#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_S 1 +#define CRYPTO_DMACH1CTL_PRIO_HIGH 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_LOW 0x00000000 + +// Field: [0] EN +// +// Channel enable: +// +// Note: Disabling an active channel will interrupt the DMA operation. The +// ongoing block transfer will be completed, but no new transfers will be +// requested. +// ENUMs: +// EN Channel enabled +// DIS Channel disabled +#define CRYPTO_DMACH1CTL_EN 0x00000001 +#define CRYPTO_DMACH1CTL_EN_BITN 0 +#define CRYPTO_DMACH1CTL_EN_M 0x00000001 +#define CRYPTO_DMACH1CTL_EN_S 0 +#define CRYPTO_DMACH1CTL_EN_EN 0x00000001 +#define CRYPTO_DMACH1CTL_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1EXTADDR +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Channel external address value. +// Holds the last updated external address after being sent to the master +// interface. +#define CRYPTO_DMACH1EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH1EXTADDR_ADDR_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1LEN +// +//***************************************************************************** +// Field: [15:0] LEN +// +// DMA transfer length in bytes. +// During configuration, this register contains the DMA transfer length in +// bytes. During operation, it contains the last updated value of the DMA +// transfer length after being sent to the master interface. +// Note: Writing a non-zero value to this register field starts the transfer if +// the channel is enabled by setting DMACH1CTL.EN. +#define CRYPTO_DMACH1LEN_LEN_W 16 +#define CRYPTO_DMACH1LEN_LEN_M 0x0000FFFF +#define CRYPTO_DMACH1LEN_LEN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMABUSCFG +// +//***************************************************************************** +// Field: [15:12] AHB_MST1_BURST_SIZE +// +// Maximum burst size that can be performed on the AHB bus +// ENUMs: +// 64_BYTE 64 bytes +// 32_BYTE 32 bytes +// 16_BYTE 16 bytes +// 8_BYTE 8 bytes +// 4_BYTE 4 bytes +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 + +// Field: [11] AHB_MST1_IDLE_EN +// +// Idle transfer insertion between consecutive burst transfers on AHB +// ENUMs: +// IDLE Idle transfer insertion enabled +// NO_IDLE Do not insert idle transfers. +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 + +// Field: [10] AHB_MST1_INCR_EN +// +// Burst length type of AHB transfer +// ENUMs: +// SPECIFIED Fixed length bursts or single transfers +// UNSPECIFIED Unspecified length burst transfers +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 + +// Field: [9] AHB_MST1_LOCK_EN +// +// Locked transform on AHB +// ENUMs: +// LOCKED Transfers are locked +// NOT_LOCKED Transfers are not locked +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 + +// Field: [8] AHB_MST1_BIGEND +// +// Endianess for the AHB master +// ENUMs: +// BIG_ENDIAN Big Endian +// LITTLE_ENDIAN Little Endian +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAPORTERR +// +//***************************************************************************** +// Field: [12] AHB_ERR +// +// A 1 indicates that the Crypto peripheral has detected an AHB bus error +#define CRYPTO_DMAPORTERR_AHB_ERR 0x00001000 +#define CRYPTO_DMAPORTERR_AHB_ERR_BITN 12 +#define CRYPTO_DMAPORTERR_AHB_ERR_M 0x00001000 +#define CRYPTO_DMAPORTERR_AHB_ERR_S 12 + +// Field: [9] LAST_CH +// +// Indicates which channel was serviced last (channel 0 or channel 1) by the +// AHB master port. +#define CRYPTO_DMAPORTERR_LAST_CH 0x00000200 +#define CRYPTO_DMAPORTERR_LAST_CH_BITN 9 +#define CRYPTO_DMAPORTERR_LAST_CH_M 0x00000200 +#define CRYPTO_DMAPORTERR_LAST_CH_S 9 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAHWVER +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VER +// +// Major version number +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_W 4 +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_M 0x0F000000 +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_S 24 + +// Field: [23:20] HW_MINOR_VER +// +// Minor version number +#define CRYPTO_DMAHWVER_HW_MINOR_VER_W 4 +#define CRYPTO_DMAHWVER_HW_MINOR_VER_M 0x00F00000 +#define CRYPTO_DMAHWVER_HW_MINOR_VER_S 20 + +// Field: [19:16] HW_PATCH_LVL +// +// Patch level. +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_W 4 +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_M 0x000F0000 +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_S 16 + +// Field: [15:8] VER_NUM_COMPL +// +// Bit-by-bit complement of the VER_NUM field bits. +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_W 8 +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_M 0x0000FF00 +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_S 8 + +// Field: [7:0] VER_NUM +// +// Version number of the DMA Controller (209) +#define CRYPTO_DMAHWVER_VER_NUM_W 8 +#define CRYPTO_DMAHWVER_VER_NUM_M 0x000000FF +#define CRYPTO_DMAHWVER_VER_NUM_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYWRITEAREA +// +//***************************************************************************** +// Field: [7] RAM_AREA7 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 + +// Field: [6] RAM_AREA6 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 + +// Field: [5] RAM_AREA5 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 + +// Field: [4] RAM_AREA4 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 + +// Field: [3] RAM_AREA3 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 + +// Field: [2] RAM_AREA2 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 + +// Field: [1] RAM_AREA1 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 + +// Field: [0] RAM_AREA0 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYWRITTENAREA +// +//***************************************************************************** +// Field: [7] RAM_AREA_WRITTEN7 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 + +// Field: [6] RAM_AREA_WRITTEN6 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 + +// Field: [5] RAM_AREA_WRITTEN5 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 + +// Field: [4] RAM_AREA_WRITTEN4 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 + +// Field: [3] RAM_AREA_WRITTEN3 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 + +// Field: [2] RAM_AREA_WRITTEN2 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 + +// Field: [1] RAM_AREA_WRITTEN1 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 + +// Field: [0] RAM_AREA_WRITTEN0 +// +// On read this bit returns the key area written status. +// +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_WRITTEN 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_NOT_WRITTEN 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYSIZE +// +//***************************************************************************** +// Field: [1:0] SIZE +// +// Key size +// +// When writing to this register, KEYWRITTENAREA will be reset. +// +// Note: For the Crypto peripheral this field is fixed to 128 bits. For +// software compatibility KEYWRITTENAREA will be reset when writing to this +// register. +// ENUMs: +// 256_BIT Not supported +// 192_BIT Not supported +// 128_BIT 128 bits +#define CRYPTO_KEYSIZE_SIZE_W 2 +#define CRYPTO_KEYSIZE_SIZE_M 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_S 0 +#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 +#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYREADAREA +// +//***************************************************************************** +// Field: [31] BUSY +// +// Key store operation busy status flag (read only) +// +// 0: operation is completed. +// 1: operation is not completed and the key store is busy. +#define CRYPTO_KEYREADAREA_BUSY 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_BITN 31 +#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_S 31 + +// Field: [3:0] RAM_AREA +// +// Selects the area of the key store RAM from where the key needs to be read +// that will be written to the AES engine. +// +// Only RAM areas that contain valid written keys can be selected. +// ENUMs: +// NO_RAM No RAM +// RAM_AREA7 RAM Area 7 +// RAM_AREA6 RAM Area 6 +// RAM_AREA5 RAM Area 5 +// RAM_AREA4 RAM Area 4 +// RAM_AREA3 RAM Area 3 +// RAM_AREA2 RAM Area 2 +// RAM_AREA1 RAM Area 1 +// RAM_AREA0 RAM Area 0 +#define CRYPTO_KEYREADAREA_RAM_AREA_W 4 +#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F +#define CRYPTO_KEYREADAREA_RAM_AREA_S 0 +#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY20 +// +//***************************************************************************** +// Field: [31:0] KEY2 +// +// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register array. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY20_KEY2_W 32 +#define CRYPTO_AESKEY20_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY20_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY21 +// +//***************************************************************************** +// Field: [31:0] KEY2 +// +// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register array. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY21_KEY2_W 32 +#define CRYPTO_AESKEY21_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY21_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY22 +// +//***************************************************************************** +// Field: [31:0] KEY2 +// +// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register array. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY22_KEY2_W 32 +#define CRYPTO_AESKEY22_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY22_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY23 +// +//***************************************************************************** +// Field: [31:0] KEY2 +// +// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register array. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY23_KEY2_W 32 +#define CRYPTO_AESKEY23_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY23_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY30 +// +//***************************************************************************** +// Field: [31:0] KEY3 +// +// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register arrary. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY30_KEY3_W 32 +#define CRYPTO_AESKEY30_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY30_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY31 +// +//***************************************************************************** +// Field: [31:0] KEY3 +// +// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register arrary. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY31_KEY3_W 32 +#define CRYPTO_AESKEY31_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY31_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY32 +// +//***************************************************************************** +// Field: [31:0] KEY3 +// +// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register arrary. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY32_KEY3_W 32 +#define CRYPTO_AESKEY32_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY32_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY33 +// +//***************************************************************************** +// Field: [31:0] KEY3 +// +// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register arrary. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY33_KEY3_W 32 +#define CRYPTO_AESKEY33_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY33_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV0 +// +//***************************************************************************** +// Field: [31:0] IV +// +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESIV0_IV_W 32 +#define CRYPTO_AESIV0_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV0_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV1 +// +//***************************************************************************** +// Field: [31:0] IV +// +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESIV1_IV_W 32 +#define CRYPTO_AESIV1_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV1_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV2 +// +//***************************************************************************** +// Field: [31:0] IV +// +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESIV2_IV_W 32 +#define CRYPTO_AESIV2_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV2_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV3 +// +//***************************************************************************** +// Field: [31:0] IV +// +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESIV3_IV_W 32 +#define CRYPTO_AESIV3_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV3_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESCTL +// +//***************************************************************************** +// Field: [31] CONTEXT_RDY +// +// If 1, this status bit indicates that the context data registers can be +// overwritten and the Host is permitted to write the next context. Writing a +// context means writing either a mode, the crypto length or +// AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length registers +#define CRYPTO_AESCTL_CONTEXT_RDY 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_RDY_BITN 31 +#define CRYPTO_AESCTL_CONTEXT_RDY_M 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_RDY_S 31 + +// Field: [30] SAVED_CONTEXT_RDY +// +// If read as 1, this status bit indicates that an AES authentication TAG +// and/or IV block(s) is/are available for the Host to retrieve. This bit is +// only asserted if SAVE_CONTEXT is set to 1. The bit is mutually exclusive +// with CONTEXT_RDY. +// +// Writing 1 clears the bit to zero, indicating the Crypto peripheral can start +// its next operation. This bit is also cleared when the 4th word of the output +// TAG and/or IV is read. +// +// Note: All other mode bit writes will be ignored when this mode bit is +// written with 1. +// +// Note: This bit is controlled automatically by the Crypto peripheral for TAG +// read DMA operations. +// +// For typical use, this bit does NOT need to be written, but is used for +// status reading only. In this case, this status bit is automatically +// maintained by the Crypto peripheral. +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 + +// Field: [29] SAVE_CONTEXT +// +// IV must be read before the AES engine can start a new operation. +#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 +#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 + +// Field: [24:22] CCM_M +// +// Defines M that indicates the length of the authentication field for CCM +// operations; the authentication field length equals two times the value of +// CCM_M plus one. +// Note: The Crypto peripheral always returns a 128-bit authentication field, +// of which the M least significant bytes are valid. All values are supported. +#define CRYPTO_AESCTL_CCM_M_W 3 +#define CRYPTO_AESCTL_CCM_M_M 0x01C00000 +#define CRYPTO_AESCTL_CCM_M_S 22 + +// Field: [21:19] CCM_L +// +// Defines L that indicates the width of the length field for CCM operations; +// the length field in bytes equals the value of CMM_L plus one. All values are +// supported. +#define CRYPTO_AESCTL_CCM_L_W 3 +#define CRYPTO_AESCTL_CCM_L_M 0x00380000 +#define CRYPTO_AESCTL_CCM_L_S 19 + +// Field: [18] CCM +// +// AES-CCM mode enable. +// AES-CCM is a combined mode, using AES for both authentication and +// encryption. +// Note: Selecting AES-CCM mode requires writing of AESDATALEN1.LEN_MSW and +// AESDATALEN0.LEN_LSW after all other registers. +// Note: The CTR mode bit in this register must also be set to 1 to enable +// AES-CTR; selecting other AES modes than CTR mode is invalid. +#define CRYPTO_AESCTL_CCM 0x00040000 +#define CRYPTO_AESCTL_CCM_BITN 18 +#define CRYPTO_AESCTL_CCM_M 0x00040000 +#define CRYPTO_AESCTL_CCM_S 18 + +// Field: [15] CBC_MAC +// +// MAC mode enable. +// The DIR bit must be set to 1 for this mode. +// Selecting this mode requires writing the AESDATALEN1.LEN_MSW and +// AESDATALEN0.LEN_LSW registers after all other registers. +#define CRYPTO_AESCTL_CBC_MAC 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_BITN 15 +#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_S 15 + +// Field: [8:7] CTR_WIDTH +// +// Specifies the counter width for AES-CTR mode +// ENUMs: +// 128_BIT 128 bits +// 96_BIT 96 bits +// 64_BIT 64 bits +// 32_BIT 32 bits +#define CRYPTO_AESCTL_CTR_WIDTH_W 2 +#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_S 7 +#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 +#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 +#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 + +// Field: [6] CTR +// +// AES-CTR mode enable +// This bit must also be set for CCM, when encryption/decryption is required. +#define CRYPTO_AESCTL_CTR 0x00000040 +#define CRYPTO_AESCTL_CTR_BITN 6 +#define CRYPTO_AESCTL_CTR_M 0x00000040 +#define CRYPTO_AESCTL_CTR_S 6 + +// Field: [5] CBC +// +// CBC mode enable +#define CRYPTO_AESCTL_CBC 0x00000020 +#define CRYPTO_AESCTL_CBC_BITN 5 +#define CRYPTO_AESCTL_CBC_M 0x00000020 +#define CRYPTO_AESCTL_CBC_S 5 + +// Field: [4:3] KEY_SIZE +// +// This field specifies the key size. +// The key size is automatically configured when a new key is loaded via the +// key store module. +// 00 = N/A - reserved +// 01 = 128 bits +// 10 = N/A - reserved +// 11 = N/A - reserved +// For the Crypto peripheral this field is fixed to 128 bits. +#define CRYPTO_AESCTL_KEY_SIZE_W 2 +#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 +#define CRYPTO_AESCTL_KEY_SIZE_S 3 + +// Field: [2] DIR +// +// Direction. +// 0 : Decrypt operation is performed. +// 1 : Encrypt operation is performed. +// +// This bit must be written with a 1 when CBC-MAC is selected. +#define CRYPTO_AESCTL_DIR 0x00000004 +#define CRYPTO_AESCTL_DIR_BITN 2 +#define CRYPTO_AESCTL_DIR_M 0x00000004 +#define CRYPTO_AESCTL_DIR_S 2 + +// Field: [1] INPUT_RDY +// +// If read as 1, this status bit indicates that the 16-byte AES input buffer is +// empty. The Host is permitted to write the next block of data. +// +// Writing a 0 clears the bit to zero and indicates that the AES engine can use +// the provided input data block. +// +// Writing a 1 to this bit will be ignored. +// +// Note: For DMA operations, this bit is automatically controlled by the Crypto +// peripheral. +// After reset, this bit is 0. After writing a context (note 1), this bit will +// become 1. +// +// For typical use, this bit does NOT need to be written, but is used for +// status reading only. In this case, this status bit is automatically +// maintained by the Crypto peripheral. +#define CRYPTO_AESCTL_INPUT_RDY 0x00000002 +#define CRYPTO_AESCTL_INPUT_RDY_BITN 1 +#define CRYPTO_AESCTL_INPUT_RDY_M 0x00000002 +#define CRYPTO_AESCTL_INPUT_RDY_S 1 + +// Field: [0] OUTPUT_RDY +// +// If read as 1, this status bit indicates that an AES output block is +// available to be retrieved by the Host. +// +// Writing a 0 clears the bit to zero and indicates that output data is read by +// the Host. The AES engine can provide a next output data block. +// +// Writing a 1 to this bit will be ignored. +// +// Note: For DMA operations, this bit is automatically controlled by the Crypto +// peripheral. +// +// For typical use, this bit does NOT need to be written, but is used for +// status reading only. In this case, this status bit is automatically +// maintained by the Crypto peripheral. +#define CRYPTO_AESCTL_OUTPUT_RDY 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_RDY_BITN 0 +#define CRYPTO_AESCTL_OUTPUT_RDY_M 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_RDY_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATALEN0 +// +//***************************************************************************** +// Field: [31:0] LEN_LSW +// +// Used to write the Length values to the Crypto peripheral. +// +// This register contains bits [31:0] of the combined data length. +#define CRYPTO_AESDATALEN0_LEN_LSW_W 32 +#define CRYPTO_AESDATALEN0_LEN_LSW_M 0xFFFFFFFF +#define CRYPTO_AESDATALEN0_LEN_LSW_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATALEN1 +// +//***************************************************************************** +// Field: [28:0] LEN_MSW +// +// Bits [60:32] of the combined data length. +// +// Bits [60:0] of the crypto length registers AESDATALEN1 and AESDATALEN0 store +// the cryptographic data length in bytes for all modes. Once processing with +// this context is started, this length decrements to zero. Data lengths up to +// (2^61 - 1) bytes are allowed. +// For GCM, any value up to 2^36 - 32 bytes can be used. This is because a +// 32-bit counter mode is used; the maximum number of 128-bit blocks is 2^32 - +// 2, resulting in a maximum number of bytes of 2^36 - 32. +// Writing to this register triggers the engine to start using this context. +// This is valid for all modes except GCM and CCM. +// Note: For the combined modes (GCM and CCM), this length does not include the +// authentication only data; the authentication length is specified in the +// AESAUTHLEN.LEN. +// All modes must have a length > 0. For the combined modes, it is allowed to +// have one of the lengths equal to zero. +// For the basic encryption modes (ECB/CBC/CTR) it is allowed to program zero +// to the length field; in that case the length is assumed infinite. +// All data must be byte (8-bit) aligned for stream cipher modes; bit aligned +// data streams are not supported by the Crypto peripheral. For block cipher +// modes, the data length must be programmed in multiples of the block cipher +// size, 16 bytes. +#define CRYPTO_AESDATALEN1_LEN_MSW_W 29 +#define CRYPTO_AESDATALEN1_LEN_MSW_M 0x1FFFFFFF +#define CRYPTO_AESDATALEN1_LEN_MSW_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESAUTHLEN +// +//***************************************************************************** +// Field: [31:0] LEN +// +// Authentication data length in bytes for combined mode, CCM only. +// Supported AAD-lengths for CCM are from 0 to (216 - 28) bytes. Once +// processing with this context is started, this length decrements to zero. +// Writing this register triggers the engine to start using this context for +// CCM. +#define CRYPTO_AESAUTHLEN_LEN_W 32 +#define CRYPTO_AESAUTHLEN_LEN_M 0xFFFFFFFF +#define CRYPTO_AESAUTHLEN_LEN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT0 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data register 0 for output block data from the Crypto peripheral. +// These bits = AES Output Data[31:0] of {127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must +// be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT0_DATA_W 32 +#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT0_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN0 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for input block data to the Crypto peripheral. +// These bits = AES Input Data[31:0] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host write operation, these registers must be written with the 128-bit +// input block for the next AES operation. Writing at a word-aligned offset +// within this address range will store the word (4 bytes) of data into the +// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data +// input buffer. This buffer is used for the next AES operation. If the last +// data block is not completely filled with valid data (see notes below), it is +// allowed to write only the words with valid data. Next AES operation is +// triggered by writing to AESCTL.INPUT_RDY. +// +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. +// For GCM/CCM, the last block of both AAD and message data may contain less +// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically +// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and +// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is +// ignored. +#define CRYPTO_AESDATAIN0_DATA_W 32 +#define CRYPTO_AESDATAIN0_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN0_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT1 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for output block data from the Crypto peripheral. +// These bits = AES Output Data[63:32] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must +// be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT1_DATA_W 32 +#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT1_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN1 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for input block data to the Crypto peripheral. +// These bits = AES Input Data[63:32] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host write operation, these registers must be written with the 128-bit +// input block for the next AES operation. Writing at a word-aligned offset +// within this address range will store the word (4 bytes) of data into the +// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data +// input buffer. This buffer is used for the next AES operation. If the last +// data block is not completely filled with valid data (see notes below), it is +// allowed to write only the words with valid data. Next AES operation is +// triggered by writing to AESCTL.INPUT_RDY. +// +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. +// For GCM/CCM, the last block of both AAD and message data may contain less +// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically +// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and +// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is +// ignored. +#define CRYPTO_AESDATAIN1_DATA_W 32 +#define CRYPTO_AESDATAIN1_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN1_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT2 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for output block data from the Crypto peripheral. +// These bits = AES Output Data[95:64] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must +// be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT2_DATA_W 32 +#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT2_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN2 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for input block data to the Crypto peripheral. +// These bits = AES Input Data[95:64] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host write operation, these registers must be written with the 128-bit +// input block for the next AES operation. Writing at a word-aligned offset +// within this address range will store the word (4 bytes) of data into the +// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data +// input buffer. This buffer is used for the next AES operation. If the last +// data block is not completely filled with valid data (see notes below), it is +// allowed to write only the words with valid data. Next AES operation is +// triggered by writing to AESCTL.INPUT_RDY. +// +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. +// For GCM/CCM, the last block of both AAD and message data may contain less +// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically +// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and +// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is +// ignored. +#define CRYPTO_AESDATAIN2_DATA_W 32 +#define CRYPTO_AESDATAIN2_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN2_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT3 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for output block data from the Crypto peripheral. +// These bits = AES Output Data[127:96] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must +// be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT3_DATA_W 32 +#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT3_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN3 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for input block data to the Crypto peripheral. +// These bits = AES Input Data[127:96] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host write operation, these registers must be written with the 128-bit +// input block for the next AES operation. Writing at a word-aligned offset +// within this address range will store the word (4 bytes) of data into the +// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data +// input buffer. This buffer is used for the next AES operation. If the last +// data block is not completely filled with valid data (see notes below), it is +// allowed to write only the words with valid data. Next AES operation is +// triggered by writing to AESCTL.INPUT_RDY. +// +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. +// For GCM/CCM, the last block of both AAD and message data may contain less +// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically +// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and +// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is +// ignored. +#define CRYPTO_AESDATAIN3_DATA_W 32 +#define CRYPTO_AESDATAIN3_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN3_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT0 +// +//***************************************************************************** +// Field: [31:0] TAG +// +// This register contains the authentication TAG for the combined and +// authentication-only modes. +#define CRYPTO_AESTAGOUT0_TAG_W 32 +#define CRYPTO_AESTAGOUT0_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT0_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT1 +// +//***************************************************************************** +// Field: [31:0] TAG +// +// This register contains the authentication TAG for the combined and +// authentication-only modes. +#define CRYPTO_AESTAGOUT1_TAG_W 32 +#define CRYPTO_AESTAGOUT1_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT1_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT2 +// +//***************************************************************************** +// Field: [31:0] TAG +// +// This register contains the authentication TAG for the combined and +// authentication-only modes. +#define CRYPTO_AESTAGOUT2_TAG_W 32 +#define CRYPTO_AESTAGOUT2_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT2_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT3 +// +//***************************************************************************** +// Field: [31:0] TAG +// +// This register contains the authentication TAG for the combined and +// authentication-only modes. +#define CRYPTO_AESTAGOUT3_TAG_W 32 +#define CRYPTO_AESTAGOUT3_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT3_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_ALGSEL +// +//***************************************************************************** +// Field: [31] TAG +// +// If this bit is cleared to 0, the DMA operation involves only data. +// If this bit is set, the DMA operation includes a TAG (Authentication Result +// / Digest). +#define CRYPTO_ALGSEL_TAG 0x80000000 +#define CRYPTO_ALGSEL_TAG_BITN 31 +#define CRYPTO_ALGSEL_TAG_M 0x80000000 +#define CRYPTO_ALGSEL_TAG_S 31 + +// Field: [1] AES +// +// If set to 1, the AES data is loaded via DMA +// Both Read and Write maximum transfer size to DMA engine is set to 16 bytes +#define CRYPTO_ALGSEL_AES 0x00000002 +#define CRYPTO_ALGSEL_AES_BITN 1 +#define CRYPTO_ALGSEL_AES_M 0x00000002 +#define CRYPTO_ALGSEL_AES_S 1 + +// Field: [0] KEY_STORE +// +// If set to 1, selects the Key Store to be loaded via DMA. +// The maximum transfer size to DMA engine is set to 32 bytes (however +// transfers of 16, 24 and 32 bytes are allowed) +#define CRYPTO_ALGSEL_KEY_STORE 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_BITN 0 +#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAPROTCTL +// +//***************************************************************************** +// Field: [0] EN +// +// Select AHB transfer protection control for DMA transfers using the key store +// area as destination. +// 0 : transfers use 'USER' type access. +// 1 : transfers use 'PRIVILEGED' type access. +#define CRYPTO_DMAPROTCTL_EN 0x00000001 +#define CRYPTO_DMAPROTCTL_EN_BITN 0 +#define CRYPTO_DMAPROTCTL_EN_M 0x00000001 +#define CRYPTO_DMAPROTCTL_EN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_SWRESET +// +//***************************************************************************** +// Field: [0] RESET +// +// If this bit is set to 1, the following modules are reset: +// - Master control internal state is reset. That includes interrupt, error +// status register and result available interrupt generation FSM. +// - Key store module state is reset. That includes clearing the Written Area +// flags; therefore the keys must be reloaded to the key store module. +// Writing 0 has no effect. +// The bit is self cleared after executing the reset. +#define CRYPTO_SWRESET_RESET 0x00000001 +#define CRYPTO_SWRESET_RESET_BITN 0 +#define CRYPTO_SWRESET_RESET_M 0x00000001 +#define CRYPTO_SWRESET_RESET_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQTYPE +// +//***************************************************************************** +// Field: [0] LEVEL +// +// If this bit is 0, the interrupt output is a pulse. +// If this bit is set to 1, the interrupt is a level interrupt that must be +// cleared by writing the interrupt clear register. +// This bit is applicable for both interrupt output signals. +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_BITN 0 +#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQEN +// +//***************************************************************************** +// Field: [1] DMA_IN_DONE +// +// This bit enables IRQSTAT.DMA_IN_DONE as source for IRQ. +#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// This bit enables IRQSTAT.RESULT_AVAIL as source for IRQ. +#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQCLR +// +//***************************************************************************** +// Field: [31] DMA_BUS_ERR +// +// If 1 is written to this bit, IRQSTAT.DMA_BUS_ERR is cleared. +#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 + +// Field: [30] KEY_ST_WR_ERR +// +// If 1 is written to this bit, IRQSTAT.KEY_ST_WR_ERR is cleared. +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 + +// Field: [29] KEY_ST_RD_ERR +// +// If 1 is written to this bit, IRQSTAT.KEY_ST_RD_ERR is cleared. +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 + +// Field: [1] DMA_IN_DONE +// +// If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared. +#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared. +#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQSET +// +//***************************************************************************** +// Field: [1] DMA_IN_DONE +// +// If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set. +// Writing 0 has no effect. +#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set. +// Writing 0 has no effect. +#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQSTAT +// +//***************************************************************************** +// Field: [31] DMA_BUS_ERR +// +// This bit is set when a DMA bus error is detected during a DMA operation. The +// value of this register is held until it is cleared via IRQCLR.DMA_BUS_ERR +// Note: This error is asserted if an error is detected on the AHB master +// interface during a DMA operation. +// Note: This is not an interrupt source. +#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 + +// Field: [30] KEY_ST_WR_ERR +// +// This bit is set when a write error is detected during the DMA write +// operation to the key store memory. The value of this register is held until +// it is cleared via IRQCLR.KEY_ST_WR_ERR +// Note: This error is asserted if a DMA operation does not cover a full key +// area or more areas are written than expected. +// Note: This is not an interrupt source. +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 + +// Field: [29] KEY_ST_RD_ERR +// +// This bit will be set when a read error is detected during the read of a key +// from the key store, while copying it to the AES engine. The value of this +// register is held until it is cleared via IRQCLR.KEY_ST_RD_ERR. +// Note: This error is asserted if a key location is selected in the key store +// that is not available. +// Note: This is not an interrupt source. +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 + +// Field: [1] DMA_IN_DONE +// +// This bit returns the status of DMA data in done interrupt. +#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// This bit is set high when the Crypto peripheral has a result available. +#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HWVER +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VER +// +// Major version number +#define CRYPTO_HWVER_HW_MAJOR_VER_W 4 +#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 +#define CRYPTO_HWVER_HW_MAJOR_VER_S 24 + +// Field: [23:20] HW_MINOR_VER +// +// Minor version number +#define CRYPTO_HWVER_HW_MINOR_VER_W 4 +#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 +#define CRYPTO_HWVER_HW_MINOR_VER_S 20 + +// Field: [19:16] HW_PATCH_LVL +// +// Patch level, starts at 0 at first delivery of this version. +#define CRYPTO_HWVER_HW_PATCH_LVL_W 4 +#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 +#define CRYPTO_HWVER_HW_PATCH_LVL_S 16 + +// Field: [15:8] VER_NUM_COMPL +// +// These bits simply contain the complement of VER_NUM (0x87), used by a driver +// to ascertain that the Crypto peripheral register is indeed read. +#define CRYPTO_HWVER_VER_NUM_COMPL_W 8 +#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 +#define CRYPTO_HWVER_VER_NUM_COMPL_S 8 + +// Field: [7:0] VER_NUM +// +// The version number for the Crypto peripheral, this field contains the value +// 120 (decimal) or 0x78. +#define CRYPTO_HWVER_VER_NUM_W 8 +#define CRYPTO_HWVER_VER_NUM_M 0x000000FF +#define CRYPTO_HWVER_VER_NUM_S 0 + + +#endif // __CRYPTO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi.h new file mode 100644 index 0000000..a83653f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi.h @@ -0,0 +1,197 @@ +/****************************************************************************** +* Filename: hw_ddi.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_DDI_H__ +#define __HW_DDI_H__ + +//***************************************************************************** +// +// This file contains macros for controlling the DDI master and +// accessing DDI Slave registers via the DDI Master. +// There are 3 categories of macros in this file: +// - macros that provide an offset to a register +// located within the DDI Master itself. +// - macros that define bits or bitfields +// within the DDI Master Registers. +// - macros that provide an "instruction offset" +// that are used when accessing a DDI Slave. +// +// The macros that that provide DDI Master register offsets and +// define bits and bitfields for those registers are the typical +// macros that appear in most hw_.h header files. In +// the following example DDI_O_CFG is a macro for a +// register offset and DDI_CFG_WAITFORACK is a macro for +// a bit in that register. This example code will set the WAITFORACK +// bit in register DDI_O_CFG of the DDI Master. (Note: this +// access the Master not the Slave). +// +// HWREG(AUX_OSCDDI_BASE + DDI_O_CFG) |= DDI_CFG_WAITFORACK; +// +// +// The "instruction offset" macros are used to pass an instruction to +// the DDI Master when accessing DDI slave registers. These macros are +// only used when accessing DDI Slave Registers. (Remember DDI +// Master Registers are accessed normally). +// +// The instructions supported when accessing a DDI Slave Regsiter follow: +// - Direct Access to a DDI Slave register. I.e. read or +// write the register. +// - Set the specified bits in a DDI Slave register. +// - Clear the specified bits in a DDI Slave register. +// - Mask write of 4 bits to the a DDI Slave register. +// - Mask write of 8 bits to the a DDI Slave register. +// - Mask write of 16 bits to the a DDI Slave register. +// +// Note: only the "Direct Access" offset should be used when reading +// a DDI Slave register. Only 8- and 16-bit reads are supported. +// +// The generic format of using this marcos for a read follows: +// // read low 16-bits in DDI_SLAVE_OFF +// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR); +// +// // read high 16-bits in DDI_SLAVE_OFF +// // add 2 for data[31:16] +// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_DIR); + +// // read data[31:24] byte in DDI_SLAVE_OFF +// // add 3 for data[31:24] +// myuchar = HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 3 + DDI_O_DIR); +// +// Notes: In the above example: +// - DDI_MASTER_BASE is the base address of the DDI Master defined +// in the hw_memmap.h header file. +// - DDI_SLAVE_OFF is the DDI Slave offset defined in the +// hw_.h header file (e.g. hw_osc_top.h for the oscsc +// oscillator modules. +// - DDI_O_DIR is the "instruction offset" macro defined in this +// file that specifies the Direct Access instruction. +// +// Writes can use any of the "instruction macros". +// The following examples do a "direct write" to DDI Slave register +// DDI_SLAVE_OFF using different size operands: +// +// // ---------- DIRECT WRITES ---------- +// // Write 32-bits aligned +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x12345678; + +// // Write 16-bits aligned to high 16-bits then low 16-bits +// // Add 2 to get to high 16-bits. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0xabcd; +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0xef01; +// +// // Write each byte at DDI_SLAVE_OFF, one at a time. +// // Add 1,2,or 3 to get to bytes 1,2, or 3. +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x33; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 1) = 0x44; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0x55; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 3) = 0x66; +// +// // ---------- SET/CLR ---------- +// The set and clear functions behave similarly to eachother. Each +// can be performed on an 8-, 16-, or 32-bit operand. +// Examples follow: +// // Set all odd bits in a 32-bit words +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_SET) = 0xaaaaaaaa; +// +// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_CLR) = 0x00ff0000; +// +// // Set even bits in byte 2 (data[23:16]) using 8-bit operand +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_CLR) = 0x55; +// +// // ---------- MASKED WRITES ---------- +// The mask writes are a bit different. They operate on nibbles, +// bytes, and 16-bit elements. Two operands are required; a 'mask' +// and 'data'; The operands are concatenated and written to the master. +// e.g. the mask and data are combined as follows for a 16 bit masked +// write: +// (mask << 16) | data; +// Examples follow: +// +// // Write 5555 to low 16-bits of DDI_SLAVE_OFF register +// // a long write is needed (32-bits). +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xffff5555; + +// // Write 1AA to data bits 24:16 in high 16-bits of DDI_SLAVE_OFF register +// // Note add 4 for high 16-bits at DDI_SLAVE_OFF; mask is 1ff! +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 4) = 0x01ff01aa; +// +// // Do an 8 bit masked write of 00 to low byte of register (data[7:0]). +// // a short write is needed (16-bits). +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xff00; +// +// // Do an 8 bit masked write of 11 to byte 1 of register (data[15:8]). +// // add 2 to get to byte 1. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 2) = 0xff11; +// +// // Do an 8 bit masked write of 33 to high byte of register (data[31:24]). +// // add 6 to get to byte 3. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 6) = 0xff33; +// +// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). +// // Byte write is needed. +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xf7; +// +// // Do an 4 bit masked write of 4 to data[7:4]). +// // Add 1 for next nibble +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 1) = 0xf4; +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the DDI master instruction offsets. +// +//***************************************************************************** +#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction +#define DDI_O_SET 0x00000040 // Offset for 'Set' instruction. +#define DDI_O_CLR 0x00000080 // Offset for 'Clear' instruction. +#define DDI_O_MASK4B 0x00000100 // Offset for 4-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 7:4 are mask. Bits 3:0 are data. + // Requires 'byte' write. +#define DDI_O_MASK8B 0x00000180 // Offset for 8-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 15:8 are mask. Bits 7:0 are data. + // Requires 'short' write. +#define DDI_O_MASK16B 0x00000200 // Offset for 16-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 31:16 are mask. Bits 15:0 are data. + // Requires 'long' write. + + + +#endif // __HW_DDI_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi_0_osc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi_0_osc.h new file mode 100644 index 0000000..9363ec1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi_0_osc.h @@ -0,0 +1,1071 @@ +/****************************************************************************** +* Filename: hw_ddi_0_osc_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_DDI_0_OSC_H__ +#define __HW_DDI_0_OSC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// DDI_0_OSC component +// +//***************************************************************************** +// Control 0 +#define DDI_0_OSC_O_CTL0 0x00000000 + +// Control 1 +#define DDI_0_OSC_O_CTL1 0x00000004 + +// RADC External Configuration +#define DDI_0_OSC_O_RADCEXTCFG 0x00000008 + +// Amplitude Compensation Control +#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C + +// Amplitude Compensation Threshold 1 +#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 + +// Amplitude Compensation Threshold 2 +#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 + +// Analog Bypass Values 1 +#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 + +// Internal +#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C + +// Analog Test Control +#define DDI_0_OSC_O_ATESTCTL 0x00000020 + +// ADC Doubler Nanoamp Control +#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 + +// XOSCHF Control +#define DDI_0_OSC_O_XOSCHFCTL 0x00000028 + +// Low Frequency Oscillator Control +#define DDI_0_OSC_O_LFOSCCTL 0x0000002C + +// RCOSCHF Control +#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 + +// Status 0 +#define DDI_0_OSC_O_STAT0 0x00000034 + +// Status 1 +#define DDI_0_OSC_O_STAT1 0x00000038 + +// Status 2 +#define DDI_0_OSC_O_STAT2 0x0000003C + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_CTL0 +// +//***************************************************************************** +// Field: [31] XTAL_IS_24M +// +// Set based on the accurate high frequency XTAL. +// ENUMs: +// 24M Internal. Only to be used through TI provided API. +// 48M Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 + +// Field: [29] BYPASS_XOSC_LF_CLK_QUAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 + +// Field: [28] BYPASS_RCOSC_LF_CLK_QUAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 + +// Field: [27:26] DOUBLER_START_DURATION +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 + +// Field: [25] DOUBLER_RESET_DURATION +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 + +// Field: [22] FORCE_KICKSTART_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN 0x00400000 +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_M 0x00400000 +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_S 22 + +// Field: [16] ALLOW_SCLK_HF_SWITCHING +// +// 0: Default - Switching of HF clock source is disabled . +// 1: Allows switching of sclk_hf source. +// +// Provided to prevent switching of the SCLK_HF source when running from flash +// (a long period during switching could corrupt flash). When sclk_hf +// switching is disabled, a new source can be started when SCLK_HF_SRC_SEL is +// changed, but the switch will not occur until this bit is set. This bit +// should be set to enable clock switching after STAT0.PENDINGSCLKHFSWITCHING +// indicates the new HF clock is ready. When switching completes (also +// indicated by STAT0.PENDINGSCLKHFSWITCHING) sclk_hf switching should be +// disabled to prevent flash corruption. Switching should not be enabled when +// running from flash. +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING 0x00010000 +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_M 0x00010000 +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_S 16 + +// Field: [14] HPOSC_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 + +// Field: [12] RCOSC_LF_TRIMMED +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 + +// Field: [11] XOSC_HF_POWER_MODE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 + +// Field: [10] XOSC_LF_DIG_BYPASS +// +// Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf +// clock. +// +// 0: Use 32kHz XOSC as xosc_lf clock source +// 1: Use digital input (from AON) as xosc_lf clock source. +// +// This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf +// as the sclk_lf source. The muxing performed by this bit is not glitch free. +// The following procedure must be followed when changing this field to avoid +// glitches on sclk_lf. +// +// 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock +// source. +// 2) Set or clear this bit to bypass or not bypass the xosc_lf. +// 3) Set SCLK_LF_SRC_SEL to use xosc_lf. +// +// It is recommended that either the rcosc_hf or xosc_hf (whichever is +// currently active) be selected as the source in step 1 above. This provides a +// faster clock change. +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 + +// Field: [9] CLK_LOSS_EN +// +// Enable clock loss detection and hence the indicators to system controller. +// Checks both SCLK_HF and SCLK_LF clock loss indicators. +// +// 0: Disable +// 1: Enable +// +// Clock loss detection must be disabled when changing the sclk_lf source. +// STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf +// source has completed. +#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 + +// Field: [8:7] ACLK_TDC_SRC_SEL +// +// Source select for aclk_tdc. +// +// 00: RCOSC_HF (48MHz) +// 01: RCOSC_HF (24MHz) +// 10: XOSC_HF (24MHz) +// 11: Not used +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 + +// Field: [6:5] ACLK_REF_SRC_SEL +// +// Source select for aclk_ref +// +// 00: RCOSC_HF derived (31.25kHz) +// 01: XOSC_HF derived (31.25kHz) +// 10: RCOSC_LF (32kHz) +// 11: XOSC_LF (32.768kHz) +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000060 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 5 + +// Field: [3:2] SCLK_LF_SRC_SEL +// +// Source select for sclk_lf +// ENUMs: +// XOSCLF Low frequency XOSC +// RCOSCLF Low frequency RCOSC +// XOSCHFDLF Low frequency clock derived from High Frequency +// XOSC +// RCOSCHFDLF Low frequency clock derived from High Frequency +// RCOSC +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 + +// Field: [1] SCLK_MF_SRC_SEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// XCOSCHFDMF Medium frequency clock derived from high frequency +// XOSC. +// RCOSCHFDMF Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_M 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_S 1 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_XCOSCHFDMF 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_RCOSCHFDMF 0x00000000 + +// Field: [0] SCLK_HF_SRC_SEL +// +// Source select for sclk_hf. XOSC option is supported for test and debug only +// and should be used when the XOSC_HF is running. +// ENUMs: +// XOSC High frequency XOSC clk +// RCOSC High frequency RCOSC clock +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_CTL1 +// +//***************************************************************************** +// Field: [22:18] RCOSCHFCTRIMFRACT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 + +// Field: [17] RCOSCHFCTRIMFRACT_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 + +// Field: [1:0] XOSC_HF_FAST_START +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_RADCEXTCFG +// +//***************************************************************************** +// Field: [31:22] HPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 + +// Field: [21:16] LPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 + +// Field: [15:12] IDAC_STEP +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 + +// Field: [11:6] RADC_DAC_TH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 + +// Field: [5] RADC_MODE_IS_SAR +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPCTL +// +//***************************************************************************** +// Field: [30] AMPCOMP_REQ_MODE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 + +// Field: [29:28] AMPCOMP_FSM_UPDATE_RATE +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 250KHZ Internal. Only to be used through TI provided API. +// 500KHZ Internal. Only to be used through TI provided API. +// 1MHZ Internal. Only to be used through TI provided API. +// 2MHZ Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 + +// Field: [27] AMPCOMP_SW_CTRL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 + +// Field: [26] AMPCOMP_SW_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 + +// Field: [23:20] IBIAS_OFFSET +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 + +// Field: [19:16] IBIAS_INIT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 + +// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 + +// Field: [7:4] CAP_STEP +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 + +// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPTH1 +// +//***************************************************************************** +// Field: [23:18] HPMRAMP3_LTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 + +// Field: [15:10] HPMRAMP3_HTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 + +// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 + +// Field: [5:0] HPMRAMP1_TH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPTH2 +// +//***************************************************************************** +// Field: [31:26] LPMUPDATE_LTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 + +// Field: [23:18] LPMUPDATE_HTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 + +// Field: [15:10] ADC_COMP_AMPTH_LPM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 + +// Field: [7:2] ADC_COMP_AMPTH_HPM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ANABYPASSVAL1 +// +//***************************************************************************** +// Field: [19:16] XOSC_HF_ROW_Q12 +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 + +// Field: [15:0] XOSC_HF_COLUMN_Q12 +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ANABYPASSVAL2 +// +//***************************************************************************** +// Field: [13:0] XOSC_HF_IBIASTHERM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ATESTCTL +// +//***************************************************************************** +// Field: [29] SCLK_LF_AUX_EN +// +// Enable 32 kHz clock to AUX_COMPB. +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x20000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x20000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 29 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL +// +//***************************************************************************** +// Field: [24] NANOAMP_BIAS_ENABLE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 + +// Field: [23] SPARE23 +// +// Software should not rely on the value of a reserved. Writing any other value +// than the reset value may result in undefined behavior +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 + +// Field: [5] ADC_SH_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 + +// Field: [4] ADC_SH_VBUF_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 + +// Field: [1:0] ADC_IREF_CTRL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_XOSCHFCTL +// +//***************************************************************************** +// Field: [9:8] PEAK_DET_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 + +// Field: [6] BYPASS +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 + +// Field: [4:2] HP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 + +// Field: [1:0] LP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_LFOSCCTL +// +//***************************************************************************** +// Field: [23:22] XOSCLF_REGULATOR_TRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 + +// Field: [21:18] XOSCLF_CMIRRWR_RATIO +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 + +// Field: [9:8] RCOSCLF_RTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 6P0MEG Internal. Only to be used through TI provided API. +// 6P5MEG Internal. Only to be used through TI provided API. +// 7P0MEG Internal. Only to be used through TI provided API. +// 7P5MEG Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 + +// Field: [7:0] RCOSCLF_CTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_RCOSCHFCTL +// +//***************************************************************************** +// Field: [15:8] RCOSCHF_CTRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT0 +// +//***************************************************************************** +// Field: [30:29] SCLK_LF_SRC +// +// Indicates source for the sclk_lf +// ENUMs: +// XOSCLF Low frequency XOSC +// RCOSCLF Low frequency RCOSC +// XOSCHFDLF Low frequency clock derived from High Frequency +// XOSC +// RCOSCHFDLF Low frequency clock derived from High Frequency +// RCOSC +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 + +// Field: [28] SCLK_HF_SRC +// +// Indicates source for the sclk_hf +// ENUMs: +// XOSC High frequency XOSC +// RCOSC High frequency RCOSC clock +#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 + +// Field: [22] RCOSC_HF_EN +// +// RCOSC_HF_EN +#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 + +// Field: [21] RCOSC_LF_EN +// +// RCOSC_LF_EN +#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 + +// Field: [20] XOSC_LF_EN +// +// XOSC_LF_EN +#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 + +// Field: [19] CLK_DCDC_RDY +// +// CLK_DCDC_RDY +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 + +// Field: [18] CLK_DCDC_RDY_ACK +// +// CLK_DCDC_RDY_ACK +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 + +// Field: [17] SCLK_HF_LOSS +// +// Indicates sclk_hf is lost +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 + +// Field: [16] SCLK_LF_LOSS +// +// Indicates sclk_lf is lost +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 + +// Field: [15] XOSC_HF_EN +// +// Indicates that XOSC_HF is enabled. +#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 + +// Field: [13] XB_48M_CLK_EN +// +// Indicates that the 48MHz clock from the DOUBLER is enabled. +// +// It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler +// bypass for the 48MHz crystal). +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 + +// Field: [11] XOSC_HF_LP_BUF_EN +// +// XOSC_HF_LP_BUF_EN +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 + +// Field: [10] XOSC_HF_HP_BUF_EN +// +// XOSC_HF_HP_BUF_EN +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 + +// Field: [8] ADC_THMET +// +// ADC_THMET +#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_S 8 + +// Field: [7] ADC_DATA_READY +// +// indicates when adc_data is ready. +#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 + +// Field: [6:1] ADC_DATA +// +// adc_data +#define DDI_0_OSC_STAT0_ADC_DATA_W 6 +#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E +#define DDI_0_OSC_STAT0_ADC_DATA_S 1 + +// Field: [0] PENDINGSCLKHFSWITCHING +// +// Indicates when sclk_hf is ready to be switched +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT1 +// +//***************************************************************************** +// Field: [31:28] RAMPSTATE +// +// AMPCOMP FSM State +// ENUMs: +// FAST_START_SETTLE FAST_START_SETTLE +// FAST_START FAST_START +// DUMMY_TO_INIT_1 DUMMY_TO_INIT_1 +// IDAC_DEC_W_MEASURE IDAC_DECREMENT_WITH_MEASURE +// IBIAS_INC IBIAS_INCREMENT +// LPM_UPDATE LPM_UPDATE +// IBIAS_DEC_W_MEASURE IBIAS_DECREMENT_WITH_MEASURE +// IBIAS_CAP_UPDATE IBIAS_CAP_UPDATE +// IDAC_INCREMENT IDAC_INCREMENT +// HPM_UPDATE HPM_UPDATE +// HPM_RAMP3 HPM_RAMP3 +// HPM_RAMP2 HPM_RAMP2 +// HPM_RAMP1 HPM_RAMP1 +// INITIALIZATION INITIALIZATION +// RESET RESET +#define DDI_0_OSC_STAT1_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_S 28 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 + +// Field: [27:22] HPM_UPDATE_AMP +// +// OSC amplitude during HPM_UPDATE state. +// When amplitude compensation of XOSC_HF is enabled in high performance mode, +// this value is the amplitude of the crystal oscillations measured by the +// on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 +// would indicate that the amplitude of the crystal is approximately 480 mV. +// To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero +// value. +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 + +// Field: [21:16] LPM_UPDATE_AMP +// +// OSC amplitude during LPM_UPDATE state +// When amplitude compensation of XOSC_HF is enabled in low power mode, this +// value is the amplitude of the crystal oscillations measured by the on-chip +// oscillator ADC, divided by 15 mV. For example, a value of 0x20 would +// indicate that the amplitude of the crystal is approximately 480 mV. To +// enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero +// value. +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 + +// Field: [15] FORCE_RCOSC_HF +// +// force_rcosc_hf +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 + +// Field: [14] SCLK_HF_EN +// +// SCLK_HF_EN +#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 + +// Field: [13] SCLK_MF_EN +// +// SCLK_MF_EN +#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 + +// Field: [12] ACLK_ADC_EN +// +// ACLK_ADC_EN +#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 + +// Field: [11] ACLK_TDC_EN +// +// ACLK_TDC_EN +#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 + +// Field: [10] ACLK_REF_EN +// +// ACLK_REF_EN +#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 + +// Field: [9] CLK_CHP_EN +// +// CLK_CHP_EN +#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 + +// Field: [8] CLK_DCDC_EN +// +// CLK_DCDC_EN +#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 + +// Field: [7] SCLK_HF_GOOD +// +// SCLK_HF_GOOD +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 + +// Field: [6] SCLK_MF_GOOD +// +// SCLK_MF_GOOD +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 + +// Field: [5] SCLK_LF_GOOD +// +// SCLK_LF_GOOD +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 + +// Field: [4] ACLK_ADC_GOOD +// +// ACLK_ADC_GOOD +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 + +// Field: [3] ACLK_TDC_GOOD +// +// ACLK_TDC_GOOD +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 + +// Field: [2] ACLK_REF_GOOD +// +// ACLK_REF_GOOD +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 + +// Field: [1] CLK_CHP_GOOD +// +// CLK_CHP_GOOD +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 + +// Field: [0] CLK_DCDC_GOOD +// +// CLK_DCDC_GOOD +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT2 +// +//***************************************************************************** +// Field: [31:26] ADC_DCBIAS +// +// DC Bias read by RADC during SAR mode +// The value is an unsigned integer. It is used for debug only. +#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 + +// Field: [25] HPM_RAMP1_THMET +// +// Indication of threshold is met for hpm_ramp1 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 + +// Field: [24] HPM_RAMP2_THMET +// +// Indication of threshold is met for hpm_ramp2 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 + +// Field: [23] HPM_RAMP3_THMET +// +// Indication of threshold is met for hpm_ramp3 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 + +// Field: [15:12] RAMPSTATE +// +// xosc_hf amplitude compensation FSM +// +// This is identical to STAT1.RAMPSTATE. See that description for encoding. +#define DDI_0_OSC_STAT2_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 +#define DDI_0_OSC_STAT2_RAMPSTATE_S 12 + +// Field: [3] AMPCOMP_REQ +// +// ampcomp_req +#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 + +// Field: [2] XOSC_HF_AMPGOOD +// +// amplitude of xosc_hf is within the required threshold (set by DDI). Not used +// for anything just for debug/status +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 + +// Field: [1] XOSC_HF_FREQGOOD +// +// frequency of xosc_hf is good to use for the digital clocks +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 + +// Field: [0] XOSC_HF_RF_FREQGOOD +// +// frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio +// operations. Used for SW to start synthesizer. +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 + + +#endif // __DDI_0_OSC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_device.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_device.h new file mode 100644 index 0000000..a415529 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_device.h @@ -0,0 +1,168 @@ +/****************************************************************************** +* Filename: hw_device.h +* Revised: 2017-06-21 10:06:25 +0200 (Wed, 21 Jun 2017) +* Revision: 49177 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_DEVICE_H__ +#define __HW_DEVICE_H__ + +#include "../inc/hw_chip_def.h" + +#ifdef CC_GET_CHIP_PACKAGE + +#if ( CC_GET_CHIP_PACKAGE == 0x7 ) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 7x7 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 0x3F +#define AON_EVENT_DIO1 17 +#define AON_EVENT_DIO2 16 +#define AON_EVENT_DIO3 15 +#define AON_EVENT_DIO4 14 +#define AON_EVENT_DIO5 13 +#define AON_EVENT_DIO6 12 +#define AON_EVENT_DIO7 11 +#define AON_EVENT_DIO8 10 +#define AON_EVENT_DIO9 9 +#define AON_EVENT_DIO10 8 +#define AON_EVENT_DIO11 7 +#define AON_EVENT_DIO12 6 +#define AON_EVENT_DIO13 5 +#define AON_EVENT_DIO14 4 +#define AON_EVENT_DIO15 3 +#define AON_EVENT_DIO16 2 +#define AON_EVENT_DIO17 1 +#define AON_EVENT_DIO18 31 +#define AON_EVENT_DIO19 30 +#define AON_EVENT_DIO20 29 +#define AON_EVENT_DIO21 28 +#define AON_EVENT_DIO22 27 +#define AON_EVENT_DIO23 26 +#define AON_EVENT_DIO24 25 +#define AON_EVENT_DIO25 24 +#define AON_EVENT_DIO26 23 +#define AON_EVENT_DIO27 22 +#define AON_EVENT_DIO28 21 +#define AON_EVENT_DIO29 20 +#define AON_EVENT_DIO30 19 +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x7 ) + +#if ( CC_GET_CHIP_PACKAGE == 0x5 ) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 5x5 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 15 +#define AON_EVENT_DIO1 14 +#define AON_EVENT_DIO2 13 +#define AON_EVENT_DIO3 12 +#define AON_EVENT_DIO4 11 +#define AON_EVENT_DIO5 2 +#define AON_EVENT_DIO6 1 +#define AON_EVENT_DIO7 26 +#define AON_EVENT_DIO8 25 +#define AON_EVENT_DIO9 23 +#define AON_EVENT_DIO10 24 +#define AON_EVENT_DIO11 22 +#define AON_EVENT_DIO12 21 +#define AON_EVENT_DIO13 20 +#define AON_EVENT_DIO14 19 +#define AON_EVENT_DIO15 0x3F +#define AON_EVENT_DIO16 0x3F +#define AON_EVENT_DIO17 0x3F +#define AON_EVENT_DIO18 0x3F +#define AON_EVENT_DIO19 0x3F +#define AON_EVENT_DIO20 0x3F +#define AON_EVENT_DIO21 0x3F +#define AON_EVENT_DIO22 0x3F +#define AON_EVENT_DIO23 0x3F +#define AON_EVENT_DIO24 0x3F +#define AON_EVENT_DIO25 0x3F +#define AON_EVENT_DIO26 0x3F +#define AON_EVENT_DIO27 0x3F +#define AON_EVENT_DIO28 0x3F +#define AON_EVENT_DIO29 0x3F +#define AON_EVENT_DIO30 0x3F +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x5 ) + +#if ( CC_GET_CHIP_PACKAGE == 0x4 ) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 4x4 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 13 +#define AON_EVENT_DIO1 12 +#define AON_EVENT_DIO2 11 +#define AON_EVENT_DIO3 2 +#define AON_EVENT_DIO4 1 +#define AON_EVENT_DIO5 26 +#define AON_EVENT_DIO6 25 +#define AON_EVENT_DIO7 24 +#define AON_EVENT_DIO8 23 +#define AON_EVENT_DIO9 22 +#define AON_EVENT_DIO10 0x3F +#define AON_EVENT_DIO11 0x3F +#define AON_EVENT_DIO12 0x3F +#define AON_EVENT_DIO13 0x3F +#define AON_EVENT_DIO14 0x3F +#define AON_EVENT_DIO15 0x3F +#define AON_EVENT_DIO16 0x3F +#define AON_EVENT_DIO17 0x3F +#define AON_EVENT_DIO18 0x3F +#define AON_EVENT_DIO19 0x3F +#define AON_EVENT_DIO20 0x3F +#define AON_EVENT_DIO21 0x3F +#define AON_EVENT_DIO22 0x3F +#define AON_EVENT_DIO23 0x3F +#define AON_EVENT_DIO24 0x3F +#define AON_EVENT_DIO25 0x3F +#define AON_EVENT_DIO26 0x3F +#define AON_EVENT_DIO27 0x3F +#define AON_EVENT_DIO28 0x3F +#define AON_EVENT_DIO29 0x3F +#define AON_EVENT_DIO30 0x3F +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x4 ) + +#endif // defined( CC_GET_CHIP_PACKAGE ) +#endif // __HW_DEVICE_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_event.h new file mode 100644 index 0000000..288b54b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_event.h @@ -0,0 +1,3301 @@ +/****************************************************************************** +* Filename: hw_event_h +* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) +* Revision: 48904 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_EVENT_H__ +#define __HW_EVENT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// EVENT component +// +//***************************************************************************** +// Output Selection for CPU Interrupt 0 +#define EVENT_O_CPUIRQSEL0 0x00000000 + +// Output Selection for CPU Interrupt 1 +#define EVENT_O_CPUIRQSEL1 0x00000004 + +// Output Selection for CPU Interrupt 2 +#define EVENT_O_CPUIRQSEL2 0x00000008 + +// Output Selection for CPU Interrupt 3 +#define EVENT_O_CPUIRQSEL3 0x0000000C + +// Output Selection for CPU Interrupt 4 +#define EVENT_O_CPUIRQSEL4 0x00000010 + +// Output Selection for CPU Interrupt 5 +#define EVENT_O_CPUIRQSEL5 0x00000014 + +// Output Selection for CPU Interrupt 6 +#define EVENT_O_CPUIRQSEL6 0x00000018 + +// Output Selection for CPU Interrupt 7 +#define EVENT_O_CPUIRQSEL7 0x0000001C + +// Output Selection for CPU Interrupt 8 +#define EVENT_O_CPUIRQSEL8 0x00000020 + +// Output Selection for CPU Interrupt 9 +#define EVENT_O_CPUIRQSEL9 0x00000024 + +// Output Selection for CPU Interrupt 10 +#define EVENT_O_CPUIRQSEL10 0x00000028 + +// Output Selection for CPU Interrupt 11 +#define EVENT_O_CPUIRQSEL11 0x0000002C + +// Output Selection for CPU Interrupt 12 +#define EVENT_O_CPUIRQSEL12 0x00000030 + +// Output Selection for CPU Interrupt 13 +#define EVENT_O_CPUIRQSEL13 0x00000034 + +// Output Selection for CPU Interrupt 14 +#define EVENT_O_CPUIRQSEL14 0x00000038 + +// Output Selection for CPU Interrupt 15 +#define EVENT_O_CPUIRQSEL15 0x0000003C + +// Output Selection for CPU Interrupt 16 +#define EVENT_O_CPUIRQSEL16 0x00000040 + +// Output Selection for CPU Interrupt 17 +#define EVENT_O_CPUIRQSEL17 0x00000044 + +// Output Selection for CPU Interrupt 18 +#define EVENT_O_CPUIRQSEL18 0x00000048 + +// Output Selection for CPU Interrupt 19 +#define EVENT_O_CPUIRQSEL19 0x0000004C + +// Output Selection for CPU Interrupt 20 +#define EVENT_O_CPUIRQSEL20 0x00000050 + +// Output Selection for CPU Interrupt 21 +#define EVENT_O_CPUIRQSEL21 0x00000054 + +// Output Selection for CPU Interrupt 22 +#define EVENT_O_CPUIRQSEL22 0x00000058 + +// Output Selection for CPU Interrupt 23 +#define EVENT_O_CPUIRQSEL23 0x0000005C + +// Output Selection for CPU Interrupt 24 +#define EVENT_O_CPUIRQSEL24 0x00000060 + +// Output Selection for CPU Interrupt 25 +#define EVENT_O_CPUIRQSEL25 0x00000064 + +// Output Selection for CPU Interrupt 26 +#define EVENT_O_CPUIRQSEL26 0x00000068 + +// Output Selection for CPU Interrupt 27 +#define EVENT_O_CPUIRQSEL27 0x0000006C + +// Output Selection for CPU Interrupt 28 +#define EVENT_O_CPUIRQSEL28 0x00000070 + +// Output Selection for CPU Interrupt 29 +#define EVENT_O_CPUIRQSEL29 0x00000074 + +// Output Selection for CPU Interrupt 30 +#define EVENT_O_CPUIRQSEL30 0x00000078 + +// Output Selection for CPU Interrupt 31 +#define EVENT_O_CPUIRQSEL31 0x0000007C + +// Output Selection for CPU Interrupt 32 +#define EVENT_O_CPUIRQSEL32 0x00000080 + +// Output Selection for CPU Interrupt 33 +#define EVENT_O_CPUIRQSEL33 0x00000084 + +// Output Selection for RFC Event 0 +#define EVENT_O_RFCSEL0 0x00000100 + +// Output Selection for RFC Event 1 +#define EVENT_O_RFCSEL1 0x00000104 + +// Output Selection for RFC Event 2 +#define EVENT_O_RFCSEL2 0x00000108 + +// Output Selection for RFC Event 3 +#define EVENT_O_RFCSEL3 0x0000010C + +// Output Selection for RFC Event 4 +#define EVENT_O_RFCSEL4 0x00000110 + +// Output Selection for RFC Event 5 +#define EVENT_O_RFCSEL5 0x00000114 + +// Output Selection for RFC Event 6 +#define EVENT_O_RFCSEL6 0x00000118 + +// Output Selection for RFC Event 7 +#define EVENT_O_RFCSEL7 0x0000011C + +// Output Selection for RFC Event 8 +#define EVENT_O_RFCSEL8 0x00000120 + +// Output Selection for RFC Event 9 +#define EVENT_O_RFCSEL9 0x00000124 + +// Output Selection for GPT0 0 +#define EVENT_O_GPT0ACAPTSEL 0x00000200 + +// Output Selection for GPT0 1 +#define EVENT_O_GPT0BCAPTSEL 0x00000204 + +// Output Selection for GPT1 0 +#define EVENT_O_GPT1ACAPTSEL 0x00000300 + +// Output Selection for GPT1 1 +#define EVENT_O_GPT1BCAPTSEL 0x00000304 + +// Output Selection for GPT2 0 +#define EVENT_O_GPT2ACAPTSEL 0x00000400 + +// Output Selection for GPT2 1 +#define EVENT_O_GPT2BCAPTSEL 0x00000404 + +// Output Selection for DMA Channel 1 SREQ +#define EVENT_O_UDMACH1SSEL 0x00000508 + +// Output Selection for DMA Channel 1 REQ +#define EVENT_O_UDMACH1BSEL 0x0000050C + +// Output Selection for DMA Channel 2 SREQ +#define EVENT_O_UDMACH2SSEL 0x00000510 + +// Output Selection for DMA Channel 2 REQ +#define EVENT_O_UDMACH2BSEL 0x00000514 + +// Output Selection for DMA Channel 3 SREQ +#define EVENT_O_UDMACH3SSEL 0x00000518 + +// Output Selection for DMA Channel 3 REQ +#define EVENT_O_UDMACH3BSEL 0x0000051C + +// Output Selection for DMA Channel 4 SREQ +#define EVENT_O_UDMACH4SSEL 0x00000520 + +// Output Selection for DMA Channel 4 REQ +#define EVENT_O_UDMACH4BSEL 0x00000524 + +// Output Selection for DMA Channel 5 SREQ +#define EVENT_O_UDMACH5SSEL 0x00000528 + +// Output Selection for DMA Channel 5 REQ +#define EVENT_O_UDMACH5BSEL 0x0000052C + +// Output Selection for DMA Channel 6 SREQ +#define EVENT_O_UDMACH6SSEL 0x00000530 + +// Output Selection for DMA Channel 6 REQ +#define EVENT_O_UDMACH6BSEL 0x00000534 + +// Output Selection for DMA Channel 7 SREQ +#define EVENT_O_UDMACH7SSEL 0x00000538 + +// Output Selection for DMA Channel 7 REQ +#define EVENT_O_UDMACH7BSEL 0x0000053C + +// Output Selection for DMA Channel 8 SREQ +#define EVENT_O_UDMACH8SSEL 0x00000540 + +// Output Selection for DMA Channel 8 REQ +#define EVENT_O_UDMACH8BSEL 0x00000544 + +// Output Selection for DMA Channel 9 SREQ +#define EVENT_O_UDMACH9SSEL 0x00000548 + +// Output Selection for DMA Channel 9 REQ +#define EVENT_O_UDMACH9BSEL 0x0000054C + +// Output Selection for DMA Channel 10 SREQ +#define EVENT_O_UDMACH10SSEL 0x00000550 + +// Output Selection for DMA Channel 10 REQ +#define EVENT_O_UDMACH10BSEL 0x00000554 + +// Output Selection for DMA Channel 11 SREQ +#define EVENT_O_UDMACH11SSEL 0x00000558 + +// Output Selection for DMA Channel 11 REQ +#define EVENT_O_UDMACH11BSEL 0x0000055C + +// Output Selection for DMA Channel 12 SREQ +#define EVENT_O_UDMACH12SSEL 0x00000560 + +// Output Selection for DMA Channel 12 REQ +#define EVENT_O_UDMACH12BSEL 0x00000564 + +// Output Selection for DMA Channel 13 REQ +#define EVENT_O_UDMACH13BSEL 0x0000056C + +// Output Selection for DMA Channel 14 REQ +#define EVENT_O_UDMACH14BSEL 0x00000574 + +// Output Selection for DMA Channel 15 REQ +#define EVENT_O_UDMACH15BSEL 0x0000057C + +// Output Selection for DMA Channel 16 SREQ +#define EVENT_O_UDMACH16SSEL 0x00000580 + +// Output Selection for DMA Channel 16 REQ +#define EVENT_O_UDMACH16BSEL 0x00000584 + +// Output Selection for DMA Channel 17 SREQ +#define EVENT_O_UDMACH17SSEL 0x00000588 + +// Output Selection for DMA Channel 17 REQ +#define EVENT_O_UDMACH17BSEL 0x0000058C + +// Output Selection for DMA Channel 21 SREQ +#define EVENT_O_UDMACH21SSEL 0x000005A8 + +// Output Selection for DMA Channel 21 REQ +#define EVENT_O_UDMACH21BSEL 0x000005AC + +// Output Selection for DMA Channel 22 SREQ +#define EVENT_O_UDMACH22SSEL 0x000005B0 + +// Output Selection for DMA Channel 22 REQ +#define EVENT_O_UDMACH22BSEL 0x000005B4 + +// Output Selection for DMA Channel 23 SREQ +#define EVENT_O_UDMACH23SSEL 0x000005B8 + +// Output Selection for DMA Channel 23 REQ +#define EVENT_O_UDMACH23BSEL 0x000005BC + +// Output Selection for DMA Channel 24 SREQ +#define EVENT_O_UDMACH24SSEL 0x000005C0 + +// Output Selection for DMA Channel 24 REQ +#define EVENT_O_UDMACH24BSEL 0x000005C4 + +// Output Selection for GPT3 0 +#define EVENT_O_GPT3ACAPTSEL 0x00000600 + +// Output Selection for GPT3 1 +#define EVENT_O_GPT3BCAPTSEL 0x00000604 + +// Output Selection for AUX Subscriber 0 +#define EVENT_O_AUXSEL0 0x00000700 + +// Output Selection for NMI Subscriber 0 +#define EVENT_O_CM3NMISEL0 0x00000800 + +// Output Selection for I2S Subscriber 0 +#define EVENT_O_I2SSTMPSEL0 0x00000900 + +// Output Selection for FRZ Subscriber +#define EVENT_O_FRZSEL0 0x00000A00 + +// Set or Clear Software Events +#define EVENT_O_SWEV 0x00000F00 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +#define EVENT_CPUIRQSEL0_EV_W 7 +#define EVENT_CPUIRQSEL0_EV_M 0x0000007F +#define EVENT_CPUIRQSEL0_EV_S 0 +#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL1 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// I2C_IRQ Interrupt event from I2C +#define EVENT_CPUIRQSEL1_EV_W 7 +#define EVENT_CPUIRQSEL1_EV_M 0x0000007F +#define EVENT_CPUIRQSEL1_EV_S 0 +#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL2 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +#define EVENT_CPUIRQSEL2_EV_W 7 +#define EVENT_CPUIRQSEL2_EV_M 0x0000007F +#define EVENT_CPUIRQSEL2_EV_S 0 +#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL4 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +#define EVENT_CPUIRQSEL4_EV_W 7 +#define EVENT_CPUIRQSEL4_EV_M 0x0000007F +#define EVENT_CPUIRQSEL4_EV_S 0 +#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL5 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +#define EVENT_CPUIRQSEL5_EV_W 7 +#define EVENT_CPUIRQSEL5_EV_M 0x0000007F +#define EVENT_CPUIRQSEL5_EV_S 0 +#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL6 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SWEV0 AUX software event 0, triggered by +// AUX_EVCTL:SWEVSET.SWEV0, also available as +// AUX_EVENT0 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +// AUX domain wakeup control +// AON_EVENT:AUXWUSEL +#define EVENT_CPUIRQSEL6_EV_W 7 +#define EVENT_CPUIRQSEL6_EV_M 0x0000007F +#define EVENT_CPUIRQSEL6_EV_S 0 +#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL7 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +#define EVENT_CPUIRQSEL7_EV_W 7 +#define EVENT_CPUIRQSEL7_EV_M 0x0000007F +#define EVENT_CPUIRQSEL7_EV_S 0 +#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL8 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +#define EVENT_CPUIRQSEL8_EV_W 7 +#define EVENT_CPUIRQSEL8_EV_M 0x0000007F +#define EVENT_CPUIRQSEL8_EV_S 0 +#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL9 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +#define EVENT_CPUIRQSEL9_EV_W 7 +#define EVENT_CPUIRQSEL9_EV_M 0x0000007F +#define EVENT_CPUIRQSEL9_EV_S 0 +#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL10 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +#define EVENT_CPUIRQSEL10_EV_W 7 +#define EVENT_CPUIRQSEL10_EV_M 0x0000007F +#define EVENT_CPUIRQSEL10_EV_S 0 +#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL11 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +#define EVENT_CPUIRQSEL11_EV_W 7 +#define EVENT_CPUIRQSEL11_EV_M 0x0000007F +#define EVENT_CPUIRQSEL11_EV_S 0 +#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL12 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// I2S_IRQ Interrupt event from I2S +#define EVENT_CPUIRQSEL12_EV_W 7 +#define EVENT_CPUIRQSEL12_EV_M 0x0000007F +#define EVENT_CPUIRQSEL12_EV_S 0 +#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL13 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SWEV1 AUX software event 1, triggered by +// AUX_EVCTL:SWEVSET.SWEV1, also available as +// AUX_EVENT2 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +// AUX domain wakeup control +// AON_EVENT:AUXWUSEL +#define EVENT_CPUIRQSEL13_EV_W 7 +#define EVENT_CPUIRQSEL13_EV_M 0x0000007F +#define EVENT_CPUIRQSEL13_EV_S 0 +#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL14 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +#define EVENT_CPUIRQSEL14_EV_W 7 +#define EVENT_CPUIRQSEL14_EV_M 0x0000007F +#define EVENT_CPUIRQSEL14_EV_S 0 +#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL15 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +#define EVENT_CPUIRQSEL15_EV_W 7 +#define EVENT_CPUIRQSEL15_EV_M 0x0000007F +#define EVENT_CPUIRQSEL15_EV_S 0 +#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL16 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +#define EVENT_CPUIRQSEL16_EV_W 7 +#define EVENT_CPUIRQSEL16_EV_M 0x0000007F +#define EVENT_CPUIRQSEL16_EV_S 0 +#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL17 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +#define EVENT_CPUIRQSEL17_EV_W 7 +#define EVENT_CPUIRQSEL17_EV_M 0x0000007F +#define EVENT_CPUIRQSEL17_EV_S 0 +#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL18 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +#define EVENT_CPUIRQSEL18_EV_W 7 +#define EVENT_CPUIRQSEL18_EV_M 0x0000007F +#define EVENT_CPUIRQSEL18_EV_S 0 +#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL19 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +#define EVENT_CPUIRQSEL19_EV_W 7 +#define EVENT_CPUIRQSEL19_EV_M 0x0000007F +#define EVENT_CPUIRQSEL19_EV_S 0 +#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL20 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +#define EVENT_CPUIRQSEL20_EV_W 7 +#define EVENT_CPUIRQSEL20_EV_M 0x0000007F +#define EVENT_CPUIRQSEL20_EV_S 0 +#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL21 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +#define EVENT_CPUIRQSEL21_EV_W 7 +#define EVENT_CPUIRQSEL21_EV_M 0x0000007F +#define EVENT_CPUIRQSEL21_EV_S 0 +#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL22 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +#define EVENT_CPUIRQSEL22_EV_W 7 +#define EVENT_CPUIRQSEL22_EV_M 0x0000007F +#define EVENT_CPUIRQSEL22_EV_S 0 +#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL23 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +#define EVENT_CPUIRQSEL23_EV_W 7 +#define EVENT_CPUIRQSEL23_EV_M 0x0000007F +#define EVENT_CPUIRQSEL23_EV_S 0 +#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL24 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +#define EVENT_CPUIRQSEL24_EV_W 7 +#define EVENT_CPUIRQSEL24_EV_M 0x0000007F +#define EVENT_CPUIRQSEL24_EV_S 0 +#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL25 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS +#define EVENT_CPUIRQSEL25_EV_W 7 +#define EVENT_CPUIRQSEL25_EV_M 0x0000007F +#define EVENT_CPUIRQSEL25_EV_S 0 +#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL26 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +#define EVENT_CPUIRQSEL26_EV_W 7 +#define EVENT_CPUIRQSEL26_EV_M 0x0000007F +#define EVENT_CPUIRQSEL26_EV_S 0 +#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL27 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_CPUIRQSEL27_EV_W 7 +#define EVENT_CPUIRQSEL27_EV_M 0x0000007F +#define EVENT_CPUIRQSEL27_EV_S 0 +#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL28 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +#define EVENT_CPUIRQSEL28_EV_W 7 +#define EVENT_CPUIRQSEL28_EV_M 0x0000007F +#define EVENT_CPUIRQSEL28_EV_S 0 +#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL29 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +#define EVENT_CPUIRQSEL29_EV_W 7 +#define EVENT_CPUIRQSEL29_EV_M 0x0000007F +#define EVENT_CPUIRQSEL29_EV_S 0 +#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL30 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg +// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled +// by CRYPTO:IRQEN.DMA_IN_DONE +// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, +// see UDMA0:SOFTREQ +// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see +// UDMA0:SOFTREQ +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2S_IRQ Interrupt event from I2S +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// NONE Always inactive +#define EVENT_CPUIRQSEL30_EV_W 7 +#define EVENT_CPUIRQSEL30_EV_M 0x0000007F +#define EVENT_CPUIRQSEL30_EV_S 0 +#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 +#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B +#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 +#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 +#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 +#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL31 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +#define EVENT_CPUIRQSEL31_EV_W 7 +#define EVENT_CPUIRQSEL31_EV_M 0x0000007F +#define EVENT_CPUIRQSEL31_EV_S 0 +#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL32 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +#define EVENT_CPUIRQSEL32_EV_W 7 +#define EVENT_CPUIRQSEL32_EV_M 0x0000007F +#define EVENT_CPUIRQSEL32_EV_S 0 +#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL33 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN +#define EVENT_CPUIRQSEL33_EV_W 7 +#define EVENT_CPUIRQSEL33_EV_M 0x0000007F +#define EVENT_CPUIRQSEL33_EV_S 0 +#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +#define EVENT_RFCSEL0_EV_W 7 +#define EVENT_RFCSEL0_EV_M 0x0000007F +#define EVENT_RFCSEL0_EV_S 0 +#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL1 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +#define EVENT_RFCSEL1_EV_W 7 +#define EVENT_RFCSEL1_EV_M 0x0000007F +#define EVENT_RFCSEL1_EV_S 0 +#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL2 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +#define EVENT_RFCSEL2_EV_W 7 +#define EVENT_RFCSEL2_EV_M 0x0000007F +#define EVENT_RFCSEL2_EV_S 0 +#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL3 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +#define EVENT_RFCSEL3_EV_W 7 +#define EVENT_RFCSEL3_EV_M 0x0000007F +#define EVENT_RFCSEL3_EV_S 0 +#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL4 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +#define EVENT_RFCSEL4_EV_W 7 +#define EVENT_RFCSEL4_EV_M 0x0000007F +#define EVENT_RFCSEL4_EV_S 0 +#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL5 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +#define EVENT_RFCSEL5_EV_W 7 +#define EVENT_RFCSEL5_EV_M 0x0000007F +#define EVENT_RFCSEL5_EV_S 0 +#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL6 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +#define EVENT_RFCSEL6_EV_W 7 +#define EVENT_RFCSEL6_EV_M 0x0000007F +#define EVENT_RFCSEL6_EV_S 0 +#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL7 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +#define EVENT_RFCSEL7_EV_W 7 +#define EVENT_RFCSEL7_EV_M 0x0000007F +#define EVENT_RFCSEL7_EV_S 0 +#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL8 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +#define EVENT_RFCSEL8_EV_W 7 +#define EVENT_RFCSEL8_EV_M 0x0000007F +#define EVENT_RFCSEL8_EV_S 0 +#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL9 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2S_IRQ Interrupt event from I2S +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +// NONE Always inactive +#define EVENT_RFCSEL9_EV_W 7 +#define EVENT_RFCSEL9_EV_M 0x0000007F +#define EVENT_RFCSEL9_EV_S 0 +#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B +#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A +#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_RFCSEL9_EV_SWEV1 0x00000065 +#define EVENT_RFCSEL9_EV_SWEV0 0x00000064 +#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 +#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 +#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 +#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 +#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 +#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 +#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 +#define EVENT_RFCSEL9_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT0ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT0ACAPTSEL_EV_W 7 +#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0ACAPTSEL_EV_S 0 +#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT0BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT0BCAPTSEL_EV_W 7 +#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0BCAPTSEL_EV_S 0 +#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT1ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT1ACAPTSEL_EV_W 7 +#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1ACAPTSEL_EV_S 0 +#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT1BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT1BCAPTSEL_EV_W 7 +#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1BCAPTSEL_EV_S 0 +#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT2ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT2ACAPTSEL_EV_W 7 +#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2ACAPTSEL_EV_S 0 +#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT2BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT2BCAPTSEL_EV_W 7 +#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2BCAPTSEL_EV_S 0 +#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH1SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by +// UART0:DMACTL.RXDMAE +#define EVENT_UDMACH1SSEL_EV_W 7 +#define EVENT_UDMACH1SSEL_EV_M 0x0000007F +#define EVENT_UDMACH1SSEL_EV_S 0 +#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH1BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by +// UART0:DMACTL.RXDMAE +#define EVENT_UDMACH1BSEL_EV_W 7 +#define EVENT_UDMACH1BSEL_EV_M 0x0000007F +#define EVENT_UDMACH1BSEL_EV_S 0 +#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH2SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by +// UART0:DMACTL.TXDMAE +#define EVENT_UDMACH2SSEL_EV_W 7 +#define EVENT_UDMACH2SSEL_EV_M 0x0000007F +#define EVENT_UDMACH2SSEL_EV_S 0 +#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH2BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by +// UART0:DMACTL.TXDMAE +#define EVENT_UDMACH2BSEL_EV_W 7 +#define EVENT_UDMACH2BSEL_EV_M 0x0000007F +#define EVENT_UDMACH2BSEL_EV_S 0 +#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH3SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH3SSEL_EV_W 7 +#define EVENT_UDMACH3SSEL_EV_M 0x0000007F +#define EVENT_UDMACH3SSEL_EV_S 0 +#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH3BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH3BSEL_EV_W 7 +#define EVENT_UDMACH3BSEL_EV_M 0x0000007F +#define EVENT_UDMACH3BSEL_EV_S 0 +#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH4SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH4SSEL_EV_W 7 +#define EVENT_UDMACH4SSEL_EV_M 0x0000007F +#define EVENT_UDMACH4SSEL_EV_S 0 +#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH4BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH4BSEL_EV_W 7 +#define EVENT_UDMACH4BSEL_EV_M 0x0000007F +#define EVENT_UDMACH4BSEL_EV_S 0 +#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH5SSEL +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_UDMACH5BSEL +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_UDMACH6SSEL +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_UDMACH6BSEL +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_UDMACH7SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_DMASREQ DMA single request event from AUX, configured by +// AUX_EVCTL:DMACTL +#define EVENT_UDMACH7SSEL_EV_W 7 +#define EVENT_UDMACH7SSEL_EV_M 0x0000007F +#define EVENT_UDMACH7SSEL_EV_S 0 +#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH7BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_DMABREQ DMA burst request event from AUX, configured by +// AUX_EVCTL:DMACTL +#define EVENT_UDMACH7BSEL_EV_W 7 +#define EVENT_UDMACH7BSEL_EV_M 0x0000007F +#define EVENT_UDMACH7BSEL_EV_S 0 +#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH8SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +#define EVENT_UDMACH8SSEL_EV_W 7 +#define EVENT_UDMACH8SSEL_EV_M 0x0000007F +#define EVENT_UDMACH8SSEL_EV_S 0 +#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH8BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +#define EVENT_UDMACH8BSEL_EV_W 7 +#define EVENT_UDMACH8BSEL_EV_M 0x0000007F +#define EVENT_UDMACH8BSEL_EV_S 0 +#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH9SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH9SSEL_EV_W 7 +#define EVENT_UDMACH9SSEL_EV_M 0x0000007F +#define EVENT_UDMACH9SSEL_EV_S 0 +#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 +#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH9BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH9BSEL_EV_W 7 +#define EVENT_UDMACH9BSEL_EV_M 0x0000007F +#define EVENT_UDMACH9BSEL_EV_S 0 +#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH10SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH10SSEL_EV_W 7 +#define EVENT_UDMACH10SSEL_EV_M 0x0000007F +#define EVENT_UDMACH10SSEL_EV_S 0 +#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 +#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH10BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH10BSEL_EV_W 7 +#define EVENT_UDMACH10BSEL_EV_M 0x0000007F +#define EVENT_UDMACH10BSEL_EV_S 0 +#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH11SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH11SSEL_EV_W 7 +#define EVENT_UDMACH11SSEL_EV_M 0x0000007F +#define EVENT_UDMACH11SSEL_EV_S 0 +#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 +#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH11BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH11BSEL_EV_W 7 +#define EVENT_UDMACH11BSEL_EV_M 0x0000007F +#define EVENT_UDMACH11BSEL_EV_S 0 +#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH12SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH12SSEL_EV_W 7 +#define EVENT_UDMACH12SSEL_EV_M 0x0000007F +#define EVENT_UDMACH12SSEL_EV_S 0 +#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 +#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH12BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH12BSEL_EV_W 7 +#define EVENT_UDMACH12BSEL_EV_M 0x0000007F +#define EVENT_UDMACH12BSEL_EV_S 0 +#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH13BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +#define EVENT_UDMACH13BSEL_EV_W 7 +#define EVENT_UDMACH13BSEL_EV_M 0x0000007F +#define EVENT_UDMACH13BSEL_EV_S 0 +#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH14BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// CPU_HALTED CPU halted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_DMABREQ DMA burst request event from AUX, configured by +// AUX_EVCTL:DMACTL +// AUX_DMASREQ DMA single request event from AUX, configured by +// AUX_EVCTL:DMACTL +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +// WDT_NMI Watchdog non maskable interrupt event, controlled +// by WDT:CTL.INTTYPE +// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg +// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled +// by CRYPTO:IRQEN.DMA_IN_DONE +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by +// UART0:DMACTL.TXDMAE +// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by +// UART0:DMACTL.TXDMAE +// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by +// UART0:DMACTL.RXDMAE +// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by +// UART0:DMACTL.RXDMAE +// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// AUX_SWEV1 AUX software event 1, triggered by +// AUX_EVCTL:SWEVSET.SWEV1, also available as +// AUX_EVENT2 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +// AUX domain wakeup control +// AON_EVENT:AUXWUSEL +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, +// see UDMA0:SOFTREQ +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see +// UDMA0:SOFTREQ +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2C_IRQ Interrupt event from I2C +// I2S_IRQ Interrupt event from I2S +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +// NONE Always inactive +#define EVENT_UDMACH14BSEL_EV_W 7 +#define EVENT_UDMACH14BSEL_EV_M 0x0000007F +#define EVENT_UDMACH14BSEL_EV_S 0 +#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 +#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 +#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 +#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 +#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 +#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 +#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 +#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 +#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 +#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 +#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 +#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 +#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 +#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F +#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E +#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D +#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C +#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B +#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 +#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 +#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 +#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH15BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +#define EVENT_UDMACH15BSEL_EV_W 7 +#define EVENT_UDMACH15BSEL_EV_M 0x0000007F +#define EVENT_UDMACH15BSEL_EV_S 0 +#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH16SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH16SSEL_EV_W 7 +#define EVENT_UDMACH16SSEL_EV_M 0x0000007F +#define EVENT_UDMACH16SSEL_EV_S 0 +#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH16BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH16BSEL_EV_W 7 +#define EVENT_UDMACH16BSEL_EV_M 0x0000007F +#define EVENT_UDMACH16BSEL_EV_S 0 +#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH17SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH17SSEL_EV_W 7 +#define EVENT_UDMACH17SSEL_EV_M 0x0000007F +#define EVENT_UDMACH17SSEL_EV_S 0 +#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH17BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH17BSEL_EV_W 7 +#define EVENT_UDMACH17BSEL_EV_M 0x0000007F +#define EVENT_UDMACH17BSEL_EV_S 0 +#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH21SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_UDMACH21SSEL_EV_W 7 +#define EVENT_UDMACH21SSEL_EV_M 0x0000007F +#define EVENT_UDMACH21SSEL_EV_S 0 +#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH21BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_UDMACH21BSEL_EV_W 7 +#define EVENT_UDMACH21BSEL_EV_M 0x0000007F +#define EVENT_UDMACH21BSEL_EV_S 0 +#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH22SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +#define EVENT_UDMACH22SSEL_EV_W 7 +#define EVENT_UDMACH22SSEL_EV_M 0x0000007F +#define EVENT_UDMACH22SSEL_EV_S 0 +#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH22BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +#define EVENT_UDMACH22BSEL_EV_W 7 +#define EVENT_UDMACH22BSEL_EV_M 0x0000007F +#define EVENT_UDMACH22BSEL_EV_S 0 +#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH23SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +#define EVENT_UDMACH23SSEL_EV_W 7 +#define EVENT_UDMACH23SSEL_EV_M 0x0000007F +#define EVENT_UDMACH23SSEL_EV_S 0 +#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH23BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +#define EVENT_UDMACH23BSEL_EV_W 7 +#define EVENT_UDMACH23BSEL_EV_M 0x0000007F +#define EVENT_UDMACH23BSEL_EV_S 0 +#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH24SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +#define EVENT_UDMACH24SSEL_EV_W 7 +#define EVENT_UDMACH24SSEL_EV_M 0x0000007F +#define EVENT_UDMACH24SSEL_EV_S 0 +#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH24BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +#define EVENT_UDMACH24BSEL_EV_W 7 +#define EVENT_UDMACH24BSEL_EV_M 0x0000007F +#define EVENT_UDMACH24BSEL_EV_S 0 +#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 + +//***************************************************************************** +// +// Register: EVENT_O_GPT3ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT3ACAPTSEL_EV_W 7 +#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3ACAPTSEL_EV_S 0 +#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT3BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT3BCAPTSEL_EV_W 7 +#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3BCAPTSEL_EV_S 0 +#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_AUXSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +// NONE Always inactive +#define EVENT_AUXSEL0_EV_W 7 +#define EVENT_AUXSEL0_EV_M 0x0000007F +#define EVENT_AUXSEL0_EV_S 0 +#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_AUXSEL0_EV_GPT1B 0x00000013 +#define EVENT_AUXSEL0_EV_GPT1A 0x00000012 +#define EVENT_AUXSEL0_EV_GPT0B 0x00000011 +#define EVENT_AUXSEL0_EV_GPT0A 0x00000010 +#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F +#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E +#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D +#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C +#define EVENT_AUXSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_CM3NMISEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// WDT_NMI Watchdog non maskable interrupt event, controlled +// by WDT:CTL.INTTYPE +#define EVENT_CM3NMISEL0_EV_W 7 +#define EVENT_CM3NMISEL0_EV_M 0x0000007F +#define EVENT_CM3NMISEL0_EV_S 0 +#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 + +//***************************************************************************** +// +// Register: EVENT_O_I2SSTMPSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// NONE Always inactive +#define EVENT_I2SSTMPSEL0_EV_W 7 +#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F +#define EVENT_I2SSTMPSEL0_EV_S 0 +#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_FRZSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// CPU_HALTED CPU halted +// NONE Always inactive +#define EVENT_FRZSEL0_EV_W 7 +#define EVENT_FRZSEL0_EV_M 0x0000007F +#define EVENT_FRZSEL0_EV_S 0 +#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 +#define EVENT_FRZSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_SWEV +// +//***************************************************************************** +// Field: [24] SWEV3 +// +// Writing "1" to this bit when the value is "0" triggers the Software 3 event. +#define EVENT_SWEV_SWEV3 0x01000000 +#define EVENT_SWEV_SWEV3_BITN 24 +#define EVENT_SWEV_SWEV3_M 0x01000000 +#define EVENT_SWEV_SWEV3_S 24 + +// Field: [16] SWEV2 +// +// Writing "1" to this bit when the value is "0" triggers the Software 2 event. +#define EVENT_SWEV_SWEV2 0x00010000 +#define EVENT_SWEV_SWEV2_BITN 16 +#define EVENT_SWEV_SWEV2_M 0x00010000 +#define EVENT_SWEV_SWEV2_S 16 + +// Field: [8] SWEV1 +// +// Writing "1" to this bit when the value is "0" triggers the Software 1 event. +#define EVENT_SWEV_SWEV1 0x00000100 +#define EVENT_SWEV_SWEV1_BITN 8 +#define EVENT_SWEV_SWEV1_M 0x00000100 +#define EVENT_SWEV_SWEV1_S 8 + +// Field: [0] SWEV0 +// +// Writing "1" to this bit when the value is "0" triggers the Software 0 event. +#define EVENT_SWEV_SWEV0 0x00000001 +#define EVENT_SWEV_SWEV0_BITN 0 +#define EVENT_SWEV_SWEV0_M 0x00000001 +#define EVENT_SWEV_SWEV0_S 0 + + +#endif // __EVENT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_fcfg1.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_fcfg1.h new file mode 100644 index 0000000..39899da --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_fcfg1.h @@ -0,0 +1,3028 @@ +/****************************************************************************** +* Filename: hw_fcfg1_h +* Revised: 2017-02-06 19:32:22 +0100 (Mon, 06 Feb 2017) +* Revision: 48408 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_FCFG1_H__ +#define __HW_FCFG1_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// FCFG1 component +// +//***************************************************************************** +// Misc configurations +#define FCFG1_O_MISC_CONF_1 0x000000A0 + +// Internal +#define FCFG1_O_MISC_CONF_2 0x000000A4 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV5 0x000000C4 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV6 0x000000C8 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV10 0x000000CC + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV12 0x000000D0 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV15 0x000000D4 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV30 0x000000D8 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000DC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV6 0x000000E0 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000E4 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV12 0x000000E8 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV15 0x000000EC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV30 0x000000F0 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV5 0x000000F4 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV6 0x000000F8 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV10 0x000000FC + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV12 0x00000100 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV15 0x00000104 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV30 0x00000108 + +// Shadow of EFUSE:DIE_ID_0 +#define FCFG1_O_SHDW_DIE_ID_0 0x00000118 + +// Shadow of EFUSE:DIE_ID_1 +#define FCFG1_O_SHDW_DIE_ID_1 0x0000011C + +// Shadow of EFUSE:DIE_ID_2 +#define FCFG1_O_SHDW_DIE_ID_2 0x00000120 + +// Shadow of EFUSE:DIE_ID_3 +#define FCFG1_O_SHDW_DIE_ID_3 0x00000124 + +// Internal +#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x00000138 + +// Internal +#define FCFG1_O_SHDW_ANA_TRIM 0x0000013C + +#define FCFG1_O_FLASH_NUMBER 0x00000164 + +#define FCFG1_O_FLASH_COORDINATE 0x0000016C + +// Internal +#define FCFG1_O_FLASH_E_P 0x00000170 + +// Internal +#define FCFG1_O_FLASH_C_E_P_R 0x00000174 + +// Internal +#define FCFG1_O_FLASH_P_R_PV 0x00000178 + +// Internal +#define FCFG1_O_FLASH_EH_SEQ 0x0000017C + +// Internal +#define FCFG1_O_FLASH_VHV_E 0x00000180 + +// Internal +#define FCFG1_O_FLASH_PP 0x00000184 + +// Internal +#define FCFG1_O_FLASH_PROG_EP 0x00000188 + +// Internal +#define FCFG1_O_FLASH_ERA_PW 0x0000018C + +// Internal +#define FCFG1_O_FLASH_VHV 0x00000190 + +// Internal +#define FCFG1_O_FLASH_VHV_PV 0x00000194 + +// Internal +#define FCFG1_O_FLASH_V 0x00000198 + +// User Identification. +#define FCFG1_O_USER_ID 0x00000294 + +// Internal +#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 + +// Internal +#define FCFG1_O_ANA2_TRIM 0x000002B4 + +// Internal +#define FCFG1_O_LDO_TRIM 0x000002B8 + +// Internal +#define FCFG1_O_BAT_RC_LDO_TRIM 0x000002BC + +// MAC BLE Address 0 +#define FCFG1_O_MAC_BLE_0 0x000002E8 + +// MAC BLE Address 1 +#define FCFG1_O_MAC_BLE_1 0x000002EC + +// MAC IEEE 802.15.4 Address 0 +#define FCFG1_O_MAC_15_4_0 0x000002F0 + +// MAC IEEE 802.15.4 Address 1 +#define FCFG1_O_MAC_15_4_1 0x000002F4 + +// Internal +#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 + +// Miscellaneous Trim Parameters +#define FCFG1_O_MISC_TRIM 0x0000030C + +// Internal +#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 + +// Internal +#define FCFG1_O_TRIM_CAL_REVISION 0x00000314 + +// IcePick Device Identification +#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 + +// Factory Configuration (FCFG1) Revision +#define FCFG1_O_FCFG1_REVISION 0x0000031C + +// Misc OTP Data +#define FCFG1_O_MISC_OTP_DATA 0x00000320 + +// IO Configuration +#define FCFG1_O_IOCONF 0x00000344 + +// Internal +#define FCFG1_O_CONFIG_IF_ADC 0x0000034C + +// Internal +#define FCFG1_O_CONFIG_OSC_TOP 0x00000350 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND 0x00000354 + +// Internal +#define FCFG1_O_CONFIG_SYNTH 0x00000358 + +// AUX_ADC Gain in Absolute Reference Mode +#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C + +// AUX_ADC Gain in Relative Reference Mode +#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 + +// AUX_ADC Temperature Offsets in Absolute Reference Mode +#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 + +// Internal +#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C + +// Internal +#define FCFG1_O_AMPCOMP_TH1 0x00000370 + +// Internal +#define FCFG1_O_AMPCOMP_TH2 0x00000374 + +// Internal +#define FCFG1_O_AMPCOMP_CTRL1 0x00000378 + +// Internal +#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC 0x00000380 + +// Internal +#define FCFG1_O_VOLT_TRIM 0x00000388 + +// OSC Configuration +#define FCFG1_O_OSC_CONF 0x0000038C + +// Internal +#define FCFG1_O_FREQ_OFFSET 0x00000390 + +// Internal +#define FCFG1_O_CAP_TRIM 0x00000394 + +// Internal +#define FCFG1_O_MISC_OTP_DATA_1 0x00000398 + +// Power Down Current Control 20C +#define FCFG1_O_PWD_CURR_20C 0x0000039C + +// Power Down Current Control 35C +#define FCFG1_O_PWD_CURR_35C 0x000003A0 + +// Power Down Current Control 50C +#define FCFG1_O_PWD_CURR_50C 0x000003A4 + +// Power Down Current Control 65C +#define FCFG1_O_PWD_CURR_65C 0x000003A8 + +// Power Down Current Control 80C +#define FCFG1_O_PWD_CURR_80C 0x000003AC + +// Power Down Current Control 95C +#define FCFG1_O_PWD_CURR_95C 0x000003B0 + +// Power Down Current Control 110C +#define FCFG1_O_PWD_CURR_110C 0x000003B4 + +// Power Down Current Control 125C +#define FCFG1_O_PWD_CURR_125C 0x000003B8 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_CONF_1 +// +//***************************************************************************** +// Field: [7:0] DEVICE_MINOR_REV +// +// HW minor revision number (a value of 0xFF shall be treated equally to 0x00). +// Any test of this field by SW should be implemented as a 'greater or equal' +// comparison as signed integer. +// Value may change without warning. +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_CONF_2 +// +//***************************************************************************** +// Field: [7:0] HPOSC_COMP_P3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV5 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV6 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV10 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV12 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV15 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV30 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV5 +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV6 +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV10 +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV12 +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV15 +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV30 +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV5 +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV5_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV5_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV5_MIN_ALLOWED_RTRIM_S 18 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV6 +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_S 18 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV10 +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_S 18 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV12 +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_S 18 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV15 +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_S 18 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV30 +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_S 18 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_0 +// +//***************************************************************************** +// Field: [31:0] ID_31_0 +// +// Shadow of the DIE_ID_0 register in eFuse row number 3 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_1 +// +//***************************************************************************** +// Field: [31:0] ID_63_32 +// +// Shadow of the DIE_ID_1 register in eFuse row number 4 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_2 +// +//***************************************************************************** +// Field: [31:0] ID_95_64 +// +// Shadow of the DIE_ID_2 register in eFuse row number 5 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_3 +// +//***************************************************************************** +// Field: [31:0] ID_127_96 +// +// Shadow of the DIE_ID_3 register in eFuse row number 6 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM +// +//***************************************************************************** +// Field: [28:27] SET_RCOSC_HF_COARSE_RESISTOR +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_W \ + 2 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_M \ + 0x18000000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_S \ + 27 + +// Field: [26:23] TRIMMAG +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 + +// Field: [22:18] TRIMIREF +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 + +// Field: [17:16] ITRIM_DIG_LDO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 + +// Field: [15:12] VTRIM_DIG +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 + +// Field: [11:8] VTRIM_COARSE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 + +// Field: [7:0] RCOSCHF_CTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_ANA_TRIM +// +//***************************************************************************** +// Field: [26:25] BOD_BANDGAP_TRIM_CNF +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 + +// Field: [24] VDDR_ENABLE_PG1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 + +// Field: [23] VDDR_OK_HYS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 + +// Field: [22:21] IPTAT_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 + +// Field: [20:16] VDDR_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 + +// Field: [15:11] TRIMBOD_INTMODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 + +// Field: [10:6] TRIMBOD_EXTMODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 + +// Field: [5:0] TRIMTEMP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_NUMBER +// +//***************************************************************************** +// Field: [31:0] LOT_NUMBER +// +// Number of the manufacturing lot that produced this unit. +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_COORDINATE +// +//***************************************************************************** +// Field: [31:16] XCOORDINATE +// +// X coordinate of this unit on the wafer. +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 + +// Field: [15:0] YCOORDINATE +// +// Y coordinate of this unit on the wafer. +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_E_P +// +//***************************************************************************** +// Field: [31:24] PSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_PSU_W 8 +#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 +#define FCFG1_FLASH_E_P_PSU_S 24 + +// Field: [23:16] ESU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_ESU_W 8 +#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 +#define FCFG1_FLASH_E_P_ESU_S 16 + +// Field: [15:8] PVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_PVSU_W 8 +#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 +#define FCFG1_FLASH_E_P_PVSU_S 8 + +// Field: [7:0] EVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_EVSU_W 8 +#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF +#define FCFG1_FLASH_E_P_EVSU_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_C_E_P_R +// +//***************************************************************************** +// Field: [31:24] RVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_RVSU_W 8 +#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 +#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 + +// Field: [23:16] PV_ACCESS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 + +// Field: [15:12] A_EXEZ_SETUP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 + +// Field: [11:0] CVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_CVSU_W 12 +#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF +#define FCFG1_FLASH_C_E_P_R_CVSU_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_P_R_PV +// +//***************************************************************************** +// Field: [31:24] PH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PH_W 8 +#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 +#define FCFG1_FLASH_P_R_PV_PH_S 24 + +// Field: [23:16] RH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_RH_W 8 +#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 +#define FCFG1_FLASH_P_R_PV_RH_S 16 + +// Field: [15:8] PVH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PVH_W 8 +#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 +#define FCFG1_FLASH_P_R_PV_PVH_S 8 + +// Field: [7:0] PVH2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PVH2_W 8 +#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF +#define FCFG1_FLASH_P_R_PV_PVH2_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_EH_SEQ +// +//***************************************************************************** +// Field: [31:24] EH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_EH_W 8 +#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 +#define FCFG1_FLASH_EH_SEQ_EH_S 24 + +// Field: [23:16] SEQ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_SEQ_W 8 +#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 +#define FCFG1_FLASH_EH_SEQ_SEQ_S 16 + +// Field: [15:12] VSTAT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 +#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 +#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 + +// Field: [11:0] SM_FREQUENCY +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV_E +// +//***************************************************************************** +// Field: [31:16] VHV_E_START +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 +#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 + +// Field: [15:0] VHV_E_STEP_HIGHT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_PP +// +//***************************************************************************** +// Field: [31:24] PUMP_SU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PP_PUMP_SU_W 8 +#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 +#define FCFG1_FLASH_PP_PUMP_SU_S 24 + +// Field: [15:0] MAX_PP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PP_MAX_PP_W 16 +#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF +#define FCFG1_FLASH_PP_MAX_PP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_PROG_EP +// +//***************************************************************************** +// Field: [31:16] MAX_EP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 +#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 +#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 + +// Field: [15:0] PROGRAM_PW +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_ERA_PW +// +//***************************************************************************** +// Field: [31:0] ERASE_PW +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 +#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF +#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV +// +//***************************************************************************** +// Field: [27:24] TRIM13_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_TRIM13_P_W 4 +#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 +#define FCFG1_FLASH_VHV_TRIM13_P_S 24 + +// Field: [19:16] VHV_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_VHV_P_W 4 +#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 +#define FCFG1_FLASH_VHV_VHV_P_S 16 + +// Field: [11:8] TRIM13_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_TRIM13_E_W 4 +#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 +#define FCFG1_FLASH_VHV_TRIM13_E_S 8 + +// Field: [3:0] VHV_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_VHV_E_W 4 +#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F +#define FCFG1_FLASH_VHV_VHV_E_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV_PV +// +//***************************************************************************** +// Field: [27:24] TRIM13_PV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 + +// Field: [19:16] VHV_PV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 +#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 +#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 + +// Field: [15:8] VCG2P5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 +#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 +#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 + +// Field: [7:0] VINH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VINH_W 8 +#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF +#define FCFG1_FLASH_VHV_PV_VINH_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_V +// +//***************************************************************************** +// Field: [31:24] VSL_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_VSL_P_W 8 +#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 +#define FCFG1_FLASH_V_VSL_P_S 24 + +// Field: [23:16] VWL_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_VWL_P_W 8 +#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 +#define FCFG1_FLASH_V_VWL_P_S 16 + +// Field: [15:8] V_READ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_V_READ_W 8 +#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 +#define FCFG1_FLASH_V_V_READ_S 8 + +//***************************************************************************** +// +// Register: FCFG1_O_USER_ID +// +//***************************************************************************** +// Field: [31:28] PG_REV +// +// Field used to distinguish revisions of the device. +#define FCFG1_USER_ID_PG_REV_W 4 +#define FCFG1_USER_ID_PG_REV_M 0xF0000000 +#define FCFG1_USER_ID_PG_REV_S 28 + +// Field: [27:26] VER +// +// Version number. +// +// 0x0: Bits [25:12] of this register has the stated meaning. +// +// Any other setting indicate a different encoding of these bits. +#define FCFG1_USER_ID_VER_W 2 +#define FCFG1_USER_ID_VER_M 0x0C000000 +#define FCFG1_USER_ID_VER_S 26 + +// Field: [22:19] SEQUENCE +// +// Sequence. +// +// Used to differentiate between marketing/orderable product where other fields +// of USER_ID is the same (temp range, flash size, voltage range etc) +#define FCFG1_USER_ID_SEQUENCE_W 4 +#define FCFG1_USER_ID_SEQUENCE_M 0x00780000 +#define FCFG1_USER_ID_SEQUENCE_S 19 + +// Field: [18:16] PKG +// +// Package type. +// +// 0x0: 4x4mm QFN (RHB) package +// 0x1: 5x5mm QFN (RSM) package +// 0x2: 7x7mm QFN (RGZ) package +// 0x3: Wafer sale package (naked die) +// 0x4: 2.7x2.7mm WCSP (YFV) +// 0x5: 7x7mm QFN package with Wettable Flanks +// +// Other values are reserved for future use. +// Packages available for a specific device are shown in the device datasheet. +#define FCFG1_USER_ID_PKG_W 3 +#define FCFG1_USER_ID_PKG_M 0x00070000 +#define FCFG1_USER_ID_PKG_S 16 + +// Field: [15:12] PROTOCOL +// +// Protocols supported. +// +// 0x1: BLE +// 0x2: RF4CE +// 0x4: Zigbee/6lowpan +// 0x8: Proprietary +// +// More than one protocol can be supported on same device - values above are +// then combined. +#define FCFG1_USER_ID_PROTOCOL_W 4 +#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 +#define FCFG1_USER_ID_PROTOCOL_S 12 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_OTP_DATA3 +// +//***************************************************************************** +// Field: [31:23] EC_STEP_SIZE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 + +// Field: [22] DO_PRECOND +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 + +// Field: [21:18] MAX_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 + +// Field: [17:16] TRIM_1P7 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 + +// Field: [15:8] FLASH_SIZE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 + +// Field: [7:0] WAIT_SYSCODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ANA2_TRIM +// +//***************************************************************************** +// Field: [31] RCOSCHFCTRIMFRACT_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 + +// Field: [30:26] RCOSCHFCTRIMFRACT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 + +// Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 + +// Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 + +// Field: [21:16] NANOAMP_RES_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 6 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F0000 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 16 + +// Field: [11] DITHER_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 +#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_S 11 + +// Field: [10:8] DCDC_IPEAK +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 + +// Field: [7:6] DEAD_TIME_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 + +// Field: [5:3] DCDC_LOW_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 + +// Field: [2:0] DCDC_HIGH_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_LDO_TRIM +// +//***************************************************************************** +// Field: [28:24] VDDR_TRIM_SLEEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 + +// Field: [18:16] GLDO_CURSRC +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 + +// Field: [12:11] ITRIM_DIGLDO_LOAD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 + +// Field: [10:8] ITRIM_UDIGLDO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 + +// Field: [2:0] VTRIM_DELTA +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_BAT_RC_LDO_TRIM +// +//***************************************************************************** +// Field: [27:24] VTRIM_BOD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M 0x0F000000 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_S 24 + +// Field: [19:16] VTRIM_UDIG +// +// Internal. Only to be used through TI provided API. +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M 0x000F0000 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_S 16 + +// Field: [11:8] RCOSCHF_ITUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_M 0x00000F00 +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_S 8 + +// Field: [1:0] MEASUREPER +// +// Internal. Only to be used through TI provided API. +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_W 2 +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_M 0x00000003 +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_BLE_0 +// +//***************************************************************************** +// Field: [31:0] ADDR_0_31 +// +// The first 32-bits of the 64-bit MAC BLE address +#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 +#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_BLE_1 +// +//***************************************************************************** +// Field: [31:0] ADDR_32_63 +// +// The last 32-bits of the 64-bit MAC BLE address +#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 +#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_15_4_0 +// +//***************************************************************************** +// Field: [31:0] ADDR_0_31 +// +// The first 32-bits of the 64-bit MAC 15.4 address +#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 +#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_15_4_1 +// +//***************************************************************************** +// Field: [31:0] ADDR_32_63 +// +// The last 32-bits of the 64-bit MAC 15.4 address +#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 +#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_OTP_DATA4 +// +//***************************************************************************** +// Field: [31] STANDBY_MODE_SEL_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 + +// Field: [30:29] STANDBY_PW_SEL_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 + +// Field: [28] DIS_STANDBY_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 + +// Field: [27] DIS_IDLE_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 + +// Field: [26:24] VIN_AT_X_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 + +// Field: [23] STANDBY_MODE_SEL_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 + +// Field: [22:21] STANDBY_PW_SEL_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 + +// Field: [20] DIS_STANDBY_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 + +// Field: [19] DIS_IDLE_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 + +// Field: [18:16] VIN_AT_X_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 + +// Field: [15] STANDBY_MODE_SEL_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 + +// Field: [14:13] STANDBY_PW_SEL_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 + +// Field: [12] DIS_STANDBY_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 + +// Field: [11] DIS_IDLE_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 + +// Field: [10:8] VIN_AT_X_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 + +// Field: [7] STANDBY_MODE_SEL_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 + +// Field: [6:5] STANDBY_PW_SEL_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 + +// Field: [4] DIS_STANDBY_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 + +// Field: [3] DIS_IDLE_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 + +// Field: [2:0] VIN_AT_X_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_TRIM +// +//***************************************************************************** +// Field: [7:0] TEMPVSLOPE +// +// Signed byte value representing the TEMP slope with battery voltage, in +// degrees C / V, with four fractional bits. +#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 +#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF +#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_RCOSC_HF_TEMPCOMP +// +//***************************************************************************** +// Field: [31:24] FINE_RESISTOR +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 + +// Field: [23:16] CTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 + +// Field: [15:8] CTRIMFRACT_QUAD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 + +// Field: [7:0] CTRIMFRACT_SLOPE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_TRIM_CAL_REVISION +// +//***************************************************************************** +// Field: [31:16] FT1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_TRIM_CAL_REVISION_FT1_W 16 +#define FCFG1_TRIM_CAL_REVISION_FT1_M 0xFFFF0000 +#define FCFG1_TRIM_CAL_REVISION_FT1_S 16 + +// Field: [15:0] MP1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_TRIM_CAL_REVISION_MP1_W 16 +#define FCFG1_TRIM_CAL_REVISION_MP1_M 0x0000FFFF +#define FCFG1_TRIM_CAL_REVISION_MP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ICEPICK_DEVICE_ID +// +//***************************************************************************** +// Field: [31:28] PG_REV +// +// Field used to distinguish revisions of the device. +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 + +// Field: [27:12] WAFER_ID +// +// Field used to identify silicon die. +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 + +// Field: [11:0] MANUFACTURER_ID +// +// Manufacturer code. +// +// 0x02F: Texas Instruments +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FCFG1_REVISION +// +//***************************************************************************** +// Field: [31:0] REV +// +// The revision number of the FCFG1 layout. This value will be read by +// application SW in order to determine which FCFG1 parameters that have valid +// values. This revision number must be incremented by 1 before any devices are +// to be produced if the FCFG1 layout has changed since the previous production +// of devices. +// Value migth change without warning. +#define FCFG1_FCFG1_REVISION_REV_W 32 +#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF +#define FCFG1_FCFG1_REVISION_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_OTP_DATA +// +//***************************************************************************** +// Field: [31:28] RCOSC_HF_ITUNE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 + +// Field: [27:20] RCOSC_HF_CRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 + +// Field: [19:15] PER_M +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_PER_M_W 5 +#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 +#define FCFG1_MISC_OTP_DATA_PER_M_S 15 + +// Field: [14:12] PER_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_PER_E_W 3 +#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 +#define FCFG1_MISC_OTP_DATA_PER_E_S 12 + +// Field: [11:8] MIN_ALLOWED_RTRIM_DIV5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_W 4 +#define FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_M 0x00000F00 +#define FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_S 8 + +// Field: [7:0] TEST_PROGRAM_REV +// +// The revision of the test program used in the production process when FCFG1 +// was programmed. +// Value migth change without warning. +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_W 8 +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_M 0x000000FF +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_IOCONF +// +//***************************************************************************** +// Field: [6:0] GPIO_CNT +// +// Number of available DIOs. +#define FCFG1_IOCONF_GPIO_CNT_W 7 +#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F +#define FCFG1_IOCONF_GPIO_CNT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_IF_ADC +// +//***************************************************************************** +// Field: [31:28] FF2ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 + +// Field: [27:24] FF3ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 + +// Field: [23:20] INT3ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 + +// Field: [19:16] FF1ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 + +// Field: [15:14] AAFCAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 + +// Field: [13:10] INT2ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 + +// Field: [9:5] IFDIGLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 + +// Field: [4:0] IFANALDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_OSC_TOP +// +//***************************************************************************** +// Field: [29:26] XOSC_HF_ROW_Q12 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 + +// Field: [25:10] XOSC_HF_COLUMN_Q12 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 + +// Field: [9:2] RCOSCLF_CTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 + +// Field: [1:0] RCOSCLF_RTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_S 14 + +// Field: [13] PATRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N 0x00002000 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_BITN 13 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_M 0x00002000 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_S 13 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH +// +//***************************************************************************** +// Field: [28] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization only on +// cc13x0. +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_ABS_GAIN +// +//***************************************************************************** +// Field: [15:0] SOC_ADC_ABS_GAIN_TEMP1 +// +// SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated +// in production test.. +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_REL_GAIN +// +//***************************************************************************** +// Field: [15:0] SOC_ADC_REL_GAIN_TEMP1 +// +// SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated +// in production test.. +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_OFFSET_INT +// +//***************************************************************************** +// Field: [23:16] SOC_ADC_REL_OFFSET_TEMP1 +// +// SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed +// 8-bit number. Calculated in production test.. +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 + +// Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1 +// +// SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed +// 8-bit number. Calculated in production test.. +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT +// +//***************************************************************************** +// Field: [5:0] SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_W \ + 6 +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_M \ + 0x0000003F +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S \ + 0 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_TH1 +// +//***************************************************************************** +// Field: [23:18] HPMRAMP3_LTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 + +// Field: [15:10] HPMRAMP3_HTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 + +// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 + +// Field: [5:0] HPMRAMP1_TH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_TH2 +// +//***************************************************************************** +// Field: [31:26] LPMUPDATE_LTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 + +// Field: [23:18] LPMUPDATE_HTM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 + +// Field: [15:10] ADC_COMP_AMPTH_LPM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 + +// Field: [7:2] ADC_COMP_AMPTH_HPM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_CTRL1 +// +//***************************************************************************** +// Field: [30] AMPCOMP_REQ_MODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 + +// Field: [23:20] IBIAS_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 + +// Field: [19:16] IBIAS_INIT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 + +// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 + +// Field: [7:4] CAP_STEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 + +// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ANABYPASS_VALUE2 +// +//***************************************************************************** +// Field: [13:0] XOSC_HF_IBIASTHERM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC +// +//***************************************************************************** +// Field: [21:18] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_S 18 + +// Field: [17] RSSITRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N 0x00020000 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_BITN 17 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_M 0x00020000 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_S 17 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_VOLT_TRIM +// +//***************************************************************************** +// Field: [28:24] VDDR_TRIM_HH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 + +// Field: [20:16] VDDR_TRIM_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 + +// Field: [12:8] VDDR_TRIM_SLEEP_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 + +// Field: [4:0] TRIMBOD_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 +#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F +#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_OSC_CONF +// +//***************************************************************************** +// Field: [29] ADC_SH_VBUF_EN +// +// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 + +// Field: [28] ADC_SH_MODE_EN +// +// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 + +// Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM +// +// Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 + +// Field: [26:25] XOSCLF_REGULATOR_TRIM +// +// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 + +// Field: [24:21] XOSCLF_CMIRRWR_RATIO +// +// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 + +// Field: [20:19] XOSC_HF_FAST_START +// +// Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 + +// Field: [18] XOSC_OPTION +// +// 0: XOSC_HF unavailable (may not be bonded out) +// 1: XOSC_HF available (default) +#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 +#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_S 18 + +// Field: [17] HPOSC_OPTION +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 +#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 + +// Field: [16] HPOSC_BIAS_HOLD_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 + +// Field: [15:12] HPOSC_CURRMIRR_RATIO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 + +// Field: [11:8] HPOSC_BIAS_RES_SET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 + +// Field: [7] HPOSC_FILTER_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 + +// Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 + +// Field: [2:1] HPOSC_SERIES_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 + +// Field: [0] HPOSC_DIV3_BYPASS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FREQ_OFFSET +// +//***************************************************************************** +// Field: [31:16] HPOSC_COMP_P0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 + +// Field: [15:8] HPOSC_COMP_P1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 + +// Field: [7:0] HPOSC_COMP_P2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CAP_TRIM +// +//***************************************************************************** +// Field: [31:16] FLUX_CAP_0P28_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_W 16 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_M 0xFFFF0000 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_S 16 + +// Field: [15:0] FLUX_CAP_0P4_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_W 16 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_M 0x0000FFFF +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_OTP_DATA_1 +// +//***************************************************************************** +// Field: [28:27] PEAK_DET_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 + +// Field: [26:24] HP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 + +// Field: [23:22] LP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 + +// Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 + +// Field: [19:10] HPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 + +// Field: [9:4] LPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 + +// Field: [3:0] IDAC_STEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_20C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_20C_BASELINE_W 8 +#define FCFG1_PWD_CURR_20C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_20C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_35C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_35C_BASELINE_W 8 +#define FCFG1_PWD_CURR_35C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_35C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_50C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_50C_BASELINE_W 8 +#define FCFG1_PWD_CURR_50C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_50C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_65C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_65C_BASELINE_W 8 +#define FCFG1_PWD_CURR_65C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_65C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_80C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_80C_BASELINE_W 8 +#define FCFG1_PWD_CURR_80C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_80C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_95C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_95C_BASELINE_W 8 +#define FCFG1_PWD_CURR_95C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_95C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_110C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_110C_BASELINE_W 8 +#define FCFG1_PWD_CURR_110C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_110C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_125C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_125C_BASELINE_W 8 +#define FCFG1_PWD_CURR_125C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_125C_BASELINE_S 0 + + +#endif // __FCFG1__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_flash.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_flash.h new file mode 100644 index 0000000..03ce768 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_flash.h @@ -0,0 +1,3475 @@ +/****************************************************************************** +* Filename: hw_flash_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// FLASH component +// +//***************************************************************************** +// FMC and Efuse Status +#define FLASH_O_STAT 0x0000001C + +// Internal +#define FLASH_O_CFG 0x00000024 + +// Internal +#define FLASH_O_SYSCODE_START 0x00000028 + +// Internal +#define FLASH_O_FLASH_SIZE 0x0000002C + +// Internal +#define FLASH_O_FWLOCK 0x0000003C + +// Internal +#define FLASH_O_FWFLAG 0x00000040 + +// Internal +#define FLASH_O_EFUSE 0x00001000 + +// Internal +#define FLASH_O_EFUSEADDR 0x00001004 + +// Internal +#define FLASH_O_DATAUPPER 0x00001008 + +// Internal +#define FLASH_O_DATALOWER 0x0000100C + +// Internal +#define FLASH_O_EFUSECFG 0x00001010 + +// Internal +#define FLASH_O_EFUSESTAT 0x00001014 + +// Internal +#define FLASH_O_ACC 0x00001018 + +// Internal +#define FLASH_O_BOUNDARY 0x0000101C + +// Internal +#define FLASH_O_EFUSEFLAG 0x00001020 + +// Internal +#define FLASH_O_EFUSEKEY 0x00001024 + +// Internal +#define FLASH_O_EFUSERELEASE 0x00001028 + +// Internal +#define FLASH_O_EFUSEPINS 0x0000102C + +// Internal +#define FLASH_O_EFUSECRA 0x00001030 + +// Internal +#define FLASH_O_EFUSEREAD 0x00001034 + +// Internal +#define FLASH_O_EFUSEPROGRAM 0x00001038 + +// Internal +#define FLASH_O_EFUSEERROR 0x0000103C + +// Internal +#define FLASH_O_SINGLEBIT 0x00001040 + +// Internal +#define FLASH_O_TWOBIT 0x00001044 + +// Internal +#define FLASH_O_SELFTESTCYC 0x00001048 + +// Internal +#define FLASH_O_SELFTESTSIGN 0x0000104C + +// Internal +#define FLASH_O_FRDCTL 0x00002000 + +// Internal +#define FLASH_O_FSPRD 0x00002004 + +// Internal +#define FLASH_O_FEDACCTL1 0x00002008 + +// Internal +#define FLASH_O_FEDACSTAT 0x0000201C + +// Internal +#define FLASH_O_FBPROT 0x00002030 + +// Internal +#define FLASH_O_FBSE 0x00002034 + +// Internal +#define FLASH_O_FBBUSY 0x00002038 + +// Internal +#define FLASH_O_FBAC 0x0000203C + +// Internal +#define FLASH_O_FBFALLBACK 0x00002040 + +// Internal +#define FLASH_O_FBPRDY 0x00002044 + +// Internal +#define FLASH_O_FPAC1 0x00002048 + +// Internal +#define FLASH_O_FPAC2 0x0000204C + +// Internal +#define FLASH_O_FMAC 0x00002050 + +// Internal +#define FLASH_O_FMSTAT 0x00002054 + +// Internal +#define FLASH_O_FLOCK 0x00002064 + +// Internal +#define FLASH_O_FVREADCT 0x00002080 + +// Internal +#define FLASH_O_FVHVCT1 0x00002084 + +// Internal +#define FLASH_O_FVHVCT2 0x00002088 + +// Internal +#define FLASH_O_FVHVCT3 0x0000208C + +// Internal +#define FLASH_O_FVNVCT 0x00002090 + +// Internal +#define FLASH_O_FVSLP 0x00002094 + +// Internal +#define FLASH_O_FVWLCT 0x00002098 + +// Internal +#define FLASH_O_FEFUSECTL 0x0000209C + +// Internal +#define FLASH_O_FEFUSESTAT 0x000020A0 + +// Internal +#define FLASH_O_FEFUSEDATA 0x000020A4 + +// Internal +#define FLASH_O_FSEQPMP 0x000020A8 + +// Internal +#define FLASH_O_FBSTROBES 0x00002100 + +// Internal +#define FLASH_O_FPSTROBES 0x00002104 + +// Internal +#define FLASH_O_FBMODE 0x00002108 + +// Internal +#define FLASH_O_FTCR 0x0000210C + +// Internal +#define FLASH_O_FADDR 0x00002110 + +// Internal +#define FLASH_O_FTCTL 0x0000211C + +// Internal +#define FLASH_O_FWPWRITE0 0x00002120 + +// Internal +#define FLASH_O_FWPWRITE1 0x00002124 + +// Internal +#define FLASH_O_FWPWRITE2 0x00002128 + +// Internal +#define FLASH_O_FWPWRITE3 0x0000212C + +// Internal +#define FLASH_O_FWPWRITE4 0x00002130 + +// Internal +#define FLASH_O_FWPWRITE5 0x00002134 + +// Internal +#define FLASH_O_FWPWRITE6 0x00002138 + +// Internal +#define FLASH_O_FWPWRITE7 0x0000213C + +// Internal +#define FLASH_O_FWPWRITE_ECC 0x00002140 + +// Internal +#define FLASH_O_FSWSTAT 0x00002144 + +// Internal +#define FLASH_O_FSM_GLBCTL 0x00002200 + +// Internal +#define FLASH_O_FSM_STATE 0x00002204 + +// Internal +#define FLASH_O_FSM_STAT 0x00002208 + +// Internal +#define FLASH_O_FSM_CMD 0x0000220C + +// Internal +#define FLASH_O_FSM_PE_OSU 0x00002210 + +// Internal +#define FLASH_O_FSM_VSTAT 0x00002214 + +// Internal +#define FLASH_O_FSM_PE_VSU 0x00002218 + +// Internal +#define FLASH_O_FSM_CMP_VSU 0x0000221C + +// Internal +#define FLASH_O_FSM_EX_VAL 0x00002220 + +// Internal +#define FLASH_O_FSM_RD_H 0x00002224 + +// Internal +#define FLASH_O_FSM_P_OH 0x00002228 + +// Internal +#define FLASH_O_FSM_ERA_OH 0x0000222C + +// Internal +#define FLASH_O_FSM_SAV_PPUL 0x00002230 + +// Internal +#define FLASH_O_FSM_PE_VH 0x00002234 + +// Internal +#define FLASH_O_FSM_PRG_PW 0x00002240 + +// Internal +#define FLASH_O_FSM_ERA_PW 0x00002244 + +// Internal +#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254 + +// Internal +#define FLASH_O_FSM_TIMER 0x00002258 + +// Internal +#define FLASH_O_FSM_MODE 0x0000225C + +// Internal +#define FLASH_O_FSM_PGM 0x00002260 + +// Internal +#define FLASH_O_FSM_ERA 0x00002264 + +// Internal +#define FLASH_O_FSM_PRG_PUL 0x00002268 + +// Internal +#define FLASH_O_FSM_ERA_PUL 0x0000226C + +// Internal +#define FLASH_O_FSM_STEP_SIZE 0x00002270 + +// Internal +#define FLASH_O_FSM_PUL_CNTR 0x00002274 + +// Internal +#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 + +// Internal +#define FLASH_O_FSM_ST_MACHINE 0x0000227C + +// Internal +#define FLASH_O_FSM_FLES 0x00002280 + +// Internal +#define FLASH_O_FSM_WR_ENA 0x00002288 + +// Internal +#define FLASH_O_FSM_ACC_PP 0x0000228C + +// Internal +#define FLASH_O_FSM_ACC_EP 0x00002290 + +// Internal +#define FLASH_O_FSM_ADDR 0x000022A0 + +// Internal +#define FLASH_O_FSM_SECTOR 0x000022A4 + +// Internal +#define FLASH_O_FMC_REV_ID 0x000022A8 + +// Internal +#define FLASH_O_FSM_ERR_ADDR 0x000022AC + +// Internal +#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0 + +// Internal +#define FLASH_O_FSM_EXECUTE 0x000022B4 + +// Internal +#define FLASH_O_FSM_SECTOR1 0x000022C0 + +// Internal +#define FLASH_O_FSM_SECTOR2 0x000022C4 + +// Internal +#define FLASH_O_FSM_BSLE0 0x000022E0 + +// Internal +#define FLASH_O_FSM_BSLE1 0x000022E4 + +// Internal +#define FLASH_O_FSM_BSLP0 0x000022F0 + +// Internal +#define FLASH_O_FSM_BSLP1 0x000022F4 + +// Internal +#define FLASH_O_FCFG_BANK 0x00002400 + +// Internal +#define FLASH_O_FCFG_WRAPPER 0x00002404 + +// Internal +#define FLASH_O_FCFG_BNK_TYPE 0x00002408 + +// Internal +#define FLASH_O_FCFG_B0_START 0x00002410 + +// Internal +#define FLASH_O_FCFG_B1_START 0x00002414 + +// Internal +#define FLASH_O_FCFG_B2_START 0x00002418 + +// Internal +#define FLASH_O_FCFG_B3_START 0x0000241C + +// Internal +#define FLASH_O_FCFG_B4_START 0x00002420 + +// Internal +#define FLASH_O_FCFG_B5_START 0x00002424 + +// Internal +#define FLASH_O_FCFG_B6_START 0x00002428 + +// Internal +#define FLASH_O_FCFG_B7_START 0x0000242C + +// Internal +#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 + +//***************************************************************************** +// +// Register: FLASH_O_STAT +// +//***************************************************************************** +// Field: [15] EFUSE_BLANK +// +// Efuse scanning detected if fuse ROM is blank: +// 0 : Not blank +// 1 : Blank +#define FLASH_STAT_EFUSE_BLANK 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_BITN 15 +#define FLASH_STAT_EFUSE_BLANK_M 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_S 15 + +// Field: [14] EFUSE_TIMEOUT +// +// Efuse scanning resulted in timeout error. +// 0 : No Timeout error +// 1 : Timeout Error +#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14 +#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_S 14 + +// Field: [13] EFUSE_CRC_ERROR +// +// Efuse scanning resulted in scan chain CRC error. +// 0 : No CRC error +// 1 : CRC Error +#define FLASH_STAT_EFUSE_CRC_ERROR 0x00002000 +#define FLASH_STAT_EFUSE_CRC_ERROR_BITN 13 +#define FLASH_STAT_EFUSE_CRC_ERROR_M 0x00002000 +#define FLASH_STAT_EFUSE_CRC_ERROR_S 13 + +// Field: [12:8] EFUSE_ERRCODE +// +// Same as EFUSEERROR.CODE +#define FLASH_STAT_EFUSE_ERRCODE_W 5 +#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00 +#define FLASH_STAT_EFUSE_ERRCODE_S 8 + +// Field: [2] SAMHOLD_DIS +// +// Status indicator of flash sample and hold sequencing logic. This bit will go +// to 1 some delay after CFG.DIS_IDLE is set to 1. +// 0: Not disabled +// 1: Sample and hold disabled and stable +#define FLASH_STAT_SAMHOLD_DIS 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_BITN 2 +#define FLASH_STAT_SAMHOLD_DIS_M 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_S 2 + +// Field: [1] BUSY +// +// Fast version of the FMC FMSTAT.BUSY bit. +// This flag is valid immediately after the operation setting it (FMSTAT.BUSY +// is delayed some cycles) +// 0 : Not busy +// 1 : Busy +#define FLASH_STAT_BUSY 0x00000002 +#define FLASH_STAT_BUSY_BITN 1 +#define FLASH_STAT_BUSY_M 0x00000002 +#define FLASH_STAT_BUSY_S 1 + +// Field: [0] POWER_MODE +// +// Power state of the flash sub-system. +// 0 : Active +// 1 : Low power +#define FLASH_STAT_POWER_MODE 0x00000001 +#define FLASH_STAT_POWER_MODE_BITN 0 +#define FLASH_STAT_POWER_MODE_M 0x00000001 +#define FLASH_STAT_POWER_MODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_CFG +// +//***************************************************************************** +// Field: [8] STANDBY_MODE_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8 +#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_S 8 + +// Field: [7:6] STANDBY_PW_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_STANDBY_PW_SEL_W 2 +#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 +#define FLASH_CFG_STANDBY_PW_SEL_S 6 + +// Field: [5] DIS_EFUSECLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_EFUSECLK 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_BITN 5 +#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_S 5 + +// Field: [4] DIS_READACCESS +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_READACCESS 0x00000010 +#define FLASH_CFG_DIS_READACCESS_BITN 4 +#define FLASH_CFG_DIS_READACCESS_M 0x00000010 +#define FLASH_CFG_DIS_READACCESS_S 4 + +// Field: [3] ENABLE_SWINTF +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_ENABLE_SWINTF 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_BITN 3 +#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_S 3 + +// Field: [1] DIS_STANDBY +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_STANDBY 0x00000002 +#define FLASH_CFG_DIS_STANDBY_BITN 1 +#define FLASH_CFG_DIS_STANDBY_M 0x00000002 +#define FLASH_CFG_DIS_STANDBY_S 1 + +// Field: [0] DIS_IDLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_IDLE 0x00000001 +#define FLASH_CFG_DIS_IDLE_BITN 0 +#define FLASH_CFG_DIS_IDLE_M 0x00000001 +#define FLASH_CFG_DIS_IDLE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SYSCODE_START +// +//***************************************************************************** +// Field: [4:0] SYSCODE_START +// +// Internal. Only to be used through TI provided API. +#define FLASH_SYSCODE_START_SYSCODE_START_W 5 +#define FLASH_SYSCODE_START_SYSCODE_START_M 0x0000001F +#define FLASH_SYSCODE_START_SYSCODE_START_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FLASH_SIZE +// +//***************************************************************************** +// Field: [7:0] SECTORS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FLASH_SIZE_SECTORS_W 8 +#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF +#define FLASH_FLASH_SIZE_SECTORS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWLOCK +// +//***************************************************************************** +// Field: [2:0] FWLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWLOCK_FWLOCK_W 3 +#define FLASH_FWLOCK_FWLOCK_M 0x00000007 +#define FLASH_FWLOCK_FWLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWFLAG +// +//***************************************************************************** +// Field: [2:0] FWFLAG +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWFLAG_FWFLAG_W 3 +#define FLASH_FWFLAG_FWFLAG_M 0x00000007 +#define FLASH_FWFLAG_FWFLAG_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSE +// +//***************************************************************************** +// Field: [28:24] INSTRUCTION +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSE_INSTRUCTION_W 5 +#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000 +#define FLASH_EFUSE_INSTRUCTION_S 24 + +// Field: [15:0] DUMPWORD +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSE_DUMPWORD_W 16 +#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF +#define FLASH_EFUSE_DUMPWORD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEADDR +// +//***************************************************************************** +// Field: [15:11] BLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEADDR_BLOCK_W 5 +#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800 +#define FLASH_EFUSEADDR_BLOCK_S 11 + +// Field: [10:0] ROW +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEADDR_ROW_W 11 +#define FLASH_EFUSEADDR_ROW_M 0x000007FF +#define FLASH_EFUSEADDR_ROW_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_DATAUPPER +// +//***************************************************************************** +// Field: [7:3] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_SPARE_W 5 +#define FLASH_DATAUPPER_SPARE_M 0x000000F8 +#define FLASH_DATAUPPER_SPARE_S 3 + +// Field: [2] P +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_P 0x00000004 +#define FLASH_DATAUPPER_P_BITN 2 +#define FLASH_DATAUPPER_P_M 0x00000004 +#define FLASH_DATAUPPER_P_S 2 + +// Field: [1] R +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_R 0x00000002 +#define FLASH_DATAUPPER_R_BITN 1 +#define FLASH_DATAUPPER_R_M 0x00000002 +#define FLASH_DATAUPPER_R_S 1 + +// Field: [0] EEN +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_EEN 0x00000001 +#define FLASH_DATAUPPER_EEN_BITN 0 +#define FLASH_DATAUPPER_EEN_M 0x00000001 +#define FLASH_DATAUPPER_EEN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_DATALOWER +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATALOWER_DATA_W 32 +#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF +#define FLASH_DATALOWER_DATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSECFG +// +//***************************************************************************** +// Field: [8] IDLEGATING +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_IDLEGATING 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_BITN 8 +#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_S 8 + +// Field: [4:3] SLAVEPOWER +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_SLAVEPOWER_W 2 +#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018 +#define FLASH_EFUSECFG_SLAVEPOWER_S 3 + +// Field: [0] GATING +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_GATING 0x00000001 +#define FLASH_EFUSECFG_GATING_BITN 0 +#define FLASH_EFUSECFG_GATING_M 0x00000001 +#define FLASH_EFUSECFG_GATING_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSESTAT +// +//***************************************************************************** +// Field: [0] RESETDONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSESTAT_RESETDONE 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_BITN 0 +#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_ACC +// +//***************************************************************************** +// Field: [23:0] ACCUMULATOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_ACC_ACCUMULATOR_W 24 +#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF +#define FLASH_ACC_ACCUMULATOR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_BOUNDARY +// +//***************************************************************************** +// Field: [23] DISROW0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_DISROW0 0x00800000 +#define FLASH_BOUNDARY_DISROW0_BITN 23 +#define FLASH_BOUNDARY_DISROW0_M 0x00800000 +#define FLASH_BOUNDARY_DISROW0_S 23 + +// Field: [22] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SPARE 0x00400000 +#define FLASH_BOUNDARY_SPARE_BITN 22 +#define FLASH_BOUNDARY_SPARE_M 0x00400000 +#define FLASH_BOUNDARY_SPARE_S 22 + +// Field: [21] EFC_SELF_TEST_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21 + +// Field: [20] EFC_INSTRUCTION_INFO +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20 + +// Field: [19] EFC_INSTRUCTION_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19 + +// Field: [18] EFC_AUTOLOAD_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18 + +// Field: [17:14] OUTPUTENABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_OUTPUTENABLE_W 4 +#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000 +#define FLASH_BOUNDARY_OUTPUTENABLE_S 14 + +// Field: [13] SYS_ECC_SELF_TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13 + +// Field: [12] SYS_ECC_OVERRIDE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12 + +// Field: [11] EFC_FDI +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_FDI 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_BITN 11 +#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_S 11 + +// Field: [10] SYS_DIEID_AUTOLOAD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10 + +// Field: [9:8] SYS_REPAIR_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8 + +// Field: [7:4] SYS_WS_READ_STATES +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4 + +// Field: [3:0] INPUTENABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_INPUTENABLE_W 4 +#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F +#define FLASH_BOUNDARY_INPUTENABLE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEFLAG +// +//***************************************************************************** +// Field: [0] KEY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEFLAG_KEY 0x00000001 +#define FLASH_EFUSEFLAG_KEY_BITN 0 +#define FLASH_EFUSEFLAG_KEY_M 0x00000001 +#define FLASH_EFUSEFLAG_KEY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEKEY +// +//***************************************************************************** +// Field: [31:0] CODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEKEY_CODE_W 32 +#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF +#define FLASH_EFUSEKEY_CODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSERELEASE +// +//***************************************************************************** +// Field: [31:25] ODPYEAR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPYEAR_W 7 +#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000 +#define FLASH_EFUSERELEASE_ODPYEAR_S 25 + +// Field: [24:21] ODPMONTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPMONTH_W 4 +#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000 +#define FLASH_EFUSERELEASE_ODPMONTH_S 21 + +// Field: [20:16] ODPDAY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPDAY_W 5 +#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000 +#define FLASH_EFUSERELEASE_ODPDAY_S 16 + +// Field: [15:9] EFUSEYEAR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7 +#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00 +#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9 + +// Field: [8:5] EFUSEMONTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4 +#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0 +#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5 + +// Field: [4:0] EFUSEDAY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEDAY_W 5 +#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F +#define FLASH_EFUSERELEASE_EFUSEDAY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEPINS +// +//***************************************************************************** +// Field: [15] EFC_SELF_TEST_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15 + +// Field: [14] EFC_SELF_TEST_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14 + +// Field: [13] SYS_ECC_SELF_TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13 + +// Field: [12] EFC_INSTRUCTION_INFO +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12 + +// Field: [11] EFC_INSTRUCTION_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11 + +// Field: [10] EFC_AUTOLOAD_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10 + +// Field: [9] SYS_ECC_OVERRIDE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9 + +// Field: [8] EFC_READY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_READY 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_BITN 8 +#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_S 8 + +// Field: [7] EFC_FCLRZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7 +#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7 + +// Field: [6] SYS_DIEID_AUTOLOAD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6 + +// Field: [5:4] SYS_REPAIR_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4 + +// Field: [3:0] SYS_WS_READ_STATES +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4 +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSECRA +// +//***************************************************************************** +// Field: [5:0] DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECRA_DATA_W 6 +#define FLASH_EFUSECRA_DATA_M 0x0000003F +#define FLASH_EFUSECRA_DATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEREAD +// +//***************************************************************************** +// Field: [9:8] DATABIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_DATABIT_W 2 +#define FLASH_EFUSEREAD_DATABIT_M 0x00000300 +#define FLASH_EFUSEREAD_DATABIT_S 8 + +// Field: [7:4] READCLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_READCLOCK_W 4 +#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0 +#define FLASH_EFUSEREAD_READCLOCK_S 4 + +// Field: [3] DEBUG +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_DEBUG 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_BITN 3 +#define FLASH_EFUSEREAD_DEBUG_M 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_S 3 + +// Field: [2] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_SPARE 0x00000004 +#define FLASH_EFUSEREAD_SPARE_BITN 2 +#define FLASH_EFUSEREAD_SPARE_M 0x00000004 +#define FLASH_EFUSEREAD_SPARE_S 2 + +// Field: [1:0] MARGIN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_MARGIN_W 2 +#define FLASH_EFUSEREAD_MARGIN_M 0x00000003 +#define FLASH_EFUSEREAD_MARGIN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEPROGRAM +// +//***************************************************************************** +// Field: [30] COMPAREDISABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30 + +// Field: [29:14] CLOCKSTALL +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14 + +// Field: [13] VPPTOVDD +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13 + +// Field: [12:9] ITERATIONS +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4 +#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00 +#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9 + +// Field: [8:0] WRITECLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9 +#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF +#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEERROR +// +//***************************************************************************** +// Field: [5] DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEERROR_DONE 0x00000020 +#define FLASH_EFUSEERROR_DONE_BITN 5 +#define FLASH_EFUSEERROR_DONE_M 0x00000020 +#define FLASH_EFUSEERROR_DONE_S 5 + +// Field: [4:0] CODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEERROR_CODE_W 5 +#define FLASH_EFUSEERROR_CODE_M 0x0000001F +#define FLASH_EFUSEERROR_CODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SINGLEBIT +// +//***************************************************************************** +// Field: [31:1] FROMN +// +// Internal. Only to be used through TI provided API. +#define FLASH_SINGLEBIT_FROMN_W 31 +#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE +#define FLASH_SINGLEBIT_FROMN_S 1 + +// Field: [0] FROM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_SINGLEBIT_FROM0 0x00000001 +#define FLASH_SINGLEBIT_FROM0_BITN 0 +#define FLASH_SINGLEBIT_FROM0_M 0x00000001 +#define FLASH_SINGLEBIT_FROM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_TWOBIT +// +//***************************************************************************** +// Field: [31:1] FROMN +// +// Internal. Only to be used through TI provided API. +#define FLASH_TWOBIT_FROMN_W 31 +#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE +#define FLASH_TWOBIT_FROMN_S 1 + +// Field: [0] FROM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_TWOBIT_FROM0 0x00000001 +#define FLASH_TWOBIT_FROM0_BITN 0 +#define FLASH_TWOBIT_FROM0_M 0x00000001 +#define FLASH_TWOBIT_FROM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SELFTESTCYC +// +//***************************************************************************** +// Field: [31:0] CYCLES +// +// Internal. Only to be used through TI provided API. +#define FLASH_SELFTESTCYC_CYCLES_W 32 +#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF +#define FLASH_SELFTESTCYC_CYCLES_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SELFTESTSIGN +// +//***************************************************************************** +// Field: [31:0] SIGNATURE +// +// Internal. Only to be used through TI provided API. +#define FLASH_SELFTESTSIGN_SIGNATURE_W 32 +#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF +#define FLASH_SELFTESTSIGN_SIGNATURE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FRDCTL +// +//***************************************************************************** +// Field: [11:8] RWAIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FRDCTL_RWAIT_W 4 +#define FLASH_FRDCTL_RWAIT_M 0x00000F00 +#define FLASH_FRDCTL_RWAIT_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSPRD +// +//***************************************************************************** +// Field: [15:8] RMBSEM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RMBSEM_W 8 +#define FLASH_FSPRD_RMBSEM_M 0x0000FF00 +#define FLASH_FSPRD_RMBSEM_S 8 + +// Field: [1] RM1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RM1 0x00000002 +#define FLASH_FSPRD_RM1_BITN 1 +#define FLASH_FSPRD_RM1_M 0x00000002 +#define FLASH_FSPRD_RM1_S 1 + +// Field: [0] RM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RM0 0x00000001 +#define FLASH_FSPRD_RM0_BITN 0 +#define FLASH_FSPRD_RM0_M 0x00000001 +#define FLASH_FSPRD_RM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEDACCTL1 +// +//***************************************************************************** +// Field: [24] SUSP_IGNR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24 +#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_S 24 + +//***************************************************************************** +// +// Register: FLASH_O_FEDACSTAT +// +//***************************************************************************** +// Field: [25] RVF_INT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACSTAT_RVF_INT 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_BITN 25 +#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_S 25 + +// Field: [24] FSM_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACSTAT_FSM_DONE 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_BITN 24 +#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_S 24 + +//***************************************************************************** +// +// Register: FLASH_O_FBPROT +// +//***************************************************************************** +// Field: [0] PROTL1DIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPROT_PROTL1DIS 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_BITN 0 +#define FLASH_FBPROT_PROTL1DIS_M 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBSE +// +//***************************************************************************** +// Field: [15:0] BSE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSE_BSE_W 16 +#define FLASH_FBSE_BSE_M 0x0000FFFF +#define FLASH_FBSE_BSE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBBUSY +// +//***************************************************************************** +// Field: [7:0] BUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBBUSY_BUSY_W 8 +#define FLASH_FBBUSY_BUSY_M 0x000000FF +#define FLASH_FBBUSY_BUSY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBAC +// +//***************************************************************************** +// Field: [16] OTPPROTDIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_OTPPROTDIS 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_BITN 16 +#define FLASH_FBAC_OTPPROTDIS_M 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_S 16 + +// Field: [15:8] BAGP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_BAGP_W 8 +#define FLASH_FBAC_BAGP_M 0x0000FF00 +#define FLASH_FBAC_BAGP_S 8 + +// Field: [7:0] VREADS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_VREADS_W 8 +#define FLASH_FBAC_VREADS_M 0x000000FF +#define FLASH_FBAC_VREADS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBFALLBACK +// +//***************************************************************************** +// Field: [27:24] FSM_PWRSAV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4 +#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000 +#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24 + +// Field: [19:16] REG_PWRSAV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_REG_PWRSAV_W 4 +#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000 +#define FLASH_FBFALLBACK_REG_PWRSAV_S 16 + +// Field: [15:14] BANKPWR7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR7_W 2 +#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000 +#define FLASH_FBFALLBACK_BANKPWR7_S 14 + +// Field: [13:12] BANKPWR6 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR6_W 2 +#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000 +#define FLASH_FBFALLBACK_BANKPWR6_S 12 + +// Field: [11:10] BANKPWR5 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR5_W 2 +#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00 +#define FLASH_FBFALLBACK_BANKPWR5_S 10 + +// Field: [9:8] BANKPWR4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR4_W 2 +#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300 +#define FLASH_FBFALLBACK_BANKPWR4_S 8 + +// Field: [7:6] BANKPWR3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR3_W 2 +#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0 +#define FLASH_FBFALLBACK_BANKPWR3_S 6 + +// Field: [5:4] BANKPWR2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR2_W 2 +#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030 +#define FLASH_FBFALLBACK_BANKPWR2_S 4 + +// Field: [3:2] BANKPWR1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR1_W 2 +#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C +#define FLASH_FBFALLBACK_BANKPWR1_S 2 + +// Field: [1:0] BANKPWR0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR0_W 2 +#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003 +#define FLASH_FBFALLBACK_BANKPWR0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBPRDY +// +//***************************************************************************** +// Field: [16] BANKBUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_BANKBUSY 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_BITN 16 +#define FLASH_FBPRDY_BANKBUSY_M 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_S 16 + +// Field: [15] PUMPRDY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_PUMPRDY 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_BITN 15 +#define FLASH_FBPRDY_PUMPRDY_M 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_S 15 + +// Field: [0] BANKRDY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_BANKRDY 0x00000001 +#define FLASH_FBPRDY_BANKRDY_BITN 0 +#define FLASH_FBPRDY_BANKRDY_M 0x00000001 +#define FLASH_FBPRDY_BANKRDY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FPAC1 +// +//***************************************************************************** +// Field: [27:16] PSLEEPTDIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PSLEEPTDIS_W 12 +#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000 +#define FLASH_FPAC1_PSLEEPTDIS_S 16 + +// Field: [15:4] PUMPRESET_PW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PUMPRESET_PW_W 12 +#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0 +#define FLASH_FPAC1_PUMPRESET_PW_S 4 + +// Field: [1:0] PUMPPWR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PUMPPWR_W 2 +#define FLASH_FPAC1_PUMPPWR_M 0x00000003 +#define FLASH_FPAC1_PUMPPWR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FPAC2 +// +//***************************************************************************** +// Field: [15:0] PAGP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC2_PAGP_W 16 +#define FLASH_FPAC2_PAGP_M 0x0000FFFF +#define FLASH_FPAC2_PAGP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMAC +// +//***************************************************************************** +// Field: [2:0] BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMAC_BANK_W 3 +#define FLASH_FMAC_BANK_M 0x00000007 +#define FLASH_FMAC_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMSTAT +// +//***************************************************************************** +// Field: [17] RVSUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RVSUSP 0x00020000 +#define FLASH_FMSTAT_RVSUSP_BITN 17 +#define FLASH_FMSTAT_RVSUSP_M 0x00020000 +#define FLASH_FMSTAT_RVSUSP_S 17 + +// Field: [16] RDVER +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RDVER 0x00010000 +#define FLASH_FMSTAT_RDVER_BITN 16 +#define FLASH_FMSTAT_RDVER_M 0x00010000 +#define FLASH_FMSTAT_RDVER_S 16 + +// Field: [15] RVF +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RVF 0x00008000 +#define FLASH_FMSTAT_RVF_BITN 15 +#define FLASH_FMSTAT_RVF_M 0x00008000 +#define FLASH_FMSTAT_RVF_S 15 + +// Field: [14] ILA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ILA 0x00004000 +#define FLASH_FMSTAT_ILA_BITN 14 +#define FLASH_FMSTAT_ILA_M 0x00004000 +#define FLASH_FMSTAT_ILA_S 14 + +// Field: [13] DBF +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_DBF 0x00002000 +#define FLASH_FMSTAT_DBF_BITN 13 +#define FLASH_FMSTAT_DBF_M 0x00002000 +#define FLASH_FMSTAT_DBF_S 13 + +// Field: [12] PGV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PGV 0x00001000 +#define FLASH_FMSTAT_PGV_BITN 12 +#define FLASH_FMSTAT_PGV_M 0x00001000 +#define FLASH_FMSTAT_PGV_S 12 + +// Field: [11] PCV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PCV 0x00000800 +#define FLASH_FMSTAT_PCV_BITN 11 +#define FLASH_FMSTAT_PCV_M 0x00000800 +#define FLASH_FMSTAT_PCV_S 11 + +// Field: [10] EV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_EV 0x00000400 +#define FLASH_FMSTAT_EV_BITN 10 +#define FLASH_FMSTAT_EV_M 0x00000400 +#define FLASH_FMSTAT_EV_S 10 + +// Field: [9] CV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_CV 0x00000200 +#define FLASH_FMSTAT_CV_BITN 9 +#define FLASH_FMSTAT_CV_M 0x00000200 +#define FLASH_FMSTAT_CV_S 9 + +// Field: [8] BUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_BUSY 0x00000100 +#define FLASH_FMSTAT_BUSY_BITN 8 +#define FLASH_FMSTAT_BUSY_M 0x00000100 +#define FLASH_FMSTAT_BUSY_S 8 + +// Field: [7] ERS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ERS 0x00000080 +#define FLASH_FMSTAT_ERS_BITN 7 +#define FLASH_FMSTAT_ERS_M 0x00000080 +#define FLASH_FMSTAT_ERS_S 7 + +// Field: [6] PGM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PGM 0x00000040 +#define FLASH_FMSTAT_PGM_BITN 6 +#define FLASH_FMSTAT_PGM_M 0x00000040 +#define FLASH_FMSTAT_PGM_S 6 + +// Field: [5] INVDAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_INVDAT 0x00000020 +#define FLASH_FMSTAT_INVDAT_BITN 5 +#define FLASH_FMSTAT_INVDAT_M 0x00000020 +#define FLASH_FMSTAT_INVDAT_S 5 + +// Field: [4] CSTAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_CSTAT 0x00000010 +#define FLASH_FMSTAT_CSTAT_BITN 4 +#define FLASH_FMSTAT_CSTAT_M 0x00000010 +#define FLASH_FMSTAT_CSTAT_S 4 + +// Field: [3] VOLSTAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_VOLSTAT 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_BITN 3 +#define FLASH_FMSTAT_VOLSTAT_M 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_S 3 + +// Field: [2] ESUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ESUSP 0x00000004 +#define FLASH_FMSTAT_ESUSP_BITN 2 +#define FLASH_FMSTAT_ESUSP_M 0x00000004 +#define FLASH_FMSTAT_ESUSP_S 2 + +// Field: [1] PSUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PSUSP 0x00000002 +#define FLASH_FMSTAT_PSUSP_BITN 1 +#define FLASH_FMSTAT_PSUSP_M 0x00000002 +#define FLASH_FMSTAT_PSUSP_S 1 + +// Field: [0] SLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_SLOCK 0x00000001 +#define FLASH_FMSTAT_SLOCK_BITN 0 +#define FLASH_FMSTAT_SLOCK_M 0x00000001 +#define FLASH_FMSTAT_SLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FLOCK +// +//***************************************************************************** +// Field: [15:0] ENCOM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FLOCK_ENCOM_W 16 +#define FLASH_FLOCK_ENCOM_M 0x0000FFFF +#define FLASH_FLOCK_ENCOM_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVREADCT +// +//***************************************************************************** +// Field: [3:0] VREADCT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVREADCT_VREADCT_W 4 +#define FLASH_FVREADCT_VREADCT_M 0x0000000F +#define FLASH_FVREADCT_VREADCT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT1 +// +//***************************************************************************** +// Field: [23:20] TRIM13_E +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_TRIM13_E_W 4 +#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 +#define FLASH_FVHVCT1_TRIM13_E_S 20 + +// Field: [19:16] VHVCT_E +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_VHVCT_E_W 4 +#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 +#define FLASH_FVHVCT1_VHVCT_E_S 16 + +// Field: [7:4] TRIM13_PV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_TRIM13_PV_W 4 +#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 +#define FLASH_FVHVCT1_TRIM13_PV_S 4 + +// Field: [3:0] VHVCT_PV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_VHVCT_PV_W 4 +#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F +#define FLASH_FVHVCT1_VHVCT_PV_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT2 +// +//***************************************************************************** +// Field: [23:20] TRIM13_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT2_TRIM13_P_W 4 +#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 +#define FLASH_FVHVCT2_TRIM13_P_S 20 + +// Field: [19:16] VHVCT_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT2_VHVCT_P_W 4 +#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 +#define FLASH_FVHVCT2_VHVCT_P_S 16 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT3 +// +//***************************************************************************** +// Field: [19:16] WCT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT3_WCT_W 4 +#define FLASH_FVHVCT3_WCT_M 0x000F0000 +#define FLASH_FVHVCT3_WCT_S 16 + +// Field: [3:0] VHVCT_READ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT3_VHVCT_READ_W 4 +#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F +#define FLASH_FVHVCT3_VHVCT_READ_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVNVCT +// +//***************************************************************************** +// Field: [12:8] VCG2P5CT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVNVCT_VCG2P5CT_W 5 +#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 +#define FLASH_FVNVCT_VCG2P5CT_S 8 + +// Field: [4:0] VIN_CT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVNVCT_VIN_CT_W 5 +#define FLASH_FVNVCT_VIN_CT_M 0x0000001F +#define FLASH_FVNVCT_VIN_CT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVSLP +// +//***************************************************************************** +// Field: [15:12] VSL_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVSLP_VSL_P_W 4 +#define FLASH_FVSLP_VSL_P_M 0x0000F000 +#define FLASH_FVSLP_VSL_P_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FVWLCT +// +//***************************************************************************** +// Field: [4:0] VWLCT_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVWLCT_VWLCT_P_W 5 +#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F +#define FLASH_FVWLCT_VWLCT_P_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSECTL +// +//***************************************************************************** +// Field: [26:24] CHAIN_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_CHAIN_SEL_W 3 +#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000 +#define FLASH_FEFUSECTL_CHAIN_SEL_S 24 + +// Field: [17] WRITE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_WRITE_EN 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_BITN 17 +#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_S 17 + +// Field: [16] BP_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_BP_SEL 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_BITN 16 +#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_S 16 + +// Field: [8] EF_CLRZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8 +#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_S 8 + +// Field: [4] EF_TEST +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EF_TEST 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_BITN 4 +#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_S 4 + +// Field: [3:0] EFUSE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EFUSE_EN_W 4 +#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F +#define FLASH_FEFUSECTL_EFUSE_EN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSESTAT +// +//***************************************************************************** +// Field: [0] SHIFT_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0 +#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSEDATA +// +//***************************************************************************** +// Field: [31:0] FEFUSEDATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32 +#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF +#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSEQPMP +// +//***************************************************************************** +// Field: [27:24] TRIM_3P4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_3P4_W 4 +#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000 +#define FLASH_FSEQPMP_TRIM_3P4_S 24 + +// Field: [21:20] TRIM_1P7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_1P7_W 2 +#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 +#define FLASH_FSEQPMP_TRIM_1P7_S 20 + +// Field: [19:16] TRIM_0P8 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_0P8_W 4 +#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000 +#define FLASH_FSEQPMP_TRIM_0P8_S 16 + +// Field: [14:12] VIN_AT_X +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_VIN_AT_X_W 3 +#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 +#define FLASH_FSEQPMP_VIN_AT_X_S 12 + +// Field: [8] VIN_BY_PASS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8 +#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FBSTROBES +// +//***************************************************************************** +// Field: [24] ECBIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_ECBIT 0x01000000 +#define FLASH_FBSTROBES_ECBIT_BITN 24 +#define FLASH_FBSTROBES_ECBIT_M 0x01000000 +#define FLASH_FBSTROBES_ECBIT_S 24 + +// Field: [18] RWAIT2_FLCLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18 + +// Field: [17] RWAIT_FLCLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17 +#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17 + +// Field: [16] FLCLKEN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_FLCLKEN 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_BITN 16 +#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_S 16 + +// Field: [8] CTRLENZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_CTRLENZ 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_BITN 8 +#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_S 8 + +// Field: [6] NOCOLRED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_NOCOLRED 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_BITN 6 +#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_S 6 + +// Field: [5] PRECOL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_PRECOL 0x00000020 +#define FLASH_FBSTROBES_PRECOL_BITN 5 +#define FLASH_FBSTROBES_PRECOL_M 0x00000020 +#define FLASH_FBSTROBES_PRECOL_S 5 + +// Field: [4] TI_OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_TI_OTP 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_BITN 4 +#define FLASH_FBSTROBES_TI_OTP_M 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_S 4 + +// Field: [3] OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_OTP 0x00000008 +#define FLASH_FBSTROBES_OTP_BITN 3 +#define FLASH_FBSTROBES_OTP_M 0x00000008 +#define FLASH_FBSTROBES_OTP_S 3 + +// Field: [2] TEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_TEZ 0x00000004 +#define FLASH_FBSTROBES_TEZ_BITN 2 +#define FLASH_FBSTROBES_TEZ_M 0x00000004 +#define FLASH_FBSTROBES_TEZ_S 2 + +//***************************************************************************** +// +// Register: FLASH_O_FPSTROBES +// +//***************************************************************************** +// Field: [8] EXECUTEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_EXECUTEZ 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_BITN 8 +#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_S 8 + +// Field: [1] V3PWRDNZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1 +#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_S 1 + +// Field: [0] V5PWRDNZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0 +#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBMODE +// +//***************************************************************************** +// Field: [2:0] MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBMODE_MODE_W 3 +#define FLASH_FBMODE_MODE_M 0x00000007 +#define FLASH_FBMODE_MODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FTCR +// +//***************************************************************************** +// Field: [6:0] TCR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCR_TCR_W 7 +#define FLASH_FTCR_TCR_M 0x0000007F +#define FLASH_FTCR_TCR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FADDR +// +//***************************************************************************** +// Field: [31:0] FADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FADDR_FADDR_W 32 +#define FLASH_FADDR_FADDR_M 0xFFFFFFFF +#define FLASH_FADDR_FADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FTCTL +// +//***************************************************************************** +// Field: [16] WDATA_BLK_CLR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16 +#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_S 16 + +// Field: [1] TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCTL_TEST_EN 0x00000002 +#define FLASH_FTCTL_TEST_EN_BITN 1 +#define FLASH_FTCTL_TEST_EN_M 0x00000002 +#define FLASH_FTCTL_TEST_EN_S 1 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE0 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE0_FWPWRITE0_W 32 +#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF +#define FLASH_FWPWRITE0_FWPWRITE0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE1 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE1_FWPWRITE1_W 32 +#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF +#define FLASH_FWPWRITE1_FWPWRITE1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE2 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE2_FWPWRITE2_W 32 +#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF +#define FLASH_FWPWRITE2_FWPWRITE2_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE3 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE3_FWPWRITE3_W 32 +#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF +#define FLASH_FWPWRITE3_FWPWRITE3_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE4 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE4_FWPWRITE4_W 32 +#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF +#define FLASH_FWPWRITE4_FWPWRITE4_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE5 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE5 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE5_FWPWRITE5_W 32 +#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF +#define FLASH_FWPWRITE5_FWPWRITE5_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE6 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE6 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE6_FWPWRITE6_W 32 +#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF +#define FLASH_FWPWRITE6_FWPWRITE6_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE7 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE7_FWPWRITE7_W 32 +#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF +#define FLASH_FWPWRITE7_FWPWRITE7_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE_ECC +// +//***************************************************************************** +// Field: [31:24] ECCBYTES07_00 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24 + +// Field: [23:16] ECCBYTES15_08 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16 + +// Field: [15:8] ECCBYTES23_16 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8 + +// Field: [7:0] ECCBYTES31_24 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSWSTAT +// +//***************************************************************************** +// Field: [0] SAFELV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSWSTAT_SAFELV 0x00000001 +#define FLASH_FSWSTAT_SAFELV_BITN 0 +#define FLASH_FSWSTAT_SAFELV_M 0x00000001 +#define FLASH_FSWSTAT_SAFELV_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_GLBCTL +// +//***************************************************************************** +// Field: [0] CLKSEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0 +#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STATE +// +//***************************************************************************** +// Field: [11] CTRLENZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_CTRLENZ 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_BITN 11 +#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_S 11 + +// Field: [10] EXECUTEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_EXECUTEZ 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_BITN 10 +#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_S 10 + +// Field: [8] FSM_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_FSM_ACT 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_BITN 8 +#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_S 8 + +// Field: [7] TIOTP_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7 +#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_S 7 + +// Field: [6] OTP_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_OTP_ACT 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_BITN 6 +#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_S 6 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STAT +// +//***************************************************************************** +// Field: [2] NON_OP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_NON_OP 0x00000004 +#define FLASH_FSM_STAT_NON_OP_BITN 2 +#define FLASH_FSM_STAT_NON_OP_M 0x00000004 +#define FLASH_FSM_STAT_NON_OP_S 2 + +// Field: [1] OVR_PUL_CNT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1 +#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1 + +// Field: [0] INV_DAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_INV_DAT 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_BITN 0 +#define FLASH_FSM_STAT_INV_DAT_M 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_CMD +// +//***************************************************************************** +// Field: [5:0] FSMCMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_CMD_FSMCMD_W 6 +#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F +#define FLASH_FSM_CMD_FSMCMD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_OSU +// +//***************************************************************************** +// Field: [15:8] PGM_OSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_OSU_PGM_OSU_W 8 +#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 +#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 + +// Field: [7:0] ERA_OSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_OSU_ERA_OSU_W 8 +#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF +#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_VSTAT +// +//***************************************************************************** +// Field: [15:12] VSTAT_CNT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4 +#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 +#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_VSU +// +//***************************************************************************** +// Field: [15:8] PGM_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VSU_PGM_VSU_W 8 +#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 +#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 + +// Field: [7:0] ERA_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VSU_ERA_VSU_W 8 +#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF +#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_CMP_VSU +// +//***************************************************************************** +// Field: [15:12] ADD_EXZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EX_VAL +// +//***************************************************************************** +// Field: [15:8] REP_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EX_VAL_REP_VSU_W 8 +#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 +#define FLASH_FSM_EX_VAL_REP_VSU_S 8 + +// Field: [7:0] EXE_VALD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EX_VAL_EXE_VALD_W 8 +#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF +#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_RD_H +// +//***************************************************************************** +// Field: [7:0] RD_H +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_RD_H_RD_H_W 8 +#define FLASH_FSM_RD_H_RD_H_M 0x000000FF +#define FLASH_FSM_RD_H_RD_H_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_P_OH +// +//***************************************************************************** +// Field: [15:8] PGM_OH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_P_OH_PGM_OH_W 8 +#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 +#define FLASH_FSM_P_OH_PGM_OH_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_OH +// +//***************************************************************************** +// Field: [15:0] ERA_OH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_OH_ERA_OH_W 16 +#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF +#define FLASH_FSM_ERA_OH_ERA_OH_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SAV_PPUL +// +//***************************************************************************** +// Field: [11:0] SAV_P_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12 +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_VH +// +//***************************************************************************** +// Field: [15:8] PGM_VH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VH_PGM_VH_W 8 +#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 +#define FLASH_FSM_PE_VH_PGM_VH_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PRG_PW +// +//***************************************************************************** +// Field: [15:0] PROG_PUL_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16 +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_PW +// +//***************************************************************************** +// Field: [31:0] FSM_ERA_PW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32 +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SAV_ERA_PUL +// +//***************************************************************************** +// Field: [11:0] SAV_ERA_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12 +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_TIMER +// +//***************************************************************************** +// Field: [31:0] FSM_TIMER +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_TIMER_FSM_TIMER_W 32 +#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF +#define FLASH_FSM_TIMER_FSM_TIMER_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_MODE +// +//***************************************************************************** +// Field: [19:18] RDV_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_RDV_SUBMODE_W 2 +#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000 +#define FLASH_FSM_MODE_RDV_SUBMODE_S 18 + +// Field: [17:16] PGM_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_PGM_SUBMODE_W 2 +#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000 +#define FLASH_FSM_MODE_PGM_SUBMODE_S 16 + +// Field: [15:14] ERA_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_ERA_SUBMODE_W 2 +#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000 +#define FLASH_FSM_MODE_ERA_SUBMODE_S 14 + +// Field: [13:12] SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SUBMODE_W 2 +#define FLASH_FSM_MODE_SUBMODE_M 0x00003000 +#define FLASH_FSM_MODE_SUBMODE_S 12 + +// Field: [11:9] SAV_PGM_CMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3 +#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00 +#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9 + +// Field: [8:6] SAV_ERA_MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3 +#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0 +#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6 + +// Field: [5:3] MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_MODE_W 3 +#define FLASH_FSM_MODE_MODE_M 0x00000038 +#define FLASH_FSM_MODE_MODE_S 3 + +// Field: [2:0] CMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_CMD_W 3 +#define FLASH_FSM_MODE_CMD_M 0x00000007 +#define FLASH_FSM_MODE_CMD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PGM +// +//***************************************************************************** +// Field: [25:23] PGM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_PGM_BANK_W 3 +#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000 +#define FLASH_FSM_PGM_PGM_BANK_S 23 + +// Field: [22:0] PGM_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_PGM_ADDR_W 23 +#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF +#define FLASH_FSM_PGM_PGM_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA +// +//***************************************************************************** +// Field: [25:23] ERA_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_ERA_BANK_W 3 +#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000 +#define FLASH_FSM_ERA_ERA_BANK_S 23 + +// Field: [22:0] ERA_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_ERA_ADDR_W 23 +#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF +#define FLASH_FSM_ERA_ERA_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PRG_PUL +// +//***************************************************************************** +// Field: [19:16] BEG_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 + +// Field: [11:0] MAX_PRG_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12 +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_PUL +// +//***************************************************************************** +// Field: [19:16] MAX_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 + +// Field: [11:0] MAX_ERA_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12 +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STEP_SIZE +// +//***************************************************************************** +// Field: [24:16] EC_STEP_SIZE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PUL_CNTR +// +//***************************************************************************** +// Field: [24:16] CUR_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16 + +// Field: [11:0] PUL_CNTR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12 +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EC_STEP_HEIGHT +// +//***************************************************************************** +// Field: [3:0] EC_STEP_HEIGHT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4 +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ST_MACHINE +// +//***************************************************************************** +// Field: [23] DO_PRECOND +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 + +// Field: [22] FSM_INT_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22 + +// Field: [21] ALL_BANKS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21 + +// Field: [20] CMPV_ALLOWED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20 + +// Field: [19] RANDOM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19 +#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_S 19 + +// Field: [18] RV_SEC_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18 + +// Field: [17] RV_RES +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17 +#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_S 17 + +// Field: [16] RV_INT_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16 + +// Field: [14] ONE_TIME_GOOD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14 + +// Field: [11] DO_REDU_COL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11 + +// Field: [10:7] DBG_SHORT_ROW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7 + +// Field: [5] PGM_SEC_COF_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5 + +// Field: [4] PREC_STOP_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4 + +// Field: [3] DIS_TST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3 + +// Field: [2] CMD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2 +#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2 + +// Field: [1] INV_DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1 +#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1 + +// Field: [0] OVERRIDE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_FLES +// +//***************************************************************************** +// Field: [11:8] BLK_TIOTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_FLES_BLK_TIOTP_W 4 +#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00 +#define FLASH_FSM_FLES_BLK_TIOTP_S 8 + +// Field: [7:0] BLK_OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_FLES_BLK_OTP_W 8 +#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF +#define FLASH_FSM_FLES_BLK_OTP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_WR_ENA +// +//***************************************************************************** +// Field: [2:0] WR_ENA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_WR_ENA_WR_ENA_W 3 +#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007 +#define FLASH_FSM_WR_ENA_WR_ENA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ACC_PP +// +//***************************************************************************** +// Field: [31:0] FSM_ACC_PP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32 +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ACC_EP +// +//***************************************************************************** +// Field: [15:0] ACC_EP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ACC_EP_ACC_EP_W 16 +#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF +#define FLASH_FSM_ACC_EP_ACC_EP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ADDR +// +//***************************************************************************** +// Field: [30:28] BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ADDR_BANK_W 3 +#define FLASH_FSM_ADDR_BANK_M 0x70000000 +#define FLASH_FSM_ADDR_BANK_S 28 + +// Field: [27:0] CUR_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ADDR_CUR_ADDR_W 28 +#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF +#define FLASH_FSM_ADDR_CUR_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR +// +//***************************************************************************** +// Field: [31:16] SECT_ERASED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SECT_ERASED_W 16 +#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000 +#define FLASH_FSM_SECTOR_SECT_ERASED_S 16 + +// Field: [15:8] FSM_SECTOR_EXTENSION +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8 + +// Field: [7:4] SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SECTOR_W 4 +#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0 +#define FLASH_FSM_SECTOR_SECTOR_S 4 + +// Field: [3:0] SEC_OUT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SEC_OUT_W 4 +#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F +#define FLASH_FSM_SECTOR_SEC_OUT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMC_REV_ID +// +//***************************************************************************** +// Field: [31:12] MOD_VERSION +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMC_REV_ID_MOD_VERSION_W 20 +#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000 +#define FLASH_FMC_REV_ID_MOD_VERSION_S 12 + +// Field: [11:0] CONFIG_CRC +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12 +#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF +#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERR_ADDR +// +//***************************************************************************** +// Field: [31:8] FSM_ERR_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0xFFFFFF00 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 8 + +// Field: [3:0] FSM_ERR_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 4 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x0000000F +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PGM_MAXPUL +// +//***************************************************************************** +// Field: [11:0] FSM_PGM_MAXPUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12 +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EXECUTE +// +//***************************************************************************** +// Field: [19:16] SUSPEND_NOW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16 + +// Field: [4:0] FSMEXECUTE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5 +#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F +#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR1 +// +//***************************************************************************** +// Field: [31:0] FSM_SECTOR1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32 +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR2 +// +//***************************************************************************** +// Field: [31:0] FSM_SECTOR2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32 +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLE0 +// +//***************************************************************************** +// Field: [31:0] FSM_BSLE0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32 +#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF +#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLE1 +// +//***************************************************************************** +// Field: [31:0] FSM_BSL1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLE1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLE1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLE1_FSM_BSL1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLP0 +// +//***************************************************************************** +// Field: [31:0] FSM_BSLP0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32 +#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF +#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLP1 +// +//***************************************************************************** +// Field: [31:0] FSM_BSL1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLP1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLP1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLP1_FSM_BSL1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_BANK +// +//***************************************************************************** +// Field: [31:20] EE_BANK_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20 + +// Field: [19:16] EE_NUM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000 +#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16 + +// Field: [15:4] MAIN_BANK_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 + +// Field: [3:0] MAIN_NUM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_WRAPPER +// +//***************************************************************************** +// Field: [31:24] FAMILY_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24 + +// Field: [20] MEM_MAP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20 +#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20 + +// Field: [19:16] CPU2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_CPU2_W 4 +#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000 +#define FLASH_FCFG_WRAPPER_CPU2_S 16 + +// Field: [15:12] EE_IN_MAIN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12 + +// Field: [11] ROM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_ROM 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_BITN 11 +#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_S 11 + +// Field: [10] IFLUSH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10 +#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_S 10 + +// Field: [9] SIL3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_SIL3 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_BITN 9 +#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_S 9 + +// Field: [8] ECCA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_ECCA 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_BITN 8 +#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_S 8 + +// Field: [7:6] AUTO_SUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6 + +// Field: [5:4] UERR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_UERR_W 2 +#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030 +#define FLASH_FCFG_WRAPPER_UERR_S 4 + +// Field: [3:0] CPU_TYPE1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4 +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_BNK_TYPE +// +//***************************************************************************** +// Field: [31:28] B7_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28 + +// Field: [27:24] B6_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24 + +// Field: [23:20] B5_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20 + +// Field: [19:16] B4_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16 + +// Field: [15:12] B3_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12 + +// Field: [11:8] B2_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8 + +// Field: [7:4] B1_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4 + +// Field: [3:0] B0_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B0_START +// +//***************************************************************************** +// Field: [31:28] B0_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28 + +// Field: [27:24] B0_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24 + +// Field: [23:0] B0_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24 +#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B1_START +// +//***************************************************************************** +// Field: [31:28] B1_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28 + +// Field: [27:24] B1_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24 + +// Field: [23:0] B1_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24 +#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B2_START +// +//***************************************************************************** +// Field: [31:28] B2_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28 + +// Field: [27:24] B2_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24 + +// Field: [23:0] B2_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24 +#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B3_START +// +//***************************************************************************** +// Field: [31:28] B3_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28 + +// Field: [27:24] B3_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24 + +// Field: [23:0] B3_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24 +#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B4_START +// +//***************************************************************************** +// Field: [31:28] B4_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28 + +// Field: [27:24] B4_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24 + +// Field: [23:0] B4_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24 +#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B5_START +// +//***************************************************************************** +// Field: [31:28] B5_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28 + +// Field: [27:24] B5_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24 + +// Field: [23:0] B5_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24 +#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B6_START +// +//***************************************************************************** +// Field: [31:28] B6_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28 + +// Field: [27:24] B6_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24 + +// Field: [23:0] B6_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24 +#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B7_START +// +//***************************************************************************** +// Field: [31:28] B7_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28 + +// Field: [27:24] B7_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24 + +// Field: [23:0] B7_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24 +#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B0_SSIZE0 +// +//***************************************************************************** +// Field: [27:16] B0_NUM_SECTORS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16 + +// Field: [3:0] B0_SECT_SIZE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4 +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 + + +#endif // __FLASH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpio.h new file mode 100644 index 0000000..98f51c9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpio.h @@ -0,0 +1,2247 @@ +/****************************************************************************** +* Filename: hw_gpio_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// GPIO component +// +//***************************************************************************** +// Data Out 0 to 3 +#define GPIO_O_DOUT3_0 0x00000000 + +// Data Out 4 to 7 +#define GPIO_O_DOUT7_4 0x00000004 + +// Data Out 8 to 11 +#define GPIO_O_DOUT11_8 0x00000008 + +// Data Out 12 to 15 +#define GPIO_O_DOUT15_12 0x0000000C + +// Data Out 16 to 19 +#define GPIO_O_DOUT19_16 0x00000010 + +// Data Out 20 to 23 +#define GPIO_O_DOUT23_20 0x00000014 + +// Data Out 24 to 27 +#define GPIO_O_DOUT27_24 0x00000018 + +// Data Out 28 to 31 +#define GPIO_O_DOUT31_28 0x0000001C + +// Data Output for DIO 0 to 31 +#define GPIO_O_DOUT31_0 0x00000080 + +// Data Out Set +#define GPIO_O_DOUTSET31_0 0x00000090 + +// Data Out Clear +#define GPIO_O_DOUTCLR31_0 0x000000A0 + +// Data Out Toggle +#define GPIO_O_DOUTTGL31_0 0x000000B0 + +// Data Input from DIO 0 to 31 +#define GPIO_O_DIN31_0 0x000000C0 + +// Data Output Enable for DIO 0 to 31 +#define GPIO_O_DOE31_0 0x000000D0 + +// Event Register for DIO 0 to 31 +#define GPIO_O_EVFLAGS31_0 0x000000E0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT3_0 +// +//***************************************************************************** +// Field: [24] DIO3 +// +// Sets the state of the pin that is configured as DIO#3, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO3 0x01000000 +#define GPIO_DOUT3_0_DIO3_BITN 24 +#define GPIO_DOUT3_0_DIO3_M 0x01000000 +#define GPIO_DOUT3_0_DIO3_S 24 + +// Field: [16] DIO2 +// +// Sets the state of the pin that is configured as DIO#2, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO2 0x00010000 +#define GPIO_DOUT3_0_DIO2_BITN 16 +#define GPIO_DOUT3_0_DIO2_M 0x00010000 +#define GPIO_DOUT3_0_DIO2_S 16 + +// Field: [8] DIO1 +// +// Sets the state of the pin that is configured as DIO#1, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO1 0x00000100 +#define GPIO_DOUT3_0_DIO1_BITN 8 +#define GPIO_DOUT3_0_DIO1_M 0x00000100 +#define GPIO_DOUT3_0_DIO1_S 8 + +// Field: [0] DIO0 +// +// Sets the state of the pin that is configured as DIO#0, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO0 0x00000001 +#define GPIO_DOUT3_0_DIO0_BITN 0 +#define GPIO_DOUT3_0_DIO0_M 0x00000001 +#define GPIO_DOUT3_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT7_4 +// +//***************************************************************************** +// Field: [24] DIO7 +// +// Sets the state of the pin that is configured as DIO#7, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO7 0x01000000 +#define GPIO_DOUT7_4_DIO7_BITN 24 +#define GPIO_DOUT7_4_DIO7_M 0x01000000 +#define GPIO_DOUT7_4_DIO7_S 24 + +// Field: [16] DIO6 +// +// Sets the state of the pin that is configured as DIO#6, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO6 0x00010000 +#define GPIO_DOUT7_4_DIO6_BITN 16 +#define GPIO_DOUT7_4_DIO6_M 0x00010000 +#define GPIO_DOUT7_4_DIO6_S 16 + +// Field: [8] DIO5 +// +// Sets the state of the pin that is configured as DIO#5, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO5 0x00000100 +#define GPIO_DOUT7_4_DIO5_BITN 8 +#define GPIO_DOUT7_4_DIO5_M 0x00000100 +#define GPIO_DOUT7_4_DIO5_S 8 + +// Field: [0] DIO4 +// +// Sets the state of the pin that is configured as DIO#4, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO4 0x00000001 +#define GPIO_DOUT7_4_DIO4_BITN 0 +#define GPIO_DOUT7_4_DIO4_M 0x00000001 +#define GPIO_DOUT7_4_DIO4_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT11_8 +// +//***************************************************************************** +// Field: [24] DIO11 +// +// Sets the state of the pin that is configured as DIO#11, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO11 0x01000000 +#define GPIO_DOUT11_8_DIO11_BITN 24 +#define GPIO_DOUT11_8_DIO11_M 0x01000000 +#define GPIO_DOUT11_8_DIO11_S 24 + +// Field: [16] DIO10 +// +// Sets the state of the pin that is configured as DIO#10, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO10 0x00010000 +#define GPIO_DOUT11_8_DIO10_BITN 16 +#define GPIO_DOUT11_8_DIO10_M 0x00010000 +#define GPIO_DOUT11_8_DIO10_S 16 + +// Field: [8] DIO9 +// +// Sets the state of the pin that is configured as DIO#9, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO9 0x00000100 +#define GPIO_DOUT11_8_DIO9_BITN 8 +#define GPIO_DOUT11_8_DIO9_M 0x00000100 +#define GPIO_DOUT11_8_DIO9_S 8 + +// Field: [0] DIO8 +// +// Sets the state of the pin that is configured as DIO#8, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO8 0x00000001 +#define GPIO_DOUT11_8_DIO8_BITN 0 +#define GPIO_DOUT11_8_DIO8_M 0x00000001 +#define GPIO_DOUT11_8_DIO8_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT15_12 +// +//***************************************************************************** +// Field: [24] DIO15 +// +// Sets the state of the pin that is configured as DIO#15, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO15 0x01000000 +#define GPIO_DOUT15_12_DIO15_BITN 24 +#define GPIO_DOUT15_12_DIO15_M 0x01000000 +#define GPIO_DOUT15_12_DIO15_S 24 + +// Field: [16] DIO14 +// +// Sets the state of the pin that is configured as DIO#14, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO14 0x00010000 +#define GPIO_DOUT15_12_DIO14_BITN 16 +#define GPIO_DOUT15_12_DIO14_M 0x00010000 +#define GPIO_DOUT15_12_DIO14_S 16 + +// Field: [8] DIO13 +// +// Sets the state of the pin that is configured as DIO#13, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO13 0x00000100 +#define GPIO_DOUT15_12_DIO13_BITN 8 +#define GPIO_DOUT15_12_DIO13_M 0x00000100 +#define GPIO_DOUT15_12_DIO13_S 8 + +// Field: [0] DIO12 +// +// Sets the state of the pin that is configured as DIO#12, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO12 0x00000001 +#define GPIO_DOUT15_12_DIO12_BITN 0 +#define GPIO_DOUT15_12_DIO12_M 0x00000001 +#define GPIO_DOUT15_12_DIO12_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT19_16 +// +//***************************************************************************** +// Field: [24] DIO19 +// +// Sets the state of the pin that is configured as DIO#19, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO19 0x01000000 +#define GPIO_DOUT19_16_DIO19_BITN 24 +#define GPIO_DOUT19_16_DIO19_M 0x01000000 +#define GPIO_DOUT19_16_DIO19_S 24 + +// Field: [16] DIO18 +// +// Sets the state of the pin that is configured as DIO#18, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO18 0x00010000 +#define GPIO_DOUT19_16_DIO18_BITN 16 +#define GPIO_DOUT19_16_DIO18_M 0x00010000 +#define GPIO_DOUT19_16_DIO18_S 16 + +// Field: [8] DIO17 +// +// Sets the state of the pin that is configured as DIO#17, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO17 0x00000100 +#define GPIO_DOUT19_16_DIO17_BITN 8 +#define GPIO_DOUT19_16_DIO17_M 0x00000100 +#define GPIO_DOUT19_16_DIO17_S 8 + +// Field: [0] DIO16 +// +// Sets the state of the pin that is configured as DIO#16, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO16 0x00000001 +#define GPIO_DOUT19_16_DIO16_BITN 0 +#define GPIO_DOUT19_16_DIO16_M 0x00000001 +#define GPIO_DOUT19_16_DIO16_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT23_20 +// +//***************************************************************************** +// Field: [24] DIO23 +// +// Sets the state of the pin that is configured as DIO#23, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO23 0x01000000 +#define GPIO_DOUT23_20_DIO23_BITN 24 +#define GPIO_DOUT23_20_DIO23_M 0x01000000 +#define GPIO_DOUT23_20_DIO23_S 24 + +// Field: [16] DIO22 +// +// Sets the state of the pin that is configured as DIO#22, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO22 0x00010000 +#define GPIO_DOUT23_20_DIO22_BITN 16 +#define GPIO_DOUT23_20_DIO22_M 0x00010000 +#define GPIO_DOUT23_20_DIO22_S 16 + +// Field: [8] DIO21 +// +// Sets the state of the pin that is configured as DIO#21, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO21 0x00000100 +#define GPIO_DOUT23_20_DIO21_BITN 8 +#define GPIO_DOUT23_20_DIO21_M 0x00000100 +#define GPIO_DOUT23_20_DIO21_S 8 + +// Field: [0] DIO20 +// +// Sets the state of the pin that is configured as DIO#20, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO20 0x00000001 +#define GPIO_DOUT23_20_DIO20_BITN 0 +#define GPIO_DOUT23_20_DIO20_M 0x00000001 +#define GPIO_DOUT23_20_DIO20_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT27_24 +// +//***************************************************************************** +// Field: [24] DIO27 +// +// Sets the state of the pin that is configured as DIO#27, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO27 0x01000000 +#define GPIO_DOUT27_24_DIO27_BITN 24 +#define GPIO_DOUT27_24_DIO27_M 0x01000000 +#define GPIO_DOUT27_24_DIO27_S 24 + +// Field: [16] DIO26 +// +// Sets the state of the pin that is configured as DIO#26, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO26 0x00010000 +#define GPIO_DOUT27_24_DIO26_BITN 16 +#define GPIO_DOUT27_24_DIO26_M 0x00010000 +#define GPIO_DOUT27_24_DIO26_S 16 + +// Field: [8] DIO25 +// +// Sets the state of the pin that is configured as DIO#25, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO25 0x00000100 +#define GPIO_DOUT27_24_DIO25_BITN 8 +#define GPIO_DOUT27_24_DIO25_M 0x00000100 +#define GPIO_DOUT27_24_DIO25_S 8 + +// Field: [0] DIO24 +// +// Sets the state of the pin that is configured as DIO#24, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO24 0x00000001 +#define GPIO_DOUT27_24_DIO24_BITN 0 +#define GPIO_DOUT27_24_DIO24_M 0x00000001 +#define GPIO_DOUT27_24_DIO24_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT31_28 +// +//***************************************************************************** +// Field: [24] DIO31 +// +// Sets the state of the pin that is configured as DIO#31, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO31 0x01000000 +#define GPIO_DOUT31_28_DIO31_BITN 24 +#define GPIO_DOUT31_28_DIO31_M 0x01000000 +#define GPIO_DOUT31_28_DIO31_S 24 + +// Field: [16] DIO30 +// +// Sets the state of the pin that is configured as DIO#30, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO30 0x00010000 +#define GPIO_DOUT31_28_DIO30_BITN 16 +#define GPIO_DOUT31_28_DIO30_M 0x00010000 +#define GPIO_DOUT31_28_DIO30_S 16 + +// Field: [8] DIO29 +// +// Sets the state of the pin that is configured as DIO#29, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO29 0x00000100 +#define GPIO_DOUT31_28_DIO29_BITN 8 +#define GPIO_DOUT31_28_DIO29_M 0x00000100 +#define GPIO_DOUT31_28_DIO29_S 8 + +// Field: [0] DIO28 +// +// Sets the state of the pin that is configured as DIO#28, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO28 0x00000001 +#define GPIO_DOUT31_28_DIO28_BITN 0 +#define GPIO_DOUT31_28_DIO28_M 0x00000001 +#define GPIO_DOUT31_28_DIO28_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data output for DIO 31 +#define GPIO_DOUT31_0_DIO31 0x80000000 +#define GPIO_DOUT31_0_DIO31_BITN 31 +#define GPIO_DOUT31_0_DIO31_M 0x80000000 +#define GPIO_DOUT31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data output for DIO 30 +#define GPIO_DOUT31_0_DIO30 0x40000000 +#define GPIO_DOUT31_0_DIO30_BITN 30 +#define GPIO_DOUT31_0_DIO30_M 0x40000000 +#define GPIO_DOUT31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data output for DIO 29 +#define GPIO_DOUT31_0_DIO29 0x20000000 +#define GPIO_DOUT31_0_DIO29_BITN 29 +#define GPIO_DOUT31_0_DIO29_M 0x20000000 +#define GPIO_DOUT31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data output for DIO 28 +#define GPIO_DOUT31_0_DIO28 0x10000000 +#define GPIO_DOUT31_0_DIO28_BITN 28 +#define GPIO_DOUT31_0_DIO28_M 0x10000000 +#define GPIO_DOUT31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data output for DIO 27 +#define GPIO_DOUT31_0_DIO27 0x08000000 +#define GPIO_DOUT31_0_DIO27_BITN 27 +#define GPIO_DOUT31_0_DIO27_M 0x08000000 +#define GPIO_DOUT31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data output for DIO 26 +#define GPIO_DOUT31_0_DIO26 0x04000000 +#define GPIO_DOUT31_0_DIO26_BITN 26 +#define GPIO_DOUT31_0_DIO26_M 0x04000000 +#define GPIO_DOUT31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data output for DIO 25 +#define GPIO_DOUT31_0_DIO25 0x02000000 +#define GPIO_DOUT31_0_DIO25_BITN 25 +#define GPIO_DOUT31_0_DIO25_M 0x02000000 +#define GPIO_DOUT31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data output for DIO 24 +#define GPIO_DOUT31_0_DIO24 0x01000000 +#define GPIO_DOUT31_0_DIO24_BITN 24 +#define GPIO_DOUT31_0_DIO24_M 0x01000000 +#define GPIO_DOUT31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data output for DIO 23 +#define GPIO_DOUT31_0_DIO23 0x00800000 +#define GPIO_DOUT31_0_DIO23_BITN 23 +#define GPIO_DOUT31_0_DIO23_M 0x00800000 +#define GPIO_DOUT31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data output for DIO 22 +#define GPIO_DOUT31_0_DIO22 0x00400000 +#define GPIO_DOUT31_0_DIO22_BITN 22 +#define GPIO_DOUT31_0_DIO22_M 0x00400000 +#define GPIO_DOUT31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data output for DIO 21 +#define GPIO_DOUT31_0_DIO21 0x00200000 +#define GPIO_DOUT31_0_DIO21_BITN 21 +#define GPIO_DOUT31_0_DIO21_M 0x00200000 +#define GPIO_DOUT31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data output for DIO 20 +#define GPIO_DOUT31_0_DIO20 0x00100000 +#define GPIO_DOUT31_0_DIO20_BITN 20 +#define GPIO_DOUT31_0_DIO20_M 0x00100000 +#define GPIO_DOUT31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data output for DIO 19 +#define GPIO_DOUT31_0_DIO19 0x00080000 +#define GPIO_DOUT31_0_DIO19_BITN 19 +#define GPIO_DOUT31_0_DIO19_M 0x00080000 +#define GPIO_DOUT31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data output for DIO 18 +#define GPIO_DOUT31_0_DIO18 0x00040000 +#define GPIO_DOUT31_0_DIO18_BITN 18 +#define GPIO_DOUT31_0_DIO18_M 0x00040000 +#define GPIO_DOUT31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data output for DIO 17 +#define GPIO_DOUT31_0_DIO17 0x00020000 +#define GPIO_DOUT31_0_DIO17_BITN 17 +#define GPIO_DOUT31_0_DIO17_M 0x00020000 +#define GPIO_DOUT31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data output for DIO 16 +#define GPIO_DOUT31_0_DIO16 0x00010000 +#define GPIO_DOUT31_0_DIO16_BITN 16 +#define GPIO_DOUT31_0_DIO16_M 0x00010000 +#define GPIO_DOUT31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data output for DIO 15 +#define GPIO_DOUT31_0_DIO15 0x00008000 +#define GPIO_DOUT31_0_DIO15_BITN 15 +#define GPIO_DOUT31_0_DIO15_M 0x00008000 +#define GPIO_DOUT31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data output for DIO 14 +#define GPIO_DOUT31_0_DIO14 0x00004000 +#define GPIO_DOUT31_0_DIO14_BITN 14 +#define GPIO_DOUT31_0_DIO14_M 0x00004000 +#define GPIO_DOUT31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data output for DIO 13 +#define GPIO_DOUT31_0_DIO13 0x00002000 +#define GPIO_DOUT31_0_DIO13_BITN 13 +#define GPIO_DOUT31_0_DIO13_M 0x00002000 +#define GPIO_DOUT31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data output for DIO 12 +#define GPIO_DOUT31_0_DIO12 0x00001000 +#define GPIO_DOUT31_0_DIO12_BITN 12 +#define GPIO_DOUT31_0_DIO12_M 0x00001000 +#define GPIO_DOUT31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data output for DIO 11 +#define GPIO_DOUT31_0_DIO11 0x00000800 +#define GPIO_DOUT31_0_DIO11_BITN 11 +#define GPIO_DOUT31_0_DIO11_M 0x00000800 +#define GPIO_DOUT31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data output for DIO 10 +#define GPIO_DOUT31_0_DIO10 0x00000400 +#define GPIO_DOUT31_0_DIO10_BITN 10 +#define GPIO_DOUT31_0_DIO10_M 0x00000400 +#define GPIO_DOUT31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data output for DIO 9 +#define GPIO_DOUT31_0_DIO9 0x00000200 +#define GPIO_DOUT31_0_DIO9_BITN 9 +#define GPIO_DOUT31_0_DIO9_M 0x00000200 +#define GPIO_DOUT31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data output for DIO 8 +#define GPIO_DOUT31_0_DIO8 0x00000100 +#define GPIO_DOUT31_0_DIO8_BITN 8 +#define GPIO_DOUT31_0_DIO8_M 0x00000100 +#define GPIO_DOUT31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data output for DIO 7 +#define GPIO_DOUT31_0_DIO7 0x00000080 +#define GPIO_DOUT31_0_DIO7_BITN 7 +#define GPIO_DOUT31_0_DIO7_M 0x00000080 +#define GPIO_DOUT31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data output for DIO 6 +#define GPIO_DOUT31_0_DIO6 0x00000040 +#define GPIO_DOUT31_0_DIO6_BITN 6 +#define GPIO_DOUT31_0_DIO6_M 0x00000040 +#define GPIO_DOUT31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data output for DIO 5 +#define GPIO_DOUT31_0_DIO5 0x00000020 +#define GPIO_DOUT31_0_DIO5_BITN 5 +#define GPIO_DOUT31_0_DIO5_M 0x00000020 +#define GPIO_DOUT31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data output for DIO 4 +#define GPIO_DOUT31_0_DIO4 0x00000010 +#define GPIO_DOUT31_0_DIO4_BITN 4 +#define GPIO_DOUT31_0_DIO4_M 0x00000010 +#define GPIO_DOUT31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data output for DIO 3 +#define GPIO_DOUT31_0_DIO3 0x00000008 +#define GPIO_DOUT31_0_DIO3_BITN 3 +#define GPIO_DOUT31_0_DIO3_M 0x00000008 +#define GPIO_DOUT31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data output for DIO 2 +#define GPIO_DOUT31_0_DIO2 0x00000004 +#define GPIO_DOUT31_0_DIO2_BITN 2 +#define GPIO_DOUT31_0_DIO2_M 0x00000004 +#define GPIO_DOUT31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data output for DIO 1 +#define GPIO_DOUT31_0_DIO1 0x00000002 +#define GPIO_DOUT31_0_DIO1_BITN 1 +#define GPIO_DOUT31_0_DIO1_M 0x00000002 +#define GPIO_DOUT31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data output for DIO 0 +#define GPIO_DOUT31_0_DIO0 0x00000001 +#define GPIO_DOUT31_0_DIO0_BITN 0 +#define GPIO_DOUT31_0_DIO0_M 0x00000001 +#define GPIO_DOUT31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTSET31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Set bit 31 +#define GPIO_DOUTSET31_0_DIO31 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_BITN 31 +#define GPIO_DOUTSET31_0_DIO31_M 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Set bit 30 +#define GPIO_DOUTSET31_0_DIO30 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_BITN 30 +#define GPIO_DOUTSET31_0_DIO30_M 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Set bit 29 +#define GPIO_DOUTSET31_0_DIO29 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_BITN 29 +#define GPIO_DOUTSET31_0_DIO29_M 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Set bit 28 +#define GPIO_DOUTSET31_0_DIO28 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_BITN 28 +#define GPIO_DOUTSET31_0_DIO28_M 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Set bit 27 +#define GPIO_DOUTSET31_0_DIO27 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_BITN 27 +#define GPIO_DOUTSET31_0_DIO27_M 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Set bit 26 +#define GPIO_DOUTSET31_0_DIO26 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_BITN 26 +#define GPIO_DOUTSET31_0_DIO26_M 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Set bit 25 +#define GPIO_DOUTSET31_0_DIO25 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_BITN 25 +#define GPIO_DOUTSET31_0_DIO25_M 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Set bit 24 +#define GPIO_DOUTSET31_0_DIO24 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_BITN 24 +#define GPIO_DOUTSET31_0_DIO24_M 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Set bit 23 +#define GPIO_DOUTSET31_0_DIO23 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_BITN 23 +#define GPIO_DOUTSET31_0_DIO23_M 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Set bit 22 +#define GPIO_DOUTSET31_0_DIO22 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_BITN 22 +#define GPIO_DOUTSET31_0_DIO22_M 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Set bit 21 +#define GPIO_DOUTSET31_0_DIO21 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_BITN 21 +#define GPIO_DOUTSET31_0_DIO21_M 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Set bit 20 +#define GPIO_DOUTSET31_0_DIO20 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_BITN 20 +#define GPIO_DOUTSET31_0_DIO20_M 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Set bit 19 +#define GPIO_DOUTSET31_0_DIO19 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_BITN 19 +#define GPIO_DOUTSET31_0_DIO19_M 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Set bit 18 +#define GPIO_DOUTSET31_0_DIO18 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_BITN 18 +#define GPIO_DOUTSET31_0_DIO18_M 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Set bit 17 +#define GPIO_DOUTSET31_0_DIO17 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_BITN 17 +#define GPIO_DOUTSET31_0_DIO17_M 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Set bit 16 +#define GPIO_DOUTSET31_0_DIO16 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_BITN 16 +#define GPIO_DOUTSET31_0_DIO16_M 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Set bit 15 +#define GPIO_DOUTSET31_0_DIO15 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_BITN 15 +#define GPIO_DOUTSET31_0_DIO15_M 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Set bit 14 +#define GPIO_DOUTSET31_0_DIO14 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_BITN 14 +#define GPIO_DOUTSET31_0_DIO14_M 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Set bit 13 +#define GPIO_DOUTSET31_0_DIO13 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_BITN 13 +#define GPIO_DOUTSET31_0_DIO13_M 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Set bit 12 +#define GPIO_DOUTSET31_0_DIO12 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_BITN 12 +#define GPIO_DOUTSET31_0_DIO12_M 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Set bit 11 +#define GPIO_DOUTSET31_0_DIO11 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_BITN 11 +#define GPIO_DOUTSET31_0_DIO11_M 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Set bit 10 +#define GPIO_DOUTSET31_0_DIO10 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_BITN 10 +#define GPIO_DOUTSET31_0_DIO10_M 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Set bit 9 +#define GPIO_DOUTSET31_0_DIO9 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_BITN 9 +#define GPIO_DOUTSET31_0_DIO9_M 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Set bit 8 +#define GPIO_DOUTSET31_0_DIO8 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_BITN 8 +#define GPIO_DOUTSET31_0_DIO8_M 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Set bit 7 +#define GPIO_DOUTSET31_0_DIO7 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_BITN 7 +#define GPIO_DOUTSET31_0_DIO7_M 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Set bit 6 +#define GPIO_DOUTSET31_0_DIO6 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_BITN 6 +#define GPIO_DOUTSET31_0_DIO6_M 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Set bit 5 +#define GPIO_DOUTSET31_0_DIO5 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_BITN 5 +#define GPIO_DOUTSET31_0_DIO5_M 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Set bit 4 +#define GPIO_DOUTSET31_0_DIO4 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_BITN 4 +#define GPIO_DOUTSET31_0_DIO4_M 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Set bit 3 +#define GPIO_DOUTSET31_0_DIO3 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_BITN 3 +#define GPIO_DOUTSET31_0_DIO3_M 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Set bit 2 +#define GPIO_DOUTSET31_0_DIO2 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_BITN 2 +#define GPIO_DOUTSET31_0_DIO2_M 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Set bit 1 +#define GPIO_DOUTSET31_0_DIO1 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_BITN 1 +#define GPIO_DOUTSET31_0_DIO1_M 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Set bit 0 +#define GPIO_DOUTSET31_0_DIO0 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_BITN 0 +#define GPIO_DOUTSET31_0_DIO0_M 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTCLR31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Clears bit 31 +#define GPIO_DOUTCLR31_0_DIO31 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_BITN 31 +#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Clears bit 30 +#define GPIO_DOUTCLR31_0_DIO30 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_BITN 30 +#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Clears bit 29 +#define GPIO_DOUTCLR31_0_DIO29 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_BITN 29 +#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Clears bit 28 +#define GPIO_DOUTCLR31_0_DIO28 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_BITN 28 +#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Clears bit 27 +#define GPIO_DOUTCLR31_0_DIO27 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_BITN 27 +#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Clears bit 26 +#define GPIO_DOUTCLR31_0_DIO26 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_BITN 26 +#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Clears bit 25 +#define GPIO_DOUTCLR31_0_DIO25 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_BITN 25 +#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Clears bit 24 +#define GPIO_DOUTCLR31_0_DIO24 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_BITN 24 +#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Clears bit 23 +#define GPIO_DOUTCLR31_0_DIO23 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_BITN 23 +#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Clears bit 22 +#define GPIO_DOUTCLR31_0_DIO22 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_BITN 22 +#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Clears bit 21 +#define GPIO_DOUTCLR31_0_DIO21 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_BITN 21 +#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Clears bit 20 +#define GPIO_DOUTCLR31_0_DIO20 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_BITN 20 +#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Clears bit 19 +#define GPIO_DOUTCLR31_0_DIO19 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_BITN 19 +#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Clears bit 18 +#define GPIO_DOUTCLR31_0_DIO18 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_BITN 18 +#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Clears bit 17 +#define GPIO_DOUTCLR31_0_DIO17 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_BITN 17 +#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Clears bit 16 +#define GPIO_DOUTCLR31_0_DIO16 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_BITN 16 +#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Clears bit 15 +#define GPIO_DOUTCLR31_0_DIO15 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_BITN 15 +#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Clears bit 14 +#define GPIO_DOUTCLR31_0_DIO14 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_BITN 14 +#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Clears bit 13 +#define GPIO_DOUTCLR31_0_DIO13 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_BITN 13 +#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Clears bit 12 +#define GPIO_DOUTCLR31_0_DIO12 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_BITN 12 +#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Clears bit 11 +#define GPIO_DOUTCLR31_0_DIO11 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_BITN 11 +#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Clears bit 10 +#define GPIO_DOUTCLR31_0_DIO10 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_BITN 10 +#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Clears bit 9 +#define GPIO_DOUTCLR31_0_DIO9 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_BITN 9 +#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Clears bit 8 +#define GPIO_DOUTCLR31_0_DIO8 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_BITN 8 +#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Clears bit 7 +#define GPIO_DOUTCLR31_0_DIO7 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_BITN 7 +#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Clears bit 6 +#define GPIO_DOUTCLR31_0_DIO6 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_BITN 6 +#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Clears bit 5 +#define GPIO_DOUTCLR31_0_DIO5 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_BITN 5 +#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Clears bit 4 +#define GPIO_DOUTCLR31_0_DIO4 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_BITN 4 +#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Clears bit 3 +#define GPIO_DOUTCLR31_0_DIO3 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_BITN 3 +#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Clears bit 2 +#define GPIO_DOUTCLR31_0_DIO2 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_BITN 2 +#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Clears bit 1 +#define GPIO_DOUTCLR31_0_DIO1 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_BITN 1 +#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Clears bit 0 +#define GPIO_DOUTCLR31_0_DIO0 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_BITN 0 +#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTTGL31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Toggles bit 31 +#define GPIO_DOUTTGL31_0_DIO31 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_BITN 31 +#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Toggles bit 30 +#define GPIO_DOUTTGL31_0_DIO30 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_BITN 30 +#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Toggles bit 29 +#define GPIO_DOUTTGL31_0_DIO29 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_BITN 29 +#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Toggles bit 28 +#define GPIO_DOUTTGL31_0_DIO28 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_BITN 28 +#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Toggles bit 27 +#define GPIO_DOUTTGL31_0_DIO27 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_BITN 27 +#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Toggles bit 26 +#define GPIO_DOUTTGL31_0_DIO26 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_BITN 26 +#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Toggles bit 25 +#define GPIO_DOUTTGL31_0_DIO25 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_BITN 25 +#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Toggles bit 24 +#define GPIO_DOUTTGL31_0_DIO24 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_BITN 24 +#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Toggles bit 23 +#define GPIO_DOUTTGL31_0_DIO23 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_BITN 23 +#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Toggles bit 22 +#define GPIO_DOUTTGL31_0_DIO22 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_BITN 22 +#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Toggles bit 21 +#define GPIO_DOUTTGL31_0_DIO21 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_BITN 21 +#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Toggles bit 20 +#define GPIO_DOUTTGL31_0_DIO20 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_BITN 20 +#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Toggles bit 19 +#define GPIO_DOUTTGL31_0_DIO19 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_BITN 19 +#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Toggles bit 18 +#define GPIO_DOUTTGL31_0_DIO18 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_BITN 18 +#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Toggles bit 17 +#define GPIO_DOUTTGL31_0_DIO17 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_BITN 17 +#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Toggles bit 16 +#define GPIO_DOUTTGL31_0_DIO16 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_BITN 16 +#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Toggles bit 15 +#define GPIO_DOUTTGL31_0_DIO15 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_BITN 15 +#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Toggles bit 14 +#define GPIO_DOUTTGL31_0_DIO14 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_BITN 14 +#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Toggles bit 13 +#define GPIO_DOUTTGL31_0_DIO13 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_BITN 13 +#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Toggles bit 12 +#define GPIO_DOUTTGL31_0_DIO12 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_BITN 12 +#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Toggles bit 11 +#define GPIO_DOUTTGL31_0_DIO11 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_BITN 11 +#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Toggles bit 10 +#define GPIO_DOUTTGL31_0_DIO10 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_BITN 10 +#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Toggles bit 9 +#define GPIO_DOUTTGL31_0_DIO9 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_BITN 9 +#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Toggles bit 8 +#define GPIO_DOUTTGL31_0_DIO8 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_BITN 8 +#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Toggles bit 7 +#define GPIO_DOUTTGL31_0_DIO7 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_BITN 7 +#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Toggles bit 6 +#define GPIO_DOUTTGL31_0_DIO6 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_BITN 6 +#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Toggles bit 5 +#define GPIO_DOUTTGL31_0_DIO5 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_BITN 5 +#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Toggles bit 4 +#define GPIO_DOUTTGL31_0_DIO4 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_BITN 4 +#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Toggles bit 3 +#define GPIO_DOUTTGL31_0_DIO3 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_BITN 3 +#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Toggles bit 2 +#define GPIO_DOUTTGL31_0_DIO2 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_BITN 2 +#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Toggles bit 1 +#define GPIO_DOUTTGL31_0_DIO1 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_BITN 1 +#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Toggles bit 0 +#define GPIO_DOUTTGL31_0_DIO0 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_BITN 0 +#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DIN31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data input from DIO 31 +#define GPIO_DIN31_0_DIO31 0x80000000 +#define GPIO_DIN31_0_DIO31_BITN 31 +#define GPIO_DIN31_0_DIO31_M 0x80000000 +#define GPIO_DIN31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data input from DIO 30 +#define GPIO_DIN31_0_DIO30 0x40000000 +#define GPIO_DIN31_0_DIO30_BITN 30 +#define GPIO_DIN31_0_DIO30_M 0x40000000 +#define GPIO_DIN31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data input from DIO 29 +#define GPIO_DIN31_0_DIO29 0x20000000 +#define GPIO_DIN31_0_DIO29_BITN 29 +#define GPIO_DIN31_0_DIO29_M 0x20000000 +#define GPIO_DIN31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data input from DIO 28 +#define GPIO_DIN31_0_DIO28 0x10000000 +#define GPIO_DIN31_0_DIO28_BITN 28 +#define GPIO_DIN31_0_DIO28_M 0x10000000 +#define GPIO_DIN31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data input from DIO 27 +#define GPIO_DIN31_0_DIO27 0x08000000 +#define GPIO_DIN31_0_DIO27_BITN 27 +#define GPIO_DIN31_0_DIO27_M 0x08000000 +#define GPIO_DIN31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data input from DIO 26 +#define GPIO_DIN31_0_DIO26 0x04000000 +#define GPIO_DIN31_0_DIO26_BITN 26 +#define GPIO_DIN31_0_DIO26_M 0x04000000 +#define GPIO_DIN31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data input from DIO 25 +#define GPIO_DIN31_0_DIO25 0x02000000 +#define GPIO_DIN31_0_DIO25_BITN 25 +#define GPIO_DIN31_0_DIO25_M 0x02000000 +#define GPIO_DIN31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data input from DIO 24 +#define GPIO_DIN31_0_DIO24 0x01000000 +#define GPIO_DIN31_0_DIO24_BITN 24 +#define GPIO_DIN31_0_DIO24_M 0x01000000 +#define GPIO_DIN31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data input from DIO 23 +#define GPIO_DIN31_0_DIO23 0x00800000 +#define GPIO_DIN31_0_DIO23_BITN 23 +#define GPIO_DIN31_0_DIO23_M 0x00800000 +#define GPIO_DIN31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data input from DIO 22 +#define GPIO_DIN31_0_DIO22 0x00400000 +#define GPIO_DIN31_0_DIO22_BITN 22 +#define GPIO_DIN31_0_DIO22_M 0x00400000 +#define GPIO_DIN31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data input from DIO 21 +#define GPIO_DIN31_0_DIO21 0x00200000 +#define GPIO_DIN31_0_DIO21_BITN 21 +#define GPIO_DIN31_0_DIO21_M 0x00200000 +#define GPIO_DIN31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data input from DIO 20 +#define GPIO_DIN31_0_DIO20 0x00100000 +#define GPIO_DIN31_0_DIO20_BITN 20 +#define GPIO_DIN31_0_DIO20_M 0x00100000 +#define GPIO_DIN31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data input from DIO 19 +#define GPIO_DIN31_0_DIO19 0x00080000 +#define GPIO_DIN31_0_DIO19_BITN 19 +#define GPIO_DIN31_0_DIO19_M 0x00080000 +#define GPIO_DIN31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data input from DIO 18 +#define GPIO_DIN31_0_DIO18 0x00040000 +#define GPIO_DIN31_0_DIO18_BITN 18 +#define GPIO_DIN31_0_DIO18_M 0x00040000 +#define GPIO_DIN31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data input from DIO 17 +#define GPIO_DIN31_0_DIO17 0x00020000 +#define GPIO_DIN31_0_DIO17_BITN 17 +#define GPIO_DIN31_0_DIO17_M 0x00020000 +#define GPIO_DIN31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data input from DIO 16 +#define GPIO_DIN31_0_DIO16 0x00010000 +#define GPIO_DIN31_0_DIO16_BITN 16 +#define GPIO_DIN31_0_DIO16_M 0x00010000 +#define GPIO_DIN31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data input from DIO 15 +#define GPIO_DIN31_0_DIO15 0x00008000 +#define GPIO_DIN31_0_DIO15_BITN 15 +#define GPIO_DIN31_0_DIO15_M 0x00008000 +#define GPIO_DIN31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data input from DIO 14 +#define GPIO_DIN31_0_DIO14 0x00004000 +#define GPIO_DIN31_0_DIO14_BITN 14 +#define GPIO_DIN31_0_DIO14_M 0x00004000 +#define GPIO_DIN31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data input from DIO 13 +#define GPIO_DIN31_0_DIO13 0x00002000 +#define GPIO_DIN31_0_DIO13_BITN 13 +#define GPIO_DIN31_0_DIO13_M 0x00002000 +#define GPIO_DIN31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data input from DIO 12 +#define GPIO_DIN31_0_DIO12 0x00001000 +#define GPIO_DIN31_0_DIO12_BITN 12 +#define GPIO_DIN31_0_DIO12_M 0x00001000 +#define GPIO_DIN31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data input from DIO 11 +#define GPIO_DIN31_0_DIO11 0x00000800 +#define GPIO_DIN31_0_DIO11_BITN 11 +#define GPIO_DIN31_0_DIO11_M 0x00000800 +#define GPIO_DIN31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data input from DIO 10 +#define GPIO_DIN31_0_DIO10 0x00000400 +#define GPIO_DIN31_0_DIO10_BITN 10 +#define GPIO_DIN31_0_DIO10_M 0x00000400 +#define GPIO_DIN31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data input from DIO 9 +#define GPIO_DIN31_0_DIO9 0x00000200 +#define GPIO_DIN31_0_DIO9_BITN 9 +#define GPIO_DIN31_0_DIO9_M 0x00000200 +#define GPIO_DIN31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data input from DIO 8 +#define GPIO_DIN31_0_DIO8 0x00000100 +#define GPIO_DIN31_0_DIO8_BITN 8 +#define GPIO_DIN31_0_DIO8_M 0x00000100 +#define GPIO_DIN31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data input from DIO 7 +#define GPIO_DIN31_0_DIO7 0x00000080 +#define GPIO_DIN31_0_DIO7_BITN 7 +#define GPIO_DIN31_0_DIO7_M 0x00000080 +#define GPIO_DIN31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data input from DIO 6 +#define GPIO_DIN31_0_DIO6 0x00000040 +#define GPIO_DIN31_0_DIO6_BITN 6 +#define GPIO_DIN31_0_DIO6_M 0x00000040 +#define GPIO_DIN31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data input from DIO 5 +#define GPIO_DIN31_0_DIO5 0x00000020 +#define GPIO_DIN31_0_DIO5_BITN 5 +#define GPIO_DIN31_0_DIO5_M 0x00000020 +#define GPIO_DIN31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data input from DIO 4 +#define GPIO_DIN31_0_DIO4 0x00000010 +#define GPIO_DIN31_0_DIO4_BITN 4 +#define GPIO_DIN31_0_DIO4_M 0x00000010 +#define GPIO_DIN31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data input from DIO 3 +#define GPIO_DIN31_0_DIO3 0x00000008 +#define GPIO_DIN31_0_DIO3_BITN 3 +#define GPIO_DIN31_0_DIO3_M 0x00000008 +#define GPIO_DIN31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data input from DIO 2 +#define GPIO_DIN31_0_DIO2 0x00000004 +#define GPIO_DIN31_0_DIO2_BITN 2 +#define GPIO_DIN31_0_DIO2_M 0x00000004 +#define GPIO_DIN31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data input from DIO 1 +#define GPIO_DIN31_0_DIO1 0x00000002 +#define GPIO_DIN31_0_DIO1_BITN 1 +#define GPIO_DIN31_0_DIO1_M 0x00000002 +#define GPIO_DIN31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data input from DIO 0 +#define GPIO_DIN31_0_DIO0 0x00000001 +#define GPIO_DIN31_0_DIO0_BITN 0 +#define GPIO_DIN31_0_DIO0_M 0x00000001 +#define GPIO_DIN31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOE31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data output enable for DIO 31 +#define GPIO_DOE31_0_DIO31 0x80000000 +#define GPIO_DOE31_0_DIO31_BITN 31 +#define GPIO_DOE31_0_DIO31_M 0x80000000 +#define GPIO_DOE31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data output enable for DIO 30 +#define GPIO_DOE31_0_DIO30 0x40000000 +#define GPIO_DOE31_0_DIO30_BITN 30 +#define GPIO_DOE31_0_DIO30_M 0x40000000 +#define GPIO_DOE31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data output enable for DIO 29 +#define GPIO_DOE31_0_DIO29 0x20000000 +#define GPIO_DOE31_0_DIO29_BITN 29 +#define GPIO_DOE31_0_DIO29_M 0x20000000 +#define GPIO_DOE31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data output enable for DIO 28 +#define GPIO_DOE31_0_DIO28 0x10000000 +#define GPIO_DOE31_0_DIO28_BITN 28 +#define GPIO_DOE31_0_DIO28_M 0x10000000 +#define GPIO_DOE31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data output enable for DIO 27 +#define GPIO_DOE31_0_DIO27 0x08000000 +#define GPIO_DOE31_0_DIO27_BITN 27 +#define GPIO_DOE31_0_DIO27_M 0x08000000 +#define GPIO_DOE31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data output enable for DIO 26 +#define GPIO_DOE31_0_DIO26 0x04000000 +#define GPIO_DOE31_0_DIO26_BITN 26 +#define GPIO_DOE31_0_DIO26_M 0x04000000 +#define GPIO_DOE31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data output enable for DIO 25 +#define GPIO_DOE31_0_DIO25 0x02000000 +#define GPIO_DOE31_0_DIO25_BITN 25 +#define GPIO_DOE31_0_DIO25_M 0x02000000 +#define GPIO_DOE31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data output enable for DIO 24 +#define GPIO_DOE31_0_DIO24 0x01000000 +#define GPIO_DOE31_0_DIO24_BITN 24 +#define GPIO_DOE31_0_DIO24_M 0x01000000 +#define GPIO_DOE31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data output enable for DIO 23 +#define GPIO_DOE31_0_DIO23 0x00800000 +#define GPIO_DOE31_0_DIO23_BITN 23 +#define GPIO_DOE31_0_DIO23_M 0x00800000 +#define GPIO_DOE31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data output enable for DIO 22 +#define GPIO_DOE31_0_DIO22 0x00400000 +#define GPIO_DOE31_0_DIO22_BITN 22 +#define GPIO_DOE31_0_DIO22_M 0x00400000 +#define GPIO_DOE31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data output enable for DIO 21 +#define GPIO_DOE31_0_DIO21 0x00200000 +#define GPIO_DOE31_0_DIO21_BITN 21 +#define GPIO_DOE31_0_DIO21_M 0x00200000 +#define GPIO_DOE31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data output enable for DIO 20 +#define GPIO_DOE31_0_DIO20 0x00100000 +#define GPIO_DOE31_0_DIO20_BITN 20 +#define GPIO_DOE31_0_DIO20_M 0x00100000 +#define GPIO_DOE31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data output enable for DIO 19 +#define GPIO_DOE31_0_DIO19 0x00080000 +#define GPIO_DOE31_0_DIO19_BITN 19 +#define GPIO_DOE31_0_DIO19_M 0x00080000 +#define GPIO_DOE31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data output enable for DIO 18 +#define GPIO_DOE31_0_DIO18 0x00040000 +#define GPIO_DOE31_0_DIO18_BITN 18 +#define GPIO_DOE31_0_DIO18_M 0x00040000 +#define GPIO_DOE31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data output enable for DIO 17 +#define GPIO_DOE31_0_DIO17 0x00020000 +#define GPIO_DOE31_0_DIO17_BITN 17 +#define GPIO_DOE31_0_DIO17_M 0x00020000 +#define GPIO_DOE31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data output enable for DIO 16 +#define GPIO_DOE31_0_DIO16 0x00010000 +#define GPIO_DOE31_0_DIO16_BITN 16 +#define GPIO_DOE31_0_DIO16_M 0x00010000 +#define GPIO_DOE31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data output enable for DIO 15 +#define GPIO_DOE31_0_DIO15 0x00008000 +#define GPIO_DOE31_0_DIO15_BITN 15 +#define GPIO_DOE31_0_DIO15_M 0x00008000 +#define GPIO_DOE31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data output enable for DIO 14 +#define GPIO_DOE31_0_DIO14 0x00004000 +#define GPIO_DOE31_0_DIO14_BITN 14 +#define GPIO_DOE31_0_DIO14_M 0x00004000 +#define GPIO_DOE31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data output enable for DIO 13 +#define GPIO_DOE31_0_DIO13 0x00002000 +#define GPIO_DOE31_0_DIO13_BITN 13 +#define GPIO_DOE31_0_DIO13_M 0x00002000 +#define GPIO_DOE31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data output enable for DIO 12 +#define GPIO_DOE31_0_DIO12 0x00001000 +#define GPIO_DOE31_0_DIO12_BITN 12 +#define GPIO_DOE31_0_DIO12_M 0x00001000 +#define GPIO_DOE31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data output enable for DIO 11 +#define GPIO_DOE31_0_DIO11 0x00000800 +#define GPIO_DOE31_0_DIO11_BITN 11 +#define GPIO_DOE31_0_DIO11_M 0x00000800 +#define GPIO_DOE31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data output enable for DIO 10 +#define GPIO_DOE31_0_DIO10 0x00000400 +#define GPIO_DOE31_0_DIO10_BITN 10 +#define GPIO_DOE31_0_DIO10_M 0x00000400 +#define GPIO_DOE31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data output enable for DIO 9 +#define GPIO_DOE31_0_DIO9 0x00000200 +#define GPIO_DOE31_0_DIO9_BITN 9 +#define GPIO_DOE31_0_DIO9_M 0x00000200 +#define GPIO_DOE31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data output enable for DIO 8 +#define GPIO_DOE31_0_DIO8 0x00000100 +#define GPIO_DOE31_0_DIO8_BITN 8 +#define GPIO_DOE31_0_DIO8_M 0x00000100 +#define GPIO_DOE31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data output enable for DIO 7 +#define GPIO_DOE31_0_DIO7 0x00000080 +#define GPIO_DOE31_0_DIO7_BITN 7 +#define GPIO_DOE31_0_DIO7_M 0x00000080 +#define GPIO_DOE31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data output enable for DIO 6 +#define GPIO_DOE31_0_DIO6 0x00000040 +#define GPIO_DOE31_0_DIO6_BITN 6 +#define GPIO_DOE31_0_DIO6_M 0x00000040 +#define GPIO_DOE31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data output enable for DIO 5 +#define GPIO_DOE31_0_DIO5 0x00000020 +#define GPIO_DOE31_0_DIO5_BITN 5 +#define GPIO_DOE31_0_DIO5_M 0x00000020 +#define GPIO_DOE31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data output enable for DIO 4 +#define GPIO_DOE31_0_DIO4 0x00000010 +#define GPIO_DOE31_0_DIO4_BITN 4 +#define GPIO_DOE31_0_DIO4_M 0x00000010 +#define GPIO_DOE31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data output enable for DIO 3 +#define GPIO_DOE31_0_DIO3 0x00000008 +#define GPIO_DOE31_0_DIO3_BITN 3 +#define GPIO_DOE31_0_DIO3_M 0x00000008 +#define GPIO_DOE31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data output enable for DIO 2 +#define GPIO_DOE31_0_DIO2 0x00000004 +#define GPIO_DOE31_0_DIO2_BITN 2 +#define GPIO_DOE31_0_DIO2_M 0x00000004 +#define GPIO_DOE31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data output enable for DIO 1 +#define GPIO_DOE31_0_DIO1 0x00000002 +#define GPIO_DOE31_0_DIO1_BITN 1 +#define GPIO_DOE31_0_DIO1_M 0x00000002 +#define GPIO_DOE31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data output enable for DIO 0 +#define GPIO_DOE31_0_DIO0 0x00000001 +#define GPIO_DOE31_0_DIO0_BITN 0 +#define GPIO_DOE31_0_DIO0_M 0x00000001 +#define GPIO_DOE31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_EVFLAGS31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Event for DIO 31 +#define GPIO_EVFLAGS31_0_DIO31 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_BITN 31 +#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Event for DIO 30 +#define GPIO_EVFLAGS31_0_DIO30 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_BITN 30 +#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Event for DIO 29 +#define GPIO_EVFLAGS31_0_DIO29 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_BITN 29 +#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Event for DIO 28 +#define GPIO_EVFLAGS31_0_DIO28 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_BITN 28 +#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Event for DIO 27 +#define GPIO_EVFLAGS31_0_DIO27 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_BITN 27 +#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Event for DIO 26 +#define GPIO_EVFLAGS31_0_DIO26 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_BITN 26 +#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Event for DIO 25 +#define GPIO_EVFLAGS31_0_DIO25 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_BITN 25 +#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Event for DIO 24 +#define GPIO_EVFLAGS31_0_DIO24 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_BITN 24 +#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Event for DIO 23 +#define GPIO_EVFLAGS31_0_DIO23 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_BITN 23 +#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Event for DIO 22 +#define GPIO_EVFLAGS31_0_DIO22 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_BITN 22 +#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Event for DIO 21 +#define GPIO_EVFLAGS31_0_DIO21 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_BITN 21 +#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Event for DIO 20 +#define GPIO_EVFLAGS31_0_DIO20 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_BITN 20 +#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Event for DIO 19 +#define GPIO_EVFLAGS31_0_DIO19 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_BITN 19 +#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Event for DIO 18 +#define GPIO_EVFLAGS31_0_DIO18 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_BITN 18 +#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Event for DIO 17 +#define GPIO_EVFLAGS31_0_DIO17 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_BITN 17 +#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Event for DIO 16 +#define GPIO_EVFLAGS31_0_DIO16 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_BITN 16 +#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Event for DIO 15 +#define GPIO_EVFLAGS31_0_DIO15 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_BITN 15 +#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Event for DIO 14 +#define GPIO_EVFLAGS31_0_DIO14 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_BITN 14 +#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Event for DIO 13 +#define GPIO_EVFLAGS31_0_DIO13 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_BITN 13 +#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Event for DIO 12 +#define GPIO_EVFLAGS31_0_DIO12 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_BITN 12 +#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Event for DIO 11 +#define GPIO_EVFLAGS31_0_DIO11 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_BITN 11 +#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Event for DIO 10 +#define GPIO_EVFLAGS31_0_DIO10 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_BITN 10 +#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Event for DIO 9 +#define GPIO_EVFLAGS31_0_DIO9 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_BITN 9 +#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Event for DIO 8 +#define GPIO_EVFLAGS31_0_DIO8 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_BITN 8 +#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Event for DIO 7 +#define GPIO_EVFLAGS31_0_DIO7 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_BITN 7 +#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Event for DIO 6 +#define GPIO_EVFLAGS31_0_DIO6 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_BITN 6 +#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Event for DIO 5 +#define GPIO_EVFLAGS31_0_DIO5 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_BITN 5 +#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Event for DIO 4 +#define GPIO_EVFLAGS31_0_DIO4 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_BITN 4 +#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Event for DIO 3 +#define GPIO_EVFLAGS31_0_DIO3 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_BITN 3 +#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Event for DIO 2 +#define GPIO_EVFLAGS31_0_DIO2 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_BITN 2 +#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Event for DIO 1 +#define GPIO_EVFLAGS31_0_DIO1 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_BITN 1 +#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Event for DIO 0 +#define GPIO_EVFLAGS31_0_DIO0 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_BITN 0 +#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_S 0 + + +#endif // __GPIO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpt.h new file mode 100644 index 0000000..710edd8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpt.h @@ -0,0 +1,1686 @@ +/****************************************************************************** +* Filename: hw_gpt_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_GPT_H__ +#define __HW_GPT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// GPT component +// +//***************************************************************************** +// Configuration +#define GPT_O_CFG 0x00000000 + +// Timer A Mode +#define GPT_O_TAMR 0x00000004 + +// Timer B Mode +#define GPT_O_TBMR 0x00000008 + +// Control +#define GPT_O_CTL 0x0000000C + +// Synch Register +#define GPT_O_SYNC 0x00000010 + +// Interrupt Mask +#define GPT_O_IMR 0x00000018 + +// Raw Interrupt Status +#define GPT_O_RIS 0x0000001C + +// Masked Interrupt Status +#define GPT_O_MIS 0x00000020 + +// Interrupt Clear +#define GPT_O_ICLR 0x00000024 + +// Timer A Interval Load Register +#define GPT_O_TAILR 0x00000028 + +// Timer B Interval Load Register +#define GPT_O_TBILR 0x0000002C + +// Timer A Match Register +#define GPT_O_TAMATCHR 0x00000030 + +// Timer B Match Register +#define GPT_O_TBMATCHR 0x00000034 + +// Timer A Pre-scale +#define GPT_O_TAPR 0x00000038 + +// Timer B Pre-scale +#define GPT_O_TBPR 0x0000003C + +// Timer A Pre-scale Match +#define GPT_O_TAPMR 0x00000040 + +// Timer B Pre-scale Match +#define GPT_O_TBPMR 0x00000044 + +// Timer A Register +#define GPT_O_TAR 0x00000048 + +// Timer B Register +#define GPT_O_TBR 0x0000004C + +// Timer A Value +#define GPT_O_TAV 0x00000050 + +// Timer B Value +#define GPT_O_TBV 0x00000054 + +// Timer A Pre-scale Snap-shot +#define GPT_O_TAPS 0x0000005C + +// Timer B Pre-scale Snap-shot +#define GPT_O_TBPS 0x00000060 + +// Timer A Pre-scale Value +#define GPT_O_TAPV 0x00000064 + +// Timer B Pre-scale Value +#define GPT_O_TBPV 0x00000068 + +// DMA Event +#define GPT_O_DMAEV 0x0000006C + +// Peripheral Version +#define GPT_O_VERSION 0x00000FB0 + +// Combined CCP Output +#define GPT_O_ANDCCP 0x00000FB4 + +//***************************************************************************** +// +// Register: GPT_O_CFG +// +//***************************************************************************** +// Field: [2:0] CFG +// +// GPT Configuration +// 0x2- 0x3 - Reserved +// 0x5- 0x7 - Reserved +// ENUMs: +// 16BIT_TIMER 16-bit timer configuration. +// Configure for two 16-bit +// timers. +// Also see TAMR.TAMR and +// TBMR.TBMR. +// 32BIT_TIMER 32-bit timer configuration +#define GPT_CFG_CFG_W 3 +#define GPT_CFG_CFG_M 0x00000007 +#define GPT_CFG_CFG_S 0 +#define GPT_CFG_CFG_16BIT_TIMER 0x00000004 +#define GPT_CFG_CFG_32BIT_TIMER 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_TAMR +// +//***************************************************************************** +// Field: [15:13] TCACT +// +// Timer Compare Action Select +// ENUMs: +// CLRSET_ON_TO Clear CCP output pin immediately and set on +// Time-Out +// SETCLR_ON_TO Set CCP output pin immediately and clear on +// Time-Out +// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on +// Time-Out +// SETTOG_ON_TO Set CCP output pin immediately and toggle on +// Time-Out +// SET_ON_TO Set CCP output pin on Time-Out +// CLR_ON_TO Clear CCP output pin on Time-Out +// TOG_ON_TO Toggle State on Time-Out +// DIS_CMP Disable compare operations +#define GPT_TAMR_TCACT_W 3 +#define GPT_TAMR_TCACT_M 0x0000E000 +#define GPT_TAMR_TCACT_S 13 +#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TAMR_TCACT_DIS_CMP 0x00000000 + +// Field: [12] TACINTD +// +// One-Shot/Periodic Interrupt Disable +// ENUMs: +// DIS_TO_INTR Time-out interrupt are disabled +// EN_TO_INTR Time-out interrupt function as normal +#define GPT_TAMR_TACINTD 0x00001000 +#define GPT_TAMR_TACINTD_BITN 12 +#define GPT_TAMR_TACINTD_M 0x00001000 +#define GPT_TAMR_TACINTD_S 12 +#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 +#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 + +// Field: [11] TAPLO +// +// GPTM Timer A PWM Legacy Operation +// +// 0 Legacy operation with CCP pin driven Low when the TAILR +// register is reloaded after the timer reaches 0. +// +// 1 CCP is driven High when the TAILR register is reloaded after the timer +// reaches 0. +// +// This bit is only valid in PWM mode. +// ENUMs: +// CCP_ON_TO CCP output pin is set to 1 on time-out +// LEGACY Legacy operation +#define GPT_TAMR_TAPLO 0x00000800 +#define GPT_TAMR_TAPLO_BITN 11 +#define GPT_TAMR_TAPLO_M 0x00000800 +#define GPT_TAMR_TAPLO_S 11 +#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 +#define GPT_TAMR_TAPLO_LEGACY 0x00000000 + +// Field: [10] TAMRSU +// +// Timer A Match Register Update mode +// +// This bit defines when the TAMATCHR and TAPR registers are updated. +// +// If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and +// TAPR are updated when the timer is enabled. +// If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and +// TAPR are updated according to the configuration of this bit. +// ENUMs: +// TOUPDATE Update TAMATCHR and TAPR, if used, on the next +// time-out. +// CYCLEUPDATE Update TAMATCHR and TAPR, if used, on the next +// cycle. +#define GPT_TAMR_TAMRSU 0x00000400 +#define GPT_TAMR_TAMRSU_BITN 10 +#define GPT_TAMR_TAMRSU_M 0x00000400 +#define GPT_TAMR_TAMRSU_S 10 +#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 +#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 + +// Field: [9] TAPWMIE +// +// GPTM Timer A PWM Interrupt Enable +// This bit enables interrupts in PWM mode on rising, falling, or both edges of +// the CCP output, as defined by the CTL.TAEVENT +// In addition, when this bit is set and a capture event occurs, Timer A +// automatically generates triggers to the DMA if the trigger capability is +// enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit +// respectively. +// +// 0 Capture event interrupt is disabled. +// 1 Capture event interrupt is enabled. +// This bit is only valid in PWM mode. +// ENUMs: +// EN Interrupt is enabled. This bit is only valid in +// PWM mode. +// DIS Interrupt is disabled. +#define GPT_TAMR_TAPWMIE 0x00000200 +#define GPT_TAMR_TAPWMIE_BITN 9 +#define GPT_TAMR_TAPWMIE_M 0x00000200 +#define GPT_TAMR_TAPWMIE_S 9 +#define GPT_TAMR_TAPWMIE_EN 0x00000200 +#define GPT_TAMR_TAPWMIE_DIS 0x00000000 + +// Field: [8] TAILD +// +// GPT Timer A PWM Interval Load Write +// ENUMs: +// TOUPDATE Update the TAR register with the value in the +// TAILR register on the next timeout. If the +// prescaler is used, update the TAPS register +// with the value in the TAPR register on the next +// timeout. +// CYCLEUPDATE Update the TAR register with the value in the +// TAILR register on the next clock cycle. If the +// pre-scaler is used, update the TAPS register +// with the value in the TAPR register on the next +// clock cycle. +#define GPT_TAMR_TAILD 0x00000100 +#define GPT_TAMR_TAILD_BITN 8 +#define GPT_TAMR_TAILD_M 0x00000100 +#define GPT_TAMR_TAILD_S 8 +#define GPT_TAMR_TAILD_TOUPDATE 0x00000100 +#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 + +// Field: [7] TASNAPS +// +// GPT Timer A Snap-Shot Mode +// ENUMs: +// EN If Timer A is configured in the periodic mode, the +// actual free-running value of Timer A is loaded +// at the time-out event into the GPT Timer A +// (TAR) register. +// DIS Snap-shot mode is disabled. +#define GPT_TAMR_TASNAPS 0x00000080 +#define GPT_TAMR_TASNAPS_BITN 7 +#define GPT_TAMR_TASNAPS_M 0x00000080 +#define GPT_TAMR_TASNAPS_S 7 +#define GPT_TAMR_TASNAPS_EN 0x00000080 +#define GPT_TAMR_TASNAPS_DIS 0x00000000 + +// Field: [6] TAWOT +// +// GPT Timer A Wait-On-Trigger +// ENUMs: +// WAIT If Timer A is enabled (CTL.TAEN = 1), Timer A does +// not begin counting until it receives a trigger +// from the timer in the previous position in the +// daisy chain. This bit must be clear for GPT +// Module 0, Timer A. This function is valid for +// one-shot, periodic, and PWM modes +// NOWAIT Timer A begins counting as soon as it is enabled. +#define GPT_TAMR_TAWOT 0x00000040 +#define GPT_TAMR_TAWOT_BITN 6 +#define GPT_TAMR_TAWOT_M 0x00000040 +#define GPT_TAMR_TAWOT_S 6 +#define GPT_TAMR_TAWOT_WAIT 0x00000040 +#define GPT_TAMR_TAWOT_NOWAIT 0x00000000 + +// Field: [5] TAMIE +// +// GPT Timer A Match Interrupt Enable +// ENUMs: +// EN An interrupt is generated when the match value in +// TAMATCHR is reached in the one-shot and +// periodic modes. +// DIS The match interrupt is disabled for match events. +// Additionally, output triggers on match events +// are prevented. +#define GPT_TAMR_TAMIE 0x00000020 +#define GPT_TAMR_TAMIE_BITN 5 +#define GPT_TAMR_TAMIE_M 0x00000020 +#define GPT_TAMR_TAMIE_S 5 +#define GPT_TAMR_TAMIE_EN 0x00000020 +#define GPT_TAMR_TAMIE_DIS 0x00000000 + +// Field: [4] TACDIR +// +// GPT Timer A Count Direction +// ENUMs: +// UP The timer counts up. When counting up, the timer +// starts from a value of 0x0. +// DOWN The timer counts down. +#define GPT_TAMR_TACDIR 0x00000010 +#define GPT_TAMR_TACDIR_BITN 4 +#define GPT_TAMR_TACDIR_M 0x00000010 +#define GPT_TAMR_TACDIR_S 4 +#define GPT_TAMR_TACDIR_UP 0x00000010 +#define GPT_TAMR_TACDIR_DOWN 0x00000000 + +// Field: [3] TAAMS +// +// GPT Timer A Alternate Mode +// +// Note: To enable PWM mode, you must also clear TACM and then configure TAMR +// field to 0x2. +// ENUMs: +// PWM PWM mode is enabled +// CAP_COMP Capture/Compare mode is enabled. +#define GPT_TAMR_TAAMS 0x00000008 +#define GPT_TAMR_TAAMS_BITN 3 +#define GPT_TAMR_TAAMS_M 0x00000008 +#define GPT_TAMR_TAAMS_S 3 +#define GPT_TAMR_TAAMS_PWM 0x00000008 +#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 + +// Field: [2] TACM +// +// GPT Timer A Capture Mode +// ENUMs: +// EDGTIME Edge-Time mode +// EDGCNT Edge-Count mode +#define GPT_TAMR_TACM 0x00000004 +#define GPT_TAMR_TACM_BITN 2 +#define GPT_TAMR_TACM_M 0x00000004 +#define GPT_TAMR_TACM_S 2 +#define GPT_TAMR_TACM_EDGTIME 0x00000004 +#define GPT_TAMR_TACM_EDGCNT 0x00000000 + +// Field: [1:0] TAMR +// +// GPT Timer A Mode +// +// 0x0 Reserved +// 0x1 One-Shot Timer mode +// 0x2 Periodic Timer mode +// 0x3 Capture mode +// The Timer mode is based on the timer configuration defined by bits 2:0 in +// the CFG register +// ENUMs: +// CAPTURE Capture mode +// PERIODIC Periodic Timer mode +// ONE_SHOT One-Shot Timer mode +#define GPT_TAMR_TAMR_W 2 +#define GPT_TAMR_TAMR_M 0x00000003 +#define GPT_TAMR_TAMR_S 0 +#define GPT_TAMR_TAMR_CAPTURE 0x00000003 +#define GPT_TAMR_TAMR_PERIODIC 0x00000002 +#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 + +//***************************************************************************** +// +// Register: GPT_O_TBMR +// +//***************************************************************************** +// Field: [15:13] TCACT +// +// Timer Compare Action Select +// ENUMs: +// CLRSET_ON_TO Clear CCP output pin immediately and set on +// Time-Out +// SETCLR_ON_TO Set CCP output pin immediately and clear on +// Time-Out +// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on +// Time-Out +// SETTOG_ON_TO Set CCP output pin immediately and toggle on +// Time-Out +// SET_ON_TO Set CCP output pin on Time-Out +// CLR_ON_TO Clear CCP output pin on Time-Out +// TOG_ON_TO Toggle State on Time-Out +// DIS_CMP Disable compare operations +#define GPT_TBMR_TCACT_W 3 +#define GPT_TBMR_TCACT_M 0x0000E000 +#define GPT_TBMR_TCACT_S 13 +#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TBMR_TCACT_DIS_CMP 0x00000000 + +// Field: [12] TBCINTD +// +// One-Shot/Periodic Interrupt Mode +// ENUMs: +// DIS_TO_INTR Mask Time-Out Interrupt +// EN_TO_INTR Normal Time-Out Interrupt +#define GPT_TBMR_TBCINTD 0x00001000 +#define GPT_TBMR_TBCINTD_BITN 12 +#define GPT_TBMR_TBCINTD_M 0x00001000 +#define GPT_TBMR_TBCINTD_S 12 +#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 +#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 + +// Field: [11] TBPLO +// +// GPTM Timer B PWM Legacy Operation +// +// 0 Legacy operation with CCP pin driven Low when the TBILR +// register is reloaded after the timer reaches 0. +// +// 1 CCP is driven High when the TBILR register is reloaded after the timer +// reaches 0. +// +// This bit is only valid in PWM mode. +// ENUMs: +// CCP_ON_TO CCP output pin is set to 1 on time-out +// LEGACY Legacy operation +#define GPT_TBMR_TBPLO 0x00000800 +#define GPT_TBMR_TBPLO_BITN 11 +#define GPT_TBMR_TBPLO_M 0x00000800 +#define GPT_TBMR_TBPLO_S 11 +#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 +#define GPT_TBMR_TBPLO_LEGACY 0x00000000 + +// Field: [10] TBMRSU +// +// Timer B Match Register Update mode +// +// This bit defines when the TBMATCHR and TBPR registers are updated +// +// If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR +// and TBPR are updated when the timer is enabled. +// If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR +// and TBPR are updated according to the configuration of this bit. +// ENUMs: +// TOUPDATE Update TBMATCHR and TBPR, if used, on the next +// time-out. +// CYCLEUPDATE Update TBMATCHR and TBPR, if used, on the next +// cycle. +#define GPT_TBMR_TBMRSU 0x00000400 +#define GPT_TBMR_TBMRSU_BITN 10 +#define GPT_TBMR_TBMRSU_M 0x00000400 +#define GPT_TBMR_TBMRSU_S 10 +#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 +#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 + +// Field: [9] TBPWMIE +// +// GPTM Timer B PWM Interrupt Enable +// This bit enables interrupts in PWM mode on rising, falling, or both edges of +// the CCP output, as defined by the CTL.TBEVENT +// In addition, when this bit is set and a capture event occurs, Timer A +// automatically generates triggers to the DMA if the trigger capability is +// enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit +// respectively. +// +// 0 Capture event interrupt is disabled. +// 1 Capture event interrupt is enabled. +// This bit is only valid in PWM mode. +// ENUMs: +// EN Interrupt is enabled. This bit is only valid in +// PWM mode. +// DIS Interrupt is disabled. +#define GPT_TBMR_TBPWMIE 0x00000200 +#define GPT_TBMR_TBPWMIE_BITN 9 +#define GPT_TBMR_TBPWMIE_M 0x00000200 +#define GPT_TBMR_TBPWMIE_S 9 +#define GPT_TBMR_TBPWMIE_EN 0x00000200 +#define GPT_TBMR_TBPWMIE_DIS 0x00000000 + +// Field: [8] TBILD +// +// GPT Timer B PWM Interval Load Write +// ENUMs: +// TOUPDATE Update the TBR register with the value in the +// TBILR register on the next timeout. If the +// prescaler is used, update the TBPS register +// with the value in the TBPR register on the next +// timeout. +// CYCLEUPDATE Update the TBR register with the value in the +// TBILR register on the next clock cycle. If the +// pre-scaler is used, update the TBPS register +// with the value in the TBPR register on the next +// clock cycle. +#define GPT_TBMR_TBILD 0x00000100 +#define GPT_TBMR_TBILD_BITN 8 +#define GPT_TBMR_TBILD_M 0x00000100 +#define GPT_TBMR_TBILD_S 8 +#define GPT_TBMR_TBILD_TOUPDATE 0x00000100 +#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 + +// Field: [7] TBSNAPS +// +// GPT Timer B Snap-Shot Mode +// ENUMs: +// EN If Timer B is configured in the periodic mode +// DIS Snap-shot mode is disabled. +#define GPT_TBMR_TBSNAPS 0x00000080 +#define GPT_TBMR_TBSNAPS_BITN 7 +#define GPT_TBMR_TBSNAPS_M 0x00000080 +#define GPT_TBMR_TBSNAPS_S 7 +#define GPT_TBMR_TBSNAPS_EN 0x00000080 +#define GPT_TBMR_TBSNAPS_DIS 0x00000000 + +// Field: [6] TBWOT +// +// GPT Timer B Wait-On-Trigger +// ENUMs: +// WAIT If Timer B is enabled (CTL.TBEN is set), Timer B +// does not begin counting until it receives a +// trigger from the timer in the previous position +// in the daisy chain. This function is valid for +// one-shot, periodic, and PWM modes +// NOWAIT Timer B begins counting as soon as it is enabled. +#define GPT_TBMR_TBWOT 0x00000040 +#define GPT_TBMR_TBWOT_BITN 6 +#define GPT_TBMR_TBWOT_M 0x00000040 +#define GPT_TBMR_TBWOT_S 6 +#define GPT_TBMR_TBWOT_WAIT 0x00000040 +#define GPT_TBMR_TBWOT_NOWAIT 0x00000000 + +// Field: [5] TBMIE +// +// GPT Timer B Match Interrupt Enable. +// ENUMs: +// EN An interrupt is generated when the match value in +// the TBMATCHR register is reached in the +// one-shot and periodic modes. +// DIS The match interrupt is disabled for match events. +// Additionally, output triggers on match events +// are prevented. +#define GPT_TBMR_TBMIE 0x00000020 +#define GPT_TBMR_TBMIE_BITN 5 +#define GPT_TBMR_TBMIE_M 0x00000020 +#define GPT_TBMR_TBMIE_S 5 +#define GPT_TBMR_TBMIE_EN 0x00000020 +#define GPT_TBMR_TBMIE_DIS 0x00000000 + +// Field: [4] TBCDIR +// +// GPT Timer B Count Direction +// ENUMs: +// UP The timer counts up. When counting up, the timer +// starts from a value of 0x0. +// DOWN The timer counts down. +#define GPT_TBMR_TBCDIR 0x00000010 +#define GPT_TBMR_TBCDIR_BITN 4 +#define GPT_TBMR_TBCDIR_M 0x00000010 +#define GPT_TBMR_TBCDIR_S 4 +#define GPT_TBMR_TBCDIR_UP 0x00000010 +#define GPT_TBMR_TBCDIR_DOWN 0x00000000 + +// Field: [3] TBAMS +// +// GPT Timer B Alternate Mode +// +// Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR +// field to 0x2. +// ENUMs: +// PWM PWM mode is enabled +// CAP_COMP Capture/Compare mode is enabled. +#define GPT_TBMR_TBAMS 0x00000008 +#define GPT_TBMR_TBAMS_BITN 3 +#define GPT_TBMR_TBAMS_M 0x00000008 +#define GPT_TBMR_TBAMS_S 3 +#define GPT_TBMR_TBAMS_PWM 0x00000008 +#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 + +// Field: [2] TBCM +// +// GPT Timer B Capture Mode +// ENUMs: +// EDGTIME Edge-Time mode +// EDGCNT Edge-Count mode +#define GPT_TBMR_TBCM 0x00000004 +#define GPT_TBMR_TBCM_BITN 2 +#define GPT_TBMR_TBCM_M 0x00000004 +#define GPT_TBMR_TBCM_S 2 +#define GPT_TBMR_TBCM_EDGTIME 0x00000004 +#define GPT_TBMR_TBCM_EDGCNT 0x00000000 + +// Field: [1:0] TBMR +// +// GPT Timer B Mode +// +// 0x0 Reserved +// 0x1 One-Shot Timer mode +// 0x2 Periodic Timer mode +// 0x3 Capture mode +// The Timer mode is based on the timer configuration defined by bits 2:0 in +// the CFG register +// ENUMs: +// CAPTURE Capture mode +// PERIODIC Periodic Timer mode +// ONE_SHOT One-Shot Timer mode +#define GPT_TBMR_TBMR_W 2 +#define GPT_TBMR_TBMR_M 0x00000003 +#define GPT_TBMR_TBMR_S 0 +#define GPT_TBMR_TBMR_CAPTURE 0x00000003 +#define GPT_TBMR_TBMR_PERIODIC 0x00000002 +#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 + +//***************************************************************************** +// +// Register: GPT_O_CTL +// +//***************************************************************************** +// Field: [14] TBPWML +// +// GPT Timer B PWM Output Level +// +// 0: Output is unaffected. +// 1: Output is inverted. +// ENUMs: +// INVERTED Inverted +// NORMAL Not inverted +#define GPT_CTL_TBPWML 0x00004000 +#define GPT_CTL_TBPWML_BITN 14 +#define GPT_CTL_TBPWML_M 0x00004000 +#define GPT_CTL_TBPWML_S 14 +#define GPT_CTL_TBPWML_INVERTED 0x00004000 +#define GPT_CTL_TBPWML_NORMAL 0x00000000 + +// Field: [11:10] TBEVENT +// +// GPT Timer B Event Mode +// +// The values in this register are defined as follows: +// Value Description +// 0x0 Positive edge +// 0x1 Negative edge +// 0x2 Reserved +// 0x3 Both edges +// Note: If PWM output inversion is enabled, edge detection interrupt +// behavior is reversed. Thus, if a positive-edge interrupt trigger +// has been set and the PWM inversion generates a postive +// edge, no event-trigger interrupt asserts. Instead, the interrupt +// is generated on the negative edge of the PWM signal. +// ENUMs: +// BOTH Both edges +// NEG Negative edge +// POS Positive edge +#define GPT_CTL_TBEVENT_W 2 +#define GPT_CTL_TBEVENT_M 0x00000C00 +#define GPT_CTL_TBEVENT_S 10 +#define GPT_CTL_TBEVENT_BOTH 0x00000C00 +#define GPT_CTL_TBEVENT_NEG 0x00000400 +#define GPT_CTL_TBEVENT_POS 0x00000000 + +// Field: [9] TBSTALL +// +// GPT Timer B Stall Enable +// ENUMs: +// EN Timer B freezes counting while the processor is +// halted by the debugger. +// DIS Timer B continues counting while the processor is +// halted by the debugger. +#define GPT_CTL_TBSTALL 0x00000200 +#define GPT_CTL_TBSTALL_BITN 9 +#define GPT_CTL_TBSTALL_M 0x00000200 +#define GPT_CTL_TBSTALL_S 9 +#define GPT_CTL_TBSTALL_EN 0x00000200 +#define GPT_CTL_TBSTALL_DIS 0x00000000 + +// Field: [8] TBEN +// +// GPT Timer B Enable +// ENUMs: +// EN Timer B is enabled and begins counting or the +// capture logic is enabled based on CFG register. +// DIS Timer B is disabled. +#define GPT_CTL_TBEN 0x00000100 +#define GPT_CTL_TBEN_BITN 8 +#define GPT_CTL_TBEN_M 0x00000100 +#define GPT_CTL_TBEN_S 8 +#define GPT_CTL_TBEN_EN 0x00000100 +#define GPT_CTL_TBEN_DIS 0x00000000 + +// Field: [6] TAPWML +// +// GPT Timer A PWM Output Level +// ENUMs: +// INVERTED Inverted +// NORMAL Not inverted +#define GPT_CTL_TAPWML 0x00000040 +#define GPT_CTL_TAPWML_BITN 6 +#define GPT_CTL_TAPWML_M 0x00000040 +#define GPT_CTL_TAPWML_S 6 +#define GPT_CTL_TAPWML_INVERTED 0x00000040 +#define GPT_CTL_TAPWML_NORMAL 0x00000000 + +// Field: [3:2] TAEVENT +// +// GPT Timer A Event Mode +// +// The values in this register are defined as follows: +// Value Description +// 0x0 Positive edge +// 0x1 Negative edge +// 0x2 Reserved +// 0x3 Both edges +// Note: If PWM output inversion is enabled, edge detection interrupt +// behavior is reversed. Thus, if a positive-edge interrupt trigger +// has been set and the PWM inversion generates a postive +// edge, no event-trigger interrupt asserts. Instead, the interrupt +// is generated on the negative edge of the PWM signal. +// ENUMs: +// BOTH Both edges +// NEG Negative edge +// POS Positive edge +#define GPT_CTL_TAEVENT_W 2 +#define GPT_CTL_TAEVENT_M 0x0000000C +#define GPT_CTL_TAEVENT_S 2 +#define GPT_CTL_TAEVENT_BOTH 0x0000000C +#define GPT_CTL_TAEVENT_NEG 0x00000004 +#define GPT_CTL_TAEVENT_POS 0x00000000 + +// Field: [1] TASTALL +// +// GPT Timer A Stall Enable +// ENUMs: +// EN Timer A freezes counting while the processor is +// halted by the debugger. +// DIS Timer A continues counting while the processor is +// halted by the debugger. +#define GPT_CTL_TASTALL 0x00000002 +#define GPT_CTL_TASTALL_BITN 1 +#define GPT_CTL_TASTALL_M 0x00000002 +#define GPT_CTL_TASTALL_S 1 +#define GPT_CTL_TASTALL_EN 0x00000002 +#define GPT_CTL_TASTALL_DIS 0x00000000 + +// Field: [0] TAEN +// +// GPT Timer A Enable +// ENUMs: +// EN Timer A is enabled and begins counting or the +// capture logic is enabled based on the CFG +// register. +// DIS Timer A is disabled. +#define GPT_CTL_TAEN 0x00000001 +#define GPT_CTL_TAEN_BITN 0 +#define GPT_CTL_TAEN_M 0x00000001 +#define GPT_CTL_TAEN_S 0 +#define GPT_CTL_TAEN_EN 0x00000001 +#define GPT_CTL_TAEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_SYNC +// +//***************************************************************************** +// Field: [7:6] SYNC3 +// +// Synchronize GPT Timer 3. +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT3 is triggered +// TIMERB A timeout event for Timer B of GPT3 is triggered +// TIMERA A timeout event for Timer A of GPT3 is triggered +// NOSYNC No Sync. GPT3 is not affected. +#define GPT_SYNC_SYNC3_W 2 +#define GPT_SYNC_SYNC3_M 0x000000C0 +#define GPT_SYNC_SYNC3_S 6 +#define GPT_SYNC_SYNC3_BOTH 0x000000C0 +#define GPT_SYNC_SYNC3_TIMERB 0x00000080 +#define GPT_SYNC_SYNC3_TIMERA 0x00000040 +#define GPT_SYNC_SYNC3_NOSYNC 0x00000000 + +// Field: [5:4] SYNC2 +// +// Synchronize GPT Timer 2. +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT2 is triggered +// TIMERB A timeout event for Timer B of GPT2 is triggered +// TIMERA A timeout event for Timer A of GPT2 is triggered +// NOSYNC No Sync. GPT2 is not affected. +#define GPT_SYNC_SYNC2_W 2 +#define GPT_SYNC_SYNC2_M 0x00000030 +#define GPT_SYNC_SYNC2_S 4 +#define GPT_SYNC_SYNC2_BOTH 0x00000030 +#define GPT_SYNC_SYNC2_TIMERB 0x00000020 +#define GPT_SYNC_SYNC2_TIMERA 0x00000010 +#define GPT_SYNC_SYNC2_NOSYNC 0x00000000 + +// Field: [3:2] SYNC1 +// +// Synchronize GPT Timer 1 +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT1 is triggered +// TIMERB A timeout event for Timer B of GPT1 is triggered +// TIMERA A timeout event for Timer A of GPT1 is triggered +// NOSYNC No Sync. GPT1 is not affected. +#define GPT_SYNC_SYNC1_W 2 +#define GPT_SYNC_SYNC1_M 0x0000000C +#define GPT_SYNC_SYNC1_S 2 +#define GPT_SYNC_SYNC1_BOTH 0x0000000C +#define GPT_SYNC_SYNC1_TIMERB 0x00000008 +#define GPT_SYNC_SYNC1_TIMERA 0x00000004 +#define GPT_SYNC_SYNC1_NOSYNC 0x00000000 + +// Field: [1:0] SYNC0 +// +// Synchronize GPT Timer 0 +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT0 is triggered +// TIMERB A timeout event for Timer B of GPT0 is triggered +// TIMERA A timeout event for Timer A of GPT0 is triggered +// NOSYNC No Sync. GPT0 is not affected. +#define GPT_SYNC_SYNC0_W 2 +#define GPT_SYNC_SYNC0_M 0x00000003 +#define GPT_SYNC_SYNC0_S 0 +#define GPT_SYNC_SYNC0_BOTH 0x00000003 +#define GPT_SYNC_SYNC0_TIMERB 0x00000002 +#define GPT_SYNC_SYNC0_TIMERA 0x00000001 +#define GPT_SYNC_SYNC0_NOSYNC 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_IMR +// +//***************************************************************************** +// Field: [13] DMABIM +// +// Enabling this bit will make the RIS.DMABRIS interrupt propagate to +// MIS.DMABMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_DMABIM 0x00002000 +#define GPT_IMR_DMABIM_BITN 13 +#define GPT_IMR_DMABIM_M 0x00002000 +#define GPT_IMR_DMABIM_S 13 +#define GPT_IMR_DMABIM_EN 0x00002000 +#define GPT_IMR_DMABIM_DIS 0x00000000 + +// Field: [11] TBMIM +// +// Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TBMIM 0x00000800 +#define GPT_IMR_TBMIM_BITN 11 +#define GPT_IMR_TBMIM_M 0x00000800 +#define GPT_IMR_TBMIM_S 11 +#define GPT_IMR_TBMIM_EN 0x00000800 +#define GPT_IMR_TBMIM_DIS 0x00000000 + +// Field: [10] CBEIM +// +// Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CBEIM 0x00000400 +#define GPT_IMR_CBEIM_BITN 10 +#define GPT_IMR_CBEIM_M 0x00000400 +#define GPT_IMR_CBEIM_S 10 +#define GPT_IMR_CBEIM_EN 0x00000400 +#define GPT_IMR_CBEIM_DIS 0x00000000 + +// Field: [9] CBMIM +// +// Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CBMIM 0x00000200 +#define GPT_IMR_CBMIM_BITN 9 +#define GPT_IMR_CBMIM_M 0x00000200 +#define GPT_IMR_CBMIM_S 9 +#define GPT_IMR_CBMIM_EN 0x00000200 +#define GPT_IMR_CBMIM_DIS 0x00000000 + +// Field: [8] TBTOIM +// +// Enabling this bit will make the RIS.TBTORIS interrupt propagate to +// MIS.TBTOMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TBTOIM 0x00000100 +#define GPT_IMR_TBTOIM_BITN 8 +#define GPT_IMR_TBTOIM_M 0x00000100 +#define GPT_IMR_TBTOIM_S 8 +#define GPT_IMR_TBTOIM_EN 0x00000100 +#define GPT_IMR_TBTOIM_DIS 0x00000000 + +// Field: [5] DMAAIM +// +// Enabling this bit will make the RIS.DMAARIS interrupt propagate to +// MIS.DMAAMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_DMAAIM 0x00000020 +#define GPT_IMR_DMAAIM_BITN 5 +#define GPT_IMR_DMAAIM_M 0x00000020 +#define GPT_IMR_DMAAIM_S 5 +#define GPT_IMR_DMAAIM_EN 0x00000020 +#define GPT_IMR_DMAAIM_DIS 0x00000000 + +// Field: [4] TAMIM +// +// Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TAMIM 0x00000010 +#define GPT_IMR_TAMIM_BITN 4 +#define GPT_IMR_TAMIM_M 0x00000010 +#define GPT_IMR_TAMIM_S 4 +#define GPT_IMR_TAMIM_EN 0x00000010 +#define GPT_IMR_TAMIM_DIS 0x00000000 + +// Field: [2] CAEIM +// +// Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CAEIM 0x00000004 +#define GPT_IMR_CAEIM_BITN 2 +#define GPT_IMR_CAEIM_M 0x00000004 +#define GPT_IMR_CAEIM_S 2 +#define GPT_IMR_CAEIM_EN 0x00000004 +#define GPT_IMR_CAEIM_DIS 0x00000000 + +// Field: [1] CAMIM +// +// Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CAMIM 0x00000002 +#define GPT_IMR_CAMIM_BITN 1 +#define GPT_IMR_CAMIM_M 0x00000002 +#define GPT_IMR_CAMIM_S 1 +#define GPT_IMR_CAMIM_EN 0x00000002 +#define GPT_IMR_CAMIM_DIS 0x00000000 + +// Field: [0] TATOIM +// +// Enabling this bit will make the RIS.TATORIS interrupt propagate to +// MIS.TATOMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TATOIM 0x00000001 +#define GPT_IMR_TATOIM_BITN 0 +#define GPT_IMR_TATOIM_M 0x00000001 +#define GPT_IMR_TATOIM_S 0 +#define GPT_IMR_TATOIM_EN 0x00000001 +#define GPT_IMR_TATOIM_DIS 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_RIS +// +//***************************************************************************** +// Field: [13] DMABRIS +// +// GPT Timer B DMA Done Raw Interrupt Status +// +// 0: Transfer has not completed +// 1: Transfer has completed +#define GPT_RIS_DMABRIS 0x00002000 +#define GPT_RIS_DMABRIS_BITN 13 +#define GPT_RIS_DMABRIS_M 0x00002000 +#define GPT_RIS_DMABRIS_S 13 + +// Field: [11] TBMRIS +// +// GPT Timer B Match Raw Interrupt +// +// 0: The match value has not been reached +// 1: The match value is reached. +// +// TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR +// have been reached when configured in one-shot or periodic mode. +#define GPT_RIS_TBMRIS 0x00000800 +#define GPT_RIS_TBMRIS_BITN 11 +#define GPT_RIS_TBMRIS_M 0x00000800 +#define GPT_RIS_TBMRIS_S 11 + +// Field: [10] CBERIS +// +// GPT Timer B Capture Mode Event Raw Interrupt +// +// 0: The event has not occured. +// 1: The event has occured. +// +// This interrupt asserts when the subtimer is configured in Input Edge-Time +// mode +#define GPT_RIS_CBERIS 0x00000400 +#define GPT_RIS_CBERIS_BITN 10 +#define GPT_RIS_CBERIS_M 0x00000400 +#define GPT_RIS_CBERIS_S 10 + +// Field: [9] CBMRIS +// +// GPT Timer B Capture Mode Match Raw Interrupt +// +// 0: The capture mode match for Timer B has not occurred. +// 1: A capture mode match has occurred for Timer B. This interrupt +// asserts when the values in the TBR and TBPR +// match the values in the TBMATCHR and TBPMR +// when configured in Input Edge-Time mode. +// +// This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. +#define GPT_RIS_CBMRIS 0x00000200 +#define GPT_RIS_CBMRIS_BITN 9 +#define GPT_RIS_CBMRIS_M 0x00000200 +#define GPT_RIS_CBMRIS_S 9 + +// Field: [8] TBTORIS +// +// GPT Timer B Time-out Raw Interrupt +// +// 0: Timer B has not timed out +// 1: Timer B has timed out. +// +// This interrupt is asserted when a one-shot or periodic mode timer reaches +// its count limit. The count limit is 0 or the value loaded into TBILR, +// depending on the count direction. +#define GPT_RIS_TBTORIS 0x00000100 +#define GPT_RIS_TBTORIS_BITN 8 +#define GPT_RIS_TBTORIS_M 0x00000100 +#define GPT_RIS_TBTORIS_S 8 + +// Field: [5] DMAARIS +// +// GPT Timer A DMA Done Raw Interrupt Status +// +// 0: Transfer has not completed +// 1: Transfer has completed +#define GPT_RIS_DMAARIS 0x00000020 +#define GPT_RIS_DMAARIS_BITN 5 +#define GPT_RIS_DMAARIS_M 0x00000020 +#define GPT_RIS_DMAARIS_S 5 + +// Field: [4] TAMRIS +// +// GPT Timer A Match Raw Interrupt +// +// 0: The match value has not been reached +// 1: The match value is reached. +// +// TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR +// have been reached when configured in one-shot or periodic mode. +#define GPT_RIS_TAMRIS 0x00000010 +#define GPT_RIS_TAMRIS_BITN 4 +#define GPT_RIS_TAMRIS_M 0x00000010 +#define GPT_RIS_TAMRIS_S 4 + +// Field: [2] CAERIS +// +// GPT Timer A Capture Mode Event Raw Interrupt +// +// 0: The event has not occured. +// 1: The event has occured. +// +// This interrupt asserts when the subtimer is configured in Input Edge-Time +// mode +#define GPT_RIS_CAERIS 0x00000004 +#define GPT_RIS_CAERIS_BITN 2 +#define GPT_RIS_CAERIS_M 0x00000004 +#define GPT_RIS_CAERIS_S 2 + +// Field: [1] CAMRIS +// +// GPT Timer A Capture Mode Match Raw Interrupt +// +// 0: The capture mode match for Timer A has not occurred. +// 1: A capture mode match has occurred for Timer A. This interrupt +// asserts when the values in the TAR and TAPR +// match the values in the TAMATCHR and TAPMR +// when configured in Input Edge-Time mode. +// +// This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. +#define GPT_RIS_CAMRIS 0x00000002 +#define GPT_RIS_CAMRIS_BITN 1 +#define GPT_RIS_CAMRIS_M 0x00000002 +#define GPT_RIS_CAMRIS_S 1 + +// Field: [0] TATORIS +// +// GPT Timer A Time-out Raw Interrupt +// +// 0: Timer A has not timed out +// 1: Timer A has timed out. +// +// This interrupt is asserted when a one-shot or periodic mode timer reaches +// its count limit. The count limit is 0 or the value loaded into TAILR, +// depending on the count direction. +#define GPT_RIS_TATORIS 0x00000001 +#define GPT_RIS_TATORIS_BITN 0 +#define GPT_RIS_TATORIS_M 0x00000001 +#define GPT_RIS_TATORIS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_MIS +// +//***************************************************************************** +// Field: [13] DMABMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 +#define GPT_MIS_DMABMIS 0x00002000 +#define GPT_MIS_DMABMIS_BITN 13 +#define GPT_MIS_DMABMIS_M 0x00002000 +#define GPT_MIS_DMABMIS_S 13 + +// Field: [11] TBMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 +#define GPT_MIS_TBMMIS 0x00000800 +#define GPT_MIS_TBMMIS_BITN 11 +#define GPT_MIS_TBMMIS_M 0x00000800 +#define GPT_MIS_TBMMIS_S 11 + +// Field: [10] CBEMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 +#define GPT_MIS_CBEMIS 0x00000400 +#define GPT_MIS_CBEMIS_BITN 10 +#define GPT_MIS_CBEMIS_M 0x00000400 +#define GPT_MIS_CBEMIS_S 10 + +// Field: [9] CBMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 +#define GPT_MIS_CBMMIS 0x00000200 +#define GPT_MIS_CBMMIS_BITN 9 +#define GPT_MIS_CBMMIS_M 0x00000200 +#define GPT_MIS_CBMMIS_S 9 + +// Field: [8] TBTOMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 +#define GPT_MIS_TBTOMIS 0x00000100 +#define GPT_MIS_TBTOMIS_BITN 8 +#define GPT_MIS_TBTOMIS_M 0x00000100 +#define GPT_MIS_TBTOMIS_S 8 + +// Field: [5] DMAAMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 +#define GPT_MIS_DMAAMIS 0x00000020 +#define GPT_MIS_DMAAMIS_BITN 5 +#define GPT_MIS_DMAAMIS_M 0x00000020 +#define GPT_MIS_DMAAMIS_S 5 + +// Field: [4] TAMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 +#define GPT_MIS_TAMMIS 0x00000010 +#define GPT_MIS_TAMMIS_BITN 4 +#define GPT_MIS_TAMMIS_M 0x00000010 +#define GPT_MIS_TAMMIS_S 4 + +// Field: [2] CAEMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 +#define GPT_MIS_CAEMIS 0x00000004 +#define GPT_MIS_CAEMIS_BITN 2 +#define GPT_MIS_CAEMIS_M 0x00000004 +#define GPT_MIS_CAEMIS_S 2 + +// Field: [1] CAMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 +#define GPT_MIS_CAMMIS 0x00000002 +#define GPT_MIS_CAMMIS_BITN 1 +#define GPT_MIS_CAMMIS_M 0x00000002 +#define GPT_MIS_CAMMIS_S 1 + +// Field: [0] TATOMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 +#define GPT_MIS_TATOMIS 0x00000001 +#define GPT_MIS_TATOMIS_BITN 0 +#define GPT_MIS_TATOMIS_M 0x00000001 +#define GPT_MIS_TATOMIS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_ICLR +// +//***************************************************************************** +// Field: [13] DMABINT +// +// 0: Do nothing. +// 1: Clear RIS.DMABRIS and MIS.DMABMIS +#define GPT_ICLR_DMABINT 0x00002000 +#define GPT_ICLR_DMABINT_BITN 13 +#define GPT_ICLR_DMABINT_M 0x00002000 +#define GPT_ICLR_DMABINT_S 13 + +// Field: [11] TBMCINT +// +// 0: Do nothing. +// 1: Clear RIS.TBMRIS and MIS.TBMMIS +#define GPT_ICLR_TBMCINT 0x00000800 +#define GPT_ICLR_TBMCINT_BITN 11 +#define GPT_ICLR_TBMCINT_M 0x00000800 +#define GPT_ICLR_TBMCINT_S 11 + +// Field: [10] CBECINT +// +// 0: Do nothing. +// 1: Clear RIS.CBERIS and MIS.CBEMIS +#define GPT_ICLR_CBECINT 0x00000400 +#define GPT_ICLR_CBECINT_BITN 10 +#define GPT_ICLR_CBECINT_M 0x00000400 +#define GPT_ICLR_CBECINT_S 10 + +// Field: [9] CBMCINT +// +// 0: Do nothing. +// 1: Clear RIS.CBMRIS and MIS.CBMMIS +#define GPT_ICLR_CBMCINT 0x00000200 +#define GPT_ICLR_CBMCINT_BITN 9 +#define GPT_ICLR_CBMCINT_M 0x00000200 +#define GPT_ICLR_CBMCINT_S 9 + +// Field: [8] TBTOCINT +// +// 0: Do nothing. +// 1: Clear RIS.TBTORIS and MIS.TBTOMIS +#define GPT_ICLR_TBTOCINT 0x00000100 +#define GPT_ICLR_TBTOCINT_BITN 8 +#define GPT_ICLR_TBTOCINT_M 0x00000100 +#define GPT_ICLR_TBTOCINT_S 8 + +// Field: [5] DMAAINT +// +// 0: Do nothing. +// 1: Clear RIS.DMAARIS and MIS.DMAAMIS +#define GPT_ICLR_DMAAINT 0x00000020 +#define GPT_ICLR_DMAAINT_BITN 5 +#define GPT_ICLR_DMAAINT_M 0x00000020 +#define GPT_ICLR_DMAAINT_S 5 + +// Field: [4] TAMCINT +// +// 0: Do nothing. +// 1: Clear RIS.TAMRIS and MIS.TAMMIS +#define GPT_ICLR_TAMCINT 0x00000010 +#define GPT_ICLR_TAMCINT_BITN 4 +#define GPT_ICLR_TAMCINT_M 0x00000010 +#define GPT_ICLR_TAMCINT_S 4 + +// Field: [2] CAECINT +// +// 0: Do nothing. +// 1: Clear RIS.CAERIS and MIS.CAEMIS +#define GPT_ICLR_CAECINT 0x00000004 +#define GPT_ICLR_CAECINT_BITN 2 +#define GPT_ICLR_CAECINT_M 0x00000004 +#define GPT_ICLR_CAECINT_S 2 + +// Field: [1] CAMCINT +// +// 0: Do nothing. +// 1: Clear RIS.CAMRIS and MIS.CAMMIS +#define GPT_ICLR_CAMCINT 0x00000002 +#define GPT_ICLR_CAMCINT_BITN 1 +#define GPT_ICLR_CAMCINT_M 0x00000002 +#define GPT_ICLR_CAMCINT_S 1 + +// Field: [0] TATOCINT +// +// 0: Do nothing. +// 1: Clear RIS.TATORIS and MIS.TATOMIS +#define GPT_ICLR_TATOCINT 0x00000001 +#define GPT_ICLR_TATOCINT_BITN 0 +#define GPT_ICLR_TATOCINT_M 0x00000001 +#define GPT_ICLR_TATOCINT_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAILR +// +//***************************************************************************** +// Field: [31:0] TAILR +// +// GPT Timer A Interval Load Register +// +// Writing this field loads the counter for Timer A. A read returns the current +// value of TAILR. +#define GPT_TAILR_TAILR_W 32 +#define GPT_TAILR_TAILR_M 0xFFFFFFFF +#define GPT_TAILR_TAILR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBILR +// +//***************************************************************************** +// Field: [31:0] TBILR +// +// GPT Timer B Interval Load Register +// +// Writing this field loads the counter for Timer B. A read returns the current +// value of TBILR. +#define GPT_TBILR_TBILR_W 32 +#define GPT_TBILR_TBILR_M 0xFFFFFFFF +#define GPT_TBILR_TBILR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAMATCHR +// +//***************************************************************************** +// Field: [31:0] TAMATCHR +// +// GPT Timer A Match Register +#define GPT_TAMATCHR_TAMATCHR_W 32 +#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF +#define GPT_TAMATCHR_TAMATCHR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBMATCHR +// +//***************************************************************************** +// Field: [15:0] TBMATCHR +// +// GPT Timer B Match Register +#define GPT_TBMATCHR_TBMATCHR_W 16 +#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF +#define GPT_TBMATCHR_TBMATCHR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPR +// +//***************************************************************************** +// Field: [7:0] TAPSR +// +// Timer A Pre-scale. +// +// Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: +// +// 0: Prescaler ratio = 1 +// 1: Prescaler ratio = 2 +// 2: Prescaler ratio = 3 +// ... +// 255: Prescaler ratio = 256 +#define GPT_TAPR_TAPSR_W 8 +#define GPT_TAPR_TAPSR_M 0x000000FF +#define GPT_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPR +// +//***************************************************************************** +// Field: [7:0] TBPSR +// +// Timer B Pre-scale. +// +// Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: +// +// 0: Prescaler ratio = 1 +// 1: Prescaler ratio = 2 +// 2: Prescaler ratio = 3 +// ... +// 255: Prescaler ratio = 256 +#define GPT_TBPR_TBPSR_W 8 +#define GPT_TBPR_TBPSR_M 0x000000FF +#define GPT_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPMR +// +//***************************************************************************** +// Field: [7:0] TAPSMR +// +// GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. +#define GPT_TAPMR_TAPSMR_W 8 +#define GPT_TAPMR_TAPSMR_M 0x000000FF +#define GPT_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPMR +// +//***************************************************************************** +// Field: [7:0] TBPSMR +// +// GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits +// 23 to 16. +#define GPT_TBPMR_TBPSMR_W 8 +#define GPT_TBPMR_TBPSMR_M 0x000000FF +#define GPT_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAR +// +//***************************************************************************** +// Field: [31:0] TAR +// +// GPT Timer A Register +// +// Based on the value in the register field TAMR.TAILD, this register is +// updated with the value from TAILR register either on the next cycle or on +// the next timeout. +// +// A read returns the current value of the Timer A Count Register, in all cases +// except for Input Edge count and Timer modes. +// In the Input Edge Count Mode, this register contains the number of edges +// that have occurred. In the Input Edge Time mode, this register contains the +// time at which the last edge event took place. +#define GPT_TAR_TAR_W 32 +#define GPT_TAR_TAR_M 0xFFFFFFFF +#define GPT_TAR_TAR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBR +// +//***************************************************************************** +// Field: [31:0] TBR +// +// GPT Timer B Register +// +// Based on the value in the register field TBMR.TBILD, this register is +// updated with the value from TBILR register either on the next cycle or on +// the next timeout. +// +// A read returns the current value of the Timer B Count Register, in all cases +// except for Input Edge count and Timer modes. +// In the Input Edge Count Mode, this register contains the number of edges +// that have occurred. In the Input Edge Time mode, this register contains the +// time at which the last edge event took place. +#define GPT_TBR_TBR_W 32 +#define GPT_TBR_TBR_M 0xFFFFFFFF +#define GPT_TBR_TBR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAV +// +//***************************************************************************** +// Field: [31:0] TAV +// +// GPT Timer A Register +// A read returns the current, free-running value of Timer A in all modes. +// When written, the value written into this register is loaded into the +// TAR register on the next clock cycle. +// Note: In 16-bit mode, only the lower 16-bits of this +// register can be written with a new value. Writes to the prescaler bits have +// no effect +#define GPT_TAV_TAV_W 32 +#define GPT_TAV_TAV_M 0xFFFFFFFF +#define GPT_TAV_TAV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBV +// +//***************************************************************************** +// Field: [31:0] TBV +// +// GPT Timer B Register +// A read returns the current, free-running value of Timer B in all modes. +// When written, the value written into this register is loaded into the +// TBR register on the next clock cycle. +// Note: In 16-bit mode, only the lower 16-bits of this +// register can be written with a new value. Writes to the prescaler bits have +// no effect +#define GPT_TBV_TBV_W 32 +#define GPT_TBV_TBV_M 0xFFFFFFFF +#define GPT_TBV_TBV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPS +// +//***************************************************************************** +// Field: [7:0] PSS +// +// GPT Timer A Pre-scaler +#define GPT_TAPS_PSS_W 8 +#define GPT_TAPS_PSS_M 0x000000FF +#define GPT_TAPS_PSS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPS +// +//***************************************************************************** +// Field: [7:0] PSS +// +// GPT Timer B Pre-scaler +#define GPT_TBPS_PSS_W 8 +#define GPT_TBPS_PSS_M 0x000000FF +#define GPT_TBPS_PSS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPV +// +//***************************************************************************** +// Field: [7:0] PSV +// +// GPT Timer A Pre-scaler Value +#define GPT_TAPV_PSV_W 8 +#define GPT_TAPV_PSV_M 0x000000FF +#define GPT_TAPV_PSV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPV +// +//***************************************************************************** +// Field: [7:0] PSV +// +// GPT Timer B Pre-scaler Value +#define GPT_TBPV_PSV_W 8 +#define GPT_TBPV_PSV_M 0x000000FF +#define GPT_TBPV_PSV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_DMAEV +// +//***************************************************************************** +// Field: [11] TBMDMAEN +// +// GPT Timer B Match DMA Trigger Enable +#define GPT_DMAEV_TBMDMAEN 0x00000800 +#define GPT_DMAEV_TBMDMAEN_BITN 11 +#define GPT_DMAEV_TBMDMAEN_M 0x00000800 +#define GPT_DMAEV_TBMDMAEN_S 11 + +// Field: [10] CBEDMAEN +// +// GPT Timer B Capture Event DMA Trigger Enable +#define GPT_DMAEV_CBEDMAEN 0x00000400 +#define GPT_DMAEV_CBEDMAEN_BITN 10 +#define GPT_DMAEV_CBEDMAEN_M 0x00000400 +#define GPT_DMAEV_CBEDMAEN_S 10 + +// Field: [9] CBMDMAEN +// +// GPT Timer B Capture Match DMA Trigger Enable +#define GPT_DMAEV_CBMDMAEN 0x00000200 +#define GPT_DMAEV_CBMDMAEN_BITN 9 +#define GPT_DMAEV_CBMDMAEN_M 0x00000200 +#define GPT_DMAEV_CBMDMAEN_S 9 + +// Field: [8] TBTODMAEN +// +// GPT Timer B Time-Out DMA Trigger Enable +#define GPT_DMAEV_TBTODMAEN 0x00000100 +#define GPT_DMAEV_TBTODMAEN_BITN 8 +#define GPT_DMAEV_TBTODMAEN_M 0x00000100 +#define GPT_DMAEV_TBTODMAEN_S 8 + +// Field: [4] TAMDMAEN +// +// GPT Timer A Match DMA Trigger Enable +#define GPT_DMAEV_TAMDMAEN 0x00000010 +#define GPT_DMAEV_TAMDMAEN_BITN 4 +#define GPT_DMAEV_TAMDMAEN_M 0x00000010 +#define GPT_DMAEV_TAMDMAEN_S 4 + +// Field: [2] CAEDMAEN +// +// GPT Timer A Capture Event DMA Trigger Enable +#define GPT_DMAEV_CAEDMAEN 0x00000004 +#define GPT_DMAEV_CAEDMAEN_BITN 2 +#define GPT_DMAEV_CAEDMAEN_M 0x00000004 +#define GPT_DMAEV_CAEDMAEN_S 2 + +// Field: [1] CAMDMAEN +// +// GPT Timer A Capture Match DMA Trigger Enable +#define GPT_DMAEV_CAMDMAEN 0x00000002 +#define GPT_DMAEV_CAMDMAEN_BITN 1 +#define GPT_DMAEV_CAMDMAEN_M 0x00000002 +#define GPT_DMAEV_CAMDMAEN_S 1 + +// Field: [0] TATODMAEN +// +// GPT Timer A Time-Out DMA Trigger Enable +#define GPT_DMAEV_TATODMAEN 0x00000001 +#define GPT_DMAEV_TATODMAEN_BITN 0 +#define GPT_DMAEV_TATODMAEN_M 0x00000001 +#define GPT_DMAEV_TATODMAEN_S 0 + +//***************************************************************************** +// +// Register: GPT_O_VERSION +// +//***************************************************************************** +// Field: [31:0] VERSION +// +// Timer Revision. +#define GPT_VERSION_VERSION_W 32 +#define GPT_VERSION_VERSION_M 0xFFFFFFFF +#define GPT_VERSION_VERSION_S 0 + +//***************************************************************************** +// +// Register: GPT_O_ANDCCP +// +//***************************************************************************** +// Field: [0] CCP_AND_EN +// +// Enables AND operation of the CCP outputs for timers A and B. +// +// 0 : PWM outputs of Timer A and Timer B are the internal generated PWM +// signals of the respective timers. +// 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM +// signals and Timer B PWM ouput is Timer B PWM signal only. +#define GPT_ANDCCP_CCP_AND_EN 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_BITN 0 +#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_S 0 + + +#endif // __GPT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2c.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2c.h new file mode 100644 index 0000000..9d0d30e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2c.h @@ -0,0 +1,728 @@ +/****************************************************************************** +* Filename: hw_i2c_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// I2C component +// +//***************************************************************************** +// Slave Own Address +#define I2C_O_SOAR 0x00000000 + +// Slave Status +#define I2C_O_SSTAT 0x00000004 + +// Slave Control +#define I2C_O_SCTL 0x00000004 + +// Slave Data +#define I2C_O_SDR 0x00000008 + +// Slave Interrupt Mask +#define I2C_O_SIMR 0x0000000C + +// Slave Raw Interrupt Status +#define I2C_O_SRIS 0x00000010 + +// Slave Masked Interrupt Status +#define I2C_O_SMIS 0x00000014 + +// Slave Interrupt Clear +#define I2C_O_SICR 0x00000018 + +// Master Salve Address +#define I2C_O_MSA 0x00000800 + +// Master Status +#define I2C_O_MSTAT 0x00000804 + +// Master Control +#define I2C_O_MCTRL 0x00000804 + +// Master Data +#define I2C_O_MDR 0x00000808 + +// I2C Master Timer Period +#define I2C_O_MTPR 0x0000080C + +// Master Interrupt Mask +#define I2C_O_MIMR 0x00000810 + +// Master Raw Interrupt Status +#define I2C_O_MRIS 0x00000814 + +// Master Masked Interrupt Status +#define I2C_O_MMIS 0x00000818 + +// Master Interrupt Clear +#define I2C_O_MICR 0x0000081C + +// Master Configuration +#define I2C_O_MCR 0x00000820 + +//***************************************************************************** +// +// Register: I2C_O_SOAR +// +//***************************************************************************** +// Field: [6:0] OAR +// +// I2C slave own address +// This field specifies bits a6 through a0 of the slave address. +#define I2C_SOAR_OAR_W 7 +#define I2C_SOAR_OAR_M 0x0000007F +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SSTAT +// +//***************************************************************************** +// Field: [2] FBR +// +// First byte received +// +// 0: The first byte has not been received. +// 1: The first byte following the slave's own address has been received. +// +// This bit is only valid when the RREQ bit is set and is automatically cleared +// when data has been read from the SDR register. +// Note: This bit is not used for slave transmit operations. +#define I2C_SSTAT_FBR 0x00000004 +#define I2C_SSTAT_FBR_BITN 2 +#define I2C_SSTAT_FBR_M 0x00000004 +#define I2C_SSTAT_FBR_S 2 + +// Field: [1] TREQ +// +// Transmit request +// +// 0: No outstanding transmit request. +// 1: The I2C controller has been addressed as a slave transmitter and is using +// clock stretching to delay the master until data has been written to the SDR +// register. +#define I2C_SSTAT_TREQ 0x00000002 +#define I2C_SSTAT_TREQ_BITN 1 +#define I2C_SSTAT_TREQ_M 0x00000002 +#define I2C_SSTAT_TREQ_S 1 + +// Field: [0] RREQ +// +// Receive request +// +// 0: No outstanding receive data +// 1: The I2C controller has outstanding receive data from the I2C master and +// is using clock stretching to delay the master until data has been read from +// the SDR register. +#define I2C_SSTAT_RREQ 0x00000001 +#define I2C_SSTAT_RREQ_BITN 0 +#define I2C_SSTAT_RREQ_M 0x00000001 +#define I2C_SSTAT_RREQ_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SCTL +// +//***************************************************************************** +// Field: [0] DA +// +// Device active +// +// 0: Disables the I2C slave operation +// 1: Enables the I2C slave operation +#define I2C_SCTL_DA 0x00000001 +#define I2C_SCTL_DA_BITN 0 +#define I2C_SCTL_DA_M 0x00000001 +#define I2C_SCTL_DA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SDR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// Data for transfer +// This field contains the data for transfer during a slave receive or transmit +// operation. When written the register data is used as transmit data. When +// read, this register returns the last data received. +// Data is stored until next update, either by a system write for transmit or +// by an external master for receive. +#define I2C_SDR_DATA_W 8 +#define I2C_SDR_DATA_M 0x000000FF +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SIMR +// +//***************************************************************************** +// Field: [2] STOPIM +// +// Stop condition interrupt mask +// +// 0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt +// controller. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_SIMR_STOPIM 0x00000004 +#define I2C_SIMR_STOPIM_BITN 2 +#define I2C_SIMR_STOPIM_M 0x00000004 +#define I2C_SIMR_STOPIM_S 2 +#define I2C_SIMR_STOPIM_EN 0x00000004 +#define I2C_SIMR_STOPIM_DIS 0x00000000 + +// Field: [1] STARTIM +// +// Start condition interrupt mask +// +// 0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt +// controller. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_SIMR_STARTIM 0x00000002 +#define I2C_SIMR_STARTIM_BITN 1 +#define I2C_SIMR_STARTIM_M 0x00000002 +#define I2C_SIMR_STARTIM_S 1 +#define I2C_SIMR_STARTIM_EN 0x00000002 +#define I2C_SIMR_STARTIM_DIS 0x00000000 + +// Field: [0] DATAIM +// +// Data interrupt mask +// +// 0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt +// controller. +#define I2C_SIMR_DATAIM 0x00000001 +#define I2C_SIMR_DATAIM_BITN 0 +#define I2C_SIMR_DATAIM_M 0x00000001 +#define I2C_SIMR_DATAIM_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SRIS +// +//***************************************************************************** +// Field: [2] STOPRIS +// +// Stop condition raw interrupt status +// +// 0: No interrupt +// 1: A Stop condition interrupt is pending. +// +// This bit is cleared by writing a 1 to SICR.STOPIC. +#define I2C_SRIS_STOPRIS 0x00000004 +#define I2C_SRIS_STOPRIS_BITN 2 +#define I2C_SRIS_STOPRIS_M 0x00000004 +#define I2C_SRIS_STOPRIS_S 2 + +// Field: [1] STARTRIS +// +// Start condition raw interrupt status +// +// 0: No interrupt +// 1: A Start condition interrupt is pending. +// +// This bit is cleared by writing a 1 to SICR.STARTIC. +#define I2C_SRIS_STARTRIS 0x00000002 +#define I2C_SRIS_STARTRIS_BITN 1 +#define I2C_SRIS_STARTRIS_M 0x00000002 +#define I2C_SRIS_STARTRIS_S 1 + +// Field: [0] DATARIS +// +// Data raw interrupt status +// +// 0: No interrupt +// 1: A data received or data requested interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.DATAIC. +#define I2C_SRIS_DATARIS 0x00000001 +#define I2C_SRIS_DATARIS_BITN 0 +#define I2C_SRIS_DATARIS_M 0x00000001 +#define I2C_SRIS_DATARIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SMIS +// +//***************************************************************************** +// Field: [2] STOPMIS +// +// Stop condition masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked Stop condition interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.STOPIC. +#define I2C_SMIS_STOPMIS 0x00000004 +#define I2C_SMIS_STOPMIS_BITN 2 +#define I2C_SMIS_STOPMIS_M 0x00000004 +#define I2C_SMIS_STOPMIS_S 2 + +// Field: [1] STARTMIS +// +// Start condition masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked Start condition interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.STARTIC. +#define I2C_SMIS_STARTMIS 0x00000002 +#define I2C_SMIS_STARTMIS_BITN 1 +#define I2C_SMIS_STARTMIS_M 0x00000002 +#define I2C_SMIS_STARTMIS_S 1 + +// Field: [0] DATAMIS +// +// Data masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked data received or data requested interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.DATAIC. +#define I2C_SMIS_DATAMIS 0x00000001 +#define I2C_SMIS_DATAMIS_BITN 0 +#define I2C_SMIS_DATAMIS_M 0x00000001 +#define I2C_SMIS_DATAMIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SICR +// +//***************************************************************************** +// Field: [2] STOPIC +// +// Stop condition interrupt clear +// +// Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. +#define I2C_SICR_STOPIC 0x00000004 +#define I2C_SICR_STOPIC_BITN 2 +#define I2C_SICR_STOPIC_M 0x00000004 +#define I2C_SICR_STOPIC_S 2 + +// Field: [1] STARTIC +// +// Start condition interrupt clear +// +// Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. +#define I2C_SICR_STARTIC 0x00000002 +#define I2C_SICR_STARTIC_BITN 1 +#define I2C_SICR_STARTIC_M 0x00000002 +#define I2C_SICR_STARTIC_S 1 + +// Field: [0] DATAIC +// +// Data interrupt clear +// +// Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. +#define I2C_SICR_DATAIC 0x00000001 +#define I2C_SICR_DATAIC_BITN 0 +#define I2C_SICR_DATAIC_M 0x00000001 +#define I2C_SICR_DATAIC_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MSA +// +//***************************************************************************** +// Field: [7:1] SA +// +// I2C master slave address +// Defines which slave is addressed for the transaction in master mode +#define I2C_MSA_SA_W 7 +#define I2C_MSA_SA_M 0x000000FE +#define I2C_MSA_SA_S 1 + +// Field: [0] RS +// +// Receive or Send +// This bit-field specifies if the next operation is a receive (high) or a +// transmit/send (low) from the addressed slave SA. +// ENUMs: +// RX Receive data from slave +// TX Transmit/send data to slave +#define I2C_MSA_RS 0x00000001 +#define I2C_MSA_RS_BITN 0 +#define I2C_MSA_RS_M 0x00000001 +#define I2C_MSA_RS_S 0 +#define I2C_MSA_RS_RX 0x00000001 +#define I2C_MSA_RS_TX 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MSTAT +// +//***************************************************************************** +// Field: [6] BUSBSY +// +// Bus busy +// +// 0: The I2C bus is idle. +// 1: The I2C bus is busy. +// +// The bit changes based on the MCTRL.START and MCTRL.STOP conditions. +#define I2C_MSTAT_BUSBSY 0x00000040 +#define I2C_MSTAT_BUSBSY_BITN 6 +#define I2C_MSTAT_BUSBSY_M 0x00000040 +#define I2C_MSTAT_BUSBSY_S 6 + +// Field: [5] IDLE +// +// I2C idle +// +// 0: The I2C controller is not idle. +// 1: The I2C controller is idle. +#define I2C_MSTAT_IDLE 0x00000020 +#define I2C_MSTAT_IDLE_BITN 5 +#define I2C_MSTAT_IDLE_M 0x00000020 +#define I2C_MSTAT_IDLE_S 5 + +// Field: [4] ARBLST +// +// Arbitration lost +// +// 0: The I2C controller won arbitration. +// 1: The I2C controller lost arbitration. +#define I2C_MSTAT_ARBLST 0x00000010 +#define I2C_MSTAT_ARBLST_BITN 4 +#define I2C_MSTAT_ARBLST_M 0x00000010 +#define I2C_MSTAT_ARBLST_S 4 + +// Field: [3] DATACK_N +// +// Data Was Not Acknowledge +// +// 0: The transmitted data was acknowledged. +// 1: The transmitted data was not acknowledged. +#define I2C_MSTAT_DATACK_N 0x00000008 +#define I2C_MSTAT_DATACK_N_BITN 3 +#define I2C_MSTAT_DATACK_N_M 0x00000008 +#define I2C_MSTAT_DATACK_N_S 3 + +// Field: [2] ADRACK_N +// +// Address Was Not Acknowledge +// +// 0: The transmitted address was acknowledged. +// 1: The transmitted address was not acknowledged. +#define I2C_MSTAT_ADRACK_N 0x00000004 +#define I2C_MSTAT_ADRACK_N_BITN 2 +#define I2C_MSTAT_ADRACK_N_M 0x00000004 +#define I2C_MSTAT_ADRACK_N_S 2 + +// Field: [1] ERR +// +// Error +// +// 0: No error was detected on the last operation. +// 1: An error occurred on the last operation. +#define I2C_MSTAT_ERR 0x00000002 +#define I2C_MSTAT_ERR_BITN 1 +#define I2C_MSTAT_ERR_M 0x00000002 +#define I2C_MSTAT_ERR_S 1 + +// Field: [0] BUSY +// +// I2C busy +// +// 0: The controller is idle. +// 1: The controller is busy. +// +// When this bit-field is set, the other status bits are not valid. +// +// Note: The I2C controller requires four SYSBUS clock cycles to assert the +// BUSY status after I2C master operation has been initiated through MCTRL +// register. +// Hence after programming MCTRL register, application is requested to wait for +// four SYSBUS clock cycles before issuing a controller status inquiry through +// MSTAT register. +// Any prior inquiry would result in wrong status being reported. +#define I2C_MSTAT_BUSY 0x00000001 +#define I2C_MSTAT_BUSY_BITN 0 +#define I2C_MSTAT_BUSY_M 0x00000001 +#define I2C_MSTAT_BUSY_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MCTRL +// +//***************************************************************************** +// Field: [3] ACK +// +// Data acknowledge enable +// +// 0: The received data byte is not acknowledged automatically by the master. +// 1: The received data byte is acknowledged automatically by the master. +// +// This bit-field must be cleared when the I2C bus controller requires no +// further data to be transmitted from the slave transmitter. +// ENUMs: +// EN Enable acknowledge +// DIS Disable acknowledge +#define I2C_MCTRL_ACK 0x00000008 +#define I2C_MCTRL_ACK_BITN 3 +#define I2C_MCTRL_ACK_M 0x00000008 +#define I2C_MCTRL_ACK_S 3 +#define I2C_MCTRL_ACK_EN 0x00000008 +#define I2C_MCTRL_ACK_DIS 0x00000000 + +// Field: [2] STOP +// +// This bit-field determines if the cycle stops at the end of the data cycle or +// continues on to a repeated START condition. +// +// 0: The controller does not generate the Stop condition. +// 1: The controller generates the Stop condition. +// ENUMs: +// EN Enable STOP +// DIS Disable STOP +#define I2C_MCTRL_STOP 0x00000004 +#define I2C_MCTRL_STOP_BITN 2 +#define I2C_MCTRL_STOP_M 0x00000004 +#define I2C_MCTRL_STOP_S 2 +#define I2C_MCTRL_STOP_EN 0x00000004 +#define I2C_MCTRL_STOP_DIS 0x00000000 + +// Field: [1] START +// +// This bit-field generates the Start or Repeated Start condition. +// +// 0: The controller does not generate the Start condition. +// 1: The controller generates the Start condition. +// ENUMs: +// EN Enable START +// DIS Disable START +#define I2C_MCTRL_START 0x00000002 +#define I2C_MCTRL_START_BITN 1 +#define I2C_MCTRL_START_M 0x00000002 +#define I2C_MCTRL_START_S 1 +#define I2C_MCTRL_START_EN 0x00000002 +#define I2C_MCTRL_START_DIS 0x00000000 + +// Field: [0] RUN +// +// I2C master enable +// +// 0: The master is disabled. +// 1: The master is enabled to transmit or receive data. +// ENUMs: +// EN Enable Master +// DIS Disable Master +#define I2C_MCTRL_RUN 0x00000001 +#define I2C_MCTRL_RUN_BITN 0 +#define I2C_MCTRL_RUN_M 0x00000001 +#define I2C_MCTRL_RUN_S 0 +#define I2C_MCTRL_RUN_EN 0x00000001 +#define I2C_MCTRL_RUN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MDR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// When Read: Last RX Data is returned +// When Written: Data is transferred during TX transaction +#define I2C_MDR_DATA_W 8 +#define I2C_MDR_DATA_M 0x000000FF +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MTPR +// +//***************************************************************************** +// Field: [7] TPR_7 +// +// Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. +#define I2C_MTPR_TPR_7 0x00000080 +#define I2C_MTPR_TPR_7_BITN 7 +#define I2C_MTPR_TPR_7_M 0x00000080 +#define I2C_MTPR_TPR_7_S 7 + +// Field: [6:0] TPR +// +// SCL clock period +// This field specifies the period of the SCL clock. +// SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD +// where: +// SCL_PRD is the SCL line period (I2C clock). +// TPR is the timer period register value (range of 1 to 127) +// SCL_LP is the SCL low period (fixed at 6). +// SCL_HP is the SCL high period (fixed at 4). +// CLK_PRD is the system clock period in ns. +#define I2C_MTPR_TPR_W 7 +#define I2C_MTPR_TPR_M 0x0000007F +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MIMR +// +//***************************************************************************** +// Field: [0] IM +// +// Interrupt mask +// +// 0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The master interrupt is sent to the interrupt controller when the +// MRIS.RIS is set. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_MIMR_IM 0x00000001 +#define I2C_MIMR_IM_BITN 0 +#define I2C_MIMR_IM_M 0x00000001 +#define I2C_MIMR_IM_S 0 +#define I2C_MIMR_IM_EN 0x00000001 +#define I2C_MIMR_IM_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MRIS +// +//***************************************************************************** +// Field: [0] RIS +// +// Raw interrupt status +// +// 0: No interrupt +// 1: A master interrupt is pending. +// +// This bit is cleared by writing 1 to the MICR.IC bit . +#define I2C_MRIS_RIS 0x00000001 +#define I2C_MRIS_RIS_BITN 0 +#define I2C_MRIS_RIS_M 0x00000001 +#define I2C_MRIS_RIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MMIS +// +//***************************************************************************** +// Field: [0] MIS +// +// Masked interrupt status +// +// 0: An interrupt has not occurred or is masked. +// 1: A master interrupt is pending. +// +// This bit is cleared by writing 1 to the MICR.IC bit . +#define I2C_MMIS_MIS 0x00000001 +#define I2C_MMIS_MIS_BITN 0 +#define I2C_MMIS_MIS_M 0x00000001 +#define I2C_MMIS_MIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MICR +// +//***************************************************************************** +// Field: [0] IC +// +// Interrupt clear +// Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . +// +// Reading this register returns no meaningful data. +#define I2C_MICR_IC 0x00000001 +#define I2C_MICR_IC_BITN 0 +#define I2C_MICR_IC_M 0x00000001 +#define I2C_MICR_IC_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MCR +// +//***************************************************************************** +// Field: [5] SFE +// +// I2C slave function enable +// ENUMs: +// EN Slave mode is enabled. +// DIS Slave mode is disabled. +#define I2C_MCR_SFE 0x00000020 +#define I2C_MCR_SFE_BITN 5 +#define I2C_MCR_SFE_M 0x00000020 +#define I2C_MCR_SFE_S 5 +#define I2C_MCR_SFE_EN 0x00000020 +#define I2C_MCR_SFE_DIS 0x00000000 + +// Field: [4] MFE +// +// I2C master function enable +// ENUMs: +// EN Master mode is enabled. +// DIS Master mode is disabled. +#define I2C_MCR_MFE 0x00000010 +#define I2C_MCR_MFE_BITN 4 +#define I2C_MCR_MFE_M 0x00000010 +#define I2C_MCR_MFE_S 4 +#define I2C_MCR_MFE_EN 0x00000010 +#define I2C_MCR_MFE_DIS 0x00000000 + +// Field: [0] LPBK +// +// I2C loopback +// +// 0: Normal operation +// 1: Loopback operation (test mode) +// ENUMs: +// EN Enable Test Mode +// DIS Disable Test Mode +#define I2C_MCR_LPBK 0x00000001 +#define I2C_MCR_LPBK_BITN 0 +#define I2C_MCR_LPBK_M 0x00000001 +#define I2C_MCR_LPBK_S 0 +#define I2C_MCR_LPBK_EN 0x00000001 +#define I2C_MCR_LPBK_DIS 0x00000000 + + +#endif // __I2C__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2s.h new file mode 100644 index 0000000..ee850c7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2s.h @@ -0,0 +1,967 @@ +/****************************************************************************** +* Filename: hw_i2s_h +* Revised: 2017-11-02 10:21:28 +0100 (Thu, 02 Nov 2017) +* Revision: 50141 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_I2S_H__ +#define __HW_I2S_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// I2S component +// +//***************************************************************************** +// WCLK Source Selection +#define I2S_O_AIFWCLKSRC 0x00000000 + +// DMA Buffer Size Configuration +#define I2S_O_AIFDMACFG 0x00000004 + +// Pin Direction +#define I2S_O_AIFDIRCFG 0x00000008 + +// Serial Interface Format Configuration +#define I2S_O_AIFFMTCFG 0x0000000C + +// Word Selection Bit Mask for Pin 0 +#define I2S_O_AIFWMASK0 0x00000010 + +// Word Selection Bit Mask for Pin 1 +#define I2S_O_AIFWMASK1 0x00000014 + +// Audio Interface PWM Debug Value +#define I2S_O_AIFPWMVALUE 0x0000001C + +// DMA Input Buffer Next Pointer +#define I2S_O_AIFINPTRNEXT 0x00000020 + +// DMA Input Buffer Current Pointer +#define I2S_O_AIFINPTR 0x00000024 + +// DMA Output Buffer Next Pointer +#define I2S_O_AIFOUTPTRNEXT 0x00000028 + +// DMA Output Buffer Current Pointer +#define I2S_O_AIFOUTPTR 0x0000002C + +// Samplestamp Generator Control Register +#define I2S_O_STMPCTL 0x00000034 + +// Captured XOSC Counter Value, Capture Channel 0 +#define I2S_O_STMPXCNTCAPT0 0x00000038 + +// XOSC Period Value +#define I2S_O_STMPXPER 0x0000003C + +// Captured WCLK Counter Value, Capture Channel 0 +#define I2S_O_STMPWCNTCAPT0 0x00000040 + +// WCLK Counter Period Value +#define I2S_O_STMPWPER 0x00000044 + +// WCLK Counter Trigger Value for Input Pins +#define I2S_O_STMPINTRIG 0x00000048 + +// WCLK Counter Trigger Value for Output Pins +#define I2S_O_STMPOUTTRIG 0x0000004C + +// WCLK Counter Set Operation +#define I2S_O_STMPWSET 0x00000050 + +// WCLK Counter Add Operation +#define I2S_O_STMPWADD 0x00000054 + +// XOSC Minimum Period Value +#define I2S_O_STMPXPERMIN 0x00000058 + +// Current Value of WCNT +#define I2S_O_STMPWCNT 0x0000005C + +// Current Value of XCNT +#define I2S_O_STMPXCNT 0x00000060 + +// Internal +#define I2S_O_STMPXCNTCAPT1 0x00000064 + +// Internal +#define I2S_O_STMPWCNTCAPT1 0x00000068 + +// Interrupt Mask Register +#define I2S_O_IRQMASK 0x00000070 + +// Raw Interrupt Status Register +#define I2S_O_IRQFLAGS 0x00000074 + +// Interrupt Set Register +#define I2S_O_IRQSET 0x00000078 + +// Interrupt Clear Register +#define I2S_O_IRQCLR 0x0000007C + +//***************************************************************************** +// +// Register: I2S_O_AIFWCLKSRC +// +//***************************************************************************** +// Field: [2] WCLK_INV +// +// Inverts WCLK source (pad or internal) when set. +// +// 0: Not inverted +// 1: Inverted +#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 +#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_S 2 + +// Field: [1:0] WCLK_SRC +// +// Selects WCLK source for AIF (should be the same as the BCLK source). The +// BCLK source is defined in the PRCM:I2SBCLKSEL.SRC +// ENUMs: +// RESERVED Not supported. Will give same WCLK as 'NONE' +// ('00') +// INT Internal WCLK generator, from module PRCM +// EXT External WCLK generator, from pad +// NONE None ('0') +#define I2S_AIFWCLKSRC_WCLK_SRC_W 2 +#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_S 0 +#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 +#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 +#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 + +//***************************************************************************** +// +// Register: I2S_O_AIFDMACFG +// +//***************************************************************************** +// Field: [7:0] END_FRAME_IDX +// +// Defines the length of the DMA buffer. Writing a non-zero value to this +// register field enables and initializes AIF. Note that before doing so, all +// other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must +// have been loaded. +#define I2S_AIFDMACFG_END_FRAME_IDX_W 8 +#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF +#define I2S_AIFDMACFG_END_FRAME_IDX_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFDIRCFG +// +//***************************************************************************** +// Field: [5:4] AD1 +// +// Configures the AD1 audio data pin usage: +// +// 0x3: Reserved +// ENUMs: +// OUT Output mode +// IN Input mode +// DIS Not in use (disabled) +#define I2S_AIFDIRCFG_AD1_W 2 +#define I2S_AIFDIRCFG_AD1_M 0x00000030 +#define I2S_AIFDIRCFG_AD1_S 4 +#define I2S_AIFDIRCFG_AD1_OUT 0x00000020 +#define I2S_AIFDIRCFG_AD1_IN 0x00000010 +#define I2S_AIFDIRCFG_AD1_DIS 0x00000000 + +// Field: [1:0] AD0 +// +// Configures the AD0 audio data pin usage: +// +// 0x3: Reserved +// ENUMs: +// OUT Output mode +// IN Input mode +// DIS Not in use (disabled) +#define I2S_AIFDIRCFG_AD0_W 2 +#define I2S_AIFDIRCFG_AD0_M 0x00000003 +#define I2S_AIFDIRCFG_AD0_S 0 +#define I2S_AIFDIRCFG_AD0_OUT 0x00000002 +#define I2S_AIFDIRCFG_AD0_IN 0x00000001 +#define I2S_AIFDIRCFG_AD0_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2S_O_AIFFMTCFG +// +//***************************************************************************** +// Field: [15:8] DATA_DELAY +// +// The number of BCLK periods between a WCLK edge and MSB of the first word in +// a phase: +// +// 0x00: LJF and DSP format +// 0x01: I2S and DSP format +// 0x02: RJF format +// ... +// 0xFF: RJF format +// +// Note: When 0, MSB of the next word will be output in the idle period between +// LSB of the previous word and the start of the next word. Otherwise logical 0 +// will be output until the data delay has expired. +#define I2S_AIFFMTCFG_DATA_DELAY_W 8 +#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 +#define I2S_AIFFMTCFG_DATA_DELAY_S 8 + +// Field: [7] MEM_LEN_24 +// +// The size of each word stored to or loaded from memory: +// ENUMs: +// 24BIT 24-bit (one 8 bit and one 16 bit locked access per +// sample) +// 16BIT 16-bit (one 16 bit access per sample) +#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_S 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 + +// Field: [6] SMPL_EDGE +// +// On the serial audio interface, data (and wclk) is sampled and clocked out on +// opposite edges of BCLK. +// ENUMs: +// POS Data is sampled on the positive edge and clocked +// out on the negative edge. +// NEG Data is sampled on the negative edge and clocked +// out on the positive edge. +#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_S 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 + +// Field: [5] DUAL_PHASE +// +// Selects dual- or single-phase format. +// +// 0: Single-phase: DSP format +// 1: Dual-phase: I2S, LJF and RJF formats +#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 +#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_S 5 + +// Field: [4:0] WORD_LEN +// +// Number of bits per word (8-24): +// In single-phase format, this is the exact number of bits per word. +// In dual-phase format, this is the maximum number of bits per word. +// +// Values below 8 and above 24 give undefined behavior. Data written to memory +// is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that +// differ from this alignment will either be truncated or zero padded. +#define I2S_AIFFMTCFG_WORD_LEN_W 5 +#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F +#define I2S_AIFFMTCFG_WORD_LEN_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFWMASK0 +// +//***************************************************************************** +// Field: [7:0] MASK +// +// Bit-mask indicating valid channels in a frame on AD0. +// +// In single-phase mode, each bit represents one channel, starting with LSB for +// the first word in the frame. A frame can contain up to 8 channels. Channels +// that are not included in the mask will not be sampled and stored in memory, +// and clocked out as '0'. +// +// In dual-phase mode, only the two LSBs are considered. For a stereo +// configuration, set both bits. For a mono configuration, set bit 0 only. In +// mono mode, only channel 0 will be sampled and stored to memory, and channel +// 0 will be repeated when clocked out. +// +// In mono mode, only channel 0 will be sampled and stored to memory, and +// channel 0 will be repeated in the second phase when clocked out. +// +// If all bits are zero, no input words will be stored to memory, and the +// output data lines will be constant '0'. This can be utilized when PWM debug +// output is desired without any actively used output pins. +#define I2S_AIFWMASK0_MASK_W 8 +#define I2S_AIFWMASK0_MASK_M 0x000000FF +#define I2S_AIFWMASK0_MASK_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFWMASK1 +// +//***************************************************************************** +// Field: [7:0] MASK +// +// Bit-mask indicating valid channels in a frame on AD1. +// +// In single-phase mode, each bit represents one channel, starting with LSB for +// the first word in the frame. A frame can contain up to 8 channels. Channels +// that are not included in the mask will not be sampled and stored in memory, +// and clocked out as '0'. +// +// In dual-phase mode, only the two LSBs are considered. For a stereo +// configuration, set both bits. For a mono configuration, set bit 0 only. In +// mono mode, only channel 0 will be sampled and stored to memory, and channel +// 0 will be repeated when clocked out. +// +// In mono mode, only channel 0 will be sampled and stored to memory, and +// channel 0 will be repeated in the second phase when clocked out. +// +// If all bits are zero, no input words will be stored to memory, and the +// output data lines will be constant '0'. This can be utilized when PWM debug +// output is desired without any actively used output pins. +#define I2S_AIFWMASK1_MASK_W 8 +#define I2S_AIFWMASK1_MASK_M 0x000000FF +#define I2S_AIFWMASK1_MASK_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFPWMVALUE +// +//***************************************************************************** +// Field: [15:0] PULSE_WIDTH +// +// The value written to this register determines the width of the active high +// PWM pulse (pwm_debug), which starts together with MSB of the first output +// word in a DMA buffer: +// +// 0x0000: Constant low +// 0x0001: Width of the pulse (number of BCLK cycles, here 1). +// ... +// 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). +// 0xFFFF: Constant high +#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 +#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF +#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFINPTRNEXT +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Pointer to the first byte in the next DMA input buffer. +// +// The read value equals the last written value until the currently used DMA +// input buffer is completed, and then becomes null when the last written value +// is transferred to the DMA controller to start on the next buffer. This event +// is signalized by IRQFLAGS.AIF_DMA_IN. +// +// At startup, the value must be written once before and once after configuring +// the DMA buffer size in AIFDMACFG. +// +// The next pointer must be written to this register while the DMA function +// uses the previously written pointer. If not written in time, +// IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. +#define I2S_AIFINPTRNEXT_PTR_W 32 +#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTRNEXT_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFINPTR +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Value of the DMA input buffer pointer currently used by the DMA controller. +// Incremented by 1 (byte) or 2 (word) for each AHB access. +#define I2S_AIFINPTR_PTR_W 32 +#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTR_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFOUTPTRNEXT +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Pointer to the first byte in the next DMA output buffer. +// +// The read value equals the last written value until the currently used DMA +// output buffer is completed, and then becomes null when the last written +// value is transferred to the DMA controller to start on the next buffer. This +// event is signalized by IRQFLAGS.AIF_DMA_OUT. +// +// At startup, the value must be written once before and once after configuring +// the DMA buffer size in AIFDMACFG. At this time, the first two samples will +// be fetched from memory. +// +// The next pointer must be written to this register while the DMA function +// uses the previously written pointer. If not written in time, +// IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. +#define I2S_AIFOUTPTRNEXT_PTR_W 32 +#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTRNEXT_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFOUTPTR +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Value of the DMA output buffer pointer currently used by the DMA controller +// Incremented by 1 (byte) or 2 (word) for each AHB access. +#define I2S_AIFOUTPTR_PTR_W 32 +#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTR_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPCTL +// +//***************************************************************************** +// Field: [2] OUT_RDY +// +// Low until the output pins are ready to be started by the samplestamp +// generator. When started (that is STMPOUTTRIG equals the WCLK counter) the +// bit goes back low. +#define I2S_STMPCTL_OUT_RDY 0x00000004 +#define I2S_STMPCTL_OUT_RDY_BITN 2 +#define I2S_STMPCTL_OUT_RDY_M 0x00000004 +#define I2S_STMPCTL_OUT_RDY_S 2 + +// Field: [1] IN_RDY +// +// Low until the input pins are ready to be started by the samplestamp +// generator. When started (that is STMPINTRIG equals the WCLK counter) the bit +// goes back low. +#define I2S_STMPCTL_IN_RDY 0x00000002 +#define I2S_STMPCTL_IN_RDY_BITN 1 +#define I2S_STMPCTL_IN_RDY_M 0x00000002 +#define I2S_STMPCTL_IN_RDY_S 1 + +// Field: [0] STMP_EN +// +// Enables the samplestamp generator. The samplestamp generator must only be +// enabled after it has been properly configured. +// When cleared, all samplestamp generator counters and capture values are +// cleared. +#define I2S_STMPCTL_STMP_EN 0x00000001 +#define I2S_STMPCTL_STMP_EN_BITN 0 +#define I2S_STMPCTL_STMP_EN_M 0x00000001 +#define I2S_STMPCTL_STMP_EN_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNTCAPT0 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an +// event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for +// channel 0). This number corresponds to the number of 24 MHz clock cycles +// since the last positive edge of the selected WCLK. +// The value is cleared when STMPCTL.STMP_EN = 0. +// Note: Due to buffering and synchronization, WCLK is delayed by a small +// number of BCLK periods and clk periods. +// Note: When calculating the fractional part of the sample stamp, STMPXPER may +// be less than this bit field. +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXPER +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// The number of 24 MHz clock cycles in the previous WCLK period (that is - +// the next value of the XOSC counter at the positive WCLK edge, had it not +// been reset to 0). +// The value is cleared when STMPCTL.STMP_EN = 0. +#define I2S_STMPXPER_VALUE_W 16 +#define I2S_STMPXPER_VALUE_M 0x0000FFFF +#define I2S_STMPXPER_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNTCAPT0 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an +// event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel +// 0). This number corresponds to the number of positive WCLK edges since the +// samplestamp generator was enabled (not taking modification through +// STMPWADD/STMPWSET into account). +// The value is cleared when STMPCTL.STMP_EN = 0. +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWPER +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Used to define when STMPWCNT is to be reset so number of WCLK edges are +// found for the size of the sample buffer. This is thus a modulo value for the +// WCLK counter. This number must correspond to the size of the sample buffer +// used by the system (that is the index of the last sample plus 1). +#define I2S_STMPWPER_VALUE_W 16 +#define I2S_STMPWPER_VALUE_M 0x0000FFFF +#define I2S_STMPWPER_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPINTRIG +// +//***************************************************************************** +// Field: [15:0] IN_START_WCNT +// +// Compare value used to start the incoming audio streams. +// This bit field shall equal the WCLK counter value during the WCLK period in +// which the first input word(s) are sampled and stored to memory (that is the +// sample at the start of the very first DMA input buffer). +// +// The value of this register takes effect when the following conditions are +// met: +// - One or more pins are configured as inputs in AIFDIRCFG. +// - AIFDMACFG has been configured for the correct buffer size, and at least 32 +// BCLK cycle ticks have happened. +// +// Note: To avoid false triggers, this bit field should be set higher than +// STMPWPER.VALUE. +#define I2S_STMPINTRIG_IN_START_WCNT_W 16 +#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF +#define I2S_STMPINTRIG_IN_START_WCNT_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPOUTTRIG +// +//***************************************************************************** +// Field: [15:0] OUT_START_WCNT +// +// Compare value used to start the outgoing audio streams. +// +// This bit field must equal the WCLK counter value during the WCLK period in +// which the first output word(s) read from memory are clocked out (that is the +// sample at the start of the very first DMA output buffer). +// +// The value of this register takes effect when the following conditions are +// met: +// - One or more pins are configured as outputs in AIFDIRCFG. +// - AIFDMACFG has been configured for the correct buffer size, and 32 BCLK +// cycle ticks have happened. +// - 2 samples have been preloaded from memory (examine the AIFOUTPTR register +// if necessary). +// Note: The memory read access is only performed when required, that is +// channels 0/1 must be selected in AIFWMASK0/AIFWMASK1. +// +// Note: To avoid false triggers, this bit field should be set higher than +// STMPWPER.VALUE. +#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 +#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF +#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWSET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// WCLK counter modification: Sets the running WCLK counter equal to the +// written value. +#define I2S_STMPWSET_VALUE_W 16 +#define I2S_STMPWSET_VALUE_M 0x0000FFFF +#define I2S_STMPWSET_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWADD +// +//***************************************************************************** +// Field: [15:0] VALUE_INC +// +// WCLK counter modification: Adds the written value to the running WCLK +// counter. If a positive edge of WCLK occurs at the same time as the +// operation, this will be taken into account. +// To add a negative value, write "STMPWPER.VALUE - value". +// +#define I2S_STMPWADD_VALUE_INC_W 16 +#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF +#define I2S_STMPWADD_VALUE_INC_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXPERMIN +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Each time STMPXPER is updated, the value is also loaded into this register, +// provided that the value is smaller than the current value in this register. +// When written, the register is reset to 0xFFFF (65535), regardless of the +// value written. +// The minimum value can be used to detect extra WCLK pulses (this registers +// value will be significantly smaller than STMPXPER.VALUE). +#define I2S_STMPXPERMIN_VALUE_W 16 +#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF +#define I2S_STMPXPERMIN_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNT +// +//***************************************************************************** +// Field: [15:0] CURR_VALUE +// +// Current value of the WCLK counter +#define I2S_STMPWCNT_CURR_VALUE_W 16 +#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPWCNT_CURR_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNT +// +//***************************************************************************** +// Field: [15:0] CURR_VALUE +// +// Current value of the XOSC counter, latched when reading STMPWCNT. +#define I2S_STMPXCNT_CURR_VALUE_W 16 +#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPXCNT_CURR_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNTCAPT1 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// Internal. Only to be used through TI provided API. +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNTCAPT1 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// Internal. Only to be used through TI provided API. +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQMASK +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// IRQFLAGS.AIF_DMA_IN interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_AIF_DMA_IN 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_BITN 5 +#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// IRQFLAGS.AIF_DMA_OUT interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 +#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// IRQFLAGS.WCLK_TIMEOUT interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// IRQFLAGS.BUS_ERR interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_BUS_ERR 0x00000004 +#define I2S_IRQMASK_BUS_ERR_BITN 2 +#define I2S_IRQMASK_BUS_ERR_M 0x00000004 +#define I2S_IRQMASK_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// IRQFLAGS.WCLK_ERR interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_WCLK_ERR 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_BITN 1 +#define I2S_IRQMASK_WCLK_ERR_M 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// IRQFLAGS.PTR_ERR interrupt mask. +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_PTR_ERR 0x00000001 +#define I2S_IRQMASK_PTR_ERR_BITN 0 +#define I2S_IRQMASK_PTR_ERR_M 0x00000001 +#define I2S_IRQMASK_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQFLAGS +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// Set when condition for this bit field event occurs (auto cleared when input +// pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register +// for details. +#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 +#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// Set when condition for this bit field event occurs (auto cleared when output +// pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT +// register for details +#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 +#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// Set when the sample stamp generator does not detect a positive WCLK edge for +// 65535 clk periods. This signalizes that the internal or external BCLK and +// WCLK generator source has been disabled. +// +// The bit is sticky and may only be cleared by software (by writing '1' to +// IRQCLR.WCLK_TIMEOUT). +#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// Set when a DMA operation is not completed in time (that is audio output +// buffer underflow, or audio input buffer overflow). +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.BUS_ERR). +// +// Note that DMA initiated transactions to illegal addresses will not trigger +// an interrupt. The response to such transactions is undefined. +#define I2S_IRQFLAGS_BUS_ERR 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_BITN 2 +#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// Set when: +// - An unexpected WCLK edge occurs during the data delay period of a phase. +// Note unexpected WCLK edges during the word and idle periods of the phase are +// not detected. +// - In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles +// apart. +// - In single-phase mode, when a WCLK pulse occurs before the last channel. +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.WCLK_ERR). +#define I2S_IRQFLAGS_WCLK_ERR 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_BITN 1 +#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next +// block address in time. +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.PTR_ERR). +#define I2S_IRQFLAGS_PTR_ERR 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_BITN 0 +#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQSET +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria +// was given at the same time, in which the set will be ignored) +#define I2S_IRQSET_AIF_DMA_IN 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_BITN 5 +#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria +// was given at the same time, in which the set will be ignored) +#define I2S_IRQSET_AIF_DMA_OUT 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_BITN 4 +#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT +#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// 1: Sets the interrupt of IRQFLAGS.BUS_ERR +#define I2S_IRQSET_BUS_ERR 0x00000004 +#define I2S_IRQSET_BUS_ERR_BITN 2 +#define I2S_IRQSET_BUS_ERR_M 0x00000004 +#define I2S_IRQSET_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// 1: Sets the interrupt of IRQFLAGS.WCLK_ERR +#define I2S_IRQSET_WCLK_ERR 0x00000002 +#define I2S_IRQSET_WCLK_ERR_BITN 1 +#define I2S_IRQSET_WCLK_ERR_M 0x00000002 +#define I2S_IRQSET_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// 1: Sets the interrupt of IRQFLAGS.PTR_ERR +#define I2S_IRQSET_PTR_ERR 0x00000001 +#define I2S_IRQSET_PTR_ERR_BITN 0 +#define I2S_IRQSET_PTR_ERR_M 0x00000001 +#define I2S_IRQSET_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQCLR +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_AIF_DMA_IN 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_BITN 5 +#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 +#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given +// at the same time in which the clear will be ignored) +#define I2S_IRQCLR_BUS_ERR 0x00000004 +#define I2S_IRQCLR_BUS_ERR_BITN 2 +#define I2S_IRQCLR_BUS_ERR_M 0x00000004 +#define I2S_IRQCLR_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_WCLK_ERR 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_BITN 1 +#define I2S_IRQCLR_WCLK_ERR_M 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given +// at the same time in which the clear will be ignored) +#define I2S_IRQCLR_PTR_ERR 0x00000001 +#define I2S_IRQCLR_PTR_ERR_BITN 0 +#define I2S_IRQCLR_PTR_ERR_M 0x00000001 +#define I2S_IRQCLR_PTR_ERR_S 0 + + +#endif // __I2S__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ints.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ints.h new file mode 100644 index 0000000..3d38283 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ints.h @@ -0,0 +1,113 @@ +/****************************************************************************** +* Filename: hw_ints_h +* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) +* Revision: 48904 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_NMI_FAULT 2 // NMI Fault +#define INT_HARD_FAULT 3 // Hard Fault +#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage) + // Fault +#define INT_BUS_FAULT 5 // Bus Fault +#define INT_USAGE_FAULT 6 // Usage Fault +#define INT_SVCALL 11 // Supervisor Call (SVCall) +#define INT_DEBUG 12 // Debug Monitor +#define INT_PENDSV 14 // Pending Service Call (PendSV) +#define INT_SYSTICK 15 // SysTick Interrupt from the + // System Timer in NVIC. +#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC +#define INT_I2C_IRQ 17 // Interrupt event from I2C +#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE + // Generated events +#define INT_AON_RTC_COMB 20 // Event from AON_RTC +#define INT_UART0_COMB 21 // UART0 combined interrupt +#define INT_AUX_SWEV0 22 // AUX software event 0 +#define INT_SSI0_COMB 23 // SSI0 combined interrupt +#define INT_SSI1_COMB 24 // SSI1 combined interrupt +#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE + // Generated events +#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt +#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command + // Acknowledgement Interrupt +#define INT_I2S_IRQ 28 // Interrupt event from I2S +#define INT_AUX_SWEV1 29 // AUX software event 1 +#define INT_WDT_IRQ 30 // Watchdog interrupt event +#define INT_GPT0A 31 // GPT0A interrupt event +#define INT_GPT0B 32 // GPT0B interrupt event +#define INT_GPT1A 33 // GPT1A interrupt event +#define INT_GPT1B 34 // GPT1B interrupt event +#define INT_GPT2A 35 // GPT2A interrupt event +#define INT_GPT2B 36 // GPT2B interrupt event +#define INT_GPT3A 37 // GPT3A interrupt event +#define INT_GPT3B 38 // GPT3B interrupt event +#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt + // event +#define INT_DMA_DONE_COMB 40 // Combined DMA done +#define INT_DMA_ERR 41 // DMA bus error +#define INT_FLASH 42 // FLASH controller error event +#define INT_SWEV0 43 // Software event 0 +#define INT_AUX_COMB 44 // AUX combined event +#define INT_AON_PROG0 45 // AON programmable event 0 +#define INT_PROG0 46 // Programmable Interrupt 0 +#define INT_AUX_COMPA 47 // AUX Compare A event +#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event +#define INT_TRNG_IRQ 49 // TRNG Interrupt event + +//***************************************************************************** +// +// The following are defines for number of interrupts and priority levels. +// +//***************************************************************************** +#define NUM_INTERRUPTS 50 // Number of interrupts +#define NUM_PRIORITY_BITS 3 // Number of Priority bits +#define NUM_PRIORITY 8 // Number of priority levels + + +//***************************************************************************** +// +// Aliases for backwards compatibility with Sensor Controller Studio 1.1.0 +// +//***************************************************************************** + +#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0 +#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1 + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ioc.h new file mode 100644 index 0000000..16a800a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ioc.h @@ -0,0 +1,9839 @@ +/****************************************************************************** +* Filename: hw_ioc_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_IOC_H__ +#define __HW_IOC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// IOC component +// +//***************************************************************************** +// Configuration of DIO0 +#define IOC_O_IOCFG0 0x00000000 + +// Configuration of DIO1 +#define IOC_O_IOCFG1 0x00000004 + +// Configuration of DIO2 +#define IOC_O_IOCFG2 0x00000008 + +// Configuration of DIO3 +#define IOC_O_IOCFG3 0x0000000C + +// Configuration of DIO4 +#define IOC_O_IOCFG4 0x00000010 + +// Configuration of DIO5 +#define IOC_O_IOCFG5 0x00000014 + +// Configuration of DIO6 +#define IOC_O_IOCFG6 0x00000018 + +// Configuration of DIO7 +#define IOC_O_IOCFG7 0x0000001C + +// Configuration of DIO8 +#define IOC_O_IOCFG8 0x00000020 + +// Configuration of DIO9 +#define IOC_O_IOCFG9 0x00000024 + +// Configuration of DIO10 +#define IOC_O_IOCFG10 0x00000028 + +// Configuration of DIO11 +#define IOC_O_IOCFG11 0x0000002C + +// Configuration of DIO12 +#define IOC_O_IOCFG12 0x00000030 + +// Configuration of DIO13 +#define IOC_O_IOCFG13 0x00000034 + +// Configuration of DIO14 +#define IOC_O_IOCFG14 0x00000038 + +// Configuration of DIO15 +#define IOC_O_IOCFG15 0x0000003C + +// Configuration of DIO16 +#define IOC_O_IOCFG16 0x00000040 + +// Configuration of DIO17 +#define IOC_O_IOCFG17 0x00000044 + +// Configuration of DIO18 +#define IOC_O_IOCFG18 0x00000048 + +// Configuration of DIO19 +#define IOC_O_IOCFG19 0x0000004C + +// Configuration of DIO20 +#define IOC_O_IOCFG20 0x00000050 + +// Configuration of DIO21 +#define IOC_O_IOCFG21 0x00000054 + +// Configuration of DIO22 +#define IOC_O_IOCFG22 0x00000058 + +// Configuration of DIO23 +#define IOC_O_IOCFG23 0x0000005C + +// Configuration of DIO24 +#define IOC_O_IOCFG24 0x00000060 + +// Configuration of DIO25 +#define IOC_O_IOCFG25 0x00000064 + +// Configuration of DIO26 +#define IOC_O_IOCFG26 0x00000068 + +// Configuration of DIO27 +#define IOC_O_IOCFG27 0x0000006C + +// Configuration of DIO28 +#define IOC_O_IOCFG28 0x00000070 + +// Configuration of DIO29 +#define IOC_O_IOCFG29 0x00000074 + +// Configuration of DIO30 +#define IOC_O_IOCFG30 0x00000078 + +// Configuration of DIO31 +#define IOC_O_IOCFG31 0x0000007C + +//***************************************************************************** +// +// Register: IOC_O_IOCFG0 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG0_HYST_EN 0x40000000 +#define IOC_IOCFG0_HYST_EN_BITN 30 +#define IOC_IOCFG0_HYST_EN_M 0x40000000 +#define IOC_IOCFG0_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG0_IE 0x20000000 +#define IOC_IOCFG0_IE_BITN 29 +#define IOC_IOCFG0_IE_M 0x20000000 +#define IOC_IOCFG0_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG0_WU_CFG_W 2 +#define IOC_IOCFG0_WU_CFG_M 0x18000000 +#define IOC_IOCFG0_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input/output +// OPENSRC Open Source +// Normal input / outut +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG0_IOMODE_W 3 +#define IOC_IOCFG0_IOMODE_M 0x07000000 +#define IOC_IOCFG0_IOMODE_S 24 +#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG0_IOMODE_INV 0x01000000 +#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG0_EDGE_DET_W 2 +#define IOC_IOCFG0_EDGE_DET_M 0x00030000 +#define IOC_IOCFG0_EDGE_DET_S 16 +#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG0_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG0_PULL_CTL_W 2 +#define IOC_IOCFG0_PULL_CTL_M 0x00006000 +#define IOC_IOCFG0_PULL_CTL_S 13 +#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG0_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG0_SLEW_RED 0x00001000 +#define IOC_IOCFG0_SLEW_RED_BITN 12 +#define IOC_IOCFG0_SLEW_RED_M 0x00001000 +#define IOC_IOCFG0_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG0_IOCURR_W 2 +#define IOC_IOCFG0_IOCURR_M 0x00000C00 +#define IOC_IOCFG0_IOCURR_S 10 +#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG0_IOCURR_4MA 0x00000400 +#define IOC_IOCFG0_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG0_IOSTR_W 2 +#define IOC_IOCFG0_IOSTR_M 0x00000300 +#define IOC_IOCFG0_IOSTR_S 8 +#define IOC_IOCFG0_IOSTR_MAX 0x00000300 +#define IOC_IOCFG0_IOSTR_MED 0x00000200 +#define IOC_IOCFG0_IOSTR_MIN 0x00000100 +#define IOC_IOCFG0_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO0 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG0_PORT_ID_W 6 +#define IOC_IOCFG0_PORT_ID_M 0x0000003F +#define IOC_IOCFG0_PORT_ID_S 0 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG1 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG1_HYST_EN 0x40000000 +#define IOC_IOCFG1_HYST_EN_BITN 30 +#define IOC_IOCFG1_HYST_EN_M 0x40000000 +#define IOC_IOCFG1_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG1_IE 0x20000000 +#define IOC_IOCFG1_IE_BITN 29 +#define IOC_IOCFG1_IE_M 0x20000000 +#define IOC_IOCFG1_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG1_WU_CFG_W 2 +#define IOC_IOCFG1_WU_CFG_M 0x18000000 +#define IOC_IOCFG1_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG1_IOMODE_W 3 +#define IOC_IOCFG1_IOMODE_M 0x07000000 +#define IOC_IOCFG1_IOMODE_S 24 +#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG1_IOMODE_INV 0x01000000 +#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG1_EDGE_DET_W 2 +#define IOC_IOCFG1_EDGE_DET_M 0x00030000 +#define IOC_IOCFG1_EDGE_DET_S 16 +#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG1_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG1_PULL_CTL_W 2 +#define IOC_IOCFG1_PULL_CTL_M 0x00006000 +#define IOC_IOCFG1_PULL_CTL_S 13 +#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG1_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG1_SLEW_RED 0x00001000 +#define IOC_IOCFG1_SLEW_RED_BITN 12 +#define IOC_IOCFG1_SLEW_RED_M 0x00001000 +#define IOC_IOCFG1_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG1_IOCURR_W 2 +#define IOC_IOCFG1_IOCURR_M 0x00000C00 +#define IOC_IOCFG1_IOCURR_S 10 +#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG1_IOCURR_4MA 0x00000400 +#define IOC_IOCFG1_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG1_IOSTR_W 2 +#define IOC_IOCFG1_IOSTR_M 0x00000300 +#define IOC_IOCFG1_IOSTR_S 8 +#define IOC_IOCFG1_IOSTR_MAX 0x00000300 +#define IOC_IOCFG1_IOSTR_MED 0x00000200 +#define IOC_IOCFG1_IOSTR_MIN 0x00000100 +#define IOC_IOCFG1_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO1 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG1_PORT_ID_W 6 +#define IOC_IOCFG1_PORT_ID_M 0x0000003F +#define IOC_IOCFG1_PORT_ID_S 0 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG2 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG2_HYST_EN 0x40000000 +#define IOC_IOCFG2_HYST_EN_BITN 30 +#define IOC_IOCFG2_HYST_EN_M 0x40000000 +#define IOC_IOCFG2_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG2_IE 0x20000000 +#define IOC_IOCFG2_IE_BITN 29 +#define IOC_IOCFG2_IE_M 0x20000000 +#define IOC_IOCFG2_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG2_WU_CFG_W 2 +#define IOC_IOCFG2_WU_CFG_M 0x18000000 +#define IOC_IOCFG2_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG2_IOMODE_W 3 +#define IOC_IOCFG2_IOMODE_M 0x07000000 +#define IOC_IOCFG2_IOMODE_S 24 +#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG2_IOMODE_INV 0x01000000 +#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG2_EDGE_DET_W 2 +#define IOC_IOCFG2_EDGE_DET_M 0x00030000 +#define IOC_IOCFG2_EDGE_DET_S 16 +#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG2_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG2_PULL_CTL_W 2 +#define IOC_IOCFG2_PULL_CTL_M 0x00006000 +#define IOC_IOCFG2_PULL_CTL_S 13 +#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG2_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG2_SLEW_RED 0x00001000 +#define IOC_IOCFG2_SLEW_RED_BITN 12 +#define IOC_IOCFG2_SLEW_RED_M 0x00001000 +#define IOC_IOCFG2_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG2_IOCURR_W 2 +#define IOC_IOCFG2_IOCURR_M 0x00000C00 +#define IOC_IOCFG2_IOCURR_S 10 +#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG2_IOCURR_4MA 0x00000400 +#define IOC_IOCFG2_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG2_IOSTR_W 2 +#define IOC_IOCFG2_IOSTR_M 0x00000300 +#define IOC_IOCFG2_IOSTR_S 8 +#define IOC_IOCFG2_IOSTR_MAX 0x00000300 +#define IOC_IOCFG2_IOSTR_MED 0x00000200 +#define IOC_IOCFG2_IOSTR_MIN 0x00000100 +#define IOC_IOCFG2_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO2 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG2_PORT_ID_W 6 +#define IOC_IOCFG2_PORT_ID_M 0x0000003F +#define IOC_IOCFG2_PORT_ID_S 0 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG3 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG3_HYST_EN 0x40000000 +#define IOC_IOCFG3_HYST_EN_BITN 30 +#define IOC_IOCFG3_HYST_EN_M 0x40000000 +#define IOC_IOCFG3_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG3_IE 0x20000000 +#define IOC_IOCFG3_IE_BITN 29 +#define IOC_IOCFG3_IE_M 0x20000000 +#define IOC_IOCFG3_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG3_WU_CFG_W 2 +#define IOC_IOCFG3_WU_CFG_M 0x18000000 +#define IOC_IOCFG3_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG3_IOMODE_W 3 +#define IOC_IOCFG3_IOMODE_M 0x07000000 +#define IOC_IOCFG3_IOMODE_S 24 +#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG3_IOMODE_INV 0x01000000 +#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG3_EDGE_DET_W 2 +#define IOC_IOCFG3_EDGE_DET_M 0x00030000 +#define IOC_IOCFG3_EDGE_DET_S 16 +#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG3_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG3_PULL_CTL_W 2 +#define IOC_IOCFG3_PULL_CTL_M 0x00006000 +#define IOC_IOCFG3_PULL_CTL_S 13 +#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG3_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG3_SLEW_RED 0x00001000 +#define IOC_IOCFG3_SLEW_RED_BITN 12 +#define IOC_IOCFG3_SLEW_RED_M 0x00001000 +#define IOC_IOCFG3_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG3_IOCURR_W 2 +#define IOC_IOCFG3_IOCURR_M 0x00000C00 +#define IOC_IOCFG3_IOCURR_S 10 +#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG3_IOCURR_4MA 0x00000400 +#define IOC_IOCFG3_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG3_IOSTR_W 2 +#define IOC_IOCFG3_IOSTR_M 0x00000300 +#define IOC_IOCFG3_IOSTR_S 8 +#define IOC_IOCFG3_IOSTR_MAX 0x00000300 +#define IOC_IOCFG3_IOSTR_MED 0x00000200 +#define IOC_IOCFG3_IOSTR_MIN 0x00000100 +#define IOC_IOCFG3_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO3 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG3_PORT_ID_W 6 +#define IOC_IOCFG3_PORT_ID_M 0x0000003F +#define IOC_IOCFG3_PORT_ID_S 0 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG4 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG4_HYST_EN 0x40000000 +#define IOC_IOCFG4_HYST_EN_BITN 30 +#define IOC_IOCFG4_HYST_EN_M 0x40000000 +#define IOC_IOCFG4_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG4_IE 0x20000000 +#define IOC_IOCFG4_IE_BITN 29 +#define IOC_IOCFG4_IE_M 0x20000000 +#define IOC_IOCFG4_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG4_WU_CFG_W 2 +#define IOC_IOCFG4_WU_CFG_M 0x18000000 +#define IOC_IOCFG4_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG4_IOMODE_W 3 +#define IOC_IOCFG4_IOMODE_M 0x07000000 +#define IOC_IOCFG4_IOMODE_S 24 +#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG4_IOMODE_INV 0x01000000 +#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG4_EDGE_DET_W 2 +#define IOC_IOCFG4_EDGE_DET_M 0x00030000 +#define IOC_IOCFG4_EDGE_DET_S 16 +#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG4_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG4_PULL_CTL_W 2 +#define IOC_IOCFG4_PULL_CTL_M 0x00006000 +#define IOC_IOCFG4_PULL_CTL_S 13 +#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG4_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG4_SLEW_RED 0x00001000 +#define IOC_IOCFG4_SLEW_RED_BITN 12 +#define IOC_IOCFG4_SLEW_RED_M 0x00001000 +#define IOC_IOCFG4_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG4_IOCURR_W 2 +#define IOC_IOCFG4_IOCURR_M 0x00000C00 +#define IOC_IOCFG4_IOCURR_S 10 +#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG4_IOCURR_4MA 0x00000400 +#define IOC_IOCFG4_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG4_IOSTR_W 2 +#define IOC_IOCFG4_IOSTR_M 0x00000300 +#define IOC_IOCFG4_IOSTR_S 8 +#define IOC_IOCFG4_IOSTR_MAX 0x00000300 +#define IOC_IOCFG4_IOSTR_MED 0x00000200 +#define IOC_IOCFG4_IOSTR_MIN 0x00000100 +#define IOC_IOCFG4_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO4 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG4_PORT_ID_W 6 +#define IOC_IOCFG4_PORT_ID_M 0x0000003F +#define IOC_IOCFG4_PORT_ID_S 0 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG5 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG5_HYST_EN 0x40000000 +#define IOC_IOCFG5_HYST_EN_BITN 30 +#define IOC_IOCFG5_HYST_EN_M 0x40000000 +#define IOC_IOCFG5_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG5_IE 0x20000000 +#define IOC_IOCFG5_IE_BITN 29 +#define IOC_IOCFG5_IE_M 0x20000000 +#define IOC_IOCFG5_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG5_WU_CFG_W 2 +#define IOC_IOCFG5_WU_CFG_M 0x18000000 +#define IOC_IOCFG5_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG5_IOMODE_W 3 +#define IOC_IOCFG5_IOMODE_M 0x07000000 +#define IOC_IOCFG5_IOMODE_S 24 +#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG5_IOMODE_INV 0x01000000 +#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG5_EDGE_DET_W 2 +#define IOC_IOCFG5_EDGE_DET_M 0x00030000 +#define IOC_IOCFG5_EDGE_DET_S 16 +#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG5_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG5_PULL_CTL_W 2 +#define IOC_IOCFG5_PULL_CTL_M 0x00006000 +#define IOC_IOCFG5_PULL_CTL_S 13 +#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG5_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG5_SLEW_RED 0x00001000 +#define IOC_IOCFG5_SLEW_RED_BITN 12 +#define IOC_IOCFG5_SLEW_RED_M 0x00001000 +#define IOC_IOCFG5_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG5_IOCURR_W 2 +#define IOC_IOCFG5_IOCURR_M 0x00000C00 +#define IOC_IOCFG5_IOCURR_S 10 +#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG5_IOCURR_4MA 0x00000400 +#define IOC_IOCFG5_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG5_IOSTR_W 2 +#define IOC_IOCFG5_IOSTR_M 0x00000300 +#define IOC_IOCFG5_IOSTR_S 8 +#define IOC_IOCFG5_IOSTR_MAX 0x00000300 +#define IOC_IOCFG5_IOSTR_MED 0x00000200 +#define IOC_IOCFG5_IOSTR_MIN 0x00000100 +#define IOC_IOCFG5_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO5 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG5_PORT_ID_W 6 +#define IOC_IOCFG5_PORT_ID_M 0x0000003F +#define IOC_IOCFG5_PORT_ID_S 0 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG6 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG6_HYST_EN 0x40000000 +#define IOC_IOCFG6_HYST_EN_BITN 30 +#define IOC_IOCFG6_HYST_EN_M 0x40000000 +#define IOC_IOCFG6_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG6_IE 0x20000000 +#define IOC_IOCFG6_IE_BITN 29 +#define IOC_IOCFG6_IE_M 0x20000000 +#define IOC_IOCFG6_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG6_WU_CFG_W 2 +#define IOC_IOCFG6_WU_CFG_M 0x18000000 +#define IOC_IOCFG6_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG6_IOMODE_W 3 +#define IOC_IOCFG6_IOMODE_M 0x07000000 +#define IOC_IOCFG6_IOMODE_S 24 +#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG6_IOMODE_INV 0x01000000 +#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG6_EDGE_DET_W 2 +#define IOC_IOCFG6_EDGE_DET_M 0x00030000 +#define IOC_IOCFG6_EDGE_DET_S 16 +#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG6_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG6_PULL_CTL_W 2 +#define IOC_IOCFG6_PULL_CTL_M 0x00006000 +#define IOC_IOCFG6_PULL_CTL_S 13 +#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG6_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG6_SLEW_RED 0x00001000 +#define IOC_IOCFG6_SLEW_RED_BITN 12 +#define IOC_IOCFG6_SLEW_RED_M 0x00001000 +#define IOC_IOCFG6_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG6_IOCURR_W 2 +#define IOC_IOCFG6_IOCURR_M 0x00000C00 +#define IOC_IOCFG6_IOCURR_S 10 +#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG6_IOCURR_4MA 0x00000400 +#define IOC_IOCFG6_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG6_IOSTR_W 2 +#define IOC_IOCFG6_IOSTR_M 0x00000300 +#define IOC_IOCFG6_IOSTR_S 8 +#define IOC_IOCFG6_IOSTR_MAX 0x00000300 +#define IOC_IOCFG6_IOSTR_MED 0x00000200 +#define IOC_IOCFG6_IOSTR_MIN 0x00000100 +#define IOC_IOCFG6_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO6 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG6_PORT_ID_W 6 +#define IOC_IOCFG6_PORT_ID_M 0x0000003F +#define IOC_IOCFG6_PORT_ID_S 0 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG7 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG7_HYST_EN 0x40000000 +#define IOC_IOCFG7_HYST_EN_BITN 30 +#define IOC_IOCFG7_HYST_EN_M 0x40000000 +#define IOC_IOCFG7_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG7_IE 0x20000000 +#define IOC_IOCFG7_IE_BITN 29 +#define IOC_IOCFG7_IE_M 0x20000000 +#define IOC_IOCFG7_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG7_WU_CFG_W 2 +#define IOC_IOCFG7_WU_CFG_M 0x18000000 +#define IOC_IOCFG7_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG7_IOMODE_W 3 +#define IOC_IOCFG7_IOMODE_M 0x07000000 +#define IOC_IOCFG7_IOMODE_S 24 +#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG7_IOMODE_INV 0x01000000 +#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG7_EDGE_DET_W 2 +#define IOC_IOCFG7_EDGE_DET_M 0x00030000 +#define IOC_IOCFG7_EDGE_DET_S 16 +#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG7_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG7_PULL_CTL_W 2 +#define IOC_IOCFG7_PULL_CTL_M 0x00006000 +#define IOC_IOCFG7_PULL_CTL_S 13 +#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG7_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG7_SLEW_RED 0x00001000 +#define IOC_IOCFG7_SLEW_RED_BITN 12 +#define IOC_IOCFG7_SLEW_RED_M 0x00001000 +#define IOC_IOCFG7_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG7_IOCURR_W 2 +#define IOC_IOCFG7_IOCURR_M 0x00000C00 +#define IOC_IOCFG7_IOCURR_S 10 +#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG7_IOCURR_4MA 0x00000400 +#define IOC_IOCFG7_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG7_IOSTR_W 2 +#define IOC_IOCFG7_IOSTR_M 0x00000300 +#define IOC_IOCFG7_IOSTR_S 8 +#define IOC_IOCFG7_IOSTR_MAX 0x00000300 +#define IOC_IOCFG7_IOSTR_MED 0x00000200 +#define IOC_IOCFG7_IOSTR_MIN 0x00000100 +#define IOC_IOCFG7_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO7 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG7_PORT_ID_W 6 +#define IOC_IOCFG7_PORT_ID_M 0x0000003F +#define IOC_IOCFG7_PORT_ID_S 0 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG8 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG8_HYST_EN 0x40000000 +#define IOC_IOCFG8_HYST_EN_BITN 30 +#define IOC_IOCFG8_HYST_EN_M 0x40000000 +#define IOC_IOCFG8_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG8_IE 0x20000000 +#define IOC_IOCFG8_IE_BITN 29 +#define IOC_IOCFG8_IE_M 0x20000000 +#define IOC_IOCFG8_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG8_WU_CFG_W 2 +#define IOC_IOCFG8_WU_CFG_M 0x18000000 +#define IOC_IOCFG8_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG8_IOMODE_W 3 +#define IOC_IOCFG8_IOMODE_M 0x07000000 +#define IOC_IOCFG8_IOMODE_S 24 +#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG8_IOMODE_INV 0x01000000 +#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG8_EDGE_DET_W 2 +#define IOC_IOCFG8_EDGE_DET_M 0x00030000 +#define IOC_IOCFG8_EDGE_DET_S 16 +#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG8_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG8_PULL_CTL_W 2 +#define IOC_IOCFG8_PULL_CTL_M 0x00006000 +#define IOC_IOCFG8_PULL_CTL_S 13 +#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG8_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG8_SLEW_RED 0x00001000 +#define IOC_IOCFG8_SLEW_RED_BITN 12 +#define IOC_IOCFG8_SLEW_RED_M 0x00001000 +#define IOC_IOCFG8_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG8_IOCURR_W 2 +#define IOC_IOCFG8_IOCURR_M 0x00000C00 +#define IOC_IOCFG8_IOCURR_S 10 +#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG8_IOCURR_4MA 0x00000400 +#define IOC_IOCFG8_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG8_IOSTR_W 2 +#define IOC_IOCFG8_IOSTR_M 0x00000300 +#define IOC_IOCFG8_IOSTR_S 8 +#define IOC_IOCFG8_IOSTR_MAX 0x00000300 +#define IOC_IOCFG8_IOSTR_MED 0x00000200 +#define IOC_IOCFG8_IOSTR_MIN 0x00000100 +#define IOC_IOCFG8_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO8 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG8_PORT_ID_W 6 +#define IOC_IOCFG8_PORT_ID_M 0x0000003F +#define IOC_IOCFG8_PORT_ID_S 0 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG9 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG9_HYST_EN 0x40000000 +#define IOC_IOCFG9_HYST_EN_BITN 30 +#define IOC_IOCFG9_HYST_EN_M 0x40000000 +#define IOC_IOCFG9_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG9_IE 0x20000000 +#define IOC_IOCFG9_IE_BITN 29 +#define IOC_IOCFG9_IE_M 0x20000000 +#define IOC_IOCFG9_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG9_WU_CFG_W 2 +#define IOC_IOCFG9_WU_CFG_M 0x18000000 +#define IOC_IOCFG9_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG9_IOMODE_W 3 +#define IOC_IOCFG9_IOMODE_M 0x07000000 +#define IOC_IOCFG9_IOMODE_S 24 +#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG9_IOMODE_INV 0x01000000 +#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG9_EDGE_DET_W 2 +#define IOC_IOCFG9_EDGE_DET_M 0x00030000 +#define IOC_IOCFG9_EDGE_DET_S 16 +#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG9_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG9_PULL_CTL_W 2 +#define IOC_IOCFG9_PULL_CTL_M 0x00006000 +#define IOC_IOCFG9_PULL_CTL_S 13 +#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG9_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG9_SLEW_RED 0x00001000 +#define IOC_IOCFG9_SLEW_RED_BITN 12 +#define IOC_IOCFG9_SLEW_RED_M 0x00001000 +#define IOC_IOCFG9_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG9_IOCURR_W 2 +#define IOC_IOCFG9_IOCURR_M 0x00000C00 +#define IOC_IOCFG9_IOCURR_S 10 +#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG9_IOCURR_4MA 0x00000400 +#define IOC_IOCFG9_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG9_IOSTR_W 2 +#define IOC_IOCFG9_IOSTR_M 0x00000300 +#define IOC_IOCFG9_IOSTR_S 8 +#define IOC_IOCFG9_IOSTR_MAX 0x00000300 +#define IOC_IOCFG9_IOSTR_MED 0x00000200 +#define IOC_IOCFG9_IOSTR_MIN 0x00000100 +#define IOC_IOCFG9_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO9 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG9_PORT_ID_W 6 +#define IOC_IOCFG9_PORT_ID_M 0x0000003F +#define IOC_IOCFG9_PORT_ID_S 0 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG10 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG10_HYST_EN 0x40000000 +#define IOC_IOCFG10_HYST_EN_BITN 30 +#define IOC_IOCFG10_HYST_EN_M 0x40000000 +#define IOC_IOCFG10_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG10_IE 0x20000000 +#define IOC_IOCFG10_IE_BITN 29 +#define IOC_IOCFG10_IE_M 0x20000000 +#define IOC_IOCFG10_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG10_WU_CFG_W 2 +#define IOC_IOCFG10_WU_CFG_M 0x18000000 +#define IOC_IOCFG10_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG10_IOMODE_W 3 +#define IOC_IOCFG10_IOMODE_M 0x07000000 +#define IOC_IOCFG10_IOMODE_S 24 +#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG10_IOMODE_INV 0x01000000 +#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG10_EDGE_DET_W 2 +#define IOC_IOCFG10_EDGE_DET_M 0x00030000 +#define IOC_IOCFG10_EDGE_DET_S 16 +#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG10_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG10_PULL_CTL_W 2 +#define IOC_IOCFG10_PULL_CTL_M 0x00006000 +#define IOC_IOCFG10_PULL_CTL_S 13 +#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG10_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG10_SLEW_RED 0x00001000 +#define IOC_IOCFG10_SLEW_RED_BITN 12 +#define IOC_IOCFG10_SLEW_RED_M 0x00001000 +#define IOC_IOCFG10_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG10_IOCURR_W 2 +#define IOC_IOCFG10_IOCURR_M 0x00000C00 +#define IOC_IOCFG10_IOCURR_S 10 +#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG10_IOCURR_4MA 0x00000400 +#define IOC_IOCFG10_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG10_IOSTR_W 2 +#define IOC_IOCFG10_IOSTR_M 0x00000300 +#define IOC_IOCFG10_IOSTR_S 8 +#define IOC_IOCFG10_IOSTR_MAX 0x00000300 +#define IOC_IOCFG10_IOSTR_MED 0x00000200 +#define IOC_IOCFG10_IOSTR_MIN 0x00000100 +#define IOC_IOCFG10_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO10 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG10_PORT_ID_W 6 +#define IOC_IOCFG10_PORT_ID_M 0x0000003F +#define IOC_IOCFG10_PORT_ID_S 0 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG11 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG11_HYST_EN 0x40000000 +#define IOC_IOCFG11_HYST_EN_BITN 30 +#define IOC_IOCFG11_HYST_EN_M 0x40000000 +#define IOC_IOCFG11_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG11_IE 0x20000000 +#define IOC_IOCFG11_IE_BITN 29 +#define IOC_IOCFG11_IE_M 0x20000000 +#define IOC_IOCFG11_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG11_WU_CFG_W 2 +#define IOC_IOCFG11_WU_CFG_M 0x18000000 +#define IOC_IOCFG11_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG11_IOMODE_W 3 +#define IOC_IOCFG11_IOMODE_M 0x07000000 +#define IOC_IOCFG11_IOMODE_S 24 +#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG11_IOMODE_INV 0x01000000 +#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG11_EDGE_DET_W 2 +#define IOC_IOCFG11_EDGE_DET_M 0x00030000 +#define IOC_IOCFG11_EDGE_DET_S 16 +#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG11_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG11_PULL_CTL_W 2 +#define IOC_IOCFG11_PULL_CTL_M 0x00006000 +#define IOC_IOCFG11_PULL_CTL_S 13 +#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG11_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG11_SLEW_RED 0x00001000 +#define IOC_IOCFG11_SLEW_RED_BITN 12 +#define IOC_IOCFG11_SLEW_RED_M 0x00001000 +#define IOC_IOCFG11_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG11_IOCURR_W 2 +#define IOC_IOCFG11_IOCURR_M 0x00000C00 +#define IOC_IOCFG11_IOCURR_S 10 +#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG11_IOCURR_4MA 0x00000400 +#define IOC_IOCFG11_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG11_IOSTR_W 2 +#define IOC_IOCFG11_IOSTR_M 0x00000300 +#define IOC_IOCFG11_IOSTR_S 8 +#define IOC_IOCFG11_IOSTR_MAX 0x00000300 +#define IOC_IOCFG11_IOSTR_MED 0x00000200 +#define IOC_IOCFG11_IOSTR_MIN 0x00000100 +#define IOC_IOCFG11_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO11 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG11_PORT_ID_W 6 +#define IOC_IOCFG11_PORT_ID_M 0x0000003F +#define IOC_IOCFG11_PORT_ID_S 0 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG12 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG12_HYST_EN 0x40000000 +#define IOC_IOCFG12_HYST_EN_BITN 30 +#define IOC_IOCFG12_HYST_EN_M 0x40000000 +#define IOC_IOCFG12_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG12_IE 0x20000000 +#define IOC_IOCFG12_IE_BITN 29 +#define IOC_IOCFG12_IE_M 0x20000000 +#define IOC_IOCFG12_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG12_WU_CFG_W 2 +#define IOC_IOCFG12_WU_CFG_M 0x18000000 +#define IOC_IOCFG12_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG12_IOMODE_W 3 +#define IOC_IOCFG12_IOMODE_M 0x07000000 +#define IOC_IOCFG12_IOMODE_S 24 +#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG12_IOMODE_INV 0x01000000 +#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG12_EDGE_DET_W 2 +#define IOC_IOCFG12_EDGE_DET_M 0x00030000 +#define IOC_IOCFG12_EDGE_DET_S 16 +#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG12_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG12_PULL_CTL_W 2 +#define IOC_IOCFG12_PULL_CTL_M 0x00006000 +#define IOC_IOCFG12_PULL_CTL_S 13 +#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG12_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG12_SLEW_RED 0x00001000 +#define IOC_IOCFG12_SLEW_RED_BITN 12 +#define IOC_IOCFG12_SLEW_RED_M 0x00001000 +#define IOC_IOCFG12_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG12_IOCURR_W 2 +#define IOC_IOCFG12_IOCURR_M 0x00000C00 +#define IOC_IOCFG12_IOCURR_S 10 +#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG12_IOCURR_4MA 0x00000400 +#define IOC_IOCFG12_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG12_IOSTR_W 2 +#define IOC_IOCFG12_IOSTR_M 0x00000300 +#define IOC_IOCFG12_IOSTR_S 8 +#define IOC_IOCFG12_IOSTR_MAX 0x00000300 +#define IOC_IOCFG12_IOSTR_MED 0x00000200 +#define IOC_IOCFG12_IOSTR_MIN 0x00000100 +#define IOC_IOCFG12_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO12 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG12_PORT_ID_W 6 +#define IOC_IOCFG12_PORT_ID_M 0x0000003F +#define IOC_IOCFG12_PORT_ID_S 0 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG13 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG13_HYST_EN 0x40000000 +#define IOC_IOCFG13_HYST_EN_BITN 30 +#define IOC_IOCFG13_HYST_EN_M 0x40000000 +#define IOC_IOCFG13_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG13_IE 0x20000000 +#define IOC_IOCFG13_IE_BITN 29 +#define IOC_IOCFG13_IE_M 0x20000000 +#define IOC_IOCFG13_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG13_WU_CFG_W 2 +#define IOC_IOCFG13_WU_CFG_M 0x18000000 +#define IOC_IOCFG13_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG13_IOMODE_W 3 +#define IOC_IOCFG13_IOMODE_M 0x07000000 +#define IOC_IOCFG13_IOMODE_S 24 +#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG13_IOMODE_INV 0x01000000 +#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG13_EDGE_DET_W 2 +#define IOC_IOCFG13_EDGE_DET_M 0x00030000 +#define IOC_IOCFG13_EDGE_DET_S 16 +#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG13_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG13_PULL_CTL_W 2 +#define IOC_IOCFG13_PULL_CTL_M 0x00006000 +#define IOC_IOCFG13_PULL_CTL_S 13 +#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG13_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG13_SLEW_RED 0x00001000 +#define IOC_IOCFG13_SLEW_RED_BITN 12 +#define IOC_IOCFG13_SLEW_RED_M 0x00001000 +#define IOC_IOCFG13_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG13_IOCURR_W 2 +#define IOC_IOCFG13_IOCURR_M 0x00000C00 +#define IOC_IOCFG13_IOCURR_S 10 +#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG13_IOCURR_4MA 0x00000400 +#define IOC_IOCFG13_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG13_IOSTR_W 2 +#define IOC_IOCFG13_IOSTR_M 0x00000300 +#define IOC_IOCFG13_IOSTR_S 8 +#define IOC_IOCFG13_IOSTR_MAX 0x00000300 +#define IOC_IOCFG13_IOSTR_MED 0x00000200 +#define IOC_IOCFG13_IOSTR_MIN 0x00000100 +#define IOC_IOCFG13_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO13 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG13_PORT_ID_W 6 +#define IOC_IOCFG13_PORT_ID_M 0x0000003F +#define IOC_IOCFG13_PORT_ID_S 0 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG14 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG14_HYST_EN 0x40000000 +#define IOC_IOCFG14_HYST_EN_BITN 30 +#define IOC_IOCFG14_HYST_EN_M 0x40000000 +#define IOC_IOCFG14_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG14_IE 0x20000000 +#define IOC_IOCFG14_IE_BITN 29 +#define IOC_IOCFG14_IE_M 0x20000000 +#define IOC_IOCFG14_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG14_WU_CFG_W 2 +#define IOC_IOCFG14_WU_CFG_M 0x18000000 +#define IOC_IOCFG14_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG14_IOMODE_W 3 +#define IOC_IOCFG14_IOMODE_M 0x07000000 +#define IOC_IOCFG14_IOMODE_S 24 +#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG14_IOMODE_INV 0x01000000 +#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG14_EDGE_DET_W 2 +#define IOC_IOCFG14_EDGE_DET_M 0x00030000 +#define IOC_IOCFG14_EDGE_DET_S 16 +#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG14_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG14_PULL_CTL_W 2 +#define IOC_IOCFG14_PULL_CTL_M 0x00006000 +#define IOC_IOCFG14_PULL_CTL_S 13 +#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG14_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG14_SLEW_RED 0x00001000 +#define IOC_IOCFG14_SLEW_RED_BITN 12 +#define IOC_IOCFG14_SLEW_RED_M 0x00001000 +#define IOC_IOCFG14_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG14_IOCURR_W 2 +#define IOC_IOCFG14_IOCURR_M 0x00000C00 +#define IOC_IOCFG14_IOCURR_S 10 +#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG14_IOCURR_4MA 0x00000400 +#define IOC_IOCFG14_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG14_IOSTR_W 2 +#define IOC_IOCFG14_IOSTR_M 0x00000300 +#define IOC_IOCFG14_IOSTR_S 8 +#define IOC_IOCFG14_IOSTR_MAX 0x00000300 +#define IOC_IOCFG14_IOSTR_MED 0x00000200 +#define IOC_IOCFG14_IOSTR_MIN 0x00000100 +#define IOC_IOCFG14_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO14 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG14_PORT_ID_W 6 +#define IOC_IOCFG14_PORT_ID_M 0x0000003F +#define IOC_IOCFG14_PORT_ID_S 0 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG15 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG15_HYST_EN 0x40000000 +#define IOC_IOCFG15_HYST_EN_BITN 30 +#define IOC_IOCFG15_HYST_EN_M 0x40000000 +#define IOC_IOCFG15_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG15_IE 0x20000000 +#define IOC_IOCFG15_IE_BITN 29 +#define IOC_IOCFG15_IE_M 0x20000000 +#define IOC_IOCFG15_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG15_WU_CFG_W 2 +#define IOC_IOCFG15_WU_CFG_M 0x18000000 +#define IOC_IOCFG15_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG15_IOMODE_W 3 +#define IOC_IOCFG15_IOMODE_M 0x07000000 +#define IOC_IOCFG15_IOMODE_S 24 +#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG15_IOMODE_INV 0x01000000 +#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG15_EDGE_DET_W 2 +#define IOC_IOCFG15_EDGE_DET_M 0x00030000 +#define IOC_IOCFG15_EDGE_DET_S 16 +#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG15_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG15_PULL_CTL_W 2 +#define IOC_IOCFG15_PULL_CTL_M 0x00006000 +#define IOC_IOCFG15_PULL_CTL_S 13 +#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG15_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG15_SLEW_RED 0x00001000 +#define IOC_IOCFG15_SLEW_RED_BITN 12 +#define IOC_IOCFG15_SLEW_RED_M 0x00001000 +#define IOC_IOCFG15_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG15_IOCURR_W 2 +#define IOC_IOCFG15_IOCURR_M 0x00000C00 +#define IOC_IOCFG15_IOCURR_S 10 +#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG15_IOCURR_4MA 0x00000400 +#define IOC_IOCFG15_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG15_IOSTR_W 2 +#define IOC_IOCFG15_IOSTR_M 0x00000300 +#define IOC_IOCFG15_IOSTR_S 8 +#define IOC_IOCFG15_IOSTR_MAX 0x00000300 +#define IOC_IOCFG15_IOSTR_MED 0x00000200 +#define IOC_IOCFG15_IOSTR_MIN 0x00000100 +#define IOC_IOCFG15_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO15 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG15_PORT_ID_W 6 +#define IOC_IOCFG15_PORT_ID_M 0x0000003F +#define IOC_IOCFG15_PORT_ID_S 0 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG16 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG16_HYST_EN 0x40000000 +#define IOC_IOCFG16_HYST_EN_BITN 30 +#define IOC_IOCFG16_HYST_EN_M 0x40000000 +#define IOC_IOCFG16_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG16_IE 0x20000000 +#define IOC_IOCFG16_IE_BITN 29 +#define IOC_IOCFG16_IE_M 0x20000000 +#define IOC_IOCFG16_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG16_WU_CFG_W 2 +#define IOC_IOCFG16_WU_CFG_M 0x18000000 +#define IOC_IOCFG16_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG16_IOMODE_W 3 +#define IOC_IOCFG16_IOMODE_M 0x07000000 +#define IOC_IOCFG16_IOMODE_S 24 +#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG16_IOMODE_INV 0x01000000 +#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG16_EDGE_DET_W 2 +#define IOC_IOCFG16_EDGE_DET_M 0x00030000 +#define IOC_IOCFG16_EDGE_DET_S 16 +#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG16_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG16_PULL_CTL_W 2 +#define IOC_IOCFG16_PULL_CTL_M 0x00006000 +#define IOC_IOCFG16_PULL_CTL_S 13 +#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG16_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG16_SLEW_RED 0x00001000 +#define IOC_IOCFG16_SLEW_RED_BITN 12 +#define IOC_IOCFG16_SLEW_RED_M 0x00001000 +#define IOC_IOCFG16_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG16_IOCURR_W 2 +#define IOC_IOCFG16_IOCURR_M 0x00000C00 +#define IOC_IOCFG16_IOCURR_S 10 +#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG16_IOCURR_4MA 0x00000400 +#define IOC_IOCFG16_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG16_IOSTR_W 2 +#define IOC_IOCFG16_IOSTR_M 0x00000300 +#define IOC_IOCFG16_IOSTR_S 8 +#define IOC_IOCFG16_IOSTR_MAX 0x00000300 +#define IOC_IOCFG16_IOSTR_MED 0x00000200 +#define IOC_IOCFG16_IOSTR_MIN 0x00000100 +#define IOC_IOCFG16_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO16 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG16_PORT_ID_W 6 +#define IOC_IOCFG16_PORT_ID_M 0x0000003F +#define IOC_IOCFG16_PORT_ID_S 0 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG17 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG17_HYST_EN 0x40000000 +#define IOC_IOCFG17_HYST_EN_BITN 30 +#define IOC_IOCFG17_HYST_EN_M 0x40000000 +#define IOC_IOCFG17_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG17_IE 0x20000000 +#define IOC_IOCFG17_IE_BITN 29 +#define IOC_IOCFG17_IE_M 0x20000000 +#define IOC_IOCFG17_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG17_WU_CFG_W 2 +#define IOC_IOCFG17_WU_CFG_M 0x18000000 +#define IOC_IOCFG17_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG17_IOMODE_W 3 +#define IOC_IOCFG17_IOMODE_M 0x07000000 +#define IOC_IOCFG17_IOMODE_S 24 +#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG17_IOMODE_INV 0x01000000 +#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG17_EDGE_DET_W 2 +#define IOC_IOCFG17_EDGE_DET_M 0x00030000 +#define IOC_IOCFG17_EDGE_DET_S 16 +#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG17_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG17_PULL_CTL_W 2 +#define IOC_IOCFG17_PULL_CTL_M 0x00006000 +#define IOC_IOCFG17_PULL_CTL_S 13 +#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG17_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG17_SLEW_RED 0x00001000 +#define IOC_IOCFG17_SLEW_RED_BITN 12 +#define IOC_IOCFG17_SLEW_RED_M 0x00001000 +#define IOC_IOCFG17_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG17_IOCURR_W 2 +#define IOC_IOCFG17_IOCURR_M 0x00000C00 +#define IOC_IOCFG17_IOCURR_S 10 +#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG17_IOCURR_4MA 0x00000400 +#define IOC_IOCFG17_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG17_IOSTR_W 2 +#define IOC_IOCFG17_IOSTR_M 0x00000300 +#define IOC_IOCFG17_IOSTR_S 8 +#define IOC_IOCFG17_IOSTR_MAX 0x00000300 +#define IOC_IOCFG17_IOSTR_MED 0x00000200 +#define IOC_IOCFG17_IOSTR_MIN 0x00000100 +#define IOC_IOCFG17_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO17 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG17_PORT_ID_W 6 +#define IOC_IOCFG17_PORT_ID_M 0x0000003F +#define IOC_IOCFG17_PORT_ID_S 0 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG18 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG18_HYST_EN 0x40000000 +#define IOC_IOCFG18_HYST_EN_BITN 30 +#define IOC_IOCFG18_HYST_EN_M 0x40000000 +#define IOC_IOCFG18_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG18_IE 0x20000000 +#define IOC_IOCFG18_IE_BITN 29 +#define IOC_IOCFG18_IE_M 0x20000000 +#define IOC_IOCFG18_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG18_WU_CFG_W 2 +#define IOC_IOCFG18_WU_CFG_M 0x18000000 +#define IOC_IOCFG18_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG18_IOMODE_W 3 +#define IOC_IOCFG18_IOMODE_M 0x07000000 +#define IOC_IOCFG18_IOMODE_S 24 +#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG18_IOMODE_INV 0x01000000 +#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG18_EDGE_DET_W 2 +#define IOC_IOCFG18_EDGE_DET_M 0x00030000 +#define IOC_IOCFG18_EDGE_DET_S 16 +#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG18_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG18_PULL_CTL_W 2 +#define IOC_IOCFG18_PULL_CTL_M 0x00006000 +#define IOC_IOCFG18_PULL_CTL_S 13 +#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG18_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG18_SLEW_RED 0x00001000 +#define IOC_IOCFG18_SLEW_RED_BITN 12 +#define IOC_IOCFG18_SLEW_RED_M 0x00001000 +#define IOC_IOCFG18_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG18_IOCURR_W 2 +#define IOC_IOCFG18_IOCURR_M 0x00000C00 +#define IOC_IOCFG18_IOCURR_S 10 +#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG18_IOCURR_4MA 0x00000400 +#define IOC_IOCFG18_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG18_IOSTR_W 2 +#define IOC_IOCFG18_IOSTR_M 0x00000300 +#define IOC_IOCFG18_IOSTR_S 8 +#define IOC_IOCFG18_IOSTR_MAX 0x00000300 +#define IOC_IOCFG18_IOSTR_MED 0x00000200 +#define IOC_IOCFG18_IOSTR_MIN 0x00000100 +#define IOC_IOCFG18_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO18 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG18_PORT_ID_W 6 +#define IOC_IOCFG18_PORT_ID_M 0x0000003F +#define IOC_IOCFG18_PORT_ID_S 0 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG19 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG19_HYST_EN 0x40000000 +#define IOC_IOCFG19_HYST_EN_BITN 30 +#define IOC_IOCFG19_HYST_EN_M 0x40000000 +#define IOC_IOCFG19_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG19_IE 0x20000000 +#define IOC_IOCFG19_IE_BITN 29 +#define IOC_IOCFG19_IE_M 0x20000000 +#define IOC_IOCFG19_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG19_WU_CFG_W 2 +#define IOC_IOCFG19_WU_CFG_M 0x18000000 +#define IOC_IOCFG19_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG19_IOMODE_W 3 +#define IOC_IOCFG19_IOMODE_M 0x07000000 +#define IOC_IOCFG19_IOMODE_S 24 +#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG19_IOMODE_INV 0x01000000 +#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG19_EDGE_DET_W 2 +#define IOC_IOCFG19_EDGE_DET_M 0x00030000 +#define IOC_IOCFG19_EDGE_DET_S 16 +#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG19_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG19_PULL_CTL_W 2 +#define IOC_IOCFG19_PULL_CTL_M 0x00006000 +#define IOC_IOCFG19_PULL_CTL_S 13 +#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG19_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG19_SLEW_RED 0x00001000 +#define IOC_IOCFG19_SLEW_RED_BITN 12 +#define IOC_IOCFG19_SLEW_RED_M 0x00001000 +#define IOC_IOCFG19_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG19_IOCURR_W 2 +#define IOC_IOCFG19_IOCURR_M 0x00000C00 +#define IOC_IOCFG19_IOCURR_S 10 +#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG19_IOCURR_4MA 0x00000400 +#define IOC_IOCFG19_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG19_IOSTR_W 2 +#define IOC_IOCFG19_IOSTR_M 0x00000300 +#define IOC_IOCFG19_IOSTR_S 8 +#define IOC_IOCFG19_IOSTR_MAX 0x00000300 +#define IOC_IOCFG19_IOSTR_MED 0x00000200 +#define IOC_IOCFG19_IOSTR_MIN 0x00000100 +#define IOC_IOCFG19_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO19 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG19_PORT_ID_W 6 +#define IOC_IOCFG19_PORT_ID_M 0x0000003F +#define IOC_IOCFG19_PORT_ID_S 0 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG20 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG20_HYST_EN 0x40000000 +#define IOC_IOCFG20_HYST_EN_BITN 30 +#define IOC_IOCFG20_HYST_EN_M 0x40000000 +#define IOC_IOCFG20_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG20_IE 0x20000000 +#define IOC_IOCFG20_IE_BITN 29 +#define IOC_IOCFG20_IE_M 0x20000000 +#define IOC_IOCFG20_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG20_WU_CFG_W 2 +#define IOC_IOCFG20_WU_CFG_M 0x18000000 +#define IOC_IOCFG20_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG20_IOMODE_W 3 +#define IOC_IOCFG20_IOMODE_M 0x07000000 +#define IOC_IOCFG20_IOMODE_S 24 +#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG20_IOMODE_INV 0x01000000 +#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG20_EDGE_DET_W 2 +#define IOC_IOCFG20_EDGE_DET_M 0x00030000 +#define IOC_IOCFG20_EDGE_DET_S 16 +#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG20_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG20_PULL_CTL_W 2 +#define IOC_IOCFG20_PULL_CTL_M 0x00006000 +#define IOC_IOCFG20_PULL_CTL_S 13 +#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG20_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG20_SLEW_RED 0x00001000 +#define IOC_IOCFG20_SLEW_RED_BITN 12 +#define IOC_IOCFG20_SLEW_RED_M 0x00001000 +#define IOC_IOCFG20_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG20_IOCURR_W 2 +#define IOC_IOCFG20_IOCURR_M 0x00000C00 +#define IOC_IOCFG20_IOCURR_S 10 +#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG20_IOCURR_4MA 0x00000400 +#define IOC_IOCFG20_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG20_IOSTR_W 2 +#define IOC_IOCFG20_IOSTR_M 0x00000300 +#define IOC_IOCFG20_IOSTR_S 8 +#define IOC_IOCFG20_IOSTR_MAX 0x00000300 +#define IOC_IOCFG20_IOSTR_MED 0x00000200 +#define IOC_IOCFG20_IOSTR_MIN 0x00000100 +#define IOC_IOCFG20_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO20 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG20_PORT_ID_W 6 +#define IOC_IOCFG20_PORT_ID_M 0x0000003F +#define IOC_IOCFG20_PORT_ID_S 0 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG21 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG21_HYST_EN 0x40000000 +#define IOC_IOCFG21_HYST_EN_BITN 30 +#define IOC_IOCFG21_HYST_EN_M 0x40000000 +#define IOC_IOCFG21_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG21_IE 0x20000000 +#define IOC_IOCFG21_IE_BITN 29 +#define IOC_IOCFG21_IE_M 0x20000000 +#define IOC_IOCFG21_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG21_WU_CFG_W 2 +#define IOC_IOCFG21_WU_CFG_M 0x18000000 +#define IOC_IOCFG21_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG21_IOMODE_W 3 +#define IOC_IOCFG21_IOMODE_M 0x07000000 +#define IOC_IOCFG21_IOMODE_S 24 +#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG21_IOMODE_INV 0x01000000 +#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG21_EDGE_DET_W 2 +#define IOC_IOCFG21_EDGE_DET_M 0x00030000 +#define IOC_IOCFG21_EDGE_DET_S 16 +#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG21_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG21_PULL_CTL_W 2 +#define IOC_IOCFG21_PULL_CTL_M 0x00006000 +#define IOC_IOCFG21_PULL_CTL_S 13 +#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG21_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG21_SLEW_RED 0x00001000 +#define IOC_IOCFG21_SLEW_RED_BITN 12 +#define IOC_IOCFG21_SLEW_RED_M 0x00001000 +#define IOC_IOCFG21_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG21_IOCURR_W 2 +#define IOC_IOCFG21_IOCURR_M 0x00000C00 +#define IOC_IOCFG21_IOCURR_S 10 +#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG21_IOCURR_4MA 0x00000400 +#define IOC_IOCFG21_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG21_IOSTR_W 2 +#define IOC_IOCFG21_IOSTR_M 0x00000300 +#define IOC_IOCFG21_IOSTR_S 8 +#define IOC_IOCFG21_IOSTR_MAX 0x00000300 +#define IOC_IOCFG21_IOSTR_MED 0x00000200 +#define IOC_IOCFG21_IOSTR_MIN 0x00000100 +#define IOC_IOCFG21_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO21 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG21_PORT_ID_W 6 +#define IOC_IOCFG21_PORT_ID_M 0x0000003F +#define IOC_IOCFG21_PORT_ID_S 0 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG22 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG22_HYST_EN 0x40000000 +#define IOC_IOCFG22_HYST_EN_BITN 30 +#define IOC_IOCFG22_HYST_EN_M 0x40000000 +#define IOC_IOCFG22_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG22_IE 0x20000000 +#define IOC_IOCFG22_IE_BITN 29 +#define IOC_IOCFG22_IE_M 0x20000000 +#define IOC_IOCFG22_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG22_WU_CFG_W 2 +#define IOC_IOCFG22_WU_CFG_M 0x18000000 +#define IOC_IOCFG22_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG22_IOMODE_W 3 +#define IOC_IOCFG22_IOMODE_M 0x07000000 +#define IOC_IOCFG22_IOMODE_S 24 +#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG22_IOMODE_INV 0x01000000 +#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG22_EDGE_DET_W 2 +#define IOC_IOCFG22_EDGE_DET_M 0x00030000 +#define IOC_IOCFG22_EDGE_DET_S 16 +#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG22_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG22_PULL_CTL_W 2 +#define IOC_IOCFG22_PULL_CTL_M 0x00006000 +#define IOC_IOCFG22_PULL_CTL_S 13 +#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG22_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG22_SLEW_RED 0x00001000 +#define IOC_IOCFG22_SLEW_RED_BITN 12 +#define IOC_IOCFG22_SLEW_RED_M 0x00001000 +#define IOC_IOCFG22_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG22_IOCURR_W 2 +#define IOC_IOCFG22_IOCURR_M 0x00000C00 +#define IOC_IOCFG22_IOCURR_S 10 +#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG22_IOCURR_4MA 0x00000400 +#define IOC_IOCFG22_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG22_IOSTR_W 2 +#define IOC_IOCFG22_IOSTR_M 0x00000300 +#define IOC_IOCFG22_IOSTR_S 8 +#define IOC_IOCFG22_IOSTR_MAX 0x00000300 +#define IOC_IOCFG22_IOSTR_MED 0x00000200 +#define IOC_IOCFG22_IOSTR_MIN 0x00000100 +#define IOC_IOCFG22_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO22 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG22_PORT_ID_W 6 +#define IOC_IOCFG22_PORT_ID_M 0x0000003F +#define IOC_IOCFG22_PORT_ID_S 0 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG23 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG23_HYST_EN 0x40000000 +#define IOC_IOCFG23_HYST_EN_BITN 30 +#define IOC_IOCFG23_HYST_EN_M 0x40000000 +#define IOC_IOCFG23_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG23_IE 0x20000000 +#define IOC_IOCFG23_IE_BITN 29 +#define IOC_IOCFG23_IE_M 0x20000000 +#define IOC_IOCFG23_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG23_WU_CFG_W 2 +#define IOC_IOCFG23_WU_CFG_M 0x18000000 +#define IOC_IOCFG23_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG23_IOMODE_W 3 +#define IOC_IOCFG23_IOMODE_M 0x07000000 +#define IOC_IOCFG23_IOMODE_S 24 +#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG23_IOMODE_INV 0x01000000 +#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG23_EDGE_DET_W 2 +#define IOC_IOCFG23_EDGE_DET_M 0x00030000 +#define IOC_IOCFG23_EDGE_DET_S 16 +#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG23_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG23_PULL_CTL_W 2 +#define IOC_IOCFG23_PULL_CTL_M 0x00006000 +#define IOC_IOCFG23_PULL_CTL_S 13 +#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG23_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG23_SLEW_RED 0x00001000 +#define IOC_IOCFG23_SLEW_RED_BITN 12 +#define IOC_IOCFG23_SLEW_RED_M 0x00001000 +#define IOC_IOCFG23_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG23_IOCURR_W 2 +#define IOC_IOCFG23_IOCURR_M 0x00000C00 +#define IOC_IOCFG23_IOCURR_S 10 +#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG23_IOCURR_4MA 0x00000400 +#define IOC_IOCFG23_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG23_IOSTR_W 2 +#define IOC_IOCFG23_IOSTR_M 0x00000300 +#define IOC_IOCFG23_IOSTR_S 8 +#define IOC_IOCFG23_IOSTR_MAX 0x00000300 +#define IOC_IOCFG23_IOSTR_MED 0x00000200 +#define IOC_IOCFG23_IOSTR_MIN 0x00000100 +#define IOC_IOCFG23_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO23 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG23_PORT_ID_W 6 +#define IOC_IOCFG23_PORT_ID_M 0x0000003F +#define IOC_IOCFG23_PORT_ID_S 0 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG24 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG24_HYST_EN 0x40000000 +#define IOC_IOCFG24_HYST_EN_BITN 30 +#define IOC_IOCFG24_HYST_EN_M 0x40000000 +#define IOC_IOCFG24_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG24_IE 0x20000000 +#define IOC_IOCFG24_IE_BITN 29 +#define IOC_IOCFG24_IE_M 0x20000000 +#define IOC_IOCFG24_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG24_WU_CFG_W 2 +#define IOC_IOCFG24_WU_CFG_M 0x18000000 +#define IOC_IOCFG24_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG24_IOMODE_W 3 +#define IOC_IOCFG24_IOMODE_M 0x07000000 +#define IOC_IOCFG24_IOMODE_S 24 +#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG24_IOMODE_INV 0x01000000 +#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG24_EDGE_DET_W 2 +#define IOC_IOCFG24_EDGE_DET_M 0x00030000 +#define IOC_IOCFG24_EDGE_DET_S 16 +#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG24_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG24_PULL_CTL_W 2 +#define IOC_IOCFG24_PULL_CTL_M 0x00006000 +#define IOC_IOCFG24_PULL_CTL_S 13 +#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG24_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG24_SLEW_RED 0x00001000 +#define IOC_IOCFG24_SLEW_RED_BITN 12 +#define IOC_IOCFG24_SLEW_RED_M 0x00001000 +#define IOC_IOCFG24_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG24_IOCURR_W 2 +#define IOC_IOCFG24_IOCURR_M 0x00000C00 +#define IOC_IOCFG24_IOCURR_S 10 +#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG24_IOCURR_4MA 0x00000400 +#define IOC_IOCFG24_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG24_IOSTR_W 2 +#define IOC_IOCFG24_IOSTR_M 0x00000300 +#define IOC_IOCFG24_IOSTR_S 8 +#define IOC_IOCFG24_IOSTR_MAX 0x00000300 +#define IOC_IOCFG24_IOSTR_MED 0x00000200 +#define IOC_IOCFG24_IOSTR_MIN 0x00000100 +#define IOC_IOCFG24_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO24 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG24_PORT_ID_W 6 +#define IOC_IOCFG24_PORT_ID_M 0x0000003F +#define IOC_IOCFG24_PORT_ID_S 0 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG25 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG25_HYST_EN 0x40000000 +#define IOC_IOCFG25_HYST_EN_BITN 30 +#define IOC_IOCFG25_HYST_EN_M 0x40000000 +#define IOC_IOCFG25_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG25_IE 0x20000000 +#define IOC_IOCFG25_IE_BITN 29 +#define IOC_IOCFG25_IE_M 0x20000000 +#define IOC_IOCFG25_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG25_WU_CFG_W 2 +#define IOC_IOCFG25_WU_CFG_M 0x18000000 +#define IOC_IOCFG25_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG25_IOMODE_W 3 +#define IOC_IOCFG25_IOMODE_M 0x07000000 +#define IOC_IOCFG25_IOMODE_S 24 +#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG25_IOMODE_INV 0x01000000 +#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG25_EDGE_DET_W 2 +#define IOC_IOCFG25_EDGE_DET_M 0x00030000 +#define IOC_IOCFG25_EDGE_DET_S 16 +#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG25_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG25_PULL_CTL_W 2 +#define IOC_IOCFG25_PULL_CTL_M 0x00006000 +#define IOC_IOCFG25_PULL_CTL_S 13 +#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG25_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG25_SLEW_RED 0x00001000 +#define IOC_IOCFG25_SLEW_RED_BITN 12 +#define IOC_IOCFG25_SLEW_RED_M 0x00001000 +#define IOC_IOCFG25_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG25_IOCURR_W 2 +#define IOC_IOCFG25_IOCURR_M 0x00000C00 +#define IOC_IOCFG25_IOCURR_S 10 +#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG25_IOCURR_4MA 0x00000400 +#define IOC_IOCFG25_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG25_IOSTR_W 2 +#define IOC_IOCFG25_IOSTR_M 0x00000300 +#define IOC_IOCFG25_IOSTR_S 8 +#define IOC_IOCFG25_IOSTR_MAX 0x00000300 +#define IOC_IOCFG25_IOSTR_MED 0x00000200 +#define IOC_IOCFG25_IOSTR_MIN 0x00000100 +#define IOC_IOCFG25_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO25 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG25_PORT_ID_W 6 +#define IOC_IOCFG25_PORT_ID_M 0x0000003F +#define IOC_IOCFG25_PORT_ID_S 0 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG26 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG26_HYST_EN 0x40000000 +#define IOC_IOCFG26_HYST_EN_BITN 30 +#define IOC_IOCFG26_HYST_EN_M 0x40000000 +#define IOC_IOCFG26_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG26_IE 0x20000000 +#define IOC_IOCFG26_IE_BITN 29 +#define IOC_IOCFG26_IE_M 0x20000000 +#define IOC_IOCFG26_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG26_WU_CFG_W 2 +#define IOC_IOCFG26_WU_CFG_M 0x18000000 +#define IOC_IOCFG26_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG26_IOMODE_W 3 +#define IOC_IOCFG26_IOMODE_M 0x07000000 +#define IOC_IOCFG26_IOMODE_S 24 +#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG26_IOMODE_INV 0x01000000 +#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG26_EDGE_DET_W 2 +#define IOC_IOCFG26_EDGE_DET_M 0x00030000 +#define IOC_IOCFG26_EDGE_DET_S 16 +#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG26_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG26_PULL_CTL_W 2 +#define IOC_IOCFG26_PULL_CTL_M 0x00006000 +#define IOC_IOCFG26_PULL_CTL_S 13 +#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG26_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG26_SLEW_RED 0x00001000 +#define IOC_IOCFG26_SLEW_RED_BITN 12 +#define IOC_IOCFG26_SLEW_RED_M 0x00001000 +#define IOC_IOCFG26_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG26_IOCURR_W 2 +#define IOC_IOCFG26_IOCURR_M 0x00000C00 +#define IOC_IOCFG26_IOCURR_S 10 +#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG26_IOCURR_4MA 0x00000400 +#define IOC_IOCFG26_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG26_IOSTR_W 2 +#define IOC_IOCFG26_IOSTR_M 0x00000300 +#define IOC_IOCFG26_IOSTR_S 8 +#define IOC_IOCFG26_IOSTR_MAX 0x00000300 +#define IOC_IOCFG26_IOSTR_MED 0x00000200 +#define IOC_IOCFG26_IOSTR_MIN 0x00000100 +#define IOC_IOCFG26_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO26 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG26_PORT_ID_W 6 +#define IOC_IOCFG26_PORT_ID_M 0x0000003F +#define IOC_IOCFG26_PORT_ID_S 0 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG27 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG27_HYST_EN 0x40000000 +#define IOC_IOCFG27_HYST_EN_BITN 30 +#define IOC_IOCFG27_HYST_EN_M 0x40000000 +#define IOC_IOCFG27_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG27_IE 0x20000000 +#define IOC_IOCFG27_IE_BITN 29 +#define IOC_IOCFG27_IE_M 0x20000000 +#define IOC_IOCFG27_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG27_WU_CFG_W 2 +#define IOC_IOCFG27_WU_CFG_M 0x18000000 +#define IOC_IOCFG27_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG27_IOMODE_W 3 +#define IOC_IOCFG27_IOMODE_M 0x07000000 +#define IOC_IOCFG27_IOMODE_S 24 +#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG27_IOMODE_INV 0x01000000 +#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG27_EDGE_DET_W 2 +#define IOC_IOCFG27_EDGE_DET_M 0x00030000 +#define IOC_IOCFG27_EDGE_DET_S 16 +#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG27_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG27_PULL_CTL_W 2 +#define IOC_IOCFG27_PULL_CTL_M 0x00006000 +#define IOC_IOCFG27_PULL_CTL_S 13 +#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG27_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG27_SLEW_RED 0x00001000 +#define IOC_IOCFG27_SLEW_RED_BITN 12 +#define IOC_IOCFG27_SLEW_RED_M 0x00001000 +#define IOC_IOCFG27_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG27_IOCURR_W 2 +#define IOC_IOCFG27_IOCURR_M 0x00000C00 +#define IOC_IOCFG27_IOCURR_S 10 +#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG27_IOCURR_4MA 0x00000400 +#define IOC_IOCFG27_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG27_IOSTR_W 2 +#define IOC_IOCFG27_IOSTR_M 0x00000300 +#define IOC_IOCFG27_IOSTR_S 8 +#define IOC_IOCFG27_IOSTR_MAX 0x00000300 +#define IOC_IOCFG27_IOSTR_MED 0x00000200 +#define IOC_IOCFG27_IOSTR_MIN 0x00000100 +#define IOC_IOCFG27_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO27 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG27_PORT_ID_W 6 +#define IOC_IOCFG27_PORT_ID_M 0x0000003F +#define IOC_IOCFG27_PORT_ID_S 0 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG28 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG28_HYST_EN 0x40000000 +#define IOC_IOCFG28_HYST_EN_BITN 30 +#define IOC_IOCFG28_HYST_EN_M 0x40000000 +#define IOC_IOCFG28_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG28_IE 0x20000000 +#define IOC_IOCFG28_IE_BITN 29 +#define IOC_IOCFG28_IE_M 0x20000000 +#define IOC_IOCFG28_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG28_WU_CFG_W 2 +#define IOC_IOCFG28_WU_CFG_M 0x18000000 +#define IOC_IOCFG28_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG28_IOMODE_W 3 +#define IOC_IOCFG28_IOMODE_M 0x07000000 +#define IOC_IOCFG28_IOMODE_S 24 +#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG28_IOMODE_INV 0x01000000 +#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG28_EDGE_DET_W 2 +#define IOC_IOCFG28_EDGE_DET_M 0x00030000 +#define IOC_IOCFG28_EDGE_DET_S 16 +#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG28_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG28_PULL_CTL_W 2 +#define IOC_IOCFG28_PULL_CTL_M 0x00006000 +#define IOC_IOCFG28_PULL_CTL_S 13 +#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG28_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG28_SLEW_RED 0x00001000 +#define IOC_IOCFG28_SLEW_RED_BITN 12 +#define IOC_IOCFG28_SLEW_RED_M 0x00001000 +#define IOC_IOCFG28_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG28_IOCURR_W 2 +#define IOC_IOCFG28_IOCURR_M 0x00000C00 +#define IOC_IOCFG28_IOCURR_S 10 +#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG28_IOCURR_4MA 0x00000400 +#define IOC_IOCFG28_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG28_IOSTR_W 2 +#define IOC_IOCFG28_IOSTR_M 0x00000300 +#define IOC_IOCFG28_IOSTR_S 8 +#define IOC_IOCFG28_IOSTR_MAX 0x00000300 +#define IOC_IOCFG28_IOSTR_MED 0x00000200 +#define IOC_IOCFG28_IOSTR_MIN 0x00000100 +#define IOC_IOCFG28_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO28 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG28_PORT_ID_W 6 +#define IOC_IOCFG28_PORT_ID_M 0x0000003F +#define IOC_IOCFG28_PORT_ID_S 0 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG29 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG29_HYST_EN 0x40000000 +#define IOC_IOCFG29_HYST_EN_BITN 30 +#define IOC_IOCFG29_HYST_EN_M 0x40000000 +#define IOC_IOCFG29_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG29_IE 0x20000000 +#define IOC_IOCFG29_IE_BITN 29 +#define IOC_IOCFG29_IE_M 0x20000000 +#define IOC_IOCFG29_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG29_WU_CFG_W 2 +#define IOC_IOCFG29_WU_CFG_M 0x18000000 +#define IOC_IOCFG29_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG29_IOMODE_W 3 +#define IOC_IOCFG29_IOMODE_M 0x07000000 +#define IOC_IOCFG29_IOMODE_S 24 +#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG29_IOMODE_INV 0x01000000 +#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG29_EDGE_DET_W 2 +#define IOC_IOCFG29_EDGE_DET_M 0x00030000 +#define IOC_IOCFG29_EDGE_DET_S 16 +#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG29_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG29_PULL_CTL_W 2 +#define IOC_IOCFG29_PULL_CTL_M 0x00006000 +#define IOC_IOCFG29_PULL_CTL_S 13 +#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG29_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG29_SLEW_RED 0x00001000 +#define IOC_IOCFG29_SLEW_RED_BITN 12 +#define IOC_IOCFG29_SLEW_RED_M 0x00001000 +#define IOC_IOCFG29_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG29_IOCURR_W 2 +#define IOC_IOCFG29_IOCURR_M 0x00000C00 +#define IOC_IOCFG29_IOCURR_S 10 +#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG29_IOCURR_4MA 0x00000400 +#define IOC_IOCFG29_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG29_IOSTR_W 2 +#define IOC_IOCFG29_IOSTR_M 0x00000300 +#define IOC_IOCFG29_IOSTR_S 8 +#define IOC_IOCFG29_IOSTR_MAX 0x00000300 +#define IOC_IOCFG29_IOSTR_MED 0x00000200 +#define IOC_IOCFG29_IOSTR_MIN 0x00000100 +#define IOC_IOCFG29_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO29 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG29_PORT_ID_W 6 +#define IOC_IOCFG29_PORT_ID_M 0x0000003F +#define IOC_IOCFG29_PORT_ID_S 0 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG30 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG30_HYST_EN 0x40000000 +#define IOC_IOCFG30_HYST_EN_BITN 30 +#define IOC_IOCFG30_HYST_EN_M 0x40000000 +#define IOC_IOCFG30_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG30_IE 0x20000000 +#define IOC_IOCFG30_IE_BITN 29 +#define IOC_IOCFG30_IE_M 0x20000000 +#define IOC_IOCFG30_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG30_WU_CFG_W 2 +#define IOC_IOCFG30_WU_CFG_M 0x18000000 +#define IOC_IOCFG30_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG30_IOMODE_W 3 +#define IOC_IOCFG30_IOMODE_M 0x07000000 +#define IOC_IOCFG30_IOMODE_S 24 +#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG30_IOMODE_INV 0x01000000 +#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG30_EDGE_DET_W 2 +#define IOC_IOCFG30_EDGE_DET_M 0x00030000 +#define IOC_IOCFG30_EDGE_DET_S 16 +#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG30_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG30_PULL_CTL_W 2 +#define IOC_IOCFG30_PULL_CTL_M 0x00006000 +#define IOC_IOCFG30_PULL_CTL_S 13 +#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG30_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG30_SLEW_RED 0x00001000 +#define IOC_IOCFG30_SLEW_RED_BITN 12 +#define IOC_IOCFG30_SLEW_RED_M 0x00001000 +#define IOC_IOCFG30_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG30_IOCURR_W 2 +#define IOC_IOCFG30_IOCURR_M 0x00000C00 +#define IOC_IOCFG30_IOCURR_S 10 +#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG30_IOCURR_4MA 0x00000400 +#define IOC_IOCFG30_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG30_IOSTR_W 2 +#define IOC_IOCFG30_IOSTR_M 0x00000300 +#define IOC_IOCFG30_IOSTR_S 8 +#define IOC_IOCFG30_IOSTR_MAX 0x00000300 +#define IOC_IOCFG30_IOSTR_MED 0x00000200 +#define IOC_IOCFG30_IOSTR_MIN 0x00000100 +#define IOC_IOCFG30_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO30 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG30_PORT_ID_W 6 +#define IOC_IOCFG30_PORT_ID_M 0x0000003F +#define IOC_IOCFG30_PORT_ID_S 0 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG31 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG31_HYST_EN 0x40000000 +#define IOC_IOCFG31_HYST_EN_BITN 30 +#define IOC_IOCFG31_HYST_EN_M 0x40000000 +#define IOC_IOCFG31_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG31_IE 0x20000000 +#define IOC_IOCFG31_IE_BITN 29 +#define IOC_IOCFG31_IE_M 0x20000000 +#define IOC_IOCFG31_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG31_WU_CFG_W 2 +#define IOC_IOCFG31_WU_CFG_M 0x18000000 +#define IOC_IOCFG31_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG31_IOMODE_W 3 +#define IOC_IOCFG31_IOMODE_M 0x07000000 +#define IOC_IOCFG31_IOMODE_S 24 +#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG31_IOMODE_INV 0x01000000 +#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG31_EDGE_DET_W 2 +#define IOC_IOCFG31_EDGE_DET_M 0x00030000 +#define IOC_IOCFG31_EDGE_DET_S 16 +#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG31_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG31_PULL_CTL_W 2 +#define IOC_IOCFG31_PULL_CTL_M 0x00006000 +#define IOC_IOCFG31_PULL_CTL_S 13 +#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG31_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG31_SLEW_RED 0x00001000 +#define IOC_IOCFG31_SLEW_RED_BITN 12 +#define IOC_IOCFG31_SLEW_RED_M 0x00001000 +#define IOC_IOCFG31_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG31_IOCURR_W 2 +#define IOC_IOCFG31_IOCURR_M 0x00000C00 +#define IOC_IOCFG31_IOCURR_S 10 +#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG31_IOCURR_4MA 0x00000400 +#define IOC_IOCFG31_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG31_IOSTR_W 2 +#define IOC_IOCFG31_IOSTR_M 0x00000300 +#define IOC_IOCFG31_IOSTR_S 8 +#define IOC_IOCFG31_IOSTR_MAX 0x00000300 +#define IOC_IOCFG31_IOSTR_MED 0x00000200 +#define IOC_IOCFG31_IOSTR_MIN 0x00000100 +#define IOC_IOCFG31_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO31 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG31_PORT_ID_W 6 +#define IOC_IOCFG31_PORT_ID_M 0x0000003F +#define IOC_IOCFG31_PORT_ID_S 0 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 + + +#endif // __IOC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_memmap.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_memmap.h new file mode 100644 index 0000000..6377d81 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_memmap.h @@ -0,0 +1,158 @@ +/****************************************************************************** +* Filename: hw_memmap_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals on the CPU_MMAP interface +// +//***************************************************************************** +#define FLASHMEM_BASE 0x00000000 // FLASHMEM +#define BROM_BASE 0x10000000 // BROM +#define GPRAM_BASE 0x11000000 // GPRAM +#define SRAM_BASE 0x20000000 // SRAM +#define RFC_RAM_BASE 0x21000000 // RFC_RAM +#define SSI0_BASE 0x40000000 // SSI +#define UART0_BASE 0x40001000 // UART +#define I2C0_BASE 0x40002000 // I2C +#define SSI1_BASE 0x40008000 // SSI +#define GPT0_BASE 0x40010000 // GPT +#define GPT1_BASE 0x40011000 // GPT +#define GPT2_BASE 0x40012000 // GPT +#define GPT3_BASE 0x40013000 // GPT +#define UDMA0_BASE 0x40020000 // UDMA +#define I2S0_BASE 0x40021000 // I2S +#define GPIO_BASE 0x40022000 // GPIO +#define CRYPTO_BASE 0x40024000 // CRYPTO +#define TRNG_BASE 0x40028000 // TRNG +#define FLASH_BASE 0x40030000 // FLASH +#define VIMS_BASE 0x40034000 // VIMS +#define RFC_PWR_BASE 0x40040000 // RFC_PWR +#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL +#define RFC_RAT_BASE 0x40043000 // RFC_RAT +#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA +#define WDT_BASE 0x40080000 // WDT +#define IOC_BASE 0x40081000 // IOC +#define PRCM_BASE 0x40082000 // PRCM +#define EVENT_BASE 0x40083000 // EVENT +#define SMPH_BASE 0x40084000 // SMPH +#define ADI2_BASE 0x40086000 // ADI +#define ADI3_BASE 0x40086200 // ADI +#define AON_SYSCTL_BASE 0x40090000 // AON_SYSCTL +#define AON_WUC_BASE 0x40091000 // AON_WUC +#define AON_RTC_BASE 0x40092000 // AON_RTC +#define AON_EVENT_BASE 0x40093000 // AON_EVENT +#define AON_IOC_BASE 0x40094000 // AON_IOC +#define AON_BATMON_BASE 0x40095000 // AON_BATMON +#define AUX_AIODIO0_BASE 0x400C1000 // AUX_AIODIO +#define AUX_AIODIO1_BASE 0x400C2000 // AUX_AIODIO +#define AUX_TDC_BASE 0x400C4000 // AUX_TDC +#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL +#define AUX_WUC_BASE 0x400C6000 // AUX_WUC +#define AUX_TIMER_BASE 0x400C7000 // AUX_TIMER +#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH +#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF +#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI +#define AUX_ADI4_BASE 0x400CB000 // ADI +#define AUX_RAM_BASE 0x400E0000 // AUX_RAM +#define AUX_SCE_BASE 0x400E1000 // AUX_SCE +#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP +#define FCFG1_BASE 0x50001000 // FCFG1 +#define FCFG2_BASE 0x50002000 // FCFG2 +#ifndef CCFG_BASE +#define CCFG_BASE 0x50003000 // CCFG +#endif +#define CCFG_BASE_DEFAULT 0x50003000 // CCFG +#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base +#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base +#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base +#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base +#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base +#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base +#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base +#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base +#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base +#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base +#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base +#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base +#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base +#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base +#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base +#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base +#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base +#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base +#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base +#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base +#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base +#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base +#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base +#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base +#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base +#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base +#define AON_SYSCTL_NONBUF_BASE 0x60090000 // AON_SYSCTL CPU nonbuf base +#define AON_WUC_NONBUF_BASE 0x60091000 // AON_WUC CPU nonbuf base +#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base +#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base +#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base +#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base +#define AUX_AIODIO0_NONBUF_BASE \ + 0x600C1000 // AUX_AIODIO CPU nonbuf base +#define AUX_AIODIO1_NONBUF_BASE \ + 0x600C2000 // AUX_AIODIO CPU nonbuf base +#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base +#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base +#define AUX_WUC_NONBUF_BASE 0x600C6000 // AUX_WUC CPU nonbuf base +#define AUX_TIMER_NONBUF_BASE 0x600C7000 // AUX_TIMER CPU nonbuf base +#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base +#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base +#define AUX_DDI0_OSC_NONBUF_BASE \ + 0x600CA000 // DDI CPU nonbuf base +#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base +#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base +#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base +#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base +#define CPU_ITM_BASE 0xE0000000 // CPU_ITM +#define CPU_DWT_BASE 0xE0001000 // CPU_DWT +#define CPU_FPB_BASE 0xE0002000 // CPU_FPB +#define CPU_SCS_BASE 0xE000E000 // CPU_SCS +#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU +#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP +#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE + +#endif // __HW_MEMMAP__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_nvic.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_nvic.h new file mode 100644 index 0000000..3bdeb8b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_nvic.h @@ -0,0 +1,1026 @@ +/****************************************************************************** +* Filename: hw_nvic.h +* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) +* Revision: 42365 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number +#undef NVIC_INT_CTRL_VEC_PEN_M +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number +#undef NVIC_INT_CTRL_VEC_ACT_M +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset +#undef NVIC_VTABLE_OFFSET_M +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 9 +#undef NVIC_VTABLE_OFFSET_S +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_prcm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_prcm.h new file mode 100644 index 0000000..7974ad0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_prcm.h @@ -0,0 +1,1636 @@ +/****************************************************************************** +* Filename: hw_prcm_h +* Revised: 2017-09-14 10:33:07 +0200 (Thu, 14 Sep 2017) +* Revision: 49733 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_PRCM_H__ +#define __HW_PRCM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// PRCM component +// +//***************************************************************************** +// Infrastructure Clock Division Factor For Run Mode +#define PRCM_O_INFRCLKDIVR 0x00000000 + +// Infrastructure Clock Division Factor For Sleep Mode +#define PRCM_O_INFRCLKDIVS 0x00000004 + +// Infrastructure Clock Division Factor For DeepSleep Mode +#define PRCM_O_INFRCLKDIVDS 0x00000008 + +// MCU Voltage Domain Control +#define PRCM_O_VDCTL 0x0000000C + +// Load PRCM Settings To CLKCTRL Power Domain +#define PRCM_O_CLKLOADCTL 0x00000028 + +// RFC Clock Gate +#define PRCM_O_RFCCLKG 0x0000002C + +// VIMS Clock Gate +#define PRCM_O_VIMSCLKG 0x00000030 + +// TRNG, CRYPTO And UDMA Clock Gate For Run Mode +#define PRCM_O_SECDMACLKGR 0x0000003C + +// TRNG, CRYPTO And UDMA Clock Gate For Sleep Mode +#define PRCM_O_SECDMACLKGS 0x00000040 + +// TRNG, CRYPTO And UDMA Clock Gate For Deep Sleep Mode +#define PRCM_O_SECDMACLKGDS 0x00000044 + +// GPIO Clock Gate For Run Mode +#define PRCM_O_GPIOCLKGR 0x00000048 + +// GPIO Clock Gate For Sleep Mode +#define PRCM_O_GPIOCLKGS 0x0000004C + +// GPIO Clock Gate For Deep Sleep Mode +#define PRCM_O_GPIOCLKGDS 0x00000050 + +// GPT Clock Gate For Run Mode +#define PRCM_O_GPTCLKGR 0x00000054 + +// GPT Clock Gate For Sleep Mode +#define PRCM_O_GPTCLKGS 0x00000058 + +// GPT Clock Gate For Deep Sleep Mode +#define PRCM_O_GPTCLKGDS 0x0000005C + +// I2C Clock Gate For Run Mode +#define PRCM_O_I2CCLKGR 0x00000060 + +// I2C Clock Gate For Sleep Mode +#define PRCM_O_I2CCLKGS 0x00000064 + +// I2C Clock Gate For Deep Sleep Mode +#define PRCM_O_I2CCLKGDS 0x00000068 + +// UART Clock Gate For Run Mode +#define PRCM_O_UARTCLKGR 0x0000006C + +// UART Clock Gate For Sleep Mode +#define PRCM_O_UARTCLKGS 0x00000070 + +// UART Clock Gate For Deep Sleep Mode +#define PRCM_O_UARTCLKGDS 0x00000074 + +// SSI Clock Gate For Run Mode +#define PRCM_O_SSICLKGR 0x00000078 + +// SSI Clock Gate For Sleep Mode +#define PRCM_O_SSICLKGS 0x0000007C + +// SSI Clock Gate For Deep Sleep Mode +#define PRCM_O_SSICLKGDS 0x00000080 + +// I2S Clock Gate For Run Mode +#define PRCM_O_I2SCLKGR 0x00000084 + +// I2S Clock Gate For Sleep Mode +#define PRCM_O_I2SCLKGS 0x00000088 + +// I2S Clock Gate For Deep Sleep Mode +#define PRCM_O_I2SCLKGDS 0x0000008C + +// Internal +#define PRCM_O_CPUCLKDIV 0x000000B8 + +// I2S Clock Control +#define PRCM_O_I2SBCLKSEL 0x000000C8 + +// GPT Scalar +#define PRCM_O_GPTCLKDIV 0x000000CC + +// I2S Clock Control +#define PRCM_O_I2SCLKCTL 0x000000D0 + +// MCLK Division Ratio +#define PRCM_O_I2SMCLKDIV 0x000000D4 + +// BCLK Division Ratio +#define PRCM_O_I2SBCLKDIV 0x000000D8 + +// WCLK Division Ratio +#define PRCM_O_I2SWCLKDIV 0x000000DC + +// SW Initiated Resets +#define PRCM_O_SWRESET 0x0000010C + +// WARM Reset Control And Status +#define PRCM_O_WARMRESET 0x00000110 + +// Power Domain Control +#define PRCM_O_PDCTL0 0x0000012C + +// RFC Power Domain Control +#define PRCM_O_PDCTL0RFC 0x00000130 + +// SERIAL Power Domain Control +#define PRCM_O_PDCTL0SERIAL 0x00000134 + +// PERIPH Power Domain Control +#define PRCM_O_PDCTL0PERIPH 0x00000138 + +// Power Domain Status +#define PRCM_O_PDSTAT0 0x00000140 + +// RFC Power Domain Status +#define PRCM_O_PDSTAT0RFC 0x00000144 + +// SERIAL Power Domain Status +#define PRCM_O_PDSTAT0SERIAL 0x00000148 + +// PERIPH Power Domain Status +#define PRCM_O_PDSTAT0PERIPH 0x0000014C + +// Power Domain Control +#define PRCM_O_PDCTL1 0x0000017C + +// CPU Power Domain Direct Control +#define PRCM_O_PDCTL1CPU 0x00000184 + +// RFC Power Domain Direct Control +#define PRCM_O_PDCTL1RFC 0x00000188 + +// VIMS Mode Direct Control +#define PRCM_O_PDCTL1VIMS 0x0000018C + +// Power Manager Status +#define PRCM_O_PDSTAT1 0x00000194 + +// BUS Power Domain Direct Read Status +#define PRCM_O_PDSTAT1BUS 0x00000198 + +// RFC Power Domain Direct Read Status +#define PRCM_O_PDSTAT1RFC 0x0000019C + +// CPU Power Domain Direct Read Status +#define PRCM_O_PDSTAT1CPU 0x000001A0 + +// VIMS Mode Direct Read Status +#define PRCM_O_PDSTAT1VIMS 0x000001A4 + +// Control To RFC +#define PRCM_O_RFCBITS 0x000001CC + +// Selected RFC Mode +#define PRCM_O_RFCMODESEL 0x000001D0 + +// Allowed RFC Modes +#define PRCM_O_RFCMODEHWOPT 0x000001D4 + +// Power Profiler Register +#define PRCM_O_PWRPROFSTAT 0x000001E0 + +// Memory Retention Control +#define PRCM_O_RAMRETEN 0x00000224 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVR +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in run mode. Division ratio affects both infrastructure clock and +// perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVR_RATIO_W 2 +#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_S 0 +#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVS +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in sleep mode. Division ratio affects both infrastructure clock and +// perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVS_RATIO_W 2 +#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_S 0 +#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVDS +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in seepsleep mode. Division ratio affects both infrastructure clock +// and perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVDS_RATIO_W 2 +#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_S 0 +#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_VDCTL +// +//***************************************************************************** +// Field: [2] MCU_VD +// +// Request WUC to power down the MCU voltage domain +// +// 0: No request +// 1: Assert request when possible. An asserted power down request will result +// in a boot of the MCU system when powered up again. +// +// The bit will have no effect before the following requirements are met: +// 1. PDCTL1.CPU_ON = 0 +// 2. PDCTL1.VIMS_MODE = 0 +// 3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded with +// CLKLOADCTL.LOAD) +// 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with +// CLKLOADCTL.LOAD) +// 5. RFC do no request access to BUS +// 6. System CPU in deepsleep +#define PRCM_VDCTL_MCU_VD 0x00000004 +#define PRCM_VDCTL_MCU_VD_BITN 2 +#define PRCM_VDCTL_MCU_VD_M 0x00000004 +#define PRCM_VDCTL_MCU_VD_S 2 + +// Field: [0] ULDO +// +// Request WUC to switch to uLDO. +// +// 0: No request +// 1: Assert request when possible +// +// The bit will have no effect before the following requirements are met: +// 1. PDCTL1.CPU_ON = 0 +// 2. PDCTL1.VIMS_MODE = 0 +// 3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded with +// CLKLOADCTL.LOAD) +// 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with +// CLKLOADCTL.LOAD) +// 5. RFC do no request access to BUS +// 6. System CPU in deepsleep +#define PRCM_VDCTL_ULDO 0x00000001 +#define PRCM_VDCTL_ULDO_BITN 0 +#define PRCM_VDCTL_ULDO_M 0x00000001 +#define PRCM_VDCTL_ULDO_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_CLKLOADCTL +// +//***************************************************************************** +// Field: [1] LOAD_DONE +// +// Status of LOAD. +// Will be cleared to 0 when any of the registers requiring a LOAD is written +// to, and be set to 1 when a LOAD is done. +// Note that writing no change to a register will result in the LOAD_DONE being +// cleared. +// +// 0 : One or more registers have been write accessed after last LOAD +// 1 : No registers are write accessed after last LOAD +#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 +#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_S 1 + +// Field: [0] LOAD +// +// 0: No action +// 1: Load settings to CLKCTRL. Bit is HW cleared. +// +// Multiple changes to settings may be done before LOAD is written once so all +// changes takes place at the same time. LOAD can also be done after single +// setting updates. +// +// Registers that needs to be followed by LOAD before settings being applied +// are: +// - RFCCLKG +// - VIMSCLKG +// - SECDMACLKGR +// - SECDMACLKGS +// - SECDMACLKGDS +// - GPIOCLKGR +// - GPIOCLKGS +// - GPIOCLKGDS +// - GPTCLKGR +// - GPTCLKGS +// - GPTCLKGDS +// - GPTCLKDIV +// - I2CCLKGR +// - I2CCLKGS +// - I2CCLKGDS +// - SSICLKGR +// - SSICLKGS +// - SSICLKGDS +// - UARTCLKGR +// - UARTCLKGS +// - UARTCLKGDS +// - I2SCLKGR +// - I2SCLKGS +// - I2SCLKGDS +// - I2SBCLKSEL +// - I2SCLKCTL +// - I2SMCLKDIV +// - I2SBCLKDIV +// - I2SWCLKDIV +#define PRCM_CLKLOADCTL_LOAD 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_BITN 0 +#define PRCM_CLKLOADCTL_LOAD_M 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCCLKG +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock if RFC power domain is on +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_RFCCLKG_CLK_EN 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_BITN 0 +#define PRCM_RFCCLKG_CLK_EN_M 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_VIMSCLKG +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 00: Disable clock +// 01: Disable clock when system CPU is in DeepSleep +// 11: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_VIMSCLKG_CLK_EN_W 2 +#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 +#define PRCM_VIMSCLKG_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGR +// +//***************************************************************************** +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGS +// +//***************************************************************************** +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGDS +// +//***************************************************************************** +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGR +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGR_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGR +// +//***************************************************************************** +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGR_CLK_EN_W 4 +#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGR_CLK_EN_S 0 +#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGS +// +//***************************************************************************** +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGS_CLK_EN_W 4 +#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGS_CLK_EN_S 0 +#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGDS +// +//***************************************************************************** +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGDS_CLK_EN_W 4 +#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGDS_CLK_EN_S 0 +#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGR +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGR_CLK_EN 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_BITN 0 +#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGR +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_UARTCLKGR_CLK_EN 0x00000001 +#define PRCM_UARTCLKGR_CLK_EN_BITN 0 +#define PRCM_UARTCLKGR_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_UARTCLKGS_CLK_EN 0x00000001 +#define PRCM_UARTCLKGS_CLK_EN_BITN 0 +#define PRCM_UARTCLKGS_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_UARTCLKGDS_CLK_EN 0x00000001 +#define PRCM_UARTCLKGDS_CLK_EN_BITN 0 +#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGR +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGR_CLK_EN_W 2 +#define PRCM_SSICLKGR_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGR_CLK_EN_S 0 +#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGS_CLK_EN_W 2 +#define PRCM_SSICLKGS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGS_CLK_EN_S 0 +#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGDS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGDS_CLK_EN_W 2 +#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGDS_CLK_EN_S 0 +#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGR +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGR_CLK_EN 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_BITN 0 +#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_CPUCLKDIV +// +//***************************************************************************** +// Field: [0] RATIO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DIV2 Internal. Only to be used through TI provided API. +// DIV1 Internal. Only to be used through TI provided API. +#define PRCM_CPUCLKDIV_RATIO 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_BITN 0 +#define PRCM_CPUCLKDIV_RATIO_M 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_S 0 +#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_I2SBCLKSEL +// +//***************************************************************************** +// Field: [0] SRC +// +// BCLK source selector +// +// 0: Use external BCLK +// 1: Use internally generated clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SBCLKSEL_SRC 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_BITN 0 +#define PRCM_I2SBCLKSEL_SRC_M 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKDIV +// +//***************************************************************************** +// Field: [3:0] RATIO +// +// Scalar used for GPTs. The division rate will be constant and ungated for Run +// / Sleep / DeepSleep mode. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// Other values are not supported. +// ENUMs: +// DIV256 Divide by 256 +// DIV128 Divide by 128 +// DIV64 Divide by 64 +// DIV32 Divide by 32 +// DIV16 Divide by 16 +// DIV8 Divide by 8 +// DIV4 Divide by 4 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_GPTCLKDIV_RATIO_W 4 +#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F +#define PRCM_GPTCLKDIV_RATIO_S 0 +#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKCTL +// +//***************************************************************************** +// Field: [3] SMPL_ON_POSEDGE +// +// On the I2S serial interface, data and WCLK is sampled and clocked out on +// opposite edges of BCLK. +// +// 0 - data and WCLK are sampled on the negative edge and clocked out on the +// positive edge. +// 1 - data and WCLK are sampled on the positive edge and clocked out on the +// negative edge. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 + +// Field: [2:1] WCLK_PHASE +// +// Decides how the WCLK division ratio is calculated and used to generate +// different duty cycles (See I2SWCLKDIV.WDIV). +// +// 0: Single phase +// 1: Dual phase +// 2: User Defined +// 3: Reserved/Undefined +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 +#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 +#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 + +// Field: [0] EN +// +// +// 0: MCLK, BCLK and WCLK will be static low +// 1: Enables the generation of MCLK, BCLK and WCLK +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_EN 0x00000001 +#define PRCM_I2SCLKCTL_EN_BITN 0 +#define PRCM_I2SCLKCTL_EN_M 0x00000001 +#define PRCM_I2SCLKCTL_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SMCLKDIV +// +//***************************************************************************** +// Field: [9:0] MDIV +// +// An unsigned factor of the division ratio used to generate MCLK [2-1024]: +// +// MCLK = MCUCLK/MDIV[Hz] +// MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined +// by AON_WUC:MCUCLK.PWR_DWN_SRC +// +// A value of 0 is interpreted as 1024. +// A value of 1 is invalid. +// If MDIV is odd the low phase of the clock is one MCUCLK period longer than +// the high phase. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SMCLKDIV_MDIV_W 10 +#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF +#define PRCM_I2SMCLKDIV_MDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SBCLKDIV +// +//***************************************************************************** +// Field: [9:0] BDIV +// +// An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: +// +// BCLK = MCUCLK/BDIV[Hz] +// MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined +// by AON_WUC:MCUCLK.PWR_DWN_SRC +// +// A value of 0 is interpreted as 1024. +// A value of 1 is invalid. +// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock +// is one MCUCLK period longer than the high phase. +// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the +// clock is one MCUCLK period longer than the low phase. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SBCLKDIV_BDIV_W 10 +#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF +#define PRCM_I2SBCLKDIV_BDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SWCLKDIV +// +//***************************************************************************** +// Field: [15:0] WDIV +// +// If I2SCLKCTL.WCLK_PHASE = 0, Single phase. +// WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK +// periods. +// +// WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] +// MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined +// by AON_WUC:MCUCLK.PWR_DWN_SRC +// +// If I2SCLKCTL.WCLK_PHASE = 1, Dual phase. +// Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK +// periods. +// +// WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] +// +// If I2SCLKCTL.WCLK_PHASE = 2, User defined. +// WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] +// (unsigned, [1-255]) BCLK periods. +// +// WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SWCLKDIV_WDIV_W 16 +#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF +#define PRCM_I2SWCLKDIV_WDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SWRESET +// +//***************************************************************************** +// Field: [2] MCU +// +// Internal. Only to be used through TI provided API. +#define PRCM_SWRESET_MCU 0x00000004 +#define PRCM_SWRESET_MCU_BITN 2 +#define PRCM_SWRESET_MCU_M 0x00000004 +#define PRCM_SWRESET_MCU_S 2 + +//***************************************************************************** +// +// Register: PRCM_O_WARMRESET +// +//***************************************************************************** +// Field: [2] WR_TO_PINRESET +// +// 0: No action +// 1: A warm system reset event triggered by the below listed sources will +// result in an emulated pin reset. +// +// Warm reset sources included: +// ICEPick sysreset +// System CPU reset request, CPU_SCS:AIRCR.SYSRESETREQ +// System CPU Lockup +// WDT timeout +// +// An active ICEPick block system reset will gate all sources except ICEPick +// sysreset +// +// SW can read AON_SYSCTL:RESETCTL.RESET_SRC to find the source of the last +// reset resulting in a full power up sequence. WARMRESET in this register is +// set in the scenario that WR_TO_PINRESET=1 and one of the above listed +// sources is triggered. +#define PRCM_WARMRESET_WR_TO_PINRESET 0x00000004 +#define PRCM_WARMRESET_WR_TO_PINRESET_BITN 2 +#define PRCM_WARMRESET_WR_TO_PINRESET_M 0x00000004 +#define PRCM_WARMRESET_WR_TO_PINRESET_S 2 + +// Field: [1] LOCKUP_STAT +// +// +// 0: No registred event +// 1: A system CPU LOCKUP event has occured since last SW clear of the +// register. +// +// A read of this register clears both WDT_STAT and LOCKUP_STAT. +#define PRCM_WARMRESET_LOCKUP_STAT 0x00000002 +#define PRCM_WARMRESET_LOCKUP_STAT_BITN 1 +#define PRCM_WARMRESET_LOCKUP_STAT_M 0x00000002 +#define PRCM_WARMRESET_LOCKUP_STAT_S 1 + +// Field: [0] WDT_STAT +// +// +// 0: No registered event +// 1: A WDT event has occured since last SW clear of the register. +// +// A read of this register clears both WDT_STAT and LOCKUP_STAT. +#define PRCM_WARMRESET_WDT_STAT 0x00000001 +#define PRCM_WARMRESET_WDT_STAT_BITN 0 +#define PRCM_WARMRESET_WDT_STAT_M 0x00000001 +#define PRCM_WARMRESET_WDT_STAT_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0 +// +//***************************************************************************** +// Field: [2] PERIPH_ON +// +// PERIPH Power domain. +// +// 0: PERIPH power domain is powered down +// 1: PERIPH power domain is powered up +#define PRCM_PDCTL0_PERIPH_ON 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_BITN 2 +#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_S 2 + +// Field: [1] SERIAL_ON +// +// SERIAL Power domain. +// +// 0: SERIAL power domain is powered down +// 1: SERIAL power domain is powered up +#define PRCM_PDCTL0_SERIAL_ON 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_BITN 1 +#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_S 1 + +// Field: [0] RFC_ON +// +// +// 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 +// 1: RFC power domain powered on +#define PRCM_PDCTL0_RFC_ON 0x00000001 +#define PRCM_PDCTL0_RFC_ON_BITN 0 +#define PRCM_PDCTL0_RFC_ON_M 0x00000001 +#define PRCM_PDCTL0_RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0RFC +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.RFC_ON +#define PRCM_PDCTL0RFC_ON 0x00000001 +#define PRCM_PDCTL0RFC_ON_BITN 0 +#define PRCM_PDCTL0RFC_ON_M 0x00000001 +#define PRCM_PDCTL0RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0SERIAL +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.SERIAL_ON +#define PRCM_PDCTL0SERIAL_ON 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_BITN 0 +#define PRCM_PDCTL0SERIAL_ON_M 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0PERIPH +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.PERIPH_ON +#define PRCM_PDCTL0PERIPH_ON 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_BITN 0 +#define PRCM_PDCTL0PERIPH_ON_M 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0 +// +//***************************************************************************** +// Field: [2] PERIPH_ON +// +// PERIPH Power domain. +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_PERIPH_ON 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_BITN 2 +#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_S 2 + +// Field: [1] SERIAL_ON +// +// SERIAL Power domain. +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_SERIAL_ON 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_BITN 1 +#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_S 1 + +// Field: [0] RFC_ON +// +// RFC Power domain +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_RFC_ON 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_BITN 0 +#define PRCM_PDSTAT0_RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0RFC +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.RFC_ON +#define PRCM_PDSTAT0RFC_ON 0x00000001 +#define PRCM_PDSTAT0RFC_ON_BITN 0 +#define PRCM_PDSTAT0RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0SERIAL +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.SERIAL_ON +#define PRCM_PDSTAT0SERIAL_ON 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_BITN 0 +#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0PERIPH +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.PERIPH_ON +#define PRCM_PDSTAT0PERIPH_ON 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_BITN 0 +#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1 +// +//***************************************************************************** +// Field: [3] VIMS_MODE +// +// +// 0: VIMS power domain is only powered when CPU power domain is powered. +// 1: VIMS power domain is powered whenever the BUS power domain is powered. +#define PRCM_PDCTL1_VIMS_MODE 0x00000008 +#define PRCM_PDCTL1_VIMS_MODE_BITN 3 +#define PRCM_PDCTL1_VIMS_MODE_M 0x00000008 +#define PRCM_PDCTL1_VIMS_MODE_S 3 + +// Field: [2] RFC_ON +// +// +// 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 +// 1: RFC power domain powered on +// +// Bit shall be used by RFC in autonomus mode but there is no HW restrictions +// fom system CPU to access the bit. +#define PRCM_PDCTL1_RFC_ON 0x00000004 +#define PRCM_PDCTL1_RFC_ON_BITN 2 +#define PRCM_PDCTL1_RFC_ON_M 0x00000004 +#define PRCM_PDCTL1_RFC_ON_S 2 + +// Field: [1] CPU_ON +// +// +// 0: Causes a power down of the CPU power domain when system CPU indicates it +// is idle. +// 1: Initiates power-on of the CPU power domain. +// +// This bit is automatically set by a WIC power-on event. +#define PRCM_PDCTL1_CPU_ON 0x00000002 +#define PRCM_PDCTL1_CPU_ON_BITN 1 +#define PRCM_PDCTL1_CPU_ON_M 0x00000002 +#define PRCM_PDCTL1_CPU_ON_S 1 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1CPU +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDCTL1.CPU_ON +#define PRCM_PDCTL1CPU_ON 0x00000001 +#define PRCM_PDCTL1CPU_ON_BITN 0 +#define PRCM_PDCTL1CPU_ON_M 0x00000001 +#define PRCM_PDCTL1CPU_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1RFC +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDCTL1.RFC_ON +#define PRCM_PDCTL1RFC_ON 0x00000001 +#define PRCM_PDCTL1RFC_ON_BITN 0 +#define PRCM_PDCTL1RFC_ON_M 0x00000001 +#define PRCM_PDCTL1RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1VIMS +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDCTL1.VIMS_MODE +#define PRCM_PDCTL1VIMS_ON 0x00000001 +#define PRCM_PDCTL1VIMS_ON_BITN 0 +#define PRCM_PDCTL1VIMS_ON_M 0x00000001 +#define PRCM_PDCTL1VIMS_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1 +// +//***************************************************************************** +// Field: [4] BUS_ON +// +// +// 0: BUS domain not accessible +// 1: BUS domain is currently accessible +#define PRCM_PDSTAT1_BUS_ON 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_BITN 4 +#define PRCM_PDSTAT1_BUS_ON_M 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_S 4 + +// Field: [3] VIMS_MODE +// +// +// 0: VIMS domain not accessible +// 1: VIMS domain is currently accessible +#define PRCM_PDSTAT1_VIMS_MODE 0x00000008 +#define PRCM_PDSTAT1_VIMS_MODE_BITN 3 +#define PRCM_PDSTAT1_VIMS_MODE_M 0x00000008 +#define PRCM_PDSTAT1_VIMS_MODE_S 3 + +// Field: [2] RFC_ON +// +// +// 0: RFC domain not accessible +// 1: RFC domain is currently accessible +#define PRCM_PDSTAT1_RFC_ON 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_BITN 2 +#define PRCM_PDSTAT1_RFC_ON_M 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_S 2 + +// Field: [1] CPU_ON +// +// +// 0: CPU and BUS domain not accessible +// 1: CPU and BUS domains are both currently accessible +#define PRCM_PDSTAT1_CPU_ON 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_BITN 1 +#define PRCM_PDSTAT1_CPU_ON_M 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_S 1 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1BUS +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.BUS_ON +#define PRCM_PDSTAT1BUS_ON 0x00000001 +#define PRCM_PDSTAT1BUS_ON_BITN 0 +#define PRCM_PDSTAT1BUS_ON_M 0x00000001 +#define PRCM_PDSTAT1BUS_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1RFC +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.RFC_ON +#define PRCM_PDSTAT1RFC_ON 0x00000001 +#define PRCM_PDSTAT1RFC_ON_BITN 0 +#define PRCM_PDSTAT1RFC_ON_M 0x00000001 +#define PRCM_PDSTAT1RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1CPU +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.CPU_ON +#define PRCM_PDSTAT1CPU_ON 0x00000001 +#define PRCM_PDSTAT1CPU_ON_BITN 0 +#define PRCM_PDSTAT1CPU_ON_M 0x00000001 +#define PRCM_PDSTAT1CPU_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1VIMS +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.VIMS_MODE +#define PRCM_PDSTAT1VIMS_ON 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_BITN 0 +#define PRCM_PDSTAT1VIMS_ON_M 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCBITS +// +//***************************************************************************** +// Field: [31:0] READ +// +// Control bits for RFC. The RF core CPE processor will automatically check +// this register when it boots, and it can be used to immediately instruct CPE +// to perform some tasks at its start-up. The supported functionality is +// ROM-defined and may vary. See the technical reference manual for more +// details. +#define PRCM_RFCBITS_READ_W 32 +#define PRCM_RFCBITS_READ_M 0xFFFFFFFF +#define PRCM_RFCBITS_READ_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCMODESEL +// +//***************************************************************************** +// Field: [2:0] CURR +// +// Selects the set of commands that the RFC will accept. Only modes permitted +// by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for +// details. +// ENUMs: +// MODE7 Select Mode 7 +// MODE6 Select Mode 6 +// MODE5 Select Mode 5 +// MODE4 Select Mode 4 +// MODE3 Select Mode 3 +// MODE2 Select Mode 2 +// MODE1 Select Mode 1 +// MODE0 Select Mode 0 +#define PRCM_RFCMODESEL_CURR_W 3 +#define PRCM_RFCMODESEL_CURR_M 0x00000007 +#define PRCM_RFCMODESEL_CURR_S 0 +#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 +#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 +#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 +#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 +#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 +#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 +#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 +#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_RFCMODEHWOPT +// +//***************************************************************************** +// Field: [7:0] AVAIL +// +// Permitted RFC modes. More than one mode can be permitted. +// ENUMs: +// MODE7 Mode 7 permitted +// MODE6 Mode 6 permitted +// MODE5 Mode 5 permitted +// MODE4 Mode 4 permitted +// MODE3 Mode 3 permitted +// MODE2 Mode 2 permitted +// MODE1 Mode 1 permitted +// MODE0 Mode 0 permitted +#define PRCM_RFCMODEHWOPT_AVAIL_W 8 +#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF +#define PRCM_RFCMODEHWOPT_AVAIL_S 0 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_PWRPROFSTAT +// +//***************************************************************************** +// Field: [7:0] VALUE +// +// SW can use these bits to timestamp the application. These bits are also +// available through the testtap and can thus be used by the emulator to +// profile in real time. +#define PRCM_PWRPROFSTAT_VALUE_W 8 +#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF +#define PRCM_PWRPROFSTAT_VALUE_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RAMRETEN +// +//***************************************************************************** +// Field: [2] RFC +// +// +// 0: Retention for RFC SRAM disabled +// 1: Retention for RFC SRAM enabled +// +// Memories controlled: CPERAM MCERAM RFERAM +#define PRCM_RAMRETEN_RFC 0x00000004 +#define PRCM_RAMRETEN_RFC_BITN 2 +#define PRCM_RAMRETEN_RFC_M 0x00000004 +#define PRCM_RAMRETEN_RFC_S 2 + +// Field: [1:0] VIMS +// +// +// 0: Memory retention disabled +// 1: Memory retention enabled +// +// Bit 0: VIMS_TRAM +// Bit 1: VIMS_CRAM +// +// Legal modes depend on settings in VIMS:CTL.MODE +// +// 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to +// CACHE or SPLIT mode after waking up again +// 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in +// GPRAM mode after wake up, alternatively select OFF mode first and then CACHE +// or SPILT mode. +// 10: Illegal mode +// 11: No restrictions +#define PRCM_RAMRETEN_VIMS_W 2 +#define PRCM_RAMRETEN_VIMS_M 0x00000003 +#define PRCM_RAMRETEN_VIMS_S 0 + + +#endif // __PRCM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_dbell.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_dbell.h new file mode 100644 index 0000000..9ac876c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_dbell.h @@ -0,0 +1,1671 @@ +/****************************************************************************** +* Filename: hw_rfc_dbell_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_DBELL_H__ +#define __HW_RFC_DBELL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_DBELL component +// +//***************************************************************************** +// Doorbell Command Register +#define RFC_DBELL_O_CMDR 0x00000000 + +// Doorbell Command Status Register +#define RFC_DBELL_O_CMDSTA 0x00000004 + +// Interrupt Flags From RF Hardware Modules +#define RFC_DBELL_O_RFHWIFG 0x00000008 + +// Interrupt Enable For RF Hardware Modules +#define RFC_DBELL_O_RFHWIEN 0x0000000C + +// Interrupt Flags For Command and Packet Engine Generated Interrupts +#define RFC_DBELL_O_RFCPEIFG 0x00000010 + +// Interrupt Enable For Command and Packet Engine Generated Interrupts +#define RFC_DBELL_O_RFCPEIEN 0x00000014 + +// Interrupt Vector Selection For Command and Packet Engine Generated +// Interrupts +#define RFC_DBELL_O_RFCPEISL 0x00000018 + +// Doorbell Command Acknowledgement Interrupt Flag +#define RFC_DBELL_O_RFACKIFG 0x0000001C + +// RF Core General Purpose Output Control +#define RFC_DBELL_O_SYSGPOCTL 0x00000020 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_CMDR +// +//***************************************************************************** +// Field: [31:0] CMD +// +// Command register. Raises an interrupt to the Command and packet engine (CPE) +// upon write. +#define RFC_DBELL_CMDR_CMD_W 32 +#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF +#define RFC_DBELL_CMDR_CMD_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_CMDSTA +// +//***************************************************************************** +// Field: [31:0] STAT +// +// Status of the last command used +#define RFC_DBELL_CMDSTA_STAT_W 32 +#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF +#define RFC_DBELL_CMDSTA_STAT_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFHWIFG +// +//***************************************************************************** +// Field: [19] RATCH7 +// +// Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_S 19 + +// Field: [18] RATCH6 +// +// Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_S 18 + +// Field: [17] RATCH5 +// +// Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_S 17 + +// Field: [16] RATCH4 +// +// Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_S 16 + +// Field: [15] RATCH3 +// +// Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_S 15 + +// Field: [14] RATCH2 +// +// Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_S 14 + +// Field: [13] RATCH1 +// +// Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_S 13 + +// Field: [12] RATCH0 +// +// Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_S 12 + +// Field: [11] RFESOFT2 +// +// RF engine software defined interrupt 2 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 + +// Field: [10] RFESOFT1 +// +// RF engine software defined interrupt 1 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 + +// Field: [9] RFESOFT0 +// +// RF engine software defined interrupt 0 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 + +// Field: [8] RFEDONE +// +// RF engine command done interrupt flag. Write zero to clear flag. Write to +// one has no effect. +#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_S 8 + +// Field: [6] TRCTK +// +// Debug tracer system tick interrupt flag. Write zero to clear flag. Write to +// one has no effect. +#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_S 6 + +// Field: [5] MDMSOFT +// +// Modem synchronization word detection interrupt flag. This interrupt will be +// raised by modem when the synchronization word is received. The CPE may +// decide to reject the packet based on its header (protocol specific). Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 + +// Field: [4] MDMOUT +// +// Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has +// no effect. +#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_S 4 + +// Field: [3] MDMIN +// +// Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has +// no effect. +#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_S 3 + +// Field: [2] MDMDONE +// +// Modem command done interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_S 2 + +// Field: [1] FSCA +// +// Frequency synthesizer calibration accelerator interrupt flag. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFHWIFG_FSCA 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_BITN 1 +#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_S 1 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFHWIEN +// +//***************************************************************************** +// Field: [19] RATCH7 +// +// Interrupt enable for RFHWIFG.RATCH7. +#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_S 19 + +// Field: [18] RATCH6 +// +// Interrupt enable for RFHWIFG.RATCH6. +#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_S 18 + +// Field: [17] RATCH5 +// +// Interrupt enable for RFHWIFG.RATCH5. +#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_S 17 + +// Field: [16] RATCH4 +// +// Interrupt enable for RFHWIFG.RATCH4. +#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_S 16 + +// Field: [15] RATCH3 +// +// Interrupt enable for RFHWIFG.RATCH3. +#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_S 15 + +// Field: [14] RATCH2 +// +// Interrupt enable for RFHWIFG.RATCH2. +#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_S 14 + +// Field: [13] RATCH1 +// +// Interrupt enable for RFHWIFG.RATCH1. +#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_S 13 + +// Field: [12] RATCH0 +// +// Interrupt enable for RFHWIFG.RATCH0. +#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_S 12 + +// Field: [11] RFESOFT2 +// +// Interrupt enable for RFHWIFG.RFESOFT2. +#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 + +// Field: [10] RFESOFT1 +// +// Interrupt enable for RFHWIFG.RFESOFT1. +#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 + +// Field: [9] RFESOFT0 +// +// Interrupt enable for RFHWIFG.RFESOFT0. +#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 + +// Field: [8] RFEDONE +// +// Interrupt enable for RFHWIFG.RFEDONE. +#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_S 8 + +// Field: [6] TRCTK +// +// Interrupt enable for RFHWIFG.TRCTK. +#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_S 6 + +// Field: [5] MDMSOFT +// +// Interrupt enable for RFHWIFG.MDMSOFT. +#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 + +// Field: [4] MDMOUT +// +// Interrupt enable for RFHWIFG.MDMOUT. +#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_S 4 + +// Field: [3] MDMIN +// +// Interrupt enable for RFHWIFG.MDMIN. +#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_S 3 + +// Field: [2] MDMDONE +// +// Interrupt enable for RFHWIFG.MDMDONE. +#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_S 2 + +// Field: [1] FSCA +// +// Interrupt enable for RFHWIFG.FSCA. +#define RFC_DBELL_RFHWIEN_FSCA 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_BITN 1 +#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_S 1 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEIFG +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Interrupt flag 31. The command and packet engine (CPE) has observed an +// unexpected error. A reset of the CPE is needed. This can be done by +// switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 + +// Field: [30] BOOT_DONE +// +// Interrupt flag 30. The command and packet engine (CPE) boot is finished. +// Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 + +// Field: [29] MODULES_UNLOCKED +// +// Interrupt flag 29. As part of command and packet engine (CPE) boot process, +// it has opened access to RF Core modules and memories. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 + +// Field: [28] SYNTH_NO_LOCK +// +// Interrupt flag 28. The phase-locked loop in frequency synthesizer has +// reported loss of lock. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 + +// Field: [27] IRQ27 +// +// Interrupt flag 27. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_S 27 + +// Field: [26] RX_ABORTED +// +// Interrupt flag 26. Packet reception stopped before packet was done. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Interrupt flag 25. Specified number of bytes written to partial read Rx +// buffer. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 + +// Field: [24] RX_DATA_WRITTEN +// +// Interrupt flag 24. Data written to partial read Rx buffer. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 + +// Field: [23] RX_ENTRY_DONE +// +// Interrupt flag 23. Rx queue data entry changing state to finished. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 + +// Field: [22] RX_BUF_FULL +// +// Interrupt flag 22. Packet received that did not fit in Rx queue. BLE mode: +// Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame +// received that did not fit in the Rx queue. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 + +// Field: [21] RX_CTRL_ACK +// +// Interrupt flag 21. BLE mode only: LL control packet received with CRC OK, +// not to be ignored, then acknowledgement sent. Write zero to clear flag. +// Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 + +// Field: [20] RX_CTRL +// +// Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, +// not to be ignored. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 + +// Field: [19] RX_EMPTY +// +// Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be +// ignored, no payload. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 + +// Field: [18] RX_IGNORED +// +// Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet +// received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received +// with ignore flag set. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 + +// Field: [17] RX_NOK +// +// Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received +// with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 + +// Field: [16] RX_OK +// +// Interrupt flag 16. Packet received correctly. BLE mode: Packet received with +// CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received +// with CRC OK. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_S 16 + +// Field: [15] IRQ15 +// +// Interrupt flag 15. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_S 15 + +// Field: [14] IRQ14 +// +// Interrupt flag 14. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_S 14 + +// Field: [13] IRQ13 +// +// Interrupt flag 13. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEIFG_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEIFG_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEIFG_IRQ13_S 13 + +// Field: [12] IRQ12 +// +// Interrupt flag 12. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEIFG_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEIFG_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEIFG_IRQ12_S 12 + +// Field: [11] TX_BUFFER_CHANGED +// +// Interrupt flag 11. BLE mode only: A buffer change is complete after +// CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 + +// Field: [10] TX_ENTRY_DONE +// +// Interrupt flag 10. Tx queue data entry state changed to finished. Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 + +// Field: [9] TX_RETRANS +// +// Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted +// LL control packet, and acknowledgement transmitted for that packet. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 + +// Field: [7] TX_CTRL_ACK +// +// Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL +// control packet. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 + +// Field: [6] TX_CTRL +// +// Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 + +// Field: [5] TX_ACK +// +// Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted +// packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 + +// Field: [4] TX_DONE +// +// Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been +// transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio +// operation command in a chain of commands has finished. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 + +// Field: [2] FG_COMMAND_DONE +// +// Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation +// command has finished. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 + +// Field: [1] LAST_COMMAND_DONE +// +// Interrupt flag 1. The last radio operation command in a chain of commands +// has finished. (IEEE 802.15.4 mode: The last background level radio operation +// command in a chain of commands has finished.) Write zero to clear flag. +// Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 + +// Field: [0] COMMAND_DONE +// +// Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A +// background level radio operation command has finished.) Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEIEN +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Interrupt enable for RFCPEIFG.INTERNAL_ERROR. +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 + +// Field: [30] BOOT_DONE +// +// Interrupt enable for RFCPEIFG.BOOT_DONE. +#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 + +// Field: [29] MODULES_UNLOCKED +// +// Interrupt enable for RFCPEIFG.MODULES_UNLOCKED. +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 + +// Field: [28] SYNTH_NO_LOCK +// +// Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK. +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 + +// Field: [27] IRQ27 +// +// Interrupt enable for RFCPEIFG.IRQ27. +#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_S 27 + +// Field: [26] RX_ABORTED +// +// Interrupt enable for RFCPEIFG.RX_ABORTED. +#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN. +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 + +// Field: [24] RX_DATA_WRITTEN +// +// Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN. +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 + +// Field: [23] RX_ENTRY_DONE +// +// Interrupt enable for RFCPEIFG.RX_ENTRY_DONE. +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 + +// Field: [22] RX_BUF_FULL +// +// Interrupt enable for RFCPEIFG.RX_BUF_FULL. +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 + +// Field: [21] RX_CTRL_ACK +// +// Interrupt enable for RFCPEIFG.RX_CTRL_ACK. +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 + +// Field: [20] RX_CTRL +// +// Interrupt enable for RFCPEIFG.RX_CTRL. +#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 + +// Field: [19] RX_EMPTY +// +// Interrupt enable for RFCPEIFG.RX_EMPTY. +#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 + +// Field: [18] RX_IGNORED +// +// Interrupt enable for RFCPEIFG.RX_IGNORED. +#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 + +// Field: [17] RX_NOK +// +// Interrupt enable for RFCPEIFG.RX_NOK. +#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 + +// Field: [16] RX_OK +// +// Interrupt enable for RFCPEIFG.RX_OK. +#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_S 16 + +// Field: [15] IRQ15 +// +// Interrupt enable for RFCPEIFG.IRQ15. +#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_S 15 + +// Field: [14] IRQ14 +// +// Interrupt enable for RFCPEIFG.IRQ14. +#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_S 14 + +// Field: [13] IRQ13 +// +// Interrupt enable for RFCPEIFG.IRQ13. +#define RFC_DBELL_RFCPEIEN_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEIEN_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEIEN_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEIEN_IRQ13_S 13 + +// Field: [12] IRQ12 +// +// Interrupt enable for RFCPEIFG.IRQ12. +#define RFC_DBELL_RFCPEIEN_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEIEN_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEIEN_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEIEN_IRQ12_S 12 + +// Field: [11] TX_BUFFER_CHANGED +// +// Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED. +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 + +// Field: [10] TX_ENTRY_DONE +// +// Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 + +// Field: [9] TX_RETRANS +// +// Interrupt enable for RFCPEIFG.TX_RETRANS. +#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 + +// Field: [7] TX_CTRL_ACK +// +// Interrupt enable for RFCPEIFG.TX_CTRL_ACK. +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 + +// Field: [6] TX_CTRL +// +// Interrupt enable for RFCPEIFG.TX_CTRL. +#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 + +// Field: [5] TX_ACK +// +// Interrupt enable for RFCPEIFG.TX_ACK. +#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 + +// Field: [4] TX_DONE +// +// Interrupt enable for RFCPEIFG.TX_DONE. +#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 + +// Field: [2] FG_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.FG_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 + +// Field: [1] LAST_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 + +// Field: [0] COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEISL +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 + +// Field: [30] BOOT_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 + +// Field: [29] MODULES_UNLOCKED +// +// Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 + +// Field: [28] SYNTH_NO_LOCK +// +// Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 + +// Field: [27] IRQ27 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_S 27 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 + +// Field: [26] RX_ABORTED +// +// Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 + +// Field: [24] RX_DATA_WRITTEN +// +// Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 + +// Field: [23] RX_ENTRY_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 + +// Field: [22] RX_BUF_FULL +// +// Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 + +// Field: [21] RX_CTRL_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 + +// Field: [20] RX_CTRL +// +// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 + +// Field: [19] RX_EMPTY +// +// Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 + +// Field: [18] RX_IGNORED +// +// Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 + +// Field: [17] RX_NOK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_S 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 + +// Field: [16] RX_OK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_S 16 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 + +// Field: [15] IRQ15 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_S 15 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 + +// Field: [14] IRQ14 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_S 14 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 + +// Field: [13] IRQ13 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ13 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEISL_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_S 13 +#define RFC_DBELL_RFCPEISL_IRQ13_CPE1 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_CPE0 0x00000000 + +// Field: [12] IRQ12 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ12 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEISL_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_S 12 +#define RFC_DBELL_RFCPEISL_IRQ12_CPE1 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_CPE0 0x00000000 + +// Field: [11] TX_BUFFER_CHANGED +// +// Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 + +// Field: [10] TX_ENTRY_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 + +// Field: [9] TX_RETRANS +// +// Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 + +// Field: [7] TX_CTRL_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 + +// Field: [6] TX_CTRL +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 + +// Field: [5] TX_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_S 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 + +// Field: [4] TX_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_S 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE +// interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 + +// Field: [2] FG_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 + +// Field: [1] LAST_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 + +// Field: [0] COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFACKIFG +// +//***************************************************************************** +// Field: [0] ACKFLAG +// +// Interrupt flag for Command ACK +#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 +#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_SYSGPOCTL +// +//***************************************************************************** +// Field: [15:12] GPOCTL3 +// +// RF Core GPO control bit 3. Selects which signal to output on the RF Core GPO +// line 3. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 + +// Field: [11:8] GPOCTL2 +// +// RF Core GPO control bit 2. Selects which signal to output on the RF Core GPO +// line 2. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 + +// Field: [7:4] GPOCTL1 +// +// RF Core GPO control bit 1. Selects which signal to output on the RF Core GPO +// line 1. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 + +// Field: [3:0] GPOCTL0 +// +// RF Core GPO control bit 0. Selects which signal to output on the RF Core GPO +// line 0. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 + + +#endif // __RFC_DBELL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_pwr.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_pwr.h new file mode 100644 index 0000000..ad91fb3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_pwr.h @@ -0,0 +1,153 @@ +/****************************************************************************** +* Filename: hw_rfc_pwr_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_PWR_H__ +#define __HW_RFC_PWR_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_PWR component +// +//***************************************************************************** +// RF Core Power Management and Clock Enable +#define RFC_PWR_O_PWMCLKEN 0x00000000 + +//***************************************************************************** +// +// Register: RFC_PWR_O_PWMCLKEN +// +//***************************************************************************** +// Field: [10] RFCTRC +// +// Enable clock to the RF Core Tracer (RFCTRC) module. +#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 +#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_S 10 + +// Field: [9] FSCA +// +// Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) +// module. +#define RFC_PWR_PWMCLKEN_FSCA 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_BITN 9 +#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_S 9 + +// Field: [8] PHA +// +// Enable clock to the Packet Handling Accelerator (PHA) module. +#define RFC_PWR_PWMCLKEN_PHA 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_BITN 8 +#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_S 8 + +// Field: [7] RAT +// +// Enable clock to the Radio Timer (RAT) module. +#define RFC_PWR_PWMCLKEN_RAT 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_BITN 7 +#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_S 7 + +// Field: [6] RFERAM +// +// Enable clock to the RF Engine RAM module. +#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 +#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_S 6 + +// Field: [5] RFE +// +// Enable clock to the RF Engine (RFE) module. +#define RFC_PWR_PWMCLKEN_RFE 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_BITN 5 +#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_S 5 + +// Field: [4] MDMRAM +// +// Enable clock to the Modem RAM module. +#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 +#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_S 4 + +// Field: [3] MDM +// +// Enable clock to the Modem (MDM) module. +#define RFC_PWR_PWMCLKEN_MDM 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_BITN 3 +#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_S 3 + +// Field: [2] CPERAM +// +// Enable clock to the Command and Packet Engine (CPE) RAM module. As part of +// RF Core initialization, set this bit together with CPE bit to enable CPE to +// boot. +#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 +#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_S 2 + +// Field: [1] CPE +// +// Enable processor clock (hclk) to the Command and Packet Engine (CPE). As +// part of RF Core initialization, set this bit together with CPERAM bit to +// enable CPE to boot. +#define RFC_PWR_PWMCLKEN_CPE 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_BITN 1 +#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_S 1 + +// Field: [0] RFC +// +// Enable essential clocks for the RF Core interface. This includes the +// interconnect, the radio doorbell DBELL command interface, the power +// management (PWR) clock control module, and bus clock (sclk) for the CPE. To +// remove possibility of locking yourself out from the RF Core, this bit can +// not be cleared. If you need to disable all clocks to the RF Core, see the +// PRCM:RFCCLKG.CLK_EN register. +#define RFC_PWR_PWMCLKEN_RFC 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_BITN 0 +#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_S 0 + + +#endif // __RFC_PWR__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_rat.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_rat.h new file mode 100644 index 0000000..83f131c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_rat.h @@ -0,0 +1,190 @@ +/****************************************************************************** +* Filename: hw_rfc_rat_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_RAT_H__ +#define __HW_RFC_RAT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_RAT component +// +//***************************************************************************** +// Radio Timer Counter Value +#define RFC_RAT_O_RATCNT 0x00000004 + +// Timer Channel 0 Capture/Compare Register +#define RFC_RAT_O_RATCH0VAL 0x00000080 + +// Timer Channel 1 Capture/Compare Register +#define RFC_RAT_O_RATCH1VAL 0x00000084 + +// Timer Channel 2 Capture/Compare Register +#define RFC_RAT_O_RATCH2VAL 0x00000088 + +// Timer Channel 3 Capture/Compare Register +#define RFC_RAT_O_RATCH3VAL 0x0000008C + +// Timer Channel 4 Capture/Compare Register +#define RFC_RAT_O_RATCH4VAL 0x00000090 + +// Timer Channel 5 Capture/Compare Register +#define RFC_RAT_O_RATCH5VAL 0x00000094 + +// Timer Channel 6 Capture/Compare Register +#define RFC_RAT_O_RATCH6VAL 0x00000098 + +// Timer Channel 7 Capture/Compare Register +#define RFC_RAT_O_RATCH7VAL 0x0000009C + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCNT +// +//***************************************************************************** +// Field: [31:0] CNT +// +// Counter value. This is not writable while radio timer counter is enabled. +#define RFC_RAT_RATCNT_CNT_W 32 +#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF +#define RFC_RAT_RATCNT_CNT_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH0VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH0VAL_VAL_W 32 +#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH0VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH1VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH1VAL_VAL_W 32 +#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH1VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH2VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH2VAL_VAL_W 32 +#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH2VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH3VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH3VAL_VAL_W 32 +#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH3VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH4VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH4VAL_VAL_W 32 +#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH4VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH5VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH5VAL_VAL_W 32 +#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH5VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH6VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH6VAL_VAL_W 32 +#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH6VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH7VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH7VAL_VAL_W 32 +#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH7VAL_VAL_S 0 + + +#endif // __RFC_RAT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_smph.h new file mode 100644 index 0000000..669eb26 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_smph.h @@ -0,0 +1,1455 @@ +/****************************************************************************** +* Filename: hw_smph_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SMPH_H__ +#define __HW_SMPH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SMPH component +// +//***************************************************************************** +// MCU SEMAPHORE 0 +#define SMPH_O_SMPH0 0x00000000 + +// MCU SEMAPHORE 1 +#define SMPH_O_SMPH1 0x00000004 + +// MCU SEMAPHORE 2 +#define SMPH_O_SMPH2 0x00000008 + +// MCU SEMAPHORE 3 +#define SMPH_O_SMPH3 0x0000000C + +// MCU SEMAPHORE 4 +#define SMPH_O_SMPH4 0x00000010 + +// MCU SEMAPHORE 5 +#define SMPH_O_SMPH5 0x00000014 + +// MCU SEMAPHORE 6 +#define SMPH_O_SMPH6 0x00000018 + +// MCU SEMAPHORE 7 +#define SMPH_O_SMPH7 0x0000001C + +// MCU SEMAPHORE 8 +#define SMPH_O_SMPH8 0x00000020 + +// MCU SEMAPHORE 9 +#define SMPH_O_SMPH9 0x00000024 + +// MCU SEMAPHORE 10 +#define SMPH_O_SMPH10 0x00000028 + +// MCU SEMAPHORE 11 +#define SMPH_O_SMPH11 0x0000002C + +// MCU SEMAPHORE 12 +#define SMPH_O_SMPH12 0x00000030 + +// MCU SEMAPHORE 13 +#define SMPH_O_SMPH13 0x00000034 + +// MCU SEMAPHORE 14 +#define SMPH_O_SMPH14 0x00000038 + +// MCU SEMAPHORE 15 +#define SMPH_O_SMPH15 0x0000003C + +// MCU SEMAPHORE 16 +#define SMPH_O_SMPH16 0x00000040 + +// MCU SEMAPHORE 17 +#define SMPH_O_SMPH17 0x00000044 + +// MCU SEMAPHORE 18 +#define SMPH_O_SMPH18 0x00000048 + +// MCU SEMAPHORE 19 +#define SMPH_O_SMPH19 0x0000004C + +// MCU SEMAPHORE 20 +#define SMPH_O_SMPH20 0x00000050 + +// MCU SEMAPHORE 21 +#define SMPH_O_SMPH21 0x00000054 + +// MCU SEMAPHORE 22 +#define SMPH_O_SMPH22 0x00000058 + +// MCU SEMAPHORE 23 +#define SMPH_O_SMPH23 0x0000005C + +// MCU SEMAPHORE 24 +#define SMPH_O_SMPH24 0x00000060 + +// MCU SEMAPHORE 25 +#define SMPH_O_SMPH25 0x00000064 + +// MCU SEMAPHORE 26 +#define SMPH_O_SMPH26 0x00000068 + +// MCU SEMAPHORE 27 +#define SMPH_O_SMPH27 0x0000006C + +// MCU SEMAPHORE 28 +#define SMPH_O_SMPH28 0x00000070 + +// MCU SEMAPHORE 29 +#define SMPH_O_SMPH29 0x00000074 + +// MCU SEMAPHORE 30 +#define SMPH_O_SMPH30 0x00000078 + +// MCU SEMAPHORE 31 +#define SMPH_O_SMPH31 0x0000007C + +// MCU SEMAPHORE 0 ALIAS +#define SMPH_O_PEEK0 0x00000800 + +// MCU SEMAPHORE 1 ALIAS +#define SMPH_O_PEEK1 0x00000804 + +// MCU SEMAPHORE 2 ALIAS +#define SMPH_O_PEEK2 0x00000808 + +// MCU SEMAPHORE 3 ALIAS +#define SMPH_O_PEEK3 0x0000080C + +// MCU SEMAPHORE 4 ALIAS +#define SMPH_O_PEEK4 0x00000810 + +// MCU SEMAPHORE 5 ALIAS +#define SMPH_O_PEEK5 0x00000814 + +// MCU SEMAPHORE 6 ALIAS +#define SMPH_O_PEEK6 0x00000818 + +// MCU SEMAPHORE 7 ALIAS +#define SMPH_O_PEEK7 0x0000081C + +// MCU SEMAPHORE 8 ALIAS +#define SMPH_O_PEEK8 0x00000820 + +// MCU SEMAPHORE 9 ALIAS +#define SMPH_O_PEEK9 0x00000824 + +// MCU SEMAPHORE 10 ALIAS +#define SMPH_O_PEEK10 0x00000828 + +// MCU SEMAPHORE 11 ALIAS +#define SMPH_O_PEEK11 0x0000082C + +// MCU SEMAPHORE 12 ALIAS +#define SMPH_O_PEEK12 0x00000830 + +// MCU SEMAPHORE 13 ALIAS +#define SMPH_O_PEEK13 0x00000834 + +// MCU SEMAPHORE 14 ALIAS +#define SMPH_O_PEEK14 0x00000838 + +// MCU SEMAPHORE 15 ALIAS +#define SMPH_O_PEEK15 0x0000083C + +// MCU SEMAPHORE 16 ALIAS +#define SMPH_O_PEEK16 0x00000840 + +// MCU SEMAPHORE 17 ALIAS +#define SMPH_O_PEEK17 0x00000844 + +// MCU SEMAPHORE 18 ALIAS +#define SMPH_O_PEEK18 0x00000848 + +// MCU SEMAPHORE 19 ALIAS +#define SMPH_O_PEEK19 0x0000084C + +// MCU SEMAPHORE 20 ALIAS +#define SMPH_O_PEEK20 0x00000850 + +// MCU SEMAPHORE 21 ALIAS +#define SMPH_O_PEEK21 0x00000854 + +// MCU SEMAPHORE 22 ALIAS +#define SMPH_O_PEEK22 0x00000858 + +// MCU SEMAPHORE 23 ALIAS +#define SMPH_O_PEEK23 0x0000085C + +// MCU SEMAPHORE 24 ALIAS +#define SMPH_O_PEEK24 0x00000860 + +// MCU SEMAPHORE 25 ALIAS +#define SMPH_O_PEEK25 0x00000864 + +// MCU SEMAPHORE 26 ALIAS +#define SMPH_O_PEEK26 0x00000868 + +// MCU SEMAPHORE 27 ALIAS +#define SMPH_O_PEEK27 0x0000086C + +// MCU SEMAPHORE 28 ALIAS +#define SMPH_O_PEEK28 0x00000870 + +// MCU SEMAPHORE 29 ALIAS +#define SMPH_O_PEEK29 0x00000874 + +// MCU SEMAPHORE 30 ALIAS +#define SMPH_O_PEEK30 0x00000878 + +// MCU SEMAPHORE 31 ALIAS +#define SMPH_O_PEEK31 0x0000087C + +//***************************************************************************** +// +// Register: SMPH_O_SMPH0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH0_STAT 0x00000001 +#define SMPH_SMPH0_STAT_BITN 0 +#define SMPH_SMPH0_STAT_M 0x00000001 +#define SMPH_SMPH0_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH1_STAT 0x00000001 +#define SMPH_SMPH1_STAT_BITN 0 +#define SMPH_SMPH1_STAT_M 0x00000001 +#define SMPH_SMPH1_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH2_STAT 0x00000001 +#define SMPH_SMPH2_STAT_BITN 0 +#define SMPH_SMPH2_STAT_M 0x00000001 +#define SMPH_SMPH2_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH3_STAT 0x00000001 +#define SMPH_SMPH3_STAT_BITN 0 +#define SMPH_SMPH3_STAT_M 0x00000001 +#define SMPH_SMPH3_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH4_STAT 0x00000001 +#define SMPH_SMPH4_STAT_BITN 0 +#define SMPH_SMPH4_STAT_M 0x00000001 +#define SMPH_SMPH4_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH5_STAT 0x00000001 +#define SMPH_SMPH5_STAT_BITN 0 +#define SMPH_SMPH5_STAT_M 0x00000001 +#define SMPH_SMPH5_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH6_STAT 0x00000001 +#define SMPH_SMPH6_STAT_BITN 0 +#define SMPH_SMPH6_STAT_M 0x00000001 +#define SMPH_SMPH6_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH7_STAT 0x00000001 +#define SMPH_SMPH7_STAT_BITN 0 +#define SMPH_SMPH7_STAT_M 0x00000001 +#define SMPH_SMPH7_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH8 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH8_STAT 0x00000001 +#define SMPH_SMPH8_STAT_BITN 0 +#define SMPH_SMPH8_STAT_M 0x00000001 +#define SMPH_SMPH8_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH9 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH9_STAT 0x00000001 +#define SMPH_SMPH9_STAT_BITN 0 +#define SMPH_SMPH9_STAT_M 0x00000001 +#define SMPH_SMPH9_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH10 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH10_STAT 0x00000001 +#define SMPH_SMPH10_STAT_BITN 0 +#define SMPH_SMPH10_STAT_M 0x00000001 +#define SMPH_SMPH10_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH11 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH11_STAT 0x00000001 +#define SMPH_SMPH11_STAT_BITN 0 +#define SMPH_SMPH11_STAT_M 0x00000001 +#define SMPH_SMPH11_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH12 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH12_STAT 0x00000001 +#define SMPH_SMPH12_STAT_BITN 0 +#define SMPH_SMPH12_STAT_M 0x00000001 +#define SMPH_SMPH12_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH13 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH13_STAT 0x00000001 +#define SMPH_SMPH13_STAT_BITN 0 +#define SMPH_SMPH13_STAT_M 0x00000001 +#define SMPH_SMPH13_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH14 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH14_STAT 0x00000001 +#define SMPH_SMPH14_STAT_BITN 0 +#define SMPH_SMPH14_STAT_M 0x00000001 +#define SMPH_SMPH14_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH15 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH15_STAT 0x00000001 +#define SMPH_SMPH15_STAT_BITN 0 +#define SMPH_SMPH15_STAT_M 0x00000001 +#define SMPH_SMPH15_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH16 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH16_STAT 0x00000001 +#define SMPH_SMPH16_STAT_BITN 0 +#define SMPH_SMPH16_STAT_M 0x00000001 +#define SMPH_SMPH16_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH17 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH17_STAT 0x00000001 +#define SMPH_SMPH17_STAT_BITN 0 +#define SMPH_SMPH17_STAT_M 0x00000001 +#define SMPH_SMPH17_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH18 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH18_STAT 0x00000001 +#define SMPH_SMPH18_STAT_BITN 0 +#define SMPH_SMPH18_STAT_M 0x00000001 +#define SMPH_SMPH18_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH19 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH19_STAT 0x00000001 +#define SMPH_SMPH19_STAT_BITN 0 +#define SMPH_SMPH19_STAT_M 0x00000001 +#define SMPH_SMPH19_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH20 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH20_STAT 0x00000001 +#define SMPH_SMPH20_STAT_BITN 0 +#define SMPH_SMPH20_STAT_M 0x00000001 +#define SMPH_SMPH20_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH21 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH21_STAT 0x00000001 +#define SMPH_SMPH21_STAT_BITN 0 +#define SMPH_SMPH21_STAT_M 0x00000001 +#define SMPH_SMPH21_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH22 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH22_STAT 0x00000001 +#define SMPH_SMPH22_STAT_BITN 0 +#define SMPH_SMPH22_STAT_M 0x00000001 +#define SMPH_SMPH22_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH23 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH23_STAT 0x00000001 +#define SMPH_SMPH23_STAT_BITN 0 +#define SMPH_SMPH23_STAT_M 0x00000001 +#define SMPH_SMPH23_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH24 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH24_STAT 0x00000001 +#define SMPH_SMPH24_STAT_BITN 0 +#define SMPH_SMPH24_STAT_M 0x00000001 +#define SMPH_SMPH24_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH25 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH25_STAT 0x00000001 +#define SMPH_SMPH25_STAT_BITN 0 +#define SMPH_SMPH25_STAT_M 0x00000001 +#define SMPH_SMPH25_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH26 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH26_STAT 0x00000001 +#define SMPH_SMPH26_STAT_BITN 0 +#define SMPH_SMPH26_STAT_M 0x00000001 +#define SMPH_SMPH26_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH27 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH27_STAT 0x00000001 +#define SMPH_SMPH27_STAT_BITN 0 +#define SMPH_SMPH27_STAT_M 0x00000001 +#define SMPH_SMPH27_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH28 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH28_STAT 0x00000001 +#define SMPH_SMPH28_STAT_BITN 0 +#define SMPH_SMPH28_STAT_M 0x00000001 +#define SMPH_SMPH28_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH29 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH29_STAT 0x00000001 +#define SMPH_SMPH29_STAT_BITN 0 +#define SMPH_SMPH29_STAT_M 0x00000001 +#define SMPH_SMPH29_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH30 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH30_STAT 0x00000001 +#define SMPH_SMPH30_STAT_BITN 0 +#define SMPH_SMPH30_STAT_M 0x00000001 +#define SMPH_SMPH30_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH31 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH31_STAT 0x00000001 +#define SMPH_SMPH31_STAT_BITN 0 +#define SMPH_SMPH31_STAT_M 0x00000001 +#define SMPH_SMPH31_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK0_STAT 0x00000001 +#define SMPH_PEEK0_STAT_BITN 0 +#define SMPH_PEEK0_STAT_M 0x00000001 +#define SMPH_PEEK0_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK1_STAT 0x00000001 +#define SMPH_PEEK1_STAT_BITN 0 +#define SMPH_PEEK1_STAT_M 0x00000001 +#define SMPH_PEEK1_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK2_STAT 0x00000001 +#define SMPH_PEEK2_STAT_BITN 0 +#define SMPH_PEEK2_STAT_M 0x00000001 +#define SMPH_PEEK2_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK3_STAT 0x00000001 +#define SMPH_PEEK3_STAT_BITN 0 +#define SMPH_PEEK3_STAT_M 0x00000001 +#define SMPH_PEEK3_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK4_STAT 0x00000001 +#define SMPH_PEEK4_STAT_BITN 0 +#define SMPH_PEEK4_STAT_M 0x00000001 +#define SMPH_PEEK4_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK5_STAT 0x00000001 +#define SMPH_PEEK5_STAT_BITN 0 +#define SMPH_PEEK5_STAT_M 0x00000001 +#define SMPH_PEEK5_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK6_STAT 0x00000001 +#define SMPH_PEEK6_STAT_BITN 0 +#define SMPH_PEEK6_STAT_M 0x00000001 +#define SMPH_PEEK6_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK7_STAT 0x00000001 +#define SMPH_PEEK7_STAT_BITN 0 +#define SMPH_PEEK7_STAT_M 0x00000001 +#define SMPH_PEEK7_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK8 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK8_STAT 0x00000001 +#define SMPH_PEEK8_STAT_BITN 0 +#define SMPH_PEEK8_STAT_M 0x00000001 +#define SMPH_PEEK8_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK9 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK9_STAT 0x00000001 +#define SMPH_PEEK9_STAT_BITN 0 +#define SMPH_PEEK9_STAT_M 0x00000001 +#define SMPH_PEEK9_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK10 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK10_STAT 0x00000001 +#define SMPH_PEEK10_STAT_BITN 0 +#define SMPH_PEEK10_STAT_M 0x00000001 +#define SMPH_PEEK10_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK11 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK11_STAT 0x00000001 +#define SMPH_PEEK11_STAT_BITN 0 +#define SMPH_PEEK11_STAT_M 0x00000001 +#define SMPH_PEEK11_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK12 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK12_STAT 0x00000001 +#define SMPH_PEEK12_STAT_BITN 0 +#define SMPH_PEEK12_STAT_M 0x00000001 +#define SMPH_PEEK12_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK13 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK13_STAT 0x00000001 +#define SMPH_PEEK13_STAT_BITN 0 +#define SMPH_PEEK13_STAT_M 0x00000001 +#define SMPH_PEEK13_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK14 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK14_STAT 0x00000001 +#define SMPH_PEEK14_STAT_BITN 0 +#define SMPH_PEEK14_STAT_M 0x00000001 +#define SMPH_PEEK14_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK15 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK15_STAT 0x00000001 +#define SMPH_PEEK15_STAT_BITN 0 +#define SMPH_PEEK15_STAT_M 0x00000001 +#define SMPH_PEEK15_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK16 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK16_STAT 0x00000001 +#define SMPH_PEEK16_STAT_BITN 0 +#define SMPH_PEEK16_STAT_M 0x00000001 +#define SMPH_PEEK16_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK17 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK17_STAT 0x00000001 +#define SMPH_PEEK17_STAT_BITN 0 +#define SMPH_PEEK17_STAT_M 0x00000001 +#define SMPH_PEEK17_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK18 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK18_STAT 0x00000001 +#define SMPH_PEEK18_STAT_BITN 0 +#define SMPH_PEEK18_STAT_M 0x00000001 +#define SMPH_PEEK18_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK19 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK19_STAT 0x00000001 +#define SMPH_PEEK19_STAT_BITN 0 +#define SMPH_PEEK19_STAT_M 0x00000001 +#define SMPH_PEEK19_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK20 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK20_STAT 0x00000001 +#define SMPH_PEEK20_STAT_BITN 0 +#define SMPH_PEEK20_STAT_M 0x00000001 +#define SMPH_PEEK20_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK21 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK21_STAT 0x00000001 +#define SMPH_PEEK21_STAT_BITN 0 +#define SMPH_PEEK21_STAT_M 0x00000001 +#define SMPH_PEEK21_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK22 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK22_STAT 0x00000001 +#define SMPH_PEEK22_STAT_BITN 0 +#define SMPH_PEEK22_STAT_M 0x00000001 +#define SMPH_PEEK22_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK23 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK23_STAT 0x00000001 +#define SMPH_PEEK23_STAT_BITN 0 +#define SMPH_PEEK23_STAT_M 0x00000001 +#define SMPH_PEEK23_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK24 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK24_STAT 0x00000001 +#define SMPH_PEEK24_STAT_BITN 0 +#define SMPH_PEEK24_STAT_M 0x00000001 +#define SMPH_PEEK24_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK25 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK25_STAT 0x00000001 +#define SMPH_PEEK25_STAT_BITN 0 +#define SMPH_PEEK25_STAT_M 0x00000001 +#define SMPH_PEEK25_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK26 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK26_STAT 0x00000001 +#define SMPH_PEEK26_STAT_BITN 0 +#define SMPH_PEEK26_STAT_M 0x00000001 +#define SMPH_PEEK26_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK27 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK27_STAT 0x00000001 +#define SMPH_PEEK27_STAT_BITN 0 +#define SMPH_PEEK27_STAT_M 0x00000001 +#define SMPH_PEEK27_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK28 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK28_STAT 0x00000001 +#define SMPH_PEEK28_STAT_BITN 0 +#define SMPH_PEEK28_STAT_M 0x00000001 +#define SMPH_PEEK28_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK29 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK29_STAT 0x00000001 +#define SMPH_PEEK29_STAT_BITN 0 +#define SMPH_PEEK29_STAT_M 0x00000001 +#define SMPH_PEEK29_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK30 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK30_STAT 0x00000001 +#define SMPH_PEEK30_STAT_BITN 0 +#define SMPH_PEEK30_STAT_M 0x00000001 +#define SMPH_PEEK30_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK31 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK31_STAT 0x00000001 +#define SMPH_PEEK31_STAT_BITN 0 +#define SMPH_PEEK31_STAT_M 0x00000001 +#define SMPH_PEEK31_STAT_S 0 + + +#endif // __SMPH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ssi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ssi.h new file mode 100644 index 0000000..a83b856 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ssi.h @@ -0,0 +1,544 @@ +/****************************************************************************** +* Filename: hw_ssi_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SSI component +// +//***************************************************************************** +// Control 0 +#define SSI_O_CR0 0x00000000 + +// Control 1 +#define SSI_O_CR1 0x00000004 + +// Data +#define SSI_O_DR 0x00000008 + +// Status +#define SSI_O_SR 0x0000000C + +// Clock Prescale +#define SSI_O_CPSR 0x00000010 + +// Interrupt Mask Set and Clear +#define SSI_O_IMSC 0x00000014 + +// Raw Interrupt Status +#define SSI_O_RIS 0x00000018 + +// Masked Interrupt Status +#define SSI_O_MIS 0x0000001C + +// Interrupt Clear +#define SSI_O_ICR 0x00000020 + +// DMA Control +#define SSI_O_DMACR 0x00000024 + +//***************************************************************************** +// +// Register: SSI_O_CR0 +// +//***************************************************************************** +// Field: [15:8] SCR +// +// Serial clock rate: +// This is used to generate the transmit and receive bit rate of the SSI. The +// bit rate is +// (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). +// SCR is a value from 0-255. +#define SSI_CR0_SCR_W 8 +#define SSI_CR0_SCR_M 0x0000FF00 +#define SSI_CR0_SCR_S 8 + +// Field: [7] SPH +// +// CLKOUT phase (Motorola SPI frame format only) +// This bit selects the clock edge that captures data and enables it to change +// state. It +// has the most impact on the first bit transmitted by either permitting or not +// permitting a clock transition before the first data capture edge. +// ENUMs: +// 2ND_CLK_EDGE Data is captured on the second clock edge +// transition. +// 1ST_CLK_EDGE Data is captured on the first clock edge +// transition. +#define SSI_CR0_SPH 0x00000080 +#define SSI_CR0_SPH_BITN 7 +#define SSI_CR0_SPH_M 0x00000080 +#define SSI_CR0_SPH_S 7 +#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 +#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 + +// Field: [6] SPO +// +// CLKOUT polarity (Motorola SPI frame format only) +// ENUMs: +// HIGH SSI produces a steady state HIGH value on the +// CLKOUT pin when data is not being transferred. +// LOW SSI produces a steady state LOW value on the +// CLKOUT pin when data is +// not being transferred. +#define SSI_CR0_SPO 0x00000040 +#define SSI_CR0_SPO_BITN 6 +#define SSI_CR0_SPO_M 0x00000040 +#define SSI_CR0_SPO_S 6 +#define SSI_CR0_SPO_HIGH 0x00000040 +#define SSI_CR0_SPO_LOW 0x00000000 + +// Field: [5:4] FRF +// +// Frame format. +// The supported frame formats are Motorola SPI, TI synchronous serial and +// National Microwire. +// Value 0'b11 is reserved and shall not be used. +// ENUMs: +// NATIONAL_MICROWIRE National Microwire frame format +// TI_SYNC_SERIAL TI synchronous serial frame format +// MOTOROLA_SPI Motorola SPI frame format +#define SSI_CR0_FRF_W 2 +#define SSI_CR0_FRF_M 0x00000030 +#define SSI_CR0_FRF_S 4 +#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 +#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 +#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 + +// Field: [3:0] DSS +// +// Data Size Select. +// Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used. +// ENUMs: +// 16_BIT 16-bit data +// 15_BIT 15-bit data +// 14_BIT 14-bit data +// 13_BIT 13-bit data +// 12_BIT 12-bit data +// 11_BIT 11-bit data +// 10_BIT 10-bit data +// 9_BIT 9-bit data +// 8_BIT 8-bit data +// 7_BIT 7-bit data +// 6_BIT 6-bit data +// 5_BIT 5-bit data +// 4_BIT 4-bit data +#define SSI_CR0_DSS_W 4 +#define SSI_CR0_DSS_M 0x0000000F +#define SSI_CR0_DSS_S 0 +#define SSI_CR0_DSS_16_BIT 0x0000000F +#define SSI_CR0_DSS_15_BIT 0x0000000E +#define SSI_CR0_DSS_14_BIT 0x0000000D +#define SSI_CR0_DSS_13_BIT 0x0000000C +#define SSI_CR0_DSS_12_BIT 0x0000000B +#define SSI_CR0_DSS_11_BIT 0x0000000A +#define SSI_CR0_DSS_10_BIT 0x00000009 +#define SSI_CR0_DSS_9_BIT 0x00000008 +#define SSI_CR0_DSS_8_BIT 0x00000007 +#define SSI_CR0_DSS_7_BIT 0x00000006 +#define SSI_CR0_DSS_6_BIT 0x00000005 +#define SSI_CR0_DSS_5_BIT 0x00000004 +#define SSI_CR0_DSS_4_BIT 0x00000003 + +//***************************************************************************** +// +// Register: SSI_O_CR1 +// +//***************************************************************************** +// Field: [3] SOD +// +// Slave-mode output disabled +// This bit is relevant only in the slave mode, MS=1. In multiple-slave +// systems, it is possible for an SSI master to broadcast a message to all +// slaves in the system while ensuring that only one slave drives data onto its +// serial output line. In such systems the RXD lines from multiple slaves could +// be tied together. To operate in such systems, this bitfield can be set if +// the SSI slave is not supposed to drive the TXD line: +// +// 0: SSI can drive the TXD output in slave mode. +// 1: SSI cannot drive the TXD output in slave mode. +#define SSI_CR1_SOD 0x00000008 +#define SSI_CR1_SOD_BITN 3 +#define SSI_CR1_SOD_M 0x00000008 +#define SSI_CR1_SOD_S 3 + +// Field: [2] MS +// +// Master or slave mode select. This bit can be modified only when SSI is +// disabled, SSE=0. +// ENUMs: +// SLAVE Device configured as slave +// MASTER Device configured as master +#define SSI_CR1_MS 0x00000004 +#define SSI_CR1_MS_BITN 2 +#define SSI_CR1_MS_M 0x00000004 +#define SSI_CR1_MS_S 2 +#define SSI_CR1_MS_SLAVE 0x00000004 +#define SSI_CR1_MS_MASTER 0x00000000 + +// Field: [1] SSE +// +// Synchronous serial interface enable. +// ENUMs: +// SSI_ENABLED Operation enabled +// SSI_DISABLED Operation disabled +#define SSI_CR1_SSE 0x00000002 +#define SSI_CR1_SSE_BITN 1 +#define SSI_CR1_SSE_M 0x00000002 +#define SSI_CR1_SSE_S 1 +#define SSI_CR1_SSE_SSI_ENABLED 0x00000002 +#define SSI_CR1_SSE_SSI_DISABLED 0x00000000 + +// Field: [0] LBM +// +// Loop back mode: +// +// 0: Normal serial port operation enabled. +// 1: Output of transmit serial shifter is connected to input of receive serial +// shifter internally. +#define SSI_CR1_LBM 0x00000001 +#define SSI_CR1_LBM_BITN 0 +#define SSI_CR1_LBM_M 0x00000001 +#define SSI_CR1_LBM_S 0 + +//***************************************************************************** +// +// Register: SSI_O_DR +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Transmit/receive data +// The values read from this field or written to this field must be +// right-justified when SSI is programmed for a data size that is less than 16 +// bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit +// logic. The receive logic automatically right-justifies. +#define SSI_DR_DATA_W 16 +#define SSI_DR_DATA_M 0x0000FFFF +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// Register: SSI_O_SR +// +//***************************************************************************** +// Field: [4] BSY +// +// Serial interface busy: +// +// 0: SSI is idle +// 1: SSI is currently transmitting and/or receiving a frame or the transmit +// FIFO is not empty. +#define SSI_SR_BSY 0x00000010 +#define SSI_SR_BSY_BITN 4 +#define SSI_SR_BSY_M 0x00000010 +#define SSI_SR_BSY_S 4 + +// Field: [3] RFF +// +// Receive FIFO full: +// +// 0: Receive FIFO is not full. +// 1: Receive FIFO is full. +#define SSI_SR_RFF 0x00000008 +#define SSI_SR_RFF_BITN 3 +#define SSI_SR_RFF_M 0x00000008 +#define SSI_SR_RFF_S 3 + +// Field: [2] RNE +// +// Receive FIFO not empty +// +// 0: Receive FIFO is empty. +// 1: Receive FIFO is not empty. +#define SSI_SR_RNE 0x00000004 +#define SSI_SR_RNE_BITN 2 +#define SSI_SR_RNE_M 0x00000004 +#define SSI_SR_RNE_S 2 + +// Field: [1] TNF +// +// Transmit FIFO not full: +// +// 0: Transmit FIFO is full. +// 1: Transmit FIFO is not full. +#define SSI_SR_TNF 0x00000002 +#define SSI_SR_TNF_BITN 1 +#define SSI_SR_TNF_M 0x00000002 +#define SSI_SR_TNF_S 1 + +// Field: [0] TFE +// +// Transmit FIFO empty: +// +// 0: Transmit FIFO is not empty. +// 1: Transmit FIFO is empty. +#define SSI_SR_TFE 0x00000001 +#define SSI_SR_TFE_BITN 0 +#define SSI_SR_TFE_M 0x00000001 +#define SSI_SR_TFE_S 0 + +//***************************************************************************** +// +// Register: SSI_O_CPSR +// +//***************************************************************************** +// Field: [7:0] CPSDVSR +// +// Clock prescale divisor: +// This field specifies the division factor by which the input system clock to +// SSI must be internally divided before further use. +// The value programmed into this field must be an even non-zero number +// (2-254). The least significant bit of the programmed number is hard-coded to +// zero. If an odd number is written to this register, data read back from +// this register has the least significant bit as zero. +#define SSI_CPSR_CPSDVSR_W 8 +#define SSI_CPSR_CPSDVSR_M 0x000000FF +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// Register: SSI_O_IMSC +// +//***************************************************************************** +// Field: [3] TXIM +// +// Transmit FIFO interrupt mask: +// A read returns the current mask for transmit FIFO interrupt. On a write of +// 1, the mask for transmit FIFO interrupt is set which means the interrupt +// state will be reflected in MIS.TXMIS. A write of 0 clears the mask which +// means MIS.TXMIS will not reflect the interrupt. +#define SSI_IMSC_TXIM 0x00000008 +#define SSI_IMSC_TXIM_BITN 3 +#define SSI_IMSC_TXIM_M 0x00000008 +#define SSI_IMSC_TXIM_S 3 + +// Field: [2] RXIM +// +// Receive FIFO interrupt mask: +// A read returns the current mask for receive FIFO interrupt. On a write of 1, +// the mask for receive FIFO interrupt is set which means the interrupt state +// will be reflected in MIS.RXMIS. A write of 0 clears the mask which means +// MIS.RXMIS will not reflect the interrupt. +#define SSI_IMSC_RXIM 0x00000004 +#define SSI_IMSC_RXIM_BITN 2 +#define SSI_IMSC_RXIM_M 0x00000004 +#define SSI_IMSC_RXIM_S 2 + +// Field: [1] RTIM +// +// Receive timeout interrupt mask: +// A read returns the current mask for receive timeout interrupt. On a write of +// 1, the mask for receive timeout interrupt is set which means the interrupt +// state will be reflected in MIS.RTMIS. A write of 0 clears the mask which +// means MIS.RTMIS will not reflect the interrupt. +#define SSI_IMSC_RTIM 0x00000002 +#define SSI_IMSC_RTIM_BITN 1 +#define SSI_IMSC_RTIM_M 0x00000002 +#define SSI_IMSC_RTIM_S 1 + +// Field: [0] RORIM +// +// Receive overrun interrupt mask: +// A read returns the current mask for receive overrun interrupt. On a write of +// 1, the mask for receive overrun interrupt is set which means the interrupt +// state will be reflected in MIS.RORMIS. A write of 0 clears the mask which +// means MIS.RORMIS will not reflect the interrupt. +#define SSI_IMSC_RORIM 0x00000001 +#define SSI_IMSC_RORIM_BITN 0 +#define SSI_IMSC_RORIM_M 0x00000001 +#define SSI_IMSC_RORIM_S 0 + +//***************************************************************************** +// +// Register: SSI_O_RIS +// +//***************************************************************************** +// Field: [3] TXRIS +// +// Raw transmit FIFO interrupt status: +// The transmit interrupt is asserted when there are four or fewer valid +// entries in the transmit FIFO. The transmit interrupt is not qualified with +// the SSI enable signal. Therefore one of the following ways can be used: +// - data can be written to the transmit FIFO prior to enabling the SSI and +// the +// interrupts. +// - SSI and interrupts can be enabled so that data can be written to the +// transmit FIFO by an interrupt service routine. +#define SSI_RIS_TXRIS 0x00000008 +#define SSI_RIS_TXRIS_BITN 3 +#define SSI_RIS_TXRIS_M 0x00000008 +#define SSI_RIS_TXRIS_S 3 + +// Field: [2] RXRIS +// +// Raw interrupt state of receive FIFO interrupt: +// The receive interrupt is asserted when there are four or more valid entries +// in the receive FIFO. +#define SSI_RIS_RXRIS 0x00000004 +#define SSI_RIS_RXRIS_BITN 2 +#define SSI_RIS_RXRIS_M 0x00000004 +#define SSI_RIS_RXRIS_S 2 + +// Field: [1] RTRIS +// +// Raw interrupt state of receive timeout interrupt: +// The receive timeout interrupt is asserted when the receive FIFO is not empty +// and SSI has remained idle for a fixed 32 bit period. This mechanism can be +// used to notify the user that data is still present in the receive FIFO and +// requires servicing. This interrupt is deasserted if the receive FIFO becomes +// empty by subsequent reads, or if new data is received on RXD. +// It can also be cleared by writing to ICR.RTIC. +#define SSI_RIS_RTRIS 0x00000002 +#define SSI_RIS_RTRIS_BITN 1 +#define SSI_RIS_RTRIS_M 0x00000002 +#define SSI_RIS_RTRIS_S 1 + +// Field: [0] RORRIS +// +// Raw interrupt state of receive overrun interrupt: +// The receive overrun interrupt is asserted when the FIFO is already full and +// an additional data frame is received, causing an overrun of the FIFO. Data +// is over-written in the +// receive shift register, but not the FIFO so the FIFO contents stay valid. +// It can also be cleared by writing to ICR.RORIC. +#define SSI_RIS_RORRIS 0x00000001 +#define SSI_RIS_RORRIS_BITN 0 +#define SSI_RIS_RORRIS_M 0x00000001 +#define SSI_RIS_RORRIS_S 0 + +//***************************************************************************** +// +// Register: SSI_O_MIS +// +//***************************************************************************** +// Field: [3] TXMIS +// +// Masked interrupt state of transmit FIFO interrupt: +// This field returns the masked interrupt state of transmit FIFO interrupt +// which is the AND product of raw interrupt state RIS.TXRIS and the mask +// setting IMSC.TXIM. +#define SSI_MIS_TXMIS 0x00000008 +#define SSI_MIS_TXMIS_BITN 3 +#define SSI_MIS_TXMIS_M 0x00000008 +#define SSI_MIS_TXMIS_S 3 + +// Field: [2] RXMIS +// +// Masked interrupt state of receive FIFO interrupt: +// This field returns the masked interrupt state of receive FIFO interrupt +// which is the AND product of raw interrupt state RIS.RXRIS and the mask +// setting IMSC.RXIM. +#define SSI_MIS_RXMIS 0x00000004 +#define SSI_MIS_RXMIS_BITN 2 +#define SSI_MIS_RXMIS_M 0x00000004 +#define SSI_MIS_RXMIS_S 2 + +// Field: [1] RTMIS +// +// Masked interrupt state of receive timeout interrupt: +// This field returns the masked interrupt state of receive timeout interrupt +// which is the AND product of raw interrupt state RIS.RTRIS and the mask +// setting IMSC.RTIM. +#define SSI_MIS_RTMIS 0x00000002 +#define SSI_MIS_RTMIS_BITN 1 +#define SSI_MIS_RTMIS_M 0x00000002 +#define SSI_MIS_RTMIS_S 1 + +// Field: [0] RORMIS +// +// Masked interrupt state of receive overrun interrupt: +// This field returns the masked interrupt state of receive overrun interrupt +// which is the AND product of raw interrupt state RIS.RORRIS and the mask +// setting IMSC.RORIM. +#define SSI_MIS_RORMIS 0x00000001 +#define SSI_MIS_RORMIS_BITN 0 +#define SSI_MIS_RORMIS_M 0x00000001 +#define SSI_MIS_RORMIS_S 0 + +//***************************************************************************** +// +// Register: SSI_O_ICR +// +//***************************************************************************** +// Field: [1] RTIC +// +// Clear the receive timeout interrupt: +// Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 +// has no effect. +#define SSI_ICR_RTIC 0x00000002 +#define SSI_ICR_RTIC_BITN 1 +#define SSI_ICR_RTIC_M 0x00000002 +#define SSI_ICR_RTIC_S 1 + +// Field: [0] RORIC +// +// Clear the receive overrun interrupt: +// Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). +// Writing 0 has no effect. +#define SSI_ICR_RORIC 0x00000001 +#define SSI_ICR_RORIC_BITN 0 +#define SSI_ICR_RORIC_M 0x00000001 +#define SSI_ICR_RORIC_S 0 + +//***************************************************************************** +// +// Register: SSI_O_DMACR +// +//***************************************************************************** +// Field: [1] TXDMAE +// +// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is +// enabled. +#define SSI_DMACR_TXDMAE 0x00000002 +#define SSI_DMACR_TXDMAE_BITN 1 +#define SSI_DMACR_TXDMAE_M 0x00000002 +#define SSI_DMACR_TXDMAE_S 1 + +// Field: [0] RXDMAE +// +// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is +// enabled. +#define SSI_DMACR_RXDMAE 0x00000001 +#define SSI_DMACR_RXDMAE_BITN 0 +#define SSI_DMACR_RXDMAE_M 0x00000001 +#define SSI_DMACR_RXDMAE_S 0 + + +#endif // __SSI__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_sysctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_sysctl.h new file mode 100644 index 0000000..1ddd6bb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_sysctl.h @@ -0,0 +1,49 @@ +/****************************************************************************** +* Filename: hw_sysctl.h +* Revised: 2015-03-16 14:43:45 +0100 (Mon, 16 Mar 2015) +* Revision: 42989 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + + +//***************************************************************************** +// +// The following are initial defines for the MCU clock +// +//***************************************************************************** +#define GET_MCU_CLOCK 48000000 + + +#endif // __HW_SYSCTL_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_trng.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_trng.h new file mode 100644 index 0000000..21aa93c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_trng.h @@ -0,0 +1,609 @@ +/****************************************************************************** +* Filename: hw_trng_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_TRNG_H__ +#define __HW_TRNG_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// TRNG component +// +//***************************************************************************** +// Random Number Lower Word Readout Value +#define TRNG_O_OUT0 0x00000000 + +// Random Number Upper Word Readout Value +#define TRNG_O_OUT1 0x00000004 + +// Interrupt Status +#define TRNG_O_IRQFLAGSTAT 0x00000008 + +// Interrupt Mask +#define TRNG_O_IRQFLAGMASK 0x0000000C + +// Interrupt Flag Clear +#define TRNG_O_IRQFLAGCLR 0x00000010 + +// Control +#define TRNG_O_CTL 0x00000014 + +// Configuration 0 +#define TRNG_O_CFG0 0x00000018 + +// Alarm Control +#define TRNG_O_ALARMCNT 0x0000001C + +// FRO Enable +#define TRNG_O_FROEN 0x00000020 + +// FRO De-tune Bit +#define TRNG_O_FRODETUNE 0x00000024 + +// Alarm Event +#define TRNG_O_ALARMMASK 0x00000028 + +// Alarm Shutdown +#define TRNG_O_ALARMSTOP 0x0000002C + +// LFSR Readout Value +#define TRNG_O_LFSR0 0x00000030 + +// LFSR Readout Value +#define TRNG_O_LFSR1 0x00000034 + +// LFSR Readout Value +#define TRNG_O_LFSR2 0x00000038 + +// TRNG Engine Options Information +#define TRNG_O_HWOPT 0x00000078 + +// HW Version 0 +#define TRNG_O_HWVER0 0x0000007C + +// Interrupt Status After Masking +#define TRNG_O_IRQSTATMASK 0x00001FD8 + +// HW Version 1 +#define TRNG_O_HWVER1 0x00001FE0 + +// Interrupt Set +#define TRNG_O_IRQSET 0x00001FEC + +// SW Reset Control +#define TRNG_O_SWRESET 0x00001FF0 + +// Interrupt Status +#define TRNG_O_IRQSTAT 0x00001FF8 + +//***************************************************************************** +// +// Register: TRNG_O_OUT0 +// +//***************************************************************************** +// Field: [31:0] VALUE_31_0 +// +// LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. +#define TRNG_OUT0_VALUE_31_0_W 32 +#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF +#define TRNG_OUT0_VALUE_31_0_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_OUT1 +// +//***************************************************************************** +// Field: [31:0] VALUE_63_32 +// +// MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. +#define TRNG_OUT1_VALUE_63_32_W 32 +#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF +#define TRNG_OUT1_VALUE_63_32_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGSTAT +// +//***************************************************************************** +// Field: [31] NEED_CLOCK +// +// 1: Indicates that the TRNG is busy generating entropy or is in one of its +// test modes - clocks may not be turned off and the power supply voltage must +// be kept stable. +// 0: TRNG is idle and can be shut down +#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 + +// Field: [1] SHUTDOWN_OVF +// +// 1: The number of FROs shut down (i.e. the number of '1' bits in the +// ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR +// +// Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Data are available in OUT0 and OUT1. +// +// Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears this bit to +// '0'. +// If a new number is already available in the internal register of the TRNG, +// the number is directly clocked into the result register. In this case the +// status bit is asserted again, after one clock cycle. +#define TRNG_IRQFLAGSTAT_RDY 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_BITN 0 +#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGMASK +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this +// module. +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. +#define TRNG_IRQFLAGMASK_RDY 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_BITN 0 +#define TRNG_IRQFLAGMASK_RDY_M 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGCLR +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Clear IRQFLAGSTAT.RDY. +#define TRNG_IRQFLAGCLR_RDY 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_BITN 0 +#define TRNG_IRQFLAGCLR_RDY_M 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_CTL +// +//***************************************************************************** +// Field: [31:16] STARTUP_CYCLES +// +// This field determines the number of samples (between 2^8 and 2^24) taken to +// gather entropy from the FROs during startup. If the written value of this +// field is zero, the number of samples is 2^24, otherwise the number of +// samples equals the written value times 2^8. +// +// 0x0000: 2^24 samples +// 0x0001: 1*2^8 samples +// 0x0002: 2*2^8 samples +// 0x0003: 3*2^8 samples +// ... +// 0x8000: 32768*2^8 samples +// 0xC000: 49152*2^8 samples +// ... +// 0xFFFF: 65535*2^8 samples +// +// This field can only be modified while TRNG_EN is 0. If 1 an update will be +// ignored. +#define TRNG_CTL_STARTUP_CYCLES_W 16 +#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 +#define TRNG_CTL_STARTUP_CYCLES_S 16 + +// Field: [10] TRNG_EN +// +// 0: Forces all TRNG logic back into the idle state immediately. +// 1: Starts TRNG, gathering entropy from the FROs for the number of samples +// determined by STARTUP_CYCLES. +#define TRNG_CTL_TRNG_EN 0x00000400 +#define TRNG_CTL_TRNG_EN_BITN 10 +#define TRNG_CTL_TRNG_EN_M 0x00000400 +#define TRNG_CTL_TRNG_EN_S 10 + +// Field: [2] NO_LFSR_FB +// +// 1: Remove XNOR feedback from the main LFSR, converting it into a normal +// shift register for the XOR-ed outputs of the FROs (shifting data in on the +// LSB side). A '1' also forces the LFSR to sample continuously. +// +// This bit can only be set to '1' when TEST_MODE is also set to '1' and should +// not be used for other than test purposes +#define TRNG_CTL_NO_LFSR_FB 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_BITN 2 +#define TRNG_CTL_NO_LFSR_FB_M 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_S 2 + +// Field: [1] TEST_MODE +// +// 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2 registers (the latter +// are automatically cleared before enabling access) and keeps +// IRQFLAGSTAT.NEED_CLOCK at '1'. +// +// This bit shall not be used unless you need to change the LFSR seed prior to +// creating a new random value. All other testing is done external to register +// control. +#define TRNG_CTL_TEST_MODE 0x00000002 +#define TRNG_CTL_TEST_MODE_BITN 1 +#define TRNG_CTL_TEST_MODE_M 0x00000002 +#define TRNG_CTL_TEST_MODE_S 1 + +//***************************************************************************** +// +// Register: TRNG_O_CFG0 +// +//***************************************************************************** +// Field: [31:16] MAX_REFILL_CYCLES +// +// This field determines the maximum number of samples (between 2^8 and 2^24) +// taken to re-generate entropy from the FROs after reading out a 64 bits +// random number. If the written value of this field is zero, the number of +// samples is 2^24, otherwise the number of samples equals the written value +// times 2^8. +// +// 0x0000: 2^24 samples +// 0x0001: 1*2^8 samples +// 0x0002: 2*2^8 samples +// 0x0003: 3*2^8 samples +// ... +// 0x8000: 32768*2^8 samples +// 0xC000: 49152*2^8 samples +// ... +// 0xFFFF: 65535*2^8 samples +// +// This field can only be modified while CTL.TRNG_EN is 0. +#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 +#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 +#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 + +// Field: [11:8] SMPL_DIV +// +// This field directly controls the number of clock cycles between samples +// taken from the FROs. Default value 0 indicates that samples are taken every +// clock cycle, +// maximum value 0xF takes one sample every 16 clock cycles. +// This field must be set to a value such that the slowest FRO (even under +// worst-case +// conditions) has a cycle time less than twice the sample period. +// +// This field can only be modified while CTL.TRNG_EN is '0'. +#define TRNG_CFG0_SMPL_DIV_W 4 +#define TRNG_CFG0_SMPL_DIV_M 0x00000F00 +#define TRNG_CFG0_SMPL_DIV_S 8 + +// Field: [7:0] MIN_REFILL_CYCLES +// +// This field determines the minimum number of samples (between 2^6 and 2^14) +// taken to re-generate entropy from the FROs after reading out a 64 bits +// random number. If the value of this field is zero, the number of samples is +// fixed to the value determined by the MAX_REFILL_CYCLES field, otherwise the +// minimum number of samples equals the written value times 64 (which can be up +// to 2^14). To ensure same entropy in all generated random numbers the value 0 +// should be used. Then MAX_REFILL_CYCLES controls the minimum refill interval. +// The number of samples defined here cannot be higher than the number defined +// by the 'max_refill_cycles' field (i.e. that field takes precedence). No +// random value will be created if min refill > max refill. +// +// This field can only be modified while CTL.TRNG_EN = 0. +// +// 0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers have same entropy) +// 0x01: 1*2^6 samples +// 0x02: 2*2^6 samples +// ... +// 0xFF: 255*2^6 samples +#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 +#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF +#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMCNT +// +//***************************************************************************** +// Field: [29:24] SHUTDOWN_CNT +// +// Read-only, indicates the number of '1' bits in ALARMSTOP register. +// The maximum value equals the number of FROs. +#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 + +// Field: [20:16] SHUTDOWN_THR +// +// Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The +// interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. +#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 +#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 +#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 + +// Field: [7:0] ALARM_THR +// +// Alarm detection threshold for the repeating pattern detectors on each FRO. +// An FRO 'alarm event' is declared when a repeating pattern (of up to four +// samples length) is detected continuously for the number of samples defined +// by this field's value. Reset value 0xFF should keep the number of 'alarm +// events' to a manageable level. +#define TRNG_ALARMCNT_ALARM_THR_W 8 +#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF +#define TRNG_ALARMCNT_ALARM_THR_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_FROEN +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'. +// Default state is all '1's to enable all FROs after power-up. Note that they +// are not actually started up before the CTL.TRNG_EN bit is set to '1'. +// +// Bits are automatically forced to '0' here (and cannot be written to '1') +// while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. +#define TRNG_FROEN_FRO_MASK_W 24 +#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF +#define TRNG_FROEN_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_FRODETUNE +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run +// approximately 5% faster. The value of one of these bits may only be changed +// while the corresponding FRO is turned off (by temporarily writing a '0' in +// the corresponding +// bit of the FROEN.FRO_MASK register). +#define TRNG_FRODETUNE_FRO_MASK_W 24 +#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF +#define TRNG_FRODETUNE_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMMASK +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] +// indicates FRO 'n' experienced an 'alarm event'. +#define TRNG_ALARMMASK_FRO_MASK_W 24 +#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF +#define TRNG_ALARMMASK_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMSTOP +// +//***************************************************************************** +// Field: [23:0] FRO_FLAGS +// +// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] +// indicates FRO 'n' experienced more than one 'alarm event' in quick +// succession and has been turned off. A '1' in this field forces the +// corresponding bit in FROEN.FRO_MASK to '0'. +#define TRNG_ALARMSTOP_FRO_FLAGS_W 24 +#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF +#define TRNG_ALARMSTOP_FRO_FLAGS_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR0 +// +//***************************************************************************** +// Field: [31:0] LFSR_31_0 +// +// Bits [31:0] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR0_LFSR_31_0_W 32 +#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF +#define TRNG_LFSR0_LFSR_31_0_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR1 +// +//***************************************************************************** +// Field: [31:0] LFSR_63_32 +// +// Bits [63:32] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR1_LFSR_63_32_W 32 +#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF +#define TRNG_LFSR1_LFSR_63_32_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR2 +// +//***************************************************************************** +// Field: [16:0] LFSR_80_64 +// +// Bits [80:64] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR2_LFSR_80_64_W 17 +#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF +#define TRNG_LFSR2_LFSR_80_64_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_HWOPT +// +//***************************************************************************** +// Field: [11:6] NR_OF_FROS +// +// Number of FROs implemented in this TRNG, value 24 (decimal). +#define TRNG_HWOPT_NR_OF_FROS_W 6 +#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 +#define TRNG_HWOPT_NR_OF_FROS_S 6 + +//***************************************************************************** +// +// Register: TRNG_O_HWVER0 +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VER +// +// 4 bits binary encoding of the major hardware revision number. +#define TRNG_HWVER0_HW_MAJOR_VER_W 4 +#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 +#define TRNG_HWVER0_HW_MAJOR_VER_S 24 + +// Field: [23:20] HW_MINOR_VER +// +// 4 bits binary encoding of the minor hardware revision number. +#define TRNG_HWVER0_HW_MINOR_VER_W 4 +#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 +#define TRNG_HWVER0_HW_MINOR_VER_S 20 + +// Field: [19:16] HW_PATCH_LVL +// +// 4 bits binary encoding of the hardware patch level, initial release will +// carry value zero. +#define TRNG_HWVER0_HW_PATCH_LVL_W 4 +#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 +#define TRNG_HWVER0_HW_PATCH_LVL_S 16 + +// Field: [15:8] EIP_NUM_COMPL +// +// Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. +#define TRNG_HWVER0_EIP_NUM_COMPL_W 8 +#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 +#define TRNG_HWVER0_EIP_NUM_COMPL_S 8 + +// Field: [7:0] EIP_NUM +// +// 8 bits binary encoding of the module number. This TRNG gives 0x4B. +#define TRNG_HWVER0_EIP_NUM_W 8 +#define TRNG_HWVER0_EIP_NUM_M 0x000000FF +#define TRNG_HWVER0_EIP_NUM_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSTATMASK +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with +// IRQFLAGMASK.SHUTDOWN_OVF) +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// New random value available (result of IRQFLAGSTAT.RDY AND'ed with +// IRQFLAGMASK.RDY) +#define TRNG_IRQSTATMASK_RDY 0x00000001 +#define TRNG_IRQSTATMASK_RDY_BITN 0 +#define TRNG_IRQSTATMASK_RDY_M 0x00000001 +#define TRNG_IRQSTATMASK_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_HWVER1 +// +//***************************************************************************** +// Field: [7:0] REV +// +// The revision number of this module is Rev 2.0. +#define TRNG_HWVER1_REV_W 8 +#define TRNG_HWVER1_REV_M 0x000000FF +#define TRNG_HWVER1_REV_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSET +// +//***************************************************************************** +//***************************************************************************** +// +// Register: TRNG_O_SWRESET +// +//***************************************************************************** +// Field: [0] RESET +// +// Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 +// for reset to be completed. +#define TRNG_SWRESET_RESET 0x00000001 +#define TRNG_SWRESET_RESET_BITN 0 +#define TRNG_SWRESET_RESET_M 0x00000001 +#define TRNG_SWRESET_RESET_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSTAT +// +//***************************************************************************** +// Field: [0] STAT +// +// TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and +// IRQFLAGSTAT.RDY +#define TRNG_IRQSTAT_STAT 0x00000001 +#define TRNG_IRQSTAT_STAT_BITN 0 +#define TRNG_IRQSTAT_STAT_M 0x00000001 +#define TRNG_IRQSTAT_STAT_S 0 + + +#endif // __TRNG__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_types.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_types.h new file mode 100644 index 0000000..dfa4281 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_types.h @@ -0,0 +1,123 @@ +/****************************************************************************** +* Filename: hw_types.h +* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) +* Revision: 47152 +* +* Description: Common types and macros. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +#include +#include +#include "../inc/hw_chip_def.h" + +//***************************************************************************** +// +// Common driverlib types +// +//***************************************************************************** +typedef void (* FPTR_VOID_VOID_T) (void); +typedef void (* FPTR_VOID_UINT8_T) (uint8_t); + +//***************************************************************************** +// +// This symbol forces simple driverlib functions to be inlined in the code +// instead of using function calls. +// +//***************************************************************************** +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +//***************************************************************************** +// +// C99 types only allows bitfield defintions on certain datatypes. +// +//***************************************************************************** +typedef unsigned int __UINT32; + +//***************************************************************************** +// +// Macros for direct hardware access. +// +// If using these macros the programmer should be aware of any limitations to +// the address accessed i.e. if it supports word and/or byte access. +// +//***************************************************************************** +// Word (32 bit) access to address x +// Read example : my32BitVar = HWREG(base_addr + offset) ; +// Write example : HWREG(base_addr + offset) = my32BitVar ; +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) + +// Half word (16 bit) access to address x +// Read example : my16BitVar = HWREGH(base_addr + offset) ; +// Write example : HWREGH(base_addr + offset) = my16BitVar ; +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) + +// Byte (8 bit) access to address x +// Read example : my8BitVar = HWREGB(base_addr + offset) ; +// Write example : HWREGB(base_addr + offset) = my8BitVar ; +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) + +//***************************************************************************** +// +// Macros for hardware access to bit-band supported addresses via the bit-band region. +// +// Macros calculate the corresponding address to access in the bit-band region +// based on the actual address of the memory/register and the bit number. +// +// Do NOT use these macros to access the bit-band region directly! +// +//***************************************************************************** +// Bit-band access to address x bit number b using word access (32 bit) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +// Bit-band access to address x bit number b using half word access (16 bit) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +// Bit-band access to address x bit number b using byte access (8 bit) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + + +#endif // __HW_TYPES_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_uart.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_uart.h new file mode 100644 index 0000000..05c49a7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_uart.h @@ -0,0 +1,1044 @@ +/****************************************************************************** +* Filename: hw_uart_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// UART component +// +//***************************************************************************** +// Data +#define UART_O_DR 0x00000000 + +// Status +#define UART_O_RSR 0x00000004 + +// Error Clear +#define UART_O_ECR 0x00000004 + +// Flag +#define UART_O_FR 0x00000018 + +// Integer Baud-Rate Divisor +#define UART_O_IBRD 0x00000024 + +// Fractional Baud-Rate Divisor +#define UART_O_FBRD 0x00000028 + +// Line Control +#define UART_O_LCRH 0x0000002C + +// Control +#define UART_O_CTL 0x00000030 + +// Interrupt FIFO Level Select +#define UART_O_IFLS 0x00000034 + +// Interrupt Mask Set/Clear +#define UART_O_IMSC 0x00000038 + +// Raw Interrupt Status +#define UART_O_RIS 0x0000003C + +// Masked Interrupt Status +#define UART_O_MIS 0x00000040 + +// Interrupt Clear +#define UART_O_ICR 0x00000044 + +// DMA Control +#define UART_O_DMACTL 0x00000048 + +//***************************************************************************** +// +// Register: UART_O_DR +// +//***************************************************************************** +// Field: [11] OE +// +// UART Overrun Error: +// This bit is set to 1 if data is received and the receive FIFO is already +// full. The FIFO contents remain valid because no more data is written when +// the FIFO is full, , only the contents of the shift register are overwritten. +// This is cleared to 0 once there is an empty space in the FIFO and a new +// character can be written to it. +#define UART_DR_OE 0x00000800 +#define UART_DR_OE_BITN 11 +#define UART_DR_OE_M 0x00000800 +#define UART_DR_OE_S 11 + +// Field: [10] BE +// +// UART Break Error: +// This bit is set to 1 if a break condition was detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (i.e., the oldest received data character since last read). When a +// break occurs, a 0 character is loaded into the FIFO. The next character is +// enabled after the receive data input (UARTRXD input pin) goes to a 1 +// (marking state), and the next valid start bit is received. +#define UART_DR_BE 0x00000400 +#define UART_DR_BE_BITN 10 +#define UART_DR_BE_M 0x00000400 +#define UART_DR_BE_S 10 + +// Field: [9] PE +// +// UART Parity Error: +// When set to 1, it indicates that the parity of the received data character +// does not match the parity that the LCRH.EPS and LCRH.SPS select. +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (i.e., the oldest received data character since last read). +#define UART_DR_PE 0x00000200 +#define UART_DR_PE_BITN 9 +#define UART_DR_PE_M 0x00000200 +#define UART_DR_PE_S 9 + +// Field: [8] FE +// +// UART Framing Error: +// When set to 1, it indicates that the received character did not have a valid +// stop bit (a valid stop bit is 1). +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (i.e., the oldest received data character since last read). +#define UART_DR_FE 0x00000100 +#define UART_DR_FE_BITN 8 +#define UART_DR_FE_M 0x00000100 +#define UART_DR_FE_S 8 + +// Field: [7:0] DATA +// +// Data transmitted or received: +// On writes, the transmit data character is pushed into the FIFO. +// On reads, the oldest received data character since the last read is +// returned. +#define UART_DR_DATA_W 8 +#define UART_DR_DATA_M 0x000000FF +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// Register: UART_O_RSR +// +//***************************************************************************** +// Field: [3] OE +// +// UART Overrun Error: +// This bit is set to 1 if data is received and the receive FIFO is already +// full. The FIFO contents remain valid because no more data is written when +// the FIFO is full, , only the contents of the shift register are overwritten. +// This is cleared to 0 once there is an empty space in the FIFO and a new +// character can be written to it. +#define UART_RSR_OE 0x00000008 +#define UART_RSR_OE_BITN 3 +#define UART_RSR_OE_M 0x00000008 +#define UART_RSR_OE_S 3 + +// Field: [2] BE +// +// UART Break Error: +// This bit is set to 1 if a break condition was detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +// When a break occurs, a 0 character is loaded into the FIFO. The next +// character is enabled after the receive data input (UARTRXD input pin) goes +// to a 1 (marking state), and the next valid start bit is received. +#define UART_RSR_BE 0x00000004 +#define UART_RSR_BE_BITN 2 +#define UART_RSR_BE_M 0x00000004 +#define UART_RSR_BE_S 2 + +// Field: [1] PE +// +// UART Parity Error: +// When set to 1, it indicates that the parity of the received data character +// does not match the parity that the LCRH.EPS and LCRH.SPS select. +#define UART_RSR_PE 0x00000002 +#define UART_RSR_PE_BITN 1 +#define UART_RSR_PE_M 0x00000002 +#define UART_RSR_PE_S 1 + +// Field: [0] FE +// +// UART Framing Error: +// When set to 1, it indicates that the received character did not have a valid +// stop bit (a valid stop bit is 1). +#define UART_RSR_FE 0x00000001 +#define UART_RSR_FE_BITN 0 +#define UART_RSR_FE_M 0x00000001 +#define UART_RSR_FE_S 0 + +//***************************************************************************** +// +// Register: UART_O_ECR +// +//***************************************************************************** +// Field: [3] OE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_OE 0x00000008 +#define UART_ECR_OE_BITN 3 +#define UART_ECR_OE_M 0x00000008 +#define UART_ECR_OE_S 3 + +// Field: [2] BE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_BE 0x00000004 +#define UART_ECR_BE_BITN 2 +#define UART_ECR_BE_M 0x00000004 +#define UART_ECR_BE_S 2 + +// Field: [1] PE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_PE 0x00000002 +#define UART_ECR_PE_BITN 1 +#define UART_ECR_PE_M 0x00000002 +#define UART_ECR_PE_S 1 + +// Field: [0] FE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_FE 0x00000001 +#define UART_ECR_FE_BITN 0 +#define UART_ECR_FE_M 0x00000001 +#define UART_ECR_FE_S 0 + +//***************************************************************************** +// +// Register: UART_O_FR +// +//***************************************************************************** +// Field: [7] TXFE +// +// UART Transmit FIFO Empty: +// The meaning of this bit depends on the state of LCRH.FEN . +// - If the FIFO is disabled, this bit is set when the transmit holding +// register is empty. +// - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. +// This bit does not indicate if there is data in the transmit shift register. +#define UART_FR_TXFE 0x00000080 +#define UART_FR_TXFE_BITN 7 +#define UART_FR_TXFE_M 0x00000080 +#define UART_FR_TXFE_S 7 + +// Field: [6] RXFF +// +// UART Receive FIFO Full: +// The meaning of this bit depends on the state of LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the receive holding +// register is full. +// - If the FIFO is enabled, this bit is set when the receive FIFO is full. +#define UART_FR_RXFF 0x00000040 +#define UART_FR_RXFF_BITN 6 +#define UART_FR_RXFF_M 0x00000040 +#define UART_FR_RXFF_S 6 + +// Field: [5] TXFF +// +// UART Transmit FIFO Full: +// Transmit FIFO full. The meaning of this bit depends on the state of +// LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the transmit holding +// register is full. +// - If the FIFO is enabled, this bit is set when the transmit FIFO is full. +#define UART_FR_TXFF 0x00000020 +#define UART_FR_TXFF_BITN 5 +#define UART_FR_TXFF_M 0x00000020 +#define UART_FR_TXFF_S 5 + +// Field: [4] RXFE +// +// UART Receive FIFO Empty: +// Receive FIFO empty. The meaning of this bit depends on the state of +// LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the receive holding +// register is empty. +// - If the FIFO is enabled, this bit is set when the receive FIFO is empty. +#define UART_FR_RXFE 0x00000010 +#define UART_FR_RXFE_BITN 4 +#define UART_FR_RXFE_M 0x00000010 +#define UART_FR_RXFE_S 4 + +// Field: [3] BUSY +// +// UART Busy: +// If this bit is set to 1, the UART is busy transmitting data. This bit +// remains set until the complete byte, including all the stop bits, has been +// sent from the shift register. +// This bit is set as soon as the transmit FIFO becomes non-empty, regardless +// of whether the UART is enabled or not. +#define UART_FR_BUSY 0x00000008 +#define UART_FR_BUSY_BITN 3 +#define UART_FR_BUSY_M 0x00000008 +#define UART_FR_BUSY_S 3 + +// Field: [0] CTS +// +// Clear To Send: +// This bit is the complement of the active-low UART CTS input pin. +// That is, the bit is 1 when CTS input pin is LOW. +#define UART_FR_CTS 0x00000001 +#define UART_FR_CTS_BITN 0 +#define UART_FR_CTS_M 0x00000001 +#define UART_FR_CTS_S 0 + +//***************************************************************************** +// +// Register: UART_O_IBRD +// +//***************************************************************************** +// Field: [15:0] DIVINT +// +// The integer baud rate divisor: +// The baud rate divisor is calculated using the formula below: +// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) +// Baud rate divisor must be minimum 1 and maximum 65535. +// That is, DIVINT=0 does not give a valid baud rate. +// Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be +// illegal. +// A valid value must be written to this field before the UART can be used for +// RX or TX operations. +#define UART_IBRD_DIVINT_W 16 +#define UART_IBRD_DIVINT_M 0x0000FFFF +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// Register: UART_O_FBRD +// +//***************************************************************************** +// Field: [5:0] DIVFRAC +// +// Fractional Baud-Rate Divisor: +// The baud rate divisor is calculated using the formula below: +// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) +// Baud rate divisor must be minimum 1 and maximum 65535. +// That is, IBRD.DIVINT=0 does not give a valid baud rate. +// Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be +// illegal. +// A valid value must be written to this field before the UART can be used for +// RX or TX operations. +#define UART_FBRD_DIVFRAC_W 6 +#define UART_FBRD_DIVFRAC_M 0x0000003F +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// Register: UART_O_LCRH +// +//***************************************************************************** +// Field: [7] SPS +// +// UART Stick Parity Select: +// +// 0: Stick parity is disabled +// 1: The parity bit is transmitted and checked as invert of EPS field (i.e. +// the parity bit is transmitted and checked as 1 when EPS = 0). +// +// This bit has no effect when PEN disables parity checking and generation. +#define UART_LCRH_SPS 0x00000080 +#define UART_LCRH_SPS_BITN 7 +#define UART_LCRH_SPS_M 0x00000080 +#define UART_LCRH_SPS_S 7 + +// Field: [6:5] WLEN +// +// UART Word Length: +// These bits indicate the number of data bits transmitted or received in a +// frame. +// ENUMs: +// 8 Word Length 8 bits +// 7 Word Length 7 bits +// 6 Word Length 6 bits +// 5 Word Length 5 bits +#define UART_LCRH_WLEN_W 2 +#define UART_LCRH_WLEN_M 0x00000060 +#define UART_LCRH_WLEN_S 5 +#define UART_LCRH_WLEN_8 0x00000060 +#define UART_LCRH_WLEN_7 0x00000040 +#define UART_LCRH_WLEN_6 0x00000020 +#define UART_LCRH_WLEN_5 0x00000000 + +// Field: [4] FEN +// +// UART Enable FIFOs +// ENUMs: +// EN Transmit and receive FIFO buffers are enabled +// (FIFO mode) +// DIS FIFOs are disabled (character mode) that is, the +// FIFOs become 1-byte-deep holding registers. +#define UART_LCRH_FEN 0x00000010 +#define UART_LCRH_FEN_BITN 4 +#define UART_LCRH_FEN_M 0x00000010 +#define UART_LCRH_FEN_S 4 +#define UART_LCRH_FEN_EN 0x00000010 +#define UART_LCRH_FEN_DIS 0x00000000 + +// Field: [3] STP2 +// +// UART Two Stop Bits Select: +// If this bit is set to 1, two stop bits are transmitted at the end of the +// frame. The receive logic does not check for two stop bits being received. +#define UART_LCRH_STP2 0x00000008 +#define UART_LCRH_STP2_BITN 3 +#define UART_LCRH_STP2_M 0x00000008 +#define UART_LCRH_STP2_S 3 + +// Field: [2] EPS +// +// UART Even Parity Select +// ENUMs: +// EVEN Even parity: The UART generates or checks for an +// even number of 1s in the data and parity bits. +// ODD Odd parity: The UART generates or checks for an +// odd number of 1s in the data and parity bits. +#define UART_LCRH_EPS 0x00000004 +#define UART_LCRH_EPS_BITN 2 +#define UART_LCRH_EPS_M 0x00000004 +#define UART_LCRH_EPS_S 2 +#define UART_LCRH_EPS_EVEN 0x00000004 +#define UART_LCRH_EPS_ODD 0x00000000 + +// Field: [1] PEN +// +// UART Parity Enable +// This bit controls generation and checking of parity bit. +// ENUMs: +// EN Parity checking and generation is enabled. +// DIS Parity is disabled and no parity bit is added to +// the data frame +#define UART_LCRH_PEN 0x00000002 +#define UART_LCRH_PEN_BITN 1 +#define UART_LCRH_PEN_M 0x00000002 +#define UART_LCRH_PEN_S 1 +#define UART_LCRH_PEN_EN 0x00000002 +#define UART_LCRH_PEN_DIS 0x00000000 + +// Field: [0] BRK +// +// UART Send Break +// If this bit is set to 1, a low-level is continually output on the UARTTXD +// output pin, after completing transmission of the current character. For the +// proper execution of the break command, the +// software must set this bit for at least two complete frames. For normal use, +// this bit must be cleared to 0. +#define UART_LCRH_BRK 0x00000001 +#define UART_LCRH_BRK_BITN 0 +#define UART_LCRH_BRK_M 0x00000001 +#define UART_LCRH_BRK_S 0 + +//***************************************************************************** +// +// Register: UART_O_CTL +// +//***************************************************************************** +// Field: [15] CTSEN +// +// CTS hardware flow control enable +// ENUMs: +// EN CTS hardware flow control enabled +// DIS CTS hardware flow control disabled +#define UART_CTL_CTSEN 0x00008000 +#define UART_CTL_CTSEN_BITN 15 +#define UART_CTL_CTSEN_M 0x00008000 +#define UART_CTL_CTSEN_S 15 +#define UART_CTL_CTSEN_EN 0x00008000 +#define UART_CTL_CTSEN_DIS 0x00000000 + +// Field: [14] RTSEN +// +// RTS hardware flow control enable +// ENUMs: +// EN RTS hardware flow control enabled +// DIS RTS hardware flow control disabled +#define UART_CTL_RTSEN 0x00004000 +#define UART_CTL_RTSEN_BITN 14 +#define UART_CTL_RTSEN_M 0x00004000 +#define UART_CTL_RTSEN_S 14 +#define UART_CTL_RTSEN_EN 0x00004000 +#define UART_CTL_RTSEN_DIS 0x00000000 + +// Field: [11] RTS +// +// Request to Send +// This bit is the complement of the active-low UART RTS output. That is, when +// the bit is programmed to a 1 then RTS output on the pins is LOW. +#define UART_CTL_RTS 0x00000800 +#define UART_CTL_RTS_BITN 11 +#define UART_CTL_RTS_M 0x00000800 +#define UART_CTL_RTS_S 11 + +// Field: [9] RXE +// +// UART Receive Enable +// If the UART is disabled in the middle of reception, it completes the current +// character before stopping. +// ENUMs: +// EN UART Receive enabled +// DIS UART Receive disabled +#define UART_CTL_RXE 0x00000200 +#define UART_CTL_RXE_BITN 9 +#define UART_CTL_RXE_M 0x00000200 +#define UART_CTL_RXE_S 9 +#define UART_CTL_RXE_EN 0x00000200 +#define UART_CTL_RXE_DIS 0x00000000 + +// Field: [8] TXE +// +// UART Transmit Enable +// If the UART is disabled in the middle of transmission, it completes the +// current character before stopping. +// ENUMs: +// EN UART Transmit enabled +// DIS UART Transmit disabled +#define UART_CTL_TXE 0x00000100 +#define UART_CTL_TXE_BITN 8 +#define UART_CTL_TXE_M 0x00000100 +#define UART_CTL_TXE_S 8 +#define UART_CTL_TXE_EN 0x00000100 +#define UART_CTL_TXE_DIS 0x00000000 + +// Field: [7] LBE +// +// UART Loop Back Enable: +// Enabling the loop-back mode connects the UARTTXD output from the UART to +// UARTRXD input of the UART. +// ENUMs: +// EN Loop Back enabled +// DIS Loop Back disabled +#define UART_CTL_LBE 0x00000080 +#define UART_CTL_LBE_BITN 7 +#define UART_CTL_LBE_M 0x00000080 +#define UART_CTL_LBE_S 7 +#define UART_CTL_LBE_EN 0x00000080 +#define UART_CTL_LBE_DIS 0x00000000 + +// Field: [0] UARTEN +// +// UART Enable +// ENUMs: +// EN UART enabled +// DIS UART disabled +#define UART_CTL_UARTEN 0x00000001 +#define UART_CTL_UARTEN_BITN 0 +#define UART_CTL_UARTEN_M 0x00000001 +#define UART_CTL_UARTEN_S 0 +#define UART_CTL_UARTEN_EN 0x00000001 +#define UART_CTL_UARTEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: UART_O_IFLS +// +//***************************************************************************** +// Field: [5:3] RXSEL +// +// Receive interrupt FIFO level select: +// This field sets the trigger points for the receive interrupt. Values +// 0b101-0b111 are reserved. +// ENUMs: +// 7_8 Receive FIFO becomes >= 7/8 full +// 6_8 Receive FIFO becomes >= 3/4 full +// 4_8 Receive FIFO becomes >= 1/2 full +// 2_8 Receive FIFO becomes >= 1/4 full +// 1_8 Receive FIFO becomes >= 1/8 full +#define UART_IFLS_RXSEL_W 3 +#define UART_IFLS_RXSEL_M 0x00000038 +#define UART_IFLS_RXSEL_S 3 +#define UART_IFLS_RXSEL_7_8 0x00000020 +#define UART_IFLS_RXSEL_6_8 0x00000018 +#define UART_IFLS_RXSEL_4_8 0x00000010 +#define UART_IFLS_RXSEL_2_8 0x00000008 +#define UART_IFLS_RXSEL_1_8 0x00000000 + +// Field: [2:0] TXSEL +// +// Transmit interrupt FIFO level select: +// This field sets the trigger points for the transmit interrupt. Values +// 0b101-0b111 are reserved. +// ENUMs: +// 7_8 Transmit FIFO becomes <= 7/8 full +// 6_8 Transmit FIFO becomes <= 3/4 full +// 4_8 Transmit FIFO becomes <= 1/2 full +// 2_8 Transmit FIFO becomes <= 1/4 full +// 1_8 Transmit FIFO becomes <= 1/8 full +#define UART_IFLS_TXSEL_W 3 +#define UART_IFLS_TXSEL_M 0x00000007 +#define UART_IFLS_TXSEL_S 0 +#define UART_IFLS_TXSEL_7_8 0x00000004 +#define UART_IFLS_TXSEL_6_8 0x00000003 +#define UART_IFLS_TXSEL_4_8 0x00000002 +#define UART_IFLS_TXSEL_2_8 0x00000001 +#define UART_IFLS_TXSEL_1_8 0x00000000 + +//***************************************************************************** +// +// Register: UART_O_IMSC +// +//***************************************************************************** +// Field: [10] OEIM +// +// Overrun error interrupt mask. A read returns the current mask for UART's +// overrun error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not +// reflect the interrupt. +#define UART_IMSC_OEIM 0x00000400 +#define UART_IMSC_OEIM_BITN 10 +#define UART_IMSC_OEIM_M 0x00000400 +#define UART_IMSC_OEIM_S 10 + +// Field: [9] BEIM +// +// Break error interrupt mask. A read returns the current mask for UART's break +// error interrupt. On a write of 1, the mask of the overrun error interrupt is +// set which means the interrupt state will be reflected in MIS.BEMIS. A write +// of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. +#define UART_IMSC_BEIM 0x00000200 +#define UART_IMSC_BEIM_BITN 9 +#define UART_IMSC_BEIM_M 0x00000200 +#define UART_IMSC_BEIM_S 9 + +// Field: [8] PEIM +// +// Parity error interrupt mask. A read returns the current mask for UART's +// parity error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not +// reflect the interrupt. +#define UART_IMSC_PEIM 0x00000100 +#define UART_IMSC_PEIM_BITN 8 +#define UART_IMSC_PEIM_M 0x00000100 +#define UART_IMSC_PEIM_S 8 + +// Field: [7] FEIM +// +// Framing error interrupt mask. A read returns the current mask for UART's +// framing error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not +// reflect the interrupt. +#define UART_IMSC_FEIM 0x00000080 +#define UART_IMSC_FEIM_BITN 7 +#define UART_IMSC_FEIM_M 0x00000080 +#define UART_IMSC_FEIM_S 7 + +// Field: [6] RTIM +// +// Receive timeout interrupt mask. A read returns the current mask for UART's +// receive timeout interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not +// reflect the interrupt. +// The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the +// mask is set (RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. +#define UART_IMSC_RTIM 0x00000040 +#define UART_IMSC_RTIM_BITN 6 +#define UART_IMSC_RTIM_M 0x00000040 +#define UART_IMSC_RTIM_S 6 + +// Field: [5] TXIM +// +// Transmit interrupt mask. A read returns the current mask for UART's transmit +// interrupt. On a write of 1, the mask of the overrun error interrupt is set +// which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 +// clears the mask which means MIS.TXMIS will not reflect the interrupt. +#define UART_IMSC_TXIM 0x00000020 +#define UART_IMSC_TXIM_BITN 5 +#define UART_IMSC_TXIM_M 0x00000020 +#define UART_IMSC_TXIM_S 5 + +// Field: [4] RXIM +// +// Receive interrupt mask. A read returns the current mask for UART's receive +// interrupt. On a write of 1, the mask of the overrun error interrupt is set +// which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 +// clears the mask which means MIS.RXMIS will not reflect the interrupt. +#define UART_IMSC_RXIM 0x00000010 +#define UART_IMSC_RXIM_BITN 4 +#define UART_IMSC_RXIM_M 0x00000010 +#define UART_IMSC_RXIM_S 4 + +// Field: [1] CTSMIM +// +// Clear to Send (CTS) modem interrupt mask. A read returns the current mask +// for UART's clear to send interrupt. On a write of 1, the mask of the overrun +// error interrupt is set which means the interrupt state will be reflected in +// MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not +// reflect the interrupt. +#define UART_IMSC_CTSMIM 0x00000002 +#define UART_IMSC_CTSMIM_BITN 1 +#define UART_IMSC_CTSMIM_M 0x00000002 +#define UART_IMSC_CTSMIM_S 1 + +//***************************************************************************** +// +// Register: UART_O_RIS +// +//***************************************************************************** +// Field: [10] OERIS +// +// Overrun error interrupt status: +// This field returns the raw interrupt state of UART's overrun error +// interrupt. Overrun error occurs if data is received and the receive FIFO is +// full. +#define UART_RIS_OERIS 0x00000400 +#define UART_RIS_OERIS_BITN 10 +#define UART_RIS_OERIS_M 0x00000400 +#define UART_RIS_OERIS_S 10 + +// Field: [9] BERIS +// +// Break error interrupt status: +// This field returns the raw interrupt state of UART's break error interrupt. +// Break error is set when a break condition is detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +#define UART_RIS_BERIS 0x00000200 +#define UART_RIS_BERIS_BITN 9 +#define UART_RIS_BERIS_M 0x00000200 +#define UART_RIS_BERIS_S 9 + +// Field: [8] PERIS +// +// Parity error interrupt status: +// This field returns the raw interrupt state of UART's parity error interrupt. +// Parity error is set if the parity of the received data character does not +// match the parity that the LCRH.EPS and LCRH.SPS select. +#define UART_RIS_PERIS 0x00000100 +#define UART_RIS_PERIS_BITN 8 +#define UART_RIS_PERIS_M 0x00000100 +#define UART_RIS_PERIS_S 8 + +// Field: [7] FERIS +// +// Framing error interrupt status: +// This field returns the raw interrupt state of UART's framing error +// interrupt. Framing error is set if the received character does not have a +// valid stop bit (a valid stop bit is 1). +#define UART_RIS_FERIS 0x00000080 +#define UART_RIS_FERIS_BITN 7 +#define UART_RIS_FERIS_M 0x00000080 +#define UART_RIS_FERIS_S 7 + +// Field: [6] RTRIS +// +// Receive timeout interrupt status: +// This field returns the raw interrupt state of UART's receive timeout +// interrupt. The receive timeout interrupt is asserted when the receive FIFO +// is not empty, and no more data is received during a 32-bit period. The +// receive timeout interrupt is cleared either when the FIFO becomes empty +// through reading all the data, or when a 1 is written to ICR.RTIC. +// The raw interrupt for receive timeout cannot be set unless the mask is set +// (IMSC.RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from MIS.RTMIS and RTRIS. +#define UART_RIS_RTRIS 0x00000040 +#define UART_RIS_RTRIS_BITN 6 +#define UART_RIS_RTRIS_M 0x00000040 +#define UART_RIS_RTRIS_S 6 + +// Field: [5] TXRIS +// +// Transmit interrupt status: +// This field returns the raw interrupt state of UART's transmit interrupt. +// When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if +// the number of bytes in transmit FIFO is equal to or lower than the +// programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by +// writing data to the transmit FIFO until it becomes greater than the trigger +// level, or by clearing the interrupt through ICR.TXIC. +// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one +// location, the transmit interrupt is asserted if there is no data present in +// the transmitters single location. It is cleared by performing a single write +// to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. +#define UART_RIS_TXRIS 0x00000020 +#define UART_RIS_TXRIS_BITN 5 +#define UART_RIS_TXRIS_M 0x00000020 +#define UART_RIS_TXRIS_S 5 + +// Field: [4] RXRIS +// +// Receive interrupt status: +// This field returns the raw interrupt state of UART's receive interrupt. +// When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if +// the receive FIFO reaches the programmed trigger +// level (IFLS.RXSEL). The receive interrupt is cleared by reading data from +// the receive FIFO until it becomes less than the trigger level, or by +// clearing the interrupt through ICR.RXIC. +// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one +// location, the receive interrupt is asserted if data is received +// thereby filling the location. The receive interrupt is cleared by performing +// a single read of the receive FIFO, or by clearing the interrupt through +// ICR.RXIC. +#define UART_RIS_RXRIS 0x00000010 +#define UART_RIS_RXRIS_BITN 4 +#define UART_RIS_RXRIS_M 0x00000010 +#define UART_RIS_RXRIS_S 4 + +// Field: [1] CTSRMIS +// +// Clear to Send (CTS) modem interrupt status: +// This field returns the raw interrupt state of UART's clear to send +// interrupt. +#define UART_RIS_CTSRMIS 0x00000002 +#define UART_RIS_CTSRMIS_BITN 1 +#define UART_RIS_CTSRMIS_M 0x00000002 +#define UART_RIS_CTSRMIS_S 1 + +//***************************************************************************** +// +// Register: UART_O_MIS +// +//***************************************************************************** +// Field: [10] OEMIS +// +// Overrun error masked interrupt status: +// This field returns the masked interrupt state of the overrun interrupt which +// is the AND product of raw interrupt state RIS.OERIS and the mask setting +// IMSC.OEIM. +#define UART_MIS_OEMIS 0x00000400 +#define UART_MIS_OEMIS_BITN 10 +#define UART_MIS_OEMIS_M 0x00000400 +#define UART_MIS_OEMIS_S 10 + +// Field: [9] BEMIS +// +// Break error masked interrupt status: +// This field returns the masked interrupt state of the break error interrupt +// which is the AND product of raw interrupt state RIS.BERIS and the mask +// setting IMSC.BEIM. +#define UART_MIS_BEMIS 0x00000200 +#define UART_MIS_BEMIS_BITN 9 +#define UART_MIS_BEMIS_M 0x00000200 +#define UART_MIS_BEMIS_S 9 + +// Field: [8] PEMIS +// +// Parity error masked interrupt status: +// This field returns the masked interrupt state of the parity error interrupt +// which is the AND product of raw interrupt state RIS.PERIS and the mask +// setting IMSC.PEIM. +#define UART_MIS_PEMIS 0x00000100 +#define UART_MIS_PEMIS_BITN 8 +#define UART_MIS_PEMIS_M 0x00000100 +#define UART_MIS_PEMIS_S 8 + +// Field: [7] FEMIS +// +// Framing error masked interrupt status: Returns the masked interrupt state of +// the framing error interrupt which is the AND product of raw interrupt state +// RIS.FERIS and the mask setting IMSC.FEIM. +#define UART_MIS_FEMIS 0x00000080 +#define UART_MIS_FEMIS_BITN 7 +#define UART_MIS_FEMIS_M 0x00000080 +#define UART_MIS_FEMIS_S 7 + +// Field: [6] RTMIS +// +// Receive timeout masked interrupt status: +// Returns the masked interrupt state of the receive timeout interrupt. +// The raw interrupt for receive timeout cannot be set unless the mask is set +// (IMSC.RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from RTMIS and RIS.RTRIS. +#define UART_MIS_RTMIS 0x00000040 +#define UART_MIS_RTMIS_BITN 6 +#define UART_MIS_RTMIS_M 0x00000040 +#define UART_MIS_RTMIS_S 6 + +// Field: [5] TXMIS +// +// Transmit masked interrupt status: +// This field returns the masked interrupt state of the transmit interrupt +// which is the AND product of raw interrupt state RIS.TXRIS and the mask +// setting IMSC.TXIM. +#define UART_MIS_TXMIS 0x00000020 +#define UART_MIS_TXMIS_BITN 5 +#define UART_MIS_TXMIS_M 0x00000020 +#define UART_MIS_TXMIS_S 5 + +// Field: [4] RXMIS +// +// Receive masked interrupt status: +// This field returns the masked interrupt state of the receive interrupt +// which is the AND product of raw interrupt state RIS.RXRIS and the mask +// setting IMSC.RXIM. +#define UART_MIS_RXMIS 0x00000010 +#define UART_MIS_RXMIS_BITN 4 +#define UART_MIS_RXMIS_M 0x00000010 +#define UART_MIS_RXMIS_S 4 + +// Field: [1] CTSMMIS +// +// Clear to Send (CTS) modem masked interrupt status: +// This field returns the masked interrupt state of the clear to send interrupt +// which is the AND product of raw interrupt state RIS.CTSRMIS and the mask +// setting IMSC.CTSMIM. +#define UART_MIS_CTSMMIS 0x00000002 +#define UART_MIS_CTSMMIS_BITN 1 +#define UART_MIS_CTSMMIS_M 0x00000002 +#define UART_MIS_CTSMMIS_S 1 + +//***************************************************************************** +// +// Register: UART_O_ICR +// +//***************************************************************************** +// Field: [10] OEIC +// +// Overrun error interrupt clear: +// Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). +// Writing 0 has no effect. +#define UART_ICR_OEIC 0x00000400 +#define UART_ICR_OEIC_BITN 10 +#define UART_ICR_OEIC_M 0x00000400 +#define UART_ICR_OEIC_S 10 + +// Field: [9] BEIC +// +// Break error interrupt clear: +// Writing 1 to this field clears the break error interrupt (RIS.BERIS). +// Writing 0 has no effect. +#define UART_ICR_BEIC 0x00000200 +#define UART_ICR_BEIC_BITN 9 +#define UART_ICR_BEIC_M 0x00000200 +#define UART_ICR_BEIC_S 9 + +// Field: [8] PEIC +// +// Parity error interrupt clear: +// Writing 1 to this field clears the parity error interrupt (RIS.PERIS). +// Writing 0 has no effect. +#define UART_ICR_PEIC 0x00000100 +#define UART_ICR_PEIC_BITN 8 +#define UART_ICR_PEIC_M 0x00000100 +#define UART_ICR_PEIC_S 8 + +// Field: [7] FEIC +// +// Framing error interrupt clear: +// Writing 1 to this field clears the framing error interrupt (RIS.FERIS). +// Writing 0 has no effect. +#define UART_ICR_FEIC 0x00000080 +#define UART_ICR_FEIC_BITN 7 +#define UART_ICR_FEIC_M 0x00000080 +#define UART_ICR_FEIC_S 7 + +// Field: [6] RTIC +// +// Receive timeout interrupt clear: +// Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). +// Writing 0 has no effect. +#define UART_ICR_RTIC 0x00000040 +#define UART_ICR_RTIC_BITN 6 +#define UART_ICR_RTIC_M 0x00000040 +#define UART_ICR_RTIC_S 6 + +// Field: [5] TXIC +// +// Transmit interrupt clear: +// Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 +// has no effect. +#define UART_ICR_TXIC 0x00000020 +#define UART_ICR_TXIC_BITN 5 +#define UART_ICR_TXIC_M 0x00000020 +#define UART_ICR_TXIC_S 5 + +// Field: [4] RXIC +// +// Receive interrupt clear: +// Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 +// has no effect. +#define UART_ICR_RXIC 0x00000010 +#define UART_ICR_RXIC_BITN 4 +#define UART_ICR_RXIC_M 0x00000010 +#define UART_ICR_RXIC_S 4 + +// Field: [1] CTSMIC +// +// Clear to Send (CTS) modem interrupt clear: +// Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). +// Writing 0 has no effect. +#define UART_ICR_CTSMIC 0x00000002 +#define UART_ICR_CTSMIC_BITN 1 +#define UART_ICR_CTSMIC_M 0x00000002 +#define UART_ICR_CTSMIC_S 1 + +//***************************************************************************** +// +// Register: UART_O_DMACTL +// +//***************************************************************************** +// Field: [2] DMAONERR +// +// DMA on error. If this bit is set to 1, the DMA receive request outputs (for +// single and burst requests) are disabled when the UART error interrupt is +// asserted (more specifically if any of the error interrupts RIS.PERIS, +// RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). +#define UART_DMACTL_DMAONERR 0x00000004 +#define UART_DMACTL_DMAONERR_BITN 2 +#define UART_DMACTL_DMAONERR_M 0x00000004 +#define UART_DMACTL_DMAONERR_S 2 + +// Field: [1] TXDMAE +// +// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is +// enabled. +#define UART_DMACTL_TXDMAE 0x00000002 +#define UART_DMACTL_TXDMAE_BITN 1 +#define UART_DMACTL_TXDMAE_M 0x00000002 +#define UART_DMACTL_TXDMAE_S 1 + +// Field: [0] RXDMAE +// +// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is +// enabled. +#define UART_DMACTL_RXDMAE 0x00000001 +#define UART_DMACTL_RXDMAE_BITN 0 +#define UART_DMACTL_RXDMAE_M 0x00000001 +#define UART_DMACTL_RXDMAE_S 0 + + +#endif // __UART__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_udma.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_udma.h new file mode 100644 index 0000000..63d0a54 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_udma.h @@ -0,0 +1,575 @@ +/****************************************************************************** +* Filename: hw_udma_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_UDMA_H__ +#define __HW_UDMA_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// UDMA component +// +//***************************************************************************** +// Status +#define UDMA_O_STATUS 0x00000000 + +// Configuration +#define UDMA_O_CFG 0x00000004 + +// Channel Control Data Base Pointer +#define UDMA_O_CTRL 0x00000008 + +// Channel Alternate Control Data Base Pointer +#define UDMA_O_ALTCTRL 0x0000000C + +// Channel Wait On Request Status +#define UDMA_O_WAITONREQ 0x00000010 + +// Channel Software Request +#define UDMA_O_SOFTREQ 0x00000014 + +// Channel Set UseBurst +#define UDMA_O_SETBURST 0x00000018 + +// Channel Clear UseBurst +#define UDMA_O_CLEARBURST 0x0000001C + +// Channel Set Request Mask +#define UDMA_O_SETREQMASK 0x00000020 + +// Clear Channel Request Mask +#define UDMA_O_CLEARREQMASK 0x00000024 + +// Set Channel Enable +#define UDMA_O_SETCHANNELEN 0x00000028 + +// Clear Channel Enable +#define UDMA_O_CLEARCHANNELEN 0x0000002C + +// Channel Set Primary-Alternate +#define UDMA_O_SETCHNLPRIALT 0x00000030 + +// Channel Clear Primary-Alternate +#define UDMA_O_CLEARCHNLPRIALT 0x00000034 + +// Set Channel Priority +#define UDMA_O_SETCHNLPRIORITY 0x00000038 + +// Clear Channel Priority +#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C + +// Error Status and Clear +#define UDMA_O_ERROR 0x0000004C + +// Channel Request Done +#define UDMA_O_REQDONE 0x00000504 + +// Channel Request Done Mask +#define UDMA_O_DONEMASK 0x00000520 + +//***************************************************************************** +// +// Register: UDMA_O_STATUS +// +//***************************************************************************** +// Field: [31:28] TEST +// +// +// 0x0: Controller does not include the integration test logic +// 0x1: Controller includes the integration test logic +// 0x2: Undefined +// ... +// 0xF: Undefined +#define UDMA_STATUS_TEST_W 4 +#define UDMA_STATUS_TEST_M 0xF0000000 +#define UDMA_STATUS_TEST_S 28 + +// Field: [20:16] TOTALCHANNELS +// +// Register value returns number of available uDMA channels minus one. For +// example a read out value of: +// +// 0x00: Show that the controller is configured to use 1 uDMA channel +// 0x01: Shows that the controller is configured to use 2 uDMA channels +// ... +// 0x1F: Shows that the controller is configured to use 32 uDMA channels +// (32-1=31=0x1F) +#define UDMA_STATUS_TOTALCHANNELS_W 5 +#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 +#define UDMA_STATUS_TOTALCHANNELS_S 16 + +// Field: [7:4] STATE +// +// Current state of the control state machine. State can be one of the +// following: +// +// 0x0: Idle +// 0x1: Reading channel controller data +// 0x2: Reading source data end pointer +// 0x3: Reading destination data end pointer +// 0x4: Reading source data +// 0x5: Writing destination data +// 0x6: Waiting for uDMA request to clear +// 0x7: Writing channel controller data +// 0x8: Stalled +// 0x9: Done +// 0xA: Peripheral scatter-gather transition +// 0xB: Undefined +// ... +// 0xF: Undefined. +#define UDMA_STATUS_STATE_W 4 +#define UDMA_STATUS_STATE_M 0x000000F0 +#define UDMA_STATUS_STATE_S 4 + +// Field: [0] MASTERENABLE +// +// Shows the enable status of the controller as configured by CFG.MASTERENABLE: +// +// 0: Controller is disabled +// 1: Controller is enabled +#define UDMA_STATUS_MASTERENABLE 0x00000001 +#define UDMA_STATUS_MASTERENABLE_BITN 0 +#define UDMA_STATUS_MASTERENABLE_M 0x00000001 +#define UDMA_STATUS_MASTERENABLE_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CFG +// +//***************************************************************************** +// Field: [7:5] PRTOCTRL +// +// Sets the AHB-Lite bus protocol protection state by controlling the AHB +// signal HProt[3:1] as follows: +// +// Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring. +// Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring. +// Bit [5] Controls HProt[1] to indicate if a privileged access is occurring. +// +// When bit [n] = 1 then the corresponding HProt bit is high. +// When bit [n] = 0 then the corresponding HProt bit is low. +// +// This field controls HProt[3:1] signal for all transactions initiated by uDMA +// except two transactions below: +// - the read from the address indicated by source address pointer +// - the write to the address indicated by destination address pointer +// HProt[3:1] for these two exceptions can be controlled by dedicated fields in +// the channel configutation descriptor. +#define UDMA_CFG_PRTOCTRL_W 3 +#define UDMA_CFG_PRTOCTRL_M 0x000000E0 +#define UDMA_CFG_PRTOCTRL_S 5 + +// Field: [0] MASTERENABLE +// +// Enables the controller: +// +// 0: Disables the controller +// 1: Enables the controller +#define UDMA_CFG_MASTERENABLE 0x00000001 +#define UDMA_CFG_MASTERENABLE_BITN 0 +#define UDMA_CFG_MASTERENABLE_M 0x00000001 +#define UDMA_CFG_MASTERENABLE_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CTRL +// +//***************************************************************************** +// Field: [31:10] BASEPTR +// +// This register point to the base address for the primary data structures of +// each DMA channel. This is not stored in module, but in system memory, thus +// space must be allocated for this usage when DMA is in usage +#define UDMA_CTRL_BASEPTR_W 22 +#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 +#define UDMA_CTRL_BASEPTR_S 10 + +//***************************************************************************** +// +// Register: UDMA_O_ALTCTRL +// +//***************************************************************************** +// Field: [31:0] BASEPTR +// +// This register shows the base address for the alternate data structures and +// is calculated by module, thus read only +#define UDMA_ALTCTRL_BASEPTR_W 32 +#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF +#define UDMA_ALTCTRL_BASEPTR_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_WAITONREQ +// +//***************************************************************************** +// Field: [31:0] CHNLSTATUS +// +// Channel wait on request status: +// +// Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, +// this channel may come out of active state even if request is still present. +// Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it +// keeps channel Ch in active state until the requests are deasserted. This +// handshake is necessary for channels where the requester is in an +// asynchronous domain or can run at slower clock speed than uDMA +#define UDMA_WAITONREQ_CHNLSTATUS_W 32 +#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF +#define UDMA_WAITONREQ_CHNLSTATUS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SOFTREQ +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to generate a software uDMA request on the +// corresponding uDMA channel +// +// Bit [Ch] = 0: Does not create a uDMA request for channel Ch +// Bit [Ch] = 1: Creates a uDMA request for channel Ch +// +// Writing to a bit where a uDMA channel is not implemented does not create a +// uDMA request for that channel +#define UDMA_SOFTREQ_CHNLS_W 32 +#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF +#define UDMA_SOFTREQ_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETBURST +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the useburst status, or disables individual channels from generating +// single uDMA requests. The value R is the arbitration rate and stored in the +// controller data structure. +// +// Read as: +// +// Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on +// channel C. The controller performs 2^R, or single, bus transfers. +// +// Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. +// The controller only responds to burst transfer requests and performs 2^R +// transfers. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0. +// Bit [Ch] = 1: Disables single transfer requests on channel Ch. The +// controller performs 2^R transfers for burst requests. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETBURST_CHNLS_W 32 +#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_SETBURST_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARBURST +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to enable single transfer requests. +// +// Write as: +// +// Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer +// requests. +// +// Bit [Ch] = 1: Enables single transfer requests on channel Ch. +// +// Writing to a bit where a DMA channel is not implemented has no effect. +#define UDMA_CLEARBURST_CHNLS_W 32 +#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARBURST_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETREQMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the burst and single request mask status, or disables the +// corresponding channel from generating uDMA requests. +// +// Read as: +// Bit [Ch] = 0: External requests are enabled for channel Ch. +// Bit [Ch] = 1: External requests are disabled for channel Ch. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests. +// Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA single +// request channel [C] input from generating uDMA requests. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETREQMASK_CHNLS_W 32 +#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_SETREQMASK_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARREQMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to enable DMA request for the channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel C from +// generating requests. +// Bit [Ch] = 1: Enables channel [C] to generate DMA requests. +// +// Writing to a bit where a DMA channel is not implemented has no effect. +#define UDMA_CLEARREQMASK_CHNLS_W 32 +#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARREQMASK_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHANNELEN +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the enable status of the channels, or enables the corresponding +// channels. +// +// Read as: +// Bit [Ch] = 0: Channel Ch is disabled. +// Bit [Ch] = 1: Channel Ch is enabled. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel +// Bit [Ch] = 1: Enables channel Ch +// +// Writing to a bit where a DMA channel is not implemented has no effect +#define UDMA_SETCHANNELEN_CHNLS_W 32 +#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHANNELEN_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHANNELEN +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to disable the corresponding uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels. +// Bit [Ch] = 1: Disables channel Ch +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHANNELEN_CHNLS_W 32 +#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHANNELEN_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHNLPRIALT +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the channel control data structure status, or selects the alternate +// data structure for the corresponding uDMA channel. +// +// Read as: +// Bit [Ch] = 0: uDMA channel Ch is using the primary data structure. +// Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel +// Bit [Ch] = 1: Selects the alternate data structure for channel Ch +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETCHNLPRIALT_CHNLS_W 32 +#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIALT_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHNLPRIALT +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Clears the appropriate bit to select the primary data structure for the +// corresponding uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate +// data structure. +// Bit [Ch] = 1: Selects the primary data structure for channel Ch. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHNLPRIORITY +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the channel priority mask status, or sets the channel priority to +// high. +// +// Read as: +// Bit [Ch] = 0: uDMA channel Ch is using the default priority level. +// Bit [Ch] = 1: uDMA channel Ch is using a high priority level. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch +// to the default priority level. +// Bit [Ch] = 1: Channel Ch uses the high priority level. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETCHNLPRIORITY_CHNLS_W 32 +#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIORITY_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHNLPRIORITY +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Clear the appropriate bit to select the default priority level for the +// specified uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to +// the high priority level. +// Bit [Ch] = 1: Channel Ch uses the default priority level. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_ERROR +// +//***************************************************************************** +// Field: [0] STATUS +// +// Returns the status of bus error flag in uDMA, or clears this bit +// +// Read as: +// +// 0: No bus error detected +// 1: Bus error detected +// +// Write as: +// +// 0: No effect, status of bus error flag is unchanged. +// 1: Clears the bus error flag. +#define UDMA_ERROR_STATUS 0x00000001 +#define UDMA_ERROR_STATUS_BITN 0 +#define UDMA_ERROR_STATUS_M 0x00000001 +#define UDMA_ERROR_STATUS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_REQDONE +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Reflects the uDMA done status for the given channel, channel [Ch]. It's a +// sticky done bit. Unless cleared by writing a 1, it holds the value of 1. +// +// Read as: +// Bit [Ch] = 0: Request has not completed for channel Ch +// Bit [Ch] = 1: Request has completed for the channel Ch +// +// Writing a 1 to individual bits would clear the corresponding bit. +// +// Write as: +// Bit [Ch] = 0: No effect. +// Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 +#define UDMA_REQDONE_CHNLS_W 32 +#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF +#define UDMA_REQDONE_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_DONEMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Controls the propagation of the uDMA done and active state to the assigned +// peripheral. Specifically used for software channels. +// +// Read as: +// Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from +// reaching to the peripherals. +// Note that the uDMA done state for channel [Ch] is blocked from contributing +// to generation of combined uDMA done signal +// +// Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from +// reaching to the peripherals. +// Note that the uDMA done state for channel [Ch] is not blocked from +// contributing to generation of combined uDMA done signal +// +// Write as: +// Bit [Ch] = 0: Allows uDMA done and active stat to propagate to the +// peripherals. +// Note that this disables uDMA done state for channel [Ch] from contributing +// to generation of combined uDMA done signal +// +// Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the +// peripherals. +// Note that this enables uDMA done for channel [Ch] to contribute to +// generation of combined uDMA done signal. +#define UDMA_DONEMASK_CHNLS_W 32 +#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_DONEMASK_CHNLS_S 0 + + +#endif // __UDMA__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_vims.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_vims.h new file mode 100644 index 0000000..8ba5b60 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_vims.h @@ -0,0 +1,206 @@ +/****************************************************************************** +* Filename: hw_vims_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_VIMS_H__ +#define __HW_VIMS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// VIMS component +// +//***************************************************************************** +// Status +#define VIMS_O_STAT 0x00000000 + +// Control +#define VIMS_O_CTL 0x00000004 + +//***************************************************************************** +// +// Register: VIMS_O_STAT +// +//***************************************************************************** +// Field: [5] IDCODE_LB_DIS +// +// Icode/Dcode flash line buffer status +// +// 0: Enabled or in transition to disabled +// 1: Disabled and flushed +#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 +#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_S 5 + +// Field: [4] SYSBUS_LB_DIS +// +// Sysbus flash line buffer control +// +// 0: Enabled or in transition to disabled +// 1: Disabled and flushed +#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 +#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_S 4 + +// Field: [3] MODE_CHANGING +// +// VIMS mode change status +// +// 0: VIMS is in the mode defined by MODE +// 1: VIMS is in the process of changing to the mode given in CTL.MODE +#define VIMS_STAT_MODE_CHANGING 0x00000008 +#define VIMS_STAT_MODE_CHANGING_BITN 3 +#define VIMS_STAT_MODE_CHANGING_M 0x00000008 +#define VIMS_STAT_MODE_CHANGING_S 3 + +// Field: [2] INV +// +// This bit is set when invalidation of the cache memory is active / ongoing +#define VIMS_STAT_INV 0x00000004 +#define VIMS_STAT_INV_BITN 2 +#define VIMS_STAT_INV_M 0x00000004 +#define VIMS_STAT_INV_S 2 + +// Field: [1:0] MODE +// +// Current VIMS mode +// ENUMs: +// OFF VIMS Off mode +// CACHE VIMS Cache mode +// GPRAM VIMS GPRAM mode +#define VIMS_STAT_MODE_W 2 +#define VIMS_STAT_MODE_M 0x00000003 +#define VIMS_STAT_MODE_S 0 +#define VIMS_STAT_MODE_OFF 0x00000003 +#define VIMS_STAT_MODE_CACHE 0x00000001 +#define VIMS_STAT_MODE_GPRAM 0x00000000 + +//***************************************************************************** +// +// Register: VIMS_O_CTL +// +//***************************************************************************** +// Field: [31] STATS_CLR +// +// Set this bit to clear statistic counters. +#define VIMS_CTL_STATS_CLR 0x80000000 +#define VIMS_CTL_STATS_CLR_BITN 31 +#define VIMS_CTL_STATS_CLR_M 0x80000000 +#define VIMS_CTL_STATS_CLR_S 31 + +// Field: [30] STATS_EN +// +// Set this bit to enable statistic counters. +#define VIMS_CTL_STATS_EN 0x40000000 +#define VIMS_CTL_STATS_EN_BITN 30 +#define VIMS_CTL_STATS_EN_M 0x40000000 +#define VIMS_CTL_STATS_EN_S 30 + +// Field: [29] DYN_CG_EN +// +// 0: The in-built clock gate functionality is bypassed. +// 1: The in-built clock gate functionality is enabled, automatically gating +// the clock when not needed. +#define VIMS_CTL_DYN_CG_EN 0x20000000 +#define VIMS_CTL_DYN_CG_EN_BITN 29 +#define VIMS_CTL_DYN_CG_EN_M 0x20000000 +#define VIMS_CTL_DYN_CG_EN_S 29 + +// Field: [5] IDCODE_LB_DIS +// +// Icode/Dcode flash line buffer control +// +// 0: Enable +// 1: Disable +#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 +#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_S 5 + +// Field: [4] SYSBUS_LB_DIS +// +// Sysbus flash line buffer control +// +// 0: Enable +// 1: Disable +#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 +#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_S 4 + +// Field: [3] ARB_CFG +// +// Icode/Dcode and sysbus arbitation scheme +// +// 0: Static arbitration (icode/docde > sysbus) +// 1: Round-robin arbitration +#define VIMS_CTL_ARB_CFG 0x00000008 +#define VIMS_CTL_ARB_CFG_BITN 3 +#define VIMS_CTL_ARB_CFG_M 0x00000008 +#define VIMS_CTL_ARB_CFG_S 3 + +// Field: [2] PREF_EN +// +// Tag prefetch control +// +// 0: Disabled +// 1: Enabled +#define VIMS_CTL_PREF_EN 0x00000004 +#define VIMS_CTL_PREF_EN_BITN 2 +#define VIMS_CTL_PREF_EN_M 0x00000004 +#define VIMS_CTL_PREF_EN_S 2 + +// Field: [1:0] MODE +// +// VIMS mode request. +// Write accesses to this field will be blocked while STAT.MODE_CHANGING is set +// to 1. +// Note: Transaction from CACHE mode to GPRAM mode should be done through OFF +// mode to minimize flash block delay. +// ENUMs: +// OFF VIMS Off mode +// CACHE VIMS Cache mode +// GPRAM VIMS GPRAM mode +#define VIMS_CTL_MODE_W 2 +#define VIMS_CTL_MODE_M 0x00000003 +#define VIMS_CTL_MODE_S 0 +#define VIMS_CTL_MODE_OFF 0x00000003 +#define VIMS_CTL_MODE_CACHE 0x00000001 +#define VIMS_CTL_MODE_GPRAM 0x00000000 + + +#endif // __VIMS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_wdt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_wdt.h new file mode 100644 index 0000000..3a67579 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_wdt.h @@ -0,0 +1,290 @@ +/****************************************************************************** +* Filename: hw_wdt_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_WDT_H__ +#define __HW_WDT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// WDT component +// +//***************************************************************************** +// Configuration +#define WDT_O_LOAD 0x00000000 + +// Current Count Value +#define WDT_O_VALUE 0x00000004 + +// Control +#define WDT_O_CTL 0x00000008 + +// Interrupt Clear +#define WDT_O_ICR 0x0000000C + +// Raw Interrupt Status +#define WDT_O_RIS 0x00000010 + +// Masked Interrupt Status +#define WDT_O_MIS 0x00000014 + +// Test Mode +#define WDT_O_TEST 0x00000418 + +// Interrupt Cause Test Mode +#define WDT_O_INT_CAUS 0x0000041C + +// Lock +#define WDT_O_LOCK 0x00000C00 + +//***************************************************************************** +// +// Register: WDT_O_LOAD +// +//***************************************************************************** +// Field: [31:0] WDTLOAD +// +// This register is the 32-bit interval value used by the 32-bit counter. When +// this register is written, the value is immediately loaded and the counter is +// restarted to count down from the new value. If this register is loaded with +// 0x0000.0000, an interrupt is immediately generated. +#define WDT_LOAD_WDTLOAD_W 32 +#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF +#define WDT_LOAD_WDTLOAD_S 0 + +//***************************************************************************** +// +// Register: WDT_O_VALUE +// +//***************************************************************************** +// Field: [31:0] WDTVALUE +// +// This register contains the current count value of the timer. +#define WDT_VALUE_WDTVALUE_W 32 +#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF +#define WDT_VALUE_WDTVALUE_S 0 + +//***************************************************************************** +// +// Register: WDT_O_CTL +// +//***************************************************************************** +// Field: [2] INTTYPE +// +// WDT Interrupt Type +// +// 0: WDT interrupt is a standard interrupt. +// 1: WDT interrupt is a non-maskable interrupt. +// ENUMs: +// NONMASKABLE Non-maskable interrupt +// MASKABLE Maskable interrupt +#define WDT_CTL_INTTYPE 0x00000004 +#define WDT_CTL_INTTYPE_BITN 2 +#define WDT_CTL_INTTYPE_M 0x00000004 +#define WDT_CTL_INTTYPE_S 2 +#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 +#define WDT_CTL_INTTYPE_MASKABLE 0x00000000 + +// Field: [1] RESEN +// +// WDT Reset Enable. Defines the function of the WDT reset source (see +// PRCM:WARMRESET.WDT_STAT if enabled) +// +// 0: Disabled. +// 1: Enable the Watchdog reset output. +// ENUMs: +// EN Reset output Enabled +// DIS Reset output Disabled +#define WDT_CTL_RESEN 0x00000002 +#define WDT_CTL_RESEN_BITN 1 +#define WDT_CTL_RESEN_M 0x00000002 +#define WDT_CTL_RESEN_S 1 +#define WDT_CTL_RESEN_EN 0x00000002 +#define WDT_CTL_RESEN_DIS 0x00000000 + +// Field: [0] INTEN +// +// WDT Interrupt Enable +// +// 0: Interrupt event disabled. +// 1: Interrupt event enabled. Once set, this bit can only be cleared by a +// hardware reset. +// ENUMs: +// EN Interrupt Enabled +// DIS Interrupt Disabled +#define WDT_CTL_INTEN 0x00000001 +#define WDT_CTL_INTEN_BITN 0 +#define WDT_CTL_INTEN_M 0x00000001 +#define WDT_CTL_INTEN_S 0 +#define WDT_CTL_INTEN_EN 0x00000001 +#define WDT_CTL_INTEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: WDT_O_ICR +// +//***************************************************************************** +// Field: [31:0] WDTICR +// +// This register is the interrupt clear register. A write of any value to this +// register clears the WDT interrupt and reloads the 32-bit counter from the +// LOAD register. +#define WDT_ICR_WDTICR_W 32 +#define WDT_ICR_WDTICR_M 0xFFFFFFFF +#define WDT_ICR_WDTICR_S 0 + +//***************************************************************************** +// +// Register: WDT_O_RIS +// +//***************************************************************************** +// Field: [0] WDTRIS +// +// This register is the raw interrupt status register. WDT interrupt events can +// be monitored via this register if the controller interrupt is masked. +// +// Value Description +// +// 0: The WDT has not timed out +// 1: A WDT time-out event has occurred +// +#define WDT_RIS_WDTRIS 0x00000001 +#define WDT_RIS_WDTRIS_BITN 0 +#define WDT_RIS_WDTRIS_M 0x00000001 +#define WDT_RIS_WDTRIS_S 0 + +//***************************************************************************** +// +// Register: WDT_O_MIS +// +//***************************************************************************** +// Field: [0] WDTMIS +// +// This register is the masked interrupt status register. The value of this +// register is the logical AND of the raw interrupt bit and the WDT interrupt +// enable bit CTL.INTEN. +// +// Value Description +// +// 0: The WDT has not timed out or is masked. +// 1: An unmasked WDT time-out event has occurred. +#define WDT_MIS_WDTMIS 0x00000001 +#define WDT_MIS_WDTMIS_BITN 0 +#define WDT_MIS_WDTMIS_M 0x00000001 +#define WDT_MIS_WDTMIS_S 0 + +//***************************************************************************** +// +// Register: WDT_O_TEST +// +//***************************************************************************** +// Field: [8] STALL +// +// WDT Stall Enable +// +// 0: The WDT timer continues counting if the CPU is stopped with a debugger. +// 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the +// CPU is restarted, the WDT resumes counting. +// ENUMs: +// EN Enable STALL +// DIS Disable STALL +#define WDT_TEST_STALL 0x00000100 +#define WDT_TEST_STALL_BITN 8 +#define WDT_TEST_STALL_M 0x00000100 +#define WDT_TEST_STALL_S 8 +#define WDT_TEST_STALL_EN 0x00000100 +#define WDT_TEST_STALL_DIS 0x00000000 + +// Field: [0] TEST_EN +// +// The test enable bit +// +// 0: Enable external reset +// 1: Disables the generation of an external reset. Instead bit 1 of the +// INT_CAUS register is set and an interrupt is generated +// ENUMs: +// EN Test mode Enabled +// DIS Test mode Disabled +#define WDT_TEST_TEST_EN 0x00000001 +#define WDT_TEST_TEST_EN_BITN 0 +#define WDT_TEST_TEST_EN_M 0x00000001 +#define WDT_TEST_TEST_EN_S 0 +#define WDT_TEST_TEST_EN_EN 0x00000001 +#define WDT_TEST_TEST_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: WDT_O_INT_CAUS +// +//***************************************************************************** +// Field: [1] CAUSE_RESET +// +// Indicates that the cause of an interrupt was a reset generated but blocked +// due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). +#define WDT_INT_CAUS_CAUSE_RESET 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_BITN 1 +#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_S 1 + +// Field: [0] CAUSE_INTR +// +// Replica of RIS.WDTRIS +#define WDT_INT_CAUS_CAUSE_INTR 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_BITN 0 +#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_S 0 + +//***************************************************************************** +// +// Register: WDT_O_LOCK +// +//***************************************************************************** +// Field: [31:0] WDTLOCK +// +// WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers +// for write access. A write of any other value reapplies the lock, preventing +// any register updates (NOTE: TEST.TEST_EN bit is not lockable). +// +// A read of this register returns the following values: +// +// 0x0000.0000: Unlocked +// 0x0000.0001: Locked +#define WDT_LOCK_WDTLOCK_W 32 +#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF +#define WDT_LOCK_WDTLOCK_S 0 + + +#endif // __WDT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ant_div.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ant_div.h new file mode 100644 index 0000000..b482529 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ant_div.h @@ -0,0 +1,410 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_ant_div.h +* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ +* Revision: $Revision: 18756 $ +* +* Description: RF core patch for CC13x0 Generic FSK antenna diversity +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_ANT_DIV_H +#define _RF_PATCH_CPE_ANT_DIV_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageAntDiv[] = { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, +}; +#define _NWORD_PATCHIMAGE_ANT_DIV 247 + +#define _NWORD_PATCHSYS_ANT_DIV 0 + +#define _IRQ_PATCH_0 0x21000679 + + +#ifndef _ANT_DIV_SYSRAM_START +#define _ANT_DIV_SYSRAM_START 0x20000000 +#endif + +#ifndef _ANT_DIV_CPERAM_START +#define _ANT_DIV_CPERAM_START 0x21000000 +#endif + +#define _ANT_DIV_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _ANT_DIV_PARSER_PATCH_TAB_OFFSET 0x0338 +#define _ANT_DIV_PATCH_TAB_OFFSET 0x0340 +#define _ANT_DIV_IRQPATCH_OFFSET 0x03BC +#define _ANT_DIV_PATCH_VEC_OFFSET 0x041C + +PATCH_FUN_SPEC void enterAntDivCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_ANT_DIV > 0) + uint32_t *pPatchVec = (uint32_t *) (_ANT_DIV_CPERAM_START + _ANT_DIV_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageAntDiv, sizeof(patchImageAntDiv)); +#endif +} + +PATCH_FUN_SPEC void enterAntDivSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureAntDivPatch(void) +{ + uint8_t *pParserPatchTab = (uint8_t *) (_ANT_DIV_CPERAM_START + _ANT_DIV_PARSER_PATCH_TAB_OFFSET); + uint8_t *pPatchTab = (uint8_t *) (_ANT_DIV_CPERAM_START + _ANT_DIV_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_ANT_DIV_CPERAM_START + _ANT_DIV_IRQPATCH_OFFSET); + + + pPatchTab[80] = 0; + pPatchTab[57] = 1; + pPatchTab[53] = 2; + pPatchTab[55] = 3; + pPatchTab[110] = 4; + pPatchTab[107] = 5; + pPatchTab[65] = 6; + pPatchTab[13] = 7; + pPatchTab[43] = 8; + pPatchTab[45] = 9; + pPatchTab[48] = 10; + pParserPatchTab[0] = 11; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyAntDivPatch(void) +{ + enterAntDivSysPatch(); + enterAntDivCpePatch(); + configureAntDivPatch(); +} + +PATCH_FUN_SPEC void refreshAntDivPatch(void) +{ + enterAntDivCpePatch(); + configureAntDivPatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_ant_div(void) +{ + applyAntDivPatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_ANT_DIV_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble.h new file mode 100644 index 0000000..9e245c4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble.h @@ -0,0 +1,260 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_ble.h +* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ +* Revision: $Revision: 18438 $ +* +* Description: RF Core patch file for CC1350 Bluetooth Low Energy +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_BLE_H +#define _RF_PATCH_CPE_BLE_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageBle[] = { + 0x21000439, + 0x2100044b, + 0x2100044b, + 0x21000471, + 0x21000551, + 0x21000495, + 0x210005a7, + 0x490b4c0c, + 0x28ff7820, + 0x7ac8d101, + 0x20077020, + 0x4c08e006, + 0x28ff7820, + 0x21ffd007, + 0x49047021, + 0x0224240f, + 0x31604320, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210005c8, + 0xf82ef000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4905b570, + 0xb6724a05, + 0x28017908, + 0x2001dc02, + 0x1d127088, + 0x4710b662, + 0x21000298, + 0x00004a81, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xff8df7ff, + 0xb510bd10, + 0xff84f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x000000ff, +}; +#define _NWORD_PATCHIMAGE_BLE 108 + +#define _NWORD_PATCHSYS_BLE 0 + + + +#ifndef _BLE_SYSRAM_START +#define _BLE_SYSRAM_START 0x20000000 +#endif + +#ifndef _BLE_CPERAM_START +#define _BLE_CPERAM_START 0x21000000 +#endif + +#define _BLE_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _BLE_PARSER_PATCH_TAB_OFFSET 0x0338 +#define _BLE_PATCH_TAB_OFFSET 0x0340 +#define _BLE_IRQPATCH_OFFSET 0x03BC +#define _BLE_PATCH_VEC_OFFSET 0x041C + +PATCH_FUN_SPEC void enterBleCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_BLE > 0) + uint32_t *pPatchVec = (uint32_t *) (_BLE_CPERAM_START + _BLE_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageBle, sizeof(patchImageBle)); +#endif +} + +PATCH_FUN_SPEC void enterBleSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureBlePatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_BLE_CPERAM_START + _BLE_PATCH_TAB_OFFSET); + + + pPatchTab[112] = 0; + pPatchTab[104] = 1; + pPatchTab[105] = 2; + pPatchTab[110] = 3; + pPatchTab[65] = 4; + pPatchTab[53] = 5; + pPatchTab[48] = 6; +} + +PATCH_FUN_SPEC void applyBlePatch(void) +{ + enterBleSysPatch(); + enterBleCpePatch(); + configureBlePatch(); +} + +PATCH_FUN_SPEC void refreshBlePatch(void) +{ + enterBleCpePatch(); + configureBlePatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_ble(void) +{ + applyBlePatch(); +} + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_BLE_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h new file mode 100644 index 0000000..ab37115 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h @@ -0,0 +1,355 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_ble_priv_1_2.h +* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ +* Revision: $Revision: 18438 $ +* +* Description: RF Core patch file for CC1350 Bluetooth Low Energy with privacy 1.2 support +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_BLE_PRIV_1_2_H +#define _RF_PATCH_CPE_BLE_PRIV_1_2_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageBlePriv12[] = { + 0x210005fd, + 0x2100043d, + 0x2100044f, + 0x2100044f, + 0x21000475, + 0x210006c9, + 0x21000499, + 0x2100071f, + 0x490b4c0c, + 0x28ff7820, + 0x7ac8d101, + 0x20077020, + 0x4c08e006, + 0x28ff7820, + 0x21ffd007, + 0x49047021, + 0x0224240f, + 0x31604320, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x21000740, + 0xf8e8f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4905b570, + 0xb6724a05, + 0x28017908, + 0x2001dc02, + 0x1d127088, + 0x4710b662, + 0x21000298, + 0x00004a81, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4d53b5fe, + 0x462c4628, + 0x90003040, + 0x7e014627, + 0x78383760, + 0xd0022900, + 0xd10707c0, + 0x09c1e050, + 0x07c0d04e, + 0x7d20d14c, + 0xd5490640, + 0x31724629, + 0x20064a48, + 0x98004790, + 0x28007e00, + 0x7d20d007, + 0xd5010640, + 0xe0002003, + 0x26132001, + 0x6f68e008, + 0x28010f80, + 0x2006d002, + 0xe0014606, + 0x26072003, + 0x02312201, + 0x1a890412, + 0x02008a7a, + 0x43020412, + 0x35806f6b, + 0x68a89501, + 0x47a84d37, + 0x2e062201, + 0x2e07d002, + 0xe007d002, + 0xe00543c0, + 0x70797839, + 0x70394311, + 0x61089901, + 0xda012800, + 0x55022039, + 0x7e809800, + 0xd0022800, + 0x201e2106, + 0x6a61e002, + 0x201f1f89, + 0x6ca162a1, + 0x64e04788, + 0xbdfe2000, + 0x47804826, + 0x4822bdfe, + 0x78413060, + 0xd0022900, + 0x21007001, + 0x48217041, + 0x470038b0, + 0x4e1cb5f8, + 0x4635481f, + 0x7fec3540, + 0x09e14637, + 0x6db1d01a, + 0xd0172901, + 0x29007f69, + 0x07a1d002, + 0xe011d502, + 0xd10f07e1, + 0x06497d39, + 0x2103d50c, + 0x77e94321, + 0x6f314780, + 0x29010f89, + 0x2100d002, + 0x76793720, + 0xbdf877ec, + 0xbdf84780, + 0x31404909, + 0x28157508, + 0x281bd008, + 0x281dd008, + 0x490ad008, + 0x18400080, + 0x47706980, + 0x47704808, + 0x47704808, + 0x47704808, + 0x21000144, + 0x000100af, + 0x0000e801, + 0x00010603, + 0x0001018d, + 0x000114c0, + 0x210005b1, + 0x2100059b, + 0x210004d5, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfed3f7ff, + 0xb510bd10, + 0xfecaf7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x000000ff, +}; +#define _NWORD_PATCHIMAGE_BLE_PRIV_1_2 202 + +#define _NWORD_PATCHSYS_BLE_PRIV_1_2 0 + + + +#ifndef _BLE_PRIV_1_2_SYSRAM_START +#define _BLE_PRIV_1_2_SYSRAM_START 0x20000000 +#endif + +#ifndef _BLE_PRIV_1_2_CPERAM_START +#define _BLE_PRIV_1_2_CPERAM_START 0x21000000 +#endif + +#define _BLE_PRIV_1_2_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _BLE_PRIV_1_2_PARSER_PATCH_TAB_OFFSET 0x0338 +#define _BLE_PRIV_1_2_PATCH_TAB_OFFSET 0x0340 +#define _BLE_PRIV_1_2_IRQPATCH_OFFSET 0x03BC +#define _BLE_PRIV_1_2_PATCH_VEC_OFFSET 0x041C + +PATCH_FUN_SPEC void enterBlePriv12CpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_BLE_PRIV_1_2 > 0) + uint32_t *pPatchVec = (uint32_t *) (_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageBlePriv12, sizeof(patchImageBlePriv12)); +#endif +} + +PATCH_FUN_SPEC void enterBlePriv12SysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureBlePriv12Patch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_TAB_OFFSET); + + + pPatchTab[1] = 0; + pPatchTab[112] = 1; + pPatchTab[104] = 2; + pPatchTab[105] = 3; + pPatchTab[110] = 4; + pPatchTab[65] = 5; + pPatchTab[53] = 6; + pPatchTab[48] = 7; +} + +PATCH_FUN_SPEC void applyBlePriv12Patch(void) +{ + enterBlePriv12SysPatch(); + enterBlePriv12CpePatch(); + configureBlePriv12Patch(); +} + +PATCH_FUN_SPEC void refreshBlePriv12Patch(void) +{ + enterBlePriv12CpePatch(); + configureBlePriv12Patch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_ble_priv_1_2(void) +{ + applyBlePriv12Patch(); +} + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_BLE_PRIV_1_2_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_brepeat.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_brepeat.h new file mode 100644 index 0000000..ed41822 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_brepeat.h @@ -0,0 +1,410 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_brepeat.h +* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ +* Revision: $Revision: 18756 $ +* +* Description: RF core patch for CC13x0 for 1.2kbps and 2.4kbps Generic FSK +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_BREPEAT_H +#define _RF_PATCH_CPE_BREPEAT_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageBrepeat[] = { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, +}; +#define _NWORD_PATCHIMAGE_BREPEAT 247 + +#define _NWORD_PATCHSYS_BREPEAT 0 + +#define _IRQ_PATCH_0 0x21000679 + + +#ifndef _BREPEAT_SYSRAM_START +#define _BREPEAT_SYSRAM_START 0x20000000 +#endif + +#ifndef _BREPEAT_CPERAM_START +#define _BREPEAT_CPERAM_START 0x21000000 +#endif + +#define _BREPEAT_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _BREPEAT_PARSER_PATCH_TAB_OFFSET 0x0338 +#define _BREPEAT_PATCH_TAB_OFFSET 0x0340 +#define _BREPEAT_IRQPATCH_OFFSET 0x03BC +#define _BREPEAT_PATCH_VEC_OFFSET 0x041C + +PATCH_FUN_SPEC void enterBrepeatCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_BREPEAT > 0) + uint32_t *pPatchVec = (uint32_t *) (_BREPEAT_CPERAM_START + _BREPEAT_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageBrepeat, sizeof(patchImageBrepeat)); +#endif +} + +PATCH_FUN_SPEC void enterBrepeatSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureBrepeatPatch(void) +{ + uint8_t *pParserPatchTab = (uint8_t *) (_BREPEAT_CPERAM_START + _BREPEAT_PARSER_PATCH_TAB_OFFSET); + uint8_t *pPatchTab = (uint8_t *) (_BREPEAT_CPERAM_START + _BREPEAT_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_BREPEAT_CPERAM_START + _BREPEAT_IRQPATCH_OFFSET); + + + pPatchTab[80] = 0; + pPatchTab[57] = 1; + pPatchTab[53] = 2; + pPatchTab[55] = 3; + pPatchTab[110] = 4; + pPatchTab[107] = 5; + pPatchTab[65] = 6; + pPatchTab[13] = 7; + pPatchTab[43] = 8; + pPatchTab[45] = 9; + pPatchTab[48] = 10; + pParserPatchTab[0] = 11; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyBrepeatPatch(void) +{ + enterBrepeatSysPatch(); + enterBrepeatCpePatch(); + configureBrepeatPatch(); +} + +PATCH_FUN_SPEC void refreshBrepeatPatch(void) +{ + enterBrepeatCpePatch(); + configureBrepeatPatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_brepeat(void) +{ + applyBrepeatPatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_BREPEAT_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genfsk.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genfsk.h new file mode 100644 index 0000000..7d1a396 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genfsk.h @@ -0,0 +1,410 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_genfsk.h +* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ +* Revision: $Revision: 18756 $ +* +* Description: RF Core patch file for CC13x0 generic FSK +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_GENFSK_H +#define _RF_PATCH_CPE_GENFSK_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageGenfsk[] = { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, +}; +#define _NWORD_PATCHIMAGE_GENFSK 247 + +#define _NWORD_PATCHSYS_GENFSK 0 + +#define _IRQ_PATCH_0 0x21000679 + + +#ifndef _GENFSK_SYSRAM_START +#define _GENFSK_SYSRAM_START 0x20000000 +#endif + +#ifndef _GENFSK_CPERAM_START +#define _GENFSK_CPERAM_START 0x21000000 +#endif + +#define _GENFSK_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _GENFSK_PARSER_PATCH_TAB_OFFSET 0x0338 +#define _GENFSK_PATCH_TAB_OFFSET 0x0340 +#define _GENFSK_IRQPATCH_OFFSET 0x03BC +#define _GENFSK_PATCH_VEC_OFFSET 0x041C + +PATCH_FUN_SPEC void enterGenfskCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_GENFSK > 0) + uint32_t *pPatchVec = (uint32_t *) (_GENFSK_CPERAM_START + _GENFSK_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageGenfsk, sizeof(patchImageGenfsk)); +#endif +} + +PATCH_FUN_SPEC void enterGenfskSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureGenfskPatch(void) +{ + uint8_t *pParserPatchTab = (uint8_t *) (_GENFSK_CPERAM_START + _GENFSK_PARSER_PATCH_TAB_OFFSET); + uint8_t *pPatchTab = (uint8_t *) (_GENFSK_CPERAM_START + _GENFSK_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_GENFSK_CPERAM_START + _GENFSK_IRQPATCH_OFFSET); + + + pPatchTab[80] = 0; + pPatchTab[57] = 1; + pPatchTab[53] = 2; + pPatchTab[55] = 3; + pPatchTab[110] = 4; + pPatchTab[107] = 5; + pPatchTab[65] = 6; + pPatchTab[13] = 7; + pPatchTab[43] = 8; + pPatchTab[45] = 9; + pPatchTab[48] = 10; + pParserPatchTab[0] = 11; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyGenfskPatch(void) +{ + enterGenfskSysPatch(); + enterGenfskCpePatch(); + configureGenfskPatch(); +} + +PATCH_FUN_SPEC void refreshGenfskPatch(void) +{ + enterGenfskCpePatch(); + configureGenfskPatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_genfsk(void) +{ + applyGenfskPatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_GENFSK_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genook.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genook.h new file mode 100644 index 0000000..ba5f4d2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genook.h @@ -0,0 +1,410 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_genook.h +* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ +* Revision: $Revision: 18756 $ +* +* Description: RF core patch for CC13x0 Generic OOK +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_GENOOK_H +#define _RF_PATCH_CPE_GENOOK_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageGenook[] = { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, +}; +#define _NWORD_PATCHIMAGE_GENOOK 247 + +#define _NWORD_PATCHSYS_GENOOK 0 + +#define _IRQ_PATCH_0 0x21000679 + + +#ifndef _GENOOK_SYSRAM_START +#define _GENOOK_SYSRAM_START 0x20000000 +#endif + +#ifndef _GENOOK_CPERAM_START +#define _GENOOK_CPERAM_START 0x21000000 +#endif + +#define _GENOOK_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _GENOOK_PARSER_PATCH_TAB_OFFSET 0x0338 +#define _GENOOK_PATCH_TAB_OFFSET 0x0340 +#define _GENOOK_IRQPATCH_OFFSET 0x03BC +#define _GENOOK_PATCH_VEC_OFFSET 0x041C + +PATCH_FUN_SPEC void enterGenookCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_GENOOK > 0) + uint32_t *pPatchVec = (uint32_t *) (_GENOOK_CPERAM_START + _GENOOK_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageGenook, sizeof(patchImageGenook)); +#endif +} + +PATCH_FUN_SPEC void enterGenookSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureGenookPatch(void) +{ + uint8_t *pParserPatchTab = (uint8_t *) (_GENOOK_CPERAM_START + _GENOOK_PARSER_PATCH_TAB_OFFSET); + uint8_t *pPatchTab = (uint8_t *) (_GENOOK_CPERAM_START + _GENOOK_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_GENOOK_CPERAM_START + _GENOOK_IRQPATCH_OFFSET); + + + pPatchTab[80] = 0; + pPatchTab[57] = 1; + pPatchTab[53] = 2; + pPatchTab[55] = 3; + pPatchTab[110] = 4; + pPatchTab[107] = 5; + pPatchTab[65] = 6; + pPatchTab[13] = 7; + pPatchTab[43] = 8; + pPatchTab[45] = 9; + pPatchTab[48] = 10; + pParserPatchTab[0] = 11; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyGenookPatch(void) +{ + enterGenookSysPatch(); + enterGenookCpePatch(); + configureGenookPatch(); +} + +PATCH_FUN_SPEC void refreshGenookPatch(void) +{ + enterGenookCpePatch(); + configureGenookPatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_genook(void) +{ + applyGenookPatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_GENOOK_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ghs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ghs.h new file mode 100644 index 0000000..faa572b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ghs.h @@ -0,0 +1,410 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_ghs.h +* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ +* Revision: $Revision: 18756 $ +* +* Description: RF core patch for CC13x0 Generic 4FSK up to 1.5Mbps +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_GHS_H +#define _RF_PATCH_CPE_GHS_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageGhs[] = { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, +}; +#define _NWORD_PATCHIMAGE_GHS 247 + +#define _NWORD_PATCHSYS_GHS 0 + +#define _IRQ_PATCH_0 0x21000679 + + +#ifndef _GHS_SYSRAM_START +#define _GHS_SYSRAM_START 0x20000000 +#endif + +#ifndef _GHS_CPERAM_START +#define _GHS_CPERAM_START 0x21000000 +#endif + +#define _GHS_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _GHS_PARSER_PATCH_TAB_OFFSET 0x0338 +#define _GHS_PATCH_TAB_OFFSET 0x0340 +#define _GHS_IRQPATCH_OFFSET 0x03BC +#define _GHS_PATCH_VEC_OFFSET 0x041C + +PATCH_FUN_SPEC void enterGhsCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_GHS > 0) + uint32_t *pPatchVec = (uint32_t *) (_GHS_CPERAM_START + _GHS_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageGhs, sizeof(patchImageGhs)); +#endif +} + +PATCH_FUN_SPEC void enterGhsSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureGhsPatch(void) +{ + uint8_t *pParserPatchTab = (uint8_t *) (_GHS_CPERAM_START + _GHS_PARSER_PATCH_TAB_OFFSET); + uint8_t *pPatchTab = (uint8_t *) (_GHS_CPERAM_START + _GHS_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_GHS_CPERAM_START + _GHS_IRQPATCH_OFFSET); + + + pPatchTab[80] = 0; + pPatchTab[57] = 1; + pPatchTab[53] = 2; + pPatchTab[55] = 3; + pPatchTab[110] = 4; + pPatchTab[107] = 5; + pPatchTab[65] = 6; + pPatchTab[13] = 7; + pPatchTab[43] = 8; + pPatchTab[45] = 9; + pPatchTab[48] = 10; + pParserPatchTab[0] = 11; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyGhsPatch(void) +{ + enterGhsSysPatch(); + enterGhsCpePatch(); + configureGhsPatch(); +} + +PATCH_FUN_SPEC void refreshGhsPatch(void) +{ + enterGhsCpePatch(); + configureGhsPatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_ghs(void) +{ + applyGhsPatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_GHS_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_lrm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_lrm.h new file mode 100644 index 0000000..17cda8d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_lrm.h @@ -0,0 +1,410 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_lrm.h +* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ +* Revision: $Revision: 18756 $ +* +* Description: RF core patch for CC13x0 Legacy Long Range Mode +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_LRM_H +#define _RF_PATCH_CPE_LRM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageLrm[] = { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, +}; +#define _NWORD_PATCHIMAGE_LRM 247 + +#define _NWORD_PATCHSYS_LRM 0 + +#define _IRQ_PATCH_0 0x21000679 + + +#ifndef _LRM_SYSRAM_START +#define _LRM_SYSRAM_START 0x20000000 +#endif + +#ifndef _LRM_CPERAM_START +#define _LRM_CPERAM_START 0x21000000 +#endif + +#define _LRM_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _LRM_PARSER_PATCH_TAB_OFFSET 0x0338 +#define _LRM_PATCH_TAB_OFFSET 0x0340 +#define _LRM_IRQPATCH_OFFSET 0x03BC +#define _LRM_PATCH_VEC_OFFSET 0x041C + +PATCH_FUN_SPEC void enterLrmCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_LRM > 0) + uint32_t *pPatchVec = (uint32_t *) (_LRM_CPERAM_START + _LRM_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageLrm, sizeof(patchImageLrm)); +#endif +} + +PATCH_FUN_SPEC void enterLrmSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureLrmPatch(void) +{ + uint8_t *pParserPatchTab = (uint8_t *) (_LRM_CPERAM_START + _LRM_PARSER_PATCH_TAB_OFFSET); + uint8_t *pPatchTab = (uint8_t *) (_LRM_CPERAM_START + _LRM_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_LRM_CPERAM_START + _LRM_IRQPATCH_OFFSET); + + + pPatchTab[80] = 0; + pPatchTab[57] = 1; + pPatchTab[53] = 2; + pPatchTab[55] = 3; + pPatchTab[110] = 4; + pPatchTab[107] = 5; + pPatchTab[65] = 6; + pPatchTab[13] = 7; + pPatchTab[43] = 8; + pPatchTab[45] = 9; + pPatchTab[48] = 10; + pParserPatchTab[0] = 11; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyLrmPatch(void) +{ + enterLrmSysPatch(); + enterLrmCpePatch(); + configureLrmPatch(); +} + +PATCH_FUN_SPEC void refreshLrmPatch(void) +{ + enterLrmCpePatch(); + configureLrmPatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_lrm(void) +{ + applyLrmPatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_LRM_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_sl_longrange.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_sl_longrange.h new file mode 100644 index 0000000..c8608ff --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_sl_longrange.h @@ -0,0 +1,410 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_sl_longrange.h +* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ +* Revision: $Revision: 18756 $ +* +* Description: RF core patch for CC13x0 SimpleLink Long Range +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_SL_LONGRANGE_H +#define _RF_PATCH_CPE_SL_LONGRANGE_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageSlLongrange[] = { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, +}; +#define _NWORD_PATCHIMAGE_SL_LONGRANGE 247 + +#define _NWORD_PATCHSYS_SL_LONGRANGE 0 + +#define _IRQ_PATCH_0 0x21000679 + + +#ifndef _SL_LONGRANGE_SYSRAM_START +#define _SL_LONGRANGE_SYSRAM_START 0x20000000 +#endif + +#ifndef _SL_LONGRANGE_CPERAM_START +#define _SL_LONGRANGE_CPERAM_START 0x21000000 +#endif + +#define _SL_LONGRANGE_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _SL_LONGRANGE_PARSER_PATCH_TAB_OFFSET 0x0338 +#define _SL_LONGRANGE_PATCH_TAB_OFFSET 0x0340 +#define _SL_LONGRANGE_IRQPATCH_OFFSET 0x03BC +#define _SL_LONGRANGE_PATCH_VEC_OFFSET 0x041C + +PATCH_FUN_SPEC void enterSlLongrangeCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_SL_LONGRANGE > 0) + uint32_t *pPatchVec = (uint32_t *) (_SL_LONGRANGE_CPERAM_START + _SL_LONGRANGE_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageSlLongrange, sizeof(patchImageSlLongrange)); +#endif +} + +PATCH_FUN_SPEC void enterSlLongrangeSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureSlLongrangePatch(void) +{ + uint8_t *pParserPatchTab = (uint8_t *) (_SL_LONGRANGE_CPERAM_START + _SL_LONGRANGE_PARSER_PATCH_TAB_OFFSET); + uint8_t *pPatchTab = (uint8_t *) (_SL_LONGRANGE_CPERAM_START + _SL_LONGRANGE_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_SL_LONGRANGE_CPERAM_START + _SL_LONGRANGE_IRQPATCH_OFFSET); + + + pPatchTab[80] = 0; + pPatchTab[57] = 1; + pPatchTab[53] = 2; + pPatchTab[55] = 3; + pPatchTab[110] = 4; + pPatchTab[107] = 5; + pPatchTab[65] = 6; + pPatchTab[13] = 7; + pPatchTab[43] = 8; + pPatchTab[45] = 9; + pPatchTab[48] = 10; + pParserPatchTab[0] = 11; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applySlLongrangePatch(void) +{ + enterSlLongrangeSysPatch(); + enterSlLongrangeCpePatch(); + configureSlLongrangePatch(); +} + +PATCH_FUN_SPEC void refreshSlLongrangePatch(void) +{ + enterSlLongrangeCpePatch(); + configureSlLongrangePatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_sl_longrange(void) +{ + applySlLongrangePatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_SL_LONGRANGE_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wb_dsss.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wb_dsss.h new file mode 100644 index 0000000..1d9a16c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wb_dsss.h @@ -0,0 +1,410 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_wb_dsss.h +* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ +* Revision: $Revision: 18756 $ +* +* Description: RF core patch for CC13x0 Wideband DSSS +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_WB_DSSS_H +#define _RF_PATCH_CPE_WB_DSSS_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageWbDsss[] = { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, +}; +#define _NWORD_PATCHIMAGE_WB_DSSS 247 + +#define _NWORD_PATCHSYS_WB_DSSS 0 + +#define _IRQ_PATCH_0 0x21000679 + + +#ifndef _WB_DSSS_SYSRAM_START +#define _WB_DSSS_SYSRAM_START 0x20000000 +#endif + +#ifndef _WB_DSSS_CPERAM_START +#define _WB_DSSS_CPERAM_START 0x21000000 +#endif + +#define _WB_DSSS_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _WB_DSSS_PARSER_PATCH_TAB_OFFSET 0x0338 +#define _WB_DSSS_PATCH_TAB_OFFSET 0x0340 +#define _WB_DSSS_IRQPATCH_OFFSET 0x03BC +#define _WB_DSSS_PATCH_VEC_OFFSET 0x041C + +PATCH_FUN_SPEC void enterWbDsssCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_WB_DSSS > 0) + uint32_t *pPatchVec = (uint32_t *) (_WB_DSSS_CPERAM_START + _WB_DSSS_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageWbDsss, sizeof(patchImageWbDsss)); +#endif +} + +PATCH_FUN_SPEC void enterWbDsssSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureWbDsssPatch(void) +{ + uint8_t *pParserPatchTab = (uint8_t *) (_WB_DSSS_CPERAM_START + _WB_DSSS_PARSER_PATCH_TAB_OFFSET); + uint8_t *pPatchTab = (uint8_t *) (_WB_DSSS_CPERAM_START + _WB_DSSS_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_WB_DSSS_CPERAM_START + _WB_DSSS_IRQPATCH_OFFSET); + + + pPatchTab[80] = 0; + pPatchTab[57] = 1; + pPatchTab[53] = 2; + pPatchTab[55] = 3; + pPatchTab[110] = 4; + pPatchTab[107] = 5; + pPatchTab[65] = 6; + pPatchTab[13] = 7; + pPatchTab[43] = 8; + pPatchTab[45] = 9; + pPatchTab[48] = 10; + pParserPatchTab[0] = 11; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyWbDsssPatch(void) +{ + enterWbDsssSysPatch(); + enterWbDsssCpePatch(); + configureWbDsssPatch(); +} + +PATCH_FUN_SPEC void refreshWbDsssPatch(void) +{ + enterWbDsssCpePatch(); + configureWbDsssPatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_wb_dsss(void) +{ + applyWbDsssPatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_WB_DSSS_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_ctmode.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_ctmode.h new file mode 100644 index 0000000..bc2482e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_ctmode.h @@ -0,0 +1,410 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_wmbus_ctmode.h +* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ +* Revision: $Revision: 18756 $ +* +* Description: RF core patch for CC13x0 WMBUS C- and T-Mode +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_WMBUS_CTMODE_H +#define _RF_PATCH_CPE_WMBUS_CTMODE_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageWmbusCtmode[] = { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, +}; +#define _NWORD_PATCHIMAGE_WMBUS_CTMODE 247 + +#define _NWORD_PATCHSYS_WMBUS_CTMODE 0 + +#define _IRQ_PATCH_0 0x21000679 + + +#ifndef _WMBUS_CTMODE_SYSRAM_START +#define _WMBUS_CTMODE_SYSRAM_START 0x20000000 +#endif + +#ifndef _WMBUS_CTMODE_CPERAM_START +#define _WMBUS_CTMODE_CPERAM_START 0x21000000 +#endif + +#define _WMBUS_CTMODE_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _WMBUS_CTMODE_PARSER_PATCH_TAB_OFFSET 0x0338 +#define _WMBUS_CTMODE_PATCH_TAB_OFFSET 0x0340 +#define _WMBUS_CTMODE_IRQPATCH_OFFSET 0x03BC +#define _WMBUS_CTMODE_PATCH_VEC_OFFSET 0x041C + +PATCH_FUN_SPEC void enterWmbusCtmodeCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_WMBUS_CTMODE > 0) + uint32_t *pPatchVec = (uint32_t *) (_WMBUS_CTMODE_CPERAM_START + _WMBUS_CTMODE_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageWmbusCtmode, sizeof(patchImageWmbusCtmode)); +#endif +} + +PATCH_FUN_SPEC void enterWmbusCtmodeSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureWmbusCtmodePatch(void) +{ + uint8_t *pParserPatchTab = (uint8_t *) (_WMBUS_CTMODE_CPERAM_START + _WMBUS_CTMODE_PARSER_PATCH_TAB_OFFSET); + uint8_t *pPatchTab = (uint8_t *) (_WMBUS_CTMODE_CPERAM_START + _WMBUS_CTMODE_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_WMBUS_CTMODE_CPERAM_START + _WMBUS_CTMODE_IRQPATCH_OFFSET); + + + pPatchTab[80] = 0; + pPatchTab[57] = 1; + pPatchTab[53] = 2; + pPatchTab[55] = 3; + pPatchTab[110] = 4; + pPatchTab[107] = 5; + pPatchTab[65] = 6; + pPatchTab[13] = 7; + pPatchTab[43] = 8; + pPatchTab[45] = 9; + pPatchTab[48] = 10; + pParserPatchTab[0] = 11; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyWmbusCtmodePatch(void) +{ + enterWmbusCtmodeSysPatch(); + enterWmbusCtmodeCpePatch(); + configureWmbusCtmodePatch(); +} + +PATCH_FUN_SPEC void refreshWmbusCtmodePatch(void) +{ + enterWmbusCtmodeCpePatch(); + configureWmbusCtmodePatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_wmbus_ctmode(void) +{ + applyWmbusCtmodePatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_WMBUS_CTMODE_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_smode.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_smode.h new file mode 100644 index 0000000..2bfe15a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_smode.h @@ -0,0 +1,410 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_wmbus_smode.h +* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ +* Revision: $Revision: 18756 $ +* +* Description: RF core patch for CC13x0 WMBUS S-Mode +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_WMBUS_SMODE_H +#define _RF_PATCH_CPE_WMBUS_SMODE_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageWmbusSmode[] = { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, +}; +#define _NWORD_PATCHIMAGE_WMBUS_SMODE 247 + +#define _NWORD_PATCHSYS_WMBUS_SMODE 0 + +#define _IRQ_PATCH_0 0x21000679 + + +#ifndef _WMBUS_SMODE_SYSRAM_START +#define _WMBUS_SMODE_SYSRAM_START 0x20000000 +#endif + +#ifndef _WMBUS_SMODE_CPERAM_START +#define _WMBUS_SMODE_CPERAM_START 0x21000000 +#endif + +#define _WMBUS_SMODE_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _WMBUS_SMODE_PARSER_PATCH_TAB_OFFSET 0x0338 +#define _WMBUS_SMODE_PATCH_TAB_OFFSET 0x0340 +#define _WMBUS_SMODE_IRQPATCH_OFFSET 0x03BC +#define _WMBUS_SMODE_PATCH_VEC_OFFSET 0x041C + +PATCH_FUN_SPEC void enterWmbusSmodeCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_WMBUS_SMODE > 0) + uint32_t *pPatchVec = (uint32_t *) (_WMBUS_SMODE_CPERAM_START + _WMBUS_SMODE_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageWmbusSmode, sizeof(patchImageWmbusSmode)); +#endif +} + +PATCH_FUN_SPEC void enterWmbusSmodeSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureWmbusSmodePatch(void) +{ + uint8_t *pParserPatchTab = (uint8_t *) (_WMBUS_SMODE_CPERAM_START + _WMBUS_SMODE_PARSER_PATCH_TAB_OFFSET); + uint8_t *pPatchTab = (uint8_t *) (_WMBUS_SMODE_CPERAM_START + _WMBUS_SMODE_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_WMBUS_SMODE_CPERAM_START + _WMBUS_SMODE_IRQPATCH_OFFSET); + + + pPatchTab[80] = 0; + pPatchTab[57] = 1; + pPatchTab[53] = 2; + pPatchTab[55] = 3; + pPatchTab[110] = 4; + pPatchTab[107] = 5; + pPatchTab[65] = 6; + pPatchTab[13] = 7; + pPatchTab[43] = 8; + pPatchTab[45] = 9; + pPatchTab[48] = 10; + pParserPatchTab[0] = 11; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyWmbusSmodePatch(void) +{ + enterWmbusSmodeSysPatch(); + enterWmbusSmodeCpePatch(); + configureWmbusSmodePatch(); +} + +PATCH_FUN_SPEC void refreshWmbusSmodePatch(void) +{ + enterWmbusSmodeCpePatch(); + configureWmbusSmodePatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_wmbus_smode(void) +{ + applyWmbusSmodePatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_WMBUS_SMODE_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_brepeat.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_brepeat.h new file mode 100644 index 0000000..588d54c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_brepeat.h @@ -0,0 +1,413 @@ +/****************************************************************************** +* Filename: rf_patch_mce_brepeat.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 for 1.2kbps and 2.4kbps Generic FSK +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_BREPEAT_H +#define _RF_PATCH_MCE_BREPEAT_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchBrepeatMce[302] = { + 0x2fcf604e, + 0x030c3f9d, + 0x070c680a, + 0x00068080, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xf80007c0, + 0x1f0000f8, + 0xe007003f, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00070003, + 0x00003d1f, + 0x04000000, + 0x0000000f, + 0x000b0387, + 0x004348f4, + 0x80078000, + 0x00000670, + 0x0510091e, + 0x00070054, + 0x1f080100, + 0x00000031, + 0x3030002f, + 0x0000027f, + 0x00000000, + 0x0000aa00, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72487220, + 0x7303a32d, + 0x72037305, + 0x73067304, + 0x73767204, + 0xc7c07276, + 0x00018001, + 0x90109001, + 0x90010801, + 0x720d720c, + 0xb0c0720e, + 0xb0f07100, + 0x7218a0c0, + 0x10208132, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60836c01, + 0x60a06084, + 0x60836178, + 0x60836083, + 0x12106083, + 0x730f7220, + 0x73117310, + 0x00108181, + 0xb0709180, + 0x60796063, + 0x6656c030, + 0xc282c1e1, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0x7830688a, + 0x78409ab0, + 0x78509ac0, + 0xc4829ad0, + 0x1820c5a0, + 0x1203409d, + 0x16126e23, + 0x7870689a, + 0x607997e0, + 0xb1087276, + 0xb0f3b100, + 0xb0d8b0f1, + 0xb1087100, + 0xb200a0d8, + 0x87e0b760, + 0xb0f19780, + 0x7100b0c1, + 0xb0f17276, + 0xb012a0c1, + 0xb013b002, + 0xb484b003, + 0xb101b0d1, + 0x7100722c, + 0x8140b101, + 0x06f03940, + 0x06f38143, + 0x65b18161, + 0x1a133911, + 0x68c04cc3, + 0x22f08140, + 0x814044bd, + 0x16103980, + 0x85e11203, + 0x1a111403, + 0x44d01e01, + 0x1c13c211, + 0xc31148fa, + 0x48eb1c13, + 0x10301813, + 0x1ef08451, + 0xc10040e5, + 0x1a101830, + 0x68e23911, + 0x65b11030, + 0x68e53911, + 0x12f08461, + 0xc21160f7, + 0x10301813, + 0x1ef08461, + 0xc10040f7, + 0x1a101830, + 0x68f43911, + 0x65b11030, + 0x68f73911, + 0x12f08431, + 0x391165b1, + 0x844168fc, + 0x65b112f0, + 0x69013911, + 0x81a1721c, + 0x81e065a4, + 0x41052220, + 0xc040a0d1, + 0xc0309780, + 0xb0c19760, + 0x7100b0f1, + 0xa0c1b0f1, + 0x72487276, + 0xa002a003, + 0x73057248, + 0x73767306, + 0xa2007276, + 0x9010c7c0, + 0xb0066079, + 0xb004b016, + 0xb002b014, + 0x7810b012, + 0x90509030, + 0x90407820, + 0xb2059060, + 0x83038ae2, + 0x65ba9302, + 0xb064857f, + 0xc00bc00c, + 0xb072b011, + 0xa0c0a0c1, + 0xb0e6b116, + 0x22d18ab1, + 0xb0f24141, + 0x7100b0c2, + 0xa760b073, + 0xb7607378, + 0x226080b0, + 0x661c454b, + 0xb88f6141, + 0x18f08960, + 0x100f9550, + 0xa0c2720e, + 0xb0d7b201, + 0x7100b107, + 0x8ad0b041, + 0x415d22e0, + 0x22208210, + 0xb04d4536, + 0xc300b06d, + 0xb2019070, + 0x6656c040, + 0x7000a044, + 0x8180b88c, + 0x392489a4, + 0x00043184, + 0xc0509184, + 0x73766656, + 0x72487276, + 0x72027206, + 0x73057204, + 0x60797306, + 0xb32d721b, + 0x6656c060, + 0x6521b0f8, + 0xb107b0d7, + 0xb1077100, + 0xb1077100, + 0xb1077100, + 0xb1077100, + 0x8090120a, + 0x44632200, + 0x161a6605, + 0x1e0b815b, + 0x85524189, + 0x9862d070, + 0x1cba6656, + 0x18ab4da2, + 0x499e1efb, + 0x1af010b0, + 0x699c6605, + 0xc0f0a205, + 0x69a06605, + 0x6166a0d7, + 0x45a82201, + 0x61a913f2, + 0x92c21212, + 0x710085e2, + 0x1a12b101, + 0x45ab1e02, + 0x22017000, + 0x13f245b5, + 0x121261b6, + 0x710092c2, + 0x7000b101, + 0x39838143, + 0x94732a73, + 0x1a1085e0, + 0x120f1613, + 0x69c2143f, + 0xc200120b, + 0x41c91c0f, + 0x791b61cb, + 0xc40b61cf, + 0x318b18fb, + 0x8400313b, + 0x04107941, + 0x940000b0, + 0xa405b404, + 0x1e4185e1, + 0x1e3141e9, + 0x841041e1, + 0x31103180, + 0x94203980, + 0x841061ee, + 0x39803180, + 0x31101001, + 0x94201410, + 0x841061ee, + 0x39803180, + 0x94203120, + 0x84301201, + 0x87d097c0, + 0x84401401, + 0x87d097c0, + 0xc1001401, + 0x31111801, + 0x70009571, + 0x22011202, + 0x3a324201, + 0x38326202, + 0x69fd3911, + 0x85e37000, + 0x71001202, + 0xb107b88d, + 0x31818b11, + 0x14123d81, + 0x31818b21, + 0x14123d81, + 0x1e031a13, + 0x22f24607, + 0x12124619, + 0x1202621a, + 0x70009192, + 0x22b08ab0, + 0x1e3b4622, + 0x62244654, + 0x46541e7b, + 0xb889c00b, + 0x31808940, + 0x16103d80, + 0x140c3d30, + 0x226080b0, + 0x70004230, + 0x39838ab3, + 0x8ab106f3, + 0x0401cff0, + 0x1c1c3031, + 0x12004e4c, + 0x1c0c1810, + 0x80b04a4e, + 0x42412260, + 0x10c27000, + 0x3c321612, + 0x83208ae1, + 0x42502210, + 0x93016252, + 0x7000b0f2, + 0x623d101c, + 0x623d100c, + 0x62491821, + 0x62491421, + 0x624a161b, + 0x88409850, + 0x46572200, + 0x7000b830 +}; + +PATCH_FUN_SPEC void rf_patch_mce_brepeat(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 302; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchBrepeatMce[i]; + } +#else + const uint32_t *pS = patchBrepeatMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 37; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk.h new file mode 100644 index 0000000..9092ccb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk.h @@ -0,0 +1,567 @@ +/****************************************************************************** +* Filename: rf_patch_mce_genfsk.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Generic FSK +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_GENFSK_H +#define _RF_PATCH_MCE_GENFSK_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchGenfskMce[460] = { + 0x2fcf602b, + 0x030c3f9d, + 0x070c680a, + 0xfff0003f, + 0xff0000ff, + 0x00030006, + 0x3d1f0007, + 0x00000000, + 0x000f0400, + 0x03870000, + 0x40f4000b, + 0x80000043, + 0x06708082, + 0x091e0000, + 0x00540510, + 0x02000005, + 0x00613e10, + 0x002f0000, + 0x027f3030, + 0x00000000, + 0xaa000000, + 0x72200000, + 0xa32d7248, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72767376, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720c9001, + 0x720e720d, + 0x7100b0c0, + 0xa0c0b0f0, + 0x81327218, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x60696068, + 0x635360e5, + 0x60686068, + 0x60686068, + 0x60696068, + 0x635360e5, + 0x60686068, + 0x60686068, + 0x72201210, + 0x7310730f, + 0x81817311, + 0x91800010, + 0x6040b070, + 0xc030605e, + 0xc0b16792, + 0xc470c282, + 0x6f131820, + 0x16116e23, + 0x686f1612, + 0x9ab07830, + 0x9ac07840, + 0x9ad07850, + 0xc5a0c482, + 0x40821820, + 0x6e231203, + 0x687f1612, + 0x97e078a0, + 0x7276605e, + 0x94908160, + 0x39808140, + 0x10012a70, + 0x84321611, + 0xc0f38444, + 0xc200c0f5, + 0x40aa1c01, + 0x1c10c100, + 0x4ca240a0, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60aa689d, + 0x60aa13f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68a83914, + 0x7100b0d8, + 0xa0d8b108, + 0xb760b200, + 0x978087e0, + 0xb0c1b0f1, + 0xb0027100, + 0xb0f1b012, + 0x7276a0c1, + 0xb003b480, + 0x7229b013, + 0x7100b0d0, + 0x8140b100, + 0x71009290, + 0x8140b100, + 0x44c322f0, + 0x1c0313f0, + 0x929340cf, + 0x71009492, + 0x9295b100, + 0x71009494, + 0xb0d0b100, + 0x7000a480, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0xa200a002, + 0x730f7000, + 0xc0407310, + 0xc1006792, + 0x648591c0, + 0xb0f3b483, + 0x7100b0c3, + 0x64d6a0c3, + 0xb006605e, + 0xb004b016, + 0xb002b014, + 0x8400b012, + 0x04207862, + 0x39838143, + 0x94732a73, + 0x1832c1f2, + 0x10213162, + 0x00123151, + 0x94000020, + 0x16101030, + 0x31211001, + 0x22103930, + 0x12204110, + 0x10033150, + 0x00103180, + 0x93501630, + 0x12041202, + 0x41232273, + 0x97c08430, + 0x1a8287d2, + 0x97c08450, + 0x1a8487d4, + 0x22636125, + 0x84404130, + 0x87d097c0, + 0x14021a80, + 0x97c08460, + 0x1a8087d0, + 0x613c1404, + 0x78918440, + 0x97c00410, + 0x1a4287d2, + 0x78918460, + 0x97c00410, + 0x1a4487d4, + 0x31543152, + 0x06333963, + 0x38321613, + 0x31823834, + 0x31843982, + 0x95720042, + 0x90307810, + 0x78209050, + 0x90609040, + 0x8ae2b205, + 0x93028303, + 0xc00bc00c, + 0x31808140, + 0x39403980, + 0xc0f38141, + 0xc0140431, + 0xc0021441, + 0x695e1412, + 0x847d3122, + 0x140dc010, + 0x142d312d, + 0x318e8ace, + 0x397e311e, + 0x31498ac9, + 0x39493979, + 0x109a3129, + 0x720d720c, + 0xb101720e, + 0x7100b0d1, + 0xa0d1b072, + 0xb06ea04e, + 0xb06cb011, + 0x978ab089, + 0xb7647276, + 0xc662a764, + 0xc04f9762, + 0x8ab166d4, + 0x458c22f1, + 0x22f18ad1, + 0x6232458c, + 0xb0737100, + 0x80b7b760, + 0x45c32207, + 0x8ab1a760, + 0x419d22f1, + 0x419d2237, + 0x80b0b113, + 0x45982230, + 0x22e161ab, + 0x809041b0, + 0x41b02250, + 0x8210b0f5, + 0x418c2220, + 0xb7649789, + 0xb0f6a764, + 0x978d618c, + 0xa764b764, + 0x618cb0f6, + 0x22f08ad0, + 0x223741bc, + 0xb07541bc, + 0x80b0b113, + 0x45b62230, + 0x618cb087, + 0x431722d1, + 0x22208090, + 0x669a4317, + 0x978f618c, + 0x8410c7f3, + 0x39803180, + 0x00303183, + 0xb0879410, + 0xb0f2a0e3, + 0xb0f5a0c2, + 0xb0f1a0c5, + 0xa0c6b0c1, + 0xb113b110, + 0x220080b0, + 0x223045d4, + 0x710045d4, + 0x97801260, + 0xb88fb0f1, + 0x85708961, + 0x95511801, + 0x8a718a60, + 0xa487a488, + 0x1801c022, + 0x4df41c21, + 0x49f21412, + 0x1c0161f5, + 0x4df441f5, + 0x61f5b487, + 0xb041b488, + 0x8ad0b061, + 0x41fd22e0, + 0x22208210, + 0x71004570, + 0xb06eb04e, + 0x220180b1, + 0x2231468c, + 0x7276468c, + 0x8471b0f6, + 0xc2603121, + 0x97801410, + 0x9760c7e0, + 0x9760c6f0, + 0xb0c6b0f6, + 0xb7b0a0c1, + 0x8a748a63, + 0x8a948a83, + 0x80b17100, + 0x468c2201, + 0x468c2231, + 0x22c08ab0, + 0x89914624, + 0x41702201, + 0xc00081c1, + 0x847091c0, + 0x6a2881a2, + 0xc30091c1, + 0xb2019070, + 0xa0e3a0e0, + 0x7000a044, + 0xb0737100, + 0x80b7b760, + 0x46512207, + 0x466f2237, + 0x8ab1a760, + 0x424a22e1, + 0x22508090, + 0xb0f5424a, + 0x22208210, + 0x978d4232, + 0xa764b764, + 0x6232b0f6, + 0x431722d1, + 0x22208090, + 0x669a4317, + 0x978f6232, + 0xa0c2b0f2, + 0xa0c5b0f5, + 0xb0c1b0f1, + 0xb110a0c6, + 0x80b0b113, + 0x46592200, + 0x46592230, + 0x12607100, + 0xb0f19780, + 0x8961b88f, + 0x31808570, + 0x18013d80, + 0x8a609551, + 0xa1828a71, + 0x978f61e6, + 0xa0c2b0f2, + 0xa0c5b0f5, + 0xb0c1b0f1, + 0xb110a0c6, + 0x80b0b113, + 0x46772200, + 0x46772230, + 0x12607100, + 0xb0f19780, + 0x8961b88f, + 0x3d808570, + 0x95511801, + 0x8a918a80, + 0x61e6b182, + 0xa760b073, + 0xa7b0b760, + 0xa04eb072, + 0xb011b06e, + 0x22f08ab0, + 0x220145c3, + 0x626f4651, + 0x22b08ab0, + 0x1e3b46a0, + 0x62a246d2, + 0x46d21e7b, + 0xb889c00b, + 0x31808940, + 0x16103d80, + 0x140c3d30, + 0x220080b0, + 0x700042ae, + 0x39838ab3, + 0x8ab106f3, + 0x0401cff0, + 0x1c1c3031, + 0x12004eca, + 0x1c0c1810, + 0x80b04acc, + 0x42bf2200, + 0x10c27000, + 0x3c321612, + 0x83208ae1, + 0x42ce2210, + 0x930162d0, + 0x7000b0f2, + 0x62bb101c, + 0x62bb100c, + 0x62c71821, + 0x62c71421, + 0x62c8161b, + 0xb0f1b0f6, + 0xb113b110, + 0xb0f2b0f5, + 0x720d720c, + 0xb0e0720e, + 0x8ab2b0e3, + 0x42e522f2, + 0xb763b0c6, + 0x8ad062e8, + 0x430822f0, + 0xa404b405, + 0xa429b428, + 0x3180caa0, + 0x0001caa1, + 0x94619451, + 0x31838ad3, + 0x84103983, + 0x39803180, + 0x00303183, + 0x84009410, + 0x39503150, + 0x39838ad3, + 0xc1f406f3, + 0x31841834, + 0x00403134, + 0xb0899400, + 0x431222e2, + 0x394a8aca, + 0x312a398a, + 0xb0c5978a, + 0xb763b0c6, + 0x22d28ab2, + 0xb0c24316, + 0xb20f7000, + 0xa0e3a0e0, + 0xb764978e, + 0xb0f6a764, + 0xb113b110, + 0x22f08210, + 0xb0f54320, + 0xa0048002, + 0xa001a006, + 0x72047203, + 0x6792c050, + 0xb7647100, + 0xb0c5b0f6, + 0x7100a20f, + 0xa0c5b0f5, + 0x90307810, + 0x78209002, + 0x90609040, + 0xa20fb072, + 0x978a66d4, + 0xb0f6a764, + 0xb88c6185, + 0x89a48180, + 0x31843924, + 0x91840004, + 0x6792c060, + 0x72767376, + 0x72067248, + 0x72047202, + 0x73067305, + 0x1300605e, + 0xb32d91b0, + 0x6792c070, + 0x64f3b0f8, + 0x1a101200, + 0xc3809780, + 0xc2809760, + 0xa0c19760, + 0x8090b0c6, + 0x44402200, + 0x1e048154, + 0x97844363, + 0x8552b0f6, + 0x9862d080, + 0x89916792, + 0x43792211, + 0x8a938a82, + 0x9862e090, + 0x67929873, + 0x8a62637f, + 0xe0a08a73, + 0x98739862, + 0x87906792, + 0x1c018781, + 0x18014b8f, + 0x4b8d1ef1, + 0x1af18781, + 0x71009781, + 0x16f1b0f6, + 0xa2059781, + 0xb0f67100, + 0x6341a0c6, + 0x88409850, + 0x47932200, + 0x7000b830 +}; + +PATCH_FUN_SPEC void rf_patch_mce_genfsk(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 460; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchGenfskMce[i]; + } +#else + const uint32_t *pS = patchGenfskMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 57; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_ant_div_pqt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_ant_div_pqt.h new file mode 100644 index 0000000..0c3567a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_ant_div_pqt.h @@ -0,0 +1,528 @@ +/****************************************************************************** +* Filename: rf_patch_mce_genfsk_ant_div_pqt.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Generic FSK PQT based antenna diversity +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_GENFSK_ANT_DIV_PQT_H +#define _RF_PATCH_MCE_GENFSK_ANT_DIV_PQT_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchGenfskAntDivPqtMce[415] = { + 0x2fcf602d, + 0x00003f9d, + 0x470a031a, + 0x000f0387, + 0xff00ffcf, + 0x80000006, + 0x00070003, + 0x00003d1f, + 0x04000000, + 0x0000000f, + 0x000b0387, + 0x004340f4, + 0x80828000, + 0x00000670, + 0x0510091e, + 0x00050054, + 0x3e100200, + 0x00000061, + 0x0c30002f, + 0x0000017f, + 0xaaaa0000, + 0x0000aaaa, + 0x72200000, + 0xa32d7248, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72767376, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720c9001, + 0x720e720d, + 0x7100b0c0, + 0xa0c0b0f0, + 0x81327218, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x606c606a, + 0x62cf60e4, + 0x606a606a, + 0x606b606a, + 0x606c606a, + 0x62cf60e4, + 0x606a606a, + 0x606b606a, + 0x72201210, + 0x7310730f, + 0x81817311, + 0x91800010, + 0x6042b070, + 0x60606060, + 0x6738c030, + 0xc282c0c1, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0x78306872, + 0x78409ab0, + 0x78509ac0, + 0x78609ad0, + 0xc4829ae0, + 0x1820c5a0, + 0x12034087, + 0x16126e23, + 0x60606884, + 0x94908160, + 0x39808140, + 0x10012a70, + 0x84321611, + 0xc0f38444, + 0xc200c0f5, + 0x40ac1c01, + 0x1c10c100, + 0x4ca440a2, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60ac689f, + 0x60ac13f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68aa3914, + 0x7100b0d8, + 0xa0d8b108, + 0x85e0b005, + 0x44b51e00, + 0xb24060b7, + 0xb200a005, + 0xb003b480, + 0xb002b013, + 0x7229b012, + 0x7100b0d0, + 0x8140b100, + 0x71009290, + 0x8140b100, + 0x44c322f0, + 0x1c0313f0, + 0x929340cf, + 0x71009492, + 0x9295b100, + 0x71009494, + 0xb0d0b100, + 0x7000a480, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0x7000a002, + 0x7310730f, + 0xd04085e1, + 0x67389861, + 0x91c0c100, + 0xb4836488, + 0xb0c3b0f3, + 0xa0c37100, + 0x606064d6, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x78728400, + 0x81430420, + 0x2a733983, + 0xc1f29473, + 0x31621832, + 0x31511021, + 0x00200012, + 0x3142c022, + 0x94000020, + 0x16101030, + 0x31211001, + 0x22103930, + 0x12204114, + 0x10033150, + 0x00103180, + 0x93501630, + 0x12041202, + 0x41272273, + 0x97c08430, + 0x1a8287d2, + 0x97c08450, + 0x1a8487d4, + 0x22636129, + 0x84404134, + 0x87d097c0, + 0x14021a80, + 0x97c08460, + 0x1a8087d0, + 0x61401404, + 0x78918440, + 0x97c00410, + 0x1a4287d2, + 0x78918460, + 0x97c00410, + 0x1a4487d4, + 0x31543152, + 0x06333963, + 0x38321613, + 0x31823834, + 0x31843982, + 0x95720042, + 0x90307810, + 0x78209050, + 0x90609040, + 0x31808200, + 0x78b13980, + 0x92001410, + 0x8ae2b205, + 0x93028303, + 0x31808140, + 0x39403980, + 0xc0f38141, + 0xc0140431, + 0xc0021441, + 0x69661412, + 0x847d3122, + 0x8ac0161d, + 0x39803180, + 0x312d140d, + 0xc200142d, + 0x180d3120, + 0xa04eb072, + 0xb011b06e, + 0x7276b06c, + 0xa764b764, + 0x9762c662, + 0x7255c04f, + 0xb0f1b0f6, + 0xb113b110, + 0x720d720c, + 0xa0e0720e, + 0xb405b0e3, + 0x8ad3a404, + 0x39833183, + 0x31808410, + 0x31833980, + 0x94100030, + 0x31508400, + 0x8ad33950, + 0x06f33983, + 0x1834c1f4, + 0x31343184, + 0x94000040, + 0xa0e0b089, + 0xb0c1a0e3, + 0xb228b005, + 0x84017880, + 0xc0200401, + 0x00013140, + 0x72769401, + 0x9760c030, + 0x821a6702, + 0x1a1078a0, + 0xa7609780, + 0xb113b760, + 0x672cb0f1, + 0x8ac07100, + 0x97803980, + 0xb760a760, + 0x80b0b0f1, + 0x45cd2230, + 0x10a0b064, + 0x06103920, + 0x45cb1e00, + 0x7100b069, + 0x8ad061a6, + 0x41dc22e0, + 0x392010a0, + 0x1e000610, + 0x10a345dc, + 0x3d833143, + 0x16118611, + 0x61cb9611, + 0x314310a3, + 0xd0503d83, + 0x67389863, + 0x8ac0b064, + 0x78a13980, + 0x97801410, + 0xb760a760, + 0xb0f1b113, + 0x7100672c, + 0x223080b0, + 0x61fd45f2, + 0x31428212, + 0xd0603d82, + 0x67389862, + 0x1c23671b, + 0x67024a16, + 0x67026211, + 0x31428212, + 0xd0703d82, + 0x67389862, + 0x78a0671b, + 0x97801a10, + 0xb760a760, + 0x7100b0f1, + 0xc012b069, + 0x31823172, + 0x10203d82, + 0x10031032, + 0x6217670a, + 0x7276670a, + 0x9760c660, + 0x7880978d, + 0x04018401, + 0xc0509401, + 0xa76393b0, + 0xb0e0b763, + 0xb110a0e3, + 0xb0f6b113, + 0xa0c1b0c6, + 0xb064b0f1, + 0xb0737100, + 0xb0c1879c, + 0xa760a0c6, + 0x80b0b760, + 0x463d2200, + 0x16118601, + 0xd0809601, + 0x67389861, + 0x978f6174, + 0xb0f1a0e3, + 0xa0c6b0c1, + 0x80b0b110, + 0x46422200, + 0x12607100, + 0xb0f19780, + 0x8961b88f, + 0x18018570, + 0x8a609551, + 0xa4888a71, + 0xc022a487, + 0x1c211801, + 0x14124e5f, + 0x62604a5d, + 0x42601c01, + 0xb4874e5f, + 0xb4886260, + 0xb061b041, + 0xb04e7100, + 0x80b1b06e, + 0x46912201, + 0xb0f67276, + 0x31218471, + 0x1410c260, + 0xc7e09780, + 0xc6f09760, + 0xb0f69760, + 0xa0c1b0c6, + 0x8a63b7b0, + 0x71008a74, + 0x220180b1, + 0x8ab04691, + 0x468422c0, + 0x22018991, + 0x62914684, + 0xc00081c1, + 0x847091c0, + 0x6a8881a2, + 0xc30091c1, + 0xb2019070, + 0xa044a0e0, + 0x87907000, + 0xc360140c, + 0x1cdc180c, + 0x86014a9e, + 0x96011611, + 0x9861d090, + 0x61746738, + 0xa760b073, + 0xa7b0b760, + 0xa04eb072, + 0xb011b06e, + 0xb88c623d, + 0x89a48180, + 0x31843924, + 0x91840004, + 0x860385e4, + 0x9864e0a0, + 0x67389873, + 0x46ba1e04, + 0x16108720, + 0x62bd9720, + 0x16108730, + 0x85f29730, + 0x3d821023, + 0x3d833183, + 0x986ce0b0, + 0x6738987d, + 0x72767376, + 0x72067248, + 0x72047202, + 0x73067305, + 0x13006060, + 0xb32d91b0, + 0x6738c0c0, + 0x93b0c030, + 0x64f4b0f8, + 0x1a101200, + 0xc3809780, + 0xc2809760, + 0xa0c19760, + 0x8090b0c6, + 0x44422200, + 0x1e048154, + 0x978442e1, + 0x8552b0f6, + 0x9862d0d0, + 0x8a626738, + 0x87908a73, + 0x1c018781, + 0x18014aff, + 0x4afd1ef1, + 0x1af18781, + 0x71009781, + 0x16f1b0f6, + 0xa2059781, + 0xb0f67100, + 0x62a7a0c6, + 0x22508000, + 0xb0054707, + 0xb2406309, + 0x7000a005, + 0x39833183, + 0x00233182, + 0xa5e095f3, + 0x22548004, + 0xb5e0471a, + 0x102385f2, + 0x31833982, + 0x95f20032, + 0x82007000, + 0x39803180, + 0x4f221c23, + 0x63231021, + 0x31811031, + 0x92001410, + 0x8210a205, + 0x47272210, + 0x7000b205, + 0x8210a205, + 0x472d2210, + 0x31808200, + 0x78b13980, + 0x92001410, + 0x7000b205, + 0x88409850, + 0x47392200, + 0x7000b830 +}; + +PATCH_FUN_SPEC void rf_patch_mce_genfsk_ant_div_pqt(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 415; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchGenfskAntDivPqtMce[i]; + } +#else + const uint32_t *pS = patchGenfskAntDivPqtMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 51; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_fec_cc1101.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_fec_cc1101.h new file mode 100644 index 0000000..6b5ebbb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_fec_cc1101.h @@ -0,0 +1,584 @@ +/****************************************************************************** +* Filename: rf_patch_mce_genfsk_fec_cc1101.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Generic FSK (with CC1101-compatible FEC and interleaver) +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_GENFSK_FEC_CC1101_H +#define _RF_PATCH_MCE_GENFSK_FEC_CC1101_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchGenfskFecMce[471] = { + 0x2fcf6054, + 0x030c0f9d, + 0x070c680a, + 0xff00003f, + 0x07c0d0d0, + 0x130007e0, + 0x50433221, + 0x10037162, + 0x53403122, + 0x00017261, + 0x01000010, + 0x00021000, + 0x02000020, + 0x00042000, + 0x04000040, + 0x00084000, + 0x08000080, + 0x00018000, + 0x00200018, + 0x00200003, + 0x00290011, + 0x0029000a, + 0x00320003, + 0x00320018, + 0x003b000a, + 0x003b0011, + 0x00070003, + 0x00003d1f, + 0x04000000, + 0x0000000f, + 0x000b0387, + 0x004340f4, + 0x80828000, + 0x00000670, + 0x0510091e, + 0x00050054, + 0x3e100200, + 0x00000061, + 0x3030002f, + 0x0000027f, + 0x00000000, + 0x0000aa00, + 0x72487220, + 0x7303a32d, + 0x72037305, + 0x73067304, + 0x73767204, + 0xc7c07276, + 0x00018001, + 0x90109001, + 0x90010801, + 0x720d720c, + 0xb0c0720e, + 0xb0f07100, + 0x7218a0c0, + 0x10208132, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60896c01, + 0x60f0608c, + 0x6089631d, + 0x60896089, + 0x1210608a, + 0x730f7220, + 0x73117310, + 0x00108181, + 0xb0709180, + 0x607f6069, + 0x607f6400, + 0x67a8c030, + 0xc282c341, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0x78306892, + 0x78409ab0, + 0x78509ac0, + 0x83009ad0, + 0xc4829ae0, + 0x1820c5a0, + 0x120340a7, + 0x16126e23, + 0x607f68a4, + 0x94908160, + 0x39808140, + 0x10012a70, + 0x84321611, + 0xc0f38444, + 0xc200c0f5, + 0x40cc1c01, + 0x1c10c100, + 0x4cc440c2, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60cc68bf, + 0x60cc13f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68ca3914, + 0x7100b0d8, + 0xa0d8b108, + 0xb480b200, + 0xb013b003, + 0xb012b002, + 0xb0d07229, + 0xb1007100, + 0x92908140, + 0xb1007100, + 0x22f08140, + 0x13f044dc, + 0x40e81c03, + 0x94929293, + 0xb1007100, + 0x94949295, + 0x71006536, + 0xb0d0b100, + 0x7000a480, + 0x7310730f, + 0x67a8c040, + 0x91c0c000, + 0xc0b7c136, + 0xc009c008, + 0xc00bc00a, + 0xc00dc00c, + 0xc10e788f, + 0x9760c030, + 0x9780c000, + 0xb48464a8, + 0x10acc009, + 0x10f010bd, + 0x1e003980, + 0x81e0411c, + 0x41122210, + 0x611581a0, + 0x061010f0, + 0x6523391f, + 0x654c653c, + 0x1ce91619, + 0x6106450d, + 0x654c653c, + 0x1ce91619, + 0x6556451c, + 0x1081607f, + 0x6f121471, + 0x41292200, + 0x10233982, + 0x311a0613, + 0x1023003a, + 0x06133913, + 0x003b311b, + 0x39481028, + 0x700006f8, + 0x652381a0, + 0x1ce91619, + 0x70004536, + 0x14921062, + 0x10c16f23, + 0x41440431, + 0x61451210, + 0x10d113f0, + 0x414a0431, + 0x614b1211, + 0x700013f1, + 0xb10192c1, + 0x7100b0d1, + 0x92c0b101, + 0xb1017100, + 0x7000a0d1, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0x7000a002, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x78628400, + 0x81430420, + 0x2a733983, + 0xc1f29473, + 0x31621832, + 0x31511021, + 0x00200012, + 0x10309400, + 0x39301610, + 0x417f2210, + 0x31501220, + 0x31801003, + 0x93501670, + 0x12041202, + 0x41912273, + 0x97c08430, + 0x1a8287d2, + 0x97c08450, + 0x1a8487d4, + 0x22636193, + 0x8440419e, + 0x87d097c0, + 0x14021a80, + 0x97c08460, + 0x1a8087d0, + 0x61aa1404, + 0x78718440, + 0x97c00410, + 0x1a4287d2, + 0x78718460, + 0x97c00410, + 0x1a4487d4, + 0x31543152, + 0x06333963, + 0x38321613, + 0x31823834, + 0x31843982, + 0x95720042, + 0x90307810, + 0x78209050, + 0x90609040, + 0x8ae2b205, + 0x93028303, + 0xc00bc00c, + 0x31808140, + 0x39403980, + 0xc0f38141, + 0xc0140431, + 0xc0021441, + 0x69cc1412, + 0x847d3122, + 0x140dc010, + 0x142d312d, + 0x318e8ace, + 0x397e311e, + 0x31498ac9, + 0x39493979, + 0x109a3129, + 0x720d720c, + 0xb101720e, + 0x7100b0d1, + 0xa0d1b072, + 0xb06ea04e, + 0xb06cb011, + 0x7276978a, + 0xa764b764, + 0x9762c662, + 0xc088c04f, + 0x8ab166b0, + 0x45fa22f1, + 0x22f18ad1, + 0x626445fa, + 0xb0737100, + 0x80b7b760, + 0x46312207, + 0x8ab1a760, + 0x420b22f1, + 0x420b2237, + 0x80b0b113, + 0x46062230, + 0x22e16219, + 0x8090421e, + 0x421e2250, + 0x8210b0f5, + 0x41fa2220, + 0xb7649789, + 0xb0f6a764, + 0x978d61fa, + 0xa764b764, + 0x61fab0f6, + 0x22f08ad0, + 0x2237422a, + 0xb075422a, + 0x80b0b113, + 0x46242230, + 0x61fab087, + 0x42f322d1, + 0x22208090, + 0x66ae42f3, + 0x978f61fa, + 0xa0e3a0e0, + 0xa0c5a0c2, + 0xb0c1b0f1, + 0x7100a0c6, + 0xb0f19788, + 0x8961b88f, + 0x18018570, + 0x8a609551, + 0xa4888a71, + 0xc062a487, + 0x1c211801, + 0x14124e51, + 0x62524a4f, + 0x42521c01, + 0xb4874e51, + 0xb4886252, + 0xb041b061, + 0x22e08ad0, + 0x8210425a, + 0x45de2220, + 0xb04d7100, + 0xb04fb06d, + 0xb074b06f, + 0x8a73b201, + 0x70008552, + 0xb0737100, + 0x80b7b760, + 0x46832207, + 0x46992237, + 0x8ab1a760, + 0x427c22e1, + 0x22508090, + 0xb0f5427c, + 0x22208210, + 0x978d4264, + 0xa764b764, + 0x6264b0f6, + 0x42f322d1, + 0x22208090, + 0x66ae42f3, + 0x978f6264, + 0xa0e3a0e0, + 0xa0c5a0c2, + 0xb0c1b0f1, + 0x7100a0c6, + 0xb0f19788, + 0x8961b88f, + 0x31808570, + 0x18013d80, + 0x8a609551, + 0xa1828a71, + 0x978f6243, + 0xa0e3a0e0, + 0xa0c5a0c2, + 0xb0c1b0f1, + 0x7100a0c6, + 0xb0f19788, + 0x8961b88f, + 0x3d808570, + 0x95511801, + 0x8a918a80, + 0x6243b182, + 0x7000b0f2, + 0xb0f1b0f6, + 0xb113b110, + 0xb0f2b0f5, + 0x720d720c, + 0xb0e0720e, + 0x8ab2b0e3, + 0x42c122f2, + 0xb763b0c6, + 0x8ad062c4, + 0x42e422f0, + 0xa404b405, + 0xa429b428, + 0x3180caa0, + 0x0001caa1, + 0x94619451, + 0x31838ad3, + 0x84103983, + 0x39803180, + 0x00303183, + 0x84009410, + 0x39503150, + 0x39838ad3, + 0xc1f406f3, + 0x31841834, + 0x00403134, + 0xb0899400, + 0x42ee22e2, + 0x394a8aca, + 0x312a398a, + 0xb0c5978a, + 0xb763b0c6, + 0x22d28ab2, + 0xb0c242f2, + 0xb20f7000, + 0xa0e3a0e0, + 0xb764978e, + 0xb0f6a764, + 0xb113b110, + 0x22f08210, + 0xb0f542fc, + 0xa0048002, + 0xa001a006, + 0x72047203, + 0x67a8c050, + 0xb7647100, + 0xb0c5b0f6, + 0x7100a20f, + 0xa0c5b0f5, + 0x90307810, + 0x78209002, + 0x90609040, + 0xa20fb072, + 0x978a66b0, + 0xb0f6a764, + 0x120061f3, + 0xc06091b0, + 0x7a3067a8, + 0xc10095a0, + 0xc622c241, + 0x6e236f13, + 0x16121611, + 0xb0f86b26, + 0xa0c16564, + 0xb0d7b107, + 0x9760c070, + 0x9780c070, + 0x7100b107, + 0x7100b107, + 0xb107a0d7, + 0xc1071206, + 0xc00d78a8, + 0x31131063, + 0x677e1483, + 0x1c671616, + 0xc02f473e, + 0x78a97898, + 0xb04f120e, + 0x1206b06f, + 0x67a01060, + 0x31131013, + 0x67891493, + 0x31131063, + 0x677e1483, + 0x1c671616, + 0x0a1e474c, + 0x435f1e1e, + 0x78a97898, + 0x78a86361, + 0x162f7899, + 0x1e008150, + 0x3930434b, + 0x1cf01620, + 0x4f4b436a, + 0x10601206, + 0x101367a0, + 0x14933113, + 0x16166789, + 0x476b1c67, + 0x72036798, + 0x73057204, + 0xa0047306, + 0xc7c0a002, + 0x607f9010, + 0xb0c1b0f1, + 0xb0f17100, + 0x87f1a0c1, + 0x6e318802, + 0x6e321613, + 0x6d317000, + 0x95e16d31, + 0x6d311613, + 0x95f16d31, + 0x1efdb5b0, + 0x85d04b96, + 0x91900610, + 0x7000161d, + 0xb5b0c0f0, + 0x85d10a11, + 0x91910611, + 0x70006b99, + 0x06311001, + 0x39203121, + 0x12f10010, + 0x70001801, + 0x88409850, + 0x47a92200, + 0x7000b830 +}; + +PATCH_FUN_SPEC void rf_patch_mce_genfsk_fec_cc1101(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 471; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchGenfskFecMce[i]; + } +#else + const uint32_t *pS = patchGenfskFecMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 58; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genook.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genook.h new file mode 100644 index 0000000..58853c0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genook.h @@ -0,0 +1,576 @@ +/****************************************************************************** +* Filename: rf_patch_mce_genook.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Generic OOK +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_GENOOK_H +#define _RF_PATCH_MCE_GENOOK_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchGenookMce[463] = { + 0x00006030, + 0x01952fcf, + 0x7fff0001, + 0x030c003f, + 0x070c680a, + 0x00010000, + 0xaaaa000f, + 0x00fc00aa, + 0x00170003, + 0x0000001f, + 0x04000000, + 0x0000000f, + 0x00020387, + 0x00434074, + 0x20028000, + 0x000006f0, + 0x0500091e, + 0x00000054, + 0x50140000, + 0x00000050, + 0x7f30000f, + 0x0000007f, + 0x00000000, + 0x00000000, + 0x72487220, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72767376, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720c9001, + 0x720e720d, + 0x7100b0c0, + 0xa0c0b0f0, + 0x81327218, + 0x9862d030, + 0x10206798, + 0x1e000670, + 0x1e104074, + 0x1e204075, + 0x3982405f, + 0x163206f2, + 0x14211101, + 0x61826c01, + 0x63186182, + 0x3982632e, + 0x16323942, + 0x14211101, + 0x60e36c01, + 0x610d60e3, + 0x606b1220, + 0x72201210, + 0x7310730f, + 0x81817311, + 0x91800010, + 0x6044b070, + 0xc101606a, + 0xc470c282, + 0x6f131820, + 0x16116e23, + 0x68791612, + 0x9ab07870, + 0x9ac07880, + 0x9ad07890, + 0x981078b0, + 0xc5a0c482, + 0x408e1820, + 0x6e231203, + 0x688b1612, + 0x9ae078a0, + 0x8160606a, + 0x81409490, + 0x2a703980, + 0x16111001, + 0x84448432, + 0xc0f5c0f3, + 0x1c01c200, + 0xc10040b5, + 0x40ab1c10, + 0x10134cad, + 0x18301803, + 0x1a101a13, + 0x68a83912, + 0x13f360b5, + 0x13f360b5, + 0xc1001015, + 0x1a151850, + 0x39141a10, + 0xb0d868b3, + 0xb1087100, + 0xb200a0d8, + 0xb012b002, + 0x22168216, + 0x814640bc, + 0x06f63d46, + 0x81408165, + 0x105106f0, + 0x65570611, + 0x68c53d15, + 0x22f08140, + 0x1a1644bf, + 0x8ae14cc2, + 0x9861d040, + 0x13f06798, + 0x40dc1c03, + 0x1021c0f0, + 0x65570611, + 0x68d73d12, + 0x1041c0f0, + 0x65570611, + 0x68dd3d14, + 0x72207000, + 0x7310730f, + 0x91c0c000, + 0xb0c1b0f1, + 0x9760c050, + 0x9780c010, + 0x6491c008, + 0x39838ad3, + 0x06133953, + 0x221081e0, + 0x81a14104, + 0x10170831, + 0x81306557, + 0x39403980, + 0x45031e10, + 0x0a111071, + 0x60f46557, + 0x65571201, + 0xa0c1b204, + 0xa0c3b0f1, + 0x6798c050, + 0x7220606a, + 0x7310730f, + 0x91c0c000, + 0xb0c1b0f1, + 0x9760c050, + 0x9780c010, + 0x8216b200, + 0x41192216, + 0xb012b002, + 0xc030c008, + 0x10a178ca, + 0x65570611, + 0x6921391a, + 0x78dac0f0, + 0x061110a1, + 0x391a6557, + 0xc0706928, + 0x10a178ea, + 0x65570611, + 0x692f391a, + 0x78fac090, + 0x061110a1, + 0x391a6557, + 0x8ad36936, + 0x39533983, + 0x81e00613, + 0x414c2210, + 0x0831c011, + 0x81a16557, + 0x65576793, + 0x0831c001, + 0x613f6557, + 0x6557c011, + 0x6557c001, + 0xa0c1b204, + 0xa0c3b0f1, + 0x6798c060, + 0xc029606a, + 0x455d2208, + 0x41732201, + 0x2201616c, + 0x8aef4573, + 0x416c22ff, + 0x31116578, + 0x39119201, + 0x80fe1018, + 0x456bc019, + 0x6173c029, + 0x7100b0f1, + 0x92013111, + 0x10183911, + 0xb0f1c019, + 0x1a197100, + 0x70004573, + 0x785f10f9, + 0x100004f9, + 0x10001000, + 0x1a191000, + 0x7000457b, + 0xc0706750, + 0x847d6798, + 0x140dc010, + 0x142d312d, + 0x318e8ace, + 0x397e311e, + 0x31498ac9, + 0x39493979, + 0x10903129, + 0x72769780, + 0xa764b764, + 0x9762c662, + 0xb012b002, + 0x986be080, + 0x6798987f, + 0x6699b485, + 0x8ab1a182, + 0x45aa22f1, + 0x22f18ad1, + 0x61df45aa, + 0x80b77100, + 0x45fd2207, + 0x22b08090, + 0x105441b6, + 0x662d858c, + 0x61aa668e, + 0x22f18ab1, + 0x223741c0, + 0xb11341c0, + 0x223080b0, + 0x61ce45bb, + 0x41d322e1, + 0x22508090, + 0xb0f541d3, + 0x22108210, + 0x978941aa, + 0xa764b764, + 0x61aab0f6, + 0xb764978d, + 0xb0f6a764, + 0x8ad061aa, + 0x42da22f0, + 0x42da2237, + 0xb113b075, + 0x223080b0, + 0xb08745d9, + 0x710061aa, + 0x220780b7, + 0x223745fd, + 0x809045fc, + 0x41ee22b0, + 0x858c1054, + 0x668e662d, + 0x8ab161df, + 0x41df22e1, + 0x22508090, + 0xb0f541df, + 0x22108210, + 0x978d41df, + 0xa764b764, + 0x61dfb0f6, + 0xb110b182, + 0xb113a0e0, + 0xb074a0e3, + 0xa044b201, + 0x986ad090, + 0x10806798, + 0x1c0a1610, + 0x1cfa4a0e, + 0x66704e0e, + 0xc00ec00f, + 0x80907100, + 0x44442200, + 0x1054858c, + 0x668e662d, + 0x39808130, + 0x1e1006f0, + 0x667a461f, + 0x66646220, + 0x1e008150, + 0x1a104210, + 0x4e101cf0, + 0x62106228, + 0xb0f6a0c6, + 0xb0fba0cb, + 0xb8846306, + 0x881188c2, + 0x1e010631, + 0x1e21424a, + 0x1e31423c, + 0x10564243, + 0x39161426, + 0x624b1065, + 0x31261056, + 0x14261856, + 0x10653926, + 0x1056624b, + 0x18563136, + 0x39361426, + 0x624b1065, + 0x82121026, + 0x1c263922, + 0x18624e59, + 0x1c12c101, + 0x12014e57, + 0x31211821, + 0xcc016261, + 0x18266261, + 0x1c16c101, + 0x10614e60, + 0x62613121, + 0x9581c401, + 0x7000b0fb, + 0x466f1c8a, + 0x39208210, + 0x4e6c1c04, + 0x626dc001, + 0x9191c011, + 0x7000161f, + 0x39208210, + 0x4e761c04, + 0x6277c001, + 0x9191c011, + 0x7000c01f, + 0x468d1c8a, + 0x31808580, + 0x10013d80, + 0x10171870, + 0x468c1e1e, + 0x39703980, + 0x39818ad1, + 0x08103951, + 0x161f9190, + 0x70000a1e, + 0x10c08581, + 0x22700810, + 0x120a4295, + 0x1cba6298, + 0x161a4293, + 0xb0fb7000, + 0xb0f1b0f6, + 0xb113b110, + 0xb0f2b0f5, + 0x720d720c, + 0xb0cb720e, + 0xb0e3b0e0, + 0x22f28ab2, + 0xb0c642ac, + 0x62afb763, + 0x22f08ad0, + 0xb40542cf, + 0xa428a404, + 0xcaa0a429, + 0xcaa13180, + 0x94510001, + 0x8ad39461, + 0x39833183, + 0x31808410, + 0x31833980, + 0x94100030, + 0x31508400, + 0x8ad33950, + 0x06f33983, + 0x1834c1f4, + 0x31343184, + 0x94000040, + 0x22e2b089, + 0x8aca42d9, + 0x398a394a, + 0x978a312a, + 0xb0c6b0c5, + 0x7000b763, + 0xa0e0b20f, + 0xa0cba0e3, + 0xb764978e, + 0xb0f6a764, + 0xb113b110, + 0x8210b0fb, + 0x42e52200, + 0x8002b0f5, + 0xa006a004, + 0x7203a001, + 0xc0a07204, + 0x71006798, + 0xb0f6b764, + 0xa20fb0c5, + 0xb0f57100, + 0x7820a0c5, + 0x90029030, + 0x90407830, + 0xb0729060, + 0x6699a20f, + 0xa764978a, + 0x61a3b0f6, + 0x8180b88c, + 0x392489a4, + 0x00043184, + 0xc0b09184, + 0x73766798, + 0x72487276, + 0x72027206, + 0x73057204, + 0x606a7306, + 0xc0c06750, + 0xb0f86798, + 0xb0fbb0cb, + 0xb228b005, + 0xb0fb7100, + 0x22e08ad0, + 0x82104328, + 0x43202210, + 0x8580662d, + 0x0a103970, + 0x63206789, + 0xc0d06750, + 0xb0cb6798, + 0x120cb074, + 0x398e881e, + 0x433e1e0e, + 0x30e01210, + 0x71001a20, + 0x6b3b662d, + 0x8ad07100, + 0x434522e0, + 0x22108210, + 0x662d4336, + 0x0a113971, + 0x81549191, + 0x43361e04, + 0x1cc4161c, + 0x63364306, + 0x91b01200, + 0xb006b0f8, + 0xb004b016, + 0xb002b014, + 0x8400b012, + 0x04207862, + 0x39838143, + 0x94732a73, + 0x1832c1f2, + 0x10213162, + 0x00123151, + 0x94000020, + 0x90307820, + 0x78309050, + 0x90609040, + 0x8330c04b, + 0x06303930, + 0x43751e00, + 0x10b8300b, + 0x39181a1b, + 0x108fc00a, + 0xa203a204, + 0x22408330, + 0x165f4382, + 0x6386b204, + 0x43862230, + 0xb203163f, + 0xb072b205, + 0x22007000, + 0xb005478d, + 0x80006392, + 0x43922250, + 0xa005b240, + 0x82a27000, + 0x06123972, + 0x70000821, + 0x88409850, + 0x47992200, + 0x7000b830 +}; + +PATCH_FUN_SPEC void rf_patch_mce_genook(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 463; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchGenookMce[i]; + } +#else + const uint32_t *pS = patchGenookMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 57; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_ghs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_ghs.h new file mode 100644 index 0000000..0d0edc5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_ghs.h @@ -0,0 +1,410 @@ +/****************************************************************************** +* Filename: rf_patch_mce_ghs.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Generic 4FSK up to 1.5Mbps +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_GHS_H +#define _RF_PATCH_MCE_GHS_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchGhsMce[301] = { + 0x2fcf603c, + 0x00f03f9d, + 0x0f30003d, + 0x003f0ff0, + 0x0000ff00, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00070003, + 0x31fd31fd, + 0x04000000, + 0x001d000f, + 0x000b0387, + 0x004340f4, + 0x80828000, + 0x00000f90, + 0x0510091e, + 0x00050054, + 0x11010000, + 0x0000003c, + 0x3030002f, + 0x0000027f, + 0xd3910000, + 0x0000193d, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72487220, + 0x7303a32d, + 0x72037305, + 0x73067304, + 0x73767204, + 0xc7c07276, + 0x00018001, + 0x90109001, + 0x90010801, + 0x720d720c, + 0xb0c0720e, + 0xb0f07100, + 0x7218a0c0, + 0x10208132, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60796c01, + 0x60f4607c, + 0x607961da, + 0x60796079, + 0x6079607a, + 0x60f4607c, + 0x607961da, + 0x60796079, + 0x1210607a, + 0x730f7220, + 0x73117310, + 0x00108181, + 0xb0709180, + 0x606f6051, + 0x606f6646, + 0x663cc030, + 0xc282c141, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0x78306882, + 0x78409ac0, + 0xc4829ad0, + 0x1820c5a0, + 0x12034093, + 0x16126e23, + 0x83606890, + 0x606f97e0, + 0x94908160, + 0x39808140, + 0x10012a70, + 0x84321611, + 0xc0f38444, + 0xc200c0f5, + 0x40ba1c01, + 0x1c10c100, + 0x4cb240b0, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60ba68ad, + 0x60ba13f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68b83914, + 0x7100b0d8, + 0xa0d8b108, + 0xb760b200, + 0x97808ac0, + 0xb0c1b0f1, + 0xb0f17100, + 0x7276a0c1, + 0xb003b480, + 0xb002b013, + 0x7229b012, + 0x7100b0d0, + 0x8140b100, + 0x71009290, + 0x8140b100, + 0x44d322f0, + 0x1c0313f0, + 0x929340df, + 0x71009492, + 0x9295b100, + 0x71009494, + 0xb0d0b100, + 0x7000a480, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0x7000a002, + 0x7310730f, + 0x663cc040, + 0x92f0c000, + 0x92a08ad0, + 0x91c0c110, + 0xb2f06496, + 0x92a082b0, + 0xb0f3b483, + 0x7100b0c3, + 0x64e6a0c3, + 0xb006606f, + 0xb004b016, + 0xb002b014, + 0x8400b012, + 0x04207872, + 0x39838143, + 0x94732a73, + 0x1832c1f2, + 0x10213162, + 0x00123151, + 0x94000020, + 0x16101030, + 0x22103930, + 0x12204124, + 0x10033150, + 0x16a03180, + 0x12029350, + 0x22731204, + 0x84304136, + 0x87d297c0, + 0x84501a82, + 0x87d497c0, + 0x61381a84, + 0x41432263, + 0x97c08440, + 0x1a8087d0, + 0x84601402, + 0x87d097c0, + 0x14041a80, + 0x8440614f, + 0x04107881, + 0x87d297c0, + 0x84601a42, + 0x04107881, + 0x87d497c0, + 0x31521a44, + 0x39633154, + 0x16130633, + 0x38343832, + 0x39823182, + 0x00423184, + 0x78509572, + 0x78109360, + 0x90509030, + 0x90407820, + 0xb2059060, + 0x6965cb40, + 0x936087e0, + 0xa0c5b0f5, + 0x83038ae2, + 0xc00c9302, + 0x8140c00b, + 0x39803180, + 0x81413940, + 0x0431c0f3, + 0x1441c014, + 0x1412c002, + 0x31226979, + 0xb0d1b101, + 0xb0727100, + 0xa04ea0d1, + 0xb011b06e, + 0xa041b06c, + 0xa487a488, + 0x720d720c, + 0x7276720e, + 0xa764b764, + 0x9760c440, + 0xc020c062, + 0xc07e9780, + 0xb0e0c07f, + 0xb0c1b0f1, + 0xb0f5b0c5, + 0xb7607100, + 0xa0c5a0e0, + 0x220080b0, + 0x621345a2, + 0x7100b88f, + 0x978eb073, + 0xb201b074, + 0x85708961, + 0x95511801, + 0x8a718a60, + 0x1c211801, + 0x14124db9, + 0x61ba49b7, + 0x41ba1c01, + 0xb4874db9, + 0xb48861ba, + 0xb0f1b061, + 0xb0417100, + 0xb0f1978f, + 0xb04e7100, + 0x8a73b06e, + 0x70008552, + 0x8180b88c, + 0x392489a4, + 0x00043184, + 0xc0509184, + 0x7850663c, + 0x73769360, + 0x72487276, + 0x72027206, + 0x73057204, + 0x606f7306, + 0x91b01300, + 0xc060b32d, + 0xb0f8663c, + 0x78606509, + 0x12009360, + 0x97801a10, + 0x9760c380, + 0x9760c280, + 0xb0c6a0c1, + 0x22008090, + 0x81544451, + 0x41ec1e04, + 0x16943914, + 0xb0f69784, + 0xd0708552, + 0x663c9862, + 0x8a738a62, + 0x9862e080, + 0x663c9873, + 0x87818790, + 0x4a101c01, + 0x1ef11801, + 0x87814a0e, + 0x97811af1, + 0xb0f67100, + 0x978116f1, + 0x7100a205, + 0xa0c6b0f6, + 0x821d61c6, + 0x418b1e0d, + 0x9880c030, + 0x88a48893, + 0x31343133, + 0x422522fd, + 0x3d343d33, + 0x30d32afd, + 0x821230d4, + 0x163d622b, + 0x3cd43cd3, + 0x82121a3d, + 0x94e3622b, + 0xb05394f4, + 0xc030618b, + 0x88929880, + 0x3d323132, + 0x313388a3, + 0xe0903d33, + 0x98739862, + 0x7000663c, + 0x88409850, + 0x463d2200, + 0x7000b830, + 0x22f08150, + 0xb0704259, + 0x3162c102, + 0x8150c001, + 0x42521e00, + 0x425322f0, + 0x3160e5a0, + 0x62533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006a54 +}; + +PATCH_FUN_SPEC void rf_patch_mce_ghs(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 301; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchGhsMce[i]; + } +#else + const uint32_t *pS = patchGhsMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 37; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_hsp_4mbps.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_hsp_4mbps.h new file mode 100644 index 0000000..660f2cc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_hsp_4mbps.h @@ -0,0 +1,359 @@ +/****************************************************************************** +* Filename: rf_patch_mce_hsp_4mbps.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 4Mbps High speed mode +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_HSP_4MBPS_H +#define _RF_PATCH_MCE_HSP_4MBPS_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchHsp4mbpsMce[252] = { + 0x00036075, + 0x0079000f, + 0x00000000, + 0x000c8000, + 0x0000000a, + 0x00780002, + 0x80000000, + 0x06700808, + 0x0b000000, + 0x00500104, + 0x00000000, + 0x01ff0000, + 0x04030000, + 0x017f7f26, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x05952fc8, + 0x00ff2f8f, + 0x00ff00ff, + 0x00ff00ff, + 0x00ff00ff, + 0x00faf320, + 0xaaaa0000, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0x2000faf3, + 0x00580200, + 0x0f700288, + 0x00010fd0, + 0x0a400000, + 0x0d100002, + 0x0f590b08, + 0x04340f9a, + 0x067d0b08, + 0x09820f9a, + 0x0bcb0b08, + 0x00a60f9a, + 0x02ef0b08, + 0x00000f9a, + 0x00000000, + 0x00000000, + 0xc1020000, + 0xc0013162, + 0x1e008150, + 0x1a10406d, + 0x1020606f, + 0x6f131a10, + 0x16116e23, + 0x686f1612, + 0x72207000, + 0x7310730f, + 0x720c7311, + 0x720e720d, + 0x73057248, + 0x73767306, + 0xc7c07276, + 0xb0c09010, + 0xb0f07100, + 0x7218a0c0, + 0x10208132, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60b16c01, + 0x60de60c3, + 0x60b1611b, + 0x60b160b1, + 0x60b160b2, + 0x60de60c3, + 0x60b1611b, + 0x60b160b1, + 0x60b160b2, + 0x60de60c3, + 0x60b1611b, + 0x60b160b1, + 0x60b160b2, + 0x60de60c3, + 0x60b1611b, + 0x60b160b1, + 0x60b660b2, + 0x60b66465, + 0x60b71220, + 0x72201210, + 0x00108181, + 0xb0709180, + 0x00006083, + 0x00000000, + 0x00000000, + 0xc0110000, + 0xc560c282, + 0x6f131820, + 0x16116e23, + 0x68c71612, + 0x95a07ce0, + 0xc4f1c100, + 0x6f13c622, + 0x16116e23, + 0x68d11612, + 0x000060b6, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc3517220, + 0x9290c0f0, + 0x94926f12, + 0xb1081611, + 0x7100b0d8, + 0xa0d8b108, + 0xb480b200, + 0x91c0c140, + 0xb012b002, + 0xb013b003, + 0xb100c0c0, + 0x7100b0d0, + 0x6f12b100, + 0x94921611, + 0xa0d068f5, + 0xb483a480, + 0xb0c3b0f3, + 0x1220b0f1, + 0xc0c09760, + 0x71009780, + 0xb482a0c3, + 0xb0c1b760, + 0xb0f17100, + 0xa483a0c1, + 0xa003a760, + 0xc7c0a002, + 0x60b69010, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72200000, + 0x91b0c140, + 0x94327c52, + 0x94427c42, + 0x94027c62, + 0x93227c72, + 0x7cd07cc6, + 0xc00093b0, + 0xc3f09370, + 0xc3f13180, + 0x95f10001, + 0x96119601, + 0x7ce095e0, + 0xb00695a0, + 0xb004b016, + 0xb002b014, + 0xb107b012, + 0x7100b0d7, + 0xb072a0d7, + 0x90307b20, + 0x7b309050, + 0x90609040, + 0x72767b44, + 0x9762c022, + 0x9780c0e0, + 0x1e108210, + 0xc030454c, + 0xcb4065f2, + 0x65d36952, + 0xa0c5b0f5, + 0xb0f8b201, + 0xb0e0b110, + 0xb0737100, + 0xb072b760, + 0xb0619044, + 0xa0e0b110, + 0xb202a0c5, + 0x7ca2b074, + 0xb0c19362, + 0x7100b0f1, + 0x9780c080, + 0x88907388, + 0x88a194e0, + 0x936694f1, + 0x7100b0f1, + 0x9780c310, + 0xb0f1b3b5, + 0xc0307100, + 0x7c809780, + 0xb0f19320, + 0xc0207100, + 0xb0459780, + 0xb0f1b065, + 0xb04f7100, + 0xb0f1b06f, + 0x7276a0c1, + 0x97701240, + 0x9780fff0, + 0x9760c380, + 0xb0c8a764, + 0x7100b889, + 0xa0c8b0f8, + 0xd0408152, + 0x65f29862, + 0x97823112, + 0xb0c6b0f6, + 0xb0f67100, + 0xb107a0c6, + 0x7100b0d7, + 0x7100b107, + 0x7276b107, + 0x7100c0f0, + 0x7100b107, + 0xb5b0b107, + 0xa0d769a9, + 0x8a738a62, + 0x9862e050, + 0x65f29873, + 0xa202a201, + 0x31828942, + 0x84e73d82, + 0x313784f8, + 0x31383d37, + 0xe0603d38, + 0x98789867, + 0xc00065f2, + 0x93609370, + 0x94f094e0, + 0x73067305, + 0x72047203, + 0xa002a004, + 0x9010c7c0, + 0x7cb260b6, + 0x12f09362, + 0x738869d6, + 0x94e08890, + 0x94f188a1, + 0x7c929366, + 0xb0539362, + 0x31371007, + 0x10183d37, + 0x3d383138, + 0x9867e070, + 0x65f29878, + 0x00007000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x88409850, + 0x45f32200, + 0x7000b830 +}; + +PATCH_FUN_SPEC void rf_patch_mce_hsp_4mbps(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 252; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchHsp4mbpsMce[i]; + } +#else + const uint32_t *pS = patchHsp4mbpsMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 31; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_iqdump.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_iqdump.h new file mode 100644 index 0000000..8c4915c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_iqdump.h @@ -0,0 +1,442 @@ +/****************************************************************************** +* Filename: rf_patch_mce_iqdump.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 IQ data +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_IQDUMP_H +#define _RF_PATCH_MCE_IQDUMP_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchIqdumpMce[333] = { + 0x0000602d, + 0x3f9d2fcf, + 0x003f0001, + 0x0fffff00, + 0xf80007ff, + 0x00000300, + 0x00170003, + 0x00003d1f, + 0x08000000, + 0x0000000f, + 0x00000387, + 0x00434074, + 0x80828000, + 0x000006f0, + 0x0510091e, + 0x00070054, + 0x50140000, + 0x00000050, + 0x0c30c02f, + 0x0000017f, + 0x00000000, + 0x0000aa00, + 0x72200000, + 0xa32d7248, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72767376, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720c9001, + 0x720e720d, + 0x7100b0c0, + 0xa0c0b0f0, + 0x81327218, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x6081607e, + 0x60fa60ec, + 0x607e607e, + 0x607e607e, + 0x6081607e, + 0x619e60ec, + 0x607e607e, + 0x607e607e, + 0x6081607e, + 0x610a60ec, + 0x607e607e, + 0x607e607e, + 0x6081607e, + 0x61ba60ec, + 0x607e607e, + 0x607e607e, + 0x6081607e, + 0x614260ec, + 0x72201210, + 0x7310730f, + 0x81817311, + 0x91800010, + 0x6042b070, + 0x66896074, + 0xc0306074, + 0xc0c16674, + 0xc470c282, + 0x6f131820, + 0x16116e23, + 0x68871612, + 0x98107840, + 0xc5a0c482, + 0x40961820, + 0x6e231203, + 0x68931612, + 0x81606074, + 0x81409490, + 0x2a703980, + 0x16111001, + 0x84448432, + 0xc0f5c0f3, + 0x1c01c200, + 0xc10040bb, + 0x40b11c10, + 0x10134cb3, + 0x18301803, + 0x1a101a13, + 0x68ae3912, + 0x13f360bb, + 0x13f360bb, + 0xc1001015, + 0x1a151850, + 0x39141a10, + 0xb0d868b9, + 0xb1087100, + 0xb200a0d8, + 0xb003b480, + 0xb002b013, + 0x7229b012, + 0x7100b0d0, + 0x8140b100, + 0x71009290, + 0x8140b100, + 0x44cb22f0, + 0x1c0313f0, + 0x929340d7, + 0x71009492, + 0x9295b100, + 0x71009494, + 0xb0d0b100, + 0x7000a480, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0x7000a002, + 0x7310730f, + 0x6674c040, + 0x91c0c100, + 0xb4836497, + 0xb0c3b0f3, + 0xa0c37100, + 0x607464de, + 0xa0e0a0c2, + 0x730fa0e3, + 0x65fe7310, + 0x6674c050, + 0xc035b0c2, + 0x99c57100, + 0xb074b888, + 0x6104b0f2, + 0xa0e0a0c2, + 0x730fa0e3, + 0x65fe7310, + 0xc000c18b, + 0x120c91b0, + 0x787a1218, + 0x789e788d, + 0xb07410a9, + 0xc020b0c2, + 0x7100b0f2, + 0xc060691c, + 0xc0356674, + 0x7100b0f2, + 0x8a3099c5, + 0x8ad16593, + 0x412f2201, + 0x1ca81080, + 0x1208452e, + 0x658a1618, + 0x65938a40, + 0x22018ad1, + 0x1090413a, + 0x1e091a19, + 0x10a9453a, + 0x8154658a, + 0x41221e04, + 0x1c4c14bc, + 0x61224e5d, + 0xa0e0a0c2, + 0x730fa0e3, + 0x65fe7310, + 0x120c721b, + 0xb0741205, + 0xc020b0c2, + 0x7100b0f2, + 0xc070694e, + 0x78ad6674, + 0xb0f2881e, + 0x8ac07100, + 0x415e2200, + 0x22108200, + 0xb201455e, + 0x8902988d, + 0x3d823182, + 0x31808940, + 0x18023d80, + 0x1e0e063e, + 0x1e2e4180, + 0x1e3e4172, + 0x10564179, + 0x3d161426, + 0x61811065, + 0x31261056, + 0x14261856, + 0x10653d26, + 0x10566181, + 0x18563136, + 0x3d361426, + 0x61811065, + 0x39761026, + 0x81549196, + 0x41551e04, + 0x1c4c161c, + 0x61554e5d, + 0xc0b01001, + 0x39119191, + 0x10001000, + 0x698c1000, + 0x31307000, + 0x1cd03d30, + 0x1ce04d9a, + 0x7000499c, + 0x700010d0, + 0x700010e0, + 0x6674c080, + 0xa0e0a0c2, + 0x730fa0e3, + 0x65fe7310, + 0xb0e0b110, + 0x80b07100, + 0x45ad2200, + 0xb20161a8, + 0x6674c090, + 0xa0e0b110, + 0xc035b0c2, + 0x99c57100, + 0xb074b888, + 0x61b4b0f2, + 0x6674c0a0, + 0xa0e0a0c2, + 0x730fa0e3, + 0x65fe7310, + 0xc000c18b, + 0x120c91b0, + 0x787a1218, + 0x789e788d, + 0xb11010a9, + 0x7100b0e0, + 0x220080b0, + 0x61cd45d2, + 0xb201b074, + 0x6674c0b0, + 0xa0e0b110, + 0xc020b0c2, + 0x7100b0f2, + 0xc03569da, + 0x7100b0f2, + 0x8a3099c5, + 0x8ad16593, + 0x41eb2201, + 0x1ca81080, + 0x120845ea, + 0x658a1618, + 0x65938a40, + 0x22018ad1, + 0x109041f6, + 0x1e091a19, + 0x10a945f6, + 0x8154658a, + 0x41de1e04, + 0x1c4c14bc, + 0x61de4e5d, + 0x6674c0c0, + 0xb006b0f8, + 0xb004b016, + 0xb002b014, + 0x8400b012, + 0x04207852, + 0x39838143, + 0x94732a73, + 0x1832c1f2, + 0x10213162, + 0x00123151, + 0x94000020, + 0x16101030, + 0x22103930, + 0x1220421c, + 0x10033150, + 0x16303180, + 0x12029350, + 0x22731204, + 0x8430422e, + 0x87d297c0, + 0x84501a82, + 0x87d497c0, + 0x62301a84, + 0x423b2263, + 0x97c08440, + 0x1a8087d0, + 0x84601402, + 0x87d097c0, + 0x14041a80, + 0x84406247, + 0x04107861, + 0x87d297c0, + 0x84601a42, + 0x04107861, + 0x87d497c0, + 0x31521a44, + 0x39633154, + 0x16130633, + 0x38343832, + 0x39823182, + 0x00423184, + 0x78209572, + 0x90509030, + 0x90407830, + 0xb2059060, + 0x9140cd90, + 0xa2057000, + 0x7100b0f2, + 0xb0f2a0c2, + 0x8180b88c, + 0x392489a4, + 0x00043184, + 0xc0d09184, + 0x73766674, + 0x72487276, + 0x72027206, + 0x73057204, + 0x60747306, + 0x88409850, + 0x46752200, + 0x7000b830, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc1020000, + 0xc0013162, + 0x1e008150, + 0x1a104291, + 0x10206293, + 0x6f131a10, + 0x16116e23, + 0x6a931612, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_mce_iqdump(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 333; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchIqdumpMce[i]; + } +#else + const uint32_t *pS = patchIqdumpMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 41; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_sl_longrange.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_sl_longrange.h new file mode 100644 index 0000000..27cc2c3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_sl_longrange.h @@ -0,0 +1,354 @@ +/****************************************************************************** +* Filename: rf_patch_mce_sl_longrange.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Simplelink Long range +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_SL_LONGRANGE_H +#define _RF_PATCH_MCE_SL_LONGRANGE_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchSl_longrangeMce[256] = { + 0x146f603e, + 0x333c3c33, + 0x3cc3cccc, + 0x2fcf0005, + 0xdb3e0f9d, + 0x00007f7f, + 0x00020001, + 0x00000003, + 0x000c0003, + 0x00cc000f, + 0x003c00c3, + 0xcccc0033, + 0x33cccc33, + 0x0f003333, + 0x00000f0f, + 0x00070003, + 0x0000001f, + 0x04000000, + 0x0000000f, + 0x00010387, + 0x004348c0, + 0x80048000, + 0x000006f0, + 0x0524091e, + 0x00050054, + 0x48200800, + 0x00000048, + 0x7f7f001f, + 0x3c33014c, + 0xcccc333c, + 0x00003cc3, + 0x72487220, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72767376, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720c9001, + 0x720e720d, + 0x7100b0c0, + 0xa0c0b0f0, + 0x81327218, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x60766074, + 0x610e608a, + 0x60746074, + 0x60756074, + 0x606b1220, + 0x72201210, + 0x7310730f, + 0x81817311, + 0x91800010, + 0x6052b070, + 0x606a606a, + 0xc282c1e1, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0xc482687a, + 0x1820c810, + 0x12034087, + 0x16126e23, + 0xd0006884, + 0x606a9170, + 0x7310730f, + 0x91c0c000, + 0x8170c009, + 0x06703980, + 0x1e101610, + 0xc0b74499, + 0xc01ec008, + 0x1e2060aa, + 0xc0f7449f, + 0xc03ec018, + 0x1e4060aa, + 0xc13744a5, + 0xc07ec038, + 0x1e8060aa, + 0xc1774468, + 0xc0fec078, + 0x65f9c030, + 0x7100b0d8, + 0xa0d8b108, + 0xb480b200, + 0xb013b003, + 0xb012b002, + 0x39468146, + 0x0446c0f4, + 0xb0d01616, + 0xc13cc004, + 0x9290c070, + 0xc0707811, + 0x06321012, + 0x6f2314c2, + 0x71009493, + 0x3921b100, + 0x161468c2, + 0x44c01c64, + 0x0bf17811, + 0x1012c070, + 0x14c20632, + 0x94936f23, + 0xb1007100, + 0x68d13921, + 0xc6d5c4f4, + 0x81afc066, + 0x81e064f7, + 0x40e32210, + 0xc07060dd, + 0xc00f1610, + 0x68e564f7, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0x7220a002, + 0x061f606a, + 0x00f9316f, + 0x04411091, + 0x87da97c1, + 0x1091061a, + 0x97c10451, + 0x061b87db, + 0x14ba311b, + 0x147a3919, + 0x94936fa3, + 0x7100929e, + 0x7000b100, + 0x8ae4b0f8, + 0x93044112, + 0x9400c1f0, + 0x941078a0, + 0x8177721b, + 0x39871076, + 0x97c70677, + 0x161887d8, + 0x9867d040, + 0x782065f9, + 0x78309430, + 0x78409440, + 0x78509450, + 0x655a9460, + 0x98107890, + 0xb007656d, + 0xb104b017, + 0xc205b0d4, + 0x65e1c004, + 0x1c5465f2, + 0x91904938, + 0x81511614, + 0x41331e01, + 0x1c411671, + 0xa0d74d33, + 0x79cf79be, + 0x95ff95ee, + 0x65f21204, + 0x1c541614, + 0x9190414b, + 0xa2056145, + 0x65f9c050, + 0xa0d4a0d7, + 0x72027206, + 0x72037204, + 0x73057204, + 0x73767306, + 0x606a7276, + 0x3181c061, + 0xcff3c002, + 0x16116e12, + 0x16116e12, + 0x6e13c7e0, + 0x6e121611, + 0x69631611, + 0x6e12cff0, + 0x69691611, + 0xb0067000, + 0xb004b016, + 0xb002b014, + 0x7870b012, + 0x90509030, + 0x90407880, + 0xb2059060, + 0xc090b072, + 0xb11793b0, + 0xb116b0e7, + 0x7100b0e6, + 0xb107b073, + 0xa0e7a0e7, + 0x227080b0, + 0xa0e645a2, + 0xb0d7a0e7, + 0x7100b88e, + 0xb107b116, + 0xb061b041, + 0x93b0c0f0, + 0x8964b88f, + 0x95543114, + 0x7100a044, + 0xb04db107, + 0xb074b06d, + 0x7100b201, + 0x7000b107, + 0xb889b0d7, + 0x31848944, + 0x97243d84, + 0x97307860, + 0x69abc050, + 0xc2018740, + 0x3d601410, + 0x31648304, + 0x18043d64, + 0x3520cff0, + 0x93040404, + 0x93b0c0b0, + 0xd060b069, + 0x65f99864, + 0xb1077100, + 0x617da0d7, + 0x120a1209, + 0x140965d7, + 0x1e17141a, + 0x65d741d4, + 0x140a1419, + 0x41d41e37, + 0x140965d7, + 0x65d7141a, + 0x140a1419, + 0x3c8a3c89, + 0x71007000, + 0x7100b107, + 0x87f0b107, + 0x39803180, + 0x39818801, + 0x65c27000, + 0x10ac109b, + 0x10bd65c2, + 0x14db318d, + 0x318d10cd, + 0x318a14dc, + 0x149b14a9, + 0x95eb149c, + 0x700095fc, + 0xb079a0d7, + 0xb1047100, + 0x8820b0d7, + 0x98507000, + 0x22008840, + 0xb83045fa, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_mce_sl_longrange(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 256; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchSl_longrangeMce[i]; + } +#else + const uint32_t *pS = patchSl_longrangeMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 32; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wb_dsss.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wb_dsss.h new file mode 100644 index 0000000..e534430 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wb_dsss.h @@ -0,0 +1,392 @@ +/****************************************************************************** +* Filename: rf_patch_mce_wb_dsss.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Wideband DSSS +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_WB_DSSS_H +#define _RF_PATCH_MCE_WB_DSSS_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchWbDsssMce[279] = { + 0x2fcf6068, + 0xdb3e0f9d, + 0x7f7f0303, + 0x00010000, + 0x00030002, + 0x00030000, + 0x000f000c, + 0x00c300cc, + 0x0033003c, + 0xcc33cccc, + 0x333333cc, + 0x0f0f0f00, + 0x03050404, + 0x01070206, + 0x00090008, + 0x000b000a, + 0x0b000c00, + 0x09000a00, + 0x07010800, + 0x05030602, + 0x03030404, + 0x01010202, + 0x00000000, + 0x00000000, + 0x0b0b0c0c, + 0x09090a0a, + 0x07070808, + 0x05050606, + 0x05050404, + 0x07070606, + 0x09090808, + 0x0b0b0a0a, + 0x00000000, + 0x00000000, + 0x01010000, + 0x03030202, + 0x00070003, + 0x0000001f, + 0x04000000, + 0x0000000f, + 0x00010387, + 0x004348c9, + 0x80048000, + 0x000006f0, + 0x0524091e, + 0x00070054, + 0x280a0000, + 0x00000028, + 0x7f7f001f, + 0x3c33013e, + 0xcccc333c, + 0x00003cc3, + 0x72487220, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72767376, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720c9001, + 0x720e720d, + 0x7100b0c0, + 0xa0c0b0f0, + 0x81327218, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x60a0609e, + 0x613260b4, + 0x609e609e, + 0x609f609e, + 0x60951220, + 0x72201210, + 0x7310730f, + 0x81817311, + 0x91800010, + 0x607cb070, + 0x60946094, + 0xc282c481, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0xc48268a4, + 0x1820c810, + 0x120340b1, + 0x16126e23, + 0x784068ae, + 0x60949ab0, + 0x7310730f, + 0x91c0c000, + 0x8ab0c009, + 0x06703980, + 0xc0f41610, + 0xc036c0b5, + 0x44c61e10, + 0xc008c067, + 0x60d7c01e, + 0x44cc1e20, + 0xc018c0a7, + 0x60d7c03e, + 0x44d21e40, + 0xc038c0e7, + 0x60d7c07e, + 0x44921e80, + 0xc078c127, + 0x1062c0fe, + 0xe0301612, + 0x98789862, + 0x8160657c, + 0x81409490, + 0xb0d89290, + 0xb1087100, + 0xb200a0d8, + 0xb003b480, + 0xb002b013, + 0xb0d0b012, + 0xb1007100, + 0x22f08140, + 0xc0f044eb, + 0x84509290, + 0x71009490, + 0x8460b100, + 0x71009490, + 0x8430b100, + 0x71009490, + 0x8440b100, + 0x81af9490, + 0x81e0651b, + 0x41072210, + 0x10606101, + 0xc00f1620, + 0x6909651b, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0x7220a002, + 0x061f6094, + 0x00f9306f, + 0x04411091, + 0x87da97c1, + 0x1091061a, + 0x97c10451, + 0x061b87db, + 0x14ba311b, + 0x147a3919, + 0x71006fa3, + 0x9493b100, + 0x7000929e, + 0xc1f0b0f8, + 0x78509400, + 0x721b9410, + 0x10768ab7, + 0x06773987, + 0x87d897c7, + 0x1e071618, + 0xc0064543, + 0x1e17614e, + 0xc0064547, + 0x1e37614e, + 0xc036454b, + 0x1e77614e, + 0xc3364492, + 0xb0066182, + 0xb004b016, + 0xb002b014, + 0x7810b012, + 0x90509030, + 0x90407820, + 0xb2059060, + 0xc0b0b072, + 0xb11693b0, + 0x7100b0e6, + 0xb107b073, + 0xa0e6b116, + 0xb88eb0d7, + 0xb1077100, + 0xb061b041, + 0x93b0c0f0, + 0x8964b88f, + 0x95543114, + 0x7100a044, + 0xb04db107, + 0xb074b06d, + 0x7100b201, + 0x7000b107, + 0x88409850, + 0x457d2200, + 0x7000b830, + 0x9867d040, + 0xe1d1657c, + 0x95a06f10, + 0xe1e1c100, + 0x6f13c622, + 0x16116e23, + 0x698b1612, + 0x41e41e07, + 0xb04f654f, + 0xc0f5b06f, + 0x65d4c004, + 0x85d0b5b0, + 0x1c543920, + 0x9190499e, + 0x81511614, + 0x41971e01, + 0x1c411621, + 0xa0d74d97, + 0x797f796e, + 0x95ff95ee, + 0xb5b01204, + 0x392085d0, + 0x1c541614, + 0x919041b3, + 0xa20561ab, + 0x657cc050, + 0xa0d4a0d7, + 0x72027206, + 0x72037204, + 0x73057204, + 0x73767306, + 0x60947276, + 0x12091070, + 0xb1077100, + 0x89b3b88d, + 0x3d833183, + 0x41cd2006, + 0x14390bf3, + 0x3c8969c4, + 0x3d391649, + 0x700006f9, + 0xc28a65c2, + 0x6fab149a, + 0x149ac38a, + 0xc18a6fac, + 0x149a65c2, + 0x14db6fad, + 0x95ec14dc, + 0x700095fb, + 0x657cc060, + 0xb04f654f, + 0xc0f5b06f, + 0x7100c004, + 0x7100b107, + 0x87fcb107, + 0x95ec880b, + 0xb5b095fb, + 0x392085d0, + 0x49f91c54, + 0x16149190, + 0x1e018151, + 0x162141eb, + 0x4deb1c41, + 0x796ea0d7, + 0x95ee797f, + 0x120495ff, + 0x85d0b5b0, + 0x16143920, + 0x420e1c54, + 0x62069190, + 0xc070a205, + 0xa0d7657c, + 0x7206a0d4, + 0x72047202, + 0x72047203, + 0x73067305, + 0x72767376, + 0x00016094, + 0x00080018, + 0x001a0003, + 0x002c000a, + 0x003e0011, + 0x00080003, + 0x001a0018, + 0x002c0011, + 0x003e000a +}; + +PATCH_FUN_SPEC void rf_patch_mce_wb_dsss(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 279; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchWbDsssMce[i]; + } +#else + const uint32_t *pS = patchWbDsssMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 34; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_ctmode.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_ctmode.h new file mode 100644 index 0000000..c934970 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_ctmode.h @@ -0,0 +1,610 @@ +/****************************************************************************** +* Filename: rf_patch_mce_wmbus_ctmode.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 WMBUS C- and T-Mode +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_WMBUS_CTMODE_H +#define _RF_PATCH_MCE_WMBUS_CTMODE_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchWmbusTmodeMce[512] = { + 0x2fcf60b3, + 0xff803f9d, + 0x02b30666, + 0x0fff00ff, + 0x5555003f, + 0x05140510, + 0x0004002a, + 0x00310018, + 0x00610047, + 0x0092007a, + 0x00ba00a8, + 0x00d000c7, + 0x00d600d4, + 0x001f0045, + 0x00e800f8, + 0x00c000d0, + 0x008800a8, + 0x00600078, + 0x00440057, + 0x00180031, + 0x00250004, + 0x05b205a2, + 0x05d305c3, + 0x05f405e3, + 0x06140604, + 0x06350625, + 0x06560646, + 0x06770666, + 0x06980687, + 0x06b806a8, + 0x06c906b8, + 0x06e906d9, + 0x070a06fa, + 0x0016071b, + 0x001c002c, + 0x000e0034, + 0x001a0026, + 0x000d0032, + 0x00190025, + 0x000b0031, + 0x00130023, + 0x00060029, + 0x0006000e, + 0x0002000e, + 0x00040008, + 0x0006000e, + 0x0006000a, + 0x0002000c, + 0x00040008, + 0x0006000c, + 0x0006000e, + 0x0002000e, + 0x0000000e, + 0x0006000e, + 0x0006000a, + 0x0002000e, + 0x0006000a, + 0x0007000e, + 0x0007000f, + 0x0003000d, + 0x00050009, + 0x0001000d, + 0x0007000f, + 0x0001000f, + 0x0005000f, + 0x0007000f, + 0x0007000b, + 0x0003000b, + 0x0007000b, + 0x0007000b, + 0x0007000f, + 0x0003000f, + 0x0007000f, + 0x0003000f, + 0x3d1f0007, + 0x00000000, + 0x000f0400, + 0x03840000, + 0x00f4000b, + 0x80000043, + 0x06702801, + 0x091e0000, + 0x00040514, + 0x02000000, + 0x00613e10, + 0x842f0000, + 0x007f177f, + 0xaaaaaaaa, + 0x2abcaaaa, + 0x72200000, + 0xa32d7248, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72767376, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720c9001, + 0x720e720d, + 0x7100b0c0, + 0xa0c0b0f0, + 0x81327218, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x60ea60e8, + 0x61a66152, + 0x60e860e8, + 0x60e960e8, + 0x72201210, + 0x7310730f, + 0x81817311, + 0x91800010, + 0x60c8b070, + 0x60de60de, + 0xc282c931, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0x72ad68ee, + 0xc5a0c482, + 0x40fc1820, + 0x6e231203, + 0x68f91612, + 0x816060de, + 0x81409490, + 0x2a703980, + 0x16111001, + 0x84448432, + 0xc0f5c0f3, + 0x1c01c200, + 0xc1004121, + 0x41171c10, + 0x10134d19, + 0x18301803, + 0x1a101a13, + 0x69143912, + 0x13f36121, + 0x13f36121, + 0xc1001015, + 0x1a151850, + 0x39141a10, + 0xb0d8691f, + 0xb1087100, + 0xb200a0d8, + 0xb003b480, + 0xb002b013, + 0x7229b012, + 0x7100b0d0, + 0x8140b100, + 0x71009290, + 0x8140b100, + 0x453122f0, + 0x1c0313f0, + 0x9293413d, + 0x71009492, + 0x9295b100, + 0x71009494, + 0xb0d0b100, + 0x7000a480, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0x7000a002, + 0x7310730f, + 0x39818ad1, + 0x06113961, + 0x9861d030, + 0xc10067f9, + 0x64fd91c0, + 0x22e08ad0, + 0xb4834587, + 0xb0c3b0f3, + 0xc030b484, + 0xb10191c0, + 0x8ad5b0d1, + 0x416d22d5, + 0x809012f5, + 0x45822230, + 0x085081a0, + 0x1401c431, + 0xc0636f12, + 0x417a2252, + 0x617b1211, + 0x92c113f1, + 0x7100b101, + 0x1a133112, + 0x616d4576, + 0xb101a0d1, + 0x6544a0c3, + 0xb0d060de, + 0xc070b480, + 0x78c09290, + 0xb1009490, + 0xb1007100, + 0xa480a0d0, + 0xb0f3b483, + 0x7100b0c3, + 0x6544a0c3, + 0x861160de, + 0x9861d040, + 0x737667f9, + 0x72487276, + 0x72027206, + 0x73057204, + 0x60de7306, + 0x91b01230, + 0x939078b0, + 0xb0f8b32d, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x90307810, + 0x78209050, + 0x90609040, + 0x31808140, + 0x39403980, + 0xc0f38141, + 0xc0140431, + 0x82e01441, + 0x04107831, + 0x1410c7c1, + 0x727892e0, + 0x72557276, + 0x93008ae0, + 0xc030a311, + 0xb06993b0, + 0xb0f6b064, + 0xb101a0c6, + 0xb0f1a0d1, + 0xb0f2a0c1, + 0xb486b0c2, + 0x12008441, + 0x08011a10, + 0x1012c0f0, + 0x311e0612, + 0x3911142e, + 0x789c69df, + 0xc00a67ee, + 0x1a1fc00f, + 0x1a1bc00b, + 0x9780c1b0, + 0x9760c020, + 0x789d7878, + 0xc024048d, + 0xc006c005, + 0xb0f2b205, + 0xb88d7100, + 0x46311e2a, + 0x39708af0, + 0x140b311b, + 0x1ccb8210, + 0x22204605, + 0x22204640, + 0xb7604209, + 0xa760620b, + 0x8b10b0f1, + 0x08018b21, + 0x42142271, + 0x31163315, + 0x61f7c00a, + 0x42101e3a, + 0x61f7161a, + 0x22208210, + 0xb760421d, + 0xa760621f, + 0x8b10b0f1, + 0x08018b21, + 0x422d2271, + 0x46291e0a, + 0x33163115, + 0x3115622b, + 0xc00a3116, + 0x1e3a61f7, + 0x161a422b, + 0x809061f7, + 0x42182210, + 0x22c08ad0, + 0x10b14640, + 0x08d10481, + 0x87d197c1, + 0x4e1f1c41, + 0x67f9c050, + 0x72767278, + 0xb0f1a0c1, + 0x93b0c070, + 0x3135b201, + 0x87da97c5, + 0x97c63136, + 0x189a87d9, + 0xb88995fa, + 0x31808940, + 0x16203d80, + 0x8ae83d20, + 0xc1501808, + 0x1e4185f1, + 0xc0614a5d, + 0xc00b1810, + 0x673cc00c, + 0x79ba79a9, + 0xc10010a8, + 0x85f11808, + 0x4e711e11, + 0x467a1e01, + 0x4e7a18b9, + 0x10c510b5, + 0x4a7a1ca5, + 0x1a896283, + 0x18b9108a, + 0x10b54e93, + 0x1ca518c5, + 0x62834a93, + 0x18c07a90, + 0x10c54e93, + 0xc00018b5, + 0x4a931c05, + 0xc0dc628b, + 0x671fc0d0, + 0x1ac510d5, + 0x185d120d, + 0x10cb6295, + 0xc0d0c1cc, + 0x10d5671f, + 0x185d120d, + 0xc00d6295, + 0xa4866295, + 0x67d0a5e0, + 0xc00ac00b, + 0xc007c006, + 0x8ad0c009, + 0x46a122d0, + 0x78687889, + 0x789d048e, + 0xc010048d, + 0xb7649780, + 0x9760c2b0, + 0xb0f1b0f6, + 0xb0f2b069, + 0xb88d7100, + 0x46ba1e2a, + 0x39708af0, + 0x140b311b, + 0x1ceb048b, + 0x62ca42de, + 0x22608090, + 0x221046c0, + 0x62c646d5, + 0x9760c030, + 0xb0f1b0f6, + 0x9780c1c0, + 0x46ca1cdb, + 0xb760a760, + 0x8b218b10, + 0x22710801, + 0x120a42d1, + 0x1e3a62d4, + 0x161a42cf, + 0x722062ad, + 0xb0f2c060, + 0x6ad77100, + 0x16118601, + 0x61c79601, + 0x7276b889, + 0x78c4161a, + 0xc00ec00b, + 0xb113b074, + 0x7100b0f2, + 0x1e2ab88d, + 0x8af046f7, + 0x311b3970, + 0x161e140b, + 0x470c1e6e, + 0x43581c4b, + 0xc00ec016, + 0x1066630c, + 0xc5304301, + 0x14b0089b, + 0x91916f01, + 0xc017c006, + 0x1077630c, + 0x164f430c, + 0xc007c00b, + 0x1e008150, + 0x1cf0430c, + 0x63174f0c, + 0x8b218b10, + 0x22710801, + 0xc00a4313, + 0x1e3a62e6, + 0x161a4311, + 0xa20562e6, + 0xb0f2a0c2, + 0xb0f1a0c1, + 0x67eeb113, + 0x1a106199, + 0xc0c2c001, + 0x161c6fcd, + 0x673410b3, + 0x1a101051, + 0x161c6fcd, + 0x1c156734, + 0x6b284b2f, + 0x10516332, + 0x6b281002, + 0x7000102d, + 0x4b391cd3, + 0x18d51035, + 0x10d57000, + 0x70001835, + 0x7100b0f2, + 0x8911b88e, + 0x4f441012, + 0x18211201, + 0x1c1b3131, + 0x101b4f48, + 0x10128921, + 0x12014f4d, + 0x31311821, + 0x4f511c1c, + 0xc172101c, + 0x4f561c20, + 0xb3119308, + 0x70006b3c, + 0x7276b113, + 0x9780c070, + 0x78a09760, + 0xb0f29390, + 0x80b07100, + 0x476a2230, + 0x22108090, + 0x635f4768, + 0x67f9c060, + 0x7276b073, + 0x9780c040, + 0x9760c070, + 0x8a8367ee, + 0xc0018a94, + 0x1c1f1a11, + 0xc040437a, + 0x4b7b1cf0, + 0x8940b011, + 0x3d803180, + 0x8a809550, + 0xa4888a91, + 0xc022a487, + 0x1c211801, + 0x14124f8f, + 0x63904b8d, + 0x43901c01, + 0xb4874f8f, + 0xb4886390, + 0xb041a04e, + 0xb5e0b061, + 0x80b0b113, + 0x47942230, + 0xb0f1b0c1, + 0xb0f2a0c2, + 0x7100b113, + 0xb06eb04e, + 0xc090a760, + 0x97803120, + 0x91b01300, + 0xb0f1b760, + 0x72767100, + 0xb0c6b0f6, + 0xa0c1b0f1, + 0x1a101200, + 0xc3809780, + 0xc2809760, + 0x80909760, + 0x44c82200, + 0x1e048154, + 0x978443b5, + 0x8790b0f6, + 0x1c018781, + 0x18014bcd, + 0x4bcb1ef1, + 0x1af18781, + 0x71009781, + 0x16f1b0f6, + 0xa2059781, + 0xb0f67100, + 0x6199a0c6, + 0xc2a1961d, + 0x141d16c1, + 0x101d6fd1, + 0x82e03151, + 0x14013980, + 0x83329721, + 0x06711021, + 0x06323952, + 0x16111421, + 0x43e5c1b0, + 0x97303010, + 0x6be71270, + 0x874092dd, + 0x875094a0, + 0x700094b0, + 0x1e0087e0, + 0x84a047f3, + 0x94a097e0, + 0x92d07840, + 0x94b07850, + 0x98507000, + 0x22008840, + 0xb83047fa, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_mce_wmbus_ctmode(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 512; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchWmbusTmodeMce[i]; + } +#else + const uint32_t *pS = patchWmbusTmodeMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 64; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_smode.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_smode.h new file mode 100644 index 0000000..2bf4aa3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_smode.h @@ -0,0 +1,610 @@ +/****************************************************************************** +* Filename: rf_patch_mce_wmbus_smode.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 WMBUS S-Mode +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_WMBUS_SMODE_H +#define _RF_PATCH_MCE_WMBUS_SMODE_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchWmbusSmodeMce[512] = { + 0x2fcf602e, + 0x030c3f9d, + 0x070c680a, + 0xff00003f, + 0x00000014, + 0x00000000, + 0x00000000, + 0x00070003, + 0x00003d1f, + 0x04000000, + 0x0000000f, + 0x000b0387, + 0x004340f4, + 0x80828000, + 0x00000670, + 0x0510091e, + 0x00050004, + 0x3e100200, + 0x00000061, + 0x3030002f, + 0x0000027f, + 0x00000000, + 0x0000aa00, + 0x72487220, + 0x7303a32d, + 0x72037305, + 0x73067304, + 0x73767204, + 0xc7c07276, + 0x00018001, + 0x90109001, + 0x90010801, + 0x720d720c, + 0xb0c0720e, + 0xb0f07100, + 0x7218a0c0, + 0x10208132, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60636c01, + 0x60d76066, + 0x606362f6, + 0x60636063, + 0x12106064, + 0x730f7220, + 0x73117310, + 0x00108181, + 0xb0709180, + 0x60596043, + 0x605967ef, + 0x6791c030, + 0xc282c0e1, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0x7830686c, + 0x78409ab0, + 0x78509ac0, + 0x83009ad0, + 0xc4829ae0, + 0x1820c5a0, + 0x12034081, + 0x16126e23, + 0x6059687e, + 0x94908160, + 0x39808140, + 0x10012a70, + 0x84321611, + 0xc0f38444, + 0xc200c0f5, + 0x40a61c01, + 0x1c10c100, + 0x4c9e409c, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60a66899, + 0x60a613f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68a43914, + 0x7100b0d8, + 0xa0d8b108, + 0xb480b200, + 0xb013b003, + 0xb012b002, + 0xb0d07229, + 0xb1007100, + 0x92908140, + 0xb1007100, + 0x22f08140, + 0x13f044b6, + 0x40c21c03, + 0x94929293, + 0xb1007100, + 0x94949295, + 0xb1007100, + 0xa480b0d0, + 0xa0d17000, + 0x9760c030, + 0x9780c040, + 0xb0c1b0f1, + 0xb0f17100, + 0x7276a0c1, + 0xa002a003, + 0x730f7000, + 0xc0407310, + 0xc1006791, + 0x648291c0, + 0xb0f3b483, + 0xb484b0c3, + 0x91c0c000, + 0xb0d1b101, + 0x39858ad5, + 0x06153955, + 0x22308090, + 0x81a044ff, + 0x06100850, + 0x13f040f4, + 0x60f61211, + 0x13f11210, + 0x101b100a, + 0xb10192c0, + 0x92c17100, + 0x7100b101, + 0xa0d160ea, + 0xa0c3b101, + 0x605964c9, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x78628400, + 0x81430420, + 0x2a733983, + 0xc1f29473, + 0x31621832, + 0x31511021, + 0x00200012, + 0x10309400, + 0x39301610, + 0x411f2210, + 0x31501220, + 0x31801003, + 0x93501630, + 0x12041202, + 0x41312273, + 0x97c08430, + 0x1a8287d2, + 0x97c08450, + 0x1a8487d4, + 0x22636133, + 0x8440413e, + 0x87d097c0, + 0x14021a80, + 0x97c08460, + 0x1a8087d0, + 0x614a1404, + 0x78718440, + 0x97c00410, + 0x1a4287d2, + 0x78718460, + 0x97c00410, + 0x1a4487d4, + 0x31543152, + 0x06333963, + 0x38321613, + 0x31823834, + 0x31843982, + 0x95720042, + 0x90307810, + 0x78209050, + 0x90609040, + 0x8ae2b205, + 0x93028303, + 0x9862e050, + 0x67919873, + 0xc00bc00c, + 0x31808140, + 0x39403980, + 0xc0f38141, + 0xc0140431, + 0xc0021441, + 0x69701412, + 0x847d3122, + 0x140dc010, + 0x142d312d, + 0x318e8ace, + 0x397e311e, + 0x31498ac9, + 0x39493979, + 0x109a3129, + 0xa04eb072, + 0xb011b06e, + 0x978ab06c, + 0xb7647276, + 0xc662a764, + 0xc04f9762, + 0x6677c028, + 0x22f18ab1, + 0x8ad14597, + 0x459722f1, + 0x710061f0, + 0xb760b073, + 0x220780b7, + 0xa76045ce, + 0x22f18ab1, + 0x223741a8, + 0xb11341a8, + 0x223080b0, + 0x61b645a3, + 0x41bb22e1, + 0x22508090, + 0xb0f541bb, + 0x22208210, + 0x97894197, + 0xa764b764, + 0x6197b0f6, + 0xb764978d, + 0xb0f6a764, + 0x8ad06197, + 0x41c722f0, + 0x41c72237, + 0xb113b075, + 0x223080b0, + 0xb08745c1, + 0x22d16197, + 0x809042ba, + 0x42ba2220, + 0x6197663a, + 0xa0e0978f, + 0xa0c2a0e3, + 0xb0f1a0c5, + 0xa0c6b0c1, + 0x97887100, + 0xb88fb0f1, + 0x85708961, + 0x95511801, + 0x8a718a60, + 0xa487a488, + 0x22e08ad0, + 0x821041e8, + 0x45822220, + 0xb04e7100, + 0xb074b06e, + 0x8a73b201, + 0x70008552, + 0xb0737100, + 0x80b7b760, + 0x460f2207, + 0x46252237, + 0x8ab1a760, + 0x420822e1, + 0x22508090, + 0xb0f54208, + 0x22208210, + 0x978d41f0, + 0xa764b764, + 0x61f0b0f6, + 0x42ba22d1, + 0x22208090, + 0x663a42ba, + 0x978f61f0, + 0xa0e3a0e0, + 0xa0c5a0c2, + 0xb0c1b0f1, + 0x7100a0c6, + 0xb0f19788, + 0x8961b88f, + 0x31808570, + 0x18013d80, + 0x8a609551, + 0xa1828a71, + 0x978f61e0, + 0xa0e3a0e0, + 0xa0c5a0c2, + 0xb0c1b0f1, + 0x7100a0c6, + 0xb0f19788, + 0x8961b88f, + 0x3d808570, + 0x95511801, + 0x8a918a80, + 0x61e0b182, + 0x22b08ab0, + 0x1e3b4640, + 0x62424675, + 0x46751e7b, + 0xb889c00b, + 0x31808940, + 0x16403d80, + 0x140c3d30, + 0x220080b0, + 0x7000424e, + 0x39838ab3, + 0x8ab106f3, + 0x0401cff0, + 0x1c1c3031, + 0x12004e6d, + 0x1c0c1810, + 0x80b04a6f, + 0x425f2200, + 0x10c27000, + 0x3c321612, + 0x83208ae1, + 0x42712210, + 0x93016273, + 0x9861d060, + 0xb0f26791, + 0x101c7000, + 0x100c625b, + 0x1821625b, + 0x14216267, + 0x161b6267, + 0xb0f6626b, + 0xb110b0f1, + 0xb0f5b113, + 0x720cb0f2, + 0x720e720d, + 0xb0e3b0e0, + 0x22f28ab2, + 0xb0c64288, + 0x628bb763, + 0x22f08ad0, + 0xb40542ab, + 0xb428a404, + 0xcaa0a429, + 0xcaa13180, + 0x94510001, + 0x8ad39461, + 0x39833183, + 0x31808410, + 0x31833980, + 0x94100030, + 0x31508400, + 0x8ad33950, + 0x06f33983, + 0x1834c1f4, + 0x31343184, + 0x94000040, + 0x22e2b089, + 0x8aca42b5, + 0x398a394a, + 0x978a312a, + 0xb0c6b0c5, + 0x8ab2b763, + 0x42b922d2, + 0x7000b0c2, + 0xa0e0b20f, + 0x978ea0e3, + 0xa764b764, + 0xb110b0f6, + 0x8210b113, + 0x42c322f0, + 0x8002b0f5, + 0xa006a004, + 0x7203a001, + 0xc0707204, + 0x71006791, + 0xb0f6b764, + 0xa20fb0c5, + 0xb0f57100, + 0x7810a0c5, + 0x90029030, + 0x90407820, + 0xb0729060, + 0x6677a20f, + 0xa764978a, + 0x6190b0f6, + 0x8180b88c, + 0x392489a4, + 0x00043184, + 0xc0809184, + 0x73766791, + 0x72487276, + 0x72027206, + 0x73057204, + 0x60597306, + 0x91b01200, + 0xc090b32d, + 0xb0f86791, + 0xb0f16504, + 0xb88eb0c1, + 0xe0a08a73, + 0x98729863, + 0x71006791, + 0xb0f1a0c1, + 0xb0c2b0f2, + 0x120ac00f, + 0x1a1f120f, + 0x12031204, + 0x39888ad8, + 0x06183958, + 0xb0f27100, + 0x8b10b88d, + 0x3d803180, + 0x6320100b, + 0x121a120b, + 0x16131a14, + 0xb0f27100, + 0x8b10b88d, + 0x3d803180, + 0x7100140b, + 0xb88db0f2, + 0x31808b10, + 0x140b3d80, + 0x7100100d, + 0xb88db0f2, + 0x31808b10, + 0x140b3d80, + 0x100c140d, + 0x4f3d22fd, + 0x120d10d0, + 0x7100180d, + 0xb88db0f2, + 0x31808b10, + 0x180b3d80, + 0x100e140c, + 0x4f4b22fc, + 0x120c10c0, + 0x7100180c, + 0xb88db0f2, + 0x31808b10, + 0x180b3d80, + 0x22fe140e, + 0x10e04f58, + 0x180e120e, + 0xb0f27100, + 0x8b10b88d, + 0x3d803180, + 0x7100180b, + 0xb88db0f2, + 0x31808b10, + 0x180b3d80, + 0x398b10b6, + 0x088b397b, + 0x161f919b, + 0x1e008150, + 0x1a104373, + 0x4f731cf0, + 0x6785637e, + 0x437d1e1a, + 0x431c1e4a, + 0xb0f27100, + 0x1614121a, + 0x63141613, + 0x9863e0b0, + 0x67919874, + 0xb0f2a0c2, + 0xc01a62e4, + 0x140d7880, + 0x1cec140e, + 0xc03a4b8d, + 0x1cdc10ec, + 0xc04a4b90, + 0x98507000, + 0x22008840, + 0xb8304792, + 0x00007000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc1020000, + 0xc0013162, + 0x1e008150, + 0x1a1043f7, + 0x102063f9, + 0x6f131a10, + 0x16116e23, + 0x6bf91612, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_mce_wmbus_smode(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 512; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchWmbusSmodeMce[i]; + } +#else + const uint32_t *pS = patchWmbusSmodeMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 64; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ble.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ble.h new file mode 100644 index 0000000..3da38a3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ble.h @@ -0,0 +1,425 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_ble.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC1350 Bluetooth Low Energy +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_BLE_H +#define _RF_PATCH_RFE_BLE_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchBleRfe[311] = { + 0x0000612c, + 0x0002147f, + 0x00050006, + 0x0008000f, + 0x00520048, + 0x003fff80, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x00000000, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x003f0000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0x00000007, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x40632241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x686f1614, + 0x10257000, + 0x9100c050, + 0xc140c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x64537000, + 0x1031c052, + 0x31610631, + 0x645602c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006456, + 0x9101c051, + 0xc0e2cc01, + 0x64536456, + 0xc0c2c111, + 0xb0546456, + 0xa0547100, + 0x80f0b064, + 0x40b12200, + 0x90b01240, + 0xc2f0b032, + 0xc11168bc, + 0x6456c122, + 0x68c1c0b0, + 0x9101c051, + 0x3182c0e2, + 0x00028260, + 0xb1109132, + 0x68cbc230, + 0x00000000, + 0x12800000, + 0xb03290b0, + 0x64537000, + 0xc122c101, + 0xc1016456, + 0x6456c0c2, + 0x64998253, + 0x90b012c0, + 0x7000b032, + 0xc2726453, + 0x6456c081, + 0xc111c122, + 0xc0026456, + 0x6456c111, + 0xc331c062, + 0xc3626456, + 0x6456c111, + 0xc111c302, + 0x82536456, + 0x64993953, + 0x645bc3e2, + 0x40f62211, + 0xc881c242, + 0xc2526456, + 0x6456c111, + 0xcee1c272, + 0xc2026456, + 0x6456c881, + 0xc801c202, + 0xc0b06456, + 0x7000690a, + 0xc2426453, + 0x6456c801, + 0xc011c252, + 0xc2726456, + 0x6456c0e1, + 0xc101c002, + 0xc0626456, + 0x6456c301, + 0xc101c122, + 0xc3626456, + 0x6456c101, + 0xc101c302, + 0x82536456, + 0x70006499, + 0x00000000, + 0x00000000, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xb0608081, + 0x8092a050, + 0x92f1eff0, + 0x664f9302, + 0x45502241, + 0xc1f18080, + 0x16300410, + 0x14011101, + 0x61636c01, + 0x61656164, + 0x61676166, + 0x61696168, + 0x616d616b, + 0x6171616f, + 0x624c6249, + 0xc0f28091, + 0x31210421, + 0x2a428082, + 0x16321412, + 0x14211101, + 0x617e6c01, + 0x618461a0, + 0x617e624c, + 0x618461a0, + 0x6173624c, + 0x61736173, + 0x61736173, + 0x64a86173, + 0x64d36173, + 0x64e06173, + 0x650c6173, + 0x66596173, + 0x80826173, + 0x92f2dfe0, + 0xb0b0664f, + 0xb0b1617a, + 0x72057306, + 0x6130b030, + 0x664fcfd0, + 0xc003c284, + 0x6468c3c0, + 0x91507890, + 0x31107860, + 0x14107861, + 0x78509200, + 0x78613140, + 0x31400010, + 0x00107871, + 0x78b09210, + 0x78819260, + 0x78309221, + 0x78413140, + 0x92300010, + 0x91f0c010, + 0x61736655, + 0x80f0a054, + 0x45a82250, + 0x22008040, + 0x61a0463f, + 0x9160c800, + 0xb0508159, + 0x22418091, + 0xcfc04607, + 0x8212664f, + 0x39823182, + 0x10283942, + 0x82126477, + 0x041212f1, + 0x311f102f, + 0xc140142f, + 0x6f0d1420, + 0x10de396d, + 0x044ec3f4, + 0x3182c082, + 0x396d002e, + 0x3182c0a2, + 0x821a002d, + 0x8220398a, + 0x39803180, + 0x180bc00b, + 0x823078ac, + 0x10023940, + 0x3001c011, + 0x1801c010, + 0x31821802, + 0x26c10021, + 0xb0039191, + 0xb063b013, + 0x8203b053, + 0x80411439, + 0x463f2201, + 0x91c481b4, + 0x189581d5, + 0x4df51cb5, + 0x4a2d1cc5, + 0x80f09165, + 0x41e52210, + 0x913d6205, + 0x913eb110, + 0x9165b110, + 0x8159920f, + 0x18ab14f9, + 0x80f010bc, + 0x41a02250, + 0x46052210, + 0xcfb061e5, + 0xb063664f, + 0x10008230, + 0x0420c0f2, + 0xc0111002, + 0xc0103001, + 0x18021801, + 0x00213182, + 0x919126c1, + 0xb0139191, + 0xb063b003, + 0xb064b053, + 0x7100b054, + 0x22018041, + 0xb063463f, + 0x80f0b064, + 0x41a02250, + 0x91c181b1, + 0x189181d1, + 0xb0319161, + 0x8212621d, + 0x39823182, + 0x10283942, + 0x81596477, + 0x14598205, + 0xc00b8220, + 0x78ac180b, + 0x7100c080, + 0x6a3bb063, + 0x820161e5, + 0x31828162, + 0xefa03d82, + 0x930292f1, + 0xa003664f, + 0x80a26173, + 0x61736477, + 0x7100b050, + 0x92e06173, + 0x220082d0, + 0xb2c04650, + 0x80a07000, + 0x426c22f0, + 0xc102b030, + 0xc0013162, + 0x1e0080a0, + 0x22f04265, + 0xe6d04266, + 0x39603160, + 0x10206266, + 0x6f131a10, + 0x16116e23, + 0x6a671612, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_ble(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 311; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchBleRfe[i]; + } +#else + const uint32_t *pS = patchBleRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 38; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_brepeat.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_brepeat.h new file mode 100644 index 0000000..62ddaf5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_brepeat.h @@ -0,0 +1,539 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_brepeat.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 for 1.2kbps and 2.4kbps Generic FSK +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_BREPEAT_H +#define _RF_PATCH_RFE_BREPEAT_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchBrepeatRfe[429] = { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x6599658a, + 0x8220c088, + 0x39803950, + 0x409f1e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40a91e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40af2200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6485, + 0xc122c111, + 0xc1706442, + 0xc11168c2, + 0x6442c0c2, + 0x68c7c170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276572, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26572, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f3c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_brepeat(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 429; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchBrepeatRfe[i]; + } +#else + const uint32_t *pS = patchBrepeatRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 53; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk.h new file mode 100644 index 0000000..f35a113 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk.h @@ -0,0 +1,539 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_genfsk.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Generic FSK +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_GENFSK_H +#define _RF_PATCH_RFE_GENFSK_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchGenfskRfe[429] = { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x6599658a, + 0x8220c088, + 0x39803950, + 0x409f1e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40a91e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40af2200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6485, + 0xc122c111, + 0xc1706442, + 0xc11168c2, + 0x6442c0c2, + 0x68c7c170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276572, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26572, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f3c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_genfsk(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 429; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchGenfskRfe[i]; + } +#else + const uint32_t *pS = patchGenfskRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 53; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk_ant_div.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk_ant_div.h new file mode 100644 index 0000000..cebbc44 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk_ant_div.h @@ -0,0 +1,475 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_genfsk_ant_div.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Generic FSK antenna diversity +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_GENFSK_ANT_DIV_H +#define _RF_PATCH_RFE_GENFSK_ANT_DIV_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchGenfskAntDivRfe[365] = { + 0x0000613b, + 0x1307147f, + 0x35f1004d, + 0x0003ffa6, + 0x003f0a91, + 0xf00ff000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x003f0000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0xc0500007, + 0x70009100, + 0x9100c070, + 0x31827000, + 0x91310021, + 0x7000b110, + 0xb1018101, + 0x3182a100, + 0xb1109132, + 0x10119101, + 0x22418141, + 0x06f1404e, + 0xc0517000, + 0x18309101, + 0x31833910, + 0x3118d008, + 0x00316f41, + 0xb1109131, + 0x16141483, + 0x7000685a, + 0xc0501025, + 0xc3f49100, + 0x1420c0c0, + 0x10316f03, + 0xc0220441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0xc0820441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0x3182c0a2, + 0x91310021, + 0x1050b110, + 0x14053115, + 0x70009205, + 0xc052643e, + 0x06311031, + 0x02c13161, + 0xc1126441, + 0x39211031, + 0x31510671, + 0x644102e1, + 0xc0517000, + 0xcc019101, + 0x6441c0e2, + 0xc111643e, + 0x6441c0c2, + 0x7100b054, + 0xb064a054, + 0x220080f0, + 0xc111409c, + 0x6441c122, + 0x9101c051, + 0x3182c0e2, + 0x00028260, + 0xb1109132, + 0x68afc300, + 0x1240643e, + 0xb03290b0, + 0x39538253, + 0x64843953, + 0x68b9c360, + 0x90b01280, + 0x7000b032, + 0xc101643e, + 0x6441c122, + 0xc0c2c101, + 0x82536441, + 0x12c06484, + 0xb03290b0, + 0x643e7000, + 0xc081c272, + 0xc1226441, + 0x6441c111, + 0xc111c002, + 0xc0626441, + 0x6441c331, + 0xc111c362, + 0xc3026441, + 0x6441c111, + 0x39538253, + 0xc3e26484, + 0x22116446, + 0xc24240e1, + 0x6441c881, + 0xc111c252, + 0xc2726441, + 0x6441cee1, + 0xc881c202, + 0xc2026441, + 0x6441c801, + 0x68f5c0b0, + 0x643e7000, + 0xc801c242, + 0xc2526441, + 0x6441c011, + 0xc0e1c272, + 0xc0026441, + 0x6441c101, + 0xc301c062, + 0xc1226441, + 0x6441c101, + 0xc101c362, + 0xc3026441, + 0x6441c101, + 0x64848253, + 0x00007000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x73060000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x8080455b, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x616f616e, + 0x61716170, + 0x61736172, + 0x61766174, + 0x617a6178, + 0x62b6617c, + 0x809162b9, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x61a36186, + 0x62b9618c, + 0x61a36186, + 0x62b9618c, + 0x617e617e, + 0x617e617e, + 0x617e617e, + 0x617e6493, + 0x617e64be, + 0x617e64cb, + 0x617e64f7, + 0x617e66c6, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x613f9030, + 0x66bccff0, + 0xc003c1c4, + 0x6453c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x66c29200, + 0x8210617e, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0xa0bca040, + 0x78a080e1, + 0x90e10401, + 0x80f0a054, + 0x45bc2250, + 0x22008040, + 0x61b446ab, + 0x10ab822d, + 0x10c210bc, + 0xb0136462, + 0x6649b003, + 0xb050b053, + 0xb064b054, + 0x65fcb013, + 0x82106621, + 0x45cf22e0, + 0x7100662a, + 0x22018041, + 0x80f046ab, + 0x41af2250, + 0x221080f0, + 0xb06445df, + 0x41cf2231, + 0x664fb063, + 0xb06461cf, + 0x318f816f, + 0xdfe03d8f, + 0x66bc92ff, + 0x80417100, + 0x46ab2201, + 0x80f0b064, + 0x41f52250, + 0x8211b063, + 0x45f422c1, + 0x6698664f, + 0x816161e6, + 0x31818172, + 0x31823d81, + 0x61af3d82, + 0x3d8380f3, + 0x4e0818d3, + 0x16130bf3, + 0x4a201ce3, + 0x81e391c3, + 0x620d143b, + 0x4a201ce3, + 0x81e391c3, + 0x1cab183b, + 0x1c9b4e1c, + 0x1cbc4a1e, + 0x10b24220, + 0x22d08210, + 0x80f0421a, + 0x46202210, + 0x62206462, + 0x621110ab, + 0x6211109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6a24, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4a3b1c12, + 0xb032b0e2, + 0x92f2dfd0, + 0xc7f166bc, + 0x4e3f1421, + 0x9162c812, + 0x31829172, + 0x16223942, + 0x002080e0, + 0xb03190e0, + 0x12087000, + 0xc800c006, + 0x91709160, + 0x82017000, + 0x91c081b0, + 0x181081d0, + 0x18108151, + 0x80e11406, + 0x31828242, + 0x1c203d82, + 0x22214a67, + 0xb0e24673, + 0x1002b032, + 0x92f2dfc0, + 0x102066bc, + 0x22216273, + 0x1a324273, + 0x4e731c20, + 0xb032a0e2, + 0xdfb01002, + 0x66bc92f2, + 0x82311020, + 0xc0f03941, + 0x1e010401, + 0x16184281, + 0x3010c010, + 0x46971c08, + 0x3c101060, + 0xc7f11006, + 0x4e851461, + 0x9166c816, + 0x31818171, + 0x1c163d81, + 0x91764a8c, + 0x39463186, + 0x80e01686, + 0x048078b8, + 0x90e00060, + 0xc006b031, + 0x70001208, + 0x31818161, + 0x82403d81, + 0x18013980, + 0x4aaa1cf1, + 0x80b01401, + 0x46aa22c0, + 0xb033b0bc, + 0x92f1efa0, + 0x66bc930f, + 0x82017000, + 0x31828162, + 0xef903d82, + 0x930292f1, + 0xa00366bc, + 0x617e64f7, + 0x646280a2, + 0xb050617e, + 0x617e7100, + 0x82d092e0, + 0x46bd2200, + 0x7000b2c0, + 0x22f080a0, + 0xb03042d9, + 0x3162c102, + 0x80a0c001, + 0x42d21e00, + 0x42d322f0, + 0x3160eda0, + 0x62d33960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006ad4 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_genfsk_ant_div(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 365; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchGenfskAntDivRfe[i]; + } +#else + const uint32_t *pS = patchGenfskAntDivRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 45; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genook.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genook.h new file mode 100644 index 0000000..3c8b88b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genook.h @@ -0,0 +1,527 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_genook.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Generic OOK +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_GENOOK_H +#define _RF_PATCH_RFE_GENOOK_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchGenookRfe[425] = { + 0x00006122, + 0x0ec20ec1, + 0x0ec40ec3, + 0x0ec90ec6, + 0x0edf0ecf, + 0x0e3f0eef, + 0x0e3f0e3f, + 0x0e3f0e3f, + 0x0e3f0e3f, + 0x0d0f0e3f, + 0x0d3f0d1f, + 0x0d7f0d5f, + 0x0dbf0d9f, + 0x0dff0ddf, + 0x10000008, + 0x12031101, + 0x24f1004d, + 0x0018002e, + 0x72000a94, + 0x003ffffe, + 0x00ff007f, + 0x403003ff, + 0x40014000, + 0x40074003, + 0x404f400f, + 0x41cf40cf, + 0x47cf43cf, + 0x3fcf4fcf, + 0x1fcf2fcf, + 0x00000fcf, + 0x0008000f, + 0x003f0000, + 0x00000000, + 0x000000c0, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x406d2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x68791614, + 0x10257000, + 0x9100c050, + 0xc2b0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x645d7000, + 0x1031c052, + 0x31610631, + 0x646002c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006460, + 0xb054645d, + 0xa0547100, + 0x80f0b064, + 0x40b32200, + 0xc122c111, + 0xc3006460, + 0x645d68be, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0xc36064a3, + 0x128068c8, + 0xb03290b0, + 0x645d7000, + 0xc122c101, + 0xc1016460, + 0x6460c0c2, + 0x64a38253, + 0x90b012c0, + 0x7000b032, + 0xc272645d, + 0x6460c081, + 0xc111c122, + 0xc0026460, + 0x6460c111, + 0xc331c062, + 0xc3626460, + 0x6460c111, + 0xc111c302, + 0x82536460, + 0x64a33953, + 0x6465c3e2, + 0x40f02211, + 0xc881c242, + 0xc2526460, + 0x6460c111, + 0xcee1c272, + 0xc2026460, + 0x6460c881, + 0xc801c202, + 0xc0b06460, + 0x70006904, + 0xc242645d, + 0x6460c801, + 0xc011c252, + 0xc2726460, + 0x6460c0e1, + 0xc101c002, + 0xc0626460, + 0x6460c301, + 0xc101c122, + 0xc3626460, + 0x6460c101, + 0xc101c302, + 0x82536460, + 0x700064a3, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xb0608081, + 0x8092a050, + 0x224180a2, + 0x80804543, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61556154, + 0x61576156, + 0x61596158, + 0x615c615a, + 0x6160615e, + 0x62dd6162, + 0x809162e0, + 0x80823111, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x61836170, + 0x62e06176, + 0x61836170, + 0x62e06176, + 0x61636163, + 0x61636163, + 0x61636163, + 0x616364b2, + 0x616364cd, + 0x616364da, + 0x61636506, + 0x12106163, + 0x616890b0, + 0x90b01220, + 0x9050c010, + 0x90607a60, + 0x1210720e, + 0x61269030, + 0x674bcff0, + 0xc003c3b4, + 0x6472c3c0, + 0x91507a00, + 0x92107a10, + 0x92207a20, + 0x92307a30, + 0x92407a40, + 0x92607a50, + 0xa0bc6163, + 0xb060a0e1, + 0x80f0a054, + 0x458e2250, + 0x22008040, + 0x618546aa, + 0x674bcfe0, + 0x393080f0, + 0x22100630, + 0x79f14197, + 0x2200619c, + 0x79e1419b, + 0x79d1619c, + 0x822d9191, + 0x39408230, + 0x0410c0f1, + 0xc0121007, + 0x82193072, + 0x0419c0f1, + 0xc0f1821a, + 0x041a394a, + 0xc0f1821e, + 0x041e398e, + 0x10bc10ab, + 0x648110c2, + 0x7aa7c00f, + 0xb003b013, + 0xb053664e, + 0xb013b050, + 0xc0826624, + 0x6635668a, + 0xb0637100, + 0x22018041, + 0x80f046aa, + 0x41c02250, + 0x45c02210, + 0x46c822f0, + 0x668ac082, + 0x392010f0, + 0x81d391c0, + 0x10306654, + 0x4dde18d3, + 0x16130bf3, + 0x49f21ce3, + 0x81e391c3, + 0x61e3143b, + 0x49f21ce3, + 0x81e391c3, + 0x1cab183b, + 0x1c9b4e31, + 0x1cbc4a33, + 0x10b241f2, + 0x22d08210, + 0x80f041f0, + 0x45f22210, + 0x65f36481, + 0x10c061c0, + 0x4a0518b0, + 0x39101003, + 0x41fc1e00, + 0x3807380f, + 0x42152203, + 0x392010f0, + 0x1070180f, + 0x18073920, + 0x10036215, + 0x1801c001, + 0x1e013911, + 0x301f420d, + 0x22033017, + 0x10f04215, + 0x140f3920, + 0x39201070, + 0x66a11407, + 0x06f08230, + 0x80f13110, + 0x06313931, + 0x421f1e01, + 0xb0633810, + 0x6a1f7100, + 0x700010bc, + 0x06f08230, + 0x80f13110, + 0x06313931, + 0x422d1e01, + 0xb0633810, + 0x6a2d7100, + 0x10ab7000, + 0x109b61e7, + 0x10f261e7, + 0x91c23922, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4a461c12, + 0xb032b0e1, + 0x674bcfd0, + 0x1421c7f1, + 0xc8124e4a, + 0x91729162, + 0x7000b031, + 0xc0061208, + 0x9160c800, + 0x70009170, + 0x10308201, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4a661c20, + 0x46702211, + 0xb032b0e1, + 0x674bcfc0, + 0x42702211, + 0x1c201a32, + 0xa0e14e70, + 0xdfb0b032, + 0x674b92f2, + 0x39418231, + 0x1e0106f1, + 0x1618427b, + 0x3010c010, + 0x46891c08, + 0xc7f13c16, + 0x4e7f1461, + 0x9166c816, + 0x31818171, + 0x1c163d81, + 0x91764a86, + 0xc006b031, + 0x70001208, + 0x312381b3, + 0x187110f1, + 0x10153c21, + 0x4e931c37, + 0x10376295, + 0x14176296, + 0x4a991c3f, + 0x103f629b, + 0x1e0162a1, + 0x1211469e, + 0x42a11e0f, + 0x10f1181f, + 0x39311471, + 0x063080e0, + 0x14103121, + 0x700090e0, + 0x81628201, + 0x3d823182, + 0x92f1efa0, + 0x674b9302, + 0x6506a003, + 0x81616163, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014ac7, + 0x22c080b0, + 0xb0bc46c7, + 0xef90b033, + 0x930f92f1, + 0x7000674b, + 0xb063a003, + 0xb054b064, + 0x6506b0e0, + 0x80407100, + 0x46aa2200, + 0x64dab064, + 0x7100a0e0, + 0x22008040, + 0xb06446aa, + 0xb003a054, + 0x80a261c0, + 0x61636481, + 0x39808260, + 0x10083950, + 0x82693128, + 0xc1f13989, + 0xc01b0419, + 0x1c9a79ca, + 0x109a4af0, + 0x62f31209, + 0x1a1918a9, + 0xb0e1c00b, + 0xb064b054, + 0x80f07100, + 0x47382240, + 0x42fd2210, + 0x645a631a, + 0x1e1b1090, + 0xc0214308, + 0x10001401, + 0x673a1000, + 0x67426b01, + 0xc131b101, + 0x6f1214a1, + 0xb1109132, + 0x1a1010a0, + 0x1401c131, + 0x10001000, + 0x6b10673a, + 0xc0c2c101, + 0x62f56460, + 0x645d6742, + 0xc0c2c111, + 0x10a06460, + 0x10a2c131, + 0x14211802, + 0x6b20673a, + 0x43371e1b, + 0xc021a101, + 0x91326f12, + 0x1090b110, + 0x43371e00, + 0xc0211a10, + 0x18021092, + 0x673a1421, + 0x62f56b31, + 0x6163a054, + 0x10801004, + 0x10406b3c, + 0x91326f12, + 0x7000b110, + 0x9101c051, + 0x3182c0e2, + 0x0002cc00, + 0xb1109132, + 0x92e07000, + 0x220082d0, + 0xb2c0474c, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_genook(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 425; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchGenookRfe[i]; + } +#else + const uint32_t *pS = patchGenookRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 53; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + *pD++ = t1; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ghs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ghs.h new file mode 100644 index 0000000..22d8ba1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ghs.h @@ -0,0 +1,602 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_ghs.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Generic 4FSK up to 1.5Mbps +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_GHS_H +#define _RF_PATCH_RFE_GHS_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchGhsRfe[498] = { + 0x00006256, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x0100003f, + 0xff071f00, + 0x4030f00f, + 0x40014000, + 0x40074003, + 0x404f400f, + 0x41cf40cf, + 0x47cf43cf, + 0x3fcf4fcf, + 0x1fcf2fcf, + 0x00000fcf, + 0x00000000, + 0x00000000, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x005500a5, + 0x00550055, + 0x00550050, + 0x00550055, + 0x00aa0050, + 0x00aa00aa, + 0x00aa0005, + 0x00aa00aa, + 0x00000005, + 0x00000000, + 0x00000000, + 0x00000000, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x003f0000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0x00000007, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0500000, + 0x70009100, + 0x9100c070, + 0x31827000, + 0x91310021, + 0x7000b110, + 0xb1018101, + 0x3182a100, + 0xb1109132, + 0x10119101, + 0x22418141, + 0x06f140a0, + 0xc0517000, + 0x18309101, + 0x31833910, + 0x3118d008, + 0x00316f41, + 0xb1109131, + 0x16141483, + 0x700068ac, + 0xc0501025, + 0xc3f49100, + 0x1420c0d0, + 0x10316f03, + 0xc0220441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0xc0820441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0x3182c0a2, + 0x91310021, + 0x1052b110, + 0x31151050, + 0x92051405, + 0x39448244, + 0x31431023, + 0x92431443, + 0x10308243, + 0xc1d13920, + 0x6f151401, + 0x31130633, + 0x40e71e03, + 0x06353835, + 0x1c2440ef, + 0x26f54cee, + 0x60ef90e5, + 0x700090e5, + 0xc0526490, + 0x06311031, + 0x02c13161, + 0xc1126493, + 0x39211031, + 0x31510671, + 0x649302e1, + 0x82207000, + 0x041078a1, + 0x663d4168, + 0xc088664c, + 0x39508220, + 0x1e003980, + 0xc041410e, + 0x14183001, + 0xc0891a18, + 0x39608230, + 0x1e003980, + 0xc0414118, + 0x14193001, + 0x648d1a19, + 0xb1109136, + 0xb1109134, + 0x7100b054, + 0xb064a054, + 0x220080f0, + 0x1240411e, + 0xb03290b0, + 0xc1116490, + 0x6493c122, + 0x692dc170, + 0xc0c2c111, + 0xc1706493, + 0xc0506932, + 0x72279100, + 0x16159298, + 0x10421614, + 0xc1f01053, + 0x31318221, + 0x39813931, + 0xb0513131, + 0x6625b270, + 0x92997227, + 0x1062b270, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0x6625101b, + 0x3182c0e2, + 0x31808260, + 0x00023980, + 0x7100b061, + 0xb1109132, + 0xb061a051, + 0x82537227, + 0x39533953, + 0xc23064f0, + 0x00006962, + 0x90b01280, + 0x7000b032, + 0x9101c051, + 0xc0e2cc01, + 0x64906493, + 0xc0c2c111, + 0xb0546493, + 0xa0547100, + 0x80f0b064, + 0x41712200, + 0x90b01240, + 0xc2f0b032, + 0xc111697c, + 0x6493c122, + 0x6981c0b0, + 0x9101c051, + 0x3182c0e2, + 0x00028260, + 0xb1109132, + 0x39538253, + 0x64f03953, + 0x698fc050, + 0x12800000, + 0xb03290b0, + 0x82537000, + 0x821064f0, + 0x419d22f0, + 0x0000c960, + 0x8220699b, + 0x041078a1, + 0xc05041d0, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x72276631, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x6631101a, + 0xb061a051, + 0xc0b07227, + 0x649069c0, + 0xc122c101, + 0xc1016493, + 0x6493c0c2, + 0x648d1a15, + 0xb1109135, + 0x90b012c0, + 0x7000b032, + 0xc1016490, + 0x6493c122, + 0xc0c2c101, + 0x82536493, + 0x12c064f0, + 0xb03290b0, + 0x64907000, + 0xc081c272, + 0xc1226493, + 0x6493c111, + 0xc111c002, + 0xc0626493, + 0x6493c331, + 0xc111c362, + 0xc3026493, + 0x6493c111, + 0x39538253, + 0xc3e264f0, + 0x22116498, + 0xc24241f3, + 0x6493c881, + 0xc111c252, + 0xc2726493, + 0x6493cee1, + 0xc881c202, + 0xc2026493, + 0x6493c801, + 0x6a07c0b0, + 0x64907000, + 0xc801c242, + 0xc2526493, + 0x6493c011, + 0xc0e1c272, + 0xc0026493, + 0x6493c101, + 0xc301c062, + 0xc1226493, + 0x6493c101, + 0xc101c362, + 0xc3026493, + 0x6493c101, + 0x64f08253, + 0xb0617000, + 0x14127100, + 0x4e2d1c23, + 0xb1109133, + 0x91327000, + 0x6a25b110, + 0xb0617000, + 0x18137100, + 0x4a391c32, + 0xb1109132, + 0x91337000, + 0x6a31b110, + 0xc0c27000, + 0x10156498, + 0x1612c0c2, + 0x31416498, + 0xc0c01415, + 0x14053180, + 0x78b01054, + 0x70000404, + 0x3186c0e6, + 0x1416cc01, + 0x82611067, + 0x0401c3f0, + 0x70001417, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xb0608081, + 0x8092a050, + 0x46762241, + 0xc1f18080, + 0x16300410, + 0x14011101, + 0x62896c01, + 0x628b628a, + 0x628d628c, + 0x628f628e, + 0x62936291, + 0x62896295, + 0x63db63d8, + 0xc0f28091, + 0x31210421, + 0x2a428082, + 0x16321412, + 0x14211101, + 0x629f6c01, + 0x62a562bb, + 0x629f63db, + 0x62a562bb, + 0x629763db, + 0x62976297, + 0x62976297, + 0x64ff6297, + 0x65956297, + 0x65dd6297, + 0x66096297, + 0x12106297, + 0x720e90b0, + 0x72057306, + 0x90301210, + 0xcff0625a, + 0xc64467de, + 0xc3c0c003, + 0x784064a5, + 0x78509150, + 0x78609210, + 0x78709220, + 0x78809230, + 0x78909260, + 0x78309290, + 0x82109190, + 0x06f03940, + 0x31101001, + 0x92001410, + 0xa0e06297, + 0x80f0a054, + 0x46c42250, + 0x22008040, + 0x62bc47cd, + 0x822da040, + 0x398d318d, + 0xc0f18210, + 0x10090410, + 0x394a821a, + 0x8210041a, + 0x04103980, + 0x10ab100e, + 0x10c010bc, + 0x14c03140, + 0x10c29240, + 0xcfe064b4, + 0xb01367de, + 0x67a3b003, + 0xb050b053, + 0xb064b054, + 0x675bb013, + 0x22e08210, + 0x679446ee, + 0x91c081b0, + 0xb06381d5, + 0x80417100, + 0x47cd2201, + 0x221080f0, + 0xb064472a, + 0x42ee2231, + 0x81b0b063, + 0x81d391c0, + 0x4f0118d3, + 0x67a981d5, + 0x710062ee, + 0x22018041, + 0x80f047cd, + 0x472a2210, + 0x2231b064, + 0xb0634301, + 0x91c081b0, + 0x105081d3, + 0x18301035, + 0x4eee16a0, + 0x4aee18d3, + 0x1cbc6750, + 0x10b242ee, + 0x10bc64b4, + 0xcfd0675b, + 0x637267de, + 0x221080f0, + 0x10a2472a, + 0x675b64b4, + 0x675b675b, + 0x62c4675b, + 0x816fb064, + 0x3d8f318f, + 0x92ffdfc0, + 0x710067de, + 0x22018041, + 0xb06447cd, + 0x225080f0, + 0xb0634345, + 0x22c18211, + 0x67a9473f, + 0x82116331, + 0x473122d1, + 0x221080f0, + 0x8161472a, + 0x31818172, + 0x31823d81, + 0xefb03d82, + 0x930292f1, + 0x62bb67de, + 0x81e391c3, + 0x1cab183b, + 0x10ab4b57, + 0x1c9b7000, + 0x109b4f5a, + 0x82307000, + 0x823106f0, + 0x06f13941, + 0x3012c012, + 0x7100b063, + 0x436d1e01, + 0x81611618, + 0x3d813181, + 0x1c281416, + 0xb0314770, + 0xc006c008, + 0x70006b62, + 0xb0638290, + 0x80417100, + 0x47cd2201, + 0x221180f1, + 0x10074793, + 0x91c081b0, + 0x18d381d3, + 0x4b8e18e3, + 0x675014e3, + 0x438e1cbc, + 0x64b410b2, + 0x820310bc, + 0x92f3dfa0, + 0x675b67de, + 0x107067a9, + 0xcf906b73, + 0x632067de, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0xc7f11812, + 0x4f9f1421, + 0x9162c812, + 0xb0319172, + 0xc0087000, + 0xc800c006, + 0x91709160, + 0x82017000, + 0x91c081b0, + 0x181081d0, + 0x18108151, + 0x82311406, + 0x06f13941, + 0x43be1e01, + 0xc0101618, + 0x1c083010, + 0x106047cc, + 0x10063c10, + 0x1461c7f1, + 0xc8164fc2, + 0x81719166, + 0x3d813181, + 0x4bc91c16, + 0xb0319176, + 0xc008c006, + 0x82017000, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa00367de, + 0x62976609, + 0x64b480a2, + 0xb0506297, + 0x62977100, + 0x82d092e0, + 0x47df2200, + 0x7000b2c0 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_ghs(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 498; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchGhsRfe[i]; + } +#else + const uint32_t *pS = patchGhsRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 62; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + *pD++ = t1; + *pD++ = t2; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_hsp_4mbps.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_hsp_4mbps.h new file mode 100644 index 0000000..891ee2a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_hsp_4mbps.h @@ -0,0 +1,423 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_hsp_4mbps.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 4Mbps High speed mode +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_HSP_4MBPS_H +#define _RF_PATCH_RFE_HSP_4MBPS_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchHsp4mbpsRfe[321] = { + 0x0000611f, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x00000000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0x40300007, + 0x40014000, + 0x40074003, + 0x404f400f, + 0x41cf40cf, + 0x47cf43cf, + 0x3fcf4fcf, + 0x1fcf2fcf, + 0x02070fcf, + 0x4040067f, + 0x40404040, + 0x20403040, + 0x00401040, + 0x01c000c0, + 0x07c003c0, + 0x0fc10fc0, + 0x0fc70fc3, + 0xc0500fcf, + 0x70009100, + 0x9100c070, + 0x31827000, + 0x91310021, + 0x7000b110, + 0xb1018101, + 0x3182a100, + 0xb1109132, + 0x10119101, + 0x22418141, + 0x06f14056, + 0xc0517000, + 0x18309101, + 0x31833910, + 0x3118d008, + 0x00316f41, + 0xb1109131, + 0x16141483, + 0x70006862, + 0xc0501025, + 0xc3f49100, + 0x1420c210, + 0x10316f03, + 0xc0220441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0xc0820441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0x3182c0a2, + 0x91310021, + 0x1050b110, + 0x14053115, + 0x70009205, + 0xc0526446, + 0x06311031, + 0x02c13161, + 0xc1126449, + 0x39211031, + 0x31510671, + 0x644902e1, + 0xc0517000, + 0xcc019101, + 0x6449c0e2, + 0xc1116446, + 0x6449c0c2, + 0x7100b054, + 0xb064a054, + 0x220080f0, + 0xc11140a4, + 0x6449c122, + 0x9101c051, + 0x3182c0e2, + 0x00028260, + 0xb1109132, + 0x68b7c300, + 0x12406446, + 0xb03290b0, + 0x39538253, + 0x648c3953, + 0x68c1c360, + 0x90b01280, + 0x7000b032, + 0xc1016446, + 0x6449c122, + 0xc0c2c101, + 0x82536449, + 0x12c0648c, + 0xb03290b0, + 0x64467000, + 0xc081c272, + 0xc1226449, + 0x6449c111, + 0xc111c002, + 0xc0626449, + 0x6449c331, + 0xc111c362, + 0xc3026449, + 0x6449c111, + 0x39538253, + 0xc3e2648c, + 0x2211644e, + 0xc24240e9, + 0x6449c881, + 0xc111c252, + 0xc2726449, + 0x6449cee1, + 0xc881c202, + 0xc2026449, + 0x6449c801, + 0x68fdc0b0, + 0x64467000, + 0xc801c242, + 0xc2526449, + 0x6449c011, + 0xc0e1c272, + 0xc0026449, + 0x6449c101, + 0xc301c062, + 0xc1226449, + 0x6449c101, + 0xc101c362, + 0xc3026449, + 0x6449c101, + 0x648c8253, + 0x00007000, + 0x00000000, + 0x73060000, + 0x720b7205, + 0xb050720e, + 0xb0607100, + 0x8081a050, + 0x22418092, + 0x8080453e, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61526151, + 0x61546153, + 0x61566155, + 0x61596157, + 0x615d615b, + 0x6151615f, + 0xc0f28091, + 0x31210421, + 0x2a428082, + 0x16321412, + 0x14211101, + 0x61706c01, + 0x6174618b, + 0x61706151, + 0x6174618b, + 0x61616151, + 0x61616161, + 0x61616161, + 0x649b6161, + 0x64c66161, + 0x64d36161, + 0x64ff6161, + 0x666e6161, + 0x12106161, + 0x616690b0, + 0x90b01220, + 0x7306720e, + 0x12107205, + 0x61239030, + 0x00000000, + 0x00000000, + 0xc003c024, + 0x645bc3c0, + 0x9159c4b9, + 0x9160c800, + 0x9200c2d0, + 0x9260c3f0, + 0x3140c060, + 0x0010c0f1, + 0xc0213140, + 0x92100010, + 0x9221c371, + 0x00006161, + 0x00000000, + 0x73060000, + 0x82188159, + 0x108f108e, + 0x041ec0f1, + 0x041f394f, + 0x664110f2, + 0x10f010f7, + 0x14f03110, + 0x822b1008, + 0x39808210, + 0x180a10ba, + 0x140c10bc, + 0x1210c04d, + 0x722490e0, + 0x8040a054, + 0x461c2200, + 0x221080f0, + 0x61a545ae, + 0x72248244, + 0x222180f1, + 0x7b104604, + 0x662c9190, + 0x1ca581d5, + 0x1cc549e1, + 0x1cb54dd4, + 0x18b549c7, + 0x4a001cd5, + 0x42001ce7, + 0x2204b240, + 0x1a174200, + 0x105061ee, + 0x180510b5, + 0x4a001cd5, + 0x42001cf7, + 0x2204b240, + 0x16174200, + 0x620061ee, + 0x42001ce7, + 0x91c518b5, + 0x107081e5, + 0x1ce01850, + 0x100749df, + 0x10e761ee, + 0x1cf761ee, + 0x10b14200, + 0x91c11851, + 0x107081e1, + 0x1cf01410, + 0x10074ded, + 0x10f761ee, + 0xa240b241, + 0x80f11072, + 0x46042221, + 0x82086641, + 0x9290c0c0, + 0xb051b061, + 0x92701250, + 0xb0617100, + 0x7227a051, + 0x22008040, + 0x621141ae, + 0x91907b20, + 0x8203662c, + 0x31858165, + 0xb0313d85, + 0x92f3eff0, + 0x66649305, + 0xb054a003, + 0x7100b050, + 0x22018041, + 0xb064461c, + 0x222080f0, + 0x6211418b, + 0xa050b060, + 0x31828162, + 0x82033d82, + 0x92f3efe0, + 0x66649302, + 0x6161720e, + 0x00000000, + 0x00000000, + 0xb013b003, + 0xb0531201, + 0x7100b050, + 0x22018041, + 0xb063461c, + 0x91c381b3, + 0x188581d5, + 0x91651895, + 0x00007000, + 0x00000000, + 0x10250000, + 0x9100c050, + 0x1420c330, + 0x10316f03, + 0x0401c3f0, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0xc3f01031, + 0xc0820401, + 0x00213182, + 0xb1109131, + 0x10313963, + 0x3182c0a2, + 0x91310021, + 0x1050b110, + 0x14053115, + 0x70009205, + 0x82d092e0, + 0x46652200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304281, + 0x3162c102, + 0x80a0c001, + 0x427a1e00, + 0x427b22f0, + 0x3160e820, + 0x627b3960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006a7c +}; + +PATCH_FUN_SPEC void rf_patch_rfe_hsp_4mbps(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 321; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchHsp4mbpsRfe[i]; + } +#else + const uint32_t *pS = patchHsp4mbpsRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 40; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + *pD++ = t1; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_lrm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_lrm.h new file mode 100644 index 0000000..6b71eff --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_lrm.h @@ -0,0 +1,539 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_lrm.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Legacy Long Range Mode +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_LRM_H +#define _RF_PATCH_RFE_LRM_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchLrmRfe[429] = { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x6599658a, + 0x8220c088, + 0x39803950, + 0x409f1e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40a91e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40af2200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6485, + 0xc122c111, + 0xc1706442, + 0xc11168c2, + 0x6442c0c2, + 0x68c7c170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276572, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26572, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f3c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_lrm(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 429; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchLrmRfe[i]; + } +#else + const uint32_t *pS = patchLrmRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 53; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_sl_longrange.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_sl_longrange.h new file mode 100644 index 0000000..8d19313 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_sl_longrange.h @@ -0,0 +1,539 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_sl_longrange.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Simplelink Long range +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_SL_LONGRANGE_H +#define _RF_PATCH_RFE_SL_LONGRANGE_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchSl_longrangeRfe[429] = { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x6599658a, + 0x8220c088, + 0x39803950, + 0x409f1e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40a91e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40af2200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6485, + 0xc122c111, + 0xc1706442, + 0xc11168c2, + 0x6442c0c2, + 0x68c7c170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276572, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26572, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f3c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_sl_longrange(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 429; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchSl_longrangeRfe[i]; + } +#else + const uint32_t *pS = patchSl_longrangeRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 53; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wb_dsss.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wb_dsss.h new file mode 100644 index 0000000..cf5f7a8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wb_dsss.h @@ -0,0 +1,539 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_wb_dsss.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 Wideband DSSS +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_WB_DSSS_H +#define _RF_PATCH_RFE_WB_DSSS_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchWb_dsssRfe[429] = { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x6599658a, + 0x8220c088, + 0x39803950, + 0x409f1e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40a91e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40af2200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6485, + 0xc122c111, + 0xc1706442, + 0xc11168c2, + 0x6442c0c2, + 0x68c7c170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276572, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26572, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f3c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_wb_dsss(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 429; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchWb_dsssRfe[i]; + } +#else + const uint32_t *pS = patchWb_dsssRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 53; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_ctmode.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_ctmode.h new file mode 100644 index 0000000..2ff29c6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_ctmode.h @@ -0,0 +1,539 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_wmbus_ctmode.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 WMBUS C- and T-Mode +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_WMBUS_CTMODE_H +#define _RF_PATCH_RFE_WMBUS_CTMODE_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchWmbus_ctmodeRfe[429] = { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x6599658a, + 0x8220c088, + 0x39803950, + 0x409f1e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40a91e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40af2200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6485, + 0xc122c111, + 0xc1706442, + 0xc11168c2, + 0x6442c0c2, + 0x68c7c170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276572, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26572, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f3c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_wmbus_ctmode(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 429; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchWmbus_ctmodeRfe[i]; + } +#else + const uint32_t *pS = patchWmbus_ctmodeRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 53; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_smode.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_smode.h new file mode 100644 index 0000000..7b8b7a0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_smode.h @@ -0,0 +1,539 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_wmbus_smode.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC13x0 WMBUS S-Mode +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_WMBUS_SMODE_H +#define _RF_PATCH_RFE_WMBUS_SMODE_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchWmbus_smodeRfe[429] = { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x6599658a, + 0x8220c088, + 0x39803950, + 0x409f1e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40a91e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40af2200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6485, + 0xc122c111, + 0xc1706442, + 0xc11168c2, + 0x6442c0c2, + 0x68c7c170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276572, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26572, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f3c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_wmbus_smode(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 429; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchWmbus_smodeRfe[i]; + } +#else + const uint32_t *pS = patchWmbus_smodeRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 53; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rom/driverlib.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rom/driverlib.c new file mode 100644 index 0000000..836200c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rom/driverlib.c @@ -0,0 +1,7824 @@ +//##### AUTO GENERATED FILE...DO NOT EDIT ##### +// +// This file is autogenerated from the project definition +// and module includes defined in the 'APITable.xls' +// +//##### AUTO GENERATED FILE...DO NOT EDIT ##### +#undef DEBUG +#include "lib_src/hw_ioc.h" +#include "lib_src/hw_nvic.h" +#include "lib_src/hw_gpio.h" +#include "lib_src/hw_flash.h" +#include "lib_src/hw_device.h" +#include "lib_src/hw_aux_tdc.h" +#include "lib_src/hw_ints.h" +#include "lib_src/hw_i2c.h" +#include "lib_src/hw_trng.h" +#include "lib_src/hw_gpt.h" +#include "lib_src/hw_uart.h" +#include "lib_src/hw_smph.h" +#include "lib_src/hw_aon_rtc.h" +#include "lib_src/hw_aon_wuc.h" +#include "lib_src/hw_vims.h" +#include "lib_src/hw_aon_event.h" +#include "lib_src/hw_memmap.h" +#include "lib_src/hw_aon_ioc.h" +#include "lib_src/hw_aux_wuc.h" +#include "lib_src/hw_sysctl.h" +#include "lib_src/hw_udma.h" +#include "lib_src/hw_ssi.h" +#include "lib_src/hw_factory_cfg.h" +#include "lib_src/hw_aux_sce.h" +#include "lib_src/hw_aon_sysctl.h" +#include "lib_src/hw_types.h" +#include "lib_src/hw_aux_smph.h" +#include "lib_src/hw_ddi.h" +#include "lib_src/hw_aux_timer.h" +#include "lib_src/hw_spis.h" +#include "lib_src/hw_prcm.h" +#include "lib_src/aon_event.h" +#include "lib_src/aon_ioc.h" +#include "lib_src/aon_rtc.h" +#include "lib_src/aon_wuc.h" +#include "lib_src/aux_ctrl.h" +#include "lib_src/aux_tdc.h" +#include "lib_src/aux_timer.h" +#include "lib_src/aux_wuc.h" +#include "lib_src/ddi.h" +#include "lib_src/flash.h" +#include "lib_src/i2c.h" +#include "lib_src/interrupt.h" +#include "lib_src/ioc.h" +#include "lib_src/prcm.h" +#include "lib_src/smph.h" +#include "lib_src/spis.h" +#include "lib_src/ssi.h" +#include "lib_src/timer.h" +#include "lib_src/trng.h" +#include "lib_src/uart.h" +#include "lib_src/udma.h" +#include "lib_src/vims.h" +#include "lib_src/cpu.h" +#include "lib_src/gpio.h" +#include "lib_src/debug.h" +// +// Include interrupt functions for based ROM code +// +//***************************************************************************** +// +//! Disable all external interrupts +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +uint32_t __attribute__((naked)) +CPUcpsid(void) +{ + uint32_t ui32Ret; + + // + // Read PRIMASK and disable interrupts + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n" + : "=r"(ui32Ret)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ui32Ret); +} +#endif +#if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN) +uint32_t +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + mrs r0, PRIMASK; + cpsid i; + bx lr +} +#endif +#if defined(__TI_COMPILER_VERSION__) +uint32_t +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Enable all external interrupts +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) + uint32_t __attribute__((naked)) +CPUcpsie(void) +{ + uint32_t ui32Ret; + + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n" + : "=r"(ui32Ret)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ui32Ret); +} +#endif +#if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN) + uint32_t +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + mrs r0, PRIMASK; + cpsie i; + bx lr +} +#endif +#if defined(__TI_COMPILER_VERSION__) + uint32_t +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif +//! \\addtogroup aon_event_api +//! @{ +//***************************************************************************** +// +//! Select event source for the specified MCU wakeup programmable event +// +//***************************************************************************** +void +AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // + // Check the arguments. + // + ASSERT((ui32MCUWUEvent == AON_EVENT_MCU_WU0) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU1) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU2) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU3)); + ASSERT(ui32EventSrc <= AON_EVENT_NULL); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL); + + if(ui32MCUWUEvent == AON_EVENT_MCU_WU0) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU0_EV_S; + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU1) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU1_EV_S; + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU2) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU2_EV_S; + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU3) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU3_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU3_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) = ui32Ctrl; +} +//***************************************************************************** +// +//! Get event source for the specified MCU wakeup programmable event +// +//***************************************************************************** +uint32_t +AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent) +{ + uint32_t ui32EventSrc; + + // + // Check the arguments. + // + ASSERT((ui32MCUWUEvent == AON_EVENT_MCU_WU0) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU1) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU2) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU3)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL); + + if(ui32MCUWUEvent == AON_EVENT_MCU_WU0) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU0_EV_M) >> + AON_EVENT_MCUWUSEL_WU0_EV_S); + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU1) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU1_EV_M) >> + AON_EVENT_MCUWUSEL_WU1_EV_S); + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU2) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU2_EV_M) >> + AON_EVENT_MCUWUSEL_WU2_EV_S); + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU3) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU3_EV_M) >> + AON_EVENT_MCUWUSEL_WU3_EV_S); + } + + // + // Should never get to this statement, but suppress warning. + // + ASSERT(0); + return(0); +} +//***************************************************************************** +// +//! Select event source for the specified AUX wakeup programmable event +// +//***************************************************************************** +void +AONEventAuxWakeUpSet(uint32_t ui32AUXWUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // + // Check the arguments. + // + ASSERT((ui32AUXWUEvent == AON_EVENT_AUX_WU0) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU1) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU2)); + ASSERT(ui32EventSrc <= AON_EVENT_NULL); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL); + + if(ui32AUXWUEvent == AON_EVENT_AUX_WU0) + { + ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU0_EV_S; + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU1) + { + ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU1_EV_S; + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU2) + { + ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU2_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL) = ui32Ctrl; +} +//***************************************************************************** +// +//! Get event source for the specified AUX wakeup programmable event +// +//***************************************************************************** +uint32_t +AONEventAuxWakeUpGet(uint32_t ui32AUXWUEvent) +{ + uint32_t ui32EventSrc; + + // + // Check the arguments. + // + ASSERT((ui32AUXWUEvent == AON_EVENT_AUX_WU0) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU1) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU2)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL); + + if(ui32AUXWUEvent == AON_EVENT_AUX_WU0) + { + return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU0_EV_M) >> + AON_EVENT_AUXWUSEL_WU0_EV_S); + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU1) + { + return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU1_EV_M) >> + AON_EVENT_AUXWUSEL_WU1_EV_S); + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU2) + { + return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU2_EV_M) >> + AON_EVENT_AUXWUSEL_WU2_EV_S); + } + + // + // Should never get to this statement, but suppress warning. + // + ASSERT(0); + return(0); +} +//***************************************************************************** +// +//! Select event source for the specified programmable event forwarded to the +//! MCU event fabric +// +//***************************************************************************** +void +AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // + // Check the arguments. + // + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + ASSERT(ui32EventSrc <= AON_EVENT_NULL); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL) = ui32Ctrl; +} +//***************************************************************************** +// +//! Get source for the specified programmable event forwarded to the MCU event +//! fabric. +// +//***************************************************************************** +uint32_t +AONEventMcuGet(uint32_t ui32MCUEvent) +{ + uint32_t ui32EventSrc; + + // + // Check the arguments. + // + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S); + } + + // + // Should never get to this statement, but supress warning. + // + ASSERT(0); + return(0); +} +//! @} +//! \\addtogroup aon_ioc_api +//! @{ +//***************************************************************************** +// +//! Setup the drive strength for all IOs on the chip +// +//***************************************************************************** +void +AONIOCDriveStrengthSet(uint32_t ui32LowDrvStr, uint32_t ui32MedDrvStr, + uint32_t ui32MaxDrvStr) +{ + ASSERT((ui32LowDrvStr == AONIOC_DRV_STR5_7_14) || + (ui32LowDrvStr == AONIOC_DRV_STR5_10_20) || + (ui32LowDrvStr == AONIOC_DRV_STR7_14_28) || + (ui32LowDrvStr == AONIOC_DRV_STR10_20_40) || + (ui32LowDrvStr == AONIOC_DRV_STR14_28_56) || + (ui32LowDrvStr == AONIOC_DRV_STR20_40_80) || + (ui32LowDrvStr == AONIOC_DRV_STR28_56_112) || + (ui32LowDrvStr == AONIOC_DRV_STR40_80_112)); + ASSERT((ui32MedDrvStr == AONIOC_DRV_STR5_7_14) || + (ui32MedDrvStr == AONIOC_DRV_STR5_10_20) || + (ui32MedDrvStr == AONIOC_DRV_STR7_14_28) || + (ui32MedDrvStr == AONIOC_DRV_STR10_20_40) || + (ui32MedDrvStr == AONIOC_DRV_STR14_28_56) || + (ui32MedDrvStr == AONIOC_DRV_STR20_40_80) || + (ui32MedDrvStr == AONIOC_DRV_STR28_56_112) || + (ui32MedDrvStr == AONIOC_DRV_STR40_80_112)); + ASSERT((ui32MaxDrvStr == AONIOC_DRV_STR5_7_14) || + (ui32MaxDrvStr == AONIOC_DRV_STR5_10_20) || + (ui32MaxDrvStr == AONIOC_DRV_STR7_14_28) || + (ui32MaxDrvStr == AONIOC_DRV_STR10_20_40) || + (ui32MaxDrvStr == AONIOC_DRV_STR14_28_56) || + (ui32MaxDrvStr == AONIOC_DRV_STR20_40_80) || + (ui32MaxDrvStr == AONIOC_DRV_STR28_56_112) || + (ui32MaxDrvStr == AONIOC_DRV_STR40_80_112)); + + // + // Set the minimum drive strength. + // + HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMIN) = ui32LowDrvStr & + AON_IOC_IOSTRMIN_GRAY_CODE_M; + // + // Set the medium drive strength. + // + HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMED) = ui32MedDrvStr & + AON_IOC_IOSTRMED_GRAY_CODE_M; + // + // Set the maximum drive strength. + // + HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMAX) = ui32MaxDrvStr & + AON_IOC_IOSTRMAX_GRAY_CODE_M; + +} +//***************************************************************************** +// +//! Get a specific drive level setting for all IOs +// +//***************************************************************************** +uint32_t +AONIOCDriveStrengthGet(uint32_t ui32DriveLevel) +{ + uint32_t ui32DrvStr; + + // + // Check the arguments. + // + ASSERT((ui32DriveLevel == AONIOC_MAX_DRIVE) || + (ui32DriveLevel == AONIOC_MED_DRIVE) || + (ui32DriveLevel == AONIOC_MIN_DRIVE)); + + // + // Get the specified drive strength level. + // + if(ui32DriveLevel == AONIOC_MAX_DRIVE) + { + ui32DrvStr = HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMAX); + } + else if(ui32DriveLevel == AONIOC_MED_DRIVE) + { + ui32DrvStr = HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMED); + } + else + { + ui32DrvStr = HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMIN); + } + + // + // Return the drive strength value. + // + return(ui32DrvStr); +} +//! @} +//! \\addtogroup aon_rtc_api +//! @{ +//***************************************************************************** +// +//! Check if the AON Real Time Clock is running. +// +//***************************************************************************** +uint32_t +AONRTCStatus(void) +{ + uint32_t ui32ChannelStatus; + uint32_t ui32RtcStatus; + + // + // Read out the status' + // + ui32ChannelStatus = HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL); + ui32RtcStatus = HWREG(AON_RTC_BASE + AON_RTC_O_CTL) & + AON_RTC_CTL_EN ? AON_RTC_ACTIVE : 0; + + // + // Return the status + // + ui32RtcStatus |= (ui32ChannelStatus & AON_RTC_CHCTL_CH2_EN ? + AON_RTC_CH2 : 0) | + (ui32ChannelStatus & AON_RTC_CHCTL_CH1_EN ? + AON_RTC_CH1 : 0) | + (ui32ChannelStatus & AON_RTC_CHCTL_CH0_EN ? + AON_RTC_CH0 : 0); + return ui32RtcStatus; +} +//***************************************************************************** +// +//! Clear event from a specified channel +// +//***************************************************************************** +void +AONRTCEventClear(uint32_t ui32Channel) +{ + // + // Check the arguments. + // + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH0; + } + else if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH1; + } + else if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH2; + } +} +//***************************************************************************** +// +//! Get event status for a specified channel +// +//***************************************************************************** +bool +AONRTCEventGet(uint32_t ui32Channel) +{ + // + // Check the arguments. + // + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + return ((HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) & + AON_RTC_EVFLAGS_CH0) ? true : false); + } + else if(ui32Channel & AON_RTC_CH1) + { + return ((HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) & + AON_RTC_EVFLAGS_CH1) ? true : false); + } + else if(ui32Channel & AON_RTC_CH2) + { + return ((HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) & + AON_RTC_EVFLAGS_CH2) ? true : false); + } + + return(false); +} +//***************************************************************************** +// +//! Set operational mode of channel 1 +// +//***************************************************************************** +void +AONRTCModeCh1Set(uint32_t ui32Mode) +{ + // + // Check the arguments. + // + ASSERT((ui32Mode == AON_RTC_MODE_CH1_CAPTURE) || + (ui32Mode == AON_RTC_MODE_CH1_COMPARE)); + + if(ui32Mode == AON_RTC_MODE_CH1_CAPTURE) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH1_CAPT_EN; + } + else if(ui32Mode == AON_RTC_MODE_CH1_COMPARE) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH1_CAPT_EN); + } +} +//***************************************************************************** +// +//! Get operational mode of channel 1 +// +//***************************************************************************** +uint32_t +AONRTCModeCh1Get(void) +{ + if(HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) & AON_RTC_CHCTL_CH1_CAPT_EN) + { + return(AON_RTC_MODE_CH1_CAPTURE); + } + else + { + return(AON_RTC_MODE_CH1_COMPARE); + } +} +//***************************************************************************** +// +//! Set operational mode of channel 2 +// +//***************************************************************************** +void +AONRTCModeCh2Set(uint32_t ui32Mode) +{ + // + // Check the arguments. + // + ASSERT((ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) || + (ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE)); + + if(ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH2_CONT_EN; + } + else if(ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH2_CONT_EN); + } +} +//***************************************************************************** +// +//! Get operational mode of channel 2 +// +//***************************************************************************** +uint32_t +AONRTCModeCh2Get(void) +{ + if(HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) & AON_RTC_CHCTL_CH2_CONT_EN) + { + return(AON_RTC_MODE_CH2_CONTINUOUS); + } + else + { + return(AON_RTC_MODE_CH2_NORMALCOMPARE); + } +} +//***************************************************************************** +// +//! Enable event operation for the specified channel +// +//***************************************************************************** +void +AONRTCChannelEnable(uint32_t ui32Channel) +{ + // + // Check the arguments. + // + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH0_EN; + } + else if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH1_EN; + } + else if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH2_EN; + } +} +//***************************************************************************** +// +//! Disable event operation for the specified channel +// +//***************************************************************************** +void +AONRTCChannelDisable(uint32_t ui32Channel) +{ + // + // Check the arguments. + // + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH0_EN); + } + else if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH1_EN); + } + else if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH2_EN); + } +} +//***************************************************************************** +// +//! Set the compare value for the given channel +// +//***************************************************************************** +void +AONRTCCompareValueSet(uint32_t ui32Channel, uint32_t ui32CompValue) +{ + // + // Check the arguments. + // + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP) = ui32CompValue; + } + else if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP) = ui32CompValue; + } + else if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP) = ui32CompValue; + } +} +//***************************************************************************** +// +//! Get the compare value for the given channel +// +//***************************************************************************** +uint32_t +AONRTCCompareValueGet(uint32_t ui32Channel) +{ + // + // Check the arguments + // + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP)); + } + else if(ui32Channel & AON_RTC_CH1) + { + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP)); + } + else if(ui32Channel & AON_RTC_CH2) + { + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP)); + } + // + // Should never return from here! + // + return(0); +} +//***************************************************************************** +// +//! Get the current value of the RTC counter in a format compatible to the +//! compare registers. +// +//***************************************************************************** +uint32_t +AONRTCCurrentCompareValueGet(void) +{ + uint32_t ui32CurrentSec0; + uint32_t ui32CurrentSec1; + uint32_t ui32CurrentSubSec; + + // + // Read the integer part of the RTC counter + // + ui32CurrentSec0 = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + + // + // Read the fractional part of the RTC counter. Make sure the fractional + // part has not rolled over and incremented the integer part. + // + do { + ui32CurrentSubSec = HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC); + ui32CurrentSec1 = ui32CurrentSec0; + ui32CurrentSec0 = HWREG(AON_RTC_BASE + AON_RTC_O_SEC); + } while(ui32CurrentSec0 != ui32CurrentSec1); + + // + // Return the RTC value in the correct format + // + return ((ui32CurrentSec0 << 16) | (ui32CurrentSubSec >> 16)); +} +//! @} +//! \\addtogroup aon_wuc_api +//! @{ +//***************************************************************************** +// +//! Set the clock source for the AUX domain +// +//***************************************************************************** +void +AONWUCAuxClockConfigSet(uint32_t ui32ClkSrc, uint32_t ui32ClkDiv) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT((ui32ClkSrc == AONWUC_CLOCK_SRC_HF) || + (ui32ClkSrc == AONWUC_CLOCK_SRC_MF) || + (ui32ClkSrc == AONWUC_CLOCK_SRC_LF)); + ASSERT((ui32ClkDiv == AUX_CLOCK_DIV_2) || + (ui32ClkDiv == AUX_CLOCK_DIV_4) || + (ui32ClkDiv == AUX_CLOCK_DIV_8) || + (ui32ClkDiv == AUX_CLOCK_DIV_16) || + (ui32ClkDiv == AUX_CLOCK_DIV_32) || + (ui32ClkDiv == AUX_CLOCK_DIV_64) || + (ui32ClkDiv == AUX_CLOCK_DIV_128) || + (ui32ClkDiv == AUX_CLOCK_DIV_256) || + (ui32ClkDiv == AUX_CLOCK_DIV_UNUSED)); + + // + // Configure the clock for the AUX domain. + // + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK); + + // + // Check if we need to update the clock division factor + // + if(ui32ClkDiv != AUX_CLOCK_DIV_UNUSED) + { + ui32Reg = (ui32Reg & ~AON_WUC_AUXCLK_SCLK_HF_DIV_M) | ui32ClkDiv; + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg; + + // If switching to a HF clocks source for AUX it is necessary to + // synchronize the write on the AON RTC to ensure the clock division is + // updated before requesting the clock source + // + if(ui32ClkSrc == AONWUC_CLOCK_SRC_HF) + { + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); + } + } + + // + // Configure the clock for the AUX domain. + // + ui32Reg &= ~AON_WUC_AUXCLK_SRC_M; + if(ui32ClkSrc == AONWUC_CLOCK_SRC_HF) + { + ui32Reg |= AON_WUC_AUXCLK_SRC_SCLK_HF; + } + else if(ui32ClkSrc == AONWUC_CLOCK_SRC_MF) + { + ui32Reg |= AON_WUC_AUXCLK_SRC_SCLK_MF; + } + else if(ui32ClkSrc == AONWUC_CLOCK_SRC_LF) + { + ui32Reg |= AON_WUC_AUXCLK_SRC_SCLK_LF; + } + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg; +} +//***************************************************************************** +// +//! Configure the rentention on the AUX SRAM +// +//***************************************************************************** +void +AONWUCAuxSRamConfig(uint32_t ui32Retention) +{ + + // + // Enable/disable the retention. + // + if(ui32Retention) + { + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCFG) |= AON_WUC_AUXCFG_SRAM_RET_EN; + } + else + { + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCFG) &= ~AON_WUC_AUXCFG_SRAM_RET_EN; + } +} +//***************************************************************************** +// +//! Control the wake up procedure of the AUX domain +// +//***************************************************************************** +void +AONWUCAuxWakeupEvent(uint32_t ui32Mode) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT((ui32Mode == AONWUC_AUX_WAKEUP_SWEVT) || + (ui32Mode == AONWUC_AUX_WAKEUP) || + (ui32Mode == AONWUC_AUX_ALLOW_SLEEP)); + + // + // Wake up the AUX domain. + // + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL); + + if(ui32Mode == AONWUC_AUX_ALLOW_SLEEP) + { + ui32Reg &= ~AON_WUC_AUXCTL_AUX_FORCE_ON; + } + else + { + ui32Reg |= ui32Mode; + } + + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) = ui32Reg; +} +//***************************************************************************** +// +//! Reset the AUX domain +// +//***************************************************************************** +void +AONWUCAuxReset(void) +{ + // + // Reset the AUX domain. + // + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) |= AON_WUC_AUXCTL_RESET_REQ; + + // + // Wait for AON interface to be in sync. + // + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); + + // + // De-assert reset on the AUX domain. + // + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) &= ~AON_WUC_AUXCTL_RESET_REQ; + + // + // Wait for AON interface to be in sync. + // + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} +//***************************************************************************** +// +//! Configure the recharge controller +// +//***************************************************************************** +void +AONWUCRechargeCtrlConfigSet(bool bAdaptEnable, uint32_t ui32AdaptRate, + uint32_t ui32Period, uint32_t ui32MaxPeriod) +{ + uint32_t ui32Shift; + uint32_t ui32C1; + uint32_t ui32C2; + uint32_t ui32Reg; + uint32_t ui32Exponent; + uint32_t ui32MaxExponent; + uint32_t ui32Mantissa; + uint32_t ui32MaxMantissa; + + // + // Check the arguments. + // + ASSERT((ui32AdaptRate >= RC_RATE_MIN) || + (ui32AdaptRate <= RC_RATE_MAX)); + + ui32C1 = 0; + ui32C2 = 0; + ui32Shift = 9; + + // + // Clear the previous values. + // + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG); + ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M | + AON_WUC_RECHARGECFG_ADAPTIVE_EN_M | AON_WUC_RECHARGECFG_PER_M_M | + AON_WUC_RECHARGECFG_PER_E_M | AON_WUC_RECHARGECFG_C1_M | + AON_WUC_RECHARGECFG_C2_M); + + // + // Check if the recharge controller adaption algorithm should be active. + // + if(bAdaptEnable) + { + // + // Calculate adaption parameters. + // + while(ui32AdaptRate) + { + if(ui32AdaptRate & (1 << ui32Shift)) + { + if(!ui32C1) + { + ui32C1 = ui32Shift; + } + else if(!ui32C2) + { + if((2 * ui32AdaptRate) > ((uint32_t)(3 << ui32Shift))) + { + ui32C2 = ui32Shift + 1; + } + else + { + ui32C2 = ui32Shift; + } + } + else + { + break; + } + ui32AdaptRate &= ~(1 << ui32Shift); + } + ui32Shift--; + } + if(!ui32C2) + { + ui32C2 = ui32C1 = ui32C1 - 1; + } + + ui32C1 = 10 - ui32C1; + ui32C2 = 10 - ui32C2; + + // + // Update the recharge rate parameters. + // + ui32Reg &= ~(AON_WUC_RECHARGECFG_C1_M | AON_WUC_RECHARGECFG_C2_M); + ui32Reg |= (ui32C1 << AON_WUC_RECHARGECFG_C1_S) | + (ui32C2 << AON_WUC_RECHARGECFG_C2_S) | + AON_WUC_RECHARGECFG_ADAPTIVE_EN_M; + } + + // + // Resolve the period into an exponent and mantissa. + // + ui32Period = (ui32Period >> 4); + ui32Exponent = 0; + while(ui32Period > (AON_WUC_RECHARGECFG_PER_M_M >> AON_WUC_RECHARGECFG_PER_M_S)) + { + ui32Period >>= 1; + ui32Exponent++; + } + ui32Mantissa = ui32Period; + + // + // Resolve the max period into an exponent and mantissa. + // + ui32MaxPeriod = (ui32MaxPeriod >> 4); + ui32MaxExponent = 0; + while(ui32MaxPeriod > (AON_WUC_RECHARGECFG_MAX_PER_M_M >> AON_WUC_RECHARGECFG_MAX_PER_M_S)) + { + ui32MaxPeriod >>= 1; + ui32MaxExponent++; + } + ui32MaxMantissa = ui32MaxPeriod; + + + // + // Configure the controller. + // + ui32Reg |= ((ui32MaxMantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) | + (ui32MaxExponent << AON_WUC_RECHARGECFG_MAX_PER_E_S) | + (ui32Mantissa << AON_WUC_RECHARGECFG_PER_M_S) | + (ui32Exponent << AON_WUC_RECHARGECFG_PER_E_S)); + HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg; + +} +//***************************************************************************** +// +//! Configure the interval for oscillator amplitude calibration +// +//***************************************************************************** +void +AONWUCOscConfig(uint32_t ui32Period) +{ + uint32_t ui32Mantissa; + uint32_t ui32Exponent; + uint32_t ui32Reg; + + // + // Resolve the period into a exponent and mantissa. + // + ui32Period = (ui32Period >> 4); + ui32Exponent = 0; + while(ui32Period > (AON_WUC_OSCCFG_PER_M_M >> AON_WUC_OSCCFG_PER_M_S)) + { + ui32Period >>= 1; + ui32Exponent++; + } + ui32Mantissa = ui32Period; + + // + // Update the period for the oscillator amplitude calibration. + // + HWREG(AON_WUC_BASE + AON_WUC_O_OSCCFG) = + (ui32Mantissa << AON_WUC_OSCCFG_PER_M_S) | + (ui32Exponent << AON_WUC_OSCCFG_PER_E_S); + + // + // Set the maximum reacharge period equal to the oscillator amplitude + // calibration period. + // + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG); + ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M); + ui32Reg |= ((ui32Mantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) | + (ui32Exponent << AON_WUC_RECHARGECFG_MAX_PER_E_S)); + + // + // Write the configuration. + // + HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg; +} +//! @} +//! \\addtogroup aux_ctrl_api +//! @{ +//***************************************************************************** +// +//! Load AUX controller Firmware into dedicated RAM +// +//***************************************************************************** +void +AUXCTRLImageLoad(uint16_t *pui16Image, uint32_t ui32StartAddr, + uint32_t ui32Size) +{ + uint16_t* pui16Src16; + uint16_t* pui16Dst16; + uint32_t ui32WordCnt; + + // + // Check the arguments. + // + ASSERT(ui32StartAddr < 512); + ASSERT(ui32Size <= 1024); + ASSERT((ui32Size / 2 + ui32StartAddr) <= 512); + + // + // Copy image to AUX RAM. + // + ui32WordCnt = (ui32Size >> 1); + pui16Src16 = pui16Image; + pui16Dst16 = (uint16_t*)(AUX_RAM_BASE + (ui32StartAddr << 1)); + + while(ui32WordCnt--) + { + *pui16Dst16++ = *pui16Src16++; + } +} +//! @} +//! \\addtogroup aux_tdc_api +//! @{ +//***************************************************************************** +// +//! Configure the operation of the AUX TDC +// +//***************************************************************************** +void +AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, + uint32_t ui32StopCondition) +{ + // + // Check the arguments. + // + ASSERT(AUXTDCBaseValid(ui32Base)); + + // + // Make sure the AUX TDC is in the idle state before changing the + // configuration. + // + while(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + } + + // + // Clear previous results. + // + HWREG(ui32Base + AUX_TDC_O_CTL) = 0x0; + + // + // Change the configuration. + // + HWREG(ui32Base + AUX_TDC_O_TRIGSRC) = ui32StartCondition | ui32StopCondition; +} +//***************************************************************************** +// +//! Check if the AUX TDC is done measuring +// +//***************************************************************************** +uint32_t +AUXTDCMeasurementDone(uint32_t ui32Base) +{ + uint32_t ui32Reg; + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(AUXTDCBaseValid(ui32Base)); + + // + // Check if the AUX TDC is done measuring. + // + ui32Reg = HWREG(ui32Base + AUX_TDC_O_STAT); + if(ui32Reg & AUX_TDC_STAT_DONE) + { + ui32Status = AUX_TDC_DONE; + } + else if(ui32Reg & AUX_TDC_STAT_SAT) + { + ui32Status = AUX_TDC_TIMEOUT; + } + else + { + ui32Status = AUX_TDC_BUSY; + } + + // + // Return the status. + // + return (ui32Status); +} +//! @} +//! \\addtogroup aux_timer_api +//! @{ +//***************************************************************************** +// +//! Configure AUX timer +// +//***************************************************************************** +void +AUXTimerConfigure(uint32_t ui32Timer, uint32_t ui32Config) +{ + uint32_t ui32Val; + + // + // Check the arguments. + // + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + ASSERT(((ui32Config & 0x0000000F) == AUX_TIMER_CFG_ONE_SHOT) || + ((ui32Config & 0x0000000F) == AUX_TIMER_CFG_PERIODIC) || + ((ui32Config & 0x0000000F) == AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT) || + ((ui32Config & 0x0000000F) == AUX_TIMER_CFG_PERIODIC_EDGE_COUNT) || + ((ui32Config & 0x000000F0) == AUX_TIMER_CFG_RISING_EDGE) || + ((ui32Config & 0x000000F0) == AUX_TIMER_CFG_FALLING_EDGE) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_RTC_EVENT) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_CMP_A) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_CMP_B) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_TDCDONE) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_SMPH_RELEASE) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_ADC_DONE) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO0) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO1) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO2) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO3) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO4) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO5) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO6) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO7) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO8) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO9) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO10) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO11) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO12) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO13) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO14) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO15) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_ACLK_REF) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_MCU_EVENT) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_ADC_IRQ)); + + // + // Configure Timer 0. + // + if(ui32Timer & AUX_TIMER_0) + { + // + // Stop timer 0. + // + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = 0; + + // + // Set mode. + // + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); + ui32Val &= ~(AUX_TIMER_T0CFG_MODE_M | AUX_TIMER_T0CFG_RELOAD_M); + ui32Val |= (ui32Config & (AUX_TIMER_T0CFG_MODE_M | + AUX_TIMER_T0CFG_RELOAD_M)); + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; + + // + // If edge counter, set rising/falling edge and tick source. + // + if(ui32Config & AUX_TIMER_T0CFG_MODE_M) + { + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); + ui32Val &= ~(AUX_TIMER_T0CFG_TICK_SRC_POL_M | + AUX_TIMER_T0CFG_TICK_SRC_M); + + // + // Set edge polarity. + // + if(ui32Config & AUX_TIMER_CFG_FALLING_EDGE) + { + ui32Val |= AUX_TIMER_T0CFG_TICK_SRC_POL; + } + + // + // Set tick source. + // + ui32Val |= ((ui32Config & 0x00000F00) >> 8) << + AUX_TIMER_T0CFG_TICK_SRC_S; + + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; + } + } + + // + // Configure Timer 1. + // + if(ui32Timer & AUX_TIMER_1) + { + // + // Stop timer 1. + // + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = 0; + + // + // Set mode. + // + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); + ui32Val &= ~(AUX_TIMER_T1CFG_MODE_M | AUX_TIMER_T1CFG_RELOAD_M); + ui32Val |= ((ui32Config) & (AUX_TIMER_T1CFG_MODE_M | + AUX_TIMER_T1CFG_RELOAD_M)); + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; + + // + // If edge counter, set rising/falling edge and tick source. + // + if(ui32Config & AUX_TIMER_T1CFG_MODE) + { + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); + ui32Val &= ~(AUX_TIMER_T1CFG_TICK_SRC_POL_M | + AUX_TIMER_T1CFG_TICK_SRC_M); + + // + // Set edge polarity. + // + if(ui32Config & AUX_TIMER_CFG_FALLING_EDGE) + { + ui32Val |= AUX_TIMER_T1CFG_TICK_SRC_POL; + } + + // + // Set tick source. + // + ui32Val |= ((ui32Config & 0x00000F00) >> 8) << + AUX_TIMER_T1CFG_TICK_SRC_S; + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; + } + } +} +//***************************************************************************** +// +//! Start AUX timer +// +//***************************************************************************** +void +AUXTimerStart(uint32_t ui32Timer) +{ + // + // Check the arguments. + // + ASSERT((ui32Timer == AUX_TIMER_0) || + (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + + if(ui32Timer & AUX_TIMER_0) + { + // + // Start timer 0. + // + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = AUX_TIMER_T0CTL_EN; + } + if(ui32Timer & AUX_TIMER_1) + { + // + // Start timer 1. + // + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = AUX_TIMER_T1CTL_EN; + } +} +//***************************************************************************** +// +//! Stop AUX timer +// +//***************************************************************************** +void +AUXTimerStop(uint32_t ui32Timer) +{ + // + // Check the arguments. + // + ASSERT((ui32Timer == AUX_TIMER_0) || + (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + + if(ui32Timer & AUX_TIMER_0) + { + // + // Stop timer 0. + // + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = 0; + } + if(ui32Timer & AUX_TIMER_1) + { + // + // Stop timer 1. + // + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = 0; + } +} +//***************************************************************************** +// +//! Set AUX timer prescale value +// +//***************************************************************************** +void +AUXTimerPrescaleSet(uint32_t ui32Timer, uint32_t ui32PrescaleDiv) +{ + uint32_t ui32Val; + + // + // Check the arguments. + // + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + ASSERT(ui32PrescaleDiv <= AUX_TIMER_PRESCALE_DIV_32768); + + if(ui32Timer & AUX_TIMER_0) + { + // + // Set timer 0 prescale value. + // + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); + ui32Val &= ~AUX_TIMER_T0CFG_PRE_M; + ui32Val |= ui32PrescaleDiv << AUX_TIMER_T0CFG_PRE_S; + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; + } + if(ui32Timer & AUX_TIMER_1) + { + // + // Set timer 1 prescale value. + // + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); + ui32Val &= ~AUX_TIMER_T1CFG_PRE_M; + ui32Val |= ui32PrescaleDiv << AUX_TIMER_T1CFG_PRE_S; + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; + } +} +//***************************************************************************** +// +//! Get AUX timer prescale value +// +//***************************************************************************** +uint32_t +AUXTimerPrescaleGet(uint32_t ui32Timer) +{ + uint32_t ui32Val; + uint32_t ui32PrescaleDiv; + + // + // Check the arguments. + // + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); + + ui32Val = (HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG)); + if(ui32Timer & AUX_TIMER_0) + { + // + // Get timer 0 prescale value. + // + ui32PrescaleDiv = + (ui32Val & AUX_TIMER_T0CFG_PRE_M) >> AUX_TIMER_T0CFG_PRE_S; + } + else + { + // + // Get timer 1 prescale value. + // + ui32PrescaleDiv = + (ui32Val & AUX_TIMER_T1CFG_PRE_M) >> AUX_TIMER_T1CFG_PRE_S; + } + + return(ui32PrescaleDiv); +} +//! @} +//! \\addtogroup aux_wuc_api +//! @{ +//**************************************************************************** +// +//! Enable clocks for peripherals in the AUX domain +// +//**************************************************************************** +void +AUXWUCClockEnable(uint32_t ui32Clocks) +{ + // + // Check the arguments. + // + ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || + (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || + (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || + (ui32Clocks & AUX_WUC_SOC_CLOCK) || + (ui32Clocks & AUX_WUC_TIMER_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || + (ui32Clocks & AUX_WUC_SMPH_CLOCK) || + (ui32Clocks & AUX_WUC_TDC_CLOCK) || + (ui32Clocks & AUX_WUC_ADC_CLOCK) || + (ui32Clocks & AUX_WUC_REF_CLOCK)); + + // + // Enable some of the clocks in the clock register. + // + HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) |= (ui32Clocks & + AUX_WUC_MODCLK_MASK); + + // + // Check the rest. + // + if(ui32Clocks & AUX_WUC_ADC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = + AUX_WUC_ADCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_TDC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) = + AUX_WUC_TDCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_REF_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = + AUX_WUC_REFCLKCTL_REQ; + } +} +//**************************************************************************** +// +//! Disable clocks for peripherals in the AUX domain +// +//**************************************************************************** +void +AUXWUCClockDisable(uint32_t ui32Clocks) +{ + // + // Check the arguments. + // + ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || + (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || + (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || + (ui32Clocks & AUX_WUC_SOC_CLOCK) || + (ui32Clocks & AUX_WUC_TIMER_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || + (ui32Clocks & AUX_WUC_SMPH_CLOCK) || + (ui32Clocks & AUX_WUC_TDC_CLOCK) || + (ui32Clocks & AUX_WUC_ADC_CLOCK) || + (ui32Clocks & AUX_WUC_REF_CLOCK)); + + // + // Disable some of the clocks in the clock register. + // + HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) &= ~(ui32Clocks & + AUX_WUC_MODCLK_MASK); + + // + // Check the rest. + // + if(ui32Clocks & AUX_WUC_ADC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) &= + ~AUX_WUC_ADCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_TDC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) &= + ~AUX_WUC_TDCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_REF_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) &= + ~AUX_WUC_REFCLKCTL_REQ; + } +} +//**************************************************************************** +// +//! Get the status of a clock +// +//**************************************************************************** +uint32_t +AUXWUCClockStatus(uint32_t ui32Clocks) +{ + bool bClockStatus; + uint32_t ui32ClockRegister; + + // + // Check the arguments. + // + ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || + (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || + (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || + (ui32Clocks & AUX_WUC_SOC_CLOCK) || + (ui32Clocks & AUX_WUC_TIMER_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || + (ui32Clocks & AUX_WUC_SMPH_CLOCK) || + (ui32Clocks & AUX_WUC_TDC_CLOCK) || + (ui32Clocks & AUX_WUC_ADC_CLOCK) || + (ui32Clocks & AUX_WUC_REF_CLOCK)); + + bClockStatus = true; + + // + // Read the status registers. + // + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0); + + // + // Check all requested clocks + // + if(ui32Clocks & AUX_WUC_ADI_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AUX_ADI ? + true : false); + } + if(ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_OSCCTL ? + true : false); + } + if(ui32Clocks & AUX_WUC_TDCIF_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_TDC ? + true : false); + } + if(ui32Clocks & AUX_WUC_SOC_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_SOC ? + true : false); + } + if(ui32Clocks & AUX_WUC_TIMER_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_TIMER ? + true : false); + } + if(ui32Clocks & AUX_WUC_AIODIO0_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AIODIO0 ? + true : false); + } + if(ui32Clocks & AUX_WUC_AIODIO1_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AIODIO1 ? + true : false); + } + if(ui32Clocks & AUX_WUC_SMPH_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_SMPH ? + true : false); + } + if(ui32Clocks & AUX_WUC_ADC_CLOCK) + { + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL); + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_ADCCLKCTL_ACK ? + true : false); + } + if(ui32Clocks & AUX_WUC_TDC_CLOCK) + { + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL); + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_TDCCLKCTL_ACK ? + true : false); + } + if(ui32Clocks & AUX_WUC_REF_CLOCK) + { + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL); + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_REFCLKCTL_ACK ? + true : false); + } + + // + // Return the clock status. + // + return bClockStatus ? AUX_WUC_CLOCK_READY : AUX_WUC_CLOCK_OFF; +} +//**************************************************************************** +// +//! Control the power to the AUX domain +// +//**************************************************************************** +void +AUXWUCPowerCtrl(uint32_t ui32PowerMode) +{ + // + // Check the arguments. + // + ASSERT((ui32PowerMode == AUX_WUC_POWER_OFF) || + (ui32PowerMode == AUX_WUC_POWER_DOWN) || + (ui32PowerMode == AUX_WUC_POWER_ACTIVE)); + + // + // Power on/off. + // + if(ui32PowerMode == AUX_WUC_POWER_OFF) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWROFFREQ) = AUX_WUC_PWROFFREQ_REQ; + HWREG(AUX_WUC_BASE + AUX_WUC_O_MCUBUSCTL) = AUX_WUC_MCUBUSCTL_DISCONNECT_REQ; + return; + } + else + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWROFFREQ) = 0x0; + } + + // + // Power down/active. + // + if(ui32PowerMode == AUX_WUC_POWER_DOWN) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWRDWNREQ) = + AUX_WUC_PWRDWNREQ_REQ; + HWREG(AUX_WUC_BASE + AUX_WUC_O_MCUBUSCTL) = AUX_WUC_MCUBUSCTL_DISCONNECT_REQ; + } + else + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWRDWNREQ) = 0x0; + } +} +//! @} +//! \\addtogroup ddi_api +//! @{ +//***************************************************************************** +// +//! Write a single bit using a 16-bit maskable write +// +//***************************************************************************** +void +DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32WrData) +{ + uint32_t ui32RegAddr; + uint32_t ui32Data; + + // + // Check the arguments. + // + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(!((ui32Mask & 0xFFFF0000) ^ (ui32Mask & 0x0000FFFF))); + ASSERT(!(ui32WrData & 0xFFFF0000)); + + // + // DDI 16-bit target is on 32-bit boundary so double offset + // + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // + // Adjust for target bit in high half of the word. + // + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 4; + ui32Mask >>= 16; + } + + // + // Write mask if data is not zero (to set mask bit), else write '0'. + // + ui32Data = ui32WrData ? ui32Mask : 0x0; + + // + // Update the register. + // + AuxAdiDdiSafeWrite(ui32RegAddr, (ui32Mask << 16) | ui32Data, 4); +} +//***************************************************************************** +// +//! Write a bitfield via the DDI using 16-bit maskable write +// +//***************************************************************************** +void +DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift, + uint16_t ui32Data) +{ + uint32_t ui32RegAddr; + uint32_t ui32WrData; + + // + // Check the arguments. + // + ASSERT(DDIBaseValid(ui32Base)); + + // + // 16-bit target is on 32-bit boundary so double offset. + // + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // + // Adjust for target bit in high half of the word. + // + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 4; + ui32Mask = ui32Mask >> 16; + } + + // + // Shift data in to position. + // + ui32WrData = ui32Data << ui32Shift; + + // + // Write data. + // + AuxAdiDdiSafeWrite(ui32RegAddr, (ui32Mask << 16) | ui32WrData, 4); +} +//***************************************************************************** +// +//! Read a bit via the DDI using 16-bit READ. +// +//***************************************************************************** +uint16_t +DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask) +{ + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // + // Check the arguments. + // + ASSERT(DDIBaseValid(ui32Base)); + + // + // Calculate the address of the register. + // + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // + // Adjust for target bit in high half of the word. + // + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // + // Read a halfword on the DDI interface. + // + ui16Data = AuxAdiDdiSafeRead(ui32RegAddr, 2); + + // + // Mask data. + // + ui16Data = ui16Data & ui32Mask; + + // + // Return masked data. + // + return(ui16Data); +} +//***************************************************************************** +// +//! Read a bitfield via the DDI using 16-bit read. +// +//***************************************************************************** +uint16_t +DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift) +{ + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // + // Check the arguments. + // + ASSERT(DDIBaseValid(ui32Base)); + + // + // Calculate the register address. + // + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // + // Adjust for target bit in high half of the word. + // + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // + // Read the register. + // + ui16Data = AuxAdiDdiSafeRead(ui32RegAddr, 2); + + // + // Mask data and shift into place. + // + ui16Data &= ui32Mask; + ui16Data >>= ui32Shift; + + // + // Return data. + // + return(ui16Data); +} +//! @} +//! \\addtogroup flash_api +//! @{ +//***************************************************************************** +// +// Default values for security control in customer configuration area in flash +// top sector. TBD! It must be asured that layout corresponds with CCFG. +// +//***************************************************************************** +const uint8_t g_pui8CcfgDefaultSec[] = {0xFF, 0xFF, 0xFF, 0xC5, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xC5, 0xFF, 0xFF, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF + }; + +//***************************************************************************** +// +// Function prototypes for static functions +// +//***************************************************************************** +static void IssueFsmCommand(tFlashStateCommandsType eCommand); +static void EnableSectorsForWrite(void); +static uint32_t ScaleCycleValues(uint32_t ui32SpecifiedTiming, + uint32_t ui32ScaleValue); +static void SetWriteMode(void); +static void SetReadMode(void); +static void TrimForWrite(void); +//***************************************************************************** +// +//! \internal +//! Issues a command to the Flash State Machine. +//! +//! \param eCommand specifies the FSM command. +//! +//! Issues a command to the Flash State Machine. +//! +//! \return None +// +//***************************************************************************** +static void +IssueFsmCommand(tFlashStateCommandsType eCommand) +{ + // + // Check the arguments. + // + ASSERT( + eCommand == FAPI_ERASE_SECTOR || eCommand == FAPI_ERASE_BANK || + eCommand == FAPI_VALIDATE_SECTOR || eCommand == FAPI_CLEAR_STATUS || + eCommand == FAPI_PROGRAM_RESUME || eCommand == FAPI_ERASE_RESUME || + eCommand == FAPI_CLEAR_MORE || eCommand == FAPI_PROGRAM_SECTOR || + eCommand == FAPI_PROGRAM_DATA || eCommand == FAPI_ERASE_OTP); + + // + // Enable write to FSM register. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + // + // Issue FSM command. + // + HWREG(FLASH_BASE + FLASH_O_FSM_CMD) = eCommand; + + // + // Start command execute. + // + HWREG(FLASH_BASE + FLASH_O_FSM_EXECUTE) = FLASH_CMD_EXEC; + + // + // Disable write to FSM register. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \internal +//! Enables all sectors for erase and programming on the active bank. +//! +//! This function disables the idle reading power reduction mode, selects the +//! flash bank and enables all sectors for erase and programming on the active +//! bank. +//! Sectores may be protected from programming depending on the value of the +//! FLASH_O_FSM_BSLPx registers. +//! Sectores may be protected from erase depending on the value of the +//! FLASH_O_FSM_BSLEx registers. Additional sector erase protection is set by +//! the FLASH_O_FSM_SECTOR1 register. +//! +//! \return None +// +//***************************************************************************** +static void +EnableSectorsForWrite(void) +{ + // + // Trim flash module for program/erase operation. + // + TrimForWrite(); + + // + // Configure flash to write mode + // + SetWriteMode(); + + // + // Select flash bank. + // + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + + // + // Disable Level 1 Protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + // + // Enable all sectors for erase and programming. + // + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0xFFFF; + + // + // Enable Level 1 Protection + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; +} + +//***************************************************************************** +// +//! \internal +//! Trims the Flash Bank and Flash Pump for program/erase functionality +//! +//! This trimming will make it possible to perform erase and program operations +//! of the flash. Trim values are loaded from factory configuration area +//! (referred to as FCGF1). The trimming done by this function is valid until +//! reset of the flash module. +//! +//! Some registers shall be written with a value that is a number of FCLK +//! cycles. The trim values controlling these registers have a value of +//! number of half us. FCLK = SysClk / ((RWAIT+1) x 2). +//! In order to calculate the register value for these registers the +//! following calculation must be done: +//! +//! OtpValue SysClkMHz +//! -------- us OtpValue x --------- +//! 2 (RWAIT+1) +//! RegValue_in_no_of_clk_cycles = ----------------- = --------------------- +//! 1 4 +//! -------------- +//! SysClkMHz +//! ------------ +//! (RWAIT+1)x 2 +//! +//! This is equevivalent to: +//! +//! 16 x SysClkMHz +//! OtpValue x --------------- +//! (RWAIT+1) +//! RegValue_in_no_of_clk_cycles = ---------------------------- +//! 64 +//! +//! 16 x SysClkMHz +//! A scaling factor is set equal to: ui32FclkScale = -------------- +//! (RWAIT+1) +//! +//! which gives: +//! OtpValue x ui32FclkScale +//! RegValue_in_no_of_clk_cycles = ------------------------ +//! 64 +//! +//! \return None. +// +//***************************************************************************** +static void +TrimForWrite(void) +{ + uint32_t ui32Value; + uint32_t ui32TempVal; + uint32_t ui32FclkScale; + uint32_t ui32RWait; + + // + // Return if flash is already trimmed for program/erase operations. + // + if(HWREG(FLASH_BASE + FLASH_O_FWFLAG) & FW_WRT_TRIMMED) + { + return; + } + + //***********************************************************************// + // // + // Configure the FSM registers // + // // + //***********************************************************************// + + // + // Enable access to the FSM registers. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + // + // Determine the scaling value to be used on timing related trim values. + // The scaling value is based on the flash module clock frequency and RWAIT + // + ui32RWait = (HWREG(FLASH_BASE + FLASH_O_FRDCTL) & + FLASH_FRDCTL_RWAIT_M) >> FLASH_FRDCTL_RWAIT_S; + ui32FclkScale = (16 * FLASH_MODULE_CLK_FREQ) / (ui32RWait + 1); + + // + // Configure Program puls width bits 15:0. + // (FCFG1 offset 0x188 bits 15:0). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_PROG_EP) & + FACTORY_CFG_FLASH_PROG_EP_PROGRAM_PW_M) >> + FACTORY_CFG_FLASH_PROG_EP_PROGRAM_PW_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) & + ~FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M) | + ((ui32Value << FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S) & + FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M); + + // + // Configure Erase puls width bits 31:0. + // (FCFG1 offset 0x18C bits 31:0). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_ERA_PW) & + FACTORY_CFG_FLASH_ERA_PW_ERASE_PW_M) >> + FACTORY_CFG_FLASH_ERA_PW_ERASE_PW_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) & + ~FLASH_FSM_ERA_PW_FSM_ERA_PW_M) | + ((ui32Value << FLASH_FSM_ERA_PW_FSM_ERA_PW_S) & + FLASH_FSM_ERA_PW_FSM_ERA_PW_M); + + + // + // Configure no of flash clock cycles from EXECUTEZ going low to the + // verify data can be read in the program verify mode bits 7:0. + // (FCFG1 offset 0x174 bits 23:16). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_C_E_P_R) & + FACTORY_CFG_FLASH_C_E_P_R_PV_ACCESS_M) >> + FACTORY_CFG_FLASH_C_E_P_R_PV_ACCESS_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & + ~FLASH_FSM_EX_VAL_EXE_VALD_M) | + ((ui32Value << FLASH_FSM_EX_VAL_EXE_VALD_S) & + FLASH_FSM_EX_VAL_EXE_VALD_M); + + // + // Configure the number of flash clocks from the start of the Read mode at + // the end of the operations until the FSM clears the BUSY bit in FMSTAT. + // (FCFG1 offset 0x178 bits 23:16). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_P_R_PV) & + FACTORY_CFG_FLASH_P_R_PV_RH_M) >> + FACTORY_CFG_FLASH_P_R_PV_RH_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) = + (HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) & + ~FLASH_FSM_RD_H_RD_H_M) | + ((ui32Value << FLASH_FSM_RD_H_RD_H_S) & + FLASH_FSM_RD_H_RD_H_M); + + // + // Configure Program hold time + // (FCFG1 offset 0x178 bits 31:24). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_P_R_PV) & + FACTORY_CFG_FLASH_P_R_PV_PH_M) >> + FACTORY_CFG_FLASH_P_R_PV_PH_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) & + ~FLASH_FSM_P_OH_PGM_OH_M) | + ((ui32Value << FLASH_FSM_P_OH_PGM_OH_S) & + FLASH_FSM_P_OH_PGM_OH_M); + + // + // Configure Erase hold time + // (FCFG1 offset 0x17C bits 31:24). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_EH_SEQ) & + FACTORY_CFG_FLASH_EH_SEQ_EH_M) >> + FACTORY_CFG_FLASH_EH_SEQ_EH_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) & + ~FLASH_FSM_ERA_OH_ERA_OH_M) | + ((ui32Value << FLASH_FSM_ERA_OH_ERA_OH_S) & + FLASH_FSM_ERA_OH_ERA_OH_M); + + // + // Configure Program verify row switch time + // (FCFG1 offset0x178 bits 15:8). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_P_R_PV) & + FACTORY_CFG_FLASH_P_R_PV_PVH_M) >> + FACTORY_CFG_FLASH_P_R_PV_PVH_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) & + ~FLASH_FSM_PE_VH_PGM_VH_M) | + ((ui32Value << FLASH_FSM_PE_VH_PGM_VH_S) & + FLASH_FSM_PE_VH_PGM_VH_M); + + // + // Configure Program Operation Setup time + // (FCFG1 offset 0x170 bits 31:24). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_E_P) & + FACTORY_CFG_FLASH_E_P_PSU_M) >> + FACTORY_CFG_FLASH_E_P_PSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & + ~FLASH_FSM_PE_OSU_PGM_OSU_M) | + ((ui32Value << FLASH_FSM_PE_OSU_PGM_OSU_S) & + FLASH_FSM_PE_OSU_PGM_OSU_M); + + // + // Configure Erase Operation Setup time + // (FCGF1 offset 0x170 bits 23:16). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_E_P) & + FACTORY_CFG_FLASH_E_P_ESU_M) >> + FACTORY_CFG_FLASH_E_P_ESU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & + ~FLASH_FSM_PE_OSU_ERA_OSU_M) | + ((ui32Value << FLASH_FSM_PE_OSU_ERA_OSU_S) & + FLASH_FSM_PE_OSU_ERA_OSU_M); + + // + // Confgure Program Verify Setup time + // (FCFG1 offset 0x170 bits 15:8). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_E_P) & + FACTORY_CFG_FLASH_E_P_PVSU_M) >> + FACTORY_CFG_FLASH_E_P_PVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & + ~FLASH_FSM_PE_VSU_PGM_VSU_M) | + ((ui32Value << FLASH_FSM_PE_VSU_PGM_VSU_S) & + FLASH_FSM_PE_VSU_PGM_VSU_M); + + // + // Configure Erase Verify Setup time + // (FCFG1 offset 0x170 bits 7:0). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_E_P) & + FACTORY_CFG_FLASH_E_P_EVSU_M) >> + FACTORY_CFG_FLASH_E_P_EVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & + ~FLASH_FSM_PE_VSU_ERA_VSU_M) | + ((ui32Value << FLASH_FSM_PE_VSU_ERA_VSU_S) & + FLASH_FSM_PE_VSU_ERA_VSU_M); + + // + // Configure Addr to EXECUTEZ low setup time + // (FCFG1 offset 0x174 bits 15:12). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_C_E_P_R) & + FACTORY_CFG_FLASH_C_E_P_R_A_EXEZ_SETUP_M) >> + FACTORY_CFG_FLASH_C_E_P_R_A_EXEZ_SETUP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) & + ~FLASH_FSM_CMP_VSU_ADD_EXZ_M) | + ((ui32Value << FLASH_FSM_CMP_VSU_ADD_EXZ_S) & + FLASH_FSM_CMP_VSU_ADD_EXZ_M); + + // + // Configure Voltage Status Count + // (FCFG1 offset 0x17C bits 15:12). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_EH_SEQ) & + FACTORY_CFG_FLASH_EH_SEQ_VSTAT_M) >> + FACTORY_CFG_FLASH_EH_SEQ_VSTAT_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) = + (HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) & + ~FLASH_FSM_VSTAT_VSTAT_CNT_M) | + ((ui32Value << FLASH_FSM_VSTAT_VSTAT_CNT_S) & + FLASH_FSM_VSTAT_VSTAT_CNT_M); + + // + // Configure Repeat Verify action setup + // (FCFG1 offset 0x174 bits 31:24). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_C_E_P_R) & + FACTORY_CFG_FLASH_C_E_P_R_RVSU_M) >> + FACTORY_CFG_FLASH_C_E_P_R_RVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & + ~FLASH_FSM_EX_VAL_REP_VSU_M) | + ((ui32Value << FLASH_FSM_EX_VAL_REP_VSU_S) & + FLASH_FSM_EX_VAL_REP_VSU_M); + + // + // Configure Maximum Programming Pulses + // (FCFG1 offset 0x184 bits 15:0). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_PP) & + FACTORY_CFG_FLASH_PP_MAX_PP_M) >> + FACTORY_CFG_FLASH_PP_MAX_PP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & + ~FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M) | + ((ui32Value << FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S) & + FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M); + + // + // Configure Beginning level for VHVCT used during erase modes + // (FCFG1 offset 0x180 bits 31:16). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV_E) & + FACTORY_CFG_FLASH_VHV_E_VHV_E_START_M) >> + FACTORY_CFG_FLASH_VHV_E_VHV_E_START_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & + ~FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M) | + ((ui32Value << FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S) & + FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M); + + // + // Configure Maximum EC Level + // (FCFG1 offset 0x2B0 bits 21:18). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA3) & + FACTORY_CFG_FLASH_OTP_DATA3_MAX_EC_LEVEL_M) >> + FACTORY_CFG_FLASH_OTP_DATA3_MAX_EC_LEVEL_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & + ~FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M) | + ((ui32Value << FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S) & + FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M); + + // + // Configure Maximum Erase Pulses + // (FCFG1 offset 0x188 bits 31:16). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_PROG_EP) & + FACTORY_CFG_FLASH_PROG_EP_MAX_EP_M) >> + FACTORY_CFG_FLASH_PROG_EP_MAX_EP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & + ~FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M) | + ((ui32Value << FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S) & + FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M); + + // + // Configure the VHVCT Step Size. This is the number of erase pulses that + // must be completed for each level before the FSM increments the + // CUR_EC_LEVEL to the next higher level. Actual erase pulses per level + // equals (EC_STEP_SIZE +1). The stepping is only needed for the VHVCT + // voltage. + // (FCFG1 offset 0x2B0 bits 31:23). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA3) & + FACTORY_CFG_FLASH_OTP_DATA3_EC_STEP_SIZE_M) >> + FACTORY_CFG_FLASH_OTP_DATA3_EC_STEP_SIZE_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) = + (HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) & + ~FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M) | + ((ui32Value << FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S) & + FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M); + + // + // Configure the hight of each EC step. This is the number of counts that + // the CUR_EC_LEVEL will increment when going to a new level. Actual count + // size equals (EC_STEP_HEIGHT + 1). The stepping applies only to the VHVCT + // voltage. + // The read trim value is decremented by 1 before written to the register + // since actual counts equals (register value + 1). + // (FCFG1 offset 0x180 bits 15:0). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV_E) & + FACTORY_CFG_FLASH_VHV_E_VHV_E_STEP_HIGHT_M) >> + FACTORY_CFG_FLASH_VHV_E_VHV_E_STEP_HIGHT_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_EC_STEP_HEIGHT) = ((ui32Value - 1) & + FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M); + + // + // Configure Precondition used in erase operations + // (FCFG1 offset 0x2B0 bit 22). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA3) & + FACTORY_CFG_FLASH_OTP_DATA3_DO_PRECOND_M) >> + FACTORY_CFG_FLASH_OTP_DATA3_DO_PRECOND_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) & + ~FLASH_FSM_ST_MACHINE_DO_PRECOND_M) | + ((ui32Value << FLASH_FSM_ST_MACHINE_DO_PRECOND_S) & + FLASH_FSM_ST_MACHINE_DO_PRECOND_M); + + // + // Enable the recommended Good Time function. + // + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD; + + // + // Disable write access to FSM registers. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + + //***********************************************************************// + // // + // Configure the voltage registers // + // // + //***********************************************************************// + + // + // Unlock voltage registers (0x2080 - 0x2098). + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + + // + // Configure voltage level for the specified pump voltage of high + // voltage supply input during erase operation VHVCT_E and the TRIM13_E + // (FCFG1 offset 0x190 bits[3:0] and bits[11:8]). + // + ui32TempVal = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV); + + ui32Value = ((ui32TempVal & FACTORY_CFG_FLASH_VHV_TRIM13_E_M)>> + FACTORY_CFG_FLASH_VHV_TRIM13_E_S) << FLASH_FVHVCT1_TRIM13_E_S; + ui32Value |= ((ui32TempVal & FACTORY_CFG_FLASH_VHV_VHV_E_M)>> + FACTORY_CFG_FLASH_VHV_VHV_E_S) << FLASH_FVHVCT1_VHVCT_E_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & + ~(FLASH_FVHVCT1_TRIM13_E_M | FLASH_FVHVCT1_VHVCT_E_M)) | ui32Value; + + // + // Configure voltage level for the specified pump voltage of high voltage + // supply input during program verify operation VHVCT_PV and the TRIM13_PV + // (OTP offset 0x194 bits[19:16] and bits[27:24]). + // + ui32TempVal = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV_PV); + + ui32Value = ((ui32TempVal & FACTORY_CFG_FLASH_VHV_PV_TRIM13_PV_M)>> + FACTORY_CFG_FLASH_VHV_PV_TRIM13_PV_S) << + FLASH_FVHVCT1_TRIM13_PV_S; + ui32Value |= ((ui32TempVal & FACTORY_CFG_FLASH_VHV_PV_VHV_PV_M)>> + FACTORY_CFG_FLASH_VHV_PV_VHV_PV_S) << + FLASH_FVHVCT1_VHVCT_PV_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & + ~(FLASH_FVHVCT1_TRIM13_PV_M | FLASH_FVHVCT1_VHVCT_PV_M)) | ui32Value; + + // + // Configure voltage level for the specified pump voltage of high voltage + // supply input during program operation VHVCT_P and TRIM13_P + // (FCFG1 offset 0x190 bits[19:16] and bits[27:24]). + // + ui32TempVal = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV); + + ui32Value = ((ui32TempVal & FACTORY_CFG_FLASH_VHV_TRIM13_P_M)>> + FACTORY_CFG_FLASH_VHV_TRIM13_P_S) << FLASH_FVHVCT2_TRIM13_P_S; + ui32Value |= ((ui32TempVal & FACTORY_CFG_FLASH_VHV_VHV_P_M)>> + FACTORY_CFG_FLASH_VHV_VHV_P_S) << FLASH_FVHVCT2_VHVCT_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT2) = + (HWREG(FLASH_BASE + FLASH_O_FVHVCT2) & + ~(FLASH_FVHVCT2_TRIM13_P_M | FLASH_FVHVCT2_VHVCT_P_M)) | ui32Value; + + // + // Configure voltage level for the specified pump voltage of wordline power + // supply for read mode + // (FCFG1 offset 0x198 Bits 15:8). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_V) & + FACTORY_CFG_FLASH_V_V_READ_M) >> + FACTORY_CFG_FLASH_V_V_READ_S; + + HWREG(FLASH_BASE + FLASH_O_FVREADCT) = + (HWREG(FLASH_BASE + FLASH_O_FVREADCT) & + ~FLASH_FVREADCT_VREADCT_M) | + ((ui32Value << FLASH_FVREADCT_VREADCT_S) & + FLASH_FVREADCT_VREADCT_M); + + // + // Configure the voltage level for the VCG 2.5 CT pump voltage + // (FCFG1 offset 0x194 bits 15:8). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV_PV) & + FACTORY_CFG_FLASH_VHV_PV_VCG2P5_M) >> + FACTORY_CFG_FLASH_VHV_PV_VCG2P5_S; + + HWREG(FLASH_BASE + FLASH_O_FVNVCT) = + (HWREG(FLASH_BASE + FLASH_O_FVNVCT) & + ~FLASH_FVNVCT_VCG2P5CT_M) | + ((ui32Value << FLASH_FVNVCT_VCG2P5CT_S) & + FLASH_FVNVCT_VCG2P5CT_M); + + // + // Configure the voltage level for the specified pump voltage of high + // current power input during program operation + // (FCFG1 offset 0x198 bits 31:24). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_V) & + FACTORY_CFG_FLASH_V_VSL_P_M) >> + FACTORY_CFG_FLASH_V_VSL_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVSLP) = + (HWREG(FLASH_BASE + FLASH_O_FVSLP) & + ~FLASH_FVSLP_VSL_P_M) | + ((ui32Value << FLASH_FVSLP_VSL_P_S) & + FLASH_FVSLP_VSL_P_M); + + // + // Configure the voltage level for the specified pump voltage of wordline + // power supply during programming operations + // (OTP offset 0x198 bits 23:16). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_V) & + FACTORY_CFG_FLASH_V_VWL_P_M) >> + FACTORY_CFG_FLASH_V_VWL_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVWLCT) = + (HWREG(FLASH_BASE + FLASH_O_FVWLCT) & + ~FLASH_FVWLCT_VWLCT_P_M) | + ((ui32Value << FLASH_FVWLCT_VWLCT_P_S) & + FLASH_FVWLCT_VWLCT_P_M); + + // + // Configure the pump's TRIM_1P7 port pins. + // (FCFG1 offset 0x2B0 bits 17:16). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA3) & + FACTORY_CFG_FLASH_OTP_DATA3_TRIM_1P7_M) >> + FACTORY_CFG_FLASH_OTP_DATA3_TRIM_1P7_S; + + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~FLASH_FSEQPMP_TRIM_1P7_M) | + ((ui32Value << FLASH_FSEQPMP_TRIM_1P7_S) & + FLASH_FSEQPMP_TRIM_1P7_M); + + // + // Lock the voltage registers. + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // + // Set trimmed flag. + // + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; + HWREG(FLASH_BASE + FLASH_O_FWFLAG) |= FW_WRT_TRIMMED; + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; +} + +//***************************************************************************** +// +//! \internal +//! Used to scale the TI OTP values based on the FClk scaling value. +//! +//! \param ui32SpecifiedTiming +//! \param ui32ScaleValue +//! +//! Used to scale the TI OTP values based on the FClk scaling value. +//! +//! \return Returns the scaled value +// +//***************************************************************************** +static uint32_t +ScaleCycleValues(uint32_t ui32SpecifiedTiming, uint32_t ui32ScaleValue) +{ + return((ui32SpecifiedTiming * ui32ScaleValue) >> 6); +} + +//***************************************************************************** +// +//! \internal +//! Used to set flash in read mode. +//! +//! Flash is configured with values loaded from OTP dependent on the current +//! regulator mode. +//! +//! \return None. +// +//***************************************************************************** +static void +SetReadMode(void) +{ + uint32_t ui32TrimValue; + uint32_t ui32Value; + + // + // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + // VIN_AT_X and VIN_BY_PASS for read mode + // + if(HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL) & + AON_SYSCTL_PWRCTL_EXT_REG_MODE) + { + // Select trim values for external regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 4). + // Configure DIS_IDLE (OTP offset 0x308 bit 3). + ui32Value |= ((ui32TrimValue & + (FACTORY_CFG_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M | + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >> + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // + // Wait for disabled sample and hold functionality to be stable. + // + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 2:0) + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } + else + { + // Select trim values for internal regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 12). + // Configure DIS_IDLE (OTP offset 0x308 bit 11). + ui32Value |= ((ui32TrimValue & + (FACTORY_CFG_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M | + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >> + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // + // Wait for disabled sample and hold functionality to be stable. + // + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 10:8) + ui32Value = (((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S); + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} + +//***************************************************************************** +// +//! \internal +//! Used to set flash in write mode. +//! +//! Flash is configured with values loaded from OTP dependent on the current +//! regulator mode. +//! +//! \return None. +// +//***************************************************************************** +static void +SetWriteMode(void) +{ + uint32_t ui32TrimValue; + uint32_t ui32Value; + + // + // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + // VIN_AT_X and VIN_BY_PASS for program/erase mode + // + if(HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL) & + AON_SYSCTL_PWRCTL_EXT_REG_MODE) + { + // Select trim values for external regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 23) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 22:21) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 20). + // Configure DIS_IDLE (OTP offset 0x308 bit 19). + ui32Value |= ((ui32TrimValue & + (FACTORY_CFG_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M | + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M)) >> + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // + // Wait for disabled sample and hold functionality to be stable. + // + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 18:16) + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } + else + { + // Select trim values for internal regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 31) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 30:29) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 28). + // Configure DIS_IDLE (OTP offset 0x308 bit 27). + ui32Value |= ((ui32TrimValue & + (FACTORY_CFG_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M | + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M)) >> + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S) << + FLASH_CFG_DIS_IDLE_S; + + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // + // Wait for disabled sample and hold functionality to be stable. + // + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 26:24) + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} +//***************************************************************************** +// +//! Set power mode +// +//***************************************************************************** +void +FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriode, + uint32_t ui32PumpGracePeriode) +{ + // + // Check the arguments. + // + ASSERT(ui32PowerMode == FLASH_PWR_ACTIVE_MODE || + ui32PowerMode == FLASH_PWR_OFF_MODE || + ui32PowerMode == FLASH_PWR_DEEP_STDBY_MODE); + ASSERT(ui32BankGracePeriode <= 0xFF); + ASSERT(ui32PumpGracePeriode <= 0xFFFF); + + switch(ui32PowerMode) + { + case FLASH_PWR_ACTIVE_MODE: + // + // Set bank power mode to ACTIVE. + // + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= + (~FLASH_FBFALLBACK_BANKPWR0_M | FBFALLBACK_ACTIVE); + + // + // Set charge pump power mode to ACTIVE mode. + // + HWREG(FLASH_BASE + FLASH_O_FPAC1) |= 1 << FLASH_FPAC1_PUMPPWR_S; + break; + + case FLASH_PWR_OFF_MODE: + // + // Set bank grace periode. + // + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriode << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // + // Set pump grace periode. + // + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriode << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // + // Set bank power mode to SLEEP. + // + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= + (~FLASH_FBFALLBACK_BANKPWR0_M | FBFALLBACK_SLEEP); + + // + // Set charge pump power mode to SLEEP mode. + // + HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M; + break; + + case FLASH_PWR_DEEP_STDBY_MODE: + // + // Set bank grace periode. + // + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriode << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // + // Set pump grace periode. + // + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriode << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // + // Set bank power mode to DEEP STANDBY mode. + // + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= + (~FLASH_FBFALLBACK_BANKPWR0_M | FBFALLBACK_DEEP_STDBY); + + // + // Set charge pump power mode to SLEEP mode. + // + HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M; + break; + } +} +//***************************************************************************** +// +//! Get current configured power mode +// +//***************************************************************************** +uint32_t +FlashPowerModeGet(void) +{ + uint32_t ui32PowerMode; + uint32_t ui32BankPwrMode; + + ui32BankPwrMode = HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + FLASH_FBFALLBACK_BANKPWR0_M; + + if(ui32BankPwrMode == FBFALLBACK_SLEEP) + { + ui32PowerMode = FLASH_PWR_OFF_MODE; + } + else if(ui32BankPwrMode == FBFALLBACK_DEEP_STDBY) + { + ui32PowerMode = FLASH_PWR_DEEP_STDBY_MODE; + } + else + { + ui32PowerMode = FLASH_PWR_ACTIVE_MODE; + } + + // + // Return power mode. + // + return(ui32PowerMode); +} +//***************************************************************************** +// +//! Set sector protection +// +//***************************************************************************** +void +FlashProtectionSet(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode) +{ + uint32_t ui32SectorNumber; + + // + // Check the arguments. + // + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(ui32ProtectMode == FLASH_WRITE_PROTECT) + { + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / + FlashSectorSizeGet(); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + if(ui32SectorNumber <= 31) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber); + } + else if(ui32SectorNumber <= 63) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |= + (1 << (ui32SectorNumber & 0x1F)); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |= + (1 << (ui32SectorNumber & 0x1F)); + } + + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } +} +//***************************************************************************** +// +//! Get sector protection +// +//***************************************************************************** +uint32_t +FlashProtectionGet(uint32_t ui32SectorAddress) +{ + uint32_t ui32SectorProtect; + uint32_t ui32SectorNumber; + + // + // Check the arguments. + // + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + ui32SectorProtect = FLASH_NO_PROTECT; + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + + if(ui32SectorNumber <= 31) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + else if(ui32SectorNumber <= 63) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) & + (1 << (ui32SectorNumber & 0x1F))) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) & + (1 << (ui32SectorNumber & 0x1F)))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + + return(ui32SectorProtect); +} +//***************************************************************************** +// +//! Save sector protection to make it permanent +// +//***************************************************************************** +uint32_t +FlashProtectionSave(uint32_t ui32SectorAddress) +{ + uint32_t ui32ErrorReturn; + uint32_t ui32SectorNumber; + uint32_t ui32CcfgSectorAddr; + uint8_t pui8ProgBuf[4]; + + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // + // Check the arguments. + // + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(FlashProtectionGet(ui32SectorAddress) == FLASH_WRITE_PROTECT) + { + // + // Find sector number for specified sector. + // + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + ui32CcfgSectorAddr = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); + + // + // Adjust CCFG address to the 32-bit CCFG word holding the + // protect-bit for the specified sector. + // + ui32CcfgSectorAddr += (((ui32SectorNumber >> 5) * 4) + CCFG_OFFSET_SECT_PROT); + + // + // Find value to program by setting the protect-bit which + // corresponds to specified sector number, to 0. + // Leave other protect-bits unchanged. + // + *(uint32_t *)pui8ProgBuf = (~(1 << (ui32SectorNumber & 0x1F))) & + *(uint32_t *)ui32CcfgSectorAddr; + + ui32ErrorReturn = FlashProgram(pui8ProgBuf, ui32CcfgSectorAddr, + CCFG_SIZE_SECT_PROT); + } + + // + // Return status. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Erase a flash sector +// +//***************************************************************************** +uint32_t +FlashSectorErase(uint32_t ui32SectorAddress) +{ + uint32_t ui32ErrorReturn; + uint32_t ui32Error; + uint32_t ui32SectorBit; + uint32_t ui32SectorNumber; + + // + // Check the arguments. + // + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + // + // Enable all sectors for erase. + // + EnableSectorsForWrite(); + + // + // Check the arguments. + // + if((ui32SectorAddress > + (FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet())) || + ((ui32SectorAddress & (FlashSectorSizeGet() - 1)) != 00)) + { + // + // Invalid arguments. Exit function! + // + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Unprotect sector to be erased. + // + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + ui32SectorBit = 1 << (ui32SectorNumber & 0x1F); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + if(ui32SectorNumber < 0x20) + { + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = ~ui32SectorBit; + } + else + { + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = ~ui32SectorBit; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Write the address to the FSM. + // + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32SectorAddress + ADDR_OFFSET; + + // + // Issue the sector erase command to the FSM. + // + IssueFsmCommand(FAPI_ERASE_SECTOR); + + // + // Wait for erase to finish. + // + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // + // Update status. + // + ui32ErrorReturn = FlashCheckFsmForError(); + + // + // Disable sectors for erase. + // + FlashDisableSectorsForWrite(); + + // + // Check if flash top sector was erased. + // + if(ui32SectorAddress == (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())) + { + // + // Program security data to default values in the customer configuration + // area within the flash top sector. + // + ui32Error = FlashProgram((uint8_t *)g_pui8CcfgDefaultSec, + (ui32SectorAddress + CCFG_OFFSET_SECURITY), + CCFG_SIZE_SECURITY); + + if((ui32Error != FAPI_STATUS_SUCCESS) && + (ui32ErrorReturn == FAPI_STATUS_SUCCESS)) + { + ui32ErrorReturn = ui32Error; + } + } + + // + // Return status of operation. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Programs unprotected main bank flash sectors +// +//***************************************************************************** +uint32_t +FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) +{ + uint32_t ui32StartIndex; + uint32_t ui32StopIndex; + uint32_t ui32Index; + uint8_t ui8BankWidth; + uint8_t ui8NoOfBytes; + tFwpWriteByte *oFwpWriteByte; + uint32_t ui32ErrorReturn; + + // + // Check the arguments. + // + ASSERT((ui32Address + ui32Count) <= (FLASHMEM_BASE + FlashSizeGet())); + + // + // Enable sectors for programming. + // + EnableSectorsForWrite(); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // + // Check the arguments. + // + if((ui32Address + ui32Count) > (FLASHMEM_BASE + FlashSizeGet())) + { + // + // Invalid arguments. Exit function! + // + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // + // Set the status to indicate success. + // + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // + // Find flash bank width in number of bytes. + // + ui8BankWidth = + (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // + // Loop over the bytes to be programmed. + // + while(ui32Count) + { + // + // Setup the start position within the write data registers. + // + ui32StartIndex = ui32Address & (uint32_t)(ui8BankWidth - 1); + + // + // Setup number of bytes to program. + // + ui8NoOfBytes = ui8BankWidth - ui32StartIndex; + if(ui8NoOfBytes > ui32Count) + { + ui8NoOfBytes = ui32Count; + } + + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Write address to FADDR register. + // + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32Address + ADDR_OFFSET; + + // + // Setup the stop position within the write data registers. + // + ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); + + // + // Write each byte to the FWPWrite registers. + // + for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) + { + oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); + } + + // + // Issue the Program command to the FSM. + // + IssueFsmCommand(FAPI_PROGRAM_DATA); + + // + // Wait until the word has been programmed. + // + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // + // Exit if an access violation occurred. + // + ui32ErrorReturn = FlashCheckFsmForError(); + if(ui32ErrorReturn != FAPI_STATUS_SUCCESS) + { + break; + } + + // + // Prepare for next data burst. + // + ui32Count -= ((ui32StopIndex - ui32StartIndex) + 1); + ui32Address += ((ui32StopIndex - ui32StartIndex) + 1); + } + + // + // Disable sectors for programming. + // + FlashDisableSectorsForWrite(); + + // + // Return status of operation. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Starts programming within unprotected main bank flash sector and returns +// +//***************************************************************************** +uint32_t +FlashProgramNowait(uint32_t ui32StartAddress, uint8_t *pui8DataBuffer, + uint8_t ui8NoOfBytes) +{ + uint32_t ui32StartIndex; + uint32_t ui32StopIndex; + uint32_t ui32Index; + uint32_t ui32BankWidth; + uint32_t ui32ErrorReturn; + tFwpWriteByte *oFwpWriteByte; + + // + // Check the arguments. + // + ASSERT((ui32StartAddress + ui8NoOfBytes) <= (FLASHMEM_BASE + FlashSizeGet())); + + // + // Enable sectors for programming. + // + EnableSectorsForWrite(); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // + // Check the arguments. + // + if((ui32StartAddress + ui8NoOfBytes) > (FLASHMEM_BASE + FlashSizeGet())) + { + // + // Invalid arguments. Exit function! + // + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // + // Set status to indicate success + // + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // + // Find flash bank width in number of bytes. + // + ui32BankWidth = (((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // + // Setup the start position within the write data registers. + // + ui32StartIndex = ui32StartAddress & (ui32BankWidth - 1); + + // + // Check to see if there is more data in the buffer than the register. + // width. + // + if((ui8NoOfBytes == 0) || ((ui32StartIndex + ui8NoOfBytes) > ui32BankWidth)) + { + ui32ErrorReturn = FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH; + } + + if(ui32ErrorReturn == FAPI_STATUS_SUCCESS) + { + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Write address to FADDR register. + // + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32StartAddress + ADDR_OFFSET; + + // + // Setup the stop position within the write data registers. + // + ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); + + // + // Write each byte to the FWPWrite registers. + // + for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) + { + oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); + } + + // + // Issue the Program command to the FSM. + // + IssueFsmCommand(FAPI_PROGRAM_DATA); + } + + // + // Return the function status. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Reads efuse data from specified row +// +//***************************************************************************** +bool +FlashEfuseReadRow(uint32_t *pui32EfuseData, uint32_t ui32RowAddress) +{ + bool bStatus; + + // + // Make sure the clock for the efuse is enabled + // + HWREG(FLASH_BASE + FLASH_O_CFG) &= ~FLASH_CFG_DIS_EFUSECLK; + + // + // Set timing for EFUSE read operations. + // + HWREG(FLASH_BASE + FLASH_O_EFUSEREAD) |= ((5 << FLASH_EFUSEREAD_READCLOCK_S) & + FLASH_EFUSEREAD_READCLOCK_M); + + // + // Clear status register. + // + HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) = 0; + + // + // Select the FuseROM block 0. + // + HWREG(FLASH_BASE + FLASH_O_EFUSEADDR) = 0x00000000; + + // + // Start the read operation. + // + HWREG(FLASH_BASE + FLASH_O_EFUSE) = + (DUMPWORD_INSTR << FLASH_EFUSE_INSTRUCTION_S) | + (ui32RowAddress & FLASH_EFUSE_DUMPWORD_M); + + // + // Wait for operation to finish. + // + while(!(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_DONE)) + { + } + + // + // Check if error reported. + // + if(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_CODE_M) + { + // + // Set error status. + // + bStatus = 1; + + // + // Clear data. + // + *pui32EfuseData = 0; + } + else + { + // + // Set ok status. + // + bStatus = 0; + + // + // No error. Get data from data register. + // + *pui32EfuseData = HWREG(FLASH_BASE + FLASH_O_DATALOWER); + } + + // + // Disable the efuse clock to conserve power + // + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_EFUSECLK; + + // + // Return the data. + // + return(bStatus); +} +//***************************************************************************** +// +//! Disables all sectors for erase and programming on the active bank +// +//***************************************************************************** +void +FlashDisableSectorsForWrite(void) +{ + // + // Configure flash back to read mode + // + SetReadMode(); + + // + // Disable Level 1 Protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + // + // Disable all sectors for erase and programming. + // + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; + + // + // Enable Level 1 Protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Protect sectors from sector erase. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} +//***************************************************************************** +// +//! Erase all unprotected sectors in the flash main bank +// +//***************************************************************************** +uint32_t +FlashBankErase(bool bForcePrecondition) +{ + uint32_t ui32ErrorReturn; + uint32_t ui32Error; + uint32_t ui32SectorAddress; + uint32_t ui32RegVal; + + // + // Enable all sectors for erase. + // + EnableSectorsForWrite(); + + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Enable erase of all sectors and enable precondition if required. + // + ui32RegVal = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000; + if(bForcePrecondition) + { + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + FLASH_FSM_ST_MACHINE_DO_PRECOND; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Issue the bank erase command to the FSM. + // + IssueFsmCommand(FAPI_ERASE_BANK); + + // + // Wait for erase to finish. + // + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // + // Update status. + // + ui32ErrorReturn = FlashCheckFsmForError(); + + // + // Disable sectors for erase. + // + FlashDisableSectorsForWrite(); + + // + // Set configured precondition mode since it may have been forced on. + // + if(!(ui32RegVal & FLASH_FSM_ST_MACHINE_DO_PRECOND)) + { + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= + ~FLASH_FSM_ST_MACHINE_DO_PRECOND; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } + + // + // Program security data to default values in the customer configuration + // area within the flash top sector. + // + ui32SectorAddress = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); + ui32Error = FlashProgram((uint8_t *)g_pui8CcfgDefaultSec, + (ui32SectorAddress + CCFG_OFFSET_SECURITY), + CCFG_SIZE_SECURITY); + + if((ui32Error != FAPI_STATUS_SUCCESS) && + (ui32ErrorReturn == FAPI_STATUS_SUCCESS)) + { + ui32ErrorReturn = ui32Error; + } + + // + // Return status of operation. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Erase flash OTP/ENGR areas. +// +//***************************************************************************** +uint32_t +FlashhOtpEngrErase(void) +{ + uint32_t ui32ErrorReturn; + uint32_t ui32RegVal; + + // + // Enable all sectors for erase. + // + EnableSectorsForWrite(); + + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Disable OTP protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) |= FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Enable test commands. + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // + // Set address to OTP. + // + HWREG(FLASH_BASE + FLASH_O_FADDR) = 0xF0000000; + + // + // Enable for FSM test commands and erase precondition. + // + ui32RegVal = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + (FLASH_FSM_ST_MACHINE_CMD_EN | FLASH_FSM_ST_MACHINE_DO_PRECOND); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Issue the erase command to the FSM. + // + IssueFsmCommand(FAPI_ERASE_OTP); + + // + // Wait for erase to finish. + // + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // + // Update status. + // + ui32ErrorReturn = FlashCheckFsmForError(); + + // + // Disable sectors for erase. + // + FlashDisableSectorsForWrite(); + + // + // Disable test commands. + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // + // Renable OTP protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Disable FSM test command mode. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + + // + // Set configured precondition mode since it may have been changed. + // + if(!(ui32RegVal & FLASH_FSM_ST_MACHINE_DO_PRECOND)) + { + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= + ~FLASH_FSM_ST_MACHINE_DO_PRECOND; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Return status of operation. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Programs a data pattern in a main bank flash sector. +// +//***************************************************************************** +uint32_t +FlashProgramPattern(uint32_t ui32SectorAddress, uint32_t ui32DataPattern, + bool bInvertData) +{ + uint8_t ui8Index; + uint8_t ui8BankWidth; + tFwpWriteByte *oFwpWriteByte; + uint32_t ui32ErrorReturn; + + // + // Check the arguments. + // + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + // + // Enable sectors for programming. + // + EnableSectorsForWrite(); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // + // Check the arguments. + // + if((ui32SectorAddress > + (FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet())) || + ((ui32SectorAddress & (FlashSectorSizeGet() - 1)) != 00)) + { + // + // Invalid arguments. Exit function! + // + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // + // Find flash bank width in number of bytes. + // + ui8BankWidth = + (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Write address to FADDR register. + // + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32SectorAddress + ADDR_OFFSET; + + // + // Write each byte of the pattern to the FWPWrite registers. + // + for(ui8Index = 0; ui8Index < ui8BankWidth; ui8Index++) + { + oFwpWriteByte[ui8Index] = ui32DataPattern >> ((ui8Index * 8) & + (PATTERN_BITS - 1)); + } + + // + // Enable for FSM test command and enable the Invert Data option if + // required. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; + if(bInvertData) + { + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_INV_DATA; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Issue the Program command to the FSM. + // + IssueFsmCommand(FAPI_PROGRAM_SECTOR); + + // + // Wait until the sector has been programmed. + // + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // + // Update status of the program operation. + // + ui32ErrorReturn = FlashCheckFsmForError(); + + // + // Disable sectors for programming. + // + FlashDisableSectorsForWrite(); + + // + // Disable FSM test command mode and the Invert Data option. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_INV_DATA; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Return status of operation. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Programs flash ENGR area +// +//***************************************************************************** +uint32_t +FlashProgramEngr(uint8_t *pui8DataBuffer, uint32_t ui32AddressOffset, + uint32_t ui32Count) +{ + uint32_t ui32StartIndex; + uint32_t ui32StopIndex; + uint32_t ui32Index; + uint8_t ui8BankWidth; + uint8_t ui8NoOfBytes; + tFwpWriteByte *oFwpWriteByte; + uint32_t ui32ErrorReturn; + + // + // Check the arguments. + // + ASSERT((ui32AddressOffset + ui32Count) <= 1024); + + // + // Enable sectors for programming. + // + EnableSectorsForWrite(); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // + // Check the arguments. + // + if((ui32AddressOffset + ui32Count) > 1024) + { + // + // Invalid arguments. Exit function! + // + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // + // Set the status to indicate success. + // + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // + // Find flash bank width in number of bytes. + // + ui8BankWidth = + (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // + // Disable OTP protection. + // + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) |= FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Enable test commands. + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // + // Enable for FSM test command. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Loop over the bytes to be programmed. + // + while(ui32Count) + { + // + // Setup the start position within the write data registers. + // + ui32StartIndex = ui32AddressOffset & (uint32_t)(ui8BankWidth - 1); + + // + // Setup number of bytes to program. + // + ui8NoOfBytes = ui8BankWidth - ui32StartIndex; + if(ui8NoOfBytes > ui32Count) + { + ui8NoOfBytes = ui32Count; + } + + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Write address to FADDR register. + // + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32AddressOffset + 0xF0080000; + + // + // Setup the stop position within the write data registers. + // + ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); + + // + // Write each byte to the FWPWrite registers. + // + for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) + { + oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); + } + + // + // Issue programming command. + // + IssueFsmCommand(FAPI_PROGRAM_DATA); + + // + // Wait until the word has been programmed. + // + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // + // Update error status and exit if an error occurred. + // + ui32ErrorReturn = FlashCheckFsmForError(); + if(ui32ErrorReturn != FAPI_STATUS_SUCCESS) + { + break; + } + + // + // Prepare for next data burst. + // + ui32Count -= ((ui32StopIndex - ui32StartIndex) + 1); + ui32AddressOffset += ((ui32StopIndex - ui32StartIndex) + 1); + } + + // + // Disable sectors for programming. + // + FlashDisableSectorsForWrite(); + + // + // Reenable OTP protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Disable test commands. + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // + // Disable FSM test command mode. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Return status of operation. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! FlashOtpProgramEraseSetup prepares program and erase of the OTP/ENGR +//! sector. +// +//***************************************************************************** +void +FlashOtpProgramEraseSetup(void) +{ + // + // Disable OTP protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) |= FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Enable test commands by performing the following steps: + // - Enable SW Interface mode + // - Enable for test commands + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x0000AAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x000055AA; + + // + // Enable for FSM test commands. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} +//***************************************************************************** +// +//! FlashOtpProgramEraseCleanup restores to default program and erase +//! protection. +// +//***************************************************************************** +void +FlashOtpProgramEraseCleanup(void) +{ + // + // Reenable OTP protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Disable test commands and turn off SW interface mode. + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x0000AAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // + // Disable FSM test command mode. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} +//! @} +//! \\addtogroup i2c_api +//! @{ +//***************************************************************************** +// +//! Initializes the I2C Master block +// +//***************************************************************************** +void +I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast) +{ + uint32_t ui32SCLFreq; + uint32_t ui32TPR; + + // + // Check the arguments. + // + ASSERT(I2CBaseValid(ui32Base)); + + // + // Must enable the device before doing anything else. + // + I2CMasterEnable(ui32Base); + + // + // Get the desired SCL speed. + // + if(bFast == true) + { + ui32SCLFreq = 400000; + } + else + { + ui32SCLFreq = 100000; + } + + // + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biased to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + // + ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / (2 * 10 * ui32SCLFreq)) - 1; + HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; +} +//***************************************************************************** +// +//! Gets the error status of the I2C Master module +// +//***************************************************************************** +uint32_t +I2CMasterErr(uint32_t ui32Base) +{ + uint32_t ui32Err; + + // + // Check the arguments. + // + ASSERT(I2CBaseValid(ui32Base)); + + // + // Get the raw error state. + // + ui32Err = HWREG(ui32Base + I2C_O_MSTAT); + + // + // If the I2C master is busy, then all the other status bits are invalid, + // and there is no error to report. + // + if(ui32Err & I2C_MSTAT_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // + // Check for errors. + // + if(ui32Err & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST)) + { + return(ui32Err & (I2C_MSTAT_ARBLST | I2C_MSTAT_DATACK | I2C_MSTAT_ADRACK)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} +//! @} +//! \\addtogroup interrupt_api +//! @{ +//***************************************************************************** +// +//! This is a mapping between priority grouping encodings and the number of +//! preemption priority bits. +// +//***************************************************************************** +static const uint32_t g_pui32Priority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; + +//***************************************************************************** +// +//! This is a mapping between interrupt number and the register that contains +//! the priority encoding for that interrupt. +// +//***************************************************************************** +static const uint32_t g_pui32Regs[] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13 +}; +//***************************************************************************** +// +//! Sets the priority grouping of the interrupt controller. +// +//***************************************************************************** +void +IntPriorityGroupingSet(uint32_t ui32Bits) +{ + // + // Check the arguments. + // + ASSERT(ui32Bits < NUM_PRIORITY); + + // + // Set the priority grouping. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; +} +//***************************************************************************** +// +//! Gets the priority grouping of the interrupt controller +// +//***************************************************************************** +uint32_t +IntPriorityGroupingGet(void) +{ + uint32_t ui32Loop, ui32Value; + + // + // Read the priority grouping. + // + ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // + // Loop through the priority grouping values. + // + for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++) + { + // + // Stop looping if this value matches. + // + if(ui32Value == g_pui32Priority[ui32Loop]) + { + break; + } + } + + // + // Return the number of priority bits. + // + return(ui32Loop); +} +//***************************************************************************** +// +//! Sets the priority of an interrupt +// +//***************************************************************************** +void +IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority) +{ + uint32_t ui32Temp; + + // + // Check the arguments. + // + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + ASSERT(ui8Priority <= INT_PRI_LEVEL7); + + // + // Set the interrupt priority. + // + ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); + ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3))); + ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3)); + HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; +} +//***************************************************************************** +// +//! Gets the priority of an interrupt +// +//***************************************************************************** +int32_t +IntPriorityGet(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + + // + // Return the interrupt priority. + // + return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) & + 0xFF); +} +//***************************************************************************** +// +//! Enables an interrupt +// +//***************************************************************************** +void +IntEnable(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to enable. + // + if(ui32Interrupt == FAULT_MPU) + { + // + // Enable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ui32Interrupt == FAULT_BUS) + { + // + // Enable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ui32Interrupt == FAULT_USAGE) + { + // + // Enable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ui32Interrupt == FAULT_SYSTICK) + { + // + // Enable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // + // Enable the general interrupt. + // + HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // + // Enable the general interrupt. + // + HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48); + } +} +//***************************************************************************** +// +//! Disables an interrupt +// +//***************************************************************************** +void +IntDisable(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to disable. + // + if(ui32Interrupt == FAULT_MPU) + { + // + // Disable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ui32Interrupt == FAULT_BUS) + { + // + // Disable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ui32Interrupt == FAULT_USAGE) + { + // + // Disable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ui32Interrupt == FAULT_SYSTICK) + { + // + // Disable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // + // Disable the general interrupt. + // + HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // + // Disable the general interrupt. + // + HWREG(NVIC_DIS1) = 1 << (ui32Interrupt - 48); + } +} +//***************************************************************************** +// +//! Pends an interrupt +// +//***************************************************************************** +void +IntPendSet(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to pend. + // + if(ui32Interrupt == FAULT_NMI) + { + // + // Pend the NMI interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; + } + else if(ui32Interrupt == FAULT_PENDSV) + { + // + // Pend the PendSV interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; + } + else if(ui32Interrupt == FAULT_SYSTICK) + { + // + // Pend the SysTick interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // + // Pend the general interrupt. + // + HWREG(NVIC_PEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // + // Pend the general interrupt. + // + HWREG(NVIC_PEND1) = 1 << (ui32Interrupt - 48); + } +} +//***************************************************************************** +// +//! Query whether an interrupt is pending +// +//***************************************************************************** +bool +IntPendGet(uint32_t ui32Interrupt) +{ + uint32_t ui32IntPending; + + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Assume no interrupts are pending. + // + ui32IntPending = 0; + + // + // The lower 16 IRQ vectors are unsupported by this function + // + if (ui32Interrupt < 16) + { + + return 0; + } + + // + // Subtract lower 16 irq vectors + // + ui32Interrupt -= 16; + + // + // Check if the interrupt is pending + // + ui32IntPending = HWREG(NVIC_PEND0 + (ui32Interrupt / 32)); + ui32IntPending &= (1 << (ui32Interrupt & 31)); + + return ui32IntPending ? true : false; +} +//***************************************************************************** +// +//! Unpends an interrupt +// +//***************************************************************************** +void +IntPendClear(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to unpend. + // + if(ui32Interrupt == FAULT_PENDSV) + { + // + // Unpend the PendSV interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; + } + else if(ui32Interrupt == FAULT_SYSTICK) + { + // + // Unpend the SysTick interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // + // Unpend the general interrupt. + // + HWREG(NVIC_UNPEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // + // Unpend the general interrupt. + // + HWREG(NVIC_UNPEND1) = 1 << (ui32Interrupt - 48); + } +} +//! @} +//! \\addtogroup ioc_api +//! @{ +//***************************************************************************** +// +// This is the mapping between an IO and the corresponding configuration +// register. +// +//***************************************************************************** +static const uint32_t g_pui32IOCfgReg[] = +{ + IOC_O_IOCFG0, IOC_O_IOCFG1, IOC_O_IOCFG2, IOC_O_IOCFG3, IOC_O_IOCFG4, + IOC_O_IOCFG5, IOC_O_IOCFG6, IOC_O_IOCFG7, IOC_O_IOCFG8, IOC_O_IOCFG9, + IOC_O_IOCFG10, IOC_O_IOCFG11, IOC_O_IOCFG12, IOC_O_IOCFG13, IOC_O_IOCFG14, + IOC_O_IOCFG15, IOC_O_IOCFG16, IOC_O_IOCFG17, IOC_O_IOCFG18, IOC_O_IOCFG19, + IOC_O_IOCFG20, IOC_O_IOCFG21, IOC_O_IOCFG22, IOC_O_IOCFG23, IOC_O_IOCFG24, + IOC_O_IOCFG25, IOC_O_IOCFG26, IOC_O_IOCFG27, IOC_O_IOCFG28, IOC_O_IOCFG29, + IOC_O_IOCFG30, IOC_O_IOCFG31 +}; +//***************************************************************************** +// +//! Set the configuration of an IO port +// +//***************************************************************************** +void +IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, + uint32_t ui32IOConfig) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_SMI_CL_IN); + + // + // Get the register address. + // + ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the port. + // + HWREG(ui32Reg) = ui32IOConfig | ui32PortId; +} +//***************************************************************************** +// +//! Get the configuration of an IO port +// +//***************************************************************************** +uint32_t +IOCPortConfigureGet(uint32_t ui32IOId) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + + // + // Get the register address. + // + ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Return the IO configuration. + // + return HWREG(ui32Reg); +} +//***************************************************************************** +// +//! Set wake-up on an IO port +// +//***************************************************************************** +void +IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) || + (ui32IOShutdown == IOC_WAKE_ON_LOW) || + (ui32IOShutdown == IOC_WAKE_ON_HIGH)); + + // + // Get the register address. + // + ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_WU_CFG_M; + HWREG(ui32Reg) = ui32Config | ui32IOShutdown; +} +//***************************************************************************** +// +//! Set wake-up on an IO port +// +//***************************************************************************** +void +IOCIOJTagSet(uint32_t ui32IOId, uint32_t ui32IOJTag) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOJTag == IOC_JTAG_TDO_ENABLE) || + (ui32IOJTag == IOC_JTAG_TDI_ENABLE) || + (ui32IOJTag == IOC_JTAG_DISABLE)); + + // + // Get the register address. + // + ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32Reg); + ui32Config &= ~(IOC_IOCFG0_TDI | IOC_IOCFG0_TDO); + HWREG(ui32Reg) = ui32Config | ui32IOJTag; +} +//***************************************************************************** +// +//! Set the IO Mode of an IO Port +// +//***************************************************************************** +void +IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) || + (ui32IOMode == IOC_IOMODE_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_INV)); + + // + // Get the register address. + // + ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_IOMODE_M; + HWREG(ui32Reg) = ui32Config | ui32IOMode; +} +//***************************************************************************** +// +//! Setup interrupt detection on an IO Port +// +//***************************************************************************** +void +IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Int == IOC_INT_ENABLE) || + (ui32Int == IOC_INT_DISABLE)); + ASSERT((ui32EdgeDet == IOC_NO_EDGE) || + (ui32EdgeDet == IOC_FALLING_EDGE) || + (ui32EdgeDet == IOC_RISING_EDGE) || + (ui32EdgeDet == IOC_BOTH_EDGES)); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_EDGE_IRQ_EN | IOC_IOCFG0_EDGE_DET_M); + HWREG(ui32IOReg) = ui32Config | ((ui32Int ? IOC_IOCFG0_EDGE_IRQ_EN : 0) | ui32EdgeDet); +} +//***************************************************************************** +// +//! Set the pull on an IO port +// +//***************************************************************************** +void +IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the argument. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Pull == IOC_NO_IOPULL) || + (ui32Pull == IOC_IOPULL_UP) || + (ui32Pull == IOC_IOPULL_DOWN)); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PULL_CTL_M; + HWREG(ui32IOReg) = ui32Config | ui32Pull; +} +//***************************************************************************** +// +//! Configure hysteresis on and IO port +// +//***************************************************************************** +void +IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Hysteresis == IOC_HYST_ENABLE) || + (ui32Hysteresis == IOC_HYST_DISABLE)); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_HYST_EN; + HWREG(ui32IOReg) = ui32Config | ui32Hysteresis; +} +//***************************************************************************** +// +//! Enable/disable IO port as input +// +//***************************************************************************** +void +IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Input == IOC_INPUT_ENABLE) || + (ui32Input == IOC_INPUT_DISABLE)); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_IE; + HWREG(ui32IOReg) = ui32Config | ui32Input; +} +//***************************************************************************** +// +//! Enable/disable the slew control on an IO port +// +//***************************************************************************** +void +IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32SlewEnable == IOC_SLEW_ENABLE) || + (ui32SlewEnable == IOC_SLEW_DISABLE)); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_SLEW_RED; + HWREG(ui32IOReg) = ui32Config | ui32SlewEnable; +} +//***************************************************************************** +// +//! Configure the drive strength and maxium current of an IO port +// +//***************************************************************************** +void +IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, + uint32_t ui32DrvStrength) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOCurrent == IOC_CURRENT_2MA) || + (ui32IOCurrent == IOC_CURRENT_4MA) || + (ui32IOCurrent == IOC_CURRENT_8MA) || + (ui32IOCurrent == IOC_CURRENT_16MA)); + ASSERT((ui32DrvStrength == IOC_STRENGTH_MIN) || + (ui32DrvStrength == IOC_STRENGTH_MAX) || + (ui32DrvStrength == IOC_STRENGTH_MED) || + (ui32DrvStrength == IOC_STRENGTH_AUTO)); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_IOCURR_M | IOC_IOCFG0_IOSTR_M); + HWREG(ui32IOReg) = ui32Config | (ui32IOCurrent | ui32DrvStrength); +} +//***************************************************************************** +// +//! Setup the Port ID for this IO +// +//***************************************************************************** +void +IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_SMI_CL_IN); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PORT_ID_M; + HWREG(ui32IOReg) = ui32Config | ui32PortId; +} +//***************************************************************************** +// +//! Enables individual IO edge detect interrupt +//! +//! \param ui32IOId is the IO to enable edge detect interrupt for. +//! +//! This function enables the indicated IO edge interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None +// +//***************************************************************************** +void +IOCIntEnable(uint32_t ui32IOId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Enable the specified interrupt. + // + ui32Config = HWREG(ui32IOReg); + ui32Config |= IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} +//***************************************************************************** +// +//! Disables individual IO edge interrupt sources +// +//***************************************************************************** +void +IOCIntDisable(uint32_t ui32IOId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Disable the specified interrupt. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} +//***************************************************************************** +// +//! Setup an IO for standard GPIO input +// +//***************************************************************************** +void +IOCPinTypeGpioInput(uint32_t ui32IOId) +{ + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + + // + // Setup the IO for standard input. + // + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_INPUT); + + // + // Enable input mode in the GPIO module. + // + GPIODirModeSet(1 << ui32IOId, GPIO_DIR_MODE_IN); +} +//***************************************************************************** +// +//! Setup an IO for standard GPIO output +// +//***************************************************************************** +void +IOCPinTypeGpioOutput(uint32_t ui32IOId) +{ + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + + // + // Setup the IO for standard input. + // + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_OUTPUT); + + // + // Enable output mode in the GPIO module. + // + GPIODirModeSet(1 << ui32IOId, GPIO_DIR_MODE_OUT); +} +//***************************************************************************** +// +//! Configure a set of IOs for standard UART peripheral control +// +//***************************************************************************** +void +IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, + uint32_t ui32Cts, uint32_t ui32Rts) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == UART0_BASE); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Cts <= IOID_31) || (ui32Cts == IOID_UNUSED)); + ASSERT((ui32Rts <= IOID_31) || (ui32Rts == IOID_UNUSED)); + + // + // Setup the IOs in the desired configuration. + // + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_UART0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_UART0_TX, IOC_STD_OUTPUT); + } + if(ui32Cts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Cts, IOC_PORT_MCU_UART0_CTS, IOC_STD_INPUT); + } + if(ui32Rts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rts, IOC_PORT_MCU_UART0_RTS, IOC_STD_OUTPUT); + } +} +//***************************************************************************** +// +//! Configure a set of IOs for standard SSI peripheral master control +// +//***************************************************************************** +void +IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // + // Setup the IOs in the desired configuration. + // + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_OUTPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_OUTPUT); + } + } +} +//***************************************************************************** +// +//! Configure a set of IOs for standard SSI peripheral slave control +// +//***************************************************************************** +void +IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // + // Setup the IOs in the desired configuration. + // + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_INPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_INPUT); + } + } +} +//***************************************************************************** +// +//! Configure a set of IOs for standard I2C peripheral control +// +//***************************************************************************** +void +IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk) +{ + uint32_t ui32IOConfig; + + // + // Check the arguments. + // + ASSERT((ui32Data <= IOID_31) || (ui32Data == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // + // Define the IO configuration parameters. + // + ui32IOConfig = IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_IOPULL_UP | + IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | + IOC_INT_DISABLE | IOC_IOMODE_OPEN_DRAIN_NORMAL | + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE; + + // + // Setup the IOs in the desired configuration. + // + IOCPortConfigureSet(ui32Data, IOC_PORT_MCU_I2C_MSSDA, ui32IOConfig); + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_I2C_MSSCL, ui32IOConfig); +} +//***************************************************************************** +// +//! Configure a set of IOs for standard SPIS peripheral control +// +//***************************************************************************** +void +IOCPinTypeSpis(uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // + // Check the arguments. + // + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // + // Setup the IOs in the desired configuration. + // + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_AON_SDI, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_AON_SDO, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_AON_SCS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_AON_SCK, IOC_STD_INPUT); + } +} +//***************************************************************************** +// +//! Configure an IO for AUX control +// +//***************************************************************************** +void +IOCPinTypeAux(uint32_t ui32IOId) +{ + // + // Check the arguments. + // + ASSERT((ui32IOId <= IOID_31) || (ui32IOId == IOID_UNUSED)); + + // + // Setup the IO. + // + IOCPortConfigureSet(ui32IOId, IOC_PORT_AUX_IO, IOC_STD_INPUT); +} +//! @} +//! \\addtogroup prcm_api +//! @{ + +//***************************************************************************** +// +// Arrays that maps the "peripheral set" number (which is stored in the +// third nibble of the PRCM_PERIPH_* defines) to the PRCM register that +// contains the relevant bit for that peripheral. +// +//***************************************************************************** + +// Run mode registers +static const uint32_t g_pui32RCGCRegs[] = +{ + PRCM_O_GPTCLKGR, + PRCM_O_SSICLKGR, + PRCM_O_UARTCLKGR, + PRCM_O_I2CCLKGR, + PRCM_O_SECDMACLKGR, + PRCM_O_GPIOCLKGR, + PRCM_O_I2SCLKGR +}; + +// Sleep mode registers +static const uint32_t g_pui32SCGCRegs[] = +{ + PRCM_O_GPTCLKGS, + PRCM_O_SSICLKGS, + PRCM_O_UARTCLKGS, + PRCM_O_I2CCLKGS, + PRCM_O_SECDMASCLKG, + PRCM_O_GPIOCLKGS, + PRCM_O_I2SCLKGS +}; + +// Deep sleep mode registers +static const uint32_t g_pui32DCGCRegs[] = +{ + PRCM_O_GPTCLKGDS, + PRCM_O_SSICLKGDS, + PRCM_O_UARTCLKGDS, + PRCM_O_I2CCLKGDS, + PRCM_O_SECDMACLKGDS, + PRCM_O_GPIOCLKGDS, + PRCM_O_I2SCLKGDS +}; + +//***************************************************************************** +// +// This macro extracts the array index out of the peripheral number +// +//***************************************************************************** +#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf) + +//***************************************************************************** +// +// This macro extracts the peripheral instance number and generates bit mask +// +//***************************************************************************** +#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0xf)) + +//***************************************************************************** +// +//! Configure the infrastructure clock. +// +//***************************************************************************** +void +PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode) +{ + uint32_t ui32Divisor; + + // + // Check the arguments. + // + ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || + (ui32ClkDiv == PRCM_CLOCK_DIV_2) || + (ui32ClkDiv == PRCM_CLOCK_DIV_8) || + (ui32ClkDiv == PRCM_CLOCK_DIV_32)); + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32Divisor = 0; + + // + // Find the correct division factor. + // + if(ui32ClkDiv == PRCM_CLOCK_DIV_1) + { + ui32Divisor = 0x0; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_2) + { + ui32Divisor = 0x1; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_8) + { + ui32Divisor = 0x2; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_32) + { + ui32Divisor = 0x3; + } + + // + // Determine the correct power mode set the division factor accordingly. + // + if(ui32PowerMode == PRCM_RUN_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor; + } +} +//***************************************************************************** +// +//! Use this function to retreive the set infrastructure clock configuration +// +//***************************************************************************** +uint32_t +PRCMInfClockConfigureGet(uint32_t ui32PowerMode) +{ + uint32_t ui32ClkDiv; + uint32_t ui32Divisor; + + // + // Check the arguments. + // + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32ClkDiv = 0; + ui32Divisor = 0; + + // + // Determine the correct power mode. + // + if(ui32PowerMode == PRCM_RUN_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR); + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS); + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS); + } + + // + // Find the correct division factor. + // + if(ui32ClkDiv == 0x0) + { + ui32Divisor = PRCM_CLOCK_DIV_1; + } + else if(ui32ClkDiv == 0x1) + { + ui32Divisor = PRCM_CLOCK_DIV_2; + } + else if(ui32ClkDiv == 0x2) + { + ui32Divisor = PRCM_CLOCK_DIV_8; + } + else if(ui32ClkDiv == 0x3) + { + ui32Divisor = PRCM_CLOCK_DIV_32; + } + + // + // Return the clock divison factor. + // + return ui32Divisor; +} +//***************************************************************************** +// +//! Setup the clock division factor for a subsystem in the MCU voltage +//! domain. +// +//***************************************************************************** +void +PRCMClockConfigureSet(uint32_t ui32Domains, uint32_t ui32ClkDiv) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT((ui32Domains & PRCM_DOMAIN_SYSBUS) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_TIMER) || + (ui32Domains & PRCM_DOMAIN_SERIAL)); + ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || + (ui32ClkDiv == PRCM_CLOCK_DIV_2) || + (ui32ClkDiv == PRCM_CLOCK_DIV_4) || + (ui32ClkDiv == PRCM_CLOCK_DIV_8) || + (ui32ClkDiv == PRCM_CLOCK_DIV_16) || + (ui32ClkDiv == PRCM_CLOCK_DIV_32) || + (ui32ClkDiv == PRCM_CLOCK_DIV_64) || + (ui32ClkDiv == PRCM_CLOCK_DIV_128) || + (ui32ClkDiv == PRCM_CLOCK_DIV_256)); + + // + // Configure the selected clock dividers. + // + if(ui32Domains & PRCM_DOMAIN_SYSBUS) + { + ui32Reg = PRCM_O_SYSBUSCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + ui32Reg = PRCM_O_CPUCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + ui32Reg = PRCM_O_PERBUSCPUCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + ui32Reg = PRCM_O_PERDMACLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_TIMER) + { + ui32Reg = PRCM_O_GPTCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } +} +//***************************************************************************** +// +//! Get the clock configuration for a specific sub system in the MCU Voltage +//! Domain. +// +//***************************************************************************** +uint32_t +PRCMClockConfigureGet(uint32_t ui32Domain) +{ + uint32_t ui32ClkDiv; + + // + // Check the arguments. + // + ASSERT((ui32Domain == PRCM_DOMAIN_SYSBUS) || + (ui32Domain == PRCM_DOMAIN_CPU) || + (ui32Domain == PRCM_DOMAIN_PERIPH) || + (ui32Domain == PRCM_DOMAIN_TIMER) || + (ui32Domain == PRCM_DOMAIN_SERIAL)); + + ui32ClkDiv = 0; + + // + // Find the correct sub system. + // + if(ui32Domain == PRCM_DOMAIN_SYSBUS) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_SYSBUSCLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_CPU) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_CPUCLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_PERIPH) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_PERBUSCPUCLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_SERIAL) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_PERDMACLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_TIMER) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_GPTCLKDIV); + } + + // + // Return the clock configuration. + // + return(ui32ClkDiv); +} +//***************************************************************************** +// +//! Configure the audio clock generation +// +//***************************************************************************** +void +PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate) +{ + uint32_t ui32Reg; + uint32_t ui32MstDiv; + uint32_t ui32BitDiv; + uint32_t ui32WordDiv; + + // + // Check the arguments. + // + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) || + (ui32SampleRate == I2S_SAMPLE_RATE_24K) || + (ui32SampleRate == I2S_SAMPLE_RATE_32K) || + (ui32SampleRate == I2S_SAMPLE_RATE_48K)); + + ui32MstDiv = 0; + ui32BitDiv = 0; + ui32WordDiv = 0; + + // + // Make sure the audio clock generation is disabled before reconfiguring. + // + PRCMAudioClockDisable(); + + // + // Define the clock division factors for the audio interface. + // + switch(ui32SampleRate) + { + case I2S_SAMPLE_RATE_16K : + ui32MstDiv = 6; + ui32BitDiv = 60; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_24K : + ui32MstDiv = 4; + ui32BitDiv = 40; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_32K : + ui32MstDiv = 3; + ui32BitDiv = 30; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_48K : + ui32MstDiv = 2; + ui32BitDiv = 20; + ui32WordDiv = 25; + break; + } + + // + // Make sure to compensate the Frame clock division factor if using single + // phase format. + // + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // + // Write the clock divison factors. + // + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // + // Configure the Word clock format and polarity. + // + ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} +//***************************************************************************** +// +//! Turn power on in power domains in the MCU domain +// +//***************************************************************************** +void +PRCMPowerDomainOn(uint32_t ui32Domains) +{ + // + // Check the arguments. + // + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // + // Assert the request to power on the right domains. + // + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + + PRCM_O_PDCTL0RFC) |= PRCM_PDCTL0RFC_ON; + HWREG(PRCM_BASE + PRCM_O_PDCTL1RFC) |= PRCM_PDCTL1RFC_ON; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + + PRCM_O_PDCTL0SERIAL) |= PRCM_PDCTL0SERIAL_ON; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + + PRCM_O_PDCTL0PERIPH) |= PRCM_PDCTL0PERIPH_ON; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) |= + PRCM_PDCTL1VIMS_ON; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU) |= PRCM_PDCTL1CPU_ON; + } +} +//***************************************************************************** +// +//! Turn off a specific power domain +// +//***************************************************************************** +void +PRCMPowerDomainOff(uint32_t ui32Domains) +{ + // + // Check the arguments. + // + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // + // Assert the request to power off the right domains. + // + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + + PRCM_O_PDCTL0RFC) &= ~PRCM_PDCTL0RFC_ON; + HWREG(PRCM_BASE + PRCM_O_PDCTL1RFC) &= ~PRCM_PDCTL1RFC_ON; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + + PRCM_O_PDCTL0SERIAL) &= ~PRCM_PDCTL0SERIAL_ON; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + + PRCM_O_PDCTL0PERIPH) &= ~PRCM_PDCTL0PERIPH_ON; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) &= + ~PRCM_PDCTL1VIMS_ON; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU) &= ~PRCM_PDCTL1CPU_ON; + } +} +//***************************************************************************** +// +//! Enables a peripheral in Run mode +// +//***************************************************************************** +void +PRCMPeripheralRunEnable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // + // Enable module in Run Mode. + // + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} +//***************************************************************************** +// +//! Disables a peripheral in Run mode +// +//***************************************************************************** +void +PRCMPeripheralRunDisable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // + // Disable module in Run Mode. + // + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} +//***************************************************************************** +// +//! Enables a peripheral in sleep mode +// +//***************************************************************************** +void +PRCMPeripheralSleepEnable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // + // Enable this peripheral in sleep mode. + // + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} +//***************************************************************************** +// +//! Disables a peripheral in sleep mode +// +//***************************************************************************** +void +PRCMPeripheralSleepDisable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // + // Disable this peripheral in sleep mode + // + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} +//***************************************************************************** +// +//! Enables a peripheral in deep-sleep mode +// +//***************************************************************************** +void +PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // + // Enable this peripheral in deep-sleep mode. + // + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} +//***************************************************************************** +// +//! Disables a peripheral in deep-sleep mode +// +//***************************************************************************** +void +PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // + // Disable this peripheral in Deep Sleep mode. + // + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} +//***************************************************************************** +// +//! Get the status for a specific power domain +// +//***************************************************************************** +uint32_t +PRCMPowerDomainStatus(uint32_t ui32Domains) +{ + bool bStatus; + uint32_t ui32StatusRegister0; + uint32_t ui32StatusRegister1; + + // + // Check the arguments. + // + ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE | + PRCM_DOMAIN_SERIAL | + PRCM_DOMAIN_PERIPH))); + + bStatus = true; + ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0); + ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1); + + // + // Return the correct power status. + // + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + bStatus = bStatus && + ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) || + (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON)); + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON); + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON); + } + + // + // Return the status. + // + return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF); +} +//***************************************************************************** +// +//! Put the processor into deep-sleep mode +// +//***************************************************************************** +void +PRCMDeepSleep(void) +{ + // + // Enable deep-sleep. + // + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // + // Wait for an interrupt. + // + CPUwfi(); + + // + // Disable deep-sleep so that a future sleep will work correctly. + // + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} +//***************************************************************************** +// +//! Enable retention on specific power domains +// +//***************************************************************************** +void +PRCMRetentionEnable(uint32_t ui32PowerDomain) +{ + uint32_t ui32Retention; + + // + // Check the arguments. + // + ASSERT((PRCM_DOMAIN_PERIPH & ui32PowerDomain) || + (PRCM_DOMAIN_CPU & ui32PowerDomain)); + + // + // Get the current register. + // + ui32Retention = HWREG(PRCM_BASE + PRCM_O_PDRETEN); + + // + // Set the bits. + // + if(PRCM_DOMAIN_PERIPH & ui32PowerDomain) + { + ui32Retention |= PRCM_PDRETEN_PERIPH; + } + if(PRCM_DOMAIN_CPU & ui32PowerDomain) + { + ui32Retention |= PRCM_PDRETEN_CPU; + } + + // + // Reconfigure retention. + // + HWREG(PRCM_BASE + PRCM_O_PDRETEN) = ui32Retention; + + // + // Get the current register values. + // + ui32Retention = HWREG(PRCM_BASE + PRCM_O_RAMRETEN); + + // + // Enable retention on RF core SRAM. + // + if(PRCM_DOMAIN_RFCORE & ui32PowerDomain) + { + ui32Retention |= PRCM_RAMRETEN_RFC_M; + } + + // + // Enable retention on VIMS cache. + // + if(PRCM_DOMAIN_VIMS & ui32PowerDomain) + { + ui32Retention |= PRCM_RAMRETEN_VIMS_M; + } + + // + // Reconfigure retention. + // + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention; +} +//***************************************************************************** +// +//! Disable retention on power domains +// +//***************************************************************************** +void +PRCMRetentionDisable(uint32_t ui32PowerDomain) +{ + uint32_t ui32Retention; + + // + // Check the arguments. + // + ASSERT((PRCM_DOMAIN_PERIPH & ui32PowerDomain) || + (PRCM_DOMAIN_CPU & ui32PowerDomain)); + + // + // Get the current register. + // + ui32Retention = HWREG(PRCM_BASE + PRCM_O_PDRETEN); + + // + // Clear the bits. + // + if(PRCM_DOMAIN_PERIPH & ui32PowerDomain) + { + ui32Retention &= ~PRCM_PDRETEN_PERIPH; + } + if(PRCM_DOMAIN_CPU & ui32PowerDomain) + { + ui32Retention &= ~PRCM_PDRETEN_CPU; + } + + // + // Reconfigure retention. + // + HWREG(PRCM_BASE + PRCM_O_PDRETEN) = ui32Retention; + + // + // Get the current register values + // + ui32Retention = HWREG(PRCM_BASE + PRCM_O_RAMRETEN); + + // + // Disable retention on RF core SRAM + // + if(PRCM_DOMAIN_RFCORE & ui32PowerDomain) + { + ui32Retention &= ~PRCM_RAMRETEN_RFC_M; + } + + // + // Disable retention on VIMS cache + // + if(PRCM_DOMAIN_VIMS & ui32PowerDomain) + { + ui32Retention &= ~PRCM_RAMRETEN_VIMS_M; + } + + // + // Reconfigure retention. + // + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention; +} +//! @} +//! \\addtogroup smph_api +//! @{ +//***************************************************************************** +// +//! Acquire a semaphore +// +//***************************************************************************** +void +SMPHAcquire(uint32_t ui32Semaphore) +{ + // + // Check the arguments. + // + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // + // Wait for semaphore to be release such that it can be claimed + // Semaphore register reads 1 when lock was acquired otherwise 0 + // (i.e. SMPH_CLAIMED). + // + while(HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) == + SMPH_CLAIMED) + { + } +} +//! @} +//! \\addtogroup spis_api +//! @{ +//***************************************************************************** +// +// This is the mapping between an TX Fifo index and the corresponding +// register. +// +//***************************************************************************** +static const uint32_t g_pui32SPISTxFifo[] = +{ + SPIS_O_TXFMEM0, SPIS_O_TXFMEM1, SPIS_O_TXFMEM2, SPIS_O_TXFMEM3, SPIS_O_TXFMEM4, + SPIS_O_TXFMEM5, SPIS_O_TXFMEM6, SPIS_O_TXFMEM7, SPIS_O_TXFMEM8, SPIS_O_TXFMEM9, + SPIS_O_TXFMEM10, SPIS_O_TXFMEM11, SPIS_O_TXFMEM12, SPIS_O_TXFMEM13, + SPIS_O_TXFMEM14, SPIS_O_TXFMEM15 +}; + +//***************************************************************************** +// +// This is the mapping between an RX Fifo index and the corresponding +// register. +// +//***************************************************************************** +static const uint32_t g_pui32SPISRxFifo[] = +{ + SPIS_O_RXFMEM0, SPIS_O_RXFMEM1, SPIS_O_RXFMEM2, SPIS_O_RXFMEM3, SPIS_O_RXFMEM4, + SPIS_O_RXFMEM5, SPIS_O_RXFMEM6, SPIS_O_RXFMEM7, SPIS_O_RXFMEM8, SPIS_O_RXFMEM9, + SPIS_O_RXFMEM10, SPIS_O_RXFMEM11, SPIS_O_RXFMEM12, SPIS_O_RXFMEM13, + SPIS_O_RXFMEM14, SPIS_O_RXFMEM15 +}; +//***************************************************************************** +// +//! Puts a data element into the SPIS transmit FIFO +// +//***************************************************************************** +void +SPISDataPut(uint32_t ui32Data) +{ + // + // Wait until there is space. + // + while(HWREG(SPIS_BASE + SPIS_O_TXFSTAT) & SPIS_TXFSTAT_FULL) + { + } + + // + // Write the data to the SPIS Tx Fifo. + // + HWREG(SPIS_BASE + SPIS_O_TXFPUSH) = ui32Data; +} +//***************************************************************************** +// +//! Get a specific value in the Tx Fifo +// +//***************************************************************************** +uint32_t +SPISTxGetValue(uint32_t ui32Index) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(ui32Index < TX_FIFO_SIZE); + + // + // Find the correct register. + // + ui32Reg = g_pui32SPISTxFifo[ui32Index]; + + // + // Return the value of the TX Fifo at the specified index. + // + return HWREG(SPIS_BASE + ui32Reg); +} +//***************************************************************************** +// +//! Gets a data element from the SPIS Rx FIFO +// +//***************************************************************************** +void +SPISDataGet(uint32_t *pui32Data) +{ + // + // Wait until there is data to be read. + // + while(!(HWREG(SPIS_BASE + SPIS_O_RXFSTAT) & SPIS_RXFSTAT_NOT_EMPTY)) + { + } + + // + // Read data from SPIS Rx Fifo. + // + *pui32Data = HWREG(SPIS_BASE + SPIS_O_RXFPOP); +} +//***************************************************************************** +// +//! Get a specific value in the Rx Fifo +// +//***************************************************************************** +uint32_t +SPISRxGetValue(uint32_t ui32Index) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(ui32Index < RX_FIFO_SIZE); + + // + // Find the correct register. + // + ui32Reg = g_pui32SPISRxFifo[ui32Index]; + + // + // Return the value of the RX Fifo at the specified index. + // + return HWREG(SPIS_BASE + ui32Reg); +} +//***************************************************************************** +// +//! Gets the current interrupt status +//! +//! \param bMasked is \b false if the raw interrupt status is required or +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the SPIS module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status consisting of a bitwise OR value +//! of the available interrupts sources as described in \b SPISIntEnable(). +// +//***************************************************************************** +uint32_t +SPISIntStatus(bool bMasked) +{ + uint32_t ui32IntStatus, ui32Tmp; + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + ui32Tmp = HWREG(SPIS_BASE + SPIS_O_TXFFLAGSCLRN); + ui32IntStatus = ui32Tmp & HWREG(SPIS_BASE + SPIS_O_TXFFLAGSMASK); + ui32Tmp = HWREG(SPIS_BASE + SPIS_O_RXFFLAGSCLRN); + ui32IntStatus |= (ui32Tmp & HWREG(SPIS_BASE + SPIS_O_RXFFLAGSMASK)) << 8; + ui32Tmp = HWREG(SPIS_BASE + SPIS_O_GPFLAGS); + ui32IntStatus |= (ui32Tmp & HWREG(SPIS_BASE + SPIS_O_GPFLAGSMASK)) << 16; + } + else + { + ui32IntStatus = HWREG(SPIS_BASE + SPIS_O_TXFFLAGSCLRN) & SPIS_TX_MASK; + ui32IntStatus |= (HWREG(SPIS_BASE + SPIS_O_RXFFLAGSCLRN) << 8) & SPIS_RX_MASK; + ui32IntStatus |= (HWREG(SPIS_BASE + SPIS_O_GPFLAGS) << 16) & SPIS_GP_MASK; + } + return ui32IntStatus; +} +//! @} +//! \\addtogroup ssi_api +//! @{ +//***************************************************************************** +// +//! Configures the synchronous serial port +// +//***************************************************************************** +void +SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, uint32_t ui32DataWidth) +{ + uint32_t ui32MaxBitRate; + uint32_t ui32RegVal; + uint32_t ui32PreDiv; + uint32_t ui32SCR; + uint32_t ui32SPH_SPO; + + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || + (ui32Protocol == SSI_FRF_MOTO_MODE_1) || + (ui32Protocol == SSI_FRF_MOTO_MODE_2) || + (ui32Protocol == SSI_FRF_MOTO_MODE_3) || + (ui32Protocol == SSI_FRF_TI) || + (ui32Protocol == SSI_FRF_NMW)); + ASSERT((ui32Mode == SSI_MODE_MASTER) || + (ui32Mode == SSI_MODE_SLAVE) || + (ui32Mode == SSI_MODE_SLAVE_OD)); + ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) || + ((ui32Mode != SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 12)))); + ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); + ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); + + // + // Set the mode. + // + ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; + + // + // Set the clock predivider. + // + ui32MaxBitRate = ui32SSIClk / ui32BitRate; + ui32PreDiv = 0; + do + { + ui32PreDiv += 2; + ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; + } + while(ui32SCR > 255); + HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; + + // + // Set protocol and clock rate. + // + ui32SPH_SPO = (ui32Protocol & 3) << 6; + ui32Protocol &= SSI_CR0_FRF_M; + ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | (ui32DataWidth - 1); + HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; +} +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO +// +//***************************************************************************** +void +SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // + // Wait until there is space. + // + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // + // Write the data to the SSI. + // + HWREG(ui32Base + SSI_O_DR) = ui32Data; +} +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO +// +//***************************************************************************** +int32_t +SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // + // Check for space to write. + // + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ui32Base + SSI_O_DR) = ui32Data; + return(1); + } + else + { + return(0); + } +} +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO +// +//***************************************************************************** +void +SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ui32Base)); + + // + // Wait until there is data to be read. + // + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // + // Read data from SSI. + // + *pui32Data = HWREG(ui32Base + SSI_O_DR); +} +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pui32Data is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! This function gets received data from the receive FIFO of the specified SSI +//! module and places that data into the location specified by the \e ui32Data +//! parameter. If there is no data in the FIFO, then this function returns a +//! zero. +//! +//! \note Only the lower N bits of the value written to \e pui32Data contain +//! valid data, where N is the data width as configured by \sa +//! SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to \e pui32Data +//! contain valid data. +//! +//! \return Returns the number of elements read from the SSI receive FIFO. +// +//***************************************************************************** +int32_t +SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ui32Base)); + + // + // Check for data to read. + // + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) + { + *pui32Data = HWREG(ui32Base + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} +//! @} +//! \\addtogroup timer_api +//! @{ +//***************************************************************************** +// +//! Configures the timer(s) +// +//***************************************************************************** +void +TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || + (ui32Config == TIMER_CFG_ONE_SHOT_UP) || + (ui32Config == TIMER_CFG_PERIODIC) || + (ui32Config == TIMER_CFG_PERIODIC_UP) || + (ui32Config == TIMER_CFG_RTC) || + ((ui32Config & 0xFF000000) == TIMER_CFG_SPLIT_PAIR)); + ASSERT(((ui32Config & 0xFF000000) != TIMER_CFG_SPLIT_PAIR) || + ((((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PWM)) && + (((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PWM)))); + + // + // Disable the timers. + // + HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); + + // + // Set the global timer configuration. + // + HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24; + + // + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + // + HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE; + HWREG(ui32Base + GPT_O_TBMR) = + ((ui32Config >> 8) & 0xFF) | GPT_TBMR_TBPWMIE; +} +//***************************************************************************** +// +//! Controls the output level +// +//***************************************************************************** +void +TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Set the output levels as requested. + // + ui32Timer &= GPT_CTL_TAPWML | GPT_CTL_TBPWML; + HWREG(ui32Base + GPT_O_CTL) = (bInvert ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & + ~(ui32Timer))); +} +//***************************************************************************** +// +//! Enables or disables the ADC trigger output +// +//***************************************************************************** +void +TimerTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bEnable) +{ + uint32_t ui32Val; + + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Determine which bits to set or clear in GPTM_ADCEV. + // + ui32Val = (GPT_ADCEV_TATOADCEN | GPT_ADCEV_TBTOADCEN); + ui32Val &= ui32Timer; + + // + // Write the GPTM ADC Event register to enable or disable the trigger. + // to the ADC. + // + HWREG(ui32Base + GPT_O_ADCEV) = (bEnable ? + (HWREG(ui32Base + GPT_O_ADCEV) | ui32Val) : + (HWREG(ui32Base + GPT_O_ADCEV) & + ~(ui32Val))); + + // + // Set the trigger output as requested. + // Set the ADC trigger output as requested. + // + ui32Timer &= GPT_CTL_TAOTE | GPT_CTL_TBOTE; + HWREG(ui32Base + GPT_O_CTL) = (bEnable ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & + ~(ui32Timer))); +} +//***************************************************************************** +// +//! Controls the stall handling +// +//***************************************************************************** +void +TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Set the stall mode. + // + ui32Timer &= GPT_CTL_TASTALL | GPT_CTL_TBSTALL; + HWREG(ui32Base + GPT_O_CTL) = (bStall ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer))); +} +//***************************************************************************** +// +//! Controls the wait on trigger handling +// +//***************************************************************************** +void +TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Set the wait on trigger mode for timer A. + // + if(ui32Timer & TIMER_A) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAWOT; + } + else + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAWOT); + } + } + + // + // Set the wait on trigger mode for timer B. + // + if(ui32Timer & TIMER_B) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBWOT; + } + else + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBWOT); + } + } +} +//! @} +//! \\addtogroup trng_api +//! @{ +//***************************************************************************** +// +//! Configure the true random number generator +// +//***************************************************************************** +void +TRNGConfigure(uint32_t ui32MinSamplesPerCycle, + uint32_t ui32MaxSamplesPerCycle, + uint32_t ui32ClocksPerSample) +{ + uint32_t ui32Val; + + // + // Make sure the TRNG is disabled. + // + ui32Val = HWREG(TRNG_BASE + TRNG_O_CTL) & ~TRNG_CTL_TRNG_EN; + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // + // Configure the startup number of samples. + // + ui32Val &= ~TRNG_CTL_STARTUP_CYCLES_M; + ui32Val |= ((ui32MaxSamplesPerCycle >> 8) & 0xFFFF) << 16; + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // + // Configure the minimum and maximum number of samples pr generated number + // and the number of clocks per sample. + // + HWREG(TRNG_BASE + TRNG_O_CFG0) = + (((ui32MaxSamplesPerCycle >> 8) & 0xFFFF) << 16) | + ((ui32ClocksPerSample & 0xFF) << 8) | + ((ui32MinSamplesPerCycle >> 6) & 0xFF); +} +//***************************************************************************** +// +//! Get a random number from the generator +// +//***************************************************************************** +uint32_t +TRNGNumberGet(uint32_t ui32Word) +{ + uint32_t ui32RandomNumber; + + // + // Check the arguments. + // + ASSERT((ui32Word == TRNG_HI_WORD) || + (ui32Word == TRNG_LOW_WORD)); + + // + // Return the right requested part of the generated number. + // + if(ui32Word == TRNG_HI_WORD) + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT1); + } + else + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT0); + } + + // + // Initiate generation of new number. + // + HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1; + + // + // Return the random number. + // + return ui32RandomNumber; +} +//! @} +//! \\addtogroup uart_api +//! @{ +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated +// +//***************************************************************************** +void +UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel) +{ + uint32_t ui32Temp; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Read the FIFO level register. + // + ui32Temp = HWREG(ui32Base + UART_O_IFLS); + + // + // Extract the transmit and receive FIFO levels. + // + *pui32TxLevel = ui32Temp & UART_IFLS_TXSEL_M; + *pui32RxLevel = ui32Temp & UART_IFLS_RXSEL_M; +} +//***************************************************************************** +// +//! Sets the configuration of a UART +// +//***************************************************************************** +void +UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config) +{ + uint32_t ui32Div; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + ASSERT(ui32Baud != 0); + + // + // Stop the UART. + // + UARTDisable(ui32Base); + + // + // Compute the fractional baud rate divider. + // + ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; + + // + // Set the baud rate. + // + HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; + HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; + + // + // Set parity, data length, and number of stop bits. + // + HWREG(ui32Base + UART_O_LCRH) = ui32Config; + + // + // Clear the flags register. + // + HWREG(ui32Base + UART_O_FR) = 0; +} +//***************************************************************************** +// +//! Gets the current configuration of a UART +// +//***************************************************************************** +void +UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config) +{ + uint32_t ui32Int, ui32Frac; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Compute the baud rate. + // + ui32Int = HWREG(ui32Base + UART_O_IBRD); + ui32Frac = HWREG(ui32Base + UART_O_FBRD); + *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); + + // + // Get the parity, data length, and number of stop bits. + // + *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | + UART_LCRH_EPS | UART_LCRH_PEN)); +} +//***************************************************************************** +// +//! Disables transmitting and receiving +// +//***************************************************************************** +void +UARTDisable(uint32_t ui32Base) +{ + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Wait for end of TX. + // + while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) + { + } + + // + // Disable the FIFO. + // + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); + + // + // Disable the UART. + // + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} +//***************************************************************************** +// +//! Receives a character from the specified port +// +//***************************************************************************** +int32_t +UARTCharGetNonBlocking(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // See if there are any characters in the receive FIFO. + // + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) + { + // + // Read and return the next character. + // + return(HWREG(ui32Base + UART_O_DR)); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } +} +//***************************************************************************** +// +//! Waits for a character from the specified port +// +//***************************************************************************** +int32_t +UARTCharGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Wait until a char is available. + // + while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) + { + } + + // + // Now get the character. + // + return(HWREG(ui32Base + UART_O_DR)); +} +//***************************************************************************** +// +//! Sends a character to the specified port +// +//***************************************************************************** +bool +UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // See if there is space in the transmit FIFO. + // + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) + { + // + // Write this character to the transmit FIFO. + // + HWREG(ui32Base + UART_O_DR) = ui8Data; + + // + // Success. + // + return(true); + } + else + { + // + // There is no space in the transmit FIFO, so return a failure. + // + return(false); + } +} +//***************************************************************************** +// +//! Waits to send a character from the specified port +// +//***************************************************************************** +void +UARTCharPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Wait until space is available. + // + while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) + { + } + + // + // Send the char. + // + HWREG(ui32Base + UART_O_DR) = ui8Data; +} +//! @} +//! \\addtogroup udma_api +//! @{ +//***************************************************************************** +// +//! Enables attributes of a uDMA channel +// +//***************************************************************************** +void +uDMAChannelAttributeEnable(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32Attr) +{ + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // Set the useburst bit for this channel if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_SETBURST) = 1 << ui32ChannelNum; + } + + // + // Set the alternate control select bit for this channel, + // if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // + // Set the high priority bit for this channel, if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // + // Set the request mask bit for this channel, if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_SETREQMASK) = 1 << ui32ChannelNum; + } +} +//***************************************************************************** +// +//! Disables attributes of an uDMA channel +// +//***************************************************************************** +void +uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32Attr) +{ + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // Clear the useburst bit for this channel if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_CLEARBURST) = 1 << ui32ChannelNum; + } + + // + // Clear the alternate control select bit for this channel, if set in + // ululAttr. + // + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // + // Clear the high priority bit for this channel, if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // + // Clear the request mask bit for this channel, if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_CLEARREQMASK) = 1 << ui32ChannelNum; + } +} +//***************************************************************************** +// +//! Gets the enabled attributes of a uDMA channel +// +//***************************************************************************** +uint32_t +uDMAChannelAttributeGet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + uint32_t ui32Attr = 0; + + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // + // Check to see if useburst bit is set for this channel. + // + if(HWREG(ui32Base + UDMA_O_SETBURST) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_USEBURST; + } + + // + // Check to see if the alternate control bit is set for this channel. + // + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_ALTSELECT; + } + + // + // Check to see if the high priority bit is set for this channel. + // + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // + // Check to see if the request mask bit is set for this channel. + // + if(HWREG(ui32Base + UDMA_O_SETREQMASK) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_REQMASK; + } + + // + // Return the configuration flags. + // + return(ui32Attr); +} +//***************************************************************************** +// +//! Sets the control parameters for a uDMA channel control structure +// +//***************************************************************************** +void +uDMAChannelControlSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, + uint32_t ui32Control) +{ + tDMAControlTable *pControlTable; + + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + // + pControlTable[ui32ChannelStructIndex].ui32Control = + ((pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_DST_INC_M | + UDMA_SRC_INC_M | + UDMA_SIZE_M | + UDMA_ARB_M | + UDMA_NEXT_USEBURST)) | + ui32Control); +} +//***************************************************************************** +// +//! Sets the transfer parameters for a uDMA channel control structure +// +//***************************************************************************** +void +uDMAChannelTransferSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, + uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, + uint32_t ui32TransferSize) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + uint32_t ui32Inc; + uint32_t ui32BufferBytes; + + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((uint32_t)pvSrcAddr >= SRAM_BASE); + ASSERT((uint32_t)pvDstAddr >= SRAM_BASE); + ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= UDMA_XFER_SIZE_MAX)); + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // + // Get the current control word value and mask off the mode and size + // fields. + // + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // + // Adjust the mode if the alt control structure is selected. + // + if(ui32ChannelStructIndex & UDMA_ALT_SELECT) + { + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Mode |= UDMA_MODE_ALT_SELECT; + } + } + + // + // Set the transfer size and mode in the control word (but don't write the + // control word yet as it could kick off a transfer). + // + ui32Control |= ui32Mode | ((ui32TransferSize - 1) << UDMA_XFER_SIZE_S); + + // + // Get the address increment value for the source, from the control word. + // + ui32Inc = (ui32Control & UDMA_SRC_INC_M); + + // + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + // + if(ui32Inc != UDMA_SRC_INC_NONE) + { + ui32Inc = ui32Inc >> UDMA_SRC_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - 1); + } + + // + // Load the source ending address into the control block. + // + pControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; + + // + // Get the address increment value for the destination, from the control + // word. + // + ui32Inc = ui32Control & UDMA_DST_INC_M; + + // + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + // + if(ui32Inc != UDMA_DST_INC_NONE) + { + // + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer needs to point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + // + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + pvDstAddr = + (void *)&pControlTable[ui32ChannelStructIndex | + UDMA_ALT_SELECT].ui32Spare; + } + // + // Not a scatter-gather transfer, calculate end pointer normally. + // + else + { + ui32Inc = ui32Inc >> UDMA_DST_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); + } + } + + // + // Load the destination ending address into the control block. + // + pControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; + + // + // Write the new control word value. + // + pControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; +} +//***************************************************************************** +// +//! Configures a uDMA channel for scatter-gather mode +// +//***************************************************************************** +void +uDMAChannelScatterGatherSet(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32TaskCount, void *pvTaskList, + uint32_t ui32IsPeriphSG) +{ + tDMAControlTable *pControlTable; + tDMAControlTable *pTaskTable; + + // + // Check the parameters. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(pvTaskList != 0); + ASSERT(ui32TaskCount <= UDMA_XFER_SIZE_MAX); + ASSERT(ui32TaskCount != 0); + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // + // Get a handy pointer to the task list. + // + pTaskTable = (tDMAControlTable *)pvTaskList; + + // + // Compute the ending address for the source pointer. This will be the + // last element of the last task in the task table. + // + pControlTable[ui32ChannelNum].pvSrcEndAddr = + &pTaskTable[ui32TaskCount - 1].ui32Spare; + + // + // Compute the ending address for the destination pointer. This will be + // the end of the alternate structure for this channel. + // + pControlTable[ui32ChannelNum].pvDstEndAddr = + &pControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; + + // + // Compute the control word. Most configurable items are fixed for + // scatter-gather. Item and increment sizes are all 32-bit and arb + // size must be 4. The count is the number of items in the task list + // times 4 (4 words per task). + // + pControlTable[ui32ChannelNum].ui32Control = + (UDMA_DST_INC_32 | UDMA_SRC_INC_32 | + UDMA_SIZE_32 | UDMA_ARB_4 | + (((ui32TaskCount * 4) - 1) << UDMA_XFER_SIZE_S) | + (ui32IsPeriphSG ? UDMA_MODE_PER_SCATTER_GATHER : + UDMA_MODE_MEM_SCATTER_GATHER)); + + // + // Scatter-gather operations can leave the alt bit set. So if doing + // back to back scatter-gather transfers, the second attempt may not + // work correctly because the alt bit is set. Therefore, clear the + // alt bit here to ensure that it is always cleared before a new SG + // transfer is started. + // + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; + +} +//***************************************************************************** +// +//! Gets the current transfer size for a uDMA channel control structure +// +//***************************************************************************** +uint32_t +uDMAChannelSizeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // + // Get the current control word value and mask off all but the size field + // and the mode field. + // + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + (UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // + // If the size field and mode field are 0 then the transfer is finished + // and there are no more items to transfer. + // + if(ui32Control == 0) + { + return(0); + } + + // + // Otherwise, if either the size field or more field is non-zero, then + // not all the items have been transferred. + // + else + { + // + // Shift the size field and add one, then return to user. + // + return((ui32Control >> UDMA_XFER_SIZE_S) + 1); + } +} +//***************************************************************************** +// +//! Gets the transfer mode for a uDMA channel control structure +// +//***************************************************************************** +uint32_t +uDMAChannelModeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // + // Get the current control word value and mask off all but the mode field. + // + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + UDMA_MODE_M); + + // + // Check if scatter/gather mode, and if so, mask off the alt bit. + // + if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || + ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Control &= ~UDMA_MODE_ALT_SELECT; + } + + // + // Return the mode to the caller. + // + return(ui32Control); +} +//! @} +//! \\addtogroup vims_api +//! @{ +//***************************************************************************** +// +//! Configures the VIMS. +// +//***************************************************************************** +void +VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG); + if(bRoundRobin) + { + ui32Reg |= VIMS_CTL_ARB_CFG; + } + if(bPrefetch) + { + ui32Reg |= VIMS_CTL_PREF_EN; + } + + // + // Set the Arbitration and prefetch mode. + // + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} +//***************************************************************************** +// +//! Set the operational mode of the VIMS +// +//***************************************************************************** +void +VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(VIMSBaseValid(ui32Base)); + + ASSERT((ui32Mode == VIMS_MODE_INVALIDATE) || + (ui32Mode == VIMS_MODE_DISABLED) || + (ui32Mode == VIMS_MODE_ENABLED) || + (ui32Mode == VIMS_MODE_OFF) || + (ui32Mode == VIMS_MODE_SPLIT)); + + // + // Set the mode. + // + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~VIMS_CTL_MODE_M; + ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M); + + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} +//***************************************************************************** +// +//! Get the current operational mode of the VIMS. +// +//***************************************************************************** +uint32_t +VIMSModeGet(uint32_t ui32Base) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_STAT); + if(ui32Reg & VIMS_STAT_INV) + { + return (VIMS_MODE_INVALIDATE); + } + else + { + return (ui32Reg & VIMS_STAT_MODE_M); + } +} +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rom/driverlib.elf b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rom/driverlib.elf new file mode 100644 index 0000000..14960e7 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rom/driverlib.elf differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rom/readme.txt b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rom/readme.txt new file mode 100644 index 0000000..baec5e2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rom/readme.txt @@ -0,0 +1,32 @@ +Debugging sessions in IAR Embedded Workbench (IAR) and Code Composer Studio (CCS) +can load symbol information covering the code in ROM. +Symbols are loaded by selecting the ELF files found in the same folder as this +readme.txt file. +In addition the source code for the driverlib functions in ROM is found in the +driverlib.c file in this folder. + +Loading ROM code symbols in CCS debug session: +- Start a debug session in your project +- Select Run > Load > Add Symbols to create additional symbols +- Browse to and select each ELF file in this folder in the 'Program file' field +- Set the value of 0 in the 'Code offset' field for each ELF file +- If you enter a driverlib function in ROM during your debuging session and + get this information: + 'Can't find a source file at "..//driverlib.c"' + you can navigate to the driverlib.c file in this folder by selecting + the 'Locate File..' button. + +Loading ROM code symbols for use in IAR debug session: +- In your project select the following before starting debug session: + Project > Options.. > Debugger and then select the 'Images'-tab +- In the 'Images'-tab do the following for each of the ELF files + located in the same folder as this reame.txt file: + -- Select the 'Download extra image' box + -- Browse to the ELF file in the 'Path:' field + -- Set the value of 0 in the 'Offset:' field + -- Select the 'Debug info only' box +- If you during a debug session enters a driverlib function in ROM you will + be notified by this message: + 'Could not find following file: ..//driverlib.c' + Select the browse button and select the driverlib.c file located in this + folder. diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/startup_files/ccfg.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/startup_files/ccfg.c new file mode 100644 index 0000000..f25d1ad --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/startup_files/ccfg.c @@ -0,0 +1,529 @@ +/****************************************************************************** +* Filename: ccfg.c +* Revised: $Date: 2017-08-08 15:34:36 +0200 (ti, 08 aug 2017) $ +* Revision: $Revision: 17873 $ +* +* Description: Customer Configuration for CC13x0 device family (HW rev 2). +* +* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __CCFC_C__ +#define __CCFC_C__ + +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ccfg_simple_struct.h" + +//***************************************************************************** +// +// Introduction +// +// This file contains fields used by Boot ROM, startup code, and SW radio +// stacks to configure chip behavior. +// +// Fields are documented in more details in hw_ccfg.h and CCFG.html in +// DriverLib documentation (doc_overview.html -> CPU Domain Memory Map -> CCFG). +// +// PLEASE NOTE: +// It is not recommended to do modifications inside the ccfg.c file. +// This file is part of the CoreSDK release and future releases may have +// important modifications and new fields added without notice. +// The recommended method to modify the CCFG settings is to have a separate +// .c file that defines the specific CCFG values to be +// overridden and then include the TI provided ccfg.c at the very end, +// giving default values for non-overriden settings. +// +// Example: +// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC +// //---- Use default values for all others ---- +// #include "/source/ti/devices//startup_files/ccfg.c" +// +//***************************************************************************** + +//***************************************************************************** +// +// Internal settings, forcing several bit-fields to be set to a specific value. +// +//***************************************************************************** + +//##################################### +// Force VDDR high setting (Higher output power but also higher power consumption) +//##################################### + +#ifndef CCFG_FORCE_VDDR_HH +#define CCFG_FORCE_VDDR_HH 0x0 // Use default VDDR trim +// #define CCFG_FORCE_VDDR_HH 0x1 // Force VDDR voltage to the factory HH setting (FCFG1..VDDR_TRIM_HH) +#endif + +//***************************************************************************** +// +// Set the values of the individual bit fields. +// +//***************************************************************************** + +//##################################### +// Alternative DC/DC settings +//##################################### + +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0 // Alternative DC/DC setting enabled +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x1 // Alternative DC/DC setting disabled +#endif + +#if ( CCFG_FORCE_VDDR_HH ) +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0xC // Special VMIN level (2.5V) when forced VDDR HH voltage +#else +#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0x8 // 2.25V +#endif +#endif + +#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN +// #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0 // Disable +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x1 // Enable +#endif + +#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x0 // 31mA +#endif + +//##################################### +// XOSC override settings +//##################################### + +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x0 // Enable override +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1 // Disable override +#endif + +#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT +#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 0x0 // Delta = 0 +#endif + +#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET +#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0 // Delta = 0 +#endif + +#ifndef SET_CCFG_MODE_CONF_1_XOSC_MAX_START +#define SET_CCFG_MODE_CONF_1_XOSC_MAX_START 0x10 // 1600us +#endif + +//##################################### +// Power settings +//##################################### + +#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA +#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF // Signed delta value +1 to apply to the VDDR_TRIM_SLEEP target (0xF=-1=default=no compensation) +#endif + +#ifndef SET_CCFG_MODE_CONF_DCDC_RECHARGE +#define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x0 // Use the DC/DC during recharge in powerdown +// #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x1 // Do not use the DC/DC during recharge in powerdown +#endif + +#ifndef SET_CCFG_MODE_CONF_DCDC_ACTIVE +#define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x0 // Use the DC/DC during active mode +// #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x1 // Do not use the DC/DC during active mode +#endif + +#if ( CCFG_FORCE_VDDR_HH ) +#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // Special setting to enable forced VDDR HH voltage +#else +#ifndef SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL +// #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x0 // VDDS BOD level is 2.0V +#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // VDDS BOD level is 1.8V (or 1.65V for external regulator mode) +#endif +#endif + +#ifndef SET_CCFG_MODE_CONF_VDDR_CAP +#define SET_CCFG_MODE_CONF_VDDR_CAP 0x3A // Unsigned 8-bit integer representing the min. decoupling capacitance on VDDR in units of 100nF +#endif + +#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC +#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1 // Temperature compensation on VDDR sleep trim disabled (default) +// #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x0 // Temperature compensation on VDDR sleep trim enabled +#endif + +//##################################### +// Clock settings +//##################################### + +#ifndef SET_CCFG_MODE_CONF_SCLK_LF_OPTION +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x0 // LF clock derived from High Frequency XOSC +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x1 // External LF clock +#define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC +#endif + +#ifndef SET_CCFG_MODE_CONF_XOSC_CAP_MOD +// #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x0 // Apply cap-array delta +#define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x1 // Don't apply cap-array delta +#endif + +#ifndef SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA +#define SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF // Signed 8-bit value, directly modifying trimmed XOSC cap-array value +#endif + +#ifndef SET_CCFG_EXT_LF_CLK_DIO +#define SET_CCFG_EXT_LF_CLK_DIO 0x01 // DIO number if using external LF clock +#endif + +#ifndef SET_CCFG_EXT_LF_CLK_RTC_INCREMENT +#define SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 0x800000 // RTC increment representing the external LF clock frequency +#endif + +//##################################### +// Special HF clock source setting +//##################################### +#ifndef SET_CCFG_MODE_CONF_XOSC_FREQ +// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x1 // Use HPOSC as HF source (Unavailable on CC13xx chips) +// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x2 // HF source is a 48 MHz xtal +#define SET_CCFG_MODE_CONF_XOSC_FREQ 0x3 // HF source is a 24 MHz xtal (default) +#endif + +//##################################### +// Bootloader settings +//##################################### + +#ifndef SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE +#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00 // Disable ROM boot loader +// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader +#endif + +#ifndef SET_CCFG_BL_CONFIG_BL_LEVEL +// #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x0 // Active low to open boot loader backdoor +#define SET_CCFG_BL_CONFIG_BL_LEVEL 0x1 // Active high to open boot loader backdoor +#endif + +#ifndef SET_CCFG_BL_CONFIG_BL_PIN_NUMBER +#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0xFF // DIO number for boot loader backdoor +#endif + +#ifndef SET_CCFG_BL_CONFIG_BL_ENABLE +// #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 // Enabled boot loader backdoor +#define SET_CCFG_BL_CONFIG_BL_ENABLE 0xFF // Disabled boot loader backdoor +#endif + +//##################################### +// Debug access settings +//##################################### + +#ifndef SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE +#define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0x00 // Disable unlocking of TI FA option +// #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0xC5 // Enable unlocking of TI FA option with the unlock code +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE +// #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0x00 // Access disabled +#define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE +// #define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00 // Access disabled +#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +//##################################### +// Alternative IEEE 802.15.4 MAC address +//##################################### +#ifndef SET_CCFG_IEEE_MAC_0 +#define SET_CCFG_IEEE_MAC_0 0xFFFFFFFF // Bits [31:0] +#endif + +#ifndef SET_CCFG_IEEE_MAC_1 +#define SET_CCFG_IEEE_MAC_1 0xFFFFFFFF // Bits [63:32] +#endif + +//##################################### +// Alternative BLE address +//##################################### +#ifndef SET_CCFG_IEEE_BLE_0 +#define SET_CCFG_IEEE_BLE_0 0xFFFFFFFF // Bits [31:0] +#endif + +#ifndef SET_CCFG_IEEE_BLE_1 +#define SET_CCFG_IEEE_BLE_1 0xFFFFFFFF // Bits [63:32] +#endif + +//##################################### +// Flash erase settings +//##################################### + +#ifndef SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N +// #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x0 // Any chip erase request detected during boot will be ignored +#define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x1 // Any chip erase request detected during boot will be performed by the boot FW +#endif + +#ifndef SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N +// #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x0 // Disable the boot loader bank erase function +#define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x1 // Enable the boot loader bank erase function +#endif + +//##################################### +// Flash image valid +//##################################### +#ifndef SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID +#define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 0x00000000 // Flash image is valid +// #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID // Flash image is invalid. ROM boot loader is called. +#endif + +//##################################### +// Flash sector write protection +//##################################### +#ifndef SET_CCFG_CCFG_PROT_31_0 +#define SET_CCFG_CCFG_PROT_31_0 0xFFFFFFFF +#endif + +#ifndef SET_CCFG_CCFG_PROT_63_32 +#define SET_CCFG_CCFG_PROT_63_32 0xFFFFFFFF +#endif + +#ifndef SET_CCFG_CCFG_PROT_95_64 +#define SET_CCFG_CCFG_PROT_95_64 0xFFFFFFFF +#endif + +#ifndef SET_CCFG_CCFG_PROT_127_96 +#define SET_CCFG_CCFG_PROT_127_96 0xFFFFFFFF +#endif + +//##################################### +// Select between cache or GPRAM +//##################################### +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0 // Cache is disabled and GPRAM is available at 0x11000000-0x11001FFF +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1 // Cache is enabled and GPRAM is disabled (unavailable) +#endif + +//##################################### +// Select TCXO +//##################################### +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1 // Disable TCXO +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x0 // Enable TXCO +#endif + +//***************************************************************************** +// +// CCFG values that should not be modified. +// +//***************************************************************************** +#define SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058 +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS (CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M >> CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S) + +#if ( CCFG_FORCE_VDDR_HH ) +#define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x0 // Special setting to enable forced VDDR HH voltage +#else +#define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x1 +#endif + +#define SET_CCFG_MODE_CONF_RTC_COMP 0x1 +#define SET_CCFG_MODE_CONF_HF_COMP 0x1 + +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 0xFF +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 0xFF +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 0xFF +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 0xFF + +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 0xFF +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 0xFF +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 0xFF +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 0xFF + +#define SET_CCFG_RTC_OFFSET_RTC_COMP_P0 0xFFFF +#define SET_CCFG_RTC_OFFSET_RTC_COMP_P1 0xFF +#define SET_CCFG_RTC_OFFSET_RTC_COMP_P2 0xFF + +#define SET_CCFG_FREQ_OFFSET_HF_COMP_P0 0xFFFF +#define SET_CCFG_FREQ_OFFSET_HF_COMP_P1 0xFF +#define SET_CCFG_FREQ_OFFSET_HF_COMP_P2 0xFF + +//***************************************************************************** +// +// Concatenate bit fields to words. +// DO NOT EDIT! +// +//***************************************************************************** +#define DEFAULT_CCFG_EXT_LF_CLK ( \ + ((((uint32_t)( SET_CCFG_EXT_LF_CLK_DIO )) << CCFG_EXT_LF_CLK_DIO_S ) | ~CCFG_EXT_LF_CLK_DIO_M ) & \ + ((((uint32_t)( SET_CCFG_EXT_LF_CLK_RTC_INCREMENT )) << CCFG_EXT_LF_CLK_RTC_INCREMENT_S ) | ~CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) ) + +#define DEFAULT_CCFG_MODE_CONF_1 ( \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN )) << CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN )) << CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK )) << CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT )) << CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET )) << CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_XOSC_MAX_START )) << CCFG_MODE_CONF_1_XOSC_MAX_START_S ) | ~CCFG_MODE_CONF_1_XOSC_MAX_START_M ) ) + +#define DEFAULT_CCFG_SIZE_AND_DIS_FLAGS ( \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG )) << CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS )) << CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) ) + +#define DEFAULT_CCFG_MODE_CONF ( \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_RECHARGE )) << CCFG_MODE_CONF_DCDC_RECHARGE_S ) | ~CCFG_MODE_CONF_DCDC_RECHARGE_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_ACTIVE )) << CCFG_MODE_CONF_DCDC_ACTIVE_S ) | ~CCFG_MODE_CONF_DCDC_ACTIVE_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_EXT_LOAD )) << CCFG_MODE_CONF_VDDR_EXT_LOAD_S ) | ~CCFG_MODE_CONF_VDDR_EXT_LOAD_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL )) << CCFG_MODE_CONF_VDDS_BOD_LEVEL_S ) | ~CCFG_MODE_CONF_VDDS_BOD_LEVEL_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_SCLK_LF_OPTION )) << CCFG_MODE_CONF_SCLK_LF_OPTION_S ) | ~CCFG_MODE_CONF_SCLK_LF_OPTION_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_RTC_COMP )) << CCFG_MODE_CONF_RTC_COMP_S ) | ~CCFG_MODE_CONF_RTC_COMP_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_FREQ )) << CCFG_MODE_CONF_XOSC_FREQ_S ) | ~CCFG_MODE_CONF_XOSC_FREQ_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAP_MOD )) << CCFG_MODE_CONF_XOSC_CAP_MOD_S ) | ~CCFG_MODE_CONF_XOSC_CAP_MOD_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_HF_COMP )) << CCFG_MODE_CONF_HF_COMP_S ) | ~CCFG_MODE_CONF_HF_COMP_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA )) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) | ~CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_CAP )) << CCFG_MODE_CONF_VDDR_CAP_S ) | ~CCFG_MODE_CONF_VDDR_CAP_M ) ) + +#define DEFAULT_CCFG_VOLT_LOAD_0 ( \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M ) ) + +#define DEFAULT_CCFG_VOLT_LOAD_1 ( \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M ) ) + +#define DEFAULT_CCFG_RTC_OFFSET ( \ + ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P0 )) << CCFG_RTC_OFFSET_RTC_COMP_P0_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P0_M ) & \ + ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P1 )) << CCFG_RTC_OFFSET_RTC_COMP_P1_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P1_M ) & \ + ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P2 )) << CCFG_RTC_OFFSET_RTC_COMP_P2_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P2_M ) ) + +#define DEFAULT_CCFG_FREQ_OFFSET ( \ + ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P0 )) << CCFG_FREQ_OFFSET_HF_COMP_P0_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P0_M ) & \ + ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P1 )) << CCFG_FREQ_OFFSET_HF_COMP_P1_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P1_M ) & \ + ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P2 )) << CCFG_FREQ_OFFSET_HF_COMP_P2_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P2_M ) ) + +#define DEFAULT_CCFG_IEEE_MAC_0 SET_CCFG_IEEE_MAC_0 +#define DEFAULT_CCFG_IEEE_MAC_1 SET_CCFG_IEEE_MAC_1 +#define DEFAULT_CCFG_IEEE_BLE_0 SET_CCFG_IEEE_BLE_0 +#define DEFAULT_CCFG_IEEE_BLE_1 SET_CCFG_IEEE_BLE_1 + +#define DEFAULT_CCFG_BL_CONFIG ( \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE )) << CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S ) | ~CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_LEVEL )) << CCFG_BL_CONFIG_BL_LEVEL_S ) | ~CCFG_BL_CONFIG_BL_LEVEL_M ) & \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_PIN_NUMBER )) << CCFG_BL_CONFIG_BL_PIN_NUMBER_S ) | ~CCFG_BL_CONFIG_BL_PIN_NUMBER_M ) & \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_ENABLE )) << CCFG_BL_CONFIG_BL_ENABLE_S ) | ~CCFG_BL_CONFIG_BL_ENABLE_M ) ) + +#define DEFAULT_CCFG_ERASE_CONF ( \ + ((((uint32_t)( SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N )) << CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M ) & \ + ((((uint32_t)( SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N )) << CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M ) ) + +#define DEFAULT_CCFG_CCFG_TI_OPTIONS ( \ + ((((uint32_t)( SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE )) << CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S ) | ~CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M ) ) + +#define DEFAULT_CCFG_CCFG_TAP_DAP_0 ( \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M ) ) + +#define DEFAULT_CCFG_CCFG_TAP_DAP_1 ( \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_M ) ) + +#define DEFAULT_CCFG_IMAGE_VALID_CONF SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID + +#define DEFAULT_CCFG_CCFG_PROT_31_0 SET_CCFG_CCFG_PROT_31_0 +#define DEFAULT_CCFG_CCFG_PROT_63_32 SET_CCFG_CCFG_PROT_63_32 +#define DEFAULT_CCFG_CCFG_PROT_95_64 SET_CCFG_CCFG_PROT_95_64 +#define DEFAULT_CCFG_CCFG_PROT_127_96 SET_CCFG_CCFG_PROT_127_96 + +//***************************************************************************** +// +// Customer Configuration Area in Lock Page +// +//***************************************************************************** +#if defined(__IAR_SYSTEMS_ICC__) +__root const ccfg_t __ccfg @ ".ccfg" = +#elif defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(__ccfg, ".ccfg") +#pragma RETAIN(__ccfg) +const ccfg_t __ccfg = +#else +const ccfg_t __ccfg __attribute__((section(".ccfg"))) __attribute__((used)) = +#endif +{ // Mapped to address + DEFAULT_CCFG_EXT_LF_CLK , // 0x50003FA8 (0x50003xxx maps to last + DEFAULT_CCFG_MODE_CONF_1 , // 0x50003FAC sector in FLASH. + DEFAULT_CCFG_SIZE_AND_DIS_FLAGS , // 0x50003FB0 Independent of FLASH size) + DEFAULT_CCFG_MODE_CONF , // 0x50003FB4 + DEFAULT_CCFG_VOLT_LOAD_0 , // 0x50003FB8 + DEFAULT_CCFG_VOLT_LOAD_1 , // 0x50003FBC + DEFAULT_CCFG_RTC_OFFSET , // 0x50003FC0 + DEFAULT_CCFG_FREQ_OFFSET , // 0x50003FC4 + DEFAULT_CCFG_IEEE_MAC_0 , // 0x50003FC8 + DEFAULT_CCFG_IEEE_MAC_1 , // 0x50003FCC + DEFAULT_CCFG_IEEE_BLE_0 , // 0x50003FD0 + DEFAULT_CCFG_IEEE_BLE_1 , // 0x50003FD4 + DEFAULT_CCFG_BL_CONFIG , // 0x50003FD8 + DEFAULT_CCFG_ERASE_CONF , // 0x50003FDC + DEFAULT_CCFG_CCFG_TI_OPTIONS , // 0x50003FE0 + DEFAULT_CCFG_CCFG_TAP_DAP_0 , // 0x50003FE4 + DEFAULT_CCFG_CCFG_TAP_DAP_1 , // 0x50003FE8 + DEFAULT_CCFG_IMAGE_VALID_CONF , // 0x50003FEC + DEFAULT_CCFG_CCFG_PROT_31_0 , // 0x50003FF0 + DEFAULT_CCFG_CCFG_PROT_63_32 , // 0x50003FF4 + DEFAULT_CCFG_CCFG_PROT_95_64 , // 0x50003FF8 + DEFAULT_CCFG_CCFG_PROT_127_96 , // 0x50003FFC +}; + +#endif // __CCFC_C__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi.c new file mode 100644 index 0000000..ddab25f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi.c @@ -0,0 +1,43 @@ +/****************************************************************************** +* Filename: adi.c +* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) +* Revision: 47706 +* +* Description: Driver for the ADI interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aux_smph.h" +#include "adi.h" +#include "cpu.h" diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h new file mode 100644 index 0000000..afbd663 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h @@ -0,0 +1,791 @@ +/****************************************************************************** +* Filename: adi.h +* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) +* Revision: 47706 +* +* Description: Defines and prototypes for the ADI master interface. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup analog_group +//! @{ +//! \addtogroup adi_api +//! @{ +// +//***************************************************************************** + +#ifndef __ADI_H__ +#define __ADI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_uart.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_adi.h" +#include "debug.h" +#include "ddi.h" + +//***************************************************************************** +// +// Number of registers in the ADI slave +// +//***************************************************************************** +#define ADI_SLAVE_REGS 16 + + +//***************************************************************************** +// +// Defines that is used to control the ADI slave and master +// +//***************************************************************************** +#define ADI_PROTECT 0x00000080 +#define ADI_ACK 0x00000001 +#define ADI_SYNC 0x00000000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! \brief Checks an ADI base address. +//! +//! This function determines if an ADI port base address is valid. +//! +//! \param ui32Base is the base address of the ADI port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise +// +//***************************************************************************** +static bool +ADIBaseValid(uint32_t ui32Base) +{ + return(ui32Base == ADI2_BASE || ui32Base == ADI3_BASE || + ui32Base == AUX_ADI4_BASE); +} +#endif + + + + + +//***************************************************************************** +// +//! \brief Write an 8 bit value to a register in an ADI slave. +//! +//! This function will write a value to a single register in the analog domain. +//! The access to the registers in the analog domain is either 8, 16, or 32 bit +//! aligned. You can only do 16 bit access on registers 0-1 / 2-3, etc. Similarly +//! 32 bit accesses are always performed on register 0-3 / 4-7, etc. Addresses +//! for the registers and values being written to the registers will be +//! truncated according to this access scheme. +//! +//! \note This operation is write only for the specified register. No +//! previous value of the register will be kept (i.e. this is NOT +//! read-modify-write on the register). +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the register to write. +//! \param ui8Val is the 8 bit value to write to the register. +//! +//! \return None +//! +//! \sa ADI16RegWrite(), ADI32RegWrite() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Write the value to the register. + HWREGB(ui32Base + ui32Reg) = ui8Val; +} + +//***************************************************************************** +// +//! \brief Write a 16 bit value to 2 registers in the ADI slave. +//! +//! This function will write a value to 2 consecutive registers in the analog +//! domain. The access to the registers in the analog domain is either 8, 16 +//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3, +//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7, +//! etc. Addresses for the registers and values being written +//! to the registers will be truncated according to this access scheme. +//! +//! \note The byte addressing bit will be ignored, to ensure 16 bit access +//! to the ADI slave. +//! +//! \note This operation is write only for the specified register. No +//! previous value of the register will be kept (i.e. this is NOT +//! read-modify-write on the register). +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the register to write. +//! \param ui16Val is the 16 bit value to write to the register. +//! +//! \return None +//! +//! \sa ADI8RegWrite(), ADI32RegWrite() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16RegWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint16_t ui16Val) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Write the value to the register. + HWREGH(ui32Base + (ui32Reg & 0xFE)) = ui16Val; +} + +//***************************************************************************** +// +//! \brief Write a 32 bit value to 4 registers in the ADI slave. +//! +//! This function will write a value to 4 consecutive registers in the analog +//! domain. The access to the registers in the analog domain is either 8, 16 +//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3, +//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7, +//! etc. Addresses for the registers and values being written +//! to the registers will be truncated according to this access scheme. +//! +//! \note The byte and half word addressing bits will be ignored, to ensure +//! 32 bit access to the ADI slave. +//! +//! \note This operation is write only for the specified register. No +//! previous value of the register will be kept (i.e. this is NOT +//! read-modify-write on the register). +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the register to write. +//! \param ui32Val is the 32 bit value to write to the register. +//! +//! \return None +//! +//! \sa ADI8RegWrite(), ADI16RegWrite() +// +//***************************************************************************** +__STATIC_INLINE void +ADI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Write the value to the register. + HWREG(ui32Base + (ui32Reg & 0xFC)) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Read the value of an 8 bit register in the ADI slave. +//! +//! This function will read an 8 bit register in the analog domain and return +//! the value as the lower 8 bits of an \c uint32_t. The access to the +//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can +//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses +//! are always performed on register 0-3 / 4-7, etc. Addresses for the +//! registers and values being written to the registers will be truncated +//! according to this access scheme. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the 8 bit register to read. +//! +//! \return Returns the 8 bit value of the analog register in the least +//! significant byte of the \c uint32_t. +//! +//! \sa ADI16RegRead(), ADI32RegRead() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ADI8RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Read the register and return the value. + return(HWREGB(ui32Base + ui32Reg)); +} + +//***************************************************************************** +// +//! \brief Read the value in a 16 bit register. +//! +//! This function will read 2 x 8 bit registers in the analog domain and return +//! the value as the lower 16 bits of an \c uint32_t. The access to the +//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can +//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses +//! are always performed on register 0-3 / 4-7, etc. Addresses for the +//! registers and values being written to the registers will be truncated +//! according to this access scheme. +//! +//! \note The byte addressing bit will be ignored, to ensure 16 bit access +//! to the ADI slave. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the 16 bit register to read. +//! +//! \return Returns the 16 bit value of the 2 analog register in the 2 least +//! significant bytes of the \c uint32_t. +//! +//! \sa ADI8RegRead(), ADI32RegRead() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ADI16RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Read the registers and return the value. + return(HWREGH(ui32Base + (ui32Reg & 0xFE))); +} + +//***************************************************************************** +// +//! \brief Read the value in a 32 bit register. +//! +//! This function will read 4 x 8 bit registers in the analog domain and return +//! the value as an \c uint32_t. The access to the registers in the analog +//! domain is either 8, 16 or 32 bit aligned. You can only do 16 bit access on +//! registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always performed on +//! register 0-3 / 4-7, etc. Addresses for the registers and values being +//! written to the registers will be truncated according to this access scheme. +//! +//! \note The byte and half word addressing bits will be ignored, to ensure +//! 32 bit access to the ADI slave. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the 32 bit register to read. +//! +//! \return Returns the 32 bit value of the 4 analog registers. +//! +//! \sa ADI8RegRead(), ADI16RegRead() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ADI32RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Read the registers and return the value. + return(HWREG(ui32Base + (ui32Reg & 0xFC))); +} + +//***************************************************************************** +// +//! \brief Set specific bits in a single 8 bit ADI register. +//! +//! This function will set bits in a single register in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in a specific 8 bit register in the +//! ADI slave. Only bits in the selected register are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui8Val is the 8 bit one-hot encoded value specifying which +//! bits to set in the register. +//! +//! \return None +//! +//! \sa ADI16BitsSet(), ADI32BitsSet() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_SET; + + // Set the selected bits. + HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val; +} + +//***************************************************************************** +// +//! \brief Set specific bits in 2 x 8 bit ADI slave registers. +//! +//! This function will set bits in 2 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in 2 consecutive 8 bit registers in the +//! ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui16Val is the 16 bit one-hot encoded value specifying which +//! bits to set in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsSet(), ADI32BitsSet() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_SET; + + // Set the selected bits. + HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val; +} + +//***************************************************************************** +// +//! \brief Set specific bits in 4 x 8 bit ADI slave registers. +//! +//! This function will set bits in 4 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in 4 consecutive 8 bit registers in the +//! ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to set in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsSet(), ADI16BitsSet() +// +//***************************************************************************** +__STATIC_INLINE void +ADI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_SET; + + // Set the selected bits. + HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Clear specific bits in an 8 bit ADI register. +//! +//! This function will clear bits in a register in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to clear bits in a specific 8 bit register in +//! the ADI slave. Only bits in the selected register are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui8Val is the 8 bit one-hot encoded value specifying which +//! bits to clear in the register. +//! +//! \return None +//! +//! \sa ADI16BitsClear(), ADI32BitsClear() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_CLR; + + // Set the selected bits. + HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val; +} + +//***************************************************************************** +// +//! \brief Clear specific bits in two 8 bit ADI register. +//! +//! This function will clear bits in 2 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to clear bits in 2 consecutive 8 bit registers in +//! the ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui16Val is the 16 bit one-hot encoded value specifying which +//! bits to clear in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsClear(), ADI32BitsClear() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_CLR; + + // Set the selected bits. + HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val; +} + +//***************************************************************************** +// +//! \brief Clear specific bits in four 8 bit ADI register. +//! +//! This function will clear bits in 4 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to clear bits in 4 consecutive 8 bit registers in +//! the ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to clear in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsClear(), ADI16BitsClear() +// +//***************************************************************************** +__STATIC_INLINE void +ADI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_CLR; + + // Set the selected bits. + HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Set a value on any 4 bits inside an 8 bit register in the ADI slave. +//! +//! This function allows halfbyte (4 bit) access to the ADI slave registers. +//! The parameter \c bWriteHigh determines whether to write to the lower +//! or higher part of the 8 bit register. +//! +//! Use this function to write any value in the range 0-3 bits aligned on a +//! half byte boundary. Fx. for writing the value 0b101 to bits 1 to 3 the +//! \c ui8Val = 0xA and the \c ui8Mask = 0xE. Bit 0 will not be affected by +//! the operation, as the corresponding bit is not set in the \c ui8Mask. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the ADI port. +//! \param ui32Reg is the Least Significant Register in the ADI slave that +//! will be affected by the write operation. +//! \param bWriteHigh defines which part of the register to write in. +//! - \c true: Write upper half byte of register. +//! - \c false: Write lower half byte of register. +//! \param ui8Mask is the mask defining which of the 4 bits that should be +//! overwritten. The mask must be defined in the lower half of the 8 bits of +//! the parameter. +//! \param ui8Val is the value to write. The value must be defined in the lower +//! half of the 8 bits of the parameter. +//! +//! \return None +//! +//! \sa ADI8SetValBit(), ADI16SetValBit +// +//***************************************************************************** +__STATIC_INLINE void +ADI4SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh, + uint8_t ui8Mask, uint8_t ui8Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + ASSERT(!(ui8Val & 0xF0)); + ASSERT(!(ui8Mask & 0xF0)); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_MASK4B + (ui32Reg << 1) + (bWriteHigh ? 1 : 0); + + // Set the selected bits. + HWREGB(ui32Base + ui32RegOffset) = (ui8Mask << 4) | ui8Val; +} + +//***************************************************************************** +// +//! \brief Set a value on any bits inside an 8 bit register in the ADI slave. +//! +//! This function allows byte (8 bit) access to the ADI slave registers. +//! +//! Use this function to write any value in the range 0-7 bits aligned on a +//! byte boundary. Fx. for writing the value 0b101 to bits 1 and 3 the +//! \c ui16Val = 0x0A and the \c ui16Mask = 0x0E. Bits 0 and 5-7 will not be affected +//! by the operation, as the corresponding bits are not set in the +//! \c ui16Mask. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the ADI port. +//! \param ui32Reg is the Least Significant Register in the ADI slave that +//! will be affected by the write operation. +//! \param ui16Mask is the mask defining which of the 8 bit that should be +//! overwritten. The mask must be defined in the lower half of the 16 bits. +//! \param ui16Val is the value to write. The value must be defined in the lower +//! half of the 16 bits. +//! +//! \return None +//! +//! \sa ADI4SetValBit(), ADI16SetValBit() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Mask, + uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + ASSERT(!(ui16Val & 0xFF00)); + ASSERT(!(ui16Mask & 0xFF00)); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_MASK8B + (ui32Reg << 1); + + // Set the selected bits. + HWREGH(ui32Base + ui32RegOffset) = (ui16Mask << 8) | ui16Val; +} + +//***************************************************************************** +// +//! \brief Set a value on any bits inside an 2 x 8 bit register aligned on a +//! half-word (byte) boundary in the ADI slave. +//! +//! This function allows 2 byte (16 bit) access to the ADI slave registers. +//! +//! Use this function to write any value in the range 0-15 bits aligned on a +//! half-word (byte) boundary. Fx. for writing the value 0b101 to bits 1 and 3 the +//! \c ui32Val = 0x000A and the \c ui32Mask = 0x000E. Bits 0 and 5-15 will not +//! be affected by the operation, as the corresponding bits are not set +//! in the \c ui32Mask. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the ADI port. +//! \param ui32Reg is the Least Significant Register in the ADI slave that +//! will be affected by the write operation. +//! \param ui32Mask is the mask defining which of the 16 bit that should be +//! overwritten. The mask must be defined in the lower half of the 32 bits. +//! \param ui32Val is the value to write. The value must be defined in the lower +//! half of the 32 bits. +//! +//! \return None +//! +//! \sa ADI4SetValBit(), ADI8SetValBit() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, + uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + ASSERT(!(ui32Val & 0xFFFF0000)); + ASSERT(!(ui32Mask & 0xFFFF0000)); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_MASK16B + ((ui32Reg << 1) & 0xFC); + + // Set the selected bits. + HWREG(ui32Base + ui32RegOffset) = (ui32Mask << 16) | ui32Val; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ADI_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h new file mode 100644 index 0000000..5543464 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h @@ -0,0 +1,68 @@ +/****************************************************************************** +* Filename: adi_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup adi_api +//! @{ +//! \section sec_adi Introduction +//! \n +//! +//! \section sec_adi_api API +//! +//! The API functions can be grouped like this: +//! +//! Write: +//! - Direct (all bits): +//! - \ref ADI8RegWrite() +//! - \ref ADI16RegWrite() +//! - \ref ADI32RegWrite() +//! - Set individual bits: +//! - \ref ADI8BitsSet() +//! - \ref ADI16BitsSet() +//! - \ref ADI32BitsSet() +//! - Clear individual bits: +//! - \ref ADI8BitsClear() +//! - \ref ADI16BitsClear() +//! - \ref ADI32BitsClear() +//! - Masked: +//! - \ref ADI4SetValBit() +//! - \ref ADI8SetValBit() +//! - \ref ADI16SetValBit() +//! +//! Read: +//! - \ref ADI8RegRead() +//! - \ref ADI16RegRead() +//! - \ref ADI32RegRead() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes.c new file mode 100644 index 0000000..4b2c0b5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes.c @@ -0,0 +1,372 @@ + +/****************************************************************************** +* Filename: crypto.c +* Revised: 2019-01-25 13:11:50 +0100 (Fri, 25 Jan 2019) +* Revision: 54285 +* +* Description: Driver for the aes functions of the crypto module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aes.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AESStartDMAOperation + #define AESStartDMAOperation NOROM_AESStartDMAOperation + #undef AESSetInitializationVector + #define AESSetInitializationVector NOROM_AESSetInitializationVector + #undef AESWriteCCMInitializationVector + #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector + #undef AESReadTag + #define AESReadTag NOROM_AESReadTag + #undef AESVerifyTag + #define AESVerifyTag NOROM_AESVerifyTag + #undef AESWriteToKeyStore + #define AESWriteToKeyStore NOROM_AESWriteToKeyStore + #undef AESReadFromKeyStore + #define AESReadFromKeyStore NOROM_AESReadFromKeyStore + #undef AESWaitForIRQFlags + #define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags + #undef AESConfigureCCMCtrl + #define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl +#endif + + + +//***************************************************************************** +// +// Load the initialization vector. +// +//***************************************************************************** +void AESSetInitializationVector(const uint32_t *initializationVector) +{ + // Write initialization vector to the aes registers + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = initializationVector[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = initializationVector[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = initializationVector[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = initializationVector[3]; +} + +//***************************************************************************** +// +// Start a crypto DMA operation. +// +//***************************************************************************** +void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) +{ + if (channel0Length && channel0Addr) { + // We actually want to perform an operation. Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; // This might need AES_IRQEN_DMA_IN_DONE as well + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; + } + + if (channel1Length && channel1Addr) { + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; + } +} + +//***************************************************************************** +// +// Poll the IRQ status register and return. +// +//***************************************************************************** +uint32_t AESWaitForIRQFlags(uint32_t irqFlags) +{ + uint32_t irqTrigger = 0; + // Wait for the DMA operation to complete. Add a delay to make sure we are + // not flooding the bus with requests too much. + do { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | + CRYPTO_IRQSTAT_RESULT_AVAIL_M | + CRYPTO_IRQSTAT_DMA_BUS_ERR_M | + CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M))); + + // Save the IRQ trigger source + irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags; + + // Clear IRQ flags + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqTrigger; + + return irqTrigger; +} + +//***************************************************************************** +// +// Transfer a key from CM3 memory to a key store location. +// +//***************************************************************************** +uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea) +{ + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + ASSERT((aesKeyLength == AES_128_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_192_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_256_KEY_LENGTH_BYTES)); + + uint32_t keySize = 0; + + switch (aesKeyLength) { + case AES_128_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_128_BIT; + break; + case AES_192_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_192_BIT; + break; + case AES_256_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_256_BIT; + break; + } + + // Clear any previously written key at the keyLocation + AESInvalidateKey(keyStoreArea); + + // Disable the external interrupt to stop the interrupt form propagating + // from the module to the System CPU. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE_M | CRYPTO_IRQEN_RESULT_AVAIL_M; + + // Configure master control module. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_KEY_STORE; + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQCLR_RESULT_AVAIL); + + // Configure the size of keys contained within the key store + // Do not write to the register if the correct key size is already set. + // Writing to this register causes all current keys to be invalidated. + uint32_t keyStoreKeySize = HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE); + if (keySize != keyStoreKeySize) { + HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = keySize; + } + + // Enable key to write (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = 1 << keyStoreArea; + + // Total key length in bytes (16 for 1 x 128-bit key and 32 for 1 x 256-bit key). + AESStartDMAOperation(aesKey, aesKeyLength, 0, 0); + + // Wait for the DMA operation to complete. + uint32_t irqTrigger = AESWaitForIRQFlags(CRYPTO_IRQCLR_RESULT_AVAIL | CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQSTAT_DMA_BUS_ERR | CRYPTO_IRQSTAT_KEY_ST_WR_ERR); + + // Re-enable interrupts globally. + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // If we had a bus error or the key is not in the CRYPTO_O_KEYWRITTENAREA, return an error. + if ((irqTrigger & (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M)) || !(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + // There was an error in writing to the keyStore. + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +//***************************************************************************** +// +// Transfer a key from the keyStoreArea to the internal buffer of the module. +// +//***************************************************************************** +uint32_t AESReadFromKeyStore(uint32_t keyStoreArea) +{ + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + // Check if there is a valid key in the specified keyStoreArea + if (!(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + return AES_KEYSTORE_AREA_INVALID; + } + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = keyStoreArea; + + // Wait until key is loaded to the AES module. + // We cannot simply poll the IRQ status as only an error is communicated through + // the IRQ status and not the completion of the transfer. + do { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY_M)); + + // Check for keyStore read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M)) { + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +//***************************************************************************** +// +// Read the tag after a completed CCM, GCM, or CBC-MAC operation. +// +//***************************************************************************** +uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength) +{ + // The intermediate array is used instead of a caller-provided one + // to enable a simple API with no unintuitive alignment or size requirements. + // This is a trade-off of stack-depth vs ease-of-use that came out on the + // ease-of-use side. + uint32_t computedTag[AES_BLOCK_SIZE / sizeof(uint32_t)]; + + // Wait until the computed tag is ready. + while (!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M)); + + // Read computed tag out from the HW registers + // Need to read out all 128 bits in four reads to correctly clear CRYPTO_AESCTL_SAVED_CONTEXT_RDY flag + computedTag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); + computedTag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); + computedTag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); + computedTag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); + + memcpy(tag, computedTag, tagLength); + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Verify the provided tag against the computed tag after a completed CCM or +// GCM operation. +// +//***************************************************************************** +uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength) +{ + uint32_t resultStatus; + // The intermediate array is allocated on the stack to ensure users do not + // point the tag they provide and the one computed at the same location. + // That would cause memcmp to compare an array against itself. We could add + // a check that verifies that the arrays are not the same. If we did that and + // modified AESReadTag to just copy all 128 bits into a provided array, + // we could save 16 bytes of stack space while making the API much more + // complicated. + uint8_t computedTag[AES_BLOCK_SIZE]; + + resultStatus = AESReadTag(computedTag, tagLength); + + if (resultStatus != AES_SUCCESS) { + return resultStatus; + } + + resultStatus = memcmp(computedTag, tag, tagLength); + + if (resultStatus != 0) { + return AES_TAG_VERIFICATION_FAILED; + } + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Configure the AES module for CCM mode +// +//***************************************************************************** +void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt) +{ + uint32_t ctrlVal = 0; + + ctrlVal = ((15 - nonceLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if ( macLength >= 2 ) { + ctrlVal |= ((( macLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); + } + ctrlVal |= CRYPTO_AESCTL_CCM | + CRYPTO_AESCTL_CTR | + CRYPTO_AESCTL_SAVE_CONTEXT | + CRYPTO_AESCTL_CTR_WIDTH_128_BIT; + ctrlVal |= encrypt ? CRYPTO_AESCTL_DIR : 0; + + AESSetCtrl(ctrlVal); +} + +//***************************************************************************** +// +// Configure an IV for CCM mode of operation +// +//***************************************************************************** +void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength) +{ + union { + uint32_t word[4]; + uint8_t byte[16]; + } initializationVector = {{0}}; + + initializationVector.byte[0] = 15 - nonceLength - 1; + + memcpy(&(initializationVector.byte[1]), nonce, nonceLength); + + AESSetInitializationVector(initializationVector.word); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h new file mode 100644 index 0000000..eb199a4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h @@ -0,0 +1,843 @@ +/****************************************************************************** +* Filename: aes.h +* Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019) +* Revision: 54287 +* +* Description: AES header file. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup aes_api +//! @{ +// +//***************************************************************************** + +#ifndef __AES_H__ +#define __AES_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_crypto.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AESStartDMAOperation NOROM_AESStartDMAOperation + #define AESSetInitializationVector NOROM_AESSetInitializationVector + #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector + #define AESReadTag NOROM_AESReadTag + #define AESVerifyTag NOROM_AESVerifyTag + #define AESWriteToKeyStore NOROM_AESWriteToKeyStore + #define AESReadFromKeyStore NOROM_AESReadFromKeyStore + #define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags + #define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl +#endif + + +//***************************************************************************** +// +// Values that can be passed to AESIntEnable, AESIntDisable, and AESIntClear +// as the intFlags parameter, and returned from AESIntStatus. +// Only AES_DMA_IN_DONE and AES_RESULT_RDY are routed to the NVIC. Check each +// function to see if it supports other interrupt status flags. +// +//***************************************************************************** +#define AES_DMA_IN_DONE CRYPTO_IRQEN_DMA_IN_DONE_M +#define AES_RESULT_RDY CRYPTO_IRQEN_RESULT_AVAIL_M +#define AES_DMA_BUS_ERR CRYPTO_IRQCLR_DMA_BUS_ERR_M +#define AES_KEY_ST_WR_ERR CRYPTO_IRQCLR_KEY_ST_WR_ERR_M +#define AES_KEY_ST_RD_ERR CRYPTO_IRQCLR_KEY_ST_RD_ERR_M + + +//***************************************************************************** +// +// General constants +// +//***************************************************************************** + +// AES module return codes +#define AES_SUCCESS 0 +#define AES_KEYSTORE_ERROR 1 +#define AES_KEYSTORE_AREA_INVALID 2 +#define AES_DMA_BUSY 3 +#define AES_DMA_ERROR 4 +#define AES_TAG_NOT_READY 5 +#define AES_TAG_VERIFICATION_FAILED 6 + +// Key store module defines +#define AES_IV_LENGTH_BYTES 16 +#define AES_TAG_LENGTH_BYTES 16 +#define AES_128_KEY_LENGTH_BYTES (128 / 8) +#define AES_192_KEY_LENGTH_BYTES (192 / 8) +#define AES_256_KEY_LENGTH_BYTES (256 / 8) + +#define AES_BLOCK_SIZE 16 + +// DMA status codes +#define AES_DMA_CHANNEL0_ACTIVE CRYPTO_DMASTAT_CH0_ACT_M +#define AES_DMA_CHANNEL1_ACTIVE CRYPTO_DMASTAT_CH1_ACT_M +#define AES_DMA_PORT_ERROR CRYPTO_DMASTAT_PORT_ERR_M + +// Crypto module operation types +#define AES_ALGSEL_AES CRYPTO_ALGSEL_AES_M +#define AES_ALGSEL_KEY_STORE CRYPTO_ALGSEL_KEY_STORE_M +#define AES_ALGSEL_TAG CRYPTO_ALGSEL_TAG_M + + +//***************************************************************************** +// +// For 128-bit keys, all 8 key area locations from 0 to 7 are valid. +// A 256-bit key requires two consecutive Key Area locations. The base key area +// may be odd. Do not attempt to write a 256-bit key to AES_KEY_AREA_7. +// +//***************************************************************************** +#define AES_KEY_AREA_0 0 +#define AES_KEY_AREA_1 1 +#define AES_KEY_AREA_2 2 +#define AES_KEY_AREA_3 3 +#define AES_KEY_AREA_4 4 +#define AES_KEY_AREA_5 5 +#define AES_KEY_AREA_6 6 +#define AES_KEY_AREA_7 7 + +//***************************************************************************** +// +// Defines for the AES-CTR mode counter width +// +//***************************************************************************** +#define AES_CTR_WIDTH_32 0x0 +#define AES_CTR_WIDTH_64 0x1 +#define AES_CTR_WIDTH_96 0x2 +#define AES_CTR_WIDTH_128 0x3 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Start a crypto DMA operation +//! +//! Enable the crypto DMA channels, configure the channel addresses, +//! and set the length of the data transfer. +//! Setting the length of the data transfer automatically starts the +//! transfer. It is also used by the hardware module as a signal to +//! begin the encryption, decryption, or MAC operation. +//! +//! \param [in] channel0Addr A pointer to the address channel 0 shall use. +//! +//! \param [in] channel0Length Length of the data in bytes to be read from or +//! written to at channel0Addr. Set to 0 to not set up +//! this channel. Permitted ranges are mode dependent +//! and displayed below. +//! - ECB: [16] +//! - CBC: [1, sizeof(RAM)] +//! - CBC-MAC: [1, sizeof(RAM)] +//! - CCM: [1, sizeof(RAM)] +//! +//! \param [out] channel1Addr A pointer to the address channel 1 shall use. +//! +//! \param [in] channel1Length Length of the data in bytes to be read from or +//! written to at channel1Addr. Set to 0 to not set up +//! this channel.Permitted ranges are mode dependent +//! and displayed below. +//! - ECB: [16] +//! - CBC: [1, sizeof(RAM)] +//! - CBC-MAC: [1, sizeof(RAM)] +//! - CCM: [1, sizeof(RAM)] +//! +//! \return None +// +//***************************************************************************** +extern void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length); + +//***************************************************************************** +// +//! \brief Write the initialization vector (IV) to the crypto module. +//! +//! Depending on the mode of operation, the tag must be constructed +//! differently: +//! - CBC: No special care must be taken. Any 128-bit IV +//! (initialization vector) will suffice. +//! - CBC-MAC: IV's must be all 0's. +//! - CCM: Only 12 and 13 byte IV's are permitted. See code +//! below for formatting. +//! \code +//! uint8_t initVectorLength = 12; // Could also be 13 +//! +//! union { +//! uint32_t word[4]; +//! uint8_t byte[16]; +//! } initVector; +//! +//! uint8_t initVectorUnformatted[initVectorLength]; +//! +//! // This is the same field length value that is written to the ctrl register +//! initVector.byte[0] = L - 1; +//! +//! memcpy(&initVector.byte[1], initVectorUnformatted, initVectorLength); +//! +//! // Fill the remaining bytes with zeros +//! for (initVectorLength++; initVectorLength < sizeof(initVector.byte); initVectorLength++) { +//! initVector.byte[initVectorLength] = 0; +//! } +//! \endcode +//! +//! \param [in] initializationVector Pointer to an array with four 32-bit elements +//! to be used as initialization vector. +//! Elements of array must be word aligned in memory. +//! +//! \return None +// +//***************************************************************************** +extern void AESSetInitializationVector(const uint32_t *initializationVector); + +//***************************************************************************** +// +//! \brief Generate and load the initialization vector for a CCM operation. +//! +//! +//! \param [in] nonce Pointer to a nonce of length \c nonceLength. +//! +//! \param [in] nonceLength Number of bytes to copy from \c nonce when creating +//! the CCM IV. The L-value is also derived from it. +//! +//! \return None +// +//***************************************************************************** +extern void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength); + +//***************************************************************************** +// +//! \brief Read the tag out from the crypto module. +//! +//! This function copies the \c tagLength bytes from the tag calculated by the +//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag. +//! +//! \param [out] tag Pointer to an array of \c tagLength bytes. +//! +//! \param [in] tagLength Number of bytes to copy to \c tag. +//! +//! \return Returns a status code depending on the result of the transfer. +//! - \ref AES_TAG_NOT_READY if the tag is not ready yet +//! - \ref AES_SUCCESS otherwise +// +//***************************************************************************** +extern uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength); + +//***************************************************************************** +// +//! \brief Verifies the provided \c tag against calculated one +//! +//! This function compares the provided tag against the tag calculated by the +//! crypto module during the last CCM, GCM, or CBC-MAC +//! +//! This function copies the \c tagLength bytes from the tag calculated by the +//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag. +//! +//! \param [in] tag Pointer to an array of \c tagLength bytes. +//! +//! \param [in] tagLength Number of bytes to compare. +//! +//! \return Returns a status code depending on the result of the transfer. +//! - \ref AES_TAG_VERIFICATION_FAILED if the verification failed +//! - \ref AES_SUCCESS otherwise +// +//***************************************************************************** +extern uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength); + +//***************************************************************************** +// +//! \brief Transfer a key from main memory to a key area within the key store. +//! +//! The crypto DMA transfers the key and function does not return until +//! the operation completes. +//! The keyStore can only contain valid keys of one \c aesKeyLength at +//! any one point in time. The keyStore cannot contain both 128-bit and +//! 256-bit keys simultaneously. When a key of a different \c aesKeyLength +//! from the previous \c aesKeyLength is loaded, all previous keys are +//! invalidated. +//! +//! \param [in] aesKey Pointer to key. Does not need to be word-aligned. +//! +//! \param [in] aesKeyLength The key size in bytes. Currently, 128-bit, 192-bit, +//! and 256-bit keys are supported. +//! - \ref AES_128_KEY_LENGTH_BYTES +//! - \ref AES_192_KEY_LENGTH_BYTES +//! - \ref AES_256_KEY_LENGTH_BYTES +//! +//! \param [in] keyStoreArea The key store area to transfer the key to. +//! When using 128-bit keys, only the specified key store +//! area will be occupied. +//! When using 256-bit or 192-bit keys, two consecutive key areas +//! are used to store the key. +//! - \ref AES_KEY_AREA_0 +//! - \ref AES_KEY_AREA_1 +//! - \ref AES_KEY_AREA_2 +//! - \ref AES_KEY_AREA_3 +//! - \ref AES_KEY_AREA_4 +//! - \ref AES_KEY_AREA_5 +//! - \ref AES_KEY_AREA_6 +//! - \ref AES_KEY_AREA_7 +//! +//! When using 256-bit or 192-bit keys, the 8 \c keyStoreArea's are +//! split into four sets of two. Selecting any \c keyStoreArea automatically +//! occupies the second \c keyStoreArea of the tuples below: +//! +//! - (\ref AES_KEY_AREA_0, \ref AES_KEY_AREA_1) +//! - (\ref AES_KEY_AREA_2, \ref AES_KEY_AREA_3) +//! - (\ref AES_KEY_AREA_4, \ref AES_KEY_AREA_5) +//! - (\ref AES_KEY_AREA_6, \ref AES_KEY_AREA_7) +//! +//! For example: if \c keyStoreArea == \ref AES_KEY_AREA_2, +//! both \ref AES_KEY_AREA_2 and \ref AES_KEY_AREA_3 are occupied. +//! If \c keyStoreArea == \ref AES_KEY_AREA_5, both \ref AES_KEY_AREA_4 and \ref AES_KEY_AREA_5 are occupied. +//! +//! \return Returns a status code depending on the result of the transfer. +//! If there was an error in the read process itself, an error is +//! returned. +//! Otherwise, a success code is returned. +//! - \ref AES_KEYSTORE_ERROR +//! - \ref AES_SUCCESS +//! +//! \sa AESReadFromKeyStore +// +//***************************************************************************** +extern uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea); + +//***************************************************************************** +// +//! \brief Transfer a key from key store area to the internal buffers within +//! the hardware module. +//! +//! The function polls until the transfer is complete. +//! +//! \param [in] keyStoreArea The key store area to transfer the key from. When using +//! 256-bit keys, either of the occupied key areas may be +//! specified to load the key. There is no need to specify +//! the length of the key here as the key store keeps track +//! of how long a key associated with any valid key area is +//! and where is starts. +//! - \ref AES_KEY_AREA_0 +//! - \ref AES_KEY_AREA_1 +//! - \ref AES_KEY_AREA_2 +//! - \ref AES_KEY_AREA_3 +//! - \ref AES_KEY_AREA_4 +//! - \ref AES_KEY_AREA_5 +//! - \ref AES_KEY_AREA_6 +//! - \ref AES_KEY_AREA_7 +//! +//! \return Returns a status code depending on the result of the transfer. +//! When specifying a \c keyStoreArea value without a valid key in it an +//! error is returned. +//! If there was an error in the read process itself, an error is +//! returned. +//! Otherwise, a success code is returned. +//! - \ref AES_KEYSTORE_AREA_INVALID +//! - \ref AES_KEYSTORE_ERROR +//! - \ref AES_SUCCESS +//! +//! \sa AESWriteToKeyStore +// +//***************************************************************************** +extern uint32_t AESReadFromKeyStore(uint32_t keyStoreArea); + + +//***************************************************************************** +// +//! \brief Poll the interrupt status register and clear when done. +//! +//! This function polls until one of the bits in the \c irqFlags is +//! asserted. Only \ref AES_DMA_IN_DONE and \ref AES_RESULT_RDY can actually +//! trigger the interrupt line. That means that one of those should +//! always be included in \c irqFlags and will always be returned together +//! with any error codes. +//! +//! \param [in] irqFlags IRQ flags to poll and mask that the status register will be +//! masked with. May consist of any bitwise OR of the flags +//! below that includes at least one of +//! \ref AES_DMA_IN_DONE or \ref AES_RESULT_RDY : +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! - \ref AES_DMA_BUS_ERR +//! - \ref AES_KEY_ST_WR_ERR +//! - \ref AES_KEY_ST_RD_ERR +//! +//! \return Returns the IRQ status register masked with \c irqFlags. May be any +//! bitwise OR of the following masks: +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! - \ref AES_DMA_BUS_ERR +//! - \ref AES_KEY_ST_WR_ERR +//! - \ref AES_KEY_ST_RD_ERR +// +//***************************************************************************** +extern uint32_t AESWaitForIRQFlags(uint32_t irqFlags); + +//***************************************************************************** +// +//! \brief Configure AES engine for CCM operation. +//! +//! \param [in] nonceLength Length of the nonce. Must be <= 14. +//! +//! \param [in] macLength Length of the MAC. Must be <= 16. +//! +//! \param [in] encrypt Whether to set up an encrypt or decrypt operation. +//! - true: encrypt +//! - false: decrypt +//! +//! \return None +// +//***************************************************************************** +extern void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt); + +//***************************************************************************** +// +//! \brief Invalidate a key in the key store +//! +//! \param [in] keyStoreArea is the entry in the key store to invalidate. This +//! permanently deletes the key from the key store. +//! - \ref AES_KEY_AREA_0 +//! - \ref AES_KEY_AREA_1 +//! - \ref AES_KEY_AREA_2 +//! - \ref AES_KEY_AREA_3 +//! - \ref AES_KEY_AREA_4 +//! - \ref AES_KEY_AREA_5 +//! - \ref AES_KEY_AREA_6 +//! - \ref AES_KEY_AREA_7 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESInvalidateKey(uint32_t keyStoreArea) +{ + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + // Clear any previously written key at the key location + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << keyStoreArea); +} + +//***************************************************************************** +// +//! \brief Select type of operation +//! +//! \param [in] algorithm Flags that specify which type of operation the crypto +//! module shall perform. The flags are mutually exclusive. +//! - 0 : Reset the module +//! - \ref AES_ALGSEL_AES +//! - \ref AES_ALGSEL_TAG +//! - \ref AES_ALGSEL_KEY_STORE +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESSelectAlgorithm(uint32_t algorithm) +{ + ASSERT((algorithm == AES_ALGSEL_AES) || + (algorithm == AES_ALGSEL_AES | AES_ALGSEL_TAG) || + (algorithm == AES_ALGSEL_KEY_STORE)); + + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm; +} + +//***************************************************************************** +// +//! \brief Set up the next crypto module operation. +//! +//! The function uses a bitwise OR of the fields within the CRYPTO_O_AESCTL +//! register. The relevant field names have the format: +//! - CRYPTO_AESCTL_[field name] +//! +//! \param [in] ctrlMask Specifies which register fields shall be set. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESSetCtrl(uint32_t ctrlMask) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ctrlMask; +} + +//***************************************************************************** +// +//! \brief Specify length of the crypto operation. +//! +//! Despite specifying it here, the crypto DMA must still be +//! set up with the correct data length. +//! +//! \param [in] length Data length in bytes. If this +//! value is set to 0, only authentication of the AAD is +//! performed in CCM-mode and AESWriteAuthLength() must be set to +//! >0. +//! Range depends on the mode: +//! - ECB: [16] +//! - CBC: [1, sizeof(RAM)] +//! - CBC-MAC: [1, sizeof(RAM)] +//! - CCM: [0, sizeof(RAM)] +//! +//! \return None +//! +//! \sa AESWriteAuthLength +// +//***************************************************************************** +__STATIC_INLINE void AESSetDataLength(uint32_t length) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = length; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; +} + +//***************************************************************************** +// +//! \brief Specify the length of the additional authentication data (AAD). +//! +//! Despite specifying it here, the crypto DMA must still be set up with +//! the correct AAD length. +//! +//! \param [in] length Specifies how long the AAD is in a CCM operation. In CCM mode, +//! set this to 0 if no AAD is required. If set to 0, +//! AESWriteDataLength() must be set to >0. +//! Range depends on the mode: +//! - ECB: Do not call. +//! - CBC: [0] +//! - CBC-MAC: [0] +//! - CCM: [0, sizeof(RAM)] +//! +//! \return None +//! +//! \sa AESWriteDataLength +// +//***************************************************************************** +__STATIC_INLINE void AESSetAuthLength(uint32_t length) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = length; +} + +//***************************************************************************** +// +//! \brief Reset the accelerator and cancel ongoing operations +//! +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESReset(void) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_SWRESET) = 0x00000001; +} + +//***************************************************************************** +// +//! \brief Enable individual crypto interrupt sources. +//! +//! This function enables the indicated crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESIntEnable(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & AES_DMA_IN_DONE) || + (intFlags & AES_RESULT_RDY)); + + // Using level interrupt. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; + + // Enable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; +} + +//***************************************************************************** +// +//! \brief Disable individual crypto interrupt sources. +//! +//! This function disables the indicated crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESIntDisable(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & AES_DMA_IN_DONE) || + (intFlags & AES_RESULT_RDY)); + + // Disable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; +} + +//***************************************************************************** +// +//! \brief Get the current masked interrupt status. +//! +//! This function returns the masked interrupt status of the crypto module. +//! +//! \return Returns the status of the masked lines when enabled: +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +// +//***************************************************************************** +__STATIC_INLINE uint32_t AESIntStatusMasked(void) +{ + uint32_t mask; + + // Return the masked interrupt status + mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); + return(mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); +} + +//***************************************************************************** +// +//! \brief Get the current raw interrupt status. +//! +//! This function returns the raw interrupt status of the crypto module. +//! It returns both the status of the lines routed to the NVIC as well as the +//! error flags. +//! +//! \return Returns the raw interrupt status: +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! - \ref AES_DMA_BUS_ERR +//! - \ref AES_KEY_ST_WR_ERR +//! - \ref AES_KEY_ST_RD_ERR +// +//***************************************************************************** +__STATIC_INLINE uint32_t AESIntStatusRaw(void) +{ + // Return either the raw interrupt status + return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); +} + +//***************************************************************************** +// +//! \brief Clear crypto interrupt sources. +//! +//! The specified crypto interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in the module until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! +//! \param [in] intFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESIntClear(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & AES_DMA_IN_DONE) || + (intFlags & AES_RESULT_RDY)); + + // Clear the requested interrupt sources, + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = intFlags; +} + +//***************************************************************************** +// +//! \brief Register an interrupt handler for a crypto interrupt. +//! +//! This function does the actual registering of the interrupt handler. This +//! function enables the global interrupt in the interrupt controller; specific +//! crypto interrupts must be enabled via \ref AESIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param handlerFxn is a pointer to the function to be called when the +//! crypto interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void AESIntRegister(void (*handlerFxn)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, handlerFxn); + + // Enable the crypto interrupt. + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregister an interrupt handler for a crypto interrupt. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler called when a crypto interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void AESIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AESStartDMAOperation + #undef AESStartDMAOperation + #define AESStartDMAOperation ROM_AESStartDMAOperation + #endif + #ifdef ROM_AESSetInitializationVector + #undef AESSetInitializationVector + #define AESSetInitializationVector ROM_AESSetInitializationVector + #endif + #ifdef ROM_AESWriteCCMInitializationVector + #undef AESWriteCCMInitializationVector + #define AESWriteCCMInitializationVector ROM_AESWriteCCMInitializationVector + #endif + #ifdef ROM_AESReadTag + #undef AESReadTag + #define AESReadTag ROM_AESReadTag + #endif + #ifdef ROM_AESVerifyTag + #undef AESVerifyTag + #define AESVerifyTag ROM_AESVerifyTag + #endif + #ifdef ROM_AESWriteToKeyStore + #undef AESWriteToKeyStore + #define AESWriteToKeyStore ROM_AESWriteToKeyStore + #endif + #ifdef ROM_AESReadFromKeyStore + #undef AESReadFromKeyStore + #define AESReadFromKeyStore ROM_AESReadFromKeyStore + #endif + #ifdef ROM_AESWaitForIRQFlags + #undef AESWaitForIRQFlags + #define AESWaitForIRQFlags ROM_AESWaitForIRQFlags + #endif + #ifdef ROM_AESConfigureCCMCtrl + #undef AESConfigureCCMCtrl + #define AESConfigureCCMCtrl ROM_AESConfigureCCMCtrl + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AES_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes_doc.h new file mode 100644 index 0000000..5d94afa --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes_doc.h @@ -0,0 +1,66 @@ +/****************************************************************************** +* Filename: aes_doc.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aes_api +//! @{ +//! \section sec_aes Introduction +//! +//! The AES (advanced encryption standard) API provides access to the AES and key +//! store functionality of the crypto core. The SHA2 accelerator is also +//! contained within the crypto core. Hence, only one of SHA2 and AES may be +//! used at the same time. +//! This module offers hardware acceleration for several protocols using the +//! AES block cypher. The protocols below are supported by the hardware. The +//! driverlib documentation only explicitly references the most commonly used ones. +//! - ECB +//! - CBC +//! - CCM +//! - CBC-MAC +//! - GCM +//! +//! The key store is a section of crypto memory that is only accessible to the crypto module +//! and may be written to by the application via the crypto DMA. It is not possible to +//! read from the key store to main memory. Thereby, it is not possible to +//! compromise the key should the application be hacked if the original key in main +//! memory was overwritten already. +//! +//! The crypto core does not have retention and all configuration settings and +//! keys in the keystore are lost when going into standby or shutdown. +//! The typical security advantages a key store offers are not available in these +//! low power modes as the key must be saved in regular memory to reload +//! it after going into standby or shutdown. +//! Consequently, the keystore primarily serves as an interface to the AES accelerator. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.c new file mode 100644 index 0000000..e5037dc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.c @@ -0,0 +1,80 @@ +/****************************************************************************** +* Filename: aon_batmon.c +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Driver for the AON Battery and Temperature Monitor +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_batmon.h" +#include "../inc/hw_fcfg1.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONBatMonTemperatureGetDegC + #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC +#endif + +//***************************************************************************** +// +// AONBatMonTemperatureGetDegC() +// Returns sign extended temperature in Deg C (-256 .. +255) +// +//***************************************************************************** +int32_t +AONBatMonTemperatureGetDegC( void ) +{ + int32_t signedTemp ; // Signed extended temperature with 8 fractional bits + int32_t tempCorrection ; // Voltage dependent temp correction with 8 fractional bits + int8_t voltageSlope ; // Signed byte value representing the TEMP slope with battery voltage, in degrees C/V, with 4 fractional bits. + + // Shift left then right to sign extend the BATMON_TEMP field + signedTemp = ((((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_TEMP )) + << ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )) + >> ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )); + + // Typecasting voltageSlope to int8_t prior to assignment in order to make sure sign extension works properly + // Using byte read (HWREGB) in order to make more efficient code since voltageSlope is assigned to bits[7:0] of FCFG1_O_MISC_TRIM + voltageSlope = ((int8_t)HWREGB( FCFG1_BASE + FCFG1_O_MISC_TRIM )); + tempCorrection = (( voltageSlope * (((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT )) - 0x300 )) >> 4 ); + + return ((( signedTemp - tempCorrection ) + 0x80 ) >> 8 ); +} + + +// See aon_batmon.h for implementation of remaining functions diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.h new file mode 100644 index 0000000..ce7d323 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.h @@ -0,0 +1,306 @@ +/****************************************************************************** +* Filename: aon_batmon.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the AON Battery and Temperature +* Monitor +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonbatmon_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_BATMON_H__ +#define __AON_BATMON_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_batmon.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC +#endif + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enable the temperature and battery monitoring. +//! +//! This function will enable the measurements of the temperature and the +//! battery voltage. +//! +//! To speed up the measurement of the levels the measurement can be enabled +//! before configuring the battery and temperature settings. When all of the +//! AON_BATMON registers are configured, the calculation of the voltage and +//! temperature values can be enabled (the measurement will now take +//! effect/propagate to other blocks). +//! +//! It is possible to enable both at the same time, after the AON_BATMON +//! registers are configured, but then the first values will be ready at a +//! later point compared to the scenario above. +//! +//! \note Temperature and battery voltage measurements are not done in +//! parallel. The measurement cycle is controlled by a hardware Finite State +//! Machine. First the temperature and then the battery voltage each taking +//! one cycle to complete. However, if the comparator measuring the battery +//! voltage detects a change on the reference value, a new measurement of the +//! battery voltage only is performed immediately after. This has no impact on +//! the cycle count. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONBatMonEnable(void) +{ + // Enable the measurements. + HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = + AON_BATMON_CTL_CALC_EN | + AON_BATMON_CTL_MEAS_EN; +} + +//***************************************************************************** +// +//! \brief Disable the temperature and battery monitoring. +//! +//! This function will disable the measurements of the temperature and the +//! battery voltage. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONBatMonDisable(void) +{ + // Disable the measurements. + HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = 0; +} + + +//***************************************************************************** +// +//! \brief Get the current temperature measurement as a signed value in Deg Celsius. +//! +//! This function returns an calibrated and rounded value in degree Celsius. +//! The temperature measurements are updated every cycle. +//! +//! \note The temperature drifts slightly depending on the battery voltage. +//! This function compensates for this drift and returns a calibrated temperature. +//! +//! \note Use the function AONBatMonNewTempMeasureReady() to test for a new measurement. +//! +//! \return Returns signed integer part of temperature in Deg C (-256 .. +255) +//! +//! \sa AONBatMonNewTempMeasureReady() +// +//***************************************************************************** +extern int32_t AONBatMonTemperatureGetDegC( void ); + +//***************************************************************************** +// +//! \brief Get the battery monitor measurement. +//! +//! This function will return the current battery monitor measurement. +//! The battery voltage measurements are updated every cycle. +//! +//! \note The returned value is NOT sign-extended! +//! +//! \note Use the function \ref AONBatMonNewBatteryMeasureReady() to test for +//! a change in measurement. +//! +//! \return Returns the current battery monitor value of the battery voltage +//! measurement in a format size <3.8> in units of volt. +//! +//! \sa AONBatMonNewBatteryMeasureReady() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONBatMonBatteryVoltageGet(void) +{ + uint32_t ui32CurrentBattery; + + ui32CurrentBattery = HWREG(AON_BATMON_BASE + AON_BATMON_O_BAT); + + // Return the current battery voltage measurement. + return (ui32CurrentBattery >> AON_BATMON_BAT_FRAC_S); +} + +//***************************************************************************** +// +//! \brief Check if battery monitor measurement has changed. +//! +//! This function checks if a new battery monitor value is available. If the +//! measurement value has \b changed since last clear the function returns \c true. +//! +//! If the measurement has changed the function will automatically clear the +//! status bit. +//! +//! \note It is always possible to read out the current value of the +//! battery level using AONBatMonBatteryVoltageGet() but this function can be +//! used to check if the measurement has changed. +//! +//! \return Returns \c true if the measurement value has changed and \c false +//! otherwise. +//! +//! \sa AONBatMonNewTempMeasureReady(), AONBatMonBatteryVoltageGet() +// +//***************************************************************************** +__STATIC_INLINE bool +AONBatMonNewBatteryMeasureReady(void) +{ + bool bStatus; + + // Check the status bit. + bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) & + AON_BATMON_BATUPD_STAT ? true : false; + + // Clear status bit if set. + if(bStatus) + { + HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) = 1; + } + + // Return status. + return (bStatus); +} + +//***************************************************************************** +// +//! \brief Check if temperature monitor measurement has changed. +//! +//! This function checks if a new temperature value is available. If the +//! measurement value has \b changed since last clear the function returns \c true. +//! +//! If the measurement has changed the function will automatically clear the +//! status bit. +//! +//! \note It is always possible to read out the current value of the +//! temperature using \ref AONBatMonTemperatureGetDegC() +//! but this function can be used to check if the measurement has changed. +//! +//! \return Returns \c true if the measurement value has changed and \c false +//! otherwise. +//! +//! \sa AONBatMonNewBatteryMeasureReady(), AONBatMonTemperatureGetDegC() +// +//***************************************************************************** +__STATIC_INLINE bool +AONBatMonNewTempMeasureReady(void) +{ + bool bStatus; + + // Check the status bit. + bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) & + AON_BATMON_TEMPUPD_STAT ? true : false; + + // Clear status bit if set. + if(bStatus) + { + HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) = 1; + } + + // Return status. + return (bStatus); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONBatMonTemperatureGetDegC + #undef AONBatMonTemperatureGetDegC + #define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_BATMON_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.c new file mode 100644 index 0000000..d5e483c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.c @@ -0,0 +1,180 @@ +/****************************************************************************** +* Filename: aon_event.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the AON Event fabric. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_event.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONEventMcuWakeUpSet + #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet + #undef AONEventMcuWakeUpGet + #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet + #undef AONEventMcuSet + #define AONEventMcuSet NOROM_AONEventMcuSet + #undef AONEventMcuGet + #define AONEventMcuGet NOROM_AONEventMcuGet +#endif + +//***************************************************************************** +// +// Select event source for the specified MCU wakeup programmable event +// +//***************************************************************************** +void +AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Shift ; + uint32_t ui32Mask ; + uint32_t ui32RegAdr ; + + // Check the arguments. + ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 )) + ASSERT( ui32EventSrc <= AON_EVENT_NONE ); + + ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 ); + ui32Mask = ( 0x3F << ui32Shift ); + ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL ); + if ( ui32MCUWUEvent > 3 ) { + ui32RegAdr += 4; + } + HWREG( ui32RegAdr ) = ( HWREG( ui32RegAdr ) & ( ~ui32Mask )) | ( ui32EventSrc << ui32Shift ); +} + +//***************************************************************************** +// +// Get event source for the specified MCU wakeup programmable event +// +//***************************************************************************** +uint32_t +AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent) +{ + uint32_t ui32Shift ; + uint32_t ui32RegAdr ; + + // Check the arguments. + ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 )) + + ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 ); + ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL ); + if ( ui32MCUWUEvent > 3 ) { + ui32RegAdr += 4; + } + return (( HWREG( ui32RegAdr ) >> ui32Shift ) & 0x3F ); +} + +//***************************************************************************** +// +// Select event source for the specified programmable event forwarded to the +// MCU event fabric +// +//***************************************************************************** +void +AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL) = ui32Ctrl; +} + +//***************************************************************************** +// +// Get source for the specified programmable event forwarded to the MCU event +// fabric. +// +//***************************************************************************** +uint32_t +AONEventMcuGet(uint32_t ui32MCUEvent) +{ + uint32_t ui32EventSrc; + + // Check the arguments. + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S); + } + + // Should never get to this statement, but suppress warning. + ASSERT(0); + return(0); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h new file mode 100644 index 0000000..9c14b4d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h @@ -0,0 +1,564 @@ +/****************************************************************************** +* Filename: aon_event.h +* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) +* Revision: 49506 +* +* Description: Defines and prototypes for the AON Event fabric. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonevent_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_EVENT_H__ +#define __AON_EVENT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_event.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet + #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet + #define AONEventMcuSet NOROM_AONEventMcuSet + #define AONEventMcuGet NOROM_AONEventMcuGet +#endif + +//***************************************************************************** +// +// Event sources for the event AON fabric. +// Note: Events are level-triggered active high +// +//***************************************************************************** +#define AON_EVENT_IOEV_MCU_WU 0 // Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +#define AON_EVENT_AUX_TIMER2_EV0 1 // Event 0 from AUX Timer2 +#define AON_EVENT_AUX_TIMER2_EV1 2 // Event 1 from AUX Timer2 +#define AON_EVENT_AUX_TIMER2_EV2 3 // Event 2 from AUX Timer2 +#define AON_EVENT_AUX_TIMER2_EV3 4 // Event 3 from AUX Timer2 +#define AON_EVENT_BATMON_BATT_UL 5 // BATMON event: Battery level above upper limit +#define AON_EVENT_BATMON_BATT_LL 6 // BATMON event: Battery level below lower limit +#define AON_EVENT_BATMON_TEMP_UL 7 // BATMON event: Temperature level above upper limit +#define AON_EVENT_BATMON_TEMP_LL 8 // BATMON event: Temperature level below lower limit +#define AON_EVENT_BATMON_COMBINED 9 // Combined event from BATMON +#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC. + // Event ID 33 is reserved for future use + // Event ID 34 is reserved for future use +#define AON_EVENT_RTC_CH0 35 // RTC channel 0 +#define AON_EVENT_RTC_CH1 36 // RTC channel 1 +#define AON_EVENT_RTC_CH2 37 // RTC channel 2 +#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event +#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event +#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event +#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event +#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +#define AON_EVENT_JTAG 43 // JTAG generated event +#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0 +#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1 +#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2 +#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX) +#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX) +#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed +#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out +#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event +#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event +#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event +#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event +#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +#define AON_EVENT_AUX_COMPB_ASYNC_N 56 // Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B + // Event ID 57-62 is reserved for future use +#define AON_EVENT_NONE 63 // No event, always low + +// Keeping backward compatibility until major revision number is incremented +#define AON_EVENT_RTC0 ( AON_EVENT_RTC_CH0 ) + +//***************************************************************************** +// +// Values that can be passed to AONEventMCUWakeUpSet() and returned +// by AONEventMCUWakeUpGet(). +// +//***************************************************************************** +#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0 +#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1 +#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2 +#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3 +#define AON_EVENT_MCU_WU4 4 // Programmable MCU wake-up event 4 +#define AON_EVENT_MCU_WU5 5 // Programmable MCU wake-up event 5 +#define AON_EVENT_MCU_WU6 6 // Programmable MCU wake-up event 6 +#define AON_EVENT_MCU_WU7 7 // Programmable MCU wake-up event 7 + +//***************************************************************************** +// +// Values that can be passed to AONEventMcuSet() and AONEventMcuGet() +// +//***************************************************************************** +#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3) +#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3) +#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3) + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Select event source for the specified MCU wake-up programmable event. +//! +//! The AON event fabric has several programmable events that can wake up the MCU. +//! +//! \note The programmable event sources are effectively OR'ed together +//! to form a single wake-up event. +//! +//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources. +//! - \ref AON_EVENT_MCU_WU0 +//! - \ref AON_EVENT_MCU_WU1 +//! - \ref AON_EVENT_MCU_WU2 +//! - \ref AON_EVENT_MCU_WU3 +//! - \ref AON_EVENT_MCU_WU4 +//! - \ref AON_EVENT_MCU_WU5 +//! - \ref AON_EVENT_MCU_WU6 +//! - \ref AON_EVENT_MCU_WU7 +//! \param ui32EventSrc is an event source for the event AON fabric. +//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 +//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit +//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit +//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit +//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit +//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventMcuWakeUpGet() +// +//***************************************************************************** +extern void AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, + uint32_t ui32EventSrc); + +//***************************************************************************** +// +//! \brief Get event source for the specified MCU wake-up programmable event. +//! +//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources. +//! - \ref AON_EVENT_MCU_WU0 +//! - \ref AON_EVENT_MCU_WU1 +//! - \ref AON_EVENT_MCU_WU2 +//! - \ref AON_EVENT_MCU_WU3 +//! - \ref AON_EVENT_MCU_WU4 +//! - \ref AON_EVENT_MCU_WU5 +//! - \ref AON_EVENT_MCU_WU6 +//! - \ref AON_EVENT_MCU_WU7 +//! +//! \return Returns the event source for the event AON fabric. +//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 +//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit +//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit +//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit +//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit +//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventMcuWakeUpSet() +// +//***************************************************************************** +extern uint32_t AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent); + +//***************************************************************************** +// +//! \brief Select event source for the specified programmable event forwarded to the +//! MCU event fabric. +//! +//! The AON event fabric has a total of three programmable events that can +//! be forwarded to the MCU event fabric. +//! +//! \note The three programmable event sources are forwarded to the MCU Event +//! Fabric as: +//! - AON_PROG0 +//! - AON_PROG1 +//! - AON_PROG2 +//! +//! \param ui32MCUEvent is one of three programmable events forwarded to the +//! MCU event fabric. +//! - \ref AON_EVENT_MCU_EVENT0 +//! - \ref AON_EVENT_MCU_EVENT1 +//! - \ref AON_EVENT_MCU_EVENT2 +//! \param ui32EventSrc is an event source for the event AON fabric. +//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 +//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit +//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit +//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit +//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit +//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventMcuGet() +// +//***************************************************************************** +extern void AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc); + +//***************************************************************************** +// +//! \brief Get source for the specified programmable event forwarded to the MCU event +//! fabric. +//! +//! The AON event fabric has a total of three programmable events that can +//! be forwarded to the MCU event fabric. +//! +//! \param ui32MCUEvent is one of three programmable events forwarded to the +//! MCU event fabric. +//! - \ref AON_EVENT_MCU_EVENT0 +//! - \ref AON_EVENT_MCU_EVENT1 +//! - \ref AON_EVENT_MCU_EVENT2 +//! +//! \return Returns the event source for the event AON fabric. +//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 +//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit +//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit +//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit +//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit +//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventMcuSet() +// +//***************************************************************************** +extern uint32_t AONEventMcuGet(uint32_t ui32MCUEvent); + +//***************************************************************************** +// +//! \brief Select event source forwarded to AON Real Time Clock (RTC). +//! +//! A programmable event can be forwarded to the AON real time clock +//! for triggering a capture event on RTC channel 1. +//! +//! \param ui32EventSrc is an event source for the event AON fabric. +//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 +//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit +//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit +//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit +//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit +//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventRtcGet() +// +//***************************************************************************** +__STATIC_INLINE void +AONEventRtcSet(uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL); + ui32Ctrl &= ~(AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S; + + HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL) = ui32Ctrl; +} + +//***************************************************************************** +// +//! \brief Get event source forwarded to AON Real Time Clock (RTC). +//! +//! A programmable event can be forwarded to the AON real time clock +//! for triggering a capture event on RTC channel 1. +//! +//! \return Returns the event source to the event AON fabric. +//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 +//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit +//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit +//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit +//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit +//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventRtcSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONEventRtcGet(void) +{ + uint32_t ui32EventSrc; + + // Return the active event. + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL); + + return ((ui32EventSrc & AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M) >> + AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONEventMcuWakeUpSet + #undef AONEventMcuWakeUpSet + #define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet + #endif + #ifdef ROM_AONEventMcuWakeUpGet + #undef AONEventMcuWakeUpGet + #define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet + #endif + #ifdef ROM_AONEventMcuSet + #undef AONEventMcuSet + #define AONEventMcuSet ROM_AONEventMcuSet + #endif + #ifdef ROM_AONEventMcuGet + #undef AONEventMcuGet + #define AONEventMcuGet ROM_AONEventMcuGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_EVENT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event_doc.h new file mode 100644 index 0000000..75a8b0a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event_doc.h @@ -0,0 +1,58 @@ +/****************************************************************************** +* Filename: aon_event_doc.h +* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) +* Revision: 49506 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonevent_api +//! @{ +//! \section sec_aonevent Introduction +//! +//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and +//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers +//! to the AON event fabric. For more information on MCU event fabric, see [MCU event API](@ref event_api). +//! +//! The AON event fabric is a configurable combinatorial router between AON event sources and event +//! subscribers in both AON and MCU domains. The API to control the AON event fabric configuration +//! can be grouped based on the event subscriber to configure: +//! +//! - Wake-up events. +//! - MCU wake-up event +//! - @ref AONEventMcuWakeUpSet() +//! - @ref AONEventMcuWakeUpGet() +//! - AON RTC receives a single programmable event line from the AON event fabric. For more information, see [AON RTC API](@ref aonrtc_api). +//! - @ref AONEventRtcSet() +//! - @ref AONEventRtcGet() +//! - MCU event fabric receives a number of programmable event lines from the AON event fabric. For more information, see [MCU event API](@ref event_api). +//! - @ref AONEventMcuSet() +//! - @ref AONEventMcuGet() +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.c new file mode 100644 index 0000000..d4475b7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.c @@ -0,0 +1,39 @@ +/****************************************************************************** +* Filename: aon_ioc.c +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Driver for the AON IO Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_ioc.h" diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.h new file mode 100644 index 0000000..513e0e2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.h @@ -0,0 +1,292 @@ +/****************************************************************************** +* Filename: aon_ioc.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the AON IO Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonioc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_IOC_H__ +#define __AON_IOC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_ioc.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the drive strength +// +//***************************************************************************** +#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength +#define AONIOC_DRV_STR_2 0x00000001 +#define AONIOC_DRV_STR_3 0x00000003 +#define AONIOC_DRV_STR_4 0x00000002 +#define AONIOC_DRV_STR_5 0x00000006 +#define AONIOC_DRV_STR_6 0x00000007 +#define AONIOC_DRV_STR_7 0x00000005 +#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength + +#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN) +#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED) +#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX) + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure drive strength values for the manual drive strength options. +//! +//! This function defines the general drive strength settings for the non-AUTO +//! drive strength options in the MCU IOC. Consequently, if all IOs are using the +//! automatic drive strength option this function has no effect. +//! +//! Changing the drive strength values affects all current modes (Low-Current, +//! High-Current, and Extended-Current). Current mode for individual IOs is set in +//! MCU IOC by \ref IOCIODrvStrengthSet(). +//! +//! \note Values are Gray encoded. Simply incrementing values to increase drive +//! strength will not work. +//! +//! \param ui32DriveLevel +//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. Default value is selected +//! to give minimum 2/4/8 mA @3.3V for Low-Current mode, High-Current mode, +//! and Extended-Current mode respectively. +//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. Default value is selected +//! to give minimum 2/4/8 mA @2.5V for Low-Current mode, High-Current mode, +//! and Extended-Current mode respectively. +//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. Default value is selected +//! to give minimum 2/4/8 mA @1.8V for Low-Current mode, High-Current mode, +//! and Extended-Current mode respectively. +//! \param ui32DriveStrength sets the value used by IOs configured as non-AUTO drive strength in MCU IOC. +//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength +//! - \ref AONIOC_DRV_STR_2 +//! - \ref AONIOC_DRV_STR_3 +//! - \ref AONIOC_DRV_STR_4 +//! - \ref AONIOC_DRV_STR_5 +//! - \ref AONIOC_DRV_STR_6 +//! - \ref AONIOC_DRV_STR_7 +//! - \ref AONIOC_DRV_STR_8 : Highest drive strength +//! +//! \return None +//! +//! \sa \ref AONIOCDriveStrengthGet(), \ref IOCIODrvStrengthSet() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOCDriveStrengthSet(uint32_t ui32DriveLevel, uint32_t ui32DriveStrength) +{ + ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) || + (ui32DriveLevel == AONIOC_DRV_LVL_MED) || + (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); + ASSERT((ui32DriveStrength == AONIOC_DRV_STR_1) || + (ui32DriveStrength == AONIOC_DRV_STR_2) || + (ui32DriveStrength == AONIOC_DRV_STR_3) || + (ui32DriveStrength == AONIOC_DRV_STR_4) || + (ui32DriveStrength == AONIOC_DRV_STR_5) || + (ui32DriveStrength == AONIOC_DRV_STR_6) || + (ui32DriveStrength == AONIOC_DRV_STR_7) || + (ui32DriveStrength == AONIOC_DRV_STR_8)); + + // Set the drive strength. + HWREG(AON_IOC_BASE + ui32DriveLevel) = ui32DriveStrength; +} + +//***************************************************************************** +// +//! \brief Get a specific drive level setting for all IOs. +//! +//! Use this function to read the drive strength setting for a specific +//! IO drive level. +//! +//! \note Values are Gray encoded. +//! +//! \param ui32DriveLevel is the specific drive level to get the setting for. +//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. +//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. +//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. +//! +//! \return Returns the requested drive strength level setting for all IOs. +//! Possible values are: +//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength +//! - \ref AONIOC_DRV_STR_2 +//! - \ref AONIOC_DRV_STR_3 +//! - \ref AONIOC_DRV_STR_4 +//! - \ref AONIOC_DRV_STR_5 +//! - \ref AONIOC_DRV_STR_6 +//! - \ref AONIOC_DRV_STR_7 +//! - \ref AONIOC_DRV_STR_8 : Highest drive strength +//! +//! \sa AONIOCDriveStrengthSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONIOCDriveStrengthGet(uint32_t ui32DriveLevel) +{ + // Check the arguments. + ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) || + (ui32DriveLevel == AONIOC_DRV_LVL_MED) || + (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); + + // Return the drive strength value. + return( HWREG(AON_IOC_BASE + ui32DriveLevel) ); +} + +//***************************************************************************** +// +//! \brief Freeze the IOs. +//! +//! To retain the values of the output IOs during a powerdown/shutdown of the +//! device all IO latches in the AON domain should be frozen in their current +//! state. This ensures that software can regain control of the IOs after a +//! reboot without the IOs first falling back to the default values (i.e. input +//! and no pull). +//! +//! \return None +//! +//! \sa AONIOCFreezeDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOCFreezeEnable(void) +{ + // Set the AON IO latches as static. + HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = 0x0; +} + +//***************************************************************************** +// +//! \brief Un-freeze the IOs. +//! +//! When rebooting the chip after it has entered powerdown/shutdown mode, the +//! software can regain control of the IOs by setting the IO latches as +//! transparent. The IOs should not be unfrozen before software has restored +//! the functionality of the IO. +//! +//! \return None +//! +//! \sa AONIOCFreezeEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOCFreezeDisable(void) +{ + // Set the AON IOC latches as transparent. + HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = AON_IOC_IOCLATCH_EN; +} + +//***************************************************************************** +// +//! \brief Disable the 32kHz clock output. +//! +//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality +//! in the IOC is bypassed. Therefore, the programmer needs to call this +//! function to disable the clock output. +//! +//! \return None +//! +//! \sa AONIOC32kHzOutputEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOC32kHzOutputDisable(void) +{ + // Disable the LF clock output. + HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = AON_IOC_CLK32KCTL_OE_N; +} + +//***************************************************************************** +// +//! \brief Enable the 32kHz clock output. +//! +//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality +//! in the IOC is bypassed. Therefore, the programmer needs to call this +//! function to enable the clock output. +//! +//! \return None +//! +//! \sa AONIOC32kHzOutputDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOC32kHzOutputEnable(void) +{ + // Enable the LF clock output. + HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = 0x0; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_IOC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc_doc.h new file mode 100644 index 0000000..7fe0e93 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc_doc.h @@ -0,0 +1,65 @@ +/****************************************************************************** +* Filename: aon_ioc_doc.h +* Revised: 2016-03-30 11:01:30 +0200 (Wed, 30 Mar 2016) +* Revision: 45969 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonioc_api +//! @{ +//! \section sec_aonioc Introduction +//! +//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO). +//! The IOC consists of two APIs: +//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it. +//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc. +//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is +//! routed to a DIO for external use. +//! +//! For more information on the MCU IOC see the [IOC API](\ref ioc_api). +//! +//! \section sec_aonioc_api API +//! +//! The API functions can be grouped like this: +//! +//! Freeze IOs while MCU domain is powered down: +//! - \ref AONIOCFreezeEnable() +//! - \ref AONIOCFreezeDisable() +//! +//! Output LF clock to a DIO: +//! - \ref AONIOC32kHzOutputEnable() +//! - \ref AONIOC32kHzOutputDisable() +//! +//! Configure the value of drive strength for the three manual MCU IOC settings (MIN, MED, MAX): +//! - \ref AONIOCDriveStrengthSet() +//! - \ref AONIOCDriveStrengthGet() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.c new file mode 100644 index 0000000..005bab6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: aon_pmctl.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the AON Power-Management Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_pmctl.h" + +// See aon_pmctl.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.h new file mode 100644 index 0000000..fef39d6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.h @@ -0,0 +1,201 @@ +/****************************************************************************** +* Filename: aon_pmctl.h +* Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) +* Revision: 50156 +* +* Description: Defines and prototypes for the AON Power-Management Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonpmctl_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_PMCTL_H__ +#define __AON_PMCTL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_pmctl.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines that can be be used to enable/disable the retention on the SRAM +// banks during power off of the MCU BUS domain. The defines can be passed to +// AONPMCTLMcuSRamConfig) . +// +//***************************************************************************** +#define MCU_RAM_RET_NONE AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE +#define MCU_RAM_RET_LVL1 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1 +#define MCU_RAM_RET_LVL2 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2 +#define MCU_RAM_RET_LVL3 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3 +#define MCU_RAM_RET_FULL AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL + +//***************************************************************************** +// +// Defines for all the different power modes available through +// AONPMCTLPowerStatusGet() . +// +//***************************************************************************** +#define AONPMCTL_JTAG_POWER_ON AON_PMCTL_PWRSTAT_JTAG_PD_ON + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure the retention on the block SRAM in the MCU BUS domain. +//! +//! MCU SRAM is partitioned into 5 banks of 16 KB each. The SRAM supports +//! retention on all 5 banks during MCU BUS domain power off. The retention +//! on the SRAM can be turned on and off. Use this function to enable the +//! retention on the banks. +//! +//! If a group of banks is not represented in the parameter \c ui32Retention +//! then the retention will be disabled for that bank group during MCU BUS +//! domain power off. +//! +//! \note Retention on all SRAM banks is enabled by default. Configuration of +//! individual SRAM banks is not supported. Configuration is only supported +//! on bank group level. +//! +//! \param ui32Retention defines which groups of SRAM banks to enable/disable +//! retention on: +//! - \ref MCU_RAM_RET_NONE Retention is disabled +//! - \ref MCU_RAM_RET_LVL1 Retention on for banks 0 and 1 +//! - \ref MCU_RAM_RET_LVL2 Retention on for banks 0, 1 and 2 +//! - \ref MCU_RAM_RET_LVL3 Retention on for banks 0, 1, 2 and 3 +//! - \ref MCU_RAM_RET_FULL Retention on for all five banks +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONPMCTLMcuSRamRetConfig(uint32_t ui32Retention) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT((ui32Retention == MCU_RAM_RET_NONE) || + (ui32Retention == MCU_RAM_RET_LVL1) || + (ui32Retention == MCU_RAM_RET_LVL2) || + (ui32Retention == MCU_RAM_RET_LVL3) || + (ui32Retention == MCU_RAM_RET_FULL)); + + // Configure the retention. + ui32Reg = HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RAMCFG) & ~AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_M; + ui32Reg |= ui32Retention; + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RAMCFG) = ui32Reg; +} + +//***************************************************************************** +// +//! \brief Get the power status of the Always On (AON) domain. +//! +//! This function reports the power management status in AON. +//! +//! \return Returns the current power status of the device as a bitwise OR'ed +//! combination of these values: +//! - \ref AONPMCTL_JTAG_POWER_ON +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONPMCTLPowerStatusGet(void) +{ + // Return the power status. + return (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRSTAT)); +} + + +//***************************************************************************** +// +//! \brief Request power off of the JTAG domain. +//! +//! The JTAG domain is automatically powered up on if a debugger is connected. +//! If a debugger is not connected this function can be used to power off the +//! JTAG domain. +//! +//! \note Achieving the lowest power modes (shutdown/powerdown) requires the +//! JTAG domain to be turned off. In general the JTAG domain should never be +//! powered in production code. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONPMCTLJtagPowerOff(void) +{ + // Request the power off of the JTAG domain + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_JTAGCFG) = 0; +} + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_PMCTL_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl_doc.h new file mode 100644 index 0000000..60dec60 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl_doc.h @@ -0,0 +1,99 @@ +/****************************************************************************** +* Filename: aon_pmctl_doc.h +* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) +* Revision: 50165 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonpmctl_api +//! @{ +//! \section sec_aonpmctl Introduction +//! +//! This API provides a set of functions for using the AON Power Management +//! Controller module (AON_PMCTL). +//! +//! The AON_PMCTL module contains the following functional options: +//! - Selection of voltage regulator for the digital domain. +//! - Control of retention of MCU SRAM banks during power off of the BUS power domain. +//! - Control of power and retention of AUX SRAM. +//! - Control of power, reset, and clock for the following domains: +//! - MCU_VD +//! - JTAG_PD +//! - AUX +//! - Control of the recharging of VDDR while in uLDO state. +//! - Control of the generation of a periodic request to the OSCDIG to initiate +//! an XOSC_HF amplitude calibration sequence. +//! +//! The main clock for the AON_PMCTL module is the 2 MHz SCLK MF clock. +//! +//! AON_PMCTL supports the MCU_voltage domain with a 48 MHz clock (SCLK_HF) that is divided +//! and gated by the PRCM module before being distributed to all modules in the +//! MCU voltage domain. +//! +//! The AON_PMCTL controls the SCLK_HF clock to ensure that it is available in the +//! Active and Idle power modes, and disabled for all other modes. SCLK_HF is not +//! allowed in uLDO state since it uses too much power. +//! The SCLK_HF clock is also available for the AUX module in the Active and Idle +//! power modes. +//! +//! The AON_PMCTL selects the clock source for the AUX domain in the different +//! power modes. +//! +//! Main functionality to control power management of the JTAG power domain is +//! supported. Note that no clock control is supported, as the JTAG is clocked +//! on the TCK clock. +//! +//! +//! \section sec_aonpmctl_api API +//! +//! The API functions can be grouped like this: +//! +//! Functions to perform status report: +//! - \ref AONPMCTLPowerStatusGet() +//! +//! +//! Functions to perform device configuration: +//! - \ref AONPMCTLJtagPowerOff() +//! - \ref AONPMCTLMcuSRamRetConfig() +//! +//! Please note that due to legacy software compatibility some functionalities controlled +//! by the AON Power Management Controller module are supported through the APIs of +//! the [System Controller](@ref sysctrl_api) and [Power Controller](@ref pwrctrl_api). Relevant functions are: +//! - \ref PowerCtrlSourceGet() +//! - \ref PowerCtrlSourceSet() +//! - \ref PowerCtrlResetSourceGet() +//! - \ref SysCtrl_DCDC_VoltageConditionalControl() +//! - \ref SysCtrlClockLossResetDisable() +//! - \ref SysCtrlClockLossResetEnable() +//! - \ref SysCtrlSystemReset() +//! - \ref SysCtrlResetSourceGet() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.c new file mode 100644 index 0000000..3d0cac0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.c @@ -0,0 +1,77 @@ +/****************************************************************************** +* Filename: aon_rtc.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the AON RTC. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_rtc.h" +#include "cpu.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONRTCCurrent64BitValueGet + #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet +#endif + + +//***************************************************************************** +// +// Get the current 64-bit value of the RTC counter. +// +//***************************************************************************** +uint64_t +AONRTCCurrent64BitValueGet( void ) +{ + union { + uint64_t returnValue ; + uint32_t secAndSubSec[ 2 ] ; + } currentRtc ; + uint32_t ui32SecondSecRead ; + + // Reading SEC both before and after SUBSEC in order to detect if SEC incremented while reading SUBSEC + // If SEC incremented, we can't be sure which SEC the SUBSEC belongs to, so repeating the sequence then. + do { + currentRtc.secAndSubSec[ 1 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + currentRtc.secAndSubSec[ 0 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SUBSEC ); + ui32SecondSecRead = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + } while ( currentRtc.secAndSubSec[ 1 ] != ui32SecondSecRead ); + + return ( currentRtc.returnValue ); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.h new file mode 100644 index 0000000..a667e43 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.h @@ -0,0 +1,931 @@ +/****************************************************************************** +* Filename: aon_rtc.h +* Revised: 2017-08-16 15:13:43 +0200 (Wed, 16 Aug 2017) +* Revision: 49593 +* +* Description: Defines and prototypes for the AON RTC +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonrtc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_RTC_H__ +#define __AON_RTC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_rtc.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet +#endif + +//***************************************************************************** +// +// Values that can be passed to most of the AON_RTC APIs as the ui32Channel +// parameter. +// +//***************************************************************************** +#define AON_RTC_CH_NONE 0x0 // RTC No channel +#define AON_RTC_CH0 0x1 // RTC Channel 0 +#define AON_RTC_CH1 0x2 // RTC Channel 1 +#define AON_RTC_CH2 0x4 // RTC Channel 2 +#define AON_RTC_ACTIVE 0x8 // RTC Active + +//***************************************************************************** +// +// Values that can be passed to AONRTCConfigDelay as the ui32Delay parameter. +// +//***************************************************************************** +#define AON_RTC_CONFIG_DELAY_NODELAY 0 // NO DELAY +#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle +#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles +#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles +#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles +#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles +#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles +#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles +#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles +#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles +#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles +#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles +#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles +#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles + +//***************************************************************************** +// +// Values that can be passed to AONRTCSetModeCH1 as the ui32Mode +// parameter. +// +//***************************************************************************** +#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode +#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode + +//***************************************************************************** +// +// Values that can be passed to AONRTCSetModeCH2 as the ui32Mode +// parameter. +// +//***************************************************************************** +#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode +#define AON_RTC_MODE_CH2_NORMALCOMPARE 0 // Normal compare mode + +//***************************************************************************** +// +// Mutliplication factor for converting from seconds to corresponding time in +// the "CompareValue" format. +// The factor correspond to the compare value format described in the registers +// \ref AON_RTC_O_CH0CMP, \ref AON_RTC_O_CH1CMP and \ref AON_RTC_O_CH2CMP. +// Example1: +// 4 milliseconds in CompareValue format can be written like this: +// ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT )) +// Example2: +// 4 seconds in CompareValue format can be written like this: +// ( 4 * FACTOR_SEC_TO_COMP_VAL_FORMAT ) +// +//***************************************************************************** +#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enable the RTC. +//! +//! Enable the AON Real Time Clock. +//! +//! \note Event generation for each of the three channels must also be enabled +//! using the function AONRTCChannelEnable(). +//! +//! \return None +//! +//! \sa AONRTCChannelEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCEnable(void) +{ + // Enable RTC. + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disable the RTC. +//! +//! Disable the AON Real Time Clock. +//! +//! \note Event generation for each of the three channels can also be disabled +//! using the function AONRTCChannelDisable(). +//! +//! \return None +//! +//! \sa AONRTCChannelDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCDisable(void) +{ + // Disable RTC + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Reset the RTC. +//! +//! Reset the AON Real Time Clock. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCReset(void) +{ + // Reset RTC. + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_RESET_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Check if the RTC is active (enabled). +//! +//! \return Returns the status of the RTC. +//! - false : RTC is disabled +//! - true : RTC is enabled +// +//***************************************************************************** +__STATIC_INLINE bool +AONRTCActive(void) +{ + // Read if RTC is enabled + return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN)); +} + +//***************************************************************************** +// +//! \brief Check if an RTC channel is active (enabled). +//! +//! \param ui32Channel specifies the RTC channel to check status of. +//! Parameter must be one (and only one) of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return Returns the status of the requested channel: +//! - false : Channel is disabled +//! - true : Channel is enabled +// +//***************************************************************************** +__STATIC_INLINE bool +AONRTCChannelActive(uint32_t ui32Channel) +{ + uint32_t uint32Status = 0; + + if(ui32Channel & AON_RTC_CH0) + { + uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN); + } + + if(ui32Channel & AON_RTC_CH1) + { + uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN); + } + + if(ui32Channel & AON_RTC_CH2) + { + uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN); + } + + return(uint32Status); +} + +//***************************************************************************** +// +//! \brief Configure Event Delay for the RTC. +//! +//! Each event from the three individual channels can generate a delayed +//! event. The delay time for these events is set using this function. +//! The delay is measured in clock cycles. +//! +//! \note There is only one delay setting shared for all three channels. +//! +//! \param ui32Delay specifies the delay time for delayed events. +//! Parameter must be one of the following: +//! - \ref AON_RTC_CONFIG_DELAY_NODELAY +//! - \ref AON_RTC_CONFIG_DELAY_1 +//! - \ref AON_RTC_CONFIG_DELAY_2 +//! - \ref AON_RTC_CONFIG_DELAY_4 +//! - \ref AON_RTC_CONFIG_DELAY_8 +//! - \ref AON_RTC_CONFIG_DELAY_16 +//! - \ref AON_RTC_CONFIG_DELAY_32 +//! - \ref AON_RTC_CONFIG_DELAY_48 +//! - \ref AON_RTC_CONFIG_DELAY_64 +//! - \ref AON_RTC_CONFIG_DELAY_80 +//! - \ref AON_RTC_CONFIG_DELAY_96 +//! - \ref AON_RTC_CONFIG_DELAY_112 +//! - \ref AON_RTC_CONFIG_DELAY_128 +//! - \ref AON_RTC_CONFIG_DELAY_144 +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCDelayConfig(uint32_t ui32Delay) +{ + uint32_t ui32Cfg; + + // Check the arguments. + ASSERT(ui32Delay <= AON_RTC_CONFIG_DELAY_144); + + + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg &= ~(AON_RTC_CTL_EV_DELAY_M); + ui32Cfg |= (ui32Delay << AON_RTC_CTL_EV_DELAY_S); + + HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg; +} + +//***************************************************************************** +// +//! \brief Configure the source of the combined event. +//! +//! A combined delayed event can be generated from a combination of the three +//! delayed events. Delayed events form the specified channels are OR'ed +//! together to generate the combined event. +//! +//! \param ui32Channels specifies the channels that are to be used for +//! generating the combined event. +//! The parameter must be the bitwise OR of any of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! - \ref AON_RTC_CH_NONE +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCCombinedEventConfig(uint32_t ui32Channels) +{ + uint32_t ui32Cfg; + + // Check the arguments. + ASSERT( (ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) || + (ui32Channels == AON_RTC_CH_NONE) ); + + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg &= ~(AON_RTC_CTL_COMB_EV_MASK_M); + ui32Cfg |= (ui32Channels << AON_RTC_CTL_COMB_EV_MASK_S); + + HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg; +} + +//***************************************************************************** +// +//! \brief Clear event from a specified channel. +//! +//! In case of an active event from the specified channel, the event +//! will be cleared (de-asserted). +//! +//! \param ui32Channel clears the event from one or more RTC channels: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCEventClear(uint32_t ui32Channel) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH0; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH1; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH2; + } +} + +//***************************************************************************** +// +//! \brief Get event status for a specified channel. +//! +//! In case of an active event from the specified channel, +//! this call will return \c true otherwise \c false. +//! +//! \param ui32Channel specifies the channel from which to query the event state. +//! The parameter must be one (and only one) of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return Returns \c true if an event has occurred for the given channel, +//! otherwise \c false. +// +//***************************************************************************** +__STATIC_INLINE bool +AONRTCEventGet(uint32_t ui32Channel) +{ + uint32_t uint32Event = 0; + + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH0_BITN); + } + + if(ui32Channel & AON_RTC_CH1) + { + uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH1_BITN); + } + + if(ui32Channel & AON_RTC_CH2) + { + uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH2_BITN); + } + + return(uint32Event); +} + +//***************************************************************************** +// +//! \brief Get integer part (seconds) of RTC free-running timer. +//! +//! Get the value in seconds of RTC free-running timer, i.e. the integer part. +//! The fractional part is returned from a call to AONRTCFractionGet(). +//! +//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead +//! of this function if the <16.16> format is sufficient. +//! +//! \note To read a consistent pair of integer and fractional parts, +//! \ref AONRTCSecGet() must be called first to trigger latching of the +//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts +//! must be disabled to ensure that these operations are performed atomically. +//! +//! \return Returns the integer part of RTC free running timer. +//! +//! \sa \ref AONRTCFractionGet() \ref AONRTCCurrentCompareValueGet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCSecGet(void) +{ + // The following read gets the seconds, but also latches the fractional + // part. + return(HWREG(AON_RTC_BASE + AON_RTC_O_SEC)); +} + +//***************************************************************************** +// +//! \brief Get fractional part (sub-seconds) of RTC free-running timer. +//! +//! Get the value of the fractional part of RTC free-running timer, i.e. the +//! sub-second part. +//! +//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead +//! of this function if the <16.16> format is sufficient. +//! +//! \note To read a consistent pair of integer and fractional parts, +//! \ref AONRTCSecGet() must be called first to trigger latching of the +//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts +//! must be disabled to ensure that these operations are performed atomically. +//! +//! \return Returns the fractional part of RTC free running timer. +//! +//! \sa \ref AONRTCSecGet() \ref AONRTCCurrentCompareValueGet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCFractionGet(void) +{ + // Note1: It is recommended to use AON RTCCurrentCompareValueGet() instead + // of this function if the <16.16> format is sufficient. + // Note2: AONRTCSecGet() must be called before this function to get a + // consistent reading. + // Note3: Interrupts must be disabled between the call to AONRTCSecGet() and this + // call since there are interrupt functions that reads AON_RTC_O_SEC + return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC)); +} + +//***************************************************************************** +// +//! \brief Get the sub second increment of the RTC. +//! +//! Get the value of the sub-second increment which is added to the RTC +//! absolute time on every clock tick. +//! +//! \note For a precise and temperature independent LF clock (e.g. an LF XTAL) +//! this value would stay the same across temperature. For temperatue +//! dependent clock sources like an RC oscillator, this value will change +//! over time if the application includes functionality for doing temperature +//! compensation of the RTC clock source. The default value corresponds to a +//! LF clock frequency of exactly 32.768 kHz. +//! +//! \return Returns the sub-second increment of the RTC added to the overall +//! value on every RTC clock tick. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCSubSecIncrGet(void) +{ + return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSECINC)); +} + +//***************************************************************************** +// +//! \brief Set operational mode of channel 1. +//! +//! Set the operational mode of channel 1. It can be capture or compare mode. +//! In capture mode, an external event causes the value of the free running +//! counter to be stored, to remember the time of the event. +//! +//! \note The default mode is compare. +//! +//! \param ui32Mode specifies the mode for channel 1. +//! The parameter must be one of the following: +//! - \ref AON_RTC_MODE_CH1_CAPTURE +//! - \ref AON_RTC_MODE_CH1_COMPARE +//! +//! \return None +//! +//! \sa AONRTCModeCh1Get() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCModeCh1Set(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == AON_RTC_MODE_CH1_CAPTURE) || + (ui32Mode == AON_RTC_MODE_CH1_COMPARE)); + + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN) = ui32Mode; +} + +//***************************************************************************** +// +//! \brief Get operational mode of channel 1. +//! +//! Get the operational mode of channel 1. It can be capture or compare mode. +//! In capture mode, an external event causes the value of the free running +//! counter to be stored, to remember the time of the event. +//! +//! \return Returns the operational mode of channel 1, one of: +//! - \ref AON_RTC_MODE_CH1_CAPTURE +//! - \ref AON_RTC_MODE_CH1_COMPARE +//! +//! \sa AONRTCModeCh1Set() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCModeCh1Get(void) +{ + return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN)); +} + +//***************************************************************************** +// +//! \brief Set operational mode of channel 2. +//! +//! Set the operational mode of channel 2. It can be in continuous compare +//! mode or normal compare mode. +//! In continuous mode, a value is automatically incremented to the channel 2 +//! compare register, upon a channel 2 compare event. This allows channel 2 to +//! generate a series of completely equidistant events. +//! The increment value is set by the AONRTCIncValueCh2Set() call. +//! +//! \note The default mode is normal compare. +//! +//! \param ui32Mode specifies the mode for channel 2. +//! The parameter must be one of the following: +//! - \ref AON_RTC_MODE_CH2_CONTINUOUS +//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE +//! +//! \return None +//! +//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCModeCh2Set(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) || + (ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE)); + + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN) = ui32Mode; +} + +//***************************************************************************** +// +//! \brief Get operational mode of channel 2. +//! +//! Get the operational mode of channel 2. It can be in continuous compare +//! mode or normal compare mode. +//! In continuous mode, a value is automatically incremented to the channel 2 +//! compare register, upon a channel 2 compare event. This allows channel 2 to +//! generate a series of completely equidistant events. +//! The increment value is set by the AONRTCIncValueCh2Set() call. +//! +//! \return Returns the operational mode of channel 2, i.e. one of: +//! - \ref AON_RTC_MODE_CH2_CONTINUOUS +//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE +//! +//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCModeCh2Get(void) +{ + return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN)); +} + +//***************************************************************************** +// +//! \brief Enable event operation for the specified channel. +//! +//! Enable the event generation for the specified channel. +//! +//! \note The RTC free running clock must also be enabled globally using the +//! AONRTCEnable() call. +//! +//! \param ui32Channel specifies one or more channels to enable: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return None +//! +//! \sa AONRTCEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCChannelEnable(uint32_t ui32Channel) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 1; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 1; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 1; + } +} + +//***************************************************************************** +// +//! \brief Disable event operation for the specified channel. +//! +//! Disable the event generation for the specified channel. +//! +//! \note The RTC free running clock can also be disabled globally using the +//! AONRTCDisable() call. +//! +//! \param ui32Channel specifies one or more channels to disable: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return None +//! +//! \sa AONRTCDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCChannelDisable(uint32_t ui32Channel) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 0; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 0; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 0; + } +} + +//***************************************************************************** +// +//! \brief Set the compare value for the given channel. +//! +//! Set compare value for the specified channel. +//! +//! The format of the compare value is a 16 bit integer and 16 bit fractional +//! format <16 sec.16 subsec>. The current value of the RTC counter +//! can be retrieved in a format compatible to the compare register using +//! \ref AONRTCCurrentCompareValueGet() +//! +//! \param ui32Channel specifies one or more channels to set compare value for: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! \param ui32CompValue is the compare value to set for the specified channel. +//! - Format: <16 sec.16 subsec> +//! +//! \return None +//! +//! \sa AONRTCCurrentCompareValueGet() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCCompareValueSet(uint32_t ui32Channel, uint32_t ui32CompValue) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP) = ui32CompValue; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP) = ui32CompValue; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP) = ui32CompValue; + } +} + +//***************************************************************************** +// +//! \brief Get the compare value for the given channel. +//! +//! Get compare value for the specified channel. +//! +//! \param ui32Channel specifies a channel. +//! The parameter must be one (and only one) of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return Returns the stored compare value for the given channel. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCCompareValueGet(uint32_t ui32Channel) +{ + uint32_t ui32Value = 0; + + // Check the arguments + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP); + } + + if(ui32Channel & AON_RTC_CH1) + { + ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP); + } + + if(ui32Channel & AON_RTC_CH2) + { + ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP); + } + + return(ui32Value); +} + +//***************************************************************************** +// +//! \brief Get the current value of the RTC counter in a format that matches +//! RTC compare values. +//! +//! The compare value registers contains 16 integer and 16 fractional bits. +//! This function will return the current value of the RTC counter in an +//! identical format. +//! +//! \return Returns the current value of the RTC counter in a <16.16> format +//! (SEC[15:0].SUBSEC[31:16]). +//! +//! \sa \ref AONRTCCompareValueSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCCurrentCompareValueGet( void ) +{ + return ( HWREG( AON_RTC_BASE + AON_RTC_O_TIME )); +} + +//***************************************************************************** +// +//! \brief Get the current 64-bit value of the RTC counter. +//! +//! \note Reading SEC both before and after SUBSEC in order to detect if SEC +//! incremented while reading SUBSEC. If SEC incremented, we can't be sure +//! which SEC the SUBSEC belongs to, so repeating the sequence then. +//! +//! \return Returns the current value of the RTC counter in a 64-bits format +//! (SEC[31:0].SUBSEC[31:0]). +// +//***************************************************************************** +extern uint64_t AONRTCCurrent64BitValueGet(void); + +//***************************************************************************** +// +//! \brief Set the channel 2 increment value when operating in continuous mode. +//! +//! Set the channel 2 increment value when operating in continuous mode. +//! The specified value is automatically incremented to the channel 2 compare +//! register, upon a channel 2 compare event. This allows channel 2 to generate +//! a series of completely equidistant events. +//! +//! \param ui32IncValue is the increment value when operating in continuous mode. +//! +//! \return None +//! +//! \sa AONRTCIncValueCh2Get() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCIncValueCh2Set(uint32_t ui32IncValue) +{ + HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC) = ui32IncValue; +} + +//***************************************************************************** +// +//! \brief Get the channel2 increment value when operating in continuous mode. +//! +//! Get the channel 2 increment value, when channel 2 is operating in +//! continuous mode. +//! This value is automatically incremented to the channel 2 compare +//! register, upon a channel 2 compare event. This allows channel 2 to +//! generate a series of completely equidistant events. +//! +//! \return Returns the channel 2 increment value when operating in continuous +//! mode. +//! +//! \sa AONRTCIncValueCh2Set() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCIncValueCh2Get(void) +{ + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC)); +} + +//***************************************************************************** +// +//! \brief Get the channel 1 capture value. +//! +//! Get the channel 1 capture value. +//! The upper 16 bits of the returned value is the lower 16 bits of the +//! integer part of the RTC timer. The lower 16 bits of the returned part +//! is the upper 16 bits of the fractional part. +//! +//! \return Returns the channel 1 capture value. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCCaptureValueCh1Get(void) +{ + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH1CAPT)); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONRTCCurrent64BitValueGet + #undef AONRTCCurrent64BitValueGet + #define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_RTC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h new file mode 100644 index 0000000..b3c142b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: aon_rtc_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonrtc_api +//! @{ +//! \section sec_aonrtc Introduction +//! +//! \note If using TI-RTOS then only TI-RTOS is allowed to configure the RTC timer! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.c new file mode 100644 index 0000000..571282d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.c @@ -0,0 +1,337 @@ +/****************************************************************************** +* Filename: aux_adc.c +* Revised: 2017-11-20 14:31:35 +0100 (Mon, 20 Nov 2017) +* Revision: 50315 +* +* Description: Driver for the AUX Time to Digital Converter interface. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_adc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aux_sysif.h" +#include "../inc/hw_fcfg1.h" +#include "adi.h" +#include "event.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXADCDisable + #define AUXADCDisable NOROM_AUXADCDisable + #undef AUXADCEnableAsync + #define AUXADCEnableAsync NOROM_AUXADCEnableAsync + #undef AUXADCEnableSync + #define AUXADCEnableSync NOROM_AUXADCEnableSync + #undef AUXADCDisableInputScaling + #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling + #undef AUXADCFlushFifo + #define AUXADCFlushFifo NOROM_AUXADCFlushFifo + #undef AUXADCReadFifo + #define AUXADCReadFifo NOROM_AUXADCReadFifo + #undef AUXADCPopFifo + #define AUXADCPopFifo NOROM_AUXADCPopFifo + #undef AUXADCGetAdjustmentGain + #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain + #undef AUXADCGetAdjustmentOffset + #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset + #undef AUXADCValueToMicrovolts + #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts + #undef AUXADCMicrovoltsToValue + #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue + #undef AUXADCAdjustValueForGainAndOffset + #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset + #undef AUXADCUnadjustValueForGainAndOffset + #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset +#endif + +//***************************************************************************** +// +// Disables the ADC +// +//***************************************************************************** +void +AUXADCDisable(void) +{ + // Disable the ADC reference + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, ADI_4_AUX_ADCREF0_EN_M | ADI_4_AUX_ADCREF0_REF_ON_IDLE_M | ADI_4_AUX_ADCREF0_SRC_M); + + // Assert reset and disable the ADC + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M | ADI_4_AUX_ADC0_SMPL_MODE_M | ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M); + + // Ensure that scaling is enabled by default before next use of the ADC + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); + + // Flush the FIFO before disabling the clocks + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) + + // Disable the ADC clock (no need to wait since IOB_WUC_ADCCLKCTL_ACK goes low immediately) + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = 0; + + // Disable the ADC data interface + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = 0; +} + +//***************************************************************************** +// +// Enables the ADC for asynchronous operation +// +//***************************************************************************** +void +AUXADCEnableAsync(uint32_t refSource, uint32_t trigger) +{ + // Enable the ADC reference, with the following options: + // - SRC: Set when using relative reference + // - REF_ON_IDLE: Always cleared since there is no idle state in asynchronous operation + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, refSource | ADI_4_AUX_ADCREF0_EN_M); + + // Enable the ADC clock + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M; + while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M)); + + // Enable the ADC data interface + if (trigger == AUXADC_TRIGGER_MANUAL) { + // Manual trigger: No need to configure event routing from GPT + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN; + } else { + // GPT trigger: Configure event routing via MCU_EV to the AUX domain + HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; + } + + // Configure the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_SMPL_MODE_M); + + // Release reset and enable the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); +} + +//***************************************************************************** +// +// Enables the ADC for synchronous operation +// +//***************************************************************************** +void +AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger) +{ + // Enable the ADC reference, with the following options: + // - SRC: Set when using relative reference + // - REF_ON_IDLE: Set when using fixed reference and sample time < 21.3 us + uint8_t adcref0 = refSource | ADI_4_AUX_ADCREF0_EN_M; + if (!refSource && (sampleTime < AUXADC_SAMPLE_TIME_21P3_US)) { + adcref0 |= ADI_4_AUX_ADCREF0_REF_ON_IDLE_M; + } + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, adcref0); + + // Enable the ADC clock + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M; + while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M)); + + // Enable the ADC data interface + if (trigger == AUXADC_TRIGGER_MANUAL) { + // Manual trigger: No need to configure event routing from GPT + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN; + } else { + // GPT trigger: Configure event routing via MCU_EV to the AUX domain + HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; + } + + // Configure the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, sampleTime << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S); + + // Release reset and enable the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); +} + +//***************************************************************************** +// +// Disables scaling of the ADC input +// +//***************************************************************************** +void +AUXADCDisableInputScaling(void) +{ + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); +} + +//***************************************************************************** +// +// Flushes the ADC FIFO +// +//***************************************************************************** +void +AUXADCFlushFifo(void) +{ + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) +} + +//***************************************************************************** +// +// Waits for and returns the first sample in the ADC FIFO +// +//***************************************************************************** +uint32_t +AUXADCReadFifo(void) { + + // Wait until there is at least one sample in the FIFO + while (HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT) & AUX_ANAIF_ADCFIFOSTAT_EMPTY_M); + + // Return the first sample from the FIFO + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +//***************************************************************************** +// +// Returns the first sample in the ADC FIFO, without waiting +// +//***************************************************************************** +uint32_t +AUXADCPopFifo(void) { + + // Return the first sample from the FIFO. If the FIFO is empty, this + // generates ADC FIFO underflow + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +//***************************************************************************** +// +// Returns the gain value used when adjusting for ADC gain/offset +// +//***************************************************************************** +int32_t +AUXADCGetAdjustmentGain(uint32_t refSource) +{ + int32_t gain; + if (refSource == AUXADC_REF_FIXED) { + // AUXADC_REF_FIXED ==> ABS_GAIN + gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_ABS_GAIN) & FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S; + } else { + // AUXADC_REF_VDDS_REL ==> REL_GAIN + gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_REL_GAIN) & FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S; + } + return gain; +} + +//***************************************************************************** +// +// Returns the offset value used when adjusting for ADC gain/offset +// +//***************************************************************************** +int32_t +AUXADCGetAdjustmentOffset(uint32_t refSource) +{ + int8_t offset; + if ( refSource == AUXADC_REF_FIXED ) { + // AUXADC_REF_FIXED ==> ABS_OFFSET + offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S; + } else { + // AUXADC_REF_VDDS_REL ==> REL_OFFSET + offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S; + } + return offset; +} + +//***************************************************************************** +// +// Converts an "ideal" ADC value to microvolts +// +//***************************************************************************** +int32_t +AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue) +{ + // Chop off 4 bits during calculations to avoid 32-bit overflow + fixedRefVoltage >>= 4; + return (((adcValue * fixedRefVoltage) + 2047) / 4095) << 4; +} + +//***************************************************************************** +// +// Converts a number of microvolts to corresponding "ideal" ADC value +// +//***************************************************************************** +int32_t +AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts) +{ + // Chop off 4 bits during calculations to avoid 32-bit overflow + fixedRefVoltage >>= 4; + microvolts >>= 4; + return ((microvolts * 4095) + (fixedRefVoltage / 2)) / fixedRefVoltage; +} + +//***************************************************************************** +// +// Performs ADC value gain and offset adjustment +// +//***************************************************************************** +int32_t +AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) +{ + // Apply gain and offset adjustment + adcValue = (((adcValue + offset) * gain) + 16384) / 32768; + + // Saturate + if (adcValue < 0) { + return 0; + } else if (adcValue > 4095) { + return 4095; + } else { + return adcValue; + } +} + +//***************************************************************************** +// +// Performs the inverse of the ADC value gain and offset adjustment +// +//***************************************************************************** +int32_t +AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) +{ + // Apply inverse gain and offset adjustment + adcValue = (((adcValue * 32768) + (gain / 2)) / gain) - offset; + + // Saturate + if (adcValue < 0) { + return 0; + } else if (adcValue > 4095) { + return 4095; + } else { + return adcValue; + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h new file mode 100644 index 0000000..2731707 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h @@ -0,0 +1,599 @@ +/****************************************************************************** +* Filename: aux_adc.h +* Revised: 2018-02-07 09:45:39 +0100 (Wed, 07 Feb 2018) +* Revision: 51437 +* +* Description: Defines and prototypes for the AUX Analog-to-Digital +* Converter +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxadc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_ADC_H__ +#define __AUX_ADC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_event.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_4_aux.h" +#include "../inc/hw_aux_anaif.h" +#include "rom.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXADCDisable NOROM_AUXADCDisable + #define AUXADCEnableAsync NOROM_AUXADCEnableAsync + #define AUXADCEnableSync NOROM_AUXADCEnableSync + #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling + #define AUXADCFlushFifo NOROM_AUXADCFlushFifo + #define AUXADCReadFifo NOROM_AUXADCReadFifo + #define AUXADCPopFifo NOROM_AUXADCPopFifo + #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain + #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset + #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts + #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue + #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset + #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset +#endif + +//***************************************************************************** +// +// Defines for ADC reference sources. +// +//***************************************************************************** +#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S) +#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S) + +//***************************************************************************** +// +// Defines for the ADC FIFO status bits. +// +//***************************************************************************** +#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M) +#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M) +#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M) +#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M) +#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M) + +//***************************************************************************** +// +// Defines for supported ADC triggers. +// +//***************************************************************************** +#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE) +#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A) +#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B) +#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A) +#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B) +#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A) +#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B) +#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A) +#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B) +// Additional triggers specific for cc26x2 and cc13x2 devices +#define AUXADC_TRIGGER_GPT0A_CMP (EVENT_AUXSEL0_EV_GPT0A_CMP) +#define AUXADC_TRIGGER_GPT0B_CMP (EVENT_AUXSEL0_EV_GPT0B_CMP) +#define AUXADC_TRIGGER_GPT1A_CMP (EVENT_AUXSEL0_EV_GPT1A_CMP) +#define AUXADC_TRIGGER_GPT1B_CMP (EVENT_AUXSEL0_EV_GPT1B_CMP) +#define AUXADC_TRIGGER_GPT2A_CMP (EVENT_AUXSEL0_EV_GPT2A_CMP) +#define AUXADC_TRIGGER_GPT2B_CMP (EVENT_AUXSEL0_EV_GPT2B_CMP) +#define AUXADC_TRIGGER_GPT3A_CMP (EVENT_AUXSEL0_EV_GPT3A_CMP) +#define AUXADC_TRIGGER_GPT3B_CMP (EVENT_AUXSEL0_EV_GPT3B_CMP) + +//***************************************************************************** +// +// Defines for ADC sampling type for synchronous operation. +// +//***************************************************************************** +#define AUXADC_SAMPLE_TIME_2P7_US 3 +#define AUXADC_SAMPLE_TIME_5P3_US 4 +#define AUXADC_SAMPLE_TIME_10P6_US 5 +#define AUXADC_SAMPLE_TIME_21P3_US 6 +#define AUXADC_SAMPLE_TIME_42P6_US 7 +#define AUXADC_SAMPLE_TIME_85P3_US 8 +#define AUXADC_SAMPLE_TIME_170_US 9 +#define AUXADC_SAMPLE_TIME_341_US 10 +#define AUXADC_SAMPLE_TIME_682_US 11 +#define AUXADC_SAMPLE_TIME_1P37_MS 12 +#define AUXADC_SAMPLE_TIME_2P73_MS 13 +#define AUXADC_SAMPLE_TIME_5P46_MS 14 +#define AUXADC_SAMPLE_TIME_10P9_MS 15 + +//***************************************************************************** +// +// Equivalent voltages for fixed ADC reference, in microvolts. +// +//***************************************************************************** +#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000 +#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500 + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + + +//***************************************************************************** +// +//! \brief Disables the ADC. +//! +//! This function must be called: +//! - Before re-enabling the ADC using \ref AUXADCEnableAsync() or +//! \ref AUXADCEnableSync() +//! - Before entering system standby +// +//***************************************************************************** +extern void AUXADCDisable(void); + +//***************************************************************************** +// +//! \brief Enables the ADC for asynchronous operation. +//! +//! In asynchronous operation, the ADC samples continuously between +//! conversions. +//! +//! The ADC trigger starts the conversion. Note that the first conversion may +//! be invalid if the sampling period is too short. +//! +//! ADC input scaling is enabled by default after device reset, and is also re- +//! enabled by \ref AUXADCDisable(). To disable input scaling, call +//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableAsync(). +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! \param trigger +//! ADC conversion trigger: +//! - \ref AUXADC_TRIGGER_MANUAL +//! - \ref AUXADC_TRIGGER_GPT0A +//! - \ref AUXADC_TRIGGER_GPT0B +//! - \ref AUXADC_TRIGGER_GPT1A +//! - \ref AUXADC_TRIGGER_GPT1B +//! - \ref AUXADC_TRIGGER_GPT2A +//! - \ref AUXADC_TRIGGER_GPT2B +//! - \ref AUXADC_TRIGGER_GPT3A +//! - \ref AUXADC_TRIGGER_GPT3B +// +//***************************************************************************** +extern void AUXADCEnableAsync(uint32_t refSource, uint32_t trigger); + +//***************************************************************************** +// +//! \brief Enables the ADC for synchronous operation. +//! +//! In synchronous operation, the ADC is idle between a conversion and +//! subsequent samplings. +//! +//! The ADC trigger starts sampling with specified duration, followed by the +//! conversion. Note that the first conversion may be invalid if the initial +//! sampling period is too short. +//! +//! ADC input scaling is enabled by default after device reset, and is also re- +//! enabled by \ref AUXADCDisable(). To disable input scaling, call +//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableSync(). +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! \param sampleTime +//! ADC sampling time: +//! - \ref AUXADC_SAMPLE_TIME_2P7_US +//! - \ref AUXADC_SAMPLE_TIME_5P3_US +//! - \ref AUXADC_SAMPLE_TIME_10P6_US +//! - \ref AUXADC_SAMPLE_TIME_21P3_US +//! - \ref AUXADC_SAMPLE_TIME_42P6_US +//! - \ref AUXADC_SAMPLE_TIME_85P3_US +//! - \ref AUXADC_SAMPLE_TIME_170_US +//! - \ref AUXADC_SAMPLE_TIME_341_US +//! - \ref AUXADC_SAMPLE_TIME_682_US +//! - \ref AUXADC_SAMPLE_TIME_1P37_MS +//! - \ref AUXADC_SAMPLE_TIME_2P73_MS +//! - \ref AUXADC_SAMPLE_TIME_5P46_MS +//! - \ref AUXADC_SAMPLE_TIME_10P9_MS +//! \param trigger +//! ADC conversion trigger: +//! - \ref AUXADC_TRIGGER_MANUAL +//! - \ref AUXADC_TRIGGER_GPT0A +//! - \ref AUXADC_TRIGGER_GPT0B +//! - \ref AUXADC_TRIGGER_GPT1A +//! - \ref AUXADC_TRIGGER_GPT1B +//! - \ref AUXADC_TRIGGER_GPT2A +//! - \ref AUXADC_TRIGGER_GPT2B +//! - \ref AUXADC_TRIGGER_GPT3A +//! - \ref AUXADC_TRIGGER_GPT3B +// +//***************************************************************************** +extern void AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger); + +//***************************************************************************** +// +//! \brief Disables scaling of the ADC input. +//! +//! By default, the ADC operates internally on a version of the input signal +//! that has been scaled down by a factor 1408 / 4095. This function +//! disables that scaling, allowing for a trade-off between dynamic range and +//! and resolution. +//! +//! \note This function must only be called while the ADC is disabled, before +//! calling \ref AUXADCEnableSync() or \ref AUXADCEnableAsync(). +//! \note Different input maximum ratings apply when input scaling is disabled. +//! Violating these may damage the device. +// +//***************************************************************************** +extern void AUXADCDisableInputScaling(void); + +//***************************************************************************** +// +//! \brief Flushes the ADC FIFO. +//! +//! This empties the FIFO and clears the underflow/overflow flags. +//! +//! Note: This function must only be called while the ADC is enabled. +// +//***************************************************************************** +extern void AUXADCFlushFifo(void); + +//***************************************************************************** +// +//! \brief Generates a single manual ADC trigger. +//! +//! For synchronous mode, the trigger starts sampling followed by conversion. +//! For asynchronous mode, the trigger starts conversion. +// +//***************************************************************************** +__STATIC_INLINE void +AUXADCGenManualTrigger(void) +{ + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCTRIG) = 0; +} + +//***************************************************************************** +// +//! \brief Returns flags indicating the status of the ADC FIFO. +//! +//! The flags indicate FIFO empty, full and almost full, and whether +//! overflow/underflow has occurred. +//! +//! \return +//! A combination (bitwise OR) of the following flags: +//! - \ref AUXADC_FIFO_EMPTY_M +//! - \ref AUXADC_FIFO_ALMOST_FULL_M +//! - \ref AUXADC_FIFO_FULL_M +//! - \ref AUXADC_FIFO_UNDERFLOW_M +//! - \ref AUXADC_FIFO_OVERFLOW_M +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXADCGetFifoStatus(void) +{ + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT); +} + +//***************************************************************************** +// +//! \brief Waits for and returns the first sample in the ADC FIFO. +//! +//! This function waits until there is at least one sample in the ADC FIFO. It +//! then pops and returns the first sample from the FIFO. +//! +//! \note This procedure will deadlock if called without setting up ADC trigger +//! generation in advance. The trigger can either be manual or periodical +//! (using a GPT). +//! +//! \return The first (12-bit) sample from the ADC FIFO +// +//***************************************************************************** +extern uint32_t AUXADCReadFifo(void); + +//***************************************************************************** +// +//! \brief Returns the first sample in the ADC FIFO, without waiting. +//! +//! This function does not wait, and must only be called when there is at least +//! one sample in the ADC FIFO. Otherwise the call will generate FIFO underflow +//! (\ref AUXADC_FIFO_UNDERFLOW_M). +//! +//! \return The first (12-bit) sample from the ADC FIFO, or an undefined value +//! if the FIFO is empty +// +//***************************************************************************** +extern uint32_t AUXADCPopFifo(void); + +//***************************************************************************** +// +//! \brief Selects internal or external input for the ADC. +//! +//! Note that calling this function also selects the same input for AUX_COMPB. +//! +//! \param input +//! Internal/external input selection: +//! - \ref ADC_COMPB_IN_DCOUPL +//! - \ref ADC_COMPB_IN_VSS +//! - \ref ADC_COMPB_IN_VDDS +//! - \ref ADC_COMPB_IN_AUXIO7 +//! - \ref ADC_COMPB_IN_AUXIO6 +//! - \ref ADC_COMPB_IN_AUXIO5 +//! - \ref ADC_COMPB_IN_AUXIO4 +//! - \ref ADC_COMPB_IN_AUXIO3 +//! - \ref ADC_COMPB_IN_AUXIO2 +//! - \ref ADC_COMPB_IN_AUXIO1 +//! - \ref ADC_COMPB_IN_AUXIO0 +// +//***************************************************************************** +__STATIC_INLINE void +AUXADCSelectInput(uint32_t input) +{ + HapiSelectADCCompBInput(input); +} + +//***************************************************************************** +// +//! \brief Returns the gain value used when adjusting for ADC gain/offset. +//! +//! The function returns the gain value to be used with +//! \ref AUXADCAdjustValueForGainAndOffset() or +//! \ref AUXADCUnadjustValueForGainAndOffset(). The gain value is found during +//! chip manufacturing and is stored in the factory configuration, FCFG1. +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! +//! \return +//! The gain value to be used in adjustments +// +//***************************************************************************** +extern int32_t AUXADCGetAdjustmentGain(uint32_t refSource); + +//***************************************************************************** +// +//! \brief Returns the offset value used when adjusting for ADC gain/offset. +//! +//! The function returns the offset value to be used with +//! \ref AUXADCAdjustValueForGainAndOffset() or +//! \ref AUXADCUnadjustValueForGainAndOffset(). The offset value is found +//! during chip manufacturing and is stored in the factory configuration, +//! FCFG1. +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! +//! \return +//! The offset value to be used in adjustments +// +//***************************************************************************** +extern int32_t AUXADCGetAdjustmentOffset(uint32_t refSource); + +//***************************************************************************** +// +//! \brief Converts an "adjusted" ADC value to microvolts. +//! +//! This function can only be used when measuring with fixed ADC reference +//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for +//! whether the sampled ADC input is scaled down before conversion or not. +//! +//! \param fixedRefVoltage +//! Fixed reference voltage, in microvolts +//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal) +//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input +//! \param adcValue +//! The ADC value +//! +//! \return +//! The corresponding number of microvolts +// +//***************************************************************************** +extern int32_t AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue); + +//***************************************************************************** +// +//! \brief Converts a number of microvolts to corresponding "adjusted" ADC value. +//! +//! This function can only be used when measuring with fixed ADC reference +//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for +//! whether the sampled ADC input is scaled down before conversion or not. +//! +//! \param fixedRefVoltage +//! Fixed reference voltage, in microvolts +//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal) +//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input +//! \param microvolts +//! The number of microvolts +//! +//! \return +//! The corresponding expected ADC value (adjusted for ADC gain/offset) +// +//***************************************************************************** +extern int32_t AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts); + +//***************************************************************************** +// +//! \brief Performs ADC value gain and offset adjustment. +//! +//! This function takes a measured ADC value compensates for the internal gain +//! and offset in the ADC. +//! +//! \param adcValue +//! 12-bit ADC unadjusted value +//! \param gain +//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain() +//! \param offset +//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset() +//! +//! \return +//! 12-bit ADC adjusted value +// +//***************************************************************************** +extern int32_t AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset); + +//***************************************************************************** +// +//! \brief Performs the inverse of the ADC value gain and offset adjustment. +//! +//! This function finds the expected measured ADC value, without gain and +//! offset compensation, for a given "ideal" ADC value. The function can for +//! example be used to find ADC value thresholds to be used in Sensor +//! Controller task configurations. +//! +//! \param adcValue +//! 12-bit ADC adjusted value +//! \param gain +//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain() +//! \param offset +//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset() +//! +//! \return +//! 12-bit ADC unadjusted value +// +//***************************************************************************** +extern int32_t AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXADCDisable + #undef AUXADCDisable + #define AUXADCDisable ROM_AUXADCDisable + #endif + #ifdef ROM_AUXADCEnableAsync + #undef AUXADCEnableAsync + #define AUXADCEnableAsync ROM_AUXADCEnableAsync + #endif + #ifdef ROM_AUXADCEnableSync + #undef AUXADCEnableSync + #define AUXADCEnableSync ROM_AUXADCEnableSync + #endif + #ifdef ROM_AUXADCDisableInputScaling + #undef AUXADCDisableInputScaling + #define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling + #endif + #ifdef ROM_AUXADCFlushFifo + #undef AUXADCFlushFifo + #define AUXADCFlushFifo ROM_AUXADCFlushFifo + #endif + #ifdef ROM_AUXADCReadFifo + #undef AUXADCReadFifo + #define AUXADCReadFifo ROM_AUXADCReadFifo + #endif + #ifdef ROM_AUXADCPopFifo + #undef AUXADCPopFifo + #define AUXADCPopFifo ROM_AUXADCPopFifo + #endif + #ifdef ROM_AUXADCGetAdjustmentGain + #undef AUXADCGetAdjustmentGain + #define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain + #endif + #ifdef ROM_AUXADCGetAdjustmentOffset + #undef AUXADCGetAdjustmentOffset + #define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset + #endif + #ifdef ROM_AUXADCValueToMicrovolts + #undef AUXADCValueToMicrovolts + #define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts + #endif + #ifdef ROM_AUXADCMicrovoltsToValue + #undef AUXADCMicrovoltsToValue + #define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue + #endif + #ifdef ROM_AUXADCAdjustValueForGainAndOffset + #undef AUXADCAdjustValueForGainAndOffset + #define AUXADCAdjustValueForGainAndOffset ROM_AUXADCAdjustValueForGainAndOffset + #endif + #ifdef ROM_AUXADCUnadjustValueForGainAndOffset + #undef AUXADCUnadjustValueForGainAndOffset + #define AUXADCUnadjustValueForGainAndOffset ROM_AUXADCUnadjustValueForGainAndOffset + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_ADC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.c new file mode 100644 index 0000000..76dc0b1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: aux_smph.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the AUX Semaphore. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_smph.h" + +// See aux_smph.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.h new file mode 100644 index 0000000..4ff1314 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.h @@ -0,0 +1,258 @@ +/****************************************************************************** +* Filename: aux_smph.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the AUX Semaphore +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxsmph_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_SMPH_H__ +#define __AUX_SMPH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_aux_smph.h" +#include "../inc/hw_memmap.h" +#include "debug.h" + +//***************************************************************************** +// +// General constants and defines +// +//***************************************************************************** +#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed + +//***************************************************************************** +// +// Values that can be passed to AUXSMPHAcquire and AUXSMPHRelease +// as the ui32Semaphore parameter. +// +//***************************************************************************** +#define AUX_SMPH_0 0 // AUX Semaphore 0 +#define AUX_SMPH_1 1 // AUX Semaphore 1 +#define AUX_SMPH_2 2 // AUX Semaphore 2 +#define AUX_SMPH_3 3 // AUX Semaphore 3 +#define AUX_SMPH_4 4 // AUX Semaphore 4 +#define AUX_SMPH_5 5 // AUX Semaphore 5 +#define AUX_SMPH_6 6 // AUX Semaphore 6 +#define AUX_SMPH_7 7 // AUX Semaphore 7 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Acquire an AUX semaphore. +//! +//! This function acquires the given AUX semaphore, blocking the call until +//! the semaphore is available. +//! +//! \note The semaphore can also be acquired by the dedicated Sensor Controller. +//! The System CPU master can thus be competing for the shared resource, i.e. +//! the specified semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref AUX_SMPH_0 +//! - \ref AUX_SMPH_1 +//! - \ref AUX_SMPH_2 +//! - \ref AUX_SMPH_3 +//! - \ref AUX_SMPH_4 +//! - \ref AUX_SMPH_5 +//! - \ref AUX_SMPH_6 +//! - \ref AUX_SMPH_7 +//! +//! \return None +//! +//! \sa AUXSMPHTryAcquire(), AUXSMPHRelease() +// +//***************************************************************************** +__STATIC_INLINE void +AUXSMPHAcquire(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == AUX_SMPH_0) || + (ui32Semaphore == AUX_SMPH_1) || + (ui32Semaphore == AUX_SMPH_2) || + (ui32Semaphore == AUX_SMPH_3) || + (ui32Semaphore == AUX_SMPH_4) || + (ui32Semaphore == AUX_SMPH_5) || + (ui32Semaphore == AUX_SMPH_6) || + (ui32Semaphore == AUX_SMPH_7)); + + // Wait for semaphore to be released such that it can be claimed + // Semaphore register reads 1 when lock was acquired otherwise 0 + // (i.e. AUX_SMPH_CLAIMED). + while(HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) == + AUX_SMPH_CLAIMED) + { + } +} + +//***************************************************************************** +// +//! \brief Try to acquire an AUX semaphore. +//! +//! This function tries to acquire the given AUX semaphore, if the semaphore +//! could not be claimed the function returns false. +//! +//! \note The semaphore can also be acquired by the dedicated Sensor Controller. +//! The System CPU master can thus be competing for the shared resource, i.e. +//! the specified semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref AUX_SMPH_0 +//! - \ref AUX_SMPH_1 +//! - \ref AUX_SMPH_2 +//! - \ref AUX_SMPH_3 +//! - \ref AUX_SMPH_4 +//! - \ref AUX_SMPH_5 +//! - \ref AUX_SMPH_6 +//! - \ref AUX_SMPH_7 +//! +//! \return Returns true if semaphore was acquired, false otherwise +//! +//! \sa AUXSMPHAcquire(), AUXSMPHRelease() +// +//***************************************************************************** +__STATIC_INLINE bool +AUXSMPHTryAcquire(uint32_t ui32Semaphore) +{ + uint32_t ui32SemaReg; + + // Check the arguments. + ASSERT((ui32Semaphore == AUX_SMPH_0) || + (ui32Semaphore == AUX_SMPH_1) || + (ui32Semaphore == AUX_SMPH_2) || + (ui32Semaphore == AUX_SMPH_3) || + (ui32Semaphore == AUX_SMPH_4) || + (ui32Semaphore == AUX_SMPH_5) || + (ui32Semaphore == AUX_SMPH_6) || + (ui32Semaphore == AUX_SMPH_7)); + + // AUX Semaphore register reads 1 if lock was acquired + // (i.e. SMPH_FREE when read) but subsequent reads will read 0. + ui32SemaReg = HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore); + + return (ui32SemaReg == AUX_SMPH_FREE); +} + +//***************************************************************************** +// +//! \brief Release an AUX semaphore by System CPU master. +//! +//! This function releases the given AUX semaphore. +//! +//! \note It is up to the application to provide the convention for clearing +//! semaphore. +//! +//! \note The semaphore can also be acquired by the dedicated Sensor Controller. +//! The System CPU master can thus be competing for the shared resource, i.e. +//! the specified semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref AUX_SMPH_0 +//! - \ref AUX_SMPH_1 +//! - \ref AUX_SMPH_2 +//! - \ref AUX_SMPH_3 +//! - \ref AUX_SMPH_4 +//! - \ref AUX_SMPH_5 +//! - \ref AUX_SMPH_6 +//! - \ref AUX_SMPH_7 +//! +//! \return None +//! +//! \sa AUXSMPHAcquire(), AUXSMPHTryAcquire() +// +//***************************************************************************** +__STATIC_INLINE void +AUXSMPHRelease(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == AUX_SMPH_0) || + (ui32Semaphore == AUX_SMPH_1) || + (ui32Semaphore == AUX_SMPH_2) || + (ui32Semaphore == AUX_SMPH_3) || + (ui32Semaphore == AUX_SMPH_4) || + (ui32Semaphore == AUX_SMPH_5) || + (ui32Semaphore == AUX_SMPH_6) || + (ui32Semaphore == AUX_SMPH_7)); + + // No check before release. It is up to the application to provide the + // conventions for who and when a semaphore can be released. + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) = + AUX_SMPH_FREE; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_SMPH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.c new file mode 100644 index 0000000..b20a265 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.c @@ -0,0 +1,96 @@ +/****************************************************************************** +* Filename: aux_sysif.c +* Revised: 2018-04-17 14:54:06 +0200 (Tue, 17 Apr 2018) +* Revision: 51890 +* +* Description: Driver for the AUX System Interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_sysif.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXSYSIFOpModeChange + #define AUXSYSIFOpModeChange NOROM_AUXSYSIFOpModeChange +#endif + + +//***************************************************************************** +// +// Used in AUXSYSIFOpModeChange() to control the change of the operational mode. +// +//***************************************************************************** +static const uint8_t g_OpMode_to_order[4] = {1,2,0,3}; +static const uint8_t g_Order_to_OpMode[4] = {2,0,1,3}; + +//***************************************************************************** +// +// Controls AUX operational mode change +// +//***************************************************************************** +void +AUXSYSIFOpModeChange(uint32_t targetOpMode) +{ + uint32_t currentOpMode; + uint32_t currentOrder; + uint32_t nextMode; + + // Check the argument + ASSERT((targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_PDLP)|| + (targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_PDA) || + (targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_LP) || + (targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_A)); + + do { + currentOpMode = HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEREQ); + while ( currentOpMode != HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEACK)); + if (currentOpMode != targetOpMode) + { + currentOrder = g_OpMode_to_order[currentOpMode]; + if ( currentOrder < g_OpMode_to_order[targetOpMode]) + { + nextMode = g_Order_to_OpMode[currentOrder + 1]; + } + else + { + nextMode = g_Order_to_OpMode[currentOrder - 1]; + } + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEREQ) = nextMode; + } + } while ( currentOpMode != targetOpMode ); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.h new file mode 100644 index 0000000..41910da --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.h @@ -0,0 +1,154 @@ +/****************************************************************************** +* Filename: aux_sysif.h +* Revised: 2017-06-27 08:41:49 +0200 (Tue, 27 Jun 2017) +* Revision: 49245 +* +* Description: Defines and prototypes for the AUX System Interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxsysif_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_SYSIF_H__ +#define __AUX_SYSIF_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aux_sysif.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXSYSIFOpModeChange NOROM_AUXSYSIFOpModeChange +#endif + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +// Defines for AUX operational modes. +// +//***************************************************************************** +#define AUX_SYSIF_OPMODE_TARGET_PDLP (AUX_SYSIF_OPMODEREQ_REQ_PDLP) +#define AUX_SYSIF_OPMODE_TARGET_PDA (AUX_SYSIF_OPMODEREQ_REQ_PDA) +#define AUX_SYSIF_OPMODE_TARGET_LP (AUX_SYSIF_OPMODEREQ_REQ_LP) +#define AUX_SYSIF_OPMODE_TARGET_A (AUX_SYSIF_OPMODEREQ_REQ_A) + +//***************************************************************************** +// +//! \brief Changes the AUX operational mode to the requested target mode. +//! +//! This function controls the change of the AUX operational mode. +//! The function controls the change of the current operational mode to the +//! operational mode target by adhering to rules specified by HW. +//! +//! \param targetOpMode +//! AUX operational mode: +//! - \ref AUX_SYSIF_OPMODE_TARGET_PDLP (Powerdown operational mode with wakeup to lowpower mode) +//! - \ref AUX_SYSIF_OPMODE_TARGET_PDA (Powerdown operational mode with wakeup to active mode) +//! - \ref AUX_SYSIF_OPMODE_TARGET_LP (Lowpower operational mode) +//! - \ref AUX_SYSIF_OPMODE_TARGET_A (Active operational mode) +//! +//! \return None +// +//***************************************************************************** +extern void AUXSYSIFOpModeChange(uint32_t targetOpMode); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXSYSIFOpModeChange + #undef AUXSYSIFOpModeChange + #define AUXSYSIFOpModeChange ROM_AUXSYSIFOpModeChange + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_SYSIF_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.c new file mode 100644 index 0000000..4e6993e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.c @@ -0,0 +1,111 @@ +/****************************************************************************** +* Filename: aux_tdc.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the AUX Time to Digital Converter interface. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_tdc.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXTDCConfigSet + #define AUXTDCConfigSet NOROM_AUXTDCConfigSet + #undef AUXTDCMeasurementDone + #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone +#endif + +//***************************************************************************** +// +// Configure the operation of the AUX TDC +// +//***************************************************************************** +void +AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, + uint32_t ui32StopCondition) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Make sure the AUX TDC is in the idle state before changing the + // configuration. + while(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + } + + // Clear previous results. + HWREG(ui32Base + AUX_TDC_O_CTL) = 0x0; + + // Change the configuration. + HWREG(ui32Base + AUX_TDC_O_TRIGSRC) = ui32StartCondition | ui32StopCondition; +} + +//***************************************************************************** +// +// Check if the AUX TDC is done measuring +// +//***************************************************************************** +uint32_t +AUXTDCMeasurementDone(uint32_t ui32Base) +{ + uint32_t ui32Reg; + uint32_t ui32Status; + + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is done measuring. + ui32Reg = HWREG(ui32Base + AUX_TDC_O_STAT); + if(ui32Reg & AUX_TDC_STAT_DONE) + { + ui32Status = AUX_TDC_DONE; + } + else if(ui32Reg & AUX_TDC_STAT_SAT) + { + ui32Status = AUX_TDC_TIMEOUT; + } + else + { + ui32Status = AUX_TDC_BUSY; + } + + // Return the status. + return (ui32Status); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h new file mode 100644 index 0000000..10f3b41 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h @@ -0,0 +1,904 @@ +/****************************************************************************** +* Filename: aux_tdc.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Defines and prototypes for the AUX Time-to-Digital Converter +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxtdc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_TDC_H__ +#define __AUX_TDC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aux_tdc.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXTDCConfigSet NOROM_AUXTDCConfigSet + #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone +#endif + +//***************************************************************************** +// +// Defines for the status of a AUX TDC measurement. +// +//***************************************************************************** +#define AUX_TDC_BUSY 0x00000001 +#define AUX_TDC_TIMEOUT 0x00000002 +#define AUX_TDC_DONE 0x00000004 + +//***************************************************************************** +// +// Defines for the control of a AUX TDC. +// +//***************************************************************************** +#define AUX_TDC_RUNSYNC 0x00000001 +#define AUX_TDC_RUN 0x00000002 +#define AUX_TDC_ABORT 0x00000003 + +//***************************************************************************** +// +// Defines for possible states of the TDC internal state machine. +// +//***************************************************************************** +#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START) +#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN) +#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE) +#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT) +#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP) +#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN) +#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT) +#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR) +#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE) +#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL) +#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP) + +//***************************************************************************** +// +// Defines for controlling the AUX TDC. Values can be passed to AUXTDCConfigSet(). +// +//***************************************************************************** +#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event +#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event + +#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0) +#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1) +#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2) +#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3) +#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4) +#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5) +#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6) +#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7) +#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8) +#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9) +#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10) +#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11) +#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12) +#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13) +#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14) +#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15) +#define AUXTDC_STOP_AUXIO16 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16) +#define AUXTDC_STOP_AUXIO17 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17) +#define AUXTDC_STOP_AUXIO18 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18) +#define AUXTDC_STOP_AUXIO19 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19) +#define AUXTDC_STOP_AUXIO20 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20) +#define AUXTDC_STOP_AUXIO21 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21) +#define AUXTDC_STOP_AUXIO22 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22) +#define AUXTDC_STOP_AUXIO23 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23) +#define AUXTDC_STOP_AUXIO24 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24) +#define AUXTDC_STOP_AUXIO25 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25) +#define AUXTDC_STOP_AUXIO26 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26) +#define AUXTDC_STOP_AUXIO27 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27) +#define AUXTDC_STOP_AUXIO28 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28) +#define AUXTDC_STOP_AUXIO29 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29) +#define AUXTDC_STOP_AUXIO30 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30) +#define AUXTDC_STOP_AUXIO31 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31) +#define AUXTDC_STOP_MANUAL_EV (AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV) +#define AUXTDC_STOP_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY) +#define AUXTDC_STOP_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ) +#define AUXTDC_STOP_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD) +#define AUXTDC_STOP_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD) +#define AUXTDC_STOP_SCLK_LF (AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF) +#define AUXTDC_STOP_PWR_DWN (AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN) +#define AUXTDC_STOP_MCU_ACTIVE (AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE) +#define AUXTDC_STOP_VDDR_RECHARGE (AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE) +#define AUXTDC_STOP_TIMER2_EV0 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0) +#define AUXTDC_STOP_TIMER2_EV1 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1) +#define AUXTDC_STOP_TIMER2_EV2 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2) +#define AUXTDC_STOP_TIMER2_EV3 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3) +#define AUXTDC_STOP_TIMER2_PULSE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE) +#define AUXTDC_STOP_TDC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE) +#define AUXTDC_STOP_ADC_IRQ (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ) +#define AUXTDC_STOP_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY) +#define AUXTDC_STOP_NO_EVENT (AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT) +#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE) +#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL) +#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N) +#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0) +#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1) +#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE) +#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE) +#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV) +#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV) +#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2) +#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA) +#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB) +#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF) +#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV) + +#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event +#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event + +#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0) +#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1) +#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2) +#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3) +#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4) +#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5) +#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6) +#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7) +#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8) +#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9) +#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10) +#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11) +#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12) +#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13) +#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14) +#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15) +#define AUXTDC_START_AUXIO16 (AUX_TDC_TRIGSRC_START_SRC_AUXIO16) +#define AUXTDC_START_AUXIO17 (AUX_TDC_TRIGSRC_START_SRC_AUXIO17) +#define AUXTDC_START_AUXIO18 (AUX_TDC_TRIGSRC_START_SRC_AUXIO18) +#define AUXTDC_START_AUXIO19 (AUX_TDC_TRIGSRC_START_SRC_AUXIO19) +#define AUXTDC_START_AUXIO20 (AUX_TDC_TRIGSRC_START_SRC_AUXIO20) +#define AUXTDC_START_AUXIO21 (AUX_TDC_TRIGSRC_START_SRC_AUXIO21) +#define AUXTDC_START_AUXIO22 (AUX_TDC_TRIGSRC_START_SRC_AUXIO22) +#define AUXTDC_START_AUXIO23 (AUX_TDC_TRIGSRC_START_SRC_AUXIO23) +#define AUXTDC_START_AUXIO24 (AUX_TDC_TRIGSRC_START_SRC_AUXIO24) +#define AUXTDC_START_AUXIO25 (AUX_TDC_TRIGSRC_START_SRC_AUXIO25) +#define AUXTDC_START_AUXIO26 (AUX_TDC_TRIGSRC_START_SRC_AUXIO26) +#define AUXTDC_START_AUXIO27 (AUX_TDC_TRIGSRC_START_SRC_AUXIO27) +#define AUXTDC_START_AUXIO28 (AUX_TDC_TRIGSRC_START_SRC_AUXIO28) +#define AUXTDC_START_AUXIO29 (AUX_TDC_TRIGSRC_START_SRC_AUXIO29) +#define AUXTDC_START_AUXIO30 (AUX_TDC_TRIGSRC_START_SRC_AUXIO30) +#define AUXTDC_START_AUXIO31 (AUX_TDC_TRIGSRC_START_SRC_AUXIO31) +#define AUXTDC_START_MANUAL_EV (AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV) +#define AUXTDC_START_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY) +#define AUXTDC_START_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ) +#define AUXTDC_START_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD) +#define AUXTDC_START_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD) +#define AUXTDC_START_SCLK_LF (AUX_TDC_TRIGSRC_START_SRC_SCLK_LF) +#define AUXTDC_START_PWR_DWN (AUX_TDC_TRIGSRC_START_SRC_PWR_DWN) +#define AUXTDC_START_MCU_ACTIVE (AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE) +#define AUXTDC_START_VDDR_RECHARGE (AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE) +#define AUXTDC_START_TIMER2_EV0 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0) +#define AUXTDC_START_TIMER2_EV1 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1) +#define AUXTDC_START_TIMER2_EV2 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2) +#define AUXTDC_START_TIMER2_EV3 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3) +#define AUXTDC_START_TIMER2_PULSE (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE) +#define AUXTDC_START_TDC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE) +#define AUXTDC_START_ADC_IRQ (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ) +#define AUXTDC_START_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY) +#define AUXTDC_START_NO_EVENT (AUX_TDC_TRIGSRC_START_SRC_NO_EVENT) +#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE) +#define AUXTDC_START_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_ALMOST_FULL) +#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N) +#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0) +#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1) +#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE) +#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE) +#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV) +#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV) +#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2) +#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA) +#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB) +#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF) +#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV) + +//***************************************************************************** +// +// Defines for the possible saturation values set using AUXTDCLimitSet(). +// +//***************************************************************************** +#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12) +#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13) +#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14) +#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15) +#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16) +#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17) +#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18) +#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19) +#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20) +#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21) +#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22) +#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23) +#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24) +#define AUXTDC_NUM_SAT_VALS 16 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! \brief Checks an AUX TDC base address. +//! +//! This function determines if a AUX TDC port base address is valid. +//! +//! \param ui32Base is the base address of the AUX TDC port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +AUXTDCBaseValid(uint32_t ui32Base) +{ + return(ui32Base == AUX_TDC_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Get the status of the AUX TDC internal state machine. +//! +//! This function will return the current state of the AUX TDC internal state +//! machine. +//! \param ui32Base is base address of the AUX TDC +//! +//! \return Returns the current state of the state machine. +//! Possible states for the state machine are: +//! - \ref AUXTDC_WAIT_START +//! - \ref AUXTDC_WAIT_START_CNTEN +//! - \ref AUXTDC_IDLE +//! - \ref AUXTDC_CLRCNT +//! - \ref AUXTDC_WAIT_STOP +//! - \ref AUXTDC_WAIT_STOP_CNTDOWN +//! - \ref AUXTDC_GETRESULTS +//! - \ref AUXTDC_POR +//! - \ref AUXTDC_WAIT_CLRCNT_DONE +//! - \ref AUXTDC_START_FALL +//! - \ref AUXTDC_FORCE_STOP. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCStatusGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the status value for the correct ADI Slave. + return((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) >> + AUX_TDC_STAT_STATE_S); +} + +//***************************************************************************** +// +//! \brief Configure the operation of the AUX TDC. +//! +//! Use this function to configure the start and stop event for the AUX TDC. +//! +//! The \c ui32StartCondition must be a bitwise OR of the start event and the +//! polarity of the start event. The start events are: +//! - \ref AUXTDC_START_AUXIO0 +//! - \ref AUXTDC_START_AUXIO1 +//! - \ref AUXTDC_START_AUXIO2 +//! - \ref AUXTDC_START_AUXIO3 +//! - \ref AUXTDC_START_AUXIO4 +//! - \ref AUXTDC_START_AUXIO5 +//! - \ref AUXTDC_START_AUXIO6 +//! - \ref AUXTDC_START_AUXIO7 +//! - \ref AUXTDC_START_AUXIO8 +//! - \ref AUXTDC_START_AUXIO9 +//! - \ref AUXTDC_START_AUXIO10 +//! - \ref AUXTDC_START_AUXIO11 +//! - \ref AUXTDC_START_AUXIO12 +//! - \ref AUXTDC_START_AUXIO13 +//! - \ref AUXTDC_START_AUXIO14 +//! - \ref AUXTDC_START_AUXIO15 +//! - \ref AUXTDC_START_AUXIO16 +//! - \ref AUXTDC_START_AUXIO17 +//! - \ref AUXTDC_START_AUXIO18 +//! - \ref AUXTDC_START_AUXIO19 +//! - \ref AUXTDC_START_AUXIO20 +//! - \ref AUXTDC_START_AUXIO21 +//! - \ref AUXTDC_START_AUXIO22 +//! - \ref AUXTDC_START_AUXIO23 +//! - \ref AUXTDC_START_AUXIO24 +//! - \ref AUXTDC_START_AUXIO25 +//! - \ref AUXTDC_START_AUXIO26 +//! - \ref AUXTDC_START_AUXIO27 +//! - \ref AUXTDC_START_AUXIO28 +//! - \ref AUXTDC_START_AUXIO29 +//! - \ref AUXTDC_START_AUXIO30 +//! - \ref AUXTDC_START_AUXIO31 +//! - \ref AUXTDC_START_MANUAL_EV +//! - \ref AUXTDC_START_AON_RTC_CH2_DLY +//! - \ref AUXTDC_START_AON_RTC_4KHZ +//! - \ref AUXTDC_START_AON_BATMON_BAT_UPD +//! - \ref AUXTDC_START_AON_BATMON_TEMP_UPD +//! - \ref AUXTDC_START_SCLK_LF +//! - \ref AUXTDC_START_PWR_DWN +//! - \ref AUXTDC_START_MCU_ACTIVE +//! - \ref AUXTDC_START_VDDR_RECHARGE +//! - \ref AUXTDC_START_TIMER2_EV0 +//! - \ref AUXTDC_START_TIMER2_EV1 +//! - \ref AUXTDC_START_TIMER2_EV2 +//! - \ref AUXTDC_START_TIMER2_EV3 +//! - \ref AUXTDC_START_TIMER2_PULSE +//! - \ref AUXTDC_START_TDC_DONE +//! - \ref AUXTDC_START_ADC_IRQ +//! - \ref AUXTDC_START_ADC_FIFO_NOT_EMPTY +//! - \ref AUXTDC_START_NO_EVENT +//! - \ref AUXTDC_START_ADC_DONE +//! - \ref AUXTDC_START_ADC_FIFO_ALMOST_FULL +//! - \ref AUXTDC_START_ISRC_RESET +//! - \ref AUXTDC_START_OBSMUX0 +//! - \ref AUXTDC_START_OBSMUX1 +//! - \ref AUXTDC_START_SMPH_AUTOTAKE_DONE +//! - \ref AUXTDC_START_TDC_PRE +//! - \ref AUXTDC_START_TIMER0_EV +//! - \ref AUXTDC_START_TIMER1_EV +//! - \ref AUXTDC_START_AON_RTC_CH2 +//! - \ref AUXTDC_START_AUX_COMPA +//! - \ref AUXTDC_START_AUX_COMPB +//! - \ref AUXTDC_START_ACLK_REF +//! - \ref AUXTDC_START_MCU_EV +//! +//! The polarity of the start event is either rising \ref AUXTDC_STARTPOL_RIS +//! or falling \ref AUXTDC_STARTPOL_FALL. +//! +//! The \c ui32StopCondition must be a bitwise OR of the stop event and the +//! polarity of the stop event. The stop events are: +//! - \ref AUXTDC_STOP_AUXIO0 +//! - \ref AUXTDC_STOP_AUXIO1 +//! - \ref AUXTDC_STOP_AUXIO2 +//! - \ref AUXTDC_STOP_AUXIO3 +//! - \ref AUXTDC_STOP_AUXIO4 +//! - \ref AUXTDC_STOP_AUXIO5 +//! - \ref AUXTDC_STOP_AUXIO6 +//! - \ref AUXTDC_STOP_AUXIO7 +//! - \ref AUXTDC_STOP_AUXIO8 +//! - \ref AUXTDC_STOP_AUXIO9 +//! - \ref AUXTDC_STOP_AUXIO10 +//! - \ref AUXTDC_STOP_AUXIO11 +//! - \ref AUXTDC_STOP_AUXIO12 +//! - \ref AUXTDC_STOP_AUXIO13 +//! - \ref AUXTDC_STOP_AUXIO14 +//! - \ref AUXTDC_STOP_AUXIO15 +//! - \ref AUXTDC_STOP_AUXIO16 +//! - \ref AUXTDC_STOP_AUXIO17 +//! - \ref AUXTDC_STOP_AUXIO18 +//! - \ref AUXTDC_STOP_AUXIO19 +//! - \ref AUXTDC_STOP_AUXIO20 +//! - \ref AUXTDC_STOP_AUXIO21 +//! - \ref AUXTDC_STOP_AUXIO22 +//! - \ref AUXTDC_STOP_AUXIO23 +//! - \ref AUXTDC_STOP_AUXIO24 +//! - \ref AUXTDC_STOP_AUXIO25 +//! - \ref AUXTDC_STOP_AUXIO26 +//! - \ref AUXTDC_STOP_AUXIO27 +//! - \ref AUXTDC_STOP_AUXIO28 +//! - \ref AUXTDC_STOP_AUXIO29 +//! - \ref AUXTDC_STOP_AUXIO30 +//! - \ref AUXTDC_STOP_AUXIO31 +//! - \ref AUXTDC_STOP_MANUAL_EV +//! - \ref AUXTDC_STOP_AON_RTC_CH2_DLY +//! - \ref AUXTDC_STOP_AON_RTC_4KHZ +//! - \ref AUXTDC_STOP_AON_BATMON_BAT_UPD +//! - \ref AUXTDC_STOP_AON_BATMON_TEMP_UPD +//! - \ref AUXTDC_STOP_SCLK_LF +//! - \ref AUXTDC_STOP_PWR_DWN +//! - \ref AUXTDC_STOP_MCU_ACTIVE +//! - \ref AUXTDC_STOP_VDDR_RECHARGE +//! - \ref AUXTDC_STOP_TIMER2_EV0 +//! - \ref AUXTDC_STOP_TIMER2_EV1 +//! - \ref AUXTDC_STOP_TIMER2_EV2 +//! - \ref AUXTDC_STOP_TIMER2_EV3 +//! - \ref AUXTDC_STOP_TIMER2_PULSE +//! - \ref AUXTDC_STOP_TDC_DONE +//! - \ref AUXTDC_STOP_ADC_IRQ +//! - \ref AUXTDC_STOP_ADC_FIFO_NOT_EMPTY +//! - \ref AUXTDC_STOP_NO_EVENT +//! - \ref AUXTDC_STOP_ADC_DONE +//! - \ref AUXTDC_STOP_ADC_FIFO_ALMOST_FULL +//! - \ref AUXTDC_STOP_ISRC_RESET +//! - \ref AUXTDC_STOP_OBSMUX0 +//! - \ref AUXTDC_STOP_OBSMUX1 +//! - \ref AUXTDC_STOP_SMPH_AUTOTAKE_DONE +//! - \ref AUXTDC_STOP_TDC_PRE +//! - \ref AUXTDC_STOP_TIMER0_EV +//! - \ref AUXTDC_STOP_TIMER1_EV +//! - \ref AUXTDC_STOP_AON_RTC_CH2 +//! - \ref AUXTDC_STOP_AUX_COMPA +//! - \ref AUXTDC_STOP_AUX_COMPB +//! - \ref AUXTDC_STOP_ACLK_REF +//! - \ref AUXTDC_STOP_MCU_EV +//! +//! The polarity of the stop event is either rising \ref AUXTDC_STOPPOL_RIS +//! or falling \ref AUXTDC_STOPPOL_FALL. +//! +//! \note The AUX TDC should only be configured when the AUX TDC is in the Idle +//! state. To ensure that software does not lock up, it is recommended to +//! ensure that the AUX TDC is actually in idle when calling \ref AUXTDCConfigSet(). +//! This can be tested using \ref AUXTDCIdle(). +//! +//! \param ui32Base is base address of the AUX TDC. +//! \param ui32StartCondition is AUX TDC a bitwise OR of a start event and polarity. +//! \param ui32StopCondition is AUX TDC a bitwise OR of a stop event and polarity. +//! +//! \return None +//! +//! \sa \ref AUXTDCConfigSet(), \ref AUXTDCIdle() +// +//***************************************************************************** +extern void AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, + uint32_t ui32StopCondition); + +//***************************************************************************** +// +//! \brief Check if the AUX TDC is in idle mode. +//! +//! This function can be used to check whether the AUX TDC internal state +//! machine is in idle mode. This is required before setting the polarity +//! of the start and stop event. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return Returns \c true if state machine is in idle and returns \c false +//! if the state machine is in any other state. +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCIdle(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in the Idle state. + return (((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE) ? true : false); +} + +//***************************************************************************** +// +//! \brief Enable the AUX TDC for a measurement. +//! +//! This function is used for arming the AUX TDC to begin a measurement as +//! soon as the start condition is met. There are two run modes: +//! - \ref AUX_TDC_RUNSYNC will wait for a falling event of the start pulse before +//! starting measurement on next rising edge of start. This guarantees an edge +//! triggered start and is recommended for frequency measurements. If the +//! first falling edge is close to the start command it may be missed, but +//! the TDC shall catch later falling edges and in any case guarantee a +//! measurement start synchronous to the rising edge of the start event. +//! - The \ref AUX_TDC_RUN is asynchronous start and asynchronous stop mode. Using +//! this a TDC measurement may start immediately if start is high and hence it +//! may not give precise edge to edge measurements. This mode is only +//! recommended when start pulse is guaranteed to arrive at least 7 clock +//! periods after command. +//! +//! \note The AUX TDC should be configured and in Idle mode before calling this +//! function. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! \param ui32RunMode is the run mode for the AUX TDC. +//! - \ref AUX_TDC_RUNSYNC : Synchronous run mode. +//! - \ref AUX_TDC_RUN : Asynchronous run mode. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AUXTDCEnable(uint32_t ui32Base, uint32_t ui32RunMode) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + ASSERT((ui32RunMode == AUX_TDC_RUN) || + (ui32RunMode == AUX_TDC_RUNSYNC)); + + // Enable the AUX TDC. + HWREG(ui32Base + AUX_TDC_O_CTL) = ui32RunMode; +} + +//***************************************************************************** +// +//! \brief Force the AUX TDC back to Idle mode. +//! +//! This function will force the AUX TDC in Idle mode. The internal state +//! machine will not go directly to Idle mode, so it is left to the programmer to +//! ensure that the state machine is in Idle mode before doing any new +//! configuration. This can be checked using \ref AUXTDCIdle(). +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return None +//! +//! \sa \ref AUXTDCIdle() +// +//***************************************************************************** +__STATIC_INLINE void +AUXTDCIdleForce(uint32_t ui32Base) +{ + // Check the arguments + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Abort operation of AUX TDC and force into Idle mode. + HWREG(ui32Base + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_ABORT; +} + +//***************************************************************************** +// +//! \brief Check if the AUX TDC is done measuring. +//! +//! This function can be used to check whether the AUX TDC has finished a +//! measurement. The AUX TDC may have completed a measurement for two reasons. +//! Either it finish successfully \ref AUX_TDC_DONE or it failed due to a timeout +//! \ref AUX_TDC_TIMEOUT. If the AUX TDC is still measuring it this function +//! will return \ref AUX_TDC_BUSY. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return Returns the current status of a measurement: +//! - \ref AUX_TDC_DONE : An AUX TDC measurement finished successfully. +//! - \ref AUX_TDC_TIMEOUT : An AUX TDC measurement failed due to timeout. +//! - \ref AUX_TDC_BUSY : An AUX TDC measurement is being performed. +// +//***************************************************************************** +extern uint32_t AUXTDCMeasurementDone(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Get the value of the latest measurement. +//! +//! This function is used for retrieving the value of the latest measurement +//! performed by the AUX TDC. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return Returns the result of the latest measurement. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCMeasurementGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the measurement. + return (HWREG(ui32Base + AUX_TDC_O_RESULT)); +} + +//***************************************************************************** +// +//! \brief Set the saturation limit of the measurement. +//! +//! This function is used to set a saturation limit for the event accumulation +//! register. The saturation limit is defined as a bit width of the +//! accumulation register and therefore increases in power of 2. +//! +//! \param ui32Base is base address of the AUX TDC. +//! \param ui32Limit is the saturation limit. +//! - \ref AUXTDC_SAT_4096 +//! - \ref AUXTDC_SAT_8192 +//! - \ref AUXTDC_SAT_16384 +//! - \ref AUXTDC_SAT_32768 +//! - \ref AUXTDC_SAT_65536 +//! - \ref AUXTDC_SAT_131072 +//! - \ref AUXTDC_SAT_262144 +//! - \ref AUXTDC_SAT_524288 +//! - \ref AUXTDC_SAT_1048576 +//! - \ref AUXTDC_SAT_2097152 +//! - \ref AUXTDC_SAT_4194304 +//! - \ref AUXTDC_SAT_8388608 +//! - \ref AUXTDC_SAT_16777216 (default) +//! +//! \return None +//! +//! \note The actual value of the accumulation register might increase slightly beyond +//! the saturation value before the saturation takes effect. +//! +//! \sa \ref AUXTDCLimitGet() +// +//***************************************************************************** +__STATIC_INLINE void +AUXTDCLimitSet(uint32_t ui32Base, uint32_t ui32Limit) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + ASSERT(ui32Limit < AUXTDC_NUM_SAT_VALS); + + // Set the saturation limit. + HWREG(ui32Base + AUX_TDC_O_SATCFG) = ui32Limit; +} + +//***************************************************************************** +// +//! \brief Get the saturation limit of the measurement. +//! +//! This function is used to retrieve the current saturation for the +//! accumulator register. +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns the saturation limit. +//! - \ref AUXTDC_SAT_4096 +//! - \ref AUXTDC_SAT_8192 +//! - \ref AUXTDC_SAT_16384 +//! - \ref AUXTDC_SAT_32768 +//! - \ref AUXTDC_SAT_65536 +//! - \ref AUXTDC_SAT_131072 +//! - \ref AUXTDC_SAT_262144 +//! - \ref AUXTDC_SAT_524288 +//! - \ref AUXTDC_SAT_1048576 +//! - \ref AUXTDC_SAT_2097152 +//! - \ref AUXTDC_SAT_4194304 +//! - \ref AUXTDC_SAT_8388608 +//! - \ref AUXTDC_SAT_16777216 +//! +//! \sa \ref AUXTDCLimitSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCLimitGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the saturation limit. + return (HWREG(ui32Base + AUX_TDC_O_SATCFG)); +} + +//***************************************************************************** +// +//! \brief Enables the counter if possible. +//! +//! This function can be used to enable the AUX TDC stop/compare event counter. +//! The counter can be used to measure multiple periods of a clock signal. +//! For each stop/compare event the counter will be decremented by one and +//! the measurement will continue running until the value of the counter +//! reaches 0. The current value of the counter can be read using +//! \ref AUXTDCCounterGet(). The reset value of the counter can be set using +//! \ref AUXTDCCounterSet(). +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns \c true if the counter was successfully enabled. If the +//! AUX TDC is not in Idle mode, the counter can not be enabled, and the +//! return value will be \c false. +//! +//! \sa \ref AUXTDCCounterGet(), \ref AUXTDCCounterSet() +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCCounterEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in idle mode. If not in Idle mode, the counter + // will not be enabled. + if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + return false; + } + + // Enable the counter. + HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = AUX_TDC_TRIGCNTCFG_EN; + + // Counter successfully enabled. + return true; +} + +//***************************************************************************** +// +//! \brief Disables the counter if possible. +//! +//! This function can be used to disable the AUX TDC stop/compare event counter. +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns \c true if the counter was successfully disabled. If the +//! AUX TDC is not in Idle mode, the counter can not be disabled, and the +//! return value will be \c false. +//! +//! \sa \ref AUXTDCCounterEnable() for more information on how to use the counter. +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCCounterDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in Idle mode. If not in Idle mode, the counter + // will not be disabled. + if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + return false; + } + + // Disable the counter. + HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = 0; + + // Counter successfully disabled. + return true; +} + +//***************************************************************************** +// +//! \brief Set the reset number of counter compare/stop event to ignore before taking +//! a measurement. +//! +//! This function loads the reset value of the counter with the specified +//! number of events to ignore. A reset in this context means the counter +//! has been disabled and then enabled. +//! +//! \param ui32Base is base address of the AUX TDC. +//! \param ui32Events is the number of compare/stop events to load into the +//! counter. +//! +//! \return Returns \c true if the counter was successfully updated. If the +//! AUX TDC is not in Idle mode, the counter can not be updated, and the +//! return value will be \c false. +//! +//! \sa \ref AUXTDCCounterEnable() +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCCounterSet(uint32_t ui32Base, uint32_t ui32Events) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in idle mode. If not in idle mode, the counter + // will not be disabled. + if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + return false; + } + + // Update the reset counter value. + HWREG(ui32Base + AUX_TDC_O_TRIGCNTLOAD) = ui32Events; + + // Counter successfully updated. + return true; +} + +//***************************************************************************** +// +//! \brief Get the current number of counter compare/stop event to ignore before +//! taking a measurement. +//! +//! This function returns the current value of compare/stop events before +//! a measurement is registered. This value is decremented by one for each +//! registered compare/stop event and will always be less than or equal the +//! reset value of the counter set using \ref AUXTDCCounterSet(). +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns the current value of compare/stop events ignored before a +//! measurement is performed. +//! +//! \sa \ref AUXTDCCounterEnable(). +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCCounterGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the current counter value. + return (HWREG(ui32Base + AUX_TDC_O_TRIGCNT)); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXTDCConfigSet + #undef AUXTDCConfigSet + #define AUXTDCConfigSet ROM_AUXTDCConfigSet + #endif + #ifdef ROM_AUXTDCMeasurementDone + #undef AUXTDCMeasurementDone + #define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_TDC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/bin/gcc/driverlib.lib b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/bin/gcc/driverlib.lib new file mode 100644 index 0000000..d78e134 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/bin/gcc/driverlib.lib differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/bin/iar/driverlib.lib b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/bin/iar/driverlib.lib new file mode 100644 index 0000000..06fd588 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/bin/iar/driverlib.lib differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.c new file mode 100644 index 0000000..c50f42f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: ccfgread.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: API for reading CCFG. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ccfgread.h" + +// See ccfgread.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.h new file mode 100644 index 0000000..e3397e9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.h @@ -0,0 +1,187 @@ +/****************************************************************************** +* Filename: ccfgread.h +* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) +* Revision: 47152 +* +* Description: API for reading CCFG. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup ccfgread_api +//! @{ +// +//***************************************************************************** + +#ifndef __CCFGREAD_H__ +#define __CCFGREAD_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ccfg.h" + +//***************************************************************************** +// +// General constants and defines +// +//***************************************************************************** + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Read DIS_GPRAM from CCFG. +//! +//! \return Value of CCFG field CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM +// +//***************************************************************************** +__STATIC_INLINE bool +CCFGRead_DIS_GPRAM( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) >> + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) ; +} + +//***************************************************************************** +// +//! \brief Read EXT_LF_CLK_DIO from CCFG. +//! +//! \return Value of CCFG field CCFG_EXT_LF_CLK_DIO +// +//***************************************************************************** +__STATIC_INLINE bool +CCFGRead_EXT_LF_CLK_DIO( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ) & + CCFG_EXT_LF_CLK_DIO_M ) >> + CCFG_EXT_LF_CLK_DIO_S ) ; +} + +//***************************************************************************** +// +// Defines the possible values returned from CCFGRead_SCLK_LF_OPTION() +// +//***************************************************************************** +#define CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_RCOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) + +//***************************************************************************** +// +//! \brief Read SCLK_LF_OPTION from CCFG. +//! +//! \return Returns the value of the CCFG field CCFG_MODE_CONF_SCLK_LF_OPTION field. +//! Returns one of the following: +//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF +//! - \ref CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF +//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_LF +//! - \ref CCFGREAD_SCLK_LF_OPTION_RCOSC_LF +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CCFGRead_SCLK_LF_OPTION( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & + CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> + CCFG_MODE_CONF_SCLK_LF_OPTION_S ) ; +} + +//***************************************************************************** +// +// Defines the possible values returned from CCFGRead_XOSC_FREQ() +// +//***************************************************************************** +#define CCFGREAD_XOSC_FREQ_24M ( CCFG_MODE_CONF_XOSC_FREQ_24M >> CCFG_MODE_CONF_XOSC_FREQ_S ) +#define CCFGREAD_XOSC_FREQ_48M ( CCFG_MODE_CONF_XOSC_FREQ_48M >> CCFG_MODE_CONF_XOSC_FREQ_S ) +#define CCFGREAD_XOSC_FREQ_HPOSC ( CCFG_MODE_CONF_XOSC_FREQ_HPOSC >> CCFG_MODE_CONF_XOSC_FREQ_S ) + +//***************************************************************************** +// +//! \brief Read XOSC_FREQ setting CCFG. +//! +//! \return Returns the value of the CCFG_MODE_CONF_XOSC_FREQ field. +//! Returns one of the following: +//! - \ref CCFGREAD_XOSC_FREQ_24M +//! - \ref CCFGREAD_XOSC_FREQ_48M +//! - \ref CCFGREAD_XOSC_FREQ_HPOSC +//! +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CCFGRead_XOSC_FREQ( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & + CCFG_MODE_CONF_XOSC_FREQ_M ) >> + CCFG_MODE_CONF_XOSC_FREQ_S ) ; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_SMPH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h new file mode 100644 index 0000000..f3175fb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h @@ -0,0 +1,51 @@ +/****************************************************************************** +* Filename: ccfgread_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup ccfgread_api +//! @{ +//! \section sec_ccfgread Introduction +//! +//! The values of customer configuration (CCFG) settings in flash are determined by ccfg.c and typically +//! a user application does not need to read these CCFG values as they are used mainly during ROM boot +//! and device trimming. However, a subset of the CCFG settings need to be read by application +//! code thus DriverLib provides this API to allow easy read access to these specific settings. +//! +//! The remaining settings not accessible through this API can of course be read directly at the CCFG +//! addresses in the flash (starting at CCFG_BASE) using the HWREG macro and the provided defines. +//! CCFG settings are documented as part of the register descriptions in the CPU memory map. +//! +//! \note CCFG settings are located in flash and should be considered read-only from an application +//! point-of-view. +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.c new file mode 100644 index 0000000..cf6e5e7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.c @@ -0,0 +1,210 @@ +/****************************************************************************** +* Filename: chipinfo.c +* Revised: 2018-08-17 09:28:06 +0200 (Fri, 17 Aug 2018) +* Revision: 52354 +* +* Description: Collection of functions returning chip information. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "chipinfo.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef ChipInfo_GetSupportedProtocol_BV + #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV + #undef ChipInfo_GetPackageType + #define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType + #undef ChipInfo_GetChipType + #define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType + #undef ChipInfo_GetChipFamily + #define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily + #undef ChipInfo_GetHwRevision + #define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision + #undef ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated + #define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated +#endif + +//***************************************************************************** +// +// ChipInfo_GetSupportedProtocol_BV() +// +//***************************************************************************** +ProtocolBitVector_t +ChipInfo_GetSupportedProtocol_BV( void ) +{ + return ((ProtocolBitVector_t)( HWREG( PRCM_BASE + 0x1D4 ) & 0x0E )); +} + +//***************************************************************************** +// +// ChipInfo_GetPackageType() +// +//***************************************************************************** +PackageType_t +ChipInfo_GetPackageType( void ) +{ + PackageType_t packType = (PackageType_t)(( + HWREG( FCFG1_BASE + FCFG1_O_USER_ID ) & + FCFG1_USER_ID_PKG_M ) >> + FCFG1_USER_ID_PKG_S ) ; + + if (( packType < PACKAGE_4x4 ) || + ( packType > PACKAGE_7x7_Q1 ) ) + { + packType = PACKAGE_Unknown; + } + + return ( packType ); +} + +//***************************************************************************** +// +// ChipInfo_GetChipFamily() +// +//***************************************************************************** +ChipFamily_t +ChipInfo_GetChipFamily( void ) +{ + uint32_t waferId ; + ChipFamily_t chipFam = FAMILY_Unknown ; + + waferId = (( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) & + FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M ) >> + FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S ) ; + + if ( waferId == 0xBB41 ) { + chipFam = FAMILY_CC13x2_CC26x2 ; + } + + return ( chipFam ); +} + +//***************************************************************************** +// +// ChipInfo_GetChipType() +// +//***************************************************************************** +ChipType_t +ChipInfo_GetChipType( void ) +{ + ChipType_t chipType = CHIP_TYPE_Unknown ; + ChipFamily_t chipFam = ChipInfo_GetChipFamily() ; + uint32_t fcfg1UserId = ChipInfo_GetUserId() ; + uint32_t fcfg1Protocol = (( fcfg1UserId & FCFG1_USER_ID_PROTOCOL_M ) >> + FCFG1_USER_ID_PROTOCOL_S ) ; + uint32_t fcfg1Cc13 = (( fcfg1UserId & FCFG1_USER_ID_CC13_M ) >> + FCFG1_USER_ID_CC13_S ) ; + uint32_t fcfg1Pa = (( fcfg1UserId & FCFG1_USER_ID_PA_M ) >> + FCFG1_USER_ID_PA_S ) ; + + if ( chipFam == FAMILY_CC13x2_CC26x2 ) { + switch ( fcfg1Protocol ) { + case 0xF : + if( fcfg1Cc13 ) { + if ( fcfg1Pa ) { + chipType = CHIP_TYPE_CC1352P ; + } else { + chipType = CHIP_TYPE_CC1352 ; + } + } else { + chipType = CHIP_TYPE_CC2652 ; + } + break; + case 0x9 : + if( fcfg1Pa ) { + chipType = CHIP_TYPE_unused ; + } else { + chipType = CHIP_TYPE_CC2642 ; + } + break; + case 0x8 : + chipType = CHIP_TYPE_CC1312 ; + break; + } + } + + return ( chipType ); +} + +//***************************************************************************** +// +// ChipInfo_GetHwRevision() +// +//***************************************************************************** +HwRevision_t +ChipInfo_GetHwRevision( void ) +{ + HwRevision_t hwRev = HWREV_Unknown ; + uint32_t fcfg1Rev = ChipInfo_GetDeviceIdHwRevCode() ; + uint32_t minorHwRev = ChipInfo_GetMinorHwRev() ; + ChipFamily_t chipFam = ChipInfo_GetChipFamily() ; + + if ( chipFam == FAMILY_CC13x2_CC26x2 ) { + switch ( fcfg1Rev ) { + case 0 : // CC13x2, CC26x2 - PG1.0 + case 1 : // CC13x2, CC26x2 - PG1.01 (will also show up as PG1.0) + hwRev = (HwRevision_t)((uint32_t)HWREV_1_0 ); + break; + case 2 : // CC13x2, CC26x2 - PG1.1 (or later) + hwRev = (HwRevision_t)(((uint32_t)HWREV_1_1 ) + minorHwRev ); + break; + case 3 : // CC13x2, CC26x2 - PG2.1 (or later) + hwRev = (HwRevision_t)(((uint32_t)HWREV_2_1 ) + minorHwRev ); + break; + } + } + + return ( hwRev ); +} + +//***************************************************************************** +// ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated() +//***************************************************************************** +void +ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated( void ) +{ + if (( ! ChipInfo_ChipFamilyIs_CC13x2_CC26x2() ) || + ( ! ChipInfo_HwRevisionIs_GTEQ_2_0() ) ) + { + while(1) + { + // This driverlib version is for the CC13x2/CC26x2 PG2.0 and later chips. + // Do nothing - stay here forever + } + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h new file mode 100644 index 0000000..788cfaf --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h @@ -0,0 +1,685 @@ +/****************************************************************************** +* Filename: chipinfo.h +* Revised: 2018-06-18 10:26:12 +0200 (Mon, 18 Jun 2018) +* Revision: 52189 +* +* Description: Collection of functions returning chip information. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup ChipInfo +//! @{ +// +//***************************************************************************** + +#ifndef __CHIP_INFO_H__ +#define __CHIP_INFO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_fcfg1.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV + #define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType + #define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType + #define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily + #define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision + #define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated +#endif + +//***************************************************************************** +// +//! \brief Enumeration identifying the protocols supported. +//! +//! \note +//! This is a bit vector enumeration that indicates supported protocols. +//! E.g: 0x06 means that the chip supports both BLE and IEEE 802.15.4 +// +//***************************************************************************** +typedef enum { + PROTOCOL_Unknown = 0 , //!< None of the known protocols are supported. + PROTOCOLBIT_BLE = 0x02, //!< Bit[1] set, indicates that Bluetooth Low Energy is supported. + PROTOCOLBIT_IEEE_802_15_4 = 0x04, //!< Bit[2] set, indicates that IEEE 802.15.4 is supported. + PROTOCOLBIT_Proprietary = 0x08 //!< Bit[3] set, indicates that proprietary protocols are supported. +} ProtocolBitVector_t; + +//***************************************************************************** +// +//! \brief Returns bit vector showing supported protocols. +//! +//! \return +//! Returns \ref ProtocolBitVector_t which is a bit vector indicating supported protocols. +// +//***************************************************************************** +extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV( void ); + +//***************************************************************************** +// +//! \brief Returns true if the chip supports the BLE protocol. +//! +//! \return +//! Returns \c true if supporting the BLE protocol, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_SupportsBLE( void ) +{ + return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_BLE ) != 0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if the chip supports the IEEE 802.15.4 protocol. +//! +//! \return +//! Returns \c true if supporting the IEEE 802.15.4 protocol, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_SupportsIEEE_802_15_4( void ) +{ + return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_IEEE_802_15_4 ) != 0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if the chip supports proprietary protocols. +//! +//! \return +//! Returns \c true if supporting proprietary protocols, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_SupportsPROPRIETARY( void ) +{ + return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_Proprietary ) != 0 ); +} + +//***************************************************************************** +// +//! \brief Package type enumeration +//! +//! \note +//! Packages available for a specific device are shown in the device datasheet. +// +//***************************************************************************** +typedef enum { + PACKAGE_Unknown = -1, //!< -1 means that current package type is unknown. + PACKAGE_4x4 = 0, //!< 0 means that this is a 4x4 mm QFN (RHB) package. + PACKAGE_5x5 = 1, //!< 1 means that this is a 5x5 mm QFN (RSM) package. + PACKAGE_7x7 = 2, //!< 2 means that this is a 7x7 mm QFN (RGZ) package. + PACKAGE_WAFER = 3, //!< 3 means that this is a wafer sale package (naked die). + PACKAGE_WCSP = 4, //!< 4 means that this is a 2.7x2.7 mm WCSP (YFV). + PACKAGE_7x7_Q1 = 5 //!< 5 means that this is a 7x7 mm QFN package with Wettable Flanks. +} PackageType_t; + +//***************************************************************************** +// +//! \brief Returns package type. +//! +//! \return +//! Returns \ref PackageType_t +// +//***************************************************************************** +extern PackageType_t ChipInfo_GetPackageType( void ); + +//***************************************************************************** +// +//! \brief Returns true if this is a 4x4mm chip. +//! +//! \return +//! Returns \c true if this is a 4x4mm chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs4x4( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_4x4 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a 5x5mm chip. +//! +//! \return +//! Returns \c true if this is a 5x5mm chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs5x5( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_5x5 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a 7x7mm chip. +//! +//! \return +//! Returns \c true if this is a 7x7mm chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs7x7( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_7x7 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a wafer sale chip (naked die). +//! +//! \return +//! Returns \c true if this is a wafer sale chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIsWAFER( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_WAFER ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a WCSP chip (flip chip). +//! +//! \return +//! Returns \c true if this is a WCSP chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIsWCSP( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_WCSP ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a 7x7 Q1 chip. +//! +//! \return +//! Returns \c true if this is a 7x7 Q1 chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs7x7Q1( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_7x7_Q1 ); +} + +//***************************************************************************** +// +//! \brief Returns the internal chip HW revision code. +//! +//! \return +//! Returns the internal chip HW revision code (in range 0-15) +//***************************************************************************** +__STATIC_INLINE uint32_t +ChipInfo_GetDeviceIdHwRevCode( void ) +{ + // Returns HwRevCode = FCFG1_O_ICEPICK_DEVICE_ID[31:28] + return ( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) >> 28 ); +} + +//***************************************************************************** +// +//! \brief Returns minor hardware revision number +//! +//! The minor revision number is set to 0 for the first market released chip +//! and thereafter incremented by 1 for each minor hardware change. +//! +//! \return +//! Returns the minor hardware revision number (in range 0-127) +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ChipInfo_GetMinorHwRev( void ) +{ + uint32_t minorRev = (( HWREG( FCFG1_BASE + FCFG1_O_MISC_CONF_1 ) & + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M ) >> + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S ) ; + + if ( minorRev >= 0x80 ) { + minorRev = 0; + } + + return( minorRev ); +} + +//***************************************************************************** +// +//! \brief Returns the 32 bits USER_ID field +//! +//! How to decode the USER_ID filed is described in the Technical Reference Manual (TRM) +//! +//! \return +//! Returns the 32 bits USER_ID field +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ChipInfo_GetUserId( void ) +{ + return ( HWREG( FCFG1_BASE + FCFG1_O_USER_ID )); +} + +//***************************************************************************** +// +//! \brief Chip type enumeration +// +//***************************************************************************** +typedef enum { + CHIP_TYPE_Unknown = -1, //!< -1 means that the chip type is unknown. + CHIP_TYPE_CC1310 = 0, //!< 0 means that this is a CC1310 chip. + CHIP_TYPE_CC1350 = 1, //!< 1 means that this is a CC1350 chip. + CHIP_TYPE_CC2620 = 2, //!< 2 means that this is a CC2620 chip. + CHIP_TYPE_CC2630 = 3, //!< 3 means that this is a CC2630 chip. + CHIP_TYPE_CC2640 = 4, //!< 4 means that this is a CC2640 chip. + CHIP_TYPE_CC2650 = 5, //!< 5 means that this is a CC2650 chip. + CHIP_TYPE_CUSTOM_0 = 6, //!< 6 means that this is a CUSTOM_0 chip. + CHIP_TYPE_CUSTOM_1 = 7, //!< 7 means that this is a CUSTOM_1 chip. + CHIP_TYPE_CC2640R2 = 8, //!< 8 means that this is a CC2640R2 chip. + CHIP_TYPE_CC2642 = 9, //!< 9 means that this is a CC2642 chip. + CHIP_TYPE_unused = 10,//!< 10 unused value + CHIP_TYPE_CC2652 = 11,//!< 11 means that this is a CC2652 chip. + CHIP_TYPE_CC1312 = 12,//!< 12 means that this is a CC1312 chip. + CHIP_TYPE_CC1352 = 13,//!< 13 means that this is a CC1352 chip. + CHIP_TYPE_CC1352P = 14 //!< 14 means that this is a CC1352P chip. +} ChipType_t; + +//***************************************************************************** +// +//! \brief Returns chip type. +//! +//! \return +//! Returns \ref ChipType_t +// +//***************************************************************************** +extern ChipType_t ChipInfo_GetChipType( void ); + +//***************************************************************************** +// +//! \brief Chip family enumeration +// +//***************************************************************************** +typedef enum { + FAMILY_Unknown = -1, //!< -1 means that the chip's family member is unknown. + FAMILY_CC26x0 = 0, //!< 0 means that the chip is a CC26x0 family member. + FAMILY_CC13x0 = 1, //!< 1 means that the chip is a CC13x0 family member. + FAMILY_CC26x1 = 2, //!< 2 means that the chip is a CC26x1 family member. + FAMILY_CC26x0R2 = 3, //!< 3 means that the chip is a CC26x0R2 family (new ROM contents). + FAMILY_CC13x2_CC26x2 = 4 //!< 4 means that the chip is a CC13x2, CC26x2 family member. +} ChipFamily_t; + +//***************************************************************************** +// +//! \brief Returns chip family member. +//! +//! \return +//! Returns \ref ChipFamily_t +// +//***************************************************************************** +extern ChipFamily_t ChipInfo_GetChipFamily( void ); + +//***************************************************************************** +// +// Options for the define THIS_DRIVERLIB_BUILD +// +//***************************************************************************** +#define DRIVERLIB_BUILD_CC26X0 0 //!< 0 is the driverlib build ID for the cc26x0 driverlib. +#define DRIVERLIB_BUILD_CC13X0 1 //!< 1 is the driverlib build ID for the cc13x0 driverlib. +#define DRIVERLIB_BUILD_CC26X1 2 //!< 2 is the driverlib build ID for the cc26x1 driverlib. +#define DRIVERLIB_BUILD_CC26X0R2 3 //!< 3 is the driverlib build ID for the cc26x0r2 driverlib. +#define DRIVERLIB_BUILD_CC13X2_CC26X2 4 //!< 4 is the driverlib build ID for the cc13x2_cc26x2 driverlib. + +//***************************************************************************** +// +//! \brief Define THIS_DRIVERLIB_BUILD, identifying current driverlib build ID. +//! +//! This driverlib build identifier can be useful for compile time checking/optimization (supporting C preprocessor expressions). +// +//***************************************************************************** +#define THIS_DRIVERLIB_BUILD DRIVERLIB_BUILD_CC13X2_CC26X2 + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC13x0 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC13x0 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC13x0( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC13x0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC26x0 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC26x0 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC26x0( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC26x0R2 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC26x0R2 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC26x0R2( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0R2 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC26x1 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC26x1 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC26x1( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC26x1 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC13x2, CC26x2 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC13x2, CC26x2 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC13x2_CC26x2( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC13x2_CC26x2 ); +} + +//***************************************************************************** +// +//! \brief HW revision enumeration. +// +//***************************************************************************** +typedef enum { + HWREV_Unknown = -1, //!< -1 means that the chip's HW revision is unknown. + HWREV_1_0 = 10, //!< 10 means that the chip's HW revision is 1.0 + HWREV_1_1 = 11, //!< 11 means that the chip's HW revision is 1.1 + HWREV_2_0 = 20, //!< 20 means that the chip's HW revision is 2.0 + HWREV_2_1 = 21, //!< 21 means that the chip's HW revision is 2.1 + HWREV_2_2 = 22, //!< 22 means that the chip's HW revision is 2.2 + HWREV_2_3 = 23, //!< 23 means that the chip's HW revision is 2.3 + HWREV_2_4 = 24 //!< 24 means that the chip's HW revision is 2.4 +} HwRevision_t; + +//***************************************************************************** +// +//! \brief Returns chip HW revision. +//! +//! \return +//! Returns \ref HwRevision_t +// +//***************************************************************************** +extern HwRevision_t ChipInfo_GetHwRevision( void ); + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 1.0. +//! +//! \return +//! Returns \c true if HW revision for this chip is 1.0, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_1_0( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_1_0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.0. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.0, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_2_0( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_2_0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.0 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.0 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_0( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.1. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.1, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_2_1( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_2_1 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.1 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.1 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_1( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_1 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.2. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.2, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_2_2( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_2_2 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.2 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.2 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_2( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_2 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.3 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.3 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_3( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_3 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.4 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.4 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_4( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_4 ); +} + +//***************************************************************************** +// +//! \brief Verifies that current chip is CC13x2 or CC26x2 PG2.0 or later and never returns if violated. +//! +//! \return None +// +//***************************************************************************** +extern void ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated( void ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_ChipInfo_GetSupportedProtocol_BV + #undef ChipInfo_GetSupportedProtocol_BV + #define ChipInfo_GetSupportedProtocol_BV ROM_ChipInfo_GetSupportedProtocol_BV + #endif + #ifdef ROM_ChipInfo_GetPackageType + #undef ChipInfo_GetPackageType + #define ChipInfo_GetPackageType ROM_ChipInfo_GetPackageType + #endif + #ifdef ROM_ChipInfo_GetChipType + #undef ChipInfo_GetChipType + #define ChipInfo_GetChipType ROM_ChipInfo_GetChipType + #endif + #ifdef ROM_ChipInfo_GetChipFamily + #undef ChipInfo_GetChipFamily + #define ChipInfo_GetChipFamily ROM_ChipInfo_GetChipFamily + #endif + #ifdef ROM_ChipInfo_GetHwRevision + #undef ChipInfo_GetHwRevision + #define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision + #endif + #ifdef ROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated + #undef ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated + #define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated ROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CHIP_INFO_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.c new file mode 100644 index 0000000..293767d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.c @@ -0,0 +1,396 @@ +/****************************************************************************** +* Filename: cpu.c +* Revised: 2018-05-08 10:04:01 +0200 (Tue, 08 May 2018) +* Revision: 51972 +* +* Description: Instruction wrappers for special CPU instructions needed by +* the drivers. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "cpu.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef CPUcpsid + #define CPUcpsid NOROM_CPUcpsid + #undef CPUprimask + #define CPUprimask NOROM_CPUprimask + #undef CPUcpsie + #define CPUcpsie NOROM_CPUcpsie + #undef CPUbasepriGet + #define CPUbasepriGet NOROM_CPUbasepriGet + #undef CPUdelay + #define CPUdelay NOROM_CPUdelay +#endif + +//***************************************************************************** +// +// Disable all external interrupts +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUcpsid(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + mrs r0, PRIMASK; + cpsid i; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUcpsid(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK and disable interrupts + __asm volatile (" mrs %0, PRIMASK\n" + " cpsid i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif + +//***************************************************************************** +// +// Get the current interrupt state +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUprimask(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUprimask(void) +{ + // Read PRIMASK. + __asm(" mrs r0, PRIMASK\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUprimask(void) +{ + // Read PRIMASK. + mrs r0, PRIMASK; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUprimask(void) +{ + // Read PRIMASK. + __asm(" mrs r0, PRIMASK\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUprimask(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK + __asm volatile (" mrs %0, PRIMASK\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif + +//***************************************************************************** +// +// Enable all external interrupts +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUcpsie(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + mrs r0, PRIMASK; + cpsie i; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUcpsie(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK and enable interrupts. + __asm volatile (" mrs %0, PRIMASK\n" + " cpsie i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif + +//***************************************************************************** +// +// Get the interrupt priority disable level +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUbasepriGet(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUbasepriGet(void) +{ + // Read BASEPRI. + __asm(" mrs r0, BASEPRI\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUbasepriGet(void) +{ + // Read BASEPRI. + mrs r0, BASEPRI; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUbasepriGet(void) +{ + // Read BASEPRI. + __asm(" mrs r0, BASEPRI\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUbasepriGet(void) +{ + uint32_t ui32Ret; + + // Read BASEPRI. + __asm volatile (" mrs %0, BASEPRI\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif +//***************************************************************************** +// +// Provide a small delay +// +//***************************************************************************** +#if defined(DOXYGEN) +void +CPUdelay(uint32_t ui32Count) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +void +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times + __asm("CPUdelay:\n" + " subs r0, #1\n" + " bne.n CPUdelay\n" + " bx lr"); +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm void +CPUdelay(uint32_t ui32Count) +{ + // Delay the specified number of times (3 cycles pr. loop) +CPUdel + subs r0, #1; + bne CPUdel; + bx lr; +} +#elif defined(__TI_COMPILER_VERSION__) + // For CCS implement this function in pure assembly. This prevents the TI + // compiler from doing funny things with the optimizer. + + // Loop the specified number of times +__asm(" .sect \".text:NOROM_CPUdelay\"\n" + " .clink\n" + " .thumbfunc NOROM_CPUdelay\n" + " .thumb\n" + " .global NOROM_CPUdelay\n" + "NOROM_CPUdelay:\n" + " subs r0, #1\n" + " bne.n NOROM_CPUdelay\n" + " bx lr\n"); +#else +// GCC +void __attribute__((naked)) +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times + __asm volatile ("%=: subs %0, #1\n" + " bne %=b\n" + " bx lr\n" + : /* No output */ + : "r" (ui32Count) + ); +} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h new file mode 100644 index 0000000..e2b0561 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h @@ -0,0 +1,466 @@ +/****************************************************************************** +* Filename: cpu.h +* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) +* Revision: 52111 +* +* Description: Defines and prototypes for the CPU instruction wrapper +* functions. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup cpu_api +//! @{ +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_cpu_scs.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define CPUcpsid NOROM_CPUcpsid + #define CPUprimask NOROM_CPUprimask + #define CPUcpsie NOROM_CPUcpsie + #define CPUbasepriGet NOROM_CPUbasepriGet + #define CPUdelay NOROM_CPUdelay +#endif + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Disable all external interrupts. +//! +//! Use this function to disable all system interrupts. This function is +//! implemented as a wrapper function for the CPSID instruction. +//! +//! \return Returns the state of \b PRIMASK on entry +// +//***************************************************************************** +extern uint32_t CPUcpsid(void); + +//***************************************************************************** +// +//! \brief Get the current interrupt state. +//! +//! Use this function to retrieve the current state of the interrupts. This +//! function is implemented as a wrapper function returning the state of +//! PRIMASK. +//! +//! \return Returns the state of the \b PRIMASK (indicating whether interrupts +//! are enabled or disabled). +// +//***************************************************************************** +extern uint32_t CPUprimask(void); + +//***************************************************************************** +// +//! \brief Enable all external interrupts. +//! +//! Use this function to enable all system interrupts. This function is +//! implemented as a wrapper function for the CPSIE instruction. +//! +//! \return Returns the state of \b PRIMASK on entry. +// +//***************************************************************************** +extern uint32_t CPUcpsie(void); + +//***************************************************************************** +// +//! \brief Get the interrupt priority disable level. +//! +//! Use this function to get the level of priority that will disable +//! interrupts with a lower priority level. +//! +//! \return Returns the value of the \b BASEPRI register. +// +//***************************************************************************** +extern uint32_t CPUbasepriGet(void); + +//***************************************************************************** +// +//! \brief Provide a small non-zero delay using a simple loop counter. +//! +//! This function provides means for generating a constant length delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! \note It is not recommended using this function for long delays. +//! +//! Notice that interrupts can affect the delay if not manually disabled in advance. +//! +//! The delay depends on where code resides and the path for code fetching: +//! - Code in flash, cache enabled, prefetch enabled : 4 cycles per loop (Default) +//! - Code in flash, cache enabled, prefetch disabled : 5 cycles per loop +//! - Code in flash, cache disabled : 7 cycles per loop +//! - Code in SRAM : 6 cycles per loop +//! - Code in GPRAM : 3 cycles per loop +//! +//! \note If using an RTOS, consider using RTOS provided delay functions because +//! these will not block task scheduling and will potentially save power. +//! +//! Calculate delay count based on the wanted delay in microseconds (us): +//! - ui32Count = [delay in us] * [CPU clock in MHz] / [cycles per loop] +//! +//! Example: 250 us delay with code in flash and with cache and prefetch enabled: +//! - ui32Count = 250 * 48 / 4 = 3000 +//! +//! \param ui32Count is the number of delay loop iterations to perform. Number must be greater than zero. +//! +//! \return None +// +//***************************************************************************** +extern void CPUdelay(uint32_t ui32Count); + +//***************************************************************************** +// +//! \brief Wait for interrupt. +//! +//! Use this function to let the System CPU wait for the next interrupt. This +//! function is implemented as a wrapper function for the WFI instruction. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUwfi(void) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUwfi(void) +{ + // Wait for the next interrupt. + __asm(" wfi\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUwfi(void) +{ + // Wait for the next interrupt. + wfi; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUwfi(void) +{ + // Wait for the next interrupt. + __asm(" wfi\n"); +} +#else +__STATIC_INLINE void __attribute__((always_inline)) +CPUwfi(void) +{ + // Wait for the next interrupt. + __asm volatile (" wfi\n"); +} +#endif + +//***************************************************************************** +// +//! \brief Wait for event. +//! +//! Use this function to let the System CPU wait for the next event. This +//! function is implemented as a wrapper function for the WFE instruction. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUwfe(void) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUwfe(void) +{ + // Wait for the next event. + __asm(" wfe\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUwfe(void) +{ + // Wait for the next event. + wfe; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUwfe(void) +{ + // Wait for the next event. + __asm(" wfe\n"); +} +#else +__STATIC_INLINE void __attribute__((always_inline)) +CPUwfe(void) +{ + // Wait for the next event. + __asm volatile (" wfe\n"); +} +#endif + +//***************************************************************************** +// +//! \brief Send event. +//! +//! Use this function to let the System CPU send an event. This function is +//! implemented as a wrapper function for the SEV instruction. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUsev(void) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUsev(void) +{ + // Send event. + __asm(" sev\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUsev(void) +{ + // Send event. + sev; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUsev(void) +{ + // Send event. + __asm(" sev\n"); +} +#else +__STATIC_INLINE void __attribute__((always_inline)) +CPUsev(void) +{ + // Send event. + __asm volatile (" sev\n"); +} +#endif + + +//***************************************************************************** +// +//! \brief Update the interrupt priority disable level. +//! +//! Use this function to change the level of priority that will disable +//! interrupts with a lower priority level. +//! +//! \param ui32NewBasepri is the new basis priority level to set. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + __asm(" msr BASEPRI, r0\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + msr BASEPRI, r0; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + __asm(" msr BASEPRI, r0\n"); +} +#else +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wattributes" +__STATIC_INLINE void __attribute__ ((naked)) +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + __asm volatile (" msr BASEPRI, %0\n" + " bx lr\n" + : /* No output */ + : "r" (ui32NewBasepri) + ); +} +#pragma GCC diagnostic pop +#endif + +//***************************************************************************** +// +//! \brief Disable CPU write buffering (recommended for debug purpose only). +//! +//! This function helps debugging "bus fault crashes". +//! Disables write buffer use during default memory map accesses. +//! +//! This causes all bus faults to be precise bus faults but decreases the +//! performance of the processor because the stores to memory have to complete +//! before the next instruction can be executed. +//! +//! \return None +//! +//! \sa \ref CPU_WriteBufferEnable() +// +//***************************************************************************** +__STATIC_INLINE void +CPU_WriteBufferDisable( void ) +{ + HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1; +} + +//***************************************************************************** +// +//! \brief Enable CPU write buffering (default setting). +//! +//! Re-enables write buffer during default memory map accesses if +//! \ref CPU_WriteBufferDisable() has been used for bus fault debugging. +//! +//! \return None +//! +//! \sa \ref CPU_WriteBufferDisable() +// +//***************************************************************************** +__STATIC_INLINE void +CPU_WriteBufferEnable( void ) +{ + HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_CPUcpsid + #undef CPUcpsid + #define CPUcpsid ROM_CPUcpsid + #endif + #ifdef ROM_CPUprimask + #undef CPUprimask + #define CPUprimask ROM_CPUprimask + #endif + #ifdef ROM_CPUcpsie + #undef CPUcpsie + #define CPUcpsie ROM_CPUcpsie + #endif + #ifdef ROM_CPUbasepriGet + #undef CPUbasepriGet + #define CPUbasepriGet ROM_CPUbasepriGet + #endif + #ifdef ROM_CPUdelay + #undef CPUdelay + #define CPUdelay ROM_CPUdelay + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CPU_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h new file mode 100644 index 0000000..7f17aa3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h @@ -0,0 +1,44 @@ +/****************************************************************************** +* Filename: cpu_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup cpu_api +//! @{ +//! \section sec_cpu Introduction +//! +//! The CPU API provides a set of functions performing very low-level control of the system CPU. +//! All functions in this API are written in assembler in order to either access special registers +//! or avoid any compiler optimizations. Each function exists in several compiler specific versions: +//! One version for each supported compiler. +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.c new file mode 100644 index 0000000..d6617a2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.c @@ -0,0 +1,943 @@ +/****************************************************************************** +* Filename: crypto.c +* Revised: 2017-12-20 16:40:03 +0100 (Wed, 20 Dec 2017) +* Revision: 50869 +* +* Description: Driver for the Crypto module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "crypto.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef CRYPTOAesLoadKey + #define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey + #undef CRYPTOAesCbc + #define CRYPTOAesCbc NOROM_CRYPTOAesCbc + #undef CRYPTOAesCbcStatus + #define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus + #undef CRYPTOAesEcb + #define CRYPTOAesEcb NOROM_CRYPTOAesEcb + #undef CRYPTOAesEcbStatus + #define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus + #undef CRYPTOCcmAuthEncrypt + #define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt + #undef CRYPTOCcmAuthEncryptStatus + #define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus + #undef CRYPTOCcmAuthEncryptResultGet + #define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet + #undef CRYPTOCcmInvAuthDecrypt + #define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt + #undef CRYPTOCcmInvAuthDecryptStatus + #define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus + #undef CRYPTOCcmInvAuthDecryptResultGet + #define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet + #undef CRYPTODmaEnable + #define CRYPTODmaEnable NOROM_CRYPTODmaEnable + #undef CRYPTODmaDisable + #define CRYPTODmaDisable NOROM_CRYPTODmaDisable +#endif + +//***************************************************************************** +// +// Write the key into the Key Ram. +// +//***************************************************************************** +uint32_t +CRYPTOAesLoadKey(uint32_t *pui32AesKey, + uint32_t ui32KeyLocation) +{ + uint32_t returnStatus = AES_KEYSTORE_READ_ERROR; + + // Check the arguments. + ASSERT((ui32KeyLocation == CRYPTO_KEY_AREA_0) | + (ui32KeyLocation == CRYPTO_KEY_AREA_1) | + (ui32KeyLocation == CRYPTO_KEY_AREA_2) | + (ui32KeyLocation == CRYPTO_KEY_AREA_3) | + (ui32KeyLocation == CRYPTO_KEY_AREA_4) | + (ui32KeyLocation == CRYPTO_KEY_AREA_5) | + (ui32KeyLocation == CRYPTO_KEY_AREA_6) | + (ui32KeyLocation == CRYPTO_KEY_AREA_7)); + + // Disable the external interrupt to stop the interrupt form propagating + // from the module to the System CPU. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Clear any previously written key at the keyLocation + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << ui32KeyLocation); + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | + CRYPTO_IRQEN_RESULT_AVAIL; + + // Configure master control module. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_ALGSEL, CRYPTO_ALGSEL_KEY_STORE_BITN) = 1; + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Configure key store module for 128 bit operation. + // Do not write to the register if the correct key size is already set. + // Writing to this register causes all current keys to be invalidated. + if (HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) != KEY_STORE_SIZE_128) { + HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = KEY_STORE_SIZE_128; + } + + // Enable keys to write (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = (0x00000001 << ui32KeyLocation); + + // Enable Crypto DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the key in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32AesKey; + + // Total key length in bytes (e.g. 16 for 1 x 128-bit key). + // Writing the length of the key enables the DMA operation. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = KEY_BLENGTH; + + // Wait for the DMA operation to complete. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & + (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | + CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M | + CRYPTO_IRQSTAT_DMA_IN_DONE | + CRYPTO_IRQSTAT_RESULT_AVAIL_M))); + + // Check for errors in DMA and key store. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & + (CRYPTO_IRQSTAT_DMA_BUS_ERR | + CRYPTO_IRQSTAT_KEY_ST_WR_ERR)) == 0) + { + // Acknowledge/clear the interrupt and disable the master control. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + + // Check key status, return success if key valid. + if(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (0x00000001 << ui32KeyLocation)) + { + returnStatus = AES_SUCCESS; + } + } + + // Return status. + return returnStatus; +} + +//***************************************************************************** +// +// Start an AES-CBC operation (encryption or decryption). +// +//***************************************************************************** +uint32_t +CRYPTOAesCbc(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32MsgLength, + uint32_t *pui32Nonce, uint32_t ui32KeyLocation, + bool bEncrypt, bool bIntEnable) +{ + uint32_t ui32CtrlVal; + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; + + // Clear any outstanding interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Wait for interrupt lines from module to be cleared + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); + + // If using interrupts clear any pending interrupts and enable interrupts + // for the Crypto module. + if(bIntEnable) + { + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + // Configure Master Control module. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; + + //Wait until key is loaded to the AES module. + do + { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); + + // Check for Key store Read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) + { + return (AES_KEYSTORE_READ_ERROR); + } + + // Write initialization vector. + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = pui32Nonce[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = pui32Nonce[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = pui32Nonce[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = pui32Nonce[3]; + + // Configure AES engine for AES-CBC with 128-bit key size. + ui32CtrlVal = (CRYPTO_AESCTL_SAVE_CONTEXT | CRYPTO_AESCTL_CBC); + if(bEncrypt) + { + ui32CtrlVal |= CRYPTO_AES128_ENCRYPT; + } + else + { + ui32CtrlVal |= CRYPTO_AES128_DECRYPT; + } + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; + + // Write the length of the crypto block (plain text). + // Low and high part (high part is assumed to be always 0). + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32MsgLength; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; + HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = 0; + + // Enable Crypto DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the input data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn; + + // Input data length in bytes, equal to the message. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32MsgLength; + + // Enable Crypto DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Set up the address and length of the output data. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut; + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32MsgLength; + + // Return success + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Check the result of an AES CBC operation +// +//***************************************************************************** +uint32_t +CRYPTOAesCbcStatus(void) +{ + return(CRYPTOAesEcbStatus()); +} + +//***************************************************************************** +// +// Start an AES-ECB operation (encryption or decryption). +// +//***************************************************************************** +uint32_t +CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, + uint32_t ui32KeyLocation, bool bEncrypt, + bool bIntEnable) +{ + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; + + // Clear any outstanding interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Wait for interrupt lines from module to be cleared + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); + + // If using interrupts clear any pending interrupts and enable interrupts + // for the Crypto module. + if(bIntEnable) + { + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + // Configure Master Control module. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; + + //Wait until key is loaded to the AES module. + do + { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); + + // Check for Key store Read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) + { + return (AES_KEYSTORE_READ_ERROR); + } + + // Configure AES engine (program AES-ECB-128 encryption and no + // initialization vector - IV). + if(bEncrypt) + { + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_ENCRYPT; + } + else + { + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_DECRYPT; + } + + // Write the length of the data. + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = AES_ECB_LENGTH; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; + + // Enable Crypto DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the input data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn; + + // Input data length in bytes, equal to the message. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = AES_ECB_LENGTH; + + // Enable Crypto DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Set up the address and length of the output data. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut; + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = AES_ECB_LENGTH; + + // Return success + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Check the result of an AES ECB operation +// +//***************************************************************************** +uint32_t +CRYPTOAesEcbStatus(void) +{ + uint32_t ui32Status; + + // Get the current DMA status. + ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); + + // Check if DMA is still busy. + if(ui32Status & CRYPTO_DMA_BSY) + { + return (AES_DMA_BSY); + } + + // Check the status of the DMA operation - return error if not success. + if(ui32Status & CRYPTO_DMA_BUS_ERROR) + { + return (AES_DMA_BUS_ERROR); + } + + // Operation successful - disable interrupt and return success. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + return (AES_SUCCESS); +} + +//***************************************************************************** +// +// Start CCM operation +// +//***************************************************************************** +uint32_t +CRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength , + uint32_t *pui32Nonce, uint32_t *pui32PlainText, + uint32_t ui32PlainTextLength, uint32_t *pui32Header, + uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, + uint32_t ui32FieldLength, bool bIntEnable) +{ + uint32_t ui32CtrlVal; + uint32_t i; + uint32_t *pui32CipherText; + union { + uint32_t w[4]; + uint8_t b[16]; + } ui8InitVec; + + // Input address for the encryption engine is the same as the output. + pui32CipherText = pui32PlainText; + + // Disable global interrupt, enable local interrupt and clear any pending + // interrupts. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | + CRYPTO_IRQEN_RESULT_AVAIL; + + // Configure master control module for AES operation. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; + + // Wait until key is loaded to the AES module. + do + { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); + + // Check for Key store Read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) + { + return (AES_KEYSTORE_READ_ERROR); + } + + // Prepare the initialization vector (IV), + // Length of Nonce l(n) = 15 - ui32FieldLength. + ui8InitVec.b[0] = ui32FieldLength - 1; + for(i = 0; i < 12; i++) + { + ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i]; + } + if(ui32FieldLength == 2) + { + ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12]; + } + else + { + ui8InitVec.b[13] = 0; + } + ui8InitVec.b[14] = 0; + ui8InitVec.b[15] = 0; + + // Write initialization vector. + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3]; + + // Configure AES engine. + ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if ( ui32AuthLength >= 2 ) { + ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); + } + ui32CtrlVal |= CRYPTO_AESCTL_CCM; + ui32CtrlVal |= CRYPTO_AESCTL_CTR; + ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT; + ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S); + ui32CtrlVal |= (1 << CRYPTO_AESCTL_DIR_S); + ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S); + + // Write the configuration for 128 bit AES-CCM. + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; + + // Write the length of the crypto block (plain text). + // Low and high part (high part is assumed to be always 0). + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32PlainTextLength; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; + + // Write the length of the header field. + // Also called AAD - Additional Authentication Data. + HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength; + + // Check if any header information (AAD). + // If so configure the DMA controller to fetch the header. + if(ui32HeaderLength != 0) + { + // Enable DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Register the base address of the header (AAD). + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header; + + // Header length in bytes (may be non-block size aligned). + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength; + + // Wait for completion of the header data transfer, DMA_IN_DONE. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE)); + + // Check for DMA errors. + if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR) + { + return AES_DMA_BUS_ERROR; + } + } + + // Clear interrupt status. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Wait for interrupt lines from module to be cleared + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); + + // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only + // want interrupt to trigger once RESULT_AVAIL occurs. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE; + + + // Is using interrupts enable globally. + if(bIntEnable) + { + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + // Enable interrupts locally. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; + + // Perform encryption if requested. + if(bEncrypt) + { + // Enable DMA channel 0 + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = + (uint32_t)pui32PlainText; + + // Enable DMA channel 1 + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = + (uint32_t)pui32CipherText; + + // Payload data length in bytes, equal to the plaintext length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32PlainTextLength; + // Output data length in bytes, equal to the plaintext length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32PlainTextLength; + } + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Check the result of an AES CCM operation. +// +//***************************************************************************** +uint32_t +CRYPTOCcmAuthEncryptStatus(void) +{ + uint32_t ui32Status; + + // Get the current DMA status. + ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); + + // Check if DMA is still busy. + if(ui32Status & CRYPTO_DMA_BSY) + { + return (AES_DMA_BSY); + } + + // Check the status of the DMA operation - return error if not success. + if(ui32Status & CRYPTO_DMA_BUS_ERROR) + { + return (AES_DMA_BUS_ERROR); + } + + // Operation successful - disable interrupt and return success. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + return (AES_SUCCESS); +} + +//***************************************************************************** +// +// Get the result of an AES-CCM operation +// +//***************************************************************************** +uint32_t +CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, uint32_t *pui32CcmTag) +{ + uint32_t volatile ui32Tag[4]; + uint32_t ui32Idx; + + // Result has already been copied to the output buffer by DMA + // Disable master control. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + + // Read tag - wait for the context ready bit. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & + CRYPTO_AESCTL_SAVED_CONTEXT_RDY)); + + // Read the Tag registers. + ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); + ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); + ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); + ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); + + for(ui32Idx = 0; ui32Idx < ui32TagLength ; ui32Idx++) + { + *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx); + } + + // Operation successful - clear interrupt status. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Start a CCM Decryption and Inverse Authentication operation. +// +//***************************************************************************** +uint32_t +CRYPTOCcmInvAuthDecrypt(bool bDecrypt, uint32_t ui32AuthLength, + uint32_t *pui32Nonce, uint32_t *pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t *pui32Header, uint32_t ui32HeaderLength, + uint32_t ui32KeyLocation, + uint32_t ui32FieldLength, bool bIntEnable) +{ + uint32_t ui32CtrlVal; + uint32_t i; + uint32_t *pui32PlainText; + uint32_t ui32CryptoBlockLength; + union { + uint32_t w[4]; + uint8_t b[16]; + } ui8InitVec; + + // Input address for the encryption engine is the same as the output. + pui32PlainText = pui32CipherText; + + // Disable global interrupt, enable local interrupt and clear any pending. + // interrupts. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | + CRYPTO_IRQEN_RESULT_AVAIL; + + // Configure master control module for AES operation. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; + + // Wait until key is loaded to the AES module. + do + { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); + + // Check for Key store Read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) + { + return (AES_KEYSTORE_READ_ERROR); + } + + // Prepare the initialization vector (IV), + // Length of Nonce l(n) = 15 - ui32FieldLength. + ui8InitVec.b[0] = ui32FieldLength - 1; + for(i = 0; i < 12; i++) + { + ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i]; + } + if(ui32FieldLength == 2) + { + ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12]; + } + else + { + ui8InitVec.b[13] = 0; + } + ui8InitVec.b[14] = 0; + ui8InitVec.b[15] = 0; + + // Write initialization vector. + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3]; + + // Configure AES engine + ui32CryptoBlockLength = ui32CipherTextLength - ui32AuthLength; + ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if ( ui32AuthLength >= 2 ) { + ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); + } + ui32CtrlVal |= CRYPTO_AESCTL_CCM; + ui32CtrlVal |= CRYPTO_AESCTL_CTR; + ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT; + ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S); + ui32CtrlVal |= (0 << CRYPTO_AESCTL_DIR_S); + ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S); + + // Write the configuration for 128 bit AES-CCM. + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; + + // Write the length of the crypto block (plain text). + // Low and high part (high part is assumed to be always 0). + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32CryptoBlockLength; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; + + // Write the length of the header field. + // Also called AAD - Additional Authentication Data. + HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength; + + // Check if any header information (AAD). + // If so configure the DMA controller to fetch the header. + if(ui32HeaderLength != 0) + { + // Enable DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Register the base address of the header (AAD). + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header; + + // Header length in bytes (may be non-block size aligned). + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength; + + // Wait for completion of the header data transfer, DMA_IN_DONE. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE)); + + // Check for DMA errors. + if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR) + { + return AES_DMA_BUS_ERROR; + } + } + + // Clear interrupt status. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Wait for interrupt lines from module to be cleared + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); + + // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only + // want interrupt to trigger once RESULT_AVAIL occurs. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE; + + // Is using interrupts - clear and enable globally. + if(bIntEnable) + { + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; + + // Perform decryption if requested. + if(bDecrypt) + { + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = + (uint32_t)pui32CipherText; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32CryptoBlockLength; + + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = + (uint32_t)pui32PlainText; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32CryptoBlockLength; + } + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Checks CCM decrypt and Inverse Authentication result. +// +//***************************************************************************** +uint32_t +CRYPTOCcmInvAuthDecryptStatus(void) +{ + uint32_t ui32Status; + + // Get the current DMA status. + ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); + + // Check if DMA is still busy. + if(ui32Status & CRYPTO_DMA_BSY) + { + return (AES_DMA_BSY); + } + + // Check the status of the DMA operation - return error if not success. + if(ui32Status & CRYPTO_DMA_BUS_ERROR) + { + return (AES_DMA_BUS_ERROR); + } + + // Operation successful - disable interrupt and return success + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + return (AES_SUCCESS); +} + +//***************************************************************************** +// +// Get the result of the CCM operation. +// +//***************************************************************************** +uint32_t +CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength, + uint32_t *pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t *pui32CcmTag) +{ + uint32_t volatile ui32Tag[4]; + uint32_t ui32TagIndex; + uint32_t i; + uint32_t ui32Idx; + + ui32TagIndex = ui32CipherTextLength - ui32AuthLength; + + // Result has already been copied to the output buffer by DMA + // Disable master control. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + + // Read tag - wait for the context ready bit. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & + CRYPTO_AESCTL_SAVED_CONTEXT_RDY)); + + // Read the Tag registers. + ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); + ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); + ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); + ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); + + for(ui32Idx = 0; ui32Idx < ui32AuthLength ; ui32Idx++) + { + *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx); + } + + // Operation successful - clear interrupt status. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Verify the Tag. + for(i = 0; i < ui32AuthLength; i++) + { + if(*((uint8_t *)pui32CcmTag + i) != + (*((uint8_t *)pui32CipherText + ui32TagIndex + i))) + { + return CCM_AUTHENTICATION_FAILED; + } + } + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Enable Crypto DMA operation +// +//***************************************************************************** +void +CRYPTODmaEnable(uint32_t ui32Channels) +{ + // Check the arguments. + ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) | + (ui32Channels & CRYPTO_DMA_CHAN1)); + + // Enable the selected channels, + if(ui32Channels & CRYPTO_DMA_CHAN0) + { + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + } + if(ui32Channels & CRYPTO_DMA_CHAN1) + { + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + } +} + +//***************************************************************************** +// +// Disable Crypto DMA operation +// +//***************************************************************************** +void +CRYPTODmaDisable(uint32_t ui32Channels) +{ + // Check the arguments. + ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) | + (ui32Channels & CRYPTO_DMA_CHAN1)); + + // Enable the selected channels. + if(ui32Channels & CRYPTO_DMA_CHAN0) + { + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 0; + } + if(ui32Channels & CRYPTO_DMA_CHAN1) + { + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 0; + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h new file mode 100644 index 0000000..bb411ec --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h @@ -0,0 +1,856 @@ +/****************************************************************************** +* Filename: crypto.h +* Revised: 2018-01-12 18:46:31 +0100 (Fri, 12 Jan 2018) +* Revision: 51161 +* +* Description: AES header file. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup crypto_api +//! @{ +// +//***************************************************************************** + +#ifndef __CRYPTO_H__ +#define __CRYPTO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_crypto.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey + #define CRYPTOAesCbc NOROM_CRYPTOAesCbc + #define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus + #define CRYPTOAesEcb NOROM_CRYPTOAesEcb + #define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus + #define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt + #define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus + #define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet + #define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt + #define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus + #define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet + #define CRYPTODmaEnable NOROM_CRYPTODmaEnable + #define CRYPTODmaDisable NOROM_CRYPTODmaDisable +#endif + +//***************************************************************************** +// +// Length of AES Electronic Code Book (ECB) block in bytes +// +//***************************************************************************** +#define AES_ECB_LENGTH 16 + +//***************************************************************************** +// +// Values that can be passed to CryptoIntEnable, CryptoIntDisable, and CryptoIntClear +// as the ui32IntFlags parameter, and returned from CryptoIntStatus. +// +//***************************************************************************** +#define CRYPTO_DMA_IN_DONE 0x00000002 // DMA done interrupt mask +#define CRYPTO_RESULT_RDY 0x00000001 // Result ready interrupt mask +#define CRYPTO_DMA_BUS_ERR 0x80000000 // DMA Bus error +#define CRYPTO_KEY_ST_WR_ERR 0x40000000 // Key Store Write failed +#define CRYPTO_KEY_ST_RD_ERR 0x20000000 // Key Store Read failed + +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 // Crypto Level interrupt enabled +#define CRYPTO_IRQTYPE_PULSE 0x00000000 // Crypto pulse interrupt enabled + +#define CRYPTO_DMA_CHAN0 0x00000001 // Crypto DMA Channel 0 +#define CRYPTO_DMA_CHAN1 0x00000002 // Crypto DMA Channel 1 + +#define CRYPTO_AES128_ENCRYPT 0x0000000C // +#define CRYPTO_AES128_DECRYPT 0x00000008 // + +#define CRYPTO_DMA_READY 0x00000000 // DMA ready +#define CRYPTO_DMA_BSY 0x00000003 // DMA busy +#define CRYPTO_DMA_BUS_ERROR 0x00020000 // DMA encountered bus error + +//***************************************************************************** +// +// General constants +// +//***************************************************************************** + +// AES module return codes +#define AES_SUCCESS 0 +#define AES_KEYSTORE_READ_ERROR 1 +#define AES_KEYSTORE_WRITE_ERROR 2 +#define AES_DMA_BUS_ERROR 3 +#define CCM_AUTHENTICATION_FAILED 4 +#define AES_ECB_TEST_ERROR 8 +#define AES_NULL_ERROR 9 +#define AES_CCM_TEST_ERROR 10 +#define AES_DMA_BSY 11 + +// Key store module defines +#define STATE_BLENGTH 16 // Number of bytes in State +#define KEY_BLENGTH 16 // Number of bytes in Key +#define KEY_EXP_LENGTH 176 // Nb * (Nr+1) * 4 + +#define KEY_STORE_SIZE_128 0x00000001 +#define KEY_STORE_SIZE_192 0x00000002 +#define KEY_STORE_SIZE_256 0x00000003 +#define KEY_STORE_SIZE_BITS 0x00000003 + +//***************************************************************************** +// +// For 128 bit key all 8 Key Area locations from 0 to 8 are valid +// However for 192 bit and 256 bit keys, only even Key Areas 0, 2, 4, 6 +// are valid. +// +//***************************************************************************** +#define CRYPTO_KEY_AREA_0 0 +#define CRYPTO_KEY_AREA_1 1 +#define CRYPTO_KEY_AREA_2 2 +#define CRYPTO_KEY_AREA_3 3 +#define CRYPTO_KEY_AREA_4 4 +#define CRYPTO_KEY_AREA_5 5 +#define CRYPTO_KEY_AREA_6 6 +#define CRYPTO_KEY_AREA_7 7 + +//***************************************************************************** +// +// Defines for the current AES operation +// +//***************************************************************************** +#define CRYPTO_AES_NONE 0 +#define CRYPTO_AES_KEYL0AD 1 +#define CRYPTO_AES_ECB 2 +#define CRYPTO_AES_CCM 3 +#define CRYPTO_AES_RNG 4 +#define CRYPTO_AES_CBC 5 + +//***************************************************************************** +// +// Defines for the AES-CTR mode counter width +// +//***************************************************************************** +#define CRYPTO_AES_CTR_32 0x0 +#define CRYPTO_AES_CTR_64 0x1 +#define CRYPTO_AES_CTR_96 0x2 +#define CRYPTO_AES_CTR_128 0x3 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Write the key into the Key Ram. +//! +//! The \c ui32KeyLocation parameter is an enumerated type which specifies +//! the Key Ram location in which the key is stored. +//! +//! The pointer \c pui8AesKey has the address where the Key is stored. +//! +//! \param pui32AesKey is a pointer to an AES Key. +//! \param ui32KeyLocation is the location of the key in Key RAM. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! +//! \return Returns status of the function: +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +// +//***************************************************************************** +extern uint32_t CRYPTOAesLoadKey(uint32_t *pui32AesKey, + uint32_t ui32KeyLocation); + +//***************************************************************************** +// +//! \brief Start an AES-CBC operation (encryption or decryption). +//! +//! The function starts an AES CBC mode encrypt or decrypt operation. +//! End operation can be detected by enabling interrupt or by polling +//! CRYPTOAesCbcStatus(). Result of operation is returned by CRYPTOAesCbcStatus(). +//! +//! \param pui32MsgIn is a pointer to the input data. +//! \param pui32MsgOut is a pointer to the output data. +//! \param ui32MsgLength is the length in bytes of the input data. +//! \param pui32Nonce is a pointer to 16-byte Nonce. +//! \param ui32KeyLocation is the location of the key in Key RAM. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! \param bEncrypt is set \c true to encrypt or set \c false to decrypt. +//! \param bIntEnable is set \c true to enable Crypto interrupts or \c false to +//! disable Crypto interrupt. +//! +//! \return Returns status of the AES-CBC operation: +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +//! +//! \sa \ref CRYPTOAesCbcStatus() +// +//***************************************************************************** +extern uint32_t CRYPTOAesCbc(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, + uint32_t ui32MsgLength, uint32_t *pui32Nonce, + uint32_t ui32KeyLocation, bool bEncrypt, + bool bIntEnable); + +//***************************************************************************** +// +//! \brief Check the result of an AES CBC operation. +//! +//! This function should be called after \ref CRYPTOAesCbc() function to +//! check if the AES CBC operation was successful. +//! +//! \return Returns the status of the AES CBC operation: +//! - \ref AES_SUCCESS : Successful. +//! - \ref AES_DMA_BUS_ERROR : Failed. +//! - \ref AES_DMA_BSY : Operation is ongoing. +//! +//! \sa \ref CRYPTOAesCbc() +// +//***************************************************************************** +extern uint32_t CRYPTOAesCbcStatus(void); + +//***************************************************************************** +// +//! \brief Start an AES-ECB operation (encryption or decryption). +//! +//! The \c ui32KeyLocation parameter is an enumerated type which specifies +//! the Key Ram location in which the key is stored. +//! +//! \param pui32MsgIn is a pointer to the input data. +//! \param pui32MsgOut is a pointer to the output data. +//! \param ui32KeyLocation is the location of the key in Key RAM. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! \param bEncrypt is set \c true to encrypt or set \c false to decrypt. +//! \param bIntEnable is set \c true to enable Crypto interrupts or \c false to +//! disable Crypto interrupt. +//! +//! \return Returns status of the AES-ECB operation: +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +//! +//! \sa \ref CRYPTOAesEcbStatus() +// +//***************************************************************************** +extern uint32_t CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, + uint32_t ui32KeyLocation, bool bEncrypt, + bool bIntEnable); + +//***************************************************************************** +// +//! \brief Check the result of an AES ECB operation. +//! +//! This function should be called after \ref CRYPTOAesEcb() function to +//! check if the AES ECB operation was successful. +//! +//! \return Returns the status of the AES ECB operation: +//! - \ref AES_SUCCESS : Successful. +//! - \ref AES_DMA_BUS_ERROR : Failed. +//! - \ref AES_DMA_BSY : Operation is ongoing. +//! +//! \sa \ref CRYPTOAesEcb() +// +//***************************************************************************** +extern uint32_t CRYPTOAesEcbStatus(void); + +//***************************************************************************** +// +//! \brief Finish the encryption operation by resetting the operation mode. +//! +//! This function should be called after \ref CRYPTOAesEcbStatus() has reported +//! that the operation is finished successfully. +//! +//! \return None +//! +//! \sa \ref CRYPTOAesEcbStatus() +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOAesEcbFinish(void) +{ + // Result has already been copied to the output buffer by DMA. + // Disable master control/DMA clock and clear the operating mode. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000; +} + +//***************************************************************************** +// +//! \brief Finish the encryption operation by resetting the operation mode. +//! +//! This function should be called after \ref CRYPTOAesCbcStatus() has reported +//! that the operation is finished successfully. +//! +//! \return None +//! +//! \sa \ref CRYPTOAesCbcStatus() +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOAesCbcFinish(void) +{ + // Result has already been copied to the output buffer by DMA. + // Disable master control/DMA clock and clear the operating mode. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000; +} + +//***************************************************************************** +// +//! \brief Start CCM operation. +//! +//! The \c ui32KeyLocation is an enumerated type which specifies the Key Ram +//! location in which the key is stored. +//! +//! \param bEncrypt determines whether to run encryption or not. +//! \param ui32AuthLength is the length of the authentication field - +//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. +//! \param pui32Nonce is a pointer to 13-byte or 12-byte Nonce (Number used once). +//! \param pui32PlainText is a pointer to the octet string input message. +//! \param ui32PlainTextLength is the length of the message. +//! \param pui32Header is the length of the header (Additional Authentication +//! Data or AAD). +//! \param ui32HeaderLength is the length of the header in octets. +//! \param ui32KeyLocation is the location in Key RAM where the key is stored. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! \param ui32FieldLength is the size of the length field (2 or 3). +//! \param bIntEnable enables interrupts. +//! +//! \return Returns the status of the CCM operation +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +//! - \ref AES_DMA_BUS_ERROR +//! +//! \sa \ref CRYPTOCcmAuthEncryptStatus() +// +//***************************************************************************** +extern uint32_t CRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength, + uint32_t *pui32Nonce, + uint32_t *pui32PlainText, + uint32_t ui32PlainTextLength, + uint32_t *pui32Header, + uint32_t ui32HeaderLength, + uint32_t ui32KeyLocation, + uint32_t ui32FieldLength, + bool bIntEnable); + +//***************************************************************************** +// +//! \brief Check the result of an AES CCM operation. +//! +//! This function should be called after \ref CRYPTOCcmAuthEncrypt() function to check +//! if the AES CCM operation was successful. +//! +//! \return Returns the status of the AES CCM operation: +//! - \ref AES_SUCCESS : Successful. +//! - \ref AES_DMA_BUS_ERROR : Failed. +//! - \ref AES_DMA_BSY : Operation is ongoing. +//! +//! \sa \ref CRYPTOCcmAuthEncrypt() +// +//***************************************************************************** +extern uint32_t CRYPTOCcmAuthEncryptStatus(void); + +//***************************************************************************** +// +//! \brief Get the result of an AES CCM operation. +//! +//! This function should be called after \ref CRYPTOCcmAuthEncryptStatus(). +//! +//! \param ui32TagLength is length of the Tag. +//! \param pui32CcmTag is the location of the authentication Tag. +//! +//! \return Returns \ref AES_SUCCESS if successful. +//! +//! \sa \ref CRYPTOCcmAuthEncryptStatus() +// +//***************************************************************************** +extern uint32_t CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, + uint32_t *pui32CcmTag); + +//***************************************************************************** +// +//! \brief Start a CCM Decryption and Inverse Authentication operation. +//! +//! The \c ui32KeyLocation is an enumerated type which specifies the Key Ram +//! location in which the key is stored. +//! +//! \param bDecrypt determines whether to run decryption or not. +//! \param ui32AuthLength is the length of the authentication field - +//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. +//! \param pui32Nonce is a pointer to 13-byte or 12-byte Nonce (Number used once). +//! \param pui32CipherText is a pointer to the octet string encrypted message. +//! \param ui32CipherTextLength is the length of the encrypted message. +//! \param pui32Header is the length of the header (Additional Authentication +//! Data or AAD). +//! \param ui32HeaderLength is the length of the header in octets. +//! \param ui32KeyLocation is the location in Key RAM where the key is stored. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! \param ui32FieldLength is the size of the length field (2 or 3). +//! \param bIntEnable enables interrupts. +//! +//! \return Returns the status of the operation: +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +//! - \ref AES_DMA_BUS_ERROR +// +//***************************************************************************** +extern uint32_t CRYPTOCcmInvAuthDecrypt(bool bDecrypt, uint32_t ui32AuthLength, + uint32_t *pui32Nonce, + uint32_t *pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t *pui32Header, + uint32_t ui32HeaderLength, + uint32_t ui32KeyLocation, + uint32_t ui32FieldLength, + bool bIntEnable); + +//***************************************************************************** +// +//! \brief Checks CCM decrypt and Inverse Authentication result. +//! +//! \return Returns status of operation: +//! - \ref AES_SUCCESS : Operation was successful. +//! - \ref AES_DMA_BSY : Operation is busy. +//! - \ref AES_DMA_BUS_ERROR : An error is encountered. +// +//***************************************************************************** +extern uint32_t CRYPTOCcmInvAuthDecryptStatus(void); + +//***************************************************************************** +// +//! \brief Get the result of the CCM operation. +//! +//! \param ui32AuthLength is the length of the authentication field - +//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. +//! \param pui32CipherText is a pointer to the octet string encrypted message. +//! \param ui32CipherTextLength is the length of the encrypted message. +//! \param pui32CcmTag is the location of the authentication Tag. +//! +//! \return Returns AES_SUCCESS if successful. +// +//***************************************************************************** +extern uint32_t CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength, + uint32_t *pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t *pui32CcmTag); + +//***************************************************************************** +// +//! \brief Get the current status of the Crypto DMA controller. +//! +//! This function is used to poll the Crypto DMA controller to check if it is +//! ready for a new operation or if an error has occurred. +//! +//! The \ref CRYPTO_DMA_BUS_ERROR can also be caught using the crypto event +//! handler. +//! +//! \return Returns the current status of the DMA controller: +//! - \ref CRYPTO_DMA_READY : DMA ready for a new operation +//! - \ref CRYPTO_DMA_BSY : DMA is busy +//! - \ref CRYPTO_DMA_BUS_ERROR : DMA Bus error +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CRYPTODmaStatus(void) +{ + // Return the value of the status register. + return (HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT)); +} + +//***************************************************************************** +// +//! \brief Enable Crypto DMA operation. +//! +//! The specified Crypto DMA channels are enabled. +//! +//! \param ui32Channels is a bitwise OR of the channels to enable. +//! - \ref CRYPTO_DMA_CHAN0 +//! - \ref CRYPTO_DMA_CHAN1 +//! +//! \return None +// +//***************************************************************************** +extern void CRYPTODmaEnable(uint32_t ui32Channels); + +//***************************************************************************** +// +//! \brief Disable Crypto DMA operation. +//! +//! The specified Crypto DMA channels are disabled. +//! +//! \param ui32Channels is a bitwise OR of the channels to disable. +//! - \ref CRYPTO_DMA_CHAN0 +//! - \ref CRYPTO_DMA_CHAN1 +//! +//! \return None +// +//***************************************************************************** +extern void CRYPTODmaDisable(uint32_t ui32Channels); + +//***************************************************************************** +// +//! \brief Enables individual Crypto interrupt sources. +//! +//! This function enables the indicated Crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref CRYPTO_DMA_IN_DONE +//! - \ref CRYPTO_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntEnable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) | + (ui32IntFlags & CRYPTO_RESULT_RDY)); + + // Using level interrupt. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + + // Enable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual CRYPTO interrupt sources. +//! +//! This function disables the indicated Crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref CRYPTO_DMA_IN_DONE +//! - \ref CRYPTO_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntDisable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) | + (ui32IntFlags & CRYPTO_RESULT_RDY)); + + // Disable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the specified Crypto. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param bMasked whether to use raw or masked interrupt status: +//! - \c false : Raw interrupt status is required. +//! - \c true : Masked interrupt status is required. +//! +//! \return Returns the current interrupt status: +//! - \ref CRYPTO_DMA_IN_DONE +//! - \ref CRYPTO_RESULT_RDY +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CRYPTOIntStatus(bool bMasked) +{ + uint32_t ui32Mask; + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + ui32Mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); + return(ui32Mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); + } + else + { + return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & 0x00000003); + } +} + +//***************************************************************************** +// +//! \brief Clears Crypto interrupt sources. +//! +//! The specified Crypto interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref CRYPTO_DMA_IN_DONE +//! - \ref CRYPTO_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntClear(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) | + (ui32IntFlags & CRYPTO_RESULT_RDY)); + + // Clear the requested interrupt sources, + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for a Crypto interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific UART interrupts must be enabled via \ref CRYPTOIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, pfnHandler); + + // Enable the UART interrupt. + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a Crypto interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a Crypto interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntUnregister(void) +{ + // Disable the interrupt. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_CRYPTOAesLoadKey + #undef CRYPTOAesLoadKey + #define CRYPTOAesLoadKey ROM_CRYPTOAesLoadKey + #endif + #ifdef ROM_CRYPTOAesCbc + #undef CRYPTOAesCbc + #define CRYPTOAesCbc ROM_CRYPTOAesCbc + #endif + #ifdef ROM_CRYPTOAesCbcStatus + #undef CRYPTOAesCbcStatus + #define CRYPTOAesCbcStatus ROM_CRYPTOAesCbcStatus + #endif + #ifdef ROM_CRYPTOAesEcb + #undef CRYPTOAesEcb + #define CRYPTOAesEcb ROM_CRYPTOAesEcb + #endif + #ifdef ROM_CRYPTOAesEcbStatus + #undef CRYPTOAesEcbStatus + #define CRYPTOAesEcbStatus ROM_CRYPTOAesEcbStatus + #endif + #ifdef ROM_CRYPTOCcmAuthEncrypt + #undef CRYPTOCcmAuthEncrypt + #define CRYPTOCcmAuthEncrypt ROM_CRYPTOCcmAuthEncrypt + #endif + #ifdef ROM_CRYPTOCcmAuthEncryptStatus + #undef CRYPTOCcmAuthEncryptStatus + #define CRYPTOCcmAuthEncryptStatus ROM_CRYPTOCcmAuthEncryptStatus + #endif + #ifdef ROM_CRYPTOCcmAuthEncryptResultGet + #undef CRYPTOCcmAuthEncryptResultGet + #define CRYPTOCcmAuthEncryptResultGet ROM_CRYPTOCcmAuthEncryptResultGet + #endif + #ifdef ROM_CRYPTOCcmInvAuthDecrypt + #undef CRYPTOCcmInvAuthDecrypt + #define CRYPTOCcmInvAuthDecrypt ROM_CRYPTOCcmInvAuthDecrypt + #endif + #ifdef ROM_CRYPTOCcmInvAuthDecryptStatus + #undef CRYPTOCcmInvAuthDecryptStatus + #define CRYPTOCcmInvAuthDecryptStatus ROM_CRYPTOCcmInvAuthDecryptStatus + #endif + #ifdef ROM_CRYPTOCcmInvAuthDecryptResultGet + #undef CRYPTOCcmInvAuthDecryptResultGet + #define CRYPTOCcmInvAuthDecryptResultGet ROM_CRYPTOCcmInvAuthDecryptResultGet + #endif + #ifdef ROM_CRYPTODmaEnable + #undef CRYPTODmaEnable + #define CRYPTODmaEnable ROM_CRYPTODmaEnable + #endif + #ifdef ROM_CRYPTODmaDisable + #undef CRYPTODmaDisable + #define CRYPTODmaDisable ROM_CRYPTODmaDisable + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CRYPTO_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.c new file mode 100644 index 0000000..260a95b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.c @@ -0,0 +1,214 @@ +/****************************************************************************** +* Filename: ddi.c +* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) +* Revision: 52111 +* +* Description: Driver for the DDI master interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ddi.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef DDI32RegWrite + #define DDI32RegWrite NOROM_DDI32RegWrite + #undef DDI16BitWrite + #define DDI16BitWrite NOROM_DDI16BitWrite + #undef DDI16BitfieldWrite + #define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite + #undef DDI16BitRead + #define DDI16BitRead NOROM_DDI16BitRead + #undef DDI16BitfieldRead + #define DDI16BitfieldRead NOROM_DDI16BitfieldRead +#endif + +//***************************************************************************** +// +// Write a 32 bit value to a register in the DDI slave. +// +//***************************************************************************** +void +DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Val) +{ + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Write the value to the register. + HWREG(ui32Base + ui32Reg) = ui32Val; +} + +//***************************************************************************** +// +// Write a single bit using a 16-bit maskable write +// +//***************************************************************************** +void +DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32WrData) +{ + uint32_t ui32RegAddr; + uint32_t ui32Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(!((ui32Mask & 0xFFFF0000) ^ (ui32Mask & 0x0000FFFF))); + ASSERT(!(ui32WrData & 0xFFFF0000)); + + // DDI 16-bit target is on 32-bit boundary so double offset + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // Adjust for target bit in high half of the word. + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 4; + ui32Mask >>= 16; + } + + // Write mask if data is not zero (to set mask bit), else write '0'. + ui32Data = ui32WrData ? ui32Mask : 0x0; + + // Update the register. + HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32Data; +} + +//***************************************************************************** +// +// Write a bit field via the DDI using 16-bit maskable write +// +//***************************************************************************** +void +DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift, + uint16_t ui32Data) +{ + uint32_t ui32RegAddr; + uint32_t ui32WrData; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // 16-bit target is on 32-bit boundary so double offset. + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // Adjust for target bit in high half of the word. + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 4; + ui32Mask = ui32Mask >> 16; + } + + // Shift data in to position. + ui32WrData = ui32Data << ui32Shift; + + // Write data. + HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32WrData; +} + +//***************************************************************************** +// +// Read a bit via the DDI using 16-bit READ. +// +//***************************************************************************** +uint16_t +DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask) +{ + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // Calculate the address of the register. + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // Adjust for target bit in high half of the word. + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // Read a halfword on the DDI interface. + ui16Data = HWREGH(ui32RegAddr); + + // Mask data. + ui16Data = ui16Data & ui32Mask; + + // Return masked data. + return(ui16Data); +} + +//***************************************************************************** +// +// Read a bit field via the DDI using 16-bit read. +// +//***************************************************************************** +uint16_t +DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift) +{ + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // Calculate the register address. + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // Adjust for target bit in high half of the word. + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // Read the register. + ui16Data = HWREGH(ui32RegAddr); + + // Mask data and shift into place. + ui16Data &= ui32Mask; + ui16Data >>= ui32Shift; + + // Return data. + return(ui16Data); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.h new file mode 100644 index 0000000..80d94d2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.h @@ -0,0 +1,462 @@ +/****************************************************************************** +* Filename: ddi.h +* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) +* Revision: 52111 +* +* Description: Defines and prototypes for the DDI master interface. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup analog_group +//! @{ +//! \addtogroup ddi_api +//! @{ +// +//***************************************************************************** + +#ifndef __DDI_H__ +#define __DDI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ddi.h" +#include "../inc/hw_aux_smph.h" +#include "debug.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define DDI32RegWrite NOROM_DDI32RegWrite + #define DDI16BitWrite NOROM_DDI16BitWrite + #define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite + #define DDI16BitRead NOROM_DDI16BitRead + #define DDI16BitfieldRead NOROM_DDI16BitfieldRead +#endif + +//***************************************************************************** +// +// Number of register in the DDI slave +// +//***************************************************************************** +#define DDI_SLAVE_REGS 64 + + +//***************************************************************************** +// +// Defines that is used to control the ADI slave and master +// +//***************************************************************************** +#define DDI_PROTECT 0x00000080 +#define DDI_ACK 0x00000001 +#define DDI_SYNC 0x00000000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + + +//***************************************************************************** +// +// Helper functions +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Check a DDI base address. +//! +//! This function determines if a DDI port base address is valid. +//! +//! \param ui32Base is the base address of the DDI port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +//! +//! \endinternal +// +//***************************************************************************** +static bool +DDIBaseValid(uint32_t ui32Base) +{ + return(ui32Base == AUX_DDI0_OSC_BASE); +} +#endif + + +//***************************************************************************** +// +//! \brief Read the value in a 32 bit register. +//! +//! This function will read a register in the analog domain and return +//! the value as an \c uint32_t. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the 32 bit register to read. +//! +//! \return Returns the 32 bit value of the analog register. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +DDI32RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Read the register and return the value. + return(HWREG(ui32Base + ui32Reg)); +} + +//***************************************************************************** +// +//! \brief Set specific bits in a DDI slave register. +//! +//! This function will set bits in a register in the analog domain. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in specific register in the +//! DDI slave. Only bits in the selected register are affected by the +//! operation. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to set in the register. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_SET; + + // Set the selected bits. + HWREG(ui32Base + ui32RegOffset + ui32Reg) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Clear specific bits in a 32 bit DDI register. +//! +//! This function will clear bits in a register in the analog domain. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to clear in the register. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_CLR; + + // Clear the selected bits. + HWREG(ui32Base + ui32RegOffset + ui32Reg) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Set a value on any 8 bits inside a 32 bit register in the DDI slave. +//! +//! This function allows byte (8 bit access) to the DDI slave registers. +//! +//! Use this function to write any value in the range 0-7 bits aligned on a +//! byte boundary. For example, for writing the value 0b101 to bits 1-3 set +//! ui16Val = 0x0A and ui16Mask = 0x0E. Bits 0 and 5-7 will +//! not be affected by the operation, as long as the corresponding bits are +//! not set in the \c ui16Mask. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is the Least Significant Register in the DDI slave that +//! will be affected by the write operation. +//! \param ui32Byte is the byte number to access within the 32 bit register. +//! \param ui16Mask is the mask defining which of the 8 bits that should be +//! overwritten. The mask must be defined in the lower half of the 16 bits. +//! \param ui16Val is the value to write. The value must be defined in the lower +//! half of the 16 bits. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Byte, + uint16_t ui16Mask, uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + ASSERT(!(ui16Val & 0xFF00)); + ASSERT(!(ui16Mask & 0xFF00)); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_MASK8B + (ui32Reg << 1) + (ui32Byte << 1); + + // Set the selected bits. + HWREGH(ui32Base + ui32RegOffset) = (ui16Mask << 8) | ui16Val; +} + +//***************************************************************************** +// +//! \brief Set a value on any 16 bits inside a 32 bit register aligned on a +//! half-word boundary in the DDI slave. +//! +//! This function allows 16 bit masked access to the DDI slave registers. +//! +//! Use this function to write any value in the range 0-15 bits aligned on a +//! half-word boundary. For example, for writing the value 0b101 to bits 1-3 set +//! ui32Val = 0x000A and ui32Mask = 0x000E. Bits 0 and 5-15 will not be +//! affected by the operation, as long as the corresponding bits are not set +//! in the \c ui32Mask. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param bWriteHigh defines which part of the register to write in. +//! \param ui32Mask is the mask defining which of the 16 bit that should be +//! overwritten. The mask must be defined in the lower half of the 32 bits. +//! \param ui32Val is the value to write. The value must be defined in the lower +//! half of the 32 bits. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh, + uint32_t ui32Mask, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + ASSERT(!(ui32Val & 0xFFFF0000)); + ASSERT(!(ui32Mask & 0xFFFF0000)); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_MASK16B + (ui32Reg << 1) + (bWriteHigh ? 4 : 0); + + // Set the selected bits. + HWREG(ui32Base + ui32RegOffset) = (ui32Mask << 16) | ui32Val; +} + +//***************************************************************************** +// +//! \brief Write a 32 bit value to a register in the DDI slave. +//! +//! This function will write a value to a register in the analog +//! domain. +//! +//! \note This operation is write only for the specified register. No +//! conservation of the previous value of the register will be kept (i.e. this +//! is NOT read-modify-write on the register). +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the register to write. +//! \param ui32Val is the 32 bit value to write to the register. +//! +//! \return None +// +//***************************************************************************** +extern void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val); + +//***************************************************************************** +// +//! \brief Write a single bit using a 16-bit maskable write. +//! +//! A '1' is written to the bit if \c ui32WrData is non-zero, else a '0' is written. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param ui32Mask is the mask defining which of the 16 bit that should be overwritten. +//! \param ui32WrData is the value to write. The value must be defined in the lower half of the 32 bits. +//! +//! \return None +// +//***************************************************************************** +extern void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32WrData); + + +//***************************************************************************** +// +//! \brief Write a bit field via the DDI using 16-bit maskable write. +//! +//! Requires that entire bit field is within the half word boundary. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten. +//! \param ui32Shift is the shift value for the bit field. +//! \param ui32Data is the data aligned to bit 0. +//! +//! \return None +// +//***************************************************************************** +extern void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift, + uint16_t ui32Data); + +//***************************************************************************** +// +//! \brief Read a bit via the DDI using 16-bit read. +//! +//! \param ui32Base is the base address of the DDI module. +//! \param ui32Reg is the register to read. +//! \param ui32Mask defines the bit which should be read. +//! +//! \return Returns a zero if bit selected by mask is '0'. Else returns the mask. +// +//***************************************************************************** +extern uint16_t DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask); + +//***************************************************************************** +// +//! \brief Read a bit field via the DDI using 16-bit read. +//! +//! Requires that entire bit field is within the half word boundary. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten. +//! \param ui32Shift defines the required shift of the data to align with bit 0. +//! +//! \return Returns data aligned to bit 0. +// +//***************************************************************************** +extern uint16_t DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_DDI32RegWrite + #undef DDI32RegWrite + #define DDI32RegWrite ROM_DDI32RegWrite + #endif + #ifdef ROM_DDI16BitWrite + #undef DDI16BitWrite + #define DDI16BitWrite ROM_DDI16BitWrite + #endif + #ifdef ROM_DDI16BitfieldWrite + #undef DDI16BitfieldWrite + #define DDI16BitfieldWrite ROM_DDI16BitfieldWrite + #endif + #ifdef ROM_DDI16BitRead + #undef DDI16BitRead + #define DDI16BitRead ROM_DDI16BitRead + #endif + #ifdef ROM_DDI16BitfieldRead + #undef DDI16BitfieldRead + #define DDI16BitfieldRead ROM_DDI16BitfieldRead + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DDI_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi_doc.h new file mode 100644 index 0000000..86d5c15 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi_doc.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Filename: ddi_doc.h +* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) +* Revision: 47080 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup ddi_api +//! @{ +//! \section sec_ddi Introduction +//! \n +//! +//! \section sec_ddi_api API +//! +//! The API functions can be grouped like this: +//! +//! Write: +//! - Direct (all bits): +//! - \ref DDI32RegWrite() +//! - Set individual bits: +//! - \ref DDI32BitsSet() +//! - Clear individual bits: +//! - \ref DDI32BitsClear() +//! - Masked: +//! - \ref DDI8SetValBit() +//! - \ref DDI16SetValBit() +//! - Special functions using masked write: +//! - \ref DDI16BitWrite() +//! - \ref DDI16BitfieldWrite() +//! +//! Read: +//! - Direct (all bits): +//! - \ref DDI32RegRead() +//! - Special functions using masked read: +//! - \ref DDI16BitRead() +//! - \ref DDI16BitfieldRead() +//! +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/debug.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/debug.c new file mode 100644 index 0000000..5626638 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/debug.c @@ -0,0 +1,57 @@ +/****************************************************************************** +* Filename: debug.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the Debug functionality (NB. This is a stub which +* should never be included in a release). +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include +#include "../inc/hw_types.h" +#include "debug.h" + +//***************************************************************************** +// +// Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted. +// +//***************************************************************************** +void +__error__(char *pcFilename, uint32_t ui32Line) +{ + // Error catching. + // User can implement custom error handling for failing ASSERTs. + // Setting breakpoint here allows tracing of the failing ASSERT. + while( true ); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/debug.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/debug.h new file mode 100644 index 0000000..704fd5c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/debug.h @@ -0,0 +1,84 @@ +/****************************************************************************** +* Filename: debug.h +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Macros for assisting debug of the driver library. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup debug_api +//! @{ +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +//! Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted. +// +//***************************************************************************** +extern void __error__(char *pcFilename, uint32_t ui32Line); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DRIVERLIB_DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } + +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c new file mode 100644 index 0000000..ca51532 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c @@ -0,0 +1,45 @@ +/****************************************************************************** +* Filename: driverlib_release.c +* Revised: $Date: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) $ +* Revision: $Revision: 47152 $ +* +* Description: Provides macros for ensuring that a specfic release of +* DriverLib is used. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#include "../driverlib/driverlib_release.h" + + + + +/// Declare the current DriverLib release +DRIVERLIB_DECLARE_RELEASE(0, 54539); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h new file mode 100644 index 0000000..b7a0434 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h @@ -0,0 +1,156 @@ +/****************************************************************************** +* Filename: driverlib_release.h +* Revised: $Date: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015) $ +* Revision: $Revision: 44151 $ +* +* Description: Provides macros for ensuring that a specfic release of +* DriverLib is used. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup driverlib_release_api +//! @{ +// +//***************************************************************************** + +#ifndef __DRIVERLIB_RELEASE_H__ +#define __DRIVERLIB_RELEASE_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + + + + +/// DriverLib release group number +#define DRIVERLIB_RELEASE_GROUP 0 +/// DriverLib release build number +#define DRIVERLIB_RELEASE_BUILD 54539 + + + + +//***************************************************************************** +// +//! This macro is called internally from within DriverLib to declare the +//! DriverLib release locking object: +//! \param group is the DriverLib release group number. +//! \param build is the DriverLib release build number. +//! +//! This macro shall not be called in the application unless the intention is +//! to bypass the release locking (at own risk). +// +//***************************************************************************** +#define DRIVERLIB_DECLARE_RELEASE(group, build) \ + const volatile uint8_t driverlib_release_##group##_##build + +/// External declaration of the DriverLib release locking object +extern DRIVERLIB_DECLARE_RELEASE(0, 54539); + + + + +//***************************************************************************** +// +//! This macro shall be called once from within a function of a precompiled +//! software deliverable to lock the deliverable to a specific DriverLib +//! release. It is essential that the call is made from code that is not +//! optimized away. +//! +//! This macro locks to a specific DriverLib release: +//! \param group is the DriverLib release group number. +//! \param build is the DriverLib release build number. +//! +//! If attempting to use the precompiled deliverable with a different release +//! of DriverLib, a linker error will be produced, stating that +//! "driverlib_release_xx_yyyyy is undefined" or similar. +//! +//! To override the check, for example when upgrading DriverLib but not the +//! precompiled deliverables, or when mixing precompiled deliverables, +//! application developers may (at own risk) declare the missing DriverLib +//! release using the \ref DRIVERLIB_DECLARE_RELEASE() macro. +// +//***************************************************************************** +#define DRIVERLIB_ASSERT_RELEASE(group, build) \ + (driverlib_release_##group##_##build) + + + + +//***************************************************************************** +// +//! This macro shall be called once from within a function of a precompiled +//! software deliverable to lock the deliverable to a specific DriverLib +//! release. It is essential that the call is made from code that is not +//! optimized away. +//! +//! This macro locks to the current DriverLib release used at compile-time. +//! +//! If attempting to use the precompiled deliverable with a different release +//! of DriverLib, a linker error will be produced, stating that +//! "driverlib_release_xx_yyyyy is undefined" or similar. +//! +//! To override the check, for example when upgrading DriverLib but not the +//! precompiled deliverables, or when mixing precompiled deliverables, +//! application developers may (at own risk) declare the missing DriverLib +//! release using the \ref DRIVERLIB_DECLARE_RELEASE() macro. +// +//***************************************************************************** +#define DRIVERLIB_ASSERT_CURR_RELEASE() \ + DRIVERLIB_ASSERT_RELEASE(0, 54539) + + + + +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_RELEASE_H__ + + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event.c new file mode 100644 index 0000000..0d44d43 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: event.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the Event Fabric. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "event.h" + +// See event.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event.h new file mode 100644 index 0000000..2f84902 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event.h @@ -0,0 +1,267 @@ +/****************************************************************************** +* Filename: event.h +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Defines and prototypes for the Event Handler. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup event_api +//! @{ +// +//***************************************************************************** + +#ifndef __EVENT_H__ +#define __EVENT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_event.h" +#include "debug.h" + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Connects an event to an event subscriber via Event Fabric. +//! +//! This function connects event sources to event subscribers. +//! +//! It is not possible to read event status in this module (except software events). +//! Event status must be read in the module that contains the event source. How a +//! specific event subscriber reacts to an event is configured and documented in +//! the respective modules. +//! +//! For a full list of configurable and constant mapped event sources to event +//! subscribers see the register descriptions for +//! Event Fabric. +//! +//! Defines for event subscriber argument (\c ui32EventSubscriber) have the format: +//! - \ti_code{EVENT_O_[subscriber_name]} +//! +//! Defines for event source argument (\c ui32EventSource) must have the +//! following format where valid \c event_enum values are found in the +//! register description : +//! - \ti_code{EVENT_[subscriber_name]_EV_[event_enum]} +//! +//! Examples of valid defines for \c ui32EventSource: +//! - EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE +//! - EVENT_RFCSEL9_EV_AUX_COMPA +//! - EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD +//! +//! \note Each event subscriber can only receive a sub-set of the event sources! +//! +//! \note Switching the event source is not glitch free, so it is imperative +//! that the subscriber is disabled for interrupts when switching the event +//! source. The behavior is undefined if not disabled. +//! +//! \param ui32EventSubscriber is the \b configurable event subscriber to receive the event. +//! Click the event subscriber to see the list of valid event sources in the +//! register description. +//! - EVENT_O_CPUIRQSEL30 : System CPU interrupt 30 +//! - EVENT_O_RFCSEL9 : RF Core event 9 +//! - EVENT_O_GPT0ACAPTSEL : GPT 0A capture event +//! - EVENT_O_GPT0BCAPTSEL : GPT 0B capture event +//! - EVENT_O_GPT1ACAPTSEL : GPT 1A capture event +//! - EVENT_O_GPT1BCAPTSEL : GPT 1B capture event +//! - EVENT_O_GPT2ACAPTSEL : GPT 2A capture event +//! - EVENT_O_GPT2BCAPTSEL : GPT 2B capture event +//! - EVENT_O_GPT3ACAPTSEL : GPT 3A capture event +//! - EVENT_O_GPT3BCAPTSEL : GPT 3B capture event +//! - EVENT_O_UDMACH9SSEL : uDMA channel 9 single request +//! - EVENT_O_UDMACH9BSEL : uDMA channel 9 burst request +//! - EVENT_O_UDMACH10SSEL : uDMA channel 10 single request +//! - EVENT_O_UDMACH10BSEL : uDMA channel 10 burst request +//! - EVENT_O_UDMACH11SSEL : uDMA channel 11 single request +//! - EVENT_O_UDMACH11BSEL : uDMA channel 11 burst request +//! - EVENT_O_UDMACH12SSEL : uDMA channel 12 single request +//! - EVENT_O_UDMACH12BSEL : uDMA channel 12 burst request +//! - EVENT_O_UDMACH14BSEL : uDMA channel 14 single request +//! - EVENT_O_AUXSEL0 : AUX +//! - EVENT_O_I2SSTMPSEL0 : I2S +//! - EVENT_O_FRZSEL0 : Freeze modules (some modules can freeze on CPU Halt) +//! \param ui32EventSource is the specific event that must be acted upon. +//! - Format: \ti_code{EVENT_[subscriber_name]_EV_[event_enum]} (see explanation above) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +EventRegister(uint32_t ui32EventSubscriber, uint32_t ui32EventSource) +{ + // Check the arguments. + ASSERT(( ui32EventSubscriber == EVENT_O_CPUIRQSEL30 ) || + ( ui32EventSubscriber == EVENT_O_RFCSEL9 ) || + ( ui32EventSubscriber == EVENT_O_GPT0ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT0BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT1ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT1BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT2ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT2BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT3ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT3BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH9SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH9BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH10SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH10BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH11SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH11BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH12SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH12BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH14BSEL ) || + ( ui32EventSubscriber == EVENT_O_AUXSEL0 ) || + ( ui32EventSubscriber == EVENT_O_I2SSTMPSEL0 ) || + ( ui32EventSubscriber == EVENT_O_FRZSEL0 ) ); + + // Map the event source to the event subscriber + HWREG(EVENT_BASE + ui32EventSubscriber) = ui32EventSource; +} + +//***************************************************************************** +// +//! \brief Sets software event. +//! +//! Setting a software event triggers the event if the value was 0 before. +//! +//! \note The software event must be cleared manually after the event has +//! triggered the event subscriber. +//! +//! \param ui32SwEvent is the software event number. +//! - 0 : SW Event 0 +//! - 1 : SW Event 1 +//! - 2 : SW Event 2 +//! - 3 : SW Event 3 +//! +//! \return None +//! +//! \sa \ref EventSwEventClear() +// +//***************************************************************************** +__STATIC_INLINE void +EventSwEventSet(uint32_t ui32SwEvent) +{ + // Check the arguments. + ASSERT( ui32SwEvent <= 3 ); + + // Each software event is byte accessible + HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 1; +} + +//***************************************************************************** +// +//! \brief Clears software event. +//! +//! \param ui32SwEvent is the software event number. +//! - 0 : SW Event 0 +//! - 1 : SW Event 1 +//! - 2 : SW Event 2 +//! - 3 : SW Event 3 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +EventSwEventClear(uint32_t ui32SwEvent) +{ + // Check the arguments. + ASSERT( ui32SwEvent <= 3 ); + + // Each software event is byte accessible + HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 0; +} + +//***************************************************************************** +// +//! \brief Gets software event status. +//! +//! \param ui32SwEvent is the software event number. +//! - 0 : SW Event 0 +//! - 1 : SW Event 1 +//! - 2 : SW Event 2 +//! - 3 : SW Event 3 +//! +//! \return Returns current value of requested software event. +//! - 0 : Software event is de-asserted. +//! - 1 : Software event is asserted. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +EventSwEventGet(uint32_t ui32SwEvent) +{ + // Check the arguments. + ASSERT( ui32SwEvent <= 3 ); + + // Each software event is byte accessible + return( HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent)); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __EVENT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event_doc.h new file mode 100644 index 0000000..a17b238 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event_doc.h @@ -0,0 +1,58 @@ +/****************************************************************************** +* Filename: event_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup event_api +//! @{ +//! \section sec_event Introduction +//! +//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and +//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers +//! to the AON event fabric. For more information on AON event fabric, see [AON event API](@ref aonevent_api). +//! +//! The MCU event fabric is a combinational router between event sources and event subscribers. Most +//! event subscribers have statically routed event sources but several event subscribers have +//! configurable event sources which is configured in the MCU event fabric through this API. Although +//! configurable only a subset of event sources are available to each of the configurable event subscribers. +//! This is explained in more details in the function @ref EventRegister() which does all the event routing +//! configuration. +//! +//! MCU event fabric also contains four software events which allow software to trigger certain event +//! subscribers. Each of the four software events is an independent event source which must be set and +//! cleared in the MCU event fabric through the functions: +//! - @ref EventSwEventSet() +//! - @ref EventSwEventClear() +//! - @ref EventSwEventGet() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/flash.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/flash.c new file mode 100644 index 0000000..e99aa48 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/flash.c @@ -0,0 +1,672 @@ +/****************************************************************************** +* Filename: flash.c +* Revised: 2017-10-30 13:37:49 +0100 (Mon, 30 Oct 2017) +* Revision: 50105 +* +* Description: Driver for on chip Flash. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "flash.h" +#include "rom.h" +#include "chipinfo.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef FlashPowerModeSet + #define FlashPowerModeSet NOROM_FlashPowerModeSet + #undef FlashPowerModeGet + #define FlashPowerModeGet NOROM_FlashPowerModeGet + #undef FlashProtectionSet + #define FlashProtectionSet NOROM_FlashProtectionSet + #undef FlashProtectionGet + #define FlashProtectionGet NOROM_FlashProtectionGet + #undef FlashProtectionSave + #define FlashProtectionSave NOROM_FlashProtectionSave + #undef FlashSectorErase + #define FlashSectorErase NOROM_FlashSectorErase + #undef FlashProgram + #define FlashProgram NOROM_FlashProgram + #undef FlashEfuseReadRow + #define FlashEfuseReadRow NOROM_FlashEfuseReadRow + #undef FlashDisableSectorsForWrite + #define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite +#endif + + +//***************************************************************************** +// +// Defines for accesses to the security control in the customer configuration +// area in flash top sector. +// +//***************************************************************************** +#define CCFG_OFFSET_SECURITY CCFG_O_BL_CONFIG +#define CCFG_OFFSET_SECT_PROT CCFG_O_CCFG_PROT_31_0 +#define CCFG_SIZE_SECURITY 0x00000014 +#define CCFG_SIZE_SECT_PROT 0x00000004 + +//***************************************************************************** +// +// Default values for security control in customer configuration area in flash +// top sector. +// +//***************************************************************************** +const uint8_t g_pui8CcfgDefaultSec[] = {0xFF, 0xFF, 0xFF, 0xC5, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xC5, 0xFF, 0xFF, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF + }; + +typedef uint32_t (* FlashPrgPointer_t) (uint8_t *, uint32_t, uint32_t); + +typedef uint32_t (* FlashSectorErasePointer_t) (uint32_t); + +//***************************************************************************** +// +// Function prototypes for static functions +// +//***************************************************************************** +static void SetReadMode(void); + +//***************************************************************************** +// +// Set power mode +// +//***************************************************************************** +void +FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, + uint32_t ui32PumpGracePeriod) +{ + // Check the arguments. + ASSERT(ui32PowerMode == FLASH_PWR_ACTIVE_MODE || + ui32PowerMode == FLASH_PWR_OFF_MODE || + ui32PowerMode == FLASH_PWR_DEEP_STDBY_MODE); + ASSERT(ui32BankGracePeriod <= 0xFF); + ASSERT(ui32PumpGracePeriod <= 0xFFFF); + + switch(ui32PowerMode) + { + case FLASH_PWR_ACTIVE_MODE: + // Set bank power mode to ACTIVE. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = + (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_ACTIVE; + + // Set charge pump power mode to ACTIVE mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) = + (HWREG(FLASH_BASE + FLASH_O_FPAC1) & ~FLASH_FPAC1_PUMPPWR_M) | (1 << FLASH_FPAC1_PUMPPWR_S); + break; + + case FLASH_PWR_OFF_MODE: + // Set bank grace period. + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // Set pump grace period. + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // Set bank power mode to SLEEP. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= ~FLASH_FBFALLBACK_BANKPWR0_M; + + // Set charge pump power mode to SLEEP mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M; + break; + + case FLASH_PWR_DEEP_STDBY_MODE: + // Set bank grace period. + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // Set pump grace period. + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // Set bank power mode to DEEP STANDBY mode. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = + (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_DEEP_STDBY; + + // Set charge pump power mode to STANDBY mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) |= FLASH_FPAC1_PUMPPWR_M; + break; + } +} + +//***************************************************************************** +// +// Get current configured power mode +// +//***************************************************************************** +uint32_t +FlashPowerModeGet(void) +{ + uint32_t ui32PowerMode; + uint32_t ui32BankPwrMode; + + ui32BankPwrMode = HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + FLASH_FBFALLBACK_BANKPWR0_M; + + if(ui32BankPwrMode == FBFALLBACK_SLEEP) + { + ui32PowerMode = FLASH_PWR_OFF_MODE; + } + else if(ui32BankPwrMode == FBFALLBACK_DEEP_STDBY) + { + ui32PowerMode = FLASH_PWR_DEEP_STDBY_MODE; + } + else + { + ui32PowerMode = FLASH_PWR_ACTIVE_MODE; + } + + // Return power mode. + return(ui32PowerMode); +} + +//***************************************************************************** +// +// Set sector protection +// +//***************************************************************************** +void +FlashProtectionSet(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode) +{ + uint32_t ui32SectorNumber; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(ui32ProtectMode == FLASH_WRITE_PROTECT) + { + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / + FlashSectorSizeGet(); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + if(ui32SectorNumber <= 31) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber); + } + else if(ui32SectorNumber <= 63) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |= + (1 << (ui32SectorNumber & 0x1F)); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |= + (1 << (ui32SectorNumber & 0x1F)); + } + + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } +} + +//***************************************************************************** +// +// Get sector protection +// +//***************************************************************************** +uint32_t +FlashProtectionGet(uint32_t ui32SectorAddress) +{ + uint32_t ui32SectorProtect; + uint32_t ui32SectorNumber; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + ui32SectorProtect = FLASH_NO_PROTECT; + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + + if(ui32SectorNumber <= 31) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + else if(ui32SectorNumber <= 63) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) & + (1 << (ui32SectorNumber & 0x1F))) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) & + (1 << (ui32SectorNumber & 0x1F)))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + + return(ui32SectorProtect); +} + +//***************************************************************************** +// +// Save sector protection to make it permanent +// +//***************************************************************************** +uint32_t +FlashProtectionSave(uint32_t ui32SectorAddress) +{ + uint32_t ui32ErrorReturn; + uint32_t ui32SectorNumber; + uint32_t ui32CcfgSectorAddr; + uint32_t ui32ProgBuf; + + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(FlashProtectionGet(ui32SectorAddress) == FLASH_WRITE_PROTECT) + { + // Find sector number for specified sector. + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + ui32CcfgSectorAddr = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); + + // Adjust CCFG address to the 32-bit CCFG word holding the + // protect-bit for the specified sector. + ui32CcfgSectorAddr += (((ui32SectorNumber >> 5) * 4) + CCFG_OFFSET_SECT_PROT); + + // Find value to program by setting the protect-bit which + // corresponds to specified sector number, to 0. + // Leave other protect-bits unchanged. + ui32ProgBuf = (~(1 << (ui32SectorNumber & 0x1F))) & + *(uint32_t *)ui32CcfgSectorAddr; + + ui32ErrorReturn = FlashProgram((uint8_t*)&ui32ProgBuf, ui32CcfgSectorAddr, + CCFG_SIZE_SECT_PROT); + } + + // Return status. + return(ui32ErrorReturn); +} + +//***************************************************************************** +// +// Erase a flash sector +// +//***************************************************************************** +uint32_t +FlashSectorErase(uint32_t ui32SectorAddress) +{ + uint32_t ui32ErrorReturn; + FlashSectorErasePointer_t FuncPointer; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + // Call ROM function that handles the actual erase operation + FuncPointer = (uint32_t (*)(uint32_t)) (ROM_API_FLASH_TABLE[5]); + ui32ErrorReturn = FuncPointer(ui32SectorAddress); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); + +} + + +//***************************************************************************** +// +// Programs unprotected main bank flash sectors +// +//***************************************************************************** +uint32_t +FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) +{ + uint32_t ui32ErrorReturn; + FlashPrgPointer_t FuncPointer; + + // Check the arguments. + ASSERT((ui32Address + ui32Count) <= (FLASHMEM_BASE + FlashSizeGet())); + + // Call ROM function that handles the actual program operation + FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ROM_API_FLASH_TABLE[6]); + ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); + +} + +//***************************************************************************** +// +// Reads efuse data from specified row +// +//***************************************************************************** +bool +FlashEfuseReadRow(uint32_t *pui32EfuseData, uint32_t ui32RowAddress) +{ + bool bStatus; + + // Make sure the clock for the efuse is enabled + HWREG(FLASH_BASE + FLASH_O_CFG) &= ~FLASH_CFG_DIS_EFUSECLK; + + // Set timing for EFUSE read operations. + HWREG(FLASH_BASE + FLASH_O_EFUSEREAD) |= ((5 << FLASH_EFUSEREAD_READCLOCK_S) & + FLASH_EFUSEREAD_READCLOCK_M); + + // Clear status register. + HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) = 0; + + // Select the FuseROM block 0. + HWREG(FLASH_BASE + FLASH_O_EFUSEADDR) = 0x00000000; + + // Start the read operation. + HWREG(FLASH_BASE + FLASH_O_EFUSE) = + (DUMPWORD_INSTR << FLASH_EFUSE_INSTRUCTION_S) | + (ui32RowAddress & FLASH_EFUSE_DUMPWORD_M); + + // Wait for operation to finish. + while(!(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_DONE)) + { + } + + // Check if error reported. + if(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_CODE_M) + { + // Set error status. + bStatus = 1; + + // Clear data. + *pui32EfuseData = 0; + } + else + { + // Set ok status. + bStatus = 0; + + // No error. Get data from data register. + *pui32EfuseData = HWREG(FLASH_BASE + FLASH_O_DATALOWER); + } + + // Disable the efuse clock to conserve power + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_EFUSECLK; + + // Return the data. + return(bStatus); +} + + +//***************************************************************************** +// +// Disables all sectors for erase and programming on the active bank +// +//***************************************************************************** +void +FlashDisableSectorsForWrite(void) +{ + // Configure flash back to read mode + SetReadMode(); + + // Disable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + // Disable all sectors for erase and programming. + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; + + // Enable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Protect sectors from sector erase. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \internal +//! Used to set flash in read mode. +//! +//! Flash is configured with values loaded from OTP dependent on the current +//! regulator mode. +//! +//! \return None. +// +//***************************************************************************** +static void +SetReadMode(void) +{ + uint32_t ui32TrimValue; + uint32_t ui32Value; + + // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + // VIN_AT_X and VIN_BY_PASS for read mode + if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & + AON_PMCTL_PWRCTL_EXT_REG_MODE) + { + // Select trim values for external regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 4). + // Configure DIS_IDLE (OTP offset 0x308 bit 3). + ui32Value |= ((ui32TrimValue & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // Wait for disabled sample and hold functionality to be stable. + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 2:0) + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } + else + { + // Select trim values for internal regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 12). + // Configure DIS_IDLE (OTP offset 0x308 bit 11). + ui32Value |= ((ui32TrimValue & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // Wait for disabled sample and hold functionality to be stable. + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 10:8) + ui32Value = (((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S); + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} + +//***************************************************************************** +// +// HAPI Flash program function +// +//***************************************************************************** +uint32_t +MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer, uint32_t ui32Address, + uint32_t ui32Count) +{ + uint32_t ui32ErrorReturn; + FlashPrgPointer_t FuncPointer; + uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (5 * 4)); + + // Call ROM function + FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ui32RomAddr); + ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); +} + +//***************************************************************************** +// +// HAPI Flash sector erase function +// +//***************************************************************************** +uint32_t +MemBusWrkAroundHapiEraseSector(uint32_t ui32Address) +{ + uint32_t ui32ErrorReturn; + + FlashSectorErasePointer_t FuncPointer; + uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (3 * 4)); + + // Call ROM function + FuncPointer = (uint32_t (*)(uint32_t)) (ui32RomAddr); + ui32ErrorReturn = FuncPointer(ui32Address); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h new file mode 100644 index 0000000..ec17488 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h @@ -0,0 +1,817 @@ +/****************************************************************************** +* Filename: flash.h +* Revised: 2017-11-02 16:09:32 +0100 (Thu, 02 Nov 2017) +* Revision: 50166 +* +* Description: Defines and prototypes for the Flash driver. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_flash.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aon_pmctl.h" +#include "../inc/hw_fcfg1.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define FlashPowerModeSet NOROM_FlashPowerModeSet + #define FlashPowerModeGet NOROM_FlashPowerModeGet + #define FlashProtectionSet NOROM_FlashProtectionSet + #define FlashProtectionGet NOROM_FlashProtectionGet + #define FlashProtectionSave NOROM_FlashProtectionSave + #define FlashSectorErase NOROM_FlashSectorErase + #define FlashProgram NOROM_FlashProgram + #define FlashEfuseReadRow NOROM_FlashEfuseReadRow + #define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite +#endif + +//***************************************************************************** +// +// Values that can be returned from the API functions +// +//***************************************************************************** +#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully +#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy +#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready +#define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH \ + 0x00000003 // Incorrect parameter value +#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed + +//***************************************************************************** +// +// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and +// returned from FlashIntStatus(). +// +//***************************************************************************** +#define FLASH_INT_FSM_DONE 0x00400000 // FSM Done Interrupt Mask +#define FLASH_INT_RV 0x00010000 // Read Verify error Interrupt Mask + +//***************************************************************************** +// +// Values passed to FlashSetPowerMode() and returned from FlashGetPowerMode(). +// +//***************************************************************************** +#define FLASH_PWR_ACTIVE_MODE 0x00000000 +#define FLASH_PWR_OFF_MODE 0x00000001 +#define FLASH_PWR_DEEP_STDBY_MODE \ + 0x00000002 + +//***************************************************************************** +// +// Values passed to FlashSetProtection() and returned from FlashGetProtection(). +// +//***************************************************************************** +#define FLASH_NO_PROTECT 0x00000000 // Sector not protected +#define FLASH_WRITE_PROTECT 0x00000001 // Sector erase and program + // protected + +//***************************************************************************** +// +// Define used by the flash programming and erase functions +// +//***************************************************************************** +#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE) + +//***************************************************************************** +// +// Define used for access to factory configuration area. +// +//***************************************************************************** +#define FCFG1_OFFSET 0x1000 + +//***************************************************************************** +// +// Define for the clock frequency input to the flash module in number of MHz +// +//***************************************************************************** +#define FLASH_MODULE_CLK_FREQ 48 + +//***************************************************************************** +// +//! \brief Defined values for Flash State Machine commands +// +//***************************************************************************** +typedef enum +{ + FAPI_PROGRAM_DATA = 0x0002, //!< Program data. + FAPI_ERASE_SECTOR = 0x0006, //!< Erase sector. + FAPI_ERASE_BANK = 0x0008, //!< Erase bank. + FAPI_VALIDATE_SECTOR = 0x000E, //!< Validate sector. + FAPI_CLEAR_STATUS = 0x0010, //!< Clear status. + FAPI_PROGRAM_RESUME = 0x0014, //!< Program resume. + FAPI_ERASE_RESUME = 0x0016, //!< Erase resume. + FAPI_CLEAR_MORE = 0x0018, //!< Clear more. + FAPI_PROGRAM_SECTOR = 0x0020, //!< Program sector. + FAPI_ERASE_OTP = 0x0030 //!< Erase OTP. +} tFlashStateCommandsType; + +//***************************************************************************** +// +// Defines for values written to the FLASH_O_FSM_WR_ENA register +// +//***************************************************************************** +#define FSM_REG_WRT_ENABLE 5 +#define FSM_REG_WRT_DISABLE 2 + +//***************************************************************************** +// +// Defines for the bank power mode field the FLASH_O_FBFALLBACK register +// +//***************************************************************************** +#define FBFALLBACK_SLEEP 0 +#define FBFALLBACK_DEEP_STDBY 1 +#define FBFALLBACK_ACTIVE 3 + +//***************************************************************************** +// +// Defines for the bank grace period and pump grace period +// +//***************************************************************************** +#define FLASH_BAGP 0x14 +#define FLASH_PAGP 0x14 + +//***************************************************************************** +// +// Defines used by the FlashProgramPattern() function +// +//***************************************************************************** +#define PATTERN_BITS 0x20 // No of bits in data pattern to program + +//***************************************************************************** +// +// Defines for the FW flag bits in the FLASH_O_FWFLAG register +// +//***************************************************************************** +#define FW_WRT_TRIMMED 0x00000001 + +//***************************************************************************** +// +// Defines used by the flash programming functions +// +//***************************************************************************** +typedef volatile uint8_t tFwpWriteByte; +#define FWPWRITE_BYTE_ADDRESS ((tFwpWriteByte *)((FLASH_BASE + FLASH_O_FWPWRITE0))) + +//***************************************************************************** +// +// Define for efuse instruction +// +//***************************************************************************** +#define DUMPWORD_INSTR 0x04 + +//***************************************************************************** +// +// Define for FSM command execution +// +//***************************************************************************** +#define FLASH_CMD_EXEC 0x15 + +//***************************************************************************** +// +//! \brief Get size of a flash sector in number of bytes. +//! +//! This function will return the size of a flash sector in number of bytes. +//! +//! \return Returns size of a flash sector in number of bytes. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashSectorSizeGet(void) +{ + uint32_t ui32SectorSizeInKbyte; + + ui32SectorSizeInKbyte = (HWREG(FLASH_BASE + FLASH_O_FCFG_B0_SSIZE0) & + FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M) >> + FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S; + + // Return flash sector size in number of bytes. + return(ui32SectorSizeInKbyte * 1024); +} + +//***************************************************************************** +// +//! \brief Get the size of the flash. +//! +//! This function returns the size of the flash main bank in number of bytes. +//! +//! \return Returns the flash size in number of bytes. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashSizeGet(void) +{ + uint32_t ui32NoOfSectors; + + // Get number of flash sectors + ui32NoOfSectors = (HWREG(FLASH_BASE + FLASH_O_FLASH_SIZE) & + FLASH_FLASH_SIZE_SECTORS_M) >> + FLASH_FLASH_SIZE_SECTORS_S; + + // Return flash size in number of bytes + return(ui32NoOfSectors * FlashSectorSizeGet()); +} + +//***************************************************************************** +// +//! \brief Set power mode. +//! +//! This function will set the specified power mode. +//! +//! Any access to the bank causes a reload of the specified bank grace period +//! input value into the bank down counter. After the last access to the +//! flash bank, the down counter delays from 0 to 255 prescaled HCLK clock +//! cycles before putting the bank into one of the fallback power modes as +//! determined by \c ui32PowerMode. This value must be greater than 1 when the +//! fallback mode is not \ref FLASH_PWR_ACTIVE_MODE. +//! +//! Note: The prescaled clock used for the down counter is a clock divided by +//! 16 from input HCLK. The \c ui32BankGracePeriod parameter is ignored if +//! \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE. +//! Any access to flash memory causes the pump grace period down counter to +//! reload with value of \c ui32PumpGracePeriod. After the bank has gone to sleep, +//! the down counter delays this number of prescaled HCLK clock cycles before +//! entering one of the charge pump fallback power modes as determined by +//! \c ui32PowerMode. The prescaled clock used for the pump grace period down +//! counter is a clock divided by 16 from input HCLK. This parameter is ignored +//! if \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE. +//! +//! Changing the power mode of the flash module must be a part within a +//! device power mode transition requiring configuration of multiple modules. +//! Refer to documents describing the device power modes. +//! +//! \param ui32PowerMode is the wanted power mode. +//! The defined flash power modes are: +//! - \ref FLASH_PWR_ACTIVE_MODE +//! - \ref FLASH_PWR_OFF_MODE +//! - \ref FLASH_PWR_DEEP_STDBY_MODE +//! \param ui32BankGracePeriod is the starting count value for the bank grace +//! period down counter. +//! \param ui32PumpGracePeriod is the starting count value for the pump grace +//! period down counter. +//! +//! \return None +// +//***************************************************************************** +extern void FlashPowerModeSet(uint32_t ui32PowerMode, + uint32_t ui32BankGracePeriod, + uint32_t ui32PumpGracePeriod); + +//***************************************************************************** +// +//! \brief Get current configured power mode. +//! +//! This function will return the current configured power mode. +//! +//! \return Returns the current configured power mode. +//! The defined power modes are: +//! - \ref FLASH_PWR_ACTIVE_MODE +//! - \ref FLASH_PWR_OFF_MODE +//! - \ref FLASH_PWR_DEEP_STDBY_MODE +// +//***************************************************************************** +extern uint32_t FlashPowerModeGet(void); + +//***************************************************************************** +// +//! \brief Set sector protection. +//! +//! This function will set the specified protection on specified flash bank +//! sector. A sector can either have no protection or have write protection +//! which guards for both program and erase of that sector. +//! Sector protection can only be changed from \ref FLASH_NO_PROTECT to +//! \ref FLASH_WRITE_PROTECT! After write protecting a sector this sector can +//! only be set back to unprotected by a device reset. +//! +//! \param ui32SectorAddress is the start address of the sector to protect. +//! \param ui32ProtectMode is the enumerated sector protection mode. +//! - \ref FLASH_NO_PROTECT +//! - \ref FLASH_WRITE_PROTECT +//! +//! \return None +// +//***************************************************************************** +extern void FlashProtectionSet(uint32_t ui32SectorAddress, + uint32_t ui32ProtectMode); + +//***************************************************************************** +// +//! \brief Get sector protection. +//! +//! This return the protection mode for the specified flash bank sector. +//! +//! \param ui32SectorAddress is the start address of the desired sector. +//! +//! \return Returns the sector protection: +//! - \ref FLASH_NO_PROTECT +//! - \ref FLASH_WRITE_PROTECT +// +//***************************************************************************** +extern uint32_t FlashProtectionGet(uint32_t ui32SectorAddress); + +//***************************************************************************** +// +//! \brief Save sector protection to make it permanent. +//! +//! This function will save the current protection mode for the specified +//! flash bank sector. +//! +//! This function must only be executed from ROM or SRAM. +//! +//! \note A write protected sector will become permanent write +//! protected!! A device reset will not change the write protection! +//! +//! \param ui32SectorAddress is the start address of the sector to be protected. +//! +//! \return Returns the status of the sector protection: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_FSM_ERROR : An erase error is encountered. +// +//***************************************************************************** +extern uint32_t FlashProtectionSave(uint32_t ui32SectorAddress); + +//***************************************************************************** +// +//! \brief Checks if the Flash state machine has detected an error. +//! +//! This function returns the status of the Flash State Machine indicating if +//! an error is detected or not. Primary use is to check if an Erase or +//! Program operation has failed. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. This function must be called from ROM or +//! SRAM while any part of the flash is being programmed or erased. +//! +//! \return Returns status of Flash state machine: +//! - \ref FAPI_STATUS_FSM_ERROR +//! - \ref FAPI_STATUS_SUCCESS +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashCheckFsmForError(void) +{ + if(HWREG(FLASH_BASE + FLASH_O_FMSTAT) & FLASH_FMSTAT_CSTAT) + { + return(FAPI_STATUS_FSM_ERROR); + } + else + { + return(FAPI_STATUS_SUCCESS); + } +} + +//***************************************************************************** +// +//! \brief Checks if the Flash state machine is ready. +//! +//! This function returns the status of the Flash State Machine indicating if +//! it is ready to accept a new command or not. Primary use is to check if an +//! Erase or Program operation has finished. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. This function must be called from ROM or +//! SRAMh while any part of the flash is being programmed or erased. +//! +//! \return Returns readiness status of Flash state machine: +//! - \ref FAPI_STATUS_FSM_READY +//! - \ref FAPI_STATUS_FSM_BUSY +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashCheckFsmForReady(void) +{ + if(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_BUSY) + { + return(FAPI_STATUS_FSM_BUSY); + } + else + { + return(FAPI_STATUS_FSM_READY); + } +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the flash interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific FLASH interrupts must be enabled via \ref FlashIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the flash +//! interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_FLASH, pfnHandler); + + // Enable the flash interrupt. + IntEnable(INT_FLASH); +} + +//***************************************************************************** +// +//! \brief Unregisters the interrupt handler for the flash interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a FLASH interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntUnregister(void) +{ + // Disable the interrupts. + IntDisable(INT_FLASH); + + // Unregister the interrupt handler. + IntUnregister(INT_FLASH); +} + +//***************************************************************************** +// +//! \brief Enables flash controller interrupt sources. +//! +//! This function enables the flash controller interrupt sources. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt. +//! - \ref FLASH_INT_RV : Read verify error interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntEnable(uint32_t ui32IntFlags) +{ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= ui32IntFlags; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \brief Disables individual flash controller interrupt sources. +//! +//! This function disables the flash controller interrupt sources. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt. +//! - \ref FLASH_INT_RV : Read verify error interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntDisable(uint32_t ui32IntFlags) +{ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~ui32IntFlags; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the Flash. +//! +//! \return Returns the current interrupt status as values described in +//! \ref FlashIntEnable(). +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashIntStatus(void) +{ + uint32_t ui32IntFlags; + + ui32IntFlags = 0; + + // Check if FSM_DONE interrupt status is set. + if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_FSM_DONE) + { + ui32IntFlags = FLASH_INT_FSM_DONE; + } + + // Check if RVF_INT interrupt status is set. + if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_RVF_INT) + { + ui32IntFlags |= FLASH_INT_RV; + } + + return(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Clears flash controller interrupt source. +//! +//! The flash controller interrupt source is cleared, so that it no longer +//! asserts. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared. +//! Can be any of: +//! - \ref FLASH_INT_FSM_DONE +//! - \ref FLASH_INT_RV +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntClear(uint32_t ui32IntFlags) +{ + uint32_t ui32TempVal; + + ui32TempVal = 0; + + if(ui32IntFlags & FLASH_INT_FSM_DONE) + { + ui32TempVal = FLASH_FEDACSTAT_FSM_DONE; + } + + if(ui32IntFlags & FLASH_INT_RV) + { + ui32TempVal |= FLASH_FEDACSTAT_RVF_INT; + } + + // Clear the flash interrupt source. + HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) = ui32TempVal; +} + +//***************************************************************************** +// +//! \brief Erase a flash sector. +//! +//! This function will erase the specified flash sector. The function will +//! not return until the flash sector has been erased or an error condition +//! occurred. If flash top sector is erased the function will program the +//! the device security data bytes with default values. The device security +//! data located in the customer configuration area of the flash top sector, +//! must have valid values at all times. These values affect the configuration +//! of the device during boot. +//! +//! \warning Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. The application must disable interrupts that have +//! interrupt routines in flash. This function calls a ROM function which handles the +//! actual program operation. +//! +//! \param ui32SectorAddress is the starting address in flash of the sector to be +//! erased. +//! +//! \return Returns the status of the sector erase: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Invalid argument. +//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered. +// +//***************************************************************************** +extern uint32_t FlashSectorErase(uint32_t ui32SectorAddress); + + +//***************************************************************************** +// +//! \brief Programs unprotected flash sectors in the main bank. +//! +//! This function programs a sequence of bytes into the on-chip flash. +//! Programming each location consists of the result of an AND operation +//! of the new data and the existing data; in other words bits that contain +//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed +//! to 1. Therefore, a byte can be programmed multiple times as long as these +//! rules are followed; if a program operation attempts to change a 0 bit to +//! a 1 bit, that bit will not have its value changed. +//! +//! This function does not return until the data has been programmed or a +//! programming error occurs. +//! +//! \note It is recommended to disable cache and line buffer before programming the +//! flash. Cache and line buffer are not automatically updated if a flash program +//! causes a mismatch between new flash content and old content in cache and +//! line buffer. Remember to enable cache and line buffer when the program +//! operation completes. See \ref VIMSModeSafeSet(), \ref VIMSLineBufDisable(), +//! and \ref VIMSLineBufEnable() for more information. +//! +//! \warning Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. The application must disable interrupts that have +//! interrupt routines in flash. This function calls a ROM function which handles the +//! actual program operation. +//! +//! The \c pui8DataBuffer pointer can not point to flash. +//! +//! \param pui8DataBuffer is a pointer to the data to be programmed. +//! \param ui32Address is the starting address in flash to be programmed. +//! \param ui32Count is the number of bytes to be programmed. +//! +//! \return Returns status of the flash programming: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Too many bytes were requested. +//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered. +// +//***************************************************************************** +extern uint32_t FlashProgram(uint8_t *pui8DataBuffer, + uint32_t ui32Address, uint32_t ui32Count); + +//***************************************************************************** +// +//! \brief Reads efuse data from specified row. +//! +//! This function will read one efuse row. +//! It is assumed that any previous efuse operation has finished. +//! +//! \param pui32EfuseData is pointer to variable to be updated with efuse data. +//! \param ui32RowAddress is the efuse row number to be read. First row is row +//! number 0. +//! +//! \return Returns the status of the efuse read operation. +//! - \c false : OK status. +//! - \c true : Error status +// +//***************************************************************************** +extern bool FlashEfuseReadRow(uint32_t *pui32EfuseData, + uint32_t ui32RowAddress); + +//***************************************************************************** +// +//! \brief Disables all sectors for erase and programming on the active bank. +//! +//! This function disables all sectors for erase and programming on the active +//! bank and enables the Idle Reading Power reduction mode if no low power +//! mode is configured. Furthermore, an additional level of protection from +//! erase is enabled. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. +//! +//! \return None +// +//***************************************************************************** +extern void FlashDisableSectorsForWrite(void); + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_FlashPowerModeSet + #undef FlashPowerModeSet + #define FlashPowerModeSet ROM_FlashPowerModeSet + #endif + #ifdef ROM_FlashPowerModeGet + #undef FlashPowerModeGet + #define FlashPowerModeGet ROM_FlashPowerModeGet + #endif + #ifdef ROM_FlashProtectionSet + #undef FlashProtectionSet + #define FlashProtectionSet ROM_FlashProtectionSet + #endif + #ifdef ROM_FlashProtectionGet + #undef FlashProtectionGet + #define FlashProtectionGet ROM_FlashProtectionGet + #endif + #ifdef ROM_FlashProtectionSave + #undef FlashProtectionSave + #define FlashProtectionSave ROM_FlashProtectionSave + #endif + #ifdef ROM_FlashSectorErase + #undef FlashSectorErase + #define FlashSectorErase ROM_FlashSectorErase + #endif + #ifdef ROM_FlashProgram + #undef FlashProgram + #define FlashProgram ROM_FlashProgram + #endif + #ifdef ROM_FlashEfuseReadRow + #undef FlashEfuseReadRow + #define FlashEfuseReadRow ROM_FlashEfuseReadRow + #endif + #ifdef ROM_FlashDisableSectorsForWrite + #undef FlashDisableSectorsForWrite + #define FlashDisableSectorsForWrite ROM_FlashDisableSectorsForWrite + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.c new file mode 100644 index 0000000..fcc316a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: gpio.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the GPIO +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "gpio.h" + +// see gpio.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.h new file mode 100644 index 0000000..9a4bf16 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.h @@ -0,0 +1,643 @@ +/****************************************************************************** +* Filename: gpio.h +* Revised: 2018-05-02 11:11:40 +0200 (Wed, 02 May 2018) +* Revision: 51951 +* +* Description: Defines and prototypes for the GPIO. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup gpio_api +//! @{ +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_gpio.h" +#include "debug.h" + +//***************************************************************************** +// +// Check for legal range of variable dioNumber +// +//***************************************************************************** +#ifdef DRIVERLIB_DEBUG +#include "../inc/hw_fcfg1.h" +#include "chipinfo.h" + +static bool +dioNumberLegal( uint32_t dioNumber ) +{ + uint32_t ioCount = + (( HWREG( FCFG1_BASE + FCFG1_O_IOCONF ) & + FCFG1_IOCONF_GPIO_CNT_M ) >> + FCFG1_IOCONF_GPIO_CNT_S ) ; + + // CC13x2 + CC26x2 + if ( ChipInfo_ChipFamilyIs_CC13x2_CC26x2() ) + { + return ( (dioNumber >= (31 - ioCount)) && (dioNumber < 31) ) + } + // Special handling of CC13x0 7x7, where IO_CNT = 30 and legal range is 1..30 + // for all other chips legal range is 0..(dioNumber-1) + else if (( ioCount == 30 ) && ChipInfo_ChipFamilyIs_CC13x0() ) + { + return (( dioNumber > 0 ) && ( dioNumber <= ioCount )); + } + else + { + return ( dioNumber < ioCount ); + } + +} +#endif + +//***************************************************************************** +// +// The following values define the bit field for the GPIO DIOs. +// +//***************************************************************************** +#define GPIO_DIO_0_MASK 0x00000001 // GPIO DIO 0 mask +#define GPIO_DIO_1_MASK 0x00000002 // GPIO DIO 1 mask +#define GPIO_DIO_2_MASK 0x00000004 // GPIO DIO 2 mask +#define GPIO_DIO_3_MASK 0x00000008 // GPIO DIO 3 mask +#define GPIO_DIO_4_MASK 0x00000010 // GPIO DIO 4 mask +#define GPIO_DIO_5_MASK 0x00000020 // GPIO DIO 5 mask +#define GPIO_DIO_6_MASK 0x00000040 // GPIO DIO 6 mask +#define GPIO_DIO_7_MASK 0x00000080 // GPIO DIO 7 mask +#define GPIO_DIO_8_MASK 0x00000100 // GPIO DIO 8 mask +#define GPIO_DIO_9_MASK 0x00000200 // GPIO DIO 9 mask +#define GPIO_DIO_10_MASK 0x00000400 // GPIO DIO 10 mask +#define GPIO_DIO_11_MASK 0x00000800 // GPIO DIO 11 mask +#define GPIO_DIO_12_MASK 0x00001000 // GPIO DIO 12 mask +#define GPIO_DIO_13_MASK 0x00002000 // GPIO DIO 13 mask +#define GPIO_DIO_14_MASK 0x00004000 // GPIO DIO 14 mask +#define GPIO_DIO_15_MASK 0x00008000 // GPIO DIO 15 mask +#define GPIO_DIO_16_MASK 0x00010000 // GPIO DIO 16 mask +#define GPIO_DIO_17_MASK 0x00020000 // GPIO DIO 17 mask +#define GPIO_DIO_18_MASK 0x00040000 // GPIO DIO 18 mask +#define GPIO_DIO_19_MASK 0x00080000 // GPIO DIO 19 mask +#define GPIO_DIO_20_MASK 0x00100000 // GPIO DIO 20 mask +#define GPIO_DIO_21_MASK 0x00200000 // GPIO DIO 21 mask +#define GPIO_DIO_22_MASK 0x00400000 // GPIO DIO 22 mask +#define GPIO_DIO_23_MASK 0x00800000 // GPIO DIO 23 mask +#define GPIO_DIO_24_MASK 0x01000000 // GPIO DIO 24 mask +#define GPIO_DIO_25_MASK 0x02000000 // GPIO DIO 25 mask +#define GPIO_DIO_26_MASK 0x04000000 // GPIO DIO 26 mask +#define GPIO_DIO_27_MASK 0x08000000 // GPIO DIO 27 mask +#define GPIO_DIO_28_MASK 0x10000000 // GPIO DIO 28 mask +#define GPIO_DIO_29_MASK 0x20000000 // GPIO DIO 29 mask +#define GPIO_DIO_30_MASK 0x40000000 // GPIO DIO 30 mask +#define GPIO_DIO_31_MASK 0x80000000 // GPIO DIO 31 mask +#define GPIO_DIO_ALL_MASK 0xFFFFFFFF // GPIO all DIOs mask + +//***************************************************************************** +// +// Define constants that shall be passed as the outputEnableValue parameter to +// GPIO_setOutputEnableDio() and will be returned from the function +// GPIO_getOutputEnableDio(). +// +//***************************************************************************** +#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled +#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Reads a specific DIO. +//! +//! \param dioNumber specifies the DIO to read (0-31). +//! +//! \return Returns 0 or 1 reflecting the input value of the specified DIO. +//! +//! \sa \ref GPIO_readMultiDio(), \ref GPIO_writeDio(), \ref GPIO_writeMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_readDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Return the input value from the specified DIO. + return (( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) >> dioNumber ) & 1 ); +} + +//***************************************************************************** +// +//! \brief Reads the input value for the specified DIOs. +//! +//! This function returns the input value for multiple DIOs. +//! The value returned is not shifted and hence matches the corresponding dioMask bits. +//! +//! \param dioMask is the bit-mask representation of the DIOs to read. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return Returns a bit vector reflecting the input value of the corresponding DIOs. +//! - 0 : Corresponding DIO is low. +//! - 1 : Corresponding DIO is high. +//! +//! \sa \ref GPIO_readDio(), \ref GPIO_writeDio(), \ref GPIO_writeMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_readMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Return the input value from the specified DIOs. + return ( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) & dioMask ); +} + +//***************************************************************************** +// +//! \brief Writes a value to a specific DIO. +//! +//! \param dioNumber specifies the DIO to update (0-31). +//! \param value specifies the value to write +//! - 0 : Logic zero (low) +//! - 1 : Logic one (high) +//! +//! \return None +//! +//! \sa \ref GPIO_writeMultiDio(), \ref GPIO_readDio(), \ref GPIO_readMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_writeDio( uint32_t dioNumber, uint32_t value ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + ASSERT(( value == 0 ) || ( value == 1 )); + + // Write 0 or 1 to the byte indexed DOUT map + HWREGB( GPIO_BASE + dioNumber ) = value; +} + +//***************************************************************************** +// +//! \brief Writes masked data to the specified DIOs. +//! +//! Enables for writing multiple bits simultaneously. +//! The value to write must be shifted so it matches the corresponding dioMask bits. +//! +//! \note Note that this is a read-modify-write operation and hence not atomic. +//! +//! \param dioMask is the bit-mask representation of the DIOs to write. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! \param bitVectoredValue holds the value to be written to the corresponding DIO-bits. +//! +//! \return None +//! +//! \sa \ref GPIO_writeDio(), \ref GPIO_readDio(), \ref GPIO_readMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_writeMultiDio( uint32_t dioMask, uint32_t bitVectoredValue ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) = + ( HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) & ~dioMask ) | + ( bitVectoredValue & dioMask ); +} + +//***************************************************************************** +// +//! \brief Sets a specific DIO to 1 (high). +//! +//! \param dioNumber specifies the DIO to set (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_setMultiDio(), \ref GPIO_clearDio(), \ref GPIO_clearMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Set the specified DIO. + HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +//! \brief Sets the specified DIOs to 1 (high). +//! +//! \param dioMask is the bit-mask representation of the DIOs to set. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return None +//! +//! \sa \ref GPIO_setDio(), \ref GPIO_clearDio(), \ref GPIO_clearMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Set the DIOs. + HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = dioMask; +} + +//***************************************************************************** +// +//! \brief Clears a specific DIO to 0 (low). +//! +//! \param dioNumber specifies the DIO to clear (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_clearMultiDio(), \ref GPIO_setDio(), \ref GPIO_setMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Clear the specified DIO. + HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +//! \brief Clears the specified DIOs to 0 (low). +//! +//! \param dioMask is the bit-mask representation of the DIOs to clear. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return None +//! +//! \sa \ref GPIO_clearDio(), \ref GPIO_setDio(), \ref GPIO_setMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Clear the DIOs. + HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = dioMask; +} + +//***************************************************************************** +// +//! \brief Toggles a specific DIO. +//! +//! \param dioNumber specifies the DIO to toggle (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_toggleMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_toggleDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Toggle the specified DIO. + HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +//! \brief Toggles the specified DIOs. +//! +//! \param dioMask is the bit-mask representation of the DIOs to toggle. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return None +//! +//! \sa \ref GPIO_toggleDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_toggleMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Toggle the DIOs. + HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = dioMask; +} + +//***************************************************************************** +// +//! \brief Gets the output enable status of a specific DIO. +//! +//! This function returns the output enable status for the specified DIO. +//! The DIO can be configured as either input or output under software control. +//! +//! \param dioNumber specifies the DIO to get the output enable setting from (0-31). +//! +//! \return Returns one of the enumerated data types (0 or 1): +//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled. +//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled. +//! +//! \sa \ref GPIO_getOutputEnableMultiDio(), \ref GPIO_setOutputEnableDio(), \ref GPIO_setOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getOutputEnableDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Return the output enable status for the specified DIO. + return (( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) >> dioNumber ) & 1 ); +} + +//***************************************************************************** +// +//! \brief Gets the output enable setting of the specified DIOs. +//! +//! This function returns the output enable setting for multiple DIOs. +//! The value returned is not shifted and hence matches the corresponding dioMask bits. +//! +//! \param dioMask is the bit-mask representation of the DIOs to return the output enable settings from. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return Returns the output enable setting for multiple DIOs as a bit vector corresponding to the dioMask bits. +//! - 0 : Corresponding DIO is configured with output disabled. +//! - 1 : Corresponding DIO is configured with output enabled. +//! +//! \sa \ref GPIO_getOutputEnableDio(), \ref GPIO_setOutputEnableDio(), \ref GPIO_setOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getOutputEnableMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Return the output enable value for the specified DIOs. + return ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & dioMask ); +} + +//***************************************************************************** +// +//! \brief Sets output enable of a specific DIO. +//! +//! This function sets the GPIO output enable bit for the specified DIO. +//! The DIO can be configured as either input or output under software control. +//! +//! \param dioNumber specifies the DIO to configure (0-31). +//! \param outputEnableValue specifies the output enable setting of the specified DIO: +//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled. +//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled. +//! +//! \return None +//! +//! \sa \ref GPIO_setOutputEnableMultiDio(), \ref GPIO_getOutputEnableDio(), \ref GPIO_getOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setOutputEnableDio( uint32_t dioNumber, uint32_t outputEnableValue ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + ASSERT(( outputEnableValue == GPIO_OUTPUT_DISABLE ) || + ( outputEnableValue == GPIO_OUTPUT_ENABLE ) ); + + // Update the output enable bit for the specified DIO. + HWREGBITW( GPIO_BASE + GPIO_O_DOE31_0, dioNumber ) = outputEnableValue; +} + +//***************************************************************************** +// +//! \brief Configures the output enable setting for all specified DIOs. +//! +//! This function configures the output enable setting for the specified DIOs. +//! The output enable setting must be shifted so it matches the corresponding dioMask bits. +//! The DIOs can be configured as either an input or output under software control. +//! +//! \note Note that this is a read-modify-write operation and hence not atomic. +//! +//! \param dioMask is the bit-mask representation of the DIOs on which to configure the +//! output enable setting. The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! \param bitVectoredOutputEnable holds the output enable setting the corresponding DIO-bits: +//! - 0 : Corresponding DIO is configured with output disabled. +//! - 1 : Corresponding DIO is configured with output enabled. +//! +//! \return None +//! +//! \sa \ref GPIO_setOutputEnableDio(), \ref GPIO_getOutputEnableDio(), \ref GPIO_getOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setOutputEnableMultiDio( uint32_t dioMask, uint32_t bitVectoredOutputEnable ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) = + ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & ~dioMask ) | + ( bitVectoredOutputEnable & dioMask ); +} + +//***************************************************************************** +// +//! \brief Gets the event status of a specific DIO. +//! +//! \param dioNumber specifies the DIO to get the event status from (0-31). +//! +//! \return Returns the current event status on the specified DIO. +//! - 0 : Non-triggered event. +//! - 1 : Triggered event. +//! +//! \sa \ref GPIO_getEventMultiDio(), \ref GPIO_clearEventDio(), \ref GPIO_clearEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getEventDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Return the event status for the specified DIO. + return (( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) >> dioNumber ) & 1 ); +} + +//***************************************************************************** +// +//! \brief Gets the event status of the specified DIOs. +//! +//! This function returns the event status for multiple DIOs. +//! The value returned is not shifted and hence matches the corresponding dioMask bits. +//! +//! \param dioMask is the bit-mask representation of the DIOs to get the +//! event status from (0-31). +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return Returns a bit vector with the current event status corresponding to the specified DIOs. +//! - 0 : Corresponding DIO has no triggered event. +//! - 1 : Corresponding DIO has a triggered event. +//! +//! \sa \ref GPIO_getEventDio(), \ref GPIO_clearEventDio(), \ref GPIO_clearEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getEventMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Return the event status for the specified DIO. + return ( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) & dioMask ); +} + +//***************************************************************************** +// +//! \brief Clears the IO event status of a specific DIO. +//! +//! \param dioNumber specifies the DIO on which to clear the event status (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_clearEventMultiDio(), \ref GPIO_getEventDio(), \ref GPIO_getEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearEventDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Clear the event status for the specified DIO. + HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +//! \brief Clears the IO event status on the specified DIOs. +//! +//! \param dioMask is the bit-mask representation of the DIOs on which to +//! clear the events status. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return None +//! +//! \sa \ref GPIO_clearEventDio(), \ref GPIO_getEventDio(), \ref GPIO_getEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearEventMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Clear the event status for the specified DIOs. + HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = dioMask; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio_doc.h new file mode 100644 index 0000000..b4548af --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio_doc.h @@ -0,0 +1,90 @@ +/****************************************************************************** +* Filename: gpio_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup gpio_api +//! @{ +//! \section sec_gpio Introduction +//! +//! The GPIO module allows software to control the pins of the device directly if the IOC module has +//! been configured to route the GPIO signal to a physical pin (called DIO). Alternatively, pins can +//! be hardware controlled by other peripheral modules. For more information about the IOC module, +//! how to configure physical pins, and how to select between software controlled and hardware controlled, +//! see the [IOC API](\ref ioc_api). +//! +//! The System CPU can access the GPIO module to read the value of any DIO of the device and if the IOC +//! module has been configured such that one or more DIOs are GPIO controlled (software controlled) the +//! System CPU can write these DIOs through the GPIO module. +//! +//! The IOC module can also be configured to generate events on edge detection and these events can be +//! read and cleared in the GPIO module by the System CPU. +//! +//! \section sec_gpio_api API +//! +//! The API functions can be grouped like this: +//! +//! Set and get direction of DIO (output enable): +//! - \ref GPIO_setOutputEnableDio() +//! - \ref GPIO_setOutputEnableMultiDio() +//! - \ref GPIO_getOutputEnableDio() +//! - \ref GPIO_getOutputEnableMultiDio() +//! +//! Write DIO (requires IOC to be configured for GPIO usage): +//! - \ref GPIO_writeDio() +//! - \ref GPIO_writeMultiDio() +//! +//! Set, clear, or toggle DIO (requires IOC to be configured for GPIO usage): +//! - \ref GPIO_setDio() +//! - \ref GPIO_setMultiDio() +//! - \ref GPIO_clearDio() +//! - \ref GPIO_clearMultiDio() +//! - \ref GPIO_toggleDio() +//! - \ref GPIO_toggleMultiDio() +//! +//! Read DIO (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC): +//! - \ref GPIO_readDio() +//! - \ref GPIO_readMultiDio() +//! +//! Read or clear events (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC): +//! - \ref GPIO_getEventDio() +//! - \ref GPIO_getEventMultiDio() +//! - \ref GPIO_clearEventDio() +//! - \ref GPIO_clearEventMultiDio() +//! +//! The [IOC API](\ref ioc_api) provides two functions for easy configuration of DIOs as GPIO enabled using +//! typical settings. They also serve as examples on how to configure the IOC and GPIO modules for GPIO usage: +//! - \ref IOCPinTypeGpioInput() +//! - \ref IOCPinTypeGpioOutput() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_analog_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_analog_doc.h new file mode 100644 index 0000000..21b8b55 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_analog_doc.h @@ -0,0 +1,105 @@ +/****************************************************************************** +* Filename: group_analog_doc.h +* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) +* Revision: 47080 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup analog_group +//! @{ +//! \section sec_analog Introduction +//! +//! Access to registers in the analog domain of the device goes through master modules controlling slave +//! modules which contain the actual registers. The master module is located in the digital domain of the +//! device. The interfaces between master and slave modules are called ADI (Analog-to-Digital Interface) +//! and DDI (Digital-to-Digital Interface) depending on the type of module to access and thus the slave +//! modules are referred to as ADI slave and DDI slave. +//! +//! The ADI and DDI APIs provide access to these registers: +//! - ADI_2_REFSYS : Reference System for generating reference voltages and reference currents. +//! - Reference system control +//! - SOC LDO control +//! - ADI_3_REFSYS : Reference System for generating reference voltages and reference currents. +//! - Reference system control +//! - DC/DC control +//! - ADI_4_AUX : Controlling analog peripherals of AUX. +//! - Multiplexers +//! - Current source +//! - Comparators +//! - ADCs +//! - DDI_0_OSC : Controlling the oscillators (via AUX domain) +//! +//! The register descriptions of CPU memory map document the ADI/DDI masters. The register descriptions of +//! analog memory map document the ADI/DDI slaves. The ADI/DDI APIs allow the programmer to focus on the +//! slave registers of interest without being concerned with the ADI/DDI master part of the interface. +//! +//! Although the ADI/DDI APIs make the master "transparent" it can be useful to know a few details about +//! the ADI/DDI protocol and how the master handles transactions as it can affect how the system CPU performs. +//! - ADI protocol uses 8-bit write bus compared to 32-bit write bus in DDI. ADI protocol uses 4-bit read +//! bus compared to 16-bit read bus in DDI. Hence a 32-bit read from an ADI register is translated into 8 +//! transactions in the ADI protocol. +//! - One transaction on the ADI/DDI protocol takes several clock cycles for the master to complete. +//! - ADI slave registers are 8-bit wide. +//! - DDI slave registers are 32-bit wide. +//! - ADI/DDI master supports multiple data width accesses seen from the system CPU +//! (however, not all bit width accesses are supported by the APIs): +//! - Read: 8, 16, 32-bit +//! - Write +//! - Direct (write, set, clear): 8, 16, 32-bit +//! - Masked: 4, 8, 16-bit +//! +//! Making posted/buffered writes from the system CPU (default) to the ADI/DDI allows the system CPU to continue +//! while the ADI/DDI master handles the transactions on the ADI/DDI protocol. If using non-posted/non-buffered +//! writes the system CPU will wait for ADI/DDI master to complete the transactions to the slave before continuing +//! execution. +//! +//! Reading from ADI/DDI requires that all transactions on the ADI/DDI protocol have completed before the system CPU +//! receives the response thus the programmer must understand that the response time depends on the number of bytes +//! read. However, due to the 'set', 'clear' and 'masked write' features of the ADI/DDI most writes can be done +//! without the typical read-modify-write sequence thus reducing the need for reads to a minimum. +//! +//! Consequently, if making posted/buffered writes then the written value will not take effect in the +//! analog domain until some point later in time. An alternative to non-posted/non-buffered writes - in order to make +//! sure a written value has taken effect - is to read from the same ADI/DDI as the write as this will keep the system CPU +//! waiting until both the write and the read have completed. +//! +//! \note +//! Do NOT use masked write when writing bit fields spanning the "masked write boundary" i.e. the widest possible +//! masked write that the protocol supports (ADI = 4 bits, DDI = 16 bits). This will put the device into a +//! temporary state - which is potentially harmful to the device - as the bit field will be written over two transactions. +//! Thus to use masked writes: +//! - For ADI the bit field(s) must be within bit 0 to 3 (REG[3:0]) or bit 4 to 7 (REG[7:4]). +//! - For DDI the bit field(s) must be within bit 0 to 15 (REG[15:0]) or bit 16 to 31 (REG[31:16]). +//! +//! \note +//! If masked write is not allowed, a regular read-modify-write is necessary. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aon_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aon_doc.h new file mode 100644 index 0000000..c5056d9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aon_doc.h @@ -0,0 +1,76 @@ +/****************************************************************************** +* Filename: group_aon_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aon_group +//! @{ +//! \section sec_aon Introduction +//! +//! The Always-ON (AON) voltage domain contains the AUX power domain, AON power domain, and JTAG power domain. +//! The AON API includes functions to access the AON power domain. For functions accessing the AUX power domain +//! see the [AUX API](@ref aux_group). +//! +//! The AON power domain contains circuitry that is always enabled, except for the shutdown mode +//! (digital supply is off), and the AON power domain is clocked at 32-kHz. +//! +//! The AON API accesses the AON registers through a common module called AON Interface (AON IF) which handles the +//! actual transactions towards the much slower AON registers. Because accessing AON can cause a significant +//! delay in terms of system CPU clock cycles it is important to understand the basics about how the AON IF +//! operates. The following list describes a few of the most relevant properties of the AON IF seen from the system CPU: +//! - \ti_bold{Shadow registers}: The system CPU actually accesses a set of "shadow registers" which are being synchronized to the AON registers +//! by the AON IF every AON clock cycle. +//! - Writing an AON register via AON IF can take up to one AON clock cycle before taking effect in the AON domain. However, the system CPU can +//! continue executing without waiting for this. +//! - The AON IF supports multiple writes within the same AON clock cycle thus several registers/bit fields can be synchronized simultaneously. +//! - Reading from AON IF returns the value from last time the shadow registers were synchronized (if no writes to AON IF have occurred since) +//! thus the value can be up to one AON clock cycle old. +//! - Reading from AON IF after a write (but before synchronization has happened) will return the value from the shadow register +//! and not the last value from the AON register. Thus doing multiple read-modify-writes within one AON clock cycle is supported. +//! - \ti_bold{Read delay}: Due to an asynchronous interface to the AON IF, reading AON registers will generate a few wait cycles thus stalling +//! the system CPU until the read completes. There is no delay on writes to AON IF if using posted/buffered writes. +//! - \ti_bold{Synchronizing}: If it is required that a write to AON takes effect before continuing code execution it is possible to do a conditional "wait for +//! synchronization" by calling \ref SysCtrlAonSync(). This will wait for any pending writes to synchronize. +//! - \ti_bold{Updating}: It is also possible to do an unconditional "wait for synchronization", in case a new read +//! value is required, by calling \ref SysCtrlAonUpdate(). This is typically used after wake-up to make sure the AON IF has been +//! synchronized at least once before reading the values. +//! +//! Below are a few guidelines to write efficient code for AON access based on the properties of the interface to the AON registers. +//! - Avoid synchronizing unless required by the application. If synchronization is needed then try to group/arrange AON writes to +//! minimize the number of required synchronizations. +//! - If modifying several bit fields within a single AON register it is slightly faster to do a single read, modify the bit fields, +//! and then write it back rather than doing multiple independent read-modify-writes (due to the read delay). +//! - Using posted/buffered writes to AON (default) lets the system CPU continue execution immediately. Using non-posted/non-buffered +//! writes will generate a delay similar to a read access. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aux_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aux_doc.h new file mode 100644 index 0000000..63ddcfd --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aux_doc.h @@ -0,0 +1,58 @@ +/****************************************************************************** +* Filename: group_aux_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aux_group +//! @{ +//! \section sec_aux Introduction +//! +//! The AUX is a collective description of all the analog peripherals (ADC, comparators, and current source) and +//! the digital modules in the AUX power domain (AUX_PD) such as the sensor controller, timers, time-to-digital +//! converter, etc. AUX_PD is located within the AON voltage domain of the device. +//! +//! The sensor controller has the ability to +//! do its own power and clock management of AUX_PD, independently of the MCU domain. The sensor +//! controller can also continue doing tasks while the MCU subsystem is powered down, but with limited +//! resources compared to the larger MCU domain. +//! +//! The AUX power domain is connected to the MCU system through an asynchronous interface, ensuring +//! that all modules connected to the AUX bus are accessible from the system CPU. +//! Accessing the analog peripherals from the system CPU must be done by using TI-provided +//! drivers to ensure proper control of power management. +//! +//! \note To ease development of program code running on the sensor controller, TI provides a tool +//! chain for writing software for the controller, Sensor Controller Studio (SCS), which is a fully +//! integrated tool consisting of an IDE, compiler, assembler, and linker. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.c new file mode 100644 index 0000000..0b52735 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.c @@ -0,0 +1,172 @@ +/****************************************************************************** +* Filename: i2c.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the I2C module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "i2c.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef I2CMasterInitExpClk + #define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk + #undef I2CMasterErr + #define I2CMasterErr NOROM_I2CMasterErr + #undef I2CIntRegister + #define I2CIntRegister NOROM_I2CIntRegister + #undef I2CIntUnregister + #define I2CIntUnregister NOROM_I2CIntUnregister +#endif + +//***************************************************************************** +// +// Initializes the I2C Master block +// +//***************************************************************************** +void +I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast) +{ + uint32_t ui32SCLFreq; + uint32_t ui32TPR; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Must enable the device before doing anything else. + I2CMasterEnable(I2C0_BASE); + + // Get the desired SCL speed. + if(bFast == true) + { + ui32SCLFreq = 400000; + } + else + { + ui32SCLFreq = 100000; + } + + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biased to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / (2 * 10 * ui32SCLFreq)) - 1; + HWREG(I2C0_BASE + I2C_O_MTPR) = ui32TPR; +} + +//***************************************************************************** +// +// Gets the error status of the I2C Master module +// +//***************************************************************************** +uint32_t +I2CMasterErr(uint32_t ui32Base) +{ + uint32_t ui32Err; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the raw error state. + ui32Err = HWREG(I2C0_BASE + I2C_O_MSTAT); + + // If the I2C master is busy, then all the other status bits are invalid, + // and there is no error to report. + if(ui32Err & I2C_MSTAT_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // Check for errors. + if(ui32Err & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST)) + { + return(ui32Err & (I2C_MSTAT_ARBLST | I2C_MSTAT_DATACK_N | I2C_MSTAT_ADRACK_N)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} + +//***************************************************************************** +// +// Registers an interrupt handler for the I2C module +// +//***************************************************************************** +void +I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the interrupt number. + ui32Int = INT_I2C_IRQ; + + // Register the interrupt handler, returning an error if an error occurs. + IntRegister(ui32Int, pfnHandler); + + // Enable the I2C interrupt. + IntEnable(ui32Int); +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for the I2C module +// +//***************************************************************************** +void +I2CIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the interrupt number. + ui32Int = INT_I2C_IRQ; + + // Disable the interrupt. + IntDisable(ui32Int); + + // Unregister the interrupt handler. + IntUnregister(ui32Int); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.h new file mode 100644 index 0000000..d1e2969 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.h @@ -0,0 +1,974 @@ +/****************************************************************************** +* Filename: i2c.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and prototypes for the I2C. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup i2c_api +//! @{ +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_i2c.h" +#include "../inc/hw_sysctl.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk + #define I2CMasterErr NOROM_I2CMasterErr + #define I2CIntRegister NOROM_I2CIntRegister + #define I2CIntUnregister NOROM_I2CIntUnregister +#endif + +//***************************************************************************** +// +// I2C Master commands +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START \ + 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 + +//***************************************************************************** +// +// I2C Master error status +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte + +//***************************************************************************** +// +// I2C Slave interrupts +// +//***************************************************************************** +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an I2C base address. +//! +//! This function determines if a I2C port base address is valid. +//! +//! \param ui32Base is the base address of the I2C port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise +// +//***************************************************************************** +static bool +I2CBaseValid(uint32_t ui32Base) +{ + return(ui32Base == I2C0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Initializes the I2C Master block. +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master, and will have enabled the I2C Master block. +//! +//! If the parameter \c bFast is \c true, then the master block will be set up +//! to transfer data at 400 kbps; otherwise, it will be set up to transfer data +//! at 100 kbps. +//! +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32I2CClk is the rate of the clock supplied to the I2C module. +//! \param bFast set up for fast data transfers. +//! +//! \return None +// +//***************************************************************************** +extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast); + +//***************************************************************************** +// +//! \brief Controls the state of the I2C Master module. +//! +//! This function is used to control the state of the Master module send and +//! receive operations. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32Cmd is the command to be issued by the I2C Master module +//! The parameter can be one of the following values: +//! - \ref I2C_MASTER_CMD_SINGLE_SEND +//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE +//! - \ref I2C_MASTER_CMD_BURST_SEND_START +//! - \ref I2C_MASTER_CMD_BURST_SEND_CONT +//! - \ref I2C_MASTER_CMD_BURST_SEND_FINISH +//! - \ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) || + // (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || -> Equal to SINGLE_SEND + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP)); + + // Send the command. + HWREG(I2C0_BASE + I2C_O_MCTRL) = ui32Cmd; + + // Delay minimum four cycles in order to ensure that the I2C_O_MSTAT + // register has been correctly updated before function exit + CPUdelay(2); +} + +//***************************************************************************** +// +//! \brief Sets the address that the I2C Master will place on the bus. +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. When the \e bReceive parameter is set +//! to \b true, the address will indicate that the I2C Master is initiating a +//! read from the slave; otherwise the address will indicate that the I2C +//! Master is initiating a write to the slave. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8SlaveAddr is a 7-bit slave address +//! \param bReceive flag indicates the type of communication with the slave. +//! - \c true : I2C Master is initiating a read from the slave. +//! - \c false : I2C Master is initiating a write to the slave. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, + bool bReceive) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // Set the address of the slave with which the master will communicate. + HWREG(I2C0_BASE + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; +} + +//***************************************************************************** +// +//! \brief Enables the I2C Master block. +//! +//! This will enable operation of the I2C Master block. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Enable the clock for the master. + HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 1; + + // Enable the master block. + HWREG(I2C0_BASE + I2C_O_MCTRL) = I2C_MCTRL_RUN; +} + +//***************************************************************************** +// +//! \brief Disables the I2C master block. +//! +//! This will disable operation of the I2C master block. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Disable the master block. + HWREG(I2C0_BASE + I2C_O_MCTRL) = 0; + + // Disable the clock for the master. + HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C Master is busy. +//! +//! This function returns an indication of whether or not the I2C Master is +//! busy transmitting or receiving data. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns status of I2C Master: +//! - \c true : I2C Master is busy. +//! - \c false : I2C Master is not busy. +// +//***************************************************************************** +__STATIC_INLINE bool +I2CMasterBusy(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return the busy status. + if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C bus is busy. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function can be used in a multi-master environment to determine if +//! another master is currently using the bus. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns status of the I2C bus: +//! - \c true : I2C bus is busy. +//! - \c false : I2C bus is not busy. +// +//***************************************************************************** +__STATIC_INLINE bool +I2CMasterBusBusy(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return the bus busy status. + if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSBSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Master. +//! +//! This function reads a byte of data from the I2C Master Data Register. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns the byte received from by the I2C Master, cast as an +//! uint32_t. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CMasterDataGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Read a byte. + return(HWREG(I2C0_BASE + I2C_O_MDR)); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the I2C Master. +//! +//! This function will place the supplied data into I2C Master Data Register. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8Data is the data to be transmitted by the I2C Master +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Write the byte. + HWREG(I2C0_BASE + I2C_O_MDR) = ui8Data; +} + +//***************************************************************************** +// +//! \brief Gets the error status of the I2C Master module. +//! +//! This function is used to obtain the error status of the Master module send +//! and receive operations. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns the error status of the Master module: +//! - \ref I2C_MASTER_ERR_NONE +//! - \ref I2C_MASTER_ERR_ADDR_ACK +//! - \ref I2C_MASTER_ERR_DATA_ACK +//! - \ref I2C_MASTER_ERR_ARB_LOST +// +//***************************************************************************** +extern uint32_t I2CMasterErr(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables the I2C Master interrupt. +//! +//! Enables the I2C Master interrupt source. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterIntEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Enable the master interrupt. + HWREG(I2C0_BASE + I2C_O_MIMR) = I2C_MIMR_IM; +} + +//***************************************************************************** +// +//! \brief Disables the I2C Master interrupt. +//! +//! Disables the I2C Master interrupt source. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterIntDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Disable the master interrupt. + HWREG(I2C0_BASE + I2C_O_MIMR) = 0; +} + +//***************************************************************************** +// +//! \brief Clears I2C Master interrupt sources. +//! +//! The I2C Master interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterIntClear(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Clear the I2C master interrupt source. + HWREG(I2C0_BASE + I2C_O_MICR) = I2C_MICR_IC; +} + +//***************************************************************************** +// +//! \brief Gets the current I2C Master interrupt status. +//! +//! This returns the interrupt status for the I2C Master module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param bMasked selects either raw or masked interrupt status. +//! - \c false : Raw interrupt status is requested. +//! - \c true : Masked interrupt status is requested. +//! +//! \return Returns the current interrupt status. +//! - \c true : Active. +//! - \c false : Not active. +// +//***************************************************************************** +__STATIC_INLINE bool +I2CMasterIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return((HWREG(I2C0_BASE + I2C_O_MMIS)) ? true : false); + } + else + { + return((HWREG(I2C0_BASE + I2C_O_MRIS)) ? true : false); + } +} + +//***************************************************************************** +// +//! \brief Enables the I2C Slave block. +//! +//! This will enable operation of the I2C Slave block. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Enable the clock to the slave block. + HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 1; + + // Enable the slave. + HWREG(I2C0_BASE + I2C_O_SCTL) = I2C_SCTL_DA; +} + +//***************************************************************************** +// +//! \brief Initializes the I2C Slave block. +//! +//! This function initializes operation of the I2C Slave block. Upon +//! successful initialization of the I2C blocks, this function will have set +//! the slave address and have enabled the I2C Slave block. +//! +//! The parameter \c ui8SlaveAddr is the value that will be compared against the +//! slave address sent by an I2C master. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8SlaveAddr is the 7-bit slave address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // Must enable the device before doing anything else. + I2CSlaveEnable(I2C0_BASE); + + // Set up the slave address. + HWREG(I2C0_BASE + I2C_O_SOAR) = ui8SlaveAddr; +} + +//***************************************************************************** +// +//! \brief Sets the I2C slave address. +//! +//! This function writes the specified slave address. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8SlaveAddr is the 7-bit slave address +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8SlaveAddr) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // Set up the primary slave address. + HWREG(I2C0_BASE + I2C_O_SOAR) = ui8SlaveAddr; +} + +//***************************************************************************** +// +//! \brief Disables the I2C slave block. +//! +//! This will disable operation of the I2C slave block. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Disable the slave. + HWREG(I2C0_BASE + I2C_O_SCTL) = 0x0; + + // Disable the clock to the slave block. + HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Gets the I2C Slave module status. +//! +//! This function will return the action requested from a master, if any. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return Returns the status of the I2C Slave module: +//! - \ref I2C_SLAVE_ACT_NONE : No action has been requested of the I2C Slave module. +//! - \ref I2C_SLAVE_ACT_RREQ : An I2C master has sent data to the I2C Slave module. +//! - \ref I2C_SLAVE_ACT_TREQ : An I2C master has requested that the I2C Slave module send data. +//! - \ref I2C_SLAVE_ACT_RREQ_FBR : An I2C master has sent data to the I2C slave +//! and the first byte following the slave's own address has been received. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CSlaveStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return the slave status. + return(HWREG(I2C0_BASE + I2C_O_SSTAT)); +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Slave. +//! +//! This function reads a byte of data from the I2C Slave Data Register. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return Returns the byte received from by the I2C Slave, cast as an +//! uint32_t. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CSlaveDataGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Read a byte. + return(HWREG(I2C0_BASE + I2C_O_SDR)); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the I2C Slave. +//! +//! This function will place the supplied data into I2C Slave Data Register. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8Data data to be transmitted from the I2C Slave. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Write the byte. + HWREG(I2C0_BASE + I2C_O_SDR) = ui8Data; +} + +//***************************************************************************** +// +//! \brief Enables individual I2C Slave interrupt sources. +//! +//! Enables the indicated I2C Slave interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is the bit mask of the slave interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + uint32_t ui32Val; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START | + I2C_SLAVE_INT_DATA)); + + // Enable the slave interrupt. + ui32Val = HWREG(I2C0_BASE + I2C_O_SIMR); + ui32Val |= ui32IntFlags; + HWREG(I2C0_BASE + I2C_O_SIMR) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Disables individual I2C Slave interrupt sources. +//! +//! Disables the indicated I2C Slave interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + uint32_t ui32Val; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START | + I2C_SLAVE_INT_DATA)); + + // Disable the slave interrupt. + ui32Val = HWREG(I2C0_BASE + I2C_O_SIMR); + ui32Val &= ~ui32IntFlags; + HWREG(I2C0_BASE + I2C_O_SIMR) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Clears I2C Slave interrupt sources. +//! +//! The specified I2C Slave interrupt sources are cleared, so that they no +//! longer assert. This must be done in the interrupt handler to keep it from +//! being called again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Clear the I2C slave interrupt source. + HWREG(I2C0_BASE + I2C_O_SICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current I2C Slave interrupt status. +//! +//! This returns the interrupt status for the I2C Slave module. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param bMasked selects either raw or masked interrupt status. +//! - \c false : Raw interrupt status is requested. +//! - \c true : Masked interrupt status is requested. +//! +//! \return Returns the current interrupt status as an OR'ed combination of: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return(HWREG(I2C0_BASE + I2C_O_SMIS)); + } + else + { + return(HWREG(I2C0_BASE + I2C_O_SRIS)); + } +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the I2C module in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific I2C interrupts must be enabled via \ref I2CMasterIntEnable() and +//! \ref I2CSlaveIntEnable(). If necessary, it is the interrupt handler's +//! responsibility to clear the interrupt source via \ref I2CMasterIntClear() and +//! \ref I2CSlaveIntClear(). +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param pfnHandler is a pointer to the function to be called when the +//! I2C interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the I2C module in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when an I2C interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler no longer is called. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! \return None +//! +//! \sa \brief IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void I2CIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_I2CMasterInitExpClk + #undef I2CMasterInitExpClk + #define I2CMasterInitExpClk ROM_I2CMasterInitExpClk + #endif + #ifdef ROM_I2CMasterErr + #undef I2CMasterErr + #define I2CMasterErr ROM_I2CMasterErr + #endif + #ifdef ROM_I2CIntRegister + #undef I2CIntRegister + #define I2CIntRegister ROM_I2CIntRegister + #endif + #ifdef ROM_I2CIntUnregister + #undef I2CIntUnregister + #define I2CIntUnregister ROM_I2CIntUnregister + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c_doc.h new file mode 100644 index 0000000..c339318 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c_doc.h @@ -0,0 +1,162 @@ +/****************************************************************************** +* Filename: i2c_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup i2c_api +//! @{ +//! \section sec_i2c Introduction +//! +//! The Inter-Integrated Circuit (\i2c) API provides a set of functions for using +//! the \ti_device \i2c master and slave module. Functions are provided to perform +//! the following actions: +//! - Initialize the \i2c module. +//! - Send and receive data. +//! - Obtain status. +//! - Manage interrupts for the \i2c module. +//! +//! The \i2c master and slave module provide the ability to communicate to other IC +//! devices over an \i2c bus. The \i2c bus is specified to support devices that can +//! both transmit and receive (write and read) data. Also, devices on the \i2c bus +//! can be designated as either a master or a slave. The \ti_device \i2c module +//! supports both sending and receiving data as either a master or a slave, and also +//! support the simultaneous operation as both a master and a slave. Finally, the +//! \ti_device \i2c module can operate at two speeds: standard (100 kb/s) and fast +//! (400 kb/s). +//! +//! The master and slave \i2c module can generate interrupts. The \i2c master +//! module generates interrupts when a transmit or receive operation +//! completes (or aborts due to an error). +//! The \i2c slave module can generate interrupts when data is +//! sent or requested by a master and when a START or STOP condition is present. +//! +//! \section sec_i2c_master Master Operations +//! +//! When using this API to drive the \i2c master module, the user must first +//! initialize the \i2c master module with a call to \ref I2CMasterInitExpClk(). This +//! function sets the bus speed and enables the master module. +//! +//! The user may transmit or receive data after the successful initialization of +//! the \i2c master module. Data is transferred by first setting the slave address +//! using \ref I2CMasterSlaveAddrSet(). This function is also used to define whether +//! the transfer is a send (a write to the slave from the master) or a receive (a +//! read from the slave by the master). Then, if connected to an \i2c bus that has +//! multiple masters, the \ti_device \i2c master must first call \ref I2CMasterBusBusy() +//! before trying to initiate the desired transaction. After determining that +//! the bus is not busy, if trying to send data, the user must call the +//! \ref I2CMasterDataPut() function. The transaction can then be initiated on the bus +//! by calling the \ref I2CMasterControl() function with any of the following commands: +//! - \ref I2C_MASTER_CMD_SINGLE_SEND +//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE +//! - \ref I2C_MASTER_CMD_BURST_SEND_START +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START +//! +//! Any of these commands result in the master arbitrating for the bus, +//! driving the start sequence onto the bus, and sending the slave address and +//! direction bit across the bus. The remainder of the transaction can then be +//! driven using either a polling or interrupt-driven method. +//! +//! For the single send and receive cases, the polling method involves looping +//! on the return from \ref I2CMasterBusy(). Once the function indicates that the \i2c +//! master is no longer busy, the bus transaction is complete and can be +//! checked for errors using \ref I2CMasterErr(). If there are no errors, then the data +//! has been sent or is ready to be read using \ref I2CMasterDataGet(). For the burst +//! send and receive cases, the polling method also involves calling the +//! \ref I2CMasterControl() function for each byte transmitted or received +//! (using either the \ref I2C_MASTER_CMD_BURST_SEND_CONT or \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! commands), and for the last byte sent or received (using either the +//! \ref I2C_MASTER_CMD_BURST_SEND_FINISH or \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! commands). +//! +//! If any error is detected during the burst transfer, +//! the appropriate stop command (\ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP or +//! \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) should be used to call the +//! \ref I2CMasterControl() function. +//! +//! For the interrupt-driven transaction, the user must register an interrupt +//! handler for the \i2c devices and enable the \i2c master interrupt; the interrupt +//! occurs when the master is no longer busy. +//! +//! \section sec_i2c_slave Slave Operations +//! +//! When using this API to drive the \i2c slave module, the user must first +//! initialize the \i2c slave module with a call to \ref I2CSlaveInit(). This function +//! enables the \i2c slave module and initializes the address of the slave. After the +//! initialization completes, the user may poll the slave status using +//! \ref I2CSlaveStatus() to determine if a master requested a send or receive +//! operation. Depending on the type of operation requested, the user can call +//! \ref I2CSlaveDataPut() or \ref I2CSlaveDataGet() to complete the transaction. +//! Alternatively, the \i2c slave can handle transactions using an interrupt handler +//! registered with \ref I2CIntRegister(), and by enabling the \i2c slave interrupt. +//! +//! \section sec_i2c_api API +//! +//! The \i2c API is broken into three groups of functions: +//! those that handle status and initialization, those that +//! deal with sending and receiving data, and those that deal with +//! interrupts. +//! +//! Status and initialization functions for the \i2c module are: +//! - \ref I2CMasterInitExpClk() +//! - \ref I2CMasterEnable() +//! - \ref I2CMasterDisable() +//! - \ref I2CMasterBusBusy() +//! - \ref I2CMasterBusy() +//! - \ref I2CMasterErr() +//! - \ref I2CSlaveInit() +//! - \ref I2CSlaveEnable() +//! - \ref I2CSlaveDisable() +//! - \ref I2CSlaveStatus() +//! +//! Sending and receiving data from the \i2c module is handled by the following functions: +//! - \ref I2CMasterSlaveAddrSet() +//! - \ref I2CSlaveAddressSet() +//! - \ref I2CMasterControl() +//! - \ref I2CMasterDataGet() +//! - \ref I2CMasterDataPut() +//! - \ref I2CSlaveDataGet() +//! - \ref I2CSlaveDataPut() +//! +//! The \i2c master and slave interrupts are handled by the following functions: +//! - \ref I2CIntRegister() +//! - \ref I2CIntUnregister() +//! - \ref I2CMasterIntEnable() +//! - \ref I2CMasterIntDisable() +//! - \ref I2CMasterIntClear() +//! - \ref I2CMasterIntStatus() +//! - \ref I2CSlaveIntEnable() +//! - \ref I2CSlaveIntDisable() +//! - \ref I2CSlaveIntClear() +//! - \ref I2CSlaveIntStatus() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.c new file mode 100644 index 0000000..55e935f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.c @@ -0,0 +1,349 @@ +/****************************************************************************** +* Filename: i2s.c +* Revised: 2017-05-08 12:18:04 +0200 (Mon, 08 May 2017) +* Revision: 48924 +* +* Description: Driver for the I2S. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "i2s.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef I2SEnable + #define I2SEnable NOROM_I2SEnable + #undef I2SAudioFormatConfigure + #define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure + #undef I2SChannelConfigure + #define I2SChannelConfigure NOROM_I2SChannelConfigure + #undef I2SBufferConfig + #define I2SBufferConfig NOROM_I2SBufferConfig + #undef I2SPointerUpdate + #define I2SPointerUpdate NOROM_I2SPointerUpdate + #undef I2SPointerSet + #define I2SPointerSet NOROM_I2SPointerSet + #undef I2SSampleStampConfigure + #define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure + #undef I2SSampleStampGet + #define I2SSampleStampGet NOROM_I2SSampleStampGet +#endif + +//***************************************************************************** +// +// Global pointer to the current I2S data structure +// +//***************************************************************************** +I2SControlTable *g_pControlTable; + +//***************************************************************************** +// +// Enables the I2S module for operation +// +//***************************************************************************** +void +I2SEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Make sure the control table pointer is setup to a memory location. + if(!(g_pControlTable)) + { + return; + } + + // Write the address to the first input/output buffer. + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InBase; + g_pControlTable->ui32InOffset = 0; + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = g_pControlTable->ui32OutBase; + g_pControlTable->ui32OutOffset = 0; + + // Enable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = (uint32_t)g_pControlTable->ui16DMABufSize - 1; +} + +//***************************************************************************** +// +// Configures the I2S module +// +//***************************************************************************** +void +I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg, + uint32_t ui32BitClkDelay) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui32BitClkDelay <= 255); + + // Save the length of the audio words stored in memory. + g_pControlTable->ui16MemLen = (ui32FmtCfg & I2S_MEM_LENGTH_24) ? 24 : 16; + + // Write the configuration. + HWREG(I2S0_BASE + I2S_O_AIFFMTCFG) = ui32FmtCfg | (ui32BitClkDelay << I2S_AIFFMTCFG_DATA_DELAY_S); +} + +//**************************************************************************** +// +// Setup the audio channel configuration +// +//**************************************************************************** +void +I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg, + uint32_t ui32Chan1Cfg) +{ + uint32_t ui32InChan; + uint32_t ui32OutChan; + uint32_t ui32ChanMask; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui32Chan0Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK)) + ASSERT(ui32Chan1Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK)) + + ui32InChan = 0; + ui32OutChan = 0; + + // Configure input/output channels. + HWREG(I2S0_BASE + I2S_O_AIFDIRCFG) = ( + (( ui32Chan0Cfg << I2S_AIFDIRCFG_AD0_S) & I2S_AIFDIRCFG_AD0_M ) | + (( ui32Chan1Cfg << I2S_AIFDIRCFG_AD1_S) & I2S_AIFDIRCFG_AD1_M ) ); + + // Configure the valid channel mask. + HWREG(I2S0_BASE + I2S_O_AIFWMASK0) = (ui32Chan0Cfg >> 8) & I2S_AIFWMASK0_MASK_M; + HWREG(I2S0_BASE + I2S_O_AIFWMASK1) = (ui32Chan1Cfg >> 8) & I2S_AIFWMASK1_MASK_M; + + // Resolve and save the number of input and output channels. + ui32ChanMask = (ui32Chan0Cfg & I2S_CHAN_CFG_MASK) >> 8; + if(ui32Chan0Cfg & I2S_LINE_INPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32InChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + + } + else if(ui32Chan0Cfg & I2S_LINE_OUTPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32OutChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + } + + ui32ChanMask = (ui32Chan1Cfg & I2S_CHAN_CFG_MASK) >> 8; + if(ui32Chan1Cfg & I2S_LINE_INPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32InChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + } + else if(ui32Chan1Cfg & I2S_LINE_OUTPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32OutChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + } + + g_pControlTable->ui8InChan = (uint8_t)ui32InChan; + g_pControlTable->ui8OutChan = (uint8_t)ui32OutChan; +} + +//**************************************************************************** +// +// Set the input buffer pointers +// +//**************************************************************************** +void +I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase, + uint32_t ui32OutBufBase, uint16_t ui16DMABufSize, + uint16_t ui16ChanBufSize) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui16DMABufSize > 0); + + // Setup the input data pointer and buffer sizes. + g_pControlTable->ui16DMABufSize = ui16DMABufSize; + g_pControlTable->ui16ChBufSize = ui16ChanBufSize; + g_pControlTable->ui32InBase = ui32InBufBase; + g_pControlTable->ui32OutBase = ui32OutBufBase; +} + +//**************************************************************************** +// +// Set the buffer pointers +// +//**************************************************************************** +void +I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Update the next input/output pointer with the correct address. + if(bInput == true) + { + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = (uint32_t)pNextPointer; + } + else + { + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = (uint32_t)pNextPointer; + } +} + +//**************************************************************************** +// +// Update the buffer pointers +// +//**************************************************************************** +void +I2SPointerUpdate(uint32_t ui32Base, bool bInput) +{ + uint32_t ui32NextPtr; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Update the next input/output pointer with the correct address. + if(bInput == true) + { + ui32NextPtr = (g_pControlTable->ui8InChan * + (g_pControlTable->ui16MemLen >> 3)) * + g_pControlTable->ui16DMABufSize; + g_pControlTable->ui32InOffset = ((g_pControlTable->ui32InOffset + + ui32NextPtr) % + g_pControlTable->ui16ChBufSize); + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InOffset + + g_pControlTable->ui32InBase; + } + else + { + ui32NextPtr = (g_pControlTable->ui8OutChan * + (g_pControlTable->ui16MemLen >> 3)) * + g_pControlTable->ui16DMABufSize; + g_pControlTable->ui32OutOffset = ((g_pControlTable->ui32OutOffset + + ui32NextPtr) % + g_pControlTable->ui16ChBufSize); + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = + g_pControlTable->ui32OutOffset + + g_pControlTable->ui32OutBase; + } +} + +//***************************************************************************** +// +// Configure the sample stamp generator +// +//***************************************************************************** +void +I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, bool bOutput) +{ + uint32_t ui32Trigger; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + ui32Trigger = HWREG(I2S0_BASE + I2S_O_STMPWCNT); + ui32Trigger = (ui32Trigger + 2) % g_pControlTable->ui16ChBufSize; + + // Setup the sample stamp trigger for input streams. + if(bInput) + { + HWREG(I2S0_BASE + I2S_O_STMPINTRIG) = ui32Trigger; + } + + // Setup the sample stamp trigger for output streams. + if(bOutput) + { + HWREG(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui32Trigger; + } + +} + +//***************************************************************************** +// +// Get the current value of a sample stamp counter +// +//***************************************************************************** +uint32_t +I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel) +{ + uint32_t ui32FrameClkCnt; + uint32_t ui32SysClkCnt; + uint32_t ui32PeriodSysClkCnt; + uint32_t ui32SampleStamp; + + // Get the number of Frame clock counts since last stamp. + ui32FrameClkCnt = HWREG(I2S0_BASE + I2S_O_STMPWCNTCAPT0); + + // Get the number of system clock ticks since last frame clock edge. + ui32SysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXCNTCAPT0); + + // Get the number system clock ticks in the last frame clock period. + ui32PeriodSysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXPER); + + // Calculate the sample stamp. + ui32SampleStamp = (ui32SysClkCnt << 16) / ui32PeriodSysClkCnt; + ui32SampleStamp = (ui32SampleStamp > I2S_STMP_SATURATION) ? + I2S_STMP_SATURATION : ui32SampleStamp; + ui32SampleStamp |= (ui32FrameClkCnt << 16); + + return (ui32SampleStamp); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h new file mode 100644 index 0000000..ab50cd6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h @@ -0,0 +1,1359 @@ +/****************************************************************************** +* Filename: i2s.h +* Revised: 2018-11-16 11:16:53 +0100 (Fri, 16 Nov 2018) +* Revision: 53356 +* +* Description: Defines and prototypes for the I2S. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//**************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup i2s_api +//! @{ +// +//**************************************************************************** + +#ifndef __I2S_H__ +#define __I2S_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_i2s.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define I2SEnable NOROM_I2SEnable + #define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure + #define I2SChannelConfigure NOROM_I2SChannelConfigure + #define I2SBufferConfig NOROM_I2SBufferConfig + #define I2SPointerUpdate NOROM_I2SPointerUpdate + #define I2SPointerSet NOROM_I2SPointerSet + #define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure + #define I2SSampleStampGet NOROM_I2SSampleStampGet +#endif + +//***************************************************************************** +// +//! \brief A structure that defines an audio control table. Note: Memory for this +//! structure \b must be initialized by user application. See detailed description! +//! +//! \deprecated This structure will be removed in a future release. +//! +//! These fields are used by the I2S and normally it is not necessary for +//! software to directly read or write fields in the table. +//! +//! \note The control table must be defined by the user as a global variable and +//! the global pointer must then be assigned the address of the control table +//! inside a user function (but before calling any I2S-function). +//! +/*! +\verbatim + I2SControlTable g_controlTable; // Define global + g_pControlTable = &g_controlTable; // Assign pointer (inside a function) +\endverbatim +*/ +//! +// +//***************************************************************************** +#ifndef DEPRECATED +typedef struct +{ + uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples. + uint16_t ui16ChBufSize; //!< Size of Channel buffer. + uint8_t ui8InChan; //!< Input Channel. + uint8_t ui8OutChan; //!< Output Channel. + uint16_t ui16MemLen; //!< Length of the audio words stored in memory. + uint32_t ui32InBase; //!< Base address of the input buffer. + uint32_t ui32InOffset; //!< Value of the current input pointer offset. + uint32_t ui32OutBase; //!< Base address of the output buffer. + uint32_t ui32OutOffset; //!< Value of the current output pointer offset. +} I2SControlTable; +#endif + +//***************************************************************************** +// +// Declare global pointer to the I2S data structure. +// +// The control table must be defined by the user as a global variable and the +// global pointer must then be assigned the address of the control table: +// +// I2SControlTable g_controlTable; +// g_pControlTable = &g_controlTable; +// +//***************************************************************************** +#ifndef DEPRECATED +extern I2SControlTable *g_pControlTable; +#endif + +//***************************************************************************** +// +// Defines for the I2S DMA buffer sizes +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_DMA_BUF_SIZE_64 0x00000040 +#define I2S_DMA_BUF_SIZE_128 0x00000080 +#define I2S_DMA_BUF_SIZE_256 0x00000100 +#endif + +//***************************************************************************** +// +// Defines for the I2S audio clock configuration +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_EXT_WCLK 0x00000001 +#define I2S_INT_WCLK 0x00000002 +#define I2S_INVERT_WCLK 0x00000004 +#define I2S_NORMAL_WCLK 0x00000000 +#endif + +//***************************************************************************** +// +// Defines for the audio data line input/output configuration +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_LINE_UNUSED 0x00000000 +#define I2S_LINE_INPUT 0x00000001 +#define I2S_LINE_OUTPUT 0x00000002 +#define I2S_LINE_MASK 0x00000003 +#endif + +//***************************************************************************** +// +// Defines for activating an audio channel. +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_CHAN0_ACT 0x00000100 +#define I2S_CHAN1_ACT 0x00000200 +#define I2S_CHAN2_ACT 0x00000400 +#define I2S_CHAN3_ACT 0x00000800 +#define I2S_CHAN4_ACT 0x00001000 +#define I2S_CHAN5_ACT 0x00002000 +#define I2S_CHAN6_ACT 0x00004000 +#define I2S_CHAN7_ACT 0x00008000 +#define I2S_MONO_MODE 0x00000100 +#define I2S_STEREO_MODE 0x00000300 +#define I2S_CHAN_CFG_MASK 0x0000FF00 +#endif + +#define I2S_CHAN0_MASK 0x00000001 +#define I2S_CHAN1_MASK 0x00000002 +#define I2S_CHAN2_MASK 0x00000004 +#define I2S_CHAN3_MASK 0x00000008 +#define I2S_CHAN4_MASK 0x00000010 +#define I2S_CHAN5_MASK 0x00000020 +#define I2S_CHAN6_MASK 0x00000040 +#define I2S_CHAN7_MASK 0x00000080 + +//***************************************************************************** +// +// Defines for the audio format configuration +// +//***************************************************************************** +#define I2S_MEM_LENGTH_16 0x00000000 // 16 bit size of word in memory +#define I2S_MEM_LENGTH_24 0x00000080 // 24 bit size of word in memory +#define I2S_POS_EDGE 0x00000040 // Sample on positive edge +#define I2S_NEG_EDGE 0x00000000 // Sample on negative edge +#define I2S_DUAL_PHASE_FMT 0x00000020 // Dual Phased audio format +#define I2S_SINGLE_PHASE_FMT 0x00000000 // Single Phased audio format +#define I2S_WORD_LENGTH_8 0x00000008 // Word length is 8 bits +#define I2S_WORD_LENGTH_16 0x00000010 // Word length is 16 bits +#define I2S_WORD_LENGTH_24 0x00000018 // Word length is 24 bits + +//***************************************************************************** +// +// Defines for the sample stamp counters +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_STMP0 0x00000001 // Sample stamp counter channel 0 +#define I2S_STMP1 0x00000002 // Sample stamp counter channel 1 +#endif +#define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when + // calculating the sample stamp + +//***************************************************************************** +// +// Defines for the interrupt +// +//***************************************************************************** +#define I2S_INT_DMA_IN 0x00000020 // DMA output buffer full interrupt +#define I2S_INT_DMA_OUT 0x00000010 // DMA input buffer empty interrupt +#define I2S_INT_TIMEOUT 0x00000008 // Word Clock Timeout +#define I2S_INT_BUS_ERR 0x00000004 // DMA Bus error +#define I2S_INT_WCLK_ERR 0x00000002 // Word Clock error +#define I2S_INT_PTR_ERR 0x00000001 // Data pointer error (DMA data was not updated in time). +#define I2S_INT_ALL 0x0000003F // All interrupts + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an I2S base address. +//! +//! This function determines if an I2S port base address is valid. +//! +//! \param ui32Base is the base address of the I2S port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +I2SBaseValid(uint32_t ui32Base) +{ + return(ui32Base == I2S0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Enables the I2S module for operation. +//! +//! \deprecated This function will be removed in a future release. +//! +//! \note The module should only be enabled after configuration. When the +//! module is disabled, no data or clocks will be generated on the I2S signals. +//! +//! \note Immediately after enabling the module the programmer should update +//! the DMA data pointer registers using \ref I2SPointerUpdate() to ensure a new +//! pointer is written before the DMA transfer completes. Failure to update +//! the pointer in time will result in an \ref I2S_INT_PTR_ERR. +//! +//! \param ui32Base is the I2S module base address. +//! +//! \return None +// +//***************************************************************************** +#ifndef DEPRECATED +extern void I2SEnable(uint32_t ui32Base); +#endif + +//***************************************************************************** +// +//! \brief Disables the I2S module for operation. +//! +//! \deprecated This function will be removed in a future release. +//! +//! This function will immediately disable the I2S module. To ensure that +//! all buffer operations are completed before shutting down, the correct +//! procedure is: +//! 1. Do not update the data pointers using \ref I2SPointerUpdate(). +//! 2. Await next interrupt resulting in \ref I2S_INT_PTR_ERR. +//! 3. Disable the I2S using \ref I2SDisable() and clear the pointer error using +//! \ref I2SIntClear(). +//! 4. Disable bit clock source (done externally). +//! +//! \param ui32Base is the I2S module base address. +//! +//! \return None +// +//***************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x0; +} +#endif + +//***************************************************************************** +// +//! \brief Configures the I2S module. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The word length defines the size of the word transmitted on the data +//! lines. For single phased formats \c I2S_WORD_LENGTH_x is the exact number +//! of bits per word. In dual phased format this is the maximum number of bits +//! per word. The size is set using \ref I2S_WORD_LENGTH_8, +//! \ref I2S_WORD_LENGTH_16 or \ref I2S_WORD_LENGTH_24. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui32FmtCfg is the bitwise OR of several options: +//! - Sample size: +//! - \ref I2S_MEM_LENGTH_16 +//! - \ref I2S_MEM_LENGTH_24 +//! - Clock edge sampling: +//! - \ref I2S_POS_EDGE +//! - \ref I2S_NEG_EDGE +//! - Phase: +//! - \ref I2S_DUAL_PHASE_FMT +//! - \ref I2S_SINGLE_PHASE_FMT +//! - Word length: +//! - \ref I2S_WORD_LENGTH_8 +//! - \ref I2S_WORD_LENGTH_16 +//! - \ref I2S_WORD_LENGTH_24 +//! \param ui32BitClkDelay defines the bit clock delay by setting the number of bit clock periods between the +//! positive word clock edge and the MSB of the first word in a phase. The bit +//! clock delay is determined by the ratio between the bit clock and the frame +//! clock and the chosen audio format. The bit clock delay \b must be configured +//! depending on the chosen audio format: +//! - 0 : Left Justified Format (LJF). +//! - 1 : I2S and DSP format. +//! - 2-255 : Right Justified format (RJF). +//! +//! \return None +//! +//! \sa \ref I2SChannelConfigure() +// +//***************************************************************************** +#ifndef DEPRECATED +extern void I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg, + uint32_t ui32BitClkDelay); +#endif + +//**************************************************************************** +// +//! \brief Setup the audio channel configuration. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The channel configuration is a bitwise OR of the input/output mode of each +//! data line and the active audio channels within a specific audio frame. +//! +//! Setting up the input/output mode use one of: +//! - \ref I2S_LINE_UNUSED +//! - \ref I2S_LINE_INPUT +//! - \ref I2S_LINE_OUTPUT +//! +//! For dual phased audio (LJF,RJF,I2S) only mono and stereo modes are allowed. +//! For single phased audio format (DSP) up to 8 active channels are allowed +//! on a single data line. For setting up the active channels in a frame use: +//! - Single phased, use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_ACT +//! - \ref I2S_CHAN1_ACT +//! - \ref I2S_CHAN2_ACT +//! - \ref I2S_CHAN3_ACT +//! - \ref I2S_CHAN4_ACT +//! - \ref I2S_CHAN5_ACT +//! - \ref I2S_CHAN6_ACT +//! - \ref I2S_CHAN7_ACT +//! - Dual phased, use one of: +//! - \ref I2S_MONO_MODE (same as \ref I2S_CHAN0_ACT) +//! - \ref I2S_STEREO_MODE (same as \ref I2S_CHAN0_ACT | \ref I2S_CHAN1_ACT) +//! +//! \note The audio format and the clock configuration should be set using +//! \ref I2SAudioFormatConfigure() +//! +//! \param ui32Base is base address of the I2S module. +//! \param ui32Chan0Cfg defines the channel configuration for data line 0. +//! \param ui32Chan1Cfg defines the channel configuration for data line 1. +//! +//! \return None +//! +//! \sa \ref I2SAudioFormatConfigure() +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg, + uint32_t ui32Chan1Cfg); +#endif + +//**************************************************************************** +// +//! \brief Configure the I2S frame clock. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Configure I2S clock to be either internal or external and either normal +//! or inverted. +//! +//! \note The bit clock configuration is done externally, but the internal/ +//! external setting must match what is chosen internally in the I2S module +//! for the frame clock. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32ClkConfig is the clock configuration parameter. Bitwise OR'ed +//! combination of clock source and clock polarity: +//! - Clock source: +//! - \ref I2S_EXT_WCLK : External clock. +//! - \ref I2S_INT_WCLK : Internal clock. +//! - Clock polarity: +//! - \ref I2S_NORMAL_WCLK : Normal clock. +//! - \ref I2S_INVERT_WCLK : Inverted clock. +//! +//! \return None +// +//**************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup register WCLK Source. + HWREG(I2S0_BASE + I2S_O_AIFWCLKSRC) = ui32ClkConfig & + (I2S_AIFWCLKSRC_WCLK_INV_M | + I2S_AIFWCLKSRC_WCLK_SRC_M); +} +#endif + +//**************************************************************************** +// +//! \brief Set the input buffer pointers. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will +//! occur and all outputs will be disabled. +//! +//! \note At startup the next data pointer should be +//! written just before and just after calling the \ref I2SEnable(). +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32InBufBase is the address of the input buffer. +//! \param ui32OutBufBase is the address of the output buffer. +//! \param ui16DMABufSize is the size of the DMA buffers. Must be greater than 0! +//! \param ui16ChanBufSize is the size of the channel buffers. +//! +//! \return None +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase, + uint32_t ui32OutBufBase, uint16_t ui16DMABufSize, + uint16_t ui16ChanBufSize); +#endif + +//**************************************************************************** +// +//! \brief Update the buffer pointers. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur +//! and all outputs will be disabled. Nothing is preventing the pointers from +//! being identical, but this function relies on both pointers (input or +//! output pointers) are pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param bInput determines whether to update input or output pointer. +//! - \c true : Update input pointer. +//! - \c false : Update output pointer +//! +//! \return None +//! +//! \sa \ref I2SPointerSet() +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SPointerUpdate(uint32_t ui32Base, bool bInput); +#endif + +//**************************************************************************** +// +//! \brief Set a buffer pointer (input or output) directly. +//! +//! \deprecated This function will be removed in a future release. +//! +//! This function allows bypassing of the pointers in the global control table. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur +//! and all outputs will be disabled. Nothing is preventing the pointers from +//! being identical, but this function relies on both pointers (input or +//! output pointers) are pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param bInput determines whether to update input or output pointer. +//! - \c true : Update input pointer. +//! - \c false : Update output pointer +//! \param pNextPointer is a void pointer to user defined buffer. +//! +//! \return None +//! +//! \sa \ref I2SPointerUpdate() +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer); +#endif + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for an I2S interrupt in the dynamic interrupt table. +//! +//! \deprecated This function will be removed in a future release. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific I2S interrupts must be enabled via \ref I2SIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param pfnHandler is a pointer to the function to be called when the +//! I2S interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Register the interrupt handler. + IntRegister(INT_I2S_IRQ, pfnHandler); + + // Enable the I2S interrupt. + IntEnable(INT_I2S_IRQ); +} +#endif + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a I2S interrupt in the dynamic interrupt table. +//! +//! \deprecated This function will be removed in a future release. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when an I2S interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \param ui32Base is the base address of the I2S port. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SIntUnregister(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the interrupt. + IntDisable(INT_I2S_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_I2S_IRQ); +} +#endif + +//***************************************************************************** +// +//! \brief Configure the sample stamp generator. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param bInput enables triggering of the sample stamp generator on input. +//! \param bOutput enables triggering of the sample stamp generator on output. +//! +//! \return None +// +//***************************************************************************** +#ifndef DEPRECATED +extern void I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, + bool bOutput); +#endif + +//***************************************************************************** +// +//! \brief Enables individual I2S interrupt sources. +//! +//! This function enables the indicated I2S interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2S port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +//! - \ref I2S_INT_ALL (covers all the above) +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +I2SIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(I2S0_BASE + I2S_O_IRQMASK) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual I2S interrupt sources. +//! +//! This function disables the indicated I2S interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2S port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +//! - \ref I2S_INT_ALL (covers all the above) +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +I2SIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(I2S0_BASE + I2S_O_IRQMASK) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the specified I2S. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the I2S port +//! \param bMasked selects between raw and masked interrupt status: +//! - \c false : Raw interrupt status is required. +//! - \c true : Masked interrupt status is required. +//! +//! \return Returns the current interrupt status as a vector of: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2SIntStatus(uint32_t ui32Base, bool bMasked) +{ + uint32_t ui32Mask; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + ui32Mask = HWREG(I2S0_BASE + I2S_O_IRQFLAGS); + return(ui32Mask & HWREG(I2S0_BASE + I2S_O_IRQMASK)); + } + else + { + return(HWREG(I2S0_BASE + I2S_O_IRQFLAGS)); + } +} + +//***************************************************************************** +// +//! \brief Clears I2S interrupt sources. +//! +//! The specified I2S interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the I2S port. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +//! - \ref I2S_INT_ALL (covers all the above) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Clear the requested interrupt sources. + HWREG(I2S0_BASE + I2S_O_IRQCLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Enable the Sample Stamp generator. +//! +//! Use this function to enable the sample stamp generators. +//! +//! \note It is the user's responsibility to ensure that the sample stamp +//! generator is properly configured before it is enabled. It is the setting +//! of the Input and Output triggers configured using \ref I2SSampleStampConfigure() +//! that triggers the start point of the audio streams. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Set the enable bit. + HWREG(I2S0_BASE + I2S_O_STMPCTL) = I2S_STMPCTL_STMP_EN; +} + +//***************************************************************************** +// +//! \brief Disable the Sample Stamp generator. +//! +//! Use this function to disable the sample stamp generators. When the sample +//! stamp generator is disabled, the clock counters are automatically cleared. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Clear the enable bit. + HWREG(I2S0_BASE + I2S_O_STMPCTL) = 0; + +} + +//***************************************************************************** +// +//! \brief Get the current value of a sample stamp counter. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32Channel is the sample stamp counter to sample +//! +//! \return Returns the current value of the selected sample stamp channel. +// +//***************************************************************************** +extern uint32_t I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel); + +//***************************************************************************** +// +//! \brief Starts the I2S. +//! +//! I2S must be configured before it is started. +//! +//! \note Immediately after enabling the module the programmer must update +//! the DMA data pointer registers using \ref I2SInPointerSet() and +//! \ref I2SOutPointerSet() to ensure a new pointer is written before the DMA +//! transfer completes. Failure to update the pointer in time will result in +//! an \ref I2S_INT_PTR_ERR. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui8FixDMALength is the length of the DMA buffer: this will allow +//! the DMA to read ui8FixDMALength between to pointer refreshes. +//! +//! \return None +//! +//! \sa \ref I2SStop() +// +//***************************************************************************** +__STATIC_INLINE void I2SStart(uint32_t ui32Base, uint8_t ui8FixDMALength) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Enable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = ui8FixDMALength; +} + +//***************************************************************************** +// +//! \brief Stops the I2S module for operation. +//! +//! This function will immediately disable the I2S module. To ensure that +//! all buffer operations are completed before shutting down, the correct +//! procedure is: +//! 1. Do not update the data pointers using \ref I2SInPointerSet() and +//! \ref I2SOutPointerSet(). +//! 2. Await that values returned by \ref I2SInPointerNextGet(), +//! \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and \ref I2SOutPointerGet() +//! are zero. +//! 3. Disable the I2S using \ref I2SStop() and clear the pointer +//! error using \ref I2SIntClear(). +//! 4. Disable bit clock source (done externally). +//! +//! \param ui32Base is the I2S module base address. +//! +//! \return None +//! +//! \sa \ref I2SStart() +// +//***************************************************************************** +__STATIC_INLINE void I2SStop(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x00; +} + +//***************************************************************************** +// +//! \brief Configure the serial format of the I2S module. +//! +//! The word length defines the size of the word transmitted on the data +//! lines. For single phased formats \c ui8BitsPerSample is the exact number +//! of bits per word. In dual phased format this is the maximum number of bits +//! per word. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui8iDataDelay is the number of BCLK periods between the first WCLK +//! edge and the MSB of the first audio channel data transferred during +//! the phase. +//! \param ui8iMemory24Bits selects if the samples in memory are coded on 16 bits +//! or 24 bits. Possible values are: +//! - \ref I2S_MEM_LENGTH_16 +//! - \ref I2S_MEM_LENGTH_24 +//! \param ui8iSamplingEdge selects if sampling on falling or rising edges. +//! Possible values are: +//! - \ref I2S_NEG_EDGE +//! - \ref I2S_POS_EDGE +//! \param boolDualPhase must be set to true for dual phase and to false for +//! single phase and user-defined phase. +//! \param ui8BitsPerSample is the number of bits transmitted for each sample. +//! If this number does not match with the memory length selected +//! (16 bits or24 bits), samples will be truncated or padded. +//! \param ui16transmissionDelay is the number of WCLK periods before the first +//! transmission. +//! +//! \return None +//! +//! \sa \ref I2SFrameConfigure() +// +//***************************************************************************** +__STATIC_INLINE void +I2SFormatConfigure(uint32_t ui32Base, + uint8_t ui8iDataDelay, + uint8_t ui8iMemory24Bits, + uint8_t ui8iSamplingEdge, + bool boolDualPhase, + uint8_t ui8BitsPerSample, + uint16_t ui16transmissionDelay) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui8BitsPerSample <= I2S_AIFFMTCFG_WORD_LEN_MAX); + ASSERT(ui8BitsPerSample >= I2S_AIFFMTCFG_WORD_LEN_MIN); + + // Setup register AIFFMTCFG Source. + HWREGH(I2S0_BASE + I2S_O_AIFFMTCFG) = + (ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) | + (ui8iMemory24Bits << I2S_AIFFMTCFG_MEM_LEN_24_S) | + (ui8iSamplingEdge << I2S_AIFFMTCFG_SMPL_EDGE_S ) | + (boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) | + (ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S ); + + // Number of WCLK periods before the first read / write + HWREGH(I2S0_BASE + I2S_O_STMPWPER) = ui16transmissionDelay; +} + +//**************************************************************************** +// +//! \brief Setup the two interfaces SD0 and SD1 (also called AD0 and AD1). +//! +//! This function sets interface's direction and activated channels. +//! +//! \param ui32Base is base address of the I2S module. +//! \param ui8StatusAD0 defines the usage of AD0 +//! 0x00: AD0 is disabled +//! 0x01, AD0 is an input +//! 0x02, AD0 is an output +//! \param ui8ChanAD0 defines the channel mask for AD0. +//! Use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_MASK +//! - \ref I2S_CHAN1_MASK +//! - \ref I2S_CHAN2_MASK +//! - \ref I2S_CHAN3_MASK +//! - \ref I2S_CHAN4_MASK +//! - \ref I2S_CHAN5_MASK +//! - \ref I2S_CHAN6_MASK +//! - \ref I2S_CHAN7_MASK +//! \param ui8StatusAD1 defines the usage of AD1 +//! 0x00: AD1 is disabled +//! 0x10, AD1 is an input +//! 0x20, AD1 is an output +//! \param ui8ChanAD1 defines the channel mask for AD1. +//! Use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_MASK +//! - \ref I2S_CHAN1_MASK +//! - \ref I2S_CHAN2_MASK +//! - \ref I2S_CHAN3_MASK +//! - \ref I2S_CHAN4_MASK +//! - \ref I2S_CHAN5_MASK +//! - \ref I2S_CHAN6_MASK +//! - \ref I2S_CHAN7_MASK +//! +//! \return None +//! +//! \sa \ref I2SFormatConfigure() +// +//**************************************************************************** +__STATIC_INLINE void +I2SFrameConfigure(uint32_t ui32Base, + uint8_t ui8StatusAD0, uint8_t ui8ChanAD0, + uint8_t ui8StatusAD1, uint8_t ui8ChanAD1) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Configure input/output channels. + HWREGB(I2S0_BASE + I2S_O_AIFDIRCFG) = (ui8StatusAD0 | ui8StatusAD1); + + // Configure the valid channel mask. + HWREGB(I2S0_BASE + I2S_O_AIFWMASK0) = ui8ChanAD0; + HWREGB(I2S0_BASE + I2S_O_AIFWMASK1) = ui8ChanAD1; +} + +//**************************************************************************** +// +//! \brief Configure the I2S frame clock (also called WCLK or WS). +//! +//! Configure WCLK clock to be either internal (master) or external (slave). +//! Configure WCLK clock either normal or inverted. +//! +//! \note The bit clock configuration is done externally, but the internal/ +//! external setting must match what is chosen internally in the I2S module +//! for the frame clock. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param boolMaster false: the device is a slave (external clock) +//! true: the device is a master (internal clock) +//! \param boolWCLKInvert false: WCLK is not inverted +//! true: WCLK is internally inverted +//! +//! \return None +// +//**************************************************************************** +__STATIC_INLINE void +I2SWclkConfigure(uint32_t ui32Base, + bool boolMaster, + bool boolWCLKInvert) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui8ClkSource < I2S_AIFWCLKSRC_WCLK_SRC_RESERVED); + + // if(boolMaster == 0) then ui8ClkSource = 1 + // if(boolMaster == 1) then ui8ClkSource = 2 + uint8_t ui8ClkSource = (uint8_t)boolMaster + 0x01; + + // Setup register WCLK Source. + HWREGB(I2S0_BASE + I2S_O_AIFWCLKSRC) = + ((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) | + (boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S )); +} + +//**************************************************************************** +// +//! \brief Set the input buffer pointer. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR +//! will occur and all inputs and outputs will be disabled. +//! This function relies on pointer is pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32NextPointer is the adress of the data +//! +//! \return None +//! +//! \sa \ref I2SOutPointerSet() +// +//**************************************************************************** +__STATIC_INLINE void +I2SInPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = ui32NextPointer; +} + +//**************************************************************************** +// +//! \brief Set the output buffer pointer. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR +//! will occur and all inputs and outputs will be disabled. +//! This function relies on pointer is pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32NextPointer is the adress of the data +//! +//! \return None +//! +//! \sa \ref I2SInPointerSet() +// +//**************************************************************************** +__STATIC_INLINE void +I2SOutPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = ui32NextPointer; +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR NEXT IN register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR NEXT IN. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SInPointerNextGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT)); +} + + +//**************************************************************************** +// +//! \brief Get value stored in PTR NEXT OUT register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR NEXT OUT. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SOutPointerNextGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT)); +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR IN register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR IN. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SInPointerGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFINPTR)); +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR OUT register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR OUT. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SOutPointerGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTR)); +} + +//***************************************************************************** +// +//! \brief Configure the IN sample stamp generator. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui16TrigValue value used to set the trigger. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampInConfigure(uint32_t ui32Base, uint16_t ui16TrigValue) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup the sample stamp trigger for input streams. + HWREGH(I2S0_BASE + I2S_O_STMPINTRIG) = ui16TrigValue; +} + +//***************************************************************************** +// +//! \brief Configure the OUT sample stamp generator. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui16TrigValue value used to set the trigger. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampOutConfigure(uint32_t ui32Base, uint16_t ui16TrigValue) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup the sample stamp trigger for output streams. + HWREGH(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui16TrigValue; +} + +//***************************************************************************** +// +//! \brief Add the specified value to the WCLK count. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param i16Value is the offset to add to the counter (this value can be negative) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SWclkCounterConfigure(uint32_t ui32Base, int16_t i16Value) +{ + uint16_t ui16MinusValue; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + if (i16Value >= 0) + { + HWREGH(I2S0_BASE + I2S_O_STMPWADD) = i16Value; + } + else + { + ui16MinusValue = (uint16_t)(-i16Value); + HWREGH(I2S0_BASE + I2S_O_STMPWADD) = HWREGH(I2S0_BASE + I2S_O_STMPWPER) - ui16MinusValue; + } +} + +//***************************************************************************** +// +//! \brief Reset the WCLK count. +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SWclkCounterReset(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREGH(I2S0_BASE + I2S_O_STMPWSET) = 0; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_I2SEnable + #undef I2SEnable + #define I2SEnable ROM_I2SEnable + #endif + #ifdef ROM_I2SAudioFormatConfigure + #undef I2SAudioFormatConfigure + #define I2SAudioFormatConfigure ROM_I2SAudioFormatConfigure + #endif + #ifdef ROM_I2SChannelConfigure + #undef I2SChannelConfigure + #define I2SChannelConfigure ROM_I2SChannelConfigure + #endif + #ifdef ROM_I2SBufferConfig + #undef I2SBufferConfig + #define I2SBufferConfig ROM_I2SBufferConfig + #endif + #ifdef ROM_I2SPointerUpdate + #undef I2SPointerUpdate + #define I2SPointerUpdate ROM_I2SPointerUpdate + #endif + #ifdef ROM_I2SPointerSet + #undef I2SPointerSet + #define I2SPointerSet ROM_I2SPointerSet + #endif + #ifdef ROM_I2SSampleStampConfigure + #undef I2SSampleStampConfigure + #define I2SSampleStampConfigure ROM_I2SSampleStampConfigure + #endif + #ifdef ROM_I2SSampleStampGet + #undef I2SSampleStampGet + #define I2SSampleStampGet ROM_I2SSampleStampGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2S_H__ + +//**************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//**************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h new file mode 100644 index 0000000..27ddceb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h @@ -0,0 +1,141 @@ +/****************************************************************************** +* Filename: i2s_doc.h +* Revised: $$ +* Revision: $$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup i2s_api +//! @{ +//! \section sec_i2s Introduction +//! +//! The I2S API provides a set of functions for using the I2S module. +//! This module provides a standardized serial interface to transfer +//! audio samples from and to external audio devices such as a codec, +//! DAC, or ADC. +//! +//! The I2S module has the following features: +//! - Audio clock signals are internally generated by the PRCM module +//! or externally by another device. +//! - One or two data pins, which can be configured independently as +//! input or output +//! - Various data formats according to the settings of the module +//! - Up to two channels per data pin for dual phase formats and up +//! to eight channels per data pin for single phase formats +//! - DMA with double-buffered pointers +//! - Error detection for DMA and audio clock signal integrity +//! - A Samplestamp generator that allows maintaining of constant +//! audio latency +//! +//! The I2S module is configured through the functions \ref I2SFormatConfigure(), +//! \ref I2SFrameConfigure() and \ref I2SWclkConfigure(). +//! Transfers are enabled using \ref I2SStart(). Transfers are disabled using +//! \ref I2SStop(). Please note that a specific procedure exists in order +//! to disable transfers without losing data (refer to \ref I2SStop()). +//! +//! Data are transmitted using the two double-buffered pointers. +//! For each interface, two registers are set with the address of the data to +//! transfer. These registers are named INPTR and INPTRNEXT for the input +//! interface and OUTPTR and OUTPTRNEXT for the output. When PTR is consumed, +//! the hardware copies the content of PTRNEXT into PTR and the next transfer +//! begins. +//! The address of the next value to write or to read in memory (i.e. to receive +//! or to send out) is set using \ref I2SInPointerSet() and \ref I2SOutPointerSet(). +//! The values contented by INPTRNEXT, OUTPTRNEXT, INPTR and OUTPTR can be read using +//! \ref I2SInPointerNextGet(), \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and +//! \ref I2SOutPointerGet() functions. +//! +//! Interrupts can help the user to refresh pointers on time. Interrupts can also +//! be used to detect I2S errors. \ref I2SIntEnable() and \ref I2SIntDisable() +//! activate and deactivate interrupt(s). Interrupt status can be read through +//! \ref I2SIntStatus() and a pending interrupt can be acquitted by +//! \ref I2SIntClear() function. +//! +//! The sample stamps generator can be configured to slightly delay the +//! emission or the reception of the data (based on the number of WCLK +//! cycles) using \ref I2SSampleStampInConfigure(), \ref I2SSampleStampOutConfigure(), +//! \ref I2SWclkCounterReset() and \ref I2SWclkCounterConfigure(). The current sample stamp +//! can be computed using \ref I2SSampleStampGet(). +//! To finish, the sample stamps generator can be enable and disable using +//! the following functions: \ref I2SSampleStampEnable() and +//! \ref I2SSampleStampDisable(). +//! The sample stamps generator must be enabled prior to any transfer. +//! +//! Note: Other functions contained in the PRCM API are required to handle I2S. +//! +//! \section sec_i2s_api API +//! +//! Two APIs are coexisting. +//! It is recommended to only use the new API as the old one is deprecated and +//! will be removed soon. +//! +//! New API: +//! Functions to perform I2S configuration: +//! - \ref I2SStart() +//! - \ref I2SStop() +//! - \ref I2SFormatConfigure() +//! - \ref I2SFrameConfigure() +//! - \ref I2SWclkConfigure() +//! +//! Functions to perform transfers: +//! - \ref I2SInPointerSet() +//! - \ref I2SOutPointerSet() +//! - \ref I2SInPointerGet() +//! - \ref I2SOutPointerGet() +//! - \ref I2SInPointerNextGet() +//! - \ref I2SOutPointerNextGet() +//! +//! Functions to handle interruptions: +//! - \ref I2SIntEnable() +//! - \ref I2SIntDisable() +//! - \ref I2SIntStatus() +//! - \ref I2SIntClear() +//! +//! Functions to handle sample stamps +//! - \ref I2SSampleStampEnable() +//! - \ref I2SSampleStampDisable() +//! - \ref I2SSampleStampInConfigure() +//! - \ref I2SSampleStampOutConfigure() +//! - \ref I2SSampleStampGet() +//! - \ref I2SWclkCounterConfigure() +//! - \ref I2SWclkCounterReset() +//! +//! Old API: +//! \ref I2SEnable(), \ref I2SDisable(), \ref I2SAudioFormatConfigure(), +//! \ref I2SChannelConfigure(), \ref I2SClockConfigure(), +//! \ref I2SBufferConfig(), \ref I2SIntEnable(), \ref I2SIntDisable(), +//! \ref I2SIntStatus(), \ref I2SIntClear(), \ref I2SSampleStampEnable(), +//! \ref I2SSampleStampDisable(), \ref I2SSampleStampGet(), +//! \ref I2SPointerSet (), \ref I2SPointerUpdate(), +//! \ref I2SSampleStampConfigure(), \ref I2SIntRegister(), +//! \ref I2SIntUnregister() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.c new file mode 100644 index 0000000..b902690 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.c @@ -0,0 +1,469 @@ +/****************************************************************************** +* Filename: interrupt.c +* Revised: 2017-05-19 11:31:39 +0200 (Fri, 19 May 2017) +* Revision: 49017 +* +* Description: Driver for the NVIC Interrupt Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "interrupt.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef IntRegister + #define IntRegister NOROM_IntRegister + #undef IntUnregister + #define IntUnregister NOROM_IntUnregister + #undef IntPriorityGroupingSet + #define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet + #undef IntPriorityGroupingGet + #define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet + #undef IntPrioritySet + #define IntPrioritySet NOROM_IntPrioritySet + #undef IntPriorityGet + #define IntPriorityGet NOROM_IntPriorityGet + #undef IntEnable + #define IntEnable NOROM_IntEnable + #undef IntDisable + #define IntDisable NOROM_IntDisable + #undef IntPendSet + #define IntPendSet NOROM_IntPendSet + #undef IntPendGet + #define IntPendGet NOROM_IntPendGet + #undef IntPendClear + #define IntPendClear NOROM_IntPendClear +#endif + +//***************************************************************************** +// +//! This is a mapping between priority grouping encodings and the number of +//! preemption priority bits. +// +//***************************************************************************** +static const uint32_t g_pui32Priority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; + +//***************************************************************************** +// +//! This is a mapping between interrupt number and the register that contains +//! the priority encoding for that interrupt. +// +//***************************************************************************** +static const uint32_t g_pui32Regs[] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13 +}; + +//***************************************************************************** +// +//! \brief The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts should be disabled before unregistering the +//! corresponding handler, this should never be called. +//! +//! \return None +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // Go into an infinite loop. + while(1) + { + } +} + +//***************************************************************************** +// +//! \brief Global pointer to the (dynamic) interrupt vector table when placed in SRAM. +//! +//! Interrupt vector table is placed at "vtable_ram" defined in the linker file +//! provided by Texas Instruments. By default, this is at the beginning of SRAM. +//! +//! \note See \ti_code{interrupt.c} for compiler specific implementation! +// +//***************************************************************************** +#if defined(DOXYGEN) +// Dummy void pointer used as placeholder to generate Doxygen documentation. +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma data_alignment=256 +static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ ".vtable_ram"; +#elif defined(__TI_COMPILER_VERSION__) +#pragma DATA_ALIGN(g_pfnRAMVectors, 256) +#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable_ram") +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#elif defined (__CC_ARM) +static __attribute__((section("vtable_ram"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256))); +#else +static __attribute__((section("vtable_ram"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256))); +#endif + +//***************************************************************************** +// +// Registers a function to be called when an interrupt occurs. +// +//***************************************************************************** +void +IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)) +{ + uint32_t ui32Idx, ui32Value; + + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Make sure that the RAM vector table is correctly aligned. + ASSERT(((uint32_t)g_pfnRAMVectors & 0x000000ff) == 0); + + // See if the RAM vector table has been initialized. + if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors) + { + // Copy the vector table from the beginning of FLASH to the RAM vector + // table. + ui32Value = HWREG(NVIC_VTABLE); + for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++) + { + g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) + + ui32Value); + } + + // Point NVIC at the RAM vector table. + HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors; + } + + // Save the interrupt handler. + g_pfnRAMVectors[ui32Interrupt] = pfnHandler; +} + +//***************************************************************************** +// +// Unregisters the function to be called when an interrupt occurs. +// +//***************************************************************************** +void +IntUnregister(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Reset the interrupt handler. + g_pfnRAMVectors[ui32Interrupt] = IntDefaultHandler; +} + +//***************************************************************************** +// +// Sets the priority grouping of the interrupt controller. +// +//***************************************************************************** +void +IntPriorityGroupingSet(uint32_t ui32Bits) +{ + // Check the arguments. + ASSERT(ui32Bits < NUM_PRIORITY); + + // Set the priority grouping. + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; +} + +//***************************************************************************** +// +// Gets the priority grouping of the interrupt controller +// +//***************************************************************************** +uint32_t +IntPriorityGroupingGet(void) +{ + uint32_t ui32Loop, ui32Value; + + // Read the priority grouping. + ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // Loop through the priority grouping values. + for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++) + { + // Stop looping if this value matches. + if(ui32Value == g_pui32Priority[ui32Loop]) + { + break; + } + } + + // Return the number of priority bits. + return(ui32Loop); +} + +//***************************************************************************** +// +// Sets the priority of an interrupt +// +//***************************************************************************** +void +IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority) +{ + uint32_t ui32Temp; + + // Check the arguments. + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + ASSERT(ui8Priority <= INT_PRI_LEVEL7); + + // Set the interrupt priority. + ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); + ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3))); + ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3)); + HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; +} + +//***************************************************************************** +// +// Gets the priority of an interrupt +// +//***************************************************************************** +int32_t +IntPriorityGet(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + + // Return the interrupt priority. + return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) & + 0xFF); +} + +//***************************************************************************** +// +// Enables an interrupt +// +//***************************************************************************** +void +IntEnable(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to enable. + if(ui32Interrupt == INT_MEMMANAGE_FAULT) + { + // Enable the MemManage interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ui32Interrupt == INT_BUS_FAULT) + { + // Enable the bus fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ui32Interrupt == INT_USAGE_FAULT) + { + // Enable the usage fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Enable the System Tick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Enable the general interrupt. + HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Enable the general interrupt. + HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48); + } +} + +//***************************************************************************** +// +// Disables an interrupt +// +//***************************************************************************** +void +IntDisable(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to disable. + if(ui32Interrupt == INT_MEMMANAGE_FAULT) + { + // Disable the MemManage interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ui32Interrupt == INT_BUS_FAULT) + { + // Disable the bus fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ui32Interrupt == INT_USAGE_FAULT) + { + // Disable the usage fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Disable the System Tick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Disable the general interrupt. + HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Disable the general interrupt. + HWREG(NVIC_DIS1) = 1 << (ui32Interrupt - 48); + } +} + +//***************************************************************************** +// +// Pends an interrupt +// +//***************************************************************************** +void +IntPendSet(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to pend. + if(ui32Interrupt == INT_NMI_FAULT) + { + // Pend the NMI interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; + } + else if(ui32Interrupt == INT_PENDSV) + { + // Pend the PendSV interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Pend the SysTick interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Pend the general interrupt. + HWREG(NVIC_PEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Pend the general interrupt. + HWREG(NVIC_PEND1) = 1 << (ui32Interrupt - 48); + } +} + +//***************************************************************************** +// +// Query whether an interrupt is pending +// +//***************************************************************************** +bool +IntPendGet(uint32_t ui32Interrupt) +{ + uint32_t ui32IntPending; + + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Assume no interrupts are pending. + ui32IntPending = 0; + + // The lower 16 IRQ vectors are unsupported by this function + if (ui32Interrupt < 16) + { + + return 0; + } + + // Subtract lower 16 irq vectors + ui32Interrupt -= 16; + + // Check if the interrupt is pending + ui32IntPending = HWREG(NVIC_PEND0 + (ui32Interrupt / 32)); + ui32IntPending &= (1 << (ui32Interrupt & 31)); + + return ui32IntPending ? true : false; +} + +//***************************************************************************** +// +// Unpends an interrupt +// +//***************************************************************************** +void +IntPendClear(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to unpend. + if(ui32Interrupt == INT_PENDSV) + { + // Unpend the PendSV interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Unpend the SysTick interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Unpend the general interrupt. + HWREG(NVIC_UNPEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Unpend the general interrupt. + HWREG(NVIC_UNPEND1) = 1 << (ui32Interrupt - 48); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h new file mode 100644 index 0000000..1d70d80 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h @@ -0,0 +1,718 @@ +/****************************************************************************** +* Filename: interrupt.h +* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) +* Revision: 50272 +* +* Description: Defines and prototypes for the NVIC Interrupt Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_types.h" +#include "../inc/hw_nvic.h" +#include "debug.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define IntRegister NOROM_IntRegister + #define IntUnregister NOROM_IntUnregister + #define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet + #define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet + #define IntPrioritySet NOROM_IntPrioritySet + #define IntPriorityGet NOROM_IntPriorityGet + #define IntEnable NOROM_IntEnable + #define IntDisable NOROM_IntDisable + #define IntPendSet NOROM_IntPendSet + #define IntPendGet NOROM_IntPendGet + #define IntPendClear NOROM_IntPendClear +#endif + +//***************************************************************************** +// +// Macro to generate an interrupt priority mask based on the number of bits +// of priority supported by the hardware. For CC26xx the number of priority +// bit is 3 as defined in hw_types.h. The priority mask is +// defined as +// +// INT_PRIORITY_MASK = ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) +// +//***************************************************************************** +#define INT_PRIORITY_MASK 0x000000E0 +#define INT_PRI_LEVEL0 0x00000000 +#define INT_PRI_LEVEL1 0x00000020 +#define INT_PRI_LEVEL2 0x00000040 +#define INT_PRI_LEVEL3 0x00000060 +#define INT_PRI_LEVEL4 0x00000080 +#define INT_PRI_LEVEL5 0x000000A0 +#define INT_PRI_LEVEL6 0x000000C0 +#define INT_PRI_LEVEL7 0x000000E0 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Registers a function as an interrupt handler in the dynamic vector table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function writes a function pointer to the dynamic interrupt vector table +//! in SRAM to register the function as an interrupt handler (ISR). When the corresponding +//! interrupt occurs, and it has been enabled (see \ref IntEnable()), the function +//! pointer is fetched from the dynamic vector table, and the System CPU will +//! execute the interrupt handler. +//! +//! \note The first call to this function (directly or indirectly via a peripheral +//! driver interrupt register function) copies the interrupt vector table from +//! Flash to SRAM. NVIC uses the static vector table (in Flash) until this function +//! is called. +//! +//! \param ui32Interrupt specifies the index in the vector table to modify. +//! - System exceptions (vectors 0 to 15): +//! - INT_NMI_FAULT +//! - INT_HARD_FAULT +//! - INT_MEMMANAGE_FAULT +//! - INT_BUS_FAULT +//! - INT_USAGE_FAULT +//! - INT_SVCALL +//! - INT_DEBUG +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts (vectors >15): +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_PKA_IRQ +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_SSI1_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! - INT_OSC_COMB +//! - INT_AUX_TIMER2_EV0 +//! - INT_UART1_COMB +//! - INT_BATMON_COMB +//! \param pfnHandler is a pointer to the function to register as interrupt handler. +//! +//! \return None. +//! +//! \sa \ref IntUnregister(), \ref IntEnable() +// +//***************************************************************************** +extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler in the dynamic vector table. +//! +//! This function removes an interrupt handler from the dynamic vector table and +//! replaces it with the default interrupt handler \ref IntDefaultHandler(). +//! +//! \note Remember to disable the interrupt before removing its interrupt handler +//! from the vector table. +//! +//! \param ui32Interrupt specifies the index in the vector table to modify. +//! - See \ref IntRegister() for list of valid arguments. +//! +//! \return None. +//! +//! \sa \ref IntRegister(), \ref IntDisable() +// +//***************************************************************************** +extern void IntUnregister(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Sets the priority grouping of the interrupt controller. +//! +//! This function specifies the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! Three bits are available for hardware interrupt prioritization thus priority +//! grouping values of three through seven have the same effect. +//! +//! \param ui32Bits specifies the number of bits of preemptable priority. +//! - 0 : No pre-emption priority, eight bits of subpriority. +//! - 1 : One bit of pre-emption priority, seven bits of subpriority +//! - 2 : Two bits of pre-emption priority, six bits of subpriority +//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority +//! +//! \return None +//! +//! \sa \ref IntPrioritySet() +// +//***************************************************************************** +extern void IntPriorityGroupingSet(uint32_t ui32Bits); + +//***************************************************************************** +// +//! \brief Gets the priority grouping of the interrupt controller. +//! +//! This function returns the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! \return Returns the number of bits of preemptable priority. +//! - 0 : No pre-emption priority, eight bits of subpriority. +//! - 1 : One bit of pre-emption priority, seven bits of subpriority +//! - 2 : Two bits of pre-emption priority, six bits of subpriority +//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority +// +//***************************************************************************** +extern uint32_t IntPriorityGroupingGet(void); + +//***************************************************************************** +// +//! \brief Sets the priority of an interrupt. +//! +//! This function sets the priority of an interrupt, including system exceptions. +//! When multiple interrupts are asserted simultaneously, the ones with the highest +//! priority are processed before the lower priority interrupts. Smaller numbers +//! correspond to higher interrupt priorities thus priority 0 is the highest +//! interrupt priority. +//! +//! \warning This function does not support setting priority of interrupt vectors +//! one through three which are: +//! - 1: Reset handler +//! - 2: NMI handler +//! - 3: Hard fault handler +//! +//! \param ui32Interrupt specifies the index in the vector table to change priority for. +//! - System exceptions: +//! - INT_MEMMANAGE_FAULT +//! - INT_BUS_FAULT +//! - INT_USAGE_FAULT +//! - INT_SVCALL +//! - INT_DEBUG +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_PKA_IRQ +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_SSI1_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! - INT_OSC_COMB +//! - INT_AUX_TIMER2_EV0 +//! - INT_UART1_COMB +//! - INT_BATMON_COMB +//! \param ui8Priority specifies the priority of the interrupt. +//! - \ref INT_PRI_LEVEL0 : Highest priority. +//! - \ref INT_PRI_LEVEL1 +//! - \ref INT_PRI_LEVEL2 +//! - \ref INT_PRI_LEVEL3 +//! - \ref INT_PRI_LEVEL4 +//! - \ref INT_PRI_LEVEL5 +//! - \ref INT_PRI_LEVEL6 +//! - \ref INT_PRI_LEVEL7 : Lowest priority. +//! +//! \return None +//! +//! \sa \ref IntPriorityGroupingSet() +// +//***************************************************************************** +extern void IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority); + +//***************************************************************************** +// +//! \brief Gets the priority of an interrupt. +//! +//! This function gets the priority of an interrupt. +//! +//! \warning This function does not support getting priority of interrupt vectors +//! one through three which are: +//! - 1: Reset handler +//! - 2: NMI handler +//! - 3: Hard fault handler +//! +//! \param ui32Interrupt specifies the index in the vector table to read priority of. +//! - See \ref IntPrioritySet() for list of valid arguments. +//! +//! \return Returns the interrupt priority: +//! - \ref INT_PRI_LEVEL0 : Highest priority. +//! - \ref INT_PRI_LEVEL1 +//! - \ref INT_PRI_LEVEL2 +//! - \ref INT_PRI_LEVEL3 +//! - \ref INT_PRI_LEVEL4 +//! - \ref INT_PRI_LEVEL5 +//! - \ref INT_PRI_LEVEL6 +//! - \ref INT_PRI_LEVEL7 : Lowest priority. +// +//***************************************************************************** +extern int32_t IntPriorityGet(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Enables an interrupt or system exception. +//! +//! This function enables the specified interrupt in the interrupt controller. +//! +//! \note If a fault condition occurs while the corresponding system exception +//! is disabled, the fault is treated as a Hard Fault. +//! +//! \param ui32Interrupt specifies the index in the vector table to enable. +//! - System exceptions: +//! - INT_MEMMANAGE_FAULT +//! - INT_BUS_FAULT +//! - INT_USAGE_FAULT +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_PKA_IRQ +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_SSI1_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! - INT_OSC_COMB +//! - INT_AUX_TIMER2_EV0 +//! - INT_UART1_COMB +//! - INT_BATMON_COMB +//! +//! \return None +//! +//! \sa \ref IntDisable() +// +//***************************************************************************** +extern void IntEnable(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Disables an interrupt or system exception. +//! +//! This function disables the specified interrupt in the interrupt controller. +//! +//! \param ui32Interrupt specifies the index in the vector table to disable. +//! - See \ref IntEnable() for list of valid arguments. +//! +//! \return None +//! +//! \sa \ref IntEnable() +// +//***************************************************************************** +extern void IntDisable(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Pends an interrupt. +//! +//! This function pends the specified interrupt in the interrupt controller. +//! This causes the interrupt controller to execute the corresponding interrupt +//! handler at the next available time, based on the current interrupt state +//! priorities. +//! +//! This interrupt controller automatically clears the pending interrupt once the +//! interrupt handler is executed. +//! +//! \param ui32Interrupt specifies the index in the vector table to pend. +//! - System exceptions: +//! - INT_NMI_FAULT +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_PKA_IRQ +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_SSI1_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! - INT_OSC_COMB +//! - INT_AUX_TIMER2_EV0 +//! - INT_UART1_COMB +//! - INT_BATMON_COMB +//! +//! \return None +//! +//! \sa \ref IntEnable() +// +//***************************************************************************** +extern void IntPendSet(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Checks if an interrupt is pending. +//! +//! This function checks the interrupt controller to see if an interrupt is pending. +//! +//! The interrupt must be enabled in order for the corresponding interrupt handler +//! to be executed, so an interrupt can be pending waiting to be enabled or waiting +//! for an interrupt of higher priority to be done executing. +//! +//! \note This function does not support reading pending status for system exceptions +//! (vector table indexes <16). +//! +//! \param ui32Interrupt specifies the index in the vector table to check pending +//! status for. +//! - See \ref IntPendSet() for list of valid arguments (except system exceptions). +//! +//! \return Returns: +//! - \c true : Specified interrupt is pending. +//! - \c false : Specified interrupt is not pending. +// +//***************************************************************************** +extern bool IntPendGet(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Unpends an interrupt. +//! +//! This function unpends the specified interrupt in the interrupt controller. +//! This causes any previously generated interrupts that have not been handled yet +//! (due to higher priority interrupts or the interrupt no having been enabled +//! yet) to be discarded. +//! +//! \note It is not possible to unpend the NMI because it takes effect +//! immediately when being pended. +//! +//! \param ui32Interrupt specifies the index in the vector table to unpend. +//! - See \ref IntPendSet() for list of valid arguments (except NMI). +//! +//! \return None +// +//***************************************************************************** +extern void IntPendClear(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Enables the CPU interrupt. +//! +//! Allows the CPU to respond to interrupts. +//! +//! \return Returns: +//! - \c true : Interrupts were disabled and are now enabled. +//! - \c false : Interrupts were already enabled when the function was called. +// +//***************************************************************************** +__STATIC_INLINE bool +IntMasterEnable(void) +{ + // Enable CPU interrupts. + return(CPUcpsie()); +} + +//***************************************************************************** +// +//! \brief Disables the CPU interrupts with configurable priority. +//! +//! Prevents the CPU from receiving interrupts except NMI and hard fault. This +//! does not affect the set of interrupts enabled in the interrupt controller; +//! it just gates the interrupt from the interrupt controller to the CPU. +//! +//! \return Returns: +//! - \c true : Interrupts were already disabled when the function was called. +//! - \c false : Interrupts were enabled and are now disabled. +// +//***************************************************************************** +__STATIC_INLINE bool +IntMasterDisable(void) +{ + // Disable CPU interrupts. + return(CPUcpsid()); +} + +//***************************************************************************** +// +//! \brief Sets the priority masking level. +//! +//! This function sets the interrupt priority masking level so that all +//! interrupts at the specified or lesser priority level are masked. This +//! can be used to globally disable a set of interrupts with priority below +//! a predetermined threshold. A value of 0 disables priority +//! masking. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 will allow interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! The device supports priority levels 0 through 7. +//! +//! \param ui32PriorityMask is the priority level that will be masked. +//! - 0 : Disable priority masking. +//! - 1 : Allow priority 0 interrupts, mask interrupts with priority 1-7. +//! - 2 : Allow priority 0-1 interrupts, mask interrupts with priority 2-7. +//! - 3 : Allow priority 0-2 interrupts, mask interrupts with priority 3-7. +//! - 4 : Allow priority 0-3 interrupts, mask interrupts with priority 4-7. +//! - 5 : Allow priority 0-4 interrupts, mask interrupts with priority 5-7. +//! - 6 : Allow priority 0-5 interrupts, mask interrupts with priority 6-7. +//! - 7 : Allow priority 0-6 interrupts, mask interrupts with priority 7. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +IntPriorityMaskSet(uint32_t ui32PriorityMask) +{ + CPUbasepriSet(ui32PriorityMask); +} + +//***************************************************************************** +// +//! \brief Gets the priority masking level. +//! +//! This function gets the current setting of the interrupt priority masking +//! level. The value returned is the priority level such that all interrupts +//! of that and lesser priority are masked. A value of 0 means that priority +//! masking is disabled. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 will allow interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! +//! \return Returns the value of the interrupt priority level mask. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +IntPriorityMaskGet(void) +{ + return(CPUbasepriGet()); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_IntRegister + #undef IntRegister + #define IntRegister ROM_IntRegister + #endif + #ifdef ROM_IntUnregister + #undef IntUnregister + #define IntUnregister ROM_IntUnregister + #endif + #ifdef ROM_IntPriorityGroupingSet + #undef IntPriorityGroupingSet + #define IntPriorityGroupingSet ROM_IntPriorityGroupingSet + #endif + #ifdef ROM_IntPriorityGroupingGet + #undef IntPriorityGroupingGet + #define IntPriorityGroupingGet ROM_IntPriorityGroupingGet + #endif + #ifdef ROM_IntPrioritySet + #undef IntPrioritySet + #define IntPrioritySet ROM_IntPrioritySet + #endif + #ifdef ROM_IntPriorityGet + #undef IntPriorityGet + #define IntPriorityGet ROM_IntPriorityGet + #endif + #ifdef ROM_IntEnable + #undef IntEnable + #define IntEnable ROM_IntEnable + #endif + #ifdef ROM_IntDisable + #undef IntDisable + #define IntDisable ROM_IntDisable + #endif + #ifdef ROM_IntPendSet + #undef IntPendSet + #define IntPendSet ROM_IntPendSet + #endif + #ifdef ROM_IntPendGet + #undef IntPendGet + #define IntPendGet ROM_IntPendGet + #endif + #ifdef ROM_IntPendClear + #undef IntPendClear + #define IntPendClear ROM_IntPendClear + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt_doc.h new file mode 100644 index 0000000..ff02174 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt_doc.h @@ -0,0 +1,162 @@ +/****************************************************************************** +* Filename: interrupt_doc.h +* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) +* Revision: 50272 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup interrupt_api +//! @{ +//! \section sec_interrupt Introduction +//! +//! The interrupt controller API provides a set of functions for dealing with the +//! Nested Vectored Interrupt Controller (NVIC). Functions are provided to enable +//! and disable interrupts, register interrupt handlers, and set the priority of +//! interrupts. +//! +//! The event sources that trigger the interrupt lines in the NVIC are controlled by +//! the MCU event fabric. All event sources are statically connected to the NVIC interrupt lines +//! except one which is programmable. For more information about the MCU event fabric, see the +//! [MCU event fabric API](\ref event_api). +//! +//! \section sec_interrupt_api API +//! +//! Interrupts and system exceptions must be individually enabled and disabled through: +//! - \ref IntEnable() +//! - \ref IntDisable() +//! +//! The global CPU interrupt can be enabled and disabled with the following functions: +//! - \ref IntMasterEnable() +//! - \ref IntMasterDisable() +//! +//! This does not affect the individual interrupt enable states. Masking of the CPU +//! interrupt can be used as a simple critical section (only an NMI can interrupt the +//! CPU while the CPU interrupt is disabled), although masking the CPU +//! interrupt can increase the interrupt response time. +//! +//! It is possible to access the NVIC to see if any interrupts are pending and manually +//! clear pending interrupts which have not yet been serviced or set a specific interrupt as +//! pending to be handled based on its priority. Pending interrupts are cleared automatically +//! when the interrupt is accepted and executed. However, the event source which caused the +//! interrupt might need to be cleared manually to avoid re-triggering the corresponding interrupt. +//! The functions to read, clear, and set pending interrupts are: +//! - \ref IntPendGet() +//! - \ref IntPendClear() +//! - \ref IntPendSet() +//! +//! The interrupt prioritization in the NVIC allows handling of higher priority interrupts +//! before lower priority interrupts, as well as allowing preemption of lower priority interrupt +//! handlers by higher priority interrupts. +//! The device supports eight priority levels from 0 to 7 with 0 being the highest priority. +//! The priority of each interrupt source can be set and examined using: +//! - \ref IntPrioritySet() +//! - \ref IntPriorityGet() +//! +//! Interrupts can be masked based on their priority such that interrupts with the same or lower +//! priority than the mask are effectively disabled. This can be configured with: +//! - \ref IntPriorityMaskSet() +//! - \ref IntPriorityMaskGet() +//! +//! Subprioritization is also possible. Instead of having three bits of preemptable +//! prioritization (eight levels), the NVIC can be configured for 3 - M bits of +//! preemptable prioritization and M bits of subpriority. In this scheme, two +//! interrupts with the same preemptable prioritization but different subpriorities +//! do not cause a preemption. Instead, tail chaining is used to process +//! the two interrupts back-to-back. +//! If two interrupts with the same priority (and subpriority if so configured) are +//! asserted at the same time, the one with the lower interrupt number is +//! processed first. +//! Subprioritization is handled by: +//! - \ref IntPriorityGroupingSet() +//! - \ref IntPriorityGroupingGet() +//! +//! \section sec_interrupt_table Interrupt Vector Table +//! +//! The interrupt vector table can be configured in one of two ways: +//! - Statically (at compile time): Vector table is placed in Flash and each entry has a fixed +//! pointer to an interrupt handler (ISR). +//! - Dynamically (at runtime): Vector table is placed in SRAM and each entry can be changed +//! (registered or unregistered) at runtime. This allows a single interrupt to trigger different +//! interrupt handlers (ISRs) depending on which interrupt handler is registered at the time the +//! System CPU responds to the interrupt. +//! +//! When configured, the interrupts must be explicitly enabled in the NVIC through \ref IntEnable() +//! before the CPU can respond to the interrupt (in addition to any interrupt enabling required +//! within the peripheral). +//! +//! \subsection sec_interrupt_table_static Static Vector Table +//! +//! Static registration of interrupt handlers is accomplished by editing the interrupt handler +//! table in the startup code of the application. Texas Instruments provides startup files for +//! each supported compiler ( \ti_code{startup_.c} ) and these startup files include +//! a default static interrupt vector table. +//! All entries, except ResetISR, are declared as \c extern with weak assignment to a default +//! interrupt handler. This allows the user to declare and define a function (in the user's code) +//! with the same name as an entry in the vector table. At compile time, the linker then replaces +//! the pointer to the default interrupt handler in the vector table with the pointer to the +//! interrupt handler defined by the user. +//! +//! Statically configuring the interrupt table provides the fastest interrupt response time +//! because the stacking operation (a write to SRAM on the data bus) is performed in parallel +//! with the interrupt handler table fetch (a read from Flash on the instruction bus), as well +//! as the prefetch of the interrupt handler (assuming it is also in Flash). +//! +//! \subsection sec_interrupt_table_dynamic Dynamic Vector Table +//! +//! Alternatively, interrupts can be registered in the vector table at runtime, thus dynamically. +//! The dynamic vector table is placed in SRAM and the code can then modify the pointers to +//! interrupt handlers throughout the application. +//! +//! DriverLib uses these two functions to modify the dynamic vector table: +//! - \ref IntRegister() : Write a pointer to an interrupt handler into the vector table. +//! - \ref IntUnregister() : Write pointer to default interrupt handler into the vector table. +//! +//! \note First call to \ref IntRegister() initializes the vector table in SRAM by copying the +//! static vector table from Flash and forcing the NVIC to use the dynamic vector table from +//! this point forward. If using the dynamic vector table it is highly recommended to +//! initialize it during the setup phase of the application. The NVIC uses the static vector +//! table in Flash until the application initializes the dynamic vector table in SRAM. +//! +//! Runtime configuration of interrupts adds a small latency to the interrupt response time +//! because the stacking operation (a write to SRAM on the data bus) and the interrupt handler +//! fetch from the vector table (a read from SRAM on the instruction bus) must be performed +//! sequentially. +//! +//! The dynamic vector table, \ref g_pfnRAMVectors, is placed in SRAM in the section called +//! \c vtable_ram which is a section defined in the linker file. By default the linker file +//! places this section at the start of the SRAM but this is configurable by the user. +//! +//! \warning Runtime configuration of interrupt handlers requires that the interrupt +//! handler table is placed on a 256-byte boundary in SRAM (typically, this is +//! at the beginning of SRAM). Failure to do so results in an incorrect vector +//! address being fetched in response to an interrupt. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.c new file mode 100644 index 0000000..92d9293 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.c @@ -0,0 +1,683 @@ +/****************************************************************************** +* Filename: ioc.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the IOC. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ioc.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef IOCPortConfigureSet + #define IOCPortConfigureSet NOROM_IOCPortConfigureSet + #undef IOCPortConfigureGet + #define IOCPortConfigureGet NOROM_IOCPortConfigureGet + #undef IOCIOShutdownSet + #define IOCIOShutdownSet NOROM_IOCIOShutdownSet + #undef IOCIOModeSet + #define IOCIOModeSet NOROM_IOCIOModeSet + #undef IOCIOIntSet + #define IOCIOIntSet NOROM_IOCIOIntSet + #undef IOCIOEvtSet + #define IOCIOEvtSet NOROM_IOCIOEvtSet + #undef IOCIOPortPullSet + #define IOCIOPortPullSet NOROM_IOCIOPortPullSet + #undef IOCIOHystSet + #define IOCIOHystSet NOROM_IOCIOHystSet + #undef IOCIOInputSet + #define IOCIOInputSet NOROM_IOCIOInputSet + #undef IOCIOSlewCtrlSet + #define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet + #undef IOCIODrvStrengthSet + #define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet + #undef IOCIOPortIdSet + #define IOCIOPortIdSet NOROM_IOCIOPortIdSet + #undef IOCIntEnable + #define IOCIntEnable NOROM_IOCIntEnable + #undef IOCIntDisable + #define IOCIntDisable NOROM_IOCIntDisable + #undef IOCPinTypeGpioInput + #define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput + #undef IOCPinTypeGpioOutput + #define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput + #undef IOCPinTypeUart + #define IOCPinTypeUart NOROM_IOCPinTypeUart + #undef IOCPinTypeSsiMaster + #define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster + #undef IOCPinTypeSsiSlave + #define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave + #undef IOCPinTypeI2c + #define IOCPinTypeI2c NOROM_IOCPinTypeI2c + #undef IOCPinTypeAux + #define IOCPinTypeAux NOROM_IOCPinTypeAux +#endif + +//***************************************************************************** +// +// Set the configuration of an IO port +// +//***************************************************************************** +void +IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, + uint32_t ui32IOConfig) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the port. + HWREG(ui32Reg) = ui32IOConfig | ui32PortId; +} + +//***************************************************************************** +// +// Get the configuration of an IO port +// +//***************************************************************************** +uint32_t +IOCPortConfigureGet(uint32_t ui32IOId) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Return the IO configuration. + return HWREG(ui32Reg); +} + +//***************************************************************************** +// +// Set wake-up on an IO port +// +//***************************************************************************** +void +IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) || + (ui32IOShutdown == IOC_WAKE_ON_LOW) || + (ui32IOShutdown == IOC_WAKE_ON_HIGH)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_WU_CFG_M; + HWREG(ui32Reg) = ui32Config | ui32IOShutdown; +} + + +//***************************************************************************** +// +// Set the IO Mode of an IO Port +// +//***************************************************************************** +void +IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) || + (ui32IOMode == IOC_IOMODE_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_INV)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_IOMODE_M; + HWREG(ui32Reg) = ui32Config | ui32IOMode; +} + +//***************************************************************************** +// +// Setup interrupt detection on an IO Port +// +//***************************************************************************** +void +IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Int == IOC_INT_ENABLE) || + (ui32Int == IOC_INT_DISABLE)); + ASSERT((ui32EdgeDet == IOC_NO_EDGE) || + (ui32EdgeDet == IOC_FALLING_EDGE) || + (ui32EdgeDet == IOC_RISING_EDGE) || + (ui32EdgeDet == IOC_BOTH_EDGES)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_EDGE_IRQ_EN | IOC_IOCFG0_EDGE_DET_M); + HWREG(ui32IOReg) = ui32Config | ((ui32Int ? IOC_IOCFG0_EDGE_IRQ_EN : 0) | ui32EdgeDet); +} + +//***************************************************************************** +// +// Setup event generation on IO edge detection +// +//***************************************************************************** +void +IOCIOEvtSet(uint32_t ui32IOId, uint32_t ui32Evt) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT( (ui32Evt & ~(IOC_IOCFG0_IOEV_AON_PROG2_EN_M | + IOC_IOCFG0_IOEV_AON_PROG1_EN_M | + IOC_IOCFG0_IOEV_AON_PROG0_EN_M | + IOC_IOCFG0_IOEV_RTC_EN_M | + IOC_IOCFG0_IOEV_MCU_WU_EN_M) ) == 0x00000000); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Read current configuration. + ui32Config = HWREG(ui32IOReg); + + // Disable generation of all events. + ui32Config &= ~(IOC_IOCFG0_IOEV_AON_PROG2_EN_M | + IOC_IOCFG0_IOEV_AON_PROG1_EN_M | + IOC_IOCFG0_IOEV_AON_PROG0_EN_M | + IOC_IOCFG0_IOEV_RTC_EN_M | + IOC_IOCFG0_IOEV_MCU_WU_EN_M); + + // Enable the required events. + HWREG(ui32IOReg) = ui32Config | ui32Evt; +} + +//***************************************************************************** +// +// Set the pull on an IO port +// +//***************************************************************************** +void +IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the argument. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Pull == IOC_NO_IOPULL) || + (ui32Pull == IOC_IOPULL_UP) || + (ui32Pull == IOC_IOPULL_DOWN)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PULL_CTL_M; + HWREG(ui32IOReg) = ui32Config | ui32Pull; +} + +//***************************************************************************** +// +// Configure hysteresis on and IO port +// +//***************************************************************************** +void +IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Hysteresis == IOC_HYST_ENABLE) || + (ui32Hysteresis == IOC_HYST_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_HYST_EN; + HWREG(ui32IOReg) = ui32Config | ui32Hysteresis; +} + +//***************************************************************************** +// +// Enable/disable IO port as input +// +//***************************************************************************** +void +IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Input == IOC_INPUT_ENABLE) || + (ui32Input == IOC_INPUT_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_IE; + HWREG(ui32IOReg) = ui32Config | ui32Input; +} + +//***************************************************************************** +// +// Enable/disable the slew control on an IO port +// +//***************************************************************************** +void +IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32SlewEnable == IOC_SLEW_ENABLE) || + (ui32SlewEnable == IOC_SLEW_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_SLEW_RED; + HWREG(ui32IOReg) = ui32Config | ui32SlewEnable; +} + +//***************************************************************************** +// +// Configure the drive strength and maximum current of an IO port +// +//***************************************************************************** +void +IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, + uint32_t ui32DrvStrength) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOCurrent == IOC_CURRENT_2MA) || + (ui32IOCurrent == IOC_CURRENT_4MA) || + (ui32IOCurrent == IOC_CURRENT_8MA)); + ASSERT((ui32DrvStrength == IOC_STRENGTH_MIN) || + (ui32DrvStrength == IOC_STRENGTH_MAX) || + (ui32DrvStrength == IOC_STRENGTH_MED) || + (ui32DrvStrength == IOC_STRENGTH_AUTO)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_IOCURR_M | IOC_IOCFG0_IOSTR_M); + HWREG(ui32IOReg) = ui32Config | (ui32IOCurrent | ui32DrvStrength); +} + +//***************************************************************************** +// +// Setup the Port ID for this IO +// +//***************************************************************************** +void +IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PORT_ID_M; + HWREG(ui32IOReg) = ui32Config | ui32PortId; +} + +//***************************************************************************** +// +// Enables individual IO edge detect interrupt +// +//***************************************************************************** +void +IOCIntEnable(uint32_t ui32IOId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Enable the specified interrupt. + ui32Config = HWREG(ui32IOReg); + ui32Config |= IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} + +//***************************************************************************** +// +// Disables individual IO edge interrupt sources +// +//***************************************************************************** +void +IOCIntDisable(uint32_t ui32IOId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Disable the specified interrupt. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} + +//***************************************************************************** +// +// Setup an IO for standard GPIO input +// +//***************************************************************************** +void +IOCPinTypeGpioInput(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Setup the IO for standard input. + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_INPUT); + + // Enable input mode in the GPIO module. + GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_DISABLE); +} + +//***************************************************************************** +// +// Setup an IO for standard GPIO output +// +//***************************************************************************** +void +IOCPinTypeGpioOutput(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Setup the IO for standard input. + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_OUTPUT); + + // Enable output mode in the GPIO module. + GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_ENABLE); +} + +//***************************************************************************** +// +// Configure a set of IOs for standard UART peripheral control +// +//***************************************************************************** +void +IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, + uint32_t ui32Cts, uint32_t ui32Rts) +{ + // Check the arguments. + ASSERT(ui32Base == UART0_BASE); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Cts <= IOID_31) || (ui32Cts == IOID_UNUSED)); + ASSERT((ui32Rts <= IOID_31) || (ui32Rts == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_UART0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_UART0_TX, IOC_STD_OUTPUT); + } + if(ui32Cts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Cts, IOC_PORT_MCU_UART0_CTS, IOC_STD_INPUT); + } + if(ui32Rts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rts, IOC_PORT_MCU_UART0_RTS, IOC_STD_OUTPUT); + } +} + +//***************************************************************************** +// +// Configure a set of IOs for standard SSI peripheral master control +// +//***************************************************************************** +void +IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // Check the arguments. + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_OUTPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_OUTPUT); + } + } +} + +//***************************************************************************** +// +// Configure a set of IOs for standard SSI peripheral slave control +// +//***************************************************************************** +void +IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // Check the arguments. + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_INPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_INPUT); + } + } +} + +//***************************************************************************** +// +// Configure a set of IOs for standard I2C peripheral control +// +//***************************************************************************** +void +IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk) +{ + uint32_t ui32IOConfig; + + // Check the arguments. + ASSERT((ui32Data <= IOID_31) || (ui32Data == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Define the IO configuration parameters. + ui32IOConfig = IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_IOPULL_UP | + IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | + IOC_INT_DISABLE | IOC_IOMODE_OPEN_DRAIN_NORMAL | + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE; + + // Setup the IOs in the desired configuration. + IOCPortConfigureSet(ui32Data, IOC_PORT_MCU_I2C_MSSDA, ui32IOConfig); + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_I2C_MSSCL, ui32IOConfig); +} + + +//***************************************************************************** +// +// Configure an IO for AUX control +// +//***************************************************************************** +void +IOCPinTypeAux(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT((ui32IOId <= IOID_31) || (ui32IOId == IOID_UNUSED)); + + // Setup the IO. + IOCPortConfigureSet(ui32IOId, IOC_PORT_AUX_IO, IOC_STD_INPUT); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h new file mode 100644 index 0000000..98346e2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h @@ -0,0 +1,1225 @@ +/****************************************************************************** +* Filename: ioc.h +* Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) +* Revision: 50156 +* +* Description: Defines and prototypes for the IO Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup ioc_api +//! @{ +// +//***************************************************************************** + +#ifndef __IOC_H__ +#define __IOC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ioc.h" +#include "../inc/hw_ints.h" +#include "interrupt.h" +#include "debug.h" +#include "gpio.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define IOCPortConfigureSet NOROM_IOCPortConfigureSet + #define IOCPortConfigureGet NOROM_IOCPortConfigureGet + #define IOCIOShutdownSet NOROM_IOCIOShutdownSet + #define IOCIOModeSet NOROM_IOCIOModeSet + #define IOCIOIntSet NOROM_IOCIOIntSet + #define IOCIOEvtSet NOROM_IOCIOEvtSet + #define IOCIOPortPullSet NOROM_IOCIOPortPullSet + #define IOCIOHystSet NOROM_IOCIOHystSet + #define IOCIOInputSet NOROM_IOCIOInputSet + #define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet + #define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet + #define IOCIOPortIdSet NOROM_IOCIOPortIdSet + #define IOCIntEnable NOROM_IOCIntEnable + #define IOCIntDisable NOROM_IOCIntDisable + #define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput + #define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput + #define IOCPinTypeUart NOROM_IOCPinTypeUart + #define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster + #define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave + #define IOCPinTypeI2c NOROM_IOCPinTypeI2c + #define IOCPinTypeAux NOROM_IOCPinTypeAux +#endif + +//***************************************************************************** +// +// Number of IOs (max. total of 32) +// +//***************************************************************************** +#define NUM_IO_MAX 32 + +//***************************************************************************** +// +// The following fields are IO Id for the IOC module +// +//***************************************************************************** +#define IOID_0 0x00000000 // IO Id 0 +#define IOID_1 0x00000001 // IO Id 1 +#define IOID_2 0x00000002 // IO Id 2 +#define IOID_3 0x00000003 // IO Id 3 +#define IOID_4 0x00000004 // IO Id 4 +#define IOID_5 0x00000005 // IO Id 5 +#define IOID_6 0x00000006 // IO Id 6 +#define IOID_7 0x00000007 // IO Id 7 +#define IOID_8 0x00000008 // IO Id 8 +#define IOID_9 0x00000009 // IO Id 9 +#define IOID_10 0x0000000A // IO Id 10 +#define IOID_11 0x0000000B // IO Id 11 +#define IOID_12 0x0000000C // IO Id 12 +#define IOID_13 0x0000000D // IO Id 13 +#define IOID_14 0x0000000E // IO Id 14 +#define IOID_15 0x0000000F // IO Id 15 +#define IOID_16 0x00000010 // IO Id 16 +#define IOID_17 0x00000011 // IO Id 17 +#define IOID_18 0x00000012 // IO Id 18 +#define IOID_19 0x00000013 // IO Id 19 +#define IOID_20 0x00000014 // IO Id 20 +#define IOID_21 0x00000015 // IO Id 21 +#define IOID_22 0x00000016 // IO Id 22 +#define IOID_23 0x00000017 // IO Id 23 +#define IOID_24 0x00000018 // IO Id 24 +#define IOID_25 0x00000019 // IO Id 25 +#define IOID_26 0x0000001A // IO Id 26 +#define IOID_27 0x0000001B // IO Id 27 +#define IOID_28 0x0000001C // IO Id 28 +#define IOID_29 0x0000001D // IO Id 29 +#define IOID_30 0x0000001E // IO Id 30 +#define IOID_31 0x0000001F // IO Id 31 +#define IOID_UNUSED 0xFFFFFFFF // Unused IO Id + +#define IOC_IOID_MASK 0x000000FF // IOC IO Id bit mask + +//***************************************************************************** +// +// Number of IO ports +// +//***************************************************************************** +#define NUM_IO_PORTS 56 + +//***************************************************************************** +// +// IOC Peripheral Port Mapping +// +//***************************************************************************** +#define IOC_PORT_GPIO 0x00000000 // Default general purpose IO usage +#define IOC_PORT_AON_CLK32K 0x00000007 // AON External 32kHz clock +#define IOC_PORT_AUX_IO 0x00000008 // AUX IO Pin +#define IOC_PORT_MCU_SSI0_RX 0x00000009 // MCU SSI0 Receive Pin +#define IOC_PORT_MCU_SSI0_TX 0x0000000A // MCU SSI0 Transmit Pin +#define IOC_PORT_MCU_SSI0_FSS 0x0000000B // MCU SSI0 FSS Pin +#define IOC_PORT_MCU_SSI0_CLK 0x0000000C // MCU SSI0 Clock Pin +#define IOC_PORT_MCU_I2C_MSSDA 0x0000000D // MCU I2C Data Pin +#define IOC_PORT_MCU_I2C_MSSCL 0x0000000E // MCU I2C Clock Pin +#define IOC_PORT_MCU_UART0_RX 0x0000000F // MCU UART0 Receive Pin +#define IOC_PORT_MCU_UART0_TX 0x00000010 // MCU UART0 Transmit Pin +#define IOC_PORT_MCU_UART0_CTS 0x00000011 // MCU UART0 Clear To Send Pin +#define IOC_PORT_MCU_UART0_RTS 0x00000012 // MCU UART0 Request To Send Pin +#define IOC_PORT_MCU_UART1_RX 0x00000013 // MCU UART1 Receive Pin +#define IOC_PORT_MCU_UART1_TX 0x00000014 // MCU UART1 Transmit Pin +#define IOC_PORT_MCU_UART1_CTS 0x00000015 // MCU UART1 Clear To Send Pin +#define IOC_PORT_MCU_UART1_RTS 0x00000016 // MCU UART1 Request To Send Pin +#define IOC_PORT_MCU_PORT_EVENT0 0x00000017 // MCU PORT EVENT 0 +#define IOC_PORT_MCU_PORT_EVENT1 0x00000018 // MCU PORT EVENT 1 +#define IOC_PORT_MCU_PORT_EVENT2 0x00000019 // MCU PORT EVENT 2 +#define IOC_PORT_MCU_PORT_EVENT3 0x0000001A // MCU PORT EVENT 3 +#define IOC_PORT_MCU_PORT_EVENT4 0x0000001B // MCU PORT EVENT 4 +#define IOC_PORT_MCU_PORT_EVENT5 0x0000001C // MCU PORT EVENT 5 +#define IOC_PORT_MCU_PORT_EVENT6 0x0000001D // MCU PORT EVENT 6 +#define IOC_PORT_MCU_PORT_EVENT7 0x0000001E // MCU PORT EVENT 7 +#define IOC_PORT_MCU_SWV 0x00000020 // Serial Wire Viewer +#define IOC_PORT_MCU_SSI1_RX 0x00000021 // MCU SSI1 Receive Pin +#define IOC_PORT_MCU_SSI1_TX 0x00000022 // MCU SSI1 Transmit Pin +#define IOC_PORT_MCU_SSI1_FSS 0x00000023 // MCU SSI1 FSS Pin +#define IOC_PORT_MCU_SSI1_CLK 0x00000024 // MCU SSI1 Clock Pin +#define IOC_PORT_MCU_I2S_AD0 0x00000025 // MCU I2S Data Pin 0 +#define IOC_PORT_MCU_I2S_AD1 0x00000026 // MCU I2S Data Pin 1 +#define IOC_PORT_MCU_I2S_WCLK 0x00000027 // MCU I2S Frame/Word Clock +#define IOC_PORT_MCU_I2S_BCLK 0x00000028 // MCU I2S Bit Clock +#define IOC_PORT_MCU_I2S_MCLK 0x00000029 // MCU I2S Master clock 2 +#define IOC_PORT_RFC_TRC 0x0000002E // RF Core Tracer +#define IOC_PORT_RFC_GPO0 0x0000002F // RC Core Data Out Pin 0 +#define IOC_PORT_RFC_GPO1 0x00000030 // RC Core Data Out Pin 1 +#define IOC_PORT_RFC_GPO2 0x00000031 // RC Core Data Out Pin 2 +#define IOC_PORT_RFC_GPO3 0x00000032 // RC Core Data Out Pin 3 +#define IOC_PORT_RFC_GPI0 0x00000033 // RC Core Data In Pin 0 +#define IOC_PORT_RFC_GPI1 0x00000034 // RC Core Data In Pin 1 +#define IOC_PORT_RFC_SMI_DL_OUT 0x00000035 // RF Core SMI Data Link Out +#define IOC_PORT_RFC_SMI_DL_IN 0x00000036 // RF Core SMI Data Link in +#define IOC_PORT_RFC_SMI_CL_OUT 0x00000037 // RF Core SMI Command Link Out +#define IOC_PORT_RFC_SMI_CL_IN 0x00000038 // RF Core SMI Command Link In + +//***************************************************************************** +// +// Defines for enabling/disabling an IO +// +//***************************************************************************** +#define IOC_SLEW_ENABLE 0x00001000 +#define IOC_SLEW_DISABLE 0x00000000 +#define IOC_INPUT_ENABLE 0x20000000 +#define IOC_INPUT_DISABLE 0x00000000 +#define IOC_HYST_ENABLE 0x40000000 +#define IOC_HYST_DISABLE 0x00000000 + +//***************************************************************************** +// +// Defines that can be used to set the shutdown mode of an IO +// +//***************************************************************************** +#define IOC_NO_WAKE_UP 0x00000000 +#define IOC_WAKE_ON_LOW 0x10000000 +#define IOC_WAKE_ON_HIGH 0x18000000 + +//***************************************************************************** +// +// Defines that can be used to set the IO Mode of an IO +// +//***************************************************************************** +#define IOC_IOMODE_NORMAL 0x00000000 // Normal Input/Output +#define IOC_IOMODE_INV 0x01000000 // Inverted Input/Output +#define IOC_IOMODE_OPEN_DRAIN_NORMAL \ + 0x04000000 // Open Drain, Normal Input/Output +#define IOC_IOMODE_OPEN_DRAIN_INV \ + 0x05000000 // Open Drain, Inverted + // Input/Output +#define IOC_IOMODE_OPEN_SRC_NORMAL \ + 0x06000000 // Open Source, Normal Input/Output +#define IOC_IOMODE_OPEN_SRC_INV \ + 0x07000000 // Open Source, Inverted + // Input/Output + +//***************************************************************************** +// +// Defines that can be used to set the edge detection on an IO +// +//***************************************************************************** +#define IOC_NO_EDGE 0x00000000 // No edge detection +#define IOC_FALLING_EDGE 0x00010000 // Edge detection on falling edge +#define IOC_RISING_EDGE 0x00020000 // Edge detection on rising edge +#define IOC_BOTH_EDGES 0x00030000 // Edge detection on both edges +#define IOC_INT_ENABLE 0x00040000 // Enable interrupt on edge detect +#define IOC_INT_DISABLE 0x00000000 // Disable interrupt on edge detect +#define IOC_INT_M 0x00070000 // Int config mask + +//***************************************************************************** +// +// Defines that be used to set pull on an IO +// +//***************************************************************************** +#define IOC_NO_IOPULL 0x00006000 // No IO pull +#define IOC_IOPULL_UP 0x00004000 // Pull up +#define IOC_IOPULL_DOWN 0x00002000 // Pull down +#define IOC_IOPULL_M 0x00006000 // Pull config mask +#define IOC_IOPULL_M 0x00006000 + +//***************************************************************************** +// +// Defines that can be used to select the drive strength of an IO +// +//***************************************************************************** +#define IOC_CURRENT_2MA 0x00000000 // 2mA drive strength +#define IOC_CURRENT_4MA 0x00000400 // 4mA drive strength +#define IOC_CURRENT_8MA 0x00000800 // 4 or 8mA drive strength + +#define IOC_STRENGTH_AUTO 0x00000000 // Automatic Drive Strength + // (2/4/8 mA @ VVDS) +#define IOC_STRENGTH_MAX 0x00000300 // Maximum Drive Strength + // (2/4/8 mA @ 1.8V) +#define IOC_STRENGTH_MED 0x00000200 // Medium Drive Strength + // (2/4/8 mA @ 2.5V) +#define IOC_STRENGTH_MIN 0x00000100 // Minimum Drive Strength + // (2/4/8 mA @ 3.3V) + +//***************************************************************************** +// +// Defines that can be used to enable event generation on edge detect +// +//***************************************************************************** +#define IOC_EVT_AON_PROG2_DISABLE 0x00000000 +#define IOC_EVT_AON_PROG2_ENABLE 0x00800000 +#define IOC_EVT_AON_PROG1_DISABLE 0x00000000 +#define IOC_EVT_AON_PROG1_ENABLE 0x00400000 +#define IOC_EVT_AON_PROG0_DISABLE 0x00000000 +#define IOC_EVT_AON_PROG0_ENABLE 0x00200000 +#define IOC_EVT_RTC_DISABLE 0x00000000 +#define IOC_EVT_RTC_ENABLE 0x00000080 +#define IOC_EVT_MCU_WU_DISABLE 0x00000000 +#define IOC_EVT_MCU_WU_ENABLE 0x00000040 + +//***************************************************************************** +// +// Defines for standard IO setup +// +//***************************************************************************** +#define IOC_STD_INPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE ) +#define IOC_STD_OUTPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_DISABLE ) + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Set the configuration of an IO port. +//! +//! This function is used to configure the functionality of an IO. +//! +//! The \c ui32IOId parameter specifies which IO to configure. +//! +//! The \c ui32PortId parameter specifies which functional peripheral to hook +//! up to this IO. +//! +//! The \c ui32IOConfig parameter consists of a bitwise OR'ed value of all +//! the available configuration modes +//! +//! \note All IO Ports are tied to a specific functionality in a sub module +//! except for the \ref IOC_PORT_AUX_IO. Each of the IOs in the AUX domain are +//! hardcoded to a specific IO. When enabling one or more pins for the AUX +//! domain, they should all be configured to using \ref IOC_PORT_AUX_IO. +//! +//! \param ui32IOId defines the IO to configure and must be one of the following: +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32PortId selects the functional IO port to connect. +//! The available IO ports are: +//! - \ref IOC_PORT_GPIO +//! - \ref IOC_PORT_AON_CLK32K +//! - \ref IOC_PORT_AUX_IO +//! - \ref IOC_PORT_MCU_SSI0_RX +//! - \ref IOC_PORT_MCU_SSI0_TX +//! - \ref IOC_PORT_MCU_SSI0_FSS +//! - \ref IOC_PORT_MCU_SSI0_CLK +//! - \ref IOC_PORT_MCU_I2C_MSSDA +//! - \ref IOC_PORT_MCU_I2C_MSSCL +//! - \ref IOC_PORT_MCU_UART0_RX +//! - \ref IOC_PORT_MCU_UART0_TX +//! - \ref IOC_PORT_MCU_UART0_CTS +//! - \ref IOC_PORT_MCU_UART0_RTS +//! - \ref IOC_PORT_MCU_UART1_RX +//! - \ref IOC_PORT_MCU_UART1_TX +//! - \ref IOC_PORT_MCU_UART1_CTS +//! - \ref IOC_PORT_MCU_UART1_RTS +//! - \ref IOC_PORT_MCU_PORT_EVENT0 +//! - \ref IOC_PORT_MCU_PORT_EVENT1 +//! - \ref IOC_PORT_MCU_PORT_EVENT2 +//! - \ref IOC_PORT_MCU_PORT_EVENT3 +//! - \ref IOC_PORT_MCU_PORT_EVENT4 +//! - \ref IOC_PORT_MCU_PORT_EVENT5 +//! - \ref IOC_PORT_MCU_PORT_EVENT6 +//! - \ref IOC_PORT_MCU_PORT_EVENT7 +//! - \ref IOC_PORT_MCU_SWV +//! - \ref IOC_PORT_MCU_SSI1_RX +//! - \ref IOC_PORT_MCU_SSI1_TX +//! - \ref IOC_PORT_MCU_SSI1_FSS +//! - \ref IOC_PORT_MCU_SSI1_CLK +//! - \ref IOC_PORT_MCU_I2S_AD0 +//! - \ref IOC_PORT_MCU_I2S_AD1 +//! - \ref IOC_PORT_MCU_I2S_WCLK +//! - \ref IOC_PORT_MCU_I2S_BCLK +//! - \ref IOC_PORT_MCU_I2S_MCLK +//! - \ref IOC_PORT_RFC_TRC +//! - \ref IOC_PORT_RFC_GPO0 +//! - \ref IOC_PORT_RFC_GPO1 +//! - \ref IOC_PORT_RFC_GPO2 +//! - \ref IOC_PORT_RFC_GPO3 +//! - \ref IOC_PORT_RFC_GPI0 +//! - \ref IOC_PORT_RFC_GPI1 +//! \param ui32IOConfig is the IO configuration consisting of +//! the bitwise OR of all configuration modes: +//! - Input/output mode: +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_IOMODE_INV +//! - \ref IOC_IOMODE_OPEN_DRAIN_NORMAL +//! - \ref IOC_IOMODE_OPEN_DRAIN_INV +//! - \ref IOC_IOMODE_OPEN_SRC_NORMAL +//! - \ref IOC_IOMODE_OPEN_SRC_INV +//! - Wake-up mode (from shutdown): +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_WAKE_ON_LOW +//! - \ref IOC_WAKE_ON_HIGH +//! - Edge detection mode: +//! - \ref IOC_NO_EDGE +//! - \ref IOC_FALLING_EDGE +//! - \ref IOC_RISING_EDGE +//! - \ref IOC_BOTH_EDGES +//! - Interrupt mode on edge detection: +//! - \ref IOC_INT_ENABLE +//! - \ref IOC_INT_DISABLE +//! - Pull mode: +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_IOPULL_UP +//! - \ref IOC_IOPULL_DOWN +//! - Input mode: +//! - \ref IOC_INPUT_ENABLE +//! - \ref IOC_INPUT_DISABLE +//! - Hysteresis mode: +//! - \ref IOC_HYST_ENABLE +//! - \ref IOC_HYST_DISABLE +//! - Slew rate reduction mode: +//! - \ref IOC_SLEW_ENABLE +//! - \ref IOC_SLEW_DISABLE +//! - Current mode (see \ref IOCIODrvStrengthSet() for more details): +//! - \ref IOC_CURRENT_2MA : Low-Current mode. Min 2 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_4MA : High-Current mode. Min 4 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_8MA : Extended-Current mode. Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - Drive strength mode: +//! - \ref IOC_STRENGTH_AUTO : Automatic drive strength based on battery voltage. +//! - \ref IOC_STRENGTH_MAX : Maximum drive strength, used for low supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MED : Medium drive strength, used for medium supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MIN : Minimum drive strength, used for high supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - Assert AON_PROG2 event on edge detection: +//! - \ref IOC_EVT_AON_PROG2_DISABLE +//! - \ref IOC_EVT_AON_PROG2_ENABLE +//! - Assert AON_PROG1 event on edge detection: +//! - \ref IOC_EVT_AON_PROG1_DISABLE +//! - \ref IOC_EVT_AON_PROG1_ENABLE +//! - Assert AON_PROG0 event on edge detection: +//! - \ref IOC_EVT_AON_PROG0_DISABLE +//! - \ref IOC_EVT_AON_PROG0_ENABLE +//! - Assert RTC event on edge detection: +//! - \ref IOC_EVT_RTC_DISABLE +//! - \ref IOC_EVT_RTC_ENABLE +//! - Assert MCU_WU event on edge detection: +//! - \ref IOC_EVT_MCU_WU_DISABLE +//! - \ref IOC_EVT_MCU_WU_ENABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, + uint32_t ui32IOConfig); + +//***************************************************************************** +// +//! \brief Get the configuration of an IO port. +//! +//! This function is used for getting the configuration of an IO. +//! +//! Each IO port has a dedicated register for setting up the IO. This function +//! returns the current configuration for the given IO. +//! +//! \param ui32IOId selects the IO to return the configuration for. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return Returns the IO Port configuration. +//! See \ref IOCPortConfigureSet() for configuration options. +// +//***************************************************************************** +extern uint32_t IOCPortConfigureGet(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Set wake-up mode from shutdown on an IO port. +//! +//! This function is used to set the wake-up mode from shutdown of an IO. +//! +//! IO must be configured as input in order for wakeup to work. See \ref IOCIOInputSet(). +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32IOShutdown enables wake-up from shutdown on LOW/HIGH by this IO port. +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_WAKE_ON_LOW +//! - \ref IOC_WAKE_ON_HIGH +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown); + + +//***************************************************************************** +// +//! \brief Set the IO Mode of an IO Port. +//! +//! This function is used to set the input/output mode of an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32IOMode sets the port IO Mode. +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_IOMODE_INV +//! - \ref IOC_IOMODE_OPEN_DRAIN_NORMAL +//! - \ref IOC_IOMODE_OPEN_DRAIN_INV +//! - \ref IOC_IOMODE_OPEN_SRC_NORMAL +//! - \ref IOC_IOMODE_OPEN_SRC_INV +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode); + +//***************************************************************************** +// +//! \brief Setup edge detection and interrupt generation on an IO Port. +//! +//! This function is used to setup the edge detection and interrupt generation on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Int enables/disables interrupt generation on this IO port. +//! - \ref IOC_INT_ENABLE +//! - \ref IOC_INT_DISABLE +//! \param ui32EdgeDet enables/disables edge detection events on this IO port. +//! - \ref IOC_NO_EDGE +//! - \ref IOC_FALLING_EDGE +//! - \ref IOC_RISING_EDGE +//! - \ref IOC_BOTH_EDGES +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, + uint32_t ui32EdgeDet); + +//***************************************************************************** +// +//! \brief Setup event generation on IO edge detection. +//! +//! This function is used to setup event generation for specific events +//! when an IO edge detection occurs. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Evt is a bitwise OR of the IO events to generate when an IO edge detection occurs. +//! All other IO event generations are disabled. +//! - \ref IOC_EVT_AON_PROG2_ENABLE : AON_PROG2 event. +//! - \ref IOC_EVT_AON_PROG1_ENABLE : AON_PROG1 event. +//! - \ref IOC_EVT_AON_PROG0_ENABLE : AON_PROG0 event. +//! - \ref IOC_EVT_RTC_ENABLE : RTC event. +//! - \ref IOC_EVT_MCU_WU_ENABLE : MCU_WU event. +//! +// +//***************************************************************************** +extern void IOCIOEvtSet(uint32_t ui32IOId, uint32_t ui32Evt); + +//***************************************************************************** +// +//! \brief Set the pull on an IO port. +//! +//! This function is used to configure the pull on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Pull enables/disables pull on this IO port. +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_IOPULL_UP +//! - \ref IOC_IOPULL_DOWN +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull); + +//***************************************************************************** +// +//! \brief Configure hysteresis on and IO port. +//! +//! This function is used to enable/disable hysteresis on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Hysteresis enable/disable input hysteresis on IO. +//! - \ref IOC_HYST_ENABLE +//! - \ref IOC_HYST_DISABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis); + +//***************************************************************************** +// +//! \brief Enable/disable IO port as input. +//! +//! This function is used to enable/disable input on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Input enable/disable input on IO. +//! - \ref IOC_INPUT_ENABLE +//! - \ref IOC_INPUT_DISABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input); + +//***************************************************************************** +// +//! \brief Configure slew rate on an IO port. +//! +//! This function is used to enable/disable reduced slew rate on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32SlewEnable enables/disables reduced slew rate on an output. +//! - \ref IOC_SLEW_ENABLE +//! - \ref IOC_SLEW_DISABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable); + +//***************************************************************************** +// +//! \brief Configure the drive strength source and current mode of an IO port. +//! +//! The drive strength of an IO is configured by a combination of multiple settings +//! in several modules. The drive strength source \ti_code{ui32DrvStrength} is used for controlling +//! drive strength at different supply levels. When set to AUTO the battery monitor +//! (BATMON) adjusts the drive strength to compensate for changes in supply voltage +//! in order to keep IO current constant. Alternatively, drive strength source can +//! be controlled manually by selecting one of three options each of which is configurable +//! in the AON IOC by \ref AONIOCDriveStrengthSet(). +//! +//! Each drive strength source has three current modes: Low-Current (LC), High-Current (HC), and +//! Extended-Current (EC), and typically drive strength doubles when selecting a higher mode. +//! I.e. EC = 2 x HC = 4 x LC. +//! +//! \note Not all IOs support Extended-Current mode. See datasheet for more information +//! on the specific device. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32IOCurrent selects the IO current mode. +//! - \ref IOC_CURRENT_2MA : Low-Current mode. Min 2 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_4MA : High-Current mode. Min 4 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_8MA : Extended-Current mode. Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! \param ui32DrvStrength sets the source for drive strength control of the IO port. +//! - \ref IOC_STRENGTH_AUTO : Automatic drive strength based on battery voltage. +//! - \ref IOC_STRENGTH_MAX : Maximum drive strength, used for low supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MED : Medium drive strength, used for medium supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MIN : Minimum drive strength, used for high supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! +//! \return None +// +//***************************************************************************** +extern void IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, + uint32_t ui32DrvStrength); + +//***************************************************************************** +// +//! \brief Setup the Port ID for this IO. +//! +//! The \c ui32PortId specifies which functional peripheral to hook up to this +//! IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32PortId selects the port to map to the IO. +//! - \ref IOC_PORT_GPIO +//! - \ref IOC_PORT_AON_CLK32K +//! - \ref IOC_PORT_AUX_IO +//! - \ref IOC_PORT_MCU_SSI0_RX +//! - \ref IOC_PORT_MCU_SSI0_TX +//! - \ref IOC_PORT_MCU_SSI0_FSS +//! - \ref IOC_PORT_MCU_SSI0_CLK +//! - \ref IOC_PORT_MCU_I2C_MSSDA +//! - \ref IOC_PORT_MCU_I2C_MSSCL +//! - \ref IOC_PORT_MCU_UART0_RX +//! - \ref IOC_PORT_MCU_UART0_TX +//! - \ref IOC_PORT_MCU_UART0_CTS +//! - \ref IOC_PORT_MCU_UART0_RTS +//! - \ref IOC_PORT_MCU_UART1_RX +//! - \ref IOC_PORT_MCU_UART1_TX +//! - \ref IOC_PORT_MCU_UART1_CTS +//! - \ref IOC_PORT_MCU_UART1_RTS +//! - \ref IOC_PORT_MCU_PORT_EVENT0 +//! - \ref IOC_PORT_MCU_PORT_EVENT1 +//! - \ref IOC_PORT_MCU_PORT_EVENT2 +//! - \ref IOC_PORT_MCU_PORT_EVENT3 +//! - \ref IOC_PORT_MCU_PORT_EVENT4 +//! - \ref IOC_PORT_MCU_PORT_EVENT5 +//! - \ref IOC_PORT_MCU_PORT_EVENT6 +//! - \ref IOC_PORT_MCU_PORT_EVENT7 +//! - \ref IOC_PORT_MCU_SWV +//! - \ref IOC_PORT_MCU_SSI1_RX +//! - \ref IOC_PORT_MCU_SSI1_TX +//! - \ref IOC_PORT_MCU_SSI1_FSS +//! - \ref IOC_PORT_MCU_SSI1_CLK +//! - \ref IOC_PORT_MCU_I2S_AD0 +//! - \ref IOC_PORT_MCU_I2S_AD1 +//! - \ref IOC_PORT_MCU_I2S_WCLK +//! - \ref IOC_PORT_MCU_I2S_BCLK +//! - \ref IOC_PORT_MCU_I2S_MCLK +//! - \ref IOC_PORT_RFC_TRC +//! - \ref IOC_PORT_RFC_GPO0 +//! - \ref IOC_PORT_RFC_GPO1 +//! - \ref IOC_PORT_RFC_GPO2 +//! - \ref IOC_PORT_RFC_GPO3 +//! - \ref IOC_PORT_RFC_GPI0 +//! - \ref IOC_PORT_RFC_GPI1 +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId); + +//***************************************************************************** +// +//! \brief Register an interrupt handler for an IO edge interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific IO interrupts must be enabled via \ref IOCIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! IOC interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +IOCIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_AON_GPIO_EDGE, pfnHandler); + + // Enable the IO edge interrupt. + IntEnable(INT_AON_GPIO_EDGE); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a IO edge interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when an IO edge interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +IOCIntUnregister(void) +{ + // Disable the interrupts. + IntDisable(INT_AON_GPIO_EDGE); + + // Unregister the interrupt handler. + IntUnregister(INT_AON_GPIO_EDGE); +} + +//***************************************************************************** +// +//! \brief Enables individual IO edge detect interrupt. +//! +//! This function enables the indicated IO edge interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IOId is the IO to enable edge detect interrupt for. +//! +//! \return None +// +//***************************************************************************** +extern void IOCIntEnable(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Disables individual IO edge interrupt sources. +//! +//! This function disables the indicated IO edge interrupt source. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IOId is the IO edge interrupt source to be disabled. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +extern void IOCIntDisable(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Clears the IO edge interrupt source. +//! +//! The specified IO edge interrupt source is cleared, so that it no longer +//! asserts. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IOId is the IO causing the interrupt. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +IOCIntClear(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Clear the requested interrupt source by clearing the event. + GPIO_clearEventDio(ui32IOId); +} + +//***************************************************************************** +// +//! \brief Returns the status of the IO interrupts. +//! +//! \param ui32IOId is the IO to get the status for. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE uint32_t +IOCIntStatus(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the event status. + return (GPIO_getEventDio(ui32IOId)); +} + + +//***************************************************************************** +// +//! \brief Setup an IO for standard GPIO input. +//! +//! Setup an IO for standard GPIO input with the following configuration: +//! - Port ID: +//! - \ref IOC_PORT_GPIO +//! - Configuration: +//! - \ref IOC_CURRENT_2MA +//! - \ref IOC_STRENGTH_AUTO +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_SLEW_DISABLE +//! - \ref IOC_HYST_DISABLE +//! - \ref IOC_NO_EDGE +//! - \ref IOC_INT_DISABLE +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_INPUT_ENABLE +//! +//! \param ui32IOId is the IO to setup for GPIO input +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeGpioInput(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Setup an IO for standard GPIO output. +//! +//! Setup an IO for standard GPIO output with the following configuration: +//! - Port ID: +//! - \ref IOC_PORT_GPIO +//! - Configuration: +//! - \ref IOC_CURRENT_2MA +//! - \ref IOC_STRENGTH_AUTO +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_SLEW_DISABLE +//! - \ref IOC_HYST_DISABLE +//! - \ref IOC_NO_EDGE +//! - \ref IOC_INT_DISABLE +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_INPUT_DISABLE +//! +//! \param ui32IOId is the IO to setup for GPIO output +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeGpioOutput(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard UART peripheral control. +//! +//! The UART pins must be properly configured for the UART peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s). Other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! \note If a UART pin is not intended to be used, then the parameter in the +//! function should be \ref IOID_UNUSED. +//! +//! \param ui32Base is the base address of the UART module. +//! \param ui32Rx is the IO Id of the IO to use as UART Receive. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Tx is the IO Id of the IO to use as UART Transmit. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Cts is the IO Id of the IO to use for UART Clear to send. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Rts is the IO Id of the IO to use for UART Request to send. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Cts, + uint32_t ui32Rts); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard SSI peripheral master control. +//! +//! \param ui32Base is the base address of the SSI module to connect to the IOs +//! \param ui32Rx is the IO to connect to the SSI MISO line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Tx is the IO to connect to the SSI MOSI line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Fss is the IO to connect to the SSI FSS line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Clk is the IO to connect to the SSI Clock output line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard SSI peripheral slave control. +//! +//! \param ui32Base is the base address of the SSI module to connect to the IOs +//! \param ui32Rx is the IO to connect to the SSI MOSI line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Tx is the IO to connect to the SSI MISO line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Fss is the IO to connect to the SSI FSS line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Clk is the IO to connect to the SSI Clock input line. +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard I2C peripheral control. +//! +//! \param ui32Base is the base address of the I2C module to connect to the IOs +//! \param ui32Data is the I2C data line +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Clk is the I2C input clock +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, + uint32_t ui32Clk); + + +//***************************************************************************** +// +//! \brief Configure an IO for AUX control. +//! +//! Use this function to enable AUX to control a specific IO. Please note, that +//! when using AUX to control the IO, the input/output control in the IOC is +//! bypassed and completely controlled by AUX, so enabling or disabling input +//! in the IOC has no effect. +//! +//! \note The IOs available for AUX control can vary from device to device. +//! +//! \param ui32IOId is the IO to setup for AUX usage. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeAux(uint32_t ui32IOId); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_IOCPortConfigureSet + #undef IOCPortConfigureSet + #define IOCPortConfigureSet ROM_IOCPortConfigureSet + #endif + #ifdef ROM_IOCPortConfigureGet + #undef IOCPortConfigureGet + #define IOCPortConfigureGet ROM_IOCPortConfigureGet + #endif + #ifdef ROM_IOCIOShutdownSet + #undef IOCIOShutdownSet + #define IOCIOShutdownSet ROM_IOCIOShutdownSet + #endif + #ifdef ROM_IOCIOModeSet + #undef IOCIOModeSet + #define IOCIOModeSet ROM_IOCIOModeSet + #endif + #ifdef ROM_IOCIOIntSet + #undef IOCIOIntSet + #define IOCIOIntSet ROM_IOCIOIntSet + #endif + #ifdef ROM_IOCIOEvtSet + #undef IOCIOEvtSet + #define IOCIOEvtSet ROM_IOCIOEvtSet + #endif + #ifdef ROM_IOCIOPortPullSet + #undef IOCIOPortPullSet + #define IOCIOPortPullSet ROM_IOCIOPortPullSet + #endif + #ifdef ROM_IOCIOHystSet + #undef IOCIOHystSet + #define IOCIOHystSet ROM_IOCIOHystSet + #endif + #ifdef ROM_IOCIOInputSet + #undef IOCIOInputSet + #define IOCIOInputSet ROM_IOCIOInputSet + #endif + #ifdef ROM_IOCIOSlewCtrlSet + #undef IOCIOSlewCtrlSet + #define IOCIOSlewCtrlSet ROM_IOCIOSlewCtrlSet + #endif + #ifdef ROM_IOCIODrvStrengthSet + #undef IOCIODrvStrengthSet + #define IOCIODrvStrengthSet ROM_IOCIODrvStrengthSet + #endif + #ifdef ROM_IOCIOPortIdSet + #undef IOCIOPortIdSet + #define IOCIOPortIdSet ROM_IOCIOPortIdSet + #endif + #ifdef ROM_IOCIntEnable + #undef IOCIntEnable + #define IOCIntEnable ROM_IOCIntEnable + #endif + #ifdef ROM_IOCIntDisable + #undef IOCIntDisable + #define IOCIntDisable ROM_IOCIntDisable + #endif + #ifdef ROM_IOCPinTypeGpioInput + #undef IOCPinTypeGpioInput + #define IOCPinTypeGpioInput ROM_IOCPinTypeGpioInput + #endif + #ifdef ROM_IOCPinTypeGpioOutput + #undef IOCPinTypeGpioOutput + #define IOCPinTypeGpioOutput ROM_IOCPinTypeGpioOutput + #endif + #ifdef ROM_IOCPinTypeUart + #undef IOCPinTypeUart + #define IOCPinTypeUart ROM_IOCPinTypeUart + #endif + #ifdef ROM_IOCPinTypeSsiMaster + #undef IOCPinTypeSsiMaster + #define IOCPinTypeSsiMaster ROM_IOCPinTypeSsiMaster + #endif + #ifdef ROM_IOCPinTypeSsiSlave + #undef IOCPinTypeSsiSlave + #define IOCPinTypeSsiSlave ROM_IOCPinTypeSsiSlave + #endif + #ifdef ROM_IOCPinTypeI2c + #undef IOCPinTypeI2c + #define IOCPinTypeI2c ROM_IOCPinTypeI2c + #endif + #ifdef ROM_IOCPinTypeAux + #undef IOCPinTypeAux + #define IOCPinTypeAux ROM_IOCPinTypeAux + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __IOC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h new file mode 100644 index 0000000..cd35eff --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h @@ -0,0 +1,92 @@ +/****************************************************************************** +* Filename: ioc_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup ioc_api +//! @{ +//! \section sec_ioc Introduction +//! +//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO). +//! The IOC consists of two APIs: +//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it. +//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc. +//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is +//! routed to a DIO for external use. +//! +//! For more information on the AON IOC see the [AON IOC API](\ref aonioc_api). +//! +//! \note The output driver of a DIO is not configured by the IOC API (except for drive strength); instead, it is controlled by the +//! peripheral module which is selected to control the DIO. +//! +//! A DIO is considered "software controlled" if it is configured for GPIO control which allows the +//! System CPU to set the value of the DIO via the [GPIO API](\ref gpio_api). Alternatively, a DIO +//! can be "hardware controlled" if it is controlled by other modules than GPIO. +//! +//! \section sec_ioc_api API +//! +//! The API functions can be grouped like this: +//! +//! Configure all settings at the same time: +//! - \ref IOCPortConfigureSet() +//! - \ref IOCPortConfigureGet() +//! +//! Configure individual settings: +//! - \ref IOCIODrvStrengthSet() +//! - \ref IOCIOHystSet() +//! - \ref IOCIOInputSet() +//! - \ref IOCIOIntSet() +//! - \ref IOCIOModeSet() +//! - \ref IOCIOPortIdSet() +//! - \ref IOCIOPortPullSet() +//! - \ref IOCIOShutdownSet() +//! - \ref IOCIOSlewCtrlSet() +//! +//! Handle edge detection events: +//! - \ref IOCIntEnable() +//! - \ref IOCIntDisable() +//! - \ref IOCIntClear() +//! - \ref IOCIntStatus() +//! - \ref IOCIntRegister() +//! - \ref IOCIntUnregister() +//! +//! Configure IOCs for typical use cases (can also be used as example code): +//! - \ref IOCPinTypeAux() +//! - \ref IOCPinTypeGpioInput() +//! - \ref IOCPinTypeGpioOutput() +//! - \ref IOCPinTypeI2c() +//! - \ref IOCPinTypeSsiMaster() +//! - \ref IOCPinTypeSsiSlave() +//! - \ref IOCPinTypeUart() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/osc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/osc.c new file mode 100644 index 0000000..2e78876 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/osc.c @@ -0,0 +1,625 @@ +/****************************************************************************** +* Filename: osc.c +* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) +* Revision: 54539 +* +* Description: Driver for setting up the system Oscillators +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_fcfg1.h" +#include "aon_batmon.h" +#include "aon_rtc.h" +#include "osc.h" +#include "setup_rom.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef OSCClockSourceSet + #define OSCClockSourceSet NOROM_OSCClockSourceSet + #undef OSCClockSourceGet + #define OSCClockSourceGet NOROM_OSCClockSourceGet + #undef OSCHF_GetStartupTime + #define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime + #undef OSCHF_TurnOnXosc + #define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc + #undef OSCHF_AttemptToSwitchToXosc + #define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc + #undef OSCHF_SwitchToRcOscTurnOffXosc + #define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc + #undef OSCHF_DebugGetCrystalAmplitude + #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude + #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude + #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #undef OSC_HPOSC_Debug_InitFreqOffsetParams + #define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams + #undef OSC_HPOSCInitializeFrequencyOffsetParameters + #define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters + #undef OSC_HPOSCRelativeFrequencyOffsetGet + #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet + #undef OSC_AdjustXoscHfCapArray + #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray + #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #undef OSC_HPOSCRtcCompensate + #define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate +#endif + +//***************************************************************************** +// +// Global HPOSC curve fitting polynomials +// Parameters found/calculated when calling function +// OSC_HPOSCInitializeFrequencyOffsetParameters() +// (or OSC_HPOSC_Debug_InitFreqOffsetParams() used for debugging only) +// These global variables must be updated before using HPOSC +// +//***************************************************************************** + +static int16_t _hpOscPolynomials[ 4 ]; + +//***************************************************************************** +// +// OSCHF switch time calculator defines and globals +// +//***************************************************************************** + +#define RTC_CV_TO_MS(x) (( 1000 * ( x )) >> 16 ) +#define RTC_CV_TO_US(x) (( 1000000 * ( x )) >> 16 ) + +typedef struct { + uint32_t previousStartupTimeInUs ; + uint32_t timeXoscOff_CV ; + uint32_t timeXoscOn_CV ; + uint32_t timeXoscStable_CV ; + int32_t tempXoscOff ; +} OscHfGlobals_t; + +static OscHfGlobals_t oscHfGlobals; + +//***************************************************************************** +// +// Configure the oscillator input to the a source clock. +// +//***************************************************************************** +void +OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc) +{ + // Check the arguments. + ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || + (ui32SrcClk & OSC_SRC_CLK_HF)); + ASSERT((ui32Osc == OSC_RCOSC_HF) || + (ui32Osc == OSC_RCOSC_LF) || + (ui32Osc == OSC_XOSC_HF) || + (ui32Osc == OSC_XOSC_LF)); + + // Request the high frequency source clock (using 24 MHz XTAL) + if(ui32SrcClk & OSC_SRC_CLK_HF) + { + // Enable the HF XTAL as HF clock source + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S, + ui32Osc); + } + + // Configure the low frequency source clock. + if(ui32SrcClk & OSC_SRC_CLK_LF) + { + // Change the clock source. + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S, + ui32Osc); + } +} + +//***************************************************************************** +// +// Get the source clock settings +// +//***************************************************************************** +uint32_t +OSCClockSourceGet(uint32_t ui32SrcClk) +{ + uint32_t ui32ClockSource; + + // Check the arguments. + ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || + (ui32SrcClk & OSC_SRC_CLK_HF)); + + // Return the source for the selected clock. + if(ui32SrcClk == OSC_SRC_CLK_LF) + { + ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_SCLK_LF_SRC_M, + DDI_0_OSC_STAT0_SCLK_LF_SRC_S); + } + else + { + ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_SCLK_HF_SRC_M, + DDI_0_OSC_STAT0_SCLK_HF_SRC_S); + } + return (ui32ClockSource); +} + +//***************************************************************************** +// +// Returns maximum startup time (in microseconds) of XOSC_HF +// +//***************************************************************************** +uint32_t +OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ) +{ + uint32_t deltaTimeSinceXoscOnInMs ; + int32_t deltaTempSinceXoscOn ; + uint32_t newStartupTimeInUs ; + + deltaTimeSinceXoscOnInMs = RTC_CV_TO_MS( AONRTCCurrentCompareValueGet() - oscHfGlobals.timeXoscOn_CV ); + deltaTempSinceXoscOn = AONBatMonTemperatureGetDegC() - oscHfGlobals.tempXoscOff; + + if ( deltaTempSinceXoscOn < 0 ) { + deltaTempSinceXoscOn = -deltaTempSinceXoscOn; + } + + if ( (( timeUntilWakeupInMs + deltaTimeSinceXoscOnInMs ) > 3000 ) || + ( deltaTempSinceXoscOn > 5 ) || + ( oscHfGlobals.timeXoscStable_CV < oscHfGlobals.timeXoscOn_CV ) || + ( oscHfGlobals.previousStartupTimeInUs == 0 ) ) + { + newStartupTimeInUs = 2000; + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) { + newStartupTimeInUs = (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & + CCFG_MODE_CONF_1_XOSC_MAX_START_M ) >> + CCFG_MODE_CONF_1_XOSC_MAX_START_S ) * 125; + // Note: CCFG startup time is "in units of 100us" adding 25% margin results in *125 + } + } else { + newStartupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV ); + newStartupTimeInUs += ( newStartupTimeInUs >> 2 ); // Add 25 percent margin + if ( newStartupTimeInUs < oscHfGlobals.previousStartupTimeInUs ) { + newStartupTimeInUs = oscHfGlobals.previousStartupTimeInUs; + } + } + + if ( newStartupTimeInUs < 200 ) { + newStartupTimeInUs = 200; + } + if ( newStartupTimeInUs > 4000 ) { + newStartupTimeInUs = 4000; + } + return ( newStartupTimeInUs ); +} + + +//***************************************************************************** +// +// Turns on XOSC_HF (but without switching to XOSC_HF) +// +//***************************************************************************** +void +OSCHF_TurnOnXosc( void ) +{ +#if ( defined( ROM_OSCClockSourceSet )) + ROM_OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_XOSC_HF ); +#else + OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_XOSC_HF ); +#endif + oscHfGlobals.timeXoscOn_CV = AONRTCCurrentCompareValueGet(); +} + + +//***************************************************************************** +// +// Switch to XOSC_HF if XOSC_HF is ready. +// +//***************************************************************************** +bool +OSCHF_AttemptToSwitchToXosc( void ) +{ + uint32_t startupTimeInUs; + uint32_t prevLimmit25InUs; + +#if ( defined( ROM_OSCClockSourceGet )) + if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF ) +#else + if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF ) +#endif + { + // Already on XOSC - nothing to do + return ( 1 ); + } + if ( OSCHfSourceReady()) { + OSCHfSourceSwitch(); + + // Store startup time, but limit to 25 percent reduction each time. + oscHfGlobals.timeXoscStable_CV = AONRTCCurrentCompareValueGet(); + startupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV ); + prevLimmit25InUs = oscHfGlobals.previousStartupTimeInUs; + prevLimmit25InUs -= ( prevLimmit25InUs >> 2 ); // 25 percent margin + oscHfGlobals.previousStartupTimeInUs = startupTimeInUs; + if ( prevLimmit25InUs > startupTimeInUs ) { + oscHfGlobals.previousStartupTimeInUs = prevLimmit25InUs; + } + return ( 1 ); + } + return ( 0 ); +} + + +//***************************************************************************** +// +// Switch to RCOSC_HF and turn off XOSC_HF +// +//***************************************************************************** +void +OSCHF_SwitchToRcOscTurnOffXosc( void ) +{ +#if ( defined( ROM_OSCClockSourceSet )) + ROM_OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_RCOSC_HF ); +#else + OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_RCOSC_HF ); +#endif + + // Do the switching if not already running on RCOSC_HF +#if ( defined( ROM_OSCClockSourceGet )) + if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF ) +#else + if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF ) +#endif + { + OSCHfSourceSwitch(); + } + + oscHfGlobals.timeXoscOff_CV = AONRTCCurrentCompareValueGet(); + oscHfGlobals.tempXoscOff = AONBatMonTemperatureGetDegC(); +} + +//***************************************************************************** +// +// Adjust the XOSC HF cap array relative to the factory setting +// +//***************************************************************************** +void +OSC_AdjustXoscHfCapArray( int32_t capArrDelta ) +{ + // read the MODE_CONF register in CCFG + uint32_t ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + // Clear CAP_MODE and the CAPARRAY_DELATA field + ccfg_ModeConfReg &= ~( CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M | CCFG_MODE_CONF_XOSC_CAP_MOD_M ); + // Insert new delta value + ccfg_ModeConfReg |= ((((uint32_t)capArrDelta) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) & CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ); + // Update the HW register with the new delta value + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg )); +} + +//***************************************************************************** +// +// Initialize the frequency offset curve fitting parameters +// These are either picked diretly from FCFG1:FREQ_OFFSET & FCFG1:MISC_CONF_2 or +// calculated based on the FCFG1:HPOSC_MEAS_x parameters. +// +//***************************************************************************** + +// Using the following hardcoded constants (Using temporary constants for now) +#define D1OFFSET_p25C -24 +#define D2OFFSET_p85C -36 +#define D3OFFSET_m40C 18 +#define P3_POLYNOMIAL -47 +#define N_INSERTIONS 3 + +typedef struct { + int32_t dFreq ; + int32_t temp ; +} insertion_t ; + +static void +InitializeMeasurmentSet( insertion_t * pInsertion, uint32_t registerAddress, int32_t deltaOffset, int32_t p3PolOffset ) +{ + // Doing the following adjustment to the deltaFrequence before finding the polynomials P0, P1, P2 + // Dx = Dx + DxOFFSET - ((P3*Tx^3)/2^18) + uint32_t insertionData = HWREG( registerAddress ); + pInsertion->dFreq = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W - FCFG1_HPOSC_MEAS_1_HPOSC_D1_S ))) + >> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W )); + pInsertion->temp = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W - FCFG1_HPOSC_MEAS_1_HPOSC_T1_S ))) + >> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W )); + pInsertion->dFreq = pInsertion->dFreq + deltaOffset - (( p3PolOffset * pInsertion->temp * pInsertion->temp * pInsertion->temp ) >> 18 ); +} + +static void +FindPolynomialsAndUpdateGlobals( insertion_t * pMeasurment ) +{ + uint32_t loopCount ; + int32_t polynomial_0 ; + int32_t polynomial_1 ; + int32_t polynomial_2 ; + + int32_t Syi_ = 0 ; + int32_t Sxi_ = 0 ; + int32_t Sxi2_ = 0 ; + int32_t Sxiyi_ = 0 ; + int32_t Sxi2yi_ = 0 ; + int32_t Sxi3_ = 0 ; + int32_t Sxi4_ = 0 ; + + for ( loopCount = 0 ; loopCount < N_INSERTIONS ; loopCount++ ) { + int32_t x ; + int32_t x2 ; + int32_t y ; + + x = pMeasurment[ loopCount ].temp ; + x2 = ( x * x ); + y = pMeasurment[ loopCount ].dFreq ; + + Syi_ += ( y ); + Sxi_ += ( x ); + Sxi2_ += ( x2 ); + Sxiyi_ += ( x * y ); + Sxi2yi_ += ( x2 * y ); + Sxi3_ += ( x2 * x ); + Sxi4_ += ( x2 * x2 ); + } + + int32_t Sxx_ = ( Sxi2_ * N_INSERTIONS ) - ( Sxi_ * Sxi_ ); + int32_t Sxy_ = ( Sxiyi_ * N_INSERTIONS ) - ( Sxi_ * Syi_ ); + int32_t Sxx2_ = ( Sxi3_ * N_INSERTIONS ) - ( Sxi_ * Sxi2_ ); + int32_t Sx2y_ = ( Sxi2yi_ * N_INSERTIONS ) - ( Sxi2_ * Syi_ ); + int32_t Sx2x2_ = ( Sxi4_ * N_INSERTIONS ) - ( Sxi2_ * Sxi2_ ); + + int32_t divisor = ((((int64_t) Sxx_ * Sx2x2_ ) - ((int64_t) Sxx2_ * Sxx2_ )) + (1<<9)) >> 10 ; + if ( divisor == 0 ) { + polynomial_2 = 0 ; + polynomial_1 = 0 ; + } else { + polynomial_2 = (((int64_t) Sx2y_ * Sxx_ ) - ((int64_t) Sxy_ * Sxx2_ )) / divisor ; + polynomial_1 = (((int64_t) Sxy_ * Sx2x2_ ) - ((int64_t) Sx2y_ * Sxx2_ )) / divisor ; + } + polynomial_0 = ( Syi_ - (((( polynomial_1 * Sxi_ ) + ( polynomial_2 * Sxi2_ )) + (1<<9)) >> 10 )) / N_INSERTIONS ; + polynomial_1 = ( polynomial_1 + (1<<6)) >> 7 ; + + _hpOscPolynomials[ 0 ] = polynomial_0 ; + _hpOscPolynomials[ 1 ] = polynomial_1 ; + _hpOscPolynomials[ 2 ] = polynomial_2 ; + _hpOscPolynomials[ 3 ] = P3_POLYNOMIAL ; +} + +//***************************************************************************** +// Degub function to calculate the HPOSC polynomials for experimental data sets. +//***************************************************************************** +void +OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData ) +{ + // Calculate the curve fitting parameters from temp insertion measurements + // But first adjust the measurements with constants found in characterization + insertion_t pMeasurment[ 3 ]; + + InitializeMeasurmentSet( &pMeasurment[ 0 ], (uint32_t)&pDebugData->meas_1, pDebugData->offsetD1, pDebugData->polyP3 ); + InitializeMeasurmentSet( &pMeasurment[ 1 ], (uint32_t)&pDebugData->meas_2, pDebugData->offsetD2, pDebugData->polyP3 ); + InitializeMeasurmentSet( &pMeasurment[ 2 ], (uint32_t)&pDebugData->meas_3, pDebugData->offsetD3, pDebugData->polyP3 ); + + FindPolynomialsAndUpdateGlobals( pMeasurment ); +} + +//***************************************************************************** +// The general HPOSC initialization function - Must always be called before using HPOSC +//***************************************************************************** +void +OSC_HPOSCInitializeFrequencyOffsetParameters( void ) +{ + { + // Calculate the curve fitting parameters from temp insertion measurements + // But first adjust the measurements with constants found in characterization + insertion_t pMeasurment[ 3 ]; + + InitializeMeasurmentSet( &pMeasurment[ 0 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_1, D1OFFSET_p25C, P3_POLYNOMIAL ); + InitializeMeasurmentSet( &pMeasurment[ 1 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_2, D2OFFSET_p85C, P3_POLYNOMIAL ); + InitializeMeasurmentSet( &pMeasurment[ 2 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_3, D3OFFSET_m40C, P3_POLYNOMIAL ); + + FindPolynomialsAndUpdateGlobals( pMeasurment ); + } +} + +//***************************************************************************** +// +// Calculate the temperature dependent relative frequency offset of HPOSC +// +//***************************************************************************** +int32_t +OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ) +{ + // Estimate HPOSC frequency, using temperature and curve fitting parameters + + int32_t paramP0 = _hpOscPolynomials[ 0 ]; + int32_t paramP1 = _hpOscPolynomials[ 1 ]; + int32_t paramP2 = _hpOscPolynomials[ 2 ]; + int32_t paramP3 = _hpOscPolynomials[ 3 ]; + + // Now we can find the HPOSC freq offset, given as a signed variable d, expressed by: + // + // F_HPOSC = F_nom * (1 + d/(2^22)) , where: F_HPOSC = HPOSC frequency + // F_nom = nominal clock source frequency (e.g. 48.000 MHz) + // d = describes relative freq offset + + // We can estimate the d variable, using temperature compensation parameters: + // + // d = P0 + P1*(t - T0) + P2*(t - T0)^2 + P3*(t - T0)^3, where: P0,P1,P2,P3 are curve fitting parameters from FCFG1 + // t = current temperature (from temp sensor) in deg C + // T0 = 27 deg C (fixed temperature constant) + int32_t tempDelta = (tempDegC - 27); + int32_t tempDeltaX2 = tempDelta * tempDelta; + int32_t d = paramP0 + ((tempDelta*paramP1)>>3) + ((tempDeltaX2*paramP2)>>10) + ((tempDeltaX2*tempDelta*paramP3)>>18); + + return ( d ); +} + +//***************************************************************************** +// +// Converts the relative frequency offset of HPOSC to the RF Core parameter format. +// +//***************************************************************************** +int16_t +OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ) +{ + // The input argument, hereby referred to simply as "d", describes the frequency offset + // of the HPOSC relative to the nominal frequency in this way: + // + // F_HPOSC = F_nom * (1 + d/(2^22)) + // + // But for use by the radio, to compensate the frequency error, we need to find the + // frequency offset "rfcFreqOffset" defined in the following format: + // + // F_nom = F_HPOSC * (1 + rfCoreFreqOffset/(2^22)) + // + // To derive "rfCoreFreqOffset" from "d" we combine the two above equations and get: + // + // (1 + rfCoreFreqOffset/(2^22)) = (1 + d/(2^22))^-1 + // + // Which can be rewritten into: + // + // rfCoreFreqOffset = -d*(2^22) / ((2^22) + d) + // + // = -d * [ 1 / (1 + d/(2^22)) ] + // + // To avoid doing a 64-bit division due to the (1 + d/(2^22))^-1 expression, + // we can use Taylor series (Maclaurin series) to approximate it: + // + // 1 / (1 - x) ~= 1 + x + x^2 + x^3 + x^4 + ... etc (Maclaurin series) + // + // In our case, we have x = - d/(2^22), and we only include up to the first + // order term of the series, as the second order term ((d^2)/(2^44)) is very small: + // + // freqError ~= -d + d^2/(2^22) (+ small approximation error) + // + // The approximation error is negligible for our use. + + int32_t rfCoreFreqOffset = -HPOSC_RelFreqOffset + (( HPOSC_RelFreqOffset * HPOSC_RelFreqOffset ) >> 22 ); + + return ( rfCoreFreqOffset ); +} + +//***************************************************************************** +// +// Compensate the RTC increment based on the relative frequency offset of HPOSC +// +//***************************************************************************** +void +OSC_HPOSCRtcCompensate( int32_t relFreqOffset ) +{ + uint32_t rtcSubSecInc; + uint32_t lfClkFrequency; + uint32_t hfFreq; + int64_t calcFactor; + + // Calculate SCLK_HF frequency, defined as: + // hfFreq = 48000000 * (1 + relFreqOffset/(2^22)) + if( relFreqOffset >= 0 ) + { + calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) + 0x200000 ) / 0x400000; + } + else + { + calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) - 0x200000 ) / 0x400000; + } + hfFreq = 48000000 + calcFactor; + + // Calculate SCLK_LF frequency, defined as SCLK_LF_FREQ = SCLK_HF_FREQ / 1536 + lfClkFrequency = ( hfFreq + 768 ) / 1536; + + // Calculate SUBSECINC, defined as: SUBSECINC = 2^38 / SCLK_LF_FREQ + rtcSubSecInc = 0x4000000000 / lfClkFrequency; + + /* Update SUBSECINC value */ + SetupSetAonRtcSubSecInc(rtcSubSecInc); +} + +//***************************************************************************** +// +// Get crystal amplitude (assuming crystal is running). +// +//***************************************************************************** +uint32_t +OSCHF_DebugGetCrystalAmplitude( void ) +{ + uint32_t oscCfgRegCopy ; + uint32_t startTime ; + uint32_t deltaTime ; + uint32_t ampValue ; + + // The specified method is as follows: + // 1. Set minimum interval between oscillator amplitude calibrations. + // (Done by setting PER_M=0 and PER_E=1) + // 2. Wait approximately 4 milliseconds in order to measure over a + // moderately large number of calibrations. + // 3. Read out the crystal amplitude value from the peek detector. + // 4. Restore original oscillator amplitude calibrations interval. + // 5. Return crystal amplitude value converted to millivolt. + oscCfgRegCopy = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG ); + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG ) = ( 1 << AON_PMCTL_OSCCFG_PER_E_S ); + startTime = AONRTCCurrentCompareValueGet(); + do { + deltaTime = AONRTCCurrentCompareValueGet() - startTime; + } while ( deltaTime < ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT ))); + ampValue = ( HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_STAT1 ) & + DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M ) >> + DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S ; + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG ) = oscCfgRegCopy; + + return ( ampValue * 15 ); +} + +//***************************************************************************** +// +// Get the expected average crystal amplitude. +// +//***************************************************************************** +uint32_t +OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ) +{ + uint32_t ampCompTh1 ; + uint32_t highThreshold ; + uint32_t lowThreshold ; + + ampCompTh1 = HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_AMPCOMPTH1 ); + highThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M ) >> + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S ; + lowThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M ) >> + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S ; + + return ((( highThreshold + lowThreshold ) * 15 ) >> 1 ); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h new file mode 100644 index 0000000..a355fd1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h @@ -0,0 +1,730 @@ +/****************************************************************************** +* Filename: osc.h +* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) +* Revision: 54539 +* +* Description: Defines and prototypes for the system oscillator control. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup osc_api +//! @{ +// +//***************************************************************************** + +#ifndef __OSC_H__ +#define __OSC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_aon_pmctl.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ddi.h" +#include "../inc/hw_ddi_0_osc.h" +#include "rom.h" +#include "ddi.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define OSCClockSourceSet NOROM_OSCClockSourceSet + #define OSCClockSourceGet NOROM_OSCClockSourceGet + #define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime + #define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc + #define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc + #define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc + #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude + #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams + #define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters + #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet + #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray + #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate +#endif + +//***************************************************************************** +// +// Defines for the High Frequency XTAL Power mode +// +//***************************************************************************** +#define LOW_POWER_XOSC 1 +#define HIGH_POWER_XOSC 0 + +//***************************************************************************** +// +// Defines for the High Frequency XTAL Power mode +// +//***************************************************************************** +#define OSC_SRC_CLK_HF 0x00000001 +#define OSC_SRC_CLK_LF 0x00000004 + +#define OSC_RCOSC_HF 0x00000000 +#define OSC_XOSC_HF 0x00000001 +#define OSC_RCOSC_LF 0x00000002 +#define OSC_XOSC_LF 0x00000003 + +#define SCLK_HF_RCOSC_HF 0 +#define SCLK_HF_XOSC_HF 1 + +#define SCLK_LF_FROM_RCOSC_HF 0 +#define SCLK_LF_FROM_XOSC_HF 1 +#define SCLK_LF_FROM_RCOSC_LF 2 +#define SCLK_LF_FROM_XOSC_LF 3 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Set Power Mode for High Frequency XTAL Oscillator. +//! +//! \param ui32Mode is the power mode for the HF XTAL. +//! - \ref LOW_POWER_XOSC +//! - \ref HIGH_POWER_XOSC +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +OSCXHfPowerModeSet(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == LOW_POWER_XOSC) || + (ui32Mode == HIGH_POWER_XOSC)); + + // Change the power mode. + DDI16BitWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE, + ui32Mode); +} + +//***************************************************************************** +// +//! \brief Enables OSC clock loss event detection. +//! +//! Enables the clock loss event flag to be raised if a clock loss is detected. +//! +//! \note OSC clock loss event must be disabled before SCLK_LF clock source is +//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the +//! change is confirmed (by calling \ref OSCClockSourceGet()). +//! +//! \return None +//! +//! \sa \ref OSCClockLossEventDisable() +// +//***************************************************************************** +__STATIC_INLINE void +OSCClockLossEventEnable( void ) +{ + DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 1 ); +} + +//***************************************************************************** +// +//! \brief Disables OSC clock loss event detection. +//! +//! Disabling the OSC clock loss event does also clear the clock loss event flag. +//! +//! \note OSC clock loss event must be disabled before SCLK_LF clock source is +//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the +//! change is confirmed (by calling \ref OSCClockSourceGet()). +//! +//! \return None +//! +//! \sa \ref OSCClockLossEventEnable() +// +//***************************************************************************** +__STATIC_INLINE void +OSCClockLossEventDisable( void ) +{ + DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 0 ); +} + +//***************************************************************************** +// +//! \brief Configure the oscillator input to the a source clock. +//! +//! Use this function to set the oscillator source for one or more of the +//! system source clocks. +//! +//! When selecting the high frequency clock source (OSC_SRC_CLK_HF), this function will not do +//! the actual switch. Enabling the high frequency XTAL can take several hundred +//! micro seconds, so the actual switch is done in a separate function, \ref OSCHfSourceSwitch(), +//! leaving System CPU free to perform other tasks as the XTAL starts up. +//! +//! \note The High Frequency (\ref OSC_SRC_CLK_HF) can only be derived from the +//! high frequency oscillator. The Low Frequency source clock (\ref OSC_SRC_CLK_LF) +//! can be derived from all 4 oscillators. +//! +//! \note If enabling \ref OSC_XOSC_LF it is not safe to go to powerdown/shutdown +//! until the LF clock is running which can be checked using \ref OSCClockSourceGet(). +//! +//! \note Clock loss reset generation must be disabled before SCLK_LF (\ref OSC_SRC_CLK_LF) +//! clock source is changed and remain disabled until the change is confirmed. +//! +//! \param ui32SrcClk is the source clocks to configure. +//! - \ref OSC_SRC_CLK_HF +//! - \ref OSC_SRC_CLK_LF +//! \param ui32Osc is the oscillator that drives the source clock. +//! - \ref OSC_RCOSC_HF +//! - \ref OSC_XOSC_HF +//! - \ref OSC_RCOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF) +//! - \ref OSC_XOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF) +//! +//! \sa \ref OSCClockSourceGet(), \ref OSCHfSourceSwitch() +//! +//! \return None +// +//***************************************************************************** +extern void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc); + +//***************************************************************************** +// +//! \brief Get the source clock settings. +//! +//! Use this function to get the oscillator source for one of the system source +//! clocks. +//! +//! \param ui32SrcClk is the source clock to check. +//! - \ref OSC_SRC_CLK_HF +//! - \ref OSC_SRC_CLK_LF +//! +//! \return Returns the type of oscillator that drives the clock source. +//! - \ref OSC_RCOSC_HF +//! - \ref OSC_XOSC_HF +//! - \ref OSC_RCOSC_LF +//! - \ref OSC_XOSC_LF +//! +//! \sa \ref OSCClockSourceSet(), \ref OSCHfSourceSwitch() +// +//***************************************************************************** +extern uint32_t OSCClockSourceGet(uint32_t ui32SrcClk); + +//***************************************************************************** +// +//! \brief Check if the HF clock source is ready to be switched. +//! +//! If a request to switch the HF clock source has been made, this function +//! can be used to check if the clock source is ready to be switched. +//! +//! Once the HF clock source is ready the switch can be performed by calling +//! the \ref OSCHfSourceSwitch() +//! +//! \return Returns status of HF clock source: +//! - \c true : HF clock source is ready. +//! - \c false : HF clock source is \b not ready. +// +//***************************************************************************** +__STATIC_INLINE bool +OSCHfSourceReady(void) +{ + // Return the readiness of the HF clock source + return (DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M, + DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S)) ? + true : false; +} + +//***************************************************************************** +// +//! \brief Switch the high frequency clock. +//! +//! When switching the HF clock source the clock period might be prolonged +//! leaving the clock 'stuck-at' high or low for a few cycles. To ensure that +//! this does not coincide with a read access to the Flash, potentially +//! freezing the device, the HF clock source switch must be executed from ROM. +//! +//! \note This function will not return until the clock source has been +//! switched. It is left to the programmer to ensure, that there is a pending +//! request for a HF clock source switch before this function is called. +//! +//! \return None +//! +//! \sa \ref OSCClockSourceSet() +// +//***************************************************************************** +__STATIC_INLINE void +OSCHfSourceSwitch(void) +{ + // Read target clock (lower half of the 32-bit CTL0 register) + uint16_t hfSrc = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0) & DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M; + + // If target clock source is RCOSC, change clock source for DCDC to RCOSC + if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC) + { + // Force DCDC to use RCOSC before switching SCLK_HF to RCOSC + HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16); + // Dummy read to ensure that the write has propagated + HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); + } + + // Switch the HF clock source + HapiHFSourceSafeSwitch(); + + // If target clock source is XOSC, change clock source for DCDC to "auto" + if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC) + { + // Set DCDC clock source back to "auto" after SCLK_HF was switched to XOSC + HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M; + } +} + +//***************************************************************************** +// +//! \brief Identifies if HPOSC is enabled. +//! +//! This function checks if the device supports HPOSC and that HPOSC is selected +//! as HF oscillator for use when the radio is active. +//! +//! \return Returns status of HPOSC functionality: +//! - \c true : HPOSC is enabled. +//! - \c false : HPOSC is not enabled. +// +//***************************************************************************** +__STATIC_INLINE bool +OSC_IsHPOSCEnabled(void) +{ + bool enabled = false; + + if((( HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & CCFG_MODE_CONF_XOSC_FREQ_M) == CCFG_MODE_CONF_XOSC_FREQ_HPOSC) && + (( HWREG(FCFG1_BASE + FCFG1_O_OSC_CONF) & FCFG1_OSC_CONF_HPOSC_OPTION) == 0)) + { + enabled = true; + } + + return (enabled); +} + +//***************************************************************************** +// +//! \brief Identifies if HPOSC is enabled and that SCLK_LF is derived from XOSC_HF. +//! +//! This function checks if the device supports HPOSC and that HPOSC is selected +//! as HF oscillator for use when the radio is active and also that SCLK_LF is +//! derived from XOSC_HF. +//! +//! \return Returns status of HPOSC and SCLK_LF configuration: +//! - \c true : HPOSC is enabled and SCLK_LF is derived from XOSC_HF. +//! - \c false : Either HPOSC not enabled or SCLK_LF is not derived from XOSC_HF. +// +//***************************************************************************** +__STATIC_INLINE bool +OSC_IsHPOSCEnabledWithHfDerivedLfClock(void) +{ + bool enabled = false; + + // Check configuration by reading lower half of the 32-bit CTL0 register + uint16_t regVal = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); + if( ( ( regVal & DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M ) == DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF ) && + ( ( regVal & DDI_0_OSC_CTL0_HPOSC_MODE_EN_M ) == DDI_0_OSC_CTL0_HPOSC_MODE_EN ) ) + { + enabled = true; + } + + return (enabled); +} + +//***************************************************************************** +// +//! \brief Returns maximum startup time (in microseconds) of XOSC_HF. +//! +//! The startup time depends on several factors. This function calculates the +//! maximum startup time based on statistical information. +//! +//! \param timeUntilWakeupInMs indicates how long time (milliseconds) to the +//! startup will occur. +//! +//! \return Time margin to use in microseconds. +// +//***************************************************************************** +extern uint32_t OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ); + +//***************************************************************************** +// +//! \brief Turns on XOSC_HF (but without switching to XOSC_HF). +//! +//! This function simply indicates the need for XOSC_HF to the hardware which +//! initiates the XOSC_HF startup. +//! +//! \return None +// +//***************************************************************************** +extern void OSCHF_TurnOnXosc( void ); + +//***************************************************************************** +// +//! \brief Switch to XOSC_HF if XOSC_HF is ready. +//! +//! This is a non-blocking function checking if the XOSC_HF is ready and +//! performs the switching if ready. The function is somewhat blocking in the +//! case where switching is performed. +//! +//! \return Returns status of the XOSC_HF switching: +//! - \c true : Switching to XOSC_HF has occurred. +//! - \c false : Switching has not occurred. +// +//***************************************************************************** +extern bool OSCHF_AttemptToSwitchToXosc( void ); + +//***************************************************************************** +// +//! \brief Switch to RCOSC_HF and turn off XOSC_HF. +//! +//! This operation takes approximately 50 microseconds (can be shorter if +//! RCOSC_HF already was running). +//! +//! \return None +// +//***************************************************************************** +extern void OSCHF_SwitchToRcOscTurnOffXosc( void ); + +//***************************************************************************** +// +//! \brief Get crystal amplitude (assuming crystal is running). +//! +//! \note This is a debug function only. +//! It is hence not recommended to call this function in normal operation. +//! +//! This function uses an on-chip ADC and peak detector for reading the crystal +//! amplitude. The measurement time is set to 4 milliseconds and this function +//! does not return before the measurement is done. +//! +//! Expected value is \ref OSCHF_DebugGetExpectedAverageCrystalAmplitude +/- 50 millivolt. +//! +//! \return Returns crystal amplitude in millivolt. +//! +//! \sa OSCHF_DebugGetExpectedAverageCrystalAmplitude() +// +//***************************************************************************** +extern uint32_t OSCHF_DebugGetCrystalAmplitude( void ); + +//***************************************************************************** +// +//! \brief Get the expected average crystal amplitude. +//! +//! \note This is a debug function only. +//! It is hence not recommended to call this function in normal operation. +//! +//! This function read the configured high and low thresholds and returns +//! the mean value converted to millivolt. +//! +//! \return Returns expected average crystal amplitude in millivolt. +//! +//! \sa OSCHF_DebugGetCrystalAmplitude() +// +//***************************************************************************** +extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ); + +//***************************************************************************** +// +//! \brief Data structure for experimental HPOSC polynomials calculation. +//! +//! The structure of the meas_1, meas_2 and meas_3 parameter is +//! as defined in FCFG1_O_HPOSC_MEAS_1, 2 and 3. +//! +//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams() +// +//***************************************************************************** +typedef struct { + uint32_t meas_1 ; //!< Measurement set 1 (typically at room temp) + uint32_t meas_2 ; //!< Measurement set 2 (typically at high temp) + uint32_t meas_3 ; //!< Measurement set 3 (typically at low temp) + int32_t offsetD1 ; //!< Offset to measurement set 1 + int32_t offsetD2 ; //!< Offset to measurement set 2 + int32_t offsetD3 ; //!< Offset to measurement set 3 + int32_t polyP3 ; //!< The P3 polynomial +} HposcDebugData_t; + +//***************************************************************************** +// +//! \brief Debug function to calculate the HPOSC polynomials for experimental data sets. +//! +//! \param pDebugData pointer to the input data collected in \ref HposcDebugData_t +//! +//! \return None +//! +//! \sa OSC_HPOSCInitializeFrequencyOffsetParameters() +// +//***************************************************************************** +extern void OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData ); + +//***************************************************************************** +// +//! \brief HPOSC initialization function. Must always be called before using HPOSC. +//! +//! Calculates the fitting curve parameters (polynomials) to used by the +//! HPOSC temperature compensation. +//! +//! \return None +//! +//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams() +// +//***************************************************************************** +extern void OSC_HPOSCInitializeFrequencyOffsetParameters( void ); + +//***************************************************************************** +// +//! \brief Calculate the temperature dependent relative frequency offset of HPOSC +//! +//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature. +//! The frequency offset from the nominal value can be predicted based on +//! second order linear interpolation using coefficients measured in chip +//! production and stored as factory configuration parameters. +//! +//! This function calculates the relative frequency offset, defined as: +//! 
+//!     F_HPOSC = F_nom * (1 + d/(2^22))
+//!
+//! where +//! - F_HPOSC is the current HPOSC frequency. +//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. +//! - d is the relative frequency offset (the value returned). +//! +//! By knowing the relative frequency offset it is then possible to compensate +//! any timing related values accordingly. +//! +//! \param tempDegC is the chip temperature in degrees Celsius. Use the +//! function \ref AONBatMonTemperatureGetDegC() to get current chip temperature. +//! +//! \return Returns the relative frequency offset parameter d. +//! +//! \sa OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(), AONBatMonTemperatureGetDegC() +// +//***************************************************************************** +extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ); + +//***************************************************************************** +// +//! \brief Adjust the XOSC HF cap array relative to the factory setting +//! +//! The cap array factory setting (FCFG) can be converted to a number in the range 0 - 63. +//! Both this function and the customer configuration (CCFG) setting can apply a delta to the FCFG setting. +//! The CCFG setting is automatically applied at boot time (See ../startup_files/ccfg.c). +//! Calling this function will discard the CCFG setting and adjust relative to the FCFG setting. +//! +//! \note Adjusted value will not take effect before XOSC_HF is stopped and restarted +//! +//! \param capArrDelta specifies number of step to adjust the cap array relative to the factory setting. +//! +//! \return None +// +//***************************************************************************** +extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta ); + +//***************************************************************************** +// +//! \brief Converts the relative frequency offset of HPOSC to the RF Core parameter format. +//! +//! The HPOSC (High Precision Oscillator) clock is used by the RF Core. +//! To compensate for a frequency offset in the frequency of the clock source, +//! a frequency offset parameter can be provided as part of the radio configuration +//! override setting list to enable compensation of the RF synthesizer frequency, +//! symbol timing, and radio timer to still achieve correct frequencies. +//! +//! The RF Core takes a relative frequency offset parameter defined differently +//! compared to the relative frequency offset parameter returned from function +//! \ref OSC_HPOSCRelativeFrequencyOffsetGet() and thus needs to be converted: +//! 
+//!     F_nom = F_HPOSC * (1 + RfCoreRelFreqOffset/(2^22))
+//!
+//! where +//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. +//! - F_HPOSC is the current HPOSC frequency. +//! - RfCoreRelFreqOffset is the relative frequency offset in the "RF Core" format (the value returned). +//! +//! \param HPOSC_RelFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet() +//! +//! \return Returns the relative frequency offset in RF Core format. +//! +//! \sa OSC_HPOSCRelativeFrequencyOffsetGet() +// +//***************************************************************************** +extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ); + +//***************************************************************************** +// +//! \brief Compensate the RTC increment based on the relative frequency offset of HPOSC +//! +//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature. +//! This variation forces the RTC increment to be compensated if SCLK_LF is configured +//! to be derived from the HF clock of HPOSC. +//! This function must only be called if SCLK_LF is configured to be derived from +//! the HF clock of HPOSC. The status of this configuration can be determined +//! by calling the \ref OSC_IsHPOSCEnabledWithHfDerivedLfClock() function. +//! +//! This function first calculates the HPOSC frequency, defined as: +//! 
+//!     F_HPOSC = F_nom * (1 + d/(2^22))
+//!
+//! where +//! - F_HPOSC is the current HPOSC frequency. +//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. +//! - d is the relative frequency offset given by the input argument relFreqOffset. +//! Then the SCLK_LF frequency is calculated, defined as: +//! 
+//!     F_SCLK_LF = F_HPOSC / 1536
+//!
+//! Then the RTC increment SUBSECINC is calculated, defined as; +//! 
+//!     SUBSECINC = (2^38) / F_SCLK_LF
+//!
+//! Finally the RTC module is updated with the calculated SUBSECINC value. +//! +//! \param relFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet() +//! +//! \return None +//! +// +//***************************************************************************** +extern void OSC_HPOSCRtcCompensate( int32_t relFreqOffset ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_OSCClockSourceSet + #undef OSCClockSourceSet + #define OSCClockSourceSet ROM_OSCClockSourceSet + #endif + #ifdef ROM_OSCClockSourceGet + #undef OSCClockSourceGet + #define OSCClockSourceGet ROM_OSCClockSourceGet + #endif + #ifdef ROM_OSCHF_GetStartupTime + #undef OSCHF_GetStartupTime + #define OSCHF_GetStartupTime ROM_OSCHF_GetStartupTime + #endif + #ifdef ROM_OSCHF_TurnOnXosc + #undef OSCHF_TurnOnXosc + #define OSCHF_TurnOnXosc ROM_OSCHF_TurnOnXosc + #endif + #ifdef ROM_OSCHF_AttemptToSwitchToXosc + #undef OSCHF_AttemptToSwitchToXosc + #define OSCHF_AttemptToSwitchToXosc ROM_OSCHF_AttemptToSwitchToXosc + #endif + #ifdef ROM_OSCHF_SwitchToRcOscTurnOffXosc + #undef OSCHF_SwitchToRcOscTurnOffXosc + #define OSCHF_SwitchToRcOscTurnOffXosc ROM_OSCHF_SwitchToRcOscTurnOffXosc + #endif + #ifdef ROM_OSCHF_DebugGetCrystalAmplitude + #undef OSCHF_DebugGetCrystalAmplitude + #define OSCHF_DebugGetCrystalAmplitude ROM_OSCHF_DebugGetCrystalAmplitude + #endif + #ifdef ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude + #define OSCHF_DebugGetExpectedAverageCrystalAmplitude ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #endif + #ifdef ROM_OSC_HPOSC_Debug_InitFreqOffsetParams + #undef OSC_HPOSC_Debug_InitFreqOffsetParams + #define OSC_HPOSC_Debug_InitFreqOffsetParams ROM_OSC_HPOSC_Debug_InitFreqOffsetParams + #endif + #ifdef ROM_OSC_HPOSCInitializeFrequencyOffsetParameters + #undef OSC_HPOSCInitializeFrequencyOffsetParameters + #define OSC_HPOSCInitializeFrequencyOffsetParameters ROM_OSC_HPOSCInitializeFrequencyOffsetParameters + #endif + #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetGet + #undef OSC_HPOSCRelativeFrequencyOffsetGet + #define OSC_HPOSCRelativeFrequencyOffsetGet ROM_OSC_HPOSCRelativeFrequencyOffsetGet + #endif + #ifdef ROM_OSC_AdjustXoscHfCapArray + #undef OSC_AdjustXoscHfCapArray + #define OSC_AdjustXoscHfCapArray ROM_OSC_AdjustXoscHfCapArray + #endif + #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #endif + #ifdef ROM_OSC_HPOSCRtcCompensate + #undef OSC_HPOSCRtcCompensate + #define OSC_HPOSCRtcCompensate ROM_OSC_HPOSCRtcCompensate + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __OSC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka.c new file mode 100644 index 0000000..0c793f8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka.c @@ -0,0 +1,1661 @@ +/****************************************************************************** +* Filename: pka.c +* Revised: 2018-07-19 15:07:05 +0200 (Thu, 19 Jul 2018) +* Revision: 52294 +* +* Description: Driver for the PKA module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "pka.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef PKAClearPkaRam + #define PKAClearPkaRam NOROM_PKAClearPkaRam + #undef PKAGetOpsStatus + #define PKAGetOpsStatus NOROM_PKAGetOpsStatus + #undef PKAArrayAllZeros + #define PKAArrayAllZeros NOROM_PKAArrayAllZeros + #undef PKAZeroOutArray + #define PKAZeroOutArray NOROM_PKAZeroOutArray + #undef PKABigNumModStart + #define PKABigNumModStart NOROM_PKABigNumModStart + #undef PKABigNumModGetResult + #define PKABigNumModGetResult NOROM_PKABigNumModGetResult + #undef PKABigNumDivideStart + #define PKABigNumDivideStart NOROM_PKABigNumDivideStart + #undef PKABigNumDivideGetQuotient + #define PKABigNumDivideGetQuotient NOROM_PKABigNumDivideGetQuotient + #undef PKABigNumDivideGetRemainder + #define PKABigNumDivideGetRemainder NOROM_PKABigNumDivideGetRemainder + #undef PKABigNumCmpStart + #define PKABigNumCmpStart NOROM_PKABigNumCmpStart + #undef PKABigNumCmpGetResult + #define PKABigNumCmpGetResult NOROM_PKABigNumCmpGetResult + #undef PKABigNumInvModStart + #define PKABigNumInvModStart NOROM_PKABigNumInvModStart + #undef PKABigNumInvModGetResult + #define PKABigNumInvModGetResult NOROM_PKABigNumInvModGetResult + #undef PKABigNumMultiplyStart + #define PKABigNumMultiplyStart NOROM_PKABigNumMultiplyStart + #undef PKABigNumMultGetResult + #define PKABigNumMultGetResult NOROM_PKABigNumMultGetResult + #undef PKABigNumAddStart + #define PKABigNumAddStart NOROM_PKABigNumAddStart + #undef PKABigNumAddGetResult + #define PKABigNumAddGetResult NOROM_PKABigNumAddGetResult + #undef PKABigNumSubStart + #define PKABigNumSubStart NOROM_PKABigNumSubStart + #undef PKABigNumSubGetResult + #define PKABigNumSubGetResult NOROM_PKABigNumSubGetResult + #undef PKAEccMultiplyStart + #define PKAEccMultiplyStart NOROM_PKAEccMultiplyStart + #undef PKAEccMontgomeryMultiplyStart + #define PKAEccMontgomeryMultiplyStart NOROM_PKAEccMontgomeryMultiplyStart + #undef PKAEccMultiplyGetResult + #define PKAEccMultiplyGetResult NOROM_PKAEccMultiplyGetResult + #undef PKAEccAddStart + #define PKAEccAddStart NOROM_PKAEccAddStart + #undef PKAEccAddGetResult + #define PKAEccAddGetResult NOROM_PKAEccAddGetResult + #undef PKAEccVerifyPublicKeyWeierstrassStart + #define PKAEccVerifyPublicKeyWeierstrassStart NOROM_PKAEccVerifyPublicKeyWeierstrassStart +#endif + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef PKAClearPkaRam + #define PKAClearPkaRam NOROM_PKAClearPkaRam + #undef PKAGetOpsStatus + #define PKAGetOpsStatus NOROM_PKAGetOpsStatus + #undef PKAArrayAllZeros + #define PKAArrayAllZeros NOROM_PKAArrayAllZeros + #undef PKAZeroOutArray + #define PKAZeroOutArray NOROM_PKAZeroOutArray + #undef PKABigNumModStart + #define PKABigNumModStart NOROM_PKABigNumModStart + #undef PKABigNumModGetResult + #define PKABigNumModGetResult NOROM_PKABigNumModGetResult + #undef PKABigNumDivideStart + #define PKABigNumDivideStart NOROM_PKABigNumDivideStart + #undef PKABigNumDivideGetQuotient + #define PKABigNumDivideGetQuotient NOROM_PKABigNumDivideGetQuotient + #undef PKABigNumDivideGetRemainder + #define PKABigNumDivideGetRemainder NOROM_PKABigNumDivideGetRemainder + #undef PKABigNumCmpStart + #define PKABigNumCmpStart NOROM_PKABigNumCmpStart + #undef PKABigNumCmpGetResult + #define PKABigNumCmpGetResult NOROM_PKABigNumCmpGetResult + #undef PKABigNumInvModStart + #define PKABigNumInvModStart NOROM_PKABigNumInvModStart + #undef PKABigNumInvModGetResult + #define PKABigNumInvModGetResult NOROM_PKABigNumInvModGetResult + #undef PKABigNumMultiplyStart + #define PKABigNumMultiplyStart NOROM_PKABigNumMultiplyStart + #undef PKABigNumMultGetResult + #define PKABigNumMultGetResult NOROM_PKABigNumMultGetResult + #undef PKABigNumAddStart + #define PKABigNumAddStart NOROM_PKABigNumAddStart + #undef PKABigNumAddGetResult + #define PKABigNumAddGetResult NOROM_PKABigNumAddGetResult + #undef PKABigNumSubStart + #define PKABigNumSubStart NOROM_PKABigNumSubStart + #undef PKABigNumSubGetResult + #define PKABigNumSubGetResult NOROM_PKABigNumSubGetResult + #undef PKAEccMultiplyStart + #define PKAEccMultiplyStart NOROM_PKAEccMultiplyStart + #undef PKAEccMontgomeryMultiplyStart + #define PKAEccMontgomeryMultiplyStart NOROM_PKAEccMontgomeryMultiplyStart + #undef PKAEccMultiplyGetResult + #define PKAEccMultiplyGetResult NOROM_PKAEccMultiplyGetResult + #undef PKAEccAddStart + #define PKAEccAddStart NOROM_PKAEccAddStart + #undef PKAEccAddGetResult + #define PKAEccAddGetResult NOROM_PKAEccAddGetResult + #undef PKAEccVerifyPublicKeyWeierstrassStart + #define PKAEccVerifyPublicKeyWeierstrassStart NOROM_PKAEccVerifyPublicKeyWeierstrassStart +#endif + + + +#define MAX(x,y) (((x) > (y)) ? (x) : (y)) +#define MIN(x,y) (((x) < (y)) ? (x) : (y)) +#define INRANGE(x,y,z) ((x) > (y) && (x) < (z)) + + +//***************************************************************************** +// +// Define for the maximum curve size supported by the PKA module in 32 bit +// word. +// \note PKA hardware module can support up to 384 bit curve size due to the +// 2K of PKA RAM. +// +//***************************************************************************** +#define PKA_MAX_CURVE_SIZE_32_BIT_WORD 12 + +//***************************************************************************** +// +// Define for the maximum length of the big number supported by the PKA module +// in 32 bit word. +// +//***************************************************************************** +#define PKA_MAX_LEN_IN_32_BIT_WORD PKA_MAX_CURVE_SIZE_32_BIT_WORD + +//***************************************************************************** +// +// Used in PKAWritePkaParam() and PKAWritePkaParamExtraOffset() to specify that +// the base address of the parameter should not be written to a NPTR register. +// +//***************************************************************************** +#define PKA_NO_POINTER_REG 0xFF + +//***************************************************************************** +// +// NIST P224 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP224_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint224 NISTP224_generator = { + .x = {.byte = {0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34, + 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A, + 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B, + 0xBD, 0x0C, 0x0E, 0xB7, }}, + .y = {.byte = {0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44, + 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD, + 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5, + 0x88, 0x63, 0x37, 0xBD, }}, +}; + +const PKA_EccParam224 NISTP224_prime = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +const PKA_EccParam224 NISTP224_a = {.byte = {0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +const PKA_EccParam224 NISTP224_b = {.byte = {0xB4, 0xFF, 0x55, 0x23, 0x43, 0x39, 0x0B, 0x27, + 0xBA, 0xD8, 0xBF, 0xD7, 0xB7, 0xB0, 0x44, 0x50, + 0x56, 0x32, 0x41, 0xF5, 0xAB, 0xB3, 0x04, 0x0C, + 0x85, 0x0A, 0x05, 0xB4}}; + +const PKA_EccParam224 NISTP224_order = {.byte = {0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13, + 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +//***************************************************************************** +// +// NIST P256 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP256_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 NISTP256_generator = { + .x = {.byte = {0x96, 0xc2, 0x98, 0xd8, 0x45, 0x39, 0xa1, 0xf4, + 0xa0, 0x33, 0xeb, 0x2d, 0x81, 0x7d, 0x03, 0x77, + 0xf2, 0x40, 0xa4, 0x63, 0xe5, 0xe6, 0xbc, 0xf8, + 0x47, 0x42, 0x2c, 0xe1, 0xf2, 0xd1, 0x17, 0x6b}}, + .y = {.byte = {0xf5, 0x51, 0xbf, 0x37, 0x68, 0x40, 0xb6, 0xcb, + 0xce, 0x5e, 0x31, 0x6b, 0x57, 0x33, 0xce, 0x2b, + 0x16, 0x9e, 0x0f, 0x7c, 0x4a, 0xeb, 0xe7, 0x8e, + 0x9b, 0x7f, 0x1a, 0xfe, 0xe2, 0x42, 0xe3, 0x4f}}, +}; + +const PKA_EccParam256 NISTP256_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam256 NISTP256_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam256 NISTP256_b = {.byte = {0x4b, 0x60, 0xd2, 0x27, 0x3e, 0x3c, 0xce, 0x3b, + 0xf6, 0xb0, 0x53, 0xcc, 0xb0, 0x06, 0x1d, 0x65, + 0xbc, 0x86, 0x98, 0x76, 0x55, 0xbd, 0xeb, 0xb3, + 0xe7, 0x93, 0x3a, 0xaa, 0xd8, 0x35, 0xc6, 0x5a}}; + +const PKA_EccParam256 NISTP256_order = {.byte = {0x51, 0x25, 0x63, 0xfc, 0xc2, 0xca, 0xb9, 0xf3, + 0x84, 0x9e, 0x17, 0xa7, 0xad, 0xfa, 0xe6, 0xbc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +//***************************************************************************** +// +// NIST P384 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP384_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint384 NISTP384_generator = { + .x = {.byte = {0xb7, 0x0a, 0x76, 0x72, 0x38, 0x5e, 0x54, 0x3a, + 0x6c, 0x29, 0x55, 0xbf, 0x5d, 0xf2, 0x02, 0x55, + 0x38, 0x2a, 0x54, 0x82, 0xe0, 0x41, 0xf7, 0x59, + 0x98, 0x9b, 0xa7, 0x8b, 0x62, 0x3b, 0x1d, 0x6e, + 0x74, 0xad, 0x20, 0xf3, 0x1e, 0xc7, 0xb1, 0x8e, + 0x37, 0x05, 0x8b, 0xbe, 0x22, 0xca, 0x87, 0xaa}}, + .y = {.byte = {0x5f, 0x0e, 0xea, 0x90, 0x7c, 0x1d, 0x43, 0x7a, + 0x9d, 0x81, 0x7e, 0x1d, 0xce, 0xb1, 0x60, 0x0a, + 0xc0, 0xb8, 0xf0, 0xb5, 0x13, 0x31, 0xda, 0xe9, + 0x7c, 0x14, 0x9a, 0x28, 0xbd, 0x1d, 0xf4, 0xf8, + 0x29, 0xdc, 0x92, 0x92, 0xbf, 0x98, 0x9e, 0x5d, + 0x6f, 0x2c, 0x26, 0x96, 0x4a, 0xde, 0x17, 0x36,}}, +}; + +const PKA_EccParam384 NISTP384_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam384 NISTP384_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam384 NISTP384_b = {.byte = {0xef, 0x2a, 0xec, 0xd3, 0xed, 0xc8, 0x85, 0x2a, + 0x9d, 0xd1, 0x2e, 0x8a, 0x8d, 0x39, 0x56, 0xc6, + 0x5a, 0x87, 0x13, 0x50, 0x8f, 0x08, 0x14, 0x03, + 0x12, 0x41, 0x81, 0xfe, 0x6e, 0x9c, 0x1d, 0x18, + 0x19, 0x2d, 0xf8, 0xe3, 0x6b, 0x05, 0x8e, 0x98, + 0xe4, 0xe7, 0x3e, 0xe2, 0xa7, 0x2f, 0x31, 0xb3}}; + +const PKA_EccParam384 NISTP384_order = {.byte = {0x73, 0x29, 0xc5, 0xcc, 0x6a, 0x19, 0xec, 0xec, + 0x7a, 0xa7, 0xb0, 0x48, 0xb2, 0x0d, 0x1a, 0x58, + 0xdf, 0x2d, 0x37, 0xf4, 0x81, 0x4d, 0x63, 0xc7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + + +//***************************************************************************** +// +// NIST P521 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP521_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint521 NISTP521_generator = { + .x = {.byte = {0x66, 0xbd, 0xe5, 0xc2, 0x31, 0x7e, 0x7e, 0xf9, + 0x9b, 0x42, 0x6a, 0x85, 0xc1, 0xb3, 0x48, 0x33, + 0xde, 0xa8, 0xff, 0xa2, 0x27, 0xc1, 0x1d, 0xfe, + 0x28, 0x59, 0xe7, 0xef, 0x77, 0x5e, 0x4b, 0xa1, + 0xba, 0x3d, 0x4d, 0x6b, 0x60, 0xaf, 0x28, 0xf8, + 0x21, 0xb5, 0x3f, 0x05, 0x39, 0x81, 0x64, 0x9c, + 0x42, 0xb4, 0x95, 0x23, 0x66, 0xcb, 0x3e, 0x9e, + 0xcd, 0xe9, 0x04, 0x04, 0xb7, 0x06, 0x8e, 0x85, + 0xc6, 0x00}}, + .y = {.byte = {0x50, 0x66, 0xd1, 0x9f, 0x76, 0x94, 0xbe, 0x88, + 0x40, 0xc2, 0x72, 0xa2, 0x86, 0x70, 0x3c, 0x35, + 0x61, 0x07, 0xad, 0x3f, 0x01, 0xb9, 0x50, 0xc5, + 0x40, 0x26, 0xf4, 0x5e, 0x99, 0x72, 0xee, 0x97, + 0x2c, 0x66, 0x3e, 0x27, 0x17, 0xbd, 0xaf, 0x17, + 0x68, 0x44, 0x9b, 0x57, 0x49, 0x44, 0xf5, 0x98, + 0xd9, 0x1b, 0x7d, 0x2c, 0xb4, 0x5f, 0x8a, 0x5c, + 0x04, 0xc0, 0x3b, 0x9a, 0x78, 0x6a, 0x29, 0x39, + 0x18, 0x01}}, +}; + +const PKA_EccParam521 NISTP521_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + +const PKA_EccParam521 NISTP521_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + +const PKA_EccParam521 NISTP521_b = {.byte = {0x00, 0x3f, 0x50, 0x6b, 0xd4, 0x1f, 0x45, 0xef, + 0xf1, 0x34, 0x2c, 0x3d, 0x88, 0xdf, 0x73, 0x35, + 0x07, 0xbf, 0xb1, 0x3b, 0xbd, 0xc0, 0x52, 0x16, + 0x7b, 0x93, 0x7e, 0xec, 0x51, 0x39, 0x19, 0x56, + 0xe1, 0x09, 0xf1, 0x8e, 0x91, 0x89, 0xb4, 0xb8, + 0xf3, 0x15, 0xb3, 0x99, 0x5b, 0x72, 0xda, 0xa2, + 0xee, 0x40, 0x85, 0xb6, 0xa0, 0x21, 0x9a, 0x92, + 0x1f, 0x9a, 0x1c, 0x8e, 0x61, 0xb9, 0x3e, 0x95, + 0x51, 0x00}}; + +const PKA_EccParam521 NISTP521_order = {.byte = {0x09, 0x64, 0x38, 0x91, 0x1e, 0xb7, 0x6f, 0xbb, + 0xae, 0x47, 0x9c, 0x89, 0xb8, 0xc9, 0xb5, 0x3b, + 0xd0, 0xa5, 0x09, 0xf7, 0x48, 0x01, 0xcc, 0x7f, + 0x6b, 0x96, 0x2f, 0xbf, 0x83, 0x87, 0x86, 0x51, + 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + + +//***************************************************************************** +// +// Brainpool P256r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP256R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 BrainpoolP256R1_generator = { + .x = {.byte = {0x62, 0x32, 0xCE, 0x9A, 0xBD, 0x53, 0x44, 0x3A, + 0xC2, 0x23, 0xBD, 0xE3, 0xE1, 0x27, 0xDE, 0xB9, + 0xAF, 0xB7, 0x81, 0xFC, 0x2F, 0x48, 0x4B, 0x2C, + 0xCB, 0x57, 0x7E, 0xCB, 0xB9, 0xAE, 0xD2, 0x8B}}, + .y = {.byte = {0x97, 0x69, 0x04, 0x2F, 0xC7, 0x54, 0x1D, 0x5C, + 0x54, 0x8E, 0xED, 0x2D, 0x13, 0x45, 0x77, 0xC2, + 0xC9, 0x1D, 0x61, 0x14, 0x1A, 0x46, 0xF8, 0x97, + 0xFD, 0xC4, 0xDA, 0xC3, 0x35, 0xF8, 0x7E, 0x54}}, +}; + +const PKA_EccParam256 BrainpoolP256R1_prime = {.byte = {0x77, 0x53, 0x6E, 0x1F, 0x1D, 0x48, 0x13, 0x20, + 0x28, 0x20, 0x26, 0xD5, 0x23, 0xF6, 0x3B, 0x6E, + 0x72, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E, + 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}}; + +const PKA_EccParam256 BrainpoolP256R1_a = {.byte = {0xD9, 0xB5, 0x30, 0xF3, 0x44, 0x4B, 0x4A, 0xE9, + 0x6C, 0x5C, 0xDC, 0x26, 0xC1, 0x55, 0x80, 0xFB, + 0xE7, 0xFF, 0x7A, 0x41, 0x30, 0x75, 0xF6, 0xEE, + 0x57, 0x30, 0x2C, 0xFC, 0x75, 0x09, 0x5A, 0x7D}}; + +const PKA_EccParam256 BrainpoolP256R1_b = {.byte = {0xB6, 0x07, 0x8C, 0xFF, 0x18, 0xDC, 0xCC, 0x6B, + 0xCE, 0xE1, 0xF7, 0x5C, 0x29, 0x16, 0x84, 0x95, + 0xBF, 0x7C, 0xD7, 0xBB, 0xD9, 0xB5, 0x30, 0xF3, + 0x44, 0x4B, 0x4A, 0xE9, 0x6C, 0x5C, 0xDC, 0x26,}}; + +const PKA_EccParam256 BrainpoolP256R1_order = {.byte = {0xA7, 0x56, 0x48, 0x97, 0x82, 0x0E, 0x1E, 0x90, + 0xF7, 0xA6, 0x61, 0xB5, 0xA3, 0x7A, 0x39, 0x8C, + 0x71, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E, + 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}}; + +//***************************************************************************** +// +// Brainpool P384r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP384R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint384 BrainpoolP384R1_generator = { + .x = {.byte = {0x1E, 0xAF, 0xD4, 0x47, 0xE2, 0xB2, 0x87, 0xEF, + 0xAA, 0x46, 0xD6, 0x36, 0x34, 0xE0, 0x26, 0xE8, + 0xE8, 0x10, 0xBD, 0x0C, 0xFE, 0xCA, 0x7F, 0xDB, + 0xE3, 0x4F, 0xF1, 0x7E, 0xE7, 0xA3, 0x47, 0x88, + 0x6B, 0x3F, 0xC1, 0xB7, 0x81, 0x3A, 0xA6, 0xA2, + 0xFF, 0x45, 0xCF, 0x68, 0xF0, 0x64, 0x1C, 0x1D}}, + .y = {.byte = {0x15, 0x53, 0x3C, 0x26, 0x41, 0x03, 0x82, 0x42, + 0x11, 0x81, 0x91, 0x77, 0x21, 0x46, 0x46, 0x0E, + 0x28, 0x29, 0x91, 0xF9, 0x4F, 0x05, 0x9C, 0xE1, + 0x64, 0x58, 0xEC, 0xFE, 0x29, 0x0B, 0xB7, 0x62, + 0x52, 0xD5, 0xCF, 0x95, 0x8E, 0xEB, 0xB1, 0x5C, + 0xA4, 0xC2, 0xF9, 0x20, 0x75, 0x1D, 0xBE, 0x8A}}, +}; + +const PKA_EccParam384 BrainpoolP384R1_prime = {.byte = {0x53, 0xEC, 0x07, 0x31, 0x13, 0x00, 0x47, 0x87, + 0x71, 0x1A, 0x1D, 0x90, 0x29, 0xA7, 0xD3, 0xAC, + 0x23, 0x11, 0xB7, 0x7F, 0x19, 0xDA, 0xB1, 0x12, + 0xB4, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15, + 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F, + 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}}; + +const PKA_EccParam384 BrainpoolP384R1_a = {.byte = {0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04, + 0xEB, 0xD4, 0x3A, 0x50, 0x4A, 0x81, 0xA5, 0x8A, + 0x0F, 0xF9, 0x91, 0xBA, 0xEF, 0x65, 0x91, 0x13, + 0x87, 0x27, 0xB2, 0x4F, 0x8E, 0xA2, 0xBE, 0xC2, + 0xA0, 0xAF, 0x05, 0xCE, 0x0A, 0x08, 0x72, 0x3C, + 0x0C, 0x15, 0x8C, 0x3D, 0xC6, 0x82, 0xC3, 0x7B}}; + +const PKA_EccParam384 BrainpoolP384R1_b = {.byte = {0x11, 0x4C, 0x50, 0xFA, 0x96, 0x86, 0xB7, 0x3A, + 0x94, 0xC9, 0xDB, 0x95, 0x02, 0x39, 0xB4, 0x7C, + 0xD5, 0x62, 0xEB, 0x3E, 0xA5, 0x0E, 0x88, 0x2E, + 0xA6, 0xD2, 0xDC, 0x07, 0xE1, 0x7D, 0xB7, 0x2F, + 0x7C, 0x44, 0xF0, 0x16, 0x54, 0xB5, 0x39, 0x8B, + 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04}}; + +const PKA_EccParam384 BrainpoolP384R1_order = {.byte = {0x65, 0x65, 0x04, 0xE9, 0x02, 0x32, 0x88, 0x3B, + 0x10, 0xC3, 0x7F, 0x6B, 0xAF, 0xB6, 0x3A, 0xCF, + 0xA7, 0x25, 0x04, 0xAC, 0x6C, 0x6E, 0x16, 0x1F, + 0xB3, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15, + 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F, + 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}}; + +//***************************************************************************** +// +// Brainpool P512r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP512R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint512 BrainpoolP512R1_generator = { + .x = {.byte = {0x22, 0xF8, 0xB9, 0xBC, 0x09, 0x22, 0x35, 0x8B, + 0x68, 0x5E, 0x6A, 0x40, 0x47, 0x50, 0x6D, 0x7C, + 0x5F, 0x7D, 0xB9, 0x93, 0x7B, 0x68, 0xD1, 0x50, + 0x8D, 0xD4, 0xD0, 0xE2, 0x78, 0x1F, 0x3B, 0xFF, + 0x8E, 0x09, 0xD0, 0xF4, 0xEE, 0x62, 0x3B, 0xB4, + 0xC1, 0x16, 0xD9, 0xB5, 0x70, 0x9F, 0xED, 0x85, + 0x93, 0x6A, 0x4C, 0x9C, 0x2E, 0x32, 0x21, 0x5A, + 0x64, 0xD9, 0x2E, 0xD8, 0xBD, 0xE4, 0xAE, 0x81}}, + .y = {.byte = {0x92, 0x08, 0xD8, 0x3A, 0x0F, 0x1E, 0xCD, 0x78, + 0x06, 0x54, 0xF0, 0xA8, 0x2F, 0x2B, 0xCA, 0xD1, + 0xAE, 0x63, 0x27, 0x8A, 0xD8, 0x4B, 0xCA, 0x5B, + 0x5E, 0x48, 0x5F, 0x4A, 0x49, 0xDE, 0xDC, 0xB2, + 0x11, 0x81, 0x1F, 0x88, 0x5B, 0xC5, 0x00, 0xA0, + 0x1A, 0x7B, 0xA5, 0x24, 0x00, 0xF7, 0x09, 0xF2, + 0xFD, 0x22, 0x78, 0xCF, 0xA9, 0xBF, 0xEA, 0xC0, + 0xEC, 0x32, 0x63, 0x56, 0x5D, 0x38, 0xDE, 0x7D}}, +}; + +const PKA_EccParam512 BrainpoolP512R1_prime = {.byte = {0xF3, 0x48, 0x3A, 0x58, 0x56, 0x60, 0xAA, 0x28, + 0x85, 0xC6, 0x82, 0x2D, 0x2F, 0xFF, 0x81, 0x28, + 0xE6, 0x80, 0xA3, 0xE6, 0x2A, 0xA1, 0xCD, 0xAE, + 0x42, 0x68, 0xC6, 0x9B, 0x00, 0x9B, 0x4D, 0x7D, + 0x71, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6, + 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB, + 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F, + 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}}; + +const PKA_EccParam512 BrainpoolP512R1_a = {.byte = {0xCA, 0x94, 0xFC, 0x77, 0x4D, 0xAC, 0xC1, 0xE7, + 0xB9, 0xC7, 0xF2, 0x2B, 0xA7, 0x17, 0x11, 0x7F, + 0xB5, 0xC8, 0x9A, 0x8B, 0xC9, 0xF1, 0x2E, 0x0A, + 0xA1, 0x3A, 0x25, 0xA8, 0x5A, 0x5D, 0xED, 0x2D, + 0xBC, 0x63, 0x98, 0xEA, 0xCA, 0x41, 0x34, 0xA8, + 0x10, 0x16, 0xF9, 0x3D, 0x8D, 0xDD, 0xCB, 0x94, + 0xC5, 0x4C, 0x23, 0xAC, 0x45, 0x71, 0x32, 0xE2, + 0x89, 0x3B, 0x60, 0x8B, 0x31, 0xA3, 0x30, 0x78}}; + +const PKA_EccParam512 BrainpoolP512R1_b = {.byte = {0x23, 0xF7, 0x16, 0x80, 0x63, 0xBD, 0x09, 0x28, + 0xDD, 0xE5, 0xBA, 0x5E, 0xB7, 0x50, 0x40, 0x98, + 0x67, 0x3E, 0x08, 0xDC, 0xCA, 0x94, 0xFC, 0x77, + 0x4D, 0xAC, 0xC1, 0xE7, 0xB9, 0xC7, 0xF2, 0x2B, + 0xA7, 0x17, 0x11, 0x7F, 0xB5, 0xC8, 0x9A, 0x8B, + 0xC9, 0xF1, 0x2E, 0x0A, 0xA1, 0x3A, 0x25, 0xA8, + 0x5A, 0x5D, 0xED, 0x2D, 0xBC, 0x63, 0x98, 0xEA, + 0xCA, 0x41, 0x34, 0xA8, 0x10, 0x16, 0xF9, 0x3D}}; + +const PKA_EccParam512 BrainpoolP512R1_order = {.byte = {0x69, 0x00, 0xA9, 0x9C, 0x82, 0x96, 0x87, 0xB5, + 0xDD, 0xDA, 0x5D, 0x08, 0x81, 0xD3, 0xB1, 0x1D, + 0x47, 0x10, 0xAC, 0x7F, 0x19, 0x61, 0x86, 0x41, + 0x19, 0x26, 0xA9, 0x4C, 0x41, 0x5C, 0x3E, 0x55, + 0x70, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6, + 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB, + 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F, + 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}}; + +//***************************************************************************** +// +// Curve25519 constants in little endian format. byte[0] is the least +// significant byte and byte[Curve25519_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 Curve25519_generator = { + .x = {.byte = {0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}, + .y = {.byte = {0xd9, 0xd3, 0xce, 0x7e, 0xa2, 0xc5, 0xe9, 0x29, + 0xb2, 0x61, 0x7c, 0x6d, 0x7e, 0x4d, 0x3d, 0x92, + 0x4c, 0xd1, 0x48, 0x77, 0x2c, 0xdd, 0x1e, 0xe0, + 0xb4, 0x86, 0xa0, 0xb8, 0xa1, 0x19, 0xae, 0x20}}, +}; + +const PKA_EccParam256 Curve25519_prime = {.byte = {0xed, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; + +const PKA_EccParam256 Curve25519_a = {.byte = {0x06, 0x6d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + +const PKA_EccParam256 Curve25519_b = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + +const PKA_EccParam256 Curve25519_order = {.byte = {0xb9, 0xdc, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58, + 0xd6, 0x9c, 0xf7, 0xa2, 0xde, 0xf9, 0xde, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + + +//***************************************************************************** +// +// Zeroize PKA RAM. Not threadsafe. +// +//***************************************************************************** +void PKAClearPkaRam(void){ + // Get initial state + uint32_t secdmaclkgr = HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR); + + // OR in zeroize bit + secdmaclkgr |= PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N; + + // Start zeroization + HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr; + + // Wait 256 cycles for PKA RAM to be cleared + CPUdelay(256 / 4); + + // Turn off zeroization + HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr & (~PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N); +} + +//***************************************************************************** +// +// Write a PKA parameter to the PKA module, set required registers, and add an offset. +// +//***************************************************************************** +static uint32_t PKAWritePkaParam(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset) +{ + uint32_t i; + uint32_t *paramWordAlias = (uint32_t *)param; + // Take the floor of paramLength in 32-bit words + uint32_t paramLengthInWords = paramLength / sizeof(uint32_t); + + // Only copy data if it is specified. We may wish to simply allocate another buffer and get + // the required offset. + if (param) { + // Load the number in PKA RAM + for (i = 0; i < paramLengthInWords; i++) { + HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = paramWordAlias[i]; + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. The extra zeros at the end should not matter, as the large + // number is little-endian and thus has no effect. + // We could have correctly calculated ceiling(paramLength / sizeof(uint32_t)) above. + // However, we would not have been able to zero-out the extra few most significant + // bytes of the most significant word. That would have resulted in doing maths operations + // on whatever follows param in RAM. + if (paramLength % sizeof(uint32_t)) { + uint32_t temp = 0; + uint8_t j; + + // Load the entire word line of the param remainder + temp = paramWordAlias[i]; + + // Zero-out all bytes beyond the end of the param + for (j = paramLength % sizeof(uint32_t); j < sizeof(uint32_t); j++) { + ((uint8_t *)&temp)[j] = 0; + } + + HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = temp; + + // Increment paramLengthInWords since we take the ceiling of length / sizeof(uint32_t) + paramLengthInWords++; + } + } + + // Update the A, B, C, or D pointer with the offset address of the PKA RAM location + // where the number will be stored. + switch (ptrRegOffset) { + case PKA_O_APTR: + HWREG(PKA_BASE + PKA_O_APTR) = paramOffset >> 2; + HWREG(PKA_BASE + PKA_O_ALENGTH) = paramLengthInWords; + break; + case PKA_O_BPTR: + HWREG(PKA_BASE + PKA_O_BPTR) = paramOffset >> 2; + HWREG(PKA_BASE + PKA_O_BLENGTH) = paramLengthInWords; + break; + case PKA_O_CPTR: + HWREG(PKA_BASE + PKA_O_CPTR) = paramOffset >> 2; + break; + case PKA_O_DPTR: + HWREG(PKA_BASE + PKA_O_DPTR) = paramOffset >> 2; + break; + } + + // Ensure 8-byte alignment of next parameter. + // Returns the offset for the next parameter. + return paramOffset + sizeof(uint32_t) * (paramLengthInWords + (paramLengthInWords % 2)); +} + +//***************************************************************************** +// +// Write a PKA parameter to the PKA module but return a larger offset. +// +//***************************************************************************** +static uint32_t PKAWritePkaParamExtraOffset(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset) +{ + // Ensure 16-byte alignment. + return (sizeof(uint32_t) * 2) + PKAWritePkaParam(param, paramLength, paramOffset, ptrRegOffset); +} + +//***************************************************************************** +// +// Writes the result of a large number arithmetic operation to a provided buffer. +// +//***************************************************************************** +static uint32_t PKAGetBigNumResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + uint32_t mswOffset; + uint32_t lswOffset; + uint32_t lengthInWords; + uint32_t i; + uint32_t *resultWordAlias = (uint32_t *)resultBuf; + + // Check the arguments. + ASSERT(resultBuf); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Get the MSW register value. + mswOffset = HWREG(PKA_BASE + PKA_O_MSW); + + // If the result vector is zero, write back one zero byte so the caller does not need + // to handle a special error for the perhaps valid result of zero. + // They will only get the error status if they do not provide a buffer + if (mswOffset & PKA_MSW_RESULT_IS_ZERO_M) { + if (*resultLength){ + if(resultBuf){ + resultBuf[0] = 0; + } + + *resultLength = 1; + + return PKA_STATUS_SUCCESS; + } + else { + return PKA_STATUS_BUF_UNDERFLOW; + } + } + + // Get the length of the result + mswOffset = ((mswOffset & PKA_MSW_MSW_ADDRESS_M) + 1); + lswOffset = ((resultPKAMemAddr - PKA_RAM_BASE) >> 2); + + if (mswOffset >= lswOffset) { + lengthInWords = mswOffset - lswOffset; + } + else { + return PKA_STATUS_RESULT_ADDRESS_INCORRECT; + } + + // Check if the provided buffer length is adequate to store the result data. + if (*resultLength < lengthInWords * sizeof(uint32_t)) { + return PKA_STATUS_BUF_UNDERFLOW; + } + + // Copy the resultant length. + *resultLength = lengthInWords * sizeof(uint32_t); + + + if (resultBuf) { + // Copy the result into the resultBuf. + for (i = 0; i < lengthInWords; i++) { + resultWordAlias[i]= HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + } + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Retrieve the result of a modulo operation or the remainder of a division. +// +//***************************************************************************** +static uint32_t PKAGetBigNumResultRemainder(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + uint32_t regMSWVal; + uint32_t lengthInWords; + uint32_t i; + uint32_t *resultWordAlias = (uint32_t *)resultBuf; + + // Check the arguments. + ASSERT(resultBuf); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Get the MSW register value. + regMSWVal = HWREG(PKA_BASE + PKA_O_DIVMSW); + + // If the result vector is zero, write back one zero byte so the caller does not need + // to handle a special error for the perhaps valid result of zero. + // They will only get the error status if they do not provide a buffer + if (regMSWVal & PKA_DIVMSW_RESULT_IS_ZERO_M) { + if (*resultLength){ + if(resultBuf){ + resultBuf[0] = 0; + } + + *resultLength = 1; + + return PKA_STATUS_SUCCESS; + } + else { + return PKA_STATUS_BUF_UNDERFLOW; + } + } + + // Get the length of the result + lengthInWords = ((regMSWVal & PKA_DIVMSW_MSW_ADDRESS_M) + 1) - ((resultPKAMemAddr - PKA_RAM_BASE) >> 2); + + // Check if the provided buffer length is adequate to store the result data. + if (*resultLength < lengthInWords * sizeof(uint32_t)) { + return PKA_STATUS_BUF_UNDERFLOW; + } + + // Copy the resultant length. + *resultLength = lengthInWords * sizeof(uint32_t); + + if (resultBuf) { + // Copy the result into the resultBuf. + for (i = 0; i < lengthInWords; i++) { + resultWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + } + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Writes the resultant curve point of an ECC operation to the provided buffer. +// +//***************************************************************************** +static uint32_t PKAGetECCResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + uint32_t i = 0; + uint32_t *xWordAlias = (uint32_t *)curvePointX; + uint32_t *yWordAlias = (uint32_t *)curvePointY; + uint32_t lengthInWordsCeiling = 0; + + // Check for the arguments. + ASSERT(curvePointX); + ASSERT(curvePointY); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is completed. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + if (HWREG(PKA_BASE + PKA_O_SHIFT)) { + return PKA_STATUS_FAILURE; + } + + // Check to make sure that the result vector is not the point at infinity. + if (HWREG(PKA_BASE + PKA_O_MSW) & PKA_MSW_RESULT_IS_ZERO) { + return PKA_STATUS_POINT_AT_INFINITY; + } + + if (curvePointX != NULL) { + // Copy the x co-ordinate value of the result from vector D into + // the curvePoint. + for (i = 0; i < (length / sizeof(uint32_t)); i++) { + xWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. + if (length % sizeof(uint32_t)) { + uint32_t temp = 0; + uint8_t j; + + // Load the entire word line of the coordinate remainder + temp = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + + // Write all remaining bytes to the coordinate + for (j = 0; j < length % sizeof(uint32_t); j++) { + curvePointX[i * sizeof(uint32_t) + j] = ((uint8_t *)&temp)[j]; + } + + } + } + + lengthInWordsCeiling = (length % sizeof(uint32_t)) ? length / sizeof(uint32_t) + 1 : length / sizeof(uint32_t); + + resultPKAMemAddr += sizeof(uint32_t) * (2 + lengthInWordsCeiling + (lengthInWordsCeiling % 2)); + + if (curvePointY != NULL) { + // Copy the y co-ordinate value of the result from vector D into + // the curvePoint. + for (i = 0; i < (length / sizeof(uint32_t)); i++) { + yWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. + if (length % sizeof(uint32_t)) { + uint32_t temp = 0; + uint8_t j; + + // Load the entire word line of the coordinate remainder + temp = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + + // Write all remaining bytes to the coordinate + for (j = 0; j < length % sizeof(uint32_t); j++) { + curvePointY[i * sizeof(uint32_t) + j] = ((uint8_t *)&temp)[j]; + } + } + } + + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Provides the PKA operation status. +// +//***************************************************************************** +uint32_t PKAGetOpsStatus(void) +{ + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN_M) { + return PKA_STATUS_OPERATION_BUSY; + } + else { + return PKA_STATUS_OPERATION_RDY; + } +} + +//***************************************************************************** +// +// Check if an array consists only of zeros. +// +//***************************************************************************** +bool PKAArrayAllZeros(const uint8_t *array, uint32_t arrayLength) +{ + uint32_t i; + uint8_t arrayBits = 0; + + // We could speed things up by comparing word-wise rather than byte-wise. + // However, this extra overhead is inconsequential compared to running an + // actual PKA operation. Especially ECC operations. + for (i = 0; i < arrayLength; i++) { + arrayBits |= array[i]; + } + + if (arrayBits) { + return false; + } + else { + return true; + } + +} + +//***************************************************************************** +// +// Fill an array with zeros +// +//***************************************************************************** +void PKAZeroOutArray(const uint8_t *array, uint32_t arrayLength) +{ + uint32_t i; + // Take the floor of paramLength in 32-bit words + uint32_t arrayLengthInWords = arrayLength / sizeof(uint32_t); + + // Zero-out the array word-wise until i >= arrayLength + for (i = 0; i < arrayLengthInWords * sizeof(uint32_t); i += 4) { + HWREG(array + i) = 0; + } + + // If i != arrayLength, there are some remaining bytes to zero-out + if (arrayLength % sizeof(uint32_t)) { + // Subtract 4 from i, since i has already overshot the array + for (i -= 4; i < arrayLength; i++) { + HWREGB(array + i * sizeof(uint32_t)); + } + } +} + +//***************************************************************************** +// +// Start the big number modulus operation. +// +//***************************************************************************** +uint32_t PKABigNumModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum); + ASSERT(modulus); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(modulus, modulusLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Start the PKCP modulo operation by setting the PKA Function register. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MODULO); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the big number modulus operation. +// +//***************************************************************************** +uint32_t PKABigNumModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr) +{ + // Zero-out array in case modulo result is shorter than length + PKAZeroOutArray(resultBuf, length); + + return PKAGetBigNumResultRemainder(resultBuf, &length, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideStart(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(dividend); + ASSERT(divisor); + ASSERT(resultQuotientMemAddr); + ASSERT(resultRemainderMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(dividend, dividendLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(divisor, divisorLength, offset, PKA_O_BPTR); + + // Copy the remainder result vector address location. + if (resultRemainderMemAddr) { + *resultRemainderMemAddr = PKA_RAM_BASE + offset; + } + + // The remainder cannot ever be larger than the divisor. It should fit inside + // a buffer of that size. + offset = PKAWritePkaParamExtraOffset(0, divisorLength, offset, PKA_O_CPTR); + + // Copy the remainder result vector address location. + if (resultQuotientMemAddr) { + *resultQuotientMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the quotient location in PKA RAM + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Start the PKCP modulo operation by setting the PKA Function register. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_DIVIDE); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the quotient of the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideGetQuotient(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr) +{ + return PKAGetBigNumResult(resultBuf, length, resultQuotientMemAddr); +} + +//***************************************************************************** +// +// Get the remainder of the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideGetRemainder(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr) +{ + return PKAGetBigNumResultRemainder(resultBuf, length, resultQuotientMemAddr); +} + + +//***************************************************************************** +// +// Start the comparison of two big numbers. +// +//***************************************************************************** +uint32_t PKABigNumCmpStart(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum1); + ASSERT(bigNum2); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum1, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(bigNum2, length, offset, PKA_O_BPTR); + + // Set the PKA Function register for the Compare operation + // and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_COMPARE); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the comparison operation of two big numbers. +// +//***************************************************************************** +uint32_t PKABigNumCmpGetResult(void) +{ + uint32_t status; + + // verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Check the COMPARE register. + switch(HWREG(PKA_BASE + PKA_O_COMPARE)) { + case PKA_COMPARE_A_EQUALS_B: + status = PKA_STATUS_EQUAL; + break; + + case PKA_COMPARE_A_GREATER_THAN_B: + status = PKA_STATUS_A_GREATER_THAN_B; + break; + + case PKA_COMPARE_A_LESS_THAN_B: + status = PKA_STATUS_A_LESS_THAN_B; + break; + + default: + status = PKA_STATUS_FAILURE; + break; + } + + return status; +} + +//***************************************************************************** +// +// Start the big number inverse modulo operation. +// +//***************************************************************************** +uint32_t PKABigNumInvModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum); + ASSERT(modulus); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(modulus, modulusLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // set the PKA function to InvMod operation and the start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = 0x0000F000; + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the big number inverse modulo operation. +// +//***************************************************************************** +uint32_t PKABigNumInvModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr) +{ + // Zero-out array in case modulo result is shorter than length + PKAZeroOutArray(resultBuf, length); + + return PKAGetBigNumResult(resultBuf, &length, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the big number multiplication. +// +//***************************************************************************** +uint32_t PKABigNumMultiplyStart(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(multiplicand); + ASSERT(multiplier); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(multiplicand, multiplicandLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(multiplier, multiplierLength, offset, PKA_O_BPTR); + + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the PKA function to the multiplication and start it. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MULTIPLY); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the results of the big number multiplication. +// +//***************************************************************************** +uint32_t PKABigNumMultGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the addition of two big number. +// +//***************************************************************************** +uint32_t PKABigNumAddStart(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for arguments. + ASSERT(bigNum1); + ASSERT(bigNum2); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum1, bigNum1Length, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(bigNum2, bigNum2Length, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the function for the add operation and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_ADD); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the addition operation on two big number. +// +//***************************************************************************** +uint32_t PKABigNumSubGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the addition of two big number. +// +//***************************************************************************** +uint32_t PKABigNumSubStart(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for arguments. + ASSERT(minuend); + ASSERT(subtrahend); + ASSERT(resultPKAMemAddr); + + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(minuend, minuendLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(subtrahend, subtrahendLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the function for the add operation and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_SUBTRACT); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the addition operation on two big number. +// +//***************************************************************************** +uint32_t PKABigNumAddGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + + +//***************************************************************************** +// +// Start ECC Multiplication. +// +//***************************************************************************** +uint32_t PKAEccMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(scalar); + ASSERT(curvePointX); + ASSERT(curvePointY); + ASSERT(prime); + ASSERT(a); + ASSERT(b); + ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t)); + ASSERT(resultPKAMemAddr); + + // Make sure no PKA operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + offset = PKAWritePkaParamExtraOffset(b, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR); + offset = PKAWritePkaParamExtraOffset(curvePointY, length, offset, PKA_NO_POINTER_REG); + + // Update the result location. + // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity + if (resultPKAMemAddr) { + *resultPKAMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA function to ECC-MULT and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x05 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Start ECC Montgomery Multiplication. +// +//***************************************************************************** +uint32_t PKAEccMontgomeryMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(scalar); + ASSERT(curvePointX); + ASSERT(prime); + ASSERT(a); + ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t)); + ASSERT(resultPKAMemAddr); + + // Make sure no PKA operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR); + + // Update the result location. + // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity + if (resultPKAMemAddr) { + *resultPKAMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA function to Montgomery ECC-MULT and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x02 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Get the result of ECC Multiplication +// +//***************************************************************************** +uint32_t PKAEccMultiplyGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length); +} + +//***************************************************************************** +// +// Start the ECC Addition. +// +//***************************************************************************** +uint32_t PKAEccAddStart(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(curvePoint1X); + ASSERT(curvePoint1Y); + ASSERT(curvePoint2X); + ASSERT(curvePoint2Y); + ASSERT(prime); + ASSERT(a); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParamExtraOffset(curvePoint1X, length, offset, PKA_O_APTR); + offset = PKAWritePkaParamExtraOffset(curvePoint1Y, length, offset, PKA_NO_POINTER_REG); + + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePoint2X, length, offset, PKA_O_CPTR); + offset = PKAWritePkaParamExtraOffset(curvePoint2Y, length, offset, PKA_NO_POINTER_REG); + + // Copy the result vector location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA Function to ECC-ADD and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION ) = PKA_FUNCTION_RUN_M | (0x03 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the ECC Addition +// +//***************************************************************************** +uint32_t PKAEccAddGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length); +} + +//***************************************************************************** +// +// Verify a public key against the supplied elliptic curve equation +// +//***************************************************************************** +uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length) +{ + uint32_t pkaResult; + uint32_t resultAddress; + uint32_t resultLength; + uint8_t *scratchBuffer = (uint8_t *)(PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE / 2); + uint8_t *scratchBuffer2 = scratchBuffer + 512; + + + // Verify X in range [0, prime - 1] + PKABigNumCmpStart(curvePointX, + prime, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return PKA_STATUS_X_LARGER_THAN_PRIME; + } + + // Verify Y in range [0, prime - 1] + PKABigNumCmpStart(curvePointY, + prime, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return PKA_STATUS_Y_LARGER_THAN_PRIME; + } + + // Verify point on curve + // Short-Weierstrass equation: Y ^ 2 = X ^3 + a * X + b mod P + // Reduced: Y ^ 2 = X * (X ^ 2 + a) + b + + // tmp = X ^ 2 + PKABigNumMultiplyStart(curvePointX, length, curvePointX, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp += a + PKABigNumAddStart(scratchBuffer, resultLength, a, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp *= x + PKABigNumMultiplyStart(scratchBuffer, resultLength, curvePointX, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp += b + PKABigNumAddStart(scratchBuffer, resultLength, b, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + + // tmp2 = tmp % prime to ensure we have no fraction in the division. + // The number will only shrink from here on out. + PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + // If the result is not a multiple of the word-length, the PKA HW will round up + // because it deals in words only. That means that using 'length' directly + // would cause and underflow, since length refers to the actual length in bytes of + // the curve parameters while the PKA HW reports that rounded up to the next + // word boundary. + // Use 200 as the resultLength instead since we are copying to the scratch buffer + // anyway. + // Practically, this only happens with curves such as NIST-P521 that are not word + // multiples. + resultLength = 200; + pkaResult = PKABigNumModGetResult(scratchBuffer2, resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp = y^2 + PKABigNumMultiplyStart(curvePointY, length, curvePointY, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp %= prime + PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + // If the result is not a multiple of the word-length, the PKA HW will round up + // because it deals in words only. That means that using 'length' directly + // would cause and underflow, since length refers to the actual length in bytes of + // the curve parameters while the PKA HW reports that rounded up to the next + // word boundary. + // Use 200 as the resultLength instead since we are copying to the scratch buffer + // anyway. + // Practically, this only happens with curves such as NIST-P521 that are not word + // multiples. + resultLength = 200; + pkaResult = PKABigNumModGetResult(scratchBuffer, resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp ?= tmp2 + PKABigNumCmpStart(scratchBuffer, + scratchBuffer2, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_EQUAL) { + return PKA_STATUS_POINT_NOT_ON_CURVE; + } + else { + return PKA_STATUS_SUCCESS; + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka.h new file mode 100644 index 0000000..785e5fe --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka.h @@ -0,0 +1,1455 @@ +/****************************************************************************** +* Filename: pka.h +* Revised: 2018-07-19 15:07:05 +0200 (Thu, 19 Jul 2018) +* Revision: 52294 +* +* Description: PKA header file. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup pka_api +//! @{ +// +//***************************************************************************** + +#ifndef __PKA_H__ +#define __PKA_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_pka.h" +#include "../inc/hw_pka_ram.h" +#include "interrupt.h" +#include "sys_ctrl.h" +#include "debug.h" +#include + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define PKAClearPkaRam NOROM_PKAClearPkaRam + #define PKAGetOpsStatus NOROM_PKAGetOpsStatus + #define PKAArrayAllZeros NOROM_PKAArrayAllZeros + #define PKAZeroOutArray NOROM_PKAZeroOutArray + #define PKABigNumModStart NOROM_PKABigNumModStart + #define PKABigNumModGetResult NOROM_PKABigNumModGetResult + #define PKABigNumDivideStart NOROM_PKABigNumDivideStart + #define PKABigNumDivideGetQuotient NOROM_PKABigNumDivideGetQuotient + #define PKABigNumDivideGetRemainder NOROM_PKABigNumDivideGetRemainder + #define PKABigNumCmpStart NOROM_PKABigNumCmpStart + #define PKABigNumCmpGetResult NOROM_PKABigNumCmpGetResult + #define PKABigNumInvModStart NOROM_PKABigNumInvModStart + #define PKABigNumInvModGetResult NOROM_PKABigNumInvModGetResult + #define PKABigNumMultiplyStart NOROM_PKABigNumMultiplyStart + #define PKABigNumMultGetResult NOROM_PKABigNumMultGetResult + #define PKABigNumAddStart NOROM_PKABigNumAddStart + #define PKABigNumAddGetResult NOROM_PKABigNumAddGetResult + #define PKABigNumSubStart NOROM_PKABigNumSubStart + #define PKABigNumSubGetResult NOROM_PKABigNumSubGetResult + #define PKAEccMultiplyStart NOROM_PKAEccMultiplyStart + #define PKAEccMontgomeryMultiplyStart NOROM_PKAEccMontgomeryMultiplyStart + #define PKAEccMultiplyGetResult NOROM_PKAEccMultiplyGetResult + #define PKAEccAddStart NOROM_PKAEccAddStart + #define PKAEccAddGetResult NOROM_PKAEccAddGetResult + #define PKAEccVerifyPublicKeyWeierstrassStart NOROM_PKAEccVerifyPublicKeyWeierstrassStart +#endif + + + + +//***************************************************************************** +// +// Function return values +// +//***************************************************************************** +#define PKA_STATUS_SUCCESS 0 //!< Success +#define PKA_STATUS_FAILURE 1 //!< Failure +#define PKA_STATUS_INVALID_PARAM 2 //!< Invalid parameter +#define PKA_STATUS_BUF_UNDERFLOW 3 //!< Buffer underflow +#define PKA_STATUS_RESULT_0 4 //!< Result is all zeros +#define PKA_STATUS_A_GREATER_THAN_B 5 //!< Big number compare return status if the first big number is greater than the second. +#define PKA_STATUS_A_LESS_THAN_B 6 //!< Big number compare return status if the first big number is less than the second. +#define PKA_STATUS_EQUAL 7 //!< Big number compare return status if the first big number is equal to the second. +#define PKA_STATUS_OPERATION_BUSY 8 //!< PKA operation is in progress. +#define PKA_STATUS_OPERATION_RDY 9 //!< No PKA operation is in progress. +#define PKA_STATUS_LOCATION_IN_USE 10 //!< Location in PKA RAM is not available +#define PKA_STATUS_X_ZERO 11 //!< X coordinate of public key is 0 +#define PKA_STATUS_Y_ZERO 12 //!< Y coordinate of public key is 0 +#define PKA_STATUS_X_LARGER_THAN_PRIME 13 //!< X coordinate of public key is larger than the curve prime +#define PKA_STATUS_Y_LARGER_THAN_PRIME 14 //!< Y coordinate of public key is larger than the curve prime +#define PKA_STATUS_POINT_NOT_ON_CURVE 15 //!< The public key is not on the specified elliptic curve +#define PKA_STATUS_RESULT_ADDRESS_INCORRECT 16 //!< The address of the result passed into one of the PKA*GetResult functions is incorrect +#define PKA_STATUS_POINT_AT_INFINITY 17 //!< The ECC operation resulted in the point at infinity + + +//***************************************************************************** +// +// Length in bytes of NISTP224 parameters. +// +//***************************************************************************** +#define NISTP224_PARAM_SIZE_BYTES 28 + +//***************************************************************************** +// +// Length in bytes of NISTP256 parameters. +// +//***************************************************************************** +#define NISTP256_PARAM_SIZE_BYTES 32 + +//***************************************************************************** +// +// Length in bytes of NISTP384 parameters. +// +//***************************************************************************** +#define NISTP384_PARAM_SIZE_BYTES 48 + +//***************************************************************************** +// +// Length in bytes of NISTP521 parameters. +// +//***************************************************************************** +#define NISTP521_PARAM_SIZE_BYTES 66 + +//***************************************************************************** +// +// Length in bytes of BrainpoolP256R1 parameters. +// +//***************************************************************************** +#define BrainpoolP256R1_PARAM_SIZE_BYTES 32 + +//***************************************************************************** +// +// Length in bytes of BrainpoolP384R1 parameters. +// +//***************************************************************************** +#define BrainpoolP384R1_PARAM_SIZE_BYTES 48 + +//***************************************************************************** +// +// Length in bytes of BrainpoolP512R1 parameters. +// +//***************************************************************************** +#define BrainpoolP512R1_PARAM_SIZE_BYTES 64 + +//***************************************************************************** +// +// Length in bytes of Curve25519 parameters. +// +//***************************************************************************** +#define Curve25519_PARAM_SIZE_BYTES 32 + +//***************************************************************************** +// +// Union for parameters that forces 32-bit alignment on the byte array. +// +//***************************************************************************** +typedef union { + uint8_t byte[28]; + uint32_t word[28 / sizeof(uint32_t)]; +} PKA_EccParam224; + +typedef union { + uint8_t byte[32]; + uint32_t word[32 / sizeof(uint32_t)]; +} PKA_EccParam256; + +typedef union { + uint8_t byte[48]; + uint32_t word[48 / sizeof(uint32_t)]; +} PKA_EccParam384; + +typedef union { + uint8_t byte[64]; + uint32_t word[64 / sizeof(uint32_t)]; +} PKA_EccParam512; + +typedef union { + uint8_t byte[68]; + uint32_t word[68 / sizeof(uint32_t)]; +} PKA_EccParam521; + +//***************************************************************************** +// +// Struct to keep points in that forces adjacency of X and Y coordinates in +// memmory. +// +//***************************************************************************** + + +typedef struct PKA_EccPoint224_ { + PKA_EccParam224 x; + PKA_EccParam224 y; +} PKA_EccPoint224; + +typedef struct PKA_EccPoint256_ { + PKA_EccParam256 x; + PKA_EccParam256 y; +} PKA_EccPoint256; + +typedef struct PKA_EccPoint384_ { + PKA_EccParam384 x; + PKA_EccParam384 y; +} PKA_EccPoint384; + +typedef struct PKA_EccPoint512_ { + PKA_EccParam512 x; + PKA_EccParam512 y; +} PKA_EccPoint512; + +typedef struct PKA_EccPoint521_ { + PKA_EccParam521 x; + PKA_EccParam521 y; +} PKA_EccPoint521; + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the NISTP224 curve. +// +//***************************************************************************** +extern const PKA_EccPoint224 NISTP224_generator; + +//***************************************************************************** +// +//! \brief Prime of the NISTP224 curve. +// +//***************************************************************************** +extern const PKA_EccParam224 NISTP224_prime; + + +//***************************************************************************** +// +//! \brief a constant of the NISTP224 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam224 NISTP224_a; + + +//***************************************************************************** +// +//! \brief b constant of the NISTP224 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam224 NISTP224_b; + + +//***************************************************************************** +// +//! \brief Order of the NISTP224 curve. +// +//***************************************************************************** +extern const PKA_EccParam224 NISTP224_order; + + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the NISTP256 curve. +// +//***************************************************************************** +extern const PKA_EccPoint256 NISTP256_generator; + +//***************************************************************************** +// +//! \brief Prime of the NISTP256 curve. +// +//***************************************************************************** +extern const PKA_EccParam256 NISTP256_prime; + + +//***************************************************************************** +// +//! \brief a constant of the NISTP256 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam256 NISTP256_a; + + +//***************************************************************************** +// +//! \brief b constant of the NISTP256 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam256 NISTP256_b; + + +//***************************************************************************** +// +//! \brief Order of the NISTP256 curve. +// +//***************************************************************************** +extern const PKA_EccParam256 NISTP256_order; + + + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the NISTP384 curve. +// +//***************************************************************************** +extern const PKA_EccPoint384 NISTP384_generator; + +//***************************************************************************** +// +//! \brief Prime of the NISTP384 curve. +// +//***************************************************************************** +extern const PKA_EccParam384 NISTP384_prime; + + +//***************************************************************************** +// +//! \brief a constant of the NISTP384 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam384 NISTP384_a; + + +//***************************************************************************** +// +//! \brief b constant of the NISTP384 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam384 NISTP384_b; + + +//***************************************************************************** +// +//! \brief Order of the NISTP384 curve. +// +//***************************************************************************** +extern const PKA_EccParam384 NISTP384_order; + + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the NISTP521 curve. +// +//***************************************************************************** +extern const PKA_EccPoint521 NISTP521_generator; + +//***************************************************************************** +// +//! \brief Prime of the NISTP521 curve. +// +//***************************************************************************** +extern const PKA_EccParam521 NISTP521_prime; + + +//***************************************************************************** +// +//! \brief a constant of the NISTP521 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam521 NISTP521_a; + + +//***************************************************************************** +// +//! \brief b constant of the NISTP521 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam521 NISTP521_b; + + +//***************************************************************************** +// +//! \brief Order of the NISTP521 curve. +// +//***************************************************************************** +extern const PKA_EccParam521 NISTP521_order; + + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the BrainpoolP256R1 curve. +// +//***************************************************************************** +extern const PKA_EccPoint256 BrainpoolP256R1_generator; + +//***************************************************************************** +// +//! \brief Prime of the BrainpoolP256R1 curve. +// +//***************************************************************************** +extern const PKA_EccParam256 BrainpoolP256R1_prime; + + +//***************************************************************************** +// +//! \brief a constant of the BrainpoolP256R1 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam256 BrainpoolP256R1_a; + + +//***************************************************************************** +// +//! \brief b constant of the BrainpoolP256R1 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam256 BrainpoolP256R1_b; + + +//***************************************************************************** +// +//! \brief Order of the BrainpoolP256R1 curve. +// +//***************************************************************************** +extern const PKA_EccParam256 BrainpoolP256R1_order; + + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the BrainpoolP384R1 curve. +// +//***************************************************************************** +extern const PKA_EccPoint384 BrainpoolP384R1_generator; + +//***************************************************************************** +// +//! \brief Prime of the BrainpoolP384R1 curve. +// +//***************************************************************************** +extern const PKA_EccParam384 BrainpoolP384R1_prime; + + +//***************************************************************************** +// +//! \brief a constant of the BrainpoolP384R1 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam384 BrainpoolP384R1_a; + + +//***************************************************************************** +// +//! \brief b constant of the BrainpoolP384R1 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam384 BrainpoolP384R1_b; + + +//***************************************************************************** +// +//! \brief Order of the BrainpoolP384R1 curve. +// +//***************************************************************************** +extern const PKA_EccParam384 BrainpoolP384R1_order; + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the BrainpoolP512R1 curve. +// +//***************************************************************************** +extern const PKA_EccPoint512 BrainpoolP512R1_generator; + +//***************************************************************************** +// +//! \brief Prime of the BrainpoolP512R1 curve. +// +//***************************************************************************** +extern const PKA_EccParam512 BrainpoolP512R1_prime; + + +//***************************************************************************** +// +//! \brief a constant of the BrainpoolP512R1 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam512 BrainpoolP512R1_a; + + +//***************************************************************************** +// +//! \brief b constant of the BrainpoolP512R1 curve when expressed in short +//! Weierstrass form (y^3 = x^2 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam512 BrainpoolP512R1_b; + + +//***************************************************************************** +// +//! \brief Order of the BrainpoolP512R1 curve. +// +//***************************************************************************** +extern const PKA_EccParam512 BrainpoolP512R1_order; + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the Curve25519 curve. +// +//***************************************************************************** +extern const PKA_EccPoint256 Curve25519_generator; + +//***************************************************************************** +// +//! \brief Prime of the Curve25519 curve. +// +//***************************************************************************** +extern const PKA_EccParam256 Curve25519_prime; + + +//***************************************************************************** +// +//! \brief a constant of the Curve25519 curve when expressed in Montgomery +//! form (By^2 = x^3 + a*x^2 + x). +// +//***************************************************************************** +extern const PKA_EccParam256 Curve25519_a; + + +//***************************************************************************** +// +//! \brief b constant of the Curve25519 curve when expressed in Montgomery +//! form (By^2 = x^3 + a*x^2 + x). +// +//***************************************************************************** +extern const PKA_EccParam256 Curve25519_b; + + +//***************************************************************************** +// +//! \brief Order of the Curve25519 curve. +// +//***************************************************************************** +extern const PKA_EccParam256 Curve25519_order; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Zeroizes PKA RAM. +//! +//! This function uses the zeroization function in PRCM to clear the PKA RAM. +// +//***************************************************************************** +extern void PKAClearPkaRam(void); + +//***************************************************************************** +// +//! \brief Gets the PKA operation status. +//! +//! This function gets information on whether any PKA operation is in +//! progress or not. This function allows to check the PKA operation status +//! before starting any new PKA operation. +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA operation is in progress. +//! - \ref PKA_STATUS_OPERATION_RDY if the PKA operation is not in progress. +// +//***************************************************************************** +extern uint32_t PKAGetOpsStatus(void); + +//***************************************************************************** +// +//! \brief Checks whether and array only consists of zeros +//! +//! \param [in] array is the array to check. +//! +//! \param [in] arrayLength is the length of the array. +//! +//! \return Returns true if the array contains only zeros and false if one +//! or more bits are set. +// +//***************************************************************************** +extern bool PKAArrayAllZeros(const uint8_t *array, uint32_t arrayLength); + +//***************************************************************************** +// +//! \brief Zeros-out an array +//! +//! \param [in] array is the array to zero-out. +//! +//! \param [in] arrayLength is the length of the array. +// +//***************************************************************************** +extern void PKAZeroOutArray(const uint8_t *array, uint32_t arrayLength); + +//***************************************************************************** +// +//! \brief Starts a big number modulus operation. +//! +//! This function starts the modulo operation on the big number \c bigNum +//! using the divisor \c modulus. The PKA RAM location where the result +//! will be available is stored in \c resultPKAMemAddr. +//! +//! \param [in] bigNum is the pointer to the big number on which modulo operation +//! needs to be carried out. +//! +//! \param [in] bigNumLength is the size of the big number \c bigNum in bytes. +//! +//! \param [in] modulus is the pointer to the divisor. +//! +//! \param [in] modulusLength is the size of the divisor \c modulus in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY, if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumModGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Gets the result of the big number modulus operation. +//! +//! This function gets the result of the big number modulus operation which was +//! previously started using the function PKABigNumModStart(). +//! The function will zero-out \c resultBuf prior to copying in the result of +//! the modulo operation. +//! +//! \param [out] resultBuf is the pointer to buffer where the result needs to +//! be stored. +//! +//! \param [in] length is the size of the provided buffer in bytes. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKABigNumModStart(). +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the \c length is less than the length +//! of the result. +//! +//! \sa PKABigNumModStart() +// +//***************************************************************************** +extern uint32_t PKABigNumModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Starts a big number divide operation. +//! +//! This function starts the dive operation on the big number \c bigNum +//! using the \c divisor. The PKA RAM location where the result +//! will be available is stored in \c resultPKAMemAddr. +//! +//! \param [in] dividend is the pointer to the big number to be divided. +//! +//! \param [in] dividendLength is the size of the big number \c dividend in bytes. +//! +//! \param [in] divisor is the pointer to the divisor. +//! +//! \param [in] divisorLength is the size of the \c divisor in bytes. +//! +//! \param [out] resultQuotientMemAddr is the pointer to the quotient vector location +//! which will be set by this function. +//! +//! \param [out] resultRemainderMemAddr is the pointer to the remainder vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY, if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumDivideGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumDivideStart(const uint8_t *dividend, + uint32_t dividendLength, + const uint8_t *divisor, + uint32_t divisorLength, + uint32_t *resultQuotientMemAddr, + uint32_t *resultRemainderMemAddr); + +//***************************************************************************** +// +//! \brief Gets the quotient of the big number divide operation. +//! +//! This function gets the quotient of the big number divide operation which was +//! previously started using the function PKABigNumDivideStart(). +//! +//! \param [out] resultBuf is the pointer to buffer where the result needs to +//! be stored. +//! +//! \param [in] length is the size of the provided buffer in bytes. +//! +//! \param [in] resultQuotientMemAddr is the address of the result location which +//! was provided by the start function PKABigNumDivideStart(). +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the \c length is less than the length +//! of the result. +//! +//! \sa PKABigNumDivideStart() +// +//***************************************************************************** +extern uint32_t PKABigNumDivideGetQuotient(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr); + +//***************************************************************************** +// +//! \brief Gets the remainder of the big number divide operation. +//! +//! This function gets the remainder of the big number divide operation which was +//! previously started using the function PKABigNumDivideStart(). +//! +//! \param [out] resultBuf is the pointer to buffer where the result needs to +//! be stored. +//! +//! \param [in] length is the size of the provided buffer in bytes. +//! +//! \param [in] resultRemainderMemAddr is the address of the result location which +//! was provided by the start function PKABigNumDivideStart(). +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the \c length is less than the length +//! of the result. +//! +//! \sa PKABigNumDivideStart() +// +//***************************************************************************** +extern uint32_t PKABigNumDivideGetRemainder(uint8_t *resultBuf, uint32_t *length, uint32_t resultRemainderMemAddr); + +//***************************************************************************** +// +//! \brief Starts the comparison of two big numbers. +//! +//! This function starts the comparison of two big numbers pointed by +//! \c bigNum1 and \c bigNum2. +//! +//! \note \c bigNum1 and \c bigNum2 must have same size. +//! +//! \param [in] bigNum1 is the pointer to the first big number. +//! +//! \param [in] bigNum2 is the pointer to the second big number. +//! +//! \param [in] length is the size of the big numbers in bytes. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumCmpGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumCmpStart(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length); + +//***************************************************************************** +// +//! \brief Gets the result of the comparison operation of two big numbers. +//! +//! This function provides the results of the comparison of two big numbers +//! which was started using the PKABigNumCmpStart(). +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_OPERATION_BUSY if the operation is in progress. +//! - \ref PKA_STATUS_SUCCESS if the two big numbers are equal. +//! - \ref PKA_STATUS_A_GREATER_THAN_B if the first number is greater than the second. +//! - \ref PKA_STATUS_A_LESS_THAN_B if the first number is less than the second. +//! +//! \sa PKABigNumCmpStart() +// +//***************************************************************************** +extern uint32_t PKABigNumCmpGetResult(void); + +//***************************************************************************** +// +//! \brief Starts a big number inverse modulo operation. +//! +//! This function starts the inverse modulo operation on \c bigNum +//! using the divisor \c modulus. +//! +//! \param [in] bigNum is the pointer to the buffer containing the big number +//! (dividend). +//! +//! \param [in] bigNumLength is the size of the \c bigNum in bytes. +//! +//! \param [in] modulus is the pointer to the buffer containing the divisor. +//! +//! \param [in] modulusLength is the size of the divisor in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumInvModGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumInvModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr); + + +//***************************************************************************** +// +//! \brief Gets the result of the big number inverse modulo operation. +//! +//! This function gets the result of the big number inverse modulo operation +//! previously started using the function PKABigNumInvModStart(). +//! The function will zero-out \c resultBuf prior to copying in the result of +//! the inverse modulo operation. +//! +//! \param [out] resultBuf is the pointer to buffer where the result needs to be +//! stored. +//! +//! \param [in] length is the size of the provided buffer in bytes. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKABigNumInvModStart(). +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less +//! than the result. +//! +//! \sa PKABigNumInvModStart() +// +//***************************************************************************** +extern uint32_t PKABigNumInvModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr); + + +//***************************************************************************** +// +//! \brief Starts the multiplication of two big numbers. +//! +//! \param [in] multiplicand is the pointer to the buffer containing the big +//! number multiplicand. +//! +//! \param [in] multiplicandLength is the size of the multiplicand in bytes. +//! +//! \param [in] multiplier is the pointer to the buffer containing the big +//! number multiplier. +//! +//! \param [in] multiplierLength is the size of the multiplier in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumMultGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumMultiplyStart(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr); + + +//***************************************************************************** +// +//! \brief Gets the result of the big number multiplication. +//! +//! This function gets the result of the multiplication of two big numbers +//! operation previously started using the function PKABigNumMultiplyStart(). +//! +//! \param [out] resultBuf is the pointer to buffer where the result needs to be +//! stored. +//! +//! \param [in, out] resultLength is the address of the variable containing the length of the +//! buffer in bytes. After the operation, the actual length of the resultant is stored +//! at this address. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKABigNumMultiplyStart(). +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_FAILURE if the operation is not successful. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less +//! then the length of the result. +//! +//! \sa PKABigNumMultiplyStart() +// +//***************************************************************************** +extern uint32_t PKABigNumMultGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Starts the addition of two big numbers. +//! +//! \param [in] bigNum1 is the pointer to the buffer containing the first +//! big number. +//! +//! \param [in] bigNum1Length is the size of the first big number in bytes. +//! +//! \param [in] bigNum2 is the pointer to the buffer containing the second +//! big number. +//! +//! \param [in] bigNum2Length is the size of the second big number in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumAddGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumAddStart(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Gets the result of the addition operation on two big numbers. +//! +//! \param [out] resultBuf is the pointer to buffer where the result +//! needs to be stored. +//! +//! \param [in, out] resultLength is the address of the variable containing +//! the length of the buffer. After the operation the actual length of the +//! resultant is stored at this address. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKABigNumAddStart(). +//! +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_FAILURE if the operation is not successful. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less +//! then the length of the result. +//! +//! \sa PKABigNumAddStart() +// +//***************************************************************************** +extern uint32_t PKABigNumAddGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Starts the subtraction of one big number from another. +//! +//! \param [in] minuend is the pointer to the buffer containing the big number +//! to be subtracted from. +//! +//! \param [in] minuendLength is the size of the minuend in bytes. +//! +//! \param [in] subtrahend is the pointer to the buffer containing the big +//! number to subtract from the \c minuend. +//! +//! \param [in] subtrahendLength is the size of the subtrahend in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumSubGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumSubStart(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Gets the result of the subtraction operation on two big numbers. +//! +//! \param [out] resultBuf is the pointer to buffer where the result +//! needs to be stored. +//! +//! \param [in, out] resultLength is the address of the variable containing +//! the length of the buffer. After the operation the actual length of the +//! resultant is stored at this address. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKABigNumAddStart(). +//! +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_FAILURE if the operation is not successful. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less +//! then the length of the result. +//! +//! \sa PKABigNumSubStart() +// +//***************************************************************************** +extern uint32_t PKABigNumSubGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Starts ECC multiplication. +//! +//! \param [in] scalar is pointer to the buffer containing the scalar +//! value to be multiplied. +//! +//! \param [in] curvePointX is the pointer to the buffer containing the +//! X coordinate of the elliptic curve point to be multiplied. +//! The point must be on the given curve. +//! +//! \param [in] curvePointY is the pointer to the buffer containing the +//! Y coordinate of the elliptic curve point to be multiplied. +//! The point must be on the given curve. +//! +//! \param [in] prime is the prime of the curve. +//! +//! \param [in] a is the a constant of the curve when the curve equation is expressed +//! in short Weierstrass form (y^3 = x^2 + a*x + b). +//! +//! \param [in] b is the b constant of the curve when the curve equation is expressed +//! in short Weierstrass form (y^3 = x^2 + a*x + b). +//! +//! \param [in] length is the length of the curve parameters in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKAEccMultiplyGetResult() +// +//***************************************************************************** +extern uint32_t PKAEccMultiplyStart(const uint8_t *scalar, + const uint8_t *curvePointX, + const uint8_t *curvePointY, + const uint8_t *prime, + const uint8_t *a, + const uint8_t *b, + uint32_t length, + uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Starts ECC Montgomery multiplication. +//! +//! \param [in] scalar is pointer to the buffer containing the scalar +//! value to be multiplied. +//! +//! \param [in] curvePointX is the pointer to the buffer containing the +//! X coordinate of the elliptic curve point to be multiplied. +//! The point must be on the given curve. +//! +//! \param [in] prime is the prime of the curve. +//! +//! \param [in] a is the a constant of the curve when the curve equation is expressed +//! in short Weierstrass form (y^3 = x^2 + a*x + b). +//! +//! \param [in] length is the length of the curve parameters in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKAEccMultiplyGetResult() +// +//***************************************************************************** +extern uint32_t PKAEccMontgomeryMultiplyStart(const uint8_t *scalar, + const uint8_t *curvePointX, + const uint8_t *prime, + const uint8_t *a, + uint32_t length, + uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Gets the result of ECC multiplication +//! +//! This function gets the result of ECC point multiplication operation on the +//! EC point and the scalar value, previously started using the function +//! PKAEccMultiplyStart(). +//! +//! \param [out] curvePointX is the pointer to the structure where the X coordinate +//! of the resultant EC point will be stored. +//! +//! \param [out] curvePointY is the pointer to the structure where the Y coordinate +//! of the resultant EC point will be stored. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKAEccMultiplyStart(). +//! +//! \param [in] length is the length of the curve parameters in bytes. +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_FAILURE if the operation is not successful. +//! +//! \sa PKAEccMultiplyStart() +// +//***************************************************************************** +extern uint32_t PKAEccMultiplyGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length); + +//***************************************************************************** +// +//! \brief Starts the ECC addition. +//! +//! \param [in] curvePoint1X is the pointer to the buffer containing the +//! X coordinate of the first elliptic curve point to be added. +//! The point must be on the given curve. +//! +//! \param [in] curvePoint1Y is the pointer to the buffer containing the +//! Y coordinate of the first elliptic curve point to be added. +//! The point must be on the given curve. +//! +//! \param [in] curvePoint2X is the pointer to the buffer containing the +//! X coordinate of the second elliptic curve point to be added. +//! The point must be on the given curve. +//! +//! \param [in] curvePoint2Y is the pointer to the buffer containing the +//! Y coordinate of the second elliptic curve point to be added. +//! The point must be on the given curve. +//! +//! \param [in] prime is the prime of the curve. +//! +//! \param [in] a is the a constant of the curve when the curve equation is expressed +//! in short Weierstrass form (y^3 = x^2 + a*x + b). +//! +//! \param [in] length is the length of the curve parameters in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKAEccAddGetResult() +// +//***************************************************************************** +extern uint32_t PKAEccAddStart(const uint8_t *curvePoint1X, + const uint8_t *curvePoint1Y, + const uint8_t *curvePoint2X, + const uint8_t *curvePoint2Y, + const uint8_t *prime, + const uint8_t *a, + uint32_t length, + uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Gets the result of the ECC addition +//! +//! This function gets the result of ECC point addition operation on the +//! on the two given EC points, previously started using the function +//! PKAEccAddStart(). +//! +//! \param [out] curvePointX is the pointer to the structure where the X coordinate +//! of the resultant EC point will be stored. +//! +//! \param [out] curvePointY is the pointer to the structure where the Y coordinate +//! of the resultant EC point will be stored. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKAEccAddGetResult(). +//! +//! \param [in] length is the length of the curve parameters in bytes. +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_FAILURE if the operation is not successful. +//! +//! \sa PKAEccAddStart() +// +//***************************************************************************** +extern uint32_t PKAEccAddGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length); + + +//***************************************************************************** +// +//! \brief Begins the validation of a public key against a Short-Weierstrass curve +//! +//! This function validates a public key against a curve. +//! After performing multiple smaller PKA operations in polling mode, +//! it starts an ECC scalar multiplication. +//! +//! The function verifies that: +//! - X and Y are in the range [1, prime - 1] +//! - The point is not the point at infinity +//! - X and Y satisfy the Short-Weierstrass curve equation Y^2 = X^3 + a*X + b mod P +//! - Multiplying the point by the order of the curve yields the point at infinity +//! +//! \param [in] curvePointX is the pointer to the buffer containing the +//! X coordinate of the elliptic curve point to verify. +//! +//! \param [in] curvePointY is the pointer to the buffer containing the +//! Y coordinate of the elliptic curve point to verify. +//! +//! \param [in] prime is the prime of the curve. +//! +//! \param [in] a is the a constant of the curve when the curve equation is expressed +//! in Short-Weierstrass form (y^3 = x^2 + a*x + b). +//! +//! \param [in] b is the b constant of the curve when the curve equation is expressed +//! in Short-Weierstrass form (y^3 = x^2 + a*x + b). +//! +//! \param [in] order is the order of the curve. +//! +//! \param [in] length is the length of the curve parameters in bytes. +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing the operation. +//! - \ref PKA_STATUS_FAILURE if the operation is not successful. +//! - \ref PKA_STATUS_X_ZERO if X is zero. +//! - \ref PKA_STATUS_Y_ZERO if Y is zero. +//! - \ref PKA_STATUS_X_LARGER_THAN_PRIME if X is larger than the curve prime +//! - \ref PKA_STATUS_Y_LARGER_THAN_PRIME if Y is larger than the curve prime +//! - \ref PKA_STATUS_POINT_NOT_ON_CURVE if X and Y do not satisfy the curve equation +//! +//! \sa PKAEccVerifyPublicKeyGetResult() +// +//***************************************************************************** +extern uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t *curvePointX, + const uint8_t *curvePointY, + const uint8_t *prime, + const uint8_t *a, + const uint8_t *b, + const uint8_t *order, + uint32_t length); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_PKAClearPkaRam + #undef PKAClearPkaRam + #define PKAClearPkaRam ROM_PKAClearPkaRam + #endif + #ifdef ROM_PKAGetOpsStatus + #undef PKAGetOpsStatus + #define PKAGetOpsStatus ROM_PKAGetOpsStatus + #endif + #ifdef ROM_PKAArrayAllZeros + #undef PKAArrayAllZeros + #define PKAArrayAllZeros ROM_PKAArrayAllZeros + #endif + #ifdef ROM_PKAZeroOutArray + #undef PKAZeroOutArray + #define PKAZeroOutArray ROM_PKAZeroOutArray + #endif + #ifdef ROM_PKABigNumModStart + #undef PKABigNumModStart + #define PKABigNumModStart ROM_PKABigNumModStart + #endif + #ifdef ROM_PKABigNumModGetResult + #undef PKABigNumModGetResult + #define PKABigNumModGetResult ROM_PKABigNumModGetResult + #endif + #ifdef ROM_PKABigNumDivideStart + #undef PKABigNumDivideStart + #define PKABigNumDivideStart ROM_PKABigNumDivideStart + #endif + #ifdef ROM_PKABigNumDivideGetQuotient + #undef PKABigNumDivideGetQuotient + #define PKABigNumDivideGetQuotient ROM_PKABigNumDivideGetQuotient + #endif + #ifdef ROM_PKABigNumDivideGetRemainder + #undef PKABigNumDivideGetRemainder + #define PKABigNumDivideGetRemainder ROM_PKABigNumDivideGetRemainder + #endif + #ifdef ROM_PKABigNumCmpStart + #undef PKABigNumCmpStart + #define PKABigNumCmpStart ROM_PKABigNumCmpStart + #endif + #ifdef ROM_PKABigNumCmpGetResult + #undef PKABigNumCmpGetResult + #define PKABigNumCmpGetResult ROM_PKABigNumCmpGetResult + #endif + #ifdef ROM_PKABigNumInvModStart + #undef PKABigNumInvModStart + #define PKABigNumInvModStart ROM_PKABigNumInvModStart + #endif + #ifdef ROM_PKABigNumInvModGetResult + #undef PKABigNumInvModGetResult + #define PKABigNumInvModGetResult ROM_PKABigNumInvModGetResult + #endif + #ifdef ROM_PKABigNumMultiplyStart + #undef PKABigNumMultiplyStart + #define PKABigNumMultiplyStart ROM_PKABigNumMultiplyStart + #endif + #ifdef ROM_PKABigNumMultGetResult + #undef PKABigNumMultGetResult + #define PKABigNumMultGetResult ROM_PKABigNumMultGetResult + #endif + #ifdef ROM_PKABigNumAddStart + #undef PKABigNumAddStart + #define PKABigNumAddStart ROM_PKABigNumAddStart + #endif + #ifdef ROM_PKABigNumAddGetResult + #undef PKABigNumAddGetResult + #define PKABigNumAddGetResult ROM_PKABigNumAddGetResult + #endif + #ifdef ROM_PKABigNumSubStart + #undef PKABigNumSubStart + #define PKABigNumSubStart ROM_PKABigNumSubStart + #endif + #ifdef ROM_PKABigNumSubGetResult + #undef PKABigNumSubGetResult + #define PKABigNumSubGetResult ROM_PKABigNumSubGetResult + #endif + #ifdef ROM_PKAEccMultiplyStart + #undef PKAEccMultiplyStart + #define PKAEccMultiplyStart ROM_PKAEccMultiplyStart + #endif + #ifdef ROM_PKAEccMontgomeryMultiplyStart + #undef PKAEccMontgomeryMultiplyStart + #define PKAEccMontgomeryMultiplyStart ROM_PKAEccMontgomeryMultiplyStart + #endif + #ifdef ROM_PKAEccMultiplyGetResult + #undef PKAEccMultiplyGetResult + #define PKAEccMultiplyGetResult ROM_PKAEccMultiplyGetResult + #endif + #ifdef ROM_PKAEccAddStart + #undef PKAEccAddStart + #define PKAEccAddStart ROM_PKAEccAddStart + #endif + #ifdef ROM_PKAEccAddGetResult + #undef PKAEccAddGetResult + #define PKAEccAddGetResult ROM_PKAEccAddGetResult + #endif + #ifdef ROM_PKAEccVerifyPublicKeyWeierstrassStart + #undef PKAEccVerifyPublicKeyWeierstrassStart + #define PKAEccVerifyPublicKeyWeierstrassStart ROM_PKAEccVerifyPublicKeyWeierstrassStart + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PKA_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka_doc.h new file mode 100644 index 0000000..82d34c1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka_doc.h @@ -0,0 +1,80 @@ +/****************************************************************************** +* Filename: pka_doc.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup pka_api +//! @{ +//! \section sec_pka Introduction +//! +//! The PKA (Public Key Accelerator) API provides access to the Large Number +//! Engine (LNME). The LNME allows for efficient math operations on numbers +//! larger than those that fit within the ALU of the system CPU. It is significantly faster +//! to perform these operations using the LNME than implementing the same +//! functionality in software using regular word-wise math operations. While the +//! LNME runs in the background, the system CPU may perform other operations +//! or be turned off. +//! +//! The LNME supports both primitive math operations and serialized primitive +//! operations (sequencer operations). +//! - Addition +//! - Multiplication +//! - Comparison +//! - Modulo +//! - Inverse Modulo +//! - ECC Point Addition (including point doubling) +//! - ECC Scalar Multiplication +//! +//! These primitives and sequencer operations can be used to implement various +//! public key encryption schemes. +//! It is possible to implement the following schemes using the operations mentioned above: +//! - RSA encryption and decryption +//! - RSA sign and verify +//! - DHE (Diffie-Hellman Key Exchange) +//! - ECDH (Elliptic Curve Diffie-Hellman Key Exchange) +//! - ECDSA (Elliptic Curve Digital Signature Algorithm) +//! - ECIES (Elliptic Curve Integrated Encryption Scheme) +//! +//! The DriverLib PKA functions copy the relevant parameters into the dedicated +//! PKA RAM. The LNME requires these parameters be present and correctly +//! formatted in the PKA RAM and not system RAM. They are copied word-wise as +//! the PKA RAM does not support byte-wise access. The CPU handles the alignment differences +//! during the memory copy operation. Forcing buffer alignment in system RAM results +//! in a significant speedup of the copy operation compared to unaligned buffers. +//! +//! When the operation completes, the result is copied back into +//! a buffer in system RAM specified by the application. The PKA RAM is then cleared +//! to prevent sensitive keying material from remaining in PKA RAM. +//! +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.c new file mode 100644 index 0000000..b699d78 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.c @@ -0,0 +1,647 @@ +/****************************************************************************** +* Filename: prcm.c +* Revised: 2018-10-18 17:33:32 +0200 (Thu, 18 Oct 2018) +* Revision: 52954 +* +* Description: Driver for the PRCM. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "prcm.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef PRCMInfClockConfigureSet + #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet + #undef PRCMInfClockConfigureGet + #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet + #undef PRCMAudioClockConfigSet + #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet + #undef PRCMAudioClockConfigSetOverride + #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride + #undef PRCMAudioClockInternalSource + #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource + #undef PRCMAudioClockExternalSource + #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource + #undef PRCMPowerDomainOn + #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn + #undef PRCMPowerDomainOff + #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff + #undef PRCMPeripheralRunEnable + #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable + #undef PRCMPeripheralRunDisable + #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable + #undef PRCMPeripheralSleepEnable + #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable + #undef PRCMPeripheralSleepDisable + #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable + #undef PRCMPeripheralDeepSleepEnable + #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable + #undef PRCMPeripheralDeepSleepDisable + #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable + #undef PRCMPowerDomainStatus + #define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus + #undef PRCMDeepSleep + #define PRCMDeepSleep NOROM_PRCMDeepSleep +#endif + + +//***************************************************************************** +// +// Arrays that maps the "peripheral set" number (which is stored in +// bits[11:8] of the PRCM_PERIPH_* defines) to the PRCM register that +// contains the relevant bit for that peripheral. +// +//***************************************************************************** + +// Run mode registers +static const uint32_t g_pui32RCGCRegs[] = +{ + PRCM_O_GPTCLKGR , // Index 0 + PRCM_O_SSICLKGR , // Index 1 + PRCM_O_UARTCLKGR , // Index 2 + PRCM_O_I2CCLKGR , // Index 3 + PRCM_O_SECDMACLKGR , // Index 4 + PRCM_O_GPIOCLKGR , // Index 5 + PRCM_O_I2SCLKGR // Index 6 +}; + +// Sleep mode registers +static const uint32_t g_pui32SCGCRegs[] = +{ + PRCM_O_GPTCLKGS , // Index 0 + PRCM_O_SSICLKGS , // Index 1 + PRCM_O_UARTCLKGS , // Index 2 + PRCM_O_I2CCLKGS , // Index 3 + PRCM_O_SECDMACLKGS , // Index 4 + PRCM_O_GPIOCLKGS , // Index 5 + PRCM_O_I2SCLKGS // Index 6 +}; + +// Deep sleep mode registers +static const uint32_t g_pui32DCGCRegs[] = +{ + PRCM_O_GPTCLKGDS , // Index 0 + PRCM_O_SSICLKGDS , // Index 1 + PRCM_O_UARTCLKGDS , // Index 2 + PRCM_O_I2CCLKGDS , // Index 3 + PRCM_O_SECDMACLKGDS , // Index 4 + PRCM_O_GPIOCLKGDS , // Index 5 + PRCM_O_I2SCLKGDS // Index 6 +}; + +//***************************************************************************** +// +// This macro extracts the array index out of the peripheral number +// +//***************************************************************************** +#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf) + +//***************************************************************************** +// +// This macro extracts the peripheral instance number and generates bit mask +// +//***************************************************************************** +#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0x1f)) + + +//***************************************************************************** +// +// Configure the infrastructure clock. +// +//***************************************************************************** +void +PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode) +{ + uint32_t ui32Divisor; + + // Check the arguments. + ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || + (ui32ClkDiv == PRCM_CLOCK_DIV_2) || + (ui32ClkDiv == PRCM_CLOCK_DIV_8) || + (ui32ClkDiv == PRCM_CLOCK_DIV_32)); + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32Divisor = 0; + + // Find the correct division factor. + if(ui32ClkDiv == PRCM_CLOCK_DIV_1) + { + ui32Divisor = 0x0; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_2) + { + ui32Divisor = 0x1; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_8) + { + ui32Divisor = 0x2; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_32) + { + ui32Divisor = 0x3; + } + + // Determine the correct power mode set the division factor accordingly. + if(ui32PowerMode == PRCM_RUN_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor; + } +} + +//***************************************************************************** +// +// Use this function to get the infrastructure clock configuration +// +//***************************************************************************** +uint32_t +PRCMInfClockConfigureGet(uint32_t ui32PowerMode) +{ + uint32_t ui32ClkDiv; + uint32_t ui32Divisor; + + // Check the arguments. + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32ClkDiv = 0; + ui32Divisor = 0; + + // Determine the correct power mode. + if(ui32PowerMode == PRCM_RUN_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR); + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS); + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS); + } + + // Find the correct division factor. + if(ui32ClkDiv == 0x0) + { + ui32Divisor = PRCM_CLOCK_DIV_1; + } + else if(ui32ClkDiv == 0x1) + { + ui32Divisor = PRCM_CLOCK_DIV_2; + } + else if(ui32ClkDiv == 0x2) + { + ui32Divisor = PRCM_CLOCK_DIV_8; + } + else if(ui32ClkDiv == 0x3) + { + ui32Divisor = PRCM_CLOCK_DIV_32; + } + + // Return the clock division factor. + return ui32Divisor; +} + + +//***************************************************************************** +// +// Configure the audio clock generation +// +//***************************************************************************** +void +PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate) +{ + uint32_t ui32Reg; + uint32_t ui32MstDiv; + uint32_t ui32BitDiv; + uint32_t ui32WordDiv; + + // Check the arguments. + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) || + (ui32SampleRate == I2S_SAMPLE_RATE_24K) || + (ui32SampleRate == I2S_SAMPLE_RATE_32K) || + (ui32SampleRate == I2S_SAMPLE_RATE_48K)); + + ui32MstDiv = 0; + ui32BitDiv = 0; + ui32WordDiv = 0; + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Define the clock division factors for the audio interface. + switch(ui32SampleRate) + { + case I2S_SAMPLE_RATE_16K : + ui32MstDiv = 6; + ui32BitDiv = 60; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_24K : + ui32MstDiv = 4; + ui32BitDiv = 40; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_32K : + ui32MstDiv = 3; + ui32BitDiv = 30; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_48K : + ui32MstDiv = 2; + ui32BitDiv = 20; + ui32WordDiv = 25; + break; + } + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity. + ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} + +//***************************************************************************** +// +// Configure the audio clock generation with manual setting of clock divider. +// +//***************************************************************************** +void +PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, + uint32_t ui32BitDiv, uint32_t ui32WordDiv) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity. + ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} + +//***************************************************************************** +// +// Configure the audio clocks for I2S module +// +//***************************************************************************** +void +PRCMAudioClockConfigOverride(uint8_t ui8SamplingEdge, + uint8_t ui8WCLKPhase, + uint32_t ui32MstDiv, + uint32_t ui32BitDiv, + uint32_t ui32WordDiv) +{ + // Check the arguments. + ASSERT( ui8BitsPerSample == PRCM_WCLK_SINGLE_PHASE + || ui8BitsPerSample == PRCM_WCLK_DUAL_PHASE + || ui8BitsPerSample == PRCM_WCLK_USER_DEF); + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui8WCLKPhase) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity and enable it. + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = (ui8SamplingEdge << PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S) | + (ui8WCLKPhase << PRCM_I2SCLKCTL_WCLK_PHASE_S ) | + (1 << PRCM_I2SCLKCTL_EN_S ); +} + +//***************************************************************************** +// +// Configure the clocks as "internally generated". +// +//***************************************************************************** +void PRCMAudioClockInternalSource(void) +{ + HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 1; +} + +//***************************************************************************** +// +// Configure the clocks as "externally generated". +// +//***************************************************************************** +void PRCMAudioClockExternalSource(void) +{ + HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 0; +} + +//***************************************************************************** +// +// Turn power on in power domains in the MCU domain +// +//***************************************************************************** +void +PRCMPowerDomainOn(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Assert the request to power on the right domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 1; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 1; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 1; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 1; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 1; + } +} + +//***************************************************************************** +// +// Turn off a specific power domain +// +//***************************************************************************** +void +PRCMPowerDomainOff(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Assert the request to power off the right domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 0; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 0; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 0; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + // Write bits ui32Domains[17:16] to the VIMS_MODE alias register. + // PRCM_DOMAIN_VIMS sets VIMS_MODE=0b00, PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP sets VIMS_MODE=0b10. + ASSERT(!(ui32Domains & 0x00010000)); + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = ( ui32Domains >> 16 ) & 3; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 0; + } +} + +//***************************************************************************** +// +// Enables a peripheral in Run mode +// +//***************************************************************************** +void +PRCMPeripheralRunEnable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable module in Run Mode. + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Disables a peripheral in Run mode +// +//***************************************************************************** +void +PRCMPeripheralRunDisable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable module in Run Mode. + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Enables a peripheral in sleep mode +// +//***************************************************************************** +void +PRCMPeripheralSleepEnable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable this peripheral in sleep mode. + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Disables a peripheral in sleep mode +// +//***************************************************************************** +void +PRCMPeripheralSleepDisable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable this peripheral in sleep mode + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Enables a peripheral in deep-sleep mode +// +//***************************************************************************** +void +PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable this peripheral in deep-sleep mode. + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Disables a peripheral in deep-sleep mode +// +//***************************************************************************** +void +PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable this peripheral in Deep Sleep mode. + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Get the status for a specific power domain +// +//***************************************************************************** +uint32_t +PRCMPowerDomainStatus(uint32_t ui32Domains) +{ + bool bStatus; + uint32_t ui32StatusRegister0; + uint32_t ui32StatusRegister1; + + // Check the arguments. + ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE | + PRCM_DOMAIN_SERIAL | + PRCM_DOMAIN_PERIPH))); + + bStatus = true; + ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0); + ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1); + + // Return the correct power status. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + bStatus = bStatus && + ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) || + (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON)); + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON); + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON); + } + + // Return the status. + return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF); +} + +//***************************************************************************** +// +// Put the processor into deep-sleep mode +// +//***************************************************************************** +void +PRCMDeepSleep(void) +{ + // Enable deep-sleep. + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // Wait for an interrupt. + CPUwfi(); + + // Disable deep-sleep so that a future sleep will work correctly. + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h new file mode 100644 index 0000000..b2c4bba --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h @@ -0,0 +1,1234 @@ +/****************************************************************************** +* Filename: prcm.h +* Revised: 2018-10-23 10:19:14 +0200 (Tue, 23 Oct 2018) +* Revision: 52979 +* +* Description: Defines and prototypes for the PRCM +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup prcm_api +//! @{ +// +//***************************************************************************** + +#ifndef __PRCM_H__ +#define __PRCM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_aon_rtc.h" +#include "interrupt.h" +#include "debug.h" +#include "cpu.h" + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet + #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet + #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet + #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride + #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource + #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource + #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn + #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff + #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable + #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable + #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable + #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable + #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable + #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable + #define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus + #define PRCMDeepSleep NOROM_PRCMDeepSleep +#endif + +//***************************************************************************** +// +// Defines for the different System CPU power modes. +// +//***************************************************************************** +#define PRCM_RUN_MODE 0x00000001 +#define PRCM_SLEEP_MODE 0x00000002 +#define PRCM_DEEP_SLEEP_MODE 0x00000004 + +//***************************************************************************** +// +// Defines used for setting the clock division factors +// +//***************************************************************************** +#define PRCM_CLOCK_DIV_1 PRCM_GPTCLKDIV_RATIO_DIV1 +#define PRCM_CLOCK_DIV_2 PRCM_GPTCLKDIV_RATIO_DIV2 +#define PRCM_CLOCK_DIV_4 PRCM_GPTCLKDIV_RATIO_DIV4 +#define PRCM_CLOCK_DIV_8 PRCM_GPTCLKDIV_RATIO_DIV8 +#define PRCM_CLOCK_DIV_16 PRCM_GPTCLKDIV_RATIO_DIV16 +#define PRCM_CLOCK_DIV_32 PRCM_GPTCLKDIV_RATIO_DIV32 +#define PRCM_CLOCK_DIV_64 PRCM_GPTCLKDIV_RATIO_DIV64 +#define PRCM_CLOCK_DIV_128 PRCM_GPTCLKDIV_RATIO_DIV128 +#define PRCM_CLOCK_DIV_256 PRCM_GPTCLKDIV_RATIO_DIV256 + +//***************************************************************************** +// +// Defines used for enabling and disabling domains and memories in the MCU +// domain +// +//***************************************************************************** +#define PRCM_DOMAIN_RFCORE 0x00000001 // RF Core domain ID for + // clock/power control. +#define PRCM_DOMAIN_SERIAL 0x00000002 // Serial domain ID for + // clock/power control. +#define PRCM_DOMAIN_PERIPH 0x00000004 // Peripheral domain ID for + // clock/power control. +#define PRCM_DOMAIN_SYSBUS 0x00000008 // Bus domain ID for clock/power + // control. +#define PRCM_DOMAIN_VIMS 0x00000010 // VIMS domain ID for clock/power + // control. +#define PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP \ + 0x00020010 // For function PRCMPowerDomainOff() it is an option to + // select that VIMS power domain shall not power up + // during the next wake up from uLDO (VIMS_MODE=0b10). +#define PRCM_DOMAIN_CPU 0x00000020 // CPU domain ID for clock/power + // control. +#define PRCM_DOMAIN_TIMER 0x00000040 // GPT domain ID for clock + // control. +#define PRCM_DOMAIN_CLKCTRL 0x00000080 // Clock Control domain ID for + // clock/power control. +#define PRCM_DOMAIN_MCU 0x00000100 // Reset control for entire MCU + // domain. +#define PRCM_DOMAIN_POWER_OFF 0x00000002 // The domain is powered off +#define PRCM_DOMAIN_POWER_ON 0x00000001 // The domain is powered on +#define PRCM_DOMAIN_POWER_DOWN_READY \ + 0x00000000 // The domain is ready to be + // powered down. + +//***************************************************************************** +// +// Defines for setting up the audio interface in the I2S module. +// +//***************************************************************************** +#define PRCM_WCLK_NEG_EDGE 0x00000008 +#define PRCM_WCLK_POS_EDGE 0x00000000 +#define PRCM_WCLK_SINGLE_PHASE 0x00000000 +#define PRCM_WCLK_DUAL_PHASE 0x00000002 +#define PRCM_WCLK_USER_DEF 0x00000004 +#define PRCM_I2S_WCLK_NEG_EDGE 0 +#define PRCM_I2S_WCLK_POS_EDGE 1 +#define PRCM_I2S_WCLK_SINGLE_PHASE 0 +#define PRCM_I2S_WCLK_DUAL_PHASE 1 +#define PRCM_I2S_WCLK_USER_DEF 2 + +#define I2S_SAMPLE_RATE_16K 0x00000001 +#define I2S_SAMPLE_RATE_24K 0x00000002 +#define I2S_SAMPLE_RATE_32K 0x00000004 +#define I2S_SAMPLE_RATE_48K 0x00000008 + +//***************************************************************************** +// +// Defines used for enabling and disabling peripheral modules in the MCU domain +// bits[11:8] Defines the index into the register offset constant tables: +// g_pui32RCGCRegs, g_pui32SCGCRegs and g_pui32DCGCRegs +// bits[4:0] Defines the bit position within the register pointet on in [11:8] +// +//***************************************************************************** +#define PRCM_PERIPH_TIMER0 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S )) // Peripheral ID for GPT module 0 +#define PRCM_PERIPH_TIMER1 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for GPT module 1 +#define PRCM_PERIPH_TIMER2 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 2 )) // Peripheral ID for GPT module 2 +#define PRCM_PERIPH_TIMER3 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 3 )) // Peripheral ID for GPT module 3 +#define PRCM_PERIPH_SSI0 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S )) // Peripheral ID for SSI module 0 +#define PRCM_PERIPH_SSI1 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S + 1 )) // Peripheral ID for SSI module 1 +#define PRCM_PERIPH_UART0 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S )) // Peripheral ID for UART module 0 +#define PRCM_PERIPH_UART1 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for UART module 1 +#define PRCM_PERIPH_I2C0 ( 0x00000300 | ( PRCM_I2CCLKGR_CLK_EN_S )) // Peripheral ID for I2C module 0 +#define PRCM_PERIPH_CRYPTO ( 0x00000400 | ( PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S )) // Peripheral ID for CRYPTO module +#define PRCM_PERIPH_TRNG ( 0x00000400 | ( PRCM_SECDMACLKGR_TRNG_CLK_EN_S )) // Peripheral ID for TRNG module +#define PRCM_PERIPH_PKA ( 0x00000400 | ( PRCM_SECDMACLKGR_PKA_CLK_EN_S )) // Peripheral ID for PKA module +#define PRCM_PERIPH_UDMA ( 0x00000400 | ( PRCM_SECDMACLKGR_DMA_CLK_EN_S )) // Peripheral ID for UDMA module +#define PRCM_PERIPH_GPIO ( 0x00000500 | ( PRCM_GPIOCLKGR_CLK_EN_S )) // Peripheral ID for GPIO module +#define PRCM_PERIPH_I2S ( 0x00000600 | ( PRCM_I2SCLKGR_CLK_EN_S )) // Peripheral ID for I2S module + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \brief Checks a peripheral identifier. +//! +//! This function determines if a peripheral identifier is valid. +//! +//! \param ui32Peripheral is the peripheral identifier. +//! +//! \return Returns status of peripheral identifier: +//! - \b true : Peripheral identifier is valid. +//! - \b false : Peripheral identifier is invalid. +// +//***************************************************************************** +static bool +PRCMPeripheralValid(uint32_t ui32Peripheral) +{ + return((ui32Peripheral == PRCM_PERIPH_TIMER0) || + (ui32Peripheral == PRCM_PERIPH_TIMER1) || + (ui32Peripheral == PRCM_PERIPH_TIMER2) || + (ui32Peripheral == PRCM_PERIPH_TIMER3) || + (ui32Peripheral == PRCM_PERIPH_SSI0) || + (ui32Peripheral == PRCM_PERIPH_SSI1) || + (ui32Peripheral == PRCM_PERIPH_UART0) || + (ui32Peripheral == PRCM_PERIPH_UART1) || + (ui32Peripheral == PRCM_PERIPH_I2C0) || + (ui32Peripheral == PRCM_PERIPH_CRYPTO) || + (ui32Peripheral == PRCM_PERIPH_TRNG) || + (ui32Peripheral == PRCM_PERIPH_PKA) || + (ui32Peripheral == PRCM_PERIPH_UDMA) || + (ui32Peripheral == PRCM_PERIPH_GPIO) || + (ui32Peripheral == PRCM_PERIPH_I2S)); +} +#endif + +//***************************************************************************** +// +//! \brief Configure the infrastructure clock. +//! +//! Each System CPU power mode has its own infrastructure clock division factor. This +//! function can be used for setting up the division factor for the +//! infrastructure clock in the available power modes for the System CPU. The +//! infrastructure clock is used for all internal logic in the PRCM, and is +//! always running as long as power is on in the MCU voltage domain. +//! This can be enabled and disabled from the AON Wake Up Controller. +//! +//! \note If source clock is 48 MHz, minimum clock divider is \ref PRCM_CLOCK_DIV_2. +//! +//! \param ui32ClkDiv determines the division ratio for the infrastructure +//! clock when the device is in the specified mode. +//! Allowed division factors for all three System CPU power modes are: +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_32 +//! \param ui32PowerMode determines the System CPU operation mode for which to +//! modify the clock division factor. +//! The three allowed power modes are: +//! - \ref PRCM_RUN_MODE +//! - \ref PRCM_SLEEP_MODE +//! - \ref PRCM_DEEP_SLEEP_MODE +//! +//! \return None +// +//***************************************************************************** +extern void PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, + uint32_t ui32PowerMode); + +//***************************************************************************** +// +//! \brief Use this function to get the infrastructure clock configuration. +//! +//! \param ui32PowerMode determines which System CPU power mode to return the +//! infrastructure clock division ratio for. +//! The three allowed power modes are: +//! - \ref PRCM_RUN_MODE +//! - \ref PRCM_SLEEP_MODE +//! - \ref PRCM_DEEP_SLEEP_MODE +//! +//! \return Returns the infrastructure clock division factor for the specified +//! power mode. +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_32 +//! +//! \sa \ref PRCMInfClockConfigureSet(). +// +//***************************************************************************** +extern uint32_t PRCMInfClockConfigureGet(uint32_t ui32PowerMode); + +//***************************************************************************** +// +//! \brief Assert or de-assert a request for the uLDO. +//! +//! Use this function to request to switch to the micro Low Voltage Dropout +//! regulator (uLDO). The uLDO has a much lower capacity for supplying power +//! to the system. It is therefore imperative and solely the programmers +//! responsibility to ensure that a sufficient amount of peripheral modules +//! have been turned of before requesting a switch to the uLDO. +//! +//! \note Asserting this bit has no effect until: +//! 1. FLASH has accepted to be powered down +//! 2. Deepsleep must be asserted +//! +//! \param ui32Enable +//! - 0 : Disable uLDO request +//! - 1 : Enable uLDO request +//! +//! \return None +//! +//! \sa \ref PRCMDeepSleep() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMMcuUldoConfigure(uint32_t ui32Enable) +{ + // Enable or disable the uLDO request signal. + HWREGBITW(PRCM_BASE + PRCM_O_VDCTL, PRCM_VDCTL_ULDO_BITN) = ui32Enable; +} + +//***************************************************************************** +// +//! \brief Setup the clock division factor for the GP-Timer domain. +//! +//! Use this function to set up the clock division factor on the GP-Timer. +//! +//! The division rate will be constant and ungated for Run / Sleep / DeepSleep mode when +//! it is slower than PRCM_GPTCLKDIV_RATIO setting. +//! When set faster than PRCM_GPTCLKDIV_RATIO setting PRCM_GPTCLKDIV_RATIO will be used. +//! Note that the register will contain the written content even though the setting is +//! faster than PRCM_GPTCLKDIV_RATIO setting. +//! +//! \note For change to take effect, \ref PRCMLoadSet() needs to be called +//! +//! \param clkDiv is the division factor to set. +//! The argument must be only one of the following values: +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_4 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_16 +//! - \ref PRCM_CLOCK_DIV_32 +//! - \ref PRCM_CLOCK_DIV_64 +//! - \ref PRCM_CLOCK_DIV_128 +//! - \ref PRCM_CLOCK_DIV_256 +//! +//! \return None +//! +//! \sa \ref PRCMGPTimerClockDivisionGet() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMGPTimerClockDivisionSet( uint32_t clkDiv ) +{ + ASSERT( clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256 ); + + HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ) = clkDiv; +} + +//***************************************************************************** +// +//! \brief Get the clock division factor for the GP-Timer domain. +//! +//! Use this function to get the clock division factor set for the GP-Timer. +//! +//! \return Returns one of the following values: +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_4 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_16 +//! - \ref PRCM_CLOCK_DIV_32 +//! - \ref PRCM_CLOCK_DIV_64 +//! - \ref PRCM_CLOCK_DIV_128 +//! - \ref PRCM_CLOCK_DIV_256 +//! +//! \sa \ref PRCMGPTimerClockDivisionSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +PRCMGPTimerClockDivisionGet( void ) +{ + return ( HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV )); +} + + +//***************************************************************************** +// +//! \brief Enable the audio clock generation. +//! +//! Use this function to enable the audio clock generation. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMAudioClockEnable(void) +{ + // Enable the audio clock generation. + HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disable the audio clock generation. +//! +//! Use this function to disable the audio clock generation. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMAudioClockDisable(void) +{ + // Disable the audio clock generation + HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Configure the audio clock generation. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Use this function to set the sample rate when using internal audio clock +//! generation for the I2S module. +//! +//! \note While other clocks are possible, the stability of the four sample +//! rates defined here are only guaranteed if the clock input to the I2S module +//! is 48MHz. +//! +//! \param ui32ClkConfig is the audio clock configuration. +//! The parameter is a bitwise OR'ed value consisting of: +//! - Phase +//! - \ref PRCM_WCLK_SINGLE_PHASE +//! - \ref PRCM_WCLK_DUAL_PHASE +//! - Clock polarity +//! - \ref PRCM_WCLK_NEG_EDGE +//! - \ref PRCM_WCLK_POS_EDGE +//! \param ui32SampleRate is the desired audio clock sample rate. +//! The supported sample rate configurations are: +//! - \ref I2S_SAMPLE_RATE_16K +//! - \ref I2S_SAMPLE_RATE_24K +//! - \ref I2S_SAMPLE_RATE_32K +//! - \ref I2S_SAMPLE_RATE_48K +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockConfigSetOverride() +// +//***************************************************************************** +#ifndef DEPRECATED +extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, + uint32_t ui32SampleRate); +#endif + +//***************************************************************************** +// +//! \brief Configure the audio clock generation with manual setting of clock divider. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Use this function to set the audio clock divider values manually. +//! +//! \note See hardware documentation before setting audio clock dividers manually. +//! +//! \param ui32ClkConfig is the audio clock configuration. +//! The parameter is a bitwise OR'ed value consisting of: +//! - Phase +//! - \ref PRCM_WCLK_SINGLE_PHASE +//! - \ref PRCM_WCLK_DUAL_PHASE +//! - Clock polarity +//! - \ref PRCM_WCLK_NEG_EDGE +//! - \ref PRCM_WCLK_POS_EDGE +//! \param ui32MstDiv is the desired master clock divider. +//! \param ui32WordDiv is the desired word clock divider. +//! \param ui32BitDiv is the desired bit clock divider. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockConfigSet() +// +//***************************************************************************** +#ifndef DEPRECATED +extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, + uint32_t ui32BitDiv, uint32_t ui32WordDiv); +#endif + +//***************************************************************************** +// +//! \brief Configure the audio clocks for I2S module. +//! +//! \note See hardware documentation before setting audio clock dividers. +//! This is user's responsability to provide valid clock dividers. +//! +//! \param ui8SamplingEdge Define the clock polarity: +//! - \ref PRCM_I2S_WCLK_NEG_EDGE +//! - \ref PRCM_I2S_WCLK_POS_EDGE +//! \param ui8WCLKPhase Define I2S phase used +//! - PRCM_I2S_WCLK_SINGLE_PHASE +//! - PRCM_I2S_WCLK_DUAL_PHASE +//! - PRCM_I2S_WCLK_USER_DEF +//! \param ui32MstDiv is the desired master clock divider. +//! \param ui32BitDiv is the desired bit clock divider. +//! \param ui32WordDiv is the desired word clock divider. +//! +//! \return None +//! +//***************************************************************************** +extern void PRCMAudioClockConfigOverride + (uint8_t ui8SamplingEdge, + uint8_t ui8WCLKPhase, + uint32_t ui32MstDiv, + uint32_t ui32BitDiv, + uint32_t ui32WordDiv); + +//***************************************************************************** +// +//! \brief Configure the audio clocks to be internally generated. +//! +//! Use this function to set the audio clocks as internal. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockExternalSource() +// +//***************************************************************************** +extern void PRCMAudioClockInternalSource(void); + +//***************************************************************************** +// +//! \brief Configure the audio clocks to be externally generated. +//! +//! Use this function to set the audio clocks as external. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockInternalSource() +// +//***************************************************************************** +extern void PRCMAudioClockExternalSource(void); + +//***************************************************************************** +// +//! \brief Use this function to synchronize the load settings. +//! +//! Most of the clock settings in the PRCM module should be updated +//! synchronously. This is ensured by the implementation of a load registers +//! that, when written to, will let the previous written update values for all +//! the relevant registers propagate through to hardware. +//! +//! The functions that require a synchronization of the clock settings are: +//! - \ref PRCMAudioClockConfigSet() +//! - \ref PRCMAudioClockConfigSetOverride() +//! - \ref PRCMAudioClockDisable() +//! - \ref PRCMDomainEnable() +//! - \ref PRCMDomainDisable() +//! - \ref PRCMPeripheralRunEnable() +//! - \ref PRCMPeripheralRunDisable() +//! - \ref PRCMPeripheralSleepEnable() +//! - \ref PRCMPeripheralSleepDisable() +//! - \ref PRCMPeripheralDeepSleepEnable() +//! - \ref PRCMPeripheralDeepSleepDisable() +//! +//! \return None +//! +//! \sa \ref PRCMLoadGet() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMLoadSet(void) +{ + // Enable the update of all load related registers. + HWREG(PRCM_NONBUF_BASE + PRCM_O_CLKLOADCTL) = PRCM_CLKLOADCTL_LOAD; +} + +//***************************************************************************** +// +//! \brief Check if any of the load sensitive register has been updated. +//! +//! \return Returns status of the load sensitive register: +//! - \c true : No registers have changed since the last load. +//! - \c false : Any register has changed. +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +__STATIC_INLINE bool +PRCMLoadGet(void) +{ + // Return the load status. + return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? + true : false); +} + +//***************************************************************************** +// +//! \brief Enable clock domains in the MCU voltage domain. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \note Clocks will only be running if the domain is powered. +//! +//! \param ui32Domains is a bit mask containing the clock domains to enable. +//! The independent clock domains inside the MCU voltage domain which can be +//! configured are: +//! - \ref PRCM_DOMAIN_RFCORE +//! - \ref PRCM_DOMAIN_VIMS +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMDomainEnable(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Enable the clock domain(s). + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = PRCM_RFCCLKG_CLK_EN; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = PRCM_VIMSCLKG_CLK_EN_M; + } +} + +//***************************************************************************** +// +//! \brief Disable clock domains in the MCU voltage domain. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \note Clocks will only be running if the domain is powered. +//! +//! \param ui32Domains is a bit mask containing the clock domains to disable. +//! The independent clock domains inside the MCU voltage domain are: +//! - \ref PRCM_DOMAIN_RFCORE +//! - \ref PRCM_DOMAIN_VIMS +//! +//! \return None +//! +//! \sa PRCMDomainEnable() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMDomainDisable(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Disable the power domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = 0x0; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = 0x0; + } +} + +//***************************************************************************** +// +//! \brief Turn power on in power domains in the MCU domain. +//! +//! Use this function to turn on power domains inside the MCU voltage domain. +//! +//! Power on and power off request has different implications for the +//! different power domains. +//! - RF Core power domain: +//! - Power On : Domain is on or in the process of turning on. +//! - Power Off : Domain is powered down when System CPU is in deep sleep. The third +//! option for the RF Core is to power down when the it is idle. +//! This can be set using \b PRCMRfPowerDownWhenIdle() +//! - SERIAL power domain: +//! - Power on : Domain is powered on. +//! - Power off : Domain is powered off. +//! - PERIPHERIAL power domain: +//! - Power on : Domain is powered on. +//! - Power off : Domain is powered off. +//! - VIMS power domain: +//! - Power On : Domain is powered if Bus domain is powered. +//! - Power Off : Domain is only powered when CPU domain is on. +//! - BUS power domain: +//! - Power On : Domain is on. +//! - Power Off : Domain is on if requested by RF Core or if CPU domain is on. +//! - CPU power domain: +//! - Power On : Domain is on. +//! - Power Off : Domain is powering down if System CPU is idle. This will also +//! initiate a power down of the SRAM and BUS power domains, unless +//! RF Core is requesting them to be on. +//! +//! \note After a call to this function the status of the power domain should +//! be checked using either \ref PRCMPowerDomainStatus(). +//! Any write operation to a power domain which is still not operational can +//! result in unexpected behavior. +//! +//! \param ui32Domains determines which power domains to turn on. +//! The domains that can be turned on/off are: +//! - \b PRCM_DOMAIN_RFCORE : RF Core +//! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 +//! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 +//! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM +//! - \b PRCM_DOMAIN_SYSBUS +//! - \b PRCM_DOMAIN_CPU +//! +//! \return None +// +//***************************************************************************** +extern void PRCMPowerDomainOn(uint32_t ui32Domains); + +//***************************************************************************** +// +//! \brief Turn off a specific power domain. +//! +//! Use this function to power down domains inside the MCU voltage domain. +//! +//! \note For specifics regarding on/off configuration please see +//! \ref PRCMPowerDomainOn(). +//! +//! \param ui32Domains determines which domain to request a power down for. +//! The domains that can be turned on/off are: +//! - \b PRCM_DOMAIN_RFCORE : RF Core +//! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 +//! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 +//! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM +//! - \b PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP : SRAM, FLASH, ROM +//! - \b PRCM_DOMAIN_SYSBUS +//! - \b PRCM_DOMAIN_CPU +//! +//! \return None +// +//***************************************************************************** +extern void PRCMPowerDomainOff(uint32_t ui32Domains); + +//***************************************************************************** +// +//! \brief Configure RF core to power down when idle. +//! +//! Use this function to configure the RF core to power down when Idle. This +//! is handled automatically in hardware if the RF Core reports that it is +//! idle. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMRfPowerDownWhenIdle(void) +{ + // Configure the RF power domain. + HWREGBITW(PRCM_BASE + PRCM_O_PDCTL0RFC, PRCM_PDCTL0RFC_ON_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Enables a peripheral in Run mode. +//! +//! Peripherals are enabled with this function. At power-up, some peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! \note The actual enabling of the peripheral may be delayed until some +//! time after this function returns. Care should be taken to ensure that the +//! peripheral is not accessed until it is enabled. +//! When enabling Timers always make sure that the division factor for the +//! \b PERBUSCPUCLK is set. This will guarantee that the timers run at a +//! continuous rate even if the \b SYSBUSCLK is gated. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to enable. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_UART1 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_PKA +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralRunEnable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Disables a peripheral in Run mode +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \note The actual disabling of the peripheral may be delayed until some +//! time after this function returns. Care should be taken by the user to +//! ensure that the peripheral is not accessed in this interval as this might +//! cause the system to hang. +//! +//! \param ui32Peripheral is the peripheral to disable. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_UART1 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_PKA +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralRunDisable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Enables a peripheral in sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into sleep mode. Since the clocking configuration of the device does +//! not change, any peripheral can safely continue operating while the +//! processor is in sleep mode, and can therefore wake the processor from sleep +//! mode. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to enable in sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_UART1 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_PKA +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralSleepEnable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Disables a peripheral in sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into sleep mode. Disabling peripherals while in sleep mode helps to lower +//! the current draw of the device. If enabled (via \ref PRCMPeripheralRunEnable()), +//! the peripheral will automatically resume operation when the processor +//! leaves sleep mode, maintaining its entire state from before sleep mode was +//! entered. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to disable in sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_UART1 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_PKA +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralSleepDisable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Enables a peripheral in deep-sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into deep-sleep mode. Since the clocking configuration of the device +//! may change, not all peripherals can safely continue operating while the +//! processor is in sleep mode. This in turn depends on the chosen power mode. +//! It is the responsibility of the caller to make sensible choices. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to enable in deep-sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_UART1 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_PKA +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Disables a peripheral in deep-sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps +//! to lower the current draw of the device, and can keep peripherals that +//! require a particular clock frequency from operating when the clock changes +//! as a result of entering deep-sleep mode. If enabled (via +//! \ref PRCMPeripheralRunEnable()), the peripheral will automatically resume +//! operation when the processor leaves deep-sleep mode, maintaining its entire +//! state from before deep-sleep mode was entered. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to disable in deep-sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_UART1 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_PKA +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Get the status for a specific power domain. +//! +//! Use this function to retrieve the current power status of one or more +//! power domains. +//! +//! \param ui32Domains determines which domain to get the power status for. +//! The parameter must be an OR'ed combination of one or several of: +//! - \ref PRCM_DOMAIN_RFCORE : RF Core. +//! - \ref PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 +//! - \ref PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 +//! +//! \return Returns status of the requested domains: +//! - \ref PRCM_DOMAIN_POWER_ON : The specified domains are \b all powered up. +//! This status is unconditional and the powered up status is guaranteed. +//! - \ref PRCM_DOMAIN_POWER_OFF : Any of the domains are powered down. +// +//***************************************************************************** +extern uint32_t PRCMPowerDomainStatus(uint32_t ui32Domains); + +//***************************************************************************** +// +//! \brief Return the access status of the RF Core. +//! +//! Use this function to check if the RF Core is on and ready to be accessed. +//! Accessing register or memories that are not powered and clocked will +//! cause a bus fault. +//! +//! \return Returns access status of the RF Core. +//! - \c true : RF Core can be accessed. +//! - \c false : RF Core domain is not ready for access. +// +//***************************************************************************** +__STATIC_INLINE bool +PRCMRfReady(void) +{ + // Return the ready status of the RF Core. + return ((HWREG(PRCM_BASE + PRCM_O_PDSTAT1RFC) & + PRCM_PDSTAT1RFC_ON) ? true : false); +} + + +//***************************************************************************** +// +//! \brief Put the processor into sleep mode. +//! +//! This function places the processor into sleep mode; it does not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via PRCMPeripheralSleepEnable() continue to operate and can wake up the +//! processor. +//! +//! \return None +//! +//! \sa \ref PRCMPeripheralSleepEnable() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMSleep(void) +{ + // Wait for an interrupt. + CPUwfi(); +} + +//***************************************************************************** +// +//! \brief Put the processor into deep-sleep mode. +//! +//! This function places the processor into deep-sleep mode; it does not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via \ref PRCMPeripheralDeepSleepEnable() continue to operate and can wake up +//! the processor. +//! +//! \return None +//! +//! \sa \ref PRCMPeripheralDeepSleepEnable() +// +//***************************************************************************** +extern void PRCMDeepSleep(void); + +//***************************************************************************** +// +//! \brief Enable CACHE RAM retention +//! +//! Enables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMCacheRetentionEnable( void ) +{ + HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) |= PRCM_RAMRETEN_VIMS_M; +} + +//***************************************************************************** +// +//! \brief Disable CACHE RAM retention +//! +//! Disables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMCacheRetentionDisable( void ) +{ + HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) &= ~PRCM_RAMRETEN_VIMS_M; +} + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_PRCMInfClockConfigureSet + #undef PRCMInfClockConfigureSet + #define PRCMInfClockConfigureSet ROM_PRCMInfClockConfigureSet + #endif + #ifdef ROM_PRCMInfClockConfigureGet + #undef PRCMInfClockConfigureGet + #define PRCMInfClockConfigureGet ROM_PRCMInfClockConfigureGet + #endif + #ifdef ROM_PRCMAudioClockConfigSet + #undef PRCMAudioClockConfigSet + #define PRCMAudioClockConfigSet ROM_PRCMAudioClockConfigSet + #endif + #ifdef ROM_PRCMAudioClockConfigSetOverride + #undef PRCMAudioClockConfigSetOverride + #define PRCMAudioClockConfigSetOverride ROM_PRCMAudioClockConfigSetOverride + #endif + #ifdef ROM_PRCMAudioClockInternalSource + #undef PRCMAudioClockInternalSource + #define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource + #endif + #ifdef ROM_PRCMAudioClockExternalSource + #undef PRCMAudioClockExternalSource + #define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource + #endif + #ifdef ROM_PRCMPowerDomainOn + #undef PRCMPowerDomainOn + #define PRCMPowerDomainOn ROM_PRCMPowerDomainOn + #endif + #ifdef ROM_PRCMPowerDomainOff + #undef PRCMPowerDomainOff + #define PRCMPowerDomainOff ROM_PRCMPowerDomainOff + #endif + #ifdef ROM_PRCMPeripheralRunEnable + #undef PRCMPeripheralRunEnable + #define PRCMPeripheralRunEnable ROM_PRCMPeripheralRunEnable + #endif + #ifdef ROM_PRCMPeripheralRunDisable + #undef PRCMPeripheralRunDisable + #define PRCMPeripheralRunDisable ROM_PRCMPeripheralRunDisable + #endif + #ifdef ROM_PRCMPeripheralSleepEnable + #undef PRCMPeripheralSleepEnable + #define PRCMPeripheralSleepEnable ROM_PRCMPeripheralSleepEnable + #endif + #ifdef ROM_PRCMPeripheralSleepDisable + #undef PRCMPeripheralSleepDisable + #define PRCMPeripheralSleepDisable ROM_PRCMPeripheralSleepDisable + #endif + #ifdef ROM_PRCMPeripheralDeepSleepEnable + #undef PRCMPeripheralDeepSleepEnable + #define PRCMPeripheralDeepSleepEnable ROM_PRCMPeripheralDeepSleepEnable + #endif + #ifdef ROM_PRCMPeripheralDeepSleepDisable + #undef PRCMPeripheralDeepSleepDisable + #define PRCMPeripheralDeepSleepDisable ROM_PRCMPeripheralDeepSleepDisable + #endif + #ifdef ROM_PRCMPowerDomainStatus + #undef PRCMPowerDomainStatus + #define PRCMPowerDomainStatus ROM_PRCMPowerDomainStatus + #endif + #ifdef ROM_PRCMDeepSleep + #undef PRCMDeepSleep + #define PRCMDeepSleep ROM_PRCMDeepSleep + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PRCM_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.c new file mode 100644 index 0000000..a20da9a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.c @@ -0,0 +1,80 @@ +/****************************************************************************** +* Filename: pwr_ctrl.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Power Control driver. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "pwr_ctrl.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef PowerCtrlSourceSet + #define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet +#endif + + +//***************************************************************************** +// +// Set (Request) the main power source +// +//***************************************************************************** +void +PowerCtrlSourceSet(uint32_t ui32PowerConfig) +{ + // Check the arguments. + ASSERT((ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) || + (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) || + (ui32PowerConfig == PWRCTRL_PWRSRC_ULDO)); + + // Configure the power. + if(ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) { + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) |= + (AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE); + } + else if (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) + { + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &= + ~(AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE); + } + else + { + PRCMMcuUldoConfigure(true); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h new file mode 100644 index 0000000..59b0069 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h @@ -0,0 +1,301 @@ +/****************************************************************************** +* Filename: pwr_ctrl.h +* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) +* Revision: 50165 +* +* Description: Defines and prototypes for the System Power Control. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup pwrctrl_api +//! @{ +// +//***************************************************************************** + +#ifndef __PWR_CTRL_H__ +#define __PWR_CTRL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aon_pmctl.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_adi_2_refsys.h" +#include "debug.h" +#include "interrupt.h" +#include "osc.h" +#include "cpu.h" +#include "prcm.h" +#include "aon_ioc.h" +#include "adi.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet +#endif + +//***************************************************************************** +// +// Defines for the system power states +// +//***************************************************************************** +#define PWRCTRL_ACTIVE 0x00000001 +#define PWRCTRL_STANDBY 0x00000002 +#define PWRCTRL_POWER_DOWN 0x00000004 +#define PWRCTRL_SHUTDOWN 0x00000008 + +//***************************************************************************** +// +// Defines for the power configuration in the AON System Control 1.2 V +// +//***************************************************************************** +#define PWRCTRL_IOSEG3_ENABLE 0x00000800 +#define PWRCTRL_IOSEG2_ENABLE 0x00000400 +#define PWRCTRL_IOSEG3_DISABLE 0x00000200 +#define PWRCTRL_IOSEG2_DISABLE 0x00000100 +#define PWRCTRL_PWRSRC_DCDC 0x00000001 +#define PWRCTRL_PWRSRC_GLDO 0x00000000 +#define PWRCTRL_PWRSRC_ULDO 0x00000002 + +//***************************************************************************** +// +// The following are defines for the various reset source for the device. +// +//***************************************************************************** +#define PWRCTRL_RST_POWER_ON 0x00000000 // Reset by power on +#define PWRCTRL_RST_PIN 0x00000001 // Pin reset +#define PWRCTRL_RST_VDDS_BOD 0x00000002 // VDDS Brown Out Detect +#define PWRCTRL_RST_VDD_BOD 0x00000003 // VDD Brown Out Detect +#define PWRCTRL_RST_VDDR_BOD 0x00000004 // VDDR Brown Out Detect +#define PWRCTRL_RST_CLK_LOSS 0x00000005 // Clock loss Reset +#define PWRCTRL_RST_SW_PIN 0x00000006 // SYSRESET or pin reset +#define PWRCTRL_RST_WARM 0x00000007 // Reset via PRCM warm reset request + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Set (Request) the main power source. +//! +//! \note The system will never allow a switch to the \ref PWRCTRL_PWRSRC_ULDO +//! when in active mode. This is only allowed when the system is in lower power +//! mode where no code is executing and no peripherals are active. +//! Assuming that there is an external capacitor available for the +//! \ref PWRCTRL_PWRSRC_DCDC the system can dynamically switch back and forth +//! between the two when in active mode. +//! +//! \note The system will automatically switch to the GLDO / DCDC when waking +//! up from a low power mode. +//! +//! \param ui32PowerConfig is a bitmask indicating the target power source. +//! - \ref PWRCTRL_PWRSRC_DCDC +//! - \ref PWRCTRL_PWRSRC_GLDO +//! - \ref PWRCTRL_PWRSRC_ULDO +//! +//! \return None +// +//***************************************************************************** +extern void PowerCtrlSourceSet(uint32_t ui32PowerConfig); + +//***************************************************************************** +// +//! \brief Get the main power source. +//! +//! Use this function to retrieve the current active power source. +//! +//! When the System CPU is active it can never be powered by uLDO as this +//! is too weak a power source. +//! +//! \note Using the DCDC power supply requires an external inductor. +//! +//! \return Returns the main power source. +//! - \ref PWRCTRL_PWRSRC_DCDC +//! - \ref PWRCTRL_PWRSRC_GLDO +// +//***************************************************************************** +__STATIC_INLINE uint32_t +PowerCtrlSourceGet(void) +{ + uint32_t ui32PowerConfig; + + // Return the current power source + ui32PowerConfig = HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL); + if(ui32PowerConfig & AON_PMCTL_PWRCTL_DCDC_ACTIVE) + { + return (PWRCTRL_PWRSRC_DCDC); + } + else + { + return (PWRCTRL_PWRSRC_GLDO); + } +} + +//***************************************************************************** +// +//! \brief OBSOLETE: Get the last known reset source of the system. +//! +//! \deprecated This function will be removed in a future release. +//! Use \ref SysCtrlResetSourceGet() instead. +//! +//! This function returns reset source but does not cover if waking up from shutdown. +//! This function can be seen as a subset of function \ref SysCtrlResetSourceGet() +//! and will be removed in a future release. +//! +//! \return Returns one of the known reset values. +//! The possible reset sources are: +//! - \ref PWRCTRL_RST_POWER_ON +//! - \ref PWRCTRL_RST_PIN +//! - \ref PWRCTRL_RST_VDDS_BOD +//! - \ref PWRCTRL_RST_VDD_BOD +//! - \ref PWRCTRL_RST_VDDR_BOD +//! - \ref PWRCTRL_RST_CLK_LOSS +//! - \ref PWRCTRL_RST_SW_PIN +//! - \ref PWRCTRL_RST_WARM +//! +//! \sa \ref SysCtrlResetSourceGet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +PowerCtrlResetSourceGet(void) +{ + // Get the reset source. + return (( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & + AON_PMCTL_RESETCTL_RESET_SRC_M ) >> + AON_PMCTL_RESETCTL_RESET_SRC_S ) ; +} + +//***************************************************************************** +// +//! \brief Enables pad sleep in order to latch device outputs before shutdown. +//! +//! See \ref SysCtrlShutdown() for more information about how to enter +//! shutdown and how to wake up from shutdown. +//! +//! \return None +//! +//! \sa \ref PowerCtrlPadSleepDisable() +// +//***************************************************************************** +__STATIC_INLINE void +PowerCtrlPadSleepEnable(void) +{ + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL) = 0; + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! \brief Disables pad sleep in order to unlatch device outputs after wakeup from shutdown. +//! +//! This function must be called by the application after the device wakes up +//! from shutdown. +//! +//! See \ref SysCtrlShutdown() for more information about how to enter +//! shutdown and how to wake up from shutdown. +//! +//! \return None +//! +//! \sa \ref PowerCtrlPadSleepEnable() +// +//***************************************************************************** +__STATIC_INLINE void +PowerCtrlPadSleepDisable(void) +{ + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL) = 1; + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_PowerCtrlSourceSet + #undef PowerCtrlSourceSet + #define PowerCtrlSourceSet ROM_PowerCtrlSourceSet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PWR_CTRL_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h new file mode 100644 index 0000000..a8da556 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h @@ -0,0 +1,2674 @@ +/****************************************************************************** +* Filename: rf_ble_cmd.h +* Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018) +* Revision: 18572 +* +* Description: CC13x2/CC26x2 API for Bluetooth Low Energy commands +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __BLE_CMD_H +#define __BLE_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup ble_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_bleRadioOp_s rfc_bleRadioOp_t; +typedef struct __RFC_STRUCT rfc_ble5RadioOp_s rfc_ble5RadioOp_t; +typedef struct __RFC_STRUCT rfc_ble5Tx20RadioOp_s rfc_ble5Tx20RadioOp_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s rfc_CMD_BLE_SLAVE_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s rfc_CMD_BLE_MASTER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_s rfc_CMD_BLE_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s rfc_CMD_BLE_ADV_DIR_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s rfc_CMD_BLE_ADV_NC_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s rfc_CMD_BLE_ADV_SCAN_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s rfc_CMD_BLE_SCANNER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s rfc_CMD_BLE_INITIATOR_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s rfc_CMD_BLE_GENERIC_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s rfc_CMD_BLE_TX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s rfc_CMD_BLE_ADV_PAYLOAD_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s rfc_CMD_BLE5_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_SLAVE_s rfc_CMD_BLE5_SLAVE_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_MASTER_s rfc_CMD_BLE5_MASTER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_EXT_s rfc_CMD_BLE5_ADV_EXT_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_AUX_s rfc_CMD_BLE5_ADV_AUX_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_SCANNER_s rfc_CMD_BLE5_SCANNER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_INITIATOR_s rfc_CMD_BLE5_INITIATOR_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_GENERIC_RX_s rfc_CMD_BLE5_GENERIC_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_TX_TEST_s rfc_CMD_BLE5_TX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_s rfc_CMD_BLE5_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_DIR_s rfc_CMD_BLE5_ADV_DIR_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_NC_s rfc_CMD_BLE5_ADV_NC_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_SCAN_s rfc_CMD_BLE5_ADV_SCAN_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_PA_s rfc_CMD_BLE5_RADIO_SETUP_PA_t; +typedef struct __RFC_STRUCT rfc_bleMasterSlavePar_s rfc_bleMasterSlavePar_t; +typedef struct __RFC_STRUCT rfc_bleSlavePar_s rfc_bleSlavePar_t; +typedef struct __RFC_STRUCT rfc_bleMasterPar_s rfc_bleMasterPar_t; +typedef struct __RFC_STRUCT rfc_bleAdvPar_s rfc_bleAdvPar_t; +typedef struct __RFC_STRUCT rfc_bleScannerPar_s rfc_bleScannerPar_t; +typedef struct __RFC_STRUCT rfc_bleInitiatorPar_s rfc_bleInitiatorPar_t; +typedef struct __RFC_STRUCT rfc_bleGenericRxPar_s rfc_bleGenericRxPar_t; +typedef struct __RFC_STRUCT rfc_bleTxTestPar_s rfc_bleTxTestPar_t; +typedef struct __RFC_STRUCT rfc_ble5SlavePar_s rfc_ble5SlavePar_t; +typedef struct __RFC_STRUCT rfc_ble5MasterPar_s rfc_ble5MasterPar_t; +typedef struct __RFC_STRUCT rfc_ble5AdvExtPar_s rfc_ble5AdvExtPar_t; +typedef struct __RFC_STRUCT rfc_ble5AdvAuxPar_s rfc_ble5AdvAuxPar_t; +typedef struct __RFC_STRUCT rfc_ble5AuxChRes_s rfc_ble5AuxChRes_t; +typedef struct __RFC_STRUCT rfc_ble5ScannerPar_s rfc_ble5ScannerPar_t; +typedef struct __RFC_STRUCT rfc_ble5InitiatorPar_s rfc_ble5InitiatorPar_t; +typedef struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s rfc_bleMasterSlaveOutput_t; +typedef struct __RFC_STRUCT rfc_bleAdvOutput_s rfc_bleAdvOutput_t; +typedef struct __RFC_STRUCT rfc_bleScannerOutput_s rfc_bleScannerOutput_t; +typedef struct __RFC_STRUCT rfc_bleInitiatorOutput_s rfc_bleInitiatorOutput_t; +typedef struct __RFC_STRUCT rfc_ble5ScanInitOutput_s rfc_ble5ScanInitOutput_t; +typedef struct __RFC_STRUCT rfc_bleGenericRxOutput_s rfc_bleGenericRxOutput_t; +typedef struct __RFC_STRUCT rfc_bleTxTestOutput_s rfc_bleTxTestOutput_t; +typedef struct __RFC_STRUCT rfc_ble5ExtAdvEntry_s rfc_ble5ExtAdvEntry_t; +typedef struct __RFC_STRUCT rfc_bleWhiteListEntry_s rfc_bleWhiteListEntry_t; +typedef struct __RFC_STRUCT rfc_ble5AdiEntry_s rfc_ble5AdiEntry_t; +typedef struct __RFC_STRUCT rfc_bleRxStatus_s rfc_bleRxStatus_t; +typedef struct __RFC_STRUCT rfc_ble5RxStatus_s rfc_ble5RxStatus_t; + +//! \addtogroup bleRadioOp +//! @{ +struct __RFC_STRUCT rfc_bleRadioOp_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + uint8_t* pParams; //!< Pointer to command specific parameter structure + uint8_t* pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5RadioOp +//! @{ +struct __RFC_STRUCT rfc_ble5RadioOp_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + uint8_t* pParams; //!< Pointer to command specific parameter structure + uint8_t* pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5Tx20RadioOp +//! @{ +//! Command structure for Bluetooth commands which includes the optional field for 20-dBm PA TX power +struct __RFC_STRUCT rfc_ble5Tx20RadioOp_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + uint8_t* pParams; //!< Pointer to command specific parameter structure + uint8_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_SLAVE +//! @{ +#define CMD_BLE_SLAVE 0x1801 +//! BLE Slave Command +struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s { + uint16_t commandNo; //!< The command ID number 0x1801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleSlavePar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_MASTER +//! @{ +#define CMD_BLE_MASTER 0x1802 +//! BLE Master Command +struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s { + uint16_t commandNo; //!< The command ID number 0x1802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleMasterPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV +//! @{ +#define CMD_BLE_ADV 0x1803 +//! BLE Connectable Undirected Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_s { + uint16_t commandNo; //!< The command ID number 0x1803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_DIR +//! @{ +#define CMD_BLE_ADV_DIR 0x1804 +//! BLE Connectable Directed Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s { + uint16_t commandNo; //!< The command ID number 0x1804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_NC +//! @{ +#define CMD_BLE_ADV_NC 0x1805 +//! BLE Non-Connectable Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s { + uint16_t commandNo; //!< The command ID number 0x1805 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_SCAN +//! @{ +#define CMD_BLE_ADV_SCAN 0x1806 +//! BLE Scannable Undirected Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s { + uint16_t commandNo; //!< The command ID number 0x1806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_SCANNER +//! @{ +#define CMD_BLE_SCANNER 0x1807 +//! BLE Scanner Command +struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s { + uint16_t commandNo; //!< The command ID number 0x1807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleScannerPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleScannerOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_INITIATOR +//! @{ +#define CMD_BLE_INITIATOR 0x1808 +//! BLE Initiator Command +struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s { + uint16_t commandNo; //!< The command ID number 0x1808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleInitiatorPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleInitiatorOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_GENERIC_RX +//! @{ +#define CMD_BLE_GENERIC_RX 0x1809 +//! BLE Generic Receiver Command +struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s { + uint16_t commandNo; //!< The command ID number 0x1809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleGenericRxPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleGenericRxOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_TX_TEST +//! @{ +#define CMD_BLE_TX_TEST 0x180A +//! BLE PHY Test Transmitter Command +struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x180A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleTxTestPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleTxTestOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_PAYLOAD +//! @{ +#define CMD_BLE_ADV_PAYLOAD 0x1001 +//! BLE Update Advertising Payload Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s { + uint16_t commandNo; //!< The command ID number 0x1001 + uint8_t payloadType; //!< \brief 0: Advertising data
+ //!< 1: Scan response data + uint8_t newLen; //!< Length of the new payload + uint8_t* pNewData; //!< Pointer to the buffer containing the new data + rfc_bleAdvPar_t *pParams; //!< Pointer to the parameter structure to update +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_RADIO_SETUP +//! @{ +#define CMD_BLE5_RADIO_SETUP 0x1820 +//! Bluetooth 5 Radio Setup Command for all PHYs +struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x1820 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t mainMode:2; //!< \brief PHY to use for non-BLE commands:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:1; //!< \brief Coding to use for TX if coded PHY is selected for non-BLE commands
+ //!< 0: S = 8 (125 kbps)
+ //!< 1: S = 2 (500 kbps) + } defaultPhy; + uint8_t loDivider; //!< LO divider setting to use. Supported values: 0 or 2. + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Default transmit power + uint32_t* pRegOverrideCommon; //!< \brief Pointer to a list of hardware and configuration registers to override during common + //!< initialization. If NULL, no override is used. + uint32_t* pRegOverride1Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< 1 Mbps PHY mode. If NULL, no override is used. + uint32_t* pRegOverride2Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< 2 Mbps PHY mode. If NULL, no override is used. + uint32_t* pRegOverrideCoded; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< coded PHY mode. If NULL, no override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_SLAVE +//! @{ +#define CMD_BLE5_SLAVE 0x1821 +//! Bluetooth 5 Slave Command +struct __RFC_STRUCT rfc_CMD_BLE5_SLAVE_s { + uint16_t commandNo; //!< The command ID number 0x1821 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5SlavePar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_MASTER +//! @{ +#define CMD_BLE5_MASTER 0x1822 +//! Bluetooth 5 Master Command +struct __RFC_STRUCT rfc_CMD_BLE5_MASTER_s { + uint16_t commandNo; //!< The command ID number 0x1822 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5MasterPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_ADV_EXT +//! @{ +#define CMD_BLE5_ADV_EXT 0x1823 +//! Bluetooth 5 Extended Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE5_ADV_EXT_s { + uint16_t commandNo; //!< The command ID number 0x1823 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5AdvExtPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_ADV_AUX +//! @{ +#define CMD_BLE5_ADV_AUX 0x1824 +//! Bluetooth 5 Secondary Channel Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE5_ADV_AUX_s { + uint16_t commandNo; //!< The command ID number 0x1824 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5AdvAuxPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_SCANNER +//! @{ +#define CMD_BLE5_SCANNER 0x1827 +//! Bluetooth 5 Scanner Command +struct __RFC_STRUCT rfc_CMD_BLE5_SCANNER_s { + uint16_t commandNo; //!< The command ID number 0x1827 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5ScannerPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_ble5ScanInitOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_INITIATOR +//! @{ +#define CMD_BLE5_INITIATOR 0x1828 +//! Bluetooth 5 Initiator Command +struct __RFC_STRUCT rfc_CMD_BLE5_INITIATOR_s { + uint16_t commandNo; //!< The command ID number 0x1828 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5InitiatorPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_ble5ScanInitOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_GENERIC_RX +//! @{ +#define CMD_BLE5_GENERIC_RX 0x1829 +//! Bluetooth 5 Generic Receiver Command +struct __RFC_STRUCT rfc_CMD_BLE5_GENERIC_RX_s { + uint16_t commandNo; //!< The command ID number 0x1829 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleGenericRxPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleGenericRxOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_TX_TEST +//! @{ +#define CMD_BLE5_TX_TEST 0x182A +//! Bluetooth 5 PHY Test Transmitter Command +struct __RFC_STRUCT rfc_CMD_BLE5_TX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x182A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleTxTestPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleTxTestOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_ADV +//! @{ +#define CMD_BLE5_ADV 0x182B +//! Bluetooth 5 Connectable Undirected Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE5_ADV_s { + uint16_t commandNo; //!< The command ID number 0x182B + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_ADV_DIR +//! @{ +#define CMD_BLE5_ADV_DIR 0x182C +//! Bluetooth 5 Connectable Directed Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE5_ADV_DIR_s { + uint16_t commandNo; //!< The command ID number 0x182C + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_ADV_NC +//! @{ +#define CMD_BLE5_ADV_NC 0x182D +//! Bluetooth 5 Non-Connectable Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE5_ADV_NC_s { + uint16_t commandNo; //!< The command ID number 0x182D + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_ADV_SCAN +//! @{ +#define CMD_BLE5_ADV_SCAN 0x182E +//! Bluetooth 5 Scannable Undirected Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE5_ADV_SCAN_s { + uint16_t commandNo; //!< The command ID number 0x182E + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_RADIO_SETUP_PA +//! @{ +//! Bluetooth 5 Radio Setup Command for all PHYs with PA Switching Fields +struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_PA_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t mainMode:2; //!< \brief PHY to use for non-BLE commands:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:1; //!< \brief Coding to use for TX if coded PHY is selected for non-BLE commands
+ //!< 0: S = 8 (125 kbps)
+ //!< 1: S = 2 (500 kbps) + } defaultPhy; + uint8_t loDivider; //!< LO divider setting to use. Supported values: 0 or 2. + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Default transmit power + uint32_t* pRegOverrideCommon; //!< \brief Pointer to a list of hardware and configuration registers to override during common + //!< initialization. If NULL, no override is used. + uint32_t* pRegOverride1Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< 1 Mbps PHY mode. If NULL, no override is used. + uint32_t* pRegOverride2Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< 2 Mbps PHY mode. If NULL, no override is used. + uint32_t* pRegOverrideCoded; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< coded PHY mode. If NULL, no override is used. + uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< standard PA. Used by RF driver only, not radio CPU. + uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< 20-dBm PA. Used by RF driver only, not radio CPU. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleMasterSlavePar +//! @{ +struct __RFC_STRUCT rfc_bleMasterSlavePar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleSlavePar +//! @{ +//! Parameter structure for legacy slave (CMD_BLE_SLAVE) + +struct __RFC_STRUCT rfc_bleSlavePar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first + //!< receive operation + uint16_t __dummy0; + uint8_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleMasterPar +//! @{ +//! Parameter structure for legacy master (CMD_BLE_MASTER) + +struct __RFC_STRUCT rfc_bleMasterPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleAdvPar +//! @{ +//! Parameter structure for legacy advertiser (CMD_BLE_ADV* and CMD_BLE5_ADV*) + +struct __RFC_STRUCT rfc_bleAdvPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t advFilterPolicy:2; //!< \brief Advertiser filter policy
+ //!< 0: Process scan and connect requests from all devices
+ //!< 1: Process connect requests from all devices and only scan requests from + //!< devices that are in the white list
+ //!< 2: Process scan requests from all devices and only connect requests from + //!< devices that are in the white list
+ //!< 3: Process scan and connect requests only from devices in the white list + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType:1; //!< Directed advertiser: The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2
+ //!< 1: Report support of Channel Selection Algorithm #2 + uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used + //!< 1: Filter on bPrivIgn always + uint8_t rpaMode:1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } advConfig; + uint8_t advLen; //!< Size of advertiser data + uint8_t scanRspLen; //!< Size of scan response data + uint8_t* pAdvData; //!< Pointer to buffer containing ADV*_IND data + uint8_t* pScanRspData; //!< Pointer to buffer containing SCAN_RSP data + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< advConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed + //!< advertiser). If least significant bit is 1, the address type given by + //!< advConfig.peerAddrType is inverted. + struct { + uint8_t scanRspEndType:1; //!< \brief Command status at end if SCAN_RSP was sent:
+ //!< 0: End with BLE_DONE_OK and result True
+ //!< 1: End with BLE_DONE_SCAN_RSP and result False + } behConfig; + uint8_t __dummy0; + uint8_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the advertiser event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< advertiser event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleScannerPar +//! @{ +//! Parameter structure for legacy scanner (CMD_BLE_SCANNER) + +struct __RFC_STRUCT rfc_bleScannerPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t scanFilterPolicy:1; //!< \brief Scanning filter policy regarding advertiser address
+ //!< 0: Accept all advertisement packets
+ //!< 1: Accept only advertisement packets from devices where the advertiser's address + //!< is in the white list + uint8_t bActiveScan:1; //!< \brief 0: Passive scan
+ //!< 1: Active scan + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t rpaFilterPolicy:1; //!< \brief Filter policy for initA for ADV_DIRECT_IND messages
+ //!< 0: Accept only initA that matches own address
+ //!< 1: Also accept all resolvable private addresses + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU
+ //!< 1: Automatically set ignore bit in white list + uint8_t bEndOnRpt:1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
+ //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP + uint8_t rpaMode:1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } scanConfig; + uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure + uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec + struct { + uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure + uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit + //!< not changed + uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not + //!< changed + } backoffPar; + uint8_t scanReqLen; //!< Size of scan request data + uint8_t* pScanReqData; //!< Pointer to buffer containing SCAN_REQ data + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< scanConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list + uint16_t __dummy0; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleInitiatorPar +//! @{ +//! Parameter structure for legacy initiator (CMD_BLE_INITIATOR) + +struct __RFC_STRUCT rfc_bleInitiatorPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t bUseWhiteList:1; //!< \brief Initiator filter policy
+ //!< 0: Use specific peer address
+ //!< 1: Use white list + uint8_t bDynamicWinOffset:1; //!< \brief 0: No dynamic WinOffset insertion
+ //!< 1: Use dynamic WinOffset insertion + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType:1; //!< The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2
+ //!< 1: Report support of Channel Selection Algorithm #2 + } initConfig; + uint8_t __dummy0; + uint8_t connectReqLen; //!< Size of connect request data + uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_IND (CONNECT_REQ) + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< initConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address. If least + //!< significant bit is 1, the address type given by initConfig.peerAddrType + //!< is inverted. + ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. + //!< Set to the calculated value if a connection is made and to the next possible connection + //!< time if not. + uint16_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleGenericRxPar +//! @{ +//! Parameter structure for generic Rx (CMD_BLE_GENERIC_RX and CMD_BLE5_GENERIC_RX) + +struct __RFC_STRUCT rfc_bleGenericRxPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue. May be NULL; if so, received packets are not stored + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + uint8_t bRepeat; //!< \brief 0: End operation after receiving a packet
+ //!< 1: Restart receiver after receiving a packet + uint16_t __dummy0; + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Rx operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleTxTestPar +//! @{ +//! Parameter structure for Tx test (CMD_BLE_TX_TEST and CMD_BLE5_TX_TEST) + +struct __RFC_STRUCT rfc_bleTxTestPar_s { + uint16_t numPackets; //!< \brief Number of packets to transmit
+ //!< 0: Transmit unlimited number of packets + uint8_t payloadLength; //!< The number of payload bytes in each packet. + uint8_t packetType; //!< \brief The packet type to be used, encoded according to the Bluetooth 5.0 spec, Volume 6, Part F, + //!< Section 4.1.4 + ratmr_t period; //!< Number of radio timer cycles between the start of each packet + struct { + uint8_t bOverrideDefault:1; //!< \brief 0: Use default packet encoding
+ //!< 1: Override packet contents + uint8_t bUsePrbs9:1; //!< \brief If bOverride is 1:
+ //!< 0: No PRBS9 encoding of packet
+ //!< 1: Use PRBS9 encoding of packet + uint8_t bUsePrbs15:1; //!< \brief If bOverride is 1:
+ //!< 0: No PRBS15 encoding of packet
+ //!< 1: Use PRBS15 encoding of packet + } config; + uint8_t byteVal; //!< If config.bOverride is 1, value of each byte to be sent + uint8_t __dummy0; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Test Tx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Test Tx operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5SlavePar +//! @{ +//! Parameter structure for Bluetooth 5 slave (CMD_BLE5_SLAVE) + +struct __RFC_STRUCT rfc_ble5SlavePar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first + //!< receive operation + uint8_t maxRxPktLen; //!< Maximum packet length currently allowed for received packets on the connection + uint8_t maxLenLowRate; //!< Maximum packet length for which using S = 8 (125 kbps) is allowed when transmitting. 0: no limit. + uint8_t __dummy0; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5MasterPar +//! @{ +//! Parameter structure for Bluetooth 5 master (CMD_BLE5_MASTER) + +struct __RFC_STRUCT rfc_ble5MasterPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed + uint8_t maxRxPktLen; //!< Maximum packet length currently allowed for received packets on the connection + uint8_t maxLenLowRate; //!< Maximum packet length for which using S = 8 (125 kbps) is allowed when transmitting. 0: no limit. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5AdvExtPar +//! @{ +//! Parameter structure for extended advertiser (CMD_BLE5_ADV_EXT) + +struct __RFC_STRUCT rfc_ble5AdvExtPar_s { + struct { + uint8_t :2; + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + } advConfig; + uint8_t __dummy0; + uint8_t __dummy1; + uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types, + //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed + ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points + uint8_t* pAdvPkt; //!< Pointer to extended advertising packet for the ADV_EXT_IND packet + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< advConfig.deviceAddrType is inverted. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5AdvAuxPar +//! @{ +//! Parameter structure for secondary channel advertiser (CMD_BLE5_ADV_AUX) + +struct __RFC_STRUCT rfc_ble5AdvAuxPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t advFilterPolicy:2; //!< \brief Advertiser filter policy
+ //!< 0: Process scan and connect requests from all devices
+ //!< 1: Process connect requests from all devices and only scan requests from + //!< devices that are in the white list
+ //!< 2: Process scan requests from all devices and only connect requests from + //!< devices that are in the white list
+ //!< 3: Process scan and connect requests only from devices in the white list + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t targetAddrType:1; //!< Directed secondary advertiser: The type of the target address -- public (0) or random (1) + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t bDirected:1; //!< \brief 0: Advertiser is undirected: pWhiteList points to a white list + //!< 1: Advertiser is directed: pWhiteList points to a single device address + uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used + //!< 1: Filter on bPrivIgn always + uint8_t rpaMode:1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } advConfig; + struct { + uint8_t scanRspEndType:1; //!< \brief Command status at end if AUX_SCAN_RSP was sent:
+ //!< 0: End with BLE_DONE_OK and result True
+ //!< 1: End with BLE_DONE_SCAN_RSP and result False + } behConfig; + uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types, + //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed + ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points + uint8_t* pAdvPkt; //!< Pointer to extended advertising packet for the ADV_AUX_IND packet + uint8_t* pRspPkt; //!< \brief Pointer to extended advertising packet for the AUX_SCAN_RSP or AUX_CONNECT_RSP packet + //!< (may be NULL if not applicable) + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< advConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed + //!< advertiser). If least significant bit is 1, the address type given by + //!< advConfig.peerAddrType is inverted. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5AuxChRes +//! @{ +struct __RFC_STRUCT rfc_ble5AuxChRes_s { + ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet + uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet + uint8_t channelNo; //!< The channel index used for secondary advertising + uint8_t phyMode; //!< \brief PHY to use on secondary channel:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< Others: Reserved +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5ScannerPar +//! @{ +//! Parameter structure for Bluetooth 5 scanner (CMD_BLE5_SCANNER) + +struct __RFC_STRUCT rfc_ble5ScannerPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t scanFilterPolicy:1; //!< \brief Scanning filter policy regarding advertiser address
+ //!< 0: Accept all advertisement packets
+ //!< 1: Accept only advertisement packets from devices where the advertiser's address + //!< is in the White list. + uint8_t bActiveScan:1; //!< \brief 0: Passive scan
+ //!< 1: Active scan + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t rpaFilterPolicy:1; //!< \brief Filter policy for initA of ADV_DIRECT_IND messages
+ //!< 0: Accept only initA that matches own address
+ //!< 1: Also accept all resolvable private addresses + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for legacy packets
+ //!< 1: Automatically set ignore bit in white list for legacy packets + uint8_t bEndOnRpt:1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
+ //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP + uint8_t rpaMode:1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } scanConfig; + uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure + uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec + struct { + uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure + uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit + //!< not changed + uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not + //!< changed + } backoffPar; + struct { + uint8_t bCheckAdi:1; //!< \brief 0: Do not perform ADI filtering
+ //!< 1: Perform ADI filtering on packets where ADI is present + uint8_t bAutoAdiUpdate:1; //!< \brief 0: Do not update ADI entries in radio CPU using legacy mode (recommended)
+ //!< 1: Legacy mode: Automatically update ADI entry for received packets with + //!< AdvDataInfo after first occurrence + uint8_t bApplyDuplicateFiltering:1;//!< \brief 0: Do not apply duplicate filtering based on device address for extended + //!< advertiser packets (recommended)
+ //!< 1: Apply duplicate filtering based on device address for extended advertiser + //!< packets with no ADI field + uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for extended advertising packets
+ //!< 1: Automatically set ignore bit in white list for extended advertising packets + uint8_t bAutoAdiProcess:1; //!< \brief 0: Do not use automatic ADI processing
+ //!< 1: Automatically update ADI entry for received packets so that only the same + //!< ADI is accepted for the rest of the chain and the SID/DID combination is + //!< ignored after the entire chain is received. + uint8_t bExclusiveSid:1; //!< \brief 0: Set adiStatus.state to 0 when command starts so that all + //!< valid SIDs are accepted
+ //!< 1: Do not modify adiStatus.state when command starts
+ } extFilterConfig; + struct { + uint8_t lastAcceptedSid:4; //!< Indication of SID of last successfully received packet that was not ignored + uint8_t state:3; //!< \brief 0: No extended packet received, or last extended packet didn't have an ADI; + //!< lastAcceptedSid field is not valid
+ //!< 1: A message with ADI has been received, but no chain is under reception; + //!< ADI filtering to be performed normally
+ //!< 2: A message with SID as given in lastAcceptedSid has been + //!< received, and chained messages are still pending. Messages without this + //!< SID will be ignored
+ //!< 3: An AUX_SCAN_RSP message has been received after receiving messages with SID + //!< as given in lastAcceptedSid, and chained messages are + //!< pending. Messages with an ADI field will be ignored.
+ //!< 4: A message with no ADI has been received, and chained messages are still + //!< pending. Messages with an ADI field will be ignored.
+ //!< Others: Reserved + } adiStatus; + uint8_t __dummy0; + uint16_t __dummy1; + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< scanConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list + rfc_ble5AdiEntry_t *pAdiList; //!< Pointer to advDataInfo list + uint16_t maxWaitTimeForAuxCh; //!< \brief Maximum wait time for switching to secondary scanning withing the command. If the time + //!< to the start of the event is greater than this, the command will end with BLE_DONE_AUX. + //!< If it is smaller, the radio will automatically switch to the correct channel and PHY. + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED + ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet + uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet + uint8_t channelNo; //!< The channel index used for secondary advertising + uint8_t phyMode; //!< \brief PHY to use on secondary channel:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< Others: Reserved +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5InitiatorPar +//! @{ +//! Parameter structure for Bluetooth 5 initiator (CMD_BLE5_INITIATOR) + +struct __RFC_STRUCT rfc_ble5InitiatorPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t bUseWhiteList:1; //!< \brief Initiator filter policy
+ //!< 0: Use specific peer address
+ //!< 1: Use white list + uint8_t bDynamicWinOffset:1; //!< 1: Use dynamic WinOffset insertion + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType:1; //!< The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2 in CONNECT_IND
+ //!< 1: Report support of Channel Selection Algorithm #2 in CONNECT_IND + } initConfig; + uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure + uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec + struct { + uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure + uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit + //!< not changed + uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not + //!< changed + } backoffPar; + uint8_t connectReqLen; //!< Size of connect request data + uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_IND or AUX_CONNECT_REQ packet + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< initConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address. If least + //!< significant bit is 1, the address type given by initConfig.peerAddrType + //!< is inverted. + ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. + //!< Set to the calculated value if a connection is made and to the next possible connection + //!< time if not. + uint16_t maxWaitTimeForAuxCh; //!< \brief Maximum wait time for switching to secondary scanning withing the command. If the time + //!< to the start of the event is greater than this, the command will end with BLE_DONE_AUX. + //!< If it is smaller, the radio will automatically switch to the correct channel and PHY. + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED + ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet + uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet + uint8_t channelNo; //!< The channel index used for secondary advertising + uint8_t phyMode; //!< \brief PHY to use on secondary channel:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< Others: Reserved +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleMasterSlaveOutput +//! @{ +//! Output structure for master and slave (CMD_BLE_MASTER/CMD_BLE_SLAVE/CMD_BLE5_MASTER/CMD_BLE5_SLAVE) + +struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s { + uint8_t nTx; //!< \brief Total number of packets (including auto-empty and retransmissions) that have been + //!< transmitted + uint8_t nTxAck; //!< Total number of transmitted packets (including auto-empty) that have been ACK'ed + uint8_t nTxCtrl; //!< Number of unique LL control packets from the Tx queue that have been transmitted + uint8_t nTxCtrlAck; //!< Number of LL control packets from the Tx queue that have been finished (ACK'ed) + uint8_t nTxCtrlAckAck; //!< \brief Number of LL control packets that have been ACK'ed and where an ACK has been sent in + //!< response + uint8_t nTxRetrans; //!< Number of retransmissions that has been done + uint8_t nTxEntryDone; //!< Number of packets from the Tx queue that have been finished (ACK'ed) + uint8_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint8_t nRxCtrl; //!< Number of LL control packets that have been received with CRC OK and not ignored + uint8_t nRxCtrlAck; //!< \brief Number of LL control packets that have been received with CRC OK and not ignored, and + //!< then ACK'ed + uint8_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< \brief Number of packets that have been received with CRC OK and ignored due to repeated + //!< sequence number + uint8_t nRxEmpty; //!< Number of packets that have been received with CRC OK and no payload + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet (signed) + struct { + uint8_t bTimeStampValid:1; //!< 1 if a valid time stamp has been written to timeStamp; 0 otherwise + uint8_t bLastCrcErr:1; //!< 1 if the last received packet had CRC error; 0 otherwise + uint8_t bLastIgnored:1; //!< 1 if the last received packet with CRC OK was ignored; 0 otherwise + uint8_t bLastEmpty:1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise + uint8_t bLastCtrl:1; //!< 1 if the last received packet with CRC OK was an LL control packet; 0 otherwise + uint8_t bLastMd:1; //!< 1 if the last received packet with CRC OK had MD = 1; 0 otherwise + uint8_t bLastAck:1; //!< \brief 1 if the last received packet with CRC OK was an ACK of a transmitted packet; + //!< 0 otherwise + } pktStatus; //!< Status of received packets + ratmr_t timeStamp; //!< Slave operation: Time stamp of first received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleAdvOutput +//! @{ +//! Output structure for advertiser (CMD_BLE_ADV* and CMD_BLE5_ADV*) + +struct __RFC_STRUCT rfc_bleAdvOutput_s { + uint16_t nTxAdvInd; //!< Number of ADV*_IND packets completely transmitted + uint8_t nTxScanRsp; //!< Number of AUX_SCAN_RSP or SCAN_RSP packets transmitted + uint8_t nRxScanReq; //!< Number of AUX_SCAN_REQ or SCAN_REQ packets received OK and not ignored + uint8_t nRxConnectReq; //!< Number of AUX_CONNECT_REQ or CONNECT_IND (CONNECT_REQ) packets received OK and not ignored + uint8_t nTxConnectRsp; //!< Number of AUX_CONNECT_RSP packets transmitted + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxIgnored; //!< Number of packets received with CRC OK, but ignored + uint8_t nRxBufFull; //!< Number of packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + ratmr_t timeStamp; //!< Time stamp of the last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleScannerOutput +//! @{ +//! Output structure for legacy scanner (CMD_BLE_SCANNER) + +struct __RFC_STRUCT rfc_bleScannerOutput_s { + uint16_t nTxScanReq; //!< Number of transmitted SCAN_REQ packets + uint16_t nBackedOffScanReq; //!< Number of SCAN_REQ packets not sent due to backoff procedure + uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint16_t nRxScanRspOk; //!< Number of SCAN_RSP packets received with CRC OK and not ignored + uint16_t nRxScanRspIgnored; //!< Number of SCAN_RSP packets received with CRC OK, but ignored + uint16_t nRxScanRspNok; //!< Number of SCAN_RSP packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + uint8_t nRxScanRspBufFull; //!< Number of SCAN_RSP packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last successfully received ADV*_IND packet that was not ignored +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleInitiatorOutput +//! @{ +//! Output structure for legacy initiator (CMD_BLE_INITIATOR) + +struct __RFC_STRUCT rfc_bleInitiatorOutput_s { + uint8_t nTxConnectReq; //!< Number of transmitted CONNECT_IND (CONNECT_REQ) packets + uint8_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + ratmr_t timeStamp; //!< Time stamp of the received ADV*_IND packet that caused transmission of CONNECT_IND (CONNECT_REQ) +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5ScanInitOutput +//! @{ +//! Output structure for BLE scanner and initiator (CMD_BLE5_SCANNER and CMD_BLE5_INITIATOR) + +struct __RFC_STRUCT rfc_ble5ScanInitOutput_s { + uint16_t nTxReq; //!< Number of transmitted AUX_SCAN_REQ, SCAN_REQ, AUX_CONNECT_REQ, or CONNECT_IND packets + uint16_t nBackedOffReq; //!< Number of AUX_SCAN_REQ, SCAN_REQ, or AUX_CONNECT_REQ packets not sent due to backoff procedure + uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint16_t nRxRspOk; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC OK and not ignored + uint16_t nRxRspIgnored; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC OK, but ignored + uint16_t nRxRspNok; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + uint8_t nRxRspBufFull; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last successfully received *ADV*_IND packet that was not ignored +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleGenericRxOutput +//! @{ +//! Output structure for generic Rx (CMD_BLE_GENERIC_RX and CMD_BLE5_GENERIC_RX) + +struct __RFC_STRUCT rfc_bleGenericRxOutput_s { + uint16_t nRxOk; //!< Number of packets received with CRC OK + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleTxTestOutput +//! @{ +//! Output structure for Tx test (CMD_BLE_TX_TEST and CMD_BLE5_TX_TEST) + +struct __RFC_STRUCT rfc_bleTxTestOutput_s { + uint16_t nTx; //!< Number of packets transmitted +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5ExtAdvEntry +//! @{ +//! Common Extended Packet Entry Format + +struct __RFC_STRUCT rfc_ble5ExtAdvEntry_s { + struct { + uint8_t length:6; //!< Extended header length + uint8_t advMode:2; //!< \brief Advertiser mode as defined in BLE:
+ //!< 0: Non-connectable, non-scannable
+ //!< 1: Connectable, non-scannable
+ //!< 2: Non-connectable, scannable
+ //!< 3: Reserved + } extHdrInfo; + uint8_t extHdrFlags; //!< Extended header flags as defined in BLE + struct { + uint8_t bSkipAdvA:1; //!< \brief 0: AdvA is present in extended payload if configured in + //!< extHdrFlags
+ //!< 1: AdvA is inserted automatically from command structure if configured in + //!< extHdrFlags and is omitted from extended header + uint8_t bSkipTargetA:1; //!< \brief 0: TargetA is present in extended payload if configured in + //!< extHdrFlags. For response messages, the value is replaced + //!< by the received address when sending
+ //!< 1: TargetA is inserted automatically from command structure or received + //!< address if configured in extHdrFlags and is omitted from + //!< extended header. Not supported with CMD_BLE5_ADV_EXT. + uint8_t deviceAddrType:1; //!< \brief If bSkipAdvA = 0: The type of the device address in extended + //!< header buffer -- public (0) or random (1) + uint8_t targetAddrType:1; //!< \brief If bSkipAdvA = 0: The type of the target address in extended + //!< header buffer -- public (0) or random (1) + } extHdrConfig; + uint8_t advDataLen; //!< Size of payload buffer + uint8_t* pExtHeader; //!< \brief Pointer to buffer containing extended header. If no fields except extended + //!< header flags, automatic advertiser address, or automatic target address are + //!< present, pointer may be NULL. + uint8_t* pAdvData; //!< \brief Pointer to buffer containing advData. If advDataLen = 0, + //!< pointer may be NULL. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleWhiteListEntry +//! @{ +//! White list entry structure + +struct __RFC_STRUCT rfc_bleWhiteListEntry_s { + uint8_t size; //!< Number of while list entries. Used in the first entry of the list only + struct { + uint8_t bEnable:1; //!< 1 if the entry is in use, 0 if the entry is not in use + uint8_t addrType:1; //!< The type address in the entry -- public (0) or random (1) + uint8_t bWlIgn:1; //!< \brief 1 if the entry is to be ignored by a scanner if the AdvDataInfo + //!< field is not present, 0 otherwise. Used to mask out entries that + //!< have already been scanned and reported. + uint8_t :1; + uint8_t bPrivIgn:1; //!< \brief 1 if the entry is to be ignored as part of a privacy algorithm, + //!< 0 otherwise + } conf; + uint16_t address; //!< Least significant 16 bits of the address contained in the entry + uint32_t addressHi; //!< Most significant 32 bits of the address contained in the entry +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5AdiEntry +//! @{ +//! AdvDataInfo list entry structure + +struct __RFC_STRUCT rfc_ble5AdiEntry_s { + struct { + uint16_t advDataId:12; //!< \brief If bValid = 1: Last Advertising Data ID (DID) for the + //!< Advertising Set ID (SID) corresponding to the entry number in the array + uint16_t mode:2; //!< \brief 0: Entry is invalid (always receive packet with the given SID)
+ //!< 1: Entry is valid (ignore packets with the given SID where DID equals + //!< advDataId)
+ //!< 2: Entry is blocked (always ignore packet with the given SID)
+ //!< 3: Reserved + } advDataInfo; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleRxStatus +//! @{ +//! Receive status byte that may be appended to message in receive buffer for legacy commands + +struct __RFC_STRUCT rfc_bleRxStatus_s { + struct { + uint8_t channel:6; //!< \brief The channel on which the packet was received, provided channel is in the range + //!< 0--39; otherwise 0x3F + uint8_t bIgnore:1; //!< 1 if the packet is marked as ignored, 0 otherwise + uint8_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5RxStatus +//! @{ +//! Receive status field that may be appended to message in receive buffer for Bluetooth 5 commands + +struct __RFC_STRUCT rfc_ble5RxStatus_s { + struct { + uint16_t channel:6; //!< \brief The channel on which the packet was received, provided channel is in the range + //!< 0--39; otherwise 0x3F + uint16_t bIgnore:1; //!< 1 if the packet is marked as ignored, 0 otherwise + uint16_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise + uint16_t phyMode:2; //!< \brief The PHY on which the packet was received
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded, S = 8 (125 kbps)
+ //!< 3: Coded, S = 2 (500 kbps) + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h new file mode 100644 index 0000000..abc14d3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h @@ -0,0 +1,76 @@ +/****************************************************************************** +* Filename: rf_ble_mailbox.h +* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) +* Revision: 18171 +* +* Description: Definitions for BLE interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _BLE_MAILBOX_H +#define _BLE_MAILBOX_H + +/// \name Radio operation status +///@{ +/// \name Operation finished normally +///@{ +#define BLE_DONE_OK 0x1400 ///< Operation ended normally +#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window +#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx +#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other) +#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_IND or AUX_CONNECT_RSP received or transmitted +#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded +#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger +#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command +#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command +#define BLE_DONE_AUX 0x1409 ///< Operation ended after following aux pointer pointing far ahead +#define BLE_DONE_CONNECT_CHSEL0 0x140A ///< CONNECT_IND received or transmitted; peer does not support channel selection algorithm #2 +#define BLE_DONE_SCAN_RSP 0x140B ///< SCAN_RSP or AUX_SCAN_RSP transmitted +///@} +/// \name Operation finished with error +///@{ +#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter +#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator) +#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attempted when not in BLE mode +#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attempted without frequency synth configured +#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time +#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation +#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation +#define BLE_ERROR_AUX 0x1807 ///< Calculated AUX pointer was too far into the future or in the past +///@} +///@} + + +/// Special trigger for BLE slave command +#define BLE_TRIG_REL_SYNC 15 + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h new file mode 100644 index 0000000..94aec4a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h @@ -0,0 +1,1089 @@ +/****************************************************************************** +* Filename: rf_common_cmd.h +* Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018) +* Revision: 18756 +* +* Description: CC13x2/CC26x2 API for common/generic commands +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __COMMON_CMD_H +#define __COMMON_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup common_cmd +//! @{ + +#include +#include "rf_mailbox.h" + +typedef struct __RFC_STRUCT rfc_command_s rfc_command_t; +typedef struct __RFC_STRUCT rfc_radioOp_s rfc_radioOp_t; +typedef struct __RFC_STRUCT rfc_CMD_NOP_s rfc_CMD_NOP_t; +typedef struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s rfc_CMD_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_s rfc_CMD_FS_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_OFF_s rfc_CMD_FS_OFF_t; +typedef struct __RFC_STRUCT rfc_CMD_RX_TEST_s rfc_CMD_RX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_TX_TEST_s rfc_CMD_TX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s rfc_CMD_SYNC_STOP_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s rfc_CMD_SYNC_START_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_RESYNC_RAT_s rfc_CMD_RESYNC_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_COUNT_s rfc_CMD_COUNT_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s rfc_CMD_FS_POWERUP_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s rfc_CMD_FS_POWERDOWN_t; +typedef struct __RFC_STRUCT rfc_CMD_SCH_IMM_s rfc_CMD_SCH_IMM_t; +typedef struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s rfc_CMD_COUNT_BRANCH_t; +typedef struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s rfc_CMD_PATTERN_CHECK_t; +typedef struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_PA_s rfc_CMD_RADIO_SETUP_PA_t; +typedef struct __RFC_STRUCT rfc_CMD_ABORT_s rfc_CMD_ABORT_t; +typedef struct __RFC_STRUCT rfc_CMD_STOP_s rfc_CMD_STOP_t; +typedef struct __RFC_STRUCT rfc_CMD_GET_RSSI_s rfc_CMD_GET_RSSI_t; +typedef struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s rfc_CMD_UPDATE_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_TRIGGER_s rfc_CMD_TRIGGER_t; +typedef struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s rfc_CMD_GET_FW_INFO_t; +typedef struct __RFC_STRUCT rfc_CMD_START_RAT_s rfc_CMD_START_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_PING_s rfc_CMD_PING_t; +typedef struct __RFC_STRUCT rfc_CMD_READ_RFREG_s rfc_CMD_READ_RFREG_t; +typedef struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s rfc_CMD_ADD_DATA_ENTRY_t; +typedef struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s rfc_CMD_REMOVE_DATA_ENTRY_t; +typedef struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s rfc_CMD_FLUSH_QUEUE_t; +typedef struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s rfc_CMD_CLEAR_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s rfc_CMD_REMOVE_PENDING_ENTRIES_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s rfc_CMD_SET_RAT_CMP_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s rfc_CMD_SET_RAT_CPT_t; +typedef struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s rfc_CMD_DISABLE_RAT_CH_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s rfc_CMD_SET_RAT_OUTPUT_t; +typedef struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s rfc_CMD_ARM_RAT_CH_t; +typedef struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s rfc_CMD_DISARM_RAT_CH_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s rfc_CMD_SET_TX_POWER_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_TX20_POWER_s rfc_CMD_SET_TX20_POWER_t; +typedef struct __RFC_STRUCT rfc_CMD_CHANGE_PA_s rfc_CMD_CHANGE_PA_t; +typedef struct __RFC_STRUCT rfc_CMD_UPDATE_HPOSC_FREQ_s rfc_CMD_UPDATE_HPOSC_FREQ_t; +typedef struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s rfc_CMD_UPDATE_FS_t; +typedef struct __RFC_STRUCT rfc_CMD_MODIFY_FS_s rfc_CMD_MODIFY_FS_t; +typedef struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s rfc_CMD_BUS_REQUEST_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s rfc_CMD_SET_CMD_START_IRQ_t; + +//! \addtogroup command +//! @{ +struct __RFC_STRUCT rfc_command_s { + uint16_t commandNo; //!< The command ID number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup radioOp +//! @{ +//! Common definition for radio operation commands + +struct __RFC_STRUCT rfc_radioOp_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_NOP +//! @{ +#define CMD_NOP 0x0801 +//! No Operation Command +struct __RFC_STRUCT rfc_CMD_NOP_s { + uint16_t commandNo; //!< The command ID number 0x0801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_RADIO_SETUP +//! @{ +#define CMD_RADIO_SETUP 0x0802 +//! Radio Setup Command for Pre-Defined Schemes +struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x0802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t mode; //!< \brief The main mode to use
+ //!< 0x00: BLE
+ //!< 0x01: IEEE 802.15.4
+ //!< 0x02: 2 Mbps GFSK
+ //!< 0x05: 5 Mbps coded 8-FSK
+ //!< 0xFF: Keep existing mode; update overrides only
+ //!< Others: Reserved + uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0, 2, 4, + //!< 5, 6, 10, 12, 15, and 30. + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS +//! @{ +#define CMD_FS 0x0803 +//! Frequency Synthesizer Programming Command +struct __RFC_STRUCT rfc_CMD_FS_s { + uint16_t commandNo; //!< The command ID number 0x0803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to + struct { + uint8_t bTxMode:1; //!< \brief 0: Start synth in RX mode
+ //!< 1: Start synth in TX mode + uint8_t refFreq:6; //!< \brief 0: Use default reference frequency
+ //!< Others: Use reference frequency 48 MHz/refFreq + } synthConf; + uint8_t __dummy0; //!< Reserved, always write 0 + uint8_t __dummy1; //!< Reserved + uint8_t __dummy2; //!< Reserved + uint16_t __dummy3; //!< Reserved +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS_OFF +//! @{ +#define CMD_FS_OFF 0x0804 +//! Command for Turning off Frequency Synthesizer +struct __RFC_STRUCT rfc_CMD_FS_OFF_s { + uint16_t commandNo; //!< The command ID number 0x0804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_RX_TEST +//! @{ +#define CMD_RX_TEST 0x0807 +//! Receiver Test Command +struct __RFC_STRUCT rfc_CMD_RX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x0807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bEnaFifo:1; //!< \brief 0: Do not enable FIFO in modem, so that received data is not available
+ //!< 1: Enable FIFO in modem -- the data must be read out by the application + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bNoSync:1; //!< \brief 0: Run sync search as normal for the configured mode
+ //!< 1: Write correlation thresholds to the maximum value to avoid getting sync + } config; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for receiver + ratmr_t endTime; //!< Time to end the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_TX_TEST +//! @{ +#define CMD_TX_TEST 0x0808 +//! Transmitter Test Command +struct __RFC_STRUCT rfc_CMD_TX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x0808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bUseCw:1; //!< \brief 0: Send modulated signal
+ //!< 1: Send continuous wave + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t whitenMode:2; //!< \brief 0: No whitening
+ //!< 1: Default whitening
+ //!< 2: PRBS-15
+ //!< 3: PRBS-32 + } config; + uint8_t __dummy0; + uint16_t txWord; //!< Value to send to the modem before whitening + uint8_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for transmitter + ratmr_t endTime; //!< Time to end the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SYNC_STOP_RAT +//! @{ +#define CMD_SYNC_STOP_RAT 0x0809 +//! Synchronize and Stop Radio Timer Command +struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s { + uint16_t commandNo; //!< The command ID number 0x0809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The returned RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SYNC_START_RAT +//! @{ +#define CMD_SYNC_START_RAT 0x080A +//! Synchrously Start Radio Timer Command +struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s { + uint16_t commandNo; //!< The command ID number 0x080A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero. This parameter is returned by CMD_SYNC_STOP_RAT +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_RESYNC_RAT +//! @{ +#define CMD_RESYNC_RAT 0x0816 +//! Re-calculate rat0 value while RAT is running +struct __RFC_STRUCT rfc_CMD_RESYNC_RAT_s { + uint16_t commandNo; //!< The command ID number 0x0816 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_COUNT +//! @{ +#define CMD_COUNT 0x080B +//! Counter Command +struct __RFC_STRUCT rfc_CMD_COUNT_s { + uint16_t commandNo; //!< The command ID number 0x080B + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS_POWERUP +//! @{ +#define CMD_FS_POWERUP 0x080C +//! Power up Frequency Syntheszier Command +struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s { + uint16_t commandNo; //!< The command ID number 0x080C + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS_POWERDOWN +//! @{ +#define CMD_FS_POWERDOWN 0x080D +//! Power down Frequency Syntheszier Command +struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s { + uint16_t commandNo; //!< The command ID number 0x080D + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SCH_IMM +//! @{ +#define CMD_SCH_IMM 0x0810 +//! Run Immidiate Command as Radio Operation Command +struct __RFC_STRUCT rfc_CMD_SCH_IMM_s { + uint16_t commandNo; //!< The command ID number 0x0810 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t cmdrVal; //!< Value as would be written to CMDR + uint32_t cmdstaVal; //!< Value as would be returned in CMDSTA +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_COUNT_BRANCH +//! @{ +#define CMD_COUNT_BRANCH 0x0812 +//! Counter Command with Branch of Command Chain +struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s { + uint16_t commandNo; //!< The command ID number 0x0812 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero + rfc_radioOp_t *pNextOpIfOk; //!< Pointer to next operation if counter did not expire +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PATTERN_CHECK +//! @{ +#define CMD_PATTERN_CHECK 0x0813 +//! Command for Checking a Value in Memory aginst a Pattern +struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s { + uint16_t commandNo; //!< The command ID number 0x0813 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t operation:2; //!< \brief Operation to perform
+ //!< 0: True if value == compareVal
+ //!< 1: True if value < compareVal
+ //!< 2: True if value > compareVal
+ //!< 3: Reserved + uint16_t bByteRev:1; //!< \brief If 1, interchange the four bytes of the value, so that they are read + //!< most-significant-byte-first. + uint16_t bBitRev:1; //!< If 1, perform bit reversal of the value + uint16_t signExtend:5; //!< \brief 0: Treat value and compareVal as unsigned
+ //!< 1--31: Treat value and compareVal as signed, where the value + //!< gives the number of the most significant bit in the signed number. + uint16_t bRxVal:1; //!< \brief 0: Use pValue as a pointer
+ //!< 1: Use pValue as a signed offset to the start of the last + //!< committed RX entry element + } patternOpt; //!< Options for comparison + rfc_radioOp_t *pNextOpIfOk; //!< Pointer to next operation if comparison result was true + uint8_t* pValue; //!< Pointer to read from, or offset from last RX entry if patternOpt.bRxVal == 1 + uint32_t mask; //!< Bit mask to apply before comparison + uint32_t compareVal; //!< Value to compare to +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_RADIO_SETUP_PA +//! @{ +//! Radio Setup Command for Pre-Defined Schemes with PA Switching Fields +struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_PA_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t mode; //!< \brief The main mode to use
+ //!< 0x00: BLE
+ //!< 0x01: IEEE 802.15.4
+ //!< 0x02: 2 Mbps GFSK
+ //!< 0x05: 5 Mbps coded 8-FSK
+ //!< 0xFF: Keep existing mode; update overrides only
+ //!< Others: Reserved + uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0, 2, 4, + //!< 5, 6, 10, 12, 15, and 30. + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< standard PA. Used by RF driver only, not radio CPU. + uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< 20-dBm PA. Used by RF driver only, not radio CPU. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_ABORT +//! @{ +#define CMD_ABORT 0x0401 +//! Abort Running Radio Operation Command +struct __RFC_STRUCT rfc_CMD_ABORT_s { + uint16_t commandNo; //!< The command ID number 0x0401 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_STOP +//! @{ +#define CMD_STOP 0x0402 +//! Stop Running Radio Operation Command Gracefully +struct __RFC_STRUCT rfc_CMD_STOP_s { + uint16_t commandNo; //!< The command ID number 0x0402 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_GET_RSSI +//! @{ +#define CMD_GET_RSSI 0x0403 +//! Read RSSI Command +struct __RFC_STRUCT rfc_CMD_GET_RSSI_s { + uint16_t commandNo; //!< The command ID number 0x0403 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_UPDATE_RADIO_SETUP +//! @{ +#define CMD_UPDATE_RADIO_SETUP 0x0001 +//! Update Radio Settings Command +struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x0001 + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_TRIGGER +//! @{ +#define CMD_TRIGGER 0x0404 +//! Generate Command Trigger +struct __RFC_STRUCT rfc_CMD_TRIGGER_s { + uint16_t commandNo; //!< The command ID number 0x0404 + uint8_t triggerNo; //!< Command trigger number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_GET_FW_INFO +//! @{ +#define CMD_GET_FW_INFO 0x0002 +//! Request Information on the RF Core ROM Firmware +struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s { + uint16_t commandNo; //!< The command ID number 0x0002 + uint16_t versionNo; //!< Firmware version number + uint16_t startOffset; //!< The start of free RAM + uint16_t freeRamSz; //!< The size of free RAM + uint16_t availRatCh; //!< Bitmap of available RAT channels +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_START_RAT +//! @{ +#define CMD_START_RAT 0x0405 +//! Asynchronously Start Radio Timer Command +struct __RFC_STRUCT rfc_CMD_START_RAT_s { + uint16_t commandNo; //!< The command ID number 0x0405 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PING +//! @{ +#define CMD_PING 0x0406 +//! Respond with Command ACK Only +struct __RFC_STRUCT rfc_CMD_PING_s { + uint16_t commandNo; //!< The command ID number 0x0406 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_READ_RFREG +//! @{ +#define CMD_READ_RFREG 0x0601 +//! Read RF Core Hardware Register +struct __RFC_STRUCT rfc_CMD_READ_RFREG_s { + uint16_t commandNo; //!< The command ID number 0x0601 + uint16_t address; //!< The offset from the start of the RF core HW register bank (0x40040000) + uint32_t value; //!< Returned value of the register +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_ADD_DATA_ENTRY +//! @{ +#define CMD_ADD_DATA_ENTRY 0x0005 +//! Add Data Entry to Queue +struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s { + uint16_t commandNo; //!< The command ID number 0x0005 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to which the entry will be added + uint8_t* pEntry; //!< Pointer to the entry +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_REMOVE_DATA_ENTRY +//! @{ +#define CMD_REMOVE_DATA_ENTRY 0x0006 +//! Remove First Data Entry from Queue +struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s { + uint16_t commandNo; //!< The command ID number 0x0006 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure from which the entry will be removed + uint8_t* pEntry; //!< Pointer to the entry that was removed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FLUSH_QUEUE +//! @{ +#define CMD_FLUSH_QUEUE 0x0007 +//! Flush Data Queue +struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s { + uint16_t commandNo; //!< The command ID number 0x0007 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_CLEAR_RX +//! @{ +#define CMD_CLEAR_RX 0x0008 +//! Clear all RX Queue Entries +struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s { + uint16_t commandNo; //!< The command ID number 0x0008 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be cleared +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_REMOVE_PENDING_ENTRIES +//! @{ +#define CMD_REMOVE_PENDING_ENTRIES 0x0009 +//! Remove Pending Entries from Queue +struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s { + uint16_t commandNo; //!< The command ID number 0x0009 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_RAT_CMP +//! @{ +#define CMD_SET_RAT_CMP 0x000A +//! Set Radio Timer Channel in Compare Mode +struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s { + uint16_t commandNo; //!< The command ID number 0x000A + uint8_t ratCh; //!< The radio timer channel number + uint8_t __dummy0; + ratmr_t compareTime; //!< The time at which the compare occurs +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_RAT_CPT +//! @{ +#define CMD_SET_RAT_CPT 0x0603 +//! Set Radio Timer Channel in Capture Mode +struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s { + uint16_t commandNo; //!< The command ID number 0x0603 + struct { + uint16_t :3; + uint16_t inputSrc:5; //!< Input source indicator + uint16_t ratCh:4; //!< The radio timer channel number + uint16_t bRepeated:1; //!< \brief 0: Single capture mode
+ //!< 1: Repeated capture mode + uint16_t inputMode:2; //!< \brief Input mode:
+ //!< 0: Capture on rising edge
+ //!< 1: Capture on falling edge
+ //!< 2: Capture on both edges
+ //!< 3: Reserved + } config; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_DISABLE_RAT_CH +//! @{ +#define CMD_DISABLE_RAT_CH 0x0408 +//! Disable Radio Timer Channel +struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s { + uint16_t commandNo; //!< The command ID number 0x0408 + uint8_t ratCh; //!< The radio timer channel number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_RAT_OUTPUT +//! @{ +#define CMD_SET_RAT_OUTPUT 0x0604 +//! Set Radio Timer Output to a Specified Mode +struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s { + uint16_t commandNo; //!< The command ID number 0x0604 + struct { + uint16_t :2; + uint16_t outputSel:3; //!< Output event indicator + uint16_t outputMode:3; //!< \brief 0: Set output line low as default; and pulse on event. Duration of pulse is one RF Core clock period (ca. 41.67 ns).
+ //!< 1: Set output line high on event
+ //!< 2: Set output line low on event
+ //!< 3: Toggle (invert) output line state on event
+ //!< 4: Immediately set output line to low (does not change upon event)
+ //!< 5: Immediately set output line to high (does not change upon event)
+ //!< Others: Reserved + uint16_t ratCh:4; //!< The radio timer channel number + } config; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_ARM_RAT_CH +//! @{ +#define CMD_ARM_RAT_CH 0x0409 +//! Arm Radio Timer Channel +struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s { + uint16_t commandNo; //!< The command ID number 0x0409 + uint8_t ratCh; //!< The radio timer channel number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_DISARM_RAT_CH +//! @{ +#define CMD_DISARM_RAT_CH 0x040A +//! Disarm Radio Timer Channel +struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s { + uint16_t commandNo; //!< The command ID number 0x040A + uint8_t ratCh; //!< The radio timer channel number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_TX_POWER +//! @{ +#define CMD_SET_TX_POWER 0x0010 +//! Set Transmit Power +struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s { + uint16_t commandNo; //!< The command ID number 0x0010 + uint16_t txPower; //!< New TX power setting +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_TX20_POWER +//! @{ +#define CMD_SET_TX20_POWER 0x0014 +//! Set Transmit Power for 20-dBm PA +struct __RFC_STRUCT rfc_CMD_SET_TX20_POWER_s { + uint16_t commandNo; //!< The command ID number 0x0014 + uint16_t __dummy0; + uint32_t tx20Power; //!< New TX power setting +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_CHANGE_PA +//! @{ +#define CMD_CHANGE_PA 0x0015 +//! Set TX power with possibility to switch between PAs +struct __RFC_STRUCT rfc_CMD_CHANGE_PA_s { + uint16_t commandNo; //!< The command ID number 0x0015 + uint16_t __dummy0; + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override as part of the + //!< change, including new TX power +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_UPDATE_HPOSC_FREQ +//! @{ +#define CMD_UPDATE_HPOSC_FREQ 0x0608 +//! Set New Frequency Offset for HPOSC +struct __RFC_STRUCT rfc_CMD_UPDATE_HPOSC_FREQ_s { + uint16_t commandNo; //!< The command ID number 0x0608 + int16_t freqOffset; //!< Relative frequency offset, signed, scaled by 2-22 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_UPDATE_FS +//! @{ +#define CMD_UPDATE_FS 0x0011 +//! Set New Synthesizer Frequency without Recalibration (Deprecated; use CMD_MODIFY_FS) +struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s { + uint16_t commandNo; //!< The command ID number 0x0011 + uint16_t __dummy0; + uint32_t __dummy1; + uint32_t __dummy2; + uint16_t __dummy3; + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_MODIFY_FS +//! @{ +#define CMD_MODIFY_FS 0x0013 +//! Set New Synthesizer Frequency without Recalibration +struct __RFC_STRUCT rfc_CMD_MODIFY_FS_s { + uint16_t commandNo; //!< The command ID number 0x0013 + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BUS_REQUEST +//! @{ +#define CMD_BUS_REQUEST 0x040E +//! Request System Bus to be Availbale +struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s { + uint16_t commandNo; //!< The command ID number 0x040E + uint8_t bSysBusNeeded; //!< \brief 0: System bus may sleep
+ //!< 1: System bus access needed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_CMD_START_IRQ +//! @{ +#define CMD_SET_CMD_START_IRQ 0x0411 +//! Enable or disable generation of IRQ when a radio operation command starts +struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s { + uint16_t commandNo; //!< The command ID number 0x0411 + uint8_t bEna; //!< 1 to enable interrupt generation; 0 to disable it +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h new file mode 100644 index 0000000..ad798d5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h @@ -0,0 +1,219 @@ +/****************************************************************************** +* Filename: rf_data_entry.h +* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) +* Revision: 18170 +* +* Description: Definition of API for data exchange +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __DATA_ENTRY_H +#define __DATA_ENTRY_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup data_entry +//! @{ + +#include +#include "rf_mailbox.h" + +typedef struct __RFC_STRUCT rfc_dataEntry_s rfc_dataEntry_t; +typedef struct __RFC_STRUCT rfc_dataEntryGeneral_s rfc_dataEntryGeneral_t; +typedef struct __RFC_STRUCT rfc_dataEntryMulti_s rfc_dataEntryMulti_t; +typedef struct __RFC_STRUCT rfc_dataEntryPointer_s rfc_dataEntryPointer_t; +typedef struct __RFC_STRUCT rfc_dataEntryPartial_s rfc_dataEntryPartial_t; + +//! \addtogroup dataEntry +//! @{ +struct __RFC_STRUCT rfc_dataEntry_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryGeneral +//! @{ +//! General data entry structure (type = 0) + +struct __RFC_STRUCT rfc_dataEntryGeneral_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t data; //!< First byte of the data array to be received or transmitted +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryMulti +//! @{ +//! Multi-element data entry structure (type = 1) + +struct __RFC_STRUCT rfc_dataEntryMulti_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint16_t numElements; //!< Number of entry elements committed in the entry + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryPointer +//! @{ +//! Pointer data entry structure (type = 2) + +struct __RFC_STRUCT rfc_dataEntryPointer_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryPartial +//! @{ +//! Partial read data entry structure (type = 3) + +struct __RFC_STRUCT rfc_dataEntryPartial_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + struct { + uint16_t numElements:13; //!< Number of entry elements committed in the entry + uint16_t bEntryOpen:1; //!< 1 if the entry contains an element that is still open for appending data + uint16_t bFirstCont:1; //!< 1 if the first element is a continuation of the last packet from the previous entry + uint16_t bLastCont:1; //!< 1 if the packet in the last element continues in the next entry + } pktStatus; + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h new file mode 100644 index 0000000..f1f4c6c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h @@ -0,0 +1,210 @@ +/****************************************************************************** +* Filename: rf_hs_cmd.h +* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) +* Revision: 18170 +* +* Description: CC13x2/CC26x2 API for high-speed mode commands +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HS_CMD_H +#define __HS_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup hs_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_CMD_HS_TX_s rfc_CMD_HS_TX_t; +typedef struct __RFC_STRUCT rfc_CMD_HS_RX_s rfc_CMD_HS_RX_t; +typedef struct __RFC_STRUCT rfc_hsRxOutput_s rfc_hsRxOutput_t; +typedef struct __RFC_STRUCT rfc_hsRxStatus_s rfc_hsRxStatus_t; + +//! \addtogroup CMD_HS_TX +//! @{ +#define CMD_HS_TX 0x3841 +//! High-Speed Transmit Command +struct __RFC_STRUCT rfc_CMD_HS_TX_s { + uint16_t commandNo; //!< The command ID number 0x3841 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Transmit length as first half-word + uint8_t bCheckQAtEnd:1; //!< \brief 0: Always end with HS_DONE_OK when packet has been transmitted
+ //!< 1: Check if Tx queue is empty when packet has been transmitted + } pktConf; + uint8_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to Tx queue +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_HS_RX +//! @{ +#define CMD_HS_RX 0x3842 +//! High-Speed Receive Command +struct __RFC_STRUCT rfc_CMD_HS_RX_s { + uint16_t commandNo; //!< The command ID number 0x3842 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bUseCrc:1; //!< \brief 0: Do not receive or check CRC
+ //!< 1: Receive and check CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t addressMode:2; //!< \brief 0: No address check
+ //!< 1: Accept address0 and address1
+ //!< 2: Accept address0, address1, and 0x0000
+ //!< 3: Accept address0, address1, 0x0000, and 0xFFFF + } pktConf; + struct { + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bIncludeLen:1; //!< If 1, include the received length field in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise 3scard it + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConf; + uint16_t maxPktLen; //!< Packet length for fixed length; maximum packet length for variable length + uint16_t address0; //!< Address + uint16_t address1; //!< Address (set equal to address0 to accept only one address) + uint8_t __dummy0; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + rfc_hsRxOutput_t *pOutput; //!< Pointer to output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup hsRxOutput +//! @{ +//! Output structure for CMD_HS_RX + +struct __RFC_STRUCT rfc_hsRxOutput_s { + uint16_t nRxOk; //!< Number of packets that have been received with CRC OK + uint16_t nRxNok; //!< Number of packets that have been received with CRC error + uint16_t nRxAborted; //!< Number of packets not received due to illegal length or address mismatch + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + ratmr_t timeStamp; //!< Time stamp of last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup hsRxStatus +//! @{ +//! Receive status word that may be appended to message in receive buffer + +struct __RFC_STRUCT rfc_hsRxStatus_s { + struct { + uint16_t rssi:8; //!< RSSI of the received packet in dBm (signed) + uint16_t bCrcErr:1; //!< \brief 0: Packet received OK
+ //!< 1: Packet received with CRC error + uint16_t addressInd:2; //!< \brief 0: Received address0 (or no address check)
+ //!< 1: Received address1
+ //!< 2: Received address 0x0000
+ //!< 3: Received address 0xFFFF + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h new file mode 100644 index 0000000..9031f8e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h @@ -0,0 +1,65 @@ +/****************************************************************************** +* Filename: rf_hs_mailbox.h +* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) +* Revision: 18171 +* +* Description: Definitions for high-speed mode radio interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _HS_MAILBOX_H +#define _HS_MAILBOX_H + +/// \name Radio operation status +///@{ +/// \name Operation finished normally +///@{ +#define HS_DONE_OK 0x3440 ///< Operation ended normally +#define HS_DONE_RXTIMEOUT 0x3441 ///< Operation stopped after end trigger while waiting for sync +#define HS_DONE_RXERR 0x3442 ///< Operation ended after CRC error +#define HS_DONE_TXBUF 0x3443 ///< Tx queue was empty at start of operation +#define HS_DONE_ENDED 0x3444 ///< Operation stopped after end trigger during reception +#define HS_DONE_STOPPED 0x3445 ///< Operation stopped after stop command +#define HS_DONE_ABORT 0x3446 ///< Operation aborted by abort command +///@} +/// \name Operation finished with error +///@{ +#define HS_ERROR_PAR 0x3840 ///< Illegal parameter +#define HS_ERROR_RXBUF 0x3841 ///< No available Rx buffer at the start of a packet +#define HS_ERROR_NO_SETUP 0x3842 ///< Radio was not set up in a compatible mode +#define HS_ERROR_NO_FS 0x3843 ///< Synth was not programmed when running Rx or Tx +#define HS_ERROR_RXOVF 0x3844 ///< Rx overflow observed during operation +#define HS_ERROR_TXUNF 0x3845 ///< Tx underflow observed during operation +///@} +///@} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h new file mode 100644 index 0000000..1e92f0a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h @@ -0,0 +1,628 @@ +/****************************************************************************** +* Filename: rf_ieee_cmd.h +* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) +* Revision: 18170 +* +* Description: CC13x2/CC26x2 API for IEEE 802.15.4 commands +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __IEEE_CMD_H +#define __IEEE_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup ieee_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_s rfc_CMD_IEEE_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s rfc_CMD_IEEE_ED_SCAN_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_TX_s rfc_CMD_IEEE_TX_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s rfc_CMD_IEEE_CSMA_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s rfc_CMD_IEEE_RX_ACK_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s rfc_CMD_IEEE_ABORT_BG_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s rfc_CMD_IEEE_MOD_CCA_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s rfc_CMD_IEEE_MOD_FILT_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s rfc_CMD_IEEE_MOD_SRC_MATCH_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s rfc_CMD_IEEE_ABORT_FG_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s rfc_CMD_IEEE_STOP_FG_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s rfc_CMD_IEEE_CCA_REQ_t; +typedef struct __RFC_STRUCT rfc_ieeeRxOutput_s rfc_ieeeRxOutput_t; +typedef struct __RFC_STRUCT rfc_shortAddrEntry_s rfc_shortAddrEntry_t; +typedef struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s rfc_ieeeRxCorrCrc_t; + +//! \addtogroup CMD_IEEE_RX +//! @{ +#define CMD_IEEE_RX 0x2801 +//! IEEE 802.15.4 Receive Command +struct __RFC_STRUCT rfc_CMD_IEEE_RX_s { + uint16_t commandNo; //!< The command ID number 0x2801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to tune to in the start of the operation
+ //!< 0: Use existing channel
+ //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
+ //!< 60--207: Frequency is (2300 + channel) MHz
+ //!< Others: Reserved + struct { + uint8_t bAutoFlushCrc:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushIgn:1; //!< If 1, automatically remove packets that can be ignored according to frame filtering from Rx queue + uint8_t bIncludePhyHdr:1; //!< If 1, include the received PHY header field in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendCorrCrc:1; //!< If 1, append a correlation value and CRC result byte to the packet in the Rx queue + uint8_t bAppendSrcInd:1; //!< If 1, append an index from the source matching algorithm + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; + dataQueue_t* pRxQ; //!< Pointer to receive queue + rfc_ieeeRxOutput_t *pOutput; //!< Pointer to output structure (NULL: Do not store results) + struct { + uint16_t frameFiltEn:1; //!< \brief 0: Disable frame filtering
+ //!< 1: Enable frame filtering + uint16_t frameFiltStop:1; //!< \brief 0: Receive all packets to the end
+ //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. + uint16_t autoAckEn:1; //!< \brief 0: Disable auto ACK
+ //!< 1: Enable auto ACK. + uint16_t slottedAckEn:1; //!< \brief 0: Non-slotted ACK
+ //!< 1: Slotted ACK. + uint16_t autoPendEn:1; //!< \brief 0: Auto-pend disabled
+ //!< 1: Auto-pend enabled + uint16_t defaultPend:1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend + uint16_t bPendDataReqOnly:1; //!< \brief 0: Use auto-pend for any packet
+ //!< 1: Use auto-pend for data request packets only + uint16_t bPanCoord:1; //!< \brief 0: Device is not PAN coordinator
+ //!< 1: Device is PAN coordinator + uint16_t maxFrameVersion:2; //!< Reject frames where the frame version field in the FCF is greater than this value + uint16_t fcfReservedMask:3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero + uint16_t modifyFtFilter:2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
+ //!< 0: No modification
+ //!< 1: Invert MSB
+ //!< 2: Set MSB to 0
+ //!< 3: Set MSB to 1 + uint16_t bStrictLenFilter:1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
+ //!< 1: Accept only acknowledgement frames of length 5 + } frameFiltOpt; //!< Frame filtering options + struct { + uint8_t bAcceptFt0Beacon:1; //!< \brief Treatment of frames with frame type 000 (beacon):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt1Data:1; //!< \brief Treatment of frames with frame type 001 (data):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt2Ack:1; //!< \brief Treatment of frames with frame type 010 (ACK):
+ //!< 0: Reject, unless running ACK receive command
+ //!< 1: Always accept + uint8_t bAcceptFt3MacCmd:1; //!< \brief Treatment of frames with frame type 011 (MAC command):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt4Reserved:1; //!< \brief Treatment of frames with frame type 100 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt5Reserved:1; //!< \brief Treatment of frames with frame type 101 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt6Reserved:1; //!< \brief Treatment of frames with frame type 110 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt7Reserved:1; //!< \brief Treatment of frames with frame type 111 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + } frameTypes; //!< Frame types to receive in frame filtering + struct { + uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } ccaOpt; //!< CCA options + int8_t ccaRssiThr; //!< RSSI threshold for CCA + uint8_t __dummy0; + uint8_t numExtEntries; //!< Number of extended address entries + uint8_t numShortEntries; //!< Number of short address entries + uint32_t* pExtEntryList; //!< Pointer to list of extended address entries + uint32_t* pShortEntryList; //!< Pointer to list of short address entries + uint64_t localExtAddr; //!< The extended address of the local device + uint16_t localShortAddr; //!< The short address of the local device + uint16_t localPanID; //!< The PAN ID of the local device + uint16_t __dummy1; + uint8_t __dummy2; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx + //!< operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_ED_SCAN +//! @{ +#define CMD_IEEE_ED_SCAN 0x2802 +//! IEEE 802.15.4 Energy Detect Scan Command +struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s { + uint16_t commandNo; //!< The command ID number 0x2802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to tune to in the start of the operation
+ //!< 0: Use existing channel
+ //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
+ //!< 60--207: Frequency is (2300 + channel) MHz
+ //!< Others: Reserved + struct { + uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } ccaOpt; //!< CCA options + int8_t ccaRssiThr; //!< RSSI threshold for CCA + uint8_t __dummy0; + int8_t maxRssi; //!< The maximum RSSI recorded during the ED scan + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx + //!< operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_TX +//! @{ +#define CMD_IEEE_TX 0x2C01 +//! IEEE 802.15.4 Transmit Command +struct __RFC_STRUCT rfc_CMD_IEEE_TX_s { + uint16_t commandNo; //!< The command ID number 0x2C01 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bIncludePhyHdr:1; //!< \brief 0: Find PHY header automatically
+ //!< 1: Insert PHY header from the buffer + uint8_t bIncludeCrc:1; //!< \brief 0: Append automatically calculated CRC
+ //!< 1: Insert FCS (CRC) from the buffer + uint8_t :1; + uint8_t payloadLenMsb:5; //!< \brief Most significant bits of payload length. Should only be non-zero to create long + //!< non-standard packets for test purposes + } txOpt; + uint8_t payloadLen; //!< Number of bytes in the payload + uint8_t* pPayload; //!< Pointer to payload buffer of size payloadLen + ratmr_t timeStamp; //!< Time stamp of transmitted frame +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_CSMA +//! @{ +#define CMD_IEEE_CSMA 0x2C02 +//! IEEE 802.15.4 CSMA-CA Command +struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s { + uint16_t commandNo; //!< The command ID number 0x2C02 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t randomState; //!< The state of the pseudo-random generator + uint8_t macMaxBE; //!< The IEEE 802.15.4 MAC parameter macMaxBE + uint8_t macMaxCSMABackoffs; //!< The IEEE 802.15.4 MAC parameter macMaxCSMABackoffs + struct { + uint8_t initCW:5; //!< The initialization value for the CW parameter + uint8_t bSlotted:1; //!< \brief 0: non-slotted CSMA
+ //!< 1: slotted CSMA + uint8_t rxOffMode:2; //!< \brief 0: RX stays on during CSMA backoffs
+ //!< 1: The CSMA-CA algorithm will suspend the receiver if no frame is being received
+ //!< 2: The CSMA-CA algorithm will suspend the receiver if no frame is being received, + //!< or after finishing it (including auto ACK) otherwise
+ //!< 3: The CSMA-CA algorithm will suspend the receiver immediately during back-offs + } csmaConfig; + uint8_t NB; //!< The NB parameter from the IEEE 802.15.4 CSMA-CA algorithm + uint8_t BE; //!< The BE parameter from the IEEE 802.15.4 CSMA-CA algorithm + uint8_t remainingPeriods; //!< The number of remaining periods from a paused backoff countdown + int8_t lastRssi; //!< RSSI measured at the last CCA operation + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the CSMA-CA operation + ratmr_t lastTimeStamp; //!< Time of the last CCA operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< CSMA-CA operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_RX_ACK +//! @{ +#define CMD_IEEE_RX_ACK 0x2C03 +//! IEEE 802.15.4 Receive Acknowledgement Command +struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s { + uint16_t commandNo; //!< The command ID number 0x2C03 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t seqNo; //!< Sequence number to expect + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to give up acknowledgement reception + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to give up + //!< acknowledgement reception +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_ABORT_BG +//! @{ +#define CMD_IEEE_ABORT_BG 0x2C04 +//! IEEE 802.15.4 Abort Background Level Command +struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s { + uint16_t commandNo; //!< The command ID number 0x2C04 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_MOD_CCA +//! @{ +#define CMD_IEEE_MOD_CCA 0x2001 +//! IEEE 802.15.4 Modify CCA Parameter Command +struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s { + uint16_t commandNo; //!< The command ID number 0x2001 + struct { + uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } newCcaOpt; //!< New value of ccaOpt for the running background level operation + int8_t newCcaRssiThr; //!< New value of ccaRssiThr for the running background level operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_MOD_FILT +//! @{ +#define CMD_IEEE_MOD_FILT 0x2002 +//! IEEE 802.15.4 Modify Frame Filtering Parameter Command +struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s { + uint16_t commandNo; //!< The command ID number 0x2002 + struct { + uint16_t frameFiltEn:1; //!< \brief 0: Disable frame filtering
+ //!< 1: Enable frame filtering + uint16_t frameFiltStop:1; //!< \brief 0: Receive all packets to the end
+ //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. + uint16_t autoAckEn:1; //!< \brief 0: Disable auto ACK
+ //!< 1: Enable auto ACK. + uint16_t slottedAckEn:1; //!< \brief 0: Non-slotted ACK
+ //!< 1: Slotted ACK. + uint16_t autoPendEn:1; //!< \brief 0: Auto-pend disabled
+ //!< 1: Auto-pend enabled + uint16_t defaultPend:1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend + uint16_t bPendDataReqOnly:1; //!< \brief 0: Use auto-pend for any packet
+ //!< 1: Use auto-pend for data request packets only + uint16_t bPanCoord:1; //!< \brief 0: Device is not PAN coordinator
+ //!< 1: Device is PAN coordinator + uint16_t maxFrameVersion:2; //!< Reject frames where the frame version field in the FCF is greater than this value + uint16_t fcfReservedMask:3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero + uint16_t modifyFtFilter:2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
+ //!< 0: No modification
+ //!< 1: Invert MSB
+ //!< 2: Set MSB to 0
+ //!< 3: Set MSB to 1 + uint16_t bStrictLenFilter:1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
+ //!< 1: Accept only acknowledgement frames of length 5 + } newFrameFiltOpt; //!< New value of frameFiltOpt for the running background level operation + struct { + uint8_t bAcceptFt0Beacon:1; //!< \brief Treatment of frames with frame type 000 (beacon):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt1Data:1; //!< \brief Treatment of frames with frame type 001 (data):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt2Ack:1; //!< \brief Treatment of frames with frame type 010 (ACK):
+ //!< 0: Reject, unless running ACK receive command
+ //!< 1: Always accept + uint8_t bAcceptFt3MacCmd:1; //!< \brief Treatment of frames with frame type 011 (MAC command):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt4Reserved:1; //!< \brief Treatment of frames with frame type 100 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt5Reserved:1; //!< \brief Treatment of frames with frame type 101 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt6Reserved:1; //!< \brief Treatment of frames with frame type 110 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt7Reserved:1; //!< \brief Treatment of frames with frame type 111 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + } newFrameTypes; //!< New value of frameTypes for the running background level operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_MOD_SRC_MATCH +//! @{ +#define CMD_IEEE_MOD_SRC_MATCH 0x2003 +//! IEEE 802.15.4 Enable/Disable Source Matching Entry Command +struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s { + uint16_t commandNo; //!< The command ID number 0x2003 + struct { + uint8_t bEnable:1; //!< \brief 0: Disable entry
+ //!< 1: Enable entry + uint8_t srcPend:1; //!< New value of the pending bit for the entry + uint8_t entryType:1; //!< \brief 0: Short address
+ //!< 1: Extended address + } options; + uint8_t entryNo; //!< Index of entry to enable or disable +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_ABORT_FG +//! @{ +#define CMD_IEEE_ABORT_FG 0x2401 +//! IEEE 802.15.4 Abort Foreground Level Command +struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s { + uint16_t commandNo; //!< The command ID number 0x2401 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_STOP_FG +//! @{ +#define CMD_IEEE_STOP_FG 0x2402 +//! IEEE 802.15.4 Gracefully Stop Foreground Level Command +struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s { + uint16_t commandNo; //!< The command ID number 0x2402 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_CCA_REQ +//! @{ +#define CMD_IEEE_CCA_REQ 0x2403 +//! IEEE 802.15.4 CCA and RSSI Information Request Command +struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s { + uint16_t commandNo; //!< The command ID number 0x2403 + int8_t currentRssi; //!< The RSSI currently observed on the channel + int8_t maxRssi; //!< The maximum RSSI observed on the channel since Rx was started + struct { + uint8_t ccaState:2; //!< \brief Value of the current CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaEnergy:2; //!< \brief Value of the current energy detect CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaCorr:2; //!< \brief Value of the current correlator based carrier sense CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaSync:1; //!< \brief Value of the current sync found based carrier sense CCA state
+ //!< 0: Idle
+ //!< 1: Busy + } ccaInfo; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ieeeRxOutput +//! @{ +//! Output structure for CMD_IEEE_RX + +struct __RFC_STRUCT rfc_ieeeRxOutput_s { + uint8_t nTxAck; //!< Total number of transmitted ACK frames + uint8_t nRxBeacon; //!< Number of received beacon frames + uint8_t nRxData; //!< Number of received data frames + uint8_t nRxAck; //!< Number of received acknowledgement frames + uint8_t nRxMacCmd; //!< Number of received MAC command frames + uint8_t nRxReserved; //!< Number of received frames with reserved frame type + uint8_t nRxNok; //!< Number of received frames with CRC error + uint8_t nRxIgnored; //!< Number of frames received that are to be ignored + uint8_t nRxBufFull; //!< Number of received frames discarded because the Rx buffer was full + int8_t lastRssi; //!< RSSI of last received frame + int8_t maxRssi; //!< Highest RSSI observed in the operation + uint8_t __dummy0; + ratmr_t beaconTimeStamp; //!< Time stamp of last received beacon frame +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup shortAddrEntry +//! @{ +//! Structure for short address entries + +struct __RFC_STRUCT rfc_shortAddrEntry_s { + uint16_t shortAddr; //!< Short address + uint16_t panId; //!< PAN ID +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ieeeRxCorrCrc +//! @{ +//! Receive status byte that may be appended to message in receive buffer + +struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s { + struct { + uint8_t corr:6; //!< The correlation value + uint8_t bIgnore:1; //!< 1 if the packet should be rejected by frame filtering, 0 otherwise + uint8_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h new file mode 100644 index 0000000..7f76b5b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h @@ -0,0 +1,73 @@ +/****************************************************************************** +* Filename: rf_ieee_mailbox.h +* Revised: 2018-01-23 19:51:42 +0100 (Tue, 23 Jan 2018) +* Revision: 18189 +* +* Description: Definitions for IEEE 802.15.4 interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _IEEE_MAILBOX_H +#define _IEEE_MAILBOX_H + +#include "rf_mailbox.h" + +/// \name Radio operation status +///@{ +/// \name Operation not finished +///@{ +#define IEEE_SUSPENDED 0x2001 ///< Operation suspended +///@} +/// \name Operation finished normally +///@{ +#define IEEE_DONE_OK 0x2400 ///< Operation ended normally +#define IEEE_DONE_BUSY 0x2401 ///< CSMA-CA operation ended with failure +#define IEEE_DONE_STOPPED 0x2402 ///< Operation stopped after stop command +#define IEEE_DONE_ACK 0x2403 ///< ACK packet received with pending data bit cleared +#define IEEE_DONE_ACKPEND 0x2404 ///< ACK packet received with pending data bit set +#define IEEE_DONE_TIMEOUT 0x2405 ///< Operation ended due to timeout +#define IEEE_DONE_BGEND 0x2406 ///< FG operation ended because necessary background level + ///< operation ended +#define IEEE_DONE_ABORT 0x2407 ///< Operation aborted by command +///@} +/// \name Operation finished with error +///@{ +#define IEEE_ERROR_PAR 0x2800 ///< Illegal parameter +#define IEEE_ERROR_NO_SETUP 0x2801 ///< Operation using Rx or Tx attempted when not in 15.4 mode +#define IEEE_ERROR_NO_FS 0x2802 ///< Operation using Rx or Tx attempted without frequency synth configured +#define IEEE_ERROR_SYNTH_PROG 0x2803 ///< Synthesizer programming failed to complete on time +#define IEEE_ERROR_RXOVF 0x2804 ///< Receiver overflowed during operation +#define IEEE_ERROR_TXUNF 0x2805 ///< Transmitter underflowed during operation +///@} +///@} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h new file mode 100644 index 0000000..9ae9c7d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h @@ -0,0 +1,364 @@ +/****************************************************************************** +* Filename: rf_mailbox.h +* Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018) +* Revision: 18756 +* +* Description: Definitions for interface between system and radio CPU +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _MAILBOX_H +#define _MAILBOX_H + +#include +#include + + +/// \name RF mode values +/// Defines used to indicate mode of operation to radio core. +///@{ +#define RF_MODE_AUTO 0x00 +#define RF_MODE_BLE 0x00 +#define RF_MODE_IEEE_15_4 0x00 +#define RF_MODE_PROPRIETARY_2_4 0x00 +#define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4 +#define RF_MODE_MULTIPLE 0x00 +///@} + + +/// Type definition for RAT +typedef uint32_t ratmr_t; + + + +/// Type definition for a data queue +typedef struct { + uint8_t *pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue + uint8_t *pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue +} dataQueue_t; + + + +/// \name CPE interrupt definitions +/// Interrupt masks for the CPE interrupt in RDBELL. +///@{ +#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished +#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished +#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished +#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished +#define IRQN_TX_DONE 4 ///< Packet transmitted +#define IRQN_TX_ACK 5 ///< ACK packet transmitted +#define IRQN_TX_CTRL 6 ///< Control packet transmitted +#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet +#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet +#define IRQN_TX_RETRANS 9 ///< Packet retransmitted +#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished +#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete +#define IRQN_COMMAND_STARTED 12 ///< A radio operation command has gone into active state +#define IRQN_FG_COMMAND_STARTED 13 ///< FG level radio operation command has gone into active state +#define IRQN_PA_CHANGED 14 ///< PA is changed +#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored +#define IRQN_RX_NOK 17 ///< Packet received with CRC error +#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored +#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload +#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored +#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent +#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue +#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished +#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer +#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer +#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done +#define IRQN_RX_COLLISION_DETECTED 27 ///< A collision was indicated during packet reception +#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration +#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories +#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished + +#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed + +#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE) +#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE) +#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE) +#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE) + +#define IRQ_TX_DONE (1U << IRQN_TX_DONE) +#define IRQ_TX_ACK (1U << IRQN_TX_ACK) +#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL) +#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK) +#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK) +#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS) + +#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE) +#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED) + +#define IRQ_COMMAND_STARTED (1U << IRQN_COMMAND_STARTED) +#define IRQ_FG_COMMAND_STARTED (1U << IRQN_FG_COMMAND_STARTED) +#define IRQ_PA_CHANGED (1U << IRQN_PA_CHANGED) + +#define IRQ_RX_OK (1U << IRQN_RX_OK) +#define IRQ_RX_NOK (1U << IRQN_RX_NOK) +#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED) +#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY) +#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL) +#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK) +#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL) +#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE) +#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN) +#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN) +#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED) +#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED) +#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK) +#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED) +#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE) +#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR) +///@} + + + +/// \name CMDSTA values +/// Values returned in result byte of CMDSTA +///@{ +#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed +#define CMDSTA_Done 0x01 ///< Command successfully parsed + +#define CMDSTA_IllegalPointer 0x81 ///< The pointer signaled in CMDR is not valid +#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown +#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the + ///< command is not a direct command +#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context + ///< where it is not supported +#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled + ///< while another operation was already running in the RF core +#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed + ///< on submission. +#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was + ///< not supported by the queue in its current state +#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry + ///< was busy +///@} + + + +/// \name Macros for sending direct commands +///@{ +/// Direct command with no parameter +#define CMDR_DIR_CMD(cmdId) (((cmdId) << 16) | 1) + +/// Direct command with 1-byte parameter +#define CMDR_DIR_CMD_1BYTE(cmdId, par) (((cmdId) << 16) | ((par) << 8) | 1) + +/// Direct command with 2-byte parameter +#define CMDR_DIR_CMD_2BYTE(cmdId, par) (((cmdId) << 16) | ((par) & 0xFFFC) | 1) + +///@} + + + +/// \name Definitions for trigger types +///@{ +#define TRIG_NOW 0 ///< Triggers immediately +#define TRIG_NEVER 1 ///< Never trigs +#define TRIG_ABSTIME 2 ///< Trigs at an absolute time +#define TRIG_REL_SUBMIT 3 ///< Trigs at a time relative to the command was submitted +#define TRIG_REL_START 4 ///< Trigs at a time relative to the command started +#define TRIG_REL_PREVSTART 5 ///< Trigs at a time relative to the previous command in the chain started +#define TRIG_REL_FIRSTSTART 6 ///< Trigs at a time relative to the first command in the chain started +#define TRIG_REL_PREVEND 7 ///< Trigs at a time relative to the previous command in the chain ended +#define TRIG_REL_EVT1 8 ///< Trigs at a time relative to the context defined "Event 1" +#define TRIG_REL_EVT2 9 ///< Trigs at a time relative to the context defined "Event 2" +#define TRIG_EXTERNAL 10 ///< Trigs at an external event to the radio timer +#define TRIG_PAST_BM 0x80 ///< Bitmask for setting pastTrig bit in order to trig immediately if + ///< trigger happened in the past +///@} + + +/// \name Definitions for conditional execution +///@{ +#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort) +#define COND_NEVER 1 ///< Never run next command +#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned + ///< False +#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned + ///< False +#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of + ///< commands if it returned False +#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next + ///< command if it returned False +///@} + + + +/// \name Radio operation status +///@{ +/// \name Operation not finished +///@{ +#define IDLE 0x0000 ///< Operation not started +#define PENDING 0x0001 ///< Start of command is pending +#define ACTIVE 0x0002 ///< Running +#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command +///@} +/// \name Operation finished normally +///@{ +#define DONE_OK 0x0400 ///< Operation ended normally +#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero +#define DONE_RXERR 0x0402 ///< Operation ended with CRC error +#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout +#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command +#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command +#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed +///@} +/// \name Operation finished with error +///@{ +#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past +#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter +#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation +#define ERROR_PAR 0x0803 ///< Error in a command specific parameter +#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation +#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio + ///< operation command +#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command +#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attempted without CMD_RADIO_SETUP +#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attempted without frequency synth configured +#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed +#define ERROR_TXUNF 0x080A ///< Tx underflow observed +#define ERROR_RXOVF 0x080B ///< Rx overflow observed +#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received +#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending +///@} +///@} + + +/// \name Data entry types +///@{ +#define DATA_ENTRY_TYPE_GEN 0 ///< General type: Tx entry or single element Rx entry +#define DATA_ENTRY_TYPE_MULTI 1 ///< Multi-element Rx entry type +#define DATA_ENTRY_TYPE_PTR 2 ///< Pointer entry type +#define DATA_ENTRY_TYPE_PARTIAL 3 ///< Partial read entry type +///@ + + +/// \name Data entry statuses +///@{ +#define DATA_ENTRY_PENDING 0 ///< Entry not yet used +#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU +#define DATA_ENTRY_BUSY 2 ///< Entry being updated +#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry +#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished +///@} + + +/// \name Macros for RF register override +///@{ +/// Macro for ADI half-size value-mask combination +#define ADI_VAL_MASK(addr, mask, value) \ +(((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \ + ((((mask) & 0x0F) << 4) | ((value) & 0x0F))) +/// 32-bit write of 16-bit value +#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16)) +/// ADI register, full-size write +#define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \ +(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) +/// 2 ADI registers, full-size write +#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \ +(2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \ +(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) +/// ADI register, half-size read-modify-write +#define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \ +(((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) +/// 2 ADI registers, half-size read-modify-write +#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \ +(2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \ +(ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) + +/// 16-bit SW register as defined in radio_par_def.txt +#define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16)) +/// SW register as defined in radio_par_def.txt with added index (for use with registers > 16 bits). +#define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \ +(((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16)) +/// 8-bit SW register as defined in radio_par_def.txt +#define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \ +(((uint32_t)(val) & 0xFF) << 16)) +/// Two 8-bit SW registers as defined in radio_par_def.txt; the one given by field and the next byte. +#define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \ + (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24)) +#define SW_REG_MASK_OVERRIDE(cmd, field, offset, mask, val) (0x8003 | \ +((_POSITION_##cmd##_##field + (offset)) << 4) | (((uint32_t)(val) & 0xFF) << 16) | (((uint32_t)(mask) & 0xFF) << 24)) + +#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \ +((uint32_t)(length) << 16) | (1U << 30)) +#define HW16_MASK_ARRAY_OVERRIDE(addr, length) (0x20000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW32_MASK_ARRAY_OVERRIDE(addr, length) (0x60000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW16_MASK_VAL(mask, val) ((mask) << 16 | (val)) +#define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \ +((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30)) +#define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \ +((uint32_t)(length) << 16) | (3U << 30)) +#define MCE_RFE_OVERRIDE(mceCfg, mceRomBank, mceMode, rfeCfg, rfeRomBank, rfeMode) \ + (7 | ((mceCfg & 2) << 3) | ((rfeCfg & 2) << 4) |\ + ((mceCfg & 1) << 6) | (((mceRomBank) & 0x0F) << 7) | \ + ((rfeCfg & 1) << 11) | (((rfeRomBank) & 0x0F) << 12) | \ + (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24)) +#define HPOSC_OVERRIDE(freqOffset) (0x000B | ((freqOffset) << 16)) +#define TX20_POWER_OVERRIDE(tx20Power) (0x002B | (((uint32_t) tx20Power) << 10)) +#define TX_STD_POWER_OVERRIDE(txPower) (0x022B | (((uint32_t) txPower) << 10)) +#define MCE_RFE_SPLIT_OVERRIDE(mceRxCfg, mceTxCfg, rfeRxCfg, rfeTxCfg) \ + (0x003B | ((mceRxCfg) << 12) | ((mceTxCfg) << 17) | ((rfeRxCfg) << 22) | ((rfeTxCfg) << 27)) +#define CENTER_FREQ_OVERRIDE(centerFreq, flags) (0x004B | ((flags & 0x03) << 18) | \ + ((centerFreq) << 20)) +#define MOD_TYPE_OVERRIDE(modType, deviation, stepSz, flags) (0x005B | ((flags & 0x01) << 15) | \ + ((modType) << 16) | ((deviation) << 19) |((stepSz) << 30) ) +#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \ + (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \ + (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \ + (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \ + (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \ + (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \ + (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \ + (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \ + (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \ + 0x09) << 4)) // Use illegal value for illegal address range +/// End of string for override register +#define END_OVERRIDE 0xFFFFFFFF + + +/// ADI address-value pair +#define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF)) +#define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value)) + +/// Low half-word +#define LOWORD(value) ((value) & 0xFFFF) +/// High half-word +#define HIWORD(value) ((value) >> 16) +///@} + + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h new file mode 100644 index 0000000..3bc74e3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h @@ -0,0 +1,1171 @@ +/****************************************************************************** +* Filename: rf_prop_cmd.h +* Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018) +* Revision: 18572 +* +* Description: CC13x2/CC26x2 API for Proprietary mode commands +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __PROP_CMD_H +#define __PROP_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup prop_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_carrierSense_s rfc_carrierSense_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_s rfc_CMD_PROP_TX_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_s rfc_CMD_PROP_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s rfc_CMD_PROP_TX_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s rfc_CMD_PROP_RX_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_CS_s rfc_CMD_PROP_CS_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s rfc_CMD_PROP_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s rfc_CMD_PROP_RADIO_DIV_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_SNIFF_s rfc_CMD_PROP_RX_SNIFF_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_SNIFF_s rfc_CMD_PROP_RX_ADV_SNIFF_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_PA_s rfc_CMD_PROP_RADIO_SETUP_PA_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_PA_s rfc_CMD_PROP_RADIO_DIV_SETUP_PA_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s rfc_CMD_PROP_SET_LEN_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s rfc_CMD_PROP_RESTART_RX_t; +typedef struct __RFC_STRUCT rfc_propRxOutput_s rfc_propRxOutput_t; +typedef struct __RFC_STRUCT rfc_propRxStatus_s rfc_propRxStatus_t; + +//! \addtogroup carrierSense +//! @{ +struct __RFC_STRUCT rfc_carrierSense_s { + struct { + uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion + uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct { + uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_TX +//! @{ +#define CMD_PROP_TX 0x3801 +//! Proprietary Mode Transmit Command +struct __RFC_STRUCT rfc_CMD_PROP_TX_s { + uint16_t commandNo; //!< The command ID number 0x3801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t :2; + uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Transmit length as first byte + } pktConf; + uint8_t pktLen; //!< Packet length + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX +//! @{ +#define CMD_PROP_RX 0x3802 +//! Proprietary Mode Receive Command +struct __RFC_STRUCT rfc_CMD_PROP_RX_s { + uint16_t commandNo; //!< The command ID number 0x3802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bChkAddress:1; //!< \brief 0: No address check
+ //!< 1: Check address + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord; //!< Sync word to listen for + uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + uint8_t address0; //!< Address + uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept + //!< 0x00 as well) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_TX_ADV +//! @{ +#define CMD_PROP_TX_ADV 0x3803 +//! Proprietary Mode Advanced Transmit Command +struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s { + uint16_t commandNo; //!< The command ID number 0x3803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t :2; + uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bCrcIncSw:1; //!< \brief 0:Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + } pktConf; + uint8_t numHdrBits; //!< Number of bits in header (0--32) + uint16_t pktLen; //!< Packet length. 0: Unlimited + struct { + uint8_t bExtTxTrig:1; //!< \brief 0: Start packet on a fixed time from the command start trigger
+ //!< 1: Start packet on an external trigger (input event to RAT) + uint8_t inputMode:2; //!< \brief Input mode if external trigger is used for TX start
+ //!< 0: Rising edge
+ //!< 1: Falling edge
+ //!< 2: Both edges
+ //!< 3: Reserved + uint8_t source:5; //!< RAT input event number used for capture if external trigger is used for TX start + } startConf; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } preTrigger; //!< Trigger for transition from preamble to sync word + ratmr_t preTime; //!< \brief Time used together with preTrigger for transition from preamble to sync + //!< word. If preTrigger.triggerType is set to "now", one preamble as + //!< configured in the setup will be sent. Otherwise, the preamble will be repeated until + //!< this trigger is observed. + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet, or TX queue for unlimited length +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX_ADV +//! @{ +#define CMD_PROP_RX_ADV 0x3804 +//! Proprietary Mode Advanced Receive Command +struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s { + uint16_t commandNo; //!< The command ID number 0x3804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bCrcIncSw:1; //!< \brief 0: Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord0; //!< Sync word to listen for + uint32_t syncWord1; //!< Alternative sync word if non-zero + uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + struct { + uint16_t numHdrBits:6; //!< Number of bits in header (0--32) + uint16_t lenPos:5; //!< Position of length field in header (0--31) + uint16_t numLenBits:5; //!< Number of bits in length field (0--16) + } hdrConf; + struct { + uint16_t addrType:1; //!< \brief 0: Address after header
+ //!< 1: Address in header + uint16_t addrSize:5; //!< \brief If addrType = 0: Address size in bytes
+ //!< If addrType = 1: Address size in bits + uint16_t addrPos:5; //!< \brief If addrType = 1: Bit position of address in header
+ //!< If addrType = 0: Non-zero to extend address with sync word identifier + uint16_t numAddr:5; //!< Number of addresses in address list + } addrConf; + int8_t lenOffset; //!< Signed value to add to length field + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + uint8_t* pAddr; //!< Pointer to address list + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_CS +//! @{ +#define CMD_PROP_CS 0x3805 +//! Carrier Sense Command +struct __RFC_STRUCT rfc_CMD_PROP_CS_s { + uint16_t commandNo; //!< The command ID number 0x3805 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOffIdle:1; //!< \brief 0: Keep synth running if command ends with channel Idle
+ //!< 1: Turn off synth if command ends with channel Idle + uint8_t bFsOffBusy:1; //!< \brief 0: Keep synth running if command ends with channel Busy
+ //!< 1: Turn off synth if command ends with channel Busy + } csFsConf; + uint8_t __dummy0; + struct { + uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion + uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct { + uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RADIO_SETUP +//! @{ +#define CMD_PROP_RADIO_SETUP 0x3806 +//! Proprietary Mode Radio Setup Command for 2.4 GHz +struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x3806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t modType:3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< 2: OOK
+ //!< Others: Reserved + uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) + uint16_t deviationStepSz:2; //!< \brief Deviation step size
+ //!< 0: 250 Hz
+ //!< 1: 1000 Hz
+ //!< 2: 15.625 Hz
+ //!< 3: 62.5 Hz + } modulation; + struct { + uint32_t preScale:8; //!< Prescaler value + uint32_t rateWord:21; //!< Rate word + uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct { + uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct { + uint16_t nSwBits:6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode:4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t :1; + uint16_t whitenMode:3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RADIO_DIV_SETUP +//! @{ +#define CMD_PROP_RADIO_DIV_SETUP 0x3807 +//! Proprietary Mode Radio Setup Command for All Frequency Bands +struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x3807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t modType:3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< 2: OOK
+ //!< Others: Reserved + uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) + uint16_t deviationStepSz:2; //!< \brief Deviation step size
+ //!< 0: 250 Hz
+ //!< 1: 1000 Hz
+ //!< 2: 15.625 Hz
+ //!< 3: 62.5 Hz + } modulation; + struct { + uint32_t preScale:8; //!< Prescaler value + uint32_t rateWord:21; //!< Rate word + uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct { + uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct { + uint16_t nSwBits:6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode:4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t :1; + uint16_t whitenMode:3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters. + //!< For a single channel RF system, this should be set equal to the RF frequency used. + //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal + //!< to the center frequency of the frequency band used. + int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same + //!< intermediate frequency if supported, otherwise 0.
+ //!< 0x8000: Use default. + uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 0, 2, 4, 5, 6, 10, 12, 15, and 30 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX_SNIFF +//! @{ +#define CMD_PROP_RX_SNIFF 0x3808 +//! Proprietary Mode Receive Command with Sniff Mode +struct __RFC_STRUCT rfc_CMD_PROP_RX_SNIFF_s { + uint16_t commandNo; //!< The command ID number 0x3808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bChkAddress:1; //!< \brief 0: No address check
+ //!< 1: Check address + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord; //!< Sync word to listen for + uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + uint8_t address0; //!< Address + uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept + //!< 0x00 as well) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure + struct { + uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion + uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct { + uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX_ADV_SNIFF +//! @{ +#define CMD_PROP_RX_ADV_SNIFF 0x3809 +//! Proprietary Mode Advanced Receive Command with Sniff Mode +struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_SNIFF_s { + uint16_t commandNo; //!< The command ID number 0x3809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bCrcIncSw:1; //!< \brief 0: Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord0; //!< Sync word to listen for + uint32_t syncWord1; //!< Alternative sync word if non-zero + uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + struct { + uint16_t numHdrBits:6; //!< Number of bits in header (0--32) + uint16_t lenPos:5; //!< Position of length field in header (0--31) + uint16_t numLenBits:5; //!< Number of bits in length field (0--16) + } hdrConf; + struct { + uint16_t addrType:1; //!< \brief 0: Address after header
+ //!< 1: Address in header + uint16_t addrSize:5; //!< \brief If addrType = 0: Address size in bytes
+ //!< If addrType = 1: Address size in bits + uint16_t addrPos:5; //!< \brief If addrType = 1: Bit position of address in header
+ //!< If addrType = 0: Non-zero to extend address with sync word identifier + uint16_t numAddr:5; //!< Number of addresses in address list + } addrConf; + int8_t lenOffset; //!< Signed value to add to length field + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + uint8_t* pAddr; //!< Pointer to address list + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure + struct { + uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion + uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct { + uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RADIO_SETUP_PA +//! @{ +//! Proprietary Mode Radio Setup Command for 2.4 GHz with PA Switching Fields +struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_PA_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t modType:3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< 2: OOK
+ //!< Others: Reserved + uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) + uint16_t deviationStepSz:2; //!< \brief Deviation step size
+ //!< 0: 250 Hz
+ //!< 1: 1000 Hz
+ //!< 2: 15.625 Hz
+ //!< 3: 62.5 Hz + } modulation; + struct { + uint32_t preScale:8; //!< Prescaler value + uint32_t rateWord:21; //!< Rate word + uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct { + uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct { + uint16_t nSwBits:6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode:4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t :1; + uint16_t whitenMode:3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< standard PA. Used by RF driver only, not radio CPU. + uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< 20-dBm PA. Used by RF driver only, not radio CPU. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RADIO_DIV_SETUP_PA +//! @{ +//! Proprietary Mode Radio Setup Command for All Frequency Bands with PA Switching Fields +struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_PA_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t modType:3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< 2: OOK
+ //!< Others: Reserved + uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) + uint16_t deviationStepSz:2; //!< \brief Deviation step size
+ //!< 0: 250 Hz
+ //!< 1: 1000 Hz
+ //!< 2: 15.625 Hz
+ //!< 3: 62.5 Hz + } modulation; + struct { + uint32_t preScale:8; //!< Prescaler value + uint32_t rateWord:21; //!< Rate word + uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct { + uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct { + uint16_t nSwBits:6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode:4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t :1; + uint16_t whitenMode:3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters. + //!< For a single channel RF system, this should be set equal to the RF frequency used. + //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal + //!< to the center frequency of the frequency band used. + int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same + //!< intermediate frequency if supported, otherwise 0.
+ //!< 0x8000: Use default. + uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 0, 2, 4, 5, 6, 10, 12, 15, and 30 + uint8_t __dummy0; + uint16_t __dummy1; + uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< standard PA. Used by RF driver only, not radio CPU. + uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< 20-dBm PA. Used by RF driver only, not radio CPU. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_SET_LEN +//! @{ +#define CMD_PROP_SET_LEN 0x3401 +//! Set Packet Length Command +struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s { + uint16_t commandNo; //!< The command ID number 0x3401 + uint16_t rxLen; //!< Payload length to use +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RESTART_RX +//! @{ +#define CMD_PROP_RESTART_RX 0x3402 +//! Restart Packet Command +struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s { + uint16_t commandNo; //!< The command ID number 0x3402 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup propRxOutput +//! @{ +//! Output structure for RX operations + +struct __RFC_STRUCT rfc_propRxOutput_s { + uint16_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint16_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< Number of packets that have been received with CRC OK and ignored due to address mismatch + uint8_t nRxStopped; //!< Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1 + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + ratmr_t timeStamp; //!< Time stamp of last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup propRxStatus +//! @{ +//! Receive status byte that may be appended to message in receive buffer + +struct __RFC_STRUCT rfc_propRxStatus_s { + struct { + uint8_t addressInd:5; //!< Index of address found (0 if not applicable) + uint8_t syncWordId:1; //!< 0 for primary sync word, 1 for alternate sync word + uint8_t result:2; //!< \brief 0: Packet received correctly, not ignored
+ //!< 1: Packet received with CRC error
+ //!< 2: Packet received correctly, but can be ignored
+ //!< 3: Packet reception was aborted + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h new file mode 100644 index 0000000..c6ac409 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h @@ -0,0 +1,71 @@ +/****************************************************************************** +* Filename: rf_prop_mailbox.h +* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) +* Revision: 18171 +* +* Description: Definitions for proprietary mode radio interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _PROP_MAILBOX_H +#define _PROP_MAILBOX_H + +/// \name Radio operation status +///@{ +/// \name Operation finished normally +///@{ +#define PROP_DONE_OK 0x3400 ///< Operation ended normally +#define PROP_DONE_RXTIMEOUT 0x3401 ///< Operation stopped after end trigger while waiting for sync +#define PROP_DONE_BREAK 0x3402 ///< Rx stopped due to timeout in the middle of a packet +#define PROP_DONE_ENDED 0x3403 ///< Operation stopped after end trigger during reception +#define PROP_DONE_STOPPED 0x3404 ///< Operation stopped after stop command +#define PROP_DONE_ABORT 0x3405 ///< Operation aborted by abort command +#define PROP_DONE_RXERR 0x3406 ///< Operation ended after receiving packet with CRC error +#define PROP_DONE_IDLE 0x3407 ///< Carrier sense operation ended because of idle channel +#define PROP_DONE_BUSY 0x3408 ///< Carrier sense operation ended because of busy channel +#define PROP_DONE_IDLETIMEOUT 0x3409 ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 1 +#define PROP_DONE_BUSYTIMEOUT 0x340A ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 0 + +///@} +/// \name Operation finished with error +///@{ +#define PROP_ERROR_PAR 0x3800 ///< Illegal parameter +#define PROP_ERROR_RXBUF 0x3801 ///< No available Rx buffer at the start of a packet +#define PROP_ERROR_RXFULL 0x3802 ///< Out of Rx buffer during reception in a partial read buffer +#define PROP_ERROR_NO_SETUP 0x3803 ///< Radio was not set up in proprietary mode +#define PROP_ERROR_NO_FS 0x3804 ///< Synth was not programmed when running Rx or Tx +#define PROP_ERROR_RXOVF 0x3805 ///< Rx overflow observed during operation +#define PROP_ERROR_TXUNF 0x3806 ///< Tx underflow observed during operation +///@} +///@} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.c new file mode 100644 index 0000000..8cbb3ef --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.c @@ -0,0 +1,295 @@ +/****************************************************************************** +* Filename: rfc.c +* Revised: 2018-08-08 11:04:37 +0200 (Wed, 08 Aug 2018) +* Revision: 52334 +* +* Description: Driver for the RF Core. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "rfc.h" +#include "rf_mailbox.h" +#include + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef RFCCpeIntGetAndClear + #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear + #undef RFCDoorbellSendTo + #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo + #undef RFCSynthPowerDown + #define RFCSynthPowerDown NOROM_RFCSynthPowerDown + #undef RFCCpePatchReset + #define RFCCpePatchReset NOROM_RFCCpePatchReset + #undef RFCOverrideSearch + #define RFCOverrideSearch NOROM_RFCOverrideSearch + #undef RFCOverrideUpdate + #define RFCOverrideUpdate NOROM_RFCOverrideUpdate + #undef RFCHwIntGetAndClear + #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #undef RFCAnaDivTxOverride + #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride +#endif + + +//***************************************************************************** +// +// Get and clear CPE interrupt flags which match the provided bitmask +// +//***************************************************************************** +uint32_t +RFCCpeIntGetAndClear(uint32_t ui32Mask) +{ + // Read the CPE interrupt flags which match the provided bitmask + uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask; + + // Clear the interrupt flags + RFCCpeIntClear(ui32Ifg); + + // Return with the interrupt flags + return (ui32Ifg); +} + + +//***************************************************************************** +// +// Send a radio operation to the doorbell and wait for an acknowledgement +// +//***************************************************************************** +uint32_t +RFCDoorbellSendTo(uint32_t pOp) +{ + // Wait until the doorbell becomes available + while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) != 0); + RFCAckIntClear(); + + // Submit the command to the CM0 through the doorbell + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) = pOp; + + // Wait until the CM0 starts to parse the command + while(!HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG)); + RFCAckIntClear(); + + // Return with the content of status register + return(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDSTA)); +} + + +//***************************************************************************** +// +// Turn off the RF synthesizer. The radio will no longer respond to commands! +// +//***************************************************************************** +void +RFCSynthPowerDown(void) +{ + // Definition of reserved words + const uint32_t RFC_RESERVED0 = 0x40046054; + const uint32_t RFC_RESERVED1 = 0x40046060; + const uint32_t RFC_RESERVED2 = 0x40046058; + const uint32_t RFC_RESERVED3 = 0x40044100; + + // Disable CPE clock, enable FSCA clock. + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = (HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) + & ~RFC_PWR_PWMCLKEN_CPE_M) | RFC_PWR_PWMCLKEN_FSCA_M | RFC_PWR_PWMCLKEN_RFE_M; + + HWREG(RFC_RESERVED0) = 3; + HWREG(RFC_RESERVED1) = 0x1030; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED1) = 0x50; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED1) = 0x650; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED1) = 0x10C0; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED3) = 1; +} + + +//***************************************************************************** +// +// Reset previously patched CPE RAM to a state where it can be patched again +// +//***************************************************************************** +void +RFCCpePatchReset(void) +{ + // Function is not complete +} + + +//***************************************************************************** +// +// Function to search an override list for the provided pattern within the search depth. +// +//***************************************************************************** +uint8_t +RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth) +{ + // Search from start of the override list, to look for first override entry that matches search pattern + uint8_t override_index; + for(override_index = 0; (override_index < searchDepth) && (pOverride[override_index] != END_OVERRIDE); override_index++) + { + // Compare the value to the given pattern + if((pOverride[override_index] & mask) == pattern) + { + // Return with the index of override in case of match + return override_index; + } + } + + // Return with an invalid index + return 0xFF; +} + +//***************************************************************************** +// +// Function to calculate the proper override run-time for the High Gain PA. +// +//***************************************************************************** +uint32_t +RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode) +{ + uint16_t fsOnly; + uint16_t txSetting; + + switch (loDivider) + { + case 0: fsOnly = 0x0502; + break; + case 2: + fsOnly = 0x0102; + break; + case 4: + case 6: + case 12: + fsOnly = 0xF101; + break; + case 5: + case 10: + case 15: + case 30: + fsOnly = 0x1101; + break; + default: + // Error, should not occur! + fsOnly = 0; + break; + } + + if (frontEndMode == 255) + { + // Special value meaning 20 dBm PA + txSetting = (fsOnly | 0x00C0) & ~0x0400; + } + else if (frontEndMode == 0) + { + // Differential + txSetting = fsOnly | 0x0030; + } + else if (frontEndMode & 1) + { + // Single ended on RFP + txSetting = fsOnly | 0x0010; + } + else + { + // Single ended on RFN + txSetting = fsOnly | 0x0020; + } + + return ((((uint32_t) txSetting) << 16) | RFC_FE_OVERRIDE_ADDRESS); +} + +//***************************************************************************** +// +// Update the override list based on values stored in FCFG1 +// +//***************************************************************************** +uint8_t +RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams) +{ + // Function is left blank for compatibility reasons. + return 0; +} + + +//***************************************************************************** +// +// Get and clear HW interrupt flags +// +//***************************************************************************** +uint32_t +RFCHwIntGetAndClear(uint32_t ui32Mask) +{ + // Read the CPE interrupt flags which match the provided bitmask + uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) & ui32Mask; + + // Clear the interupt flags + RFCHwIntClear(ui32Ifg); + + // Return with the interrupt flags + return (ui32Ifg); +} + + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef RFCCpeIntGetAndClear + #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear + #undef RFCDoorbellSendTo + #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo + #undef RFCSynthPowerDown + #define RFCSynthPowerDown NOROM_RFCSynthPowerDown + #undef RFCCpePatchReset + #define RFCCpePatchReset NOROM_RFCCpePatchReset + #undef RFCOverrideSearch + #define RFCOverrideSearch NOROM_RFCOverrideSearch + #undef RFCOverrideUpdate + #define RFCOverrideUpdate NOROM_RFCOverrideUpdate + #undef RFCHwIntGetAndClear + #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #undef RFCAnaDivTxOverride + #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride +#endif + +// See rfc.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.h new file mode 100644 index 0000000..8f11ddf --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.h @@ -0,0 +1,465 @@ +/****************************************************************************** +* Filename: rfc.h +* Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018) +* Revision: 52338 +* +* Description: Defines and prototypes for the RF Core. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup rfc_api +//! @{ +// +//***************************************************************************** + +#ifndef __RFC_H__ +#define __RFC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_rfc_pwr.h" +#include "../inc/hw_rfc_dbell.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_adi.h" +#include "rf_common_cmd.h" +#include "rf_prop_cmd.h" +#include "rf_ble_cmd.h" + +// Definition of RFTRIM container +typedef struct { + uint32_t configIfAdc; + uint32_t configRfFrontend; + uint32_t configSynth; + uint32_t configMiscAdc; +} rfTrim_t; + +// Definition of maximum search depth used by the RFCOverrideUpdate function +#define RFC_MAX_SEARCH_DEPTH 5 +#define RFC_PA_TYPE_ADDRESS 0x21000345 +#define RFC_PA_TYPE_MASK 0x04 +#define RFC_PA_GAIN_ADDRESS 0x2100034C +#define RFC_PA_GAIN_MASK 0x003FFFFF +#define RFC_FE_MODE_ESCAPE_VALUE 0xFF +#define RFC_FE_OVERRIDE_ADDRESS 0x0703 +#define RFC_FE_OVERRIDE_MASK 0x0000FFFF + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear + #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo + #define RFCSynthPowerDown NOROM_RFCSynthPowerDown + #define RFCCpePatchReset NOROM_RFCCpePatchReset + #define RFCOverrideSearch NOROM_RFCOverrideSearch + #define RFCOverrideUpdate NOROM_RFCOverrideUpdate + #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride +#endif + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enable the RF core clocks. +//! +//! As soon as the RF core is started it will handle clock control +//! autonomously. No check should be performed to check the clocks. Instead +//! the radio can be ping'ed through the command interface. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +RFCClockEnable(void) +{ + // Enable basic clocks to get the CPE run + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM + | RFC_PWR_PWMCLKEN_CPE + | RFC_PWR_PWMCLKEN_RFC; +} + + +//***************************************************************************** +// +//! \brief Disable the RF core clocks. +//! +//! As soon as the RF core is started it will handle clock control +//! autonomously. No check should be performed to check the clocks. Instead +//! the radio can be ping'ed through the command interface. +//! +//! When disabling clocks it is the programmers responsibility that the +//! RF core clocks are safely gated. I.e. the RF core should be safely +//! 'parked'. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +RFCClockDisable(void) +{ + // Disable all clocks + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x0; +} + + +//***************************************************************************** +// +//! Clear HW interrupt flags +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpeIntClear(uint32_t ui32Mask) +{ + // Clear the masked pending interrupts. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = ~ui32Mask; +} + + +//***************************************************************************** +// +//! Clear CPE interrupt flags. +// +//***************************************************************************** +__STATIC_INLINE void +RFCHwIntClear(uint32_t ui32Mask) +{ + // Clear the masked pending interrupts. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = ~ui32Mask; +} + + +//***************************************************************************** +// +//! Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector). +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe0IntSelect(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE0 IRQ. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) &= ~ui32Mask; +} + + +//***************************************************************************** +// +//! Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector). +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe1IntSelect(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE1 IRQ. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) |= ui32Mask; +} + + +//***************************************************************************** +// +//! Enable CPEx interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpeIntEnable(uint32_t ui32Mask) +{ + // Enable CPE interrupts from RF Core. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask; +} + + +//***************************************************************************** +// +//! Select, clear, and enable interrupt sources to CPE0. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe0IntSelectClearEnable(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE0 IRQ. + RFCCpe0IntSelect(ui32Mask); + + // Clear the masked interrupts. + RFCCpeIntClear(ui32Mask); + + // Enable the masked interrupts. + RFCCpeIntEnable(ui32Mask); +} + + +//***************************************************************************** +// +//! Select, clear, and enable interrupt sources to CPE1. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe1IntSelectClearEnable(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE1 IRQ. + RFCCpe1IntSelect(ui32Mask); + + // Clear the masked interrupts. + RFCCpeIntClear(ui32Mask); + + // Enable the masked interrupts. + RFCCpeIntEnable(ui32Mask); +} + + +//***************************************************************************** +// +//! Enable HW interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCHwIntEnable(uint32_t ui32Mask) +{ + // Enable the masked interrupts + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) |= ui32Mask; +} + + +//***************************************************************************** +// +//! Disable CPE interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpeIntDisable(uint32_t ui32Mask) +{ + // Disable the masked interrupts + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) &= ~ui32Mask; +} + + +//***************************************************************************** +// +//! Disable HW interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCHwIntDisable(uint32_t ui32Mask) +{ + // Disable the masked interrupts + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) &= ~ui32Mask; +} + + +//***************************************************************************** +// +//! Get and clear CPE interrupt flags. +// +//***************************************************************************** +extern uint32_t RFCCpeIntGetAndClear(uint32_t ui32Mask); + + +//***************************************************************************** +// +//! Clear ACK interrupt flag. +// +//***************************************************************************** +__STATIC_INLINE void +RFCAckIntClear(void) +{ + // Clear any pending interrupts. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0x0; +} + + +//***************************************************************************** +// +//! Send a radio operation to the doorbell and wait for an acknowledgment. +// +//***************************************************************************** +extern uint32_t RFCDoorbellSendTo(uint32_t pOp); + + +//***************************************************************************** +// +//! This function implements a fast way to turn off the synthesizer. +// +//***************************************************************************** +extern void RFCSynthPowerDown(void); + + +//***************************************************************************** +// +//! Reset previously patched CPE RAM to a state where it can be patched again. +// +//***************************************************************************** +extern void RFCCpePatchReset(void); + + +//***************************************************************************** +// +// Function to search an override list for the provided pattern within the search depth. +// +//***************************************************************************** +extern uint8_t RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth); + + +//***************************************************************************** +// +//! Function to update override list +// +//***************************************************************************** +extern uint8_t RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams); + + +//***************************************************************************** +// +//! Get and clear HW interrupt flags. +// +//***************************************************************************** +extern uint32_t RFCHwIntGetAndClear(uint32_t ui32Mask); + + +//***************************************************************************** +// +//! Get the type of currently selected PA. +// +//***************************************************************************** +__STATIC_INLINE bool +RFCGetPaType(void) +{ + return (bool)(HWREGB(RFC_PA_TYPE_ADDRESS) & RFC_PA_TYPE_MASK); +} + +//***************************************************************************** +// +//! Get the gain of currently selected PA. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +RFCGetPaGain(void) +{ + return (HWREG(RFC_PA_GAIN_ADDRESS) & RFC_PA_GAIN_MASK); +} + + +//***************************************************************************** +// +//! Function to calculate the proper override run-time for the High Gain PA. +// +//***************************************************************************** +extern uint32_t RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode); + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_RFCCpeIntGetAndClear + #undef RFCCpeIntGetAndClear + #define RFCCpeIntGetAndClear ROM_RFCCpeIntGetAndClear + #endif + #ifdef ROM_RFCDoorbellSendTo + #undef RFCDoorbellSendTo + #define RFCDoorbellSendTo ROM_RFCDoorbellSendTo + #endif + #ifdef ROM_RFCSynthPowerDown + #undef RFCSynthPowerDown + #define RFCSynthPowerDown ROM_RFCSynthPowerDown + #endif + #ifdef ROM_RFCCpePatchReset + #undef RFCCpePatchReset + #define RFCCpePatchReset ROM_RFCCpePatchReset + #endif + #ifdef ROM_RFCOverrideSearch + #undef RFCOverrideSearch + #define RFCOverrideSearch ROM_RFCOverrideSearch + #endif + #ifdef ROM_RFCOverrideUpdate + #undef RFCOverrideUpdate + #define RFCOverrideUpdate ROM_RFCOverrideUpdate + #endif + #ifdef ROM_RFCHwIntGetAndClear + #undef RFCHwIntGetAndClear + #define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear + #endif + #ifdef ROM_RFCAnaDivTxOverride + #undef RFCAnaDivTxOverride + #define RFCAnaDivTxOverride ROM_RFCAnaDivTxOverride + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __RFC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom.h new file mode 100644 index 0000000..1a5b9b6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom.h @@ -0,0 +1,1055 @@ +/****************************************************************************** +* Filename: rom.h +* Revised: 2018-11-02 13:54:49 +0100 (Fri, 02 Nov 2018) +* Revision: 53196 +* +* Description: Prototypes for the ROM utility functions. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ROM_H__ +#define __ROM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "../inc/hw_types.h" + +#ifndef __HAPI_H__ +#define __HAPI_H__ + +// Start address of the ROM hard API access table (located after the ROM FW rev field) +#define ROM_HAPI_TABLE_ADDR 0x10000048 + +// ROM Hard-API function interface types +typedef uint32_t (* FPTR_CRC32_T) ( uint8_t* /* pui8Data */,\ + uint32_t /* ui32ByteCount */,\ + uint32_t /* ui32RepeatCount */); + +typedef uint32_t (* FPTR_GETFLSIZE_T) ( void ); + +typedef uint32_t (* FPTR_GETCHIPID_T) ( void ); + +typedef uint32_t (* FPTR_RESERVED1_T) ( uint32_t ); + +typedef uint32_t (* FPTR_RESERVED2_T) ( void ); + +typedef uint32_t (* FPTR_RESERVED3_T) ( uint8_t* ,\ + uint32_t ,\ + uint32_t ); +typedef void (* FPTR_RESETDEV_T) ( void ); + +typedef uint32_t (* FPTR_FLETCHER32_T) ( uint16_t* /* pui16Data */,\ + uint16_t /* ui16WordCount */,\ + uint16_t /* ui16RepeatCount */); + +typedef uint32_t (* FPTR_MINVAL_T) ( uint32_t* /* ulpDataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef uint32_t (* FPTR_MAXVAL_T) ( uint32_t* /* pui32DataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef uint32_t (* FPTR_MEANVAL_T) ( uint32_t* /* pui32DataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef uint32_t (* FPTR_STDDVAL_T) ( uint32_t* /* pui32DataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef void (* FPTR_HFSOURCESAFESWITCH_T) ( void ); + +typedef void (* FPTR_RESERVED4_T) ( uint32_t ); + +typedef void (* FPTR_RESERVED5_T) ( uint32_t ); + +typedef void (* FPTR_COMPAIN_T) ( uint8_t /* ut8Signal */); + +typedef void (* FPTR_COMPAREF_T) ( uint8_t /* ut8Signal */); + +typedef void (* FPTR_ADCCOMPBIN_T) ( uint8_t /* ut8Signal */); + +typedef void (* FPTR_DACVREF_T) ( uint8_t /* ut8Signal */); + +extern uint32_t MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer, + uint32_t ui32Address, + uint32_t ui32Count); + +extern uint32_t MemBusWrkAroundHapiEraseSector(uint32_t ui32Address); + +// ROM Hard-API access table type +typedef struct +{ + FPTR_CRC32_T Crc32; + FPTR_GETFLSIZE_T FlashGetSize; + FPTR_GETCHIPID_T GetChipId; + FPTR_RESERVED1_T ReservedLocation1; + FPTR_RESERVED2_T ReservedLocation2; + FPTR_RESERVED3_T ReservedLocation3; + FPTR_RESETDEV_T ResetDevice; + FPTR_FLETCHER32_T Fletcher32; + FPTR_MINVAL_T MinValue; + FPTR_MAXVAL_T MaxValue; + FPTR_MEANVAL_T MeanValue; + FPTR_STDDVAL_T StandDeviationValue; + FPTR_RESERVED4_T ReservedLocation4; + FPTR_RESERVED5_T ReservedLocation5; + FPTR_HFSOURCESAFESWITCH_T HFSourceSafeSwitch; + FPTR_COMPAIN_T SelectCompAInput; + FPTR_COMPAREF_T SelectCompARef; + FPTR_ADCCOMPBIN_T SelectADCCompBInput; + FPTR_DACVREF_T SelectDACVref; +} HARD_API_T; + +// Pointer to the ROM HAPI table +#define P_HARD_API ((HARD_API_T*) ROM_HAPI_TABLE_ADDR) + +#define HapiCrc32(a,b,c) P_HARD_API->Crc32(a,b,c) +#define HapiGetFlashSize() P_HARD_API->FlashGetSize() +#define HapiGetChipId() P_HARD_API->GetChipId() +#define HapiSectorErase(a) MemBusWrkAroundHapiEraseSector(a) +#define HapiProgramFlash(a,b,c) MemBusWrkAroundHapiProgramFlash(a,b,c) +#define HapiResetDevice() P_HARD_API->ResetDevice() +#define HapiFletcher32(a,b,c) P_HARD_API->Fletcher32(a,b,c) +#define HapiMinValue(a,b) P_HARD_API->MinValue(a,b) +#define HapiMaxValue(a,b) P_HARD_API->MaxValue(a,b) +#define HapiMeanValue(a,b) P_HARD_API->MeanValue(a,b) +#define HapiStandDeviationValue(a,b) P_HARD_API->StandDeviationValue(a,b) +#define HapiHFSourceSafeSwitch() P_HARD_API->HFSourceSafeSwitch() +#define HapiSelectCompAInput(a) P_HARD_API->SelectCompAInput(a) +#define HapiSelectCompARef(a) P_HARD_API->SelectCompARef(a) +#define HapiSelectADCCompBInput(a) P_HARD_API->SelectADCCompBInput(a) +#define HapiSelectDACVref(a) P_HARD_API->SelectDACVref(a) + +// Defines for input parameter to the HapiSelectCompAInput function. +#define COMPA_IN_NC 0x00 +// Defines used in CC13x0/CC26x0 devices +#define COMPA_IN_AUXIO7 0x09 +#define COMPA_IN_AUXIO6 0x0A +#define COMPA_IN_AUXIO5 0x0B +#define COMPA_IN_AUXIO4 0x0C +#define COMPA_IN_AUXIO3 0x0D +#define COMPA_IN_AUXIO2 0x0E +#define COMPA_IN_AUXIO1 0x0F +#define COMPA_IN_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7 +#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6 +#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5 +#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4 +#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3 +#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2 +#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1 +#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0 + +// Defines for input parameter to the HapiSelectCompARef function. +#define COMPA_REF_NC 0x00 +#define COMPA_REF_DCOUPL 0x01 +#define COMPA_REF_VSS 0x02 +#define COMPA_REF_VDDS 0x03 +#define COMPA_REF_ADCVREFP 0x04 +// Defines used in CC13x0/CC26x0 devices +#define COMPA_REF_AUXIO7 0x09 +#define COMPA_REF_AUXIO6 0x0A +#define COMPA_REF_AUXIO5 0x0B +#define COMPA_REF_AUXIO4 0x0C +#define COMPA_REF_AUXIO3 0x0D +#define COMPA_REF_AUXIO2 0x0E +#define COMPA_REF_AUXIO1 0x0F +#define COMPA_REF_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7 +#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6 +#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5 +#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4 +#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3 +#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2 +#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1 +#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0 + +// Defines for input parameter to the HapiSelectADCCompBInput function. +#define ADC_COMPB_IN_NC 0x00 +#define ADC_COMPB_IN_DCOUPL 0x03 +#define ADC_COMPB_IN_VSS 0x04 +#define ADC_COMPB_IN_VDDS 0x05 +// Defines used in CC13x0/CC26x0 devices +#define ADC_COMPB_IN_AUXIO7 0x09 +#define ADC_COMPB_IN_AUXIO6 0x0A +#define ADC_COMPB_IN_AUXIO5 0x0B +#define ADC_COMPB_IN_AUXIO4 0x0C +#define ADC_COMPB_IN_AUXIO3 0x0D +#define ADC_COMPB_IN_AUXIO2 0x0E +#define ADC_COMPB_IN_AUXIO1 0x0F +#define ADC_COMPB_IN_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7 +#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6 +#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5 +#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4 +#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3 +#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2 +#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1 +#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0 + +// Defines for input parameter to the HapiSelectDACVref function. +// The define values can not be changed! +#define DAC_REF_NC 0x00 +#define DAC_REF_DCOUPL 0x01 +#define DAC_REF_VSS 0x02 +#define DAC_REF_VDDS 0x03 + +#endif // __HAPI_H__ + +//***************************************************************************** +// +// Pointers to the main API tables. +// +//***************************************************************************** +#define ROM_API_TABLE ((uint32_t *) 0x10000180) +#define ROM_VERSION (ROM_API_TABLE[0]) + + +#define ROM_API_AON_EVENT_TABLE ((uint32_t*) (ROM_API_TABLE[1])) +#define ROM_API_AON_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[2])) +#define ROM_API_AON_RTC_TABLE ((uint32_t*) (ROM_API_TABLE[3])) +#define ROM_API_AUX_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[5])) +#define ROM_API_AUX_TDC_TABLE ((uint32_t*) (ROM_API_TABLE[6])) +#define ROM_API_DDI_TABLE ((uint32_t*) (ROM_API_TABLE[9])) +#define ROM_API_FLASH_TABLE ((uint32_t*) (ROM_API_TABLE[10])) +#define ROM_API_I2C_TABLE ((uint32_t*) (ROM_API_TABLE[11])) +#define ROM_API_INTERRUPT_TABLE ((uint32_t*) (ROM_API_TABLE[12])) +#define ROM_API_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[13])) +#define ROM_API_PRCM_TABLE ((uint32_t*) (ROM_API_TABLE[14])) +#define ROM_API_SMPH_TABLE ((uint32_t*) (ROM_API_TABLE[15])) +#define ROM_API_SSI_TABLE ((uint32_t*) (ROM_API_TABLE[17])) +#define ROM_API_TIMER_TABLE ((uint32_t*) (ROM_API_TABLE[18])) +#define ROM_API_TRNG_TABLE ((uint32_t*) (ROM_API_TABLE[19])) +#define ROM_API_UART_TABLE ((uint32_t*) (ROM_API_TABLE[20])) +#define ROM_API_UDMA_TABLE ((uint32_t*) (ROM_API_TABLE[21])) +#define ROM_API_VIMS_TABLE ((uint32_t*) (ROM_API_TABLE[22])) +#define ROM_API_CRYPTO_TABLE ((uint32_t*) (ROM_API_TABLE[23])) +#define ROM_API_OSC_TABLE ((uint32_t*) (ROM_API_TABLE[24])) +#define ROM_API_AUX_ADC_TABLE ((uint32_t*) (ROM_API_TABLE[25])) +#define ROM_API_SYS_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[26])) +#define ROM_API_AON_BATMON_TABLE ((uint32_t*) (ROM_API_TABLE[27])) +#define ROM_API_SETUP_ROM_TABLE ((uint32_t*) (ROM_API_TABLE[28])) +#define ROM_API_I2S_TABLE ((uint32_t*) (ROM_API_TABLE[29])) +#define ROM_API_PWR_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[30])) +#define ROM_API_AES_TABLE ((uint32_t*) (ROM_API_TABLE[31])) +#define ROM_API_PKA_TABLE ((uint32_t*) (ROM_API_TABLE[32])) +#define ROM_API_SHA2_TABLE ((uint32_t*) (ROM_API_TABLE[33])) + +// AON_EVENT FUNCTIONS +#define ROM_AONEventMcuWakeUpSet \ + ((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \ + ROM_API_AON_EVENT_TABLE[0]) + +#define ROM_AONEventMcuWakeUpGet \ + ((uint32_t (*)(uint32_t ui32MCUWUEvent)) \ + ROM_API_AON_EVENT_TABLE[1]) + +#define ROM_AONEventMcuSet \ + ((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \ + ROM_API_AON_EVENT_TABLE[4]) + +#define ROM_AONEventMcuGet \ + ((uint32_t (*)(uint32_t ui32MCUEvent)) \ + ROM_API_AON_EVENT_TABLE[5]) + + +// AON_RTC FUNCTIONS +#define ROM_AONRTCCurrent64BitValueGet \ + ((uint64_t (*)(void)) \ + ROM_API_AON_RTC_TABLE[12]) + + +// AUX_TDC FUNCTIONS +#define ROM_AUXTDCConfigSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \ + ROM_API_AUX_TDC_TABLE[0]) + +#define ROM_AUXTDCMeasurementDone \ + ((uint32_t (*)(uint32_t ui32Base)) \ + ROM_API_AUX_TDC_TABLE[1]) + + +// DDI FUNCTIONS +#define ROM_DDI16BitWrite \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData)) \ + ROM_API_DDI_TABLE[0]) + +#define ROM_DDI16BitfieldWrite \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)) \ + ROM_API_DDI_TABLE[1]) + +#define ROM_DDI16BitRead \ + ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \ + ROM_API_DDI_TABLE[2]) + +#define ROM_DDI16BitfieldRead \ + ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \ + ROM_API_DDI_TABLE[3]) + +#define ROM_DDI32RegWrite \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)) \ + ROM_API_DDI_TABLE[4]) + + +// FLASH FUNCTIONS +#define ROM_FlashPowerModeSet \ + ((void (*)(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod)) \ + ROM_API_FLASH_TABLE[0]) + +#define ROM_FlashPowerModeGet \ + ((uint32_t (*)(void)) \ + ROM_API_FLASH_TABLE[1]) + +#define ROM_FlashProtectionSet \ + ((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \ + ROM_API_FLASH_TABLE[2]) + +#define ROM_FlashProtectionGet \ + ((uint32_t (*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[3]) + +#define ROM_FlashProtectionSave \ + ((uint32_t (*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[4]) + +#define ROM_FlashEfuseReadRow \ + ((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \ + ROM_API_FLASH_TABLE[8]) + +#define ROM_FlashDisableSectorsForWrite \ + ((void (*)(void)) \ + ROM_API_FLASH_TABLE[9]) + + +// I2C FUNCTIONS +#define ROM_I2CMasterInitExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \ + ROM_API_I2C_TABLE[0]) + +#define ROM_I2CMasterErr \ + ((uint32_t (*)(uint32_t ui32Base)) \ + ROM_API_I2C_TABLE[1]) + + +// INTERRUPT FUNCTIONS +#define ROM_IntPriorityGroupingSet \ + ((void (*)(uint32_t ui32Bits)) \ + ROM_API_INTERRUPT_TABLE[0]) + +#define ROM_IntPriorityGroupingGet \ + ((uint32_t (*)(void)) \ + ROM_API_INTERRUPT_TABLE[1]) + +#define ROM_IntPrioritySet \ + ((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \ + ROM_API_INTERRUPT_TABLE[2]) + +#define ROM_IntPriorityGet \ + ((int32_t (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[3]) + +#define ROM_IntEnable \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[4]) + +#define ROM_IntDisable \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[5]) + +#define ROM_IntPendSet \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[6]) + +#define ROM_IntPendGet \ + ((bool (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[7]) + +#define ROM_IntPendClear \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[8]) + + +// IOC FUNCTIONS +#define ROM_IOCPortConfigureSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \ + ROM_API_IOC_TABLE[0]) + +#define ROM_IOCPortConfigureGet \ + ((uint32_t (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[1]) + +#define ROM_IOCIOShutdownSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \ + ROM_API_IOC_TABLE[2]) + +#define ROM_IOCIOModeSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \ + ROM_API_IOC_TABLE[4]) + +#define ROM_IOCIOIntSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \ + ROM_API_IOC_TABLE[5]) + +#define ROM_IOCIOPortPullSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \ + ROM_API_IOC_TABLE[6]) + +#define ROM_IOCIOHystSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \ + ROM_API_IOC_TABLE[7]) + +#define ROM_IOCIOInputSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \ + ROM_API_IOC_TABLE[8]) + +#define ROM_IOCIOSlewCtrlSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \ + ROM_API_IOC_TABLE[9]) + +#define ROM_IOCIODrvStrengthSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \ + ROM_API_IOC_TABLE[10]) + +#define ROM_IOCIOPortIdSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \ + ROM_API_IOC_TABLE[11]) + +#define ROM_IOCIntEnable \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[12]) + +#define ROM_IOCIntDisable \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[13]) + +#define ROM_IOCPinTypeGpioInput \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[14]) + +#define ROM_IOCPinTypeGpioOutput \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[15]) + +#define ROM_IOCPinTypeUart \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \ + ROM_API_IOC_TABLE[16]) + +#define ROM_IOCPinTypeSsiMaster \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ + ROM_API_IOC_TABLE[17]) + +#define ROM_IOCPinTypeSsiSlave \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ + ROM_API_IOC_TABLE[18]) + +#define ROM_IOCPinTypeI2c \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \ + ROM_API_IOC_TABLE[19]) + +#define ROM_IOCPinTypeAux \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[21]) + + +// PRCM FUNCTIONS +#define ROM_PRCMInfClockConfigureSet \ + ((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \ + ROM_API_PRCM_TABLE[0]) + +#define ROM_PRCMInfClockConfigureGet \ + ((uint32_t (*)(uint32_t ui32PowerMode)) \ + ROM_API_PRCM_TABLE[1]) + +#define ROM_PRCMAudioClockConfigSet \ + ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \ + ROM_API_PRCM_TABLE[4]) + +#define ROM_PRCMPowerDomainOn \ + ((void (*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[5]) + +#define ROM_PRCMPowerDomainOff \ + ((void (*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[6]) + +#define ROM_PRCMPeripheralRunEnable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[7]) + +#define ROM_PRCMPeripheralRunDisable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[8]) + +#define ROM_PRCMPeripheralSleepEnable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[9]) + +#define ROM_PRCMPeripheralSleepDisable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[10]) + +#define ROM_PRCMPeripheralDeepSleepEnable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[11]) + +#define ROM_PRCMPeripheralDeepSleepDisable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[12]) + +#define ROM_PRCMPowerDomainStatus \ + ((uint32_t (*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[13]) + +#define ROM_PRCMDeepSleep \ + ((void (*)(void)) \ + ROM_API_PRCM_TABLE[14]) + +#define ROM_PRCMAudioClockConfigSetOverride \ + ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, uint32_t ui32BitDiv, uint32_t ui32WordDiv)) \ + ROM_API_PRCM_TABLE[17]) + + +// SMPH FUNCTIONS +#define ROM_SMPHAcquire \ + ((void (*)(uint32_t ui32Semaphore)) \ + ROM_API_SMPH_TABLE[0]) + + +// SSI FUNCTIONS +#define ROM_SSIConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \ + ROM_API_SSI_TABLE[0]) + +#define ROM_SSIDataPut \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \ + ROM_API_SSI_TABLE[1]) + +#define ROM_SSIDataPutNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \ + ROM_API_SSI_TABLE[2]) + +#define ROM_SSIDataGet \ + ((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ + ROM_API_SSI_TABLE[3]) + +#define ROM_SSIDataGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ + ROM_API_SSI_TABLE[4]) + + +// TIMER FUNCTIONS +#define ROM_TimerConfigure \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \ + ROM_API_TIMER_TABLE[0]) + +#define ROM_TimerLevelControl \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \ + ROM_API_TIMER_TABLE[1]) + +#define ROM_TimerStallControl \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \ + ROM_API_TIMER_TABLE[3]) + +#define ROM_TimerWaitOnTriggerControl \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \ + ROM_API_TIMER_TABLE[4]) + +#define ROM_TimerIntervalLoadMode \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \ + ROM_API_TIMER_TABLE[5]) + +#define ROM_TimerMatchUpdateMode \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \ + ROM_API_TIMER_TABLE[6]) + + +// TRNG FUNCTIONS +#define ROM_TRNGConfigure \ + ((void (*)(uint32_t ui32MinSamplesPerCycle, uint32_t ui32MaxSamplesPerCycle, uint32_t ui32ClocksPerSample)) \ + ROM_API_TRNG_TABLE[0]) + +#define ROM_TRNGNumberGet \ + ((uint32_t (*)(uint32_t ui32Word)) \ + ROM_API_TRNG_TABLE[1]) + + +// UART FUNCTIONS +#define ROM_UARTFIFOLevelGet \ + ((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \ + ROM_API_UART_TABLE[0]) + +#define ROM_UARTConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \ + ROM_API_UART_TABLE[1]) + +#define ROM_UARTConfigGetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \ + ROM_API_UART_TABLE[2]) + +#define ROM_UARTDisable \ + ((void (*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[3]) + +#define ROM_UARTCharGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[4]) + +#define ROM_UARTCharGet \ + ((int32_t (*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[5]) + +#define ROM_UARTCharPutNonBlocking \ + ((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \ + ROM_API_UART_TABLE[6]) + +#define ROM_UARTCharPut \ + ((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \ + ROM_API_UART_TABLE[7]) + + +// UDMA FUNCTIONS +#define ROM_uDMAChannelAttributeEnable \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ + ROM_API_UDMA_TABLE[0]) + +#define ROM_uDMAChannelAttributeDisable \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ + ROM_API_UDMA_TABLE[1]) + +#define ROM_uDMAChannelAttributeGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ + ROM_API_UDMA_TABLE[2]) + +#define ROM_uDMAChannelControlSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \ + ROM_API_UDMA_TABLE[3]) + +#define ROM_uDMAChannelTransferSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize)) \ + ROM_API_UDMA_TABLE[4]) + +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \ + ROM_API_UDMA_TABLE[5]) + +#define ROM_uDMAChannelSizeGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[6]) + +#define ROM_uDMAChannelModeGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[7]) + + +// VIMS FUNCTIONS +#define ROM_VIMSConfigure \ + ((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \ + ROM_API_VIMS_TABLE[0]) + +#define ROM_VIMSModeSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \ + ROM_API_VIMS_TABLE[1]) + +#define ROM_VIMSModeGet \ + ((uint32_t (*)(uint32_t ui32Base)) \ + ROM_API_VIMS_TABLE[2]) + +#define ROM_VIMSModeSafeSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32NewMode, bool blocking)) \ + ROM_API_VIMS_TABLE[3]) + + +// OSC FUNCTIONS +#define ROM_OSCClockSourceGet \ + ((uint32_t (*)(uint32_t ui32SrcClk)) \ + ROM_API_OSC_TABLE[0]) + +#define ROM_OSCClockSourceSet \ + ((void (*)(uint32_t ui32SrcClk, uint32_t ui32Osc)) \ + ROM_API_OSC_TABLE[1]) + +#define ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert \ + ((int16_t (*)(int32_t HPOSC_RelFreqOffset)) \ + ROM_API_OSC_TABLE[3]) + + +// AUX_ADC FUNCTIONS +#define ROM_AUXADCAdjustValueForGainAndOffset \ + ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \ + ROM_API_AUX_ADC_TABLE[0]) + +#define ROM_AUXADCDisable \ + ((void (*)(void)) \ + ROM_API_AUX_ADC_TABLE[1]) + +#define ROM_AUXADCDisableInputScaling \ + ((void (*)(void)) \ + ROM_API_AUX_ADC_TABLE[2]) + +#define ROM_AUXADCEnableAsync \ + ((void (*)(uint32_t refSource, uint32_t trigger)) \ + ROM_API_AUX_ADC_TABLE[3]) + +#define ROM_AUXADCEnableSync \ + ((void (*)(uint32_t refSource, uint32_t sampleTime, uint32_t trigger)) \ + ROM_API_AUX_ADC_TABLE[4]) + +#define ROM_AUXADCFlushFifo \ + ((void (*)(void)) \ + ROM_API_AUX_ADC_TABLE[5]) + +#define ROM_AUXADCGetAdjustmentGain \ + ((int32_t (*)(uint32_t refSource)) \ + ROM_API_AUX_ADC_TABLE[6]) + +#define ROM_AUXADCGetAdjustmentOffset \ + ((int32_t (*)(uint32_t refSource)) \ + ROM_API_AUX_ADC_TABLE[7]) + +#define ROM_AUXADCMicrovoltsToValue \ + ((int32_t (*)(int32_t fixedRefVoltage, int32_t microvolts)) \ + ROM_API_AUX_ADC_TABLE[8]) + +#define ROM_AUXADCPopFifo \ + ((uint32_t (*)(void)) \ + ROM_API_AUX_ADC_TABLE[9]) + +#define ROM_AUXADCReadFifo \ + ((uint32_t (*)(void)) \ + ROM_API_AUX_ADC_TABLE[10]) + +#define ROM_AUXADCUnadjustValueForGainAndOffset \ + ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \ + ROM_API_AUX_ADC_TABLE[11]) + +#define ROM_AUXADCValueToMicrovolts \ + ((int32_t (*)(int32_t fixedRefVoltage, int32_t adcValue)) \ + ROM_API_AUX_ADC_TABLE[12]) + + +// SYS_CTRL FUNCTIONS +#define ROM_SysCtrlResetSourceGet \ + ((uint32_t (*)(void)) \ + ROM_API_SYS_CTRL_TABLE[0]) + +#define ROM_SysCtrl_DCDC_VoltageConditionalControl \ + ((void (*)(void)) \ + ROM_API_SYS_CTRL_TABLE[1]) + + +// AON_BATMON FUNCTIONS +#define ROM_AONBatMonTemperatureGetDegC \ + ((int32_t (*)(void)) \ + ROM_API_AON_BATMON_TABLE[0]) + + +// SETUP_ROM FUNCTIONS +#define ROM_SetupAfterColdResetWakeupFromShutDownCfg1 \ + ((void (*)(uint32_t ccfg_ModeConfReg)) \ + ROM_API_SETUP_ROM_TABLE[0]) + +#define ROM_SetupAfterColdResetWakeupFromShutDownCfg2 \ + ((void (*)(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)) \ + ROM_API_SETUP_ROM_TABLE[1]) + +#define ROM_SetupAfterColdResetWakeupFromShutDownCfg3 \ + ((void (*)(uint32_t ccfg_ModeConfReg)) \ + ROM_API_SETUP_ROM_TABLE[2]) + +#define ROM_SetupGetTrimForAdcShModeEn \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[3]) + +#define ROM_SetupGetTrimForAdcShVbufEn \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[4]) + +#define ROM_SetupGetTrimForAmpcompCtrl \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[5]) + +#define ROM_SetupGetTrimForAmpcompTh1 \ + ((uint32_t (*)(void)) \ + ROM_API_SETUP_ROM_TABLE[6]) + +#define ROM_SetupGetTrimForAmpcompTh2 \ + ((uint32_t (*)(void)) \ + ROM_API_SETUP_ROM_TABLE[7]) + +#define ROM_SetupGetTrimForAnabypassValue1 \ + ((uint32_t (*)(uint32_t ccfg_ModeConfReg)) \ + ROM_API_SETUP_ROM_TABLE[8]) + +#define ROM_SetupGetTrimForDblrLoopFilterResetVoltage \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[9]) + +#define ROM_SetupGetTrimForRadcExtCfg \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[10]) + +#define ROM_SetupGetTrimForRcOscLfIBiasTrim \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[11]) + +#define ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim \ + ((uint32_t (*)(void)) \ + ROM_API_SETUP_ROM_TABLE[12]) + +#define ROM_SetupGetTrimForXoscHfCtl \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[13]) + +#define ROM_SetupGetTrimForXoscHfFastStart \ + ((uint32_t (*)(void)) \ + ROM_API_SETUP_ROM_TABLE[14]) + +#define ROM_SetupGetTrimForXoscHfIbiastherm \ + ((uint32_t (*)(void)) \ + ROM_API_SETUP_ROM_TABLE[15]) + +#define ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[16]) + +#define ROM_SetupSetAonRtcSubSecInc \ + ((void (*)(uint32_t subSecInc)) \ + ROM_API_SETUP_ROM_TABLE[17]) + +#define ROM_SetupSetCacheModeAccordingToCcfgSetting \ + ((void (*)(void)) \ + ROM_API_SETUP_ROM_TABLE[18]) + +#define ROM_SetupStepVddrTrimTo \ + ((void (*)(uint32_t toCode)) \ + ROM_API_SETUP_ROM_TABLE[19]) + + +// I2S FUNCTIONS +#define ROM_I2SPointerSet \ + ((void (*)(uint32_t ui32Base, bool bInput, void * pNextPointer)) \ + ROM_API_I2S_TABLE[0]) + +#define ROM_I2SSampleStampGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32Channel)) \ + ROM_API_I2S_TABLE[1]) + + +// PWR_CTRL FUNCTIONS +#define ROM_PowerCtrlSourceSet \ + ((void (*)(uint32_t ui32PowerConfig)) \ + ROM_API_PWR_CTRL_TABLE[0]) + + +// AES FUNCTIONS +#define ROM_AESConfigureCCMCtrl \ + ((void (*)(uint32_t nonceLength, uint32_t macLength, bool encrypt)) \ + ROM_API_AES_TABLE[0]) + +#define ROM_AESReadFromKeyStore \ + ((uint32_t (*)(uint32_t keyStoreArea)) \ + ROM_API_AES_TABLE[1]) + +#define ROM_AESReadTag \ + ((uint32_t (*)(uint8_t *tag, uint32_t tagLength)) \ + ROM_API_AES_TABLE[2]) + +#define ROM_AESSetInitializationVector \ + ((void (*)(const uint32_t *initializationVector)) \ + ROM_API_AES_TABLE[3]) + +#define ROM_AESStartDMAOperation \ + ((void (*)(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \ + ROM_API_AES_TABLE[4]) + +#define ROM_AESVerifyTag \ + ((uint32_t (*)(const uint8_t *tag, uint32_t tagLength)) \ + ROM_API_AES_TABLE[5]) + +#define ROM_AESWaitForIRQFlags \ + ((uint32_t (*)(uint32_t irqFlags)) \ + ROM_API_AES_TABLE[6]) + +#define ROM_AESWriteCCMInitializationVector \ + ((void (*)(const uint8_t *nonce, uint32_t nonceLength)) \ + ROM_API_AES_TABLE[7]) + +#define ROM_AESWriteToKeyStore \ + ((uint32_t (*)(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea)) \ + ROM_API_AES_TABLE[8]) + + +// PKA FUNCTIONS +#define ROM_PKABigNumAddGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[0]) + +#define ROM_PKABigNumCmpGetResult \ + ((uint32_t (*)(void)) \ + ROM_API_PKA_TABLE[1]) + +#define ROM_PKABigNumInvModGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[2]) + +#define ROM_PKABigNumModGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[3]) + +#define ROM_PKABigNumMultGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[4]) + +#define ROM_PKAEccAddGetResult \ + ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ + ROM_API_PKA_TABLE[5]) + +#define ROM_PKAEccAddStart \ + ((uint32_t (*)(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[6]) + +#define ROM_PKAEccMultiplyGetResult \ + ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ + ROM_API_PKA_TABLE[7]) + +#define ROM_PKAEccMultiplyStart \ + ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[8]) + +#define ROM_PKAGetOpsStatus \ + ((uint32_t (*)(void)) \ + ROM_API_PKA_TABLE[9]) + +#define ROM_PKABigNumAddStart \ + ((uint32_t (*)(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[10]) + +#define ROM_PKABigNumCmpStart \ + ((uint32_t (*)(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length)) \ + ROM_API_PKA_TABLE[11]) + +#define ROM_PKABigNumInvModStart \ + ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[12]) + +#define ROM_PKABigNumModStart \ + ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[13]) + +#define ROM_PKABigNumMultiplyStart \ + ((uint32_t (*)(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[14]) + +#define ROM_PKABigNumSubGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[15]) + +#define ROM_PKABigNumSubStart \ + ((uint32_t (*)(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[16]) + +#define ROM_PKAArrayAllZeros \ + ((bool (*)(const uint8_t *array, uint32_t arrayLength)) \ + ROM_API_PKA_TABLE[17]) + +#define ROM_PKABigNumDivideGetQuotient \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr)) \ + ROM_API_PKA_TABLE[18]) + +#define ROM_PKABigNumDivideGetRemainder \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultRemainderMemAddr)) \ + ROM_API_PKA_TABLE[19]) + +#define ROM_PKABigNumDivideStart \ + ((uint32_t (*)(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr)) \ + ROM_API_PKA_TABLE[20]) + +#define ROM_PKAEccVerifyPublicKeyWeierstrassStart \ + ((uint32_t (*)(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length)) \ + ROM_API_PKA_TABLE[21]) + +#define ROM_PKAZeroOutArray \ + ((void (*)(const uint8_t *array, uint32_t arrayLength)) \ + ROM_API_PKA_TABLE[22]) + +#define ROM_PKAEccMontgomeryMultiplyStart \ + ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[23]) + + +// SHA2 FUNCTIONS +#define ROM_SHA2ComputeFinalHash \ + ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm)) \ + ROM_API_SHA2_TABLE[0]) + +#define ROM_SHA2ComputeHash \ + ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm)) \ + ROM_API_SHA2_TABLE[1]) + +#define ROM_SHA2ComputeInitialHash \ + ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength)) \ + ROM_API_SHA2_TABLE[2]) + +#define ROM_SHA2ComputeIntermediateHash \ + ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength)) \ + ROM_API_SHA2_TABLE[3]) + +#define ROM_SHA2StartDMAOperation \ + ((void (*)(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \ + ROM_API_SHA2_TABLE[4]) + +#define ROM_SHA2WaitForIRQFlags \ + ((uint32_t (*)(uint32_t irqFlags)) \ + ROM_API_SHA2_TABLE[5]) + + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ROM_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c new file mode 100644 index 0000000..e2bf8ef --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c @@ -0,0 +1,159 @@ +/******************************************************************************* +* Filename: rom_crypto.c +* Revised: 2018-09-17 08:57:21 +0200 (Mon, 17 Sep 2018) +* Revision: 52619 +* +* Description: This is the implementation for the API to the ECC functions +* built into ROM on the CC13x2/CC26x2. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +*******************************************************************************/ + +#include +#include "rom_crypto.h" + + +////////////////////////////////////* ECC *//////////////////////////////////// +#ifdef ECC_PRIME_NIST256_CURVE +//#define TEST_NIST256 +//#define PARAM_P NIST256_p; +#define PARAM_P 0x100257d4; + +//#define PARAM_R NIST256_r; +#define PARAM_R 0x100257f8; + +//#define PARAM_A NIST256_a; +#define PARAM_A 0x1002581c; + +//#define PARAM_B NIST256_b; +#define PARAM_B 0x10025840; + +//#define PARAM_GX NIST256_Gx; +#define PARAM_GX 0x10025864; + +//#define PARAM_GY NIST256_Gy; +#define PARAM_GY 0x10025888; + +#endif + + +//***************************************************************************** +// ECC_initialize +//***************************************************************************** +void +ECC_initialize(uint32_t *pWorkzone) +{ + // Initialize curve parameters + //data_p = (uint32_t *)PARAM_P; + *((uint32_t **)0x20000138) = (uint32_t *)PARAM_P; + + //data_r = (uint32_t *)PARAM_R; + *((uint32_t **)0x2000013c) = (uint32_t *)PARAM_R; + + //data_a = (uint32_t *)PARAM_A; + *((uint32_t **)0x20000140) = (uint32_t *)PARAM_A; + + //data_b = (uint32_t *)PARAM_B; + *((uint32_t **)0x20000144) = (uint32_t *)PARAM_B; + + //data_Gx = (uint32_t *)PARAM_GX; + *((uint32_t **)0x2000012c) = (uint32_t *)PARAM_GX; + + //data_Gy = (uint32_t *)PARAM_GY; + *((uint32_t **)0x20000130) = (uint32_t *)PARAM_GY; + + // Initialize window size + //win = (uint8_t) ECC_WINDOW_SIZE; + *((uint8_t *)0x20000148) = (uint8_t) ECC_WINDOW_SIZE; + + // Initialize work zone + //workzone = (uint32_t *) pWorkzone; + *((uint32_t **)0x20000134) = (uint32_t *) pWorkzone; +} + +typedef uint8_t(*ecc_keygen_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *); +ecc_keygen_t ecc_generatekey = (ecc_keygen_t)(0x1001f94d); + +typedef uint8_t(*ecdsa_sign_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdsa_sign_t ecc_ecdsa_sign = (ecdsa_sign_t)(0x10010381); + +typedef uint8_t(*ecdsa_verify_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdsa_verify_t ecc_ecdsa_verify = (ecdsa_verify_t)(0x1000c805); + +typedef uint8_t(*ecdh_computeSharedSecret_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdh_computeSharedSecret_t ecdh_computeSharedSecret = (ecdh_computeSharedSecret_t)(0x10023485); + +//***************************************************************************** +// ECC_generateKey +//***************************************************************************** +uint8_t +ECC_generateKey(uint32_t *randString, uint32_t *privateKey, + uint32_t *publicKey_x, uint32_t *publicKey_y) +{ + return (uint8_t)ecc_generatekey((uint32_t*)randString, (uint32_t*)privateKey, + (uint32_t*)publicKey_x, (uint32_t*)publicKey_y); + +} + +//***************************************************************************** +// ECC_ECDSA_sign +//***************************************************************************** +uint8_t +ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString, + uint32_t *sign1, uint32_t *sign2) +{ + return (uint8_t)ecc_ecdsa_sign((uint32_t*)secretKey, (uint32_t*)text, (uint32_t*)randString, + (uint32_t*)sign1, (uint32_t*)sign2); +} + +//***************************************************************************** +// ECC_ECDSA_verify +//***************************************************************************** +uint8_t +ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y, + uint32_t *text, uint32_t *sign1, uint32_t *sign2) +{ + return (uint8_t)ecc_ecdsa_verify((uint32_t*)publicKey_x, (uint32_t*)publicKey_y, (uint32_t*)text, + (uint32_t*)sign1, (uint32_t*)sign2); +} + +//***************************************************************************** +// ECC_ECDH_computeSharedSecret +//***************************************************************************** +uint8_t +ECC_ECDH_computeSharedSecret(uint32_t *privateKey, uint32_t *publicKey_x, + uint32_t *publicKey_y, uint32_t *sharedSecret_x, + uint32_t *sharedSecret_y) +{ + return (uint8_t)ecdh_computeSharedSecret((uint32_t*)privateKey, (uint32_t*)publicKey_x, + (uint32_t*)publicKey_y, (uint32_t*)sharedSecret_x, + (uint32_t*)sharedSecret_y); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h new file mode 100644 index 0000000..49cd7a7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h @@ -0,0 +1,212 @@ +/****************************************************************************** +* Filename: rom_crypto.h +* Revised: 2018-09-17 09:24:56 +0200 (Mon, 17 Sep 2018) +* Revision: 52624 +* +* Description: This header file is the API to the crypto functions +* built into ROM on the CC13xx/CC26xx. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +*******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup rom_crypto_api +//! @{ +// +//***************************************************************************** + +#ifndef ROM_CRYPTO_H +#define ROM_CRYPTO_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +////////////////////////////////////* ECC *///////////////////////////////////// + +/* Window size, valid values are 2,3,4,5. + * Higher the value, faster the computation at the expense of memory usage. + * + * Recommended workzone size (in 4-byte words) + * Window size: 3, Workzone size: 275 + * + */ +#define ECC_WINDOW_SIZE 3 + +/* + * ECC Supported Curves, define one: + * ECC_PRIME_NIST256_CURVE + */ +#define ECC_PRIME_NIST256_CURVE + +/* + * ECC Return Status Flags. + */ +// Scalar multiplication status +#define ECC_MODULUS_EVEN 0xDC +#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2 +#define ECC_MODULUS_LENGTH_ZERO 0x08 +#define ECC_MODULUS_MSW_IS_ZERO 0x30 +#define ECC_SCALAR_TOO_LONG 0x35 +#define ECC_SCALAR_LENGTH_ZERO 0x53 +#define ECC_ORDER_TOO_LONG 0xC6 +#define ECC_ORDER_LENGTH_ZERO 0x6C +#define ECC_X_COORD_TOO_LONG 0x3C +#define ECC_X_COORD_LENGTH_ZERO 0xC3 +#define ECC_Y_COORD_TOO_LONG 0x65 +#define ECC_Y_COORD_LENGTH_ZERO 0x56 +#define ECC_A_COEF_TOO_LONG 0x5C +#define ECC_A_COEF_LENGTH_ZERO 0xC5 +#define ECC_BAD_WINDOW_SIZE 0x66 +#define ECC_SCALAR_MUL_OK 0x99 + +// ECDSA and ECDH status +#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28 +#define ECC_ORDER_EVEN 0x82 +#define ECC_ORDER_MSW_IS_ZERO 0x23 +#define ECC_ECC_KEY_TOO_LONG 0x25 +#define ECC_ECC_KEY_LENGTH_ZERO 0x52 +#define ECC_DIGEST_TOO_LONG 0x27 +#define ECC_DIGEST_LENGTH_ZERO 0x72 +#define ECC_ECDSA_SIGN_OK 0x32 +#define ECC_ECDSA_INVALID_SIGNATURE 0x5A +#define ECC_ECDSA_VALID_SIGNATURE 0xA5 +#define ECC_SIG_P1_TOO_LONG 0x11 +#define ECC_SIG_P1_LENGTH_ZERO 0x12 +#define ECC_SIG_P2_TOO_LONG 0x22 +#define ECC_SIG_P2_LENGTH_ZERO 0x21 + +#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK + +//***************************************************************************** +/*! + * \brief Pass pointer to ECC memory allocation to ECC engine. + * + * This function can be called again to point the ECC workzone at + * a different memory buffer. + * + * \param pWorkzone Pointer to memory allocated for computations, input. + * See description at beginning of ECC section for + * memory requirements. + * + * \return None + */ +//***************************************************************************** + extern void ECC_initialize(uint32_t *pWorkzone); + +//***************************************************************************** + /*! + * \brief Generate a key. + * + * This is used for both ECDH and ECDSA. + * + * \param randString Pointer to random string, input. + * \param privateKey Pointer to the private key, output. + * \param publicKey_x Pointer to public key X-coordinate, output. + * \param publicKey_y Pointer to public key Y-coordinate, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_generateKey(uint32_t *randString, uint32_t *privateKey, + uint32_t *publicKey_x, uint32_t *publicKey_y); + +//***************************************************************************** +/*! + * \brief Sign data. + * + * \param secretKey Pointer to the secret key, input. + * \param text Pointer to the message, input. + * \param randString Pointer to random string, input. + * \param sign1 Pointer to signature part 1, output. + * \param sign2 Pointer to signature part 2, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString, + uint32_t *sign1, uint32_t *sign2); + +//***************************************************************************** +/*! + * \brief Verify signature. + * + * \param publicKey_x Pointer to public key X-coordinate, input. + * \param publicKey_y Pointer to public key Y-coordinate, input. + * \param text Pointer to message data, input. + * \param sign1 Pointer to signature part 1, input. + * \param sign2 Pointer to signature part 2, input. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y, + uint32_t *text, uint32_t *sign1, uint32_t *sign2); + +//***************************************************************************** +/*! + * \brief Compute the shared secret. + * + * \param privateKey Pointer to private key, input. + * \param publicKey_x Pointer to public key X-coordinate, input. + * \param publicKey_y Pointer to public key Y-coordinate, input. + * \param sharedSecret_x Pointer to shared secret X-coordinate, output. + * \param sharedSecret_y Pointer to shared secret Y-coordinate, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDH_computeSharedSecret(uint32_t *privateKey, + uint32_t *publicKey_x, + uint32_t *publicKey_y, + uint32_t *sharedSecret_x, + uint32_t *sharedSecret_y); + + +#ifdef __cplusplus +} +#endif + +#endif /* ROM_CRYPTO_H */ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup.c new file mode 100644 index 0000000..f76cf83 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup.c @@ -0,0 +1,344 @@ +/****************************************************************************** +* Filename: setup.c +* Revised: 2018-11-06 15:08:57 +0100 (Tue, 06 Nov 2018) +* Revision: 53239 +* +* Description: Setup file for CC13xx/CC26xx devices. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +// Hardware headers +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_2_refsys.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_adi_4_aux.h" +// Temporarily adding these defines as they are missing in hw_adi_4_aux.h +#define ADI_4_AUX_O_LPMBIAS 0x0000000E +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M 0x0000003F +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S 0 +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M 0x00000038 +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S 3 +#include "../inc/hw_aon_ioc.h" +#include "../inc/hw_aon_pmctl.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_ddi_0_osc.h" +#include "../inc/hw_ddi.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_flash.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_vims.h" +// Driverlib headers +#include "aux_sysif.h" +#include "chipinfo.h" +#include "setup.h" +#include "setup_rom.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SetupTrimDevice + #define SetupTrimDevice NOROM_SetupTrimDevice +#endif + + + +//***************************************************************************** +// +// Defined CPU delay macro with microseconds as input +// Quick check shows: (To be further investigated) +// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 5 cycles +// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 1, there is 4 cycles +// At 24 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 3 cycles +// +//***************************************************************************** +#define CPU_DELAY_MICRO_SECONDS( x ) \ + CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 ) + + +//***************************************************************************** +// +// Function declarations +// +//***************************************************************************** +static void TrimAfterColdReset( void ); +static void TrimAfterColdResetWakeupFromShutDown( uint32_t ui32Fcfg1Revision ); +static void TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void ); + +//***************************************************************************** +// +// Perform the necessary trim of the device which is not done in boot code +// +// This function should only execute coming from ROM boot. The current +// implementation does not take soft reset into account. However, it does no +// damage to execute it again. It only consumes time. +// +//***************************************************************************** +void +SetupTrimDevice(void) +{ + uint32_t ui32Fcfg1Revision; + uint32_t ui32AonSysResetctl; + + // Get layout revision of the factory configuration area + // (Handle undefined revision as revision = 0) + ui32Fcfg1Revision = HWREG(FCFG1_BASE + FCFG1_O_FCFG1_REVISION); + if ( ui32Fcfg1Revision == 0xFFFFFFFF ) { + ui32Fcfg1Revision = 0; + } + + // This driverlib version and setup file is for the CC13x2, CC26x2 PG2.0 or later chips. + // Halt if violated + ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated(); + + // Enable standby in flash bank + HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Select correct CACHE mode and set correct CACHE configuration +#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) + SetupSetCacheModeAccordingToCcfgSetting(); +#else + NOROM_SetupSetCacheModeAccordingToCcfgSetting(); +#endif + + // 1. Check for powerdown + // 2. Check for shutdown + // 3. Assume cold reset if none of the above. + // + // It is always assumed that the application will freeze the latches in + // AON_IOC when going to powerdown in order to retain the values on the IOs. + // + // NB. If this bit is not cleared before proceeding to powerdown, the IOs + // will all default to the reset configuration when restarting. + if( ! ( HWREGBITW( AON_IOC_BASE + AON_IOC_O_IOCLATCH, AON_IOC_IOCLATCH_EN_BITN ))) + { + // NB. This should be calling a ROM implementation of required trim and + // compensation + // e.g. TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown() + TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + } + // Check for shutdown + // + // When device is going to shutdown the hardware will automatically clear + // the SLEEPDIS bit in the SLEEP register in the AON_PMCTL module. + // It is left for the application to assert this bit when waking back up, + // but not before the desired IO configuration has been re-established. + else if( ! ( HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL, AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN ))) + { + // NB. This should be calling a ROM implementation of required trim and + // compensation + // e.g. TrimAfterColdResetWakeupFromShutDown() --> + // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision); + TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + } + else + { + // Consider adding a check for soft reset to allow debugging to skip + // this section!!! + // + // NB. This should be calling a ROM implementation of required trim and + // compensation + // e.g. TrimAfterColdReset() --> + // TrimAfterColdResetWakeupFromShutDown() --> + // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown() + TrimAfterColdReset(); + TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision); + TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + + } + + // Set VIMS power domain control. + // PDCTL1VIMS = 0 ==> VIMS power domain is only powered when CPU power domain is powered + HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0; + + // Configure optimal wait time for flash FSM in cases where flash pump + // wakes up from sleep + HWREG(FLASH_BASE + FLASH_O_FPAC1) = (HWREG(FLASH_BASE + FLASH_O_FPAC1) & + ~FLASH_FPAC1_PSLEEPTDIS_M) | + (0x139<> + AON_PMCTL_RESETCTL_BOOT_DET_0_S ) == 1 ) + { + ui32AonSysResetctl = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & + ~( AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M | + AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M | AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M | AON_PMCTL_RESETCTL_MCU_WARM_RESET_M )); + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl | AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M; + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl; + } + + // Make sure there are no ongoing VIMS mode change when leaving SetupTrimDevice() + // (There should typically be no wait time here, but need to be sure) + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for an eventual ongoing mode change to complete. + } +} + +//***************************************************************************** +// +//! \brief Trims to be applied when coming from POWER_DOWN (also called when +//! coming from SHUTDOWN and PIN_RESET). +//! +//! \return None +// +//***************************************************************************** +static void +TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void ) +{ + // Currently no specific trim for Powerdown +} + +//***************************************************************************** +// +//! \brief Trims to be applied when coming from SHUTDOWN (also called when +//! coming from PIN_RESET). +//! +//! \param ui32Fcfg1Revision +//! +//! \return None +// +//***************************************************************************** +static void +TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision) +{ + uint32_t ccfg_ModeConfReg ; + + // Check in CCFG for alternative DCDC setting + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) { + // ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19] (=ALT_DCDC_DITHER_EN) + // ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) = CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) + // Using a single 4-bit masked write since layout is equal for both source and destination + HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 | + ( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S )); + + } + + // TBD - Temporarily removed for CC13x2 / CC26x2 + + // Force DCDC to use RCOSC before starting up XOSC. + // Clock loss detector does not use XOSC until SCLK_HF actually switches + // and thus DCDC is not protected from clock loss on XOSC in that time frame. + // The force must be released when the switch to XOSC has happened. This is done + // in OSCHfSourceSwitch(). + HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16); + // Dummy read to ensure that the write has propagated + HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); + + // read the MODE_CONF register in CCFG + ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + + // First part of trim done after cold reset and wakeup from shutdown: + // -Adjust the VDDR_TRIM_SLEEP value. + // -Configure DCDC. + SetupAfterColdResetWakeupFromShutDownCfg1( ccfg_ModeConfReg ); + + // Addition to the CC1352 boost mode for HWREV >= 2.0 + // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode + if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) && + (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) ) + { + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL3 ) = ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST ; + } + + // Second part of trim done after cold reset and wakeup from shutdown: + // -Configure XOSC. +#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) + SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg ); +#else + NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg ); +#endif + + { + uint32_t trimReg ; + uint32_t ui32TrimValue ; + + //--- Propagate the LPM_BIAS trim --- + trimReg = HWREG( FCFG1_BASE + FCFG1_O_DAC_BIAS_CNF ); + ui32TrimValue = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M ) >> + FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S ) ; + HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_LPMBIAS ) = (( ui32TrimValue << ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S ) & + ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M ) ; + // Set LPM_BIAS_BACKUP_EN according to FCFG1 configuration + if ( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN ) { + HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN; + } else { + HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN; + } + // Set LPM_BIAS_WIDTH_TRIM according to FCFG1 configuration + { + uint32_t widthTrim = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M ) >> FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S ); + HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_COMP * 2 )) = // Set LPM_BIAS_WIDTH_TRIM = 3 + (( ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M << 8 ) | // Set mask (bits to be written) in [15:8] + ( widthTrim << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S ) ); // Set value (in correct bit pos) in [7:0] + } + } + + // Third part of trim done after cold reset and wakeup from shutdown: + // -Configure HPOSC. + // -Setup the LF clock. +#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) + SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg ); +#else + NOROM_SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg ); +#endif + + // Set AUX into power down active mode + AUXSYSIFOpModeChange( AUX_SYSIF_OPMODE_TARGET_PDA ); + + // Disable EFUSE clock + HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1; +} + + +//***************************************************************************** +// +//! \brief Trims to be applied when coming from PIN_RESET. +//! +//! \return None +// +//***************************************************************************** +static void +TrimAfterColdReset( void ) +{ + // Currently no specific trim for Cold Reset +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup.h new file mode 100644 index 0000000..496b17a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup.h @@ -0,0 +1,141 @@ +/****************************************************************************** +* Filename: setup.h +* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) +* Revision: 52993 +* +* Description: Prototypes and defines for the setup API. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup setup_api +//! @{ +// +//***************************************************************************** + +#ifndef __SETUP_H__ +#define __SETUP_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +// Hardware headers +#include "../inc/hw_types.h" +// Driverlib headers +// - None needed + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SetupTrimDevice NOROM_SetupTrimDevice +#endif + +//***************************************************************************** +// +//! \brief Performs the necessary trim of the device which is not done in ROM boot code. +//! +//! This function should only execute coming from ROM boot. +//! +//! The following is handled by this function: +//! - Checks if the driverlib variant used by the application is supported by the +//! device. Execution is halted in case of unsupported driverlib variant. +//! - Configures VIMS cache mode based on setting in CCFG. +//! - Configures functionalities like DCDC and XOSC dependent on startup modes like +//! cold reset, wakeup from shutdown and wakeup from from powerdown. +//! - Configures VIMS power domain control. +//! - Configures optimal wait time for flash FSM in cases where flash pump wakes up from sleep. +//! +//! \note The current implementation does not take soft reset into account. However, +//! it does no damage to execute it again. It only consumes time. +//! +//! \note This function is called by the compiler specific device startup codes +//! that are integrated in the SimpleLink SDKs for CC13xx/CC26XX devices. +//! +//! \return None +// +//***************************************************************************** +extern void SetupTrimDevice( void ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SetupTrimDevice + #undef SetupTrimDevice + #define SetupTrimDevice ROM_SetupTrimDevice + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SETUP_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_doc.h new file mode 100644 index 0000000..07ab97e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_doc.h @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: setup_doc.h +* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) +* Revision: 49096 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup setup_api +//! @{ +//! +//! This module contains functions for device setup which is not done in boot code. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.c new file mode 100644 index 0000000..64acd16 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.c @@ -0,0 +1,943 @@ +/****************************************************************************** +* Filename: setup_rom.c +* Revised: 2017-11-02 11:31:15 +0100 (Thu, 02 Nov 2017) +* Revision: 50143 +* +* Description: Setup file for CC13xx/CC26xx devices. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +// Hardware headers +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_2_refsys.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_adi_4_aux.h" +#include "../inc/hw_aon_batmon.h" +#include "../inc/hw_aux_sysif.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ddi_0_osc.h" +#include "../inc/hw_fcfg1.h" +// Driverlib headers +#include "ddi.h" +#include "ioc.h" +#include "osc.h" +#include "sys_ctrl.h" +#include "setup_rom.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SetupAfterColdResetWakeupFromShutDownCfg1 + #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #undef SetupAfterColdResetWakeupFromShutDownCfg2 + #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #undef SetupAfterColdResetWakeupFromShutDownCfg3 + #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #undef SetupGetTrimForAdcShModeEn + #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn + #undef SetupGetTrimForAdcShVbufEn + #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn + #undef SetupGetTrimForAmpcompCtrl + #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl + #undef SetupGetTrimForAmpcompTh1 + #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 + #undef SetupGetTrimForAmpcompTh2 + #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 + #undef SetupGetTrimForAnabypassValue1 + #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 + #undef SetupGetTrimForDblrLoopFilterResetVoltage + #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage + #undef SetupGetTrimForRadcExtCfg + #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg + #undef SetupGetTrimForRcOscLfIBiasTrim + #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim + #undef SetupGetTrimForRcOscLfRtuneCtuneTrim + #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #undef SetupGetTrimForXoscHfCtl + #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl + #undef SetupGetTrimForXoscHfFastStart + #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart + #undef SetupGetTrimForXoscHfIbiastherm + #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm + #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #undef SetupSetCacheModeAccordingToCcfgSetting + #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting + #undef SetupSetAonRtcSubSecInc + #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc + #undef SetupStepVddrTrimTo + #define SetupStepVddrTrimTo NOROM_SetupStepVddrTrimTo +#endif + +//***************************************************************************** +// +// Function declarations +// +//***************************************************************************** + +//***************************************************************************** +// +// SetupStepVddrTrimTo +// +//***************************************************************************** +void +SetupStepVddrTrimTo( uint32_t toCode ) +{ + uint32_t pmctlResetctl_reg ; + int32_t targetTrim ; + int32_t currentTrim ; + + targetTrim = SetupSignExtendVddrTrimValue( toCode & ( ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M >> ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S )); + currentTrim = SetupSignExtendVddrTrimValue(( + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) >> + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) ; + + if ( targetTrim != currentTrim ) { + pmctlResetctl_reg = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M ); + if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) { + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ( pmctlResetctl_reg & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ); + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for VDDR_LOSS_EN setting to propagate + } + + while ( targetTrim != currentTrim ) { + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + + if ( targetTrim > currentTrim ) currentTrim++; + else currentTrim--; + + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) = ( + ( HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & ~ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) | + ((((uint32_t)currentTrim) << ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) & + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) ); + } + + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + + if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) { + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = pmctlResetctl_reg; + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // And finally wait for VDDR_LOSS_EN setting to propagate + } + } +} + +//***************************************************************************** +// +// SetupAfterColdResetWakeupFromShutDownCfg1 +// +//***************************************************************************** +void +SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ) +{ + // Check for CC1352 boost mode + // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode + if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) && + (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) ) + { + // Set VDDS_BOD trim - using masked write {MASK8:DATA8} + // - TRIM_VDDS_BOD is bits[7:3] of ADI3..REFSYSCTL1 + // - Needs a positive transition on BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to + // latch new VDDS BOD. Set to 0 first to guarantee a positive transition. + HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; + // + // VDDS_BOD_LEVEL = 1 means that boost mode is selected + // - Max out the VDDS_BOD trim (=VDDS_BOD_POS_31) + HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) = + ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8 ) | + ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 ) ; + HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; + + SetupStepVddrTrimTo(( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) & + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >> + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ; + } + + // 1. + // Do not allow DCDC to be enabled if in external regulator mode. + // Preventing this by setting both the RECHARGE and the ACTIVE bits bit in the CCFG_MODE_CONF copy register (ccfg_ModeConfReg). + // + // 2. + // Adjusted battery monitor low limit in internal regulator mode. + // This is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode. + if ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) { + ccfg_ModeConfReg |= ( CCFG_MODE_CONF_DCDC_RECHARGE_M | CCFG_MODE_CONF_DCDC_ACTIVE_M ); + } else { + HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0; + } + + // set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE + // Note: Inverse polarity + HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_EN_BITN ) = + ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_RECHARGE_S ) & 1 ) ^ 1 ); + + // set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE + // Note: Inverse polarity + HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN ) = + ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_ACTIVE_S ) & 1 ) ^ 1 ); +} + +//***************************************************************************** +// +// SetupAfterColdResetWakeupFromShutDownCfg2 +// +//***************************************************************************** +void +SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ) +{ + uint32_t ui32Trim; + + // Following sequence is required for using XOSCHF, if not included + // devices crashes when trying to switch to XOSCHF. + // + // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1 + // register + ui32Trim = SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg ); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim); + + // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and + // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register. + ui32Trim = SetupGetTrimForRcOscLfRtuneCtuneTrim(); + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL, + (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M | + DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M), + DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S, + ui32Trim); + + // Trim XOSCHF IBIAS THERM. Get and set trim value for the + // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other + // register bit fields are set to 0. + ui32Trim = SetupGetTrimForXoscHfIbiastherm(); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2, + ui32Trim< writing to bits[7:4] + ui32Trim = SetupGetTrimForAdcShModeEn( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = + ( 0x20 | ( ui32Trim << 1 )); + + // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance to FCFG1 setting + // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register + // Using MASK4 write + 1 => writing to bits[7:4] + ui32Trim = SetupGetTrimForAdcShVbufEn( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = + ( 0x10 | ( ui32Trim )); + + // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields + // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting. + // Remaining register bit fields are set to their reset values of 0. + ui32Trim = SetupGetTrimForXoscHfCtl(ui32Fcfg1Revision); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim); + + // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting + // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL) + // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4)) + // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and + // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000) + ui32Trim = SetupGetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) = + ( 0x60 | ( ui32Trim << 1 )); + + // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from + // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM + // This is DDI_0_OSC_O_ATESTCTL bit[7] + // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020)) + // Using MASK4 write + 1 => writing to bits[7:4] + ui32Trim = SetupGetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) = + ( 0x80 | ( ui32Trim << 3 )); + + // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and + // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write + // This can be simplified since the registers are packed together in the same + // order both in FCFG1 and in the HW register. + // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18] + // Using MASK8 write + 4 => writing to bits[23:16] + ui32Trim = SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision ); + HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) = + ( 0xFC00 | ( ui32Trim << 2 )); + + // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit + // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting. + // Remaining register bit fields are set to their reset values of 0. + ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim); + +} + +//***************************************************************************** +// +// SetupAfterColdResetWakeupFromShutDownCfg3 +// +//***************************************************************************** +void +SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) +{ + uint32_t fcfg1OscConf; + uint32_t ui32Trim; + uint32_t currentHfClock; + uint32_t ccfgExtLfClk; + + // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC + switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) { + case 2 : + // XOSC source is a 48 MHz crystal + // Do nothing (since this is the reset setting) + break; + case 1 : + // XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, otherwise skip trimming and default to 24 MHz XOSC) + + fcfg1OscConf = HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ); + + if (( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION ) == 0 ) { + // This is a HPOSC chip, apply HPOSC settings + // Set bit DDI_0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_HPOSC_MODE_EN; + + // ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit) + // ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits) + // ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET = FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits) + // ADI_2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN (1 bit) + // ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits) + // ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP = FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits) + // ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS = FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit) + + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) & + ~( ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M | ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M ) ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S ) << ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M ) >> FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S ) << ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S ) ); + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) & ~( ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M ) ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S ) << ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S ) ); + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) & + ~( ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M | ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M | ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M | ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M )) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_FILTER_EN_M ) >> FCFG1_OSC_CONF_HPOSC_FILTER_EN_S ) << ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S ) << ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M ) >> FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S ) << ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M ) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S ) << ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S ) ); + break; + } + // Not a HPOSC chip - fall through to default + default : + // XOSC source is a 24 MHz crystal (default) + // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M; + break; + } + + // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO + // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used. + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) { + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS; + } + + // Clear DDI_0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 in DDI_0_OSC_O_CTL0. + // This is typically already 0 except on Lizard where it is set in ROM-boot + HWREG( AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN; + + // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1 + ui32Trim = SetupGetTrimForXoscHfFastStart(); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim ); + + // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION + switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) { + case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz) + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF ); + SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency + break; + case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT) + // Set SCLK_LF to use the same source as SCLK_HF + // Can be simplified a bit since possible return values for HF matches LF settings + currentHfClock = OSCClockSourceGet( OSC_SRC_CLK_HF ); + OSCClockSourceSet( OSC_SRC_CLK_LF, currentHfClock ); + while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != currentHfClock ) { + // Wait until switched + } + ccfgExtLfClk = HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ); + SetupSetAonRtcSubSecInc(( ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) >> CCFG_EXT_LF_CLK_RTC_INCREMENT_S ); + IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S, + IOC_PORT_AON_CLK32K, + IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis + // Set XOSC_LF in bypass mode to allow external 32 kHz clock + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS; + // Fall through to set XOSC_LF as SCLK_LF source + case 2 : // XOSC_LF -> SLCK_LF (32768 Hz) + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF ); + break; + default : // (=3) RCOSC_LF + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF ); + break; + } + + // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1 + HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) = + ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >> + FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) << + ADI_4_AUX_ADCREF1_VTRIM_S ) & + ADI_4_AUX_ADCREF1_VTRIM_M ); + + // Sync with AON + SysCtrlAonSync(); +} + +//***************************************************************************** +// +// SetupGetTrimForAnabypassValue1 +// +//***************************************************************************** +uint32_t +SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ) +{ + uint32_t ui32Fcfg1Value ; + uint32_t ui32XoscHfRow ; + uint32_t ui32XoscHfCol ; + uint32_t ui32TrimValue ; + + // Use device specific trim values located in factory configuration + // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in + // the ANABYPASS_VALUE1 register. Value for the other bit fields + // are set to 0. + + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP); + ui32XoscHfRow = (( ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S ); + ui32XoscHfCol = (( ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S ); + + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) { + // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation + // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg + // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by + // a define and sign extension must therefore be hard coded. + // ( A small test program is created verifying the code lines below: + // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c) + int32_t i32CustomerDeltaAdjust = + (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ))) + >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W )); + + while ( i32CustomerDeltaAdjust < 0 ) { + ui32XoscHfCol >>= 1; // COL 1 step down + if ( ui32XoscHfCol == 0 ) { // if COL below minimum + ui32XoscHfCol = 0xFFFF; // Set COL to maximum + ui32XoscHfRow >>= 1; // ROW 1 step down + if ( ui32XoscHfRow == 0 ) { // if ROW below minimum + ui32XoscHfRow = 1; // Set both ROW and COL + ui32XoscHfCol = 1; // to minimum + } + } + i32CustomerDeltaAdjust++; + } + while ( i32CustomerDeltaAdjust > 0 ) { + ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up + if ( ui32XoscHfCol > 0xFFFF ) { // if COL above maximum + ui32XoscHfCol = 1; // Set COL to minimum + ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up + if ( ui32XoscHfRow > 0xF ) { // if ROW above maximum + ui32XoscHfRow = 0xF; // Set both ROW and COL + ui32XoscHfCol = 0xFFFF; // to maximum + } + } + i32CustomerDeltaAdjust--; + } + } + + ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) | + ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) ); + + return (ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForRcOscLfRtuneCtuneTrim +// +//***************************************************************************** +uint32_t +SetupGetTrimForRcOscLfRtuneCtuneTrim( void ) +{ + uint32_t ui32TrimValue; + + // Use device specific trim values located in factory configuration + // area + ui32TrimValue = + ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<< + DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S; + + ui32TrimValue |= + ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<< + DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S; + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscHfIbiastherm +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscHfIbiastherm( void ) +{ + uint32_t ui32TrimValue; + + // Use device specific trim value located in factory configuration + // area + ui32TrimValue = + (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) & + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>> + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S; + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForAmpcompTh2 +// +//***************************************************************************** +uint32_t +SetupGetTrimForAmpcompTh2( void ) +{ + uint32_t ui32TrimValue; + uint32_t ui32Fcfg1Value; + + // Use device specific trim value located in factory configuration + // area. All defined register bit fields have corresponding trim + // value in the factory configuration area + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2); + ui32TrimValue = ((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>> + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<< + DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S; + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>> + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<< + DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<< + DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<< + DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S); + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForAmpcompTh1 +// +//***************************************************************************** +uint32_t +SetupGetTrimForAmpcompTh1( void ) +{ + uint32_t ui32TrimValue; + uint32_t ui32Fcfg1Value; + + // Use device specific trim values located in factory configuration + // area. All defined register bit fields have a corresponding trim + // value in the factory configuration area + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1); + ui32TrimValue = (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>> + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<< + DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S); + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForAmpcompCtrl +// +//***************************************************************************** +uint32_t +SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ) +{ + uint32_t ui32TrimValue ; + uint32_t ui32Fcfg1Value ; + uint32_t ibiasOffset ; + uint32_t ibiasInit ; + uint32_t modeConf1 ; + int32_t deltaAdjust ; + + // Use device specific trim values located in factory configuration + // area. Register bit fields without trim values in the factory + // configuration area will be set to the value of 0. + ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 ); + + ibiasOffset = ( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ; + ibiasInit = ( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ; + + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) { + // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG + modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ); + + // Both fields are signed 4-bit values. This is an assumption when doing the sign extension. + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W )); + deltaAdjust += (int32_t)ibiasOffset; + if ( deltaAdjust < 0 ) { + deltaAdjust = 0; + } + if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) { + deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ); + } + ibiasOffset = (uint32_t)deltaAdjust; + + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W )); + deltaAdjust += (int32_t)ibiasInit; + if ( deltaAdjust < 0 ) { + deltaAdjust = 0; + } + if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) { + deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ); + } + ibiasInit = (uint32_t)deltaAdjust; + } + ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) | + ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ; + + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>> + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<< + DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>> + FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<< + DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>> + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<< + DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S); + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + ui32TrimValue |= ((( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >> + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) << + DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S ); + } + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForDblrLoopFilterResetVoltage +// +//***************************************************************************** +uint32_t +SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ) +{ + uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) & + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >> + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S; + } + + return ( dblrLoopFilterResetVoltageValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForAdcShModeEn +// +//***************************************************************************** +uint32_t +SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForAdcShModeEnValue = 1; // Recommended default setting + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >> + FCFG1_OSC_CONF_ADC_SH_MODE_EN_S; + } + + return ( getTrimForAdcShModeEnValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForAdcShVbufEn +// +//***************************************************************************** +uint32_t +SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForAdcShVbufEnValue = 1; // Recommended default setting + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >> + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S; + } + + return ( getTrimForAdcShVbufEnValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscHfCtl +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForXoschfCtlValue = 0; // Recommended default setting + uint32_t fcfg1Data; + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); + getTrimForXoschfCtlValue = + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S); + + getTrimForXoschfCtlValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S); + + getTrimForXoschfCtlValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S); + } + + return ( getTrimForXoschfCtlValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscHfFastStart +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscHfFastStart( void ) +{ + uint32_t ui32XoscHfFastStartValue ; + + // Get value from FCFG1 + ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >> + FCFG1_OSC_CONF_XOSC_HF_FAST_START_S; + + return ( ui32XoscHfFastStartValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForRadcExtCfg +// +//***************************************************************************** +uint32_t +SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommended default setting + uint32_t fcfg1Data; + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); + getTrimForRadcExtCfgValue = + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >> + FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) << + DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S); + + getTrimForRadcExtCfgValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >> + FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) << + DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S); + + getTrimForRadcExtCfgValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >> + FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) << + DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S); + } + + return ( getTrimForRadcExtCfgValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForRcOscLfIBiasTrim +// +//***************************************************************************** +uint32_t +SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ) +{ + uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >> + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ; + } + + return ( trimForRcOscLfIBiasTrimValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ) +{ + uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M | + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >> + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ; + } + + return ( trimForXoscLfRegulatorAndCmirrwrRatioValue ); +} + +//***************************************************************************** +// +// SetupSetCacheModeAccordingToCcfgSetting +// +//***************************************************************************** +void +SetupSetCacheModeAccordingToCcfgSetting( void ) +{ + // - Make sure to enable aggressive VIMS clock gating for power optimization + // Only for PG2 devices. + // - Enable cache prefetch enable as default setting + // (Slightly higher power consumption, but higher CPU performance) + // - IF ( CCFG_..._DIS_GPRAM == 1 ) + // then: Enable cache (set cache mode = 1), even if set by ROM boot code + // (This is done because it's not set by boot code when running inside + // a debugger supporting the Halt In Boot (HIB) functionality). + // else: Set MODE_GPRAM if not already set (see inline comments as well) + uint32_t vimsCtlMode0 ; + + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for an eventual ongoing mode change to complete. + // (There should typically be no wait time here, but need to be sure) + } + + // Note that Mode=0 is equal to MODE_GPRAM + vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M ); + + + if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) { + // Enable cache (and hence disable GPRAM) + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE ); + } else if (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_GPRAM ) { + // GPRAM is enabled in CCFG but not selected + // Note: It is recommended to go via MODE_OFF when switching to MODE_GPRAM + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_OFF ); + while (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_OFF ) { + // Do nothing - wait for an eventual mode change to complete (This goes fast). + } + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + } else { + // Correct mode, but make sure PREF_EN and DYN_CG_EN always are set + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + } +} + +//***************************************************************************** +// +// SetupSetAonRtcSubSecInc +// +//***************************************************************************** +void +SetupSetAonRtcSubSecInc( uint32_t subSecInc ) +{ + // Loading a new RTCSUBSECINC value is done in 5 steps: + // 1. Write bit[15:0] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC0 + // 2. Write bit[23:16] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC1 + // 3. Set AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ + // 4. Wait for AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK + // 5. Clear AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC0 ) = (( subSecInc ) & AUX_SYSIF_RTCSUBSECINC0_INC15_0_M ); + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_SYSIF_RTCSUBSECINC1_INC23_16_M ); + + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ; + while( ! ( HWREGBITW( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL, AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN ))); + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = 0; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h new file mode 100644 index 0000000..2dd25cd --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h @@ -0,0 +1,469 @@ +/****************************************************************************** +* Filename: setup_rom.h +* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) +* Revision: 52993 +* +* Description: Prototypes and defines for the setup API. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup setup_rom_api +//! @{ +// +//***************************************************************************** + +#ifndef __SETUP_ROM_H__ +#define __SETUP_ROM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +// Hardware headers +#include "../inc/hw_types.h" +// Driverlib headers +// - None needed + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn + #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn + #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl + #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 + #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 + #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 + #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage + #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg + #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim + #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl + #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart + #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm + #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting + #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc + #define SetupStepVddrTrimTo NOROM_SetupStepVddrTrimTo +#endif + +//***************************************************************************** +// +//! \brief First part of configuration required after cold reset and when waking up from shutdown. +//! +//! Configures the following based on settings in CCFG (Customer Configuration area: +//! - Boost mode for CC13xx devices +//! - Minimal VDDR voltage threshold used during sleep mode +//! - DCDC functionality: +//! - Selects if DCDC or GLDO regulator will be used for VDDR in active mode +//! - Selects if DCDC or GLDO regulator will be used for VDDR in sleep mode +//! +//! In addition the battery monitor low limit for internal regulator mode is set +//! to a hard coded value. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return None +// +//***************************************************************************** +extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Second part of configuration required after cold reset and when waking up from shutdown. +//! +//! Configures and trims functionalites required for use of XOSC_HF. +//! The configurations and trimmings are based on settings in FCFG1 (Factory +//! Configuration area) and partly on \c ccfg_ModeConfReg. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return None +// +//***************************************************************************** +extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Third part of configuration required after cold reset and when waking up from shutdown. +//! +//! Configures the following: +//! - XOSC source selection based on \c ccfg_ModeConfReg. If HPOSC is selected on a +//! HPOSC device the oscillator is configured based on settings in FCFG1 (Factory +//! Configuration area). +//! - Clock loss detection is disabled. Will be re-enabled by TIRTOS power driver. +//! - Duration of the XOSC_HF fast startup mode based on FCFG1 setting. +//! - SCLK_LF based on \c ccfg_ModeConfReg. +//! - Output voltage of ADC fixed reference based on FCFG1 setting. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return None +// +//***************************************************************************** +extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAmpcompTh1( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAmpcompTh2( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the +//! RCOSCLF_CTUNE_TRIM bit fields in the XOSCLF_RCOSCLF_CTRL register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscHfFastStart( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in +//! the ANABYPASS_VALUE2 register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscHfIbiastherm( void ); + +//***************************************************************************** +// +//! \brief Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet +//! spanning bits [5:0] in the returned value. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) +//! +//! \param ui32VddrTrimVal +//! +//! \return Returns Sign extended VDDR_TRIM setting. +// +//***************************************************************************** +__STATIC_INLINE int32_t +SetupSignExtendVddrTrimValue( uint32_t ui32VddrTrimVal ) +{ + // The VDDR trim value is 5 bits representing the range from -10 to +21 + // (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15) + int32_t i32SignedVddrVal = ui32VddrTrimVal; + if ( i32SignedVddrVal > 0x15 ) { + i32SignedVddrVal -= 0x20; + } + return ( i32SignedVddrVal ); +} + +//***************************************************************************** +// +//! \brief Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM) +//! +//! \return None +// +//***************************************************************************** +extern void SetupSetCacheModeAccordingToCcfgSetting( void ); + +//***************************************************************************** +// +//! \brief Doing the tricky stuff needed to enter new RTCSUBSECINC value +//! +//! \param subSecInc +//! +//! \return None +// +//***************************************************************************** +extern void SetupSetAonRtcSubSecInc( uint32_t subSecInc ); + +//***************************************************************************** +// +//! \brief Set VDDR boost mode (by setting VDDR_TRIM to FCFG1..VDDR_TRIM_HH and +//! setting VDDS_BOD to max) +//! +//! \param toCode specifies the target VDDR trim value. +//! The input parameter \c toCode can be either the signed extended +//! trim value or holding the trim code bits only. +//! +//! \return None +// +//***************************************************************************** +extern void SetupStepVddrTrimTo( uint32_t toCode ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #undef SetupAfterColdResetWakeupFromShutDownCfg1 + #define SetupAfterColdResetWakeupFromShutDownCfg1 ROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #endif + #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #undef SetupAfterColdResetWakeupFromShutDownCfg2 + #define SetupAfterColdResetWakeupFromShutDownCfg2 ROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #endif + #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #undef SetupAfterColdResetWakeupFromShutDownCfg3 + #define SetupAfterColdResetWakeupFromShutDownCfg3 ROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #endif + #ifdef ROM_SetupGetTrimForAdcShModeEn + #undef SetupGetTrimForAdcShModeEn + #define SetupGetTrimForAdcShModeEn ROM_SetupGetTrimForAdcShModeEn + #endif + #ifdef ROM_SetupGetTrimForAdcShVbufEn + #undef SetupGetTrimForAdcShVbufEn + #define SetupGetTrimForAdcShVbufEn ROM_SetupGetTrimForAdcShVbufEn + #endif + #ifdef ROM_SetupGetTrimForAmpcompCtrl + #undef SetupGetTrimForAmpcompCtrl + #define SetupGetTrimForAmpcompCtrl ROM_SetupGetTrimForAmpcompCtrl + #endif + #ifdef ROM_SetupGetTrimForAmpcompTh1 + #undef SetupGetTrimForAmpcompTh1 + #define SetupGetTrimForAmpcompTh1 ROM_SetupGetTrimForAmpcompTh1 + #endif + #ifdef ROM_SetupGetTrimForAmpcompTh2 + #undef SetupGetTrimForAmpcompTh2 + #define SetupGetTrimForAmpcompTh2 ROM_SetupGetTrimForAmpcompTh2 + #endif + #ifdef ROM_SetupGetTrimForAnabypassValue1 + #undef SetupGetTrimForAnabypassValue1 + #define SetupGetTrimForAnabypassValue1 ROM_SetupGetTrimForAnabypassValue1 + #endif + #ifdef ROM_SetupGetTrimForDblrLoopFilterResetVoltage + #undef SetupGetTrimForDblrLoopFilterResetVoltage + #define SetupGetTrimForDblrLoopFilterResetVoltage ROM_SetupGetTrimForDblrLoopFilterResetVoltage + #endif + #ifdef ROM_SetupGetTrimForRadcExtCfg + #undef SetupGetTrimForRadcExtCfg + #define SetupGetTrimForRadcExtCfg ROM_SetupGetTrimForRadcExtCfg + #endif + #ifdef ROM_SetupGetTrimForRcOscLfIBiasTrim + #undef SetupGetTrimForRcOscLfIBiasTrim + #define SetupGetTrimForRcOscLfIBiasTrim ROM_SetupGetTrimForRcOscLfIBiasTrim + #endif + #ifdef ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #undef SetupGetTrimForRcOscLfRtuneCtuneTrim + #define SetupGetTrimForRcOscLfRtuneCtuneTrim ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #endif + #ifdef ROM_SetupGetTrimForXoscHfCtl + #undef SetupGetTrimForXoscHfCtl + #define SetupGetTrimForXoscHfCtl ROM_SetupGetTrimForXoscHfCtl + #endif + #ifdef ROM_SetupGetTrimForXoscHfFastStart + #undef SetupGetTrimForXoscHfFastStart + #define SetupGetTrimForXoscHfFastStart ROM_SetupGetTrimForXoscHfFastStart + #endif + #ifdef ROM_SetupGetTrimForXoscHfIbiastherm + #undef SetupGetTrimForXoscHfIbiastherm + #define SetupGetTrimForXoscHfIbiastherm ROM_SetupGetTrimForXoscHfIbiastherm + #endif + #ifdef ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #endif + #ifdef ROM_SetupSetCacheModeAccordingToCcfgSetting + #undef SetupSetCacheModeAccordingToCcfgSetting + #define SetupSetCacheModeAccordingToCcfgSetting ROM_SetupSetCacheModeAccordingToCcfgSetting + #endif + #ifdef ROM_SetupSetAonRtcSubSecInc + #undef SetupSetAonRtcSubSecInc + #define SetupSetAonRtcSubSecInc ROM_SetupSetAonRtcSubSecInc + #endif + #ifdef ROM_SetupStepVddrTrimTo + #undef SetupStepVddrTrimTo + #define SetupStepVddrTrimTo ROM_SetupStepVddrTrimTo + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SETUP_ROM_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom_doc.h new file mode 100644 index 0000000..bafcf07 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom_doc.h @@ -0,0 +1,44 @@ +/****************************************************************************** +* Filename: setup_rom_doc.h +* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) +* Revision: 49096 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup setup_rom_api +//! @{ +//! +//! This module contains functions from the Setup API which are likely to be in ROM. +//! +//! \note Do not use functions from this module directly! This module is only to be used by +//! SetupTrimDevice(). +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.c new file mode 100644 index 0000000..f5b4757 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.c @@ -0,0 +1,272 @@ +/****************************************************************************** +* Filename: sha2.c +* Revised: 2018-04-17 15:57:27 +0200 (Tue, 17 Apr 2018) +* Revision: 51892 +* +* Description: Driver for the SHA-2 functions of the crypto module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "sha2.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SHA2StartDMAOperation + #define SHA2StartDMAOperation NOROM_SHA2StartDMAOperation + #undef SHA2WaitForIRQFlags + #define SHA2WaitForIRQFlags NOROM_SHA2WaitForIRQFlags + #undef SHA2ComputeInitialHash + #define SHA2ComputeInitialHash NOROM_SHA2ComputeInitialHash + #undef SHA2ComputeIntermediateHash + #define SHA2ComputeIntermediateHash NOROM_SHA2ComputeIntermediateHash + #undef SHA2ComputeFinalHash + #define SHA2ComputeFinalHash NOROM_SHA2ComputeFinalHash + #undef SHA2ComputeHash + #define SHA2ComputeHash NOROM_SHA2ComputeHash +#endif + + +static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash); + + +//***************************************************************************** +// +// Start a SHA-2 DMA operation. +// +//***************************************************************************** +void SHA2StartDMAOperation(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) +{ + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + if (channel0Addr) { + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; + } + + if (channel1Addr) { + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; + } +} + +//***************************************************************************** +// +// Poll the IRQ status register and return. +// +//***************************************************************************** +uint32_t SHA2WaitForIRQFlags(uint32_t irqFlags) +{ + uint32_t irqTrigger = 0; + // Wait for the DMA operation to complete. Add a delay to make sure we are + // not flooding the bus with requests too much. + do { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M))); + + // Save the IRQ trigger source + irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT); + + // Clear IRQ flags + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqFlags; + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + return irqTrigger; +} + +//***************************************************************************** +// +// Start a new SHA-2 hash operation. +// +//***************************************************************************** +uint32_t SHA2ComputeInitialHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength) +{ + ASSERT(message); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + + return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, initialMessageLength, initialMessageLength, hashAlgorithm, true, false); +} + +//***************************************************************************** +// +// Start an intermediate SHA-2 hash operation. +// +//***************************************************************************** +uint32_t SHA2ComputeIntermediateHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength) +{ + ASSERT(message); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, 0, intermediateMessageLength, hashAlgorithm, false, false); +} + +//***************************************************************************** +// +// Start an intermediate SHA-2 hash operation and finalize it. +// +//***************************************************************************** +uint32_t SHA2ComputeFinalHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm) +{ + ASSERT(message); + ASSERT(totalMsgLength); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + ASSERT(resultDigest); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, resultDigest, intermediateDigest, totalMsgLength, messageLength, hashAlgorithm, false, true); +} + +//***************************************************************************** +// +// Start and finalize a new SHA-2 hash operation. +// +//***************************************************************************** +uint32_t SHA2ComputeHash(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm) +{ + ASSERT(message); + ASSERT(totalMsgLength); + ASSERT(resultDigest); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, resultDigest, 0, totalMsgLength, totalMsgLength, hashAlgorithm, true, true); +} + +//***************************************************************************** +// +// Start any SHA-2 hash operation. +// +//***************************************************************************** +static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash) +{ + uint8_t digestLength = 0; + uint32_t dmaAlgorithmSelect = 0; + + SHA2ClearDigestAvailableFlag(); + + switch (hashAlgorithm) { + case SHA2_MODE_SELECT_SHA224: + digestLength = SHA2_SHA224_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA256; + break; + case SHA2_MODE_SELECT_SHA256: + digestLength = SHA2_SHA256_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA256; + break; + case SHA2_MODE_SELECT_SHA384: + digestLength = SHA2_SHA384_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA512; + break; + case SHA2_MODE_SELECT_SHA512: + digestLength = SHA2_SHA512_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA512; + break; + default: + return SHA2_INVALID_ALGORITHM; + } + + if (initialHash && finalHash) { + // The empty string is a perfectly valid message. It obviously has a length of 0. The DMA cannot + // handle running with a transfer length of 0. This workaround depends on the hash engine adding the + // trailing 1 bit and 0-padding bits after the DMAtransfer is complete and not in the DMA itself. + // totalMsgLength is purposefully not altered as it is appended to the end of the message during finalization + // and determines how many padding-bytes are added. + // Altering totalMsgLength would alter the final hash digest. + // Because totalMsgLength specifies that the message is of length 0, the content of the byte loaded + // through the DMA is irrelevant. It is overwritten internally in the hash engine. + messageLength = messageLength ? messageLength : 1; + } + + // Setting the incorrect number of bits here leads to the calculation of the correct result + // but a failure to read them out. + // The tag bit is set to read out the digest via DMA rather than through the slave interface. + SHA2SelectAlgorithm(dmaAlgorithmSelect | (resultDigest ? SHA2_ALGSEL_TAG : 0)); + SHA2IntClear(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); + SHA2IntEnable(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); + + HWREG(CRYPTO_BASE + CRYPTO_O_HASHMODE) = hashAlgorithm | (initialHash ? CRYPTO_HASHMODE_NEW_HASH_M : 0); + + // Only load the intermediate digest if requested. + if (intermediateDigest && !initialHash) { + SHA2SetDigest(intermediateDigest, digestLength); + } + + // If this is the final hash, finalization is required. This means appending a 1 bit, padding the message until this section + // is 448 bytes long, and adding the 64 bit total length of the message in bits. Thankfully, this is all done in hardware. + if (finalHash) { + // This specific length must be specified in bits not bytes. + SHA2SetMessageLength(totalMsgLength * 8); + HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) = CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M; + + } + + // The cast is fine in this case. SHA2StartDMAOperation channel one serves as input and no one does + // hash operations in-place. + SHA2StartDMAOperation((uint8_t *)message, messageLength, resultDigest, digestLength); + + return SHA2_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.h new file mode 100644 index 0000000..7fe3cfb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.h @@ -0,0 +1,802 @@ +/****************************************************************************** +* Filename: sha2.h +* Revised: 2018-04-17 16:04:03 +0200 (Tue, 17 Apr 2018) +* Revision: 51893 +* +* Description: SHA-2 header file. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup sha2_api +//! @{ +// +//***************************************************************************** + +#ifndef __SHA2_H__ +#define __SHA2_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_crypto.h" +#include "../inc/hw_ccfg.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SHA2StartDMAOperation NOROM_SHA2StartDMAOperation + #define SHA2WaitForIRQFlags NOROM_SHA2WaitForIRQFlags + #define SHA2ComputeInitialHash NOROM_SHA2ComputeInitialHash + #define SHA2ComputeIntermediateHash NOROM_SHA2ComputeIntermediateHash + #define SHA2ComputeFinalHash NOROM_SHA2ComputeFinalHash + #define SHA2ComputeHash NOROM_SHA2ComputeHash +#endif + +//***************************************************************************** +// +// Values that can be passed to SHA2IntEnable, SHA2IntDisable, and SHA2IntClear +// as the intFlags parameter, and returned from SHA2IntStatus. +// Only SHA2_DMA_IN_DONE and SHA2_RESULT_RDY are routed to the NVIC. Check each +// function to see if it supports other interrupt status flags. +// +//***************************************************************************** +#define SHA2_DMA_IN_DONE (CRYPTO_IRQEN_DMA_IN_DONE_M) +#define SHA2_RESULT_RDY (CRYPTO_IRQEN_RESULT_AVAIL_M) +#define SHA2_DMA_BUS_ERR (CRYPTO_IRQCLR_DMA_BUS_ERR_M) + + +//***************************************************************************** +// +// General constants +// +//***************************************************************************** + +// SHA-2 module return codes +#define SHA2_SUCCESS 0 +#define SHA2_INVALID_ALGORITHM 1 +#define SHA2_DMA_BUSY 3 +#define SHA2_DMA_ERROR 4 +#define SHA2_DIGEST_NOT_READY 5 +#define SHA2_OLD_DIGEST_NOT_READ 6 + +// SHA-2 output digest lengths in bytes. +#define SHA2_SHA224_DIGEST_LENGTH_BYTES (224 / 8) +#define SHA2_SHA256_DIGEST_LENGTH_BYTES (256 / 8) +#define SHA2_SHA384_DIGEST_LENGTH_BYTES (384 / 8) +#define SHA2_SHA512_DIGEST_LENGTH_BYTES (512 / 8) + +//Selectable SHA-2 modes. They determine the algorithm used and if initial +//values will be set to the default constants or not +#define SHA2_MODE_SELECT_SHA224 (CRYPTO_HASHMODE_SHA224_MODE_M) +#define SHA2_MODE_SELECT_SHA256 (CRYPTO_HASHMODE_SHA256_MODE_M) +#define SHA2_MODE_SELECT_SHA384 (CRYPTO_HASHMODE_SHA384_MODE_M) +#define SHA2_MODE_SELECT_SHA512 (CRYPTO_HASHMODE_SHA512_MODE_M) +#define SHA2_MODE_SELECT_NEW_HASH (CRYPTO_HASHMODE_NEW_HASH_M) + +// SHA-2 block lengths. When hashing block-wise, they define the size of each +// block provided to the new and intermediate hash functions. +#define SHA2_SHA224_BLOCK_SIZE_BYTES (512 / 8) +#define SHA2_SHA256_BLOCK_SIZE_BYTES (512 / 8) +#define SHA2_SHA384_BLOCK_SIZE_BYTES (1024 / 8) +#define SHA2_SHA512_BLOCK_SIZE_BYTES (1024 / 8) + +// DMA status codes +#define SHA2_DMA_CHANNEL0_ACTIVE (CRYPTO_DMASTAT_CH0_ACT_M) +#define SHA2_DMA_CHANNEL1_ACTIVE (CRYPTO_DMASTAT_CH1_ACT_M) +#define SHA2_DMA_PORT_ERROR (CRYPTO_DMASTAT_PORT_ERR_M) + +// Crypto module DMA operation types +#define SHA2_ALGSEL_SHA256 0x04 +#define SHA2_ALGSEL_SHA512 0x08 +#define SHA2_ALGSEL_TAG (CRYPTO_ALGSEL_TAG_M) + + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Start a crypto DMA operation +//! +//! Enable the crypto DMA channels, configure the channel addresses, +//! and set the length of the data transfer. +//! Setting the length of the data transfer automatically starts the +//! transfer. It is also used by the hardware module as a signal to +//! begin the encryption, decryption, or MAC operation. +//! +//! \param [in] channel0Addr +//! A pointer to the address channel 0 shall use. +//! +//! \param [in] channel0Length +//! Length of the data in bytes to be read from or written to at +//! \c channel0Addr. Set to 0 to not set up this channel. +//! +//! \param [out] channel1Addr +//! A pointer to the address channel 1 shall use. +//! +//! \param [in] channel1Length +//! Length of the data in bytes to be read from or written to at +//! \c channel1Addr. Set to 0 to not set up this channel. +//! +//! \return None +// +//***************************************************************************** +extern void SHA2StartDMAOperation(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length); + +//***************************************************************************** +// +//! \brief Poll the interrupt status register and clear when done. +//! +//! This function polls until one of the bits in the \c irqFlags is +//! asserted. Only \ref SHA2_DMA_IN_DONE and \ref SHA2_RESULT_RDY can actually +//! trigger the interrupt line. That means that one of those should +//! always be included in \c irqFlags and will always be returned together +//! with any error codes. +//! +//! \param [in] irqFlags +//! IRQ flags to poll and mask that the status register will be +//! masked with. Consists of any bitwise OR of the flags +//! below that includes at least one of +//! \ref SHA2_DMA_IN_DONE or \ref SHA2_RESULT_RDY : +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +//! - \ref SHA2_DMA_BUS_ERR +//! +//! \return Returns the IRQ status register masked with \c irqFlags. May be any +//! bitwise OR of the following masks: +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +//! - \ref SHA2_DMA_BUS_ERR +// +//***************************************************************************** +extern uint32_t SHA2WaitForIRQFlags(uint32_t irqFlags); + +//***************************************************************************** +// +//! \brief Start a new SHA-2 hash operation. +//! +//! This function begins a new piecewise hash operation. +//! +//! Call this function when starting a new hash operation and the +//! entire message is not yet available. +//! +//! Call SHA2ComputeIntermediateHash() or SHA2ComputeFinalHash() +//! after this call. +//! +//! If the device shall go into standby in between calls to this +//! function and either SHA2ComputeIntermediateHash() or +//! SHA2ComputeFinalHash(), the intermediate digest must be saved in +//! system RAM. +//! +//! \param [in] message +//! Byte array containing the start of the message to hash. +//! Must be exactly as long as the block length of the selected +//! algorithm. +//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES +//! +//! \param [out] intermediateDigest +//! Pointer to intermediate digest. +//! - NULL The intermediate digest will be stored in the internal +//! registers of the SHA module. +//! - Not NULL Specifies the location the intermediate digest will +//! be written to. +//! +//! Must be of a length equal to the digest length of the selected +//! hash algorithm. +//! Must be 32-bit aligned. \c intermediateDigest is copied into the +//! registers through the AHB slave interface in +//! SHA2ComputeIntermediateHash() and SHA2ComputeFinalHash(). +//! This can only be done word-by-word. +//! +//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of: +//! - \ref SHA2_MODE_SELECT_SHA224 +//! - \ref SHA2_MODE_SELECT_SHA256 +//! - \ref SHA2_MODE_SELECT_SHA384 +//! - \ref SHA2_MODE_SELECT_SHA512 +//! +//! \param [in] initialMessageLength The length in bytes of the first +//! section of the message to process. Must be a multiple of the +//! block size. +//! +//! \return Returns a SHA-2 return code. +//! - \ref SHA2_SUCCESS +//! - \ref SHA2_INVALID_ALGORITHM +//! +//! \sa SHA2ComputeIntermediateHash() +//! \sa SHA2ComputeFinalHash() +// +//***************************************************************************** +extern uint32_t SHA2ComputeInitialHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength); + +//***************************************************************************** +// +//! \brief Resume a SHA-2 hash operation but do not finalize it. +//! +//! This function resumes a previous hash operation. +//! +//! Call this function when continuing a hash operation and the +//! message is not yet complete. +//! +//! Call this function again or SHA2ComputeFinalHash() +//! after this call. +//! +//! If the device shall go into standby in between calls to this +//! function and SHA2ComputeFinalHash(), the intermediate +//! digest must be saved in system RAM. +//! +//! \param [in] message +//! Byte array containing the start of the current block of the +//! message to hash. +//! Must be exactly as long as the block length of the selected +//! algorithm. +//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES +//! +//! \param [in, out] intermediateDigest +//! Pointer to intermediate digest. +//! - NULL The intermediate digest will be sourced from the internal +//! registers of the SHA module and stored there after the +//! operation completes. +//! - Not NULL Specifies the location the intermediate digest will +//! be read from and written to. +//! +//! Must be of a length equal to the digest length of the selected +//! hash algorithm. +//! Must be 32-bit aligned. \c intermediateDigest is copied from and +//! to the registers through the AHB slave interface. +//! This can only be done word-by-word. +//! +//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of: +//! - \ref SHA2_MODE_SELECT_SHA224 +//! - \ref SHA2_MODE_SELECT_SHA256 +//! - \ref SHA2_MODE_SELECT_SHA384 +//! - \ref SHA2_MODE_SELECT_SHA512 +//! +//! \param [in] intermediateMessageLength The length in bytes of this +//! section of the message to process. Must be a multiple of the +//! block size. +//! +//! \return Returns a SHA-2 return code. +//! - \ref SHA2_SUCCESS +//! - \ref SHA2_INVALID_ALGORITHM +//! +//! \sa SHA2ComputeInitialHash() +//! \sa SHA2ComputeFinalHash() +// +//***************************************************************************** +extern uint32_t SHA2ComputeIntermediateHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength); + +//***************************************************************************** +// +//! \brief Resume a SHA-2 hash operation and finalize it. +//! +//! This function resumes a previous hash session. +//! +//! Call this function when continuing a hash operation and the +//! message is complete. +//! +//! \param [in] message +//! Byte array containing the final block of the message to hash. +//! Any length <= the block size is acceptable. +//! The DMA finalize the message as necessary. +//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES +//! +//! \param [out] resultDigest +//! Byte array that the final digest will be written to. Must be of +//! a length equal to the digest length of the selected hash algorithm. +//! +//! \param [in] intermediateDigest +//! Pointer to intermediate digest. +//! - NULL The intermediate digest will be sourced from the internal +//! registers of the SHA module. +//! - Not NULL Specifies the location the intermediate digest will +//! be read from. +//! Must be of a length equal to the digest length of the selected +//! hash algorithm. +//! Must be 32-bit aligned. \c intermediateDigest is copied from and +//! to the registers through the AHB slave interface. +//! This can only be done word-by-word. +//! +//! \param [in] totalMsgLength +//! The length in bytes of the entire \c message including the sections +//! passed to previous calls to SHA2ComputeInitialHash() and +//! SHA2ComputeIntermediateHash(). +//! +//! \param [in] messageLength The length in bytes of the last +//! section of the message to process. Does not need to be +//! a multiple of the block size. +//! +//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of: +//! - \ref SHA2_MODE_SELECT_SHA224 +//! - \ref SHA2_MODE_SELECT_SHA256 +//! - \ref SHA2_MODE_SELECT_SHA384 +//! - \ref SHA2_MODE_SELECT_SHA512 +//! +//! \return Returns a SHA-2 return code. +//! - \ref SHA2_SUCCESS +//! - \ref SHA2_INVALID_ALGORITHM +//! +//! \sa SHA2ComputeInitialHash() +//! \sa SHA2ComputeIntermediateHash() +// +//***************************************************************************** +extern uint32_t SHA2ComputeFinalHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm); + +//***************************************************************************** +// +//! \brief Start a SHA-2 hash operation and return the finalized digest. +//! +//! This function starts a hash operation and returns the finalized +//! digest. +//! +//! Use this function if the entire message is available when starting +//! the hash. +//! +//! \param [in] message +//! Byte array containing the message that will be hashed. +//! Any length <= the block size is acceptable. +//! The DMA will finalize the message as necessary. +//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES +//! +//! \param [out] resultDigest +//! Byte array that the final digest will be written to. Must be of a +//! length equal to the digest length of the selected hash algorithm. +//! +//! \param [in] totalMsgLength +//! The length in bytes of the entire \c message. +//! +//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of: +//! - \ref SHA2_MODE_SELECT_SHA224 +//! - \ref SHA2_MODE_SELECT_SHA256 +//! - \ref SHA2_MODE_SELECT_SHA384 +//! - \ref SHA2_MODE_SELECT_SHA512 +//! +//! \return Returns a SHA-2 return code. +//! - \ref SHA2_SUCCESS +//! - \ref SHA2_INVALID_ALGORITHM +//! +// +//***************************************************************************** +extern uint32_t SHA2ComputeHash(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm); + +//***************************************************************************** +// +//! \brief Configure the crypto DMA for a particular operation. +//! +//! \param algorithm +//! Configures the crypto DMA for a particular operation. +//! It also powers on the respective part of the system. +//! \ref SHA2_ALGSEL_TAG may be combined with another flag. All other +//! flags are mutually exclusive. +//! - 0 : Reset the module and turn off all sub-modules. +//! - \ref SHA2_ALGSEL_SHA256 Configure for a SHA224 or SHA256 operation. +//! - \ref SHA2_ALGSEL_SHA512 Configure for a SHA384 or SHA512 operation. +//! - \ref SHA2_ALGSEL_TAG Read out hash via DMA rather than the slave interface +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SHA2SelectAlgorithm(uint32_t algorithm) +{ + ASSERT((algorithm == SHA2_ALGSEL_SHA256) || + (algorithm == SHA2_ALGSEL_SHA512) || + (algorithm == SHA2_ALGSEL_SHA256 | SHA2_ALGSEL_TAG) || + (algorithm == SHA2_ALGSEL_SHA512 | SHA2_ALGSEL_TAG)); + + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm; +} + + + +//***************************************************************************** +// +//! \brief Specify the total length of the message. +//! +//! Despite specifying it here, the crypto DMA must still be +//! set up with the correct data length. +//! +//! Call this function only when setting up the final hash operation to +//! enable finalization. +//! +//! \param length Total message length in bits. +//! +//! \return None +//! +//! \sa SHA2StartDMAOperation() +// +//***************************************************************************** +__STATIC_INLINE void SHA2SetMessageLength(uint32_t length) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_HASHINLENL) = length; + // CRYPTO_O_HASHINLENH is automatically set to 0. No need for the extra write. +} + +//***************************************************************************** +// +//! \brief Load an intermediate digest. +//! +//! \param [in] digestLength +//! Length of the digest in bytes. Must be one of: +//! - \ref SHA2_SHA224_DIGEST_LENGTH_BYTES +//! - \ref SHA2_SHA256_DIGEST_LENGTH_BYTES +//! - \ref SHA2_SHA384_DIGEST_LENGTH_BYTES +//! - \ref SHA2_SHA512_DIGEST_LENGTH_BYTES +//! +//! \param [in] digest +//! Pointer to an intermediate digest. Must be 32-bit aligned. +//! +// +//***************************************************************************** +__STATIC_INLINE void SHA2SetDigest(uint32_t *digest, uint8_t digestLength) +{ + // Check the arguments. + ASSERT(!(digest == NULL) && !((uint32_t)digest & 0x03)); + ASSERT((digestLength == SHA2_SHA224_DIGEST_LENGTH_BYTES) || + (digestLength == SHA2_SHA256_DIGEST_LENGTH_BYTES) || + (digestLength == SHA2_SHA384_DIGEST_LENGTH_BYTES) || + (digestLength == SHA2_SHA512_DIGEST_LENGTH_BYTES)); + + // Write digest + uint32_t i = 0; + for (i = 0; i < (digestLength / sizeof(uint32_t)); i++) { + HWREG(CRYPTO_BASE + CRYPTO_O_HASHDIGESTA + (i * sizeof(uint32_t))) = digest[i]; + } + +} + +//***************************************************************************** +// +//! \brief Read the intermediate or final digest. +//! +//! \param [in] digestLength Length of the digest in bytes. Must be one of: +//! - ref SHA2_SHA224_DIGEST_LENGTH_BYTES +//! - ref SHA2_SHA256_DIGEST_LENGTH_BYTES +//! - ref SHA2_SHA384_DIGEST_LENGTH_BYTES +//! - ref SHA2_SHA512_DIGEST_LENGTH_BYTES +//! +//! \param [out] digest +//! Pointer to an intermediate digest. Must be 32-bit aligned. +//! +//! \return Returns a status code. +//! - \ref SHA2_OLD_DIGEST_NOT_READ +//! - \ref SHA2_SUCCESS +// +//***************************************************************************** +__STATIC_INLINE uint32_t SHA2GetDigest(uint32_t *digest, uint8_t digestLength) +{ + // Check the arguments. + ASSERT(!(digest == NULL) && !((uint32_t)digest & 0x03)); + ASSERT((digestLength == SHA2_SHA224_DIGEST_LENGTH_BYTES) || + (digestLength == SHA2_SHA256_DIGEST_LENGTH_BYTES) || + (digestLength == SHA2_SHA384_DIGEST_LENGTH_BYTES) || + (digestLength == SHA2_SHA512_DIGEST_LENGTH_BYTES)); + + if (HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) & CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_M) { + return SHA2_OLD_DIGEST_NOT_READ; + } + else { + // Read digest + uint32_t i = 0; + for (i = 0; i < (digestLength / sizeof(uint32_t)); i++) { + digest[i] = HWREG(CRYPTO_BASE + CRYPTO_O_HASHDIGESTA + (i * sizeof(uint32_t))); + } + return SHA2_SUCCESS; + } +} + +//***************************************************************************** +// +//! \brief Confirm digest was read. +// +//***************************************************************************** +__STATIC_INLINE void SHA2ClearDigestAvailableFlag(void) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) = HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL); +} + +//***************************************************************************** +// +//! \brief Enable individual crypto interrupt sources. +//! +//! This function enables the indicated crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param intFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SHA2IntEnable(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & SHA2_DMA_IN_DONE) || + (intFlags & SHA2_RESULT_RDY)); + + // Using level interrupt. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; + + // Enable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; +} + +//***************************************************************************** +// +//! \brief Disable individual crypto interrupt sources. +//! +//! This function disables the indicated crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param intFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SHA2IntDisable(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & SHA2_DMA_IN_DONE) || + (intFlags & SHA2_RESULT_RDY)); + + // Disable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; +} + +//***************************************************************************** +// +//! \brief Get the current masked interrupt status. +//! +//! This function returns the masked interrupt status of the crypto module. +//! +//! \return Returns the status of the masked lines when enabled: +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +// +//***************************************************************************** +__STATIC_INLINE uint32_t SHA2IntStatusMasked(void) +{ + uint32_t mask; + + // Return the masked interrupt status + mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); + return(mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); +} + +//***************************************************************************** +// +//! \brief Get the current raw interrupt status. +//! +//! This function returns the raw interrupt status of the crypto module. +//! It returns both the status of the lines routed to the NVIC as well as the +//! error flags. +//! +//! \return Returns the raw interrupt status: +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +//! - \ref SHA2_DMA_BUS_ERR +// +//***************************************************************************** +__STATIC_INLINE uint32_t SHA2IntStatusRaw(void) +{ + // Return either the raw interrupt status + return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); +} + +//***************************************************************************** +// +//! \brief Clear crypto interrupt sources. +//! +//! The specified crypto interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in the module until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SHA2IntClear(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & SHA2_DMA_IN_DONE) || + (intFlags & SHA2_RESULT_RDY)); + + // Clear the requested interrupt sources, + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = intFlags; +} + +//***************************************************************************** +// +//! \brief Register an interrupt handler for a crypto interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific crypto interrupts must be enabled via \ref SHA2IntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \param handlerFxn is a pointer to the function to be called when the +//! crypto interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void SHA2IntRegister(void (*handlerFxn)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, handlerFxn); + + // Enable the crypto interrupt. + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregister an interrupt handler for a crypto interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler called when a crypto interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void SHA2IntUnregister(void) +{ + // Disable the interrupt. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SHA2StartDMAOperation + #undef SHA2StartDMAOperation + #define SHA2StartDMAOperation ROM_SHA2StartDMAOperation + #endif + #ifdef ROM_SHA2WaitForIRQFlags + #undef SHA2WaitForIRQFlags + #define SHA2WaitForIRQFlags ROM_SHA2WaitForIRQFlags + #endif + #ifdef ROM_SHA2ComputeInitialHash + #undef SHA2ComputeInitialHash + #define SHA2ComputeInitialHash ROM_SHA2ComputeInitialHash + #endif + #ifdef ROM_SHA2ComputeIntermediateHash + #undef SHA2ComputeIntermediateHash + #define SHA2ComputeIntermediateHash ROM_SHA2ComputeIntermediateHash + #endif + #ifdef ROM_SHA2ComputeFinalHash + #undef SHA2ComputeFinalHash + #define SHA2ComputeFinalHash ROM_SHA2ComputeFinalHash + #endif + #ifdef ROM_SHA2ComputeHash + #undef SHA2ComputeHash + #define SHA2ComputeHash ROM_SHA2ComputeHash + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SHA2_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2_doc.h new file mode 100644 index 0000000..d516cbe --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2_doc.h @@ -0,0 +1,62 @@ +/****************************************************************************** +* Filename: sha2_doc.h +* Revised: 2017-11-01 10:33:37 +0100 (Wed, 01 Nov 2017) +* Revision: 50125 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup sha2_api +//! @{ +//! \section sec_sha2 Introduction +//! +//! The SHA-2 (Secure Hash Algorithm) API provides access to the SHA-2 +//! functionality of the crypto core. The AES accelerator and keystore are +//! also contained within the crypto core. Hence, only one of SHA-2 and AES +//! may be used at the same time. +//! This module offers hardware acceleration for the SHA-2 family of hash +//! algorithms. The following output digest sizes are supported: +//! - 224 bits +//! - 256 bits +//! - 384 bits +//! - 512 bits +//! +//! Messages are hashed in one go or in multiple steps. Stepwise hashing +//! consists of an initial hash, multiple intermediate hashes, and a +//! finalization hash. +//! +//! The crypto core does not have retention and all configuration settings +//! are lost when going into standby or shutdown. If you wish to continue +//! a hash operation after going into standby or shutdown, you must load +//! the intermediate hash into system RAM before entering standby or shutdown +//! and load the intermediate hash back into the crypto module after resuming +//! operation. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph.c new file mode 100644 index 0000000..84df1f3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph.c @@ -0,0 +1,101 @@ +/****************************************************************************** +* Filename: smph.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the MCU Semaphore. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "smph.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SMPHAcquire + #define SMPHAcquire NOROM_SMPHAcquire +#endif + +//***************************************************************************** +// +// Acquire a semaphore +// +//***************************************************************************** +void +SMPHAcquire(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // Wait for semaphore to be release such that it can be claimed + // Semaphore register reads 1 when lock was acquired otherwise 0 + // (i.e. SMPH_CLAIMED). + while(HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) == + SMPH_CLAIMED) + { + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph.h new file mode 100644 index 0000000..636979d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph.h @@ -0,0 +1,312 @@ +/****************************************************************************** +* Filename: smph.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the MCU Semaphore. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup mcusemaphore_api +//! @{ +// +//***************************************************************************** + +#ifndef __SMPH_H__ +#define __SMPH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_smph.h" +#include "../inc/hw_memmap.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SMPHAcquire NOROM_SMPHAcquire +#endif + +//***************************************************************************** +// +// General constants and defines +// +//***************************************************************************** +#define SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed + +//***************************************************************************** +// +// Values that can be passed to SMPHAcquire, SMPHTryAcquire and SMPHRelease +// as the ui32Semaphore parameter. +// +//***************************************************************************** +#define SMPH_0 0 // MCU Semaphore 0 +#define SMPH_1 1 // MCU Semaphore 1 +#define SMPH_2 2 // MCU Semaphore 2 +#define SMPH_3 3 // MCU Semaphore 3 +#define SMPH_4 4 // MCU Semaphore 4 +#define SMPH_5 5 // MCU Semaphore 5 +#define SMPH_6 6 // MCU Semaphore 6 +#define SMPH_7 7 // MCU Semaphore 7 +#define SMPH_8 8 // MCU Semaphore 8 +#define SMPH_9 9 // MCU Semaphore 9 +#define SMPH_10 10 // MCU Semaphore 10 +#define SMPH_11 11 // MCU Semaphore 11 +#define SMPH_12 12 // MCU Semaphore 12 +#define SMPH_13 13 // MCU Semaphore 13 +#define SMPH_14 14 // MCU Semaphore 14 +#define SMPH_15 15 // MCU Semaphore 15 +#define SMPH_16 16 // MCU Semaphore 16 +#define SMPH_17 17 // MCU Semaphore 17 +#define SMPH_18 18 // MCU Semaphore 18 +#define SMPH_19 19 // MCU Semaphore 19 +#define SMPH_20 20 // MCU Semaphore 20 +#define SMPH_21 21 // MCU Semaphore 21 +#define SMPH_22 22 // MCU Semaphore 22 +#define SMPH_23 23 // MCU Semaphore 23 +#define SMPH_24 24 // MCU Semaphore 24 +#define SMPH_25 25 // MCU Semaphore 25 +#define SMPH_26 26 // MCU Semaphore 26 +#define SMPH_27 27 // MCU Semaphore 27 +#define SMPH_28 28 // MCU Semaphore 28 +#define SMPH_29 29 // MCU Semaphore 29 +#define SMPH_30 30 // MCU Semaphore 30 +#define SMPH_31 31 // MCU Semaphore 31 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Acquire a semaphore. +//! +//! This function acquires the given semaphore, blocking the call until +//! the semaphore is available. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref SMPH_0 +//! - \ref SMPH_1 +//! - ... +//! - \ref SMPH_31 +//! +//! \return None +// +//***************************************************************************** +extern void SMPHAcquire(uint32_t ui32Semaphore); + +//***************************************************************************** +// +//! \brief Try to Acquire a semaphore. +//! +//! This function tries to acquire the given semaphore, if the semaphore +//! could not be claimed the function returns false. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref SMPH_0 +//! - \ref SMPH_1 +//! - ... +//! - \ref SMPH_31 +//! +//! \return Returns if a semaphore was acquired +//! - \c true : Semaphore acquired. +//! - \c false : Semaphore \b not acquired. +// +//***************************************************************************** +__STATIC_INLINE bool +SMPHTryAcquire(uint32_t ui32Semaphore) +{ + uint32_t ui32SemaReg; + + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // Semaphore register reads 1 if lock was acquired + // (i.e. SMPH_FREE). + ui32SemaReg = HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore); + + return (ui32SemaReg == SMPH_FREE); +} + +//***************************************************************************** +// +//! \brief Release a semaphore. +//! +//! This function releases the given semaphore. +//! +//! \note It is up to the application to provide the convention for clearing +//! semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref SMPH_0 +//! - \ref SMPH_1 +//! - ... +//! - \ref SMPH_31 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SMPHRelease(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // No check before release, it is up to the application to provide the + // conventions for who and when a semaphore can be released. + HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) = SMPH_FREE; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SMPHAcquire + #undef SMPHAcquire + #define SMPHAcquire ROM_SMPHAcquire + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SMPH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph_doc.h new file mode 100644 index 0000000..c66ef84 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph_doc.h @@ -0,0 +1,57 @@ +/****************************************************************************** +* Filename: smph_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup mcusemaphore_api +//! @{ +//! \section sec_mcusemaphore Introduction +//! +//! The MCU Semaphore offers 32 semaphores that each can be claimed and released in an atomic operation. +//! One and only one semaphore can be handled during a transaction. +//! +//! Claiming a semaphore causes subsequent claims/reads to return '0' (i.e. "not available"). +//! How the semaphores are used and respected is decided by software. +//! +//! \section sec_mcusemaphore_api API +//! +//! The API functions can be grouped like this: +//! +//! Semaphore acquire: +//! - \ref SMPHAcquire() +//! - \ref SMPHTryAcquire() +//! +//! Semaphore release: +//! - \ref SMPHRelease() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.c new file mode 100644 index 0000000..76fc8e7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.c @@ -0,0 +1,253 @@ +/****************************************************************************** +* Filename: ssi.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for Synchronous Serial Interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ssi.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SSIConfigSetExpClk + #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk + #undef SSIDataPut + #define SSIDataPut NOROM_SSIDataPut + #undef SSIDataPutNonBlocking + #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking + #undef SSIDataGet + #define SSIDataGet NOROM_SSIDataGet + #undef SSIDataGetNonBlocking + #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking + #undef SSIIntRegister + #define SSIIntRegister NOROM_SSIIntRegister + #undef SSIIntUnregister + #define SSIIntUnregister NOROM_SSIIntUnregister +#endif + +//***************************************************************************** +// +// Configures the synchronous serial port +// +//***************************************************************************** +void +SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, uint32_t ui32DataWidth) +{ + uint32_t ui32MaxBitRate; + uint32_t ui32RegVal; + uint32_t ui32PreDiv; + uint32_t ui32SCR; + uint32_t ui32SPH_SPO; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || + (ui32Protocol == SSI_FRF_MOTO_MODE_1) || + (ui32Protocol == SSI_FRF_MOTO_MODE_2) || + (ui32Protocol == SSI_FRF_MOTO_MODE_3) || + (ui32Protocol == SSI_FRF_TI) || + (ui32Protocol == SSI_FRF_NMW)); + ASSERT((ui32Mode == SSI_MODE_MASTER) || + (ui32Mode == SSI_MODE_SLAVE) || + (ui32Mode == SSI_MODE_SLAVE_OD)); + ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) || + ((ui32Mode != SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 12)))); + ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); + ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); + + // Set the mode. + ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; + + // Set the clock predivider. + ui32MaxBitRate = ui32SSIClk / ui32BitRate; + ui32PreDiv = 0; + do + { + ui32PreDiv += 2; + ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; + } + while(ui32SCR > 255); + HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; + + // Set protocol and clock rate. + ui32SPH_SPO = (ui32Protocol & 3) << 6; + ui32Protocol &= SSI_CR0_FRF_M; + ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | (ui32DataWidth - 1); + HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; +} + +//***************************************************************************** +// +// Puts a data element into the SSI transmit FIFO +// +//***************************************************************************** +int32_t +SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // Check for space to write. + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ui32Base + SSI_O_DR) = ui32Data; + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +// Puts a data element into the SSI transmit FIFO +// +//***************************************************************************** +void +SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // Wait until there is space. + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // Write the data to the SSI. + HWREG(ui32Base + SSI_O_DR) = ui32Data; +} + +//***************************************************************************** +// +// Gets a data element from the SSI receive FIFO +// +//***************************************************************************** +void +SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Wait until there is data to be read. + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // Read data from SSI. + *pui32Data = HWREG(ui32Base + SSI_O_DR); +} + +//***************************************************************************** +// +// Gets a data element from the SSI receive FIFO +// +//***************************************************************************** +int32_t +SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Check for data to read. + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) + { + *pui32Data = HWREG(ui32Base + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +// Registers an interrupt handler for the synchronous serial port +// +//***************************************************************************** +void +SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Determine the interrupt number based on the SSI port. + ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB; + + // Register the interrupt handler. + IntRegister(ui32Int, pfnHandler); + + // Enable the synchronous serial port interrupt. + IntEnable(ui32Int); +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for the synchronous serial port +// +//***************************************************************************** +void +SSIIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Determine the interrupt number based on the SSI port. + ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB; + + // Disable the interrupt. + IntDisable(ui32Int); + + // Unregister the interrupt handler. + IntUnregister(ui32Int); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.h new file mode 100644 index 0000000..87a9745 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.h @@ -0,0 +1,700 @@ +/****************************************************************************** +* Filename: ssi.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and macros for the SSI. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup ssi_api +//! @{ +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "../inc/hw_ssi.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk + #define SSIDataPut NOROM_SSIDataPut + #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking + #define SSIDataGet NOROM_SSIDataGet + #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking + #define SSIIntRegister NOROM_SSIIntRegister + #define SSIIntUnregister NOROM_SSIIntUnregister +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ui32IntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half full or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or more +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that are returned from SSIStatus +// +//***************************************************************************** +#define SSI_RX_FULL 0x00000008 // Receive FIFO full +#define SSI_RX_NOT_EMPTY 0x00000004 // Receive FIFO not empty +#define SSI_TX_NOT_FULL 0x00000002 // Transmit FIFO not full +#define SSI_TX_EMPTY 0x00000001 // Transmit FIFO empty +#define SSI_STATUS_MASK 0x0000000F + +//***************************************************************************** +// +// Values that can be passed to SSIConfigSetExpClk. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). +// +//***************************************************************************** +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an SSI base address. +//! +//! This function determines if an SSI module base address is valid. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +SSIBaseValid(uint32_t ui32Base) +{ + return(ui32Base == SSI0_BASE || ui32Base == SSI1_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Configures the synchronous serial port. +//! +//! This function configures the synchronous serial port. It sets +//! the SSI protocol, mode of operation, bit rate, and data width. +//! +//! The \c ui32Protocol parameter defines the data frame format. The Motorola +//! frame formats imply the following polarity and phase configurations: +//! +//! 
+//! Polarity Phase       Mode
+//!   0       0   SSI_FRF_MOTO_MODE_0
+//!   0       1   SSI_FRF_MOTO_MODE_1
+//!   1       0   SSI_FRF_MOTO_MODE_2
+//!   1       1   SSI_FRF_MOTO_MODE_3
+//!
+//! +//! The \c ui32Mode parameter defines the operating mode of the SSI module. +//! The SSI module can operate as a master or slave; if a slave, the SSI can be +//! configured to disable output on its serial output line. +//! +//! The \c ui32BitRate parameter defines the bit rate for the SSI. This bit +//! rate must satisfy the following clock ratio criteria: +//! - Master mode : FSSI >= 2 * bit rate +//! - Slave mode : FSSI >= 12 * bit rate +//! +//! where FSSI is the frequency of the clock supplied to the SSI module. +//! +//! The \c ui32DataWidth parameter defines the width of the data transfers, and +//! can be a value between 4 and 16, inclusive. +//! +//! \note The peripheral clock is not necessarily the same as the processor clock. +//! The frequency of the peripheral clock is set by the system control. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32SSIClk is the rate of the clock supplied to the SSI module. +//! \param ui32Protocol specifies the data transfer protocol. +//! The parameter can be one of the following values: +//! - \ref SSI_FRF_MOTO_MODE_0 +//! - \ref SSI_FRF_MOTO_MODE_1 +//! - \ref SSI_FRF_MOTO_MODE_2 +//! - \ref SSI_FRF_MOTO_MODE_3 +//! - \ref SSI_FRF_TI +//! - \ref SSI_FRF_NMW. +//! \param ui32Mode specifies the mode of operation. +//! The parameter can be one of the following values: +//! - \ref SSI_MODE_MASTER +//! - \ref SSI_MODE_SLAVE +//! - \ref SSI_MODE_SLAVE_OD +//! \param ui32BitRate specifies the clock rate. +//! \param ui32DataWidth specifies number of bits transferred per frame. +//! Must be a value between 4 and 16, both included. +//! +//! \return None +// +//***************************************************************************** +extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, uint32_t ui32DataWidth); + +//***************************************************************************** +// +//! \brief Enables the synchronous serial port. +//! +//! This function enables operation of the synchronous serial port. The +//! synchronous serial port must be configured before it is enabled. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Read-modify-write the enable bit. + HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE; +} + +//***************************************************************************** +// +//! \brief Disables the synchronous serial port. +//! +//! This function disables operation of the synchronous serial port. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Read-modify-write the enable bit. + HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE); +} + +//***************************************************************************** +// +//! \brief Puts a data element into the SSI transmit FIFO. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module. +//! +//! \note The upper 32 - N bits of the \c ui32Data are discarded by the +//! hardware, where N is the data width as configured by \ref SSIConfigSetExpClk(). +//! For example, if the interface is configured for 8-bit data width, the upper +//! 24 bits of \c ui32Data are discarded. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32Data is the data to be transmitted over the SSI interface. +//! +//! \return None +// +//***************************************************************************** +extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data); + +//***************************************************************************** +// +//! \brief Puts a data element into the SSI transmit FIFO. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module. If there is no space in the FIFO, then this function +//! returns a zero. +//! +//! \note The upper 32 - N bits of the \c ui32Data are discarded by the hardware, +//! where N is the data width as configured by \ref SSIConfigSetExpClk(). For +//! example, if the interface is configured for 8-bit data width, the upper 24 +//! bits of \c ui32Data are discarded. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32Data is the data to be transmitted over the SSI interface. +//! +//! \return Returns the number of elements written to the SSI transmit FIFO. +// +//***************************************************************************** +extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data); + +//***************************************************************************** +// +//! \brief Gets a data element from the SSI receive FIFO. +//! +//! This function gets received data from the receive FIFO of the specified +//! SSI module and places that data into the location specified by the +//! \c pui32Data parameter. +//! +//! \note Only the lower N bits of the value written to \c pui32Data contain +//! valid data, where N is the data width as configured by +//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to +//! \c pui32Data contain valid data. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pui32Data is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! \return None +// +//***************************************************************************** +extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data); + +//***************************************************************************** +// +//! \brief Gets a data element from the SSI receive FIFO. +//! +//! This function gets received data from the receive FIFO of the specified SSI +//! module and places that data into the location specified by the \c ui32Data +//! parameter. If there is no data in the FIFO, then this function returns a +//! zero. +//! +//! \note Only the lower N bits of the value written to \c pui32Data contain +//! valid data, where N is the data width as configured by +//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to \c pui32Data +//! contain valid data. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pui32Data is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! \return Returns the number of elements read from the SSI receive FIFO. +// +//***************************************************************************** +extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data); + +//***************************************************************************** +// +//! \brief Determines whether the SSI transmitter is busy or not. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \c false is returned, then the transmit FIFO +//! is empty and all bits of the last transmitted word have left the hardware +//! shift register. +//! +//! \param ui32Base is the base address of the SSI port. +//! +//! \return Returns status of the SSI transmit buffer. +//! - \c true : SSI is transmitting. +//! - \c false : SSI transmissions are complete. +// +//***************************************************************************** +__STATIC_INLINE bool +SSIBusy(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Determine if the SSI is busy. + return((HWREG(ui32Base + SSI_O_SR) & SSI_SR_BSY) ? true : false); +} + +//***************************************************************************** +// +//! \brief Get the status of the SSI data buffers. +//! +//! This function is used to poll the status of the internal FIFOs in the SSI +//! module. The status of both TX and RX FIFO is returned. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return Returns the current status of the internal SSI data buffers. +//! The status is a bitwise OR'ed combination of: +//! - \ref SSI_RX_FULL : Receive FIFO full. +//! - \ref SSI_RX_NOT_EMPTY : Receive FIFO not empty. +//! - \ref SSI_TX_NOT_FULL : Transmit FIFO not full. +//! - \ref SSI_TX_EMPTY : Transmit FIFO empty. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SSIStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Return the status + return (HWREG(ui32Base + SSI_O_SR) & SSI_STATUS_MASK); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific SSI interrupts must be enabled via \ref SSIIntEnable(). If necessary, +//! it is the interrupt handler's responsibility to clear the interrupt source +//! via \ref SSIIntClear(). +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial port interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when a SSI +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void SSIIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables individual SSI interrupt sources. +//! +//! Enables the indicated SSI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. +//! - \ref SSI_TXFF +//! - \ref SSI_RXFF +//! - \ref SSI_RXTO +//! - \ref SSI_RXOR +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(ui32Base + SSI_O_IMSC) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual SSI interrupt sources. +//! +//! Disables the indicated SSI interrupt sources. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. +//! - \ref SSI_TXFF +//! - \ref SSI_RXFF +//! - \ref SSI_RXTO +//! - \ref SSI_RXOR +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(ui32Base + SSI_O_IMSC) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Clears SSI interrupt sources. +//! +//! The specified SSI interrupt sources are cleared so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupts from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter can consist of either or both of: +//! - \ref SSI_RXTO : Timeout interrupt. +//! - \ref SSI_RXOR : Overrun interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Clear the requested interrupt sources. + HWREG(ui32Base + SSI_O_ICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the SSI module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param bMasked selects either raw or masked interrupt. +//! \c false : Raw interrupt status is required. +//! \c true : Masked interrupt status is required. +//! +//! \return Returns the current interrupt status as an OR'ed combination of: +//! - \ref SSI_TXFF +//! - \ref SSI_RXFF +//! - \ref SSI_RXTO +//! - \ref SSI_RXOR +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SSIIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return(HWREG(ui32Base + SSI_O_MIS)); + } + else + { + return(HWREG(ui32Base + SSI_O_RIS)); + } +} + +//***************************************************************************** +// +//! \brief Enable SSI DMA operation. +//! +//! The specified SSI DMA features are enabled. The SSI can be +//! configured to use DMA for transmit and/or receive data transfers. +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the SSI. +//! +//! \param ui32Base is the base address of the SSI port. +//! \param ui32DMAFlags is a bit mask of the DMA features to enable. +//! The parameter is the bitwise OR of any of the following values: +//! - \ref SSI_DMA_RX : Enable DMA for receive. +//! - \ref SSI_DMA_TX : Enable DMA for transmit. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Set the requested bits in the SSI DMA control register. + HWREG(ui32Base + SSI_O_DMACR) |= ui32DMAFlags; +} + +//***************************************************************************** +// +//! \brief Disable SSI DMA operation. +//! +//! This function is used to disable SSI DMA features that were enabled +//! by \ref SSIDMAEnable(). The specified SSI DMA features are disabled. +//! +//! \param ui32Base is the base address of the SSI port. +//! \param ui32DMAFlags is a bit mask of the DMA features to disable. +//! The parameter is the bitwise OR of any of the following values: +//! - \ref SSI_DMA_RX : Disable DMA for receive. +//! - \ref SSI_DMA_TX : Disable DMA for transmit. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Clear the requested bits in the SSI DMA control register. + HWREG(ui32Base + SSI_O_DMACR) &= ~ui32DMAFlags; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SSIConfigSetExpClk + #undef SSIConfigSetExpClk + #define SSIConfigSetExpClk ROM_SSIConfigSetExpClk + #endif + #ifdef ROM_SSIDataPut + #undef SSIDataPut + #define SSIDataPut ROM_SSIDataPut + #endif + #ifdef ROM_SSIDataPutNonBlocking + #undef SSIDataPutNonBlocking + #define SSIDataPutNonBlocking ROM_SSIDataPutNonBlocking + #endif + #ifdef ROM_SSIDataGet + #undef SSIDataGet + #define SSIDataGet ROM_SSIDataGet + #endif + #ifdef ROM_SSIDataGetNonBlocking + #undef SSIDataGetNonBlocking + #define SSIDataGetNonBlocking ROM_SSIDataGetNonBlocking + #endif + #ifdef ROM_SSIIntRegister + #undef SSIIntRegister + #define SSIIntRegister ROM_SSIIntRegister + #endif + #ifdef ROM_SSIIntUnregister + #undef SSIIntUnregister + #define SSIIntUnregister ROM_SSIIntUnregister + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_chacha.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_chacha.c new file mode 100644 index 0000000..50f46c8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_chacha.c @@ -0,0 +1,121 @@ +/****************************************************************************** +* Filename: sw_chacha.c +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* +chacha-ref.c version 20080118 +D. J. Bernstein +Public domain. +*/ + +#define ECRYPT_LITTLE_ENDIAN + +#include "sw_ecrypt-sync.h" + +#define ROTATE(v,c) (ROTL32(v,c)) +#define XOR(v,w) ((v) ^ (w)) +#define PLUS(v,w) (U32V((v) + (w))) +#define PLUSONE(v) (PLUS((v),1)) + +#define QUARTERROUND(a,b,c,d) \ + x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]),16); \ + x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]),12); \ + x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]), 8); \ + x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]), 7); + +static void salsa20_wordtobyte(u8 output[64],const u32 input[16]) +{ + u32 x[16]; + int i; + + for (i = 0;i < 16;++i) x[i] = input[i]; + for (i = 8;i > 0;i -= 2) { + QUARTERROUND( 0, 4, 8,12) + QUARTERROUND( 1, 5, 9,13) + QUARTERROUND( 2, 6,10,14) + QUARTERROUND( 3, 7,11,15) + QUARTERROUND( 0, 5,10,15) + QUARTERROUND( 1, 6,11,12) + QUARTERROUND( 2, 7, 8,13) + QUARTERROUND( 3, 4, 9,14) + } + for (i = 0;i < 16;++i) x[i] = PLUS(x[i],input[i]); + for (i = 0;i < 16;++i) U32TO8_LITTLE(output + 4 * i,x[i]); +} + +void ECRYPT_init(void) +{ + return; +} + +static const char sigma[16] = "expand 32-byte k"; +static const char tau[16] = "expand 16-byte k"; + +void ECRYPT_keysetup(ECRYPT_ctx *x,const u8 *k,u32 kbits,u32 ivbits) +{ + const char *constants; + + x->input[4] = U8TO32_LITTLE(k + 0); + x->input[5] = U8TO32_LITTLE(k + 4); + x->input[6] = U8TO32_LITTLE(k + 8); + x->input[7] = U8TO32_LITTLE(k + 12); + if (kbits == 256) { /* recommended */ + k += 16; + constants = sigma; + } else { /* kbits == 128 */ + constants = tau; + } + x->input[8] = U8TO32_LITTLE(k + 0); + x->input[9] = U8TO32_LITTLE(k + 4); + x->input[10] = U8TO32_LITTLE(k + 8); + x->input[11] = U8TO32_LITTLE(k + 12); + x->input[0] = U8TO32_LITTLE(constants + 0); + x->input[1] = U8TO32_LITTLE(constants + 4); + x->input[2] = U8TO32_LITTLE(constants + 8); + x->input[3] = U8TO32_LITTLE(constants + 12); +} + +void ECRYPT_ivsetup(ECRYPT_ctx *x,const u8 *iv) +{ + x->input[12] = 0; + x->input[13] = 0; + x->input[14] = U8TO32_LITTLE(iv + 0); + x->input[15] = U8TO32_LITTLE(iv + 4); +} + +void ECRYPT_encrypt_bytes(ECRYPT_ctx *x,const u8 *m,u8 *c,u32 bytes) +{ + u8 output[64]; + int i; + + if (!bytes) return; + for (;;) { + salsa20_wordtobyte(output,x->input); + x->input[12] = PLUSONE(x->input[12]); + if (!x->input[12]) { + x->input[13] = PLUSONE(x->input[13]); + /* stopping at 2^70 bytes per nonce is user's responsibility */ + } + if (bytes <= 64) { + for (i = 0;i < bytes;++i) c[i] = m[i] ^ output[i]; + return; + } + for (i = 0;i < 64;++i) c[i] = m[i] ^ output[i]; + bytes -= 64; + c += 64; + m += 64; + } +} + +void ECRYPT_decrypt_bytes(ECRYPT_ctx *x,const u8 *c,u8 *m,u32 bytes) +{ + ECRYPT_encrypt_bytes(x,c,m,bytes); +} + +void ECRYPT_keystream_bytes(ECRYPT_ctx *x,u8 *stream,u32 bytes) +{ + u32 i; + for (i = 0;i < bytes;++i) stream[i] = 0; + ECRYPT_encrypt_bytes(x,stream,stream,bytes); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-config.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-config.h new file mode 100644 index 0000000..e8885f7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-config.h @@ -0,0 +1,279 @@ +/****************************************************************************** +* Filename: sw_ecrypt-config.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* ecrypt-config.h */ + +/* *** Normally, it should not be necessary to edit this file. *** */ + +#ifndef ECRYPT_CONFIG +#define ECRYPT_CONFIG + +/* ------------------------------------------------------------------------- */ + +/* Guess the endianness of the target architecture. */ + +/* + * The LITTLE endian machines: + */ +#if ( ! defined(ECRYPT_LITTLE_ENDIAN)) +#if defined(__ultrix) /* Older MIPS */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__alpha) /* Alpha */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_M_IX86) /* x86 (MSC, Borland) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_MSC_VER) /* x86 (surely MSC) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */ +#define ECRYPT_LITTLE_ENDIAN + +/* + * The BIG endian machines: + */ +#elif defined(sun) /* Newer Sparc's */ +#define ECRYPT_BIG_ENDIAN +#elif defined(__ppc__) /* PowerPC */ +#define ECRYPT_BIG_ENDIAN + +/* + * Finally machines with UNKNOWN endianness: + */ +#elif defined (_AIX) /* RS6000 */ +#define ECRYPT_UNKNOWN +#elif defined(__hpux) /* HP-PA */ +#define ECRYPT_UNKNOWN +#elif defined(__aux) /* 68K */ +#define ECRYPT_UNKNOWN +#elif defined(__dgux) /* 88K (but P6 in latest boxes) */ +#define ECRYPT_UNKNOWN +#elif defined(__sgi) /* Newer MIPS */ +#define ECRYPT_UNKNOWN +#else /* Any other processor */ +#define ECRYPT_UNKNOWN +#endif +#endif + +/* ------------------------------------------------------------------------- */ + +/* + * Find minimal-width types to store 8-bit, 16-bit, 32-bit, and 64-bit + * integers. + * + * Note: to enable 64-bit types on 32-bit compilers, it might be + * necessary to switch from ISO C90 mode to ISO C99 mode (e.g., gcc + * -std=c99). + */ + +#include + +/* --- check char --- */ + +#if (UCHAR_MAX / 0xFU > 0xFU) +#ifndef I8T +#define I8T char +#define U8C(v) (v##U) + +#if (UCHAR_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (UCHAR_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T char +#define U16C(v) (v##U) +#endif + +#if (UCHAR_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T char +#define U32C(v) (v##U) +#endif + +#if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T char +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check short --- */ + +#if (USHRT_MAX / 0xFU > 0xFU) +#ifndef I8T +#define I8T short +#define U8C(v) (v##U) + +#if (USHRT_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (USHRT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T short +#define U16C(v) (v##U) +#endif + +#if (USHRT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T short +#define U32C(v) (v##U) +#endif + +#if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T short +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check int --- */ + +#if (UINT_MAX / 0xFU > 0xFU) +#ifndef I8T +#define I8T int +#define U8C(v) (v##U) + +#if (ULONG_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (UINT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T int +#define U16C(v) (v##U) +#endif + +#if (UINT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T int +#define U32C(v) (v##U) +#endif + +#if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T int +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check long --- */ + +#if (ULONG_MAX / 0xFUL > 0xFUL) +#ifndef I8T +#define I8T long +#define U8C(v) (v##UL) + +#if (ULONG_MAX == 0xFFUL) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (ULONG_MAX / 0xFFUL > 0xFFUL) +#ifndef I16T +#define I16T long +#define U16C(v) (v##UL) +#endif + +#if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL) +#ifndef I32T +#define I32T long +#define U32C(v) (v##UL) +#endif + +#if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL) +#ifndef I64T +#define I64T long +#define U64C(v) (v##UL) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check long long --- */ + +#ifdef ULLONG_MAX + +#if (ULLONG_MAX / 0xFULL > 0xFULL) +#ifndef I8T +#define I8T long long +#define U8C(v) (v##ULL) + +#if (ULLONG_MAX == 0xFFULL) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (ULLONG_MAX / 0xFFULL > 0xFFULL) +#ifndef I16T +#define I16T long long +#define U16C(v) (v##ULL) +#endif + +#if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL) +#ifndef I32T +#define I32T long long +#define U32C(v) (v##ULL) +#endif + +#if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL) +#ifndef I64T +#define I64T long long +#define U64C(v) (v##ULL) +#endif + +#endif +#endif +#endif +#endif + +#endif + +/* --- check __int64 --- */ + +#ifdef _UI64_MAX + +#if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64) +#ifndef I64T +#define I64T __int64 +#define U64C(v) (v##ui64) +#endif + +#endif + +#endif + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-machine.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-machine.h new file mode 100644 index 0000000..4d2a2e5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-machine.h @@ -0,0 +1,51 @@ +/****************************************************************************** +* Filename: sw_ecrypt-machine.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* ecrypt-machine.h */ + +/* + * This file is included by 'ecrypt-portable.h'. It allows to override + * the default macros for specific platforms. Please carefully check + * the machine code generated by your compiler (with optimisations + * turned on) before deciding to edit this file. + */ + +/* ------------------------------------------------------------------------- */ + +#if (defined(ECRYPT_DEFAULT_ROT) && !defined(ECRYPT_MACHINE_ROT)) + +#define ECRYPT_MACHINE_ROT + +#if (defined(WIN32) && defined(_MSC_VER)) + +#undef ROTL32 +#undef ROTR32 +#undef ROTL64 +#undef ROTR64 + +#include + +#define ROTL32(v, n) _lrotl(v, n) +#define ROTR32(v, n) _lrotr(v, n) +#define ROTL64(v, n) _rotl64(v, n) +#define ROTR64(v, n) _rotr64(v, n) + +#endif + +#endif + +/* ------------------------------------------------------------------------- */ + +#if (defined(ECRYPT_DEFAULT_SWAP) && !defined(ECRYPT_MACHINE_SWAP)) + +#define ECRYPT_MACHINE_SWAP + +/* + * If you want to overwrite the default swap macros, put it here. And so on. + */ + +#endif + +/* ------------------------------------------------------------------------- */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-portable.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-portable.h new file mode 100644 index 0000000..8ce940d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-portable.h @@ -0,0 +1,308 @@ +/****************************************************************************** +* Filename: sw_ecrypt-portable.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* ecrypt-portable.h */ + +/* + * WARNING: the conversions defined below are implemented as macros, + * and should be used carefully. They should NOT be used with + * parameters which perform some action. E.g., the following two lines + * are not equivalent: + * + * 1) ++x; y = ROTL32(x, n); + * 2) y = ROTL32(++x, n); + */ + +/* + * *** Please do not edit this file. *** + * + * The default macros can be overridden for specific architectures by + * editing 'ecrypt-machine.h'. + */ + +#ifndef ECRYPT_PORTABLE +#define ECRYPT_PORTABLE + +#include "sw_ecrypt-config.h" + +/* ------------------------------------------------------------------------- */ + +/* + * The following types are defined (if available): + * + * u8: unsigned integer type, at least 8 bits + * u16: unsigned integer type, at least 16 bits + * u32: unsigned integer type, at least 32 bits + * u64: unsigned integer type, at least 64 bits + * + * s8, s16, s32, s64 -> signed counterparts of u8, u16, u32, u64 + * + * The selection of minimum-width integer types is taken care of by + * 'ecrypt-config.h'. Note: to enable 64-bit types on 32-bit + * compilers, it might be necessary to switch from ISO C90 mode to ISO + * C99 mode (e.g., gcc -std=c99). + */ + +#ifdef I8T +typedef signed I8T s8; +typedef unsigned I8T u8; +#endif + +#ifdef I16T +typedef signed I16T s16; +typedef unsigned I16T u16; +#endif + +#ifdef I32T +typedef signed I32T s32; +typedef unsigned I32T u32; +#endif + +#ifdef I64T +typedef signed I64T s64; +typedef unsigned I64T u64; +#endif + +/* + * The following macros are used to obtain exact-width results. + */ + +#define U8V(v) ((u8)(v) & U8C(0xFF)) +#define U16V(v) ((u16)(v) & U16C(0xFFFF)) +#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF)) +#define U64V(v) ((u64)(v) & U64C(0xFFFFFFFFFFFFFFFF)) + +/* ------------------------------------------------------------------------- */ + +/* + * The following macros return words with their bits rotated over n + * positions to the left/right. + */ + +#define ECRYPT_DEFAULT_ROT + +#define ROTL8(v, n) \ + (U8V((v) << (n)) | ((v) >> (8 - (n)))) + +#define ROTL16(v, n) \ + (U16V((v) << (n)) | ((v) >> (16 - (n)))) + +#define ROTL32(v, n) \ + (U32V((v) << (n)) | ((v) >> (32 - (n)))) + +#define ROTL64(v, n) \ + (U64V((v) << (n)) | ((v) >> (64 - (n)))) + +#define ROTR8(v, n) ROTL8(v, 8 - (n)) +#define ROTR16(v, n) ROTL16(v, 16 - (n)) +#define ROTR32(v, n) ROTL32(v, 32 - (n)) +#define ROTR64(v, n) ROTL64(v, 64 - (n)) + +#include "sw_ecrypt-machine.h" + +/* ------------------------------------------------------------------------- */ + +/* + * The following macros return a word with bytes in reverse order. + */ + +#define ECRYPT_DEFAULT_SWAP + +#define SWAP16(v) \ + ROTL16(v, 8) + +#define SWAP32(v) \ + ((ROTL32(v, 8) & U32C(0x00FF00FF)) | \ + (ROTL32(v, 24) & U32C(0xFF00FF00))) + +#ifdef ECRYPT_NATIVE64 +#define SWAP64(v) \ + ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | \ + (ROTL64(v, 24) & U64C(0x0000FF000000FF00)) | \ + (ROTL64(v, 40) & U64C(0x00FF000000FF0000)) | \ + (ROTL64(v, 56) & U64C(0xFF000000FF000000))) +#else +#define SWAP64(v) \ + (((u64)SWAP32(U32V(v)) << 32) | (u64)SWAP32(U32V(v >> 32))) +#endif + +#include "sw_ecrypt-machine.h" + +#define ECRYPT_DEFAULT_WTOW + +#ifdef ECRYPT_LITTLE_ENDIAN +#define U16TO16_LITTLE(v) (v) +#define U32TO32_LITTLE(v) (v) +#define U64TO64_LITTLE(v) (v) + +#define U16TO16_BIG(v) SWAP16(v) +#define U32TO32_BIG(v) SWAP32(v) +#define U64TO64_BIG(v) SWAP64(v) +#endif + +#ifdef ECRYPT_BIG_ENDIAN +#define U16TO16_LITTLE(v) SWAP16(v) +#define U32TO32_LITTLE(v) SWAP32(v) +#define U64TO64_LITTLE(v) SWAP64(v) + +#define U16TO16_BIG(v) (v) +#define U32TO32_BIG(v) (v) +#define U64TO64_BIG(v) (v) +#endif + +#include "sw_ecrypt-machine.h" + +/* + * The following macros load words from an array of bytes with + * different types of endianness, and vice versa. + */ + +#define ECRYPT_DEFAULT_BTOW + +#if (!defined(ECRYPT_UNKNOWN) && defined(ECRYPT_I8T_IS_BYTE)) + +#define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16*)(p))[0]) +#define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32*)(p))[0]) +#define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64*)(p))[0]) + +#define U8TO16_BIG(p) U16TO16_BIG(((u16*)(p))[0]) +#define U8TO32_BIG(p) U32TO32_BIG(((u32*)(p))[0]) +#define U8TO64_BIG(p) U64TO64_BIG(((u64*)(p))[0]) + +#define U16TO8_LITTLE(p, v) (((u16*)(p))[0] = U16TO16_LITTLE(v)) +#define U32TO8_LITTLE(p, v) (((u32*)(p))[0] = U32TO32_LITTLE(v)) +#define U64TO8_LITTLE(p, v) (((u64*)(p))[0] = U64TO64_LITTLE(v)) + +#define U16TO8_BIG(p, v) (((u16*)(p))[0] = U16TO16_BIG(v)) +#define U32TO8_BIG(p, v) (((u32*)(p))[0] = U32TO32_BIG(v)) +#define U64TO8_BIG(p, v) (((u64*)(p))[0] = U64TO64_BIG(v)) + +#else + +#define U8TO16_LITTLE(p) \ + (((u16)((p)[0]) ) | \ + ((u16)((p)[1]) << 8)) + +#define U8TO32_LITTLE(p) \ + (((u32)((p)[0]) ) | \ + ((u32)((p)[1]) << 8) | \ + ((u32)((p)[2]) << 16) | \ + ((u32)((p)[3]) << 24)) + +#ifdef ECRYPT_NATIVE64 +#define U8TO64_LITTLE(p) \ + (((u64)((p)[0]) ) | \ + ((u64)((p)[1]) << 8) | \ + ((u64)((p)[2]) << 16) | \ + ((u64)((p)[3]) << 24) | \ + ((u64)((p)[4]) << 32) | \ + ((u64)((p)[5]) << 40) | \ + ((u64)((p)[6]) << 48) | \ + ((u64)((p)[7]) << 56)) +#else +#define U8TO64_LITTLE(p) \ + ((u64)U8TO32_LITTLE(p) | ((u64)U8TO32_LITTLE((p) + 4) << 32)) +#endif + +#define U8TO16_BIG(p) \ + (((u16)((p)[0]) << 8) | \ + ((u16)((p)[1]) )) + +#define U8TO32_BIG(p) \ + (((u32)((p)[0]) << 24) | \ + ((u32)((p)[1]) << 16) | \ + ((u32)((p)[2]) << 8) | \ + ((u32)((p)[3]) )) + +#ifdef ECRYPT_NATIVE64 +#define U8TO64_BIG(p) \ + (((u64)((p)[0]) << 56) | \ + ((u64)((p)[1]) << 48) | \ + ((u64)((p)[2]) << 40) | \ + ((u64)((p)[3]) << 32) | \ + ((u64)((p)[4]) << 24) | \ + ((u64)((p)[5]) << 16) | \ + ((u64)((p)[6]) << 8) | \ + ((u64)((p)[7]) )) +#else +#define U8TO64_BIG(p) \ + (((u64)U8TO32_BIG(p) << 32) | (u64)U8TO32_BIG((p) + 4)) +#endif + +#define U16TO8_LITTLE(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + } while (0) + +#define U32TO8_LITTLE(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + (p)[2] = U8V((v) >> 16); \ + (p)[3] = U8V((v) >> 24); \ + } while (0) + +#ifdef ECRYPT_NATIVE64 +#define U64TO8_LITTLE(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + (p)[2] = U8V((v) >> 16); \ + (p)[3] = U8V((v) >> 24); \ + (p)[4] = U8V((v) >> 32); \ + (p)[5] = U8V((v) >> 40); \ + (p)[6] = U8V((v) >> 48); \ + (p)[7] = U8V((v) >> 56); \ + } while (0) +#else +#define U64TO8_LITTLE(p, v) \ + do { \ + U32TO8_LITTLE((p), U32V((v) )); \ + U32TO8_LITTLE((p) + 4, U32V((v) >> 32)); \ + } while (0) +#endif + +#define U16TO8_BIG(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + } while (0) + +#define U32TO8_BIG(p, v) \ + do { \ + (p)[0] = U8V((v) >> 24); \ + (p)[1] = U8V((v) >> 16); \ + (p)[2] = U8V((v) >> 8); \ + (p)[3] = U8V((v) ); \ + } while (0) + +#ifdef ECRYPT_NATIVE64 +#define U64TO8_BIG(p, v) \ + do { \ + (p)[0] = U8V((v) >> 56); \ + (p)[1] = U8V((v) >> 48); \ + (p)[2] = U8V((v) >> 40); \ + (p)[3] = U8V((v) >> 32); \ + (p)[4] = U8V((v) >> 24); \ + (p)[5] = U8V((v) >> 16); \ + (p)[6] = U8V((v) >> 8); \ + (p)[7] = U8V((v) ); \ + } while (0) +#else +#define U64TO8_BIG(p, v) \ + do { \ + U32TO8_BIG((p), U32V((v) >> 32)); \ + U32TO8_BIG((p) + 4, U32V((v) )); \ + } while (0) +#endif + +#endif + +#include "sw_ecrypt-machine.h" + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h new file mode 100644 index 0000000..dddb384 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h @@ -0,0 +1,284 @@ +/****************************************************************************** +* Filename: sw_ecrypt-sync.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* ecrypt-sync.h */ + +/* + * Header file for synchronous stream ciphers without authentication + * mechanism. + * + * *** Please only edit parts marked with "[edit]". *** + */ + +#ifndef ECRYPT_SYNC +#define ECRYPT_SYNC + +#include "sw_ecrypt-portable.h" + +/* ------------------------------------------------------------------------- */ + +/* Cipher parameters */ + +/* + * The name of your cipher. + */ +#define ECRYPT_NAME "ChaCha8" +#define ECRYPT_PROFILE "_____" + +/* + * Specify which key and IV sizes are supported by your cipher. A user + * should be able to enumerate the supported sizes by running the + * following code: + * + * for (i = 0; ECRYPT_KEYSIZE(i) <= ECRYPT_MAXKEYSIZE; ++i) + * { + * keysize = ECRYPT_KEYSIZE(i); + * + * ... + * } + * + * All sizes are in bits. + */ + +#define ECRYPT_MAXKEYSIZE 256 /* [edit] */ +#define ECRYPT_KEYSIZE(i) (128 + (i)*128) /* [edit] */ + +#define ECRYPT_MAXIVSIZE 64 /* [edit] */ +#define ECRYPT_IVSIZE(i) (64 + (i)*64) /* [edit] */ + +/* ------------------------------------------------------------------------- */ + +/* Data structures */ + +/* + * ECRYPT_ctx is the structure containing the representation of the + * internal state of your cipher. + */ + +typedef struct +{ + u32 input[16]; /* could be compressed */ + /* + * [edit] + * + * Put here all state variable needed during the encryption process. + */ +} ECRYPT_ctx; + +/* ------------------------------------------------------------------------- */ + +/* Mandatory functions */ + +/* + * Key and message independent initialization. This function will be + * called once when the program starts (e.g., to build expanded S-box + * tables). + */ +void ECRYPT_init(void); + +/* + * Key setup. It is the user's responsibility to select the values of + * keysize and ivsize from the set of supported values specified + * above. + */ +void ECRYPT_keysetup( + ECRYPT_ctx* ctx, + const u8* key, + u32 keysize, /* Key size in bits. */ + u32 ivsize); /* IV size in bits. */ + +/* + * IV setup. After having called ECRYPT_keysetup(), the user is + * allowed to call ECRYPT_ivsetup() different times in order to + * encrypt/decrypt different messages with the same key but different + * IV's. + */ +void ECRYPT_ivsetup( + ECRYPT_ctx* ctx, + const u8* iv); + +/* + * Encryption/decryption of arbitrary length messages. + * + * For efficiency reasons, the API provides two types of + * encrypt/decrypt functions. The ECRYPT_encrypt_bytes() function + * (declared here) encrypts byte strings of arbitrary length, while + * the ECRYPT_encrypt_blocks() function (defined later) only accepts + * lengths which are multiples of ECRYPT_BLOCKLENGTH. + * + * The user is allowed to make multiple calls to + * ECRYPT_encrypt_blocks() to incrementally encrypt a long message, + * but he is NOT allowed to make additional encryption calls once he + * has called ECRYPT_encrypt_bytes() (unless he starts a new message + * of course). For example, this sequence of calls is acceptable: + * + * ECRYPT_keysetup(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_bytes(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_blocks(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_bytes(); + * + * The following sequence is not: + * + * ECRYPT_keysetup(); + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_bytes(); + * ECRYPT_encrypt_blocks(); + */ + +void ECRYPT_encrypt_bytes( + ECRYPT_ctx* ctx, + const u8* plaintext, + u8* ciphertext, + u32 msglen); /* Message length in bytes. */ + +void ECRYPT_decrypt_bytes( + ECRYPT_ctx* ctx, + const u8* ciphertext, + u8* plaintext, + u32 msglen); /* Message length in bytes. */ + +/* ------------------------------------------------------------------------- */ + +/* Optional features */ + +/* + * For testing purposes it can sometimes be useful to have a function + * which immediately generates keystream without having to provide it + * with a zero plaintext. If your cipher cannot provide this function + * (e.g., because it is not strictly a synchronous cipher), please + * reset the ECRYPT_GENERATES_KEYSTREAM flag. + */ + +#define ECRYPT_GENERATES_KEYSTREAM +#ifdef ECRYPT_GENERATES_KEYSTREAM + +void ECRYPT_keystream_bytes( + ECRYPT_ctx* ctx, + u8* keystream, + u32 length); /* Length of keystream in bytes. */ + +#endif + +/* ------------------------------------------------------------------------- */ + +/* Optional optimizations */ + +/* + * By default, the functions in this section are implemented using + * calls to functions declared above. However, you might want to + * implement them differently for performance reasons. + */ + +/* + * All-in-one encryption/decryption of (short) packets. + * + * The default definitions of these functions can be found in + * "ecrypt-sync.c". If you want to implement them differently, please + * undef the ECRYPT_USES_DEFAULT_ALL_IN_ONE flag. + */ +#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */ + +void ECRYPT_encrypt_packet( + ECRYPT_ctx* ctx, + const u8* iv, + const u8* plaintext, + u8* ciphertext, + u32 msglen); + +void ECRYPT_decrypt_packet( + ECRYPT_ctx* ctx, + const u8* iv, + const u8* ciphertext, + u8* plaintext, + u32 msglen); + +/* + * Encryption/decryption of blocks. + * + * By default, these functions are defined as macros. If you want to + * provide a different implementation, please undef the + * ECRYPT_USES_DEFAULT_BLOCK_MACROS flag and implement the functions + * declared below. + */ + +#define ECRYPT_BLOCKLENGTH 64 /* [edit] */ + +#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */ +#ifdef ECRYPT_USES_DEFAULT_BLOCK_MACROS + +#define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \ + ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, \ + (blocks) * ECRYPT_BLOCKLENGTH) + +#define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \ + ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, \ + (blocks) * ECRYPT_BLOCKLENGTH) + +#ifdef ECRYPT_GENERATES_KEYSTREAM + +#define ECRYPT_keystream_blocks(ctx, keystream, blocks) \ + ECRYPT_keystream_bytes(ctx, keystream, \ + (blocks) * ECRYPT_BLOCKLENGTH) + +#endif + +#else + +void ECRYPT_encrypt_blocks( + ECRYPT_ctx* ctx, + const u8* plaintext, + u8* ciphertext, + u32 blocks); /* Message length in blocks. */ + +void ECRYPT_decrypt_blocks( + ECRYPT_ctx* ctx, + const u8* ciphertext, + u8* plaintext, + u32 blocks); /* Message length in blocks. */ + +#ifdef ECRYPT_GENERATES_KEYSTREAM + +void ECRYPT_keystream_blocks( + ECRYPT_ctx* ctx, + const u8* keystream, + u32 blocks); /* Keystream length in blocks. */ + +#endif + +#endif + +/* + * If your cipher can be implemented in different ways, you can use + * the ECRYPT_VARIANT parameter to allow the user to choose between + * them at compile time (e.g., gcc -DECRYPT_VARIANT=3 ...). Please + * only use this possibility if you really think it could make a + * significant difference and keep the number of variants + * (ECRYPT_MAXVARIANT) as small as possible (definitely not more than + * 10). Note also that all variants should have exactly the same + * external interface (i.e., the same ECRYPT_BLOCKLENGTH, etc.). + */ +#define ECRYPT_MAXVARIANT 1 /* [edit] */ + +#ifndef ECRYPT_VARIANT +#define ECRYPT_VARIANT 1 +#endif + +#if (ECRYPT_VARIANT > ECRYPT_MAXVARIANT) +#error this variant does not exist +#endif + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna-32.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna-32.h new file mode 100644 index 0000000..2aa2eeb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna-32.h @@ -0,0 +1,223 @@ +/****************************************************************************** +* Filename: sw_poly1305-donna-32.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* + poly1305 implementation using 32 bit * 32 bit = 64 bit multiplication and 64 bit addition +*/ + +#if defined(_MSC_VER) + #define POLY1305_NOINLINE __declspec(noinline) +#elif defined(__GNUC__) + #define POLY1305_NOINLINE __attribute__((noinline)) +#else + #define POLY1305_NOINLINE +#endif + +#define poly1305_block_size 16 + +/* 17 + sizeof(size_t) + 14*sizeof(unsigned long) */ +typedef struct { + unsigned long r[5]; + unsigned long h[5]; + unsigned long pad[4]; + size_t leftover; + unsigned char buffer[poly1305_block_size]; + unsigned char final; +} poly1305_state_internal_t; + +/* interpret four 8 bit unsigned integers as a 32 bit unsigned integer in little endian */ +static unsigned long +U8TO32(const unsigned char *p) { + return + (((unsigned long)(p[0] & 0xff) ) | + ((unsigned long)(p[1] & 0xff) << 8) | + ((unsigned long)(p[2] & 0xff) << 16) | + ((unsigned long)(p[3] & 0xff) << 24)); +} + +/* store a 32 bit unsigned integer as four 8 bit unsigned integers in little endian */ +static void +U32TO8(unsigned char *p, unsigned long v) { + p[0] = (v ) & 0xff; + p[1] = (v >> 8) & 0xff; + p[2] = (v >> 16) & 0xff; + p[3] = (v >> 24) & 0xff; +} + +void +poly1305_init(poly1305_context *ctx, const unsigned char key[32]) { + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + + /* r &= 0xffffffc0ffffffc0ffffffc0fffffff */ + st->r[0] = (U8TO32(&key[ 0]) ) & 0x3ffffff; + st->r[1] = (U8TO32(&key[ 3]) >> 2) & 0x3ffff03; + st->r[2] = (U8TO32(&key[ 6]) >> 4) & 0x3ffc0ff; + st->r[3] = (U8TO32(&key[ 9]) >> 6) & 0x3f03fff; + st->r[4] = (U8TO32(&key[12]) >> 8) & 0x00fffff; + + /* h = 0 */ + st->h[0] = 0; + st->h[1] = 0; + st->h[2] = 0; + st->h[3] = 0; + st->h[4] = 0; + + /* save pad for later */ + st->pad[0] = U8TO32(&key[16]); + st->pad[1] = U8TO32(&key[20]); + st->pad[2] = U8TO32(&key[24]); + st->pad[3] = U8TO32(&key[28]); + + st->leftover = 0; + st->final = 0; +} + +static void +poly1305_blocks(poly1305_state_internal_t *st, const unsigned char *m, size_t bytes) { + const unsigned long hibit = (st->final) ? 0 : (1UL << 24); /* 1 << 128 */ + unsigned long r0,r1,r2,r3,r4; + unsigned long s1,s2,s3,s4; + unsigned long h0,h1,h2,h3,h4; + unsigned long long d0,d1,d2,d3,d4; + unsigned long c; + + r0 = st->r[0]; + r1 = st->r[1]; + r2 = st->r[2]; + r3 = st->r[3]; + r4 = st->r[4]; + + s1 = r1 * 5; + s2 = r2 * 5; + s3 = r3 * 5; + s4 = r4 * 5; + + h0 = st->h[0]; + h1 = st->h[1]; + h2 = st->h[2]; + h3 = st->h[3]; + h4 = st->h[4]; + + while (bytes >= poly1305_block_size) { + /* h += m[i] */ + h0 += (U8TO32(m+ 0) ) & 0x3ffffff; + h1 += (U8TO32(m+ 3) >> 2) & 0x3ffffff; + h2 += (U8TO32(m+ 6) >> 4) & 0x3ffffff; + h3 += (U8TO32(m+ 9) >> 6) & 0x3ffffff; + h4 += (U8TO32(m+12) >> 8) | hibit; + + /* h *= r */ + d0 = ((unsigned long long)h0 * r0) + ((unsigned long long)h1 * s4) + ((unsigned long long)h2 * s3) + ((unsigned long long)h3 * s2) + ((unsigned long long)h4 * s1); + d1 = ((unsigned long long)h0 * r1) + ((unsigned long long)h1 * r0) + ((unsigned long long)h2 * s4) + ((unsigned long long)h3 * s3) + ((unsigned long long)h4 * s2); + d2 = ((unsigned long long)h0 * r2) + ((unsigned long long)h1 * r1) + ((unsigned long long)h2 * r0) + ((unsigned long long)h3 * s4) + ((unsigned long long)h4 * s3); + d3 = ((unsigned long long)h0 * r3) + ((unsigned long long)h1 * r2) + ((unsigned long long)h2 * r1) + ((unsigned long long)h3 * r0) + ((unsigned long long)h4 * s4); + d4 = ((unsigned long long)h0 * r4) + ((unsigned long long)h1 * r3) + ((unsigned long long)h2 * r2) + ((unsigned long long)h3 * r1) + ((unsigned long long)h4 * r0); + + /* (partial) h %= p */ + c = (unsigned long)(d0 >> 26); h0 = (unsigned long)d0 & 0x3ffffff; + d1 += c; c = (unsigned long)(d1 >> 26); h1 = (unsigned long)d1 & 0x3ffffff; + d2 += c; c = (unsigned long)(d2 >> 26); h2 = (unsigned long)d2 & 0x3ffffff; + d3 += c; c = (unsigned long)(d3 >> 26); h3 = (unsigned long)d3 & 0x3ffffff; + d4 += c; c = (unsigned long)(d4 >> 26); h4 = (unsigned long)d4 & 0x3ffffff; + h0 += c * 5; c = (h0 >> 26); h0 = h0 & 0x3ffffff; + h1 += c; + + m += poly1305_block_size; + bytes -= poly1305_block_size; + } + + st->h[0] = h0; + st->h[1] = h1; + st->h[2] = h2; + st->h[3] = h3; + st->h[4] = h4; +} + +POLY1305_NOINLINE void +poly1305_finish(poly1305_context *ctx, unsigned char mac[16]) { + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + unsigned long h0,h1,h2,h3,h4,c; + unsigned long g0,g1,g2,g3,g4; + unsigned long long f; + unsigned long mask; + + /* process the remaining block */ + if (st->leftover) { + size_t i = st->leftover; + st->buffer[i++] = 1; + for (; i < poly1305_block_size; i++) + st->buffer[i] = 0; + st->final = 1; + poly1305_blocks(st, st->buffer, poly1305_block_size); + } + + /* fully carry h */ + h0 = st->h[0]; + h1 = st->h[1]; + h2 = st->h[2]; + h3 = st->h[3]; + h4 = st->h[4]; + + c = h1 >> 26; h1 = h1 & 0x3ffffff; + h2 += c; c = h2 >> 26; h2 = h2 & 0x3ffffff; + h3 += c; c = h3 >> 26; h3 = h3 & 0x3ffffff; + h4 += c; c = h4 >> 26; h4 = h4 & 0x3ffffff; + h0 += c * 5; c = h0 >> 26; h0 = h0 & 0x3ffffff; + h1 += c; + + /* compute h + -p */ + g0 = h0 + 5; c = g0 >> 26; g0 &= 0x3ffffff; + g1 = h1 + c; c = g1 >> 26; g1 &= 0x3ffffff; + g2 = h2 + c; c = g2 >> 26; g2 &= 0x3ffffff; + g3 = h3 + c; c = g3 >> 26; g3 &= 0x3ffffff; + g4 = h4 + c - (1UL << 26); + + /* select h if h < p, or h + -p if h >= p */ + mask = (g4 >> ((sizeof(unsigned long) * 8) - 1)) - 1; + g0 &= mask; + g1 &= mask; + g2 &= mask; + g3 &= mask; + g4 &= mask; + mask = ~mask; + h0 = (h0 & mask) | g0; + h1 = (h1 & mask) | g1; + h2 = (h2 & mask) | g2; + h3 = (h3 & mask) | g3; + h4 = (h4 & mask) | g4; + + /* h = h % (2^128) */ + h0 = ((h0 ) | (h1 << 26)) & 0xffffffff; + h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff; + h2 = ((h2 >> 12) | (h3 << 14)) & 0xffffffff; + h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff; + + /* mac = (h + pad) % (2^128) */ + f = (unsigned long long)h0 + st->pad[0] ; h0 = (unsigned long)f; + f = (unsigned long long)h1 + st->pad[1] + (f >> 32); h1 = (unsigned long)f; + f = (unsigned long long)h2 + st->pad[2] + (f >> 32); h2 = (unsigned long)f; + f = (unsigned long long)h3 + st->pad[3] + (f >> 32); h3 = (unsigned long)f; + + U32TO8(mac + 0, h0); + U32TO8(mac + 4, h1); + U32TO8(mac + 8, h2); + U32TO8(mac + 12, h3); + + /* zero out the state */ + st->h[0] = 0; + st->h[1] = 0; + st->h[2] = 0; + st->h[3] = 0; + st->h[4] = 0; + st->r[0] = 0; + st->r[1] = 0; + st->r[2] = 0; + st->r[3] = 0; + st->r[4] = 0; + st->pad[0] = 0; + st->pad[1] = 0; + st->pad[2] = 0; + st->pad[3] = 0; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.c new file mode 100644 index 0000000..2c1680e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.c @@ -0,0 +1,186 @@ +/****************************************************************************** +* Filename: sw_poly1305-donna.c +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ + +#include "sw_poly1305-donna.h" + +#include "sw_poly1305-donna-32.h" + +void +poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes) { + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + size_t i; + + /* handle leftover */ + if (st->leftover) { + size_t want = (poly1305_block_size - st->leftover); + if (want > bytes) + want = bytes; + for (i = 0; i < want; i++) + st->buffer[st->leftover + i] = m[i]; + bytes -= want; + m += want; + st->leftover += want; + if (st->leftover < poly1305_block_size) + return; + poly1305_blocks(st, st->buffer, poly1305_block_size); + st->leftover = 0; + } + + /* process full blocks */ + if (bytes >= poly1305_block_size) { + size_t want = (bytes & ~(poly1305_block_size - 1)); + poly1305_blocks(st, m, want); + m += want; + bytes -= want; + } + + /* store leftover */ + if (bytes) { + for (i = 0; i < bytes; i++) + st->buffer[st->leftover + i] = m[i]; + st->leftover += bytes; + } +} + +void +poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]) { + poly1305_context ctx; + poly1305_init(&ctx, key); + poly1305_update(&ctx, m, bytes); + poly1305_finish(&ctx, mac); +} + +int +poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]) { + size_t i; + unsigned int dif = 0; + for (i = 0; i < 16; i++) + dif |= (mac1[i] ^ mac2[i]); + dif = (dif - 1) >> ((sizeof(unsigned int) * 8) - 1); + return (dif & 1); +} + + +/* test a few basic operations */ +int +poly1305_power_on_self_test(void) { + /* example from nacl */ + static const unsigned char nacl_key[32] = { + 0xee,0xa6,0xa7,0x25,0x1c,0x1e,0x72,0x91, + 0x6d,0x11,0xc2,0xcb,0x21,0x4d,0x3c,0x25, + 0x25,0x39,0x12,0x1d,0x8e,0x23,0x4e,0x65, + 0x2d,0x65,0x1f,0xa4,0xc8,0xcf,0xf8,0x80 + }; + + static const unsigned char nacl_msg[131] = { + 0x8e,0x99,0x3b,0x9f,0x48,0x68,0x12,0x73, + 0xc2,0x96,0x50,0xba,0x32,0xfc,0x76,0xce, + 0x48,0x33,0x2e,0xa7,0x16,0x4d,0x96,0xa4, + 0x47,0x6f,0xb8,0xc5,0x31,0xa1,0x18,0x6a, + 0xc0,0xdf,0xc1,0x7c,0x98,0xdc,0xe8,0x7b, + 0x4d,0xa7,0xf0,0x11,0xec,0x48,0xc9,0x72, + 0x71,0xd2,0xc2,0x0f,0x9b,0x92,0x8f,0xe2, + 0x27,0x0d,0x6f,0xb8,0x63,0xd5,0x17,0x38, + 0xb4,0x8e,0xee,0xe3,0x14,0xa7,0xcc,0x8a, + 0xb9,0x32,0x16,0x45,0x48,0xe5,0x26,0xae, + 0x90,0x22,0x43,0x68,0x51,0x7a,0xcf,0xea, + 0xbd,0x6b,0xb3,0x73,0x2b,0xc0,0xe9,0xda, + 0x99,0x83,0x2b,0x61,0xca,0x01,0xb6,0xde, + 0x56,0x24,0x4a,0x9e,0x88,0xd5,0xf9,0xb3, + 0x79,0x73,0xf6,0x22,0xa4,0x3d,0x14,0xa6, + 0x59,0x9b,0x1f,0x65,0x4c,0xb4,0x5a,0x74, + 0xe3,0x55,0xa5 + }; + + static const unsigned char nacl_mac[16] = { + 0xf3,0xff,0xc7,0x70,0x3f,0x94,0x00,0xe5, + 0x2a,0x7d,0xfb,0x4b,0x3d,0x33,0x05,0xd9 + }; + + /* generates a final value of (2^130 - 2) == 3 */ + static const unsigned char wrap_key[32] = { + 0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + }; + + static const unsigned char wrap_msg[16] = { + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff + }; + + static const unsigned char wrap_mac[16] = { + 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + }; + + /* + mac of the macs of messages of length 0 to 256, where the key and messages + have all their values set to the length + */ + static const unsigned char total_key[32] = { + 0x01,0x02,0x03,0x04,0x05,0x06,0x07, + 0xff,0xfe,0xfd,0xfc,0xfb,0xfa,0xf9, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff + }; + + static const unsigned char total_mac[16] = { + 0x64,0xaf,0xe2,0xe8,0xd6,0xad,0x7b,0xbd, + 0xd2,0x87,0xf9,0x7c,0x44,0x62,0x3d,0x39 + }; + + poly1305_context ctx; + poly1305_context total_ctx; + unsigned char all_key[32]; + unsigned char all_msg[256]; + unsigned char mac[16]; + size_t i, j; + int result = 1; + + for (i = 0; i < sizeof(mac); i++) + mac[i] = 0; + poly1305_auth(mac, nacl_msg, sizeof(nacl_msg), nacl_key); + result &= poly1305_verify(nacl_mac, mac); + + for (i = 0; i < sizeof(mac); i++) + mac[i] = 0; + poly1305_init(&ctx, nacl_key); + poly1305_update(&ctx, nacl_msg + 0, 32); + poly1305_update(&ctx, nacl_msg + 32, 64); + poly1305_update(&ctx, nacl_msg + 96, 16); + poly1305_update(&ctx, nacl_msg + 112, 8); + poly1305_update(&ctx, nacl_msg + 120, 4); + poly1305_update(&ctx, nacl_msg + 124, 2); + poly1305_update(&ctx, nacl_msg + 126, 1); + poly1305_update(&ctx, nacl_msg + 127, 1); + poly1305_update(&ctx, nacl_msg + 128, 1); + poly1305_update(&ctx, nacl_msg + 129, 1); + poly1305_update(&ctx, nacl_msg + 130, 1); + poly1305_finish(&ctx, mac); + result &= poly1305_verify(nacl_mac, mac); + + for (i = 0; i < sizeof(mac); i++) + mac[i] = 0; + poly1305_auth(mac, wrap_msg, sizeof(wrap_msg), wrap_key); + result &= poly1305_verify(wrap_mac, mac); + + poly1305_init(&total_ctx, total_key); + for (i = 0; i < 256; i++) { + /* set key and message to 'i,i,i..' */ + for (j = 0; j < sizeof(all_key); j++) + all_key[j] = i; + for (j = 0; j < i; j++) + all_msg[j] = i; + poly1305_auth(mac, all_msg, i, all_key); + poly1305_update(&total_ctx, mac, 16); + } + poly1305_finish(&total_ctx, mac); + result &= poly1305_verify(total_mac, mac); + + return result; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.h new file mode 100644 index 0000000..574efab --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.h @@ -0,0 +1,25 @@ +/****************************************************************************** +* Filename: sw_poly1305-donna.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ + +#ifndef POLY1305_DONNA_H +#define POLY1305_DONNA_H + +#include + +typedef struct { + size_t aligner; + unsigned char opaque[136]; +} poly1305_context; + +void poly1305_init(poly1305_context *ctx, const unsigned char key[32]); +void poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes); +void poly1305_finish(poly1305_context *ctx, unsigned char mac[16]); +void poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]); + +int poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]); +int poly1305_power_on_self_test(void); + +#endif /* POLY1305_DONNA_H */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c new file mode 100644 index 0000000..5f52764 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c @@ -0,0 +1,375 @@ +/****************************************************************************** +* Filename: sys_ctrl.c +* Revised: 2018-06-26 15:19:11 +0200 (Tue, 26 Jun 2018) +* Revision: 52220 +* +* Description: Driver for the System Control. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +// Hardware headers +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ioc.h" +// Driverlib headers +#include "aon_batmon.h" +#include "flash.h" +#include "gpio.h" +#include "setup_rom.h" +#include "sys_ctrl.h" + + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SysCtrlIdle + #define SysCtrlIdle NOROM_SysCtrlIdle + #undef SysCtrlShutdownWithAbort + #define SysCtrlShutdownWithAbort NOROM_SysCtrlShutdownWithAbort + #undef SysCtrlShutdown + #define SysCtrlShutdown NOROM_SysCtrlShutdown + #undef SysCtrlStandby + #define SysCtrlStandby NOROM_SysCtrlStandby + #undef SysCtrlSetRechargeBeforePowerDown + #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown + #undef SysCtrlAdjustRechargeAfterPowerDown + #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown + #undef SysCtrl_DCDC_VoltageConditionalControl + #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl + #undef SysCtrlResetSourceGet + #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet +#endif + + + +//***************************************************************************** +// +// Force the system in to idle mode +// +//***************************************************************************** +void SysCtrlIdle(uint32_t vimsPdMode) +{ + // Configure the VIMS mode + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) = vimsPdMode; + + // Always keep cache retention ON in IDLE + PRCMCacheRetentionEnable(); + + // Turn off the CPU power domain, will take effect when PRCMDeepSleep() executes + PRCMPowerDomainOff(PRCM_DOMAIN_CPU); + + // Ensure any possible outstanding AON writes complete + SysCtrlAonSync(); + + // Invoke deep sleep to go to IDLE + PRCMDeepSleep(); +} + +//***************************************************************************** +// +// Try to enter shutdown but abort if wakeup event happened before shutdown +// +//***************************************************************************** +void SysCtrlShutdownWithAbort(void) +{ + uint32_t wu_detect_vector = 0; + uint32_t io_num = 0; + + // For all IO CFG registers check if wakeup detect is enabled + for(io_num = 0; io_num < 32; io_num++) + { + // Read MSB from WU_CFG bit field + if( HWREG(IOC_BASE + IOC_O_IOCFG0 + (io_num * 4) ) & (1 << (IOC_IOCFG0_WU_CFG_S + IOC_IOCFG0_WU_CFG_W - 1)) ) + { + wu_detect_vector |= (1 << io_num); + } + } + + // Wakeup events are detected when pads are in sleep mode + PowerCtrlPadSleepEnable(); + + // Make sure all potential events have propagated before checking event flags + SysCtrlAonUpdate(); + SysCtrlAonUpdate(); + + // If no edge detect flags for wakeup enabled IOs are set then shut down the device + if( GPIO_getEventMultiDio(wu_detect_vector) == 0 ) + { + SysCtrlShutdown(); + } + else + { + PowerCtrlPadSleepDisable(); + } +} + +//***************************************************************************** +// +// Force the system into shutdown mode +// +//***************************************************************************** +void SysCtrlShutdown(void) +{ + // Request shutdown mode + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SHUTDOWN) = AON_PMCTL_SHUTDOWN_EN; + + // Make sure System CPU does not continue beyond this point. + // Shutdown happens when all shutdown conditions are met. + while(1); +} + +//***************************************************************************** +// +// Force the system in to standby mode +// +//***************************************************************************** +void SysCtrlStandby(bool retainCache, uint32_t vimsPdMode, uint32_t rechargeMode) +{ + uint32_t modeVIMS; + + // Freeze the IOs on the boundary between MCU and AON + AONIOCFreezeEnable(); + + // Ensure any possible outstanding AON writes complete before turning off the power domains + SysCtrlAonSync(); + + // Request power off of domains in the MCU voltage domain + PRCMPowerDomainOff(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL | PRCM_DOMAIN_PERIPH | PRCM_DOMAIN_CPU); + + // Ensure that no clocks are forced on in any modes for Crypto, DMA and I2S + HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) &= (~PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN & ~PRCM_SECDMACLKGR_DMA_AM_CLK_EN); + HWREG(PRCM_BASE + PRCM_O_I2SCLKGR) &= ~PRCM_I2SCLKGR_AM_CLK_EN; + + // Gate running deep sleep clocks for Crypto, DMA and I2S + PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_CRYPTO); + PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_UDMA); + PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_I2S); + + // Load the new clock settings + PRCMLoadSet(); + + // Configure the VIMS power domain mode + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) = vimsPdMode; + + // Request uLDO during standby + PRCMMcuUldoConfigure(1); + + // Check the regulator mode + if (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & AON_PMCTL_PWRCTL_EXT_REG_MODE) + { + // In external regulator mode the recharge functionality is disabled + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = 0x00000000; + } + else + { + // In internal regulator mode the recharge functionality is set up with + // adaptive recharge mode and fixed parameter values + if(rechargeMode == SYSCTRL_PREFERRED_RECHARGE_MODE) + { + // Enable the Recharge Comparator + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = AON_PMCTL_RECHARGECFG_MODE_COMPARATOR; + } + else + { + // Set requested recharge mode + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = rechargeMode; + } + } + + // Ensure all writes have taken effect + SysCtrlAonSync(); + + // Ensure UDMA, Crypto and I2C clocks are turned off + while (!PRCMLoadGet()) {;} + + // Ensure power domains have been turned off. + // CPU power domain will power down when PRCMDeepSleep() executes. + while (PRCMPowerDomainStatus(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL | PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_OFF) {;} + + // Turn off cache retention if requested + if (retainCache == false) { + + // Get the current VIMS mode + do { + modeVIMS = VIMSModeGet(VIMS_BASE); + } while (modeVIMS == VIMS_MODE_CHANGING); + + // If in a cache mode, turn VIMS off + if (modeVIMS == VIMS_MODE_ENABLED) { + VIMSModeSet(VIMS_BASE, VIMS_MODE_OFF); + } + + // Disable retention of cache RAM + PRCMCacheRetentionDisable(); + } + + // Invoke deep sleep to go to STANDBY + PRCMDeepSleep(); +} + +//***************************************************************************** +// +// SysCtrlSetRechargeBeforePowerDown( xoscPowerMode ) +// +//***************************************************************************** +void +SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ) +{ + uint32_t ccfg_ModeConfReg ; + + // read the MODE_CONF register in CCFG + ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + // Do temperature compensation if enabled + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC ) == 0 ) { + int32_t vddrSleepDelta ; + int32_t curTemp ; + int32_t tcDelta ; + int32_t vddrSleepTrim ; + + // Get VDDR_TRIM_SLEEP_DELTA + 1 (sign extended) ==> vddrSleepDelta = -7..+8 + vddrSleepDelta = (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ))) + >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W )) + 1 ; + curTemp = AONBatMonTemperatureGetDegC(); + tcDelta = ( 62 - curTemp ) >> 3; + if ( tcDelta > 7 ) { + tcDelta = 7 ; + } + if ( tcDelta > vddrSleepDelta ) { + vddrSleepDelta = tcDelta ; + } + vddrSleepTrim = (( HWREG( FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_MISC_TRIM ) & FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_M ) >> + FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_S ) ; + vddrSleepTrim -= vddrSleepDelta ; + if ( vddrSleepTrim > 15 ) vddrSleepTrim = 15 ; + if ( vddrSleepTrim < 1 ) vddrSleepTrim = 1 ; + // Write adjusted value using MASKED write (MASK8) + HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 * 2 )) = (( ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_M << 4 ) | + (( vddrSleepTrim << ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_S ) & ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_M ) ); + // Make a dummy read in order to make sure the write above is done before going into standby + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 ); + } +} + + +//***************************************************************************** +// +// SysCtrlAdjustRechargeAfterPowerDown() +// +//***************************************************************************** +void +SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ) +{ + // Nothing to be done but keeping this function for platform compatibility. +} + + +//***************************************************************************** +// +// SysCtrl_DCDC_VoltageConditionalControl() +// +//***************************************************************************** +void +SysCtrl_DCDC_VoltageConditionalControl( void ) +{ + uint32_t batThreshold ; // Fractional format with 8 fractional bits. + uint32_t aonBatmonBat ; // Fractional format with 8 fractional bits. + uint32_t ccfg_ModeConfReg ; // Holds a copy of the CCFG_O_MODE_CONF register. + uint32_t aonPmctlPwrctl ; // Reflect whats read/written to the AON_PMCTL_O_PWRCTL register. + + // We could potentially call this function before any battery voltage measurement + // is made/available. In that case we must make sure that we do not turn off the DCDC. + // This can be done by doing nothing as long as the battery voltage is 0 (Since the + // reset value of the battery voltage register is 0). + aonBatmonBat = HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT ); + if ( aonBatmonBat != 0 ) { + // Check if Voltage Conditional Control is enabled + // It is enabled if all the following are true: + // - DCDC in use (either in active or recharge mode), (in use if one of the corresponding CCFG bits are zero). + // - Alternative DCDC settings are enabled ( DIS_ALT_DCDC_SETTING == 0 ) + // - Not in external regulator mode ( EXT_REG_MODE == 0 ) + ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + + if (((( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) || + (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) ) && + (( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) == 0 ) && + (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) ) + { + aonPmctlPwrctl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ); + batThreshold = (((( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & + CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) >> + CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) + 28 ) << 4 ); + + if ( aonPmctlPwrctl & ( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M )) { + // DCDC is ON, check if it should be switched off + if ( aonBatmonBat < batThreshold ) { + aonPmctlPwrctl &= ~( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M ); + + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl; + } + } else { + // DCDC is OFF, check if it should be switched on + if ( aonBatmonBat > batThreshold ) { + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_EN_M ; + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_ACTIVE_M ; + + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl; + } + } + } + } +} + + +//***************************************************************************** +// +// SysCtrlResetSourceGet() +// +//***************************************************************************** +uint32_t +SysCtrlResetSourceGet( void ) +{ + uint32_t aonPmctlResetCtl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ); + + if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_WU_FROM_SD_M ) { + if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M ) { + return ( RSTSRC_WAKEUP_FROM_SHUTDOWN ); + } else { + return ( RSTSRC_WAKEUP_FROM_TCK_NOISE ); + } + } else { + return (( aonPmctlResetCtl & AON_PMCTL_RESETCTL_RESET_SRC_M ) >> AON_PMCTL_RESETCTL_RESET_SRC_S ); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h new file mode 100644 index 0000000..15aabd4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h @@ -0,0 +1,577 @@ +/****************************************************************************** +* Filename: sys_ctrl.h +* Revised: 2018-09-17 14:58:51 +0200 (Mon, 17 Sep 2018) +* Revision: 52634 +* +* Description: Defines and prototypes for the System Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup sysctrl_api +//! @{ +// +//***************************************************************************** + +#ifndef __SYSCTRL_H__ +#define __SYSCTRL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_sysctl.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_aon_ioc.h" +#include "../inc/hw_ddi_0_osc.h" +#include "../inc/hw_rfc_pwr.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_aon_pmctl.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_fcfg1.h" +#include "interrupt.h" +#include "debug.h" +#include "pwr_ctrl.h" +#include "osc.h" +#include "prcm.h" +#include "adi.h" +#include "ddi.h" +#include "cpu.h" +#include "vims.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SysCtrlIdle NOROM_SysCtrlIdle + #define SysCtrlShutdownWithAbort NOROM_SysCtrlShutdownWithAbort + #define SysCtrlShutdown NOROM_SysCtrlShutdown + #define SysCtrlStandby NOROM_SysCtrlStandby + #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown + #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown + #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl + #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet +#endif + +//***************************************************************************** +// +// Defines for the settings of the main XOSC +// +//***************************************************************************** +#define SYSCTRL_SYSBUS_ON 0x00000001 +#define SYSCTRL_SYSBUS_OFF 0x00000000 + +//***************************************************************************** +// +// Defines for the different power modes of the System CPU +// +//***************************************************************************** +#define CPU_RUN 0x00000000 +#define CPU_SLEEP 0x00000001 +#define CPU_DEEP_SLEEP 0x00000002 + +//***************************************************************************** +// +// Defines for SysCtrlSetRechargeBeforePowerDown +// +//***************************************************************************** +#define XOSC_IN_HIGH_POWER_MODE 0 // When xosc_hf is in HIGH_POWER_XOSC +#define XOSC_IN_LOW_POWER_MODE 1 // When xosc_hf is in LOW_POWER_XOSC + +//***************************************************************************** +// +// Defines for the vimsPdMode parameter of SysCtrlIdle and SysCtrlStandby +// +//***************************************************************************** +#define VIMS_ON_CPU_ON_MODE 0 // VIMS power domain is only powered when CPU power domain is powered +#define VIMS_ON_BUS_ON_MODE 1 // VIMS power domain is powered whenever the BUS power domain is powered +#define VIMS_NO_PWR_UP_MODE 2 // VIMS power domain is not powered up at next wakeup. + +//***************************************************************************** +// +// Defines for the rechargeMode parameter of SysCtrlStandby +// +//***************************************************************************** +#define SYSCTRL_PREFERRED_RECHARGE_MODE \ + 0xFFFFFFFF // Preferred recharge mode + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Force the system into idle mode. +//! +//! This function forces the system into IDLE mode by configuring the requested +//! VIMS mode, enabling cache retention and powering off the CPU power domain. +//! +//! \param vimsPdMode selects the requested VIMS power domain mode +//! The parameter must be one of the following: +//! - \ref VIMS_ON_CPU_ON_MODE +//! - \ref VIMS_ON_BUS_ON_MODE +//! - \ref VIMS_NO_PWR_UP_MODE +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlIdle(uint32_t vimsPdMode); + +//***************************************************************************** +// +//! \brief Try to enter shutdown but abort if wakeup event happened before shutdown. +//! +//! This function puts the device in shutdown state if no wakeup events are +//! detected before shutdown. +//! +//! Compared to the basic \ref SysCtrlShutdown() function this function makes sure +//! that wakeup events that happen before actual shutdown are also detected. This +//! function either enters shutdown with a guaranteed wakeup detection or returns +//! to the caller function due to a pre-shutdown wakeup event. +//! +//! See \ref SysCtrlShutdown() for basic information about how to configure the device before +//! shutdown and how to wakeup from shutdown. +//! +//! This function uses IO edge detection in addition to the mandatory wakeup configuration. +//! Additional requirements to the application for this function are: +//! - \b Before : +//! - When the application configures an IO for wakeup (see \ref IOCIOShutdownSet()) +//! the application must also configure the same IO for edge detection +//! (see \ref IOCIOIntSet()). +//! - Edge detection must use the same polarity as the wakeup configuration. +//! - Application must enable peripheral power domain (see \ref PRCMPowerDomainOn()) +//! and enable GPIO module in the peripheral power domain (see \ref PRCMPeripheralRunEnable()). +//! - \b After : +//! - An edge, with same polarity as a wakeup event, was detected on a wakeup +//! enabled IO before shutdown, and the shutdown was aborted. The application must +//! clear the event generated by the edge detect (see \ref GPIO_clearEventDio()) and +//! decide what happens next. +//! +//! Useful functions related to shutdown: +//! - \ref IOCIOShutdownSet() : Enables wakeup from shutdown. +//! - \ref IOCIOIntSet() : Enables IO edge detection. +//! - \ref PRCMPowerDomainOn() : Enables peripheral power domain. +//! - \ref PRCMPeripheralRunEnable() : Enables GPIO module. +//! - \ref SysCtrlResetSourceGet() : Detects wakeup from shutdown. +//! - \ref PowerCtrlPadSleepDisable() : Unlatches outputs (disables pad sleep) after +//! wakeup from shutdown. +//! - \ref GPIO_clearEventDio() : Clears edge detects. +//! +//! It is recommended to disable interrupts before calling this function because: +//! - Pads are in sleep mode while this function runs. +//! - An interrupt routine might be terminated if it is triggered after the decision +//! to enter shutdown. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlShutdownWithAbort(void); + +//***************************************************************************** +// +//! \brief Enable shutdown of the device. +//! +//! This function puts the device in shutdown state. The device automatically +//! latches all outputs (pads in sleep) before it turns off all internal power +//! supplies. +//! +//! JTAG must be disconnected and JTAG power domain must be off before device can +//! enter shutdown. This function waits until the device satisfies all shutdown +//! conditions before it enters shutdown. +//! +//! \note The application must unlatch the outputs when the device wakes up from shutdown. +//! It is recommended that any outputs that need to be restored after a wakeup from +//! shutdown are restored before outputs are unlatched in order to avoid glitches. +//! +//! See \ref PowerCtrlPadSleepDisable() for information about how to unlatch outputs +//! (disable pad sleep) after wakeup from shutdown. +//! +//! \note Wakeup events are only detected after the device enters shutdown. +//! +//! See \ref IOCIOShutdownSet() for information about how to enable wakeup from shutdown. +//! +//! See \ref SysCtrlResetSourceGet() for information about how to detect wakeup +//! from shutdown. +//! +//! It is recommended to disable interrupts before calling this function. Shutdown +//! happens immediately when the device satisfies all shutdown conditions thus +//! interrupt routines triggered after this function is called might be +//! aborted. +//! +//! \return This function does \b not return. +// +//***************************************************************************** +extern void SysCtrlShutdown(void); + +//***************************************************************************** +// +//! \brief Force the system into standby mode. +//! +//! This function forces all power domains (RFCORE, SERIAL, PERIPHERAL) off. +//! The VIMS and CPU power domains are turned off by the HW when the +//! \ref PRCMDeepSleep() function is called. +//! The IOs are latched (frozen) before the power domains are turned off to +//! avoid glitches. +//! The VIMS retention (cache) and VIMS module are turned off if requested. +//! The deep-sleep clock for the crypto and DMA modules are turned off, +//! as they must be off in order to enter standby. +//! This function assumes that the LF clock has already been switched to +//! and that the LF clock qualifiers must have been disabled/bypassed. +//! +//! In internal regulator mode the adaptive recharge functionality is enabled +//! with fixed parameter values. +//! In external regulator mode the recharge functionality is disabled. +//! +//! \note This function is optimized to execute with TI-RTOS. There might be +//! application specific prerequisites you would want to do before entering +//! standby which deviate from this specific implementation. +//! +//! \param retainCache selects if VIMS cache shall be retained or not. +//! - false : VIMS cache is not retained +//! - true : VIMS cache is retained +//! \param vimsPdMode selects the VIMS power domain mode. +//! The parameter must be one of the following: +//! - \ref VIMS_ON_CPU_ON_MODE +//! - \ref VIMS_NO_PWR_UP_MODE +//! \param rechargeMode specifies the requested recharge mode. +//! The parameter must be one of the following: +//! - \ref SYSCTRL_PREFERRED_RECHARGE_MODE : Preferred recharge mode specified by TI +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlStandby(bool retainCache, uint32_t vimsPdMode, uint32_t rechargeMode); + +//***************************************************************************** +// +//! \brief Get the CPU core clock frequency. +//! +//! Use this function to get the current clock frequency for the CPU. +//! +//! The CPU can run from 48 MHz and down to 750kHz. The frequency is defined +//! by the combined division factor of the SYSBUS and the CPU clock divider. +//! +//! \return Returns the current CPU core clock frequency. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SysCtrlClockGet( void ) +{ + // Return fixed clock speed + return( GET_MCU_CLOCK ); +} + +//***************************************************************************** +// +//! \brief Sync all accesses to the AON register interface. +//! +//! When this function returns, all writes to the AON register interface are +//! guaranteed to have propagated to hardware. The function will return +//! immediately if no AON writes are pending; otherwise, it will wait for the next +//! AON clock before returning. +//! +//! \return None +//! +//! \sa \ref SysCtrlAonUpdate() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlAonSync(void) +{ + // Sync the AON interface + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! \brief Update all interfaces to AON. +//! +//! When this function returns, at least 1 clock cycle has progressed on the +//! AON domain, so that any outstanding updates to and from the AON interface +//! is guaranteed to be in sync. +//! +//! \note This function should primarily be used after wakeup from sleep modes, +//! as it will guarantee that all shadow registers on the AON interface are updated +//! before reading any AON registers from the MCU domain. If a write has been +//! done to the AON interface it is sufficient to call the \ref SysCtrlAonSync(). +//! +//! \return None +//! +//! \sa \ref SysCtrlAonSync() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlAonUpdate(void) +{ + // Force a clock cycle on the AON interface to guarantee all registers are + // in sync. + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC) = 1; + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! \brief Set Recharge values before entering Power Down. +//! +//! This function shall be called just before entering Power Down. +//! This function typically does nothing (default setting), but +//! if temperature compensated recharge level are enabled (by setting +//! CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC = 0) +//! it adds temperature compensation to the recharge level. +//! +//! \param xoscPowerMode (typically running in XOSC_IN_HIGH_POWER_MODE all the time). +//! - \ref XOSC_IN_HIGH_POWER_MODE : When xosc_hf is in HIGH_POWER_XOSC. +//! - \ref XOSC_IN_LOW_POWER_MODE : When xosc_hf is in LOW_POWER_XOSC. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ); + +//***************************************************************************** +// +//! \brief Adjust Recharge calculations to be used next. +//! +//! Nothing to be done but keeping this function for platform compatibility. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ); + +//***************************************************************************** +// +//! \brief Turns DCDC on or off depending of what is considered to be optimal usage. +//! +//! This function controls the DCDC only if both the following CCFG settings are \c true: +//! - DCDC is configured to be used. +//! - Alternative DCDC settings are defined and enabled. +//! +//! The DCDC is configured in accordance to the CCFG settings when turned on. +//! +//! This function should be called periodically. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrl_DCDC_VoltageConditionalControl( void ); + +//***************************************************************************** +// \name Return values from calling SysCtrlResetSourceGet() +//@{ +//***************************************************************************** +#define RSTSRC_PWR_ON (( AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_PIN_RESET (( AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_VDDS_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_VDDR_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_CLK_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_SYSRESET (( AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_WARMRESET (( AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_WAKEUP_FROM_SHUTDOWN ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 1 ) +#define RSTSRC_WAKEUP_FROM_TCK_NOISE ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 2 ) +//@} + +//***************************************************************************** +// +//! \brief Returns the reset source (including "wakeup from shutdown"). +//! +//! In case of \ref RSTSRC_WAKEUP_FROM_SHUTDOWN the application is +//! responsible for unlatching the outputs (disable pad sleep). +//! See \ref PowerCtrlPadSleepDisable() for more information. +//! +//! \return Returns the reset source. +//! - \ref RSTSRC_PWR_ON +//! - \ref RSTSRC_PIN_RESET +//! - \ref RSTSRC_VDDS_LOSS +//! - \ref RSTSRC_VDDR_LOSS +//! - \ref RSTSRC_CLK_LOSS +//! - \ref RSTSRC_SYSRESET +//! - \ref RSTSRC_WARMRESET +//! - \ref RSTSRC_WAKEUP_FROM_SHUTDOWN +//! - \ref RSTSRC_WAKEUP_FROM_TCK_NOISE +// +//***************************************************************************** +extern uint32_t SysCtrlResetSourceGet( void ); + +//***************************************************************************** +// +//! \brief Perform a full system reset. +//! +//! \return The chip will reset and hence never return from this call. +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlSystemReset( void ) +{ + // Disable CPU interrupts + CPUcpsid(); + // Write reset register + HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_SYSRESET_BITN ) = 1; + // Finally, wait until the above write propagates + while ( 1 ) { + // Do nothing, just wait for the reset (and never return from here) + } +} + +//***************************************************************************** +// +//! \brief Enables reset if OSC clock loss event is asserted. +//! +//! Clock loss circuit in analog domain must be enabled as well in order to +//! actually enable for a clock loss reset to occur +//! \ref OSCClockLossEventEnable(). +//! +//! \note This function shall typically not be called because the clock loss +//! reset functionality is controlled by the boot code (a factory configuration +//! defines whether it is set or not). +//! +//! \return None +//! +//! \sa \ref SysCtrlClockLossResetDisable(), \ref OSCClockLossEventEnable() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlClockLossResetEnable(void) +{ + // Set clock loss enable bit in AON_SYSCTRL using bit banding + HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disables reset due to OSC clock loss event. +//! +//! \note This function shall typically not be called because the clock loss +//! reset functionality is controlled by the boot code (a factory configuration +//! defines whether it is set or not). +//! +//! \return None +//! +//! \sa \ref SysCtrlClockLossResetEnable() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlClockLossResetDisable(void) +{ + // Clear clock loss enable bit in AON_SYSCTRL using bit banding + HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 0; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SysCtrlIdle + #undef SysCtrlIdle + #define SysCtrlIdle ROM_SysCtrlIdle + #endif + #ifdef ROM_SysCtrlShutdownWithAbort + #undef SysCtrlShutdownWithAbort + #define SysCtrlShutdownWithAbort ROM_SysCtrlShutdownWithAbort + #endif + #ifdef ROM_SysCtrlShutdown + #undef SysCtrlShutdown + #define SysCtrlShutdown ROM_SysCtrlShutdown + #endif + #ifdef ROM_SysCtrlStandby + #undef SysCtrlStandby + #define SysCtrlStandby ROM_SysCtrlStandby + #endif + #ifdef ROM_SysCtrlSetRechargeBeforePowerDown + #undef SysCtrlSetRechargeBeforePowerDown + #define SysCtrlSetRechargeBeforePowerDown ROM_SysCtrlSetRechargeBeforePowerDown + #endif + #ifdef ROM_SysCtrlAdjustRechargeAfterPowerDown + #undef SysCtrlAdjustRechargeAfterPowerDown + #define SysCtrlAdjustRechargeAfterPowerDown ROM_SysCtrlAdjustRechargeAfterPowerDown + #endif + #ifdef ROM_SysCtrl_DCDC_VoltageConditionalControl + #undef SysCtrl_DCDC_VoltageConditionalControl + #define SysCtrl_DCDC_VoltageConditionalControl ROM_SysCtrl_DCDC_VoltageConditionalControl + #endif + #ifdef ROM_SysCtrlResetSourceGet + #undef SysCtrlResetSourceGet + #define SysCtrlResetSourceGet ROM_SysCtrlResetSourceGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTRL_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick.c new file mode 100644 index 0000000..29aa43b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: systick.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the SysTick timer in NVIC +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "systick.h" + +// See systick.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick.h new file mode 100644 index 0000000..735171d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick.h @@ -0,0 +1,287 @@ +/****************************************************************************** +* Filename: systick.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Prototypes for the SysTick driver. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_types.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// API Functions and Prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enables the SysTick counter. +//! +//! This will start the SysTick counter. If an interrupt handler has been +//! registered, it will be called when the SysTick counter rolls over. +//! +//! \note Calling this function will cause the SysTick counter to (re)commence +//! counting from its current value. The counter is not automatically reloaded +//! with the period as specified in a previous call to \ref SysTickPeriodSet(). If +//! an immediate reload is required, the NVIC_ST_CURRENT register must be +//! written to force this. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the supplied period on the next +//! clock. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickEnable(void) +{ + // Enable SysTick. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; +} + +//***************************************************************************** +// +//! \brief Disables the SysTick counter. +//! +//! This will stop the SysTick counter. If an interrupt handler has been +//! registered, it will no longer be called until SysTick is restarted. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickDisable(void) +{ + // Disable SysTick. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the SysTick interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler, returning an error if an error occurs. + IntRegister(INT_SYSTICK, pfnHandler); + + // Enable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! \brief Unregisters the interrupt handler for the SysTick interrupt in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntUnregister(void) +{ + // Disable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + + // Unregister the interrupt handler. + IntUnregister(INT_SYSTICK); +} + +//***************************************************************************** +// +//! \brief Enables the SysTick interrupt. +//! +//! This function will enable the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \note The SysTick interrupt handler does not need to clear the SysTick +//! interrupt source as this is done automatically by NVIC when the interrupt +//! handler is called. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntEnable(void) +{ + // Enable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! \brief Disables the SysTick interrupt. +//! +//! This function will disable the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntDisable(void) +{ + // Disable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); +} + +//***************************************************************************** +// +//! \brief Sets the period of the SysTick counter. +//! +//! This function sets the rate at which the SysTick counter wraps; this +//! equals to the number of processor clocks between interrupts. +//! +//! \note Calling this function does not cause the SysTick counter to reload +//! immediately. If an immediate reload is required, the NVIC_ST_CURRENT +//! register must be written. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the \c ui32Period supplied here +//! on the next clock after the SysTick is enabled. +//! +//! \param ui32Period is the number of clock ticks in each period of the +//! SysTick counter; must be between 1 and 16,777,216 (0x1000000), both included. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickPeriodSet(uint32_t ui32Period) +{ + // Check the arguments. + ASSERT((ui32Period > 0) && (ui32Period <= 16777216)); + + // Set the period of the SysTick counter. + HWREG(NVIC_ST_RELOAD) = ui32Period - 1; +} + +//***************************************************************************** +// +//! \brief Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps; this +//! equals to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SysTickPeriodGet(void) +{ + // Return the period of the SysTick counter. + return(HWREG(NVIC_ST_RELOAD) + 1); +} + +//***************************************************************************** +// +//! \brief Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter; this will +//! be a value between the (period - 1) and zero, both included. +//! +//! \return Returns the current value of the SysTick counter +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SysTickValueGet(void) +{ + // Return the current value of the SysTick counter. + return(HWREG(NVIC_ST_CURRENT)); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ + +//***************************************************************************** +// +//! Close the Doxygen group +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick_doc.h new file mode 100644 index 0000000..70848fc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick_doc.h @@ -0,0 +1,68 @@ +/****************************************************************************** +* Filename: systick_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup systick_api +//! @{ +//! \section sec_systick Introduction +//! +//! The system CPU includes a system timer, SysTick, integrated in the NVIC which provides a simple, 24-bit, +//! clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. +//! When enabled, the timer counts down on each clock from the reload value to 0, reloads (wraps) on +//! the next clock edge, then decrements on subsequent clocks. +//! +//! The SysTick counter runs on the system clock. If this clock signal is stopped for low-power mode, the +//! SysTick counter stops. +//! +//! When the processor is halted for debugging, the counter does not decrement. +//! +//! \section sec_systick_api API +//! +//! The API functions can be grouped like this: +//! +//! Configuration and status: +//! - \ref SysTickPeriodSet() +//! - \ref SysTickPeriodGet() +//! - \ref SysTickValueGet() +//! +//! Enable and disable: +//! - \ref SysTickEnable() +//! - \ref SysTickDisable() +//! +//! Interrupt configuration: +//! - \ref SysTickIntRegister() +//! - \ref SysTickIntUnregister() +//! - \ref SysTickIntEnable() +//! - \ref SysTickIntDisable() +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer.c new file mode 100644 index 0000000..86c484f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer.c @@ -0,0 +1,392 @@ +/****************************************************************************** +* Filename: timer.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the General Purpose Timer +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "timer.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef TimerConfigure + #define TimerConfigure NOROM_TimerConfigure + #undef TimerLevelControl + #define TimerLevelControl NOROM_TimerLevelControl + #undef TimerStallControl + #define TimerStallControl NOROM_TimerStallControl + #undef TimerWaitOnTriggerControl + #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl + #undef TimerIntRegister + #define TimerIntRegister NOROM_TimerIntRegister + #undef TimerIntUnregister + #define TimerIntUnregister NOROM_TimerIntUnregister + #undef TimerMatchUpdateMode + #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode + #undef TimerIntervalLoadMode + #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode +#endif + +//***************************************************************************** +// +//! \brief Gets the timer interrupt number. +//! +//! Given a timer base address, this function returns the corresponding +//! interrupt number. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return Returns a timer interrupt number, or -1 if \c ui32Base is invalid. +// +//***************************************************************************** +static uint32_t +TimerIntNumberGet(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // Loop through the table that maps timer base addresses to interrupt + // numbers. + switch(ui32Base) + { + case GPT0_BASE : + ui32Int = INT_GPT0A; + break; + case GPT1_BASE : + ui32Int = INT_GPT1A; + break; + case GPT2_BASE : + ui32Int = INT_GPT2A; + break; + case GPT3_BASE : + ui32Int = INT_GPT3A; + break; + default : + ui32Int = 0x0; + } + + // Return the interrupt number or (-1) if not base address is not matched. + return (ui32Int); +} + +//***************************************************************************** +// +// Configures the timer(s) +// +//***************************************************************************** +void +TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || + (ui32Config == TIMER_CFG_ONE_SHOT_UP) || + (ui32Config == TIMER_CFG_PERIODIC) || + (ui32Config == TIMER_CFG_PERIODIC_UP) || + ((ui32Config & 0xFF000000) == TIMER_CFG_SPLIT_PAIR)); + ASSERT(((ui32Config & 0xFF000000) != TIMER_CFG_SPLIT_PAIR) || + ((((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PWM)) && + (((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PWM)))); + + // Disable the timers. + HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); + + // Set the global timer configuration. + HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24; + + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE; + HWREG(ui32Base + GPT_O_TBMR) = + ((ui32Config >> 8) & 0xFF) | GPT_TBMR_TBPWMIE; +} + +//***************************************************************************** +// +// Controls the output level +// +//***************************************************************************** +void +TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the output levels as requested. + ui32Timer &= GPT_CTL_TAPWML | GPT_CTL_TBPWML; + HWREG(ui32Base + GPT_O_CTL) = (bInvert ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & + ~(ui32Timer))); +} + +//***************************************************************************** +// +// Controls the stall handling +// +//***************************************************************************** +void +TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the stall mode. + ui32Timer &= GPT_CTL_TASTALL | GPT_CTL_TBSTALL; + HWREG(ui32Base + GPT_O_CTL) = (bStall ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer))); +} + +//***************************************************************************** +// +// Controls the wait on trigger handling +// +//***************************************************************************** +void +TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the wait on trigger mode for timer A. + if(ui32Timer & TIMER_A) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAWOT; + } + else + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAWOT); + } + } + + // Set the wait on trigger mode for timer B. + if(ui32Timer & TIMER_B) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBWOT; + } + else + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBWOT); + } + } +} + +//***************************************************************************** +// +// Registers an interrupt handler for the timer interrupt +// +//***************************************************************************** +void +TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Get the interrupt number for this timer module. + ui32Int = TimerIntNumberGet(ui32Base); + + // Register an interrupt handler for timer A if requested. + if(ui32Timer & TIMER_A) + { + // Register the interrupt handler. + IntRegister(ui32Int, pfnHandler); + + // Enable the interrupt. + IntEnable(ui32Int); + } + + // Register an interrupt handler for timer B if requested. + if(ui32Timer & TIMER_B) + { + // Register the interrupt handler. + IntRegister(ui32Int + 1, pfnHandler); + + // Enable the interrupt. + IntEnable(ui32Int + 1); + } +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for the timer interrupt +// +//***************************************************************************** +void +TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Get the interrupt number for this timer module. + ui32Int = TimerIntNumberGet(ui32Base); + + // Unregister the interrupt handler for timer A if requested. + if(ui32Timer & TIMER_A) + { + // Disable the interrupt. + IntDisable(ui32Int); + + // Unregister the interrupt handler. + IntUnregister(ui32Int); + } + + // Unregister the interrupt handler for timer B if requested. + if(ui32Timer & TIMER_B) + { + // Disable the interrupt. + IntDisable(ui32Int + 1); + + // Unregister the interrupt handler. + IntUnregister(ui32Int + 1); + } +} + +//***************************************************************************** +// +// Sets the Match Register Update mode +// +//***************************************************************************** +void +TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); + ASSERT((ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) || (ui32Mode == TIMER_MATCHUPDATE_TIMEOUT)); + + // Set mode for timer A + if(ui32Timer & TIMER_A) + { + if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAMRSU); + } + else + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAMRSU; + } + } + + // Set mode for timer B + if(ui32Timer & TIMER_B) + { + if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBMRSU); + } + else + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBMRSU; + } + } +} + +//***************************************************************************** +// +// Sets the Interval Load mode +// +//***************************************************************************** +void +TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); + ASSERT((ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) || (ui32Mode == TIMER_INTERVALLOAD_TIMEOUT)); + + // Set mode for timer A + if(ui32Timer & TIMER_A) + { + if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAILD); + } + else + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAILD; + } + } + + // Set mode for timer B + if(ui32Timer & TIMER_B) + { + if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBILD); + } + else + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBILD; + } + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer.h new file mode 100644 index 0000000..da13074 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer.h @@ -0,0 +1,1176 @@ +/****************************************************************************** +* Filename: timer.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//**************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup timer_api +//! @{ +// +//**************************************************************************** + +#ifndef __GPT_H__ +#define __GPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_gpt.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define TimerConfigure NOROM_TimerConfigure + #define TimerLevelControl NOROM_TimerLevelControl + #define TimerStallControl NOROM_TimerStallControl + #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl + #define TimerIntRegister NOROM_TimerIntRegister + #define TimerIntUnregister NOROM_TimerIntUnregister + #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode + #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ui32Config parameter. +// +//***************************************************************************** +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ui32IntFlags parameter, and returned from +// TimerIntStatus. +// +//***************************************************************************** +#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ui32Event parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ui32Timer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000FF // Timer A +#define TIMER_B 0x0000FF00 // Timer B +#define TIMER_BOTH 0x0000FFFF // Timer Both + +//***************************************************************************** +// +// Values that can be passed to GPTSynchronize as the ui32Timers parameter +// +//***************************************************************************** +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B + +//***************************************************************************** +// +// Values that can be passed to TimerMatchUpdateMode +// +//***************************************************************************** +#define TIMER_MATCHUPDATE_NEXTCYCLE 0x00000000 // Apply match register on next cycle +#define TIMER_MATCHUPDATE_TIMEOUT 0x00000001 // Apply match register on next timeout + +//***************************************************************************** +// +// Values that can be passed to TimerIntervalLoad +// +//***************************************************************************** +#define TIMER_INTERVALLOAD_NEXTCYCLE 0x00000000 // Load TxR register with the value in the TxILR register on the next clock cycle +#define TIMER_INTERVALLOAD_TIMEOUT 0x00000001 // Load TxR register with the value in the TxILR register on next timeout + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks a timer base address. +//! +//! This function determines if a timer module base address is valid. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +TimerBaseValid(uint32_t ui32Base) +{ + return((ui32Base == GPT0_BASE) || (ui32Base == GPT1_BASE) || + (ui32Base == GPT2_BASE) || (ui32Base == GPT3_BASE)); +} +#endif + +//***************************************************************************** +// +//! \brief Enables the timer(s). +//! +//! This function enables operation of the timer module. The timer must be +//! configured before it is enabled. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to enable. Must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerEnable(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Enable the timer(s) module. + HWREG(ui32Base + GPT_O_CTL) |= ui32Timer & (GPT_CTL_TAEN | GPT_CTL_TBEN); +} + +//***************************************************************************** +// +//! \brief Disables the timer(s). +//! +//! This function disables operation of the timer module. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to disable. Must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerDisable(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Disable the timer module. + HWREG(ui32Base + GPT_O_CTL) &= ~(ui32Timer & + (GPT_CTL_TAEN | GPT_CTL_TBEN)); +} + +//***************************************************************************** +// +//! \brief Configures the timer(s). +//! +//! This function configures the operating mode of the timer(s). The timer +//! module is disabled before being configured and is left in the disabled +//! state. +//! +//! The timers are comprised of two 16-bit timers that can +//! operate independently or be concatenated to form a 32-bit timer. +//! +//! \note If the timers are used independently the length of timer can be +//! extended to 24 bit by use of an 8 bit prescale register set using +//! \ref TimerPrescaleSet(). +//! +//! When configuring for full-width timer \c ui32Config is set +//! as one of the following values: +//! - \ref TIMER_CFG_ONE_SHOT : Full-width one-shot timer. +//! - \ref TIMER_CFG_ONE_SHOT_UP : Full-width one-shot timer that counts up +//! instead of down. +//! - \ref TIMER_CFG_PERIODIC : Full-width periodic timer. +//! - \ref TIMER_CFG_PERIODIC_UP : Full-width periodic timer that counts up +//! instead of down. +//! +//! When configuring for a pair of half-width timers, each timer is separately +//! configured. The timers are configured by setting \c ui32Config to +//! the bitwise OR of one of each of the following three: +//! - Use half-width timers: +//! - \ref TIMER_CFG_SPLIT_PAIR +//! - Timer A: +//! - \ref TIMER_CFG_A_ONE_SHOT : Half-width one-shot timer +//! - \ref TIMER_CFG_A_ONE_SHOT_UP : Half-width one-shot timer that counts up +//! instead of down. +//! - \ref TIMER_CFG_A_PERIODIC : Half-width periodic timer +//! - \ref TIMER_CFG_A_PERIODIC_UP : Half-width periodic timer that counts up +//! instead of down. +//! - \ref TIMER_CFG_A_CAP_COUNT : Half-width edge count capture +//! - \ref TIMER_CFG_A_CAP_COUNT_UP : Half-width edge count capture that counts +//! up instead of down. +//! - \ref TIMER_CFG_A_CAP_TIME : Half-width edge time capture +//! - \ref TIMER_CFG_A_CAP_TIME_UP : Half-width edge time capture that counts up +//! instead of down. +//! - \ref TIMER_CFG_A_PWM : Half-width PWM output +//! - Timer B: +//! - Same as Timer A but using TIMER_CFG_B_* instead. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Config is the configuration for the timer. +//! +//! \return None +// +//***************************************************************************** +extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config); + +//***************************************************************************** +// +//! \brief Controls the output level. +//! +//! This function configures the PWM output level for the specified timer. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust. Must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param bInvert specifies the output level. +//! - \c true : Timer's output is active low. +//! - \c false : Timer's output is active high. +//! +//! \return None +// +//***************************************************************************** +extern void TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, + bool bInvert); + +//***************************************************************************** +// +//! \brief Controls the event type. +//! +//! This function configures the signal edge(s) that triggers the timer when +//! in capture mode. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Event specifies the type of event; must be one of: +//! - \ref TIMER_EVENT_POS_EDGE +//! - \ref TIMER_EVENT_NEG_EDGE +//! - \ref TIMER_EVENT_BOTH_EDGES +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerEventControl(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Event) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the event type. + ui32Timer &= GPT_CTL_TAEVENT_M | GPT_CTL_TBEVENT_M; + HWREG(ui32Base + GPT_O_CTL) = ((HWREG(ui32Base + GPT_O_CTL) & ~ui32Timer) | + (ui32Event & ui32Timer)); +} + +//***************************************************************************** +// +//! \brief Controls the stall handling. +//! +//! This function controls the stall response for the specified timer. If the +//! \e bStall parameter is \b true, then the timer stops counting if the +//! processor enters debug mode; otherwise the timer keeps running while in +//! debug mode. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param bStall specifies the response to a stall signal. +//! - \c true : Timer stops counting if the processor enters debug mode. +//! - \c false : Timer keeps running if the processor enters debug mode. +//! +//! \return None +// +//***************************************************************************** +extern void TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, + bool bStall); + +//***************************************************************************** +// +//! \brief Controls the wait on trigger handling. +//! +//! This function controls whether or not a timer waits for a trigger input to +//! start counting. When enabled, the previous timer in the trigger chain must +//! count to its timeout in order for this timer to start counting. Refer to +//! the part's data sheet for a description of the trigger chain. +//! +//! \note This function should not be used for Timer 0A or Wide Timer 0A. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param bWait specifies if the timer should wait for a trigger input. +//! - \c true : Wait for trigger. +//! - \c false : Do not wait for trigger. +//! +//! \return None +// +//***************************************************************************** +extern void TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, + bool bWait); + +//***************************************************************************** +// +//! \brief Set the timer prescale value. +//! +//! This function configures the value of the timer clock prescaler. The +//! prescaler is only operational when in half-width mode and is used to extend +//! the range of the half-width timer modes. +//! +//! When in one-shot or periodic down count modes, \b ui32Value defines the +//! prescaler for the timer counter. When acting as a true prescaler, the +//! prescaler counts down to 0 before the value in timer registers are incremented. +//! +//! In all other individual/split modes, \b ui32Value is a linear extension of +//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes +//! of the 16/32-bit timer. +//! +//! \note Because the prescaler counts down to 0 the timer division ratio equals +//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the timer prescale value which must be between 0 and 255 +//! (both included). +//! - 0 : Timer division ratio = 1 (disable prescaling). +//! - 1 : Timer division ratio = 2. +//! - ... +//! - 255 : Timer division ratio = 256. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + ASSERT(ui32Value < 256); + + // Set the timer A prescaler if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAPR) = ui32Value; + } + + // Set the timer B prescaler if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBPR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Get the timer prescale value. +//! +//! This function gets the value of the timer clock prescaler. The +//! prescaler is only operational when in half-width mode and is used to extend +//! the range of the half-width timer modes. +//! +//! When in one-shot or periodic down count modes, \b ui32Value defines the +//! prescaler for the timer counter. When acting as a true prescaler, the +//! prescaler counts down to 0 before the value in timer registers are incremented. +//! +//! In all other individual/split modes, \b ui32Value is a linear extension of +//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes +//! of the 16/32-bit timer. +//! +//! \note Because the prescaler counts down to 0 the timer division ratio equals +//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the value of the timer prescaler. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Return the appropriate prescale value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPR) : + HWREG(ui32Base + GPT_O_TBPR)); +} + +//***************************************************************************** +// +//! \brief Set the timer prescale match value. +//! +//! This function configures the value of the input clock prescaler match +//! value. When in a half-width mode that uses the counter match and the +//! prescaler, the prescale match effectively extends the range of the match. +//! The prescaler provides the least significant bits when counting down in +//! periodic and one-shot modes; in all other modes, the prescaler provides the +//! most significant bits. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the timer prescale match value which must be between 0 +//! and 255 (both included). +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + ASSERT(ui32Value < 256); + + // Set the timer A prescale match if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAPMR) = ui32Value; + } + + // Set the timer B prescale match if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBPMR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Get the timer prescale match value. +//! +//! This function gets the value of the input clock prescaler match value. +//! When in a half-width mode that uses the counter match and prescaler, the +//! prescale match effectively extends the range of the match. The prescaler +//! provides the least significant bits when counting down in periodic and +//! one-shot modes; in all other modes, the prescaler provides the most +//! significant bits. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the value of the timer prescale match. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate prescale match value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPMR) : + HWREG(ui32Base + GPT_O_TBPMR)); +} + +//***************************************************************************** +// +//! \brief Sets the timer load value. +//! +//! This function configures the timer load value; if the timer is running then +//! the value is immediately loaded into the timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the load value. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the timer A load value if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAILR) = ui32Value; + } + + // Set the timer B load value if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBILR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Gets the timer load value. +//! +//! This function gets the currently programmed interval load value for the +//! specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the load value for the timer +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate load value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAILR) : + HWREG(ui32Base + GPT_O_TBILR)); +} + +//***************************************************************************** +// +//! \brief Gets the current timer value. +//! +//! This function reads the current value of the specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate timer value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAR) : + HWREG(ui32Base + GPT_O_TBR)); +} + +//***************************************************************************** +// +//! \brief Sets the timer match value. +//! +//! This function configures the match value for a timer. This value is used +//! in capture count mode to determine when to interrupt the processor and in +//! PWM mode to determine the duty cycle of the output signal. Match interrupts +//! can also be generated in periodic and one-shot modes when the value of the +//! counter matches this register. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the match value. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the timer A match value if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAMATCHR) = ui32Value; + } + + // Set the timer B match value if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBMATCHR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Gets the timer match value. +//! +//! This function gets the match value for the specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return Returns the match value for the timer +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate match value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAMATCHR) : + HWREG(ui32Base + GPT_O_TBMATCHR)); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the timer interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific timer interrupts must be enabled via \ref TimerIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! \ref TimerIntClear(). +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s); must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param pfnHandler is a pointer to the function to be called when the timer +//! interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, + void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the timer interrupt in the dynamic interrupt table. +//! +//! This function unregisters the handler to be called when a timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s); must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer); + +//***************************************************************************** +// +//! \brief Enables individual timer interrupt sources. +//! +//! This function enables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter must be the bitwise OR of any combination of +//! the following: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(ui32Base + GPT_O_IMR) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual timer interrupt sources. +//! +//! This function disables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter must be the bitwise OR of any combination of +//! the following: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(ui32Base + GPT_O_IMR) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the timer module. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the timer module. +//! \param bMasked selects either raw or masked interrupt status: +//! - \c true : Masked interrupt. +//! - \c false : Raw interrupt. +//! +//! \return The current interrupt status, enumerated as a bit field of values: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + return(bMasked ? HWREG(ui32Base + GPT_O_MIS) : + HWREG(ui32Base + GPT_O_RIS)); +} + +//***************************************************************************** +// +//! \brief Clears timer interrupt sources. +//! +//! The specified timer interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter must be the bitwise OR of any combination of +//! the following: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Clear the requested interrupt sources. + HWREG(ui32Base + GPT_O_ICLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Synchronizes the counters in a set of timers. +//! +//! This function synchronizes the counters in a specified set of timers. +//! When a timer is running in half-width mode, each half can be included or +//! excluded in the synchronization event. When a timer is running in +//! full-width mode, only the A timer can be synchronized (specifying the B +//! timer has no effect). +//! +//! \param ui32Base is the base address of the timer module. This parameter must +//! be the base address of Timer0 (in other words, \b GPT0_BASE). +//! \param ui32Timers is the set of timers to synchronize. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TIMER_0A_SYNC +//! - \ref TIMER_0B_SYNC +//! - \ref TIMER_1A_SYNC +//! - \ref TIMER_1B_SYNC +//! - \ref TIMER_2A_SYNC +//! - \ref TIMER_2B_SYNC +//! - \ref TIMER_3A_SYNC +//! - \ref TIMER_3B_SYNC +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers) +{ + // Check the arguments. + ASSERT(ui32Base == GPT0_BASE); + + // Synchronize the specified timers. + HWREG(ui32Base + GPT_O_SYNC) = ui32Timers; +} + +//***************************************************************************** +// +//! \brief Enables AND'ing of the CCP outputs from Timer A and Timer B. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerCcpCombineEnable(uint32_t ui32Base) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + + // Set the bit + HWREG(ui32Base + GPT_O_ANDCCP) |= GPT_ANDCCP_CCP_AND_EN; +} + +//***************************************************************************** +// +//! \brief Disables AND'ing of the CCP outputs from Timer A and Timer B. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerCcpCombineDisable(uint32_t ui32Base) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + + // Clear the bit + HWREG(ui32Base + GPT_O_ANDCCP) &= ~(GPT_ANDCCP_CCP_AND_EN); +} + +//***************************************************************************** +// +//! \brief Sets the Match Register Update mode. +//! +//! This function controls when the Match Register value and Prescale Register value +//! are applied after writing these registers while a timer is enabled. +//! +//! \note If the timer is disabled when setting the update mode the Match Register +//! and Prescale Register values are applied immediately when enabling the timer. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to configure; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Mode sets the mode: +//! - \ref TIMER_MATCHUPDATE_NEXTCYCLE : Apply Match Register and Prescale Register on next clock +//! cycle after writing any of these registers. +//! - \ref TIMER_MATCHUPDATE_TIMEOUT : Apply Match Register and Prescale Register on next timeout +//! after writing any of these registers. +//! +//! \return None +// +//***************************************************************************** +extern void TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode); + +//***************************************************************************** +// +//! \brief Sets the Interval Load mode. +//! +//! This function controls when the Timer Register and Prescale Snap-shot (if used) +//! are updated. +//! +//! Timer Register (TAR/TBR) is updated when Interval Load Register (TAILR/TBILR) is written +//! and the Prescale Snap-shot (TAPS/TBPS) is updated when Prescale Register (TAPR/TBPR) is +//! written depending on the mode of operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to configure; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Mode sets the mode: +//! - \ref TIMER_INTERVALLOAD_NEXTCYCLE : Update Timer Register and Prescale Snap-shot on next clock +//! cycle after writing Interval Load Register or Prescale Register, respectively. +//! - \ref TIMER_INTERVALLOAD_TIMEOUT : Update Timer Register and Prescale Snap-shot on next timeout +//! after writing Interval Load Register or Prescale Register, respectively. +//! +//! \return None +// +//***************************************************************************** +extern void TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_TimerConfigure + #undef TimerConfigure + #define TimerConfigure ROM_TimerConfigure + #endif + #ifdef ROM_TimerLevelControl + #undef TimerLevelControl + #define TimerLevelControl ROM_TimerLevelControl + #endif + #ifdef ROM_TimerStallControl + #undef TimerStallControl + #define TimerStallControl ROM_TimerStallControl + #endif + #ifdef ROM_TimerWaitOnTriggerControl + #undef TimerWaitOnTriggerControl + #define TimerWaitOnTriggerControl ROM_TimerWaitOnTriggerControl + #endif + #ifdef ROM_TimerIntRegister + #undef TimerIntRegister + #define TimerIntRegister ROM_TimerIntRegister + #endif + #ifdef ROM_TimerIntUnregister + #undef TimerIntUnregister + #define TimerIntUnregister ROM_TimerIntUnregister + #endif + #ifdef ROM_TimerMatchUpdateMode + #undef TimerMatchUpdateMode + #define TimerMatchUpdateMode ROM_TimerMatchUpdateMode + #endif + #ifdef ROM_TimerIntervalLoadMode + #undef TimerIntervalLoadMode + #define TimerIntervalLoadMode ROM_TimerIntervalLoadMode + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer_doc.h new file mode 100644 index 0000000..d15c086 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer_doc.h @@ -0,0 +1,121 @@ +/****************************************************************************** +* Filename: timer_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup timer_api +//! @{ +//! \section sec_timer Introduction +//! +//! The timer API provides a set of functions for using the general-purpose timer module. +//! +//! The timer module contains four timer blocks with the following functional options: +//! - Operating modes: +//! - 16-bit with 8-bit prescaler or 32-bit programmable one-shot timer. +//! - 16-bit with 8-bit prescaler or 32-bit programmable periodic timer. +//! - Two capture compare PWM pins (CCP) for each 32-bit timer. +//! - 24-bit input-edge count or 24-bit time-capture modes. +//! - 24-bit PWM mode with software-programmable output inversion of the PWM signal. +//! - Count up or down. +//! - Daisy chaining of timer modules allows a single timer to initiate multiple timing events. +//! - Timer synchronization allows selected timers to start counting on the same clock cycle. +//! - User-enabled stalling when the System CPU asserts a CPU Halt flag during debug. +//! - Ability to determine the elapsed time between the assertion of the timer interrupt and +//! entry into the interrupt service routine. +//! +//! Each timer block provides two half-width timers/counters that can be configured +//! to operate independently as timers or event counters or to operate as a combined +//! full-width timer. +//! The timers provide 16-bit half-width timers and a 32-bit full-width timer. +//! For the purposes of this API, the two +//! half-width timers provided by a timer block are referred to as TimerA and +//! TimerB, and the full-width timer is referred to as TimerA. +//! +//! When in half-width mode, the timer can also be configured for event capture or +//! as a pulse width modulation (PWM) generator. When configured for event +//! capture, the timer acts as a counter. It can be configured to count either the +//! time between events or the events themselves. The type of event +//! being counted can be configured as a positive edge, a negative edge, or both +//! edges. When a timer is configured as a PWM generator, the input signal used to +//! capture events becomes an output signal, and the timer drives an +//! edge-aligned pulse onto that signal. +//! +//! Control is also provided over interrupt sources and events. Interrupts can be +//! generated to indicate that an event has been captured, or that a certain number +//! of events have been captured. Interrupts can also be generated when the timer +//! has counted down to 0 or when the timer matches a certain value. +//! +//! Timer configuration is handled by \ref TimerConfigure(), which performs the high +//! level setup of the timer module; that is, it is used to set up full- or +//! half-width modes, and to select between PWM, capture, and timer operations. +//! +//! \section sec_timer_api API +//! +//! The API functions can be grouped like this: +//! +//! Functions to perform timer control: +//! - \ref TimerConfigure() +//! - \ref TimerEnable() +//! - \ref TimerDisable() +//! - \ref TimerLevelControl() +//! - \ref TimerWaitOnTriggerControl() +//! - \ref TimerEventControl() +//! - \ref TimerStallControl() +//! - \ref TimerIntervalLoadMode() +//! - \ref TimerMatchUpdateMode() +//! - \ref TimerCcpCombineDisable() +//! - \ref TimerCcpCombineEnable() +//! +//! Functions to manage timer content: +//! - \ref TimerLoadSet() +//! - \ref TimerLoadGet() +//! - \ref TimerPrescaleSet() +//! - \ref TimerPrescaleGet() +//! - \ref TimerMatchSet() +//! - \ref TimerMatchGet() +//! - \ref TimerPrescaleMatchSet() +//! - \ref TimerPrescaleMatchGet() +//! - \ref TimerValueGet() +//! - \ref TimerSynchronize() +//! +//! Functions to manage the interrupt handler for the timer interrupt: +//! - \ref TimerIntRegister() +//! - \ref TimerIntUnregister() +//! +//! The individual interrupt sources within the timer module are managed with: +//! - \ref TimerIntEnable() +//! - \ref TimerIntDisable() +//! - \ref TimerIntStatus() +//! - \ref TimerIntClear() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/trng.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/trng.c new file mode 100644 index 0000000..7c1c4e1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/trng.c @@ -0,0 +1,112 @@ +/****************************************************************************** +* Filename: trng.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the TRNG module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "trng.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef TRNGConfigure + #define TRNGConfigure NOROM_TRNGConfigure + #undef TRNGNumberGet + #define TRNGNumberGet NOROM_TRNGNumberGet +#endif + +//***************************************************************************** +// +// Configure the true random number generator +// +//***************************************************************************** +void +TRNGConfigure(uint32_t ui32MinSamplesPerCycle, + uint32_t ui32MaxSamplesPerCycle, + uint32_t ui32ClocksPerSample) +{ + uint32_t ui32Val; + + // Make sure the TRNG is disabled. + ui32Val = HWREG(TRNG_BASE + TRNG_O_CTL) & ~TRNG_CTL_TRNG_EN; + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // Configure the startup number of samples. + ui32Val &= ~TRNG_CTL_STARTUP_CYCLES_M; + ui32Val |= ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CTL_STARTUP_CYCLES_S ) & TRNG_CTL_STARTUP_CYCLES_M ); + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // Configure the minimum and maximum number of samples pr generated number + // and the number of clocks per sample. + HWREG(TRNG_BASE + TRNG_O_CFG0) = ( + ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CFG0_MAX_REFILL_CYCLES_S ) & TRNG_CFG0_MAX_REFILL_CYCLES_M ) | + ((( ui32ClocksPerSample ) << TRNG_CFG0_SMPL_DIV_S ) & TRNG_CFG0_SMPL_DIV_M ) | + ((( ui32MinSamplesPerCycle >> 6 ) << TRNG_CFG0_MIN_REFILL_CYCLES_S ) & TRNG_CFG0_MIN_REFILL_CYCLES_M ) ); +} + +//***************************************************************************** +// +// Get a random number from the generator +// +//***************************************************************************** +uint32_t +TRNGNumberGet(uint32_t ui32Word) +{ + uint32_t ui32RandomNumber; + + // Check the arguments. + ASSERT((ui32Word == TRNG_HI_WORD) || + (ui32Word == TRNG_LOW_WORD)); + + // Return the right requested part of the generated number. + if(ui32Word == TRNG_HI_WORD) + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT1); + } + else + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT0); + } + + // Initiate generation of new number. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1; + + // Return the random number. + return ui32RandomNumber; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/trng.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/trng.h new file mode 100644 index 0000000..08a485b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/trng.h @@ -0,0 +1,451 @@ +/****************************************************************************** +* Filename: trng.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and prototypes for the true random number gen. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup trng_api +//! @{ +// +//***************************************************************************** + +#ifndef __TRNG_H__ +#define __TRNG_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_trng.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define TRNGConfigure NOROM_TRNGConfigure + #define TRNGNumberGet NOROM_TRNGNumberGet +#endif + +//***************************************************************************** +// +// +// +//***************************************************************************** +#define TRNG_NUMBER_READY 0x00000001 // +#define TRNG_FRO_SHUTDOWN 0x00000002 // +#define TRNG_NEED_CLOCK 0x80000000 // + +#define TRNG_HI_WORD 0x00000001 +#define TRNG_LOW_WORD 0x00000002 + +//***************************************************************************** +// +// API Function and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure the true random number generator. +//! +//! Use this function to set the minimum and maximum number of samples required +//! in each generation of a new random number. +//! +//! \param ui32MinSamplesPerCycle is the minimum number of samples per each +//! generated random number. Constraints: +//! - Value must be bigger than or equal to 2^6 and less than 2^14. +//! - The 6 LSBs of the argument are truncated. +//! - If the value is zero, the number of samples is fixed to the value determined +//! by ui32MaxSamplesPerCycle. To ensure same entropy in all generated random +//! numbers the value 0 should be used. +//! \param ui32MaxSamplesPerCycle is the maximum number of samples per each +//! generated random number. Constraints: +//! - Value must be between 2^8 and 2^24 (both included). +//! - The 8 LSBs of the argument are truncated. +//! - Value 0 and 2^24 both give the highest possible value. +//! \param ui32ClocksPerSample is the number of clock cycles for each time +//! a new sample is generated from the FROs. +//! - 0 : Every sample. +//! - 1 : Every second sample. +//! - ... +//! - 15 : Every 16. sample. +//! +//! \return None +// +//***************************************************************************** +extern void TRNGConfigure(uint32_t ui32MinSamplesPerCycle, + uint32_t ui32MaxSamplesPerCycle, + uint32_t ui32ClocksPerSample); + +//***************************************************************************** +// +//! \brief Enable the TRNG. +//! +//! Enable the TRNG to start preparing a random number. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGEnable(void) +{ + // Enable the TRNG. + HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disable the TRNG module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGDisable(void) +{ + // Enable the TRNG + HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Get a random number from the generator. +//! +//! Use this function to get either the high or low part of the 64 bit +//! generated number. +//! +//! \note Data from this register is only valid if the TRNG has produced a +//! number. Use \ref TRNGStatusGet() to poll the for status. After calling this +//! function a new random number will be generated. +//! +//! \param ui32Word determines if whether to return the high or low 32 bits. +//! - \ref TRNG_HI_WORD +//! - \ref TRNG_LOW_WORD +//! +//! \return Return either the high or low part of the 64 bit generated random +//! number. +// +//***************************************************************************** +extern uint32_t TRNGNumberGet(uint32_t ui32Word); + +//***************************************************************************** +// +//! \brief Get the status of the TRNG. +//! +//! Use this function to retrieve the status of the TRNG. +//! +//! \return Returns the current status of the TRNG module. +//! The returned status is a bitwise OR'ed combination of: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! - \ref TRNG_NEED_CLOCK +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TRNGStatusGet(void) +{ + // Return the status. + return (HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); +} + +//***************************************************************************** +// +//! \brief Reset the TRNG. +//! +//! Use this function to reset the TRNG module. Reset will be low for +//! approximately 5 clock cycles. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGReset(void) +{ + // Reset the TRNG. + HWREG(TRNG_BASE + TRNG_O_SWRESET) = 1; +} + +//***************************************************************************** +// +//! \brief Enables individual TRNG interrupt sources. +//! +//! This function enables the indicated TRNG interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntEnable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || + (ui32IntFlags & TRNG_FRO_SHUTDOWN)); + + // Enable the specified interrupts. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual TRNG interrupt sources. +//! +//! This function disables the indicated TRNG interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntDisable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || + (ui32IntFlags & TRNG_FRO_SHUTDOWN)); + + // Disable the specified interrupts. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status of the TRNG module. +//! +//! This function returns the interrupt status for the specified TRNG. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param bMasked selects either raw or masked interrupt status. +//! - \c true : Masked interrupt. +//! - \c false : Raw interrupt. +//! +//! \return Returns the current interrupt status, enumerated as: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TRNGIntStatus(bool bMasked) +{ + uint32_t ui32Mask; + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + ui32Mask = HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK); + return(ui32Mask & HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); + } + else + { + return(HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT) & 0x00000003); + } +} + +//***************************************************************************** +// +//! \brief Clears TRNG interrupt sources. +//! +//! The specified TRNG interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntClear(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || + (ui32IntFlags & TRNG_FRO_SHUTDOWN)); + + // Clear the requested interrupt sources. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for a TRNG interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific TRNG interrupts must be enabled via \ref TRNGIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! TRNG interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_TRNG_IRQ, pfnHandler); + + // Enable the TRNG interrupt. + IntEnable(INT_TRNG_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a TRNG interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a Crypto interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntUnregister(void) +{ + // Disable the interrupt. + IntDisable(INT_TRNG_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_TRNG_IRQ); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_TRNGConfigure + #undef TRNGConfigure + #define TRNGConfigure ROM_TRNGConfigure + #endif + #ifdef ROM_TRNGNumberGet + #undef TRNGNumberGet + #define TRNGNumberGet ROM_TRNGNumberGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __TRNG_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart.c new file mode 100644 index 0000000..7818fc5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart.c @@ -0,0 +1,304 @@ +/****************************************************************************** +* Filename: uart.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the UART. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "uart.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef UARTFIFOLevelGet + #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet + #undef UARTConfigSetExpClk + #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk + #undef UARTConfigGetExpClk + #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk + #undef UARTDisable + #define UARTDisable NOROM_UARTDisable + #undef UARTCharGetNonBlocking + #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking + #undef UARTCharGet + #define UARTCharGet NOROM_UARTCharGet + #undef UARTCharPutNonBlocking + #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking + #undef UARTCharPut + #define UARTCharPut NOROM_UARTCharPut + #undef UARTIntRegister + #define UARTIntRegister NOROM_UARTIntRegister + #undef UARTIntUnregister + #define UARTIntUnregister NOROM_UARTIntUnregister +#endif + +//***************************************************************************** +// +// Gets the FIFO level at which interrupts are generated +// +//***************************************************************************** +void +UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel) +{ + uint32_t ui32Temp; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Read the FIFO level register. + ui32Temp = HWREG(ui32Base + UART_O_IFLS); + + // Extract the transmit and receive FIFO levels. + *pui32TxLevel = ui32Temp & UART_IFLS_TXSEL_M; + *pui32RxLevel = ui32Temp & UART_IFLS_RXSEL_M; +} + +//***************************************************************************** +// +// Sets the configuration of a UART +// +//***************************************************************************** +void +UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config) +{ + uint32_t ui32Div; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT(ui32Baud != 0); + + // Stop the UART. + UARTDisable(ui32Base); + + // Compute the fractional baud rate divider. + ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; + + // Set the baud rate. + HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; + HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; + + // Set parity, data length, and number of stop bits. + HWREG(ui32Base + UART_O_LCRH) = ui32Config; +} + +//***************************************************************************** +// +// Gets the current configuration of a UART +// +//***************************************************************************** +void +UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config) +{ + uint32_t ui32Int, ui32Frac; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Compute the baud rate. + ui32Int = HWREG(ui32Base + UART_O_IBRD); + ui32Frac = HWREG(ui32Base + UART_O_FBRD); + *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); + + // Get the parity, data length, and number of stop bits. + *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | + UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +// Disables transmitting and receiving +// +//***************************************************************************** +void +UARTDisable(uint32_t ui32Base) +{ + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait for end of TX. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) + { + } + + // Disable the FIFO. + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); + + // Disable the UART. + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +// Receives a character from the specified port +// +//***************************************************************************** +int32_t +UARTCharGetNonBlocking(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // See if there are any characters in the receive FIFO. + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) + { + // Read and return the next character. + return(HWREG(ui32Base + UART_O_DR)); + } + else + { + // There are no characters, so return a failure. + return(-1); + } +} + +//***************************************************************************** +// +// Waits for a character from the specified port +// +//***************************************************************************** +int32_t +UARTCharGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait until a char is available. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) + { + } + + // Now get the character. + return(HWREG(ui32Base + UART_O_DR)); +} + +//***************************************************************************** +// +// Sends a character to the specified port +// +//***************************************************************************** +bool +UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // See if there is space in the transmit FIFO. + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) + { + // Write this character to the transmit FIFO. + HWREG(ui32Base + UART_O_DR) = ui8Data; + + // Success. + return(true); + } + else + { + // There is no space in the transmit FIFO, so return a failure. + return(false); + } +} + +//***************************************************************************** +// +// Waits to send a character from the specified port +// +//***************************************************************************** +void +UARTCharPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait until space is available. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) + { + } + + // Send the char. + HWREG(ui32Base + UART_O_DR) = ui8Data; +} + +//***************************************************************************** +// +// Registers an interrupt handler for a UART interrupt +// +//***************************************************************************** +void +UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Register and enable the interrupt handler. + // (Doing the '& 0xFFFF' to catch both buffered and unbufferd offsets) + if (( ui32Base & 0xFFFF ) == ( UART0_BASE & 0xFFFF )) { + IntRegister(INT_UART0_COMB, pfnHandler); + IntEnable(INT_UART0_COMB); + } else { + IntRegister(INT_UART1_COMB, pfnHandler); + IntEnable(INT_UART1_COMB); + } +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for a UART interrupt +// +//***************************************************************************** +void +UARTIntUnregister(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Disable and unregister the interrupt. + // (Doing the '& 0xFFFF' to catch both buffered and unbufferd offsets) + if (( ui32Base & 0xFFFF ) == ( UART0_BASE & 0xFFFF )) { + IntDisable(INT_UART0_COMB); + IntUnregister(INT_UART0_COMB); + } else { + IntDisable(INT_UART1_COMB); + IntUnregister(INT_UART1_COMB); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart.h new file mode 100644 index 0000000..138c86c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart.h @@ -0,0 +1,1097 @@ +/****************************************************************************** +* Filename: uart.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Defines and prototypes for the UART. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_uart.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet + #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk + #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk + #define UARTDisable NOROM_UARTDisable + #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking + #define UARTCharGet NOROM_UARTCharGet + #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking + #define UARTCharPut NOROM_UARTCharPut + #define UARTIntRegister NOROM_UARTIntRegister + #define UARTIntUnregister NOROM_UARTIntUnregister +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ui32IntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_EOT ( UART_IMSC_EOTIM ) // End Of Transmission Interrupt Mask +#define UART_INT_OE ( UART_IMSC_OEIM ) // Overrun Error Interrupt Mask +#define UART_INT_BE ( UART_IMSC_BEIM ) // Break Error Interrupt Mask +#define UART_INT_PE ( UART_IMSC_PEIM ) // Parity Error Interrupt Mask +#define UART_INT_FE ( UART_IMSC_FEIM ) // Framing Error Interrupt Mask +#define UART_INT_RT ( UART_IMSC_RTIM ) // Receive Timeout Interrupt Mask +#define UART_INT_TX ( UART_IMSC_TXIM ) // Transmit Interrupt Mask +#define UART_INT_RX ( UART_IMSC_RXIM ) // Receive Interrupt Mask +#define UART_INT_CTS ( UART_IMSC_CTSMIM ) // CTS Modem Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter +// and returned by UARTConfigGetExpClk in the pui32Config parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ui32Parity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32TxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32RxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 + +//***************************************************************************** +// +// Values returned from the UARTBusy(). +// +//***************************************************************************** +#define UART_BUSY 0x00000001 +#define UART_IDLE 0x00000000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks a UART base address. +//! +//! This function determines if a UART port base address is valid. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +UARTBaseValid(uint32_t ui32Base) +{ + return(( ui32Base == UART0_BASE ) || ( ui32Base == UART0_NONBUF_BASE ) || + ( ui32Base == UART1_BASE ) || ( ui32Base == UART1_NONBUF_BASE ) ); +} +#endif + +//***************************************************************************** +// +//! \brief Sets the type of parity. +//! +//! This function sets the type of parity to use for transmitting and expect +//! when receiving. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Parity specifies the type of parity to use. The last two allow +//! direct control of the parity bit; it is always either one or zero based on +//! the mode. +//! - \ref UART_CONFIG_PAR_NONE +//! - \ref UART_CONFIG_PAR_EVEN +//! - \ref UART_CONFIG_PAR_ODD +//! - \ref UART_CONFIG_PAR_ONE +//! - \ref UART_CONFIG_PAR_ZERO +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) || + (ui32Parity == UART_CONFIG_PAR_EVEN) || + (ui32Parity == UART_CONFIG_PAR_ODD) || + (ui32Parity == UART_CONFIG_PAR_ONE) || + (ui32Parity == UART_CONFIG_PAR_ZERO)); + + // Set the parity mode. + HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & + ~(UART_LCRH_SPS | UART_LCRH_EPS | + UART_LCRH_PEN)) | ui32Parity); +} + +//***************************************************************************** +// +//! \brief Gets the type of parity currently being used. +//! +//! This function gets the type of parity used for transmitting data and +//! expected when receiving data. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns the current parity settings, specified as one of: +//! - \ref UART_CONFIG_PAR_NONE +//! - \ref UART_CONFIG_PAR_EVEN +//! - \ref UART_CONFIG_PAR_ODD +//! - \ref UART_CONFIG_PAR_ONE +//! - \ref UART_CONFIG_PAR_ZERO +// +//***************************************************************************** +__STATIC_INLINE uint32_t +UARTParityModeGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the current parity setting + return(HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +//! \brief Sets the FIFO level at which interrupts are generated. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one of: +//! - \ref UART_FIFO_TX1_8 +//! - \ref UART_FIFO_TX2_8 +//! - \ref UART_FIFO_TX4_8 +//! - \ref UART_FIFO_TX6_8 +//! - \ref UART_FIFO_TX7_8 +//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of: +//! - \ref UART_FIFO_RX1_8 +//! - \ref UART_FIFO_RX2_8 +//! - \ref UART_FIFO_RX4_8 +//! - \ref UART_FIFO_RX6_8 +//! - \ref UART_FIFO_RX7_8 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, + uint32_t ui32RxLevel) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32TxLevel == UART_FIFO_TX1_8) || + (ui32TxLevel == UART_FIFO_TX2_8) || + (ui32TxLevel == UART_FIFO_TX4_8) || + (ui32TxLevel == UART_FIFO_TX6_8) || + (ui32TxLevel == UART_FIFO_TX7_8)); + ASSERT((ui32RxLevel == UART_FIFO_RX1_8) || + (ui32RxLevel == UART_FIFO_RX2_8) || + (ui32RxLevel == UART_FIFO_RX4_8) || + (ui32RxLevel == UART_FIFO_RX6_8) || + (ui32RxLevel == UART_FIFO_RX7_8)); + + // Set the FIFO interrupt levels. + HWREG(ui32Base + UART_O_IFLS) = ui32TxLevel | ui32RxLevel; +} + +//***************************************************************************** +// +//! \brief Gets the FIFO level at which interrupts are generated. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of: +//! - \ref UART_FIFO_TX1_8 +//! - \ref UART_FIFO_TX2_8 +//! - \ref UART_FIFO_TX4_8 +//! - \ref UART_FIFO_TX6_8 +//! - \ref UART_FIFO_TX7_8 +//! \param pui32RxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of: +//! - \ref UART_FIFO_RX1_8 +//! - \ref UART_FIFO_RX2_8 +//! - \ref UART_FIFO_RX4_8 +//! - \ref UART_FIFO_RX6_8 +//! - \ref UART_FIFO_RX7_8 +//! +//! \return None +// +//***************************************************************************** +extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel); + +//***************************************************************************** +// +//! \brief Sets the configuration of a UART. +//! +//! This function configures the UART for operation in the specified data +//! format. +//! +//! \note The peripheral clock is not necessarily the same as the processor +//! clock. The frequency of the peripheral clock is set by the system control. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param ui32Baud is the desired baud rate. +//! - Minimum baud rate: ui32Baud >= ceil(ui32UARTClk / 1,048,559.875) +//! - Maximum baud rate: ui32Baud <= floor(ui32UARTClk / 15.875) +//! \param ui32Config is the data format for the port. +//! The parameter is the bitwise OR of three values: +//! - Number of data bits +//! - \ref UART_CONFIG_WLEN_8 : 8 data bits per byte. +//! - \ref UART_CONFIG_WLEN_7 : 7 data bits per byte. +//! - \ref UART_CONFIG_WLEN_6 : 6 data bits per byte. +//! - \ref UART_CONFIG_WLEN_5 : 5 data bits per byte. +//! - Number of stop bits +//! - \ref UART_CONFIG_STOP_ONE : One stop bit. +//! - \ref UART_CONFIG_STOP_TWO : Two stop bits. +//! - Parity +//! - \ref UART_CONFIG_PAR_NONE +//! - \ref UART_CONFIG_PAR_EVEN +//! - \ref UART_CONFIG_PAR_ODD +//! - \ref UART_CONFIG_PAR_ONE +//! - \ref UART_CONFIG_PAR_ZERO +//! +//! \return None +// +//***************************************************************************** +extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config); + +//***************************************************************************** +// +//! \brief Gets the current configuration of a UART. +//! +//! The baud rate and data format for the UART is determined, given an +//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an "official" baud rate. The data format returned in +//! \c pui32Config is enumerated the same as the \c ui32Config parameter of +//! \ref UARTConfigSetExpClk(). +//! +//! \note The peripheral clock is not necessarily the same as the processor +//! clock. The frequency of the peripheral clock is set by the system control. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param pui32Baud is a pointer to storage for the baud rate. +//! \param pui32Config is a pointer to storage for the data format. +//! +//! \return None +// +//***************************************************************************** +extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config); + +//***************************************************************************** +// +//! \brief Enables transmitting and receiving. +//! +//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit +//! and receive FIFOs. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Enable the FIFO. + HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; + + // Enable RX, TX, and the UART. + HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +//! \brief Disables transmitting and receiving. +//! +//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of +//! transmission of the current character, and flushes the transmit FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +extern void UARTDisable(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables the transmit and receive FIFOs. +//! +//! This functions enables the transmit and receive FIFOs in the UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTFIFOEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Enable the FIFO. + HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; +} + +//***************************************************************************** +// +//! \brief Disables the transmit and receive FIFOs. +//! +//! This functions disables the transmit and receive FIFOs in the UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTFIFODisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Disable the FIFO. + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); +} + +//***************************************************************************** +// +//! \brief Determines if there are any characters in the receive FIFO. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns status of the receive FIFO. +//! - \c true : There is data in the receive FIFO. +//! - \c false : There is no data in the receive FIFO. +// +//***************************************************************************** +__STATIC_INLINE bool +UARTCharsAvail(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the availability of characters. + return((HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) ? false : true); +} + +//***************************************************************************** +// +//! \brief Determines if there is any space in the transmit FIFO. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns status of the transmit FIFO. +//! - \c true : There is space available in the transmit FIFO. +//! - \c false : There is no space available in the transmit FIFO. +// +//***************************************************************************** +__STATIC_INLINE bool +UARTSpaceAvail(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the availability of space. + return((HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) ? false : true); +} + +//***************************************************************************** +// +//! \brief Receives a character from the specified port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. +//! +//! \note The \ref UARTCharsAvail() function should be called before +//! attempting to call this function. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns the character read from the specified port, cast as an +//! \c int32_t. A \c -1 is returned if there are no characters present in the +//! receive FIFO. +//! +//! \sa \ref UARTCharsAvail() +// +//***************************************************************************** +extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Waits for a character from the specified port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. If there are no characters available, this function waits until a +//! character is received before returning. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns the character read from the specified port, cast as an +//! \c int32_t. +// +//***************************************************************************** +extern int32_t UARTCharGet(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Sends a character to the specified port. +//! +//! This function writes the character \c ui8Data to the transmit FIFO for the +//! specified port. This function does not block, so if there is no space +//! available, then a \c false is returned, and the application must retry the +//! function later. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui8Data is the character to be transmitted. +//! +//! \return Returns status of the character transmit. +//! - \c true : The character was successfully placed in the transmit FIFO. +//! - \c false : There was no space available in the transmit FIFO. Try again later. +// +//***************************************************************************** +extern bool UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data); + +//***************************************************************************** +// +//! \brief Waits to send a character from the specified port. +//! +//! This function sends the character \c ui8Data to the transmit FIFO for the +//! specified port. If there is no space available in the transmit FIFO, this +//! function waits until there is space available before returning. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui8Data is the character to be transmitted. +//! +//! \return None +// +//***************************************************************************** +extern void UARTCharPut(uint32_t ui32Base, uint8_t ui8Data); + +//***************************************************************************** +// +//! \brief Determines whether the UART transmitter is busy or not. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \c false is returned, the transmit FIFO is +//! empty and all bits of the last transmitted character, including all stop +//! bits, have left the hardware shift register. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns status of UART transmitter. +//! - \c true : UART is transmitting. +//! - \c false : All transmissions are complete. +// +//***************************************************************************** +__STATIC_INLINE bool +UARTBusy(uint32_t ui32Base) +{ + // Check the argument. + ASSERT(UARTBaseValid(ui32Base)); + + // Determine if the UART is busy. + return((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? + UART_BUSY : UART_IDLE); +} + +//***************************************************************************** +// +//! \brief Causes a BREAK to be sent. +//! +//! \note For proper transmission of a break +//! command, the break must be asserted for at least two complete frames. +//! +//! \param ui32Base is the base address of the UART port. +//! \param bBreakState controls the output level. +//! - \c true : Asserts a break condition on the UART. +//! - \c false : Removes the break condition. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTBreakCtl(uint32_t ui32Base, bool bBreakState) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Set the break condition as requested. + HWREG(ui32Base + UART_O_LCRH) = + (bBreakState ? + (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : + (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for a UART interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific UART interrupts must be enabled via \ref UARTIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \param ui32Base is the base address of the UART module. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a UART interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a UART interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \param ui32Base is the base address of the UART module. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void UARTIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables individual UART interrupt sources. +//! +//! This function enables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UART_INT_EOT : End Of Transmission interrupt. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(ui32Base + UART_O_IMSC) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual UART interrupt sources. +//! +//! This function disables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! - \ref UART_INT_EOT : End Of Transmission interrupt. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(ui32Base + UART_O_IMSC) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the specified UART. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the UART port. +//! \param bMasked selects either raw or masked interrupt. +//! - \c true : Masked interrupt status is required. +//! - \c false : Raw interrupt status is required. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of: +//! - \ref UART_INT_EOT : End Of Transmission interrupt. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +UARTIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return(HWREG(ui32Base + UART_O_MIS)); + } + else + { + return(HWREG(ui32Base + UART_O_RIS)); + } +} + +//***************************************************************************** +// +//! \brief Clears UART interrupt sources. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref UART_INT_EOT : End Of Transmission interrupt. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments + ASSERT(UARTBaseValid(ui32Base)); + + // Clear the requested interrupt sources + HWREG(ui32Base + UART_O_ICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Enable UART DMA operation. +//! +//! The specified UART DMA features are enabled. The UART can be +//! configured to use DMA for transmit or receive, and to disable +//! receive if an error occurs. +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the UART. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32DMAFlags is a bit mask of the DMA features to enable. +//! The parameter is the bitwise OR of any of the following values: +//! - UART_DMA_RX : Enable DMA for receive. +//! - UART_DMA_TX : Enable DMA for transmit. +//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Set the requested bits in the UART DMA control register. + HWREG(ui32Base + UART_O_DMACTL) |= ui32DMAFlags; +} + +//***************************************************************************** +// +//! \brief Disable UART DMA operation. +//! +//! This function is used to disable UART DMA features that were enabled +//! by \ref UARTDMAEnable(). The specified UART DMA features are disabled. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32DMAFlags is a bit mask of the DMA features to disable. +//! The parameter is the bitwise OR of any of the following values: +//! - UART_DMA_RX : Enable DMA for receive. +//! - UART_DMA_TX : Enable DMA for transmit. +//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Clear the requested bits in the UART DMA control register. + HWREG(ui32Base + UART_O_DMACTL) &= ~ui32DMAFlags; +} + +//***************************************************************************** +// +//! \brief Gets current receiver errors. +//! +//! This function returns the current state of each of the 4 receiver error +//! sources. The returned errors are equivalent to the four error bits +//! returned via the previous call to \ref UARTCharGet() or \ref UARTCharGetNonBlocking() +//! with the exception that the overrun error is set immediately the overrun +//! occurs rather than when a character is next read. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns a bitwise OR combination of the receiver error flags: +//! - \ref UART_RXERROR_FRAMING +//! - \ref UART_RXERROR_PARITY +//! - \ref UART_RXERROR_BREAK +//! - \ref UART_RXERROR_OVERRUN +// +//***************************************************************************** +__STATIC_INLINE uint32_t +UARTRxErrorGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the current value of the receive status register. + return(HWREG(ui32Base + UART_O_RSR) & 0x0000000F); +} + +//***************************************************************************** +// +//! \brief Clears all reported receiver errors. +//! +//! This function is used to clear all receiver error conditions reported via +//! \ref UARTRxErrorGet(). If using the overrun, framing error, parity error or +//! break interrupts, this function must be called after clearing the interrupt +//! to ensure that later errors of the same type trigger another interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTRxErrorClear(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Any write to the Error Clear Register will clear all bits which are + // currently set. + HWREG(ui32Base + UART_O_ECR) = 0; +} + +//***************************************************************************** +// +//! \brief Enables hardware flow control for both CTS and RTS +//! +//! Hardware flow control is disabled by default. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTHwFlowControlEnable( uint32_t ui32Base ) +{ + // Check the arguments. + ASSERT( UARTBaseValid( ui32Base )); + + HWREG( ui32Base + UART_O_CTL ) |= ( UART_CTL_CTSEN | UART_CTL_RTSEN ); +} + +//***************************************************************************** +// +//! \brief Disables hardware flow control for both CTS and RTS +//! +//! Hardware flow control is disabled by default. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTHwFlowControlDisable( uint32_t ui32Base ) +{ + // Check the arguments. + ASSERT( UARTBaseValid( ui32Base )); + + HWREG( ui32Base + UART_O_CTL ) &= ~( UART_CTL_CTSEN | UART_CTL_RTSEN ); +} + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_UARTFIFOLevelGet + #undef UARTFIFOLevelGet + #define UARTFIFOLevelGet ROM_UARTFIFOLevelGet + #endif + #ifdef ROM_UARTConfigSetExpClk + #undef UARTConfigSetExpClk + #define UARTConfigSetExpClk ROM_UARTConfigSetExpClk + #endif + #ifdef ROM_UARTConfigGetExpClk + #undef UARTConfigGetExpClk + #define UARTConfigGetExpClk ROM_UARTConfigGetExpClk + #endif + #ifdef ROM_UARTDisable + #undef UARTDisable + #define UARTDisable ROM_UARTDisable + #endif + #ifdef ROM_UARTCharGetNonBlocking + #undef UARTCharGetNonBlocking + #define UARTCharGetNonBlocking ROM_UARTCharGetNonBlocking + #endif + #ifdef ROM_UARTCharGet + #undef UARTCharGet + #define UARTCharGet ROM_UARTCharGet + #endif + #ifdef ROM_UARTCharPutNonBlocking + #undef UARTCharPutNonBlocking + #define UARTCharPutNonBlocking ROM_UARTCharPutNonBlocking + #endif + #ifdef ROM_UARTCharPut + #undef UARTCharPut + #define UARTCharPut ROM_UARTCharPut + #endif + #ifdef ROM_UARTIntRegister + #undef UARTIntRegister + #define UARTIntRegister ROM_UARTIntRegister + #endif + #ifdef ROM_UARTIntUnregister + #undef UARTIntUnregister + #define UARTIntUnregister ROM_UARTIntUnregister + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart_doc.h new file mode 100644 index 0000000..ba77f94 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart_doc.h @@ -0,0 +1,107 @@ +/****************************************************************************** +* Filename: uart_doc.h +* Revised: 2018-02-09 15:45:36 +0100 (fr, 09 feb 2018) +* Revision: 51470 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +/*! +\addtogroup uart_api +@{ + +\section sec_uart_printf Use printf() + +DriverLib only supports writing a single character at a time to the UART buffer but it is +possible to utilize the library function \c printf by overriding a few of the functions used by +\c printf with a device specific definition. However, the implementation of \c printf is +compiler specific and requires different functions to be overridden depending on the compiler. + +Using \c printf can increase code size significantly but some compilers provide a highly optimized +and configurable implementation suitable for embedded systems which makes the code size increase +acceptable for most applications. See the compiler's documentation for details about how to +configure the \c printf library function. + +It is required that the application configures and enables the UART module before using \c printf +function. + +\subsection sec_uart_printf_ccs Code Composer Studio + +In Code Composer Studio the functions \c fputc and \c fputs must be overridden. + +\code{.c} +#include +#include + +#define PRINTF_UART UART0_BASE + +// Override 'fputc' function in order to use printf() to output to UART +int fputc(int _c, register FILE *_fp) +{ + UARTCharPut(PRINTF_UART, (uint8_t)_c); + return _c; +} + +// Override 'fputs' function in order to use printf() to output to UART +int fputs(const char *_ptr, register FILE *_fp) +{ + unsigned int i, len; + + len = strlen(_ptr); + + for(i=0 ; i +#include + +#define PRINTF_UART UART0_BASE + +// Override 'putchar' function in order to use printf() to output to UART. +int putchar(int data) +{ + UARTCharPut(PRINTF_UART, (uint8_t)data); + return data; +} +\endcode + +@} +*/ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/udma.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/udma.c new file mode 100644 index 0000000..0665a42 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/udma.c @@ -0,0 +1,448 @@ +/****************************************************************************** +* Filename: udma.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the uDMA controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "udma.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef uDMAChannelAttributeEnable + #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable + #undef uDMAChannelAttributeDisable + #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable + #undef uDMAChannelAttributeGet + #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet + #undef uDMAChannelControlSet + #define uDMAChannelControlSet NOROM_uDMAChannelControlSet + #undef uDMAChannelTransferSet + #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet + #undef uDMAChannelScatterGatherSet + #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet + #undef uDMAChannelSizeGet + #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet + #undef uDMAChannelModeGet + #define uDMAChannelModeGet NOROM_uDMAChannelModeGet +#endif + +//***************************************************************************** +// +// Enables attributes of a uDMA channel +// +//***************************************************************************** +void +uDMAChannelAttributeEnable(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32Attr) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Set the useburst bit for this channel if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_SETBURST) = 1 << ui32ChannelNum; + } + + // Set the alternate control select bit for this channel, + // if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // Set the high priority bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // Set the request mask bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_SETREQMASK) = 1 << ui32ChannelNum; + } +} + +//***************************************************************************** +// +// Disables attributes of an uDMA channel +// +//***************************************************************************** +void +uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32Attr) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Clear the useburst bit for this channel if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_CLEARBURST) = 1 << ui32ChannelNum; + } + + // Clear the alternate control select bit for this channel, if set in + // ululAttr. + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // Clear the high priority bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // Clear the request mask bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_CLEARREQMASK) = 1 << ui32ChannelNum; + } +} + +//***************************************************************************** +// +// Gets the enabled attributes of a uDMA channel +// +//***************************************************************************** +uint32_t +uDMAChannelAttributeGet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + uint32_t ui32Attr = 0; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Check to see if useburst bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETBURST) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_USEBURST; + } + + // Check to see if the alternate control bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_ALTSELECT; + } + + // Check to see if the high priority bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // Check to see if the request mask bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETREQMASK) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_REQMASK; + } + + // Return the configuration flags. + return(ui32Attr); +} + +//***************************************************************************** +// +// Sets the control parameters for a uDMA channel control structure +// +//***************************************************************************** +void +uDMAChannelControlSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, + uint32_t ui32Control) +{ + tDMAControlTable *pControlTable; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + pControlTable[ui32ChannelStructIndex].ui32Control = + ((pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_DST_INC_M | + UDMA_SRC_INC_M | + UDMA_SIZE_M | + UDMA_ARB_M | + UDMA_NEXT_USEBURST)) | + ui32Control); +} + +//***************************************************************************** +// +// Sets the transfer parameters for a uDMA channel control structure +// +//***************************************************************************** +void +uDMAChannelTransferSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, + uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, + uint32_t ui32TransferSize) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + uint32_t ui32Inc; + uint32_t ui32BufferBytes; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((uint32_t)pvSrcAddr >= SRAM_BASE); + ASSERT((uint32_t)pvDstAddr >= SRAM_BASE); + ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= UDMA_XFER_SIZE_MAX)); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off the mode and size + // fields. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // Adjust the mode if the alt control structure is selected. + if(ui32ChannelStructIndex & UDMA_ALT_SELECT) + { + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Mode |= UDMA_MODE_ALT_SELECT; + } + } + + // Set the transfer size and mode in the control word (but don't write the + // control word yet as it could kick off a transfer). + ui32Control |= ui32Mode | ((ui32TransferSize - 1) << UDMA_XFER_SIZE_S); + + // Get the address increment value for the source, from the control word. + ui32Inc = (ui32Control & UDMA_SRC_INC_M); + + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + if(ui32Inc != UDMA_SRC_INC_NONE) + { + ui32Inc = ui32Inc >> UDMA_SRC_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - (1 << ui32Inc)); + } + + // Load the source ending address into the control block. + pControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; + + // Get the address increment value for the destination, from the control + // word. + ui32Inc = ui32Control & UDMA_DST_INC_M; + + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + if(ui32Inc != UDMA_DST_INC_NONE) + { + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer needs to point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + pvDstAddr = + (void *)&pControlTable[ui32ChannelStructIndex | + UDMA_ALT_SELECT].ui32Spare; + } + // Not a scatter-gather transfer, calculate end pointer normally. + else + { + ui32Inc = ui32Inc >> UDMA_DST_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); + } + } + + // Load the destination ending address into the control block. + pControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; + + // Write the new control word value. + pControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; +} + +//***************************************************************************** +// +// Configures a uDMA channel for scatter-gather mode +// +//***************************************************************************** +void +uDMAChannelScatterGatherSet(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32TaskCount, void *pvTaskList, + uint32_t ui32IsPeriphSG) +{ + tDMAControlTable *pControlTable; + tDMAControlTable *pTaskTable; + + // Check the parameters. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(pvTaskList != 0); + ASSERT(ui32TaskCount <= UDMA_XFER_SIZE_MAX); + ASSERT(ui32TaskCount != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get a handy pointer to the task list. + pTaskTable = (tDMAControlTable *)pvTaskList; + + // Compute the ending address for the source pointer. This will be the + // last element of the last task in the task table. + pControlTable[ui32ChannelNum].pvSrcEndAddr = + &pTaskTable[ui32TaskCount - 1].ui32Spare; + + // Compute the ending address for the destination pointer. This will be + // the end of the alternate structure for this channel. + pControlTable[ui32ChannelNum].pvDstEndAddr = + &pControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; + + // Compute the control word. Most configurable items are fixed for + // scatter-gather. Item and increment sizes are all 32-bit and arb + // size must be 4. The count is the number of items in the task list + // times 4 (4 words per task). + pControlTable[ui32ChannelNum].ui32Control = + (UDMA_DST_INC_32 | UDMA_SRC_INC_32 | + UDMA_SIZE_32 | UDMA_ARB_4 | + (((ui32TaskCount * 4) - 1) << UDMA_XFER_SIZE_S) | + (ui32IsPeriphSG ? UDMA_MODE_PER_SCATTER_GATHER : + UDMA_MODE_MEM_SCATTER_GATHER)); + + // Scatter-gather operations can leave the alt bit set. So if doing + // back to back scatter-gather transfers, the second attempt may not + // work correctly because the alt bit is set. Therefore, clear the + // alt bit here to ensure that it is always cleared before a new SG + // transfer is started. + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + +} + +//***************************************************************************** +// +// Gets the current transfer size for a uDMA channel control structure +// +//***************************************************************************** +uint32_t +uDMAChannelSizeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off all but the size field + // and the mode field. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + (UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // If the size field and mode field are 0 then the transfer is finished + // and there are no more items to transfer. + if(ui32Control == 0) + { + return(0); + } + + // Otherwise, if either the size field or more field is non-zero, then + // not all the items have been transferred. + else + { + // Shift the size field and add one, then return to user. + return((ui32Control >> UDMA_XFER_SIZE_S) + 1); + } +} + +//***************************************************************************** +// +// Gets the transfer mode for a uDMA channel control structure +// +//***************************************************************************** +uint32_t +uDMAChannelModeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off all but the mode field. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + UDMA_MODE_M); + + // Check if scatter/gather mode, and if so, mask off the alt bit. + if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || + ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Control &= ~UDMA_MODE_ALT_SELECT; + } + + // Return the mode to the caller. + return(ui32Control); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/udma.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/udma.h new file mode 100644 index 0000000..443da6e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/udma.h @@ -0,0 +1,1240 @@ +/****************************************************************************** +* Filename: udma.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and prototypes for the uDMA controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup udma_api +//! @{ +// +//***************************************************************************** + +#ifndef __UDMA_H__ +#define __UDMA_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_udma.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable + #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable + #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet + #define uDMAChannelControlSet NOROM_uDMAChannelControlSet + #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet + #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet + #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet + #define uDMAChannelModeGet NOROM_uDMAChannelModeGet +#endif + +//***************************************************************************** +// +//! \brief A structure that defines an entry in the channel control table. +//! +//! These fields are used by the uDMA controller and normally it is not necessary for +//! software to directly read or write fields in the table. +// +//***************************************************************************** +typedef struct +{ + volatile void *pvSrcEndAddr; //!< The ending source address of the data transfer. + volatile void *pvDstEndAddr; //!< The ending destination address of the data transfer. + volatile uint32_t ui32Control; //!< The channel control mode. + volatile uint32_t ui32Spare; //!< An unused location. +} +tDMAControlTable; + +//***************************************************************************** +// +//! \brief A helper macro for building scatter-gather task table entries. +//! +//! This macro is intended to be used to help populate a table of uDMA tasks +//! for a scatter-gather transfer. This macro will calculate the values for +//! the fields of a task structure entry based on the input parameters. +//! +//! There are specific requirements for the values of each parameter. No +//! checking is done so it is up to the caller to ensure that correct values +//! are used for the parameters. +//! +//! This macro is intended to be used to initialize individual entries of +//! a structure of tDMAControlTable type, like this: +//! +/*! +\verbatim + tDMAControlTable MyTaskList[] = + { + uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, + UDMA_SRC_INC_8, MySourceBuf, + UDMA_DST_INC_8, MyDestBuf, + UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), + uDMATaskStructEntry(Task2Count, ... ), + } +\endverbatim +*/ +//! \param ui32TransferCount is the count of items to transfer for this task. +//! It must be in the range 1-1024. +//! \param ui32ItemSize is the bit size of the items to transfer for this task. +//! It must be one of: +//! - \ref UDMA_SIZE_8 +//! - \ref UDMA_SIZE_16 +//! - \ref UDMA_SIZE_32 +//! \param ui32SrcIncrement is the bit size increment for source data. +//! It must be one of: +//! - \ref UDMA_SRC_INC_8 +//! - \ref UDMA_SRC_INC_16 +//! - \ref UDMA_SRC_INC_32 +//! - \ref UDMA_SRC_INC_NONE +//! \param pvSrcAddr is the starting address of the data to transfer. +//! \param ui32DstIncrement is the bit size increment for destination data. +//! It must be one of: +//! - \ref UDMA_DST_INC_8 +//! - \ref UDMA_DST_INC_16 +//! - \ref UDMA_DST_INC_32 +//! - \ref UDMA_DST_INC_NONE +//! \param pvDstAddr is the starting address of the destination data. +//! \param ui32ArbSize is the arbitration size to use for the transfer task. +//! This is used to select the arbitration size in powers of 2, from 1 to 1024. +//! It must be one of: +//! - \ref UDMA_ARB_1 +//! - \ref UDMA_ARB_2 +//! - \ref UDMA_ARB_4 +//! - ... +//! - \ref UDMA_ARB_1024 +//! \param ui32Mode is the transfer mode for this task. +//! Note that normally all tasks will be one of the scatter-gather modes while the +//! last task is a task list will be AUTO or BASIC. +//! It must be one of: +//! - \ref UDMA_MODE_BASIC +//! - \ref UDMA_MODE_AUTO +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER +//! - \ref UDMA_MODE_PER_SCATTER_GATHER +//! +//! \return None (this is not a function) +// +//***************************************************************************** +#define uDMATaskStructEntry(ui32TransferCount, \ + ui32ItemSize, \ + ui32SrcIncrement, \ + pvSrcAddr, \ + ui32DstIncrement, \ + pvDstAddr, \ + ui32ArbSize, \ + ui32Mode) \ + { \ + (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : \ + ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \ + ((ui32SrcIncrement) >> 26)) - 1]))), \ + (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : \ + ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \ + ((ui32DstIncrement) >> 30)) - 1]))), \ + (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ + (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \ + ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ + ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ + (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \ + } + +//***************************************************************************** +// +// The hardware configured number of uDMA channels. +// +//***************************************************************************** +#define UDMA_NUM_CHANNELS 21 + +//***************************************************************************** +// +// The level of priority for the uDMA channels +// +//***************************************************************************** +#define UDMA_PRIORITY_LOW 0x00000000 +#define UDMA_PRIORITY_HIGH 0x00000001 + +//***************************************************************************** +// +// Flags that can be passed to uDMAChannelAttributeEnable(), +// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). +// +//***************************************************************************** +#define UDMA_ATTR_USEBURST 0x00000001 +#define UDMA_ATTR_ALTSELECT 0x00000002 +#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 +#define UDMA_ATTR_REQMASK 0x00000008 +#define UDMA_ATTR_ALL 0x0000000F + +//***************************************************************************** +// +// DMA control modes that can be passed to uDMAChannelModeSet() and returned +// uDMAChannelModeGet(). +// +//***************************************************************************** +#define UDMA_MODE_STOP 0x00000000 +#define UDMA_MODE_BASIC 0x00000001 +#define UDMA_MODE_AUTO 0x00000002 +#define UDMA_MODE_PINGPONG 0x00000003 +#define UDMA_MODE_MEM_SCATTER_GATHER \ + 0x00000004 +#define UDMA_MODE_PER_SCATTER_GATHER \ + 0x00000006 +#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_MODE_ALT_SELECT 0x00000001 + +//***************************************************************************** +// +// Channel configuration values that can be passed to uDMAControlSet(). +// +//***************************************************************************** +#define UDMA_DST_INC_8 0x00000000 +#define UDMA_DST_INC_16 0x40000000 +#define UDMA_DST_INC_32 0x80000000 +#define UDMA_DST_INC_NONE 0xC0000000 +#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment +#define UDMA_DST_INC_S 30 +#define UDMA_SRC_INC_8 0x00000000 +#define UDMA_SRC_INC_16 0x04000000 +#define UDMA_SRC_INC_32 0x08000000 +#define UDMA_SRC_INC_NONE 0x0c000000 +#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment +#define UDMA_SRC_INC_S 26 +#define UDMA_SIZE_8 0x00000000 +#define UDMA_SIZE_16 0x11000000 +#define UDMA_SIZE_32 0x22000000 +#define UDMA_SIZE_M 0x33000000 // Data Size +#define UDMA_SIZE_S 24 +#define UDMA_ARB_1 0x00000000 +#define UDMA_ARB_2 0x00004000 +#define UDMA_ARB_4 0x00008000 +#define UDMA_ARB_8 0x0000c000 +#define UDMA_ARB_16 0x00010000 +#define UDMA_ARB_32 0x00014000 +#define UDMA_ARB_64 0x00018000 +#define UDMA_ARB_128 0x0001c000 +#define UDMA_ARB_256 0x00020000 +#define UDMA_ARB_512 0x00024000 +#define UDMA_ARB_1024 0x00028000 +#define UDMA_ARB_M 0x0003C000 // Arbitration Size +#define UDMA_ARB_S 14 +#define UDMA_NEXT_USEBURST 0x00000008 +#define UDMA_XFER_SIZE_MAX 1024 +#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size +#define UDMA_XFER_SIZE_S 4 + +//***************************************************************************** +// +// Channel numbers to be passed to API functions that require a channel number +// ID. +// +//***************************************************************************** +#define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0 +#define UDMA_CHAN_UART0_RX 1 // UART0 RX Data +#define UDMA_CHAN_UART0_TX 2 // UART0 RX Data +#define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data +#define UDMA_CHAN_SSI0_TX 4 // SSI0 RX Data +#define UDMA_CHAN_AUX_ADC 7 // AUX ADC event +#define UDMA_CHAN_AUX_SW 8 // AUX Software event +#define UDMA_CHAN_TIMER0_A 9 // Timer0 A event +#define UDMA_CHAN_TIMER0_B 10 // Timer0 B event +#define UDMA_CHAN_TIMER1_A 11 +#define UDMA_CHAN_TIMER1_B 12 +#define UDMA_CHAN_AON_PROG2 13 +#define UDMA_CHAN_DMA_PROG 14 +#define UDMA_CHAN_AON_RTC 15 +#define UDMA_CHAN_SSI1_RX 16 +#define UDMA_CHAN_SSI1_TX 17 +#define UDMA_CHAN_SW_EVT1 18 +#define UDMA_CHAN_SW_EVT2 19 +#define UDMA_CHAN_SW_EVT3 20 + +//***************************************************************************** +// +// Flags to be OR'd with the channel ID to indicate if the primary or alternate +// control structure should be used. +// +//***************************************************************************** +#define UDMA_PRI_SELECT 0x00000000 +#define UDMA_ALT_SELECT 0x00000020 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks a uDMA base address. +//! +//! This function determines if a uDMA module base address is valid. +//! +//! \param ui32Base specifies the uDMA module base address. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +uDMABaseValid(uint32_t ui32Base) +{ + return(ui32Base == UDMA0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Enables the uDMA controller for use. +//! +//! This function enables the uDMA controller. The uDMA controller must be +//! enabled before it can be configured and used. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Set the master enable bit in the config register. + HWREG(ui32Base + UDMA_O_CFG) = UDMA_CFG_MASTERENABLE; +} + +//***************************************************************************** +// +//! \brief Disables the uDMA controller for use. +//! +//! This function disables the uDMA controller. Once disabled, the uDMA +//! controller will not operate until re-enabled with \ref uDMAEnable(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +uDMADisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Clear the master enable bit in the config register. + HWREG(ui32Base + UDMA_O_CFG) = 0; +} + +//***************************************************************************** +// +//! \brief Gets the uDMA error status. +//! +//! This function returns the uDMA error status. It should be called from +//! within the uDMA error interrupt handler to determine if a uDMA error +//! occurred. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Returns non-zero if a uDMA error is pending. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +uDMAErrorStatusGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Return the uDMA error status. + return(HWREG(ui32Base + UDMA_O_ERROR)); +} + +//***************************************************************************** +// +//! \brief Clears the uDMA error interrupt. +//! +//! This function clears a pending uDMA error interrupt. It should be called +//! from within the uDMA error interrupt handler to clear the interrupt. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAErrorStatusClear(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Clear the uDMA error interrupt. + HWREG(ui32Base + UDMA_O_ERROR) = UDMA_ERROR_STATUS; +} + +//***************************************************************************** +// +//! \brief Enables a uDMA channel for operation. +//! +//! This function enables a specific uDMA channel for use. This function must +//! be used to enable a channel before it can be used to perform a uDMA +//! transfer. +//! +//! When a uDMA transfer is completed, the channel will be automatically +//! disabled by the uDMA controller. Therefore, this function should be called +//! prior to starting up any new transfer. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number to enable. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelEnable(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the bit for this channel in the enable set register. + HWREG(ui32Base + UDMA_O_SETCHANNELEN) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Disables a uDMA channel for operation. +//! +//! This function disables a specific uDMA channel. Once disabled, a channel +//! will not respond to uDMA transfer requests until re-enabled via +//! \ref uDMAChannelEnable(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number to disable. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelDisable(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the bit for this channel in the enable clear register. + HWREG(ui32Base + UDMA_O_CLEARCHANNELEN) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Checks if a uDMA channel is enabled for operation. +//! +//! This function checks to see if a specific uDMA channel is enabled. This +//! can be used to check the status of a transfer, since the channel will +//! be automatically disabled at the end of a transfer. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number to check. +//! +//! \return Returns status of uDMA channel. +//! - \c true : Channel is enabled. +//! - \c false : Disabled. +// +//***************************************************************************** +__STATIC_INLINE bool +uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // AND the specified channel bit with the enable register, and return the + // result. + return((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ? + true : false); +} + +//***************************************************************************** +// +//! \brief Sets the base address for the channel control table. +//! +//! This function sets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. The table must be aligned on a 1024 byte boundary. The base +//! address must be set before any of the channel functions can be used. +//! Setting the base address of the primary control table will automatically +//! set the address for the alternate control table as the next memory +//! location after the primary control table. +//! +//! The size of the channel control table depends on the number of uDMA +//! channels, and which transfer modes are used. Refer to the introductory +//! text and the microcontroller datasheet for more information about the +//! channel control table. +//! +//! \note This register cannot be read when the controller is in the reset +//! state. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param pControlTable is a pointer to the 1024 byte aligned base address +//! of the uDMA channel control table. The address must be an absolute address +//! in system memory space. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAControlBaseSet(uint32_t ui32Base, void *pControlTable) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(((uint32_t)pControlTable & ~0x3FF) == + (uint32_t)pControlTable); + ASSERT((uint32_t)pControlTable >= SRAM_BASE); + + // Program the base address into the register. + HWREG(ui32Base + UDMA_O_CTRL) = (uint32_t)pControlTable; +} + +//***************************************************************************** +// +//! \brief Gets the base address for the channel control table. +//! +//! This function gets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Returns a pointer to the base address of the channel control table. +// +//***************************************************************************** +__STATIC_INLINE void * +uDMAControlBaseGet(uint32_t ui32Base) +{ + // Check the arguments. + + ASSERT(uDMABaseValid(ui32Base)); + // Read the current value of the control base register, and return it to + // the caller. + return((void *)HWREG(ui32Base + UDMA_O_CTRL)); +} + +//***************************************************************************** +// +//! \brief Gets the base address for the channel control table alternate structures. +//! +//! This function gets the base address of the second half of the channel +//! control table that holds the alternate control structures for each channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Returns a pointer to the base address of the second half of the +//! channel control table. +// +//***************************************************************************** +__STATIC_INLINE void * +uDMAControlAlternateBaseGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Read the current value of the control base register, and return it to + // the caller. + return((void *)HWREG(ui32Base + UDMA_O_ALTCTRL)); +} + +//***************************************************************************** +// +//! \brief Requests a uDMA channel to start a transfer. +//! +//! This function allows software to request a uDMA channel to begin a +//! transfer. This could be used for performing a memory to memory transfer, +//! or if for some reason a transfer needs to be initiated by software instead +//! of the peripheral associated with that channel. +//! +//! \note If the channel is a software channel and interrupts are used, then +//! the completion will be signaled on the uDMA dedicated interrupt. If a +//! peripheral channel is used, then the completion will be signaled on the +//! peripheral's interrupt. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number on which to request a uDMA +//! transfer. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelRequest(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the bit for this channel in the software uDMA request register. + HWREG(ui32Base + UDMA_O_SOFTREQ) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Enables attributes of a uDMA channel. +//! +//! This function is used to enable attributes of a uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel to configure. +//! \param ui32Attr is a combination of attributes for the channel. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelAttributeEnable(uint32_t ui32Base, + uint32_t ui32ChannelNum, + uint32_t ui32Attr); + +//***************************************************************************** +// +//! \brief Disables attributes of an uDMA channel. +//! +//! This function is used to disable attributes of a uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel to configure. +//! \param ui32Attr is a combination of attributes for the channel. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelAttributeDisable(uint32_t ui32Base, + uint32_t ui32ChannelNum, + uint32_t ui32Attr); + +//***************************************************************************** +// +//! \brief Gets the enabled attributes of a uDMA channel. +//! +//! This function returns a combination of flags representing the attributes of +//! the uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel to configure. +//! +//! \return Returns the bitwise OR of the attributes of the uDMA channel, which +//! can be any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +// +//***************************************************************************** +extern uint32_t uDMAChannelAttributeGet(uint32_t ui32Base, + uint32_t ui32ChannelNum); + +//***************************************************************************** +// +//! \brief Sets the control parameters for a uDMA channel control structure. +//! +//! This function is used to set control parameters for a uDMA transfer. These +//! are typically parameters that are not changed often. +//! +//! \note The address increment cannot be smaller than the data size. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT : Use primary data structure. +//! - \ref UDMA_ALT_SELECT : Use alternate data structure. +//! \param ui32Control is the bitwise OR of five values: +//! - Data size +//! - \ref UDMA_SIZE_8 : 8 bits. +//! - \ref UDMA_SIZE_16 : 16 bits. +//! - \ref UDMA_SIZE_32 : 32 bits. +//! - Source address increment +//! - \ref UDMA_SRC_INC_8 : 8 bits. +//! - \ref UDMA_SRC_INC_16 : 16 bits. +//! - \ref UDMA_SRC_INC_32 : 32 bits. +//! - \ref UDMA_SRC_INC_NONE : Non-incrementing. +//! - Destination address increment +//! - \ref UDMA_DST_INC_8 : 8 bits. +//! - \ref UDMA_DST_INC_16 : 16 bits. +//! - \ref UDMA_DST_INC_32 : 32 bits. +//! - \ref UDMA_DST_INC_NONE : Non-incrementing. +//! - Arbitration size. Determines how many items are transferred before +//! the uDMA controller re-arbitrates for the bus. In power of 2. +//! - \ref UDMA_ARB_1 +//! - \ref UDMA_ARB_2 +//! - \ref UDMA_ARB_4 +//! - \ref UDMA_ARB_8 +//! - ... +//! - \ref UDMA_ARB_1024 +//! - Force the channel to only respond to burst requests at the tail end of a scatter-gather transfer. +//! - \ref UDMA_NEXT_USEBURST +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelControlSet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex, + uint32_t ui32Control); + +//***************************************************************************** +// +//! \brief Sets the transfer parameters for a uDMA channel control structure. +//! +//! This function is used to set the parameters for a uDMA transfer. These are +//! typically parameters that are changed often. The function +//! \ref uDMAChannelControlSet() MUST be called at least once for this channel prior +//! to calling this function. +//! +//! The \c pvSrcAddr and \c pvDstAddr parameters are pointers to the first +//! location of the data to be transferred. These addresses should be aligned +//! according to the item size. The compiler will take care of this if the +//! pointers are pointing to storage of the appropriate data type. +//! +//! The two scatter/gather modes, MEMORY and PERIPHERAL, are actually different +//! depending on whether the primary or alternate control structure is +//! selected. This function will look for the \ref UDMA_PRI_SELECT and +//! \ref UDMA_ALT_SELECT flag along with the channel number and will set the +//! scatter/gather mode as appropriate for the primary or alternate control +//! structure. +//! +//! The channel must also be enabled using \ref uDMAChannelEnable() after calling +//! this function. The transfer will not begin until the channel has been set +//! up and enabled. Note that the channel is automatically disabled after the +//! transfer is completed, meaning that \ref uDMAChannelEnable() must be called +//! again after setting up the next transfer. +//! +//! \note Great care must be taken to not modify a channel control structure +//! that is in use or else the results will be unpredictable, including the +//! possibility of undesired data transfers to or from memory or peripherals. +//! For BASIC and AUTO modes, it is safe to make changes when the channel is +//! disabled, or the \ref uDMAChannelModeGet() returns \ref UDMA_MODE_STOP. For +//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the +//! primary or alternate control structure only when the other is being used. +//! The \ref uDMAChannelModeGet() function will return \ref UDMA_MODE_STOP when a +//! channel control structure is inactive and safe to modify. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT : Use primary data structure. +//! - \ref UDMA_ALT_SELECT : Use alternate data structure. +//! \param ui32Mode is the type of uDMA transfer. +//! The parameter should be one of the following values: +//! - \ref UDMA_MODE_STOP : Stops the uDMA transfer. The controller sets the mode +//! to this value at the end of a transfer. +//! - \ref UDMA_MODE_BASIC : Perform a basic transfer based on request. +//! - \ref UDMA_MODE_AUTO to perform a transfer that will always complete once +//! started even if request is removed. +//! - \ref UDMA_MODE_PINGPONG : Set up a transfer that switches between the +//! primary and alternate control structures for the channel. This allows +//! use of ping-pong buffering for uDMA transfers. +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER : Set up a memory scatter-gather transfer. +//! - \ref UDMA_MODE_PER_SCATTER_GATHER : Set up a peripheral scatter-gather transfer. +//! \param pvSrcAddr is the source address for the transfer. +//! \param pvDstAddr is the destination address for the transfer. +//! \param ui32TransferSize is the number of data items to transfer (\b NOT bytes). +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelTransferSet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex, + uint32_t ui32Mode, void *pvSrcAddr, + void *pvDstAddr, uint32_t ui32TransferSize); + +//***************************************************************************** +// +//! \brief Configures a uDMA channel for scatter-gather mode. +//! +//! This function is used to configure a channel for scatter-gather mode. +//! The caller must have already set up a task list, and pass a pointer to +//! the start of the task list as the \c pvTaskList parameter. +//! +//! The \c ui32TaskCount parameter is the count of tasks in the task list, not the +//! size of the task list. +//! +//! The flag \c bIsPeriphSG should be used to indicate +//! if the scatter-gather should be configured for a peripheral or memory +//! scatter-gather operation. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the uDMA channel number. +//! \param ui32TaskCount is the number of scatter-gather tasks to execute. +//! \param pvTaskList is a pointer to the beginning of the scatter-gather +//! task list. +//! \param ui32IsPeriphSG is a flag to indicate it is a peripheral +//! scatter-gather transfer (else it will be memory scatter-gather transfer) +//! +//! \return None +//! +//! \sa \ref uDMATaskStructEntry() +// +//***************************************************************************** +extern void uDMAChannelScatterGatherSet(uint32_t ui32Base, + uint32_t ui32ChannelNum, + uint32_t ui32TaskCount, + void *pvTaskList, + uint32_t ui32IsPeriphSG); + +//***************************************************************************** +// +//! \brief Gets the current transfer size for a uDMA channel control structure. +//! +//! This function is used to get the uDMA transfer size for a channel. The +//! transfer size is the number of items to transfer, where the size of an item +//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, +//! then the number of remaining items will be returned. If the transfer is +//! complete, then 0 will be returned. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT +//! - \ref UDMA_ALT_SELECT +//! +//! \return Returns the number of items remaining to transfer. +// +//***************************************************************************** +extern uint32_t uDMAChannelSizeGet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex); + +//***************************************************************************** +// +//! \brief Gets the transfer mode for a uDMA channel control structure. +//! +//! This function is used to get the transfer mode for the uDMA channel. It +//! can be used to query the status of a transfer on a channel. When the +//! transfer is complete the mode will be \ref UDMA_MODE_STOP. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT +//! - \ref UDMA_ALT_SELECT +//! +//! \return Returns the transfer mode of the specified channel and control +//! structure, which will be one of the following values: +//! - \ref UDMA_MODE_STOP +//! - \ref UDMA_MODE_BASIC +//! - \ref UDMA_MODE_AUTO +//! - \ref UDMA_MODE_PINGPONG +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER +//! - \ref UDMA_MODE_PER_SCATTER_GATHER +// +//***************************************************************************** +extern uint32_t uDMAChannelModeGet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex); + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the uDMA controller in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! \note The interrupt handler for uDMA is for transfer completion when the +//! software channel is used, and for error interrupts. The interrupts for each +//! peripheral channel are handled through the individual peripheral interrupt +//! handlers. +//! +//! \param ui32Base is the base address of the uDMA module. +//! \param ui32IntChannel specifies which uDMA interrupt is to be registered. +//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts +//! from the uDMA software channel. +//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error +//! interrupts. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntRegister(uint32_t ui32Base, uint32_t ui32IntChannel, + void (*pfnHandler)(void)) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(pfnHandler); + ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR)); + + // Register the interrupt handler. + IntRegister(ui32IntChannel, pfnHandler); + + // Enable the memory management fault. + IntEnable(ui32IntChannel); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the uDMA controller in the dynamic interrupt table. +//! +//! This function will disable and clear the handler to be called for the +//! specified uDMA interrupt. +//! +//! \param ui32Base is the base address of the uDMA module. +//! \param ui32IntChannel specifies which uDMA interrupt to unregister. +//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts +//! from the uDMA software channel. +//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error +//! interrupts. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntUnregister(uint32_t ui32Base, uint32_t ui32IntChannel) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR)); + + // Disable the interrupt. + IntDisable(ui32IntChannel); + + // Unregister the interrupt handler. + IntUnregister(ui32IntChannel); +} + +//***************************************************************************** +// +//! \brief Clears uDMA interrupt done status. +//! +//! Clears bits in the uDMA interrupt status register according to which bits +//! are set in \c ui32ChanMask. There is one bit for each channel. If a a bit +//! is set in \c ui32ChanMask, then that corresponding channel's interrupt +//! status will be cleared (if it was set). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntClear(uint32_t ui32Base, uint32_t ui32ChanMask) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Clear the requested bits in the uDMA interrupt status register. + HWREG(ui32Base + UDMA_O_REQDONE) = ui32ChanMask; +} + +//***************************************************************************** +// +//! \brief Get the uDMA interrupt status. +//! +//! This function returns the interrupt status for the specified UDMA. This +//! function does not differentiate between software or hardware activated +//! interrupts. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE uint32_t +uDMAIntStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Return the uDMA interrupt status register. + return (HWREG(ui32Base + UDMA_O_REQDONE)); +} + +//***************************************************************************** +// +//! \brief Enable interrupt on software event driven uDMA transfers. +//! +//! \note The main purpose of this function is to prevent propagation of uDMA +//! status signals to a peripheral, if a peripheral and a software event is +//! sharing the uDMA channel. If it is desired to initiate a transfer by +//! writing to a register inside the uDMA (this means a software driven +//! channel), then the uDMA status signals propagation need to be blocked to +//! the hardware peripherals. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32IntChannel identifies which uDMA interrupt to enable software +//! interrupts for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntSwEventEnable(uint32_t ui32Base, uint32_t ui32IntChannel) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS); + + // Enable the channel. + HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 1; +} + +//***************************************************************************** +// +//! \brief Disable interrupt on software event driven uDMA transfers. +//! +//! This register disables the blocking of the uDMA status signals propagation +//! to the hardware peripheral connected to the uDMA on the \c ui32IntChannel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32IntChannel identifies which uDMA interrupt to disable software +//! interrupts for. +//! +//! \return None +//! +//! \sa \ref uDMAIntSwEventEnable() +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntSwEventDisable(uint32_t ui32Base, uint32_t ui32IntChannel) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS); + + // Disable the SW channel. + HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 0; +} + +//***************************************************************************** +// +//! \brief Return the status of the uDMA module. +//! +//! \note This status register cannot be read when the controller is in the reset state. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Current status of the uDMA module. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +uDMAGetStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Read and return the status register. + return HWREG(ui32Base + UDMA_O_STATUS); +} + +//***************************************************************************** +// +//! \brief Set the priority of a uDMA channel. +//! +//! \note Writing 0 to a bit has no effect on the priority. To reset a channel +//! priority to the default value use \ref uDMAChannelPriorityClear(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is uDMA channel to set the priority for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelPrioritySet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the channel priority to high. + HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Get the priority of a uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum The uDMA channel to get the priority for. +//! +//! \return Returns one of: +//! - \ref UDMA_PRIORITY_HIGH +//! - \ref UDMA_PRIORITY_LOW +// +//***************************************************************************** +__STATIC_INLINE bool +uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Return the channel priority. + return(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ? + UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW); +} + +//***************************************************************************** +// +//! \brief Clear the priority of a uDMA channel. +//! +//! \note Writing 0 to a bit has no effect on the priority. To set a channel +//! priority to high use \ref uDMAChannelPrioritySet(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum The uDMA channel to clear the priority for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Clear the channel priority. + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_uDMAChannelAttributeEnable + #undef uDMAChannelAttributeEnable + #define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable + #endif + #ifdef ROM_uDMAChannelAttributeDisable + #undef uDMAChannelAttributeDisable + #define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable + #endif + #ifdef ROM_uDMAChannelAttributeGet + #undef uDMAChannelAttributeGet + #define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet + #endif + #ifdef ROM_uDMAChannelControlSet + #undef uDMAChannelControlSet + #define uDMAChannelControlSet ROM_uDMAChannelControlSet + #endif + #ifdef ROM_uDMAChannelTransferSet + #undef uDMAChannelTransferSet + #define uDMAChannelTransferSet ROM_uDMAChannelTransferSet + #endif + #ifdef ROM_uDMAChannelScatterGatherSet + #undef uDMAChannelScatterGatherSet + #define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet + #endif + #ifdef ROM_uDMAChannelSizeGet + #undef uDMAChannelSizeGet + #define uDMAChannelSizeGet ROM_uDMAChannelSizeGet + #endif + #ifdef ROM_uDMAChannelModeGet + #undef uDMAChannelModeGet + #define uDMAChannelModeGet ROM_uDMAChannelModeGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UDMA_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/vims.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/vims.c new file mode 100644 index 0000000..6d348d1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/vims.c @@ -0,0 +1,176 @@ +/****************************************************************************** +* Filename: vims.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the VIMS. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "vims.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef VIMSConfigure + #define VIMSConfigure NOROM_VIMSConfigure + #undef VIMSModeSet + #define VIMSModeSet NOROM_VIMSModeSet + #undef VIMSModeGet + #define VIMSModeGet NOROM_VIMSModeGet + #undef VIMSModeSafeSet + #define VIMSModeSafeSet NOROM_VIMSModeSafeSet +#endif + +//***************************************************************************** +// +// Configures the VIMS. +// +//***************************************************************************** +void +VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG); + if(bRoundRobin) + { + ui32Reg |= VIMS_CTL_ARB_CFG; + } + if(bPrefetch) + { + ui32Reg |= VIMS_CTL_PREF_EN; + } + + // Set the Arbitration and prefetch mode. + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +//***************************************************************************** +// +// Set the operational mode of the VIMS +// +//***************************************************************************** +void +VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ASSERT((ui32Mode == VIMS_MODE_DISABLED) || + (ui32Mode == VIMS_MODE_ENABLED) || + (ui32Mode == VIMS_MODE_OFF)); + + // Set the mode. + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~VIMS_CTL_MODE_M; + ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M); + + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +//***************************************************************************** +// +// Get the current operational mode of the VIMS. +// +//***************************************************************************** +uint32_t +VIMSModeGet(uint32_t ui32Base) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_STAT); + if(ui32Reg & VIMS_STAT_MODE_CHANGING) + { + return (VIMS_MODE_CHANGING); + } + else + { + return (ui32Reg & VIMS_STAT_MODE_M); + } +} + +//***************************************************************************** +// +// Safe setting of new VIMS mode +// - Function might be blocking +// - Can be called for any mode change (also if actually not changing mode) +// +//***************************************************************************** +void +VIMSModeSafeSet( uint32_t ui32Base, uint32_t ui32NewMode, bool blocking ) +{ + uint32_t currentMode; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + ASSERT((ui32NewMode == VIMS_MODE_DISABLED) || + (ui32NewMode == VIMS_MODE_ENABLED) || + (ui32NewMode == VIMS_MODE_OFF)); + + // Make sure that only the mode bits are set in the input parameter + // (done just for security since it is critical to the code flow) + ui32NewMode &= VIMS_CTL_MODE_M; + + // Wait for any pending change to complete and get current VIMS mode + // (This is a blocking point but will typically only be a blocking point + // only if mode is changed multiple times with blocking=0) + do { + currentMode = VIMSModeGet( ui32Base ); + } while ( currentMode == VIMS_MODE_CHANGING ); + + // First check that it actually is a mode change request + if ( ui32NewMode != currentMode ) { + // Set new mode + VIMSModeSet( ui32Base, ui32NewMode ); + + // Wait for final mode change to complete - if blocking is requested + if ( blocking ) { + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for change to complete. + } + } + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/vims.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/vims.h new file mode 100644 index 0000000..9e6ecaf --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/vims.h @@ -0,0 +1,371 @@ +/****************************************************************************** +* Filename: vims.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the VIMS. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup vims_api +//! @{ +// +//***************************************************************************** + +#ifndef __VIMS_H__ +#define __VIMS_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_vims.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define VIMSConfigure NOROM_VIMSConfigure + #define VIMSModeSet NOROM_VIMSModeSet + #define VIMSModeGet NOROM_VIMSModeGet + #define VIMSModeSafeSet NOROM_VIMSModeSafeSet +#endif + +//***************************************************************************** +// +// Values that can be passed to VIMSModeSet() as the ui32IntFlags parameter, +// and returned from VIMSModeGet(). +// +//***************************************************************************** +#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE + // can not be changed at moment. +#define VIMS_MODE_DISABLED (VIMS_CTL_MODE_GPRAM) // Disabled mode (GPRAM enabled). +#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached. +#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \brief Checks a VIMS base address. +//! +//! This function determines if the VIMS base address is valid. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +VIMSBaseValid(uint32_t ui32Base) +{ + return(ui32Base == VIMS_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Configures the VIMS. +//! +//! This function sets general control settings of the VIMS system. +//! +//! \note The VIMS mode must be set using the \ref VIMSModeSet() call. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param bRoundRobin specifies the arbitration method. +//! - \c true : Round Robin arbitration between the two available read/write interfaces +//! (i.e. Icode/Dcode and Sysbus) is to be used. +//! - \c false : Strict arbitration will be used, where Icode/Dcode +//! is preferred over the Sysbus. +//! \param bPrefetch specifies if prefetching is to be used. +//! - \c true : Cache is to prefetch tag data for the following address. +//! - \c false : No prefetch. +//! +//! \return None +//! +//! \sa \ref VIMSModeSet() +// +//***************************************************************************** +extern void VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, + bool bPrefetch); + +//***************************************************************************** +// +//! \brief Set the operational mode of the VIMS. +//! +//! This function sets the operational mode of the VIMS. +//! +//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. +//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will not be operational. +//! Reads and writes to flash will be uncached. +//! After a short delay (approx. 1029 clock cycles) the VIMS will +//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). +//! +//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is +//! accessible: +//! The GP RAM will be accessible. +//! The Cache will not be operational. +//! Reads from flash will be uncached. +//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). +//! +//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will be operational for SYSCODE space. +//! Reads from flash in USERCODE space will be uncached. +//! +//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. +//! +//! \note The VIMS must be invalidated when switching mode. +//! This is done by setting VIMS_MODE_OFF before setting any new mode. +//! This is automatically handled in \ref VIMSModeSafeSet() +//! +//! \note It is highly recommended that the VIMS is put in disabled mode before +//! \b writing to flash, since the cache will not be updated nor invalidated +//! by flash writes. The line buffers should also be disabled when updating the +//! flash. Once \ref VIMSModeSet() is used to set the VIMS in +//! \ref VIMS_MODE_CHANGING mode, the user should check using +//! \ref VIMSModeGet() when the mode switches to \ref VIMS_MODE_DISABLED. Only when +//! the mode has changed the cache has been completely invalidated. +//! +//! \note Access from System Bus is never cached. Only access through ICODE +//! DCODE bus from the System CPU is cached. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param ui32Mode is the operational mode. +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! +//! \return None +//! +//! \sa \ref VIMSModeGet() and \ref VIMSModeSafeSet() +// +//***************************************************************************** +extern void VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode); + +//***************************************************************************** +// +//! \brief Get the current operational mode of the VIMS. +//! +//! This function returns the operational mode of the VIMS. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return Returns one of: +//! - \ref VIMS_MODE_CHANGING +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! +//! \sa \ref VIMSModeSet() +// +//***************************************************************************** +extern uint32_t VIMSModeGet(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Set the operational mode of the VIMS in a safe sequence. +//! +//! This function sets the operational mode of the VIMS in a safe sequence +//! +//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. +//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will not be operational (read/write to flash will be uncached). +//! After a short delay (approx. 1029 clock cycles) the VIMS will +//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). +//! +//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is +//! accessible: +//! The GP RAM will be accessible. +//! The Cache will not be operational. +//! Reads from flash will be uncached. +//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). +//! +//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will be operational for SYSCODE space. +//! Reads from flash in USERCODE space will be uncached. +//! +//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. +//! +//! \note The VIMS must be invalidated when switching mode. +//! This is done by setting VIMS_MODE_OFF before setting any new mode. +//! This is automatically handled in this function. +//! +//! \note It is highly recommended that the VIMS is put in disabled mode before +//! \b writing to flash, since the cache will not be updated nor invalidated +//! by flash writes. The line buffers should also be disabled when updating the +//! flash. +//! +//! \note Access from System Bus is never cached. Only access through ICODE +//! DCODE bus from the System CPU is cached. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param ui32NewMode is the new operational mode: +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! \param blocking shall be set to TRUE if further code execution shall be +//! blocked (delayed) until mode change is completed. +//! +//! \return None +//! +//! \sa \ref VIMSModeSet() and \ref VIMSModeGet() +// +//***************************************************************************** +extern void VIMSModeSafeSet( uint32_t ui32Base , + uint32_t ui32NewMode , + bool blocking ); + +//***************************************************************************** +// +//! \brief Disable VIMS linebuffers. +//! +//! Linebuffers should only be disabled when attempting to update the flash, to +//! ensure that the content of the buffers is not stale. As soon as flash is +//! updated the linebuffers should be reenabled. Failing to enable +//! will have a performance impact. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +VIMSLineBufDisable(uint32_t ui32Base) +{ + // Disable line buffers + HWREG(ui32Base + VIMS_O_CTL) |= VIMS_CTL_IDCODE_LB_DIS_M | + VIMS_CTL_SYSBUS_LB_DIS_M; +} + +//***************************************************************************** +// +//! \brief Enable VIMS linebuffers. +//! +//! Linebuffers should only be disabled when attempting to update the flash, to +//! ensure that the content of the buffers is not stale. As soon as flash is +//! updated the linebuffers should be reenabled. Failing to enable +//! will have a performance impact. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +VIMSLineBufEnable(uint32_t ui32Base) +{ + // Enable linebuffers + HWREG(ui32Base + VIMS_O_CTL) &= ~(VIMS_CTL_IDCODE_LB_DIS_M | + VIMS_CTL_SYSBUS_LB_DIS_M); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_VIMSConfigure + #undef VIMSConfigure + #define VIMSConfigure ROM_VIMSConfigure + #endif + #ifdef ROM_VIMSModeSet + #undef VIMSModeSet + #define VIMSModeSet ROM_VIMSModeSet + #endif + #ifdef ROM_VIMSModeGet + #undef VIMSModeGet + #define VIMSModeGet ROM_VIMSModeGet + #endif + #ifdef ROM_VIMSModeSafeSet + #undef VIMSModeSafeSet + #define VIMSModeSafeSet ROM_VIMSModeSafeSet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __VIMS_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.c new file mode 100644 index 0000000..054febd --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: wdt.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the Watchdog Timer. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "watchdog.h" + +// See watchdog.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.h new file mode 100644 index 0000000..373fb52 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.h @@ -0,0 +1,520 @@ +/****************************************************************************** +* Filename: wdt.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and prototypes for the Watchdog Timer. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup wdt_api +//! @{ +// +//***************************************************************************** + +#ifndef __WDT_H__ +#define __WDT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_wdt.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//***************************************************************************** +#define WATCHDOG_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WATCHDOG_LOCK_LOCKED 0x00000001 // Locked +#define WATCHDOG_LOCK_UNLOCK 0x1ACCE551 // Unlocks the Watchdog Timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and +// WDT_MIS registers. +// +//***************************************************************************** +#define WATCHDOG_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The type of interrupt that can be generated by the watchdog. +// +//***************************************************************************** +#define WATCHDOG_INT_TYPE_INT 0x00000000 +#define WATCHDOG_INT_TYPE_NMI 0x00000004 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Determines if the watchdog timer is enabled. +//! +//! This function checks to see if the watchdog timer is enabled. +//! +//! \return Returns status of Watchdog Timer: +//! - \c true : Watchdog timer is enabled. +//! - \c false : Watchdog timer is disabled. +// +//***************************************************************************** +__STATIC_INLINE bool +WatchdogRunning(void) +{ + // See if the watchdog timer module is enabled, and return. + return((HWREG(WDT_BASE + WDT_O_CTL) & WDT_CTL_INTEN) ? true : false); +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer. +//! +//! This function enables the watchdog timer counter and interrupt. +//! +//! Once enabled, the watchdog interrupt can only be disabled by a hardware reset. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogEnable(void) +{ + // Enable the watchdog timer module. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTEN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer reset. +//! +//! This function enables the capability of the watchdog timer to issue a reset +//! to the processor after a second timeout condition. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogResetEnable(void) +{ + // Enable the watchdog reset. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disables the watchdog timer reset. +//! +//! This function disables the capability of the watchdog timer to issue a +//! reset to the processor after a second timeout condition. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogResetDisable(void) +{ + // Disable the watchdog reset. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer lock mechanism. +//! +//! This function locks out write access to the watchdog timer configuration +//! registers. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogLock(void) +{ + // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK + // register causes the lock to go into effect. + HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_LOCKED; +} + +//***************************************************************************** +// +//! \brief Disables the watchdog timer lock mechanism. +//! +//! This function enables write access to the watchdog timer configuration +//! registers. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogUnlock(void) +{ + // Unlock watchdog register writes. + HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_UNLOCK; +} + +//***************************************************************************** +// +//! \brief Gets the state of the watchdog timer lock mechanism. +//! +//! This function returns the lock state of the watchdog timer registers. +//! +//! \return Returns state of lock mechanism. +//! - \c true : Watchdog timer registers are locked. +//! - \c false : Registers are not locked. +// +//***************************************************************************** +__STATIC_INLINE bool +WatchdogLockState(void) +{ + // Get the lock state. + return((HWREG(WDT_BASE + WDT_O_LOCK) == WATCHDOG_LOCK_LOCKED) ? + true : false); +} + +//***************************************************************************** +// +//! \brief Sets the watchdog timer reload value. +//! +//! This function configures the value to load into the watchdog timer when the +//! count reaches zero for the first time; if the watchdog timer is running +//! when this function is called, then the value is immediately loaded into the +//! watchdog timer counter. If the \c ui32LoadVal parameter is 0, then an +//! interrupt is immediately generated. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \param ui32LoadVal is the load value for the watchdog timer. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock(), \ref WatchdogReloadGet() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogReloadSet(uint32_t ui32LoadVal) +{ + // Set the load register. + HWREG(WDT_BASE + WDT_O_LOAD) = ui32LoadVal; +} + +//***************************************************************************** +// +//! \brief Gets the watchdog timer reload value. +//! +//! This function gets the value that is loaded into the watchdog timer when +//! the count reaches zero for the first time. +//! +//! \return None +//! +//! \sa \ref WatchdogReloadSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +WatchdogReloadGet(void) +{ + // Get the load register. + return(HWREG(WDT_BASE + WDT_O_LOAD)); +} + +//***************************************************************************** +// +//! \brief Gets the current watchdog timer value. +//! +//! This function reads the current value of the watchdog timer. +//! +//! \return Returns the current value of the watchdog timer. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +WatchdogValueGet(void) +{ + // Get the current watchdog timer register value. + return(HWREG(WDT_BASE + WDT_O_VALUE)); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! The watchdog timer interrupt must be enabled via \ref WatchdogIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! \ref WatchdogIntClear(). +//! +//! \note This function registers the standard watchdog interrupt handler. To +//! register the NMI watchdog handler, use \ref IntRegister() to register the +//! handler for the \b INT_NMI_FAULT interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! watchdog timer interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_WDT_IRQ, pfnHandler); + + // Enable the watchdog timer interrupt. + IntEnable(INT_WDT_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. This +//! function clears the handler to be called when a watchdog timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \note This function registers the standard watchdog interrupt handler. To +//! register the NMI watchdog handler, use \ref IntRegister() to register the +//! handler for the \b INT_NMI_FAULT interrupt. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntUnregister(void) +{ + // Disable the interrupt. + IntDisable(INT_WDT_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_WDT_IRQ); +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer. +//! +//! This function enables the watchdog timer interrupt by calling \ref WatchdogEnable(). +//! +//! \return None +//! +//! \sa \ref WatchdogEnable() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntEnable(void) +{ + // Enable the Watchdog interrupt. + WatchdogEnable(); +} + +//***************************************************************************** +// +//! \brief Gets the current watchdog timer interrupt status. +//! +//! This function returns the interrupt status for the watchdog timer module. +//! +//! \return Returns the interrupt status. +//! - 1 : Watchdog time-out has occurred. +//! - 0 : Watchdog time-out has not occurred. +//! +//! \sa \ref WatchdogIntClear(); +// +//***************************************************************************** +__STATIC_INLINE uint32_t +WatchdogIntStatus(void) +{ + // Return either the interrupt status or the raw interrupt status as + // requested. + return(HWREG(WDT_BASE + WDT_O_RIS)); +} + +//***************************************************************************** +// +//! \brief Clears the watchdog timer interrupt. +//! +//! The watchdog timer interrupt source is cleared, so that it no longer +//! asserts. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntClear(void) +{ + // Clear the interrupt source. + HWREG(WDT_BASE + WDT_O_ICR) = WATCHDOG_INT_TIMEOUT; +} + +//***************************************************************************** +// +//! \brief Sets the type of interrupt generated by the watchdog. +//! +//! This function sets the type of interrupt that is generated if the watchdog +//! timer expires. +//! +//! When configured to generate an NMI, the watchdog interrupt must still be +//! enabled with \ref WatchdogIntEnable(), and it must still be cleared inside the +//! NMI handler with \ref WatchdogIntClear(). +//! +//! \param ui32Type is the type of interrupt to generate. +//! - \ref WATCHDOG_INT_TYPE_INT : Generate a standard interrupt (default). +//! - \ref WATCHDOG_INT_TYPE_NMI : Generate a non-maskable interrupt (NMI). +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntTypeSet(uint32_t ui32Type) +{ + // Check the arguments. + ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) || + (ui32Type == WATCHDOG_INT_TYPE_NMI)); + + // Set the interrupt type. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTTYPE_BITN) = (ui32Type == WATCHDOG_INT_TYPE_INT)? 0 : 1; +} + +//***************************************************************************** +// +//! \brief Enables stalling of the watchdog timer during debug events. +//! +//! This function allows the watchdog timer to stop counting when the processor +//! is stopped by the debugger. By doing so, the watchdog is prevented from +//! expiring and resetting the system (if reset is enabled). The watchdog instead expires +//! after the appropriate number of processor cycles have been executed while +//! debugging (or at the appropriate time after the processor has been +//! restarted). +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogStallEnable(void) +{ + // Enable timer stalling. + HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disables stalling of the watchdog timer during debug events. +//! +//! This function disables the debug mode stall of the watchdog timer. By +//! doing so, the watchdog timer continues to count regardless of the processor +//! debug state. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogStallDisable(void) +{ + // Disable timer stalling. + HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 0; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __WDT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog_doc.h new file mode 100644 index 0000000..877bab7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog_doc.h @@ -0,0 +1,121 @@ +/****************************************************************************** +* Filename: watchdog_doc.h +* Revised: 2018-02-09 15:45:36 +0100 (Fri, 09 Feb 2018) +* Revision: 51470 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup wdt_api +//! @{ +//! \section sec_wdt Introduction +//! +//! The Watchdog Timer (WDT) allows the application to regain control if the system stalls due to +//! unexpected software behavior. The WDT can generate a normal interrupt or a non-maskable interrupt +//! on the first time-out and a system reset on the following time-out if the application fails to +//! restart the WDT. +//! +//! WDT has the following features: +//! - 32-bit down counter with a configurable load register. +//! - Configurable interrupt generation logic with interrupt masking and optional NMI function. +//! - Optional reset generation. +//! - Register protection from runaway software (lock). +//! - User-enabled stalling when the system CPU asserts the CPU Halt flag during debug. +//! +//! The WDT runs at system HF clock divided by 32; however, when in powerdown it runs at +//! LF clock (32 kHz) - if the LF clock to the MCU domain is enabled. +//! +//! If application does not restart the WDT, using \ref WatchdogIntClear(), before a time-out: +//! - At the first time-out the WDT asserts the interrupt, reloads the 32-bit counter with the load +//! value, and resumes counting down from that value. +//! - If the WDT counts down to zero again before the application clears the interrupt, and the +//! reset signal has been enabled, the WDT asserts its reset signal to the system. +//! +//! \note By default, a "warm reset" triggers a pin reset and thus reboots the device. +//! +//! A reset caused by the WDT can be detected as a "warm reset" using \ref SysCtrlResetSourceGet(). +//! However, it is not possible to detect which of the warm reset sources that caused the reset. +//! +//! Typical use case: +//! - Use \ref WatchdogIntTypeSet() to select either standard interrupt or non-maskable interrupt on +//! first time-out. +//! - The application must implement an interrupt handler for the selected interrupt type. If +//! application uses the \e static vector table (see startup_.c) the interrupt +//! handlers for standard interrupt and non-maskable interrupt are named WatchdogIntHandler() +//! and NmiSR() respectively. For more information about \e static and \e dynamic vector table, +//! see \ref sec_interrupt_table. +//! - Use \ref WatchdogResetEnable() to enable reset on second time-out. +//! - Use \ref WatchdogReloadSet() to set (re)load value of the counter. +//! - Use \ref WatchdogEnable() to start the WDT counter. The WDT counts down from the load value. +//! - Use \ref WatchdogLock() to lock WDT configuration to prevent unintended re-configuration. +//! - Application must use \ref WatchdogIntClear() to restart the counter before WDT times out. +//! - If application does not restart the counter before it reaches zero (times out) the WDT asserts +//! the selected type of interrupt, reloads the counter, and starts counting down again. +//! - The interrupt handler triggered by the first time-out can be used to log debug information +//! or try to enter a safe "pre-reset" state in order to have a more graceful reset when the WDT +//! times out the second time. +//! - It is \b not recommended that the WDT interrupt handler clears the WDT interrupt and thus +//! reloads the WDT counter. This means that the WDT interrupt handler never returns. +//! - If the application does not clear the WDT interrupt and the WDT times out when the interrupt +//! is still asserted then WDT triggers a reset (if enabled). +//! +//! \section sec_wdt_api API +//! +//! The API functions can be grouped like this: +//! +//! Watchdog configuration: +//! - \ref WatchdogIntTypeSet() +//! - \ref WatchdogResetEnable() +//! - \ref WatchdogResetDisable() +//! - \ref WatchdogReloadSet() +//! - \ref WatchdogEnable() +//! +//! Status: +//! - \ref WatchdogRunning() +//! - \ref WatchdogValueGet() +//! - \ref WatchdogReloadGet() +//! - \ref WatchdogIntStatus() +//! +//! Interrupt configuration: +//! - \ref WatchdogIntEnable() +//! - \ref WatchdogIntClear() +//! - \ref WatchdogIntRegister() +//! - \ref WatchdogIntUnregister() +//! +//! Register protection: +//! - \ref WatchdogLock() +//! - \ref WatchdogLockState() +//! - \ref WatchdogUnlock() +//! +//! Stall configuration for debugging: +//! - \ref WatchdogStallDisable() +//! - \ref WatchdogStallEnable() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/asmdefs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/asmdefs.h new file mode 100644 index 0000000..1768b4c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/asmdefs.h @@ -0,0 +1,151 @@ +/****************************************************************************** +* Filename: asmdefs.h +* Revised: 2015-06-05 14:39:10 +0200 (Fri, 05 Jun 2015) +* Revision: 43803 +* +* Description: Macros to allow assembly code be portable among tool chains. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef __IAR_SYSTEMS_ICC__ + +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) +#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) + +// +// Assembler mnemonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data + +#endif // __IAR_SYSTEMS_ICC__ + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#if defined(__GNUC__) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler mnemonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // __GNUC__ + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#if defined(__CC_ARM) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 +#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 + +// +// Assembler mnemonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ + +#endif // __CC_ARM + + +#endif // __ASMDEF_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi.h new file mode 100644 index 0000000..d55fe0f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi.h @@ -0,0 +1,1182 @@ +/****************************************************************************** +* Filename: hw_adi.h +* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) +* Revision: 42365 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_H__ +#define __HW_ADI_H__ + +//***************************************************************************** +// +// This file contains macros for controlling the ADI master and +// accessing ADI slave registers via the ADI Master. +// There are 3 categories of macros in this file: +// - macros that provide an offset to a register +// located within the DDI Master itself. +// - macros that define bits or bitfields +// within the DDI Master Registers. +// - macros that provide an "instruction offset" +// that are used when accessing a ADI Slave. +// +// The macros that that provide ADI Master register offsets and +// define bits and bitfields for those registers are the typical +// macros that appear in most hw_.h header files. In +// the following example ADI_O_SLAVECONF is a macro for a +// register offset and ADI_SLAVECONF_WAITFORACK is a macro for +// a bit in that register. This example code will set the WAITFORACK +// bit in register ADI_O_SLAVECONF of the ADI Master. (Note: this +// access the Master not the Slave). +// +// HWREG(ADI3_BASE + ADI_O_SLAVECONF) |= ADI_SLAVECONF_WAITFORACK; +// +// The "instruction offset" macros are used to pass an instruction to +// the ADI Master when accessing ADI slave registers. These macros are +// only used when accessing ADI Slave Registers. (Remember ADI +// Master Registers are accessed normally). +// +// The instructions supported when accessing an ADI Slave Register follow: +// - Direct Access to an ADI Slave register. I.e. read or +// write the register. +// - Set the specified bits in a ADI Slave register. +// - Clear the specified bits in a ADI Slave register. +// - Mask write of 4 bits to the a ADI Slave register. +// - Mask write of 8 bits to the a ADI Slave register. +// - Mask write of 16 bits to the a ADI Slave register. +// +// Note: only the "Direct Access" offset should be used when reading +// a ADI Slave register. Only 4-bit reads are supported and 8 bits write are +// supported natively. If accessing wider bitfields, the read/write operation +// will be spread out over a number of transactions. This is hidden for the +// user, but can potentially be very timeconsuming. Especially of running +// on a slow clock. +// +// The generic format of using these macros for a read follows: +// // Read low 8-bits in ADI_SLAVE_OFF +// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); +// +// // Read high 8-bits in ADI_SLAVE_OFF (data[31:16]) +// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); +// +// Notes: In the above example: +// - ADI_MASTER_BASE is the base address of the ADI Master defined +// in the hw_memmap.h header file. +// - ADI_SLAVE_OFF is the ADI Slave offset defined in the +// hw_.h header file (e.g. hw_adi_3_refsys_top.h for the refsys +// module). +// - ADI_O_DIR is the "instruction offset" macro defined in this +// file that specifies the Direct Access instruction. +// +// Writes can use any of the "instruction macros". +// The following examples do a "direct write" to an ADI Slave register +// ADI_SLAVE_OFF using different size operands: +// +// // ---------- DIRECT WRITES ---------- +// // Write 32-bits aligned +// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x12345678; +// +// // Write 16-bits aligned to high 16-bits then low 16-bits +// // Add 2 to get to high 16-bits. +// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0xabcd; +// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0xef01; +// +// // Write each byte at ADI_SLAVE_OFF, one at a time. +// // Add 1,2,or 3 to get to bytes 1,2, or 3. +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x33; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 1) = 0x44; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0x55; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 3) = 0x66; +// +// // ---------- SET/CLR ---------- +// The set and clear functions behave similarly to eachother. Each +// can be performed on an 8-, 16-, or 32-bit operand. +// Examples follow: +// // Set all odd bits in a 32-bit words +// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_SET) = 0xaaaaaaaa; +// +// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand +// HWREG(DDI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_CLR) = 0x00ff0000; +// +// // Set even bits in byte 2 (data[23:16]) using 8-bit operand +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + 2 + ADI_O_CLR) = 0x55; +// +// // ---------- MASKED WRITES ---------- +// The mask writes are a bit different. They operate on nibbles, +// bytes, and 16-bit elements. Two operands are required; a 'mask' +// and 'data'; The operands are concatenated and written to the master. +// e.g. the mask and data are combined as follows for a 16 bit masked +// write: +// (mask << 16) | data; +// Examples follow: +// +// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). +// // Byte write is needed. +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_MASK4B01) = 0xf7; +// +// // Do an 4 bit masked write of 4 to data[7:4]). +// // Add 1 for next nibble +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + ADI_O_MASK4B01 + 1) = 0xf4; +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the ADI master instruction offsets. +// +//***************************************************************************** +#define ADI_O_DIR 0x00000000 // Offset for the direct access + // instruction +#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. +#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. +#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). + // Bits 7:4 are mask. Bits 3:0 are data. + // Requires 'byte' write. +#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). Bits 15:8 are + // mask. Bits 7:0 are data. Requires + // 'short' write. +#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). Bits 31:16 + // are mask. Bits 15:0 are data. + // Requires 'long' write. + +//***************************************************************************** +// +// The following are defines for the ADI register offsets. +// +//***************************************************************************** +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVESTAT register. +// +//***************************************************************************** +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ + // signal. Writing 0 to this bit + // forces a sync with slave, + // ensuring that req will be 0. It + // is recommended to write 0 to + // this register before power down + // of the master. +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK + // signal +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVECONF register. +// +//***************************************************************************** +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer + // accessible when this bit is set. + // (unless sticky_bit_overwrite is + // asserted on top module) +#define ADI_SLAVECONF_CONFLOCK_M \ + 0x00000080 +#define ADI_SLAVECONF_CONFLOCK_S 7 +#define ADI_SLAVECONF_WAITFORACK \ + 0x00000004 // A transaction on the ADI + // interface does not end until ack + // has been received from the slave + // when this bit is set. + +#define ADI_SLAVECONF_WAITFORACK_M \ + 0x00000004 +#define ADI_SLAVECONF_WAITFORACK_S 2 +#define ADI_SLAVECONF_ADICLKSPEED_M \ + 0x00000003 // Sets the period of an ADI + // transactions. All transactions + // takes an even number of clock + // cycles,- ADI clock rising edge + // occurs in the middle of the + // period. Data and ctrl to slave + // is set up in beginning of cycle, + // and data from slave is read in + // after the transaction 00: An ADI + // transaction takes 2 master clock + // cyclkes 01: An ADI transaction + // takes 4 master clock cycles 10: + // And ADI Transaction takes 8 + // master clock cycles 11: An ADI + // transaction takes 16 master + // clock cycles + +#define ADI_SLAVECONF_ADICLKSPEED_S 0 + +//***************************************************************************** +// +// The following are defines pseudo-magic numbers that should go away. +// New code should not use these registers and old code should be ported +// to not use these. +// +//***************************************************************************** +#define ADI_O_DIR03 0x00000000 // Direct access for adi byte + // offsets 0 to 3 +#define ADI_O_DIR47 0x00000004 // Direct access for adi byte + // offsets 4 to 7 +#define ADI_O_DIR811 0x00000008 // Direct access for adi byte + // offsets 8 to 11 +#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte + // offsets 12 to 15 +#define ADI_O_SET03 0x00000010 // Set register for ADI byte + // offsets 0 to 3 +#define ADI_O_SET47 0x00000014 // Set register for ADI byte + // offsets 4 to 7 +#define ADI_O_SET811 0x00000018 // Set register for ADI byte + // offsets 8 to 11 +#define ADI_O_SET1215 0x0000001C // Set register for ADI byte + // offsets 12 to 15 +#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte + // offsets 0 to 3 +#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte + // offsets 4 to 7 +#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte + // offsets 8 to 11 +#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte + // offsets 12 to 15 +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration + // register +#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI + // Registers at byte offsets 14 and + // 15 +#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI + // Registers at byte offsets 14 and + // 15 +#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI + // Registers at byte offsets 14 and + // 15 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR03 register. +// +//***************************************************************************** +#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 +#define ADI_DIR03_B3_S 24 +#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 +#define ADI_DIR03_B2_S 16 +#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 +#define ADI_DIR03_B1_S 8 +#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 +#define ADI_DIR03_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR47 register. +// +//***************************************************************************** +#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 +#define ADI_DIR47_B3_S 24 +#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 +#define ADI_DIR47_B2_S 16 +#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 +#define ADI_DIR47_B1_S 8 +#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 +#define ADI_DIR47_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR811 register. +// +//***************************************************************************** +#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register + // 11 +#define ADI_DIR811_B3_S 24 +#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register + // 10 +#define ADI_DIR811_B2_S 16 +#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 +#define ADI_DIR811_B1_S 8 +#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 +#define ADI_DIR811_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR1215 register. +// +//***************************************************************************** +#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register + // 15 +#define ADI_DIR1215_B3_S 24 +#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register + // 14 +#define ADI_DIR1215_B2_S 16 +#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register + // 13 +#define ADI_DIR1215_B1_S 8 +#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register + // 12 +#define ADI_DIR1215_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET03 register. +// +//***************************************************************************** +#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 3. Read returns 0. +#define ADI_SET03_S3_S 24 +#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 2. Read returns 0. +#define ADI_SET03_S2_S 16 +#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 1. Read returns 0. +#define ADI_SET03_S1_S 8 +#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 0. Read returns 0. +#define ADI_SET03_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET47 register. +// +//***************************************************************************** +#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 7. Read returns 0. +#define ADI_SET47_S3_S 24 +#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 6. Read returns 0. +#define ADI_SET47_S2_S 16 +#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 5. Read returns 0. +#define ADI_SET47_S1_S 8 +#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 4. Read returns 0. +#define ADI_SET47_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET811 register. +// +//***************************************************************************** +#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 11. Read returns 0. +#define ADI_SET811_S3_S 24 +#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 10. Read returns 0. +#define ADI_SET811_S2_S 16 +#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 9. Read returns 0. +#define ADI_SET811_S1_S 8 +#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 8. Read returns 0. +#define ADI_SET811_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET1215 register. +// +//***************************************************************************** +#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 15. Read returns 0. +#define ADI_SET1215_S3_S 24 +#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 14. Read returns 0. +#define ADI_SET1215_S2_S 16 +#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 13. Read returns 0. +#define ADI_SET1215_S1_S 8 +#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 12. Read returns 0. +#define ADI_SET1215_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR03 register. +// +//***************************************************************************** +#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 3 +#define ADI_CLR03_S3_S 24 +#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 2 +#define ADI_CLR03_S2_S 16 +#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 1 +#define ADI_CLR03_S1_S 8 +#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 0 +#define ADI_CLR03_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR47 register. +// +//***************************************************************************** +#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 7 +#define ADI_CLR47_S3_S 24 +#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 6 +#define ADI_CLR47_S2_S 16 +#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 5 +#define ADI_CLR47_S1_S 8 +#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 4 +#define ADI_CLR47_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR811 register. +// +//***************************************************************************** +#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 11 +#define ADI_CLR811_S3_S 24 +#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 10 +#define ADI_CLR811_S2_S 16 +#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 9 +#define ADI_CLR811_S1_S 8 +#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 8 +#define ADI_CLR811_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR1215 register. +// +//***************************************************************************** +#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 15 +#define ADI_CLR1215_S3_S 24 +#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 14 +#define ADI_CLR1215_S2_S 16 +#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 13 +#define ADI_CLR1215_S1_S 8 +#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 12 +#define ADI_CLR1215_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVESTAT register. +// +//***************************************************************************** +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ + // signal. Writing 0 to this bit + // forces a sync with slave, + // ensuring that req will be 0. It + // is recommended to write 0 to + // this register before power down + // of the master. +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK + // signal +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVECONF register. +// +//***************************************************************************** +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer + // accessible when this bit is set. + // (unless sticky_bit_overwrite is + // asserted on top module) +#define ADI_SLAVECONF_CONFLOCK_M \ + 0x00000080 +#define ADI_SLAVECONF_CONFLOCK_S 7 +#define ADI_SLAVECONF_WAITFORACK \ + 0x00000004 // A transaction on the ADI + // interface does not end until ack + // has been received from the slave + // when this bit is set. + +#define ADI_SLAVECONF_WAITFORACK_M \ + 0x00000004 +#define ADI_SLAVECONF_WAITFORACK_S 2 +#define ADI_SLAVECONF_ADICLKSPEED_M \ + 0x00000003 // Sets the period of an ADI + // transactions. All transactions + // takes an even number of clock + // cycles,- ADI clock rising edge + // occurs in the middle of the + // period. Data and ctrl to slave + // is set up in beginning of cycle, + // and data from slave is read in + // after the transaction 00: An ADI + // transaction takes 2 master clock + // cyclkes 01: An ADI transaction + // takes 4 master clock cycles 10: + // And ADI Transaction takes 8 + // master clock cycles 11: An ADI + // transaction takes 16 master + // clock cycles + +#define ADI_SLAVECONF_ADICLKSPEED_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B01 register. +// +//***************************************************************************** +#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 1 +#define ADI_MASK4B01_M1H_S 28 +#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 1, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B01_D1H_S 24 +#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 1 +#define ADI_MASK4B01_M1L_S 20 +#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 1, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B01_D1L_S 16 +#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 0 +#define ADI_MASK4B01_M0H_S 12 +#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 0, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B01_D0H_S 8 +#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 0 +#define ADI_MASK4B01_M0L_S 4 +#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 0, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B01_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B23 register. +// +//***************************************************************************** +#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 3 +#define ADI_MASK4B23_M1H_S 28 +#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 3, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B23_D1H_S 24 +#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 3 +#define ADI_MASK4B23_M1L_S 20 +#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 3, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B23_D1L_S 16 +#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 2 +#define ADI_MASK4B23_M0H_S 12 +#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 2, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B23_D0H_S 8 +#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 2 +#define ADI_MASK4B23_M0L_S 4 +#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 2, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B23_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B45 register. +// +//***************************************************************************** +#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 5 +#define ADI_MASK4B45_M1H_S 28 +#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 5, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B45_D1H_S 24 +#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 5 +#define ADI_MASK4B45_M1L_S 20 +#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 5, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B45_D1L_S 16 +#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 4 +#define ADI_MASK4B45_M0H_S 12 +#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 4, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B45_D0H_S 8 +#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 4 +#define ADI_MASK4B45_M0L_S 4 +#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 4, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B45_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B67 register. +// +//***************************************************************************** +#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 7 +#define ADI_MASK4B67_M1H_S 28 +#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 7, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B67_D1H_S 24 +#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 7 +#define ADI_MASK4B67_M1L_S 20 +#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 7, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B67_D1L_S 16 +#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 6 +#define ADI_MASK4B67_M0H_S 12 +#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 6, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B67_D0H_S 8 +#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 6 +#define ADI_MASK4B67_M0L_S 4 +#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 6, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B67_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B89 register. +// +//***************************************************************************** +#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 9 +#define ADI_MASK4B89_M1H_S 28 +#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 9, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B89_D1H_S 24 +#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 9 +#define ADI_MASK4B89_M1L_S 20 +#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 9, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B89_D1L_S 16 +#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 8 +#define ADI_MASK4B89_M0H_S 12 +#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 8, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B89_D0H_S 8 +#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 8 +#define ADI_MASK4B89_M0L_S 4 +#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 8, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B89_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1011 register. +// +//***************************************************************************** +#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 11 +#define ADI_MASK4B1011_M1H_S 28 +#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 11, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1011_D1H_S 24 +#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 11 +#define ADI_MASK4B1011_M1L_S 20 +#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 11, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1011_D1L_S 16 +#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 10 +#define ADI_MASK4B1011_M0H_S 12 +#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 10, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1011_D0H_S 8 +#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 10 +#define ADI_MASK4B1011_M0L_S 4 +#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 10, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1011_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1213 register. +// +//***************************************************************************** +#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 13 +#define ADI_MASK4B1213_M1H_S 28 +#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 13, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1213_D1H_S 24 +#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 13 +#define ADI_MASK4B1213_M1L_S 20 +#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 13, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1213_D1L_S 16 +#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 12 +#define ADI_MASK4B1213_M0H_S 12 +#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 12, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1213_D0H_S 8 +#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 12 +#define ADI_MASK4B1213_M0L_S 4 +#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 12, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1213_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1415 register. +// +//***************************************************************************** +#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 15 +#define ADI_MASK4B1415_M1H_S 28 +#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 15, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1415_D1H_S 24 +#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 15 +#define ADI_MASK4B1415_M1L_S 20 +#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 15, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1415_D1L_S 16 +#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 14 +#define ADI_MASK4B1415_M0H_S 12 +#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 14, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1415_D0H_S 8 +#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 14 +#define ADI_MASK4B1415_M0L_S 4 +#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 14, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1415_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B01 register. +// +//***************************************************************************** +#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 +#define ADI_MASK8B01_M1_S 24 +#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B01_D1_S 16 +#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 +#define ADI_MASK8B01_M0_S 8 +#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B01_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B23 register. +// +//***************************************************************************** +#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 +#define ADI_MASK8B23_M1_S 24 +#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B23_D1_S 16 +#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 +#define ADI_MASK8B23_M0_S 8 +#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B23_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B45 register. +// +//***************************************************************************** +#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 +#define ADI_MASK8B45_M1_S 24 +#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B45_D1_S 16 +#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 +#define ADI_MASK8B45_M0_S 8 +#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B45_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B67 register. +// +//***************************************************************************** +#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 +#define ADI_MASK8B67_M1_S 24 +#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B67_D1_S 16 +#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 +#define ADI_MASK8B67_M0_S 8 +#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B67_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B89 register. +// +//***************************************************************************** +#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 +#define ADI_MASK8B89_M1_S 24 +#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B89_D1_S 16 +#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 +#define ADI_MASK8B89_M0_S 8 +#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B89_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1011 register. +// +//***************************************************************************** +#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 +#define ADI_MASK8B1011_M1_S 24 +#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1011_D1_S 16 +#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 +#define ADI_MASK8B1011_M0_S 8 +#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1011_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1213 register. +// +//***************************************************************************** +#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 +#define ADI_MASK8B1213_M1_S 24 +#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1213_D1_S 16 +#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 +#define ADI_MASK8B1213_M0_S 8 +#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1213_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1415 register. +// +//***************************************************************************** +#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 +#define ADI_MASK8B1415_M1_S 24 +#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1415_D1_S 16 +#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 +#define ADI_MASK8B1415_M0_S 8 +#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1415_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B01 register. +// +//***************************************************************************** +#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 +#define ADI_MASK16B01_M_S 16 +#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at + // offsets 0 and 1, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B01_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B23 register. +// +//***************************************************************************** +#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 +#define ADI_MASK16B23_M_S 16 +#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at + // offsets 2 and 3, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B23_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B45 register. +// +//***************************************************************************** +#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 +#define ADI_MASK16B45_M_S 16 +#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at + // offsets 4 and 5, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B45_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B67 register. +// +//***************************************************************************** +#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 +#define ADI_MASK16B67_M_S 16 +#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at + // offsets 6 and 7, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B67_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B89 register. +// +//***************************************************************************** +#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 +#define ADI_MASK16B89_M_S 16 +#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at + // offsets 8 and 9, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B89_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1011 register. +// +//***************************************************************************** +#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 +#define ADI_MASK16B1011_M_S 16 +#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at + // offsets 10 and 11, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1011_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1213 register. +// +//***************************************************************************** +#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 +#define ADI_MASK16B1213_M_S 16 +#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at + // offsets 12 and 13, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1213_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1415 register. +// +//***************************************************************************** +#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 +#define ADI_MASK16B1415_M_S 16 +#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at + // offsets 14 and 15, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1415_D_S 0 + +#endif // __HW_ADI_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h new file mode 100644 index 0000000..069c3d5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h @@ -0,0 +1,362 @@ +/****************************************************************************** +* Filename: hw_adi_2_refsys_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_2_REFSYS_H__ +#define __HW_ADI_2_REFSYS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_2_REFSYS component +// +//***************************************************************************** +// Internal +#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_REFSYSCTL0 +// +//***************************************************************************** +// Field: [4:0] TRIM_IREF +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL0 +// +//***************************************************************************** +// Field: [7:4] VTRIM_UDIG +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 + +// Field: [3:0] VTRIM_BOD +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL1 +// +//***************************************************************************** +// Field: [7:4] VTRIM_COARSE +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 + +// Field: [3:0] VTRIM_DIG +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL2 +// +//***************************************************************************** +// Field: [2:0] VTRIM_DELTA +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL3 +// +//***************************************************************************** +// Field: [7:6] ITRIM_DIGLDO_LOAD +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 + +// Field: [5:3] ITRIM_DIGLDO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BIAS_120P Internal. Only to be used through TI provided API. +// BIAS_100P Internal. Only to be used through TI provided API. +// BIAS_80P Internal. Only to be used through TI provided API. +// BIAS_60P Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 + +// Field: [2:0] ITRIM_UDIGLDO +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL4 +// +//***************************************************************************** +// Field: [6:5] UDIG_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 + +// Field: [4:2] DIG_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 + +// Field: [1] BIAS_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 + +// Field: [0] UDIG_LDO_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL5 +// +//***************************************************************************** +// Field: [3] IMON_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 + +// Field: [2:0] TESTSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDD_AON Internal. Only to be used through TI provided API. +// VREF_AMP Internal. Only to be used through TI provided API. +// ITEST Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL0 +// +//***************************************************************************** +// Field: [7] FILTER_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 + +// Field: [6:5] BIAS_RECHARGE_DLY +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// MIN_DLY_X8 Internal. Only to be used through TI provided API. +// MIN_DLY_X4 Internal. Only to be used through TI provided API. +// MIN_DLY_X2 Internal. Only to be used through TI provided API. +// MIN_DLY_X1 Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 + +// Field: [4:3] TUNE_CAP +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SHIFT_M108 Internal. Only to be used through TI provided API. +// SHIFT_M70 Internal. Only to be used through TI provided API. +// SHIFT_M35 Internal. Only to be used through TI provided API. +// SHIFT_0 Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 + +// Field: [2:1] SERIES_CAP +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 + +// Field: [0] DIV3_BYPASS +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// HPOSC_2520MHZ Internal. Only to be used through TI provided API. +// HPOSC_840MHZ Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL1 +// +//***************************************************************************** +// Field: [5] BIAS_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 + +// Field: [4] PWRDET_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 + +// Field: [3:0] BIAS_RES_SET +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL2 +// +//***************************************************************************** +// Field: [7] BIAS_HOLD_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 + +// Field: [6] TESTMUX_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 + +// Field: [5:4] ATEST_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 + +// Field: [3:0] CURRMIRR_RATIO +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 + + +#endif // __ADI_2_REFSYS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h new file mode 100644 index 0000000..5aab222 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h @@ -0,0 +1,685 @@ +/****************************************************************************** +* Filename: hw_adi_3_refsys_h +* Revised: 2018-09-27 10:33:21 +0200 (Thu, 27 Sep 2018) +* Revision: 52772 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_3_REFSYS_H__ +#define __HW_ADI_3_REFSYS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_3_REFSYS component +// +//***************************************************************************** +// Internal +#define ADI_3_REFSYS_O_ATESTCTL1 0x00000001 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 + +// DCDC Control 0 +#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 + +// DCDC Control 1 +#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 + +// DCDC Control 2 +#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 + +// Internal +#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 + +// Internal +#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A + +// Internal +#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B + +// RECHARGE_CONTROL_1 +#define ADI_3_REFSYS_O_AUX_DEBUG 0x0000000C + +// Recharge Comparator Control Byte 0 +#define ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 0x0000000D + +// Recharge Comparator Control Byte 1 +#define ADI_3_REFSYS_O_CTL_RECHARGE_CMP1 0x0000000E + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_ATESTCTL1 +// +//***************************************************************************** +// Field: [4:3] ATEST0_CTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// ICELL_A0 Internal. Only to be used through TI provided API. +// IREF_A0 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_W 2 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_M 0x00000018 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_S 3 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_ICELL_A0 0x00000010 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_IREF_A0 0x00000008 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_NC 0x00000000 + +// Field: [2:0] ATEST1_CTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VREFM_A1 Internal. Only to be used through TI provided API. +// VPP_DIV5_A1 Internal. Only to be used through TI provided API. +// VREAD_DIV2_A1 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_W 3 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_M 0x00000007 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_S 0 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VREFM_A1 0x00000004 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VPP_DIV5_A1 0x00000002 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VREAD_DIV2_A1 0x00000001 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL0 +// +//***************************************************************************** +// Field: [7:0] TESTCTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BMCOMPOUT Internal. Only to be used through TI provided API. +// VTEMP Internal. Only to be used through TI provided API. +// VREF0P8V Internal. Only to be used through TI provided API. +// VBGUNBUFF Internal. Only to be used through TI provided API. +// VBG Internal. Only to be used through TI provided API. +// IREF4U Internal. Only to be used through TI provided API. +// IVREF4U Internal. Only to be used through TI provided API. +// IPTAT2U Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL1 +// +//***************************************************************************** +// Field: [7:3] TRIM_VDDS_BOD +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// POS_27 Internal. Only to be used through TI provided API. +// POS_26 Internal. Only to be used through TI provided API. +// POS_25 Internal. Only to be used through TI provided API. +// POS_24 Internal. Only to be used through TI provided API. +// POS_31 Internal. Only to be used through TI provided API. +// POS_30 Internal. Only to be used through TI provided API. +// POS_29 Internal. Only to be used through TI provided API. +// POS_28 Internal. Only to be used through TI provided API. +// POS_19 Internal. Only to be used through TI provided API. +// POS_18 Internal. Only to be used through TI provided API. +// POS_17 Internal. Only to be used through TI provided API. +// POS_16 Internal. Only to be used through TI provided API. +// POS_23 Internal. Only to be used through TI provided API. +// POS_22 Internal. Only to be used through TI provided API. +// POS_21 Internal. Only to be used through TI provided API. +// POS_20 Internal. Only to be used through TI provided API. +// POS_11 Internal. Only to be used through TI provided API. +// POS_10 Internal. Only to be used through TI provided API. +// POS_9 Internal. Only to be used through TI provided API. +// POS_8 Internal. Only to be used through TI provided API. +// POS_15 Internal. Only to be used through TI provided API. +// POS_14 Internal. Only to be used through TI provided API. +// POS_13 Internal. Only to be used through TI provided API. +// POS_12 Internal. Only to be used through TI provided API. +// POS_3 Internal. Only to be used through TI provided API. +// POS_2 Internal. Only to be used through TI provided API. +// POS_1 Internal. Only to be used through TI provided API. +// POS_0 Internal. Only to be used through TI provided API. +// POS_7 Internal. Only to be used through TI provided API. +// POS_6 Internal. Only to be used through TI provided API. +// POS_5 Internal. Only to be used through TI provided API. +// POS_4 Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 + +// Field: [2] BATMON_COMP_TEST_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 + +// Field: [1:0] TESTCTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// IPTAT1U Internal. Only to be used through TI provided API. +// BMCOMPIN Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL2 +// +//***************************************************************************** +// Field: [7:4] TRIM_VREF +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 + +// Field: [3] BOD_EXTERNAL_REG_MODE +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE_M 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE_S 3 + +// Field: [1:0] TRIM_TSENSE +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL3 +// +//***************************************************************************** +// Field: [7] BOD_BG_TRIM_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 + +// Field: [6] VTEMP_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 + +// Field: [5:0] TRIM_VBG +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL0 +// +//***************************************************************************** +// Field: [7:5] GLDO_ISRC +// +// Set charge and re-charge current level. +// 2's complement encoding. +// +// 0x0: Default 11mA. +// 0x3: Max 15mA. +// 0x4: Max 5mA +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 + +// Field: [4:0] VDDR_TRIM +// +// Set the VDDR voltage. +// Proprietary encoding. +// +// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. +// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. +// Step size = 16mV +// +// 0x00: Default, about 1.63V. +// 0x05: Typical voltage after trim voltage 1.71V. +// 0x15: Max voltage 1.96V. +// 0x16: Min voltage 1.47V. +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL1 +// +//***************************************************************************** +// Field: [7:6] IPTAT_TRIM +// +// Trim GLDO bias current. +// Proprietary encoding. +// +// 0x0: Default +// 0x1: Increase GLDO bias by 1.3x. +// 0x2: Increase GLDO bias by 1.6x. +// 0x3: Decrease GLDO bias by 0.7x. +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 + +// Field: [5] VDDR_OK_HYST +// +// Increase the hysteresis for when VDDR is considered ok. +// +// 0: Hysteresis = 60mV +// 1: Hysteresis = 70mV +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 + +// Field: [4:0] VDDR_TRIM_SLEEP +// +// Set the min VDDR voltage threshold during sleep mode. +// Proprietary encoding. +// +// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. +// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. +// Step size = 16mV +// +// 0x00: Default, about 1.63V. +// 0x19: Typical voltage after trim voltage 1.52V. +// 0x15: Max voltage 1.96V. +// 0x16: Min voltage 1.47V. +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL2 +// +//***************************************************************************** +// Field: [6] TURNON_EA_SW +// +// Turn on erroramp switch +// +// 0: Erroramp Off (Default) +// 1: Erroramp On. Turns on GLDO error amp switch. +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 + +// Field: [5] TEST_VDDR +// +// Connect VDDR to ATEST bus +// +// 0: Not connected. +// 1: Connected +// +// Set TESTSEL = 0x0 first before setting this bit. +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 + +// Field: [4] BIAS_DIS +// +// Disable dummy bias current. +// +// 0: Dummy bias current on (Default) +// 1: Dummy bias current off +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 + +// Field: [3:0] TESTSEL +// +// Select signal for test bus, one hot. +// ENUMs: +// VDDROK VDDR_OK connected to test bus. +// IB1U 1uA bias current connected to test bus. +// PASSGATE Pass transistor gate voltage connected to test +// bus. +// ERRAMP_OUT Error amp output voltage connected to test bus. +// NC No signal connected to test bus. +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL3 +// +//***************************************************************************** +// Field: [1:0] VDDR_BOOST_COMP +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BOOST_P1 Internal. Only to be used through TI provided API. +// BOOST Internal. Only to be used through TI provided API. +// BOOST_N1 Internal. Only to be used through TI provided API. +// DEFAULT Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_W 2 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_M 0x00000003 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_S 0 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_P1 0x00000003 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST 0x00000002 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_N1 0x00000001 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_DEFAULT 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL4 +// +//***************************************************************************** +// Field: [7:6] DEADTIME_TRIM +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 + +// Field: [5:3] LOW_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 + +// Field: [2:0] HIGH_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL5 +// +//***************************************************************************** +// Field: [5] TESTN +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 + +// Field: [4] TESTP +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 + +// Field: [3] DITHER_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 + +// Field: [2:0] IPEAK +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_AUX_DEBUG +// +//***************************************************************************** +// Field: [6] LPM_BIAS_BACKUP_EN +// +// Activate the backup circuit in case the main circuit does not work +#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN 0x00000040 +#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN_M 0x00000040 +#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN_S 6 + +// Field: [5] DAC_DBG_OFFSET_COMP +// +// Offset compensation signal (Debug Mode) +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP 0x00000020 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP_M 0x00000020 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP_S 5 + +// Field: [4] DAC_DBG_HOLD +// +// S-H Cap hold signal (Debug Mode) +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD 0x00000010 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD_M 0x00000010 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD_S 4 + +// Field: [3] DAC_DBG_PRECHARGE +// +// PRE-CHARGE signal (Debug Mode) +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE 0x00000008 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE_M 0x00000008 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE_S 3 + +// Field: [2] DAC_DBG_CAP_SAMPLE +// +// Cap-array sample signal (Debug Mode) +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE 0x00000004 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE_M 0x00000004 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE_S 2 + +// Field: [1] DAC_DBG_SAMPLE +// +// S-H Cap sample signal (Debug Mode) +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE 0x00000002 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE_M 0x00000002 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE_S 1 + +// Field: [0] DAC_DBG_EN +// +// Enable Debug Mode +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN 0x00000001 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN_M 0x00000001 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 +// +//***************************************************************************** +// Field: [4] COMP_CLK_DISABLE +// +// Enable/Disable the 32 kHz clock (SCLK_LF) to the recharge comparator +// ENUMs: +// DIS Disable the clock +// EN Enable the clock +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE 0x00000010 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_M 0x00000010 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_S 4 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_DIS 0x00000010 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_EN 0x00000000 + +// Field: [3:0] TRIM_RECHARGE_COMP_REFLEVEL +// +// Trim ref level of recharge. +// +// 0xF: 90% of VDDR level. +// 0x0: 100% of VDDR level. +// +// Step size = 0.67% of VDDR level. +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_W \ + 4 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_M \ + 0x0000000F +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_S \ + 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_CTL_RECHARGE_CMP1 +// +//***************************************************************************** +// Field: [7] RECHARGE_BLOCK_VTRIG_EN +// +// Enable/Disable ATEST input to VDDR input of recharge comparator. Used for +// trimming the recharge voltage reference level +// ENUMs: +// EN Enable. VDDR input is connected to ATEST network +// DIS Disable. VDDR input is connected to VDDR itself +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN 0x00000080 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_M \ + 0x00000080 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_S \ + 7 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_EN \ + 0x00000080 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_DIS \ + 0x00000000 + +// Field: [6] RECHARGE_BLOCK_ATEST_EN +// +// Enable/Disable test inputs/outputs to recharge comparator block +// ENUMs: +// EN Enable +// DIS Disable +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN 0x00000040 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_M \ + 0x00000040 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_S \ + 6 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_EN \ + 0x00000040 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_DIS \ + 0x00000000 + +// Field: [5] FORCE_SAMPLE_VDDR +// +// Force Sample of VDDR on cap divider +// ENUMs: +// EN Enable +// DIS Disable +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR 0x00000020 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_M 0x00000020 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_S 5 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_EN 0x00000020 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_DIS 0x00000000 + +// Field: [4:0] TRIM_RECHARGE_COMP_OFFSET +// +// Trim offset of Recharge comparator. +// +// 0x00: Maximum degeneration on input side (VDDR side). +// 0x1F: Maximum degeneration on reference side from cap divider. +// 0x10: Nominal code. +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_W \ + 5 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_M \ + 0x0000001F +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_S \ + 0 + + +#endif // __ADI_3_REFSYS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h new file mode 100644 index 0000000..f17daf6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h @@ -0,0 +1,513 @@ +/****************************************************************************** +* Filename: hw_adi_4_aux_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_4_AUX_H__ +#define __HW_ADI_4_AUX_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_4_AUX component +// +//***************************************************************************** +// Internal +#define ADI_4_AUX_O_MUX0 0x00000000 + +// Internal +#define ADI_4_AUX_O_MUX1 0x00000001 + +// Internal +#define ADI_4_AUX_O_MUX2 0x00000002 + +// Internal +#define ADI_4_AUX_O_MUX3 0x00000003 + +// Current Source +#define ADI_4_AUX_O_ISRC 0x00000004 + +// Comparator +#define ADI_4_AUX_O_COMP 0x00000005 + +// Internal +#define ADI_4_AUX_O_MUX4 0x00000007 + +// ADC Control 0 +#define ADI_4_AUX_O_ADC0 0x00000008 + +// ADC Control 1 +#define ADI_4_AUX_O_ADC1 0x00000009 + +// ADC Reference 0 +#define ADI_4_AUX_O_ADCREF0 0x0000000A + +// ADC Reference 1 +#define ADI_4_AUX_O_ADCREF1 0x0000000B + +// Internal +#define ADI_4_AUX_O_LPMBIAS 0x0000000E + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX0 +// +//***************************************************************************** +// Field: [6] ADCCOMPB_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDDR_1P8V Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX0_ADCCOMPB_IN 0x00000040 +#define ADI_4_AUX_MUX0_ADCCOMPB_IN_M 0x00000040 +#define ADI_4_AUX_MUX0_ADCCOMPB_IN_S 6 +#define ADI_4_AUX_MUX0_ADCCOMPB_IN_VDDR_1P8V 0x00000040 +#define ADI_4_AUX_MUX0_ADCCOMPB_IN_NC 0x00000000 + +// Field: [3:0] COMPA_REF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// ADCVREFP Internal. Only to be used through TI provided API. +// VDDS Internal. Only to be used through TI provided API. +// VSS Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX0_COMPA_REF_W 4 +#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F +#define ADI_4_AUX_MUX0_COMPA_REF_S 0 +#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008 +#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004 +#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002 +#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX1 +// +//***************************************************************************** +// Field: [7:0] COMPA_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO19 Internal. Only to be used through TI provided API. +// AUXIO20 Internal. Only to be used through TI provided API. +// AUXIO21 Internal. Only to be used through TI provided API. +// AUXIO22 Internal. Only to be used through TI provided API. +// AUXIO23 Internal. Only to be used through TI provided API. +// AUXIO24 Internal. Only to be used through TI provided API. +// AUXIO25 Internal. Only to be used through TI provided API. +// AUXIO26 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX1_COMPA_IN_W 8 +#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF +#define ADI_4_AUX_MUX1_COMPA_IN_S 0 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO19 0x00000080 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO20 0x00000040 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO21 0x00000020 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO22 0x00000010 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO23 0x00000008 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO24 0x00000004 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO25 0x00000002 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO26 0x00000001 +#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX2 +// +//***************************************************************************** +// Field: [7:3] ADCCOMPB_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDDS Internal. Only to be used through TI provided API. +// VSS Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// ATEST1 Internal. Only to be used through TI provided API. +// ATEST0 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000 + +// Field: [2:0] DAC_VREF_SEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDDS Internal. Only to be used through TI provided API. +// ADCREF Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_W 3 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_M 0x00000007 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_S 0 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_VDDS 0x00000004 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_ADCREF 0x00000002 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX3 +// +//***************************************************************************** +// Field: [7:0] ADCCOMPB_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO19 Internal. Only to be used through TI provided API. +// AUXIO20 Internal. Only to be used through TI provided API. +// AUXIO21 Internal. Only to be used through TI provided API. +// AUXIO22 Internal. Only to be used through TI provided API. +// AUXIO23 Internal. Only to be used through TI provided API. +// AUXIO24 Internal. Only to be used through TI provided API. +// AUXIO25 Internal. Only to be used through TI provided API. +// AUXIO26 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO19 0x00000080 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO20 0x00000040 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO21 0x00000020 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO22 0x00000010 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO23 0x00000008 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO24 0x00000004 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO25 0x00000002 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO26 0x00000001 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ISRC +// +//***************************************************************************** +// Field: [7:2] TRIM +// +// Adjust current from current source. +// +// Output currents may be combined to get desired total current. +// ENUMs: +// 11P75U 11.75 uA +// 4P5U 4.5 uA +// 2P0U 2.0 uA +// 1P0U 1.0 uA +// 0P5U 0.5 uA +// 0P25U 0.25 uA +// NC No current connected +#define ADI_4_AUX_ISRC_TRIM_W 6 +#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC +#define ADI_4_AUX_ISRC_TRIM_S 2 +#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080 +#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040 +#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020 +#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010 +#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008 +#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004 +#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000 + +// Field: [0] EN +// +// Current source enable +#define ADI_4_AUX_ISRC_EN 0x00000001 +#define ADI_4_AUX_ISRC_EN_M 0x00000001 +#define ADI_4_AUX_ISRC_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_COMP +// +//***************************************************************************** +// Field: [7] COMPA_REF_RES_EN +// +// Enables 400kohm resistance from COMPA reference node to ground. Used with +// COMPA_REF_CURR_EN to generate voltage reference for cap-sense. +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7 + +// Field: [6] COMPA_REF_CURR_EN +// +// Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires +// ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for +// cap-sense. +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 + +// Field: [5:3] LPM_BIAS_WIDTH_TRIM +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_W 3 +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M 0x00000038 +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S 3 + +// Field: [2] COMPB_EN +// +// COMPB enable +#define ADI_4_AUX_COMP_COMPB_EN 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_S 2 + +// Field: [0] COMPA_EN +// +// COMPA enable +#define ADI_4_AUX_COMP_COMPA_EN 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX4 +// +//***************************************************************************** +// Field: [7:0] COMPA_REF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO19 Internal. Only to be used through TI provided API. +// AUXIO20 Internal. Only to be used through TI provided API. +// AUXIO21 Internal. Only to be used through TI provided API. +// AUXIO22 Internal. Only to be used through TI provided API. +// AUXIO23 Internal. Only to be used through TI provided API. +// AUXIO24 Internal. Only to be used through TI provided API. +// AUXIO25 Internal. Only to be used through TI provided API. +// AUXIO26 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX4_COMPA_REF_W 8 +#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF +#define ADI_4_AUX_MUX4_COMPA_REF_S 0 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO19 0x00000080 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO20 0x00000040 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO21 0x00000020 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO22 0x00000010 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO23 0x00000008 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO24 0x00000004 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO25 0x00000002 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO26 0x00000001 +#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADC0 +// +//***************************************************************************** +// Field: [7] SMPL_MODE +// +// ADC Sampling mode: +// +// 0: Synchronous mode +// 1: Asynchronous mode +// +// The ADC does a sample-and-hold before conversion. In synchronous mode the +// sampling starts when the ADC clock detects a rising edge on the trigger +// signal. Jitter/uncertainty will be inferred in the detection if the trigger +// signal originates from a domain that is asynchronous to the ADC clock. +// SMPL_CYCLE_EXP determines the the duration of sampling. +// Conversion starts immediately after sampling ends. +// +// In asynchronous mode the sampling is continuous when enabled. Sampling ends +// and conversion starts immediately with the rising edge of the trigger +// signal. Sampling restarts when the conversion has finished. +// Asynchronous mode is useful when it is important to avoid jitter in the +// sampling instant of an externally driven signal +#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_S 7 + +// Field: [6:3] SMPL_CYCLE_EXP +// +// Controls the sampling duration before conversion when the ADC is operated in +// synchronous mode (SMPL_MODE = 0). The setting has no effect in asynchronous +// mode. The sampling duration is given as 2^(SMPL_CYCLE_EXP + 1) / 6 us. +// ENUMs: +// 10P9_MS 65536x 6 MHz clock periods = 10.9ms +// 5P46_MS 32768x 6 MHz clock periods = 5.46ms +// 2P73_MS 16384x 6 MHz clock periods = 2.73ms +// 1P37_MS 8192x 6 MHz clock periods = 1.37ms +// 682_US 4096x 6 MHz clock periods = 682us +// 341_US 2048x 6 MHz clock periods = 341us +// 170_US 1024x 6 MHz clock periods = 170us +// 85P3_US 512x 6 MHz clock periods = 85.3us +// 42P6_US 256x 6 MHz clock periods = 42.6us +// 21P3_US 128x 6 MHz clock periods = 21.3us +// 10P6_US 64x 6 MHz clock periods = 10.6us +// 5P3_US 32x 6 MHz clock periods = 5.3us +// 2P7_US 16x 6 MHz clock periods = 2.7us +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018 + +// Field: [1] RESET_N +// +// Reset ADC digital subchip, active low. ADC must be reset every time it is +// reconfigured. +// +// 0: Reset +// 1: Normal operation +#define ADI_4_AUX_ADC0_RESET_N 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_S 1 + +// Field: [0] EN +// +// ADC Enable +// +// 0: Disable +// 1: Enable +#define ADI_4_AUX_ADC0_EN 0x00000001 +#define ADI_4_AUX_ADC0_EN_M 0x00000001 +#define ADI_4_AUX_ADC0_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADC1 +// +//***************************************************************************** +// Field: [0] SCALE_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADCREF0 +// +//***************************************************************************** +// Field: [6] REF_ON_IDLE +// +// Enable ADCREF in IDLE state. +// +// 0: Disabled in IDLE state +// 1: Enabled in IDLE state +// +// Keep ADCREF enabled when ADC0.SMPL_MODE = 0. +// Recommendation: Enable ADCREF always when ADC0.SMPL_CYCLE_EXP is less than +// 0x6 (21.3us sampling time). +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 + +// Field: [5] IOMUX +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_S 5 + +// Field: [4] EXT +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADCREF0_EXT 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_S 4 + +// Field: [3] SRC +// +// ADC reference source: +// +// 0: Fixed reference = 4.3V +// 1: Relative reference = VDDS +#define ADI_4_AUX_ADCREF0_SRC 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_S 3 + +// Field: [0] EN +// +// ADC reference module enable: +// +// 0: ADC reference module powered down +// 1: ADC reference module enabled +#define ADI_4_AUX_ADCREF0_EN 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_M 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADCREF1 +// +//***************************************************************************** +// Field: [5:0] VTRIM +// +// Trim output voltage of ADC fixed reference (64 steps, 2's complement). +// Applies only for ADCREF0.SRC = 0. +// +// Examples: +// 0x00 - nominal voltage 1.43V +// 0x01 - nominal + 0.4% 1.435V +// 0x3F - nominal - 0.4% 1.425V +// 0x1F - maximum voltage 1.6V +// 0x20 - minimum voltage 1.3V +#define ADI_4_AUX_ADCREF1_VTRIM_W 6 +#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F +#define ADI_4_AUX_ADCREF1_VTRIM_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_LPMBIAS +// +//***************************************************************************** +// Field: [5:0] LPM_TRIM_IOUT +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_W 6 +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M 0x0000003F +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S 0 + + +#endif // __ADI_4_AUX__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h new file mode 100644 index 0000000..257c8a6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h @@ -0,0 +1,662 @@ +/****************************************************************************** +* Filename: hw_aon_batmon_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_BATMON_H__ +#define __HW_AON_BATMON_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_BATMON component +// +//***************************************************************************** +// Internal +#define AON_BATMON_O_CTL 0x00000000 + +// Internal +#define AON_BATMON_O_MEASCFG 0x00000004 + +// Internal +#define AON_BATMON_O_TEMPP0 0x0000000C + +// Internal +#define AON_BATMON_O_TEMPP1 0x00000010 + +// Internal +#define AON_BATMON_O_TEMPP2 0x00000014 + +// Internal +#define AON_BATMON_O_BATMONP0 0x00000018 + +// Internal +#define AON_BATMON_O_BATMONP1 0x0000001C + +// Internal +#define AON_BATMON_O_IOSTRP0 0x00000020 + +// Internal +#define AON_BATMON_O_FLASHPUMPP0 0x00000024 + +// Last Measured Battery Voltage +#define AON_BATMON_O_BAT 0x00000028 + +// Battery Update +#define AON_BATMON_O_BATUPD 0x0000002C + +// Temperature +#define AON_BATMON_O_TEMP 0x00000030 + +// Temperature Update +#define AON_BATMON_O_TEMPUPD 0x00000034 + +// Event Mask +#define AON_BATMON_O_EVENTMASK 0x00000048 + +// Event +#define AON_BATMON_O_EVENT 0x0000004C + +// Battery Upper Limit +#define AON_BATMON_O_BATTUL 0x00000050 + +// Battery Lower Limit +#define AON_BATMON_O_BATTLL 0x00000054 + +// Temperature Upper Limit +#define AON_BATMON_O_TEMPUL 0x00000058 + +// Temperature Lower Limit +#define AON_BATMON_O_TEMPLL 0x0000005C + +//***************************************************************************** +// +// Register: AON_BATMON_O_CTL +// +//***************************************************************************** +// Field: [1] CALC_EN +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_CTL_CALC_EN 0x00000002 +#define AON_BATMON_CTL_CALC_EN_BITN 1 +#define AON_BATMON_CTL_CALC_EN_M 0x00000002 +#define AON_BATMON_CTL_CALC_EN_S 1 + +// Field: [0] MEAS_EN +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_CTL_MEAS_EN 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_BITN 0 +#define AON_BATMON_CTL_MEAS_EN_M 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_MEASCFG +// +//***************************************************************************** +// Field: [1:0] PER +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 32CYC Internal. Only to be used through TI provided API. +// 16CYC Internal. Only to be used through TI provided API. +// 8CYC Internal. Only to be used through TI provided API. +// CONT Internal. Only to be used through TI provided API. +#define AON_BATMON_MEASCFG_PER_W 2 +#define AON_BATMON_MEASCFG_PER_M 0x00000003 +#define AON_BATMON_MEASCFG_PER_S 0 +#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003 +#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002 +#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001 +#define AON_BATMON_MEASCFG_PER_CONT 0x00000000 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP0 +// +//***************************************************************************** +// Field: [7:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP0_CFG_W 8 +#define AON_BATMON_TEMPP0_CFG_M 0x000000FF +#define AON_BATMON_TEMPP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP1 +// +//***************************************************************************** +// Field: [5:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP1_CFG_W 6 +#define AON_BATMON_TEMPP1_CFG_M 0x0000003F +#define AON_BATMON_TEMPP1_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP2 +// +//***************************************************************************** +// Field: [4:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP2_CFG_W 5 +#define AON_BATMON_TEMPP2_CFG_M 0x0000001F +#define AON_BATMON_TEMPP2_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATMONP0 +// +//***************************************************************************** +// Field: [6:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_BATMONP0_CFG_W 7 +#define AON_BATMON_BATMONP0_CFG_M 0x0000007F +#define AON_BATMON_BATMONP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATMONP1 +// +//***************************************************************************** +// Field: [5:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_BATMONP1_CFG_W 6 +#define AON_BATMON_BATMONP1_CFG_M 0x0000003F +#define AON_BATMON_BATMONP1_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_IOSTRP0 +// +//***************************************************************************** +// Field: [5:4] CFG2 +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_IOSTRP0_CFG2_W 2 +#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030 +#define AON_BATMON_IOSTRP0_CFG2_S 4 + +// Field: [3:0] CFG1 +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_IOSTRP0_CFG1_W 4 +#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F +#define AON_BATMON_IOSTRP0_CFG1_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_FLASHPUMPP0 +// +//***************************************************************************** +// Field: [9] DIS_NOISE_FILTER +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER 0x00000200 +#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_BITN 9 +#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_M 0x00000200 +#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_S 9 + +// Field: [8] FALLB +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8 +#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_S 8 + +// Field: [7:6] HIGHLIM +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6 + +// Field: [5] LOWLIM +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5 + +// Field: [4] OVR +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4 +#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_S 4 + +// Field: [3:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_CFG_W 4 +#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F +#define AON_BATMON_FLASHPUMPP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BAT +// +//***************************************************************************** +// Field: [10:8] INT +// +// Integer part: +// +// 0x0: 0V + fractional part +// ... +// 0x3: 3V + fractional part +// 0x4: 4V + fractional part +#define AON_BATMON_BAT_INT_W 3 +#define AON_BATMON_BAT_INT_M 0x00000700 +#define AON_BATMON_BAT_INT_S 8 + +// Field: [7:0] FRAC +// +// Fractional part, standard binary fractional encoding. +// +// 0x00: .0V +// ... +// 0x20: 1/8 = .125V +// 0x40: 1/4 = .25V +// 0x80: 1/2 = .5V +// ... +// 0xA0: 1/2 + 1/8 = .625V +// ... +// 0xFF: Max +#define AON_BATMON_BAT_FRAC_W 8 +#define AON_BATMON_BAT_FRAC_M 0x000000FF +#define AON_BATMON_BAT_FRAC_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATUPD +// +//***************************************************************************** +// Field: [0] STAT +// +// +// 0: No update since last clear +// 1: New battery voltage is present. +// +// Write 1 to clear the status. +#define AON_BATMON_BATUPD_STAT 0x00000001 +#define AON_BATMON_BATUPD_STAT_BITN 0 +#define AON_BATMON_BATUPD_STAT_M 0x00000001 +#define AON_BATMON_BATUPD_STAT_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMP +// +//***************************************************************************** +// Field: [16:8] INT +// +// Integer part (signed) of temperature value. +// Total value = INTEGER + FRACTIONAL +// 2's complement encoding +// +// 0x100: Min value +// 0x1D8: -40C +// 0x1FF: -1C +// 0x00: 0C +// 0x1B: 27C +// 0x55: 85C +// 0xFF: Max value +#define AON_BATMON_TEMP_INT_W 9 +#define AON_BATMON_TEMP_INT_M 0x0001FF00 +#define AON_BATMON_TEMP_INT_S 8 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPUPD +// +//***************************************************************************** +// Field: [0] STAT +// +// +// 0: No update since last clear +// 1: New temperature is present. +// +// Write 1 to clear the status. +#define AON_BATMON_TEMPUPD_STAT 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_BITN 0 +#define AON_BATMON_TEMPUPD_STAT_M 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_EVENTMASK +// +//***************************************************************************** +// Field: [5] TEMP_UPDATE_MASK +// +// 1: EVENT.TEMP_UPDATE contributes to combined event from BATMON +// 0: EVENT.TEMP_UPDATE does not contribute to combined event from BATMON +#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK 0x00000020 +#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_BITN 5 +#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_M 0x00000020 +#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_S 5 + +// Field: [4] BATT_UPDATE_MASK +// +// 1: EVENT.BATT_UPDATE contributes to combined event from BATMON +// 0: EVENT.BATT_UPDATE does not contribute to combined event from BATMON +#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK 0x00000010 +#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_BITN 4 +#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_M 0x00000010 +#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_S 4 + +// Field: [3] TEMP_BELOW_LL_MASK +// +// 1: EVENT.TEMP_BELOW_LL contributes to combined event from BATMON +// 0: EVENT.TEMP_BELOW_LL does not contribute to combined event from BATMON +#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK 0x00000008 +#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_BITN 3 +#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_M 0x00000008 +#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_S 3 + +// Field: [2] TEMP_OVER_UL_MASK +// +// 1: EVENT.TEMP_OVER_UL contributes to combined event from BATMON +// 0: EVENT.TEMP_OVER_UL does not contribute to combined event from BATMON +#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK 0x00000004 +#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_BITN 2 +#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_M 0x00000004 +#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_S 2 + +// Field: [1] BATT_BELOW_LL_MASK +// +// 1: EVENT.BATT_BELOW_LL contributes to combined event from BATMON +// 0: EVENT.BATT_BELOW_LL does not contribute to combined event from BATMON +#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK 0x00000002 +#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_BITN 1 +#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_M 0x00000002 +#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_S 1 + +// Field: [0] BATT_OVER_UL_MASK +// +// 1: EVENT.BATT_OVER_UL contributes to combined event from BATMON +// 0: EVENT.BATT_OVER_UL does not contribute to combined event from BATMON +#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK 0x00000001 +#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_BITN 0 +#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_M 0x00000001 +#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_EVENT +// +//***************************************************************************** +// Field: [5] TEMP_UPDATE +// +// Alias to TEMPUPD.STAT +#define AON_BATMON_EVENT_TEMP_UPDATE 0x00000020 +#define AON_BATMON_EVENT_TEMP_UPDATE_BITN 5 +#define AON_BATMON_EVENT_TEMP_UPDATE_M 0x00000020 +#define AON_BATMON_EVENT_TEMP_UPDATE_S 5 + +// Field: [4] BATT_UPDATE +// +// Alias to BATUPD.STAT +#define AON_BATMON_EVENT_BATT_UPDATE 0x00000010 +#define AON_BATMON_EVENT_BATT_UPDATE_BITN 4 +#define AON_BATMON_EVENT_BATT_UPDATE_M 0x00000010 +#define AON_BATMON_EVENT_BATT_UPDATE_S 4 + +// Field: [3] TEMP_BELOW_LL +// +// Read: +// 1: Temperature level is below the lower limit set by TEMPLL. +// 0: Temperature level is not below the lower limit set by TEMPLL. +// Write: +// 1: Clears the flag +// 0: No change in the flag +#define AON_BATMON_EVENT_TEMP_BELOW_LL 0x00000008 +#define AON_BATMON_EVENT_TEMP_BELOW_LL_BITN 3 +#define AON_BATMON_EVENT_TEMP_BELOW_LL_M 0x00000008 +#define AON_BATMON_EVENT_TEMP_BELOW_LL_S 3 + +// Field: [2] TEMP_OVER_UL +// +// Read: +// 1: Temperature level is above the upper limit set by TEMPUL. +// 0: Temperature level is not above the upper limit set by TEMPUL. +// Write: +// 1: Clears the flag +// 0: No change in the flag +#define AON_BATMON_EVENT_TEMP_OVER_UL 0x00000004 +#define AON_BATMON_EVENT_TEMP_OVER_UL_BITN 2 +#define AON_BATMON_EVENT_TEMP_OVER_UL_M 0x00000004 +#define AON_BATMON_EVENT_TEMP_OVER_UL_S 2 + +// Field: [1] BATT_BELOW_LL +// +// Read: +// 1: Battery level is below the lower limit set by BATTLL. +// 0: Battery level is not below the lower limit set by BATTLL. +// Write: +// 1: Clears the flag +// 0: No change in the flag +#define AON_BATMON_EVENT_BATT_BELOW_LL 0x00000002 +#define AON_BATMON_EVENT_BATT_BELOW_LL_BITN 1 +#define AON_BATMON_EVENT_BATT_BELOW_LL_M 0x00000002 +#define AON_BATMON_EVENT_BATT_BELOW_LL_S 1 + +// Field: [0] BATT_OVER_UL +// +// Read: +// 1: Battery level is above the upper limit set by BATTUL. +// 0: Battery level is not above the upper limit set by BATTUL. +// Write: +// 1: Clears the flag +// 0: No change in the flag +#define AON_BATMON_EVENT_BATT_OVER_UL 0x00000001 +#define AON_BATMON_EVENT_BATT_OVER_UL_BITN 0 +#define AON_BATMON_EVENT_BATT_OVER_UL_M 0x00000001 +#define AON_BATMON_EVENT_BATT_OVER_UL_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATTUL +// +//***************************************************************************** +// Field: [10:8] INT +// +// Integer part: +// +// 0x0: 0V + fractional part +// ... +// 0x3: 3V + fractional part +// 0x4: 4V + fractional part +#define AON_BATMON_BATTUL_INT_W 3 +#define AON_BATMON_BATTUL_INT_M 0x00000700 +#define AON_BATMON_BATTUL_INT_S 8 + +// Field: [7:0] FRAC +// +// Fractional part, standard binary fractional encoding. +// +// 0x00: .0V +// ... +// 0x20: 1/8 = .125V +// 0x40: 1/4 = .25V +// 0x80: 1/2 = .5V +// ... +// 0xA0: 1/2 + 1/8 = .625V +// ... +// 0xFF: Max +#define AON_BATMON_BATTUL_FRAC_W 8 +#define AON_BATMON_BATTUL_FRAC_M 0x000000FF +#define AON_BATMON_BATTUL_FRAC_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATTLL +// +//***************************************************************************** +// Field: [10:8] INT +// +// Integer part: +// +// 0x0: 0V + fractional part +// ... +// 0x3: 3V + fractional part +// 0x4: 4V + fractional part +#define AON_BATMON_BATTLL_INT_W 3 +#define AON_BATMON_BATTLL_INT_M 0x00000700 +#define AON_BATMON_BATTLL_INT_S 8 + +// Field: [7:0] FRAC +// +// Fractional part, standard binary fractional encoding. +// +// 0x00: .0V +// ... +// 0x20: 1/8 = .125V +// 0x40: 1/4 = .25V +// 0x80: 1/2 = .5V +// ... +// 0xA0: 1/2 + 1/8 = .625V +// ... +// 0xFF: Max +#define AON_BATMON_BATTLL_FRAC_W 8 +#define AON_BATMON_BATTLL_FRAC_M 0x000000FF +#define AON_BATMON_BATTLL_FRAC_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPUL +// +//***************************************************************************** +// Field: [16:8] INT +// +// Integer part (signed) of temperature upper limit. +// Total value = INTEGER + FRACTIONAL +// 2's complement encoding +// +// 0x100: Min value +// 0x1D8: -40C +// 0x1FF: -1C +// 0x00: 0C +// 0x1B: 27C +// 0x55: 85C +// 0xFF: Max value +#define AON_BATMON_TEMPUL_INT_W 9 +#define AON_BATMON_TEMPUL_INT_M 0x0001FF00 +#define AON_BATMON_TEMPUL_INT_S 8 + +// Field: [7:6] FRAC +// +// Fractional part of temperature upper limit. +// Total value = INTEGER + FRACTIONAL +// The encoding is an extension of the 2's complement encoding. +// +// 00: 0.0C +// 01: 0.25C +// 10: 0.5C +// 11: 0.75C +// +// For example: +// 000000001,00 = ( 1+0,00) = 1,00 +// 000000000,11 = ( 0+0,75) = 0,75 +// 000000000,10 = ( 0+0,50) = 0,50 +// 000000000,01 = ( 0+0,25) = 0,25 +// 000000000,00 = ( 0+0,00) = 0,00 +// 111111111,11 = (-1+0,75) = -0,25 +// 111111111,10 = (-1+0,50) = -0,50 +// 111111111,01 = (-1+0,25) = -0,75 +// 111111111,00 = (-1+0,00) = -1,00 +// 111111110,11 = (-2+0,75) = -1,25 +#define AON_BATMON_TEMPUL_FRAC_W 2 +#define AON_BATMON_TEMPUL_FRAC_M 0x000000C0 +#define AON_BATMON_TEMPUL_FRAC_S 6 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPLL +// +//***************************************************************************** +// Field: [16:8] INT +// +// Integer part (signed) of temperature lower limit. +// Total value = INTEGER + FRACTIONAL +// 2's complement encoding +// +// 0x100: Min value +// 0x1D8: -40C +// 0x1FF: -1C +// 0x00: 0C +// 0x1B: 27C +// 0x55: 85C +// 0xFF: Max value +#define AON_BATMON_TEMPLL_INT_W 9 +#define AON_BATMON_TEMPLL_INT_M 0x0001FF00 +#define AON_BATMON_TEMPLL_INT_S 8 + +// Field: [7:6] FRAC +// +// Fractional part of temperature lower limit. +// Total value = INTEGER + FRACTIONAL +// The encoding is an extension of the 2's complement encoding. +// +// 00: 0.0C +// 01: 0.25C +// 10: 0.5C +// 11: 0.75C +// +// For example: +// 000000001,00 = ( 1+0,00) = 1,00 +// 000000000,11 = ( 0+0,75) = 0,75 +// 000000000,10 = ( 0+0,50) = 0,50 +// 000000000,01 = ( 0+0,25) = 0,25 +// 000000000,00 = ( 0+0,00) = 0,00 +// 111111111,11 = (-1+0,75) = -0,25 +// 111111111,10 = (-1+0,50) = -0,50 +// 111111111,01 = (-1+0,25) = -0,75 +// 111111111,00 = (-1+0,00) = -1,00 +// 111111110,11 = (-2+0,75) = -1,25 +#define AON_BATMON_TEMPLL_FRAC_W 2 +#define AON_BATMON_TEMPLL_FRAC_M 0x000000C0 +#define AON_BATMON_TEMPLL_FRAC_S 6 + + +#endif // __AON_BATMON__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h new file mode 100644 index 0000000..1f070c8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h @@ -0,0 +1,1135 @@ +/****************************************************************************** +* Filename: hw_aon_event_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_EVENT_H__ +#define __HW_AON_EVENT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_EVENT component +// +//***************************************************************************** +// Wake-up Selector For MCU +#define AON_EVENT_O_MCUWUSEL 0x00000000 + +// Wake-up Selector For MCU +#define AON_EVENT_O_MCUWUSEL1 0x00000004 + +// Event Selector For MCU Event Fabric +#define AON_EVENT_O_EVTOMCUSEL 0x00000008 + +// RTC Capture Event Selector For AON_RTC +#define AON_EVENT_O_RTCSEL 0x0000000C + +//***************************************************************************** +// +// Register: AON_EVENT_O_MCUWUSEL +// +//***************************************************************************** +// Field: [29:24] WU3_EV +// +// MCU Wakeup Source #3 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL_WU3_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_S 24 +#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_COMBINED 0x09000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP_LL 0x08000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP_UL 0x07000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_BATT_LL 0x06000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_BATT_UL 0x05000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV3 0x04000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV2 0x03000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV1 0x02000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV0 0x01000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_IOEV_MCU_WU 0x00000000 + +// Field: [21:16] WU2_EV +// +// MCU Wakeup Source #2 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL_WU2_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_S 16 +#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_COMBINED 0x00090000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP_LL 0x00080000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP_UL 0x00070000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_BATT_LL 0x00060000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_BATT_UL 0x00050000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV3 0x00040000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV2 0x00030000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV1 0x00020000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV0 0x00010000 +#define AON_EVENT_MCUWUSEL_WU2_EV_IOEV_MCU_WU 0x00000000 + +// Field: [13:8] WU1_EV +// +// MCU Wakeup Source #1 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL_WU1_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_S 8 +#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_COMBINED 0x00000900 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP_LL 0x00000800 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP_UL 0x00000700 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_BATT_LL 0x00000600 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_BATT_UL 0x00000500 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV3 0x00000400 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV2 0x00000300 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV1 0x00000200 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV0 0x00000100 +#define AON_EVENT_MCUWUSEL_WU1_EV_IOEV_MCU_WU 0x00000000 + +// Field: [5:0] WU0_EV +// +// MCU Wakeup Source #0 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL_WU0_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_S 0 +#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_COMBINED 0x00000009 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP_LL 0x00000008 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP_UL 0x00000007 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_BATT_LL 0x00000006 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_BATT_UL 0x00000005 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV3 0x00000004 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV2 0x00000003 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV1 0x00000002 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV0 0x00000001 +#define AON_EVENT_MCUWUSEL_WU0_EV_IOEV_MCU_WU 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_MCUWUSEL1 +// +//***************************************************************************** +// Field: [29:24] WU7_EV +// +// MCU Wakeup Source #7 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL1_WU7_EV_W 6 +#define AON_EVENT_MCUWUSEL1_WU7_EV_M 0x3F000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_S 24 +#define AON_EVENT_MCUWUSEL1_WU7_EV_NONE 0x3F000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB_ASYNC_N 0x38000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB_ASYNC 0x37000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_VOLT 0x36000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP 0x35000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER1_EV 0x34000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER0_EV 0x33000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TDC_DONE 0x32000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_ADC_DONE 0x31000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB 0x30000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPA 0x2F000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV2 0x2E000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV1 0x2D000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV0 0x2C000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_JTAG 0x2B000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_UPD 0x2A000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_COMB_DLY 0x29000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH2_DLY 0x28000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH1_DLY 0x27000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH0_DLY 0x26000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH2 0x25000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH1 0x24000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH0 0x23000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_PAD 0x20000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_COMBINED 0x09000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP_LL 0x08000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP_UL 0x07000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_BATT_LL 0x06000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_BATT_UL 0x05000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV3 0x04000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV2 0x03000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV1 0x02000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV0 0x01000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_IOEV_MCU_WU 0x00000000 + +// Field: [21:16] WU6_EV +// +// MCU Wakeup Source #6 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL1_WU6_EV_W 6 +#define AON_EVENT_MCUWUSEL1_WU6_EV_M 0x003F0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_S 16 +#define AON_EVENT_MCUWUSEL1_WU6_EV_NONE 0x003F0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_JTAG 0x002B0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH2 0x00250000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH1 0x00240000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH0 0x00230000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_PAD 0x00200000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_COMBINED 0x00090000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP_LL 0x00080000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP_UL 0x00070000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_BATT_LL 0x00060000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_BATT_UL 0x00050000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV3 0x00040000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV2 0x00030000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV1 0x00020000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV0 0x00010000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_IOEV_MCU_WU 0x00000000 + +// Field: [13:8] WU5_EV +// +// MCU Wakeup Source #5 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL1_WU5_EV_W 6 +#define AON_EVENT_MCUWUSEL1_WU5_EV_M 0x00003F00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_S 8 +#define AON_EVENT_MCUWUSEL1_WU5_EV_NONE 0x00003F00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_JTAG 0x00002B00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH2 0x00002500 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH1 0x00002400 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH0 0x00002300 +#define AON_EVENT_MCUWUSEL1_WU5_EV_PAD 0x00002000 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_COMBINED 0x00000900 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP_LL 0x00000800 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP_UL 0x00000700 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_BATT_LL 0x00000600 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_BATT_UL 0x00000500 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV3 0x00000400 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV2 0x00000300 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV1 0x00000200 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV0 0x00000100 +#define AON_EVENT_MCUWUSEL1_WU5_EV_IOEV_MCU_WU 0x00000000 + +// Field: [5:0] WU4_EV +// +// MCU Wakeup Source #4 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL1_WU4_EV_W 6 +#define AON_EVENT_MCUWUSEL1_WU4_EV_M 0x0000003F +#define AON_EVENT_MCUWUSEL1_WU4_EV_S 0 +#define AON_EVENT_MCUWUSEL1_WU4_EV_NONE 0x0000003F +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_MCUWUSEL1_WU4_EV_JTAG 0x0000002B +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_UPD 0x0000002A +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH2 0x00000025 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH1 0x00000024 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH0 0x00000023 +#define AON_EVENT_MCUWUSEL1_WU4_EV_PAD 0x00000020 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_COMBINED 0x00000009 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP_LL 0x00000008 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP_UL 0x00000007 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_BATT_LL 0x00000006 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_BATT_UL 0x00000005 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV3 0x00000004 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV2 0x00000003 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV1 0x00000002 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV0 0x00000001 +#define AON_EVENT_MCUWUSEL1_WU4_EV_IOEV_MCU_WU 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_EVTOMCUSEL +// +//***************************************************************************** +// Field: [21:16] AON_PROG2_EV +// +// Event selector for AON_PROG2 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG2 event. +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_AON_PROG2 Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_AON_PROG2 in +// [MCU_IOC:IOCFGx.IOEV_AON_PROG2_EN] +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_COMBINED 0x00090000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP_LL 0x00080000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP_UL 0x00070000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_BATT_LL 0x00060000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_BATT_UL 0x00050000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV3 0x00040000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV2 0x00030000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV1 0x00020000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV0 0x00010000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_IOEV_AON_PROG2 0x00000000 + +// Field: [13:8] AON_PROG1_EV +// +// Event selector for AON_PROG1 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG1 event. +// ENUMs: +// NONE +// AUX_COMPB_ASYNC_N +// AUX_COMPB_ASYNC +// BATMON_VOLT +// BATMON_TEMP +// AUX_TIMER1_EV +// AUX_TIMER0_EV +// AUX_TDC_DONE +// AUX_ADC_DONE +// AUX_COMPB +// AUX_COMPA +// AUX_SWEV2 +// AUX_SWEV1 +// AUX_SWEV0 +// JTAG +// RTC_UPD +// RTC_COMB_DLY +// RTC_CH2_DLY +// RTC_CH1_DLY +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_AON_PROG1 Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_AON_PROG1 in +// [MCU_IOC:IOCFGx.IOEV_AON_PROG1_EN] +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_COMBINED 0x00000900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP_LL 0x00000800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP_UL 0x00000700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_BATT_LL 0x00000600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_BATT_UL 0x00000500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV3 0x00000400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV2 0x00000300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV1 0x00000200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV0 0x00000100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_IOEV_AON_PROG1 0x00000000 + +// Field: [5:0] AON_PROG0_EV +// +// Event selector for AON_PROG0 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG0 event. +// ENUMs: +// NONE +// AUX_COMPB_ASYNC_N +// AUX_COMPB_ASYNC +// BATMON_VOLT +// BATMON_TEMP +// AUX_TIMER1_EV +// AUX_TIMER0_EV +// AUX_TDC_DONE +// AUX_ADC_DONE +// AUX_COMPB +// AUX_COMPA +// AUX_SWEV2 +// AUX_SWEV1 +// AUX_SWEV0 +// JTAG +// RTC_UPD +// RTC_COMB_DLY +// RTC_CH2_DLY +// RTC_CH1_DLY +// RTC_CH0_DLY +// RTC_CH2 +// RTC_CH1 +// RTC_CH0 +// PAD +// BATMON_COMBINED +// BATMON_TEMP_LL +// BATMON_TEMP_UL +// BATMON_BATT_LL +// BATMON_BATT_UL +// AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 +// IOEV_AON_PROG0 Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_AON_PROG0 in +// [MCU_IOC:IOCFGx.IOEV_AON_PROG0_EN] +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_COMBINED 0x00000009 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP_LL 0x00000008 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP_UL 0x00000007 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_BATT_LL 0x00000006 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_BATT_UL 0x00000005 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV3 0x00000004 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV2 0x00000003 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV1 0x00000002 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV0 0x00000001 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_IOEV_AON_PROG0 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_RTCSEL +// +//***************************************************************************** +// Field: [5:0] RTC_CH1_CAPT_EV +// +// AON Event Source id# for RTCSEL event which is fed to AON_RTC. Please refer +// to AON_RTC:CH1CAPT +// ENUMs: +// NONE +// AUX_COMPB_ASYNC_N +// AUX_COMPB_ASYNC +// BATMON_VOLT +// BATMON_TEMP +// AUX_TIMER1_EV +// AUX_TIMER0_EV +// AUX_TDC_DONE +// AUX_ADC_DONE +// AUX_COMPB +// AUX_COMPA +// AUX_SWEV2 +// AUX_SWEV1 +// AUX_SWEV0 +// JTAG +// RTC_UPD +// RTC_COMB_DLY +// RTC_CH2_DLY +// RTC_CH1_DLY +// RTC_CH0_DLY +// RTC_CH2 +// RTC_CH1 +// RTC_CH0 +// PAD +// BATMON_COMBINED +// BATMON_TEMP_LL +// BATMON_TEMP_UL +// BATMON_BATT_LL +// BATMON_BATT_UL +// AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 +// IOEV_RTC Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_RTC in +// [MCU_IOC:IOCFGx.IOEV_RTC_EN] +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_COMBINED 0x00000009 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP_LL 0x00000008 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP_UL 0x00000007 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_BATT_LL 0x00000006 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_BATT_UL 0x00000005 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV3 0x00000004 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV2 0x00000003 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV1 0x00000002 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV0 0x00000001 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_IOEV_RTC 0x00000000 + + +#endif // __AON_EVENT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h new file mode 100644 index 0000000..b40b8fa --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h @@ -0,0 +1,158 @@ +/****************************************************************************** +* Filename: hw_aon_ioc_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_IOC_H__ +#define __HW_AON_IOC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_IOC component +// +//***************************************************************************** +// Internal +#define AON_IOC_O_IOSTRMIN 0x00000000 + +// Internal +#define AON_IOC_O_IOSTRMED 0x00000004 + +// Internal +#define AON_IOC_O_IOSTRMAX 0x00000008 + +// IO Latch Control +#define AON_IOC_O_IOCLATCH 0x0000000C + +// SCLK_LF External Output Control +#define AON_IOC_O_CLK32KCTL 0x00000010 + +// TCK IO Pin Control +#define AON_IOC_O_TCKCTL 0x00000014 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMIN +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMED +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMED_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMED_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMAX +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOCLATCH +// +//***************************************************************************** +// Field: [0] EN +// +// Controls latches between MCU IOC and AON_IOC. +// +// The latches are transparent by default. +// +// They must be closed prior to power off the domain(s) controlling the IOs in +// order to preserve IO values on external pins. +// ENUMs: +// TRANSP Latches are transparent, meaning the value of the +// IO is directly controlled by the GPIO or +// peripheral value +// STATIC Latches are static, meaning the current value on +// the IO pin is frozen by latches and kept even +// if GPIO module or a peripheral module is turned +// off +#define AON_IOC_IOCLATCH_EN 0x00000001 +#define AON_IOC_IOCLATCH_EN_BITN 0 +#define AON_IOC_IOCLATCH_EN_M 0x00000001 +#define AON_IOC_IOCLATCH_EN_S 0 +#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001 +#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000 + +//***************************************************************************** +// +// Register: AON_IOC_O_CLK32KCTL +// +//***************************************************************************** +// Field: [0] OE_N +// +// 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (for +// example IOC:IOCFG0.PORT_ID) set to AON_CLK32K. +// 1: Output enable not active +#define AON_IOC_CLK32KCTL_OE_N 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_BITN 0 +#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_TCKCTL +// +//***************************************************************************** +// Field: [0] EN +// +// 0: Input driver for TCK disabled. +// 1: Input driver for TCK enabled. +#define AON_IOC_TCKCTL_EN 0x00000001 +#define AON_IOC_TCKCTL_EN_BITN 0 +#define AON_IOC_TCKCTL_EN_M 0x00000001 +#define AON_IOC_TCKCTL_EN_S 0 + + +#endif // __AON_IOC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h new file mode 100644 index 0000000..33192cf --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h @@ -0,0 +1,625 @@ +/****************************************************************************** +* Filename: hw_aon_pmctl_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_PMCTL_H__ +#define __HW_AON_PMCTL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_PMCTL component +// +//***************************************************************************** +// AUX SCE Clock Management +#define AON_PMCTL_O_AUXSCECLK 0x00000004 + +// RAM Configuration +#define AON_PMCTL_O_RAMCFG 0x00000008 + +// Power Management Control +#define AON_PMCTL_O_PWRCTL 0x00000010 + +// AON Power and Reset Status +#define AON_PMCTL_O_PWRSTAT 0x00000014 + +// Shutdown Control +#define AON_PMCTL_O_SHUTDOWN 0x00000018 + +// Recharge Controller Configuration +#define AON_PMCTL_O_RECHARGECFG 0x0000001C + +// Recharge Controller Status +#define AON_PMCTL_O_RECHARGESTAT 0x00000020 + +// Oscillator Configuration +#define AON_PMCTL_O_OSCCFG 0x00000024 + +// Reset Management +#define AON_PMCTL_O_RESETCTL 0x00000028 + +// Sleep Control +#define AON_PMCTL_O_SLEEPCTL 0x0000002C + +// JTAG Configuration +#define AON_PMCTL_O_JTAGCFG 0x00000034 + +// JTAG USERCODE +#define AON_PMCTL_O_JTAGUSERCODE 0x0000003C + +//***************************************************************************** +// +// Register: AON_PMCTL_O_AUXSCECLK +// +//***************************************************************************** +// Field: [8] PD_SRC +// +// Selects the clock source for the AUX domain when AUX is in powerdown mode. +// Note: Switching the clock source is guaranteed to be glitch-free +// ENUMs: +// SCLK_LF LF clock (SCLK_LF ) +// NO_CLOCK No clock +#define AON_PMCTL_AUXSCECLK_PD_SRC 0x00000100 +#define AON_PMCTL_AUXSCECLK_PD_SRC_BITN 8 +#define AON_PMCTL_AUXSCECLK_PD_SRC_M 0x00000100 +#define AON_PMCTL_AUXSCECLK_PD_SRC_S 8 +#define AON_PMCTL_AUXSCECLK_PD_SRC_SCLK_LF 0x00000100 +#define AON_PMCTL_AUXSCECLK_PD_SRC_NO_CLOCK 0x00000000 + +// Field: [0] SRC +// +// Selects the clock source for the AUX domain when AUX is in active mode. +// Note: Switching the clock source is guaranteed to be glitch-free +// ENUMs: +// SCLK_MF MF Clock (SCLK_MF) +// SCLK_HFDIV2 HF Clock divided by 2 (SCLK_HFDIV2) +#define AON_PMCTL_AUXSCECLK_SRC 0x00000001 +#define AON_PMCTL_AUXSCECLK_SRC_BITN 0 +#define AON_PMCTL_AUXSCECLK_SRC_M 0x00000001 +#define AON_PMCTL_AUXSCECLK_SRC_S 0 +#define AON_PMCTL_AUXSCECLK_SRC_SCLK_MF 0x00000001 +#define AON_PMCTL_AUXSCECLK_SRC_SCLK_HFDIV2 0x00000000 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_RAMCFG +// +//***************************************************************************** +// Field: [17] AUX_SRAM_PWR_OFF +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF 0x00020000 +#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_BITN 17 +#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_M 0x00020000 +#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_S 17 + +// Field: [16] AUX_SRAM_RET_EN +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN 0x00010000 +#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_BITN 16 +#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_M 0x00010000 +#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_S 16 + +// Field: [3:0] BUS_SRAM_RET_EN +// +// MCU SRAM is partitioned into 5 banks . This register controls which of the +// banks that has retention during MCU Bus domain power off +// ENUMs: +// RET_FULL Retention on for all banks SRAM:BANK0, SRAM:BANK1 +// ,SRAM:BANK2, SRAM:BANK3 and SRAM:BANK4 +// RET_LEVEL3 Retention on for SRAM:BANK0, SRAM:BANK1 +// ,SRAM:BANK2 and SRAM:BANK3 +// RET_LEVEL2 Retention on for SRAM:BANK0, SRAM:BANK1 and +// SRAM:BANK2 +// RET_LEVEL1 Retention on for SRAM:BANK0 and SRAM:BANK1 +// RET_NONE Retention is disabled +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_W 4 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_M 0x0000000F +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_S 0 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL 0x0000000F +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3 0x00000007 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2 0x00000003 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1 0x00000001 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_PWRCTL +// +//***************************************************************************** +// Field: [2] DCDC_ACTIVE +// +// Select to use DCDC regulator for VDDR in active mode +// +// 0: Use GLDO for regulation of VDDR in active mode. +// 1: Use DCDC for regulation of VDDR in active mode. +// +// DCDC_EN must also be set for DCDC to be used as regulator for VDDR in active +// mode +#define AON_PMCTL_PWRCTL_DCDC_ACTIVE 0x00000004 +#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN 2 +#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 +#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_S 2 + +// Field: [1] EXT_REG_MODE +// +// Status of source for VDDRsupply: +// +// 0: DCDC or GLDO are generating VDDR +// 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR +#define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002 +#define AON_PMCTL_PWRCTL_EXT_REG_MODE_BITN 1 +#define AON_PMCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 +#define AON_PMCTL_PWRCTL_EXT_REG_MODE_S 1 + +// Field: [0] DCDC_EN +// +// Select to use DCDC regulator during recharge of VDDR +// +// 0: Use GLDO for recharge of VDDR +// 1: Use DCDC for recharge of VDDR +// +// Note: This bitfield should be set to the same as DCDC_ACTIVE +#define AON_PMCTL_PWRCTL_DCDC_EN 0x00000001 +#define AON_PMCTL_PWRCTL_DCDC_EN_BITN 0 +#define AON_PMCTL_PWRCTL_DCDC_EN_M 0x00000001 +#define AON_PMCTL_PWRCTL_DCDC_EN_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_PWRSTAT +// +//***************************************************************************** +// Field: [2] JTAG_PD_ON +// +// Indicates JTAG power state: +// +// 0: JTAG is powered off +// 1: JTAG is powered on +#define AON_PMCTL_PWRSTAT_JTAG_PD_ON 0x00000004 +#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_BITN 2 +#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_M 0x00000004 +#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_S 2 + +// Field: [1] AUX_BUS_RESET_DONE +// +// Indicates Reset Done from AUX Bus: +// +// 0: AUX Bus is being reset +// 1: AUX Bus reset is released +#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE 0x00000002 +#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_BITN 1 +#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_M 0x00000002 +#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_S 1 + +// Field: [0] AUX_RESET_DONE +// +// Indicates Reset Done from AUX: +// +// 0: AUX is being reset +// 1: AUX reset is released +#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE 0x00000001 +#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_BITN 0 +#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_M 0x00000001 +#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_SHUTDOWN +// +//***************************************************************************** +// Field: [0] EN +// +// Shutdown control. +// +// 0: Do not write 0 to this bit. +// 1: Immediately start the process to enter shutdown mode +#define AON_PMCTL_SHUTDOWN_EN 0x00000001 +#define AON_PMCTL_SHUTDOWN_EN_BITN 0 +#define AON_PMCTL_SHUTDOWN_EN_M 0x00000001 +#define AON_PMCTL_SHUTDOWN_EN_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_RECHARGECFG +// +//***************************************************************************** +// Field: [31:30] MODE +// +// Selects recharge algorithm for VDDR when the system is running on the uLDO +// ENUMs: +// COMPARATOR External recharge comparator. +// Note that the clock to +// the recharge comparator must be enabled, +// +// [ANATOP_MMAP:ADI_3_REFSYS:CTL_RECHARGE_CMP0:COMP_CLK_DISABLE], +// before selecting this recharge algorithm. +// ADAPTIVE Adaptive timer +// STATIC Static timer +// OFF Recharge disabled +#define AON_PMCTL_RECHARGECFG_MODE_W 2 +#define AON_PMCTL_RECHARGECFG_MODE_M 0xC0000000 +#define AON_PMCTL_RECHARGECFG_MODE_S 30 +#define AON_PMCTL_RECHARGECFG_MODE_COMPARATOR 0xC0000000 +#define AON_PMCTL_RECHARGECFG_MODE_ADAPTIVE 0x80000000 +#define AON_PMCTL_RECHARGECFG_MODE_STATIC 0x40000000 +#define AON_PMCTL_RECHARGECFG_MODE_OFF 0x00000000 + +// Field: [23:20] C2 +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RECHARGECFG_C2_W 4 +#define AON_PMCTL_RECHARGECFG_C2_M 0x00F00000 +#define AON_PMCTL_RECHARGECFG_C2_S 20 + +// Field: [19:16] C1 +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RECHARGECFG_C1_W 4 +#define AON_PMCTL_RECHARGECFG_C1_M 0x000F0000 +#define AON_PMCTL_RECHARGECFG_C1_S 16 + +// Field: [15:11] MAX_PER_M +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RECHARGECFG_MAX_PER_M_W 5 +#define AON_PMCTL_RECHARGECFG_MAX_PER_M_M 0x0000F800 +#define AON_PMCTL_RECHARGECFG_MAX_PER_M_S 11 + +// Field: [10:8] MAX_PER_E +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RECHARGECFG_MAX_PER_E_W 3 +#define AON_PMCTL_RECHARGECFG_MAX_PER_E_M 0x00000700 +#define AON_PMCTL_RECHARGECFG_MAX_PER_E_S 8 + +// Field: [7:3] PER_M +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RECHARGECFG_PER_M_W 5 +#define AON_PMCTL_RECHARGECFG_PER_M_M 0x000000F8 +#define AON_PMCTL_RECHARGECFG_PER_M_S 3 + +// Field: [2:0] PER_E +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RECHARGECFG_PER_E_W 3 +#define AON_PMCTL_RECHARGECFG_PER_E_M 0x00000007 +#define AON_PMCTL_RECHARGECFG_PER_E_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_RECHARGESTAT +// +//***************************************************************************** +// Field: [19:16] VDDR_SMPLS +// +// The last 4 VDDR samples. +// +// For each bit: +// 0: VDDR was below VDDR_OK threshold when recharge started +// 1: VDDR was above VDDR_OK threshold when recharge started +// +// The register is updated prior to every recharge period with a shift left, +// and bit 0 is updated with the last VDDR sample. +#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_W 4 +#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 +#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_S 16 + +// Field: [15:0] MAX_USED_PER +// +// Shows the maximum number of 32kHz periods that have separated two recharge +// cycles and VDDR still was above VDDR_OK threshold when the latter recharge +// started. This register can be used as an indication of the leakage current +// during standby. +// +// This bitfield is cleared to 0 when writing this register. +#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_W 16 +#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF +#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_OSCCFG +// +//***************************************************************************** +// Field: [7:3] PER_M +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_OSCCFG_PER_M_W 5 +#define AON_PMCTL_OSCCFG_PER_M_M 0x000000F8 +#define AON_PMCTL_OSCCFG_PER_M_S 3 + +// Field: [2:0] PER_E +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_OSCCFG_PER_E_W 3 +#define AON_PMCTL_OSCCFG_PER_E_M 0x00000007 +#define AON_PMCTL_OSCCFG_PER_E_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_RESETCTL +// +//***************************************************************************** +// Field: [31] SYSRESET +// +// Cold reset register. Writing 1 to this bitfield will reset the entire chip +// and cause boot code to run again. +// +// 0: No effect +// 1: Generate system reset. Appears as SYSRESET in RESET_SRC +#define AON_PMCTL_RESETCTL_SYSRESET 0x80000000 +#define AON_PMCTL_RESETCTL_SYSRESET_BITN 31 +#define AON_PMCTL_RESETCTL_SYSRESET_M 0x80000000 +#define AON_PMCTL_RESETCTL_SYSRESET_S 31 + +// Field: [25] BOOT_DET_1_CLR +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_S 25 + +// Field: [24] BOOT_DET_0_CLR +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_S 24 + +// Field: [17] BOOT_DET_1_SET +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_S 17 + +// Field: [16] BOOT_DET_0_SET +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_S 16 + +// Field: [15] WU_FROM_SD +// +// A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from +// SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin +// being forced low) +// +// Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup +// sources. +// +// 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC +// 1: A wakeup has occurred from SHUTDOWN +// +// Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. +#define AON_PMCTL_RESETCTL_WU_FROM_SD 0x00008000 +#define AON_PMCTL_RESETCTL_WU_FROM_SD_BITN 15 +#define AON_PMCTL_RESETCTL_WU_FROM_SD_M 0x00008000 +#define AON_PMCTL_RESETCTL_WU_FROM_SD_S 15 + +// Field: [14] GPIO_WU_FROM_SD +// +// A wakeup from SHUTDOWN on an IO event has occurred +// +// Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup +// sources. +// +// 0: The wakeup did not occur from SHUTDOWN on an IO event +// 1: A wakeup from SHUTDOWN occurred from an IO event +// +// The case where WU_FROM_SD is asserted but this bitfield is not asserted will +// only occur in a debug session. The boot code will not proceed with wakeup +// from SHUTDOWN procedure until this bitfield is asserted as well. +// +// Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. +#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 +#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 +#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 +#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 + +// Field: [13] BOOT_DET_1 +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_BOOT_DET_1 0x00002000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_BITN 13 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_M 0x00002000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_S 13 + +// Field: [12] BOOT_DET_0 +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_BOOT_DET_0 0x00001000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_BITN 12 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_M 0x00001000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_S 12 + +// Field: [8] VDDS_LOSS_EN +// +// Controls reset generation in case VDDS is lost +// +// 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 +// 1: Brown out detect of VDDS generates system reset +#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN 0x00000100 +#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_BITN 8 +#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000100 +#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_S 8 + +// Field: [7] VDDR_LOSS_EN +// +// Controls reset generation in case VDDR is lost +// +// 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 +// 1: Brown out detect of VDDR generates system reset +#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN 0x00000080 +#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_BITN 7 +#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000080 +#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_S 7 + +// Field: [6] VDD_LOSS_EN +// +// Controls reset generation in case VDD is lost +// +// 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 +// 1: Brown out detect of VDD generates system reset +#define AON_PMCTL_RESETCTL_VDD_LOSS_EN 0x00000040 +#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_BITN 6 +#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_M 0x00000040 +#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_S 6 + +// Field: [5] CLK_LOSS_EN +// +// Controls reset generation in case SCLK_LF, SCLK_MF or SCLK_HF is lost when +// clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] +// +// 0: Clock loss is ignored +// 1: Clock loss generates system reset +// +// Note: Clock loss reset generation must be disabled when changing clock +// source for SCLK_LF. Failure to do so may result in a spurious system +// reset. Clock loss reset generation is controlled by +// [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] +#define AON_PMCTL_RESETCTL_CLK_LOSS_EN 0x00000020 +#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN 5 +#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_M 0x00000020 +#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_S 5 + +// Field: [4] MCU_WARM_RESET +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_MCU_WARM_RESET 0x00000010 +#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_BITN 4 +#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_M 0x00000010 +#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_S 4 + +// Field: [3:1] RESET_SRC +// +// Shows the root cause of the last system reset. More than the reported reset +// source can have been active during the last system reset but only the root +// cause is reported. +// +// The capture feature is not rearmed until all off the possible reset sources +// have been released and the result has been copied to AON_PMCTL. During the +// copy and rearm process it is one 2MHz period in which and eventual new +// system reset will be reported as Power on reset regardless of the root +// cause. +// ENUMs: +// WARMRESET Software reset via PRCM warm reset request +// SYSRESET Software reset via SYSRESET or hardware power +// management timeout detection. +// +// Note: The hardware power +// management timeout circuit is always enabled. +// CLK_LOSS SCLK_LF, SCLK_MF or SCLK_HF clock loss detect +// VDDR_LOSS Brown out detect on VDDR +// VDDS_LOSS Brown out detect on VDDS +// PIN_RESET Reset pin +// PWR_ON Power on reset +#define AON_PMCTL_RESETCTL_RESET_SRC_W 3 +#define AON_PMCTL_RESETCTL_RESET_SRC_M 0x0000000E +#define AON_PMCTL_RESETCTL_RESET_SRC_S 1 +#define AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E +#define AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C +#define AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A +#define AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 +#define AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 +#define AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 +#define AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_SLEEPCTL +// +//***************************************************************************** +// Field: [0] IO_PAD_SLEEP_DIS +// +// Controls the I/O pad sleep mode. The boot code will set this bitfield +// automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is +// set). +// +// 0: I/O pad sleep mode is enabled, meaning all outputs and pad configurations +// are latched. Inputs are transparent if pad is configured as input before +// IO_PAD_SLEEP_DIS is set to 1 +// 1: I/O pad sleep mode is disabled +// +// Application software must reconfigure the state for all IO's before setting +// this bitfield upon waking up from a SHUTDOWN to avoid glitches on pins. +#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 +#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 +#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 +#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_JTAGCFG +// +//***************************************************************************** +// Field: [8] JTAG_PD_FORCE_ON +// +// Controls JTAG Power domain power state: +// +// 0: Controlled exclusively by debug subsystem. (JTAG Power domain will be +// powered off unless a debugger is attached) +// 1: JTAG Power Domain is forced on, independent of debug subsystem. +// +// Note: The reset value causes JTAG Power domain to be powered on by default. +// Software must clear this bit to turn off the JTAG Power domain +#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 +#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 +#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 +#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_S 8 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_JTAGUSERCODE +// +//***************************************************************************** +// Field: [31:0] USER_CODE +// +// 32-bit JTAG USERCODE register feeding main JTAG TAP +// Note: This field can be locked by LOCKCFG.LOCK +#define AON_PMCTL_JTAGUSERCODE_USER_CODE_W 32 +#define AON_PMCTL_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF +#define AON_PMCTL_JTAGUSERCODE_USER_CODE_S 0 + + +#endif // __AON_PMCTL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h new file mode 100644 index 0000000..6644cf4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h @@ -0,0 +1,546 @@ +/****************************************************************************** +* Filename: hw_aon_rtc_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_RTC_H__ +#define __HW_AON_RTC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_RTC component +// +//***************************************************************************** +// Control +#define AON_RTC_O_CTL 0x00000000 + +// Event Flags, RTC Status +#define AON_RTC_O_EVFLAGS 0x00000004 + +// Second Counter Value, Integer Part +#define AON_RTC_O_SEC 0x00000008 + +// Second Counter Value, Fractional Part +#define AON_RTC_O_SUBSEC 0x0000000C + +// Subseconds Increment +#define AON_RTC_O_SUBSECINC 0x00000010 + +// Channel Configuration +#define AON_RTC_O_CHCTL 0x00000014 + +// Channel 0 Compare Value +#define AON_RTC_O_CH0CMP 0x00000018 + +// Channel 1 Compare Value +#define AON_RTC_O_CH1CMP 0x0000001C + +// Channel 2 Compare Value +#define AON_RTC_O_CH2CMP 0x00000020 + +// Channel 2 Compare Value Auto-increment +#define AON_RTC_O_CH2CMPINC 0x00000024 + +// Channel 1 Capture Value +#define AON_RTC_O_CH1CAPT 0x00000028 + +// AON Synchronization +#define AON_RTC_O_SYNC 0x0000002C + +// Current Counter Value +#define AON_RTC_O_TIME 0x00000030 + +// Synchronization to SCLK_LF +#define AON_RTC_O_SYNCLF 0x00000034 + +//***************************************************************************** +// +// Register: AON_RTC_O_CTL +// +//***************************************************************************** +// Field: [18:16] COMB_EV_MASK +// +// Eventmask selecting which delayed events that form the combined event. +// ENUMs: +// CH2 Use Channel 2 delayed event in combined event +// CH1 Use Channel 1 delayed event in combined event +// CH0 Use Channel 0 delayed event in combined event +// NONE No event is selected for combined event. +#define AON_RTC_CTL_COMB_EV_MASK_W 3 +#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 +#define AON_RTC_CTL_COMB_EV_MASK_S 16 +#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 +#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 +#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 +#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 + +// Field: [11:8] EV_DELAY +// +// Number of SCLK_LF clock cycles waited before generating delayed events. +// (Common setting for all RTC cannels) the delayed event is delayed +// ENUMs: +// D144 Delay by 144 clock cycles +// D128 Delay by 128 clock cycles +// D112 Delay by 112 clock cycles +// D96 Delay by 96 clock cycles +// D80 Delay by 80 clock cycles +// D64 Delay by 64 clock cycles +// D48 Delay by 48 clock cycles +// D32 Delay by 32 clock cycles +// D16 Delay by 16 clock cycles +// D8 Delay by 8 clock cycles +// D4 Delay by 4 clock cycles +// D2 Delay by 2 clock cycles +// D1 Delay by 1 clock cycles +// D0 No delay on delayed event +#define AON_RTC_CTL_EV_DELAY_W 4 +#define AON_RTC_CTL_EV_DELAY_M 0x00000F00 +#define AON_RTC_CTL_EV_DELAY_S 8 +#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 +#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 +#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 +#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 +#define AON_RTC_CTL_EV_DELAY_D80 0x00000900 +#define AON_RTC_CTL_EV_DELAY_D64 0x00000800 +#define AON_RTC_CTL_EV_DELAY_D48 0x00000700 +#define AON_RTC_CTL_EV_DELAY_D32 0x00000600 +#define AON_RTC_CTL_EV_DELAY_D16 0x00000500 +#define AON_RTC_CTL_EV_DELAY_D8 0x00000400 +#define AON_RTC_CTL_EV_DELAY_D4 0x00000300 +#define AON_RTC_CTL_EV_DELAY_D2 0x00000200 +#define AON_RTC_CTL_EV_DELAY_D1 0x00000100 +#define AON_RTC_CTL_EV_DELAY_D0 0x00000000 + +// Field: [7] RESET +// +// RTC Counter reset. +// +// Writing 1 to this bit will reset the RTC counter. +// +// This bit is cleared when reset takes effect +#define AON_RTC_CTL_RESET 0x00000080 +#define AON_RTC_CTL_RESET_BITN 7 +#define AON_RTC_CTL_RESET_M 0x00000080 +#define AON_RTC_CTL_RESET_S 7 + +// Field: [2] RTC_4KHZ_EN +// +// RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 +// which is used by AUX timer. +// +// 0: RTC_4KHZ signal is forced to 0 +// 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) +#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 +#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_S 2 + +// Field: [1] RTC_UPD_EN +// +// RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is +// SCLK_LF divided by 2 +// +// 0: RTC_UPD signal is forced to 0 +// 1: RTC_UPD signal is toggling @16 kHz +#define AON_RTC_CTL_RTC_UPD_EN 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_BITN 1 +#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_S 1 + +// Field: [0] EN +// +// Enable RTC counter +// +// 0: Halted (frozen) +// 1: Running +#define AON_RTC_CTL_EN 0x00000001 +#define AON_RTC_CTL_EN_BITN 0 +#define AON_RTC_CTL_EN_M 0x00000001 +#define AON_RTC_CTL_EN_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_EVFLAGS +// +//***************************************************************************** +// Field: [16] CH2 +// +// Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or +// passes the CH2CMP value. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH2CMP provided that the channel is enabled and the new value matches any +// time between next RTC value and 1 second in the past +// +// Writing 1 clears this flag. +// +// AUX_SCE can read the flag through AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and clear it +// using AUX_SYSIF:RTCEVCLR.RTC_CH2_EV_CLR. +#define AON_RTC_EVFLAGS_CH2 0x00010000 +#define AON_RTC_EVFLAGS_CH2_BITN 16 +#define AON_RTC_EVFLAGS_CH2_M 0x00010000 +#define AON_RTC_EVFLAGS_CH2_S 16 + +// Field: [8] CH1 +// +// Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following: +// - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP +// value. +// - CHCTL.CH1_CAPT_EN = 1 and capture occurs. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH1CMP provided that the channel is enabled, in compare mode and the new +// value matches any time between next RTC value and 1 second in the past. +// +// Writing 1 clears this flag. +#define AON_RTC_EVFLAGS_CH1 0x00000100 +#define AON_RTC_EVFLAGS_CH1_BITN 8 +#define AON_RTC_EVFLAGS_CH1_M 0x00000100 +#define AON_RTC_EVFLAGS_CH1_S 8 + +// Field: [0] CH0 +// +// Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or +// passes the CH0CMP value. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH0CMP provided that the channels is enabled and the new value matches any +// time between next RTC value and 1 second in the past. +// +// Writing 1 clears this flag. +#define AON_RTC_EVFLAGS_CH0 0x00000001 +#define AON_RTC_EVFLAGS_CH0_BITN 0 +#define AON_RTC_EVFLAGS_CH0_M 0x00000001 +#define AON_RTC_EVFLAGS_CH0_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SEC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// Unsigned integer representing Real Time Clock in seconds. +// +// When reading this register the content of SUBSEC.VALUE is simultaneously +// latched. A consistent reading of the combined Real Time Clock can be +// obtained by first reading this register, then reading SUBSEC register. +#define AON_RTC_SEC_VALUE_W 32 +#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SEC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SUBSEC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// Unsigned integer representing Real Time Clock in fractions of a second +// (VALUE/2^32 seconds) at the time when SEC register was read. +// +// Examples : +// - 0x0000_0000 = 0.0 sec +// - 0x4000_0000 = 0.25 sec +// - 0x8000_0000 = 0.5 sec +// - 0xC000_0000 = 0.75 sec +#define AON_RTC_SUBSEC_VALUE_W 32 +#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SUBSEC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SUBSECINC +// +//***************************************************************************** +// Field: [23:0] VALUEINC +// +// This value compensates for a SCLK_LF clock which has an offset from 32768 +// Hz. +// +// The compensation value can be found as 2^38 / freq, where freq is SCLK_LF +// clock frequency in Hertz +// +// This value is added to SUBSEC.VALUE on every cycle, and carry of this is +// added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with +// SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a +// hidden 6-bit register that generates a carry into the above mentioned +// addition on overflow. +// The default value corresponds to incrementing by precisely 1/32768 of a +// second. +// +// NOTE: This register is read only. Modification of the register value must be +// done using registers AUX_SYSIF:RTCSUBSECINC0 , AUX_SYSIF:RTCSUBSECINC1 and +// AUX_SYSIF:RTCSUBSECINCCTL +#define AON_RTC_SUBSECINC_VALUEINC_W 24 +#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF +#define AON_RTC_SUBSECINC_VALUEINC_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CHCTL +// +//***************************************************************************** +// Field: [18] CH2_CONT_EN +// +// Set to enable continuous operation of Channel 2 +#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 +#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_S 18 + +// Field: [16] CH2_EN +// +// RTC Channel 2 Enable +// +// 0: Disable RTC Channel 2 +// 1: Enable RTC Channel 2 +#define AON_RTC_CHCTL_CH2_EN 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_BITN 16 +#define AON_RTC_CHCTL_CH2_EN_M 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_S 16 + +// Field: [9] CH1_CAPT_EN +// +// Set Channel 1 mode +// +// 0: Compare mode (default) +// 1: Capture mode +#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 +#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 + +// Field: [8] CH1_EN +// +// RTC Channel 1 Enable +// +// 0: Disable RTC Channel 1 +// 1: Enable RTC Channel 1 +#define AON_RTC_CHCTL_CH1_EN 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_BITN 8 +#define AON_RTC_CHCTL_CH1_EN_M 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_S 8 + +// Field: [0] CH0_EN +// +// RTC Channel 0 Enable +// +// 0: Disable RTC Channel 0 +// 1: Enable RTC Channel 0 +#define AON_RTC_CHCTL_CH0_EN 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_BITN 0 +#define AON_RTC_CHCTL_CH0_EN_M 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH0CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 0 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to one SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH0CMP_VALUE_W 32 +#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH0CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH1CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 1 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to one SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH1CMP_VALUE_W 32 +#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH1CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH2CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 2 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to one SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH2CMP_VALUE_W 32 +#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH2CMPINC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every +// channel 2 compare event. +#define AON_RTC_CH2CMPINC_VALUE_W 32 +#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMPINC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH1CAPT +// +//***************************************************************************** +// Field: [31:16] SEC +// +// Value of SEC.VALUE bits 15:0 at capture time. +#define AON_RTC_CH1CAPT_SEC_W 16 +#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 +#define AON_RTC_CH1CAPT_SEC_S 16 + +// Field: [15:0] SUBSEC +// +// Value of SUBSEC.VALUE bits 31:16 at capture time. +#define AON_RTC_CH1CAPT_SUBSEC_W 16 +#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF +#define AON_RTC_CH1CAPT_SUBSEC_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SYNC +// +//***************************************************************************** +// Field: [0] WBUSY +// +// This register will always return 0,- however it will not return the value +// until there are no outstanding write requests between MCU and AON +// +// Note: Writing to this register prior to reading will force a wait until next +// SCLK_MF edge. This is recommended for syncing read registers from AON when +// waking up from sleep +// Failure to do so may result in reading AON values from prior to going to +// sleep +#define AON_RTC_SYNC_WBUSY 0x00000001 +#define AON_RTC_SYNC_WBUSY_BITN 0 +#define AON_RTC_SYNC_WBUSY_M 0x00000001 +#define AON_RTC_SYNC_WBUSY_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_TIME +// +//***************************************************************************** +// Field: [31:16] SEC_L +// +// Returns the lower halfword of SEC register. +#define AON_RTC_TIME_SEC_L_W 16 +#define AON_RTC_TIME_SEC_L_M 0xFFFF0000 +#define AON_RTC_TIME_SEC_L_S 16 + +// Field: [15:0] SUBSEC_H +// +// Returns the upper halfword of SUBSEC register. +#define AON_RTC_TIME_SUBSEC_H_W 16 +#define AON_RTC_TIME_SUBSEC_H_M 0x0000FFFF +#define AON_RTC_TIME_SUBSEC_H_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SYNCLF +// +//***************************************************************************** +// Field: [0] PHASE +// +// This bit will always return the SCLK_LF phase. The return will delayed until +// a positive or negative edge of SCLK_LF is seen. +// 0: Falling edge of SCLK_LF +// 1: Rising edge of SCLK_LF +#define AON_RTC_SYNCLF_PHASE 0x00000001 +#define AON_RTC_SYNCLF_PHASE_BITN 0 +#define AON_RTC_SYNCLF_PHASE_M 0x00000001 +#define AON_RTC_SYNCLF_PHASE_S 0 + + +#endif // __AON_RTC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h new file mode 100644 index 0000000..29d8cf9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h @@ -0,0 +1,1030 @@ +/****************************************************************************** +* Filename: hw_aux_aiodio_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_AIODIO_H__ +#define __HW_AUX_AIODIO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_AIODIO component +// +//***************************************************************************** +// Input Output Mode +#define AUX_AIODIO_O_IOMODE 0x00000000 + +// General Purpose Input Output Digital Input Enable +#define AUX_AIODIO_O_GPIODIE 0x00000004 + +// Input Output Peripheral Output Enable +#define AUX_AIODIO_O_IOPOE 0x00000008 + +// General Purpose Input Output Data Out +#define AUX_AIODIO_O_GPIODOUT 0x0000000C + +// General Purpose Input Output Data In +#define AUX_AIODIO_O_GPIODIN 0x00000010 + +// General Purpose Input Output Data Out Set +#define AUX_AIODIO_O_GPIODOUTSET 0x00000014 + +// General Purpose Input Output Data Out Clear +#define AUX_AIODIO_O_GPIODOUTCLR 0x00000018 + +// General Purpose Input Output Data Out Toggle +#define AUX_AIODIO_O_GPIODOUTTGL 0x0000001C + +// Input Output 0 Peripheral Select +#define AUX_AIODIO_O_IO0PSEL 0x00000020 + +// Input Output 1 Peripheral Select +#define AUX_AIODIO_O_IO1PSEL 0x00000024 + +// Input Output 2 Peripheral Select +#define AUX_AIODIO_O_IO2PSEL 0x00000028 + +// Input Output 3 Peripheral Select +#define AUX_AIODIO_O_IO3PSEL 0x0000002C + +// Input Output 4 Peripheral Select +#define AUX_AIODIO_O_IO4PSEL 0x00000030 + +// Input Output 5 Peripheral Select +#define AUX_AIODIO_O_IO5PSEL 0x00000034 + +// Input Output 6 Peripheral Select +#define AUX_AIODIO_O_IO6PSEL 0x00000038 + +// Input Output 7 Peripheral Select +#define AUX_AIODIO_O_IO7PSEL 0x0000003C + +// Input Output Mode Low +#define AUX_AIODIO_O_IOMODEL 0x00000040 + +// Input Output Mode High +#define AUX_AIODIO_O_IOMODEH 0x00000044 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IOMODE +// +//***************************************************************************** +// Field: [15:14] IO7 +// +// Selects mode for AUXIO[8i+7]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 7 is 0: +// - If GPIODOUT bit 7 is 0: +// AUXIO[8i+7] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 7 is 1: +// AUXIO[8i+7] is driven high. +// +// When IOPOE bit 7 is 1: +// - If signal selected by +// IO7PSEL.SRC is 0: AUXIO[8i+7] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO7PSEL.SRC is 1: AUXIO[8i+7] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 7 is 0: +// - If GPIODOUT bit 7 is 0: +// AUXIO[8i+7] is driven low. +// - If GPIODOUT bit 7 is 1: +// AUXIO[8i+7] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 7 is 1: +// - If signal selected by +// IO7PSEL.SRC is 0: AUXIO[8i+7] is driven low. +// - If signal selected by +// IO7PSEL.SRC is 1: AUXIO[8i+7] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 7 is 0: +// AUXIO[8i+7] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 7 is 1: +// AUXIO[8i+7] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 7 is 0: +// GPIODOUT bit 7 drives AUXIO[8i+7]. +// +// When IOPOE bit 7 is 1: +// The signal selected by IO7PSEL.SRC drives +// AUXIO[8i+7]. +#define AUX_AIODIO_IOMODE_IO7_W 2 +#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_S 14 +#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 +#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 +#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 + +// Field: [13:12] IO6 +// +// Selects mode for AUXIO[8i+6]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 6 is 0: +// - If GPIODOUT bit 6 is 0: +// AUXIO[8i+6] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 6 is 1: +// AUXIO[8i+6] is driven high. +// +// When IOPOE bit 6 is 1: +// - If signal selected by +// IO6PSEL.SRC is 0: AUXIO[8i+6] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO6PSEL.SRC is 1: AUXIO[8i+6] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 6 is 0: +// - If GPIODOUT bit 6 is 0: +// AUXIO[8i+6] is driven low. +// - If GPIODOUT bit 6 is 1: +// AUXIO[8i+6] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 6 is 1: +// - If signal selected by +// IO6PSEL.SRC is 0: AUXIO[8i+6] is driven low. +// - If signal selected by +// IO6PSEL.SRC is 1: AUXIO[8i+6] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 6 is 0: +// AUXIO[8i+6] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 6 is 1: +// AUXIO[8i+6] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 6 is 0: +// GPIODOUT bit 6 drives AUXIO[8i+6]. +// +// When IOPOE bit 6 is 1: +// The signal selected by IO6PSEL.SRC drives +// AUXIO[8i+6]. +#define AUX_AIODIO_IOMODE_IO6_W 2 +#define AUX_AIODIO_IOMODE_IO6_M 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_S 12 +#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 +#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 +#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 + +// Field: [11:10] IO5 +// +// Selects mode for AUXIO[8i+5]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 5 is 0: +// - If GPIODOUT bit 5 is 0: +// AUXIO[8i+5] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 5 is 1: +// AUXIO[8i+5] is driven high. +// +// When IOPOE bit 5 is 1: +// - If signal selected by +// IO5PSEL.SRC is 0: AUXIO[8i+5] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO5PSEL.SRC is 1: AUXIO[8i+5] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 5 is 0: +// - If GPIODOUT bit 5 is 0: +// AUXIO[8i+5] is driven low. +// - If GPIODOUT bit 5 is 1: +// AUXIO[8i+5] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 5 is 1: +// - If signal selected by +// IO5PSEL.SRC is 0: AUXIO[8i+5] is driven low. +// - If signal selected by +// IO5PSEL.SRC is 1: AUXIO[8i+5] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 5 is 0: +// AUXIO[8i+5] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 5 is 1: +// AUXIO[8i+5] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 5 is 0: +// GPIODOUT bit 5 drives AUXIO[8i+5]. +// +// When IOPOE bit 5 is 1: +// The signal selected by IO5PSEL.SRC drives +// AUXIO[8i+5]. +#define AUX_AIODIO_IOMODE_IO5_W 2 +#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_S 10 +#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 +#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 +#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 + +// Field: [9:8] IO4 +// +// Selects mode for AUXIO[8i+4]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 4 is 0: +// - If GPIODOUT bit 4 is 0: +// AUXIO[8i+4] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 4 is 1: +// AUXIO[8i+4] is driven high. +// +// When IOPOE bit 4 is 1: +// - If signal selected by +// IO4PSEL.SRC is 0: AUXIO[8i+4] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO4PSEL.SRC is 1: AUXIO[8i+4] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 4 is 0: +// - If GPIODOUT bit 4 is 0: +// AUXIO[8i+4] is driven low. +// - If GPIODOUT bit 4 is 1: +// AUXIO[8i+4] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 4 is 1: +// - If signal selected by +// IO4PSEL.SRC is 0: AUXIO[8i+4] is driven low. +// - If signal selected by +// IO4PSEL.SRC is 1: AUXIO[8i+4] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 4 is 0: +// AUXIO[8i+4] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 4 is 1: +// AUXIO[8i+4] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 4 is 0: +// GPIODOUT bit 4 drives AUXIO[8i+4]. +// +// When IOPOE bit 4 is 1: +// The signal selected by IO4PSEL.SRC drives +// AUXIO[8i+4]. +#define AUX_AIODIO_IOMODE_IO4_W 2 +#define AUX_AIODIO_IOMODE_IO4_M 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_S 8 +#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 +#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 +#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 + +// Field: [7:6] IO3 +// +// Selects mode for AUXIO[8i+3]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 3 is 0: +// - If GPIODOUT bit 3 is 0: +// AUXIO[8i+3] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 3 is 1: +// AUXIO[8i+3] is driven high. +// +// When IOPOE bit 3 is 1: +// - If signal selected by +// IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 3 is 0: +// - If GPIODOUT bit 3 is 0: +// AUXIO[8i+3] is driven low. +// - If GPIODOUT bit 3 is 1: +// AUXIO[8i+3] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 3 is 1: +// - If signal selected by +// IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low. +// - If signal selected by +// IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 3 is 0: +// AUXIO[8i+3] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 3 is 1: +// AUXIO[8i+3] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 3 is 0: +// GPIODOUT bit 3 drives AUXIO[8i+3]. +// +// When IOPOE bit 3 is 1: +// The signal selected by IO3PSEL.SRC drives +// AUXIO[8i+3]. +#define AUX_AIODIO_IOMODE_IO3_W 2 +#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_S 6 +#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 +#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 +#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 + +// Field: [5:4] IO2 +// +// Select mode for AUXIO[8i+2]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 2 is 0: +// - If GPIODOUT bit 2 is 0: +// AUXIO[8i+2] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 2 is 1: +// AUXIO[8i+2] is driven high. +// +// When IOPOE bit 2 is 1: +// - If signal selected by +// IO2PSEL.SRC is 0: AUXIO[8i+2] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO2PSEL.SRC is 1: AUXIO[8i+2] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 2 is 0: +// - If GPIODOUT bit 2 is 0: +// AUXIO[8i+2] is driven low. +// - If GPIODOUT bit 2 is 1: +// AUXIO[8i+2] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 2 is 1: +// - If signal selected by +// IO2PSEL.SRC is 0: AUXIO[8i+2] is driven low. +// - If signal selected by +// IO2PSEL.SRC is 1: AUXIO[8i+2] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 2 is 0: +// AUXIO[8i+2] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 2 is 1: +// AUXIO[8i+2] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 2 is 0: +// GPIODOUT bit 2 drives AUXIO[8i+2]. +// +// When IOPOE bit 2 is 1: +// The signal selected by IO2PSEL.SRC drives +// AUXIO[8i+2]. +#define AUX_AIODIO_IOMODE_IO2_W 2 +#define AUX_AIODIO_IOMODE_IO2_M 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_S 4 +#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 +#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 +#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 + +// Field: [3:2] IO1 +// +// Select mode for AUXIO[8i+1]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 1 is 0: +// - If GPIODOUT bit 1 is 0: +// AUXIO[8i+1] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 1 is 1: +// AUXIO[8i+1] is driven high. +// +// When IOPOE bit 1 is 1: +// - If signal selected by +// IO1PSEL.SRC is 0: AUXIO[8i+1] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO1PSEL.SRC is 1: AUXIO[8i+1] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 1 is 0: +// - If GPIODOUT bit 1 is 0: +// AUXIO[8i+1] is driven low. +// - If GPIODOUT bit 1 is 1: +// AUXIO[8i+1] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 1 is 1: +// - If signal selected by +// IO1PSEL.SRC is 0: AUXIO[8i+1] is driven low. +// - If signal selected by +// IO1PSEL.SRC is 1: AUXIO[8i+1] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 1 is 0: +// AUXIO[8i+1] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 1 is 1: +// AUXIO[8i+1] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 1 is 0: +// GPIODOUT bit 1 drives AUXIO[8i+1]. +// +// When IOPOE bit 1 is 1: +// The signal selected by IO1PSEL.SRC drives +// AUXIO[8i+1]. +#define AUX_AIODIO_IOMODE_IO1_W 2 +#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_S 2 +#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 +#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 +#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 + +// Field: [1:0] IO0 +// +// Select mode for AUXIO[8i+0]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 0 is 0: +// - If GPIODOUT bit 0 is 0: +// AUXIO[8i+0] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 0 is 1: +// AUXIO[8i+0] is driven high. +// +// When IOPOE bit 0 is 1: +// - If signal selected by +// IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 0 is 0: +// - If GPIODOUT bit 0 is 0: +// AUXIO[8i+0] is driven low. +// - If GPIODOUT bit 0 is 1: +// AUXIO[8i+0] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 0 is 1: +// - If signal selected by +// IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low. +// - If signal selected by +// IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 0 is 0: +// AUXIO[8i+0] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 0 is 1: +// AUXIO[8i+0] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 0 is 0: +// GPIODOUT bit 0 drives AUXIO[8i+0]. +// +// When IOPOE bit 0 is 1: +// The signal selected by IO0PSEL.SRC drives +// AUXIO[8i+0]. +#define AUX_AIODIO_IOMODE_IO0_W 2 +#define AUX_AIODIO_IOMODE_IO0_M 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_S 0 +#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 +#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 +#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODIE +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to enable digital input buffer for +// AUXIO[8i+n]. +// Write 0 to bit index n in this bit vector to disable digital input buffer +// for AUXIO[8i+n]. +// +// You must enable the digital input buffer for AUXIO[8i+n] to read the pin +// value in GPIODIN. +// You must disable the digital input buffer for analog input or pins that +// float to avoid current leakage. +#define AUX_AIODIO_GPIODIE_IO7_0_W 8 +#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIE_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IOPOE +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be +// driven from source given in [IOnPSEL.*]. +// Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be +// driven from bit n in GPIODOUT. +#define AUX_AIODIO_IOPOE_IO7_0_W 8 +#define AUX_AIODIO_IOPOE_IO7_0_M 0x000000FF +#define AUX_AIODIO_IOPOE_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUT +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. +// Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. +// +// You must clear bit n in IOPOE to connect bit n in this bit vector to +// AUXIO[8i+n]. +#define AUX_AIODIO_GPIODOUT_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUT_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODIN +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit +// n is set. Otherwise, bit n is read as 0. +#define AUX_AIODIO_GPIODIN_IO7_0_W 8 +#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIN_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTSET +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to set GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTCLR +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTTGL +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO0PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO0PSEL_SRC_W 3 +#define AUX_AIODIO_IO0PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO0PSEL_SRC_S 0 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO1PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO1PSEL_SRC_W 3 +#define AUX_AIODIO_IO1PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO1PSEL_SRC_S 0 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO2PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO2PSEL_SRC_W 3 +#define AUX_AIODIO_IO2PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO2PSEL_SRC_S 0 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO3PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO3PSEL_SRC_W 3 +#define AUX_AIODIO_IO3PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO3PSEL_SRC_S 0 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO4PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO4PSEL_SRC_W 3 +#define AUX_AIODIO_IO4PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO4PSEL_SRC_S 0 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO5PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO5PSEL_SRC_W 3 +#define AUX_AIODIO_IO5PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO5PSEL_SRC_S 0 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO6PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO6PSEL_SRC_W 3 +#define AUX_AIODIO_IO6PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO6PSEL_SRC_S 0 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO7PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO7PSEL_SRC_W 3 +#define AUX_AIODIO_IO7PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO7PSEL_SRC_S 0 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IOMODEL +// +//***************************************************************************** +// Field: [7:6] IO3 +// +// See IOMODE.IO3. +#define AUX_AIODIO_IOMODEL_IO3_W 2 +#define AUX_AIODIO_IOMODEL_IO3_M 0x000000C0 +#define AUX_AIODIO_IOMODEL_IO3_S 6 + +// Field: [5:4] IO2 +// +// See IOMODE.IO2. +#define AUX_AIODIO_IOMODEL_IO2_W 2 +#define AUX_AIODIO_IOMODEL_IO2_M 0x00000030 +#define AUX_AIODIO_IOMODEL_IO2_S 4 + +// Field: [3:2] IO1 +// +// See IOMODE.IO1. +#define AUX_AIODIO_IOMODEL_IO1_W 2 +#define AUX_AIODIO_IOMODEL_IO1_M 0x0000000C +#define AUX_AIODIO_IOMODEL_IO1_S 2 + +// Field: [1:0] IO0 +// +// See IOMODE.IO0. +#define AUX_AIODIO_IOMODEL_IO0_W 2 +#define AUX_AIODIO_IOMODEL_IO0_M 0x00000003 +#define AUX_AIODIO_IOMODEL_IO0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IOMODEH +// +//***************************************************************************** +// Field: [7:6] IO7 +// +// See IOMODE.IO7. +#define AUX_AIODIO_IOMODEH_IO7_W 2 +#define AUX_AIODIO_IOMODEH_IO7_M 0x000000C0 +#define AUX_AIODIO_IOMODEH_IO7_S 6 + +// Field: [5:4] IO6 +// +// See IOMODE.IO6. +#define AUX_AIODIO_IOMODEH_IO6_W 2 +#define AUX_AIODIO_IOMODEH_IO6_M 0x00000030 +#define AUX_AIODIO_IOMODEH_IO6_S 4 + +// Field: [3:2] IO5 +// +// See IOMODE.IO5. +#define AUX_AIODIO_IOMODEH_IO5_W 2 +#define AUX_AIODIO_IOMODEH_IO5_M 0x0000000C +#define AUX_AIODIO_IOMODEH_IO5_S 2 + +// Field: [1:0] IO4 +// +// See IOMODE.IO4. +#define AUX_AIODIO_IOMODEH_IO4_W 2 +#define AUX_AIODIO_IOMODEH_IO4_M 0x00000003 +#define AUX_AIODIO_IOMODEH_IO4_S 0 + + +#endif // __AUX_AIODIO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h new file mode 100644 index 0000000..f9777f8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h @@ -0,0 +1,633 @@ +/****************************************************************************** +* Filename: hw_aux_anaif_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_ANAIF_H__ +#define __HW_AUX_ANAIF_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_ANAIF component +// +//***************************************************************************** +// ADC Control +#define AUX_ANAIF_O_ADCCTL 0x00000010 + +// ADC FIFO Status +#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 + +// ADC FIFO +#define AUX_ANAIF_O_ADCFIFO 0x00000018 + +// ADC Trigger +#define AUX_ANAIF_O_ADCTRIG 0x0000001C + +// Current Source Control +#define AUX_ANAIF_O_ISRCCTL 0x00000020 + +// DAC Control +#define AUX_ANAIF_O_DACCTL 0x00000030 + +// Low Power Mode Bias Control +#define AUX_ANAIF_O_LPMBIASCTL 0x00000034 + +// DAC Sample Control +#define AUX_ANAIF_O_DACSMPLCTL 0x00000038 + +// DAC Sample Configuration 0 +#define AUX_ANAIF_O_DACSMPLCFG0 0x0000003C + +// DAC Sample Configuration 1 +#define AUX_ANAIF_O_DACSMPLCFG1 0x00000040 + +// DAC Value +#define AUX_ANAIF_O_DACVALUE 0x00000044 + +// DAC Status +#define AUX_ANAIF_O_DACSTAT 0x00000048 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCCTL +// +//***************************************************************************** +// Field: [14] START_POL +// +// Select active polarity for START_SRC event. +// ENUMs: +// FALL Set ADC trigger on falling edge of event source. +// RISE Set ADC trigger on rising edge of event source. +#define AUX_ANAIF_ADCCTL_START_POL 0x00004000 +#define AUX_ANAIF_ADCCTL_START_POL_BITN 14 +#define AUX_ANAIF_ADCCTL_START_POL_M 0x00004000 +#define AUX_ANAIF_ADCCTL_START_POL_S 14 +#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00004000 +#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 + +// Field: [13:8] START_SRC +// +// Select ADC trigger event source from the asynchronous AUX event bus. +// +// Set START_SRC to NO_EVENT if you want to trigger the ADC manually through +// ADCTRIG.START. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_ANAIF_ADCCTL_START_SRC_W 6 +#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00003F00 +#define AUX_ANAIF_ADCCTL_START_SRC_S 8 +#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT 0x00003F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_ISRC_RESET_N 0x00003800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TDC_DONE 0x00003700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER0_EV 0x00003600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER1_EV 0x00003500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_PULSE 0x00003400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV3 0x00003300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV2 0x00003200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV1 0x00003100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV0 0x00003000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00002F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00002E00 +#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00002B00 +#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00002A00 +#define AUX_ANAIF_ADCCTL_START_SRC_VDDR_RECHARGE 0x00002900 +#define AUX_ANAIF_ADCCTL_START_SRC_MCU_ACTIVE 0x00002800 +#define AUX_ANAIF_ADCCTL_START_SRC_PWR_DWN 0x00002700 +#define AUX_ANAIF_ADCCTL_START_SRC_SCLK_LF 0x00002600 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_TEMP_UPD 0x00002500 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_BAT_UPD 0x00002400 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_4KHZ 0x00002300 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2_DLY 0x00002200 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2 0x00002100 +#define AUX_ANAIF_ADCCTL_START_SRC_MANUAL_EV 0x00002000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO31 0x00001F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO30 0x00001E00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO29 0x00001D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO28 0x00001C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO27 0x00001B00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO26 0x00001A00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO25 0x00001900 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO24 0x00001800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO23 0x00001700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO22 0x00001600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO21 0x00001500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO20 0x00001400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO19 0x00001300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO18 0x00001200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO17 0x00001100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO16 0x00001000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00000F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00000E00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00000D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00000C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00000B00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00000A00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00000900 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00000800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00000700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00000600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00000500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00000400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00000300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000000 + +// Field: [1:0] CMD +// +// ADC interface command. +// +// Non-enumerated values are not supported. The written value is returned when +// read. +// ENUMs: +// FLUSH Flush ADC FIFO. +// +// You must set CMD to EN or +// DIS after flush. +// +// System CPU must wait two +// clock cycles before it sets CMD to EN or DIS. +// EN Enable ADC interface. +// DIS Disable ADC interface. +#define AUX_ANAIF_ADCCTL_CMD_W 2 +#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_S 0 +#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 +#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCFIFOSTAT +// +//***************************************************************************** +// Field: [4] OVERFLOW +// +// FIFO overflow flag. +// +// 0: FIFO has not overflowed. +// 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. +// +// When the flag is set, the ADC FIFO write pointer is static. It is not +// possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 + +// Field: [3] UNDERFLOW +// +// FIFO underflow flag. +// +// 0: FIFO has not underflowed. +// 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. +// +// When the flag is set, the ADC FIFO read pointer is static. Read returns the +// previous sample that was read. Flush FIFO to clear the flag. +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 + +// Field: [2] FULL +// +// FIFO full flag. +// +// 0: FIFO is not full, there is less than 4 samples in the FIFO. +// 1: FIFO is full, there are 4 samples in the FIFO. +// +// When the flag is set, it is not possible to add more samples to the ADC +// FIFO. An attempt to add samples sets the OVERFLOW flag. +#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 + +// Field: [1] ALMOST_FULL +// +// FIFO almost full flag. +// +// 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL +// flag is also asserted in the latter case. +// 1: There are 3 samples in the FIFO, there is room for one more sample. +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 + +// Field: [0] EMPTY +// +// FIFO empty flag. +// +// 0: FIFO contains one or more samples. +// 1: FIFO is empty. +// +// When the flag is set, read returns the previous sample that was read and +// sets the UNDERFLOW flag. +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCFIFO +// +//***************************************************************************** +// Field: [11:0] DATA +// +// FIFO data. +// +// Read: +// Get oldest ADC sample from FIFO. +// +// Write: +// Write dummy sample to FIFO. This is useful for code development when you do +// not have real ADC samples. +#define AUX_ANAIF_ADCFIFO_DATA_W 12 +#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF +#define AUX_ANAIF_ADCFIFO_DATA_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCTRIG +// +//***************************************************************************** +// Field: [0] START +// +// Manual ADC trigger. +// +// 0: No effect. +// 1: Single ADC trigger. +// +// To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to +// avoid conflict with event-driven ADC trigger. +#define AUX_ANAIF_ADCTRIG_START 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_BITN 0 +#define AUX_ANAIF_ADCTRIG_START_M 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ISRCCTL +// +//***************************************************************************** +// Field: [0] RESET_N +// +// ISRC reset control. +// +// 0: ISRC drives 0 uA. +// 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. +#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 +#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_DACCTL +// +//***************************************************************************** +// Field: [5] DAC_EN +// +// DAC module enable. +// +// 0: Disable DAC. +// 1: Enable DAC. +// +// The Sensor Controller must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ +// equals PDA. +// +// The System CPU must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA +// in Standby TI-RTOS power mode. The System CPU must set +// AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE to use the DAC in Active +// and Idle TI-RTOS power modes. +#define AUX_ANAIF_DACCTL_DAC_EN 0x00000020 +#define AUX_ANAIF_DACCTL_DAC_EN_BITN 5 +#define AUX_ANAIF_DACCTL_DAC_EN_M 0x00000020 +#define AUX_ANAIF_DACCTL_DAC_EN_S 5 + +// Field: [4] DAC_BUFFER_EN +// +// DAC buffer enable. +// +// DAC buffer reduces the time required to produce the programmed voltage at +// the expense of increased current consumption. +// +// 0: Disable DAC buffer. +// 1: Enable DAC buffer. +// +// Enable buffer when DAC_VOUT_SEL equals COMPA_IN. +// +// Do not enable the buffer when AUX_SYSIF:OPMODEREQ.REQ equals PDA or PDLP. +#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN 0x00000010 +#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_BITN 4 +#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_M 0x00000010 +#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_S 4 + +// Field: [3] DAC_PRECHARGE_EN +// +// DAC precharge enable. +// +// Only enable precharge when ADI_4_AUX:MUX2.DAC_VREF_SEL equals DCOUPL and +// VDDS is higher than 2.65 V. +// +// DAC output voltage range: +// +// 0: 0 V to 1.28 V. +// 1: 1.28 V to 2.56 V. +// +// Otherwise, see ADI_4_AUX:MUX2.DAC_VREF_SEL for DAC output voltage range. +// +// Enable precharge 1 us before you enable the DAC and the buffer. +#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN 0x00000008 +#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_BITN 3 +#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_M 0x00000008 +#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_S 3 + +// Field: [2:0] DAC_VOUT_SEL +// +// DAC output connection. +// +// An analog node must only have one driver. Other drivers for the following +// analog nodes are configured in [ANATOP_MMAP::ADI_4_AUX:*]. +// ENUMs: +// COMPA_IN Connect to COMPA_IN analog node. +// +// Required setting to drive +// external load selected in +// ADI_4_AUX:MUX1.COMPA_IN. +// COMPA_REF Connect to COMPA_REF analog node. +// +// It is not possible to +// drive external loads connected to COMPA_REF I/O +// mux with this setting. +// COMPB_REF Connect to COMPB_REF analog node. +// +// Required setting to use +// Comparator B. +// NC Connect to nothing +// +// It is recommended to use +// NC as intermediate step when you change +// DAC_VOUT_SEL. +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_W 3 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_M 0x00000007 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_S 0 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_IN 0x00000004 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_REF 0x00000002 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPB_REF 0x00000001 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_LPMBIASCTL +// +//***************************************************************************** +// Field: [0] EN +// +// Module enable. +// +// 0: Disable low power mode bias module. +// 1: Enable low power mode bias module. +// +// Set EN to 1 15 us before you enable the DAC or Comparator A. +#define AUX_ANAIF_LPMBIASCTL_EN 0x00000001 +#define AUX_ANAIF_LPMBIASCTL_EN_BITN 0 +#define AUX_ANAIF_LPMBIASCTL_EN_M 0x00000001 +#define AUX_ANAIF_LPMBIASCTL_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_DACSMPLCTL +// +//***************************************************************************** +// Field: [0] EN +// +// DAC sample clock enable. +// +// 0: Disable sample clock. The sample clock stops low and DACSTAT becomes 0 +// when the current sample clock period completes. +// 1: Enable DAC sample clock. DACSTAT must be 0 before you enable sample +// clock. +#define AUX_ANAIF_DACSMPLCTL_EN 0x00000001 +#define AUX_ANAIF_DACSMPLCTL_EN_BITN 0 +#define AUX_ANAIF_DACSMPLCTL_EN_M 0x00000001 +#define AUX_ANAIF_DACSMPLCTL_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_DACSMPLCFG0 +// +//***************************************************************************** +// Field: [5:0] CLKDIV +// +// Clock division. +// +// AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE divided by (CLKDIV + 1) determines the +// sample clock base frequency. +// +// 0: Divide by 1. +// 1: Divide by 2. +// ... +// 63: Divide by 64. +#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_W 6 +#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_M 0x0000003F +#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_DACSMPLCFG1 +// +//***************************************************************************** +// Field: [14] H_PER +// +// High time. +// +// The sample clock period is high for this many base periods. +// +// 0: 2 periods +// 1: 4 periods +#define AUX_ANAIF_DACSMPLCFG1_H_PER 0x00004000 +#define AUX_ANAIF_DACSMPLCFG1_H_PER_BITN 14 +#define AUX_ANAIF_DACSMPLCFG1_H_PER_M 0x00004000 +#define AUX_ANAIF_DACSMPLCFG1_H_PER_S 14 + +// Field: [13:12] L_PER +// +// Low time. +// +// The sample clock period is low for this many base periods. +// +// 0: 1 period +// 1: 2 periods +// 2: 3 periods +// 3: 4 periods +#define AUX_ANAIF_DACSMPLCFG1_L_PER_W 2 +#define AUX_ANAIF_DACSMPLCFG1_L_PER_M 0x00003000 +#define AUX_ANAIF_DACSMPLCFG1_L_PER_S 12 + +// Field: [11:8] SETUP_CNT +// +// Setup count. +// +// Number of active sample clock periods during the setup phase. +// +// 0: 1 sample clock period +// 1: 2 sample clock periods +// ... +// 15 : 16 sample clock periods +#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_W 4 +#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_M 0x00000F00 +#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_S 8 + +// Field: [7:0] HOLD_INTERVAL +// +// Hold interval. +// +// Number of inactive sample clock periods between each active sample clock +// period during hold phase. The sample clock is low when inactive. +// +// The range is 0 to 255. +#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_W 8 +#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_M 0x000000FF +#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_DACVALUE +// +//***************************************************************************** +// Field: [7:0] VALUE +// +// DAC value. +// +// Digital data word for the DAC. +// +// Only change VALUE when DACCTL.DAC_EN is 0. Then wait 1 us before you enable +// the DAC. +#define AUX_ANAIF_DACVALUE_VALUE_W 8 +#define AUX_ANAIF_DACVALUE_VALUE_M 0x000000FF +#define AUX_ANAIF_DACVALUE_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_DACSTAT +// +//***************************************************************************** +// Field: [1] SETUP_ACTIVE +// +// DAC setup phase status. +// +// 0: Sample clock is disabled or setup phase is complete. +// 1: Setup phase in progress. +#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE 0x00000002 +#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_BITN 1 +#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_M 0x00000002 +#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_S 1 + +// Field: [0] HOLD_ACTIVE +// +// DAC hold phase status. +// +// 0: Sample clock is disabled or DAC is not in hold phase. +// 1: Hold phase in progress. +#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE 0x00000001 +#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_BITN 0 +#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_M 0x00000001 +#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_S 0 + + +#endif // __AUX_ANAIF__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h new file mode 100644 index 0000000..3bf1344 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h @@ -0,0 +1,2355 @@ +/****************************************************************************** +* Filename: hw_aux_evctl_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_EVCTL_H__ +#define __HW_AUX_EVCTL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_EVCTL component +// +//***************************************************************************** +// Event Status 0 +#define AUX_EVCTL_O_EVSTAT0 0x00000000 + +// Event Status 1 +#define AUX_EVCTL_O_EVSTAT1 0x00000004 + +// Event Status 2 +#define AUX_EVCTL_O_EVSTAT2 0x00000008 + +// Event Status 3 +#define AUX_EVCTL_O_EVSTAT3 0x0000000C + +// Sensor Controller Engine Wait Event Configuration 0 +#define AUX_EVCTL_O_SCEWEVCFG0 0x00000010 + +// Sensor Controller Engine Wait Event Configuration 1 +#define AUX_EVCTL_O_SCEWEVCFG1 0x00000014 + +// Direct Memory Access Control +#define AUX_EVCTL_O_DMACTL 0x00000018 + +// Software Event Set +#define AUX_EVCTL_O_SWEVSET 0x00000020 + +// Events To AON Flags +#define AUX_EVCTL_O_EVTOAONFLAGS 0x00000024 + +// Events To AON Polarity +#define AUX_EVCTL_O_EVTOAONPOL 0x00000028 + +// Events To AON Clear +#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000002C + +// Events to MCU Flags +#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000030 + +// Event To MCU Polarity +#define AUX_EVCTL_O_EVTOMCUPOL 0x00000034 + +// Events To MCU Flags Clear +#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038 + +// Combined Event To MCU Mask +#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000003C + +// Event Observation Configuration +#define AUX_EVCTL_O_EVOBSCFG 0x00000040 + +// Programmable Delay +#define AUX_EVCTL_O_PROGDLY 0x00000044 + +// Manual +#define AUX_EVCTL_O_MANUAL 0x00000048 + +// Event Status 0 Low +#define AUX_EVCTL_O_EVSTAT0L 0x0000004C + +// Event Status 0 High +#define AUX_EVCTL_O_EVSTAT0H 0x00000050 + +// Event Status 1 Low +#define AUX_EVCTL_O_EVSTAT1L 0x00000054 + +// Event Status 1 High +#define AUX_EVCTL_O_EVSTAT1H 0x00000058 + +// Event Status 2 Low +#define AUX_EVCTL_O_EVSTAT2L 0x0000005C + +// Event Status 2 High +#define AUX_EVCTL_O_EVSTAT2H 0x00000060 + +// Event Status 3 Low +#define AUX_EVCTL_O_EVSTAT3L 0x00000064 + +// Event Status 3 High +#define AUX_EVCTL_O_EVSTAT3H 0x00000068 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT0 +// +//***************************************************************************** +// Field: [15] AUXIO15 +// +// AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT0_AUXIO15 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO15_BITN 15 +#define AUX_EVCTL_EVSTAT0_AUXIO15_M 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO15_S 15 + +// Field: [14] AUXIO14 +// +// AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT0_AUXIO14 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO14_BITN 14 +#define AUX_EVCTL_EVSTAT0_AUXIO14_M 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO14_S 14 + +// Field: [13] AUXIO13 +// +// AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT0_AUXIO13 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO13_BITN 13 +#define AUX_EVCTL_EVSTAT0_AUXIO13_M 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO13_S 13 + +// Field: [12] AUXIO12 +// +// AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT0_AUXIO12 0x00001000 +#define AUX_EVCTL_EVSTAT0_AUXIO12_BITN 12 +#define AUX_EVCTL_EVSTAT0_AUXIO12_M 0x00001000 +#define AUX_EVCTL_EVSTAT0_AUXIO12_S 12 + +// Field: [11] AUXIO11 +// +// AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT0_AUXIO11 0x00000800 +#define AUX_EVCTL_EVSTAT0_AUXIO11_BITN 11 +#define AUX_EVCTL_EVSTAT0_AUXIO11_M 0x00000800 +#define AUX_EVCTL_EVSTAT0_AUXIO11_S 11 + +// Field: [10] AUXIO10 +// +// AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT0_AUXIO10 0x00000400 +#define AUX_EVCTL_EVSTAT0_AUXIO10_BITN 10 +#define AUX_EVCTL_EVSTAT0_AUXIO10_M 0x00000400 +#define AUX_EVCTL_EVSTAT0_AUXIO10_S 10 + +// Field: [9] AUXIO9 +// +// AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT0_AUXIO9 0x00000200 +#define AUX_EVCTL_EVSTAT0_AUXIO9_BITN 9 +#define AUX_EVCTL_EVSTAT0_AUXIO9_M 0x00000200 +#define AUX_EVCTL_EVSTAT0_AUXIO9_S 9 + +// Field: [8] AUXIO8 +// +// AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT0_AUXIO8 0x00000100 +#define AUX_EVCTL_EVSTAT0_AUXIO8_BITN 8 +#define AUX_EVCTL_EVSTAT0_AUXIO8_M 0x00000100 +#define AUX_EVCTL_EVSTAT0_AUXIO8_S 8 + +// Field: [7] AUXIO7 +// +// AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT0_AUXIO7 0x00000080 +#define AUX_EVCTL_EVSTAT0_AUXIO7_BITN 7 +#define AUX_EVCTL_EVSTAT0_AUXIO7_M 0x00000080 +#define AUX_EVCTL_EVSTAT0_AUXIO7_S 7 + +// Field: [6] AUXIO6 +// +// AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT0_AUXIO6 0x00000040 +#define AUX_EVCTL_EVSTAT0_AUXIO6_BITN 6 +#define AUX_EVCTL_EVSTAT0_AUXIO6_M 0x00000040 +#define AUX_EVCTL_EVSTAT0_AUXIO6_S 6 + +// Field: [5] AUXIO5 +// +// AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT0_AUXIO5 0x00000020 +#define AUX_EVCTL_EVSTAT0_AUXIO5_BITN 5 +#define AUX_EVCTL_EVSTAT0_AUXIO5_M 0x00000020 +#define AUX_EVCTL_EVSTAT0_AUXIO5_S 5 + +// Field: [4] AUXIO4 +// +// AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT0_AUXIO4 0x00000010 +#define AUX_EVCTL_EVSTAT0_AUXIO4_BITN 4 +#define AUX_EVCTL_EVSTAT0_AUXIO4_M 0x00000010 +#define AUX_EVCTL_EVSTAT0_AUXIO4_S 4 + +// Field: [3] AUXIO3 +// +// AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT0_AUXIO3 0x00000008 +#define AUX_EVCTL_EVSTAT0_AUXIO3_BITN 3 +#define AUX_EVCTL_EVSTAT0_AUXIO3_M 0x00000008 +#define AUX_EVCTL_EVSTAT0_AUXIO3_S 3 + +// Field: [2] AUXIO2 +// +// AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 2 +#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUXIO2_S 2 + +// Field: [1] AUXIO1 +// +// AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 1 +#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUXIO1_S 1 + +// Field: [0] AUXIO0 +// +// AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00000001 +#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 0 +#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00000001 +#define AUX_EVCTL_EVSTAT0_AUXIO0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT1 +// +//***************************************************************************** +// Field: [15] AUXIO31 +// +// AUXIO31 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT1_AUXIO31 0x00008000 +#define AUX_EVCTL_EVSTAT1_AUXIO31_BITN 15 +#define AUX_EVCTL_EVSTAT1_AUXIO31_M 0x00008000 +#define AUX_EVCTL_EVSTAT1_AUXIO31_S 15 + +// Field: [14] AUXIO30 +// +// AUXIO30 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT1_AUXIO30 0x00004000 +#define AUX_EVCTL_EVSTAT1_AUXIO30_BITN 14 +#define AUX_EVCTL_EVSTAT1_AUXIO30_M 0x00004000 +#define AUX_EVCTL_EVSTAT1_AUXIO30_S 14 + +// Field: [13] AUXIO29 +// +// AUXIO29 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT1_AUXIO29 0x00002000 +#define AUX_EVCTL_EVSTAT1_AUXIO29_BITN 13 +#define AUX_EVCTL_EVSTAT1_AUXIO29_M 0x00002000 +#define AUX_EVCTL_EVSTAT1_AUXIO29_S 13 + +// Field: [12] AUXIO28 +// +// AUXIO28 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT1_AUXIO28 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO28_BITN 12 +#define AUX_EVCTL_EVSTAT1_AUXIO28_M 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO28_S 12 + +// Field: [11] AUXIO27 +// +// AUXIO27 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT1_AUXIO27 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO27_BITN 11 +#define AUX_EVCTL_EVSTAT1_AUXIO27_M 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO27_S 11 + +// Field: [10] AUXIO26 +// +// AUXIO26 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT1_AUXIO26 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO26_BITN 10 +#define AUX_EVCTL_EVSTAT1_AUXIO26_M 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO26_S 10 + +// Field: [9] AUXIO25 +// +// AUXIO25 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT1_AUXIO25 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO25_BITN 9 +#define AUX_EVCTL_EVSTAT1_AUXIO25_M 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO25_S 9 + +// Field: [8] AUXIO24 +// +// AUXIO24 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT1_AUXIO24 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO24_BITN 8 +#define AUX_EVCTL_EVSTAT1_AUXIO24_M 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO24_S 8 + +// Field: [7] AUXIO23 +// +// AUXIO23 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT1_AUXIO23 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO23_BITN 7 +#define AUX_EVCTL_EVSTAT1_AUXIO23_M 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO23_S 7 + +// Field: [6] AUXIO22 +// +// AUXIO22 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT1_AUXIO22 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO22_BITN 6 +#define AUX_EVCTL_EVSTAT1_AUXIO22_M 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO22_S 6 + +// Field: [5] AUXIO21 +// +// AUXIO21 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT1_AUXIO21 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO21_BITN 5 +#define AUX_EVCTL_EVSTAT1_AUXIO21_M 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO21_S 5 + +// Field: [4] AUXIO20 +// +// AUXIO20 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT1_AUXIO20 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO20_BITN 4 +#define AUX_EVCTL_EVSTAT1_AUXIO20_M 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO20_S 4 + +// Field: [3] AUXIO19 +// +// AUXIO19 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT1_AUXIO19 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO19_BITN 3 +#define AUX_EVCTL_EVSTAT1_AUXIO19_M 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO19_S 3 + +// Field: [2] AUXIO18 +// +// AUXIO18 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT1_AUXIO18 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO18_BITN 2 +#define AUX_EVCTL_EVSTAT1_AUXIO18_M 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO18_S 2 + +// Field: [1] AUXIO17 +// +// AUXIO17 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT1_AUXIO17 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO17_BITN 1 +#define AUX_EVCTL_EVSTAT1_AUXIO17_M 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO17_S 1 + +// Field: [0] AUXIO16 +// +// AUXIO16 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT1_AUXIO16 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO16_BITN 0 +#define AUX_EVCTL_EVSTAT1_AUXIO16_M 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO16_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT2 +// +//***************************************************************************** +// Field: [15] AUX_COMPB +// +// Comparator B output. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPB_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT2_AUX_COMPB 0x00008000 +#define AUX_EVCTL_EVSTAT2_AUX_COMPB_BITN 15 +#define AUX_EVCTL_EVSTAT2_AUX_COMPB_M 0x00008000 +#define AUX_EVCTL_EVSTAT2_AUX_COMPB_S 15 + +// Field: [14] AUX_COMPA +// +// Comparator A output. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPA_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT2_AUX_COMPA 0x00004000 +#define AUX_EVCTL_EVSTAT2_AUX_COMPA_BITN 14 +#define AUX_EVCTL_EVSTAT2_AUX_COMPA_M 0x00004000 +#define AUX_EVCTL_EVSTAT2_AUX_COMPA_S 14 + +// Field: [13] MCU_OBSMUX1 +// +// Observation input 1 from IOC. +// This event is configured by IOC:OBSAUXOUTPUT.SEL1. +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1 0x00002000 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_BITN 13 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_M 0x00002000 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_S 13 + +// Field: [12] MCU_OBSMUX0 +// +// Observation input 0 from IOC. +// This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by +// IOC:OBSAUXOUTPUT.SEL_MISC. +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0 0x00001000 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_BITN 12 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_M 0x00001000 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_S 12 + +// Field: [11] MCU_EV +// +// Event from EVENT configured by EVENT:AUXSEL0. +#define AUX_EVCTL_EVSTAT2_MCU_EV 0x00000800 +#define AUX_EVCTL_EVSTAT2_MCU_EV_BITN 11 +#define AUX_EVCTL_EVSTAT2_MCU_EV_M 0x00000800 +#define AUX_EVCTL_EVSTAT2_MCU_EV_S 11 + +// Field: [10] ACLK_REF +// +// TDC reference clock. +// It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by +// AUX_SYSIF:TDCREFCLKCTL.REQ. +#define AUX_EVCTL_EVSTAT2_ACLK_REF 0x00000400 +#define AUX_EVCTL_EVSTAT2_ACLK_REF_BITN 10 +#define AUX_EVCTL_EVSTAT2_ACLK_REF_M 0x00000400 +#define AUX_EVCTL_EVSTAT2_ACLK_REF_S 10 + +// Field: [9] VDDR_RECHARGE +// +// Event is high during VDDR recharge. +#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE 0x00000200 +#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_BITN 9 +#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_M 0x00000200 +#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_S 9 + +// Field: [8] MCU_ACTIVE +// +// Event is high while system(MCU, AUX, or JTAG domains) is active or +// transitions to active (GLDO or DCDC power supply state). Event is not high +// during VDDR recharge. +#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE 0x00000100 +#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_BITN 8 +#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_M 0x00000100 +#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_S 8 + +// Field: [7] PWR_DWN +// +// Event is high while system(MCU, AUX, or JTAG domains) is in powerdown (uLDO +// power supply). +#define AUX_EVCTL_EVSTAT2_PWR_DWN 0x00000080 +#define AUX_EVCTL_EVSTAT2_PWR_DWN_BITN 7 +#define AUX_EVCTL_EVSTAT2_PWR_DWN_M 0x00000080 +#define AUX_EVCTL_EVSTAT2_PWR_DWN_S 7 + +// Field: [6] SCLK_LF +// +// SCLK_LF clock +#define AUX_EVCTL_EVSTAT2_SCLK_LF 0x00000040 +#define AUX_EVCTL_EVSTAT2_SCLK_LF_BITN 6 +#define AUX_EVCTL_EVSTAT2_SCLK_LF_M 0x00000040 +#define AUX_EVCTL_EVSTAT2_SCLK_LF_S 6 + +// Field: [5] AON_BATMON_TEMP_UPD +// +// Event is high for two SCLK_MF clock periods when there is an update of +// AON_BATMON:TEMP. +#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD 0x00000020 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_BITN 5 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_M 0x00000020 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_S 5 + +// Field: [4] AON_BATMON_BAT_UPD +// +// Event is high for two SCLK_MF clock periods when there is an update of +// AON_BATMON:BAT. +#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD 0x00000010 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_BITN 4 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_M 0x00000010 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_S 4 + +// Field: [3] AON_RTC_4KHZ +// +// AON_RTC:SUBSEC.VALUE bit 19. +// AON_RTC:CTL.RTC_4KHZ_EN enables this event. +#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ 0x00000008 +#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_BITN 3 +#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_M 0x00000008 +#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_S 3 + +// Field: [2] AON_RTC_CH2_DLY +// +// AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration. +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY 0x00000004 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_BITN 2 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_M 0x00000004 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_S 2 + +// Field: [1] AON_RTC_CH2 +// +// AON_RTC:EVFLAGS.CH2. +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2 0x00000002 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_BITN 1 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_M 0x00000002 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_S 1 + +// Field: [0] MANUAL_EV +// +// Programmable event. See MANUAL for description. +#define AUX_EVCTL_EVSTAT2_MANUAL_EV 0x00000001 +#define AUX_EVCTL_EVSTAT2_MANUAL_EV_BITN 0 +#define AUX_EVCTL_EVSTAT2_MANUAL_EV_M 0x00000001 +#define AUX_EVCTL_EVSTAT2_MANUAL_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT3 +// +//***************************************************************************** +// Field: [15] AUX_TIMER2_CLKSWITCH_RDY +// +// AUX_SYSIF:TIMER2CLKSWITCH.RDY +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY 0x00008000 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_BITN 15 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_M 0x00008000 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_S 15 + +// Field: [14] AUX_DAC_HOLD_ACTIVE +// +// AUX_ANAIF:DACSTAT.HOLD_ACTIVE +#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE 0x00004000 +#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_BITN 14 +#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_M 0x00004000 +#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_S 14 + +// Field: [13] AUX_SMPH_AUTOTAKE_DONE +// +// See AUX_SMPH:AUTOTAKE.SMPH_ID for description. +#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE 0x00002000 +#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_BITN 13 +#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_M 0x00002000 +#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_S 13 + +// Field: [12] AUX_ADC_FIFO_NOT_EMPTY +// +// AUX_ANAIF:ADCFIFOSTAT.EMPTY negated +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY 0x00001000 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_BITN 12 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_M 0x00001000 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_S 12 + +// Field: [11] AUX_ADC_FIFO_ALMOST_FULL +// +// AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_BITN 11 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000800 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_S 11 + +// Field: [10] AUX_ADC_IRQ +// +// The logical function for this event is configurable. +// +// When DMACTL.EN = 1 : +// Event = UDMA0 Channel 7 done event OR +// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW +// +// When DMACTL.EN = 0 : +// Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR +// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW +// +// Bit 7 in UDMA0:DONEMASK must be 0. +#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_S 10 + +// Field: [9] AUX_ADC_DONE +// +// AUX_ANAIF ADC conversion done event. +// Event is synchronized at AUX bus rate. +#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE 0x00000200 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_BITN 9 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_M 0x00000200 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_S 9 + +// Field: [8] AUX_ISRC_RESET_N +// +// AUX_ANAIF:ISRCCTL.RESET_N +#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N 0x00000100 +#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_BITN 8 +#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_M 0x00000100 +#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_S 8 + +// Field: [7] AUX_TDC_DONE +// +// AUX_TDC:STAT.DONE +#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE 0x00000080 +#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_BITN 7 +#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_M 0x00000080 +#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_S 7 + +// Field: [6] AUX_TIMER0_EV +// +// AUX_TIMER0_EV event, see AUX_TIMER01:T0TARGET for description. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV 0x00000040 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_BITN 6 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_M 0x00000040 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_S 6 + +// Field: [5] AUX_TIMER1_EV +// +// AUX_TIMER1_EV event, see AUX_TIMER01:T1TARGET for description. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_S 5 + +// Field: [4] AUX_TIMER2_PULSE +// +// AUX_TIMER2 pulse event. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE 0x00000010 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_BITN 4 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_M 0x00000010 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_S 4 + +// Field: [3] AUX_TIMER2_EV3 +// +// AUX_TIMER2 event output 3. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3 0x00000008 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_BITN 3 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_M 0x00000008 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_S 3 + +// Field: [2] AUX_TIMER2_EV2 +// +// AUX_TIMER2 event output 2. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2 0x00000004 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_BITN 2 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_M 0x00000004 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_S 2 + +// Field: [1] AUX_TIMER2_EV1 +// +// AUX_TIMER2 event output 1. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1 0x00000002 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_BITN 1 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_M 0x00000002 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_S 1 + +// Field: [0] AUX_TIMER2_EV0 +// +// AUX_TIMER2 event output 0. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0 0x00000001 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_BITN 0 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_M 0x00000001 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_SCEWEVCFG0 +// +//***************************************************************************** +// Field: [6] COMB_EV_EN +// +// Event combination control: +// +// 0: Disable event combination. +// 1: Enable event combination. +#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN 0x00000040 +#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_BITN 6 +#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_M 0x00000040 +#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_S 6 + +// Field: [5:0] EV0_SEL +// +// Select the event source from the synchronous event bus to be used in event +// equation. +// ENUMs: +// AUX_TIMER2_CLKSWITCH_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY +// AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE +// AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB EVSTAT2.AUX_COMPB +// AUX_COMPA EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0 +// MCU_EV EVSTAT2.MCU_EV +// ACLK_REF EVSTAT2.ACLK_REF +// VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE EVSTAT2.MCU_ACTIVE +// PWR_DWN EVSTAT2.PWR_DWN +// SCLK_LF EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 EVSTAT2.AON_RTC_CH2 +// AUX_PROG_DLY_IDLE Programmable delay event as described in PROGDLY +// AUXIO31 EVSTAT1.AUXIO31 +// AUXIO30 EVSTAT1.AUXIO30 +// AUXIO29 EVSTAT1.AUXIO29 +// AUXIO28 EVSTAT1.AUXIO28 +// AUXIO27 EVSTAT1.AUXIO27 +// AUXIO26 EVSTAT1.AUXIO26 +// AUXIO25 EVSTAT1.AUXIO25 +// AUXIO24 EVSTAT1.AUXIO24 +// AUXIO23 EVSTAT1.AUXIO23 +// AUXIO22 EVSTAT1.AUXIO22 +// AUXIO21 EVSTAT1.AUXIO21 +// AUXIO20 EVSTAT1.AUXIO20 +// AUXIO19 EVSTAT1.AUXIO19 +// AUXIO18 EVSTAT1.AUXIO18 +// AUXIO17 EVSTAT1.AUXIO17 +// AUXIO16 EVSTAT1.AUXIO16 +// AUXIO15 EVSTAT0.AUXIO15 +// AUXIO14 EVSTAT0.AUXIO14 +// AUXIO13 EVSTAT0.AUXIO13 +// AUXIO12 EVSTAT0.AUXIO12 +// AUXIO11 EVSTAT0.AUXIO11 +// AUXIO10 EVSTAT0.AUXIO10 +// AUXIO9 EVSTAT0.AUXIO9 +// AUXIO8 EVSTAT0.AUXIO8 +// AUXIO7 EVSTAT0.AUXIO7 +// AUXIO6 EVSTAT0.AUXIO6 +// AUXIO5 EVSTAT0.AUXIO5 +// AUXIO4 EVSTAT0.AUXIO4 +// AUXIO3 EVSTAT0.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_W 6 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_M 0x0000003F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_S 0 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_CLKSWITCH_RDY 0x0000003F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_IRQ 0x0000003A +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_DONE 0x00000039 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ISRC_RESET_N 0x00000038 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TDC_DONE 0x00000037 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER0_EV 0x00000036 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER1_EV 0x00000035 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_PULSE 0x00000034 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV3 0x00000033 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV2 0x00000032 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV1 0x00000031 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV0 0x00000030 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_COMPB 0x0000002F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_COMPA 0x0000002E +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_OBSMUX1 0x0000002D +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_OBSMUX0 0x0000002C +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_EV 0x0000002B +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_ACLK_REF 0x0000002A +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_VDDR_RECHARGE 0x00000029 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_ACTIVE 0x00000028 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_PWR_DWN 0x00000027 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_SCLK_LF 0x00000026 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_4KHZ 0x00000023 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_CH2_DLY 0x00000022 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_CH2 0x00000021 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_PROG_DLY_IDLE 0x00000020 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO31 0x0000001F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO30 0x0000001E +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO29 0x0000001D +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO28 0x0000001C +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO27 0x0000001B +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO26 0x0000001A +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO25 0x00000019 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO24 0x00000018 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO23 0x00000017 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO22 0x00000016 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO21 0x00000015 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO20 0x00000014 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO19 0x00000013 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO18 0x00000012 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO17 0x00000011 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO16 0x00000010 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO15 0x0000000F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO14 0x0000000E +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO13 0x0000000D +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO12 0x0000000C +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO11 0x0000000B +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO10 0x0000000A +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO9 0x00000009 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO8 0x00000008 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO7 0x00000007 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO6 0x00000006 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO5 0x00000005 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO4 0x00000004 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO3 0x00000003 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO2 0x00000002 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO1 0x00000001 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_SCEWEVCFG1 +// +//***************************************************************************** +// Field: [7] EV0_POL +// +// Polarity of SCEWEVCFG0.EV0_SEL event. +// +// When SCEWEVCFG0.COMB_EV_EN is 0: +// +// 0: Non-inverted. +// 1: Non-inverted. +// +// When SCEWEVCFG0.COMB_EV_EN is 1. +// +// 0: Non-inverted. +// 1: Inverted. +#define AUX_EVCTL_SCEWEVCFG1_EV0_POL 0x00000080 +#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_BITN 7 +#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_M 0x00000080 +#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_S 7 + +// Field: [6] EV1_POL +// +// Polarity of EV1_SEL event. +// +// When SCEWEVCFG0.COMB_EV_EN is 0: +// +// 0: Non-inverted. +// 1: Non-inverted. +// +// When SCEWEVCFG0.COMB_EV_EN is 1. +// +// 0: Non-inverted. +// 1: Inverted. +#define AUX_EVCTL_SCEWEVCFG1_EV1_POL 0x00000040 +#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_BITN 6 +#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_M 0x00000040 +#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_S 6 + +// Field: [5:0] EV1_SEL +// +// Select the event source from the synchronous event bus to be used in event +// equation. +// ENUMs: +// AUX_TIMER2_CLKSWITCH_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY +// AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE +// AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB EVSTAT2.AUX_COMPB +// AUX_COMPA EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0 +// MCU_EV EVSTAT2.MCU_EV +// ACLK_REF EVSTAT2.ACLK_REF +// VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE EVSTAT2.MCU_ACTIVE +// PWR_DWN EVSTAT2.PWR_DWN +// SCLK_LF EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 EVSTAT2.AON_RTC_CH2 +// AUX_PROG_DLY_IDLE Programmable delay event as described in PROGDLY +// AUXIO31 EVSTAT1.AUXIO31 +// AUXIO30 EVSTAT1.AUXIO30 +// AUXIO29 EVSTAT1.AUXIO29 +// AUXIO28 EVSTAT1.AUXIO28 +// AUXIO27 EVSTAT1.AUXIO27 +// AUXIO26 EVSTAT1.AUXIO26 +// AUXIO25 EVSTAT1.AUXIO25 +// AUXIO24 EVSTAT1.AUXIO24 +// AUXIO23 EVSTAT1.AUXIO23 +// AUXIO22 EVSTAT1.AUXIO22 +// AUXIO21 EVSTAT1.AUXIO21 +// AUXIO20 EVSTAT1.AUXIO20 +// AUXIO19 EVSTAT1.AUXIO19 +// AUXIO18 EVSTAT1.AUXIO18 +// AUXIO17 EVSTAT1.AUXIO17 +// AUXIO16 EVSTAT1.AUXIO16 +// AUXIO15 EVSTAT0.AUXIO15 +// AUXIO14 EVSTAT0.AUXIO14 +// AUXIO13 EVSTAT0.AUXIO13 +// AUXIO12 EVSTAT0.AUXIO12 +// AUXIO11 EVSTAT0.AUXIO11 +// AUXIO10 EVSTAT0.AUXIO10 +// AUXIO9 EVSTAT0.AUXIO9 +// AUXIO8 EVSTAT0.AUXIO8 +// AUXIO7 EVSTAT0.AUXIO7 +// AUXIO6 EVSTAT0.AUXIO6 +// AUXIO5 EVSTAT0.AUXIO5 +// AUXIO4 EVSTAT0.AUXIO4 +// AUXIO3 EVSTAT0.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_W 6 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_M 0x0000003F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_S 0 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_CLKSWITCH_RDY 0x0000003F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_IRQ 0x0000003A +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_DONE 0x00000039 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ISRC_RESET_N 0x00000038 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TDC_DONE 0x00000037 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER0_EV 0x00000036 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER1_EV 0x00000035 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_PULSE 0x00000034 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV3 0x00000033 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV2 0x00000032 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV1 0x00000031 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV0 0x00000030 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_COMPB 0x0000002F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_COMPA 0x0000002E +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_OBSMUX1 0x0000002D +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_OBSMUX0 0x0000002C +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_EV 0x0000002B +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_ACLK_REF 0x0000002A +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_VDDR_RECHARGE 0x00000029 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_ACTIVE 0x00000028 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_PWR_DWN 0x00000027 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_SCLK_LF 0x00000026 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_4KHZ 0x00000023 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_CH2_DLY 0x00000022 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_CH2 0x00000021 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_PROG_DLY_IDLE 0x00000020 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO31 0x0000001F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO30 0x0000001E +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO29 0x0000001D +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO28 0x0000001C +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO27 0x0000001B +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO26 0x0000001A +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO25 0x00000019 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO24 0x00000018 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO23 0x00000017 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO22 0x00000016 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO21 0x00000015 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO20 0x00000014 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO19 0x00000013 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO18 0x00000012 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO17 0x00000011 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO16 0x00000010 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO15 0x0000000F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO14 0x0000000E +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO13 0x0000000D +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO12 0x0000000C +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO11 0x0000000B +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO10 0x0000000A +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO9 0x00000009 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO8 0x00000008 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO7 0x00000007 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO6 0x00000006 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO5 0x00000005 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO4 0x00000004 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO3 0x00000003 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO2 0x00000002 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO1 0x00000001 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_DMACTL +// +//***************************************************************************** +// Field: [2] REQ_MODE +// +// UDMA0 Request mode +// ENUMs: +// SINGLE Single requests are generated on UDMA0 channel 7 +// when the condition configured in SEL is met. +// BURST Burst requests are generated on UDMA0 channel 7 +// when the condition configured in SEL is met. +#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_S 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000 + +// Field: [1] EN +// +// uDMA ADC interface enable. +// +// 0: Disable UDMA0 interface to ADC. +// 1: Enable UDMA0 interface to ADC. +#define AUX_EVCTL_DMACTL_EN 0x00000002 +#define AUX_EVCTL_DMACTL_EN_BITN 1 +#define AUX_EVCTL_DMACTL_EN_M 0x00000002 +#define AUX_EVCTL_DMACTL_EN_S 1 + +// Field: [0] SEL +// +// Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO +// data. +// ENUMs: +// AUX_ADC_FIFO_ALMOST_FULL UDMA0 trigger event will be generated when the ADC +// FIFO is almost full (3/4 full). +// AUX_ADC_FIFO_NOT_EMPTY UDMA0 trigger event will be generated when there +// are samples in the ADC FIFO. +#define AUX_EVCTL_DMACTL_SEL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_BITN 0 +#define AUX_EVCTL_DMACTL_SEL_M 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_S 0 +#define AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_SWEVSET +// +//***************************************************************************** +// Field: [2] SWEV2 +// +// Software event flag 2. +// +// 0: No effect. +// 1: Set software event flag 2. +#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2 +#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// Software event flag 1. +// +// 0: No effect. +// 1: Set software event flag 1. +#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1 +#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// Software event flag 0. +// +// 0: No effect. +// 1: Set software event flag 0. +#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0 +#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONFLAGS +// +//***************************************************************************** +// Field: [8] AUX_TIMER1_EV +// +// This event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV +// occurs on EVSTAT3.AUX_TIMER1_EV. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_S 8 + +// Field: [7] AUX_TIMER0_EV +// +// This event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV +// occurs on EVSTAT3.AUX_TIMER0_EV. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_S 7 + +// Field: [6] AUX_TDC_DONE +// +// This event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs +// on EVSTAT3.AUX_TDC_DONE. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_S 6 + +// Field: [5] AUX_ADC_DONE +// +// This event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs +// on EVSTAT3.AUX_ADC_DONE. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_S 5 + +// Field: [4] AUX_COMPB +// +// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on +// EVSTAT2.AUX_COMPB. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4 + +// Field: [3] AUX_COMPA +// +// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on +// EVSTAT2.AUX_COMPA. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3 + +// Field: [2] SWEV2 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV2. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV1. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV0. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONPOL +// +//***************************************************************************** +// Field: [8] AUX_TIMER1_EV +// +// Select the level of EVSTAT3.AUX_TIMER1_EV that sets +// EVTOAONFLAGS.AUX_TIMER1_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_LOW 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_HIGH 0x00000000 + +// Field: [7] AUX_TIMER0_EV +// +// Select the level of EVSTAT3.AUX_TIMER0_EV that sets +// EVTOAONFLAGS.AUX_TIMER0_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_LOW 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_HIGH 0x00000000 + +// Field: [6] AUX_TDC_DONE +// +// Select level of EVSTAT3.AUX_TDC_DONE that sets EVTOAONFLAGS.AUX_TDC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_HIGH 0x00000000 + +// Field: [5] AUX_ADC_DONE +// +// Select the level of EVSTAT3.AUX_ADC_DONE that sets +// EVTOAONFLAGS.AUX_ADC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_LOW 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_HIGH 0x00000000 + +// Field: [4] AUX_COMPB +// +// Select the edge of EVSTAT2.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB. +// ENUMs: +// FALL Falling edge +// RISE Rising edge +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_FALL 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_RISE 0x00000000 + +// Field: [3] AUX_COMPA +// +// Select the edge of EVSTAT2.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA. +// ENUMs: +// FALL Falling edge +// RISE Rising edge +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_FALL 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_RISE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONFLAGSCLR +// +//***************************************************************************** +// Field: [8] AUX_TIMER1_EV +// +// Write 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_S 8 + +// Field: [7] AUX_TIMER0_EV +// +// Write 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_S 7 + +// Field: [6] AUX_TDC_DONE +// +// Write 1 to clear EVTOAONFLAGS.AUX_TDC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_S 6 + +// Field: [5] AUX_ADC_DONE +// +// Write 1 to clear EVTOAONFLAGS.AUX_ADC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_S 5 + +// Field: [4] AUX_COMPB +// +// Write 1 to clear EVTOAONFLAGS.AUX_COMPB. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4 + +// Field: [3] AUX_COMPA +// +// Write 1 to clear EVTOAONFLAGS.AUX_COMPA. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3 + +// Field: [2] SWEV2 +// +// Write 1 to clear EVTOAONFLAGS.SWEV2. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// Write 1 to clear EVTOAONFLAGS.SWEV1. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// Write 1 to clear EVTOAONFLAGS.SWEV0. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUFLAGS +// +//***************************************************************************** +// Field: [15] AUX_TIMER2_PULSE +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_PULSE +// occurs on EVSTAT3.AUX_TIMER2_PULSE. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE 0x00008000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_BITN 15 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_M 0x00008000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_S 15 + +// Field: [14] AUX_TIMER2_EV3 +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV3 +// occurs on EVSTAT3.AUX_TIMER2_EV3. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3 0x00004000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_BITN 14 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_M 0x00004000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_S 14 + +// Field: [13] AUX_TIMER2_EV2 +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV2 +// occurs on EVSTAT3.AUX_TIMER2_EV2. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2 0x00002000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_BITN 13 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_M 0x00002000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_S 13 + +// Field: [12] AUX_TIMER2_EV1 +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV1 +// occurs on EVSTAT3.AUX_TIMER2_EV1. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1 0x00001000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_BITN 12 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_M 0x00001000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_S 12 + +// Field: [11] AUX_TIMER2_EV0 +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV0 +// occurs on EVSTAT3.AUX_TIMER2_EV0. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0 0x00000800 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_BITN 11 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_M 0x00000800 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_S 11 + +// Field: [10] AUX_ADC_IRQ +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs +// on EVSTAT3.AUX_ADC_IRQ. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_S 10 + +// Field: [9] MCU_OBSMUX0 +// +// This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs +// on EVSTAT2.MCU_OBSMUX0. +#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_S 9 + +// Field: [8] AUX_ADC_FIFO_ALMOST_FULL +// +// This event flag is set when level selected by +// EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on +// EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] AUX_ADC_DONE +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs +// on EVSTAT3.AUX_ADC_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_S 7 + +// Field: [6] AUX_SMPH_AUTOTAKE_DONE +// +// This event flag is set when level selected by +// EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] AUX_TIMER1_EV +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV +// occurs on EVSTAT3.AUX_TIMER1_EV. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_S 5 + +// Field: [4] AUX_TIMER0_EV +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV +// occurs on EVSTAT3.AUX_TIMER0_EV. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_S 4 + +// Field: [3] AUX_TDC_DONE +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs +// on EVSTAT3.AUX_TDC_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on +// EVSTAT2.AUX_COMPB. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on +// EVSTAT2.AUX_COMPA. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1 + +// Field: [0] AUX_WU_EV +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_WU_EV occurs on +// reduction-OR of the AUX_SYSIF:WUFLAGS register. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUPOL +// +//***************************************************************************** +// Field: [15] AUX_TIMER2_PULSE +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_PULSE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE 0x00008000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_BITN 15 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_M 0x00008000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_S 15 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_LOW 0x00008000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_HIGH 0x00000000 + +// Field: [14] AUX_TIMER2_EV3 +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV3. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3 0x00004000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_BITN 14 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_M 0x00004000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_S 14 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_LOW 0x00004000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_HIGH 0x00000000 + +// Field: [13] AUX_TIMER2_EV2 +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV2. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2 0x00002000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_BITN 13 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_M 0x00002000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_S 13 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_LOW 0x00002000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_HIGH 0x00000000 + +// Field: [12] AUX_TIMER2_EV1 +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV1. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1 0x00001000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_BITN 12 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_M 0x00001000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_S 12 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_LOW 0x00001000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_HIGH 0x00000000 + +// Field: [11] AUX_TIMER2_EV0 +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV0. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0 0x00000800 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_BITN 11 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_M 0x00000800 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_S 11 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_LOW 0x00000800 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_HIGH 0x00000000 + +// Field: [10] AUX_ADC_IRQ +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_IRQ. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_LOW 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_HIGH 0x00000000 + +// Field: [9] MCU_OBSMUX0 +// +// Select the event source level that sets EVTOMCUFLAGS.MCU_OBSMUX0. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_LOW 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_HIGH 0x00000000 + +// Field: [8] AUX_ADC_FIFO_ALMOST_FULL +// +// Select the event source level that sets +// EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_LOW 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000 + +// Field: [7] AUX_ADC_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_LOW 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_HIGH 0x00000000 + +// Field: [6] AUX_SMPH_AUTOTAKE_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_HIGH 0x00000000 + +// Field: [5] AUX_TIMER1_EV +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER1_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_LOW 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_HIGH 0x00000000 + +// Field: [4] AUX_TIMER0_EV +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER0_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_LOW 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_HIGH 0x00000000 + +// Field: [3] AUX_TDC_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TDC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_LOW 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_HIGH 0x00000000 + +// Field: [2] AUX_COMPB +// +// Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPB. +// ENUMs: +// FALL Falling edge +// RISE Rising edge +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_FALL 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_RISE 0x00000000 + +// Field: [1] AUX_COMPA +// +// Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPA. +// ENUMs: +// FALL Falling edge +// RISE Rising edge +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_FALL 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_RISE 0x00000000 + +// Field: [0] AUX_WU_EV +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_WU_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_LOW 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_HIGH 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUFLAGSCLR +// +//***************************************************************************** +// Field: [15] AUX_TIMER2_PULSE +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_PULSE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE 0x00008000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_BITN 15 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_M 0x00008000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_S 15 + +// Field: [14] AUX_TIMER2_EV3 +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV3. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3 0x00004000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_BITN 14 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_M 0x00004000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_S 14 + +// Field: [13] AUX_TIMER2_EV2 +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV2. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2 0x00002000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_BITN 13 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_M 0x00002000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_S 13 + +// Field: [12] AUX_TIMER2_EV1 +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV1. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1 0x00001000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_BITN 12 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_M 0x00001000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_S 12 + +// Field: [11] AUX_TIMER2_EV0 +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV0. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0 0x00000800 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_BITN 11 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_M 0x00000800 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_S 11 + +// Field: [10] AUX_ADC_IRQ +// +// Write 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_S 10 + +// Field: [9] MCU_OBSMUX0 +// +// Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_S 9 + +// Field: [8] AUX_ADC_FIFO_ALMOST_FULL +// +// Write 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] AUX_ADC_DONE +// +// Write 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_S 7 + +// Field: [6] AUX_SMPH_AUTOTAKE_DONE +// +// Write 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] AUX_TIMER1_EV +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_S 5 + +// Field: [4] AUX_TIMER0_EV +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_S 4 + +// Field: [3] AUX_TDC_DONE +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1 + +// Field: [0] AUX_WU_EV +// +// Write 1 to clear EVTOMCUFLAGS.AUX_WU_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_COMBEVTOMCUMASK +// +//***************************************************************************** +// Field: [15] AUX_TIMER2_PULSE +// +// EVTOMCUFLAGS.AUX_TIMER2_PULSE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE 0x00008000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_BITN 15 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_M 0x00008000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_S 15 + +// Field: [14] AUX_TIMER2_EV3 +// +// EVTOMCUFLAGS.AUX_TIMER2_EV3 contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3 0x00004000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_BITN 14 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_M 0x00004000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_S 14 + +// Field: [13] AUX_TIMER2_EV2 +// +// EVTOMCUFLAGS.AUX_TIMER2_EV2 contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2 0x00002000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_BITN 13 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_M 0x00002000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_S 13 + +// Field: [12] AUX_TIMER2_EV1 +// +// EVTOMCUFLAGS.AUX_TIMER2_EV1 contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1 0x00001000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_BITN 12 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_M 0x00001000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_S 12 + +// Field: [11] AUX_TIMER2_EV0 +// +// EVTOMCUFLAGS.AUX_TIMER2_EV0 contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0 0x00000800 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_BITN 11 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_M 0x00000800 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_S 11 + +// Field: [10] AUX_ADC_IRQ +// +// EVTOMCUFLAGS.AUX_ADC_IRQ contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_S 10 + +// Field: [9] MCU_OBSMUX0 +// +// EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_BITN 9 +#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_S 9 + +// Field: [8] AUX_ADC_FIFO_ALMOST_FULL +// +// EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] AUX_ADC_DONE +// +// EVTOMCUFLAGS.AUX_ADC_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_BITN 7 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_S 7 + +// Field: [6] AUX_SMPH_AUTOTAKE_DONE +// +// EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] AUX_TIMER1_EV +// +// EVTOMCUFLAGS.AUX_TIMER1_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_S 5 + +// Field: [4] AUX_TIMER0_EV +// +// EVTOMCUFLAGS.AUX_TIMER0_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_BITN 4 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_S 4 + +// Field: [3] AUX_TDC_DONE +// +// EVTOMCUFLAGS.AUX_TDC_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_BITN 3 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event. +// +// 0: Exclude +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1 + +// Field: [0] AUX_WU_EV +// +// EVTOMCUFLAGS.AUX_WU_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_BITN 0 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_M 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVOBSCFG +// +//***************************************************************************** +// Field: [5:0] EVOBS_SEL +// +// Select which event from the asynchronous event bus that represents +// AUX_EV_OBS in AUX_AIODIOn. +// ENUMs: +// AUX_TIMER2_CLKSW_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY +// AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE +// AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB EVSTAT2.AUX_COMPB +// AUX_COMPA EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0 +// MCU_EV EVSTAT2.MCU_EV +// ACLK_REF EVSTAT2.ACLK_REF +// VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE EVSTAT2.MCU_ACTIVE +// PWR_DWN EVSTAT2.PWR_DWN +// SCLK_LF EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 EVSTAT2.AON_RTC_CH2 +// MANUAL_EV EVSTAT2.MANUAL_EV +// AUXIO31 EVSTAT1.AUXIO31 +// AUXIO30 EVSTAT1.AUXIO30 +// AUXIO29 EVSTAT1.AUXIO29 +// AUXIO28 EVSTAT1.AUXIO28 +// AUXIO27 EVSTAT1.AUXIO27 +// AUXIO26 EVSTAT1.AUXIO26 +// AUXIO25 EVSTAT1.AUXIO25 +// AUXIO24 EVSTAT1.AUXIO24 +// AUXIO23 EVSTAT1.AUXIO23 +// AUXIO22 EVSTAT1.AUXIO22 +// AUXIO21 EVSTAT1.AUXIO21 +// AUXIO20 EVSTAT1.AUXIO20 +// AUXIO19 EVSTAT1.AUXIO19 +// AUXIO18 EVSTAT1.AUXIO18 +// AUXIO17 EVSTAT1.AUXIO17 +// AUXIO16 EVSTAT1.AUXIO16 +// AUXIO15 EVSTAT0.AUXIO15 +// AUXIO14 EVSTAT0.AUXIO14 +// AUXIO13 EVSTAT0.AUXIO13 +// AUXIO12 EVSTAT0.AUXIO12 +// AUXIO11 EVSTAT0.AUXIO11 +// AUXIO10 EVSTAT0.AUXIO10 +// AUXIO9 EVSTAT0.AUXIO9 +// AUXIO8 EVSTAT0.AUXIO8 +// AUXIO7 EVSTAT0.AUXIO7 +// AUXIO6 EVSTAT0.AUXIO6 +// AUXIO5 EVSTAT0.AUXIO5 +// AUXIO4 EVSTAT0.AUXIO4 +// AUXIO3 EVSTAT0.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_W 6 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_M 0x0000003F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_S 0 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_CLKSW_RDY 0x0000003F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_IRQ 0x0000003A +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_DONE 0x00000039 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ISRC_RESET_N 0x00000038 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TDC_DONE 0x00000037 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER0_EV 0x00000036 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER1_EV 0x00000035 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_PULSE 0x00000034 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV3 0x00000033 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV2 0x00000032 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV1 0x00000031 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV0 0x00000030 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_COMPB 0x0000002F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_COMPA 0x0000002E +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_OBSMUX1 0x0000002D +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_OBSMUX0 0x0000002C +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_EV 0x0000002B +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_ACLK_REF 0x0000002A +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_VDDR_RECHARGE 0x00000029 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_ACTIVE 0x00000028 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_PWR_DWN 0x00000027 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_SCLK_LF 0x00000026 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_4KHZ 0x00000023 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_CH2_DLY 0x00000022 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_CH2 0x00000021 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MANUAL_EV 0x00000020 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO31 0x0000001F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO30 0x0000001E +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO29 0x0000001D +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO28 0x0000001C +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO27 0x0000001B +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO26 0x0000001A +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO25 0x00000019 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO24 0x00000018 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO23 0x00000017 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO22 0x00000016 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO21 0x00000015 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO20 0x00000014 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO19 0x00000013 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO18 0x00000012 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO17 0x00000011 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO16 0x00000010 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO15 0x0000000F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO14 0x0000000E +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO13 0x0000000D +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO12 0x0000000C +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO11 0x0000000B +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO10 0x0000000A +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO9 0x00000009 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO8 0x00000008 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO7 0x00000007 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO6 0x00000006 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO5 0x00000005 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO4 0x00000004 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO3 0x00000003 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO2 0x00000002 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO1 0x00000001 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_PROGDLY +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// VALUE decrements to 0 at a rate of 1 MHz. +// +// The event AUX_PROG_DLY_IDLE is high when VALUE is 0, otherwise it is low. +// +// Only use the programmable delay counter and the AUX_PROG_DLY_IDLE event when +// AUX_SYSIF:OPMODEACK.ACK equals A or LP. +// +// Decrementation of VALUE halts when either is true: +// - AUX_SCE:CTL.DBG_FREEZE_EN is set and system CPU is halted in debug mode. +// - AUX_SYSIF:TIMERHALT.PROGDLY is set. +#define AUX_EVCTL_PROGDLY_VALUE_W 16 +#define AUX_EVCTL_PROGDLY_VALUE_M 0x0000FFFF +#define AUX_EVCTL_PROGDLY_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_MANUAL +// +//***************************************************************************** +// Field: [0] EV +// +// This bit field sets the value of EVSTAT2.MANUAL_EV. +#define AUX_EVCTL_MANUAL_EV 0x00000001 +#define AUX_EVCTL_MANUAL_EV_BITN 0 +#define AUX_EVCTL_MANUAL_EV_M 0x00000001 +#define AUX_EVCTL_MANUAL_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT0L +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT0 event 7 down to 0. +#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT0H +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT0 event 15 down to 8. +#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT1L +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT1 event 7 down to 0. +#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT1H +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT1 event 15 down to 8. +#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT2L +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT2 event 7 down to 0. +#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT2H +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT2 event 15 down to 8. +#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT3L +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT3 event 7 down to 0. +#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT3H +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT3 event 15 down to 8. +#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_S 0 + + +#endif // __AUX_EVCTL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h new file mode 100644 index 0000000..fb426ef --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h @@ -0,0 +1,748 @@ +/****************************************************************************** +* Filename: hw_aux_mac_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_MAC_H__ +#define __HW_AUX_MAC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_MAC component +// +//***************************************************************************** +// Signed Operand 0 +#define AUX_MAC_O_OP0S 0x00000000 + +// Unsigned Operand 0 +#define AUX_MAC_O_OP0U 0x00000004 + +// Signed Operand 1 and Multiply +#define AUX_MAC_O_OP1SMUL 0x00000008 + +// Unsigned Operand 1 and Multiply +#define AUX_MAC_O_OP1UMUL 0x0000000C + +// Signed Operand 1 and Multiply-Accumulate +#define AUX_MAC_O_OP1SMAC 0x00000010 + +// Unsigned Operand 1 and Multiply-Accumulate +#define AUX_MAC_O_OP1UMAC 0x00000014 + +// Signed Operand 1 and 16-bit Addition +#define AUX_MAC_O_OP1SADD16 0x00000018 + +// Unsigned Operand 1 and 16-bit Addition +#define AUX_MAC_O_OP1UADD16 0x0000001C + +// Signed Operand 1 and 32-bit Addition +#define AUX_MAC_O_OP1SADD32 0x00000020 + +// Unsigned Operand 1 and 32-bit Addition +#define AUX_MAC_O_OP1UADD32 0x00000024 + +// Count Leading Zero +#define AUX_MAC_O_CLZ 0x00000028 + +// Count Leading Sign +#define AUX_MAC_O_CLS 0x0000002C + +// Accumulator Shift +#define AUX_MAC_O_ACCSHIFT 0x00000030 + +// Accumulator Reset +#define AUX_MAC_O_ACCRESET 0x00000034 + +// Accumulator Bits 15:0 +#define AUX_MAC_O_ACC15_0 0x00000038 + +// Accumulator Bits 16:1 +#define AUX_MAC_O_ACC16_1 0x0000003C + +// Accumulator Bits 17:2 +#define AUX_MAC_O_ACC17_2 0x00000040 + +// Accumulator Bits 18:3 +#define AUX_MAC_O_ACC18_3 0x00000044 + +// Accumulator Bits 19:4 +#define AUX_MAC_O_ACC19_4 0x00000048 + +// Accumulator Bits 20:5 +#define AUX_MAC_O_ACC20_5 0x0000004C + +// Accumulator Bits 21:6 +#define AUX_MAC_O_ACC21_6 0x00000050 + +// Accumulator Bits 22:7 +#define AUX_MAC_O_ACC22_7 0x00000054 + +// Accumulator Bits 23:8 +#define AUX_MAC_O_ACC23_8 0x00000058 + +// Accumulator Bits 24:9 +#define AUX_MAC_O_ACC24_9 0x0000005C + +// Accumulator Bits 25:10 +#define AUX_MAC_O_ACC25_10 0x00000060 + +// Accumulator Bits 26:11 +#define AUX_MAC_O_ACC26_11 0x00000064 + +// Accumulator Bits 27:12 +#define AUX_MAC_O_ACC27_12 0x00000068 + +// Accumulator Bits 28:13 +#define AUX_MAC_O_ACC28_13 0x0000006C + +// Accumulator Bits 29:14 +#define AUX_MAC_O_ACC29_14 0x00000070 + +// Accumulator Bits 30:15 +#define AUX_MAC_O_ACC30_15 0x00000074 + +// Accumulator Bits 31:16 +#define AUX_MAC_O_ACC31_16 0x00000078 + +// Accumulator Bits 32:17 +#define AUX_MAC_O_ACC32_17 0x0000007C + +// Accumulator Bits 33:18 +#define AUX_MAC_O_ACC33_18 0x00000080 + +// Accumulator Bits 34:19 +#define AUX_MAC_O_ACC34_19 0x00000084 + +// Accumulator Bits 35:20 +#define AUX_MAC_O_ACC35_20 0x00000088 + +// Accumulator Bits 36:21 +#define AUX_MAC_O_ACC36_21 0x0000008C + +// Accumulator Bits 37:22 +#define AUX_MAC_O_ACC37_22 0x00000090 + +// Accumulator Bits 38:23 +#define AUX_MAC_O_ACC38_23 0x00000094 + +// Accumulator Bits 39:24 +#define AUX_MAC_O_ACC39_24 0x00000098 + +// Accumulator Bits 39:32 +#define AUX_MAC_O_ACC39_32 0x0000009C + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP0S +// +//***************************************************************************** +// Field: [15:0] OP0_VALUE +// +// Signed operand 0. +// +// Operand for multiply, multiply-and-accumulate, or 32-bit add operations. +#define AUX_MAC_OP0S_OP0_VALUE_W 16 +#define AUX_MAC_OP0S_OP0_VALUE_M 0x0000FFFF +#define AUX_MAC_OP0S_OP0_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP0U +// +//***************************************************************************** +// Field: [15:0] OP0_VALUE +// +// Unsigned operand 0. +// +// Operand for multiply, multiply-and-accumulate, or 32-bit add operations. +#define AUX_MAC_OP0U_OP0_VALUE_W 16 +#define AUX_MAC_OP0U_OP0_VALUE_M 0x0000FFFF +#define AUX_MAC_OP0U_OP0_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1SMUL +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Signed operand 1 and multiplication trigger. +// +// Write OP1_VALUE to set signed operand 1 and trigger the following operation: +// +// When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * +// OP0S.OP0_VALUE. +// When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE * +// OP0U.OP0_VALUE. +#define AUX_MAC_OP1SMUL_OP1_VALUE_W 16 +#define AUX_MAC_OP1SMUL_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1SMUL_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1UMUL +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Unsigned operand 1 and multiplication trigger. +// +// Write OP1_VALUE to set unsigned operand 1 and trigger the following +// operation: +// +// When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * +// OP0S.OP0_VALUE. +// When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE * +// OP0U.OP0_VALUE. +#define AUX_MAC_OP1UMUL_OP1_VALUE_W 16 +#define AUX_MAC_OP1UMUL_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1UMUL_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1SMAC +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Signed operand 1 and multiply-accumulation trigger. +// +// Write OP1_VALUE to set signed operand 1 and trigger the following operation: +// +// When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * +// OP0S.OP0_VALUE ). +// When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE * +// OP0U.OP0_VALUE ). +#define AUX_MAC_OP1SMAC_OP1_VALUE_W 16 +#define AUX_MAC_OP1SMAC_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1SMAC_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1UMAC +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Unsigned operand 1 and multiply-accumulation trigger. +// +// Write OP1_VALUE to set unsigned operand 1 and trigger the following +// operation: +// +// When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * +// OP0S.OP0_VALUE ). +// When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE * +// OP0U.OP0_VALUE ). +#define AUX_MAC_OP1UMAC_OP1_VALUE_W 16 +#define AUX_MAC_OP1UMAC_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1UMAC_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1SADD16 +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Signed operand 1 and 16-bit addition trigger. +// +// Write OP1_VALUE to set signed operand 1 and trigger the following operation: +// +// ACC = ACC + OP1_VALUE. +#define AUX_MAC_OP1SADD16_OP1_VALUE_W 16 +#define AUX_MAC_OP1SADD16_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1SADD16_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1UADD16 +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Unsigned operand 1 and 16-bit addition trigger. +// +// Write OP1_VALUE to set unsigned operand 1 and trigger the following +// operation: +// +// ACC = ACC + OP1_VALUE. +#define AUX_MAC_OP1UADD16_OP1_VALUE_W 16 +#define AUX_MAC_OP1UADD16_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1UADD16_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1SADD32 +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Upper half of signed 32-bit operand and addition trigger. +// +// Write OP1_VALUE to set upper half of signed 32-bit operand and trigger the +// following operation: +// +// When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + +// (( OP1_VALUE << 16) | OP0S.OP0_VALUE ). +// When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC + +// (( OP1_VALUE << 16) | OP0U.OP0_VALUE ). +#define AUX_MAC_OP1SADD32_OP1_VALUE_W 16 +#define AUX_MAC_OP1SADD32_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1SADD32_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1UADD32 +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Upper half of unsigned 32-bit operand and addition trigger. +// +// Write OP1_VALUE to set upper half of unsigned 32-bit operand and trigger the +// following operation: +// +// When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + +// (( OP1_VALUE << 16) | OP0S.OP0_VALUE ). +// When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC + +// (( OP1_VALUE << 16) | OP0U.OP0_VALUE ). +#define AUX_MAC_OP1UADD32_OP1_VALUE_W 16 +#define AUX_MAC_OP1UADD32_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1UADD32_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_CLZ +// +//***************************************************************************** +// Field: [5:0] VALUE +// +// Number of leading zero bits in the accumulator: +// +// 0x00: 0 leading zeros. +// 0x01: 1 leading zero. +// ... +// 0x28: 40 leading zeros (accumulator value is 0). +#define AUX_MAC_CLZ_VALUE_W 6 +#define AUX_MAC_CLZ_VALUE_M 0x0000003F +#define AUX_MAC_CLZ_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_CLS +// +//***************************************************************************** +// Field: [5:0] VALUE +// +// Number of leading sign bits in the accumulator. +// +// When MSB of accumulator is 0, VALUE is number of leading zeros, MSB +// included. +// When MSB of accumulator is 1, VALUE is number of leading ones, MSB included. +// +// VALUE range is 1 thru 40. +#define AUX_MAC_CLS_VALUE_W 6 +#define AUX_MAC_CLS_VALUE_M 0x0000003F +#define AUX_MAC_CLS_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACCSHIFT +// +//***************************************************************************** +// Field: [2] LSL1 +// +// Logic shift left by 1 bit. +// +// Write 1 to shift the accumulator one bit to the left, 0 inserted at bit 0. +#define AUX_MAC_ACCSHIFT_LSL1 0x00000004 +#define AUX_MAC_ACCSHIFT_LSL1_BITN 2 +#define AUX_MAC_ACCSHIFT_LSL1_M 0x00000004 +#define AUX_MAC_ACCSHIFT_LSL1_S 2 + +// Field: [1] LSR1 +// +// Logic shift right by 1 bit. +// +// Write 1 to shift the accumulator one bit to the right, 0 inserted at bit 39. +#define AUX_MAC_ACCSHIFT_LSR1 0x00000002 +#define AUX_MAC_ACCSHIFT_LSR1_BITN 1 +#define AUX_MAC_ACCSHIFT_LSR1_M 0x00000002 +#define AUX_MAC_ACCSHIFT_LSR1_S 1 + +// Field: [0] ASR1 +// +// Arithmetic shift right by 1 bit. +// +// Write 1 to shift the accumulator one bit to the right, previous sign bit +// inserted at bit 39. +#define AUX_MAC_ACCSHIFT_ASR1 0x00000001 +#define AUX_MAC_ACCSHIFT_ASR1_BITN 0 +#define AUX_MAC_ACCSHIFT_ASR1_M 0x00000001 +#define AUX_MAC_ACCSHIFT_ASR1_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACCRESET +// +//***************************************************************************** +// Field: [15:0] TRG +// +// Write any value to this register to trigger a reset of all bits in the +// accumulator. +#define AUX_MAC_ACCRESET_TRG_W 16 +#define AUX_MAC_ACCRESET_TRG_M 0x0000FFFF +#define AUX_MAC_ACCRESET_TRG_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC15_0 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 15:0. +// +// Write VALUE to initialize bits 15:0 of accumulator. +#define AUX_MAC_ACC15_0_VALUE_W 16 +#define AUX_MAC_ACC15_0_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC15_0_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC16_1 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 16:1. +#define AUX_MAC_ACC16_1_VALUE_W 16 +#define AUX_MAC_ACC16_1_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC16_1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC17_2 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 17:2. +#define AUX_MAC_ACC17_2_VALUE_W 16 +#define AUX_MAC_ACC17_2_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC17_2_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC18_3 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 18:3. +#define AUX_MAC_ACC18_3_VALUE_W 16 +#define AUX_MAC_ACC18_3_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC18_3_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC19_4 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 19:4. +#define AUX_MAC_ACC19_4_VALUE_W 16 +#define AUX_MAC_ACC19_4_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC19_4_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC20_5 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 20:5. +#define AUX_MAC_ACC20_5_VALUE_W 16 +#define AUX_MAC_ACC20_5_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC20_5_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC21_6 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 21:6. +#define AUX_MAC_ACC21_6_VALUE_W 16 +#define AUX_MAC_ACC21_6_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC21_6_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC22_7 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 22:7. +#define AUX_MAC_ACC22_7_VALUE_W 16 +#define AUX_MAC_ACC22_7_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC22_7_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC23_8 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 23:8. +#define AUX_MAC_ACC23_8_VALUE_W 16 +#define AUX_MAC_ACC23_8_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC23_8_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC24_9 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 24:9. +#define AUX_MAC_ACC24_9_VALUE_W 16 +#define AUX_MAC_ACC24_9_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC24_9_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC25_10 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 25:10. +#define AUX_MAC_ACC25_10_VALUE_W 16 +#define AUX_MAC_ACC25_10_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC25_10_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC26_11 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 26:11. +#define AUX_MAC_ACC26_11_VALUE_W 16 +#define AUX_MAC_ACC26_11_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC26_11_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC27_12 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 27:12. +#define AUX_MAC_ACC27_12_VALUE_W 16 +#define AUX_MAC_ACC27_12_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC27_12_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC28_13 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 28:13. +#define AUX_MAC_ACC28_13_VALUE_W 16 +#define AUX_MAC_ACC28_13_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC28_13_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC29_14 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 29:14. +#define AUX_MAC_ACC29_14_VALUE_W 16 +#define AUX_MAC_ACC29_14_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC29_14_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC30_15 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 30:15. +#define AUX_MAC_ACC30_15_VALUE_W 16 +#define AUX_MAC_ACC30_15_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC30_15_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC31_16 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 31:16. +// +// Write VALUE to initialize bits 31:16 of accumulator. +#define AUX_MAC_ACC31_16_VALUE_W 16 +#define AUX_MAC_ACC31_16_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC31_16_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC32_17 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 32:17. +#define AUX_MAC_ACC32_17_VALUE_W 16 +#define AUX_MAC_ACC32_17_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC32_17_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC33_18 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 33:18. +#define AUX_MAC_ACC33_18_VALUE_W 16 +#define AUX_MAC_ACC33_18_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC33_18_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC34_19 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 34:19. +#define AUX_MAC_ACC34_19_VALUE_W 16 +#define AUX_MAC_ACC34_19_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC34_19_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC35_20 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 35:20. +#define AUX_MAC_ACC35_20_VALUE_W 16 +#define AUX_MAC_ACC35_20_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC35_20_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC36_21 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 36:21. +#define AUX_MAC_ACC36_21_VALUE_W 16 +#define AUX_MAC_ACC36_21_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC36_21_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC37_22 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 37:22. +#define AUX_MAC_ACC37_22_VALUE_W 16 +#define AUX_MAC_ACC37_22_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC37_22_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC38_23 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 38:23. +#define AUX_MAC_ACC38_23_VALUE_W 16 +#define AUX_MAC_ACC38_23_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC38_23_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC39_24 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 39:24. +#define AUX_MAC_ACC39_24_VALUE_W 16 +#define AUX_MAC_ACC39_24_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC39_24_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC39_32 +// +//***************************************************************************** +// Field: [7:0] VALUE +// +// Value of the accumulator, bits 39:32. +// +// Write VALUE to initialize bits 39:32 of accumulator. +#define AUX_MAC_ACC39_32_VALUE_W 8 +#define AUX_MAC_ACC39_32_VALUE_M 0x000000FF +#define AUX_MAC_ACC39_32_VALUE_S 0 + + +#endif // __AUX_MAC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h new file mode 100644 index 0000000..427948a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* Filename: hw_aux_ram_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_RAM_H__ +#define __HW_AUX_RAM_H__ + + +#define AUX_RAM_O_BANK0 0x00000000 +#define AUX_RAM_BANK0_BYTE_SIZE 4096 + +#define AUX_RAM_TOT_BYTE_SIZE 4096 + + + +#endif // __HW_AUX_RAM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h new file mode 100644 index 0000000..5be902d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h @@ -0,0 +1,398 @@ +/****************************************************************************** +* Filename: hw_aux_sce_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SCE_H__ +#define __HW_AUX_SCE_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SCE component +// +//***************************************************************************** +// Internal +#define AUX_SCE_O_CTL 0x00000000 + +// Internal +#define AUX_SCE_O_FETCHSTAT 0x00000004 + +// Internal +#define AUX_SCE_O_CPUSTAT 0x00000008 + +// Internal +#define AUX_SCE_O_WUSTAT 0x0000000C + +// Internal +#define AUX_SCE_O_REG1_0 0x00000010 + +// Internal +#define AUX_SCE_O_REG3_2 0x00000014 + +// Internal +#define AUX_SCE_O_REG5_4 0x00000018 + +// Internal +#define AUX_SCE_O_REG7_6 0x0000001C + +// Internal +#define AUX_SCE_O_LOOPADDR 0x00000020 + +// Internal +#define AUX_SCE_O_LOOPCNT 0x00000024 + +//***************************************************************************** +// +// Register: AUX_SCE_O_CTL +// +//***************************************************************************** +// Field: [31:24] FORCE_EV_LOW +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_EV_LOW_W 8 +#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000 +#define AUX_SCE_CTL_FORCE_EV_LOW_S 24 + +// Field: [23:16] FORCE_EV_HIGH +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8 +#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000 +#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16 + +// Field: [15:8] RESET_VECTOR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_RESET_VECTOR_W 8 +#define AUX_SCE_CTL_RESET_VECTOR_M 0x0000FF00 +#define AUX_SCE_CTL_RESET_VECTOR_S 8 + +// Field: [6] DBG_FREEZE_EN +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6 +#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6 + +// Field: [5] FORCE_WU_LOW +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5 +#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_S 5 + +// Field: [4] FORCE_WU_HIGH +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4 +#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4 + +// Field: [3] RESTART +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_RESTART 0x00000008 +#define AUX_SCE_CTL_RESTART_BITN 3 +#define AUX_SCE_CTL_RESTART_M 0x00000008 +#define AUX_SCE_CTL_RESTART_S 3 + +// Field: [2] SINGLE_STEP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_SINGLE_STEP 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_BITN 2 +#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_S 2 + +// Field: [1] SUSPEND +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_SUSPEND 0x00000002 +#define AUX_SCE_CTL_SUSPEND_BITN 1 +#define AUX_SCE_CTL_SUSPEND_M 0x00000002 +#define AUX_SCE_CTL_SUSPEND_S 1 + +// Field: [0] CLK_EN +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_CLK_EN 0x00000001 +#define AUX_SCE_CTL_CLK_EN_BITN 0 +#define AUX_SCE_CTL_CLK_EN_M 0x00000001 +#define AUX_SCE_CTL_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_FETCHSTAT +// +//***************************************************************************** +// Field: [31:16] OPCODE +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_FETCHSTAT_OPCODE_W 16 +#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000 +#define AUX_SCE_FETCHSTAT_OPCODE_S 16 + +// Field: [15:0] PC +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_FETCHSTAT_PC_W 16 +#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF +#define AUX_SCE_FETCHSTAT_PC_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_CPUSTAT +// +//***************************************************************************** +// Field: [11] BUS_ERROR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11 +#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11 + +// Field: [10] SLEEP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_SLEEP 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_BITN 10 +#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_S 10 + +// Field: [9] WEV +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_WEV 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_BITN 9 +#define AUX_SCE_CPUSTAT_WEV_M 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_S 9 + +// Field: [8] HALTED +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_HALTED 0x00000100 +#define AUX_SCE_CPUSTAT_HALTED_BITN 8 +#define AUX_SCE_CPUSTAT_HALTED_M 0x00000100 +#define AUX_SCE_CPUSTAT_HALTED_S 8 + +// Field: [3] V_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3 +#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_S 3 + +// Field: [2] C_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2 +#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_S 2 + +// Field: [1] N_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1 +#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_S 1 + +// Field: [0] Z_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0 +#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_WUSTAT +// +//***************************************************************************** +// Field: [18:16] EXC_VECTOR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_EXC_VECTOR_W 3 +#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00070000 +#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16 + +// Field: [8] WU_SIGNAL +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8 +#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8 + +// Field: [7:0] EV_SIGNALS +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SCEWEV_PROG Internal. Only to be used through TI provided API. +// AUX_ADC_FIFO_NOT_EMPTY Internal. Only to be used through TI provided API. +// AUX_TIMER1_EV_OR_IDLE Internal. Only to be used through TI provided API. +// AUX_TIMER0_EV_OR_IDLE Internal. Only to be used through TI provided API. +// AUX_TDC_DONE Internal. Only to be used through TI provided API. +// AUX_COMPB Internal. Only to be used through TI provided API. +// AUX_COMPA Internal. Only to be used through TI provided API. +// AUX_PROG_DLY_IDLE Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8 +#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF +#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0 +#define AUX_SCE_WUSTAT_EV_SIGNALS_SCEWEV_PROG 0x00000080 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_ADC_FIFO_NOT_EMPTY 0x00000040 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TIMER1_EV_OR_IDLE 0x00000020 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TIMER0_EV_OR_IDLE 0x00000010 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TDC_DONE 0x00000008 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_COMPB 0x00000004 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_COMPA 0x00000002 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_PROG_DLY_IDLE 0x00000001 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG1_0 +// +//***************************************************************************** +// Field: [31:16] REG1 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG1_0_REG1_W 16 +#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000 +#define AUX_SCE_REG1_0_REG1_S 16 + +// Field: [15:0] REG0 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG1_0_REG0_W 16 +#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF +#define AUX_SCE_REG1_0_REG0_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG3_2 +// +//***************************************************************************** +// Field: [31:16] REG3 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG3_2_REG3_W 16 +#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000 +#define AUX_SCE_REG3_2_REG3_S 16 + +// Field: [15:0] REG2 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG3_2_REG2_W 16 +#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF +#define AUX_SCE_REG3_2_REG2_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG5_4 +// +//***************************************************************************** +// Field: [31:16] REG5 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG5_4_REG5_W 16 +#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000 +#define AUX_SCE_REG5_4_REG5_S 16 + +// Field: [15:0] REG4 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG5_4_REG4_W 16 +#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF +#define AUX_SCE_REG5_4_REG4_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG7_6 +// +//***************************************************************************** +// Field: [31:16] REG7 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG7_6_REG7_W 16 +#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000 +#define AUX_SCE_REG7_6_REG7_S 16 + +// Field: [15:0] REG6 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG7_6_REG6_W 16 +#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF +#define AUX_SCE_REG7_6_REG6_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_LOOPADDR +// +//***************************************************************************** +// Field: [31:16] STOP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPADDR_STOP_W 16 +#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000 +#define AUX_SCE_LOOPADDR_STOP_S 16 + +// Field: [15:0] START +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPADDR_START_W 16 +#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF +#define AUX_SCE_LOOPADDR_START_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_LOOPCNT +// +//***************************************************************************** +// Field: [7:0] ITER_LEFT +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8 +#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF +#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0 + + +#endif // __AUX_SCE__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h new file mode 100644 index 0000000..3f6555e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h @@ -0,0 +1,282 @@ +/****************************************************************************** +* Filename: hw_aux_smph_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SMPH_H__ +#define __HW_AUX_SMPH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SMPH component +// +//***************************************************************************** +// Semaphore 0 +#define AUX_SMPH_O_SMPH0 0x00000000 + +// Semaphore 1 +#define AUX_SMPH_O_SMPH1 0x00000004 + +// Semaphore 2 +#define AUX_SMPH_O_SMPH2 0x00000008 + +// Semaphore 3 +#define AUX_SMPH_O_SMPH3 0x0000000C + +// Semaphore 4 +#define AUX_SMPH_O_SMPH4 0x00000010 + +// Semaphore 5 +#define AUX_SMPH_O_SMPH5 0x00000014 + +// Semaphore 6 +#define AUX_SMPH_O_SMPH6 0x00000018 + +// Semaphore 7 +#define AUX_SMPH_O_SMPH7 0x0000001C + +// Auto Take +#define AUX_SMPH_O_AUTOTAKE 0x00000020 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH0_STAT 0x00000001 +#define AUX_SMPH_SMPH0_STAT_BITN 0 +#define AUX_SMPH_SMPH0_STAT_M 0x00000001 +#define AUX_SMPH_SMPH0_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH1_STAT 0x00000001 +#define AUX_SMPH_SMPH1_STAT_BITN 0 +#define AUX_SMPH_SMPH1_STAT_M 0x00000001 +#define AUX_SMPH_SMPH1_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH2_STAT 0x00000001 +#define AUX_SMPH_SMPH2_STAT_BITN 0 +#define AUX_SMPH_SMPH2_STAT_M 0x00000001 +#define AUX_SMPH_SMPH2_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH3_STAT 0x00000001 +#define AUX_SMPH_SMPH3_STAT_BITN 0 +#define AUX_SMPH_SMPH3_STAT_M 0x00000001 +#define AUX_SMPH_SMPH3_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH4_STAT 0x00000001 +#define AUX_SMPH_SMPH4_STAT_BITN 0 +#define AUX_SMPH_SMPH4_STAT_M 0x00000001 +#define AUX_SMPH_SMPH4_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH5_STAT 0x00000001 +#define AUX_SMPH_SMPH5_STAT_BITN 0 +#define AUX_SMPH_SMPH5_STAT_M 0x00000001 +#define AUX_SMPH_SMPH5_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH6_STAT 0x00000001 +#define AUX_SMPH_SMPH6_STAT_BITN 0 +#define AUX_SMPH_SMPH6_STAT_M 0x00000001 +#define AUX_SMPH_SMPH6_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH7_STAT 0x00000001 +#define AUX_SMPH_SMPH7_STAT_BITN 0 +#define AUX_SMPH_SMPH7_STAT_M 0x00000001 +#define AUX_SMPH_SMPH7_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_AUTOTAKE +// +//***************************************************************************** +// Field: [2:0] SMPH_ID +// +// Write the semaphore ID,0x0-0x7, to SMPH_ID to request this semaphore until +// it is granted. +// +// When semaphore SMPH_ID is granted, event +// AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE becomes 1. +// +// The event becomes 0 when software releases the semaphore or writes a new +// value to SMPH_ID. +// +// To avoid corrupted semaphores: +// - Usage of this functionality must be restricted to one CPU core. +// - Software must wait until AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE is 1 +// before it writes a new value to SMPH_ID. +#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0 + + +#endif // __AUX_SMPH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h new file mode 100644 index 0000000..baf3482 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h @@ -0,0 +1,239 @@ +/****************************************************************************** +* Filename: hw_aux_spim_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SPIM_H__ +#define __HW_AUX_SPIM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SPIM component +// +//***************************************************************************** +// SPI Master Configuration +#define AUX_SPIM_O_SPIMCFG 0x00000000 + +// MISO Configuration +#define AUX_SPIM_O_MISOCFG 0x00000004 + +// MOSI Control +#define AUX_SPIM_O_MOSICTL 0x00000008 + +// Transmit 8 Bit +#define AUX_SPIM_O_TX8 0x0000000C + +// Transmit 16 Bit +#define AUX_SPIM_O_TX16 0x00000010 + +// Receive 8 Bit +#define AUX_SPIM_O_RX8 0x00000014 + +// Receive 16 Bit +#define AUX_SPIM_O_RX16 0x00000018 + +// SCLK Idle +#define AUX_SPIM_O_SCLKIDLE 0x0000001C + +// Data Idle +#define AUX_SPIM_O_DATAIDLE 0x00000020 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_SPIMCFG +// +//***************************************************************************** +// Field: [7:2] DIV +// +// SCLK divider. +// +// Peripheral clock frequency division gives the SCLK clock frequency. The +// division factor equals (2 * (DIV+1)): +// +// 0x00: Divide by 2. +// 0x01: Divide by 4. +// 0x02: Divide by 6. +// ... +// 0x3F: Divide by 128. +#define AUX_SPIM_SPIMCFG_DIV_W 6 +#define AUX_SPIM_SPIMCFG_DIV_M 0x000000FC +#define AUX_SPIM_SPIMCFG_DIV_S 2 + +// Field: [1] PHA +// +// Phase of the MOSI and MISO data signals. +// +// 0: Sample MISO at leading (odd) edges and shift MOSI at trailing (even) +// edges of SCLK. +// 1: Sample MISO at trailing (even) edges and shift MOSI at leading (odd) +// edges of SCLK. +#define AUX_SPIM_SPIMCFG_PHA 0x00000002 +#define AUX_SPIM_SPIMCFG_PHA_BITN 1 +#define AUX_SPIM_SPIMCFG_PHA_M 0x00000002 +#define AUX_SPIM_SPIMCFG_PHA_S 1 + +// Field: [0] POL +// +// Polarity of the SCLK signal. +// +// 0: SCLK is low when idle, first clock edge rises. +// 1: SCLK is high when idle, first clock edge falls. +#define AUX_SPIM_SPIMCFG_POL 0x00000001 +#define AUX_SPIM_SPIMCFG_POL_BITN 0 +#define AUX_SPIM_SPIMCFG_POL_M 0x00000001 +#define AUX_SPIM_SPIMCFG_POL_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_MISOCFG +// +//***************************************************************************** +// Field: [4:0] AUXIO +// +// AUXIO to MISO mux. +// +// Select the AUXIO pin that connects to MISO. +#define AUX_SPIM_MISOCFG_AUXIO_W 5 +#define AUX_SPIM_MISOCFG_AUXIO_M 0x0000001F +#define AUX_SPIM_MISOCFG_AUXIO_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_MOSICTL +// +//***************************************************************************** +// Field: [0] VALUE +// +// MOSI level control. +// +// 0: Set MOSI low. +// 1: Set MOSI high. +#define AUX_SPIM_MOSICTL_VALUE 0x00000001 +#define AUX_SPIM_MOSICTL_VALUE_BITN 0 +#define AUX_SPIM_MOSICTL_VALUE_M 0x00000001 +#define AUX_SPIM_MOSICTL_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_TX8 +// +//***************************************************************************** +// Field: [7:0] DATA +// +// 8 bit data transfer. +// +// Write DATA to start transfer, MSB first. When transfer completes, MOSI stays +// at the value of LSB. +#define AUX_SPIM_TX8_DATA_W 8 +#define AUX_SPIM_TX8_DATA_M 0x000000FF +#define AUX_SPIM_TX8_DATA_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_TX16 +// +//***************************************************************************** +// Field: [15:0] DATA +// +// 16 bit data transfer. +// +// Write DATA to start transfer, MSB first. When transfer completes, MOSI stays +// at the value of LSB. +#define AUX_SPIM_TX16_DATA_W 16 +#define AUX_SPIM_TX16_DATA_M 0x0000FFFF +#define AUX_SPIM_TX16_DATA_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_RX8 +// +//***************************************************************************** +// Field: [7:0] DATA +// +// Latest 8 bits received on MISO. +#define AUX_SPIM_RX8_DATA_W 8 +#define AUX_SPIM_RX8_DATA_M 0x000000FF +#define AUX_SPIM_RX8_DATA_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_RX16 +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Latest 16 bits received on MISO. +#define AUX_SPIM_RX16_DATA_W 16 +#define AUX_SPIM_RX16_DATA_M 0x0000FFFF +#define AUX_SPIM_RX16_DATA_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_SCLKIDLE +// +//***************************************************************************** +// Field: [0] STAT +// +// Wait for SCLK idle. +// +// Read operation stalls until SCLK is idle with no remaining clock edges. Read +// then returns 1. +// +// AUX_SCE can use this to control CS deassertion. +#define AUX_SPIM_SCLKIDLE_STAT 0x00000001 +#define AUX_SPIM_SCLKIDLE_STAT_BITN 0 +#define AUX_SPIM_SCLKIDLE_STAT_M 0x00000001 +#define AUX_SPIM_SCLKIDLE_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_DATAIDLE +// +//***************************************************************************** +// Field: [0] STAT +// +// Wait for data idle. +// +// Read operation stalls until the SCLK period associated with LSB transmission +// completes. Read then returns 1. +// +// AUX_SCE can use this to control CS deassertion. +#define AUX_SPIM_DATAIDLE_STAT 0x00000001 +#define AUX_SPIM_DATAIDLE_STAT_BITN 0 +#define AUX_SPIM_DATAIDLE_STAT_M 0x00000001 +#define AUX_SPIM_DATAIDLE_STAT_S 0 + + +#endif // __AUX_SPIM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h new file mode 100644 index 0000000..8b7ab84 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h @@ -0,0 +1,2088 @@ +/****************************************************************************** +* Filename: hw_aux_sysif_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SYSIF_H__ +#define __HW_AUX_SYSIF_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SYSIF component +// +//***************************************************************************** +// Operational Mode Request +#define AUX_SYSIF_O_OPMODEREQ 0x00000000 + +// Operational Mode Acknowledgement +#define AUX_SYSIF_O_OPMODEACK 0x00000004 + +// Programmable Wakeup 0 Configuration +#define AUX_SYSIF_O_PROGWU0CFG 0x00000008 + +// Programmable Wakeup 1 Configuration +#define AUX_SYSIF_O_PROGWU1CFG 0x0000000C + +// Programmable Wakeup 2 Configuration +#define AUX_SYSIF_O_PROGWU2CFG 0x00000010 + +// Programmable Wakeup 3 Configuration +#define AUX_SYSIF_O_PROGWU3CFG 0x00000014 + +// Software Wakeup Triggers +#define AUX_SYSIF_O_SWWUTRIG 0x00000018 + +// Wakeup Flags +#define AUX_SYSIF_O_WUFLAGS 0x0000001C + +// Wakeup Flags Clear +#define AUX_SYSIF_O_WUFLAGSCLR 0x00000020 + +// Wakeup Gate +#define AUX_SYSIF_O_WUGATE 0x00000024 + +// Vector Configuration 0 +#define AUX_SYSIF_O_VECCFG0 0x00000028 + +// Vector Configuration 1 +#define AUX_SYSIF_O_VECCFG1 0x0000002C + +// Vector Configuration 2 +#define AUX_SYSIF_O_VECCFG2 0x00000030 + +// Vector Configuration 3 +#define AUX_SYSIF_O_VECCFG3 0x00000034 + +// Vector Configuration 4 +#define AUX_SYSIF_O_VECCFG4 0x00000038 + +// Vector Configuration 5 +#define AUX_SYSIF_O_VECCFG5 0x0000003C + +// Vector Configuration 6 +#define AUX_SYSIF_O_VECCFG6 0x00000040 + +// Vector Configuration 7 +#define AUX_SYSIF_O_VECCFG7 0x00000044 + +// Event Synchronization Rate +#define AUX_SYSIF_O_EVSYNCRATE 0x00000048 + +// Peripheral Operational Rate +#define AUX_SYSIF_O_PEROPRATE 0x0000004C + +// ADC Clock Control +#define AUX_SYSIF_O_ADCCLKCTL 0x00000050 + +// TDC Counter Clock Control +#define AUX_SYSIF_O_TDCCLKCTL 0x00000054 + +// TDC Reference Clock Control +#define AUX_SYSIF_O_TDCREFCLKCTL 0x00000058 + +// AUX_TIMER2 Clock Control +#define AUX_SYSIF_O_TIMER2CLKCTL 0x0000005C + +// AUX_TIMER2 Clock Status +#define AUX_SYSIF_O_TIMER2CLKSTAT 0x00000060 + +// AUX_TIMER2 Clock Switch +#define AUX_SYSIF_O_TIMER2CLKSWITCH 0x00000064 + +// AUX_TIMER2 Debug Control +#define AUX_SYSIF_O_TIMER2DBGCTL 0x00000068 + +// Clock Shift Detection +#define AUX_SYSIF_O_CLKSHIFTDET 0x00000070 + +// VDDR Recharge Trigger +#define AUX_SYSIF_O_RECHARGETRIG 0x00000074 + +// VDDR Recharge Detection +#define AUX_SYSIF_O_RECHARGEDET 0x00000078 + +// Real Time Counter Sub Second Increment 0 +#define AUX_SYSIF_O_RTCSUBSECINC0 0x0000007C + +// Real Time Counter Sub Second Increment 1 +#define AUX_SYSIF_O_RTCSUBSECINC1 0x00000080 + +// Real Time Counter Sub Second Increment Control +#define AUX_SYSIF_O_RTCSUBSECINCCTL 0x00000084 + +// Real Time Counter Second +#define AUX_SYSIF_O_RTCSEC 0x00000088 + +// Real Time Counter Sub-Second +#define AUX_SYSIF_O_RTCSUBSEC 0x0000008C + +// AON_RTC Event Clear +#define AUX_SYSIF_O_RTCEVCLR 0x00000090 + +// AON_BATMON Battery Voltage Value +#define AUX_SYSIF_O_BATMONBAT 0x00000094 + +// AON_BATMON Temperature Value +#define AUX_SYSIF_O_BATMONTEMP 0x0000009C + +// Timer Halt +#define AUX_SYSIF_O_TIMERHALT 0x000000A0 + +// AUX_TIMER2 Bridge +#define AUX_SYSIF_O_TIMER2BRIDGE 0x000000B0 + +// Software Power Profiler +#define AUX_SYSIF_O_SWPWRPROF 0x000000B4 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_OPMODEREQ +// +//***************************************************************************** +// Field: [1:0] REQ +// +// AUX operational mode request. +// ENUMs: +// PDLP Powerdown operational mode with wakeup to lowpower +// mode, characterized by: +// - Powerdown system power +// supply state (uLDO) request. +// - +// AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock +// frequency (SCE_RATE). +// - An active wakeup flag +// overrides the operational mode externally to +// lowpower (LP) as long as the flag is set. +// PDA Powerdown operational mode with wakeup to active +// mode, characterized by: +// - Powerdown system power +// supply state (uLDO) request. +// - +// AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock +// frequency (SCE_RATE). +// - An active wakeup flag +// overrides the operational mode externally to +// active (A) as long as the flag is set. +// LP Lowpower operational mode, characterized by: +// - Powerdown system power +// supply state (uLDO) request. +// - SCE clock frequency +// (SCE_RATE) equals SCLK_MF. +// - An active wakeup flag +// does not change operational mode. +// A Active operational mode, characterized by: +// - Active system power +// supply state (GLDO or DCDC) request. +// - AON_PMCTL:AUXSCECLK.SRC +// sets the SCE clock frequency (SCE_RATE). +// - An active wakeup flag +// does not change operational mode. +#define AUX_SYSIF_OPMODEREQ_REQ_W 2 +#define AUX_SYSIF_OPMODEREQ_REQ_M 0x00000003 +#define AUX_SYSIF_OPMODEREQ_REQ_S 0 +#define AUX_SYSIF_OPMODEREQ_REQ_PDLP 0x00000003 +#define AUX_SYSIF_OPMODEREQ_REQ_PDA 0x00000002 +#define AUX_SYSIF_OPMODEREQ_REQ_LP 0x00000001 +#define AUX_SYSIF_OPMODEREQ_REQ_A 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_OPMODEACK +// +//***************************************************************************** +// Field: [1:0] ACK +// +// AUX operational mode acknowledgement. +// ENUMs: +// PDLP Powerdown operational mode with wakeup to lowpower +// mode is acknowledged. +// PDA Powerdown operational mode with wakeup to active +// mode is acknowledged. +// LP Lowpower operational mode is acknowledged. +// A Active operational mode is acknowledged. +#define AUX_SYSIF_OPMODEACK_ACK_W 2 +#define AUX_SYSIF_OPMODEACK_ACK_M 0x00000003 +#define AUX_SYSIF_OPMODEACK_ACK_S 0 +#define AUX_SYSIF_OPMODEACK_ACK_PDLP 0x00000003 +#define AUX_SYSIF_OPMODEACK_ACK_PDA 0x00000002 +#define AUX_SYSIF_OPMODEACK_ACK_LP 0x00000001 +#define AUX_SYSIF_OPMODEACK_ACK_A 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_PROGWU0CFG +// +//***************************************************************************** +// Field: [7] POL +// +// Polarity of WU_SRC. +// +// The procedure used to clear the wakeup flag decides level or edge +// sensitivity, see WUFLAGSCLR.PROG_WU0. +// ENUMs: +// LOW The wakeup flag is set when WU_SRC is low or goes +// low. +// HIGH The wakeup flag is set when WU_SRC is high or goes +// high. +#define AUX_SYSIF_PROGWU0CFG_POL 0x00000080 +#define AUX_SYSIF_PROGWU0CFG_POL_BITN 7 +#define AUX_SYSIF_PROGWU0CFG_POL_M 0x00000080 +#define AUX_SYSIF_PROGWU0CFG_POL_S 7 +#define AUX_SYSIF_PROGWU0CFG_POL_LOW 0x00000080 +#define AUX_SYSIF_PROGWU0CFG_POL_HIGH 0x00000000 + +// Field: [6] EN +// +// Programmable wakeup flag enable. +// +// 0: Disable wakeup flag. +// 1: Enable wakeup flag. +#define AUX_SYSIF_PROGWU0CFG_EN 0x00000040 +#define AUX_SYSIF_PROGWU0CFG_EN_BITN 6 +#define AUX_SYSIF_PROGWU0CFG_EN_M 0x00000040 +#define AUX_SYSIF_PROGWU0CFG_EN_S 6 + +// Field: [5:0] WU_SRC +// +// Wakeup source from the asynchronous AUX event bus. +// +// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU0 is 1. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_W 6 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_M 0x0000003F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_S 0 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_NO_EVENT 0x0000003F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPB 0x0000002F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPA 0x0000002E +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_EV 0x0000002B +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_ACLK_REF 0x0000002A +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_ACTIVE 0x00000028 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_PWR_DWN 0x00000027 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_SCLK_LF 0x00000026 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2 0x00000021 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MANUAL_EV 0x00000020 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO31 0x0000001F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO30 0x0000001E +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO29 0x0000001D +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO28 0x0000001C +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO27 0x0000001B +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO26 0x0000001A +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO25 0x00000019 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO24 0x00000018 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO23 0x00000017 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO22 0x00000016 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO21 0x00000015 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO20 0x00000014 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO19 0x00000013 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO18 0x00000012 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO17 0x00000011 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO16 0x00000010 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO15 0x0000000F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO14 0x0000000E +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO13 0x0000000D +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO12 0x0000000C +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO11 0x0000000B +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO10 0x0000000A +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO9 0x00000009 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO8 0x00000008 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO7 0x00000007 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO6 0x00000006 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO5 0x00000005 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO4 0x00000004 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO3 0x00000003 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO2 0x00000002 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO1 0x00000001 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_PROGWU1CFG +// +//***************************************************************************** +// Field: [7] POL +// +// Polarity of WU_SRC. +// +// The procedure used to clear the wakeup flag decides level or edge +// sensitivity, see WUFLAGSCLR.PROG_WU1. +// ENUMs: +// LOW The wakeup flag is set when WU_SRC is low or goes +// low. +// HIGH The wakeup flag is set when WU_SRC is high or goes +// high. +#define AUX_SYSIF_PROGWU1CFG_POL 0x00000080 +#define AUX_SYSIF_PROGWU1CFG_POL_BITN 7 +#define AUX_SYSIF_PROGWU1CFG_POL_M 0x00000080 +#define AUX_SYSIF_PROGWU1CFG_POL_S 7 +#define AUX_SYSIF_PROGWU1CFG_POL_LOW 0x00000080 +#define AUX_SYSIF_PROGWU1CFG_POL_HIGH 0x00000000 + +// Field: [6] EN +// +// Programmable wakeup flag enable. +// +// 0: Disable wakeup flag. +// 1: Enable wakeup flag. +#define AUX_SYSIF_PROGWU1CFG_EN 0x00000040 +#define AUX_SYSIF_PROGWU1CFG_EN_BITN 6 +#define AUX_SYSIF_PROGWU1CFG_EN_M 0x00000040 +#define AUX_SYSIF_PROGWU1CFG_EN_S 6 + +// Field: [5:0] WU_SRC +// +// Wakeup source from the asynchronous AUX event bus. +// +// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU1 is 1. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_W 6 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_M 0x0000003F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_S 0 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_NO_EVENT 0x0000003F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPB 0x0000002F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPA 0x0000002E +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_EV 0x0000002B +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_ACLK_REF 0x0000002A +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_ACTIVE 0x00000028 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_PWR_DWN 0x00000027 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_SCLK_LF 0x00000026 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2 0x00000021 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MANUAL_EV 0x00000020 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO31 0x0000001F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO30 0x0000001E +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO29 0x0000001D +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO28 0x0000001C +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO27 0x0000001B +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO26 0x0000001A +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO25 0x00000019 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO24 0x00000018 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO23 0x00000017 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO22 0x00000016 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO21 0x00000015 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO20 0x00000014 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO19 0x00000013 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO18 0x00000012 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO17 0x00000011 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO16 0x00000010 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO15 0x0000000F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO14 0x0000000E +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO13 0x0000000D +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO12 0x0000000C +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO11 0x0000000B +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO10 0x0000000A +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO9 0x00000009 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO8 0x00000008 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO7 0x00000007 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO6 0x00000006 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO5 0x00000005 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO4 0x00000004 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO3 0x00000003 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO2 0x00000002 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO1 0x00000001 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_PROGWU2CFG +// +//***************************************************************************** +// Field: [7] POL +// +// Polarity of WU_SRC. +// +// The procedure used to clear the wakeup flag decides level or edge +// sensitivity, see WUFLAGSCLR.PROG_WU2. +// ENUMs: +// LOW The wakeup flag is set when WU_SRC is low or goes +// low. +// HIGH The wakeup flag is set when WU_SRC is high or goes +// high. +#define AUX_SYSIF_PROGWU2CFG_POL 0x00000080 +#define AUX_SYSIF_PROGWU2CFG_POL_BITN 7 +#define AUX_SYSIF_PROGWU2CFG_POL_M 0x00000080 +#define AUX_SYSIF_PROGWU2CFG_POL_S 7 +#define AUX_SYSIF_PROGWU2CFG_POL_LOW 0x00000080 +#define AUX_SYSIF_PROGWU2CFG_POL_HIGH 0x00000000 + +// Field: [6] EN +// +// Programmable wakeup flag enable. +// +// 0: Disable wakeup flag. +// 1: Enable wakeup flag. +#define AUX_SYSIF_PROGWU2CFG_EN 0x00000040 +#define AUX_SYSIF_PROGWU2CFG_EN_BITN 6 +#define AUX_SYSIF_PROGWU2CFG_EN_M 0x00000040 +#define AUX_SYSIF_PROGWU2CFG_EN_S 6 + +// Field: [5:0] WU_SRC +// +// Wakeup source from the asynchronous AUX event bus. +// +// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU2 is 1. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_W 6 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_M 0x0000003F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_S 0 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_NO_EVENT 0x0000003F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPB 0x0000002F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPA 0x0000002E +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_EV 0x0000002B +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_ACLK_REF 0x0000002A +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_ACTIVE 0x00000028 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_PWR_DWN 0x00000027 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_SCLK_LF 0x00000026 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2 0x00000021 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MANUAL_EV 0x00000020 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO31 0x0000001F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO30 0x0000001E +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO29 0x0000001D +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO28 0x0000001C +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO27 0x0000001B +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO26 0x0000001A +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO25 0x00000019 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO24 0x00000018 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO23 0x00000017 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO22 0x00000016 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO21 0x00000015 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO20 0x00000014 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO19 0x00000013 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO18 0x00000012 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO17 0x00000011 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO16 0x00000010 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO15 0x0000000F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO14 0x0000000E +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO13 0x0000000D +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO12 0x0000000C +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO11 0x0000000B +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO10 0x0000000A +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO9 0x00000009 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO8 0x00000008 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO7 0x00000007 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO6 0x00000006 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO5 0x00000005 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO4 0x00000004 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO3 0x00000003 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO2 0x00000002 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO1 0x00000001 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_PROGWU3CFG +// +//***************************************************************************** +// Field: [7] POL +// +// Polarity of WU_SRC. +// +// The procedure used to clear the wakeup flag decides level or edge +// sensitivity, see WUFLAGSCLR.PROG_WU3. +// ENUMs: +// LOW The wakeup flag is set when WU_SRC is low or goes +// low. +// HIGH The wakeup flag is set when WU_SRC is high or goes +// high. +#define AUX_SYSIF_PROGWU3CFG_POL 0x00000080 +#define AUX_SYSIF_PROGWU3CFG_POL_BITN 7 +#define AUX_SYSIF_PROGWU3CFG_POL_M 0x00000080 +#define AUX_SYSIF_PROGWU3CFG_POL_S 7 +#define AUX_SYSIF_PROGWU3CFG_POL_LOW 0x00000080 +#define AUX_SYSIF_PROGWU3CFG_POL_HIGH 0x00000000 + +// Field: [6] EN +// +// Programmable wakeup flag enable. +// +// 0: Disable wakeup flag. +// 1: Enable wakeup flag. +#define AUX_SYSIF_PROGWU3CFG_EN 0x00000040 +#define AUX_SYSIF_PROGWU3CFG_EN_BITN 6 +#define AUX_SYSIF_PROGWU3CFG_EN_M 0x00000040 +#define AUX_SYSIF_PROGWU3CFG_EN_S 6 + +// Field: [5:0] WU_SRC +// +// Wakeup source from the asynchronous AUX event bus. +// +// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU3 is 1. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_W 6 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_M 0x0000003F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_S 0 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_NO_EVENT 0x0000003F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPB 0x0000002F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPA 0x0000002E +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_EV 0x0000002B +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_ACLK_REF 0x0000002A +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_ACTIVE 0x00000028 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_PWR_DWN 0x00000027 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_SCLK_LF 0x00000026 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2 0x00000021 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MANUAL_EV 0x00000020 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO31 0x0000001F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO30 0x0000001E +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO29 0x0000001D +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO28 0x0000001C +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO27 0x0000001B +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO26 0x0000001A +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO25 0x00000019 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO24 0x00000018 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO23 0x00000017 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO22 0x00000016 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO21 0x00000015 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO20 0x00000014 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO19 0x00000013 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO18 0x00000012 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO17 0x00000011 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO16 0x00000010 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO15 0x0000000F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO14 0x0000000E +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO13 0x0000000D +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO12 0x0000000C +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO11 0x0000000B +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO10 0x0000000A +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO9 0x00000009 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO8 0x00000008 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO7 0x00000007 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO6 0x00000006 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO5 0x00000005 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO4 0x00000004 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO3 0x00000003 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO2 0x00000002 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO1 0x00000001 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_SWWUTRIG +// +//***************************************************************************** +// Field: [3] SW_WU3 +// +// Software wakeup 3 trigger. +// +// 0: No effect. +// 1: Set WUFLAGS.SW_WU3 and trigger AUX wakeup. +#define AUX_SYSIF_SWWUTRIG_SW_WU3 0x00000008 +#define AUX_SYSIF_SWWUTRIG_SW_WU3_BITN 3 +#define AUX_SYSIF_SWWUTRIG_SW_WU3_M 0x00000008 +#define AUX_SYSIF_SWWUTRIG_SW_WU3_S 3 + +// Field: [2] SW_WU2 +// +// Software wakeup 2 trigger. +// +// 0: No effect. +// 1: Set WUFLAGS.SW_WU2 and trigger AUX wakeup. +#define AUX_SYSIF_SWWUTRIG_SW_WU2 0x00000004 +#define AUX_SYSIF_SWWUTRIG_SW_WU2_BITN 2 +#define AUX_SYSIF_SWWUTRIG_SW_WU2_M 0x00000004 +#define AUX_SYSIF_SWWUTRIG_SW_WU2_S 2 + +// Field: [1] SW_WU1 +// +// Software wakeup 1 trigger. +// +// 0: No effect. +// 1: Set WUFLAGS.SW_WU1 and trigger AUX wakeup. +#define AUX_SYSIF_SWWUTRIG_SW_WU1 0x00000002 +#define AUX_SYSIF_SWWUTRIG_SW_WU1_BITN 1 +#define AUX_SYSIF_SWWUTRIG_SW_WU1_M 0x00000002 +#define AUX_SYSIF_SWWUTRIG_SW_WU1_S 1 + +// Field: [0] SW_WU0 +// +// Software wakeup 0 trigger. +// +// 0: No effect. +// 1: Set WUFLAGS.SW_WU0 and trigger AUX wakeup. +#define AUX_SYSIF_SWWUTRIG_SW_WU0 0x00000001 +#define AUX_SYSIF_SWWUTRIG_SW_WU0_BITN 0 +#define AUX_SYSIF_SWWUTRIG_SW_WU0_M 0x00000001 +#define AUX_SYSIF_SWWUTRIG_SW_WU0_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_WUFLAGS +// +//***************************************************************************** +// Field: [7] SW_WU3 +// +// Software wakeup 3 flag. +// +// 0: Software wakeup 3 not triggered. +// 1: Software wakeup 3 triggered. +#define AUX_SYSIF_WUFLAGS_SW_WU3 0x00000080 +#define AUX_SYSIF_WUFLAGS_SW_WU3_BITN 7 +#define AUX_SYSIF_WUFLAGS_SW_WU3_M 0x00000080 +#define AUX_SYSIF_WUFLAGS_SW_WU3_S 7 + +// Field: [6] SW_WU2 +// +// Software wakeup 2 flag. +// +// 0: Software wakeup 2 not triggered. +// 1: Software wakeup 2 triggered. +#define AUX_SYSIF_WUFLAGS_SW_WU2 0x00000040 +#define AUX_SYSIF_WUFLAGS_SW_WU2_BITN 6 +#define AUX_SYSIF_WUFLAGS_SW_WU2_M 0x00000040 +#define AUX_SYSIF_WUFLAGS_SW_WU2_S 6 + +// Field: [5] SW_WU1 +// +// Software wakeup 1 flag. +// +// 0: Software wakeup 1 not triggered. +// 1: Software wakeup 1 triggered. +#define AUX_SYSIF_WUFLAGS_SW_WU1 0x00000020 +#define AUX_SYSIF_WUFLAGS_SW_WU1_BITN 5 +#define AUX_SYSIF_WUFLAGS_SW_WU1_M 0x00000020 +#define AUX_SYSIF_WUFLAGS_SW_WU1_S 5 + +// Field: [4] SW_WU0 +// +// Software wakeup 0 flag. +// +// 0: Software wakeup 0 not triggered. +// 1: Software wakeup 0 triggered. +#define AUX_SYSIF_WUFLAGS_SW_WU0 0x00000010 +#define AUX_SYSIF_WUFLAGS_SW_WU0_BITN 4 +#define AUX_SYSIF_WUFLAGS_SW_WU0_M 0x00000010 +#define AUX_SYSIF_WUFLAGS_SW_WU0_S 4 + +// Field: [3] PROG_WU3 +// +// Programmable wakeup 3. +// +// 0: Programmable wakeup 3 not triggered. +// 1: Programmable wakeup 3 triggered. +#define AUX_SYSIF_WUFLAGS_PROG_WU3 0x00000008 +#define AUX_SYSIF_WUFLAGS_PROG_WU3_BITN 3 +#define AUX_SYSIF_WUFLAGS_PROG_WU3_M 0x00000008 +#define AUX_SYSIF_WUFLAGS_PROG_WU3_S 3 + +// Field: [2] PROG_WU2 +// +// Programmable wakeup 2. +// +// 0: Programmable wakeup 2 not triggered. +// 1: Programmable wakeup 2 triggered. +#define AUX_SYSIF_WUFLAGS_PROG_WU2 0x00000004 +#define AUX_SYSIF_WUFLAGS_PROG_WU2_BITN 2 +#define AUX_SYSIF_WUFLAGS_PROG_WU2_M 0x00000004 +#define AUX_SYSIF_WUFLAGS_PROG_WU2_S 2 + +// Field: [1] PROG_WU1 +// +// Programmable wakeup 1. +// +// 0: Programmable wakeup 1 not triggered. +// 1: Programmable wakeup 1 triggered. +#define AUX_SYSIF_WUFLAGS_PROG_WU1 0x00000002 +#define AUX_SYSIF_WUFLAGS_PROG_WU1_BITN 1 +#define AUX_SYSIF_WUFLAGS_PROG_WU1_M 0x00000002 +#define AUX_SYSIF_WUFLAGS_PROG_WU1_S 1 + +// Field: [0] PROG_WU0 +// +// Programmable wakeup 0. +// +// 0: Programmable wakeup 0 not triggered. +// 1: Programmable wakeup 0 triggered. +#define AUX_SYSIF_WUFLAGS_PROG_WU0 0x00000001 +#define AUX_SYSIF_WUFLAGS_PROG_WU0_BITN 0 +#define AUX_SYSIF_WUFLAGS_PROG_WU0_M 0x00000001 +#define AUX_SYSIF_WUFLAGS_PROG_WU0_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_WUFLAGSCLR +// +//***************************************************************************** +// Field: [7] SW_WU3 +// +// Clear software wakeup flag 3. +// +// 0: No effect. +// 1: Clear WUFLAGS.SW_WU3. Keep high until WUFLAGS.SW_WU3 is 0. +#define AUX_SYSIF_WUFLAGSCLR_SW_WU3 0x00000080 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_BITN 7 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_M 0x00000080 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_S 7 + +// Field: [6] SW_WU2 +// +// Clear software wakeup flag 2. +// +// 0: No effect. +// 1: Clear WUFLAGS.SW_WU2. Keep high until WUFLAGS.SW_WU2 is 0. +#define AUX_SYSIF_WUFLAGSCLR_SW_WU2 0x00000040 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_BITN 6 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_M 0x00000040 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_S 6 + +// Field: [5] SW_WU1 +// +// Clear software wakeup flag 1. +// +// 0: No effect. +// 1: Clear WUFLAGS.SW_WU1. Keep high until WUFLAGS.SW_WU1 is 0. +#define AUX_SYSIF_WUFLAGSCLR_SW_WU1 0x00000020 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_BITN 5 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_M 0x00000020 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_S 5 + +// Field: [4] SW_WU0 +// +// Clear software wakeup flag 0. +// +// 0: No effect. +// 1: Clear WUFLAGS.SW_WU0. Keep high until WUFLAGS.SW_WU0 is 0. +#define AUX_SYSIF_WUFLAGSCLR_SW_WU0 0x00000010 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_BITN 4 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_M 0x00000010 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_S 4 + +// Field: [3] PROG_WU3 +// +// Programmable wakeup flag 3. +// +// 0: No effect. +// 1: Clear WUFLAGS.PROG_WU3. Keep high until WUFLAGS.PROG_WU3 is 0. +// +// The wakeup flag becomes edge sensitive if you write PROG_WU3 to 0 when +// PROGWU3CFG.EN is 1. +// The wakeup flag becomes level sensitive if you write PROG_WU3 to 0 when +// PROGWU3CFG.EN is 0, then set PROGWU3CFG.EN. +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3 0x00000008 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_BITN 3 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_M 0x00000008 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_S 3 + +// Field: [2] PROG_WU2 +// +// Programmable wakeup flag 2. +// +// 0: No effect. +// 1: Clear WUFLAGS.PROG_WU2. Keep high until WUFLAGS.PROG_WU2 is 0. +// +// The wakeup flag becomes edge sensitive if you write PROG_WU2 to 0 when +// PROGWU2CFG.EN is 1. +// The wakeup flag becomes level sensitive if you write PROG_WU2 to 0 when +// PROGWU2CFG.EN is 0, then set PROGWU2CFG.EN. +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2 0x00000004 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_BITN 2 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_M 0x00000004 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_S 2 + +// Field: [1] PROG_WU1 +// +// Programmable wakeup flag 1. +// +// 0: No effect. +// 1: Clear WUFLAGS.PROG_WU1. Keep high until WUFLAGS.PROG_WU1 is 0. +// +// The wakeup flag becomes edge sensitive if you write PROG_WU1 to 0 when +// PROGWU1CFG.EN is 1. +// The wakeup flag becomes level sensitive if you write PROG_WU1 to 0 when +// PROGWU1CFG.EN is 0, then set PROGWU1CFG.EN. +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1 0x00000002 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_BITN 1 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_M 0x00000002 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_S 1 + +// Field: [0] PROG_WU0 +// +// Programmable wakeup flag 0. +// +// 0: No effect. +// 1: Clear WUFLAGS.PROG_WU0. Keep high until WUFLAGS.PROG_WU0 is 0. +// +// The wakeup flag becomes edge sensitive if you write PROG_WU0 to 0 when +// PROGWU0CFG.EN is 1. +// The wakeup flag becomes level sensitive if you write PROG_WU0 to 0 when +// PROGWU0CFG.EN is 0, then set PROGWU0CFG.EN. +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0 0x00000001 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_BITN 0 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_M 0x00000001 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_WUGATE +// +//***************************************************************************** +// Field: [0] EN +// +// Wakeup output enable. +// +// 0: Disable AUX wakeup output. +// 1: Enable AUX wakeup output. +#define AUX_SYSIF_WUGATE_EN 0x00000001 +#define AUX_SYSIF_WUGATE_EN_BITN 0 +#define AUX_SYSIF_WUGATE_EN_M 0x00000001 +#define AUX_SYSIF_WUGATE_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG0 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 0. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG0_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG0_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG0_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG0_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG0_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG1 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 1. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG1_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG1_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG1_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG1_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG1_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG2 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 2. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG2_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG2_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG2_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG2_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG2_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG3 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 3. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG3_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG3_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG3_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG3_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG3_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG4 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 4. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG4_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG4_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG4_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG4_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG4_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG5 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 5. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG5_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG5_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG5_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG5_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG5_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG6 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 6. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG6_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG6_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG6_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG6_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG6_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG7 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 7. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG7_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG7_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG7_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG7_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG7_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_EVSYNCRATE +// +//***************************************************************************** +// Field: [2] AUX_COMPA_SYNC_RATE +// +// Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPA event. +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE 0x00000004 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_BITN 2 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_M 0x00000004 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_S 2 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_BUS_RATE 0x00000004 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_SCE_RATE 0x00000000 + +// Field: [1] AUX_COMPB_SYNC_RATE +// +// Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPB event. +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE 0x00000002 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_BITN 1 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_M 0x00000002 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_S 1 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_BUS_RATE 0x00000002 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_SCE_RATE 0x00000000 + +// Field: [0] AUX_TIMER2_SYNC_RATE +// +// Select synchronization rate for: +// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE 0x00000001 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_BITN 0 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_M 0x00000001 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_S 0 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_BUS_RATE 0x00000001 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_SCE_RATE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_PEROPRATE +// +//***************************************************************************** +// Field: [3] ANAIF_DAC_OP_RATE +// +// Select operational rate for AUX_ANAIF DAC sample clock state machine. +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE 0x00000008 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BITN 3 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_M 0x00000008 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_S 3 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BUS_RATE 0x00000008 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_SCE_RATE 0x00000000 + +// Field: [2] TIMER01_OP_RATE +// +// Select operational rate for AUX_TIMER01. +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE 0x00000004 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_BITN 2 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_M 0x00000004 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_S 2 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_BUS_RATE 0x00000004 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_SCE_RATE 0x00000000 + +// Field: [1] SPIM_OP_RATE +// +// Select operational rate for AUX_SPIM. +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE 0x00000002 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_BITN 1 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_M 0x00000002 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_S 1 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_BUS_RATE 0x00000002 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_SCE_RATE 0x00000000 + +// Field: [0] MAC_OP_RATE +// +// Select operational rate for AUX_MAC. +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE 0x00000001 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_BITN 0 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_M 0x00000001 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_S 0 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_BUS_RATE 0x00000001 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_SCE_RATE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_ADCCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// Clock acknowledgement. +// +// 0: ADC clock is disabled. +// 1: ADC clock is enabled. +#define AUX_SYSIF_ADCCLKCTL_ACK 0x00000002 +#define AUX_SYSIF_ADCCLKCTL_ACK_BITN 1 +#define AUX_SYSIF_ADCCLKCTL_ACK_M 0x00000002 +#define AUX_SYSIF_ADCCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// ADC clock request. +// +// 0: Disable ADC clock. +// 1: Enable ADC clock. +// +// Only modify REQ when equal to ACK. +#define AUX_SYSIF_ADCCLKCTL_REQ 0x00000001 +#define AUX_SYSIF_ADCCLKCTL_REQ_BITN 0 +#define AUX_SYSIF_ADCCLKCTL_REQ_M 0x00000001 +#define AUX_SYSIF_ADCCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TDCCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// TDC counter clock acknowledgement. +// +// 0: TDC counter clock is disabled. +// 1: TDC counter clock is enabled. +#define AUX_SYSIF_TDCCLKCTL_ACK 0x00000002 +#define AUX_SYSIF_TDCCLKCTL_ACK_BITN 1 +#define AUX_SYSIF_TDCCLKCTL_ACK_M 0x00000002 +#define AUX_SYSIF_TDCCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// TDC counter clock request. +// +// 0: Disable TDC counter clock. +// 1: Enable TDC counter clock. +// +// Only modify REQ when equal to ACK. +#define AUX_SYSIF_TDCCLKCTL_REQ 0x00000001 +#define AUX_SYSIF_TDCCLKCTL_REQ_BITN 0 +#define AUX_SYSIF_TDCCLKCTL_REQ_M 0x00000001 +#define AUX_SYSIF_TDCCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TDCREFCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// TDC reference clock acknowledgement. +// +// 0: TDC reference clock is disabled. +// 1: TDC reference clock is enabled. +#define AUX_SYSIF_TDCREFCLKCTL_ACK 0x00000002 +#define AUX_SYSIF_TDCREFCLKCTL_ACK_BITN 1 +#define AUX_SYSIF_TDCREFCLKCTL_ACK_M 0x00000002 +#define AUX_SYSIF_TDCREFCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// TDC reference clock request. +// +// 0: Disable TDC reference clock. +// 1: Enable TDC reference clock. +// +// Only modify REQ when equal to ACK. +#define AUX_SYSIF_TDCREFCLKCTL_REQ 0x00000001 +#define AUX_SYSIF_TDCREFCLKCTL_REQ_BITN 0 +#define AUX_SYSIF_TDCREFCLKCTL_REQ_M 0x00000001 +#define AUX_SYSIF_TDCREFCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TIMER2CLKCTL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select clock source for AUX_TIMER2. +// +// Update is only accepted if SRC equals TIMER2CLKSTAT.STAT or +// TIMER2CLKSWITCH.RDY is 1. +// +// It is recommended to select NONE only when TIMER2BRIDGE.BUSY is 0. +// +// A non-enumerated value is ignored. +// ENUMs: +// SCLK_HFDIV2 SCLK_HF / 2 +// SCLK_MF SCLK_MF +// SCLK_LF SCLK_LF +// NONE no clock +#define AUX_SYSIF_TIMER2CLKCTL_SRC_W 3 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_M 0x00000007 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_S 0 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_HFDIV2 0x00000004 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_MF 0x00000002 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_LF 0x00000001 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TIMER2CLKSTAT +// +//***************************************************************************** +// Field: [2:0] STAT +// +// AUX_TIMER2 clock source status. +// ENUMs: +// SCLK_HFDIV2 SCLK_HF / 2 +// SCLK_MF SCLK_MF +// SCLK_LF SCLK_LF +// NONE No clock +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_W 3 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_M 0x00000007 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_S 0 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_HFDIV2 0x00000004 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_MF 0x00000002 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_LF 0x00000001 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TIMER2CLKSWITCH +// +//***************************************************************************** +// Field: [0] RDY +// +// Status of clock switcher. +// +// 0: TIMER2CLKCTL.SRC is different from TIMER2CLKSTAT.STAT. +// 1: TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT. +// +// RDY connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY. +#define AUX_SYSIF_TIMER2CLKSWITCH_RDY 0x00000001 +#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_BITN 0 +#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_M 0x00000001 +#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TIMER2DBGCTL +// +//***************************************************************************** +// Field: [0] DBG_FREEZE_EN +// +// Debug freeze enable. +// +// 0: AUX_TIMER2 does not halt when the system CPU halts in debug mode. +// 1: Halt AUX_TIMER2 when the system CPU halts in debug mode. +#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN 0x00000001 +#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_BITN 0 +#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_M 0x00000001 +#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_CLKSHIFTDET +// +//***************************************************************************** +// Field: [0] STAT +// +// Clock shift detection. +// +// Write: +// +// 0: Restart clock shift detection. +// 1: Do not use. +// +// Read: +// +// 0: MCU domain did not enter or exit active state since you wrote 0 to STAT. +// 1: MCU domain entered or exited active state since you wrote 0 to STAT. +#define AUX_SYSIF_CLKSHIFTDET_STAT 0x00000001 +#define AUX_SYSIF_CLKSHIFTDET_STAT_BITN 0 +#define AUX_SYSIF_CLKSHIFTDET_STAT_M 0x00000001 +#define AUX_SYSIF_CLKSHIFTDET_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RECHARGETRIG +// +//***************************************************************************** +// Field: [0] TRIG +// +// Recharge trigger. +// +// 0: No effect. +// 1: Request VDDR recharge. +// +// Request VDDR recharge only when AUX_EVCTL:EVSTAT2.PWR_DWN is 1. +// +// Follow this sequence when OPMODEREQ.REQ is LP: +// - Set TRIG. +// - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 1. +// - Clear TRIG. +// - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 0. +// +// Follow this sequence when OPMODEREQ.REQ is PDA or PDLP: +// - Set TRIG. +// - Clear TRIG. +#define AUX_SYSIF_RECHARGETRIG_TRIG 0x00000001 +#define AUX_SYSIF_RECHARGETRIG_TRIG_BITN 0 +#define AUX_SYSIF_RECHARGETRIG_TRIG_M 0x00000001 +#define AUX_SYSIF_RECHARGETRIG_TRIG_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RECHARGEDET +// +//***************************************************************************** +// Field: [1] STAT +// +// VDDR recharge detector status. +// +// 0: No recharge of VDDR has occurred since EN was set. +// 1: Recharge of VDDR has occurred since EN was set. +#define AUX_SYSIF_RECHARGEDET_STAT 0x00000002 +#define AUX_SYSIF_RECHARGEDET_STAT_BITN 1 +#define AUX_SYSIF_RECHARGEDET_STAT_M 0x00000002 +#define AUX_SYSIF_RECHARGEDET_STAT_S 1 + +// Field: [0] EN +// +// VDDR recharge detector enable. +// +// 0: Disable recharge detection. STAT becomes zero. +// 1: Enable recharge detection. +#define AUX_SYSIF_RECHARGEDET_EN 0x00000001 +#define AUX_SYSIF_RECHARGEDET_EN_BITN 0 +#define AUX_SYSIF_RECHARGEDET_EN_M 0x00000001 +#define AUX_SYSIF_RECHARGEDET_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RTCSUBSECINC0 +// +//***************************************************************************** +// Field: [15:0] INC15_0 +// +// New value for bits 15:0 in AON_RTC:SUBSECINC. +#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_W 16 +#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_M 0x0000FFFF +#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RTCSUBSECINC1 +// +//***************************************************************************** +// Field: [7:0] INC23_16 +// +// New value for bits 23:16 in AON_RTC:SUBSECINC. +#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_W 8 +#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_M 0x000000FF +#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RTCSUBSECINCCTL +// +//***************************************************************************** +// Field: [1] UPD_ACK +// +// Update acknowledgement. +// +// 0: AON_RTC has not acknowledged UPD_REQ. +// 1: AON_RTC has acknowledged UPD_REQ. +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK 0x00000002 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN 1 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_S 1 + +// Field: [0] UPD_REQ +// +// Request AON_RTC to update AON_RTC:SUBSECINC. +// +// 0: Clear request to update. +// 1: Set request to update. +// +// Only change UPD_REQ when it equals UPD_ACK. Clear UPD_REQ after UPD_ACK is +// 1. +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ 0x00000001 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_BITN 0 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RTCSEC +// +//***************************************************************************** +// Field: [15:0] SEC +// +// Bits 15:0 in AON_RTC:SEC.VALUE. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads of SEC. +// - Then read SEC until two consecutive reads are equal. +#define AUX_SYSIF_RTCSEC_SEC_W 16 +#define AUX_SYSIF_RTCSEC_SEC_M 0x0000FFFF +#define AUX_SYSIF_RTCSEC_SEC_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RTCSUBSEC +// +//***************************************************************************** +// Field: [15:0] SUBSEC +// +// Bits 31:16 in AON_RTC:SUBSEC.VALUE. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads SUBSEC. +// - Then read SUBSEC until two consecutive reads are equal. +#define AUX_SYSIF_RTCSUBSEC_SUBSEC_W 16 +#define AUX_SYSIF_RTCSUBSEC_SUBSEC_M 0x0000FFFF +#define AUX_SYSIF_RTCSUBSEC_SUBSEC_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RTCEVCLR +// +//***************************************************************************** +// Field: [0] RTC_CH2_EV_CLR +// +// Clear events from AON_RTC channel 2. +// +// 0: No effect. +// 1: Clear events from AON_RTC channel 2. +// +// Keep RTC_CH2_EV_CLR high until AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and +// AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY are 0. +#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR 0x00000001 +#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_BITN 0 +#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_M 0x00000001 +#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_BATMONBAT +// +//***************************************************************************** +// Field: [10:8] INT +// +// See AON_BATMON:BAT.INT. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads of INT. +// - Then read INT until two consecutive reads are equal. +#define AUX_SYSIF_BATMONBAT_INT_W 3 +#define AUX_SYSIF_BATMONBAT_INT_M 0x00000700 +#define AUX_SYSIF_BATMONBAT_INT_S 8 + +// Field: [7:0] FRAC +// +// See AON_BATMON:BAT.FRAC. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads of FRAC. +// - Then read FRAC until two consecutive reads are equal. +#define AUX_SYSIF_BATMONBAT_FRAC_W 8 +#define AUX_SYSIF_BATMONBAT_FRAC_M 0x000000FF +#define AUX_SYSIF_BATMONBAT_FRAC_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_BATMONTEMP +// +//***************************************************************************** +// Field: [15:11] SIGN +// +// Sign extension of INT. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads of SIGN. +// - Then read SIGN until two consecutive reads are equal. +#define AUX_SYSIF_BATMONTEMP_SIGN_W 5 +#define AUX_SYSIF_BATMONTEMP_SIGN_M 0x0000F800 +#define AUX_SYSIF_BATMONTEMP_SIGN_S 11 + +// Field: [10:2] INT +// +// See AON_BATMON:TEMP.INT. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads of INT. +// - Then read INT until two consecutive reads are equal. +#define AUX_SYSIF_BATMONTEMP_INT_W 9 +#define AUX_SYSIF_BATMONTEMP_INT_M 0x000007FC +#define AUX_SYSIF_BATMONTEMP_INT_S 2 + +// Field: [1:0] FRAC +// +// See AON_BATMON:TEMP.FRAC. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads of FRAC. +// - Then read FRAC until two consecutive reads are equal. +#define AUX_SYSIF_BATMONTEMP_FRAC_W 2 +#define AUX_SYSIF_BATMONTEMP_FRAC_M 0x00000003 +#define AUX_SYSIF_BATMONTEMP_FRAC_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TIMERHALT +// +//***************************************************************************** +// Field: [3] PROGDLY +// +// Halt programmable delay. +// +// 0: AUX_EVCTL:PROGDLY.VALUE decrements as normal. +// 1: Halt AUX_EVCTL:PROGDLY.VALUE decrementation. +#define AUX_SYSIF_TIMERHALT_PROGDLY 0x00000008 +#define AUX_SYSIF_TIMERHALT_PROGDLY_BITN 3 +#define AUX_SYSIF_TIMERHALT_PROGDLY_M 0x00000008 +#define AUX_SYSIF_TIMERHALT_PROGDLY_S 3 + +// Field: [2] AUX_TIMER2 +// +// Halt AUX_TIMER2. +// +// 0: AUX_TIMER2 operates as normal. +// 1: Halt AUX_TIMER2 operation. +#define AUX_SYSIF_TIMERHALT_AUX_TIMER2 0x00000004 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_BITN 2 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_M 0x00000004 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_S 2 + +// Field: [1] AUX_TIMER1 +// +// Halt AUX_TIMER01 Timer 1. +// +// 0: AUX_TIMER01 Timer 1 operates as normal. +// 1: Halt AUX_TIMER01 Timer 1 operation. +#define AUX_SYSIF_TIMERHALT_AUX_TIMER1 0x00000002 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_BITN 1 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_M 0x00000002 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_S 1 + +// Field: [0] AUX_TIMER0 +// +// Halt AUX_TIMER01 Timer 0. +// +// 0: AUX_TIMER01 Timer 0 operates as normal. +// 1: Halt AUX_TIMER01 Timer 0 operation. +#define AUX_SYSIF_TIMERHALT_AUX_TIMER0 0x00000001 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_BITN 0 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_M 0x00000001 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TIMER2BRIDGE +// +//***************************************************************************** +// Field: [0] BUSY +// +// Status of bus transactions to AUX_TIMER2. +// +// 0: No unfinished bus transactions. +// 1: A bus transaction is ongoing. +#define AUX_SYSIF_TIMER2BRIDGE_BUSY 0x00000001 +#define AUX_SYSIF_TIMER2BRIDGE_BUSY_BITN 0 +#define AUX_SYSIF_TIMER2BRIDGE_BUSY_M 0x00000001 +#define AUX_SYSIF_TIMER2BRIDGE_BUSY_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_SWPWRPROF +// +//***************************************************************************** +// Field: [2:0] STAT +// +// Software status bits that can be read by the power profiler. +#define AUX_SYSIF_SWPWRPROF_STAT_W 3 +#define AUX_SYSIF_SWPWRPROF_STAT_M 0x00000007 +#define AUX_SYSIF_SWPWRPROF_STAT_S 0 + + +#endif // __AUX_SYSIF__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h new file mode 100644 index 0000000..eee6d69 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h @@ -0,0 +1,879 @@ +/****************************************************************************** +* Filename: hw_aux_tdc_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_TDC_H__ +#define __HW_AUX_TDC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_TDC component +// +//***************************************************************************** +// Control +#define AUX_TDC_O_CTL 0x00000000 + +// Status +#define AUX_TDC_O_STAT 0x00000004 + +// Result +#define AUX_TDC_O_RESULT 0x00000008 + +// Saturation Configuration +#define AUX_TDC_O_SATCFG 0x0000000C + +// Trigger Source +#define AUX_TDC_O_TRIGSRC 0x00000010 + +// Trigger Counter +#define AUX_TDC_O_TRIGCNT 0x00000014 + +// Trigger Counter Load +#define AUX_TDC_O_TRIGCNTLOAD 0x00000018 + +// Trigger Counter Configuration +#define AUX_TDC_O_TRIGCNTCFG 0x0000001C + +// Prescaler Control +#define AUX_TDC_O_PRECTL 0x00000020 + +// Prescaler Counter +#define AUX_TDC_O_PRECNTR 0x00000024 + +//***************************************************************************** +// +// Register: AUX_TDC_O_CTL +// +//***************************************************************************** +// Field: [1:0] CMD +// +// TDC commands. +// ENUMs: +// ABORT Force TDC state machine back to IDLE state. +// +// Never write this command +// while AUX_TDC:STAT.STATE equals CLR_CNT or +// WAIT_CLR_CNT_DONE. +// RUN Asynchronous counter start. +// +// The counter starts to +// count when the start event is high. To achieve +// precise edge-to-edge measurements you must +// ensure that the start event is low for at least +// 420 ns after you write this command. +// RUN_SYNC_START Synchronous counter start. +// +// The counter looks for the +// opposite edge of the selected start event +// before it starts to count when the selected +// edge occurs. This guarantees an edge-triggered +// start and is recommended for frequency +// measurements. +// CLR_RESULT Clear STAT.SAT, STAT.DONE, and RESULT.VALUE. +// +// This is not needed as +// prerequisite for a measurement. Reliable clear +// is only guaranteed from IDLE state. +#define AUX_TDC_CTL_CMD_W 2 +#define AUX_TDC_CTL_CMD_M 0x00000003 +#define AUX_TDC_CTL_CMD_S 0 +#define AUX_TDC_CTL_CMD_ABORT 0x00000003 +#define AUX_TDC_CTL_CMD_RUN 0x00000002 +#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 +#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_STAT +// +//***************************************************************************** +// Field: [7] SAT +// +// TDC measurement saturation flag. +// +// 0: Conversion has not saturated. +// 1: Conversion stopped due to saturation. +// +// This field is cleared when a new measurement is started or when CLR_RESULT +// is written to CTL.CMD. +#define AUX_TDC_STAT_SAT 0x00000080 +#define AUX_TDC_STAT_SAT_BITN 7 +#define AUX_TDC_STAT_SAT_M 0x00000080 +#define AUX_TDC_STAT_SAT_S 7 + +// Field: [6] DONE +// +// TDC measurement complete flag. +// +// 0: TDC measurement has not yet completed. +// 1: TDC measurement has completed. +// +// This field clears when a new TDC measurement starts or when you write +// CLR_RESULT to CTL.CMD. +#define AUX_TDC_STAT_DONE 0x00000040 +#define AUX_TDC_STAT_DONE_BITN 6 +#define AUX_TDC_STAT_DONE_M 0x00000040 +#define AUX_TDC_STAT_DONE_S 6 + +// Field: [5:0] STATE +// +// TDC state machine status. +// ENUMs: +// FORCE_STOP Current state is TDC_FORCESTOP. +// You wrote ABORT to +// CTL.CMD to abort the TDC measurement. +// START_FALL Current state is TDC_WAIT_STARTFALL. +// The fast-counter circuit +// waits for a falling edge on the start event. +// WAIT_CLR_CNT_DONE Current state is TDC_STATE_WAIT_CLRCNT_DONE. +// The state machine waits +// for fast-counter circuit to finish reset. +// POR Current state is TDC_STATE_POR. +// This is the reset state. +// GET_RESULT Current state is TDC_STATE_GETRESULTS. +// The state machine copies +// the counter value from the fast-counter +// circuit. +// WAIT_STOP_CNTDWN Current state is TDC_STATE_WAIT_STOPCNTDOWN. +// The fast-counter circuit +// looks for the stop condition. It will ignore a +// number of stop events configured in +// TRIGCNTLOAD.CNT. +// WAIT_STOP Current state is TDC_STATE_WAIT_STOP. +// The state machine waits +// for the fast-counter circuit to stop. +// CLR_CNT Current state is TDC_STATE_CLRCNT. The +// fast-counter circuit is reset. +// IDLE Current state is TDC_STATE_IDLE. +// This is the default state +// after reset and abortion. State will change +// when you write CTL.CMD to either RUN_SYNC_START +// or RUN. +// WAIT_START_STOP_CNT_EN Current state is TDC_STATE_WAIT_STARTSTOPCNTEN. +// The fast-counter circuit +// looks for the start condition. The state +// machine waits for the fast-counter to +// increment. +// WAIT_START Current state is TDC_STATE_WAIT_START. +// The fast-counter circuit +// looks for the start condition. The state +// machine waits for the fast-counter to +// increment. +#define AUX_TDC_STAT_STATE_W 6 +#define AUX_TDC_STAT_STATE_M 0x0000003F +#define AUX_TDC_STAT_STATE_S 0 +#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E +#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E +#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 +#define AUX_TDC_STAT_STATE_POR 0x0000000F +#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E +#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C +#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 +#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 +#define AUX_TDC_STAT_STATE_IDLE 0x00000006 +#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 +#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_RESULT +// +//***************************************************************************** +// Field: [24:0] VALUE +// +// TDC conversion result. +// +// The result of the TDC conversion is given in number of clock edges of the +// clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and +// falling edges are counted. +// +// If TDC counter saturates, VALUE is slightly higher than SATCFG.LIMIT, as it +// takes a non-zero time to stop the measurement. Hence, the maximum value of +// this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT +// to R24. +#define AUX_TDC_RESULT_VALUE_W 25 +#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF +#define AUX_TDC_RESULT_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_SATCFG +// +//***************************************************************************** +// Field: [3:0] LIMIT +// +// Saturation limit. +// +// The flag STAT.SAT is set when the TDC counter saturates. +// +// Values not enumerated are not supported +// ENUMs: +// R24 Result bit 24: TDC conversion saturates and stops +// when RESULT.VALUE[24] is set. +// R23 Result bit 23: TDC conversion saturates and stops +// when RESULT.VALUE[23] is set. +// R22 Result bit 22: TDC conversion saturates and stops +// when RESULT.VALUE[22] is set. +// R21 Result bit 21: TDC conversion saturates and stops +// when RESULT.VALUE[21] is set. +// R20 Result bit 20: TDC conversion saturates and stops +// when RESULT.VALUE[20] is set. +// R19 Result bit 19: TDC conversion saturates and stops +// when RESULT.VALUE[19] is set. +// R18 Result bit 18: TDC conversion saturates and stops +// when RESULT.VALUE[18] is set. +// R17 Result bit 17: TDC conversion saturates and stops +// when RESULT.VALUE[17] is set. +// R16 Result bit 16: TDC conversion saturates and stops +// when RESULT.VALUE[16] is set. +// R15 Result bit 15: TDC conversion saturates and stops +// when RESULT.VALUE[15] is set. +// R14 Result bit 14: TDC conversion saturates and stops +// when RESULT.VALUE[14] is set. +// R13 Result bit 13: TDC conversion saturates and stops +// when RESULT.VALUE[13] is set. +// R12 Result bit 12: TDC conversion saturates and stops +// when RESULT.VALUE[12] is set. +#define AUX_TDC_SATCFG_LIMIT_W 4 +#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_S 0 +#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E +#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D +#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C +#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B +#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A +#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 +#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 +#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 +#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 +#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 +#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 +#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGSRC +// +//***************************************************************************** +// Field: [14] STOP_POL +// +// Polarity of stop source. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// LOW TDC conversion stops when low level is detected. +// HIGH TDC conversion stops when high level is detected. +#define AUX_TDC_TRIGSRC_STOP_POL 0x00004000 +#define AUX_TDC_TRIGSRC_STOP_POL_BITN 14 +#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00004000 +#define AUX_TDC_TRIGSRC_STOP_POL_S 14 +#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00004000 +#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 + +// Field: [13:8] STOP_SRC +// +// Select stop source from the asynchronous AUX event bus. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// NO_EVENT No event. +// AUX_TDC_PRE Select TDC Prescaler event which is generated by +// configuration of PRECTL. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TDC_TRIGSRC_STOP_SRC_W 6 +#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00003F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_S 8 +#define AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT 0x00003F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE 0x00003E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ 0x00003A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE 0x00003900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N 0x00003800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE 0x00003700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV 0x00003600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV 0x00003500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE 0x00003400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3 0x00003300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2 0x00003200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1 0x00003100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0 0x00003000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00002F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00002E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1 0x00002D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0 0x00002C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00002B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00002A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE 0x00002900 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE 0x00002800 +#define AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN 0x00002700 +#define AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF 0x00002600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD 0x00002500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD 0x00002400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ 0x00002300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY 0x00002200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00002100 +#define AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31 0x00001F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30 0x00001E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29 0x00001D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28 0x00001C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27 0x00001B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26 0x00001A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25 0x00001900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24 0x00001800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23 0x00001700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22 0x00001600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21 0x00001500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20 0x00001400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19 0x00001300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18 0x00001200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17 0x00001100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16 0x00001000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00000F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00000E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00000D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00000C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00000B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00000A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00000900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00000800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00000700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00000600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00000500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00000400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00000300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000000 + +// Field: [6] START_POL +// +// Polarity of start source. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// LOW TDC conversion starts when low level is detected. +// HIGH TDC conversion starts when high level is detected. +#define AUX_TDC_TRIGSRC_START_POL 0x00000040 +#define AUX_TDC_TRIGSRC_START_POL_BITN 6 +#define AUX_TDC_TRIGSRC_START_POL_M 0x00000040 +#define AUX_TDC_TRIGSRC_START_POL_S 6 +#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000040 +#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 + +// Field: [5:0] START_SRC +// +// Select start source from the asynchronous AUX event bus. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// NO_EVENT No event. +// AUX_TDC_PRE Select TDC Prescaler event which is generated by +// configuration of PRECTL. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TDC_TRIGSRC_START_SRC_W 6 +#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000003F +#define AUX_TDC_TRIGSRC_START_SRC_S 0 +#define AUX_TDC_TRIGSRC_START_SRC_NO_EVENT 0x0000003F +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE 0x0000003E +#define AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x0000002F +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x0000002E +#define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000002B +#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000002A +#define AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE 0x00000028 +#define AUX_TDC_TRIGSRC_START_SRC_PWR_DWN 0x00000027 +#define AUX_TDC_TRIGSRC_START_SRC_SCLK_LF 0x00000026 +#define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000021 +#define AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV 0x00000020 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO31 0x0000001F +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO30 0x0000001E +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO29 0x0000001D +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO28 0x0000001C +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO27 0x0000001B +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO26 0x0000001A +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO25 0x00000019 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO24 0x00000018 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO23 0x00000017 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO22 0x00000016 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO21 0x00000015 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO20 0x00000014 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO19 0x00000013 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO18 0x00000012 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO17 0x00000011 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO16 0x00000010 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000000F +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000000E +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000000D +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x0000000C +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x0000000B +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x0000000A +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000009 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000008 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000007 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000006 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000005 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000004 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000003 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x00000002 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x00000001 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNT +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. +// +// Read CNT to get the remaining number of stop events to ignore during a TDC +// measurement. +// +// Write CNT to update the remaining number of stop events to ignore during a +// TDC measurement. The TDC measurement ignores updates of CNT if there are no +// more stop events left to ignore. +// +// When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the +// start of the measurement. +#define AUX_TDC_TRIGCNT_CNT_W 16 +#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNT_CNT_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNTLOAD +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. +// +// To measure frequency of an event source: +// - Set start event equal to stop event. +// - Set CNT to number of periods to measure. Both 0 and 1 values measures a +// single event source period. +// +// To measure pulse width of an event source: +// - Set start event source equal to stop event source. +// - Select different polarity for start and stop event. +// - Set CNT to 0. +// +// To measure time from the start event to the Nth stop event when N > 1: +// - Select different start and stop event source. +// - Set CNT to (N-1). +// +// See the Technical Reference Manual for event timing requirements. +// +// When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start +// of the measurement. +#define AUX_TDC_TRIGCNTLOAD_CNT_W 16 +#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNTLOAD_CNT_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNTCFG +// +//***************************************************************************** +// Field: [0] EN +// +// Enable stop-counter. +// +// 0: Disable stop-counter. +// 1: Enable stop-counter. +// +// Change only while STAT.STATE is IDLE. +#define AUX_TDC_TRIGCNTCFG_EN 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_BITN 0 +#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_PRECTL +// +//***************************************************************************** +// Field: [7] RESET_N +// +// Prescaler reset. +// +// 0: Reset prescaler. +// 1: Release reset of prescaler. +// +// AUX_TDC_PRE event becomes 0 when you reset the prescaler. +#define AUX_TDC_PRECTL_RESET_N 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_BITN 7 +#define AUX_TDC_PRECTL_RESET_N_M 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_S 7 + +// Field: [6] RATIO +// +// Prescaler ratio. +// +// This controls how often the AUX_TDC_PRE event is generated by the prescaler. +// ENUMs: +// DIV64 Prescaler divides input by 64. +// +// AUX_TDC_PRE event has a +// rising edge for every 64 rising edges of the +// input. AUX_TDC_PRE event toggles on every 32nd +// rising edge of the input. +// DIV16 Prescaler divides input by 16. +// +// AUX_TDC_PRE event has a +// rising edge for every 16 rising edges of the +// input. AUX_TDC_PRE event toggles on every 8th +// rising edge of the input. +#define AUX_TDC_PRECTL_RATIO 0x00000040 +#define AUX_TDC_PRECTL_RATIO_BITN 6 +#define AUX_TDC_PRECTL_RATIO_M 0x00000040 +#define AUX_TDC_PRECTL_RATIO_S 6 +#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 +#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 + +// Field: [5:0] SRC +// +// Prescaler event source. +// +// Select an event from the asynchronous AUX event bus to connect to the +// prescaler input. +// +// Configure only while RESET_N is 0. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TDC_PRECTL_SRC_W 6 +#define AUX_TDC_PRECTL_SRC_M 0x0000003F +#define AUX_TDC_PRECTL_SRC_S 0 +#define AUX_TDC_PRECTL_SRC_NO_EVENT 0x0000003F +#define AUX_TDC_PRECTL_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_TDC_PRECTL_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_TDC_PRECTL_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_TDC_PRECTL_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_TDC_PRECTL_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x0000002F +#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x0000002E +#define AUX_TDC_PRECTL_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_TDC_PRECTL_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000002B +#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000002A +#define AUX_TDC_PRECTL_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_TDC_PRECTL_SRC_MCU_ACTIVE 0x00000028 +#define AUX_TDC_PRECTL_SRC_PWR_DWN 0x00000027 +#define AUX_TDC_PRECTL_SRC_SCLK_LF 0x00000026 +#define AUX_TDC_PRECTL_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_TDC_PRECTL_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_TDC_PRECTL_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000021 +#define AUX_TDC_PRECTL_SRC_MANUAL_EV 0x00000020 +#define AUX_TDC_PRECTL_SRC_AUXIO31 0x0000001F +#define AUX_TDC_PRECTL_SRC_AUXIO30 0x0000001E +#define AUX_TDC_PRECTL_SRC_AUXIO29 0x0000001D +#define AUX_TDC_PRECTL_SRC_AUXIO28 0x0000001C +#define AUX_TDC_PRECTL_SRC_AUXIO27 0x0000001B +#define AUX_TDC_PRECTL_SRC_AUXIO26 0x0000001A +#define AUX_TDC_PRECTL_SRC_AUXIO25 0x00000019 +#define AUX_TDC_PRECTL_SRC_AUXIO24 0x00000018 +#define AUX_TDC_PRECTL_SRC_AUXIO23 0x00000017 +#define AUX_TDC_PRECTL_SRC_AUXIO22 0x00000016 +#define AUX_TDC_PRECTL_SRC_AUXIO21 0x00000015 +#define AUX_TDC_PRECTL_SRC_AUXIO20 0x00000014 +#define AUX_TDC_PRECTL_SRC_AUXIO19 0x00000013 +#define AUX_TDC_PRECTL_SRC_AUXIO18 0x00000012 +#define AUX_TDC_PRECTL_SRC_AUXIO17 0x00000011 +#define AUX_TDC_PRECTL_SRC_AUXIO16 0x00000010 +#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000000F +#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000000E +#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000000D +#define AUX_TDC_PRECTL_SRC_AUXIO12 0x0000000C +#define AUX_TDC_PRECTL_SRC_AUXIO11 0x0000000B +#define AUX_TDC_PRECTL_SRC_AUXIO10 0x0000000A +#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000009 +#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000008 +#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000007 +#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000006 +#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000005 +#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000004 +#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000003 +#define AUX_TDC_PRECTL_SRC_AUXIO2 0x00000002 +#define AUX_TDC_PRECTL_SRC_AUXIO1 0x00000001 +#define AUX_TDC_PRECTL_SRC_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_PRECNTR +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Prescaler counter value. +// +// Write a value to CNT to capture the value of the 16-bit prescaler counter +// into CNT. Read CNT to get the captured value. +// +// The read value gets 1 LSB uncertainty if the event source level rises when +// you release the reset. +// The read value gets 1 LSB uncertainty if the event source level rises when +// you capture the prescaler counter. +// +// Please note the following: +// - The prescaler counter is reset to 2 by PRECTL.RESET_N. +// - The captured value is 2 when the number of rising edges on prescaler input +// is less than 3. Otherwise, captured value equals number of event pulses - 1. +#define AUX_TDC_PRECNTR_CNT_W 16 +#define AUX_TDC_PRECNTR_CNT_M 0x0000FFFF +#define AUX_TDC_PRECNTR_CNT_S 0 + + +#endif // __AUX_TDC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h new file mode 100644 index 0000000..6c6a2fa --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h @@ -0,0 +1,611 @@ +/****************************************************************************** +* Filename: hw_aux_timer01_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_TIMER01_H__ +#define __HW_AUX_TIMER01_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_TIMER01 component +// +//***************************************************************************** +// Timer 0 Configuration +#define AUX_TIMER01_O_T0CFG 0x00000000 + +// Timer 0 Control +#define AUX_TIMER01_O_T0CTL 0x00000004 + +// Timer 0 Target +#define AUX_TIMER01_O_T0TARGET 0x00000008 + +// Timer 0 Counter +#define AUX_TIMER01_O_T0CNTR 0x0000000C + +// Timer 1 Configuration +#define AUX_TIMER01_O_T1CFG 0x00000010 + +// Timer 1 Control +#define AUX_TIMER01_O_T1CTL 0x00000014 + +// Timer 1 Target +#define AUX_TIMER01_O_T1TARGET 0x00000018 + +// Timer 1 Counter +#define AUX_TIMER01_O_T1CNTR 0x0000001C + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T0CFG +// +//***************************************************************************** +// Field: [14] TICK_SRC_POL +// +// Tick source polarity for Timer 0. +// ENUMs: +// FALL Count on falling edges of TICK_SRC. +// RISE Count on rising edges of TICK_SRC. +#define AUX_TIMER01_T0CFG_TICK_SRC_POL 0x00004000 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_BITN 14 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_M 0x00004000 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_S 14 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_FALL 0x00004000 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_RISE 0x00000000 + +// Field: [13:8] TICK_SRC +// +// Select Timer 0 tick source from the synchronous event bus. +// ENUMs: +// AUX_TIMER2_CLKSW_RDY AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY +// AUX_DAC_HOLD_ACTIVE AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// NO_EVENT No event. +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TIMER01_T0CFG_TICK_SRC_W 6 +#define AUX_TIMER01_T0CFG_TICK_SRC_M 0x00003F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_S 8 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_DONE 0x00003900 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TDC_DONE 0x00003700 +#define AUX_TIMER01_T0CFG_TICK_SRC_NO_EVENT 0x00003600 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER1_EV 0x00003500 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPB 0x00002F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPA 0x00002E00 +#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00 +#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00 +#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_EV 0x00002B00 +#define AUX_TIMER01_T0CFG_TICK_SRC_ACLK_REF 0x00002A00 +#define AUX_TIMER01_T0CFG_TICK_SRC_VDDR_RECHARGE 0x00002900 +#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_ACTIVE 0x00002800 +#define AUX_TIMER01_T0CFG_TICK_SRC_PWR_DWN 0x00002700 +#define AUX_TIMER01_T0CFG_TICK_SRC_SCLK_LF 0x00002600 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2 0x00002100 +#define AUX_TIMER01_T0CFG_TICK_SRC_MANUAL_EV 0x00002000 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO31 0x00001F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO30 0x00001E00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO29 0x00001D00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO28 0x00001C00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO27 0x00001B00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO26 0x00001A00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO25 0x00001900 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO24 0x00001800 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO23 0x00001700 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO22 0x00001600 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO21 0x00001500 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO20 0x00001400 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO19 0x00001300 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO18 0x00001200 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO17 0x00001100 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO16 0x00001000 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO15 0x00000F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO14 0x00000E00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO13 0x00000D00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO12 0x00000C00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO11 0x00000B00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO10 0x00000A00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO9 0x00000900 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO8 0x00000800 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO7 0x00000700 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO6 0x00000600 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO5 0x00000500 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO4 0x00000400 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO3 0x00000300 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO2 0x00000200 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO1 0x00000100 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO0 0x00000000 + +// Field: [7:4] PRE +// +// Prescaler division ratio is 2^PRE: +// +// 0x0: Divide by 1. +// 0x1: Divide by 2. +// 0x2: Divide by 4. +// ... +// 0xF: Divide by 32,768. +#define AUX_TIMER01_T0CFG_PRE_W 4 +#define AUX_TIMER01_T0CFG_PRE_M 0x000000F0 +#define AUX_TIMER01_T0CFG_PRE_S 4 + +// Field: [1] MODE +// +// Timer 0 mode. +// +// Configure source for Timer 0 prescaler. +// ENUMs: +// TICK Use event set by TICK_SRC as source for prescaler. +// CLK Use clock as source for prescaler. Note that +// AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the +// clock frequency. +#define AUX_TIMER01_T0CFG_MODE 0x00000002 +#define AUX_TIMER01_T0CFG_MODE_BITN 1 +#define AUX_TIMER01_T0CFG_MODE_M 0x00000002 +#define AUX_TIMER01_T0CFG_MODE_S 1 +#define AUX_TIMER01_T0CFG_MODE_TICK 0x00000002 +#define AUX_TIMER01_T0CFG_MODE_CLK 0x00000000 + +// Field: [0] RELOAD +// +// Timer 0 reload mode. +// ENUMs: +// CONT Continuous mode. +// +// Timer 0 restarts when the +// counter value becomes equal to or greater than +// ( T0TARGET.VALUE - 1). +// MAN Manual mode. +// +// Timer 0 stops and +// T0CTL.EN becomes 0 when the counter value +// becomes equal to or greater than +// T0TARGET.VALUE. +#define AUX_TIMER01_T0CFG_RELOAD 0x00000001 +#define AUX_TIMER01_T0CFG_RELOAD_BITN 0 +#define AUX_TIMER01_T0CFG_RELOAD_M 0x00000001 +#define AUX_TIMER01_T0CFG_RELOAD_S 0 +#define AUX_TIMER01_T0CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER01_T0CFG_RELOAD_MAN 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T0CTL +// +//***************************************************************************** +// Field: [0] EN +// +// Timer 0 enable. +// +// 0: Disable Timer 0. +// 1: Enable Timer 0. +// +// The counter restarts from 0 when you enable Timer 0. +#define AUX_TIMER01_T0CTL_EN 0x00000001 +#define AUX_TIMER01_T0CTL_EN_BITN 0 +#define AUX_TIMER01_T0CTL_EN_M 0x00000001 +#define AUX_TIMER01_T0CTL_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T0TARGET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Timer 0 target value. +// +// Manual Reload Mode: +// - Timer 0 increments until the counter value becomes equal to or greater +// than VALUE. +// - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter +// value is equal to or greater than VALUE. +// +// Note: When VALUE is 0, Timer 0 counts to 1. AUX_TIMER0_EV pulses high for 1 +// peripheral clock period. +// +// Continuous Reload Mode: +// - Timer 0 increments until the counter value becomes equal to or greater +// than ( VALUE - 1), then restarts from 0. +// - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter +// value is 0, except for when you enable the timer. +// +// Note: When VALUE is less than 2, Timer 0 counter value remains 0. +// AUX_TIMER0_EV goes high and remains high 1 peripheral clock period after you +// enable the timer. +// +// +// It is allowed to update the VALUE while the timer runs. +#define AUX_TIMER01_T0TARGET_VALUE_W 16 +#define AUX_TIMER01_T0TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER01_T0TARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T0CNTR +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Timer 0 counter value. +#define AUX_TIMER01_T0CNTR_VALUE_W 16 +#define AUX_TIMER01_T0CNTR_VALUE_M 0x0000FFFF +#define AUX_TIMER01_T0CNTR_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T1CFG +// +//***************************************************************************** +// Field: [14] TICK_SRC_POL +// +// Tick source polarity for Timer 1. +// ENUMs: +// FALL Count on falling edges of TICK_SRC. +// RISE Count on rising edges of TICK_SRC. +#define AUX_TIMER01_T1CFG_TICK_SRC_POL 0x00004000 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_BITN 14 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_M 0x00004000 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_S 14 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_FALL 0x00004000 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_RISE 0x00000000 + +// Field: [13:8] TICK_SRC +// +// Select Timer 1 tick source from the synchronous event bus. +// ENUMs: +// AUX_TIMER2_CLKSW_RDY AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY +// AUX_DAC_HOLD_ACTIVE AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// NO_EVENT No event. +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TIMER01_T1CFG_TICK_SRC_W 6 +#define AUX_TIMER01_T1CFG_TICK_SRC_M 0x00003F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_S 8 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_DONE 0x00003900 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TDC_DONE 0x00003700 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER0_EV 0x00003600 +#define AUX_TIMER01_T1CFG_TICK_SRC_NO_EVENT 0x00003500 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPB 0x00002F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPA 0x00002E00 +#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00 +#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00 +#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_EV 0x00002B00 +#define AUX_TIMER01_T1CFG_TICK_SRC_ACLK_REF 0x00002A00 +#define AUX_TIMER01_T1CFG_TICK_SRC_VDDR_RECHARGE 0x00002900 +#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_ACTIVE 0x00002800 +#define AUX_TIMER01_T1CFG_TICK_SRC_PWR_DWN 0x00002700 +#define AUX_TIMER01_T1CFG_TICK_SRC_SCLK_LF 0x00002600 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2 0x00002100 +#define AUX_TIMER01_T1CFG_TICK_SRC_MANUAL_EV 0x00002000 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO31 0x00001F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO30 0x00001E00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO29 0x00001D00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO28 0x00001C00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO27 0x00001B00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO26 0x00001A00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO25 0x00001900 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO24 0x00001800 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO23 0x00001700 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO22 0x00001600 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO21 0x00001500 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO20 0x00001400 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO19 0x00001300 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO18 0x00001200 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO17 0x00001100 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO16 0x00001000 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO15 0x00000F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO14 0x00000E00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO13 0x00000D00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO12 0x00000C00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO11 0x00000B00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO10 0x00000A00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO9 0x00000900 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO8 0x00000800 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO7 0x00000700 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO6 0x00000600 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO5 0x00000500 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO4 0x00000400 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO3 0x00000300 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO2 0x00000200 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO1 0x00000100 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO0 0x00000000 + +// Field: [7:4] PRE +// +// Prescaler division ratio is 2^PRE: +// +// 0x0: Divide by 1. +// 0x1: Divide by 2. +// 0x2: Divide by 4. +// ... +// 0xF: Divide by 32,768. +#define AUX_TIMER01_T1CFG_PRE_W 4 +#define AUX_TIMER01_T1CFG_PRE_M 0x000000F0 +#define AUX_TIMER01_T1CFG_PRE_S 4 + +// Field: [1] MODE +// +// Timer 1 mode. +// +// Configure source for Timer 1 prescaler. +// ENUMs: +// TICK Use event set by TICK_SRC as source for prescaler. +// CLK Use clock as source for prescaler. Note that +// AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the +// clock frequency. +#define AUX_TIMER01_T1CFG_MODE 0x00000002 +#define AUX_TIMER01_T1CFG_MODE_BITN 1 +#define AUX_TIMER01_T1CFG_MODE_M 0x00000002 +#define AUX_TIMER01_T1CFG_MODE_S 1 +#define AUX_TIMER01_T1CFG_MODE_TICK 0x00000002 +#define AUX_TIMER01_T1CFG_MODE_CLK 0x00000000 + +// Field: [0] RELOAD +// +// Timer 1 reload mode. +// ENUMs: +// CONT Continuous mode. +// +// Timer 1 restarts when the +// counter value becomes equal to or greater than +// ( T1TARGET.VALUE - 1). +// MAN Manual mode. +// +// Timer 1 stops and +// T1CTL.EN becomes 0 when the counter value +// becomes equal to or greater than +// T1TARGET.VALUE. +#define AUX_TIMER01_T1CFG_RELOAD 0x00000001 +#define AUX_TIMER01_T1CFG_RELOAD_BITN 0 +#define AUX_TIMER01_T1CFG_RELOAD_M 0x00000001 +#define AUX_TIMER01_T1CFG_RELOAD_S 0 +#define AUX_TIMER01_T1CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER01_T1CFG_RELOAD_MAN 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T1CTL +// +//***************************************************************************** +// Field: [0] EN +// +// Timer 1 enable. +// +// 0: Disable Timer 1. +// 1: Enable Timer 1. +// +// The counter restarts from 0 when you enable Timer 1. +#define AUX_TIMER01_T1CTL_EN 0x00000001 +#define AUX_TIMER01_T1CTL_EN_BITN 0 +#define AUX_TIMER01_T1CTL_EN_M 0x00000001 +#define AUX_TIMER01_T1CTL_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T1TARGET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Timer 1 target value. +// +// Manual Reload Mode: +// - Timer 1 increments until the counter value becomes equal to or greater +// than VALUE. +// - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter +// value is equal to or greater than VALUE. +// +// Note: When VALUE is 0, Timer 1 counts to 1. AUX_TIMER1_EV pulses high for 1 +// peripheral clock period. +// +// Continuous Reload Mode: +// - Timer 1 increments until the counter value becomes equal to or greater +// than ( VALUE - 1), then restarts from 0. +// - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter +// value is 0, except for when you enable the timer. +// +// Note: When VALUE is less than 2, Timer 1 counter value remains 0. +// AUX_TIMER1_EV goes high and remains high 1 peripheral clock period after you +// enable the timer. +// +// +// It is allowed to update the VALUE while the timer runs. +#define AUX_TIMER01_T1TARGET_VALUE_W 16 +#define AUX_TIMER01_T1TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER01_T1TARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T1CNTR +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Timer 1 counter value. +#define AUX_TIMER01_T1CNTR_VALUE_W 16 +#define AUX_TIMER01_T1CNTR_VALUE_M 0x0000FFFF +#define AUX_TIMER01_T1CNTR_VALUE_S 0 + + +#endif // __AUX_TIMER01__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h new file mode 100644 index 0000000..48cb3cc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h @@ -0,0 +1,2491 @@ +/****************************************************************************** +* Filename: hw_aux_timer2_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_TIMER2_H__ +#define __HW_AUX_TIMER2_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_TIMER2 component +// +//***************************************************************************** +// Timer Control +#define AUX_TIMER2_O_CTL 0x00000000 + +// Target +#define AUX_TIMER2_O_TARGET 0x00000004 + +// Shadow Target +#define AUX_TIMER2_O_SHDWTARGET 0x00000008 + +// Counter +#define AUX_TIMER2_O_CNTR 0x0000000C + +// Clock Prescaler Configuration +#define AUX_TIMER2_O_PRECFG 0x00000010 + +// Event Control +#define AUX_TIMER2_O_EVCTL 0x00000014 + +// Pulse Trigger +#define AUX_TIMER2_O_PULSETRIG 0x00000018 + +// Channel 0 Event Configuration +#define AUX_TIMER2_O_CH0EVCFG 0x00000080 + +// Channel 0 Capture Configuration +#define AUX_TIMER2_O_CH0CCFG 0x00000084 + +// Channel 0 Pipeline Capture Compare +#define AUX_TIMER2_O_CH0PCC 0x00000088 + +// Channel 0 Capture Compare +#define AUX_TIMER2_O_CH0CC 0x0000008C + +// Channel 1 Event Configuration +#define AUX_TIMER2_O_CH1EVCFG 0x00000090 + +// Channel 1 Capture Configuration +#define AUX_TIMER2_O_CH1CCFG 0x00000094 + +// Channel 1 Pipeline Capture Compare +#define AUX_TIMER2_O_CH1PCC 0x00000098 + +// Channel 1 Capture Compare +#define AUX_TIMER2_O_CH1CC 0x0000009C + +// Channel 2 Event Configuration +#define AUX_TIMER2_O_CH2EVCFG 0x000000A0 + +// Channel 2 Capture Configuration +#define AUX_TIMER2_O_CH2CCFG 0x000000A4 + +// Channel 2 Pipeline Capture Compare +#define AUX_TIMER2_O_CH2PCC 0x000000A8 + +// Channel 2 Capture Compare +#define AUX_TIMER2_O_CH2CC 0x000000AC + +// Channel 3 Event Configuration +#define AUX_TIMER2_O_CH3EVCFG 0x000000B0 + +// Channel 3 Capture Configuration +#define AUX_TIMER2_O_CH3CCFG 0x000000B4 + +// Channel 3 Pipeline Capture Compare +#define AUX_TIMER2_O_CH3PCC 0x000000B8 + +// Channel 3 Capture Compare +#define AUX_TIMER2_O_CH3CC 0x000000BC + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CTL +// +//***************************************************************************** +// Field: [6] CH3_RESET +// +// Channel 3 reset. +// +// 0: No effect. +// 1: Reset CH3CC, CH3PCC, CH3EVCFG, and CH3CCFG. +// +// Read returns 0. +#define AUX_TIMER2_CTL_CH3_RESET 0x00000040 +#define AUX_TIMER2_CTL_CH3_RESET_BITN 6 +#define AUX_TIMER2_CTL_CH3_RESET_M 0x00000040 +#define AUX_TIMER2_CTL_CH3_RESET_S 6 + +// Field: [5] CH2_RESET +// +// Channel 2 reset. +// +// 0: No effect. +// 1: Reset CH2CC, CH2PCC, CH2EVCFG, and CH2CCFG. +// +// Read returns 0. +#define AUX_TIMER2_CTL_CH2_RESET 0x00000020 +#define AUX_TIMER2_CTL_CH2_RESET_BITN 5 +#define AUX_TIMER2_CTL_CH2_RESET_M 0x00000020 +#define AUX_TIMER2_CTL_CH2_RESET_S 5 + +// Field: [4] CH1_RESET +// +// Channel 1 reset. +// +// 0: No effect. +// 1: Reset CH1CC, CH1PCC, CH1EVCFG, and CH1CCFG. +// +// Read returns 0. +#define AUX_TIMER2_CTL_CH1_RESET 0x00000010 +#define AUX_TIMER2_CTL_CH1_RESET_BITN 4 +#define AUX_TIMER2_CTL_CH1_RESET_M 0x00000010 +#define AUX_TIMER2_CTL_CH1_RESET_S 4 + +// Field: [3] CH0_RESET +// +// Channel 0 reset. +// +// 0: No effect. +// 1: Reset CH0CC, CH0PCC, CH0EVCFG, and CH0CCFG. +// +// Read returns 0. +#define AUX_TIMER2_CTL_CH0_RESET 0x00000008 +#define AUX_TIMER2_CTL_CH0_RESET_BITN 3 +#define AUX_TIMER2_CTL_CH0_RESET_M 0x00000008 +#define AUX_TIMER2_CTL_CH0_RESET_S 3 + +// Field: [2] TARGET_EN +// +// Select counter target value. +// +// You must select TARGET to use shadow target functionality. +// ENUMs: +// TARGET TARGET.VALUE +// CNTR_MAX 65535 +#define AUX_TIMER2_CTL_TARGET_EN 0x00000004 +#define AUX_TIMER2_CTL_TARGET_EN_BITN 2 +#define AUX_TIMER2_CTL_TARGET_EN_M 0x00000004 +#define AUX_TIMER2_CTL_TARGET_EN_S 2 +#define AUX_TIMER2_CTL_TARGET_EN_TARGET 0x00000004 +#define AUX_TIMER2_CTL_TARGET_EN_CNTR_MAX 0x00000000 + +// Field: [1:0] MODE +// +// Timer mode control. +// +// The timer restarts from 0 when you set MODE to UP_ONCE, UP_PER, or +// UPDWN_PER. +// +// When you write MODE all internally queued updates to [CHnCC.*] and TARGET +// clear. +// ENUMs: +// UPDWN_PER Count up and down periodically. The timer counts +// from 0 to target value and back to 0, +// repeatedly. +// +// Period = (target value * +// 2) * timer clock period +// UP_PER Count up periodically. The timer increments from 0 +// to target value, repeatedly. +// +// Period = (target value + +// 1) * timer clock period +// UP_ONCE Count up once. The timer increments from 0 to +// target value, then stops and sets MODE to DIS. +// DIS Disable timer. Updates to counter, channels, and +// events stop. +#define AUX_TIMER2_CTL_MODE_W 2 +#define AUX_TIMER2_CTL_MODE_M 0x00000003 +#define AUX_TIMER2_CTL_MODE_S 0 +#define AUX_TIMER2_CTL_MODE_UPDWN_PER 0x00000003 +#define AUX_TIMER2_CTL_MODE_UP_PER 0x00000002 +#define AUX_TIMER2_CTL_MODE_UP_ONCE 0x00000001 +#define AUX_TIMER2_CTL_MODE_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_TARGET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// 16 bit user defined counter target value, which is used when selected by +// CTL.TARGET_EN. +#define AUX_TIMER2_TARGET_VALUE_W 16 +#define AUX_TIMER2_TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER2_TARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_SHDWTARGET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Target value for next counter period. +// +// The timer copies VALUE to TARGET.VALUE when CNTR.VALUE becomes 0. The copy +// does not happen when you restart the timer. +// +// This is useful to avoid period jitter in PWM applications with time-varying +// period, sometimes referenced as phase corrected PWM. +#define AUX_TIMER2_SHDWTARGET_VALUE_W 16 +#define AUX_TIMER2_SHDWTARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER2_SHDWTARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CNTR +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// 16 bit current counter value. +#define AUX_TIMER2_CNTR_VALUE_W 16 +#define AUX_TIMER2_CNTR_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CNTR_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_PRECFG +// +//***************************************************************************** +// Field: [7:0] CLKDIV +// +// Clock division. +// +// CLKDIV determines the timer clock frequency for counter, synchronization, +// and timer event updates. The timer clock frequency is the clock selected by +// AUX_SYSIF:TIMER2CLKCTL.SRC divided by (CLKDIV + 1). This inverse is the +// timer clock period. +// +// 0x00: Divide by 1. +// 0x01: Divide by 2. +// ... +// 0xFF: Divide by 256. +#define AUX_TIMER2_PRECFG_CLKDIV_W 8 +#define AUX_TIMER2_PRECFG_CLKDIV_M 0x000000FF +#define AUX_TIMER2_PRECFG_CLKDIV_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_EVCTL +// +//***************************************************************************** +// Field: [7] EV3_SET +// +// Set event 3. +// +// Write 1 to set event 3. +#define AUX_TIMER2_EVCTL_EV3_SET 0x00000080 +#define AUX_TIMER2_EVCTL_EV3_SET_BITN 7 +#define AUX_TIMER2_EVCTL_EV3_SET_M 0x00000080 +#define AUX_TIMER2_EVCTL_EV3_SET_S 7 + +// Field: [6] EV3_CLR +// +// Clear event 3. +// +// Write 1 to clear event 3. +#define AUX_TIMER2_EVCTL_EV3_CLR 0x00000040 +#define AUX_TIMER2_EVCTL_EV3_CLR_BITN 6 +#define AUX_TIMER2_EVCTL_EV3_CLR_M 0x00000040 +#define AUX_TIMER2_EVCTL_EV3_CLR_S 6 + +// Field: [5] EV2_SET +// +// Set event 2. +// +// Write 1 to set event 2. +#define AUX_TIMER2_EVCTL_EV2_SET 0x00000020 +#define AUX_TIMER2_EVCTL_EV2_SET_BITN 5 +#define AUX_TIMER2_EVCTL_EV2_SET_M 0x00000020 +#define AUX_TIMER2_EVCTL_EV2_SET_S 5 + +// Field: [4] EV2_CLR +// +// Clear event 2. +// +// Write 1 to clear event 2. +#define AUX_TIMER2_EVCTL_EV2_CLR 0x00000010 +#define AUX_TIMER2_EVCTL_EV2_CLR_BITN 4 +#define AUX_TIMER2_EVCTL_EV2_CLR_M 0x00000010 +#define AUX_TIMER2_EVCTL_EV2_CLR_S 4 + +// Field: [3] EV1_SET +// +// Set event 1. +// +// Write 1 to set event 1. +#define AUX_TIMER2_EVCTL_EV1_SET 0x00000008 +#define AUX_TIMER2_EVCTL_EV1_SET_BITN 3 +#define AUX_TIMER2_EVCTL_EV1_SET_M 0x00000008 +#define AUX_TIMER2_EVCTL_EV1_SET_S 3 + +// Field: [2] EV1_CLR +// +// Clear event 1. +// +// Write 1 to clear event 1. +#define AUX_TIMER2_EVCTL_EV1_CLR 0x00000004 +#define AUX_TIMER2_EVCTL_EV1_CLR_BITN 2 +#define AUX_TIMER2_EVCTL_EV1_CLR_M 0x00000004 +#define AUX_TIMER2_EVCTL_EV1_CLR_S 2 + +// Field: [1] EV0_SET +// +// Set event 0. +// +// Write 1 to set event 0. +#define AUX_TIMER2_EVCTL_EV0_SET 0x00000002 +#define AUX_TIMER2_EVCTL_EV0_SET_BITN 1 +#define AUX_TIMER2_EVCTL_EV0_SET_M 0x00000002 +#define AUX_TIMER2_EVCTL_EV0_SET_S 1 + +// Field: [0] EV0_CLR +// +// Clear event 0. +// +// Write 1 to clear event 0. +#define AUX_TIMER2_EVCTL_EV0_CLR 0x00000001 +#define AUX_TIMER2_EVCTL_EV0_CLR_BITN 0 +#define AUX_TIMER2_EVCTL_EV0_CLR_M 0x00000001 +#define AUX_TIMER2_EVCTL_EV0_CLR_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_PULSETRIG +// +//***************************************************************************** +// Field: [0] TRIG +// +// Pulse trigger. +// +// Write 1 to generate a pulse to AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. Pulse +// width equals the duty cycle of AUX_SYSIF:TIMER2CLKCTL.SRC. +#define AUX_TIMER2_PULSETRIG_TRIG 0x00000001 +#define AUX_TIMER2_PULSETRIG_TRIG_BITN 0 +#define AUX_TIMER2_PULSETRIG_TRIG_M 0x00000001 +#define AUX_TIMER2_PULSETRIG_TRIG_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH0EVCFG +// +//***************************************************************************** +// Field: [7] EV3_GEN +// +// Event 3 enable. +// +// 0: Channel 0 does not control event 3. +// 1: Channel 0 controls event 3. +// +// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH0EVCFG_EV3_GEN 0x00000080 +#define AUX_TIMER2_CH0EVCFG_EV3_GEN_BITN 7 +#define AUX_TIMER2_CH0EVCFG_EV3_GEN_M 0x00000080 +#define AUX_TIMER2_CH0EVCFG_EV3_GEN_S 7 + +// Field: [6] EV2_GEN +// +// Event 2 enable. +// +// 0: Channel 0 does not control event 2. +// 1: Channel 0 controls event 2. +// +// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH0EVCFG_EV2_GEN 0x00000040 +#define AUX_TIMER2_CH0EVCFG_EV2_GEN_BITN 6 +#define AUX_TIMER2_CH0EVCFG_EV2_GEN_M 0x00000040 +#define AUX_TIMER2_CH0EVCFG_EV2_GEN_S 6 + +// Field: [5] EV1_GEN +// +// Event 1 enable. +// +// 0: Channel 0 does not control event 1. +// 1: Channel 0 controls event 1. +// +// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH0EVCFG_EV1_GEN 0x00000020 +#define AUX_TIMER2_CH0EVCFG_EV1_GEN_BITN 5 +#define AUX_TIMER2_CH0EVCFG_EV1_GEN_M 0x00000020 +#define AUX_TIMER2_CH0EVCFG_EV1_GEN_S 5 + +// Field: [4] EV0_GEN +// +// Event 0 enable. +// +// 0: Channel 0 does not control event 0. +// 1: Channel 0 controls event 0. +// +// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH0EVCFG_EV0_GEN 0x00000010 +#define AUX_TIMER2_CH0EVCFG_EV0_GEN_BITN 4 +#define AUX_TIMER2_CH0EVCFG_EV0_GEN_M 0x00000010 +#define AUX_TIMER2_CH0EVCFG_EV0_GEN_S 4 + +// Field: [3:0] CCACT +// +// Capture-Compare action. +// +// Capture-Compare action defines 15 different channel functions that utilize +// capture, compare, and zero events. +// ENUMs: +// PULSE_ON_CMP Pulse on compare repeatedly. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP Toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// SET_ON_CMP Set on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// CLR_ON_CMP Clear on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UP_PER +// for edge-aligned PWM generation. Duty cycle is +// given by: +// +// When CH0CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = +// CH0CC.VALUE / ( TARGET.VALUE + 1 ). +// +// When CH0CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 1. +// +// Enabled events are +// cleared when CH0CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UPDWN_PER +// for center-aligned PWM generation. Duty cycle +// is given by: +// +// When CH0CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = 1 - ( +// CH0CC.VALUE / TARGET.VALUE ). +// +// When CH0CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 0. +// +// Enabled events are set +// when CH0CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT Set on capture repeatedly. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH0CC.VALUE. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Select this function +// with no event enable. +// - Configure CH0CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// enable events. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. +// +// Continuously capture +// period and pulse width of the signal selected +// by CH0CCFG.CAPT_SRC relative to the signal edge +// given by CH0CCFG.EDGE. +// +// Set enabled events when +// CH0CC.VALUE contains signal period and +// CH0PCC.VALUE contains signal pulse width. +// +// Notes: +// - Make sure that you +// configure CH0CCFG.CAPT_SRC and CCACT when +// CTL.MODE equals DIS, then set CTL.MODE to +// UP_ONCE or UP_PER. +// - The counter restarts in +// the selected timer mode when CH0CC.VALUE +// contains the signal period. +// - If more than one +// channel uses this function, the channels will +// perform this function one at a time. The +// channel with lowest number has priority and +// performs the function first. Next measurement +// starts when current measurement completes +// successfully or times out. A timeout occurs +// when counter equals target. +// - If you want to observe +// a timeout event configure another channel to +// SET_ON_CAPT. +// +// Signal property +// requirements: +// - Signal Period >= 2 * ( +// 1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal Period <= 65535 +// * (1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal low and high +// phase >= (1 + PRECFG.CLKDIV ) * timer clock +// period. +// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_CMP_DIS Set on compare, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CH0CC.VALUE = CNTR.VALUE. +// - Disable channel. +// CLR_ON_CMP_DIS Clear on compare, and then disable channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are +// cleared when CH0CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are set +// when CH0CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT_DIS Set on capture, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH0CC.VALUE. +// - Disable channel. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Set CCACT to +// SET_ON_CAPT with no event enable. +// - Configure CH0CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// set CCACT to SET_ON_CAPT_DIS. Event enable is +// optional. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// DIS Disable channel. +#define AUX_TIMER2_CH0EVCFG_CCACT_W 4 +#define AUX_TIMER2_CH0EVCFG_CCACT_M 0x0000000F +#define AUX_TIMER2_CH0EVCFG_CCACT_S 0 +#define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP 0x0000000F +#define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP 0x0000000E +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP 0x0000000D +#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP 0x0000000C +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B +#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT 0x00000009 +#define AUX_TIMER2_CH0EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 +#define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 +#define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 +#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 +#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 +#define AUX_TIMER2_CH0EVCFG_CCACT_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH0CCFG +// +//***************************************************************************** +// Field: [6:1] CAPT_SRC +// +// Select capture signal source from the asynchronous AUX event bus. +// +// The selected signal enters the edge-detection circuit. False capture events +// can occur when: +// - the edge-detection circuit contains expired signal samples and the circuit +// is enabled without flush as described in CH0EVCFG +// - this register is reconfigured while CTL.MODE is different from DIS. +// +// You can avoid false capture events. When wanted channel function is: +// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH0EVCFG.CCACT. +// - SET_ON_CAPT, see description for SET_ON_CAPT in CH0EVCFG.CCACT. +// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in +// CH0EVCFG.CCACT. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_W 6 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_M 0x0000007E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_S 1 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_NO_EVENT 0x0000007E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPB 0x0000005E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPA 0x0000005C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_EV 0x00000056 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_ACLK_REF 0x00000054 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_PWR_DWN 0x0000004E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_SCLK_LF 0x0000004C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MANUAL_EV 0x00000040 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO31 0x0000003E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO30 0x0000003C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO29 0x0000003A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO28 0x00000038 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO27 0x00000036 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO26 0x00000034 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO25 0x00000032 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO24 0x00000030 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO23 0x0000002E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO22 0x0000002C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO21 0x0000002A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO20 0x00000028 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO19 0x00000026 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO18 0x00000024 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO17 0x00000022 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO16 0x00000020 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO15 0x0000001E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO14 0x0000001C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO13 0x0000001A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO12 0x00000018 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO11 0x00000016 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO10 0x00000014 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO9 0x00000012 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO8 0x00000010 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO7 0x0000000E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO6 0x0000000C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO5 0x0000000A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO4 0x00000008 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO3 0x00000006 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO2 0x00000004 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO1 0x00000002 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO0 0x00000000 + +// Field: [0] EDGE +// +// Edge configuration. +// +// Channel captures counter value at selected edge on signal source selected by +// CAPT_SRC. See CH0EVCFG.CCACT. +// ENUMs: +// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. +// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. +#define AUX_TIMER2_CH0CCFG_EDGE 0x00000001 +#define AUX_TIMER2_CH0CCFG_EDGE_BITN 0 +#define AUX_TIMER2_CH0CCFG_EDGE_M 0x00000001 +#define AUX_TIMER2_CH0CCFG_EDGE_S 0 +#define AUX_TIMER2_CH0CCFG_EDGE_RISING 0x00000001 +#define AUX_TIMER2_CH0CCFG_EDGE_FALLING 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH0PCC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Pipeline Capture Compare value. +// +// 16-bit user defined pipeline compare value or channel-updated capture value. +// +// Compare mode: +// An update of VALUE will be transferred to CH0CC.VALUE when the next +// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for +// PWM generation and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When CH0EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the +// width of the low or high phase of the selected signal. This is specified by +// CH0CCFG.EDGE and CH0CCFG.CAPT_SRC. +#define AUX_TIMER2_CH0PCC_VALUE_W 16 +#define AUX_TIMER2_CH0PCC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH0PCC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH0CC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Capture Compare value. +// +// 16-bit user defined compare value or channel-updated capture value. +// +// Compare mode: +// VALUE is compared against CNTR.VALUE and an event is generated as specified +// by CH0EVCFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VALUE when a capture event occurs. +// CH0EVCFG.CCACT determines if VALUE is a signal period or a regular capture +// value. +#define AUX_TIMER2_CH0CC_VALUE_W 16 +#define AUX_TIMER2_CH0CC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH0CC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH1EVCFG +// +//***************************************************************************** +// Field: [7] EV3_GEN +// +// Event 3 enable. +// +// 0: Channel 1 does not control event 3. +// 1: Channel 1 controls event 3. +// +// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH1EVCFG_EV3_GEN 0x00000080 +#define AUX_TIMER2_CH1EVCFG_EV3_GEN_BITN 7 +#define AUX_TIMER2_CH1EVCFG_EV3_GEN_M 0x00000080 +#define AUX_TIMER2_CH1EVCFG_EV3_GEN_S 7 + +// Field: [6] EV2_GEN +// +// Event 2 enable. +// +// 0: Channel 1 does not control event 2. +// 1: Channel 1 controls event 2. +// +// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH1EVCFG_EV2_GEN 0x00000040 +#define AUX_TIMER2_CH1EVCFG_EV2_GEN_BITN 6 +#define AUX_TIMER2_CH1EVCFG_EV2_GEN_M 0x00000040 +#define AUX_TIMER2_CH1EVCFG_EV2_GEN_S 6 + +// Field: [5] EV1_GEN +// +// Event 1 enable. +// +// 0: Channel 1 does not control event 1. +// 1: Channel 1 controls event 1. +// +// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH1EVCFG_EV1_GEN 0x00000020 +#define AUX_TIMER2_CH1EVCFG_EV1_GEN_BITN 5 +#define AUX_TIMER2_CH1EVCFG_EV1_GEN_M 0x00000020 +#define AUX_TIMER2_CH1EVCFG_EV1_GEN_S 5 + +// Field: [4] EV0_GEN +// +// Event 0 enable. +// +// 0: Channel 1 does not control event 0. +// 1: Channel 1 controls event 0. +// +// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH1EVCFG_EV0_GEN 0x00000010 +#define AUX_TIMER2_CH1EVCFG_EV0_GEN_BITN 4 +#define AUX_TIMER2_CH1EVCFG_EV0_GEN_M 0x00000010 +#define AUX_TIMER2_CH1EVCFG_EV0_GEN_S 4 + +// Field: [3:0] CCACT +// +// Capture-Compare action. +// +// Capture-Compare action defines 15 different channel functions that utilize +// capture, compare, and zero events. +// ENUMs: +// PULSE_ON_CMP Pulse on compare repeatedly. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP Toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// SET_ON_CMP Set on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// CLR_ON_CMP Clear on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UP_PER +// for edge-aligned PWM generation. Duty cycle is +// given by: +// +// When CH1CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = +// CH1CC.VALUE / ( TARGET.VALUE + 1 ). +// +// When CH1CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 1. +// +// Enabled events are +// cleared when CH1CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UPDWN_PER +// for center-aligned PWM generation. Duty cycle +// is given by: +// +// When CH1CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = 1 - ( +// CH1CC.VALUE / TARGET.VALUE ). +// +// When CH1CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 0. +// +// Enabled events are set +// when CH1CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT Set on capture repeatedly. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH1CC.VALUE. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Select this function +// with no event enable. +// - Configure CH1CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// enable events. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. +// +// Continuously capture +// period and pulse width of the signal selected +// by CH1CCFG.CAPT_SRC relative to the signal edge +// given by CH1CCFG.EDGE. +// +// Set enabled events when +// CH1CC.VALUE contains signal period and +// CH1PCC.VALUE contains signal pulse width. +// +// Notes: +// - Make sure that you +// configure CH1CCFG.CAPT_SRC and CCACT when +// CTL.MODE equals DIS, then set CTL.MODE to +// UP_ONCE or UP_PER. +// - The counter restarts in +// the selected timer mode when CH1CC.VALUE +// contains the signal period. +// - If more than one +// channel uses this function, the channels will +// perform this function one at a time. The +// channel with lowest number has priority and +// performs the function first. Next measurement +// starts when current measurement completes +// successfully or times out. A timeout occurs +// when counter equals target. +// - If you want to observe +// a timeout event configure another channel to +// SET_ON_CAPT. +// +// Signal property +// requirements: +// - Signal Period >= 2 * ( +// 1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal Period <= 65535 +// * (1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal low and high +// phase >= (1 + PRECFG.CLKDIV ) * timer clock +// period. +// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_CMP_DIS Set on compare, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CH1CC.VALUE = CNTR.VALUE. +// - Disable channel. +// CLR_ON_CMP_DIS Clear on compare, and then disable channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are +// cleared when CH1CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are set +// when CH1CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT_DIS Set on capture, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH1CC.VALUE. +// - Disable channel. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Set CCACT to +// SET_ON_CAPT with no event enable. +// - Configure CH1CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// set CCACT to SET_ON_CAPT_DIS. Event enable is +// optional. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// DIS Disable channel. +#define AUX_TIMER2_CH1EVCFG_CCACT_W 4 +#define AUX_TIMER2_CH1EVCFG_CCACT_M 0x0000000F +#define AUX_TIMER2_CH1EVCFG_CCACT_S 0 +#define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP 0x0000000F +#define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP 0x0000000E +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP 0x0000000D +#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP 0x0000000C +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B +#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT 0x00000009 +#define AUX_TIMER2_CH1EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 +#define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 +#define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 +#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 +#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 +#define AUX_TIMER2_CH1EVCFG_CCACT_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH1CCFG +// +//***************************************************************************** +// Field: [6:1] CAPT_SRC +// +// Select capture signal source from the asynchronous AUX event bus. +// +// The selected signal enters the edge-detection circuit. False capture events +// can occur when: +// - the edge-detection circuit contains expired signal samples and the circuit +// is enabled without flush as described in CH1EVCFG +// - this register is reconfigured while CTL.MODE is different from DIS. +// +// You can avoid false capture events. When wanted channel function is: +// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH1EVCFG.CCACT. +// - SET_ON_CAPT, see description for SET_ON_CAPT in CH1EVCFG.CCACT. +// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in +// CH1EVCFG.CCACT. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_W 6 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_M 0x0000007E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_S 1 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_NO_EVENT 0x0000007E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPB 0x0000005E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPA 0x0000005C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_EV 0x00000056 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_ACLK_REF 0x00000054 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_PWR_DWN 0x0000004E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_SCLK_LF 0x0000004C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MANUAL_EV 0x00000040 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO31 0x0000003E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO30 0x0000003C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO29 0x0000003A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO28 0x00000038 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO27 0x00000036 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO26 0x00000034 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO25 0x00000032 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO24 0x00000030 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO23 0x0000002E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO22 0x0000002C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO21 0x0000002A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO20 0x00000028 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO19 0x00000026 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO18 0x00000024 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO17 0x00000022 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO16 0x00000020 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO15 0x0000001E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO14 0x0000001C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO13 0x0000001A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO12 0x00000018 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO11 0x00000016 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO10 0x00000014 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO9 0x00000012 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO8 0x00000010 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO7 0x0000000E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO6 0x0000000C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO5 0x0000000A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO4 0x00000008 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO3 0x00000006 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO2 0x00000004 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO1 0x00000002 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO0 0x00000000 + +// Field: [0] EDGE +// +// Edge configuration. +// +// Channel captures counter value at selected edge on signal source selected by +// CAPT_SRC. See CH1EVCFG.CCACT. +// ENUMs: +// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. +// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. +#define AUX_TIMER2_CH1CCFG_EDGE 0x00000001 +#define AUX_TIMER2_CH1CCFG_EDGE_BITN 0 +#define AUX_TIMER2_CH1CCFG_EDGE_M 0x00000001 +#define AUX_TIMER2_CH1CCFG_EDGE_S 0 +#define AUX_TIMER2_CH1CCFG_EDGE_RISING 0x00000001 +#define AUX_TIMER2_CH1CCFG_EDGE_FALLING 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH1PCC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Pipeline Capture Compare value. +// +// 16-bit user defined pipeline compare value or channel-updated capture value. +// +// Compare mode: +// An update of VALUE will be transferred to CH1CC.VALUE when the next +// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for +// PWM generation and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When CH1EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the +// width of the low or high phase of the selected signal. This is specified by +// CH1CCFG.EDGE and CH1CCFG.CAPT_SRC. +#define AUX_TIMER2_CH1PCC_VALUE_W 16 +#define AUX_TIMER2_CH1PCC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH1PCC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH1CC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Capture Compare value. +// +// 16-bit user defined compare value or channel-updated capture value. +// +// Compare mode: +// VALUE is compared against CNTR.VALUE and an event is generated as specified +// by CH1EVCFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VALUE when a capture event occurs. +// CH1EVCFG.CCACT determines if VALUE is a signal period or a regular capture +// value. +#define AUX_TIMER2_CH1CC_VALUE_W 16 +#define AUX_TIMER2_CH1CC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH1CC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH2EVCFG +// +//***************************************************************************** +// Field: [7] EV3_GEN +// +// Event 3 enable. +// +// 0: Channel 2 does not control event 3. +// 1: Channel 2 controls event 3. +// +// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH2EVCFG_EV3_GEN 0x00000080 +#define AUX_TIMER2_CH2EVCFG_EV3_GEN_BITN 7 +#define AUX_TIMER2_CH2EVCFG_EV3_GEN_M 0x00000080 +#define AUX_TIMER2_CH2EVCFG_EV3_GEN_S 7 + +// Field: [6] EV2_GEN +// +// Event 2 enable. +// +// 0: Channel 2 does not control event 2. +// 1: Channel 2 controls event 2. +// +// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH2EVCFG_EV2_GEN 0x00000040 +#define AUX_TIMER2_CH2EVCFG_EV2_GEN_BITN 6 +#define AUX_TIMER2_CH2EVCFG_EV2_GEN_M 0x00000040 +#define AUX_TIMER2_CH2EVCFG_EV2_GEN_S 6 + +// Field: [5] EV1_GEN +// +// Event 1 enable. +// +// 0: Channel 2 does not control event 1. +// 1: Channel 2 controls event 1. +// +// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH2EVCFG_EV1_GEN 0x00000020 +#define AUX_TIMER2_CH2EVCFG_EV1_GEN_BITN 5 +#define AUX_TIMER2_CH2EVCFG_EV1_GEN_M 0x00000020 +#define AUX_TIMER2_CH2EVCFG_EV1_GEN_S 5 + +// Field: [4] EV0_GEN +// +// Event 0 enable. +// +// 0: Channel 2 does not control event 0. +// 1: Channel 2 controls event 0. +// +// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH2EVCFG_EV0_GEN 0x00000010 +#define AUX_TIMER2_CH2EVCFG_EV0_GEN_BITN 4 +#define AUX_TIMER2_CH2EVCFG_EV0_GEN_M 0x00000010 +#define AUX_TIMER2_CH2EVCFG_EV0_GEN_S 4 + +// Field: [3:0] CCACT +// +// Capture-Compare action. +// +// Capture-Compare action defines 15 different channel functions that utilize +// capture, compare, and zero events. +// ENUMs: +// PULSE_ON_CMP Pulse on compare repeatedly. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP Toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// SET_ON_CMP Set on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// CLR_ON_CMP Clear on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UP_PER +// for edge-aligned PWM generation. Duty cycle is +// given by: +// +// When CH2CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = +// CH2CC.VALUE / ( TARGET.VALUE + 1 ). +// +// When CH2CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 1. +// +// Enabled events are +// cleared when CH2CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UPDWN_PER +// for center-aligned PWM generation. Duty cycle +// is given by: +// +// When CH2CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = 1 - ( +// CH2CC.VALUE / TARGET.VALUE ). +// +// When CH2CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 0. +// +// Enabled events are set +// when CH2CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT Set on capture repeatedly. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH2CC.VALUE. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Select this function +// with no event enable. +// - Configure CH2CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// enable events. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. +// +// Continuously capture +// period and pulse width of the signal selected +// by CH2CCFG.CAPT_SRC relative to the signal edge +// given by CH2CCFG.EDGE. +// +// Set enabled events when +// CH2CC.VALUE contains signal period and +// CH2PCC.VALUE contains signal pulse width. +// +// Notes: +// - Make sure that you +// configure CH2CCFG.CAPT_SRC and CCACT when +// CTL.MODE equals DIS, then set CTL.MODE to +// UP_ONCE or UP_PER. +// - The counter restarts in +// the selected timer mode when CH2CC.VALUE +// contains the signal period. +// - If more than one +// channel uses this function, the channels will +// perform this function one at a time. The +// channel with lowest number has priority and +// performs the function first. Next measurement +// starts when current measurement completes +// successfully or times out. A timeout occurs +// when counter equals target. +// - If you want to observe +// a timeout event configure another channel to +// SET_ON_CAPT. +// +// Signal property +// requirements: +// - Signal Period >= 2 * ( +// 1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal Period <= 65535 +// * (1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal low and high +// phase >= (1 + PRECFG.CLKDIV ) * timer clock +// period. +// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_CMP_DIS Set on compare, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CH2CC.VALUE = CNTR.VALUE. +// - Disable channel. +// CLR_ON_CMP_DIS Clear on compare, and then disable channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are +// cleared when CH2CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are set +// when CH2CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT_DIS Set on capture, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH2CC.VALUE. +// - Disable channel. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Set to SET_ON_CAPT +// with no event enable. +// - Configure CH2CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// set to SET_ON_CAPT_DIS. Event enable is +// optional. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// DIS Disable channel. +#define AUX_TIMER2_CH2EVCFG_CCACT_W 4 +#define AUX_TIMER2_CH2EVCFG_CCACT_M 0x0000000F +#define AUX_TIMER2_CH2EVCFG_CCACT_S 0 +#define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP 0x0000000F +#define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP 0x0000000E +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP 0x0000000D +#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP 0x0000000C +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B +#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT 0x00000009 +#define AUX_TIMER2_CH2EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 +#define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 +#define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 +#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 +#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 +#define AUX_TIMER2_CH2EVCFG_CCACT_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH2CCFG +// +//***************************************************************************** +// Field: [6:1] CAPT_SRC +// +// Select capture signal source from the asynchronous AUX event bus. +// +// The selected signal enters the edge-detection circuit. False capture events +// can occur when: +// - the edge-detection circuit contains expired signal samples and the circuit +// is enabled without flush as described in CH2EVCFG +// - this register is reconfigured while CTL.MODE is different from DIS. +// +// You can avoid false capture events. When wanted channel function is: +// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH2EVCFG.CCACT. +// - SET_ON_CAPT, see description for SET_ON_CAPT in CH2EVCFG.CCACT. +// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in +// CH2EVCFG.CCACT. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_W 6 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_M 0x0000007E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_S 1 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_NO_EVENT 0x0000007E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPB 0x0000005E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPA 0x0000005C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_EV 0x00000056 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_ACLK_REF 0x00000054 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_PWR_DWN 0x0000004E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_SCLK_LF 0x0000004C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MANUAL_EV 0x00000040 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO31 0x0000003E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO30 0x0000003C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO29 0x0000003A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO28 0x00000038 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO27 0x00000036 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO26 0x00000034 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO25 0x00000032 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO24 0x00000030 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO23 0x0000002E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO22 0x0000002C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO21 0x0000002A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO20 0x00000028 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO19 0x00000026 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO18 0x00000024 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO17 0x00000022 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO16 0x00000020 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO15 0x0000001E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO14 0x0000001C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO13 0x0000001A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO12 0x00000018 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO11 0x00000016 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO10 0x00000014 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO9 0x00000012 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO8 0x00000010 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO7 0x0000000E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO6 0x0000000C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO5 0x0000000A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO4 0x00000008 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO3 0x00000006 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO2 0x00000004 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO1 0x00000002 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO0 0x00000000 + +// Field: [0] EDGE +// +// Edge configuration. +// +// Channel captures counter value at selected edge on signal source selected by +// CAPT_SRC. See CH2EVCFG.CCACT. +// ENUMs: +// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. +// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. +#define AUX_TIMER2_CH2CCFG_EDGE 0x00000001 +#define AUX_TIMER2_CH2CCFG_EDGE_BITN 0 +#define AUX_TIMER2_CH2CCFG_EDGE_M 0x00000001 +#define AUX_TIMER2_CH2CCFG_EDGE_S 0 +#define AUX_TIMER2_CH2CCFG_EDGE_RISING 0x00000001 +#define AUX_TIMER2_CH2CCFG_EDGE_FALLING 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH2PCC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Pipeline Capture Compare value. +// +// 16-bit user defined pipeline compare value or channel-updated capture value. +// +// Compare mode: +// An update of VALUE will be transferred to CH2CC.VALUE when the next +// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for +// PWM generation and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When CH2EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the +// width of the low or high phase of the selected signal. This is specified by +// CH2CCFG.EDGE and CH2CCFG.CAPT_SRC. +#define AUX_TIMER2_CH2PCC_VALUE_W 16 +#define AUX_TIMER2_CH2PCC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH2PCC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH2CC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Capture Compare value. +// +// 16-bit user defined compare value or channel-updated capture value. +// +// Compare mode: +// VALUE is compared against CNTR.VALUE and an event is generated as specified +// by CH2EVCFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VALUE when a capture event occurs. +// CH2EVCFG.CCACT determines if VALUE is a signal period or a regular capture +// value. +#define AUX_TIMER2_CH2CC_VALUE_W 16 +#define AUX_TIMER2_CH2CC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH2CC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH3EVCFG +// +//***************************************************************************** +// Field: [7] EV3_GEN +// +// Event 3 enable. +// +// 0: Channel 3 does not control event 3. +// 1: Channel 3 controls event 3. +// +// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH3EVCFG_EV3_GEN 0x00000080 +#define AUX_TIMER2_CH3EVCFG_EV3_GEN_BITN 7 +#define AUX_TIMER2_CH3EVCFG_EV3_GEN_M 0x00000080 +#define AUX_TIMER2_CH3EVCFG_EV3_GEN_S 7 + +// Field: [6] EV2_GEN +// +// Event 2 enable. +// +// 0: Channel 3 does not control event 2. +// 1: Channel 3 controls event 2. +// +// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH3EVCFG_EV2_GEN 0x00000040 +#define AUX_TIMER2_CH3EVCFG_EV2_GEN_BITN 6 +#define AUX_TIMER2_CH3EVCFG_EV2_GEN_M 0x00000040 +#define AUX_TIMER2_CH3EVCFG_EV2_GEN_S 6 + +// Field: [5] EV1_GEN +// +// Event 1 enable. +// +// 0: Channel 3 does not control event 1. +// 1: Channel 3 controls event 1. +// +// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH3EVCFG_EV1_GEN 0x00000020 +#define AUX_TIMER2_CH3EVCFG_EV1_GEN_BITN 5 +#define AUX_TIMER2_CH3EVCFG_EV1_GEN_M 0x00000020 +#define AUX_TIMER2_CH3EVCFG_EV1_GEN_S 5 + +// Field: [4] EV0_GEN +// +// Event 0 enable. +// +// 0: Channel 3 does not control event 0. +// 1: Channel 3 controls event 0. +// +// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH3EVCFG_EV0_GEN 0x00000010 +#define AUX_TIMER2_CH3EVCFG_EV0_GEN_BITN 4 +#define AUX_TIMER2_CH3EVCFG_EV0_GEN_M 0x00000010 +#define AUX_TIMER2_CH3EVCFG_EV0_GEN_S 4 + +// Field: [3:0] CCACT +// +// Capture-Compare action. +// +// Capture-Compare action defines 15 different channel functions that utilize +// capture, compare, and zero events. +// ENUMs: +// PULSE_ON_CMP Pulse on compare repeatedly. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP Toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// SET_ON_CMP Set on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// CLR_ON_CMP Clear on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UP_PER +// for edge-aligned PWM generation. Duty cycle is +// given by: +// +// When CH3CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = +// CH3CC.VALUE / ( TARGET.VALUE + 1 ). +// +// When CH3CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 1. +// +// Enabled events are +// cleared when CH3CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UPDWN_PER +// for center-aligned PWM generation. Duty cycle +// is given by: +// +// When CH3CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = 1 - ( +// CH3CC.VALUE / TARGET.VALUE ). +// +// When CH3CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 0. +// +// Enabled events are set +// when CH3CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT Set on capture repeatedly. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH3CC.VALUE. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Select this function +// with no event enable. +// - Configure CH3CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// enable events. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. +// +// Continuously capture +// period and pulse width of the signal selected +// by CH3CCFG.CAPT_SRC relative to the signal edge +// given by CH3CCFG.EDGE. +// +// Set enabled events when +// CH3CC.VALUE contains signal period and +// CH3PCC.VALUE contains signal pulse width. +// +// Notes: +// - Make sure that you +// configure CH3CCFG.CAPT_SRC and CCACT when +// CTL.MODE equals DIS, then set CTL.MODE to +// UP_ONCE or UP_PER. +// - The counter restarts in +// the selected timer mode when CH3CC.VALUE +// contains the signal period. +// - If more than one +// channel uses this function, the channels will +// perform this function one at a time. The +// channel with lowest number has priority and +// performs the function first. Next measurement +// starts when current measurement completes +// successfully or times out. A timeout occurs +// when counter equals target. +// - If you want to observe +// a timeout event configure another channel to +// SET_ON_CAPT. +// +// Signal property +// requirements: +// - Signal Period >= 2 * ( +// 1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal Period <= 65535 +// * (1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal low and high +// phase >= (1 + PRECFG.CLKDIV ) * timer clock +// period. +// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_CMP_DIS Set on compare, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CH3CC.VALUE = CNTR.VALUE. +// - Disable channel. +// CLR_ON_CMP_DIS Clear on compare, and then disable channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are +// cleared when CH3CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are set +// when CH3CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT_DIS Set on capture, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH3CC.VALUE. +// - Disable channel. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Set CCACT to +// SET_ON_CAPT with no event enable. +// - Configure CH3CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// set CCACT to SET_ON_CAPT_DIS. Event enable is +// optional. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// DIS Disable channel. +#define AUX_TIMER2_CH3EVCFG_CCACT_W 4 +#define AUX_TIMER2_CH3EVCFG_CCACT_M 0x0000000F +#define AUX_TIMER2_CH3EVCFG_CCACT_S 0 +#define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP 0x0000000F +#define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP 0x0000000E +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP 0x0000000D +#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP 0x0000000C +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B +#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT 0x00000009 +#define AUX_TIMER2_CH3EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 +#define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 +#define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 +#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 +#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 +#define AUX_TIMER2_CH3EVCFG_CCACT_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH3CCFG +// +//***************************************************************************** +// Field: [6:1] CAPT_SRC +// +// Select capture signal source from the asynchronous AUX event bus. +// +// The selected signal enters the edge-detection circuit. False capture events +// can occur when: +// - the edge-detection circuit contains expired signal samples and the circuit +// is enabled without flush as described in CH3EVCFG +// - this register is reconfigured while CTL.MODE is different from DIS. +// +// You can avoid false capture events. When wanted channel function: +// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH3EVCFG.CCACT. +// - SET_ON_CAPT, see description for SET_ON_CAPT in CH3EVCFG.CCACT. +// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in +// CH3EVCFG.CCACT. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_W 6 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_M 0x0000007E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_S 1 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_NO_EVENT 0x0000007E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPB 0x0000005E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPA 0x0000005C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_EV 0x00000056 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_ACLK_REF 0x00000054 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_PWR_DWN 0x0000004E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_SCLK_LF 0x0000004C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MANUAL_EV 0x00000040 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO31 0x0000003E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO30 0x0000003C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO29 0x0000003A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO28 0x00000038 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO27 0x00000036 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO26 0x00000034 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO25 0x00000032 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO24 0x00000030 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO23 0x0000002E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO22 0x0000002C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO21 0x0000002A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO20 0x00000028 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO19 0x00000026 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO18 0x00000024 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO17 0x00000022 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO16 0x00000020 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO15 0x0000001E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO14 0x0000001C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO13 0x0000001A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO12 0x00000018 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO11 0x00000016 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO10 0x00000014 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO9 0x00000012 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO8 0x00000010 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO7 0x0000000E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO6 0x0000000C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO5 0x0000000A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO4 0x00000008 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO3 0x00000006 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO2 0x00000004 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO1 0x00000002 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO0 0x00000000 + +// Field: [0] EDGE +// +// Edge configuration. +// +// Channel captures counter value at selected edge on signal source selected by +// CAPT_SRC. See CH3EVCFG.CCACT. +// ENUMs: +// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. +// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. +#define AUX_TIMER2_CH3CCFG_EDGE 0x00000001 +#define AUX_TIMER2_CH3CCFG_EDGE_BITN 0 +#define AUX_TIMER2_CH3CCFG_EDGE_M 0x00000001 +#define AUX_TIMER2_CH3CCFG_EDGE_S 0 +#define AUX_TIMER2_CH3CCFG_EDGE_RISING 0x00000001 +#define AUX_TIMER2_CH3CCFG_EDGE_FALLING 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH3PCC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Pipeline Capture Compare value. +// +// 16-bit user defined pipeline compare value or channel-updated capture value. +// +// Compare mode: +// An update of VALUE will be transferred to CH3CC.VALUE when the next +// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for +// PWM generation and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When CH3EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the +// width of the low or high phase of the selected signal. This is specified by +// CH3CCFG.EDGE and CH3CCFG.CAPT_SRC. +#define AUX_TIMER2_CH3PCC_VALUE_W 16 +#define AUX_TIMER2_CH3PCC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH3PCC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH3CC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Capture Compare value. +// +// 16-bit user defined compare value or channel-updated capture value. +// +// Compare mode: +// VALUE is compared against CNTR.VALUE and an event is generated as specified +// by CH3EVCFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VALUE when a capture event occurs. +// CH3EVCFG.CCACT determines if VALUE is a signal period or a regular capture +// value. +#define AUX_TIMER2_CH3CC_VALUE_W 16 +#define AUX_TIMER2_CH3CC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH3CC_VALUE_S 0 + + +#endif // __AUX_TIMER2__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h new file mode 100644 index 0000000..fc5a834 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h @@ -0,0 +1,1910 @@ +/****************************************************************************** +* Filename: hw_ccfg_h +* Revised: 2018-10-19 08:48:09 +0200 (Fri, 19 Oct 2018) +* Revision: 52957 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CCFG_H__ +#define __HW_CCFG_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CCFG component +// +//***************************************************************************** +// Extern LF clock configuration +#define CCFG_O_EXT_LF_CLK 0x00001FA8 + +// Mode Configuration 1 +#define CCFG_O_MODE_CONF_1 0x00001FAC + +// CCFG Size and Disable Flags +#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00001FB0 + +// Mode Configuration 0 +#define CCFG_O_MODE_CONF 0x00001FB4 + +// Voltage Load 0 +#define CCFG_O_VOLT_LOAD_0 0x00001FB8 + +// Voltage Load 1 +#define CCFG_O_VOLT_LOAD_1 0x00001FBC + +// Real Time Clock Offset +#define CCFG_O_RTC_OFFSET 0x00001FC0 + +// Frequency Offset +#define CCFG_O_FREQ_OFFSET 0x00001FC4 + +// IEEE MAC Address 0 +#define CCFG_O_IEEE_MAC_0 0x00001FC8 + +// IEEE MAC Address 1 +#define CCFG_O_IEEE_MAC_1 0x00001FCC + +// IEEE BLE Address 0 +#define CCFG_O_IEEE_BLE_0 0x00001FD0 + +// IEEE BLE Address 1 +#define CCFG_O_IEEE_BLE_1 0x00001FD4 + +// Bootloader Configuration +#define CCFG_O_BL_CONFIG 0x00001FD8 + +// Erase Configuration +#define CCFG_O_ERASE_CONF 0x00001FDC + +// TI Options +#define CCFG_O_CCFG_TI_OPTIONS 0x00001FE0 + +// Test Access Points Enable 0 +#define CCFG_O_CCFG_TAP_DAP_0 0x00001FE4 + +// Test Access Points Enable 1 +#define CCFG_O_CCFG_TAP_DAP_1 0x00001FE8 + +// Image Valid +#define CCFG_O_IMAGE_VALID_CONF 0x00001FEC + +// Protect Sectors 0-31 +#define CCFG_O_CCFG_PROT_31_0 0x00001FF0 + +// Protect Sectors 32-63 +#define CCFG_O_CCFG_PROT_63_32 0x00001FF4 + +// Protect Sectors 64-95 +#define CCFG_O_CCFG_PROT_95_64 0x00001FF8 + +// Protect Sectors 96-127 +#define CCFG_O_CCFG_PROT_127_96 0x00001FFC + +//***************************************************************************** +// +// Register: CCFG_O_EXT_LF_CLK +// +//***************************************************************************** +// Field: [31:24] DIO +// +// Unsigned integer, selecting the DIO to supply external 32kHz clock as +// SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO +// will be marked as reserved by the pin driver (TI-RTOS environment) and hence +// not selectable for other usage. +#define CCFG_EXT_LF_CLK_DIO_W 8 +#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 +#define CCFG_EXT_LF_CLK_DIO_S 24 + +// Field: [23:0] RTC_INCREMENT +// +// Unsigned integer, defining the input frequency of the external clock and is +// written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: +// EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: +// RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_MODE_CONF_1 +// +//***************************************************************************** +// Field: [23:20] ALT_DCDC_VMIN +// +// Minimum voltage for when DC/DC should be used if alternate DC/DC setting is +// enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). +// Voltage = (28 + ALT_DCDC_VMIN) / 16. +// 0: 1.75V +// 1: 1.8125V +// ... +// 14: 2.625V +// 15: 2.6875V +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 + +// Field: [19] ALT_DCDC_DITHER_EN +// +// Enable DC/DC dithering if alternate DC/DC setting is enabled +// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). +// 0: Dither disable +// 1: Dither enable +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 + +// Field: [18:16] ALT_DCDC_IPEAK +// +// Inductor peak current if alternate DC/DC setting is enabled +// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external +// inductor! +// Peak current = 31 + ( 4 * ALT_DCDC_IPEAK ) : +// 0: 31mA (min) +// ... +// 4: 47mA +// ... +// 7: 59mA (max) +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 + +// Field: [15:12] DELTA_IBIAS_INIT +// +// Signed delta value for IBIAS_INIT. Delta value only applies if +// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +// See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 + +// Field: [11:8] DELTA_IBIAS_OFFSET +// +// Signed delta value for IBIAS_OFFSET. Delta value only applies if +// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +// See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 + +// Field: [7:0] XOSC_MAX_START +// +// Unsigned value of maximum XOSC startup time (worst case) in units of 100us. +// Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 +#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF +#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_SIZE_AND_DIS_FLAGS +// +//***************************************************************************** +// Field: [31:16] SIZE_OF_CCFG +// +// Total size of CCFG in bytes. +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 + +// Field: [15:4] DISABLE_FLAGS +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 + +// Field: [3] DIS_TCXO +// +// Disable TCXO. +// 0: TCXO functionality enabled. +// 1: TCXO functionality disabled. +// Note: +// An external TCXO is required if DIS_TCXO = 0. +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 + +// Field: [2] DIS_GPRAM +// +// Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). +// 0: GPRAM is enabled and hence CACHE disabled. +// 1: GPRAM is disabled and instead CACHE is enabled (default). +// Notes: +// - Disabling CACHE will reduce CPU execution speed (up to 60%). +// - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if +// enabled. +// See: +// VIMS:CTL.MODE +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 + +// Field: [1] DIS_ALT_DCDC_SETTING +// +// Disable alternate DC/DC settings. +// 0: Enable alternate DC/DC settings. +// 1: Disable alternate DC/DC settings. +// See: +// MODE_CONF_1.ALT_DCDC_VMIN +// MODE_CONF_1.ALT_DCDC_DITHER_EN +// MODE_CONF_1.ALT_DCDC_IPEAK +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 + +// Field: [0] DIS_XOSC_OVR +// +// Disable XOSC override functionality. +// 0: Enable XOSC override functionality. +// 1: Disable XOSC override functionality. +// See: +// MODE_CONF_1.DELTA_IBIAS_INIT +// MODE_CONF_1.DELTA_IBIAS_OFFSET +// MODE_CONF_1.XOSC_MAX_START +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_MODE_CONF +// +//***************************************************************************** +// Field: [31:28] VDDR_TRIM_SLEEP_DELTA +// +// Signed delta value to apply to the +// VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H. +// 0x8 (-8) : Delta = -7 +// ... +// 0xF (-1) : Delta = 0 +// 0x0 (0) : Delta = +1 +// ... +// 0x7 (7) : Delta = +8 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 + +// Field: [27] DCDC_RECHARGE +// +// DC/DC during recharge in powerdown. +// 0: Use the DC/DC during recharge in powerdown. +// 1: Do not use the DC/DC during recharge in powerdown (default). +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 +#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 + +// Field: [26] DCDC_ACTIVE +// +// DC/DC in active mode. +// 0: Use the DC/DC during active mode. +// 1: Do not use the DC/DC during active mode (default). +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 +#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 + +// Field: [25] VDDR_EXT_LOAD +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 + +// Field: [24] VDDS_BOD_LEVEL +// +// VDDS BOD level. +// 0: VDDS BOD level is 2.0V (necessary for external load mode, or for maximum +// PA output power on CC13xx). +// 1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default). +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 + +// Field: [23:22] SCLK_LF_OPTION +// +// Select source for SCLK_LF. +// ENUMs: +// RCOSC_LF Low frequency RCOSC (default) +// XOSC_LF 32.768kHz low frequency XOSC +// EXTERNAL_LF External low frequency clock on DIO defined by +// EXT_LF_CLK.DIO. The RTC tick speed +// AON_RTC:SUBSECINC is updated to +// EXT_LF_CLK.RTC_INCREMENT (done in the +// trimDevice() xxWare boot function). External +// clock must always be running when the chip is +// in standby for VDDR recharge timing. +// XOSC_HF_DLF 31.25kHz clock derived from 24MHz XOSC (dividing +// by 768 in HW). The RTC tick speed +// [AON_RTC.SUBSECINC.*] is updated to 0x8637BD, +// corresponding to a 31.25kHz clock (done in the +// trimDevice() xxWare boot function). Standby +// power mode is not supported when using this +// clock source. +#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 + +// Field: [21] VDDR_TRIM_SLEEP_TC +// +// 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated +// 0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time +// standby mode is entered. This improves low-temperature RCOSC_LF frequency +// stability in standby mode. +// +// When temperature compensation is performed, the delta is calculates this +// way: +// Delta = max (delta, min(8, floor(62-temp)/8)) +// Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current +// temperature in degrees C. +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 + +// Field: [20] RTC_COMP +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_RTC_COMP 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_BITN 20 +#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_S 20 + +// Field: [19:18] XOSC_FREQ +// +// Selects high precision HF oscillator (activated when using the radio). +// ENUMs: +// 24M 24 MHz XOSC_HF +// 48M 48 MHz XOSC_HF +// HPOSC HPOSC +#define CCFG_MODE_CONF_XOSC_FREQ_W 2 +#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_S 18 +#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 +#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 + +// Field: [17] XOSC_CAP_MOD +// +// Enable modification (delta) to XOSC cap-array. Value specified in +// XOSC_CAPARRAY_DELTA. +// 0: Apply cap-array delta +// 1: Do not apply cap-array delta (default) +#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 + +// Field: [16] HF_COMP +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_HF_COMP 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_BITN 16 +#define CCFG_MODE_CONF_HF_COMP_M 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_S 16 + +// Field: [15:8] XOSC_CAPARRAY_DELTA +// +// Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. +// Enabled by XOSC_CAP_MOD. +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 + +// Field: [7:0] VDDR_CAP +// +// Unsigned 8-bit integer, representing the minimum decoupling capacitance +// (worst case) on VDDR, in units of 100nF. This should take into account +// capacitor tolerance and voltage dependent capacitance variation. This bit +// affects the recharge period calculation when going into powerdown or +// standby. +// +// NOTE! If using the following functions this field must be configured (used +// by TI RTOS): +// SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() +#define CCFG_MODE_CONF_VDDR_CAP_W 8 +#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF +#define CCFG_MODE_CONF_VDDR_CAP_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_VOLT_LOAD_0 +// +//***************************************************************************** +// Field: [31:24] VDDR_EXT_TP45 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 + +// Field: [23:16] VDDR_EXT_TP25 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 + +// Field: [15:8] VDDR_EXT_TP5 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 + +// Field: [7:0] VDDR_EXT_TM15 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_VOLT_LOAD_1 +// +//***************************************************************************** +// Field: [31:24] VDDR_EXT_TP125 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 + +// Field: [23:16] VDDR_EXT_TP105 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 + +// Field: [15:8] VDDR_EXT_TP85 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 + +// Field: [7:0] VDDR_EXT_TP65 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_RTC_OFFSET +// +//***************************************************************************** +// Field: [31:16] RTC_COMP_P0 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 + +// Field: [15:8] RTC_COMP_P1 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 + +// Field: [7:0] RTC_COMP_P2 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF +#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_FREQ_OFFSET +// +//***************************************************************************** +// Field: [31:16] HF_COMP_P0 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 + +// Field: [15:8] HF_COMP_P1 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 + +// Field: [7:0] HF_COMP_P2 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF +#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_MAC_0 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[31:0] of the 64-bits custom IEEE MAC address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_MAC_0_ADDR_W 32 +#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_0_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_MAC_1 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[63:32] of the 64-bits custom IEEE MAC address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_MAC_1_ADDR_W 32 +#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_1_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_BLE_0 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[31:0] of the 64-bits custom IEEE BLE address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_BLE_0_ADDR_W 32 +#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_0_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_BLE_1 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[63:32] of the 64-bits custom IEEE BLE address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_BLE_1_ADDR_W 32 +#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_1_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_BL_CONFIG +// +//***************************************************************************** +// Field: [31:24] BOOTLOADER_ENABLE +// +// Bootloader enable. Boot loader can be accessed if +// IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and +// conditions for boot loader backdoor are met). +// 0xC5: Boot loader is enabled. +// Any other value: Boot loader is disabled. +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 + +// Field: [16] BL_LEVEL +// +// Sets the active level of the selected DIO number BL_PIN_NUMBER if boot +// loader backdoor is enabled by the BL_ENABLE field. +// 0: Active low. +// 1: Active high. +#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 +#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_S 16 + +// Field: [15:8] BL_PIN_NUMBER +// +// DIO number that is level checked if the boot loader backdoor is enabled by +// the BL_ENABLE field. +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 + +// Field: [7:0] BL_ENABLE +// +// Enables the boot loader backdoor. +// 0xC5: Boot loader backdoor is enabled. +// Any other value: Boot loader backdoor is disabled. +// +// NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader +// backdoor is enabled. +#define CCFG_BL_CONFIG_BL_ENABLE_W 8 +#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF +#define CCFG_BL_CONFIG_BL_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_ERASE_CONF +// +//***************************************************************************** +// Field: [8] CHIP_ERASE_DIS_N +// +// Chip erase. +// This bit controls if a chip erase requested through the JTAG WUC TAP will be +// ignored in a following boot caused by a reset of the MCU VD. +// A successful chip erase operation will force the content of the flash main +// bank back to the state as it was when delivered by TI. +// 0: Disable. Any chip erase request detected during boot will be ignored. +// 1: Enable. Any chip erase request detected during boot will be performed by +// the boot FW. +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 + +// Field: [0] BANK_ERASE_DIS_N +// +// Bank erase. +// This bit controls if the ROM serial boot loader will accept a received Bank +// Erase command (COMMAND_BANK_ERASE). +// A successful Bank Erase operation will erase all main bank sectors not +// protected by write protect configuration bits in CCFG. +// 0: Disable the boot loader bank erase function. +// 1: Enable the boot loader bank erase function. +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TI_OPTIONS +// +//***************************************************************************** +// Field: [7:0] TI_FA_ENABLE +// +// TI Failure Analysis. +// 0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) +// option with the unlock code. +// All other values: Disable the functionality of unlocking the TI FA option +// with the unlock code. +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TAP_DAP_0 +// +//***************************************************************************** +// Field: [23:16] CPU_DAP_ENABLE +// +// Enable CPU DAP. +// 0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM +// boot FW. +// Any other value: Main CPU DAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 + +// Field: [15:8] PWRPROF_TAP_ENABLE +// +// Enable PWRPROF TAP. +// 0xC5: PWRPROF TAP access is enabled during power-up/system-reset by ROM boot +// FW if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PWRPROF TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S 8 + +// Field: [7:0] TEST_TAP_ENABLE +// +// Enable Test TAP. +// 0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW +// if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: TEST TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TAP_DAP_1 +// +//***************************************************************************** +// Field: [23:16] PBIST2_TAP_ENABLE +// +// Enable PBIST2 TAP. +// 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot +// FW if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PBIST2 TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 + +// Field: [15:8] PBIST1_TAP_ENABLE +// +// Enable PBIST1 TAP. +// 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot +// FW if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PBIST1 TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 + +// Field: [7:0] AON_TAP_ENABLE +// +// Enable AON TAP +// 0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW +// if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: AON TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IMAGE_VALID_CONF +// +//***************************************************************************** +// Field: [31:0] IMAGE_VALID +// +// This field must have the address value of the start of the flash vector +// table in order to enable the boot FW in ROM to transfer control to a flash +// image. +// Any illegal vector table start address value will force the boot FW in ROM +// to transfer control to the serial boot loader in ROM. +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_31_0 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_31 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 + +// Field: [30] WRT_PROT_SEC_30 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 + +// Field: [29] WRT_PROT_SEC_29 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 + +// Field: [28] WRT_PROT_SEC_28 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 + +// Field: [27] WRT_PROT_SEC_27 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 + +// Field: [26] WRT_PROT_SEC_26 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 + +// Field: [25] WRT_PROT_SEC_25 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 + +// Field: [24] WRT_PROT_SEC_24 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 + +// Field: [23] WRT_PROT_SEC_23 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 + +// Field: [22] WRT_PROT_SEC_22 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 + +// Field: [21] WRT_PROT_SEC_21 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 + +// Field: [20] WRT_PROT_SEC_20 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 + +// Field: [19] WRT_PROT_SEC_19 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 + +// Field: [18] WRT_PROT_SEC_18 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 + +// Field: [17] WRT_PROT_SEC_17 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 + +// Field: [16] WRT_PROT_SEC_16 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 + +// Field: [15] WRT_PROT_SEC_15 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 + +// Field: [14] WRT_PROT_SEC_14 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 + +// Field: [13] WRT_PROT_SEC_13 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 + +// Field: [12] WRT_PROT_SEC_12 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 + +// Field: [11] WRT_PROT_SEC_11 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 + +// Field: [10] WRT_PROT_SEC_10 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 + +// Field: [9] WRT_PROT_SEC_9 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 + +// Field: [8] WRT_PROT_SEC_8 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 + +// Field: [7] WRT_PROT_SEC_7 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 + +// Field: [6] WRT_PROT_SEC_6 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 + +// Field: [5] WRT_PROT_SEC_5 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 + +// Field: [4] WRT_PROT_SEC_4 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 + +// Field: [3] WRT_PROT_SEC_3 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 + +// Field: [2] WRT_PROT_SEC_2 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 + +// Field: [1] WRT_PROT_SEC_1 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 + +// Field: [0] WRT_PROT_SEC_0 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_63_32 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_63 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 + +// Field: [30] WRT_PROT_SEC_62 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 + +// Field: [29] WRT_PROT_SEC_61 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 + +// Field: [28] WRT_PROT_SEC_60 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 + +// Field: [27] WRT_PROT_SEC_59 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 + +// Field: [26] WRT_PROT_SEC_58 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 + +// Field: [25] WRT_PROT_SEC_57 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 + +// Field: [24] WRT_PROT_SEC_56 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 + +// Field: [23] WRT_PROT_SEC_55 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 + +// Field: [22] WRT_PROT_SEC_54 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 + +// Field: [21] WRT_PROT_SEC_53 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 + +// Field: [20] WRT_PROT_SEC_52 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 + +// Field: [19] WRT_PROT_SEC_51 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 + +// Field: [18] WRT_PROT_SEC_50 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 + +// Field: [17] WRT_PROT_SEC_49 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 + +// Field: [16] WRT_PROT_SEC_48 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 + +// Field: [15] WRT_PROT_SEC_47 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 + +// Field: [14] WRT_PROT_SEC_46 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 + +// Field: [13] WRT_PROT_SEC_45 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 + +// Field: [12] WRT_PROT_SEC_44 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 + +// Field: [11] WRT_PROT_SEC_43 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 + +// Field: [10] WRT_PROT_SEC_42 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 + +// Field: [9] WRT_PROT_SEC_41 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 + +// Field: [8] WRT_PROT_SEC_40 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 + +// Field: [7] WRT_PROT_SEC_39 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 + +// Field: [6] WRT_PROT_SEC_38 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 + +// Field: [5] WRT_PROT_SEC_37 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 + +// Field: [4] WRT_PROT_SEC_36 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 + +// Field: [3] WRT_PROT_SEC_35 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 + +// Field: [2] WRT_PROT_SEC_34 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 + +// Field: [1] WRT_PROT_SEC_33 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 + +// Field: [0] WRT_PROT_SEC_32 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_95_64 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_95 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 + +// Field: [30] WRT_PROT_SEC_94 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 + +// Field: [29] WRT_PROT_SEC_93 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 + +// Field: [28] WRT_PROT_SEC_92 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 + +// Field: [27] WRT_PROT_SEC_91 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 + +// Field: [26] WRT_PROT_SEC_90 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 + +// Field: [25] WRT_PROT_SEC_89 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 + +// Field: [24] WRT_PROT_SEC_88 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 + +// Field: [23] WRT_PROT_SEC_87 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 + +// Field: [22] WRT_PROT_SEC_86 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 + +// Field: [21] WRT_PROT_SEC_85 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 + +// Field: [20] WRT_PROT_SEC_84 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 + +// Field: [19] WRT_PROT_SEC_83 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 + +// Field: [18] WRT_PROT_SEC_82 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 + +// Field: [17] WRT_PROT_SEC_81 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 + +// Field: [16] WRT_PROT_SEC_80 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 + +// Field: [15] WRT_PROT_SEC_79 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 + +// Field: [14] WRT_PROT_SEC_78 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 + +// Field: [13] WRT_PROT_SEC_77 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 + +// Field: [12] WRT_PROT_SEC_76 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 + +// Field: [11] WRT_PROT_SEC_75 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 + +// Field: [10] WRT_PROT_SEC_74 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 + +// Field: [9] WRT_PROT_SEC_73 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 + +// Field: [8] WRT_PROT_SEC_72 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 + +// Field: [7] WRT_PROT_SEC_71 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 + +// Field: [6] WRT_PROT_SEC_70 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 + +// Field: [5] WRT_PROT_SEC_69 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 + +// Field: [4] WRT_PROT_SEC_68 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 + +// Field: [3] WRT_PROT_SEC_67 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 + +// Field: [2] WRT_PROT_SEC_66 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 + +// Field: [1] WRT_PROT_SEC_65 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 + +// Field: [0] WRT_PROT_SEC_64 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_127_96 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_127 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 + +// Field: [30] WRT_PROT_SEC_126 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 + +// Field: [29] WRT_PROT_SEC_125 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 + +// Field: [28] WRT_PROT_SEC_124 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 + +// Field: [27] WRT_PROT_SEC_123 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 + +// Field: [26] WRT_PROT_SEC_122 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 + +// Field: [25] WRT_PROT_SEC_121 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 + +// Field: [24] WRT_PROT_SEC_120 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 + +// Field: [23] WRT_PROT_SEC_119 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 + +// Field: [22] WRT_PROT_SEC_118 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 + +// Field: [21] WRT_PROT_SEC_117 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 + +// Field: [20] WRT_PROT_SEC_116 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 + +// Field: [19] WRT_PROT_SEC_115 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 + +// Field: [18] WRT_PROT_SEC_114 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 + +// Field: [17] WRT_PROT_SEC_113 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 + +// Field: [16] WRT_PROT_SEC_112 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 + +// Field: [15] WRT_PROT_SEC_111 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 + +// Field: [14] WRT_PROT_SEC_110 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 + +// Field: [13] WRT_PROT_SEC_109 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 + +// Field: [12] WRT_PROT_SEC_108 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 + +// Field: [11] WRT_PROT_SEC_107 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 + +// Field: [10] WRT_PROT_SEC_106 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 + +// Field: [9] WRT_PROT_SEC_105 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 + +// Field: [8] WRT_PROT_SEC_104 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 + +// Field: [7] WRT_PROT_SEC_103 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 + +// Field: [6] WRT_PROT_SEC_102 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 + +// Field: [5] WRT_PROT_SEC_101 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 + +// Field: [4] WRT_PROT_SEC_100 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 + +// Field: [3] WRT_PROT_SEC_99 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 + +// Field: [2] WRT_PROT_SEC_98 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 + +// Field: [1] WRT_PROT_SEC_97 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 + +// Field: [0] WRT_PROT_SEC_96 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 + + +#endif // __CCFG__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h new file mode 100644 index 0000000..9e59f45 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h @@ -0,0 +1,81 @@ +/****************************************************************************** +* Filename: hw_ccfg_simple_struct_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CCFG_SIMPLE_STRUCT_H__ +#define __HW_CCFG_SIMPLE_STRUCT_H__ + +//***************************************************************************** +// +// Customer configuration (ccfg) typedef. +// The implementation of this struct is required by device ROM boot code +// and must be placed at the end of flash. Do not modify this struct! +// +//***************************************************************************** +typedef struct +{ // Mapped to address + uint32_t CCFG_EXT_LF_CLK ; // 0x50004FA8 + uint32_t CCFG_MODE_CONF_1 ; // 0x50004FAC + uint32_t CCFG_SIZE_AND_DIS_FLAGS ; // 0x50004FB0 + uint32_t CCFG_MODE_CONF ; // 0x50004FB4 + uint32_t CCFG_VOLT_LOAD_0 ; // 0x50004FB8 + uint32_t CCFG_VOLT_LOAD_1 ; // 0x50004FBC + uint32_t CCFG_RTC_OFFSET ; // 0x50004FC0 + uint32_t CCFG_FREQ_OFFSET ; // 0x50004FC4 + uint32_t CCFG_IEEE_MAC_0 ; // 0x50004FC8 + uint32_t CCFG_IEEE_MAC_1 ; // 0x50004FCC + uint32_t CCFG_IEEE_BLE_0 ; // 0x50004FD0 + uint32_t CCFG_IEEE_BLE_1 ; // 0x50004FD4 + uint32_t CCFG_BL_CONFIG ; // 0x50004FD8 + uint32_t CCFG_ERASE_CONF ; // 0x50004FDC + uint32_t CCFG_CCFG_TI_OPTIONS ; // 0x50004FE0 + uint32_t CCFG_CCFG_TAP_DAP_0 ; // 0x50004FE4 + uint32_t CCFG_CCFG_TAP_DAP_1 ; // 0x50004FE8 + uint32_t CCFG_IMAGE_VALID_CONF ; // 0x50004FEC + uint32_t CCFG_CCFG_PROT_31_0 ; // 0x50004FF0 + uint32_t CCFG_CCFG_PROT_63_32 ; // 0x50004FF4 + uint32_t CCFG_CCFG_PROT_95_64 ; // 0x50004FF8 + uint32_t CCFG_CCFG_PROT_127_96 ; // 0x50004FFC +} ccfg_t; + +//***************************************************************************** +// +// Define the extern ccfg structure (__ccfg) +// +//***************************************************************************** +extern const ccfg_t __ccfg; + + +#endif // __HW_CCFG_SIMPLE_STRUCT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h new file mode 100644 index 0000000..b9b504f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h @@ -0,0 +1,234 @@ +/****************************************************************************** +* Filename: hw_chip_def.h +* Revised: 2017-06-26 09:33:33 +0200 (Mon, 26 Jun 2017) +* Revision: 49227 +* +* Description: Defines for device properties. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup config_api +//! @{ +// +//***************************************************************************** + +#ifndef __HW_CHIP_DEF_H__ +#define __HW_CHIP_DEF_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Define CC_CHIP_ID code used in the following macros defined at the bottom: +// CC_GET_CHIP_FAMILY/DEVICE/PACKAGE/HWREV +// +//***************************************************************************** +/* CC2620F128 */ +#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21) + #define CC_CHIP_ID 0x26200720 +#elif defined(CC2620F128RHB_R20) || defined(CC2620F128RHB_R21) + #define CC_CHIP_ID 0x26200520 +#elif defined(CC2620F128RSM_R20) || defined(CC2620F128RSM_R21) + #define CC_CHIP_ID 0x26200420 +#elif defined(CC2620F128_R20) || defined(CC2620F128_R21) + #define CC_CHIP_ID 0x26200020 +#elif defined(CC2620F128RGZ_R22) || defined(CC2620F128RGZ) + #define CC_CHIP_ID 0x26200722 +#elif defined(CC2620F128RHB_R22) || defined(CC2620F128RHB) + #define CC_CHIP_ID 0x26200522 +#elif defined(CC2620F128RSM_R22) || defined(CC2620F128RSM) + #define CC_CHIP_ID 0x26200422 +#elif defined(CC2620F128_R22) || defined(CC2620F128) + #define CC_CHIP_ID 0x26200022 +/* CC2630F128 */ +#elif defined(CC2630F128RGZ_R20) || defined(CC2630F128RGZ_R21) + #define CC_CHIP_ID 0x26300720 +#elif defined(CC2630F128RHB_R20) || defined(CC2630F128RHB_R21) + #define CC_CHIP_ID 0x26300520 +#elif defined(CC2630F128RSM_R20) || defined(CC2630F128RSM_R21) + #define CC_CHIP_ID 0x26300420 +#elif defined(CC2630F128_R20) || defined(CC2630F128_R21) + #define CC_CHIP_ID 0x26300020 +#elif defined(CC2630F128RGZ_R22) || defined(CC2630F128RGZ) + #define CC_CHIP_ID 0x26300722 +#elif defined(CC2630F128RHB_R22) || defined(CC2630F128RHB) + #define CC_CHIP_ID 0x26300522 +#elif defined(CC2630F128RSM_R22) || defined(CC2630F128RSM) + #define CC_CHIP_ID 0x26300422 +#elif defined(CC2630F128_R22) || defined(CC2630F128) + #define CC_CHIP_ID 0x26300022 +/* CC2640F128 */ +#elif defined(CC2640F128RGZ_R20) || defined(CC2640F128RGZ_R21) + #define CC_CHIP_ID 0x26400720 +#elif defined(CC2640F128RHB_R20) || defined(CC2640F128RHB_R21) + #define CC_CHIP_ID 0x26400520 +#elif defined(CC2640F128RSM_R20) || defined(CC2640F128RSM_R21) + #define CC_CHIP_ID 0x26400420 +#elif defined(CC2640F128_R20) || defined(CC2640F128_R21) + #define CC_CHIP_ID 0x26400020 +#elif defined(CC2640F128RGZ_R22) || defined(CC2640F128RGZ) + #define CC_CHIP_ID 0x26400722 +#elif defined(CC2640F128RHB_R22) || defined(CC2640F128RHB) + #define CC_CHIP_ID 0x26400522 +#elif defined(CC2640F128RSM_R22) || defined(CC2640F128RSM) + #define CC_CHIP_ID 0x26400422 +#elif defined(CC2640F128_R22) || defined(CC2640F128) + #define CC_CHIP_ID 0x26400022 +/* CC2650F128 */ +#elif defined(CC2650F128RGZ_R20) || defined(CC2650F128RGZ_R21) + #define CC_CHIP_ID 0x26500720 +#elif defined(CC2650F128RHB_R20) || defined(CC2650F128RHB_R21) + #define CC_CHIP_ID 0x26500520 +#elif defined(CC2650F128RSM_R20) || defined(CC2650F128RSM_R21) + #define CC_CHIP_ID 0x26500420 +#elif defined(CC2650F128_R20) || defined(CC2650F128_R21) + #define CC_CHIP_ID 0x26500020 +#elif defined(CC2650F128RGZ_R22) || defined(CC2650F128RGZ) + #define CC_CHIP_ID 0x26500722 +#elif defined(CC2650F128RHB_R22) || defined(CC2650F128RHB) + #define CC_CHIP_ID 0x26500522 +#elif defined(CC2650F128RSM_R22) || defined(CC2650F128RSM) + #define CC_CHIP_ID 0x26500422 +#elif defined(CC2650F128_R22) || defined(CC2650F128) + #define CC_CHIP_ID 0x26500022 +/* CC2650L128 (OTP) */ +#elif defined(CC2650L128) + #define CC_CHIP_ID 0x26501710 +/* CC1310F128 */ +#elif defined(CC1310F128RGZ_R20) || defined(CC1310F128RGZ) + #define CC_CHIP_ID 0x13100720 +#elif defined(CC1310F128RHB_R20) || defined(CC1310F128RHB) + #define CC_CHIP_ID 0x13100520 +#elif defined(CC1310F128RSM_R20) || defined(CC1310F128RSM) + #define CC_CHIP_ID 0x13100420 +#elif defined(CC1310F128_R20) || defined(CC1310F128) + #define CC_CHIP_ID 0x13100020 +/* CC1350F128 */ +#elif defined(CC1350F128RGZ_R20) || defined(CC1350F128RGZ) + #define CC_CHIP_ID 0x13500720 +#elif defined(CC1350F128RHB_R20) || defined(CC1350F128RHB) + #define CC_CHIP_ID 0x13500520 +#elif defined(CC1350F128RSM_R20) || defined(CC1350F128RSM) + #define CC_CHIP_ID 0x13500420 +#elif defined(CC1350F128_R20) || defined(CC1350F128) + #define CC_CHIP_ID 0x13500020 +/* CC2640R2F */ +#elif defined(CC2640R2FRGZ_R25) || defined(CC2640R2FRGZ) + #define CC_CHIP_ID 0x26401710 +#elif defined(CC2640R2FRHB_R25) || defined(CC2640R2FRHB) + #define CC_CHIP_ID 0x26401510 +#elif defined(CC2640R2FRSM_R25) || defined(CC2640R2FRSM) + #define CC_CHIP_ID 0x26401410 +#elif defined(CC2640R2F_R25) || defined(CC2640R2F) + #define CC_CHIP_ID 0x26401010 +/* CC2652R1F */ +#elif defined(CC2652R1FRGZ_R10) || defined(CC2652R1FRGZ) + #define CC_CHIP_ID 0x26523710 +#elif defined(CC2652R1F_R10) || defined(CC2652R1F) + #define CC_CHIP_ID 0x26523010 +/* CC2644R1F */ +#elif defined(CC2644R1FRGZ_R10) || defined(CC2644R1FRGZ) + #define CC_CHIP_ID 0x26443710 +#elif defined(CC2644R1F_R10) || defined(CC2644R1F) + #define CC_CHIP_ID 0x26443010 +/* CC2642R1F */ +#elif defined(CC2642R1FRGZ_R10) || defined(CC2642R1FRGZ) + #define CC_CHIP_ID 0x26423710 +#elif defined(CC2642R1F_R10) || defined(CC2642R1F) + #define CC_CHIP_ID 0x26423010 +/* CC1354R1F */ +#elif defined(CC1354R1FRGZ_R10) || defined(CC1354R1FRGZ) + #define CC_CHIP_ID 0x13543710 +#elif defined(CC1354R1F_R10) || defined(CC1354R1F) + #define CC_CHIP_ID 0x13543010 +/* CC1352R1F */ +#elif defined(CC1352R1FRGZ_R10) || defined(CC1352R1FRGZ) + #define CC_CHIP_ID 0x13523710 +#elif defined(CC1352R1F_R10) || defined(CC1352R1F) + #define CC_CHIP_ID 0x13523010 +/* CC1312R1F */ +#elif defined(CC1312R1FRGZ_R10) || defined(CC1312R1FRGZ) + #define CC_CHIP_ID 0x13123710 +#elif defined(CC1312R1F_R10) || defined(CC1312R1F) + #define CC_CHIP_ID 0x13123010 +#endif + +#define CC_GET_CHIP_FAMILY 0x26 +#define CC_GET_CHIP_OPTION 0x3 +#define CC_GET_CHIP_HWREV 0x20 + +#ifdef CC_CHIP_ID + /* Define chip package only if specified */ + #if (CC_CHIP_ID & 0x00000F00) != 0 + #define CC_GET_CHIP_PACKAGE (((CC_CHIP_ID) & 0x00000F00) >> 8) + #endif + + /* Define chip device */ + #define CC_GET_CHIP_DEVICE (((CC_CHIP_ID) & 0xFFFF0000) >> 16) + + /* The chip family, option and package shall match the DriverLib release */ + #if (CC_GET_CHIP_OPTION != ((CC_CHIP_ID & 0x0000F000) >> 12)) + #error "Specified chip option does not match DriverLib release" + #endif + #if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0)) + #error "Specified chip hardware revision does not match DriverLib release" + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __HW_CHIP_DEF_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h new file mode 100644 index 0000000..5386ee9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h @@ -0,0 +1,856 @@ +/****************************************************************************** +* Filename: hw_cpu_dwt_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_DWT_H__ +#define __HW_CPU_DWT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_DWT component +// +//***************************************************************************** +// Control +#define CPU_DWT_O_CTRL 0x00000000 + +// Current PC Sampler Cycle Count +#define CPU_DWT_O_CYCCNT 0x00000004 + +// CPI Count +#define CPU_DWT_O_CPICNT 0x00000008 + +// Exception Overhead Count +#define CPU_DWT_O_EXCCNT 0x0000000C + +// Sleep Count +#define CPU_DWT_O_SLEEPCNT 0x00000010 + +// LSU Count +#define CPU_DWT_O_LSUCNT 0x00000014 + +// Fold Count +#define CPU_DWT_O_FOLDCNT 0x00000018 + +// Program Counter Sample +#define CPU_DWT_O_PCSR 0x0000001C + +// Comparator 0 +#define CPU_DWT_O_COMP0 0x00000020 + +// Mask 0 +#define CPU_DWT_O_MASK0 0x00000024 + +// Function 0 +#define CPU_DWT_O_FUNCTION0 0x00000028 + +// Comparator 1 +#define CPU_DWT_O_COMP1 0x00000030 + +// Mask 1 +#define CPU_DWT_O_MASK1 0x00000034 + +// Function 1 +#define CPU_DWT_O_FUNCTION1 0x00000038 + +// Comparator 2 +#define CPU_DWT_O_COMP2 0x00000040 + +// Mask 2 +#define CPU_DWT_O_MASK2 0x00000044 + +// Function 2 +#define CPU_DWT_O_FUNCTION2 0x00000048 + +// Comparator 3 +#define CPU_DWT_O_COMP3 0x00000050 + +// Mask 3 +#define CPU_DWT_O_MASK3 0x00000054 + +// Function 3 +#define CPU_DWT_O_FUNCTION3 0x00000058 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CTRL +// +//***************************************************************************** +// Field: [25] NOCYCCNT +// +// When set, CYCCNT is not supported. +#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 +#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_S 25 + +// Field: [24] NOPRFCNT +// +// When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. +#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 +#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_S 24 + +// Field: [22] CYCEVTENA +// +// Enables Cycle count event. Emits an event when the POSTCNT counter triggers +// it. See CYCTAP and POSTPRESET for details. This event is only emitted if +// PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. +// +// 0: Cycle count events disabled +// 1: Cycle count events enabled +#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 +#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_S 22 + +// Field: [21] FOLDEVTENA +// +// Enables Folded instruction count event. Emits an event when FOLDCNT +// overflows (every 256 cycles of folded instructions). A folded instruction is +// one that does not incur even one cycle to execute. For example, an IT +// instruction is folded away and so does not use up one cycle. +// +// 0: Folded instruction count events disabled. +// 1: Folded instruction count events enabled. +#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 +#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_S 21 + +// Field: [20] LSUEVTENA +// +// Enables LSU count event. Emits an event when LSUCNT overflows (every 256 +// cycles of LSU operation). LSU counts include all LSU costs after the initial +// cycle for the instruction. +// +// 0: LSU count events disabled. +// 1: LSU count events enabled. +#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 +#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_S 20 + +// Field: [19] SLEEPEVTENA +// +// Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 +// cycles that the processor is sleeping). +// +// 0: Sleep count events disabled. +// 1: Sleep count events enabled. +#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 +#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 + +// Field: [18] EXCEVTENA +// +// Enables Interrupt overhead event. Emits an event when EXCCNT overflows +// (every 256 cycles of interrupt overhead). +// +// 0x0: Interrupt overhead event disabled. +// 0x1: Interrupt overhead event enabled. +#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 +#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_S 18 + +// Field: [17] CPIEVTENA +// +// Enables CPI count event. Emits an event when CPICNT overflows (every 256 +// cycles of multi-cycle instructions). +// +// 0: CPI counter events disabled. +// 1: CPI counter events enabled. +#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 +#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_S 17 + +// Field: [16] EXCTRCENA +// +// Enables Interrupt event tracing. +// +// 0: Interrupt event trace disabled. +// 1: Interrupt event trace enabled. +#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 +#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_S 16 + +// Field: [12] PCSAMPLEENA +// +// Enables PC Sampling event. A PC sample event is emitted when the POSTCNT +// counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this +// bit overrides CYCEVTENA. +// +// 0: PC Sampling event disabled. +// 1: Sampling event enabled. +#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 +#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 + +// Field: [11:10] SYNCTAP +// +// Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA +// must also be enabled for this feature. +// Synchronization packets (if enabled) are generated on tap transitions (0 to1 +// or 1 to 0). +// ENUMs: +// BIT28 Tap at bit 28 of CYCCNT +// BIT26 Tap at bit 26 of CYCCNT +// BIT24 Tap at bit 24 of CYCCNT +// DIS Disabled. No synchronization packets +#define CPU_DWT_CTRL_SYNCTAP_W 2 +#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_S 10 +#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 +#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 +#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 + +// Field: [9] CYCTAP +// +// Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the +// selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the +// POSTCNT, post-scalar counter. That counter then counts down. On a bit change +// when post-scalar is 0, it triggers an event for PC sampling or cycle count +// event (see details in CYCEVTENA). +// ENUMs: +// BIT10 Selects bit [10] to tap +// BIT6 Selects bit [6] to tap +#define CPU_DWT_CTRL_CYCTAP 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BITN 9 +#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_S 9 +#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 + +// Field: [8:5] POSTCNT +// +// Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 +// to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it +// triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the +// value from POSTPRESET. +#define CPU_DWT_CTRL_POSTCNT_W 4 +#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 +#define CPU_DWT_CTRL_POSTCNT_S 5 + +// Field: [4:1] POSTPRESET +// +// Reload value for post-scalar counter POSTCNT. When 0, events are triggered +// on each tap change (a power of 2). If this field has a non-0 value, it forms +// a count-down value, to be reloaded into POSTCNT each time it reaches 0. For +// example, a value 1 in this register means an event is formed every other tap +// change. +#define CPU_DWT_CTRL_POSTPRESET_W 4 +#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E +#define CPU_DWT_CTRL_POSTPRESET_S 1 + +// Field: [0] CYCCNTENA +// +// Enable CYCCNT, allowing it to increment and generate synchronization and +// count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. +#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 +#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CYCCNT +// +//***************************************************************************** +// Field: [31:0] CYCCNT +// +// Current PC Sampler Cycle Counter count value. When enabled, this counter +// counts the number of core cycles, except when the core is halted. The cycle +// counter is a free running counter, counting upwards (this counter will not +// advance in power modes where free-running clock to CPU stops). It wraps +// around to 0 on overflow. The debugger must initialize this to 0 when first +// enabling. +#define CPU_DWT_CYCCNT_CYCCNT_W 32 +#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF +#define CPU_DWT_CYCCNT_CYCCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CPICNT +// +//***************************************************************************** +// Field: [7:0] CPICNT +// +// Current CPI counter value. Increments on the additional cycles (the first +// cycle is not counted) required to execute all instructions except those +// recorded by LSUCNT. This counter also increments on all instruction fetch +// stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter +// overflows. This counter initializes to 0 when it is enabled using +// CTRL.CPIEVTENA. +#define CPU_DWT_CPICNT_CPICNT_W 8 +#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF +#define CPU_DWT_CPICNT_CPICNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_EXCCNT +// +//***************************************************************************** +// Field: [7:0] EXCCNT +// +// Current interrupt overhead counter value. Counts the total cycles spent in +// interrupt processing (for example entry stacking, return unstacking, +// pre-emption). An event is emitted on counter overflow (every 256 cycles). +// This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. +#define CPU_DWT_EXCCNT_EXCCNT_W 8 +#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF +#define CPU_DWT_EXCCNT_EXCCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_SLEEPCNT +// +//***************************************************************************** +// Field: [7:0] SLEEPCNT +// +// Sleep counter. Counts the number of cycles during which the processor is +// sleeping. An event is emitted on counter overflow (every 256 cycles). This +// counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note +// that the sleep counter is clocked using CPU's free-running clock. In some +// power modes the free-running clock to CPU is gated to minimize power +// consumption. This means that the sleep counter will be invalid in these +// power modes. +#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 +#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF +#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_LSUCNT +// +//***************************************************************************** +// Field: [7:0] LSUCNT +// +// LSU counter. This counts the total number of cycles that the processor is +// processing an LSU operation. The initial execution cost of the instruction +// is not counted. For example, an LDR that takes two cycles to complete +// increments this counter one cycle. Equivalently, an LDR that stalls for two +// cycles (i.e. takes four cycles to execute), increments this counter three +// times. An event is emitted on counter overflow (every 256 cycles). This +// counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. +#define CPU_DWT_LSUCNT_LSUCNT_W 8 +#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF +#define CPU_DWT_LSUCNT_LSUCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FOLDCNT +// +//***************************************************************************** +// Field: [7:0] FOLDCNT +// +// This counts the total number folded instructions. This counter initializes +// to 0 when it is enabled using CTRL.FOLDEVTENA. +#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 +#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF +#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_PCSR +// +//***************************************************************************** +// Field: [31:0] EIASAMPLE +// +// Execution instruction address sample, or 0xFFFFFFFF if the core is halted. +#define CPU_DWT_PCSR_EIASAMPLE_W 32 +#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF +#define CPU_DWT_PCSR_EIASAMPLE_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP0 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler +// Counter (CYCCNT). +#define CPU_DWT_COMP0_COMP_W 32 +#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP0_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK0 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP0. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP0. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK0_MASK_W 4 +#define CPU_DWT_MASK0_MASK_M 0x0000000F +#define CPU_DWT_MASK0_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION0 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_S 24 + +// Field: [7] CYCMATCH +// +// This bit is only available in comparator 0. When set, COMP0 will compare +// against the cycle counter (CYCCNT). +#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 +#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION0_FUNCTION_W 4 +#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION0_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP1 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION1. +// Comparator 1 can also compare data values. So this register can contain +// reference values for data matching. +#define CPU_DWT_COMP1_COMP_W 32 +#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP1_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK1 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP1. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP1. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK1_MASK_W 4 +#define CPU_DWT_MASK1_MASK_M 0x0000000F +#define CPU_DWT_MASK1_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION1 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_S 24 + +// Field: [19:16] DATAVADDR1 +// +// Identity of a second linked address comparator for data value matching when +// DATAVMATCH == 1 and LNK1ENA == 1. +#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 +#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 + +// Field: [15:12] DATAVADDR0 +// +// Identity of a linked address comparator for data value matching when +// DATAVMATCH == 1. +#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 +#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 + +// Field: [11:10] DATAVSIZE +// +// Defines the size of the data in the COMP1 register that is to be matched: +// +// 0x0: Byte +// 0x1: Halfword +// 0x2: Word +// 0x3: Unpredictable. +#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 +#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 +#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 + +// Field: [9] LNK1ENA +// +// Read only bit-field only supported in comparator 1. +// +// 0: DATAVADDR1 not supported +// 1: DATAVADDR1 supported (enabled) +#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 +#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 + +// Field: [8] DATAVMATCH +// +// Data match feature: +// +// 0: Perform address comparison +// 1: Perform data value compare. The comparators given by DATAVADDR0 and +// DATAVADDR1 provide the address for the data comparison. The FUNCTION setting +// for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and +// those comparators only provide the address match for the data comparison. +// +// This bit is only available in comparator 1. +#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 +#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings: +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and +// DATAVADDR1 if DATAVMATCH is also set. The comparators given by DATAVADDR0 +// and DATAVADDR1 can then only perform address comparator matches for +// comparator 1 data matches. +// Note 4: If the data matching functionality is not included during +// implementation it is not possible to set DATAVADDR0, DATAVADDR1, or +// DATAVMATCH. This means that the data matching functionality is not available +// in the implementation. Test the availability of data matching by writing and +// reading DATAVMATCH. If it is not settable then data matching is unavailable. +// Note 5: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION1_FUNCTION_W 4 +#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION1_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP2 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION2. +#define CPU_DWT_COMP2_COMP_W 32 +#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP2_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK2 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP2. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP2. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK2_MASK_W 4 +#define CPU_DWT_MASK2_MASK_M 0x0000000F +#define CPU_DWT_MASK2_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION2 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_S 24 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION2_FUNCTION_W 4 +#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION2_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP3 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION3. +#define CPU_DWT_COMP3_COMP_W 32 +#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP3_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK3 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP3. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP3. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK3_MASK_W 4 +#define CPU_DWT_MASK3_MASK_M 0x0000000F +#define CPU_DWT_MASK3_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION3 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_S 24 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION3_FUNCTION_W 4 +#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION3_FUNCTION_S 0 + + +#endif // __CPU_DWT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h new file mode 100644 index 0000000..c87fab0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h @@ -0,0 +1,443 @@ +/****************************************************************************** +* Filename: hw_cpu_fpb_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_FPB_H__ +#define __HW_CPU_FPB_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_FPB component +// +//***************************************************************************** +// Control +#define CPU_FPB_O_CTRL 0x00000000 + +// Remap +#define CPU_FPB_O_REMAP 0x00000004 + +// Comparator 0 +#define CPU_FPB_O_COMP0 0x00000008 + +// Comparator 1 +#define CPU_FPB_O_COMP1 0x0000000C + +// Comparator 2 +#define CPU_FPB_O_COMP2 0x00000010 + +// Comparator 3 +#define CPU_FPB_O_COMP3 0x00000014 + +// Comparator 4 +#define CPU_FPB_O_COMP4 0x00000018 + +// Comparator 5 +#define CPU_FPB_O_COMP5 0x0000001C + +// Comparator 6 +#define CPU_FPB_O_COMP6 0x00000020 + +// Comparator 7 +#define CPU_FPB_O_COMP7 0x00000024 + +//***************************************************************************** +// +// Register: CPU_FPB_O_CTRL +// +//***************************************************************************** +// Field: [13:12] NUM_CODE2 +// +// Number of full banks of code comparators, sixteen comparators per bank. +// Where less than sixteen code comparators are provided, the bank count is +// zero, and the number present indicated by NUM_CODE1. This read only field +// contains 3'b000 to indicate 0 banks for Cortex-M processor. +#define CPU_FPB_CTRL_NUM_CODE2_W 2 +#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 +#define CPU_FPB_CTRL_NUM_CODE2_S 12 + +// Field: [11:8] NUM_LIT +// +// Number of literal slots field. +// +// 0x0: No literal slots +// 0x2: Two literal slots +#define CPU_FPB_CTRL_NUM_LIT_W 4 +#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 +#define CPU_FPB_CTRL_NUM_LIT_S 8 + +// Field: [7:4] NUM_CODE1 +// +// Number of code slots field. +// +// 0x0: No code slots +// 0x2: Two code slots +// 0x6: Six code slots +#define CPU_FPB_CTRL_NUM_CODE1_W 4 +#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 +#define CPU_FPB_CTRL_NUM_CODE1_S 4 + +// Field: [1] KEY +// +// Key field. In order to write to this register, this bit-field must be +// written to '1'. This bit always reads 0. +#define CPU_FPB_CTRL_KEY 0x00000002 +#define CPU_FPB_CTRL_KEY_BITN 1 +#define CPU_FPB_CTRL_KEY_M 0x00000002 +#define CPU_FPB_CTRL_KEY_S 1 + +// Field: [0] ENABLE +// +// Flash patch unit enable bit +// +// 0x0: Flash patch unit disabled +// 0x1: Flash patch unit enabled +#define CPU_FPB_CTRL_ENABLE 0x00000001 +#define CPU_FPB_CTRL_ENABLE_BITN 0 +#define CPU_FPB_CTRL_ENABLE_M 0x00000001 +#define CPU_FPB_CTRL_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_REMAP +// +//***************************************************************************** +// Field: [28:5] REMAP +// +// Remap base address field. +#define CPU_FPB_REMAP_REMAP_W 24 +#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 +#define CPU_FPB_REMAP_REMAP_S 5 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP0 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP0_REPLACE_W 2 +#define CPU_FPB_COMP0_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP0_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP0_COMP_W 27 +#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP0_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 0. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 0 disabled +// 0x1: Compare and remap for comparator 0 enabled +#define CPU_FPB_COMP0_ENABLE 0x00000001 +#define CPU_FPB_COMP0_ENABLE_BITN 0 +#define CPU_FPB_COMP0_ENABLE_M 0x00000001 +#define CPU_FPB_COMP0_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP1 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP1_REPLACE_W 2 +#define CPU_FPB_COMP1_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP1_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP1_COMP_W 27 +#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP1_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 1. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 1 disabled +// 0x1: Compare and remap for comparator 1 enabled +#define CPU_FPB_COMP1_ENABLE 0x00000001 +#define CPU_FPB_COMP1_ENABLE_BITN 0 +#define CPU_FPB_COMP1_ENABLE_M 0x00000001 +#define CPU_FPB_COMP1_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP2 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP2_REPLACE_W 2 +#define CPU_FPB_COMP2_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP2_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP2_COMP_W 27 +#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP2_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 2. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 2 disabled +// 0x1: Compare and remap for comparator 2 enabled +#define CPU_FPB_COMP2_ENABLE 0x00000001 +#define CPU_FPB_COMP2_ENABLE_BITN 0 +#define CPU_FPB_COMP2_ENABLE_M 0x00000001 +#define CPU_FPB_COMP2_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP3 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP3_REPLACE_W 2 +#define CPU_FPB_COMP3_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP3_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP3_COMP_W 27 +#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP3_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 3. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 3 disabled +// 0x1: Compare and remap for comparator 3 enabled +#define CPU_FPB_COMP3_ENABLE 0x00000001 +#define CPU_FPB_COMP3_ENABLE_BITN 0 +#define CPU_FPB_COMP3_ENABLE_M 0x00000001 +#define CPU_FPB_COMP3_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP4 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP4_REPLACE_W 2 +#define CPU_FPB_COMP4_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP4_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP4_COMP_W 27 +#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP4_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 4. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 4 disabled +// 0x1: Compare and remap for comparator 4 enabled +#define CPU_FPB_COMP4_ENABLE 0x00000001 +#define CPU_FPB_COMP4_ENABLE_BITN 0 +#define CPU_FPB_COMP4_ENABLE_M 0x00000001 +#define CPU_FPB_COMP4_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP5 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP5_REPLACE_W 2 +#define CPU_FPB_COMP5_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP5_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP5_COMP_W 27 +#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP5_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 5. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 5 disabled +// 0x1: Compare and remap for comparator 5 enabled +#define CPU_FPB_COMP5_ENABLE 0x00000001 +#define CPU_FPB_COMP5_ENABLE_BITN 0 +#define CPU_FPB_COMP5_ENABLE_M 0x00000001 +#define CPU_FPB_COMP5_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP6 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Comparator 6 is +// a literal comparator and the only supported setting is 0x0. Other settings +// will be ignored. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP6_REPLACE_W 2 +#define CPU_FPB_COMP6_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP6_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP6_COMP_W 27 +#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP6_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 6. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 6 disabled +// 0x1: Compare and remap for comparator 6 enabled +#define CPU_FPB_COMP6_ENABLE 0x00000001 +#define CPU_FPB_COMP6_ENABLE_BITN 0 +#define CPU_FPB_COMP6_ENABLE_M 0x00000001 +#define CPU_FPB_COMP6_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP7 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Comparator 7 is +// a literal comparator and the only supported setting is 0x0. Other settings +// will be ignored. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP7_REPLACE_W 2 +#define CPU_FPB_COMP7_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP7_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP7_COMP_W 27 +#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP7_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 7. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 7 disabled +// 0x1: Compare and remap for comparator 7 enabled +#define CPU_FPB_COMP7_ENABLE 0x00000001 +#define CPU_FPB_COMP7_ENABLE_BITN 0 +#define CPU_FPB_COMP7_ENABLE_M 0x00000001 +#define CPU_FPB_COMP7_ENABLE_S 0 + + +#endif // __CPU_FPB__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h new file mode 100644 index 0000000..528e1e8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h @@ -0,0 +1,1122 @@ +/****************************************************************************** +* Filename: hw_cpu_itm_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_ITM_H__ +#define __HW_CPU_ITM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_ITM component +// +//***************************************************************************** +// Stimulus Port 0 +#define CPU_ITM_O_STIM0 0x00000000 + +// Stimulus Port 1 +#define CPU_ITM_O_STIM1 0x00000004 + +// Stimulus Port 2 +#define CPU_ITM_O_STIM2 0x00000008 + +// Stimulus Port 3 +#define CPU_ITM_O_STIM3 0x0000000C + +// Stimulus Port 4 +#define CPU_ITM_O_STIM4 0x00000010 + +// Stimulus Port 5 +#define CPU_ITM_O_STIM5 0x00000014 + +// Stimulus Port 6 +#define CPU_ITM_O_STIM6 0x00000018 + +// Stimulus Port 7 +#define CPU_ITM_O_STIM7 0x0000001C + +// Stimulus Port 8 +#define CPU_ITM_O_STIM8 0x00000020 + +// Stimulus Port 9 +#define CPU_ITM_O_STIM9 0x00000024 + +// Stimulus Port 10 +#define CPU_ITM_O_STIM10 0x00000028 + +// Stimulus Port 11 +#define CPU_ITM_O_STIM11 0x0000002C + +// Stimulus Port 12 +#define CPU_ITM_O_STIM12 0x00000030 + +// Stimulus Port 13 +#define CPU_ITM_O_STIM13 0x00000034 + +// Stimulus Port 14 +#define CPU_ITM_O_STIM14 0x00000038 + +// Stimulus Port 15 +#define CPU_ITM_O_STIM15 0x0000003C + +// Stimulus Port 16 +#define CPU_ITM_O_STIM16 0x00000040 + +// Stimulus Port 17 +#define CPU_ITM_O_STIM17 0x00000044 + +// Stimulus Port 18 +#define CPU_ITM_O_STIM18 0x00000048 + +// Stimulus Port 19 +#define CPU_ITM_O_STIM19 0x0000004C + +// Stimulus Port 20 +#define CPU_ITM_O_STIM20 0x00000050 + +// Stimulus Port 21 +#define CPU_ITM_O_STIM21 0x00000054 + +// Stimulus Port 22 +#define CPU_ITM_O_STIM22 0x00000058 + +// Stimulus Port 23 +#define CPU_ITM_O_STIM23 0x0000005C + +// Stimulus Port 24 +#define CPU_ITM_O_STIM24 0x00000060 + +// Stimulus Port 25 +#define CPU_ITM_O_STIM25 0x00000064 + +// Stimulus Port 26 +#define CPU_ITM_O_STIM26 0x00000068 + +// Stimulus Port 27 +#define CPU_ITM_O_STIM27 0x0000006C + +// Stimulus Port 28 +#define CPU_ITM_O_STIM28 0x00000070 + +// Stimulus Port 29 +#define CPU_ITM_O_STIM29 0x00000074 + +// Stimulus Port 30 +#define CPU_ITM_O_STIM30 0x00000078 + +// Stimulus Port 31 +#define CPU_ITM_O_STIM31 0x0000007C + +// Trace Enable +#define CPU_ITM_O_TER 0x00000E00 + +// Trace Privilege +#define CPU_ITM_O_TPR 0x00000E40 + +// Trace Control +#define CPU_ITM_O_TCR 0x00000E80 + +// Lock Access +#define CPU_ITM_O_LAR 0x00000FB0 + +// Lock Status +#define CPU_ITM_O_LSR 0x00000FB4 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM0 +// +//***************************************************************************** +// Field: [31:0] STIM0 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM0_STIM0_W 32 +#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF +#define CPU_ITM_STIM0_STIM0_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM1 +// +//***************************************************************************** +// Field: [31:0] STIM1 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM1_STIM1_W 32 +#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF +#define CPU_ITM_STIM1_STIM1_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM2 +// +//***************************************************************************** +// Field: [31:0] STIM2 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM2_STIM2_W 32 +#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF +#define CPU_ITM_STIM2_STIM2_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM3 +// +//***************************************************************************** +// Field: [31:0] STIM3 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM3_STIM3_W 32 +#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF +#define CPU_ITM_STIM3_STIM3_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM4 +// +//***************************************************************************** +// Field: [31:0] STIM4 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM4_STIM4_W 32 +#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF +#define CPU_ITM_STIM4_STIM4_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM5 +// +//***************************************************************************** +// Field: [31:0] STIM5 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM5_STIM5_W 32 +#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF +#define CPU_ITM_STIM5_STIM5_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM6 +// +//***************************************************************************** +// Field: [31:0] STIM6 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM6_STIM6_W 32 +#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF +#define CPU_ITM_STIM6_STIM6_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM7 +// +//***************************************************************************** +// Field: [31:0] STIM7 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM7_STIM7_W 32 +#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF +#define CPU_ITM_STIM7_STIM7_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM8 +// +//***************************************************************************** +// Field: [31:0] STIM8 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM8_STIM8_W 32 +#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF +#define CPU_ITM_STIM8_STIM8_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM9 +// +//***************************************************************************** +// Field: [31:0] STIM9 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM9_STIM9_W 32 +#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF +#define CPU_ITM_STIM9_STIM9_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM10 +// +//***************************************************************************** +// Field: [31:0] STIM10 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM10_STIM10_W 32 +#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF +#define CPU_ITM_STIM10_STIM10_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM11 +// +//***************************************************************************** +// Field: [31:0] STIM11 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM11_STIM11_W 32 +#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF +#define CPU_ITM_STIM11_STIM11_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM12 +// +//***************************************************************************** +// Field: [31:0] STIM12 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM12_STIM12_W 32 +#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF +#define CPU_ITM_STIM12_STIM12_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM13 +// +//***************************************************************************** +// Field: [31:0] STIM13 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM13_STIM13_W 32 +#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF +#define CPU_ITM_STIM13_STIM13_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM14 +// +//***************************************************************************** +// Field: [31:0] STIM14 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM14_STIM14_W 32 +#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF +#define CPU_ITM_STIM14_STIM14_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM15 +// +//***************************************************************************** +// Field: [31:0] STIM15 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM15_STIM15_W 32 +#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF +#define CPU_ITM_STIM15_STIM15_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM16 +// +//***************************************************************************** +// Field: [31:0] STIM16 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM16_STIM16_W 32 +#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF +#define CPU_ITM_STIM16_STIM16_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM17 +// +//***************************************************************************** +// Field: [31:0] STIM17 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM17_STIM17_W 32 +#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF +#define CPU_ITM_STIM17_STIM17_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM18 +// +//***************************************************************************** +// Field: [31:0] STIM18 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM18_STIM18_W 32 +#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF +#define CPU_ITM_STIM18_STIM18_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM19 +// +//***************************************************************************** +// Field: [31:0] STIM19 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM19_STIM19_W 32 +#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF +#define CPU_ITM_STIM19_STIM19_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM20 +// +//***************************************************************************** +// Field: [31:0] STIM20 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM20_STIM20_W 32 +#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF +#define CPU_ITM_STIM20_STIM20_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM21 +// +//***************************************************************************** +// Field: [31:0] STIM21 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM21_STIM21_W 32 +#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF +#define CPU_ITM_STIM21_STIM21_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM22 +// +//***************************************************************************** +// Field: [31:0] STIM22 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM22_STIM22_W 32 +#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF +#define CPU_ITM_STIM22_STIM22_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM23 +// +//***************************************************************************** +// Field: [31:0] STIM23 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM23_STIM23_W 32 +#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF +#define CPU_ITM_STIM23_STIM23_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM24 +// +//***************************************************************************** +// Field: [31:0] STIM24 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM24_STIM24_W 32 +#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF +#define CPU_ITM_STIM24_STIM24_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM25 +// +//***************************************************************************** +// Field: [31:0] STIM25 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM25_STIM25_W 32 +#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF +#define CPU_ITM_STIM25_STIM25_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM26 +// +//***************************************************************************** +// Field: [31:0] STIM26 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM26_STIM26_W 32 +#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF +#define CPU_ITM_STIM26_STIM26_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM27 +// +//***************************************************************************** +// Field: [31:0] STIM27 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM27_STIM27_W 32 +#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF +#define CPU_ITM_STIM27_STIM27_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM28 +// +//***************************************************************************** +// Field: [31:0] STIM28 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM28_STIM28_W 32 +#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF +#define CPU_ITM_STIM28_STIM28_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM29 +// +//***************************************************************************** +// Field: [31:0] STIM29 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM29_STIM29_W 32 +#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF +#define CPU_ITM_STIM29_STIM29_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM30 +// +//***************************************************************************** +// Field: [31:0] STIM30 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM30_STIM30_W 32 +#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF +#define CPU_ITM_STIM30_STIM30_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM31 +// +//***************************************************************************** +// Field: [31:0] STIM31 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM31_STIM31_W 32 +#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF +#define CPU_ITM_STIM31_STIM31_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TER +// +//***************************************************************************** +// Field: [31] STIMENA31 +// +// Bit mask to enable tracing on ITM stimulus port 31. +#define CPU_ITM_TER_STIMENA31 0x80000000 +#define CPU_ITM_TER_STIMENA31_BITN 31 +#define CPU_ITM_TER_STIMENA31_M 0x80000000 +#define CPU_ITM_TER_STIMENA31_S 31 + +// Field: [30] STIMENA30 +// +// Bit mask to enable tracing on ITM stimulus port 30. +#define CPU_ITM_TER_STIMENA30 0x40000000 +#define CPU_ITM_TER_STIMENA30_BITN 30 +#define CPU_ITM_TER_STIMENA30_M 0x40000000 +#define CPU_ITM_TER_STIMENA30_S 30 + +// Field: [29] STIMENA29 +// +// Bit mask to enable tracing on ITM stimulus port 29. +#define CPU_ITM_TER_STIMENA29 0x20000000 +#define CPU_ITM_TER_STIMENA29_BITN 29 +#define CPU_ITM_TER_STIMENA29_M 0x20000000 +#define CPU_ITM_TER_STIMENA29_S 29 + +// Field: [28] STIMENA28 +// +// Bit mask to enable tracing on ITM stimulus port 28. +#define CPU_ITM_TER_STIMENA28 0x10000000 +#define CPU_ITM_TER_STIMENA28_BITN 28 +#define CPU_ITM_TER_STIMENA28_M 0x10000000 +#define CPU_ITM_TER_STIMENA28_S 28 + +// Field: [27] STIMENA27 +// +// Bit mask to enable tracing on ITM stimulus port 27. +#define CPU_ITM_TER_STIMENA27 0x08000000 +#define CPU_ITM_TER_STIMENA27_BITN 27 +#define CPU_ITM_TER_STIMENA27_M 0x08000000 +#define CPU_ITM_TER_STIMENA27_S 27 + +// Field: [26] STIMENA26 +// +// Bit mask to enable tracing on ITM stimulus port 26. +#define CPU_ITM_TER_STIMENA26 0x04000000 +#define CPU_ITM_TER_STIMENA26_BITN 26 +#define CPU_ITM_TER_STIMENA26_M 0x04000000 +#define CPU_ITM_TER_STIMENA26_S 26 + +// Field: [25] STIMENA25 +// +// Bit mask to enable tracing on ITM stimulus port 25. +#define CPU_ITM_TER_STIMENA25 0x02000000 +#define CPU_ITM_TER_STIMENA25_BITN 25 +#define CPU_ITM_TER_STIMENA25_M 0x02000000 +#define CPU_ITM_TER_STIMENA25_S 25 + +// Field: [24] STIMENA24 +// +// Bit mask to enable tracing on ITM stimulus port 24. +#define CPU_ITM_TER_STIMENA24 0x01000000 +#define CPU_ITM_TER_STIMENA24_BITN 24 +#define CPU_ITM_TER_STIMENA24_M 0x01000000 +#define CPU_ITM_TER_STIMENA24_S 24 + +// Field: [23] STIMENA23 +// +// Bit mask to enable tracing on ITM stimulus port 23. +#define CPU_ITM_TER_STIMENA23 0x00800000 +#define CPU_ITM_TER_STIMENA23_BITN 23 +#define CPU_ITM_TER_STIMENA23_M 0x00800000 +#define CPU_ITM_TER_STIMENA23_S 23 + +// Field: [22] STIMENA22 +// +// Bit mask to enable tracing on ITM stimulus port 22. +#define CPU_ITM_TER_STIMENA22 0x00400000 +#define CPU_ITM_TER_STIMENA22_BITN 22 +#define CPU_ITM_TER_STIMENA22_M 0x00400000 +#define CPU_ITM_TER_STIMENA22_S 22 + +// Field: [21] STIMENA21 +// +// Bit mask to enable tracing on ITM stimulus port 21. +#define CPU_ITM_TER_STIMENA21 0x00200000 +#define CPU_ITM_TER_STIMENA21_BITN 21 +#define CPU_ITM_TER_STIMENA21_M 0x00200000 +#define CPU_ITM_TER_STIMENA21_S 21 + +// Field: [20] STIMENA20 +// +// Bit mask to enable tracing on ITM stimulus port 20. +#define CPU_ITM_TER_STIMENA20 0x00100000 +#define CPU_ITM_TER_STIMENA20_BITN 20 +#define CPU_ITM_TER_STIMENA20_M 0x00100000 +#define CPU_ITM_TER_STIMENA20_S 20 + +// Field: [19] STIMENA19 +// +// Bit mask to enable tracing on ITM stimulus port 19. +#define CPU_ITM_TER_STIMENA19 0x00080000 +#define CPU_ITM_TER_STIMENA19_BITN 19 +#define CPU_ITM_TER_STIMENA19_M 0x00080000 +#define CPU_ITM_TER_STIMENA19_S 19 + +// Field: [18] STIMENA18 +// +// Bit mask to enable tracing on ITM stimulus port 18. +#define CPU_ITM_TER_STIMENA18 0x00040000 +#define CPU_ITM_TER_STIMENA18_BITN 18 +#define CPU_ITM_TER_STIMENA18_M 0x00040000 +#define CPU_ITM_TER_STIMENA18_S 18 + +// Field: [17] STIMENA17 +// +// Bit mask to enable tracing on ITM stimulus port 17. +#define CPU_ITM_TER_STIMENA17 0x00020000 +#define CPU_ITM_TER_STIMENA17_BITN 17 +#define CPU_ITM_TER_STIMENA17_M 0x00020000 +#define CPU_ITM_TER_STIMENA17_S 17 + +// Field: [16] STIMENA16 +// +// Bit mask to enable tracing on ITM stimulus port 16. +#define CPU_ITM_TER_STIMENA16 0x00010000 +#define CPU_ITM_TER_STIMENA16_BITN 16 +#define CPU_ITM_TER_STIMENA16_M 0x00010000 +#define CPU_ITM_TER_STIMENA16_S 16 + +// Field: [15] STIMENA15 +// +// Bit mask to enable tracing on ITM stimulus port 15. +#define CPU_ITM_TER_STIMENA15 0x00008000 +#define CPU_ITM_TER_STIMENA15_BITN 15 +#define CPU_ITM_TER_STIMENA15_M 0x00008000 +#define CPU_ITM_TER_STIMENA15_S 15 + +// Field: [14] STIMENA14 +// +// Bit mask to enable tracing on ITM stimulus port 14. +#define CPU_ITM_TER_STIMENA14 0x00004000 +#define CPU_ITM_TER_STIMENA14_BITN 14 +#define CPU_ITM_TER_STIMENA14_M 0x00004000 +#define CPU_ITM_TER_STIMENA14_S 14 + +// Field: [13] STIMENA13 +// +// Bit mask to enable tracing on ITM stimulus port 13. +#define CPU_ITM_TER_STIMENA13 0x00002000 +#define CPU_ITM_TER_STIMENA13_BITN 13 +#define CPU_ITM_TER_STIMENA13_M 0x00002000 +#define CPU_ITM_TER_STIMENA13_S 13 + +// Field: [12] STIMENA12 +// +// Bit mask to enable tracing on ITM stimulus port 12. +#define CPU_ITM_TER_STIMENA12 0x00001000 +#define CPU_ITM_TER_STIMENA12_BITN 12 +#define CPU_ITM_TER_STIMENA12_M 0x00001000 +#define CPU_ITM_TER_STIMENA12_S 12 + +// Field: [11] STIMENA11 +// +// Bit mask to enable tracing on ITM stimulus port 11. +#define CPU_ITM_TER_STIMENA11 0x00000800 +#define CPU_ITM_TER_STIMENA11_BITN 11 +#define CPU_ITM_TER_STIMENA11_M 0x00000800 +#define CPU_ITM_TER_STIMENA11_S 11 + +// Field: [10] STIMENA10 +// +// Bit mask to enable tracing on ITM stimulus port 10. +#define CPU_ITM_TER_STIMENA10 0x00000400 +#define CPU_ITM_TER_STIMENA10_BITN 10 +#define CPU_ITM_TER_STIMENA10_M 0x00000400 +#define CPU_ITM_TER_STIMENA10_S 10 + +// Field: [9] STIMENA9 +// +// Bit mask to enable tracing on ITM stimulus port 9. +#define CPU_ITM_TER_STIMENA9 0x00000200 +#define CPU_ITM_TER_STIMENA9_BITN 9 +#define CPU_ITM_TER_STIMENA9_M 0x00000200 +#define CPU_ITM_TER_STIMENA9_S 9 + +// Field: [8] STIMENA8 +// +// Bit mask to enable tracing on ITM stimulus port 8. +#define CPU_ITM_TER_STIMENA8 0x00000100 +#define CPU_ITM_TER_STIMENA8_BITN 8 +#define CPU_ITM_TER_STIMENA8_M 0x00000100 +#define CPU_ITM_TER_STIMENA8_S 8 + +// Field: [7] STIMENA7 +// +// Bit mask to enable tracing on ITM stimulus port 7. +#define CPU_ITM_TER_STIMENA7 0x00000080 +#define CPU_ITM_TER_STIMENA7_BITN 7 +#define CPU_ITM_TER_STIMENA7_M 0x00000080 +#define CPU_ITM_TER_STIMENA7_S 7 + +// Field: [6] STIMENA6 +// +// Bit mask to enable tracing on ITM stimulus port 6. +#define CPU_ITM_TER_STIMENA6 0x00000040 +#define CPU_ITM_TER_STIMENA6_BITN 6 +#define CPU_ITM_TER_STIMENA6_M 0x00000040 +#define CPU_ITM_TER_STIMENA6_S 6 + +// Field: [5] STIMENA5 +// +// Bit mask to enable tracing on ITM stimulus port 5. +#define CPU_ITM_TER_STIMENA5 0x00000020 +#define CPU_ITM_TER_STIMENA5_BITN 5 +#define CPU_ITM_TER_STIMENA5_M 0x00000020 +#define CPU_ITM_TER_STIMENA5_S 5 + +// Field: [4] STIMENA4 +// +// Bit mask to enable tracing on ITM stimulus port 4. +#define CPU_ITM_TER_STIMENA4 0x00000010 +#define CPU_ITM_TER_STIMENA4_BITN 4 +#define CPU_ITM_TER_STIMENA4_M 0x00000010 +#define CPU_ITM_TER_STIMENA4_S 4 + +// Field: [3] STIMENA3 +// +// Bit mask to enable tracing on ITM stimulus port 3. +#define CPU_ITM_TER_STIMENA3 0x00000008 +#define CPU_ITM_TER_STIMENA3_BITN 3 +#define CPU_ITM_TER_STIMENA3_M 0x00000008 +#define CPU_ITM_TER_STIMENA3_S 3 + +// Field: [2] STIMENA2 +// +// Bit mask to enable tracing on ITM stimulus port 2. +#define CPU_ITM_TER_STIMENA2 0x00000004 +#define CPU_ITM_TER_STIMENA2_BITN 2 +#define CPU_ITM_TER_STIMENA2_M 0x00000004 +#define CPU_ITM_TER_STIMENA2_S 2 + +// Field: [1] STIMENA1 +// +// Bit mask to enable tracing on ITM stimulus port 1. +#define CPU_ITM_TER_STIMENA1 0x00000002 +#define CPU_ITM_TER_STIMENA1_BITN 1 +#define CPU_ITM_TER_STIMENA1_M 0x00000002 +#define CPU_ITM_TER_STIMENA1_S 1 + +// Field: [0] STIMENA0 +// +// Bit mask to enable tracing on ITM stimulus port 0. +#define CPU_ITM_TER_STIMENA0 0x00000001 +#define CPU_ITM_TER_STIMENA0_BITN 0 +#define CPU_ITM_TER_STIMENA0_M 0x00000001 +#define CPU_ITM_TER_STIMENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TPR +// +//***************************************************************************** +// Field: [3:0] PRIVMASK +// +// Bit mask to enable unprivileged (User) access to ITM stimulus ports: +// +// Bit [0] enables stimulus ports 0, 1, ..., and 7. +// Bit [1] enables stimulus ports 8, 9, ..., and 15. +// Bit [2] enables stimulus ports 16, 17, ..., and 23. +// Bit [3] enables stimulus ports 24, 25, ..., and 31. +// +// 0: User access allowed to stimulus ports +// 1: Privileged access only to stimulus ports +#define CPU_ITM_TPR_PRIVMASK_W 4 +#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F +#define CPU_ITM_TPR_PRIVMASK_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TCR +// +//***************************************************************************** +// Field: [23] BUSY +// +// Set when ITM events present and being drained. +#define CPU_ITM_TCR_BUSY 0x00800000 +#define CPU_ITM_TCR_BUSY_BITN 23 +#define CPU_ITM_TCR_BUSY_M 0x00800000 +#define CPU_ITM_TCR_BUSY_S 23 + +// Field: [22:16] ATBID +// +// Trace Bus ID for CoreSight system. Optional identifier for multi-source +// trace stream formatting. If multi-source trace is in use, this field must be +// written with a non-zero value. +#define CPU_ITM_TCR_ATBID_W 7 +#define CPU_ITM_TCR_ATBID_M 0x007F0000 +#define CPU_ITM_TCR_ATBID_S 16 + +// Field: [9:8] TSPRESCALE +// +// Timestamp prescaler +// ENUMs: +// DIV64 Divide by 64 +// DIV16 Divide by 16 +// DIV4 Divide by 4 +// NOPRESCALING No prescaling +#define CPU_ITM_TCR_TSPRESCALE_W 2 +#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_S 8 +#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 +#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 +#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 + +// Field: [4] SWOENA +// +// Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If +// TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of +// the timestamp counter. +// +// 0x0: Mode disabled. Timestamp counter uses system clock from the core and +// counts continuously. +// 0x1: Timestamp counter uses lineout (data related) clock from TPIU +// interface. The timestamp counter is held in reset while the output line is +// idle. +#define CPU_ITM_TCR_SWOENA 0x00000010 +#define CPU_ITM_TCR_SWOENA_BITN 4 +#define CPU_ITM_TCR_SWOENA_M 0x00000010 +#define CPU_ITM_TCR_SWOENA_S 4 + +// Field: [3] DWTENA +// +// Enables the DWT stimulus (hardware event packet emission to the TPIU from +// the DWT) +#define CPU_ITM_TCR_DWTENA 0x00000008 +#define CPU_ITM_TCR_DWTENA_BITN 3 +#define CPU_ITM_TCR_DWTENA_M 0x00000008 +#define CPU_ITM_TCR_DWTENA_S 3 + +// Field: [2] SYNCENA +// +// Enables synchronization packet transmission for a synchronous TPIU. +// CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization +// speed. +#define CPU_ITM_TCR_SYNCENA 0x00000004 +#define CPU_ITM_TCR_SYNCENA_BITN 2 +#define CPU_ITM_TCR_SYNCENA_M 0x00000004 +#define CPU_ITM_TCR_SYNCENA_S 2 + +// Field: [1] TSENA +// +// Enables differential timestamps. Differential timestamps are emitted when a +// packet is written to the FIFO with a non-zero timestamp counter, and when +// the timestamp counter overflows. Timestamps are emitted during idle times +// after a fixed number of two million cycles. This provides a time reference +// for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps +// are triggered by activity on the internal trace bus only. In this case there +// is no regular timestamp output when the ITM is idle. +#define CPU_ITM_TCR_TSENA 0x00000002 +#define CPU_ITM_TCR_TSENA_BITN 1 +#define CPU_ITM_TCR_TSENA_M 0x00000002 +#define CPU_ITM_TCR_TSENA_S 1 + +// Field: [0] ITMENA +// +// Enables ITM. This is the master enable, and must be set before ITM Stimulus +// and Trace Enable registers can be written. +#define CPU_ITM_TCR_ITMENA 0x00000001 +#define CPU_ITM_TCR_ITMENA_BITN 0 +#define CPU_ITM_TCR_ITMENA_M 0x00000001 +#define CPU_ITM_TCR_ITMENA_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_LAR +// +//***************************************************************************** +// Field: [31:0] LOCK_ACCESS +// +// A privileged write of 0xC5ACCE55 enables more write access to Control +// Registers TER, TPR and TCR. An invalid write removes write access. +#define CPU_ITM_LAR_LOCK_ACCESS_W 32 +#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF +#define CPU_ITM_LAR_LOCK_ACCESS_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_LSR +// +//***************************************************************************** +// Field: [2] BYTEACC +// +// Reads 0 which means 8-bit lock access is not be implemented. +#define CPU_ITM_LSR_BYTEACC 0x00000004 +#define CPU_ITM_LSR_BYTEACC_BITN 2 +#define CPU_ITM_LSR_BYTEACC_M 0x00000004 +#define CPU_ITM_LSR_BYTEACC_S 2 + +// Field: [1] ACCESS +// +// Write access to component is blocked. All writes are ignored, reads are +// permitted. +#define CPU_ITM_LSR_ACCESS 0x00000002 +#define CPU_ITM_LSR_ACCESS_BITN 1 +#define CPU_ITM_LSR_ACCESS_M 0x00000002 +#define CPU_ITM_LSR_ACCESS_S 1 + +// Field: [0] PRESENT +// +// Indicates that a lock mechanism exists for this component. +#define CPU_ITM_LSR_PRESENT 0x00000001 +#define CPU_ITM_LSR_PRESENT_BITN 0 +#define CPU_ITM_LSR_PRESENT_M 0x00000001 +#define CPU_ITM_LSR_PRESENT_S 0 + + +#endif // __CPU_ITM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h new file mode 100644 index 0000000..69bf441 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h @@ -0,0 +1,220 @@ +/****************************************************************************** +* Filename: hw_cpu_rom_table_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_ROM_TABLE_H__ +#define __HW_CPU_ROM_TABLE_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_ROM_TABLE component +// +//***************************************************************************** +// System Control Space Component +#define CPU_ROM_TABLE_O_SCS 0x00000000 + +// Data Watchpoint and Trace Component +#define CPU_ROM_TABLE_O_DWT 0x00000004 + +// Flash Patch and Breakpoint Component +#define CPU_ROM_TABLE_O_FPB 0x00000008 + +// Instrumentation Trace Component +#define CPU_ROM_TABLE_O_ITM 0x0000000C + +// Trace Port Interface Component +#define CPU_ROM_TABLE_O_TPIU 0x00000010 + +// Enhanced Trace Component +#define CPU_ROM_TABLE_O_ETM 0x00000014 + +// End Marker +#define CPU_ROM_TABLE_O_END 0x00000018 + +// System Memory Map Access for DAP +#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_SCS +// +//***************************************************************************** +// Field: [31:0] SCS +// +// Points to the SCS at 0xE000E000. +// (SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000. +#define CPU_ROM_TABLE_SCS_SCS_W 32 +#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF +#define CPU_ROM_TABLE_SCS_SCS_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_DWT +// +//***************************************************************************** +// Field: [31:1] DWT +// +// Points to the Data Watchpoint and Trace block at 0xE0001000. +// (2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000. +#define CPU_ROM_TABLE_DWT_DWT_W 31 +#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE +#define CPU_ROM_TABLE_DWT_DWT_S 1 + +// Field: [0] DWT_PRESENT +// +// 0: DWT is not present +// 1: DWT is present. +#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_FPB +// +//***************************************************************************** +// Field: [31:1] FPB +// +// Points to the Flash Patch and Breakpoint block at 0xE0002000. +// (2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000. +#define CPU_ROM_TABLE_FPB_FPB_W 31 +#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE +#define CPU_ROM_TABLE_FPB_FPB_S 1 + +// Field: [0] FPB_PRESENT +// +// 0: FPB is not present +// 1: FPB is present. +#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_ITM +// +//***************************************************************************** +// Field: [31:1] ITM +// +// Points to the Instrumentation Trace block at 0xE0000000. +// (2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000. +#define CPU_ROM_TABLE_ITM_ITM_W 31 +#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ITM_ITM_S 1 + +// Field: [0] ITM_PRESENT +// +// 0: ITM is not present +// 1: ITM is present. +#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_TPIU +// +//***************************************************************************** +// Field: [31:1] TPIU +// +// Points to the TPIU. TPIU is at 0xE0040000. +// (2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000. +#define CPU_ROM_TABLE_TPIU_TPIU_W 31 +#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE +#define CPU_ROM_TABLE_TPIU_TPIU_S 1 + +// Field: [0] TPIU_PRESENT +// +// 0: TPIU is not present +// 1: TPIU is present. +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_ETM +// +//***************************************************************************** +// Field: [31:1] ETM +// +// Points to the ETM. ETM is at 0xE0041000. +// (2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000. +#define CPU_ROM_TABLE_ETM_ETM_W 31 +#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ETM_ETM_S 1 + +// Field: [0] ETM_PRESENT +// +// 0: ETM is not present +// 1: ETM is present. +#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_END +// +//***************************************************************************** +// Field: [31:0] END +// +// End of the ROM table +#define CPU_ROM_TABLE_END_END_W 32 +#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF +#define CPU_ROM_TABLE_END_END_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_SYSTEM_ACCESS +// +//***************************************************************************** +// Field: [0] SYSTEM_ACCESS +// +// 1: The system memory map is accessible using the DAP +// 0: Only debug resources are accessible using the DAP +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 + + +#endif // __CPU_ROM_TABLE__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h new file mode 100644 index 0000000..33ccf0c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h @@ -0,0 +1,4789 @@ +/****************************************************************************** +* Filename: hw_cpu_scs_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_SCS_H__ +#define __HW_CPU_SCS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_SCS component +// +//***************************************************************************** +// Interrupt Control Type +#define CPU_SCS_O_ICTR 0x00000004 + +// Auxiliary Control +#define CPU_SCS_O_ACTLR 0x00000008 + +// SysTick Control and Status +#define CPU_SCS_O_STCSR 0x00000010 + +// SysTick Reload Value +#define CPU_SCS_O_STRVR 0x00000014 + +// SysTick Current Value +#define CPU_SCS_O_STCVR 0x00000018 + +// SysTick Calibration Value +#define CPU_SCS_O_STCR 0x0000001C + +// Irq 0 to 31 Set Enable +#define CPU_SCS_O_NVIC_ISER0 0x00000100 + +// Irq 32 to 63 Set Enable +#define CPU_SCS_O_NVIC_ISER1 0x00000104 + +// Irq 0 to 31 Clear Enable +#define CPU_SCS_O_NVIC_ICER0 0x00000180 + +// Irq 32 to 63 Clear Enable +#define CPU_SCS_O_NVIC_ICER1 0x00000184 + +// Irq 0 to 31 Set Pending +#define CPU_SCS_O_NVIC_ISPR0 0x00000200 + +// Irq 32 to 63 Set Pending +#define CPU_SCS_O_NVIC_ISPR1 0x00000204 + +// Irq 0 to 31 Clear Pending +#define CPU_SCS_O_NVIC_ICPR0 0x00000280 + +// Irq 32 to 63 Clear Pending +#define CPU_SCS_O_NVIC_ICPR1 0x00000284 + +// Irq 0 to 31 Active Bit +#define CPU_SCS_O_NVIC_IABR0 0x00000300 + +// Irq 32 to 63 Active Bit +#define CPU_SCS_O_NVIC_IABR1 0x00000304 + +// Irq 0 to 3 Priority +#define CPU_SCS_O_NVIC_IPR0 0x00000400 + +// Irq 4 to 7 Priority +#define CPU_SCS_O_NVIC_IPR1 0x00000404 + +// Irq 8 to 11 Priority +#define CPU_SCS_O_NVIC_IPR2 0x00000408 + +// Irq 12 to 15 Priority +#define CPU_SCS_O_NVIC_IPR3 0x0000040C + +// Irq 16 to 19 Priority +#define CPU_SCS_O_NVIC_IPR4 0x00000410 + +// Irq 20 to 23 Priority +#define CPU_SCS_O_NVIC_IPR5 0x00000414 + +// Irq 24 to 27 Priority +#define CPU_SCS_O_NVIC_IPR6 0x00000418 + +// Irq 28 to 31 Priority +#define CPU_SCS_O_NVIC_IPR7 0x0000041C + +// Irq 32 to 35 Priority +#define CPU_SCS_O_NVIC_IPR8 0x00000420 + +// Irq 32 to 35 Priority +#define CPU_SCS_O_NVIC_IPR9 0x00000424 + +// CPUID Base +#define CPU_SCS_O_CPUID 0x00000D00 + +// Interrupt Control State +#define CPU_SCS_O_ICSR 0x00000D04 + +// Vector Table Offset +#define CPU_SCS_O_VTOR 0x00000D08 + +// Application Interrupt/Reset Control +#define CPU_SCS_O_AIRCR 0x00000D0C + +// System Control +#define CPU_SCS_O_SCR 0x00000D10 + +// Configuration Control +#define CPU_SCS_O_CCR 0x00000D14 + +// System Handlers 4-7 Priority +#define CPU_SCS_O_SHPR1 0x00000D18 + +// System Handlers 8-11 Priority +#define CPU_SCS_O_SHPR2 0x00000D1C + +// System Handlers 12-15 Priority +#define CPU_SCS_O_SHPR3 0x00000D20 + +// System Handler Control and State +#define CPU_SCS_O_SHCSR 0x00000D24 + +// Configurable Fault Status +#define CPU_SCS_O_CFSR 0x00000D28 + +// Hard Fault Status +#define CPU_SCS_O_HFSR 0x00000D2C + +// Debug Fault Status +#define CPU_SCS_O_DFSR 0x00000D30 + +// Mem Manage Fault Address +#define CPU_SCS_O_MMFAR 0x00000D34 + +// Bus Fault Address +#define CPU_SCS_O_BFAR 0x00000D38 + +// Auxiliary Fault Status +#define CPU_SCS_O_AFSR 0x00000D3C + +// Processor Feature 0 +#define CPU_SCS_O_ID_PFR0 0x00000D40 + +// Processor Feature 1 +#define CPU_SCS_O_ID_PFR1 0x00000D44 + +// Debug Feature 0 +#define CPU_SCS_O_ID_DFR0 0x00000D48 + +// Auxiliary Feature 0 +#define CPU_SCS_O_ID_AFR0 0x00000D4C + +// Memory Model Feature 0 +#define CPU_SCS_O_ID_MMFR0 0x00000D50 + +// Memory Model Feature 1 +#define CPU_SCS_O_ID_MMFR1 0x00000D54 + +// Memory Model Feature 2 +#define CPU_SCS_O_ID_MMFR2 0x00000D58 + +// Memory Model Feature 3 +#define CPU_SCS_O_ID_MMFR3 0x00000D5C + +// ISA Feature 0 +#define CPU_SCS_O_ID_ISAR0 0x00000D60 + +// ISA Feature 1 +#define CPU_SCS_O_ID_ISAR1 0x00000D64 + +// ISA Feature 2 +#define CPU_SCS_O_ID_ISAR2 0x00000D68 + +// ISA Feature 3 +#define CPU_SCS_O_ID_ISAR3 0x00000D6C + +// ISA Feature 4 +#define CPU_SCS_O_ID_ISAR4 0x00000D70 + +// Coprocessor Access Control +#define CPU_SCS_O_CPACR 0x00000D88 + +// MPU Type +#define CPU_SCS_O_MPU_TYPE 0x00000D90 + +// MPU Control +#define CPU_SCS_O_MPU_CTRL 0x00000D94 + +// MPU Region Number +#define CPU_SCS_O_MPU_RNR 0x00000D98 + +// MPU Region Base Address +#define CPU_SCS_O_MPU_RBAR 0x00000D9C + +// MPU Region Attribute and Size +#define CPU_SCS_O_MPU_RASR 0x00000DA0 + +// MPU Alias 1 Region Base Address +#define CPU_SCS_O_MPU_RBAR_A1 0x00000DA4 + +// MPU Alias 1 Region Attribute and Size +#define CPU_SCS_O_MPU_RASR_A1 0x00000DA8 + +// MPU Alias 2 Region Base Address +#define CPU_SCS_O_MPU_RBAR_A2 0x00000DAC + +// MPU Alias 2 Region Attribute and Size +#define CPU_SCS_O_MPU_RASR_A2 0x00000DB0 + +// MPU Alias 3 Region Base Address +#define CPU_SCS_O_MPU_RBAR_A3 0x00000DB4 + +// MPU Alias 3 Region Attribute and Size +#define CPU_SCS_O_MPU_RASR_A3 0x00000DB8 + +// Debug Halting Control and Status +#define CPU_SCS_O_DHCSR 0x00000DF0 + +// Deubg Core Register Selector +#define CPU_SCS_O_DCRSR 0x00000DF4 + +// Debug Core Register Data +#define CPU_SCS_O_DCRDR 0x00000DF8 + +// Debug Exception and Monitor Control +#define CPU_SCS_O_DEMCR 0x00000DFC + +// Software Trigger Interrupt +#define CPU_SCS_O_STIR 0x00000F00 + +// Floating Point Context Control +#define CPU_SCS_O_FPCCR 0x00000F34 + +// Floating-Point Context Address +#define CPU_SCS_O_FPCAR 0x00000F38 + +// Floating Point Default Status Control +#define CPU_SCS_O_FPDSCR 0x00000F3C + +// Media and FP Feature 0 +#define CPU_SCS_O_MVFR0 0x00000F40 + +// Media and FP Feature 1 +#define CPU_SCS_O_MVFR1 0x00000F44 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ICTR +// +//***************************************************************************** +// Field: [2:0] INTLINESNUM +// +// Total number of interrupt lines in groups of 32. +// +// 0: 0...32 +// 1: 33...64 +// 2: 65...96 +// 3: 97...128 +// 4: 129...160 +// 5: 161...192 +// 6: 193...224 +// 7: 225...256 +#define CPU_SCS_ICTR_INTLINESNUM_W 3 +#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 +#define CPU_SCS_ICTR_INTLINESNUM_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ACTLR +// +//***************************************************************************** +// Field: [9] DISOOFP +// +// Disables floating point instructions completing out of order with respect to +// integer instructions. +#define CPU_SCS_ACTLR_DISOOFP 0x00000200 +#define CPU_SCS_ACTLR_DISOOFP_BITN 9 +#define CPU_SCS_ACTLR_DISOOFP_M 0x00000200 +#define CPU_SCS_ACTLR_DISOOFP_S 9 + +// Field: [8] DISFPCA +// +// Disable automatic update of CONTROL.FPCA +#define CPU_SCS_ACTLR_DISFPCA 0x00000100 +#define CPU_SCS_ACTLR_DISFPCA_BITN 8 +#define CPU_SCS_ACTLR_DISFPCA_M 0x00000100 +#define CPU_SCS_ACTLR_DISFPCA_S 8 + +// Field: [2] DISFOLD +// +// Disables folding of IT instruction. +#define CPU_SCS_ACTLR_DISFOLD 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_BITN 2 +#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_S 2 + +// Field: [1] DISDEFWBUF +// +// Disables write buffer use during default memory map accesses. This causes +// all bus faults to be precise bus faults but decreases the performance of the +// processor because the stores to memory have to complete before the next +// instruction can be executed. +#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 +#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 + +// Field: [0] DISMCYCINT +// +// Disables interruption of multi-cycle instructions. This increases the +// interrupt latency of the processor becuase LDM/STM completes before +// interrupt stacking occurs. +#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 +#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCSR +// +//***************************************************************************** +// Field: [16] COUNTFLAG +// +// Returns 1 if timer counted to 0 since last time this was read. Clears on +// read by application of any part of the SysTick Control and Status Register. +// If read by the debugger using the DAP, this bit is cleared on read-only if +// the MasterType bit in the **AHB-AP** Control Register is set to 0. +// Otherwise, COUNTFLAG is not changed by the debugger read. +#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 +#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_S 16 + +// Field: [2] CLKSOURCE +// +// Clock source: +// +// 0: External reference clock. +// 1: Core clock +// +// External clock is not available in this device. Writes to this field will be +// ignored. +#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 +#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_S 2 + +// Field: [1] TICKINT +// +// 0: Counting down to zero does not pend the SysTick handler. Software can use +// COUNTFLAG to determine if the SysTick handler has ever counted to zero. +// 1: Counting down to zero pends the SysTick handler. +#define CPU_SCS_STCSR_TICKINT 0x00000002 +#define CPU_SCS_STCSR_TICKINT_BITN 1 +#define CPU_SCS_STCSR_TICKINT_M 0x00000002 +#define CPU_SCS_STCSR_TICKINT_S 1 + +// Field: [0] ENABLE +// +// Enable SysTick counter +// +// 0: Counter disabled +// 1: Counter operates in a multi-shot way. That is, counter loads with the +// Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it +// sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on +// TICKINT. It then loads STRVR.RELOAD again, and begins counting. +#define CPU_SCS_STCSR_ENABLE 0x00000001 +#define CPU_SCS_STCSR_ENABLE_BITN 0 +#define CPU_SCS_STCSR_ENABLE_M 0x00000001 +#define CPU_SCS_STCSR_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STRVR +// +//***************************************************************************** +// Field: [23:0] RELOAD +// +// Value to load into the SysTick Current Value Register STCVR.CURRENT when the +// counter reaches 0. +#define CPU_SCS_STRVR_RELOAD_W 24 +#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF +#define CPU_SCS_STRVR_RELOAD_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCVR +// +//***************************************************************************** +// Field: [23:0] CURRENT +// +// Current value at the time the register is accessed. No read-modify-write +// protection is provided, so change with care. Writing to it with any value +// clears the register to 0. Clearing this register also clears +// STCSR.COUNTFLAG. +#define CPU_SCS_STCVR_CURRENT_W 24 +#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF +#define CPU_SCS_STCVR_CURRENT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCR +// +//***************************************************************************** +// Field: [31] NOREF +// +// Reads as one. Indicates that no separate reference clock is provided. +#define CPU_SCS_STCR_NOREF 0x80000000 +#define CPU_SCS_STCR_NOREF_BITN 31 +#define CPU_SCS_STCR_NOREF_M 0x80000000 +#define CPU_SCS_STCR_NOREF_S 31 + +// Field: [30] SKEW +// +// Reads as one. The calibration value is not exactly 10ms because of clock +// frequency. This could affect its suitability as a software real time clock. +#define CPU_SCS_STCR_SKEW 0x40000000 +#define CPU_SCS_STCR_SKEW_BITN 30 +#define CPU_SCS_STCR_SKEW_M 0x40000000 +#define CPU_SCS_STCR_SKEW_S 30 + +// Field: [23:0] TENMS +// +// An optional Reload value to be used for 10ms (100Hz) timing, subject to +// system clock skew errors. The value read is valid only when core clock is at +// 48MHz. +#define CPU_SCS_STCR_TENMS_W 24 +#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF +#define CPU_SCS_STCR_TENMS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISER0 +// +//***************************************************************************** +// Field: [31] SETENA31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 +#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 + +// Field: [30] SETENA30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 +#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 + +// Field: [29] SETENA29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 +#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 + +// Field: [28] SETENA28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 +#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 + +// Field: [27] SETENA27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 +#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 + +// Field: [26] SETENA26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 +#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 + +// Field: [25] SETENA25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 +#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 + +// Field: [24] SETENA24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 +#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 + +// Field: [23] SETENA23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 +#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 + +// Field: [22] SETENA22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 +#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 + +// Field: [21] SETENA21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 +#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 + +// Field: [20] SETENA20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 +#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 + +// Field: [19] SETENA19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 +#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 + +// Field: [18] SETENA18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 +#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 + +// Field: [17] SETENA17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 +#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 + +// Field: [16] SETENA16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 +#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 + +// Field: [15] SETENA15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 +#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 + +// Field: [14] SETENA14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 +#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 + +// Field: [13] SETENA13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 +#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 + +// Field: [12] SETENA12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 +#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 + +// Field: [11] SETENA11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 +#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 + +// Field: [10] SETENA10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 +#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 + +// Field: [9] SETENA9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 +#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 + +// Field: [8] SETENA8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 +#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 + +// Field: [7] SETENA7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 +#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 + +// Field: [6] SETENA6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 +#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 + +// Field: [5] SETENA5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 +#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 + +// Field: [4] SETENA4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 +#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 + +// Field: [3] SETENA3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 +#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 + +// Field: [2] SETENA2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 +#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 + +// Field: [1] SETENA1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 +#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 + +// Field: [0] SETENA0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 +#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISER1 +// +//***************************************************************************** +// Field: [5] SETENA37 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA37 0x00000020 +#define CPU_SCS_NVIC_ISER1_SETENA37_BITN 5 +#define CPU_SCS_NVIC_ISER1_SETENA37_M 0x00000020 +#define CPU_SCS_NVIC_ISER1_SETENA37_S 5 + +// Field: [4] SETENA36 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA36 0x00000010 +#define CPU_SCS_NVIC_ISER1_SETENA36_BITN 4 +#define CPU_SCS_NVIC_ISER1_SETENA36_M 0x00000010 +#define CPU_SCS_NVIC_ISER1_SETENA36_S 4 + +// Field: [3] SETENA35 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA35 0x00000008 +#define CPU_SCS_NVIC_ISER1_SETENA35_BITN 3 +#define CPU_SCS_NVIC_ISER1_SETENA35_M 0x00000008 +#define CPU_SCS_NVIC_ISER1_SETENA35_S 3 + +// Field: [2] SETENA34 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA34 0x00000004 +#define CPU_SCS_NVIC_ISER1_SETENA34_BITN 2 +#define CPU_SCS_NVIC_ISER1_SETENA34_M 0x00000004 +#define CPU_SCS_NVIC_ISER1_SETENA34_S 2 + +// Field: [1] SETENA33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 +#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 + +// Field: [0] SETENA32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 +#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICER0 +// +//***************************************************************************** +// Field: [31] CLRENA31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 +#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 + +// Field: [30] CLRENA30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 +#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 + +// Field: [29] CLRENA29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 +#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 + +// Field: [28] CLRENA28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 +#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 + +// Field: [27] CLRENA27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 +#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 + +// Field: [26] CLRENA26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 +#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 + +// Field: [25] CLRENA25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 +#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 + +// Field: [24] CLRENA24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 +#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 + +// Field: [23] CLRENA23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 +#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 + +// Field: [22] CLRENA22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 +#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 + +// Field: [21] CLRENA21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 +#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 + +// Field: [20] CLRENA20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 +#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 + +// Field: [19] CLRENA19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 +#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 + +// Field: [18] CLRENA18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 +#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 + +// Field: [17] CLRENA17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 +#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 + +// Field: [16] CLRENA16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 +#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 + +// Field: [15] CLRENA15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 +#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 + +// Field: [14] CLRENA14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 +#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 + +// Field: [13] CLRENA13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 +#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 + +// Field: [12] CLRENA12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 +#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 + +// Field: [11] CLRENA11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 +#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 + +// Field: [10] CLRENA10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 +#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 + +// Field: [9] CLRENA9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 +#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 + +// Field: [8] CLRENA8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 +#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 + +// Field: [7] CLRENA7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 +#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 + +// Field: [6] CLRENA6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 +#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 + +// Field: [5] CLRENA5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 +#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 + +// Field: [4] CLRENA4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 +#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 + +// Field: [3] CLRENA3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 +#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 + +// Field: [2] CLRENA2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 +#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 + +// Field: [1] CLRENA1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 +#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 + +// Field: [0] CLRENA0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 +#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICER1 +// +//***************************************************************************** +// Field: [5] CLRENA37 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA37 0x00000020 +#define CPU_SCS_NVIC_ICER1_CLRENA37_BITN 5 +#define CPU_SCS_NVIC_ICER1_CLRENA37_M 0x00000020 +#define CPU_SCS_NVIC_ICER1_CLRENA37_S 5 + +// Field: [4] CLRENA36 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA36 0x00000010 +#define CPU_SCS_NVIC_ICER1_CLRENA36_BITN 4 +#define CPU_SCS_NVIC_ICER1_CLRENA36_M 0x00000010 +#define CPU_SCS_NVIC_ICER1_CLRENA36_S 4 + +// Field: [3] CLRENA35 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA35 0x00000008 +#define CPU_SCS_NVIC_ICER1_CLRENA35_BITN 3 +#define CPU_SCS_NVIC_ICER1_CLRENA35_M 0x00000008 +#define CPU_SCS_NVIC_ICER1_CLRENA35_S 3 + +// Field: [2] CLRENA34 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA34 0x00000004 +#define CPU_SCS_NVIC_ICER1_CLRENA34_BITN 2 +#define CPU_SCS_NVIC_ICER1_CLRENA34_M 0x00000004 +#define CPU_SCS_NVIC_ICER1_CLRENA34_S 2 + +// Field: [1] CLRENA33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 +#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 + +// Field: [0] CLRENA32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 +#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISPR0 +// +//***************************************************************************** +// Field: [31] SETPEND31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 + +// Field: [30] SETPEND30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 + +// Field: [29] SETPEND29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 + +// Field: [28] SETPEND28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 + +// Field: [27] SETPEND27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 + +// Field: [26] SETPEND26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 + +// Field: [25] SETPEND25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 + +// Field: [24] SETPEND24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 + +// Field: [23] SETPEND23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 + +// Field: [22] SETPEND22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 + +// Field: [21] SETPEND21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 + +// Field: [20] SETPEND20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 + +// Field: [19] SETPEND19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 + +// Field: [18] SETPEND18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 + +// Field: [17] SETPEND17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 + +// Field: [16] SETPEND16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 + +// Field: [15] SETPEND15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 + +// Field: [14] SETPEND14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 + +// Field: [13] SETPEND13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 + +// Field: [12] SETPEND12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 + +// Field: [11] SETPEND11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 + +// Field: [10] SETPEND10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 + +// Field: [9] SETPEND9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 + +// Field: [8] SETPEND8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 + +// Field: [7] SETPEND7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 + +// Field: [6] SETPEND6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 + +// Field: [5] SETPEND5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 + +// Field: [4] SETPEND4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 + +// Field: [3] SETPEND3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 + +// Field: [2] SETPEND2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 + +// Field: [1] SETPEND1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 + +// Field: [0] SETPEND0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISPR1 +// +//***************************************************************************** +// Field: [5] SETPEND37 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND37 0x00000020 +#define CPU_SCS_NVIC_ISPR1_SETPEND37_BITN 5 +#define CPU_SCS_NVIC_ISPR1_SETPEND37_M 0x00000020 +#define CPU_SCS_NVIC_ISPR1_SETPEND37_S 5 + +// Field: [4] SETPEND36 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND36 0x00000010 +#define CPU_SCS_NVIC_ISPR1_SETPEND36_BITN 4 +#define CPU_SCS_NVIC_ISPR1_SETPEND36_M 0x00000010 +#define CPU_SCS_NVIC_ISPR1_SETPEND36_S 4 + +// Field: [3] SETPEND35 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND35 0x00000008 +#define CPU_SCS_NVIC_ISPR1_SETPEND35_BITN 3 +#define CPU_SCS_NVIC_ISPR1_SETPEND35_M 0x00000008 +#define CPU_SCS_NVIC_ISPR1_SETPEND35_S 3 + +// Field: [2] SETPEND34 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND34 0x00000004 +#define CPU_SCS_NVIC_ISPR1_SETPEND34_BITN 2 +#define CPU_SCS_NVIC_ISPR1_SETPEND34_M 0x00000004 +#define CPU_SCS_NVIC_ISPR1_SETPEND34_S 2 + +// Field: [1] SETPEND33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 + +// Field: [0] SETPEND32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICPR0 +// +//***************************************************************************** +// Field: [31] CLRPEND31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 + +// Field: [30] CLRPEND30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 + +// Field: [29] CLRPEND29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 + +// Field: [28] CLRPEND28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 + +// Field: [27] CLRPEND27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 + +// Field: [26] CLRPEND26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 + +// Field: [25] CLRPEND25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 + +// Field: [24] CLRPEND24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 + +// Field: [23] CLRPEND23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 + +// Field: [22] CLRPEND22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 + +// Field: [21] CLRPEND21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 + +// Field: [20] CLRPEND20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 + +// Field: [19] CLRPEND19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 + +// Field: [18] CLRPEND18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 + +// Field: [17] CLRPEND17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 + +// Field: [16] CLRPEND16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 + +// Field: [15] CLRPEND15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 + +// Field: [14] CLRPEND14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 + +// Field: [13] CLRPEND13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 + +// Field: [12] CLRPEND12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 + +// Field: [11] CLRPEND11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 + +// Field: [10] CLRPEND10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 + +// Field: [9] CLRPEND9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 + +// Field: [8] CLRPEND8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 + +// Field: [7] CLRPEND7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 + +// Field: [6] CLRPEND6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 + +// Field: [5] CLRPEND5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 + +// Field: [4] CLRPEND4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 + +// Field: [3] CLRPEND3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 + +// Field: [2] CLRPEND2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 + +// Field: [1] CLRPEND1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 + +// Field: [0] CLRPEND0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICPR1 +// +//***************************************************************************** +// Field: [5] CLRPEND37 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND37 0x00000020 +#define CPU_SCS_NVIC_ICPR1_CLRPEND37_BITN 5 +#define CPU_SCS_NVIC_ICPR1_CLRPEND37_M 0x00000020 +#define CPU_SCS_NVIC_ICPR1_CLRPEND37_S 5 + +// Field: [4] CLRPEND36 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND36 0x00000010 +#define CPU_SCS_NVIC_ICPR1_CLRPEND36_BITN 4 +#define CPU_SCS_NVIC_ICPR1_CLRPEND36_M 0x00000010 +#define CPU_SCS_NVIC_ICPR1_CLRPEND36_S 4 + +// Field: [3] CLRPEND35 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND35 0x00000008 +#define CPU_SCS_NVIC_ICPR1_CLRPEND35_BITN 3 +#define CPU_SCS_NVIC_ICPR1_CLRPEND35_M 0x00000008 +#define CPU_SCS_NVIC_ICPR1_CLRPEND35_S 3 + +// Field: [2] CLRPEND34 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND34 0x00000004 +#define CPU_SCS_NVIC_ICPR1_CLRPEND34_BITN 2 +#define CPU_SCS_NVIC_ICPR1_CLRPEND34_M 0x00000004 +#define CPU_SCS_NVIC_ICPR1_CLRPEND34_S 2 + +// Field: [1] CLRPEND33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 + +// Field: [0] CLRPEND32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IABR0 +// +//***************************************************************************** +// Field: [31] ACTIVE31 +// +// Reading 0 from this bit implies that interrupt line 31 is not active. +// Reading 1 from this bit implies that the interrupt line 31 is active (See +// EVENT:CPUIRQSEL31.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 + +// Field: [30] ACTIVE30 +// +// Reading 0 from this bit implies that interrupt line 30 is not active. +// Reading 1 from this bit implies that the interrupt line 30 is active (See +// EVENT:CPUIRQSEL30.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 + +// Field: [29] ACTIVE29 +// +// Reading 0 from this bit implies that interrupt line 29 is not active. +// Reading 1 from this bit implies that the interrupt line 29 is active (See +// EVENT:CPUIRQSEL29.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 + +// Field: [28] ACTIVE28 +// +// Reading 0 from this bit implies that interrupt line 28 is not active. +// Reading 1 from this bit implies that the interrupt line 28 is active (See +// EVENT:CPUIRQSEL28.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 + +// Field: [27] ACTIVE27 +// +// Reading 0 from this bit implies that interrupt line 27 is not active. +// Reading 1 from this bit implies that the interrupt line 27 is active (See +// EVENT:CPUIRQSEL27.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 + +// Field: [26] ACTIVE26 +// +// Reading 0 from this bit implies that interrupt line 26 is not active. +// Reading 1 from this bit implies that the interrupt line 26 is active (See +// EVENT:CPUIRQSEL26.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 + +// Field: [25] ACTIVE25 +// +// Reading 0 from this bit implies that interrupt line 25 is not active. +// Reading 1 from this bit implies that the interrupt line 25 is active (See +// EVENT:CPUIRQSEL25.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 + +// Field: [24] ACTIVE24 +// +// Reading 0 from this bit implies that interrupt line 24 is not active. +// Reading 1 from this bit implies that the interrupt line 24 is active (See +// EVENT:CPUIRQSEL24.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 + +// Field: [23] ACTIVE23 +// +// Reading 0 from this bit implies that interrupt line 23 is not active. +// Reading 1 from this bit implies that the interrupt line 23 is active (See +// EVENT:CPUIRQSEL23.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 + +// Field: [22] ACTIVE22 +// +// Reading 0 from this bit implies that interrupt line 22 is not active. +// Reading 1 from this bit implies that the interrupt line 22 is active (See +// EVENT:CPUIRQSEL22.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 + +// Field: [21] ACTIVE21 +// +// Reading 0 from this bit implies that interrupt line 21 is not active. +// Reading 1 from this bit implies that the interrupt line 21 is active (See +// EVENT:CPUIRQSEL21.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 + +// Field: [20] ACTIVE20 +// +// Reading 0 from this bit implies that interrupt line 20 is not active. +// Reading 1 from this bit implies that the interrupt line 20 is active (See +// EVENT:CPUIRQSEL20.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 + +// Field: [19] ACTIVE19 +// +// Reading 0 from this bit implies that interrupt line 19 is not active. +// Reading 1 from this bit implies that the interrupt line 19 is active (See +// EVENT:CPUIRQSEL19.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 + +// Field: [18] ACTIVE18 +// +// Reading 0 from this bit implies that interrupt line 18 is not active. +// Reading 1 from this bit implies that the interrupt line 18 is active (See +// EVENT:CPUIRQSEL18.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 + +// Field: [17] ACTIVE17 +// +// Reading 0 from this bit implies that interrupt line 17 is not active. +// Reading 1 from this bit implies that the interrupt line 17 is active (See +// EVENT:CPUIRQSEL17.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 + +// Field: [16] ACTIVE16 +// +// Reading 0 from this bit implies that interrupt line 16 is not active. +// Reading 1 from this bit implies that the interrupt line 16 is active (See +// EVENT:CPUIRQSEL16.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 + +// Field: [15] ACTIVE15 +// +// Reading 0 from this bit implies that interrupt line 15 is not active. +// Reading 1 from this bit implies that the interrupt line 15 is active (See +// EVENT:CPUIRQSEL15.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 + +// Field: [14] ACTIVE14 +// +// Reading 0 from this bit implies that interrupt line 14 is not active. +// Reading 1 from this bit implies that the interrupt line 14 is active (See +// EVENT:CPUIRQSEL14.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 + +// Field: [13] ACTIVE13 +// +// Reading 0 from this bit implies that interrupt line 13 is not active. +// Reading 1 from this bit implies that the interrupt line 13 is active (See +// EVENT:CPUIRQSEL13.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 + +// Field: [12] ACTIVE12 +// +// Reading 0 from this bit implies that interrupt line 12 is not active. +// Reading 1 from this bit implies that the interrupt line 12 is active (See +// EVENT:CPUIRQSEL12.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 + +// Field: [11] ACTIVE11 +// +// Reading 0 from this bit implies that interrupt line 11 is not active. +// Reading 1 from this bit implies that the interrupt line 11 is active (See +// EVENT:CPUIRQSEL11.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 + +// Field: [10] ACTIVE10 +// +// Reading 0 from this bit implies that interrupt line 10 is not active. +// Reading 1 from this bit implies that the interrupt line 10 is active (See +// EVENT:CPUIRQSEL10.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 + +// Field: [9] ACTIVE9 +// +// Reading 0 from this bit implies that interrupt line 9 is not active. Reading +// 1 from this bit implies that the interrupt line 9 is active (See +// EVENT:CPUIRQSEL9.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 + +// Field: [8] ACTIVE8 +// +// Reading 0 from this bit implies that interrupt line 8 is not active. Reading +// 1 from this bit implies that the interrupt line 8 is active (See +// EVENT:CPUIRQSEL8.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 + +// Field: [7] ACTIVE7 +// +// Reading 0 from this bit implies that interrupt line 7 is not active. Reading +// 1 from this bit implies that the interrupt line 7 is active (See +// EVENT:CPUIRQSEL7.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 + +// Field: [6] ACTIVE6 +// +// Reading 0 from this bit implies that interrupt line 6 is not active. Reading +// 1 from this bit implies that the interrupt line 6 is active (See +// EVENT:CPUIRQSEL6.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 + +// Field: [5] ACTIVE5 +// +// Reading 0 from this bit implies that interrupt line 5 is not active. Reading +// 1 from this bit implies that the interrupt line 5 is active (See +// EVENT:CPUIRQSEL5.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 + +// Field: [4] ACTIVE4 +// +// Reading 0 from this bit implies that interrupt line 4 is not active. Reading +// 1 from this bit implies that the interrupt line 4 is active (See +// EVENT:CPUIRQSEL4.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 + +// Field: [3] ACTIVE3 +// +// Reading 0 from this bit implies that interrupt line 3 is not active. Reading +// 1 from this bit implies that the interrupt line 3 is active (See +// EVENT:CPUIRQSEL3.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 + +// Field: [2] ACTIVE2 +// +// Reading 0 from this bit implies that interrupt line 2 is not active. Reading +// 1 from this bit implies that the interrupt line 2 is active (See +// EVENT:CPUIRQSEL2.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 + +// Field: [1] ACTIVE1 +// +// Reading 0 from this bit implies that interrupt line 1 is not active. Reading +// 1 from this bit implies that the interrupt line 1 is active (See +// EVENT:CPUIRQSEL1.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 + +// Field: [0] ACTIVE0 +// +// Reading 0 from this bit implies that interrupt line 0 is not active. Reading +// 1 from this bit implies that the interrupt line 0 is active (See +// EVENT:CPUIRQSEL0.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IABR1 +// +//***************************************************************************** +// Field: [5] ACTIVE37 +// +// Reading 0 from this bit implies that interrupt line 37 is not active. +// Reading 1 from this bit implies that the interrupt line 37 is active (See +// EVENT:CPUIRQSEL37.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE37 0x00000020 +#define CPU_SCS_NVIC_IABR1_ACTIVE37_BITN 5 +#define CPU_SCS_NVIC_IABR1_ACTIVE37_M 0x00000020 +#define CPU_SCS_NVIC_IABR1_ACTIVE37_S 5 + +// Field: [4] ACTIVE36 +// +// Reading 0 from this bit implies that interrupt line 36 is not active. +// Reading 1 from this bit implies that the interrupt line 36 is active (See +// EVENT:CPUIRQSEL36.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE36 0x00000010 +#define CPU_SCS_NVIC_IABR1_ACTIVE36_BITN 4 +#define CPU_SCS_NVIC_IABR1_ACTIVE36_M 0x00000010 +#define CPU_SCS_NVIC_IABR1_ACTIVE36_S 4 + +// Field: [3] ACTIVE35 +// +// Reading 0 from this bit implies that interrupt line 35 is not active. +// Reading 1 from this bit implies that the interrupt line 35 is active (See +// EVENT:CPUIRQSEL35.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE35 0x00000008 +#define CPU_SCS_NVIC_IABR1_ACTIVE35_BITN 3 +#define CPU_SCS_NVIC_IABR1_ACTIVE35_M 0x00000008 +#define CPU_SCS_NVIC_IABR1_ACTIVE35_S 3 + +// Field: [2] ACTIVE34 +// +// Reading 0 from this bit implies that interrupt line 34 is not active. +// Reading 1 from this bit implies that the interrupt line 34 is active (See +// EVENT:CPUIRQSEL34.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE34 0x00000004 +#define CPU_SCS_NVIC_IABR1_ACTIVE34_BITN 2 +#define CPU_SCS_NVIC_IABR1_ACTIVE34_M 0x00000004 +#define CPU_SCS_NVIC_IABR1_ACTIVE34_S 2 + +// Field: [1] ACTIVE33 +// +// Reading 0 from this bit implies that interrupt line 33 is not active. +// Reading 1 from this bit implies that the interrupt line 33 is active (See +// EVENT:CPUIRQSEL33.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 + +// Field: [0] ACTIVE32 +// +// Reading 0 from this bit implies that interrupt line 32 is not active. +// Reading 1 from this bit implies that the interrupt line 32 is active (See +// EVENT:CPUIRQSEL32.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR0 +// +//***************************************************************************** +// Field: [31:24] PRI_3 +// +// Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 +#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 + +// Field: [23:16] PRI_2 +// +// Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 + +// Field: [15:8] PRI_1 +// +// Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 + +// Field: [7:0] PRI_0 +// +// Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF +#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR1 +// +//***************************************************************************** +// Field: [31:24] PRI_7 +// +// Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 +#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 + +// Field: [23:16] PRI_6 +// +// Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 + +// Field: [15:8] PRI_5 +// +// Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 + +// Field: [7:0] PRI_4 +// +// Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF +#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR2 +// +//***************************************************************************** +// Field: [31:24] PRI_11 +// +// Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 + +// Field: [23:16] PRI_10 +// +// Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 + +// Field: [15:8] PRI_9 +// +// Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 + +// Field: [7:0] PRI_8 +// +// Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF +#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR3 +// +//***************************************************************************** +// Field: [31:24] PRI_15 +// +// Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 + +// Field: [23:16] PRI_14 +// +// Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 + +// Field: [15:8] PRI_13 +// +// Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 + +// Field: [7:0] PRI_12 +// +// Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF +#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR4 +// +//***************************************************************************** +// Field: [31:24] PRI_19 +// +// Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 +#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 + +// Field: [23:16] PRI_18 +// +// Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 + +// Field: [15:8] PRI_17 +// +// Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 + +// Field: [7:0] PRI_16 +// +// Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF +#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR5 +// +//***************************************************************************** +// Field: [31:24] PRI_23 +// +// Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 +#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 + +// Field: [23:16] PRI_22 +// +// Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 + +// Field: [15:8] PRI_21 +// +// Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 + +// Field: [7:0] PRI_20 +// +// Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF +#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR6 +// +//***************************************************************************** +// Field: [31:24] PRI_27 +// +// Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 +#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 + +// Field: [23:16] PRI_26 +// +// Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 + +// Field: [15:8] PRI_25 +// +// Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 + +// Field: [7:0] PRI_24 +// +// Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF +#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR7 +// +//***************************************************************************** +// Field: [31:24] PRI_31 +// +// Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 +#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 + +// Field: [23:16] PRI_30 +// +// Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 + +// Field: [15:8] PRI_29 +// +// Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 + +// Field: [7:0] PRI_28 +// +// Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF +#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR8 +// +//***************************************************************************** +// Field: [31:24] PRI_35 +// +// Priority of interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_35_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_35_M 0xFF000000 +#define CPU_SCS_NVIC_IPR8_PRI_35_S 24 + +// Field: [23:16] PRI_34 +// +// Priority of interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_34_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_34_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR8_PRI_34_S 16 + +// Field: [15:8] PRI_33 +// +// Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 + +// Field: [7:0] PRI_32 +// +// Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF +#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR9 +// +//***************************************************************************** +// Field: [15:8] PRI_37 +// +// Priority of interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). +#define CPU_SCS_NVIC_IPR9_PRI_37_W 8 +#define CPU_SCS_NVIC_IPR9_PRI_37_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR9_PRI_37_S 8 + +// Field: [7:0] PRI_36 +// +// Priority of interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). +#define CPU_SCS_NVIC_IPR9_PRI_36_W 8 +#define CPU_SCS_NVIC_IPR9_PRI_36_M 0x000000FF +#define CPU_SCS_NVIC_IPR9_PRI_36_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CPUID +// +//***************************************************************************** +// Field: [31:24] IMPLEMENTER +// +// Implementor code. +#define CPU_SCS_CPUID_IMPLEMENTER_W 8 +#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 +#define CPU_SCS_CPUID_IMPLEMENTER_S 24 + +// Field: [23:20] VARIANT +// +// Implementation defined variant number. +#define CPU_SCS_CPUID_VARIANT_W 4 +#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 +#define CPU_SCS_CPUID_VARIANT_S 20 + +// Field: [19:16] CONSTANT +// +// Reads as 0xF +#define CPU_SCS_CPUID_CONSTANT_W 4 +#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 +#define CPU_SCS_CPUID_CONSTANT_S 16 + +// Field: [15:4] PARTNO +// +// Number of processor within family. +#define CPU_SCS_CPUID_PARTNO_W 12 +#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 +#define CPU_SCS_CPUID_PARTNO_S 4 + +// Field: [3:0] REVISION +// +// Implementation defined revision number. +#define CPU_SCS_CPUID_REVISION_W 4 +#define CPU_SCS_CPUID_REVISION_M 0x0000000F +#define CPU_SCS_CPUID_REVISION_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ICSR +// +//***************************************************************************** +// Field: [31] NMIPENDSET +// +// Set pending NMI bit. Setting this bit pends and activates an NMI. Because +// NMI is the highest-priority interrupt, it takes effect as soon as it +// registers. +// +// 0: No action +// 1: Set pending NMI +#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 +#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_S 31 + +// Field: [28] PENDSVSET +// +// Set pending pendSV bit. +// +// 0: No action +// 1: Set pending PendSV +#define CPU_SCS_ICSR_PENDSVSET 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_BITN 28 +#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_S 28 + +// Field: [27] PENDSVCLR +// +// Clear pending pendSV bit +// +// 0: No action +// 1: Clear pending pendSV +#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 +#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_S 27 + +// Field: [26] PENDSTSET +// +// Set a pending SysTick bit. +// +// 0: No action +// 1: Set pending SysTick +#define CPU_SCS_ICSR_PENDSTSET 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_BITN 26 +#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_S 26 + +// Field: [25] PENDSTCLR +// +// Clear pending SysTick bit +// +// 0: No action +// 1: Clear pending SysTick +#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 +#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_S 25 + +// Field: [23] ISRPREEMPT +// +// This field can only be used at debug time. It indicates that a pending +// interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, +// the interrupt is serviced. +// +// 0: A pending exception is not serviced. +// 1: A pending exception is serviced on exit from the debug halt state +#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 +#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_S 23 + +// Field: [22] ISRPENDING +// +// Interrupt pending flag. Excludes NMI and faults. +// +// 0x0: Interrupt not pending +// 0x1: Interrupt pending +#define CPU_SCS_ICSR_ISRPENDING 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_BITN 22 +#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_S 22 + +// Field: [17:12] VECTPENDING +// +// Pending ISR number field. This field contains the interrupt number of the +// highest priority pending ISR. +#define CPU_SCS_ICSR_VECTPENDING_W 6 +#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 +#define CPU_SCS_ICSR_VECTPENDING_S 12 + +// Field: [11] RETTOBASE +// +// Indicates whether there are preempted active exceptions: +// +// 0: There are preempted active exceptions to execute +// 1: There are no active exceptions, or the currently-executing exception is +// the only active exception. +#define CPU_SCS_ICSR_RETTOBASE 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_BITN 11 +#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_S 11 + +// Field: [8:0] VECTACTIVE +// +// Active ISR number field. Reset clears this field. +#define CPU_SCS_ICSR_VECTACTIVE_W 9 +#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF +#define CPU_SCS_ICSR_VECTACTIVE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_VTOR +// +//***************************************************************************** +// Field: [29:7] TBLOFF +// +// Bits 29 down to 7 of the vector table base offset. +#define CPU_SCS_VTOR_TBLOFF_W 23 +#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 +#define CPU_SCS_VTOR_TBLOFF_S 7 + +//***************************************************************************** +// +// Register: CPU_SCS_O_AIRCR +// +//***************************************************************************** +// Field: [31:16] VECTKEY +// +// Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. +// Otherwise the write value is ignored. Read always returns 0xFA05. +#define CPU_SCS_AIRCR_VECTKEY_W 16 +#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 +#define CPU_SCS_AIRCR_VECTKEY_S 16 + +// Field: [15] ENDIANESS +// +// Data endianness bit +// ENUMs: +// BIG Big endian +// LITTLE Little endian +#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 +#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_S 15 +#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 + +// Field: [10:8] PRIGROUP +// +// Interrupt priority grouping field. This field is a binary point position +// indicator for creating subpriorities for exceptions that share the same +// pre-emption level. It divides the PRI_n field in the Interrupt Priority +// Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption +// level and a subpriority level. The binary point is a left-of value. This +// means that the PRIGROUP value represents a point starting at the left of the +// Least Significant Bit (LSB). The lowest value might not be 0 depending on +// the number of bits allocated for priorities, and implementation choices. +#define CPU_SCS_AIRCR_PRIGROUP_W 3 +#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 +#define CPU_SCS_AIRCR_PRIGROUP_S 8 + +// Field: [2] SYSRESETREQ +// +// Requests a warm reset. Setting this bit does not prevent Halting Debug from +// running. +#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 +#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 + +// Field: [1] VECTCLRACTIVE +// +// Clears all active state information for active NMI, fault, and interrupts. +// It is the responsibility of the application to reinitialize the stack. This +// bit is for returning to a known state during debug. The bit self-clears. +// IPSR is not cleared by this operation. So, if used by an application, it +// must only be used at the base level of activation, or within a system +// handler whose active bit can be set. +#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 + +// Field: [0] VECTRESET +// +// System Reset bit. Resets the system, with the exception of debug components. +// This bit is reserved for debug use and can be written to 1 only when the +// core is halted. The bit self-clears. Writing this bit to 1 while core is not +// halted may result in unpredictable behavior. +#define CPU_SCS_AIRCR_VECTRESET 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_BITN 0 +#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SCR +// +//***************************************************************************** +// Field: [4] SEVONPEND +// +// Send Event on Pending bit: +// +// 0: Only enabled interrupts or events can wakeup the processor, disabled +// interrupts are excluded +// 1: Enabled events and all interrupts, including disabled interrupts, can +// wakeup the processor. +// +// When an event or interrupt enters pending state, the event signal wakes up +// the processor from WFE. If +// the processor is not waiting for an event, the event is registered and +// affects the next WFE. +// The processor also wakes up on execution of an SEV instruction. +#define CPU_SCS_SCR_SEVONPEND 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_BITN 4 +#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_S 4 + +// Field: [2] SLEEPDEEP +// +// Controls whether the processor uses sleep or deep sleep as its low power +// mode +// ENUMs: +// DEEPSLEEP Deep sleep +// SLEEP Sleep +#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 +#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_S 2 +#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 + +// Field: [1] SLEEPONEXIT +// +// Sleep on exit when returning from Handler mode to Thread mode. Enables +// interrupt driven applications to avoid returning to empty main application. +// +// 0: Do not sleep when returning to thread mode +// 1: Sleep on ISR exit +#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 +#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_S 1 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CCR +// +//***************************************************************************** +// Field: [9] STKALIGN +// +// Stack alignment bit. +// +// 0: Only 4-byte alignment is guaranteed for the SP used prior to the +// exception on exception entry. +// 1: On exception entry, the SP used prior to the exception is adjusted to be +// 8-byte aligned and the context to restore it is saved. The SP is restored on +// the associated exception return. +#define CPU_SCS_CCR_STKALIGN 0x00000200 +#define CPU_SCS_CCR_STKALIGN_BITN 9 +#define CPU_SCS_CCR_STKALIGN_M 0x00000200 +#define CPU_SCS_CCR_STKALIGN_S 9 + +// Field: [8] BFHFNMIGN +// +// Enables handlers with priority -1 or -2 to ignore data BusFaults caused by +// load and store instructions. This applies to the HardFault, NMI, and +// FAULTMASK escalated handlers: +// +// 0: Data BusFaults caused by load and store instructions cause a lock-up +// 1: Data BusFaults caused by load and store instructions are ignored. +// +// Set this bit to 1 only when the handler and its data are in absolutely safe +// memory. The normal use +// of this bit is to probe system devices and bridges to detect problems. +#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 +#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_S 8 + +// Field: [4] DIV_0_TRP +// +// Enables faulting or halting when the processor executes an SDIV or UDIV +// instruction with a divisor of 0: +// +// 0: Do not trap divide by 0. In this mode, a divide by zero returns a +// quotient of 0. +// 1: Trap divide by 0. The relevant Usage Fault Status Register bit is +// CFSR.DIVBYZERO. +#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 +#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_S 4 + +// Field: [3] UNALIGN_TRP +// +// Enables unaligned access traps: +// +// 0: Do not trap unaligned halfword and word accesses +// 1: Trap unaligned halfword and word accesses. The relevant Usage Fault +// Status Register bit is CFSR.UNALIGNED. +// +// If this bit is set to 1, an unaligned access generates a UsageFault. +// Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of +// the value in UNALIGN_TRP. +#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 +#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_S 3 + +// Field: [1] USERSETMPEND +// +// Enables unprivileged software access to STIR: +// +// 0: User code is not allowed to write to the Software Trigger Interrupt +// register (STIR). +// 1: User code can write the Software Trigger Interrupt register (STIR) to +// trigger (pend) a Main exception, which is associated with the Main stack +// pointer. +#define CPU_SCS_CCR_USERSETMPEND 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_BITN 1 +#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_S 1 + +// Field: [0] NONBASETHREDENA +// +// Indicates how the processor enters Thread mode: +// +// 0: Processor can enter Thread mode only when no exception is active. +// 1: Processor can enter Thread mode from any level using the appropriate +// return value (EXC_RETURN). +// +// Exception returns occur when one of the following instructions loads a value +// of 0xFXXXXXXX into the PC while in Handler mode: +// - POP/LDM which includes loading the PC. +// - LDR with PC as a destination. +// - BX with any register. +// The value written to the PC is intercepted and is referred to as the +// EXC_RETURN value. +#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 +#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR1 +// +//***************************************************************************** +// Field: [23:16] PRI_6 +// +// Priority of system handler 6. UsageFault +#define CPU_SCS_SHPR1_PRI_6_W 8 +#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_SHPR1_PRI_6_S 16 + +// Field: [15:8] PRI_5 +// +// Priority of system handler 5: BusFault +#define CPU_SCS_SHPR1_PRI_5_W 8 +#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_SHPR1_PRI_5_S 8 + +// Field: [7:0] PRI_4 +// +// Priority of system handler 4: MemManage +#define CPU_SCS_SHPR1_PRI_4_W 8 +#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF +#define CPU_SCS_SHPR1_PRI_4_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR2 +// +//***************************************************************************** +// Field: [31:24] PRI_11 +// +// Priority of system handler 11. SVCall +#define CPU_SCS_SHPR2_PRI_11_W 8 +#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_SHPR2_PRI_11_S 24 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR3 +// +//***************************************************************************** +// Field: [31:24] PRI_15 +// +// Priority of system handler 15. SysTick exception +#define CPU_SCS_SHPR3_PRI_15_W 8 +#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_SHPR3_PRI_15_S 24 + +// Field: [23:16] PRI_14 +// +// Priority of system handler 14. Pend SV +#define CPU_SCS_SHPR3_PRI_14_W 8 +#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_SHPR3_PRI_14_S 16 + +// Field: [7:0] PRI_12 +// +// Priority of system handler 12. Debug Monitor +#define CPU_SCS_SHPR3_PRI_12_W 8 +#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF +#define CPU_SCS_SHPR3_PRI_12_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHCSR +// +//***************************************************************************** +// Field: [18] USGFAULTENA +// +// Usage fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 +#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_S 18 +#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 + +// Field: [17] BUSFAULTENA +// +// Bus fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 + +// Field: [16] MEMFAULTENA +// +// MemManage fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 + +// Field: [15] SVCALLPENDED +// +// SVCall pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 + +// Field: [14] BUSFAULTPENDED +// +// BusFault pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [13] MEMFAULTPENDED +// +// MemManage exception pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [12] USGFAULTPENDED +// +// Usage fault pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [11] SYSTICKACT +// +// SysTick active flag. +// +// 0x0: Not active +// 0x1: Active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 +#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_S 11 +#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 + +// Field: [10] PENDSVACT +// +// PendSV active +// +// 0x0: Not active +// 0x1: Active +#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 +#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_S 10 + +// Field: [8] MONITORACT +// +// Debug monitor active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_MONITORACT 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_BITN 8 +#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_S 8 +#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 + +// Field: [7] SVCALLACT +// +// SVCall active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 +#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_S 7 +#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 + +// Field: [3] USGFAULTACT +// +// UsageFault exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 +#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_S 3 +#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 + +// Field: [1] BUSFAULTACT +// +// BusFault exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 + +// Field: [0] MEMFAULTACT +// +// MemManage exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CFSR +// +//***************************************************************************** +// Field: [25] DIVBYZERO +// +// When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is +// enabled and an SDIV or UDIV instruction is used with a divisor of 0, this +// fault occurs The instruction is executed and the return PC points to it. If +// CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. +#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 +#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_S 25 + +// Field: [24] UNALIGNED +// +// When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an +// unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD +// instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. +#define CPU_SCS_CFSR_UNALIGNED 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_BITN 24 +#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_S 24 + +// Field: [19] NOCP +// +// Attempt to use a coprocessor instruction. The processor does not support +// coprocessor instructions. +#define CPU_SCS_CFSR_NOCP 0x00080000 +#define CPU_SCS_CFSR_NOCP_BITN 19 +#define CPU_SCS_CFSR_NOCP_M 0x00080000 +#define CPU_SCS_CFSR_NOCP_S 19 + +// Field: [18] INVPC +// +// Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid +// context, invalid value. The return PC points to the instruction that tried +// to set the PC. +#define CPU_SCS_CFSR_INVPC 0x00040000 +#define CPU_SCS_CFSR_INVPC_BITN 18 +#define CPU_SCS_CFSR_INVPC_M 0x00040000 +#define CPU_SCS_CFSR_INVPC_S 18 + +// Field: [17] INVSTATE +// +// Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX +// type instruction has changed state). This includes state change after entry +// to or return from exception, as well as from inter-working instructions. +// Return PC points to faulting instruction, with the invalid state. +#define CPU_SCS_CFSR_INVSTATE 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_BITN 17 +#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_S 17 + +// Field: [16] UNDEFINSTR +// +// This bit is set when the processor attempts to execute an undefined +// instruction. This is an instruction that the processor cannot decode. The +// return PC points to the undefined instruction. +#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 +#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_S 16 + +// Field: [15] BFARVALID +// +// This bit is set if the Bus Fault Address Register (BFAR) contains a valid +// address. This is true after a bus fault where the address is known. Other +// faults can clear this bit, such as a Mem Manage fault occurring later. If a +// Bus fault occurs that is escalated to a Hard Fault because of priority, the +// Hard Fault handler must clear this bit. This prevents problems if returning +// to a stacked active Bus fault handler whose BFAR value has been overwritten. +#define CPU_SCS_CFSR_BFARVALID 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_BITN 15 +#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_S 15 + +// Field: [12] STKERR +// +// Stacking from exception has caused one or more bus faults. The SP is still +// adjusted and the values in the context area on the stack might be incorrect. +// BFAR is not written. +#define CPU_SCS_CFSR_STKERR 0x00001000 +#define CPU_SCS_CFSR_STKERR_BITN 12 +#define CPU_SCS_CFSR_STKERR_M 0x00001000 +#define CPU_SCS_CFSR_STKERR_S 12 + +// Field: [11] UNSTKERR +// +// Unstack from exception return has caused one or more bus faults. This is +// chained to the handler, so that the original return stack is still present. +// SP is not adjusted from failing return and new save is not performed. BFAR +// is not written. +#define CPU_SCS_CFSR_UNSTKERR 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_BITN 11 +#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_S 11 + +// Field: [10] IMPRECISERR +// +// Imprecise data bus error. It is a BusFault, but the Return PC is not related +// to the causing instruction. This is not a synchronous fault. So, if detected +// when the priority of the current activation is higher than the Bus Fault, it +// only pends. Bus fault activates when returning to a lower priority +// activation. If a precise fault occurs before returning to a lower priority +// exception, the handler detects both IMPRECISERR set and one of the precise +// fault status bits set at the same time. BFAR is not written. +#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 +#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_S 10 + +// Field: [9] PRECISERR +// +// Precise data bus error return. +#define CPU_SCS_CFSR_PRECISERR 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_BITN 9 +#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_S 9 + +// Field: [8] IBUSERR +// +// Instruction bus error flag. This flag is set by a prefetch error. The fault +// stops on the instruction, so if the error occurs under a branch shadow, no +// fault occurs. BFAR is not written. +#define CPU_SCS_CFSR_IBUSERR 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_BITN 8 +#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_S 8 + +// Field: [7] MMARVALID +// +// Memory Manage Address Register (MMFAR) address valid flag. A later-arriving +// fault, such as a bus fault, can clear a memory manage fault.. If a MemManage +// fault occurs that is escalated to a Hard Fault because of priority, the Hard +// Fault handler must clear this bit. This prevents problems on return to a +// stacked active MemManage handler whose MMFAR value has been overwritten. +#define CPU_SCS_CFSR_MMARVALID 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_BITN 7 +#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_S 7 + +// Field: [4] MSTKERR +// +// Stacking from exception has caused one or more access violations. The SP is +// still adjusted and the values in the context area on the stack might be +// incorrect. MMFAR is not written. +#define CPU_SCS_CFSR_MSTKERR 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_BITN 4 +#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_S 4 + +// Field: [3] MUNSTKERR +// +// Unstack from exception return has caused one or more access violations. This +// is chained to the handler, so that the original return stack is still +// present. SP is not adjusted from failing return and new save is not +// performed. MMFAR is not written. +#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 +#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_S 3 + +// Field: [1] DACCVIOL +// +// Data access violation flag. Attempting to load or store at a location that +// does not permit the operation sets this flag. The return PC points to the +// faulting instruction. This error loads MMFAR with the address of the +// attempted access. +#define CPU_SCS_CFSR_DACCVIOL 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_BITN 1 +#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_S 1 + +// Field: [0] IACCVIOL +// +// Instruction access violation flag. Attempting to fetch an instruction from a +// location that does not permit execution sets this flag. This occurs on any +// access to an XN region, even when the MPU is disabled or not present. The +// return PC points to the faulting instruction. MMFAR is not written. +#define CPU_SCS_CFSR_IACCVIOL 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_BITN 0 +#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_HFSR +// +//***************************************************************************** +// Field: [31] DEBUGEVT +// +// This bit is set if there is a fault related to debug. This is only possible +// when halting debug is not enabled. For monitor enabled debug, it only +// happens for BKPT when the current priority is higher than the monitor. When +// both halting and monitor debug are disabled, it only happens for debug +// events that are not ignored (minimally, BKPT). The Debug Fault Status +// Register is updated. +#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 +#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_S 31 + +// Field: [30] FORCED +// +// Hard Fault activated because a Configurable Fault was received and cannot +// activate because of priority or because the Configurable Fault is disabled. +// The Hard Fault handler then has to read the other fault status registers to +// determine cause. +#define CPU_SCS_HFSR_FORCED 0x40000000 +#define CPU_SCS_HFSR_FORCED_BITN 30 +#define CPU_SCS_HFSR_FORCED_M 0x40000000 +#define CPU_SCS_HFSR_FORCED_S 30 + +// Field: [1] VECTTBL +// +// This bit is set if there is a fault because of vector table read on +// exception processing (Bus Fault). This case is always a Hard Fault. The +// return PC points to the pre-empted instruction. +#define CPU_SCS_HFSR_VECTTBL 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_BITN 1 +#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_S 1 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DFSR +// +//***************************************************************************** +// Field: [4] EXTERNAL +// +// External debug request flag. The processor stops on next instruction +// boundary. +// +// 0x0: External debug request signal not asserted +// 0x1: External debug request signal asserted +#define CPU_SCS_DFSR_EXTERNAL 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_BITN 4 +#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_S 4 + +// Field: [3] VCATCH +// +// Vector catch flag. When this flag is set, a flag in one of the local fault +// status registers is also set to indicate the type of fault. +// +// 0x0: No vector catch occurred +// 0x1: Vector catch occurred +#define CPU_SCS_DFSR_VCATCH 0x00000008 +#define CPU_SCS_DFSR_VCATCH_BITN 3 +#define CPU_SCS_DFSR_VCATCH_M 0x00000008 +#define CPU_SCS_DFSR_VCATCH_S 3 + +// Field: [2] DWTTRAP +// +// Data Watchpoint and Trace (DWT) flag. The processor stops at the current +// instruction or at the next instruction. +// +// 0x0: No DWT match +// 0x1: DWT match +#define CPU_SCS_DFSR_DWTTRAP 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_BITN 2 +#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_S 2 + +// Field: [1] BKPT +// +// BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, +// and also by normal code. Return PC points to breakpoint containing +// instruction. +// +// 0x0: No BKPT instruction execution +// 0x1: BKPT instruction execution +#define CPU_SCS_DFSR_BKPT 0x00000002 +#define CPU_SCS_DFSR_BKPT_BITN 1 +#define CPU_SCS_DFSR_BKPT_M 0x00000002 +#define CPU_SCS_DFSR_BKPT_S 1 + +// Field: [0] HALTED +// +// Halt request flag. The processor is halted on the next instruction. +// +// 0x0: No halt request +// 0x1: Halt requested by NVIC, including step +#define CPU_SCS_DFSR_HALTED 0x00000001 +#define CPU_SCS_DFSR_HALTED_BITN 0 +#define CPU_SCS_DFSR_HALTED_M 0x00000001 +#define CPU_SCS_DFSR_HALTED_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MMFAR +// +//***************************************************************************** +// Field: [31:0] ADDRESS +// +// Mem Manage fault address field. +// This field is the data address of a faulted load or store attempt. When an +// unaligned access faults, the address is the actual address that faulted. +// Because an access can be split into multiple parts, each aligned, this +// address can be any offset in the range of the requested size. Flags +// CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination +// with CFSR.MMARVALIDindicate the cause of the fault. +#define CPU_SCS_MMFAR_ADDRESS_W 32 +#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_MMFAR_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_BFAR +// +//***************************************************************************** +// Field: [31:0] ADDRESS +// +// Bus fault address field. This field is the data address of a faulted load or +// store attempt. When an unaligned access faults, the address is the address +// requested by the instruction, even if that is not the address that faulted. +// Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and +// CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the +// fault. +#define CPU_SCS_BFAR_ADDRESS_W 32 +#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_BFAR_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_AFSR +// +//***************************************************************************** +// Field: [31:0] IMPDEF +// +// Implementation defined. The bits map directly onto the signal assignment to +// the auxiliary fault inputs. Tied to 0 +#define CPU_SCS_AFSR_IMPDEF_W 32 +#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF +#define CPU_SCS_AFSR_IMPDEF_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_PFR0 +// +//***************************************************************************** +// Field: [7:4] STATE1 +// +// State1 (T-bit == 1) +// +// 0x0: N/A +// 0x1: N/A +// 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit +// Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit +// instructions can be added using the appropriate instruction attribute, but +// other 32-bit basic instructions cannot.) +// 0x3: Thumb-2 encoding with all Thumb-2 basic instructions +#define CPU_SCS_ID_PFR0_STATE1_W 4 +#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 +#define CPU_SCS_ID_PFR0_STATE1_S 4 + +// Field: [3:0] STATE0 +// +// State0 (T-bit == 0) +// +// 0x0: No ARM encoding +// 0x1: N/A +#define CPU_SCS_ID_PFR0_STATE0_W 4 +#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F +#define CPU_SCS_ID_PFR0_STATE0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_PFR1 +// +//***************************************************************************** +// Field: [11:8] MICROCONTROLLER_PROGRAMMERS_MODEL +// +// Microcontroller programmer's model +// +// 0x0: Not supported +// 0x2: Two-stack support +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_DFR0 +// +//***************************************************************************** +// Field: [23:20] MICROCONTROLLER_DEBUG_MODEL +// +// Microcontroller Debug Model - memory mapped +// +// 0x0: Not supported +// 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_AFR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR2 +// +//***************************************************************************** +// Field: [24] WAIT_FOR_INTERRUPT_STALLING +// +// wait for interrupt stalling +// +// 0x0: Not supported +// 0x1: Wait for interrupt supported +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR4 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_CPACR +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_TYPE +// +//***************************************************************************** +// Field: [23:16] IREGION +// +// The processor core uses only a unified MPU, this field always reads 0x0. +#define CPU_SCS_MPU_TYPE_IREGION_W 8 +#define CPU_SCS_MPU_TYPE_IREGION_M 0x00FF0000 +#define CPU_SCS_MPU_TYPE_IREGION_S 16 + +// Field: [15:8] DREGION +// +// Number of supported MPU regions field. This field reads 0x08 indicating +// eight MPU regions. +#define CPU_SCS_MPU_TYPE_DREGION_W 8 +#define CPU_SCS_MPU_TYPE_DREGION_M 0x0000FF00 +#define CPU_SCS_MPU_TYPE_DREGION_S 8 + +// Field: [0] SEPARATE +// +// The processor core uses only a unified MPU, thus this field is always 0. +#define CPU_SCS_MPU_TYPE_SEPARATE 0x00000001 +#define CPU_SCS_MPU_TYPE_SEPARATE_BITN 0 +#define CPU_SCS_MPU_TYPE_SEPARATE_M 0x00000001 +#define CPU_SCS_MPU_TYPE_SEPARATE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_CTRL +// +//***************************************************************************** +// Field: [2] PRIVDEFENA +// +// This bit enables the default memory map for privileged access, as a +// background region, when the MPU is enabled. The background region acts as if +// it was region number 1 before any settable regions. Any region that is set +// up overlays this default map, and overrides it. If this bit is not set, the +// default memory map is disabled, and memory not covered by a region faults. +// This applies to memory type, Execute Never (XN), cache and shareable rules. +// However, this only applies to privileged mode (fetch and data access). User +// mode code faults unless a region has been set up for its code and data. When +// the MPU is disabled, the default map acts on both privileged and user mode +// code. XN and SO rules always apply to the system partition whether this +// enable is set or not. If the MPU is disabled, this bit is ignored. +#define CPU_SCS_MPU_CTRL_PRIVDEFENA 0x00000004 +#define CPU_SCS_MPU_CTRL_PRIVDEFENA_BITN 2 +#define CPU_SCS_MPU_CTRL_PRIVDEFENA_M 0x00000004 +#define CPU_SCS_MPU_CTRL_PRIVDEFENA_S 2 + +// Field: [1] HFNMIENA +// +// This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated +// handlers. If this bit and ENABLE are set, the MPU is enabled when in these +// handlers. If this bit is not set, the MPU is disabled when in these +// handlers, regardless of the value of ENABLE bit. If this bit is set and +// ENABLE is not set, behavior is unpredictable. +#define CPU_SCS_MPU_CTRL_HFNMIENA 0x00000002 +#define CPU_SCS_MPU_CTRL_HFNMIENA_BITN 1 +#define CPU_SCS_MPU_CTRL_HFNMIENA_M 0x00000002 +#define CPU_SCS_MPU_CTRL_HFNMIENA_S 1 + +// Field: [0] ENABLE +// +// Enable MPU +// +// 0: MPU disabled +// 1: MPU enabled +#define CPU_SCS_MPU_CTRL_ENABLE 0x00000001 +#define CPU_SCS_MPU_CTRL_ENABLE_BITN 0 +#define CPU_SCS_MPU_CTRL_ENABLE_M 0x00000001 +#define CPU_SCS_MPU_CTRL_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RNR +// +//***************************************************************************** +// Field: [7:0] REGION +// +// Region select field. +// This field selects the region to operate on when using the MPU_RASR and +// MPU_RBAR. It must be written first except when the address MPU_RBAR.VALID +// and MPU_RBAR.REGION fields are written, which overwrites this. +#define CPU_SCS_MPU_RNR_REGION_W 8 +#define CPU_SCS_MPU_RNR_REGION_M 0x000000FF +#define CPU_SCS_MPU_RNR_REGION_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RBAR +// +//***************************************************************************** +// Field: [31:5] ADDR +// +// Region base address field. +// The position of the LSB depends on the region size, so that the base address +// is aligned according to an even multiple of size. The power of 2 size +// specified by the SZENABLE field of the MPU Region Attribute and Size +// Register defines how many bits of base address are used. +#define CPU_SCS_MPU_RBAR_ADDR_W 27 +#define CPU_SCS_MPU_RBAR_ADDR_M 0xFFFFFFE0 +#define CPU_SCS_MPU_RBAR_ADDR_S 5 + +// Field: [4] VALID +// +// MPU region number valid: +// 0: MPU_RNR remains unchanged and is interpreted. +// 1: MPU_RNR is overwritten by REGION. +#define CPU_SCS_MPU_RBAR_VALID 0x00000010 +#define CPU_SCS_MPU_RBAR_VALID_BITN 4 +#define CPU_SCS_MPU_RBAR_VALID_M 0x00000010 +#define CPU_SCS_MPU_RBAR_VALID_S 4 + +// Field: [3:0] REGION +// +// MPU region override field +#define CPU_SCS_MPU_RBAR_REGION_W 4 +#define CPU_SCS_MPU_RBAR_REGION_M 0x0000000F +#define CPU_SCS_MPU_RBAR_REGION_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RASR +// +//***************************************************************************** +// Field: [28] XN +// +// Instruction access disable: +// 0: Enable instruction fetches +// 1: Disable instruction fetches +#define CPU_SCS_MPU_RASR_XN 0x10000000 +#define CPU_SCS_MPU_RASR_XN_BITN 28 +#define CPU_SCS_MPU_RASR_XN_M 0x10000000 +#define CPU_SCS_MPU_RASR_XN_S 28 + +// Field: [26:24] AP +// +// Data access permission: +// 0x0: Priviliged permissions: No access. User permissions: No access. +// 0x1: Priviliged permissions: Read-write. User permissions: No access. +// 0x2: Priviliged permissions: Read-write. User permissions: Read-only. +// 0x3: Priviliged permissions: Read-write. User permissions: Read-write. +// 0x4: Reserved +// 0x5: Priviliged permissions: Read-only. User permissions: No access. +// 0x6: Priviliged permissions: Read-only. User permissions: Read-only. +// 0x7: Priviliged permissions: Read-only. User permissions: Read-only. +#define CPU_SCS_MPU_RASR_AP_W 3 +#define CPU_SCS_MPU_RASR_AP_M 0x07000000 +#define CPU_SCS_MPU_RASR_AP_S 24 + +// Field: [21:19] TEX +// +// Type extension +#define CPU_SCS_MPU_RASR_TEX_W 3 +#define CPU_SCS_MPU_RASR_TEX_M 0x00380000 +#define CPU_SCS_MPU_RASR_TEX_S 19 + +// Field: [18] S +// +// Shareable bit: +// 0: Not shareable +// 1: Shareable +#define CPU_SCS_MPU_RASR_S 0x00040000 +#define CPU_SCS_MPU_RASR_S_BITN 18 +#define CPU_SCS_MPU_RASR_S_M 0x00040000 +#define CPU_SCS_MPU_RASR_S_S 18 + +// Field: [17] C +// +// Cacheable bit: +// 0: Not cacheable +// 1: Cacheable +#define CPU_SCS_MPU_RASR_C 0x00020000 +#define CPU_SCS_MPU_RASR_C_BITN 17 +#define CPU_SCS_MPU_RASR_C_M 0x00020000 +#define CPU_SCS_MPU_RASR_C_S 17 + +// Field: [16] B +// +// Bufferable bit: +// 0: Not bufferable +// 1: Bufferable +#define CPU_SCS_MPU_RASR_B 0x00010000 +#define CPU_SCS_MPU_RASR_B_BITN 16 +#define CPU_SCS_MPU_RASR_B_M 0x00010000 +#define CPU_SCS_MPU_RASR_B_S 16 + +// Field: [15:8] SRD +// +// Sub-Region Disable field: +// Setting a bit in this field disables the corresponding sub-region. Regions +// are split into eight equal-sized sub-regions. Sub-regions are not supported +// for region sizes of 128 bytes and less. +#define CPU_SCS_MPU_RASR_SRD_W 8 +#define CPU_SCS_MPU_RASR_SRD_M 0x0000FF00 +#define CPU_SCS_MPU_RASR_SRD_S 8 + +// Field: [5:1] SIZE +// +// MPU Protection Region Size Field: +// 0x04: 32B +// 0x05: 64B +// 0x06: 128B +// 0x07: 256B +// 0x08: 512B +// 0x09: 1KB +// 0x0A: 2KB +// 0x0B: 4KB +// 0x0C: 8KB +// 0x0D: 16KB +// 0x0E: 32KB +// 0x0F: 64KB +// 0x10: 128KB +// 0x11: 256KB +// 0x12: 512KB +// 0x13: 1MB +// 0x14: 2MB +// 0x15: 4MB +// 0x16: 8MB +// 0x17: 16MB +// 0x18: 32MB +// 0x19: 64MB +// 0x1A: 128MB +// 0x1B: 256MB +// 0x1C: 512MB +// 0x1D: 1GB +// 0x1E: 2GB +// 0x1F: 4GB +#define CPU_SCS_MPU_RASR_SIZE_W 5 +#define CPU_SCS_MPU_RASR_SIZE_M 0x0000003E +#define CPU_SCS_MPU_RASR_SIZE_S 1 + +// Field: [0] ENABLE +// +// Region enable bit: +// 0: Disable region +// 1: Enable region +#define CPU_SCS_MPU_RASR_ENABLE 0x00000001 +#define CPU_SCS_MPU_RASR_ENABLE_BITN 0 +#define CPU_SCS_MPU_RASR_ENABLE_M 0x00000001 +#define CPU_SCS_MPU_RASR_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RBAR_A1 +// +//***************************************************************************** +// Field: [31:0] MPU_RBAR_A1 +// +// Alias for MPU_RBAR +#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_W 32 +#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_M 0xFFFFFFFF +#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RASR_A1 +// +//***************************************************************************** +// Field: [31:0] MPU_RASR_A1 +// +// Alias for MPU_RASR +#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_W 32 +#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_M 0xFFFFFFFF +#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RBAR_A2 +// +//***************************************************************************** +// Field: [31:0] MPU_RBAR_A2 +// +// Alias for MPU_RBAR +#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_W 32 +#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_M 0xFFFFFFFF +#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RASR_A2 +// +//***************************************************************************** +// Field: [31:0] MPU_RASR_A2 +// +// Alias for MPU_RASR +#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_W 32 +#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_M 0xFFFFFFFF +#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RBAR_A3 +// +//***************************************************************************** +// Field: [31:0] MPU_RBAR_A3 +// +// Alias for MPU_RBAR +#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_W 32 +#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_M 0xFFFFFFFF +#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RASR_A3 +// +//***************************************************************************** +// Field: [31:0] MPU_RASR_A3 +// +// Alias for MPU_RASR +#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_W 32 +#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_M 0xFFFFFFFF +#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DHCSR +// +//***************************************************************************** +// Field: [25] S_RESET_ST +// +// Indicates that the core has been reset, or is now being reset, since the +// last time this bit was read. This a sticky bit that clears on read. So, +// reading twice and getting 1 then 0 means it was reset in the past. Reading +// twice and getting 1 both times means that it is being reset now (held in +// reset still). +// When writing to this register, 0 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 +#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_S 25 + +// Field: [24] S_RETIRE_ST +// +// Indicates that an instruction has completed since last read. This is a +// sticky bit that clears on read. This determines if the core is stalled on a +// load/store or fetch. +// When writing to this register, 0 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 +#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 + +// Field: [19] S_LOCKUP +// +// Reads as one if the core is running (not halted) and a lockup condition is +// present. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 +#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_S 19 + +// Field: [18] S_SLEEP +// +// Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must +// use C_HALT to gain control or wait for interrupt to wake-up. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 +#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_S 18 + +// Field: [17] S_HALT +// +// The core is in debug state when this bit is set. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_HALT 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_BITN 17 +#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_S 17 + +// Field: [16] S_REGRDY +// +// Register Read/Write on the Debug Core Register Selector register is +// available. Last transfer is complete. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 +#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_S 16 + +// Field: [5] C_SNAPSTALL +// +// If the core is stalled on a load/store operation the stall ceases and the +// instruction is forced to complete. This enables Halting debug to gain +// control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. +// The core reads S_RETIRE_ST as 0. This indicates that no instruction has +// advanced. This prevents misuse. The bus state is Unpredictable when this is +// used. S_RETIRE_ST can detect core stalls on load/store operations. +#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 +#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 + +// Field: [3] C_MASKINTS +// +// Mask interrupts when stepping or running in halted debug. This masking does +// not affect NMI, fault exceptions and SVC caused by execution of the +// instructions. This bit must only be modified when the processor is halted +// (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released +// (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must +// be separate). Modifying C_MASKINTS while the system is running with halting +// debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable +// behavior. +#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 +#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_S 3 + +// Field: [2] C_STEP +// +// Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. +// Must only be modified when the processor is halted (S_HALT == 1). +// Modifying C_STEP while the system is running with halting debug support +// enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. +#define CPU_SCS_DHCSR_C_STEP 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_BITN 2 +#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_S 2 + +// Field: [1] C_HALT +// +// Halts the core. This bit is set automatically when the core Halts. For +// example Breakpoint. This bit clears on core reset. +#define CPU_SCS_DHCSR_C_HALT 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_BITN 1 +#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_S 1 + +// Field: [0] C_DEBUGEN +// +// Enables debug. This can only be written by AHB-AP and not by the core. It is +// ignored when written by the core, which cannot set or clear it. The core +// must write a 1 to it when writing C_HALT to halt itself. +// The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when +// C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will +// be unknown to software when C_DEBUGEN = 0. +#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 +#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DCRSR +// +//***************************************************************************** +// Field: [16] REGWNR +// +// 1: Write +// 0: Read +#define CPU_SCS_DCRSR_REGWNR 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_BITN 16 +#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_S 16 + +// Field: [4:0] REGSEL +// +// Register select +// +// 0x00: R0 +// 0x01: R1 +// 0x02: R2 +// 0x03: R3 +// 0x04: R4 +// 0x05: R5 +// 0x06: R6 +// 0x07: R7 +// 0x08: R8 +// 0x09: R9 +// 0x0A: R10 +// 0x0B: R11 +// 0x0C: R12 +// 0x0D: Current SP +// 0x0E: LR +// 0x0F: DebugReturnAddress +// 0x10: XPSR/flags, execution state information, and exception number +// 0x11: MSP (Main SP) +// 0x12: PSP (Process SP) +// 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK +#define CPU_SCS_DCRSR_REGSEL_W 5 +#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F +#define CPU_SCS_DCRSR_REGSEL_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DCRDR +// +//***************************************************************************** +// Field: [31:0] DCRDR +// +// This register holds data for reading and writing registers to and from the +// processor. This is the data value written to the register selected by DCRSR. +// When the processor receives a request from DCRSR, this register is read or +// written by the processor using a normal load-store unit operation. If core +// register transfers are not being performed, software-based debug monitors +// can use this register for communication in non-halting debug. This enables +// flags and bits to acknowledge state and indicate if commands have been +// accepted to, replied to, or accepted and replied to. +#define CPU_SCS_DCRDR_DCRDR_W 32 +#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF +#define CPU_SCS_DCRDR_DCRDR_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DEMCR +// +//***************************************************************************** +// Field: [24] TRCENA +// +// This bit must be set to 1 to enable use of the trace and debug blocks: DWT, +// ITM, ETM and TPIU. This enables control of power usage unless tracing is +// required. The application can enable this, for ITM use, or use by a +// debugger. +#define CPU_SCS_DEMCR_TRCENA 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_BITN 24 +#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_S 24 + +// Field: [19] MON_REQ +// +// This enables the monitor to identify how it wakes up. This bit clears on a +// Core Reset. +// +// 0x0: Woken up by debug exception. +// 0x1: Woken up by MON_PEND +#define CPU_SCS_DEMCR_MON_REQ 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_BITN 19 +#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_S 19 + +// Field: [18] MON_STEP +// +// When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. +// This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped +// according to the priority of the monitor and settings of PRIMASK, FAULTMASK, +// or BASEPRI. +#define CPU_SCS_DEMCR_MON_STEP 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_BITN 18 +#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_S 18 + +// Field: [17] MON_PEND +// +// Pend the monitor to activate when priority permits. This can wake up the +// monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for +// Monitor debug. This register does not reset on a system reset. It is only +// reset by a power-on reset. Software in the reset handler or later, or by the +// DAP must enable the debug monitor. +#define CPU_SCS_DEMCR_MON_PEND 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_BITN 17 +#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_S 17 + +// Field: [16] MON_EN +// +// Enable the debug monitor. +// When enabled, the System handler priority register controls its priority +// level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN +// overrides this bit. Vector catching is semi-synchronous. When a matching +// event is seen, a Halt is requested. Because the processor can only halt on +// an instruction boundary, it must wait until the next instruction boundary. +// As a result, it stops on the first instruction of the exception handler. +// However, two special cases exist when a vector catch has triggered: 1. If a +// fault is taken during vectoring, vector read or stack push error, the halt +// occurs on the corresponding fault handler, for the vector error or stack +// push. 2. If a late arriving interrupt comes in during vectoring, it is not +// taken. That is, an implementation that supports the late arrival +// optimization must suppress it in this case. +#define CPU_SCS_DEMCR_MON_EN 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_BITN 16 +#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_S 16 + +// Field: [10] VC_HARDERR +// +// Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 +#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_S 10 + +// Field: [9] VC_INTERR +// +// Debug trap on a fault occurring during an exception entry or return +// sequence. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 +#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_S 9 + +// Field: [8] VC_BUSERR +// +// Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 +#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_S 8 + +// Field: [7] VC_STATERR +// +// Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is +// cleared. +#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 +#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_S 7 + +// Field: [6] VC_CHKERR +// +// Debug trap on Usage Fault enabled checking errors. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 +#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_S 6 + +// Field: [5] VC_NOCPERR +// +// Debug trap on a UsageFault access to a Coprocessor. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 +#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 + +// Field: [4] VC_MMERR +// +// Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is +// cleared. +#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 +#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_S 4 + +// Field: [0] VC_CORERESET +// +// Reset Vector Catch. Halt running system if Core reset occurs. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 +#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STIR +// +//***************************************************************************** +// Field: [8:0] INTID +// +// Interrupt ID field. Writing a value to this bit-field is the same as +// manually pending an interrupt by setting the corresponding interrupt bit in +// an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. +#define CPU_SCS_STIR_INTID_W 9 +#define CPU_SCS_STIR_INTID_M 0x000001FF +#define CPU_SCS_STIR_INTID_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_FPCCR +// +//***************************************************************************** +// Field: [31] ASPEN +// +// Automatic State Preservation enable. +// When this bit is set is will cause bit [2] of the Special CONTROL register +// to be set (FPCA) on execution of a floating point instruction which results +// in the floating point state automatically being preserved on exception +// entry. +#define CPU_SCS_FPCCR_ASPEN 0x80000000 +#define CPU_SCS_FPCCR_ASPEN_BITN 31 +#define CPU_SCS_FPCCR_ASPEN_M 0x80000000 +#define CPU_SCS_FPCCR_ASPEN_S 31 + +// Field: [30] LSPEN +// +// Lazy State Preservation enable. +// Lazy state preservation is when the processor performs a context save, space +// on the stack is reserved for the floating point state but it is not stacked +// until the new context performs a floating point operation. +// 0: Disable automatic lazy state preservation for floating-point context. +// 1: Enable automatic lazy state preservation for floating-point context. +#define CPU_SCS_FPCCR_LSPEN 0x40000000 +#define CPU_SCS_FPCCR_LSPEN_BITN 30 +#define CPU_SCS_FPCCR_LSPEN_M 0x40000000 +#define CPU_SCS_FPCCR_LSPEN_S 30 + +// Field: [8] MONRDY +// +// Indicates whether the the software executing when the processor allocated +// the FP stack frame was able to set the DebugMonitor exception to pending. +// 0: DebugMonitor is disabled or priority did not permit setting +// DEMCR.MON_PEND when the floating-point stack frame was allocated. +// 1: DebugMonitor is enabled and priority permits setting DEMCR.MON_PEND when +// the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_MONRDY 0x00000100 +#define CPU_SCS_FPCCR_MONRDY_BITN 8 +#define CPU_SCS_FPCCR_MONRDY_M 0x00000100 +#define CPU_SCS_FPCCR_MONRDY_S 8 + +// Field: [6] BFRDY +// +// Indicates whether the software executing when the processor allocated the FP +// stack frame was able to set the BusFault exception to pending. +// 0: BusFault is disabled or priority did not permit setting the BusFault +// handler to the pending state when the floating-point stack frame was +// allocated. +// 1: BusFault is enabled and priority permitted setting the BusFault handler +// to the pending state when the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_BFRDY 0x00000040 +#define CPU_SCS_FPCCR_BFRDY_BITN 6 +#define CPU_SCS_FPCCR_BFRDY_M 0x00000040 +#define CPU_SCS_FPCCR_BFRDY_S 6 + +// Field: [5] MMRDY +// +// Indicates whether the software executing when the processor allocated the FP +// stack frame was able to set the MemManage exception to pending. +// 0: MemManage is disabled or priority did not permit setting the MemManage +// handler to the pending state when the floating-point stack frame was +// allocated. +// 1: MemManage is enabled and priority permitted setting the MemManage handler +// to the pending state when the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_MMRDY 0x00000020 +#define CPU_SCS_FPCCR_MMRDY_BITN 5 +#define CPU_SCS_FPCCR_MMRDY_M 0x00000020 +#define CPU_SCS_FPCCR_MMRDY_S 5 + +// Field: [4] HFRDY +// +// Indicates whether the software executing when the processor allocated the FP +// stack frame was able to set the HardFault exception to pending. +// 0: Priority did not permit setting the HardFault handler to the pending +// state when the floating-point stack frame was allocated. +// 1: Priority permitted setting the HardFault handler to the pending state +// when the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_HFRDY 0x00000010 +#define CPU_SCS_FPCCR_HFRDY_BITN 4 +#define CPU_SCS_FPCCR_HFRDY_M 0x00000010 +#define CPU_SCS_FPCCR_HFRDY_S 4 + +// Field: [3] THREAD +// +// Indicates the processor mode was Thread when it allocated the FP stack +// frame. +// 0: Mode was not Thread Mode when the floating-point stack frame was +// allocated. +// 1: Mode was Thread Mode when the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_THREAD 0x00000008 +#define CPU_SCS_FPCCR_THREAD_BITN 3 +#define CPU_SCS_FPCCR_THREAD_M 0x00000008 +#define CPU_SCS_FPCCR_THREAD_S 3 + +// Field: [1] USER +// +// Indicates the privilege level of the software executing was User +// (Unpriviledged) when the processor allocated the FP stack frame: +// 0: Privilege level was not user when the floating-point stack frame was +// allocated. +// 1: Privilege level was user when the floating-point stack frame was +// allocated. +#define CPU_SCS_FPCCR_USER 0x00000002 +#define CPU_SCS_FPCCR_USER_BITN 1 +#define CPU_SCS_FPCCR_USER_M 0x00000002 +#define CPU_SCS_FPCCR_USER_S 1 + +// Field: [0] LSPACT +// +// Indicates whether Lazy preservation of the FP state is active: +// 0: Lazy state preservation is not active. +// 1: Lazy state preservation is active. floating-point stack frame has been +// allocated but saving state to it has been deferred. +#define CPU_SCS_FPCCR_LSPACT 0x00000001 +#define CPU_SCS_FPCCR_LSPACT_BITN 0 +#define CPU_SCS_FPCCR_LSPACT_M 0x00000001 +#define CPU_SCS_FPCCR_LSPACT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_FPCAR +// +//***************************************************************************** +// Field: [31:2] ADDRESS +// +// Holds the (double-word-aligned) location of the unpopulated floating-point +// register space allocated on an exception stack frame. +#define CPU_SCS_FPCAR_ADDRESS_W 30 +#define CPU_SCS_FPCAR_ADDRESS_M 0xFFFFFFFC +#define CPU_SCS_FPCAR_ADDRESS_S 2 + +//***************************************************************************** +// +// Register: CPU_SCS_O_FPDSCR +// +//***************************************************************************** +// Field: [26] AHP +// +// Default value for Alternative Half Precision bit. (If this bit is set to 1 +// then Alternative half-precision format is selected). +#define CPU_SCS_FPDSCR_AHP 0x04000000 +#define CPU_SCS_FPDSCR_AHP_BITN 26 +#define CPU_SCS_FPDSCR_AHP_M 0x04000000 +#define CPU_SCS_FPDSCR_AHP_S 26 + +// Field: [25] DN +// +// Default value for Default NaN mode bit. (If this bit is set to 1 then any +// operation involving one or more NaNs returns the Default NaN). +#define CPU_SCS_FPDSCR_DN 0x02000000 +#define CPU_SCS_FPDSCR_DN_BITN 25 +#define CPU_SCS_FPDSCR_DN_M 0x02000000 +#define CPU_SCS_FPDSCR_DN_S 25 + +// Field: [24] FZ +// +// Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then +// Flush-to-zero mode is enabled). +#define CPU_SCS_FPDSCR_FZ 0x01000000 +#define CPU_SCS_FPDSCR_FZ_BITN 24 +#define CPU_SCS_FPDSCR_FZ_M 0x01000000 +#define CPU_SCS_FPDSCR_FZ_S 24 + +// Field: [23:22] RMODE +// +// Default value for Rounding Mode control field. (The encoding for this field +// is: +// 0b00 Round to Nearest (RN) mode +// 0b01 Round towards Plus Infinity (RP) mode +// 0b10 Round towards Minus Infinity (RM) mode +// 0b11 Round towards Zero (RZ) mode. +// The specified rounding mode is used by almost all floating-point +// instructions). +#define CPU_SCS_FPDSCR_RMODE_W 2 +#define CPU_SCS_FPDSCR_RMODE_M 0x00C00000 +#define CPU_SCS_FPDSCR_RMODE_S 22 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MVFR0 +// +//***************************************************************************** +// Field: [31:28] FP_ROUNDING_MODES +// +// Indicates the rounding modes supported by the FP floating-point hardware. +// The value of this field is: 0b0001 - all rounding modes supported. +#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_W 4 +#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_M 0xF0000000 +#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_S 28 + +// Field: [27:24] SHORT_VECTORS +// +// Indicates the hardware support for FP short vectors. The value of this field +// is: 0b0000 - not supported. +#define CPU_SCS_MVFR0_SHORT_VECTORS_W 4 +#define CPU_SCS_MVFR0_SHORT_VECTORS_M 0x0F000000 +#define CPU_SCS_MVFR0_SHORT_VECTORS_S 24 + +// Field: [23:20] SQUARE_ROOT +// +// Indicates the hardware support for FP square root operations. The value of +// this field is: 0b0001 - supported. +#define CPU_SCS_MVFR0_SQUARE_ROOT_W 4 +#define CPU_SCS_MVFR0_SQUARE_ROOT_M 0x00F00000 +#define CPU_SCS_MVFR0_SQUARE_ROOT_S 20 + +// Field: [19:16] DIVIDE +// +// Indicates the hardware support for FP divide operations. The value of this +// field is: 0b0001 - supported. +#define CPU_SCS_MVFR0_DIVIDE_W 4 +#define CPU_SCS_MVFR0_DIVIDE_M 0x000F0000 +#define CPU_SCS_MVFR0_DIVIDE_S 16 + +// Field: [15:12] FP_EXCEPTION_TRAPPING +// +// Indicates whether the FP hardware implementation supports exception +// trapping. The value of this field is: 0b0000 - not supported. +#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_W 4 +#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_M 0x0000F000 +#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_S 12 + +// Field: [11:8] DOUBLE_PRECISION +// +// Indicates the hardware support for FP double-precision operations. The value +// of this field is: 0b0000 - not supported. +#define CPU_SCS_MVFR0_DOUBLE_PRECISION_W 4 +#define CPU_SCS_MVFR0_DOUBLE_PRECISION_M 0x00000F00 +#define CPU_SCS_MVFR0_DOUBLE_PRECISION_S 8 + +// Field: [7:4] SINGLE_PRECISION +// +// Indicates the hardware support for FP single-precision operations. The value +// of this field is: 0b0010 - supported. +#define CPU_SCS_MVFR0_SINGLE_PRECISION_W 4 +#define CPU_SCS_MVFR0_SINGLE_PRECISION_M 0x000000F0 +#define CPU_SCS_MVFR0_SINGLE_PRECISION_S 4 + +// Field: [3:0] A_SIMD +// +// Indicates the size of the FP register bank. The value of this field is: +// 0b0001 - supported, 16 x 64-bit registers. +#define CPU_SCS_MVFR0_A_SIMD_W 4 +#define CPU_SCS_MVFR0_A_SIMD_M 0x0000000F +#define CPU_SCS_MVFR0_A_SIMD_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MVFR1 +// +//***************************************************************************** +// Field: [31:28] FP_FUSED_MAC +// +// Indicates whether the FP supports fused multiply accumulate operations. The +// value of this field is: 0b0001 - supported. +#define CPU_SCS_MVFR1_FP_FUSED_MAC_W 4 +#define CPU_SCS_MVFR1_FP_FUSED_MAC_M 0xF0000000 +#define CPU_SCS_MVFR1_FP_FUSED_MAC_S 28 + +// Field: [27:24] FP_HPFP +// +// Indicates whether the FP supports half-precision floating-point conversion +// operations. The value of this field is: 0b0001 - supported. +#define CPU_SCS_MVFR1_FP_HPFP_W 4 +#define CPU_SCS_MVFR1_FP_HPFP_M 0x0F000000 +#define CPU_SCS_MVFR1_FP_HPFP_S 24 + +// Field: [7:4] D_NAN_MODE +// +// Indicates whether the FP hardware implementation supports only the Default +// NaN mode. The value of this field is: 0b0001 - hardware supports propagation +// of NaN values. +#define CPU_SCS_MVFR1_D_NAN_MODE_W 4 +#define CPU_SCS_MVFR1_D_NAN_MODE_M 0x000000F0 +#define CPU_SCS_MVFR1_D_NAN_MODE_S 4 + +// Field: [3:0] FTZ_MODE +// +// Indicates whether the FP hardware implementation supports only the +// Flush-to-Zero mode of operation. The value of this field is: 0b0001 - +// hardware supports full denormalized number arithmetic. +#define CPU_SCS_MVFR1_FTZ_MODE_W 4 +#define CPU_SCS_MVFR1_FTZ_MODE_M 0x0000000F +#define CPU_SCS_MVFR1_FTZ_MODE_S 0 + + +#endif // __CPU_SCS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h new file mode 100644 index 0000000..e4b89d1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h @@ -0,0 +1,68 @@ +/****************************************************************************** +* Filename: hw_cpu_tiprop_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_TIPROP_H__ +#define __HW_CPU_TIPROP_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_TIPROP component +// +//***************************************************************************** +// Internal +#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8 + +//***************************************************************************** +// +// Register: CPU_TIPROP_O_TRACECLKMUX +// +//***************************************************************************** +// Field: [0] TRACECLK_N_SWV +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// TRACECLK Internal. Only to be used through TI provided API. +// SWV Internal. Only to be used through TI provided API. +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000 + + +#endif // __CPU_TIPROP__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h new file mode 100644 index 0000000..f95bb09 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h @@ -0,0 +1,347 @@ +/****************************************************************************** +* Filename: hw_cpu_tpiu_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_TPIU_H__ +#define __HW_CPU_TPIU_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_TPIU component +// +//***************************************************************************** +// Supported Sync Port Sizes +#define CPU_TPIU_O_SSPSR 0x00000000 + +// Current Sync Port Size +#define CPU_TPIU_O_CSPSR 0x00000004 + +// Async Clock Prescaler +#define CPU_TPIU_O_ACPR 0x00000010 + +// Selected Pin Protocol +#define CPU_TPIU_O_SPPR 0x000000F0 + +// Formatter and Flush Status +#define CPU_TPIU_O_FFSR 0x00000300 + +// Formatter and Flush Control +#define CPU_TPIU_O_FFCR 0x00000304 + +// Formatter Synchronization Counter +#define CPU_TPIU_O_FSCR 0x00000308 + +// Claim Tag Mask +#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 + +// Claim Tag Set +#define CPU_TPIU_O_CLAIMSET 0x00000FA0 + +// Current Claim Tag +#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 + +// Claim Tag Clear +#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 + +// Device ID +#define CPU_TPIU_O_DEVID 0x00000FC8 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_SSPSR +// +//***************************************************************************** +// Field: [3] FOUR +// +// 4-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_FOUR 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_BITN 3 +#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_S 3 + +// Field: [2] THREE +// +// 3-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_THREE 0x00000004 +#define CPU_TPIU_SSPSR_THREE_BITN 2 +#define CPU_TPIU_SSPSR_THREE_M 0x00000004 +#define CPU_TPIU_SSPSR_THREE_S 2 + +// Field: [1] TWO +// +// 2-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_TWO 0x00000002 +#define CPU_TPIU_SSPSR_TWO_BITN 1 +#define CPU_TPIU_SSPSR_TWO_M 0x00000002 +#define CPU_TPIU_SSPSR_TWO_S 1 + +// Field: [0] ONE +// +// 1-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_ONE 0x00000001 +#define CPU_TPIU_SSPSR_ONE_BITN 0 +#define CPU_TPIU_SSPSR_ONE_M 0x00000001 +#define CPU_TPIU_SSPSR_ONE_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CSPSR +// +//***************************************************************************** +// Field: [3] FOUR +// +// 4-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_FOUR 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_BITN 3 +#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_S 3 + +// Field: [2] THREE +// +// 3-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_THREE 0x00000004 +#define CPU_TPIU_CSPSR_THREE_BITN 2 +#define CPU_TPIU_CSPSR_THREE_M 0x00000004 +#define CPU_TPIU_CSPSR_THREE_S 2 + +// Field: [1] TWO +// +// 2-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_TWO 0x00000002 +#define CPU_TPIU_CSPSR_TWO_BITN 1 +#define CPU_TPIU_CSPSR_TWO_M 0x00000002 +#define CPU_TPIU_CSPSR_TWO_S 1 + +// Field: [0] ONE +// +// 1-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_ONE 0x00000001 +#define CPU_TPIU_CSPSR_ONE_BITN 0 +#define CPU_TPIU_CSPSR_ONE_M 0x00000001 +#define CPU_TPIU_CSPSR_ONE_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_ACPR +// +//***************************************************************************** +// Field: [12:0] PRESCALER +// +// Divisor for input trace clock is (PRESCALER + 1). +#define CPU_TPIU_ACPR_PRESCALER_W 13 +#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF +#define CPU_TPIU_ACPR_PRESCALER_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_SPPR +// +//***************************************************************************** +// Field: [1:0] PROTOCOL +// +// Trace output protocol +// ENUMs: +// SWO_NRZ SerialWire Output (NRZ) +// SWO_MANCHESTER SerialWire Output (Manchester). This is the reset +// value. +// TRACEPORT TracePort mode +#define CPU_TPIU_SPPR_PROTOCOL_W 2 +#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 +#define CPU_TPIU_SPPR_PROTOCOL_S 0 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 +#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FFSR +// +//***************************************************************************** +// Field: [3] FTNONSTOP +// +// 0: Formatter can be stopped +// 1: Formatter cannot be stopped +#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 +#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_S 3 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FFCR +// +//***************************************************************************** +// Field: [8] TRIGIN +// +// Indicates that triggers are inserted when a trigger pin is asserted. +#define CPU_TPIU_FFCR_TRIGIN 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_BITN 8 +#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_S 8 + +// Field: [1] ENFCONT +// +// Enable continuous formatting: +// +// 0: Continuous formatting disabled +// 1: Continuous formatting enabled +#define CPU_TPIU_FFCR_ENFCONT 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_BITN 1 +#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_S 1 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FSCR +// +//***************************************************************************** +// Field: [31:0] FSCR +// +// The global synchronization trigger is generated by the Program Counter (PC) +// Sampler block. This means that there is no synchronization counter in the +// TPIU. +#define CPU_TPIU_FSCR_FSCR_W 32 +#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF +#define CPU_TPIU_FSCR_FSCR_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMMASK +// +//***************************************************************************** +// Field: [31:0] CLAIMMASK +// +// This register forms one half of the Claim Tag value. When reading this +// register returns the number of bits that can be set (each bit is considered +// separately): +// +// 0: This claim tag bit is not implemented +// 1: This claim tag bit is not implemented +// +// The behavior when writing to this register is described in CLAIMSET. +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMSET +// +//***************************************************************************** +// Field: [31:0] CLAIMSET +// +// This register forms one half of the Claim Tag value. Writing to this +// location allows individual bits to be set (each bit is considered +// separately): +// +// 0: No effect +// 1: Set this bit in the claim tag +// +// The behavior when reading from this location is described in CLAIMMASK. +#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 +#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMTAG +// +//***************************************************************************** +// Field: [31:0] CLAIMTAG +// +// This register forms one half of the Claim Tag value. Reading this register +// returns the current Claim Tag value. +// Reading CLAIMMASK determines how many bits from this register must be used. +// +// The behavior when writing to this register is described in CLAIMCLR. +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMCLR +// +//***************************************************************************** +// Field: [31:0] CLAIMCLR +// +// This register forms one half of the Claim Tag value. Writing to this +// location enables individual bits to be cleared (each bit is considered +// separately): +// +// 0: No effect +// 1: Clear this bit in the claim tag. +// +// The behavior when reading from this location is described in CLAIMTAG. +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_DEVID +// +//***************************************************************************** +// Field: [31:0] DEVID +// +// This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no +// ETM present. +#define CPU_TPIU_DEVID_DEVID_W 32 +#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF +#define CPU_TPIU_DEVID_DEVID_S 0 + + +#endif // __CPU_TPIU__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h new file mode 100644 index 0000000..e349b89 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h @@ -0,0 +1,3966 @@ +/****************************************************************************** +* Filename: hw_crypto_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CRYPTO_H__ +#define __HW_CRYPTO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CRYPTO component +// +//***************************************************************************** +// Channel 0 Control +#define CRYPTO_O_DMACH0CTL 0x00000000 + +// Channel 0 External Address +#define CRYPTO_O_DMACH0EXTADDR 0x00000004 + +// Channel 0 DMA Length +#define CRYPTO_O_DMACH0LEN 0x0000000C + +// DMAC Status +#define CRYPTO_O_DMASTAT 0x00000018 + +// DMAC Software Reset +#define CRYPTO_O_DMASWRESET 0x0000001C + +// Channel 1 Control +#define CRYPTO_O_DMACH1CTL 0x00000020 + +// Channel 1 External Address +#define CRYPTO_O_DMACH1EXTADDR 0x00000024 + +// Channel 1 DMA Length +#define CRYPTO_O_DMACH1LEN 0x0000002C + +// DMAC Master Run-time Parameters +#define CRYPTO_O_DMABUSCFG 0x00000078 + +// DMAC Port Error Raw Status +#define CRYPTO_O_DMAPORTERR 0x0000007C + +// DMAC Version +#define CRYPTO_O_DMAHWVER 0x000000FC + +// Key Store Write Area +#define CRYPTO_O_KEYWRITEAREA 0x00000400 + +// Key Store Written Area +#define CRYPTO_O_KEYWRITTENAREA 0x00000404 + +// Key Store Size +#define CRYPTO_O_KEYSIZE 0x00000408 + +// Key Store Read Area +#define CRYPTO_O_KEYREADAREA 0x0000040C + +// AES_KEY2_0 / AES_GHASH_H_IN_0 +#define CRYPTO_O_AESKEY20 0x00000500 + +// AES_KEY2_0 / AES_GHASH_H_IN_0 +#define CRYPTO_O_AESKEY21 0x00000504 + +// AES_KEY2_0 / AES_GHASH_H_IN_0 +#define CRYPTO_O_AESKEY22 0x00000508 + +// AES_KEY2_0 / AES_GHASH_H_IN_0 +#define CRYPTO_O_AESKEY23 0x0000050C + +// AES_KEY3_0 / AES_KEY2_4 +#define CRYPTO_O_AESKEY30 0x00000510 + +// AES_KEY3_0 / AES_KEY2_4 +#define CRYPTO_O_AESKEY31 0x00000514 + +// AES_KEY3_0 / AES_KEY2_4 +#define CRYPTO_O_AESKEY32 0x00000518 + +// AES_KEY3_0 / AES_KEY2_4 +#define CRYPTO_O_AESKEY33 0x0000051C + +// AES initialization vector registers +#define CRYPTO_O_AESIV0 0x00000540 + +// AES initialization vector registers +#define CRYPTO_O_AESIV1 0x00000544 + +// AES initialization vector registers +#define CRYPTO_O_AESIV2 0x00000548 + +// AES initialization vector registers +#define CRYPTO_O_AESIV3 0x0000054C + +// AES Control +#define CRYPTO_O_AESCTL 0x00000550 + +// AES Crypto Length 0 (LSW) +#define CRYPTO_O_AESDATALEN0 0x00000554 + +// AES Crypto Length 1 (MSW) +#define CRYPTO_O_AESDATALEN1 0x00000558 + +// AES Authentication Length +#define CRYPTO_O_AESAUTHLEN 0x0000055C + +// Data Input/Output +#define CRYPTO_O_AESDATAOUT0 0x00000560 + +// AES Data Input_Output 0 +#define CRYPTO_O_AESDATAIN0 0x00000560 + +// Data Input/Output +#define CRYPTO_O_AESDATAOUT1 0x00000564 + +// AES Data Input_Output 0 +#define CRYPTO_O_AESDATAIN1 0x00000564 + +// Data Input/Output +#define CRYPTO_O_AESDATAOUT2 0x00000568 + +// AES Data Input_Output 2 +#define CRYPTO_O_AESDATAIN2 0x00000568 + +// Data Input/Output +#define CRYPTO_O_AESDATAOUT3 0x0000056C + +// AES Data Input_Output 3 +#define CRYPTO_O_AESDATAIN3 0x0000056C + +// AES Tag Out 0 +#define CRYPTO_O_AESTAGOUT0 0x00000570 + +// AES Tag Out 0 +#define CRYPTO_O_AESTAGOUT1 0x00000574 + +// AES Tag Out 0 +#define CRYPTO_O_AESTAGOUT2 0x00000578 + +// AES Tag Out 0 +#define CRYPTO_O_AESTAGOUT3 0x0000057C + +// HASH Data Input 1 +#define CRYPTO_O_HASHDATAIN1 0x00000604 + +// HASH Data Input 2 +#define CRYPTO_O_HASHDATAIN2 0x00000608 + +// HASH Data Input 3 +#define CRYPTO_O_HASHDATAIN3 0x0000060C + +// HASH Data Input 4 +#define CRYPTO_O_HASHDATAIN4 0x00000610 + +// HASH Data Input 5 +#define CRYPTO_O_HASHDATAIN5 0x00000614 + +// HASH Data Input 6 +#define CRYPTO_O_HASHDATAIN6 0x00000618 + +// HASH Data Input 7 +#define CRYPTO_O_HASHDATAIN7 0x0000061C + +// HASH Data Input 8 +#define CRYPTO_O_HASHDATAIN8 0x00000620 + +// HASH Data Input 9 +#define CRYPTO_O_HASHDATAIN9 0x00000624 + +// HASH Data Input 10 +#define CRYPTO_O_HASHDATAIN10 0x00000628 + +// HASH Data Input 11 +#define CRYPTO_O_HASHDATAIN11 0x0000062C + +// HASH Data Input 12 +#define CRYPTO_O_HASHDATAIN12 0x00000630 + +// HASH Data Input 13 +#define CRYPTO_O_HASHDATAIN13 0x00000634 + +// HASH Data Input 14 +#define CRYPTO_O_HASHDATAIN14 0x00000638 + +// HASH Data Input 15 +#define CRYPTO_O_HASHDATAIN15 0x0000063C + +// HASH Data Input 16 +#define CRYPTO_O_HASHDATAIN16 0x00000640 + +// HASH Data Input 17 +#define CRYPTO_O_HASHDATAIN17 0x00000644 + +// HASH Data Input 18 +#define CRYPTO_O_HASHDATAIN18 0x00000648 + +// HASH Data Input 19 +#define CRYPTO_O_HASHDATAIN19 0x0000064C + +// HASH Data Input 20 +#define CRYPTO_O_HASHDATAIN20 0x00000650 + +// HASH Data Input 21 +#define CRYPTO_O_HASHDATAIN21 0x00000654 + +// HASH Data Input 22 +#define CRYPTO_O_HASHDATAIN22 0x00000658 + +// HASH Data Input 23 +#define CRYPTO_O_HASHDATAIN23 0x0000065C + +// HASH Data Input 24 +#define CRYPTO_O_HASHDATAIN24 0x00000660 + +// HASH Data Input 25 +#define CRYPTO_O_HASHDATAIN25 0x00000664 + +// HASH Data Input 26 +#define CRYPTO_O_HASHDATAIN26 0x00000668 + +// HASH Data Input 27 +#define CRYPTO_O_HASHDATAIN27 0x0000066C + +// HASH Data Input 28 +#define CRYPTO_O_HASHDATAIN28 0x00000670 + +// HASH Data Input 29 +#define CRYPTO_O_HASHDATAIN29 0x00000674 + +// HASH Data Input 30 +#define CRYPTO_O_HASHDATAIN30 0x00000678 + +// HASH Data Input 31 +#define CRYPTO_O_HASHDATAIN31 0x0000067C + +// HASH Input_Output Buffer Control +#define CRYPTO_O_HASHIOBUFCTRL 0x00000680 + +// HASH Mode +#define CRYPTO_O_HASHMODE 0x00000684 + +// HASH Input Length LSB +#define CRYPTO_O_HASHINLENL 0x00000688 + +// HASH Input Length MSB +#define CRYPTO_O_HASHINLENH 0x0000068C + +// HASH Digest A +#define CRYPTO_O_HASHDIGESTA 0x000006C0 + +// HASH Digest B +#define CRYPTO_O_HASHDIGESTB 0x000006C4 + +// HASH Digest C +#define CRYPTO_O_HASHDIGESTC 0x000006C8 + +// HASH Digest D +#define CRYPTO_O_HASHDIGESTD 0x000006CC + +// HASH Digest E +#define CRYPTO_O_HASHDIGESTE 0x000006D0 + +// HASH Digest F +#define CRYPTO_O_HASHDIGESTF 0x000006D4 + +// HASH Digest G +#define CRYPTO_O_HASHDIGESTG 0x000006D8 + +// HASH Digest H +#define CRYPTO_O_HASHDIGESTH 0x000006DC + +// HASH Digest I +#define CRYPTO_O_HASHDIGESTI 0x000006E0 + +// HASH Digest J +#define CRYPTO_O_HASHDIGESTJ 0x000006E4 + +// HASH Digest K +#define CRYPTO_O_HASHDIGESTK 0x000006E8 + +// HASH Digest L +#define CRYPTO_O_HASHDIGESTL 0x000006EC + +// HASH Digest M +#define CRYPTO_O_HASHDIGESTM 0x000006F0 + +// HASH Digest N +#define CRYPTO_O_HASHDIGESTN 0x000006F4 + +// HASH Digest 0 +#define CRYPTO_O_HASHDIGESTO 0x000006F8 + +// HASH Digest P +#define CRYPTO_O_HASHDIGESTP 0x000006FC + +// Algorithm Select +#define CRYPTO_O_ALGSEL 0x00000700 + +// DMA Protection Control +#define CRYPTO_O_DMAPROTCTL 0x00000704 + +// Software Reset +#define CRYPTO_O_SWRESET 0x00000740 + +// Control Interrupt Configuration +#define CRYPTO_O_IRQTYPE 0x00000780 + +// Control Interrupt Enable +#define CRYPTO_O_IRQEN 0x00000784 + +// Control Interrupt Clear +#define CRYPTO_O_IRQCLR 0x00000788 + +// Control Interrupt Set +#define CRYPTO_O_IRQSET 0x0000078C + +// Control Interrupt Status +#define CRYPTO_O_IRQSTAT 0x00000790 + +// Hardware Version +#define CRYPTO_O_HWVER 0x000007FC + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0CTL +// +//***************************************************************************** +// Field: [1] PRIO +// +// Channel priority +// 0: Low +// 1: High +// If both channels have the same priority, access of the channels to the +// external port is arbitrated using the round robin scheme. If one channel has +// a high priority and another one low, the channel with the high priority is +// served first, in case of simultaneous access requests. +#define CRYPTO_DMACH0CTL_PRIO 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_BITN 1 +#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_S 1 + +// Field: [0] EN +// +// Channel enable +// 0: Disabled +// 1: Enable +// Note: Disabling an active channel interrupts the DMA operation. The ongoing +// block transfer completes, but no new transfers are requested. +#define CRYPTO_DMACH0CTL_EN 0x00000001 +#define CRYPTO_DMACH0CTL_EN_BITN 0 +#define CRYPTO_DMACH0CTL_EN_M 0x00000001 +#define CRYPTO_DMACH0CTL_EN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0EXTADDR +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Channel external address value +// When read during operation, it holds the last updated external address after +// being sent to the master interface. Note: The crypto DMA copies out upto 3 +// bytes until it hits a word boundary, thus the address need not be word +// aligned. +#define CRYPTO_DMACH0EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH0EXTADDR_ADDR_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0LEN +// +//***************************************************************************** +// Field: [15:0] DMALEN +// +// Channel DMA length in bytes +// During configuration, this register contains the DMA transfer length in +// bytes. During operation, it contains the last updated value of the DMA +// transfer length after being sent to the master interface. +// Note: Setting this register to a nonzero value starts the transfer if the +// channel is enabled. Therefore, this register must be written last when +// setting up a DMA channel. +#define CRYPTO_DMACH0LEN_DMALEN_W 16 +#define CRYPTO_DMACH0LEN_DMALEN_M 0x0000FFFF +#define CRYPTO_DMACH0LEN_DMALEN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMASTAT +// +//***************************************************************************** +// Field: [17] PORT_ERR +// +// Reflects possible transfer errors on the AHB port. +#define CRYPTO_DMASTAT_PORT_ERR 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_BITN 17 +#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_S 17 + +// Field: [1] CH1_ACT +// +// A value of 1 indicates that channel 1 is active (DMA transfer on-going). +#define CRYPTO_DMASTAT_CH1_ACT 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACT_BITN 1 +#define CRYPTO_DMASTAT_CH1_ACT_M 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACT_S 1 + +// Field: [0] CH0_ACT +// +// A value of 1 indicates that channel 0 is active (DMA transfer on-going). +#define CRYPTO_DMASTAT_CH0_ACT 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACT_BITN 0 +#define CRYPTO_DMASTAT_CH0_ACT_M 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACT_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMASWRESET +// +//***************************************************************************** +// Field: [0] SWRES +// +// Software reset enable +// 0 : Disabled +// 1 : Enabled (self-cleared to 0) +// Completion of the software reset must be checked through the DMASTAT +#define CRYPTO_DMASWRESET_SWRES 0x00000001 +#define CRYPTO_DMASWRESET_SWRES_BITN 0 +#define CRYPTO_DMASWRESET_SWRES_M 0x00000001 +#define CRYPTO_DMASWRESET_SWRES_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1CTL +// +//***************************************************************************** +// Field: [1] PRIO +// +// Channel priority +// 0: Low +// 1: High +// If both channels have the same priority, access of the channels to the +// external port is arbitrated using the round robin scheme. If one channel has +// a high priority and another one low, the channel with the high priority is +// served first, in case of simultaneous access requests. +#define CRYPTO_DMACH1CTL_PRIO 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_BITN 1 +#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_S 1 + +// Field: [0] EN +// +// Channel enable +// 0: Disabled +// 1: Enable +// Note: Disabling an active channel interrupts the DMA operation. The ongoing +// block transfer completes, but no new transfers are requested. +#define CRYPTO_DMACH1CTL_EN 0x00000001 +#define CRYPTO_DMACH1CTL_EN_BITN 0 +#define CRYPTO_DMACH1CTL_EN_M 0x00000001 +#define CRYPTO_DMACH1CTL_EN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1EXTADDR +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Channel external address value. +// When read during operation, it holds the last updated external address after +// being sent to the master interface. Note: The crypto DMA copies out upto 3 +// bytes until it hits a word boundary, thus the address need not be word +// aligned. +#define CRYPTO_DMACH1EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH1EXTADDR_ADDR_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1LEN +// +//***************************************************************************** +// Field: [15:0] DMALEN +// +// Channel DMA length in bytes. +// During configuration, this register contains the DMA transfer length in +// bytes. During operation, it contains the last updated value of the DMA +// transfer length after being sent to the master interface. +// Note: Setting this register to a nonzero value starts the transfer if the +// channel is enabled. Therefore, this register must be written last when +// setting up a DMA channel. +#define CRYPTO_DMACH1LEN_DMALEN_W 16 +#define CRYPTO_DMACH1LEN_DMALEN_M 0x0000FFFF +#define CRYPTO_DMACH1LEN_DMALEN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMABUSCFG +// +//***************************************************************************** +// Field: [15:12] AHB_MST1_BURST_SIZE +// +// Maximum burst size that can be performed on the AHB bus +// ENUMs: +// 64_BYTE 64 bytes +// 32_BYTE 32 bytes +// 16_BYTE 16 bytes +// 8_BYTE 8 bytes +// 4_BYTE 4 bytes +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 + +// Field: [11] AHB_MST1_IDLE_EN +// +// Idle insertion between consecutive burst transfers on AHB +// ENUMs: +// IDLE Idle transfer insertion enabled +// NO_IDLE Do not insert idle transfers. +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 + +// Field: [10] AHB_MST1_INCR_EN +// +// Burst length type of AHB transfer +// ENUMs: +// SPECIFIED Fixed length bursts or single transfers +// UNSPECIFIED Unspecified length burst transfers +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 + +// Field: [9] AHB_MST1_LOCK_EN +// +// Locked transform on AHB +// ENUMs: +// LOCKED Transfers are locked +// NOT_LOCKED Transfers are not locked +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 + +// Field: [8] AHB_MST1_BIGEND +// +// Endianess for the AHB master +// ENUMs: +// BIG_ENDIAN Big Endian +// LITTLE_ENDIAN Little Endian +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAPORTERR +// +//***************************************************************************** +// Field: [12] PORT1_AHB_ERROR +// +// A value of 1 indicates that the EIP-101 has detected an AHB bus error +#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR 0x00001000 +#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_BITN 12 +#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_M 0x00001000 +#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_S 12 + +// Field: [9] PORT1_CHANNEL +// +// Indicates which channel has serviced last (channel 0 or channel 1) by AHB +// master port. +#define CRYPTO_DMAPORTERR_PORT1_CHANNEL 0x00000200 +#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_BITN 9 +#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_M 0x00000200 +#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_S 9 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAHWVER +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VERSION +// +// Major version number +#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_W 4 +#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_M 0x0F000000 +#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_S 24 + +// Field: [23:20] HW_MINOR_VERSION +// +// Minor version number +#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_W 4 +#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_M 0x00F00000 +#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_S 20 + +// Field: [19:16] HW_PATCH_LEVEL +// +// Patch level +// Starts at 0 at first delivery of this version +#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_W 4 +#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_M 0x000F0000 +#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_S 16 + +// Field: [15:8] EIP_NUMBER_COMPL +// +// Bit-by-bit complement of the EIP_NUMBER field bits. +#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_W 8 +#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_M 0x0000FF00 +#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_S 8 + +// Field: [7:0] EIP_NUMBER +// +// Binary encoding of the EIP-number of this DMA controller (209) +#define CRYPTO_DMAHWVER_EIP_NUMBER_W 8 +#define CRYPTO_DMAHWVER_EIP_NUMBER_M 0x000000FF +#define CRYPTO_DMAHWVER_EIP_NUMBER_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYWRITEAREA +// +//***************************************************************************** +// Field: [7] RAM_AREA7 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA7 is not selected to be written. +// 1: RAM_AREA7 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 + +// Field: [6] RAM_AREA6 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA6 is not selected to be written. +// 1: RAM_AREA6 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 + +// Field: [5] RAM_AREA5 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA5 is not selected to be written. +// 1: RAM_AREA5 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 + +// Field: [4] RAM_AREA4 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA4 is not selected to be written. +// 1: RAM_AREA4 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 + +// Field: [3] RAM_AREA3 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA3 is not selected to be written. +// 1: RAM_AREA3 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 + +// Field: [2] RAM_AREA2 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA2 is not selected to be written. +// 1: RAM_AREA2 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 + +// Field: [1] RAM_AREA1 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA1 is not selected to be written. +// 1: RAM_AREA1 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 + +// Field: [0] RAM_AREA0 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA0 is not selected to be written. +// 1: RAM_AREA0 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYWRITTENAREA +// +//***************************************************************************** +// Field: [7] RAM_AREA_WRITTEN7 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 + +// Field: [6] RAM_AREA_WRITTEN6 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 + +// Field: [5] RAM_AREA_WRITTEN5 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 + +// Field: [4] RAM_AREA_WRITTEN4 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 + +// Field: [3] RAM_AREA_WRITTEN3 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 + +// Field: [2] RAM_AREA_WRITTEN2 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 + +// Field: [1] RAM_AREA_WRITTEN1 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 + +// Field: [0] RAM_AREA_WRITTEN0 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYSIZE +// +//***************************************************************************** +// Field: [1:0] SIZE +// +// Key size: +// 00: Reserved +// When writing this to this register, the KEY_STORE_WRITTEN_AREA register is +// reset. +// ENUMs: +// 256_BIT 256 bits +// 192_BIT 192 bits +// 128_BIT 128 bits +#define CRYPTO_KEYSIZE_SIZE_W 2 +#define CRYPTO_KEYSIZE_SIZE_M 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_S 0 +#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 +#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYREADAREA +// +//***************************************************************************** +// Field: [31] BUSY +// +// Key store operation busy status flag (read only): +// 0: Operation is complete. +// 1: Operation is not completed and the key store is busy. +#define CRYPTO_KEYREADAREA_BUSY 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_BITN 31 +#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_S 31 + +// Field: [3:0] RAM_AREA +// +// Selects the area of the key store RAM from where the key needs to be read +// that will be writen to the AES engine +// RAM_AREA: +// +// RAM areas RAM_AREA0, RAM_AREA2, RAM_AREA4 and RAM_AREA6 are the only valid +// read areas for 192 and 256 bits key sizes. +// Only RAM areas that contain valid written keys can be selected. +// ENUMs: +// NO_RAM No RAM +// RAM_AREA7 RAM Area 7 +// RAM_AREA6 RAM Area 6 +// RAM_AREA5 RAM Area 5 +// RAM_AREA4 RAM Area 4 +// RAM_AREA3 RAM Area 3 +// RAM_AREA2 RAM Area 2 +// RAM_AREA1 RAM Area 1 +// RAM_AREA0 RAM Area 0 +#define CRYPTO_KEYREADAREA_RAM_AREA_W 4 +#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F +#define CRYPTO_KEYREADAREA_RAM_AREA_S 0 +#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY20 +// +//***************************************************************************** +// Field: [31:0] AES_KEY2 +// +// AES_KEY2/AES_GHASH_H[31:0] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY20_AES_KEY2_W 32 +#define CRYPTO_AESKEY20_AES_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY20_AES_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY21 +// +//***************************************************************************** +// Field: [31:0] AES_KEY2 +// +// AES_KEY2/AES_GHASH_H[31:0] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY21_AES_KEY2_W 32 +#define CRYPTO_AESKEY21_AES_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY21_AES_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY22 +// +//***************************************************************************** +// Field: [31:0] AES_KEY2 +// +// AES_KEY2/AES_GHASH_H[31:0] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY22_AES_KEY2_W 32 +#define CRYPTO_AESKEY22_AES_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY22_AES_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY23 +// +//***************************************************************************** +// Field: [31:0] AES_KEY2 +// +// AES_KEY2/AES_GHASH_H[31:0] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY23_AES_KEY2_W 32 +#define CRYPTO_AESKEY23_AES_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY23_AES_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY30 +// +//***************************************************************************** +// Field: [31:0] AES_KEY3 +// +// AES_KEY3[31:0]/AES_KEY2[159:128] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY30_AES_KEY3_W 32 +#define CRYPTO_AESKEY30_AES_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY30_AES_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY31 +// +//***************************************************************************** +// Field: [31:0] AES_KEY3 +// +// AES_KEY3[31:0]/AES_KEY2[159:128] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY31_AES_KEY3_W 32 +#define CRYPTO_AESKEY31_AES_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY31_AES_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY32 +// +//***************************************************************************** +// Field: [31:0] AES_KEY3 +// +// AES_KEY3[31:0]/AES_KEY2[159:128] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY32_AES_KEY3_W 32 +#define CRYPTO_AESKEY32_AES_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY32_AES_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY33 +// +//***************************************************************************** +// Field: [31:0] AES_KEY3 +// +// AES_KEY3[31:0]/AES_KEY2[159:128] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY33_AES_KEY3_W 32 +#define CRYPTO_AESKEY33_AES_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY33_AES_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV0 +// +//***************************************************************************** +// Field: [31:0] AES_IV +// +// AES_IV[31:0] +// +// Initialization vector +// Used for regular non-ECB modes (CBC/CTR): +// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers +// must be written with a new 128-bit IV. After an operation, these registers +// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode +// is selected, this value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine +// +// For GCM: +// -[127:0] - AES_IV - For GCM operations, these registers must be written with +// a new 128-bit IV. +// After an operation, these registers contain the updated 128-bit result IV, +// generated by the EIP-120t. Note that bits [127:96] of the IV represent the +// initial counter value (which is 1 for GCM) and must therefore be initialized +// to 0x01000000. This value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine. +// +// For CCM: +// -[127:0] - A0: For CCM this field must be written with value A0, this value +// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and +// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL +// register. This 'L' indicates the width of the Nonce and counter. The loaded +// counter must be initialized to 0. The total width of A0 is 128-bit. +// +// For CBC-MAC: +// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the +// start of each operation. After an operation, these registers contain the +// 128-bit TAG output, generated by the EIP-120t. +#define CRYPTO_AESIV0_AES_IV_W 32 +#define CRYPTO_AESIV0_AES_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV0_AES_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV1 +// +//***************************************************************************** +// Field: [31:0] AES_IV +// +// AES_IV[31:0] +// +// Initialization vector +// Used for regular non-ECB modes (CBC/CTR): +// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers +// must be written with a new 128-bit IV. After an operation, these registers +// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode +// is selected, this value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine +// +// For GCM: +// -[127:0] - AES_IV - For GCM operations, these registers must be written with +// a new 128-bit IV. +// After an operation, these registers contain the updated 128-bit result IV, +// generated by the EIP-120t. Note that bits [127:96] of the IV represent the +// initial counter value (which is 1 for GCM) and must therefore be initialized +// to 0x01000000. This value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine. +// +// For CCM: +// -[127:0] - A0: For CCM this field must be written with value A0, this value +// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and +// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL +// register. This 'L' indicates the width of the Nonce and counter. The loaded +// counter must be initialized to 0. The total width of A0 is 128-bit. +// +// For CBC-MAC: +// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the +// start of each operation. After an operation, these registers contain the +// 128-bit TAG output, generated by the EIP-120t. +#define CRYPTO_AESIV1_AES_IV_W 32 +#define CRYPTO_AESIV1_AES_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV1_AES_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV2 +// +//***************************************************************************** +// Field: [31:0] AES_IV +// +// AES_IV[31:0] +// +// Initialization vector +// Used for regular non-ECB modes (CBC/CTR): +// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers +// must be written with a new 128-bit IV. After an operation, these registers +// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode +// is selected, this value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine +// +// For GCM: +// -[127:0] - AES_IV - For GCM operations, these registers must be written with +// a new 128-bit IV. +// After an operation, these registers contain the updated 128-bit result IV, +// generated by the EIP-120t. Note that bits [127:96] of the IV represent the +// initial counter value (which is 1 for GCM) and must therefore be initialized +// to 0x01000000. This value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine. +// +// For CCM: +// -[127:0] - A0: For CCM this field must be written with value A0, this value +// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and +// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL +// register. This 'L' indicates the width of the Nonce and counter. The loaded +// counter must be initialized to 0. The total width of A0 is 128-bit. +// +// For CBC-MAC: +// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the +// start of each operation. After an operation, these registers contain the +// 128-bit TAG output, generated by the EIP-120t. +#define CRYPTO_AESIV2_AES_IV_W 32 +#define CRYPTO_AESIV2_AES_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV2_AES_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV3 +// +//***************************************************************************** +// Field: [31:0] AES_IV +// +// AES_IV[31:0] +// +// Initialization vector +// Used for regular non-ECB modes (CBC/CTR): +// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers +// must be written with a new 128-bit IV. After an operation, these registers +// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode +// is selected, this value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine +// +// For GCM: +// -[127:0] - AES_IV - For GCM operations, these registers must be written with +// a new 128-bit IV. +// After an operation, these registers contain the updated 128-bit result IV, +// generated by the EIP-120t. Note that bits [127:96] of the IV represent the +// initial counter value (which is 1 for GCM) and must therefore be initialized +// to 0x01000000. This value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine. +// +// For CCM: +// -[127:0] - A0: For CCM this field must be written with value A0, this value +// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and +// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL +// register. This 'L' indicates the width of the Nonce and counter. The loaded +// counter must be initialized to 0. The total width of A0 is 128-bit. +// +// For CBC-MAC: +// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the +// start of each operation. After an operation, these registers contain the +// 128-bit TAG output, generated by the EIP-120t. +#define CRYPTO_AESIV3_AES_IV_W 32 +#define CRYPTO_AESIV3_AES_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV3_AES_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESCTL +// +//***************************************************************************** +// Field: [31] CONTEXT_READY +// +// If 1, this read-only status bit indicates that the context data registers +// can be overwritten and the host is permitted to write the next context. +#define CRYPTO_AESCTL_CONTEXT_READY 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_READY_BITN 31 +#define CRYPTO_AESCTL_CONTEXT_READY_M 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_READY_S 31 + +// Field: [30] SAVED_CONTEXT_RDY +// +// If 1, this status bit indicates that an AES authentication TAG and/or IV +// block(s) is/are available for the host to retrieve. This bit is only +// asserted if the save_context bit is set to 1. The bit is mutual exclusive +// with the context_ready bit. +// Writing one clears the bit to 0, indicating the AES core can start its next +// operation. This bit is also cleared when the 4th word of the output TAG +// and/or IV is read. +// Note: All other mode bit writes are ignored when this mode bit is written +// with 1. +// Note: This bit is controlled automatically by the EIP-120t for TAG read DMA +// operations. +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 + +// Field: [29] SAVE_CONTEXT +// +// This bit indicates that an authentication TAG or result IV needs to be +// stored as a result context. +// Typically this bit must be set for authentication modes returning a TAG +// (CBC-MAC, GCM and CCM), or for basic encryption modes that require future +// continuation with the current result IV. +// If this bit is set, the engine retains its full context until the TAG and/or +// IV registers are read. +// The TAG or IV must be read before the AES engine can start a new operation. +#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 +#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 + +// Field: [24:22] CCM_M +// +// Defines M, which indicates the length of the authentication field for CCM +// operations; the authentication field length equals two times (the value of +// CCM-M plus one). +// Note: The EIP-120t always returns a 128-bit authentication field, of which +// the M least significant bytes are valid. All values are supported. +#define CRYPTO_AESCTL_CCM_M_W 3 +#define CRYPTO_AESCTL_CCM_M_M 0x01C00000 +#define CRYPTO_AESCTL_CCM_M_S 22 + +// Field: [21:19] CCM_L +// +// Defines L, which indicates the width of the length field for CCM operations; +// the length field in bytes equals the value of CMM-L plus one. All values are +// supported. +#define CRYPTO_AESCTL_CCM_L_W 3 +#define CRYPTO_AESCTL_CCM_L_M 0x00380000 +#define CRYPTO_AESCTL_CCM_L_S 19 + +// Field: [18] CCM +// +// If set to 1, AES-CCM is selected +// AES-CCM is a combined mode, using AES for authentication and encryption. +// Note: Selecting AES-CCM mode requires writing of the AAD length register +// after all other registers. +// Note: The CTR mode bit in this register must also be set to 1 to enable +// AES-CTR; selecting other AES modes than CTR mode is invalid. +#define CRYPTO_AESCTL_CCM 0x00040000 +#define CRYPTO_AESCTL_CCM_BITN 18 +#define CRYPTO_AESCTL_CCM_M 0x00040000 +#define CRYPTO_AESCTL_CCM_S 18 + +// Field: [17:16] GCM +// +// Set these bits to 11 to select AES-GCM mode. +// AES-GCM is a combined mode, using the Galois field multiplier GF(2 to the +// power of 128) for authentication and AES-CTR mode for encryption. +// Note: The CTR mode bit in this register must also be set to 1 to enable +// AES-CTR +// Bit combination description: +// 00 = No GCM mode +// 01 = Reserved, do not select +// 10 = Reserved, do not select +// 11 = Autonomous GHASH (both H- and Y0-encrypted calculated internally) +// Note: The EIP-120t-1 configuration only supports mode 11 (autonomous GHASH), +// other GCM modes are not allowed. +#define CRYPTO_AESCTL_GCM_W 2 +#define CRYPTO_AESCTL_GCM_M 0x00030000 +#define CRYPTO_AESCTL_GCM_S 16 + +// Field: [15] CBC_MAC +// +// Set to 1 to select AES-CBC MAC mode. +// The direction bit must be set to 1 for this mode. +// Selecting this mode requires writing the length register after all other +// registers. +#define CRYPTO_AESCTL_CBC_MAC 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_BITN 15 +#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_S 15 + +// Field: [8:7] CTR_WIDTH +// +// Specifies the counter width for AES-CTR mode +// 00 = 32-bit counter +// 01 = 64-bit counter +// 10 = 96-bit counter +// 11 = 128-bit counter +// ENUMs: +// 128_BIT 128 bits +// 96_BIT 96 bits +// 64_BIT 64 bits +// 32_BIT 32 bits +#define CRYPTO_AESCTL_CTR_WIDTH_W 2 +#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_S 7 +#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 +#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 +#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 + +// Field: [6] CTR +// +// If set to 1, AES counter mode (CTR) is selected. +// Note: This bit must also be set for GCM and CCM, when encryption/decryption +// is required. +#define CRYPTO_AESCTL_CTR 0x00000040 +#define CRYPTO_AESCTL_CTR_BITN 6 +#define CRYPTO_AESCTL_CTR_M 0x00000040 +#define CRYPTO_AESCTL_CTR_S 6 + +// Field: [5] CBC +// +// If set to 1, cipher-block-chaining (CBC) mode is selected. +#define CRYPTO_AESCTL_CBC 0x00000020 +#define CRYPTO_AESCTL_CBC_BITN 5 +#define CRYPTO_AESCTL_CBC_M 0x00000020 +#define CRYPTO_AESCTL_CBC_S 5 + +// Field: [4:3] KEY_SIZE +// +// This read-only field specifies the key size. +// The key size is automatically configured when a new key is loaded through +// the key store module. +// 00 = N/A - Reserved +// 01 = 128-bit +// 10 = 192-bit +// 11 = 256-bit +#define CRYPTO_AESCTL_KEY_SIZE_W 2 +#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 +#define CRYPTO_AESCTL_KEY_SIZE_S 3 + +// Field: [2] DIR +// +// If set to 1 an encrypt operation is performed. +// If set to 0 a decrypt operation is performed. +// This bit must be written with a 1 when CBC-MAC is selected. +#define CRYPTO_AESCTL_DIR 0x00000004 +#define CRYPTO_AESCTL_DIR_BITN 2 +#define CRYPTO_AESCTL_DIR_M 0x00000004 +#define CRYPTO_AESCTL_DIR_S 2 + +// Field: [1] INPUT_READY +// +// If 1, this status bit indicates that the 16-byte AES input buffer is empty. +// The host is permitted to write the next block of data. +// Writing 0 clears the bit to 0 and indicates that the AES core can use the +// provided input data block. +// Writing 1 to this bit is ignored. +// Note: For DMA operations, this bit is automatically controlled by the +// EIP-120t. +// After reset, this bit is 0. After writing a context, this bit becomes 1. +#define CRYPTO_AESCTL_INPUT_READY 0x00000002 +#define CRYPTO_AESCTL_INPUT_READY_BITN 1 +#define CRYPTO_AESCTL_INPUT_READY_M 0x00000002 +#define CRYPTO_AESCTL_INPUT_READY_S 1 + +// Field: [0] OUTPUT_READY +// +// If 1, this status bit indicates that an AES output block is available to be +// retrieved by the host. +// Writing 0 clears the bit to 0 and indicates that output data is read by the +// host. The AES core can provide a next output data block. +// Writing 1 to this bit is ignored. +// Note: For DMA operations, this bit is automatically controlled by the +// EIP-120t. +#define CRYPTO_AESCTL_OUTPUT_READY 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_READY_BITN 0 +#define CRYPTO_AESCTL_OUTPUT_READY_M 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_READY_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATALEN0 +// +//***************************************************************************** +// Field: [31:0] C_LENGTH +// +// C_LENGTH[31:0] +// Bits [60:0] of the crypto length registers (LSW and MSW) store the +// cryptographic data length in bytes for all modes. Once processing with this +// context is started, this length decrements to 0. Data lengths up to (261: 1) +// bytes are allowed. +// For GCM, any value up to 236 - 32 bytes can be used. This is because a +// 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 - +// 2, resulting in a maximum number of bytes of 236 - 32. +// A write to this register triggers the engine to start using this context. +// This is valid for all modes except GCM and CCM. +// Note: For the combined modes (GCM and CCM), this length does not include the +// authentication only data; the authentication length is specified in the +// AESAUTHLEN register +// All modes must have a length greater than 0. For the combined modes, it is +// allowed to have one of the lengths equal to 0. +// For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program +// zero to the length field; in that case the length is assumed infinite. +// All data must be byte (8-bit) aligned for stream cipher modes; bit aligned +// data streams are not supported by the EIP-120t. For block cipher modes, the +// data length must be programmed in multiples of the block cipher size, 16 +// bytes. +// For a host read operation, these registers return all-0s. +#define CRYPTO_AESDATALEN0_C_LENGTH_W 32 +#define CRYPTO_AESDATALEN0_C_LENGTH_M 0xFFFFFFFF +#define CRYPTO_AESDATALEN0_C_LENGTH_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATALEN1 +// +//***************************************************************************** +// Field: [28:0] C_LENGTH +// +// C_LENGTH[60:32] +// Bits [60:0] of the crypto length registers (LSW and MSW) store the +// cryptographic data length in bytes for all modes. Once processing with this +// context is started, this length decrements to 0. Data lengths up to (261: 1) +// bytes are allowed. +// For GCM, any value up to 236 - 32 bytes can be used. This is because a +// 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 - +// 2, resulting in a maximum number of bytes of 236 - 32. +// A write to this register triggers the engine to start using this context. +// This is valid for all modes except GCM and CCM. +// Note: For the combined modes (GCM and CCM), this length does not include the +// authentication only data; the authentication length is specified in the +// AESAUTHLEN register +// All modes must have a length greater than 0. For the combined modes, it is +// allowed to have one of the lengths equal to 0. +// For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program +// zero to the length field; in that case the length is assumed infinite. +// All data must be byte (8-bit) aligned for stream cipher modes; bit aligned +// data streams are not supported by the EIP-120t. For block cipher modes, the +// data length must be programmed in multiples of the block cipher size, 16 +// bytes. +// For a host read operation, these registers return all-0s. +#define CRYPTO_AESDATALEN1_C_LENGTH_W 29 +#define CRYPTO_AESDATALEN1_C_LENGTH_M 0x1FFFFFFF +#define CRYPTO_AESDATALEN1_C_LENGTH_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESAUTHLEN +// +//***************************************************************************** +// Field: [31:0] AUTH_LENGTH +// +// Bits [31:0] of the authentication length register store the authentication +// data length in bytes for combined modes only (GCM or CCM). +// Supported AAD-lengths for CCM are from 0 to (2^16 - 2^8) bytes. For GCM any +// value up to (2^32 - 1) bytes can be used. Once processing with this context +// is started, this length decrements to 0. +// A write to this register triggers the engine to start using this context for +// GCM and CCM. +// For a host read operation, these registers return all-0s. +#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_W 32 +#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_M 0xFFFFFFFF +#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT0 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data register 0 for output block data from the Crypto peripheral. +// These bits = AES Output Data[31:0] of {127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY +// must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT0_DATA_W 32 +#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT0_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN0 +// +//***************************************************************************** +// Field: [31:0] AES_DATA_IN_OUT +// +// AES input data[31:0] / AES output data[31:0] +// Data registers for input/output block data to/from the EIP-120t. +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES core via DMA. For a host write +// operation, these registers must be written with the 128-bit input block for +// the next AES operation. Writing at a word-aligned offset within this address +// range stores the word (4 bytes) of data into the corresponding position of +// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is +// used for the next AES operation. If the last data block is not completely +// filled with valid data (see notes below), it is allowed to write only the +// words with valid data. Next AES operation is triggered by writing to the +// input_ready flag of the AES_CTRL register. +// For a host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range reads one word (4 bytes) of data out the 4-word deep (16 +// bytes = 128-bits AES block) data output buffer. The words (4 words, one full +// block) should be read before the core will move the next block to the data +// output buffer. To empty the data output buffer, the output_ready flag of the +// AES_CTRL register must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the +// last block of both AAD and message data may contain less than 128 bits +// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks +// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR +// mode, the remaining data in an unaligned data block is ignored. +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_W 32 +#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT1 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data register 0 for output block data from the Crypto peripheral. +// These bits = AES Output Data[31:0] of {127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY +// must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT1_DATA_W 32 +#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT1_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN1 +// +//***************************************************************************** +// Field: [31:0] AES_DATA_IN_OUT +// +// AES input data[31:0] / AES output data[63:32] +// Data registers for input/output block data to/from the EIP-120t. +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES core via DMA. For a host write +// operation, these registers must be written with the 128-bit input block for +// the next AES operation. Writing at a word-aligned offset within this address +// range stores the word (4 bytes) of data into the corresponding position of +// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is +// used for the next AES operation. If the last data block is not completely +// filled with valid data (see notes below), it is allowed to write only the +// words with valid data. Next AES operation is triggered by writing to the +// input_ready flag of the AES_CTRL register. +// For a host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range reads one word (4 bytes) of data out the 4-word deep (16 +// bytes = 128-bits AES block) data output buffer. The words (4 words, one full +// block) should be read before the core will move the next block to the data +// output buffer. To empty the data output buffer, the output_ready flag of the +// AES_CTRL register must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the +// last block of both AAD and message data may contain less than 128 bits +// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks +// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR +// mode, the remaining data in an unaligned data block is ignored. +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_W 32 +#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT2 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data register 0 for output block data from the Crypto peripheral. +// These bits = AES Output Data[31:0] of {127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY +// must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT2_DATA_W 32 +#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT2_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN2 +// +//***************************************************************************** +// Field: [31:0] AES_DATA_IN_OUT +// +// AES input data[95:64] / AES output data[95:64] +// Data registers for input/output block data to/from the EIP-120t. +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES core via DMA. For a host write +// operation, these registers must be written with the 128-bit input block for +// the next AES operation. Writing at a word-aligned offset within this address +// range stores the word (4 bytes) of data into the corresponding position of +// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is +// used for the next AES operation. If the last data block is not completely +// filled with valid data (see notes below), it is allowed to write only the +// words with valid data. Next AES operation is triggered by writing to the +// input_ready flag of the AES_CTRL register. +// For a host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range reads one word (4 bytes) of data out the 4-word deep (16 +// bytes = 128-bits AES block) data output buffer. The words (4 words, one full +// block) should be read before the core will move the next block to the data +// output buffer. To empty the data output buffer, the output_ready flag of the +// AES_CTRL register must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the +// last block of both AAD and message data may contain less than 128 bits +// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks +// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR +// mode, the remaining data in an unaligned data block is ignored. +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_W 32 +#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT3 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data register 0 for output block data from the Crypto peripheral. +// These bits = AES Output Data[31:0] of {127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY +// must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT3_DATA_W 32 +#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT3_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN3 +// +//***************************************************************************** +// Field: [31:0] AES_DATA_IN_OUT +// +// AES input data[127:96] / AES output data[127:96] +// Data registers for input/output block data to/from the EIP-120t. +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES core via DMA. For a host write +// operation, these registers must be written with the 128-bit input block for +// the next AES operation. Writing at a word-aligned offset within this address +// range stores the word (4 bytes) of data into the corresponding position of +// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is +// used for the next AES operation. If the last data block is not completely +// filled with valid data (see notes below), it is allowed to write only the +// words with valid data. Next AES operation is triggered by writing to the +// input_ready flag of the AES_CTRL register. +// For a host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range reads one word (4 bytes) of data out the 4-word deep (16 +// bytes = 128-bits AES block) data output buffer. The words (4 words, one full +// block) should be read before the core will move the next block to the data +// output buffer. To empty the data output buffer, the output_ready flag of the +// AES_CTRL register must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the +// last block of both AAD and message data may contain less than 128 bits +// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks +// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR +// mode, the remaining data in an unaligned data block is ignored. +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_W 32 +#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT0 +// +//***************************************************************************** +// Field: [31:0] AES_TAG +// +// AES_TAG[31:0] +// Bits [31:0] of this register stores the authentication value for the +// combined and authentication only modes. +// For a host read operation, these registers contain the last 128-bit TAG +// output of the EIP-120t; the TAG is available until the next context is +// written. +// This register will only contain valid data if the TAG is available and when +// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for +// operations/modes that do not return a TAG, reads from this register return +// data from the IV register. +#define CRYPTO_AESTAGOUT0_AES_TAG_W 32 +#define CRYPTO_AESTAGOUT0_AES_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT0_AES_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT1 +// +//***************************************************************************** +// Field: [31:0] AES_TAG +// +// AES_TAG[31:0] +// Bits [31:0] of this register stores the authentication value for the +// combined and authentication only modes. +// For a host read operation, these registers contain the last 128-bit TAG +// output of the EIP-120t; the TAG is available until the next context is +// written. +// This register will only contain valid data if the TAG is available and when +// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for +// operations/modes that do not return a TAG, reads from this register return +// data from the IV register. +#define CRYPTO_AESTAGOUT1_AES_TAG_W 32 +#define CRYPTO_AESTAGOUT1_AES_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT1_AES_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT2 +// +//***************************************************************************** +// Field: [31:0] AES_TAG +// +// AES_TAG[31:0] +// Bits [31:0] of this register stores the authentication value for the +// combined and authentication only modes. +// For a host read operation, these registers contain the last 128-bit TAG +// output of the EIP-120t; the TAG is available until the next context is +// written. +// This register will only contain valid data if the TAG is available and when +// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for +// operations/modes that do not return a TAG, reads from this register return +// data from the IV register. +#define CRYPTO_AESTAGOUT2_AES_TAG_W 32 +#define CRYPTO_AESTAGOUT2_AES_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT2_AES_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT3 +// +//***************************************************************************** +// Field: [31:0] AES_TAG +// +// AES_TAG[31:0] +// Bits [31:0] of this register stores the authentication value for the +// combined and authentication only modes. +// For a host read operation, these registers contain the last 128-bit TAG +// output of the EIP-120t; the TAG is available until the next context is +// written. +// This register will only contain valid data if the TAG is available and when +// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for +// operations/modes that do not return a TAG, reads from this register return +// data from the IV register. +#define CRYPTO_AESTAGOUT3_AES_TAG_W 32 +#define CRYPTO_AESTAGOUT3_AES_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT3_AES_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN1 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[63:32] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is +// busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN2 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[95:64] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is +// busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN3 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[127:96] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when the rfd_in bit of +// the HASH_IO_BUF_CTRL register is high. If the rfd_in bit is 0, the engine is +// busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASH_IO_BUF_CTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN4 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[159:128] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is '1'. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN5 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[191:160] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN6 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[223:192] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN7 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[255:224] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN8 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[287:256] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN9 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[319:288] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN10 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[351:320] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN11 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[383:352] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN12 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[415:384] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN13 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[447:416] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN14 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[479:448] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN15 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[511:480] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN16 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[543:512] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN17 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[575:544] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN18 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[607:576] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN19 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[639:608] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN20 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[671:640] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN21 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[703:672] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN22 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[735:704] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN23 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[767:736] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN24 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[799:768] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN25 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[831:800] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN26 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[863:832] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN27 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[895:864] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN28 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[923:896] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN29 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[959:924] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN30 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[991:960] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN31 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[1023:992] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHIOBUFCTRL +// +//***************************************************************************** +// Field: [7] PAD_DMA_MESSAGE +// +// Note: This bit must only be used when data is supplied through the DMA. It +// should not be used when data is supplied through the slave interface. +// This bit indicates whether the hash engine has to pad the message, received +// through the DMA and finalize the hash. +// When set to 1, the hash engine pads the last block using the programmed +// length. After padding, the final hash result is calculated. +// When set to 0, the hash engine treats the last written block as block-size +// aligned and calculates the intermediate digest. +// This bit is automatically cleared when the last DMA data block is arrived in +// the hash engine. +#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE 0x00000080 +#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_BITN 7 +#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M 0x00000080 +#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_S 7 + +// Field: [6] GET_DIGEST +// +// Note: The bit description below is only applicable when data is sent through +// the slave interface. This bit must be set to 0 when data is received through +// the DMA. +// This bit indicates whether the hash engine should provide the hash digest. +// When provided simultaneously with data_in_av, the hash digest is provided +// after processing the data that is currently in the HASHDATAINn register. +// When provided without data_in_av, the current internal digest buffer value +// is copied to the HASHDIGESTn registers. +// The host must write a 1 to this bit to make the intermediate hash digest +// available. +// Writing 0 to this bit has no effect. +// This bit is automatically cleared (that is, reads 0) when the hash engine +// has processed the contents of the HASHDATAINn register. In the period +// between this bit is set by the host and the actual HASHDATAINn processing, +// this bit reads 1. +#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST 0x00000040 +#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_BITN 6 +#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_M 0x00000040 +#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_S 6 + +// Field: [5] PAD_MESSAGE +// +// Note: The bit description below is only applicable when data is sent through +// the slave interface. This bit must be set to 0 when data is received through +// the DMA. +// This bit indicates that the HASHDATAINn registers hold the last data of the +// message and hash padding must be applied. +// The host must write this bit to 1 in order to indicate to the hash engine +// that the HASHDATAINn register currently holds the last data of the message. +// When pad_message is set to 1, the hash engine will add padding bits to the +// data currently in the HASHDATAINn register. +// When the last message block is smaller than 512 bits, the pad_message bit +// must be set to 1 together with the data_in_av bit. +// When the last message block is equal to 512 bits, pad_message may be set +// together with data_in_av. In this case the pad_message bit may also be set +// after the last data block has been written to the hash engine (so when the +// rfd_in bit has become 1 again after writing the last data block). +// Writing 0 to this bit has no effect. +// This bit is automatically cleared (i.e. reads 0) by the hash engine. This +// bit reads 1 between the time it was set by the host and the hash engine +// interpreted its value. +#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE 0x00000020 +#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_BITN 5 +#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_M 0x00000020 +#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_S 5 + +// Field: [2] RFD_IN +// +// Note: The bit description below is only applicable when data is sent through +// the slave interface. This bit can be ignored when data is received through +// the DMA. +// Read-only status of the input buffer of the hash engine. +// When 1, the input buffer of the hash engine can accept new data; the +// HASHDATAINn registers can safely be populated with new data. +// When 0, the input buffer of the hash engine is processing the data that is +// currently in HASHDATAINn; writing new data to these registers is not +// allowed. +#define CRYPTO_HASHIOBUFCTRL_RFD_IN 0x00000004 +#define CRYPTO_HASHIOBUFCTRL_RFD_IN_BITN 2 +#define CRYPTO_HASHIOBUFCTRL_RFD_IN_M 0x00000004 +#define CRYPTO_HASHIOBUFCTRL_RFD_IN_S 2 + +// Field: [1] DATA_IN_AV +// +// Note: The bit description below is only applicable when data is sent through +// the slave interface. This bit must be set to 0 when data is received through +// the DMA. +// This bit indicates that the HASHDATAINn registers contain new input data for +// processing. +// The host must write a 1 to this bit to start processing the data in +// HASHDATAINn; the hash engine will process the new data as soon as it is +// ready for it (rfd_in bit is 1). +// Writing 0 to this bit has no effect. +// This bit is automatically cleared (i.e. reads as 0) when the hash engine +// starts processing the HASHDATAINn contents. This bit reads 1 between the +// time it was set by the host and the hash engine actually starts processing +// the input data block. +#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV 0x00000002 +#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_BITN 1 +#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_M 0x00000002 +#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_S 1 + +// Field: [0] OUTPUT_FULL +// +// Indicates that the output buffer registers (HASHDIGESTn) are available for +// reading by the host. +// When this bit reads 0, the output buffer registers are released; the hash +// engine is allowed to write new data to it. In this case, the registers +// should not be read by the host. +// When this bit reads 1, the hash engine has stored the result of the latest +// hash operation in the output buffer registers. As long as this bit reads 1, +// the host may read output buffer registers and the hash engine is prevented +// from writing new data to the output buffer. +// After retrieving the hash result data from the output buffer, the host must +// write a 1 to this bit to clear it. This makes the digest output buffer +// available for the hash engine to store new hash results. +// Writing 0 to this bit has no effect. +// Note: If this bit is asserted (1) no new operation should be started before +// the digest is retrieved from the hash engine and this bit is cleared (0). +#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL 0x00000001 +#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_BITN 0 +#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_M 0x00000001 +#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHMODE +// +//***************************************************************************** +// Field: [6] SHA384_MODE +// +// The host must write this bit with 1 prior to processing a SHA 384 session. +#define CRYPTO_HASHMODE_SHA384_MODE 0x00000040 +#define CRYPTO_HASHMODE_SHA384_MODE_BITN 6 +#define CRYPTO_HASHMODE_SHA384_MODE_M 0x00000040 +#define CRYPTO_HASHMODE_SHA384_MODE_S 6 + +// Field: [5] SHA512_MODE +// +// The host must write this bit with 1 prior to processing a SHA 512 session. +#define CRYPTO_HASHMODE_SHA512_MODE 0x00000020 +#define CRYPTO_HASHMODE_SHA512_MODE_BITN 5 +#define CRYPTO_HASHMODE_SHA512_MODE_M 0x00000020 +#define CRYPTO_HASHMODE_SHA512_MODE_S 5 + +// Field: [4] SHA224_MODE +// +// The host must write this bit with 1 prior to processing a SHA 224 session. +#define CRYPTO_HASHMODE_SHA224_MODE 0x00000010 +#define CRYPTO_HASHMODE_SHA224_MODE_BITN 4 +#define CRYPTO_HASHMODE_SHA224_MODE_M 0x00000010 +#define CRYPTO_HASHMODE_SHA224_MODE_S 4 + +// Field: [3] SHA256_MODE +// +// The host must write this bit with 1 prior to processing a SHA 256 session. +#define CRYPTO_HASHMODE_SHA256_MODE 0x00000008 +#define CRYPTO_HASHMODE_SHA256_MODE_BITN 3 +#define CRYPTO_HASHMODE_SHA256_MODE_M 0x00000008 +#define CRYPTO_HASHMODE_SHA256_MODE_S 3 + +// Field: [0] NEW_HASH +// +// When set to 1, it indicates that the hash engine must start processing a new +// hash session. The [HASHDIGESTn.* ] registers will automatically be loaded +// with the initial hash algorithm constants of the selected hash algorithm. +// When this bit is 0 while the hash processing is started, the initial hash +// algorithm constants are not loaded in the HASHDIGESTn registers. The hash +// engine will start processing with the digest that is currently in its +// internal HASHDIGESTn registers. +// This bit is automatically cleared when hash processing is started. +#define CRYPTO_HASHMODE_NEW_HASH 0x00000001 +#define CRYPTO_HASHMODE_NEW_HASH_BITN 0 +#define CRYPTO_HASHMODE_NEW_HASH_M 0x00000001 +#define CRYPTO_HASHMODE_NEW_HASH_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHINLENL +// +//***************************************************************************** +// Field: [31:0] LENGTH_IN +// +// LENGTH_IN[31:0] +// Message length registers. The content of these registers is used by the hash +// engine during the message padding phase of the hash session. The data lines +// of this registers are directly connected to the interface of the hash +// engine. +// For a write operation by the host, these registers should be written with +// the message length in bits. +// +// Final hash operations: +// The total input data length must be programmed for new hash operations that +// require finalization (padding). The input data must be provided through the +// slave or DMA interface. +// +// Continued hash operations (finalized): +// For continued hash operations that require finalization, the total message +// length must be programmed, including the length of previously hashed data +// that corresponds to the written input digest. +// +// Non-final hash operations: +// For hash operations that do not require finalization (input data length is +// multiple of 512-bits which is SHA-256 data block size), the length field +// does not need to be programmed since not used by the operation. +// +// If the message length in bits is below (2^32-1), then only this register +// needs to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s +// in this case. +// The host may write the length register at any time during the hash session +// when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written +// before the last data of the active hash session is written into the hash +// engine. +// host read operations from these register locations will return 0s. +// Note: When getting data from DMA, this register must be programmed before +// DMA is programmed to start. +#define CRYPTO_HASHINLENL_LENGTH_IN_W 32 +#define CRYPTO_HASHINLENL_LENGTH_IN_M 0xFFFFFFFF +#define CRYPTO_HASHINLENL_LENGTH_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHINLENH +// +//***************************************************************************** +// Field: [31:0] LENGTH_IN +// +// LENGTH_IN[63:32] +// Message length registers. The content of these registers is used by the hash +// engine during the message padding phase of the hash session. The data lines +// of this registers are directly connected to the interface of the hash +// engine. +// For a write operation by the host, these registers should be written with +// the message length in bits. +// +// Final hash operations: +// The total input data length must be programmed for new hash operations that +// require finalization (padding). The input data must be provided through the +// slave or DMA interface. +// +// Continued hash operations (finalized): +// For continued hash operations that require finalization, the total message +// length must be programmed, including the length of previously hashed data +// that corresponds to the written input digest. +// +// Non-final hash operations: +// For hash operations that do not require finalization (input data length is +// multiple of 512-bits which is SHA-256 data block size), the length field +// does not need to be programmed since not used by the operation. +// +// If the message length in bits is below (2^32-1), then only HASHINLENL needs +// to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s in +// this case. +// The host may write the length register at any time during the hash session +// when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written +// before the last data of the active hash session is written into the hash +// engine. +// host read operations from these register locations will return 0s. +// Note: When getting data from DMA, this register must be programmed before +// DMA is programmed to start. +#define CRYPTO_HASHINLENH_LENGTH_IN_W 32 +#define CRYPTO_HASHINLENH_LENGTH_IN_M 0xFFFFFFFF +#define CRYPTO_HASHINLENH_LENGTH_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTA +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[31:0] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTA_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTA_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTA_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTB +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[63:32] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTB_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTB_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTB_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTC +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[95:64] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTC_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTC_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTC_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTD +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[127:96] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTD_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTD_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTD_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTE +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[159:128] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTE_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTE_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTE_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTF +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[191:160] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTF_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTF_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTF_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTG +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[223:192] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTG_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTG_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTG_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTH +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[255:224] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTH_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTH_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTH_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTI +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[287:256] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTI_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTI_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTI_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTJ +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[319:288] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTK +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[351:320] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTK_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTK_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTK_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTL +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[383:352] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTL_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTL_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTL_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTM +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[415:384] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTM_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTM_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTM_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTN +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[447:416] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTN_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTN_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTN_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTO +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[479:448] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTO_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTO_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTO_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTP +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[511:480] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTP_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTP_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTP_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_ALGSEL +// +//***************************************************************************** +// Field: [32] HASH_SHA_512 +// +// If set to one, selects the hash engine in 512B mode as destination for the +// DMA +// The maximum transfer size to DMA engine is set to 64 bytes for reading and +// 32 bytes for writing (the latter is only applicable if the hash result is +// written out through the DMA). +#define CRYPTO_ALGSEL_HASH_SHA_512 0x100000000 +#define CRYPTO_ALGSEL_HASH_SHA_512_BITN 32 +#define CRYPTO_ALGSEL_HASH_SHA_512_M 0x100000000 +#define CRYPTO_ALGSEL_HASH_SHA_512_S 32 + +// Field: [31] TAG +// +// If this bit is cleared to 0, the DMA operation involves only data. +// If this bit is set, the DMA operation includes a TAG (Authentication Result +// / Digest). +// For SHA-256 operation, a DMA must be set up for both input data and TAG. For +// any other selected module, setting this bit only allows a DMA that reads the +// TAG. No data allowed to be transferred to or from the selected module via +// the DMA. +#define CRYPTO_ALGSEL_TAG 0x80000000 +#define CRYPTO_ALGSEL_TAG_BITN 31 +#define CRYPTO_ALGSEL_TAG_M 0x80000000 +#define CRYPTO_ALGSEL_TAG_S 31 + +// Field: [2] HASH_SHA_256 +// +// If set to one, selects the hash engine in 256B mode as destination for the +// DMA +// The maximum transfer size to DMA engine is set to 64 bytes for reading and +// 32 bytes for writing (the latter is only applicable if the hash result is +// written out through the DMA). +#define CRYPTO_ALGSEL_HASH_SHA_256 0x00000004 +#define CRYPTO_ALGSEL_HASH_SHA_256_BITN 2 +#define CRYPTO_ALGSEL_HASH_SHA_256_M 0x00000004 +#define CRYPTO_ALGSEL_HASH_SHA_256_S 2 + +// Field: [1] AES +// +// If set to one, selects the AES engine as source/destination for the DMA +// The read and write maximum transfer size to the DMA engine is set to 16 +// bytes. +#define CRYPTO_ALGSEL_AES 0x00000002 +#define CRYPTO_ALGSEL_AES_BITN 1 +#define CRYPTO_ALGSEL_AES_M 0x00000002 +#define CRYPTO_ALGSEL_AES_S 1 + +// Field: [0] KEY_STORE +// +// If set to one, selects the Key Store as destination for the DMA +// The maximum transfer size to DMA engine is set to 32 bytes (however +// transfers of 16, 24 and 32 bytes are allowed) +#define CRYPTO_ALGSEL_KEY_STORE 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_BITN 0 +#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAPROTCTL +// +//***************************************************************************** +// Field: [0] PROT_EN +// +// Select AHB transfer protection control for DMA transfers using the key store +// area as destination. +// 0 : transfers use 'USER' type access. +// 1 : transfers use 'PRIVILEGED' type access. +#define CRYPTO_DMAPROTCTL_PROT_EN 0x00000001 +#define CRYPTO_DMAPROTCTL_PROT_EN_BITN 0 +#define CRYPTO_DMAPROTCTL_PROT_EN_M 0x00000001 +#define CRYPTO_DMAPROTCTL_PROT_EN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_SWRESET +// +//***************************************************************************** +// Field: [0] SW_RESET +// +// If this bit is set to 1, the following modules are reset: +// - Master control internal state is reset. That includes interrupt, error +// status register, and result available interrupt generation FSM. +// - Key store module state is reset. That includes clearing the written area +// flags; therefore, the keys must be reloaded to the key store module. +// Writing 0 has no effect. +// The bit is self cleared after executing the reset. +#define CRYPTO_SWRESET_SW_RESET 0x00000001 +#define CRYPTO_SWRESET_SW_RESET_BITN 0 +#define CRYPTO_SWRESET_SW_RESET_M 0x00000001 +#define CRYPTO_SWRESET_SW_RESET_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQTYPE +// +//***************************************************************************** +// Field: [0] LEVEL +// +// If this bit is 0, the interrupt output is a pulse. +// If this bit is set to 1, the interrupt is a level interrupt that must be +// cleared by writing the interrupt clear register. +// This bit is applicable for both interrupt output signals. +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_BITN 0 +#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQEN +// +//***************************************************************************** +// Field: [1] DMA_IN_DONE +// +// If this bit is set to 0, the DMA input done (irq_dma_in_done) interrupt +// output is disabled and remains 0. +// If this bit is set to 1, the DMA input done interrupt output is enabled. +#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// If this bit is set to 0, the result available (irq_result_av) interrupt +// output is disabled and remains 0. +// If this bit is set to 1, the result available interrupt output is enabled. +#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQCLR +// +//***************************************************************************** +// Field: [31] DMA_BUS_ERR +// +// If 1 is written to this bit, the DMA bus error status is cleared. +// Writing 0 has no effect. +#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 + +// Field: [30] KEY_ST_WR_ERR +// +// If 1 is written to this bit, the key store write error status is cleared. +// Writing 0 has no effect. +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 + +// Field: [29] KEY_ST_RD_ERR +// +// If 1 is written to this bit, the key store read error status is cleared. +// Writing 0 has no effect. +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 + +// Field: [1] DMA_IN_DONE +// +// If 1 is written to this bit, the DMA in done (irq_dma_in_done) interrupt +// output is cleared. +// Writing 0 has no effect. +// Note that clearing an interrupt makes sense only if the interrupt output is +// programmed as level (refer to IRQTYPE). +#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// If 1 is written to this bit, the result available (irq_result_av) interrupt +// output is cleared. +// Writing 0 has no effect. +// Note that clearing an interrupt makes sense only if the interrupt output is +// programmed as level (refer to IRQTYPE). +#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQSET +// +//***************************************************************************** +// Field: [1] DMA_IN_DONE +// +// If 1 is written to this bit, the DMA data in done (irq_dma_in_done) +// interrupt output is set to one. +// Writing 0 has no effect. +// If the interrupt configuration register is programmed to pulse, clearing the +// DMA data in done (irq_dma_in_done) interrupt is not needed. If it is +// programmed to level, clearing the interrupt output should be done by writing +// the interrupt clear register (IRQCLR.DMA_IN_DONE). +#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// If 1 is written to this bit, the result available (irq_result_av) interrupt +// output is set to one. +// Writing 0 has no effect. +// If the interrupt configuration register is programmed to pulse, clearing the +// result available (irq_result_av) interrupt is not needed. If it is +// programmed to level, clearing the interrupt output should be done by writing +// the interrupt clear register (IRQCLR.RESULT_AVAIL). +#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQSTAT +// +//***************************************************************************** +// Field: [31] DMA_BUS_ERR +// +// This bit is set when a DMA bus error is detected during a DMA operation. The +// value of this register is held until it is cleared through the +// IRQCLR.DMA_BUS_ERR +// Note: This error is asserted if an error is detected on the AHB master +// interface during a DMA operation. +#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 + +// Field: [30] KEY_ST_WR_ERR +// +// This bit is set when a write error is detected during the DMA write +// operation to the key store memory. The value of this register is held until +// it is cleared through the IRQCLR.KEY_ST_WR_ERR register. +// Note: This error is asserted if a DMA operation does not cover a full key +// area or more areas are written than expected. +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 + +// Field: [29] KEY_ST_RD_ERR +// +// This bit is set when a read error is detected during the read of a key from +// the key store, while copying it to the AES core. The value of this register +// is held until it is cleared through the IRQCLR.KEY_ST_RD_ERR register. +// Note: This error is asserted if a key location is selected in the key store +// that is not available. +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 + +// Field: [1] DMA_IN_DONE +// +// This read only bit returns the actual DMA data in done (irq_data_in_done) +// interrupt status of the DMA data in done interrupt output pin +// (irq_data_in_done). +#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// This read only bit returns the actual result available (irq_result_av) +// interrupt status of the result available interrupt output pin +// (irq_result_av). +#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HWVER +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VER +// +// Major version number +#define CRYPTO_HWVER_HW_MAJOR_VER_W 4 +#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 +#define CRYPTO_HWVER_HW_MAJOR_VER_S 24 + +// Field: [23:20] HW_MINOR_VER +// +// Minor version number +#define CRYPTO_HWVER_HW_MINOR_VER_W 4 +#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 +#define CRYPTO_HWVER_HW_MINOR_VER_S 20 + +// Field: [19:16] HW_PATCH_LVL +// +// Patch level +// Starts at 0 at first delivery of this version +#define CRYPTO_HWVER_HW_PATCH_LVL_W 4 +#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 +#define CRYPTO_HWVER_HW_PATCH_LVL_S 16 + +// Field: [15:8] VER_NUM_COMPL +// +// These bits simply contain the complement of bits [7:0] (0x87), used by a +// driver to ascertain that the EIP-120t register is indeed read. +#define CRYPTO_HWVER_VER_NUM_COMPL_W 8 +#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 +#define CRYPTO_HWVER_VER_NUM_COMPL_S 8 + +// Field: [7:0] VER_NUM +// +// These bits encode the EIP number for the EIP-120t, this field contains the +// value 120 (decimal) or 0x78. +#define CRYPTO_HWVER_VER_NUM_W 8 +#define CRYPTO_HWVER_VER_NUM_M 0x000000FF +#define CRYPTO_HWVER_VER_NUM_S 0 + + +#endif // __CRYPTO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi.h new file mode 100644 index 0000000..51e48a4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi.h @@ -0,0 +1,197 @@ +/****************************************************************************** +* Filename: hw_ddi.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_DDI_H__ +#define __HW_DDI_H__ + +//***************************************************************************** +// +// This file contains macros for controlling the DDI master and +// accessing DDI Slave registers via the DDI Master. +// There are 3 categories of macros in this file: +// - macros that provide an offset to a register +// located within the DDI Master itself. +// - macros that define bits or bitfields +// within the DDI Master Registers. +// - macros that provide an "instruction offset" +// that are used when accessing a DDI Slave. +// +// The macros that that provide DDI Master register offsets and +// define bits and bitfields for those registers are the typical +// macros that appear in most hw_.h header files. In +// the following example DDI_O_CFG is a macro for a +// register offset and DDI_CFG_WAITFORACK is a macro for +// a bit in that register. This example code will set the WAITFORACK +// bit in register DDI_O_CFG of the DDI Master. (Note: this +// access the Master not the Slave). +// +// HWREG(AUX_OSCDDI_BASE + DDI_O_CFG) |= DDI_CFG_WAITFORACK; +// +// +// The "instruction offset" macros are used to pass an instruction to +// the DDI Master when accessing DDI slave registers. These macros are +// only used when accessing DDI Slave Registers. (Remember DDI +// Master Registers are accessed normally). +// +// The instructions supported when accessing a DDI Slave Regsiter follow: +// - Direct Access to a DDI Slave register. I.e. read or +// write the register. +// - Set the specified bits in a DDI Slave register. +// - Clear the specified bits in a DDI Slave register. +// - Mask write of 4 bits to the a DDI Slave register. +// - Mask write of 8 bits to the a DDI Slave register. +// - Mask write of 16 bits to the a DDI Slave register. +// +// Note: only the "Direct Access" offset should be used when reading +// a DDI Slave register. Only 8- and 16-bit reads are supported. +// +// The generic format of using this marcos for a read follows: +// // read low 16-bits in DDI_SLAVE_OFF +// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR); +// +// // read high 16-bits in DDI_SLAVE_OFF +// // add 2 for data[31:16] +// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_DIR); + +// // read data[31:24] byte in DDI_SLAVE_OFF +// // add 3 for data[31:24] +// myuchar = HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 3 + DDI_O_DIR); +// +// Notes: In the above example: +// - DDI_MASTER_BASE is the base address of the DDI Master defined +// in the hw_memmap.h header file. +// - DDI_SLAVE_OFF is the DDI Slave offset defined in the +// hw_.h header file (e.g. hw_osc_top.h for the oscsc +// oscillator modules. +// - DDI_O_DIR is the "instruction offset" macro defined in this +// file that specifies the Direct Access instruction. +// +// Writes can use any of the "instruction macros". +// The following examples do a "direct write" to DDI Slave register +// DDI_SLAVE_OFF using different size operands: +// +// // ---------- DIRECT WRITES ---------- +// // Write 32-bits aligned +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x12345678; + +// // Write 16-bits aligned to high 16-bits then low 16-bits +// // Add 2 to get to high 16-bits. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0xabcd; +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0xef01; +// +// // Write each byte at DDI_SLAVE_OFF, one at a time. +// // Add 1,2,or 3 to get to bytes 1,2, or 3. +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x33; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 1) = 0x44; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0x55; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 3) = 0x66; +// +// // ---------- SET/CLR ---------- +// The set and clear functions behave similarly to eachother. Each +// can be performed on an 8-, 16-, or 32-bit operand. +// Examples follow: +// // Set all odd bits in a 32-bit words +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_SET) = 0xaaaaaaaa; +// +// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_CLR) = 0x00ff0000; +// +// // Set even bits in byte 2 (data[23:16]) using 8-bit operand +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_CLR) = 0x55; +// +// // ---------- MASKED WRITES ---------- +// The mask writes are a bit different. They operate on nibbles, +// bytes, and 16-bit elements. Two operands are required; a 'mask' +// and 'data'; The operands are concatenated and written to the master. +// e.g. the mask and data are combined as follows for a 16 bit masked +// write: +// (mask << 16) | data; +// Examples follow: +// +// // Write 5555 to low 16-bits of DDI_SLAVE_OFF register +// // a long write is needed (32-bits). +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xffff5555; + +// // Write 1AA to data bits 24:16 in high 16-bits of DDI_SLAVE_OFF register +// // Note add 4 for high 16-bits at DDI_SLAVE_OFF; mask is 1ff! +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 4) = 0x01ff01aa; +// +// // Do an 8 bit masked write of 00 to low byte of register (data[7:0]). +// // a short write is needed (16-bits). +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xff00; +// +// // Do an 8 bit masked write of 11 to byte 1 of register (data[15:8]). +// // add 2 to get to byte 1. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 2) = 0xff11; +// +// // Do an 8 bit masked write of 33 to high byte of register (data[31:24]). +// // add 6 to get to byte 3. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 6) = 0xff33; +// +// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). +// // Byte write is needed. +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xf7; +// +// // Do an 4 bit masked write of 4 to data[7:4]). +// // Add 1 for next nibble +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 1) = 0xf4; +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the DDI master instruction offsets. +// +//***************************************************************************** +#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction +#define DDI_O_SET 0x00000080 // Offset for 'Set' instruction. +#define DDI_O_CLR 0x00000100 // Offset for 'Clear' instruction. +#define DDI_O_MASK4B 0x00000200 // Offset for 4-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 7:4 are mask. Bits 3:0 are data. + // Requires 'byte' write. +#define DDI_O_MASK8B 0x00000300 // Offset for 8-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 15:8 are mask. Bits 7:0 are data. + // Requires 'short' write. +#define DDI_O_MASK16B 0x00000400 // Offset for 16-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 31:16 are mask. Bits 15:0 are data. + // Requires 'long' write. + + + +#endif // __HW_DDI_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h new file mode 100644 index 0000000..d74a01d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h @@ -0,0 +1,1153 @@ +/****************************************************************************** +* Filename: hw_ddi_0_osc_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_DDI_0_OSC_H__ +#define __HW_DDI_0_OSC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// DDI_0_OSC component +// +//***************************************************************************** +// Control 0 +#define DDI_0_OSC_O_CTL0 0x00000000 + +// Control 1 +#define DDI_0_OSC_O_CTL1 0x00000004 + +// RADC External Configuration +#define DDI_0_OSC_O_RADCEXTCFG 0x00000008 + +// Amplitude Compensation Control +#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C + +// Amplitude Compensation Threshold 1 +#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 + +// Amplitude Compensation Threshold 2 +#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 + +// Analog Bypass Values 1 +#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 + +// Internal +#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C + +// Analog Test Control +#define DDI_0_OSC_O_ATESTCTL 0x00000020 + +// ADC Doubler Nanoamp Control +#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 + +// XOSCHF Control +#define DDI_0_OSC_O_XOSCHFCTL 0x00000028 + +// Low Frequency Oscillator Control +#define DDI_0_OSC_O_LFOSCCTL 0x0000002C + +// RCOSCHF Control +#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 + +// RCOSC_MF Control +#define DDI_0_OSC_O_RCOSCMFCTL 0x00000034 + +// Status 0 +#define DDI_0_OSC_O_STAT0 0x0000003C + +// Status 1 +#define DDI_0_OSC_O_STAT1 0x00000040 + +// Status 2 +#define DDI_0_OSC_O_STAT2 0x00000044 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_CTL0 +// +//***************************************************************************** +// Field: [31] XTAL_IS_24M +// +// Set based on the accurate high frequency XTAL. +// ENUMs: +// 24M Internal. Only to be used through TI provided API. +// 48M Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 + +// Field: [29] BYPASS_XOSC_LF_CLK_QUAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 + +// Field: [28] BYPASS_RCOSC_LF_CLK_QUAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 + +// Field: [27:26] DOUBLER_START_DURATION +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 + +// Field: [25] DOUBLER_RESET_DURATION +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 + +// Field: [24] CLK_DCDC_SRC_SEL +// +// Select DCDC clock source. +// +// 0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC +// 1: CLK_DCDC is always 48 MHz clock from RCOSC +#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL 0x01000000 +#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M 0x01000000 +#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_S 24 + +// Field: [14] HPOSC_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 + +// Field: [12] RCOSC_LF_TRIMMED +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 + +// Field: [11] XOSC_HF_POWER_MODE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 + +// Field: [10] XOSC_LF_DIG_BYPASS +// +// Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf +// clock. +// +// 0: Use 32kHz XOSC as xosc_lf clock source +// 1: Use digital input (from AON) as xosc_lf clock source. +// +// This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf +// as the sclk_lf source. The muxing performed by this bit is not glitch free. +// The following procedure must be followed when changing this field to avoid +// glitches on sclk_lf. +// +// 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock +// source. +// 2) Set or clear this bit to bypass or not bypass the xosc_lf. +// 3) Set SCLK_LF_SRC_SEL to use xosc_lf. +// +// It is recommended that either the rcosc_hf or xosc_hf (whichever is +// currently active) be selected as the source in step 1 above. This provides a +// faster clock change. +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 + +// Field: [9] CLK_LOSS_EN +// +// Enable clock loss detection and hence the indicators to the system +// controller. Checks both SCLK_HF, SCLK_MF and SCLK_LF clock loss indicators. +// +// 0: Disable +// 1: Enable +// +// Clock loss detection must be disabled when changing the sclk_lf source. +// STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf +// source has completed. +#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 + +// Field: [8:7] ACLK_TDC_SRC_SEL +// +// Source select for aclk_tdc. +// +// 00: RCOSC_HF (48MHz) +// 01: RCOSC_HF (24MHz) +// 10: XOSC_HF (24MHz) +// 11: Not used +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 + +// Field: [6:4] ACLK_REF_SRC_SEL +// +// Source select for aclk_ref +// +// 000: RCOSC_HF derived (31.25kHz) +// 001: XOSC_HF derived (31.25kHz) +// 010: RCOSC_LF (32kHz) +// 011: XOSC_LF (32.768kHz) +// 100: RCOSC_MF (2MHz) +// 101-111: Not used +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 3 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000070 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 4 + +// Field: [3:2] SCLK_LF_SRC_SEL +// +// Source select for sclk_lf +// ENUMs: +// XOSCLF Low frequency XOSC +// RCOSCLF Low frequency RCOSC +// XOSCHFDLF Low frequency clock derived from High Frequency +// XOSC +// RCOSCHFDLF Low frequency clock derived from High Frequency +// RCOSC +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 + +// Field: [0] SCLK_HF_SRC_SEL +// +// Source select for sclk_hf. +// ENUMs: +// XOSC High frequency XOSC clock +// RCOSC High frequency RCOSC clock +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_CTL1 +// +//***************************************************************************** +// Field: [22:18] RCOSCHFCTRIMFRACT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 + +// Field: [17] RCOSCHFCTRIMFRACT_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 + +// Field: [1:0] XOSC_HF_FAST_START +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_RADCEXTCFG +// +//***************************************************************************** +// Field: [31:22] HPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 + +// Field: [21:16] LPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 + +// Field: [15:12] IDAC_STEP +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 + +// Field: [11:6] RADC_DAC_TH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 + +// Field: [5] RADC_MODE_IS_SAR +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPCTL +// +//***************************************************************************** +// Field: [30] AMPCOMP_REQ_MODE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 + +// Field: [29:28] AMPCOMP_FSM_UPDATE_RATE +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 250KHZ Internal. Only to be used through TI provided API. +// 500KHZ Internal. Only to be used through TI provided API. +// 1MHZ Internal. Only to be used through TI provided API. +// 2MHZ Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 + +// Field: [27] AMPCOMP_SW_CTRL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 + +// Field: [26] AMPCOMP_SW_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 + +// Field: [23:20] IBIAS_OFFSET +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 + +// Field: [19:16] IBIAS_INIT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 + +// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 + +// Field: [7:4] CAP_STEP +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 + +// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPTH1 +// +//***************************************************************************** +// Field: [23:18] HPMRAMP3_LTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 + +// Field: [15:10] HPMRAMP3_HTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 + +// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 + +// Field: [5:0] HPMRAMP1_TH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPTH2 +// +//***************************************************************************** +// Field: [31:26] LPMUPDATE_LTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 + +// Field: [23:18] LPMUPDATE_HTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 + +// Field: [15:10] ADC_COMP_AMPTH_LPM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 + +// Field: [7:2] ADC_COMP_AMPTH_HPM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ANABYPASSVAL1 +// +//***************************************************************************** +// Field: [19:16] XOSC_HF_ROW_Q12 +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 + +// Field: [15:0] XOSC_HF_COLUMN_Q12 +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ANABYPASSVAL2 +// +//***************************************************************************** +// Field: [13:0] XOSC_HF_IBIASTHERM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ATESTCTL +// +//***************************************************************************** +// Field: [31] SCLK_LF_AUX_EN +// +// Enable 32 kHz clock to AUX_COMPB. +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x80000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x80000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 31 + +// Field: [15:14] TEST_RCOSCMF +// +// Test mode control for RCOSC_MF +// +// 0x0: test modes disabled +// 0x1: boosted bias current into self biased inverter +// 0x2: clock qualification disabled +// 0x3: boosted bias current into self biased inverter + clock qualification +// disabled +#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_W 2 +#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_M 0x0000C000 +#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_S 14 + +// Field: [13:12] ATEST_RCOSCMF +// +// ATEST control for RCOSC_MF +// +// 0x0: ATEST disabled +// 0x1: ATEST enabled, VDD_LOCAL connected, ATEST internal to **RCOSC_MF* +// enabled to send out 2MHz clock. +// 0x2: ATEST disabled +// 0x3: ATEST enabled, bias current connected, ATEST internal to **RCOSC_MF* +// enabled to send out 2MHz clock. +#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_W 2 +#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_M 0x00003000 +#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_S 12 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL +// +//***************************************************************************** +// Field: [24] NANOAMP_BIAS_ENABLE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 + +// Field: [23] SPARE23 +// +// Software should not rely on the value of a reserved. Writing any other value +// than the reset value may result in undefined behavior +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 + +// Field: [5] ADC_SH_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 + +// Field: [4] ADC_SH_VBUF_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 + +// Field: [1:0] ADC_IREF_CTRL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_XOSCHFCTL +// +//***************************************************************************** +// Field: [13] TCXO_MODE_XOSC_HF_EN +// +// If this register is 1 when TCXO_MODE is 1, then the XOSC_HF is enabled, +// turning on the XOSC_HF bias current allowing a DC bias point to be provided +// to the clipped-sine wave clock signal on external input. +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN 0x00002000 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_M 0x00002000 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_S 13 + +// Field: [12] TCXO_MODE +// +// If this register is 1 when BYPASS is 1, this will enable clock +// qualification on the TCXO clock on external input. This register has no +// effect when BYPASS is 0. +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE 0x00001000 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_M 0x00001000 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_S 12 + +// Field: [9:8] PEAK_DET_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 + +// Field: [6] BYPASS +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 + +// Field: [4:2] HP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 + +// Field: [1:0] LP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_LFOSCCTL +// +//***************************************************************************** +// Field: [23:22] XOSCLF_REGULATOR_TRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 + +// Field: [21:18] XOSCLF_CMIRRWR_RATIO +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 + +// Field: [9:8] RCOSCLF_RTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 6P0MEG Internal. Only to be used through TI provided API. +// 6P5MEG Internal. Only to be used through TI provided API. +// 7P0MEG Internal. Only to be used through TI provided API. +// 7P5MEG Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 + +// Field: [7:0] RCOSCLF_CTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_RCOSCHFCTL +// +//***************************************************************************** +// Field: [15:8] RCOSCHF_CTRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_RCOSCMFCTL +// +//***************************************************************************** +// Field: [15:9] RCOSC_MF_CAP_ARRAY +// +// Adjust RCOSC_MF capacitor array. +// +// 0x0: nominal frequency, 0.625pF +// 0x40: highest frequency, 0.125pF +// 0x3F: lowest frequency, 1.125pF +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_W 7 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_M 0x0000FE00 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_S 9 + +// Field: [8] RCOSC_MF_REG_SEL +// +// Choose regulator type. +// +// 0: default +// 1: alternate +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL 0x00000100 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_M 0x00000100 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_S 8 + +// Field: [7:6] RCOSC_MF_RES_COARSE +// +// Select coarse resistor for frequency adjustment. +// +// 0x0: 400kohms, default +// 0x1: 300kohms, min +// 0x2: 600kohms, max +// 0x3: 500kohms +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_W 2 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_M 0x000000C0 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_S 6 + +// Field: [5:4] RCOSC_MF_RES_FINE +// +// Select fine resistor for frequency adjustment. +// +// 0x0: 11kohms, minimum resistance, max freq +// 0x1: 13kohms +// 0x2: 16kohms +// 0x3: 20kohms, max resistance, min freq +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_W 2 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_M 0x00000030 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_S 4 + +// Field: [3:0] RCOSC_MF_BIAS_ADJ +// +// Adjusts bias current to RCOSC_MF. +// +// 0x8 minimum current +// 0x0 default current +// 0x7 maximum current +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_W 4 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_M 0x0000000F +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT0 +// +//***************************************************************************** +// Field: [30:29] SCLK_LF_SRC +// +// Indicates source for the sclk_lf +// ENUMs: +// XOSCLF Low frequency XOSC +// RCOSCLF Low frequency RCOSC +// XOSCHFDLF Low frequency clock derived from High Frequency +// XOSC +// RCOSCHFDLF Low frequency clock derived from High Frequency +// RCOSC +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 + +// Field: [28] SCLK_HF_SRC +// +// Indicates source for the sclk_hf +// ENUMs: +// XOSC High frequency XOSC +// RCOSC High frequency RCOSC clock +#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 + +// Field: [22] RCOSC_HF_EN +// +// RCOSC_HF_EN +#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 + +// Field: [21] RCOSC_LF_EN +// +// RCOSC_LF_EN +#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 + +// Field: [20] XOSC_LF_EN +// +// XOSC_LF_EN +#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 + +// Field: [19] CLK_DCDC_RDY +// +// CLK_DCDC_RDY +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 + +// Field: [18] CLK_DCDC_RDY_ACK +// +// CLK_DCDC_RDY_ACK +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 + +// Field: [17] SCLK_HF_LOSS +// +// Indicates sclk_hf is lost +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 + +// Field: [16] SCLK_LF_LOSS +// +// Indicates sclk_lf is lost +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 + +// Field: [15] XOSC_HF_EN +// +// Indicates that XOSC_HF is enabled. +#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 + +// Field: [13] XB_48M_CLK_EN +// +// Indicates that the 48MHz clock from the DOUBLER is enabled. +// +// It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler +// bypass for the 48MHz crystal). +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 + +// Field: [11] XOSC_HF_LP_BUF_EN +// +// XOSC_HF_LP_BUF_EN +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 + +// Field: [10] XOSC_HF_HP_BUF_EN +// +// XOSC_HF_HP_BUF_EN +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 + +// Field: [8] ADC_THMET +// +// ADC_THMET +#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_S 8 + +// Field: [7] ADC_DATA_READY +// +// indicates when adc_data is ready. +#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 + +// Field: [6:1] ADC_DATA +// +// adc_data +#define DDI_0_OSC_STAT0_ADC_DATA_W 6 +#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E +#define DDI_0_OSC_STAT0_ADC_DATA_S 1 + +// Field: [0] PENDINGSCLKHFSWITCHING +// +// Indicates when SCLK_HF clock source is ready to be switched +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT1 +// +//***************************************************************************** +// Field: [31:28] RAMPSTATE +// +// AMPCOMP FSM State +// ENUMs: +// FAST_START_SETTLE FAST_START_SETTLE +// FAST_START FAST_START +// DUMMY_TO_INIT_1 DUMMY_TO_INIT_1 +// IDAC_DEC_W_MEASURE IDAC_DECREMENT_WITH_MEASURE +// IBIAS_INC IBIAS_INCREMENT +// LPM_UPDATE LPM_UPDATE +// IBIAS_DEC_W_MEASURE IBIAS_DECREMENT_WITH_MEASURE +// IBIAS_CAP_UPDATE IBIAS_CAP_UPDATE +// IDAC_INCREMENT IDAC_INCREMENT +// HPM_UPDATE HPM_UPDATE +// HPM_RAMP3 HPM_RAMP3 +// HPM_RAMP2 HPM_RAMP2 +// HPM_RAMP1 HPM_RAMP1 +// INITIALIZATION INITIALIZATION +// RESET RESET +#define DDI_0_OSC_STAT1_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_S 28 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 + +// Field: [27:22] HPM_UPDATE_AMP +// +// XOSC_HF amplitude during HPM_UPDATE state. +// When amplitude compensation of XOSC_HF is enabled in high performance mode, +// this value is the amplitude of the crystal oscillations measured by the +// on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 +// would indicate that the amplitude of the crystal is approximately 480 mV. +// To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero +// value. +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 + +// Field: [21:16] LPM_UPDATE_AMP +// +// XOSC_HF amplitude during LPM_UPDATE state +// When amplitude compensation of XOSC_HF is enabled in low power mode, this +// value is the amplitude of the crystal oscillations measured by the on-chip +// oscillator ADC, divided by 15 mV. For example, a value of 0x20 would +// indicate that the amplitude of the crystal is approximately 480 mV. To +// enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero +// value. +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 + +// Field: [15] FORCE_RCOSC_HF +// +// force_rcosc_hf +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 + +// Field: [14] SCLK_HF_EN +// +// SCLK_HF_EN +#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 + +// Field: [13] SCLK_MF_EN +// +// SCLK_MF_EN +#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 + +// Field: [12] ACLK_ADC_EN +// +// ACLK_ADC_EN +#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 + +// Field: [11] ACLK_TDC_EN +// +// ACLK_TDC_EN +#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 + +// Field: [10] ACLK_REF_EN +// +// ACLK_REF_EN +#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 + +// Field: [9] CLK_CHP_EN +// +// CLK_CHP_EN +#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 + +// Field: [8] CLK_DCDC_EN +// +// CLK_DCDC_EN +#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 + +// Field: [7] SCLK_HF_GOOD +// +// SCLK_HF_GOOD +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 + +// Field: [6] SCLK_MF_GOOD +// +// SCLK_MF_GOOD +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 + +// Field: [5] SCLK_LF_GOOD +// +// SCLK_LF_GOOD +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 + +// Field: [4] ACLK_ADC_GOOD +// +// ACLK_ADC_GOOD +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 + +// Field: [3] ACLK_TDC_GOOD +// +// ACLK_TDC_GOOD +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 + +// Field: [2] ACLK_REF_GOOD +// +// ACLK_REF_GOOD. +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 + +// Field: [1] CLK_CHP_GOOD +// +// CLK_CHP_GOOD +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 + +// Field: [0] CLK_DCDC_GOOD +// +// CLK_DCDC_GOOD +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT2 +// +//***************************************************************************** +// Field: [31:26] ADC_DCBIAS +// +// DC Bias read by RADC during SAR mode +// The value is an unsigned integer. It is used for debug only. +#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 + +// Field: [25] HPM_RAMP1_THMET +// +// Indication of threshold is met for hpm_ramp1 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 + +// Field: [24] HPM_RAMP2_THMET +// +// Indication of threshold is met for hpm_ramp2 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 + +// Field: [23] HPM_RAMP3_THMET +// +// Indication of threshold is met for hpm_ramp3 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 + +// Field: [15:12] RAMPSTATE +// +// xosc_hf amplitude compensation FSM +// +// This is identical to STAT1.RAMPSTATE. See that description for encoding. +#define DDI_0_OSC_STAT2_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 +#define DDI_0_OSC_STAT2_RAMPSTATE_S 12 + +// Field: [3] AMPCOMP_REQ +// +// ampcomp_req +#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 + +// Field: [2] XOSC_HF_AMPGOOD +// +// amplitude of xosc_hf is within the required threshold (set by DDI). Not used +// for anything just for debug/status +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 + +// Field: [1] XOSC_HF_FREQGOOD +// +// frequency of xosc_hf is good to use for the digital clocks +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 + +// Field: [0] XOSC_HF_RF_FREQGOOD +// +// frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio +// operations. Used for SW to start synthesizer. +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 + + +#endif // __DDI_0_OSC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_event.h new file mode 100644 index 0000000..c365d74 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_event.h @@ -0,0 +1,3688 @@ +/****************************************************************************** +* Filename: hw_event_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_EVENT_H__ +#define __HW_EVENT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// EVENT component +// +//***************************************************************************** +// Output Selection for CPU Interrupt 0 +#define EVENT_O_CPUIRQSEL0 0x00000000 + +// Output Selection for CPU Interrupt 1 +#define EVENT_O_CPUIRQSEL1 0x00000004 + +// Output Selection for CPU Interrupt 2 +#define EVENT_O_CPUIRQSEL2 0x00000008 + +// Output Selection for CPU Interrupt 3 +#define EVENT_O_CPUIRQSEL3 0x0000000C + +// Output Selection for CPU Interrupt 4 +#define EVENT_O_CPUIRQSEL4 0x00000010 + +// Output Selection for CPU Interrupt 5 +#define EVENT_O_CPUIRQSEL5 0x00000014 + +// Output Selection for CPU Interrupt 6 +#define EVENT_O_CPUIRQSEL6 0x00000018 + +// Output Selection for CPU Interrupt 7 +#define EVENT_O_CPUIRQSEL7 0x0000001C + +// Output Selection for CPU Interrupt 8 +#define EVENT_O_CPUIRQSEL8 0x00000020 + +// Output Selection for CPU Interrupt 9 +#define EVENT_O_CPUIRQSEL9 0x00000024 + +// Output Selection for CPU Interrupt 10 +#define EVENT_O_CPUIRQSEL10 0x00000028 + +// Output Selection for CPU Interrupt 11 +#define EVENT_O_CPUIRQSEL11 0x0000002C + +// Output Selection for CPU Interrupt 12 +#define EVENT_O_CPUIRQSEL12 0x00000030 + +// Output Selection for CPU Interrupt 13 +#define EVENT_O_CPUIRQSEL13 0x00000034 + +// Output Selection for CPU Interrupt 14 +#define EVENT_O_CPUIRQSEL14 0x00000038 + +// Output Selection for CPU Interrupt 15 +#define EVENT_O_CPUIRQSEL15 0x0000003C + +// Output Selection for CPU Interrupt 16 +#define EVENT_O_CPUIRQSEL16 0x00000040 + +// Output Selection for CPU Interrupt 17 +#define EVENT_O_CPUIRQSEL17 0x00000044 + +// Output Selection for CPU Interrupt 18 +#define EVENT_O_CPUIRQSEL18 0x00000048 + +// Output Selection for CPU Interrupt 19 +#define EVENT_O_CPUIRQSEL19 0x0000004C + +// Output Selection for CPU Interrupt 20 +#define EVENT_O_CPUIRQSEL20 0x00000050 + +// Output Selection for CPU Interrupt 21 +#define EVENT_O_CPUIRQSEL21 0x00000054 + +// Output Selection for CPU Interrupt 22 +#define EVENT_O_CPUIRQSEL22 0x00000058 + +// Output Selection for CPU Interrupt 23 +#define EVENT_O_CPUIRQSEL23 0x0000005C + +// Output Selection for CPU Interrupt 24 +#define EVENT_O_CPUIRQSEL24 0x00000060 + +// Output Selection for CPU Interrupt 25 +#define EVENT_O_CPUIRQSEL25 0x00000064 + +// Output Selection for CPU Interrupt 26 +#define EVENT_O_CPUIRQSEL26 0x00000068 + +// Output Selection for CPU Interrupt 27 +#define EVENT_O_CPUIRQSEL27 0x0000006C + +// Output Selection for CPU Interrupt 28 +#define EVENT_O_CPUIRQSEL28 0x00000070 + +// Output Selection for CPU Interrupt 29 +#define EVENT_O_CPUIRQSEL29 0x00000074 + +// Output Selection for CPU Interrupt 30 +#define EVENT_O_CPUIRQSEL30 0x00000078 + +// Output Selection for CPU Interrupt 31 +#define EVENT_O_CPUIRQSEL31 0x0000007C + +// Output Selection for CPU Interrupt 32 +#define EVENT_O_CPUIRQSEL32 0x00000080 + +// Output Selection for CPU Interrupt 33 +#define EVENT_O_CPUIRQSEL33 0x00000084 + +// Output Selection for CPU Interrupt 34 +#define EVENT_O_CPUIRQSEL34 0x00000088 + +// Output Selection for CPU Interrupt 35 +#define EVENT_O_CPUIRQSEL35 0x0000008C + +// Output Selection for CPU Interrupt 36 +#define EVENT_O_CPUIRQSEL36 0x00000090 + +// Output Selection for CPU Interrupt 37 +#define EVENT_O_CPUIRQSEL37 0x00000094 + +// Output Selection for RFC Event 0 +#define EVENT_O_RFCSEL0 0x00000100 + +// Output Selection for RFC Event 1 +#define EVENT_O_RFCSEL1 0x00000104 + +// Output Selection for RFC Event 2 +#define EVENT_O_RFCSEL2 0x00000108 + +// Output Selection for RFC Event 3 +#define EVENT_O_RFCSEL3 0x0000010C + +// Output Selection for RFC Event 4 +#define EVENT_O_RFCSEL4 0x00000110 + +// Output Selection for RFC Event 5 +#define EVENT_O_RFCSEL5 0x00000114 + +// Output Selection for RFC Event 6 +#define EVENT_O_RFCSEL6 0x00000118 + +// Output Selection for RFC Event 7 +#define EVENT_O_RFCSEL7 0x0000011C + +// Output Selection for RFC Event 8 +#define EVENT_O_RFCSEL8 0x00000120 + +// Output Selection for RFC Event 9 +#define EVENT_O_RFCSEL9 0x00000124 + +// Output Selection for GPT0 0 +#define EVENT_O_GPT0ACAPTSEL 0x00000200 + +// Output Selection for GPT0 1 +#define EVENT_O_GPT0BCAPTSEL 0x00000204 + +// Output Selection for GPT1 0 +#define EVENT_O_GPT1ACAPTSEL 0x00000300 + +// Output Selection for GPT1 1 +#define EVENT_O_GPT1BCAPTSEL 0x00000304 + +// Output Selection for GPT2 0 +#define EVENT_O_GPT2ACAPTSEL 0x00000400 + +// Output Selection for GPT2 1 +#define EVENT_O_GPT2BCAPTSEL 0x00000404 + +// Output Selection for DMA Channel 1 SREQ +#define EVENT_O_UDMACH1SSEL 0x00000508 + +// Output Selection for DMA Channel 1 REQ +#define EVENT_O_UDMACH1BSEL 0x0000050C + +// Output Selection for DMA Channel 2 SREQ +#define EVENT_O_UDMACH2SSEL 0x00000510 + +// Output Selection for DMA Channel 2 REQ +#define EVENT_O_UDMACH2BSEL 0x00000514 + +// Output Selection for DMA Channel 3 SREQ +#define EVENT_O_UDMACH3SSEL 0x00000518 + +// Output Selection for DMA Channel 3 REQ +#define EVENT_O_UDMACH3BSEL 0x0000051C + +// Output Selection for DMA Channel 4 SREQ +#define EVENT_O_UDMACH4SSEL 0x00000520 + +// Output Selection for DMA Channel 4 REQ +#define EVENT_O_UDMACH4BSEL 0x00000524 + +// Output Selection for DMA Channel 5 SREQ +#define EVENT_O_UDMACH5SSEL 0x00000528 + +// Output Selection for DMA Channel 5 REQ +#define EVENT_O_UDMACH5BSEL 0x0000052C + +// Output Selection for DMA Channel 6 SREQ +#define EVENT_O_UDMACH6SSEL 0x00000530 + +// Output Selection for DMA Channel 6 REQ +#define EVENT_O_UDMACH6BSEL 0x00000534 + +// Output Selection for DMA Channel 7 SREQ +#define EVENT_O_UDMACH7SSEL 0x00000538 + +// Output Selection for DMA Channel 7 REQ +#define EVENT_O_UDMACH7BSEL 0x0000053C + +// Output Selection for DMA Channel 8 SREQ +#define EVENT_O_UDMACH8SSEL 0x00000540 + +// Output Selection for DMA Channel 8 REQ +#define EVENT_O_UDMACH8BSEL 0x00000544 + +// Output Selection for DMA Channel 9 SREQ +#define EVENT_O_UDMACH9SSEL 0x00000548 + +// Output Selection for DMA Channel 9 REQ +#define EVENT_O_UDMACH9BSEL 0x0000054C + +// Output Selection for DMA Channel 10 SREQ +#define EVENT_O_UDMACH10SSEL 0x00000550 + +// Output Selection for DMA Channel 10 REQ +#define EVENT_O_UDMACH10BSEL 0x00000554 + +// Output Selection for DMA Channel 11 SREQ +#define EVENT_O_UDMACH11SSEL 0x00000558 + +// Output Selection for DMA Channel 11 REQ +#define EVENT_O_UDMACH11BSEL 0x0000055C + +// Output Selection for DMA Channel 12 SREQ +#define EVENT_O_UDMACH12SSEL 0x00000560 + +// Output Selection for DMA Channel 12 REQ +#define EVENT_O_UDMACH12BSEL 0x00000564 + +// Output Selection for DMA Channel 13 REQ +#define EVENT_O_UDMACH13BSEL 0x0000056C + +// Output Selection for DMA Channel 14 REQ +#define EVENT_O_UDMACH14BSEL 0x00000574 + +// Output Selection for DMA Channel 15 REQ +#define EVENT_O_UDMACH15BSEL 0x0000057C + +// Output Selection for DMA Channel 16 SREQ +#define EVENT_O_UDMACH16SSEL 0x00000580 + +// Output Selection for DMA Channel 16 REQ +#define EVENT_O_UDMACH16BSEL 0x00000584 + +// Output Selection for DMA Channel 17 SREQ +#define EVENT_O_UDMACH17SSEL 0x00000588 + +// Output Selection for DMA Channel 17 REQ +#define EVENT_O_UDMACH17BSEL 0x0000058C + +// Output Selection for DMA Channel 21 SREQ +#define EVENT_O_UDMACH21SSEL 0x000005A8 + +// Output Selection for DMA Channel 21 REQ +#define EVENT_O_UDMACH21BSEL 0x000005AC + +// Output Selection for DMA Channel 22 SREQ +#define EVENT_O_UDMACH22SSEL 0x000005B0 + +// Output Selection for DMA Channel 22 REQ +#define EVENT_O_UDMACH22BSEL 0x000005B4 + +// Output Selection for DMA Channel 23 SREQ +#define EVENT_O_UDMACH23SSEL 0x000005B8 + +// Output Selection for DMA Channel 23 REQ +#define EVENT_O_UDMACH23BSEL 0x000005BC + +// Output Selection for DMA Channel 24 SREQ +#define EVENT_O_UDMACH24SSEL 0x000005C0 + +// Output Selection for DMA Channel 24 REQ +#define EVENT_O_UDMACH24BSEL 0x000005C4 + +// Output Selection for GPT3 0 +#define EVENT_O_GPT3ACAPTSEL 0x00000600 + +// Output Selection for GPT3 1 +#define EVENT_O_GPT3BCAPTSEL 0x00000604 + +// Output Selection for AUX Subscriber 0 +#define EVENT_O_AUXSEL0 0x00000700 + +// Output Selection for NMI Subscriber 0 +#define EVENT_O_CM3NMISEL0 0x00000800 + +// Output Selection for I2S Subscriber 0 +#define EVENT_O_I2SSTMPSEL0 0x00000900 + +// Output Selection for FRZ Subscriber +#define EVENT_O_FRZSEL0 0x00000A00 + +// Set or Clear Software Events +#define EVENT_O_SWEV 0x00000F00 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +#define EVENT_CPUIRQSEL0_EV_W 7 +#define EVENT_CPUIRQSEL0_EV_M 0x0000007F +#define EVENT_CPUIRQSEL0_EV_S 0 +#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL1 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// I2C_IRQ Interrupt event from I2C +#define EVENT_CPUIRQSEL1_EV_W 7 +#define EVENT_CPUIRQSEL1_EV_M 0x0000007F +#define EVENT_CPUIRQSEL1_EV_S 0 +#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL2 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +#define EVENT_CPUIRQSEL2_EV_W 7 +#define EVENT_CPUIRQSEL2_EV_M 0x0000007F +#define EVENT_CPUIRQSEL2_EV_S 0 +#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL3 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// PKA_IRQ PKA Interrupt event +#define EVENT_CPUIRQSEL3_EV_W 7 +#define EVENT_CPUIRQSEL3_EV_M 0x0000007F +#define EVENT_CPUIRQSEL3_EV_S 0 +#define EVENT_CPUIRQSEL3_EV_PKA_IRQ 0x0000001F + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL4 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +#define EVENT_CPUIRQSEL4_EV_W 7 +#define EVENT_CPUIRQSEL4_EV_M 0x0000007F +#define EVENT_CPUIRQSEL4_EV_S 0 +#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL5 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +#define EVENT_CPUIRQSEL5_EV_W 7 +#define EVENT_CPUIRQSEL5_EV_M 0x0000007F +#define EVENT_CPUIRQSEL5_EV_S 0 +#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL6 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SWEV0 AUX software event 0, triggered by +// AUX_EVCTL:SWEVSET.SWEV0, also available as +// AUX_EVENT0 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +#define EVENT_CPUIRQSEL6_EV_W 7 +#define EVENT_CPUIRQSEL6_EV_M 0x0000007F +#define EVENT_CPUIRQSEL6_EV_S 0 +#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL7 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +#define EVENT_CPUIRQSEL7_EV_W 7 +#define EVENT_CPUIRQSEL7_EV_M 0x0000007F +#define EVENT_CPUIRQSEL7_EV_S 0 +#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL8 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +#define EVENT_CPUIRQSEL8_EV_W 7 +#define EVENT_CPUIRQSEL8_EV_M 0x0000007F +#define EVENT_CPUIRQSEL8_EV_S 0 +#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL9 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +#define EVENT_CPUIRQSEL9_EV_W 7 +#define EVENT_CPUIRQSEL9_EV_M 0x0000007F +#define EVENT_CPUIRQSEL9_EV_S 0 +#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL10 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +#define EVENT_CPUIRQSEL10_EV_W 7 +#define EVENT_CPUIRQSEL10_EV_M 0x0000007F +#define EVENT_CPUIRQSEL10_EV_S 0 +#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL11 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +#define EVENT_CPUIRQSEL11_EV_W 7 +#define EVENT_CPUIRQSEL11_EV_M 0x0000007F +#define EVENT_CPUIRQSEL11_EV_S 0 +#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL12 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// I2S_IRQ Interrupt event from I2S +#define EVENT_CPUIRQSEL12_EV_W 7 +#define EVENT_CPUIRQSEL12_EV_M 0x0000007F +#define EVENT_CPUIRQSEL12_EV_S 0 +#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL13 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SWEV1 AUX software event 1, triggered by +// AUX_EVCTL:SWEVSET.SWEV1, also available as +// AUX_EVENT2 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +#define EVENT_CPUIRQSEL13_EV_W 7 +#define EVENT_CPUIRQSEL13_EV_M 0x0000007F +#define EVENT_CPUIRQSEL13_EV_S 0 +#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL14 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +#define EVENT_CPUIRQSEL14_EV_W 7 +#define EVENT_CPUIRQSEL14_EV_M 0x0000007F +#define EVENT_CPUIRQSEL14_EV_S 0 +#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL15 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +#define EVENT_CPUIRQSEL15_EV_W 7 +#define EVENT_CPUIRQSEL15_EV_M 0x0000007F +#define EVENT_CPUIRQSEL15_EV_S 0 +#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL16 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +#define EVENT_CPUIRQSEL16_EV_W 7 +#define EVENT_CPUIRQSEL16_EV_M 0x0000007F +#define EVENT_CPUIRQSEL16_EV_S 0 +#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL17 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +#define EVENT_CPUIRQSEL17_EV_W 7 +#define EVENT_CPUIRQSEL17_EV_M 0x0000007F +#define EVENT_CPUIRQSEL17_EV_S 0 +#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL18 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +#define EVENT_CPUIRQSEL18_EV_W 7 +#define EVENT_CPUIRQSEL18_EV_M 0x0000007F +#define EVENT_CPUIRQSEL18_EV_S 0 +#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL19 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +#define EVENT_CPUIRQSEL19_EV_W 7 +#define EVENT_CPUIRQSEL19_EV_M 0x0000007F +#define EVENT_CPUIRQSEL19_EV_S 0 +#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL20 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +#define EVENT_CPUIRQSEL20_EV_W 7 +#define EVENT_CPUIRQSEL20_EV_M 0x0000007F +#define EVENT_CPUIRQSEL20_EV_S 0 +#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL21 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +#define EVENT_CPUIRQSEL21_EV_W 7 +#define EVENT_CPUIRQSEL21_EV_M 0x0000007F +#define EVENT_CPUIRQSEL21_EV_S 0 +#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL22 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +#define EVENT_CPUIRQSEL22_EV_W 7 +#define EVENT_CPUIRQSEL22_EV_M 0x0000007F +#define EVENT_CPUIRQSEL22_EV_S 0 +#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL23 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +#define EVENT_CPUIRQSEL23_EV_W 7 +#define EVENT_CPUIRQSEL23_EV_M 0x0000007F +#define EVENT_CPUIRQSEL23_EV_S 0 +#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL24 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +#define EVENT_CPUIRQSEL24_EV_W 7 +#define EVENT_CPUIRQSEL24_EV_M 0x0000007F +#define EVENT_CPUIRQSEL24_EV_S 0 +#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL25 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS +#define EVENT_CPUIRQSEL25_EV_W 7 +#define EVENT_CPUIRQSEL25_EV_M 0x0000007F +#define EVENT_CPUIRQSEL25_EV_S 0 +#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL26 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +#define EVENT_CPUIRQSEL26_EV_W 7 +#define EVENT_CPUIRQSEL26_EV_M 0x0000007F +#define EVENT_CPUIRQSEL26_EV_S 0 +#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL27 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_CPUIRQSEL27_EV_W 7 +#define EVENT_CPUIRQSEL27_EV_M 0x0000007F +#define EVENT_CPUIRQSEL27_EV_S 0 +#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL28 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +#define EVENT_CPUIRQSEL28_EV_W 7 +#define EVENT_CPUIRQSEL28_EV_M 0x0000007F +#define EVENT_CPUIRQSEL28_EV_S 0 +#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL29 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +#define EVENT_CPUIRQSEL29_EV_W 7 +#define EVENT_CPUIRQSEL29_EV_M 0x0000007F +#define EVENT_CPUIRQSEL29_EV_S 0 +#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL30 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg +// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled +// by CRYPTO:IRQEN.DMA_IN_DONE +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, +// see UDMA0:SOFTREQ +// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see +// UDMA0:SOFTREQ +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2S_IRQ Interrupt event from I2S +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// NONE Always inactive +#define EVENT_CPUIRQSEL30_EV_W 7 +#define EVENT_CPUIRQSEL30_EV_M 0x0000007F +#define EVENT_CPUIRQSEL30_EV_S 0 +#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 +#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B +#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 +#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 +#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 +#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL31 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +#define EVENT_CPUIRQSEL31_EV_W 7 +#define EVENT_CPUIRQSEL31_EV_M 0x0000007F +#define EVENT_CPUIRQSEL31_EV_S 0 +#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL32 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +#define EVENT_CPUIRQSEL32_EV_W 7 +#define EVENT_CPUIRQSEL32_EV_M 0x0000007F +#define EVENT_CPUIRQSEL32_EV_S 0 +#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL33 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN +#define EVENT_CPUIRQSEL33_EV_W 7 +#define EVENT_CPUIRQSEL33_EV_M 0x0000007F +#define EVENT_CPUIRQSEL33_EV_S 0 +#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL34 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// OSC_COMB Combined event from Oscillator control +#define EVENT_CPUIRQSEL34_EV_W 7 +#define EVENT_CPUIRQSEL34_EV_M 0x0000007F +#define EVENT_CPUIRQSEL34_EV_S 0 +#define EVENT_CPUIRQSEL34_EV_OSC_COMB 0x00000006 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL35 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +#define EVENT_CPUIRQSEL35_EV_W 7 +#define EVENT_CPUIRQSEL35_EV_M 0x0000007F +#define EVENT_CPUIRQSEL35_EV_S 0 +#define EVENT_CPUIRQSEL35_EV_AUX_TIMER2_EV0 0x00000038 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL36 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +#define EVENT_CPUIRQSEL36_EV_W 7 +#define EVENT_CPUIRQSEL36_EV_M 0x0000007F +#define EVENT_CPUIRQSEL36_EV_S 0 +#define EVENT_CPUIRQSEL36_EV_UART1_COMB 0x00000025 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL37 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// BATMON_COMB Combined event from battery monitor +#define EVENT_CPUIRQSEL37_EV_W 7 +#define EVENT_CPUIRQSEL37_EV_M 0x0000007F +#define EVENT_CPUIRQSEL37_EV_S 0 +#define EVENT_CPUIRQSEL37_EV_BATMON_COMB 0x00000005 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +#define EVENT_RFCSEL0_EV_W 7 +#define EVENT_RFCSEL0_EV_M 0x0000007F +#define EVENT_RFCSEL0_EV_S 0 +#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL1 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +#define EVENT_RFCSEL1_EV_W 7 +#define EVENT_RFCSEL1_EV_M 0x0000007F +#define EVENT_RFCSEL1_EV_S 0 +#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL2 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +#define EVENT_RFCSEL2_EV_W 7 +#define EVENT_RFCSEL2_EV_M 0x0000007F +#define EVENT_RFCSEL2_EV_S 0 +#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL3 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +#define EVENT_RFCSEL3_EV_W 7 +#define EVENT_RFCSEL3_EV_M 0x0000007F +#define EVENT_RFCSEL3_EV_S 0 +#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL4 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +#define EVENT_RFCSEL4_EV_W 7 +#define EVENT_RFCSEL4_EV_M 0x0000007F +#define EVENT_RFCSEL4_EV_S 0 +#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL5 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +#define EVENT_RFCSEL5_EV_W 7 +#define EVENT_RFCSEL5_EV_M 0x0000007F +#define EVENT_RFCSEL5_EV_S 0 +#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL6 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +#define EVENT_RFCSEL6_EV_W 7 +#define EVENT_RFCSEL6_EV_M 0x0000007F +#define EVENT_RFCSEL6_EV_S 0 +#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL7 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +#define EVENT_RFCSEL7_EV_W 7 +#define EVENT_RFCSEL7_EV_M 0x0000007F +#define EVENT_RFCSEL7_EV_S 0 +#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL8 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +#define EVENT_RFCSEL8_EV_W 7 +#define EVENT_RFCSEL8_EV_M 0x0000007F +#define EVENT_RFCSEL8_EV_S 0 +#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL9 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2S_IRQ Interrupt event from I2S +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +// NONE Always inactive +#define EVENT_RFCSEL9_EV_W 7 +#define EVENT_RFCSEL9_EV_M 0x0000007F +#define EVENT_RFCSEL9_EV_S 0 +#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B +#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A +#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_RFCSEL9_EV_SWEV1 0x00000065 +#define EVENT_RFCSEL9_EV_SWEV0 0x00000064 +#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_RFCSEL9_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_RFCSEL9_EV_UART1_COMB 0x00000025 +#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 +#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 +#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 +#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 +#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 +#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 +#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 +#define EVENT_RFCSEL9_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT0ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT0ACAPTSEL_EV_W 7 +#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0ACAPTSEL_EV_S 0 +#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT0ACAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0ACAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT0ACAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT0BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT0BCAPTSEL_EV_W 7 +#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0BCAPTSEL_EV_S 0 +#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT0BCAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0BCAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT0BCAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT1ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT1ACAPTSEL_EV_W 7 +#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1ACAPTSEL_EV_S 0 +#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT1ACAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1ACAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT1ACAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT1BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT1BCAPTSEL_EV_W 7 +#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1BCAPTSEL_EV_S 0 +#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT1BCAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1BCAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT1BCAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT2ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT2ACAPTSEL_EV_W 7 +#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2ACAPTSEL_EV_S 0 +#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT2ACAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2ACAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT2ACAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT2BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT2BCAPTSEL_EV_W 7 +#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2BCAPTSEL_EV_S 0 +#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT2BCAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2BCAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT2BCAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH1SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by +// UART0:DMACTL.RXDMAE +#define EVENT_UDMACH1SSEL_EV_W 7 +#define EVENT_UDMACH1SSEL_EV_M 0x0000007F +#define EVENT_UDMACH1SSEL_EV_S 0 +#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH1BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by +// UART0:DMACTL.RXDMAE +#define EVENT_UDMACH1BSEL_EV_W 7 +#define EVENT_UDMACH1BSEL_EV_M 0x0000007F +#define EVENT_UDMACH1BSEL_EV_S 0 +#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH2SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by +// UART0:DMACTL.TXDMAE +#define EVENT_UDMACH2SSEL_EV_W 7 +#define EVENT_UDMACH2SSEL_EV_M 0x0000007F +#define EVENT_UDMACH2SSEL_EV_S 0 +#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH2BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by +// UART0:DMACTL.TXDMAE +#define EVENT_UDMACH2BSEL_EV_W 7 +#define EVENT_UDMACH2BSEL_EV_M 0x0000007F +#define EVENT_UDMACH2BSEL_EV_S 0 +#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH3SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH3SSEL_EV_W 7 +#define EVENT_UDMACH3SSEL_EV_M 0x0000007F +#define EVENT_UDMACH3SSEL_EV_S 0 +#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH3BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH3BSEL_EV_W 7 +#define EVENT_UDMACH3BSEL_EV_M 0x0000007F +#define EVENT_UDMACH3BSEL_EV_S 0 +#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH4SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH4SSEL_EV_W 7 +#define EVENT_UDMACH4SSEL_EV_M 0x0000007F +#define EVENT_UDMACH4SSEL_EV_S 0 +#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH4BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH4BSEL_EV_W 7 +#define EVENT_UDMACH4BSEL_EV_M 0x0000007F +#define EVENT_UDMACH4BSEL_EV_S 0 +#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH5SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART1_RX_DMASREQ UART1 RX DMA single request, controlled by +// UART1:DMACTL.RXDMAE +#define EVENT_UDMACH5SSEL_EV_W 7 +#define EVENT_UDMACH5SSEL_EV_M 0x0000007F +#define EVENT_UDMACH5SSEL_EV_S 0 +#define EVENT_UDMACH5SSEL_EV_UART1_RX_DMASREQ 0x00000035 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH5BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART1_RX_DMABREQ UART1 RX DMA burst request, controlled by +// UART1:DMACTL.RXDMAE +#define EVENT_UDMACH5BSEL_EV_W 7 +#define EVENT_UDMACH5BSEL_EV_M 0x0000007F +#define EVENT_UDMACH5BSEL_EV_S 0 +#define EVENT_UDMACH5BSEL_EV_UART1_RX_DMABREQ 0x00000034 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH6SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART1_TX_DMASREQ UART1 TX DMA single request, controlled by +// UART1:DMACTL.TXDMAE +#define EVENT_UDMACH6SSEL_EV_W 7 +#define EVENT_UDMACH6SSEL_EV_M 0x0000007F +#define EVENT_UDMACH6SSEL_EV_S 0 +#define EVENT_UDMACH6SSEL_EV_UART1_TX_DMASREQ 0x00000037 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH6BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART1_TX_DMABREQ UART1 TX DMA burst request, controlled by +// UART1:DMACTL.TXDMAE +#define EVENT_UDMACH6BSEL_EV_W 7 +#define EVENT_UDMACH6BSEL_EV_M 0x0000007F +#define EVENT_UDMACH6BSEL_EV_S 0 +#define EVENT_UDMACH6BSEL_EV_UART1_TX_DMABREQ 0x00000036 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH7SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_DMASREQ DMA single request event from AUX, configured by +// AUX_EVCTL:DMACTL +#define EVENT_UDMACH7SSEL_EV_W 7 +#define EVENT_UDMACH7SSEL_EV_M 0x0000007F +#define EVENT_UDMACH7SSEL_EV_S 0 +#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH7BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_DMABREQ DMA burst request event from AUX, configured by +// AUX_EVCTL:DMACTL +#define EVENT_UDMACH7BSEL_EV_W 7 +#define EVENT_UDMACH7BSEL_EV_M 0x0000007F +#define EVENT_UDMACH7BSEL_EV_S 0 +#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH8SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +#define EVENT_UDMACH8SSEL_EV_W 7 +#define EVENT_UDMACH8SSEL_EV_M 0x0000007F +#define EVENT_UDMACH8SSEL_EV_S 0 +#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH8BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +#define EVENT_UDMACH8BSEL_EV_W 7 +#define EVENT_UDMACH8BSEL_EV_M 0x0000007F +#define EVENT_UDMACH8BSEL_EV_S 0 +#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH9SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH9SSEL_EV_W 7 +#define EVENT_UDMACH9SSEL_EV_M 0x0000007F +#define EVENT_UDMACH9SSEL_EV_S 0 +#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 +#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH9BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH9BSEL_EV_W 7 +#define EVENT_UDMACH9BSEL_EV_M 0x0000007F +#define EVENT_UDMACH9BSEL_EV_S 0 +#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH10SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH10SSEL_EV_W 7 +#define EVENT_UDMACH10SSEL_EV_M 0x0000007F +#define EVENT_UDMACH10SSEL_EV_S 0 +#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 +#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH10BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH10BSEL_EV_W 7 +#define EVENT_UDMACH10BSEL_EV_M 0x0000007F +#define EVENT_UDMACH10BSEL_EV_S 0 +#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH11SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH11SSEL_EV_W 7 +#define EVENT_UDMACH11SSEL_EV_M 0x0000007F +#define EVENT_UDMACH11SSEL_EV_S 0 +#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 +#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH11BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH11BSEL_EV_W 7 +#define EVENT_UDMACH11BSEL_EV_M 0x0000007F +#define EVENT_UDMACH11BSEL_EV_S 0 +#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH12SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH12SSEL_EV_W 7 +#define EVENT_UDMACH12SSEL_EV_M 0x0000007F +#define EVENT_UDMACH12SSEL_EV_S 0 +#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 +#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH12BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH12BSEL_EV_W 7 +#define EVENT_UDMACH12BSEL_EV_M 0x0000007F +#define EVENT_UDMACH12BSEL_EV_S 0 +#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH13BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +#define EVENT_UDMACH13BSEL_EV_W 7 +#define EVENT_UDMACH13BSEL_EV_M 0x0000007F +#define EVENT_UDMACH13BSEL_EV_S 0 +#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH14BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// CPU_HALTED CPU halted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_DMABREQ DMA burst request event from AUX, configured by +// AUX_EVCTL:DMACTL +// AUX_DMASREQ DMA single request event from AUX, configured by +// AUX_EVCTL:DMACTL +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +// WDT_NMI Watchdog non maskable interrupt event, controlled +// by WDT:CTL.INTTYPE +// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg +// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled +// by CRYPTO:IRQEN.DMA_IN_DONE +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_TX_DMASREQ UART1 TX DMA single request, controlled by +// UART1:DMACTL.TXDMAE +// UART1_TX_DMABREQ UART1 TX DMA burst request, controlled by +// UART1:DMACTL.TXDMAE +// UART1_RX_DMASREQ UART1 RX DMA single request, controlled by +// UART1:DMACTL.RXDMAE +// UART1_RX_DMABREQ UART1 RX DMA burst request, controlled by +// UART1:DMACTL.RXDMAE +// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by +// UART0:DMACTL.TXDMAE +// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by +// UART0:DMACTL.TXDMAE +// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by +// UART0:DMACTL.RXDMAE +// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by +// UART0:DMACTL.RXDMAE +// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// PKA_IRQ PKA Interrupt event +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// AUX_SWEV1 AUX software event 1, triggered by +// AUX_EVCTL:SWEVSET.SWEV1, also available as +// AUX_EVENT2 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, +// see UDMA0:SOFTREQ +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see +// UDMA0:SOFTREQ +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2C_IRQ Interrupt event from I2C +// I2S_IRQ Interrupt event from I2S +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +// NONE Always inactive +#define EVENT_UDMACH14BSEL_EV_W 7 +#define EVENT_UDMACH14BSEL_EV_M 0x0000007F +#define EVENT_UDMACH14BSEL_EV_S 0 +#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 +#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 +#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 +#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 +#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_UDMACH14BSEL_EV_UART1_TX_DMASREQ 0x00000037 +#define EVENT_UDMACH14BSEL_EV_UART1_TX_DMABREQ 0x00000036 +#define EVENT_UDMACH14BSEL_EV_UART1_RX_DMASREQ 0x00000035 +#define EVENT_UDMACH14BSEL_EV_UART1_RX_DMABREQ 0x00000034 +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 +#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 +#define EVENT_UDMACH14BSEL_EV_UART1_COMB 0x00000025 +#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 +#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_UDMACH14BSEL_EV_PKA_IRQ 0x0000001F +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 +#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 +#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 +#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 +#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 +#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 +#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F +#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E +#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D +#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C +#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B +#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_UDMACH14BSEL_EV_OSC_COMB 0x00000006 +#define EVENT_UDMACH14BSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 +#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 +#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 +#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH15BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +#define EVENT_UDMACH15BSEL_EV_W 7 +#define EVENT_UDMACH15BSEL_EV_M 0x0000007F +#define EVENT_UDMACH15BSEL_EV_S 0 +#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH16SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH16SSEL_EV_W 7 +#define EVENT_UDMACH16SSEL_EV_M 0x0000007F +#define EVENT_UDMACH16SSEL_EV_S 0 +#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH16BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH16BSEL_EV_W 7 +#define EVENT_UDMACH16BSEL_EV_M 0x0000007F +#define EVENT_UDMACH16BSEL_EV_S 0 +#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH17SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH17SSEL_EV_W 7 +#define EVENT_UDMACH17SSEL_EV_M 0x0000007F +#define EVENT_UDMACH17SSEL_EV_S 0 +#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH17BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH17BSEL_EV_W 7 +#define EVENT_UDMACH17BSEL_EV_M 0x0000007F +#define EVENT_UDMACH17BSEL_EV_S 0 +#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH21SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_UDMACH21SSEL_EV_W 7 +#define EVENT_UDMACH21SSEL_EV_M 0x0000007F +#define EVENT_UDMACH21SSEL_EV_S 0 +#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH21BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_UDMACH21BSEL_EV_W 7 +#define EVENT_UDMACH21BSEL_EV_M 0x0000007F +#define EVENT_UDMACH21BSEL_EV_S 0 +#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH22SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +#define EVENT_UDMACH22SSEL_EV_W 7 +#define EVENT_UDMACH22SSEL_EV_M 0x0000007F +#define EVENT_UDMACH22SSEL_EV_S 0 +#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH22BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +#define EVENT_UDMACH22BSEL_EV_W 7 +#define EVENT_UDMACH22BSEL_EV_M 0x0000007F +#define EVENT_UDMACH22BSEL_EV_S 0 +#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH23SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +#define EVENT_UDMACH23SSEL_EV_W 7 +#define EVENT_UDMACH23SSEL_EV_M 0x0000007F +#define EVENT_UDMACH23SSEL_EV_S 0 +#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH23BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +#define EVENT_UDMACH23BSEL_EV_W 7 +#define EVENT_UDMACH23BSEL_EV_M 0x0000007F +#define EVENT_UDMACH23BSEL_EV_S 0 +#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH24SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +#define EVENT_UDMACH24SSEL_EV_W 7 +#define EVENT_UDMACH24SSEL_EV_M 0x0000007F +#define EVENT_UDMACH24SSEL_EV_S 0 +#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH24BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +#define EVENT_UDMACH24BSEL_EV_W 7 +#define EVENT_UDMACH24BSEL_EV_M 0x0000007F +#define EVENT_UDMACH24BSEL_EV_S 0 +#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 + +//***************************************************************************** +// +// Register: EVENT_O_GPT3ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT3ACAPTSEL_EV_W 7 +#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3ACAPTSEL_EV_S 0 +#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT3ACAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3ACAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT3ACAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT3BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT3BCAPTSEL_EV_W 7 +#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3BCAPTSEL_EV_S 0 +#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT3BCAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3BCAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT3BCAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_AUXSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +// NONE Always inactive +#define EVENT_AUXSEL0_EV_W 7 +#define EVENT_AUXSEL0_EV_M 0x0000007F +#define EVENT_AUXSEL0_EV_S 0 +#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_AUXSEL0_EV_GPT3B_CMP 0x00000044 +#define EVENT_AUXSEL0_EV_GPT3A_CMP 0x00000043 +#define EVENT_AUXSEL0_EV_GPT2B_CMP 0x00000042 +#define EVENT_AUXSEL0_EV_GPT2A_CMP 0x00000041 +#define EVENT_AUXSEL0_EV_GPT1B_CMP 0x00000040 +#define EVENT_AUXSEL0_EV_GPT1A_CMP 0x0000003F +#define EVENT_AUXSEL0_EV_GPT0B_CMP 0x0000003E +#define EVENT_AUXSEL0_EV_GPT0A_CMP 0x0000003D +#define EVENT_AUXSEL0_EV_GPT1B 0x00000013 +#define EVENT_AUXSEL0_EV_GPT1A 0x00000012 +#define EVENT_AUXSEL0_EV_GPT0B 0x00000011 +#define EVENT_AUXSEL0_EV_GPT0A 0x00000010 +#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F +#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E +#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D +#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C +#define EVENT_AUXSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_CM3NMISEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// WDT_NMI Watchdog non maskable interrupt event, controlled +// by WDT:CTL.INTTYPE +#define EVENT_CM3NMISEL0_EV_W 7 +#define EVENT_CM3NMISEL0_EV_M 0x0000007F +#define EVENT_CM3NMISEL0_EV_S 0 +#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 + +//***************************************************************************** +// +// Register: EVENT_O_I2SSTMPSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// NONE Always inactive +#define EVENT_I2SSTMPSEL0_EV_W 7 +#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F +#define EVENT_I2SSTMPSEL0_EV_S 0 +#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_FRZSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// CPU_HALTED CPU halted +// NONE Always inactive +#define EVENT_FRZSEL0_EV_W 7 +#define EVENT_FRZSEL0_EV_M 0x0000007F +#define EVENT_FRZSEL0_EV_S 0 +#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 +#define EVENT_FRZSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_SWEV +// +//***************************************************************************** +// Field: [24] SWEV3 +// +// Writing "1" to this bit when the value is "0" triggers the Software 3 event. +#define EVENT_SWEV_SWEV3 0x01000000 +#define EVENT_SWEV_SWEV3_BITN 24 +#define EVENT_SWEV_SWEV3_M 0x01000000 +#define EVENT_SWEV_SWEV3_S 24 + +// Field: [16] SWEV2 +// +// Writing "1" to this bit when the value is "0" triggers the Software 2 event. +#define EVENT_SWEV_SWEV2 0x00010000 +#define EVENT_SWEV_SWEV2_BITN 16 +#define EVENT_SWEV_SWEV2_M 0x00010000 +#define EVENT_SWEV_SWEV2_S 16 + +// Field: [8] SWEV1 +// +// Writing "1" to this bit when the value is "0" triggers the Software 1 event. +#define EVENT_SWEV_SWEV1 0x00000100 +#define EVENT_SWEV_SWEV1_BITN 8 +#define EVENT_SWEV_SWEV1_M 0x00000100 +#define EVENT_SWEV_SWEV1_S 8 + +// Field: [0] SWEV0 +// +// Writing "1" to this bit when the value is "0" triggers the Software 0 event. +#define EVENT_SWEV_SWEV0 0x00000001 +#define EVENT_SWEV_SWEV0_BITN 0 +#define EVENT_SWEV_SWEV0_M 0x00000001 +#define EVENT_SWEV_SWEV0_S 0 + + +#endif // __EVENT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h new file mode 100644 index 0000000..31bca68 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h @@ -0,0 +1,2904 @@ +/****************************************************************************** +* Filename: hw_fcfg1_h +* Revised: 2018-11-06 14:08:24 +0100 (Tue, 06 Nov 2018) +* Revision: 53237 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_FCFG1_H__ +#define __HW_FCFG1_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// FCFG1 component +// +//***************************************************************************** +// Misc configurations +#define FCFG1_O_MISC_CONF_1 0x000000A0 + +// Internal +#define FCFG1_O_MISC_CONF_2 0x000000A4 + +// Internal +#define FCFG1_O_HPOSC_MEAS_5 0x000000B0 + +// Internal +#define FCFG1_O_HPOSC_MEAS_4 0x000000B4 + +// Internal +#define FCFG1_O_HPOSC_MEAS_3 0x000000B8 + +// Internal +#define FCFG1_O_HPOSC_MEAS_2 0x000000BC + +// Internal +#define FCFG1_O_HPOSC_MEAS_1 0x000000C0 + +// Internal +#define FCFG1_O_CONFIG_CC26_FE 0x000000C4 + +// Internal +#define FCFG1_O_CONFIG_CC13_FE 0x000000C8 + +// Internal +#define FCFG1_O_CONFIG_RF_COMMON 0x000000CC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4 0x000000D0 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4 0x000000D4 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G 0x000000D8 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G 0x000000DC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV4_CC26 0x000000E0 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV4_CC13 0x000000E4 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000E8 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV6_CC26 0x000000EC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV6_CC13 0x000000F0 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000F4 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV12_CC26 0x000000F8 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV12_CC13 0x000000FC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV15 0x00000100 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV30 0x00000104 + +// Flash information +#define FCFG1_O_FLASH_NUMBER 0x00000164 + +// Flash information +#define FCFG1_O_FLASH_COORDINATE 0x0000016C + +// Internal +#define FCFG1_O_FLASH_E_P 0x00000170 + +// Internal +#define FCFG1_O_FLASH_C_E_P_R 0x00000174 + +// Internal +#define FCFG1_O_FLASH_P_R_PV 0x00000178 + +// Internal +#define FCFG1_O_FLASH_EH_SEQ 0x0000017C + +// Internal +#define FCFG1_O_FLASH_VHV_E 0x00000180 + +// Internal +#define FCFG1_O_FLASH_PP 0x00000184 + +// Internal +#define FCFG1_O_FLASH_PROG_EP 0x00000188 + +// Internal +#define FCFG1_O_FLASH_ERA_PW 0x0000018C + +// Internal +#define FCFG1_O_FLASH_VHV 0x00000190 + +// Internal +#define FCFG1_O_FLASH_VHV_PV 0x00000194 + +// Internal +#define FCFG1_O_FLASH_V 0x00000198 + +// User Identification. +#define FCFG1_O_USER_ID 0x00000294 + +// Internal +#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 + +// Internal +#define FCFG1_O_ANA2_TRIM 0x000002B4 + +// Internal +#define FCFG1_O_LDO_TRIM 0x000002B8 + +// MAC BLE Address 0 +#define FCFG1_O_MAC_BLE_0 0x000002E8 + +// MAC BLE Address 1 +#define FCFG1_O_MAC_BLE_1 0x000002EC + +// MAC IEEE 802.15.4 Address 0 +#define FCFG1_O_MAC_15_4_0 0x000002F0 + +// MAC IEEE 802.15.4 Address 1 +#define FCFG1_O_MAC_15_4_1 0x000002F4 + +// Internal +#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 + +// Miscellaneous Trim Parameters +#define FCFG1_O_MISC_TRIM 0x0000030C + +// Internal +#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 + +// IcePick Device Identification +#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 + +// Factory Configuration (FCFG1) Revision +#define FCFG1_O_FCFG1_REVISION 0x0000031C + +// Misc OTP Data +#define FCFG1_O_MISC_OTP_DATA 0x00000320 + +// IO Configuration +#define FCFG1_O_IOCONF 0x00000344 + +// Internal +#define FCFG1_O_CONFIG_IF_ADC 0x0000034C + +// Internal +#define FCFG1_O_CONFIG_OSC_TOP 0x00000350 + +// AUX_ADC Gain in Absolute Reference Mode +#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C + +// AUX_ADC Gain in Relative Reference Mode +#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 + +// AUX_ADC Temperature Offsets in Absolute Reference Mode +#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 + +// Internal +#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C + +// Internal +#define FCFG1_O_AMPCOMP_TH1 0x00000370 + +// Internal +#define FCFG1_O_AMPCOMP_TH2 0x00000374 + +// Internal +#define FCFG1_O_AMPCOMP_CTRL1 0x00000378 + +// Internal +#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C + +// Internal +#define FCFG1_O_VOLT_TRIM 0x00000388 + +// OSC Configuration +#define FCFG1_O_OSC_CONF 0x0000038C + +// Internal +#define FCFG1_O_FREQ_OFFSET 0x00000390 + +// Internal +#define FCFG1_O_MISC_OTP_DATA_1 0x00000398 + +// Shadow of EFUSE:DIE_ID_0 register +#define FCFG1_O_SHDW_DIE_ID_0 0x000003D0 + +// Shadow of EFUSE:DIE_ID_1 register +#define FCFG1_O_SHDW_DIE_ID_1 0x000003D4 + +// Shadow of EFUSE:DIE_ID_2 register +#define FCFG1_O_SHDW_DIE_ID_2 0x000003D8 + +// Shadow of EFUSE:DIE_ID_3 register +#define FCFG1_O_SHDW_DIE_ID_3 0x000003DC + +// Internal +#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x000003F8 + +// Internal +#define FCFG1_O_SHDW_ANA_TRIM 0x000003FC + +// Internal +#define FCFG1_O_DAC_BIAS_CNF 0x0000040C + +// Internal +#define FCFG1_O_TFW_PROBE 0x00000418 + +// Internal +#define FCFG1_O_TFW_FT 0x0000041C + +// Internal +#define FCFG1_O_DAC_CAL0 0x00000420 + +// Internal +#define FCFG1_O_DAC_CAL1 0x00000424 + +// Internal +#define FCFG1_O_DAC_CAL2 0x00000428 + +// Internal +#define FCFG1_O_DAC_CAL3 0x0000042C + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_CONF_1 +// +//***************************************************************************** +// Field: [7:0] DEVICE_MINOR_REV +// +// HW minor revision number (a value of 0xFF shall be treated equally to 0x00). +// Any test of this field by SW should be implemented as a 'greater or equal' +// comparison as signed integer. +// Value may change without warning. +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_CONF_2 +// +//***************************************************************************** +// Field: [7:0] HPOSC_COMP_P3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_5 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_W 16 +#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_S 16 + +// Field: [15:8] HPOSC_T5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_W 8 +#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_S 8 + +// Field: [7:0] HPOSC_DT5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_W 8 +#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_M 0x000000FF +#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_4 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D4 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_W 16 +#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_S 16 + +// Field: [15:8] HPOSC_T4 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_W 8 +#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_S 8 + +// Field: [7:0] HPOSC_DT4 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_W 8 +#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_M 0x000000FF +#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_3 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_W 16 +#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_S 16 + +// Field: [15:8] HPOSC_T3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_W 8 +#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_S 8 + +// Field: [7:0] HPOSC_DT3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_W 8 +#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_M 0x000000FF +#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_2 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_W 16 +#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_S 16 + +// Field: [15:8] HPOSC_T2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_W 8 +#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_S 8 + +// Field: [7:0] HPOSC_DT2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_W 8 +#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_M 0x000000FF +#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_1 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_W 16 +#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_S 16 + +// Field: [15:8] HPOSC_T1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_W 8 +#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_S 8 + +// Field: [7:0] HPOSC_DT1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_W 8 +#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_M 0x000000FF +#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_CC26_FE +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_W 4 +#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_LNA_IB_W 4 +#define FCFG1_CONFIG_CC26_FE_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_CC26_FE_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_S 14 + +// Field: [13] PATRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N 0x00002000 +#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_BITN 13 +#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_M 0x00002000 +#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_S 13 + +// Field: [12] RSSITRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N 0x00001000 +#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_BITN 12 +#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_M 0x00001000 +#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_S 12 + +// Field: [7:0] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_M 0x000000FF +#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_CC13_FE +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_W 4 +#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_LNA_IB_W 4 +#define FCFG1_CONFIG_CC13_FE_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_CC13_FE_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_S 14 + +// Field: [13] PATRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N 0x00002000 +#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_BITN 13 +#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_M 0x00002000 +#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_S 13 + +// Field: [12] RSSITRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N 0x00001000 +#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_BITN 12 +#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_M 0x00001000 +#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_S 12 + +// Field: [7:0] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_M 0x000000FF +#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_COMMON +// +//***************************************************************************** +// Field: [31] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP 0x80000000 +#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_BITN 31 +#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_M 0x80000000 +#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_S 31 + +// Field: [30:25] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_M 0x7E000000 +#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_S 25 + +// Field: [21] PA20DBMTRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N 0x00200000 +#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_BITN 21 +#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_M 0x00200000 +#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_S 21 + +// Field: [20:16] CTL_PA_20DBM_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_W 5 +#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_M 0x001F0000 +#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_S 16 + +// Field: [15:9] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_M 0x0000FE00 +#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_DACTRIM_W 6 +#define FCFG1_CONFIG_RF_COMMON_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_RF_COMMON_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV4_CC26 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV4_CC13 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV5 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV6_CC26 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV6_CC13 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV10 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV12_CC26 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV12_CC13 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV15 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV30 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_NUMBER +// +//***************************************************************************** +// Field: [31:0] LOT_NUMBER +// +// Number of the manufacturing lot that produced this unit. +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_COORDINATE +// +//***************************************************************************** +// Field: [31:16] XCOORDINATE +// +// X coordinate of this unit on the wafer. +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 + +// Field: [15:0] YCOORDINATE +// +// Y coordinate of this unit on the wafer. +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_E_P +// +//***************************************************************************** +// Field: [31:24] PSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_PSU_W 8 +#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 +#define FCFG1_FLASH_E_P_PSU_S 24 + +// Field: [23:16] ESU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_ESU_W 8 +#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 +#define FCFG1_FLASH_E_P_ESU_S 16 + +// Field: [15:8] PVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_PVSU_W 8 +#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 +#define FCFG1_FLASH_E_P_PVSU_S 8 + +// Field: [7:0] EVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_EVSU_W 8 +#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF +#define FCFG1_FLASH_E_P_EVSU_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_C_E_P_R +// +//***************************************************************************** +// Field: [31:24] RVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_RVSU_W 8 +#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 +#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 + +// Field: [23:16] PV_ACCESS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 + +// Field: [15:12] A_EXEZ_SETUP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 + +// Field: [11:0] CVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_CVSU_W 12 +#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF +#define FCFG1_FLASH_C_E_P_R_CVSU_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_P_R_PV +// +//***************************************************************************** +// Field: [31:24] PH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PH_W 8 +#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 +#define FCFG1_FLASH_P_R_PV_PH_S 24 + +// Field: [23:16] RH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_RH_W 8 +#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 +#define FCFG1_FLASH_P_R_PV_RH_S 16 + +// Field: [15:8] PVH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PVH_W 8 +#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 +#define FCFG1_FLASH_P_R_PV_PVH_S 8 + +// Field: [7:0] PVH2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PVH2_W 8 +#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF +#define FCFG1_FLASH_P_R_PV_PVH2_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_EH_SEQ +// +//***************************************************************************** +// Field: [31:24] EH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_EH_W 8 +#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 +#define FCFG1_FLASH_EH_SEQ_EH_S 24 + +// Field: [23:16] SEQ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_SEQ_W 8 +#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 +#define FCFG1_FLASH_EH_SEQ_SEQ_S 16 + +// Field: [15:12] VSTAT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 +#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 +#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 + +// Field: [11:0] SM_FREQUENCY +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV_E +// +//***************************************************************************** +// Field: [31:16] VHV_E_START +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 +#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 + +// Field: [15:0] VHV_E_STEP_HIGHT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_PP +// +//***************************************************************************** +// Field: [31:24] PUMP_SU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PP_PUMP_SU_W 8 +#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 +#define FCFG1_FLASH_PP_PUMP_SU_S 24 + +// Field: [23:16] TRIM3P4 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PP_TRIM3P4_W 8 +#define FCFG1_FLASH_PP_TRIM3P4_M 0x00FF0000 +#define FCFG1_FLASH_PP_TRIM3P4_S 16 + +// Field: [15:0] MAX_PP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PP_MAX_PP_W 16 +#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF +#define FCFG1_FLASH_PP_MAX_PP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_PROG_EP +// +//***************************************************************************** +// Field: [31:16] MAX_EP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 +#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 +#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 + +// Field: [15:0] PROGRAM_PW +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_ERA_PW +// +//***************************************************************************** +// Field: [31:0] ERASE_PW +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 +#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF +#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV +// +//***************************************************************************** +// Field: [27:24] TRIM13_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_TRIM13_P_W 4 +#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 +#define FCFG1_FLASH_VHV_TRIM13_P_S 24 + +// Field: [19:16] VHV_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_VHV_P_W 4 +#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 +#define FCFG1_FLASH_VHV_VHV_P_S 16 + +// Field: [11:8] TRIM13_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_TRIM13_E_W 4 +#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 +#define FCFG1_FLASH_VHV_TRIM13_E_S 8 + +// Field: [3:0] VHV_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_VHV_E_W 4 +#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F +#define FCFG1_FLASH_VHV_VHV_E_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV_PV +// +//***************************************************************************** +// Field: [27:24] TRIM13_PV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 + +// Field: [19:16] VHV_PV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 +#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 +#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 + +// Field: [15:8] VCG2P5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 +#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 +#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 + +// Field: [7:0] VINH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VINH_W 8 +#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF +#define FCFG1_FLASH_VHV_PV_VINH_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_V +// +//***************************************************************************** +// Field: [31:24] VSL_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_VSL_P_W 8 +#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 +#define FCFG1_FLASH_V_VSL_P_S 24 + +// Field: [23:16] VWL_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_VWL_P_W 8 +#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 +#define FCFG1_FLASH_V_VWL_P_S 16 + +// Field: [15:8] V_READ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_V_READ_W 8 +#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 +#define FCFG1_FLASH_V_V_READ_S 8 + +// Field: [7:0] TRIM0P8 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_TRIM0P8_W 8 +#define FCFG1_FLASH_V_TRIM0P8_M 0x000000FF +#define FCFG1_FLASH_V_TRIM0P8_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_USER_ID +// +//***************************************************************************** +// Field: [31:28] PG_REV +// +// Field used to distinguish revisions of the device +#define FCFG1_USER_ID_PG_REV_W 4 +#define FCFG1_USER_ID_PG_REV_M 0xF0000000 +#define FCFG1_USER_ID_PG_REV_S 28 + +// Field: [27:26] VER +// +// Version number. +// +// 0x0: Bits [25:12] of this register has the stated meaning. +// +// Any other setting indicate a different encoding of these bits. +#define FCFG1_USER_ID_VER_W 2 +#define FCFG1_USER_ID_VER_M 0x0C000000 +#define FCFG1_USER_ID_VER_S 26 + +// Field: [25] PA +// +// 0: Does not support 20dBm PA +// 1: Supports 20dBM PA +#define FCFG1_USER_ID_PA 0x02000000 +#define FCFG1_USER_ID_PA_BITN 25 +#define FCFG1_USER_ID_PA_M 0x02000000 +#define FCFG1_USER_ID_PA_S 25 + +// Field: [23] CC13 +// +// 0: CC26xx device type +// 1: CC13xx device type +#define FCFG1_USER_ID_CC13 0x00800000 +#define FCFG1_USER_ID_CC13_BITN 23 +#define FCFG1_USER_ID_CC13_M 0x00800000 +#define FCFG1_USER_ID_CC13_S 23 + +// Field: [22:19] SEQUENCE +// +// Sequence. +// +// Used to differentiate between marketing/orderable product where other fields +// of this register are the same (temp range, flash size, voltage range etc) +#define FCFG1_USER_ID_SEQUENCE_W 4 +#define FCFG1_USER_ID_SEQUENCE_M 0x00780000 +#define FCFG1_USER_ID_SEQUENCE_S 19 + +// Field: [18:16] PKG +// +// Package type. +// +// 0x0: 4x4mm QFN (RHB) package +// 0x1: 5x5mm QFN (RSM) package +// 0x2: 7x7mm QFN (RGZ) package +// 0x3: Wafer sale package (naked die) +// 0x4: WCSP (YFV) +// 0x5: 7x7mm QFN package with Wettable Flanks +// +// Other values are reserved for future use. +// Packages available for a specific device are shown in the device datasheet. +#define FCFG1_USER_ID_PKG_W 3 +#define FCFG1_USER_ID_PKG_M 0x00070000 +#define FCFG1_USER_ID_PKG_S 16 + +// Field: [15:12] PROTOCOL +// +// Protocols supported. +// +// 0x1: BLE +// 0x2: RF4CE +// 0x4: Zigbee/6lowpan +// 0x8: Proprietary +// +// More than one protocol can be supported on same device - values above are +// then combined. +#define FCFG1_USER_ID_PROTOCOL_W 4 +#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 +#define FCFG1_USER_ID_PROTOCOL_S 12 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_OTP_DATA3 +// +//***************************************************************************** +// Field: [31:23] EC_STEP_SIZE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 + +// Field: [22] DO_PRECOND +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 + +// Field: [21:18] MAX_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 + +// Field: [17:16] TRIM_1P7 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 + +// Field: [15:8] FLASH_SIZE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 + +// Field: [7:0] WAIT_SYSCODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ANA2_TRIM +// +//***************************************************************************** +// Field: [31] RCOSCHFCTRIMFRACT_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 + +// Field: [30:26] RCOSCHFCTRIMFRACT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 + +// Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 + +// Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 + +// Field: [21:15] NANOAMP_RES_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 7 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F8000 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 15 + +// Field: [11] DITHER_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 +#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_S 11 + +// Field: [10:8] DCDC_IPEAK +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 + +// Field: [7:6] DEAD_TIME_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 + +// Field: [5:3] DCDC_LOW_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 + +// Field: [2:0] DCDC_HIGH_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_LDO_TRIM +// +//***************************************************************************** +// Field: [28:24] VDDR_TRIM_SLEEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 + +// Field: [18:16] GLDO_CURSRC +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 + +// Field: [12:11] ITRIM_DIGLDO_LOAD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 + +// Field: [10:8] ITRIM_UDIGLDO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 + +// Field: [2:0] VTRIM_DELTA +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_BLE_0 +// +//***************************************************************************** +// Field: [31:0] ADDR_0_31 +// +// The first 32-bits of the 64-bit MAC BLE address +#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 +#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_BLE_1 +// +//***************************************************************************** +// Field: [31:0] ADDR_32_63 +// +// The last 32-bits of the 64-bit MAC BLE address +#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 +#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_15_4_0 +// +//***************************************************************************** +// Field: [31:0] ADDR_0_31 +// +// The first 32-bits of the 64-bit MAC 15.4 address +#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 +#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_15_4_1 +// +//***************************************************************************** +// Field: [31:0] ADDR_32_63 +// +// The last 32-bits of the 64-bit MAC 15.4 address +#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 +#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_OTP_DATA4 +// +//***************************************************************************** +// Field: [31] STANDBY_MODE_SEL_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 + +// Field: [30:29] STANDBY_PW_SEL_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 + +// Field: [28] DIS_STANDBY_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 + +// Field: [27] DIS_IDLE_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 + +// Field: [26:24] VIN_AT_X_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 + +// Field: [23] STANDBY_MODE_SEL_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 + +// Field: [22:21] STANDBY_PW_SEL_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 + +// Field: [20] DIS_STANDBY_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 + +// Field: [19] DIS_IDLE_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 + +// Field: [18:16] VIN_AT_X_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 + +// Field: [15] STANDBY_MODE_SEL_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 + +// Field: [14:13] STANDBY_PW_SEL_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 + +// Field: [12] DIS_STANDBY_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 + +// Field: [11] DIS_IDLE_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 + +// Field: [10:8] VIN_AT_X_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 + +// Field: [7] STANDBY_MODE_SEL_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 + +// Field: [6:5] STANDBY_PW_SEL_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 + +// Field: [4] DIS_STANDBY_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 + +// Field: [3] DIS_IDLE_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 + +// Field: [2:0] VIN_AT_X_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_TRIM +// +//***************************************************************************** +// Field: [16:12] TRIM_RECHARGE_COMP_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_W 5 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_M 0x0001F000 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_S 12 + +// Field: [11:8] TRIM_RECHARGE_COMP_REFLEVEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_W 4 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_M 0x00000F00 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_S 8 + +// Field: [7:0] TEMPVSLOPE +// +// Signed byte value representing the TEMP slope with battery voltage, in +// degrees C / V, with four fractional bits. +#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 +#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF +#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_RCOSC_HF_TEMPCOMP +// +//***************************************************************************** +// Field: [31:24] FINE_RESISTOR +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 + +// Field: [23:16] CTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 + +// Field: [15:8] CTRIMFRACT_QUAD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 + +// Field: [7:0] CTRIMFRACT_SLOPE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ICEPICK_DEVICE_ID +// +//***************************************************************************** +// Field: [31:28] PG_REV +// +// Field used to distinguish revisions of the device. +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 + +// Field: [27:12] WAFER_ID +// +// Field used to identify silicon die. +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 + +// Field: [11:0] MANUFACTURER_ID +// +// Manufacturer code. +// +// 0x02F: Texas Instruments +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FCFG1_REVISION +// +//***************************************************************************** +// Field: [31:0] REV +// +// The revision number of the FCFG1 layout. This value will be read by +// application SW in order to determine which FCFG1 parameters that have valid +// values. This revision number must be incremented by 1 before any devices are +// to be produced if the FCFG1 layout has changed since the previous production +// of devices. +// Value migth change without warning. +#define FCFG1_FCFG1_REVISION_REV_W 32 +#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF +#define FCFG1_FCFG1_REVISION_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_OTP_DATA +// +//***************************************************************************** +// Field: [31:28] RCOSC_HF_ITUNE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 + +// Field: [27:20] RCOSC_HF_CRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 + +// Field: [19:15] PER_M +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_PER_M_W 5 +#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 +#define FCFG1_MISC_OTP_DATA_PER_M_S 15 + +// Field: [14:12] PER_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_PER_E_W 3 +#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 +#define FCFG1_MISC_OTP_DATA_PER_E_S 12 + +//***************************************************************************** +// +// Register: FCFG1_O_IOCONF +// +//***************************************************************************** +// Field: [6:0] GPIO_CNT +// +// Number of available DIOs. +#define FCFG1_IOCONF_GPIO_CNT_W 7 +#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F +#define FCFG1_IOCONF_GPIO_CNT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_IF_ADC +// +//***************************************************************************** +// Field: [31:28] FF2ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 + +// Field: [27:24] FF3ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 + +// Field: [23:20] INT3ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 + +// Field: [19:16] FF1ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 + +// Field: [15:14] AAFCAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 + +// Field: [13:10] INT2ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 + +// Field: [9:5] IFDIGLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 + +// Field: [4:0] IFANALDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_OSC_TOP +// +//***************************************************************************** +// Field: [29:26] XOSC_HF_ROW_Q12 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 + +// Field: [25:10] XOSC_HF_COLUMN_Q12 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 + +// Field: [9:2] RCOSCLF_CTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 + +// Field: [1:0] RCOSCLF_RTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_ABS_GAIN +// +//***************************************************************************** +// Field: [15:0] SOC_ADC_ABS_GAIN_TEMP1 +// +// SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated +// in production test.. +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_REL_GAIN +// +//***************************************************************************** +// Field: [15:0] SOC_ADC_REL_GAIN_TEMP1 +// +// SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated +// in production test.. +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_OFFSET_INT +// +//***************************************************************************** +// Field: [23:16] SOC_ADC_REL_OFFSET_TEMP1 +// +// SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed +// 8-bit number. Calculated in production test.. +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 + +// Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1 +// +// SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed +// 8-bit number. Calculated in production test.. +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT +// +//***************************************************************************** +// Field: [5:0] SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_W \ + 6 +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_M \ + 0x0000003F +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S \ + 0 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_TH1 +// +//***************************************************************************** +// Field: [23:18] HPMRAMP3_LTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 + +// Field: [15:10] HPMRAMP3_HTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 + +// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 + +// Field: [5:0] HPMRAMP1_TH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_TH2 +// +//***************************************************************************** +// Field: [31:26] LPMUPDATE_LTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 + +// Field: [23:18] LPMUPDATE_HTM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 + +// Field: [15:10] ADC_COMP_AMPTH_LPM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 + +// Field: [7:2] ADC_COMP_AMPTH_HPM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_CTRL1 +// +//***************************************************************************** +// Field: [30] AMPCOMP_REQ_MODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 + +// Field: [23:20] IBIAS_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 + +// Field: [19:16] IBIAS_INIT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 + +// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 + +// Field: [7:4] CAP_STEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 + +// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ANABYPASS_VALUE2 +// +//***************************************************************************** +// Field: [13:0] XOSC_HF_IBIASTHERM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_VOLT_TRIM +// +//***************************************************************************** +// Field: [28:24] VDDR_TRIM_HH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 + +// Field: [20:16] VDDR_TRIM_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 + +// Field: [12:8] VDDR_TRIM_SLEEP_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 + +// Field: [4:0] TRIMBOD_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 +#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F +#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_OSC_CONF +// +//***************************************************************************** +// Field: [29] ADC_SH_VBUF_EN +// +// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 + +// Field: [28] ADC_SH_MODE_EN +// +// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 + +// Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM +// +// Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 + +// Field: [26:25] XOSCLF_REGULATOR_TRIM +// +// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 + +// Field: [24:21] XOSCLF_CMIRRWR_RATIO +// +// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 + +// Field: [20:19] XOSC_HF_FAST_START +// +// Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 + +// Field: [18] XOSC_OPTION +// +// 0: XOSC_HF unavailable (may not be bonded out) +// 1: XOSC_HF available (default) +#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 +#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_S 18 + +// Field: [17] HPOSC_OPTION +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 +#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 + +// Field: [16] HPOSC_BIAS_HOLD_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 + +// Field: [15:12] HPOSC_CURRMIRR_RATIO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 + +// Field: [11:8] HPOSC_BIAS_RES_SET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 + +// Field: [7] HPOSC_FILTER_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 + +// Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 + +// Field: [2:1] HPOSC_SERIES_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 + +// Field: [0] HPOSC_DIV3_BYPASS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FREQ_OFFSET +// +//***************************************************************************** +// Field: [31:16] HPOSC_COMP_P0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 + +// Field: [15:8] HPOSC_COMP_P1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 + +// Field: [7:0] HPOSC_COMP_P2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_OTP_DATA_1 +// +//***************************************************************************** +// Field: [28:27] PEAK_DET_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 + +// Field: [26:24] HP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 + +// Field: [23:22] LP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 + +// Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 + +// Field: [19:10] HPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 + +// Field: [9:4] LPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 + +// Field: [3:0] IDAC_STEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_0 +// +//***************************************************************************** +// Field: [31:0] ID_31_0 +// +// Shadow of DIE_ID_0 register in eFuse row number 5 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_1 +// +//***************************************************************************** +// Field: [31:0] ID_63_32 +// +// Shadow of DIE_ID_1 register in eFuse row number 6 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_2 +// +//***************************************************************************** +// Field: [31:0] ID_95_64 +// +// Shadow of DIE_ID_2 register in eFuse row number 7 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_3 +// +//***************************************************************************** +// Field: [31:0] ID_127_96 +// +// Shadow of DIE_ID_3 register in eFuse row number 8 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM +// +//***************************************************************************** +// Field: [26:23] TRIMMAG +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 + +// Field: [22:18] TRIMIREF +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 + +// Field: [17:16] ITRIM_DIG_LDO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 + +// Field: [15:12] VTRIM_DIG +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 + +// Field: [11:8] VTRIM_COARSE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 + +// Field: [7:0] RCOSCHF_CTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_ANA_TRIM +// +//***************************************************************************** +// Field: [30] ALT_VDDR_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM 0x40000000 +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_BITN 30 +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_M 0x40000000 +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_S 30 + +// Field: [29] DET_LOGIC_DIS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS 0x20000000 +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_BITN 29 +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_M 0x20000000 +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_S 29 + +// Field: [28:27] BOD_BANDGAP_TRIM_CNF_EXT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_W 2 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_M 0x18000000 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_S 27 + +// Field: [26:25] BOD_BANDGAP_TRIM_CNF +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 + +// Field: [24] VDDR_ENABLE_PG1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 + +// Field: [23] VDDR_OK_HYS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 + +// Field: [22:21] IPTAT_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 + +// Field: [20:16] VDDR_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 + +// Field: [15:11] TRIMBOD_INTMODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 + +// Field: [10:6] TRIMBOD_EXTMODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 + +// Field: [5:0] TRIMTEMP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_DAC_BIAS_CNF +// +//***************************************************************************** +// Field: [17:12] LPM_TRIM_IOUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_W 6 +#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M 0x0003F000 +#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S 12 + +// Field: [11:9] LPM_BIAS_WIDTH_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_W 3 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M 0x00000E00 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S 9 + +// Field: [8] LPM_BIAS_BACKUP_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN 0x00000100 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_BITN 8 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_M 0x00000100 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_S 8 + +//***************************************************************************** +// +// Register: FCFG1_O_TFW_PROBE +// +//***************************************************************************** +// Field: [31:0] REV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_TFW_PROBE_REV_W 32 +#define FCFG1_TFW_PROBE_REV_M 0xFFFFFFFF +#define FCFG1_TFW_PROBE_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_TFW_FT +// +//***************************************************************************** +// Field: [31:0] REV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_TFW_FT_REV_W 32 +#define FCFG1_TFW_FT_REV_M 0xFFFFFFFF +#define FCFG1_TFW_FT_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_DAC_CAL0 +// +//***************************************************************************** +// Field: [31:16] SOC_DAC_VOUT_CAL_DECOUPLE_C2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_W 16 +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_M 0xFFFF0000 +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_S 16 + +// Field: [15:0] SOC_DAC_VOUT_CAL_DECOUPLE_C1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_W 16 +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_M 0x0000FFFF +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_DAC_CAL1 +// +//***************************************************************************** +// Field: [31:16] SOC_DAC_VOUT_CAL_PRECH_C2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_W 16 +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_M 0xFFFF0000 +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_S 16 + +// Field: [15:0] SOC_DAC_VOUT_CAL_PRECH_C1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_W 16 +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_M 0x0000FFFF +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_DAC_CAL2 +// +//***************************************************************************** +// Field: [31:16] SOC_DAC_VOUT_CAL_ADCREF_C2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_W 16 +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_M 0xFFFF0000 +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_S 16 + +// Field: [15:0] SOC_DAC_VOUT_CAL_ADCREF_C1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_W 16 +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_M 0x0000FFFF +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_DAC_CAL3 +// +//***************************************************************************** +// Field: [31:16] SOC_DAC_VOUT_CAL_VDDS_C2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_W 16 +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_M 0xFFFF0000 +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_S 16 + +// Field: [15:0] SOC_DAC_VOUT_CAL_VDDS_C1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_W 16 +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_M 0x0000FFFF +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_S 0 + + +#endif // __FCFG1__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_flash.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_flash.h new file mode 100644 index 0000000..cfc45cb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_flash.h @@ -0,0 +1,3498 @@ +/****************************************************************************** +* Filename: hw_flash_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// FLASH component +// +//***************************************************************************** +// FMC and Efuse Status +#define FLASH_O_STAT 0x0000001C + +// Internal +#define FLASH_O_CFG 0x00000024 + +// Internal +#define FLASH_O_SYSCODE_START 0x00000028 + +// Internal +#define FLASH_O_FLASH_SIZE 0x0000002C + +// Internal +#define FLASH_O_FWLOCK 0x0000003C + +// Internal +#define FLASH_O_FWFLAG 0x00000040 + +// Internal +#define FLASH_O_EFUSE 0x00001000 + +// Internal +#define FLASH_O_EFUSEADDR 0x00001004 + +// Internal +#define FLASH_O_DATAUPPER 0x00001008 + +// Internal +#define FLASH_O_DATALOWER 0x0000100C + +// Internal +#define FLASH_O_EFUSECFG 0x00001010 + +// Internal +#define FLASH_O_EFUSESTAT 0x00001014 + +// Internal +#define FLASH_O_ACC 0x00001018 + +// Internal +#define FLASH_O_BOUNDARY 0x0000101C + +// Internal +#define FLASH_O_EFUSEFLAG 0x00001020 + +// Internal +#define FLASH_O_EFUSEKEY 0x00001024 + +// Internal +#define FLASH_O_EFUSERELEASE 0x00001028 + +// Internal +#define FLASH_O_EFUSEPINS 0x0000102C + +// Internal +#define FLASH_O_EFUSECRA 0x00001030 + +// Internal +#define FLASH_O_EFUSEREAD 0x00001034 + +// Internal +#define FLASH_O_EFUSEPROGRAM 0x00001038 + +// Internal +#define FLASH_O_EFUSEERROR 0x0000103C + +// Internal +#define FLASH_O_SINGLEBIT 0x00001040 + +// Internal +#define FLASH_O_TWOBIT 0x00001044 + +// Internal +#define FLASH_O_SELFTESTCYC 0x00001048 + +// Internal +#define FLASH_O_SELFTESTSIGN 0x0000104C + +// Internal +#define FLASH_O_FRDCTL 0x00002000 + +// Internal +#define FLASH_O_FSPRD 0x00002004 + +// Internal +#define FLASH_O_FEDACCTL1 0x00002008 + +// Internal +#define FLASH_O_FEDACSTAT 0x0000201C + +// Internal +#define FLASH_O_FBPROT 0x00002030 + +// Internal +#define FLASH_O_FBSE 0x00002034 + +// Internal +#define FLASH_O_FBBUSY 0x00002038 + +// Internal +#define FLASH_O_FBAC 0x0000203C + +// Internal +#define FLASH_O_FBFALLBACK 0x00002040 + +// Internal +#define FLASH_O_FBPRDY 0x00002044 + +// Internal +#define FLASH_O_FPAC1 0x00002048 + +// Internal +#define FLASH_O_FPAC2 0x0000204C + +// Internal +#define FLASH_O_FMAC 0x00002050 + +// Internal +#define FLASH_O_FMSTAT 0x00002054 + +// Internal +#define FLASH_O_FLOCK 0x00002064 + +// Internal +#define FLASH_O_FVREADCT 0x00002080 + +// Internal +#define FLASH_O_FVHVCT1 0x00002084 + +// Internal +#define FLASH_O_FVHVCT2 0x00002088 + +// Internal +#define FLASH_O_FVHVCT3 0x0000208C + +// Internal +#define FLASH_O_FVNVCT 0x00002090 + +// Internal +#define FLASH_O_FVSLP 0x00002094 + +// Internal +#define FLASH_O_FVWLCT 0x00002098 + +// Internal +#define FLASH_O_FEFUSECTL 0x0000209C + +// Internal +#define FLASH_O_FEFUSESTAT 0x000020A0 + +// Internal +#define FLASH_O_FEFUSEDATA 0x000020A4 + +// Internal +#define FLASH_O_FSEQPMP 0x000020A8 + +// Internal +#define FLASH_O_FBSTROBES 0x00002100 + +// Internal +#define FLASH_O_FPSTROBES 0x00002104 + +// Internal +#define FLASH_O_FBMODE 0x00002108 + +// Internal +#define FLASH_O_FTCR 0x0000210C + +// Internal +#define FLASH_O_FADDR 0x00002110 + +// Internal +#define FLASH_O_FTCTL 0x0000211C + +// Internal +#define FLASH_O_FWPWRITE0 0x00002120 + +// Internal +#define FLASH_O_FWPWRITE1 0x00002124 + +// Internal +#define FLASH_O_FWPWRITE2 0x00002128 + +// Internal +#define FLASH_O_FWPWRITE3 0x0000212C + +// Internal +#define FLASH_O_FWPWRITE4 0x00002130 + +// Internal +#define FLASH_O_FWPWRITE5 0x00002134 + +// Internal +#define FLASH_O_FWPWRITE6 0x00002138 + +// Internal +#define FLASH_O_FWPWRITE7 0x0000213C + +// Internal +#define FLASH_O_FWPWRITE_ECC 0x00002140 + +// Internal +#define FLASH_O_FSWSTAT 0x00002144 + +// Internal +#define FLASH_O_FSM_GLBCTL 0x00002200 + +// Internal +#define FLASH_O_FSM_STATE 0x00002204 + +// Internal +#define FLASH_O_FSM_STAT 0x00002208 + +// Internal +#define FLASH_O_FSM_CMD 0x0000220C + +// Internal +#define FLASH_O_FSM_PE_OSU 0x00002210 + +// Internal +#define FLASH_O_FSM_VSTAT 0x00002214 + +// Internal +#define FLASH_O_FSM_PE_VSU 0x00002218 + +// Internal +#define FLASH_O_FSM_CMP_VSU 0x0000221C + +// Internal +#define FLASH_O_FSM_EX_VAL 0x00002220 + +// Internal +#define FLASH_O_FSM_RD_H 0x00002224 + +// Internal +#define FLASH_O_FSM_P_OH 0x00002228 + +// Internal +#define FLASH_O_FSM_ERA_OH 0x0000222C + +// Internal +#define FLASH_O_FSM_SAV_PPUL 0x00002230 + +// Internal +#define FLASH_O_FSM_PE_VH 0x00002234 + +// Internal +#define FLASH_O_FSM_PRG_PW 0x00002240 + +// Internal +#define FLASH_O_FSM_ERA_PW 0x00002244 + +// Internal +#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254 + +// Internal +#define FLASH_O_FSM_TIMER 0x00002258 + +// Internal +#define FLASH_O_FSM_MODE 0x0000225C + +// Internal +#define FLASH_O_FSM_PGM 0x00002260 + +// Internal +#define FLASH_O_FSM_ERA 0x00002264 + +// Internal +#define FLASH_O_FSM_PRG_PUL 0x00002268 + +// Internal +#define FLASH_O_FSM_ERA_PUL 0x0000226C + +// Internal +#define FLASH_O_FSM_STEP_SIZE 0x00002270 + +// Internal +#define FLASH_O_FSM_PUL_CNTR 0x00002274 + +// Internal +#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 + +// Internal +#define FLASH_O_FSM_ST_MACHINE 0x0000227C + +// Internal +#define FLASH_O_FSM_FLES 0x00002280 + +// Internal +#define FLASH_O_FSM_WR_ENA 0x00002288 + +// Internal +#define FLASH_O_FSM_ACC_PP 0x0000228C + +// Internal +#define FLASH_O_FSM_ACC_EP 0x00002290 + +// Internal +#define FLASH_O_FSM_ADDR 0x000022A0 + +// Internal +#define FLASH_O_FSM_SECTOR 0x000022A4 + +// Internal +#define FLASH_O_FMC_REV_ID 0x000022A8 + +// Internal +#define FLASH_O_FSM_ERR_ADDR 0x000022AC + +// Internal +#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0 + +// Internal +#define FLASH_O_FSM_EXECUTE 0x000022B4 + +// Internal +#define FLASH_O_FSM_SECTOR1 0x000022C0 + +// Internal +#define FLASH_O_FSM_SECTOR2 0x000022C4 + +// Internal +#define FLASH_O_FSM_BSLE0 0x000022E0 + +// Internal +#define FLASH_O_FSM_BSLE1 0x000022E4 + +// Internal +#define FLASH_O_FSM_BSLP0 0x000022F0 + +// Internal +#define FLASH_O_FSM_BSLP1 0x000022F4 + +// FMC FSM Enable 128-bit Wide Programming +#define FLASH_O_FSM_PGM128 0x000022F8 + +// Internal +#define FLASH_O_FCFG_BANK 0x00002400 + +// Internal +#define FLASH_O_FCFG_WRAPPER 0x00002404 + +// Internal +#define FLASH_O_FCFG_BNK_TYPE 0x00002408 + +// Internal +#define FLASH_O_FCFG_B0_START 0x00002410 + +// Internal +#define FLASH_O_FCFG_B1_START 0x00002414 + +// Internal +#define FLASH_O_FCFG_B2_START 0x00002418 + +// Internal +#define FLASH_O_FCFG_B3_START 0x0000241C + +// Internal +#define FLASH_O_FCFG_B4_START 0x00002420 + +// Internal +#define FLASH_O_FCFG_B5_START 0x00002424 + +// Internal +#define FLASH_O_FCFG_B6_START 0x00002428 + +// Internal +#define FLASH_O_FCFG_B7_START 0x0000242C + +// Internal +#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 + +//***************************************************************************** +// +// Register: FLASH_O_STAT +// +//***************************************************************************** +// Field: [15] EFUSE_BLANK +// +// Efuse scanning detected if fuse ROM is blank: +// 0 : Not blank +// 1 : Blank +#define FLASH_STAT_EFUSE_BLANK 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_BITN 15 +#define FLASH_STAT_EFUSE_BLANK_M 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_S 15 + +// Field: [14] EFUSE_TIMEOUT +// +// Efuse scanning resulted in timeout error. +// 0 : No Timeout error +// 1 : Timeout Error +#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14 +#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_S 14 + +// Field: [13] SPRS_BYTE_NOT_OK +// +// Efuse scanning resulted in scan chain Sparse byte error. +// 0 : No Sparse error +// 1 : Sparse Error +#define FLASH_STAT_SPRS_BYTE_NOT_OK 0x00002000 +#define FLASH_STAT_SPRS_BYTE_NOT_OK_BITN 13 +#define FLASH_STAT_SPRS_BYTE_NOT_OK_M 0x00002000 +#define FLASH_STAT_SPRS_BYTE_NOT_OK_S 13 + +// Field: [12:8] EFUSE_ERRCODE +// +// Same as EFUSEERROR.CODE +#define FLASH_STAT_EFUSE_ERRCODE_W 5 +#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00 +#define FLASH_STAT_EFUSE_ERRCODE_S 8 + +// Field: [2] SAMHOLD_DIS +// +// Status indicator of flash sample and hold sequencing logic. This bit will go +// to 1 some delay after CFG.DIS_IDLE is set to 1. +// 0: Not disabled +// 1: Sample and hold disabled and stable +#define FLASH_STAT_SAMHOLD_DIS 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_BITN 2 +#define FLASH_STAT_SAMHOLD_DIS_M 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_S 2 + +// Field: [1] BUSY +// +// Fast version of the FMC FMSTAT.BUSY bit. +// This flag is valid immediately after the operation setting it (FMSTAT.BUSY +// is delayed some cycles) +// 0 : Not busy +// 1 : Busy +#define FLASH_STAT_BUSY 0x00000002 +#define FLASH_STAT_BUSY_BITN 1 +#define FLASH_STAT_BUSY_M 0x00000002 +#define FLASH_STAT_BUSY_S 1 + +// Field: [0] POWER_MODE +// +// Power state of the flash sub-system. +// 0 : Active +// 1 : Low power +#define FLASH_STAT_POWER_MODE 0x00000001 +#define FLASH_STAT_POWER_MODE_BITN 0 +#define FLASH_STAT_POWER_MODE_M 0x00000001 +#define FLASH_STAT_POWER_MODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_CFG +// +//***************************************************************************** +// Field: [8] STANDBY_MODE_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8 +#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_S 8 + +// Field: [7:6] STANDBY_PW_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_STANDBY_PW_SEL_W 2 +#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 +#define FLASH_CFG_STANDBY_PW_SEL_S 6 + +// Field: [5] DIS_EFUSECLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_EFUSECLK 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_BITN 5 +#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_S 5 + +// Field: [4] DIS_READACCESS +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_READACCESS 0x00000010 +#define FLASH_CFG_DIS_READACCESS_BITN 4 +#define FLASH_CFG_DIS_READACCESS_M 0x00000010 +#define FLASH_CFG_DIS_READACCESS_S 4 + +// Field: [3] ENABLE_SWINTF +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_ENABLE_SWINTF 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_BITN 3 +#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_S 3 + +// Field: [1] DIS_STANDBY +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_STANDBY 0x00000002 +#define FLASH_CFG_DIS_STANDBY_BITN 1 +#define FLASH_CFG_DIS_STANDBY_M 0x00000002 +#define FLASH_CFG_DIS_STANDBY_S 1 + +// Field: [0] DIS_IDLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_IDLE 0x00000001 +#define FLASH_CFG_DIS_IDLE_BITN 0 +#define FLASH_CFG_DIS_IDLE_M 0x00000001 +#define FLASH_CFG_DIS_IDLE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SYSCODE_START +// +//***************************************************************************** +// Field: [5:0] SYSCODE_START +// +// Internal. Only to be used through TI provided API. +#define FLASH_SYSCODE_START_SYSCODE_START_W 6 +#define FLASH_SYSCODE_START_SYSCODE_START_M 0x0000003F +#define FLASH_SYSCODE_START_SYSCODE_START_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FLASH_SIZE +// +//***************************************************************************** +// Field: [7:0] SECTORS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FLASH_SIZE_SECTORS_W 8 +#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF +#define FLASH_FLASH_SIZE_SECTORS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWLOCK +// +//***************************************************************************** +// Field: [2:0] FWLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWLOCK_FWLOCK_W 3 +#define FLASH_FWLOCK_FWLOCK_M 0x00000007 +#define FLASH_FWLOCK_FWLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWFLAG +// +//***************************************************************************** +// Field: [2:0] FWFLAG +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWFLAG_FWFLAG_W 3 +#define FLASH_FWFLAG_FWFLAG_M 0x00000007 +#define FLASH_FWFLAG_FWFLAG_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSE +// +//***************************************************************************** +// Field: [28:24] INSTRUCTION +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSE_INSTRUCTION_W 5 +#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000 +#define FLASH_EFUSE_INSTRUCTION_S 24 + +// Field: [15:0] DUMPWORD +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSE_DUMPWORD_W 16 +#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF +#define FLASH_EFUSE_DUMPWORD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEADDR +// +//***************************************************************************** +// Field: [15:11] BLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEADDR_BLOCK_W 5 +#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800 +#define FLASH_EFUSEADDR_BLOCK_S 11 + +// Field: [10:0] ROW +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEADDR_ROW_W 11 +#define FLASH_EFUSEADDR_ROW_M 0x000007FF +#define FLASH_EFUSEADDR_ROW_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_DATAUPPER +// +//***************************************************************************** +// Field: [7:3] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_SPARE_W 5 +#define FLASH_DATAUPPER_SPARE_M 0x000000F8 +#define FLASH_DATAUPPER_SPARE_S 3 + +// Field: [2] P +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_P 0x00000004 +#define FLASH_DATAUPPER_P_BITN 2 +#define FLASH_DATAUPPER_P_M 0x00000004 +#define FLASH_DATAUPPER_P_S 2 + +// Field: [1] R +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_R 0x00000002 +#define FLASH_DATAUPPER_R_BITN 1 +#define FLASH_DATAUPPER_R_M 0x00000002 +#define FLASH_DATAUPPER_R_S 1 + +// Field: [0] EEN +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_EEN 0x00000001 +#define FLASH_DATAUPPER_EEN_BITN 0 +#define FLASH_DATAUPPER_EEN_M 0x00000001 +#define FLASH_DATAUPPER_EEN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_DATALOWER +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATALOWER_DATA_W 32 +#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF +#define FLASH_DATALOWER_DATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSECFG +// +//***************************************************************************** +// Field: [8] IDLEGATING +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_IDLEGATING 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_BITN 8 +#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_S 8 + +// Field: [4:3] SLAVEPOWER +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_SLAVEPOWER_W 2 +#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018 +#define FLASH_EFUSECFG_SLAVEPOWER_S 3 + +// Field: [0] GATING +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_GATING 0x00000001 +#define FLASH_EFUSECFG_GATING_BITN 0 +#define FLASH_EFUSECFG_GATING_M 0x00000001 +#define FLASH_EFUSECFG_GATING_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSESTAT +// +//***************************************************************************** +// Field: [0] RESETDONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSESTAT_RESETDONE 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_BITN 0 +#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_ACC +// +//***************************************************************************** +// Field: [23:0] ACCUMULATOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_ACC_ACCUMULATOR_W 24 +#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF +#define FLASH_ACC_ACCUMULATOR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_BOUNDARY +// +//***************************************************************************** +// Field: [23] DISROW0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_DISROW0 0x00800000 +#define FLASH_BOUNDARY_DISROW0_BITN 23 +#define FLASH_BOUNDARY_DISROW0_M 0x00800000 +#define FLASH_BOUNDARY_DISROW0_S 23 + +// Field: [22] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SPARE 0x00400000 +#define FLASH_BOUNDARY_SPARE_BITN 22 +#define FLASH_BOUNDARY_SPARE_M 0x00400000 +#define FLASH_BOUNDARY_SPARE_S 22 + +// Field: [21] EFC_SELF_TEST_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21 + +// Field: [20] EFC_INSTRUCTION_INFO +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20 + +// Field: [19] EFC_INSTRUCTION_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19 + +// Field: [18] EFC_AUTOLOAD_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18 + +// Field: [17:14] OUTPUTENABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_OUTPUTENABLE_W 4 +#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000 +#define FLASH_BOUNDARY_OUTPUTENABLE_S 14 + +// Field: [13] SYS_ECC_SELF_TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13 + +// Field: [12] SYS_ECC_OVERRIDE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12 + +// Field: [11] EFC_FDI +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_FDI 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_BITN 11 +#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_S 11 + +// Field: [10] SYS_DIEID_AUTOLOAD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10 + +// Field: [9:8] SYS_REPAIR_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8 + +// Field: [7:4] SYS_WS_READ_STATES +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4 + +// Field: [3:0] INPUTENABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_INPUTENABLE_W 4 +#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F +#define FLASH_BOUNDARY_INPUTENABLE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEFLAG +// +//***************************************************************************** +// Field: [0] KEY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEFLAG_KEY 0x00000001 +#define FLASH_EFUSEFLAG_KEY_BITN 0 +#define FLASH_EFUSEFLAG_KEY_M 0x00000001 +#define FLASH_EFUSEFLAG_KEY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEKEY +// +//***************************************************************************** +// Field: [31:0] CODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEKEY_CODE_W 32 +#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF +#define FLASH_EFUSEKEY_CODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSERELEASE +// +//***************************************************************************** +// Field: [31:25] ODPYEAR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPYEAR_W 7 +#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000 +#define FLASH_EFUSERELEASE_ODPYEAR_S 25 + +// Field: [24:21] ODPMONTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPMONTH_W 4 +#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000 +#define FLASH_EFUSERELEASE_ODPMONTH_S 21 + +// Field: [20:16] ODPDAY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPDAY_W 5 +#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000 +#define FLASH_EFUSERELEASE_ODPDAY_S 16 + +// Field: [15:9] EFUSEYEAR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7 +#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00 +#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9 + +// Field: [8:5] EFUSEMONTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4 +#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0 +#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5 + +// Field: [4:0] EFUSEDAY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEDAY_W 5 +#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F +#define FLASH_EFUSERELEASE_EFUSEDAY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEPINS +// +//***************************************************************************** +// Field: [15] EFC_SELF_TEST_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15 + +// Field: [14] EFC_SELF_TEST_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14 + +// Field: [13] SYS_ECC_SELF_TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13 + +// Field: [12] EFC_INSTRUCTION_INFO +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12 + +// Field: [11] EFC_INSTRUCTION_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11 + +// Field: [10] EFC_AUTOLOAD_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10 + +// Field: [9] SYS_ECC_OVERRIDE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9 + +// Field: [8] EFC_READY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_READY 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_BITN 8 +#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_S 8 + +// Field: [7] EFC_FCLRZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7 +#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7 + +// Field: [6] SYS_DIEID_AUTOLOAD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6 + +// Field: [5:4] SYS_REPAIR_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4 + +// Field: [3:0] SYS_WS_READ_STATES +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4 +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSECRA +// +//***************************************************************************** +// Field: [5:0] DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECRA_DATA_W 6 +#define FLASH_EFUSECRA_DATA_M 0x0000003F +#define FLASH_EFUSECRA_DATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEREAD +// +//***************************************************************************** +// Field: [9:8] DATABIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_DATABIT_W 2 +#define FLASH_EFUSEREAD_DATABIT_M 0x00000300 +#define FLASH_EFUSEREAD_DATABIT_S 8 + +// Field: [7:4] READCLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_READCLOCK_W 4 +#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0 +#define FLASH_EFUSEREAD_READCLOCK_S 4 + +// Field: [3] DEBUG +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_DEBUG 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_BITN 3 +#define FLASH_EFUSEREAD_DEBUG_M 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_S 3 + +// Field: [2] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_SPARE 0x00000004 +#define FLASH_EFUSEREAD_SPARE_BITN 2 +#define FLASH_EFUSEREAD_SPARE_M 0x00000004 +#define FLASH_EFUSEREAD_SPARE_S 2 + +// Field: [1:0] MARGIN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_MARGIN_W 2 +#define FLASH_EFUSEREAD_MARGIN_M 0x00000003 +#define FLASH_EFUSEREAD_MARGIN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEPROGRAM +// +//***************************************************************************** +// Field: [30] COMPAREDISABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30 + +// Field: [29:14] CLOCKSTALL +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14 + +// Field: [13] VPPTOVDD +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13 + +// Field: [12:9] ITERATIONS +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4 +#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00 +#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9 + +// Field: [8:0] WRITECLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9 +#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF +#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEERROR +// +//***************************************************************************** +// Field: [5] DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEERROR_DONE 0x00000020 +#define FLASH_EFUSEERROR_DONE_BITN 5 +#define FLASH_EFUSEERROR_DONE_M 0x00000020 +#define FLASH_EFUSEERROR_DONE_S 5 + +// Field: [4:0] CODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEERROR_CODE_W 5 +#define FLASH_EFUSEERROR_CODE_M 0x0000001F +#define FLASH_EFUSEERROR_CODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SINGLEBIT +// +//***************************************************************************** +// Field: [31:1] FROMN +// +// Internal. Only to be used through TI provided API. +#define FLASH_SINGLEBIT_FROMN_W 31 +#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE +#define FLASH_SINGLEBIT_FROMN_S 1 + +// Field: [0] FROM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_SINGLEBIT_FROM0 0x00000001 +#define FLASH_SINGLEBIT_FROM0_BITN 0 +#define FLASH_SINGLEBIT_FROM0_M 0x00000001 +#define FLASH_SINGLEBIT_FROM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_TWOBIT +// +//***************************************************************************** +// Field: [31:1] FROMN +// +// Internal. Only to be used through TI provided API. +#define FLASH_TWOBIT_FROMN_W 31 +#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE +#define FLASH_TWOBIT_FROMN_S 1 + +// Field: [0] FROM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_TWOBIT_FROM0 0x00000001 +#define FLASH_TWOBIT_FROM0_BITN 0 +#define FLASH_TWOBIT_FROM0_M 0x00000001 +#define FLASH_TWOBIT_FROM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SELFTESTCYC +// +//***************************************************************************** +// Field: [31:0] CYCLES +// +// Internal. Only to be used through TI provided API. +#define FLASH_SELFTESTCYC_CYCLES_W 32 +#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF +#define FLASH_SELFTESTCYC_CYCLES_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SELFTESTSIGN +// +//***************************************************************************** +// Field: [31:0] SIGNATURE +// +// Internal. Only to be used through TI provided API. +#define FLASH_SELFTESTSIGN_SIGNATURE_W 32 +#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF +#define FLASH_SELFTESTSIGN_SIGNATURE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FRDCTL +// +//***************************************************************************** +// Field: [11:8] RWAIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FRDCTL_RWAIT_W 4 +#define FLASH_FRDCTL_RWAIT_M 0x00000F00 +#define FLASH_FRDCTL_RWAIT_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSPRD +// +//***************************************************************************** +// Field: [15:8] RMBSEM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RMBSEM_W 8 +#define FLASH_FSPRD_RMBSEM_M 0x0000FF00 +#define FLASH_FSPRD_RMBSEM_S 8 + +// Field: [1] RM1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RM1 0x00000002 +#define FLASH_FSPRD_RM1_BITN 1 +#define FLASH_FSPRD_RM1_M 0x00000002 +#define FLASH_FSPRD_RM1_S 1 + +// Field: [0] RM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RM0 0x00000001 +#define FLASH_FSPRD_RM0_BITN 0 +#define FLASH_FSPRD_RM0_M 0x00000001 +#define FLASH_FSPRD_RM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEDACCTL1 +// +//***************************************************************************** +// Field: [24] SUSP_IGNR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24 +#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_S 24 + +//***************************************************************************** +// +// Register: FLASH_O_FEDACSTAT +// +//***************************************************************************** +// Field: [25] RVF_INT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACSTAT_RVF_INT 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_BITN 25 +#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_S 25 + +// Field: [24] FSM_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACSTAT_FSM_DONE 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_BITN 24 +#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_S 24 + +//***************************************************************************** +// +// Register: FLASH_O_FBPROT +// +//***************************************************************************** +// Field: [0] PROTL1DIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPROT_PROTL1DIS 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_BITN 0 +#define FLASH_FBPROT_PROTL1DIS_M 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBSE +// +//***************************************************************************** +// Field: [15:0] BSE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSE_BSE_W 16 +#define FLASH_FBSE_BSE_M 0x0000FFFF +#define FLASH_FBSE_BSE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBBUSY +// +//***************************************************************************** +// Field: [7:0] BUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBBUSY_BUSY_W 8 +#define FLASH_FBBUSY_BUSY_M 0x000000FF +#define FLASH_FBBUSY_BUSY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBAC +// +//***************************************************************************** +// Field: [16] OTPPROTDIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_OTPPROTDIS 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_BITN 16 +#define FLASH_FBAC_OTPPROTDIS_M 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_S 16 + +// Field: [15:8] BAGP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_BAGP_W 8 +#define FLASH_FBAC_BAGP_M 0x0000FF00 +#define FLASH_FBAC_BAGP_S 8 + +// Field: [7:0] VREADS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_VREADS_W 8 +#define FLASH_FBAC_VREADS_M 0x000000FF +#define FLASH_FBAC_VREADS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBFALLBACK +// +//***************************************************************************** +// Field: [27:24] FSM_PWRSAV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4 +#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000 +#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24 + +// Field: [19:16] REG_PWRSAV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_REG_PWRSAV_W 4 +#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000 +#define FLASH_FBFALLBACK_REG_PWRSAV_S 16 + +// Field: [15:14] BANKPWR7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR7_W 2 +#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000 +#define FLASH_FBFALLBACK_BANKPWR7_S 14 + +// Field: [13:12] BANKPWR6 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR6_W 2 +#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000 +#define FLASH_FBFALLBACK_BANKPWR6_S 12 + +// Field: [11:10] BANKPWR5 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR5_W 2 +#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00 +#define FLASH_FBFALLBACK_BANKPWR5_S 10 + +// Field: [9:8] BANKPWR4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR4_W 2 +#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300 +#define FLASH_FBFALLBACK_BANKPWR4_S 8 + +// Field: [7:6] BANKPWR3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR3_W 2 +#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0 +#define FLASH_FBFALLBACK_BANKPWR3_S 6 + +// Field: [5:4] BANKPWR2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR2_W 2 +#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030 +#define FLASH_FBFALLBACK_BANKPWR2_S 4 + +// Field: [3:2] BANKPWR1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR1_W 2 +#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C +#define FLASH_FBFALLBACK_BANKPWR1_S 2 + +// Field: [1:0] BANKPWR0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR0_W 2 +#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003 +#define FLASH_FBFALLBACK_BANKPWR0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBPRDY +// +//***************************************************************************** +// Field: [16] BANKBUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_BANKBUSY 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_BITN 16 +#define FLASH_FBPRDY_BANKBUSY_M 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_S 16 + +// Field: [15] PUMPRDY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_PUMPRDY 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_BITN 15 +#define FLASH_FBPRDY_PUMPRDY_M 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_S 15 + +// Field: [0] BANKRDY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_BANKRDY 0x00000001 +#define FLASH_FBPRDY_BANKRDY_BITN 0 +#define FLASH_FBPRDY_BANKRDY_M 0x00000001 +#define FLASH_FBPRDY_BANKRDY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FPAC1 +// +//***************************************************************************** +// Field: [27:16] PSLEEPTDIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PSLEEPTDIS_W 12 +#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000 +#define FLASH_FPAC1_PSLEEPTDIS_S 16 + +// Field: [15:4] PUMPRESET_PW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PUMPRESET_PW_W 12 +#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0 +#define FLASH_FPAC1_PUMPRESET_PW_S 4 + +// Field: [1:0] PUMPPWR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PUMPPWR_W 2 +#define FLASH_FPAC1_PUMPPWR_M 0x00000003 +#define FLASH_FPAC1_PUMPPWR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FPAC2 +// +//***************************************************************************** +// Field: [15:0] PAGP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC2_PAGP_W 16 +#define FLASH_FPAC2_PAGP_M 0x0000FFFF +#define FLASH_FPAC2_PAGP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMAC +// +//***************************************************************************** +// Field: [2:0] BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMAC_BANK_W 3 +#define FLASH_FMAC_BANK_M 0x00000007 +#define FLASH_FMAC_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMSTAT +// +//***************************************************************************** +// Field: [17] RVSUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RVSUSP 0x00020000 +#define FLASH_FMSTAT_RVSUSP_BITN 17 +#define FLASH_FMSTAT_RVSUSP_M 0x00020000 +#define FLASH_FMSTAT_RVSUSP_S 17 + +// Field: [16] RDVER +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RDVER 0x00010000 +#define FLASH_FMSTAT_RDVER_BITN 16 +#define FLASH_FMSTAT_RDVER_M 0x00010000 +#define FLASH_FMSTAT_RDVER_S 16 + +// Field: [15] RVF +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RVF 0x00008000 +#define FLASH_FMSTAT_RVF_BITN 15 +#define FLASH_FMSTAT_RVF_M 0x00008000 +#define FLASH_FMSTAT_RVF_S 15 + +// Field: [14] ILA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ILA 0x00004000 +#define FLASH_FMSTAT_ILA_BITN 14 +#define FLASH_FMSTAT_ILA_M 0x00004000 +#define FLASH_FMSTAT_ILA_S 14 + +// Field: [13] DBF +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_DBF 0x00002000 +#define FLASH_FMSTAT_DBF_BITN 13 +#define FLASH_FMSTAT_DBF_M 0x00002000 +#define FLASH_FMSTAT_DBF_S 13 + +// Field: [12] PGV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PGV 0x00001000 +#define FLASH_FMSTAT_PGV_BITN 12 +#define FLASH_FMSTAT_PGV_M 0x00001000 +#define FLASH_FMSTAT_PGV_S 12 + +// Field: [11] PCV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PCV 0x00000800 +#define FLASH_FMSTAT_PCV_BITN 11 +#define FLASH_FMSTAT_PCV_M 0x00000800 +#define FLASH_FMSTAT_PCV_S 11 + +// Field: [10] EV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_EV 0x00000400 +#define FLASH_FMSTAT_EV_BITN 10 +#define FLASH_FMSTAT_EV_M 0x00000400 +#define FLASH_FMSTAT_EV_S 10 + +// Field: [9] CV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_CV 0x00000200 +#define FLASH_FMSTAT_CV_BITN 9 +#define FLASH_FMSTAT_CV_M 0x00000200 +#define FLASH_FMSTAT_CV_S 9 + +// Field: [8] BUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_BUSY 0x00000100 +#define FLASH_FMSTAT_BUSY_BITN 8 +#define FLASH_FMSTAT_BUSY_M 0x00000100 +#define FLASH_FMSTAT_BUSY_S 8 + +// Field: [7] ERS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ERS 0x00000080 +#define FLASH_FMSTAT_ERS_BITN 7 +#define FLASH_FMSTAT_ERS_M 0x00000080 +#define FLASH_FMSTAT_ERS_S 7 + +// Field: [6] PGM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PGM 0x00000040 +#define FLASH_FMSTAT_PGM_BITN 6 +#define FLASH_FMSTAT_PGM_M 0x00000040 +#define FLASH_FMSTAT_PGM_S 6 + +// Field: [5] INVDAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_INVDAT 0x00000020 +#define FLASH_FMSTAT_INVDAT_BITN 5 +#define FLASH_FMSTAT_INVDAT_M 0x00000020 +#define FLASH_FMSTAT_INVDAT_S 5 + +// Field: [4] CSTAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_CSTAT 0x00000010 +#define FLASH_FMSTAT_CSTAT_BITN 4 +#define FLASH_FMSTAT_CSTAT_M 0x00000010 +#define FLASH_FMSTAT_CSTAT_S 4 + +// Field: [3] VOLSTAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_VOLSTAT 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_BITN 3 +#define FLASH_FMSTAT_VOLSTAT_M 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_S 3 + +// Field: [2] ESUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ESUSP 0x00000004 +#define FLASH_FMSTAT_ESUSP_BITN 2 +#define FLASH_FMSTAT_ESUSP_M 0x00000004 +#define FLASH_FMSTAT_ESUSP_S 2 + +// Field: [1] PSUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PSUSP 0x00000002 +#define FLASH_FMSTAT_PSUSP_BITN 1 +#define FLASH_FMSTAT_PSUSP_M 0x00000002 +#define FLASH_FMSTAT_PSUSP_S 1 + +// Field: [0] SLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_SLOCK 0x00000001 +#define FLASH_FMSTAT_SLOCK_BITN 0 +#define FLASH_FMSTAT_SLOCK_M 0x00000001 +#define FLASH_FMSTAT_SLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FLOCK +// +//***************************************************************************** +// Field: [15:0] ENCOM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FLOCK_ENCOM_W 16 +#define FLASH_FLOCK_ENCOM_M 0x0000FFFF +#define FLASH_FLOCK_ENCOM_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVREADCT +// +//***************************************************************************** +// Field: [3:0] VREADCT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVREADCT_VREADCT_W 4 +#define FLASH_FVREADCT_VREADCT_M 0x0000000F +#define FLASH_FVREADCT_VREADCT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT1 +// +//***************************************************************************** +// Field: [23:20] TRIM13_E +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_TRIM13_E_W 4 +#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 +#define FLASH_FVHVCT1_TRIM13_E_S 20 + +// Field: [19:16] VHVCT_E +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_VHVCT_E_W 4 +#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 +#define FLASH_FVHVCT1_VHVCT_E_S 16 + +// Field: [7:4] TRIM13_PV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_TRIM13_PV_W 4 +#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 +#define FLASH_FVHVCT1_TRIM13_PV_S 4 + +// Field: [3:0] VHVCT_PV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_VHVCT_PV_W 4 +#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F +#define FLASH_FVHVCT1_VHVCT_PV_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT2 +// +//***************************************************************************** +// Field: [23:20] TRIM13_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT2_TRIM13_P_W 4 +#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 +#define FLASH_FVHVCT2_TRIM13_P_S 20 + +// Field: [19:16] VHVCT_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT2_VHVCT_P_W 4 +#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 +#define FLASH_FVHVCT2_VHVCT_P_S 16 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT3 +// +//***************************************************************************** +// Field: [19:16] WCT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT3_WCT_W 4 +#define FLASH_FVHVCT3_WCT_M 0x000F0000 +#define FLASH_FVHVCT3_WCT_S 16 + +// Field: [3:0] VHVCT_READ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT3_VHVCT_READ_W 4 +#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F +#define FLASH_FVHVCT3_VHVCT_READ_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVNVCT +// +//***************************************************************************** +// Field: [12:8] VCG2P5CT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVNVCT_VCG2P5CT_W 5 +#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 +#define FLASH_FVNVCT_VCG2P5CT_S 8 + +// Field: [4:0] VIN_CT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVNVCT_VIN_CT_W 5 +#define FLASH_FVNVCT_VIN_CT_M 0x0000001F +#define FLASH_FVNVCT_VIN_CT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVSLP +// +//***************************************************************************** +// Field: [15:12] VSL_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVSLP_VSL_P_W 4 +#define FLASH_FVSLP_VSL_P_M 0x0000F000 +#define FLASH_FVSLP_VSL_P_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FVWLCT +// +//***************************************************************************** +// Field: [4:0] VWLCT_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVWLCT_VWLCT_P_W 5 +#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F +#define FLASH_FVWLCT_VWLCT_P_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSECTL +// +//***************************************************************************** +// Field: [26:24] CHAIN_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_CHAIN_SEL_W 3 +#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000 +#define FLASH_FEFUSECTL_CHAIN_SEL_S 24 + +// Field: [17] WRITE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_WRITE_EN 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_BITN 17 +#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_S 17 + +// Field: [16] BP_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_BP_SEL 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_BITN 16 +#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_S 16 + +// Field: [8] EF_CLRZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8 +#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_S 8 + +// Field: [4] EF_TEST +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EF_TEST 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_BITN 4 +#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_S 4 + +// Field: [3:0] EFUSE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EFUSE_EN_W 4 +#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F +#define FLASH_FEFUSECTL_EFUSE_EN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSESTAT +// +//***************************************************************************** +// Field: [0] SHIFT_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0 +#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSEDATA +// +//***************************************************************************** +// Field: [31:0] FEFUSEDATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32 +#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF +#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSEQPMP +// +//***************************************************************************** +// Field: [27:24] TRIM_3P4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_3P4_W 4 +#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000 +#define FLASH_FSEQPMP_TRIM_3P4_S 24 + +// Field: [21:20] TRIM_1P7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_1P7_W 2 +#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 +#define FLASH_FSEQPMP_TRIM_1P7_S 20 + +// Field: [19:16] TRIM_0P8 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_0P8_W 4 +#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000 +#define FLASH_FSEQPMP_TRIM_0P8_S 16 + +// Field: [14:12] VIN_AT_X +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_VIN_AT_X_W 3 +#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 +#define FLASH_FSEQPMP_VIN_AT_X_S 12 + +// Field: [8] VIN_BY_PASS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8 +#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FBSTROBES +// +//***************************************************************************** +// Field: [24] ECBIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_ECBIT 0x01000000 +#define FLASH_FBSTROBES_ECBIT_BITN 24 +#define FLASH_FBSTROBES_ECBIT_M 0x01000000 +#define FLASH_FBSTROBES_ECBIT_S 24 + +// Field: [18] RWAIT2_FLCLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18 + +// Field: [17] RWAIT_FLCLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17 +#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17 + +// Field: [16] FLCLKEN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_FLCLKEN 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_BITN 16 +#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_S 16 + +// Field: [8] CTRLENZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_CTRLENZ 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_BITN 8 +#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_S 8 + +// Field: [6] NOCOLRED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_NOCOLRED 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_BITN 6 +#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_S 6 + +// Field: [5] PRECOL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_PRECOL 0x00000020 +#define FLASH_FBSTROBES_PRECOL_BITN 5 +#define FLASH_FBSTROBES_PRECOL_M 0x00000020 +#define FLASH_FBSTROBES_PRECOL_S 5 + +// Field: [4] TI_OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_TI_OTP 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_BITN 4 +#define FLASH_FBSTROBES_TI_OTP_M 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_S 4 + +// Field: [3] OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_OTP 0x00000008 +#define FLASH_FBSTROBES_OTP_BITN 3 +#define FLASH_FBSTROBES_OTP_M 0x00000008 +#define FLASH_FBSTROBES_OTP_S 3 + +// Field: [2] TEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_TEZ 0x00000004 +#define FLASH_FBSTROBES_TEZ_BITN 2 +#define FLASH_FBSTROBES_TEZ_M 0x00000004 +#define FLASH_FBSTROBES_TEZ_S 2 + +//***************************************************************************** +// +// Register: FLASH_O_FPSTROBES +// +//***************************************************************************** +// Field: [8] EXECUTEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_EXECUTEZ 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_BITN 8 +#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_S 8 + +// Field: [1] V3PWRDNZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1 +#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_S 1 + +// Field: [0] V5PWRDNZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0 +#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBMODE +// +//***************************************************************************** +// Field: [2:0] MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBMODE_MODE_W 3 +#define FLASH_FBMODE_MODE_M 0x00000007 +#define FLASH_FBMODE_MODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FTCR +// +//***************************************************************************** +// Field: [6:0] TCR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCR_TCR_W 7 +#define FLASH_FTCR_TCR_M 0x0000007F +#define FLASH_FTCR_TCR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FADDR +// +//***************************************************************************** +// Field: [31:0] FADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FADDR_FADDR_W 32 +#define FLASH_FADDR_FADDR_M 0xFFFFFFFF +#define FLASH_FADDR_FADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FTCTL +// +//***************************************************************************** +// Field: [16] WDATA_BLK_CLR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16 +#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_S 16 + +// Field: [1] TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCTL_TEST_EN 0x00000002 +#define FLASH_FTCTL_TEST_EN_BITN 1 +#define FLASH_FTCTL_TEST_EN_M 0x00000002 +#define FLASH_FTCTL_TEST_EN_S 1 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE0 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE0_FWPWRITE0_W 32 +#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF +#define FLASH_FWPWRITE0_FWPWRITE0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE1 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE1_FWPWRITE1_W 32 +#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF +#define FLASH_FWPWRITE1_FWPWRITE1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE2 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE2_FWPWRITE2_W 32 +#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF +#define FLASH_FWPWRITE2_FWPWRITE2_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE3 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE3_FWPWRITE3_W 32 +#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF +#define FLASH_FWPWRITE3_FWPWRITE3_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE4 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE4_FWPWRITE4_W 32 +#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF +#define FLASH_FWPWRITE4_FWPWRITE4_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE5 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE5 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE5_FWPWRITE5_W 32 +#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF +#define FLASH_FWPWRITE5_FWPWRITE5_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE6 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE6 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE6_FWPWRITE6_W 32 +#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF +#define FLASH_FWPWRITE6_FWPWRITE6_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE7 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE7_FWPWRITE7_W 32 +#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF +#define FLASH_FWPWRITE7_FWPWRITE7_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE_ECC +// +//***************************************************************************** +// Field: [31:24] ECCBYTES07_00 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24 + +// Field: [23:16] ECCBYTES15_08 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16 + +// Field: [15:8] ECCBYTES23_16 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8 + +// Field: [7:0] ECCBYTES31_24 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSWSTAT +// +//***************************************************************************** +// Field: [0] SAFELV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSWSTAT_SAFELV 0x00000001 +#define FLASH_FSWSTAT_SAFELV_BITN 0 +#define FLASH_FSWSTAT_SAFELV_M 0x00000001 +#define FLASH_FSWSTAT_SAFELV_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_GLBCTL +// +//***************************************************************************** +// Field: [0] CLKSEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0 +#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STATE +// +//***************************************************************************** +// Field: [11] CTRLENZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_CTRLENZ 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_BITN 11 +#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_S 11 + +// Field: [10] EXECUTEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_EXECUTEZ 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_BITN 10 +#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_S 10 + +// Field: [8] FSM_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_FSM_ACT 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_BITN 8 +#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_S 8 + +// Field: [7] TIOTP_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7 +#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_S 7 + +// Field: [6] OTP_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_OTP_ACT 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_BITN 6 +#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_S 6 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STAT +// +//***************************************************************************** +// Field: [2] NON_OP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_NON_OP 0x00000004 +#define FLASH_FSM_STAT_NON_OP_BITN 2 +#define FLASH_FSM_STAT_NON_OP_M 0x00000004 +#define FLASH_FSM_STAT_NON_OP_S 2 + +// Field: [1] OVR_PUL_CNT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1 +#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1 + +// Field: [0] INV_DAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_INV_DAT 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_BITN 0 +#define FLASH_FSM_STAT_INV_DAT_M 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_CMD +// +//***************************************************************************** +// Field: [5:0] FSMCMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_CMD_FSMCMD_W 6 +#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F +#define FLASH_FSM_CMD_FSMCMD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_OSU +// +//***************************************************************************** +// Field: [15:8] PGM_OSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_OSU_PGM_OSU_W 8 +#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 +#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 + +// Field: [7:0] ERA_OSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_OSU_ERA_OSU_W 8 +#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF +#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_VSTAT +// +//***************************************************************************** +// Field: [15:12] VSTAT_CNT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4 +#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 +#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_VSU +// +//***************************************************************************** +// Field: [15:8] PGM_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VSU_PGM_VSU_W 8 +#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 +#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 + +// Field: [7:0] ERA_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VSU_ERA_VSU_W 8 +#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF +#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_CMP_VSU +// +//***************************************************************************** +// Field: [15:12] ADD_EXZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EX_VAL +// +//***************************************************************************** +// Field: [15:8] REP_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EX_VAL_REP_VSU_W 8 +#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 +#define FLASH_FSM_EX_VAL_REP_VSU_S 8 + +// Field: [7:0] EXE_VALD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EX_VAL_EXE_VALD_W 8 +#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF +#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_RD_H +// +//***************************************************************************** +// Field: [7:0] RD_H +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_RD_H_RD_H_W 8 +#define FLASH_FSM_RD_H_RD_H_M 0x000000FF +#define FLASH_FSM_RD_H_RD_H_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_P_OH +// +//***************************************************************************** +// Field: [15:8] PGM_OH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_P_OH_PGM_OH_W 8 +#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 +#define FLASH_FSM_P_OH_PGM_OH_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_OH +// +//***************************************************************************** +// Field: [15:0] ERA_OH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_OH_ERA_OH_W 16 +#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF +#define FLASH_FSM_ERA_OH_ERA_OH_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SAV_PPUL +// +//***************************************************************************** +// Field: [11:0] SAV_P_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12 +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_VH +// +//***************************************************************************** +// Field: [15:8] PGM_VH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VH_PGM_VH_W 8 +#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 +#define FLASH_FSM_PE_VH_PGM_VH_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PRG_PW +// +//***************************************************************************** +// Field: [15:0] PROG_PUL_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16 +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_PW +// +//***************************************************************************** +// Field: [31:0] FSM_ERA_PW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32 +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SAV_ERA_PUL +// +//***************************************************************************** +// Field: [11:0] SAV_ERA_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12 +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_TIMER +// +//***************************************************************************** +// Field: [31:0] FSM_TIMER +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_TIMER_FSM_TIMER_W 32 +#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF +#define FLASH_FSM_TIMER_FSM_TIMER_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_MODE +// +//***************************************************************************** +// Field: [19:18] RDV_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_RDV_SUBMODE_W 2 +#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000 +#define FLASH_FSM_MODE_RDV_SUBMODE_S 18 + +// Field: [17:16] PGM_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_PGM_SUBMODE_W 2 +#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000 +#define FLASH_FSM_MODE_PGM_SUBMODE_S 16 + +// Field: [15:14] ERA_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_ERA_SUBMODE_W 2 +#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000 +#define FLASH_FSM_MODE_ERA_SUBMODE_S 14 + +// Field: [13:12] SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SUBMODE_W 2 +#define FLASH_FSM_MODE_SUBMODE_M 0x00003000 +#define FLASH_FSM_MODE_SUBMODE_S 12 + +// Field: [11:9] SAV_PGM_CMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3 +#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00 +#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9 + +// Field: [8:6] SAV_ERA_MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3 +#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0 +#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6 + +// Field: [5:3] MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_MODE_W 3 +#define FLASH_FSM_MODE_MODE_M 0x00000038 +#define FLASH_FSM_MODE_MODE_S 3 + +// Field: [2:0] CMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_CMD_W 3 +#define FLASH_FSM_MODE_CMD_M 0x00000007 +#define FLASH_FSM_MODE_CMD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PGM +// +//***************************************************************************** +// Field: [25:23] PGM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_PGM_BANK_W 3 +#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000 +#define FLASH_FSM_PGM_PGM_BANK_S 23 + +// Field: [22:0] PGM_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_PGM_ADDR_W 23 +#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF +#define FLASH_FSM_PGM_PGM_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA +// +//***************************************************************************** +// Field: [25:23] ERA_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_ERA_BANK_W 3 +#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000 +#define FLASH_FSM_ERA_ERA_BANK_S 23 + +// Field: [22:0] ERA_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_ERA_ADDR_W 23 +#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF +#define FLASH_FSM_ERA_ERA_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PRG_PUL +// +//***************************************************************************** +// Field: [19:16] BEG_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 + +// Field: [11:0] MAX_PRG_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12 +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_PUL +// +//***************************************************************************** +// Field: [19:16] MAX_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 + +// Field: [11:0] MAX_ERA_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12 +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STEP_SIZE +// +//***************************************************************************** +// Field: [24:16] EC_STEP_SIZE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PUL_CNTR +// +//***************************************************************************** +// Field: [24:16] CUR_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16 + +// Field: [11:0] PUL_CNTR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12 +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EC_STEP_HEIGHT +// +//***************************************************************************** +// Field: [3:0] EC_STEP_HEIGHT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4 +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ST_MACHINE +// +//***************************************************************************** +// Field: [23] DO_PRECOND +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 + +// Field: [22] FSM_INT_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22 + +// Field: [21] ALL_BANKS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21 + +// Field: [20] CMPV_ALLOWED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20 + +// Field: [19] RANDOM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19 +#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_S 19 + +// Field: [18] RV_SEC_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18 + +// Field: [17] RV_RES +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17 +#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_S 17 + +// Field: [16] RV_INT_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16 + +// Field: [14] ONE_TIME_GOOD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14 + +// Field: [11] DO_REDU_COL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11 + +// Field: [10:7] DBG_SHORT_ROW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7 + +// Field: [5] PGM_SEC_COF_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5 + +// Field: [4] PREC_STOP_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4 + +// Field: [3] DIS_TST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3 + +// Field: [2] CMD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2 +#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2 + +// Field: [1] INV_DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1 +#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1 + +// Field: [0] OVERRIDE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_FLES +// +//***************************************************************************** +// Field: [11:8] BLK_TIOTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_FLES_BLK_TIOTP_W 4 +#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00 +#define FLASH_FSM_FLES_BLK_TIOTP_S 8 + +// Field: [7:0] BLK_OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_FLES_BLK_OTP_W 8 +#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF +#define FLASH_FSM_FLES_BLK_OTP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_WR_ENA +// +//***************************************************************************** +// Field: [2:0] WR_ENA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_WR_ENA_WR_ENA_W 3 +#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007 +#define FLASH_FSM_WR_ENA_WR_ENA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ACC_PP +// +//***************************************************************************** +// Field: [31:0] FSM_ACC_PP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32 +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ACC_EP +// +//***************************************************************************** +// Field: [15:0] ACC_EP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ACC_EP_ACC_EP_W 16 +#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF +#define FLASH_FSM_ACC_EP_ACC_EP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ADDR +// +//***************************************************************************** +// Field: [30:28] BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ADDR_BANK_W 3 +#define FLASH_FSM_ADDR_BANK_M 0x70000000 +#define FLASH_FSM_ADDR_BANK_S 28 + +// Field: [27:0] CUR_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ADDR_CUR_ADDR_W 28 +#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF +#define FLASH_FSM_ADDR_CUR_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR +// +//***************************************************************************** +// Field: [31:16] SECT_ERASED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SECT_ERASED_W 16 +#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000 +#define FLASH_FSM_SECTOR_SECT_ERASED_S 16 + +// Field: [15:8] FSM_SECTOR_EXTENSION +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8 + +// Field: [7:4] SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SECTOR_W 4 +#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0 +#define FLASH_FSM_SECTOR_SECTOR_S 4 + +// Field: [3:0] SEC_OUT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SEC_OUT_W 4 +#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F +#define FLASH_FSM_SECTOR_SEC_OUT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMC_REV_ID +// +//***************************************************************************** +// Field: [31:12] MOD_VERSION +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMC_REV_ID_MOD_VERSION_W 20 +#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000 +#define FLASH_FMC_REV_ID_MOD_VERSION_S 12 + +// Field: [11:0] CONFIG_CRC +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12 +#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF +#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERR_ADDR +// +//***************************************************************************** +// Field: [31:8] FSM_ERR_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0xFFFFFF00 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 8 + +// Field: [3:0] FSM_ERR_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 4 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x0000000F +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PGM_MAXPUL +// +//***************************************************************************** +// Field: [11:0] FSM_PGM_MAXPUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12 +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EXECUTE +// +//***************************************************************************** +// Field: [19:16] SUSPEND_NOW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16 + +// Field: [4:0] FSMEXECUTE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5 +#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F +#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR1 +// +//***************************************************************************** +// Field: [31:0] FSM_SECTOR1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32 +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR2 +// +//***************************************************************************** +// Field: [31:0] FSM_SECTOR2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32 +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLE0 +// +//***************************************************************************** +// Field: [31:0] FSM_BSLE0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32 +#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF +#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLE1 +// +//***************************************************************************** +// Field: [31:0] FSM_BSL1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLE1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLE1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLE1_FSM_BSL1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLP0 +// +//***************************************************************************** +// Field: [31:0] FSM_BSLP0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32 +#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF +#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLP1 +// +//***************************************************************************** +// Field: [31:0] FSM_BSL1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLP1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLP1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLP1_FSM_BSL1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PGM128 +// +//***************************************************************************** +// Field: [0] EN_PGM128 +// +// 1: Enables 128-bit wide programming. This mode requires programming supply +// voltage to be greater than 2.5v at the Flash Pump. The primary use case for +// this mode is manufacturing test for test time reduction. +// +// 0: 64-bit wide programming. Valid at any programming voltage. A 128-bit +// word is divided into two 64-bit words for programming. [default] +// +// This register is write protected with the FSM_WR_ENA register. +#define FLASH_FSM_PGM128_EN_PGM128 0x00000001 +#define FLASH_FSM_PGM128_EN_PGM128_BITN 0 +#define FLASH_FSM_PGM128_EN_PGM128_M 0x00000001 +#define FLASH_FSM_PGM128_EN_PGM128_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_BANK +// +//***************************************************************************** +// Field: [31:20] EE_BANK_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20 + +// Field: [19:16] EE_NUM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000 +#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16 + +// Field: [15:4] MAIN_BANK_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 + +// Field: [3:0] MAIN_NUM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_WRAPPER +// +//***************************************************************************** +// Field: [31:24] FAMILY_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24 + +// Field: [20] MEM_MAP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20 +#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20 + +// Field: [19:16] CPU2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_CPU2_W 4 +#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000 +#define FLASH_FCFG_WRAPPER_CPU2_S 16 + +// Field: [15:12] EE_IN_MAIN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12 + +// Field: [11] ROM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_ROM 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_BITN 11 +#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_S 11 + +// Field: [10] IFLUSH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10 +#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_S 10 + +// Field: [9] SIL3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_SIL3 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_BITN 9 +#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_S 9 + +// Field: [8] ECCA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_ECCA 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_BITN 8 +#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_S 8 + +// Field: [7:6] AUTO_SUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6 + +// Field: [5:4] UERR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_UERR_W 2 +#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030 +#define FLASH_FCFG_WRAPPER_UERR_S 4 + +// Field: [3:0] CPU_TYPE1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4 +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_BNK_TYPE +// +//***************************************************************************** +// Field: [31:28] B7_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28 + +// Field: [27:24] B6_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24 + +// Field: [23:20] B5_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20 + +// Field: [19:16] B4_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16 + +// Field: [15:12] B3_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12 + +// Field: [11:8] B2_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8 + +// Field: [7:4] B1_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4 + +// Field: [3:0] B0_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B0_START +// +//***************************************************************************** +// Field: [31:28] B0_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28 + +// Field: [27:24] B0_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24 + +// Field: [23:0] B0_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24 +#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B1_START +// +//***************************************************************************** +// Field: [31:28] B1_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28 + +// Field: [27:24] B1_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24 + +// Field: [23:0] B1_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24 +#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B2_START +// +//***************************************************************************** +// Field: [31:28] B2_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28 + +// Field: [27:24] B2_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24 + +// Field: [23:0] B2_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24 +#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B3_START +// +//***************************************************************************** +// Field: [31:28] B3_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28 + +// Field: [27:24] B3_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24 + +// Field: [23:0] B3_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24 +#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B4_START +// +//***************************************************************************** +// Field: [31:28] B4_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28 + +// Field: [27:24] B4_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24 + +// Field: [23:0] B4_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24 +#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B5_START +// +//***************************************************************************** +// Field: [31:28] B5_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28 + +// Field: [27:24] B5_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24 + +// Field: [23:0] B5_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24 +#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B6_START +// +//***************************************************************************** +// Field: [31:28] B6_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28 + +// Field: [27:24] B6_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24 + +// Field: [23:0] B6_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24 +#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B7_START +// +//***************************************************************************** +// Field: [31:28] B7_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28 + +// Field: [27:24] B7_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24 + +// Field: [23:0] B7_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24 +#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B0_SSIZE0 +// +//***************************************************************************** +// Field: [27:16] B0_NUM_SECTORS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16 + +// Field: [3:0] B0_SECT_SIZE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4 +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 + + +#endif // __FLASH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h new file mode 100644 index 0000000..1bf518b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h @@ -0,0 +1,2247 @@ +/****************************************************************************** +* Filename: hw_gpio_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// GPIO component +// +//***************************************************************************** +// Data Out 0 to 3 +#define GPIO_O_DOUT3_0 0x00000000 + +// Data Out 4 to 7 +#define GPIO_O_DOUT7_4 0x00000004 + +// Data Out 8 to 11 +#define GPIO_O_DOUT11_8 0x00000008 + +// Data Out 12 to 15 +#define GPIO_O_DOUT15_12 0x0000000C + +// Data Out 16 to 19 +#define GPIO_O_DOUT19_16 0x00000010 + +// Data Out 20 to 23 +#define GPIO_O_DOUT23_20 0x00000014 + +// Data Out 24 to 27 +#define GPIO_O_DOUT27_24 0x00000018 + +// Data Out 28 to 31 +#define GPIO_O_DOUT31_28 0x0000001C + +// Data Output for DIO 0 to 31 +#define GPIO_O_DOUT31_0 0x00000080 + +// Data Out Set +#define GPIO_O_DOUTSET31_0 0x00000090 + +// Data Out Clear +#define GPIO_O_DOUTCLR31_0 0x000000A0 + +// Data Out Toggle +#define GPIO_O_DOUTTGL31_0 0x000000B0 + +// Data Input from DIO 0 to 31 +#define GPIO_O_DIN31_0 0x000000C0 + +// Data Output Enable for DIO 0 to 31 +#define GPIO_O_DOE31_0 0x000000D0 + +// Event Register for DIO 0 to 31 +#define GPIO_O_EVFLAGS31_0 0x000000E0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT3_0 +// +//***************************************************************************** +// Field: [24] DIO3 +// +// Sets the state of the pin that is configured as DIO#3, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO3 0x01000000 +#define GPIO_DOUT3_0_DIO3_BITN 24 +#define GPIO_DOUT3_0_DIO3_M 0x01000000 +#define GPIO_DOUT3_0_DIO3_S 24 + +// Field: [16] DIO2 +// +// Sets the state of the pin that is configured as DIO#2, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO2 0x00010000 +#define GPIO_DOUT3_0_DIO2_BITN 16 +#define GPIO_DOUT3_0_DIO2_M 0x00010000 +#define GPIO_DOUT3_0_DIO2_S 16 + +// Field: [8] DIO1 +// +// Sets the state of the pin that is configured as DIO#1, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO1 0x00000100 +#define GPIO_DOUT3_0_DIO1_BITN 8 +#define GPIO_DOUT3_0_DIO1_M 0x00000100 +#define GPIO_DOUT3_0_DIO1_S 8 + +// Field: [0] DIO0 +// +// Sets the state of the pin that is configured as DIO#0, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO0 0x00000001 +#define GPIO_DOUT3_0_DIO0_BITN 0 +#define GPIO_DOUT3_0_DIO0_M 0x00000001 +#define GPIO_DOUT3_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT7_4 +// +//***************************************************************************** +// Field: [24] DIO7 +// +// Sets the state of the pin that is configured as DIO#7, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO7 0x01000000 +#define GPIO_DOUT7_4_DIO7_BITN 24 +#define GPIO_DOUT7_4_DIO7_M 0x01000000 +#define GPIO_DOUT7_4_DIO7_S 24 + +// Field: [16] DIO6 +// +// Sets the state of the pin that is configured as DIO#6, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO6 0x00010000 +#define GPIO_DOUT7_4_DIO6_BITN 16 +#define GPIO_DOUT7_4_DIO6_M 0x00010000 +#define GPIO_DOUT7_4_DIO6_S 16 + +// Field: [8] DIO5 +// +// Sets the state of the pin that is configured as DIO#5, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO5 0x00000100 +#define GPIO_DOUT7_4_DIO5_BITN 8 +#define GPIO_DOUT7_4_DIO5_M 0x00000100 +#define GPIO_DOUT7_4_DIO5_S 8 + +// Field: [0] DIO4 +// +// Sets the state of the pin that is configured as DIO#4, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO4 0x00000001 +#define GPIO_DOUT7_4_DIO4_BITN 0 +#define GPIO_DOUT7_4_DIO4_M 0x00000001 +#define GPIO_DOUT7_4_DIO4_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT11_8 +// +//***************************************************************************** +// Field: [24] DIO11 +// +// Sets the state of the pin that is configured as DIO#11, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO11 0x01000000 +#define GPIO_DOUT11_8_DIO11_BITN 24 +#define GPIO_DOUT11_8_DIO11_M 0x01000000 +#define GPIO_DOUT11_8_DIO11_S 24 + +// Field: [16] DIO10 +// +// Sets the state of the pin that is configured as DIO#10, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO10 0x00010000 +#define GPIO_DOUT11_8_DIO10_BITN 16 +#define GPIO_DOUT11_8_DIO10_M 0x00010000 +#define GPIO_DOUT11_8_DIO10_S 16 + +// Field: [8] DIO9 +// +// Sets the state of the pin that is configured as DIO#9, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO9 0x00000100 +#define GPIO_DOUT11_8_DIO9_BITN 8 +#define GPIO_DOUT11_8_DIO9_M 0x00000100 +#define GPIO_DOUT11_8_DIO9_S 8 + +// Field: [0] DIO8 +// +// Sets the state of the pin that is configured as DIO#8, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO8 0x00000001 +#define GPIO_DOUT11_8_DIO8_BITN 0 +#define GPIO_DOUT11_8_DIO8_M 0x00000001 +#define GPIO_DOUT11_8_DIO8_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT15_12 +// +//***************************************************************************** +// Field: [24] DIO15 +// +// Sets the state of the pin that is configured as DIO#15, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO15 0x01000000 +#define GPIO_DOUT15_12_DIO15_BITN 24 +#define GPIO_DOUT15_12_DIO15_M 0x01000000 +#define GPIO_DOUT15_12_DIO15_S 24 + +// Field: [16] DIO14 +// +// Sets the state of the pin that is configured as DIO#14, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO14 0x00010000 +#define GPIO_DOUT15_12_DIO14_BITN 16 +#define GPIO_DOUT15_12_DIO14_M 0x00010000 +#define GPIO_DOUT15_12_DIO14_S 16 + +// Field: [8] DIO13 +// +// Sets the state of the pin that is configured as DIO#13, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO13 0x00000100 +#define GPIO_DOUT15_12_DIO13_BITN 8 +#define GPIO_DOUT15_12_DIO13_M 0x00000100 +#define GPIO_DOUT15_12_DIO13_S 8 + +// Field: [0] DIO12 +// +// Sets the state of the pin that is configured as DIO#12, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO12 0x00000001 +#define GPIO_DOUT15_12_DIO12_BITN 0 +#define GPIO_DOUT15_12_DIO12_M 0x00000001 +#define GPIO_DOUT15_12_DIO12_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT19_16 +// +//***************************************************************************** +// Field: [24] DIO19 +// +// Sets the state of the pin that is configured as DIO#19, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO19 0x01000000 +#define GPIO_DOUT19_16_DIO19_BITN 24 +#define GPIO_DOUT19_16_DIO19_M 0x01000000 +#define GPIO_DOUT19_16_DIO19_S 24 + +// Field: [16] DIO18 +// +// Sets the state of the pin that is configured as DIO#18, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO18 0x00010000 +#define GPIO_DOUT19_16_DIO18_BITN 16 +#define GPIO_DOUT19_16_DIO18_M 0x00010000 +#define GPIO_DOUT19_16_DIO18_S 16 + +// Field: [8] DIO17 +// +// Sets the state of the pin that is configured as DIO#17, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO17 0x00000100 +#define GPIO_DOUT19_16_DIO17_BITN 8 +#define GPIO_DOUT19_16_DIO17_M 0x00000100 +#define GPIO_DOUT19_16_DIO17_S 8 + +// Field: [0] DIO16 +// +// Sets the state of the pin that is configured as DIO#16, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO16 0x00000001 +#define GPIO_DOUT19_16_DIO16_BITN 0 +#define GPIO_DOUT19_16_DIO16_M 0x00000001 +#define GPIO_DOUT19_16_DIO16_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT23_20 +// +//***************************************************************************** +// Field: [24] DIO23 +// +// Sets the state of the pin that is configured as DIO#23, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO23 0x01000000 +#define GPIO_DOUT23_20_DIO23_BITN 24 +#define GPIO_DOUT23_20_DIO23_M 0x01000000 +#define GPIO_DOUT23_20_DIO23_S 24 + +// Field: [16] DIO22 +// +// Sets the state of the pin that is configured as DIO#22, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO22 0x00010000 +#define GPIO_DOUT23_20_DIO22_BITN 16 +#define GPIO_DOUT23_20_DIO22_M 0x00010000 +#define GPIO_DOUT23_20_DIO22_S 16 + +// Field: [8] DIO21 +// +// Sets the state of the pin that is configured as DIO#21, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO21 0x00000100 +#define GPIO_DOUT23_20_DIO21_BITN 8 +#define GPIO_DOUT23_20_DIO21_M 0x00000100 +#define GPIO_DOUT23_20_DIO21_S 8 + +// Field: [0] DIO20 +// +// Sets the state of the pin that is configured as DIO#20, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO20 0x00000001 +#define GPIO_DOUT23_20_DIO20_BITN 0 +#define GPIO_DOUT23_20_DIO20_M 0x00000001 +#define GPIO_DOUT23_20_DIO20_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT27_24 +// +//***************************************************************************** +// Field: [24] DIO27 +// +// Sets the state of the pin that is configured as DIO#27, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO27 0x01000000 +#define GPIO_DOUT27_24_DIO27_BITN 24 +#define GPIO_DOUT27_24_DIO27_M 0x01000000 +#define GPIO_DOUT27_24_DIO27_S 24 + +// Field: [16] DIO26 +// +// Sets the state of the pin that is configured as DIO#26, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO26 0x00010000 +#define GPIO_DOUT27_24_DIO26_BITN 16 +#define GPIO_DOUT27_24_DIO26_M 0x00010000 +#define GPIO_DOUT27_24_DIO26_S 16 + +// Field: [8] DIO25 +// +// Sets the state of the pin that is configured as DIO#25, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO25 0x00000100 +#define GPIO_DOUT27_24_DIO25_BITN 8 +#define GPIO_DOUT27_24_DIO25_M 0x00000100 +#define GPIO_DOUT27_24_DIO25_S 8 + +// Field: [0] DIO24 +// +// Sets the state of the pin that is configured as DIO#24, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO24 0x00000001 +#define GPIO_DOUT27_24_DIO24_BITN 0 +#define GPIO_DOUT27_24_DIO24_M 0x00000001 +#define GPIO_DOUT27_24_DIO24_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT31_28 +// +//***************************************************************************** +// Field: [24] DIO31 +// +// Sets the state of the pin that is configured as DIO#31, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO31 0x01000000 +#define GPIO_DOUT31_28_DIO31_BITN 24 +#define GPIO_DOUT31_28_DIO31_M 0x01000000 +#define GPIO_DOUT31_28_DIO31_S 24 + +// Field: [16] DIO30 +// +// Sets the state of the pin that is configured as DIO#30, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO30 0x00010000 +#define GPIO_DOUT31_28_DIO30_BITN 16 +#define GPIO_DOUT31_28_DIO30_M 0x00010000 +#define GPIO_DOUT31_28_DIO30_S 16 + +// Field: [8] DIO29 +// +// Sets the state of the pin that is configured as DIO#29, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO29 0x00000100 +#define GPIO_DOUT31_28_DIO29_BITN 8 +#define GPIO_DOUT31_28_DIO29_M 0x00000100 +#define GPIO_DOUT31_28_DIO29_S 8 + +// Field: [0] DIO28 +// +// Sets the state of the pin that is configured as DIO#28, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO28 0x00000001 +#define GPIO_DOUT31_28_DIO28_BITN 0 +#define GPIO_DOUT31_28_DIO28_M 0x00000001 +#define GPIO_DOUT31_28_DIO28_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data output for DIO 31 +#define GPIO_DOUT31_0_DIO31 0x80000000 +#define GPIO_DOUT31_0_DIO31_BITN 31 +#define GPIO_DOUT31_0_DIO31_M 0x80000000 +#define GPIO_DOUT31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data output for DIO 30 +#define GPIO_DOUT31_0_DIO30 0x40000000 +#define GPIO_DOUT31_0_DIO30_BITN 30 +#define GPIO_DOUT31_0_DIO30_M 0x40000000 +#define GPIO_DOUT31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data output for DIO 29 +#define GPIO_DOUT31_0_DIO29 0x20000000 +#define GPIO_DOUT31_0_DIO29_BITN 29 +#define GPIO_DOUT31_0_DIO29_M 0x20000000 +#define GPIO_DOUT31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data output for DIO 28 +#define GPIO_DOUT31_0_DIO28 0x10000000 +#define GPIO_DOUT31_0_DIO28_BITN 28 +#define GPIO_DOUT31_0_DIO28_M 0x10000000 +#define GPIO_DOUT31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data output for DIO 27 +#define GPIO_DOUT31_0_DIO27 0x08000000 +#define GPIO_DOUT31_0_DIO27_BITN 27 +#define GPIO_DOUT31_0_DIO27_M 0x08000000 +#define GPIO_DOUT31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data output for DIO 26 +#define GPIO_DOUT31_0_DIO26 0x04000000 +#define GPIO_DOUT31_0_DIO26_BITN 26 +#define GPIO_DOUT31_0_DIO26_M 0x04000000 +#define GPIO_DOUT31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data output for DIO 25 +#define GPIO_DOUT31_0_DIO25 0x02000000 +#define GPIO_DOUT31_0_DIO25_BITN 25 +#define GPIO_DOUT31_0_DIO25_M 0x02000000 +#define GPIO_DOUT31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data output for DIO 24 +#define GPIO_DOUT31_0_DIO24 0x01000000 +#define GPIO_DOUT31_0_DIO24_BITN 24 +#define GPIO_DOUT31_0_DIO24_M 0x01000000 +#define GPIO_DOUT31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data output for DIO 23 +#define GPIO_DOUT31_0_DIO23 0x00800000 +#define GPIO_DOUT31_0_DIO23_BITN 23 +#define GPIO_DOUT31_0_DIO23_M 0x00800000 +#define GPIO_DOUT31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data output for DIO 22 +#define GPIO_DOUT31_0_DIO22 0x00400000 +#define GPIO_DOUT31_0_DIO22_BITN 22 +#define GPIO_DOUT31_0_DIO22_M 0x00400000 +#define GPIO_DOUT31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data output for DIO 21 +#define GPIO_DOUT31_0_DIO21 0x00200000 +#define GPIO_DOUT31_0_DIO21_BITN 21 +#define GPIO_DOUT31_0_DIO21_M 0x00200000 +#define GPIO_DOUT31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data output for DIO 20 +#define GPIO_DOUT31_0_DIO20 0x00100000 +#define GPIO_DOUT31_0_DIO20_BITN 20 +#define GPIO_DOUT31_0_DIO20_M 0x00100000 +#define GPIO_DOUT31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data output for DIO 19 +#define GPIO_DOUT31_0_DIO19 0x00080000 +#define GPIO_DOUT31_0_DIO19_BITN 19 +#define GPIO_DOUT31_0_DIO19_M 0x00080000 +#define GPIO_DOUT31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data output for DIO 18 +#define GPIO_DOUT31_0_DIO18 0x00040000 +#define GPIO_DOUT31_0_DIO18_BITN 18 +#define GPIO_DOUT31_0_DIO18_M 0x00040000 +#define GPIO_DOUT31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data output for DIO 17 +#define GPIO_DOUT31_0_DIO17 0x00020000 +#define GPIO_DOUT31_0_DIO17_BITN 17 +#define GPIO_DOUT31_0_DIO17_M 0x00020000 +#define GPIO_DOUT31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data output for DIO 16 +#define GPIO_DOUT31_0_DIO16 0x00010000 +#define GPIO_DOUT31_0_DIO16_BITN 16 +#define GPIO_DOUT31_0_DIO16_M 0x00010000 +#define GPIO_DOUT31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data output for DIO 15 +#define GPIO_DOUT31_0_DIO15 0x00008000 +#define GPIO_DOUT31_0_DIO15_BITN 15 +#define GPIO_DOUT31_0_DIO15_M 0x00008000 +#define GPIO_DOUT31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data output for DIO 14 +#define GPIO_DOUT31_0_DIO14 0x00004000 +#define GPIO_DOUT31_0_DIO14_BITN 14 +#define GPIO_DOUT31_0_DIO14_M 0x00004000 +#define GPIO_DOUT31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data output for DIO 13 +#define GPIO_DOUT31_0_DIO13 0x00002000 +#define GPIO_DOUT31_0_DIO13_BITN 13 +#define GPIO_DOUT31_0_DIO13_M 0x00002000 +#define GPIO_DOUT31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data output for DIO 12 +#define GPIO_DOUT31_0_DIO12 0x00001000 +#define GPIO_DOUT31_0_DIO12_BITN 12 +#define GPIO_DOUT31_0_DIO12_M 0x00001000 +#define GPIO_DOUT31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data output for DIO 11 +#define GPIO_DOUT31_0_DIO11 0x00000800 +#define GPIO_DOUT31_0_DIO11_BITN 11 +#define GPIO_DOUT31_0_DIO11_M 0x00000800 +#define GPIO_DOUT31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data output for DIO 10 +#define GPIO_DOUT31_0_DIO10 0x00000400 +#define GPIO_DOUT31_0_DIO10_BITN 10 +#define GPIO_DOUT31_0_DIO10_M 0x00000400 +#define GPIO_DOUT31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data output for DIO 9 +#define GPIO_DOUT31_0_DIO9 0x00000200 +#define GPIO_DOUT31_0_DIO9_BITN 9 +#define GPIO_DOUT31_0_DIO9_M 0x00000200 +#define GPIO_DOUT31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data output for DIO 8 +#define GPIO_DOUT31_0_DIO8 0x00000100 +#define GPIO_DOUT31_0_DIO8_BITN 8 +#define GPIO_DOUT31_0_DIO8_M 0x00000100 +#define GPIO_DOUT31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data output for DIO 7 +#define GPIO_DOUT31_0_DIO7 0x00000080 +#define GPIO_DOUT31_0_DIO7_BITN 7 +#define GPIO_DOUT31_0_DIO7_M 0x00000080 +#define GPIO_DOUT31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data output for DIO 6 +#define GPIO_DOUT31_0_DIO6 0x00000040 +#define GPIO_DOUT31_0_DIO6_BITN 6 +#define GPIO_DOUT31_0_DIO6_M 0x00000040 +#define GPIO_DOUT31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data output for DIO 5 +#define GPIO_DOUT31_0_DIO5 0x00000020 +#define GPIO_DOUT31_0_DIO5_BITN 5 +#define GPIO_DOUT31_0_DIO5_M 0x00000020 +#define GPIO_DOUT31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data output for DIO 4 +#define GPIO_DOUT31_0_DIO4 0x00000010 +#define GPIO_DOUT31_0_DIO4_BITN 4 +#define GPIO_DOUT31_0_DIO4_M 0x00000010 +#define GPIO_DOUT31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data output for DIO 3 +#define GPIO_DOUT31_0_DIO3 0x00000008 +#define GPIO_DOUT31_0_DIO3_BITN 3 +#define GPIO_DOUT31_0_DIO3_M 0x00000008 +#define GPIO_DOUT31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data output for DIO 2 +#define GPIO_DOUT31_0_DIO2 0x00000004 +#define GPIO_DOUT31_0_DIO2_BITN 2 +#define GPIO_DOUT31_0_DIO2_M 0x00000004 +#define GPIO_DOUT31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data output for DIO 1 +#define GPIO_DOUT31_0_DIO1 0x00000002 +#define GPIO_DOUT31_0_DIO1_BITN 1 +#define GPIO_DOUT31_0_DIO1_M 0x00000002 +#define GPIO_DOUT31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data output for DIO 0 +#define GPIO_DOUT31_0_DIO0 0x00000001 +#define GPIO_DOUT31_0_DIO0_BITN 0 +#define GPIO_DOUT31_0_DIO0_M 0x00000001 +#define GPIO_DOUT31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTSET31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Set bit 31 +#define GPIO_DOUTSET31_0_DIO31 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_BITN 31 +#define GPIO_DOUTSET31_0_DIO31_M 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Set bit 30 +#define GPIO_DOUTSET31_0_DIO30 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_BITN 30 +#define GPIO_DOUTSET31_0_DIO30_M 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Set bit 29 +#define GPIO_DOUTSET31_0_DIO29 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_BITN 29 +#define GPIO_DOUTSET31_0_DIO29_M 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Set bit 28 +#define GPIO_DOUTSET31_0_DIO28 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_BITN 28 +#define GPIO_DOUTSET31_0_DIO28_M 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Set bit 27 +#define GPIO_DOUTSET31_0_DIO27 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_BITN 27 +#define GPIO_DOUTSET31_0_DIO27_M 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Set bit 26 +#define GPIO_DOUTSET31_0_DIO26 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_BITN 26 +#define GPIO_DOUTSET31_0_DIO26_M 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Set bit 25 +#define GPIO_DOUTSET31_0_DIO25 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_BITN 25 +#define GPIO_DOUTSET31_0_DIO25_M 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Set bit 24 +#define GPIO_DOUTSET31_0_DIO24 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_BITN 24 +#define GPIO_DOUTSET31_0_DIO24_M 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Set bit 23 +#define GPIO_DOUTSET31_0_DIO23 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_BITN 23 +#define GPIO_DOUTSET31_0_DIO23_M 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Set bit 22 +#define GPIO_DOUTSET31_0_DIO22 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_BITN 22 +#define GPIO_DOUTSET31_0_DIO22_M 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Set bit 21 +#define GPIO_DOUTSET31_0_DIO21 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_BITN 21 +#define GPIO_DOUTSET31_0_DIO21_M 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Set bit 20 +#define GPIO_DOUTSET31_0_DIO20 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_BITN 20 +#define GPIO_DOUTSET31_0_DIO20_M 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Set bit 19 +#define GPIO_DOUTSET31_0_DIO19 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_BITN 19 +#define GPIO_DOUTSET31_0_DIO19_M 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Set bit 18 +#define GPIO_DOUTSET31_0_DIO18 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_BITN 18 +#define GPIO_DOUTSET31_0_DIO18_M 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Set bit 17 +#define GPIO_DOUTSET31_0_DIO17 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_BITN 17 +#define GPIO_DOUTSET31_0_DIO17_M 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Set bit 16 +#define GPIO_DOUTSET31_0_DIO16 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_BITN 16 +#define GPIO_DOUTSET31_0_DIO16_M 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Set bit 15 +#define GPIO_DOUTSET31_0_DIO15 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_BITN 15 +#define GPIO_DOUTSET31_0_DIO15_M 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Set bit 14 +#define GPIO_DOUTSET31_0_DIO14 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_BITN 14 +#define GPIO_DOUTSET31_0_DIO14_M 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Set bit 13 +#define GPIO_DOUTSET31_0_DIO13 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_BITN 13 +#define GPIO_DOUTSET31_0_DIO13_M 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Set bit 12 +#define GPIO_DOUTSET31_0_DIO12 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_BITN 12 +#define GPIO_DOUTSET31_0_DIO12_M 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Set bit 11 +#define GPIO_DOUTSET31_0_DIO11 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_BITN 11 +#define GPIO_DOUTSET31_0_DIO11_M 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Set bit 10 +#define GPIO_DOUTSET31_0_DIO10 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_BITN 10 +#define GPIO_DOUTSET31_0_DIO10_M 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Set bit 9 +#define GPIO_DOUTSET31_0_DIO9 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_BITN 9 +#define GPIO_DOUTSET31_0_DIO9_M 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Set bit 8 +#define GPIO_DOUTSET31_0_DIO8 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_BITN 8 +#define GPIO_DOUTSET31_0_DIO8_M 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Set bit 7 +#define GPIO_DOUTSET31_0_DIO7 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_BITN 7 +#define GPIO_DOUTSET31_0_DIO7_M 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Set bit 6 +#define GPIO_DOUTSET31_0_DIO6 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_BITN 6 +#define GPIO_DOUTSET31_0_DIO6_M 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Set bit 5 +#define GPIO_DOUTSET31_0_DIO5 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_BITN 5 +#define GPIO_DOUTSET31_0_DIO5_M 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Set bit 4 +#define GPIO_DOUTSET31_0_DIO4 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_BITN 4 +#define GPIO_DOUTSET31_0_DIO4_M 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Set bit 3 +#define GPIO_DOUTSET31_0_DIO3 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_BITN 3 +#define GPIO_DOUTSET31_0_DIO3_M 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Set bit 2 +#define GPIO_DOUTSET31_0_DIO2 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_BITN 2 +#define GPIO_DOUTSET31_0_DIO2_M 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Set bit 1 +#define GPIO_DOUTSET31_0_DIO1 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_BITN 1 +#define GPIO_DOUTSET31_0_DIO1_M 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Set bit 0 +#define GPIO_DOUTSET31_0_DIO0 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_BITN 0 +#define GPIO_DOUTSET31_0_DIO0_M 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTCLR31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Clears bit 31 +#define GPIO_DOUTCLR31_0_DIO31 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_BITN 31 +#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Clears bit 30 +#define GPIO_DOUTCLR31_0_DIO30 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_BITN 30 +#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Clears bit 29 +#define GPIO_DOUTCLR31_0_DIO29 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_BITN 29 +#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Clears bit 28 +#define GPIO_DOUTCLR31_0_DIO28 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_BITN 28 +#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Clears bit 27 +#define GPIO_DOUTCLR31_0_DIO27 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_BITN 27 +#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Clears bit 26 +#define GPIO_DOUTCLR31_0_DIO26 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_BITN 26 +#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Clears bit 25 +#define GPIO_DOUTCLR31_0_DIO25 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_BITN 25 +#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Clears bit 24 +#define GPIO_DOUTCLR31_0_DIO24 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_BITN 24 +#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Clears bit 23 +#define GPIO_DOUTCLR31_0_DIO23 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_BITN 23 +#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Clears bit 22 +#define GPIO_DOUTCLR31_0_DIO22 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_BITN 22 +#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Clears bit 21 +#define GPIO_DOUTCLR31_0_DIO21 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_BITN 21 +#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Clears bit 20 +#define GPIO_DOUTCLR31_0_DIO20 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_BITN 20 +#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Clears bit 19 +#define GPIO_DOUTCLR31_0_DIO19 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_BITN 19 +#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Clears bit 18 +#define GPIO_DOUTCLR31_0_DIO18 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_BITN 18 +#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Clears bit 17 +#define GPIO_DOUTCLR31_0_DIO17 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_BITN 17 +#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Clears bit 16 +#define GPIO_DOUTCLR31_0_DIO16 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_BITN 16 +#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Clears bit 15 +#define GPIO_DOUTCLR31_0_DIO15 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_BITN 15 +#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Clears bit 14 +#define GPIO_DOUTCLR31_0_DIO14 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_BITN 14 +#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Clears bit 13 +#define GPIO_DOUTCLR31_0_DIO13 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_BITN 13 +#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Clears bit 12 +#define GPIO_DOUTCLR31_0_DIO12 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_BITN 12 +#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Clears bit 11 +#define GPIO_DOUTCLR31_0_DIO11 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_BITN 11 +#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Clears bit 10 +#define GPIO_DOUTCLR31_0_DIO10 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_BITN 10 +#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Clears bit 9 +#define GPIO_DOUTCLR31_0_DIO9 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_BITN 9 +#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Clears bit 8 +#define GPIO_DOUTCLR31_0_DIO8 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_BITN 8 +#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Clears bit 7 +#define GPIO_DOUTCLR31_0_DIO7 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_BITN 7 +#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Clears bit 6 +#define GPIO_DOUTCLR31_0_DIO6 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_BITN 6 +#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Clears bit 5 +#define GPIO_DOUTCLR31_0_DIO5 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_BITN 5 +#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Clears bit 4 +#define GPIO_DOUTCLR31_0_DIO4 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_BITN 4 +#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Clears bit 3 +#define GPIO_DOUTCLR31_0_DIO3 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_BITN 3 +#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Clears bit 2 +#define GPIO_DOUTCLR31_0_DIO2 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_BITN 2 +#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Clears bit 1 +#define GPIO_DOUTCLR31_0_DIO1 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_BITN 1 +#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Clears bit 0 +#define GPIO_DOUTCLR31_0_DIO0 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_BITN 0 +#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTTGL31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Toggles bit 31 +#define GPIO_DOUTTGL31_0_DIO31 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_BITN 31 +#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Toggles bit 30 +#define GPIO_DOUTTGL31_0_DIO30 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_BITN 30 +#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Toggles bit 29 +#define GPIO_DOUTTGL31_0_DIO29 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_BITN 29 +#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Toggles bit 28 +#define GPIO_DOUTTGL31_0_DIO28 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_BITN 28 +#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Toggles bit 27 +#define GPIO_DOUTTGL31_0_DIO27 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_BITN 27 +#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Toggles bit 26 +#define GPIO_DOUTTGL31_0_DIO26 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_BITN 26 +#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Toggles bit 25 +#define GPIO_DOUTTGL31_0_DIO25 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_BITN 25 +#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Toggles bit 24 +#define GPIO_DOUTTGL31_0_DIO24 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_BITN 24 +#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Toggles bit 23 +#define GPIO_DOUTTGL31_0_DIO23 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_BITN 23 +#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Toggles bit 22 +#define GPIO_DOUTTGL31_0_DIO22 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_BITN 22 +#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Toggles bit 21 +#define GPIO_DOUTTGL31_0_DIO21 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_BITN 21 +#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Toggles bit 20 +#define GPIO_DOUTTGL31_0_DIO20 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_BITN 20 +#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Toggles bit 19 +#define GPIO_DOUTTGL31_0_DIO19 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_BITN 19 +#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Toggles bit 18 +#define GPIO_DOUTTGL31_0_DIO18 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_BITN 18 +#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Toggles bit 17 +#define GPIO_DOUTTGL31_0_DIO17 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_BITN 17 +#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Toggles bit 16 +#define GPIO_DOUTTGL31_0_DIO16 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_BITN 16 +#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Toggles bit 15 +#define GPIO_DOUTTGL31_0_DIO15 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_BITN 15 +#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Toggles bit 14 +#define GPIO_DOUTTGL31_0_DIO14 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_BITN 14 +#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Toggles bit 13 +#define GPIO_DOUTTGL31_0_DIO13 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_BITN 13 +#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Toggles bit 12 +#define GPIO_DOUTTGL31_0_DIO12 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_BITN 12 +#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Toggles bit 11 +#define GPIO_DOUTTGL31_0_DIO11 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_BITN 11 +#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Toggles bit 10 +#define GPIO_DOUTTGL31_0_DIO10 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_BITN 10 +#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Toggles bit 9 +#define GPIO_DOUTTGL31_0_DIO9 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_BITN 9 +#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Toggles bit 8 +#define GPIO_DOUTTGL31_0_DIO8 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_BITN 8 +#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Toggles bit 7 +#define GPIO_DOUTTGL31_0_DIO7 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_BITN 7 +#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Toggles bit 6 +#define GPIO_DOUTTGL31_0_DIO6 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_BITN 6 +#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Toggles bit 5 +#define GPIO_DOUTTGL31_0_DIO5 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_BITN 5 +#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Toggles bit 4 +#define GPIO_DOUTTGL31_0_DIO4 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_BITN 4 +#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Toggles bit 3 +#define GPIO_DOUTTGL31_0_DIO3 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_BITN 3 +#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Toggles bit 2 +#define GPIO_DOUTTGL31_0_DIO2 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_BITN 2 +#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Toggles bit 1 +#define GPIO_DOUTTGL31_0_DIO1 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_BITN 1 +#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Toggles bit 0 +#define GPIO_DOUTTGL31_0_DIO0 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_BITN 0 +#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DIN31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data input from DIO 31 +#define GPIO_DIN31_0_DIO31 0x80000000 +#define GPIO_DIN31_0_DIO31_BITN 31 +#define GPIO_DIN31_0_DIO31_M 0x80000000 +#define GPIO_DIN31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data input from DIO 30 +#define GPIO_DIN31_0_DIO30 0x40000000 +#define GPIO_DIN31_0_DIO30_BITN 30 +#define GPIO_DIN31_0_DIO30_M 0x40000000 +#define GPIO_DIN31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data input from DIO 29 +#define GPIO_DIN31_0_DIO29 0x20000000 +#define GPIO_DIN31_0_DIO29_BITN 29 +#define GPIO_DIN31_0_DIO29_M 0x20000000 +#define GPIO_DIN31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data input from DIO 28 +#define GPIO_DIN31_0_DIO28 0x10000000 +#define GPIO_DIN31_0_DIO28_BITN 28 +#define GPIO_DIN31_0_DIO28_M 0x10000000 +#define GPIO_DIN31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data input from DIO 27 +#define GPIO_DIN31_0_DIO27 0x08000000 +#define GPIO_DIN31_0_DIO27_BITN 27 +#define GPIO_DIN31_0_DIO27_M 0x08000000 +#define GPIO_DIN31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data input from DIO 26 +#define GPIO_DIN31_0_DIO26 0x04000000 +#define GPIO_DIN31_0_DIO26_BITN 26 +#define GPIO_DIN31_0_DIO26_M 0x04000000 +#define GPIO_DIN31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data input from DIO 25 +#define GPIO_DIN31_0_DIO25 0x02000000 +#define GPIO_DIN31_0_DIO25_BITN 25 +#define GPIO_DIN31_0_DIO25_M 0x02000000 +#define GPIO_DIN31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data input from DIO 24 +#define GPIO_DIN31_0_DIO24 0x01000000 +#define GPIO_DIN31_0_DIO24_BITN 24 +#define GPIO_DIN31_0_DIO24_M 0x01000000 +#define GPIO_DIN31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data input from DIO 23 +#define GPIO_DIN31_0_DIO23 0x00800000 +#define GPIO_DIN31_0_DIO23_BITN 23 +#define GPIO_DIN31_0_DIO23_M 0x00800000 +#define GPIO_DIN31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data input from DIO 22 +#define GPIO_DIN31_0_DIO22 0x00400000 +#define GPIO_DIN31_0_DIO22_BITN 22 +#define GPIO_DIN31_0_DIO22_M 0x00400000 +#define GPIO_DIN31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data input from DIO 21 +#define GPIO_DIN31_0_DIO21 0x00200000 +#define GPIO_DIN31_0_DIO21_BITN 21 +#define GPIO_DIN31_0_DIO21_M 0x00200000 +#define GPIO_DIN31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data input from DIO 20 +#define GPIO_DIN31_0_DIO20 0x00100000 +#define GPIO_DIN31_0_DIO20_BITN 20 +#define GPIO_DIN31_0_DIO20_M 0x00100000 +#define GPIO_DIN31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data input from DIO 19 +#define GPIO_DIN31_0_DIO19 0x00080000 +#define GPIO_DIN31_0_DIO19_BITN 19 +#define GPIO_DIN31_0_DIO19_M 0x00080000 +#define GPIO_DIN31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data input from DIO 18 +#define GPIO_DIN31_0_DIO18 0x00040000 +#define GPIO_DIN31_0_DIO18_BITN 18 +#define GPIO_DIN31_0_DIO18_M 0x00040000 +#define GPIO_DIN31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data input from DIO 17 +#define GPIO_DIN31_0_DIO17 0x00020000 +#define GPIO_DIN31_0_DIO17_BITN 17 +#define GPIO_DIN31_0_DIO17_M 0x00020000 +#define GPIO_DIN31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data input from DIO 16 +#define GPIO_DIN31_0_DIO16 0x00010000 +#define GPIO_DIN31_0_DIO16_BITN 16 +#define GPIO_DIN31_0_DIO16_M 0x00010000 +#define GPIO_DIN31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data input from DIO 15 +#define GPIO_DIN31_0_DIO15 0x00008000 +#define GPIO_DIN31_0_DIO15_BITN 15 +#define GPIO_DIN31_0_DIO15_M 0x00008000 +#define GPIO_DIN31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data input from DIO 14 +#define GPIO_DIN31_0_DIO14 0x00004000 +#define GPIO_DIN31_0_DIO14_BITN 14 +#define GPIO_DIN31_0_DIO14_M 0x00004000 +#define GPIO_DIN31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data input from DIO 13 +#define GPIO_DIN31_0_DIO13 0x00002000 +#define GPIO_DIN31_0_DIO13_BITN 13 +#define GPIO_DIN31_0_DIO13_M 0x00002000 +#define GPIO_DIN31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data input from DIO 12 +#define GPIO_DIN31_0_DIO12 0x00001000 +#define GPIO_DIN31_0_DIO12_BITN 12 +#define GPIO_DIN31_0_DIO12_M 0x00001000 +#define GPIO_DIN31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data input from DIO 11 +#define GPIO_DIN31_0_DIO11 0x00000800 +#define GPIO_DIN31_0_DIO11_BITN 11 +#define GPIO_DIN31_0_DIO11_M 0x00000800 +#define GPIO_DIN31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data input from DIO 10 +#define GPIO_DIN31_0_DIO10 0x00000400 +#define GPIO_DIN31_0_DIO10_BITN 10 +#define GPIO_DIN31_0_DIO10_M 0x00000400 +#define GPIO_DIN31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data input from DIO 9 +#define GPIO_DIN31_0_DIO9 0x00000200 +#define GPIO_DIN31_0_DIO9_BITN 9 +#define GPIO_DIN31_0_DIO9_M 0x00000200 +#define GPIO_DIN31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data input from DIO 8 +#define GPIO_DIN31_0_DIO8 0x00000100 +#define GPIO_DIN31_0_DIO8_BITN 8 +#define GPIO_DIN31_0_DIO8_M 0x00000100 +#define GPIO_DIN31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data input from DIO 7 +#define GPIO_DIN31_0_DIO7 0x00000080 +#define GPIO_DIN31_0_DIO7_BITN 7 +#define GPIO_DIN31_0_DIO7_M 0x00000080 +#define GPIO_DIN31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data input from DIO 6 +#define GPIO_DIN31_0_DIO6 0x00000040 +#define GPIO_DIN31_0_DIO6_BITN 6 +#define GPIO_DIN31_0_DIO6_M 0x00000040 +#define GPIO_DIN31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data input from DIO 5 +#define GPIO_DIN31_0_DIO5 0x00000020 +#define GPIO_DIN31_0_DIO5_BITN 5 +#define GPIO_DIN31_0_DIO5_M 0x00000020 +#define GPIO_DIN31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data input from DIO 4 +#define GPIO_DIN31_0_DIO4 0x00000010 +#define GPIO_DIN31_0_DIO4_BITN 4 +#define GPIO_DIN31_0_DIO4_M 0x00000010 +#define GPIO_DIN31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data input from DIO 3 +#define GPIO_DIN31_0_DIO3 0x00000008 +#define GPIO_DIN31_0_DIO3_BITN 3 +#define GPIO_DIN31_0_DIO3_M 0x00000008 +#define GPIO_DIN31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data input from DIO 2 +#define GPIO_DIN31_0_DIO2 0x00000004 +#define GPIO_DIN31_0_DIO2_BITN 2 +#define GPIO_DIN31_0_DIO2_M 0x00000004 +#define GPIO_DIN31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data input from DIO 1 +#define GPIO_DIN31_0_DIO1 0x00000002 +#define GPIO_DIN31_0_DIO1_BITN 1 +#define GPIO_DIN31_0_DIO1_M 0x00000002 +#define GPIO_DIN31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data input from DIO 0 +#define GPIO_DIN31_0_DIO0 0x00000001 +#define GPIO_DIN31_0_DIO0_BITN 0 +#define GPIO_DIN31_0_DIO0_M 0x00000001 +#define GPIO_DIN31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOE31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data output enable for DIO 31 +#define GPIO_DOE31_0_DIO31 0x80000000 +#define GPIO_DOE31_0_DIO31_BITN 31 +#define GPIO_DOE31_0_DIO31_M 0x80000000 +#define GPIO_DOE31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data output enable for DIO 30 +#define GPIO_DOE31_0_DIO30 0x40000000 +#define GPIO_DOE31_0_DIO30_BITN 30 +#define GPIO_DOE31_0_DIO30_M 0x40000000 +#define GPIO_DOE31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data output enable for DIO 29 +#define GPIO_DOE31_0_DIO29 0x20000000 +#define GPIO_DOE31_0_DIO29_BITN 29 +#define GPIO_DOE31_0_DIO29_M 0x20000000 +#define GPIO_DOE31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data output enable for DIO 28 +#define GPIO_DOE31_0_DIO28 0x10000000 +#define GPIO_DOE31_0_DIO28_BITN 28 +#define GPIO_DOE31_0_DIO28_M 0x10000000 +#define GPIO_DOE31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data output enable for DIO 27 +#define GPIO_DOE31_0_DIO27 0x08000000 +#define GPIO_DOE31_0_DIO27_BITN 27 +#define GPIO_DOE31_0_DIO27_M 0x08000000 +#define GPIO_DOE31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data output enable for DIO 26 +#define GPIO_DOE31_0_DIO26 0x04000000 +#define GPIO_DOE31_0_DIO26_BITN 26 +#define GPIO_DOE31_0_DIO26_M 0x04000000 +#define GPIO_DOE31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data output enable for DIO 25 +#define GPIO_DOE31_0_DIO25 0x02000000 +#define GPIO_DOE31_0_DIO25_BITN 25 +#define GPIO_DOE31_0_DIO25_M 0x02000000 +#define GPIO_DOE31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data output enable for DIO 24 +#define GPIO_DOE31_0_DIO24 0x01000000 +#define GPIO_DOE31_0_DIO24_BITN 24 +#define GPIO_DOE31_0_DIO24_M 0x01000000 +#define GPIO_DOE31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data output enable for DIO 23 +#define GPIO_DOE31_0_DIO23 0x00800000 +#define GPIO_DOE31_0_DIO23_BITN 23 +#define GPIO_DOE31_0_DIO23_M 0x00800000 +#define GPIO_DOE31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data output enable for DIO 22 +#define GPIO_DOE31_0_DIO22 0x00400000 +#define GPIO_DOE31_0_DIO22_BITN 22 +#define GPIO_DOE31_0_DIO22_M 0x00400000 +#define GPIO_DOE31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data output enable for DIO 21 +#define GPIO_DOE31_0_DIO21 0x00200000 +#define GPIO_DOE31_0_DIO21_BITN 21 +#define GPIO_DOE31_0_DIO21_M 0x00200000 +#define GPIO_DOE31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data output enable for DIO 20 +#define GPIO_DOE31_0_DIO20 0x00100000 +#define GPIO_DOE31_0_DIO20_BITN 20 +#define GPIO_DOE31_0_DIO20_M 0x00100000 +#define GPIO_DOE31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data output enable for DIO 19 +#define GPIO_DOE31_0_DIO19 0x00080000 +#define GPIO_DOE31_0_DIO19_BITN 19 +#define GPIO_DOE31_0_DIO19_M 0x00080000 +#define GPIO_DOE31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data output enable for DIO 18 +#define GPIO_DOE31_0_DIO18 0x00040000 +#define GPIO_DOE31_0_DIO18_BITN 18 +#define GPIO_DOE31_0_DIO18_M 0x00040000 +#define GPIO_DOE31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data output enable for DIO 17 +#define GPIO_DOE31_0_DIO17 0x00020000 +#define GPIO_DOE31_0_DIO17_BITN 17 +#define GPIO_DOE31_0_DIO17_M 0x00020000 +#define GPIO_DOE31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data output enable for DIO 16 +#define GPIO_DOE31_0_DIO16 0x00010000 +#define GPIO_DOE31_0_DIO16_BITN 16 +#define GPIO_DOE31_0_DIO16_M 0x00010000 +#define GPIO_DOE31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data output enable for DIO 15 +#define GPIO_DOE31_0_DIO15 0x00008000 +#define GPIO_DOE31_0_DIO15_BITN 15 +#define GPIO_DOE31_0_DIO15_M 0x00008000 +#define GPIO_DOE31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data output enable for DIO 14 +#define GPIO_DOE31_0_DIO14 0x00004000 +#define GPIO_DOE31_0_DIO14_BITN 14 +#define GPIO_DOE31_0_DIO14_M 0x00004000 +#define GPIO_DOE31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data output enable for DIO 13 +#define GPIO_DOE31_0_DIO13 0x00002000 +#define GPIO_DOE31_0_DIO13_BITN 13 +#define GPIO_DOE31_0_DIO13_M 0x00002000 +#define GPIO_DOE31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data output enable for DIO 12 +#define GPIO_DOE31_0_DIO12 0x00001000 +#define GPIO_DOE31_0_DIO12_BITN 12 +#define GPIO_DOE31_0_DIO12_M 0x00001000 +#define GPIO_DOE31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data output enable for DIO 11 +#define GPIO_DOE31_0_DIO11 0x00000800 +#define GPIO_DOE31_0_DIO11_BITN 11 +#define GPIO_DOE31_0_DIO11_M 0x00000800 +#define GPIO_DOE31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data output enable for DIO 10 +#define GPIO_DOE31_0_DIO10 0x00000400 +#define GPIO_DOE31_0_DIO10_BITN 10 +#define GPIO_DOE31_0_DIO10_M 0x00000400 +#define GPIO_DOE31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data output enable for DIO 9 +#define GPIO_DOE31_0_DIO9 0x00000200 +#define GPIO_DOE31_0_DIO9_BITN 9 +#define GPIO_DOE31_0_DIO9_M 0x00000200 +#define GPIO_DOE31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data output enable for DIO 8 +#define GPIO_DOE31_0_DIO8 0x00000100 +#define GPIO_DOE31_0_DIO8_BITN 8 +#define GPIO_DOE31_0_DIO8_M 0x00000100 +#define GPIO_DOE31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data output enable for DIO 7 +#define GPIO_DOE31_0_DIO7 0x00000080 +#define GPIO_DOE31_0_DIO7_BITN 7 +#define GPIO_DOE31_0_DIO7_M 0x00000080 +#define GPIO_DOE31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data output enable for DIO 6 +#define GPIO_DOE31_0_DIO6 0x00000040 +#define GPIO_DOE31_0_DIO6_BITN 6 +#define GPIO_DOE31_0_DIO6_M 0x00000040 +#define GPIO_DOE31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data output enable for DIO 5 +#define GPIO_DOE31_0_DIO5 0x00000020 +#define GPIO_DOE31_0_DIO5_BITN 5 +#define GPIO_DOE31_0_DIO5_M 0x00000020 +#define GPIO_DOE31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data output enable for DIO 4 +#define GPIO_DOE31_0_DIO4 0x00000010 +#define GPIO_DOE31_0_DIO4_BITN 4 +#define GPIO_DOE31_0_DIO4_M 0x00000010 +#define GPIO_DOE31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data output enable for DIO 3 +#define GPIO_DOE31_0_DIO3 0x00000008 +#define GPIO_DOE31_0_DIO3_BITN 3 +#define GPIO_DOE31_0_DIO3_M 0x00000008 +#define GPIO_DOE31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data output enable for DIO 2 +#define GPIO_DOE31_0_DIO2 0x00000004 +#define GPIO_DOE31_0_DIO2_BITN 2 +#define GPIO_DOE31_0_DIO2_M 0x00000004 +#define GPIO_DOE31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data output enable for DIO 1 +#define GPIO_DOE31_0_DIO1 0x00000002 +#define GPIO_DOE31_0_DIO1_BITN 1 +#define GPIO_DOE31_0_DIO1_M 0x00000002 +#define GPIO_DOE31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data output enable for DIO 0 +#define GPIO_DOE31_0_DIO0 0x00000001 +#define GPIO_DOE31_0_DIO0_BITN 0 +#define GPIO_DOE31_0_DIO0_M 0x00000001 +#define GPIO_DOE31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_EVFLAGS31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Event for DIO 31 +#define GPIO_EVFLAGS31_0_DIO31 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_BITN 31 +#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Event for DIO 30 +#define GPIO_EVFLAGS31_0_DIO30 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_BITN 30 +#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Event for DIO 29 +#define GPIO_EVFLAGS31_0_DIO29 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_BITN 29 +#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Event for DIO 28 +#define GPIO_EVFLAGS31_0_DIO28 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_BITN 28 +#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Event for DIO 27 +#define GPIO_EVFLAGS31_0_DIO27 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_BITN 27 +#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Event for DIO 26 +#define GPIO_EVFLAGS31_0_DIO26 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_BITN 26 +#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Event for DIO 25 +#define GPIO_EVFLAGS31_0_DIO25 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_BITN 25 +#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Event for DIO 24 +#define GPIO_EVFLAGS31_0_DIO24 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_BITN 24 +#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Event for DIO 23 +#define GPIO_EVFLAGS31_0_DIO23 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_BITN 23 +#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Event for DIO 22 +#define GPIO_EVFLAGS31_0_DIO22 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_BITN 22 +#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Event for DIO 21 +#define GPIO_EVFLAGS31_0_DIO21 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_BITN 21 +#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Event for DIO 20 +#define GPIO_EVFLAGS31_0_DIO20 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_BITN 20 +#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Event for DIO 19 +#define GPIO_EVFLAGS31_0_DIO19 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_BITN 19 +#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Event for DIO 18 +#define GPIO_EVFLAGS31_0_DIO18 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_BITN 18 +#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Event for DIO 17 +#define GPIO_EVFLAGS31_0_DIO17 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_BITN 17 +#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Event for DIO 16 +#define GPIO_EVFLAGS31_0_DIO16 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_BITN 16 +#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Event for DIO 15 +#define GPIO_EVFLAGS31_0_DIO15 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_BITN 15 +#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Event for DIO 14 +#define GPIO_EVFLAGS31_0_DIO14 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_BITN 14 +#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Event for DIO 13 +#define GPIO_EVFLAGS31_0_DIO13 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_BITN 13 +#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Event for DIO 12 +#define GPIO_EVFLAGS31_0_DIO12 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_BITN 12 +#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Event for DIO 11 +#define GPIO_EVFLAGS31_0_DIO11 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_BITN 11 +#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Event for DIO 10 +#define GPIO_EVFLAGS31_0_DIO10 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_BITN 10 +#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Event for DIO 9 +#define GPIO_EVFLAGS31_0_DIO9 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_BITN 9 +#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Event for DIO 8 +#define GPIO_EVFLAGS31_0_DIO8 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_BITN 8 +#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Event for DIO 7 +#define GPIO_EVFLAGS31_0_DIO7 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_BITN 7 +#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Event for DIO 6 +#define GPIO_EVFLAGS31_0_DIO6 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_BITN 6 +#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Event for DIO 5 +#define GPIO_EVFLAGS31_0_DIO5 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_BITN 5 +#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Event for DIO 4 +#define GPIO_EVFLAGS31_0_DIO4 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_BITN 4 +#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Event for DIO 3 +#define GPIO_EVFLAGS31_0_DIO3 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_BITN 3 +#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Event for DIO 2 +#define GPIO_EVFLAGS31_0_DIO2 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_BITN 2 +#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Event for DIO 1 +#define GPIO_EVFLAGS31_0_DIO1 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_BITN 1 +#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Event for DIO 0 +#define GPIO_EVFLAGS31_0_DIO0 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_BITN 0 +#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_S 0 + + +#endif // __GPIO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h new file mode 100644 index 0000000..cbd0988 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* Filename: hw_gpram_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_GPRAM_H__ +#define __HW_GPRAM_H__ + + +#define GPRAM_O_BANK0 0x00000000 +#define GPRAM_BANK0_BYTE_SIZE 8192 + +#define GPRAM_TOT_BYTE_SIZE 8192 + + + +#endif // __HW_GPRAM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h new file mode 100644 index 0000000..d9cc05d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h @@ -0,0 +1,1697 @@ +/****************************************************************************** +* Filename: hw_gpt_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_GPT_H__ +#define __HW_GPT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// GPT component +// +//***************************************************************************** +// Configuration +#define GPT_O_CFG 0x00000000 + +// Timer A Mode +#define GPT_O_TAMR 0x00000004 + +// Timer B Mode +#define GPT_O_TBMR 0x00000008 + +// Control +#define GPT_O_CTL 0x0000000C + +// Synch Register +#define GPT_O_SYNC 0x00000010 + +// Interrupt Mask +#define GPT_O_IMR 0x00000018 + +// Raw Interrupt Status +#define GPT_O_RIS 0x0000001C + +// Masked Interrupt Status +#define GPT_O_MIS 0x00000020 + +// Interrupt Clear +#define GPT_O_ICLR 0x00000024 + +// Timer A Interval Load Register +#define GPT_O_TAILR 0x00000028 + +// Timer B Interval Load Register +#define GPT_O_TBILR 0x0000002C + +// Timer A Match Register +#define GPT_O_TAMATCHR 0x00000030 + +// Timer B Match Register +#define GPT_O_TBMATCHR 0x00000034 + +// Timer A Pre-scale +#define GPT_O_TAPR 0x00000038 + +// Timer B Pre-scale +#define GPT_O_TBPR 0x0000003C + +// Timer A Pre-scale Match +#define GPT_O_TAPMR 0x00000040 + +// Timer B Pre-scale Match +#define GPT_O_TBPMR 0x00000044 + +// Timer A Register +#define GPT_O_TAR 0x00000048 + +// Timer B Register +#define GPT_O_TBR 0x0000004C + +// Timer A Value +#define GPT_O_TAV 0x00000050 + +// Timer B Value +#define GPT_O_TBV 0x00000054 + +// Timer A Pre-scale Snap-shot +#define GPT_O_TAPS 0x0000005C + +// Timer B Pre-scale Snap-shot +#define GPT_O_TBPS 0x00000060 + +// Timer A Pre-scale Value +#define GPT_O_TAPV 0x00000064 + +// Timer B Pre-scale Value +#define GPT_O_TBPV 0x00000068 + +// DMA Event +#define GPT_O_DMAEV 0x0000006C + +// Peripheral Version +#define GPT_O_VERSION 0x00000FB0 + +// Combined CCP Output +#define GPT_O_ANDCCP 0x00000FB4 + +//***************************************************************************** +// +// Register: GPT_O_CFG +// +//***************************************************************************** +// Field: [2:0] CFG +// +// GPT Configuration +// 0x2- 0x3 - Reserved +// 0x5- 0x7 - Reserved +// ENUMs: +// 16BIT_TIMER 16-bit timer configuration. +// Configure for two 16-bit +// timers. +// Also see TAMR.TAMR and +// TBMR.TBMR. +// 32BIT_TIMER 32-bit timer configuration +#define GPT_CFG_CFG_W 3 +#define GPT_CFG_CFG_M 0x00000007 +#define GPT_CFG_CFG_S 0 +#define GPT_CFG_CFG_16BIT_TIMER 0x00000004 +#define GPT_CFG_CFG_32BIT_TIMER 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_TAMR +// +//***************************************************************************** +// Field: [15:13] TCACT +// +// Timer Compare Action Select +// ENUMs: +// CLRSET_ON_TO Clear CCP output pin immediately and set on +// Time-Out +// SETCLR_ON_TO Set CCP output pin immediately and clear on +// Time-Out +// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on +// Time-Out +// SETTOG_ON_TO Set CCP output pin immediately and toggle on +// Time-Out +// SET_ON_TO Set CCP output pin on Time-Out +// CLR_ON_TO Clear CCP output pin on Time-Out +// TOG_ON_TO Toggle State on Time-Out +// DIS_CMP Disable compare operations +#define GPT_TAMR_TCACT_W 3 +#define GPT_TAMR_TCACT_M 0x0000E000 +#define GPT_TAMR_TCACT_S 13 +#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TAMR_TCACT_DIS_CMP 0x00000000 + +// Field: [12] TACINTD +// +// One-Shot/Periodic Interrupt Disable +// ENUMs: +// DIS_TO_INTR Time-out interrupt are disabled +// EN_TO_INTR Time-out interrupt function as normal +#define GPT_TAMR_TACINTD 0x00001000 +#define GPT_TAMR_TACINTD_BITN 12 +#define GPT_TAMR_TACINTD_M 0x00001000 +#define GPT_TAMR_TACINTD_S 12 +#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 +#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 + +// Field: [11] TAPLO +// +// GPTM Timer A PWM Legacy Operation +// +// 0 Legacy operation with CCP pin driven Low when the TAILR +// register is reloaded after the timer reaches 0. +// +// 1 CCP is driven High when the TAILR register is reloaded after the timer +// reaches 0. +// +// This bit is only valid in PWM mode. +// ENUMs: +// CCP_ON_TO CCP output pin is set to 1 on time-out +// LEGACY Legacy operation +#define GPT_TAMR_TAPLO 0x00000800 +#define GPT_TAMR_TAPLO_BITN 11 +#define GPT_TAMR_TAPLO_M 0x00000800 +#define GPT_TAMR_TAPLO_S 11 +#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 +#define GPT_TAMR_TAPLO_LEGACY 0x00000000 + +// Field: [10] TAMRSU +// +// Timer A Match Register Update mode +// +// This bit defines when the TAMATCHR and TAPR registers are updated. +// +// If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and +// TAPR are updated when the timer is enabled. +// If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and +// TAPR are updated according to the configuration of this bit. +// ENUMs: +// TOUPDATE Update TAMATCHR and TAPR, if used, on the next +// time-out. +// CYCLEUPDATE Update TAMATCHR and TAPR, if used, on the next +// cycle. +#define GPT_TAMR_TAMRSU 0x00000400 +#define GPT_TAMR_TAMRSU_BITN 10 +#define GPT_TAMR_TAMRSU_M 0x00000400 +#define GPT_TAMR_TAMRSU_S 10 +#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 +#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 + +// Field: [9] TAPWMIE +// +// GPTM Timer A PWM Interrupt Enable +// This bit enables interrupts in PWM mode on rising, falling, or both edges of +// the CCP output, as defined by the CTL.TAEVENT +// In addition, when this bit is set and a capture event occurs, Timer A +// automatically generates triggers to the DMA if the trigger capability is +// enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit +// respectively. +// +// 0 Capture event interrupt is disabled. +// 1 Capture event interrupt is enabled. +// This bit is only valid in PWM mode. +// ENUMs: +// EN Interrupt is enabled. This bit is only valid in +// PWM mode. +// DIS Interrupt is disabled. +#define GPT_TAMR_TAPWMIE 0x00000200 +#define GPT_TAMR_TAPWMIE_BITN 9 +#define GPT_TAMR_TAPWMIE_M 0x00000200 +#define GPT_TAMR_TAPWMIE_S 9 +#define GPT_TAMR_TAPWMIE_EN 0x00000200 +#define GPT_TAMR_TAPWMIE_DIS 0x00000000 + +// Field: [8] TAILD +// +// GPT Timer A PWM Interval Load Write +// ENUMs: +// TOUPDATE Update the TAR register with the value in the +// TAILR register on the next timeout. If the +// prescaler is used, update the TAPS register +// with the value in the TAPR register on the next +// timeout. +// CYCLEUPDATE Update the TAR register with the value in the +// TAILR register on the next clock cycle. If the +// pre-scaler is used, update the TAPS register +// with the value in the TAPR register on the next +// clock cycle. +#define GPT_TAMR_TAILD 0x00000100 +#define GPT_TAMR_TAILD_BITN 8 +#define GPT_TAMR_TAILD_M 0x00000100 +#define GPT_TAMR_TAILD_S 8 +#define GPT_TAMR_TAILD_TOUPDATE 0x00000100 +#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 + +// Field: [7] TASNAPS +// +// GPT Timer A Snap-Shot Mode +// ENUMs: +// EN If Timer A is configured in the periodic mode, the +// actual free-running value of Timer A is loaded +// at the time-out event into the GPT Timer A +// (TAR) register. +// DIS Snap-shot mode is disabled. +#define GPT_TAMR_TASNAPS 0x00000080 +#define GPT_TAMR_TASNAPS_BITN 7 +#define GPT_TAMR_TASNAPS_M 0x00000080 +#define GPT_TAMR_TASNAPS_S 7 +#define GPT_TAMR_TASNAPS_EN 0x00000080 +#define GPT_TAMR_TASNAPS_DIS 0x00000000 + +// Field: [6] TAWOT +// +// GPT Timer A Wait-On-Trigger +// ENUMs: +// WAIT If Timer A is enabled (CTL.TAEN = 1), Timer A does +// not begin counting until it receives a trigger +// from the timer in the previous position in the +// daisy chain. This bit must be clear for GPT +// Module 0, Timer A. This function is valid for +// one-shot, periodic, and PWM modes +// NOWAIT Timer A begins counting as soon as it is enabled. +#define GPT_TAMR_TAWOT 0x00000040 +#define GPT_TAMR_TAWOT_BITN 6 +#define GPT_TAMR_TAWOT_M 0x00000040 +#define GPT_TAMR_TAWOT_S 6 +#define GPT_TAMR_TAWOT_WAIT 0x00000040 +#define GPT_TAMR_TAWOT_NOWAIT 0x00000000 + +// Field: [5] TAMIE +// +// GPT Timer A Match Interrupt Enable +// ENUMs: +// EN An interrupt is generated when the match value in +// TAMATCHR is reached in the one-shot and +// periodic modes. +// DIS The match interrupt is disabled for match events. +// Additionally, output triggers on match events +// are prevented. +#define GPT_TAMR_TAMIE 0x00000020 +#define GPT_TAMR_TAMIE_BITN 5 +#define GPT_TAMR_TAMIE_M 0x00000020 +#define GPT_TAMR_TAMIE_S 5 +#define GPT_TAMR_TAMIE_EN 0x00000020 +#define GPT_TAMR_TAMIE_DIS 0x00000000 + +// Field: [4] TACDIR +// +// GPT Timer A Count Direction +// ENUMs: +// UP The timer counts up. When counting up, the timer +// starts from a value of 0x0. +// DOWN The timer counts down. +#define GPT_TAMR_TACDIR 0x00000010 +#define GPT_TAMR_TACDIR_BITN 4 +#define GPT_TAMR_TACDIR_M 0x00000010 +#define GPT_TAMR_TACDIR_S 4 +#define GPT_TAMR_TACDIR_UP 0x00000010 +#define GPT_TAMR_TACDIR_DOWN 0x00000000 + +// Field: [3] TAAMS +// +// GPT Timer A Alternate Mode +// +// Note: To enable PWM mode, you must also clear TACM and then configure TAMR +// field to 0x2. +// ENUMs: +// PWM PWM mode is enabled +// CAP_COMP Capture/Compare mode is enabled. +#define GPT_TAMR_TAAMS 0x00000008 +#define GPT_TAMR_TAAMS_BITN 3 +#define GPT_TAMR_TAAMS_M 0x00000008 +#define GPT_TAMR_TAAMS_S 3 +#define GPT_TAMR_TAAMS_PWM 0x00000008 +#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 + +// Field: [2] TACM +// +// GPT Timer A Capture Mode +// ENUMs: +// EDGTIME Edge-Time mode +// EDGCNT Edge-Count mode +#define GPT_TAMR_TACM 0x00000004 +#define GPT_TAMR_TACM_BITN 2 +#define GPT_TAMR_TACM_M 0x00000004 +#define GPT_TAMR_TACM_S 2 +#define GPT_TAMR_TACM_EDGTIME 0x00000004 +#define GPT_TAMR_TACM_EDGCNT 0x00000000 + +// Field: [1:0] TAMR +// +// GPT Timer A Mode +// +// 0x0 Reserved +// 0x1 One-Shot Timer mode +// 0x2 Periodic Timer mode +// 0x3 Capture mode +// The Timer mode is based on the timer configuration defined by bits 2:0 in +// the CFG register +// ENUMs: +// CAPTURE Capture mode +// PERIODIC Periodic Timer mode +// ONE_SHOT One-Shot Timer mode +#define GPT_TAMR_TAMR_W 2 +#define GPT_TAMR_TAMR_M 0x00000003 +#define GPT_TAMR_TAMR_S 0 +#define GPT_TAMR_TAMR_CAPTURE 0x00000003 +#define GPT_TAMR_TAMR_PERIODIC 0x00000002 +#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 + +//***************************************************************************** +// +// Register: GPT_O_TBMR +// +//***************************************************************************** +// Field: [15:13] TCACT +// +// Timer Compare Action Select +// ENUMs: +// CLRSET_ON_TO Clear CCP output pin immediately and set on +// Time-Out +// SETCLR_ON_TO Set CCP output pin immediately and clear on +// Time-Out +// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on +// Time-Out +// SETTOG_ON_TO Set CCP output pin immediately and toggle on +// Time-Out +// SET_ON_TO Set CCP output pin on Time-Out +// CLR_ON_TO Clear CCP output pin on Time-Out +// TOG_ON_TO Toggle State on Time-Out +// DIS_CMP Disable compare operations +#define GPT_TBMR_TCACT_W 3 +#define GPT_TBMR_TCACT_M 0x0000E000 +#define GPT_TBMR_TCACT_S 13 +#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TBMR_TCACT_DIS_CMP 0x00000000 + +// Field: [12] TBCINTD +// +// One-Shot/Periodic Interrupt Mode +// ENUMs: +// DIS_TO_INTR Mask Time-Out Interrupt +// EN_TO_INTR Normal Time-Out Interrupt +#define GPT_TBMR_TBCINTD 0x00001000 +#define GPT_TBMR_TBCINTD_BITN 12 +#define GPT_TBMR_TBCINTD_M 0x00001000 +#define GPT_TBMR_TBCINTD_S 12 +#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 +#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 + +// Field: [11] TBPLO +// +// GPTM Timer B PWM Legacy Operation +// +// 0 Legacy operation with CCP pin driven Low when the TBILR +// register is reloaded after the timer reaches 0. +// +// 1 CCP is driven High when the TBILR register is reloaded after the timer +// reaches 0. +// +// This bit is only valid in PWM mode. +// ENUMs: +// CCP_ON_TO CCP output pin is set to 1 on time-out +// LEGACY Legacy operation +#define GPT_TBMR_TBPLO 0x00000800 +#define GPT_TBMR_TBPLO_BITN 11 +#define GPT_TBMR_TBPLO_M 0x00000800 +#define GPT_TBMR_TBPLO_S 11 +#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 +#define GPT_TBMR_TBPLO_LEGACY 0x00000000 + +// Field: [10] TBMRSU +// +// Timer B Match Register Update mode +// +// This bit defines when the TBMATCHR and TBPR registers are updated +// +// If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR +// and TBPR are updated when the timer is enabled. +// If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR +// and TBPR are updated according to the configuration of this bit. +// ENUMs: +// TOUPDATE Update TBMATCHR and TBPR, if used, on the next +// time-out. +// CYCLEUPDATE Update TBMATCHR and TBPR, if used, on the next +// cycle. +#define GPT_TBMR_TBMRSU 0x00000400 +#define GPT_TBMR_TBMRSU_BITN 10 +#define GPT_TBMR_TBMRSU_M 0x00000400 +#define GPT_TBMR_TBMRSU_S 10 +#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 +#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 + +// Field: [9] TBPWMIE +// +// GPTM Timer B PWM Interrupt Enable +// This bit enables interrupts in PWM mode on rising, falling, or both edges of +// the CCP output, as defined by the CTL.TBEVENT +// In addition, when this bit is set and a capture event occurs, Timer A +// automatically generates triggers to the DMA if the trigger capability is +// enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit +// respectively. +// +// 0 Capture event interrupt is disabled. +// 1 Capture event interrupt is enabled. +// This bit is only valid in PWM mode. +// ENUMs: +// EN Interrupt is enabled. This bit is only valid in +// PWM mode. +// DIS Interrupt is disabled. +#define GPT_TBMR_TBPWMIE 0x00000200 +#define GPT_TBMR_TBPWMIE_BITN 9 +#define GPT_TBMR_TBPWMIE_M 0x00000200 +#define GPT_TBMR_TBPWMIE_S 9 +#define GPT_TBMR_TBPWMIE_EN 0x00000200 +#define GPT_TBMR_TBPWMIE_DIS 0x00000000 + +// Field: [8] TBILD +// +// GPT Timer B PWM Interval Load Write +// ENUMs: +// TOUPDATE Update the TBR register with the value in the +// TBILR register on the next timeout. If the +// prescaler is used, update the TBPS register +// with the value in the TBPR register on the next +// timeout. +// CYCLEUPDATE Update the TBR register with the value in the +// TBILR register on the next clock cycle. If the +// pre-scaler is used, update the TBPS register +// with the value in the TBPR register on the next +// clock cycle. +#define GPT_TBMR_TBILD 0x00000100 +#define GPT_TBMR_TBILD_BITN 8 +#define GPT_TBMR_TBILD_M 0x00000100 +#define GPT_TBMR_TBILD_S 8 +#define GPT_TBMR_TBILD_TOUPDATE 0x00000100 +#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 + +// Field: [7] TBSNAPS +// +// GPT Timer B Snap-Shot Mode +// ENUMs: +// EN If Timer B is configured in the periodic mode +// DIS Snap-shot mode is disabled. +#define GPT_TBMR_TBSNAPS 0x00000080 +#define GPT_TBMR_TBSNAPS_BITN 7 +#define GPT_TBMR_TBSNAPS_M 0x00000080 +#define GPT_TBMR_TBSNAPS_S 7 +#define GPT_TBMR_TBSNAPS_EN 0x00000080 +#define GPT_TBMR_TBSNAPS_DIS 0x00000000 + +// Field: [6] TBWOT +// +// GPT Timer B Wait-On-Trigger +// ENUMs: +// WAIT If Timer B is enabled (CTL.TBEN is set), Timer B +// does not begin counting until it receives a +// trigger from the timer in the previous position +// in the daisy chain. This function is valid for +// one-shot, periodic, and PWM modes +// NOWAIT Timer B begins counting as soon as it is enabled. +#define GPT_TBMR_TBWOT 0x00000040 +#define GPT_TBMR_TBWOT_BITN 6 +#define GPT_TBMR_TBWOT_M 0x00000040 +#define GPT_TBMR_TBWOT_S 6 +#define GPT_TBMR_TBWOT_WAIT 0x00000040 +#define GPT_TBMR_TBWOT_NOWAIT 0x00000000 + +// Field: [5] TBMIE +// +// GPT Timer B Match Interrupt Enable. +// ENUMs: +// EN An interrupt is generated when the match value in +// the TBMATCHR register is reached in the +// one-shot and periodic modes. +// DIS The match interrupt is disabled for match events. +// Additionally, output triggers on match events +// are prevented. +#define GPT_TBMR_TBMIE 0x00000020 +#define GPT_TBMR_TBMIE_BITN 5 +#define GPT_TBMR_TBMIE_M 0x00000020 +#define GPT_TBMR_TBMIE_S 5 +#define GPT_TBMR_TBMIE_EN 0x00000020 +#define GPT_TBMR_TBMIE_DIS 0x00000000 + +// Field: [4] TBCDIR +// +// GPT Timer B Count Direction +// ENUMs: +// UP The timer counts up. When counting up, the timer +// starts from a value of 0x0. +// DOWN The timer counts down. +#define GPT_TBMR_TBCDIR 0x00000010 +#define GPT_TBMR_TBCDIR_BITN 4 +#define GPT_TBMR_TBCDIR_M 0x00000010 +#define GPT_TBMR_TBCDIR_S 4 +#define GPT_TBMR_TBCDIR_UP 0x00000010 +#define GPT_TBMR_TBCDIR_DOWN 0x00000000 + +// Field: [3] TBAMS +// +// GPT Timer B Alternate Mode +// +// Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR +// field to 0x2. +// ENUMs: +// PWM PWM mode is enabled +// CAP_COMP Capture/Compare mode is enabled. +#define GPT_TBMR_TBAMS 0x00000008 +#define GPT_TBMR_TBAMS_BITN 3 +#define GPT_TBMR_TBAMS_M 0x00000008 +#define GPT_TBMR_TBAMS_S 3 +#define GPT_TBMR_TBAMS_PWM 0x00000008 +#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 + +// Field: [2] TBCM +// +// GPT Timer B Capture Mode +// ENUMs: +// EDGTIME Edge-Time mode +// EDGCNT Edge-Count mode +#define GPT_TBMR_TBCM 0x00000004 +#define GPT_TBMR_TBCM_BITN 2 +#define GPT_TBMR_TBCM_M 0x00000004 +#define GPT_TBMR_TBCM_S 2 +#define GPT_TBMR_TBCM_EDGTIME 0x00000004 +#define GPT_TBMR_TBCM_EDGCNT 0x00000000 + +// Field: [1:0] TBMR +// +// GPT Timer B Mode +// +// 0x0 Reserved +// 0x1 One-Shot Timer mode +// 0x2 Periodic Timer mode +// 0x3 Capture mode +// The Timer mode is based on the timer configuration defined by bits 2:0 in +// the CFG register +// ENUMs: +// CAPTURE Capture mode +// PERIODIC Periodic Timer mode +// ONE_SHOT One-Shot Timer mode +#define GPT_TBMR_TBMR_W 2 +#define GPT_TBMR_TBMR_M 0x00000003 +#define GPT_TBMR_TBMR_S 0 +#define GPT_TBMR_TBMR_CAPTURE 0x00000003 +#define GPT_TBMR_TBMR_PERIODIC 0x00000002 +#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 + +//***************************************************************************** +// +// Register: GPT_O_CTL +// +//***************************************************************************** +// Field: [14] TBPWML +// +// GPT Timer B PWM Output Level +// +// 0: Output is unaffected. +// 1: Output is inverted. +// ENUMs: +// INVERTED Inverted +// NORMAL Not inverted +#define GPT_CTL_TBPWML 0x00004000 +#define GPT_CTL_TBPWML_BITN 14 +#define GPT_CTL_TBPWML_M 0x00004000 +#define GPT_CTL_TBPWML_S 14 +#define GPT_CTL_TBPWML_INVERTED 0x00004000 +#define GPT_CTL_TBPWML_NORMAL 0x00000000 + +// Field: [11:10] TBEVENT +// +// GPT Timer B Event Mode +// +// The values in this register are defined as follows: +// Value Description +// 0x0 Positive edge +// 0x1 Negative edge +// 0x2 Reserved +// 0x3 Both edges +// Note: If PWM output inversion is enabled, edge detection interrupt +// behavior is reversed. Thus, if a positive-edge interrupt trigger +// has been set and the PWM inversion generates a postive +// edge, no event-trigger interrupt asserts. Instead, the interrupt +// is generated on the negative edge of the PWM signal. +// ENUMs: +// BOTH Both edges +// NEG Negative edge +// POS Positive edge +#define GPT_CTL_TBEVENT_W 2 +#define GPT_CTL_TBEVENT_M 0x00000C00 +#define GPT_CTL_TBEVENT_S 10 +#define GPT_CTL_TBEVENT_BOTH 0x00000C00 +#define GPT_CTL_TBEVENT_NEG 0x00000400 +#define GPT_CTL_TBEVENT_POS 0x00000000 + +// Field: [9] TBSTALL +// +// GPT Timer B Stall Enable +// ENUMs: +// EN Timer B freezes counting while the processor is +// halted by the debugger. +// DIS Timer B continues counting while the processor is +// halted by the debugger. +#define GPT_CTL_TBSTALL 0x00000200 +#define GPT_CTL_TBSTALL_BITN 9 +#define GPT_CTL_TBSTALL_M 0x00000200 +#define GPT_CTL_TBSTALL_S 9 +#define GPT_CTL_TBSTALL_EN 0x00000200 +#define GPT_CTL_TBSTALL_DIS 0x00000000 + +// Field: [8] TBEN +// +// GPT Timer B Enable +// ENUMs: +// EN Timer B is enabled and begins counting or the +// capture logic is enabled based on CFG register. +// DIS Timer B is disabled. +#define GPT_CTL_TBEN 0x00000100 +#define GPT_CTL_TBEN_BITN 8 +#define GPT_CTL_TBEN_M 0x00000100 +#define GPT_CTL_TBEN_S 8 +#define GPT_CTL_TBEN_EN 0x00000100 +#define GPT_CTL_TBEN_DIS 0x00000000 + +// Field: [6] TAPWML +// +// GPT Timer A PWM Output Level +// ENUMs: +// INVERTED Inverted +// NORMAL Not inverted +#define GPT_CTL_TAPWML 0x00000040 +#define GPT_CTL_TAPWML_BITN 6 +#define GPT_CTL_TAPWML_M 0x00000040 +#define GPT_CTL_TAPWML_S 6 +#define GPT_CTL_TAPWML_INVERTED 0x00000040 +#define GPT_CTL_TAPWML_NORMAL 0x00000000 + +// Field: [3:2] TAEVENT +// +// GPT Timer A Event Mode +// +// The values in this register are defined as follows: +// Value Description +// 0x0 Positive edge +// 0x1 Negative edge +// 0x2 Reserved +// 0x3 Both edges +// Note: If PWM output inversion is enabled, edge detection interrupt +// behavior is reversed. Thus, if a positive-edge interrupt trigger +// has been set and the PWM inversion generates a postive +// edge, no event-trigger interrupt asserts. Instead, the interrupt +// is generated on the negative edge of the PWM signal. +// ENUMs: +// BOTH Both edges +// NEG Negative edge +// POS Positive edge +#define GPT_CTL_TAEVENT_W 2 +#define GPT_CTL_TAEVENT_M 0x0000000C +#define GPT_CTL_TAEVENT_S 2 +#define GPT_CTL_TAEVENT_BOTH 0x0000000C +#define GPT_CTL_TAEVENT_NEG 0x00000004 +#define GPT_CTL_TAEVENT_POS 0x00000000 + +// Field: [1] TASTALL +// +// GPT Timer A Stall Enable +// ENUMs: +// EN Timer A freezes counting while the processor is +// halted by the debugger. +// DIS Timer A continues counting while the processor is +// halted by the debugger. +#define GPT_CTL_TASTALL 0x00000002 +#define GPT_CTL_TASTALL_BITN 1 +#define GPT_CTL_TASTALL_M 0x00000002 +#define GPT_CTL_TASTALL_S 1 +#define GPT_CTL_TASTALL_EN 0x00000002 +#define GPT_CTL_TASTALL_DIS 0x00000000 + +// Field: [0] TAEN +// +// GPT Timer A Enable +// ENUMs: +// EN Timer A is enabled and begins counting or the +// capture logic is enabled based on the CFG +// register. +// DIS Timer A is disabled. +#define GPT_CTL_TAEN 0x00000001 +#define GPT_CTL_TAEN_BITN 0 +#define GPT_CTL_TAEN_M 0x00000001 +#define GPT_CTL_TAEN_S 0 +#define GPT_CTL_TAEN_EN 0x00000001 +#define GPT_CTL_TAEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_SYNC +// +//***************************************************************************** +// Field: [7:6] SYNC3 +// +// Synchronize GPT Timer 3. +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT3 is triggered +// TIMERB A timeout event for Timer B of GPT3 is triggered +// TIMERA A timeout event for Timer A of GPT3 is triggered +// NOSYNC No Sync. GPT3 is not affected. +#define GPT_SYNC_SYNC3_W 2 +#define GPT_SYNC_SYNC3_M 0x000000C0 +#define GPT_SYNC_SYNC3_S 6 +#define GPT_SYNC_SYNC3_BOTH 0x000000C0 +#define GPT_SYNC_SYNC3_TIMERB 0x00000080 +#define GPT_SYNC_SYNC3_TIMERA 0x00000040 +#define GPT_SYNC_SYNC3_NOSYNC 0x00000000 + +// Field: [5:4] SYNC2 +// +// Synchronize GPT Timer 2. +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT2 is triggered +// TIMERB A timeout event for Timer B of GPT2 is triggered +// TIMERA A timeout event for Timer A of GPT2 is triggered +// NOSYNC No Sync. GPT2 is not affected. +#define GPT_SYNC_SYNC2_W 2 +#define GPT_SYNC_SYNC2_M 0x00000030 +#define GPT_SYNC_SYNC2_S 4 +#define GPT_SYNC_SYNC2_BOTH 0x00000030 +#define GPT_SYNC_SYNC2_TIMERB 0x00000020 +#define GPT_SYNC_SYNC2_TIMERA 0x00000010 +#define GPT_SYNC_SYNC2_NOSYNC 0x00000000 + +// Field: [3:2] SYNC1 +// +// Synchronize GPT Timer 1 +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT1 is triggered +// TIMERB A timeout event for Timer B of GPT1 is triggered +// TIMERA A timeout event for Timer A of GPT1 is triggered +// NOSYNC No Sync. GPT1 is not affected. +#define GPT_SYNC_SYNC1_W 2 +#define GPT_SYNC_SYNC1_M 0x0000000C +#define GPT_SYNC_SYNC1_S 2 +#define GPT_SYNC_SYNC1_BOTH 0x0000000C +#define GPT_SYNC_SYNC1_TIMERB 0x00000008 +#define GPT_SYNC_SYNC1_TIMERA 0x00000004 +#define GPT_SYNC_SYNC1_NOSYNC 0x00000000 + +// Field: [1:0] SYNC0 +// +// Synchronize GPT Timer 0 +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT0 is triggered +// TIMERB A timeout event for Timer B of GPT0 is triggered +// TIMERA A timeout event for Timer A of GPT0 is triggered +// NOSYNC No Sync. GPT0 is not affected. +#define GPT_SYNC_SYNC0_W 2 +#define GPT_SYNC_SYNC0_M 0x00000003 +#define GPT_SYNC_SYNC0_S 0 +#define GPT_SYNC_SYNC0_BOTH 0x00000003 +#define GPT_SYNC_SYNC0_TIMERB 0x00000002 +#define GPT_SYNC_SYNC0_TIMERA 0x00000001 +#define GPT_SYNC_SYNC0_NOSYNC 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_IMR +// +//***************************************************************************** +// Field: [13] DMABIM +// +// Enabling this bit will make the RIS.DMABRIS interrupt propagate to +// MIS.DMABMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_DMABIM 0x00002000 +#define GPT_IMR_DMABIM_BITN 13 +#define GPT_IMR_DMABIM_M 0x00002000 +#define GPT_IMR_DMABIM_S 13 +#define GPT_IMR_DMABIM_EN 0x00002000 +#define GPT_IMR_DMABIM_DIS 0x00000000 + +// Field: [11] TBMIM +// +// Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TBMIM 0x00000800 +#define GPT_IMR_TBMIM_BITN 11 +#define GPT_IMR_TBMIM_M 0x00000800 +#define GPT_IMR_TBMIM_S 11 +#define GPT_IMR_TBMIM_EN 0x00000800 +#define GPT_IMR_TBMIM_DIS 0x00000000 + +// Field: [10] CBEIM +// +// Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CBEIM 0x00000400 +#define GPT_IMR_CBEIM_BITN 10 +#define GPT_IMR_CBEIM_M 0x00000400 +#define GPT_IMR_CBEIM_S 10 +#define GPT_IMR_CBEIM_EN 0x00000400 +#define GPT_IMR_CBEIM_DIS 0x00000000 + +// Field: [9] CBMIM +// +// Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CBMIM 0x00000200 +#define GPT_IMR_CBMIM_BITN 9 +#define GPT_IMR_CBMIM_M 0x00000200 +#define GPT_IMR_CBMIM_S 9 +#define GPT_IMR_CBMIM_EN 0x00000200 +#define GPT_IMR_CBMIM_DIS 0x00000000 + +// Field: [8] TBTOIM +// +// Enabling this bit will make the RIS.TBTORIS interrupt propagate to +// MIS.TBTOMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TBTOIM 0x00000100 +#define GPT_IMR_TBTOIM_BITN 8 +#define GPT_IMR_TBTOIM_M 0x00000100 +#define GPT_IMR_TBTOIM_S 8 +#define GPT_IMR_TBTOIM_EN 0x00000100 +#define GPT_IMR_TBTOIM_DIS 0x00000000 + +// Field: [5] DMAAIM +// +// Enabling this bit will make the RIS.DMAARIS interrupt propagate to +// MIS.DMAAMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_DMAAIM 0x00000020 +#define GPT_IMR_DMAAIM_BITN 5 +#define GPT_IMR_DMAAIM_M 0x00000020 +#define GPT_IMR_DMAAIM_S 5 +#define GPT_IMR_DMAAIM_EN 0x00000020 +#define GPT_IMR_DMAAIM_DIS 0x00000000 + +// Field: [4] TAMIM +// +// Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TAMIM 0x00000010 +#define GPT_IMR_TAMIM_BITN 4 +#define GPT_IMR_TAMIM_M 0x00000010 +#define GPT_IMR_TAMIM_S 4 +#define GPT_IMR_TAMIM_EN 0x00000010 +#define GPT_IMR_TAMIM_DIS 0x00000000 + +// Field: [2] CAEIM +// +// Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CAEIM 0x00000004 +#define GPT_IMR_CAEIM_BITN 2 +#define GPT_IMR_CAEIM_M 0x00000004 +#define GPT_IMR_CAEIM_S 2 +#define GPT_IMR_CAEIM_EN 0x00000004 +#define GPT_IMR_CAEIM_DIS 0x00000000 + +// Field: [1] CAMIM +// +// Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CAMIM 0x00000002 +#define GPT_IMR_CAMIM_BITN 1 +#define GPT_IMR_CAMIM_M 0x00000002 +#define GPT_IMR_CAMIM_S 1 +#define GPT_IMR_CAMIM_EN 0x00000002 +#define GPT_IMR_CAMIM_DIS 0x00000000 + +// Field: [0] TATOIM +// +// Enabling this bit will make the RIS.TATORIS interrupt propagate to +// MIS.TATOMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TATOIM 0x00000001 +#define GPT_IMR_TATOIM_BITN 0 +#define GPT_IMR_TATOIM_M 0x00000001 +#define GPT_IMR_TATOIM_S 0 +#define GPT_IMR_TATOIM_EN 0x00000001 +#define GPT_IMR_TATOIM_DIS 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_RIS +// +//***************************************************************************** +// Field: [13] DMABRIS +// +// GPT Timer B DMA Done Raw Interrupt Status +// +// 0: Transfer has not completed +// 1: Transfer has completed +#define GPT_RIS_DMABRIS 0x00002000 +#define GPT_RIS_DMABRIS_BITN 13 +#define GPT_RIS_DMABRIS_M 0x00002000 +#define GPT_RIS_DMABRIS_S 13 + +// Field: [11] TBMRIS +// +// GPT Timer B Match Raw Interrupt +// +// 0: The match value has not been reached +// 1: The match value is reached. +// +// TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR +// have been reached when configured in one-shot or periodic mode. +#define GPT_RIS_TBMRIS 0x00000800 +#define GPT_RIS_TBMRIS_BITN 11 +#define GPT_RIS_TBMRIS_M 0x00000800 +#define GPT_RIS_TBMRIS_S 11 + +// Field: [10] CBERIS +// +// GPT Timer B Capture Mode Event Raw Interrupt +// +// 0: The event has not occured. +// 1: The event has occured. +// +// This interrupt asserts when the subtimer is configured in Input Edge-Time +// mode +#define GPT_RIS_CBERIS 0x00000400 +#define GPT_RIS_CBERIS_BITN 10 +#define GPT_RIS_CBERIS_M 0x00000400 +#define GPT_RIS_CBERIS_S 10 + +// Field: [9] CBMRIS +// +// GPT Timer B Capture Mode Match Raw Interrupt +// +// 0: The capture mode match for Timer B has not occurred. +// 1: A capture mode match has occurred for Timer B. This interrupt +// asserts when the values in the TBR and TBPR +// match the values in the TBMATCHR and TBPMR +// when configured in Input Edge-Time mode. +// +// This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. +#define GPT_RIS_CBMRIS 0x00000200 +#define GPT_RIS_CBMRIS_BITN 9 +#define GPT_RIS_CBMRIS_M 0x00000200 +#define GPT_RIS_CBMRIS_S 9 + +// Field: [8] TBTORIS +// +// GPT Timer B Time-out Raw Interrupt +// +// 0: Timer B has not timed out +// 1: Timer B has timed out. +// +// This interrupt is asserted when a one-shot or periodic mode timer reaches +// its count limit. The count limit is 0 or the value loaded into TBILR, +// depending on the count direction. +#define GPT_RIS_TBTORIS 0x00000100 +#define GPT_RIS_TBTORIS_BITN 8 +#define GPT_RIS_TBTORIS_M 0x00000100 +#define GPT_RIS_TBTORIS_S 8 + +// Field: [5] DMAARIS +// +// GPT Timer A DMA Done Raw Interrupt Status +// +// 0: Transfer has not completed +// 1: Transfer has completed +#define GPT_RIS_DMAARIS 0x00000020 +#define GPT_RIS_DMAARIS_BITN 5 +#define GPT_RIS_DMAARIS_M 0x00000020 +#define GPT_RIS_DMAARIS_S 5 + +// Field: [4] TAMRIS +// +// GPT Timer A Match Raw Interrupt +// +// 0: The match value has not been reached +// 1: The match value is reached. +// +// TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR +// have been reached when configured in one-shot or periodic mode. +#define GPT_RIS_TAMRIS 0x00000010 +#define GPT_RIS_TAMRIS_BITN 4 +#define GPT_RIS_TAMRIS_M 0x00000010 +#define GPT_RIS_TAMRIS_S 4 + +// Field: [2] CAERIS +// +// GPT Timer A Capture Mode Event Raw Interrupt +// +// 0: The event has not occured. +// 1: The event has occured. +// +// This interrupt asserts when the subtimer is configured in Input Edge-Time +// mode +#define GPT_RIS_CAERIS 0x00000004 +#define GPT_RIS_CAERIS_BITN 2 +#define GPT_RIS_CAERIS_M 0x00000004 +#define GPT_RIS_CAERIS_S 2 + +// Field: [1] CAMRIS +// +// GPT Timer A Capture Mode Match Raw Interrupt +// +// 0: The capture mode match for Timer A has not occurred. +// 1: A capture mode match has occurred for Timer A. This interrupt +// asserts when the values in the TAR and TAPR +// match the values in the TAMATCHR and TAPMR +// when configured in Input Edge-Time mode. +// +// This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. +#define GPT_RIS_CAMRIS 0x00000002 +#define GPT_RIS_CAMRIS_BITN 1 +#define GPT_RIS_CAMRIS_M 0x00000002 +#define GPT_RIS_CAMRIS_S 1 + +// Field: [0] TATORIS +// +// GPT Timer A Time-out Raw Interrupt +// +// 0: Timer A has not timed out +// 1: Timer A has timed out. +// +// This interrupt is asserted when a one-shot or periodic mode timer reaches +// its count limit. The count limit is 0 or the value loaded into TAILR, +// depending on the count direction. +#define GPT_RIS_TATORIS 0x00000001 +#define GPT_RIS_TATORIS_BITN 0 +#define GPT_RIS_TATORIS_M 0x00000001 +#define GPT_RIS_TATORIS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_MIS +// +//***************************************************************************** +// Field: [13] DMABMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 +#define GPT_MIS_DMABMIS 0x00002000 +#define GPT_MIS_DMABMIS_BITN 13 +#define GPT_MIS_DMABMIS_M 0x00002000 +#define GPT_MIS_DMABMIS_S 13 + +// Field: [11] TBMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 +#define GPT_MIS_TBMMIS 0x00000800 +#define GPT_MIS_TBMMIS_BITN 11 +#define GPT_MIS_TBMMIS_M 0x00000800 +#define GPT_MIS_TBMMIS_S 11 + +// Field: [10] CBEMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 +#define GPT_MIS_CBEMIS 0x00000400 +#define GPT_MIS_CBEMIS_BITN 10 +#define GPT_MIS_CBEMIS_M 0x00000400 +#define GPT_MIS_CBEMIS_S 10 + +// Field: [9] CBMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 +#define GPT_MIS_CBMMIS 0x00000200 +#define GPT_MIS_CBMMIS_BITN 9 +#define GPT_MIS_CBMMIS_M 0x00000200 +#define GPT_MIS_CBMMIS_S 9 + +// Field: [8] TBTOMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 +#define GPT_MIS_TBTOMIS 0x00000100 +#define GPT_MIS_TBTOMIS_BITN 8 +#define GPT_MIS_TBTOMIS_M 0x00000100 +#define GPT_MIS_TBTOMIS_S 8 + +// Field: [5] DMAAMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 +#define GPT_MIS_DMAAMIS 0x00000020 +#define GPT_MIS_DMAAMIS_BITN 5 +#define GPT_MIS_DMAAMIS_M 0x00000020 +#define GPT_MIS_DMAAMIS_S 5 + +// Field: [4] TAMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 +#define GPT_MIS_TAMMIS 0x00000010 +#define GPT_MIS_TAMMIS_BITN 4 +#define GPT_MIS_TAMMIS_M 0x00000010 +#define GPT_MIS_TAMMIS_S 4 + +// Field: [2] CAEMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 +#define GPT_MIS_CAEMIS 0x00000004 +#define GPT_MIS_CAEMIS_BITN 2 +#define GPT_MIS_CAEMIS_M 0x00000004 +#define GPT_MIS_CAEMIS_S 2 + +// Field: [1] CAMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 +#define GPT_MIS_CAMMIS 0x00000002 +#define GPT_MIS_CAMMIS_BITN 1 +#define GPT_MIS_CAMMIS_M 0x00000002 +#define GPT_MIS_CAMMIS_S 1 + +// Field: [0] TATOMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 +#define GPT_MIS_TATOMIS 0x00000001 +#define GPT_MIS_TATOMIS_BITN 0 +#define GPT_MIS_TATOMIS_M 0x00000001 +#define GPT_MIS_TATOMIS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_ICLR +// +//***************************************************************************** +// Field: [13] DMABINT +// +// 0: Do nothing. +// 1: Clear RIS.DMABRIS and MIS.DMABMIS +#define GPT_ICLR_DMABINT 0x00002000 +#define GPT_ICLR_DMABINT_BITN 13 +#define GPT_ICLR_DMABINT_M 0x00002000 +#define GPT_ICLR_DMABINT_S 13 + +// Field: [11] TBMCINT +// +// 0: Do nothing. +// 1: Clear RIS.TBMRIS and MIS.TBMMIS +#define GPT_ICLR_TBMCINT 0x00000800 +#define GPT_ICLR_TBMCINT_BITN 11 +#define GPT_ICLR_TBMCINT_M 0x00000800 +#define GPT_ICLR_TBMCINT_S 11 + +// Field: [10] CBECINT +// +// 0: Do nothing. +// 1: Clear RIS.CBERIS and MIS.CBEMIS +#define GPT_ICLR_CBECINT 0x00000400 +#define GPT_ICLR_CBECINT_BITN 10 +#define GPT_ICLR_CBECINT_M 0x00000400 +#define GPT_ICLR_CBECINT_S 10 + +// Field: [9] CBMCINT +// +// 0: Do nothing. +// 1: Clear RIS.CBMRIS and MIS.CBMMIS +#define GPT_ICLR_CBMCINT 0x00000200 +#define GPT_ICLR_CBMCINT_BITN 9 +#define GPT_ICLR_CBMCINT_M 0x00000200 +#define GPT_ICLR_CBMCINT_S 9 + +// Field: [8] TBTOCINT +// +// 0: Do nothing. +// 1: Clear RIS.TBTORIS and MIS.TBTOMIS +#define GPT_ICLR_TBTOCINT 0x00000100 +#define GPT_ICLR_TBTOCINT_BITN 8 +#define GPT_ICLR_TBTOCINT_M 0x00000100 +#define GPT_ICLR_TBTOCINT_S 8 + +// Field: [5] DMAAINT +// +// 0: Do nothing. +// 1: Clear RIS.DMAARIS and MIS.DMAAMIS +#define GPT_ICLR_DMAAINT 0x00000020 +#define GPT_ICLR_DMAAINT_BITN 5 +#define GPT_ICLR_DMAAINT_M 0x00000020 +#define GPT_ICLR_DMAAINT_S 5 + +// Field: [4] TAMCINT +// +// 0: Do nothing. +// 1: Clear RIS.TAMRIS and MIS.TAMMIS +#define GPT_ICLR_TAMCINT 0x00000010 +#define GPT_ICLR_TAMCINT_BITN 4 +#define GPT_ICLR_TAMCINT_M 0x00000010 +#define GPT_ICLR_TAMCINT_S 4 + +// Field: [2] CAECINT +// +// 0: Do nothing. +// 1: Clear RIS.CAERIS and MIS.CAEMIS +#define GPT_ICLR_CAECINT 0x00000004 +#define GPT_ICLR_CAECINT_BITN 2 +#define GPT_ICLR_CAECINT_M 0x00000004 +#define GPT_ICLR_CAECINT_S 2 + +// Field: [1] CAMCINT +// +// 0: Do nothing. +// 1: Clear RIS.CAMRIS and MIS.CAMMIS +#define GPT_ICLR_CAMCINT 0x00000002 +#define GPT_ICLR_CAMCINT_BITN 1 +#define GPT_ICLR_CAMCINT_M 0x00000002 +#define GPT_ICLR_CAMCINT_S 1 + +// Field: [0] TATOCINT +// +// 0: Do nothing. +// 1: Clear RIS.TATORIS and MIS.TATOMIS +#define GPT_ICLR_TATOCINT 0x00000001 +#define GPT_ICLR_TATOCINT_BITN 0 +#define GPT_ICLR_TATOCINT_M 0x00000001 +#define GPT_ICLR_TATOCINT_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAILR +// +//***************************************************************************** +// Field: [31:0] TAILR +// +// GPT Timer A Interval Load Register +// +// Writing this field loads the counter for Timer A. A read returns the current +// value of TAILR. +#define GPT_TAILR_TAILR_W 32 +#define GPT_TAILR_TAILR_M 0xFFFFFFFF +#define GPT_TAILR_TAILR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBILR +// +//***************************************************************************** +// Field: [31:0] TBILR +// +// GPT Timer B Interval Load Register +// +// Writing this field loads the counter for Timer B. A read returns the current +// value of TBILR. +#define GPT_TBILR_TBILR_W 32 +#define GPT_TBILR_TBILR_M 0xFFFFFFFF +#define GPT_TBILR_TBILR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAMATCHR +// +//***************************************************************************** +// Field: [31:0] TAMATCHR +// +// GPT Timer A Match Register +#define GPT_TAMATCHR_TAMATCHR_W 32 +#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF +#define GPT_TAMATCHR_TAMATCHR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBMATCHR +// +//***************************************************************************** +// Field: [15:0] TBMATCHR +// +// GPT Timer B Match Register +#define GPT_TBMATCHR_TBMATCHR_W 16 +#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF +#define GPT_TBMATCHR_TBMATCHR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPR +// +//***************************************************************************** +// Field: [7:0] TAPSR +// +// Timer A Pre-scale. +// +// Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: +// +// 0: Prescaler ratio = 1 +// 1: Prescaler ratio = 2 +// 2: Prescaler ratio = 3 +// ... +// 255: Prescaler ratio = 256 +#define GPT_TAPR_TAPSR_W 8 +#define GPT_TAPR_TAPSR_M 0x000000FF +#define GPT_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPR +// +//***************************************************************************** +// Field: [7:0] TBPSR +// +// Timer B Pre-scale. +// +// Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: +// +// 0: Prescaler ratio = 1 +// 1: Prescaler ratio = 2 +// 2: Prescaler ratio = 3 +// ... +// 255: Prescaler ratio = 256 +#define GPT_TBPR_TBPSR_W 8 +#define GPT_TBPR_TBPSR_M 0x000000FF +#define GPT_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPMR +// +//***************************************************************************** +// Field: [7:0] TAPSMR +// +// GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. +#define GPT_TAPMR_TAPSMR_W 8 +#define GPT_TAPMR_TAPSMR_M 0x000000FF +#define GPT_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPMR +// +//***************************************************************************** +// Field: [7:0] TBPSMR +// +// GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits +// 23 to 16. +#define GPT_TBPMR_TBPSMR_W 8 +#define GPT_TBPMR_TBPSMR_M 0x000000FF +#define GPT_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAR +// +//***************************************************************************** +// Field: [31:0] TAR +// +// GPT Timer A Register +// +// Based on the value in the register field TAMR.TAILD, this register is +// updated with the value from TAILR register either on the next cycle or on +// the next timeout. +// +// A read returns the current value of the Timer A Count Register, in all cases +// except for Input Edge count and Timer modes. +// In the Input Edge Count Mode, this register contains the number of edges +// that have occurred. In the Input Edge Time mode, this register contains the +// time at which the last edge event took place. +#define GPT_TAR_TAR_W 32 +#define GPT_TAR_TAR_M 0xFFFFFFFF +#define GPT_TAR_TAR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBR +// +//***************************************************************************** +// Field: [31:0] TBR +// +// GPT Timer B Register +// +// Based on the value in the register field TBMR.TBILD, this register is +// updated with the value from TBILR register either on the next cycle or on +// the next timeout. +// +// A read returns the current value of the Timer B Count Register, in all cases +// except for Input Edge count and Timer modes. +// In the Input Edge Count Mode, this register contains the number of edges +// that have occurred. In the Input Edge Time mode, this register contains the +// time at which the last edge event took place. +#define GPT_TBR_TBR_W 32 +#define GPT_TBR_TBR_M 0xFFFFFFFF +#define GPT_TBR_TBR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAV +// +//***************************************************************************** +// Field: [31:0] TAV +// +// GPT Timer A Register +// A read returns the current, free-running value of Timer A in all modes. +// When written, the value written into this register is loaded into the +// TAR register on the next clock cycle. +// Note: In 16-bit mode, only the lower 16-bits of this +// register can be written with a new value. Writes to the prescaler bits have +// no effect +#define GPT_TAV_TAV_W 32 +#define GPT_TAV_TAV_M 0xFFFFFFFF +#define GPT_TAV_TAV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBV +// +//***************************************************************************** +// Field: [31:0] TBV +// +// GPT Timer B Register +// A read returns the current, free-running value of Timer B in all modes. +// When written, the value written into this register is loaded into the +// TBR register on the next clock cycle. +// Note: In 16-bit mode, only the lower 16-bits of this +// register can be written with a new value. Writes to the prescaler bits have +// no effect +#define GPT_TBV_TBV_W 32 +#define GPT_TBV_TBV_M 0xFFFFFFFF +#define GPT_TBV_TBV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPS +// +//***************************************************************************** +// Field: [7:0] PSS +// +// GPT Timer A Pre-scaler +#define GPT_TAPS_PSS_W 8 +#define GPT_TAPS_PSS_M 0x000000FF +#define GPT_TAPS_PSS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPS +// +//***************************************************************************** +// Field: [7:0] PSS +// +// GPT Timer B Pre-scaler +#define GPT_TBPS_PSS_W 8 +#define GPT_TBPS_PSS_M 0x000000FF +#define GPT_TBPS_PSS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPV +// +//***************************************************************************** +// Field: [7:0] PSV +// +// GPT Timer A Pre-scaler Value +#define GPT_TAPV_PSV_W 8 +#define GPT_TAPV_PSV_M 0x000000FF +#define GPT_TAPV_PSV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPV +// +//***************************************************************************** +// Field: [7:0] PSV +// +// GPT Timer B Pre-scaler Value +#define GPT_TBPV_PSV_W 8 +#define GPT_TBPV_PSV_M 0x000000FF +#define GPT_TBPV_PSV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_DMAEV +// +//***************************************************************************** +// Field: [11] TBMDMAEN +// +// GPT Timer B Match DMA Trigger Enable +#define GPT_DMAEV_TBMDMAEN 0x00000800 +#define GPT_DMAEV_TBMDMAEN_BITN 11 +#define GPT_DMAEV_TBMDMAEN_M 0x00000800 +#define GPT_DMAEV_TBMDMAEN_S 11 + +// Field: [10] CBEDMAEN +// +// GPT Timer B Capture Event DMA Trigger Enable +#define GPT_DMAEV_CBEDMAEN 0x00000400 +#define GPT_DMAEV_CBEDMAEN_BITN 10 +#define GPT_DMAEV_CBEDMAEN_M 0x00000400 +#define GPT_DMAEV_CBEDMAEN_S 10 + +// Field: [9] CBMDMAEN +// +// GPT Timer B Capture Match DMA Trigger Enable +#define GPT_DMAEV_CBMDMAEN 0x00000200 +#define GPT_DMAEV_CBMDMAEN_BITN 9 +#define GPT_DMAEV_CBMDMAEN_M 0x00000200 +#define GPT_DMAEV_CBMDMAEN_S 9 + +// Field: [8] TBTODMAEN +// +// GPT Timer B Time-Out DMA Trigger Enable +#define GPT_DMAEV_TBTODMAEN 0x00000100 +#define GPT_DMAEV_TBTODMAEN_BITN 8 +#define GPT_DMAEV_TBTODMAEN_M 0x00000100 +#define GPT_DMAEV_TBTODMAEN_S 8 + +// Field: [4] TAMDMAEN +// +// GPT Timer A Match DMA Trigger Enable +#define GPT_DMAEV_TAMDMAEN 0x00000010 +#define GPT_DMAEV_TAMDMAEN_BITN 4 +#define GPT_DMAEV_TAMDMAEN_M 0x00000010 +#define GPT_DMAEV_TAMDMAEN_S 4 + +// Field: [2] CAEDMAEN +// +// GPT Timer A Capture Event DMA Trigger Enable +#define GPT_DMAEV_CAEDMAEN 0x00000004 +#define GPT_DMAEV_CAEDMAEN_BITN 2 +#define GPT_DMAEV_CAEDMAEN_M 0x00000004 +#define GPT_DMAEV_CAEDMAEN_S 2 + +// Field: [1] CAMDMAEN +// +// GPT Timer A Capture Match DMA Trigger Enable +#define GPT_DMAEV_CAMDMAEN 0x00000002 +#define GPT_DMAEV_CAMDMAEN_BITN 1 +#define GPT_DMAEV_CAMDMAEN_M 0x00000002 +#define GPT_DMAEV_CAMDMAEN_S 1 + +// Field: [0] TATODMAEN +// +// GPT Timer A Time-Out DMA Trigger Enable +#define GPT_DMAEV_TATODMAEN 0x00000001 +#define GPT_DMAEV_TATODMAEN_BITN 0 +#define GPT_DMAEV_TATODMAEN_M 0x00000001 +#define GPT_DMAEV_TATODMAEN_S 0 + +//***************************************************************************** +// +// Register: GPT_O_VERSION +// +//***************************************************************************** +// Field: [31:0] VERSION +// +// Timer Revision. +#define GPT_VERSION_VERSION_W 32 +#define GPT_VERSION_VERSION_M 0xFFFFFFFF +#define GPT_VERSION_VERSION_S 0 + +//***************************************************************************** +// +// Register: GPT_O_ANDCCP +// +//***************************************************************************** +// Field: [1] LD_TO_EN +// +// PWM assertion would happen at timeout +// +// 0: PWM assertion happens when counter matches load value +// 1: PWM assertion happens at timeout of the counter +#define GPT_ANDCCP_LD_TO_EN 0x00000002 +#define GPT_ANDCCP_LD_TO_EN_BITN 1 +#define GPT_ANDCCP_LD_TO_EN_M 0x00000002 +#define GPT_ANDCCP_LD_TO_EN_S 1 + +// Field: [0] CCP_AND_EN +// +// Enables AND operation of the CCP outputs for timers A and B. +// +// 0 : PWM outputs of Timer A and Timer B are the internal generated PWM +// signals of the respective timers. +// 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM +// signals and Timer B PWM ouput is Timer B PWM signal only. +#define GPT_ANDCCP_CCP_AND_EN 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_BITN 0 +#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_S 0 + + +#endif // __GPT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h new file mode 100644 index 0000000..3c23b78 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h @@ -0,0 +1,728 @@ +/****************************************************************************** +* Filename: hw_i2c_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// I2C component +// +//***************************************************************************** +// Slave Own Address +#define I2C_O_SOAR 0x00000000 + +// Slave Status +#define I2C_O_SSTAT 0x00000004 + +// Slave Control +#define I2C_O_SCTL 0x00000004 + +// Slave Data +#define I2C_O_SDR 0x00000008 + +// Slave Interrupt Mask +#define I2C_O_SIMR 0x0000000C + +// Slave Raw Interrupt Status +#define I2C_O_SRIS 0x00000010 + +// Slave Masked Interrupt Status +#define I2C_O_SMIS 0x00000014 + +// Slave Interrupt Clear +#define I2C_O_SICR 0x00000018 + +// Master Salve Address +#define I2C_O_MSA 0x00000800 + +// Master Status +#define I2C_O_MSTAT 0x00000804 + +// Master Control +#define I2C_O_MCTRL 0x00000804 + +// Master Data +#define I2C_O_MDR 0x00000808 + +// I2C Master Timer Period +#define I2C_O_MTPR 0x0000080C + +// Master Interrupt Mask +#define I2C_O_MIMR 0x00000810 + +// Master Raw Interrupt Status +#define I2C_O_MRIS 0x00000814 + +// Master Masked Interrupt Status +#define I2C_O_MMIS 0x00000818 + +// Master Interrupt Clear +#define I2C_O_MICR 0x0000081C + +// Master Configuration +#define I2C_O_MCR 0x00000820 + +//***************************************************************************** +// +// Register: I2C_O_SOAR +// +//***************************************************************************** +// Field: [6:0] OAR +// +// I2C slave own address +// This field specifies bits a6 through a0 of the slave address. +#define I2C_SOAR_OAR_W 7 +#define I2C_SOAR_OAR_M 0x0000007F +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SSTAT +// +//***************************************************************************** +// Field: [2] FBR +// +// First byte received +// +// 0: The first byte has not been received. +// 1: The first byte following the slave's own address has been received. +// +// This bit is only valid when the RREQ bit is set and is automatically cleared +// when data has been read from the SDR register. +// Note: This bit is not used for slave transmit operations. +#define I2C_SSTAT_FBR 0x00000004 +#define I2C_SSTAT_FBR_BITN 2 +#define I2C_SSTAT_FBR_M 0x00000004 +#define I2C_SSTAT_FBR_S 2 + +// Field: [1] TREQ +// +// Transmit request +// +// 0: No outstanding transmit request. +// 1: The I2C controller has been addressed as a slave transmitter and is using +// clock stretching to delay the master until data has been written to the SDR +// register. +#define I2C_SSTAT_TREQ 0x00000002 +#define I2C_SSTAT_TREQ_BITN 1 +#define I2C_SSTAT_TREQ_M 0x00000002 +#define I2C_SSTAT_TREQ_S 1 + +// Field: [0] RREQ +// +// Receive request +// +// 0: No outstanding receive data +// 1: The I2C controller has outstanding receive data from the I2C master and +// is using clock stretching to delay the master until data has been read from +// the SDR register. +#define I2C_SSTAT_RREQ 0x00000001 +#define I2C_SSTAT_RREQ_BITN 0 +#define I2C_SSTAT_RREQ_M 0x00000001 +#define I2C_SSTAT_RREQ_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SCTL +// +//***************************************************************************** +// Field: [0] DA +// +// Device active +// +// 0: Disables the I2C slave operation +// 1: Enables the I2C slave operation +#define I2C_SCTL_DA 0x00000001 +#define I2C_SCTL_DA_BITN 0 +#define I2C_SCTL_DA_M 0x00000001 +#define I2C_SCTL_DA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SDR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// Data for transfer +// This field contains the data for transfer during a slave receive or transmit +// operation. When written the register data is used as transmit data. When +// read, this register returns the last data received. +// Data is stored until next update, either by a system write for transmit or +// by an external master for receive. +#define I2C_SDR_DATA_W 8 +#define I2C_SDR_DATA_M 0x000000FF +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SIMR +// +//***************************************************************************** +// Field: [2] STOPIM +// +// Stop condition interrupt mask +// +// 0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt +// controller. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_SIMR_STOPIM 0x00000004 +#define I2C_SIMR_STOPIM_BITN 2 +#define I2C_SIMR_STOPIM_M 0x00000004 +#define I2C_SIMR_STOPIM_S 2 +#define I2C_SIMR_STOPIM_EN 0x00000004 +#define I2C_SIMR_STOPIM_DIS 0x00000000 + +// Field: [1] STARTIM +// +// Start condition interrupt mask +// +// 0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt +// controller. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_SIMR_STARTIM 0x00000002 +#define I2C_SIMR_STARTIM_BITN 1 +#define I2C_SIMR_STARTIM_M 0x00000002 +#define I2C_SIMR_STARTIM_S 1 +#define I2C_SIMR_STARTIM_EN 0x00000002 +#define I2C_SIMR_STARTIM_DIS 0x00000000 + +// Field: [0] DATAIM +// +// Data interrupt mask +// +// 0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt +// controller. +#define I2C_SIMR_DATAIM 0x00000001 +#define I2C_SIMR_DATAIM_BITN 0 +#define I2C_SIMR_DATAIM_M 0x00000001 +#define I2C_SIMR_DATAIM_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SRIS +// +//***************************************************************************** +// Field: [2] STOPRIS +// +// Stop condition raw interrupt status +// +// 0: No interrupt +// 1: A Stop condition interrupt is pending. +// +// This bit is cleared by writing a 1 to SICR.STOPIC. +#define I2C_SRIS_STOPRIS 0x00000004 +#define I2C_SRIS_STOPRIS_BITN 2 +#define I2C_SRIS_STOPRIS_M 0x00000004 +#define I2C_SRIS_STOPRIS_S 2 + +// Field: [1] STARTRIS +// +// Start condition raw interrupt status +// +// 0: No interrupt +// 1: A Start condition interrupt is pending. +// +// This bit is cleared by writing a 1 to SICR.STARTIC. +#define I2C_SRIS_STARTRIS 0x00000002 +#define I2C_SRIS_STARTRIS_BITN 1 +#define I2C_SRIS_STARTRIS_M 0x00000002 +#define I2C_SRIS_STARTRIS_S 1 + +// Field: [0] DATARIS +// +// Data raw interrupt status +// +// 0: No interrupt +// 1: A data received or data requested interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.DATAIC. +#define I2C_SRIS_DATARIS 0x00000001 +#define I2C_SRIS_DATARIS_BITN 0 +#define I2C_SRIS_DATARIS_M 0x00000001 +#define I2C_SRIS_DATARIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SMIS +// +//***************************************************************************** +// Field: [2] STOPMIS +// +// Stop condition masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked Stop condition interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.STOPIC. +#define I2C_SMIS_STOPMIS 0x00000004 +#define I2C_SMIS_STOPMIS_BITN 2 +#define I2C_SMIS_STOPMIS_M 0x00000004 +#define I2C_SMIS_STOPMIS_S 2 + +// Field: [1] STARTMIS +// +// Start condition masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked Start condition interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.STARTIC. +#define I2C_SMIS_STARTMIS 0x00000002 +#define I2C_SMIS_STARTMIS_BITN 1 +#define I2C_SMIS_STARTMIS_M 0x00000002 +#define I2C_SMIS_STARTMIS_S 1 + +// Field: [0] DATAMIS +// +// Data masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked data received or data requested interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.DATAIC. +#define I2C_SMIS_DATAMIS 0x00000001 +#define I2C_SMIS_DATAMIS_BITN 0 +#define I2C_SMIS_DATAMIS_M 0x00000001 +#define I2C_SMIS_DATAMIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SICR +// +//***************************************************************************** +// Field: [2] STOPIC +// +// Stop condition interrupt clear +// +// Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. +#define I2C_SICR_STOPIC 0x00000004 +#define I2C_SICR_STOPIC_BITN 2 +#define I2C_SICR_STOPIC_M 0x00000004 +#define I2C_SICR_STOPIC_S 2 + +// Field: [1] STARTIC +// +// Start condition interrupt clear +// +// Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. +#define I2C_SICR_STARTIC 0x00000002 +#define I2C_SICR_STARTIC_BITN 1 +#define I2C_SICR_STARTIC_M 0x00000002 +#define I2C_SICR_STARTIC_S 1 + +// Field: [0] DATAIC +// +// Data interrupt clear +// +// Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. +#define I2C_SICR_DATAIC 0x00000001 +#define I2C_SICR_DATAIC_BITN 0 +#define I2C_SICR_DATAIC_M 0x00000001 +#define I2C_SICR_DATAIC_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MSA +// +//***************************************************************************** +// Field: [7:1] SA +// +// I2C master slave address +// Defines which slave is addressed for the transaction in master mode +#define I2C_MSA_SA_W 7 +#define I2C_MSA_SA_M 0x000000FE +#define I2C_MSA_SA_S 1 + +// Field: [0] RS +// +// Receive or Send +// This bit-field specifies if the next operation is a receive (high) or a +// transmit/send (low) from the addressed slave SA. +// ENUMs: +// RX Receive data from slave +// TX Transmit/send data to slave +#define I2C_MSA_RS 0x00000001 +#define I2C_MSA_RS_BITN 0 +#define I2C_MSA_RS_M 0x00000001 +#define I2C_MSA_RS_S 0 +#define I2C_MSA_RS_RX 0x00000001 +#define I2C_MSA_RS_TX 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MSTAT +// +//***************************************************************************** +// Field: [6] BUSBSY +// +// Bus busy +// +// 0: The I2C bus is idle. +// 1: The I2C bus is busy. +// +// The bit changes based on the MCTRL.START and MCTRL.STOP conditions. +#define I2C_MSTAT_BUSBSY 0x00000040 +#define I2C_MSTAT_BUSBSY_BITN 6 +#define I2C_MSTAT_BUSBSY_M 0x00000040 +#define I2C_MSTAT_BUSBSY_S 6 + +// Field: [5] IDLE +// +// I2C idle +// +// 0: The I2C controller is not idle. +// 1: The I2C controller is idle. +#define I2C_MSTAT_IDLE 0x00000020 +#define I2C_MSTAT_IDLE_BITN 5 +#define I2C_MSTAT_IDLE_M 0x00000020 +#define I2C_MSTAT_IDLE_S 5 + +// Field: [4] ARBLST +// +// Arbitration lost +// +// 0: The I2C controller won arbitration. +// 1: The I2C controller lost arbitration. +#define I2C_MSTAT_ARBLST 0x00000010 +#define I2C_MSTAT_ARBLST_BITN 4 +#define I2C_MSTAT_ARBLST_M 0x00000010 +#define I2C_MSTAT_ARBLST_S 4 + +// Field: [3] DATACK_N +// +// Data Was Not Acknowledge +// +// 0: The transmitted data was acknowledged. +// 1: The transmitted data was not acknowledged. +#define I2C_MSTAT_DATACK_N 0x00000008 +#define I2C_MSTAT_DATACK_N_BITN 3 +#define I2C_MSTAT_DATACK_N_M 0x00000008 +#define I2C_MSTAT_DATACK_N_S 3 + +// Field: [2] ADRACK_N +// +// Address Was Not Acknowledge +// +// 0: The transmitted address was acknowledged. +// 1: The transmitted address was not acknowledged. +#define I2C_MSTAT_ADRACK_N 0x00000004 +#define I2C_MSTAT_ADRACK_N_BITN 2 +#define I2C_MSTAT_ADRACK_N_M 0x00000004 +#define I2C_MSTAT_ADRACK_N_S 2 + +// Field: [1] ERR +// +// Error +// +// 0: No error was detected on the last operation. +// 1: An error occurred on the last operation. +#define I2C_MSTAT_ERR 0x00000002 +#define I2C_MSTAT_ERR_BITN 1 +#define I2C_MSTAT_ERR_M 0x00000002 +#define I2C_MSTAT_ERR_S 1 + +// Field: [0] BUSY +// +// I2C busy +// +// 0: The controller is idle. +// 1: The controller is busy. +// +// When this bit-field is set, the other status bits are not valid. +// +// Note: The I2C controller requires four SYSBUS clock cycles to assert the +// BUSY status after I2C master operation has been initiated through MCTRL +// register. +// Hence after programming MCTRL register, application is requested to wait for +// four SYSBUS clock cycles before issuing a controller status inquiry through +// MSTAT register. +// Any prior inquiry would result in wrong status being reported. +#define I2C_MSTAT_BUSY 0x00000001 +#define I2C_MSTAT_BUSY_BITN 0 +#define I2C_MSTAT_BUSY_M 0x00000001 +#define I2C_MSTAT_BUSY_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MCTRL +// +//***************************************************************************** +// Field: [3] ACK +// +// Data acknowledge enable +// +// 0: The received data byte is not acknowledged automatically by the master. +// 1: The received data byte is acknowledged automatically by the master. +// +// This bit-field must be cleared when the I2C bus controller requires no +// further data to be transmitted from the slave transmitter. +// ENUMs: +// EN Enable acknowledge +// DIS Disable acknowledge +#define I2C_MCTRL_ACK 0x00000008 +#define I2C_MCTRL_ACK_BITN 3 +#define I2C_MCTRL_ACK_M 0x00000008 +#define I2C_MCTRL_ACK_S 3 +#define I2C_MCTRL_ACK_EN 0x00000008 +#define I2C_MCTRL_ACK_DIS 0x00000000 + +// Field: [2] STOP +// +// This bit-field determines if the cycle stops at the end of the data cycle or +// continues on to a repeated START condition. +// +// 0: The controller does not generate the Stop condition. +// 1: The controller generates the Stop condition. +// ENUMs: +// EN Enable STOP +// DIS Disable STOP +#define I2C_MCTRL_STOP 0x00000004 +#define I2C_MCTRL_STOP_BITN 2 +#define I2C_MCTRL_STOP_M 0x00000004 +#define I2C_MCTRL_STOP_S 2 +#define I2C_MCTRL_STOP_EN 0x00000004 +#define I2C_MCTRL_STOP_DIS 0x00000000 + +// Field: [1] START +// +// This bit-field generates the Start or Repeated Start condition. +// +// 0: The controller does not generate the Start condition. +// 1: The controller generates the Start condition. +// ENUMs: +// EN Enable START +// DIS Disable START +#define I2C_MCTRL_START 0x00000002 +#define I2C_MCTRL_START_BITN 1 +#define I2C_MCTRL_START_M 0x00000002 +#define I2C_MCTRL_START_S 1 +#define I2C_MCTRL_START_EN 0x00000002 +#define I2C_MCTRL_START_DIS 0x00000000 + +// Field: [0] RUN +// +// I2C master enable +// +// 0: The master is disabled. +// 1: The master is enabled to transmit or receive data. +// ENUMs: +// EN Enable Master +// DIS Disable Master +#define I2C_MCTRL_RUN 0x00000001 +#define I2C_MCTRL_RUN_BITN 0 +#define I2C_MCTRL_RUN_M 0x00000001 +#define I2C_MCTRL_RUN_S 0 +#define I2C_MCTRL_RUN_EN 0x00000001 +#define I2C_MCTRL_RUN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MDR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// When Read: Last RX Data is returned +// When Written: Data is transferred during TX transaction +#define I2C_MDR_DATA_W 8 +#define I2C_MDR_DATA_M 0x000000FF +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MTPR +// +//***************************************************************************** +// Field: [7] TPR_7 +// +// Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. +#define I2C_MTPR_TPR_7 0x00000080 +#define I2C_MTPR_TPR_7_BITN 7 +#define I2C_MTPR_TPR_7_M 0x00000080 +#define I2C_MTPR_TPR_7_S 7 + +// Field: [6:0] TPR +// +// SCL clock period +// This field specifies the period of the SCL clock. +// SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD +// where: +// SCL_PRD is the SCL line period (I2C clock). +// TPR is the timer period register value (range of 1 to 127) +// SCL_LP is the SCL low period (fixed at 6). +// SCL_HP is the SCL high period (fixed at 4). +// CLK_PRD is the system clock period in ns. +#define I2C_MTPR_TPR_W 7 +#define I2C_MTPR_TPR_M 0x0000007F +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MIMR +// +//***************************************************************************** +// Field: [0] IM +// +// Interrupt mask +// +// 0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The master interrupt is sent to the interrupt controller when the +// MRIS.RIS is set. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_MIMR_IM 0x00000001 +#define I2C_MIMR_IM_BITN 0 +#define I2C_MIMR_IM_M 0x00000001 +#define I2C_MIMR_IM_S 0 +#define I2C_MIMR_IM_EN 0x00000001 +#define I2C_MIMR_IM_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MRIS +// +//***************************************************************************** +// Field: [0] RIS +// +// Raw interrupt status +// +// 0: No interrupt +// 1: A master interrupt is pending. +// +// This bit is cleared by writing 1 to the MICR.IC bit . +#define I2C_MRIS_RIS 0x00000001 +#define I2C_MRIS_RIS_BITN 0 +#define I2C_MRIS_RIS_M 0x00000001 +#define I2C_MRIS_RIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MMIS +// +//***************************************************************************** +// Field: [0] MIS +// +// Masked interrupt status +// +// 0: An interrupt has not occurred or is masked. +// 1: A master interrupt is pending. +// +// This bit is cleared by writing 1 to the MICR.IC bit . +#define I2C_MMIS_MIS 0x00000001 +#define I2C_MMIS_MIS_BITN 0 +#define I2C_MMIS_MIS_M 0x00000001 +#define I2C_MMIS_MIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MICR +// +//***************************************************************************** +// Field: [0] IC +// +// Interrupt clear +// Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . +// +// Reading this register returns no meaningful data. +#define I2C_MICR_IC 0x00000001 +#define I2C_MICR_IC_BITN 0 +#define I2C_MICR_IC_M 0x00000001 +#define I2C_MICR_IC_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MCR +// +//***************************************************************************** +// Field: [5] SFE +// +// I2C slave function enable +// ENUMs: +// EN Slave mode is enabled. +// DIS Slave mode is disabled. +#define I2C_MCR_SFE 0x00000020 +#define I2C_MCR_SFE_BITN 5 +#define I2C_MCR_SFE_M 0x00000020 +#define I2C_MCR_SFE_S 5 +#define I2C_MCR_SFE_EN 0x00000020 +#define I2C_MCR_SFE_DIS 0x00000000 + +// Field: [4] MFE +// +// I2C master function enable +// ENUMs: +// EN Master mode is enabled. +// DIS Master mode is disabled. +#define I2C_MCR_MFE 0x00000010 +#define I2C_MCR_MFE_BITN 4 +#define I2C_MCR_MFE_M 0x00000010 +#define I2C_MCR_MFE_S 4 +#define I2C_MCR_MFE_EN 0x00000010 +#define I2C_MCR_MFE_DIS 0x00000000 + +// Field: [0] LPBK +// +// I2C loopback +// +// 0: Normal operation +// 1: Loopback operation (test mode) +// ENUMs: +// EN Enable Test Mode +// DIS Disable Test Mode +#define I2C_MCR_LPBK 0x00000001 +#define I2C_MCR_LPBK_BITN 0 +#define I2C_MCR_LPBK_M 0x00000001 +#define I2C_MCR_LPBK_S 0 +#define I2C_MCR_LPBK_EN 0x00000001 +#define I2C_MCR_LPBK_DIS 0x00000000 + + +#endif // __I2C__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h new file mode 100644 index 0000000..a0bfed9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h @@ -0,0 +1,967 @@ +/****************************************************************************** +* Filename: hw_i2s_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_I2S_H__ +#define __HW_I2S_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// I2S component +// +//***************************************************************************** +// WCLK Source Selection +#define I2S_O_AIFWCLKSRC 0x00000000 + +// DMA Buffer Size Configuration +#define I2S_O_AIFDMACFG 0x00000004 + +// Pin Direction +#define I2S_O_AIFDIRCFG 0x00000008 + +// Serial Interface Format Configuration +#define I2S_O_AIFFMTCFG 0x0000000C + +// Word Selection Bit Mask for Pin 0 +#define I2S_O_AIFWMASK0 0x00000010 + +// Word Selection Bit Mask for Pin 1 +#define I2S_O_AIFWMASK1 0x00000014 + +// Audio Interface PWM Debug Value +#define I2S_O_AIFPWMVALUE 0x0000001C + +// DMA Input Buffer Next Pointer +#define I2S_O_AIFINPTRNEXT 0x00000020 + +// DMA Input Buffer Current Pointer +#define I2S_O_AIFINPTR 0x00000024 + +// DMA Output Buffer Next Pointer +#define I2S_O_AIFOUTPTRNEXT 0x00000028 + +// DMA Output Buffer Current Pointer +#define I2S_O_AIFOUTPTR 0x0000002C + +// Samplestamp Generator Control Register +#define I2S_O_STMPCTL 0x00000034 + +// Captured XOSC Counter Value, Capture Channel 0 +#define I2S_O_STMPXCNTCAPT0 0x00000038 + +// XOSC Period Value +#define I2S_O_STMPXPER 0x0000003C + +// Captured WCLK Counter Value, Capture Channel 0 +#define I2S_O_STMPWCNTCAPT0 0x00000040 + +// WCLK Counter Period Value +#define I2S_O_STMPWPER 0x00000044 + +// WCLK Counter Trigger Value for Input Pins +#define I2S_O_STMPINTRIG 0x00000048 + +// WCLK Counter Trigger Value for Output Pins +#define I2S_O_STMPOUTTRIG 0x0000004C + +// WCLK Counter Set Operation +#define I2S_O_STMPWSET 0x00000050 + +// WCLK Counter Add Operation +#define I2S_O_STMPWADD 0x00000054 + +// XOSC Minimum Period Value +#define I2S_O_STMPXPERMIN 0x00000058 + +// Current Value of WCNT +#define I2S_O_STMPWCNT 0x0000005C + +// Current Value of XCNT +#define I2S_O_STMPXCNT 0x00000060 + +// Internal +#define I2S_O_STMPXCNTCAPT1 0x00000064 + +// Internal +#define I2S_O_STMPWCNTCAPT1 0x00000068 + +// Interrupt Mask Register +#define I2S_O_IRQMASK 0x00000070 + +// Raw Interrupt Status Register +#define I2S_O_IRQFLAGS 0x00000074 + +// Interrupt Set Register +#define I2S_O_IRQSET 0x00000078 + +// Interrupt Clear Register +#define I2S_O_IRQCLR 0x0000007C + +//***************************************************************************** +// +// Register: I2S_O_AIFWCLKSRC +// +//***************************************************************************** +// Field: [2] WCLK_INV +// +// Inverts WCLK source (pad or internal) when set. +// +// 0: Not inverted +// 1: Inverted +#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 +#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_S 2 + +// Field: [1:0] WCLK_SRC +// +// Selects WCLK source for AIF (should be the same as the BCLK source). The +// BCLK source is defined in the PRCM:I2SBCLKSEL.SRC +// ENUMs: +// RESERVED Not supported. Will give same WCLK as 'NONE' +// ('00') +// INT Internal WCLK generator, from module PRCM +// EXT External WCLK generator, from pad +// NONE None ('0') +#define I2S_AIFWCLKSRC_WCLK_SRC_W 2 +#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_S 0 +#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 +#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 +#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 + +//***************************************************************************** +// +// Register: I2S_O_AIFDMACFG +// +//***************************************************************************** +// Field: [7:0] END_FRAME_IDX +// +// Defines the length of the DMA buffer. Writing a non-zero value to this +// register field enables and initializes AIF. Note that before doing so, all +// other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must +// have been loaded. +#define I2S_AIFDMACFG_END_FRAME_IDX_W 8 +#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF +#define I2S_AIFDMACFG_END_FRAME_IDX_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFDIRCFG +// +//***************************************************************************** +// Field: [5:4] AD1 +// +// Configures the AD1 audio data pin usage: +// +// 0x3: Reserved +// ENUMs: +// OUT Output mode +// IN Input mode +// DIS Not in use (disabled) +#define I2S_AIFDIRCFG_AD1_W 2 +#define I2S_AIFDIRCFG_AD1_M 0x00000030 +#define I2S_AIFDIRCFG_AD1_S 4 +#define I2S_AIFDIRCFG_AD1_OUT 0x00000020 +#define I2S_AIFDIRCFG_AD1_IN 0x00000010 +#define I2S_AIFDIRCFG_AD1_DIS 0x00000000 + +// Field: [1:0] AD0 +// +// Configures the AD0 audio data pin usage: +// +// 0x3: Reserved +// ENUMs: +// OUT Output mode +// IN Input mode +// DIS Not in use (disabled) +#define I2S_AIFDIRCFG_AD0_W 2 +#define I2S_AIFDIRCFG_AD0_M 0x00000003 +#define I2S_AIFDIRCFG_AD0_S 0 +#define I2S_AIFDIRCFG_AD0_OUT 0x00000002 +#define I2S_AIFDIRCFG_AD0_IN 0x00000001 +#define I2S_AIFDIRCFG_AD0_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2S_O_AIFFMTCFG +// +//***************************************************************************** +// Field: [15:8] DATA_DELAY +// +// The number of BCLK periods between a WCLK edge and MSB of the first word in +// a phase: +// +// 0x00: LJF and DSP format +// 0x01: I2S and DSP format +// 0x02: RJF format +// ... +// 0xFF: RJF format +// +// Note: When 0, MSB of the next word will be output in the idle period between +// LSB of the previous word and the start of the next word. Otherwise logical 0 +// will be output until the data delay has expired. +#define I2S_AIFFMTCFG_DATA_DELAY_W 8 +#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 +#define I2S_AIFFMTCFG_DATA_DELAY_S 8 + +// Field: [7] MEM_LEN_24 +// +// The size of each word stored to or loaded from memory: +// ENUMs: +// 24BIT 24-bit (one 8 bit and one 16 bit locked access per +// sample) +// 16BIT 16-bit (one 16 bit access per sample) +#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_S 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 + +// Field: [6] SMPL_EDGE +// +// On the serial audio interface, data (and wclk) is sampled and clocked out on +// opposite edges of BCLK. +// ENUMs: +// POS Data is sampled on the positive edge and clocked +// out on the negative edge. +// NEG Data is sampled on the negative edge and clocked +// out on the positive edge. +#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_S 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 + +// Field: [5] DUAL_PHASE +// +// Selects dual- or single-phase format. +// +// 0: Single-phase: DSP format +// 1: Dual-phase: I2S, LJF and RJF formats +#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 +#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_S 5 + +// Field: [4:0] WORD_LEN +// +// Number of bits per word (8-24): +// In single-phase format, this is the exact number of bits per word. +// In dual-phase format, this is the maximum number of bits per word. +// +// Values below 8 and above 24 give undefined behavior. Data written to memory +// is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that +// differ from this alignment will either be truncated or zero padded. +#define I2S_AIFFMTCFG_WORD_LEN_W 5 +#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F +#define I2S_AIFFMTCFG_WORD_LEN_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFWMASK0 +// +//***************************************************************************** +// Field: [7:0] MASK +// +// Bit-mask indicating valid channels in a frame on AD0. +// +// In single-phase mode, each bit represents one channel, starting with LSB for +// the first word in the frame. A frame can contain up to 8 channels. Channels +// that are not included in the mask will not be sampled and stored in memory, +// and clocked out as '0'. +// +// In dual-phase mode, only the two LSBs are considered. For a stereo +// configuration, set both bits. For a mono configuration, set bit 0 only. In +// mono mode, only channel 0 will be sampled and stored to memory, and channel +// 0 will be repeated when clocked out. +// +// In mono mode, only channel 0 will be sampled and stored to memory, and +// channel 0 will be repeated in the second phase when clocked out. +// +// If all bits are zero, no input words will be stored to memory, and the +// output data lines will be constant '0'. This can be utilized when PWM debug +// output is desired without any actively used output pins. +#define I2S_AIFWMASK0_MASK_W 8 +#define I2S_AIFWMASK0_MASK_M 0x000000FF +#define I2S_AIFWMASK0_MASK_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFWMASK1 +// +//***************************************************************************** +// Field: [7:0] MASK +// +// Bit-mask indicating valid channels in a frame on AD1. +// +// In single-phase mode, each bit represents one channel, starting with LSB for +// the first word in the frame. A frame can contain up to 8 channels. Channels +// that are not included in the mask will not be sampled and stored in memory, +// and clocked out as '0'. +// +// In dual-phase mode, only the two LSBs are considered. For a stereo +// configuration, set both bits. For a mono configuration, set bit 0 only. In +// mono mode, only channel 0 will be sampled and stored to memory, and channel +// 0 will be repeated when clocked out. +// +// In mono mode, only channel 0 will be sampled and stored to memory, and +// channel 0 will be repeated in the second phase when clocked out. +// +// If all bits are zero, no input words will be stored to memory, and the +// output data lines will be constant '0'. This can be utilized when PWM debug +// output is desired without any actively used output pins. +#define I2S_AIFWMASK1_MASK_W 8 +#define I2S_AIFWMASK1_MASK_M 0x000000FF +#define I2S_AIFWMASK1_MASK_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFPWMVALUE +// +//***************************************************************************** +// Field: [15:0] PULSE_WIDTH +// +// The value written to this register determines the width of the active high +// PWM pulse (pwm_debug), which starts together with MSB of the first output +// word in a DMA buffer: +// +// 0x0000: Constant low +// 0x0001: Width of the pulse (number of BCLK cycles, here 1). +// ... +// 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). +// 0xFFFF: Constant high +#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 +#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF +#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFINPTRNEXT +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Pointer to the first byte in the next DMA input buffer. +// +// The read value equals the last written value until the currently used DMA +// input buffer is completed, and then becomes null when the last written value +// is transferred to the DMA controller to start on the next buffer. This event +// is signalized by IRQFLAGS.AIF_DMA_IN. +// +// At startup, the value must be written once before and once after configuring +// the DMA buffer size in AIFDMACFG. +// +// The next pointer must be written to this register while the DMA function +// uses the previously written pointer. If not written in time, +// IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. +#define I2S_AIFINPTRNEXT_PTR_W 32 +#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTRNEXT_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFINPTR +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Value of the DMA input buffer pointer currently used by the DMA controller. +// Incremented by 1 (byte) or 2 (word) for each AHB access. +#define I2S_AIFINPTR_PTR_W 32 +#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTR_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFOUTPTRNEXT +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Pointer to the first byte in the next DMA output buffer. +// +// The read value equals the last written value until the currently used DMA +// output buffer is completed, and then becomes null when the last written +// value is transferred to the DMA controller to start on the next buffer. This +// event is signalized by IRQFLAGS.AIF_DMA_OUT. +// +// At startup, the value must be written once before and once after configuring +// the DMA buffer size in AIFDMACFG. At this time, the first two samples will +// be fetched from memory. +// +// The next pointer must be written to this register while the DMA function +// uses the previously written pointer. If not written in time, +// IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. +#define I2S_AIFOUTPTRNEXT_PTR_W 32 +#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTRNEXT_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFOUTPTR +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Value of the DMA output buffer pointer currently used by the DMA controller +// Incremented by 1 (byte) or 2 (word) for each AHB access. +#define I2S_AIFOUTPTR_PTR_W 32 +#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTR_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPCTL +// +//***************************************************************************** +// Field: [2] OUT_RDY +// +// Low until the output pins are ready to be started by the samplestamp +// generator. When started (that is STMPOUTTRIG equals the WCLK counter) the +// bit goes back low. +#define I2S_STMPCTL_OUT_RDY 0x00000004 +#define I2S_STMPCTL_OUT_RDY_BITN 2 +#define I2S_STMPCTL_OUT_RDY_M 0x00000004 +#define I2S_STMPCTL_OUT_RDY_S 2 + +// Field: [1] IN_RDY +// +// Low until the input pins are ready to be started by the samplestamp +// generator. When started (that is STMPINTRIG equals the WCLK counter) the bit +// goes back low. +#define I2S_STMPCTL_IN_RDY 0x00000002 +#define I2S_STMPCTL_IN_RDY_BITN 1 +#define I2S_STMPCTL_IN_RDY_M 0x00000002 +#define I2S_STMPCTL_IN_RDY_S 1 + +// Field: [0] STMP_EN +// +// Enables the samplestamp generator. The samplestamp generator must only be +// enabled after it has been properly configured. +// When cleared, all samplestamp generator counters and capture values are +// cleared. +#define I2S_STMPCTL_STMP_EN 0x00000001 +#define I2S_STMPCTL_STMP_EN_BITN 0 +#define I2S_STMPCTL_STMP_EN_M 0x00000001 +#define I2S_STMPCTL_STMP_EN_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNTCAPT0 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an +// event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for +// channel 0). This number corresponds to the number of 24 MHz clock cycles +// since the last positive edge of the selected WCLK. +// The value is cleared when STMPCTL.STMP_EN = 0. +// Note: Due to buffering and synchronization, WCLK is delayed by a small +// number of BCLK periods and clk periods. +// Note: When calculating the fractional part of the sample stamp, STMPXPER may +// be less than this bit field. +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXPER +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// The number of 24 MHz clock cycles in the previous WCLK period (that is - +// the next value of the XOSC counter at the positive WCLK edge, had it not +// been reset to 0). +// The value is cleared when STMPCTL.STMP_EN = 0. +#define I2S_STMPXPER_VALUE_W 16 +#define I2S_STMPXPER_VALUE_M 0x0000FFFF +#define I2S_STMPXPER_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNTCAPT0 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an +// event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel +// 0). This number corresponds to the number of positive WCLK edges since the +// samplestamp generator was enabled (not taking modification through +// STMPWADD/STMPWSET into account). +// The value is cleared when STMPCTL.STMP_EN = 0. +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWPER +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Used to define when STMPWCNT is to be reset so number of WCLK edges are +// found for the size of the sample buffer. This is thus a modulo value for the +// WCLK counter. This number must correspond to the size of the sample buffer +// used by the system (that is the index of the last sample plus 1). +#define I2S_STMPWPER_VALUE_W 16 +#define I2S_STMPWPER_VALUE_M 0x0000FFFF +#define I2S_STMPWPER_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPINTRIG +// +//***************************************************************************** +// Field: [15:0] IN_START_WCNT +// +// Compare value used to start the incoming audio streams. +// This bit field shall equal the WCLK counter value during the WCLK period in +// which the first input word(s) are sampled and stored to memory (that is the +// sample at the start of the very first DMA input buffer). +// +// The value of this register takes effect when the following conditions are +// met: +// - One or more pins are configured as inputs in AIFDIRCFG. +// - AIFDMACFG has been configured for the correct buffer size, and at least 32 +// BCLK cycle ticks have happened. +// +// Note: To avoid false triggers, this bit field should be set higher than +// STMPWPER.VALUE. +#define I2S_STMPINTRIG_IN_START_WCNT_W 16 +#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF +#define I2S_STMPINTRIG_IN_START_WCNT_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPOUTTRIG +// +//***************************************************************************** +// Field: [15:0] OUT_START_WCNT +// +// Compare value used to start the outgoing audio streams. +// +// This bit field must equal the WCLK counter value during the WCLK period in +// which the first output word(s) read from memory are clocked out (that is the +// sample at the start of the very first DMA output buffer). +// +// The value of this register takes effect when the following conditions are +// met: +// - One or more pins are configured as outputs in AIFDIRCFG. +// - AIFDMACFG has been configured for the correct buffer size, and 32 BCLK +// cycle ticks have happened. +// - 2 samples have been preloaded from memory (examine the AIFOUTPTR register +// if necessary). +// Note: The memory read access is only performed when required, that is +// channels 0/1 must be selected in AIFWMASK0/AIFWMASK1. +// +// Note: To avoid false triggers, this bit field should be set higher than +// STMPWPER.VALUE. +#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 +#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF +#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWSET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// WCLK counter modification: Sets the running WCLK counter equal to the +// written value. +#define I2S_STMPWSET_VALUE_W 16 +#define I2S_STMPWSET_VALUE_M 0x0000FFFF +#define I2S_STMPWSET_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWADD +// +//***************************************************************************** +// Field: [15:0] VALUE_INC +// +// WCLK counter modification: Adds the written value to the running WCLK +// counter. If a positive edge of WCLK occurs at the same time as the +// operation, this will be taken into account. +// To add a negative value, write "STMPWPER.VALUE - value". +// +#define I2S_STMPWADD_VALUE_INC_W 16 +#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF +#define I2S_STMPWADD_VALUE_INC_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXPERMIN +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Each time STMPXPER is updated, the value is also loaded into this register, +// provided that the value is smaller than the current value in this register. +// When written, the register is reset to 0xFFFF (65535), regardless of the +// value written. +// The minimum value can be used to detect extra WCLK pulses (this registers +// value will be significantly smaller than STMPXPER.VALUE). +#define I2S_STMPXPERMIN_VALUE_W 16 +#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF +#define I2S_STMPXPERMIN_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNT +// +//***************************************************************************** +// Field: [15:0] CURR_VALUE +// +// Current value of the WCLK counter +#define I2S_STMPWCNT_CURR_VALUE_W 16 +#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPWCNT_CURR_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNT +// +//***************************************************************************** +// Field: [15:0] CURR_VALUE +// +// Current value of the XOSC counter, latched when reading STMPWCNT. +#define I2S_STMPXCNT_CURR_VALUE_W 16 +#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPXCNT_CURR_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNTCAPT1 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// Internal. Only to be used through TI provided API. +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNTCAPT1 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// Internal. Only to be used through TI provided API. +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQMASK +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// IRQFLAGS.AIF_DMA_IN interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_AIF_DMA_IN 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_BITN 5 +#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// IRQFLAGS.AIF_DMA_OUT interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 +#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// IRQFLAGS.WCLK_TIMEOUT interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// IRQFLAGS.BUS_ERR interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_BUS_ERR 0x00000004 +#define I2S_IRQMASK_BUS_ERR_BITN 2 +#define I2S_IRQMASK_BUS_ERR_M 0x00000004 +#define I2S_IRQMASK_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// IRQFLAGS.WCLK_ERR interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_WCLK_ERR 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_BITN 1 +#define I2S_IRQMASK_WCLK_ERR_M 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// IRQFLAGS.PTR_ERR interrupt mask. +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_PTR_ERR 0x00000001 +#define I2S_IRQMASK_PTR_ERR_BITN 0 +#define I2S_IRQMASK_PTR_ERR_M 0x00000001 +#define I2S_IRQMASK_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQFLAGS +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// Set when condition for this bit field event occurs (auto cleared when input +// pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register +// for details. +#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 +#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// Set when condition for this bit field event occurs (auto cleared when output +// pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT +// register for details +#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 +#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// Set when the sample stamp generator does not detect a positive WCLK edge for +// 65535 clk periods. This signalizes that the internal or external BCLK and +// WCLK generator source has been disabled. +// +// The bit is sticky and may only be cleared by software (by writing '1' to +// IRQCLR.WCLK_TIMEOUT). +#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// Set when a DMA operation is not completed in time (that is audio output +// buffer underflow, or audio input buffer overflow). +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.BUS_ERR). +// +// Note that DMA initiated transactions to illegal addresses will not trigger +// an interrupt. The response to such transactions is undefined. +#define I2S_IRQFLAGS_BUS_ERR 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_BITN 2 +#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// Set when: +// - An unexpected WCLK edge occurs during the data delay period of a phase. +// Note unexpected WCLK edges during the word and idle periods of the phase are +// not detected. +// - In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles +// apart. +// - In single-phase mode, when a WCLK pulse occurs before the last channel. +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.WCLK_ERR). +#define I2S_IRQFLAGS_WCLK_ERR 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_BITN 1 +#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next +// block address in time. +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.PTR_ERR). +#define I2S_IRQFLAGS_PTR_ERR 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_BITN 0 +#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQSET +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria +// was given at the same time, in which the set will be ignored) +#define I2S_IRQSET_AIF_DMA_IN 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_BITN 5 +#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria +// was given at the same time, in which the set will be ignored) +#define I2S_IRQSET_AIF_DMA_OUT 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_BITN 4 +#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT +#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// 1: Sets the interrupt of IRQFLAGS.BUS_ERR +#define I2S_IRQSET_BUS_ERR 0x00000004 +#define I2S_IRQSET_BUS_ERR_BITN 2 +#define I2S_IRQSET_BUS_ERR_M 0x00000004 +#define I2S_IRQSET_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// 1: Sets the interrupt of IRQFLAGS.WCLK_ERR +#define I2S_IRQSET_WCLK_ERR 0x00000002 +#define I2S_IRQSET_WCLK_ERR_BITN 1 +#define I2S_IRQSET_WCLK_ERR_M 0x00000002 +#define I2S_IRQSET_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// 1: Sets the interrupt of IRQFLAGS.PTR_ERR +#define I2S_IRQSET_PTR_ERR 0x00000001 +#define I2S_IRQSET_PTR_ERR_BITN 0 +#define I2S_IRQSET_PTR_ERR_M 0x00000001 +#define I2S_IRQSET_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQCLR +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_AIF_DMA_IN 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_BITN 5 +#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 +#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given +// at the same time in which the clear will be ignored) +#define I2S_IRQCLR_BUS_ERR 0x00000004 +#define I2S_IRQCLR_BUS_ERR_BITN 2 +#define I2S_IRQCLR_BUS_ERR_M 0x00000004 +#define I2S_IRQCLR_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_WCLK_ERR 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_BITN 1 +#define I2S_IRQCLR_WCLK_ERR_M 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given +// at the same time in which the clear will be ignored) +#define I2S_IRQCLR_PTR_ERR 0x00000001 +#define I2S_IRQCLR_PTR_ERR_BITN 0 +#define I2S_IRQCLR_PTR_ERR_M 0x00000001 +#define I2S_IRQCLR_PTR_ERR_S 0 + + +#endif // __I2S__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ints.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ints.h new file mode 100644 index 0000000..481ae09 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ints.h @@ -0,0 +1,120 @@ +/****************************************************************************** +* Filename: hw_ints_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_NMI_FAULT 2 // NMI Fault +#define INT_HARD_FAULT 3 // Hard Fault +#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage) + // Fault +#define INT_BUS_FAULT 5 // Bus Fault +#define INT_USAGE_FAULT 6 // Usage Fault +#define INT_SVCALL 11 // Supervisor Call (SVCall) +#define INT_DEBUG 12 // Debug Monitor +#define INT_PENDSV 14 // Pending Service Call (PendSV) +#define INT_SYSTICK 15 // SysTick Interrupt from the + // System Timer in NVIC. +#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC +#define INT_I2C_IRQ 17 // Interrupt event from I2C +#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE + // Generated events +#define INT_PKA_IRQ 19 // PKA Interrupt event +#define INT_AON_RTC_COMB 20 // Event from AON_RTC +#define INT_UART0_COMB 21 // UART0 combined interrupt +#define INT_AUX_SWEV0 22 // AUX software event 0 +#define INT_SSI0_COMB 23 // SSI0 combined interrupt +#define INT_SSI1_COMB 24 // SSI1 combined interrupt +#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE + // Generated events +#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt +#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command + // Acknowledgement Interrupt +#define INT_I2S_IRQ 28 // Interrupt event from I2S +#define INT_AUX_SWEV1 29 // AUX software event 1 +#define INT_WDT_IRQ 30 // Watchdog interrupt event +#define INT_GPT0A 31 // GPT0A interrupt event +#define INT_GPT0B 32 // GPT0B interrupt event +#define INT_GPT1A 33 // GPT1A interrupt event +#define INT_GPT1B 34 // GPT1B interrupt event +#define INT_GPT2A 35 // GPT2A interrupt event +#define INT_GPT2B 36 // GPT2B interrupt event +#define INT_GPT3A 37 // GPT3A interrupt event +#define INT_GPT3B 38 // GPT3B interrupt event +#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt + // event +#define INT_DMA_DONE_COMB 40 // Combined DMA done +#define INT_DMA_ERR 41 // DMA bus error +#define INT_FLASH 42 // FLASH controller error event +#define INT_SWEV0 43 // Software event 0 +#define INT_AUX_COMB 44 // AUX combined event +#define INT_AON_PROG0 45 // AON programmable event 0 +#define INT_PROG0 46 // Programmable Interrupt 0 +#define INT_AUX_COMPA 47 // AUX Compare A event +#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event +#define INT_TRNG_IRQ 49 // TRNG Interrupt event +#define INT_OSC_COMB 50 // Combined event from Oscillator + // control +#define INT_AUX_TIMER2_EV0 51 // AUX Timer2 event 0 +#define INT_UART1_COMB 52 // UART1 combined interrupt +#define INT_BATMON_COMB 53 // Combined event from battery + // monitor + +//***************************************************************************** +// +// The following are defines for number of interrupts and priority levels. +// +//***************************************************************************** +#define NUM_INTERRUPTS 54 // Number of interrupts +#define NUM_PRIORITY_BITS 3 // Number of Priority bits +#define NUM_PRIORITY 8 // Number of priority levels + + +//***************************************************************************** +// +// Aliases for backwards compatibility with Sensor Controller Studio 1.1.0 +// +//***************************************************************************** + +#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0 +#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1 + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h new file mode 100644 index 0000000..53ab201 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h @@ -0,0 +1,11887 @@ +/****************************************************************************** +* Filename: hw_ioc_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_IOC_H__ +#define __HW_IOC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// IOC component +// +//***************************************************************************** +// Configuration of DIO0 +#define IOC_O_IOCFG0 0x00000000 + +// Configuration of DIO1 +#define IOC_O_IOCFG1 0x00000004 + +// Configuration of DIO2 +#define IOC_O_IOCFG2 0x00000008 + +// Configuration of DIO3 +#define IOC_O_IOCFG3 0x0000000C + +// Configuration of DIO4 +#define IOC_O_IOCFG4 0x00000010 + +// Configuration of DIO5 +#define IOC_O_IOCFG5 0x00000014 + +// Configuration of DIO6 +#define IOC_O_IOCFG6 0x00000018 + +// Configuration of DIO7 +#define IOC_O_IOCFG7 0x0000001C + +// Configuration of DIO8 +#define IOC_O_IOCFG8 0x00000020 + +// Configuration of DIO9 +#define IOC_O_IOCFG9 0x00000024 + +// Configuration of DIO10 +#define IOC_O_IOCFG10 0x00000028 + +// Configuration of DIO11 +#define IOC_O_IOCFG11 0x0000002C + +// Configuration of DIO12 +#define IOC_O_IOCFG12 0x00000030 + +// Configuration of DIO13 +#define IOC_O_IOCFG13 0x00000034 + +// Configuration of DIO14 +#define IOC_O_IOCFG14 0x00000038 + +// Configuration of DIO15 +#define IOC_O_IOCFG15 0x0000003C + +// Configuration of DIO16 +#define IOC_O_IOCFG16 0x00000040 + +// Configuration of DIO17 +#define IOC_O_IOCFG17 0x00000044 + +// Configuration of DIO18 +#define IOC_O_IOCFG18 0x00000048 + +// Configuration of DIO19 +#define IOC_O_IOCFG19 0x0000004C + +// Configuration of DIO20 +#define IOC_O_IOCFG20 0x00000050 + +// Configuration of DIO21 +#define IOC_O_IOCFG21 0x00000054 + +// Configuration of DIO22 +#define IOC_O_IOCFG22 0x00000058 + +// Configuration of DIO23 +#define IOC_O_IOCFG23 0x0000005C + +// Configuration of DIO24 +#define IOC_O_IOCFG24 0x00000060 + +// Configuration of DIO25 +#define IOC_O_IOCFG25 0x00000064 + +// Configuration of DIO26 +#define IOC_O_IOCFG26 0x00000068 + +// Configuration of DIO27 +#define IOC_O_IOCFG27 0x0000006C + +// Configuration of DIO28 +#define IOC_O_IOCFG28 0x00000070 + +// Configuration of DIO29 +#define IOC_O_IOCFG29 0x00000074 + +// Configuration of DIO30 +#define IOC_O_IOCFG30 0x00000078 + +// Configuration of DIO31 +#define IOC_O_IOCFG31 0x0000007C + +//***************************************************************************** +// +// Register: IOC_O_IOCFG0 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG0_HYST_EN 0x40000000 +#define IOC_IOCFG0_HYST_EN_BITN 30 +#define IOC_IOCFG0_HYST_EN_M 0x40000000 +#define IOC_IOCFG0_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG0_IE 0x20000000 +#define IOC_IOCFG0_IE_BITN 29 +#define IOC_IOCFG0_IE_M 0x20000000 +#define IOC_IOCFG0_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG0_WU_CFG_W 2 +#define IOC_IOCFG0_WU_CFG_M 0x18000000 +#define IOC_IOCFG0_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input/output +// OPENSRC Open Source +// Normal input / outut +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG0_IOMODE_W 3 +#define IOC_IOCFG0_IOMODE_M 0x07000000 +#define IOC_IOCFG0_IOMODE_S 24 +#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG0_IOMODE_INV 0x01000000 +#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG0_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG0_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG0_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG0_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG0_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG0_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG0_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG0_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG0_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG0_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG0_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG0_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG0_EDGE_DET_W 2 +#define IOC_IOCFG0_EDGE_DET_M 0x00030000 +#define IOC_IOCFG0_EDGE_DET_S 16 +#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG0_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG0_PULL_CTL_W 2 +#define IOC_IOCFG0_PULL_CTL_M 0x00006000 +#define IOC_IOCFG0_PULL_CTL_S 13 +#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG0_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG0_SLEW_RED 0x00001000 +#define IOC_IOCFG0_SLEW_RED_BITN 12 +#define IOC_IOCFG0_SLEW_RED_M 0x00001000 +#define IOC_IOCFG0_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG0_IOCURR_W 2 +#define IOC_IOCFG0_IOCURR_M 0x00000C00 +#define IOC_IOCFG0_IOCURR_S 10 +#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG0_IOCURR_4MA 0x00000400 +#define IOC_IOCFG0_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG0_IOSTR_W 2 +#define IOC_IOCFG0_IOSTR_M 0x00000300 +#define IOC_IOCFG0_IOSTR_S 8 +#define IOC_IOCFG0_IOSTR_MAX 0x00000300 +#define IOC_IOCFG0_IOSTR_MED 0x00000200 +#define IOC_IOCFG0_IOSTR_MIN 0x00000100 +#define IOC_IOCFG0_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG0_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG0_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG0_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG0_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG0_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG0_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG0_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG0_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO0 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG0_PORT_ID_W 6 +#define IOC_IOCFG0_PORT_ID_M 0x0000003F +#define IOC_IOCFG0_PORT_ID_S 0 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG0_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG0_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG0_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG0_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG1 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG1_HYST_EN 0x40000000 +#define IOC_IOCFG1_HYST_EN_BITN 30 +#define IOC_IOCFG1_HYST_EN_M 0x40000000 +#define IOC_IOCFG1_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG1_IE 0x20000000 +#define IOC_IOCFG1_IE_BITN 29 +#define IOC_IOCFG1_IE_M 0x20000000 +#define IOC_IOCFG1_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG1_WU_CFG_W 2 +#define IOC_IOCFG1_WU_CFG_M 0x18000000 +#define IOC_IOCFG1_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG1_IOMODE_W 3 +#define IOC_IOCFG1_IOMODE_M 0x07000000 +#define IOC_IOCFG1_IOMODE_S 24 +#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG1_IOMODE_INV 0x01000000 +#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG1_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG1_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG1_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG1_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG1_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG1_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG1_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG1_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG1_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG1_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG1_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG1_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG1_EDGE_DET_W 2 +#define IOC_IOCFG1_EDGE_DET_M 0x00030000 +#define IOC_IOCFG1_EDGE_DET_S 16 +#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG1_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG1_PULL_CTL_W 2 +#define IOC_IOCFG1_PULL_CTL_M 0x00006000 +#define IOC_IOCFG1_PULL_CTL_S 13 +#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG1_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG1_SLEW_RED 0x00001000 +#define IOC_IOCFG1_SLEW_RED_BITN 12 +#define IOC_IOCFG1_SLEW_RED_M 0x00001000 +#define IOC_IOCFG1_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG1_IOCURR_W 2 +#define IOC_IOCFG1_IOCURR_M 0x00000C00 +#define IOC_IOCFG1_IOCURR_S 10 +#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG1_IOCURR_4MA 0x00000400 +#define IOC_IOCFG1_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG1_IOSTR_W 2 +#define IOC_IOCFG1_IOSTR_M 0x00000300 +#define IOC_IOCFG1_IOSTR_S 8 +#define IOC_IOCFG1_IOSTR_MAX 0x00000300 +#define IOC_IOCFG1_IOSTR_MED 0x00000200 +#define IOC_IOCFG1_IOSTR_MIN 0x00000100 +#define IOC_IOCFG1_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG1_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG1_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG1_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG1_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG1_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG1_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG1_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG1_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO1 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG1_PORT_ID_W 6 +#define IOC_IOCFG1_PORT_ID_M 0x0000003F +#define IOC_IOCFG1_PORT_ID_S 0 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG1_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG1_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG1_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG1_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG2 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG2_HYST_EN 0x40000000 +#define IOC_IOCFG2_HYST_EN_BITN 30 +#define IOC_IOCFG2_HYST_EN_M 0x40000000 +#define IOC_IOCFG2_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG2_IE 0x20000000 +#define IOC_IOCFG2_IE_BITN 29 +#define IOC_IOCFG2_IE_M 0x20000000 +#define IOC_IOCFG2_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG2_WU_CFG_W 2 +#define IOC_IOCFG2_WU_CFG_M 0x18000000 +#define IOC_IOCFG2_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG2_IOMODE_W 3 +#define IOC_IOCFG2_IOMODE_M 0x07000000 +#define IOC_IOCFG2_IOMODE_S 24 +#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG2_IOMODE_INV 0x01000000 +#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG2_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG2_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG2_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG2_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG2_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG2_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG2_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG2_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG2_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG2_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG2_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG2_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG2_EDGE_DET_W 2 +#define IOC_IOCFG2_EDGE_DET_M 0x00030000 +#define IOC_IOCFG2_EDGE_DET_S 16 +#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG2_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG2_PULL_CTL_W 2 +#define IOC_IOCFG2_PULL_CTL_M 0x00006000 +#define IOC_IOCFG2_PULL_CTL_S 13 +#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG2_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG2_SLEW_RED 0x00001000 +#define IOC_IOCFG2_SLEW_RED_BITN 12 +#define IOC_IOCFG2_SLEW_RED_M 0x00001000 +#define IOC_IOCFG2_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG2_IOCURR_W 2 +#define IOC_IOCFG2_IOCURR_M 0x00000C00 +#define IOC_IOCFG2_IOCURR_S 10 +#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG2_IOCURR_4MA 0x00000400 +#define IOC_IOCFG2_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG2_IOSTR_W 2 +#define IOC_IOCFG2_IOSTR_M 0x00000300 +#define IOC_IOCFG2_IOSTR_S 8 +#define IOC_IOCFG2_IOSTR_MAX 0x00000300 +#define IOC_IOCFG2_IOSTR_MED 0x00000200 +#define IOC_IOCFG2_IOSTR_MIN 0x00000100 +#define IOC_IOCFG2_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG2_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG2_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG2_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG2_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG2_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG2_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG2_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG2_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO2 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG2_PORT_ID_W 6 +#define IOC_IOCFG2_PORT_ID_M 0x0000003F +#define IOC_IOCFG2_PORT_ID_S 0 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG2_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG2_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG2_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG2_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG3 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG3_HYST_EN 0x40000000 +#define IOC_IOCFG3_HYST_EN_BITN 30 +#define IOC_IOCFG3_HYST_EN_M 0x40000000 +#define IOC_IOCFG3_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG3_IE 0x20000000 +#define IOC_IOCFG3_IE_BITN 29 +#define IOC_IOCFG3_IE_M 0x20000000 +#define IOC_IOCFG3_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG3_WU_CFG_W 2 +#define IOC_IOCFG3_WU_CFG_M 0x18000000 +#define IOC_IOCFG3_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG3_IOMODE_W 3 +#define IOC_IOCFG3_IOMODE_M 0x07000000 +#define IOC_IOCFG3_IOMODE_S 24 +#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG3_IOMODE_INV 0x01000000 +#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG3_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG3_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG3_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG3_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG3_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG3_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG3_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG3_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG3_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG3_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG3_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG3_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG3_EDGE_DET_W 2 +#define IOC_IOCFG3_EDGE_DET_M 0x00030000 +#define IOC_IOCFG3_EDGE_DET_S 16 +#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG3_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG3_PULL_CTL_W 2 +#define IOC_IOCFG3_PULL_CTL_M 0x00006000 +#define IOC_IOCFG3_PULL_CTL_S 13 +#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG3_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG3_SLEW_RED 0x00001000 +#define IOC_IOCFG3_SLEW_RED_BITN 12 +#define IOC_IOCFG3_SLEW_RED_M 0x00001000 +#define IOC_IOCFG3_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG3_IOCURR_W 2 +#define IOC_IOCFG3_IOCURR_M 0x00000C00 +#define IOC_IOCFG3_IOCURR_S 10 +#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG3_IOCURR_4MA 0x00000400 +#define IOC_IOCFG3_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG3_IOSTR_W 2 +#define IOC_IOCFG3_IOSTR_M 0x00000300 +#define IOC_IOCFG3_IOSTR_S 8 +#define IOC_IOCFG3_IOSTR_MAX 0x00000300 +#define IOC_IOCFG3_IOSTR_MED 0x00000200 +#define IOC_IOCFG3_IOSTR_MIN 0x00000100 +#define IOC_IOCFG3_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG3_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG3_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG3_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG3_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG3_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG3_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG3_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG3_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO3 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG3_PORT_ID_W 6 +#define IOC_IOCFG3_PORT_ID_M 0x0000003F +#define IOC_IOCFG3_PORT_ID_S 0 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG3_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG3_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG3_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG3_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG4 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG4_HYST_EN 0x40000000 +#define IOC_IOCFG4_HYST_EN_BITN 30 +#define IOC_IOCFG4_HYST_EN_M 0x40000000 +#define IOC_IOCFG4_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG4_IE 0x20000000 +#define IOC_IOCFG4_IE_BITN 29 +#define IOC_IOCFG4_IE_M 0x20000000 +#define IOC_IOCFG4_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG4_WU_CFG_W 2 +#define IOC_IOCFG4_WU_CFG_M 0x18000000 +#define IOC_IOCFG4_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG4_IOMODE_W 3 +#define IOC_IOCFG4_IOMODE_M 0x07000000 +#define IOC_IOCFG4_IOMODE_S 24 +#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG4_IOMODE_INV 0x01000000 +#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG4_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG4_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG4_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG4_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG4_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG4_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG4_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG4_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG4_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG4_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG4_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG4_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG4_EDGE_DET_W 2 +#define IOC_IOCFG4_EDGE_DET_M 0x00030000 +#define IOC_IOCFG4_EDGE_DET_S 16 +#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG4_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG4_PULL_CTL_W 2 +#define IOC_IOCFG4_PULL_CTL_M 0x00006000 +#define IOC_IOCFG4_PULL_CTL_S 13 +#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG4_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG4_SLEW_RED 0x00001000 +#define IOC_IOCFG4_SLEW_RED_BITN 12 +#define IOC_IOCFG4_SLEW_RED_M 0x00001000 +#define IOC_IOCFG4_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG4_IOCURR_W 2 +#define IOC_IOCFG4_IOCURR_M 0x00000C00 +#define IOC_IOCFG4_IOCURR_S 10 +#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG4_IOCURR_4MA 0x00000400 +#define IOC_IOCFG4_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG4_IOSTR_W 2 +#define IOC_IOCFG4_IOSTR_M 0x00000300 +#define IOC_IOCFG4_IOSTR_S 8 +#define IOC_IOCFG4_IOSTR_MAX 0x00000300 +#define IOC_IOCFG4_IOSTR_MED 0x00000200 +#define IOC_IOCFG4_IOSTR_MIN 0x00000100 +#define IOC_IOCFG4_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG4_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG4_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG4_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG4_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG4_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG4_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG4_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG4_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO4 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG4_PORT_ID_W 6 +#define IOC_IOCFG4_PORT_ID_M 0x0000003F +#define IOC_IOCFG4_PORT_ID_S 0 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG4_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG4_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG4_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG4_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG5 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG5_HYST_EN 0x40000000 +#define IOC_IOCFG5_HYST_EN_BITN 30 +#define IOC_IOCFG5_HYST_EN_M 0x40000000 +#define IOC_IOCFG5_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG5_IE 0x20000000 +#define IOC_IOCFG5_IE_BITN 29 +#define IOC_IOCFG5_IE_M 0x20000000 +#define IOC_IOCFG5_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG5_WU_CFG_W 2 +#define IOC_IOCFG5_WU_CFG_M 0x18000000 +#define IOC_IOCFG5_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG5_IOMODE_W 3 +#define IOC_IOCFG5_IOMODE_M 0x07000000 +#define IOC_IOCFG5_IOMODE_S 24 +#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG5_IOMODE_INV 0x01000000 +#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG5_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG5_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG5_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG5_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG5_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG5_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG5_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG5_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG5_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG5_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG5_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG5_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG5_EDGE_DET_W 2 +#define IOC_IOCFG5_EDGE_DET_M 0x00030000 +#define IOC_IOCFG5_EDGE_DET_S 16 +#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG5_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG5_PULL_CTL_W 2 +#define IOC_IOCFG5_PULL_CTL_M 0x00006000 +#define IOC_IOCFG5_PULL_CTL_S 13 +#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG5_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG5_SLEW_RED 0x00001000 +#define IOC_IOCFG5_SLEW_RED_BITN 12 +#define IOC_IOCFG5_SLEW_RED_M 0x00001000 +#define IOC_IOCFG5_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG5_IOCURR_W 2 +#define IOC_IOCFG5_IOCURR_M 0x00000C00 +#define IOC_IOCFG5_IOCURR_S 10 +#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG5_IOCURR_4MA 0x00000400 +#define IOC_IOCFG5_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG5_IOSTR_W 2 +#define IOC_IOCFG5_IOSTR_M 0x00000300 +#define IOC_IOCFG5_IOSTR_S 8 +#define IOC_IOCFG5_IOSTR_MAX 0x00000300 +#define IOC_IOCFG5_IOSTR_MED 0x00000200 +#define IOC_IOCFG5_IOSTR_MIN 0x00000100 +#define IOC_IOCFG5_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG5_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG5_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG5_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG5_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG5_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG5_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG5_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG5_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO5 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG5_PORT_ID_W 6 +#define IOC_IOCFG5_PORT_ID_M 0x0000003F +#define IOC_IOCFG5_PORT_ID_S 0 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG5_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG5_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG5_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG5_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG6 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG6_HYST_EN 0x40000000 +#define IOC_IOCFG6_HYST_EN_BITN 30 +#define IOC_IOCFG6_HYST_EN_M 0x40000000 +#define IOC_IOCFG6_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG6_IE 0x20000000 +#define IOC_IOCFG6_IE_BITN 29 +#define IOC_IOCFG6_IE_M 0x20000000 +#define IOC_IOCFG6_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG6_WU_CFG_W 2 +#define IOC_IOCFG6_WU_CFG_M 0x18000000 +#define IOC_IOCFG6_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG6_IOMODE_W 3 +#define IOC_IOCFG6_IOMODE_M 0x07000000 +#define IOC_IOCFG6_IOMODE_S 24 +#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG6_IOMODE_INV 0x01000000 +#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG6_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG6_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG6_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG6_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG6_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG6_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG6_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG6_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG6_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG6_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG6_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG6_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG6_EDGE_DET_W 2 +#define IOC_IOCFG6_EDGE_DET_M 0x00030000 +#define IOC_IOCFG6_EDGE_DET_S 16 +#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG6_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG6_PULL_CTL_W 2 +#define IOC_IOCFG6_PULL_CTL_M 0x00006000 +#define IOC_IOCFG6_PULL_CTL_S 13 +#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG6_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG6_SLEW_RED 0x00001000 +#define IOC_IOCFG6_SLEW_RED_BITN 12 +#define IOC_IOCFG6_SLEW_RED_M 0x00001000 +#define IOC_IOCFG6_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG6_IOCURR_W 2 +#define IOC_IOCFG6_IOCURR_M 0x00000C00 +#define IOC_IOCFG6_IOCURR_S 10 +#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG6_IOCURR_4MA 0x00000400 +#define IOC_IOCFG6_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG6_IOSTR_W 2 +#define IOC_IOCFG6_IOSTR_M 0x00000300 +#define IOC_IOCFG6_IOSTR_S 8 +#define IOC_IOCFG6_IOSTR_MAX 0x00000300 +#define IOC_IOCFG6_IOSTR_MED 0x00000200 +#define IOC_IOCFG6_IOSTR_MIN 0x00000100 +#define IOC_IOCFG6_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG6_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG6_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG6_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG6_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG6_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG6_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG6_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG6_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO6 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG6_PORT_ID_W 6 +#define IOC_IOCFG6_PORT_ID_M 0x0000003F +#define IOC_IOCFG6_PORT_ID_S 0 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG6_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG6_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG6_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG6_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG7 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG7_HYST_EN 0x40000000 +#define IOC_IOCFG7_HYST_EN_BITN 30 +#define IOC_IOCFG7_HYST_EN_M 0x40000000 +#define IOC_IOCFG7_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG7_IE 0x20000000 +#define IOC_IOCFG7_IE_BITN 29 +#define IOC_IOCFG7_IE_M 0x20000000 +#define IOC_IOCFG7_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG7_WU_CFG_W 2 +#define IOC_IOCFG7_WU_CFG_M 0x18000000 +#define IOC_IOCFG7_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG7_IOMODE_W 3 +#define IOC_IOCFG7_IOMODE_M 0x07000000 +#define IOC_IOCFG7_IOMODE_S 24 +#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG7_IOMODE_INV 0x01000000 +#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG7_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG7_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG7_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG7_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG7_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG7_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG7_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG7_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG7_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG7_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG7_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG7_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG7_EDGE_DET_W 2 +#define IOC_IOCFG7_EDGE_DET_M 0x00030000 +#define IOC_IOCFG7_EDGE_DET_S 16 +#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG7_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG7_PULL_CTL_W 2 +#define IOC_IOCFG7_PULL_CTL_M 0x00006000 +#define IOC_IOCFG7_PULL_CTL_S 13 +#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG7_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG7_SLEW_RED 0x00001000 +#define IOC_IOCFG7_SLEW_RED_BITN 12 +#define IOC_IOCFG7_SLEW_RED_M 0x00001000 +#define IOC_IOCFG7_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG7_IOCURR_W 2 +#define IOC_IOCFG7_IOCURR_M 0x00000C00 +#define IOC_IOCFG7_IOCURR_S 10 +#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG7_IOCURR_4MA 0x00000400 +#define IOC_IOCFG7_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG7_IOSTR_W 2 +#define IOC_IOCFG7_IOSTR_M 0x00000300 +#define IOC_IOCFG7_IOSTR_S 8 +#define IOC_IOCFG7_IOSTR_MAX 0x00000300 +#define IOC_IOCFG7_IOSTR_MED 0x00000200 +#define IOC_IOCFG7_IOSTR_MIN 0x00000100 +#define IOC_IOCFG7_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG7_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG7_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG7_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG7_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG7_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG7_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG7_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG7_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO7 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG7_PORT_ID_W 6 +#define IOC_IOCFG7_PORT_ID_M 0x0000003F +#define IOC_IOCFG7_PORT_ID_S 0 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG7_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG7_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG7_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG7_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG8 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG8_HYST_EN 0x40000000 +#define IOC_IOCFG8_HYST_EN_BITN 30 +#define IOC_IOCFG8_HYST_EN_M 0x40000000 +#define IOC_IOCFG8_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG8_IE 0x20000000 +#define IOC_IOCFG8_IE_BITN 29 +#define IOC_IOCFG8_IE_M 0x20000000 +#define IOC_IOCFG8_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG8_WU_CFG_W 2 +#define IOC_IOCFG8_WU_CFG_M 0x18000000 +#define IOC_IOCFG8_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG8_IOMODE_W 3 +#define IOC_IOCFG8_IOMODE_M 0x07000000 +#define IOC_IOCFG8_IOMODE_S 24 +#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG8_IOMODE_INV 0x01000000 +#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG8_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG8_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG8_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG8_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG8_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG8_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG8_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG8_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG8_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG8_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG8_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG8_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG8_EDGE_DET_W 2 +#define IOC_IOCFG8_EDGE_DET_M 0x00030000 +#define IOC_IOCFG8_EDGE_DET_S 16 +#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG8_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG8_PULL_CTL_W 2 +#define IOC_IOCFG8_PULL_CTL_M 0x00006000 +#define IOC_IOCFG8_PULL_CTL_S 13 +#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG8_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG8_SLEW_RED 0x00001000 +#define IOC_IOCFG8_SLEW_RED_BITN 12 +#define IOC_IOCFG8_SLEW_RED_M 0x00001000 +#define IOC_IOCFG8_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG8_IOCURR_W 2 +#define IOC_IOCFG8_IOCURR_M 0x00000C00 +#define IOC_IOCFG8_IOCURR_S 10 +#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG8_IOCURR_4MA 0x00000400 +#define IOC_IOCFG8_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG8_IOSTR_W 2 +#define IOC_IOCFG8_IOSTR_M 0x00000300 +#define IOC_IOCFG8_IOSTR_S 8 +#define IOC_IOCFG8_IOSTR_MAX 0x00000300 +#define IOC_IOCFG8_IOSTR_MED 0x00000200 +#define IOC_IOCFG8_IOSTR_MIN 0x00000100 +#define IOC_IOCFG8_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG8_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG8_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG8_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG8_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG8_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG8_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG8_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG8_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO8 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG8_PORT_ID_W 6 +#define IOC_IOCFG8_PORT_ID_M 0x0000003F +#define IOC_IOCFG8_PORT_ID_S 0 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG8_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG8_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG8_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG8_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG9 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG9_HYST_EN 0x40000000 +#define IOC_IOCFG9_HYST_EN_BITN 30 +#define IOC_IOCFG9_HYST_EN_M 0x40000000 +#define IOC_IOCFG9_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG9_IE 0x20000000 +#define IOC_IOCFG9_IE_BITN 29 +#define IOC_IOCFG9_IE_M 0x20000000 +#define IOC_IOCFG9_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG9_WU_CFG_W 2 +#define IOC_IOCFG9_WU_CFG_M 0x18000000 +#define IOC_IOCFG9_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG9_IOMODE_W 3 +#define IOC_IOCFG9_IOMODE_M 0x07000000 +#define IOC_IOCFG9_IOMODE_S 24 +#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG9_IOMODE_INV 0x01000000 +#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG9_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG9_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG9_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG9_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG9_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG9_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG9_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG9_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG9_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG9_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG9_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG9_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG9_EDGE_DET_W 2 +#define IOC_IOCFG9_EDGE_DET_M 0x00030000 +#define IOC_IOCFG9_EDGE_DET_S 16 +#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG9_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG9_PULL_CTL_W 2 +#define IOC_IOCFG9_PULL_CTL_M 0x00006000 +#define IOC_IOCFG9_PULL_CTL_S 13 +#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG9_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG9_SLEW_RED 0x00001000 +#define IOC_IOCFG9_SLEW_RED_BITN 12 +#define IOC_IOCFG9_SLEW_RED_M 0x00001000 +#define IOC_IOCFG9_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG9_IOCURR_W 2 +#define IOC_IOCFG9_IOCURR_M 0x00000C00 +#define IOC_IOCFG9_IOCURR_S 10 +#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG9_IOCURR_4MA 0x00000400 +#define IOC_IOCFG9_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG9_IOSTR_W 2 +#define IOC_IOCFG9_IOSTR_M 0x00000300 +#define IOC_IOCFG9_IOSTR_S 8 +#define IOC_IOCFG9_IOSTR_MAX 0x00000300 +#define IOC_IOCFG9_IOSTR_MED 0x00000200 +#define IOC_IOCFG9_IOSTR_MIN 0x00000100 +#define IOC_IOCFG9_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG9_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG9_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG9_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG9_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG9_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG9_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG9_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG9_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO9 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG9_PORT_ID_W 6 +#define IOC_IOCFG9_PORT_ID_M 0x0000003F +#define IOC_IOCFG9_PORT_ID_S 0 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG9_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG9_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG9_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG9_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG10 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG10_HYST_EN 0x40000000 +#define IOC_IOCFG10_HYST_EN_BITN 30 +#define IOC_IOCFG10_HYST_EN_M 0x40000000 +#define IOC_IOCFG10_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG10_IE 0x20000000 +#define IOC_IOCFG10_IE_BITN 29 +#define IOC_IOCFG10_IE_M 0x20000000 +#define IOC_IOCFG10_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG10_WU_CFG_W 2 +#define IOC_IOCFG10_WU_CFG_M 0x18000000 +#define IOC_IOCFG10_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG10_IOMODE_W 3 +#define IOC_IOCFG10_IOMODE_M 0x07000000 +#define IOC_IOCFG10_IOMODE_S 24 +#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG10_IOMODE_INV 0x01000000 +#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG10_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG10_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG10_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG10_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG10_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG10_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG10_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG10_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG10_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG10_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG10_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG10_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG10_EDGE_DET_W 2 +#define IOC_IOCFG10_EDGE_DET_M 0x00030000 +#define IOC_IOCFG10_EDGE_DET_S 16 +#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG10_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG10_PULL_CTL_W 2 +#define IOC_IOCFG10_PULL_CTL_M 0x00006000 +#define IOC_IOCFG10_PULL_CTL_S 13 +#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG10_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG10_SLEW_RED 0x00001000 +#define IOC_IOCFG10_SLEW_RED_BITN 12 +#define IOC_IOCFG10_SLEW_RED_M 0x00001000 +#define IOC_IOCFG10_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG10_IOCURR_W 2 +#define IOC_IOCFG10_IOCURR_M 0x00000C00 +#define IOC_IOCFG10_IOCURR_S 10 +#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG10_IOCURR_4MA 0x00000400 +#define IOC_IOCFG10_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG10_IOSTR_W 2 +#define IOC_IOCFG10_IOSTR_M 0x00000300 +#define IOC_IOCFG10_IOSTR_S 8 +#define IOC_IOCFG10_IOSTR_MAX 0x00000300 +#define IOC_IOCFG10_IOSTR_MED 0x00000200 +#define IOC_IOCFG10_IOSTR_MIN 0x00000100 +#define IOC_IOCFG10_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG10_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG10_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG10_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG10_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG10_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG10_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG10_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG10_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO10 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG10_PORT_ID_W 6 +#define IOC_IOCFG10_PORT_ID_M 0x0000003F +#define IOC_IOCFG10_PORT_ID_S 0 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG10_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG10_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG10_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG10_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG11 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG11_HYST_EN 0x40000000 +#define IOC_IOCFG11_HYST_EN_BITN 30 +#define IOC_IOCFG11_HYST_EN_M 0x40000000 +#define IOC_IOCFG11_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG11_IE 0x20000000 +#define IOC_IOCFG11_IE_BITN 29 +#define IOC_IOCFG11_IE_M 0x20000000 +#define IOC_IOCFG11_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG11_WU_CFG_W 2 +#define IOC_IOCFG11_WU_CFG_M 0x18000000 +#define IOC_IOCFG11_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG11_IOMODE_W 3 +#define IOC_IOCFG11_IOMODE_M 0x07000000 +#define IOC_IOCFG11_IOMODE_S 24 +#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG11_IOMODE_INV 0x01000000 +#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG11_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG11_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG11_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG11_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG11_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG11_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG11_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG11_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG11_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG11_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG11_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG11_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG11_EDGE_DET_W 2 +#define IOC_IOCFG11_EDGE_DET_M 0x00030000 +#define IOC_IOCFG11_EDGE_DET_S 16 +#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG11_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG11_PULL_CTL_W 2 +#define IOC_IOCFG11_PULL_CTL_M 0x00006000 +#define IOC_IOCFG11_PULL_CTL_S 13 +#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG11_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG11_SLEW_RED 0x00001000 +#define IOC_IOCFG11_SLEW_RED_BITN 12 +#define IOC_IOCFG11_SLEW_RED_M 0x00001000 +#define IOC_IOCFG11_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG11_IOCURR_W 2 +#define IOC_IOCFG11_IOCURR_M 0x00000C00 +#define IOC_IOCFG11_IOCURR_S 10 +#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG11_IOCURR_4MA 0x00000400 +#define IOC_IOCFG11_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG11_IOSTR_W 2 +#define IOC_IOCFG11_IOSTR_M 0x00000300 +#define IOC_IOCFG11_IOSTR_S 8 +#define IOC_IOCFG11_IOSTR_MAX 0x00000300 +#define IOC_IOCFG11_IOSTR_MED 0x00000200 +#define IOC_IOCFG11_IOSTR_MIN 0x00000100 +#define IOC_IOCFG11_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG11_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG11_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG11_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG11_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG11_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG11_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG11_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG11_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO11 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG11_PORT_ID_W 6 +#define IOC_IOCFG11_PORT_ID_M 0x0000003F +#define IOC_IOCFG11_PORT_ID_S 0 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG11_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG11_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG11_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG11_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG12 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG12_HYST_EN 0x40000000 +#define IOC_IOCFG12_HYST_EN_BITN 30 +#define IOC_IOCFG12_HYST_EN_M 0x40000000 +#define IOC_IOCFG12_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG12_IE 0x20000000 +#define IOC_IOCFG12_IE_BITN 29 +#define IOC_IOCFG12_IE_M 0x20000000 +#define IOC_IOCFG12_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG12_WU_CFG_W 2 +#define IOC_IOCFG12_WU_CFG_M 0x18000000 +#define IOC_IOCFG12_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG12_IOMODE_W 3 +#define IOC_IOCFG12_IOMODE_M 0x07000000 +#define IOC_IOCFG12_IOMODE_S 24 +#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG12_IOMODE_INV 0x01000000 +#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG12_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG12_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG12_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG12_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG12_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG12_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG12_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG12_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG12_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG12_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG12_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG12_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG12_EDGE_DET_W 2 +#define IOC_IOCFG12_EDGE_DET_M 0x00030000 +#define IOC_IOCFG12_EDGE_DET_S 16 +#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG12_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG12_PULL_CTL_W 2 +#define IOC_IOCFG12_PULL_CTL_M 0x00006000 +#define IOC_IOCFG12_PULL_CTL_S 13 +#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG12_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG12_SLEW_RED 0x00001000 +#define IOC_IOCFG12_SLEW_RED_BITN 12 +#define IOC_IOCFG12_SLEW_RED_M 0x00001000 +#define IOC_IOCFG12_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG12_IOCURR_W 2 +#define IOC_IOCFG12_IOCURR_M 0x00000C00 +#define IOC_IOCFG12_IOCURR_S 10 +#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG12_IOCURR_4MA 0x00000400 +#define IOC_IOCFG12_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG12_IOSTR_W 2 +#define IOC_IOCFG12_IOSTR_M 0x00000300 +#define IOC_IOCFG12_IOSTR_S 8 +#define IOC_IOCFG12_IOSTR_MAX 0x00000300 +#define IOC_IOCFG12_IOSTR_MED 0x00000200 +#define IOC_IOCFG12_IOSTR_MIN 0x00000100 +#define IOC_IOCFG12_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG12_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG12_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG12_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG12_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG12_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG12_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG12_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG12_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO12 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG12_PORT_ID_W 6 +#define IOC_IOCFG12_PORT_ID_M 0x0000003F +#define IOC_IOCFG12_PORT_ID_S 0 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG12_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG12_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG12_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG12_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG13 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG13_HYST_EN 0x40000000 +#define IOC_IOCFG13_HYST_EN_BITN 30 +#define IOC_IOCFG13_HYST_EN_M 0x40000000 +#define IOC_IOCFG13_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG13_IE 0x20000000 +#define IOC_IOCFG13_IE_BITN 29 +#define IOC_IOCFG13_IE_M 0x20000000 +#define IOC_IOCFG13_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG13_WU_CFG_W 2 +#define IOC_IOCFG13_WU_CFG_M 0x18000000 +#define IOC_IOCFG13_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG13_IOMODE_W 3 +#define IOC_IOCFG13_IOMODE_M 0x07000000 +#define IOC_IOCFG13_IOMODE_S 24 +#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG13_IOMODE_INV 0x01000000 +#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG13_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG13_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG13_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG13_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG13_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG13_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG13_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG13_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG13_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG13_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG13_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG13_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG13_EDGE_DET_W 2 +#define IOC_IOCFG13_EDGE_DET_M 0x00030000 +#define IOC_IOCFG13_EDGE_DET_S 16 +#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG13_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG13_PULL_CTL_W 2 +#define IOC_IOCFG13_PULL_CTL_M 0x00006000 +#define IOC_IOCFG13_PULL_CTL_S 13 +#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG13_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG13_SLEW_RED 0x00001000 +#define IOC_IOCFG13_SLEW_RED_BITN 12 +#define IOC_IOCFG13_SLEW_RED_M 0x00001000 +#define IOC_IOCFG13_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG13_IOCURR_W 2 +#define IOC_IOCFG13_IOCURR_M 0x00000C00 +#define IOC_IOCFG13_IOCURR_S 10 +#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG13_IOCURR_4MA 0x00000400 +#define IOC_IOCFG13_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG13_IOSTR_W 2 +#define IOC_IOCFG13_IOSTR_M 0x00000300 +#define IOC_IOCFG13_IOSTR_S 8 +#define IOC_IOCFG13_IOSTR_MAX 0x00000300 +#define IOC_IOCFG13_IOSTR_MED 0x00000200 +#define IOC_IOCFG13_IOSTR_MIN 0x00000100 +#define IOC_IOCFG13_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG13_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG13_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG13_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG13_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG13_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG13_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG13_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG13_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO13 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG13_PORT_ID_W 6 +#define IOC_IOCFG13_PORT_ID_M 0x0000003F +#define IOC_IOCFG13_PORT_ID_S 0 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG13_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG13_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG13_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG13_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG14 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG14_HYST_EN 0x40000000 +#define IOC_IOCFG14_HYST_EN_BITN 30 +#define IOC_IOCFG14_HYST_EN_M 0x40000000 +#define IOC_IOCFG14_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG14_IE 0x20000000 +#define IOC_IOCFG14_IE_BITN 29 +#define IOC_IOCFG14_IE_M 0x20000000 +#define IOC_IOCFG14_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG14_WU_CFG_W 2 +#define IOC_IOCFG14_WU_CFG_M 0x18000000 +#define IOC_IOCFG14_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG14_IOMODE_W 3 +#define IOC_IOCFG14_IOMODE_M 0x07000000 +#define IOC_IOCFG14_IOMODE_S 24 +#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG14_IOMODE_INV 0x01000000 +#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG14_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG14_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG14_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG14_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG14_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG14_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG14_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG14_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG14_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG14_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG14_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG14_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG14_EDGE_DET_W 2 +#define IOC_IOCFG14_EDGE_DET_M 0x00030000 +#define IOC_IOCFG14_EDGE_DET_S 16 +#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG14_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG14_PULL_CTL_W 2 +#define IOC_IOCFG14_PULL_CTL_M 0x00006000 +#define IOC_IOCFG14_PULL_CTL_S 13 +#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG14_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG14_SLEW_RED 0x00001000 +#define IOC_IOCFG14_SLEW_RED_BITN 12 +#define IOC_IOCFG14_SLEW_RED_M 0x00001000 +#define IOC_IOCFG14_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG14_IOCURR_W 2 +#define IOC_IOCFG14_IOCURR_M 0x00000C00 +#define IOC_IOCFG14_IOCURR_S 10 +#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG14_IOCURR_4MA 0x00000400 +#define IOC_IOCFG14_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG14_IOSTR_W 2 +#define IOC_IOCFG14_IOSTR_M 0x00000300 +#define IOC_IOCFG14_IOSTR_S 8 +#define IOC_IOCFG14_IOSTR_MAX 0x00000300 +#define IOC_IOCFG14_IOSTR_MED 0x00000200 +#define IOC_IOCFG14_IOSTR_MIN 0x00000100 +#define IOC_IOCFG14_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG14_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG14_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG14_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG14_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG14_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG14_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG14_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG14_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO14 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG14_PORT_ID_W 6 +#define IOC_IOCFG14_PORT_ID_M 0x0000003F +#define IOC_IOCFG14_PORT_ID_S 0 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG14_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG14_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG14_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG14_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG15 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG15_HYST_EN 0x40000000 +#define IOC_IOCFG15_HYST_EN_BITN 30 +#define IOC_IOCFG15_HYST_EN_M 0x40000000 +#define IOC_IOCFG15_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG15_IE 0x20000000 +#define IOC_IOCFG15_IE_BITN 29 +#define IOC_IOCFG15_IE_M 0x20000000 +#define IOC_IOCFG15_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG15_WU_CFG_W 2 +#define IOC_IOCFG15_WU_CFG_M 0x18000000 +#define IOC_IOCFG15_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG15_IOMODE_W 3 +#define IOC_IOCFG15_IOMODE_M 0x07000000 +#define IOC_IOCFG15_IOMODE_S 24 +#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG15_IOMODE_INV 0x01000000 +#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG15_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG15_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG15_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG15_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG15_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG15_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG15_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG15_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG15_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG15_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG15_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG15_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG15_EDGE_DET_W 2 +#define IOC_IOCFG15_EDGE_DET_M 0x00030000 +#define IOC_IOCFG15_EDGE_DET_S 16 +#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG15_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG15_PULL_CTL_W 2 +#define IOC_IOCFG15_PULL_CTL_M 0x00006000 +#define IOC_IOCFG15_PULL_CTL_S 13 +#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG15_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG15_SLEW_RED 0x00001000 +#define IOC_IOCFG15_SLEW_RED_BITN 12 +#define IOC_IOCFG15_SLEW_RED_M 0x00001000 +#define IOC_IOCFG15_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG15_IOCURR_W 2 +#define IOC_IOCFG15_IOCURR_M 0x00000C00 +#define IOC_IOCFG15_IOCURR_S 10 +#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG15_IOCURR_4MA 0x00000400 +#define IOC_IOCFG15_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG15_IOSTR_W 2 +#define IOC_IOCFG15_IOSTR_M 0x00000300 +#define IOC_IOCFG15_IOSTR_S 8 +#define IOC_IOCFG15_IOSTR_MAX 0x00000300 +#define IOC_IOCFG15_IOSTR_MED 0x00000200 +#define IOC_IOCFG15_IOSTR_MIN 0x00000100 +#define IOC_IOCFG15_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG15_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG15_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG15_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG15_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG15_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG15_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG15_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG15_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO15 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG15_PORT_ID_W 6 +#define IOC_IOCFG15_PORT_ID_M 0x0000003F +#define IOC_IOCFG15_PORT_ID_S 0 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG15_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG15_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG15_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG15_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG16 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG16_HYST_EN 0x40000000 +#define IOC_IOCFG16_HYST_EN_BITN 30 +#define IOC_IOCFG16_HYST_EN_M 0x40000000 +#define IOC_IOCFG16_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG16_IE 0x20000000 +#define IOC_IOCFG16_IE_BITN 29 +#define IOC_IOCFG16_IE_M 0x20000000 +#define IOC_IOCFG16_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG16_WU_CFG_W 2 +#define IOC_IOCFG16_WU_CFG_M 0x18000000 +#define IOC_IOCFG16_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG16_IOMODE_W 3 +#define IOC_IOCFG16_IOMODE_M 0x07000000 +#define IOC_IOCFG16_IOMODE_S 24 +#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG16_IOMODE_INV 0x01000000 +#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG16_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG16_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG16_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG16_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG16_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG16_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG16_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG16_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG16_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG16_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG16_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG16_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG16_EDGE_DET_W 2 +#define IOC_IOCFG16_EDGE_DET_M 0x00030000 +#define IOC_IOCFG16_EDGE_DET_S 16 +#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG16_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG16_PULL_CTL_W 2 +#define IOC_IOCFG16_PULL_CTL_M 0x00006000 +#define IOC_IOCFG16_PULL_CTL_S 13 +#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG16_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG16_SLEW_RED 0x00001000 +#define IOC_IOCFG16_SLEW_RED_BITN 12 +#define IOC_IOCFG16_SLEW_RED_M 0x00001000 +#define IOC_IOCFG16_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG16_IOCURR_W 2 +#define IOC_IOCFG16_IOCURR_M 0x00000C00 +#define IOC_IOCFG16_IOCURR_S 10 +#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG16_IOCURR_4MA 0x00000400 +#define IOC_IOCFG16_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG16_IOSTR_W 2 +#define IOC_IOCFG16_IOSTR_M 0x00000300 +#define IOC_IOCFG16_IOSTR_S 8 +#define IOC_IOCFG16_IOSTR_MAX 0x00000300 +#define IOC_IOCFG16_IOSTR_MED 0x00000200 +#define IOC_IOCFG16_IOSTR_MIN 0x00000100 +#define IOC_IOCFG16_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG16_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG16_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG16_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG16_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG16_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG16_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG16_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG16_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO16 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG16_PORT_ID_W 6 +#define IOC_IOCFG16_PORT_ID_M 0x0000003F +#define IOC_IOCFG16_PORT_ID_S 0 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG16_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG16_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG16_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG16_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG17 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG17_HYST_EN 0x40000000 +#define IOC_IOCFG17_HYST_EN_BITN 30 +#define IOC_IOCFG17_HYST_EN_M 0x40000000 +#define IOC_IOCFG17_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG17_IE 0x20000000 +#define IOC_IOCFG17_IE_BITN 29 +#define IOC_IOCFG17_IE_M 0x20000000 +#define IOC_IOCFG17_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG17_WU_CFG_W 2 +#define IOC_IOCFG17_WU_CFG_M 0x18000000 +#define IOC_IOCFG17_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG17_IOMODE_W 3 +#define IOC_IOCFG17_IOMODE_M 0x07000000 +#define IOC_IOCFG17_IOMODE_S 24 +#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG17_IOMODE_INV 0x01000000 +#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG17_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG17_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG17_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG17_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG17_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG17_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG17_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG17_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG17_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG17_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG17_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG17_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG17_EDGE_DET_W 2 +#define IOC_IOCFG17_EDGE_DET_M 0x00030000 +#define IOC_IOCFG17_EDGE_DET_S 16 +#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG17_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG17_PULL_CTL_W 2 +#define IOC_IOCFG17_PULL_CTL_M 0x00006000 +#define IOC_IOCFG17_PULL_CTL_S 13 +#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG17_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG17_SLEW_RED 0x00001000 +#define IOC_IOCFG17_SLEW_RED_BITN 12 +#define IOC_IOCFG17_SLEW_RED_M 0x00001000 +#define IOC_IOCFG17_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG17_IOCURR_W 2 +#define IOC_IOCFG17_IOCURR_M 0x00000C00 +#define IOC_IOCFG17_IOCURR_S 10 +#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG17_IOCURR_4MA 0x00000400 +#define IOC_IOCFG17_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG17_IOSTR_W 2 +#define IOC_IOCFG17_IOSTR_M 0x00000300 +#define IOC_IOCFG17_IOSTR_S 8 +#define IOC_IOCFG17_IOSTR_MAX 0x00000300 +#define IOC_IOCFG17_IOSTR_MED 0x00000200 +#define IOC_IOCFG17_IOSTR_MIN 0x00000100 +#define IOC_IOCFG17_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG17_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG17_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG17_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG17_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG17_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG17_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG17_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG17_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO17 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG17_PORT_ID_W 6 +#define IOC_IOCFG17_PORT_ID_M 0x0000003F +#define IOC_IOCFG17_PORT_ID_S 0 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG17_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG17_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG17_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG17_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG18 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG18_HYST_EN 0x40000000 +#define IOC_IOCFG18_HYST_EN_BITN 30 +#define IOC_IOCFG18_HYST_EN_M 0x40000000 +#define IOC_IOCFG18_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG18_IE 0x20000000 +#define IOC_IOCFG18_IE_BITN 29 +#define IOC_IOCFG18_IE_M 0x20000000 +#define IOC_IOCFG18_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG18_WU_CFG_W 2 +#define IOC_IOCFG18_WU_CFG_M 0x18000000 +#define IOC_IOCFG18_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG18_IOMODE_W 3 +#define IOC_IOCFG18_IOMODE_M 0x07000000 +#define IOC_IOCFG18_IOMODE_S 24 +#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG18_IOMODE_INV 0x01000000 +#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG18_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG18_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG18_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG18_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG18_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG18_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG18_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG18_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG18_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG18_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG18_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG18_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG18_EDGE_DET_W 2 +#define IOC_IOCFG18_EDGE_DET_M 0x00030000 +#define IOC_IOCFG18_EDGE_DET_S 16 +#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG18_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG18_PULL_CTL_W 2 +#define IOC_IOCFG18_PULL_CTL_M 0x00006000 +#define IOC_IOCFG18_PULL_CTL_S 13 +#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG18_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG18_SLEW_RED 0x00001000 +#define IOC_IOCFG18_SLEW_RED_BITN 12 +#define IOC_IOCFG18_SLEW_RED_M 0x00001000 +#define IOC_IOCFG18_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG18_IOCURR_W 2 +#define IOC_IOCFG18_IOCURR_M 0x00000C00 +#define IOC_IOCFG18_IOCURR_S 10 +#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG18_IOCURR_4MA 0x00000400 +#define IOC_IOCFG18_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG18_IOSTR_W 2 +#define IOC_IOCFG18_IOSTR_M 0x00000300 +#define IOC_IOCFG18_IOSTR_S 8 +#define IOC_IOCFG18_IOSTR_MAX 0x00000300 +#define IOC_IOCFG18_IOSTR_MED 0x00000200 +#define IOC_IOCFG18_IOSTR_MIN 0x00000100 +#define IOC_IOCFG18_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG18_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG18_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG18_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG18_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG18_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG18_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG18_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG18_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO18 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG18_PORT_ID_W 6 +#define IOC_IOCFG18_PORT_ID_M 0x0000003F +#define IOC_IOCFG18_PORT_ID_S 0 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG18_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG18_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG18_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG18_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG19 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG19_HYST_EN 0x40000000 +#define IOC_IOCFG19_HYST_EN_BITN 30 +#define IOC_IOCFG19_HYST_EN_M 0x40000000 +#define IOC_IOCFG19_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG19_IE 0x20000000 +#define IOC_IOCFG19_IE_BITN 29 +#define IOC_IOCFG19_IE_M 0x20000000 +#define IOC_IOCFG19_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG19_WU_CFG_W 2 +#define IOC_IOCFG19_WU_CFG_M 0x18000000 +#define IOC_IOCFG19_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG19_IOMODE_W 3 +#define IOC_IOCFG19_IOMODE_M 0x07000000 +#define IOC_IOCFG19_IOMODE_S 24 +#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG19_IOMODE_INV 0x01000000 +#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG19_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG19_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG19_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG19_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG19_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG19_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG19_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG19_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG19_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG19_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG19_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG19_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG19_EDGE_DET_W 2 +#define IOC_IOCFG19_EDGE_DET_M 0x00030000 +#define IOC_IOCFG19_EDGE_DET_S 16 +#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG19_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG19_PULL_CTL_W 2 +#define IOC_IOCFG19_PULL_CTL_M 0x00006000 +#define IOC_IOCFG19_PULL_CTL_S 13 +#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG19_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG19_SLEW_RED 0x00001000 +#define IOC_IOCFG19_SLEW_RED_BITN 12 +#define IOC_IOCFG19_SLEW_RED_M 0x00001000 +#define IOC_IOCFG19_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG19_IOCURR_W 2 +#define IOC_IOCFG19_IOCURR_M 0x00000C00 +#define IOC_IOCFG19_IOCURR_S 10 +#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG19_IOCURR_4MA 0x00000400 +#define IOC_IOCFG19_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG19_IOSTR_W 2 +#define IOC_IOCFG19_IOSTR_M 0x00000300 +#define IOC_IOCFG19_IOSTR_S 8 +#define IOC_IOCFG19_IOSTR_MAX 0x00000300 +#define IOC_IOCFG19_IOSTR_MED 0x00000200 +#define IOC_IOCFG19_IOSTR_MIN 0x00000100 +#define IOC_IOCFG19_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG19_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG19_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG19_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG19_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG19_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG19_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG19_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG19_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO19 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG19_PORT_ID_W 6 +#define IOC_IOCFG19_PORT_ID_M 0x0000003F +#define IOC_IOCFG19_PORT_ID_S 0 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG19_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG19_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG19_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG19_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG20 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG20_HYST_EN 0x40000000 +#define IOC_IOCFG20_HYST_EN_BITN 30 +#define IOC_IOCFG20_HYST_EN_M 0x40000000 +#define IOC_IOCFG20_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG20_IE 0x20000000 +#define IOC_IOCFG20_IE_BITN 29 +#define IOC_IOCFG20_IE_M 0x20000000 +#define IOC_IOCFG20_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG20_WU_CFG_W 2 +#define IOC_IOCFG20_WU_CFG_M 0x18000000 +#define IOC_IOCFG20_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG20_IOMODE_W 3 +#define IOC_IOCFG20_IOMODE_M 0x07000000 +#define IOC_IOCFG20_IOMODE_S 24 +#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG20_IOMODE_INV 0x01000000 +#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG20_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG20_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG20_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG20_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG20_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG20_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG20_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG20_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG20_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG20_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG20_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG20_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG20_EDGE_DET_W 2 +#define IOC_IOCFG20_EDGE_DET_M 0x00030000 +#define IOC_IOCFG20_EDGE_DET_S 16 +#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG20_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG20_PULL_CTL_W 2 +#define IOC_IOCFG20_PULL_CTL_M 0x00006000 +#define IOC_IOCFG20_PULL_CTL_S 13 +#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG20_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG20_SLEW_RED 0x00001000 +#define IOC_IOCFG20_SLEW_RED_BITN 12 +#define IOC_IOCFG20_SLEW_RED_M 0x00001000 +#define IOC_IOCFG20_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG20_IOCURR_W 2 +#define IOC_IOCFG20_IOCURR_M 0x00000C00 +#define IOC_IOCFG20_IOCURR_S 10 +#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG20_IOCURR_4MA 0x00000400 +#define IOC_IOCFG20_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG20_IOSTR_W 2 +#define IOC_IOCFG20_IOSTR_M 0x00000300 +#define IOC_IOCFG20_IOSTR_S 8 +#define IOC_IOCFG20_IOSTR_MAX 0x00000300 +#define IOC_IOCFG20_IOSTR_MED 0x00000200 +#define IOC_IOCFG20_IOSTR_MIN 0x00000100 +#define IOC_IOCFG20_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG20_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG20_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG20_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG20_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG20_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG20_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG20_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG20_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO20 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG20_PORT_ID_W 6 +#define IOC_IOCFG20_PORT_ID_M 0x0000003F +#define IOC_IOCFG20_PORT_ID_S 0 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG20_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG20_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG20_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG20_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG21 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG21_HYST_EN 0x40000000 +#define IOC_IOCFG21_HYST_EN_BITN 30 +#define IOC_IOCFG21_HYST_EN_M 0x40000000 +#define IOC_IOCFG21_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG21_IE 0x20000000 +#define IOC_IOCFG21_IE_BITN 29 +#define IOC_IOCFG21_IE_M 0x20000000 +#define IOC_IOCFG21_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG21_WU_CFG_W 2 +#define IOC_IOCFG21_WU_CFG_M 0x18000000 +#define IOC_IOCFG21_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG21_IOMODE_W 3 +#define IOC_IOCFG21_IOMODE_M 0x07000000 +#define IOC_IOCFG21_IOMODE_S 24 +#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG21_IOMODE_INV 0x01000000 +#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG21_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG21_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG21_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG21_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG21_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG21_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG21_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG21_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG21_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG21_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG21_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG21_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG21_EDGE_DET_W 2 +#define IOC_IOCFG21_EDGE_DET_M 0x00030000 +#define IOC_IOCFG21_EDGE_DET_S 16 +#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG21_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG21_PULL_CTL_W 2 +#define IOC_IOCFG21_PULL_CTL_M 0x00006000 +#define IOC_IOCFG21_PULL_CTL_S 13 +#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG21_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG21_SLEW_RED 0x00001000 +#define IOC_IOCFG21_SLEW_RED_BITN 12 +#define IOC_IOCFG21_SLEW_RED_M 0x00001000 +#define IOC_IOCFG21_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG21_IOCURR_W 2 +#define IOC_IOCFG21_IOCURR_M 0x00000C00 +#define IOC_IOCFG21_IOCURR_S 10 +#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG21_IOCURR_4MA 0x00000400 +#define IOC_IOCFG21_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG21_IOSTR_W 2 +#define IOC_IOCFG21_IOSTR_M 0x00000300 +#define IOC_IOCFG21_IOSTR_S 8 +#define IOC_IOCFG21_IOSTR_MAX 0x00000300 +#define IOC_IOCFG21_IOSTR_MED 0x00000200 +#define IOC_IOCFG21_IOSTR_MIN 0x00000100 +#define IOC_IOCFG21_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG21_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG21_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG21_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG21_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG21_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG21_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG21_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG21_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO21 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG21_PORT_ID_W 6 +#define IOC_IOCFG21_PORT_ID_M 0x0000003F +#define IOC_IOCFG21_PORT_ID_S 0 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG21_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG21_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG21_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG21_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG22 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG22_HYST_EN 0x40000000 +#define IOC_IOCFG22_HYST_EN_BITN 30 +#define IOC_IOCFG22_HYST_EN_M 0x40000000 +#define IOC_IOCFG22_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG22_IE 0x20000000 +#define IOC_IOCFG22_IE_BITN 29 +#define IOC_IOCFG22_IE_M 0x20000000 +#define IOC_IOCFG22_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG22_WU_CFG_W 2 +#define IOC_IOCFG22_WU_CFG_M 0x18000000 +#define IOC_IOCFG22_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG22_IOMODE_W 3 +#define IOC_IOCFG22_IOMODE_M 0x07000000 +#define IOC_IOCFG22_IOMODE_S 24 +#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG22_IOMODE_INV 0x01000000 +#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG22_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG22_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG22_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG22_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG22_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG22_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG22_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG22_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG22_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG22_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG22_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG22_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG22_EDGE_DET_W 2 +#define IOC_IOCFG22_EDGE_DET_M 0x00030000 +#define IOC_IOCFG22_EDGE_DET_S 16 +#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG22_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG22_PULL_CTL_W 2 +#define IOC_IOCFG22_PULL_CTL_M 0x00006000 +#define IOC_IOCFG22_PULL_CTL_S 13 +#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG22_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG22_SLEW_RED 0x00001000 +#define IOC_IOCFG22_SLEW_RED_BITN 12 +#define IOC_IOCFG22_SLEW_RED_M 0x00001000 +#define IOC_IOCFG22_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG22_IOCURR_W 2 +#define IOC_IOCFG22_IOCURR_M 0x00000C00 +#define IOC_IOCFG22_IOCURR_S 10 +#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG22_IOCURR_4MA 0x00000400 +#define IOC_IOCFG22_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG22_IOSTR_W 2 +#define IOC_IOCFG22_IOSTR_M 0x00000300 +#define IOC_IOCFG22_IOSTR_S 8 +#define IOC_IOCFG22_IOSTR_MAX 0x00000300 +#define IOC_IOCFG22_IOSTR_MED 0x00000200 +#define IOC_IOCFG22_IOSTR_MIN 0x00000100 +#define IOC_IOCFG22_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG22_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG22_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG22_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG22_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG22_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG22_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG22_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG22_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO22 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG22_PORT_ID_W 6 +#define IOC_IOCFG22_PORT_ID_M 0x0000003F +#define IOC_IOCFG22_PORT_ID_S 0 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG22_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG22_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG22_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG22_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG23 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG23_HYST_EN 0x40000000 +#define IOC_IOCFG23_HYST_EN_BITN 30 +#define IOC_IOCFG23_HYST_EN_M 0x40000000 +#define IOC_IOCFG23_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG23_IE 0x20000000 +#define IOC_IOCFG23_IE_BITN 29 +#define IOC_IOCFG23_IE_M 0x20000000 +#define IOC_IOCFG23_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG23_WU_CFG_W 2 +#define IOC_IOCFG23_WU_CFG_M 0x18000000 +#define IOC_IOCFG23_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG23_IOMODE_W 3 +#define IOC_IOCFG23_IOMODE_M 0x07000000 +#define IOC_IOCFG23_IOMODE_S 24 +#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG23_IOMODE_INV 0x01000000 +#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG23_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG23_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG23_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG23_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG23_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG23_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG23_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG23_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG23_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG23_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG23_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG23_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG23_EDGE_DET_W 2 +#define IOC_IOCFG23_EDGE_DET_M 0x00030000 +#define IOC_IOCFG23_EDGE_DET_S 16 +#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG23_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG23_PULL_CTL_W 2 +#define IOC_IOCFG23_PULL_CTL_M 0x00006000 +#define IOC_IOCFG23_PULL_CTL_S 13 +#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG23_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG23_SLEW_RED 0x00001000 +#define IOC_IOCFG23_SLEW_RED_BITN 12 +#define IOC_IOCFG23_SLEW_RED_M 0x00001000 +#define IOC_IOCFG23_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG23_IOCURR_W 2 +#define IOC_IOCFG23_IOCURR_M 0x00000C00 +#define IOC_IOCFG23_IOCURR_S 10 +#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG23_IOCURR_4MA 0x00000400 +#define IOC_IOCFG23_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG23_IOSTR_W 2 +#define IOC_IOCFG23_IOSTR_M 0x00000300 +#define IOC_IOCFG23_IOSTR_S 8 +#define IOC_IOCFG23_IOSTR_MAX 0x00000300 +#define IOC_IOCFG23_IOSTR_MED 0x00000200 +#define IOC_IOCFG23_IOSTR_MIN 0x00000100 +#define IOC_IOCFG23_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG23_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG23_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG23_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG23_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG23_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG23_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG23_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG23_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO23 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG23_PORT_ID_W 6 +#define IOC_IOCFG23_PORT_ID_M 0x0000003F +#define IOC_IOCFG23_PORT_ID_S 0 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG23_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG23_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG23_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG23_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG24 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG24_HYST_EN 0x40000000 +#define IOC_IOCFG24_HYST_EN_BITN 30 +#define IOC_IOCFG24_HYST_EN_M 0x40000000 +#define IOC_IOCFG24_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG24_IE 0x20000000 +#define IOC_IOCFG24_IE_BITN 29 +#define IOC_IOCFG24_IE_M 0x20000000 +#define IOC_IOCFG24_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG24_WU_CFG_W 2 +#define IOC_IOCFG24_WU_CFG_M 0x18000000 +#define IOC_IOCFG24_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG24_IOMODE_W 3 +#define IOC_IOCFG24_IOMODE_M 0x07000000 +#define IOC_IOCFG24_IOMODE_S 24 +#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG24_IOMODE_INV 0x01000000 +#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG24_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG24_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG24_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG24_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG24_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG24_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG24_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG24_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG24_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG24_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG24_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG24_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG24_EDGE_DET_W 2 +#define IOC_IOCFG24_EDGE_DET_M 0x00030000 +#define IOC_IOCFG24_EDGE_DET_S 16 +#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG24_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG24_PULL_CTL_W 2 +#define IOC_IOCFG24_PULL_CTL_M 0x00006000 +#define IOC_IOCFG24_PULL_CTL_S 13 +#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG24_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG24_SLEW_RED 0x00001000 +#define IOC_IOCFG24_SLEW_RED_BITN 12 +#define IOC_IOCFG24_SLEW_RED_M 0x00001000 +#define IOC_IOCFG24_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG24_IOCURR_W 2 +#define IOC_IOCFG24_IOCURR_M 0x00000C00 +#define IOC_IOCFG24_IOCURR_S 10 +#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG24_IOCURR_4MA 0x00000400 +#define IOC_IOCFG24_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG24_IOSTR_W 2 +#define IOC_IOCFG24_IOSTR_M 0x00000300 +#define IOC_IOCFG24_IOSTR_S 8 +#define IOC_IOCFG24_IOSTR_MAX 0x00000300 +#define IOC_IOCFG24_IOSTR_MED 0x00000200 +#define IOC_IOCFG24_IOSTR_MIN 0x00000100 +#define IOC_IOCFG24_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG24_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG24_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG24_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG24_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG24_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG24_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG24_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG24_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO24 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG24_PORT_ID_W 6 +#define IOC_IOCFG24_PORT_ID_M 0x0000003F +#define IOC_IOCFG24_PORT_ID_S 0 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG24_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG24_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG24_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG24_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG25 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG25_HYST_EN 0x40000000 +#define IOC_IOCFG25_HYST_EN_BITN 30 +#define IOC_IOCFG25_HYST_EN_M 0x40000000 +#define IOC_IOCFG25_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG25_IE 0x20000000 +#define IOC_IOCFG25_IE_BITN 29 +#define IOC_IOCFG25_IE_M 0x20000000 +#define IOC_IOCFG25_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG25_WU_CFG_W 2 +#define IOC_IOCFG25_WU_CFG_M 0x18000000 +#define IOC_IOCFG25_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG25_IOMODE_W 3 +#define IOC_IOCFG25_IOMODE_M 0x07000000 +#define IOC_IOCFG25_IOMODE_S 24 +#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG25_IOMODE_INV 0x01000000 +#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG25_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG25_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG25_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG25_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG25_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG25_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG25_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG25_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG25_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG25_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG25_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG25_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG25_EDGE_DET_W 2 +#define IOC_IOCFG25_EDGE_DET_M 0x00030000 +#define IOC_IOCFG25_EDGE_DET_S 16 +#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG25_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG25_PULL_CTL_W 2 +#define IOC_IOCFG25_PULL_CTL_M 0x00006000 +#define IOC_IOCFG25_PULL_CTL_S 13 +#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG25_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG25_SLEW_RED 0x00001000 +#define IOC_IOCFG25_SLEW_RED_BITN 12 +#define IOC_IOCFG25_SLEW_RED_M 0x00001000 +#define IOC_IOCFG25_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG25_IOCURR_W 2 +#define IOC_IOCFG25_IOCURR_M 0x00000C00 +#define IOC_IOCFG25_IOCURR_S 10 +#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG25_IOCURR_4MA 0x00000400 +#define IOC_IOCFG25_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG25_IOSTR_W 2 +#define IOC_IOCFG25_IOSTR_M 0x00000300 +#define IOC_IOCFG25_IOSTR_S 8 +#define IOC_IOCFG25_IOSTR_MAX 0x00000300 +#define IOC_IOCFG25_IOSTR_MED 0x00000200 +#define IOC_IOCFG25_IOSTR_MIN 0x00000100 +#define IOC_IOCFG25_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG25_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG25_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG25_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG25_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG25_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG25_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG25_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG25_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO25 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG25_PORT_ID_W 6 +#define IOC_IOCFG25_PORT_ID_M 0x0000003F +#define IOC_IOCFG25_PORT_ID_S 0 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG25_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG25_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG25_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG25_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG26 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG26_HYST_EN 0x40000000 +#define IOC_IOCFG26_HYST_EN_BITN 30 +#define IOC_IOCFG26_HYST_EN_M 0x40000000 +#define IOC_IOCFG26_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG26_IE 0x20000000 +#define IOC_IOCFG26_IE_BITN 29 +#define IOC_IOCFG26_IE_M 0x20000000 +#define IOC_IOCFG26_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG26_WU_CFG_W 2 +#define IOC_IOCFG26_WU_CFG_M 0x18000000 +#define IOC_IOCFG26_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG26_IOMODE_W 3 +#define IOC_IOCFG26_IOMODE_M 0x07000000 +#define IOC_IOCFG26_IOMODE_S 24 +#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG26_IOMODE_INV 0x01000000 +#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG26_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG26_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG26_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG26_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG26_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG26_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG26_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG26_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG26_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG26_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG26_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG26_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG26_EDGE_DET_W 2 +#define IOC_IOCFG26_EDGE_DET_M 0x00030000 +#define IOC_IOCFG26_EDGE_DET_S 16 +#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG26_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG26_PULL_CTL_W 2 +#define IOC_IOCFG26_PULL_CTL_M 0x00006000 +#define IOC_IOCFG26_PULL_CTL_S 13 +#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG26_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG26_SLEW_RED 0x00001000 +#define IOC_IOCFG26_SLEW_RED_BITN 12 +#define IOC_IOCFG26_SLEW_RED_M 0x00001000 +#define IOC_IOCFG26_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG26_IOCURR_W 2 +#define IOC_IOCFG26_IOCURR_M 0x00000C00 +#define IOC_IOCFG26_IOCURR_S 10 +#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG26_IOCURR_4MA 0x00000400 +#define IOC_IOCFG26_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG26_IOSTR_W 2 +#define IOC_IOCFG26_IOSTR_M 0x00000300 +#define IOC_IOCFG26_IOSTR_S 8 +#define IOC_IOCFG26_IOSTR_MAX 0x00000300 +#define IOC_IOCFG26_IOSTR_MED 0x00000200 +#define IOC_IOCFG26_IOSTR_MIN 0x00000100 +#define IOC_IOCFG26_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG26_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG26_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG26_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG26_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG26_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG26_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG26_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG26_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO26 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG26_PORT_ID_W 6 +#define IOC_IOCFG26_PORT_ID_M 0x0000003F +#define IOC_IOCFG26_PORT_ID_S 0 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG26_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG26_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG26_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG26_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG27 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG27_HYST_EN 0x40000000 +#define IOC_IOCFG27_HYST_EN_BITN 30 +#define IOC_IOCFG27_HYST_EN_M 0x40000000 +#define IOC_IOCFG27_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG27_IE 0x20000000 +#define IOC_IOCFG27_IE_BITN 29 +#define IOC_IOCFG27_IE_M 0x20000000 +#define IOC_IOCFG27_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG27_WU_CFG_W 2 +#define IOC_IOCFG27_WU_CFG_M 0x18000000 +#define IOC_IOCFG27_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG27_IOMODE_W 3 +#define IOC_IOCFG27_IOMODE_M 0x07000000 +#define IOC_IOCFG27_IOMODE_S 24 +#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG27_IOMODE_INV 0x01000000 +#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG27_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG27_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG27_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG27_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG27_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG27_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG27_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG27_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG27_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG27_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG27_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG27_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG27_EDGE_DET_W 2 +#define IOC_IOCFG27_EDGE_DET_M 0x00030000 +#define IOC_IOCFG27_EDGE_DET_S 16 +#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG27_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG27_PULL_CTL_W 2 +#define IOC_IOCFG27_PULL_CTL_M 0x00006000 +#define IOC_IOCFG27_PULL_CTL_S 13 +#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG27_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG27_SLEW_RED 0x00001000 +#define IOC_IOCFG27_SLEW_RED_BITN 12 +#define IOC_IOCFG27_SLEW_RED_M 0x00001000 +#define IOC_IOCFG27_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG27_IOCURR_W 2 +#define IOC_IOCFG27_IOCURR_M 0x00000C00 +#define IOC_IOCFG27_IOCURR_S 10 +#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG27_IOCURR_4MA 0x00000400 +#define IOC_IOCFG27_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG27_IOSTR_W 2 +#define IOC_IOCFG27_IOSTR_M 0x00000300 +#define IOC_IOCFG27_IOSTR_S 8 +#define IOC_IOCFG27_IOSTR_MAX 0x00000300 +#define IOC_IOCFG27_IOSTR_MED 0x00000200 +#define IOC_IOCFG27_IOSTR_MIN 0x00000100 +#define IOC_IOCFG27_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG27_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG27_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG27_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG27_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG27_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG27_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG27_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG27_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO27 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG27_PORT_ID_W 6 +#define IOC_IOCFG27_PORT_ID_M 0x0000003F +#define IOC_IOCFG27_PORT_ID_S 0 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG27_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG27_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG27_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG27_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG28 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG28_HYST_EN 0x40000000 +#define IOC_IOCFG28_HYST_EN_BITN 30 +#define IOC_IOCFG28_HYST_EN_M 0x40000000 +#define IOC_IOCFG28_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG28_IE 0x20000000 +#define IOC_IOCFG28_IE_BITN 29 +#define IOC_IOCFG28_IE_M 0x20000000 +#define IOC_IOCFG28_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG28_WU_CFG_W 2 +#define IOC_IOCFG28_WU_CFG_M 0x18000000 +#define IOC_IOCFG28_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG28_IOMODE_W 3 +#define IOC_IOCFG28_IOMODE_M 0x07000000 +#define IOC_IOCFG28_IOMODE_S 24 +#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG28_IOMODE_INV 0x01000000 +#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG28_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG28_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG28_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG28_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG28_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG28_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG28_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG28_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG28_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG28_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG28_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG28_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG28_EDGE_DET_W 2 +#define IOC_IOCFG28_EDGE_DET_M 0x00030000 +#define IOC_IOCFG28_EDGE_DET_S 16 +#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG28_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG28_PULL_CTL_W 2 +#define IOC_IOCFG28_PULL_CTL_M 0x00006000 +#define IOC_IOCFG28_PULL_CTL_S 13 +#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG28_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG28_SLEW_RED 0x00001000 +#define IOC_IOCFG28_SLEW_RED_BITN 12 +#define IOC_IOCFG28_SLEW_RED_M 0x00001000 +#define IOC_IOCFG28_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG28_IOCURR_W 2 +#define IOC_IOCFG28_IOCURR_M 0x00000C00 +#define IOC_IOCFG28_IOCURR_S 10 +#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG28_IOCURR_4MA 0x00000400 +#define IOC_IOCFG28_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG28_IOSTR_W 2 +#define IOC_IOCFG28_IOSTR_M 0x00000300 +#define IOC_IOCFG28_IOSTR_S 8 +#define IOC_IOCFG28_IOSTR_MAX 0x00000300 +#define IOC_IOCFG28_IOSTR_MED 0x00000200 +#define IOC_IOCFG28_IOSTR_MIN 0x00000100 +#define IOC_IOCFG28_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG28_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG28_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG28_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG28_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG28_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG28_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG28_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG28_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO28 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG28_PORT_ID_W 6 +#define IOC_IOCFG28_PORT_ID_M 0x0000003F +#define IOC_IOCFG28_PORT_ID_S 0 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG28_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG28_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG28_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG28_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG29 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG29_HYST_EN 0x40000000 +#define IOC_IOCFG29_HYST_EN_BITN 30 +#define IOC_IOCFG29_HYST_EN_M 0x40000000 +#define IOC_IOCFG29_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG29_IE 0x20000000 +#define IOC_IOCFG29_IE_BITN 29 +#define IOC_IOCFG29_IE_M 0x20000000 +#define IOC_IOCFG29_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG29_WU_CFG_W 2 +#define IOC_IOCFG29_WU_CFG_M 0x18000000 +#define IOC_IOCFG29_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG29_IOMODE_W 3 +#define IOC_IOCFG29_IOMODE_M 0x07000000 +#define IOC_IOCFG29_IOMODE_S 24 +#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG29_IOMODE_INV 0x01000000 +#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG29_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG29_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG29_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG29_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG29_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG29_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG29_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG29_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG29_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG29_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG29_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG29_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG29_EDGE_DET_W 2 +#define IOC_IOCFG29_EDGE_DET_M 0x00030000 +#define IOC_IOCFG29_EDGE_DET_S 16 +#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG29_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG29_PULL_CTL_W 2 +#define IOC_IOCFG29_PULL_CTL_M 0x00006000 +#define IOC_IOCFG29_PULL_CTL_S 13 +#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG29_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG29_SLEW_RED 0x00001000 +#define IOC_IOCFG29_SLEW_RED_BITN 12 +#define IOC_IOCFG29_SLEW_RED_M 0x00001000 +#define IOC_IOCFG29_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG29_IOCURR_W 2 +#define IOC_IOCFG29_IOCURR_M 0x00000C00 +#define IOC_IOCFG29_IOCURR_S 10 +#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG29_IOCURR_4MA 0x00000400 +#define IOC_IOCFG29_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG29_IOSTR_W 2 +#define IOC_IOCFG29_IOSTR_M 0x00000300 +#define IOC_IOCFG29_IOSTR_S 8 +#define IOC_IOCFG29_IOSTR_MAX 0x00000300 +#define IOC_IOCFG29_IOSTR_MED 0x00000200 +#define IOC_IOCFG29_IOSTR_MIN 0x00000100 +#define IOC_IOCFG29_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG29_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG29_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG29_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG29_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG29_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG29_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG29_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG29_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO29 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG29_PORT_ID_W 6 +#define IOC_IOCFG29_PORT_ID_M 0x0000003F +#define IOC_IOCFG29_PORT_ID_S 0 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG29_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG29_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG29_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG29_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG30 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG30_HYST_EN 0x40000000 +#define IOC_IOCFG30_HYST_EN_BITN 30 +#define IOC_IOCFG30_HYST_EN_M 0x40000000 +#define IOC_IOCFG30_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG30_IE 0x20000000 +#define IOC_IOCFG30_IE_BITN 29 +#define IOC_IOCFG30_IE_M 0x20000000 +#define IOC_IOCFG30_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG30_WU_CFG_W 2 +#define IOC_IOCFG30_WU_CFG_M 0x18000000 +#define IOC_IOCFG30_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG30_IOMODE_W 3 +#define IOC_IOCFG30_IOMODE_M 0x07000000 +#define IOC_IOCFG30_IOMODE_S 24 +#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG30_IOMODE_INV 0x01000000 +#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG30_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG30_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG30_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG30_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG30_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG30_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG30_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG30_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG30_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG30_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG30_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG30_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG30_EDGE_DET_W 2 +#define IOC_IOCFG30_EDGE_DET_M 0x00030000 +#define IOC_IOCFG30_EDGE_DET_S 16 +#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG30_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG30_PULL_CTL_W 2 +#define IOC_IOCFG30_PULL_CTL_M 0x00006000 +#define IOC_IOCFG30_PULL_CTL_S 13 +#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG30_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG30_SLEW_RED 0x00001000 +#define IOC_IOCFG30_SLEW_RED_BITN 12 +#define IOC_IOCFG30_SLEW_RED_M 0x00001000 +#define IOC_IOCFG30_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG30_IOCURR_W 2 +#define IOC_IOCFG30_IOCURR_M 0x00000C00 +#define IOC_IOCFG30_IOCURR_S 10 +#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG30_IOCURR_4MA 0x00000400 +#define IOC_IOCFG30_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG30_IOSTR_W 2 +#define IOC_IOCFG30_IOSTR_M 0x00000300 +#define IOC_IOCFG30_IOSTR_S 8 +#define IOC_IOCFG30_IOSTR_MAX 0x00000300 +#define IOC_IOCFG30_IOSTR_MED 0x00000200 +#define IOC_IOCFG30_IOSTR_MIN 0x00000100 +#define IOC_IOCFG30_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG30_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG30_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG30_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG30_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG30_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG30_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG30_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG30_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO30 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG30_PORT_ID_W 6 +#define IOC_IOCFG30_PORT_ID_M 0x0000003F +#define IOC_IOCFG30_PORT_ID_S 0 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG30_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG30_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG30_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG30_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG31 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG31_HYST_EN 0x40000000 +#define IOC_IOCFG31_HYST_EN_BITN 30 +#define IOC_IOCFG31_HYST_EN_M 0x40000000 +#define IOC_IOCFG31_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG31_IE 0x20000000 +#define IOC_IOCFG31_IE_BITN 29 +#define IOC_IOCFG31_IE_M 0x20000000 +#define IOC_IOCFG31_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG31_WU_CFG_W 2 +#define IOC_IOCFG31_WU_CFG_M 0x18000000 +#define IOC_IOCFG31_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG31_IOMODE_W 3 +#define IOC_IOCFG31_IOMODE_M 0x07000000 +#define IOC_IOCFG31_IOMODE_S 24 +#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG31_IOMODE_INV 0x01000000 +#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG31_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG31_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG31_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG31_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG31_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG31_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG31_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG31_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG31_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG31_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG31_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG31_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG31_EDGE_DET_W 2 +#define IOC_IOCFG31_EDGE_DET_M 0x00030000 +#define IOC_IOCFG31_EDGE_DET_S 16 +#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG31_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG31_PULL_CTL_W 2 +#define IOC_IOCFG31_PULL_CTL_M 0x00006000 +#define IOC_IOCFG31_PULL_CTL_S 13 +#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG31_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG31_SLEW_RED 0x00001000 +#define IOC_IOCFG31_SLEW_RED_BITN 12 +#define IOC_IOCFG31_SLEW_RED_M 0x00001000 +#define IOC_IOCFG31_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG31_IOCURR_W 2 +#define IOC_IOCFG31_IOCURR_M 0x00000C00 +#define IOC_IOCFG31_IOCURR_S 10 +#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG31_IOCURR_4MA 0x00000400 +#define IOC_IOCFG31_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG31_IOSTR_W 2 +#define IOC_IOCFG31_IOSTR_M 0x00000300 +#define IOC_IOCFG31_IOSTR_S 8 +#define IOC_IOCFG31_IOSTR_MAX 0x00000300 +#define IOC_IOCFG31_IOSTR_MED 0x00000200 +#define IOC_IOCFG31_IOSTR_MIN 0x00000100 +#define IOC_IOCFG31_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG31_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG31_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG31_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG31_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG31_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG31_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG31_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG31_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO31 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG31_PORT_ID_W 6 +#define IOC_IOCFG31_PORT_ID_M 0x0000003F +#define IOC_IOCFG31_PORT_ID_S 0 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG31_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG31_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG31_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG31_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 + + +#endif // __IOC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h new file mode 100644 index 0000000..07d07f6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h @@ -0,0 +1,180 @@ +/****************************************************************************** +* Filename: hw_memmap_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals on the CPU_MMAP interface +// +//***************************************************************************** +#define FLASHMEM_BASE 0x00000000 // FLASHMEM +#define BROM_BASE 0x10000000 // BROM +#define GPRAM_BASE 0x11000000 // GPRAM +#define SRAM_BASE 0x20000000 // SRAM +#define RFC_RAM_BASE 0x21000000 // RFC_RAM +#define RFC_ULLRAM_BASE 0x21004000 // RFC_ULLRAM +#define SSI0_BASE 0x40000000 // SSI +#define UART0_BASE 0x40001000 // UART +#define I2C0_BASE 0x40002000 // I2C +#define SSI1_BASE 0x40008000 // SSI +#define UART1_BASE 0x4000B000 // UART +#define GPT0_BASE 0x40010000 // GPT +#define GPT1_BASE 0x40011000 // GPT +#define GPT2_BASE 0x40012000 // GPT +#define GPT3_BASE 0x40013000 // GPT +#define UDMA0_BASE 0x40020000 // UDMA +#define I2S0_BASE 0x40021000 // I2S +#define GPIO_BASE 0x40022000 // GPIO +#define CRYPTO_BASE 0x40024000 // CRYPTO +#define PKA_BASE 0x40025000 // PKA +#define PKA_RAM_BASE 0x40026000 // PKA_RAM +#define PKA_INT_BASE 0x40027000 // PKA_INT +#define TRNG_BASE 0x40028000 // TRNG +#define FLASH_BASE 0x40030000 // FLASH +#define VIMS_BASE 0x40034000 // VIMS +#define SRAM_MMR_BASE 0x40035000 // SRAM_MMR +#define RFC_PWR_BASE 0x40040000 // RFC_PWR +#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL +#define RFC_RAT_BASE 0x40043000 // RFC_RAT +#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA +#define WDT_BASE 0x40080000 // WDT +#define IOC_BASE 0x40081000 // IOC +#define PRCM_BASE 0x40082000 // PRCM +#define EVENT_BASE 0x40083000 // EVENT +#define SMPH_BASE 0x40084000 // SMPH +#define ADI2_BASE 0x40086000 // ADI +#define ADI3_BASE 0x40086200 // ADI +#define AON_PMCTL_BASE 0x40090000 // AON_PMCTL +#define AON_RTC_BASE 0x40092000 // AON_RTC +#define AON_EVENT_BASE 0x40093000 // AON_EVENT +#define AON_IOC_BASE 0x40094000 // AON_IOC +#define AON_BATMON_BASE 0x40095000 // AON_BATMON +#define AUX_SPIM_BASE 0x400C1000 // AUX_SPIM +#define AUX_MAC_BASE 0x400C2000 // AUX_MAC +#define AUX_TIMER2_BASE 0x400C3000 // AUX_TIMER2 +#define AUX_TDC_BASE 0x400C4000 // AUX_TDC +#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL +#define AUX_SYSIF_BASE 0x400C6000 // AUX_SYSIF +#define AUX_TIMER01_BASE 0x400C7000 // AUX_TIMER01 +#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH +#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF +#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI +#define AUX_ADI4_BASE 0x400CB000 // ADI +#define AUX_AIODIO0_BASE 0x400CC000 // AUX_AIODIO +#define AUX_AIODIO1_BASE 0x400CD000 // AUX_AIODIO +#define AUX_AIODIO2_BASE 0x400CE000 // AUX_AIODIO +#define AUX_AIODIO3_BASE 0x400CF000 // AUX_AIODIO +#define AUX_RAM_BASE 0x400E0000 // AUX_RAM +#define AUX_SCE_BASE 0x400E1000 // AUX_SCE +#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP +#define FCFG1_BASE 0x50001000 // FCFG1 +#define FCFG2_BASE 0x50002000 // FCFG2 +#ifndef CCFG_BASE +#define CCFG_BASE 0x50003000 // CCFG +#endif +#define CCFG_BASE_DEFAULT 0x50003000 // CCFG +#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base +#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base +#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base +#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base +#define UART1_NONBUF_BASE 0x6000B000 // UART CPU nonbuf base +#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base +#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base +#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base +#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base +#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base +#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base +#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base +#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base +#define PKA_NONBUF_BASE 0x60025000 // PKA CPU nonbuf base +#define PKA_RAM_NONBUF_BASE 0x60026000 // PKA_RAM CPU nonbuf base +#define PKA_INT_NONBUF_BASE 0x60027000 // PKA_INT CPU nonbuf base +#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base +#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base +#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base +#define SRAM_MMR_NONBUF_BASE 0x60035000 // SRAM_MMR CPU nonbuf base +#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base +#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base +#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base +#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base +#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base +#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base +#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base +#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base +#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base +#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base +#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base +#define AON_PMCTL_NONBUF_BASE 0x60090000 // AON_PMCTL CPU nonbuf base +#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base +#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base +#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base +#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base +#define AUX_SPIM_NONBUF_BASE 0x600C1000 // AUX_SPIM CPU nonbuf base +#define AUX_MAC_NONBUF_BASE 0x600C2000 // AUX_MAC CPU nonbuf base +#define AUX_TIMER2_NONBUF_BASE 0x600C3000 // AUX_TIMER2 CPU nonbuf base +#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base +#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base +#define AUX_SYSIF_NONBUF_BASE 0x600C6000 // AUX_SYSIF CPU nonbuf base +#define AUX_TIMER01_NONBUF_BASE \ + 0x600C7000 // AUX_TIMER01 CPU nonbuf base +#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base +#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base +#define AUX_DDI0_OSC_NONBUF_BASE \ + 0x600CA000 // DDI CPU nonbuf base +#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base +#define AUX_AIODIO0_NONBUF_BASE \ + 0x600CC000 // AUX_AIODIO CPU nonbuf base +#define AUX_AIODIO1_NONBUF_BASE \ + 0x600CD000 // AUX_AIODIO CPU nonbuf base +#define AUX_AIODIO2_NONBUF_BASE \ + 0x600CE000 // AUX_AIODIO CPU nonbuf base +#define AUX_AIODIO3_NONBUF_BASE \ + 0x600CF000 // AUX_AIODIO CPU nonbuf base +#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base +#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base +#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base +#define CPU_ITM_BASE 0xE0000000 // CPU_ITM +#define CPU_DWT_BASE 0xE0001000 // CPU_DWT +#define CPU_FPB_BASE 0xE0002000 // CPU_FPB +#define CPU_SCS_BASE 0xE000E000 // CPU_SCS +#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU +#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP +#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE + +#endif // __HW_MEMMAP__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_nvic.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_nvic.h new file mode 100644 index 0000000..3bdeb8b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_nvic.h @@ -0,0 +1,1026 @@ +/****************************************************************************** +* Filename: hw_nvic.h +* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) +* Revision: 42365 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number +#undef NVIC_INT_CTRL_VEC_PEN_M +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number +#undef NVIC_INT_CTRL_VEC_ACT_M +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset +#undef NVIC_VTABLE_OFFSET_M +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 9 +#undef NVIC_VTABLE_OFFSET_S +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka.h new file mode 100644 index 0000000..ffe4e40 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka.h @@ -0,0 +1,606 @@ +/****************************************************************************** +* Filename: hw_pka_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_PKA_H__ +#define __HW_PKA_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// PKA component +// +//***************************************************************************** +// PKA Vector A Address +#define PKA_O_APTR 0x00000000 + +// PKA Vector B Address +#define PKA_O_BPTR 0x00000004 + +// PKA Vector C Address +#define PKA_O_CPTR 0x00000008 + +// PKA Vector D Address +#define PKA_O_DPTR 0x0000000C + +// PKA Vector A Length +#define PKA_O_ALENGTH 0x00000010 + +// PKA Vector B Length +#define PKA_O_BLENGTH 0x00000014 + +// PKA Bit Shift Value +#define PKA_O_SHIFT 0x00000018 + +// PKA Function +#define PKA_O_FUNCTION 0x0000001C + +// PKA compare result +#define PKA_O_COMPARE 0x00000020 + +// PKA most-significant-word of result vector +#define PKA_O_MSW 0x00000024 + +// PKA most-significant-word of divide remainder +#define PKA_O_DIVMSW 0x00000028 + +// PKA sequencer control and status register +#define PKA_O_SEQCTRL 0x000000C8 + +// PKA hardware options register +#define PKA_O_OPTIONS 0x000000F4 + +// PKA firmware revision and capabilities register +#define PKA_O_FWREV 0x000000F8 + +// PKA hardware revision register +#define PKA_O_HWREV 0x000000FC + +//***************************************************************************** +// +// Register: PKA_O_APTR +// +//***************************************************************************** +// Field: [10:0] APTR +// +// This register specifies the location of vector A within the PKA RAM. Vectors +// are identified through the location of their least-significant 32-bit word. +// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte +// boundary. +#define PKA_APTR_APTR_W 11 +#define PKA_APTR_APTR_M 0x000007FF +#define PKA_APTR_APTR_S 0 + +//***************************************************************************** +// +// Register: PKA_O_BPTR +// +//***************************************************************************** +// Field: [10:0] BPTR +// +// This register specifies the location of vector B within the PKA RAM. Vectors +// are identified through the location of their least-significant 32-bit word. +// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte +// boundary. +#define PKA_BPTR_BPTR_W 11 +#define PKA_BPTR_BPTR_M 0x000007FF +#define PKA_BPTR_BPTR_S 0 + +//***************************************************************************** +// +// Register: PKA_O_CPTR +// +//***************************************************************************** +// Field: [10:0] CPTR +// +// This register specifies the location of vector C within the PKA RAM. Vectors +// are identified through the location of their least-significant 32-bit word. +// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte +// boundary. +#define PKA_CPTR_CPTR_W 11 +#define PKA_CPTR_CPTR_M 0x000007FF +#define PKA_CPTR_CPTR_S 0 + +//***************************************************************************** +// +// Register: PKA_O_DPTR +// +//***************************************************************************** +// Field: [10:0] DPTR +// +// This register specifies the location of vector D within the PKA RAM. Vectors +// are identified through the location of their least-significant 32-bit word. +// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte +// boundary. +#define PKA_DPTR_DPTR_W 11 +#define PKA_DPTR_DPTR_M 0x000007FF +#define PKA_DPTR_DPTR_S 0 + +//***************************************************************************** +// +// Register: PKA_O_ALENGTH +// +//***************************************************************************** +// Field: [8:0] ALENGTH +// +// This register specifies the length (in 32-bit words) of Vector A. +#define PKA_ALENGTH_ALENGTH_W 9 +#define PKA_ALENGTH_ALENGTH_M 0x000001FF +#define PKA_ALENGTH_ALENGTH_S 0 + +//***************************************************************************** +// +// Register: PKA_O_BLENGTH +// +//***************************************************************************** +// Field: [8:0] BLENGTH +// +// This register specifies the length (in 32-bit words) of Vector B. +#define PKA_BLENGTH_BLENGTH_W 9 +#define PKA_BLENGTH_BLENGTH_M 0x000001FF +#define PKA_BLENGTH_BLENGTH_S 0 + +//***************************************************************************** +// +// Register: PKA_O_SHIFT +// +//***************************************************************************** +// Field: [4:0] NUM_BITS_TO_SHIFT +// +// This register specifies the number of bits to shift the input vector (in the +// range 0-31) during a Rshift or Lshift operation. +#define PKA_SHIFT_NUM_BITS_TO_SHIFT_W 5 +#define PKA_SHIFT_NUM_BITS_TO_SHIFT_M 0x0000001F +#define PKA_SHIFT_NUM_BITS_TO_SHIFT_S 0 + +//***************************************************************************** +// +// Register: PKA_O_FUNCTION +// +//***************************************************************************** +// Field: [24] STALL_RESULT +// +// When written with a 1b, updating of the COMPARE bit, MSW and DIVMSW +// registers, as well as resetting the run bit is stalled beyond the point that +// a running operation is actually finished. Use this to allow software enough +// time to read results from a previous operation when the newly started +// operation is known to take only a short amount of time. If a result is +// waiting, the result registers is updated and the run bit is reset in the +// clock cycle following writing the stall result bit back to 0b. The Stall +// result function may only be used for basic PKCP operations. +#define PKA_FUNCTION_STALL_RESULT 0x01000000 +#define PKA_FUNCTION_STALL_RESULT_BITN 24 +#define PKA_FUNCTION_STALL_RESULT_M 0x01000000 +#define PKA_FUNCTION_STALL_RESULT_S 24 + +// Field: [15] RUN +// +// The host sets this bit to instruct the PKA module to begin processing the +// basic PKCP or complex sequencer operation. This bit is reset low +// automatically when the operation is complete. +// After a reset, the run bit is always set to 1b. Depending on the option, +// program ROM or program RAM, the following applies: +// Program ROM - The first sequencer instruction sets the bit to 0b. This is +// done immediately after the hardware reset is released. +// Program RAM - The sequencer must set the bit to 0b. As a valid firmware may +// not have been loaded, the sequencer is held in software reset after the +// hardware reset is released (the SEQCTRL.RESET bit is set to 1b). After the +// FW image is loaded and the Reset bit is cleared, the sequencer starts to +// execute the FW. The first instruction clears the run bit. +// In both cases a few clock cycles are needed before the first instruction is +// executed and the run bit state has been propagated. +#define PKA_FUNCTION_RUN 0x00008000 +#define PKA_FUNCTION_RUN_BITN 15 +#define PKA_FUNCTION_RUN_M 0x00008000 +#define PKA_FUNCTION_RUN_S 15 + +// Field: [14:12] SEQUENCER_OPERATIONS +// +// These bits select the complex sequencer operation to perform: +// 0x0: None +// 0x1: ExpMod-CRT +// 0x2: ECmontMUL +// 0x3: ECC-ADD (if available in firmware, otherwise reserved) +// 0x4: ExpMod-ACT2 +// 0x5: ECC-MUL (if available in firmware, otherwise reserved) +// 0x6: ExpMod-variable +// 0x7: ModInv (if available in firmware, otherwise reserved) +// The encoding of these operations is determined by sequencer firmware. +#define PKA_FUNCTION_SEQUENCER_OPERATIONS_W 3 +#define PKA_FUNCTION_SEQUENCER_OPERATIONS_M 0x00007000 +#define PKA_FUNCTION_SEQUENCER_OPERATIONS_S 12 + +// Field: [11] COPY +// +// Perform copy operation +#define PKA_FUNCTION_COPY 0x00000800 +#define PKA_FUNCTION_COPY_BITN 11 +#define PKA_FUNCTION_COPY_M 0x00000800 +#define PKA_FUNCTION_COPY_S 11 + +// Field: [10] COMPARE +// +// Perform compare operation +#define PKA_FUNCTION_COMPARE 0x00000400 +#define PKA_FUNCTION_COMPARE_BITN 10 +#define PKA_FUNCTION_COMPARE_M 0x00000400 +#define PKA_FUNCTION_COMPARE_S 10 + +// Field: [9] MODULO +// +// Perform modulo operation +#define PKA_FUNCTION_MODULO 0x00000200 +#define PKA_FUNCTION_MODULO_BITN 9 +#define PKA_FUNCTION_MODULO_M 0x00000200 +#define PKA_FUNCTION_MODULO_S 9 + +// Field: [8] DIVIDE +// +// Perform divide operation +#define PKA_FUNCTION_DIVIDE 0x00000100 +#define PKA_FUNCTION_DIVIDE_BITN 8 +#define PKA_FUNCTION_DIVIDE_M 0x00000100 +#define PKA_FUNCTION_DIVIDE_S 8 + +// Field: [7] LSHIFT +// +// Perform left shift operation +#define PKA_FUNCTION_LSHIFT 0x00000080 +#define PKA_FUNCTION_LSHIFT_BITN 7 +#define PKA_FUNCTION_LSHIFT_M 0x00000080 +#define PKA_FUNCTION_LSHIFT_S 7 + +// Field: [6] RSHIFT +// +// Perform right shift operation +#define PKA_FUNCTION_RSHIFT 0x00000040 +#define PKA_FUNCTION_RSHIFT_BITN 6 +#define PKA_FUNCTION_RSHIFT_M 0x00000040 +#define PKA_FUNCTION_RSHIFT_S 6 + +// Field: [5] SUBTRACT +// +// Perform subtract operation +#define PKA_FUNCTION_SUBTRACT 0x00000020 +#define PKA_FUNCTION_SUBTRACT_BITN 5 +#define PKA_FUNCTION_SUBTRACT_M 0x00000020 +#define PKA_FUNCTION_SUBTRACT_S 5 + +// Field: [4] ADD +// +// Perform add operation +#define PKA_FUNCTION_ADD 0x00000010 +#define PKA_FUNCTION_ADD_BITN 4 +#define PKA_FUNCTION_ADD_M 0x00000010 +#define PKA_FUNCTION_ADD_S 4 + +// Field: [3] MS_ONE +// +// Loads the location of the Most Significant one bit within the result word +// indicated in the MSW register into bits [4:0] of the DIVMSW.MSW_ADDRESS +// register - can only be used with basic PKCP operations, except for Divide, +// Modulo and Compare. +#define PKA_FUNCTION_MS_ONE 0x00000008 +#define PKA_FUNCTION_MS_ONE_BITN 3 +#define PKA_FUNCTION_MS_ONE_M 0x00000008 +#define PKA_FUNCTION_MS_ONE_S 3 + +// Field: [1] ADDSUB +// +// Perform combined add/subtract operation +#define PKA_FUNCTION_ADDSUB 0x00000002 +#define PKA_FUNCTION_ADDSUB_BITN 1 +#define PKA_FUNCTION_ADDSUB_M 0x00000002 +#define PKA_FUNCTION_ADDSUB_S 1 + +// Field: [0] MULTIPLY +// +// Perform multiply operation +#define PKA_FUNCTION_MULTIPLY 0x00000001 +#define PKA_FUNCTION_MULTIPLY_BITN 0 +#define PKA_FUNCTION_MULTIPLY_M 0x00000001 +#define PKA_FUNCTION_MULTIPLY_S 0 + +//***************************************************************************** +// +// Register: PKA_O_COMPARE +// +//***************************************************************************** +// Field: [2] A_GREATER_THAN_B +// +// Vector_A is greater than Vector_B +#define PKA_COMPARE_A_GREATER_THAN_B 0x00000004 +#define PKA_COMPARE_A_GREATER_THAN_B_BITN 2 +#define PKA_COMPARE_A_GREATER_THAN_B_M 0x00000004 +#define PKA_COMPARE_A_GREATER_THAN_B_S 2 + +// Field: [1] A_LESS_THAN_B +// +// Vector_A is less than Vector_B +#define PKA_COMPARE_A_LESS_THAN_B 0x00000002 +#define PKA_COMPARE_A_LESS_THAN_B_BITN 1 +#define PKA_COMPARE_A_LESS_THAN_B_M 0x00000002 +#define PKA_COMPARE_A_LESS_THAN_B_S 1 + +// Field: [0] A_EQUALS_B +// +// Vector_A is equal to Vector_B +#define PKA_COMPARE_A_EQUALS_B 0x00000001 +#define PKA_COMPARE_A_EQUALS_B_BITN 0 +#define PKA_COMPARE_A_EQUALS_B_M 0x00000001 +#define PKA_COMPARE_A_EQUALS_B_S 0 + +//***************************************************************************** +// +// Register: PKA_O_MSW +// +//***************************************************************************** +// Field: [15] RESULT_IS_ZERO +// +// The result vector is all zeroes, ignore the address returned in bits [10:0] +#define PKA_MSW_RESULT_IS_ZERO 0x00008000 +#define PKA_MSW_RESULT_IS_ZERO_BITN 15 +#define PKA_MSW_RESULT_IS_ZERO_M 0x00008000 +#define PKA_MSW_RESULT_IS_ZERO_S 15 + +// Field: [10:0] MSW_ADDRESS +// +// Address of the most-significant nonzero 32-bit word of the result vector in +// PKA RAM +#define PKA_MSW_MSW_ADDRESS_W 11 +#define PKA_MSW_MSW_ADDRESS_M 0x000007FF +#define PKA_MSW_MSW_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: PKA_O_DIVMSW +// +//***************************************************************************** +// Field: [15] RESULT_IS_ZERO +// +// The result vector is all zeroes, ignore the address returned in bits [10:0] +#define PKA_DIVMSW_RESULT_IS_ZERO 0x00008000 +#define PKA_DIVMSW_RESULT_IS_ZERO_BITN 15 +#define PKA_DIVMSW_RESULT_IS_ZERO_M 0x00008000 +#define PKA_DIVMSW_RESULT_IS_ZERO_S 15 + +// Field: [10:0] MSW_ADDRESS +// +// Address of the most significant nonzero 32-bit word of the remainder result +// vector in PKA RAM +#define PKA_DIVMSW_MSW_ADDRESS_W 11 +#define PKA_DIVMSW_MSW_ADDRESS_M 0x000007FF +#define PKA_DIVMSW_MSW_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: PKA_O_SEQCTRL +// +//***************************************************************************** +// Field: [31] RESET +// +// Option program ROM: Reset value = 0. Read/Write, reset value 0b (ZERO). +// Writing 1b resets the sequencer, write to 0b to restart operations again. As +// the reset value is 0b, the sequencer will automatically start operations +// executing from program ROM. This bit should always be written with zero and +// ignored when reading this register. +// +// Option Program RAM: Reset value =1. Read/Write, reset value 1b (ONE). When +// 1b, the sequencer is held in a reset state and the PKA_PROGRAM area is +// accessible for loading the sequencer program (while the PKA_DATA_RAM is +// inaccessible), write to 0b to (re)start sequencer operations and disable +// PKA_PROGRAM area accessibility (also enables the PKA_DATA_RAM accesses). +// Resetting the sequencer (in order to load other firmware) should only be +// done when the PKA Engine is not performing any operations (i.e. the +// FUNCTION.RUN bit should be zero). +#define PKA_SEQCTRL_RESET 0x80000000 +#define PKA_SEQCTRL_RESET_BITN 31 +#define PKA_SEQCTRL_RESET_M 0x80000000 +#define PKA_SEQCTRL_RESET_S 31 + +// Field: [15:8] SEQUENCER_STAT +// +// These read-only bits can be used by the sequencer to communicate status to +// the outside world. Bit [8] is also used as sequencer interrupt, with the +// complement of this bit ORed into the FUNCTION.RUN bit. This field should +// always be written with zeroes and ignored when reading this register. +#define PKA_SEQCTRL_SEQUENCER_STAT_W 8 +#define PKA_SEQCTRL_SEQUENCER_STAT_M 0x0000FF00 +#define PKA_SEQCTRL_SEQUENCER_STAT_S 8 + +// Field: [7:0] SW_CONTROL_STAT +// +// These bits can be used by software to trigger sequencer operations. External +// logic can set these bits by writing 1b, cannot reset them by writing 0b. The +// sequencer can reset these bits by writing 0b, cannot set them by writing 1b. +// Setting the FUNCTION.RUN bit together with a nonzero sequencer operations +// field automatically sets bit [0] here. This field should always be written +// with zeroes and ignored when reading this register. +#define PKA_SEQCTRL_SW_CONTROL_STAT_W 8 +#define PKA_SEQCTRL_SW_CONTROL_STAT_M 0x000000FF +#define PKA_SEQCTRL_SW_CONTROL_STAT_S 0 + +//***************************************************************************** +// +// Register: PKA_O_OPTIONS +// +//***************************************************************************** +// Field: [11] INT_MASKING +// +// Interrupt Masking +// 0x0: indicates that the main interrupt output (bit [1] of the interrupts +// output bus) is the direct complement of the run bit in the PKA_CONTROL +// register, 0x1 : indicates +// that interrupt masking logic is present for this output. +// Note: Reset value is undefined +#define PKA_OPTIONS_INT_MASKING 0x00000800 +#define PKA_OPTIONS_INT_MASKING_BITN 11 +#define PKA_OPTIONS_INT_MASKING_M 0x00000800 +#define PKA_OPTIONS_INT_MASKING_S 11 + +// Field: [10:8] PROTECTION_OPTION +// +// Protection Option +// 0x0: indicates no additional protection against side channel attacks, +// +// 0x1: indicates the SCAP option +// 0x2: Reserved +// 0x3: indicates the PROT option; +// Note: Reset value is undefined +#define PKA_OPTIONS_PROTECTION_OPTION_W 3 +#define PKA_OPTIONS_PROTECTION_OPTION_M 0x00000700 +#define PKA_OPTIONS_PROTECTION_OPTION_S 8 + +// Field: [7] PROGRAM_RAM +// +// Program RAM +// 0x1: indicates sequencer program storage in RAM, 0x0: +// indicates sequencer program storage in ROM. +// Note: Reset value is undefined +#define PKA_OPTIONS_PROGRAM_RAM 0x00000080 +#define PKA_OPTIONS_PROGRAM_RAM_BITN 7 +#define PKA_OPTIONS_PROGRAM_RAM_M 0x00000080 +#define PKA_OPTIONS_PROGRAM_RAM_S 7 + +// Field: [6:5] SEQUENCER_CONFIGURATION +// +// Sequencer Configuration +// 0x0: Reserved +// 0x1 : Indicates a standard sequencer +// 0x2: Reserved +// 0x3: Reserved +#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_W 2 +#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_M 0x00000060 +#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_S 5 + +// Field: [1:0] PKCP_CONFIGURATION +// +// PKCP Configuration 0x0 +// : Reserved +// 0x1 : Indicates a PKCP with a 16x16 multiplier, 0x2: +// indicates a PKCP with a 32x32 multiplier, 0x3 : Reserved +// Note: Reset value is undefined. +#define PKA_OPTIONS_PKCP_CONFIGURATION_W 2 +#define PKA_OPTIONS_PKCP_CONFIGURATION_M 0x00000003 +#define PKA_OPTIONS_PKCP_CONFIGURATION_S 0 + +//***************************************************************************** +// +// Register: PKA_O_FWREV +// +//***************************************************************************** +// Field: [31:28] FW_CAPABILITIES +// +// Firmware Capabilities +// +// 4-bit binary encoding for the functionality implemented +// in the firmware. +// 0x0: indicates basic ModExp with/without CRT. 0x1: +// adds Modular Inversion, 0x2: value +// 2 adds Modular Inversion and ECC operations. +// 0x3-0xF : Reserved. +#define PKA_FWREV_FW_CAPABILITIES_W 4 +#define PKA_FWREV_FW_CAPABILITIES_M 0xF0000000 +#define PKA_FWREV_FW_CAPABILITIES_S 28 + +// Field: [27:24] MAJOR_FW_REVISION +// +// 4-bit binary encoding of the major firmware revision number +#define PKA_FWREV_MAJOR_FW_REVISION_W 4 +#define PKA_FWREV_MAJOR_FW_REVISION_M 0x0F000000 +#define PKA_FWREV_MAJOR_FW_REVISION_S 24 + +// Field: [23:20] MINOR_FW_REVISION +// +// 4-bit binary encoding of the minor firmware revision number +#define PKA_FWREV_MINOR_FW_REVISION_W 4 +#define PKA_FWREV_MINOR_FW_REVISION_M 0x00F00000 +#define PKA_FWREV_MINOR_FW_REVISION_S 20 + +// Field: [19:16] FW_PATCH_LEVEL +// +// 4-bit binary encoding of the firmware patch level, initial release will +// carry value zero +// Patches are used to remove bugs without changing the functionality or +// interface of a module. +#define PKA_FWREV_FW_PATCH_LEVEL_W 4 +#define PKA_FWREV_FW_PATCH_LEVEL_M 0x000F0000 +#define PKA_FWREV_FW_PATCH_LEVEL_S 16 + +//***************************************************************************** +// +// Register: PKA_O_HWREV +// +//***************************************************************************** +// Field: [27:24] MAJOR_HW_REVISION +// +// 4-bit binary encoding of the major hardware revision number +#define PKA_HWREV_MAJOR_HW_REVISION_W 4 +#define PKA_HWREV_MAJOR_HW_REVISION_M 0x0F000000 +#define PKA_HWREV_MAJOR_HW_REVISION_S 24 + +// Field: [23:20] MINOR_HW_REVISION +// +// 4-bit binary encoding of the minor hardware revision number +#define PKA_HWREV_MINOR_HW_REVISION_W 4 +#define PKA_HWREV_MINOR_HW_REVISION_M 0x00F00000 +#define PKA_HWREV_MINOR_HW_REVISION_S 20 + +// Field: [19:16] HW_PATCH_LEVEL +// +// 4-bit binary encoding of the hardware patch level, initial release will +// carry value zero +// Patches are used to remove bugs without changing the functionality or +// interface of a module. +#define PKA_HWREV_HW_PATCH_LEVEL_W 4 +#define PKA_HWREV_HW_PATCH_LEVEL_M 0x000F0000 +#define PKA_HWREV_HW_PATCH_LEVEL_S 16 + +// Field: [15:8] COMPLEMENT_OF_BASIC_EIP_NUMBER +// +// Bit-by-bit logic complement of bits [7:0], EIP-28 gives 0xE3 +#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_W 8 +#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_M 0x0000FF00 +#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_S 8 + +// Field: [7:0] BASIC_EIP_NUMBER +// +// 8-bit binary encoding of the EIP number, EIP-28 gives 0x1C +#define PKA_HWREV_BASIC_EIP_NUMBER_W 8 +#define PKA_HWREV_BASIC_EIP_NUMBER_M 0x000000FF +#define PKA_HWREV_BASIC_EIP_NUMBER_S 0 + + +#endif // __PKA__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h new file mode 100644 index 0000000..5920199 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h @@ -0,0 +1,157 @@ +/****************************************************************************** +* Filename: hw_pka_int_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_PKA_INT_H__ +#define __HW_PKA_INT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// PKA_INT component +// +//***************************************************************************** +// PKA Options register +#define PKA_INT_O_OPTIONS 0x00000FF8 + +// PKA hardware revision register +#define PKA_INT_O_REVISION 0x00000FFC + +//***************************************************************************** +// +// Register: PKA_INT_O_OPTIONS +// +//***************************************************************************** +// Field: [10] AIC_PRESENT +// +// When set to '1', indicates that an EIP201 AIC is included in the EIP150 +#define PKA_INT_OPTIONS_AIC_PRESENT 0x00000400 +#define PKA_INT_OPTIONS_AIC_PRESENT_BITN 10 +#define PKA_INT_OPTIONS_AIC_PRESENT_M 0x00000400 +#define PKA_INT_OPTIONS_AIC_PRESENT_S 10 + +// Field: [9] EIP76_PRESENT +// +// When set to '1', indicates that the EIP76 TRNG is included in the EIP150 +#define PKA_INT_OPTIONS_EIP76_PRESENT 0x00000200 +#define PKA_INT_OPTIONS_EIP76_PRESENT_BITN 9 +#define PKA_INT_OPTIONS_EIP76_PRESENT_M 0x00000200 +#define PKA_INT_OPTIONS_EIP76_PRESENT_S 9 + +// Field: [8] EIP28_PRESENT +// +// When set to '1', indicates that the EIP28 PKA is included in the EIP150 +#define PKA_INT_OPTIONS_EIP28_PRESENT 0x00000100 +#define PKA_INT_OPTIONS_EIP28_PRESENT_BITN 8 +#define PKA_INT_OPTIONS_EIP28_PRESENT_M 0x00000100 +#define PKA_INT_OPTIONS_EIP28_PRESENT_S 8 + +// Field: [3] AXI_INTERFACE +// +// When set to '1', indicates that the EIP150 is equipped with a AXI interface +#define PKA_INT_OPTIONS_AXI_INTERFACE 0x00000008 +#define PKA_INT_OPTIONS_AXI_INTERFACE_BITN 3 +#define PKA_INT_OPTIONS_AXI_INTERFACE_M 0x00000008 +#define PKA_INT_OPTIONS_AXI_INTERFACE_S 3 + +// Field: [2] AHB_IS_ASYNC +// +// When set to '1', indicates that AHB interface is asynchronous Only +// applicable when AHB_INTERFACE is 1 +#define PKA_INT_OPTIONS_AHB_IS_ASYNC 0x00000004 +#define PKA_INT_OPTIONS_AHB_IS_ASYNC_BITN 2 +#define PKA_INT_OPTIONS_AHB_IS_ASYNC_M 0x00000004 +#define PKA_INT_OPTIONS_AHB_IS_ASYNC_S 2 + +// Field: [1] AHB_INTERFACE +// +// When set to '1', indicates that the EIP150 is equipped with a AHB interface +#define PKA_INT_OPTIONS_AHB_INTERFACE 0x00000002 +#define PKA_INT_OPTIONS_AHB_INTERFACE_BITN 1 +#define PKA_INT_OPTIONS_AHB_INTERFACE_M 0x00000002 +#define PKA_INT_OPTIONS_AHB_INTERFACE_S 1 + +// Field: [0] PLB_INTERFACE +// +// When set to '1', indicates that the EIP150 is equipped with a PLB interface +#define PKA_INT_OPTIONS_PLB_INTERFACE 0x00000001 +#define PKA_INT_OPTIONS_PLB_INTERFACE_BITN 0 +#define PKA_INT_OPTIONS_PLB_INTERFACE_M 0x00000001 +#define PKA_INT_OPTIONS_PLB_INTERFACE_S 0 + +//***************************************************************************** +// +// Register: PKA_INT_O_REVISION +// +//***************************************************************************** +// Field: [27:24] MAJOR_REVISION +// +// These bits encode the major version number for this module +#define PKA_INT_REVISION_MAJOR_REVISION_W 4 +#define PKA_INT_REVISION_MAJOR_REVISION_M 0x0F000000 +#define PKA_INT_REVISION_MAJOR_REVISION_S 24 + +// Field: [23:20] MINOR_REVISION +// +// These bits encode the minor version number for this module +#define PKA_INT_REVISION_MINOR_REVISION_W 4 +#define PKA_INT_REVISION_MINOR_REVISION_M 0x00F00000 +#define PKA_INT_REVISION_MINOR_REVISION_S 20 + +// Field: [19:16] PATCH_LEVEL +// +// These bits encode the hardware patch level for this module they start at +// value 0 on the first release +#define PKA_INT_REVISION_PATCH_LEVEL_W 4 +#define PKA_INT_REVISION_PATCH_LEVEL_M 0x000F0000 +#define PKA_INT_REVISION_PATCH_LEVEL_S 16 + +// Field: [15:8] COMP_EIP_NUM +// +// These bits simply contain the complement of bits [7:0], used by a driver to +// ascertain that the EIP150 revision register is indeed read +#define PKA_INT_REVISION_COMP_EIP_NUM_W 8 +#define PKA_INT_REVISION_COMP_EIP_NUM_M 0x0000FF00 +#define PKA_INT_REVISION_COMP_EIP_NUM_S 8 + +// Field: [7:0] EIP_NUM +// +// These bits encode the AuthenTec EIP number for the EIP150 +#define PKA_INT_REVISION_EIP_NUM_W 8 +#define PKA_INT_REVISION_EIP_NUM_M 0x000000FF +#define PKA_INT_REVISION_EIP_NUM_S 0 + + +#endif // __PKA_INT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h new file mode 100644 index 0000000..4c4599e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* Filename: hw_pka_ram_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_PKA_RAM_H__ +#define __HW_PKA_RAM_H__ + + +#define PKA_RAM_O_BANK0 0x00000000 +#define PKA_RAM_BANK0_BYTE_SIZE 2048 + +#define PKA_RAM_TOT_BYTE_SIZE 2048 + + + +#endif // __HW_PKA_RAM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h new file mode 100644 index 0000000..38fecfa --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h @@ -0,0 +1,2529 @@ +/****************************************************************************** +* Filename: hw_prcm_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_PRCM_H__ +#define __HW_PRCM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// PRCM component +// +//***************************************************************************** +// Infrastructure Clock Division Factor For Run Mode +#define PRCM_O_INFRCLKDIVR 0x00000000 + +// Infrastructure Clock Division Factor For Sleep Mode +#define PRCM_O_INFRCLKDIVS 0x00000004 + +// Infrastructure Clock Division Factor For DeepSleep Mode +#define PRCM_O_INFRCLKDIVDS 0x00000008 + +// MCU Voltage Domain Control +#define PRCM_O_VDCTL 0x0000000C + +// Load PRCM Settings To CLKCTRL Power Domain +#define PRCM_O_CLKLOADCTL 0x00000028 + +// RFC Clock Gate +#define PRCM_O_RFCCLKG 0x0000002C + +// VIMS Clock Gate +#define PRCM_O_VIMSCLKG 0x00000030 + +// SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes +#define PRCM_O_SECDMACLKGR 0x0000003C + +// SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode +#define PRCM_O_SECDMACLKGS 0x00000040 + +// SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode +#define PRCM_O_SECDMACLKGDS 0x00000044 + +// GPIO Clock Gate For Run And All Modes +#define PRCM_O_GPIOCLKGR 0x00000048 + +// GPIO Clock Gate For Sleep Mode +#define PRCM_O_GPIOCLKGS 0x0000004C + +// GPIO Clock Gate For Deep Sleep Mode +#define PRCM_O_GPIOCLKGDS 0x00000050 + +// GPT Clock Gate For Run And All Modes +#define PRCM_O_GPTCLKGR 0x00000054 + +// GPT Clock Gate For Sleep Mode +#define PRCM_O_GPTCLKGS 0x00000058 + +// GPT Clock Gate For Deep Sleep Mode +#define PRCM_O_GPTCLKGDS 0x0000005C + +// I2C Clock Gate For Run And All Modes +#define PRCM_O_I2CCLKGR 0x00000060 + +// I2C Clock Gate For Sleep Mode +#define PRCM_O_I2CCLKGS 0x00000064 + +// I2C Clock Gate For Deep Sleep Mode +#define PRCM_O_I2CCLKGDS 0x00000068 + +// UART Clock Gate For Run And All Modes +#define PRCM_O_UARTCLKGR 0x0000006C + +// UART Clock Gate For Sleep Mode +#define PRCM_O_UARTCLKGS 0x00000070 + +// UART Clock Gate For Deep Sleep Mode +#define PRCM_O_UARTCLKGDS 0x00000074 + +// SSI Clock Gate For Run And All Modes +#define PRCM_O_SSICLKGR 0x00000078 + +// SSI Clock Gate For Sleep Mode +#define PRCM_O_SSICLKGS 0x0000007C + +// SSI Clock Gate For Deep Sleep Mode +#define PRCM_O_SSICLKGDS 0x00000080 + +// I2S Clock Gate For Run And All Modes +#define PRCM_O_I2SCLKGR 0x00000084 + +// I2S Clock Gate For Sleep Mode +#define PRCM_O_I2SCLKGS 0x00000088 + +// I2S Clock Gate For Deep Sleep Mode +#define PRCM_O_I2SCLKGDS 0x0000008C + +// Internal +#define PRCM_O_SYSBUSCLKDIV 0x000000B4 + +// Internal +#define PRCM_O_CPUCLKDIV 0x000000B8 + +// Internal +#define PRCM_O_PERBUSCPUCLKDIV 0x000000BC + +// Internal +#define PRCM_O_PERDMACLKDIV 0x000000C4 + +// I2S Clock Control +#define PRCM_O_I2SBCLKSEL 0x000000C8 + +// GPT Scalar +#define PRCM_O_GPTCLKDIV 0x000000CC + +// I2S Clock Control +#define PRCM_O_I2SCLKCTL 0x000000D0 + +// MCLK Division Ratio +#define PRCM_O_I2SMCLKDIV 0x000000D4 + +// BCLK Division Ratio +#define PRCM_O_I2SBCLKDIV 0x000000D8 + +// WCLK Division Ratio +#define PRCM_O_I2SWCLKDIV 0x000000DC + +// RESET For SEC (PKA And TRNG And CRYPTO) And UDMA +#define PRCM_O_RESETSECDMA 0x000000F0 + +// RESET For GPIO IPs +#define PRCM_O_RESETGPIO 0x000000F4 + +// RESET For GPT Ips +#define PRCM_O_RESETGPT 0x000000F8 + +// RESET For I2C IPs +#define PRCM_O_RESETI2C 0x000000FC + +// RESET For UART IPs +#define PRCM_O_RESETUART 0x00000100 + +// RESET For SSI IPs +#define PRCM_O_RESETSSI 0x00000104 + +// RESET For I2S IP +#define PRCM_O_RESETI2S 0x00000108 + +// Power Domain Control +#define PRCM_O_PDCTL0 0x0000012C + +// RFC Power Domain Control +#define PRCM_O_PDCTL0RFC 0x00000130 + +// SERIAL Power Domain Control +#define PRCM_O_PDCTL0SERIAL 0x00000134 + +// PERIPH Power Domain Control +#define PRCM_O_PDCTL0PERIPH 0x00000138 + +// Power Domain Status +#define PRCM_O_PDSTAT0 0x00000140 + +// RFC Power Domain Status +#define PRCM_O_PDSTAT0RFC 0x00000144 + +// SERIAL Power Domain Status +#define PRCM_O_PDSTAT0SERIAL 0x00000148 + +// PERIPH Power Domain Status +#define PRCM_O_PDSTAT0PERIPH 0x0000014C + +// Power Domain Control +#define PRCM_O_PDCTL1 0x0000017C + +// CPU Power Domain Direct Control +#define PRCM_O_PDCTL1CPU 0x00000184 + +// RFC Power Domain Direct Control +#define PRCM_O_PDCTL1RFC 0x00000188 + +// VIMS Mode Direct Control +#define PRCM_O_PDCTL1VIMS 0x0000018C + +// Power Manager Status +#define PRCM_O_PDSTAT1 0x00000194 + +// BUS Power Domain Direct Read Status +#define PRCM_O_PDSTAT1BUS 0x00000198 + +// RFC Power Domain Direct Read Status +#define PRCM_O_PDSTAT1RFC 0x0000019C + +// CPU Power Domain Direct Read Status +#define PRCM_O_PDSTAT1CPU 0x000001A0 + +// VIMS Mode Direct Read Status +#define PRCM_O_PDSTAT1VIMS 0x000001A4 + +// Control To RFC +#define PRCM_O_RFCBITS 0x000001CC + +// Selected RFC Mode +#define PRCM_O_RFCMODESEL 0x000001D0 + +// Allowed RFC Modes +#define PRCM_O_RFCMODEHWOPT 0x000001D4 + +// Power Profiler Register +#define PRCM_O_PWRPROFSTAT 0x000001E0 + +// MCU SRAM configuration +#define PRCM_O_MCUSRAMCFG 0x0000021C + +// Memory Retention Control +#define PRCM_O_RAMRETEN 0x00000224 + +// Oscillator Interrupt Mask +#define PRCM_O_OSCIMSC 0x00000290 + +// Oscillator Raw Interrupt Status +#define PRCM_O_OSCRIS 0x00000294 + +// Oscillator Raw Interrupt Clear +#define PRCM_O_OSCICR 0x00000298 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVR +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in run mode. Division ratio affects both infrastructure clock and +// perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVR_RATIO_W 2 +#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_S 0 +#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVS +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in sleep mode. Division ratio affects both infrastructure clock and +// perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVS_RATIO_W 2 +#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_S 0 +#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVDS +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in seepsleep mode. Division ratio affects both infrastructure clock +// and perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVDS_RATIO_W 2 +#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_S 0 +#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_VDCTL +// +//***************************************************************************** +// Field: [0] ULDO +// +// Request PMCTL to switch to uLDO. +// +// 0: No request +// 1: Assert request when possible +// +// The bit will have no effect before the following requirements are met: +// 1. PDCTL1.CPU_ON = 0 +// 2. PDCTL1.VIMS_MODE = x0 +// 3. SECDMACLKGDS.DMA_CLK_EN = 0 and S.CRYPTO_CLK_EN] = 0 and +// SECDMACLKGR.DMA_AM_CLK_EN = 0 (Note: Settings must be loaded with +// CLKLOADCTL.LOAD) +// 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 and SECDMACLKGR.CRYPTO_AM_CLK_EN = 0 +// (Note: Settings must be loaded with CLKLOADCTL.LOAD) +// 5. I2SCLKGDS.CLK_EN = 0 and I2SCLKGR.AM_CLK_EN = 0 (Note: Settings must be +// loaded with CLKLOADCTL.LOAD) +// 6. RFC do no request access to BUS +// 7. System CPU in deepsleep +#define PRCM_VDCTL_ULDO 0x00000001 +#define PRCM_VDCTL_ULDO_BITN 0 +#define PRCM_VDCTL_ULDO_M 0x00000001 +#define PRCM_VDCTL_ULDO_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_CLKLOADCTL +// +//***************************************************************************** +// Field: [1] LOAD_DONE +// +// Status of LOAD. +// Will be cleared to 0 when any of the registers requiring a LOAD is written +// to, and be set to 1 when a LOAD is done. +// Note that writing no change to a register will result in the LOAD_DONE being +// cleared. +// +// 0 : One or more registers have been write accessed after last LOAD +// 1 : No registers are write accessed after last LOAD +#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 +#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_S 1 + +// Field: [0] LOAD +// +// +// 0: No action +// 1: Load settings to CLKCTRL. Bit is HW cleared. +// +// Multiple changes to settings may be done before LOAD is written once so all +// changes takes place at the same time. LOAD can also be done after single +// setting updates. +// +// Registers that needs to be followed by LOAD before settings being applied +// are: +// - SYSBUSCLKDIV +// - CPUCLKDIV +// - PERBUSCPUCLKDIV +// - PERDMACLKDIV +// - PERBUSCPUCLKG +// - RFCCLKG +// - VIMSCLKG +// - SECDMACLKGR +// - SECDMACLKGS +// - SECDMACLKGDS +// - GPIOCLKGR +// - GPIOCLKGS +// - GPIOCLKGDS +// - GPTCLKGR +// - GPTCLKGS +// - GPTCLKGDS +// - GPTCLKDIV +// - I2CCLKGR +// - I2CCLKGS +// - I2CCLKGDS +// - SSICLKGR +// - SSICLKGS +// - SSICLKGDS +// - UARTCLKGR +// - UARTCLKGS +// - UARTCLKGDS +// - I2SCLKGR +// - I2SCLKGS +// - I2SCLKGDS +// - I2SBCLKSEL +// - I2SCLKCTL +// - I2SMCLKDIV +// - I2SBCLKDIV +// - I2SWCLKDIV +#define PRCM_CLKLOADCTL_LOAD 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_BITN 0 +#define PRCM_CLKLOADCTL_LOAD_M 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCCLKG +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable Clock +// 1: Enable clock if RFC power domain is on +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_RFCCLKG_CLK_EN 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_BITN 0 +#define PRCM_RFCCLKG_CLK_EN_M 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_VIMSCLKG +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// 00: Disable clock +// 01: Disable clock when SYSBUS clock is disabled +// 11: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_VIMSCLKG_CLK_EN_W 2 +#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 +#define PRCM_VIMSCLKG_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGR +// +//***************************************************************************** +// Field: [24] DMA_AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides DMA_CLK_EN, SECDMACLKGS.DMA_CLK_EN and SECDMACLKGDS.DMA_CLK_EN +// when enabled. +// +// SYSBUS clock will always run when enabled +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN 0x01000000 +#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_BITN 24 +#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_M 0x01000000 +#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_S 24 + +// Field: [19] PKA_ZERIOZE_RESET_N +// +// Zeroization logic hardware reset. +// +// 0: pka_zeroize logic inactive. +// 1: pka_zeroize of memory is enabled. +// +// This register must remain active until the memory are completely zeroized +// which requires 256 periods on systembus clock. +#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N 0x00080000 +#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_BITN 19 +#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_M 0x00080000 +#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_S 19 + +// Field: [18] PKA_AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides PKA_CLK_EN, SECDMACLKGS.PKA_CLK_EN and SECDMACLKGDS.PKA_CLK_EN +// when enabled. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN 0x00040000 +#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_BITN 18 +#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_M 0x00040000 +#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_S 18 + +// Field: [17] TRNG_AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides TRNG_CLK_EN, SECDMACLKGS.TRNG_CLK_EN and SECDMACLKGDS.TRNG_CLK_EN +// when enabled. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN 0x00020000 +#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_BITN 17 +#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_M 0x00020000 +#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_S 17 + +// Field: [16] CRYPTO_AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CRYPTO_CLK_EN, SECDMACLKGS.CRYPTO_CLK_EN and +// SECDMACLKGDS.CRYPTO_CLK_EN when enabled. +// +// SYSBUS clock will always run when enabled +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN 0x00010000 +#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_BITN 16 +#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_M 0x00010000 +#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_S 16 + +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by DMA_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 + +// Field: [2] PKA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by PKA_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_PKA_CLK_EN 0x00000004 +#define PRCM_SECDMACLKGR_PKA_CLK_EN_BITN 2 +#define PRCM_SECDMACLKGR_PKA_CLK_EN_M 0x00000004 +#define PRCM_SECDMACLKGR_PKA_CLK_EN_S 2 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by TRNG_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by CRYPTO_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGS +// +//***************************************************************************** +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 + +// Field: [2] PKA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_PKA_CLK_EN 0x00000004 +#define PRCM_SECDMACLKGS_PKA_CLK_EN_BITN 2 +#define PRCM_SECDMACLKGS_PKA_CLK_EN_M 0x00000004 +#define PRCM_SECDMACLKGS_PKA_CLK_EN_S 2 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGDS +// +//***************************************************************************** +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 + +// Field: [2] PKA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_PKA_CLK_EN 0x00000004 +#define PRCM_SECDMACLKGDS_PKA_CLK_EN_BITN 2 +#define PRCM_SECDMACLKGDS_PKA_CLK_EN_M 0x00000004 +#define PRCM_SECDMACLKGDS_PKA_CLK_EN_S 2 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// SYSBUS clock will always run when enabled +// +// Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// SYSBUS clock will always run when enabled +// +// Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGR +// +//***************************************************************************** +// Field: [8] AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CLK_EN, GPIOCLKGS.CLK_EN and GPIOCLKGDS.CLK_EN when enabled. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGR_AM_CLK_EN 0x00000100 +#define PRCM_GPIOCLKGR_AM_CLK_EN_BITN 8 +#define PRCM_GPIOCLKGR_AM_CLK_EN_M 0x00000100 +#define PRCM_GPIOCLKGR_AM_CLK_EN_S 8 + +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGR_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by GPIOCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by GPIOCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGR +// +//***************************************************************************** +// Field: [11:8] AM_CLK_EN +// +// Each bit below has the following meaning: +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CLK_EN, GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled. +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// AM_GPT3 Enable clock for GPT3 in all modes +// AM_GPT2 Enable clock for GPT2 in all modes +// AM_GPT1 Enable clock for GPT1 in all modes +// AM_GPT0 Enable clock for GPT0 in all modes +#define PRCM_GPTCLKGR_AM_CLK_EN_W 4 +#define PRCM_GPTCLKGR_AM_CLK_EN_M 0x00000F00 +#define PRCM_GPTCLKGR_AM_CLK_EN_S 8 +#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT3 0x00000800 +#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT2 0x00000400 +#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT1 0x00000200 +#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT0 0x00000100 + +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by AM_CLK_EN +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGR_CLK_EN_W 4 +#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGR_CLK_EN_S 0 +#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGS +// +//***************************************************************************** +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by GPTCLKGR.AM_CLK_EN +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGS_CLK_EN_W 4 +#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGS_CLK_EN_S 0 +#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGDS +// +//***************************************************************************** +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by GPTCLKGR.AM_CLK_EN +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGDS_CLK_EN_W 4 +#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGDS_CLK_EN_S 0 +#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGR +// +//***************************************************************************** +// Field: [8] AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CLK_EN, I2CCLKGS.CLK_EN and I2CCLKGDS.CLK_EN when enabled. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGR_AM_CLK_EN 0x00000100 +#define PRCM_I2CCLKGR_AM_CLK_EN_BITN 8 +#define PRCM_I2CCLKGR_AM_CLK_EN_M 0x00000100 +#define PRCM_I2CCLKGR_AM_CLK_EN_S 8 + +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGR_CLK_EN 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_BITN 0 +#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by I2CCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by I2CCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGR +// +//***************************************************************************** +// Field: [9:8] AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CLK_EN, UARTCLKGS.CLK_EN and UARTCLKGDS.CLK_EN when enabled. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// AM_UART1 Enable clock for UART1 +// AM_UART0 Enable clock for UART0 +#define PRCM_UARTCLKGR_AM_CLK_EN_W 2 +#define PRCM_UARTCLKGR_AM_CLK_EN_M 0x00000300 +#define PRCM_UARTCLKGR_AM_CLK_EN_S 8 +#define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART1 0x00000200 +#define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART0 0x00000100 + +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// UART1 Enable clock for UART1 +// UART0 Enable clock for UART0 +#define PRCM_UARTCLKGR_CLK_EN_W 2 +#define PRCM_UARTCLKGR_CLK_EN_M 0x00000003 +#define PRCM_UARTCLKGR_CLK_EN_S 0 +#define PRCM_UARTCLKGR_CLK_EN_UART1 0x00000002 +#define PRCM_UARTCLKGR_CLK_EN_UART0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by UARTCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// AM_UART1 Enable clock for UART1 +// AM_UART0 Enable clock for UART0 +#define PRCM_UARTCLKGS_CLK_EN_W 2 +#define PRCM_UARTCLKGS_CLK_EN_M 0x00000003 +#define PRCM_UARTCLKGS_CLK_EN_S 0 +#define PRCM_UARTCLKGS_CLK_EN_AM_UART1 0x00000002 +#define PRCM_UARTCLKGS_CLK_EN_AM_UART0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGDS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by UARTCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// AM_UART1 Enable clock for UART1 +// AM_UART0 Enable clock for UART0 +#define PRCM_UARTCLKGDS_CLK_EN_W 2 +#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000003 +#define PRCM_UARTCLKGDS_CLK_EN_S 0 +#define PRCM_UARTCLKGDS_CLK_EN_AM_UART1 0x00000002 +#define PRCM_UARTCLKGDS_CLK_EN_AM_UART0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGR +// +//***************************************************************************** +// Field: [9:8] AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CLK_EN, SSICLKGS.CLK_EN and SSICLKGDS.CLK_EN when enabled. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGR_AM_CLK_EN_W 2 +#define PRCM_SSICLKGR_AM_CLK_EN_M 0x00000300 +#define PRCM_SSICLKGR_AM_CLK_EN_S 8 +#define PRCM_SSICLKGR_AM_CLK_EN_SSI1 0x00000200 +#define PRCM_SSICLKGR_AM_CLK_EN_SSI0 0x00000100 + +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGR_CLK_EN_W 2 +#define PRCM_SSICLKGR_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGR_CLK_EN_S 0 +#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SSICLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGS_CLK_EN_W 2 +#define PRCM_SSICLKGS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGS_CLK_EN_S 0 +#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGDS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SSICLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGDS_CLK_EN_W 2 +#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGDS_CLK_EN_S 0 +#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGR +// +//***************************************************************************** +// Field: [8] AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CLK_EN, I2SCLKGS.CLK_EN and I2SCLKGDS.CLK_EN when enabled. +// SYSBUS clock will always run when enabled +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGR_AM_CLK_EN 0x00000100 +#define PRCM_I2SCLKGR_AM_CLK_EN_BITN 8 +#define PRCM_I2SCLKGR_AM_CLK_EN_M 0x00000100 +#define PRCM_I2SCLKGR_AM_CLK_EN_S 8 + +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGR_CLK_EN 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_BITN 0 +#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by I2SCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// SYSBUS clock will always run when enabled +// +// Can be forced on by I2SCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SYSBUSCLKDIV +// +//***************************************************************************** +// Field: [2:0] RATIO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DIV2 Internal. Only to be used through TI provided API. +// DIV1 Internal. Only to be used through TI provided API. +#define PRCM_SYSBUSCLKDIV_RATIO_W 3 +#define PRCM_SYSBUSCLKDIV_RATIO_M 0x00000007 +#define PRCM_SYSBUSCLKDIV_RATIO_S 0 +#define PRCM_SYSBUSCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_SYSBUSCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_CPUCLKDIV +// +//***************************************************************************** +// Field: [0] RATIO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DIV2 Internal. Only to be used through TI provided API. +// DIV1 Internal. Only to be used through TI provided API. +#define PRCM_CPUCLKDIV_RATIO 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_BITN 0 +#define PRCM_CPUCLKDIV_RATIO_M 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_S 0 +#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_PERBUSCPUCLKDIV +// +//***************************************************************************** +// Field: [3:0] RATIO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DIV256 Internal. Only to be used through TI provided API. +// DIV128 Internal. Only to be used through TI provided API. +// DIV64 Internal. Only to be used through TI provided API. +// DIV32 Internal. Only to be used through TI provided API. +// DIV16 Internal. Only to be used through TI provided API. +// DIV8 Internal. Only to be used through TI provided API. +// DIV4 Internal. Only to be used through TI provided API. +// DIV2 Internal. Only to be used through TI provided API. +// DIV1 Internal. Only to be used through TI provided API. +#define PRCM_PERBUSCPUCLKDIV_RATIO_W 4 +#define PRCM_PERBUSCPUCLKDIV_RATIO_M 0x0000000F +#define PRCM_PERBUSCPUCLKDIV_RATIO_S 0 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_PERDMACLKDIV +// +//***************************************************************************** +// Field: [3:0] RATIO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DIV256 Internal. Only to be used through TI provided API. +// DIV128 Internal. Only to be used through TI provided API. +// DIV64 Internal. Only to be used through TI provided API. +// DIV32 Internal. Only to be used through TI provided API. +// DIV16 Internal. Only to be used through TI provided API. +// DIV8 Internal. Only to be used through TI provided API. +// DIV4 Internal. Only to be used through TI provided API. +// DIV2 Internal. Only to be used through TI provided API. +// DIV1 Internal. Only to be used through TI provided API. +#define PRCM_PERDMACLKDIV_RATIO_W 4 +#define PRCM_PERDMACLKDIV_RATIO_M 0x0000000F +#define PRCM_PERDMACLKDIV_RATIO_S 0 +#define PRCM_PERDMACLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_PERDMACLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_PERDMACLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_PERDMACLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_PERDMACLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_PERDMACLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_PERDMACLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_PERDMACLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_PERDMACLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_I2SBCLKSEL +// +//***************************************************************************** +// Field: [0] SRC +// +// BCLK source selector +// +// 0: Use external BCLK +// 1: Use internally generated clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SBCLKSEL_SRC 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_BITN 0 +#define PRCM_I2SBCLKSEL_SRC_M 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKDIV +// +//***************************************************************************** +// Field: [3:0] RATIO +// +// Scalar used for GPTs. The division rate will be constant and ungated for Run +// / Sleep / DeepSleep mode. For changes to take effect, CLKLOADCTL.LOAD +// needs to be written Other values are not supported. +// ENUMs: +// DIV256 Divide by 256 +// DIV128 Divide by 128 +// DIV64 Divide by 64 +// DIV32 Divide by 32 +// DIV16 Divide by 16 +// DIV8 Divide by 8 +// DIV4 Divide by 4 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_GPTCLKDIV_RATIO_W 4 +#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F +#define PRCM_GPTCLKDIV_RATIO_S 0 +#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKCTL +// +//***************************************************************************** +// Field: [3] SMPL_ON_POSEDGE +// +// On the I2S serial interface, data and WCLK is sampled and clocked out on +// opposite edges of BCLK. +// +// 0 - data and WCLK are sampled on the negative edge and clocked out on the +// positive edge. +// 1 - data and WCLK are sampled on the positive edge and clocked out on the +// negative edge. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 + +// Field: [2:1] WCLK_PHASE +// +// Decides how the WCLK division ratio is calculated and used to generate +// different duty cycles (See I2SWCLKDIV.WDIV). +// +// 0: Single phase +// 1: Dual phase +// 2: User Defined +// 3: Reserved/Undefined +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 +#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 +#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 + +// Field: [0] EN +// +// +// 0: MCLK, BCLK and WCLK will be static low +// 1: Enables the generation of MCLK, BCLK and WCLK +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_EN 0x00000001 +#define PRCM_I2SCLKCTL_EN_BITN 0 +#define PRCM_I2SCLKCTL_EN_M 0x00000001 +#define PRCM_I2SCLKCTL_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SMCLKDIV +// +//***************************************************************************** +// Field: [9:0] MDIV +// +// An unsigned factor of the division ratio used to generate MCLK [2-1024]: +// +// MCLK = MCUCLK/MDIV[Hz] +// MCUCLK is 48MHz. +// +// A value of 0 is interpreted as 1024. +// A value of 1 is invalid. +// If MDIV is odd the low phase of the clock is one MCUCLK period longer than +// the high phase. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SMCLKDIV_MDIV_W 10 +#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF +#define PRCM_I2SMCLKDIV_MDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SBCLKDIV +// +//***************************************************************************** +// Field: [9:0] BDIV +// +// An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: +// +// BCLK = MCUCLK/BDIV[Hz] +// MCUCLK is 48MHz. +// +// A value of 0 is interpreted as 1024. +// A value of 1 is invalid. +// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock +// is one MCUCLK period longer than the high phase. +// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the +// clock is one MCUCLK period longer than the low phase. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SBCLKDIV_BDIV_W 10 +#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF +#define PRCM_I2SBCLKDIV_BDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SWCLKDIV +// +//***************************************************************************** +// Field: [15:0] WDIV +// +// If I2SCLKCTL.WCLK_PHASE = 0, Single phase. +// WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK +// periods. +// +// WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] +// MCUCLK is 48MHz. +// +// If I2SCLKCTL.WCLK_PHASE = 1, Dual phase. +// Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK +// periods. +// +// WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] +// +// If I2SCLKCTL.WCLK_PHASE = 2, User defined. +// WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] +// (unsigned, [1-255]) BCLK periods. +// +// WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SWCLKDIV_WDIV_W 16 +#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF +#define PRCM_I2SWCLKDIV_WDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETSECDMA +// +//***************************************************************************** +// Field: [8] DMA +// +// Write 1 to reset. HW cleared. +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETSECDMA_DMA 0x00000100 +#define PRCM_RESETSECDMA_DMA_BITN 8 +#define PRCM_RESETSECDMA_DMA_M 0x00000100 +#define PRCM_RESETSECDMA_DMA_S 8 + +// Field: [2] PKA +// +// Write 1 to reset. HW cleared. +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETSECDMA_PKA 0x00000004 +#define PRCM_RESETSECDMA_PKA_BITN 2 +#define PRCM_RESETSECDMA_PKA_M 0x00000004 +#define PRCM_RESETSECDMA_PKA_S 2 + +// Field: [1] TRNG +// +// Write 1 to reset. HW cleared. +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETSECDMA_TRNG 0x00000002 +#define PRCM_RESETSECDMA_TRNG_BITN 1 +#define PRCM_RESETSECDMA_TRNG_M 0x00000002 +#define PRCM_RESETSECDMA_TRNG_S 1 + +// Field: [0] CRYPTO +// +// Write 1 to reset. HW cleared. +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETSECDMA_CRYPTO 0x00000001 +#define PRCM_RESETSECDMA_CRYPTO_BITN 0 +#define PRCM_RESETSECDMA_CRYPTO_M 0x00000001 +#define PRCM_RESETSECDMA_CRYPTO_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETGPIO +// +//***************************************************************************** +// Field: [0] GPIO +// +// +// 0: No action +// 1: Reset GPIO. HW cleared. +// +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETGPIO_GPIO 0x00000001 +#define PRCM_RESETGPIO_GPIO_BITN 0 +#define PRCM_RESETGPIO_GPIO_M 0x00000001 +#define PRCM_RESETGPIO_GPIO_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETGPT +// +//***************************************************************************** +// Field: [0] GPT +// +// +// 0: No action +// 1: Reset all GPTs. HW cleared. +// +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETGPT_GPT 0x00000001 +#define PRCM_RESETGPT_GPT_BITN 0 +#define PRCM_RESETGPT_GPT_M 0x00000001 +#define PRCM_RESETGPT_GPT_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETI2C +// +//***************************************************************************** +// Field: [0] I2C +// +// +// 0: No action +// 1: Reset I2C. HW cleared. +// +// Acess will only have effect when SERIAL power domain is on, +// PDSTAT0.SERIAL_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETI2C_I2C 0x00000001 +#define PRCM_RESETI2C_I2C_BITN 0 +#define PRCM_RESETI2C_I2C_M 0x00000001 +#define PRCM_RESETI2C_I2C_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETUART +// +//***************************************************************************** +// Field: [1] UART1 +// +// +// 0: No action +// 1: Reset UART1. HW cleared. +// +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETUART_UART1 0x00000002 +#define PRCM_RESETUART_UART1_BITN 1 +#define PRCM_RESETUART_UART1_M 0x00000002 +#define PRCM_RESETUART_UART1_S 1 + +// Field: [0] UART0 +// +// +// 0: No action +// 1: Reset UART0. HW cleared. +// +// Acess will only have effect when SERIAL power domain is on, +// PDSTAT0.SERIAL_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETUART_UART0 0x00000001 +#define PRCM_RESETUART_UART0_BITN 0 +#define PRCM_RESETUART_UART0_M 0x00000001 +#define PRCM_RESETUART_UART0_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETSSI +// +//***************************************************************************** +// Field: [1:0] SSI +// +// SSI 0: +// +// 0: No action +// 1: Reset SSI. HW cleared. +// +// Acess will only have effect when SERIAL power domain is on, +// PDSTAT0.SERIAL_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +// +// SSI 1: +// +// 0: No action +// 1: Reset SSI. HW cleared. +// +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETSSI_SSI_W 2 +#define PRCM_RESETSSI_SSI_M 0x00000003 +#define PRCM_RESETSSI_SSI_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETI2S +// +//***************************************************************************** +// Field: [0] I2S +// +// +// 0: No action +// 1: Reset module. HW cleared. +// +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETI2S_I2S 0x00000001 +#define PRCM_RESETI2S_I2S_BITN 0 +#define PRCM_RESETI2S_I2S_M 0x00000001 +#define PRCM_RESETI2S_I2S_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0 +// +//***************************************************************************** +// Field: [2] PERIPH_ON +// +// PERIPH Power domain. +// +// 0: PERIPH power domain is powered down +// 1: PERIPH power domain is powered up +#define PRCM_PDCTL0_PERIPH_ON 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_BITN 2 +#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_S 2 + +// Field: [1] SERIAL_ON +// +// SERIAL Power domain. +// +// 0: SERIAL power domain is powered down +// 1: SERIAL power domain is powered up +#define PRCM_PDCTL0_SERIAL_ON 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_BITN 1 +#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_S 1 + +// Field: [0] RFC_ON +// +// +// 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 +// 1: RFC power domain powered on +#define PRCM_PDCTL0_RFC_ON 0x00000001 +#define PRCM_PDCTL0_RFC_ON_BITN 0 +#define PRCM_PDCTL0_RFC_ON_M 0x00000001 +#define PRCM_PDCTL0_RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0RFC +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.RFC_ON +#define PRCM_PDCTL0RFC_ON 0x00000001 +#define PRCM_PDCTL0RFC_ON_BITN 0 +#define PRCM_PDCTL0RFC_ON_M 0x00000001 +#define PRCM_PDCTL0RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0SERIAL +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.SERIAL_ON +#define PRCM_PDCTL0SERIAL_ON 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_BITN 0 +#define PRCM_PDCTL0SERIAL_ON_M 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0PERIPH +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.PERIPH_ON +#define PRCM_PDCTL0PERIPH_ON 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_BITN 0 +#define PRCM_PDCTL0PERIPH_ON_M 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0 +// +//***************************************************************************** +// Field: [2] PERIPH_ON +// +// PERIPH Power domain. +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_PERIPH_ON 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_BITN 2 +#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_S 2 + +// Field: [1] SERIAL_ON +// +// SERIAL Power domain. +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_SERIAL_ON 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_BITN 1 +#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_S 1 + +// Field: [0] RFC_ON +// +// RFC Power domain +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_RFC_ON 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_BITN 0 +#define PRCM_PDSTAT0_RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0RFC +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.RFC_ON +#define PRCM_PDSTAT0RFC_ON 0x00000001 +#define PRCM_PDSTAT0RFC_ON_BITN 0 +#define PRCM_PDSTAT0RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0SERIAL +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.SERIAL_ON +#define PRCM_PDSTAT0SERIAL_ON 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_BITN 0 +#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0PERIPH +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.PERIPH_ON +#define PRCM_PDSTAT0PERIPH_ON 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_BITN 0 +#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1 +// +//***************************************************************************** +// Field: [4:3] VIMS_MODE +// +// +// 00: VIMS power domain is only powered when CPU power domain is powered. +// 01: VIMS power domain is powered whenever the BUS power domain is powered. +// 1X: Block power up of VIMS power domain at next wake up. This mode only has +// effect when VIMS power domain is not powered. Used for Autonomous RF Core. +#define PRCM_PDCTL1_VIMS_MODE_W 2 +#define PRCM_PDCTL1_VIMS_MODE_M 0x00000018 +#define PRCM_PDCTL1_VIMS_MODE_S 3 + +// Field: [2] RFC_ON +// +// 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1: RFC power +// domain powered on Bit shall be used by RFC in autonomous mode but there is +// no HW restrictions fom system CPU to access the bit. +#define PRCM_PDCTL1_RFC_ON 0x00000004 +#define PRCM_PDCTL1_RFC_ON_BITN 2 +#define PRCM_PDCTL1_RFC_ON_M 0x00000004 +#define PRCM_PDCTL1_RFC_ON_S 2 + +// Field: [1] CPU_ON +// +// +// 0: Causes a power down of the CPU power domain when system CPU indicates it +// is idle. +// 1: Initiates power-on of the CPU power domain. +// +// This bit is automatically set by a WIC power-on event. +#define PRCM_PDCTL1_CPU_ON 0x00000002 +#define PRCM_PDCTL1_CPU_ON_BITN 1 +#define PRCM_PDCTL1_CPU_ON_M 0x00000002 +#define PRCM_PDCTL1_CPU_ON_S 1 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1CPU +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDCTL1.CPU_ON +#define PRCM_PDCTL1CPU_ON 0x00000001 +#define PRCM_PDCTL1CPU_ON_BITN 0 +#define PRCM_PDCTL1CPU_ON_M 0x00000001 +#define PRCM_PDCTL1CPU_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1RFC +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDCTL1.RFC_ON +#define PRCM_PDCTL1RFC_ON 0x00000001 +#define PRCM_PDCTL1RFC_ON_BITN 0 +#define PRCM_PDCTL1RFC_ON_M 0x00000001 +#define PRCM_PDCTL1RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1VIMS +// +//***************************************************************************** +// Field: [1:0] MODE +// +// This is an alias for PDCTL1.VIMS_MODE +#define PRCM_PDCTL1VIMS_MODE_W 2 +#define PRCM_PDCTL1VIMS_MODE_M 0x00000003 +#define PRCM_PDCTL1VIMS_MODE_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1 +// +//***************************************************************************** +// Field: [4] BUS_ON +// +// +// 0: BUS domain not accessible +// 1: BUS domain is currently accessible +#define PRCM_PDSTAT1_BUS_ON 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_BITN 4 +#define PRCM_PDSTAT1_BUS_ON_M 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_S 4 + +// Field: [3] VIMS_ON +// +// +// 0: VIMS domain not accessible +// 1: VIMS domain is currently accessible +#define PRCM_PDSTAT1_VIMS_ON 0x00000008 +#define PRCM_PDSTAT1_VIMS_ON_BITN 3 +#define PRCM_PDSTAT1_VIMS_ON_M 0x00000008 +#define PRCM_PDSTAT1_VIMS_ON_S 3 + +// Field: [2] RFC_ON +// +// +// 0: RFC domain not accessible +// 1: RFC domain is currently accessible +#define PRCM_PDSTAT1_RFC_ON 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_BITN 2 +#define PRCM_PDSTAT1_RFC_ON_M 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_S 2 + +// Field: [1] CPU_ON +// +// +// 0: CPU and BUS domain not accessible +// 1: CPU and BUS domains are both currently accessible +#define PRCM_PDSTAT1_CPU_ON 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_BITN 1 +#define PRCM_PDSTAT1_CPU_ON_M 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_S 1 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1BUS +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.BUS_ON +#define PRCM_PDSTAT1BUS_ON 0x00000001 +#define PRCM_PDSTAT1BUS_ON_BITN 0 +#define PRCM_PDSTAT1BUS_ON_M 0x00000001 +#define PRCM_PDSTAT1BUS_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1RFC +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.RFC_ON +#define PRCM_PDSTAT1RFC_ON 0x00000001 +#define PRCM_PDSTAT1RFC_ON_BITN 0 +#define PRCM_PDSTAT1RFC_ON_M 0x00000001 +#define PRCM_PDSTAT1RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1CPU +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.CPU_ON +#define PRCM_PDSTAT1CPU_ON 0x00000001 +#define PRCM_PDSTAT1CPU_ON_BITN 0 +#define PRCM_PDSTAT1CPU_ON_M 0x00000001 +#define PRCM_PDSTAT1CPU_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1VIMS +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.VIMS_ON +#define PRCM_PDSTAT1VIMS_ON 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_BITN 0 +#define PRCM_PDSTAT1VIMS_ON_M 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCBITS +// +//***************************************************************************** +// Field: [31:0] READ +// +// Control bits for RFC. The RF core CPE processor will automatically check +// this register when it boots, and it can be used to immediately instruct CPE +// to perform some tasks at its start-up. The supported functionality is +// ROM-defined and may vary. See the technical reference manual for more +// details. +#define PRCM_RFCBITS_READ_W 32 +#define PRCM_RFCBITS_READ_M 0xFFFFFFFF +#define PRCM_RFCBITS_READ_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCMODESEL +// +//***************************************************************************** +// Field: [2:0] CURR +// +// Selects the set of commands that the RFC will accept. Only modes permitted +// by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for +// details. +// ENUMs: +// MODE7 Select Mode 7 +// MODE6 Select Mode 6 +// MODE5 Select Mode 5 +// MODE4 Select Mode 4 +// MODE3 Select Mode 3 +// MODE2 Select Mode 2 +// MODE1 Select Mode 1 +// MODE0 Select Mode 0 +#define PRCM_RFCMODESEL_CURR_W 3 +#define PRCM_RFCMODESEL_CURR_M 0x00000007 +#define PRCM_RFCMODESEL_CURR_S 0 +#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 +#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 +#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 +#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 +#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 +#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 +#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 +#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_RFCMODEHWOPT +// +//***************************************************************************** +// Field: [7:0] AVAIL +// +// Permitted RFC modes. More than one mode can be permitted. +// ENUMs: +// MODE7 Mode 7 permitted +// MODE6 Mode 6 permitted +// MODE5 Mode 5 permitted +// MODE4 Mode 4 permitted +// MODE3 Mode 3 permitted +// MODE2 Mode 2 permitted +// MODE1 Mode 1 permitted +// MODE0 Mode 0 permitted +#define PRCM_RFCMODEHWOPT_AVAIL_W 8 +#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF +#define PRCM_RFCMODEHWOPT_AVAIL_S 0 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_PWRPROFSTAT +// +//***************************************************************************** +// Field: [7:0] VALUE +// +// SW can use these bits to timestamp the application. These bits are also +// available through the testtap and can thus be used by the emulator to +// profile in real time. +#define PRCM_PWRPROFSTAT_VALUE_W 8 +#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF +#define PRCM_PWRPROFSTAT_VALUE_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_MCUSRAMCFG +// +//***************************************************************************** +// Field: [5] BM_OFF +// +// Burst Mode disable +// +// 0: Burst Mode enabled. +// 1: Burst Mode off. +#define PRCM_MCUSRAMCFG_BM_OFF 0x00000020 +#define PRCM_MCUSRAMCFG_BM_OFF_BITN 5 +#define PRCM_MCUSRAMCFG_BM_OFF_M 0x00000020 +#define PRCM_MCUSRAMCFG_BM_OFF_S 5 + +// Field: [4] PAGE +// +// Page Mode select +// +// 0: Page Mode disabled. Memory works in standard mode +// 1: Page Mode enabled. Only one half of butterfly array selected. Page Mode +// will select either LSB half or MSB half of the word based on PGS setting. +// +// This mode can be used for additional power saving +#define PRCM_MCUSRAMCFG_PAGE 0x00000010 +#define PRCM_MCUSRAMCFG_PAGE_BITN 4 +#define PRCM_MCUSRAMCFG_PAGE_M 0x00000010 +#define PRCM_MCUSRAMCFG_PAGE_S 4 + +// Field: [3] PGS +// +// 0: Select LSB half of word during Page Mode, PAGE = 1 +// 1: Select MSB half of word during Page Mode, PAGE = 1 +#define PRCM_MCUSRAMCFG_PGS 0x00000008 +#define PRCM_MCUSRAMCFG_PGS_BITN 3 +#define PRCM_MCUSRAMCFG_PGS_M 0x00000008 +#define PRCM_MCUSRAMCFG_PGS_S 3 + +// Field: [2] BM +// +// Burst Mode Enable +// +// 0: Burst Mode Disable. Memory works in standard mode. +// 1: Burst Mode Enable +// +// When in Burst Mode bitline precharge and wordline firing depends on PCH_F +// and PCH_L. +// Burst Mode results in reduction in active power. +#define PRCM_MCUSRAMCFG_BM 0x00000004 +#define PRCM_MCUSRAMCFG_BM_BITN 2 +#define PRCM_MCUSRAMCFG_BM_M 0x00000004 +#define PRCM_MCUSRAMCFG_BM_S 2 + +// Field: [1] PCH_F +// +// 0: No bitline precharge in second half of cycle +// 1: Bitline precharge in second half of cycle when in Burst Mode, BM = 1 +#define PRCM_MCUSRAMCFG_PCH_F 0x00000002 +#define PRCM_MCUSRAMCFG_PCH_F_BITN 1 +#define PRCM_MCUSRAMCFG_PCH_F_M 0x00000002 +#define PRCM_MCUSRAMCFG_PCH_F_S 1 + +// Field: [0] PCH_L +// +// 0: No bitline precharge in first half of cycle +// 1: Bitline precharge in first half of cycle when in Burst Mode, BM = 1 +#define PRCM_MCUSRAMCFG_PCH_L 0x00000001 +#define PRCM_MCUSRAMCFG_PCH_L_BITN 0 +#define PRCM_MCUSRAMCFG_PCH_L_M 0x00000001 +#define PRCM_MCUSRAMCFG_PCH_L_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RAMRETEN +// +//***************************************************************************** +// Field: [3] RFCULL +// +// 0: Retention for RFC ULL SRAM disabled +// 1: Retention for RFC ULL SRAM enabled +// +// Memories controlled: +// CPEULLRAM +#define PRCM_RAMRETEN_RFCULL 0x00000008 +#define PRCM_RAMRETEN_RFCULL_BITN 3 +#define PRCM_RAMRETEN_RFCULL_M 0x00000008 +#define PRCM_RAMRETEN_RFCULL_S 3 + +// Field: [2] RFC +// +// 0: Retention for RFC SRAM disabled +// 1: Retention for RFC SRAM enabled +// +// Memories controlled: CPERAM MCERAM RFERAM DSBRAM +#define PRCM_RAMRETEN_RFC 0x00000004 +#define PRCM_RAMRETEN_RFC_BITN 2 +#define PRCM_RAMRETEN_RFC_M 0x00000004 +#define PRCM_RAMRETEN_RFC_S 2 + +// Field: [1:0] VIMS +// +// +// 0: Memory retention disabled +// 1: Memory retention enabled +// +// Bit 0: VIMS_TRAM +// Bit 1: VIMS_CRAM +// +// Legal modes depend on settings in VIMS:CTL.MODE +// +// 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to +// CACHE or SPLIT mode after waking up again +// 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in +// GPRAM mode after wake up, alternatively select OFF mode first and then CACHE +// or SPILT mode. +// 10: Illegal mode +// 11: No restrictions +#define PRCM_RAMRETEN_VIMS_W 2 +#define PRCM_RAMRETEN_VIMS_M 0x00000003 +#define PRCM_RAMRETEN_VIMS_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_OSCIMSC +// +//***************************************************************************** +// Field: [7] HFSRCPENDIM +// +// 0: Disable interrupt generation when HFSRCPEND is qualified +// 1: Enable interrupt generation when HFSRCPEND is qualified +#define PRCM_OSCIMSC_HFSRCPENDIM 0x00000080 +#define PRCM_OSCIMSC_HFSRCPENDIM_BITN 7 +#define PRCM_OSCIMSC_HFSRCPENDIM_M 0x00000080 +#define PRCM_OSCIMSC_HFSRCPENDIM_S 7 + +// Field: [6] LFSRCDONEIM +// +// 0: Disable interrupt generation when LFSRCDONE is qualified +// 1: Enable interrupt generation when LFSRCDONE is qualified +#define PRCM_OSCIMSC_LFSRCDONEIM 0x00000040 +#define PRCM_OSCIMSC_LFSRCDONEIM_BITN 6 +#define PRCM_OSCIMSC_LFSRCDONEIM_M 0x00000040 +#define PRCM_OSCIMSC_LFSRCDONEIM_S 6 + +// Field: [5] XOSCDLFIM +// +// 0: Disable interrupt generation when XOSCDLF is qualified +// 1: Enable interrupt generation when XOSCDLF is qualified +#define PRCM_OSCIMSC_XOSCDLFIM 0x00000020 +#define PRCM_OSCIMSC_XOSCDLFIM_BITN 5 +#define PRCM_OSCIMSC_XOSCDLFIM_M 0x00000020 +#define PRCM_OSCIMSC_XOSCDLFIM_S 5 + +// Field: [4] XOSCLFIM +// +// 0: Disable interrupt generation when XOSCLF is qualified +// 1: Enable interrupt generation when XOSCLF is qualified +#define PRCM_OSCIMSC_XOSCLFIM 0x00000010 +#define PRCM_OSCIMSC_XOSCLFIM_BITN 4 +#define PRCM_OSCIMSC_XOSCLFIM_M 0x00000010 +#define PRCM_OSCIMSC_XOSCLFIM_S 4 + +// Field: [3] RCOSCDLFIM +// +// 0: Disable interrupt generation when RCOSCDLF is qualified +// 1: Enable interrupt generation when RCOSCDLF is qualified +#define PRCM_OSCIMSC_RCOSCDLFIM 0x00000008 +#define PRCM_OSCIMSC_RCOSCDLFIM_BITN 3 +#define PRCM_OSCIMSC_RCOSCDLFIM_M 0x00000008 +#define PRCM_OSCIMSC_RCOSCDLFIM_S 3 + +// Field: [2] RCOSCLFIM +// +// 0: Disable interrupt generation when RCOSCLF is qualified +// 1: Enable interrupt generation when RCOSCLF is qualified +#define PRCM_OSCIMSC_RCOSCLFIM 0x00000004 +#define PRCM_OSCIMSC_RCOSCLFIM_BITN 2 +#define PRCM_OSCIMSC_RCOSCLFIM_M 0x00000004 +#define PRCM_OSCIMSC_RCOSCLFIM_S 2 + +// Field: [1] XOSCHFIM +// +// 0: Disable interrupt generation when XOSCHF is qualified +// 1: Enable interrupt generation when XOSCHF is qualified +#define PRCM_OSCIMSC_XOSCHFIM 0x00000002 +#define PRCM_OSCIMSC_XOSCHFIM_BITN 1 +#define PRCM_OSCIMSC_XOSCHFIM_M 0x00000002 +#define PRCM_OSCIMSC_XOSCHFIM_S 1 + +// Field: [0] RCOSCHFIM +// +// 0: Disable interrupt generation when RCOSCHF is qualified +// 1: Enable interrupt generation when RCOSCHF is qualified +#define PRCM_OSCIMSC_RCOSCHFIM 0x00000001 +#define PRCM_OSCIMSC_RCOSCHFIM_BITN 0 +#define PRCM_OSCIMSC_RCOSCHFIM_M 0x00000001 +#define PRCM_OSCIMSC_RCOSCHFIM_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_OSCRIS +// +//***************************************************************************** +// Field: [7] HFSRCPENDRIS +// +// 0: HFSRCPEND has not been qualified +// 1: HFSRCPEND has been qualified since last clear +// +// Interrupt is qualified regardless of OSCIMSC.HFSRCPENDIM setting. The order +// of qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.HFSRCPENDC +#define PRCM_OSCRIS_HFSRCPENDRIS 0x00000080 +#define PRCM_OSCRIS_HFSRCPENDRIS_BITN 7 +#define PRCM_OSCRIS_HFSRCPENDRIS_M 0x00000080 +#define PRCM_OSCRIS_HFSRCPENDRIS_S 7 + +// Field: [6] LFSRCDONERIS +// +// 0: LFSRCDONE has not been qualified +// 1: LFSRCDONE has been qualified since last clear +// +// Interrupt is qualified regardless of OSCIMSC.LFSRCDONEIM setting. The order +// of qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.LFSRCDONEC +#define PRCM_OSCRIS_LFSRCDONERIS 0x00000040 +#define PRCM_OSCRIS_LFSRCDONERIS_BITN 6 +#define PRCM_OSCRIS_LFSRCDONERIS_M 0x00000040 +#define PRCM_OSCRIS_LFSRCDONERIS_S 6 + +// Field: [5] XOSCDLFRIS +// +// 0: XOSCDLF has not been qualified +// 1: XOSCDLF has been qualified since last clear. +// +// Interrupt is qualified regardless of OSCIMSC.XOSCDLFIM setting. The order of +// qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.XOSCDLFC +#define PRCM_OSCRIS_XOSCDLFRIS 0x00000020 +#define PRCM_OSCRIS_XOSCDLFRIS_BITN 5 +#define PRCM_OSCRIS_XOSCDLFRIS_M 0x00000020 +#define PRCM_OSCRIS_XOSCDLFRIS_S 5 + +// Field: [4] XOSCLFRIS +// +// 0: XOSCLF has not been qualified +// 1: XOSCLF has been qualified since last clear. +// +// Interrupt is qualified regardless of OSCIMSC.XOSCLFIM setting. The order of +// qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.XOSCLFC +#define PRCM_OSCRIS_XOSCLFRIS 0x00000010 +#define PRCM_OSCRIS_XOSCLFRIS_BITN 4 +#define PRCM_OSCRIS_XOSCLFRIS_M 0x00000010 +#define PRCM_OSCRIS_XOSCLFRIS_S 4 + +// Field: [3] RCOSCDLFRIS +// +// 0: RCOSCDLF has not been qualified +// 1: RCOSCDLF has been qualified since last clear. +// +// Interrupt is qualified regardless of OSCIMSC.RCOSCDLFIM setting. The order +// of qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.RCOSCDLFC +#define PRCM_OSCRIS_RCOSCDLFRIS 0x00000008 +#define PRCM_OSCRIS_RCOSCDLFRIS_BITN 3 +#define PRCM_OSCRIS_RCOSCDLFRIS_M 0x00000008 +#define PRCM_OSCRIS_RCOSCDLFRIS_S 3 + +// Field: [2] RCOSCLFRIS +// +// 0: RCOSCLF has not been qualified +// 1: RCOSCLF has been qualified since last clear. +// +// Interrupt is qualified regardless of OSCIMSC.RCOSCLFIM setting. The order of +// qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.RCOSCLFC +#define PRCM_OSCRIS_RCOSCLFRIS 0x00000004 +#define PRCM_OSCRIS_RCOSCLFRIS_BITN 2 +#define PRCM_OSCRIS_RCOSCLFRIS_M 0x00000004 +#define PRCM_OSCRIS_RCOSCLFRIS_S 2 + +// Field: [1] XOSCHFRIS +// +// 0: XOSCHF has not been qualified +// 1: XOSCHF has been qualified since last clear. +// +// Interrupt is qualified regardless of OSCIMSC.XOSCHFIM setting. The order of +// qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.XOSCHFC +#define PRCM_OSCRIS_XOSCHFRIS 0x00000002 +#define PRCM_OSCRIS_XOSCHFRIS_BITN 1 +#define PRCM_OSCRIS_XOSCHFRIS_M 0x00000002 +#define PRCM_OSCRIS_XOSCHFRIS_S 1 + +// Field: [0] RCOSCHFRIS +// +// 0: RCOSCHF has not been qualified +// 1: RCOSCHF has been qualified since last clear. +// +// Interrupt is qualified regardless of OSCIMSC.RCOSCHFIM setting. The order of +// qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.RCOSCHFC +#define PRCM_OSCRIS_RCOSCHFRIS 0x00000001 +#define PRCM_OSCRIS_RCOSCHFRIS_BITN 0 +#define PRCM_OSCRIS_RCOSCHFRIS_M 0x00000001 +#define PRCM_OSCRIS_RCOSCHFRIS_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_OSCICR +// +//***************************************************************************** +// Field: [7] HFSRCPENDC +// +// Writing 1 to this field clears the HFSRCPEND raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_HFSRCPENDC 0x00000080 +#define PRCM_OSCICR_HFSRCPENDC_BITN 7 +#define PRCM_OSCICR_HFSRCPENDC_M 0x00000080 +#define PRCM_OSCICR_HFSRCPENDC_S 7 + +// Field: [6] LFSRCDONEC +// +// Writing 1 to this field clears the LFSRCDONE raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_LFSRCDONEC 0x00000040 +#define PRCM_OSCICR_LFSRCDONEC_BITN 6 +#define PRCM_OSCICR_LFSRCDONEC_M 0x00000040 +#define PRCM_OSCICR_LFSRCDONEC_S 6 + +// Field: [5] XOSCDLFC +// +// Writing 1 to this field clears the XOSCDLF raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_XOSCDLFC 0x00000020 +#define PRCM_OSCICR_XOSCDLFC_BITN 5 +#define PRCM_OSCICR_XOSCDLFC_M 0x00000020 +#define PRCM_OSCICR_XOSCDLFC_S 5 + +// Field: [4] XOSCLFC +// +// Writing 1 to this field clears the XOSCLF raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_XOSCLFC 0x00000010 +#define PRCM_OSCICR_XOSCLFC_BITN 4 +#define PRCM_OSCICR_XOSCLFC_M 0x00000010 +#define PRCM_OSCICR_XOSCLFC_S 4 + +// Field: [3] RCOSCDLFC +// +// Writing 1 to this field clears the RCOSCDLF raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_RCOSCDLFC 0x00000008 +#define PRCM_OSCICR_RCOSCDLFC_BITN 3 +#define PRCM_OSCICR_RCOSCDLFC_M 0x00000008 +#define PRCM_OSCICR_RCOSCDLFC_S 3 + +// Field: [2] RCOSCLFC +// +// Writing 1 to this field clears the RCOSCLF raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_RCOSCLFC 0x00000004 +#define PRCM_OSCICR_RCOSCLFC_BITN 2 +#define PRCM_OSCICR_RCOSCLFC_M 0x00000004 +#define PRCM_OSCICR_RCOSCLFC_S 2 + +// Field: [1] XOSCHFC +// +// Writing 1 to this field clears the XOSCHF raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_XOSCHFC 0x00000002 +#define PRCM_OSCICR_XOSCHFC_BITN 1 +#define PRCM_OSCICR_XOSCHFC_M 0x00000002 +#define PRCM_OSCICR_XOSCHFC_S 1 + +// Field: [0] RCOSCHFC +// +// Writing 1 to this field clears the RCOSCHF raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_RCOSCHFC 0x00000001 +#define PRCM_OSCICR_RCOSCHFC_BITN 0 +#define PRCM_OSCICR_RCOSCHFC_M 0x00000001 +#define PRCM_OSCICR_RCOSCHFC_S 0 + + +#endif // __PRCM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h new file mode 100644 index 0000000..262827d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h @@ -0,0 +1,1672 @@ +/****************************************************************************** +* Filename: hw_rfc_dbell_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_DBELL_H__ +#define __HW_RFC_DBELL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_DBELL component +// +//***************************************************************************** +// Doorbell Command Register +#define RFC_DBELL_O_CMDR 0x00000000 + +// Doorbell Command Status Register +#define RFC_DBELL_O_CMDSTA 0x00000004 + +// Interrupt Flags From RF Hardware Modules +#define RFC_DBELL_O_RFHWIFG 0x00000008 + +// Interrupt Enable For RF Hardware Modules +#define RFC_DBELL_O_RFHWIEN 0x0000000C + +// Interrupt Flags For Command and Packet Engine Generated Interrupts +#define RFC_DBELL_O_RFCPEIFG 0x00000010 + +// Interrupt Enable For Command and Packet Engine Generated Interrupts +#define RFC_DBELL_O_RFCPEIEN 0x00000014 + +// Interrupt Vector Selection For Command and Packet Engine Generated +// Interrupts +#define RFC_DBELL_O_RFCPEISL 0x00000018 + +// Doorbell Command Acknowledgement Interrupt Flag +#define RFC_DBELL_O_RFACKIFG 0x0000001C + +// RF Core General Purpose Output Control +#define RFC_DBELL_O_SYSGPOCTL 0x00000020 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_CMDR +// +//***************************************************************************** +// Field: [31:0] CMD +// +// Command register. Raises an interrupt to the Command and packet engine (CPE) +// upon write. +#define RFC_DBELL_CMDR_CMD_W 32 +#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF +#define RFC_DBELL_CMDR_CMD_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_CMDSTA +// +//***************************************************************************** +// Field: [31:0] STAT +// +// Status of the last command used +#define RFC_DBELL_CMDSTA_STAT_W 32 +#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF +#define RFC_DBELL_CMDSTA_STAT_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFHWIFG +// +//***************************************************************************** +// Field: [19] RATCH7 +// +// Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_S 19 + +// Field: [18] RATCH6 +// +// Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_S 18 + +// Field: [17] RATCH5 +// +// Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_S 17 + +// Field: [16] RATCH4 +// +// Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_S 16 + +// Field: [15] RATCH3 +// +// Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_S 15 + +// Field: [14] RATCH2 +// +// Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_S 14 + +// Field: [13] RATCH1 +// +// Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_S 13 + +// Field: [12] RATCH0 +// +// Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_S 12 + +// Field: [11] RFESOFT2 +// +// RF engine software defined interrupt 2 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 + +// Field: [10] RFESOFT1 +// +// RF engine software defined interrupt 1 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 + +// Field: [9] RFESOFT0 +// +// RF engine software defined interrupt 0 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 + +// Field: [8] RFEDONE +// +// RF engine command done interrupt flag. Write zero to clear flag. Write to +// one has no effect. +#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_S 8 + +// Field: [6] TRCTK +// +// Debug tracer system tick interrupt flag. Write zero to clear flag. Write to +// one has no effect. +#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_S 6 + +// Field: [5] MDMSOFT +// +// Modem software defined interrupt flag. Write zero to clear flag. Write to +// one has no effect. +#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 + +// Field: [4] MDMOUT +// +// Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has +// no effect. +#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_S 4 + +// Field: [3] MDMIN +// +// Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has +// no effect. +#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_S 3 + +// Field: [2] MDMDONE +// +// Modem command done interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_S 2 + +// Field: [1] FSCA +// +// Frequency synthesizer calibration accelerator interrupt flag. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFHWIFG_FSCA 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_BITN 1 +#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_S 1 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFHWIEN +// +//***************************************************************************** +// Field: [19] RATCH7 +// +// Interrupt enable for RFHWIFG.RATCH7. +#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_S 19 + +// Field: [18] RATCH6 +// +// Interrupt enable for RFHWIFG.RATCH6. +#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_S 18 + +// Field: [17] RATCH5 +// +// Interrupt enable for RFHWIFG.RATCH5. +#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_S 17 + +// Field: [16] RATCH4 +// +// Interrupt enable for RFHWIFG.RATCH4. +#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_S 16 + +// Field: [15] RATCH3 +// +// Interrupt enable for RFHWIFG.RATCH3. +#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_S 15 + +// Field: [14] RATCH2 +// +// Interrupt enable for RFHWIFG.RATCH2. +#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_S 14 + +// Field: [13] RATCH1 +// +// Interrupt enable for RFHWIFG.RATCH1. +#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_S 13 + +// Field: [12] RATCH0 +// +// Interrupt enable for RFHWIFG.RATCH0. +#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_S 12 + +// Field: [11] RFESOFT2 +// +// Interrupt enable for RFHWIFG.RFESOFT2. +#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 + +// Field: [10] RFESOFT1 +// +// Interrupt enable for RFHWIFG.RFESOFT1. +#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 + +// Field: [9] RFESOFT0 +// +// Interrupt enable for RFHWIFG.RFESOFT0. +#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 + +// Field: [8] RFEDONE +// +// Interrupt enable for RFHWIFG.RFEDONE. +#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_S 8 + +// Field: [6] TRCTK +// +// Interrupt enable for RFHWIFG.TRCTK. +#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_S 6 + +// Field: [5] MDMSOFT +// +// Interrupt enable for RFHWIFG.MDMSOFT. +#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 + +// Field: [4] MDMOUT +// +// Interrupt enable for RFHWIFG.MDMOUT. +#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_S 4 + +// Field: [3] MDMIN +// +// Interrupt enable for RFHWIFG.MDMIN. +#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_S 3 + +// Field: [2] MDMDONE +// +// Interrupt enable for RFHWIFG.MDMDONE. +#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_S 2 + +// Field: [1] FSCA +// +// Interrupt enable for RFHWIFG.FSCA. +#define RFC_DBELL_RFHWIEN_FSCA 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_BITN 1 +#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_S 1 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEIFG +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Interrupt flag 31. The command and packet engine (CPE) has observed an +// unexpected error. A reset of the CPE is needed. This can be done by +// switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 + +// Field: [30] BOOT_DONE +// +// Interrupt flag 30. The command and packet engine (CPE) boot is finished. +// Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 + +// Field: [29] MODULES_UNLOCKED +// +// Interrupt flag 29. As part of command and packet engine (CPE) boot process, +// it has opened access to RF Core modules and memories. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 + +// Field: [28] SYNTH_NO_LOCK +// +// Interrupt flag 28. The phase-locked loop in frequency synthesizer has +// reported loss of lock. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 + +// Field: [27] IRQ27 +// +// Interrupt flag 27. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_S 27 + +// Field: [26] RX_ABORTED +// +// Interrupt flag 26. Packet reception stopped before packet was done. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Interrupt flag 25. Specified number of bytes written to partial read Rx +// buffer. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 + +// Field: [24] RX_DATA_WRITTEN +// +// Interrupt flag 24. Data written to partial read Rx buffer. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 + +// Field: [23] RX_ENTRY_DONE +// +// Interrupt flag 23. Rx queue data entry changing state to finished. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 + +// Field: [22] RX_BUF_FULL +// +// Interrupt flag 22. Packet received that did not fit in Rx queue. BLE mode: +// Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame +// received that did not fit in the Rx queue. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 + +// Field: [21] RX_CTRL_ACK +// +// Interrupt flag 21. BLE mode only: LL control packet received with CRC OK, +// not to be ignored, then acknowledgement sent. Write zero to clear flag. +// Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 + +// Field: [20] RX_CTRL +// +// Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, +// not to be ignored. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 + +// Field: [19] RX_EMPTY +// +// Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be +// ignored, no payload. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 + +// Field: [18] RX_IGNORED +// +// Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet +// received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received +// with ignore flag set. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 + +// Field: [17] RX_NOK +// +// Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received +// with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 + +// Field: [16] RX_OK +// +// Interrupt flag 16. Packet received correctly. BLE mode: Packet received with +// CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received +// with CRC OK. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_S 16 + +// Field: [15] IRQ15 +// +// Interrupt flag 15. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_S 15 + +// Field: [14] IRQ14 +// +// Interrupt flag 14. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_S 14 + +// Field: [13] FG_COMMAND_STARTED +// +// Interrupt flag 13. IEEE 802.15.4 mode only: A foreground radio operation +// command has gone into active state. +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED 0x00002000 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_BITN 13 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_M 0x00002000 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_S 13 + +// Field: [12] COMMAND_STARTED +// +// Interrupt flag 12. A radio operation command has gone into active state. +#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED 0x00001000 +#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_BITN 12 +#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_M 0x00001000 +#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_S 12 + +// Field: [11] TX_BUFFER_CHANGED +// +// Interrupt flag 11. BLE mode only: A buffer change is complete after +// CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 + +// Field: [10] TX_ENTRY_DONE +// +// Interrupt flag 10. Tx queue data entry state changed to finished. Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 + +// Field: [9] TX_RETRANS +// +// Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted +// LL control packet, and acknowledgement transmitted for that packet. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 + +// Field: [7] TX_CTRL_ACK +// +// Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL +// control packet. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 + +// Field: [6] TX_CTRL +// +// Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 + +// Field: [5] TX_ACK +// +// Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted +// packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 + +// Field: [4] TX_DONE +// +// Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been +// transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio +// operation command in a chain of commands has finished. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 + +// Field: [2] FG_COMMAND_DONE +// +// Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation +// command has finished. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 + +// Field: [1] LAST_COMMAND_DONE +// +// Interrupt flag 1. The last radio operation command in a chain of commands +// has finished. (IEEE 802.15.4 mode: The last background level radio operation +// command in a chain of commands has finished.) Write zero to clear flag. +// Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 + +// Field: [0] COMMAND_DONE +// +// Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A +// background level radio operation command has finished.) Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEIEN +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Interrupt enable for RFCPEIFG.INTERNAL_ERROR. +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 + +// Field: [30] BOOT_DONE +// +// Interrupt enable for RFCPEIFG.BOOT_DONE. +#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 + +// Field: [29] MODULES_UNLOCKED +// +// Interrupt enable for RFCPEIFG.MODULES_UNLOCKED. +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 + +// Field: [28] SYNTH_NO_LOCK +// +// Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK. +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 + +// Field: [27] IRQ27 +// +// Interrupt enable for RFCPEIFG.IRQ27. +#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_S 27 + +// Field: [26] RX_ABORTED +// +// Interrupt enable for RFCPEIFG.RX_ABORTED. +#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN. +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 + +// Field: [24] RX_DATA_WRITTEN +// +// Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN. +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 + +// Field: [23] RX_ENTRY_DONE +// +// Interrupt enable for RFCPEIFG.RX_ENTRY_DONE. +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 + +// Field: [22] RX_BUF_FULL +// +// Interrupt enable for RFCPEIFG.RX_BUF_FULL. +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 + +// Field: [21] RX_CTRL_ACK +// +// Interrupt enable for RFCPEIFG.RX_CTRL_ACK. +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 + +// Field: [20] RX_CTRL +// +// Interrupt enable for RFCPEIFG.RX_CTRL. +#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 + +// Field: [19] RX_EMPTY +// +// Interrupt enable for RFCPEIFG.RX_EMPTY. +#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 + +// Field: [18] RX_IGNORED +// +// Interrupt enable for RFCPEIFG.RX_IGNORED. +#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 + +// Field: [17] RX_NOK +// +// Interrupt enable for RFCPEIFG.RX_NOK. +#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 + +// Field: [16] RX_OK +// +// Interrupt enable for RFCPEIFG.RX_OK. +#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_S 16 + +// Field: [15] IRQ15 +// +// Interrupt enable for RFCPEIFG.IRQ15. +#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_S 15 + +// Field: [14] IRQ14 +// +// Interrupt enable for RFCPEIFG.IRQ14. +#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_S 14 + +// Field: [13] FG_COMMAND_STARTED +// +// Interrupt enable for RFCPEIFG.FG_COMMAND_STARTED. +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED 0x00002000 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_BITN 13 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_M 0x00002000 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_S 13 + +// Field: [12] COMMAND_STARTED +// +// Interrupt enable for RFCPEIFG.COMMAND_STARTED. +#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED 0x00001000 +#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_BITN 12 +#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_M 0x00001000 +#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_S 12 + +// Field: [11] TX_BUFFER_CHANGED +// +// Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED. +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 + +// Field: [10] TX_ENTRY_DONE +// +// Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 + +// Field: [9] TX_RETRANS +// +// Interrupt enable for RFCPEIFG.TX_RETRANS. +#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 + +// Field: [7] TX_CTRL_ACK +// +// Interrupt enable for RFCPEIFG.TX_CTRL_ACK. +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 + +// Field: [6] TX_CTRL +// +// Interrupt enable for RFCPEIFG.TX_CTRL. +#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 + +// Field: [5] TX_ACK +// +// Interrupt enable for RFCPEIFG.TX_ACK. +#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 + +// Field: [4] TX_DONE +// +// Interrupt enable for RFCPEIFG.TX_DONE. +#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 + +// Field: [2] FG_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.FG_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 + +// Field: [1] LAST_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 + +// Field: [0] COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEISL +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 + +// Field: [30] BOOT_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 + +// Field: [29] MODULES_UNLOCKED +// +// Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 + +// Field: [28] SYNTH_NO_LOCK +// +// Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 + +// Field: [27] IRQ27 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_S 27 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 + +// Field: [26] RX_ABORTED +// +// Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 + +// Field: [24] RX_DATA_WRITTEN +// +// Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 + +// Field: [23] RX_ENTRY_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 + +// Field: [22] RX_BUF_FULL +// +// Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 + +// Field: [21] RX_CTRL_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 + +// Field: [20] RX_CTRL +// +// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 + +// Field: [19] RX_EMPTY +// +// Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 + +// Field: [18] RX_IGNORED +// +// Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 + +// Field: [17] RX_NOK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_S 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 + +// Field: [16] RX_OK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_S 16 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 + +// Field: [15] IRQ15 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_S 15 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 + +// Field: [14] IRQ14 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_S 14 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 + +// Field: [13] FG_COMMAND_STARTED +// +// Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_STARTED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED 0x00002000 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_BITN 13 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_M 0x00002000 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_S 13 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE1 0x00002000 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE0 0x00000000 + +// Field: [12] COMMAND_STARTED +// +// Select which CPU interrupt vector the RFCPEIFG.COMMAND_STARTED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED 0x00001000 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_BITN 12 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_M 0x00001000 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_S 12 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE1 0x00001000 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE0 0x00000000 + +// Field: [11] TX_BUFFER_CHANGED +// +// Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 + +// Field: [10] TX_ENTRY_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 + +// Field: [9] TX_RETRANS +// +// Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 + +// Field: [7] TX_CTRL_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 + +// Field: [6] TX_CTRL +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 + +// Field: [5] TX_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_S 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 + +// Field: [4] TX_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_S 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE +// interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 + +// Field: [2] FG_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 + +// Field: [1] LAST_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 + +// Field: [0] COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFACKIFG +// +//***************************************************************************** +// Field: [0] ACKFLAG +// +// Interrupt flag for Command ACK +#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 +#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_SYSGPOCTL +// +//***************************************************************************** +// Field: [15:12] GPOCTL3 +// +// RF Core GPO control bit 3. Selects which signal to output on the RF Core GPO +// line 3. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 + +// Field: [11:8] GPOCTL2 +// +// RF Core GPO control bit 2. Selects which signal to output on the RF Core GPO +// line 2. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 + +// Field: [7:4] GPOCTL1 +// +// RF Core GPO control bit 1. Selects which signal to output on the RF Core GPO +// line 1. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 + +// Field: [3:0] GPOCTL0 +// +// RF Core GPO control bit 0. Selects which signal to output on the RF Core GPO +// line 0. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 + + +#endif // __RFC_DBELL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h new file mode 100644 index 0000000..7c636d9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h @@ -0,0 +1,153 @@ +/****************************************************************************** +* Filename: hw_rfc_pwr_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_PWR_H__ +#define __HW_RFC_PWR_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_PWR component +// +//***************************************************************************** +// RF Core Power Management and Clock Enable +#define RFC_PWR_O_PWMCLKEN 0x00000000 + +//***************************************************************************** +// +// Register: RFC_PWR_O_PWMCLKEN +// +//***************************************************************************** +// Field: [10] RFCTRC +// +// Enable clock to the RF Core Tracer (RFCTRC) module. +#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 +#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_S 10 + +// Field: [9] FSCA +// +// Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) +// module. +#define RFC_PWR_PWMCLKEN_FSCA 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_BITN 9 +#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_S 9 + +// Field: [8] PHA +// +// Enable clock to the Packet Handling Accelerator (PHA) module. +#define RFC_PWR_PWMCLKEN_PHA 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_BITN 8 +#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_S 8 + +// Field: [7] RAT +// +// Enable clock to the Radio Timer (RAT) module. +#define RFC_PWR_PWMCLKEN_RAT 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_BITN 7 +#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_S 7 + +// Field: [6] RFERAM +// +// Enable clock to the RF Engine RAM module. +#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 +#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_S 6 + +// Field: [5] RFE +// +// Enable clock to the RF Engine (RFE) module. +#define RFC_PWR_PWMCLKEN_RFE 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_BITN 5 +#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_S 5 + +// Field: [4] MDMRAM +// +// Enable clock to the Modem RAM module. +#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 +#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_S 4 + +// Field: [3] MDM +// +// Enable clock to the Modem (MDM) module. +#define RFC_PWR_PWMCLKEN_MDM 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_BITN 3 +#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_S 3 + +// Field: [2] CPERAM +// +// Enable clock to the Command and Packet Engine (CPE) RAM module. As part of +// RF Core initialization, set this bit together with CPE bit to enable CPE to +// boot. +#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 +#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_S 2 + +// Field: [1] CPE +// +// Enable processor clock (hclk) to the Command and Packet Engine (CPE). As +// part of RF Core initialization, set this bit together with CPERAM bit to +// enable CPE to boot. +#define RFC_PWR_PWMCLKEN_CPE 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_BITN 1 +#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_S 1 + +// Field: [0] RFC +// +// Enable essential clocks for the RF Core interface. This includes the +// interconnect, the radio doorbell DBELL command interface, the power +// management (PWR) clock control module, and bus clock (sclk) for the CPE. To +// remove possibility of locking yourself out from the RF Core, this bit can +// not be cleared. If you need to disable all clocks to the RF Core, see the +// PRCM:RFCCLKG.CLK_EN register. +#define RFC_PWR_PWMCLKEN_RFC 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_BITN 0 +#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_S 0 + + +#endif // __RFC_PWR__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h new file mode 100644 index 0000000..b2bdfd6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h @@ -0,0 +1,198 @@ +/****************************************************************************** +* Filename: hw_rfc_rat_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_RAT_H__ +#define __HW_RFC_RAT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_RAT component +// +//***************************************************************************** +// Radio Timer Counter Value +#define RFC_RAT_O_RATCNT 0x00000004 + +// Timer Channel 0 Capture/Compare Register +#define RFC_RAT_O_RATCH0VAL 0x00000080 + +// Timer Channel 1 Capture/Compare Register +#define RFC_RAT_O_RATCH1VAL 0x00000084 + +// Timer Channel 2 Capture/Compare Register +#define RFC_RAT_O_RATCH2VAL 0x00000088 + +// Timer Channel 3 Capture/Compare Register +#define RFC_RAT_O_RATCH3VAL 0x0000008C + +// Timer Channel 4 Capture/Compare Register +#define RFC_RAT_O_RATCH4VAL 0x00000090 + +// Timer Channel 5 Capture/Compare Register +#define RFC_RAT_O_RATCH5VAL 0x00000094 + +// Timer Channel 6 Capture/Compare Register +#define RFC_RAT_O_RATCH6VAL 0x00000098 + +// Timer Channel 7 Capture/Compare Register +#define RFC_RAT_O_RATCH7VAL 0x0000009C + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCNT +// +//***************************************************************************** +// Field: [31:0] CNT +// +// Counter value. This is not writable while radio timer counter is enabled. +#define RFC_RAT_RATCNT_CNT_W 32 +#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF +#define RFC_RAT_RATCNT_CNT_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH0VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH0VAL_VAL_W 32 +#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH0VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH1VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH1VAL_VAL_W 32 +#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH1VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH2VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH2VAL_VAL_W 32 +#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH2VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH3VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH3VAL_VAL_W 32 +#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH3VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH4VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH4VAL_VAL_W 32 +#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH4VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH5VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH5VAL_VAL_W 32 +#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH5VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH6VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH6VAL_VAL_W 32 +#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH6VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH7VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH7VAL_VAL_W 32 +#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH7VAL_VAL_S 0 + + +#endif // __RFC_RAT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h new file mode 100644 index 0000000..717184e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h @@ -0,0 +1,30767 @@ +/****************************************************************************** +* Filename: hw_rfc_ullram_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_ULLRAM_H__ +#define __HW_RFC_ULLRAM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_ULLRAM component +// +//***************************************************************************** +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK10 0x00000000 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11 0x00000004 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12 0x00000008 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK13 0x0000000C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK14 0x00000010 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK15 0x00000014 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK16 0x00000018 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK17 0x0000001C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK18 0x00000020 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK19 0x00000024 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK110 0x00000028 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK111 0x0000002C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK112 0x00000030 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK113 0x00000034 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK114 0x00000038 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK115 0x0000003C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK116 0x00000040 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK117 0x00000044 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK118 0x00000048 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK119 0x0000004C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK120 0x00000050 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK121 0x00000054 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK122 0x00000058 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK123 0x0000005C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK124 0x00000060 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK125 0x00000064 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK126 0x00000068 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK127 0x0000006C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK128 0x00000070 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK129 0x00000074 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK130 0x00000078 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK131 0x0000007C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK132 0x00000080 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK133 0x00000084 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK134 0x00000088 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK135 0x0000008C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK136 0x00000090 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK137 0x00000094 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK138 0x00000098 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK139 0x0000009C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK140 0x000000A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK141 0x000000A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK142 0x000000A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK143 0x000000AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK144 0x000000B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK145 0x000000B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK146 0x000000B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK147 0x000000BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK148 0x000000C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK149 0x000000C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK150 0x000000C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK151 0x000000CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK152 0x000000D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK153 0x000000D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK154 0x000000D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK155 0x000000DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK156 0x000000E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK157 0x000000E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK158 0x000000E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK159 0x000000EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK160 0x000000F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK161 0x000000F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK162 0x000000F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK163 0x000000FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK164 0x00000100 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK165 0x00000104 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK166 0x00000108 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK167 0x0000010C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK168 0x00000110 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK169 0x00000114 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK170 0x00000118 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK171 0x0000011C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK172 0x00000120 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK173 0x00000124 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK174 0x00000128 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK175 0x0000012C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK176 0x00000130 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK177 0x00000134 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK178 0x00000138 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK179 0x0000013C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK180 0x00000140 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK181 0x00000144 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK182 0x00000148 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK183 0x0000014C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK184 0x00000150 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK185 0x00000154 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK186 0x00000158 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK187 0x0000015C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK188 0x00000160 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK189 0x00000164 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK190 0x00000168 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK191 0x0000016C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK192 0x00000170 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK193 0x00000174 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK194 0x00000178 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK195 0x0000017C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK196 0x00000180 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK197 0x00000184 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK198 0x00000188 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK199 0x0000018C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1100 0x00000190 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1101 0x00000194 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1102 0x00000198 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1103 0x0000019C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1104 0x000001A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1105 0x000001A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1106 0x000001A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1107 0x000001AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1108 0x000001B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1109 0x000001B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1110 0x000001B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1111 0x000001BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1112 0x000001C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1113 0x000001C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1114 0x000001C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1115 0x000001CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1116 0x000001D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1117 0x000001D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1118 0x000001D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1119 0x000001DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1120 0x000001E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1121 0x000001E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1122 0x000001E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1123 0x000001EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1124 0x000001F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1125 0x000001F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1126 0x000001F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1127 0x000001FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1128 0x00000200 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1129 0x00000204 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1130 0x00000208 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1131 0x0000020C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1132 0x00000210 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1133 0x00000214 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1134 0x00000218 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1135 0x0000021C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1136 0x00000220 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1137 0x00000224 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1138 0x00000228 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1139 0x0000022C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1140 0x00000230 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1141 0x00000234 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1142 0x00000238 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1143 0x0000023C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1144 0x00000240 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1145 0x00000244 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1146 0x00000248 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1147 0x0000024C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1148 0x00000250 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1149 0x00000254 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1150 0x00000258 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1151 0x0000025C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1152 0x00000260 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1153 0x00000264 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1154 0x00000268 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1155 0x0000026C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1156 0x00000270 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1157 0x00000274 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1158 0x00000278 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1159 0x0000027C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1160 0x00000280 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1161 0x00000284 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1162 0x00000288 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1163 0x0000028C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1164 0x00000290 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1165 0x00000294 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1166 0x00000298 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1167 0x0000029C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1168 0x000002A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1169 0x000002A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1170 0x000002A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1171 0x000002AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1172 0x000002B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1173 0x000002B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1174 0x000002B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1175 0x000002BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1176 0x000002C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1177 0x000002C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1178 0x000002C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1179 0x000002CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1180 0x000002D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1181 0x000002D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1182 0x000002D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1183 0x000002DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1184 0x000002E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1185 0x000002E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1186 0x000002E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1187 0x000002EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1188 0x000002F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1189 0x000002F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1190 0x000002F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1191 0x000002FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1192 0x00000300 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1193 0x00000304 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1194 0x00000308 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1195 0x0000030C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1196 0x00000310 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1197 0x00000314 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1198 0x00000318 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1199 0x0000031C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1200 0x00000320 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1201 0x00000324 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1202 0x00000328 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1203 0x0000032C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1204 0x00000330 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1205 0x00000334 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1206 0x00000338 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1207 0x0000033C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1208 0x00000340 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1209 0x00000344 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1210 0x00000348 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1211 0x0000034C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1212 0x00000350 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1213 0x00000354 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1214 0x00000358 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1215 0x0000035C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1216 0x00000360 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1217 0x00000364 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1218 0x00000368 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1219 0x0000036C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1220 0x00000370 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1221 0x00000374 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1222 0x00000378 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1223 0x0000037C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1224 0x00000380 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1225 0x00000384 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1226 0x00000388 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1227 0x0000038C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1228 0x00000390 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1229 0x00000394 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1230 0x00000398 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1231 0x0000039C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1232 0x000003A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1233 0x000003A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1234 0x000003A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1235 0x000003AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1236 0x000003B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1237 0x000003B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1238 0x000003B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1239 0x000003BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1240 0x000003C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1241 0x000003C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1242 0x000003C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1243 0x000003CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1244 0x000003D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1245 0x000003D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1246 0x000003D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1247 0x000003DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1248 0x000003E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1249 0x000003E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1250 0x000003E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1251 0x000003EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1252 0x000003F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1253 0x000003F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1254 0x000003F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1255 0x000003FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1256 0x00000400 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1257 0x00000404 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1258 0x00000408 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1259 0x0000040C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1260 0x00000410 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1261 0x00000414 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1262 0x00000418 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1263 0x0000041C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1264 0x00000420 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1265 0x00000424 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1266 0x00000428 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1267 0x0000042C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1268 0x00000430 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1269 0x00000434 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1270 0x00000438 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1271 0x0000043C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1272 0x00000440 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1273 0x00000444 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1274 0x00000448 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1275 0x0000044C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1276 0x00000450 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1277 0x00000454 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1278 0x00000458 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1279 0x0000045C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1280 0x00000460 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1281 0x00000464 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1282 0x00000468 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1283 0x0000046C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1284 0x00000470 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1285 0x00000474 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1286 0x00000478 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1287 0x0000047C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1288 0x00000480 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1289 0x00000484 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1290 0x00000488 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1291 0x0000048C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1292 0x00000490 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1293 0x00000494 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1294 0x00000498 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1295 0x0000049C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1296 0x000004A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1297 0x000004A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1298 0x000004A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1299 0x000004AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1300 0x000004B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1301 0x000004B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1302 0x000004B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1303 0x000004BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1304 0x000004C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1305 0x000004C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1306 0x000004C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1307 0x000004CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1308 0x000004D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1309 0x000004D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1310 0x000004D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1311 0x000004DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1312 0x000004E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1313 0x000004E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1314 0x000004E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1315 0x000004EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1316 0x000004F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1317 0x000004F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1318 0x000004F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1319 0x000004FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1320 0x00000500 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1321 0x00000504 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1322 0x00000508 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1323 0x0000050C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1324 0x00000510 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1325 0x00000514 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1326 0x00000518 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1327 0x0000051C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1328 0x00000520 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1329 0x00000524 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1330 0x00000528 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1331 0x0000052C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1332 0x00000530 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1333 0x00000534 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1334 0x00000538 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1335 0x0000053C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1336 0x00000540 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1337 0x00000544 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1338 0x00000548 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1339 0x0000054C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1340 0x00000550 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1341 0x00000554 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1342 0x00000558 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1343 0x0000055C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1344 0x00000560 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1345 0x00000564 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1346 0x00000568 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1347 0x0000056C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1348 0x00000570 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1349 0x00000574 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1350 0x00000578 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1351 0x0000057C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1352 0x00000580 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1353 0x00000584 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1354 0x00000588 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1355 0x0000058C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1356 0x00000590 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1357 0x00000594 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1358 0x00000598 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1359 0x0000059C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1360 0x000005A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1361 0x000005A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1362 0x000005A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1363 0x000005AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1364 0x000005B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1365 0x000005B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1366 0x000005B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1367 0x000005BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1368 0x000005C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1369 0x000005C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1370 0x000005C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1371 0x000005CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1372 0x000005D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1373 0x000005D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1374 0x000005D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1375 0x000005DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1376 0x000005E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1377 0x000005E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1378 0x000005E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1379 0x000005EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1380 0x000005F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1381 0x000005F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1382 0x000005F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1383 0x000005FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1384 0x00000600 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1385 0x00000604 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1386 0x00000608 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1387 0x0000060C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1388 0x00000610 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1389 0x00000614 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1390 0x00000618 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1391 0x0000061C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1392 0x00000620 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1393 0x00000624 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1394 0x00000628 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1395 0x0000062C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1396 0x00000630 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1397 0x00000634 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1398 0x00000638 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1399 0x0000063C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1400 0x00000640 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1401 0x00000644 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1402 0x00000648 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1403 0x0000064C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1404 0x00000650 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1405 0x00000654 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1406 0x00000658 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1407 0x0000065C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1408 0x00000660 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1409 0x00000664 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1410 0x00000668 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1411 0x0000066C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1412 0x00000670 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1413 0x00000674 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1414 0x00000678 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1415 0x0000067C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1416 0x00000680 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1417 0x00000684 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1418 0x00000688 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1419 0x0000068C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1420 0x00000690 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1421 0x00000694 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1422 0x00000698 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1423 0x0000069C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1424 0x000006A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1425 0x000006A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1426 0x000006A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1427 0x000006AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1428 0x000006B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1429 0x000006B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1430 0x000006B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1431 0x000006BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1432 0x000006C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1433 0x000006C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1434 0x000006C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1435 0x000006CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1436 0x000006D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1437 0x000006D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1438 0x000006D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1439 0x000006DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1440 0x000006E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1441 0x000006E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1442 0x000006E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1443 0x000006EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1444 0x000006F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1445 0x000006F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1446 0x000006F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1447 0x000006FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1448 0x00000700 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1449 0x00000704 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1450 0x00000708 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1451 0x0000070C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1452 0x00000710 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1453 0x00000714 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1454 0x00000718 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1455 0x0000071C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1456 0x00000720 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1457 0x00000724 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1458 0x00000728 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1459 0x0000072C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1460 0x00000730 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1461 0x00000734 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1462 0x00000738 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1463 0x0000073C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1464 0x00000740 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1465 0x00000744 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1466 0x00000748 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1467 0x0000074C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1468 0x00000750 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1469 0x00000754 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1470 0x00000758 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1471 0x0000075C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1472 0x00000760 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1473 0x00000764 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1474 0x00000768 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1475 0x0000076C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1476 0x00000770 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1477 0x00000774 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1478 0x00000778 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1479 0x0000077C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1480 0x00000780 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1481 0x00000784 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1482 0x00000788 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1483 0x0000078C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1484 0x00000790 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1485 0x00000794 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1486 0x00000798 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1487 0x0000079C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1488 0x000007A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1489 0x000007A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1490 0x000007A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1491 0x000007AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1492 0x000007B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1493 0x000007B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1494 0x000007B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1495 0x000007BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1496 0x000007C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1497 0x000007C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1498 0x000007C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1499 0x000007CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1500 0x000007D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1501 0x000007D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1502 0x000007D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1503 0x000007DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1504 0x000007E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1505 0x000007E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1506 0x000007E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1507 0x000007EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1508 0x000007F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1509 0x000007F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1510 0x000007F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1511 0x000007FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1512 0x00000800 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1513 0x00000804 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1514 0x00000808 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1515 0x0000080C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1516 0x00000810 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1517 0x00000814 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1518 0x00000818 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1519 0x0000081C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1520 0x00000820 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1521 0x00000824 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1522 0x00000828 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1523 0x0000082C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1524 0x00000830 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1525 0x00000834 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1526 0x00000838 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1527 0x0000083C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1528 0x00000840 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1529 0x00000844 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1530 0x00000848 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1531 0x0000084C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1532 0x00000850 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1533 0x00000854 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1534 0x00000858 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1535 0x0000085C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1536 0x00000860 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1537 0x00000864 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1538 0x00000868 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1539 0x0000086C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1540 0x00000870 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1541 0x00000874 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1542 0x00000878 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1543 0x0000087C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1544 0x00000880 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1545 0x00000884 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1546 0x00000888 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1547 0x0000088C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1548 0x00000890 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1549 0x00000894 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1550 0x00000898 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1551 0x0000089C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1552 0x000008A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1553 0x000008A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1554 0x000008A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1555 0x000008AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1556 0x000008B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1557 0x000008B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1558 0x000008B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1559 0x000008BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1560 0x000008C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1561 0x000008C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1562 0x000008C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1563 0x000008CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1564 0x000008D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1565 0x000008D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1566 0x000008D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1567 0x000008DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1568 0x000008E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1569 0x000008E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1570 0x000008E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1571 0x000008EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1572 0x000008F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1573 0x000008F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1574 0x000008F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1575 0x000008FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1576 0x00000900 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1577 0x00000904 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1578 0x00000908 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1579 0x0000090C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1580 0x00000910 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1581 0x00000914 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1582 0x00000918 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1583 0x0000091C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1584 0x00000920 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1585 0x00000924 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1586 0x00000928 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1587 0x0000092C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1588 0x00000930 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1589 0x00000934 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1590 0x00000938 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1591 0x0000093C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1592 0x00000940 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1593 0x00000944 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1594 0x00000948 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1595 0x0000094C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1596 0x00000950 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1597 0x00000954 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1598 0x00000958 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1599 0x0000095C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1600 0x00000960 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1601 0x00000964 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1602 0x00000968 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1603 0x0000096C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1604 0x00000970 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1605 0x00000974 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1606 0x00000978 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1607 0x0000097C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1608 0x00000980 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1609 0x00000984 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1610 0x00000988 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1611 0x0000098C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1612 0x00000990 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1613 0x00000994 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1614 0x00000998 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1615 0x0000099C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1616 0x000009A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1617 0x000009A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1618 0x000009A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1619 0x000009AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1620 0x000009B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1621 0x000009B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1622 0x000009B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1623 0x000009BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1624 0x000009C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1625 0x000009C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1626 0x000009C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1627 0x000009CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1628 0x000009D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1629 0x000009D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1630 0x000009D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1631 0x000009DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1632 0x000009E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1633 0x000009E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1634 0x000009E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1635 0x000009EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1636 0x000009F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1637 0x000009F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1638 0x000009F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1639 0x000009FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1640 0x00000A00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1641 0x00000A04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1642 0x00000A08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1643 0x00000A0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1644 0x00000A10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1645 0x00000A14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1646 0x00000A18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1647 0x00000A1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1648 0x00000A20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1649 0x00000A24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1650 0x00000A28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1651 0x00000A2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1652 0x00000A30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1653 0x00000A34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1654 0x00000A38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1655 0x00000A3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1656 0x00000A40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1657 0x00000A44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1658 0x00000A48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1659 0x00000A4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1660 0x00000A50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1661 0x00000A54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1662 0x00000A58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1663 0x00000A5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1664 0x00000A60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1665 0x00000A64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1666 0x00000A68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1667 0x00000A6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1668 0x00000A70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1669 0x00000A74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1670 0x00000A78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1671 0x00000A7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1672 0x00000A80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1673 0x00000A84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1674 0x00000A88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1675 0x00000A8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1676 0x00000A90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1677 0x00000A94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1678 0x00000A98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1679 0x00000A9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1680 0x00000AA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1681 0x00000AA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1682 0x00000AA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1683 0x00000AAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1684 0x00000AB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1685 0x00000AB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1686 0x00000AB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1687 0x00000ABC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1688 0x00000AC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1689 0x00000AC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1690 0x00000AC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1691 0x00000ACC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1692 0x00000AD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1693 0x00000AD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1694 0x00000AD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1695 0x00000ADC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1696 0x00000AE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1697 0x00000AE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1698 0x00000AE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1699 0x00000AEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1700 0x00000AF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1701 0x00000AF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1702 0x00000AF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1703 0x00000AFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1704 0x00000B00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1705 0x00000B04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1706 0x00000B08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1707 0x00000B0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1708 0x00000B10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1709 0x00000B14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1710 0x00000B18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1711 0x00000B1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1712 0x00000B20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1713 0x00000B24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1714 0x00000B28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1715 0x00000B2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1716 0x00000B30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1717 0x00000B34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1718 0x00000B38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1719 0x00000B3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1720 0x00000B40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1721 0x00000B44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1722 0x00000B48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1723 0x00000B4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1724 0x00000B50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1725 0x00000B54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1726 0x00000B58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1727 0x00000B5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1728 0x00000B60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1729 0x00000B64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1730 0x00000B68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1731 0x00000B6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1732 0x00000B70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1733 0x00000B74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1734 0x00000B78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1735 0x00000B7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1736 0x00000B80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1737 0x00000B84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1738 0x00000B88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1739 0x00000B8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1740 0x00000B90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1741 0x00000B94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1742 0x00000B98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1743 0x00000B9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1744 0x00000BA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1745 0x00000BA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1746 0x00000BA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1747 0x00000BAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1748 0x00000BB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1749 0x00000BB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1750 0x00000BB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1751 0x00000BBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1752 0x00000BC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1753 0x00000BC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1754 0x00000BC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1755 0x00000BCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1756 0x00000BD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1757 0x00000BD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1758 0x00000BD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1759 0x00000BDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1760 0x00000BE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1761 0x00000BE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1762 0x00000BE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1763 0x00000BEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1764 0x00000BF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1765 0x00000BF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1766 0x00000BF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1767 0x00000BFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1768 0x00000C00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1769 0x00000C04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1770 0x00000C08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1771 0x00000C0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1772 0x00000C10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1773 0x00000C14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1774 0x00000C18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1775 0x00000C1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1776 0x00000C20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1777 0x00000C24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1778 0x00000C28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1779 0x00000C2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1780 0x00000C30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1781 0x00000C34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1782 0x00000C38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1783 0x00000C3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1784 0x00000C40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1785 0x00000C44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1786 0x00000C48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1787 0x00000C4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1788 0x00000C50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1789 0x00000C54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1790 0x00000C58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1791 0x00000C5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1792 0x00000C60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1793 0x00000C64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1794 0x00000C68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1795 0x00000C6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1796 0x00000C70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1797 0x00000C74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1798 0x00000C78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1799 0x00000C7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1800 0x00000C80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1801 0x00000C84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1802 0x00000C88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1803 0x00000C8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1804 0x00000C90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1805 0x00000C94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1806 0x00000C98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1807 0x00000C9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1808 0x00000CA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1809 0x00000CA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1810 0x00000CA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1811 0x00000CAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1812 0x00000CB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1813 0x00000CB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1814 0x00000CB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1815 0x00000CBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1816 0x00000CC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1817 0x00000CC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1818 0x00000CC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1819 0x00000CCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1820 0x00000CD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1821 0x00000CD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1822 0x00000CD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1823 0x00000CDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1824 0x00000CE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1825 0x00000CE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1826 0x00000CE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1827 0x00000CEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1828 0x00000CF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1829 0x00000CF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1830 0x00000CF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1831 0x00000CFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1832 0x00000D00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1833 0x00000D04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1834 0x00000D08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1835 0x00000D0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1836 0x00000D10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1837 0x00000D14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1838 0x00000D18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1839 0x00000D1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1840 0x00000D20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1841 0x00000D24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1842 0x00000D28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1843 0x00000D2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1844 0x00000D30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1845 0x00000D34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1846 0x00000D38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1847 0x00000D3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1848 0x00000D40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1849 0x00000D44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1850 0x00000D48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1851 0x00000D4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1852 0x00000D50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1853 0x00000D54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1854 0x00000D58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1855 0x00000D5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1856 0x00000D60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1857 0x00000D64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1858 0x00000D68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1859 0x00000D6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1860 0x00000D70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1861 0x00000D74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1862 0x00000D78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1863 0x00000D7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1864 0x00000D80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1865 0x00000D84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1866 0x00000D88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1867 0x00000D8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1868 0x00000D90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1869 0x00000D94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1870 0x00000D98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1871 0x00000D9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1872 0x00000DA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1873 0x00000DA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1874 0x00000DA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1875 0x00000DAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1876 0x00000DB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1877 0x00000DB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1878 0x00000DB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1879 0x00000DBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1880 0x00000DC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1881 0x00000DC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1882 0x00000DC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1883 0x00000DCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1884 0x00000DD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1885 0x00000DD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1886 0x00000DD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1887 0x00000DDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1888 0x00000DE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1889 0x00000DE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1890 0x00000DE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1891 0x00000DEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1892 0x00000DF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1893 0x00000DF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1894 0x00000DF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1895 0x00000DFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1896 0x00000E00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1897 0x00000E04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1898 0x00000E08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1899 0x00000E0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1900 0x00000E10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1901 0x00000E14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1902 0x00000E18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1903 0x00000E1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1904 0x00000E20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1905 0x00000E24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1906 0x00000E28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1907 0x00000E2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1908 0x00000E30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1909 0x00000E34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1910 0x00000E38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1911 0x00000E3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1912 0x00000E40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1913 0x00000E44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1914 0x00000E48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1915 0x00000E4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1916 0x00000E50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1917 0x00000E54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1918 0x00000E58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1919 0x00000E5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1920 0x00000E60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1921 0x00000E64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1922 0x00000E68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1923 0x00000E6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1924 0x00000E70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1925 0x00000E74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1926 0x00000E78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1927 0x00000E7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1928 0x00000E80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1929 0x00000E84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1930 0x00000E88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1931 0x00000E8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1932 0x00000E90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1933 0x00000E94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1934 0x00000E98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1935 0x00000E9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1936 0x00000EA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1937 0x00000EA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1938 0x00000EA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1939 0x00000EAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1940 0x00000EB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1941 0x00000EB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1942 0x00000EB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1943 0x00000EBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1944 0x00000EC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1945 0x00000EC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1946 0x00000EC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1947 0x00000ECC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1948 0x00000ED0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1949 0x00000ED4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1950 0x00000ED8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1951 0x00000EDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1952 0x00000EE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1953 0x00000EE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1954 0x00000EE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1955 0x00000EEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1956 0x00000EF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1957 0x00000EF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1958 0x00000EF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1959 0x00000EFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1960 0x00000F00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1961 0x00000F04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1962 0x00000F08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1963 0x00000F0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1964 0x00000F10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1965 0x00000F14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1966 0x00000F18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1967 0x00000F1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1968 0x00000F20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1969 0x00000F24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1970 0x00000F28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1971 0x00000F2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1972 0x00000F30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1973 0x00000F34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1974 0x00000F38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1975 0x00000F3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1976 0x00000F40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1977 0x00000F44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1978 0x00000F48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1979 0x00000F4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1980 0x00000F50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1981 0x00000F54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1982 0x00000F58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1983 0x00000F5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1984 0x00000F60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1985 0x00000F64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1986 0x00000F68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1987 0x00000F6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1988 0x00000F70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1989 0x00000F74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1990 0x00000F78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1991 0x00000F7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1992 0x00000F80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1993 0x00000F84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1994 0x00000F88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1995 0x00000F8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1996 0x00000F90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1997 0x00000F94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1998 0x00000F98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1999 0x00000F9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11000 0x00000FA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11001 0x00000FA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11002 0x00000FA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11003 0x00000FAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11004 0x00000FB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11005 0x00000FB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11006 0x00000FB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11007 0x00000FBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11008 0x00000FC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11009 0x00000FC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11010 0x00000FC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11011 0x00000FCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11012 0x00000FD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11013 0x00000FD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11014 0x00000FD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11015 0x00000FDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11016 0x00000FE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11017 0x00000FE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11018 0x00000FE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11019 0x00000FEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11020 0x00000FF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11021 0x00000FF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11022 0x00000FF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11023 0x00000FFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11024 0x00001000 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11025 0x00001004 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11026 0x00001008 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11027 0x0000100C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11028 0x00001010 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11029 0x00001014 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11030 0x00001018 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11031 0x0000101C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11032 0x00001020 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11033 0x00001024 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11034 0x00001028 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11035 0x0000102C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11036 0x00001030 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11037 0x00001034 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11038 0x00001038 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11039 0x0000103C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11040 0x00001040 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11041 0x00001044 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11042 0x00001048 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11043 0x0000104C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11044 0x00001050 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11045 0x00001054 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11046 0x00001058 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11047 0x0000105C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11048 0x00001060 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11049 0x00001064 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11050 0x00001068 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11051 0x0000106C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11052 0x00001070 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11053 0x00001074 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11054 0x00001078 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11055 0x0000107C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11056 0x00001080 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11057 0x00001084 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11058 0x00001088 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11059 0x0000108C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11060 0x00001090 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11061 0x00001094 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11062 0x00001098 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11063 0x0000109C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11064 0x000010A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11065 0x000010A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11066 0x000010A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11067 0x000010AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11068 0x000010B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11069 0x000010B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11070 0x000010B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11071 0x000010BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11072 0x000010C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11073 0x000010C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11074 0x000010C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11075 0x000010CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11076 0x000010D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11077 0x000010D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11078 0x000010D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11079 0x000010DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11080 0x000010E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11081 0x000010E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11082 0x000010E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11083 0x000010EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11084 0x000010F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11085 0x000010F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11086 0x000010F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11087 0x000010FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11088 0x00001100 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11089 0x00001104 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11090 0x00001108 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11091 0x0000110C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11092 0x00001110 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11093 0x00001114 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11094 0x00001118 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11095 0x0000111C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11096 0x00001120 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11097 0x00001124 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11098 0x00001128 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11099 0x0000112C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11100 0x00001130 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11101 0x00001134 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11102 0x00001138 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11103 0x0000113C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11104 0x00001140 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11105 0x00001144 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11106 0x00001148 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11107 0x0000114C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11108 0x00001150 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11109 0x00001154 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11110 0x00001158 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11111 0x0000115C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11112 0x00001160 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11113 0x00001164 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11114 0x00001168 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11115 0x0000116C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11116 0x00001170 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11117 0x00001174 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11118 0x00001178 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11119 0x0000117C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11120 0x00001180 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11121 0x00001184 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11122 0x00001188 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11123 0x0000118C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11124 0x00001190 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11125 0x00001194 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11126 0x00001198 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11127 0x0000119C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11128 0x000011A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11129 0x000011A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11130 0x000011A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11131 0x000011AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11132 0x000011B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11133 0x000011B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11134 0x000011B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11135 0x000011BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11136 0x000011C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11137 0x000011C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11138 0x000011C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11139 0x000011CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11140 0x000011D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11141 0x000011D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11142 0x000011D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11143 0x000011DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11144 0x000011E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11145 0x000011E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11146 0x000011E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11147 0x000011EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11148 0x000011F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11149 0x000011F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11150 0x000011F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11151 0x000011FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11152 0x00001200 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11153 0x00001204 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11154 0x00001208 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11155 0x0000120C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11156 0x00001210 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11157 0x00001214 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11158 0x00001218 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11159 0x0000121C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11160 0x00001220 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11161 0x00001224 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11162 0x00001228 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11163 0x0000122C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11164 0x00001230 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11165 0x00001234 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11166 0x00001238 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11167 0x0000123C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11168 0x00001240 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11169 0x00001244 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11170 0x00001248 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11171 0x0000124C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11172 0x00001250 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11173 0x00001254 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11174 0x00001258 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11175 0x0000125C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11176 0x00001260 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11177 0x00001264 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11178 0x00001268 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11179 0x0000126C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11180 0x00001270 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11181 0x00001274 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11182 0x00001278 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11183 0x0000127C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11184 0x00001280 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11185 0x00001284 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11186 0x00001288 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11187 0x0000128C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11188 0x00001290 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11189 0x00001294 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11190 0x00001298 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11191 0x0000129C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11192 0x000012A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11193 0x000012A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11194 0x000012A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11195 0x000012AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11196 0x000012B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11197 0x000012B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11198 0x000012B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11199 0x000012BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11200 0x000012C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11201 0x000012C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11202 0x000012C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11203 0x000012CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11204 0x000012D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11205 0x000012D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11206 0x000012D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11207 0x000012DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11208 0x000012E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11209 0x000012E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11210 0x000012E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11211 0x000012EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11212 0x000012F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11213 0x000012F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11214 0x000012F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11215 0x000012FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11216 0x00001300 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11217 0x00001304 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11218 0x00001308 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11219 0x0000130C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11220 0x00001310 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11221 0x00001314 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11222 0x00001318 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11223 0x0000131C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11224 0x00001320 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11225 0x00001324 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11226 0x00001328 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11227 0x0000132C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11228 0x00001330 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11229 0x00001334 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11230 0x00001338 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11231 0x0000133C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11232 0x00001340 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11233 0x00001344 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11234 0x00001348 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11235 0x0000134C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11236 0x00001350 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11237 0x00001354 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11238 0x00001358 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11239 0x0000135C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11240 0x00001360 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11241 0x00001364 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11242 0x00001368 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11243 0x0000136C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11244 0x00001370 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11245 0x00001374 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11246 0x00001378 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11247 0x0000137C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11248 0x00001380 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11249 0x00001384 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11250 0x00001388 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11251 0x0000138C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11252 0x00001390 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11253 0x00001394 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11254 0x00001398 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11255 0x0000139C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11256 0x000013A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11257 0x000013A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11258 0x000013A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11259 0x000013AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11260 0x000013B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11261 0x000013B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11262 0x000013B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11263 0x000013BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11264 0x000013C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11265 0x000013C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11266 0x000013C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11267 0x000013CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11268 0x000013D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11269 0x000013D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11270 0x000013D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11271 0x000013DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11272 0x000013E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11273 0x000013E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11274 0x000013E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11275 0x000013EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11276 0x000013F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11277 0x000013F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11278 0x000013F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11279 0x000013FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11280 0x00001400 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11281 0x00001404 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11282 0x00001408 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11283 0x0000140C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11284 0x00001410 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11285 0x00001414 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11286 0x00001418 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11287 0x0000141C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11288 0x00001420 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11289 0x00001424 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11290 0x00001428 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11291 0x0000142C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11292 0x00001430 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11293 0x00001434 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11294 0x00001438 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11295 0x0000143C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11296 0x00001440 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11297 0x00001444 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11298 0x00001448 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11299 0x0000144C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11300 0x00001450 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11301 0x00001454 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11302 0x00001458 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11303 0x0000145C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11304 0x00001460 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11305 0x00001464 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11306 0x00001468 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11307 0x0000146C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11308 0x00001470 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11309 0x00001474 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11310 0x00001478 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11311 0x0000147C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11312 0x00001480 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11313 0x00001484 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11314 0x00001488 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11315 0x0000148C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11316 0x00001490 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11317 0x00001494 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11318 0x00001498 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11319 0x0000149C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11320 0x000014A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11321 0x000014A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11322 0x000014A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11323 0x000014AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11324 0x000014B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11325 0x000014B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11326 0x000014B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11327 0x000014BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11328 0x000014C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11329 0x000014C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11330 0x000014C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11331 0x000014CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11332 0x000014D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11333 0x000014D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11334 0x000014D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11335 0x000014DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11336 0x000014E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11337 0x000014E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11338 0x000014E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11339 0x000014EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11340 0x000014F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11341 0x000014F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11342 0x000014F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11343 0x000014FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11344 0x00001500 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11345 0x00001504 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11346 0x00001508 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11347 0x0000150C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11348 0x00001510 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11349 0x00001514 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11350 0x00001518 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11351 0x0000151C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11352 0x00001520 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11353 0x00001524 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11354 0x00001528 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11355 0x0000152C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11356 0x00001530 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11357 0x00001534 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11358 0x00001538 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11359 0x0000153C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11360 0x00001540 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11361 0x00001544 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11362 0x00001548 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11363 0x0000154C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11364 0x00001550 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11365 0x00001554 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11366 0x00001558 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11367 0x0000155C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11368 0x00001560 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11369 0x00001564 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11370 0x00001568 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11371 0x0000156C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11372 0x00001570 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11373 0x00001574 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11374 0x00001578 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11375 0x0000157C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11376 0x00001580 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11377 0x00001584 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11378 0x00001588 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11379 0x0000158C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11380 0x00001590 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11381 0x00001594 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11382 0x00001598 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11383 0x0000159C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11384 0x000015A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11385 0x000015A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11386 0x000015A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11387 0x000015AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11388 0x000015B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11389 0x000015B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11390 0x000015B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11391 0x000015BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11392 0x000015C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11393 0x000015C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11394 0x000015C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11395 0x000015CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11396 0x000015D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11397 0x000015D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11398 0x000015D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11399 0x000015DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11400 0x000015E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11401 0x000015E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11402 0x000015E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11403 0x000015EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11404 0x000015F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11405 0x000015F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11406 0x000015F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11407 0x000015FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11408 0x00001600 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11409 0x00001604 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11410 0x00001608 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11411 0x0000160C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11412 0x00001610 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11413 0x00001614 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11414 0x00001618 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11415 0x0000161C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11416 0x00001620 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11417 0x00001624 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11418 0x00001628 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11419 0x0000162C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11420 0x00001630 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11421 0x00001634 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11422 0x00001638 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11423 0x0000163C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11424 0x00001640 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11425 0x00001644 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11426 0x00001648 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11427 0x0000164C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11428 0x00001650 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11429 0x00001654 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11430 0x00001658 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11431 0x0000165C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11432 0x00001660 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11433 0x00001664 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11434 0x00001668 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11435 0x0000166C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11436 0x00001670 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11437 0x00001674 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11438 0x00001678 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11439 0x0000167C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11440 0x00001680 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11441 0x00001684 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11442 0x00001688 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11443 0x0000168C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11444 0x00001690 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11445 0x00001694 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11446 0x00001698 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11447 0x0000169C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11448 0x000016A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11449 0x000016A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11450 0x000016A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11451 0x000016AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11452 0x000016B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11453 0x000016B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11454 0x000016B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11455 0x000016BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11456 0x000016C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11457 0x000016C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11458 0x000016C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11459 0x000016CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11460 0x000016D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11461 0x000016D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11462 0x000016D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11463 0x000016DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11464 0x000016E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11465 0x000016E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11466 0x000016E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11467 0x000016EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11468 0x000016F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11469 0x000016F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11470 0x000016F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11471 0x000016FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11472 0x00001700 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11473 0x00001704 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11474 0x00001708 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11475 0x0000170C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11476 0x00001710 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11477 0x00001714 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11478 0x00001718 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11479 0x0000171C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11480 0x00001720 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11481 0x00001724 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11482 0x00001728 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11483 0x0000172C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11484 0x00001730 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11485 0x00001734 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11486 0x00001738 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11487 0x0000173C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11488 0x00001740 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11489 0x00001744 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11490 0x00001748 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11491 0x0000174C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11492 0x00001750 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11493 0x00001754 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11494 0x00001758 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11495 0x0000175C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11496 0x00001760 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11497 0x00001764 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11498 0x00001768 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11499 0x0000176C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11500 0x00001770 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11501 0x00001774 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11502 0x00001778 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11503 0x0000177C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11504 0x00001780 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11505 0x00001784 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11506 0x00001788 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11507 0x0000178C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11508 0x00001790 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11509 0x00001794 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11510 0x00001798 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11511 0x0000179C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11512 0x000017A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11513 0x000017A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11514 0x000017A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11515 0x000017AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11516 0x000017B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11517 0x000017B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11518 0x000017B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11519 0x000017BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11520 0x000017C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11521 0x000017C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11522 0x000017C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11523 0x000017CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11524 0x000017D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11525 0x000017D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11526 0x000017D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11527 0x000017DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11528 0x000017E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11529 0x000017E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11530 0x000017E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11531 0x000017EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11532 0x000017F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11533 0x000017F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11534 0x000017F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11535 0x000017FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11536 0x00001800 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11537 0x00001804 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11538 0x00001808 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11539 0x0000180C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11540 0x00001810 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11541 0x00001814 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11542 0x00001818 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11543 0x0000181C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11544 0x00001820 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11545 0x00001824 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11546 0x00001828 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11547 0x0000182C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11548 0x00001830 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11549 0x00001834 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11550 0x00001838 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11551 0x0000183C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11552 0x00001840 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11553 0x00001844 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11554 0x00001848 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11555 0x0000184C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11556 0x00001850 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11557 0x00001854 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11558 0x00001858 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11559 0x0000185C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11560 0x00001860 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11561 0x00001864 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11562 0x00001868 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11563 0x0000186C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11564 0x00001870 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11565 0x00001874 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11566 0x00001878 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11567 0x0000187C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11568 0x00001880 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11569 0x00001884 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11570 0x00001888 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11571 0x0000188C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11572 0x00001890 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11573 0x00001894 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11574 0x00001898 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11575 0x0000189C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11576 0x000018A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11577 0x000018A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11578 0x000018A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11579 0x000018AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11580 0x000018B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11581 0x000018B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11582 0x000018B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11583 0x000018BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11584 0x000018C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11585 0x000018C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11586 0x000018C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11587 0x000018CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11588 0x000018D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11589 0x000018D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11590 0x000018D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11591 0x000018DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11592 0x000018E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11593 0x000018E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11594 0x000018E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11595 0x000018EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11596 0x000018F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11597 0x000018F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11598 0x000018F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11599 0x000018FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11600 0x00001900 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11601 0x00001904 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11602 0x00001908 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11603 0x0000190C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11604 0x00001910 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11605 0x00001914 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11606 0x00001918 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11607 0x0000191C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11608 0x00001920 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11609 0x00001924 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11610 0x00001928 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11611 0x0000192C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11612 0x00001930 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11613 0x00001934 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11614 0x00001938 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11615 0x0000193C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11616 0x00001940 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11617 0x00001944 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11618 0x00001948 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11619 0x0000194C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11620 0x00001950 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11621 0x00001954 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11622 0x00001958 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11623 0x0000195C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11624 0x00001960 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11625 0x00001964 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11626 0x00001968 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11627 0x0000196C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11628 0x00001970 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11629 0x00001974 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11630 0x00001978 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11631 0x0000197C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11632 0x00001980 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11633 0x00001984 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11634 0x00001988 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11635 0x0000198C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11636 0x00001990 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11637 0x00001994 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11638 0x00001998 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11639 0x0000199C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11640 0x000019A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11641 0x000019A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11642 0x000019A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11643 0x000019AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11644 0x000019B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11645 0x000019B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11646 0x000019B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11647 0x000019BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11648 0x000019C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11649 0x000019C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11650 0x000019C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11651 0x000019CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11652 0x000019D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11653 0x000019D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11654 0x000019D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11655 0x000019DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11656 0x000019E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11657 0x000019E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11658 0x000019E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11659 0x000019EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11660 0x000019F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11661 0x000019F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11662 0x000019F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11663 0x000019FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11664 0x00001A00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11665 0x00001A04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11666 0x00001A08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11667 0x00001A0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11668 0x00001A10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11669 0x00001A14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11670 0x00001A18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11671 0x00001A1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11672 0x00001A20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11673 0x00001A24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11674 0x00001A28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11675 0x00001A2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11676 0x00001A30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11677 0x00001A34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11678 0x00001A38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11679 0x00001A3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11680 0x00001A40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11681 0x00001A44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11682 0x00001A48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11683 0x00001A4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11684 0x00001A50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11685 0x00001A54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11686 0x00001A58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11687 0x00001A5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11688 0x00001A60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11689 0x00001A64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11690 0x00001A68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11691 0x00001A6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11692 0x00001A70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11693 0x00001A74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11694 0x00001A78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11695 0x00001A7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11696 0x00001A80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11697 0x00001A84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11698 0x00001A88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11699 0x00001A8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11700 0x00001A90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11701 0x00001A94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11702 0x00001A98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11703 0x00001A9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11704 0x00001AA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11705 0x00001AA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11706 0x00001AA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11707 0x00001AAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11708 0x00001AB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11709 0x00001AB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11710 0x00001AB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11711 0x00001ABC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11712 0x00001AC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11713 0x00001AC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11714 0x00001AC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11715 0x00001ACC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11716 0x00001AD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11717 0x00001AD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11718 0x00001AD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11719 0x00001ADC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11720 0x00001AE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11721 0x00001AE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11722 0x00001AE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11723 0x00001AEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11724 0x00001AF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11725 0x00001AF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11726 0x00001AF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11727 0x00001AFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11728 0x00001B00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11729 0x00001B04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11730 0x00001B08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11731 0x00001B0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11732 0x00001B10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11733 0x00001B14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11734 0x00001B18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11735 0x00001B1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11736 0x00001B20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11737 0x00001B24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11738 0x00001B28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11739 0x00001B2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11740 0x00001B30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11741 0x00001B34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11742 0x00001B38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11743 0x00001B3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11744 0x00001B40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11745 0x00001B44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11746 0x00001B48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11747 0x00001B4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11748 0x00001B50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11749 0x00001B54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11750 0x00001B58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11751 0x00001B5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11752 0x00001B60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11753 0x00001B64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11754 0x00001B68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11755 0x00001B6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11756 0x00001B70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11757 0x00001B74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11758 0x00001B78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11759 0x00001B7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11760 0x00001B80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11761 0x00001B84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11762 0x00001B88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11763 0x00001B8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11764 0x00001B90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11765 0x00001B94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11766 0x00001B98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11767 0x00001B9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11768 0x00001BA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11769 0x00001BA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11770 0x00001BA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11771 0x00001BAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11772 0x00001BB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11773 0x00001BB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11774 0x00001BB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11775 0x00001BBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11776 0x00001BC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11777 0x00001BC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11778 0x00001BC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11779 0x00001BCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11780 0x00001BD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11781 0x00001BD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11782 0x00001BD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11783 0x00001BDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11784 0x00001BE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11785 0x00001BE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11786 0x00001BE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11787 0x00001BEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11788 0x00001BF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11789 0x00001BF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11790 0x00001BF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11791 0x00001BFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11792 0x00001C00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11793 0x00001C04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11794 0x00001C08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11795 0x00001C0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11796 0x00001C10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11797 0x00001C14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11798 0x00001C18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11799 0x00001C1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11800 0x00001C20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11801 0x00001C24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11802 0x00001C28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11803 0x00001C2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11804 0x00001C30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11805 0x00001C34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11806 0x00001C38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11807 0x00001C3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11808 0x00001C40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11809 0x00001C44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11810 0x00001C48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11811 0x00001C4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11812 0x00001C50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11813 0x00001C54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11814 0x00001C58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11815 0x00001C5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11816 0x00001C60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11817 0x00001C64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11818 0x00001C68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11819 0x00001C6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11820 0x00001C70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11821 0x00001C74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11822 0x00001C78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11823 0x00001C7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11824 0x00001C80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11825 0x00001C84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11826 0x00001C88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11827 0x00001C8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11828 0x00001C90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11829 0x00001C94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11830 0x00001C98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11831 0x00001C9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11832 0x00001CA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11833 0x00001CA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11834 0x00001CA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11835 0x00001CAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11836 0x00001CB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11837 0x00001CB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11838 0x00001CB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11839 0x00001CBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11840 0x00001CC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11841 0x00001CC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11842 0x00001CC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11843 0x00001CCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11844 0x00001CD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11845 0x00001CD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11846 0x00001CD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11847 0x00001CDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11848 0x00001CE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11849 0x00001CE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11850 0x00001CE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11851 0x00001CEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11852 0x00001CF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11853 0x00001CF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11854 0x00001CF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11855 0x00001CFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11856 0x00001D00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11857 0x00001D04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11858 0x00001D08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11859 0x00001D0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11860 0x00001D10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11861 0x00001D14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11862 0x00001D18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11863 0x00001D1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11864 0x00001D20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11865 0x00001D24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11866 0x00001D28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11867 0x00001D2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11868 0x00001D30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11869 0x00001D34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11870 0x00001D38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11871 0x00001D3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11872 0x00001D40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11873 0x00001D44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11874 0x00001D48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11875 0x00001D4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11876 0x00001D50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11877 0x00001D54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11878 0x00001D58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11879 0x00001D5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11880 0x00001D60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11881 0x00001D64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11882 0x00001D68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11883 0x00001D6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11884 0x00001D70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11885 0x00001D74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11886 0x00001D78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11887 0x00001D7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11888 0x00001D80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11889 0x00001D84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11890 0x00001D88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11891 0x00001D8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11892 0x00001D90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11893 0x00001D94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11894 0x00001D98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11895 0x00001D9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11896 0x00001DA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11897 0x00001DA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11898 0x00001DA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11899 0x00001DAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11900 0x00001DB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11901 0x00001DB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11902 0x00001DB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11903 0x00001DBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11904 0x00001DC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11905 0x00001DC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11906 0x00001DC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11907 0x00001DCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11908 0x00001DD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11909 0x00001DD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11910 0x00001DD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11911 0x00001DDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11912 0x00001DE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11913 0x00001DE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11914 0x00001DE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11915 0x00001DEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11916 0x00001DF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11917 0x00001DF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11918 0x00001DF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11919 0x00001DFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11920 0x00001E00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11921 0x00001E04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11922 0x00001E08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11923 0x00001E0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11924 0x00001E10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11925 0x00001E14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11926 0x00001E18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11927 0x00001E1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11928 0x00001E20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11929 0x00001E24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11930 0x00001E28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11931 0x00001E2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11932 0x00001E30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11933 0x00001E34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11934 0x00001E38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11935 0x00001E3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11936 0x00001E40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11937 0x00001E44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11938 0x00001E48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11939 0x00001E4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11940 0x00001E50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11941 0x00001E54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11942 0x00001E58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11943 0x00001E5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11944 0x00001E60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11945 0x00001E64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11946 0x00001E68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11947 0x00001E6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11948 0x00001E70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11949 0x00001E74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11950 0x00001E78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11951 0x00001E7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11952 0x00001E80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11953 0x00001E84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11954 0x00001E88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11955 0x00001E8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11956 0x00001E90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11957 0x00001E94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11958 0x00001E98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11959 0x00001E9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11960 0x00001EA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11961 0x00001EA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11962 0x00001EA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11963 0x00001EAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11964 0x00001EB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11965 0x00001EB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11966 0x00001EB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11967 0x00001EBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11968 0x00001EC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11969 0x00001EC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11970 0x00001EC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11971 0x00001ECC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11972 0x00001ED0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11973 0x00001ED4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11974 0x00001ED8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11975 0x00001EDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11976 0x00001EE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11977 0x00001EE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11978 0x00001EE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11979 0x00001EEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11980 0x00001EF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11981 0x00001EF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11982 0x00001EF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11983 0x00001EFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11984 0x00001F00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11985 0x00001F04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11986 0x00001F08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11987 0x00001F0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11988 0x00001F10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11989 0x00001F14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11990 0x00001F18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11991 0x00001F1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11992 0x00001F20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11993 0x00001F24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11994 0x00001F28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11995 0x00001F2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11996 0x00001F30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11997 0x00001F34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11998 0x00001F38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11999 0x00001F3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12000 0x00001F40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12001 0x00001F44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12002 0x00001F48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12003 0x00001F4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12004 0x00001F50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12005 0x00001F54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12006 0x00001F58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12007 0x00001F5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12008 0x00001F60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12009 0x00001F64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12010 0x00001F68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12011 0x00001F6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12012 0x00001F70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12013 0x00001F74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12014 0x00001F78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12015 0x00001F7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12016 0x00001F80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12017 0x00001F84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12018 0x00001F88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12019 0x00001F8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12020 0x00001F90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12021 0x00001F94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12022 0x00001F98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12023 0x00001F9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12024 0x00001FA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12025 0x00001FA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12026 0x00001FA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12027 0x00001FAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12028 0x00001FB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12029 0x00001FB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12030 0x00001FB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12031 0x00001FBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12032 0x00001FC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12033 0x00001FC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12034 0x00001FC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12035 0x00001FCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12036 0x00001FD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12037 0x00001FD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12038 0x00001FD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12039 0x00001FDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12040 0x00001FE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12041 0x00001FE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12042 0x00001FE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12043 0x00001FEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12044 0x00001FF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12045 0x00001FF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12046 0x00001FF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12047 0x00001FFC + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK10 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK10_DATA_W 32 +#define RFC_ULLRAM_BANK10_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK10_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11_DATA_W 32 +#define RFC_ULLRAM_BANK11_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12_DATA_W 32 +#define RFC_ULLRAM_BANK12_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK13 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK13_DATA_W 32 +#define RFC_ULLRAM_BANK13_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK13_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK14 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK14_DATA_W 32 +#define RFC_ULLRAM_BANK14_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK14_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK15 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK15_DATA_W 32 +#define RFC_ULLRAM_BANK15_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK15_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK16 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK16_DATA_W 32 +#define RFC_ULLRAM_BANK16_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK16_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK17 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK17_DATA_W 32 +#define RFC_ULLRAM_BANK17_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK17_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK18 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK18_DATA_W 32 +#define RFC_ULLRAM_BANK18_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK18_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK19 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK19_DATA_W 32 +#define RFC_ULLRAM_BANK19_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK19_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK110 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK110_DATA_W 32 +#define RFC_ULLRAM_BANK110_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK110_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK111 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK111_DATA_W 32 +#define RFC_ULLRAM_BANK111_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK111_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK112 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK112_DATA_W 32 +#define RFC_ULLRAM_BANK112_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK112_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK113 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK113_DATA_W 32 +#define RFC_ULLRAM_BANK113_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK113_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK114 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK114_DATA_W 32 +#define RFC_ULLRAM_BANK114_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK114_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK115 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK115_DATA_W 32 +#define RFC_ULLRAM_BANK115_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK115_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK116 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK116_DATA_W 32 +#define RFC_ULLRAM_BANK116_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK116_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK117 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK117_DATA_W 32 +#define RFC_ULLRAM_BANK117_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK117_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK118 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK118_DATA_W 32 +#define RFC_ULLRAM_BANK118_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK118_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK119 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK119_DATA_W 32 +#define RFC_ULLRAM_BANK119_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK119_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK120 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK120_DATA_W 32 +#define RFC_ULLRAM_BANK120_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK120_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK121 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK121_DATA_W 32 +#define RFC_ULLRAM_BANK121_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK121_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK122 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK122_DATA_W 32 +#define RFC_ULLRAM_BANK122_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK122_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK123 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK123_DATA_W 32 +#define RFC_ULLRAM_BANK123_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK123_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK124 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK124_DATA_W 32 +#define RFC_ULLRAM_BANK124_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK124_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK125 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK125_DATA_W 32 +#define RFC_ULLRAM_BANK125_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK125_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK126 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK126_DATA_W 32 +#define RFC_ULLRAM_BANK126_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK126_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK127 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK127_DATA_W 32 +#define RFC_ULLRAM_BANK127_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK127_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK128 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK128_DATA_W 32 +#define RFC_ULLRAM_BANK128_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK128_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK129 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK129_DATA_W 32 +#define RFC_ULLRAM_BANK129_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK129_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK130 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK130_DATA_W 32 +#define RFC_ULLRAM_BANK130_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK130_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK131 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK131_DATA_W 32 +#define RFC_ULLRAM_BANK131_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK131_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK132 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK132_DATA_W 32 +#define RFC_ULLRAM_BANK132_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK132_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK133 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK133_DATA_W 32 +#define RFC_ULLRAM_BANK133_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK133_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK134 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK134_DATA_W 32 +#define RFC_ULLRAM_BANK134_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK134_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK135 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK135_DATA_W 32 +#define RFC_ULLRAM_BANK135_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK135_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK136 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK136_DATA_W 32 +#define RFC_ULLRAM_BANK136_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK136_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK137 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK137_DATA_W 32 +#define RFC_ULLRAM_BANK137_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK137_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK138 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK138_DATA_W 32 +#define RFC_ULLRAM_BANK138_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK138_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK139 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK139_DATA_W 32 +#define RFC_ULLRAM_BANK139_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK139_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK140 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK140_DATA_W 32 +#define RFC_ULLRAM_BANK140_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK140_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK141 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK141_DATA_W 32 +#define RFC_ULLRAM_BANK141_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK141_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK142 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK142_DATA_W 32 +#define RFC_ULLRAM_BANK142_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK142_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK143 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK143_DATA_W 32 +#define RFC_ULLRAM_BANK143_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK143_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK144 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK144_DATA_W 32 +#define RFC_ULLRAM_BANK144_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK144_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK145 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK145_DATA_W 32 +#define RFC_ULLRAM_BANK145_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK145_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK146 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK146_DATA_W 32 +#define RFC_ULLRAM_BANK146_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK146_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK147 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK147_DATA_W 32 +#define RFC_ULLRAM_BANK147_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK147_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK148 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK148_DATA_W 32 +#define RFC_ULLRAM_BANK148_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK148_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK149 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK149_DATA_W 32 +#define RFC_ULLRAM_BANK149_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK149_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK150 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK150_DATA_W 32 +#define RFC_ULLRAM_BANK150_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK150_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK151 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK151_DATA_W 32 +#define RFC_ULLRAM_BANK151_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK151_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK152 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK152_DATA_W 32 +#define RFC_ULLRAM_BANK152_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK152_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK153 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK153_DATA_W 32 +#define RFC_ULLRAM_BANK153_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK153_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK154 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK154_DATA_W 32 +#define RFC_ULLRAM_BANK154_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK154_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK155 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK155_DATA_W 32 +#define RFC_ULLRAM_BANK155_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK155_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK156 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK156_DATA_W 32 +#define RFC_ULLRAM_BANK156_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK156_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK157 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK157_DATA_W 32 +#define RFC_ULLRAM_BANK157_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK157_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK158 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK158_DATA_W 32 +#define RFC_ULLRAM_BANK158_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK158_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK159 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK159_DATA_W 32 +#define RFC_ULLRAM_BANK159_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK159_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK160 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK160_DATA_W 32 +#define RFC_ULLRAM_BANK160_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK160_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK161 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK161_DATA_W 32 +#define RFC_ULLRAM_BANK161_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK161_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK162 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK162_DATA_W 32 +#define RFC_ULLRAM_BANK162_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK162_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK163 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK163_DATA_W 32 +#define RFC_ULLRAM_BANK163_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK163_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK164 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK164_DATA_W 32 +#define RFC_ULLRAM_BANK164_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK164_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK165 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK165_DATA_W 32 +#define RFC_ULLRAM_BANK165_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK165_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK166 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK166_DATA_W 32 +#define RFC_ULLRAM_BANK166_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK166_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK167 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK167_DATA_W 32 +#define RFC_ULLRAM_BANK167_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK167_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK168 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK168_DATA_W 32 +#define RFC_ULLRAM_BANK168_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK168_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK169 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK169_DATA_W 32 +#define RFC_ULLRAM_BANK169_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK169_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK170 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK170_DATA_W 32 +#define RFC_ULLRAM_BANK170_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK170_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK171 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK171_DATA_W 32 +#define RFC_ULLRAM_BANK171_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK171_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK172 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK172_DATA_W 32 +#define RFC_ULLRAM_BANK172_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK172_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK173 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK173_DATA_W 32 +#define RFC_ULLRAM_BANK173_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK173_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK174 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK174_DATA_W 32 +#define RFC_ULLRAM_BANK174_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK174_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK175 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK175_DATA_W 32 +#define RFC_ULLRAM_BANK175_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK175_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK176 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK176_DATA_W 32 +#define RFC_ULLRAM_BANK176_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK176_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK177 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK177_DATA_W 32 +#define RFC_ULLRAM_BANK177_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK177_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK178 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK178_DATA_W 32 +#define RFC_ULLRAM_BANK178_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK178_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK179 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK179_DATA_W 32 +#define RFC_ULLRAM_BANK179_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK179_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK180 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK180_DATA_W 32 +#define RFC_ULLRAM_BANK180_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK180_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK181 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK181_DATA_W 32 +#define RFC_ULLRAM_BANK181_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK181_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK182 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK182_DATA_W 32 +#define RFC_ULLRAM_BANK182_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK182_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK183 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK183_DATA_W 32 +#define RFC_ULLRAM_BANK183_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK183_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK184 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK184_DATA_W 32 +#define RFC_ULLRAM_BANK184_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK184_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK185 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK185_DATA_W 32 +#define RFC_ULLRAM_BANK185_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK185_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK186 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK186_DATA_W 32 +#define RFC_ULLRAM_BANK186_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK186_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK187 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK187_DATA_W 32 +#define RFC_ULLRAM_BANK187_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK187_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK188 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK188_DATA_W 32 +#define RFC_ULLRAM_BANK188_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK188_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK189 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK189_DATA_W 32 +#define RFC_ULLRAM_BANK189_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK189_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK190 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK190_DATA_W 32 +#define RFC_ULLRAM_BANK190_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK190_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK191 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK191_DATA_W 32 +#define RFC_ULLRAM_BANK191_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK191_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK192 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK192_DATA_W 32 +#define RFC_ULLRAM_BANK192_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK192_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK193 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK193_DATA_W 32 +#define RFC_ULLRAM_BANK193_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK193_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK194 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK194_DATA_W 32 +#define RFC_ULLRAM_BANK194_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK194_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK195 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK195_DATA_W 32 +#define RFC_ULLRAM_BANK195_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK195_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK196 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK196_DATA_W 32 +#define RFC_ULLRAM_BANK196_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK196_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK197 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK197_DATA_W 32 +#define RFC_ULLRAM_BANK197_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK197_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK198 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK198_DATA_W 32 +#define RFC_ULLRAM_BANK198_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK198_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK199 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK199_DATA_W 32 +#define RFC_ULLRAM_BANK199_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK199_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1100 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1100_DATA_W 32 +#define RFC_ULLRAM_BANK1100_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1100_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1101 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1101_DATA_W 32 +#define RFC_ULLRAM_BANK1101_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1101_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1102 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1102_DATA_W 32 +#define RFC_ULLRAM_BANK1102_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1102_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1103 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1103_DATA_W 32 +#define RFC_ULLRAM_BANK1103_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1103_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1104 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1104_DATA_W 32 +#define RFC_ULLRAM_BANK1104_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1104_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1105 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1105_DATA_W 32 +#define RFC_ULLRAM_BANK1105_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1105_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1106 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1106_DATA_W 32 +#define RFC_ULLRAM_BANK1106_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1106_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1107 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1107_DATA_W 32 +#define RFC_ULLRAM_BANK1107_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1107_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1108 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1108_DATA_W 32 +#define RFC_ULLRAM_BANK1108_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1108_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1109 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1109_DATA_W 32 +#define RFC_ULLRAM_BANK1109_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1109_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1110 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1110_DATA_W 32 +#define RFC_ULLRAM_BANK1110_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1110_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1111 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1111_DATA_W 32 +#define RFC_ULLRAM_BANK1111_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1111_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1112 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1112_DATA_W 32 +#define RFC_ULLRAM_BANK1112_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1112_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1113 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1113_DATA_W 32 +#define RFC_ULLRAM_BANK1113_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1113_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1114 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1114_DATA_W 32 +#define RFC_ULLRAM_BANK1114_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1114_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1115 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1115_DATA_W 32 +#define RFC_ULLRAM_BANK1115_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1115_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1116 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1116_DATA_W 32 +#define RFC_ULLRAM_BANK1116_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1116_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1117 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1117_DATA_W 32 +#define RFC_ULLRAM_BANK1117_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1117_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1118 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1118_DATA_W 32 +#define RFC_ULLRAM_BANK1118_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1118_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1119 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1119_DATA_W 32 +#define RFC_ULLRAM_BANK1119_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1119_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1120 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1120_DATA_W 32 +#define RFC_ULLRAM_BANK1120_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1120_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1121 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1121_DATA_W 32 +#define RFC_ULLRAM_BANK1121_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1121_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1122 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1122_DATA_W 32 +#define RFC_ULLRAM_BANK1122_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1122_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1123 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1123_DATA_W 32 +#define RFC_ULLRAM_BANK1123_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1123_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1124 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1124_DATA_W 32 +#define RFC_ULLRAM_BANK1124_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1124_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1125 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1125_DATA_W 32 +#define RFC_ULLRAM_BANK1125_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1125_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1126 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1126_DATA_W 32 +#define RFC_ULLRAM_BANK1126_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1126_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1127 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1127_DATA_W 32 +#define RFC_ULLRAM_BANK1127_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1127_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1128 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1128_DATA_W 32 +#define RFC_ULLRAM_BANK1128_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1128_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1129 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1129_DATA_W 32 +#define RFC_ULLRAM_BANK1129_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1129_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1130 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1130_DATA_W 32 +#define RFC_ULLRAM_BANK1130_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1130_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1131 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1131_DATA_W 32 +#define RFC_ULLRAM_BANK1131_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1131_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1132 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1132_DATA_W 32 +#define RFC_ULLRAM_BANK1132_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1132_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1133 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1133_DATA_W 32 +#define RFC_ULLRAM_BANK1133_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1133_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1134 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1134_DATA_W 32 +#define RFC_ULLRAM_BANK1134_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1134_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1135 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1135_DATA_W 32 +#define RFC_ULLRAM_BANK1135_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1135_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1136 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1136_DATA_W 32 +#define RFC_ULLRAM_BANK1136_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1136_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1137 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1137_DATA_W 32 +#define RFC_ULLRAM_BANK1137_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1137_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1138 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1138_DATA_W 32 +#define RFC_ULLRAM_BANK1138_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1138_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1139 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1139_DATA_W 32 +#define RFC_ULLRAM_BANK1139_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1139_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1140 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1140_DATA_W 32 +#define RFC_ULLRAM_BANK1140_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1140_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1141 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1141_DATA_W 32 +#define RFC_ULLRAM_BANK1141_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1141_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1142 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1142_DATA_W 32 +#define RFC_ULLRAM_BANK1142_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1142_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1143 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1143_DATA_W 32 +#define RFC_ULLRAM_BANK1143_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1143_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1144 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1144_DATA_W 32 +#define RFC_ULLRAM_BANK1144_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1144_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1145 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1145_DATA_W 32 +#define RFC_ULLRAM_BANK1145_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1145_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1146 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1146_DATA_W 32 +#define RFC_ULLRAM_BANK1146_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1146_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1147 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1147_DATA_W 32 +#define RFC_ULLRAM_BANK1147_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1147_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1148 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1148_DATA_W 32 +#define RFC_ULLRAM_BANK1148_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1148_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1149 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1149_DATA_W 32 +#define RFC_ULLRAM_BANK1149_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1149_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1150 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1150_DATA_W 32 +#define RFC_ULLRAM_BANK1150_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1150_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1151 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1151_DATA_W 32 +#define RFC_ULLRAM_BANK1151_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1151_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1152 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1152_DATA_W 32 +#define RFC_ULLRAM_BANK1152_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1152_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1153 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1153_DATA_W 32 +#define RFC_ULLRAM_BANK1153_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1153_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1154 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1154_DATA_W 32 +#define RFC_ULLRAM_BANK1154_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1154_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1155 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1155_DATA_W 32 +#define RFC_ULLRAM_BANK1155_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1155_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1156 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1156_DATA_W 32 +#define RFC_ULLRAM_BANK1156_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1156_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1157 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1157_DATA_W 32 +#define RFC_ULLRAM_BANK1157_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1157_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1158 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1158_DATA_W 32 +#define RFC_ULLRAM_BANK1158_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1158_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1159 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1159_DATA_W 32 +#define RFC_ULLRAM_BANK1159_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1159_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1160 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1160_DATA_W 32 +#define RFC_ULLRAM_BANK1160_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1160_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1161 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1161_DATA_W 32 +#define RFC_ULLRAM_BANK1161_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1161_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1162 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1162_DATA_W 32 +#define RFC_ULLRAM_BANK1162_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1162_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1163 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1163_DATA_W 32 +#define RFC_ULLRAM_BANK1163_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1163_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1164 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1164_DATA_W 32 +#define RFC_ULLRAM_BANK1164_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1164_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1165 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1165_DATA_W 32 +#define RFC_ULLRAM_BANK1165_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1165_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1166 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1166_DATA_W 32 +#define RFC_ULLRAM_BANK1166_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1166_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1167 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1167_DATA_W 32 +#define RFC_ULLRAM_BANK1167_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1167_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1168 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1168_DATA_W 32 +#define RFC_ULLRAM_BANK1168_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1168_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1169 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1169_DATA_W 32 +#define RFC_ULLRAM_BANK1169_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1169_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1170 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1170_DATA_W 32 +#define RFC_ULLRAM_BANK1170_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1170_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1171 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1171_DATA_W 32 +#define RFC_ULLRAM_BANK1171_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1171_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1172 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1172_DATA_W 32 +#define RFC_ULLRAM_BANK1172_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1172_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1173 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1173_DATA_W 32 +#define RFC_ULLRAM_BANK1173_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1173_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1174 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1174_DATA_W 32 +#define RFC_ULLRAM_BANK1174_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1174_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1175 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1175_DATA_W 32 +#define RFC_ULLRAM_BANK1175_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1175_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1176 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1176_DATA_W 32 +#define RFC_ULLRAM_BANK1176_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1176_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1177 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1177_DATA_W 32 +#define RFC_ULLRAM_BANK1177_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1177_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1178 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1178_DATA_W 32 +#define RFC_ULLRAM_BANK1178_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1178_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1179 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1179_DATA_W 32 +#define RFC_ULLRAM_BANK1179_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1179_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1180 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1180_DATA_W 32 +#define RFC_ULLRAM_BANK1180_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1180_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1181 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1181_DATA_W 32 +#define RFC_ULLRAM_BANK1181_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1181_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1182 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1182_DATA_W 32 +#define RFC_ULLRAM_BANK1182_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1182_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1183 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1183_DATA_W 32 +#define RFC_ULLRAM_BANK1183_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1183_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1184 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1184_DATA_W 32 +#define RFC_ULLRAM_BANK1184_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1184_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1185 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1185_DATA_W 32 +#define RFC_ULLRAM_BANK1185_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1185_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1186 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1186_DATA_W 32 +#define RFC_ULLRAM_BANK1186_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1186_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1187 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1187_DATA_W 32 +#define RFC_ULLRAM_BANK1187_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1187_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1188 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1188_DATA_W 32 +#define RFC_ULLRAM_BANK1188_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1188_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1189 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1189_DATA_W 32 +#define RFC_ULLRAM_BANK1189_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1189_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1190 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1190_DATA_W 32 +#define RFC_ULLRAM_BANK1190_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1190_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1191 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1191_DATA_W 32 +#define RFC_ULLRAM_BANK1191_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1191_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1192 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1192_DATA_W 32 +#define RFC_ULLRAM_BANK1192_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1192_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1193 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1193_DATA_W 32 +#define RFC_ULLRAM_BANK1193_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1193_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1194 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1194_DATA_W 32 +#define RFC_ULLRAM_BANK1194_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1194_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1195 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1195_DATA_W 32 +#define RFC_ULLRAM_BANK1195_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1195_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1196 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1196_DATA_W 32 +#define RFC_ULLRAM_BANK1196_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1196_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1197 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1197_DATA_W 32 +#define RFC_ULLRAM_BANK1197_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1197_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1198 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1198_DATA_W 32 +#define RFC_ULLRAM_BANK1198_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1198_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1199 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1199_DATA_W 32 +#define RFC_ULLRAM_BANK1199_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1199_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1200 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1200_DATA_W 32 +#define RFC_ULLRAM_BANK1200_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1200_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1201 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1201_DATA_W 32 +#define RFC_ULLRAM_BANK1201_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1201_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1202 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1202_DATA_W 32 +#define RFC_ULLRAM_BANK1202_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1202_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1203 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1203_DATA_W 32 +#define RFC_ULLRAM_BANK1203_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1203_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1204 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1204_DATA_W 32 +#define RFC_ULLRAM_BANK1204_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1204_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1205 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1205_DATA_W 32 +#define RFC_ULLRAM_BANK1205_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1205_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1206 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1206_DATA_W 32 +#define RFC_ULLRAM_BANK1206_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1206_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1207 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1207_DATA_W 32 +#define RFC_ULLRAM_BANK1207_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1207_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1208 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1208_DATA_W 32 +#define RFC_ULLRAM_BANK1208_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1208_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1209 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1209_DATA_W 32 +#define RFC_ULLRAM_BANK1209_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1209_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1210 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1210_DATA_W 32 +#define RFC_ULLRAM_BANK1210_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1210_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1211 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1211_DATA_W 32 +#define RFC_ULLRAM_BANK1211_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1211_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1212 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1212_DATA_W 32 +#define RFC_ULLRAM_BANK1212_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1212_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1213 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1213_DATA_W 32 +#define RFC_ULLRAM_BANK1213_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1213_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1214 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1214_DATA_W 32 +#define RFC_ULLRAM_BANK1214_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1214_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1215 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1215_DATA_W 32 +#define RFC_ULLRAM_BANK1215_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1215_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1216 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1216_DATA_W 32 +#define RFC_ULLRAM_BANK1216_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1216_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1217 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1217_DATA_W 32 +#define RFC_ULLRAM_BANK1217_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1217_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1218 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1218_DATA_W 32 +#define RFC_ULLRAM_BANK1218_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1218_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1219 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1219_DATA_W 32 +#define RFC_ULLRAM_BANK1219_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1219_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1220 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1220_DATA_W 32 +#define RFC_ULLRAM_BANK1220_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1220_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1221 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1221_DATA_W 32 +#define RFC_ULLRAM_BANK1221_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1221_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1222 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1222_DATA_W 32 +#define RFC_ULLRAM_BANK1222_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1222_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1223 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1223_DATA_W 32 +#define RFC_ULLRAM_BANK1223_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1223_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1224 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1224_DATA_W 32 +#define RFC_ULLRAM_BANK1224_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1224_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1225 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1225_DATA_W 32 +#define RFC_ULLRAM_BANK1225_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1225_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1226 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1226_DATA_W 32 +#define RFC_ULLRAM_BANK1226_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1226_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1227 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1227_DATA_W 32 +#define RFC_ULLRAM_BANK1227_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1227_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1228 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1228_DATA_W 32 +#define RFC_ULLRAM_BANK1228_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1228_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1229 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1229_DATA_W 32 +#define RFC_ULLRAM_BANK1229_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1229_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1230 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1230_DATA_W 32 +#define RFC_ULLRAM_BANK1230_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1230_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1231 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1231_DATA_W 32 +#define RFC_ULLRAM_BANK1231_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1231_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1232 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1232_DATA_W 32 +#define RFC_ULLRAM_BANK1232_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1232_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1233 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1233_DATA_W 32 +#define RFC_ULLRAM_BANK1233_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1233_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1234 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1234_DATA_W 32 +#define RFC_ULLRAM_BANK1234_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1234_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1235 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1235_DATA_W 32 +#define RFC_ULLRAM_BANK1235_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1235_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1236 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1236_DATA_W 32 +#define RFC_ULLRAM_BANK1236_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1236_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1237 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1237_DATA_W 32 +#define RFC_ULLRAM_BANK1237_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1237_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1238 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1238_DATA_W 32 +#define RFC_ULLRAM_BANK1238_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1238_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1239 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1239_DATA_W 32 +#define RFC_ULLRAM_BANK1239_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1239_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1240 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1240_DATA_W 32 +#define RFC_ULLRAM_BANK1240_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1240_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1241 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1241_DATA_W 32 +#define RFC_ULLRAM_BANK1241_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1241_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1242 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1242_DATA_W 32 +#define RFC_ULLRAM_BANK1242_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1242_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1243 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1243_DATA_W 32 +#define RFC_ULLRAM_BANK1243_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1243_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1244 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1244_DATA_W 32 +#define RFC_ULLRAM_BANK1244_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1244_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1245 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1245_DATA_W 32 +#define RFC_ULLRAM_BANK1245_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1245_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1246 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1246_DATA_W 32 +#define RFC_ULLRAM_BANK1246_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1246_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1247 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1247_DATA_W 32 +#define RFC_ULLRAM_BANK1247_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1247_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1248 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1248_DATA_W 32 +#define RFC_ULLRAM_BANK1248_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1248_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1249 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1249_DATA_W 32 +#define RFC_ULLRAM_BANK1249_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1249_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1250 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1250_DATA_W 32 +#define RFC_ULLRAM_BANK1250_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1250_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1251 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1251_DATA_W 32 +#define RFC_ULLRAM_BANK1251_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1251_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1252 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1252_DATA_W 32 +#define RFC_ULLRAM_BANK1252_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1252_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1253 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1253_DATA_W 32 +#define RFC_ULLRAM_BANK1253_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1253_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1254 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1254_DATA_W 32 +#define RFC_ULLRAM_BANK1254_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1254_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1255 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1255_DATA_W 32 +#define RFC_ULLRAM_BANK1255_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1255_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1256 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1256_DATA_W 32 +#define RFC_ULLRAM_BANK1256_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1256_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1257 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1257_DATA_W 32 +#define RFC_ULLRAM_BANK1257_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1257_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1258 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1258_DATA_W 32 +#define RFC_ULLRAM_BANK1258_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1258_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1259 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1259_DATA_W 32 +#define RFC_ULLRAM_BANK1259_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1259_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1260 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1260_DATA_W 32 +#define RFC_ULLRAM_BANK1260_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1260_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1261 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1261_DATA_W 32 +#define RFC_ULLRAM_BANK1261_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1261_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1262 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1262_DATA_W 32 +#define RFC_ULLRAM_BANK1262_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1262_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1263 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1263_DATA_W 32 +#define RFC_ULLRAM_BANK1263_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1263_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1264 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1264_DATA_W 32 +#define RFC_ULLRAM_BANK1264_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1264_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1265 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1265_DATA_W 32 +#define RFC_ULLRAM_BANK1265_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1265_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1266 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1266_DATA_W 32 +#define RFC_ULLRAM_BANK1266_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1266_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1267 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1267_DATA_W 32 +#define RFC_ULLRAM_BANK1267_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1267_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1268 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1268_DATA_W 32 +#define RFC_ULLRAM_BANK1268_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1268_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1269 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1269_DATA_W 32 +#define RFC_ULLRAM_BANK1269_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1269_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1270 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1270_DATA_W 32 +#define RFC_ULLRAM_BANK1270_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1270_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1271 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1271_DATA_W 32 +#define RFC_ULLRAM_BANK1271_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1271_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1272 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1272_DATA_W 32 +#define RFC_ULLRAM_BANK1272_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1272_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1273 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1273_DATA_W 32 +#define RFC_ULLRAM_BANK1273_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1273_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1274 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1274_DATA_W 32 +#define RFC_ULLRAM_BANK1274_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1274_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1275 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1275_DATA_W 32 +#define RFC_ULLRAM_BANK1275_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1275_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1276 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1276_DATA_W 32 +#define RFC_ULLRAM_BANK1276_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1276_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1277 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1277_DATA_W 32 +#define RFC_ULLRAM_BANK1277_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1277_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1278 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1278_DATA_W 32 +#define RFC_ULLRAM_BANK1278_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1278_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1279 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1279_DATA_W 32 +#define RFC_ULLRAM_BANK1279_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1279_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1280 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1280_DATA_W 32 +#define RFC_ULLRAM_BANK1280_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1280_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1281 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1281_DATA_W 32 +#define RFC_ULLRAM_BANK1281_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1281_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1282 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1282_DATA_W 32 +#define RFC_ULLRAM_BANK1282_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1282_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1283 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1283_DATA_W 32 +#define RFC_ULLRAM_BANK1283_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1283_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1284 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1284_DATA_W 32 +#define RFC_ULLRAM_BANK1284_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1284_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1285 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1285_DATA_W 32 +#define RFC_ULLRAM_BANK1285_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1285_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1286 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1286_DATA_W 32 +#define RFC_ULLRAM_BANK1286_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1286_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1287 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1287_DATA_W 32 +#define RFC_ULLRAM_BANK1287_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1287_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1288 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1288_DATA_W 32 +#define RFC_ULLRAM_BANK1288_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1288_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1289 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1289_DATA_W 32 +#define RFC_ULLRAM_BANK1289_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1289_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1290 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1290_DATA_W 32 +#define RFC_ULLRAM_BANK1290_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1290_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1291 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1291_DATA_W 32 +#define RFC_ULLRAM_BANK1291_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1291_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1292 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1292_DATA_W 32 +#define RFC_ULLRAM_BANK1292_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1292_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1293 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1293_DATA_W 32 +#define RFC_ULLRAM_BANK1293_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1293_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1294 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1294_DATA_W 32 +#define RFC_ULLRAM_BANK1294_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1294_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1295 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1295_DATA_W 32 +#define RFC_ULLRAM_BANK1295_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1295_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1296 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1296_DATA_W 32 +#define RFC_ULLRAM_BANK1296_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1296_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1297 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1297_DATA_W 32 +#define RFC_ULLRAM_BANK1297_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1297_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1298 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1298_DATA_W 32 +#define RFC_ULLRAM_BANK1298_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1298_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1299 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1299_DATA_W 32 +#define RFC_ULLRAM_BANK1299_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1299_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1300 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1300_DATA_W 32 +#define RFC_ULLRAM_BANK1300_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1300_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1301 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1301_DATA_W 32 +#define RFC_ULLRAM_BANK1301_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1301_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1302 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1302_DATA_W 32 +#define RFC_ULLRAM_BANK1302_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1302_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1303 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1303_DATA_W 32 +#define RFC_ULLRAM_BANK1303_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1303_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1304 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1304_DATA_W 32 +#define RFC_ULLRAM_BANK1304_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1304_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1305 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1305_DATA_W 32 +#define RFC_ULLRAM_BANK1305_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1305_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1306 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1306_DATA_W 32 +#define RFC_ULLRAM_BANK1306_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1306_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1307 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1307_DATA_W 32 +#define RFC_ULLRAM_BANK1307_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1307_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1308 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1308_DATA_W 32 +#define RFC_ULLRAM_BANK1308_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1308_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1309 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1309_DATA_W 32 +#define RFC_ULLRAM_BANK1309_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1309_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1310 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1310_DATA_W 32 +#define RFC_ULLRAM_BANK1310_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1310_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1311 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1311_DATA_W 32 +#define RFC_ULLRAM_BANK1311_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1311_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1312 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1312_DATA_W 32 +#define RFC_ULLRAM_BANK1312_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1312_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1313 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1313_DATA_W 32 +#define RFC_ULLRAM_BANK1313_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1313_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1314 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1314_DATA_W 32 +#define RFC_ULLRAM_BANK1314_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1314_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1315 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1315_DATA_W 32 +#define RFC_ULLRAM_BANK1315_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1315_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1316 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1316_DATA_W 32 +#define RFC_ULLRAM_BANK1316_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1316_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1317 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1317_DATA_W 32 +#define RFC_ULLRAM_BANK1317_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1317_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1318 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1318_DATA_W 32 +#define RFC_ULLRAM_BANK1318_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1318_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1319 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1319_DATA_W 32 +#define RFC_ULLRAM_BANK1319_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1319_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1320 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1320_DATA_W 32 +#define RFC_ULLRAM_BANK1320_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1320_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1321 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1321_DATA_W 32 +#define RFC_ULLRAM_BANK1321_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1321_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1322 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1322_DATA_W 32 +#define RFC_ULLRAM_BANK1322_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1322_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1323 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1323_DATA_W 32 +#define RFC_ULLRAM_BANK1323_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1323_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1324 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1324_DATA_W 32 +#define RFC_ULLRAM_BANK1324_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1324_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1325 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1325_DATA_W 32 +#define RFC_ULLRAM_BANK1325_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1325_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1326 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1326_DATA_W 32 +#define RFC_ULLRAM_BANK1326_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1326_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1327 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1327_DATA_W 32 +#define RFC_ULLRAM_BANK1327_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1327_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1328 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1328_DATA_W 32 +#define RFC_ULLRAM_BANK1328_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1328_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1329 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1329_DATA_W 32 +#define RFC_ULLRAM_BANK1329_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1329_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1330 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1330_DATA_W 32 +#define RFC_ULLRAM_BANK1330_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1330_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1331 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1331_DATA_W 32 +#define RFC_ULLRAM_BANK1331_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1331_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1332 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1332_DATA_W 32 +#define RFC_ULLRAM_BANK1332_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1332_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1333 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1333_DATA_W 32 +#define RFC_ULLRAM_BANK1333_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1333_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1334 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1334_DATA_W 32 +#define RFC_ULLRAM_BANK1334_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1334_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1335 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1335_DATA_W 32 +#define RFC_ULLRAM_BANK1335_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1335_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1336 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1336_DATA_W 32 +#define RFC_ULLRAM_BANK1336_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1336_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1337 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1337_DATA_W 32 +#define RFC_ULLRAM_BANK1337_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1337_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1338 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1338_DATA_W 32 +#define RFC_ULLRAM_BANK1338_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1338_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1339 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1339_DATA_W 32 +#define RFC_ULLRAM_BANK1339_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1339_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1340 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1340_DATA_W 32 +#define RFC_ULLRAM_BANK1340_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1340_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1341 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1341_DATA_W 32 +#define RFC_ULLRAM_BANK1341_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1341_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1342 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1342_DATA_W 32 +#define RFC_ULLRAM_BANK1342_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1342_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1343 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1343_DATA_W 32 +#define RFC_ULLRAM_BANK1343_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1343_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1344 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1344_DATA_W 32 +#define RFC_ULLRAM_BANK1344_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1344_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1345 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1345_DATA_W 32 +#define RFC_ULLRAM_BANK1345_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1345_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1346 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1346_DATA_W 32 +#define RFC_ULLRAM_BANK1346_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1346_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1347 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1347_DATA_W 32 +#define RFC_ULLRAM_BANK1347_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1347_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1348 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1348_DATA_W 32 +#define RFC_ULLRAM_BANK1348_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1348_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1349 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1349_DATA_W 32 +#define RFC_ULLRAM_BANK1349_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1349_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1350 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1350_DATA_W 32 +#define RFC_ULLRAM_BANK1350_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1350_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1351 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1351_DATA_W 32 +#define RFC_ULLRAM_BANK1351_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1351_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1352 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1352_DATA_W 32 +#define RFC_ULLRAM_BANK1352_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1352_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1353 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1353_DATA_W 32 +#define RFC_ULLRAM_BANK1353_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1353_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1354 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1354_DATA_W 32 +#define RFC_ULLRAM_BANK1354_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1354_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1355 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1355_DATA_W 32 +#define RFC_ULLRAM_BANK1355_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1355_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1356 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1356_DATA_W 32 +#define RFC_ULLRAM_BANK1356_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1356_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1357 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1357_DATA_W 32 +#define RFC_ULLRAM_BANK1357_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1357_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1358 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1358_DATA_W 32 +#define RFC_ULLRAM_BANK1358_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1358_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1359 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1359_DATA_W 32 +#define RFC_ULLRAM_BANK1359_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1359_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1360 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1360_DATA_W 32 +#define RFC_ULLRAM_BANK1360_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1360_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1361 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1361_DATA_W 32 +#define RFC_ULLRAM_BANK1361_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1361_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1362 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1362_DATA_W 32 +#define RFC_ULLRAM_BANK1362_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1362_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1363 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1363_DATA_W 32 +#define RFC_ULLRAM_BANK1363_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1363_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1364 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1364_DATA_W 32 +#define RFC_ULLRAM_BANK1364_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1364_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1365 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1365_DATA_W 32 +#define RFC_ULLRAM_BANK1365_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1365_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1366 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1366_DATA_W 32 +#define RFC_ULLRAM_BANK1366_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1366_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1367 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1367_DATA_W 32 +#define RFC_ULLRAM_BANK1367_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1367_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1368 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1368_DATA_W 32 +#define RFC_ULLRAM_BANK1368_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1368_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1369 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1369_DATA_W 32 +#define RFC_ULLRAM_BANK1369_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1369_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1370 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1370_DATA_W 32 +#define RFC_ULLRAM_BANK1370_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1370_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1371 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1371_DATA_W 32 +#define RFC_ULLRAM_BANK1371_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1371_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1372 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1372_DATA_W 32 +#define RFC_ULLRAM_BANK1372_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1372_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1373 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1373_DATA_W 32 +#define RFC_ULLRAM_BANK1373_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1373_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1374 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1374_DATA_W 32 +#define RFC_ULLRAM_BANK1374_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1374_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1375 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1375_DATA_W 32 +#define RFC_ULLRAM_BANK1375_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1375_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1376 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1376_DATA_W 32 +#define RFC_ULLRAM_BANK1376_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1376_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1377 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1377_DATA_W 32 +#define RFC_ULLRAM_BANK1377_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1377_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1378 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1378_DATA_W 32 +#define RFC_ULLRAM_BANK1378_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1378_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1379 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1379_DATA_W 32 +#define RFC_ULLRAM_BANK1379_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1379_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1380 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1380_DATA_W 32 +#define RFC_ULLRAM_BANK1380_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1380_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1381 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1381_DATA_W 32 +#define RFC_ULLRAM_BANK1381_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1381_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1382 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1382_DATA_W 32 +#define RFC_ULLRAM_BANK1382_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1382_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1383 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1383_DATA_W 32 +#define RFC_ULLRAM_BANK1383_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1383_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1384 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1384_DATA_W 32 +#define RFC_ULLRAM_BANK1384_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1384_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1385 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1385_DATA_W 32 +#define RFC_ULLRAM_BANK1385_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1385_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1386 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1386_DATA_W 32 +#define RFC_ULLRAM_BANK1386_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1386_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1387 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1387_DATA_W 32 +#define RFC_ULLRAM_BANK1387_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1387_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1388 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1388_DATA_W 32 +#define RFC_ULLRAM_BANK1388_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1388_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1389 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1389_DATA_W 32 +#define RFC_ULLRAM_BANK1389_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1389_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1390 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1390_DATA_W 32 +#define RFC_ULLRAM_BANK1390_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1390_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1391 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1391_DATA_W 32 +#define RFC_ULLRAM_BANK1391_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1391_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1392 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1392_DATA_W 32 +#define RFC_ULLRAM_BANK1392_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1392_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1393 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1393_DATA_W 32 +#define RFC_ULLRAM_BANK1393_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1393_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1394 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1394_DATA_W 32 +#define RFC_ULLRAM_BANK1394_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1394_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1395 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1395_DATA_W 32 +#define RFC_ULLRAM_BANK1395_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1395_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1396 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1396_DATA_W 32 +#define RFC_ULLRAM_BANK1396_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1396_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1397 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1397_DATA_W 32 +#define RFC_ULLRAM_BANK1397_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1397_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1398 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1398_DATA_W 32 +#define RFC_ULLRAM_BANK1398_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1398_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1399 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1399_DATA_W 32 +#define RFC_ULLRAM_BANK1399_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1399_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1400 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1400_DATA_W 32 +#define RFC_ULLRAM_BANK1400_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1400_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1401 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1401_DATA_W 32 +#define RFC_ULLRAM_BANK1401_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1401_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1402 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1402_DATA_W 32 +#define RFC_ULLRAM_BANK1402_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1402_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1403 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1403_DATA_W 32 +#define RFC_ULLRAM_BANK1403_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1403_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1404 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1404_DATA_W 32 +#define RFC_ULLRAM_BANK1404_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1404_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1405 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1405_DATA_W 32 +#define RFC_ULLRAM_BANK1405_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1405_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1406 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1406_DATA_W 32 +#define RFC_ULLRAM_BANK1406_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1406_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1407 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1407_DATA_W 32 +#define RFC_ULLRAM_BANK1407_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1407_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1408 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1408_DATA_W 32 +#define RFC_ULLRAM_BANK1408_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1408_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1409 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1409_DATA_W 32 +#define RFC_ULLRAM_BANK1409_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1409_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1410 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1410_DATA_W 32 +#define RFC_ULLRAM_BANK1410_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1410_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1411 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1411_DATA_W 32 +#define RFC_ULLRAM_BANK1411_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1411_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1412 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1412_DATA_W 32 +#define RFC_ULLRAM_BANK1412_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1412_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1413 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1413_DATA_W 32 +#define RFC_ULLRAM_BANK1413_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1413_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1414 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1414_DATA_W 32 +#define RFC_ULLRAM_BANK1414_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1414_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1415 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1415_DATA_W 32 +#define RFC_ULLRAM_BANK1415_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1415_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1416 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1416_DATA_W 32 +#define RFC_ULLRAM_BANK1416_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1416_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1417 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1417_DATA_W 32 +#define RFC_ULLRAM_BANK1417_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1417_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1418 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1418_DATA_W 32 +#define RFC_ULLRAM_BANK1418_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1418_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1419 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1419_DATA_W 32 +#define RFC_ULLRAM_BANK1419_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1419_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1420 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1420_DATA_W 32 +#define RFC_ULLRAM_BANK1420_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1420_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1421 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1421_DATA_W 32 +#define RFC_ULLRAM_BANK1421_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1421_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1422 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1422_DATA_W 32 +#define RFC_ULLRAM_BANK1422_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1422_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1423 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1423_DATA_W 32 +#define RFC_ULLRAM_BANK1423_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1423_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1424 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1424_DATA_W 32 +#define RFC_ULLRAM_BANK1424_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1424_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1425 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1425_DATA_W 32 +#define RFC_ULLRAM_BANK1425_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1425_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1426 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1426_DATA_W 32 +#define RFC_ULLRAM_BANK1426_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1426_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1427 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1427_DATA_W 32 +#define RFC_ULLRAM_BANK1427_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1427_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1428 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1428_DATA_W 32 +#define RFC_ULLRAM_BANK1428_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1428_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1429 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1429_DATA_W 32 +#define RFC_ULLRAM_BANK1429_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1429_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1430 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1430_DATA_W 32 +#define RFC_ULLRAM_BANK1430_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1430_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1431 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1431_DATA_W 32 +#define RFC_ULLRAM_BANK1431_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1431_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1432 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1432_DATA_W 32 +#define RFC_ULLRAM_BANK1432_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1432_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1433 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1433_DATA_W 32 +#define RFC_ULLRAM_BANK1433_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1433_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1434 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1434_DATA_W 32 +#define RFC_ULLRAM_BANK1434_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1434_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1435 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1435_DATA_W 32 +#define RFC_ULLRAM_BANK1435_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1435_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1436 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1436_DATA_W 32 +#define RFC_ULLRAM_BANK1436_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1436_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1437 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1437_DATA_W 32 +#define RFC_ULLRAM_BANK1437_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1437_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1438 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1438_DATA_W 32 +#define RFC_ULLRAM_BANK1438_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1438_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1439 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1439_DATA_W 32 +#define RFC_ULLRAM_BANK1439_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1439_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1440 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1440_DATA_W 32 +#define RFC_ULLRAM_BANK1440_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1440_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1441 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1441_DATA_W 32 +#define RFC_ULLRAM_BANK1441_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1441_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1442 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1442_DATA_W 32 +#define RFC_ULLRAM_BANK1442_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1442_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1443 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1443_DATA_W 32 +#define RFC_ULLRAM_BANK1443_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1443_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1444 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1444_DATA_W 32 +#define RFC_ULLRAM_BANK1444_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1444_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1445 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1445_DATA_W 32 +#define RFC_ULLRAM_BANK1445_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1445_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1446 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1446_DATA_W 32 +#define RFC_ULLRAM_BANK1446_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1446_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1447 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1447_DATA_W 32 +#define RFC_ULLRAM_BANK1447_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1447_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1448 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1448_DATA_W 32 +#define RFC_ULLRAM_BANK1448_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1448_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1449 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1449_DATA_W 32 +#define RFC_ULLRAM_BANK1449_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1449_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1450 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1450_DATA_W 32 +#define RFC_ULLRAM_BANK1450_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1450_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1451 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1451_DATA_W 32 +#define RFC_ULLRAM_BANK1451_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1451_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1452 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1452_DATA_W 32 +#define RFC_ULLRAM_BANK1452_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1452_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1453 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1453_DATA_W 32 +#define RFC_ULLRAM_BANK1453_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1453_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1454 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1454_DATA_W 32 +#define RFC_ULLRAM_BANK1454_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1454_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1455 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1455_DATA_W 32 +#define RFC_ULLRAM_BANK1455_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1455_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1456 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1456_DATA_W 32 +#define RFC_ULLRAM_BANK1456_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1456_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1457 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1457_DATA_W 32 +#define RFC_ULLRAM_BANK1457_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1457_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1458 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1458_DATA_W 32 +#define RFC_ULLRAM_BANK1458_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1458_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1459 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1459_DATA_W 32 +#define RFC_ULLRAM_BANK1459_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1459_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1460 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1460_DATA_W 32 +#define RFC_ULLRAM_BANK1460_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1460_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1461 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1461_DATA_W 32 +#define RFC_ULLRAM_BANK1461_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1461_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1462 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1462_DATA_W 32 +#define RFC_ULLRAM_BANK1462_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1462_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1463 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1463_DATA_W 32 +#define RFC_ULLRAM_BANK1463_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1463_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1464 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1464_DATA_W 32 +#define RFC_ULLRAM_BANK1464_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1464_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1465 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1465_DATA_W 32 +#define RFC_ULLRAM_BANK1465_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1465_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1466 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1466_DATA_W 32 +#define RFC_ULLRAM_BANK1466_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1466_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1467 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1467_DATA_W 32 +#define RFC_ULLRAM_BANK1467_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1467_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1468 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1468_DATA_W 32 +#define RFC_ULLRAM_BANK1468_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1468_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1469 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1469_DATA_W 32 +#define RFC_ULLRAM_BANK1469_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1469_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1470 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1470_DATA_W 32 +#define RFC_ULLRAM_BANK1470_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1470_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1471 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1471_DATA_W 32 +#define RFC_ULLRAM_BANK1471_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1471_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1472 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1472_DATA_W 32 +#define RFC_ULLRAM_BANK1472_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1472_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1473 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1473_DATA_W 32 +#define RFC_ULLRAM_BANK1473_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1473_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1474 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1474_DATA_W 32 +#define RFC_ULLRAM_BANK1474_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1474_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1475 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1475_DATA_W 32 +#define RFC_ULLRAM_BANK1475_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1475_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1476 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1476_DATA_W 32 +#define RFC_ULLRAM_BANK1476_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1476_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1477 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1477_DATA_W 32 +#define RFC_ULLRAM_BANK1477_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1477_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1478 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1478_DATA_W 32 +#define RFC_ULLRAM_BANK1478_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1478_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1479 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1479_DATA_W 32 +#define RFC_ULLRAM_BANK1479_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1479_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1480 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1480_DATA_W 32 +#define RFC_ULLRAM_BANK1480_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1480_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1481 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1481_DATA_W 32 +#define RFC_ULLRAM_BANK1481_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1481_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1482 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1482_DATA_W 32 +#define RFC_ULLRAM_BANK1482_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1482_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1483 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1483_DATA_W 32 +#define RFC_ULLRAM_BANK1483_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1483_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1484 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1484_DATA_W 32 +#define RFC_ULLRAM_BANK1484_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1484_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1485 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1485_DATA_W 32 +#define RFC_ULLRAM_BANK1485_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1485_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1486 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1486_DATA_W 32 +#define RFC_ULLRAM_BANK1486_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1486_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1487 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1487_DATA_W 32 +#define RFC_ULLRAM_BANK1487_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1487_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1488 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1488_DATA_W 32 +#define RFC_ULLRAM_BANK1488_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1488_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1489 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1489_DATA_W 32 +#define RFC_ULLRAM_BANK1489_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1489_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1490 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1490_DATA_W 32 +#define RFC_ULLRAM_BANK1490_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1490_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1491 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1491_DATA_W 32 +#define RFC_ULLRAM_BANK1491_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1491_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1492 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1492_DATA_W 32 +#define RFC_ULLRAM_BANK1492_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1492_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1493 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1493_DATA_W 32 +#define RFC_ULLRAM_BANK1493_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1493_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1494 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1494_DATA_W 32 +#define RFC_ULLRAM_BANK1494_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1494_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1495 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1495_DATA_W 32 +#define RFC_ULLRAM_BANK1495_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1495_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1496 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1496_DATA_W 32 +#define RFC_ULLRAM_BANK1496_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1496_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1497 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1497_DATA_W 32 +#define RFC_ULLRAM_BANK1497_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1497_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1498 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1498_DATA_W 32 +#define RFC_ULLRAM_BANK1498_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1498_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1499 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1499_DATA_W 32 +#define RFC_ULLRAM_BANK1499_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1499_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1500 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1500_DATA_W 32 +#define RFC_ULLRAM_BANK1500_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1500_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1501 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1501_DATA_W 32 +#define RFC_ULLRAM_BANK1501_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1501_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1502 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1502_DATA_W 32 +#define RFC_ULLRAM_BANK1502_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1502_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1503 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1503_DATA_W 32 +#define RFC_ULLRAM_BANK1503_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1503_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1504 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1504_DATA_W 32 +#define RFC_ULLRAM_BANK1504_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1504_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1505 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1505_DATA_W 32 +#define RFC_ULLRAM_BANK1505_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1505_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1506 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1506_DATA_W 32 +#define RFC_ULLRAM_BANK1506_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1506_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1507 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1507_DATA_W 32 +#define RFC_ULLRAM_BANK1507_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1507_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1508 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1508_DATA_W 32 +#define RFC_ULLRAM_BANK1508_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1508_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1509 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1509_DATA_W 32 +#define RFC_ULLRAM_BANK1509_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1509_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1510 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1510_DATA_W 32 +#define RFC_ULLRAM_BANK1510_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1510_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1511 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1511_DATA_W 32 +#define RFC_ULLRAM_BANK1511_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1511_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1512 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1512_DATA_W 32 +#define RFC_ULLRAM_BANK1512_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1512_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1513 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1513_DATA_W 32 +#define RFC_ULLRAM_BANK1513_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1513_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1514 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1514_DATA_W 32 +#define RFC_ULLRAM_BANK1514_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1514_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1515 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1515_DATA_W 32 +#define RFC_ULLRAM_BANK1515_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1515_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1516 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1516_DATA_W 32 +#define RFC_ULLRAM_BANK1516_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1516_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1517 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1517_DATA_W 32 +#define RFC_ULLRAM_BANK1517_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1517_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1518 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1518_DATA_W 32 +#define RFC_ULLRAM_BANK1518_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1518_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1519 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1519_DATA_W 32 +#define RFC_ULLRAM_BANK1519_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1519_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1520 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1520_DATA_W 32 +#define RFC_ULLRAM_BANK1520_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1520_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1521 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1521_DATA_W 32 +#define RFC_ULLRAM_BANK1521_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1521_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1522 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1522_DATA_W 32 +#define RFC_ULLRAM_BANK1522_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1522_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1523 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1523_DATA_W 32 +#define RFC_ULLRAM_BANK1523_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1523_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1524 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1524_DATA_W 32 +#define RFC_ULLRAM_BANK1524_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1524_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1525 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1525_DATA_W 32 +#define RFC_ULLRAM_BANK1525_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1525_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1526 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1526_DATA_W 32 +#define RFC_ULLRAM_BANK1526_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1526_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1527 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1527_DATA_W 32 +#define RFC_ULLRAM_BANK1527_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1527_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1528 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1528_DATA_W 32 +#define RFC_ULLRAM_BANK1528_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1528_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1529 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1529_DATA_W 32 +#define RFC_ULLRAM_BANK1529_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1529_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1530 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1530_DATA_W 32 +#define RFC_ULLRAM_BANK1530_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1530_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1531 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1531_DATA_W 32 +#define RFC_ULLRAM_BANK1531_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1531_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1532 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1532_DATA_W 32 +#define RFC_ULLRAM_BANK1532_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1532_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1533 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1533_DATA_W 32 +#define RFC_ULLRAM_BANK1533_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1533_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1534 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1534_DATA_W 32 +#define RFC_ULLRAM_BANK1534_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1534_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1535 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1535_DATA_W 32 +#define RFC_ULLRAM_BANK1535_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1535_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1536 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1536_DATA_W 32 +#define RFC_ULLRAM_BANK1536_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1536_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1537 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1537_DATA_W 32 +#define RFC_ULLRAM_BANK1537_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1537_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1538 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1538_DATA_W 32 +#define RFC_ULLRAM_BANK1538_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1538_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1539 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1539_DATA_W 32 +#define RFC_ULLRAM_BANK1539_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1539_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1540 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1540_DATA_W 32 +#define RFC_ULLRAM_BANK1540_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1540_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1541 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1541_DATA_W 32 +#define RFC_ULLRAM_BANK1541_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1541_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1542 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1542_DATA_W 32 +#define RFC_ULLRAM_BANK1542_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1542_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1543 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1543_DATA_W 32 +#define RFC_ULLRAM_BANK1543_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1543_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1544 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1544_DATA_W 32 +#define RFC_ULLRAM_BANK1544_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1544_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1545 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1545_DATA_W 32 +#define RFC_ULLRAM_BANK1545_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1545_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1546 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1546_DATA_W 32 +#define RFC_ULLRAM_BANK1546_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1546_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1547 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1547_DATA_W 32 +#define RFC_ULLRAM_BANK1547_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1547_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1548 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1548_DATA_W 32 +#define RFC_ULLRAM_BANK1548_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1548_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1549 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1549_DATA_W 32 +#define RFC_ULLRAM_BANK1549_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1549_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1550 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1550_DATA_W 32 +#define RFC_ULLRAM_BANK1550_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1550_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1551 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1551_DATA_W 32 +#define RFC_ULLRAM_BANK1551_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1551_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1552 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1552_DATA_W 32 +#define RFC_ULLRAM_BANK1552_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1552_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1553 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1553_DATA_W 32 +#define RFC_ULLRAM_BANK1553_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1553_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1554 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1554_DATA_W 32 +#define RFC_ULLRAM_BANK1554_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1554_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1555 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1555_DATA_W 32 +#define RFC_ULLRAM_BANK1555_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1555_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1556 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1556_DATA_W 32 +#define RFC_ULLRAM_BANK1556_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1556_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1557 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1557_DATA_W 32 +#define RFC_ULLRAM_BANK1557_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1557_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1558 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1558_DATA_W 32 +#define RFC_ULLRAM_BANK1558_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1558_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1559 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1559_DATA_W 32 +#define RFC_ULLRAM_BANK1559_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1559_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1560 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1560_DATA_W 32 +#define RFC_ULLRAM_BANK1560_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1560_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1561 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1561_DATA_W 32 +#define RFC_ULLRAM_BANK1561_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1561_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1562 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1562_DATA_W 32 +#define RFC_ULLRAM_BANK1562_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1562_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1563 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1563_DATA_W 32 +#define RFC_ULLRAM_BANK1563_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1563_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1564 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1564_DATA_W 32 +#define RFC_ULLRAM_BANK1564_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1564_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1565 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1565_DATA_W 32 +#define RFC_ULLRAM_BANK1565_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1565_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1566 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1566_DATA_W 32 +#define RFC_ULLRAM_BANK1566_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1566_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1567 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1567_DATA_W 32 +#define RFC_ULLRAM_BANK1567_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1567_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1568 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1568_DATA_W 32 +#define RFC_ULLRAM_BANK1568_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1568_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1569 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1569_DATA_W 32 +#define RFC_ULLRAM_BANK1569_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1569_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1570 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1570_DATA_W 32 +#define RFC_ULLRAM_BANK1570_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1570_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1571 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1571_DATA_W 32 +#define RFC_ULLRAM_BANK1571_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1571_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1572 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1572_DATA_W 32 +#define RFC_ULLRAM_BANK1572_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1572_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1573 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1573_DATA_W 32 +#define RFC_ULLRAM_BANK1573_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1573_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1574 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1574_DATA_W 32 +#define RFC_ULLRAM_BANK1574_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1574_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1575 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1575_DATA_W 32 +#define RFC_ULLRAM_BANK1575_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1575_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1576 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1576_DATA_W 32 +#define RFC_ULLRAM_BANK1576_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1576_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1577 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1577_DATA_W 32 +#define RFC_ULLRAM_BANK1577_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1577_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1578 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1578_DATA_W 32 +#define RFC_ULLRAM_BANK1578_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1578_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1579 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1579_DATA_W 32 +#define RFC_ULLRAM_BANK1579_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1579_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1580 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1580_DATA_W 32 +#define RFC_ULLRAM_BANK1580_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1580_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1581 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1581_DATA_W 32 +#define RFC_ULLRAM_BANK1581_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1581_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1582 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1582_DATA_W 32 +#define RFC_ULLRAM_BANK1582_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1582_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1583 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1583_DATA_W 32 +#define RFC_ULLRAM_BANK1583_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1583_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1584 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1584_DATA_W 32 +#define RFC_ULLRAM_BANK1584_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1584_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1585 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1585_DATA_W 32 +#define RFC_ULLRAM_BANK1585_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1585_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1586 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1586_DATA_W 32 +#define RFC_ULLRAM_BANK1586_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1586_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1587 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1587_DATA_W 32 +#define RFC_ULLRAM_BANK1587_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1587_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1588 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1588_DATA_W 32 +#define RFC_ULLRAM_BANK1588_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1588_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1589 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1589_DATA_W 32 +#define RFC_ULLRAM_BANK1589_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1589_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1590 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1590_DATA_W 32 +#define RFC_ULLRAM_BANK1590_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1590_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1591 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1591_DATA_W 32 +#define RFC_ULLRAM_BANK1591_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1591_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1592 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1592_DATA_W 32 +#define RFC_ULLRAM_BANK1592_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1592_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1593 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1593_DATA_W 32 +#define RFC_ULLRAM_BANK1593_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1593_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1594 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1594_DATA_W 32 +#define RFC_ULLRAM_BANK1594_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1594_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1595 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1595_DATA_W 32 +#define RFC_ULLRAM_BANK1595_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1595_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1596 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1596_DATA_W 32 +#define RFC_ULLRAM_BANK1596_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1596_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1597 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1597_DATA_W 32 +#define RFC_ULLRAM_BANK1597_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1597_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1598 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1598_DATA_W 32 +#define RFC_ULLRAM_BANK1598_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1598_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1599 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1599_DATA_W 32 +#define RFC_ULLRAM_BANK1599_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1599_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1600 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1600_DATA_W 32 +#define RFC_ULLRAM_BANK1600_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1600_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1601 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1601_DATA_W 32 +#define RFC_ULLRAM_BANK1601_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1601_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1602 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1602_DATA_W 32 +#define RFC_ULLRAM_BANK1602_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1602_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1603 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1603_DATA_W 32 +#define RFC_ULLRAM_BANK1603_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1603_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1604 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1604_DATA_W 32 +#define RFC_ULLRAM_BANK1604_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1604_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1605 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1605_DATA_W 32 +#define RFC_ULLRAM_BANK1605_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1605_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1606 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1606_DATA_W 32 +#define RFC_ULLRAM_BANK1606_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1606_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1607 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1607_DATA_W 32 +#define RFC_ULLRAM_BANK1607_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1607_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1608 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1608_DATA_W 32 +#define RFC_ULLRAM_BANK1608_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1608_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1609 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1609_DATA_W 32 +#define RFC_ULLRAM_BANK1609_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1609_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1610 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1610_DATA_W 32 +#define RFC_ULLRAM_BANK1610_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1610_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1611 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1611_DATA_W 32 +#define RFC_ULLRAM_BANK1611_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1611_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1612 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1612_DATA_W 32 +#define RFC_ULLRAM_BANK1612_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1612_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1613 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1613_DATA_W 32 +#define RFC_ULLRAM_BANK1613_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1613_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1614 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1614_DATA_W 32 +#define RFC_ULLRAM_BANK1614_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1614_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1615 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1615_DATA_W 32 +#define RFC_ULLRAM_BANK1615_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1615_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1616 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1616_DATA_W 32 +#define RFC_ULLRAM_BANK1616_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1616_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1617 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1617_DATA_W 32 +#define RFC_ULLRAM_BANK1617_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1617_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1618 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1618_DATA_W 32 +#define RFC_ULLRAM_BANK1618_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1618_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1619 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1619_DATA_W 32 +#define RFC_ULLRAM_BANK1619_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1619_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1620 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1620_DATA_W 32 +#define RFC_ULLRAM_BANK1620_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1620_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1621 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1621_DATA_W 32 +#define RFC_ULLRAM_BANK1621_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1621_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1622 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1622_DATA_W 32 +#define RFC_ULLRAM_BANK1622_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1622_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1623 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1623_DATA_W 32 +#define RFC_ULLRAM_BANK1623_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1623_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1624 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1624_DATA_W 32 +#define RFC_ULLRAM_BANK1624_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1624_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1625 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1625_DATA_W 32 +#define RFC_ULLRAM_BANK1625_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1625_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1626 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1626_DATA_W 32 +#define RFC_ULLRAM_BANK1626_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1626_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1627 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1627_DATA_W 32 +#define RFC_ULLRAM_BANK1627_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1627_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1628 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1628_DATA_W 32 +#define RFC_ULLRAM_BANK1628_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1628_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1629 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1629_DATA_W 32 +#define RFC_ULLRAM_BANK1629_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1629_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1630 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1630_DATA_W 32 +#define RFC_ULLRAM_BANK1630_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1630_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1631 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1631_DATA_W 32 +#define RFC_ULLRAM_BANK1631_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1631_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1632 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1632_DATA_W 32 +#define RFC_ULLRAM_BANK1632_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1632_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1633 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1633_DATA_W 32 +#define RFC_ULLRAM_BANK1633_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1633_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1634 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1634_DATA_W 32 +#define RFC_ULLRAM_BANK1634_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1634_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1635 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1635_DATA_W 32 +#define RFC_ULLRAM_BANK1635_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1635_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1636 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1636_DATA_W 32 +#define RFC_ULLRAM_BANK1636_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1636_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1637 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1637_DATA_W 32 +#define RFC_ULLRAM_BANK1637_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1637_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1638 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1638_DATA_W 32 +#define RFC_ULLRAM_BANK1638_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1638_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1639 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1639_DATA_W 32 +#define RFC_ULLRAM_BANK1639_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1639_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1640 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1640_DATA_W 32 +#define RFC_ULLRAM_BANK1640_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1640_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1641 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1641_DATA_W 32 +#define RFC_ULLRAM_BANK1641_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1641_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1642 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1642_DATA_W 32 +#define RFC_ULLRAM_BANK1642_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1642_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1643 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1643_DATA_W 32 +#define RFC_ULLRAM_BANK1643_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1643_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1644 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1644_DATA_W 32 +#define RFC_ULLRAM_BANK1644_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1644_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1645 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1645_DATA_W 32 +#define RFC_ULLRAM_BANK1645_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1645_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1646 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1646_DATA_W 32 +#define RFC_ULLRAM_BANK1646_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1646_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1647 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1647_DATA_W 32 +#define RFC_ULLRAM_BANK1647_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1647_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1648 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1648_DATA_W 32 +#define RFC_ULLRAM_BANK1648_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1648_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1649 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1649_DATA_W 32 +#define RFC_ULLRAM_BANK1649_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1649_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1650 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1650_DATA_W 32 +#define RFC_ULLRAM_BANK1650_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1650_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1651 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1651_DATA_W 32 +#define RFC_ULLRAM_BANK1651_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1651_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1652 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1652_DATA_W 32 +#define RFC_ULLRAM_BANK1652_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1652_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1653 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1653_DATA_W 32 +#define RFC_ULLRAM_BANK1653_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1653_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1654 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1654_DATA_W 32 +#define RFC_ULLRAM_BANK1654_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1654_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1655 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1655_DATA_W 32 +#define RFC_ULLRAM_BANK1655_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1655_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1656 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1656_DATA_W 32 +#define RFC_ULLRAM_BANK1656_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1656_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1657 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1657_DATA_W 32 +#define RFC_ULLRAM_BANK1657_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1657_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1658 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1658_DATA_W 32 +#define RFC_ULLRAM_BANK1658_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1658_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1659 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1659_DATA_W 32 +#define RFC_ULLRAM_BANK1659_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1659_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1660 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1660_DATA_W 32 +#define RFC_ULLRAM_BANK1660_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1660_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1661 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1661_DATA_W 32 +#define RFC_ULLRAM_BANK1661_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1661_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1662 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1662_DATA_W 32 +#define RFC_ULLRAM_BANK1662_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1662_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1663 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1663_DATA_W 32 +#define RFC_ULLRAM_BANK1663_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1663_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1664 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1664_DATA_W 32 +#define RFC_ULLRAM_BANK1664_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1664_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1665 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1665_DATA_W 32 +#define RFC_ULLRAM_BANK1665_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1665_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1666 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1666_DATA_W 32 +#define RFC_ULLRAM_BANK1666_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1666_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1667 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1667_DATA_W 32 +#define RFC_ULLRAM_BANK1667_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1667_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1668 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1668_DATA_W 32 +#define RFC_ULLRAM_BANK1668_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1668_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1669 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1669_DATA_W 32 +#define RFC_ULLRAM_BANK1669_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1669_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1670 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1670_DATA_W 32 +#define RFC_ULLRAM_BANK1670_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1670_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1671 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1671_DATA_W 32 +#define RFC_ULLRAM_BANK1671_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1671_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1672 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1672_DATA_W 32 +#define RFC_ULLRAM_BANK1672_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1672_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1673 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1673_DATA_W 32 +#define RFC_ULLRAM_BANK1673_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1673_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1674 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1674_DATA_W 32 +#define RFC_ULLRAM_BANK1674_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1674_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1675 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1675_DATA_W 32 +#define RFC_ULLRAM_BANK1675_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1675_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1676 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1676_DATA_W 32 +#define RFC_ULLRAM_BANK1676_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1676_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1677 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1677_DATA_W 32 +#define RFC_ULLRAM_BANK1677_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1677_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1678 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1678_DATA_W 32 +#define RFC_ULLRAM_BANK1678_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1678_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1679 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1679_DATA_W 32 +#define RFC_ULLRAM_BANK1679_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1679_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1680 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1680_DATA_W 32 +#define RFC_ULLRAM_BANK1680_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1680_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1681 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1681_DATA_W 32 +#define RFC_ULLRAM_BANK1681_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1681_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1682 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1682_DATA_W 32 +#define RFC_ULLRAM_BANK1682_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1682_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1683 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1683_DATA_W 32 +#define RFC_ULLRAM_BANK1683_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1683_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1684 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1684_DATA_W 32 +#define RFC_ULLRAM_BANK1684_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1684_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1685 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1685_DATA_W 32 +#define RFC_ULLRAM_BANK1685_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1685_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1686 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1686_DATA_W 32 +#define RFC_ULLRAM_BANK1686_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1686_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1687 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1687_DATA_W 32 +#define RFC_ULLRAM_BANK1687_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1687_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1688 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1688_DATA_W 32 +#define RFC_ULLRAM_BANK1688_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1688_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1689 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1689_DATA_W 32 +#define RFC_ULLRAM_BANK1689_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1689_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1690 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1690_DATA_W 32 +#define RFC_ULLRAM_BANK1690_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1690_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1691 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1691_DATA_W 32 +#define RFC_ULLRAM_BANK1691_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1691_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1692 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1692_DATA_W 32 +#define RFC_ULLRAM_BANK1692_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1692_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1693 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1693_DATA_W 32 +#define RFC_ULLRAM_BANK1693_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1693_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1694 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1694_DATA_W 32 +#define RFC_ULLRAM_BANK1694_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1694_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1695 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1695_DATA_W 32 +#define RFC_ULLRAM_BANK1695_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1695_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1696 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1696_DATA_W 32 +#define RFC_ULLRAM_BANK1696_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1696_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1697 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1697_DATA_W 32 +#define RFC_ULLRAM_BANK1697_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1697_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1698 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1698_DATA_W 32 +#define RFC_ULLRAM_BANK1698_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1698_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1699 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1699_DATA_W 32 +#define RFC_ULLRAM_BANK1699_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1699_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1700 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1700_DATA_W 32 +#define RFC_ULLRAM_BANK1700_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1700_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1701 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1701_DATA_W 32 +#define RFC_ULLRAM_BANK1701_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1701_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1702 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1702_DATA_W 32 +#define RFC_ULLRAM_BANK1702_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1702_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1703 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1703_DATA_W 32 +#define RFC_ULLRAM_BANK1703_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1703_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1704 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1704_DATA_W 32 +#define RFC_ULLRAM_BANK1704_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1704_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1705 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1705_DATA_W 32 +#define RFC_ULLRAM_BANK1705_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1705_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1706 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1706_DATA_W 32 +#define RFC_ULLRAM_BANK1706_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1706_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1707 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1707_DATA_W 32 +#define RFC_ULLRAM_BANK1707_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1707_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1708 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1708_DATA_W 32 +#define RFC_ULLRAM_BANK1708_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1708_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1709 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1709_DATA_W 32 +#define RFC_ULLRAM_BANK1709_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1709_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1710 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1710_DATA_W 32 +#define RFC_ULLRAM_BANK1710_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1710_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1711 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1711_DATA_W 32 +#define RFC_ULLRAM_BANK1711_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1711_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1712 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1712_DATA_W 32 +#define RFC_ULLRAM_BANK1712_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1712_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1713 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1713_DATA_W 32 +#define RFC_ULLRAM_BANK1713_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1713_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1714 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1714_DATA_W 32 +#define RFC_ULLRAM_BANK1714_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1714_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1715 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1715_DATA_W 32 +#define RFC_ULLRAM_BANK1715_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1715_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1716 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1716_DATA_W 32 +#define RFC_ULLRAM_BANK1716_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1716_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1717 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1717_DATA_W 32 +#define RFC_ULLRAM_BANK1717_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1717_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1718 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1718_DATA_W 32 +#define RFC_ULLRAM_BANK1718_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1718_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1719 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1719_DATA_W 32 +#define RFC_ULLRAM_BANK1719_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1719_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1720 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1720_DATA_W 32 +#define RFC_ULLRAM_BANK1720_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1720_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1721 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1721_DATA_W 32 +#define RFC_ULLRAM_BANK1721_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1721_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1722 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1722_DATA_W 32 +#define RFC_ULLRAM_BANK1722_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1722_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1723 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1723_DATA_W 32 +#define RFC_ULLRAM_BANK1723_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1723_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1724 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1724_DATA_W 32 +#define RFC_ULLRAM_BANK1724_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1724_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1725 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1725_DATA_W 32 +#define RFC_ULLRAM_BANK1725_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1725_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1726 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1726_DATA_W 32 +#define RFC_ULLRAM_BANK1726_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1726_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1727 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1727_DATA_W 32 +#define RFC_ULLRAM_BANK1727_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1727_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1728 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1728_DATA_W 32 +#define RFC_ULLRAM_BANK1728_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1728_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1729 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1729_DATA_W 32 +#define RFC_ULLRAM_BANK1729_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1729_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1730 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1730_DATA_W 32 +#define RFC_ULLRAM_BANK1730_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1730_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1731 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1731_DATA_W 32 +#define RFC_ULLRAM_BANK1731_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1731_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1732 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1732_DATA_W 32 +#define RFC_ULLRAM_BANK1732_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1732_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1733 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1733_DATA_W 32 +#define RFC_ULLRAM_BANK1733_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1733_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1734 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1734_DATA_W 32 +#define RFC_ULLRAM_BANK1734_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1734_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1735 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1735_DATA_W 32 +#define RFC_ULLRAM_BANK1735_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1735_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1736 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1736_DATA_W 32 +#define RFC_ULLRAM_BANK1736_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1736_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1737 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1737_DATA_W 32 +#define RFC_ULLRAM_BANK1737_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1737_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1738 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1738_DATA_W 32 +#define RFC_ULLRAM_BANK1738_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1738_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1739 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1739_DATA_W 32 +#define RFC_ULLRAM_BANK1739_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1739_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1740 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1740_DATA_W 32 +#define RFC_ULLRAM_BANK1740_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1740_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1741 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1741_DATA_W 32 +#define RFC_ULLRAM_BANK1741_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1741_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1742 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1742_DATA_W 32 +#define RFC_ULLRAM_BANK1742_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1742_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1743 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1743_DATA_W 32 +#define RFC_ULLRAM_BANK1743_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1743_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1744 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1744_DATA_W 32 +#define RFC_ULLRAM_BANK1744_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1744_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1745 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1745_DATA_W 32 +#define RFC_ULLRAM_BANK1745_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1745_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1746 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1746_DATA_W 32 +#define RFC_ULLRAM_BANK1746_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1746_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1747 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1747_DATA_W 32 +#define RFC_ULLRAM_BANK1747_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1747_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1748 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1748_DATA_W 32 +#define RFC_ULLRAM_BANK1748_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1748_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1749 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1749_DATA_W 32 +#define RFC_ULLRAM_BANK1749_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1749_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1750 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1750_DATA_W 32 +#define RFC_ULLRAM_BANK1750_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1750_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1751 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1751_DATA_W 32 +#define RFC_ULLRAM_BANK1751_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1751_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1752 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1752_DATA_W 32 +#define RFC_ULLRAM_BANK1752_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1752_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1753 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1753_DATA_W 32 +#define RFC_ULLRAM_BANK1753_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1753_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1754 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1754_DATA_W 32 +#define RFC_ULLRAM_BANK1754_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1754_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1755 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1755_DATA_W 32 +#define RFC_ULLRAM_BANK1755_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1755_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1756 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1756_DATA_W 32 +#define RFC_ULLRAM_BANK1756_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1756_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1757 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1757_DATA_W 32 +#define RFC_ULLRAM_BANK1757_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1757_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1758 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1758_DATA_W 32 +#define RFC_ULLRAM_BANK1758_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1758_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1759 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1759_DATA_W 32 +#define RFC_ULLRAM_BANK1759_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1759_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1760 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1760_DATA_W 32 +#define RFC_ULLRAM_BANK1760_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1760_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1761 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1761_DATA_W 32 +#define RFC_ULLRAM_BANK1761_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1761_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1762 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1762_DATA_W 32 +#define RFC_ULLRAM_BANK1762_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1762_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1763 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1763_DATA_W 32 +#define RFC_ULLRAM_BANK1763_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1763_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1764 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1764_DATA_W 32 +#define RFC_ULLRAM_BANK1764_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1764_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1765 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1765_DATA_W 32 +#define RFC_ULLRAM_BANK1765_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1765_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1766 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1766_DATA_W 32 +#define RFC_ULLRAM_BANK1766_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1766_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1767 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1767_DATA_W 32 +#define RFC_ULLRAM_BANK1767_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1767_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1768 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1768_DATA_W 32 +#define RFC_ULLRAM_BANK1768_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1768_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1769 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1769_DATA_W 32 +#define RFC_ULLRAM_BANK1769_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1769_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1770 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1770_DATA_W 32 +#define RFC_ULLRAM_BANK1770_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1770_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1771 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1771_DATA_W 32 +#define RFC_ULLRAM_BANK1771_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1771_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1772 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1772_DATA_W 32 +#define RFC_ULLRAM_BANK1772_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1772_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1773 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1773_DATA_W 32 +#define RFC_ULLRAM_BANK1773_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1773_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1774 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1774_DATA_W 32 +#define RFC_ULLRAM_BANK1774_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1774_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1775 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1775_DATA_W 32 +#define RFC_ULLRAM_BANK1775_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1775_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1776 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1776_DATA_W 32 +#define RFC_ULLRAM_BANK1776_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1776_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1777 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1777_DATA_W 32 +#define RFC_ULLRAM_BANK1777_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1777_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1778 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1778_DATA_W 32 +#define RFC_ULLRAM_BANK1778_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1778_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1779 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1779_DATA_W 32 +#define RFC_ULLRAM_BANK1779_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1779_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1780 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1780_DATA_W 32 +#define RFC_ULLRAM_BANK1780_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1780_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1781 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1781_DATA_W 32 +#define RFC_ULLRAM_BANK1781_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1781_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1782 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1782_DATA_W 32 +#define RFC_ULLRAM_BANK1782_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1782_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1783 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1783_DATA_W 32 +#define RFC_ULLRAM_BANK1783_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1783_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1784 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1784_DATA_W 32 +#define RFC_ULLRAM_BANK1784_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1784_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1785 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1785_DATA_W 32 +#define RFC_ULLRAM_BANK1785_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1785_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1786 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1786_DATA_W 32 +#define RFC_ULLRAM_BANK1786_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1786_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1787 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1787_DATA_W 32 +#define RFC_ULLRAM_BANK1787_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1787_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1788 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1788_DATA_W 32 +#define RFC_ULLRAM_BANK1788_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1788_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1789 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1789_DATA_W 32 +#define RFC_ULLRAM_BANK1789_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1789_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1790 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1790_DATA_W 32 +#define RFC_ULLRAM_BANK1790_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1790_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1791 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1791_DATA_W 32 +#define RFC_ULLRAM_BANK1791_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1791_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1792 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1792_DATA_W 32 +#define RFC_ULLRAM_BANK1792_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1792_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1793 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1793_DATA_W 32 +#define RFC_ULLRAM_BANK1793_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1793_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1794 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1794_DATA_W 32 +#define RFC_ULLRAM_BANK1794_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1794_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1795 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1795_DATA_W 32 +#define RFC_ULLRAM_BANK1795_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1795_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1796 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1796_DATA_W 32 +#define RFC_ULLRAM_BANK1796_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1796_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1797 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1797_DATA_W 32 +#define RFC_ULLRAM_BANK1797_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1797_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1798 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1798_DATA_W 32 +#define RFC_ULLRAM_BANK1798_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1798_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1799 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1799_DATA_W 32 +#define RFC_ULLRAM_BANK1799_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1799_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1800 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1800_DATA_W 32 +#define RFC_ULLRAM_BANK1800_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1800_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1801 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1801_DATA_W 32 +#define RFC_ULLRAM_BANK1801_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1801_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1802 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1802_DATA_W 32 +#define RFC_ULLRAM_BANK1802_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1802_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1803 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1803_DATA_W 32 +#define RFC_ULLRAM_BANK1803_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1803_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1804 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1804_DATA_W 32 +#define RFC_ULLRAM_BANK1804_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1804_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1805 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1805_DATA_W 32 +#define RFC_ULLRAM_BANK1805_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1805_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1806 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1806_DATA_W 32 +#define RFC_ULLRAM_BANK1806_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1806_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1807 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1807_DATA_W 32 +#define RFC_ULLRAM_BANK1807_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1807_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1808 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1808_DATA_W 32 +#define RFC_ULLRAM_BANK1808_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1808_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1809 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1809_DATA_W 32 +#define RFC_ULLRAM_BANK1809_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1809_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1810 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1810_DATA_W 32 +#define RFC_ULLRAM_BANK1810_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1810_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1811 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1811_DATA_W 32 +#define RFC_ULLRAM_BANK1811_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1811_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1812 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1812_DATA_W 32 +#define RFC_ULLRAM_BANK1812_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1812_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1813 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1813_DATA_W 32 +#define RFC_ULLRAM_BANK1813_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1813_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1814 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1814_DATA_W 32 +#define RFC_ULLRAM_BANK1814_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1814_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1815 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1815_DATA_W 32 +#define RFC_ULLRAM_BANK1815_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1815_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1816 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1816_DATA_W 32 +#define RFC_ULLRAM_BANK1816_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1816_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1817 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1817_DATA_W 32 +#define RFC_ULLRAM_BANK1817_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1817_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1818 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1818_DATA_W 32 +#define RFC_ULLRAM_BANK1818_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1818_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1819 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1819_DATA_W 32 +#define RFC_ULLRAM_BANK1819_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1819_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1820 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1820_DATA_W 32 +#define RFC_ULLRAM_BANK1820_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1820_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1821 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1821_DATA_W 32 +#define RFC_ULLRAM_BANK1821_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1821_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1822 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1822_DATA_W 32 +#define RFC_ULLRAM_BANK1822_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1822_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1823 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1823_DATA_W 32 +#define RFC_ULLRAM_BANK1823_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1823_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1824 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1824_DATA_W 32 +#define RFC_ULLRAM_BANK1824_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1824_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1825 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1825_DATA_W 32 +#define RFC_ULLRAM_BANK1825_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1825_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1826 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1826_DATA_W 32 +#define RFC_ULLRAM_BANK1826_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1826_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1827 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1827_DATA_W 32 +#define RFC_ULLRAM_BANK1827_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1827_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1828 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1828_DATA_W 32 +#define RFC_ULLRAM_BANK1828_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1828_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1829 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1829_DATA_W 32 +#define RFC_ULLRAM_BANK1829_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1829_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1830 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1830_DATA_W 32 +#define RFC_ULLRAM_BANK1830_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1830_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1831 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1831_DATA_W 32 +#define RFC_ULLRAM_BANK1831_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1831_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1832 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1832_DATA_W 32 +#define RFC_ULLRAM_BANK1832_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1832_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1833 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1833_DATA_W 32 +#define RFC_ULLRAM_BANK1833_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1833_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1834 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1834_DATA_W 32 +#define RFC_ULLRAM_BANK1834_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1834_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1835 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1835_DATA_W 32 +#define RFC_ULLRAM_BANK1835_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1835_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1836 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1836_DATA_W 32 +#define RFC_ULLRAM_BANK1836_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1836_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1837 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1837_DATA_W 32 +#define RFC_ULLRAM_BANK1837_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1837_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1838 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1838_DATA_W 32 +#define RFC_ULLRAM_BANK1838_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1838_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1839 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1839_DATA_W 32 +#define RFC_ULLRAM_BANK1839_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1839_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1840 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1840_DATA_W 32 +#define RFC_ULLRAM_BANK1840_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1840_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1841 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1841_DATA_W 32 +#define RFC_ULLRAM_BANK1841_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1841_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1842 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1842_DATA_W 32 +#define RFC_ULLRAM_BANK1842_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1842_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1843 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1843_DATA_W 32 +#define RFC_ULLRAM_BANK1843_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1843_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1844 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1844_DATA_W 32 +#define RFC_ULLRAM_BANK1844_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1844_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1845 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1845_DATA_W 32 +#define RFC_ULLRAM_BANK1845_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1845_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1846 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1846_DATA_W 32 +#define RFC_ULLRAM_BANK1846_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1846_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1847 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1847_DATA_W 32 +#define RFC_ULLRAM_BANK1847_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1847_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1848 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1848_DATA_W 32 +#define RFC_ULLRAM_BANK1848_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1848_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1849 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1849_DATA_W 32 +#define RFC_ULLRAM_BANK1849_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1849_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1850 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1850_DATA_W 32 +#define RFC_ULLRAM_BANK1850_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1850_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1851 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1851_DATA_W 32 +#define RFC_ULLRAM_BANK1851_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1851_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1852 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1852_DATA_W 32 +#define RFC_ULLRAM_BANK1852_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1852_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1853 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1853_DATA_W 32 +#define RFC_ULLRAM_BANK1853_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1853_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1854 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1854_DATA_W 32 +#define RFC_ULLRAM_BANK1854_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1854_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1855 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1855_DATA_W 32 +#define RFC_ULLRAM_BANK1855_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1855_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1856 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1856_DATA_W 32 +#define RFC_ULLRAM_BANK1856_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1856_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1857 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1857_DATA_W 32 +#define RFC_ULLRAM_BANK1857_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1857_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1858 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1858_DATA_W 32 +#define RFC_ULLRAM_BANK1858_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1858_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1859 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1859_DATA_W 32 +#define RFC_ULLRAM_BANK1859_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1859_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1860 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1860_DATA_W 32 +#define RFC_ULLRAM_BANK1860_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1860_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1861 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1861_DATA_W 32 +#define RFC_ULLRAM_BANK1861_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1861_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1862 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1862_DATA_W 32 +#define RFC_ULLRAM_BANK1862_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1862_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1863 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1863_DATA_W 32 +#define RFC_ULLRAM_BANK1863_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1863_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1864 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1864_DATA_W 32 +#define RFC_ULLRAM_BANK1864_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1864_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1865 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1865_DATA_W 32 +#define RFC_ULLRAM_BANK1865_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1865_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1866 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1866_DATA_W 32 +#define RFC_ULLRAM_BANK1866_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1866_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1867 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1867_DATA_W 32 +#define RFC_ULLRAM_BANK1867_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1867_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1868 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1868_DATA_W 32 +#define RFC_ULLRAM_BANK1868_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1868_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1869 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1869_DATA_W 32 +#define RFC_ULLRAM_BANK1869_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1869_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1870 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1870_DATA_W 32 +#define RFC_ULLRAM_BANK1870_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1870_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1871 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1871_DATA_W 32 +#define RFC_ULLRAM_BANK1871_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1871_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1872 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1872_DATA_W 32 +#define RFC_ULLRAM_BANK1872_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1872_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1873 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1873_DATA_W 32 +#define RFC_ULLRAM_BANK1873_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1873_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1874 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1874_DATA_W 32 +#define RFC_ULLRAM_BANK1874_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1874_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1875 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1875_DATA_W 32 +#define RFC_ULLRAM_BANK1875_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1875_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1876 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1876_DATA_W 32 +#define RFC_ULLRAM_BANK1876_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1876_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1877 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1877_DATA_W 32 +#define RFC_ULLRAM_BANK1877_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1877_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1878 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1878_DATA_W 32 +#define RFC_ULLRAM_BANK1878_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1878_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1879 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1879_DATA_W 32 +#define RFC_ULLRAM_BANK1879_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1879_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1880 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1880_DATA_W 32 +#define RFC_ULLRAM_BANK1880_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1880_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1881 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1881_DATA_W 32 +#define RFC_ULLRAM_BANK1881_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1881_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1882 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1882_DATA_W 32 +#define RFC_ULLRAM_BANK1882_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1882_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1883 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1883_DATA_W 32 +#define RFC_ULLRAM_BANK1883_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1883_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1884 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1884_DATA_W 32 +#define RFC_ULLRAM_BANK1884_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1884_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1885 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1885_DATA_W 32 +#define RFC_ULLRAM_BANK1885_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1885_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1886 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1886_DATA_W 32 +#define RFC_ULLRAM_BANK1886_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1886_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1887 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1887_DATA_W 32 +#define RFC_ULLRAM_BANK1887_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1887_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1888 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1888_DATA_W 32 +#define RFC_ULLRAM_BANK1888_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1888_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1889 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1889_DATA_W 32 +#define RFC_ULLRAM_BANK1889_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1889_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1890 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1890_DATA_W 32 +#define RFC_ULLRAM_BANK1890_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1890_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1891 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1891_DATA_W 32 +#define RFC_ULLRAM_BANK1891_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1891_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1892 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1892_DATA_W 32 +#define RFC_ULLRAM_BANK1892_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1892_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1893 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1893_DATA_W 32 +#define RFC_ULLRAM_BANK1893_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1893_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1894 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1894_DATA_W 32 +#define RFC_ULLRAM_BANK1894_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1894_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1895 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1895_DATA_W 32 +#define RFC_ULLRAM_BANK1895_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1895_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1896 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1896_DATA_W 32 +#define RFC_ULLRAM_BANK1896_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1896_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1897 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1897_DATA_W 32 +#define RFC_ULLRAM_BANK1897_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1897_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1898 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1898_DATA_W 32 +#define RFC_ULLRAM_BANK1898_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1898_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1899 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1899_DATA_W 32 +#define RFC_ULLRAM_BANK1899_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1899_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1900 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1900_DATA_W 32 +#define RFC_ULLRAM_BANK1900_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1900_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1901 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1901_DATA_W 32 +#define RFC_ULLRAM_BANK1901_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1901_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1902 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1902_DATA_W 32 +#define RFC_ULLRAM_BANK1902_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1902_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1903 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1903_DATA_W 32 +#define RFC_ULLRAM_BANK1903_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1903_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1904 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1904_DATA_W 32 +#define RFC_ULLRAM_BANK1904_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1904_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1905 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1905_DATA_W 32 +#define RFC_ULLRAM_BANK1905_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1905_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1906 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1906_DATA_W 32 +#define RFC_ULLRAM_BANK1906_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1906_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1907 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1907_DATA_W 32 +#define RFC_ULLRAM_BANK1907_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1907_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1908 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1908_DATA_W 32 +#define RFC_ULLRAM_BANK1908_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1908_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1909 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1909_DATA_W 32 +#define RFC_ULLRAM_BANK1909_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1909_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1910 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1910_DATA_W 32 +#define RFC_ULLRAM_BANK1910_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1910_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1911 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1911_DATA_W 32 +#define RFC_ULLRAM_BANK1911_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1911_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1912 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1912_DATA_W 32 +#define RFC_ULLRAM_BANK1912_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1912_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1913 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1913_DATA_W 32 +#define RFC_ULLRAM_BANK1913_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1913_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1914 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1914_DATA_W 32 +#define RFC_ULLRAM_BANK1914_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1914_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1915 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1915_DATA_W 32 +#define RFC_ULLRAM_BANK1915_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1915_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1916 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1916_DATA_W 32 +#define RFC_ULLRAM_BANK1916_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1916_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1917 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1917_DATA_W 32 +#define RFC_ULLRAM_BANK1917_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1917_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1918 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1918_DATA_W 32 +#define RFC_ULLRAM_BANK1918_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1918_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1919 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1919_DATA_W 32 +#define RFC_ULLRAM_BANK1919_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1919_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1920 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1920_DATA_W 32 +#define RFC_ULLRAM_BANK1920_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1920_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1921 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1921_DATA_W 32 +#define RFC_ULLRAM_BANK1921_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1921_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1922 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1922_DATA_W 32 +#define RFC_ULLRAM_BANK1922_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1922_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1923 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1923_DATA_W 32 +#define RFC_ULLRAM_BANK1923_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1923_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1924 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1924_DATA_W 32 +#define RFC_ULLRAM_BANK1924_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1924_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1925 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1925_DATA_W 32 +#define RFC_ULLRAM_BANK1925_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1925_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1926 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1926_DATA_W 32 +#define RFC_ULLRAM_BANK1926_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1926_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1927 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1927_DATA_W 32 +#define RFC_ULLRAM_BANK1927_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1927_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1928 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1928_DATA_W 32 +#define RFC_ULLRAM_BANK1928_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1928_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1929 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1929_DATA_W 32 +#define RFC_ULLRAM_BANK1929_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1929_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1930 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1930_DATA_W 32 +#define RFC_ULLRAM_BANK1930_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1930_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1931 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1931_DATA_W 32 +#define RFC_ULLRAM_BANK1931_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1931_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1932 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1932_DATA_W 32 +#define RFC_ULLRAM_BANK1932_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1932_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1933 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1933_DATA_W 32 +#define RFC_ULLRAM_BANK1933_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1933_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1934 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1934_DATA_W 32 +#define RFC_ULLRAM_BANK1934_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1934_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1935 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1935_DATA_W 32 +#define RFC_ULLRAM_BANK1935_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1935_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1936 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1936_DATA_W 32 +#define RFC_ULLRAM_BANK1936_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1936_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1937 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1937_DATA_W 32 +#define RFC_ULLRAM_BANK1937_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1937_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1938 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1938_DATA_W 32 +#define RFC_ULLRAM_BANK1938_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1938_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1939 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1939_DATA_W 32 +#define RFC_ULLRAM_BANK1939_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1939_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1940 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1940_DATA_W 32 +#define RFC_ULLRAM_BANK1940_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1940_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1941 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1941_DATA_W 32 +#define RFC_ULLRAM_BANK1941_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1941_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1942 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1942_DATA_W 32 +#define RFC_ULLRAM_BANK1942_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1942_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1943 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1943_DATA_W 32 +#define RFC_ULLRAM_BANK1943_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1943_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1944 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1944_DATA_W 32 +#define RFC_ULLRAM_BANK1944_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1944_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1945 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1945_DATA_W 32 +#define RFC_ULLRAM_BANK1945_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1945_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1946 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1946_DATA_W 32 +#define RFC_ULLRAM_BANK1946_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1946_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1947 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1947_DATA_W 32 +#define RFC_ULLRAM_BANK1947_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1947_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1948 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1948_DATA_W 32 +#define RFC_ULLRAM_BANK1948_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1948_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1949 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1949_DATA_W 32 +#define RFC_ULLRAM_BANK1949_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1949_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1950 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1950_DATA_W 32 +#define RFC_ULLRAM_BANK1950_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1950_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1951 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1951_DATA_W 32 +#define RFC_ULLRAM_BANK1951_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1951_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1952 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1952_DATA_W 32 +#define RFC_ULLRAM_BANK1952_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1952_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1953 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1953_DATA_W 32 +#define RFC_ULLRAM_BANK1953_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1953_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1954 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1954_DATA_W 32 +#define RFC_ULLRAM_BANK1954_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1954_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1955 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1955_DATA_W 32 +#define RFC_ULLRAM_BANK1955_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1955_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1956 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1956_DATA_W 32 +#define RFC_ULLRAM_BANK1956_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1956_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1957 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1957_DATA_W 32 +#define RFC_ULLRAM_BANK1957_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1957_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1958 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1958_DATA_W 32 +#define RFC_ULLRAM_BANK1958_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1958_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1959 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1959_DATA_W 32 +#define RFC_ULLRAM_BANK1959_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1959_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1960 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1960_DATA_W 32 +#define RFC_ULLRAM_BANK1960_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1960_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1961 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1961_DATA_W 32 +#define RFC_ULLRAM_BANK1961_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1961_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1962 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1962_DATA_W 32 +#define RFC_ULLRAM_BANK1962_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1962_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1963 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1963_DATA_W 32 +#define RFC_ULLRAM_BANK1963_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1963_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1964 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1964_DATA_W 32 +#define RFC_ULLRAM_BANK1964_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1964_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1965 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1965_DATA_W 32 +#define RFC_ULLRAM_BANK1965_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1965_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1966 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1966_DATA_W 32 +#define RFC_ULLRAM_BANK1966_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1966_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1967 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1967_DATA_W 32 +#define RFC_ULLRAM_BANK1967_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1967_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1968 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1968_DATA_W 32 +#define RFC_ULLRAM_BANK1968_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1968_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1969 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1969_DATA_W 32 +#define RFC_ULLRAM_BANK1969_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1969_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1970 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1970_DATA_W 32 +#define RFC_ULLRAM_BANK1970_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1970_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1971 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1971_DATA_W 32 +#define RFC_ULLRAM_BANK1971_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1971_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1972 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1972_DATA_W 32 +#define RFC_ULLRAM_BANK1972_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1972_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1973 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1973_DATA_W 32 +#define RFC_ULLRAM_BANK1973_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1973_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1974 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1974_DATA_W 32 +#define RFC_ULLRAM_BANK1974_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1974_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1975 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1975_DATA_W 32 +#define RFC_ULLRAM_BANK1975_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1975_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1976 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1976_DATA_W 32 +#define RFC_ULLRAM_BANK1976_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1976_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1977 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1977_DATA_W 32 +#define RFC_ULLRAM_BANK1977_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1977_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1978 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1978_DATA_W 32 +#define RFC_ULLRAM_BANK1978_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1978_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1979 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1979_DATA_W 32 +#define RFC_ULLRAM_BANK1979_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1979_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1980 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1980_DATA_W 32 +#define RFC_ULLRAM_BANK1980_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1980_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1981 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1981_DATA_W 32 +#define RFC_ULLRAM_BANK1981_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1981_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1982 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1982_DATA_W 32 +#define RFC_ULLRAM_BANK1982_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1982_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1983 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1983_DATA_W 32 +#define RFC_ULLRAM_BANK1983_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1983_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1984 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1984_DATA_W 32 +#define RFC_ULLRAM_BANK1984_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1984_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1985 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1985_DATA_W 32 +#define RFC_ULLRAM_BANK1985_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1985_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1986 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1986_DATA_W 32 +#define RFC_ULLRAM_BANK1986_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1986_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1987 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1987_DATA_W 32 +#define RFC_ULLRAM_BANK1987_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1987_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1988 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1988_DATA_W 32 +#define RFC_ULLRAM_BANK1988_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1988_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1989 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1989_DATA_W 32 +#define RFC_ULLRAM_BANK1989_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1989_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1990 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1990_DATA_W 32 +#define RFC_ULLRAM_BANK1990_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1990_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1991 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1991_DATA_W 32 +#define RFC_ULLRAM_BANK1991_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1991_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1992 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1992_DATA_W 32 +#define RFC_ULLRAM_BANK1992_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1992_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1993 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1993_DATA_W 32 +#define RFC_ULLRAM_BANK1993_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1993_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1994 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1994_DATA_W 32 +#define RFC_ULLRAM_BANK1994_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1994_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1995 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1995_DATA_W 32 +#define RFC_ULLRAM_BANK1995_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1995_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1996 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1996_DATA_W 32 +#define RFC_ULLRAM_BANK1996_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1996_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1997 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1997_DATA_W 32 +#define RFC_ULLRAM_BANK1997_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1997_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1998 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1998_DATA_W 32 +#define RFC_ULLRAM_BANK1998_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1998_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1999 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1999_DATA_W 32 +#define RFC_ULLRAM_BANK1999_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1999_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11000 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11000_DATA_W 32 +#define RFC_ULLRAM_BANK11000_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11000_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11001 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11001_DATA_W 32 +#define RFC_ULLRAM_BANK11001_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11001_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11002 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11002_DATA_W 32 +#define RFC_ULLRAM_BANK11002_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11002_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11003 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11003_DATA_W 32 +#define RFC_ULLRAM_BANK11003_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11003_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11004 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11004_DATA_W 32 +#define RFC_ULLRAM_BANK11004_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11004_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11005 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11005_DATA_W 32 +#define RFC_ULLRAM_BANK11005_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11005_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11006 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11006_DATA_W 32 +#define RFC_ULLRAM_BANK11006_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11006_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11007 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11007_DATA_W 32 +#define RFC_ULLRAM_BANK11007_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11007_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11008 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11008_DATA_W 32 +#define RFC_ULLRAM_BANK11008_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11008_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11009 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11009_DATA_W 32 +#define RFC_ULLRAM_BANK11009_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11009_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11010 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11010_DATA_W 32 +#define RFC_ULLRAM_BANK11010_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11010_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11011 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11011_DATA_W 32 +#define RFC_ULLRAM_BANK11011_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11011_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11012 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11012_DATA_W 32 +#define RFC_ULLRAM_BANK11012_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11012_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11013 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11013_DATA_W 32 +#define RFC_ULLRAM_BANK11013_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11013_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11014 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11014_DATA_W 32 +#define RFC_ULLRAM_BANK11014_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11014_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11015 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11015_DATA_W 32 +#define RFC_ULLRAM_BANK11015_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11015_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11016 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11016_DATA_W 32 +#define RFC_ULLRAM_BANK11016_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11016_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11017 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11017_DATA_W 32 +#define RFC_ULLRAM_BANK11017_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11017_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11018 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11018_DATA_W 32 +#define RFC_ULLRAM_BANK11018_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11018_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11019 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11019_DATA_W 32 +#define RFC_ULLRAM_BANK11019_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11019_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11020 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11020_DATA_W 32 +#define RFC_ULLRAM_BANK11020_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11020_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11021 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11021_DATA_W 32 +#define RFC_ULLRAM_BANK11021_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11021_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11022 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11022_DATA_W 32 +#define RFC_ULLRAM_BANK11022_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11022_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11023 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11023_DATA_W 32 +#define RFC_ULLRAM_BANK11023_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11023_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11024 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11024_DATA_W 32 +#define RFC_ULLRAM_BANK11024_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11024_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11025 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11025_DATA_W 32 +#define RFC_ULLRAM_BANK11025_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11025_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11026 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11026_DATA_W 32 +#define RFC_ULLRAM_BANK11026_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11026_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11027 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11027_DATA_W 32 +#define RFC_ULLRAM_BANK11027_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11027_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11028 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11028_DATA_W 32 +#define RFC_ULLRAM_BANK11028_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11028_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11029 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11029_DATA_W 32 +#define RFC_ULLRAM_BANK11029_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11029_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11030 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11030_DATA_W 32 +#define RFC_ULLRAM_BANK11030_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11030_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11031 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11031_DATA_W 32 +#define RFC_ULLRAM_BANK11031_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11031_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11032 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11032_DATA_W 32 +#define RFC_ULLRAM_BANK11032_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11032_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11033 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11033_DATA_W 32 +#define RFC_ULLRAM_BANK11033_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11033_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11034 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11034_DATA_W 32 +#define RFC_ULLRAM_BANK11034_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11034_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11035 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11035_DATA_W 32 +#define RFC_ULLRAM_BANK11035_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11035_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11036 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11036_DATA_W 32 +#define RFC_ULLRAM_BANK11036_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11036_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11037 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11037_DATA_W 32 +#define RFC_ULLRAM_BANK11037_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11037_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11038 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11038_DATA_W 32 +#define RFC_ULLRAM_BANK11038_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11038_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11039 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11039_DATA_W 32 +#define RFC_ULLRAM_BANK11039_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11039_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11040 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11040_DATA_W 32 +#define RFC_ULLRAM_BANK11040_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11040_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11041 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11041_DATA_W 32 +#define RFC_ULLRAM_BANK11041_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11041_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11042 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11042_DATA_W 32 +#define RFC_ULLRAM_BANK11042_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11042_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11043 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11043_DATA_W 32 +#define RFC_ULLRAM_BANK11043_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11043_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11044 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11044_DATA_W 32 +#define RFC_ULLRAM_BANK11044_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11044_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11045 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11045_DATA_W 32 +#define RFC_ULLRAM_BANK11045_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11045_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11046 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11046_DATA_W 32 +#define RFC_ULLRAM_BANK11046_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11046_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11047 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11047_DATA_W 32 +#define RFC_ULLRAM_BANK11047_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11047_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11048 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11048_DATA_W 32 +#define RFC_ULLRAM_BANK11048_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11048_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11049 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11049_DATA_W 32 +#define RFC_ULLRAM_BANK11049_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11049_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11050 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11050_DATA_W 32 +#define RFC_ULLRAM_BANK11050_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11050_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11051 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11051_DATA_W 32 +#define RFC_ULLRAM_BANK11051_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11051_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11052 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11052_DATA_W 32 +#define RFC_ULLRAM_BANK11052_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11052_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11053 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11053_DATA_W 32 +#define RFC_ULLRAM_BANK11053_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11053_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11054 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11054_DATA_W 32 +#define RFC_ULLRAM_BANK11054_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11054_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11055 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11055_DATA_W 32 +#define RFC_ULLRAM_BANK11055_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11055_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11056 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11056_DATA_W 32 +#define RFC_ULLRAM_BANK11056_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11056_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11057 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11057_DATA_W 32 +#define RFC_ULLRAM_BANK11057_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11057_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11058 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11058_DATA_W 32 +#define RFC_ULLRAM_BANK11058_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11058_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11059 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11059_DATA_W 32 +#define RFC_ULLRAM_BANK11059_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11059_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11060 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11060_DATA_W 32 +#define RFC_ULLRAM_BANK11060_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11060_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11061 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11061_DATA_W 32 +#define RFC_ULLRAM_BANK11061_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11061_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11062 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11062_DATA_W 32 +#define RFC_ULLRAM_BANK11062_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11062_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11063 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11063_DATA_W 32 +#define RFC_ULLRAM_BANK11063_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11063_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11064 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11064_DATA_W 32 +#define RFC_ULLRAM_BANK11064_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11064_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11065 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11065_DATA_W 32 +#define RFC_ULLRAM_BANK11065_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11065_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11066 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11066_DATA_W 32 +#define RFC_ULLRAM_BANK11066_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11066_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11067 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11067_DATA_W 32 +#define RFC_ULLRAM_BANK11067_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11067_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11068 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11068_DATA_W 32 +#define RFC_ULLRAM_BANK11068_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11068_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11069 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11069_DATA_W 32 +#define RFC_ULLRAM_BANK11069_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11069_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11070 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11070_DATA_W 32 +#define RFC_ULLRAM_BANK11070_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11070_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11071 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11071_DATA_W 32 +#define RFC_ULLRAM_BANK11071_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11071_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11072 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11072_DATA_W 32 +#define RFC_ULLRAM_BANK11072_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11072_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11073 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11073_DATA_W 32 +#define RFC_ULLRAM_BANK11073_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11073_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11074 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11074_DATA_W 32 +#define RFC_ULLRAM_BANK11074_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11074_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11075 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11075_DATA_W 32 +#define RFC_ULLRAM_BANK11075_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11075_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11076 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11076_DATA_W 32 +#define RFC_ULLRAM_BANK11076_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11076_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11077 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11077_DATA_W 32 +#define RFC_ULLRAM_BANK11077_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11077_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11078 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11078_DATA_W 32 +#define RFC_ULLRAM_BANK11078_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11078_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11079 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11079_DATA_W 32 +#define RFC_ULLRAM_BANK11079_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11079_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11080 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11080_DATA_W 32 +#define RFC_ULLRAM_BANK11080_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11080_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11081 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11081_DATA_W 32 +#define RFC_ULLRAM_BANK11081_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11081_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11082 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11082_DATA_W 32 +#define RFC_ULLRAM_BANK11082_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11082_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11083 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11083_DATA_W 32 +#define RFC_ULLRAM_BANK11083_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11083_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11084 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11084_DATA_W 32 +#define RFC_ULLRAM_BANK11084_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11084_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11085 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11085_DATA_W 32 +#define RFC_ULLRAM_BANK11085_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11085_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11086 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11086_DATA_W 32 +#define RFC_ULLRAM_BANK11086_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11086_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11087 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11087_DATA_W 32 +#define RFC_ULLRAM_BANK11087_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11087_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11088 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11088_DATA_W 32 +#define RFC_ULLRAM_BANK11088_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11088_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11089 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11089_DATA_W 32 +#define RFC_ULLRAM_BANK11089_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11089_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11090 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11090_DATA_W 32 +#define RFC_ULLRAM_BANK11090_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11090_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11091 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11091_DATA_W 32 +#define RFC_ULLRAM_BANK11091_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11091_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11092 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11092_DATA_W 32 +#define RFC_ULLRAM_BANK11092_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11092_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11093 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11093_DATA_W 32 +#define RFC_ULLRAM_BANK11093_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11093_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11094 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11094_DATA_W 32 +#define RFC_ULLRAM_BANK11094_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11094_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11095 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11095_DATA_W 32 +#define RFC_ULLRAM_BANK11095_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11095_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11096 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11096_DATA_W 32 +#define RFC_ULLRAM_BANK11096_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11096_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11097 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11097_DATA_W 32 +#define RFC_ULLRAM_BANK11097_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11097_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11098 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11098_DATA_W 32 +#define RFC_ULLRAM_BANK11098_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11098_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11099 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11099_DATA_W 32 +#define RFC_ULLRAM_BANK11099_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11099_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11100 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11100_DATA_W 32 +#define RFC_ULLRAM_BANK11100_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11100_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11101 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11101_DATA_W 32 +#define RFC_ULLRAM_BANK11101_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11101_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11102 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11102_DATA_W 32 +#define RFC_ULLRAM_BANK11102_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11102_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11103 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11103_DATA_W 32 +#define RFC_ULLRAM_BANK11103_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11103_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11104 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11104_DATA_W 32 +#define RFC_ULLRAM_BANK11104_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11104_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11105 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11105_DATA_W 32 +#define RFC_ULLRAM_BANK11105_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11105_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11106 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11106_DATA_W 32 +#define RFC_ULLRAM_BANK11106_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11106_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11107 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11107_DATA_W 32 +#define RFC_ULLRAM_BANK11107_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11107_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11108 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11108_DATA_W 32 +#define RFC_ULLRAM_BANK11108_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11108_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11109 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11109_DATA_W 32 +#define RFC_ULLRAM_BANK11109_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11109_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11110 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11110_DATA_W 32 +#define RFC_ULLRAM_BANK11110_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11110_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11111 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11111_DATA_W 32 +#define RFC_ULLRAM_BANK11111_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11111_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11112 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11112_DATA_W 32 +#define RFC_ULLRAM_BANK11112_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11112_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11113 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11113_DATA_W 32 +#define RFC_ULLRAM_BANK11113_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11113_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11114 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11114_DATA_W 32 +#define RFC_ULLRAM_BANK11114_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11114_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11115 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11115_DATA_W 32 +#define RFC_ULLRAM_BANK11115_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11115_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11116 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11116_DATA_W 32 +#define RFC_ULLRAM_BANK11116_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11116_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11117 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11117_DATA_W 32 +#define RFC_ULLRAM_BANK11117_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11117_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11118 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11118_DATA_W 32 +#define RFC_ULLRAM_BANK11118_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11118_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11119 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11119_DATA_W 32 +#define RFC_ULLRAM_BANK11119_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11119_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11120 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11120_DATA_W 32 +#define RFC_ULLRAM_BANK11120_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11120_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11121 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11121_DATA_W 32 +#define RFC_ULLRAM_BANK11121_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11121_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11122 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11122_DATA_W 32 +#define RFC_ULLRAM_BANK11122_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11122_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11123 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11123_DATA_W 32 +#define RFC_ULLRAM_BANK11123_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11123_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11124 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11124_DATA_W 32 +#define RFC_ULLRAM_BANK11124_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11124_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11125 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11125_DATA_W 32 +#define RFC_ULLRAM_BANK11125_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11125_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11126 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11126_DATA_W 32 +#define RFC_ULLRAM_BANK11126_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11126_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11127 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11127_DATA_W 32 +#define RFC_ULLRAM_BANK11127_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11127_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11128 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11128_DATA_W 32 +#define RFC_ULLRAM_BANK11128_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11128_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11129 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11129_DATA_W 32 +#define RFC_ULLRAM_BANK11129_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11129_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11130 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11130_DATA_W 32 +#define RFC_ULLRAM_BANK11130_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11130_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11131 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11131_DATA_W 32 +#define RFC_ULLRAM_BANK11131_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11131_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11132 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11132_DATA_W 32 +#define RFC_ULLRAM_BANK11132_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11132_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11133 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11133_DATA_W 32 +#define RFC_ULLRAM_BANK11133_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11133_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11134 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11134_DATA_W 32 +#define RFC_ULLRAM_BANK11134_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11134_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11135 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11135_DATA_W 32 +#define RFC_ULLRAM_BANK11135_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11135_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11136 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11136_DATA_W 32 +#define RFC_ULLRAM_BANK11136_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11136_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11137 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11137_DATA_W 32 +#define RFC_ULLRAM_BANK11137_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11137_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11138 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11138_DATA_W 32 +#define RFC_ULLRAM_BANK11138_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11138_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11139 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11139_DATA_W 32 +#define RFC_ULLRAM_BANK11139_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11139_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11140 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11140_DATA_W 32 +#define RFC_ULLRAM_BANK11140_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11140_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11141 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11141_DATA_W 32 +#define RFC_ULLRAM_BANK11141_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11141_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11142 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11142_DATA_W 32 +#define RFC_ULLRAM_BANK11142_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11142_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11143 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11143_DATA_W 32 +#define RFC_ULLRAM_BANK11143_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11143_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11144 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11144_DATA_W 32 +#define RFC_ULLRAM_BANK11144_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11144_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11145 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11145_DATA_W 32 +#define RFC_ULLRAM_BANK11145_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11145_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11146 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11146_DATA_W 32 +#define RFC_ULLRAM_BANK11146_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11146_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11147 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11147_DATA_W 32 +#define RFC_ULLRAM_BANK11147_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11147_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11148 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11148_DATA_W 32 +#define RFC_ULLRAM_BANK11148_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11148_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11149 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11149_DATA_W 32 +#define RFC_ULLRAM_BANK11149_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11149_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11150 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11150_DATA_W 32 +#define RFC_ULLRAM_BANK11150_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11150_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11151 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11151_DATA_W 32 +#define RFC_ULLRAM_BANK11151_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11151_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11152 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11152_DATA_W 32 +#define RFC_ULLRAM_BANK11152_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11152_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11153 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11153_DATA_W 32 +#define RFC_ULLRAM_BANK11153_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11153_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11154 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11154_DATA_W 32 +#define RFC_ULLRAM_BANK11154_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11154_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11155 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11155_DATA_W 32 +#define RFC_ULLRAM_BANK11155_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11155_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11156 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11156_DATA_W 32 +#define RFC_ULLRAM_BANK11156_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11156_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11157 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11157_DATA_W 32 +#define RFC_ULLRAM_BANK11157_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11157_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11158 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11158_DATA_W 32 +#define RFC_ULLRAM_BANK11158_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11158_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11159 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11159_DATA_W 32 +#define RFC_ULLRAM_BANK11159_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11159_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11160 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11160_DATA_W 32 +#define RFC_ULLRAM_BANK11160_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11160_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11161 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11161_DATA_W 32 +#define RFC_ULLRAM_BANK11161_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11161_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11162 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11162_DATA_W 32 +#define RFC_ULLRAM_BANK11162_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11162_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11163 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11163_DATA_W 32 +#define RFC_ULLRAM_BANK11163_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11163_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11164 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11164_DATA_W 32 +#define RFC_ULLRAM_BANK11164_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11164_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11165 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11165_DATA_W 32 +#define RFC_ULLRAM_BANK11165_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11165_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11166 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11166_DATA_W 32 +#define RFC_ULLRAM_BANK11166_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11166_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11167 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11167_DATA_W 32 +#define RFC_ULLRAM_BANK11167_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11167_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11168 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11168_DATA_W 32 +#define RFC_ULLRAM_BANK11168_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11168_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11169 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11169_DATA_W 32 +#define RFC_ULLRAM_BANK11169_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11169_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11170 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11170_DATA_W 32 +#define RFC_ULLRAM_BANK11170_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11170_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11171 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11171_DATA_W 32 +#define RFC_ULLRAM_BANK11171_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11171_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11172 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11172_DATA_W 32 +#define RFC_ULLRAM_BANK11172_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11172_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11173 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11173_DATA_W 32 +#define RFC_ULLRAM_BANK11173_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11173_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11174 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11174_DATA_W 32 +#define RFC_ULLRAM_BANK11174_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11174_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11175 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11175_DATA_W 32 +#define RFC_ULLRAM_BANK11175_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11175_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11176 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11176_DATA_W 32 +#define RFC_ULLRAM_BANK11176_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11176_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11177 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11177_DATA_W 32 +#define RFC_ULLRAM_BANK11177_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11177_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11178 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11178_DATA_W 32 +#define RFC_ULLRAM_BANK11178_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11178_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11179 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11179_DATA_W 32 +#define RFC_ULLRAM_BANK11179_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11179_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11180 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11180_DATA_W 32 +#define RFC_ULLRAM_BANK11180_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11180_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11181 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11181_DATA_W 32 +#define RFC_ULLRAM_BANK11181_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11181_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11182 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11182_DATA_W 32 +#define RFC_ULLRAM_BANK11182_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11182_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11183 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11183_DATA_W 32 +#define RFC_ULLRAM_BANK11183_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11183_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11184 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11184_DATA_W 32 +#define RFC_ULLRAM_BANK11184_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11184_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11185 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11185_DATA_W 32 +#define RFC_ULLRAM_BANK11185_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11185_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11186 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11186_DATA_W 32 +#define RFC_ULLRAM_BANK11186_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11186_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11187 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11187_DATA_W 32 +#define RFC_ULLRAM_BANK11187_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11187_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11188 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11188_DATA_W 32 +#define RFC_ULLRAM_BANK11188_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11188_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11189 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11189_DATA_W 32 +#define RFC_ULLRAM_BANK11189_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11189_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11190 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11190_DATA_W 32 +#define RFC_ULLRAM_BANK11190_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11190_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11191 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11191_DATA_W 32 +#define RFC_ULLRAM_BANK11191_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11191_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11192 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11192_DATA_W 32 +#define RFC_ULLRAM_BANK11192_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11192_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11193 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11193_DATA_W 32 +#define RFC_ULLRAM_BANK11193_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11193_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11194 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11194_DATA_W 32 +#define RFC_ULLRAM_BANK11194_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11194_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11195 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11195_DATA_W 32 +#define RFC_ULLRAM_BANK11195_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11195_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11196 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11196_DATA_W 32 +#define RFC_ULLRAM_BANK11196_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11196_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11197 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11197_DATA_W 32 +#define RFC_ULLRAM_BANK11197_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11197_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11198 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11198_DATA_W 32 +#define RFC_ULLRAM_BANK11198_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11198_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11199 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11199_DATA_W 32 +#define RFC_ULLRAM_BANK11199_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11199_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11200 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11200_DATA_W 32 +#define RFC_ULLRAM_BANK11200_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11200_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11201 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11201_DATA_W 32 +#define RFC_ULLRAM_BANK11201_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11201_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11202 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11202_DATA_W 32 +#define RFC_ULLRAM_BANK11202_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11202_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11203 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11203_DATA_W 32 +#define RFC_ULLRAM_BANK11203_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11203_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11204 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11204_DATA_W 32 +#define RFC_ULLRAM_BANK11204_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11204_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11205 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11205_DATA_W 32 +#define RFC_ULLRAM_BANK11205_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11205_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11206 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11206_DATA_W 32 +#define RFC_ULLRAM_BANK11206_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11206_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11207 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11207_DATA_W 32 +#define RFC_ULLRAM_BANK11207_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11207_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11208 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11208_DATA_W 32 +#define RFC_ULLRAM_BANK11208_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11208_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11209 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11209_DATA_W 32 +#define RFC_ULLRAM_BANK11209_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11209_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11210 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11210_DATA_W 32 +#define RFC_ULLRAM_BANK11210_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11210_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11211 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11211_DATA_W 32 +#define RFC_ULLRAM_BANK11211_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11211_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11212 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11212_DATA_W 32 +#define RFC_ULLRAM_BANK11212_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11212_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11213 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11213_DATA_W 32 +#define RFC_ULLRAM_BANK11213_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11213_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11214 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11214_DATA_W 32 +#define RFC_ULLRAM_BANK11214_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11214_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11215 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11215_DATA_W 32 +#define RFC_ULLRAM_BANK11215_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11215_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11216 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11216_DATA_W 32 +#define RFC_ULLRAM_BANK11216_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11216_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11217 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11217_DATA_W 32 +#define RFC_ULLRAM_BANK11217_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11217_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11218 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11218_DATA_W 32 +#define RFC_ULLRAM_BANK11218_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11218_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11219 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11219_DATA_W 32 +#define RFC_ULLRAM_BANK11219_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11219_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11220 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11220_DATA_W 32 +#define RFC_ULLRAM_BANK11220_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11220_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11221 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11221_DATA_W 32 +#define RFC_ULLRAM_BANK11221_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11221_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11222 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11222_DATA_W 32 +#define RFC_ULLRAM_BANK11222_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11222_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11223 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11223_DATA_W 32 +#define RFC_ULLRAM_BANK11223_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11223_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11224 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11224_DATA_W 32 +#define RFC_ULLRAM_BANK11224_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11224_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11225 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11225_DATA_W 32 +#define RFC_ULLRAM_BANK11225_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11225_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11226 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11226_DATA_W 32 +#define RFC_ULLRAM_BANK11226_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11226_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11227 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11227_DATA_W 32 +#define RFC_ULLRAM_BANK11227_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11227_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11228 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11228_DATA_W 32 +#define RFC_ULLRAM_BANK11228_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11228_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11229 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11229_DATA_W 32 +#define RFC_ULLRAM_BANK11229_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11229_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11230 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11230_DATA_W 32 +#define RFC_ULLRAM_BANK11230_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11230_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11231 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11231_DATA_W 32 +#define RFC_ULLRAM_BANK11231_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11231_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11232 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11232_DATA_W 32 +#define RFC_ULLRAM_BANK11232_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11232_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11233 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11233_DATA_W 32 +#define RFC_ULLRAM_BANK11233_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11233_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11234 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11234_DATA_W 32 +#define RFC_ULLRAM_BANK11234_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11234_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11235 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11235_DATA_W 32 +#define RFC_ULLRAM_BANK11235_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11235_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11236 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11236_DATA_W 32 +#define RFC_ULLRAM_BANK11236_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11236_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11237 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11237_DATA_W 32 +#define RFC_ULLRAM_BANK11237_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11237_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11238 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11238_DATA_W 32 +#define RFC_ULLRAM_BANK11238_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11238_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11239 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11239_DATA_W 32 +#define RFC_ULLRAM_BANK11239_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11239_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11240 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11240_DATA_W 32 +#define RFC_ULLRAM_BANK11240_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11240_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11241 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11241_DATA_W 32 +#define RFC_ULLRAM_BANK11241_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11241_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11242 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11242_DATA_W 32 +#define RFC_ULLRAM_BANK11242_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11242_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11243 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11243_DATA_W 32 +#define RFC_ULLRAM_BANK11243_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11243_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11244 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11244_DATA_W 32 +#define RFC_ULLRAM_BANK11244_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11244_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11245 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11245_DATA_W 32 +#define RFC_ULLRAM_BANK11245_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11245_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11246 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11246_DATA_W 32 +#define RFC_ULLRAM_BANK11246_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11246_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11247 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11247_DATA_W 32 +#define RFC_ULLRAM_BANK11247_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11247_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11248 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11248_DATA_W 32 +#define RFC_ULLRAM_BANK11248_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11248_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11249 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11249_DATA_W 32 +#define RFC_ULLRAM_BANK11249_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11249_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11250 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11250_DATA_W 32 +#define RFC_ULLRAM_BANK11250_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11250_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11251 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11251_DATA_W 32 +#define RFC_ULLRAM_BANK11251_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11251_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11252 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11252_DATA_W 32 +#define RFC_ULLRAM_BANK11252_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11252_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11253 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11253_DATA_W 32 +#define RFC_ULLRAM_BANK11253_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11253_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11254 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11254_DATA_W 32 +#define RFC_ULLRAM_BANK11254_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11254_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11255 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11255_DATA_W 32 +#define RFC_ULLRAM_BANK11255_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11255_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11256 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11256_DATA_W 32 +#define RFC_ULLRAM_BANK11256_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11256_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11257 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11257_DATA_W 32 +#define RFC_ULLRAM_BANK11257_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11257_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11258 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11258_DATA_W 32 +#define RFC_ULLRAM_BANK11258_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11258_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11259 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11259_DATA_W 32 +#define RFC_ULLRAM_BANK11259_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11259_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11260 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11260_DATA_W 32 +#define RFC_ULLRAM_BANK11260_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11260_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11261 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11261_DATA_W 32 +#define RFC_ULLRAM_BANK11261_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11261_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11262 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11262_DATA_W 32 +#define RFC_ULLRAM_BANK11262_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11262_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11263 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11263_DATA_W 32 +#define RFC_ULLRAM_BANK11263_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11263_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11264 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11264_DATA_W 32 +#define RFC_ULLRAM_BANK11264_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11264_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11265 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11265_DATA_W 32 +#define RFC_ULLRAM_BANK11265_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11265_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11266 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11266_DATA_W 32 +#define RFC_ULLRAM_BANK11266_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11266_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11267 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11267_DATA_W 32 +#define RFC_ULLRAM_BANK11267_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11267_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11268 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11268_DATA_W 32 +#define RFC_ULLRAM_BANK11268_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11268_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11269 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11269_DATA_W 32 +#define RFC_ULLRAM_BANK11269_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11269_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11270 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11270_DATA_W 32 +#define RFC_ULLRAM_BANK11270_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11270_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11271 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11271_DATA_W 32 +#define RFC_ULLRAM_BANK11271_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11271_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11272 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11272_DATA_W 32 +#define RFC_ULLRAM_BANK11272_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11272_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11273 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11273_DATA_W 32 +#define RFC_ULLRAM_BANK11273_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11273_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11274 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11274_DATA_W 32 +#define RFC_ULLRAM_BANK11274_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11274_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11275 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11275_DATA_W 32 +#define RFC_ULLRAM_BANK11275_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11275_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11276 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11276_DATA_W 32 +#define RFC_ULLRAM_BANK11276_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11276_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11277 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11277_DATA_W 32 +#define RFC_ULLRAM_BANK11277_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11277_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11278 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11278_DATA_W 32 +#define RFC_ULLRAM_BANK11278_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11278_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11279 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11279_DATA_W 32 +#define RFC_ULLRAM_BANK11279_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11279_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11280 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11280_DATA_W 32 +#define RFC_ULLRAM_BANK11280_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11280_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11281 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11281_DATA_W 32 +#define RFC_ULLRAM_BANK11281_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11281_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11282 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11282_DATA_W 32 +#define RFC_ULLRAM_BANK11282_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11282_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11283 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11283_DATA_W 32 +#define RFC_ULLRAM_BANK11283_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11283_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11284 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11284_DATA_W 32 +#define RFC_ULLRAM_BANK11284_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11284_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11285 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11285_DATA_W 32 +#define RFC_ULLRAM_BANK11285_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11285_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11286 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11286_DATA_W 32 +#define RFC_ULLRAM_BANK11286_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11286_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11287 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11287_DATA_W 32 +#define RFC_ULLRAM_BANK11287_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11287_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11288 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11288_DATA_W 32 +#define RFC_ULLRAM_BANK11288_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11288_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11289 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11289_DATA_W 32 +#define RFC_ULLRAM_BANK11289_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11289_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11290 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11290_DATA_W 32 +#define RFC_ULLRAM_BANK11290_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11290_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11291 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11291_DATA_W 32 +#define RFC_ULLRAM_BANK11291_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11291_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11292 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11292_DATA_W 32 +#define RFC_ULLRAM_BANK11292_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11292_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11293 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11293_DATA_W 32 +#define RFC_ULLRAM_BANK11293_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11293_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11294 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11294_DATA_W 32 +#define RFC_ULLRAM_BANK11294_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11294_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11295 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11295_DATA_W 32 +#define RFC_ULLRAM_BANK11295_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11295_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11296 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11296_DATA_W 32 +#define RFC_ULLRAM_BANK11296_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11296_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11297 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11297_DATA_W 32 +#define RFC_ULLRAM_BANK11297_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11297_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11298 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11298_DATA_W 32 +#define RFC_ULLRAM_BANK11298_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11298_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11299 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11299_DATA_W 32 +#define RFC_ULLRAM_BANK11299_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11299_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11300 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11300_DATA_W 32 +#define RFC_ULLRAM_BANK11300_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11300_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11301 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11301_DATA_W 32 +#define RFC_ULLRAM_BANK11301_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11301_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11302 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11302_DATA_W 32 +#define RFC_ULLRAM_BANK11302_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11302_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11303 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11303_DATA_W 32 +#define RFC_ULLRAM_BANK11303_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11303_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11304 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11304_DATA_W 32 +#define RFC_ULLRAM_BANK11304_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11304_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11305 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11305_DATA_W 32 +#define RFC_ULLRAM_BANK11305_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11305_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11306 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11306_DATA_W 32 +#define RFC_ULLRAM_BANK11306_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11306_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11307 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11307_DATA_W 32 +#define RFC_ULLRAM_BANK11307_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11307_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11308 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11308_DATA_W 32 +#define RFC_ULLRAM_BANK11308_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11308_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11309 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11309_DATA_W 32 +#define RFC_ULLRAM_BANK11309_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11309_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11310 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11310_DATA_W 32 +#define RFC_ULLRAM_BANK11310_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11310_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11311 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11311_DATA_W 32 +#define RFC_ULLRAM_BANK11311_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11311_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11312 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11312_DATA_W 32 +#define RFC_ULLRAM_BANK11312_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11312_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11313 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11313_DATA_W 32 +#define RFC_ULLRAM_BANK11313_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11313_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11314 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11314_DATA_W 32 +#define RFC_ULLRAM_BANK11314_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11314_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11315 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11315_DATA_W 32 +#define RFC_ULLRAM_BANK11315_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11315_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11316 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11316_DATA_W 32 +#define RFC_ULLRAM_BANK11316_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11316_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11317 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11317_DATA_W 32 +#define RFC_ULLRAM_BANK11317_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11317_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11318 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11318_DATA_W 32 +#define RFC_ULLRAM_BANK11318_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11318_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11319 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11319_DATA_W 32 +#define RFC_ULLRAM_BANK11319_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11319_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11320 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11320_DATA_W 32 +#define RFC_ULLRAM_BANK11320_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11320_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11321 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11321_DATA_W 32 +#define RFC_ULLRAM_BANK11321_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11321_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11322 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11322_DATA_W 32 +#define RFC_ULLRAM_BANK11322_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11322_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11323 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11323_DATA_W 32 +#define RFC_ULLRAM_BANK11323_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11323_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11324 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11324_DATA_W 32 +#define RFC_ULLRAM_BANK11324_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11324_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11325 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11325_DATA_W 32 +#define RFC_ULLRAM_BANK11325_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11325_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11326 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11326_DATA_W 32 +#define RFC_ULLRAM_BANK11326_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11326_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11327 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11327_DATA_W 32 +#define RFC_ULLRAM_BANK11327_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11327_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11328 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11328_DATA_W 32 +#define RFC_ULLRAM_BANK11328_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11328_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11329 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11329_DATA_W 32 +#define RFC_ULLRAM_BANK11329_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11329_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11330 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11330_DATA_W 32 +#define RFC_ULLRAM_BANK11330_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11330_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11331 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11331_DATA_W 32 +#define RFC_ULLRAM_BANK11331_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11331_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11332 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11332_DATA_W 32 +#define RFC_ULLRAM_BANK11332_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11332_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11333 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11333_DATA_W 32 +#define RFC_ULLRAM_BANK11333_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11333_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11334 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11334_DATA_W 32 +#define RFC_ULLRAM_BANK11334_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11334_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11335 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11335_DATA_W 32 +#define RFC_ULLRAM_BANK11335_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11335_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11336 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11336_DATA_W 32 +#define RFC_ULLRAM_BANK11336_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11336_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11337 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11337_DATA_W 32 +#define RFC_ULLRAM_BANK11337_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11337_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11338 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11338_DATA_W 32 +#define RFC_ULLRAM_BANK11338_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11338_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11339 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11339_DATA_W 32 +#define RFC_ULLRAM_BANK11339_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11339_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11340 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11340_DATA_W 32 +#define RFC_ULLRAM_BANK11340_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11340_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11341 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11341_DATA_W 32 +#define RFC_ULLRAM_BANK11341_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11341_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11342 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11342_DATA_W 32 +#define RFC_ULLRAM_BANK11342_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11342_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11343 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11343_DATA_W 32 +#define RFC_ULLRAM_BANK11343_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11343_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11344 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11344_DATA_W 32 +#define RFC_ULLRAM_BANK11344_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11344_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11345 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11345_DATA_W 32 +#define RFC_ULLRAM_BANK11345_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11345_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11346 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11346_DATA_W 32 +#define RFC_ULLRAM_BANK11346_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11346_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11347 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11347_DATA_W 32 +#define RFC_ULLRAM_BANK11347_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11347_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11348 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11348_DATA_W 32 +#define RFC_ULLRAM_BANK11348_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11348_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11349 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11349_DATA_W 32 +#define RFC_ULLRAM_BANK11349_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11349_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11350 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11350_DATA_W 32 +#define RFC_ULLRAM_BANK11350_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11350_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11351 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11351_DATA_W 32 +#define RFC_ULLRAM_BANK11351_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11351_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11352 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11352_DATA_W 32 +#define RFC_ULLRAM_BANK11352_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11352_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11353 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11353_DATA_W 32 +#define RFC_ULLRAM_BANK11353_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11353_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11354 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11354_DATA_W 32 +#define RFC_ULLRAM_BANK11354_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11354_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11355 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11355_DATA_W 32 +#define RFC_ULLRAM_BANK11355_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11355_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11356 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11356_DATA_W 32 +#define RFC_ULLRAM_BANK11356_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11356_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11357 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11357_DATA_W 32 +#define RFC_ULLRAM_BANK11357_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11357_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11358 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11358_DATA_W 32 +#define RFC_ULLRAM_BANK11358_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11358_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11359 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11359_DATA_W 32 +#define RFC_ULLRAM_BANK11359_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11359_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11360 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11360_DATA_W 32 +#define RFC_ULLRAM_BANK11360_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11360_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11361 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11361_DATA_W 32 +#define RFC_ULLRAM_BANK11361_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11361_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11362 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11362_DATA_W 32 +#define RFC_ULLRAM_BANK11362_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11362_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11363 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11363_DATA_W 32 +#define RFC_ULLRAM_BANK11363_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11363_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11364 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11364_DATA_W 32 +#define RFC_ULLRAM_BANK11364_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11364_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11365 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11365_DATA_W 32 +#define RFC_ULLRAM_BANK11365_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11365_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11366 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11366_DATA_W 32 +#define RFC_ULLRAM_BANK11366_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11366_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11367 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11367_DATA_W 32 +#define RFC_ULLRAM_BANK11367_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11367_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11368 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11368_DATA_W 32 +#define RFC_ULLRAM_BANK11368_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11368_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11369 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11369_DATA_W 32 +#define RFC_ULLRAM_BANK11369_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11369_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11370 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11370_DATA_W 32 +#define RFC_ULLRAM_BANK11370_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11370_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11371 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11371_DATA_W 32 +#define RFC_ULLRAM_BANK11371_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11371_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11372 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11372_DATA_W 32 +#define RFC_ULLRAM_BANK11372_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11372_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11373 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11373_DATA_W 32 +#define RFC_ULLRAM_BANK11373_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11373_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11374 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11374_DATA_W 32 +#define RFC_ULLRAM_BANK11374_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11374_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11375 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11375_DATA_W 32 +#define RFC_ULLRAM_BANK11375_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11375_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11376 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11376_DATA_W 32 +#define RFC_ULLRAM_BANK11376_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11376_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11377 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11377_DATA_W 32 +#define RFC_ULLRAM_BANK11377_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11377_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11378 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11378_DATA_W 32 +#define RFC_ULLRAM_BANK11378_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11378_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11379 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11379_DATA_W 32 +#define RFC_ULLRAM_BANK11379_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11379_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11380 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11380_DATA_W 32 +#define RFC_ULLRAM_BANK11380_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11380_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11381 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11381_DATA_W 32 +#define RFC_ULLRAM_BANK11381_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11381_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11382 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11382_DATA_W 32 +#define RFC_ULLRAM_BANK11382_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11382_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11383 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11383_DATA_W 32 +#define RFC_ULLRAM_BANK11383_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11383_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11384 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11384_DATA_W 32 +#define RFC_ULLRAM_BANK11384_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11384_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11385 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11385_DATA_W 32 +#define RFC_ULLRAM_BANK11385_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11385_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11386 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11386_DATA_W 32 +#define RFC_ULLRAM_BANK11386_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11386_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11387 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11387_DATA_W 32 +#define RFC_ULLRAM_BANK11387_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11387_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11388 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11388_DATA_W 32 +#define RFC_ULLRAM_BANK11388_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11388_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11389 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11389_DATA_W 32 +#define RFC_ULLRAM_BANK11389_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11389_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11390 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11390_DATA_W 32 +#define RFC_ULLRAM_BANK11390_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11390_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11391 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11391_DATA_W 32 +#define RFC_ULLRAM_BANK11391_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11391_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11392 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11392_DATA_W 32 +#define RFC_ULLRAM_BANK11392_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11392_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11393 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11393_DATA_W 32 +#define RFC_ULLRAM_BANK11393_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11393_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11394 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11394_DATA_W 32 +#define RFC_ULLRAM_BANK11394_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11394_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11395 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11395_DATA_W 32 +#define RFC_ULLRAM_BANK11395_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11395_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11396 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11396_DATA_W 32 +#define RFC_ULLRAM_BANK11396_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11396_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11397 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11397_DATA_W 32 +#define RFC_ULLRAM_BANK11397_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11397_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11398 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11398_DATA_W 32 +#define RFC_ULLRAM_BANK11398_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11398_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11399 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11399_DATA_W 32 +#define RFC_ULLRAM_BANK11399_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11399_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11400 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11400_DATA_W 32 +#define RFC_ULLRAM_BANK11400_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11400_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11401 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11401_DATA_W 32 +#define RFC_ULLRAM_BANK11401_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11401_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11402 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11402_DATA_W 32 +#define RFC_ULLRAM_BANK11402_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11402_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11403 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11403_DATA_W 32 +#define RFC_ULLRAM_BANK11403_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11403_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11404 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11404_DATA_W 32 +#define RFC_ULLRAM_BANK11404_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11404_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11405 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11405_DATA_W 32 +#define RFC_ULLRAM_BANK11405_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11405_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11406 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11406_DATA_W 32 +#define RFC_ULLRAM_BANK11406_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11406_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11407 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11407_DATA_W 32 +#define RFC_ULLRAM_BANK11407_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11407_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11408 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11408_DATA_W 32 +#define RFC_ULLRAM_BANK11408_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11408_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11409 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11409_DATA_W 32 +#define RFC_ULLRAM_BANK11409_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11409_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11410 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11410_DATA_W 32 +#define RFC_ULLRAM_BANK11410_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11410_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11411 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11411_DATA_W 32 +#define RFC_ULLRAM_BANK11411_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11411_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11412 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11412_DATA_W 32 +#define RFC_ULLRAM_BANK11412_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11412_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11413 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11413_DATA_W 32 +#define RFC_ULLRAM_BANK11413_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11413_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11414 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11414_DATA_W 32 +#define RFC_ULLRAM_BANK11414_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11414_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11415 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11415_DATA_W 32 +#define RFC_ULLRAM_BANK11415_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11415_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11416 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11416_DATA_W 32 +#define RFC_ULLRAM_BANK11416_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11416_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11417 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11417_DATA_W 32 +#define RFC_ULLRAM_BANK11417_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11417_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11418 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11418_DATA_W 32 +#define RFC_ULLRAM_BANK11418_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11418_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11419 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11419_DATA_W 32 +#define RFC_ULLRAM_BANK11419_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11419_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11420 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11420_DATA_W 32 +#define RFC_ULLRAM_BANK11420_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11420_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11421 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11421_DATA_W 32 +#define RFC_ULLRAM_BANK11421_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11421_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11422 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11422_DATA_W 32 +#define RFC_ULLRAM_BANK11422_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11422_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11423 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11423_DATA_W 32 +#define RFC_ULLRAM_BANK11423_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11423_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11424 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11424_DATA_W 32 +#define RFC_ULLRAM_BANK11424_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11424_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11425 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11425_DATA_W 32 +#define RFC_ULLRAM_BANK11425_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11425_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11426 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11426_DATA_W 32 +#define RFC_ULLRAM_BANK11426_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11426_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11427 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11427_DATA_W 32 +#define RFC_ULLRAM_BANK11427_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11427_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11428 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11428_DATA_W 32 +#define RFC_ULLRAM_BANK11428_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11428_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11429 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11429_DATA_W 32 +#define RFC_ULLRAM_BANK11429_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11429_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11430 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11430_DATA_W 32 +#define RFC_ULLRAM_BANK11430_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11430_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11431 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11431_DATA_W 32 +#define RFC_ULLRAM_BANK11431_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11431_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11432 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11432_DATA_W 32 +#define RFC_ULLRAM_BANK11432_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11432_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11433 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11433_DATA_W 32 +#define RFC_ULLRAM_BANK11433_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11433_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11434 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11434_DATA_W 32 +#define RFC_ULLRAM_BANK11434_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11434_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11435 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11435_DATA_W 32 +#define RFC_ULLRAM_BANK11435_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11435_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11436 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11436_DATA_W 32 +#define RFC_ULLRAM_BANK11436_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11436_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11437 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11437_DATA_W 32 +#define RFC_ULLRAM_BANK11437_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11437_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11438 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11438_DATA_W 32 +#define RFC_ULLRAM_BANK11438_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11438_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11439 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11439_DATA_W 32 +#define RFC_ULLRAM_BANK11439_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11439_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11440 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11440_DATA_W 32 +#define RFC_ULLRAM_BANK11440_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11440_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11441 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11441_DATA_W 32 +#define RFC_ULLRAM_BANK11441_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11441_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11442 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11442_DATA_W 32 +#define RFC_ULLRAM_BANK11442_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11442_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11443 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11443_DATA_W 32 +#define RFC_ULLRAM_BANK11443_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11443_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11444 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11444_DATA_W 32 +#define RFC_ULLRAM_BANK11444_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11444_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11445 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11445_DATA_W 32 +#define RFC_ULLRAM_BANK11445_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11445_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11446 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11446_DATA_W 32 +#define RFC_ULLRAM_BANK11446_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11446_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11447 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11447_DATA_W 32 +#define RFC_ULLRAM_BANK11447_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11447_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11448 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11448_DATA_W 32 +#define RFC_ULLRAM_BANK11448_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11448_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11449 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11449_DATA_W 32 +#define RFC_ULLRAM_BANK11449_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11449_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11450 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11450_DATA_W 32 +#define RFC_ULLRAM_BANK11450_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11450_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11451 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11451_DATA_W 32 +#define RFC_ULLRAM_BANK11451_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11451_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11452 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11452_DATA_W 32 +#define RFC_ULLRAM_BANK11452_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11452_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11453 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11453_DATA_W 32 +#define RFC_ULLRAM_BANK11453_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11453_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11454 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11454_DATA_W 32 +#define RFC_ULLRAM_BANK11454_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11454_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11455 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11455_DATA_W 32 +#define RFC_ULLRAM_BANK11455_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11455_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11456 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11456_DATA_W 32 +#define RFC_ULLRAM_BANK11456_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11456_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11457 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11457_DATA_W 32 +#define RFC_ULLRAM_BANK11457_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11457_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11458 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11458_DATA_W 32 +#define RFC_ULLRAM_BANK11458_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11458_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11459 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11459_DATA_W 32 +#define RFC_ULLRAM_BANK11459_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11459_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11460 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11460_DATA_W 32 +#define RFC_ULLRAM_BANK11460_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11460_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11461 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11461_DATA_W 32 +#define RFC_ULLRAM_BANK11461_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11461_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11462 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11462_DATA_W 32 +#define RFC_ULLRAM_BANK11462_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11462_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11463 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11463_DATA_W 32 +#define RFC_ULLRAM_BANK11463_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11463_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11464 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11464_DATA_W 32 +#define RFC_ULLRAM_BANK11464_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11464_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11465 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11465_DATA_W 32 +#define RFC_ULLRAM_BANK11465_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11465_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11466 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11466_DATA_W 32 +#define RFC_ULLRAM_BANK11466_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11466_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11467 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11467_DATA_W 32 +#define RFC_ULLRAM_BANK11467_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11467_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11468 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11468_DATA_W 32 +#define RFC_ULLRAM_BANK11468_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11468_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11469 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11469_DATA_W 32 +#define RFC_ULLRAM_BANK11469_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11469_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11470 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11470_DATA_W 32 +#define RFC_ULLRAM_BANK11470_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11470_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11471 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11471_DATA_W 32 +#define RFC_ULLRAM_BANK11471_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11471_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11472 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11472_DATA_W 32 +#define RFC_ULLRAM_BANK11472_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11472_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11473 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11473_DATA_W 32 +#define RFC_ULLRAM_BANK11473_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11473_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11474 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11474_DATA_W 32 +#define RFC_ULLRAM_BANK11474_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11474_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11475 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11475_DATA_W 32 +#define RFC_ULLRAM_BANK11475_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11475_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11476 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11476_DATA_W 32 +#define RFC_ULLRAM_BANK11476_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11476_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11477 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11477_DATA_W 32 +#define RFC_ULLRAM_BANK11477_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11477_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11478 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11478_DATA_W 32 +#define RFC_ULLRAM_BANK11478_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11478_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11479 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11479_DATA_W 32 +#define RFC_ULLRAM_BANK11479_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11479_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11480 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11480_DATA_W 32 +#define RFC_ULLRAM_BANK11480_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11480_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11481 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11481_DATA_W 32 +#define RFC_ULLRAM_BANK11481_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11481_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11482 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11482_DATA_W 32 +#define RFC_ULLRAM_BANK11482_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11482_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11483 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11483_DATA_W 32 +#define RFC_ULLRAM_BANK11483_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11483_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11484 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11484_DATA_W 32 +#define RFC_ULLRAM_BANK11484_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11484_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11485 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11485_DATA_W 32 +#define RFC_ULLRAM_BANK11485_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11485_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11486 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11486_DATA_W 32 +#define RFC_ULLRAM_BANK11486_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11486_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11487 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11487_DATA_W 32 +#define RFC_ULLRAM_BANK11487_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11487_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11488 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11488_DATA_W 32 +#define RFC_ULLRAM_BANK11488_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11488_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11489 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11489_DATA_W 32 +#define RFC_ULLRAM_BANK11489_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11489_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11490 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11490_DATA_W 32 +#define RFC_ULLRAM_BANK11490_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11490_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11491 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11491_DATA_W 32 +#define RFC_ULLRAM_BANK11491_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11491_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11492 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11492_DATA_W 32 +#define RFC_ULLRAM_BANK11492_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11492_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11493 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11493_DATA_W 32 +#define RFC_ULLRAM_BANK11493_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11493_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11494 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11494_DATA_W 32 +#define RFC_ULLRAM_BANK11494_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11494_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11495 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11495_DATA_W 32 +#define RFC_ULLRAM_BANK11495_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11495_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11496 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11496_DATA_W 32 +#define RFC_ULLRAM_BANK11496_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11496_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11497 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11497_DATA_W 32 +#define RFC_ULLRAM_BANK11497_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11497_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11498 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11498_DATA_W 32 +#define RFC_ULLRAM_BANK11498_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11498_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11499 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11499_DATA_W 32 +#define RFC_ULLRAM_BANK11499_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11499_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11500 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11500_DATA_W 32 +#define RFC_ULLRAM_BANK11500_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11500_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11501 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11501_DATA_W 32 +#define RFC_ULLRAM_BANK11501_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11501_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11502 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11502_DATA_W 32 +#define RFC_ULLRAM_BANK11502_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11502_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11503 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11503_DATA_W 32 +#define RFC_ULLRAM_BANK11503_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11503_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11504 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11504_DATA_W 32 +#define RFC_ULLRAM_BANK11504_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11504_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11505 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11505_DATA_W 32 +#define RFC_ULLRAM_BANK11505_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11505_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11506 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11506_DATA_W 32 +#define RFC_ULLRAM_BANK11506_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11506_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11507 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11507_DATA_W 32 +#define RFC_ULLRAM_BANK11507_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11507_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11508 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11508_DATA_W 32 +#define RFC_ULLRAM_BANK11508_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11508_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11509 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11509_DATA_W 32 +#define RFC_ULLRAM_BANK11509_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11509_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11510 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11510_DATA_W 32 +#define RFC_ULLRAM_BANK11510_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11510_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11511 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11511_DATA_W 32 +#define RFC_ULLRAM_BANK11511_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11511_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11512 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11512_DATA_W 32 +#define RFC_ULLRAM_BANK11512_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11512_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11513 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11513_DATA_W 32 +#define RFC_ULLRAM_BANK11513_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11513_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11514 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11514_DATA_W 32 +#define RFC_ULLRAM_BANK11514_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11514_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11515 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11515_DATA_W 32 +#define RFC_ULLRAM_BANK11515_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11515_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11516 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11516_DATA_W 32 +#define RFC_ULLRAM_BANK11516_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11516_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11517 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11517_DATA_W 32 +#define RFC_ULLRAM_BANK11517_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11517_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11518 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11518_DATA_W 32 +#define RFC_ULLRAM_BANK11518_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11518_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11519 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11519_DATA_W 32 +#define RFC_ULLRAM_BANK11519_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11519_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11520 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11520_DATA_W 32 +#define RFC_ULLRAM_BANK11520_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11520_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11521 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11521_DATA_W 32 +#define RFC_ULLRAM_BANK11521_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11521_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11522 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11522_DATA_W 32 +#define RFC_ULLRAM_BANK11522_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11522_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11523 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11523_DATA_W 32 +#define RFC_ULLRAM_BANK11523_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11523_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11524 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11524_DATA_W 32 +#define RFC_ULLRAM_BANK11524_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11524_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11525 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11525_DATA_W 32 +#define RFC_ULLRAM_BANK11525_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11525_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11526 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11526_DATA_W 32 +#define RFC_ULLRAM_BANK11526_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11526_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11527 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11527_DATA_W 32 +#define RFC_ULLRAM_BANK11527_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11527_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11528 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11528_DATA_W 32 +#define RFC_ULLRAM_BANK11528_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11528_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11529 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11529_DATA_W 32 +#define RFC_ULLRAM_BANK11529_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11529_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11530 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11530_DATA_W 32 +#define RFC_ULLRAM_BANK11530_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11530_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11531 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11531_DATA_W 32 +#define RFC_ULLRAM_BANK11531_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11531_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11532 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11532_DATA_W 32 +#define RFC_ULLRAM_BANK11532_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11532_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11533 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11533_DATA_W 32 +#define RFC_ULLRAM_BANK11533_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11533_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11534 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11534_DATA_W 32 +#define RFC_ULLRAM_BANK11534_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11534_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11535 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11535_DATA_W 32 +#define RFC_ULLRAM_BANK11535_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11535_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11536 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11536_DATA_W 32 +#define RFC_ULLRAM_BANK11536_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11536_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11537 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11537_DATA_W 32 +#define RFC_ULLRAM_BANK11537_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11537_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11538 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11538_DATA_W 32 +#define RFC_ULLRAM_BANK11538_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11538_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11539 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11539_DATA_W 32 +#define RFC_ULLRAM_BANK11539_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11539_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11540 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11540_DATA_W 32 +#define RFC_ULLRAM_BANK11540_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11540_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11541 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11541_DATA_W 32 +#define RFC_ULLRAM_BANK11541_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11541_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11542 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11542_DATA_W 32 +#define RFC_ULLRAM_BANK11542_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11542_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11543 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11543_DATA_W 32 +#define RFC_ULLRAM_BANK11543_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11543_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11544 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11544_DATA_W 32 +#define RFC_ULLRAM_BANK11544_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11544_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11545 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11545_DATA_W 32 +#define RFC_ULLRAM_BANK11545_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11545_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11546 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11546_DATA_W 32 +#define RFC_ULLRAM_BANK11546_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11546_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11547 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11547_DATA_W 32 +#define RFC_ULLRAM_BANK11547_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11547_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11548 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11548_DATA_W 32 +#define RFC_ULLRAM_BANK11548_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11548_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11549 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11549_DATA_W 32 +#define RFC_ULLRAM_BANK11549_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11549_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11550 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11550_DATA_W 32 +#define RFC_ULLRAM_BANK11550_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11550_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11551 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11551_DATA_W 32 +#define RFC_ULLRAM_BANK11551_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11551_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11552 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11552_DATA_W 32 +#define RFC_ULLRAM_BANK11552_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11552_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11553 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11553_DATA_W 32 +#define RFC_ULLRAM_BANK11553_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11553_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11554 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11554_DATA_W 32 +#define RFC_ULLRAM_BANK11554_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11554_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11555 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11555_DATA_W 32 +#define RFC_ULLRAM_BANK11555_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11555_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11556 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11556_DATA_W 32 +#define RFC_ULLRAM_BANK11556_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11556_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11557 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11557_DATA_W 32 +#define RFC_ULLRAM_BANK11557_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11557_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11558 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11558_DATA_W 32 +#define RFC_ULLRAM_BANK11558_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11558_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11559 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11559_DATA_W 32 +#define RFC_ULLRAM_BANK11559_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11559_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11560 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11560_DATA_W 32 +#define RFC_ULLRAM_BANK11560_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11560_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11561 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11561_DATA_W 32 +#define RFC_ULLRAM_BANK11561_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11561_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11562 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11562_DATA_W 32 +#define RFC_ULLRAM_BANK11562_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11562_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11563 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11563_DATA_W 32 +#define RFC_ULLRAM_BANK11563_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11563_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11564 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11564_DATA_W 32 +#define RFC_ULLRAM_BANK11564_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11564_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11565 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11565_DATA_W 32 +#define RFC_ULLRAM_BANK11565_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11565_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11566 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11566_DATA_W 32 +#define RFC_ULLRAM_BANK11566_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11566_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11567 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11567_DATA_W 32 +#define RFC_ULLRAM_BANK11567_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11567_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11568 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11568_DATA_W 32 +#define RFC_ULLRAM_BANK11568_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11568_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11569 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11569_DATA_W 32 +#define RFC_ULLRAM_BANK11569_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11569_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11570 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11570_DATA_W 32 +#define RFC_ULLRAM_BANK11570_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11570_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11571 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11571_DATA_W 32 +#define RFC_ULLRAM_BANK11571_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11571_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11572 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11572_DATA_W 32 +#define RFC_ULLRAM_BANK11572_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11572_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11573 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11573_DATA_W 32 +#define RFC_ULLRAM_BANK11573_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11573_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11574 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11574_DATA_W 32 +#define RFC_ULLRAM_BANK11574_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11574_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11575 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11575_DATA_W 32 +#define RFC_ULLRAM_BANK11575_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11575_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11576 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11576_DATA_W 32 +#define RFC_ULLRAM_BANK11576_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11576_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11577 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11577_DATA_W 32 +#define RFC_ULLRAM_BANK11577_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11577_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11578 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11578_DATA_W 32 +#define RFC_ULLRAM_BANK11578_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11578_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11579 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11579_DATA_W 32 +#define RFC_ULLRAM_BANK11579_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11579_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11580 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11580_DATA_W 32 +#define RFC_ULLRAM_BANK11580_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11580_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11581 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11581_DATA_W 32 +#define RFC_ULLRAM_BANK11581_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11581_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11582 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11582_DATA_W 32 +#define RFC_ULLRAM_BANK11582_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11582_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11583 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11583_DATA_W 32 +#define RFC_ULLRAM_BANK11583_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11583_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11584 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11584_DATA_W 32 +#define RFC_ULLRAM_BANK11584_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11584_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11585 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11585_DATA_W 32 +#define RFC_ULLRAM_BANK11585_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11585_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11586 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11586_DATA_W 32 +#define RFC_ULLRAM_BANK11586_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11586_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11587 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11587_DATA_W 32 +#define RFC_ULLRAM_BANK11587_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11587_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11588 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11588_DATA_W 32 +#define RFC_ULLRAM_BANK11588_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11588_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11589 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11589_DATA_W 32 +#define RFC_ULLRAM_BANK11589_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11589_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11590 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11590_DATA_W 32 +#define RFC_ULLRAM_BANK11590_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11590_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11591 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11591_DATA_W 32 +#define RFC_ULLRAM_BANK11591_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11591_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11592 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11592_DATA_W 32 +#define RFC_ULLRAM_BANK11592_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11592_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11593 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11593_DATA_W 32 +#define RFC_ULLRAM_BANK11593_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11593_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11594 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11594_DATA_W 32 +#define RFC_ULLRAM_BANK11594_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11594_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11595 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11595_DATA_W 32 +#define RFC_ULLRAM_BANK11595_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11595_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11596 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11596_DATA_W 32 +#define RFC_ULLRAM_BANK11596_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11596_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11597 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11597_DATA_W 32 +#define RFC_ULLRAM_BANK11597_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11597_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11598 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11598_DATA_W 32 +#define RFC_ULLRAM_BANK11598_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11598_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11599 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11599_DATA_W 32 +#define RFC_ULLRAM_BANK11599_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11599_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11600 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11600_DATA_W 32 +#define RFC_ULLRAM_BANK11600_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11600_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11601 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11601_DATA_W 32 +#define RFC_ULLRAM_BANK11601_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11601_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11602 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11602_DATA_W 32 +#define RFC_ULLRAM_BANK11602_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11602_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11603 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11603_DATA_W 32 +#define RFC_ULLRAM_BANK11603_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11603_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11604 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11604_DATA_W 32 +#define RFC_ULLRAM_BANK11604_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11604_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11605 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11605_DATA_W 32 +#define RFC_ULLRAM_BANK11605_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11605_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11606 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11606_DATA_W 32 +#define RFC_ULLRAM_BANK11606_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11606_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11607 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11607_DATA_W 32 +#define RFC_ULLRAM_BANK11607_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11607_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11608 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11608_DATA_W 32 +#define RFC_ULLRAM_BANK11608_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11608_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11609 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11609_DATA_W 32 +#define RFC_ULLRAM_BANK11609_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11609_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11610 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11610_DATA_W 32 +#define RFC_ULLRAM_BANK11610_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11610_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11611 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11611_DATA_W 32 +#define RFC_ULLRAM_BANK11611_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11611_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11612 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11612_DATA_W 32 +#define RFC_ULLRAM_BANK11612_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11612_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11613 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11613_DATA_W 32 +#define RFC_ULLRAM_BANK11613_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11613_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11614 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11614_DATA_W 32 +#define RFC_ULLRAM_BANK11614_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11614_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11615 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11615_DATA_W 32 +#define RFC_ULLRAM_BANK11615_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11615_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11616 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11616_DATA_W 32 +#define RFC_ULLRAM_BANK11616_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11616_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11617 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11617_DATA_W 32 +#define RFC_ULLRAM_BANK11617_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11617_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11618 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11618_DATA_W 32 +#define RFC_ULLRAM_BANK11618_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11618_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11619 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11619_DATA_W 32 +#define RFC_ULLRAM_BANK11619_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11619_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11620 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11620_DATA_W 32 +#define RFC_ULLRAM_BANK11620_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11620_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11621 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11621_DATA_W 32 +#define RFC_ULLRAM_BANK11621_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11621_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11622 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11622_DATA_W 32 +#define RFC_ULLRAM_BANK11622_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11622_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11623 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11623_DATA_W 32 +#define RFC_ULLRAM_BANK11623_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11623_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11624 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11624_DATA_W 32 +#define RFC_ULLRAM_BANK11624_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11624_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11625 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11625_DATA_W 32 +#define RFC_ULLRAM_BANK11625_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11625_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11626 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11626_DATA_W 32 +#define RFC_ULLRAM_BANK11626_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11626_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11627 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11627_DATA_W 32 +#define RFC_ULLRAM_BANK11627_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11627_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11628 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11628_DATA_W 32 +#define RFC_ULLRAM_BANK11628_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11628_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11629 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11629_DATA_W 32 +#define RFC_ULLRAM_BANK11629_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11629_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11630 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11630_DATA_W 32 +#define RFC_ULLRAM_BANK11630_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11630_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11631 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11631_DATA_W 32 +#define RFC_ULLRAM_BANK11631_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11631_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11632 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11632_DATA_W 32 +#define RFC_ULLRAM_BANK11632_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11632_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11633 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11633_DATA_W 32 +#define RFC_ULLRAM_BANK11633_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11633_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11634 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11634_DATA_W 32 +#define RFC_ULLRAM_BANK11634_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11634_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11635 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11635_DATA_W 32 +#define RFC_ULLRAM_BANK11635_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11635_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11636 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11636_DATA_W 32 +#define RFC_ULLRAM_BANK11636_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11636_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11637 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11637_DATA_W 32 +#define RFC_ULLRAM_BANK11637_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11637_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11638 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11638_DATA_W 32 +#define RFC_ULLRAM_BANK11638_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11638_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11639 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11639_DATA_W 32 +#define RFC_ULLRAM_BANK11639_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11639_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11640 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11640_DATA_W 32 +#define RFC_ULLRAM_BANK11640_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11640_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11641 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11641_DATA_W 32 +#define RFC_ULLRAM_BANK11641_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11641_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11642 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11642_DATA_W 32 +#define RFC_ULLRAM_BANK11642_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11642_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11643 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11643_DATA_W 32 +#define RFC_ULLRAM_BANK11643_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11643_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11644 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11644_DATA_W 32 +#define RFC_ULLRAM_BANK11644_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11644_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11645 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11645_DATA_W 32 +#define RFC_ULLRAM_BANK11645_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11645_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11646 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11646_DATA_W 32 +#define RFC_ULLRAM_BANK11646_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11646_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11647 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11647_DATA_W 32 +#define RFC_ULLRAM_BANK11647_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11647_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11648 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11648_DATA_W 32 +#define RFC_ULLRAM_BANK11648_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11648_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11649 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11649_DATA_W 32 +#define RFC_ULLRAM_BANK11649_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11649_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11650 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11650_DATA_W 32 +#define RFC_ULLRAM_BANK11650_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11650_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11651 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11651_DATA_W 32 +#define RFC_ULLRAM_BANK11651_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11651_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11652 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11652_DATA_W 32 +#define RFC_ULLRAM_BANK11652_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11652_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11653 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11653_DATA_W 32 +#define RFC_ULLRAM_BANK11653_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11653_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11654 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11654_DATA_W 32 +#define RFC_ULLRAM_BANK11654_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11654_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11655 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11655_DATA_W 32 +#define RFC_ULLRAM_BANK11655_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11655_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11656 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11656_DATA_W 32 +#define RFC_ULLRAM_BANK11656_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11656_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11657 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11657_DATA_W 32 +#define RFC_ULLRAM_BANK11657_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11657_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11658 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11658_DATA_W 32 +#define RFC_ULLRAM_BANK11658_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11658_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11659 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11659_DATA_W 32 +#define RFC_ULLRAM_BANK11659_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11659_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11660 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11660_DATA_W 32 +#define RFC_ULLRAM_BANK11660_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11660_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11661 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11661_DATA_W 32 +#define RFC_ULLRAM_BANK11661_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11661_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11662 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11662_DATA_W 32 +#define RFC_ULLRAM_BANK11662_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11662_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11663 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11663_DATA_W 32 +#define RFC_ULLRAM_BANK11663_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11663_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11664 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11664_DATA_W 32 +#define RFC_ULLRAM_BANK11664_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11664_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11665 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11665_DATA_W 32 +#define RFC_ULLRAM_BANK11665_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11665_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11666 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11666_DATA_W 32 +#define RFC_ULLRAM_BANK11666_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11666_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11667 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11667_DATA_W 32 +#define RFC_ULLRAM_BANK11667_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11667_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11668 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11668_DATA_W 32 +#define RFC_ULLRAM_BANK11668_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11668_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11669 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11669_DATA_W 32 +#define RFC_ULLRAM_BANK11669_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11669_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11670 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11670_DATA_W 32 +#define RFC_ULLRAM_BANK11670_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11670_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11671 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11671_DATA_W 32 +#define RFC_ULLRAM_BANK11671_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11671_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11672 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11672_DATA_W 32 +#define RFC_ULLRAM_BANK11672_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11672_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11673 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11673_DATA_W 32 +#define RFC_ULLRAM_BANK11673_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11673_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11674 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11674_DATA_W 32 +#define RFC_ULLRAM_BANK11674_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11674_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11675 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11675_DATA_W 32 +#define RFC_ULLRAM_BANK11675_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11675_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11676 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11676_DATA_W 32 +#define RFC_ULLRAM_BANK11676_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11676_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11677 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11677_DATA_W 32 +#define RFC_ULLRAM_BANK11677_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11677_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11678 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11678_DATA_W 32 +#define RFC_ULLRAM_BANK11678_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11678_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11679 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11679_DATA_W 32 +#define RFC_ULLRAM_BANK11679_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11679_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11680 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11680_DATA_W 32 +#define RFC_ULLRAM_BANK11680_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11680_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11681 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11681_DATA_W 32 +#define RFC_ULLRAM_BANK11681_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11681_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11682 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11682_DATA_W 32 +#define RFC_ULLRAM_BANK11682_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11682_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11683 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11683_DATA_W 32 +#define RFC_ULLRAM_BANK11683_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11683_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11684 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11684_DATA_W 32 +#define RFC_ULLRAM_BANK11684_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11684_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11685 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11685_DATA_W 32 +#define RFC_ULLRAM_BANK11685_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11685_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11686 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11686_DATA_W 32 +#define RFC_ULLRAM_BANK11686_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11686_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11687 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11687_DATA_W 32 +#define RFC_ULLRAM_BANK11687_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11687_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11688 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11688_DATA_W 32 +#define RFC_ULLRAM_BANK11688_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11688_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11689 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11689_DATA_W 32 +#define RFC_ULLRAM_BANK11689_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11689_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11690 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11690_DATA_W 32 +#define RFC_ULLRAM_BANK11690_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11690_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11691 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11691_DATA_W 32 +#define RFC_ULLRAM_BANK11691_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11691_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11692 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11692_DATA_W 32 +#define RFC_ULLRAM_BANK11692_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11692_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11693 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11693_DATA_W 32 +#define RFC_ULLRAM_BANK11693_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11693_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11694 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11694_DATA_W 32 +#define RFC_ULLRAM_BANK11694_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11694_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11695 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11695_DATA_W 32 +#define RFC_ULLRAM_BANK11695_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11695_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11696 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11696_DATA_W 32 +#define RFC_ULLRAM_BANK11696_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11696_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11697 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11697_DATA_W 32 +#define RFC_ULLRAM_BANK11697_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11697_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11698 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11698_DATA_W 32 +#define RFC_ULLRAM_BANK11698_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11698_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11699 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11699_DATA_W 32 +#define RFC_ULLRAM_BANK11699_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11699_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11700 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11700_DATA_W 32 +#define RFC_ULLRAM_BANK11700_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11700_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11701 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11701_DATA_W 32 +#define RFC_ULLRAM_BANK11701_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11701_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11702 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11702_DATA_W 32 +#define RFC_ULLRAM_BANK11702_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11702_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11703 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11703_DATA_W 32 +#define RFC_ULLRAM_BANK11703_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11703_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11704 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11704_DATA_W 32 +#define RFC_ULLRAM_BANK11704_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11704_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11705 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11705_DATA_W 32 +#define RFC_ULLRAM_BANK11705_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11705_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11706 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11706_DATA_W 32 +#define RFC_ULLRAM_BANK11706_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11706_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11707 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11707_DATA_W 32 +#define RFC_ULLRAM_BANK11707_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11707_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11708 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11708_DATA_W 32 +#define RFC_ULLRAM_BANK11708_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11708_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11709 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11709_DATA_W 32 +#define RFC_ULLRAM_BANK11709_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11709_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11710 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11710_DATA_W 32 +#define RFC_ULLRAM_BANK11710_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11710_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11711 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11711_DATA_W 32 +#define RFC_ULLRAM_BANK11711_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11711_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11712 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11712_DATA_W 32 +#define RFC_ULLRAM_BANK11712_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11712_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11713 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11713_DATA_W 32 +#define RFC_ULLRAM_BANK11713_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11713_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11714 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11714_DATA_W 32 +#define RFC_ULLRAM_BANK11714_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11714_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11715 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11715_DATA_W 32 +#define RFC_ULLRAM_BANK11715_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11715_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11716 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11716_DATA_W 32 +#define RFC_ULLRAM_BANK11716_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11716_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11717 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11717_DATA_W 32 +#define RFC_ULLRAM_BANK11717_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11717_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11718 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11718_DATA_W 32 +#define RFC_ULLRAM_BANK11718_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11718_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11719 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11719_DATA_W 32 +#define RFC_ULLRAM_BANK11719_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11719_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11720 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11720_DATA_W 32 +#define RFC_ULLRAM_BANK11720_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11720_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11721 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11721_DATA_W 32 +#define RFC_ULLRAM_BANK11721_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11721_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11722 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11722_DATA_W 32 +#define RFC_ULLRAM_BANK11722_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11722_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11723 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11723_DATA_W 32 +#define RFC_ULLRAM_BANK11723_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11723_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11724 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11724_DATA_W 32 +#define RFC_ULLRAM_BANK11724_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11724_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11725 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11725_DATA_W 32 +#define RFC_ULLRAM_BANK11725_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11725_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11726 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11726_DATA_W 32 +#define RFC_ULLRAM_BANK11726_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11726_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11727 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11727_DATA_W 32 +#define RFC_ULLRAM_BANK11727_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11727_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11728 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11728_DATA_W 32 +#define RFC_ULLRAM_BANK11728_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11728_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11729 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11729_DATA_W 32 +#define RFC_ULLRAM_BANK11729_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11729_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11730 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11730_DATA_W 32 +#define RFC_ULLRAM_BANK11730_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11730_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11731 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11731_DATA_W 32 +#define RFC_ULLRAM_BANK11731_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11731_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11732 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11732_DATA_W 32 +#define RFC_ULLRAM_BANK11732_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11732_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11733 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11733_DATA_W 32 +#define RFC_ULLRAM_BANK11733_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11733_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11734 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11734_DATA_W 32 +#define RFC_ULLRAM_BANK11734_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11734_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11735 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11735_DATA_W 32 +#define RFC_ULLRAM_BANK11735_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11735_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11736 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11736_DATA_W 32 +#define RFC_ULLRAM_BANK11736_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11736_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11737 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11737_DATA_W 32 +#define RFC_ULLRAM_BANK11737_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11737_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11738 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11738_DATA_W 32 +#define RFC_ULLRAM_BANK11738_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11738_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11739 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11739_DATA_W 32 +#define RFC_ULLRAM_BANK11739_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11739_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11740 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11740_DATA_W 32 +#define RFC_ULLRAM_BANK11740_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11740_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11741 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11741_DATA_W 32 +#define RFC_ULLRAM_BANK11741_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11741_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11742 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11742_DATA_W 32 +#define RFC_ULLRAM_BANK11742_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11742_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11743 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11743_DATA_W 32 +#define RFC_ULLRAM_BANK11743_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11743_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11744 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11744_DATA_W 32 +#define RFC_ULLRAM_BANK11744_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11744_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11745 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11745_DATA_W 32 +#define RFC_ULLRAM_BANK11745_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11745_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11746 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11746_DATA_W 32 +#define RFC_ULLRAM_BANK11746_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11746_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11747 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11747_DATA_W 32 +#define RFC_ULLRAM_BANK11747_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11747_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11748 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11748_DATA_W 32 +#define RFC_ULLRAM_BANK11748_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11748_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11749 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11749_DATA_W 32 +#define RFC_ULLRAM_BANK11749_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11749_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11750 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11750_DATA_W 32 +#define RFC_ULLRAM_BANK11750_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11750_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11751 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11751_DATA_W 32 +#define RFC_ULLRAM_BANK11751_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11751_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11752 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11752_DATA_W 32 +#define RFC_ULLRAM_BANK11752_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11752_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11753 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11753_DATA_W 32 +#define RFC_ULLRAM_BANK11753_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11753_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11754 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11754_DATA_W 32 +#define RFC_ULLRAM_BANK11754_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11754_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11755 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11755_DATA_W 32 +#define RFC_ULLRAM_BANK11755_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11755_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11756 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11756_DATA_W 32 +#define RFC_ULLRAM_BANK11756_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11756_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11757 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11757_DATA_W 32 +#define RFC_ULLRAM_BANK11757_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11757_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11758 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11758_DATA_W 32 +#define RFC_ULLRAM_BANK11758_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11758_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11759 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11759_DATA_W 32 +#define RFC_ULLRAM_BANK11759_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11759_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11760 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11760_DATA_W 32 +#define RFC_ULLRAM_BANK11760_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11760_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11761 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11761_DATA_W 32 +#define RFC_ULLRAM_BANK11761_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11761_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11762 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11762_DATA_W 32 +#define RFC_ULLRAM_BANK11762_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11762_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11763 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11763_DATA_W 32 +#define RFC_ULLRAM_BANK11763_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11763_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11764 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11764_DATA_W 32 +#define RFC_ULLRAM_BANK11764_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11764_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11765 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11765_DATA_W 32 +#define RFC_ULLRAM_BANK11765_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11765_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11766 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11766_DATA_W 32 +#define RFC_ULLRAM_BANK11766_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11766_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11767 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11767_DATA_W 32 +#define RFC_ULLRAM_BANK11767_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11767_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11768 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11768_DATA_W 32 +#define RFC_ULLRAM_BANK11768_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11768_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11769 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11769_DATA_W 32 +#define RFC_ULLRAM_BANK11769_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11769_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11770 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11770_DATA_W 32 +#define RFC_ULLRAM_BANK11770_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11770_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11771 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11771_DATA_W 32 +#define RFC_ULLRAM_BANK11771_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11771_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11772 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11772_DATA_W 32 +#define RFC_ULLRAM_BANK11772_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11772_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11773 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11773_DATA_W 32 +#define RFC_ULLRAM_BANK11773_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11773_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11774 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11774_DATA_W 32 +#define RFC_ULLRAM_BANK11774_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11774_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11775 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11775_DATA_W 32 +#define RFC_ULLRAM_BANK11775_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11775_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11776 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11776_DATA_W 32 +#define RFC_ULLRAM_BANK11776_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11776_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11777 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11777_DATA_W 32 +#define RFC_ULLRAM_BANK11777_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11777_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11778 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11778_DATA_W 32 +#define RFC_ULLRAM_BANK11778_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11778_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11779 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11779_DATA_W 32 +#define RFC_ULLRAM_BANK11779_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11779_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11780 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11780_DATA_W 32 +#define RFC_ULLRAM_BANK11780_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11780_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11781 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11781_DATA_W 32 +#define RFC_ULLRAM_BANK11781_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11781_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11782 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11782_DATA_W 32 +#define RFC_ULLRAM_BANK11782_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11782_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11783 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11783_DATA_W 32 +#define RFC_ULLRAM_BANK11783_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11783_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11784 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11784_DATA_W 32 +#define RFC_ULLRAM_BANK11784_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11784_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11785 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11785_DATA_W 32 +#define RFC_ULLRAM_BANK11785_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11785_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11786 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11786_DATA_W 32 +#define RFC_ULLRAM_BANK11786_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11786_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11787 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11787_DATA_W 32 +#define RFC_ULLRAM_BANK11787_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11787_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11788 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11788_DATA_W 32 +#define RFC_ULLRAM_BANK11788_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11788_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11789 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11789_DATA_W 32 +#define RFC_ULLRAM_BANK11789_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11789_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11790 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11790_DATA_W 32 +#define RFC_ULLRAM_BANK11790_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11790_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11791 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11791_DATA_W 32 +#define RFC_ULLRAM_BANK11791_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11791_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11792 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11792_DATA_W 32 +#define RFC_ULLRAM_BANK11792_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11792_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11793 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11793_DATA_W 32 +#define RFC_ULLRAM_BANK11793_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11793_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11794 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11794_DATA_W 32 +#define RFC_ULLRAM_BANK11794_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11794_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11795 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11795_DATA_W 32 +#define RFC_ULLRAM_BANK11795_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11795_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11796 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11796_DATA_W 32 +#define RFC_ULLRAM_BANK11796_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11796_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11797 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11797_DATA_W 32 +#define RFC_ULLRAM_BANK11797_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11797_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11798 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11798_DATA_W 32 +#define RFC_ULLRAM_BANK11798_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11798_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11799 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11799_DATA_W 32 +#define RFC_ULLRAM_BANK11799_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11799_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11800 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11800_DATA_W 32 +#define RFC_ULLRAM_BANK11800_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11800_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11801 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11801_DATA_W 32 +#define RFC_ULLRAM_BANK11801_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11801_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11802 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11802_DATA_W 32 +#define RFC_ULLRAM_BANK11802_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11802_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11803 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11803_DATA_W 32 +#define RFC_ULLRAM_BANK11803_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11803_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11804 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11804_DATA_W 32 +#define RFC_ULLRAM_BANK11804_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11804_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11805 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11805_DATA_W 32 +#define RFC_ULLRAM_BANK11805_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11805_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11806 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11806_DATA_W 32 +#define RFC_ULLRAM_BANK11806_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11806_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11807 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11807_DATA_W 32 +#define RFC_ULLRAM_BANK11807_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11807_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11808 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11808_DATA_W 32 +#define RFC_ULLRAM_BANK11808_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11808_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11809 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11809_DATA_W 32 +#define RFC_ULLRAM_BANK11809_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11809_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11810 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11810_DATA_W 32 +#define RFC_ULLRAM_BANK11810_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11810_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11811 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11811_DATA_W 32 +#define RFC_ULLRAM_BANK11811_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11811_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11812 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11812_DATA_W 32 +#define RFC_ULLRAM_BANK11812_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11812_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11813 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11813_DATA_W 32 +#define RFC_ULLRAM_BANK11813_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11813_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11814 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11814_DATA_W 32 +#define RFC_ULLRAM_BANK11814_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11814_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11815 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11815_DATA_W 32 +#define RFC_ULLRAM_BANK11815_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11815_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11816 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11816_DATA_W 32 +#define RFC_ULLRAM_BANK11816_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11816_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11817 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11817_DATA_W 32 +#define RFC_ULLRAM_BANK11817_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11817_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11818 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11818_DATA_W 32 +#define RFC_ULLRAM_BANK11818_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11818_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11819 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11819_DATA_W 32 +#define RFC_ULLRAM_BANK11819_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11819_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11820 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11820_DATA_W 32 +#define RFC_ULLRAM_BANK11820_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11820_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11821 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11821_DATA_W 32 +#define RFC_ULLRAM_BANK11821_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11821_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11822 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11822_DATA_W 32 +#define RFC_ULLRAM_BANK11822_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11822_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11823 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11823_DATA_W 32 +#define RFC_ULLRAM_BANK11823_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11823_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11824 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11824_DATA_W 32 +#define RFC_ULLRAM_BANK11824_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11824_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11825 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11825_DATA_W 32 +#define RFC_ULLRAM_BANK11825_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11825_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11826 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11826_DATA_W 32 +#define RFC_ULLRAM_BANK11826_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11826_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11827 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11827_DATA_W 32 +#define RFC_ULLRAM_BANK11827_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11827_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11828 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11828_DATA_W 32 +#define RFC_ULLRAM_BANK11828_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11828_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11829 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11829_DATA_W 32 +#define RFC_ULLRAM_BANK11829_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11829_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11830 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11830_DATA_W 32 +#define RFC_ULLRAM_BANK11830_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11830_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11831 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11831_DATA_W 32 +#define RFC_ULLRAM_BANK11831_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11831_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11832 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11832_DATA_W 32 +#define RFC_ULLRAM_BANK11832_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11832_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11833 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11833_DATA_W 32 +#define RFC_ULLRAM_BANK11833_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11833_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11834 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11834_DATA_W 32 +#define RFC_ULLRAM_BANK11834_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11834_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11835 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11835_DATA_W 32 +#define RFC_ULLRAM_BANK11835_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11835_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11836 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11836_DATA_W 32 +#define RFC_ULLRAM_BANK11836_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11836_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11837 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11837_DATA_W 32 +#define RFC_ULLRAM_BANK11837_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11837_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11838 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11838_DATA_W 32 +#define RFC_ULLRAM_BANK11838_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11838_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11839 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11839_DATA_W 32 +#define RFC_ULLRAM_BANK11839_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11839_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11840 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11840_DATA_W 32 +#define RFC_ULLRAM_BANK11840_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11840_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11841 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11841_DATA_W 32 +#define RFC_ULLRAM_BANK11841_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11841_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11842 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11842_DATA_W 32 +#define RFC_ULLRAM_BANK11842_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11842_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11843 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11843_DATA_W 32 +#define RFC_ULLRAM_BANK11843_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11843_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11844 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11844_DATA_W 32 +#define RFC_ULLRAM_BANK11844_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11844_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11845 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11845_DATA_W 32 +#define RFC_ULLRAM_BANK11845_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11845_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11846 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11846_DATA_W 32 +#define RFC_ULLRAM_BANK11846_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11846_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11847 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11847_DATA_W 32 +#define RFC_ULLRAM_BANK11847_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11847_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11848 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11848_DATA_W 32 +#define RFC_ULLRAM_BANK11848_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11848_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11849 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11849_DATA_W 32 +#define RFC_ULLRAM_BANK11849_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11849_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11850 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11850_DATA_W 32 +#define RFC_ULLRAM_BANK11850_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11850_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11851 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11851_DATA_W 32 +#define RFC_ULLRAM_BANK11851_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11851_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11852 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11852_DATA_W 32 +#define RFC_ULLRAM_BANK11852_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11852_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11853 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11853_DATA_W 32 +#define RFC_ULLRAM_BANK11853_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11853_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11854 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11854_DATA_W 32 +#define RFC_ULLRAM_BANK11854_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11854_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11855 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11855_DATA_W 32 +#define RFC_ULLRAM_BANK11855_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11855_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11856 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11856_DATA_W 32 +#define RFC_ULLRAM_BANK11856_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11856_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11857 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11857_DATA_W 32 +#define RFC_ULLRAM_BANK11857_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11857_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11858 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11858_DATA_W 32 +#define RFC_ULLRAM_BANK11858_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11858_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11859 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11859_DATA_W 32 +#define RFC_ULLRAM_BANK11859_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11859_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11860 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11860_DATA_W 32 +#define RFC_ULLRAM_BANK11860_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11860_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11861 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11861_DATA_W 32 +#define RFC_ULLRAM_BANK11861_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11861_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11862 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11862_DATA_W 32 +#define RFC_ULLRAM_BANK11862_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11862_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11863 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11863_DATA_W 32 +#define RFC_ULLRAM_BANK11863_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11863_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11864 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11864_DATA_W 32 +#define RFC_ULLRAM_BANK11864_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11864_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11865 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11865_DATA_W 32 +#define RFC_ULLRAM_BANK11865_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11865_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11866 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11866_DATA_W 32 +#define RFC_ULLRAM_BANK11866_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11866_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11867 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11867_DATA_W 32 +#define RFC_ULLRAM_BANK11867_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11867_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11868 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11868_DATA_W 32 +#define RFC_ULLRAM_BANK11868_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11868_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11869 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11869_DATA_W 32 +#define RFC_ULLRAM_BANK11869_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11869_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11870 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11870_DATA_W 32 +#define RFC_ULLRAM_BANK11870_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11870_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11871 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11871_DATA_W 32 +#define RFC_ULLRAM_BANK11871_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11871_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11872 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11872_DATA_W 32 +#define RFC_ULLRAM_BANK11872_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11872_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11873 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11873_DATA_W 32 +#define RFC_ULLRAM_BANK11873_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11873_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11874 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11874_DATA_W 32 +#define RFC_ULLRAM_BANK11874_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11874_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11875 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11875_DATA_W 32 +#define RFC_ULLRAM_BANK11875_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11875_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11876 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11876_DATA_W 32 +#define RFC_ULLRAM_BANK11876_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11876_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11877 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11877_DATA_W 32 +#define RFC_ULLRAM_BANK11877_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11877_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11878 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11878_DATA_W 32 +#define RFC_ULLRAM_BANK11878_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11878_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11879 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11879_DATA_W 32 +#define RFC_ULLRAM_BANK11879_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11879_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11880 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11880_DATA_W 32 +#define RFC_ULLRAM_BANK11880_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11880_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11881 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11881_DATA_W 32 +#define RFC_ULLRAM_BANK11881_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11881_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11882 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11882_DATA_W 32 +#define RFC_ULLRAM_BANK11882_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11882_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11883 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11883_DATA_W 32 +#define RFC_ULLRAM_BANK11883_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11883_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11884 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11884_DATA_W 32 +#define RFC_ULLRAM_BANK11884_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11884_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11885 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11885_DATA_W 32 +#define RFC_ULLRAM_BANK11885_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11885_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11886 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11886_DATA_W 32 +#define RFC_ULLRAM_BANK11886_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11886_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11887 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11887_DATA_W 32 +#define RFC_ULLRAM_BANK11887_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11887_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11888 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11888_DATA_W 32 +#define RFC_ULLRAM_BANK11888_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11888_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11889 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11889_DATA_W 32 +#define RFC_ULLRAM_BANK11889_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11889_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11890 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11890_DATA_W 32 +#define RFC_ULLRAM_BANK11890_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11890_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11891 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11891_DATA_W 32 +#define RFC_ULLRAM_BANK11891_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11891_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11892 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11892_DATA_W 32 +#define RFC_ULLRAM_BANK11892_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11892_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11893 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11893_DATA_W 32 +#define RFC_ULLRAM_BANK11893_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11893_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11894 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11894_DATA_W 32 +#define RFC_ULLRAM_BANK11894_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11894_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11895 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11895_DATA_W 32 +#define RFC_ULLRAM_BANK11895_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11895_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11896 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11896_DATA_W 32 +#define RFC_ULLRAM_BANK11896_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11896_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11897 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11897_DATA_W 32 +#define RFC_ULLRAM_BANK11897_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11897_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11898 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11898_DATA_W 32 +#define RFC_ULLRAM_BANK11898_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11898_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11899 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11899_DATA_W 32 +#define RFC_ULLRAM_BANK11899_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11899_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11900 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11900_DATA_W 32 +#define RFC_ULLRAM_BANK11900_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11900_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11901 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11901_DATA_W 32 +#define RFC_ULLRAM_BANK11901_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11901_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11902 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11902_DATA_W 32 +#define RFC_ULLRAM_BANK11902_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11902_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11903 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11903_DATA_W 32 +#define RFC_ULLRAM_BANK11903_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11903_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11904 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11904_DATA_W 32 +#define RFC_ULLRAM_BANK11904_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11904_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11905 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11905_DATA_W 32 +#define RFC_ULLRAM_BANK11905_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11905_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11906 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11906_DATA_W 32 +#define RFC_ULLRAM_BANK11906_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11906_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11907 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11907_DATA_W 32 +#define RFC_ULLRAM_BANK11907_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11907_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11908 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11908_DATA_W 32 +#define RFC_ULLRAM_BANK11908_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11908_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11909 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11909_DATA_W 32 +#define RFC_ULLRAM_BANK11909_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11909_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11910 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11910_DATA_W 32 +#define RFC_ULLRAM_BANK11910_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11910_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11911 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11911_DATA_W 32 +#define RFC_ULLRAM_BANK11911_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11911_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11912 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11912_DATA_W 32 +#define RFC_ULLRAM_BANK11912_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11912_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11913 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11913_DATA_W 32 +#define RFC_ULLRAM_BANK11913_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11913_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11914 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11914_DATA_W 32 +#define RFC_ULLRAM_BANK11914_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11914_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11915 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11915_DATA_W 32 +#define RFC_ULLRAM_BANK11915_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11915_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11916 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11916_DATA_W 32 +#define RFC_ULLRAM_BANK11916_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11916_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11917 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11917_DATA_W 32 +#define RFC_ULLRAM_BANK11917_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11917_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11918 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11918_DATA_W 32 +#define RFC_ULLRAM_BANK11918_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11918_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11919 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11919_DATA_W 32 +#define RFC_ULLRAM_BANK11919_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11919_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11920 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11920_DATA_W 32 +#define RFC_ULLRAM_BANK11920_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11920_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11921 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11921_DATA_W 32 +#define RFC_ULLRAM_BANK11921_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11921_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11922 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11922_DATA_W 32 +#define RFC_ULLRAM_BANK11922_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11922_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11923 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11923_DATA_W 32 +#define RFC_ULLRAM_BANK11923_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11923_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11924 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11924_DATA_W 32 +#define RFC_ULLRAM_BANK11924_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11924_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11925 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11925_DATA_W 32 +#define RFC_ULLRAM_BANK11925_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11925_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11926 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11926_DATA_W 32 +#define RFC_ULLRAM_BANK11926_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11926_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11927 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11927_DATA_W 32 +#define RFC_ULLRAM_BANK11927_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11927_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11928 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11928_DATA_W 32 +#define RFC_ULLRAM_BANK11928_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11928_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11929 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11929_DATA_W 32 +#define RFC_ULLRAM_BANK11929_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11929_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11930 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11930_DATA_W 32 +#define RFC_ULLRAM_BANK11930_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11930_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11931 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11931_DATA_W 32 +#define RFC_ULLRAM_BANK11931_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11931_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11932 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11932_DATA_W 32 +#define RFC_ULLRAM_BANK11932_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11932_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11933 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11933_DATA_W 32 +#define RFC_ULLRAM_BANK11933_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11933_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11934 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11934_DATA_W 32 +#define RFC_ULLRAM_BANK11934_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11934_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11935 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11935_DATA_W 32 +#define RFC_ULLRAM_BANK11935_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11935_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11936 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11936_DATA_W 32 +#define RFC_ULLRAM_BANK11936_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11936_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11937 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11937_DATA_W 32 +#define RFC_ULLRAM_BANK11937_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11937_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11938 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11938_DATA_W 32 +#define RFC_ULLRAM_BANK11938_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11938_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11939 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11939_DATA_W 32 +#define RFC_ULLRAM_BANK11939_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11939_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11940 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11940_DATA_W 32 +#define RFC_ULLRAM_BANK11940_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11940_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11941 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11941_DATA_W 32 +#define RFC_ULLRAM_BANK11941_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11941_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11942 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11942_DATA_W 32 +#define RFC_ULLRAM_BANK11942_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11942_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11943 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11943_DATA_W 32 +#define RFC_ULLRAM_BANK11943_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11943_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11944 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11944_DATA_W 32 +#define RFC_ULLRAM_BANK11944_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11944_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11945 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11945_DATA_W 32 +#define RFC_ULLRAM_BANK11945_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11945_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11946 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11946_DATA_W 32 +#define RFC_ULLRAM_BANK11946_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11946_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11947 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11947_DATA_W 32 +#define RFC_ULLRAM_BANK11947_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11947_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11948 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11948_DATA_W 32 +#define RFC_ULLRAM_BANK11948_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11948_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11949 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11949_DATA_W 32 +#define RFC_ULLRAM_BANK11949_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11949_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11950 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11950_DATA_W 32 +#define RFC_ULLRAM_BANK11950_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11950_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11951 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11951_DATA_W 32 +#define RFC_ULLRAM_BANK11951_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11951_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11952 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11952_DATA_W 32 +#define RFC_ULLRAM_BANK11952_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11952_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11953 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11953_DATA_W 32 +#define RFC_ULLRAM_BANK11953_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11953_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11954 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11954_DATA_W 32 +#define RFC_ULLRAM_BANK11954_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11954_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11955 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11955_DATA_W 32 +#define RFC_ULLRAM_BANK11955_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11955_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11956 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11956_DATA_W 32 +#define RFC_ULLRAM_BANK11956_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11956_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11957 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11957_DATA_W 32 +#define RFC_ULLRAM_BANK11957_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11957_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11958 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11958_DATA_W 32 +#define RFC_ULLRAM_BANK11958_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11958_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11959 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11959_DATA_W 32 +#define RFC_ULLRAM_BANK11959_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11959_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11960 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11960_DATA_W 32 +#define RFC_ULLRAM_BANK11960_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11960_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11961 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11961_DATA_W 32 +#define RFC_ULLRAM_BANK11961_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11961_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11962 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11962_DATA_W 32 +#define RFC_ULLRAM_BANK11962_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11962_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11963 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11963_DATA_W 32 +#define RFC_ULLRAM_BANK11963_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11963_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11964 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11964_DATA_W 32 +#define RFC_ULLRAM_BANK11964_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11964_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11965 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11965_DATA_W 32 +#define RFC_ULLRAM_BANK11965_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11965_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11966 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11966_DATA_W 32 +#define RFC_ULLRAM_BANK11966_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11966_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11967 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11967_DATA_W 32 +#define RFC_ULLRAM_BANK11967_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11967_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11968 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11968_DATA_W 32 +#define RFC_ULLRAM_BANK11968_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11968_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11969 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11969_DATA_W 32 +#define RFC_ULLRAM_BANK11969_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11969_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11970 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11970_DATA_W 32 +#define RFC_ULLRAM_BANK11970_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11970_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11971 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11971_DATA_W 32 +#define RFC_ULLRAM_BANK11971_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11971_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11972 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11972_DATA_W 32 +#define RFC_ULLRAM_BANK11972_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11972_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11973 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11973_DATA_W 32 +#define RFC_ULLRAM_BANK11973_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11973_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11974 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11974_DATA_W 32 +#define RFC_ULLRAM_BANK11974_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11974_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11975 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11975_DATA_W 32 +#define RFC_ULLRAM_BANK11975_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11975_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11976 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11976_DATA_W 32 +#define RFC_ULLRAM_BANK11976_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11976_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11977 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11977_DATA_W 32 +#define RFC_ULLRAM_BANK11977_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11977_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11978 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11978_DATA_W 32 +#define RFC_ULLRAM_BANK11978_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11978_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11979 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11979_DATA_W 32 +#define RFC_ULLRAM_BANK11979_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11979_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11980 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11980_DATA_W 32 +#define RFC_ULLRAM_BANK11980_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11980_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11981 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11981_DATA_W 32 +#define RFC_ULLRAM_BANK11981_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11981_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11982 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11982_DATA_W 32 +#define RFC_ULLRAM_BANK11982_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11982_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11983 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11983_DATA_W 32 +#define RFC_ULLRAM_BANK11983_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11983_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11984 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11984_DATA_W 32 +#define RFC_ULLRAM_BANK11984_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11984_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11985 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11985_DATA_W 32 +#define RFC_ULLRAM_BANK11985_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11985_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11986 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11986_DATA_W 32 +#define RFC_ULLRAM_BANK11986_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11986_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11987 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11987_DATA_W 32 +#define RFC_ULLRAM_BANK11987_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11987_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11988 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11988_DATA_W 32 +#define RFC_ULLRAM_BANK11988_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11988_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11989 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11989_DATA_W 32 +#define RFC_ULLRAM_BANK11989_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11989_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11990 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11990_DATA_W 32 +#define RFC_ULLRAM_BANK11990_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11990_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11991 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11991_DATA_W 32 +#define RFC_ULLRAM_BANK11991_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11991_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11992 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11992_DATA_W 32 +#define RFC_ULLRAM_BANK11992_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11992_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11993 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11993_DATA_W 32 +#define RFC_ULLRAM_BANK11993_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11993_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11994 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11994_DATA_W 32 +#define RFC_ULLRAM_BANK11994_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11994_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11995 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11995_DATA_W 32 +#define RFC_ULLRAM_BANK11995_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11995_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11996 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11996_DATA_W 32 +#define RFC_ULLRAM_BANK11996_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11996_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11997 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11997_DATA_W 32 +#define RFC_ULLRAM_BANK11997_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11997_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11998 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11998_DATA_W 32 +#define RFC_ULLRAM_BANK11998_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11998_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11999 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11999_DATA_W 32 +#define RFC_ULLRAM_BANK11999_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11999_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12000 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12000_DATA_W 32 +#define RFC_ULLRAM_BANK12000_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12000_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12001 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12001_DATA_W 32 +#define RFC_ULLRAM_BANK12001_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12001_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12002 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12002_DATA_W 32 +#define RFC_ULLRAM_BANK12002_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12002_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12003 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12003_DATA_W 32 +#define RFC_ULLRAM_BANK12003_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12003_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12004 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12004_DATA_W 32 +#define RFC_ULLRAM_BANK12004_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12004_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12005 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12005_DATA_W 32 +#define RFC_ULLRAM_BANK12005_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12005_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12006 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12006_DATA_W 32 +#define RFC_ULLRAM_BANK12006_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12006_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12007 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12007_DATA_W 32 +#define RFC_ULLRAM_BANK12007_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12007_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12008 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12008_DATA_W 32 +#define RFC_ULLRAM_BANK12008_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12008_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12009 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12009_DATA_W 32 +#define RFC_ULLRAM_BANK12009_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12009_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12010 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12010_DATA_W 32 +#define RFC_ULLRAM_BANK12010_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12010_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12011 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12011_DATA_W 32 +#define RFC_ULLRAM_BANK12011_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12011_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12012 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12012_DATA_W 32 +#define RFC_ULLRAM_BANK12012_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12012_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12013 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12013_DATA_W 32 +#define RFC_ULLRAM_BANK12013_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12013_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12014 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12014_DATA_W 32 +#define RFC_ULLRAM_BANK12014_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12014_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12015 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12015_DATA_W 32 +#define RFC_ULLRAM_BANK12015_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12015_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12016 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12016_DATA_W 32 +#define RFC_ULLRAM_BANK12016_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12016_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12017 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12017_DATA_W 32 +#define RFC_ULLRAM_BANK12017_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12017_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12018 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12018_DATA_W 32 +#define RFC_ULLRAM_BANK12018_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12018_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12019 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12019_DATA_W 32 +#define RFC_ULLRAM_BANK12019_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12019_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12020 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12020_DATA_W 32 +#define RFC_ULLRAM_BANK12020_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12020_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12021 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12021_DATA_W 32 +#define RFC_ULLRAM_BANK12021_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12021_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12022 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12022_DATA_W 32 +#define RFC_ULLRAM_BANK12022_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12022_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12023 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12023_DATA_W 32 +#define RFC_ULLRAM_BANK12023_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12023_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12024 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12024_DATA_W 32 +#define RFC_ULLRAM_BANK12024_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12024_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12025 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12025_DATA_W 32 +#define RFC_ULLRAM_BANK12025_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12025_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12026 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12026_DATA_W 32 +#define RFC_ULLRAM_BANK12026_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12026_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12027 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12027_DATA_W 32 +#define RFC_ULLRAM_BANK12027_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12027_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12028 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12028_DATA_W 32 +#define RFC_ULLRAM_BANK12028_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12028_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12029 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12029_DATA_W 32 +#define RFC_ULLRAM_BANK12029_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12029_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12030 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12030_DATA_W 32 +#define RFC_ULLRAM_BANK12030_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12030_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12031 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12031_DATA_W 32 +#define RFC_ULLRAM_BANK12031_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12031_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12032 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12032_DATA_W 32 +#define RFC_ULLRAM_BANK12032_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12032_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12033 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12033_DATA_W 32 +#define RFC_ULLRAM_BANK12033_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12033_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12034 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12034_DATA_W 32 +#define RFC_ULLRAM_BANK12034_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12034_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12035 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12035_DATA_W 32 +#define RFC_ULLRAM_BANK12035_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12035_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12036 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12036_DATA_W 32 +#define RFC_ULLRAM_BANK12036_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12036_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12037 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12037_DATA_W 32 +#define RFC_ULLRAM_BANK12037_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12037_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12038 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12038_DATA_W 32 +#define RFC_ULLRAM_BANK12038_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12038_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12039 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12039_DATA_W 32 +#define RFC_ULLRAM_BANK12039_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12039_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12040 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12040_DATA_W 32 +#define RFC_ULLRAM_BANK12040_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12040_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12041 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12041_DATA_W 32 +#define RFC_ULLRAM_BANK12041_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12041_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12042 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12042_DATA_W 32 +#define RFC_ULLRAM_BANK12042_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12042_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12043 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12043_DATA_W 32 +#define RFC_ULLRAM_BANK12043_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12043_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12044 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12044_DATA_W 32 +#define RFC_ULLRAM_BANK12044_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12044_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12045 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12045_DATA_W 32 +#define RFC_ULLRAM_BANK12045_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12045_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12046 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12046_DATA_W 32 +#define RFC_ULLRAM_BANK12046_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12046_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12047 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12047_DATA_W 32 +#define RFC_ULLRAM_BANK12047_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12047_DATA_S 0 + + +#endif // __RFC_ULLRAM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_smph.h new file mode 100644 index 0000000..c111576 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_smph.h @@ -0,0 +1,1455 @@ +/****************************************************************************** +* Filename: hw_smph_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SMPH_H__ +#define __HW_SMPH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SMPH component +// +//***************************************************************************** +// MCU SEMAPHORE 0 +#define SMPH_O_SMPH0 0x00000000 + +// MCU SEMAPHORE 1 +#define SMPH_O_SMPH1 0x00000004 + +// MCU SEMAPHORE 2 +#define SMPH_O_SMPH2 0x00000008 + +// MCU SEMAPHORE 3 +#define SMPH_O_SMPH3 0x0000000C + +// MCU SEMAPHORE 4 +#define SMPH_O_SMPH4 0x00000010 + +// MCU SEMAPHORE 5 +#define SMPH_O_SMPH5 0x00000014 + +// MCU SEMAPHORE 6 +#define SMPH_O_SMPH6 0x00000018 + +// MCU SEMAPHORE 7 +#define SMPH_O_SMPH7 0x0000001C + +// MCU SEMAPHORE 8 +#define SMPH_O_SMPH8 0x00000020 + +// MCU SEMAPHORE 9 +#define SMPH_O_SMPH9 0x00000024 + +// MCU SEMAPHORE 10 +#define SMPH_O_SMPH10 0x00000028 + +// MCU SEMAPHORE 11 +#define SMPH_O_SMPH11 0x0000002C + +// MCU SEMAPHORE 12 +#define SMPH_O_SMPH12 0x00000030 + +// MCU SEMAPHORE 13 +#define SMPH_O_SMPH13 0x00000034 + +// MCU SEMAPHORE 14 +#define SMPH_O_SMPH14 0x00000038 + +// MCU SEMAPHORE 15 +#define SMPH_O_SMPH15 0x0000003C + +// MCU SEMAPHORE 16 +#define SMPH_O_SMPH16 0x00000040 + +// MCU SEMAPHORE 17 +#define SMPH_O_SMPH17 0x00000044 + +// MCU SEMAPHORE 18 +#define SMPH_O_SMPH18 0x00000048 + +// MCU SEMAPHORE 19 +#define SMPH_O_SMPH19 0x0000004C + +// MCU SEMAPHORE 20 +#define SMPH_O_SMPH20 0x00000050 + +// MCU SEMAPHORE 21 +#define SMPH_O_SMPH21 0x00000054 + +// MCU SEMAPHORE 22 +#define SMPH_O_SMPH22 0x00000058 + +// MCU SEMAPHORE 23 +#define SMPH_O_SMPH23 0x0000005C + +// MCU SEMAPHORE 24 +#define SMPH_O_SMPH24 0x00000060 + +// MCU SEMAPHORE 25 +#define SMPH_O_SMPH25 0x00000064 + +// MCU SEMAPHORE 26 +#define SMPH_O_SMPH26 0x00000068 + +// MCU SEMAPHORE 27 +#define SMPH_O_SMPH27 0x0000006C + +// MCU SEMAPHORE 28 +#define SMPH_O_SMPH28 0x00000070 + +// MCU SEMAPHORE 29 +#define SMPH_O_SMPH29 0x00000074 + +// MCU SEMAPHORE 30 +#define SMPH_O_SMPH30 0x00000078 + +// MCU SEMAPHORE 31 +#define SMPH_O_SMPH31 0x0000007C + +// MCU SEMAPHORE 0 ALIAS +#define SMPH_O_PEEK0 0x00000800 + +// MCU SEMAPHORE 1 ALIAS +#define SMPH_O_PEEK1 0x00000804 + +// MCU SEMAPHORE 2 ALIAS +#define SMPH_O_PEEK2 0x00000808 + +// MCU SEMAPHORE 3 ALIAS +#define SMPH_O_PEEK3 0x0000080C + +// MCU SEMAPHORE 4 ALIAS +#define SMPH_O_PEEK4 0x00000810 + +// MCU SEMAPHORE 5 ALIAS +#define SMPH_O_PEEK5 0x00000814 + +// MCU SEMAPHORE 6 ALIAS +#define SMPH_O_PEEK6 0x00000818 + +// MCU SEMAPHORE 7 ALIAS +#define SMPH_O_PEEK7 0x0000081C + +// MCU SEMAPHORE 8 ALIAS +#define SMPH_O_PEEK8 0x00000820 + +// MCU SEMAPHORE 9 ALIAS +#define SMPH_O_PEEK9 0x00000824 + +// MCU SEMAPHORE 10 ALIAS +#define SMPH_O_PEEK10 0x00000828 + +// MCU SEMAPHORE 11 ALIAS +#define SMPH_O_PEEK11 0x0000082C + +// MCU SEMAPHORE 12 ALIAS +#define SMPH_O_PEEK12 0x00000830 + +// MCU SEMAPHORE 13 ALIAS +#define SMPH_O_PEEK13 0x00000834 + +// MCU SEMAPHORE 14 ALIAS +#define SMPH_O_PEEK14 0x00000838 + +// MCU SEMAPHORE 15 ALIAS +#define SMPH_O_PEEK15 0x0000083C + +// MCU SEMAPHORE 16 ALIAS +#define SMPH_O_PEEK16 0x00000840 + +// MCU SEMAPHORE 17 ALIAS +#define SMPH_O_PEEK17 0x00000844 + +// MCU SEMAPHORE 18 ALIAS +#define SMPH_O_PEEK18 0x00000848 + +// MCU SEMAPHORE 19 ALIAS +#define SMPH_O_PEEK19 0x0000084C + +// MCU SEMAPHORE 20 ALIAS +#define SMPH_O_PEEK20 0x00000850 + +// MCU SEMAPHORE 21 ALIAS +#define SMPH_O_PEEK21 0x00000854 + +// MCU SEMAPHORE 22 ALIAS +#define SMPH_O_PEEK22 0x00000858 + +// MCU SEMAPHORE 23 ALIAS +#define SMPH_O_PEEK23 0x0000085C + +// MCU SEMAPHORE 24 ALIAS +#define SMPH_O_PEEK24 0x00000860 + +// MCU SEMAPHORE 25 ALIAS +#define SMPH_O_PEEK25 0x00000864 + +// MCU SEMAPHORE 26 ALIAS +#define SMPH_O_PEEK26 0x00000868 + +// MCU SEMAPHORE 27 ALIAS +#define SMPH_O_PEEK27 0x0000086C + +// MCU SEMAPHORE 28 ALIAS +#define SMPH_O_PEEK28 0x00000870 + +// MCU SEMAPHORE 29 ALIAS +#define SMPH_O_PEEK29 0x00000874 + +// MCU SEMAPHORE 30 ALIAS +#define SMPH_O_PEEK30 0x00000878 + +// MCU SEMAPHORE 31 ALIAS +#define SMPH_O_PEEK31 0x0000087C + +//***************************************************************************** +// +// Register: SMPH_O_SMPH0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH0_STAT 0x00000001 +#define SMPH_SMPH0_STAT_BITN 0 +#define SMPH_SMPH0_STAT_M 0x00000001 +#define SMPH_SMPH0_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH1_STAT 0x00000001 +#define SMPH_SMPH1_STAT_BITN 0 +#define SMPH_SMPH1_STAT_M 0x00000001 +#define SMPH_SMPH1_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH2_STAT 0x00000001 +#define SMPH_SMPH2_STAT_BITN 0 +#define SMPH_SMPH2_STAT_M 0x00000001 +#define SMPH_SMPH2_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH3_STAT 0x00000001 +#define SMPH_SMPH3_STAT_BITN 0 +#define SMPH_SMPH3_STAT_M 0x00000001 +#define SMPH_SMPH3_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH4_STAT 0x00000001 +#define SMPH_SMPH4_STAT_BITN 0 +#define SMPH_SMPH4_STAT_M 0x00000001 +#define SMPH_SMPH4_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH5_STAT 0x00000001 +#define SMPH_SMPH5_STAT_BITN 0 +#define SMPH_SMPH5_STAT_M 0x00000001 +#define SMPH_SMPH5_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH6_STAT 0x00000001 +#define SMPH_SMPH6_STAT_BITN 0 +#define SMPH_SMPH6_STAT_M 0x00000001 +#define SMPH_SMPH6_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH7_STAT 0x00000001 +#define SMPH_SMPH7_STAT_BITN 0 +#define SMPH_SMPH7_STAT_M 0x00000001 +#define SMPH_SMPH7_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH8 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH8_STAT 0x00000001 +#define SMPH_SMPH8_STAT_BITN 0 +#define SMPH_SMPH8_STAT_M 0x00000001 +#define SMPH_SMPH8_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH9 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH9_STAT 0x00000001 +#define SMPH_SMPH9_STAT_BITN 0 +#define SMPH_SMPH9_STAT_M 0x00000001 +#define SMPH_SMPH9_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH10 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH10_STAT 0x00000001 +#define SMPH_SMPH10_STAT_BITN 0 +#define SMPH_SMPH10_STAT_M 0x00000001 +#define SMPH_SMPH10_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH11 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH11_STAT 0x00000001 +#define SMPH_SMPH11_STAT_BITN 0 +#define SMPH_SMPH11_STAT_M 0x00000001 +#define SMPH_SMPH11_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH12 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH12_STAT 0x00000001 +#define SMPH_SMPH12_STAT_BITN 0 +#define SMPH_SMPH12_STAT_M 0x00000001 +#define SMPH_SMPH12_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH13 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH13_STAT 0x00000001 +#define SMPH_SMPH13_STAT_BITN 0 +#define SMPH_SMPH13_STAT_M 0x00000001 +#define SMPH_SMPH13_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH14 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH14_STAT 0x00000001 +#define SMPH_SMPH14_STAT_BITN 0 +#define SMPH_SMPH14_STAT_M 0x00000001 +#define SMPH_SMPH14_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH15 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH15_STAT 0x00000001 +#define SMPH_SMPH15_STAT_BITN 0 +#define SMPH_SMPH15_STAT_M 0x00000001 +#define SMPH_SMPH15_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH16 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH16_STAT 0x00000001 +#define SMPH_SMPH16_STAT_BITN 0 +#define SMPH_SMPH16_STAT_M 0x00000001 +#define SMPH_SMPH16_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH17 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH17_STAT 0x00000001 +#define SMPH_SMPH17_STAT_BITN 0 +#define SMPH_SMPH17_STAT_M 0x00000001 +#define SMPH_SMPH17_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH18 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH18_STAT 0x00000001 +#define SMPH_SMPH18_STAT_BITN 0 +#define SMPH_SMPH18_STAT_M 0x00000001 +#define SMPH_SMPH18_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH19 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH19_STAT 0x00000001 +#define SMPH_SMPH19_STAT_BITN 0 +#define SMPH_SMPH19_STAT_M 0x00000001 +#define SMPH_SMPH19_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH20 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH20_STAT 0x00000001 +#define SMPH_SMPH20_STAT_BITN 0 +#define SMPH_SMPH20_STAT_M 0x00000001 +#define SMPH_SMPH20_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH21 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH21_STAT 0x00000001 +#define SMPH_SMPH21_STAT_BITN 0 +#define SMPH_SMPH21_STAT_M 0x00000001 +#define SMPH_SMPH21_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH22 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH22_STAT 0x00000001 +#define SMPH_SMPH22_STAT_BITN 0 +#define SMPH_SMPH22_STAT_M 0x00000001 +#define SMPH_SMPH22_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH23 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH23_STAT 0x00000001 +#define SMPH_SMPH23_STAT_BITN 0 +#define SMPH_SMPH23_STAT_M 0x00000001 +#define SMPH_SMPH23_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH24 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH24_STAT 0x00000001 +#define SMPH_SMPH24_STAT_BITN 0 +#define SMPH_SMPH24_STAT_M 0x00000001 +#define SMPH_SMPH24_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH25 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH25_STAT 0x00000001 +#define SMPH_SMPH25_STAT_BITN 0 +#define SMPH_SMPH25_STAT_M 0x00000001 +#define SMPH_SMPH25_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH26 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH26_STAT 0x00000001 +#define SMPH_SMPH26_STAT_BITN 0 +#define SMPH_SMPH26_STAT_M 0x00000001 +#define SMPH_SMPH26_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH27 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH27_STAT 0x00000001 +#define SMPH_SMPH27_STAT_BITN 0 +#define SMPH_SMPH27_STAT_M 0x00000001 +#define SMPH_SMPH27_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH28 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH28_STAT 0x00000001 +#define SMPH_SMPH28_STAT_BITN 0 +#define SMPH_SMPH28_STAT_M 0x00000001 +#define SMPH_SMPH28_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH29 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH29_STAT 0x00000001 +#define SMPH_SMPH29_STAT_BITN 0 +#define SMPH_SMPH29_STAT_M 0x00000001 +#define SMPH_SMPH29_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH30 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH30_STAT 0x00000001 +#define SMPH_SMPH30_STAT_BITN 0 +#define SMPH_SMPH30_STAT_M 0x00000001 +#define SMPH_SMPH30_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH31 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH31_STAT 0x00000001 +#define SMPH_SMPH31_STAT_BITN 0 +#define SMPH_SMPH31_STAT_M 0x00000001 +#define SMPH_SMPH31_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK0_STAT 0x00000001 +#define SMPH_PEEK0_STAT_BITN 0 +#define SMPH_PEEK0_STAT_M 0x00000001 +#define SMPH_PEEK0_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK1_STAT 0x00000001 +#define SMPH_PEEK1_STAT_BITN 0 +#define SMPH_PEEK1_STAT_M 0x00000001 +#define SMPH_PEEK1_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK2_STAT 0x00000001 +#define SMPH_PEEK2_STAT_BITN 0 +#define SMPH_PEEK2_STAT_M 0x00000001 +#define SMPH_PEEK2_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK3_STAT 0x00000001 +#define SMPH_PEEK3_STAT_BITN 0 +#define SMPH_PEEK3_STAT_M 0x00000001 +#define SMPH_PEEK3_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK4_STAT 0x00000001 +#define SMPH_PEEK4_STAT_BITN 0 +#define SMPH_PEEK4_STAT_M 0x00000001 +#define SMPH_PEEK4_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK5_STAT 0x00000001 +#define SMPH_PEEK5_STAT_BITN 0 +#define SMPH_PEEK5_STAT_M 0x00000001 +#define SMPH_PEEK5_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK6_STAT 0x00000001 +#define SMPH_PEEK6_STAT_BITN 0 +#define SMPH_PEEK6_STAT_M 0x00000001 +#define SMPH_PEEK6_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK7_STAT 0x00000001 +#define SMPH_PEEK7_STAT_BITN 0 +#define SMPH_PEEK7_STAT_M 0x00000001 +#define SMPH_PEEK7_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK8 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK8_STAT 0x00000001 +#define SMPH_PEEK8_STAT_BITN 0 +#define SMPH_PEEK8_STAT_M 0x00000001 +#define SMPH_PEEK8_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK9 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK9_STAT 0x00000001 +#define SMPH_PEEK9_STAT_BITN 0 +#define SMPH_PEEK9_STAT_M 0x00000001 +#define SMPH_PEEK9_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK10 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK10_STAT 0x00000001 +#define SMPH_PEEK10_STAT_BITN 0 +#define SMPH_PEEK10_STAT_M 0x00000001 +#define SMPH_PEEK10_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK11 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK11_STAT 0x00000001 +#define SMPH_PEEK11_STAT_BITN 0 +#define SMPH_PEEK11_STAT_M 0x00000001 +#define SMPH_PEEK11_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK12 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK12_STAT 0x00000001 +#define SMPH_PEEK12_STAT_BITN 0 +#define SMPH_PEEK12_STAT_M 0x00000001 +#define SMPH_PEEK12_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK13 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK13_STAT 0x00000001 +#define SMPH_PEEK13_STAT_BITN 0 +#define SMPH_PEEK13_STAT_M 0x00000001 +#define SMPH_PEEK13_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK14 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK14_STAT 0x00000001 +#define SMPH_PEEK14_STAT_BITN 0 +#define SMPH_PEEK14_STAT_M 0x00000001 +#define SMPH_PEEK14_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK15 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK15_STAT 0x00000001 +#define SMPH_PEEK15_STAT_BITN 0 +#define SMPH_PEEK15_STAT_M 0x00000001 +#define SMPH_PEEK15_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK16 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK16_STAT 0x00000001 +#define SMPH_PEEK16_STAT_BITN 0 +#define SMPH_PEEK16_STAT_M 0x00000001 +#define SMPH_PEEK16_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK17 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK17_STAT 0x00000001 +#define SMPH_PEEK17_STAT_BITN 0 +#define SMPH_PEEK17_STAT_M 0x00000001 +#define SMPH_PEEK17_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK18 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK18_STAT 0x00000001 +#define SMPH_PEEK18_STAT_BITN 0 +#define SMPH_PEEK18_STAT_M 0x00000001 +#define SMPH_PEEK18_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK19 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK19_STAT 0x00000001 +#define SMPH_PEEK19_STAT_BITN 0 +#define SMPH_PEEK19_STAT_M 0x00000001 +#define SMPH_PEEK19_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK20 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK20_STAT 0x00000001 +#define SMPH_PEEK20_STAT_BITN 0 +#define SMPH_PEEK20_STAT_M 0x00000001 +#define SMPH_PEEK20_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK21 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK21_STAT 0x00000001 +#define SMPH_PEEK21_STAT_BITN 0 +#define SMPH_PEEK21_STAT_M 0x00000001 +#define SMPH_PEEK21_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK22 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK22_STAT 0x00000001 +#define SMPH_PEEK22_STAT_BITN 0 +#define SMPH_PEEK22_STAT_M 0x00000001 +#define SMPH_PEEK22_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK23 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK23_STAT 0x00000001 +#define SMPH_PEEK23_STAT_BITN 0 +#define SMPH_PEEK23_STAT_M 0x00000001 +#define SMPH_PEEK23_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK24 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK24_STAT 0x00000001 +#define SMPH_PEEK24_STAT_BITN 0 +#define SMPH_PEEK24_STAT_M 0x00000001 +#define SMPH_PEEK24_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK25 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK25_STAT 0x00000001 +#define SMPH_PEEK25_STAT_BITN 0 +#define SMPH_PEEK25_STAT_M 0x00000001 +#define SMPH_PEEK25_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK26 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK26_STAT 0x00000001 +#define SMPH_PEEK26_STAT_BITN 0 +#define SMPH_PEEK26_STAT_M 0x00000001 +#define SMPH_PEEK26_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK27 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK27_STAT 0x00000001 +#define SMPH_PEEK27_STAT_BITN 0 +#define SMPH_PEEK27_STAT_M 0x00000001 +#define SMPH_PEEK27_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK28 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK28_STAT 0x00000001 +#define SMPH_PEEK28_STAT_BITN 0 +#define SMPH_PEEK28_STAT_M 0x00000001 +#define SMPH_PEEK28_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK29 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK29_STAT 0x00000001 +#define SMPH_PEEK29_STAT_BITN 0 +#define SMPH_PEEK29_STAT_M 0x00000001 +#define SMPH_PEEK29_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK30 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK30_STAT 0x00000001 +#define SMPH_PEEK30_STAT_BITN 0 +#define SMPH_PEEK30_STAT_M 0x00000001 +#define SMPH_PEEK30_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK31 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK31_STAT 0x00000001 +#define SMPH_PEEK31_STAT_BITN 0 +#define SMPH_PEEK31_STAT_M 0x00000001 +#define SMPH_PEEK31_STAT_S 0 + + +#endif // __SMPH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h new file mode 100644 index 0000000..e16dd83 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h @@ -0,0 +1,150 @@ +/****************************************************************************** +* Filename: hw_sram_mmr_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SRAM_MMR_H__ +#define __HW_SRAM_MMR_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SRAM_MMR component +// +//***************************************************************************** +// Parity Error Control +#define SRAM_MMR_O_PER_CTL 0x00000000 + +// Parity Error Check +#define SRAM_MMR_O_PER_CHK 0x00000004 + +// Parity Error Debug +#define SRAM_MMR_O_PER_DBG 0x00000008 + +// Memory Control +#define SRAM_MMR_O_MEM_CTL 0x0000000C + +//***************************************************************************** +// +// Register: SRAM_MMR_O_PER_CTL +// +//***************************************************************************** +// Field: [8] PER_DISABLE +// +// Parity Status Disable +// +// 0: A parity error will update PER_CHK.PER_ADDR field +// 1: Parity error does not update PER_CHK.PER_ADDR field +#define SRAM_MMR_PER_CTL_PER_DISABLE 0x00000100 +#define SRAM_MMR_PER_CTL_PER_DISABLE_BITN 8 +#define SRAM_MMR_PER_CTL_PER_DISABLE_M 0x00000100 +#define SRAM_MMR_PER_CTL_PER_DISABLE_S 8 + +// Field: [0] PER_DEBUG_ENABLE +// +// Parity Error Debug Enable +// +// 0: Normal operation +// 1: An address offset can be written to PER_DBG.PER_DEBUG_ADDR and parity +// errors will be generated on reads from within this offset +#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE 0x00000001 +#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_BITN 0 +#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_M 0x00000001 +#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_S 0 + +//***************************************************************************** +// +// Register: SRAM_MMR_O_PER_CHK +// +//***************************************************************************** +// Field: [23:0] PER_ADDR +// +// Parity Error Address Offset +// Returns the last address offset which resulted in a parity error during an +// SRAM read. The address offset returned is always the word-aligned address +// that contains the location with the parity error. For parity faults on non +// word-aligned accesses, CPU_SCS:BFAR.ADDRESS will hold the address of the +// location that resulted in parity error. +#define SRAM_MMR_PER_CHK_PER_ADDR_W 24 +#define SRAM_MMR_PER_CHK_PER_ADDR_M 0x00FFFFFF +#define SRAM_MMR_PER_CHK_PER_ADDR_S 0 + +//***************************************************************************** +// +// Register: SRAM_MMR_O_PER_DBG +// +//***************************************************************************** +// Field: [23:0] PER_DEBUG_ADDR +// +// Debug Parity Error Address Offset +// When PER_CTL.PER_DEBUG is 1, this field is used to set a parity debug +// address offset. The address offset must be a word-aligned address. Writes +// within this address offset will force incorrect parity bits to be stored +// together with the data written. The following reads within this same address +// offset will thus result in parity errors to be generated. +#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_W 24 +#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_M 0x00FFFFFF +#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_S 0 + +//***************************************************************************** +// +// Register: SRAM_MMR_O_MEM_CTL +// +//***************************************************************************** +// Field: [1] MEM_BUSY +// +// Memory Busy status +// +// 0: Memory accepts transfers +// 1: Memory controller is busy during initialization. Read and write transfers +// are not performed. +#define SRAM_MMR_MEM_CTL_MEM_BUSY 0x00000002 +#define SRAM_MMR_MEM_CTL_MEM_BUSY_BITN 1 +#define SRAM_MMR_MEM_CTL_MEM_BUSY_M 0x00000002 +#define SRAM_MMR_MEM_CTL_MEM_BUSY_S 1 + +// Field: [0] MEM_CLR_EN +// +// Memory Contents Initialization enable +// +// Writing 1 to MEM_CLR_EN will start memory initialization. The contents of +// all byte locations will be initialized to 0x00. MEM_BUSY will be 1 until +// memory initialization has completed. +#define SRAM_MMR_MEM_CTL_MEM_CLR_EN 0x00000001 +#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_BITN 0 +#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_M 0x00000001 +#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_S 0 + + +#endif // __SRAM_MMR__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h new file mode 100644 index 0000000..e8acb3d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h @@ -0,0 +1,544 @@ +/****************************************************************************** +* Filename: hw_ssi_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SSI component +// +//***************************************************************************** +// Control 0 +#define SSI_O_CR0 0x00000000 + +// Control 1 +#define SSI_O_CR1 0x00000004 + +// Data +#define SSI_O_DR 0x00000008 + +// Status +#define SSI_O_SR 0x0000000C + +// Clock Prescale +#define SSI_O_CPSR 0x00000010 + +// Interrupt Mask Set and Clear +#define SSI_O_IMSC 0x00000014 + +// Raw Interrupt Status +#define SSI_O_RIS 0x00000018 + +// Masked Interrupt Status +#define SSI_O_MIS 0x0000001C + +// Interrupt Clear +#define SSI_O_ICR 0x00000020 + +// DMA Control +#define SSI_O_DMACR 0x00000024 + +//***************************************************************************** +// +// Register: SSI_O_CR0 +// +//***************************************************************************** +// Field: [15:8] SCR +// +// Serial clock rate: +// This is used to generate the transmit and receive bit rate of the SSI. The +// bit rate is +// (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). +// SCR is a value from 0-255. +#define SSI_CR0_SCR_W 8 +#define SSI_CR0_SCR_M 0x0000FF00 +#define SSI_CR0_SCR_S 8 + +// Field: [7] SPH +// +// CLKOUT phase (Motorola SPI frame format only) +// This bit selects the clock edge that captures data and enables it to change +// state. It +// has the most impact on the first bit transmitted by either permitting or not +// permitting a clock transition before the first data capture edge. +// ENUMs: +// 2ND_CLK_EDGE Data is captured on the second clock edge +// transition. +// 1ST_CLK_EDGE Data is captured on the first clock edge +// transition. +#define SSI_CR0_SPH 0x00000080 +#define SSI_CR0_SPH_BITN 7 +#define SSI_CR0_SPH_M 0x00000080 +#define SSI_CR0_SPH_S 7 +#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 +#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 + +// Field: [6] SPO +// +// CLKOUT polarity (Motorola SPI frame format only) +// ENUMs: +// HIGH SSI produces a steady state HIGH value on the +// CLKOUT pin when data is not being transferred. +// LOW SSI produces a steady state LOW value on the +// CLKOUT pin when data is +// not being transferred. +#define SSI_CR0_SPO 0x00000040 +#define SSI_CR0_SPO_BITN 6 +#define SSI_CR0_SPO_M 0x00000040 +#define SSI_CR0_SPO_S 6 +#define SSI_CR0_SPO_HIGH 0x00000040 +#define SSI_CR0_SPO_LOW 0x00000000 + +// Field: [5:4] FRF +// +// Frame format. +// The supported frame formats are Motorola SPI, TI synchronous serial and +// National Microwire. +// Value 0'b11 is reserved and shall not be used. +// ENUMs: +// NATIONAL_MICROWIRE National Microwire frame format +// TI_SYNC_SERIAL TI synchronous serial frame format +// MOTOROLA_SPI Motorola SPI frame format +#define SSI_CR0_FRF_W 2 +#define SSI_CR0_FRF_M 0x00000030 +#define SSI_CR0_FRF_S 4 +#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 +#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 +#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 + +// Field: [3:0] DSS +// +// Data Size Select. +// Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used. +// ENUMs: +// 16_BIT 16-bit data +// 15_BIT 15-bit data +// 14_BIT 14-bit data +// 13_BIT 13-bit data +// 12_BIT 12-bit data +// 11_BIT 11-bit data +// 10_BIT 10-bit data +// 9_BIT 9-bit data +// 8_BIT 8-bit data +// 7_BIT 7-bit data +// 6_BIT 6-bit data +// 5_BIT 5-bit data +// 4_BIT 4-bit data +#define SSI_CR0_DSS_W 4 +#define SSI_CR0_DSS_M 0x0000000F +#define SSI_CR0_DSS_S 0 +#define SSI_CR0_DSS_16_BIT 0x0000000F +#define SSI_CR0_DSS_15_BIT 0x0000000E +#define SSI_CR0_DSS_14_BIT 0x0000000D +#define SSI_CR0_DSS_13_BIT 0x0000000C +#define SSI_CR0_DSS_12_BIT 0x0000000B +#define SSI_CR0_DSS_11_BIT 0x0000000A +#define SSI_CR0_DSS_10_BIT 0x00000009 +#define SSI_CR0_DSS_9_BIT 0x00000008 +#define SSI_CR0_DSS_8_BIT 0x00000007 +#define SSI_CR0_DSS_7_BIT 0x00000006 +#define SSI_CR0_DSS_6_BIT 0x00000005 +#define SSI_CR0_DSS_5_BIT 0x00000004 +#define SSI_CR0_DSS_4_BIT 0x00000003 + +//***************************************************************************** +// +// Register: SSI_O_CR1 +// +//***************************************************************************** +// Field: [3] SOD +// +// Slave-mode output disabled +// This bit is relevant only in the slave mode, MS=1. In multiple-slave +// systems, it is possible for an SSI master to broadcast a message to all +// slaves in the system while ensuring that only one slave drives data onto its +// serial output line. In such systems the RXD lines from multiple slaves could +// be tied together. To operate in such systems, this bitfield can be set if +// the SSI slave is not supposed to drive the TXD line: +// +// 0: SSI can drive the TXD output in slave mode. +// 1: SSI cannot drive the TXD output in slave mode. +#define SSI_CR1_SOD 0x00000008 +#define SSI_CR1_SOD_BITN 3 +#define SSI_CR1_SOD_M 0x00000008 +#define SSI_CR1_SOD_S 3 + +// Field: [2] MS +// +// Master or slave mode select. This bit can be modified only when SSI is +// disabled, SSE=0. +// ENUMs: +// SLAVE Device configured as slave +// MASTER Device configured as master +#define SSI_CR1_MS 0x00000004 +#define SSI_CR1_MS_BITN 2 +#define SSI_CR1_MS_M 0x00000004 +#define SSI_CR1_MS_S 2 +#define SSI_CR1_MS_SLAVE 0x00000004 +#define SSI_CR1_MS_MASTER 0x00000000 + +// Field: [1] SSE +// +// Synchronous serial interface enable. +// ENUMs: +// SSI_ENABLED Operation enabled +// SSI_DISABLED Operation disabled +#define SSI_CR1_SSE 0x00000002 +#define SSI_CR1_SSE_BITN 1 +#define SSI_CR1_SSE_M 0x00000002 +#define SSI_CR1_SSE_S 1 +#define SSI_CR1_SSE_SSI_ENABLED 0x00000002 +#define SSI_CR1_SSE_SSI_DISABLED 0x00000000 + +// Field: [0] LBM +// +// Loop back mode: +// +// 0: Normal serial port operation enabled. +// 1: Output of transmit serial shifter is connected to input of receive serial +// shifter internally. +#define SSI_CR1_LBM 0x00000001 +#define SSI_CR1_LBM_BITN 0 +#define SSI_CR1_LBM_M 0x00000001 +#define SSI_CR1_LBM_S 0 + +//***************************************************************************** +// +// Register: SSI_O_DR +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Transmit/receive data +// The values read from this field or written to this field must be +// right-justified when SSI is programmed for a data size that is less than 16 +// bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit +// logic. The receive logic automatically right-justifies. +#define SSI_DR_DATA_W 16 +#define SSI_DR_DATA_M 0x0000FFFF +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// Register: SSI_O_SR +// +//***************************************************************************** +// Field: [4] BSY +// +// Serial interface busy: +// +// 0: SSI is idle +// 1: SSI is currently transmitting and/or receiving a frame or the transmit +// FIFO is not empty. +#define SSI_SR_BSY 0x00000010 +#define SSI_SR_BSY_BITN 4 +#define SSI_SR_BSY_M 0x00000010 +#define SSI_SR_BSY_S 4 + +// Field: [3] RFF +// +// Receive FIFO full: +// +// 0: Receive FIFO is not full. +// 1: Receive FIFO is full. +#define SSI_SR_RFF 0x00000008 +#define SSI_SR_RFF_BITN 3 +#define SSI_SR_RFF_M 0x00000008 +#define SSI_SR_RFF_S 3 + +// Field: [2] RNE +// +// Receive FIFO not empty +// +// 0: Receive FIFO is empty. +// 1: Receive FIFO is not empty. +#define SSI_SR_RNE 0x00000004 +#define SSI_SR_RNE_BITN 2 +#define SSI_SR_RNE_M 0x00000004 +#define SSI_SR_RNE_S 2 + +// Field: [1] TNF +// +// Transmit FIFO not full: +// +// 0: Transmit FIFO is full. +// 1: Transmit FIFO is not full. +#define SSI_SR_TNF 0x00000002 +#define SSI_SR_TNF_BITN 1 +#define SSI_SR_TNF_M 0x00000002 +#define SSI_SR_TNF_S 1 + +// Field: [0] TFE +// +// Transmit FIFO empty: +// +// 0: Transmit FIFO is not empty. +// 1: Transmit FIFO is empty. +#define SSI_SR_TFE 0x00000001 +#define SSI_SR_TFE_BITN 0 +#define SSI_SR_TFE_M 0x00000001 +#define SSI_SR_TFE_S 0 + +//***************************************************************************** +// +// Register: SSI_O_CPSR +// +//***************************************************************************** +// Field: [7:0] CPSDVSR +// +// Clock prescale divisor: +// This field specifies the division factor by which the input system clock to +// SSI must be internally divided before further use. +// The value programmed into this field must be an even non-zero number +// (2-254). The least significant bit of the programmed number is hard-coded to +// zero. If an odd number is written to this register, data read back from +// this register has the least significant bit as zero. +#define SSI_CPSR_CPSDVSR_W 8 +#define SSI_CPSR_CPSDVSR_M 0x000000FF +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// Register: SSI_O_IMSC +// +//***************************************************************************** +// Field: [3] TXIM +// +// Transmit FIFO interrupt mask: +// A read returns the current mask for transmit FIFO interrupt. On a write of +// 1, the mask for transmit FIFO interrupt is set which means the interrupt +// state will be reflected in MIS.TXMIS. A write of 0 clears the mask which +// means MIS.TXMIS will not reflect the interrupt. +#define SSI_IMSC_TXIM 0x00000008 +#define SSI_IMSC_TXIM_BITN 3 +#define SSI_IMSC_TXIM_M 0x00000008 +#define SSI_IMSC_TXIM_S 3 + +// Field: [2] RXIM +// +// Receive FIFO interrupt mask: +// A read returns the current mask for receive FIFO interrupt. On a write of 1, +// the mask for receive FIFO interrupt is set which means the interrupt state +// will be reflected in MIS.RXMIS. A write of 0 clears the mask which means +// MIS.RXMIS will not reflect the interrupt. +#define SSI_IMSC_RXIM 0x00000004 +#define SSI_IMSC_RXIM_BITN 2 +#define SSI_IMSC_RXIM_M 0x00000004 +#define SSI_IMSC_RXIM_S 2 + +// Field: [1] RTIM +// +// Receive timeout interrupt mask: +// A read returns the current mask for receive timeout interrupt. On a write of +// 1, the mask for receive timeout interrupt is set which means the interrupt +// state will be reflected in MIS.RTMIS. A write of 0 clears the mask which +// means MIS.RTMIS will not reflect the interrupt. +#define SSI_IMSC_RTIM 0x00000002 +#define SSI_IMSC_RTIM_BITN 1 +#define SSI_IMSC_RTIM_M 0x00000002 +#define SSI_IMSC_RTIM_S 1 + +// Field: [0] RORIM +// +// Receive overrun interrupt mask: +// A read returns the current mask for receive overrun interrupt. On a write of +// 1, the mask for receive overrun interrupt is set which means the interrupt +// state will be reflected in MIS.RORMIS. A write of 0 clears the mask which +// means MIS.RORMIS will not reflect the interrupt. +#define SSI_IMSC_RORIM 0x00000001 +#define SSI_IMSC_RORIM_BITN 0 +#define SSI_IMSC_RORIM_M 0x00000001 +#define SSI_IMSC_RORIM_S 0 + +//***************************************************************************** +// +// Register: SSI_O_RIS +// +//***************************************************************************** +// Field: [3] TXRIS +// +// Raw transmit FIFO interrupt status: +// The transmit interrupt is asserted when there are four or fewer valid +// entries in the transmit FIFO. The transmit interrupt is not qualified with +// the SSI enable signal. Therefore one of the following ways can be used: +// - data can be written to the transmit FIFO prior to enabling the SSI and +// the +// interrupts. +// - SSI and interrupts can be enabled so that data can be written to the +// transmit FIFO by an interrupt service routine. +#define SSI_RIS_TXRIS 0x00000008 +#define SSI_RIS_TXRIS_BITN 3 +#define SSI_RIS_TXRIS_M 0x00000008 +#define SSI_RIS_TXRIS_S 3 + +// Field: [2] RXRIS +// +// Raw interrupt state of receive FIFO interrupt: +// The receive interrupt is asserted when there are four or more valid entries +// in the receive FIFO. +#define SSI_RIS_RXRIS 0x00000004 +#define SSI_RIS_RXRIS_BITN 2 +#define SSI_RIS_RXRIS_M 0x00000004 +#define SSI_RIS_RXRIS_S 2 + +// Field: [1] RTRIS +// +// Raw interrupt state of receive timeout interrupt: +// The receive timeout interrupt is asserted when the receive FIFO is not empty +// and SSI has remained idle for a fixed 32 bit period. This mechanism can be +// used to notify the user that data is still present in the receive FIFO and +// requires servicing. This interrupt is deasserted if the receive FIFO becomes +// empty by subsequent reads, or if new data is received on RXD. +// It can also be cleared by writing to ICR.RTIC. +#define SSI_RIS_RTRIS 0x00000002 +#define SSI_RIS_RTRIS_BITN 1 +#define SSI_RIS_RTRIS_M 0x00000002 +#define SSI_RIS_RTRIS_S 1 + +// Field: [0] RORRIS +// +// Raw interrupt state of receive overrun interrupt: +// The receive overrun interrupt is asserted when the FIFO is already full and +// an additional data frame is received, causing an overrun of the FIFO. Data +// is over-written in the +// receive shift register, but not the FIFO so the FIFO contents stay valid. +// It can also be cleared by writing to ICR.RORIC. +#define SSI_RIS_RORRIS 0x00000001 +#define SSI_RIS_RORRIS_BITN 0 +#define SSI_RIS_RORRIS_M 0x00000001 +#define SSI_RIS_RORRIS_S 0 + +//***************************************************************************** +// +// Register: SSI_O_MIS +// +//***************************************************************************** +// Field: [3] TXMIS +// +// Masked interrupt state of transmit FIFO interrupt: +// This field returns the masked interrupt state of transmit FIFO interrupt +// which is the AND product of raw interrupt state RIS.TXRIS and the mask +// setting IMSC.TXIM. +#define SSI_MIS_TXMIS 0x00000008 +#define SSI_MIS_TXMIS_BITN 3 +#define SSI_MIS_TXMIS_M 0x00000008 +#define SSI_MIS_TXMIS_S 3 + +// Field: [2] RXMIS +// +// Masked interrupt state of receive FIFO interrupt: +// This field returns the masked interrupt state of receive FIFO interrupt +// which is the AND product of raw interrupt state RIS.RXRIS and the mask +// setting IMSC.RXIM. +#define SSI_MIS_RXMIS 0x00000004 +#define SSI_MIS_RXMIS_BITN 2 +#define SSI_MIS_RXMIS_M 0x00000004 +#define SSI_MIS_RXMIS_S 2 + +// Field: [1] RTMIS +// +// Masked interrupt state of receive timeout interrupt: +// This field returns the masked interrupt state of receive timeout interrupt +// which is the AND product of raw interrupt state RIS.RTRIS and the mask +// setting IMSC.RTIM. +#define SSI_MIS_RTMIS 0x00000002 +#define SSI_MIS_RTMIS_BITN 1 +#define SSI_MIS_RTMIS_M 0x00000002 +#define SSI_MIS_RTMIS_S 1 + +// Field: [0] RORMIS +// +// Masked interrupt state of receive overrun interrupt: +// This field returns the masked interrupt state of receive overrun interrupt +// which is the AND product of raw interrupt state RIS.RORRIS and the mask +// setting IMSC.RORIM. +#define SSI_MIS_RORMIS 0x00000001 +#define SSI_MIS_RORMIS_BITN 0 +#define SSI_MIS_RORMIS_M 0x00000001 +#define SSI_MIS_RORMIS_S 0 + +//***************************************************************************** +// +// Register: SSI_O_ICR +// +//***************************************************************************** +// Field: [1] RTIC +// +// Clear the receive timeout interrupt: +// Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 +// has no effect. +#define SSI_ICR_RTIC 0x00000002 +#define SSI_ICR_RTIC_BITN 1 +#define SSI_ICR_RTIC_M 0x00000002 +#define SSI_ICR_RTIC_S 1 + +// Field: [0] RORIC +// +// Clear the receive overrun interrupt: +// Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). +// Writing 0 has no effect. +#define SSI_ICR_RORIC 0x00000001 +#define SSI_ICR_RORIC_BITN 0 +#define SSI_ICR_RORIC_M 0x00000001 +#define SSI_ICR_RORIC_S 0 + +//***************************************************************************** +// +// Register: SSI_O_DMACR +// +//***************************************************************************** +// Field: [1] TXDMAE +// +// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is +// enabled. +#define SSI_DMACR_TXDMAE 0x00000002 +#define SSI_DMACR_TXDMAE_BITN 1 +#define SSI_DMACR_TXDMAE_M 0x00000002 +#define SSI_DMACR_TXDMAE_S 1 + +// Field: [0] RXDMAE +// +// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is +// enabled. +#define SSI_DMACR_RXDMAE 0x00000001 +#define SSI_DMACR_RXDMAE_BITN 0 +#define SSI_DMACR_RXDMAE_M 0x00000001 +#define SSI_DMACR_RXDMAE_S 0 + + +#endif // __SSI__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sysctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sysctl.h new file mode 100644 index 0000000..1ddd6bb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sysctl.h @@ -0,0 +1,49 @@ +/****************************************************************************** +* Filename: hw_sysctl.h +* Revised: 2015-03-16 14:43:45 +0100 (Mon, 16 Mar 2015) +* Revision: 42989 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + + +//***************************************************************************** +// +// The following are initial defines for the MCU clock +// +//***************************************************************************** +#define GET_MCU_CLOCK 48000000 + + +#endif // __HW_SYSCTL_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_trng.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_trng.h new file mode 100644 index 0000000..6ea8bd7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_trng.h @@ -0,0 +1,609 @@ +/****************************************************************************** +* Filename: hw_trng_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_TRNG_H__ +#define __HW_TRNG_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// TRNG component +// +//***************************************************************************** +// Random Number Lower Word Readout Value +#define TRNG_O_OUT0 0x00000000 + +// Random Number Upper Word Readout Value +#define TRNG_O_OUT1 0x00000004 + +// Interrupt Status +#define TRNG_O_IRQFLAGSTAT 0x00000008 + +// Interrupt Mask +#define TRNG_O_IRQFLAGMASK 0x0000000C + +// Interrupt Flag Clear +#define TRNG_O_IRQFLAGCLR 0x00000010 + +// Control +#define TRNG_O_CTL 0x00000014 + +// Configuration 0 +#define TRNG_O_CFG0 0x00000018 + +// Alarm Control +#define TRNG_O_ALARMCNT 0x0000001C + +// FRO Enable +#define TRNG_O_FROEN 0x00000020 + +// FRO De-tune Bit +#define TRNG_O_FRODETUNE 0x00000024 + +// Alarm Event +#define TRNG_O_ALARMMASK 0x00000028 + +// Alarm Shutdown +#define TRNG_O_ALARMSTOP 0x0000002C + +// LFSR Readout Value +#define TRNG_O_LFSR0 0x00000030 + +// LFSR Readout Value +#define TRNG_O_LFSR1 0x00000034 + +// LFSR Readout Value +#define TRNG_O_LFSR2 0x00000038 + +// TRNG Engine Options Information +#define TRNG_O_HWOPT 0x00000078 + +// HW Version 0 +#define TRNG_O_HWVER0 0x0000007C + +// Interrupt Status After Masking +#define TRNG_O_IRQSTATMASK 0x00001FD8 + +// HW Version 1 +#define TRNG_O_HWVER1 0x00001FE0 + +// Interrupt Set +#define TRNG_O_IRQSET 0x00001FEC + +// SW Reset Control +#define TRNG_O_SWRESET 0x00001FF0 + +// Interrupt Status +#define TRNG_O_IRQSTAT 0x00001FF8 + +//***************************************************************************** +// +// Register: TRNG_O_OUT0 +// +//***************************************************************************** +// Field: [31:0] VALUE_31_0 +// +// LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. +#define TRNG_OUT0_VALUE_31_0_W 32 +#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF +#define TRNG_OUT0_VALUE_31_0_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_OUT1 +// +//***************************************************************************** +// Field: [31:0] VALUE_63_32 +// +// MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. +#define TRNG_OUT1_VALUE_63_32_W 32 +#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF +#define TRNG_OUT1_VALUE_63_32_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGSTAT +// +//***************************************************************************** +// Field: [31] NEED_CLOCK +// +// 1: Indicates that the TRNG is busy generating entropy or is in one of its +// test modes - clocks may not be turned off and the power supply voltage must +// be kept stable. +// 0: TRNG is idle and can be shut down +#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 + +// Field: [1] SHUTDOWN_OVF +// +// 1: The number of FROs shut down (i.e. the number of '1' bits in the +// ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR +// +// Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Data are available in OUT0 and OUT1. +// +// Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears this bit to +// '0'. +// If a new number is already available in the internal register of the TRNG, +// the number is directly clocked into the result register. In this case the +// status bit is asserted again, after one clock cycle. +#define TRNG_IRQFLAGSTAT_RDY 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_BITN 0 +#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGMASK +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this +// module. +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. +#define TRNG_IRQFLAGMASK_RDY 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_BITN 0 +#define TRNG_IRQFLAGMASK_RDY_M 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGCLR +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Clear IRQFLAGSTAT.RDY. +#define TRNG_IRQFLAGCLR_RDY 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_BITN 0 +#define TRNG_IRQFLAGCLR_RDY_M 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_CTL +// +//***************************************************************************** +// Field: [31:16] STARTUP_CYCLES +// +// This field determines the number of samples (between 2^8 and 2^24) taken to +// gather entropy from the FROs during startup. If the written value of this +// field is zero, the number of samples is 2^24, otherwise the number of +// samples equals the written value times 2^8. +// +// 0x0000: 2^24 samples +// 0x0001: 1*2^8 samples +// 0x0002: 2*2^8 samples +// 0x0003: 3*2^8 samples +// ... +// 0x8000: 32768*2^8 samples +// 0xC000: 49152*2^8 samples +// ... +// 0xFFFF: 65535*2^8 samples +// +// This field can only be modified while TRNG_EN is 0. If 1 an update will be +// ignored. +#define TRNG_CTL_STARTUP_CYCLES_W 16 +#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 +#define TRNG_CTL_STARTUP_CYCLES_S 16 + +// Field: [10] TRNG_EN +// +// 0: Forces all TRNG logic back into the idle state immediately. +// 1: Starts TRNG, gathering entropy from the FROs for the number of samples +// determined by STARTUP_CYCLES. +#define TRNG_CTL_TRNG_EN 0x00000400 +#define TRNG_CTL_TRNG_EN_BITN 10 +#define TRNG_CTL_TRNG_EN_M 0x00000400 +#define TRNG_CTL_TRNG_EN_S 10 + +// Field: [2] NO_LFSR_FB +// +// 1: Remove XNOR feedback from the main LFSR, converting it into a normal +// shift register for the XOR-ed outputs of the FROs (shifting data in on the +// LSB side). A '1' also forces the LFSR to sample continuously. +// +// This bit can only be set to '1' when TEST_MODE is also set to '1' and should +// not be used for other than test purposes +#define TRNG_CTL_NO_LFSR_FB 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_BITN 2 +#define TRNG_CTL_NO_LFSR_FB_M 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_S 2 + +// Field: [1] TEST_MODE +// +// 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2 registers (the latter +// are automatically cleared before enabling access) and keeps +// IRQFLAGSTAT.NEED_CLOCK at '1'. +// +// This bit shall not be used unless you need to change the LFSR seed prior to +// creating a new random value. All other testing is done external to register +// control. +#define TRNG_CTL_TEST_MODE 0x00000002 +#define TRNG_CTL_TEST_MODE_BITN 1 +#define TRNG_CTL_TEST_MODE_M 0x00000002 +#define TRNG_CTL_TEST_MODE_S 1 + +//***************************************************************************** +// +// Register: TRNG_O_CFG0 +// +//***************************************************************************** +// Field: [31:16] MAX_REFILL_CYCLES +// +// This field determines the maximum number of samples (between 2^8 and 2^24) +// taken to re-generate entropy from the FROs after reading out a 64 bits +// random number. If the written value of this field is zero, the number of +// samples is 2^24, otherwise the number of samples equals the written value +// times 2^8. +// +// 0x0000: 2^24 samples +// 0x0001: 1*2^8 samples +// 0x0002: 2*2^8 samples +// 0x0003: 3*2^8 samples +// ... +// 0x8000: 32768*2^8 samples +// 0xC000: 49152*2^8 samples +// ... +// 0xFFFF: 65535*2^8 samples +// +// This field can only be modified while CTL.TRNG_EN is 0. +#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 +#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 +#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 + +// Field: [11:8] SMPL_DIV +// +// This field directly controls the number of clock cycles between samples +// taken from the FROs. Default value 0 indicates that samples are taken every +// clock cycle, +// maximum value 0xF takes one sample every 16 clock cycles. +// This field must be set to a value such that the slowest FRO (even under +// worst-case +// conditions) has a cycle time less than twice the sample period. +// +// This field can only be modified while CTL.TRNG_EN is '0'. +#define TRNG_CFG0_SMPL_DIV_W 4 +#define TRNG_CFG0_SMPL_DIV_M 0x00000F00 +#define TRNG_CFG0_SMPL_DIV_S 8 + +// Field: [7:0] MIN_REFILL_CYCLES +// +// This field determines the minimum number of samples (between 2^6 and 2^14) +// taken to re-generate entropy from the FROs after reading out a 64 bits +// random number. If the value of this field is zero, the number of samples is +// fixed to the value determined by the MAX_REFILL_CYCLES field, otherwise the +// minimum number of samples equals the written value times 64 (which can be up +// to 2^14). To ensure same entropy in all generated random numbers the value 0 +// should be used. Then MAX_REFILL_CYCLES controls the minimum refill interval. +// The number of samples defined here cannot be higher than the number defined +// by the 'max_refill_cycles' field (i.e. that field takes precedence). No +// random value will be created if min refill > max refill. +// +// This field can only be modified while CTL.TRNG_EN = 0. +// +// 0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers have same entropy) +// 0x01: 1*2^6 samples +// 0x02: 2*2^6 samples +// ... +// 0xFF: 255*2^6 samples +#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 +#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF +#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMCNT +// +//***************************************************************************** +// Field: [29:24] SHUTDOWN_CNT +// +// Read-only, indicates the number of '1' bits in ALARMSTOP register. +// The maximum value equals the number of FROs. +#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 + +// Field: [20:16] SHUTDOWN_THR +// +// Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The +// interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. +#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 +#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 +#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 + +// Field: [7:0] ALARM_THR +// +// Alarm detection threshold for the repeating pattern detectors on each FRO. +// An FRO 'alarm event' is declared when a repeating pattern (of up to four +// samples length) is detected continuously for the number of samples defined +// by this field's value. Reset value 0xFF should keep the number of 'alarm +// events' to a manageable level. +#define TRNG_ALARMCNT_ALARM_THR_W 8 +#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF +#define TRNG_ALARMCNT_ALARM_THR_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_FROEN +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'. +// Default state is all '1's to enable all FROs after power-up. Note that they +// are not actually started up before the CTL.TRNG_EN bit is set to '1'. +// +// Bits are automatically forced to '0' here (and cannot be written to '1') +// while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. +#define TRNG_FROEN_FRO_MASK_W 24 +#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF +#define TRNG_FROEN_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_FRODETUNE +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run +// approximately 5% faster. The value of one of these bits may only be changed +// while the corresponding FRO is turned off (by temporarily writing a '0' in +// the corresponding +// bit of the FROEN.FRO_MASK register). +#define TRNG_FRODETUNE_FRO_MASK_W 24 +#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF +#define TRNG_FRODETUNE_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMMASK +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] +// indicates FRO 'n' experienced an 'alarm event'. +#define TRNG_ALARMMASK_FRO_MASK_W 24 +#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF +#define TRNG_ALARMMASK_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMSTOP +// +//***************************************************************************** +// Field: [23:0] FRO_FLAGS +// +// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] +// indicates FRO 'n' experienced more than one 'alarm event' in quick +// succession and has been turned off. A '1' in this field forces the +// corresponding bit in FROEN.FRO_MASK to '0'. +#define TRNG_ALARMSTOP_FRO_FLAGS_W 24 +#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF +#define TRNG_ALARMSTOP_FRO_FLAGS_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR0 +// +//***************************************************************************** +// Field: [31:0] LFSR_31_0 +// +// Bits [31:0] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR0_LFSR_31_0_W 32 +#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF +#define TRNG_LFSR0_LFSR_31_0_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR1 +// +//***************************************************************************** +// Field: [31:0] LFSR_63_32 +// +// Bits [63:32] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR1_LFSR_63_32_W 32 +#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF +#define TRNG_LFSR1_LFSR_63_32_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR2 +// +//***************************************************************************** +// Field: [16:0] LFSR_80_64 +// +// Bits [80:64] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR2_LFSR_80_64_W 17 +#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF +#define TRNG_LFSR2_LFSR_80_64_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_HWOPT +// +//***************************************************************************** +// Field: [11:6] NR_OF_FROS +// +// Number of FROs implemented in this TRNG, value 24 (decimal). +#define TRNG_HWOPT_NR_OF_FROS_W 6 +#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 +#define TRNG_HWOPT_NR_OF_FROS_S 6 + +//***************************************************************************** +// +// Register: TRNG_O_HWVER0 +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VER +// +// 4 bits binary encoding of the major hardware revision number. +#define TRNG_HWVER0_HW_MAJOR_VER_W 4 +#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 +#define TRNG_HWVER0_HW_MAJOR_VER_S 24 + +// Field: [23:20] HW_MINOR_VER +// +// 4 bits binary encoding of the minor hardware revision number. +#define TRNG_HWVER0_HW_MINOR_VER_W 4 +#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 +#define TRNG_HWVER0_HW_MINOR_VER_S 20 + +// Field: [19:16] HW_PATCH_LVL +// +// 4 bits binary encoding of the hardware patch level, initial release will +// carry value zero. +#define TRNG_HWVER0_HW_PATCH_LVL_W 4 +#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 +#define TRNG_HWVER0_HW_PATCH_LVL_S 16 + +// Field: [15:8] EIP_NUM_COMPL +// +// Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. +#define TRNG_HWVER0_EIP_NUM_COMPL_W 8 +#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 +#define TRNG_HWVER0_EIP_NUM_COMPL_S 8 + +// Field: [7:0] EIP_NUM +// +// 8 bits binary encoding of the module number. This TRNG gives 0x4B. +#define TRNG_HWVER0_EIP_NUM_W 8 +#define TRNG_HWVER0_EIP_NUM_M 0x000000FF +#define TRNG_HWVER0_EIP_NUM_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSTATMASK +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with +// IRQFLAGMASK.SHUTDOWN_OVF) +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// New random value available (result of IRQFLAGSTAT.RDY AND'ed with +// IRQFLAGMASK.RDY) +#define TRNG_IRQSTATMASK_RDY 0x00000001 +#define TRNG_IRQSTATMASK_RDY_BITN 0 +#define TRNG_IRQSTATMASK_RDY_M 0x00000001 +#define TRNG_IRQSTATMASK_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_HWVER1 +// +//***************************************************************************** +// Field: [7:0] REV +// +// The revision number of this module is Rev 2.0. +#define TRNG_HWVER1_REV_W 8 +#define TRNG_HWVER1_REV_M 0x000000FF +#define TRNG_HWVER1_REV_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSET +// +//***************************************************************************** +//***************************************************************************** +// +// Register: TRNG_O_SWRESET +// +//***************************************************************************** +// Field: [0] RESET +// +// Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 +// for reset to be completed. +#define TRNG_SWRESET_RESET 0x00000001 +#define TRNG_SWRESET_RESET_BITN 0 +#define TRNG_SWRESET_RESET_M 0x00000001 +#define TRNG_SWRESET_RESET_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSTAT +// +//***************************************************************************** +// Field: [0] STAT +// +// TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and +// IRQFLAGSTAT.RDY +#define TRNG_IRQSTAT_STAT 0x00000001 +#define TRNG_IRQSTAT_STAT_BITN 0 +#define TRNG_IRQSTAT_STAT_M 0x00000001 +#define TRNG_IRQSTAT_STAT_S 0 + + +#endif // __TRNG__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_types.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_types.h new file mode 100644 index 0000000..dfa4281 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_types.h @@ -0,0 +1,123 @@ +/****************************************************************************** +* Filename: hw_types.h +* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) +* Revision: 47152 +* +* Description: Common types and macros. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +#include +#include +#include "../inc/hw_chip_def.h" + +//***************************************************************************** +// +// Common driverlib types +// +//***************************************************************************** +typedef void (* FPTR_VOID_VOID_T) (void); +typedef void (* FPTR_VOID_UINT8_T) (uint8_t); + +//***************************************************************************** +// +// This symbol forces simple driverlib functions to be inlined in the code +// instead of using function calls. +// +//***************************************************************************** +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +//***************************************************************************** +// +// C99 types only allows bitfield defintions on certain datatypes. +// +//***************************************************************************** +typedef unsigned int __UINT32; + +//***************************************************************************** +// +// Macros for direct hardware access. +// +// If using these macros the programmer should be aware of any limitations to +// the address accessed i.e. if it supports word and/or byte access. +// +//***************************************************************************** +// Word (32 bit) access to address x +// Read example : my32BitVar = HWREG(base_addr + offset) ; +// Write example : HWREG(base_addr + offset) = my32BitVar ; +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) + +// Half word (16 bit) access to address x +// Read example : my16BitVar = HWREGH(base_addr + offset) ; +// Write example : HWREGH(base_addr + offset) = my16BitVar ; +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) + +// Byte (8 bit) access to address x +// Read example : my8BitVar = HWREGB(base_addr + offset) ; +// Write example : HWREGB(base_addr + offset) = my8BitVar ; +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) + +//***************************************************************************** +// +// Macros for hardware access to bit-band supported addresses via the bit-band region. +// +// Macros calculate the corresponding address to access in the bit-band region +// based on the actual address of the memory/register and the bit number. +// +// Do NOT use these macros to access the bit-band region directly! +// +//***************************************************************************** +// Bit-band access to address x bit number b using word access (32 bit) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +// Bit-band access to address x bit number b using half word access (16 bit) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +// Bit-band access to address x bit number b using byte access (8 bit) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + + +#endif // __HW_TYPES_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_uart.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_uart.h new file mode 100644 index 0000000..f0b1bab --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_uart.h @@ -0,0 +1,1087 @@ +/****************************************************************************** +* Filename: hw_uart_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// UART component +// +//***************************************************************************** +// Data +#define UART_O_DR 0x00000000 + +// Status +#define UART_O_RSR 0x00000004 + +// Error Clear +#define UART_O_ECR 0x00000004 + +// Flag +#define UART_O_FR 0x00000018 + +// Integer Baud-Rate Divisor +#define UART_O_IBRD 0x00000024 + +// Fractional Baud-Rate Divisor +#define UART_O_FBRD 0x00000028 + +// Line Control +#define UART_O_LCRH 0x0000002C + +// Control +#define UART_O_CTL 0x00000030 + +// Interrupt FIFO Level Select +#define UART_O_IFLS 0x00000034 + +// Interrupt Mask Set/Clear +#define UART_O_IMSC 0x00000038 + +// Raw Interrupt Status +#define UART_O_RIS 0x0000003C + +// Masked Interrupt Status +#define UART_O_MIS 0x00000040 + +// Interrupt Clear +#define UART_O_ICR 0x00000044 + +// DMA Control +#define UART_O_DMACTL 0x00000048 + +//***************************************************************************** +// +// Register: UART_O_DR +// +//***************************************************************************** +// Field: [11] OE +// +// UART Overrun Error: +// This bit is set to 1 if data is received and the receive FIFO is already +// full. The FIFO contents remain valid because no more data is written when +// the FIFO is full, , only the contents of the shift register are overwritten. +// This is cleared to 0 once there is an empty space in the FIFO and a new +// character can be written to it. +#define UART_DR_OE 0x00000800 +#define UART_DR_OE_BITN 11 +#define UART_DR_OE_M 0x00000800 +#define UART_DR_OE_S 11 + +// Field: [10] BE +// +// UART Break Error: +// This bit is set to 1 if a break condition was detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (that is., the oldest received data character since last read). When a +// break occurs, a 0 character is loaded into the FIFO. The next character is +// enabled after the receive data input (UARTRXD input pin) goes to a 1 +// (marking state), and the next valid start bit is received. +#define UART_DR_BE 0x00000400 +#define UART_DR_BE_BITN 10 +#define UART_DR_BE_M 0x00000400 +#define UART_DR_BE_S 10 + +// Field: [9] PE +// +// UART Parity Error: +// When set to 1, it indicates that the parity of the received data character +// does not match the parity that the LCRH.EPS and LCRH.SPS select. +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (that is, the oldest received data character since last read). +#define UART_DR_PE 0x00000200 +#define UART_DR_PE_BITN 9 +#define UART_DR_PE_M 0x00000200 +#define UART_DR_PE_S 9 + +// Field: [8] FE +// +// UART Framing Error: +// When set to 1, it indicates that the received character did not have a valid +// stop bit (a valid stop bit is 1). +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (that is., the oldest received data character since last read). +#define UART_DR_FE 0x00000100 +#define UART_DR_FE_BITN 8 +#define UART_DR_FE_M 0x00000100 +#define UART_DR_FE_S 8 + +// Field: [7:0] DATA +// +// Data transmitted or received: +// On writes, the transmit data character is pushed into the FIFO. +// On reads, the oldest received data character since the last read is +// returned. +#define UART_DR_DATA_W 8 +#define UART_DR_DATA_M 0x000000FF +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// Register: UART_O_RSR +// +//***************************************************************************** +// Field: [3] OE +// +// UART Overrun Error: +// This bit is set to 1 if data is received and the receive FIFO is already +// full. The FIFO contents remain valid because no more data is written when +// the FIFO is full, , only the contents of the shift register are overwritten. +// This is cleared to 0 once there is an empty space in the FIFO and a new +// character can be written to it. +#define UART_RSR_OE 0x00000008 +#define UART_RSR_OE_BITN 3 +#define UART_RSR_OE_M 0x00000008 +#define UART_RSR_OE_S 3 + +// Field: [2] BE +// +// UART Break Error: +// This bit is set to 1 if a break condition was detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +// When a break occurs, a 0 character is loaded into the FIFO. The next +// character is enabled after the receive data input (UARTRXD input pin) goes +// to a 1 (marking state), and the next valid start bit is received. +#define UART_RSR_BE 0x00000004 +#define UART_RSR_BE_BITN 2 +#define UART_RSR_BE_M 0x00000004 +#define UART_RSR_BE_S 2 + +// Field: [1] PE +// +// UART Parity Error: +// When set to 1, it indicates that the parity of the received data character +// does not match the parity that the LCRH.EPS and LCRH.SPS select. +#define UART_RSR_PE 0x00000002 +#define UART_RSR_PE_BITN 1 +#define UART_RSR_PE_M 0x00000002 +#define UART_RSR_PE_S 1 + +// Field: [0] FE +// +// UART Framing Error: +// When set to 1, it indicates that the received character did not have a valid +// stop bit (a valid stop bit is 1). +#define UART_RSR_FE 0x00000001 +#define UART_RSR_FE_BITN 0 +#define UART_RSR_FE_M 0x00000001 +#define UART_RSR_FE_S 0 + +//***************************************************************************** +// +// Register: UART_O_ECR +// +//***************************************************************************** +// Field: [3] OE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_OE 0x00000008 +#define UART_ECR_OE_BITN 3 +#define UART_ECR_OE_M 0x00000008 +#define UART_ECR_OE_S 3 + +// Field: [2] BE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_BE 0x00000004 +#define UART_ECR_BE_BITN 2 +#define UART_ECR_BE_M 0x00000004 +#define UART_ECR_BE_S 2 + +// Field: [1] PE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_PE 0x00000002 +#define UART_ECR_PE_BITN 1 +#define UART_ECR_PE_M 0x00000002 +#define UART_ECR_PE_S 1 + +// Field: [0] FE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_FE 0x00000001 +#define UART_ECR_FE_BITN 0 +#define UART_ECR_FE_M 0x00000001 +#define UART_ECR_FE_S 0 + +//***************************************************************************** +// +// Register: UART_O_FR +// +//***************************************************************************** +// Field: [7] TXFE +// +// UART Transmit FIFO Empty: +// The meaning of this bit depends on the state of LCRH.FEN . +// - If the FIFO is disabled, this bit is set when the transmit holding +// register is empty. +// - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. +// This bit does not indicate if there is data in the transmit shift register. +#define UART_FR_TXFE 0x00000080 +#define UART_FR_TXFE_BITN 7 +#define UART_FR_TXFE_M 0x00000080 +#define UART_FR_TXFE_S 7 + +// Field: [6] RXFF +// +// UART Receive FIFO Full: +// The meaning of this bit depends on the state of LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the receive holding +// register is full. +// - If the FIFO is enabled, this bit is set when the receive FIFO is full. +#define UART_FR_RXFF 0x00000040 +#define UART_FR_RXFF_BITN 6 +#define UART_FR_RXFF_M 0x00000040 +#define UART_FR_RXFF_S 6 + +// Field: [5] TXFF +// +// UART Transmit FIFO Full: +// Transmit FIFO full. The meaning of this bit depends on the state of +// LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the transmit holding +// register is full. +// - If the FIFO is enabled, this bit is set when the transmit FIFO is full. +#define UART_FR_TXFF 0x00000020 +#define UART_FR_TXFF_BITN 5 +#define UART_FR_TXFF_M 0x00000020 +#define UART_FR_TXFF_S 5 + +// Field: [4] RXFE +// +// UART Receive FIFO Empty: +// Receive FIFO empty. The meaning of this bit depends on the state of +// LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the receive holding +// register is empty. +// - If the FIFO is enabled, this bit is set when the receive FIFO is empty. +#define UART_FR_RXFE 0x00000010 +#define UART_FR_RXFE_BITN 4 +#define UART_FR_RXFE_M 0x00000010 +#define UART_FR_RXFE_S 4 + +// Field: [3] BUSY +// +// UART Busy: +// If this bit is set to 1, the UART is busy transmitting data. This bit +// remains set until the complete byte, including all the stop bits, has been +// sent from the shift register. +// This bit is set as soon as the transmit FIFO becomes non-empty, regardless +// of whether the UART is enabled or not. +#define UART_FR_BUSY 0x00000008 +#define UART_FR_BUSY_BITN 3 +#define UART_FR_BUSY_M 0x00000008 +#define UART_FR_BUSY_S 3 + +// Field: [0] CTS +// +// Clear To Send: +// This bit is the complement of the active-low UART CTS input pin. +// That is, the bit is 1 when CTS input pin is LOW. +#define UART_FR_CTS 0x00000001 +#define UART_FR_CTS_BITN 0 +#define UART_FR_CTS_M 0x00000001 +#define UART_FR_CTS_S 0 + +//***************************************************************************** +// +// Register: UART_O_IBRD +// +//***************************************************************************** +// Field: [15:0] DIVINT +// +// The integer baud rate divisor: +// The baud rate divisor is calculated using the formula below: +// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) +// Baud rate divisor must be minimum 1 and maximum 65535. +// That is, DIVINT=0 does not give a valid baud rate. +// Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be +// illegal. +// A valid value must be written to this field before the UART can be used for +// RX or TX operations. +#define UART_IBRD_DIVINT_W 16 +#define UART_IBRD_DIVINT_M 0x0000FFFF +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// Register: UART_O_FBRD +// +//***************************************************************************** +// Field: [5:0] DIVFRAC +// +// Fractional Baud-Rate Divisor: +// The baud rate divisor is calculated using the formula below: +// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) +// Baud rate divisor must be minimum 1 and maximum 65535. +// That is, IBRD.DIVINT=0 does not give a valid baud rate. +// Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be +// illegal. +// A valid value must be written to this field before the UART can be used for +// RX or TX operations. +#define UART_FBRD_DIVFRAC_W 6 +#define UART_FBRD_DIVFRAC_M 0x0000003F +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// Register: UART_O_LCRH +// +//***************************************************************************** +// Field: [7] SPS +// +// UART Stick Parity Select: +// +// 0: Stick parity is disabled +// 1: The parity bit is transmitted and checked as invert of EPS field (i.e. +// the parity bit is transmitted and checked as 1 when EPS = 0). +// +// This bit has no effect when PEN disables parity checking and generation. +#define UART_LCRH_SPS 0x00000080 +#define UART_LCRH_SPS_BITN 7 +#define UART_LCRH_SPS_M 0x00000080 +#define UART_LCRH_SPS_S 7 + +// Field: [6:5] WLEN +// +// UART Word Length: +// These bits indicate the number of data bits transmitted or received in a +// frame. +// ENUMs: +// 8 Word Length 8 bits +// 7 Word Length 7 bits +// 6 Word Length 6 bits +// 5 Word Length 5 bits +#define UART_LCRH_WLEN_W 2 +#define UART_LCRH_WLEN_M 0x00000060 +#define UART_LCRH_WLEN_S 5 +#define UART_LCRH_WLEN_8 0x00000060 +#define UART_LCRH_WLEN_7 0x00000040 +#define UART_LCRH_WLEN_6 0x00000020 +#define UART_LCRH_WLEN_5 0x00000000 + +// Field: [4] FEN +// +// UART Enable FIFOs +// ENUMs: +// EN Transmit and receive FIFO buffers are enabled +// (FIFO mode) +// DIS FIFOs are disabled (character mode) that is, the +// FIFOs become 1-byte-deep holding registers. +#define UART_LCRH_FEN 0x00000010 +#define UART_LCRH_FEN_BITN 4 +#define UART_LCRH_FEN_M 0x00000010 +#define UART_LCRH_FEN_S 4 +#define UART_LCRH_FEN_EN 0x00000010 +#define UART_LCRH_FEN_DIS 0x00000000 + +// Field: [3] STP2 +// +// UART Two Stop Bits Select: +// If this bit is set to 1, two stop bits are transmitted at the end of the +// frame. The receive logic does not check for two stop bits being received. +#define UART_LCRH_STP2 0x00000008 +#define UART_LCRH_STP2_BITN 3 +#define UART_LCRH_STP2_M 0x00000008 +#define UART_LCRH_STP2_S 3 + +// Field: [2] EPS +// +// UART Even Parity Select +// ENUMs: +// EVEN Even parity: The UART generates or checks for an +// even number of 1s in the data and parity bits. +// ODD Odd parity: The UART generates or checks for an +// odd number of 1s in the data and parity bits. +#define UART_LCRH_EPS 0x00000004 +#define UART_LCRH_EPS_BITN 2 +#define UART_LCRH_EPS_M 0x00000004 +#define UART_LCRH_EPS_S 2 +#define UART_LCRH_EPS_EVEN 0x00000004 +#define UART_LCRH_EPS_ODD 0x00000000 + +// Field: [1] PEN +// +// UART Parity Enable +// This bit controls generation and checking of parity bit. +// ENUMs: +// EN Parity checking and generation is enabled. +// DIS Parity is disabled and no parity bit is added to +// the data frame +#define UART_LCRH_PEN 0x00000002 +#define UART_LCRH_PEN_BITN 1 +#define UART_LCRH_PEN_M 0x00000002 +#define UART_LCRH_PEN_S 1 +#define UART_LCRH_PEN_EN 0x00000002 +#define UART_LCRH_PEN_DIS 0x00000000 + +// Field: [0] BRK +// +// UART Send Break +// If this bit is set to 1, a low-level is continually output on the UARTTXD +// output pin, after completing transmission of the current character. For the +// proper execution of the break command, the +// software must set this bit for at least two complete frames. For normal use, +// this bit must be cleared to 0. +#define UART_LCRH_BRK 0x00000001 +#define UART_LCRH_BRK_BITN 0 +#define UART_LCRH_BRK_M 0x00000001 +#define UART_LCRH_BRK_S 0 + +//***************************************************************************** +// +// Register: UART_O_CTL +// +//***************************************************************************** +// Field: [15] CTSEN +// +// CTS hardware flow control enable +// ENUMs: +// EN CTS hardware flow control enabled +// DIS CTS hardware flow control disabled +#define UART_CTL_CTSEN 0x00008000 +#define UART_CTL_CTSEN_BITN 15 +#define UART_CTL_CTSEN_M 0x00008000 +#define UART_CTL_CTSEN_S 15 +#define UART_CTL_CTSEN_EN 0x00008000 +#define UART_CTL_CTSEN_DIS 0x00000000 + +// Field: [14] RTSEN +// +// RTS hardware flow control enable +// ENUMs: +// EN RTS hardware flow control enabled +// DIS RTS hardware flow control disabled +#define UART_CTL_RTSEN 0x00004000 +#define UART_CTL_RTSEN_BITN 14 +#define UART_CTL_RTSEN_M 0x00004000 +#define UART_CTL_RTSEN_S 14 +#define UART_CTL_RTSEN_EN 0x00004000 +#define UART_CTL_RTSEN_DIS 0x00000000 + +// Field: [11] RTS +// +// Request to Send +// This bit is the complement of the active-low UART RTS output. That is, when +// the bit is programmed to a 1 then RTS output on the pins is LOW. +#define UART_CTL_RTS 0x00000800 +#define UART_CTL_RTS_BITN 11 +#define UART_CTL_RTS_M 0x00000800 +#define UART_CTL_RTS_S 11 + +// Field: [9] RXE +// +// UART Receive Enable +// If the UART is disabled in the middle of reception, it completes the current +// character before stopping. +// ENUMs: +// EN UART Receive enabled +// DIS UART Receive disabled +#define UART_CTL_RXE 0x00000200 +#define UART_CTL_RXE_BITN 9 +#define UART_CTL_RXE_M 0x00000200 +#define UART_CTL_RXE_S 9 +#define UART_CTL_RXE_EN 0x00000200 +#define UART_CTL_RXE_DIS 0x00000000 + +// Field: [8] TXE +// +// UART Transmit Enable +// If the UART is disabled in the middle of transmission, it completes the +// current character before stopping. +// ENUMs: +// EN UART Transmit enabled +// DIS UART Transmit disabled +#define UART_CTL_TXE 0x00000100 +#define UART_CTL_TXE_BITN 8 +#define UART_CTL_TXE_M 0x00000100 +#define UART_CTL_TXE_S 8 +#define UART_CTL_TXE_EN 0x00000100 +#define UART_CTL_TXE_DIS 0x00000000 + +// Field: [7] LBE +// +// UART Loop Back Enable: +// Enabling the loop-back mode connects the UARTTXD output from the UART to +// UARTRXD input of the UART. +// ENUMs: +// EN Loop Back enabled +// DIS Loop Back disabled +#define UART_CTL_LBE 0x00000080 +#define UART_CTL_LBE_BITN 7 +#define UART_CTL_LBE_M 0x00000080 +#define UART_CTL_LBE_S 7 +#define UART_CTL_LBE_EN 0x00000080 +#define UART_CTL_LBE_DIS 0x00000000 + +// Field: [0] UARTEN +// +// UART Enable +// ENUMs: +// EN UART enabled +// DIS UART disabled +#define UART_CTL_UARTEN 0x00000001 +#define UART_CTL_UARTEN_BITN 0 +#define UART_CTL_UARTEN_M 0x00000001 +#define UART_CTL_UARTEN_S 0 +#define UART_CTL_UARTEN_EN 0x00000001 +#define UART_CTL_UARTEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: UART_O_IFLS +// +//***************************************************************************** +// Field: [5:3] RXSEL +// +// Receive interrupt FIFO level select: +// This field sets the trigger points for the receive interrupt. Values +// 0b101-0b111 are reserved. +// ENUMs: +// 7_8 Receive FIFO becomes >= 7/8 full +// 6_8 Receive FIFO becomes >= 3/4 full +// 4_8 Receive FIFO becomes >= 1/2 full +// 2_8 Receive FIFO becomes >= 1/4 full +// 1_8 Receive FIFO becomes >= 1/8 full +#define UART_IFLS_RXSEL_W 3 +#define UART_IFLS_RXSEL_M 0x00000038 +#define UART_IFLS_RXSEL_S 3 +#define UART_IFLS_RXSEL_7_8 0x00000020 +#define UART_IFLS_RXSEL_6_8 0x00000018 +#define UART_IFLS_RXSEL_4_8 0x00000010 +#define UART_IFLS_RXSEL_2_8 0x00000008 +#define UART_IFLS_RXSEL_1_8 0x00000000 + +// Field: [2:0] TXSEL +// +// Transmit interrupt FIFO level select: +// This field sets the trigger points for the transmit interrupt. Values +// 0b101-0b111 are reserved. +// ENUMs: +// 7_8 Transmit FIFO becomes <= 7/8 full +// 6_8 Transmit FIFO becomes <= 3/4 full +// 4_8 Transmit FIFO becomes <= 1/2 full +// 2_8 Transmit FIFO becomes <= 1/4 full +// 1_8 Transmit FIFO becomes <= 1/8 full +#define UART_IFLS_TXSEL_W 3 +#define UART_IFLS_TXSEL_M 0x00000007 +#define UART_IFLS_TXSEL_S 0 +#define UART_IFLS_TXSEL_7_8 0x00000004 +#define UART_IFLS_TXSEL_6_8 0x00000003 +#define UART_IFLS_TXSEL_4_8 0x00000002 +#define UART_IFLS_TXSEL_2_8 0x00000001 +#define UART_IFLS_TXSEL_1_8 0x00000000 + +//***************************************************************************** +// +// Register: UART_O_IMSC +// +//***************************************************************************** +// Field: [11] EOTIM +// +// End of Transmission interrupt mask. A read returns the current mask for +// UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set +// which means the interrupt state will be reflected in MIS.EOTMIS. A write of +// 0 clears the mask which means MIS.EOTMIS will not reflect the interrupt. +#define UART_IMSC_EOTIM 0x00000800 +#define UART_IMSC_EOTIM_BITN 11 +#define UART_IMSC_EOTIM_M 0x00000800 +#define UART_IMSC_EOTIM_S 11 + +// Field: [10] OEIM +// +// Overrun error interrupt mask. A read returns the current mask for UART's +// overrun error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not +// reflect the interrupt. +#define UART_IMSC_OEIM 0x00000400 +#define UART_IMSC_OEIM_BITN 10 +#define UART_IMSC_OEIM_M 0x00000400 +#define UART_IMSC_OEIM_S 10 + +// Field: [9] BEIM +// +// Break error interrupt mask. A read returns the current mask for UART's break +// error interrupt. On a write of 1, the mask of the overrun error interrupt is +// set which means the interrupt state will be reflected in MIS.BEMIS. A write +// of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. +#define UART_IMSC_BEIM 0x00000200 +#define UART_IMSC_BEIM_BITN 9 +#define UART_IMSC_BEIM_M 0x00000200 +#define UART_IMSC_BEIM_S 9 + +// Field: [8] PEIM +// +// Parity error interrupt mask. A read returns the current mask for UART's +// parity error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not +// reflect the interrupt. +#define UART_IMSC_PEIM 0x00000100 +#define UART_IMSC_PEIM_BITN 8 +#define UART_IMSC_PEIM_M 0x00000100 +#define UART_IMSC_PEIM_S 8 + +// Field: [7] FEIM +// +// Framing error interrupt mask. A read returns the current mask for UART's +// framing error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not +// reflect the interrupt. +#define UART_IMSC_FEIM 0x00000080 +#define UART_IMSC_FEIM_BITN 7 +#define UART_IMSC_FEIM_M 0x00000080 +#define UART_IMSC_FEIM_S 7 + +// Field: [6] RTIM +// +// Receive timeout interrupt mask. A read returns the current mask for UART's +// receive timeout interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not +// reflect the interrupt. +// The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the +// mask is set (RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. +#define UART_IMSC_RTIM 0x00000040 +#define UART_IMSC_RTIM_BITN 6 +#define UART_IMSC_RTIM_M 0x00000040 +#define UART_IMSC_RTIM_S 6 + +// Field: [5] TXIM +// +// Transmit interrupt mask. A read returns the current mask for UART's transmit +// interrupt. On a write of 1, the mask of the overrun error interrupt is set +// which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 +// clears the mask which means MIS.TXMIS will not reflect the interrupt. +#define UART_IMSC_TXIM 0x00000020 +#define UART_IMSC_TXIM_BITN 5 +#define UART_IMSC_TXIM_M 0x00000020 +#define UART_IMSC_TXIM_S 5 + +// Field: [4] RXIM +// +// Receive interrupt mask. A read returns the current mask for UART's receive +// interrupt. On a write of 1, the mask of the overrun error interrupt is set +// which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 +// clears the mask which means MIS.RXMIS will not reflect the interrupt. +#define UART_IMSC_RXIM 0x00000010 +#define UART_IMSC_RXIM_BITN 4 +#define UART_IMSC_RXIM_M 0x00000010 +#define UART_IMSC_RXIM_S 4 + +// Field: [1] CTSMIM +// +// Clear to Send (CTS) modem interrupt mask. A read returns the current mask +// for UART's clear to send interrupt. On a write of 1, the mask of the overrun +// error interrupt is set which means the interrupt state will be reflected in +// MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not +// reflect the interrupt. +#define UART_IMSC_CTSMIM 0x00000002 +#define UART_IMSC_CTSMIM_BITN 1 +#define UART_IMSC_CTSMIM_M 0x00000002 +#define UART_IMSC_CTSMIM_S 1 + +//***************************************************************************** +// +// Register: UART_O_RIS +// +//***************************************************************************** +// Field: [11] EOTRIS +// +// End of Transmission interrupt status: +// This field returns the raw interrupt state of UART's end of transmission +// interrupt. End of transmission flag is set when all the Transmit data in the +// FIFO and on the TX Line is tranmitted. +#define UART_RIS_EOTRIS 0x00000800 +#define UART_RIS_EOTRIS_BITN 11 +#define UART_RIS_EOTRIS_M 0x00000800 +#define UART_RIS_EOTRIS_S 11 + +// Field: [10] OERIS +// +// Overrun error interrupt status: +// This field returns the raw interrupt state of UART's overrun error +// interrupt. Overrun error occurs if data is received and the receive FIFO is +// full. +#define UART_RIS_OERIS 0x00000400 +#define UART_RIS_OERIS_BITN 10 +#define UART_RIS_OERIS_M 0x00000400 +#define UART_RIS_OERIS_S 10 + +// Field: [9] BERIS +// +// Break error interrupt status: +// This field returns the raw interrupt state of UART's break error interrupt. +// Break error is set when a break condition is detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +#define UART_RIS_BERIS 0x00000200 +#define UART_RIS_BERIS_BITN 9 +#define UART_RIS_BERIS_M 0x00000200 +#define UART_RIS_BERIS_S 9 + +// Field: [8] PERIS +// +// Parity error interrupt status: +// This field returns the raw interrupt state of UART's parity error interrupt. +// Parity error is set if the parity of the received data character does not +// match the parity that the LCRH.EPS and LCRH.SPS select. +#define UART_RIS_PERIS 0x00000100 +#define UART_RIS_PERIS_BITN 8 +#define UART_RIS_PERIS_M 0x00000100 +#define UART_RIS_PERIS_S 8 + +// Field: [7] FERIS +// +// Framing error interrupt status: +// This field returns the raw interrupt state of UART's framing error +// interrupt. Framing error is set if the received character does not have a +// valid stop bit (a valid stop bit is 1). +#define UART_RIS_FERIS 0x00000080 +#define UART_RIS_FERIS_BITN 7 +#define UART_RIS_FERIS_M 0x00000080 +#define UART_RIS_FERIS_S 7 + +// Field: [6] RTRIS +// +// Receive timeout interrupt status: +// This field returns the raw interrupt state of UART's receive timeout +// interrupt. The receive timeout interrupt is asserted when the receive FIFO +// is not empty, and no more data is received during a 32-bit period. The +// receive timeout interrupt is cleared either when the FIFO becomes empty +// through reading all the data, or when a 1 is written to ICR.RTIC. +// The raw interrupt for receive timeout cannot be set unless the mask is set +// (IMSC.RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from MIS.RTMIS and RTRIS. +#define UART_RIS_RTRIS 0x00000040 +#define UART_RIS_RTRIS_BITN 6 +#define UART_RIS_RTRIS_M 0x00000040 +#define UART_RIS_RTRIS_S 6 + +// Field: [5] TXRIS +// +// Transmit interrupt status: +// This field returns the raw interrupt state of UART's transmit interrupt. +// When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if +// the number of bytes in transmit FIFO is equal to or lower than the +// programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by +// writing data to the transmit FIFO until it becomes greater than the trigger +// level, or by clearing the interrupt through ICR.TXIC. +// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one +// location, the transmit interrupt is asserted if there is no data present in +// the transmitters single location. It is cleared by performing a single write +// to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. +#define UART_RIS_TXRIS 0x00000020 +#define UART_RIS_TXRIS_BITN 5 +#define UART_RIS_TXRIS_M 0x00000020 +#define UART_RIS_TXRIS_S 5 + +// Field: [4] RXRIS +// +// Receive interrupt status: +// This field returns the raw interrupt state of UART's receive interrupt. +// When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if +// the receive FIFO reaches the programmed trigger +// level (IFLS.RXSEL). The receive interrupt is cleared by reading data from +// the receive FIFO until it becomes less than the trigger level, or by +// clearing the interrupt through ICR.RXIC. +// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one +// location, the receive interrupt is asserted if data is received +// thereby filling the location. The receive interrupt is cleared by performing +// a single read of the receive FIFO, or by clearing the interrupt through +// ICR.RXIC. +#define UART_RIS_RXRIS 0x00000010 +#define UART_RIS_RXRIS_BITN 4 +#define UART_RIS_RXRIS_M 0x00000010 +#define UART_RIS_RXRIS_S 4 + +// Field: [1] CTSRMIS +// +// Clear to Send (CTS) modem interrupt status: +// This field returns the raw interrupt state of UART's clear to send +// interrupt. +#define UART_RIS_CTSRMIS 0x00000002 +#define UART_RIS_CTSRMIS_BITN 1 +#define UART_RIS_CTSRMIS_M 0x00000002 +#define UART_RIS_CTSRMIS_S 1 + +//***************************************************************************** +// +// Register: UART_O_MIS +// +//***************************************************************************** +// Field: [11] EOTMIS +// +// End of Transmission interrupt status: +// This field returns the masked interrupt state of the overrun interrupt which +// is the AND product of raw interrupt state RIS.EOTRIS and the mask setting +// IMSC.EOTIM. +#define UART_MIS_EOTMIS 0x00000800 +#define UART_MIS_EOTMIS_BITN 11 +#define UART_MIS_EOTMIS_M 0x00000800 +#define UART_MIS_EOTMIS_S 11 + +// Field: [10] OEMIS +// +// Overrun error masked interrupt status: +// This field returns the masked interrupt state of the overrun interrupt which +// is the AND product of raw interrupt state RIS.OERIS and the mask setting +// IMSC.OEIM. +#define UART_MIS_OEMIS 0x00000400 +#define UART_MIS_OEMIS_BITN 10 +#define UART_MIS_OEMIS_M 0x00000400 +#define UART_MIS_OEMIS_S 10 + +// Field: [9] BEMIS +// +// Break error masked interrupt status: +// This field returns the masked interrupt state of the break error interrupt +// which is the AND product of raw interrupt state RIS.BERIS and the mask +// setting IMSC.BEIM. +#define UART_MIS_BEMIS 0x00000200 +#define UART_MIS_BEMIS_BITN 9 +#define UART_MIS_BEMIS_M 0x00000200 +#define UART_MIS_BEMIS_S 9 + +// Field: [8] PEMIS +// +// Parity error masked interrupt status: +// This field returns the masked interrupt state of the parity error interrupt +// which is the AND product of raw interrupt state RIS.PERIS and the mask +// setting IMSC.PEIM. +#define UART_MIS_PEMIS 0x00000100 +#define UART_MIS_PEMIS_BITN 8 +#define UART_MIS_PEMIS_M 0x00000100 +#define UART_MIS_PEMIS_S 8 + +// Field: [7] FEMIS +// +// Framing error masked interrupt status: Returns the masked interrupt state of +// the framing error interrupt which is the AND product of raw interrupt state +// RIS.FERIS and the mask setting IMSC.FEIM. +#define UART_MIS_FEMIS 0x00000080 +#define UART_MIS_FEMIS_BITN 7 +#define UART_MIS_FEMIS_M 0x00000080 +#define UART_MIS_FEMIS_S 7 + +// Field: [6] RTMIS +// +// Receive timeout masked interrupt status: +// Returns the masked interrupt state of the receive timeout interrupt. +// The raw interrupt for receive timeout cannot be set unless the mask is set +// (IMSC.RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from RTMIS and RIS.RTRIS. +#define UART_MIS_RTMIS 0x00000040 +#define UART_MIS_RTMIS_BITN 6 +#define UART_MIS_RTMIS_M 0x00000040 +#define UART_MIS_RTMIS_S 6 + +// Field: [5] TXMIS +// +// Transmit masked interrupt status: +// This field returns the masked interrupt state of the transmit interrupt +// which is the AND product of raw interrupt state RIS.TXRIS and the mask +// setting IMSC.TXIM. +#define UART_MIS_TXMIS 0x00000020 +#define UART_MIS_TXMIS_BITN 5 +#define UART_MIS_TXMIS_M 0x00000020 +#define UART_MIS_TXMIS_S 5 + +// Field: [4] RXMIS +// +// Receive masked interrupt status: +// This field returns the masked interrupt state of the receive interrupt +// which is the AND product of raw interrupt state RIS.RXRIS and the mask +// setting IMSC.RXIM. +#define UART_MIS_RXMIS 0x00000010 +#define UART_MIS_RXMIS_BITN 4 +#define UART_MIS_RXMIS_M 0x00000010 +#define UART_MIS_RXMIS_S 4 + +// Field: [1] CTSMMIS +// +// Clear to Send (CTS) modem masked interrupt status: +// This field returns the masked interrupt state of the clear to send interrupt +// which is the AND product of raw interrupt state RIS.CTSRMIS and the mask +// setting IMSC.CTSMIM. +#define UART_MIS_CTSMMIS 0x00000002 +#define UART_MIS_CTSMMIS_BITN 1 +#define UART_MIS_CTSMMIS_M 0x00000002 +#define UART_MIS_CTSMMIS_S 1 + +//***************************************************************************** +// +// Register: UART_O_ICR +// +//***************************************************************************** +// Field: [11] EOTIC +// +// End of Transmission interrupt clear: +// Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS). +// Writing 0 has no effect. +#define UART_ICR_EOTIC 0x00000800 +#define UART_ICR_EOTIC_BITN 11 +#define UART_ICR_EOTIC_M 0x00000800 +#define UART_ICR_EOTIC_S 11 + +// Field: [10] OEIC +// +// Overrun error interrupt clear: +// Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). +// Writing 0 has no effect. +#define UART_ICR_OEIC 0x00000400 +#define UART_ICR_OEIC_BITN 10 +#define UART_ICR_OEIC_M 0x00000400 +#define UART_ICR_OEIC_S 10 + +// Field: [9] BEIC +// +// Break error interrupt clear: +// Writing 1 to this field clears the break error interrupt (RIS.BERIS). +// Writing 0 has no effect. +#define UART_ICR_BEIC 0x00000200 +#define UART_ICR_BEIC_BITN 9 +#define UART_ICR_BEIC_M 0x00000200 +#define UART_ICR_BEIC_S 9 + +// Field: [8] PEIC +// +// Parity error interrupt clear: +// Writing 1 to this field clears the parity error interrupt (RIS.PERIS). +// Writing 0 has no effect. +#define UART_ICR_PEIC 0x00000100 +#define UART_ICR_PEIC_BITN 8 +#define UART_ICR_PEIC_M 0x00000100 +#define UART_ICR_PEIC_S 8 + +// Field: [7] FEIC +// +// Framing error interrupt clear: +// Writing 1 to this field clears the framing error interrupt (RIS.FERIS). +// Writing 0 has no effect. +#define UART_ICR_FEIC 0x00000080 +#define UART_ICR_FEIC_BITN 7 +#define UART_ICR_FEIC_M 0x00000080 +#define UART_ICR_FEIC_S 7 + +// Field: [6] RTIC +// +// Receive timeout interrupt clear: +// Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). +// Writing 0 has no effect. +#define UART_ICR_RTIC 0x00000040 +#define UART_ICR_RTIC_BITN 6 +#define UART_ICR_RTIC_M 0x00000040 +#define UART_ICR_RTIC_S 6 + +// Field: [5] TXIC +// +// Transmit interrupt clear: +// Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 +// has no effect. +#define UART_ICR_TXIC 0x00000020 +#define UART_ICR_TXIC_BITN 5 +#define UART_ICR_TXIC_M 0x00000020 +#define UART_ICR_TXIC_S 5 + +// Field: [4] RXIC +// +// Receive interrupt clear: +// Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 +// has no effect. +#define UART_ICR_RXIC 0x00000010 +#define UART_ICR_RXIC_BITN 4 +#define UART_ICR_RXIC_M 0x00000010 +#define UART_ICR_RXIC_S 4 + +// Field: [1] CTSMIC +// +// Clear to Send (CTS) modem interrupt clear: +// Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). +// Writing 0 has no effect. +#define UART_ICR_CTSMIC 0x00000002 +#define UART_ICR_CTSMIC_BITN 1 +#define UART_ICR_CTSMIC_M 0x00000002 +#define UART_ICR_CTSMIC_S 1 + +//***************************************************************************** +// +// Register: UART_O_DMACTL +// +//***************************************************************************** +// Field: [2] DMAONERR +// +// DMA on error. If this bit is set to 1, the DMA receive request outputs (for +// single and burst requests) are disabled when the UART error interrupt is +// asserted (more specifically if any of the error interrupts RIS.PERIS, +// RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). +#define UART_DMACTL_DMAONERR 0x00000004 +#define UART_DMACTL_DMAONERR_BITN 2 +#define UART_DMACTL_DMAONERR_M 0x00000004 +#define UART_DMACTL_DMAONERR_S 2 + +// Field: [1] TXDMAE +// +// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is +// enabled. +#define UART_DMACTL_TXDMAE 0x00000002 +#define UART_DMACTL_TXDMAE_BITN 1 +#define UART_DMACTL_TXDMAE_M 0x00000002 +#define UART_DMACTL_TXDMAE_S 1 + +// Field: [0] RXDMAE +// +// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is +// enabled. +#define UART_DMACTL_RXDMAE 0x00000001 +#define UART_DMACTL_RXDMAE_BITN 0 +#define UART_DMACTL_RXDMAE_M 0x00000001 +#define UART_DMACTL_RXDMAE_S 0 + + +#endif // __UART__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_udma.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_udma.h new file mode 100644 index 0000000..566192b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_udma.h @@ -0,0 +1,575 @@ +/****************************************************************************** +* Filename: hw_udma_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_UDMA_H__ +#define __HW_UDMA_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// UDMA component +// +//***************************************************************************** +// Status +#define UDMA_O_STATUS 0x00000000 + +// Configuration +#define UDMA_O_CFG 0x00000004 + +// Channel Control Data Base Pointer +#define UDMA_O_CTRL 0x00000008 + +// Channel Alternate Control Data Base Pointer +#define UDMA_O_ALTCTRL 0x0000000C + +// Channel Wait On Request Status +#define UDMA_O_WAITONREQ 0x00000010 + +// Channel Software Request +#define UDMA_O_SOFTREQ 0x00000014 + +// Channel Set UseBurst +#define UDMA_O_SETBURST 0x00000018 + +// Channel Clear UseBurst +#define UDMA_O_CLEARBURST 0x0000001C + +// Channel Set Request Mask +#define UDMA_O_SETREQMASK 0x00000020 + +// Clear Channel Request Mask +#define UDMA_O_CLEARREQMASK 0x00000024 + +// Set Channel Enable +#define UDMA_O_SETCHANNELEN 0x00000028 + +// Clear Channel Enable +#define UDMA_O_CLEARCHANNELEN 0x0000002C + +// Channel Set Primary-Alternate +#define UDMA_O_SETCHNLPRIALT 0x00000030 + +// Channel Clear Primary-Alternate +#define UDMA_O_CLEARCHNLPRIALT 0x00000034 + +// Set Channel Priority +#define UDMA_O_SETCHNLPRIORITY 0x00000038 + +// Clear Channel Priority +#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C + +// Error Status and Clear +#define UDMA_O_ERROR 0x0000004C + +// Channel Request Done +#define UDMA_O_REQDONE 0x00000504 + +// Channel Request Done Mask +#define UDMA_O_DONEMASK 0x00000520 + +//***************************************************************************** +// +// Register: UDMA_O_STATUS +// +//***************************************************************************** +// Field: [31:28] TEST +// +// +// 0x0: Controller does not include the integration test logic +// 0x1: Controller includes the integration test logic +// 0x2: Undefined +// ... +// 0xF: Undefined +#define UDMA_STATUS_TEST_W 4 +#define UDMA_STATUS_TEST_M 0xF0000000 +#define UDMA_STATUS_TEST_S 28 + +// Field: [20:16] TOTALCHANNELS +// +// Register value returns number of available uDMA channels minus one. For +// example a read out value of: +// +// 0x00: Show that the controller is configured to use 1 uDMA channel +// 0x01: Shows that the controller is configured to use 2 uDMA channels +// ... +// 0x1F: Shows that the controller is configured to use 32 uDMA channels +// (32-1=31=0x1F) +#define UDMA_STATUS_TOTALCHANNELS_W 5 +#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 +#define UDMA_STATUS_TOTALCHANNELS_S 16 + +// Field: [7:4] STATE +// +// Current state of the control state machine. State can be one of the +// following: +// +// 0x0: Idle +// 0x1: Reading channel controller data +// 0x2: Reading source data end pointer +// 0x3: Reading destination data end pointer +// 0x4: Reading source data +// 0x5: Writing destination data +// 0x6: Waiting for uDMA request to clear +// 0x7: Writing channel controller data +// 0x8: Stalled +// 0x9: Done +// 0xA: Peripheral scatter-gather transition +// 0xB: Undefined +// ... +// 0xF: Undefined. +#define UDMA_STATUS_STATE_W 4 +#define UDMA_STATUS_STATE_M 0x000000F0 +#define UDMA_STATUS_STATE_S 4 + +// Field: [0] MASTERENABLE +// +// Shows the enable status of the controller as configured by CFG.MASTERENABLE: +// +// 0: Controller is disabled +// 1: Controller is enabled +#define UDMA_STATUS_MASTERENABLE 0x00000001 +#define UDMA_STATUS_MASTERENABLE_BITN 0 +#define UDMA_STATUS_MASTERENABLE_M 0x00000001 +#define UDMA_STATUS_MASTERENABLE_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CFG +// +//***************************************************************************** +// Field: [7:5] PRTOCTRL +// +// Sets the AHB-Lite bus protocol protection state by controlling the AHB +// signal HProt[3:1] as follows: +// +// Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring. +// Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring. +// Bit [5] Controls HProt[1] to indicate if a privileged access is occurring. +// +// When bit [n] = 1 then the corresponding HProt bit is high. +// When bit [n] = 0 then the corresponding HProt bit is low. +// +// This field controls HProt[3:1] signal for all transactions initiated by uDMA +// except two transactions below: +// - the read from the address indicated by source address pointer +// - the write to the address indicated by destination address pointer +// HProt[3:1] for these two exceptions can be controlled by dedicated fields in +// the channel configutation descriptor. +#define UDMA_CFG_PRTOCTRL_W 3 +#define UDMA_CFG_PRTOCTRL_M 0x000000E0 +#define UDMA_CFG_PRTOCTRL_S 5 + +// Field: [0] MASTERENABLE +// +// Enables the controller: +// +// 0: Disables the controller +// 1: Enables the controller +#define UDMA_CFG_MASTERENABLE 0x00000001 +#define UDMA_CFG_MASTERENABLE_BITN 0 +#define UDMA_CFG_MASTERENABLE_M 0x00000001 +#define UDMA_CFG_MASTERENABLE_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CTRL +// +//***************************************************************************** +// Field: [31:10] BASEPTR +// +// This register point to the base address for the primary data structures of +// each DMA channel. This is not stored in module, but in system memory, thus +// space must be allocated for this usage when DMA is in usage +#define UDMA_CTRL_BASEPTR_W 22 +#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 +#define UDMA_CTRL_BASEPTR_S 10 + +//***************************************************************************** +// +// Register: UDMA_O_ALTCTRL +// +//***************************************************************************** +// Field: [31:0] BASEPTR +// +// This register shows the base address for the alternate data structures and +// is calculated by module, thus read only +#define UDMA_ALTCTRL_BASEPTR_W 32 +#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF +#define UDMA_ALTCTRL_BASEPTR_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_WAITONREQ +// +//***************************************************************************** +// Field: [31:0] CHNLSTATUS +// +// Channel wait on request status: +// +// Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, +// this channel may come out of active state even if request is still present. +// Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it +// keeps channel Ch in active state until the requests are deasserted. This +// handshake is necessary for channels where the requester is in an +// asynchronous domain or can run at slower clock speed than uDMA +#define UDMA_WAITONREQ_CHNLSTATUS_W 32 +#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF +#define UDMA_WAITONREQ_CHNLSTATUS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SOFTREQ +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to generate a software uDMA request on the +// corresponding uDMA channel +// +// Bit [Ch] = 0: Does not create a uDMA request for channel Ch +// Bit [Ch] = 1: Creates a uDMA request for channel Ch +// +// Writing to a bit where a uDMA channel is not implemented does not create a +// uDMA request for that channel +#define UDMA_SOFTREQ_CHNLS_W 32 +#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF +#define UDMA_SOFTREQ_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETBURST +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the useburst status, or disables individual channels from generating +// single uDMA requests. The value R is the arbitration rate and stored in the +// controller data structure. +// +// Read as: +// +// Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on +// channel C. The controller performs 2^R, or single, bus transfers. +// +// Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. +// The controller only responds to burst transfer requests and performs 2^R +// transfers. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0. +// Bit [Ch] = 1: Disables single transfer requests on channel Ch. The +// controller performs 2^R transfers for burst requests. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETBURST_CHNLS_W 32 +#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_SETBURST_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARBURST +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to enable single transfer requests. +// +// Write as: +// +// Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer +// requests. +// +// Bit [Ch] = 1: Enables single transfer requests on channel Ch. +// +// Writing to a bit where a DMA channel is not implemented has no effect. +#define UDMA_CLEARBURST_CHNLS_W 32 +#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARBURST_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETREQMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the burst and single request mask status, or disables the +// corresponding channel from generating uDMA requests. +// +// Read as: +// Bit [Ch] = 0: External requests are enabled for channel Ch. +// Bit [Ch] = 1: External requests are disabled for channel Ch. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests. +// Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA single +// request channel [C] input from generating uDMA requests. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETREQMASK_CHNLS_W 32 +#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_SETREQMASK_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARREQMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to enable DMA request for the channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel C from +// generating requests. +// Bit [Ch] = 1: Enables channel [C] to generate DMA requests. +// +// Writing to a bit where a DMA channel is not implemented has no effect. +#define UDMA_CLEARREQMASK_CHNLS_W 32 +#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARREQMASK_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHANNELEN +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the enable status of the channels, or enables the corresponding +// channels. +// +// Read as: +// Bit [Ch] = 0: Channel Ch is disabled. +// Bit [Ch] = 1: Channel Ch is enabled. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel +// Bit [Ch] = 1: Enables channel Ch +// +// Writing to a bit where a DMA channel is not implemented has no effect +#define UDMA_SETCHANNELEN_CHNLS_W 32 +#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHANNELEN_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHANNELEN +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to disable the corresponding uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels. +// Bit [Ch] = 1: Disables channel Ch +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHANNELEN_CHNLS_W 32 +#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHANNELEN_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHNLPRIALT +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the channel control data structure status, or selects the alternate +// data structure for the corresponding uDMA channel. +// +// Read as: +// Bit [Ch] = 0: uDMA channel Ch is using the primary data structure. +// Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel +// Bit [Ch] = 1: Selects the alternate data structure for channel Ch +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETCHNLPRIALT_CHNLS_W 32 +#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIALT_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHNLPRIALT +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Clears the appropriate bit to select the primary data structure for the +// corresponding uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate +// data structure. +// Bit [Ch] = 1: Selects the primary data structure for channel Ch. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHNLPRIORITY +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the channel priority mask status, or sets the channel priority to +// high. +// +// Read as: +// Bit [Ch] = 0: uDMA channel Ch is using the default priority level. +// Bit [Ch] = 1: uDMA channel Ch is using a high priority level. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch +// to the default priority level. +// Bit [Ch] = 1: Channel Ch uses the high priority level. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETCHNLPRIORITY_CHNLS_W 32 +#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIORITY_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHNLPRIORITY +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Clear the appropriate bit to select the default priority level for the +// specified uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to +// the high priority level. +// Bit [Ch] = 1: Channel Ch uses the default priority level. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_ERROR +// +//***************************************************************************** +// Field: [0] STATUS +// +// Returns the status of bus error flag in uDMA, or clears this bit +// +// Read as: +// +// 0: No bus error detected +// 1: Bus error detected +// +// Write as: +// +// 0: No effect, status of bus error flag is unchanged. +// 1: Clears the bus error flag. +#define UDMA_ERROR_STATUS 0x00000001 +#define UDMA_ERROR_STATUS_BITN 0 +#define UDMA_ERROR_STATUS_M 0x00000001 +#define UDMA_ERROR_STATUS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_REQDONE +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Reflects the uDMA done status for the given channel, channel [Ch]. It's a +// sticky done bit. Unless cleared by writing a 1, it holds the value of 1. +// +// Read as: +// Bit [Ch] = 0: Request has not completed for channel Ch +// Bit [Ch] = 1: Request has completed for the channel Ch +// +// Writing a 1 to individual bits would clear the corresponding bit. +// +// Write as: +// Bit [Ch] = 0: No effect. +// Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 +#define UDMA_REQDONE_CHNLS_W 32 +#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF +#define UDMA_REQDONE_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_DONEMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Controls the propagation of the uDMA done and active state to the assigned +// peripheral. Specifically used for software channels. +// +// Read as: +// Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from +// reaching to the peripherals. +// Note that the uDMA done state for channel [Ch] is blocked from contributing +// to generation of combined uDMA done signal +// +// Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from +// reaching to the peripherals. +// Note that the uDMA done state for channel [Ch] is not blocked from +// contributing to generation of combined uDMA done signal +// +// Write as: +// Bit [Ch] = 0: Allows uDMA done and active stat to propagate to the +// peripherals. +// Note that this disables uDMA done state for channel [Ch] from contributing +// to generation of combined uDMA done signal +// +// Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the +// peripherals. +// Note that this enables uDMA done for channel [Ch] to contribute to +// generation of combined uDMA done signal. +#define UDMA_DONEMASK_CHNLS_W 32 +#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_DONEMASK_CHNLS_S 0 + + +#endif // __UDMA__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_vims.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_vims.h new file mode 100644 index 0000000..c668670 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_vims.h @@ -0,0 +1,204 @@ +/****************************************************************************** +* Filename: hw_vims_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_VIMS_H__ +#define __HW_VIMS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// VIMS component +// +//***************************************************************************** +// Status +#define VIMS_O_STAT 0x00000000 + +// Control +#define VIMS_O_CTL 0x00000004 + +//***************************************************************************** +// +// Register: VIMS_O_STAT +// +//***************************************************************************** +// Field: [5] IDCODE_LB_DIS +// +// Icode/Dcode flash line buffer status +// +// 0: Enabled or in transition to disabled +// 1: Disabled and flushed +#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 +#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_S 5 + +// Field: [4] SYSBUS_LB_DIS +// +// Sysbus flash line buffer control +// +// 0: Enabled or in transition to disabled +// 1: Disabled and flushed +#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 +#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_S 4 + +// Field: [3] MODE_CHANGING +// +// VIMS mode change status +// +// 0: VIMS is in the mode defined by MODE +// 1: VIMS is in the process of changing to the mode given in CTL.MODE +#define VIMS_STAT_MODE_CHANGING 0x00000008 +#define VIMS_STAT_MODE_CHANGING_BITN 3 +#define VIMS_STAT_MODE_CHANGING_M 0x00000008 +#define VIMS_STAT_MODE_CHANGING_S 3 + +// Field: [2] INV +// +// This bit is set when invalidation of the cache memory is active / ongoing +#define VIMS_STAT_INV 0x00000004 +#define VIMS_STAT_INV_BITN 2 +#define VIMS_STAT_INV_M 0x00000004 +#define VIMS_STAT_INV_S 2 + +// Field: [1:0] MODE +// +// Current VIMS mode +// ENUMs: +// OFF VIMS Off mode +// CACHE VIMS Cache mode +// GPRAM VIMS GPRAM mode +#define VIMS_STAT_MODE_W 2 +#define VIMS_STAT_MODE_M 0x00000003 +#define VIMS_STAT_MODE_S 0 +#define VIMS_STAT_MODE_OFF 0x00000003 +#define VIMS_STAT_MODE_CACHE 0x00000001 +#define VIMS_STAT_MODE_GPRAM 0x00000000 + +//***************************************************************************** +// +// Register: VIMS_O_CTL +// +//***************************************************************************** +// Field: [31] STATS_CLR +// +// Set this bit to clear statistic counters. +#define VIMS_CTL_STATS_CLR 0x80000000 +#define VIMS_CTL_STATS_CLR_BITN 31 +#define VIMS_CTL_STATS_CLR_M 0x80000000 +#define VIMS_CTL_STATS_CLR_S 31 + +// Field: [30] STATS_EN +// +// Set this bit to enable statistic counters. +#define VIMS_CTL_STATS_EN 0x40000000 +#define VIMS_CTL_STATS_EN_BITN 30 +#define VIMS_CTL_STATS_EN_M 0x40000000 +#define VIMS_CTL_STATS_EN_S 30 + +// Field: [29] DYN_CG_EN +// +// 0: The in-built clock gate functionality is bypassed. +// 1: The in-built clock gate functionality is enabled, automatically gating +// the clock when not needed. +#define VIMS_CTL_DYN_CG_EN 0x20000000 +#define VIMS_CTL_DYN_CG_EN_BITN 29 +#define VIMS_CTL_DYN_CG_EN_M 0x20000000 +#define VIMS_CTL_DYN_CG_EN_S 29 + +// Field: [5] IDCODE_LB_DIS +// +// Icode/Dcode flash line buffer control +// +// 0: Enable +// 1: Disable +#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 +#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_S 5 + +// Field: [4] SYSBUS_LB_DIS +// +// Sysbus flash line buffer control +// +// 0: Enable +// 1: Disable +#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 +#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_S 4 + +// Field: [3] ARB_CFG +// +// Icode/Dcode and sysbus arbitation scheme +// +// 0: Static arbitration (icode/docde > sysbus) +// 1: Round-robin arbitration +#define VIMS_CTL_ARB_CFG 0x00000008 +#define VIMS_CTL_ARB_CFG_BITN 3 +#define VIMS_CTL_ARB_CFG_M 0x00000008 +#define VIMS_CTL_ARB_CFG_S 3 + +// Field: [2] PREF_EN +// +// Tag prefetch control +// +// 0: Disabled +// 1: Enabled +#define VIMS_CTL_PREF_EN 0x00000004 +#define VIMS_CTL_PREF_EN_BITN 2 +#define VIMS_CTL_PREF_EN_M 0x00000004 +#define VIMS_CTL_PREF_EN_S 2 + +// Field: [1:0] MODE +// +// VIMS mode request. +// Write accesses to this field will be blocked while STAT.MODE_CHANGING is set +// to 1. +// ENUMs: +// OFF VIMS Off mode +// CACHE VIMS Cache mode +// GPRAM VIMS GPRAM mode +#define VIMS_CTL_MODE_W 2 +#define VIMS_CTL_MODE_M 0x00000003 +#define VIMS_CTL_MODE_S 0 +#define VIMS_CTL_MODE_OFF 0x00000003 +#define VIMS_CTL_MODE_CACHE 0x00000001 +#define VIMS_CTL_MODE_GPRAM 0x00000000 + + +#endif // __VIMS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h new file mode 100644 index 0000000..5c1155c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h @@ -0,0 +1,290 @@ +/****************************************************************************** +* Filename: hw_wdt_h +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_WDT_H__ +#define __HW_WDT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// WDT component +// +//***************************************************************************** +// Configuration +#define WDT_O_LOAD 0x00000000 + +// Current Count Value +#define WDT_O_VALUE 0x00000004 + +// Control +#define WDT_O_CTL 0x00000008 + +// Interrupt Clear +#define WDT_O_ICR 0x0000000C + +// Raw Interrupt Status +#define WDT_O_RIS 0x00000010 + +// Masked Interrupt Status +#define WDT_O_MIS 0x00000014 + +// Test Mode +#define WDT_O_TEST 0x00000418 + +// Interrupt Cause Test Mode +#define WDT_O_INT_CAUS 0x0000041C + +// Lock +#define WDT_O_LOCK 0x00000C00 + +//***************************************************************************** +// +// Register: WDT_O_LOAD +// +//***************************************************************************** +// Field: [31:0] WDTLOAD +// +// This register is the 32-bit interval value used by the 32-bit counter. When +// this register is written, the value is immediately loaded and the counter is +// restarted to count down from the new value. If this register is loaded with +// 0x0000.0000, an interrupt is immediately generated. +#define WDT_LOAD_WDTLOAD_W 32 +#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF +#define WDT_LOAD_WDTLOAD_S 0 + +//***************************************************************************** +// +// Register: WDT_O_VALUE +// +//***************************************************************************** +// Field: [31:0] WDTVALUE +// +// This register contains the current count value of the timer. +#define WDT_VALUE_WDTVALUE_W 32 +#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF +#define WDT_VALUE_WDTVALUE_S 0 + +//***************************************************************************** +// +// Register: WDT_O_CTL +// +//***************************************************************************** +// Field: [2] INTTYPE +// +// WDT Interrupt Type +// +// 0: WDT interrupt is a standard interrupt. +// 1: WDT interrupt is a non-maskable interrupt. +// ENUMs: +// NONMASKABLE Non-maskable interrupt +// MASKABLE Maskable interrupt +#define WDT_CTL_INTTYPE 0x00000004 +#define WDT_CTL_INTTYPE_BITN 2 +#define WDT_CTL_INTTYPE_M 0x00000004 +#define WDT_CTL_INTTYPE_S 2 +#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 +#define WDT_CTL_INTTYPE_MASKABLE 0x00000000 + +// Field: [1] RESEN +// +// WDT Reset Enable. Defines the function of the WDT reset source (see +// PRCM:WARMRESET.WDT_STAT if enabled) +// +// 0: Disabled. +// 1: Enable the Watchdog reset output. +// ENUMs: +// EN Reset output Enabled +// DIS Reset output Disabled +#define WDT_CTL_RESEN 0x00000002 +#define WDT_CTL_RESEN_BITN 1 +#define WDT_CTL_RESEN_M 0x00000002 +#define WDT_CTL_RESEN_S 1 +#define WDT_CTL_RESEN_EN 0x00000002 +#define WDT_CTL_RESEN_DIS 0x00000000 + +// Field: [0] INTEN +// +// WDT Interrupt Enable +// +// 0: Interrupt event disabled. +// 1: Interrupt event enabled. Once set, this bit can only be cleared by a +// hardware reset. +// ENUMs: +// EN Interrupt Enabled +// DIS Interrupt Disabled +#define WDT_CTL_INTEN 0x00000001 +#define WDT_CTL_INTEN_BITN 0 +#define WDT_CTL_INTEN_M 0x00000001 +#define WDT_CTL_INTEN_S 0 +#define WDT_CTL_INTEN_EN 0x00000001 +#define WDT_CTL_INTEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: WDT_O_ICR +// +//***************************************************************************** +// Field: [31:0] WDTICR +// +// This register is the interrupt clear register. A write of any value to this +// register clears the WDT interrupt and reloads the 32-bit counter from the +// LOAD register. +#define WDT_ICR_WDTICR_W 32 +#define WDT_ICR_WDTICR_M 0xFFFFFFFF +#define WDT_ICR_WDTICR_S 0 + +//***************************************************************************** +// +// Register: WDT_O_RIS +// +//***************************************************************************** +// Field: [0] WDTRIS +// +// This register is the raw interrupt status register. WDT interrupt events can +// be monitored via this register if the controller interrupt is masked. +// +// Value Description +// +// 0: The WDT has not timed out +// 1: A WDT time-out event has occurred +// +#define WDT_RIS_WDTRIS 0x00000001 +#define WDT_RIS_WDTRIS_BITN 0 +#define WDT_RIS_WDTRIS_M 0x00000001 +#define WDT_RIS_WDTRIS_S 0 + +//***************************************************************************** +// +// Register: WDT_O_MIS +// +//***************************************************************************** +// Field: [0] WDTMIS +// +// This register is the masked interrupt status register. The value of this +// register is the logical AND of the raw interrupt bit and the WDT interrupt +// enable bit CTL.INTEN. +// +// Value Description +// +// 0: The WDT has not timed out or is masked. +// 1: An unmasked WDT time-out event has occurred. +#define WDT_MIS_WDTMIS 0x00000001 +#define WDT_MIS_WDTMIS_BITN 0 +#define WDT_MIS_WDTMIS_M 0x00000001 +#define WDT_MIS_WDTMIS_S 0 + +//***************************************************************************** +// +// Register: WDT_O_TEST +// +//***************************************************************************** +// Field: [8] STALL +// +// WDT Stall Enable +// +// 0: The WDT timer continues counting if the CPU is stopped with a debugger. +// 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the +// CPU is restarted, the WDT resumes counting. +// ENUMs: +// EN Enable STALL +// DIS Disable STALL +#define WDT_TEST_STALL 0x00000100 +#define WDT_TEST_STALL_BITN 8 +#define WDT_TEST_STALL_M 0x00000100 +#define WDT_TEST_STALL_S 8 +#define WDT_TEST_STALL_EN 0x00000100 +#define WDT_TEST_STALL_DIS 0x00000000 + +// Field: [0] TEST_EN +// +// The test enable bit +// +// 0: Enable external reset +// 1: Disables the generation of an external reset. Instead bit 1 of the +// INT_CAUS register is set and an interrupt is generated +// ENUMs: +// EN Test mode Enabled +// DIS Test mode Disabled +#define WDT_TEST_TEST_EN 0x00000001 +#define WDT_TEST_TEST_EN_BITN 0 +#define WDT_TEST_TEST_EN_M 0x00000001 +#define WDT_TEST_TEST_EN_S 0 +#define WDT_TEST_TEST_EN_EN 0x00000001 +#define WDT_TEST_TEST_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: WDT_O_INT_CAUS +// +//***************************************************************************** +// Field: [1] CAUSE_RESET +// +// Indicates that the cause of an interrupt was a reset generated but blocked +// due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). +#define WDT_INT_CAUS_CAUSE_RESET 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_BITN 1 +#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_S 1 + +// Field: [0] CAUSE_INTR +// +// Replica of RIS.WDTRIS +#define WDT_INT_CAUS_CAUSE_INTR 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_BITN 0 +#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_S 0 + +//***************************************************************************** +// +// Register: WDT_O_LOCK +// +//***************************************************************************** +// Field: [31:0] WDTLOCK +// +// WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers +// for write access. A write of any other value reapplies the lock, preventing +// any register updates (NOTE: TEST.TEST_EN bit is not lockable). +// +// A read of this register returns the following values: +// +// 0x0000.0000: Unlocked +// 0x0000.0001: Locked +#define WDT_LOCK_WDTLOCK_W 32 +#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF +#define WDT_LOCK_WDTLOCK_S 0 + + +#endif // __WDT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h new file mode 100644 index 0000000..528f7ee --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h @@ -0,0 +1,218 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_bt5.h +* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ +* Revision: $Revision: 18889 $ +* +* Description: RF core patch for Bluetooth 5 support ("BLE" and "BLE5" API command sets) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_BT5_H +#define _RF_PATCH_CPE_BT5_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageBt5[] = { + 0x21004059, + 0x210040a5, + 0x21004085, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0x21014805, + 0x438a6802, + 0x6b836002, + 0x6383438b, + 0x6002430a, + 0x47004801, + 0x40046000, + 0x00005b3f, + 0x490cb510, + 0x4a0c4788, + 0x5e512106, + 0xd0072900, + 0xd0052902, + 0xd0032909, + 0xd0012910, + 0xd1072911, + 0x43c92177, + 0xdd014288, + 0xdd012800, + 0x43c0207f, + 0x0000bd10, + 0x000065a9, + 0x21000380, +}; +#define _NWORD_PATCHIMAGE_BT5 37 + +#define _NWORD_PATCHCPEHD_BT5 0 + +#define _NWORD_PATCHSYS_BT5 0 + + + +#ifndef _BT5_SYSRAM_START +#define _BT5_SYSRAM_START 0x20000000 +#endif + +#ifndef _BT5_CPERAM_START +#define _BT5_CPERAM_START 0x21000000 +#endif + +#define _BT5_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _BT5_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _BT5_PATCH_TAB_OFFSET 0x03D4 +#define _BT5_IRQPATCH_OFFSET 0x0480 +#define _BT5_PATCH_VEC_OFFSET 0x404C + +#define _BT5_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _BT5_NO_PROG_STATE_VAR +static uint8_t bBt5PatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterBt5CpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_BT5 > 0) + uint32_t *pPatchVec = (uint32_t *) (_BT5_CPERAM_START + _BT5_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageBt5, sizeof(patchImageBt5)); +#endif +} + +PATCH_FUN_SPEC void enterBt5CpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_BT5 > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_BT5_CPERAM_START + _BT5_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterBt5SysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureBt5Patch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_BT5_CPERAM_START + _BT5_PATCH_TAB_OFFSET); + + + pPatchTab[76] = 0; + pPatchTab[91] = 1; + pPatchTab[79] = 2; +} + +PATCH_FUN_SPEC void applyBt5Patch(void) +{ +#ifdef _BT5_NO_PROG_STATE_VAR + enterBt5SysPatch(); + enterBt5CpePatch(); +#else + if (!bBt5PatchEntered) + { + enterBt5SysPatch(); + enterBt5CpePatch(); + bBt5PatchEntered = 1; + } +#endif + enterBt5CpeHdPatch(); + configureBt5Patch(); +} + +PATCH_FUN_SPEC void refreshBt5Patch(void) +{ + enterBt5CpeHdPatch(); + configureBt5Patch(); +} + +#ifndef _BT5_NO_PROG_STATE_VAR +PATCH_FUN_SPEC void cleanBt5Patch(void) +{ + bBt5PatchEntered = 0; +} +#endif + +PATCH_FUN_SPEC void rf_patch_cpe_bt5(void) +{ + applyBt5Patch(); +} + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_BT5_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h new file mode 100644 index 0000000..f1b9ffd --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h @@ -0,0 +1,191 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_ieee_802_15_4.h +* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ +* Revision: $Revision: 18889 $ +* +* Description: RF core patch for IEEE 802.15.4-2006 support ("IEEE" API command set) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_IEEE_802_15_4_H +#define _RF_PATCH_CPE_IEEE_802_15_4_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageIeee802154[] = { + 0x21004051, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, +}; +#define _NWORD_PATCHIMAGE_IEEE_802_15_4 12 + +#define _NWORD_PATCHCPEHD_IEEE_802_15_4 0 + +#define _NWORD_PATCHSYS_IEEE_802_15_4 0 + + + +#ifndef _IEEE_802_15_4_SYSRAM_START +#define _IEEE_802_15_4_SYSRAM_START 0x20000000 +#endif + +#ifndef _IEEE_802_15_4_CPERAM_START +#define _IEEE_802_15_4_CPERAM_START 0x21000000 +#endif + +#define _IEEE_802_15_4_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _IEEE_802_15_4_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _IEEE_802_15_4_PATCH_TAB_OFFSET 0x03D4 +#define _IEEE_802_15_4_IRQPATCH_OFFSET 0x0480 +#define _IEEE_802_15_4_PATCH_VEC_OFFSET 0x404C + +#define _IEEE_802_15_4_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _IEEE_802_15_4_NO_PROG_STATE_VAR +static uint8_t bIeee802154PatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterIeee802154CpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_IEEE_802_15_4 > 0) + uint32_t *pPatchVec = (uint32_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageIeee802154, sizeof(patchImageIeee802154)); +#endif +} + +PATCH_FUN_SPEC void enterIeee802154CpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_IEEE_802_15_4 > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterIeee802154SysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureIeee802154Patch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_TAB_OFFSET); + + + pPatchTab[76] = 0; +} + +PATCH_FUN_SPEC void applyIeee802154Patch(void) +{ +#ifdef _IEEE_802_15_4_NO_PROG_STATE_VAR + enterIeee802154SysPatch(); + enterIeee802154CpePatch(); +#else + if (!bIeee802154PatchEntered) + { + enterIeee802154SysPatch(); + enterIeee802154CpePatch(); + bIeee802154PatchEntered = 1; + } +#endif + enterIeee802154CpeHdPatch(); + configureIeee802154Patch(); +} + +PATCH_FUN_SPEC void refreshIeee802154Patch(void) +{ + enterIeee802154CpeHdPatch(); + configureIeee802154Patch(); +} + +#ifndef _IEEE_802_15_4_NO_PROG_STATE_VAR +PATCH_FUN_SPEC void cleanIeee802154Patch(void) +{ + bIeee802154PatchEntered = 0; +} +#endif + +PATCH_FUN_SPEC void rf_patch_cpe_ieee_802_15_4(void) +{ + applyIeee802154Patch(); +} + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_IEEE_802_15_4_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h new file mode 100644 index 0000000..8c741ac --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h @@ -0,0 +1,246 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_multi_protocol.h +* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ +* Revision: $Revision: 18889 $ +* +* Description: RF core patch for multi-protocol support (all available API command sets) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_MULTI_PROTOCOL_H +#define _RF_PATCH_CPE_MULTI_PROTOCOL_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageMultiProtocol[] = { + 0x21004061, + 0x210040cb, + 0x2100408d, + 0x2100410d, + 0x210040ed, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf819f000, + 0x296cb2e1, + 0x2804d00b, + 0x2806d001, + 0x490ed107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490b2002, + 0x210c780a, + 0xd0024211, + 0x22804909, + 0xb003600a, + 0xb5f0bdf0, + 0x4907b083, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000133, + 0xe000e200, + 0x00031641, + 0x00031b23, + 0x21014805, + 0x438a6802, + 0x6b836002, + 0x6383438b, + 0x6002430a, + 0x47004801, + 0x40046000, + 0x00005b3f, + 0x490cb510, + 0x4a0c4788, + 0x5e512106, + 0xd0072900, + 0xd0052902, + 0xd0032909, + 0xd0012910, + 0xd1072911, + 0x43c92177, + 0xdd014288, + 0xdd012800, + 0x43c0207f, + 0x0000bd10, + 0x000065a9, + 0x21000380, +}; +#define _NWORD_PATCHIMAGE_MULTI_PROTOCOL 63 + +#define _NWORD_PATCHCPEHD_MULTI_PROTOCOL 0 + +#define _NWORD_PATCHSYS_MULTI_PROTOCOL 0 + + + +#ifndef _MULTI_PROTOCOL_SYSRAM_START +#define _MULTI_PROTOCOL_SYSRAM_START 0x20000000 +#endif + +#ifndef _MULTI_PROTOCOL_CPERAM_START +#define _MULTI_PROTOCOL_CPERAM_START 0x21000000 +#endif + +#define _MULTI_PROTOCOL_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _MULTI_PROTOCOL_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _MULTI_PROTOCOL_PATCH_TAB_OFFSET 0x03D4 +#define _MULTI_PROTOCOL_IRQPATCH_OFFSET 0x0480 +#define _MULTI_PROTOCOL_PATCH_VEC_OFFSET 0x404C + +#define _MULTI_PROTOCOL_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _MULTI_PROTOCOL_NO_PROG_STATE_VAR +static uint8_t bMultiProtocolPatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterMultiProtocolCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_MULTI_PROTOCOL > 0) + uint32_t *pPatchVec = (uint32_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageMultiProtocol, sizeof(patchImageMultiProtocol)); +#endif +} + +PATCH_FUN_SPEC void enterMultiProtocolCpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_MULTI_PROTOCOL > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterMultiProtocolSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureMultiProtocolPatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_TAB_OFFSET); + + + pPatchTab[76] = 0; + pPatchTab[62] = 1; + pPatchTab[64] = 2; + pPatchTab[91] = 3; + pPatchTab[79] = 4; +} + +PATCH_FUN_SPEC void applyMultiProtocolPatch(void) +{ +#ifdef _MULTI_PROTOCOL_NO_PROG_STATE_VAR + enterMultiProtocolSysPatch(); + enterMultiProtocolCpePatch(); +#else + if (!bMultiProtocolPatchEntered) + { + enterMultiProtocolSysPatch(); + enterMultiProtocolCpePatch(); + bMultiProtocolPatchEntered = 1; + } +#endif + enterMultiProtocolCpeHdPatch(); + configureMultiProtocolPatch(); +} + +PATCH_FUN_SPEC void refreshMultiProtocolPatch(void) +{ + enterMultiProtocolCpeHdPatch(); + configureMultiProtocolPatch(); +} + +#ifndef _MULTI_PROTOCOL_NO_PROG_STATE_VAR +PATCH_FUN_SPEC void cleanMultiProtocolPatch(void) +{ + bMultiProtocolPatchEntered = 0; +} +#endif + +PATCH_FUN_SPEC void rf_patch_cpe_multi_protocol(void) +{ + applyMultiProtocolPatch(); +} + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_MULTI_PROTOCOL_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h new file mode 100644 index 0000000..39b058b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h @@ -0,0 +1,1452 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_multi_protocol_rtls.h +* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ +* Revision: $Revision: 18889 $ +* +* Description: RF core patch for multi-protocol support (all available API command sets) with RTLS components in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H +#define _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageMultiProtocolRtls[] = { + 0x21004631, + 0x21004683, + 0x21004075, + 0x2100486f, + 0x210040ad, + 0x21004117, + 0x210040d9, + 0x2100492d, + 0x21004139, + 0x21005349, + 0x68084908, + 0x43902221, + 0x48076008, + 0x68c34700, + 0x230260c3, + 0xd1fd1e5b, + 0x68c32210, + 0x60c34393, + 0x4770618a, + 0x40048000, + 0x00005c01, + 0x4801b430, + 0x00004700, + 0x00020efd, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf819f000, + 0x296cb2e1, + 0x2804d00b, + 0x2806d001, + 0x490ed107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490b2002, + 0x210c780a, + 0xd0024211, + 0x22804909, + 0xb003600a, + 0xb5f0bdf0, + 0x4907b083, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000133, + 0xe000e200, + 0x00031641, + 0x00031b23, + 0x21014805, + 0x438a6802, + 0x6b836002, + 0x6383438b, + 0x6002430a, + 0x47004801, + 0x40046000, + 0x00005b3f, + 0x4803b510, + 0x30106800, + 0xfe72f000, + 0x47084901, + 0x21000108, + 0x000095e3, + 0x4cffb570, + 0x5d002044, + 0x008049fe, + 0x68801840, + 0x46054780, + 0xd0112801, + 0x5d00207e, + 0xd30d2805, + 0x06002021, + 0x00897e41, + 0x7f0a1809, + 0xd0072a02, + 0x77082003, + 0x49f43480, + 0x478888a0, + 0xbd704628, + 0x77012104, + 0x700148f1, + 0xb5ffe7f4, + 0x7e934aec, + 0x49ef185b, + 0x3280600b, + 0x09897891, + 0x49edd16e, + 0x29006909, + 0x680bd06a, + 0x041bb2da, + 0x4be40e1c, + 0x7edb3360, + 0xd01b2c01, + 0x005b2410, + 0x1edb46a6, + 0x4be5469c, + 0x681b684d, + 0x00923108, + 0x1f121852, + 0x9202402b, + 0x4ae13030, + 0x93002401, + 0x60549103, + 0x26224adf, + 0x27106914, + 0x6114433c, + 0xe0302200, + 0x009b2408, + 0x1f9b46a6, + 0xc910e7e2, + 0x40634fd9, + 0x9301402b, + 0x24014623, + 0x603c0364, + 0x34404cd3, + 0x4cd26060, + 0x68643c40, + 0xd5061a24, + 0x3c804cd1, + 0x04bf6827, + 0xbf20d401, + 0x4fcbe7fa, + 0x633c9c01, + 0x44709c02, + 0xd90042a1, + 0x4cc59903, + 0x42346864, + 0x4cc3d006, + 0x68263c80, + 0x43be2702, + 0x26006026, + 0x45621c52, + 0x9c00d3d1, + 0x405c49c0, + 0x3940402c, + 0x1a12684a, + 0x48bcd4fc, + 0x48bc6304, + 0x60412100, + 0x690248bb, + 0x438a2110, + 0xbdff6102, + 0x212248b4, + 0x420a6842, + 0x4ab2d0fc, + 0x68103a80, + 0x43882102, + 0xbdff6010, + 0x4daab5f3, + 0x5d46202f, + 0xb08148b2, + 0x05806900, + 0x2e011600, + 0x1c40d002, + 0xe0001040, + 0x49ad301e, + 0x6a093140, + 0x4ba14aac, + 0x691a4351, + 0x6a1b0e09, + 0xd0222e01, + 0x01591852, + 0x316731ff, + 0x18544b9f, + 0x68d93340, + 0xb2894fa0, + 0xb2821a08, + 0x68783f40, + 0xd4fc1b00, + 0x462860da, + 0x90003060, + 0x49958381, + 0x31122050, + 0x35804788, + 0x980180a8, + 0xd0082800, + 0x990278aa, + 0xfabef000, + 0x1852e007, + 0x31ce0119, + 0x4896e7dc, + 0x99006ac0, + 0x489577c8, + 0x68407829, + 0x08c14348, + 0xd00b2e01, + 0x38134620, + 0x687a340e, + 0xd4fc1b12, + 0x0c0b4a8f, + 0xb2896193, + 0xbdfe6151, + 0x38114620, + 0xe7f23409, + 0x4c7cb570, + 0x35604625, + 0x1e407fa8, + 0xd80d2802, + 0x28006aa0, + 0x2182d004, + 0x70015d09, + 0x62a01c40, + 0x1e406a60, + 0x7fa86260, + 0x77a81cc0, + 0x28057fa8, + 0xd112d322, + 0x28026a60, + 0x497ddd08, + 0x47881e80, + 0x62611c81, + 0xd0012800, + 0xbd702001, + 0x46082100, + 0xff7af7ff, + 0xf7ff2110, + 0x486afef2, + 0x6ac13840, + 0xd0fc07c9, + 0x38804867, + 0x22026801, + 0x60014311, + 0x8ba84964, + 0x60c83140, + 0x36404626, + 0x495e7930, + 0x18400080, + 0x47806880, + 0xd1de2800, + 0x29057fa9, + 0x7fead301, + 0x29047172, + 0x7de1d3d7, + 0xd1022900, + 0x29007e21, + 0x7eead0d1, + 0x015268e1, + 0x60e11889, + 0xb570bd70, + 0x20444d4f, + 0x48535d46, + 0x3820494e, + 0x00b07ec4, + 0x68801840, + 0x4b5a4780, + 0x781a09a1, + 0xd10a4211, + 0x21ff2221, + 0x76510612, + 0x22004948, + 0x600a1f09, + 0x2101604a, + 0x212f7019, + 0x29025d49, + 0x2e31d008, + 0x07e1d003, + 0xd0032900, + 0x0861e003, + 0xe7f907c9, + 0x35802400, + 0xbd70706c, + 0x4c39b5f8, + 0x46272500, + 0x723d3760, + 0x5d00202f, + 0xd03a2802, + 0x47804845, + 0x36404626, + 0x7ff04937, + 0x62203920, + 0x43087849, + 0x48347560, + 0x38406265, + 0x2d007fc5, + 0x7d20d006, + 0x43082120, + 0x06e87520, + 0x72380ec0, + 0x7f30493a, + 0x4a3a4788, + 0xd0112d00, + 0x61c54839, + 0x20074b28, + 0x63983b40, + 0x21054d26, + 0x07806950, + 0x6868d1fc, + 0xd0f94208, + 0x30404831, + 0x63186800, + 0x28007f30, + 0x6e60d001, + 0x6be16210, + 0x47882039, + 0x20006420, + 0x482cbdf8, + 0xb5f0e7fa, + 0x20444915, + 0x2b045c43, + 0x460ad00a, + 0x78103268, + 0x28004f12, + 0x28ffd070, + 0x2b04d012, + 0xe006d003, + 0x327b460a, + 0x68cce7f3, + 0x19640145, + 0x242f60cc, + 0x2c015c64, + 0x0640d101, + 0x62480e00, + 0x701020ff, + 0x4c09202f, + 0x60200200, + 0x6a484d07, + 0x68623d40, + 0xd03f07d2, + 0xe02b220f, + 0x21000160, + 0x00025500, + 0x0000423d, + 0x21000020, + 0x40045080, + 0x210000e8, + 0x40022080, + 0x40043040, + 0xe000ed00, + 0xe000e280, + 0x400452c0, + 0x00155556, + 0x40046040, + 0x210002c0, + 0x40045180, + 0x0002175f, + 0x210004e0, + 0x00020749, + 0x00020e45, + 0x40042000, + 0x40042100, + 0x0002469d, + 0x4ec363aa, + 0x2801e003, + 0x632edd07, + 0x28001e80, + 0x6862dd1a, + 0xd1f607d2, + 0x2007e006, + 0x20ff63a8, + 0xe0116328, + 0xdd0f2800, + 0x26146862, + 0xd0b64232, + 0x7b524ab8, + 0x60220212, + 0x22084bb7, + 0x4bb7601a, + 0x6248601a, + 0xbdf02001, + 0x19c00098, + 0x64086880, + 0xbdf02000, + 0x460148b2, + 0x7bca3120, + 0x76823060, + 0x73c82002, + 0x470048af, + 0xb50049ad, + 0x71083140, + 0xd01c2831, + 0x4603dc08, + 0xfec0f000, + 0x0e13190a, + 0x0e0e150e, + 0x0e1d1b0e, + 0xd0122835, + 0xd0122836, + 0xd00a2838, + 0xd006283b, + 0x008049a3, + 0x68801840, + 0x48a2bd00, + 0x48a2bd00, + 0x48a2bd00, + 0x48a2bd00, + 0x48a2bd00, + 0x48a2bd00, + 0xb5f0bd00, + 0xb0854c98, + 0x31204621, + 0x7bce9103, + 0x5d092144, + 0xd0012907, + 0xd17e2934, + 0x35804625, + 0x2a00786a, + 0x7d21d07a, + 0xd5770689, + 0x3180498b, + 0x7f09468e, + 0xd0282e01, + 0x0f090709, + 0x702b004b, + 0x025b2301, + 0x2300469c, + 0x93029300, + 0xd0302900, + 0x4f8e0993, + 0xd00b07db, + 0x2b007f3b, + 0x23f7d001, + 0x4b8a401a, + 0x781b3320, + 0xd0012b00, + 0x401a23ef, + 0x0f5b0693, + 0xd00b2b07, + 0x07db08d3, + 0x2200d00c, + 0x4a82767a, + 0x9200321c, + 0x0909e013, + 0xe7d77029, + 0x02922201, + 0xe7f24694, + 0x07d20912, + 0x2201d008, + 0x4a7a767a, + 0x92003220, + 0x02522201, + 0xe0009202, + 0x4a772100, + 0x63d32307, + 0x4a752322, + 0x68523240, + 0xd0fa421a, + 0x6b524a72, + 0x61da4b72, + 0x693b4f72, + 0x43932210, + 0x4b71613b, + 0x0792695a, + 0x4a6fd1fc, + 0x68123240, + 0x06d370aa, + 0x1e9a0edb, + 0xd3002a13, + 0x46222302, + 0x92013260, + 0x76d33008, + 0xd0552900, + 0x7f7f4677, + 0x469600da, + 0x2a041bd2, + 0x2204da00, + 0xd0232e01, + 0x330e0093, + 0xe052e001, + 0x4e60e04e, + 0x467362b3, + 0x485a181b, + 0x434a6203, + 0x45624617, + 0x4667dd00, + 0x9902485b, + 0x99026041, + 0x1e4919c9, + 0x68016081, + 0x43112221, + 0x6a266001, + 0x62261c76, + 0x98036266, + 0x28017bc0, + 0xe00ad006, + 0x4f5000d6, + 0x62be3616, + 0xe7dd011b, + 0x494f4849, + 0xf7ff3040, + 0x2e02fc48, + 0x78aadd06, + 0x98004639, + 0xf85cf000, + 0xe00f2102, + 0x98004639, + 0xfd5cf7ff, + 0x31404946, + 0x9a016ac9, + 0x210077d1, + 0xd0002e01, + 0xf7ff2108, + 0x2103fccc, + 0x77819801, + 0xbdf0b005, + 0x21019a01, + 0x6a217791, + 0x62211c49, + 0xe0026261, + 0x34602100, + 0x4a3777a1, + 0x62912100, + 0x62084931, + 0x7bc09803, + 0xd1e92801, + 0x3040482e, + 0x06c968c1, + 0x2100d5fc, + 0x29021c49, + 0x4930dbfc, + 0xfc0bf7ff, + 0x481ee7dc, + 0x4601b510, + 0x460a3160, + 0x232f7e89, + 0x29025419, + 0x7d01d010, + 0xd5130689, + 0x29016a01, + 0x6ec1dd10, + 0x06c97849, + 0x1e8b0ec9, + 0xd8092b12, + 0x1e5b7d43, + 0xe0067543, + 0xfbfcf7ff, + 0xd0002800, + 0xbd102001, + 0x76d12100, + 0xbd102000, + 0x33804b1b, + 0x7083695b, + 0x22017042, + 0x42910252, + 0x2102dd03, + 0x71017001, + 0x21014770, + 0x47707001, + 0x0000ffff, + 0x21000048, + 0xe000e280, + 0xe000e100, + 0x21000160, + 0x00020f47, + 0x00025500, + 0x2100461d, + 0x21004517, + 0x21004489, + 0x2100442f, + 0x2100437d, + 0x21004171, + 0x21000000, + 0x40045040, + 0x40042100, + 0x400451c0, + 0x40042000, + 0x40045300, + 0x40048000, + 0x40046000, + 0x490cb510, + 0x4a0c4788, + 0x5e512106, + 0xd0072900, + 0xd0052902, + 0xd0032909, + 0xd0012910, + 0xd1072911, + 0x43c92177, + 0xdd014288, + 0xdd012800, + 0x43c0207f, + 0x0000bd10, + 0x000065a9, + 0x21000380, + 0x2500b570, + 0x614548ff, + 0xf000207d, + 0x4cfefcfd, + 0x07c06ae0, + 0x62e5d0fc, + 0xf0002082, + 0x48fbfcf5, + 0x07c96ac1, + 0x62c5d0fc, + 0x60a12101, + 0x60a56025, + 0x384048f6, + 0x60056081, + 0xbd706085, + 0x4bf4b530, + 0x68db685b, + 0xd00d2b00, + 0x189c0852, + 0x4def4aef, + 0xe0053240, + 0x079b6853, + 0x6b6bd5fc, + 0x1c405423, + 0xdbf74288, + 0xb5f7bd30, + 0x2400468e, + 0x00c9214b, + 0x49e8468c, + 0x684e4627, + 0x46254623, + 0x62544ae6, + 0x6ad24ae1, + 0x4ae307d1, + 0x68520fc9, + 0x42821b92, + 0x2701d900, + 0x6a524ae0, + 0xd006429a, + 0x684648dd, + 0x46604bde, + 0xb29d6adb, + 0x29014613, + 0x2f00d001, + 0x4ad6d0e6, + 0x6ad16ad0, + 0x0fc006c0, + 0x0fc90689, + 0x29014ed3, + 0x2801d101, + 0x210fd011, + 0x020968b0, + 0x1d404008, + 0x48cc6190, + 0x62c12100, + 0x62012101, + 0x68784fcc, + 0x99026130, + 0xd00e2902, + 0x9802e013, + 0xd1032802, + 0x684048c7, + 0x61486871, + 0x20004671, + 0xf7ff9a02, + 0x2401ff9b, + 0x6871e7ea, + 0x8d892c01, + 0x1a40d01c, + 0x48c160f0, + 0x0a2a6ac0, + 0x0a08b281, + 0xb2c91880, + 0x1889b2ea, + 0x084a0840, + 0x23ff1811, + 0x1a103301, + 0x02001a59, + 0xfc6cf000, + 0x68706170, + 0x8d828873, + 0x18d56931, + 0xe00468f0, + 0x30f01a40, + 0x6879e7e0, + 0x1a096131, + 0xd3fa42a9, + 0x21009d02, + 0xd0052d02, + 0xd1032c01, + 0x1a086931, + 0x1ac11a80, + 0x1a406930, + 0x2c0160f0, + 0x2000d002, + 0xbdfe43c0, + 0xbdfe2000, + 0x4ba6b510, + 0x2402499e, + 0x28002201, + 0x48a4d007, + 0x694861d8, + 0x61484390, + 0x43206948, + 0x48a1e006, + 0x694861d8, + 0x61484310, + 0x43a06948, + 0x499b6148, + 0x6bc83940, + 0x40184b9c, + 0x43032303, + 0x431063cb, + 0xbd1063c8, + 0x9c02b510, + 0x02240112, + 0x3c013cff, + 0x43143a10, + 0x430c1e49, + 0x61cc498b, + 0x4b8a624b, + 0x3b402202, + 0x2200605a, + 0x620a62ca, + 0x02004a87, + 0x79926852, + 0xd0022a02, + 0x61881cc0, + 0x1d00bd10, + 0x7808e7fb, + 0x62c84983, + 0x49804770, + 0x68896849, + 0xd0042900, + 0x18080840, + 0x7800497e, + 0x487a62c8, + 0x38402103, + 0x60416001, + 0x20014976, + 0x60486008, + 0xb5384770, + 0xf7ff4605, + 0x4872ffe8, + 0x62c12100, + 0x62012108, + 0x78234c71, + 0x68a09300, + 0x05004b77, + 0x78620f00, + 0xffb6f7ff, + 0xf7ff2000, + 0x6861ff91, + 0x68082d02, + 0x8dc8d100, + 0x2101462a, + 0xfef9f7ff, + 0xb5f7bd38, + 0x46154966, + 0x684a2000, + 0x46944607, + 0x6ac94960, + 0x496207ce, + 0x68490ff6, + 0x1a8a4662, + 0x428a9900, + 0x2701d900, + 0x6a4c495e, + 0xd0074284, + 0xd0012c00, + 0xe0002001, + 0xf7ff2000, + 0x4620ff69, + 0xd0012e01, + 0xd0e32f00, + 0x21004851, + 0x4a526141, + 0x4e526ad0, + 0x0fc006c0, + 0xd1032d00, + 0x685b4b50, + 0x61636874, + 0xd0012f00, + 0xd01d2800, + 0x462a2401, + 0x99012000, + 0xfea8f7ff, + 0x6ac0484b, + 0xb2810223, + 0xb2ca0a08, + 0x1a101811, + 0x02001a59, + 0xfb88f000, + 0x4a436170, + 0x61316851, + 0x79836870, + 0x432f461f, + 0x2b01d00e, + 0xe01ad014, + 0x68b0230f, + 0x4018021b, + 0x61901d40, + 0x62c14837, + 0x62012101, + 0xe7e82400, + 0x2c008d83, + 0x1ac9d002, + 0xe00731f0, + 0xe0051ac9, + 0xd1042d00, + 0x1ac98d83, + 0x310531ff, + 0x8d8160f1, + 0x23008877, + 0x19c9468c, + 0x68f06932, + 0x4a2ce002, + 0x61326852, + 0x428a1a12, + 0x2d00d3f9, + 0x2c00d006, + 0x6931d004, + 0x46601a09, + 0x1bc31a08, + 0x1ac06930, + 0x2c0060f0, + 0x2000d001, + 0x2000bdfe, + 0xbdfe43c0, + 0x4605b538, + 0xff39f7ff, + 0x2100481a, + 0x210862c1, + 0x4c1a6201, + 0x93007823, + 0x4b2068a0, + 0x0f000500, + 0xf7ff7862, + 0x2000ff07, + 0xfee2f7ff, + 0x2d006861, + 0xd1006808, + 0x462a8dc8, + 0xf7ff2101, + 0xbd38ff52, + 0x4c0db530, + 0x62e52500, + 0x3a100112, + 0x430a1e49, + 0x626361e2, + 0x1c800200, + 0x480961a0, + 0x60012101, + 0x61456942, + 0x32404a06, + 0x68406011, + 0xe0173028, + 0x40041100, + 0x40046000, + 0x40045040, + 0x210053e8, + 0x40043000, + 0x40045300, + 0x400451c0, + 0x40044040, + 0x08180532, + 0x0818070e, + 0xfff000ff, + 0x0000aaaa, + 0x318049ff, + 0xbd306008, + 0x4605b538, + 0xfee5f7ff, + 0x210048fc, + 0x210662c1, + 0x4cfb6201, + 0x78232108, + 0x68a09300, + 0x05004bf9, + 0x78620f00, + 0xffb8f7ff, + 0x48f749f8, + 0x200161c8, + 0xfe8af7ff, + 0x462a6860, + 0x21016800, + 0xfefdf7ff, + 0xb530bd38, + 0x4bf24df2, + 0x35804cf2, + 0xd00e2a40, + 0x58420089, + 0x625a0c12, + 0xb2925842, + 0x1808629a, + 0x0c096841, + 0x684062a1, + 0x6328b280, + 0x00c9bd30, + 0x0c125842, + 0x584262da, + 0x631ab292, + 0x68411808, + 0x62590c09, + 0xb2896841, + 0x68816299, + 0x49e00c0a, + 0x634a31c0, + 0xb2926882, + 0x68c1638a, + 0x62a10c09, + 0xe7e168c0, + 0x4606b5f0, + 0x2080b089, + 0xfa8ef000, + 0x2500b662, + 0x204f4cd2, + 0x60e56066, + 0x00c049d6, + 0x47889501, + 0x68606125, + 0x290079c1, + 0x21ffd001, + 0x30203101, + 0x4acf60a1, + 0x62117901, + 0x21207902, + 0xd1002a00, + 0x70212140, + 0x21027980, + 0xd1002800, + 0x48ca2101, + 0x47807061, + 0x49c06860, + 0x79403020, + 0x62c83180, + 0x478048c6, + 0x80602000, + 0x384048bf, + 0x48c56bc0, + 0x610149c3, + 0x90002000, + 0x684849b8, + 0x24003020, + 0x46267c40, + 0x46259405, + 0x90029403, + 0x48b3e20c, + 0x4ab02700, + 0x68506147, + 0x31504601, + 0x48ade001, + 0x42886840, + 0x48b8d3fb, + 0x48b64780, + 0x48b76147, + 0x7ac07ac1, + 0x0fc907c9, + 0x40102202, + 0xd0024301, + 0xb00948b3, + 0x48a5bdf0, + 0x80412100, + 0x97076847, + 0x7cf93720, + 0x90060860, + 0xfa32f000, + 0xd1142900, + 0x42a09805, + 0x9802d011, + 0xd03b2800, + 0x07c09902, + 0x0fc00849, + 0x28009102, + 0x7cb8d002, + 0x90024048, + 0x98027c39, + 0xfa1cf000, + 0x9807460d, + 0x6b409405, + 0x5bc200ef, + 0x428a9900, + 0x1db9d02e, + 0x1d395a43, + 0x5c439300, + 0x5c421cb9, + 0x5c411cf9, + 0xf000200e, + 0x488afa0d, + 0x68402201, + 0x6b402300, + 0x5bc04611, + 0xf0000400, + 0x488dfa09, + 0x48924780, + 0x29037801, + 0x4882d1fc, + 0x8f096841, + 0x497e8041, + 0x46026848, + 0xe0073238, + 0x7c381c6d, + 0x42a8b2ed, + 0x2500d8cd, + 0x6848e7cb, + 0xd3fc4290, + 0x68404878, + 0x5bc06b40, + 0x48799000, + 0x68813840, + 0xf000207e, + 0x4873f9eb, + 0x6a386847, + 0xd0062800, + 0x46200041, + 0xf9d0f000, + 0xd0052900, + 0x496de014, + 0x780a69b8, + 0xe0334621, + 0xd00b2c00, + 0x30204638, + 0x07ca7fc1, + 0x2201d018, + 0x43917782, + 0x496f77c1, + 0x608802d0, + 0x900469b8, + 0x90076a38, + 0x46200041, + 0xf9b2f000, + 0x42819807, + 0x2c00d113, + 0x4638d00f, + 0x7fc13020, + 0xd401078a, + 0xe7664869, + 0x77822202, + 0x401122fd, + 0x200177c1, + 0x02c04960, + 0x69f86088, + 0x46209004, + 0xf0006a39, + 0x4852f997, + 0x98047802, + 0xfec1f7ff, + 0xd1042c00, + 0x6840484e, + 0x28027980, + 0x9806d00c, + 0x484b9001, + 0x79806840, + 0xd0072801, + 0x28004f48, + 0x2802d058, + 0xe078d07e, + 0xe12f2402, + 0xf7ff4620, + 0xb280fe87, + 0x48414684, + 0x6ac33040, + 0x68504a40, + 0x98016907, + 0x1d4800c1, + 0x6850543b, + 0x1d086903, + 0x4660541d, + 0xd00e2800, + 0x20006852, + 0x691243c0, + 0x50502c00, + 0xe002d167, + 0xb2a41ca4, + 0x9803e053, + 0x90031c40, + 0x6857e04f, + 0x5dc02027, + 0xd0012801, + 0xe0146950, + 0x30804832, + 0x071b6a83, + 0x61530f1b, + 0x05806a80, + 0x2b070e80, + 0x3b10dd01, + 0x281f6153, + 0x3840dd01, + 0x0100b200, + 0x010018c0, + 0x30ff6150, + 0x30014b33, + 0xd3014298, + 0x61502000, + 0x30804824, + 0x69536a40, + 0x18c00200, + 0x5058693b, + 0xb2816950, + 0xe0ca207f, + 0xf7ff4620, + 0xb281fddf, + 0x30404817, + 0x48176ac3, + 0x69076840, + 0x00c09801, + 0x54bb1d42, + 0x1d034a13, + 0x29006852, + 0x54d56912, + 0x4910d04e, + 0x68492200, + 0x690943d2, + 0x500a2c00, + 0x1c76d0af, + 0x2c01b2b6, + 0xf7ffd8a8, + 0x4809fbf5, + 0x8d386847, + 0xe00042b0, + 0xd303e040, + 0x99038d7a, + 0xd27e428a, + 0x42884914, + 0xe054e028, + 0x40043000, + 0x40046000, + 0x210053e8, + 0x0000aaaa, + 0x08180532, + 0x40044040, + 0x40045140, + 0x40045300, + 0x0000424f, + 0x00009083, + 0x00004be3, + 0x0000c210, + 0x40041100, + 0x00000de5, + 0x21000128, + 0x04040003, + 0x210002e4, + 0x04060003, + 0x00000201, + 0x0000ffff, + 0x8d78d102, + 0xd06f4288, + 0x484d2101, + 0x60810449, + 0xe684484c, + 0x21004a4c, + 0x69126852, + 0xe75f5011, + 0xf7ff4620, + 0xb282fcc6, + 0x46946878, + 0x98016903, + 0x00c04639, + 0x549d1d02, + 0x6ad34a44, + 0x6917687a, + 0x54bb1d42, + 0x2a004662, + 0x6849d00a, + 0x43d22200, + 0x2c026909, + 0xd800500a, + 0x1c76e745, + 0xe73fb2b6, + 0x68494939, + 0x3120468c, + 0x290179c9, + 0x4938d125, + 0x07136a8a, + 0x0f1b4a37, + 0x6a896997, + 0x0f3f073f, + 0x69920589, + 0x05920e89, + 0x2b070e92, + 0x3b10dd00, + 0xdd002f07, + 0x291f3f10, + 0x3940dd01, + 0x2a1fb209, + 0x3a40dd03, + 0xe01fe000, + 0x0109b212, + 0x19c918c9, + 0x18890112, + 0x4924010a, + 0x4923614a, + 0x694a4b26, + 0x320132ff, + 0xd301429a, + 0x614a2200, + 0x6a524a20, + 0x0212694b, + 0x466218d3, + 0x50136912, + 0xb2816948, + 0xf0002083, + 0xe6fbf873, + 0x98018fb9, + 0xf856f000, + 0xd1072900, + 0x28009801, + 0x8778d004, + 0x48102101, + 0x608103c9, + 0x68414810, + 0x42a18889, + 0xe5ecd900, + 0x480b2101, + 0x60810409, + 0x1e49480b, + 0x8d026840, + 0xd103428a, + 0x42888d40, + 0xe5d3d100, + 0x98014906, + 0x87486849, + 0xf0002081, + 0x2000f825, + 0x0000e5ef, + 0x40041100, + 0x04030003, + 0x210053e8, + 0x40046040, + 0x400451c0, + 0x40045080, + 0x00000201, + 0x49068800, + 0xd1064288, + 0x21004805, + 0x49058501, + 0x20016241, + 0x20824770, + 0x00004770, + 0x00006801, + 0x21000108, + 0x21004159, + 0x4801b403, + 0xbd019001, + 0x00003cc3, + 0x4801b403, + 0xbd019001, + 0x0000937d, + 0x4801b403, + 0xbd019001, + 0x00009361, + 0x4801b403, + 0xbd019001, + 0x0000867b, + 0x4801b403, + 0xbd019001, + 0x000049a3, + 0x4801b403, + 0xbd019001, + 0x00003c8f, + 0x4801b403, + 0xbd019001, + 0x00003ca9, + 0x4674b430, + 0x78251e64, + 0x42ab1c64, + 0x461dd200, + 0x005b5d63, + 0xbc3018e3, + 0x00004718, + 0x08180532, + 0x0818070e, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; +#define _NWORD_PATCHIMAGE_MULTI_PROTOCOL_RTLS 1261 + +CPE_PATCH_TYPE patchCpeHd[] = { + 0x00000000, +}; +#define _NWORD_PATCHCPEHD_MULTI_PROTOCOL_RTLS 1 + +#define _NWORD_PATCHSYS_MULTI_PROTOCOL_RTLS 0 + + + +#ifndef _MULTI_PROTOCOL_RTLS_SYSRAM_START +#define _MULTI_PROTOCOL_RTLS_SYSRAM_START 0x20000000 +#endif + +#ifndef _MULTI_PROTOCOL_RTLS_CPERAM_START +#define _MULTI_PROTOCOL_RTLS_CPERAM_START 0x21000000 +#endif + +#define _MULTI_PROTOCOL_RTLS_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _MULTI_PROTOCOL_RTLS_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _MULTI_PROTOCOL_RTLS_PATCH_TAB_OFFSET 0x03D4 +#define _MULTI_PROTOCOL_RTLS_IRQPATCH_OFFSET 0x0480 +#define _MULTI_PROTOCOL_RTLS_PATCH_VEC_OFFSET 0x404C + +#define _MULTI_PROTOCOL_RTLS_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR +static uint8_t bMultiProtocolRtlsPatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterMultiProtocolRtlsCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_MULTI_PROTOCOL_RTLS > 0) + uint32_t *pPatchVec = (uint32_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageMultiProtocolRtls, sizeof(patchImageMultiProtocolRtls)); +#endif +} + +PATCH_FUN_SPEC void enterMultiProtocolRtlsCpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_MULTI_PROTOCOL_RTLS > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterMultiProtocolRtlsSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureMultiProtocolRtlsPatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_TAB_OFFSET); + + + pPatchTab[1] = 0; + pPatchTab[18] = 1; + pPatchTab[81] = 2; + pPatchTab[26] = 3; + pPatchTab[76] = 4; + pPatchTab[62] = 5; + pPatchTab[64] = 6; + pPatchTab[91] = 7; + pPatchTab[79] = 8; + pPatchTab[168] = 9; +} + +PATCH_FUN_SPEC void applyMultiProtocolRtlsPatch(void) +{ +#ifdef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR + enterMultiProtocolRtlsSysPatch(); + enterMultiProtocolRtlsCpePatch(); +#else + if (!bMultiProtocolRtlsPatchEntered) + { + enterMultiProtocolRtlsSysPatch(); + enterMultiProtocolRtlsCpePatch(); + bMultiProtocolRtlsPatchEntered = 1; + } +#endif + enterMultiProtocolRtlsCpeHdPatch(); + configureMultiProtocolRtlsPatch(); +} + +PATCH_FUN_SPEC void refreshMultiProtocolRtlsPatch(void) +{ + enterMultiProtocolRtlsCpeHdPatch(); + configureMultiProtocolRtlsPatch(); +} + +#ifndef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR +PATCH_FUN_SPEC void cleanMultiProtocolRtlsPatch(void) +{ + bMultiProtocolRtlsPatchEntered = 0; +} +#endif + +PATCH_FUN_SPEC void rf_patch_cpe_multi_protocol_rtls(void) +{ + applyMultiProtocolRtlsPatch(); +} + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h new file mode 100644 index 0000000..0b27e83 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h @@ -0,0 +1,219 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_prop.h +* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ +* Revision: $Revision: 18889 $ +* +* Description: RF core patch for proprietary radio support ("PROP" API command set) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_PROP_H +#define _RF_PATCH_CPE_PROP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageProp[] = { + 0x21004059, + 0x210040c3, + 0x21004085, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf819f000, + 0x296cb2e1, + 0x2804d00b, + 0x2806d001, + 0x490ed107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490b2002, + 0x210c780a, + 0xd0024211, + 0x22804909, + 0xb003600a, + 0xb5f0bdf0, + 0x4907b083, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000133, + 0xe000e200, + 0x00031641, + 0x00031b23, +}; +#define _NWORD_PATCHIMAGE_PROP 38 + +#define _NWORD_PATCHCPEHD_PROP 0 + +#define _NWORD_PATCHSYS_PROP 0 + + + +#ifndef _PROP_SYSRAM_START +#define _PROP_SYSRAM_START 0x20000000 +#endif + +#ifndef _PROP_CPERAM_START +#define _PROP_CPERAM_START 0x21000000 +#endif + +#define _PROP_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _PROP_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _PROP_PATCH_TAB_OFFSET 0x03D4 +#define _PROP_IRQPATCH_OFFSET 0x0480 +#define _PROP_PATCH_VEC_OFFSET 0x404C + +#define _PROP_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _PROP_NO_PROG_STATE_VAR +static uint8_t bPropPatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterPropCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_PROP > 0) + uint32_t *pPatchVec = (uint32_t *) (_PROP_CPERAM_START + _PROP_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageProp, sizeof(patchImageProp)); +#endif +} + +PATCH_FUN_SPEC void enterPropCpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_PROP > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_PROP_CPERAM_START + _PROP_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterPropSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configurePropPatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_PROP_CPERAM_START + _PROP_PATCH_TAB_OFFSET); + + + pPatchTab[76] = 0; + pPatchTab[62] = 1; + pPatchTab[64] = 2; +} + +PATCH_FUN_SPEC void applyPropPatch(void) +{ +#ifdef _PROP_NO_PROG_STATE_VAR + enterPropSysPatch(); + enterPropCpePatch(); +#else + if (!bPropPatchEntered) + { + enterPropSysPatch(); + enterPropCpePatch(); + bPropPatchEntered = 1; + } +#endif + enterPropCpeHdPatch(); + configurePropPatch(); +} + +PATCH_FUN_SPEC void refreshPropPatch(void) +{ + enterPropCpeHdPatch(); + configurePropPatch(); +} + +#ifndef _PROP_NO_PROG_STATE_VAR +PATCH_FUN_SPEC void cleanPropPatch(void) +{ + bPropPatchEntered = 0; +} +#endif + +PATCH_FUN_SPEC void rf_patch_cpe_prop(void) +{ + applyPropPatch(); +} + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_PROP_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h new file mode 100644 index 0000000..da5407e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h @@ -0,0 +1,438 @@ +/****************************************************************************** +* Filename: rf_patch_mce_iqdump.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for IQ-dump support in CC13x2 PG2.1 and CC26x2 PG2.1 +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_IQDUMP_H +#define _RF_PATCH_MCE_IQDUMP_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchIqdumpMce[337] = { + 0x2fcf6030, + 0x00013f9d, + 0xff00003f, + 0x07ff0fff, + 0x0300f800, + 0x00068080, + 0x00170003, + 0x00003d1f, + 0x08000000, + 0x0000000f, + 0x00000387, + 0x00434074, + 0x00828000, + 0x06f00080, + 0x091e0000, + 0x00540510, + 0x00000007, + 0x00505014, + 0xc02f0000, + 0x017f0c30, + 0x00000000, + 0x00000000, + 0x00000000, + 0x0000aa00, + 0x66957223, + 0xa4e5a35d, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72917391, + 0xffc0b008, + 0xa0089010, + 0x720e720d, + 0x7210720f, + 0x7100b0d0, + 0xa0d0b110, + 0x8162721b, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x60816080, + 0x610b60fd, + 0x60806080, + 0x60806080, + 0x60816080, + 0x61af60fd, + 0x60806080, + 0x60806080, + 0x60816080, + 0x611b60fd, + 0x60806080, + 0x60806080, + 0x60816080, + 0x61cb60fd, + 0x60806080, + 0x60806080, + 0x60816080, + 0x615360fd, + 0x72231210, + 0x73127311, + 0x81b17313, + 0x91b00010, + 0x6044b070, + 0xc0306076, + 0xc0c1669b, + 0xc4e0c2b2, + 0x6f131820, + 0x16116e23, + 0x68871612, + 0x99c07830, + 0x948078a0, + 0xc4f29490, + 0x1820c750, + 0x12034099, + 0x16126e23, + 0x78b06896, + 0x72639990, + 0x6076b63c, + 0x96408190, + 0x39808170, + 0x10012a70, + 0x84a21611, + 0xc0f384b4, + 0xc200c0f5, + 0x40c21c01, + 0x1c10c100, + 0x4cba40b8, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60c268b5, + 0x60c213f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68c03914, + 0x7100b0e8, + 0xa0e8b128, + 0xb910b230, + 0x99308990, + 0xb0d1b111, + 0xb0027100, + 0xb111b012, + 0x7291a0d1, + 0xb003b630, + 0x722cb013, + 0x7100b0e0, + 0x8170b120, + 0x710092c0, + 0x8170b120, + 0x44db22f0, + 0x1c0313f0, + 0x92c340e7, + 0x71009642, + 0x92c5b120, + 0x71009644, + 0xb0e0b120, + 0x7000a630, + 0xc030a0e1, + 0xc0409910, + 0xb1119930, + 0x7100b0d1, + 0xa0d1b111, + 0xa0037291, + 0xa230a002, + 0x73117000, + 0xc0407312, + 0xc100669b, + 0x649e91f0, + 0xb113b633, + 0x7100b0d3, + 0x64eea0d3, + 0xa0d26076, + 0xa0f3a0f0, + 0x73127311, + 0xc050660f, + 0xb0d2669b, + 0x7100c035, + 0xba389b75, + 0xb112b074, + 0xa0d26115, + 0xa0f3a0f0, + 0x73127311, + 0xc18b660f, + 0x91e0c000, + 0x1218120c, + 0x787d786a, + 0x10a9788e, + 0xb0d2b074, + 0xb112c020, + 0x692d7100, + 0x669bc060, + 0xb112c035, + 0x9b757100, + 0x65a48bf0, + 0x22018ca1, + 0x10804140, + 0x453f1ca8, + 0x16181208, + 0x8c00659b, + 0x8ca165a4, + 0x414b2201, + 0x1a191090, + 0x454b1e09, + 0x659b10a9, + 0x1e048184, + 0x14bc4133, + 0x4e7e1c4c, + 0xa0d26133, + 0xa0f3a0f0, + 0x73127311, + 0x721e660f, + 0x1205120c, + 0xb0d2b074, + 0xb112c020, + 0x695f7100, + 0x669bc070, + 0x89ce789d, + 0x7100b112, + 0x22008c90, + 0x8230416f, + 0x456f2210, + 0x9a3db231, + 0x31828ab2, + 0x8af03d82, + 0x3d803180, + 0x063e1802, + 0x41911e0e, + 0x41831e2e, + 0x418a1e3e, + 0x14261056, + 0x10653d16, + 0x10566192, + 0x18563126, + 0x3d261426, + 0x61921065, + 0x31361056, + 0x14261856, + 0x10653d36, + 0x10266192, + 0x91c63976, + 0x1e048184, + 0x161c4166, + 0x4e7e1c4c, + 0x10016166, + 0x91c1c0b0, + 0x10003911, + 0x10001000, + 0x7000699d, + 0x3d303130, + 0x4dab1cd0, + 0x49ad1ce0, + 0x10d07000, + 0x10e07000, + 0xc0807000, + 0xa0d2669b, + 0xa0f3a0f0, + 0x73127311, + 0xb130660f, + 0x7100b0f0, + 0x220080b0, + 0x61b945be, + 0xc090b231, + 0xb130669b, + 0xb0d2a0f0, + 0x7100c035, + 0xba389b75, + 0xb112b074, + 0xc0a061c5, + 0xa0d2669b, + 0xa0f3a0f0, + 0x73127311, + 0xc18b660f, + 0x91e0c000, + 0x1218120c, + 0x787d786a, + 0x10a9788e, + 0xb0f0b130, + 0x80b07100, + 0x45e32200, + 0xb07461de, + 0xc0b0b231, + 0xb130669b, + 0xb0d2a0f0, + 0xb112c020, + 0x69eb7100, + 0xb112c035, + 0x9b757100, + 0x65a48bf0, + 0x22018ca1, + 0x108041fc, + 0x45fb1ca8, + 0x16181208, + 0x8c00659b, + 0x8ca165a4, + 0x42072201, + 0x1a191090, + 0x46071e09, + 0x659b10a9, + 0x1e048184, + 0x14bc41ef, + 0x4e7e1c4c, + 0x824061ef, + 0x46172230, + 0x7100b0d5, + 0xa0d5b115, + 0xc0c0620f, + 0xb118669b, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x78428440, + 0x81730420, + 0x2a733983, + 0xc1f294e3, + 0x31621832, + 0x31511021, + 0x00200012, + 0x10309440, + 0x39301610, + 0x42352210, + 0x31501220, + 0x31801003, + 0x93801630, + 0x12041202, + 0x42472273, + 0x997084a0, + 0x1a828982, + 0x997084c0, + 0x1a848984, + 0x22636249, + 0x84b04254, + 0x89809970, + 0x14021a80, + 0x997084d0, + 0x1a808980, + 0x62601404, + 0x785184b0, + 0x99700410, + 0x1a428982, + 0x785184d0, + 0x99700410, + 0x1a448984, + 0x31543152, + 0x06333963, + 0x38321613, + 0x31823834, + 0x31843982, + 0x97220042, + 0x959084a0, + 0x95a084b0, + 0x95b084c0, + 0x95c084d0, + 0x90307810, + 0x78209050, + 0x90609040, + 0xcd90b235, + 0x70009170, + 0xb112a235, + 0xa0d27100, + 0xba3cb112, + 0x8b5481b0, + 0x31843924, + 0x91b40004, + 0x669bc0d0, + 0x72917391, + 0x72066695, + 0x72047202, + 0x73067305, + 0x86306076, + 0x3151c801, + 0x96300410, + 0x9a007000, + 0x220089f0, + 0xb9e0469c, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_mce_iqdump(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 337; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchIqdumpMce[i]; + } +#else + const uint32_t *pS = patchIqdumpMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 42; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + *pD++ = t1; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h new file mode 100644 index 0000000..264ba4f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h @@ -0,0 +1,609 @@ +/****************************************************************************** +* Filename: rf_patch_mce_tof.h +* Revised: $Date: 2019-01-31 15:04:59 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18843 $ +* +* Description: RF core MCE patch for time of flight 2Mbps PHY for CC13x2 and CC26x2 +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_TOF_H +#define _RF_PATCH_MCE_TOF_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchTofMce[506] = { + 0x0003605b, + 0x00f1000f, + 0x00000000, + 0x000c8000, + 0x00000000, + 0x0c650000, + 0x80000000, + 0x00800010, + 0x00000000, + 0x0594091e, + 0x00000350, + 0x7c200000, + 0x000000c2, + 0x34340013, + 0x0003005a, + 0x00000032, + 0xfe6b2840, + 0xdeade8ca, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x07d00011, + 0x6fdd2fea, + 0x0fb00ff0, + 0xf80f0003, + 0x007f7f30, + 0x3434001f, + 0x8010005a, + 0x01900000, + 0x40000800, + 0xc0300c65, + 0x722367ee, + 0xa35d7263, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72917391, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720d9001, + 0x720f720e, + 0xb0d07210, + 0xc0407100, + 0xa0d067ee, + 0x721bb110, + 0x10208162, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60936c01, + 0x60c260a4, + 0x6219617b, + 0x60936093, + 0x60936093, + 0x60c260a4, + 0x6219617b, + 0x60936093, + 0x60976093, + 0x12206095, + 0xc050609a, + 0x121267ee, + 0x73117223, + 0x73137312, + 0x81b17314, + 0x91b20012, + 0x6073b070, + 0xc2b2c011, + 0x1820c710, + 0x6e236f13, + 0x16121611, + 0x7d7068a8, + 0xc0229990, + 0x39818161, + 0xd0601812, + 0x67ee9a12, + 0x40971e01, + 0x99907d80, + 0x93807d50, + 0x93307d60, + 0x93007d90, + 0x6097b360, + 0xc07067e5, + 0x677e67ee, + 0x91f0c070, + 0x670bb750, + 0xb233b914, + 0xa750672d, + 0x95b488d4, + 0x95c488e4, + 0x95948ca4, + 0x95a487c4, + 0x2a007cb0, + 0x88d49060, + 0x88e495d4, + 0xc0f495e4, + 0x91449134, + 0x22008c80, + 0xb0f040e5, + 0xb0f6b130, + 0xb0d5b0d0, + 0xb110b136, + 0xb140b100, + 0x73137314, + 0x2a007cb0, + 0xc0f19060, + 0x40f51e0e, + 0x99311611, + 0xc037b912, + 0xb115b041, + 0xa910c031, + 0xb0737100, + 0xba3eb910, + 0x22008090, + 0x80b24574, + 0x45182262, + 0x220280c2, + 0xb061410b, + 0x2250b140, + 0x824040f9, + 0x45152200, + 0x40f9220f, + 0x679e100f, + 0x100f60f9, + 0x60f967b4, + 0xb234a913, + 0x93acba39, + 0xa0d58462, + 0xb0d1720f, + 0x7100b111, + 0xb1119937, + 0xb35d7100, + 0x9930c3f0, + 0xc0d0b074, + 0x894193f0, + 0x67bf9791, + 0x14018941, + 0x7100b111, + 0xba3aba3b, + 0xc210b078, + 0xa2329930, + 0xb111b235, + 0xa35d7100, + 0x7291b06e, + 0x8af2a0d1, + 0x3d823182, + 0x67eec080, + 0x8c528c33, + 0x8c441423, + 0x14248c62, + 0x06f28b32, + 0x31418b21, + 0x97a20012, + 0x0424cff2, + 0x31433143, + 0x97b40034, + 0x6957c8f0, + 0xb130b235, + 0xb136a0f0, + 0xb140a0f6, + 0xb914a100, + 0xa7507291, + 0xa002a003, + 0x9010c7c0, + 0x72047203, + 0x73067305, + 0xa23267e5, + 0x8242b235, + 0x456b1e02, + 0xc0907223, + 0x609767ee, + 0xa232b235, + 0xd0a08942, + 0x67ee9a12, + 0x67e56159, + 0x677ec00f, + 0x91f0c070, + 0xc0b0670b, + 0xb01367ee, + 0x22008c80, + 0xb0f04189, + 0xb0f6b130, + 0xb0d5b0d0, + 0xb136b111, + 0x72917313, + 0xc0e1b912, + 0x41951e0e, + 0x99311611, + 0xb041c037, + 0xc031b232, + 0xb115a910, + 0xb0737100, + 0xba3eb910, + 0x22008090, + 0x80b24614, + 0x45b32262, + 0x41992250, + 0x22008240, + 0x220f45b0, + 0x100f4199, + 0x6199679e, + 0x67b4100f, + 0xb9136199, + 0xba39b234, + 0xa0d593ac, + 0x7313720f, + 0x73147210, + 0x264081b0, + 0xb0d191b0, + 0x7100b111, + 0x9937b041, + 0x7100b111, + 0xc3f0b35d, + 0xb0749930, + 0x93f0c0d0, + 0x7100b111, + 0xc210b078, + 0xa2329930, + 0x7100b111, + 0xb06ea35d, + 0xa0d1a910, + 0x899167bf, + 0x81a01401, + 0x99311401, + 0xb0d6b116, + 0xb1167100, + 0x8090a0d6, + 0x46142200, + 0x88d4b012, + 0x88e495b4, + 0x8ca495c4, + 0x87c49594, + 0x729195a4, + 0x2a208230, + 0x92302630, + 0xc070672d, + 0x8af287b1, + 0x3d823182, + 0x69fbc310, + 0xb111b064, + 0xa0f6b136, + 0xa0f0b130, + 0x8242b235, + 0x46021e02, + 0x7291b914, + 0xa002a003, + 0x9010c7c0, + 0x72047203, + 0x73067305, + 0x67eec0c0, + 0x609767e5, + 0x67eec0d0, + 0x7291b235, + 0x677e6202, + 0xc070c00b, + 0x670b91f0, + 0x67eec0e0, + 0x727ab914, + 0xb0137226, + 0x73147313, + 0x8c8072c9, + 0x422d2200, + 0xb130b0f0, + 0x85b06231, + 0x95d085c1, + 0xb10095e1, + 0xb110b140, + 0xb0f6b064, + 0xb0d5b0d0, + 0x7313b136, + 0xb041b061, + 0x42411e1b, + 0xb9127291, + 0xc13772c9, + 0x1e0ec070, + 0x16104247, + 0x9930c0b7, + 0xb115b232, + 0xa910c031, + 0xb0737100, + 0xba3eb910, + 0x22008090, + 0x80b24705, + 0x46682262, + 0x220280c2, + 0xb061425b, + 0x2250b140, + 0x82404249, + 0x46652200, + 0x4249220f, + 0x679e100f, + 0x100f6249, + 0x624967b4, + 0x1e1bb234, + 0xa9154285, + 0xb913b916, + 0x8b33ba3b, + 0x8b2406f3, + 0x00433144, + 0x8c3397a3, + 0x14038c50, + 0x8c448c60, + 0x31431404, + 0x00343143, + 0x81b097b4, + 0x91b02650, + 0x67eec0f0, + 0xa91362bf, + 0x264081b0, + 0x993791b0, + 0x93acba39, + 0x720fa0d5, + 0xb111b0d1, + 0x7100b111, + 0xc3e0b35d, + 0xb0749930, + 0x93f0c0d0, + 0x97918941, + 0xb11167bf, + 0xb0787100, + 0x9930c210, + 0xb235a232, + 0x7100b111, + 0xb06ea35d, + 0xa0d17291, + 0x31828af2, + 0xba3b3d82, + 0x06f38b33, + 0x31448b24, + 0x92630043, + 0x8c508c33, + 0x8c601403, + 0x14048c44, + 0x31433143, + 0x97b40034, + 0x6abdc8f0, + 0xbc9062e3, + 0x95b488d4, + 0x95c488e4, + 0x95948ca4, + 0x95a487c4, + 0x85b0c01b, + 0x95d085c1, + 0x731195e1, + 0x73137312, + 0xb1007314, + 0xb0f6b140, + 0xb110b136, + 0xa232b064, + 0x22628242, + 0x722342d7, + 0xb115b064, + 0xc410b232, + 0x679e6ae0, + 0xb2356249, + 0xa100b140, + 0xa0f6b136, + 0x7291b914, + 0xa003a750, + 0xc7c0a002, + 0x72039010, + 0x73057204, + 0x73117306, + 0x73137312, + 0x720f7314, + 0x7210720d, + 0x7223720e, + 0xb235a232, + 0x1e028242, + 0x722346fc, + 0x67eec100, + 0xc1106097, + 0xb23567ee, + 0x8942a232, + 0x824262e4, + 0x430b2212, + 0xb016b006, + 0xb002b012, + 0xb014b004, + 0x90307ca0, + 0x7cb09050, + 0x90609040, + 0x73127311, + 0x73147313, + 0x720e720d, + 0x7210720f, + 0xb0e1b121, + 0xb0727100, + 0xd680a0e1, + 0x679e6b28, + 0x93f0c090, + 0xbc907000, + 0x9930c040, + 0xb910b911, + 0xb111b0d1, + 0x72917100, + 0xb111a0d1, + 0x9635722c, + 0xc0f38c82, + 0xb013b003, + 0x92c08170, + 0x96408190, + 0xb120b0e0, + 0x22027100, + 0x85b04750, + 0x92c39640, + 0x7100b120, + 0x964085c0, + 0x7100b120, + 0x96408590, + 0xb12092c3, + 0x85a07100, + 0xb1209640, + 0x8cb07100, + 0x0410cff1, + 0xb1209640, + 0x96367100, + 0x9930c040, + 0xb910b911, + 0xb111b0d1, + 0xb120a0e0, + 0x72917100, + 0xb111a0d1, + 0x1e108750, + 0xb2354371, + 0xa9156378, + 0xb913b916, + 0x2a308230, + 0x92302620, + 0x6b79c090, + 0xc120ac90, + 0x700067ee, + 0x721b7223, + 0x92c0c0f0, + 0xc1f1722f, + 0xc01592d1, + 0x7c977c86, + 0x8c807ccc, + 0x43912200, + 0x94407cf0, + 0x94607d10, + 0x7d206393, + 0xac909440, + 0xc1009636, + 0x816e91e0, + 0xc01d398e, + 0x439d1e0e, + 0x7000c03d, + 0x726a7269, + 0xb0537ce2, + 0xc76093a2, + 0x73a36ba4, + 0x96908a40, + 0x96a18a51, + 0x7cd093a6, + 0x8a4393a0, + 0x31338a54, + 0x31343d33, + 0x70003d34, + 0x8a439a31, + 0x31338a54, + 0x31343d63, + 0x96933d64, + 0xb05396a4, + 0x1e0e7000, + 0x8c3143d6, + 0x18108c40, + 0xc0024fd0, + 0x161110d1, + 0x16201812, + 0x1c203d20, + 0x10204fe4, + 0x63e41610, + 0x3d201620, + 0x4be41cd0, + 0x63e410d0, + 0xc082c000, + 0x8c448c33, + 0x1c241834, + 0x14424fe0, + 0x63e44be2, + 0x63e410d0, + 0x18d0c000, + 0x720d7000, + 0x720f720e, + 0x73117210, + 0x73137312, + 0x70007314, + 0x89f09a00, + 0x47ef2200, + 0x7000b9e0 +}; + +PATCH_FUN_SPEC void rf_patch_mce_tof(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 506; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchTofMce[i]; + } +#else + const uint32_t *pS = patchTofMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 63; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + *pD++ = t1; + *pD++ = t2; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h new file mode 100644 index 0000000..12f516d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h @@ -0,0 +1,571 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_tof.h +* Revised: $Date: 2019-01-31 15:04:59 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18843 $ +* +* Description: RF core RFE patch for time of flight 2Mbps PHY for CC13x2 and CC26x2 +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_TOF_H +#define _RF_PATCH_RFE_TOF_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchTofRfe[461] = { + 0x00006194, + 0x004535aa, + 0x0421a355, + 0x1f40004c, + 0x0000003f, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x6fcf7fcf, + 0x4fcf5fcf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x00000000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x40772241, + 0x700006f1, + 0x9150c050, + 0xc0707000, + 0x70009150, + 0x00213182, + 0xb1609181, + 0x10257000, + 0x9100c050, + 0xc140c3f4, + 0x6f031420, + 0x04411031, + 0x22f082a0, + 0x26514094, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92551405, + 0x64677000, + 0x1031c2b2, + 0x31610631, + 0x646a02c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x7000646a, + 0x82b16464, + 0x39813181, + 0x646ac0e2, + 0xc1116467, + 0x646ac122, + 0x68c7c470, + 0xc0c2c111, + 0x64e0646a, + 0x700064f3, + 0x82b1647c, + 0x39813181, + 0x6482c182, + 0xc111647f, + 0x6482c0a2, + 0x68d9c470, + 0xc162c331, + 0x64e06482, + 0x700064f3, + 0xb054b050, + 0x80407100, + 0x44ed2240, + 0x40e02200, + 0x8081b060, + 0x44e01e11, + 0xa0547000, + 0x80f0b064, + 0x40e02200, + 0x12407000, + 0xb03290b0, + 0x395382a3, + 0x64ad3953, + 0x68fbc2f0, + 0xc1f18080, + 0xc1510410, + 0x41071c10, + 0xc2216467, + 0x646ac0c2, + 0x647f610b, + 0xc162c441, + 0xce306482, + 0x1280690c, + 0xb03290b0, + 0x64677000, + 0xc0c2c201, + 0x80a0646a, + 0x39403180, + 0xc1016918, + 0x646ac0c2, + 0xc122c101, + 0x82a3646a, + 0x12c064ad, + 0xb03290b0, + 0x647f7000, + 0xc162c401, + 0x80a06482, + 0x39403180, + 0xc301692c, + 0x6482c162, + 0xc0a2c101, + 0x82a36482, + 0x12c064ad, + 0xb03290b0, + 0x64677000, + 0xc081c272, + 0xc122646a, + 0x646ac111, + 0xc111c002, + 0xc062646a, + 0x646ac331, + 0xc111c362, + 0xc302646a, + 0x646ac111, + 0x395382a3, + 0xc3e264ad, + 0x2211646f, + 0xc242414f, + 0x646ac881, + 0xc111c252, + 0xc272646a, + 0x646acee1, + 0xc881c202, + 0xc202646a, + 0x646ac801, + 0x6963c170, + 0x64677000, + 0xc801c242, + 0xc252646a, + 0x646ac011, + 0xc0e1c272, + 0xc002646a, + 0x646ac101, + 0xc301c062, + 0xc122646a, + 0x646ac101, + 0xc101c362, + 0xc302646a, + 0x646ac101, + 0x64ad82a3, + 0x80817000, + 0x418f1e11, + 0xb054b050, + 0x80407100, + 0x41902240, + 0xb064a054, + 0x220180f1, + 0x70004584, + 0x41842200, + 0x6181b060, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xa050b060, + 0x80928081, + 0x45b32241, + 0xc1f18080, + 0x16300410, + 0x14011101, + 0x61c66c01, + 0x61c661c6, + 0x61c661c6, + 0x61e661c6, + 0x61e661c6, + 0x61c661c6, + 0x809161c6, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x61c661cf, + 0x61c661cf, + 0x61c661c6, + 0x61c661c6, + 0x61c861c8, + 0x61cbb0b0, + 0x7306b0b1, + 0xb0307205, + 0x78206198, + 0x78427831, + 0x78547873, + 0x78667885, + 0x92719260, + 0x92939282, + 0x92b592a4, + 0xc01f91a6, + 0x3940924f, + 0x100106f0, + 0x14103110, + 0x61c89250, + 0xcff0b060, + 0x66306793, + 0xb0e16624, + 0xb054b050, + 0x8262b064, + 0x39823182, + 0x64873942, + 0x7100b0e1, + 0x22008040, + 0xb0644621, + 0x225280f2, + 0x22224611, + 0x22324608, + 0x1e02460f, + 0xdfe041f5, + 0x67939342, + 0x61f56511, + 0x663f663a, + 0x80f0b064, + 0x46112250, + 0x663561f5, + 0xcfd061f5, + 0xa0546793, + 0xa050b064, + 0xa052b060, + 0xa053b062, + 0x6565b063, + 0xcfc06511, + 0x720e6793, + 0xcfb061c8, + 0x62116793, + 0x82b16464, + 0x39813181, + 0x646ac0e2, + 0xc1116467, + 0x646ac122, + 0x700064f3, + 0x70006539, + 0x70006511, + 0x64676565, + 0xc0c2c111, + 0x7000646a, + 0xc1016467, + 0x646ac0c2, + 0xc8007000, + 0x81a991b0, + 0x8091b050, + 0x46b02241, + 0x31828262, + 0x39423982, + 0x82626487, + 0x102f06f2, + 0x142f311f, + 0x22d68266, + 0xc1404655, + 0xc5006256, + 0x6f0d1420, + 0x10de396d, + 0x044ec3f4, + 0x3182c082, + 0x396d002e, + 0x3182c0a2, + 0x826a002d, + 0x06fa398a, + 0x31808270, + 0xc00b3980, + 0x10bc180b, + 0x825318ac, + 0x149b1439, + 0x06f08260, + 0x31101001, + 0x81a11410, + 0x140c1410, + 0x46ea22c6, + 0x39408280, + 0x100206f0, + 0x3001c011, + 0x1801c010, + 0x31821802, + 0x26c10021, + 0xb00391e1, + 0xb063b013, + 0x8041b053, + 0x46e12201, + 0x92148204, + 0x1cb58225, + 0x18954e99, + 0x80f091b5, + 0x428b2240, + 0x913d62ae, + 0x913eb110, + 0x80e0b110, + 0x46a32200, + 0x42a322e6, + 0x1895b0e0, + 0x925f91b5, + 0x14f981a9, + 0x225080f0, + 0x224046e1, + 0x637646ae, + 0x6793cfa0, + 0xa052b063, + 0xc0f28280, + 0x10020420, + 0x3001c011, + 0x1801c010, + 0x31821802, + 0x26c10021, + 0x720e91e1, + 0xb01391e1, + 0xb063b003, + 0xb064b053, + 0x7100b054, + 0x22018041, + 0xb06346e1, + 0x80f0b064, + 0x42e12220, + 0x92118201, + 0x18918221, + 0xb03191b1, + 0x674e62c7, + 0x81a9a0e0, + 0x14598255, + 0x7100c080, + 0x6addb063, + 0xb0e6628b, + 0xa053a052, + 0x81b28251, + 0x3d823182, + 0x7000a003, + 0x39478287, + 0x82803987, + 0x06f03980, + 0xc0111002, + 0xc0103001, + 0x18021801, + 0x00213182, + 0x91d126c1, + 0xb012b002, + 0x39408280, + 0x100206f0, + 0x3001c011, + 0x1801c010, + 0x31821802, + 0x26c10021, + 0xb00391e1, + 0xb063b013, + 0x7100b053, + 0xb062a053, + 0x8041b052, + 0x46e12201, + 0x921481f4, + 0x82048225, + 0x4f201cb5, + 0x91b51895, + 0x224080f0, + 0x62ae4311, + 0x92148204, + 0x10408224, + 0x91b01890, + 0x1c751845, + 0x80f04f2d, + 0x43112240, + 0x913d62ae, + 0x913eb110, + 0x80e0b110, + 0x47372200, + 0x433722e6, + 0x91b5b0e0, + 0x81a9925f, + 0x80f014f9, + 0x463f2250, + 0x46ae2240, + 0x674e6355, + 0x81a9a0e0, + 0x14598255, + 0x7100c140, + 0x6b47b062, + 0x80a26311, + 0x61c86487, + 0x39428262, + 0x608706f2, + 0x7100b050, + 0x829061c8, + 0x22018041, + 0x81f446e1, + 0x82259214, + 0x91b51895, + 0x224180f1, + 0x6b5646ae, + 0x318181b1, + 0xdf903d81, + 0x67939341, + 0x22018041, + 0x81f446e1, + 0x82259214, + 0x4b411cc5, + 0x91b51895, + 0x224080f0, + 0x62ae4362, + 0x6793cf80, + 0x80418290, + 0x46e12201, + 0x92148204, + 0x18958225, + 0x80f191b5, + 0x46ae2241, + 0x80416b79, + 0x46e12201, + 0x92148204, + 0x1cc58225, + 0x18954ad7, + 0x80f091b5, + 0x43852240, + 0x933062ae, + 0x22008320, + 0xb3104794, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_tof(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 461; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchTofRfe[i]; + } +#else + const uint32_t *pS = patchTofRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 57; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rom/driverlib.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rom/driverlib.c new file mode 100644 index 0000000..eb38999 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rom/driverlib.c @@ -0,0 +1,7596 @@ +#include "../driverlib/adi.h" +#include "../driverlib/aes.h" +#include "../driverlib/aon_batmon.h" +#include "../driverlib/aon_batmon.h" +#include "../driverlib/aon_batmon.h" +#include "../driverlib/aon_event.h" +#include "../driverlib/aon_ioc.h" +#include "../driverlib/aon_rtc.h" +#include "../driverlib/aon_rtc.h" +#include "../driverlib/aux_adc.h" +#include "../driverlib/aux_ctrl.h" +#include "../driverlib/aux_tdc.h" +#include "../driverlib/chipinfo.h" +#include "../driverlib/cpu.h" +#include "../driverlib/cpu.h" +#include "../driverlib/crypto.h" +#include "../driverlib/ddi.h" +#include "../driverlib/ddi.h" +#include "../driverlib/event.h" +#include "../driverlib/flash.h" +#include "../driverlib/flash.h" +#include "../driverlib/gpio.h" +#include "../driverlib/i2c.h" +#include "../driverlib/i2s.h" +#include "../driverlib/interrupt.h" +#include "../driverlib/ioc.h" +#include "../driverlib/ioc.h" +#include "../driverlib/osc.h" +#include "../driverlib/osc.h" +#include "../driverlib/pka.h" +#include "../driverlib/prcm.h" +#include "../driverlib/pwr_ctrl.h" +#include "../driverlib/setup_rom.h" +#include "../driverlib/setup_rom.h" +#include "../driverlib/setup_rom.h" +#include "../driverlib/sha2.h" +#include "../driverlib/smph.h" +#include "../driverlib/ssi.h" +#include "../driverlib/sys_ctrl.h" +#include "../driverlib/sys_ctrl.h" +#include "../driverlib/timer.h" +#include "../driverlib/trng.h" +#include "../driverlib/uart.h" +#include "../driverlib/udma.h" +#include "../driverlib/vims.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_2_refsys.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_adi_4_aux.h" +#include "../inc/hw_aon_batmon.h" +#include "../inc/hw_aux_sysif.h" +#include "../inc/hw_aux_sysif.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ddi_0_osc.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_ioc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "../inc/hw_types.h" +#include "../inc/hw_types.h" +#include "../inc/hw_types.h" + +//***************************************************************************** +// +// Disable all external interrupts +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUcpsid(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + mrs r0, PRIMASK; + cpsid i; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUcpsid(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK and disable interrupts + __asm volatile (" mrs %0, PRIMASK\n" + " cpsid i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif +//***************************************************************************** +// +// Enable all external interrupts +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUcpsie(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + mrs r0, PRIMASK; + cpsie i; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUcpsie(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK and enable interrupts. + __asm volatile (" mrs %0, PRIMASK\n" + " cpsie i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif +//***************************************************************************** +// +// Provide a small delay +// +//***************************************************************************** +#if defined(DOXYGEN) +void +CPUdelay(uint32_t ui32Count) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +void +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times + __asm("CPUdelay:\n" + " subs r0, #1\n" + " bne.n CPUdelay\n" + " bx lr"); +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm void +CPUdelay(uint32_t ui32Count) +{ + // Delay the specified number of times (3 cycles pr. loop) +CPUdel + subs r0, #1; + bne CPUdel; + bx lr; +} +#elif defined(__TI_COMPILER_VERSION__) + // For CCS implement this function in pure assembly. This prevents the TI + // compiler from doing funny things with the optimizer. + + // Loop the specified number of times +__asm(" .sect \".text:CPUdelay\"\n" + " .clink\n" + " .thumbfunc CPUdelay\n" + " .thumb\n" + " .global CPUdelay\n" + "CPUdelay:\n" + " subs r0, #1\n" + " bne.n CPUdelay\n" + " bx lr\n"); +#else +// GCC +void __attribute__((naked)) +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times + __asm volatile ("%=: subs %0, #1\n" + " bne %=b\n" + " bx lr\n" + : /* No output */ + : "r" (ui32Count) + ); +} +#endif + +void AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc) { + uint32_t ui32Shift ; + uint32_t ui32Mask ; + uint32_t ui32RegAdr ; + + // Check the arguments. + ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 )) + ASSERT( ui32EventSrc <= AON_EVENT_NONE ); + + ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 ); + ui32Mask = ( 0x3F << ui32Shift ); + ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL ); + if ( ui32MCUWUEvent > 3 ) { + ui32RegAdr += 4; + } + HWREG( ui32RegAdr ) = ( HWREG( ui32RegAdr ) & ( ~ui32Mask )) | ( ui32EventSrc << ui32Shift ); +} + +uint32_t AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent) { + uint32_t ui32Shift ; + uint32_t ui32RegAdr ; + + // Check the arguments. + ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 )) + + ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 ); + ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL ); + if ( ui32MCUWUEvent > 3 ) { + ui32RegAdr += 4; + } + return (( HWREG( ui32RegAdr ) >> ui32Shift ) & 0x3F ); +} + +void AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc) { + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL) = ui32Ctrl; +} + +uint32_t AONEventMcuGet(uint32_t ui32MCUEvent) { + uint32_t ui32EventSrc; + + // Check the arguments. + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S); + } + + // Should never get to this statement, but suppress warning. + ASSERT(0); + return(0); +} + +uint64_t AONRTCCurrent64BitValueGet( void ) { + union { + uint64_t returnValue ; + uint32_t secAndSubSec[ 2 ] ; + } currentRtc ; + uint32_t ui32SecondSecRead ; + + // Reading SEC both before and after SUBSEC in order to detect if SEC incremented while reading SUBSEC + // If SEC incremented, we can't be sure which SEC the SUBSEC belongs to, so repeating the sequence then. + do { + currentRtc.secAndSubSec[ 1 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + currentRtc.secAndSubSec[ 0 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SUBSEC ); + ui32SecondSecRead = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + } while ( currentRtc.secAndSubSec[ 1 ] != ui32SecondSecRead ); + + return ( currentRtc.returnValue ); +} + +void AUXCTRLImageLoad(uint16_t *pui16Image, uint32_t ui32StartAddr, uint32_t ui32Size) { + uint16_t* pui16Src16; + uint16_t* pui16Dst16; + uint32_t ui32WordCnt; + + // Check the arguments. + ASSERT(ui32StartAddr < 512); + ASSERT(ui32Size <= 1024); + ASSERT((ui32Size / 2 + ui32StartAddr) <= 512); + + // Copy image to AUX RAM. + ui32WordCnt = (ui32Size >> 1); + pui16Src16 = pui16Image; + pui16Dst16 = (uint16_t*)(AUX_RAM_BASE + (ui32StartAddr << 1)); + + while(ui32WordCnt--) + { + *pui16Dst16++ = *pui16Src16++; + } +} + +void AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition) { + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Make sure the AUX TDC is in the idle state before changing the + // configuration. + while(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + } + + // Clear previous results. + HWREG(ui32Base + AUX_TDC_O_CTL) = 0x0; + + // Change the configuration. + HWREG(ui32Base + AUX_TDC_O_TRIGSRC) = ui32StartCondition | ui32StopCondition; +} + +uint32_t AUXTDCMeasurementDone(uint32_t ui32Base) { + uint32_t ui32Reg; + uint32_t ui32Status; + + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is done measuring. + ui32Reg = HWREG(ui32Base + AUX_TDC_O_STAT); + if(ui32Reg & AUX_TDC_STAT_DONE) + { + ui32Status = AUX_TDC_DONE; + } + else if(ui32Reg & AUX_TDC_STAT_SAT) + { + ui32Status = AUX_TDC_TIMEOUT; + } + else + { + ui32Status = AUX_TDC_BUSY; + } + + // Return the status. + return (ui32Status); +} + +void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) { + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Write the value to the register. + HWREG(ui32Base + ui32Reg) = ui32Val; +} + +void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData) { + uint32_t ui32RegAddr; + uint32_t ui32Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(!((ui32Mask & 0xFFFF0000) ^ (ui32Mask & 0x0000FFFF))); + ASSERT(!(ui32WrData & 0xFFFF0000)); + + // DDI 16-bit target is on 32-bit boundary so double offset + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // Adjust for target bit in high half of the word. + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 4; + ui32Mask >>= 16; + } + + // Write mask if data is not zero (to set mask bit), else write '0'. + ui32Data = ui32WrData ? ui32Mask : 0x0; + + // Update the register. + HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32Data; +} + +void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data) { + uint32_t ui32RegAddr; + uint32_t ui32WrData; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // 16-bit target is on 32-bit boundary so double offset. + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // Adjust for target bit in high half of the word. + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 4; + ui32Mask = ui32Mask >> 16; + } + + // Shift data in to position. + ui32WrData = ui32Data << ui32Shift; + + // Write data. + HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32WrData; +} + +uint16_t DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask) { + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // Calculate the address of the register. + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // Adjust for target bit in high half of the word. + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // Read a halfword on the DDI interface. + ui16Data = HWREGH(ui32RegAddr); + + // Mask data. + ui16Data = ui16Data & ui32Mask; + + // Return masked data. + return(ui16Data); +} + +uint16_t DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift) { + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // Calculate the register address. + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // Adjust for target bit in high half of the word. + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // Read the register. + ui16Data = HWREGH(ui32RegAddr); + + // Mask data and shift into place. + ui16Data &= ui32Mask; + ui16Data >>= ui32Shift; + + // Return data. + return(ui16Data); +} + +//***************************************************************************** +// +// Defines for accesses to the security control in the customer configuration +// area in flash top sector. +// +//***************************************************************************** +#define CCFG_OFFSET_SECURITY CCFG_O_BL_CONFIG +#define CCFG_OFFSET_SECT_PROT CCFG_O_CCFG_PROT_31_0 +#define CCFG_SIZE_SECURITY 0x00000014 +#define CCFG_SIZE_SECT_PROT 0x00000004 + +//***************************************************************************** +// +// Default values for security control in customer configuration area in flash +// top sector. +// +//***************************************************************************** +const uint8_t g_pui8CcfgDefaultSec[] = {0xFF, 0xFF, 0xFF, 0xC5, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xC5, 0xFF, 0xFF, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF + }; + +//***************************************************************************** +// +// Function prototypes for static functions +// +//***************************************************************************** +static void IssueFsmCommand(tFlashStateCommandsType eCommand); +static void EnableSectorsForWrite(void); +static uint32_t ScaleCycleValues(uint32_t ui32SpecifiedTiming, + uint32_t ui32ScaleValue); +static void SetWriteMode(void); +static void TrimForWrite(void); +static void SetReadMode(void); + +void FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod) { + // Check the arguments. + ASSERT(ui32PowerMode == FLASH_PWR_ACTIVE_MODE || + ui32PowerMode == FLASH_PWR_OFF_MODE || + ui32PowerMode == FLASH_PWR_DEEP_STDBY_MODE); + ASSERT(ui32BankGracePeriod <= 0xFF); + ASSERT(ui32PumpGracePeriod <= 0xFFFF); + + switch(ui32PowerMode) + { + case FLASH_PWR_ACTIVE_MODE: + // Set bank power mode to ACTIVE. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = + (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_ACTIVE; + + // Set charge pump power mode to ACTIVE mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) = + (HWREG(FLASH_BASE + FLASH_O_FPAC1) & ~FLASH_FPAC1_PUMPPWR_M) | (1 << FLASH_FPAC1_PUMPPWR_S); + break; + + case FLASH_PWR_OFF_MODE: + // Set bank grace period. + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // Set pump grace period. + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // Set bank power mode to SLEEP. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= ~FLASH_FBFALLBACK_BANKPWR0_M; + + // Set charge pump power mode to SLEEP mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M; + break; + + case FLASH_PWR_DEEP_STDBY_MODE: + // Set bank grace period. + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // Set pump grace period. + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // Set bank power mode to DEEP STANDBY mode. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = + (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_DEEP_STDBY; + + // Set charge pump power mode to STANDBY mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) |= FLASH_FPAC1_PUMPPWR_M; + break; + } +} + +uint32_t FlashPowerModeGet(void) { + uint32_t ui32PowerMode; + uint32_t ui32BankPwrMode; + + ui32BankPwrMode = HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + FLASH_FBFALLBACK_BANKPWR0_M; + + if(ui32BankPwrMode == FBFALLBACK_SLEEP) + { + ui32PowerMode = FLASH_PWR_OFF_MODE; + } + else if(ui32BankPwrMode == FBFALLBACK_DEEP_STDBY) + { + ui32PowerMode = FLASH_PWR_DEEP_STDBY_MODE; + } + else + { + ui32PowerMode = FLASH_PWR_ACTIVE_MODE; + } + + // Return power mode. + return(ui32PowerMode); +} + +void FlashProtectionSet(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode) { + uint32_t ui32SectorNumber; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(ui32ProtectMode == FLASH_WRITE_PROTECT) + { + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / + FlashSectorSizeGet(); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + if(ui32SectorNumber <= 31) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber); + } + else if(ui32SectorNumber <= 63) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |= + (1 << (ui32SectorNumber & 0x1F)); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |= + (1 << (ui32SectorNumber & 0x1F)); + } + + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } +} + +uint32_t FlashProtectionGet(uint32_t ui32SectorAddress) { + uint32_t ui32SectorProtect; + uint32_t ui32SectorNumber; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + ui32SectorProtect = FLASH_NO_PROTECT; + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + + if(ui32SectorNumber <= 31) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + else if(ui32SectorNumber <= 63) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) & + (1 << (ui32SectorNumber & 0x1F))) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) & + (1 << (ui32SectorNumber & 0x1F)))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + + return(ui32SectorProtect); +} + +uint32_t FlashProtectionSave(uint32_t ui32SectorAddress) { + uint32_t ui32ErrorReturn; + uint32_t ui32SectorNumber; + uint32_t ui32CcfgSectorAddr; + uint32_t ui32ProgBuf; + + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(FlashProtectionGet(ui32SectorAddress) == FLASH_WRITE_PROTECT) + { + // Find sector number for specified sector. + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + ui32CcfgSectorAddr = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); + + // Adjust CCFG address to the 32-bit CCFG word holding the + // protect-bit for the specified sector. + ui32CcfgSectorAddr += (((ui32SectorNumber >> 5) * 4) + CCFG_OFFSET_SECT_PROT); + + // Find value to program by setting the protect-bit which + // corresponds to specified sector number, to 0. + // Leave other protect-bits unchanged. + ui32ProgBuf = (~(1 << (ui32SectorNumber & 0x1F))) & + *(uint32_t *)ui32CcfgSectorAddr; + + ui32ErrorReturn = FlashProgram((uint8_t*)&ui32ProgBuf, ui32CcfgSectorAddr, + CCFG_SIZE_SECT_PROT); + } + + // Return status. + return(ui32ErrorReturn); +} + +uint32_t FlashSectorErase(uint32_t ui32SectorAddress) { + // The below code part constitutes the variant of the FlashSectorErase() + // function that is located in ROM. The source code of this variant is not + // visible in internal or external driverlib. The source code is + // only compiled during a ROM build. + // The two above code parts (seperated by compile switches) constitute wrapper + // functions which both call this ROM variant of the function. + // The ROM variant is called by referrencing it directly through the ROM API table. + uint32_t ui32ErrorReturn; + uint32_t ui32Error; + uint32_t ui32SectorBit; + uint32_t ui32SectorNumber; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + // Enable all sectors for erase. + EnableSectorsForWrite(); + + // Check the arguments. + if((ui32SectorAddress > + (FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet())) || + ((ui32SectorAddress & (FlashSectorSizeGet() - 1)) != 00)) + { + // Invalid arguments. Exit function! + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Unprotect sector to be erased. + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + ui32SectorBit = 1 << (ui32SectorNumber & 0x1F); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + if(ui32SectorNumber < 0x20) + { + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = ~ui32SectorBit; + } + else + { + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = ~ui32SectorBit; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Write the address to the FSM. + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32SectorAddress + ADDR_OFFSET; + + // Issue the sector erase command to the FSM. + IssueFsmCommand(FAPI_ERASE_SECTOR); + + // Wait for erase to finish. + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // Update status. + ui32ErrorReturn = FlashCheckFsmForError(); + + // Disable sectors for erase. + FlashDisableSectorsForWrite(); + + // Check if flash top sector was erased. + if(ui32SectorAddress == (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())) + { + // Program security data to default values in the customer configuration + // area within the flash top sector. + ui32Error = FlashProgram((uint8_t *)g_pui8CcfgDefaultSec, + (ui32SectorAddress + CCFG_OFFSET_SECURITY), + CCFG_SIZE_SECURITY); + + if((ui32Error != FAPI_STATUS_SUCCESS) && + (ui32ErrorReturn == FAPI_STATUS_SUCCESS)) + { + ui32ErrorReturn = ui32Error; + } +} + + // Return status of operation. + return(ui32ErrorReturn); +} + +uint32_t FlashBankErase(bool bForcePrecondition) { + uint32_t ui32ErrorReturn; + uint32_t ui32SectorAddress; + uint32_t ui32RegVal; + + // Enable all sectors for erase. + EnableSectorsForWrite(); + + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Enable erase of all sectors and enable precondition if required. + ui32RegVal = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000; + if(bForcePrecondition) + { + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + FLASH_FSM_ST_MACHINE_DO_PRECOND; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Issue the bank erase command to the FSM. + IssueFsmCommand(FAPI_ERASE_BANK); + + // Wait for erase to finish. + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // Update status. + ui32ErrorReturn = FlashCheckFsmForError(); + + // Disable sectors for erase. + FlashDisableSectorsForWrite(); + + // Set configured precondition mode since it may have been forced on. + if(!(ui32RegVal & FLASH_FSM_ST_MACHINE_DO_PRECOND)) + { + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= + ~FLASH_FSM_ST_MACHINE_DO_PRECOND; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } + + // Program security data to default values in the customer configuration + // area within the flash top sector if erase was successful. + if(ui32ErrorReturn == FAPI_STATUS_SUCCESS) + { + ui32SectorAddress = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); + ui32ErrorReturn = FlashProgram((uint8_t *)g_pui8CcfgDefaultSec, + (ui32SectorAddress + CCFG_OFFSET_SECURITY), + CCFG_SIZE_SECURITY); + } + + // Return status of operation. + return(ui32ErrorReturn); +} + +uint32_t FlashhOtpEngrErase(void) { + uint32_t ui32ErrorReturn; + uint32_t ui32RegVal; + + // Enable all sectors for erase. + EnableSectorsForWrite(); + + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Disable OTP protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) |= FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Enable test commands. + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // Set address to OTP. + HWREG(FLASH_BASE + FLASH_O_FADDR) = 0xF0000000; + + // Enable for FSM test commands and erase precondition. + ui32RegVal = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + (FLASH_FSM_ST_MACHINE_CMD_EN | FLASH_FSM_ST_MACHINE_DO_PRECOND); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Issue the erase command to the FSM. + IssueFsmCommand(FAPI_ERASE_OTP); + + // Wait for erase to finish. + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // Update status. + ui32ErrorReturn = FlashCheckFsmForError(); + + // Disable sectors for erase. + FlashDisableSectorsForWrite(); + + // Disable test commands. + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // Renable OTP protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Disable FSM test command mode. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + + // Set configured precondition mode since it may have been changed. + if(!(ui32RegVal & FLASH_FSM_ST_MACHINE_DO_PRECOND)) + { + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= + ~FLASH_FSM_ST_MACHINE_DO_PRECOND; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Return status of operation. + return(ui32ErrorReturn); +} + +uint32_t FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) { + // The below code part constitutes the variant of the FlashProgram() function + // that is located in ROM. The source code of this variant is not visible in + // internal or external driverlib. The source code is only compiled during a ROM + // build. + // The two above code parts (seperated by compile switches) constitute wrapper + // functions which both call this ROM variant of the function. + // The ROM variant is called by referrencing it directly through the ROM API table. + uint32_t ui32StartIndex; + uint32_t ui32StopIndex; + uint32_t ui32Index; + uint8_t ui8BankWidth; + uint8_t ui8NoOfBytes; + tFwpWriteByte *oFwpWriteByte; + uint32_t ui32ErrorReturn; + + // Check the arguments. + ASSERT((ui32Address + ui32Count) <= (FLASHMEM_BASE + FlashSizeGet())); + + // Enable sectors for programming. + EnableSectorsForWrite(); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // Check the arguments. + if((ui32Address + ui32Count) > (FLASHMEM_BASE + FlashSizeGet())) + { + // Invalid arguments. Exit function! + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // Set the status to indicate success. + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // Find flash bank width in number of bytes. + ui8BankWidth = + (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // Loop over the bytes to be programmed. + while(ui32Count) + { + // Setup the start position within the write data registers. + ui32StartIndex = ui32Address & (uint32_t)(ui8BankWidth - 1); + + // Setup number of bytes to program. + ui8NoOfBytes = ui8BankWidth - ui32StartIndex; + if(ui8NoOfBytes > ui32Count) + { + ui8NoOfBytes = ui32Count; + } + + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Write address to FADDR register. + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32Address + ADDR_OFFSET; + + // Setup the stop position within the write data registers. + ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); + + // Write each byte to the FWPWrite registers. + for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) + { + oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); + } + + // Issue the Program command to the FSM. + IssueFsmCommand(FAPI_PROGRAM_DATA); + + // Wait until the word has been programmed. + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // Exit if an access violation occurred. + ui32ErrorReturn = FlashCheckFsmForError(); + if(ui32ErrorReturn != FAPI_STATUS_SUCCESS) + { + break; + } + + // Prepare for next data burst. + ui32Count -= ((ui32StopIndex - ui32StartIndex) + 1); + ui32Address += ((ui32StopIndex - ui32StartIndex) + 1); + } + + // Disable sectors for programming. + FlashDisableSectorsForWrite(); + + // Return status of operation. + return(ui32ErrorReturn); +} + +uint32_t FlashProgramNowait(uint32_t ui32StartAddress, uint8_t *pui8DataBuffer, uint8_t ui8NoOfBytes) { + uint32_t ui32StartIndex; + uint32_t ui32StopIndex; + uint32_t ui32Index; + uint32_t ui32BankWidth; + uint32_t ui32ErrorReturn; + tFwpWriteByte *oFwpWriteByte; + + // Check the arguments. + ASSERT((ui32StartAddress + ui8NoOfBytes) <= (FLASHMEM_BASE + FlashSizeGet())); + + // Enable sectors for programming. + EnableSectorsForWrite(); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // Check the arguments. + if((ui32StartAddress + ui8NoOfBytes) > (FLASHMEM_BASE + FlashSizeGet())) + { + // Invalid arguments. Exit function! + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // Set status to indicate success + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // Find flash bank width in number of bytes. + ui32BankWidth = (((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // Setup the start position within the write data registers. + ui32StartIndex = ui32StartAddress & (ui32BankWidth - 1); + + // Check to see if there is more data in the buffer than the register. + // width. + if((ui8NoOfBytes == 0) || ((ui32StartIndex + ui8NoOfBytes) > ui32BankWidth)) + { + ui32ErrorReturn = FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH; + } + + if(ui32ErrorReturn == FAPI_STATUS_SUCCESS) + { + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Write address to FADDR register. + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32StartAddress + ADDR_OFFSET; + + // Setup the stop position within the write data registers. + ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); + + // Write each byte to the FWPWrite registers. + for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) + { + oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); +} + + // Issue the Program command to the FSM. + IssueFsmCommand(FAPI_PROGRAM_DATA); + } + + // Return the function status. + return(ui32ErrorReturn); +} + +bool FlashEfuseReadRow(uint32_t *pui32EfuseData, uint32_t ui32RowAddress) { + bool bStatus; + + // Make sure the clock for the efuse is enabled + HWREG(FLASH_BASE + FLASH_O_CFG) &= ~FLASH_CFG_DIS_EFUSECLK; + + // Set timing for EFUSE read operations. + HWREG(FLASH_BASE + FLASH_O_EFUSEREAD) |= ((5 << FLASH_EFUSEREAD_READCLOCK_S) & + FLASH_EFUSEREAD_READCLOCK_M); + + // Clear status register. + HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) = 0; + + // Select the FuseROM block 0. + HWREG(FLASH_BASE + FLASH_O_EFUSEADDR) = 0x00000000; + + // Start the read operation. + HWREG(FLASH_BASE + FLASH_O_EFUSE) = + (DUMPWORD_INSTR << FLASH_EFUSE_INSTRUCTION_S) | + (ui32RowAddress & FLASH_EFUSE_DUMPWORD_M); + + // Wait for operation to finish. + while(!(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_DONE)) + { + } + + // Check if error reported. + if(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_CODE_M) + { + // Set error status. + bStatus = 1; + + // Clear data. + *pui32EfuseData = 0; + } + else + { + // Set ok status. + bStatus = 0; + + // No error. Get data from data register. + *pui32EfuseData = HWREG(FLASH_BASE + FLASH_O_DATALOWER); + } + + // Disable the efuse clock to conserve power + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_EFUSECLK; + + // Return the data. + return(bStatus); +} + +uint32_t FlashProgramPattern(uint32_t ui32SectorAddress, uint32_t ui32DataPattern, bool bInvertData) { + uint8_t ui8Index; + uint8_t ui8BankWidth; + tFwpWriteByte *oFwpWriteByte; + uint32_t ui32ErrorReturn; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + // Enable sectors for programming. + EnableSectorsForWrite(); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // Check the arguments. + if((ui32SectorAddress > + (FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet())) || + ((ui32SectorAddress & (FlashSectorSizeGet() - 1)) != 00)) + { + // Invalid arguments. Exit function! + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // Find flash bank width in number of bytes. + ui8BankWidth = + (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Write address to FADDR register. + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32SectorAddress + ADDR_OFFSET; + + // Write each byte of the pattern to the FWPWrite registers. + for(ui8Index = 0; ui8Index < ui8BankWidth; ui8Index++) + { + oFwpWriteByte[ui8Index] = ui32DataPattern >> ((ui8Index * 8) & + (PATTERN_BITS - 1)); + } + + // Enable for FSM test command and enable the Invert Data option if + // required. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; + if(bInvertData) + { + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_INV_DATA; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Issue the Program command to the FSM. + IssueFsmCommand(FAPI_PROGRAM_SECTOR); + + // Wait until the sector has been programmed. + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // Update status of the program operation. + ui32ErrorReturn = FlashCheckFsmForError(); + + // Disable sectors for programming. + FlashDisableSectorsForWrite(); + + // Disable FSM test command mode and the Invert Data option. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_INV_DATA; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Return status of operation. + return(ui32ErrorReturn); +} + +uint32_t FlashProgramEngr(uint8_t *pui8DataBuffer, uint32_t ui32AddressOffset, uint32_t ui32Count) { + uint32_t ui32StartIndex; + uint32_t ui32StopIndex; + uint32_t ui32Index; + uint8_t ui8BankWidth; + uint8_t ui8NoOfBytes; + tFwpWriteByte *oFwpWriteByte; + uint32_t ui32ErrorReturn; + + // Check the arguments. + ASSERT((ui32AddressOffset + ui32Count) <= 2048); + // Enable sectors for programming. + EnableSectorsForWrite(); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // Check the arguments. + if((ui32AddressOffset + ui32Count) > 2048) + { + // Invalid arguments. Exit function! + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // Set the status to indicate success. + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // Find flash bank width in number of bytes. + ui8BankWidth = + (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // Disable OTP protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) |= FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Enable test commands. + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // Enable for FSM test command. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Loop over the bytes to be programmed. + while(ui32Count) + { + // Setup the start position within the write data registers. + ui32StartIndex = ui32AddressOffset & (uint32_t)(ui8BankWidth - 1); + + // Setup number of bytes to program. + ui8NoOfBytes = ui8BankWidth - ui32StartIndex; + if(ui8NoOfBytes > ui32Count) + { + ui8NoOfBytes = ui32Count; + } + + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Write address to FADDR register. + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32AddressOffset + 0xF0080000; + + // Setup the stop position within the write data registers. + ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); + + // Write each byte to the FWPWrite registers. + for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) + { + oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); + } + + // Issue programming command. + IssueFsmCommand(FAPI_PROGRAM_DATA); + + // Wait until the word has been programmed. + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // Update error status and exit if an error occurred. + ui32ErrorReturn = FlashCheckFsmForError(); + if(ui32ErrorReturn != FAPI_STATUS_SUCCESS) + { + break; + } + + // Prepare for next data burst. + ui32Count -= ((ui32StopIndex - ui32StartIndex) + 1); + ui32AddressOffset += ((ui32StopIndex - ui32StartIndex) + 1); + } + + // Disable sectors for programming. + FlashDisableSectorsForWrite(); + + // Re-enable OTP protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Disable test commands. + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // Disable FSM test command mode. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Return status of operation. + return(ui32ErrorReturn); +} + +void FlashOtpProgramEraseSetup(void) { + // Disable OTP protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) |= FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Enable test commands by performing the following steps: + // - Enable SW Interface mode + // - Enable for test commands + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x0000AAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x000055AA; + + // Enable for FSM test commands. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +void FlashOtpProgramEraseCleanup(void) { + // Re-enable OTP protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Disable test commands and turn off SW interface mode. + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x0000AAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // Disable FSM test command mode. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +void FlashDisableSectorsForWrite(void) { + // Configure flash back to read mode + SetReadMode(); + + // Disable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + // Disable all sectors for erase and programming. + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; + + // Enable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Protect sectors from sector erase. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} +//***************************************************************************** +// +//! \internal +//! Issues a command to the Flash State Machine. +//! +//! \param eCommand specifies the FSM command. +//! +//! Issues a command to the Flash State Machine. +//! +//! \return None +// +//***************************************************************************** +static void +IssueFsmCommand(tFlashStateCommandsType eCommand) +{ + // Check the arguments. + ASSERT( + eCommand == FAPI_ERASE_SECTOR || eCommand == FAPI_ERASE_BANK || + eCommand == FAPI_VALIDATE_SECTOR || eCommand == FAPI_CLEAR_STATUS || + eCommand == FAPI_PROGRAM_RESUME || eCommand == FAPI_ERASE_RESUME || + eCommand == FAPI_CLEAR_MORE || eCommand == FAPI_PROGRAM_SECTOR || + eCommand == FAPI_PROGRAM_DATA || eCommand == FAPI_ERASE_OTP); + + // Enable write to FSM register. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + // Issue FSM command. + HWREG(FLASH_BASE + FLASH_O_FSM_CMD) = eCommand; + + // Start command execute. + HWREG(FLASH_BASE + FLASH_O_FSM_EXECUTE) = FLASH_CMD_EXEC; + + // Disable write to FSM register. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \internal +//! Enables all sectors for erase and programming on the active bank. +//! +//! This function disables the idle reading power reduction mode, selects the +//! flash bank and enables all sectors for erase and programming on the active +//! bank. +//! Sectors may be protected from programming depending on the value of the +//! FLASH_O_FSM_BSLPx registers. +//! Sectors may be protected from erase depending on the value of the +//! FLASH_O_FSM_BSLEx registers. Additional sector erase protection is set by +//! the FLASH_O_FSM_SECTOR1 register. +//! +//! \return None +// +//***************************************************************************** +static void +EnableSectorsForWrite(void) +{ + // Trim flash module for program/erase operation. + TrimForWrite(); + + // Configure flash to write mode + SetWriteMode(); + + // Select flash bank. + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + + // Disable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + // Enable all sectors for erase and programming. + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0xFFFF; + + // Enable Level 1 Protection + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; +} + +//***************************************************************************** +// +//! \internal +//! Trims the Flash Bank and Flash Pump for program/erase functionality +//! +//! This trimming will make it possible to perform erase and program operations +//! of the flash. Trim values are loaded from factory configuration area +//! (referred to as FCGF1). The trimming done by this function is valid until +//! reset of the flash module. +//! +//! Some registers shall be written with a value that is a number of FCLK +//! cycles. The trim values controlling these registers have a value of +//! number of half us. FCLK = SysClk / ((RWAIT+1) x 2). +//! +//! In order to calculate the register value for these registers the +//! following calculation must be done: +//! +//! OtpValue SysClkMHz +//! -------- us OtpValue x --------- +//! 2 (RWAIT+1) +//! RegValue_in_no_of_clk_cycles = ----------------- = --------------------- +//! 1 4 +//! -------------- +//! SysClkMHz +//! ------------ +//! (RWAIT+1)x 2 +//! +//! This is equivalent to: +//! +//! 16 x SysClkMHz +//! OtpValue x --------------- +//! (RWAIT+1) +//! RegValue_in_no_of_clk_cycles = ---------------------------- +//! 64 +//! +//! A scaling factor is set equal to: +//! +//! 16 x SysClkMHz +//! ui32FclkScale = -------------- +//! (RWAIT+1) +//! +//! which gives: +//! +//! OtpValue x ui32FclkScale +//! RegValue_in_no_of_clk_cycles = ------------------------ +//! 64 +//! +//! \return None. +// +//***************************************************************************** +static void +TrimForWrite(void) +{ + uint32_t ui32Value; + uint32_t ui32TempVal; + uint32_t ui32FclkScale; + uint32_t ui32RWait; + + // Return if flash is already trimmed for program/erase operations. + if(HWREG(FLASH_BASE + FLASH_O_FWFLAG) & FW_WRT_TRIMMED) + { + return; + } + + //***********************************************************************// + // // + // Configure the FSM registers // + // // + //***********************************************************************// + + // Enable access to the FSM registers. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + // Determine the scaling value to be used on timing related trim values. + // The scaling value is based on the flash module clock frequency and RWAIT + ui32RWait = (HWREG(FLASH_BASE + FLASH_O_FRDCTL) & + FLASH_FRDCTL_RWAIT_M) >> FLASH_FRDCTL_RWAIT_S; + ui32FclkScale = (16 * FLASH_MODULE_CLK_FREQ) / (ui32RWait + 1); + + // Configure Program pulse width bits 15:0. + // (FCFG1 offset 0x188 bits 15:0). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PROG_EP) & + FCFG1_FLASH_PROG_EP_PROGRAM_PW_M) >> + FCFG1_FLASH_PROG_EP_PROGRAM_PW_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) & + ~FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M) | + ((ui32Value << FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S) & + FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M); + + // Configure Erase pulse width bits 31:0. + // (FCFG1 offset 0x18C bits 31:0). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_ERA_PW) & + FCFG1_FLASH_ERA_PW_ERASE_PW_M) >> + FCFG1_FLASH_ERA_PW_ERASE_PW_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) & + ~FLASH_FSM_ERA_PW_FSM_ERA_PW_M) | + ((ui32Value << FLASH_FSM_ERA_PW_FSM_ERA_PW_S) & + FLASH_FSM_ERA_PW_FSM_ERA_PW_M); + + + // Configure no of flash clock cycles from EXECUTEZ going low to the + // verify data can be read in the program verify mode bits 7:0. + // (FCFG1 offset 0x174 bits 23:16). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) & + FCFG1_FLASH_C_E_P_R_PV_ACCESS_M) >> + FCFG1_FLASH_C_E_P_R_PV_ACCESS_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & + ~FLASH_FSM_EX_VAL_EXE_VALD_M) | + ((ui32Value << FLASH_FSM_EX_VAL_EXE_VALD_S) & + FLASH_FSM_EX_VAL_EXE_VALD_M); + + // Configure the number of flash clocks from the start of the Read mode at + // the end of the operations until the FSM clears the BUSY bit in FMSTAT. + // (FCFG1 offset 0x178 bits 23:16). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) & + FCFG1_FLASH_P_R_PV_RH_M) >> + FCFG1_FLASH_P_R_PV_RH_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) = + (HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) & + ~FLASH_FSM_RD_H_RD_H_M) | + ((ui32Value << FLASH_FSM_RD_H_RD_H_S) & + FLASH_FSM_RD_H_RD_H_M); + + // Configure Program hold time + // (FCFG1 offset 0x178 bits 31:24). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) & + FCFG1_FLASH_P_R_PV_PH_M) >> + FCFG1_FLASH_P_R_PV_PH_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) & + ~FLASH_FSM_P_OH_PGM_OH_M) | + ((ui32Value << FLASH_FSM_P_OH_PGM_OH_S) & + FLASH_FSM_P_OH_PGM_OH_M); + + // Configure Erase hold time + // (FCFG1 offset 0x17C bits 31:24). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_EH_SEQ) & + FCFG1_FLASH_EH_SEQ_EH_M) >> + FCFG1_FLASH_EH_SEQ_EH_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) & + ~FLASH_FSM_ERA_OH_ERA_OH_M) | + ((ui32Value << FLASH_FSM_ERA_OH_ERA_OH_S) & + FLASH_FSM_ERA_OH_ERA_OH_M); + + // Configure Program verify row switch time + // (FCFG1 offset0x178 bits 15:8). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) & + FCFG1_FLASH_P_R_PV_PVH_M) >> + FCFG1_FLASH_P_R_PV_PVH_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) & + ~FLASH_FSM_PE_VH_PGM_VH_M) | + ((ui32Value << FLASH_FSM_PE_VH_PGM_VH_S) & + FLASH_FSM_PE_VH_PGM_VH_M); + + // Configure Program Operation Setup time + // (FCFG1 offset 0x170 bits 31:24). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_PSU_M) >> + FCFG1_FLASH_E_P_PSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & + ~FLASH_FSM_PE_OSU_PGM_OSU_M) | + ((ui32Value << FLASH_FSM_PE_OSU_PGM_OSU_S) & + FLASH_FSM_PE_OSU_PGM_OSU_M); + + // Configure Erase Operation Setup time + // (FCGF1 offset 0x170 bits 23:16). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_ESU_M) >> + FCFG1_FLASH_E_P_ESU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & + ~FLASH_FSM_PE_OSU_ERA_OSU_M) | + ((ui32Value << FLASH_FSM_PE_OSU_ERA_OSU_S) & + FLASH_FSM_PE_OSU_ERA_OSU_M); + + // Configure Program Verify Setup time + // (FCFG1 offset 0x170 bits 15:8). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_PVSU_M) >> + FCFG1_FLASH_E_P_PVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & + ~FLASH_FSM_PE_VSU_PGM_VSU_M) | + ((ui32Value << FLASH_FSM_PE_VSU_PGM_VSU_S) & + FLASH_FSM_PE_VSU_PGM_VSU_M); + + // Configure Erase Verify Setup time + // (FCFG1 offset 0x170 bits 7:0). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_EVSU_M) >> + FCFG1_FLASH_E_P_EVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & + ~FLASH_FSM_PE_VSU_ERA_VSU_M) | + ((ui32Value << FLASH_FSM_PE_VSU_ERA_VSU_S) & + FLASH_FSM_PE_VSU_ERA_VSU_M); + + // Configure Addr to EXECUTEZ low setup time + // (FCFG1 offset 0x174 bits 15:12). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) & + FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M) >> + FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) & + ~FLASH_FSM_CMP_VSU_ADD_EXZ_M) | + ((ui32Value << FLASH_FSM_CMP_VSU_ADD_EXZ_S) & + FLASH_FSM_CMP_VSU_ADD_EXZ_M); + + // Configure Voltage Status Count + // (FCFG1 offset 0x17C bits 15:12). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_EH_SEQ) & + FCFG1_FLASH_EH_SEQ_VSTAT_M) >> + FCFG1_FLASH_EH_SEQ_VSTAT_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) = + (HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) & + ~FLASH_FSM_VSTAT_VSTAT_CNT_M) | + ((ui32Value << FLASH_FSM_VSTAT_VSTAT_CNT_S) & + FLASH_FSM_VSTAT_VSTAT_CNT_M); + + // Configure Repeat Verify action setup + // (FCFG1 offset 0x174 bits 31:24). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) & + FCFG1_FLASH_C_E_P_R_RVSU_M) >> + FCFG1_FLASH_C_E_P_R_RVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & + ~FLASH_FSM_EX_VAL_REP_VSU_M) | + ((ui32Value << FLASH_FSM_EX_VAL_REP_VSU_S) & + FLASH_FSM_EX_VAL_REP_VSU_M); + + // Configure Maximum Programming Pulses + // (FCFG1 offset 0x184 bits 15:0). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PP) & + FCFG1_FLASH_PP_MAX_PP_M) >> + FCFG1_FLASH_PP_MAX_PP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & + ~FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M) | + ((ui32Value << FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S) & + FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M); + + // Configure Beginning level for VHVCT used during erase modes + // (FCFG1 offset 0x180 bits 31:16). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_E) & + FCFG1_FLASH_VHV_E_VHV_E_START_M) >> + FCFG1_FLASH_VHV_E_VHV_E_START_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & + ~FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M) | + ((ui32Value << FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S) & + FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M); + + // Configure Maximum EC Level + // (FCFG1 offset 0x2B0 bits 21:18). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M) >> + FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & + ~FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M) | + ((ui32Value << FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S) & + FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M); + + // Configure Maximum Erase Pulses + // (FCFG1 offset 0x188 bits 31:16). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PROG_EP) & + FCFG1_FLASH_PROG_EP_MAX_EP_M) >> + FCFG1_FLASH_PROG_EP_MAX_EP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & + ~FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M) | + ((ui32Value << FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S) & + FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M); + + // Configure the VHVCT Step Size. This is the number of erase pulses that + // must be completed for each level before the FSM increments the + // CUR_EC_LEVEL to the next higher level. Actual erase pulses per level + // equals (EC_STEP_SIZE +1). The stepping is only needed for the VHVCT + // voltage. + // (FCFG1 offset 0x2B0 bits 31:23). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M) >> + FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) = + (HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) & + ~FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M) | + ((ui32Value << FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S) & + FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M); + + // Configure the hight of each EC step. This is the number of counts that + // the CUR_EC_LEVEL will increment when going to a new level. Actual count + // size equals (EC_STEP_HEIGHT + 1). The stepping applies only to the VHVCT + // voltage. + // The read trim value is decremented by 1 before written to the register + // since actual counts equals (register value + 1). + // (FCFG1 offset 0x180 bits 15:0). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_E) & + FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M) >> + FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_EC_STEP_HEIGHT) = ((ui32Value - 1) & + FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M); + + // Configure Precondition used in erase operations + // (FCFG1 offset 0x2B0 bit 22). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M) >> + FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) & + ~FLASH_FSM_ST_MACHINE_DO_PRECOND_M) | + ((ui32Value << FLASH_FSM_ST_MACHINE_DO_PRECOND_S) & + FLASH_FSM_ST_MACHINE_DO_PRECOND_M); + + // Enable the recommended Good Time function. + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD; + + // Disable write access to FSM registers. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + + //***********************************************************************// + // // + // Configure the voltage registers // + // // + //***********************************************************************// + + // Unlock voltage registers (0x2080 - 0x2098). + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + + // Configure voltage level for the specified pump voltage of high + // voltage supply input during erase operation VHVCT_E and the TRIM13_E + // (FCFG1 offset 0x190 bits[3:0] and bits[11:8]). + ui32TempVal = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV); + + ui32Value = ((ui32TempVal & FCFG1_FLASH_VHV_TRIM13_E_M)>> + FCFG1_FLASH_VHV_TRIM13_E_S) << FLASH_FVHVCT1_TRIM13_E_S; + ui32Value |= ((ui32TempVal & FCFG1_FLASH_VHV_VHV_E_M)>> + FCFG1_FLASH_VHV_VHV_E_S) << FLASH_FVHVCT1_VHVCT_E_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & + ~(FLASH_FVHVCT1_TRIM13_E_M | FLASH_FVHVCT1_VHVCT_E_M)) | ui32Value; + + // Configure voltage level for the specified pump voltage of high voltage + // supply input during program verify operation VHVCT_PV and the TRIM13_PV + // (OTP offset 0x194 bits[19:16] and bits[27:24]). + ui32TempVal = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_PV); + + ui32Value = ((ui32TempVal & FCFG1_FLASH_VHV_PV_TRIM13_PV_M)>> + FCFG1_FLASH_VHV_PV_TRIM13_PV_S) << + FLASH_FVHVCT1_TRIM13_PV_S; + ui32Value |= ((ui32TempVal & FCFG1_FLASH_VHV_PV_VHV_PV_M)>> + FCFG1_FLASH_VHV_PV_VHV_PV_S) << + FLASH_FVHVCT1_VHVCT_PV_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & + ~(FLASH_FVHVCT1_TRIM13_PV_M | FLASH_FVHVCT1_VHVCT_PV_M)) | ui32Value; + + // Configure voltage level for the specified pump voltage of high voltage + // supply input during program operation VHVCT_P and TRIM13_P + // (FCFG1 offset 0x190 bits[19:16] and bits[27:24]). + ui32TempVal = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV); + + ui32Value = ((ui32TempVal & FCFG1_FLASH_VHV_TRIM13_P_M)>> + FCFG1_FLASH_VHV_TRIM13_P_S) << FLASH_FVHVCT2_TRIM13_P_S; + ui32Value |= ((ui32TempVal & FCFG1_FLASH_VHV_VHV_P_M)>> + FCFG1_FLASH_VHV_VHV_P_S) << FLASH_FVHVCT2_VHVCT_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT2) = + (HWREG(FLASH_BASE + FLASH_O_FVHVCT2) & + ~(FLASH_FVHVCT2_TRIM13_P_M | FLASH_FVHVCT2_VHVCT_P_M)) | ui32Value; + + // Configure voltage level for the specified pump voltage of wordline power + // supply for read mode + // (FCFG1 offset 0x198 Bits 15:8). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) & + FCFG1_FLASH_V_V_READ_M) >> + FCFG1_FLASH_V_V_READ_S; + + HWREG(FLASH_BASE + FLASH_O_FVREADCT) = + (HWREG(FLASH_BASE + FLASH_O_FVREADCT) & + ~FLASH_FVREADCT_VREADCT_M) | + ((ui32Value << FLASH_FVREADCT_VREADCT_S) & + FLASH_FVREADCT_VREADCT_M); + + // Configure the voltage level for the VCG 2.5 CT pump voltage + // (FCFG1 offset 0x194 bits 15:8). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_PV) & + FCFG1_FLASH_VHV_PV_VCG2P5_M) >> + FCFG1_FLASH_VHV_PV_VCG2P5_S; + + HWREG(FLASH_BASE + FLASH_O_FVNVCT) = + (HWREG(FLASH_BASE + FLASH_O_FVNVCT) & + ~FLASH_FVNVCT_VCG2P5CT_M) | + ((ui32Value << FLASH_FVNVCT_VCG2P5CT_S) & + FLASH_FVNVCT_VCG2P5CT_M); + + // Configure the voltage level for the specified pump voltage of high + // current power input during program operation + // (FCFG1 offset 0x198 bits 31:24). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) & + FCFG1_FLASH_V_VSL_P_M) >> + FCFG1_FLASH_V_VSL_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVSLP) = + (HWREG(FLASH_BASE + FLASH_O_FVSLP) & + ~FLASH_FVSLP_VSL_P_M) | + ((ui32Value << FLASH_FVSLP_VSL_P_S) & + FLASH_FVSLP_VSL_P_M); + + // Configure the voltage level for the specified pump voltage of wordline + // power supply during programming operations + // (OTP offset 0x198 bits 23:16). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) & + FCFG1_FLASH_V_VWL_P_M) >> + FCFG1_FLASH_V_VWL_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVWLCT) = + (HWREG(FLASH_BASE + FLASH_O_FVWLCT) & + ~FLASH_FVWLCT_VWLCT_P_M) | + ((ui32Value << FLASH_FVWLCT_VWLCT_P_S) & + FLASH_FVWLCT_VWLCT_P_M); + + // Configure the pump's TRIM_1P7 port pins. + // (FCFG1 offset 0x2B0 bits 17:16). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M) >> + FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S; + + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~FLASH_FSEQPMP_TRIM_1P7_M) | + ((ui32Value << FLASH_FSEQPMP_TRIM_1P7_S) & + FLASH_FSEQPMP_TRIM_1P7_M); + + // Lock the voltage registers. + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // Set trimmed flag. + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; + HWREG(FLASH_BASE + FLASH_O_FWFLAG) |= FW_WRT_TRIMMED; + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; +} + +//***************************************************************************** +// +//! \internal +//! Used to scale the TI OTP values based on the FClk scaling value. +//! +//! \param ui32SpecifiedTiming +//! \param ui32ScaleValue +//! +//! Used to scale the TI OTP values based on the FClk scaling value. +//! +//! \return Returns the scaled value +// +//***************************************************************************** +static uint32_t +ScaleCycleValues(uint32_t ui32SpecifiedTiming, uint32_t ui32ScaleValue) +{ + return((ui32SpecifiedTiming * ui32ScaleValue) >> 6); +} + +//***************************************************************************** +// +//! \internal +//! Used to set flash in read mode. +//! +//! Flash is configured with values loaded from OTP dependent on the current +//! regulator mode. +//! +//! \return None. +// +//***************************************************************************** +static void +SetReadMode(void) +{ + uint32_t ui32TrimValue; + uint32_t ui32Value; + + // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + // VIN_AT_X and VIN_BY_PASS for read mode + if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & + AON_PMCTL_PWRCTL_EXT_REG_MODE) + { + // Select trim values for external regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 4). + // Configure DIS_IDLE (OTP offset 0x308 bit 3). + ui32Value |= ((ui32TrimValue & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // Wait for disabled sample and hold functionality to be stable. + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 2:0) + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } + else + { + // Select trim values for internal regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 12). + // Configure DIS_IDLE (OTP offset 0x308 bit 11). + ui32Value |= ((ui32TrimValue & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // Wait for disabled sample and hold functionality to be stable. + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 10:8) + ui32Value = (((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S); + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} + +//***************************************************************************** +// +//! \internal +//! Used to set flash in write mode. +//! +//! Flash is configured with values loaded from OTP dependent on the current +//! regulator mode. +//! +//! \return None. +// +//***************************************************************************** +static void +SetWriteMode(void) +{ + uint32_t ui32TrimValue; + uint32_t ui32Value; + + // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + // VIN_AT_X and VIN_BY_PASS for program/erase mode + if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & + AON_PMCTL_PWRCTL_EXT_REG_MODE) + { + // Select trim values for external regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 23) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 22:21) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 20). + // Configure DIS_IDLE (OTP offset 0x308 bit 19). + ui32Value |= ((ui32TrimValue & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // Wait for disabled sample and hold functionality to be stable. + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 18:16) + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } + else + { + // Select trim values for internal regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 31) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 30:29) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 28). + // Configure DIS_IDLE (OTP offset 0x308 bit 27). + ui32Value |= ((ui32TrimValue & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S) << + FLASH_CFG_DIS_IDLE_S; + + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // Wait for disabled sample and hold functionality to be stable. + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 26:24) + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} + +void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast) { + uint32_t ui32SCLFreq; + uint32_t ui32TPR; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Must enable the device before doing anything else. + I2CMasterEnable(I2C0_BASE); + + // Get the desired SCL speed. + if(bFast == true) + { + ui32SCLFreq = 400000; + } + else + { + ui32SCLFreq = 100000; + } + + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biased to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / (2 * 10 * ui32SCLFreq)) - 1; + HWREG(I2C0_BASE + I2C_O_MTPR) = ui32TPR; +} + +uint32_t I2CMasterErr(uint32_t ui32Base) { + uint32_t ui32Err; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the raw error state. + ui32Err = HWREG(I2C0_BASE + I2C_O_MSTAT); + + // If the I2C master is busy, then all the other status bits are invalid, + // and there is no error to report. + if(ui32Err & I2C_MSTAT_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // Check for errors. + if(ui32Err & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST)) + { + return(ui32Err & (I2C_MSTAT_ARBLST | I2C_MSTAT_DATACK_N | I2C_MSTAT_ADRACK_N)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} +//***************************************************************************** +// +//! This is a mapping between priority grouping encodings and the number of +//! preemption priority bits. +// +//***************************************************************************** +static const uint32_t g_pui32Priority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; + +//***************************************************************************** +// +//! This is a mapping between interrupt number and the register that contains +//! the priority encoding for that interrupt. +// +//***************************************************************************** +static const uint32_t g_pui32Regs[] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13 +}; + +void IntPriorityGroupingSet(uint32_t ui32Bits) { + // Check the arguments. + ASSERT(ui32Bits < NUM_PRIORITY); + + // Set the priority grouping. + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; +} + +uint32_t IntPriorityGroupingGet(void) { + uint32_t ui32Loop, ui32Value; + + // Read the priority grouping. + ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // Loop through the priority grouping values. + for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++) + { + // Stop looping if this value matches. + if(ui32Value == g_pui32Priority[ui32Loop]) + { + break; + } + } + + // Return the number of priority bits. + return(ui32Loop); +} + +void IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority) { + uint32_t ui32Temp; + + // Check the arguments. + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + ASSERT(ui8Priority <= INT_PRI_LEVEL7); + + // Set the interrupt priority. + ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); + ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3))); + ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3)); + HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; +} + +int32_t IntPriorityGet(uint32_t ui32Interrupt) { + // Check the arguments. + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + + // Return the interrupt priority. + return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) & + 0xFF); +} + +void IntEnable(uint32_t ui32Interrupt) { + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to enable. + if(ui32Interrupt == INT_MEMMANAGE_FAULT) + { + // Enable the MemManage interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ui32Interrupt == INT_BUS_FAULT) + { + // Enable the bus fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ui32Interrupt == INT_USAGE_FAULT) + { + // Enable the usage fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Enable the System Tick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Enable the general interrupt. + HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Enable the general interrupt. + HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48); + } +} + +void IntDisable(uint32_t ui32Interrupt) { + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to disable. + if(ui32Interrupt == INT_MEMMANAGE_FAULT) + { + // Disable the MemManage interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ui32Interrupt == INT_BUS_FAULT) + { + // Disable the bus fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ui32Interrupt == INT_USAGE_FAULT) + { + // Disable the usage fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Disable the System Tick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Disable the general interrupt. + HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Disable the general interrupt. + HWREG(NVIC_DIS1) = 1 << (ui32Interrupt - 48); + } +} + +void IntPendSet(uint32_t ui32Interrupt) { + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to pend. + if(ui32Interrupt == INT_NMI_FAULT) + { + // Pend the NMI interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; + } + else if(ui32Interrupt == INT_PENDSV) + { + // Pend the PendSV interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Pend the SysTick interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Pend the general interrupt. + HWREG(NVIC_PEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Pend the general interrupt. + HWREG(NVIC_PEND1) = 1 << (ui32Interrupt - 48); + } +} + +bool IntPendGet(uint32_t ui32Interrupt) { + uint32_t ui32IntPending; + + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Assume no interrupts are pending. + ui32IntPending = 0; + + // The lower 16 IRQ vectors are unsupported by this function + if (ui32Interrupt < 16) + { + + return 0; + } + + // Subtract lower 16 irq vectors + ui32Interrupt -= 16; + + // Check if the interrupt is pending + ui32IntPending = HWREG(NVIC_PEND0 + (ui32Interrupt / 32)); + ui32IntPending &= (1 << (ui32Interrupt & 31)); + + return ui32IntPending ? true : false; +} + +void IntPendClear(uint32_t ui32Interrupt) { + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to unpend. + if(ui32Interrupt == INT_PENDSV) + { + // Unpend the PendSV interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Unpend the SysTick interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Unpend the general interrupt. + HWREG(NVIC_UNPEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Unpend the general interrupt. + HWREG(NVIC_UNPEND1) = 1 << (ui32Interrupt - 48); + } +} + +void IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the port. + HWREG(ui32Reg) = ui32IOConfig | ui32PortId; +} + +uint32_t IOCPortConfigureGet(uint32_t ui32IOId) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Return the IO configuration. + return HWREG(ui32Reg); +} + +void IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown) { + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) || + (ui32IOShutdown == IOC_WAKE_ON_LOW) || + (ui32IOShutdown == IOC_WAKE_ON_HIGH)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_WU_CFG_M; + HWREG(ui32Reg) = ui32Config | ui32IOShutdown; +} + +void IOCIOJTagSet(uint32_t ui32IOId, uint32_t ui32IOJTag) { + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOJTag == IOC_JTAG_TDO_ENABLE) || + (ui32IOJTag == IOC_JTAG_TDI_ENABLE) || + (ui32IOJTag == IOC_JTAG_DISABLE)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~(IOC_IOCFG0_TDI | IOC_IOCFG0_TDO); + HWREG(ui32Reg) = ui32Config | ui32IOJTag; +} + +void IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode) { + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) || + (ui32IOMode == IOC_IOMODE_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_INV)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_IOMODE_M; + HWREG(ui32Reg) = ui32Config | ui32IOMode; +} + +void IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Int == IOC_INT_ENABLE) || + (ui32Int == IOC_INT_DISABLE)); + ASSERT((ui32EdgeDet == IOC_NO_EDGE) || + (ui32EdgeDet == IOC_FALLING_EDGE) || + (ui32EdgeDet == IOC_RISING_EDGE) || + (ui32EdgeDet == IOC_BOTH_EDGES)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_EDGE_IRQ_EN | IOC_IOCFG0_EDGE_DET_M); + HWREG(ui32IOReg) = ui32Config | ((ui32Int ? IOC_IOCFG0_EDGE_IRQ_EN : 0) | ui32EdgeDet); +} + +void IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the argument. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Pull == IOC_NO_IOPULL) || + (ui32Pull == IOC_IOPULL_UP) || + (ui32Pull == IOC_IOPULL_DOWN)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PULL_CTL_M; + HWREG(ui32IOReg) = ui32Config | ui32Pull; +} + +void IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Hysteresis == IOC_HYST_ENABLE) || + (ui32Hysteresis == IOC_HYST_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_HYST_EN; + HWREG(ui32IOReg) = ui32Config | ui32Hysteresis; +} + +void IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Input == IOC_INPUT_ENABLE) || + (ui32Input == IOC_INPUT_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_IE; + HWREG(ui32IOReg) = ui32Config | ui32Input; +} + +void IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32SlewEnable == IOC_SLEW_ENABLE) || + (ui32SlewEnable == IOC_SLEW_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_SLEW_RED; + HWREG(ui32IOReg) = ui32Config | ui32SlewEnable; +} + +void IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOCurrent == IOC_CURRENT_2MA) || + (ui32IOCurrent == IOC_CURRENT_4MA) || + (ui32IOCurrent == IOC_CURRENT_8MA)); + ASSERT((ui32DrvStrength == IOC_STRENGTH_MIN) || + (ui32DrvStrength == IOC_STRENGTH_MAX) || + (ui32DrvStrength == IOC_STRENGTH_MED) || + (ui32DrvStrength == IOC_STRENGTH_AUTO)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_IOCURR_M | IOC_IOCFG0_IOSTR_M); + HWREG(ui32IOReg) = ui32Config | (ui32IOCurrent | ui32DrvStrength); +} + +void IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PORT_ID_M; + HWREG(ui32IOReg) = ui32Config | ui32PortId; +} + +void IOCIntEnable(uint32_t ui32IOId) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Enable the specified interrupt. + ui32Config = HWREG(ui32IOReg); + ui32Config |= IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} + +void IOCIntDisable(uint32_t ui32IOId) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Disable the specified interrupt. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} + +void IOCPinTypeGpioInput(uint32_t ui32IOId) { + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Setup the IO for standard input. + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_INPUT); + + // Enable input mode in the GPIO module. + GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_DISABLE); +} + +void IOCPinTypeGpioOutput(uint32_t ui32IOId) { + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Setup the IO for standard input. + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_OUTPUT); + + // Enable output mode in the GPIO module. + GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_ENABLE); +} + +void IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts) { + // Check the arguments. + ASSERT(ui32Base == UART0_BASE); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Cts <= IOID_31) || (ui32Cts == IOID_UNUSED)); + ASSERT((ui32Rts <= IOID_31) || (ui32Rts == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_UART0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_UART0_TX, IOC_STD_OUTPUT); + } + if(ui32Cts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Cts, IOC_PORT_MCU_UART0_CTS, IOC_STD_INPUT); + } + if(ui32Rts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rts, IOC_PORT_MCU_UART0_RTS, IOC_STD_OUTPUT); + } +} + +void IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk) { + // Check the arguments. + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_OUTPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_OUTPUT); + } + } +} + +void IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk) { + // Check the arguments. + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_INPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_INPUT); + } + } +} + +void IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk) { + uint32_t ui32IOConfig; + + // Check the arguments. + ASSERT((ui32Data <= IOID_31) || (ui32Data == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Define the IO configuration parameters. + ui32IOConfig = IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_IOPULL_UP | + IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | + IOC_INT_DISABLE | IOC_IOMODE_OPEN_DRAIN_NORMAL | + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE; + + // Setup the IOs in the desired configuration. + IOCPortConfigureSet(ui32Data, IOC_PORT_MCU_I2C_MSSDA, ui32IOConfig); + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_I2C_MSSCL, ui32IOConfig); +} + +void IOCPinTypeAux(uint32_t ui32IOId) { + // Check the arguments. + ASSERT((ui32IOId <= IOID_31) || (ui32IOId == IOID_UNUSED)); + + // Setup the IO. + IOCPortConfigureSet(ui32IOId, IOC_PORT_AUX_IO, IOC_STD_INPUT); +} + +//***************************************************************************** +// +// Arrays that maps the "peripheral set" number (which is stored in +// bits[11:8] of the PRCM_PERIPH_* defines) to the PRCM register that +// contains the relevant bit for that peripheral. +// +//***************************************************************************** + +// Run mode registers +static const uint32_t g_pui32RCGCRegs[] = +{ + PRCM_O_GPTCLKGR , // Index 0 + PRCM_O_SSICLKGR , // Index 1 + PRCM_O_UARTCLKGR , // Index 2 + PRCM_O_I2CCLKGR , // Index 3 + PRCM_O_SECDMACLKGR , // Index 4 + PRCM_O_GPIOCLKGR , // Index 5 + PRCM_O_I2SCLKGR // Index 6 +}; + +// Sleep mode registers +static const uint32_t g_pui32SCGCRegs[] = +{ + PRCM_O_GPTCLKGS , // Index 0 + PRCM_O_SSICLKGS , // Index 1 + PRCM_O_UARTCLKGS , // Index 2 + PRCM_O_I2CCLKGS , // Index 3 + PRCM_O_SECDMACLKGS , // Index 4 + PRCM_O_GPIOCLKGS , // Index 5 + PRCM_O_I2SCLKGS // Index 6 +}; + +// Deep sleep mode registers +static const uint32_t g_pui32DCGCRegs[] = +{ + PRCM_O_GPTCLKGDS , // Index 0 + PRCM_O_SSICLKGDS , // Index 1 + PRCM_O_UARTCLKGDS , // Index 2 + PRCM_O_I2CCLKGDS , // Index 3 + PRCM_O_SECDMACLKGDS , // Index 4 + PRCM_O_GPIOCLKGDS , // Index 5 + PRCM_O_I2SCLKGDS // Index 6 +}; + +//***************************************************************************** +// +// This macro extracts the array index out of the peripheral number +// +//***************************************************************************** +#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf) + +//***************************************************************************** +// +// This macro extracts the peripheral instance number and generates bit mask +// +//***************************************************************************** +#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0x1f)) + + +void PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode) { + uint32_t ui32Divisor; + + // Check the arguments. + ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || + (ui32ClkDiv == PRCM_CLOCK_DIV_2) || + (ui32ClkDiv == PRCM_CLOCK_DIV_8) || + (ui32ClkDiv == PRCM_CLOCK_DIV_32)); + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32Divisor = 0; + + // Find the correct division factor. + if(ui32ClkDiv == PRCM_CLOCK_DIV_1) + { + ui32Divisor = 0x0; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_2) + { + ui32Divisor = 0x1; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_8) + { + ui32Divisor = 0x2; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_32) + { + ui32Divisor = 0x3; + } + + // Determine the correct power mode set the division factor accordingly. + if(ui32PowerMode == PRCM_RUN_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor; + } +} + +uint32_t PRCMInfClockConfigureGet(uint32_t ui32PowerMode) { + uint32_t ui32ClkDiv; + uint32_t ui32Divisor; + + // Check the arguments. + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32ClkDiv = 0; + ui32Divisor = 0; + + // Determine the correct power mode. + if(ui32PowerMode == PRCM_RUN_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR); + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS); + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS); + } + + // Find the correct division factor. + if(ui32ClkDiv == 0x0) + { + ui32Divisor = PRCM_CLOCK_DIV_1; + } + else if(ui32ClkDiv == 0x1) + { + ui32Divisor = PRCM_CLOCK_DIV_2; + } + else if(ui32ClkDiv == 0x2) + { + ui32Divisor = PRCM_CLOCK_DIV_8; + } + else if(ui32ClkDiv == 0x3) + { + ui32Divisor = PRCM_CLOCK_DIV_32; + } + + // Return the clock division factor. + return ui32Divisor; +} + +void PRCMClockConfigureSet(uint32_t ui32Domains, uint32_t ui32ClkDiv) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_SYSBUS) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_TIMER) || + (ui32Domains & PRCM_DOMAIN_SERIAL)); + ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || + (ui32ClkDiv == PRCM_CLOCK_DIV_2) || + (ui32ClkDiv == PRCM_CLOCK_DIV_4) || + (ui32ClkDiv == PRCM_CLOCK_DIV_8) || + (ui32ClkDiv == PRCM_CLOCK_DIV_16) || + (ui32ClkDiv == PRCM_CLOCK_DIV_32) || + (ui32ClkDiv == PRCM_CLOCK_DIV_64) || + (ui32ClkDiv == PRCM_CLOCK_DIV_128) || + (ui32ClkDiv == PRCM_CLOCK_DIV_256)); + + // Configure the selected clock dividers. + if(ui32Domains & PRCM_DOMAIN_SYSBUS) + { + ui32Reg = PRCM_O_SYSBUSCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + ui32Reg = PRCM_O_CPUCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + ui32Reg = PRCM_O_PERBUSCPUCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + ui32Reg = PRCM_O_PERDMACLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_TIMER) + { + ui32Reg = PRCM_O_GPTCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } +} + +uint32_t PRCMClockConfigureGet(uint32_t ui32Domain) { + uint32_t ui32ClkDiv; + + // Check the arguments. + ASSERT((ui32Domain == PRCM_DOMAIN_SYSBUS) || + (ui32Domain == PRCM_DOMAIN_CPU) || + (ui32Domain == PRCM_DOMAIN_PERIPH) || + (ui32Domain == PRCM_DOMAIN_TIMER) || + (ui32Domain == PRCM_DOMAIN_SERIAL)); + + ui32ClkDiv = 0; + + // Find the correct sub system. + if(ui32Domain == PRCM_DOMAIN_SYSBUS) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_SYSBUSCLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_CPU) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_CPUCLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_PERIPH) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_PERBUSCPUCLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_SERIAL) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_PERDMACLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_TIMER) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_GPTCLKDIV); + } + + // Return the clock configuration. + return(ui32ClkDiv); +} + +void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate) { + uint32_t ui32Reg; + uint32_t ui32MstDiv; + uint32_t ui32BitDiv; + uint32_t ui32WordDiv; + + // Check the arguments. + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) || + (ui32SampleRate == I2S_SAMPLE_RATE_24K) || + (ui32SampleRate == I2S_SAMPLE_RATE_32K) || + (ui32SampleRate == I2S_SAMPLE_RATE_48K)); + + ui32MstDiv = 0; + ui32BitDiv = 0; + ui32WordDiv = 0; + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Define the clock division factors for the audio interface. + switch(ui32SampleRate) + { + case I2S_SAMPLE_RATE_16K : + ui32MstDiv = 6; + ui32BitDiv = 60; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_24K : + ui32MstDiv = 4; + ui32BitDiv = 40; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_32K : + ui32MstDiv = 3; + ui32BitDiv = 30; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_48K : + ui32MstDiv = 2; + ui32BitDiv = 20; + ui32WordDiv = 25; + break; + } + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity. + ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} + +void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, uint32_t ui32BitDiv, uint32_t ui32WordDiv) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity. + ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} + +void PRCMPowerDomainOn(uint32_t ui32Domains) { + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Assert the request to power on the right domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 1; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 1; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 1; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 1; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 1; + } +} + +void PRCMPowerDomainOff(uint32_t ui32Domains) { + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Assert the request to power off the right domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 0; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 0; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 0; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + // Write bits ui32Domains[17:16] to the VIMS_MODE alias register. + // PRCM_DOMAIN_VIMS sets VIMS_MODE=0b00, PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP sets VIMS_MODE=0b10. + ASSERT(!(ui32Domains & 0x00010000)); + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = ( ui32Domains >> 16 ) & 3; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 0; + } +} + +void PRCMPeripheralRunEnable(uint32_t ui32Peripheral) { + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable module in Run Mode. + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +void PRCMPeripheralRunDisable(uint32_t ui32Peripheral) { + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable module in Run Mode. + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +void PRCMPeripheralSleepEnable(uint32_t ui32Peripheral) { + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable this peripheral in sleep mode. + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +void PRCMPeripheralSleepDisable(uint32_t ui32Peripheral) { + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable this peripheral in sleep mode + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +void PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral) { + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable this peripheral in deep-sleep mode. + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +void PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral) { + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable this peripheral in Deep Sleep mode. + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +uint32_t PRCMPowerDomainStatus(uint32_t ui32Domains) { + bool bStatus; + uint32_t ui32StatusRegister0; + uint32_t ui32StatusRegister1; + + // Check the arguments. + ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE | + PRCM_DOMAIN_SERIAL | + PRCM_DOMAIN_PERIPH))); + + bStatus = true; + ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0); + ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1); + + // Return the correct power status. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + bStatus = bStatus && + ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) || + (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON)); + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON); + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON); + } + + // Return the status. + return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF); +} + +void PRCMDeepSleep(void) { + // Enable deep-sleep. + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // Wait for an interrupt. + CPUwfi(); + + // Disable deep-sleep so that a future sleep will work correctly. + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} + +void PRCMRetentionEnable(uint32_t ui32PowerDomain) { + uint32_t ui32Retention; + + // Check the arguments. + ASSERT(PRCM_DOMAIN_CPU & ui32PowerDomain); + + // Get the current register values. + ui32Retention = HWREG(PRCM_BASE + PRCM_O_RAMRETEN); + + // Enable retention on RF core SRAM. + if(PRCM_DOMAIN_RFCORE & ui32PowerDomain) + { + ui32Retention |= PRCM_RAMRETEN_RFC_M; + } + + // Enable retention on VIMS cache. + if(PRCM_DOMAIN_VIMS & ui32PowerDomain) + { + ui32Retention |= PRCM_RAMRETEN_VIMS_M; + } + + // Enable retention on RFC ULL SRAM. + if(PRCM_DOMAIN_RFCULL_SRAM & ui32PowerDomain) + { + ui32Retention |= PRCM_RAMRETEN_RFCULL_M; + } + + // Reconfigure retention. + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention; +} + +void PRCMRetentionDisable(uint32_t ui32PowerDomain) { + uint32_t ui32Retention; + + // Check the arguments. + ASSERT(PRCM_DOMAIN_CPU & ui32PowerDomain); + + // Get the current register values + ui32Retention = HWREG(PRCM_BASE + PRCM_O_RAMRETEN); + + // Disable retention on RF core SRAM + if(PRCM_DOMAIN_RFCORE & ui32PowerDomain) + { + ui32Retention &= ~PRCM_RAMRETEN_RFC_M; + } + + // Disable retention on VIMS cache + if(PRCM_DOMAIN_VIMS & ui32PowerDomain) + { + ui32Retention &= ~PRCM_RAMRETEN_VIMS_M; + } + + // Disable retention on RFC ULL SRAM. + if(PRCM_DOMAIN_RFCULL_SRAM & ui32PowerDomain) + { + ui32Retention &= ~PRCM_RAMRETEN_RFCULL_M; + } + + // Reconfigure retention. + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention; +} + +void SMPHAcquire(uint32_t ui32Semaphore) { + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // Wait for semaphore to be release such that it can be claimed + // Semaphore register reads 1 when lock was acquired otherwise 0 + // (i.e. SMPH_CLAIMED). + while(HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) == + SMPH_CLAIMED) + { + } +} + +void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth) { + uint32_t ui32MaxBitRate; + uint32_t ui32RegVal; + uint32_t ui32PreDiv; + uint32_t ui32SCR; + uint32_t ui32SPH_SPO; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || + (ui32Protocol == SSI_FRF_MOTO_MODE_1) || + (ui32Protocol == SSI_FRF_MOTO_MODE_2) || + (ui32Protocol == SSI_FRF_MOTO_MODE_3) || + (ui32Protocol == SSI_FRF_TI) || + (ui32Protocol == SSI_FRF_NMW)); + ASSERT((ui32Mode == SSI_MODE_MASTER) || + (ui32Mode == SSI_MODE_SLAVE) || + (ui32Mode == SSI_MODE_SLAVE_OD)); + ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) || + ((ui32Mode != SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 12)))); + ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); + ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); + + // Set the mode. + ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; + + // Set the clock predivider. + ui32MaxBitRate = ui32SSIClk / ui32BitRate; + ui32PreDiv = 0; + do + { + ui32PreDiv += 2; + ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; + } + while(ui32SCR > 255); + HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; + + // Set protocol and clock rate. + ui32SPH_SPO = (ui32Protocol & 3) << 6; + ui32Protocol &= SSI_CR0_FRF_M; + ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | (ui32DataWidth - 1); + HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; +} + +int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) { + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // Check for space to write. + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ui32Base + SSI_O_DR) = ui32Data; + return(1); + } + else + { + return(0); + } +} + +void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) { + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // Wait until there is space. + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // Write the data to the SSI. + HWREG(ui32Base + SSI_O_DR) = ui32Data; +} + +void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) { + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Wait until there is data to be read. + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // Read data from SSI. + *pui32Data = HWREG(ui32Base + SSI_O_DR); +} + +int32_t SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) { + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Check for data to read. + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) + { + *pui32Data = HWREG(ui32Base + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} + +void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) { + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || + (ui32Config == TIMER_CFG_ONE_SHOT_UP) || + (ui32Config == TIMER_CFG_PERIODIC) || + (ui32Config == TIMER_CFG_PERIODIC_UP) || + ((ui32Config & 0xFF000000) == TIMER_CFG_SPLIT_PAIR)); + ASSERT(((ui32Config & 0xFF000000) != TIMER_CFG_SPLIT_PAIR) || + ((((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PWM)) && + (((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PWM)))); + + // Disable the timers. + HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); + + // Set the global timer configuration. + HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24; + + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE; + HWREG(ui32Base + GPT_O_TBMR) = + ((ui32Config >> 8) & 0xFF) | GPT_TBMR_TBPWMIE; +} + +void TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) { + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the output levels as requested. + ui32Timer &= GPT_CTL_TAPWML | GPT_CTL_TBPWML; + HWREG(ui32Base + GPT_O_CTL) = (bInvert ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & + ~(ui32Timer))); +} + +void TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall) { + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the stall mode. + ui32Timer &= GPT_CTL_TASTALL | GPT_CTL_TBSTALL; + HWREG(ui32Base + GPT_O_CTL) = (bStall ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer))); +} + +void TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait) { + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the wait on trigger mode for timer A. + if(ui32Timer & TIMER_A) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAWOT; + } + else + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAWOT); + } + } + + // Set the wait on trigger mode for timer B. + if(ui32Timer & TIMER_B) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBWOT; + } + else + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBWOT); + } + } +} + +void TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) { + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); + ASSERT((ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) || (ui32Mode == TIMER_MATCHUPDATE_TIMEOUT)); + + // Set mode for timer A + if(ui32Timer & TIMER_A) + { + if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAMRSU); + } + else + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAMRSU; + } + } + + // Set mode for timer B + if(ui32Timer & TIMER_B) + { + if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBMRSU); + } + else + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBMRSU; + } + } +} + +void TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) { + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); + ASSERT((ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) || (ui32Mode == TIMER_INTERVALLOAD_TIMEOUT)); + + // Set mode for timer A + if(ui32Timer & TIMER_A) + { + if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAILD); + } + else + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAILD; + } + } + + // Set mode for timer B + if(ui32Timer & TIMER_B) + { + if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBILD); + } + else + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBILD; + } + } +} + +void TRNGConfigure(uint32_t ui32MinSamplesPerCycle, uint32_t ui32MaxSamplesPerCycle, uint32_t ui32ClocksPerSample) { + uint32_t ui32Val; + + // Make sure the TRNG is disabled. + ui32Val = HWREG(TRNG_BASE + TRNG_O_CTL) & ~TRNG_CTL_TRNG_EN; + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // Configure the startup number of samples. + ui32Val &= ~TRNG_CTL_STARTUP_CYCLES_M; + ui32Val |= ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CTL_STARTUP_CYCLES_S ) & TRNG_CTL_STARTUP_CYCLES_M ); + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // Configure the minimum and maximum number of samples pr generated number + // and the number of clocks per sample. + HWREG(TRNG_BASE + TRNG_O_CFG0) = ( + ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CFG0_MAX_REFILL_CYCLES_S ) & TRNG_CFG0_MAX_REFILL_CYCLES_M ) | + ((( ui32ClocksPerSample ) << TRNG_CFG0_SMPL_DIV_S ) & TRNG_CFG0_SMPL_DIV_M ) | + ((( ui32MinSamplesPerCycle >> 6 ) << TRNG_CFG0_MIN_REFILL_CYCLES_S ) & TRNG_CFG0_MIN_REFILL_CYCLES_M ) ); +} + +uint32_t TRNGNumberGet(uint32_t ui32Word) { + uint32_t ui32RandomNumber; + + // Check the arguments. + ASSERT((ui32Word == TRNG_HI_WORD) || + (ui32Word == TRNG_LOW_WORD)); + + // Return the right requested part of the generated number. + if(ui32Word == TRNG_HI_WORD) + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT1); + } + else + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT0); + } + + // Initiate generation of new number. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1; + + // Return the random number. + return ui32RandomNumber; +} + +void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel) { + uint32_t ui32Temp; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Read the FIFO level register. + ui32Temp = HWREG(ui32Base + UART_O_IFLS); + + // Extract the transmit and receive FIFO levels. + *pui32TxLevel = ui32Temp & UART_IFLS_TXSEL_M; + *pui32RxLevel = ui32Temp & UART_IFLS_RXSEL_M; +} + +void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config) { + uint32_t ui32Div; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT(ui32Baud != 0); + + // Stop the UART. + UARTDisable(ui32Base); + + // Compute the fractional baud rate divider. + ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; + + // Set the baud rate. + HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; + HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; + + // Set parity, data length, and number of stop bits. + HWREG(ui32Base + UART_O_LCRH) = ui32Config; +} + +void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config) { + uint32_t ui32Int, ui32Frac; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Compute the baud rate. + ui32Int = HWREG(ui32Base + UART_O_IBRD); + ui32Frac = HWREG(ui32Base + UART_O_FBRD); + *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); + + // Get the parity, data length, and number of stop bits. + *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | + UART_LCRH_EPS | UART_LCRH_PEN)); +} + +void UARTDisable(uint32_t ui32Base) { + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait for end of TX. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) + { + } + + // Disable the FIFO. + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); + + // Disable the UART. + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +int32_t UARTCharGetNonBlocking(uint32_t ui32Base) { + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // See if there are any characters in the receive FIFO. + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) + { + // Read and return the next character. + return(HWREG(ui32Base + UART_O_DR)); + } + else + { + // There are no characters, so return a failure. + return(-1); + } +} + +int32_t UARTCharGet(uint32_t ui32Base) { + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait until a char is available. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) + { + } + + // Now get the character. + return(HWREG(ui32Base + UART_O_DR)); +} + +bool UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) { + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // See if there is space in the transmit FIFO. + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) + { + // Write this character to the transmit FIFO. + HWREG(ui32Base + UART_O_DR) = ui8Data; + + // Success. + return(true); + } + else + { + // There is no space in the transmit FIFO, so return a failure. + return(false); + } +} + +void UARTCharPut(uint32_t ui32Base, uint8_t ui8Data) { + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait until space is available. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) + { + } + + // Send the char. + HWREG(ui32Base + UART_O_DR) = ui8Data; +} + +void uDMAChannelAttributeEnable(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr) { + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Set the useburst bit for this channel if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_SETBURST) = 1 << ui32ChannelNum; + } + + // Set the alternate control select bit for this channel, + // if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // Set the high priority bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // Set the request mask bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_SETREQMASK) = 1 << ui32ChannelNum; + } +} + +void uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr) { + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Clear the useburst bit for this channel if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_CLEARBURST) = 1 << ui32ChannelNum; + } + + // Clear the alternate control select bit for this channel, if set in + // ululAttr. + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // Clear the high priority bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // Clear the request mask bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_CLEARREQMASK) = 1 << ui32ChannelNum; + } +} + +uint32_t uDMAChannelAttributeGet(uint32_t ui32Base, uint32_t ui32ChannelNum) { + uint32_t ui32Attr = 0; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Check to see if useburst bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETBURST) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_USEBURST; + } + + // Check to see if the alternate control bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_ALTSELECT; + } + + // Check to see if the high priority bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // Check to see if the request mask bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETREQMASK) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_REQMASK; + } + + // Return the configuration flags. + return(ui32Attr); +} + +void uDMAChannelControlSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control) { + tDMAControlTable *pControlTable; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + pControlTable[ui32ChannelStructIndex].ui32Control = + ((pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_DST_INC_M | + UDMA_SRC_INC_M | + UDMA_SIZE_M | + UDMA_ARB_M | + UDMA_NEXT_USEBURST)) | + ui32Control); +} + +void uDMAChannelTransferSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize) { + tDMAControlTable *pControlTable; + uint32_t ui32Control; + uint32_t ui32Inc; + uint32_t ui32BufferBytes; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((uint32_t)pvSrcAddr >= SRAM_BASE); + ASSERT((uint32_t)pvDstAddr >= SRAM_BASE); + ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= UDMA_XFER_SIZE_MAX)); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off the mode and size + // fields. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // Adjust the mode if the alt control structure is selected. + if(ui32ChannelStructIndex & UDMA_ALT_SELECT) + { + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Mode |= UDMA_MODE_ALT_SELECT; + } + } + + // Set the transfer size and mode in the control word (but don't write the + // control word yet as it could kick off a transfer). + ui32Control |= ui32Mode | ((ui32TransferSize - 1) << UDMA_XFER_SIZE_S); + + // Get the address increment value for the source, from the control word. + ui32Inc = (ui32Control & UDMA_SRC_INC_M); + + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + if(ui32Inc != UDMA_SRC_INC_NONE) + { + ui32Inc = ui32Inc >> UDMA_SRC_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - (1 << ui32Inc)); + } + + // Load the source ending address into the control block. + pControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; + + // Get the address increment value for the destination, from the control + // word. + ui32Inc = ui32Control & UDMA_DST_INC_M; + + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + if(ui32Inc != UDMA_DST_INC_NONE) + { + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer needs to point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + pvDstAddr = + (void *)&pControlTable[ui32ChannelStructIndex | + UDMA_ALT_SELECT].ui32Spare; + } + // Not a scatter-gather transfer, calculate end pointer normally. + else + { + ui32Inc = ui32Inc >> UDMA_DST_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); + } + } + + // Load the destination ending address into the control block. + pControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; + + // Write the new control word value. + pControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; +} + +void uDMAChannelScatterGatherSet(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG) { + tDMAControlTable *pControlTable; + tDMAControlTable *pTaskTable; + + // Check the parameters. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(pvTaskList != 0); + ASSERT(ui32TaskCount <= UDMA_XFER_SIZE_MAX); + ASSERT(ui32TaskCount != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get a handy pointer to the task list. + pTaskTable = (tDMAControlTable *)pvTaskList; + + // Compute the ending address for the source pointer. This will be the + // last element of the last task in the task table. + pControlTable[ui32ChannelNum].pvSrcEndAddr = + &pTaskTable[ui32TaskCount - 1].ui32Spare; + + // Compute the ending address for the destination pointer. This will be + // the end of the alternate structure for this channel. + pControlTable[ui32ChannelNum].pvDstEndAddr = + &pControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; + + // Compute the control word. Most configurable items are fixed for + // scatter-gather. Item and increment sizes are all 32-bit and arb + // size must be 4. The count is the number of items in the task list + // times 4 (4 words per task). + pControlTable[ui32ChannelNum].ui32Control = + (UDMA_DST_INC_32 | UDMA_SRC_INC_32 | + UDMA_SIZE_32 | UDMA_ARB_4 | + (((ui32TaskCount * 4) - 1) << UDMA_XFER_SIZE_S) | + (ui32IsPeriphSG ? UDMA_MODE_PER_SCATTER_GATHER : + UDMA_MODE_MEM_SCATTER_GATHER)); + + // Scatter-gather operations can leave the alt bit set. So if doing + // back to back scatter-gather transfers, the second attempt may not + // work correctly because the alt bit is set. Therefore, clear the + // alt bit here to ensure that it is always cleared before a new SG + // transfer is started. + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + +} + +uint32_t uDMAChannelSizeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) { + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off all but the size field + // and the mode field. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + (UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // If the size field and mode field are 0 then the transfer is finished + // and there are no more items to transfer. + if(ui32Control == 0) + { + return(0); + } + + // Otherwise, if either the size field or more field is non-zero, then + // not all the items have been transferred. + else + { + // Shift the size field and add one, then return to user. + return((ui32Control >> UDMA_XFER_SIZE_S) + 1); + } +} + +uint32_t uDMAChannelModeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) { + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off all but the mode field. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + UDMA_MODE_M); + + // Check if scatter/gather mode, and if so, mask off the alt bit. + if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || + ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Control &= ~UDMA_MODE_ALT_SELECT; + } + + // Return the mode to the caller. + return(ui32Control); +} + +void VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG); + if(bRoundRobin) + { + ui32Reg |= VIMS_CTL_ARB_CFG; + } + if(bPrefetch) + { + ui32Reg |= VIMS_CTL_PREF_EN; + } + + // Set the Arbitration and prefetch mode. + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +void VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ASSERT((ui32Mode == VIMS_MODE_DISABLED) || + (ui32Mode == VIMS_MODE_ENABLED) || + (ui32Mode == VIMS_MODE_OFF)); + + // Set the mode. + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~VIMS_CTL_MODE_M; + ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M); + + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +uint32_t VIMSModeGet(uint32_t ui32Base) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_STAT); + if(ui32Reg & VIMS_STAT_MODE_CHANGING) + { + return (VIMS_MODE_CHANGING); + } + else + { + return (ui32Reg & VIMS_STAT_MODE_M); + } +} + +void VIMSModeSafeSet( uint32_t ui32Base, uint32_t ui32NewMode, bool blocking ) { + uint32_t currentMode; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + ASSERT((ui32NewMode == VIMS_MODE_DISABLED) || + (ui32NewMode == VIMS_MODE_ENABLED) || + (ui32NewMode == VIMS_MODE_OFF)); + + // Make sure that only the mode bits are set in the input parameter + // (done just for security since it is critical to the code flow) + ui32NewMode &= VIMS_CTL_MODE_M; + + // Wait for any pending change to complete and get current VIMS mode + // (This is a blocking point but will typically only be a blocking point + // only if mode is changed multiple times with blocking=0) + do { + currentMode = VIMSModeGet( ui32Base ); + } while ( currentMode == VIMS_MODE_CHANGING ); + + // First check that it actually is a mode change request + if ( ui32NewMode != currentMode ) { + // Set new mode + VIMSModeSet( ui32Base, ui32NewMode ); + + // Wait for final mode change to complete - if blocking is requested + if ( blocking ) { + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for change to complete. + } + } + } +} + +void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc) { + // Check the arguments. + ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || + (ui32SrcClk & OSC_SRC_CLK_HF)); + ASSERT((ui32Osc == OSC_RCOSC_HF) || + (ui32Osc == OSC_RCOSC_LF) || + (ui32Osc == OSC_XOSC_HF) || + (ui32Osc == OSC_XOSC_LF)); + + // Request the high frequency source clock (using 24 MHz XTAL) + if(ui32SrcClk & OSC_SRC_CLK_HF) + { + // Enable the HF XTAL as HF clock source + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S, + ui32Osc); + } + + // Configure the low frequency source clock. + if(ui32SrcClk & OSC_SRC_CLK_LF) + { + // Change the clock source. + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S, + ui32Osc); + } +} + +uint32_t OSCClockSourceGet(uint32_t ui32SrcClk) { + uint32_t ui32ClockSource; + + // Check the arguments. + ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || + (ui32SrcClk & OSC_SRC_CLK_HF)); + + // Return the source for the selected clock. + if(ui32SrcClk == OSC_SRC_CLK_LF) + { + ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_SCLK_LF_SRC_M, + DDI_0_OSC_STAT0_SCLK_LF_SRC_S); + } + else + { + ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_SCLK_HF_SRC_M, + DDI_0_OSC_STAT0_SCLK_HF_SRC_S); + } + return (ui32ClockSource); +} + +int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ) { + // Estimate HPOSC frequency, using temperature and curve fitting parameters + uint32_t fitParams = HWREG(FCFG1_BASE + FCFG1_O_FREQ_OFFSET); + // Extract the P0,P1,P2 params, and sign extend them via shifting up/down + int32_t paramP0 = ((((int32_t) fitParams) << (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S)) + >> (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W)); + int32_t paramP1 = ((((int32_t) fitParams) << (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S)) + >> (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W)); + int32_t paramP2 = ((((int32_t) fitParams) << (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S)) + >> (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W)); + int32_t paramP3 = ((((int32_t) HWREG(FCFG1_BASE + FCFG1_O_MISC_CONF_2)) + << (32 - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S)) + >> (32 - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W)); + + // Now we can find the HPOSC freq offset, given as a signed variable d, expressed by: + // + // F_HPOSC = F_nom * (1 + d/(2^22)) , where: F_HPOSC = HPOSC frequency + // F_nom = nominal clock source frequency (e.g. 48.000 MHz) + // d = describes relative freq offset + + // We can estimate the d variable, using temperature compensation parameters: + // + // d = P0 + P1*(t - T0) + P2*(t - T0)^2 + P3*(t - T0)^3, where: P0,P1,P2,P3 are curve fitting parameters from FCFG1 + // t = current temperature (from temp sensor) in deg C + // T0 = 27 deg C (fixed temperature constant) + int32_t tempDelta = (tempDegC - 27); + int32_t tempDeltaX2 = tempDelta * tempDelta; + int32_t d = paramP0 + ((tempDelta*paramP1)>>3) + ((tempDeltaX2*paramP2)>>10) + ((tempDeltaX2*tempDelta*paramP3)>>18); + + return ( d ); +} + +int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ) { + // The input argument, hereby referred to simply as "d", describes the frequency offset + // of the HPOSC relative to the nominal frequency in this way: + // + // F_HPOSC = F_nom * (1 + d/(2^22)) + // + // But for use by the radio, to compensate the frequency error, we need to find the + // frequency offset "rfcFreqOffset" defined in the following format: + // + // F_nom = F_HPOSC * (1 + rfCoreFreqOffset/(2^22)) + // + // To derive "rfCoreFreqOffset" from "d" we combine the two above equations and get: + // + // (1 + rfCoreFreqOffset/(2^22)) = (1 + d/(2^22))^-1 + // + // Which can be rewritten into: + // + // rfCoreFreqOffset = -d*(2^22) / ((2^22) + d) + // + // = -d * [ 1 / (1 + d/(2^22)) ] + // + // To avoid doing a 64-bit division due to the (1 + d/(2^22))^-1 expression, + // we can use Taylor series (Maclaurin series) to approximate it: + // + // 1 / (1 - x) ~= 1 + x + x^2 + x^3 + x^4 + ... etc (Maclaurin series) + // + // In our case, we have x = - d/(2^22), and we only include up to the first + // order term of the series, as the second order term ((d^2)/(2^44)) is very small: + // + // freqError ~= -d + d^2/(2^22) (+ small approximation error) + // + // The approximation error is negligible for our use. + + int32_t rfCoreFreqOffset = -HPOSC_RelFreqOffset + (( HPOSC_RelFreqOffset * HPOSC_RelFreqOffset ) >> 22 ); + + return ( rfCoreFreqOffset ); +} + +void AUXADCDisable(void) { + // Disable the ADC reference + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, ADI_4_AUX_ADCREF0_EN_M | ADI_4_AUX_ADCREF0_REF_ON_IDLE_M | ADI_4_AUX_ADCREF0_SRC_M); + + // Assert reset and disable the ADC + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M | ADI_4_AUX_ADC0_SMPL_MODE_M | ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M); + + // Ensure that scaling is enabled by default before next use of the ADC + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); + + // Flush the FIFO before disabling the clocks + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) + + // Disable the ADC clock (no need to wait since IOB_WUC_ADCCLKCTL_ACK goes low immediately) + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = 0; + + // Disable the ADC data interface + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = 0; +} + +void AUXADCEnableAsync(uint32_t refSource, uint32_t trigger) { + // Enable the ADC reference, with the following options: + // - SRC: Set when using relative reference + // - REF_ON_IDLE: Always cleared since there is no idle state in asynchronous operation + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, refSource | ADI_4_AUX_ADCREF0_EN_M); + + // Enable the ADC clock + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M; + while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M)); + + // Enable the ADC data interface + if (trigger == AUXADC_TRIGGER_MANUAL) { + // Manual trigger: No need to configure event routing from GPT + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN; + } else { + // GPT trigger: Configure event routing via MCU_EV to the AUX domain + HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; + } + + // Configure the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_SMPL_MODE_M); + + // Release reset and enable the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); +} + +void AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger) { + // Enable the ADC reference, with the following options: + // - SRC: Set when using relative reference + // - REF_ON_IDLE: Set when using fixed reference and sample time < 21.3 us + uint8_t adcref0 = refSource | ADI_4_AUX_ADCREF0_EN_M; + if (!refSource && (sampleTime < AUXADC_SAMPLE_TIME_21P3_US)) { + adcref0 |= ADI_4_AUX_ADCREF0_REF_ON_IDLE_M; + } + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, adcref0); + + // Enable the ADC clock + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M; + while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M)); + + // Enable the ADC data interface + if (trigger == AUXADC_TRIGGER_MANUAL) { + // Manual trigger: No need to configure event routing from GPT + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN; + } else { + // GPT trigger: Configure event routing via MCU_EV to the AUX domain + HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; + } + + // Configure the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, sampleTime << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S); + + // Release reset and enable the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); +} + +void AUXADCDisableInputScaling(void) { + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); +} + +void AUXADCFlushFifo(void) { + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) +} + +uint32_t AUXADCReadFifo(void) { + + // Wait until there is at least one sample in the FIFO + while (HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT) & AUX_ANAIF_ADCFIFOSTAT_EMPTY_M); + + // Return the first sample from the FIFO + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +uint32_t AUXADCPopFifo(void) { + + // Return the first sample from the FIFO. If the FIFO is empty, this + // generates ADC FIFO underflow + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +int32_t AUXADCGetAdjustmentGain(uint32_t refSource) { + int32_t gain; + if (refSource == AUXADC_REF_FIXED) { + // AUXADC_REF_FIXED ==> ABS_GAIN + gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_ABS_GAIN) & FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S; + } else { + // AUXADC_REF_VDDS_REL ==> REL_GAIN + gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_REL_GAIN) & FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S; + } + return gain; +} + +int32_t AUXADCGetAdjustmentOffset(uint32_t refSource) { + int8_t offset; + if ( refSource == AUXADC_REF_FIXED ) { + // AUXADC_REF_FIXED ==> ABS_OFFSET + offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S; + } else { + // AUXADC_REF_VDDS_REL ==> REL_OFFSET + offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S; + } + return offset; +} + +int32_t AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue) { + // Chop off 4 bits during calculations to avoid 32-bit overflow + fixedRefVoltage >>= 4; + return (((adcValue * fixedRefVoltage) + 2047) / 4095) << 4; +} + +int32_t AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts) { + // Chop off 4 bits during calculations to avoid 32-bit overflow + fixedRefVoltage >>= 4; + microvolts >>= 4; + return ((microvolts * 4095) + (fixedRefVoltage / 2)) / fixedRefVoltage; +} + +int32_t AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) { + // Apply gain and offset adjustment + adcValue = (((adcValue + offset) * gain) + 16384) / 32768; + + // Saturate + if (adcValue < 0) { + return 0; + } else if (adcValue > 4095) { + return 4095; + } else { + return adcValue; + } +} + +int32_t AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) { + // Apply inverse gain and offset adjustment + adcValue = (((adcValue * 32768) + (gain / 2)) / gain) - offset; + + // Saturate + if (adcValue < 0) { + return 0; + } else if (adcValue > 4095) { + return 4095; + } else { + return adcValue; + } +} + +void SysCtrl_DCDC_VoltageConditionalControl( void ) { + uint32_t batThreshold ; // Fractional format with 8 fractional bits. + uint32_t aonBatmonBat ; // Fractional format with 8 fractional bits. + uint32_t ccfg_ModeConfReg ; // Holds a copy of the CCFG_O_MODE_CONF register. + uint32_t aonPmctlPwrctl ; // Reflect whats read/written to the AON_PMCTL_O_PWRCTL register. + + // We could potentially call this function before any battery voltage measurement + // is made/available. In that case we must make sure that we do not turn off the DCDC. + // This can be done by doing nothing as long as the battery voltage is 0 (Since the + // reset value of the battery voltage register is 0). + aonBatmonBat = HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT ); + if ( aonBatmonBat != 0 ) { + // Check if Voltage Conditional Control is enabled + // It is enabled if all the following are true: + // - DCDC in use (either in active or recharge mode), (in use if one of the corresponding CCFG bits are zero). + // - Alternative DCDC settings are enabled ( DIS_ALT_DCDC_SETTING == 0 ) + // - Not in external regulator mode ( EXT_REG_MODE == 0 ) + ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + + if (((( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) || + (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) ) && + (( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) == 0 ) && + (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) ) + { + aonPmctlPwrctl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ); + batThreshold = (((( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & + CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) >> + CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) + 28 ) << 4 ); + + if ( aonPmctlPwrctl & ( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M )) { + // DCDC is ON, check if it should be switched off + if ( aonBatmonBat < batThreshold ) { + aonPmctlPwrctl &= ~( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M ); + + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl; + } + } else { + // DCDC is OFF, check if it should be switched on + if ( aonBatmonBat > batThreshold ) { + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_EN_M ; + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_ACTIVE_M ; + + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl; + } + } + } + } +} + +uint32_t SysCtrlResetSourceGet( void ) { + uint32_t aonPmctlResetCtl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ); + + if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_WU_FROM_SD_M ) { + if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M ) { + return ( RSTSRC_WAKEUP_FROM_SHUTDOWN ); + } else { + return ( RSTSRC_WAKEUP_FROM_TCK_NOISE ); + } + } else { + return (( aonPmctlResetCtl & AON_PMCTL_RESETCTL_RESET_SRC_M ) >> AON_PMCTL_RESETCTL_RESET_SRC_S ); + } +} + +int32_t AONBatMonTemperatureGetDegC( void ) { + int32_t signedTemp ; // Signed extended temperature with 8 fractional bits + int32_t tempCorrection ; // Voltage dependent temp correction with 8 fractional bits + int8_t voltageSlope ; // Signed byte value representing the TEMP slope with battery voltage, in degrees C/V, with 4 fractional bits. + + // Shift left then right to sign extend the BATMON_TEMP field + signedTemp = ((((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_TEMP )) + << ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )) + >> ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )); + + // Typecasting voltageSlope to int8_t prior to assignment in order to make sure sign extension works properly + // Using byte read (HWREGB) in order to make more efficient code since voltageSlope is assigned to bits[7:0] of FCFG1_O_MISC_TRIM + voltageSlope = ((int8_t)HWREGB( FCFG1_BASE + FCFG1_O_MISC_TRIM )); + tempCorrection = (( voltageSlope * (((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT )) - 0x300 )) >> 4 ); + + return ((( signedTemp - tempCorrection ) + 0x80 ) >> 8 ); +} + +void SetupStepVddrTrimTo( uint32_t toCode ) { + uint32_t pmctlResetctl_reg ; + int32_t targetTrim ; + int32_t currentTrim ; + + targetTrim = SetupSignExtendVddrTrimValue( toCode & ( ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M >> ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S )); + currentTrim = SetupSignExtendVddrTrimValue(( + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) >> + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) ; + + if ( targetTrim != currentTrim ) { + pmctlResetctl_reg = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M ); + if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) { + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ( pmctlResetctl_reg & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ); + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for VDDR_LOSS_EN setting to propagate + } + + while ( targetTrim != currentTrim ) { + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + + if ( targetTrim > currentTrim ) currentTrim++; + else currentTrim--; + + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) = ( + ( HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & ~ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) | + ((((uint32_t)currentTrim) << ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) & + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) ); + } + + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + + if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) { + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = pmctlResetctl_reg; + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // And finally wait for VDDR_LOSS_EN setting to propagate + } + } +} + +void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ) { + // Check for CC1352 boost mode + // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode + if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) && + (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) ) + { + // Set VDDS_BOD trim - using masked write {MASK8:DATA8} + // - TRIM_VDDS_BOD is bits[7:3] of ADI3..REFSYSCTL1 + // - Needs a positive transition on BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to + // latch new VDDS BOD. Set to 0 first to guarantee a positive transition. + HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; + // + // VDDS_BOD_LEVEL = 1 means that boost mode is selected + // - Max out the VDDS_BOD trim (=VDDS_BOD_POS_31) + HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) = + ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8 ) | + ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 ) ; + HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; + + SetupStepVddrTrimTo(( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) & + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >> + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ; + } + + // 1. + // Do not allow DCDC to be enabled if in external regulator mode. + // Preventing this by setting both the RECHARGE and the ACTIVE bits bit in the CCFG_MODE_CONF copy register (ccfg_ModeConfReg). + // + // 2. + // Adjusted battery monitor low limit in internal regulator mode. + // This is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode. + if ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) { + ccfg_ModeConfReg |= ( CCFG_MODE_CONF_DCDC_RECHARGE_M | CCFG_MODE_CONF_DCDC_ACTIVE_M ); + } else { + HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0; + } + + // set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE + // Note: Inverse polarity + HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_EN_BITN ) = + ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_RECHARGE_S ) & 1 ) ^ 1 ); + + // set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE + // Note: Inverse polarity + HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN ) = + ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_ACTIVE_S ) & 1 ) ^ 1 ); +} + +void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ) { + uint32_t ui32Trim; + + // Following sequence is required for using XOSCHF, if not included + // devices crashes when trying to switch to XOSCHF. + // + // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1 + // register + ui32Trim = SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg ); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim); + + // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and + // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register. + ui32Trim = SetupGetTrimForRcOscLfRtuneCtuneTrim(); + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL, + (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M | + DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M), + DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S, + ui32Trim); + + // Trim XOSCHF IBIAS THERM. Get and set trim value for the + // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other + // register bit fields are set to 0. + ui32Trim = SetupGetTrimForXoscHfIbiastherm(); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2, + ui32Trim< writing to bits[7:4] + ui32Trim = SetupGetTrimForAdcShModeEn( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = + ( 0x20 | ( ui32Trim << 1 )); + + // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance to FCFG1 setting + // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register + // Using MASK4 write + 1 => writing to bits[7:4] + ui32Trim = SetupGetTrimForAdcShVbufEn( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = + ( 0x10 | ( ui32Trim )); + + // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields + // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting. + // Remaining register bit fields are set to their reset values of 0. + ui32Trim = SetupGetTrimForXoscHfCtl(ui32Fcfg1Revision); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim); + + // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting + // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL) + // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4)) + // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and + // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000) + ui32Trim = SetupGetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) = + ( 0x60 | ( ui32Trim << 1 )); + + // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from + // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM + // This is DDI_0_OSC_O_ATESTCTL bit[7] + // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020)) + // Using MASK4 write + 1 => writing to bits[7:4] + ui32Trim = SetupGetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) = + ( 0x80 | ( ui32Trim << 3 )); + + // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and + // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write + // This can be simplified since the registers are packed together in the same + // order both in FCFG1 and in the HW register. + // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18] + // Using MASK8 write + 4 => writing to bits[23:16] + ui32Trim = SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision ); + HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) = + ( 0xFC00 | ( ui32Trim << 2 )); + + // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit + // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting. + // Remaining register bit fields are set to their reset values of 0. + ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim); + +} + +void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) { + uint32_t fcfg1OscConf; + uint32_t ui32Trim; +#if ( ! defined( SKIP_SCLK_LF_SRC_CHANGE )) + uint32_t currentHfClock; + uint32_t ccfgExtLfClk; +#endif + + // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC + switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) { + case 2 : + // XOSC source is a 48 MHz crystal + // Do nothing (since this is the reset setting) + break; + case 1 : + // XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, otherwise skip trimming and default to 24 MHz XOSC) + + fcfg1OscConf = HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ); + + if (( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION ) == 0 ) { + // This is a HPOSC chip, apply HPOSC settings + // Set bit DDI_0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_HPOSC_MODE_EN; + + // ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit) + // ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits) + // ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET = FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits) + // ADI_2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN (1 bit) + // ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits) + // ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP = FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits) + // ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS = FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit) + + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) & + ~( ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M | ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M ) ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S ) << ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M ) >> FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S ) << ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S ) ); + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) & ~( ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M ) ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S ) << ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S ) ); + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) & + ~( ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M | ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M | ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M | ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M )) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_FILTER_EN_M ) >> FCFG1_OSC_CONF_HPOSC_FILTER_EN_S ) << ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S ) << ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M ) >> FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S ) << ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M ) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S ) << ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S ) ); + break; + } + // Not a HPOSC chip - fall through to default + default : + // XOSC source is a 24 MHz crystal (default) + // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M; + break; + } + + // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO + // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used. + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) { + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS; + } + + // Clear DDI_0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 in DDI_0_OSC_O_CTL0. + // This is typically already 0 except on Lizard where it is set in ROM-boot + HWREG( AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN; + + // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1 + ui32Trim = SetupGetTrimForXoscHfFastStart(); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim ); + +#if ( defined( SKIP_SCLK_LF_SRC_CHANGE )) + // If SKIP_SCLK_LF_SRC_CHANGE is defined we will skip the switch-statement below, and + // remain on RCOSCHFDLF as LF source (since RCOSCHFDLF is the reset setting). + // (RCOSCHFDLF = Low frequency clock derived from RCOSC_HF). + // Note1: Function SetupAfterColdResetWakeupFromShutDownCfg3() is a ROM function in some devices (R2 and Agama) + // It must be removed from rom.h on these devices in order to avoid that the ROM version is called. + // Note2: It's not possible to enter STANDBY when running the LF clock from RCOSCHFDLF, however IDLE will work just fine. + // RCOSCHFDLF (RCOSC_HF/1536) -> SCLK_LF (=31250 Hz) + SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency +#else + // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION + switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) { + case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz) + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF ); + SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency + break; + case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT) + // Set SCLK_LF to use the same source as SCLK_HF + // Can be simplified a bit since possible return values for HF matches LF settings + currentHfClock = OSCClockSourceGet( OSC_SRC_CLK_HF ); + OSCClockSourceSet( OSC_SRC_CLK_LF, currentHfClock ); + while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != currentHfClock ) { + // Wait until switched + } + ccfgExtLfClk = HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ); + SetupSetAonRtcSubSecInc(( ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) >> CCFG_EXT_LF_CLK_RTC_INCREMENT_S ); + IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S, + IOC_PORT_AON_CLK32K, + IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis + // Set XOSC_LF in bypass mode to allow external 32 kHz clock + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS; + // Fall through to set XOSC_LF as SCLK_LF source + case 2 : // XOSC_LF -> SLCK_LF (32768 Hz) + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF ); + break; + default : // (=3) RCOSC_LF + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF ); + break; + } +#endif // ( ! defined( SKIP_SCLK_LF_SRC_CHANGE )) + + // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1 + HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) = + ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >> + FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) << + ADI_4_AUX_ADCREF1_VTRIM_S ) & + ADI_4_AUX_ADCREF1_VTRIM_M ); + + // Sync with AON + SysCtrlAonSync(); +} + +uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ) { + uint32_t ui32Fcfg1Value ; + uint32_t ui32XoscHfRow ; + uint32_t ui32XoscHfCol ; + uint32_t ui32TrimValue ; + + // Use device specific trim values located in factory configuration + // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in + // the ANABYPASS_VALUE1 register. Value for the other bit fields + // are set to 0. + + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP); + ui32XoscHfRow = (( ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S ); + ui32XoscHfCol = (( ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S ); + + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) { + // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation + // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg + // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by + // a define and sign extension must therefore be hard coded. + // ( A small test program is created verifying the code lines below: + // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c) + int32_t i32CustomerDeltaAdjust = + (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ))) + >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W )); + + while ( i32CustomerDeltaAdjust < 0 ) { + ui32XoscHfCol >>= 1; // COL 1 step down + if ( ui32XoscHfCol == 0 ) { // if COL below minimum + ui32XoscHfCol = 0xFFFF; // Set COL to maximum + ui32XoscHfRow >>= 1; // ROW 1 step down + if ( ui32XoscHfRow == 0 ) { // if ROW below minimum + ui32XoscHfRow = 1; // Set both ROW and COL + ui32XoscHfCol = 1; // to minimum + } + } + i32CustomerDeltaAdjust++; + } + while ( i32CustomerDeltaAdjust > 0 ) { + ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up + if ( ui32XoscHfCol > 0xFFFF ) { // if COL above maximum + ui32XoscHfCol = 1; // Set COL to minimum + ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up + if ( ui32XoscHfRow > 0xF ) { // if ROW above maximum + ui32XoscHfRow = 0xF; // Set both ROW and COL + ui32XoscHfCol = 0xFFFF; // to maximum + } + } + i32CustomerDeltaAdjust--; + } + } + + ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) | + ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) ); + + return (ui32TrimValue); +} + +uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ) { + uint32_t ui32TrimValue; + + // Use device specific trim values located in factory configuration + // area + ui32TrimValue = + ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<< + DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S; + + ui32TrimValue |= + ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<< + DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S; + + return(ui32TrimValue); +} + +uint32_t SetupGetTrimForXoscHfIbiastherm( void ) { + uint32_t ui32TrimValue; + + // Use device specific trim value located in factory configuration + // area + ui32TrimValue = + (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) & + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>> + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S; + + return(ui32TrimValue); +} + +uint32_t SetupGetTrimForAmpcompTh2( void ) { + uint32_t ui32TrimValue; + uint32_t ui32Fcfg1Value; + + // Use device specific trim value located in factory configuration + // area. All defined register bit fields have corresponding trim + // value in the factory configuration area + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2); + ui32TrimValue = ((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>> + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<< + DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S; + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>> + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<< + DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<< + DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<< + DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S); + + return(ui32TrimValue); +} + +uint32_t SetupGetTrimForAmpcompTh1( void ) { + uint32_t ui32TrimValue; + uint32_t ui32Fcfg1Value; + + // Use device specific trim values located in factory configuration + // area. All defined register bit fields have a corresponding trim + // value in the factory configuration area + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1); + ui32TrimValue = (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>> + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<< + DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S); + + return(ui32TrimValue); +} + +uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ) { + uint32_t ui32TrimValue ; + uint32_t ui32Fcfg1Value ; + uint32_t ibiasOffset ; + uint32_t ibiasInit ; + uint32_t modeConf1 ; + int32_t deltaAdjust ; + + // Use device specific trim values located in factory configuration + // area. Register bit fields without trim values in the factory + // configuration area will be set to the value of 0. + ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 ); + + ibiasOffset = ( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ; + ibiasInit = ( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ; + + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) { + // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG + modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ); + + // Both fields are signed 4-bit values. This is an assumption when doing the sign extension. + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W )); + deltaAdjust += (int32_t)ibiasOffset; + if ( deltaAdjust < 0 ) { + deltaAdjust = 0; + } + if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) { + deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ); + } + ibiasOffset = (uint32_t)deltaAdjust; + + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W )); + deltaAdjust += (int32_t)ibiasInit; + if ( deltaAdjust < 0 ) { + deltaAdjust = 0; + } + if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) { + deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ); + } + ibiasInit = (uint32_t)deltaAdjust; + } + ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) | + ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ; + + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>> + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<< + DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>> + FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<< + DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>> + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<< + DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S); + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + ui32TrimValue |= ((( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >> + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) << + DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S ); + } + + return(ui32TrimValue); +} + +uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ) { + uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) & + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >> + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S; + } + + return ( dblrLoopFilterResetVoltageValue ); +} + +uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ) { + uint32_t getTrimForAdcShModeEnValue = 1; // Recommended default setting + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >> + FCFG1_OSC_CONF_ADC_SH_MODE_EN_S; + } + + return ( getTrimForAdcShModeEnValue ); +} + +uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ) { + uint32_t getTrimForAdcShVbufEnValue = 1; // Recommended default setting + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >> + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S; + } + + return ( getTrimForAdcShVbufEnValue ); +} + +uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ) { + uint32_t getTrimForXoschfCtlValue = 0; // Recommended default setting + uint32_t fcfg1Data; + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); + getTrimForXoschfCtlValue = + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S); + + getTrimForXoschfCtlValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S); + + getTrimForXoschfCtlValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S); + } + + return ( getTrimForXoschfCtlValue ); +} + +uint32_t SetupGetTrimForXoscHfFastStart( void ) { + uint32_t ui32XoscHfFastStartValue ; + + // Get value from FCFG1 + ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >> + FCFG1_OSC_CONF_XOSC_HF_FAST_START_S; + + return ( ui32XoscHfFastStartValue ); +} + +uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ) { + uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommended default setting + uint32_t fcfg1Data; + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); + getTrimForRadcExtCfgValue = + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >> + FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) << + DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S); + + getTrimForRadcExtCfgValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >> + FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) << + DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S); + + getTrimForRadcExtCfgValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >> + FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) << + DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S); + } + + return ( getTrimForRadcExtCfgValue ); +} + +uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ) { + uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >> + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ; + } + + return ( trimForRcOscLfIBiasTrimValue ); +} + +uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ) { + uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M | + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >> + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ; + } + + return ( trimForXoscLfRegulatorAndCmirrwrRatioValue ); +} + +void SetupSetCacheModeAccordingToCcfgSetting( void ) { + // - Make sure to enable aggressive VIMS clock gating for power optimization + // Only for PG2 devices. + // - Enable cache prefetch enable as default setting + // (Slightly higher power consumption, but higher CPU performance) + // - IF ( CCFG_..._DIS_GPRAM == 1 ) + // then: Enable cache (set cache mode = 1), even if set by ROM boot code + // (This is done because it's not set by boot code when running inside + // a debugger supporting the Halt In Boot (HIB) functionality). + // else: Set MODE_GPRAM if not already set (see inline comments as well) + uint32_t vimsCtlMode0 ; + + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for an eventual ongoing mode change to complete. + // (There should typically be no wait time here, but need to be sure) + } + + // Note that Mode=0 is equal to MODE_GPRAM + vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M ); + +#if ( defined( DO_NOT_ENABLE_CACHE_IN_TRIM_DEVICE )) + #if ( defined( CODE_IN_FLASH )) + // Enable cache (and hence disable GPRAM) + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE ); + #else + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + #endif +#else + + if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) { + // Enable cache (and hence disable GPRAM) + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE ); + } else if (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_GPRAM ) { + // GPRAM is enabled in CCFG but not selected + // Note: It is recommended to go via MODE_OFF when switching to MODE_GPRAM + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_OFF ); + while (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_OFF ) { + // Do nothing - wait for an eventual mode change to complete (This goes fast). + } + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + } else { + // Correct mode, but make sure PREF_EN and DYN_CG_EN always are set + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + } +#endif +} + +void SetupSetAonRtcSubSecInc( uint32_t subSecInc ) { + // Loading a new RTCSUBSECINC value is done in 5 steps: + // 1. Write bit[15:0] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC0 + // 2. Write bit[23:16] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC1 + // 3. Set AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ + // 4. Wait for AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK + // 5. Clear AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC0 ) = (( subSecInc ) & AUX_SYSIF_RTCSUBSECINC0_INC15_0_M ); + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_SYSIF_RTCSUBSECINC1_INC23_16_M ); + + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ; + while( ! ( HWREGBITW( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL, AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN ))); + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = 0; +} + +void I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer) { + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Update the next input/output pointer with the correct address. + if(bInput == true) + { + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = (uint32_t)pNextPointer; + } + else + { + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = (uint32_t)pNextPointer; + } +} + +uint32_t I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel) { + uint32_t ui32FrameClkCnt; + uint32_t ui32SysClkCnt; + uint32_t ui32PeriodSysClkCnt; + uint32_t ui32SampleStamp; + + // Get the number of Frame clock counts since last stamp. + ui32FrameClkCnt = HWREG(I2S0_BASE + I2S_O_STMPWCNTCAPT0); + + // Get the number of system clock ticks since last frame clock edge. + ui32SysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXCNTCAPT0); + + // Get the number system clock ticks in the last frame clock period. + ui32PeriodSysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXPER); + + // Calculate the sample stamp. + ui32SampleStamp = (ui32SysClkCnt << 16) / ui32PeriodSysClkCnt; + ui32SampleStamp = (ui32SampleStamp > I2S_STMP_SATURATION) ? + I2S_STMP_SATURATION : ui32SampleStamp; + ui32SampleStamp |= (ui32FrameClkCnt << 16); + + return (ui32SampleStamp); +} + +void PowerCtrlSourceSet(uint32_t ui32PowerConfig) { + // Check the arguments. + ASSERT((ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) || + (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) || + (ui32PowerConfig == PWRCTRL_PWRSRC_ULDO)); + + // Configure the power. + if(ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) { + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) |= + (AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE); + } + else if (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) + { + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &= + ~(AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE); + } + else + { + PRCMMcuUldoConfigure(true); + } +} + +void AESSetInitializationVector(const uint32_t *initializationVector) { + // Write initialization vector to the aes registers + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = initializationVector[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = initializationVector[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = initializationVector[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = initializationVector[3]; +} + +void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) { + if (channel0Length && channel0Addr) { + // We actually want to perform an operation. Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; // This might need AES_IRQEN_DMA_IN_DONE as well + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; + } + + if (channel1Length && channel1Addr) { + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; + } +} + +uint32_t AESWaitForIRQFlags(uint32_t irqFlags) { + uint32_t irqTrigger = 0; + // Wait for the DMA operation to complete. Add a delay to make sure we are + // not flooding the bus with requests too much. + do { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | + CRYPTO_IRQSTAT_RESULT_AVAIL_M | + CRYPTO_IRQSTAT_DMA_BUS_ERR_M | + CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M))); + + // Save the IRQ trigger source + irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags; + + // Clear IRQ flags + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqTrigger; + + return irqTrigger; +} + +uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea) { + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + ASSERT((aesKeyLength == AES_128_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_192_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_256_KEY_LENGTH_BYTES)); + + uint32_t keySize = 0; + + switch (aesKeyLength) { + case AES_128_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_128_BIT; + break; + case AES_192_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_192_BIT; + break; + case AES_256_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_256_BIT; + break; + } + + // Clear any previously written key at the keyLocation + AESInvalidateKey(keyStoreArea); + + // Disable the external interrupt to stop the interrupt form propagating + // from the module to the System CPU. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE_M | CRYPTO_IRQEN_RESULT_AVAIL_M; + + // Configure master control module. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_KEY_STORE; + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQCLR_RESULT_AVAIL); + + // Configure the size of keys contained within the key store + // Do not write to the register if the correct key size is already set. + // Writing to this register causes all current keys to be invalidated. + uint32_t keyStoreKeySize = HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE); + if (keySize != keyStoreKeySize) { + HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = keySize; + } + + // Enable key to write (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = 1 << keyStoreArea; + + // Total key length in bytes (16 for 1 x 128-bit key and 32 for 1 x 256-bit key). + AESStartDMAOperation(aesKey, aesKeyLength, 0, 0); + + // Wait for the DMA operation to complete. + uint32_t irqTrigger = AESWaitForIRQFlags(CRYPTO_IRQCLR_RESULT_AVAIL | CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQSTAT_DMA_BUS_ERR | CRYPTO_IRQSTAT_KEY_ST_WR_ERR); + + // Re-enable interrupts globally. + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // If we had a bus error or the key is not in the CRYPTO_O_KEYWRITTENAREA, return an error. + if ((irqTrigger & (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M)) || !(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + // There was an error in writing to the keyStore. + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +uint32_t AESReadFromKeyStore(uint32_t keyStoreArea) { + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + // Check if there is a valid key in the specified keyStoreArea + if (!(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + return AES_KEYSTORE_AREA_INVALID; + } + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = keyStoreArea; + + // Wait until key is loaded to the AES module. + // We cannot simply poll the IRQ status as only an error is communicated through + // the IRQ status and not the completion of the transfer. + do { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY_M)); + + // Check for keyStore read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M)) { + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength) { + // The intermediate array is used instead of a caller-provided one + // to enable a simple API with no unintuitive alignment or size requirements. + // This is a trade-off of stack-depth vs ease-of-use that came out on the + // ease-of-use side. + uint32_t computedTag[AES_BLOCK_SIZE / sizeof(uint32_t)]; + + // Wait until the computed tag is ready. + while (!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M)); + + // Read computed tag out from the HW registers + // Need to read out all 128 bits in four reads to correctly clear CRYPTO_AESCTL_SAVED_CONTEXT_RDY flag + computedTag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); + computedTag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); + computedTag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); + computedTag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); + + memcpy(tag, computedTag, tagLength); + + return AES_SUCCESS; +} + +uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength) { + uint32_t resultStatus; + // The intermediate array is allocated on the stack to ensure users do not + // point the tag they provide and the one computed at the same location. + // That would cause memcmp to compare an array against itself. We could add + // a check that verifies that the arrays are not the same. If we did that and + // modified AESReadTag to just copy all 128 bits into a provided array, + // we could save 16 bytes of stack space while making the API much more + // complicated. + uint8_t computedTag[AES_BLOCK_SIZE]; + + resultStatus = AESReadTag(computedTag, tagLength); + + if (resultStatus != AES_SUCCESS) { + return resultStatus; + } + + resultStatus = memcmp(computedTag, tag, tagLength); + + if (resultStatus != 0) { + return AES_TAG_VERIFICATION_FAILED; + } + + return AES_SUCCESS; +} + +void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt) { + uint32_t ctrlVal = 0; + + ctrlVal = ((15 - nonceLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if ( macLength >= 2 ) { + ctrlVal |= ((( macLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); + } + ctrlVal |= CRYPTO_AESCTL_CCM | + CRYPTO_AESCTL_CTR | + CRYPTO_AESCTL_SAVE_CONTEXT | + CRYPTO_AESCTL_CTR_WIDTH_128_BIT; + ctrlVal |= encrypt ? CRYPTO_AESCTL_DIR : 0; + + AESSetCtrl(ctrlVal); +} + +void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength) { + union { + uint32_t word[4]; + uint8_t byte[16]; + } initializationVector = {{0}}; + + initializationVector.byte[0] = 15 - nonceLength - 1; + + memcpy(&(initializationVector.byte[1]), nonce, nonceLength); + + AESSetInitializationVector(initializationVector.word); +} + + +#define MAX(x,y) (((x) > (y)) ? (x) : (y)) +#define MIN(x,y) (((x) < (y)) ? (x) : (y)) +#define INRANGE(x,y,z) ((x) > (y) && (x) < (z)) + + +//***************************************************************************** +// +// Define for the maximum curve size supported by the PKA module in 32 bit +// word. +// \note PKA hardware module can support up to 384 bit curve size due to the +// 2K of PKA RAM. +// +//***************************************************************************** +#define PKA_MAX_CURVE_SIZE_32_BIT_WORD 12 + +//***************************************************************************** +// +// Define for the maximum length of the big number supported by the PKA module +// in 32 bit word. +// +//***************************************************************************** +#define PKA_MAX_LEN_IN_32_BIT_WORD PKA_MAX_CURVE_SIZE_32_BIT_WORD + +//***************************************************************************** +// +// Used in PKAWritePkaParam() and PKAWritePkaParamExtraOffset() to specify that +// the base address of the parameter should not be written to a NPTR register. +// +//***************************************************************************** +#define PKA_NO_POINTER_REG 0xFF + +//***************************************************************************** +// +// NIST P224 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP224_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint224 NISTP224_generator = { + .x = {.byte = {0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34, + 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A, + 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B, + 0xBD, 0x0C, 0x0E, 0xB7, }}, + .y = {.byte = {0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44, + 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD, + 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5, + 0x88, 0x63, 0x37, 0xBD, }}, +}; + +const PKA_EccParam224 NISTP224_prime = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +const PKA_EccParam224 NISTP224_a = {.byte = {0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +const PKA_EccParam224 NISTP224_b = {.byte = {0xB4, 0xFF, 0x55, 0x23, 0x43, 0x39, 0x0B, 0x27, + 0xBA, 0xD8, 0xBF, 0xD7, 0xB7, 0xB0, 0x44, 0x50, + 0x56, 0x32, 0x41, 0xF5, 0xAB, 0xB3, 0x04, 0x0C, + 0x85, 0x0A, 0x05, 0xB4}}; + +const PKA_EccParam224 NISTP224_order = {.byte = {0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13, + 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +//***************************************************************************** +// +// NIST P256 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP256_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 NISTP256_generator = { + .x = {.byte = {0x96, 0xc2, 0x98, 0xd8, 0x45, 0x39, 0xa1, 0xf4, + 0xa0, 0x33, 0xeb, 0x2d, 0x81, 0x7d, 0x03, 0x77, + 0xf2, 0x40, 0xa4, 0x63, 0xe5, 0xe6, 0xbc, 0xf8, + 0x47, 0x42, 0x2c, 0xe1, 0xf2, 0xd1, 0x17, 0x6b}}, + .y = {.byte = {0xf5, 0x51, 0xbf, 0x37, 0x68, 0x40, 0xb6, 0xcb, + 0xce, 0x5e, 0x31, 0x6b, 0x57, 0x33, 0xce, 0x2b, + 0x16, 0x9e, 0x0f, 0x7c, 0x4a, 0xeb, 0xe7, 0x8e, + 0x9b, 0x7f, 0x1a, 0xfe, 0xe2, 0x42, 0xe3, 0x4f}}, +}; + +const PKA_EccParam256 NISTP256_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam256 NISTP256_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam256 NISTP256_b = {.byte = {0x4b, 0x60, 0xd2, 0x27, 0x3e, 0x3c, 0xce, 0x3b, + 0xf6, 0xb0, 0x53, 0xcc, 0xb0, 0x06, 0x1d, 0x65, + 0xbc, 0x86, 0x98, 0x76, 0x55, 0xbd, 0xeb, 0xb3, + 0xe7, 0x93, 0x3a, 0xaa, 0xd8, 0x35, 0xc6, 0x5a}}; + +const PKA_EccParam256 NISTP256_order = {.byte = {0x51, 0x25, 0x63, 0xfc, 0xc2, 0xca, 0xb9, 0xf3, + 0x84, 0x9e, 0x17, 0xa7, 0xad, 0xfa, 0xe6, 0xbc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +//***************************************************************************** +// +// NIST P384 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP384_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint384 NISTP384_generator = { + .x = {.byte = {0xb7, 0x0a, 0x76, 0x72, 0x38, 0x5e, 0x54, 0x3a, + 0x6c, 0x29, 0x55, 0xbf, 0x5d, 0xf2, 0x02, 0x55, + 0x38, 0x2a, 0x54, 0x82, 0xe0, 0x41, 0xf7, 0x59, + 0x98, 0x9b, 0xa7, 0x8b, 0x62, 0x3b, 0x1d, 0x6e, + 0x74, 0xad, 0x20, 0xf3, 0x1e, 0xc7, 0xb1, 0x8e, + 0x37, 0x05, 0x8b, 0xbe, 0x22, 0xca, 0x87, 0xaa}}, + .y = {.byte = {0x5f, 0x0e, 0xea, 0x90, 0x7c, 0x1d, 0x43, 0x7a, + 0x9d, 0x81, 0x7e, 0x1d, 0xce, 0xb1, 0x60, 0x0a, + 0xc0, 0xb8, 0xf0, 0xb5, 0x13, 0x31, 0xda, 0xe9, + 0x7c, 0x14, 0x9a, 0x28, 0xbd, 0x1d, 0xf4, 0xf8, + 0x29, 0xdc, 0x92, 0x92, 0xbf, 0x98, 0x9e, 0x5d, + 0x6f, 0x2c, 0x26, 0x96, 0x4a, 0xde, 0x17, 0x36,}}, +}; + +const PKA_EccParam384 NISTP384_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam384 NISTP384_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam384 NISTP384_b = {.byte = {0xef, 0x2a, 0xec, 0xd3, 0xed, 0xc8, 0x85, 0x2a, + 0x9d, 0xd1, 0x2e, 0x8a, 0x8d, 0x39, 0x56, 0xc6, + 0x5a, 0x87, 0x13, 0x50, 0x8f, 0x08, 0x14, 0x03, + 0x12, 0x41, 0x81, 0xfe, 0x6e, 0x9c, 0x1d, 0x18, + 0x19, 0x2d, 0xf8, 0xe3, 0x6b, 0x05, 0x8e, 0x98, + 0xe4, 0xe7, 0x3e, 0xe2, 0xa7, 0x2f, 0x31, 0xb3}}; + +const PKA_EccParam384 NISTP384_order = {.byte = {0x73, 0x29, 0xc5, 0xcc, 0x6a, 0x19, 0xec, 0xec, + 0x7a, 0xa7, 0xb0, 0x48, 0xb2, 0x0d, 0x1a, 0x58, + 0xdf, 0x2d, 0x37, 0xf4, 0x81, 0x4d, 0x63, 0xc7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + + +//***************************************************************************** +// +// NIST P521 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP521_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint521 NISTP521_generator = { + .x = {.byte = {0x66, 0xbd, 0xe5, 0xc2, 0x31, 0x7e, 0x7e, 0xf9, + 0x9b, 0x42, 0x6a, 0x85, 0xc1, 0xb3, 0x48, 0x33, + 0xde, 0xa8, 0xff, 0xa2, 0x27, 0xc1, 0x1d, 0xfe, + 0x28, 0x59, 0xe7, 0xef, 0x77, 0x5e, 0x4b, 0xa1, + 0xba, 0x3d, 0x4d, 0x6b, 0x60, 0xaf, 0x28, 0xf8, + 0x21, 0xb5, 0x3f, 0x05, 0x39, 0x81, 0x64, 0x9c, + 0x42, 0xb4, 0x95, 0x23, 0x66, 0xcb, 0x3e, 0x9e, + 0xcd, 0xe9, 0x04, 0x04, 0xb7, 0x06, 0x8e, 0x85, + 0xc6, 0x00}}, + .y = {.byte = {0x50, 0x66, 0xd1, 0x9f, 0x76, 0x94, 0xbe, 0x88, + 0x40, 0xc2, 0x72, 0xa2, 0x86, 0x70, 0x3c, 0x35, + 0x61, 0x07, 0xad, 0x3f, 0x01, 0xb9, 0x50, 0xc5, + 0x40, 0x26, 0xf4, 0x5e, 0x99, 0x72, 0xee, 0x97, + 0x2c, 0x66, 0x3e, 0x27, 0x17, 0xbd, 0xaf, 0x17, + 0x68, 0x44, 0x9b, 0x57, 0x49, 0x44, 0xf5, 0x98, + 0xd9, 0x1b, 0x7d, 0x2c, 0xb4, 0x5f, 0x8a, 0x5c, + 0x04, 0xc0, 0x3b, 0x9a, 0x78, 0x6a, 0x29, 0x39, + 0x18, 0x01}}, +}; + +const PKA_EccParam521 NISTP521_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + +const PKA_EccParam521 NISTP521_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + +const PKA_EccParam521 NISTP521_b = {.byte = {0x00, 0x3f, 0x50, 0x6b, 0xd4, 0x1f, 0x45, 0xef, + 0xf1, 0x34, 0x2c, 0x3d, 0x88, 0xdf, 0x73, 0x35, + 0x07, 0xbf, 0xb1, 0x3b, 0xbd, 0xc0, 0x52, 0x16, + 0x7b, 0x93, 0x7e, 0xec, 0x51, 0x39, 0x19, 0x56, + 0xe1, 0x09, 0xf1, 0x8e, 0x91, 0x89, 0xb4, 0xb8, + 0xf3, 0x15, 0xb3, 0x99, 0x5b, 0x72, 0xda, 0xa2, + 0xee, 0x40, 0x85, 0xb6, 0xa0, 0x21, 0x9a, 0x92, + 0x1f, 0x9a, 0x1c, 0x8e, 0x61, 0xb9, 0x3e, 0x95, + 0x51, 0x00}}; + +const PKA_EccParam521 NISTP521_order = {.byte = {0x09, 0x64, 0x38, 0x91, 0x1e, 0xb7, 0x6f, 0xbb, + 0xae, 0x47, 0x9c, 0x89, 0xb8, 0xc9, 0xb5, 0x3b, + 0xd0, 0xa5, 0x09, 0xf7, 0x48, 0x01, 0xcc, 0x7f, + 0x6b, 0x96, 0x2f, 0xbf, 0x83, 0x87, 0x86, 0x51, + 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + + +//***************************************************************************** +// +// Brainpool P256r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP256R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 BrainpoolP256R1_generator = { + .x = {.byte = {0x62, 0x32, 0xCE, 0x9A, 0xBD, 0x53, 0x44, 0x3A, + 0xC2, 0x23, 0xBD, 0xE3, 0xE1, 0x27, 0xDE, 0xB9, + 0xAF, 0xB7, 0x81, 0xFC, 0x2F, 0x48, 0x4B, 0x2C, + 0xCB, 0x57, 0x7E, 0xCB, 0xB9, 0xAE, 0xD2, 0x8B}}, + .y = {.byte = {0x97, 0x69, 0x04, 0x2F, 0xC7, 0x54, 0x1D, 0x5C, + 0x54, 0x8E, 0xED, 0x2D, 0x13, 0x45, 0x77, 0xC2, + 0xC9, 0x1D, 0x61, 0x14, 0x1A, 0x46, 0xF8, 0x97, + 0xFD, 0xC4, 0xDA, 0xC3, 0x35, 0xF8, 0x7E, 0x54}}, +}; + +const PKA_EccParam256 BrainpoolP256R1_prime = {.byte = {0x77, 0x53, 0x6E, 0x1F, 0x1D, 0x48, 0x13, 0x20, + 0x28, 0x20, 0x26, 0xD5, 0x23, 0xF6, 0x3B, 0x6E, + 0x72, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E, + 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}}; + +const PKA_EccParam256 BrainpoolP256R1_a = {.byte = {0xD9, 0xB5, 0x30, 0xF3, 0x44, 0x4B, 0x4A, 0xE9, + 0x6C, 0x5C, 0xDC, 0x26, 0xC1, 0x55, 0x80, 0xFB, + 0xE7, 0xFF, 0x7A, 0x41, 0x30, 0x75, 0xF6, 0xEE, + 0x57, 0x30, 0x2C, 0xFC, 0x75, 0x09, 0x5A, 0x7D}}; + +const PKA_EccParam256 BrainpoolP256R1_b = {.byte = {0xB6, 0x07, 0x8C, 0xFF, 0x18, 0xDC, 0xCC, 0x6B, + 0xCE, 0xE1, 0xF7, 0x5C, 0x29, 0x16, 0x84, 0x95, + 0xBF, 0x7C, 0xD7, 0xBB, 0xD9, 0xB5, 0x30, 0xF3, + 0x44, 0x4B, 0x4A, 0xE9, 0x6C, 0x5C, 0xDC, 0x26,}}; + +const PKA_EccParam256 BrainpoolP256R1_order = {.byte = {0xA7, 0x56, 0x48, 0x97, 0x82, 0x0E, 0x1E, 0x90, + 0xF7, 0xA6, 0x61, 0xB5, 0xA3, 0x7A, 0x39, 0x8C, + 0x71, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E, + 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}}; + +//***************************************************************************** +// +// Brainpool P384r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP384R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint384 BrainpoolP384R1_generator = { + .x = {.byte = {0x1E, 0xAF, 0xD4, 0x47, 0xE2, 0xB2, 0x87, 0xEF, + 0xAA, 0x46, 0xD6, 0x36, 0x34, 0xE0, 0x26, 0xE8, + 0xE8, 0x10, 0xBD, 0x0C, 0xFE, 0xCA, 0x7F, 0xDB, + 0xE3, 0x4F, 0xF1, 0x7E, 0xE7, 0xA3, 0x47, 0x88, + 0x6B, 0x3F, 0xC1, 0xB7, 0x81, 0x3A, 0xA6, 0xA2, + 0xFF, 0x45, 0xCF, 0x68, 0xF0, 0x64, 0x1C, 0x1D}}, + .y = {.byte = {0x15, 0x53, 0x3C, 0x26, 0x41, 0x03, 0x82, 0x42, + 0x11, 0x81, 0x91, 0x77, 0x21, 0x46, 0x46, 0x0E, + 0x28, 0x29, 0x91, 0xF9, 0x4F, 0x05, 0x9C, 0xE1, + 0x64, 0x58, 0xEC, 0xFE, 0x29, 0x0B, 0xB7, 0x62, + 0x52, 0xD5, 0xCF, 0x95, 0x8E, 0xEB, 0xB1, 0x5C, + 0xA4, 0xC2, 0xF9, 0x20, 0x75, 0x1D, 0xBE, 0x8A}}, +}; + +const PKA_EccParam384 BrainpoolP384R1_prime = {.byte = {0x53, 0xEC, 0x07, 0x31, 0x13, 0x00, 0x47, 0x87, + 0x71, 0x1A, 0x1D, 0x90, 0x29, 0xA7, 0xD3, 0xAC, + 0x23, 0x11, 0xB7, 0x7F, 0x19, 0xDA, 0xB1, 0x12, + 0xB4, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15, + 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F, + 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}}; + +const PKA_EccParam384 BrainpoolP384R1_a = {.byte = {0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04, + 0xEB, 0xD4, 0x3A, 0x50, 0x4A, 0x81, 0xA5, 0x8A, + 0x0F, 0xF9, 0x91, 0xBA, 0xEF, 0x65, 0x91, 0x13, + 0x87, 0x27, 0xB2, 0x4F, 0x8E, 0xA2, 0xBE, 0xC2, + 0xA0, 0xAF, 0x05, 0xCE, 0x0A, 0x08, 0x72, 0x3C, + 0x0C, 0x15, 0x8C, 0x3D, 0xC6, 0x82, 0xC3, 0x7B}}; + +const PKA_EccParam384 BrainpoolP384R1_b = {.byte = {0x11, 0x4C, 0x50, 0xFA, 0x96, 0x86, 0xB7, 0x3A, + 0x94, 0xC9, 0xDB, 0x95, 0x02, 0x39, 0xB4, 0x7C, + 0xD5, 0x62, 0xEB, 0x3E, 0xA5, 0x0E, 0x88, 0x2E, + 0xA6, 0xD2, 0xDC, 0x07, 0xE1, 0x7D, 0xB7, 0x2F, + 0x7C, 0x44, 0xF0, 0x16, 0x54, 0xB5, 0x39, 0x8B, + 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04}}; + +const PKA_EccParam384 BrainpoolP384R1_order = {.byte = {0x65, 0x65, 0x04, 0xE9, 0x02, 0x32, 0x88, 0x3B, + 0x10, 0xC3, 0x7F, 0x6B, 0xAF, 0xB6, 0x3A, 0xCF, + 0xA7, 0x25, 0x04, 0xAC, 0x6C, 0x6E, 0x16, 0x1F, + 0xB3, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15, + 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F, + 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}}; + +//***************************************************************************** +// +// Brainpool P512r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP512R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint512 BrainpoolP512R1_generator = { + .x = {.byte = {0x22, 0xF8, 0xB9, 0xBC, 0x09, 0x22, 0x35, 0x8B, + 0x68, 0x5E, 0x6A, 0x40, 0x47, 0x50, 0x6D, 0x7C, + 0x5F, 0x7D, 0xB9, 0x93, 0x7B, 0x68, 0xD1, 0x50, + 0x8D, 0xD4, 0xD0, 0xE2, 0x78, 0x1F, 0x3B, 0xFF, + 0x8E, 0x09, 0xD0, 0xF4, 0xEE, 0x62, 0x3B, 0xB4, + 0xC1, 0x16, 0xD9, 0xB5, 0x70, 0x9F, 0xED, 0x85, + 0x93, 0x6A, 0x4C, 0x9C, 0x2E, 0x32, 0x21, 0x5A, + 0x64, 0xD9, 0x2E, 0xD8, 0xBD, 0xE4, 0xAE, 0x81}}, + .y = {.byte = {0x92, 0x08, 0xD8, 0x3A, 0x0F, 0x1E, 0xCD, 0x78, + 0x06, 0x54, 0xF0, 0xA8, 0x2F, 0x2B, 0xCA, 0xD1, + 0xAE, 0x63, 0x27, 0x8A, 0xD8, 0x4B, 0xCA, 0x5B, + 0x5E, 0x48, 0x5F, 0x4A, 0x49, 0xDE, 0xDC, 0xB2, + 0x11, 0x81, 0x1F, 0x88, 0x5B, 0xC5, 0x00, 0xA0, + 0x1A, 0x7B, 0xA5, 0x24, 0x00, 0xF7, 0x09, 0xF2, + 0xFD, 0x22, 0x78, 0xCF, 0xA9, 0xBF, 0xEA, 0xC0, + 0xEC, 0x32, 0x63, 0x56, 0x5D, 0x38, 0xDE, 0x7D}}, +}; + +const PKA_EccParam512 BrainpoolP512R1_prime = {.byte = {0xF3, 0x48, 0x3A, 0x58, 0x56, 0x60, 0xAA, 0x28, + 0x85, 0xC6, 0x82, 0x2D, 0x2F, 0xFF, 0x81, 0x28, + 0xE6, 0x80, 0xA3, 0xE6, 0x2A, 0xA1, 0xCD, 0xAE, + 0x42, 0x68, 0xC6, 0x9B, 0x00, 0x9B, 0x4D, 0x7D, + 0x71, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6, + 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB, + 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F, + 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}}; + +const PKA_EccParam512 BrainpoolP512R1_a = {.byte = {0xCA, 0x94, 0xFC, 0x77, 0x4D, 0xAC, 0xC1, 0xE7, + 0xB9, 0xC7, 0xF2, 0x2B, 0xA7, 0x17, 0x11, 0x7F, + 0xB5, 0xC8, 0x9A, 0x8B, 0xC9, 0xF1, 0x2E, 0x0A, + 0xA1, 0x3A, 0x25, 0xA8, 0x5A, 0x5D, 0xED, 0x2D, + 0xBC, 0x63, 0x98, 0xEA, 0xCA, 0x41, 0x34, 0xA8, + 0x10, 0x16, 0xF9, 0x3D, 0x8D, 0xDD, 0xCB, 0x94, + 0xC5, 0x4C, 0x23, 0xAC, 0x45, 0x71, 0x32, 0xE2, + 0x89, 0x3B, 0x60, 0x8B, 0x31, 0xA3, 0x30, 0x78}}; + +const PKA_EccParam512 BrainpoolP512R1_b = {.byte = {0x23, 0xF7, 0x16, 0x80, 0x63, 0xBD, 0x09, 0x28, + 0xDD, 0xE5, 0xBA, 0x5E, 0xB7, 0x50, 0x40, 0x98, + 0x67, 0x3E, 0x08, 0xDC, 0xCA, 0x94, 0xFC, 0x77, + 0x4D, 0xAC, 0xC1, 0xE7, 0xB9, 0xC7, 0xF2, 0x2B, + 0xA7, 0x17, 0x11, 0x7F, 0xB5, 0xC8, 0x9A, 0x8B, + 0xC9, 0xF1, 0x2E, 0x0A, 0xA1, 0x3A, 0x25, 0xA8, + 0x5A, 0x5D, 0xED, 0x2D, 0xBC, 0x63, 0x98, 0xEA, + 0xCA, 0x41, 0x34, 0xA8, 0x10, 0x16, 0xF9, 0x3D}}; + +const PKA_EccParam512 BrainpoolP512R1_order = {.byte = {0x69, 0x00, 0xA9, 0x9C, 0x82, 0x96, 0x87, 0xB5, + 0xDD, 0xDA, 0x5D, 0x08, 0x81, 0xD3, 0xB1, 0x1D, + 0x47, 0x10, 0xAC, 0x7F, 0x19, 0x61, 0x86, 0x41, + 0x19, 0x26, 0xA9, 0x4C, 0x41, 0x5C, 0x3E, 0x55, + 0x70, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6, + 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB, + 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F, + 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}}; + +//***************************************************************************** +// +// Curve25519 constants in little endian format. byte[0] is the least +// significant byte and byte[Curve25519_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 Curve25519_generator = { + .x = {.byte = {0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}, + .y = {.byte = {0xd9, 0xd3, 0xce, 0x7e, 0xa2, 0xc5, 0xe9, 0x29, + 0xb2, 0x61, 0x7c, 0x6d, 0x7e, 0x4d, 0x3d, 0x92, + 0x4c, 0xd1, 0x48, 0x77, 0x2c, 0xdd, 0x1e, 0xe0, + 0xb4, 0x86, 0xa0, 0xb8, 0xa1, 0x19, 0xae, 0x20}}, +}; + +const PKA_EccParam256 Curve25519_prime = {.byte = {0xed, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; + +const PKA_EccParam256 Curve25519_a = {.byte = {0x06, 0x6d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + +const PKA_EccParam256 Curve25519_b = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + +const PKA_EccParam256 Curve25519_order = {.byte = {0xb9, 0xdc, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58, + 0xd6, 0x9c, 0xf7, 0xa2, 0xde, 0xf9, 0xde, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + +//***************************************************************************** +// +// Write a PKA parameter to the PKA module, set required registers, and add an offset. +// +//***************************************************************************** +static uint32_t PKAWritePkaParam(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset) +{ + uint32_t i; + uint32_t *paramWordAlias = (uint32_t *)param; + // Take the floor of paramLength in 32-bit words + uint32_t paramLengthInWords = paramLength / sizeof(uint32_t); + + // Only copy data if it is specified. We may wish to simply allocate another buffer and get + // the required offset. + if (param) { + // Load the number in PKA RAM + for (i = 0; i < paramLengthInWords; i++) { + HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = paramWordAlias[i]; + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. The extra zeros at the end should not matter, as the large + // number is little-endian and thus has no effect. + // We could have correctly calculated ceiling(paramLength / sizeof(uint32_t)) above. + // However, we would not have been able to zero-out the extra few most significant + // bytes of the most significant word. That would have resulted in doing maths operations + // on whatever follows param in RAM. + if (paramLength % sizeof(uint32_t)) { + uint32_t temp = 0; + uint8_t j; + + // Load the entire word line of the param remainder + temp = paramWordAlias[i]; + + // Zero-out all bytes beyond the end of the param + for (j = paramLength % sizeof(uint32_t); j < sizeof(uint32_t); j++) { + ((uint8_t *)&temp)[j] = 0; + } + + HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = temp; + + // Increment paramLengthInWords since we take the ceiling of length / sizeof(uint32_t) + paramLengthInWords++; + } + } + + // Update the A, B, C, or D pointer with the offset address of the PKA RAM location + // where the number will be stored. + switch (ptrRegOffset) { + case PKA_O_APTR: + HWREG(PKA_BASE + PKA_O_APTR) = paramOffset >> 2; + HWREG(PKA_BASE + PKA_O_ALENGTH) = paramLengthInWords; + break; + case PKA_O_BPTR: + HWREG(PKA_BASE + PKA_O_BPTR) = paramOffset >> 2; + HWREG(PKA_BASE + PKA_O_BLENGTH) = paramLengthInWords; + break; + case PKA_O_CPTR: + HWREG(PKA_BASE + PKA_O_CPTR) = paramOffset >> 2; + break; + case PKA_O_DPTR: + HWREG(PKA_BASE + PKA_O_DPTR) = paramOffset >> 2; + break; + } + + // Ensure 8-byte alignment of next parameter. + // Returns the offset for the next parameter. + return paramOffset + sizeof(uint32_t) * (paramLengthInWords + (paramLengthInWords % 2)); +} + +//***************************************************************************** +// +// Write a PKA parameter to the PKA module but return a larger offset. +// +//***************************************************************************** +static uint32_t PKAWritePkaParamExtraOffset(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset) +{ + // Ensure 16-byte alignment. + return (sizeof(uint32_t) * 2) + PKAWritePkaParam(param, paramLength, paramOffset, ptrRegOffset); +} + +//***************************************************************************** +// +// Writes the result of a large number arithmetic operation to a provided buffer. +// +//***************************************************************************** +static uint32_t PKAGetBigNumResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + uint32_t mswOffset; + uint32_t lswOffset; + uint32_t lengthInWords; + uint32_t i; + uint32_t *resultWordAlias = (uint32_t *)resultBuf; + + // Check the arguments. + ASSERT(resultBuf); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Get the MSW register value. + mswOffset = HWREG(PKA_BASE + PKA_O_MSW); + + // If the result vector is zero, write back one zero byte so the caller does not need + // to handle a special error for the perhaps valid result of zero. + // They will only get the error status if they do not provide a buffer + if (mswOffset & PKA_MSW_RESULT_IS_ZERO_M) { + if (*resultLength){ + if(resultBuf){ + resultBuf[0] = 0; + } + + *resultLength = 1; + + return PKA_STATUS_SUCCESS; + } + else { + return PKA_STATUS_BUF_UNDERFLOW; + } + } + + // Get the length of the result + mswOffset = ((mswOffset & PKA_MSW_MSW_ADDRESS_M) + 1); + lswOffset = ((resultPKAMemAddr - PKA_RAM_BASE) >> 2); + + if (mswOffset >= lswOffset) { + lengthInWords = mswOffset - lswOffset; + } + else { + return PKA_STATUS_RESULT_ADDRESS_INCORRECT; + } + + // Check if the provided buffer length is adequate to store the result data. + if (*resultLength < lengthInWords * sizeof(uint32_t)) { + return PKA_STATUS_BUF_UNDERFLOW; + } + + // Copy the resultant length. + *resultLength = lengthInWords * sizeof(uint32_t); + + + if (resultBuf) { + // Copy the result into the resultBuf. + for (i = 0; i < lengthInWords; i++) { + resultWordAlias[i]= HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + } + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Retrieve the result of a modulo operation or the remainder of a division. +// +//***************************************************************************** +static uint32_t PKAGetBigNumResultRemainder(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + uint32_t regMSWVal; + uint32_t lengthInWords; + uint32_t i; + uint32_t *resultWordAlias = (uint32_t *)resultBuf; + + // Check the arguments. + ASSERT(resultBuf); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Get the MSW register value. + regMSWVal = HWREG(PKA_BASE + PKA_O_DIVMSW); + + // If the result vector is zero, write back one zero byte so the caller does not need + // to handle a special error for the perhaps valid result of zero. + // They will only get the error status if they do not provide a buffer + if (regMSWVal & PKA_DIVMSW_RESULT_IS_ZERO_M) { + if (*resultLength){ + if(resultBuf){ + resultBuf[0] = 0; + } + + *resultLength = 1; + + return PKA_STATUS_SUCCESS; + } + else { + return PKA_STATUS_BUF_UNDERFLOW; + } + } + + // Get the length of the result + lengthInWords = ((regMSWVal & PKA_DIVMSW_MSW_ADDRESS_M) + 1) - ((resultPKAMemAddr - PKA_RAM_BASE) >> 2); + + // Check if the provided buffer length is adequate to store the result data. + if (*resultLength < lengthInWords * sizeof(uint32_t)) { + return PKA_STATUS_BUF_UNDERFLOW; + } + + // Copy the resultant length. + *resultLength = lengthInWords * sizeof(uint32_t); + + if (resultBuf) { + // Copy the result into the resultBuf. + for (i = 0; i < lengthInWords; i++) { + resultWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + } + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Writes the resultant curve point of an ECC operation to the provided buffer. +// +//***************************************************************************** +static uint32_t PKAGetECCResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + uint32_t i = 0; + uint32_t *xWordAlias = (uint32_t *)curvePointX; + uint32_t *yWordAlias = (uint32_t *)curvePointY; + uint32_t lengthInWordsCeiling = 0; + + // Check for the arguments. + ASSERT(curvePointX); + ASSERT(curvePointY); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is completed. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + if (HWREG(PKA_BASE + PKA_O_SHIFT)) { + return PKA_STATUS_FAILURE; + } + + // Check to make sure that the result vector is not the point at infinity. + if (HWREG(PKA_BASE + PKA_O_MSW) & PKA_MSW_RESULT_IS_ZERO) { + return PKA_STATUS_POINT_AT_INFINITY; + } + + if (curvePointX != NULL) { + // Copy the x co-ordinate value of the result from vector D into + // the curvePoint. + for (i = 0; i < (length / sizeof(uint32_t)); i++) { + xWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. + if (length % sizeof(uint32_t)) { + uint32_t temp = 0; + uint8_t j; + + // Load the entire word line of the coordinate remainder + temp = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + + // Write all remaining bytes to the coordinate + for (j = 0; j < length % sizeof(uint32_t); j++) { + curvePointX[i * sizeof(uint32_t) + j] = ((uint8_t *)&temp)[j]; + } + + } + } + + lengthInWordsCeiling = (length % sizeof(uint32_t)) ? length / sizeof(uint32_t) + 1 : length / sizeof(uint32_t); + + resultPKAMemAddr += sizeof(uint32_t) * (2 + lengthInWordsCeiling + (lengthInWordsCeiling % 2)); + + if (curvePointY != NULL) { + // Copy the y co-ordinate value of the result from vector D into + // the curvePoint. + for (i = 0; i < (length / sizeof(uint32_t)); i++) { + yWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. + if (length % sizeof(uint32_t)) { + uint32_t temp = 0; + uint8_t j; + + // Load the entire word line of the coordinate remainder + temp = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + + // Write all remaining bytes to the coordinate + for (j = 0; j < length % sizeof(uint32_t); j++) { + curvePointY[i * sizeof(uint32_t) + j] = ((uint8_t *)&temp)[j]; + } + } + } + + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Provides the PKA operation status. +// +//***************************************************************************** +uint32_t PKAGetOpsStatus(void) +{ + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN_M) { + return PKA_STATUS_OPERATION_BUSY; + } + else { + return PKA_STATUS_OPERATION_RDY; + } +} + +//***************************************************************************** +// +// Check if an array consists only of zeros. +// +//***************************************************************************** +bool PKAArrayAllZeros(const uint8_t *array, uint32_t arrayLength) +{ + uint32_t i; + uint8_t arrayBits = 0; + + // We could speed things up by comparing word-wise rather than byte-wise. + // However, this extra overhead is inconsequential compared to running an + // actual PKA operation. Especially ECC operations. + for (i = 0; i < arrayLength; i++) { + arrayBits |= array[i]; + } + + if (arrayBits) { + return false; + } + else { + return true; + } + +} + +//***************************************************************************** +// +// Fill an array with zeros +// +//***************************************************************************** +void PKAZeroOutArray(const uint8_t *array, uint32_t arrayLength) +{ + uint32_t i; + // Take the floor of paramLength in 32-bit words + uint32_t arrayLengthInWords = arrayLength / sizeof(uint32_t); + + // Zero-out the array word-wise until i >= arrayLength + for (i = 0; i < arrayLengthInWords * sizeof(uint32_t); i += 4) { + HWREG(array + i) = 0; + } + + // If i != arrayLength, there are some remaining bytes to zero-out + if (arrayLength % sizeof(uint32_t)) { + // Subtract 4 from i, since i has already overshot the array + for (i -= 4; i < arrayLength; i++) { + HWREGB(array + i * sizeof(uint32_t)); + } + } +} + +//***************************************************************************** +// +// Start the big number modulus operation. +// +//***************************************************************************** +uint32_t PKABigNumModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum); + ASSERT(modulus); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(modulus, modulusLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Start the PKCP modulo operation by setting the PKA Function register. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MODULO); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the big number modulus operation. +// +//***************************************************************************** +uint32_t PKABigNumModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr) +{ + // Zero-out array in case modulo result is shorter than length + PKAZeroOutArray(resultBuf, length); + + return PKAGetBigNumResultRemainder(resultBuf, &length, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideStart(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(dividend); + ASSERT(divisor); + ASSERT(resultQuotientMemAddr); + ASSERT(resultRemainderMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(dividend, dividendLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(divisor, divisorLength, offset, PKA_O_BPTR); + + // Copy the remainder result vector address location. + if (resultRemainderMemAddr) { + *resultRemainderMemAddr = PKA_RAM_BASE + offset; + } + + // The remainder cannot ever be larger than the divisor. It should fit inside + // a buffer of that size. + offset = PKAWritePkaParamExtraOffset(0, divisorLength, offset, PKA_O_CPTR); + + // Copy the remainder result vector address location. + if (resultQuotientMemAddr) { + *resultQuotientMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the quotient location in PKA RAM + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Start the PKCP modulo operation by setting the PKA Function register. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_DIVIDE); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the quotient of the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideGetQuotient(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr) +{ + return PKAGetBigNumResult(resultBuf, length, resultQuotientMemAddr); +} + +//***************************************************************************** +// +// Get the remainder of the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideGetRemainder(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr) +{ + return PKAGetBigNumResultRemainder(resultBuf, length, resultQuotientMemAddr); +} + + +//***************************************************************************** +// +// Start the comparison of two big numbers. +// +//***************************************************************************** +uint32_t PKABigNumCmpStart(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum1); + ASSERT(bigNum2); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum1, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(bigNum2, length, offset, PKA_O_BPTR); + + // Set the PKA Function register for the Compare operation + // and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_COMPARE); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the comparison operation of two big numbers. +// +//***************************************************************************** +uint32_t PKABigNumCmpGetResult(void) +{ + uint32_t status; + + // verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Check the COMPARE register. + switch(HWREG(PKA_BASE + PKA_O_COMPARE)) { + case PKA_COMPARE_A_EQUALS_B: + status = PKA_STATUS_EQUAL; + break; + + case PKA_COMPARE_A_GREATER_THAN_B: + status = PKA_STATUS_A_GREATER_THAN_B; + break; + + case PKA_COMPARE_A_LESS_THAN_B: + status = PKA_STATUS_A_LESS_THAN_B; + break; + + default: + status = PKA_STATUS_FAILURE; + break; + } + + return status; +} + +//***************************************************************************** +// +// Start the big number inverse modulo operation. +// +//***************************************************************************** +uint32_t PKABigNumInvModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum); + ASSERT(modulus); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(modulus, modulusLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // set the PKA function to InvMod operation and the start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = 0x0000F000; + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the big number inverse modulo operation. +// +//***************************************************************************** +uint32_t PKABigNumInvModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr) +{ + // Zero-out array in case modulo result is shorter than length + PKAZeroOutArray(resultBuf, length); + + return PKAGetBigNumResult(resultBuf, &length, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the big number multiplication. +// +//***************************************************************************** +uint32_t PKABigNumMultiplyStart(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(multiplicand); + ASSERT(multiplier); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(multiplicand, multiplicandLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(multiplier, multiplierLength, offset, PKA_O_BPTR); + + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the PKA function to the multiplication and start it. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MULTIPLY); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the results of the big number multiplication. +// +//***************************************************************************** +uint32_t PKABigNumMultGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the addition of two big number. +// +//***************************************************************************** +uint32_t PKABigNumAddStart(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for arguments. + ASSERT(bigNum1); + ASSERT(bigNum2); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum1, bigNum1Length, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(bigNum2, bigNum2Length, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the function for the add operation and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_ADD); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the addition operation on two big number. +// +//***************************************************************************** +uint32_t PKABigNumSubGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the addition of two big number. +// +//***************************************************************************** +uint32_t PKABigNumSubStart(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for arguments. + ASSERT(minuend); + ASSERT(subtrahend); + ASSERT(resultPKAMemAddr); + + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(minuend, minuendLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(subtrahend, subtrahendLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the function for the add operation and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_SUBTRACT); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the addition operation on two big number. +// +//***************************************************************************** +uint32_t PKABigNumAddGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + + +//***************************************************************************** +// +// Start ECC Multiplication. +// +//***************************************************************************** +uint32_t PKAEccMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(scalar); + ASSERT(curvePointX); + ASSERT(curvePointY); + ASSERT(prime); + ASSERT(a); + ASSERT(b); + ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t)); + ASSERT(resultPKAMemAddr); + + // Make sure no PKA operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + offset = PKAWritePkaParamExtraOffset(b, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR); + offset = PKAWritePkaParamExtraOffset(curvePointY, length, offset, PKA_NO_POINTER_REG); + + // Update the result location. + // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity + if (resultPKAMemAddr) { + *resultPKAMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA function to ECC-MULT and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x05 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Start ECC Montgomery Multiplication. +// +//***************************************************************************** +uint32_t PKAEccMontgomeryMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(scalar); + ASSERT(curvePointX); + ASSERT(prime); + ASSERT(a); + ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t)); + ASSERT(resultPKAMemAddr); + + // Make sure no PKA operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR); + + // Update the result location. + // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity + if (resultPKAMemAddr) { + *resultPKAMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA function to Montgomery ECC-MULT and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x02 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Get the result of ECC Multiplication +// +//***************************************************************************** +uint32_t PKAEccMultiplyGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length); +} + +//***************************************************************************** +// +// Start the ECC Addition. +// +//***************************************************************************** +uint32_t PKAEccAddStart(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(curvePoint1X); + ASSERT(curvePoint1Y); + ASSERT(curvePoint2X); + ASSERT(curvePoint2Y); + ASSERT(prime); + ASSERT(a); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParamExtraOffset(curvePoint1X, length, offset, PKA_O_APTR); + offset = PKAWritePkaParamExtraOffset(curvePoint1Y, length, offset, PKA_NO_POINTER_REG); + + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePoint2X, length, offset, PKA_O_CPTR); + offset = PKAWritePkaParamExtraOffset(curvePoint2Y, length, offset, PKA_NO_POINTER_REG); + + // Copy the result vector location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA Function to ECC-ADD and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION ) = PKA_FUNCTION_RUN_M | (0x03 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the ECC Addition +// +//***************************************************************************** +uint32_t PKAEccAddGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length); +} + +//***************************************************************************** +// +// Verify a public key against the supplied elliptic curve equation +// +//***************************************************************************** +uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length) +{ + uint32_t pkaResult; + uint32_t resultAddress; + uint32_t resultLength; + uint8_t *scratchBuffer = (uint8_t *)(PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE / 2); + uint8_t *scratchBuffer2 = scratchBuffer + 512; + + + // Verify X in range [0, prime - 1] + PKABigNumCmpStart(curvePointX, + prime, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return PKA_STATUS_X_LARGER_THAN_PRIME; + } + + // Verify Y in range [0, prime - 1] + PKABigNumCmpStart(curvePointY, + prime, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return PKA_STATUS_Y_LARGER_THAN_PRIME; + } + + // Verify point on curve + // Short-Weierstrass equation: Y ^ 2 = X ^3 + a * X + b mod P + // Reduced: Y ^ 2 = X * (X ^ 2 + a) + b + + // tmp = X ^ 2 + PKABigNumMultiplyStart(curvePointX, length, curvePointX, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp += a + PKABigNumAddStart(scratchBuffer, resultLength, a, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp *= x + PKABigNumMultiplyStart(scratchBuffer, resultLength, curvePointX, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp += b + PKABigNumAddStart(scratchBuffer, resultLength, b, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + + // tmp2 = tmp % prime to ensure we have no fraction in the division. + // The number will only shrink from here on out. + PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + // If the result is not a multiple of the word-length, the PKA HW will round up + // because it deals in words only. That means that using 'length' directly + // would cause and underflow, since length refers to the actual length in bytes of + // the curve parameters while the PKA HW reports that rounded up to the next + // word boundary. + // Use 200 as the resultLength instead since we are copying to the scratch buffer + // anyway. + // Practically, this only happens with curves such as NIST-P521 that are not word + // multiples. + resultLength = 200; + pkaResult = PKABigNumModGetResult(scratchBuffer2, resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp = y^2 + PKABigNumMultiplyStart(curvePointY, length, curvePointY, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp %= prime + PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + // If the result is not a multiple of the word-length, the PKA HW will round up + // because it deals in words only. That means that using 'length' directly + // would cause and underflow, since length refers to the actual length in bytes of + // the curve parameters while the PKA HW reports that rounded up to the next + // word boundary. + // Use 200 as the resultLength instead since we are copying to the scratch buffer + // anyway. + // Practically, this only happens with curves such as NIST-P521 that are not word + // multiples. + resultLength = 200; + pkaResult = PKABigNumModGetResult(scratchBuffer, resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp ?= tmp2 + PKABigNumCmpStart(scratchBuffer, + scratchBuffer2, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_EQUAL) { + return PKA_STATUS_POINT_NOT_ON_CURVE; + } + else { + return PKA_STATUS_SUCCESS; + } +} + + +static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash); + + +void SHA2StartDMAOperation(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) { + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + if (channel0Addr) { + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; + } + + if (channel1Addr) { + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; + } +} + +uint32_t SHA2WaitForIRQFlags(uint32_t irqFlags) { + uint32_t irqTrigger = 0; + // Wait for the DMA operation to complete. Add a delay to make sure we are + // not flooding the bus with requests too much. + do { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M))); + + // Save the IRQ trigger source + irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT); + + // Clear IRQ flags + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqFlags; + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + return irqTrigger; +} + +uint32_t SHA2ComputeInitialHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength) { + ASSERT(message); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + + return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, initialMessageLength, initialMessageLength, hashAlgorithm, true, false); +} + +uint32_t SHA2ComputeIntermediateHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength) { + ASSERT(message); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, 0, intermediateMessageLength, hashAlgorithm, false, false); +} + +uint32_t SHA2ComputeFinalHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm) { + ASSERT(message); + ASSERT(totalMsgLength); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + ASSERT(resultDigest); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, resultDigest, intermediateDigest, totalMsgLength, messageLength, hashAlgorithm, false, true); +} + +uint32_t SHA2ComputeHash(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm) { + ASSERT(message); + ASSERT(totalMsgLength); + ASSERT(resultDigest); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, resultDigest, 0, totalMsgLength, totalMsgLength, hashAlgorithm, true, true); +} + +static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash) { + uint8_t digestLength = 0; + uint32_t dmaAlgorithmSelect = 0; + + SHA2ClearDigestAvailableFlag(); + + switch (hashAlgorithm) { + case SHA2_MODE_SELECT_SHA224: + digestLength = SHA2_SHA224_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA256; + break; + case SHA2_MODE_SELECT_SHA256: + digestLength = SHA2_SHA256_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA256; + break; + case SHA2_MODE_SELECT_SHA384: + digestLength = SHA2_SHA384_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA512; + break; + case SHA2_MODE_SELECT_SHA512: + digestLength = SHA2_SHA512_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA512; + break; + default: + return SHA2_INVALID_ALGORITHM; + } + + if (initialHash && finalHash) { + // The empty string is a perfectly valid message. It obviously has a length of 0. The DMA cannot + // handle running with a transfer length of 0. This workaround depends on the hash engine adding the + // trailing 1 bit and 0-padding bits after the DMAtransfer is complete and not in the DMA itself. + // totalMsgLength is purposefully not altered as it is appended to the end of the message during finalization + // and determines how many padding-bytes are added. + // Altering totalMsgLength would alter the final hash digest. + // Because totalMsgLength specifies that the message is of length 0, the content of the byte loaded + // through the DMA is irrelevant. It is overwritten internally in the hash engine. + messageLength = messageLength ? messageLength : 1; + } + + // Setting the incorrect number of bits here leads to the calculation of the correct result + // but a failure to read them out. + // The tag bit is set to read out the digest via DMA rather than through the slave interface. + SHA2SelectAlgorithm(dmaAlgorithmSelect | (resultDigest ? SHA2_ALGSEL_TAG : 0)); + SHA2IntClear(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); + SHA2IntEnable(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); + + HWREG(CRYPTO_BASE + CRYPTO_O_HASHMODE) = hashAlgorithm | (initialHash ? CRYPTO_HASHMODE_NEW_HASH_M : 0); + + // Only load the intermediate digest if requested. + if (intermediateDigest && !initialHash) { + SHA2SetDigest(intermediateDigest, digestLength); + } + + // If this is the final hash, finalization is required. This means appending a 1 bit, padding the message until this section + // is 448 bytes long, and adding the 64 bit total length of the message in bits. Thankfully, this is all done in hardware. + if (finalHash) { + // This specific length must be specified in bits not bytes. + SHA2SetMessageLength(totalMsgLength * 8); + HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) = CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M; + + } + + // The cast is fine in this case. SHA2StartDMAOperation channel one serves as input and no one does + // hash operations in-place. + SHA2StartDMAOperation((uint8_t *)message, messageLength, resultDigest, digestLength); + + return SHA2_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rom/driverlib.elf b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rom/driverlib.elf new file mode 100644 index 0000000..9d09f2a Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rom/driverlib.elf differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rom/readme.txt b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rom/readme.txt new file mode 100644 index 0000000..baec5e2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rom/readme.txt @@ -0,0 +1,32 @@ +Debugging sessions in IAR Embedded Workbench (IAR) and Code Composer Studio (CCS) +can load symbol information covering the code in ROM. +Symbols are loaded by selecting the ELF files found in the same folder as this +readme.txt file. +In addition the source code for the driverlib functions in ROM is found in the +driverlib.c file in this folder. + +Loading ROM code symbols in CCS debug session: +- Start a debug session in your project +- Select Run > Load > Add Symbols to create additional symbols +- Browse to and select each ELF file in this folder in the 'Program file' field +- Set the value of 0 in the 'Code offset' field for each ELF file +- If you enter a driverlib function in ROM during your debuging session and + get this information: + 'Can't find a source file at "..//driverlib.c"' + you can navigate to the driverlib.c file in this folder by selecting + the 'Locate File..' button. + +Loading ROM code symbols for use in IAR debug session: +- In your project select the following before starting debug session: + Project > Options.. > Debugger and then select the 'Images'-tab +- In the 'Images'-tab do the following for each of the ELF files + located in the same folder as this reame.txt file: + -- Select the 'Download extra image' box + -- Browse to the ELF file in the 'Path:' field + -- Set the value of 0 in the 'Offset:' field + -- Select the 'Debug info only' box +- If you during a debug session enters a driverlib function in ROM you will + be notified by this message: + 'Could not find following file: ..//driverlib.c' + Select the browse button and select the driverlib.c file located in this + folder. diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/startup_files/ccfg.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/startup_files/ccfg.c new file mode 100644 index 0000000..09a65b6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/startup_files/ccfg.c @@ -0,0 +1,532 @@ +/****************************************************************************** +* Filename: ccfg.c +* Revised: $Date: 2017-11-02 11:36:28 +0100 (Thu, 02 Nov 2017) $ +* Revision: $Revision: 18030 $ +* +* Description: Customer Configuration for: +* CC13x2, CC13x4, CC26x2, CC26x4 device family (HW rev 2). +* +* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __CCFC_C__ +#define __CCFC_C__ + +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ccfg_simple_struct.h" + +//***************************************************************************** +// +// Introduction +// +// This file contains fields used by Boot ROM, startup code, and SW radio +// stacks to configure chip behavior. +// +// Fields are documented in more details in hw_ccfg.h and CCFG.html in +// DriverLib documentation (doc_overview.html -> CPU Domain Memory Map -> CCFG). +// +// PLEASE NOTE: +// It is not recommended to do modifications inside the ccfg.c file. +// This file is part of the CoreSDK release and future releases may have +// important modifications and new fields added without notice. +// The recommended method to modify the CCFG settings is to have a separate +// .c file that defines the specific CCFG values to be +// overridden and then include the TI provided ccfg.c at the very end, +// giving default values for non-overriden settings. +// +// Example: +// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC +// //---- Use default values for all others ---- +// #include "/source/ti/devices//startup_files/ccfg.c" +// +//***************************************************************************** + +//***************************************************************************** +// +// Internal settings, forcing several bit-fields to be set to a specific value. +// +//***************************************************************************** + +//##################################### +// Force VDDR high setting (Higher output power but also higher power consumption) +// This is also called "boost mode" +//##################################### + +#ifndef CCFG_FORCE_VDDR_HH +#define CCFG_FORCE_VDDR_HH 0x0 // Use default VDDR trim +// #define CCFG_FORCE_VDDR_HH 0x1 // Force VDDR voltage to the factory HH setting (FCFG1..VDDR_TRIM_HH) +#endif + +//***************************************************************************** +// +// Set the values of the individual bit fields. +// +//***************************************************************************** + +//##################################### +// Alternative DC/DC settings +//##################################### + +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0 // Alternative DC/DC setting enabled +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x1 // Alternative DC/DC setting disabled +#endif + +#if ( CCFG_FORCE_VDDR_HH ) +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0xC // Special VMIN level (2.5V) when forced VDDR HH voltage +#else +#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0x8 // 2.25V +#endif +#endif + +#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0 // Dithering disabled +// #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x1 // Dithering enabled +#endif + +#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x0 // Peak current +#endif + +//##################################### +// XOSC override settings +//##################################### + +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x0 // Enable override +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1 // Disable override +#endif + +#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT +#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 0x0 // Delta = 0 +#endif + +#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET +#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0 // Delta = 0 +#endif + +#ifndef SET_CCFG_MODE_CONF_1_XOSC_MAX_START +#define SET_CCFG_MODE_CONF_1_XOSC_MAX_START 0x10 // 1600us +#endif + +//##################################### +// Power settings +//##################################### + +#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA +#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF // Signed delta value +1 to apply to the VDDR_TRIM_SLEEP target (0xF=-1=default=no compensation) +#endif + +#ifndef SET_CCFG_MODE_CONF_DCDC_RECHARGE +#define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x0 // Use the DC/DC during recharge in powerdown +// #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x1 // Do not use the DC/DC during recharge in powerdown +#endif + +#ifndef SET_CCFG_MODE_CONF_DCDC_ACTIVE +#define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x0 // Use the DC/DC during active mode +// #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x1 // Do not use the DC/DC during active mode +#endif + +#if ( CCFG_FORCE_VDDR_HH ) +#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // Special setting to enable forced VDDR HH voltage +#else +#ifndef SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL +// #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x0 // VDDS BOD level is 2.0V +#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // VDDS BOD level is 1.8V (or 1.65V for external regulator mode) +#endif +#endif + +#ifndef SET_CCFG_MODE_CONF_VDDR_CAP +#define SET_CCFG_MODE_CONF_VDDR_CAP 0x3A // Unsigned 8-bit integer representing the min. decoupling capacitance on VDDR in units of 100nF +#endif + +#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC +#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1 // Temperature compensation on VDDR sleep trim disabled (default) +// #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x0 // Temperature compensation on VDDR sleep trim enabled +#endif + +//##################################### +// Clock settings +//##################################### + +#ifndef SET_CCFG_MODE_CONF_SCLK_LF_OPTION +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x0 // LF clock derived from High Frequency XOSC +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x1 // External LF clock +#define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC +#endif + +#ifndef SET_CCFG_MODE_CONF_XOSC_CAP_MOD +// #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x0 // Apply cap-array delta +#define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x1 // Don't apply cap-array delta +#endif + +#ifndef SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA +#define SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF // Signed 8-bit value, directly modifying trimmed XOSC cap-array value +#endif + +#ifndef SET_CCFG_EXT_LF_CLK_DIO +#define SET_CCFG_EXT_LF_CLK_DIO 0x01 // DIO number if using external LF clock +#endif + +#ifndef SET_CCFG_EXT_LF_CLK_RTC_INCREMENT +#define SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 0x800000 // RTC increment representing the external LF clock frequency +#endif + +//##################################### +// Special HF clock source setting +//##################################### +#ifndef SET_CCFG_MODE_CONF_XOSC_FREQ +// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x1 // Use HPOSC as HF source (if executing on a HPOSC chip, otherwise using default (=0x3)) +#define SET_CCFG_MODE_CONF_XOSC_FREQ 0x2 // HF source is a 48 MHz xtal (default on x2/x4 chips) +// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x3 // HF source is a 24 MHz xtal (default on x0 chips) +#endif + +//##################################### +// Bootloader settings +//##################################### + +#ifndef SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE +#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00 // Disable ROM boot loader +// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader +#endif + +#ifndef SET_CCFG_BL_CONFIG_BL_LEVEL +// #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x0 // Active low to open boot loader backdoor +#define SET_CCFG_BL_CONFIG_BL_LEVEL 0x1 // Active high to open boot loader backdoor +#endif + +#ifndef SET_CCFG_BL_CONFIG_BL_PIN_NUMBER +#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0xFF // DIO number for boot loader backdoor +#endif + +#ifndef SET_CCFG_BL_CONFIG_BL_ENABLE +// #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 // Enabled boot loader backdoor +#define SET_CCFG_BL_CONFIG_BL_ENABLE 0xFF // Disabled boot loader backdoor +#endif + +//##################################### +// Debug access settings +//##################################### + +#ifndef SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE +#define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0x00 // Disable unlocking of TI FA option. +// #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0xC5 // Enable unlocking of TI FA option with the unlock code +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE +// #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0x00 // Access disabled +#define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE +//#define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0x00 // Access disabled +#define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00 // Access disabled +//#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +//##################################### +// Alternative IEEE 802.15.4 MAC address +//##################################### +#ifndef SET_CCFG_IEEE_MAC_0 +#define SET_CCFG_IEEE_MAC_0 0xFFFFFFFF // Bits [31:0] +#endif + +#ifndef SET_CCFG_IEEE_MAC_1 +#define SET_CCFG_IEEE_MAC_1 0xFFFFFFFF // Bits [63:32] +#endif + +//##################################### +// Alternative BLE address +//##################################### +#ifndef SET_CCFG_IEEE_BLE_0 +#define SET_CCFG_IEEE_BLE_0 0xFFFFFFFF // Bits [31:0] +#endif + +#ifndef SET_CCFG_IEEE_BLE_1 +#define SET_CCFG_IEEE_BLE_1 0xFFFFFFFF // Bits [63:32] +#endif + +//##################################### +// Flash erase settings +//##################################### + +#ifndef SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N +// #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x0 // Any chip erase request detected during boot will be ignored +#define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x1 // Any chip erase request detected during boot will be performed by the boot FW +#endif + +#ifndef SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N +// #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x0 // Disable the boot loader bank erase function +#define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x1 // Enable the boot loader bank erase function +#endif + +//##################################### +// Flash image valid +//##################################### +#ifndef SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID +#define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 0x00000000 // Flash image vector table is at address 0x00000000 (default) +// #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID // Flash image vector table is at address +// #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID // Flash image vector table address is invalid. ROM boot loader is called. +#endif + +//##################################### +// Flash sector write protection +//##################################### +#ifndef SET_CCFG_CCFG_PROT_31_0 +#define SET_CCFG_CCFG_PROT_31_0 0xFFFFFFFF +#endif + +#ifndef SET_CCFG_CCFG_PROT_63_32 +#define SET_CCFG_CCFG_PROT_63_32 0xFFFFFFFF +#endif + +#ifndef SET_CCFG_CCFG_PROT_95_64 +#define SET_CCFG_CCFG_PROT_95_64 0xFFFFFFFF +#endif + +#ifndef SET_CCFG_CCFG_PROT_127_96 +#define SET_CCFG_CCFG_PROT_127_96 0xFFFFFFFF +#endif + +//##################################### +// Select between cache or GPRAM +//##################################### +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0 // Cache is disabled and GPRAM is available at 0x11000000-0x11001FFF +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1 // Cache is enabled and GPRAM is disabled (unavailable) +#endif + +//##################################### +// Select TCXO +//##################################### +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1 // Disable TCXO +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x0 // Enable TXCO +#endif + +//***************************************************************************** +// +// CCFG values that should not be modified. +// +//***************************************************************************** +#define SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058 +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS (CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M >> CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S) + +#if ( CCFG_FORCE_VDDR_HH ) +#define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x0 // Special setting to enable forced VDDR HH voltage +#else +#define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x1 +#endif + +#define SET_CCFG_MODE_CONF_RTC_COMP 0x1 +#define SET_CCFG_MODE_CONF_HF_COMP 0x1 + +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 0xFF +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 0xFF +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 0xFF +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 0xFF + +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 0xFF +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 0xFF +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 0xFF +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 0xFF + +#define SET_CCFG_RTC_OFFSET_RTC_COMP_P0 0xFFFF +#define SET_CCFG_RTC_OFFSET_RTC_COMP_P1 0xFF +#define SET_CCFG_RTC_OFFSET_RTC_COMP_P2 0xFF + +#define SET_CCFG_FREQ_OFFSET_HF_COMP_P0 0xFFFF +#define SET_CCFG_FREQ_OFFSET_HF_COMP_P1 0xFF +#define SET_CCFG_FREQ_OFFSET_HF_COMP_P2 0xFF + +//***************************************************************************** +// +// Concatenate bit fields to words. +// DO NOT EDIT! +// +//***************************************************************************** +#define DEFAULT_CCFG_EXT_LF_CLK ( \ + ((((uint32_t)( SET_CCFG_EXT_LF_CLK_DIO )) << CCFG_EXT_LF_CLK_DIO_S ) | ~CCFG_EXT_LF_CLK_DIO_M ) & \ + ((((uint32_t)( SET_CCFG_EXT_LF_CLK_RTC_INCREMENT )) << CCFG_EXT_LF_CLK_RTC_INCREMENT_S ) | ~CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) ) + +#define DEFAULT_CCFG_MODE_CONF_1 ( \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN )) << CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN )) << CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK )) << CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT )) << CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET )) << CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_XOSC_MAX_START )) << CCFG_MODE_CONF_1_XOSC_MAX_START_S ) | ~CCFG_MODE_CONF_1_XOSC_MAX_START_M ) ) + +#define DEFAULT_CCFG_SIZE_AND_DIS_FLAGS ( \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG )) << CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS )) << CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) ) + +#define DEFAULT_CCFG_MODE_CONF ( \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_RECHARGE )) << CCFG_MODE_CONF_DCDC_RECHARGE_S ) | ~CCFG_MODE_CONF_DCDC_RECHARGE_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_ACTIVE )) << CCFG_MODE_CONF_DCDC_ACTIVE_S ) | ~CCFG_MODE_CONF_DCDC_ACTIVE_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_EXT_LOAD )) << CCFG_MODE_CONF_VDDR_EXT_LOAD_S ) | ~CCFG_MODE_CONF_VDDR_EXT_LOAD_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL )) << CCFG_MODE_CONF_VDDS_BOD_LEVEL_S ) | ~CCFG_MODE_CONF_VDDS_BOD_LEVEL_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_SCLK_LF_OPTION )) << CCFG_MODE_CONF_SCLK_LF_OPTION_S ) | ~CCFG_MODE_CONF_SCLK_LF_OPTION_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_RTC_COMP )) << CCFG_MODE_CONF_RTC_COMP_S ) | ~CCFG_MODE_CONF_RTC_COMP_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_FREQ )) << CCFG_MODE_CONF_XOSC_FREQ_S ) | ~CCFG_MODE_CONF_XOSC_FREQ_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAP_MOD )) << CCFG_MODE_CONF_XOSC_CAP_MOD_S ) | ~CCFG_MODE_CONF_XOSC_CAP_MOD_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_HF_COMP )) << CCFG_MODE_CONF_HF_COMP_S ) | ~CCFG_MODE_CONF_HF_COMP_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA )) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) | ~CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_CAP )) << CCFG_MODE_CONF_VDDR_CAP_S ) | ~CCFG_MODE_CONF_VDDR_CAP_M ) ) + +#define DEFAULT_CCFG_VOLT_LOAD_0 ( \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M ) ) + +#define DEFAULT_CCFG_VOLT_LOAD_1 ( \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M ) ) + +#define DEFAULT_CCFG_RTC_OFFSET ( \ + ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P0 )) << CCFG_RTC_OFFSET_RTC_COMP_P0_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P0_M ) & \ + ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P1 )) << CCFG_RTC_OFFSET_RTC_COMP_P1_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P1_M ) & \ + ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P2 )) << CCFG_RTC_OFFSET_RTC_COMP_P2_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P2_M ) ) + +#define DEFAULT_CCFG_FREQ_OFFSET ( \ + ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P0 )) << CCFG_FREQ_OFFSET_HF_COMP_P0_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P0_M ) & \ + ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P1 )) << CCFG_FREQ_OFFSET_HF_COMP_P1_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P1_M ) & \ + ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P2 )) << CCFG_FREQ_OFFSET_HF_COMP_P2_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P2_M ) ) + +#define DEFAULT_CCFG_IEEE_MAC_0 SET_CCFG_IEEE_MAC_0 +#define DEFAULT_CCFG_IEEE_MAC_1 SET_CCFG_IEEE_MAC_1 +#define DEFAULT_CCFG_IEEE_BLE_0 SET_CCFG_IEEE_BLE_0 +#define DEFAULT_CCFG_IEEE_BLE_1 SET_CCFG_IEEE_BLE_1 + +#define DEFAULT_CCFG_BL_CONFIG ( \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE )) << CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S ) | ~CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_LEVEL )) << CCFG_BL_CONFIG_BL_LEVEL_S ) | ~CCFG_BL_CONFIG_BL_LEVEL_M ) & \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_PIN_NUMBER )) << CCFG_BL_CONFIG_BL_PIN_NUMBER_S ) | ~CCFG_BL_CONFIG_BL_PIN_NUMBER_M ) & \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_ENABLE )) << CCFG_BL_CONFIG_BL_ENABLE_S ) | ~CCFG_BL_CONFIG_BL_ENABLE_M ) ) + +#define DEFAULT_CCFG_ERASE_CONF ( \ + ((((uint32_t)( SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N )) << CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M ) & \ + ((((uint32_t)( SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N )) << CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M ) ) + +#define DEFAULT_CCFG_CCFG_TI_OPTIONS ( \ + ((((uint32_t)( SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE )) << CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S ) | ~CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M ) ) + +#define DEFAULT_CCFG_CCFG_TAP_DAP_0 ( \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M ) ) + +#define DEFAULT_CCFG_CCFG_TAP_DAP_1 ( \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M ) ) + +#define DEFAULT_CCFG_IMAGE_VALID_CONF SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID + +#define DEFAULT_CCFG_CCFG_PROT_31_0 SET_CCFG_CCFG_PROT_31_0 +#define DEFAULT_CCFG_CCFG_PROT_63_32 SET_CCFG_CCFG_PROT_63_32 +#define DEFAULT_CCFG_CCFG_PROT_95_64 SET_CCFG_CCFG_PROT_95_64 +#define DEFAULT_CCFG_CCFG_PROT_127_96 SET_CCFG_CCFG_PROT_127_96 + +//***************************************************************************** +// +// Customer Configuration Area in Lock Page +// +//***************************************************************************** +#if defined(__IAR_SYSTEMS_ICC__) +__root const ccfg_t __ccfg @ ".ccfg" = +#elif defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(__ccfg, ".ccfg") +#pragma RETAIN(__ccfg) +const ccfg_t __ccfg = +#else +const ccfg_t __ccfg __attribute__((section(".ccfg"))) __attribute__((used)) = +#endif +{ // Mapped to address + DEFAULT_CCFG_EXT_LF_CLK , // 0x50003FA8 (0x50003xxx maps to last + DEFAULT_CCFG_MODE_CONF_1 , // 0x50003FAC sector in FLASH. + DEFAULT_CCFG_SIZE_AND_DIS_FLAGS , // 0x50003FB0 Independent of FLASH size) + DEFAULT_CCFG_MODE_CONF , // 0x50003FB4 + DEFAULT_CCFG_VOLT_LOAD_0 , // 0x50003FB8 + DEFAULT_CCFG_VOLT_LOAD_1 , // 0x50003FBC + DEFAULT_CCFG_RTC_OFFSET , // 0x50003FC0 + DEFAULT_CCFG_FREQ_OFFSET , // 0x50003FC4 + DEFAULT_CCFG_IEEE_MAC_0 , // 0x50003FC8 + DEFAULT_CCFG_IEEE_MAC_1 , // 0x50003FCC + DEFAULT_CCFG_IEEE_BLE_0 , // 0x50003FD0 + DEFAULT_CCFG_IEEE_BLE_1 , // 0x50003FD4 + DEFAULT_CCFG_BL_CONFIG , // 0x50003FD8 + DEFAULT_CCFG_ERASE_CONF , // 0x50003FDC + DEFAULT_CCFG_CCFG_TI_OPTIONS , // 0x50003FE0 + DEFAULT_CCFG_CCFG_TAP_DAP_0 , // 0x50003FE4 + DEFAULT_CCFG_CCFG_TAP_DAP_1 , // 0x50003FE8 + DEFAULT_CCFG_IMAGE_VALID_CONF , // 0x50003FEC + DEFAULT_CCFG_CCFG_PROT_31_0 , // 0x50003FF0 + DEFAULT_CCFG_CCFG_PROT_63_32 , // 0x50003FF4 + DEFAULT_CCFG_CCFG_PROT_95_64 , // 0x50003FF8 + DEFAULT_CCFG_CCFG_PROT_127_96 , // 0x50003FFC +}; + +#endif // __CCFC_C__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi.c new file mode 100644 index 0000000..47ecc7f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi.c @@ -0,0 +1,73 @@ +/****************************************************************************** +* Filename: adi.c +* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) +* Revision: 47706 +* +* Description: Driver for the ADI interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aux_smph.h" +#include "adi.h" +#include "cpu.h" + + +//***************************************************************************** +// +// SafeHapiVoid() and SafeHapiAuxAdiSelect() +// Common wrapper functions for the Hapi functions needing workaround for the +// "bus arbitration" issue. +// +//***************************************************************************** +void SafeHapiVoid( FPTR_VOID_VOID_T fPtr ) +{ + bool bIrqEnabled = ( ! CPUcpsid() ); + while ( ! HWREG( AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 )); + fPtr(); + HWREG( AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 ) = 1; + if ( bIrqEnabled ) { + CPUcpsie(); + } +} + +void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ) +{ + bool bIrqEnabled = ( ! CPUcpsid() ); + while ( ! HWREG( AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 )); + fPtr( ut8Signal ); + HWREG( AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 ) = 1; + if ( bIrqEnabled ) { + CPUcpsie(); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi.h new file mode 100644 index 0000000..a204232 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi.h @@ -0,0 +1,861 @@ +/****************************************************************************** +* Filename: adi.h +* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) +* Revision: 47706 +* +* Description: Defines and prototypes for the ADI master interface. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup analog_group +//! @{ +//! \addtogroup adi_api +//! @{ +// +//***************************************************************************** + +#ifndef __ADI_H__ +#define __ADI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_uart.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_adi.h" +#include "debug.h" +#include "ddi.h" + +//***************************************************************************** +// +// Number of registers in the ADI slave +// +//***************************************************************************** +#define ADI_SLAVE_REGS 16 + + +//***************************************************************************** +// +// Defines that is used to control the ADI slave and master +// +//***************************************************************************** +#define ADI_PROTECT 0x00000080 +#define ADI_ACK 0x00000001 +#define ADI_SYNC 0x00000000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! \brief Checks an ADI base address. +//! +//! This function determines if an ADI port base address is valid. +//! +//! \param ui32Base is the base address of the ADI port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise +// +//***************************************************************************** +static bool +ADIBaseValid(uint32_t ui32Base) +{ + return(ui32Base == ADI2_BASE || ui32Base == ADI3_BASE || + ui32Base == AUX_ADI4_BASE); +} +#endif + + + + + +//***************************************************************************** +// +//! \brief Write an 8 bit value to a register in an ADI slave. +//! +//! This function will write a value to a single register in the analog domain. +//! The access to the registers in the analog domain is either 8, 16, or 32 bit +//! aligned. You can only do 16 bit access on registers 0-1 / 2-3, etc. Similarly +//! 32 bit accesses are always performed on register 0-3 / 4-7, etc. Addresses +//! for the registers and values being written to the registers will be +//! truncated according to this access scheme. +//! +//! \note This operation is write only for the specified register. No +//! previous value of the register will be kept (i.e. this is NOT +//! read-modify-write on the register). +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the register to write. +//! \param ui8Val is the 8 bit value to write to the register. +//! +//! \return None +//! +//! \sa ADI16RegWrite(), ADI32RegWrite() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Write the value to the register. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32Reg, ui8Val, 1); + } else { + HWREGB(ui32Base + ui32Reg) = ui8Val; + } +} + +//***************************************************************************** +// +//! \brief Write a 16 bit value to 2 registers in the ADI slave. +//! +//! This function will write a value to 2 consecutive registers in the analog +//! domain. The access to the registers in the analog domain is either 8, 16 +//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3, +//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7, +//! etc. Addresses for the registers and values being written +//! to the registers will be truncated according to this access scheme. +//! +//! \note The byte addressing bit will be ignored, to ensure 16 bit access +//! to the ADI slave. +//! +//! \note This operation is write only for the specified register. No +//! previous value of the register will be kept (i.e. this is NOT +//! read-modify-write on the register). +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the register to write. +//! \param ui16Val is the 16 bit value to write to the register. +//! +//! \return None +//! +//! \sa ADI8RegWrite(), ADI32RegWrite() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16RegWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint16_t ui16Val) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Write the value to the register. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + (ui32Reg & 0xFE), ui16Val, 2); + } else { + HWREGH(ui32Base + (ui32Reg & 0xFE)) = ui16Val; + } +} + +//***************************************************************************** +// +//! \brief Write a 32 bit value to 4 registers in the ADI slave. +//! +//! This function will write a value to 4 consecutive registers in the analog +//! domain. The access to the registers in the analog domain is either 8, 16 +//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3, +//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7, +//! etc. Addresses for the registers and values being written +//! to the registers will be truncated according to this access scheme. +//! +//! \note The byte and half word addressing bits will be ignored, to ensure +//! 32 bit access to the ADI slave. +//! +//! \note This operation is write only for the specified register. No +//! previous value of the register will be kept (i.e. this is NOT +//! read-modify-write on the register). +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the register to write. +//! \param ui32Val is the 32 bit value to write to the register. +//! +//! \return None +//! +//! \sa ADI8RegWrite(), ADI16RegWrite() +// +//***************************************************************************** +__STATIC_INLINE void +ADI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Write the value to the register. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + (ui32Reg & 0xFC), ui32Val, 4); + } else { + HWREG(ui32Base + (ui32Reg & 0xFC)) = ui32Val; + } +} + +//***************************************************************************** +// +//! \brief Read the value of an 8 bit register in the ADI slave. +//! +//! This function will read an 8 bit register in the analog domain and return +//! the value as the lower 8 bits of an \c uint32_t. The access to the +//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can +//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses +//! are always performed on register 0-3 / 4-7, etc. Addresses for the +//! registers and values being written to the registers will be truncated +//! according to this access scheme. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the 8 bit register to read. +//! +//! \return Returns the 8 bit value of the analog register in the least +//! significant byte of the \c uint32_t. +//! +//! \sa ADI16RegRead(), ADI32RegRead() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ADI8RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Read the register and return the value. + if (ui32Base==AUX_ADI4_BASE) { + return AuxAdiDdiSafeRead(ui32Base + ui32Reg, 1); + } else { + return(HWREGB(ui32Base + ui32Reg)); + } +} + +//***************************************************************************** +// +//! \brief Read the value in a 16 bit register. +//! +//! This function will read 2 x 8 bit registers in the analog domain and return +//! the value as the lower 16 bits of an \c uint32_t. The access to the +//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can +//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses +//! are always performed on register 0-3 / 4-7, etc. Addresses for the +//! registers and values being written to the registers will be truncated +//! according to this access scheme. +//! +//! \note The byte addressing bit will be ignored, to ensure 16 bit access +//! to the ADI slave. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the 16 bit register to read. +//! +//! \return Returns the 16 bit value of the 2 analog register in the 2 least +//! significant bytes of the \c uint32_t. +//! +//! \sa ADI8RegRead(), ADI32RegRead() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ADI16RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Read the registers and return the value. + if (ui32Base==AUX_ADI4_BASE) { + return AuxAdiDdiSafeRead(ui32Base + (ui32Reg & 0xFE), 2); + } else { + return(HWREGH(ui32Base + (ui32Reg & 0xFE))); + } +} + +//***************************************************************************** +// +//! \brief Read the value in a 32 bit register. +//! +//! This function will read 4 x 8 bit registers in the analog domain and return +//! the value as an \c uint32_t. The access to the registers in the analog +//! domain is either 8, 16 or 32 bit aligned. You can only do 16 bit access on +//! registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always performed on +//! register 0-3 / 4-7, etc. Addresses for the registers and values being +//! written to the registers will be truncated according to this access scheme. +//! +//! \note The byte and half word addressing bits will be ignored, to ensure +//! 32 bit access to the ADI slave. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the 32 bit register to read. +//! +//! \return Returns the 32 bit value of the 4 analog registers. +//! +//! \sa ADI8RegRead(), ADI16RegRead() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ADI32RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Read the registers and return the value. + if (ui32Base==AUX_ADI4_BASE) { + return AuxAdiDdiSafeRead(ui32Base + (ui32Reg & 0xFC), 4); + } else { + return(HWREG(ui32Base + (ui32Reg & 0xFC))); + } +} + +//***************************************************************************** +// +//! \brief Set specific bits in a single 8 bit ADI register. +//! +//! This function will set bits in a single register in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in a specific 8 bit register in the +//! ADI slave. Only bits in the selected register are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui8Val is the 8 bit one-hot encoded value specifying which +//! bits to set in the register. +//! +//! \return None +//! +//! \sa ADI16BitsSet(), ADI32BitsSet() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_SET; + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + ui32Reg, ui8Val, 1); + } else { + HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val; + } +} + +//***************************************************************************** +// +//! \brief Set specific bits in 2 x 8 bit ADI slave registers. +//! +//! This function will set bits in 2 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in 2 consecutive 8 bit registers in the +//! ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui16Val is the 16 bit one-hot encoded value specifying which +//! bits to set in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsSet(), ADI32BitsSet() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_SET; + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + (ui32Reg & 0xFE), ui16Val, 2); + } else { + HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val; + } +} + +//***************************************************************************** +// +//! \brief Set specific bits in 4 x 8 bit ADI slave registers. +//! +//! This function will set bits in 4 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in 4 consecutive 8 bit registers in the +//! ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to set in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsSet(), ADI16BitsSet() +// +//***************************************************************************** +__STATIC_INLINE void +ADI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_SET; + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + (ui32Reg & 0xFC), ui32Val, 4); + } else { + HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val; + } +} + +//***************************************************************************** +// +//! \brief Clear specific bits in an 8 bit ADI register. +//! +//! This function will clear bits in a register in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to clear bits in a specific 8 bit register in +//! the ADI slave. Only bits in the selected register are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui8Val is the 8 bit one-hot encoded value specifying which +//! bits to clear in the register. +//! +//! \return None +//! +//! \sa ADI16BitsClear(), ADI32BitsClear() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_CLR; + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + ui32Reg, ui8Val, 1); + } else { + HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val; + } +} + +//***************************************************************************** +// +//! \brief Clear specific bits in two 8 bit ADI register. +//! +//! This function will clear bits in 2 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to clear bits in 2 consecutive 8 bit registers in +//! the ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui16Val is the 16 bit one-hot encoded value specifying which +//! bits to clear in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsClear(), ADI32BitsClear() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_CLR; + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + (ui32Reg & 0xFE), ui16Val, 2); + } else { + HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val; + } +} + +//***************************************************************************** +// +//! \brief Clear specific bits in four 8 bit ADI register. +//! +//! This function will clear bits in 4 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to clear bits in 4 consecutive 8 bit registers in +//! the ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to clear in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsClear(), ADI16BitsClear() +// +//***************************************************************************** +__STATIC_INLINE void +ADI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_CLR; + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + (ui32Reg & 0xFC), ui32Val, 4); + } else { + HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val; + } +} + +//***************************************************************************** +// +//! \brief Set a value on any 4 bits inside an 8 bit register in the ADI slave. +//! +//! This function allows halfbyte (4 bit) access to the ADI slave registers. +//! The parameter \c bWriteHigh determines whether to write to the lower +//! or higher part of the 8 bit register. +//! +//! Use this function to write any value in the range 0-3 bits aligned on a +//! half byte boundary. Fx. for writing the value 0b101 to bits 1 to 3 the +//! \c ui8Val = 0xA and the \c ui8Mask = 0xE. Bit 0 will not be affected by +//! the operation, as the corresponding bit is not set in the \c ui8Mask. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the ADI port. +//! \param ui32Reg is the Least Significant Register in the ADI slave that +//! will be affected by the write operation. +//! \param bWriteHigh defines which part of the register to write in. +//! - \c true: Write upper half byte of register. +//! - \c false: Write lower half byte of register. +//! \param ui8Mask is the mask defining which of the 4 bits that should be +//! overwritten. The mask must be defined in the lower half of the 8 bits of +//! the parameter. +//! \param ui8Val is the value to write. The value must be defined in the lower +//! half of the 8 bits of the parameter. +//! +//! \return None +//! +//! \sa ADI8SetValBit(), ADI16SetValBit +// +//***************************************************************************** +__STATIC_INLINE void +ADI4SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh, + uint8_t ui8Mask, uint8_t ui8Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + ASSERT(!(ui8Val & 0xF0)); + ASSERT(!(ui8Mask & 0xF0)); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_MASK4B + (ui32Reg << 1) + (bWriteHigh ? 1 : 0); + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset, (ui8Mask << 4) | ui8Val, 1); + } else { + HWREGB(ui32Base + ui32RegOffset) = (ui8Mask << 4) | ui8Val; + } +} + +//***************************************************************************** +// +//! \brief Set a value on any bits inside an 8 bit register in the ADI slave. +//! +//! This function allows byte (8 bit) access to the ADI slave registers. +//! +//! Use this function to write any value in the range 0-7 bits aligned on a +//! byte boundary. Fx. for writing the value 0b101 to bits 1 and 3 the +//! \c ui16Val = 0x0A and the \c ui16Mask = 0x0E. Bits 0 and 5-7 will not be affected +//! by the operation, as the corresponding bits are not set in the +//! \c ui16Mask. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the ADI port. +//! \param ui32Reg is the Least Significant Register in the ADI slave that +//! will be affected by the write operation. +//! \param ui16Mask is the mask defining which of the 8 bit that should be +//! overwritten. The mask must be defined in the lower half of the 16 bits. +//! \param ui16Val is the value to write. The value must be defined in the lower +//! half of the 16 bits. +//! +//! \return None +//! +//! \sa ADI4SetValBit(), ADI16SetValBit() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Mask, + uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + ASSERT(!(ui16Val & 0xFF00)); + ASSERT(!(ui16Mask & 0xFF00)); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_MASK8B + (ui32Reg << 1); + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset, (ui16Mask << 8) | ui16Val, 2); + } else { + HWREGH(ui32Base + ui32RegOffset) = (ui16Mask << 8) | ui16Val; + } +} + +//***************************************************************************** +// +//! \brief Set a value on any bits inside an 2 x 8 bit register aligned on a +//! half-word (byte) boundary in the ADI slave. +//! +//! This function allows 2 byte (16 bit) access to the ADI slave registers. +//! +//! Use this function to write any value in the range 0-15 bits aligned on a +//! half-word (byte) boundary. Fx. for writing the value 0b101 to bits 1 and 3 the +//! \c ui32Val = 0x000A and the \c ui32Mask = 0x000E. Bits 0 and 5-15 will not +//! be affected by the operation, as the corresponding bits are not set +//! in the \c ui32Mask. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the ADI port. +//! \param ui32Reg is the Least Significant Register in the ADI slave that +//! will be affected by the write operation. +//! \param ui32Mask is the mask defining which of the 16 bit that should be +//! overwritten. The mask must be defined in the lower half of the 32 bits. +//! \param ui32Val is the value to write. The value must be defined in the lower +//! half of the 32 bits. +//! +//! \return None +//! +//! \sa ADI4SetValBit(), ADI8SetValBit() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, + uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + ASSERT(!(ui32Val & 0xFFFF0000)); + ASSERT(!(ui32Mask & 0xFFFF0000)); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_MASK16B + ((ui32Reg << 1) & 0xFC); + + // Set the selected bits. + if (ui32Base==AUX_ADI4_BASE) { + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset, (ui32Mask << 16) | ui32Val, 4); + } else { + HWREG(ui32Base + ui32RegOffset) = (ui32Mask << 16) | ui32Val; + } +} + +//***************************************************************************** +// +// SafeHapiVoid() and SafeHapiAuxAdiSelect() +// Common wrapper functions for the Hapi functions needing workaround for the +// "bus arbitration" issue. +// +//***************************************************************************** +void SafeHapiVoid( FPTR_VOID_VOID_T fPtr ); +void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ADI_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi_doc.h new file mode 100644 index 0000000..5543464 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi_doc.h @@ -0,0 +1,68 @@ +/****************************************************************************** +* Filename: adi_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup adi_api +//! @{ +//! \section sec_adi Introduction +//! \n +//! +//! \section sec_adi_api API +//! +//! The API functions can be grouped like this: +//! +//! Write: +//! - Direct (all bits): +//! - \ref ADI8RegWrite() +//! - \ref ADI16RegWrite() +//! - \ref ADI32RegWrite() +//! - Set individual bits: +//! - \ref ADI8BitsSet() +//! - \ref ADI16BitsSet() +//! - \ref ADI32BitsSet() +//! - Clear individual bits: +//! - \ref ADI8BitsClear() +//! - \ref ADI16BitsClear() +//! - \ref ADI32BitsClear() +//! - Masked: +//! - \ref ADI4SetValBit() +//! - \ref ADI8SetValBit() +//! - \ref ADI16SetValBit() +//! +//! Read: +//! - \ref ADI8RegRead() +//! - \ref ADI16RegRead() +//! - \ref ADI32RegRead() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aes.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aes.c new file mode 100644 index 0000000..4b2c0b5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aes.c @@ -0,0 +1,372 @@ + +/****************************************************************************** +* Filename: crypto.c +* Revised: 2019-01-25 13:11:50 +0100 (Fri, 25 Jan 2019) +* Revision: 54285 +* +* Description: Driver for the aes functions of the crypto module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aes.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AESStartDMAOperation + #define AESStartDMAOperation NOROM_AESStartDMAOperation + #undef AESSetInitializationVector + #define AESSetInitializationVector NOROM_AESSetInitializationVector + #undef AESWriteCCMInitializationVector + #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector + #undef AESReadTag + #define AESReadTag NOROM_AESReadTag + #undef AESVerifyTag + #define AESVerifyTag NOROM_AESVerifyTag + #undef AESWriteToKeyStore + #define AESWriteToKeyStore NOROM_AESWriteToKeyStore + #undef AESReadFromKeyStore + #define AESReadFromKeyStore NOROM_AESReadFromKeyStore + #undef AESWaitForIRQFlags + #define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags + #undef AESConfigureCCMCtrl + #define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl +#endif + + + +//***************************************************************************** +// +// Load the initialization vector. +// +//***************************************************************************** +void AESSetInitializationVector(const uint32_t *initializationVector) +{ + // Write initialization vector to the aes registers + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = initializationVector[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = initializationVector[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = initializationVector[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = initializationVector[3]; +} + +//***************************************************************************** +// +// Start a crypto DMA operation. +// +//***************************************************************************** +void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) +{ + if (channel0Length && channel0Addr) { + // We actually want to perform an operation. Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; // This might need AES_IRQEN_DMA_IN_DONE as well + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; + } + + if (channel1Length && channel1Addr) { + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; + } +} + +//***************************************************************************** +// +// Poll the IRQ status register and return. +// +//***************************************************************************** +uint32_t AESWaitForIRQFlags(uint32_t irqFlags) +{ + uint32_t irqTrigger = 0; + // Wait for the DMA operation to complete. Add a delay to make sure we are + // not flooding the bus with requests too much. + do { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | + CRYPTO_IRQSTAT_RESULT_AVAIL_M | + CRYPTO_IRQSTAT_DMA_BUS_ERR_M | + CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M))); + + // Save the IRQ trigger source + irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags; + + // Clear IRQ flags + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqTrigger; + + return irqTrigger; +} + +//***************************************************************************** +// +// Transfer a key from CM3 memory to a key store location. +// +//***************************************************************************** +uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea) +{ + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + ASSERT((aesKeyLength == AES_128_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_192_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_256_KEY_LENGTH_BYTES)); + + uint32_t keySize = 0; + + switch (aesKeyLength) { + case AES_128_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_128_BIT; + break; + case AES_192_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_192_BIT; + break; + case AES_256_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_256_BIT; + break; + } + + // Clear any previously written key at the keyLocation + AESInvalidateKey(keyStoreArea); + + // Disable the external interrupt to stop the interrupt form propagating + // from the module to the System CPU. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE_M | CRYPTO_IRQEN_RESULT_AVAIL_M; + + // Configure master control module. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_KEY_STORE; + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQCLR_RESULT_AVAIL); + + // Configure the size of keys contained within the key store + // Do not write to the register if the correct key size is already set. + // Writing to this register causes all current keys to be invalidated. + uint32_t keyStoreKeySize = HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE); + if (keySize != keyStoreKeySize) { + HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = keySize; + } + + // Enable key to write (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = 1 << keyStoreArea; + + // Total key length in bytes (16 for 1 x 128-bit key and 32 for 1 x 256-bit key). + AESStartDMAOperation(aesKey, aesKeyLength, 0, 0); + + // Wait for the DMA operation to complete. + uint32_t irqTrigger = AESWaitForIRQFlags(CRYPTO_IRQCLR_RESULT_AVAIL | CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQSTAT_DMA_BUS_ERR | CRYPTO_IRQSTAT_KEY_ST_WR_ERR); + + // Re-enable interrupts globally. + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // If we had a bus error or the key is not in the CRYPTO_O_KEYWRITTENAREA, return an error. + if ((irqTrigger & (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M)) || !(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + // There was an error in writing to the keyStore. + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +//***************************************************************************** +// +// Transfer a key from the keyStoreArea to the internal buffer of the module. +// +//***************************************************************************** +uint32_t AESReadFromKeyStore(uint32_t keyStoreArea) +{ + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + // Check if there is a valid key in the specified keyStoreArea + if (!(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + return AES_KEYSTORE_AREA_INVALID; + } + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = keyStoreArea; + + // Wait until key is loaded to the AES module. + // We cannot simply poll the IRQ status as only an error is communicated through + // the IRQ status and not the completion of the transfer. + do { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY_M)); + + // Check for keyStore read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M)) { + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +//***************************************************************************** +// +// Read the tag after a completed CCM, GCM, or CBC-MAC operation. +// +//***************************************************************************** +uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength) +{ + // The intermediate array is used instead of a caller-provided one + // to enable a simple API with no unintuitive alignment or size requirements. + // This is a trade-off of stack-depth vs ease-of-use that came out on the + // ease-of-use side. + uint32_t computedTag[AES_BLOCK_SIZE / sizeof(uint32_t)]; + + // Wait until the computed tag is ready. + while (!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M)); + + // Read computed tag out from the HW registers + // Need to read out all 128 bits in four reads to correctly clear CRYPTO_AESCTL_SAVED_CONTEXT_RDY flag + computedTag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); + computedTag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); + computedTag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); + computedTag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); + + memcpy(tag, computedTag, tagLength); + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Verify the provided tag against the computed tag after a completed CCM or +// GCM operation. +// +//***************************************************************************** +uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength) +{ + uint32_t resultStatus; + // The intermediate array is allocated on the stack to ensure users do not + // point the tag they provide and the one computed at the same location. + // That would cause memcmp to compare an array against itself. We could add + // a check that verifies that the arrays are not the same. If we did that and + // modified AESReadTag to just copy all 128 bits into a provided array, + // we could save 16 bytes of stack space while making the API much more + // complicated. + uint8_t computedTag[AES_BLOCK_SIZE]; + + resultStatus = AESReadTag(computedTag, tagLength); + + if (resultStatus != AES_SUCCESS) { + return resultStatus; + } + + resultStatus = memcmp(computedTag, tag, tagLength); + + if (resultStatus != 0) { + return AES_TAG_VERIFICATION_FAILED; + } + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Configure the AES module for CCM mode +// +//***************************************************************************** +void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt) +{ + uint32_t ctrlVal = 0; + + ctrlVal = ((15 - nonceLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if ( macLength >= 2 ) { + ctrlVal |= ((( macLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); + } + ctrlVal |= CRYPTO_AESCTL_CCM | + CRYPTO_AESCTL_CTR | + CRYPTO_AESCTL_SAVE_CONTEXT | + CRYPTO_AESCTL_CTR_WIDTH_128_BIT; + ctrlVal |= encrypt ? CRYPTO_AESCTL_DIR : 0; + + AESSetCtrl(ctrlVal); +} + +//***************************************************************************** +// +// Configure an IV for CCM mode of operation +// +//***************************************************************************** +void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength) +{ + union { + uint32_t word[4]; + uint8_t byte[16]; + } initializationVector = {{0}}; + + initializationVector.byte[0] = 15 - nonceLength - 1; + + memcpy(&(initializationVector.byte[1]), nonce, nonceLength); + + AESSetInitializationVector(initializationVector.word); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aes.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aes.h new file mode 100644 index 0000000..eb199a4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aes.h @@ -0,0 +1,843 @@ +/****************************************************************************** +* Filename: aes.h +* Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019) +* Revision: 54287 +* +* Description: AES header file. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup aes_api +//! @{ +// +//***************************************************************************** + +#ifndef __AES_H__ +#define __AES_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_crypto.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AESStartDMAOperation NOROM_AESStartDMAOperation + #define AESSetInitializationVector NOROM_AESSetInitializationVector + #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector + #define AESReadTag NOROM_AESReadTag + #define AESVerifyTag NOROM_AESVerifyTag + #define AESWriteToKeyStore NOROM_AESWriteToKeyStore + #define AESReadFromKeyStore NOROM_AESReadFromKeyStore + #define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags + #define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl +#endif + + +//***************************************************************************** +// +// Values that can be passed to AESIntEnable, AESIntDisable, and AESIntClear +// as the intFlags parameter, and returned from AESIntStatus. +// Only AES_DMA_IN_DONE and AES_RESULT_RDY are routed to the NVIC. Check each +// function to see if it supports other interrupt status flags. +// +//***************************************************************************** +#define AES_DMA_IN_DONE CRYPTO_IRQEN_DMA_IN_DONE_M +#define AES_RESULT_RDY CRYPTO_IRQEN_RESULT_AVAIL_M +#define AES_DMA_BUS_ERR CRYPTO_IRQCLR_DMA_BUS_ERR_M +#define AES_KEY_ST_WR_ERR CRYPTO_IRQCLR_KEY_ST_WR_ERR_M +#define AES_KEY_ST_RD_ERR CRYPTO_IRQCLR_KEY_ST_RD_ERR_M + + +//***************************************************************************** +// +// General constants +// +//***************************************************************************** + +// AES module return codes +#define AES_SUCCESS 0 +#define AES_KEYSTORE_ERROR 1 +#define AES_KEYSTORE_AREA_INVALID 2 +#define AES_DMA_BUSY 3 +#define AES_DMA_ERROR 4 +#define AES_TAG_NOT_READY 5 +#define AES_TAG_VERIFICATION_FAILED 6 + +// Key store module defines +#define AES_IV_LENGTH_BYTES 16 +#define AES_TAG_LENGTH_BYTES 16 +#define AES_128_KEY_LENGTH_BYTES (128 / 8) +#define AES_192_KEY_LENGTH_BYTES (192 / 8) +#define AES_256_KEY_LENGTH_BYTES (256 / 8) + +#define AES_BLOCK_SIZE 16 + +// DMA status codes +#define AES_DMA_CHANNEL0_ACTIVE CRYPTO_DMASTAT_CH0_ACT_M +#define AES_DMA_CHANNEL1_ACTIVE CRYPTO_DMASTAT_CH1_ACT_M +#define AES_DMA_PORT_ERROR CRYPTO_DMASTAT_PORT_ERR_M + +// Crypto module operation types +#define AES_ALGSEL_AES CRYPTO_ALGSEL_AES_M +#define AES_ALGSEL_KEY_STORE CRYPTO_ALGSEL_KEY_STORE_M +#define AES_ALGSEL_TAG CRYPTO_ALGSEL_TAG_M + + +//***************************************************************************** +// +// For 128-bit keys, all 8 key area locations from 0 to 7 are valid. +// A 256-bit key requires two consecutive Key Area locations. The base key area +// may be odd. Do not attempt to write a 256-bit key to AES_KEY_AREA_7. +// +//***************************************************************************** +#define AES_KEY_AREA_0 0 +#define AES_KEY_AREA_1 1 +#define AES_KEY_AREA_2 2 +#define AES_KEY_AREA_3 3 +#define AES_KEY_AREA_4 4 +#define AES_KEY_AREA_5 5 +#define AES_KEY_AREA_6 6 +#define AES_KEY_AREA_7 7 + +//***************************************************************************** +// +// Defines for the AES-CTR mode counter width +// +//***************************************************************************** +#define AES_CTR_WIDTH_32 0x0 +#define AES_CTR_WIDTH_64 0x1 +#define AES_CTR_WIDTH_96 0x2 +#define AES_CTR_WIDTH_128 0x3 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Start a crypto DMA operation +//! +//! Enable the crypto DMA channels, configure the channel addresses, +//! and set the length of the data transfer. +//! Setting the length of the data transfer automatically starts the +//! transfer. It is also used by the hardware module as a signal to +//! begin the encryption, decryption, or MAC operation. +//! +//! \param [in] channel0Addr A pointer to the address channel 0 shall use. +//! +//! \param [in] channel0Length Length of the data in bytes to be read from or +//! written to at channel0Addr. Set to 0 to not set up +//! this channel. Permitted ranges are mode dependent +//! and displayed below. +//! - ECB: [16] +//! - CBC: [1, sizeof(RAM)] +//! - CBC-MAC: [1, sizeof(RAM)] +//! - CCM: [1, sizeof(RAM)] +//! +//! \param [out] channel1Addr A pointer to the address channel 1 shall use. +//! +//! \param [in] channel1Length Length of the data in bytes to be read from or +//! written to at channel1Addr. Set to 0 to not set up +//! this channel.Permitted ranges are mode dependent +//! and displayed below. +//! - ECB: [16] +//! - CBC: [1, sizeof(RAM)] +//! - CBC-MAC: [1, sizeof(RAM)] +//! - CCM: [1, sizeof(RAM)] +//! +//! \return None +// +//***************************************************************************** +extern void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length); + +//***************************************************************************** +// +//! \brief Write the initialization vector (IV) to the crypto module. +//! +//! Depending on the mode of operation, the tag must be constructed +//! differently: +//! - CBC: No special care must be taken. Any 128-bit IV +//! (initialization vector) will suffice. +//! - CBC-MAC: IV's must be all 0's. +//! - CCM: Only 12 and 13 byte IV's are permitted. See code +//! below for formatting. +//! \code +//! uint8_t initVectorLength = 12; // Could also be 13 +//! +//! union { +//! uint32_t word[4]; +//! uint8_t byte[16]; +//! } initVector; +//! +//! uint8_t initVectorUnformatted[initVectorLength]; +//! +//! // This is the same field length value that is written to the ctrl register +//! initVector.byte[0] = L - 1; +//! +//! memcpy(&initVector.byte[1], initVectorUnformatted, initVectorLength); +//! +//! // Fill the remaining bytes with zeros +//! for (initVectorLength++; initVectorLength < sizeof(initVector.byte); initVectorLength++) { +//! initVector.byte[initVectorLength] = 0; +//! } +//! \endcode +//! +//! \param [in] initializationVector Pointer to an array with four 32-bit elements +//! to be used as initialization vector. +//! Elements of array must be word aligned in memory. +//! +//! \return None +// +//***************************************************************************** +extern void AESSetInitializationVector(const uint32_t *initializationVector); + +//***************************************************************************** +// +//! \brief Generate and load the initialization vector for a CCM operation. +//! +//! +//! \param [in] nonce Pointer to a nonce of length \c nonceLength. +//! +//! \param [in] nonceLength Number of bytes to copy from \c nonce when creating +//! the CCM IV. The L-value is also derived from it. +//! +//! \return None +// +//***************************************************************************** +extern void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength); + +//***************************************************************************** +// +//! \brief Read the tag out from the crypto module. +//! +//! This function copies the \c tagLength bytes from the tag calculated by the +//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag. +//! +//! \param [out] tag Pointer to an array of \c tagLength bytes. +//! +//! \param [in] tagLength Number of bytes to copy to \c tag. +//! +//! \return Returns a status code depending on the result of the transfer. +//! - \ref AES_TAG_NOT_READY if the tag is not ready yet +//! - \ref AES_SUCCESS otherwise +// +//***************************************************************************** +extern uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength); + +//***************************************************************************** +// +//! \brief Verifies the provided \c tag against calculated one +//! +//! This function compares the provided tag against the tag calculated by the +//! crypto module during the last CCM, GCM, or CBC-MAC +//! +//! This function copies the \c tagLength bytes from the tag calculated by the +//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag. +//! +//! \param [in] tag Pointer to an array of \c tagLength bytes. +//! +//! \param [in] tagLength Number of bytes to compare. +//! +//! \return Returns a status code depending on the result of the transfer. +//! - \ref AES_TAG_VERIFICATION_FAILED if the verification failed +//! - \ref AES_SUCCESS otherwise +// +//***************************************************************************** +extern uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength); + +//***************************************************************************** +// +//! \brief Transfer a key from main memory to a key area within the key store. +//! +//! The crypto DMA transfers the key and function does not return until +//! the operation completes. +//! The keyStore can only contain valid keys of one \c aesKeyLength at +//! any one point in time. The keyStore cannot contain both 128-bit and +//! 256-bit keys simultaneously. When a key of a different \c aesKeyLength +//! from the previous \c aesKeyLength is loaded, all previous keys are +//! invalidated. +//! +//! \param [in] aesKey Pointer to key. Does not need to be word-aligned. +//! +//! \param [in] aesKeyLength The key size in bytes. Currently, 128-bit, 192-bit, +//! and 256-bit keys are supported. +//! - \ref AES_128_KEY_LENGTH_BYTES +//! - \ref AES_192_KEY_LENGTH_BYTES +//! - \ref AES_256_KEY_LENGTH_BYTES +//! +//! \param [in] keyStoreArea The key store area to transfer the key to. +//! When using 128-bit keys, only the specified key store +//! area will be occupied. +//! When using 256-bit or 192-bit keys, two consecutive key areas +//! are used to store the key. +//! - \ref AES_KEY_AREA_0 +//! - \ref AES_KEY_AREA_1 +//! - \ref AES_KEY_AREA_2 +//! - \ref AES_KEY_AREA_3 +//! - \ref AES_KEY_AREA_4 +//! - \ref AES_KEY_AREA_5 +//! - \ref AES_KEY_AREA_6 +//! - \ref AES_KEY_AREA_7 +//! +//! When using 256-bit or 192-bit keys, the 8 \c keyStoreArea's are +//! split into four sets of two. Selecting any \c keyStoreArea automatically +//! occupies the second \c keyStoreArea of the tuples below: +//! +//! - (\ref AES_KEY_AREA_0, \ref AES_KEY_AREA_1) +//! - (\ref AES_KEY_AREA_2, \ref AES_KEY_AREA_3) +//! - (\ref AES_KEY_AREA_4, \ref AES_KEY_AREA_5) +//! - (\ref AES_KEY_AREA_6, \ref AES_KEY_AREA_7) +//! +//! For example: if \c keyStoreArea == \ref AES_KEY_AREA_2, +//! both \ref AES_KEY_AREA_2 and \ref AES_KEY_AREA_3 are occupied. +//! If \c keyStoreArea == \ref AES_KEY_AREA_5, both \ref AES_KEY_AREA_4 and \ref AES_KEY_AREA_5 are occupied. +//! +//! \return Returns a status code depending on the result of the transfer. +//! If there was an error in the read process itself, an error is +//! returned. +//! Otherwise, a success code is returned. +//! - \ref AES_KEYSTORE_ERROR +//! - \ref AES_SUCCESS +//! +//! \sa AESReadFromKeyStore +// +//***************************************************************************** +extern uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea); + +//***************************************************************************** +// +//! \brief Transfer a key from key store area to the internal buffers within +//! the hardware module. +//! +//! The function polls until the transfer is complete. +//! +//! \param [in] keyStoreArea The key store area to transfer the key from. When using +//! 256-bit keys, either of the occupied key areas may be +//! specified to load the key. There is no need to specify +//! the length of the key here as the key store keeps track +//! of how long a key associated with any valid key area is +//! and where is starts. +//! - \ref AES_KEY_AREA_0 +//! - \ref AES_KEY_AREA_1 +//! - \ref AES_KEY_AREA_2 +//! - \ref AES_KEY_AREA_3 +//! - \ref AES_KEY_AREA_4 +//! - \ref AES_KEY_AREA_5 +//! - \ref AES_KEY_AREA_6 +//! - \ref AES_KEY_AREA_7 +//! +//! \return Returns a status code depending on the result of the transfer. +//! When specifying a \c keyStoreArea value without a valid key in it an +//! error is returned. +//! If there was an error in the read process itself, an error is +//! returned. +//! Otherwise, a success code is returned. +//! - \ref AES_KEYSTORE_AREA_INVALID +//! - \ref AES_KEYSTORE_ERROR +//! - \ref AES_SUCCESS +//! +//! \sa AESWriteToKeyStore +// +//***************************************************************************** +extern uint32_t AESReadFromKeyStore(uint32_t keyStoreArea); + + +//***************************************************************************** +// +//! \brief Poll the interrupt status register and clear when done. +//! +//! This function polls until one of the bits in the \c irqFlags is +//! asserted. Only \ref AES_DMA_IN_DONE and \ref AES_RESULT_RDY can actually +//! trigger the interrupt line. That means that one of those should +//! always be included in \c irqFlags and will always be returned together +//! with any error codes. +//! +//! \param [in] irqFlags IRQ flags to poll and mask that the status register will be +//! masked with. May consist of any bitwise OR of the flags +//! below that includes at least one of +//! \ref AES_DMA_IN_DONE or \ref AES_RESULT_RDY : +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! - \ref AES_DMA_BUS_ERR +//! - \ref AES_KEY_ST_WR_ERR +//! - \ref AES_KEY_ST_RD_ERR +//! +//! \return Returns the IRQ status register masked with \c irqFlags. May be any +//! bitwise OR of the following masks: +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! - \ref AES_DMA_BUS_ERR +//! - \ref AES_KEY_ST_WR_ERR +//! - \ref AES_KEY_ST_RD_ERR +// +//***************************************************************************** +extern uint32_t AESWaitForIRQFlags(uint32_t irqFlags); + +//***************************************************************************** +// +//! \brief Configure AES engine for CCM operation. +//! +//! \param [in] nonceLength Length of the nonce. Must be <= 14. +//! +//! \param [in] macLength Length of the MAC. Must be <= 16. +//! +//! \param [in] encrypt Whether to set up an encrypt or decrypt operation. +//! - true: encrypt +//! - false: decrypt +//! +//! \return None +// +//***************************************************************************** +extern void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt); + +//***************************************************************************** +// +//! \brief Invalidate a key in the key store +//! +//! \param [in] keyStoreArea is the entry in the key store to invalidate. This +//! permanently deletes the key from the key store. +//! - \ref AES_KEY_AREA_0 +//! - \ref AES_KEY_AREA_1 +//! - \ref AES_KEY_AREA_2 +//! - \ref AES_KEY_AREA_3 +//! - \ref AES_KEY_AREA_4 +//! - \ref AES_KEY_AREA_5 +//! - \ref AES_KEY_AREA_6 +//! - \ref AES_KEY_AREA_7 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESInvalidateKey(uint32_t keyStoreArea) +{ + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + // Clear any previously written key at the key location + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << keyStoreArea); +} + +//***************************************************************************** +// +//! \brief Select type of operation +//! +//! \param [in] algorithm Flags that specify which type of operation the crypto +//! module shall perform. The flags are mutually exclusive. +//! - 0 : Reset the module +//! - \ref AES_ALGSEL_AES +//! - \ref AES_ALGSEL_TAG +//! - \ref AES_ALGSEL_KEY_STORE +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESSelectAlgorithm(uint32_t algorithm) +{ + ASSERT((algorithm == AES_ALGSEL_AES) || + (algorithm == AES_ALGSEL_AES | AES_ALGSEL_TAG) || + (algorithm == AES_ALGSEL_KEY_STORE)); + + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm; +} + +//***************************************************************************** +// +//! \brief Set up the next crypto module operation. +//! +//! The function uses a bitwise OR of the fields within the CRYPTO_O_AESCTL +//! register. The relevant field names have the format: +//! - CRYPTO_AESCTL_[field name] +//! +//! \param [in] ctrlMask Specifies which register fields shall be set. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESSetCtrl(uint32_t ctrlMask) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ctrlMask; +} + +//***************************************************************************** +// +//! \brief Specify length of the crypto operation. +//! +//! Despite specifying it here, the crypto DMA must still be +//! set up with the correct data length. +//! +//! \param [in] length Data length in bytes. If this +//! value is set to 0, only authentication of the AAD is +//! performed in CCM-mode and AESWriteAuthLength() must be set to +//! >0. +//! Range depends on the mode: +//! - ECB: [16] +//! - CBC: [1, sizeof(RAM)] +//! - CBC-MAC: [1, sizeof(RAM)] +//! - CCM: [0, sizeof(RAM)] +//! +//! \return None +//! +//! \sa AESWriteAuthLength +// +//***************************************************************************** +__STATIC_INLINE void AESSetDataLength(uint32_t length) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = length; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; +} + +//***************************************************************************** +// +//! \brief Specify the length of the additional authentication data (AAD). +//! +//! Despite specifying it here, the crypto DMA must still be set up with +//! the correct AAD length. +//! +//! \param [in] length Specifies how long the AAD is in a CCM operation. In CCM mode, +//! set this to 0 if no AAD is required. If set to 0, +//! AESWriteDataLength() must be set to >0. +//! Range depends on the mode: +//! - ECB: Do not call. +//! - CBC: [0] +//! - CBC-MAC: [0] +//! - CCM: [0, sizeof(RAM)] +//! +//! \return None +//! +//! \sa AESWriteDataLength +// +//***************************************************************************** +__STATIC_INLINE void AESSetAuthLength(uint32_t length) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = length; +} + +//***************************************************************************** +// +//! \brief Reset the accelerator and cancel ongoing operations +//! +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESReset(void) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_SWRESET) = 0x00000001; +} + +//***************************************************************************** +// +//! \brief Enable individual crypto interrupt sources. +//! +//! This function enables the indicated crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESIntEnable(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & AES_DMA_IN_DONE) || + (intFlags & AES_RESULT_RDY)); + + // Using level interrupt. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; + + // Enable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; +} + +//***************************************************************************** +// +//! \brief Disable individual crypto interrupt sources. +//! +//! This function disables the indicated crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESIntDisable(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & AES_DMA_IN_DONE) || + (intFlags & AES_RESULT_RDY)); + + // Disable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; +} + +//***************************************************************************** +// +//! \brief Get the current masked interrupt status. +//! +//! This function returns the masked interrupt status of the crypto module. +//! +//! \return Returns the status of the masked lines when enabled: +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +// +//***************************************************************************** +__STATIC_INLINE uint32_t AESIntStatusMasked(void) +{ + uint32_t mask; + + // Return the masked interrupt status + mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); + return(mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); +} + +//***************************************************************************** +// +//! \brief Get the current raw interrupt status. +//! +//! This function returns the raw interrupt status of the crypto module. +//! It returns both the status of the lines routed to the NVIC as well as the +//! error flags. +//! +//! \return Returns the raw interrupt status: +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! - \ref AES_DMA_BUS_ERR +//! - \ref AES_KEY_ST_WR_ERR +//! - \ref AES_KEY_ST_RD_ERR +// +//***************************************************************************** +__STATIC_INLINE uint32_t AESIntStatusRaw(void) +{ + // Return either the raw interrupt status + return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); +} + +//***************************************************************************** +// +//! \brief Clear crypto interrupt sources. +//! +//! The specified crypto interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in the module until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! +//! \param [in] intFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESIntClear(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & AES_DMA_IN_DONE) || + (intFlags & AES_RESULT_RDY)); + + // Clear the requested interrupt sources, + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = intFlags; +} + +//***************************************************************************** +// +//! \brief Register an interrupt handler for a crypto interrupt. +//! +//! This function does the actual registering of the interrupt handler. This +//! function enables the global interrupt in the interrupt controller; specific +//! crypto interrupts must be enabled via \ref AESIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param handlerFxn is a pointer to the function to be called when the +//! crypto interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void AESIntRegister(void (*handlerFxn)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, handlerFxn); + + // Enable the crypto interrupt. + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregister an interrupt handler for a crypto interrupt. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler called when a crypto interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void AESIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AESStartDMAOperation + #undef AESStartDMAOperation + #define AESStartDMAOperation ROM_AESStartDMAOperation + #endif + #ifdef ROM_AESSetInitializationVector + #undef AESSetInitializationVector + #define AESSetInitializationVector ROM_AESSetInitializationVector + #endif + #ifdef ROM_AESWriteCCMInitializationVector + #undef AESWriteCCMInitializationVector + #define AESWriteCCMInitializationVector ROM_AESWriteCCMInitializationVector + #endif + #ifdef ROM_AESReadTag + #undef AESReadTag + #define AESReadTag ROM_AESReadTag + #endif + #ifdef ROM_AESVerifyTag + #undef AESVerifyTag + #define AESVerifyTag ROM_AESVerifyTag + #endif + #ifdef ROM_AESWriteToKeyStore + #undef AESWriteToKeyStore + #define AESWriteToKeyStore ROM_AESWriteToKeyStore + #endif + #ifdef ROM_AESReadFromKeyStore + #undef AESReadFromKeyStore + #define AESReadFromKeyStore ROM_AESReadFromKeyStore + #endif + #ifdef ROM_AESWaitForIRQFlags + #undef AESWaitForIRQFlags + #define AESWaitForIRQFlags ROM_AESWaitForIRQFlags + #endif + #ifdef ROM_AESConfigureCCMCtrl + #undef AESConfigureCCMCtrl + #define AESConfigureCCMCtrl ROM_AESConfigureCCMCtrl + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AES_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_batmon.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_batmon.c new file mode 100644 index 0000000..e5037dc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_batmon.c @@ -0,0 +1,80 @@ +/****************************************************************************** +* Filename: aon_batmon.c +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Driver for the AON Battery and Temperature Monitor +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_batmon.h" +#include "../inc/hw_fcfg1.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONBatMonTemperatureGetDegC + #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC +#endif + +//***************************************************************************** +// +// AONBatMonTemperatureGetDegC() +// Returns sign extended temperature in Deg C (-256 .. +255) +// +//***************************************************************************** +int32_t +AONBatMonTemperatureGetDegC( void ) +{ + int32_t signedTemp ; // Signed extended temperature with 8 fractional bits + int32_t tempCorrection ; // Voltage dependent temp correction with 8 fractional bits + int8_t voltageSlope ; // Signed byte value representing the TEMP slope with battery voltage, in degrees C/V, with 4 fractional bits. + + // Shift left then right to sign extend the BATMON_TEMP field + signedTemp = ((((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_TEMP )) + << ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )) + >> ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )); + + // Typecasting voltageSlope to int8_t prior to assignment in order to make sure sign extension works properly + // Using byte read (HWREGB) in order to make more efficient code since voltageSlope is assigned to bits[7:0] of FCFG1_O_MISC_TRIM + voltageSlope = ((int8_t)HWREGB( FCFG1_BASE + FCFG1_O_MISC_TRIM )); + tempCorrection = (( voltageSlope * (((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT )) - 0x300 )) >> 4 ); + + return ((( signedTemp - tempCorrection ) + 0x80 ) >> 8 ); +} + + +// See aon_batmon.h for implementation of remaining functions diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_batmon.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_batmon.h new file mode 100644 index 0000000..ce7d323 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_batmon.h @@ -0,0 +1,306 @@ +/****************************************************************************** +* Filename: aon_batmon.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the AON Battery and Temperature +* Monitor +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonbatmon_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_BATMON_H__ +#define __AON_BATMON_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_batmon.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC +#endif + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enable the temperature and battery monitoring. +//! +//! This function will enable the measurements of the temperature and the +//! battery voltage. +//! +//! To speed up the measurement of the levels the measurement can be enabled +//! before configuring the battery and temperature settings. When all of the +//! AON_BATMON registers are configured, the calculation of the voltage and +//! temperature values can be enabled (the measurement will now take +//! effect/propagate to other blocks). +//! +//! It is possible to enable both at the same time, after the AON_BATMON +//! registers are configured, but then the first values will be ready at a +//! later point compared to the scenario above. +//! +//! \note Temperature and battery voltage measurements are not done in +//! parallel. The measurement cycle is controlled by a hardware Finite State +//! Machine. First the temperature and then the battery voltage each taking +//! one cycle to complete. However, if the comparator measuring the battery +//! voltage detects a change on the reference value, a new measurement of the +//! battery voltage only is performed immediately after. This has no impact on +//! the cycle count. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONBatMonEnable(void) +{ + // Enable the measurements. + HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = + AON_BATMON_CTL_CALC_EN | + AON_BATMON_CTL_MEAS_EN; +} + +//***************************************************************************** +// +//! \brief Disable the temperature and battery monitoring. +//! +//! This function will disable the measurements of the temperature and the +//! battery voltage. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONBatMonDisable(void) +{ + // Disable the measurements. + HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = 0; +} + + +//***************************************************************************** +// +//! \brief Get the current temperature measurement as a signed value in Deg Celsius. +//! +//! This function returns an calibrated and rounded value in degree Celsius. +//! The temperature measurements are updated every cycle. +//! +//! \note The temperature drifts slightly depending on the battery voltage. +//! This function compensates for this drift and returns a calibrated temperature. +//! +//! \note Use the function AONBatMonNewTempMeasureReady() to test for a new measurement. +//! +//! \return Returns signed integer part of temperature in Deg C (-256 .. +255) +//! +//! \sa AONBatMonNewTempMeasureReady() +// +//***************************************************************************** +extern int32_t AONBatMonTemperatureGetDegC( void ); + +//***************************************************************************** +// +//! \brief Get the battery monitor measurement. +//! +//! This function will return the current battery monitor measurement. +//! The battery voltage measurements are updated every cycle. +//! +//! \note The returned value is NOT sign-extended! +//! +//! \note Use the function \ref AONBatMonNewBatteryMeasureReady() to test for +//! a change in measurement. +//! +//! \return Returns the current battery monitor value of the battery voltage +//! measurement in a format size <3.8> in units of volt. +//! +//! \sa AONBatMonNewBatteryMeasureReady() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONBatMonBatteryVoltageGet(void) +{ + uint32_t ui32CurrentBattery; + + ui32CurrentBattery = HWREG(AON_BATMON_BASE + AON_BATMON_O_BAT); + + // Return the current battery voltage measurement. + return (ui32CurrentBattery >> AON_BATMON_BAT_FRAC_S); +} + +//***************************************************************************** +// +//! \brief Check if battery monitor measurement has changed. +//! +//! This function checks if a new battery monitor value is available. If the +//! measurement value has \b changed since last clear the function returns \c true. +//! +//! If the measurement has changed the function will automatically clear the +//! status bit. +//! +//! \note It is always possible to read out the current value of the +//! battery level using AONBatMonBatteryVoltageGet() but this function can be +//! used to check if the measurement has changed. +//! +//! \return Returns \c true if the measurement value has changed and \c false +//! otherwise. +//! +//! \sa AONBatMonNewTempMeasureReady(), AONBatMonBatteryVoltageGet() +// +//***************************************************************************** +__STATIC_INLINE bool +AONBatMonNewBatteryMeasureReady(void) +{ + bool bStatus; + + // Check the status bit. + bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) & + AON_BATMON_BATUPD_STAT ? true : false; + + // Clear status bit if set. + if(bStatus) + { + HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) = 1; + } + + // Return status. + return (bStatus); +} + +//***************************************************************************** +// +//! \brief Check if temperature monitor measurement has changed. +//! +//! This function checks if a new temperature value is available. If the +//! measurement value has \b changed since last clear the function returns \c true. +//! +//! If the measurement has changed the function will automatically clear the +//! status bit. +//! +//! \note It is always possible to read out the current value of the +//! temperature using \ref AONBatMonTemperatureGetDegC() +//! but this function can be used to check if the measurement has changed. +//! +//! \return Returns \c true if the measurement value has changed and \c false +//! otherwise. +//! +//! \sa AONBatMonNewBatteryMeasureReady(), AONBatMonTemperatureGetDegC() +// +//***************************************************************************** +__STATIC_INLINE bool +AONBatMonNewTempMeasureReady(void) +{ + bool bStatus; + + // Check the status bit. + bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) & + AON_BATMON_TEMPUPD_STAT ? true : false; + + // Clear status bit if set. + if(bStatus) + { + HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) = 1; + } + + // Return status. + return (bStatus); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONBatMonTemperatureGetDegC + #undef AONBatMonTemperatureGetDegC + #define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_BATMON_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event.c new file mode 100644 index 0000000..0e1559b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event.c @@ -0,0 +1,299 @@ +/****************************************************************************** +* Filename: aon_event.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the AON Event fabric. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_event.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONEventMcuWakeUpSet + #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet + #undef AONEventMcuWakeUpGet + #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet + #undef AONEventAuxWakeUpSet + #define AONEventAuxWakeUpSet NOROM_AONEventAuxWakeUpSet + #undef AONEventAuxWakeUpGet + #define AONEventAuxWakeUpGet NOROM_AONEventAuxWakeUpGet + #undef AONEventMcuSet + #define AONEventMcuSet NOROM_AONEventMcuSet + #undef AONEventMcuGet + #define AONEventMcuGet NOROM_AONEventMcuGet +#endif + +//***************************************************************************** +// +// Select event source for the specified MCU wakeup programmable event +// +//***************************************************************************** +void +AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT((ui32MCUWUEvent == AON_EVENT_MCU_WU0) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU1) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU2) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU3)); + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL); + + if(ui32MCUWUEvent == AON_EVENT_MCU_WU0) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU0_EV_S; + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU1) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU1_EV_S; + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU2) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU2_EV_S; + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU3) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU3_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU3_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) = ui32Ctrl; +} + +//***************************************************************************** +// +// Get event source for the specified MCU wakeup programmable event +// +//***************************************************************************** +uint32_t +AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent) +{ + uint32_t ui32EventSrc; + + // Check the arguments. + ASSERT((ui32MCUWUEvent == AON_EVENT_MCU_WU0) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU1) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU2) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU3)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL); + + if(ui32MCUWUEvent == AON_EVENT_MCU_WU0) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU0_EV_M) >> + AON_EVENT_MCUWUSEL_WU0_EV_S); + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU1) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU1_EV_M) >> + AON_EVENT_MCUWUSEL_WU1_EV_S); + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU2) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU2_EV_M) >> + AON_EVENT_MCUWUSEL_WU2_EV_S); + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU3) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU3_EV_M) >> + AON_EVENT_MCUWUSEL_WU3_EV_S); + } + + // Should never get to this statement, but suppress warning. + ASSERT(0); + return(0); +} + +//***************************************************************************** +// +// Select event source for the specified AUX wakeup programmable event +// +//***************************************************************************** +void +AONEventAuxWakeUpSet(uint32_t ui32AUXWUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT((ui32AUXWUEvent == AON_EVENT_AUX_WU0) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU1) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU2)); + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL); + + if(ui32AUXWUEvent == AON_EVENT_AUX_WU0) + { + ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU0_EV_S; + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU1) + { + ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU1_EV_S; + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU2) + { + ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU2_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL) = ui32Ctrl; +} + +//***************************************************************************** +// +// Get event source for the specified AUX wakeup programmable event +// +//***************************************************************************** +uint32_t +AONEventAuxWakeUpGet(uint32_t ui32AUXWUEvent) +{ + uint32_t ui32EventSrc; + + // Check the arguments. + ASSERT((ui32AUXWUEvent == AON_EVENT_AUX_WU0) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU1) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU2)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL); + + if(ui32AUXWUEvent == AON_EVENT_AUX_WU0) + { + return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU0_EV_M) >> + AON_EVENT_AUXWUSEL_WU0_EV_S); + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU1) + { + return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU1_EV_M) >> + AON_EVENT_AUXWUSEL_WU1_EV_S); + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU2) + { + return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU2_EV_M) >> + AON_EVENT_AUXWUSEL_WU2_EV_S); + } + + // Should never get to this statement, but suppress warning. + ASSERT(0); + return(0); +} + +//***************************************************************************** +// +// Select event source for the specified programmable event forwarded to the +// MCU event fabric +// +//***************************************************************************** +void +AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL) = ui32Ctrl; +} + +//***************************************************************************** +// +// Get source for the specified programmable event forwarded to the MCU event +// fabric. +// +//***************************************************************************** +uint32_t +AONEventMcuGet(uint32_t ui32MCUEvent) +{ + uint32_t ui32EventSrc; + + // Check the arguments. + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S); + } + + // Should never get to this statement, but suppress warning. + ASSERT(0); + return(0); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event.h new file mode 100644 index 0000000..cdceba4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event.h @@ -0,0 +1,620 @@ +/****************************************************************************** +* Filename: aon_event.h +* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) +* Revision: 49506 +* +* Description: Defines and prototypes for the AON Event fabric. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonevent_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_EVENT_H__ +#define __AON_EVENT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_device.h" +#include "../inc/hw_aon_event.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet + #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet + #define AONEventAuxWakeUpSet NOROM_AONEventAuxWakeUpSet + #define AONEventAuxWakeUpGet NOROM_AONEventAuxWakeUpGet + #define AONEventMcuSet NOROM_AONEventMcuSet + #define AONEventMcuGet NOROM_AONEventMcuGet +#endif + +//***************************************************************************** +// +// Event sources for the event AON fabric. +// Note: Events are level-triggered active high +// +//***************************************************************************** +// AON_EVENT_DIO0 // Edge detect on DIO0. See hw_device.h +// ... // ... +// AON_EVENT_DIO31 // Edge detect on DIO31. See hw_device.h +#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC. + // Event ID 33 is reserved for future use + // Event ID 34 is reserved for future use +#define AON_EVENT_RTC_CH0 35 // RTC channel 0 +#define AON_EVENT_RTC_CH1 36 // RTC channel 1 +#define AON_EVENT_RTC_CH2 37 // RTC channel 2 +#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event +#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event +#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event +#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event +#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +#define AON_EVENT_JTAG 43 // JTAG generated event +#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0 +#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1 +#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2 +#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX) +#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX) +#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed +#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out +#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event +#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event +#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event +#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event +#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +#define AON_EVENT_AUX_COMPB_ASYNC_N 56 // Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B + // Event ID 57-62 is reserved for future use +#define AON_EVENT_NONE 63 // No event, always low + +// Keeping backward compatibility until major revision number is incremented +#define AON_EVENT_RTC0 ( AON_EVENT_RTC_CH0 ) + +//***************************************************************************** +// +// Values that can be passed to AONEventMCUWakeUpSet() and returned +// by AONEventMCUWakeUpGet(). +// +//***************************************************************************** +#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0 +#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1 +#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2 +#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3 + +//***************************************************************************** +// +// Values that can be passed to AONEventAuxWakeUpSet() and AONEventAuxWakeUpGet() +// +//***************************************************************************** +#define AON_EVENT_AUX_WU0 0 // Programmable AUX wake-up event 0 +#define AON_EVENT_AUX_WU1 1 // Programmable AUX wake-up event 1 +#define AON_EVENT_AUX_WU2 2 // Programmable AUX wake-up event 2 + +//***************************************************************************** +// +// Values that can be passed to AONEventMcuSet() and AONEventMcuGet() +// +//***************************************************************************** +#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3) +#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3) +#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3) + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Select event source for the specified MCU wake-up programmable event. +//! +//! The AON event fabric has several programmable events that can wake up the MCU. +//! +//! \note The programmable event sources are effectively OR'ed together +//! to form a single wake-up event. +//! +//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources. +//! - \ref AON_EVENT_MCU_WU0 +//! - \ref AON_EVENT_MCU_WU1 +//! - \ref AON_EVENT_MCU_WU2 +//! - \ref AON_EVENT_MCU_WU3 +//! \param ui32EventSrc is an event source for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventMcuWakeUpGet() +// +//***************************************************************************** +extern void AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, + uint32_t ui32EventSrc); + +//***************************************************************************** +// +//! \brief Get event source for the specified MCU wake-up programmable event. +//! +//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources. +//! - \ref AON_EVENT_MCU_WU0 +//! - \ref AON_EVENT_MCU_WU1 +//! - \ref AON_EVENT_MCU_WU2 +//! - \ref AON_EVENT_MCU_WU3 +//! +//! \return Returns the event source for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventMcuWakeUpSet() +// +//***************************************************************************** +extern uint32_t AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent); + +//***************************************************************************** +// +//! \brief Select event source for the specified AUX wake-up programmable event. +//! +//! The AON event fabric has a total of three programmable events that can +//! wake-up the AUX domain. +//! +//! \note The three programmable event sources are effectively OR'ed together +//! to form a single wake-up event. +//! +//! \param ui32AUXWUEvent is one of three programmable AUX wake-up event sources. +//! - \ref AON_EVENT_AUX_WU0 +//! - \ref AON_EVENT_AUX_WU1 +//! - \ref AON_EVENT_AUX_WU2 +//! \param ui32EventSrc is an event sources for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventAuxWakeUpGet() +// +//***************************************************************************** +extern void AONEventAuxWakeUpSet(uint32_t ui32AUXWUEvent, + uint32_t ui32EventSrc); + +//***************************************************************************** +// +//! \brief Get event source for the specified AUX wake-up programmable event. +//! +//! The AON event fabric has a total of three programmable events that can +//! wake-up the AUX domain. +//! +//! \param ui32AUXWUEvent is one of three programmable AUX wake-up event sources. +//! - \ref AON_EVENT_AUX_WU0 +//! - \ref AON_EVENT_AUX_WU1 +//! - \ref AON_EVENT_AUX_WU2 +//! +//! \return Returns the event source for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventAuxWakeUpSet() +// +//***************************************************************************** +extern uint32_t AONEventAuxWakeUpGet(uint32_t ui32AUXWUEvent); + +//***************************************************************************** +// +//! \brief Select event source for the specified programmable event forwarded to the +//! MCU event fabric. +//! +//! The AON event fabric has a total of three programmable events that can +//! be forwarded to the MCU event fabric. +//! +//! \note The three programmable event sources are forwarded to the MCU Event +//! Fabric as: +//! - AON_PROG0 +//! - AON_PROG1 +//! - AON_PROG2 +//! +//! \param ui32MCUEvent is one of three programmable events forwarded to the +//! MCU event fabric. +//! - \ref AON_EVENT_MCU_EVENT0 +//! - \ref AON_EVENT_MCU_EVENT1 +//! - \ref AON_EVENT_MCU_EVENT2 +//! \param ui32EventSrc is an event source for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventMcuGet() +// +//***************************************************************************** +extern void AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc); + +//***************************************************************************** +// +//! \brief Get source for the specified programmable event forwarded to the MCU event +//! fabric. +//! +//! The AON event fabric has a total of three programmable events that can +//! be forwarded to the MCU event fabric. +//! +//! \param ui32MCUEvent is one of three programmable events forwarded to the +//! MCU event fabric. +//! - \ref AON_EVENT_MCU_EVENT0 +//! - \ref AON_EVENT_MCU_EVENT1 +//! - \ref AON_EVENT_MCU_EVENT2 +//! +//! \return Returns the event source for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventMcuSet() +// +//***************************************************************************** +extern uint32_t AONEventMcuGet(uint32_t ui32MCUEvent); + +//***************************************************************************** +// +//! \brief Select event source forwarded to AON Real Time Clock (RTC). +//! +//! A programmable event can be forwarded to the AON real time clock +//! for triggering a capture event on RTC channel 1. +//! +//! \param ui32EventSrc is an event source for the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventRtcGet() +// +//***************************************************************************** +__STATIC_INLINE void +AONEventRtcSet(uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL); + ui32Ctrl &= ~(AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S; + + HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL) = ui32Ctrl; +} + +//***************************************************************************** +// +//! \brief Get event source forwarded to AON Real Time Clock (RTC). +//! +//! A programmable event can be forwarded to the AON real time clock +//! for triggering a capture event on RTC channel 1. +//! +//! \return Returns the event source to the event AON fabric. +//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h +//! - ... +//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventRtcSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONEventRtcGet(void) +{ + uint32_t ui32EventSrc; + + // Return the active event. + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL); + + return ((ui32EventSrc & AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M) >> + AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONEventMcuWakeUpSet + #undef AONEventMcuWakeUpSet + #define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet + #endif + #ifdef ROM_AONEventMcuWakeUpGet + #undef AONEventMcuWakeUpGet + #define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet + #endif + #ifdef ROM_AONEventAuxWakeUpSet + #undef AONEventAuxWakeUpSet + #define AONEventAuxWakeUpSet ROM_AONEventAuxWakeUpSet + #endif + #ifdef ROM_AONEventAuxWakeUpGet + #undef AONEventAuxWakeUpGet + #define AONEventAuxWakeUpGet ROM_AONEventAuxWakeUpGet + #endif + #ifdef ROM_AONEventMcuSet + #undef AONEventMcuSet + #define AONEventMcuSet ROM_AONEventMcuSet + #endif + #ifdef ROM_AONEventMcuGet + #undef AONEventMcuGet + #define AONEventMcuGet ROM_AONEventMcuGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_EVENT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event_doc.h new file mode 100644 index 0000000..e1fcea8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event_doc.h @@ -0,0 +1,61 @@ +/****************************************************************************** +* Filename: aon_event_doc.h +* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) +* Revision: 49506 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonevent_api +//! @{ +//! \section sec_aonevent Introduction +//! +//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and +//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers +//! to the AON event fabric. For more information on MCU event fabric, see [MCU event API](@ref event_api). +//! +//! The AON event fabric is a configurable combinatorial router between AON event sources and event +//! subscribers in both AON and MCU domains. The API to control the AON event fabric configuration +//! can be grouped based on the event subscriber to configure: +//! +//! - Wake-up events. +//! - MCU wake-up event +//! - @ref AONEventMcuWakeUpSet() +//! - @ref AONEventMcuWakeUpGet() +//! - AUX wake-up event +//! - @ref AONEventAuxWakeUpSet() +//! - @ref AONEventAuxWakeUpGet() +//! - AON RTC receives a single programmable event line from the AON event fabric. For more information, see [AON RTC API](@ref aonrtc_api). +//! - @ref AONEventRtcSet() +//! - @ref AONEventRtcGet() +//! - MCU event fabric receives a number of programmable event lines from the AON event fabric. For more information, see [MCU event API](@ref event_api). +//! - @ref AONEventMcuSet() +//! - @ref AONEventMcuGet() +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc.c new file mode 100644 index 0000000..d4475b7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc.c @@ -0,0 +1,39 @@ +/****************************************************************************** +* Filename: aon_ioc.c +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Driver for the AON IO Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_ioc.h" diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc.h new file mode 100644 index 0000000..513e0e2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc.h @@ -0,0 +1,292 @@ +/****************************************************************************** +* Filename: aon_ioc.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the AON IO Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonioc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_IOC_H__ +#define __AON_IOC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_ioc.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the drive strength +// +//***************************************************************************** +#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength +#define AONIOC_DRV_STR_2 0x00000001 +#define AONIOC_DRV_STR_3 0x00000003 +#define AONIOC_DRV_STR_4 0x00000002 +#define AONIOC_DRV_STR_5 0x00000006 +#define AONIOC_DRV_STR_6 0x00000007 +#define AONIOC_DRV_STR_7 0x00000005 +#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength + +#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN) +#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED) +#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX) + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure drive strength values for the manual drive strength options. +//! +//! This function defines the general drive strength settings for the non-AUTO +//! drive strength options in the MCU IOC. Consequently, if all IOs are using the +//! automatic drive strength option this function has no effect. +//! +//! Changing the drive strength values affects all current modes (Low-Current, +//! High-Current, and Extended-Current). Current mode for individual IOs is set in +//! MCU IOC by \ref IOCIODrvStrengthSet(). +//! +//! \note Values are Gray encoded. Simply incrementing values to increase drive +//! strength will not work. +//! +//! \param ui32DriveLevel +//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. Default value is selected +//! to give minimum 2/4/8 mA @3.3V for Low-Current mode, High-Current mode, +//! and Extended-Current mode respectively. +//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. Default value is selected +//! to give minimum 2/4/8 mA @2.5V for Low-Current mode, High-Current mode, +//! and Extended-Current mode respectively. +//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. Default value is selected +//! to give minimum 2/4/8 mA @1.8V for Low-Current mode, High-Current mode, +//! and Extended-Current mode respectively. +//! \param ui32DriveStrength sets the value used by IOs configured as non-AUTO drive strength in MCU IOC. +//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength +//! - \ref AONIOC_DRV_STR_2 +//! - \ref AONIOC_DRV_STR_3 +//! - \ref AONIOC_DRV_STR_4 +//! - \ref AONIOC_DRV_STR_5 +//! - \ref AONIOC_DRV_STR_6 +//! - \ref AONIOC_DRV_STR_7 +//! - \ref AONIOC_DRV_STR_8 : Highest drive strength +//! +//! \return None +//! +//! \sa \ref AONIOCDriveStrengthGet(), \ref IOCIODrvStrengthSet() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOCDriveStrengthSet(uint32_t ui32DriveLevel, uint32_t ui32DriveStrength) +{ + ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) || + (ui32DriveLevel == AONIOC_DRV_LVL_MED) || + (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); + ASSERT((ui32DriveStrength == AONIOC_DRV_STR_1) || + (ui32DriveStrength == AONIOC_DRV_STR_2) || + (ui32DriveStrength == AONIOC_DRV_STR_3) || + (ui32DriveStrength == AONIOC_DRV_STR_4) || + (ui32DriveStrength == AONIOC_DRV_STR_5) || + (ui32DriveStrength == AONIOC_DRV_STR_6) || + (ui32DriveStrength == AONIOC_DRV_STR_7) || + (ui32DriveStrength == AONIOC_DRV_STR_8)); + + // Set the drive strength. + HWREG(AON_IOC_BASE + ui32DriveLevel) = ui32DriveStrength; +} + +//***************************************************************************** +// +//! \brief Get a specific drive level setting for all IOs. +//! +//! Use this function to read the drive strength setting for a specific +//! IO drive level. +//! +//! \note Values are Gray encoded. +//! +//! \param ui32DriveLevel is the specific drive level to get the setting for. +//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. +//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. +//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. +//! +//! \return Returns the requested drive strength level setting for all IOs. +//! Possible values are: +//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength +//! - \ref AONIOC_DRV_STR_2 +//! - \ref AONIOC_DRV_STR_3 +//! - \ref AONIOC_DRV_STR_4 +//! - \ref AONIOC_DRV_STR_5 +//! - \ref AONIOC_DRV_STR_6 +//! - \ref AONIOC_DRV_STR_7 +//! - \ref AONIOC_DRV_STR_8 : Highest drive strength +//! +//! \sa AONIOCDriveStrengthSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONIOCDriveStrengthGet(uint32_t ui32DriveLevel) +{ + // Check the arguments. + ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) || + (ui32DriveLevel == AONIOC_DRV_LVL_MED) || + (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); + + // Return the drive strength value. + return( HWREG(AON_IOC_BASE + ui32DriveLevel) ); +} + +//***************************************************************************** +// +//! \brief Freeze the IOs. +//! +//! To retain the values of the output IOs during a powerdown/shutdown of the +//! device all IO latches in the AON domain should be frozen in their current +//! state. This ensures that software can regain control of the IOs after a +//! reboot without the IOs first falling back to the default values (i.e. input +//! and no pull). +//! +//! \return None +//! +//! \sa AONIOCFreezeDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOCFreezeEnable(void) +{ + // Set the AON IO latches as static. + HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = 0x0; +} + +//***************************************************************************** +// +//! \brief Un-freeze the IOs. +//! +//! When rebooting the chip after it has entered powerdown/shutdown mode, the +//! software can regain control of the IOs by setting the IO latches as +//! transparent. The IOs should not be unfrozen before software has restored +//! the functionality of the IO. +//! +//! \return None +//! +//! \sa AONIOCFreezeEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOCFreezeDisable(void) +{ + // Set the AON IOC latches as transparent. + HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = AON_IOC_IOCLATCH_EN; +} + +//***************************************************************************** +// +//! \brief Disable the 32kHz clock output. +//! +//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality +//! in the IOC is bypassed. Therefore, the programmer needs to call this +//! function to disable the clock output. +//! +//! \return None +//! +//! \sa AONIOC32kHzOutputEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOC32kHzOutputDisable(void) +{ + // Disable the LF clock output. + HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = AON_IOC_CLK32KCTL_OE_N; +} + +//***************************************************************************** +// +//! \brief Enable the 32kHz clock output. +//! +//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality +//! in the IOC is bypassed. Therefore, the programmer needs to call this +//! function to enable the clock output. +//! +//! \return None +//! +//! \sa AONIOC32kHzOutputDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOC32kHzOutputEnable(void) +{ + // Enable the LF clock output. + HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = 0x0; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_IOC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc_doc.h new file mode 100644 index 0000000..7fe0e93 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc_doc.h @@ -0,0 +1,65 @@ +/****************************************************************************** +* Filename: aon_ioc_doc.h +* Revised: 2016-03-30 11:01:30 +0200 (Wed, 30 Mar 2016) +* Revision: 45969 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonioc_api +//! @{ +//! \section sec_aonioc Introduction +//! +//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO). +//! The IOC consists of two APIs: +//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it. +//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc. +//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is +//! routed to a DIO for external use. +//! +//! For more information on the MCU IOC see the [IOC API](\ref ioc_api). +//! +//! \section sec_aonioc_api API +//! +//! The API functions can be grouped like this: +//! +//! Freeze IOs while MCU domain is powered down: +//! - \ref AONIOCFreezeEnable() +//! - \ref AONIOCFreezeDisable() +//! +//! Output LF clock to a DIO: +//! - \ref AONIOC32kHzOutputEnable() +//! - \ref AONIOC32kHzOutputDisable() +//! +//! Configure the value of drive strength for the three manual MCU IOC settings (MIN, MED, MAX): +//! - \ref AONIOCDriveStrengthSet() +//! - \ref AONIOCDriveStrengthGet() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc.c new file mode 100644 index 0000000..98821e1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc.c @@ -0,0 +1,102 @@ +/****************************************************************************** +* Filename: aon_rtc.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the AON RTC. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_rtc.h" +#include "cpu.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONRTCCurrentCompareValueGet + #define AONRTCCurrentCompareValueGet NOROM_AONRTCCurrentCompareValueGet + #undef AONRTCCurrent64BitValueGet + #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet +#endif + + +//***************************************************************************** +// +// Get the current value of the RTC counter in a format compatible to the compare registers. +// +//***************************************************************************** +uint32_t +AONRTCCurrentCompareValueGet( void ) +{ + uint32_t ui32CurrentSec ; + uint32_t ui32CurrentSubSec ; + uint32_t ui32SecondSecRead ; + + // Reading SEC both before and after SUBSEC in order to detect if SEC incremented while reading SUBSEC + // If SEC incremented, we can't be sure which SEC the SUBSEC belongs to, so repeating the sequence then. + do { + ui32CurrentSec = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + ui32CurrentSubSec = HWREG( AON_RTC_BASE + AON_RTC_O_SUBSEC ); + ui32SecondSecRead = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + } while ( ui32CurrentSec != ui32SecondSecRead ); + + return (( ui32CurrentSec << 16 ) | ( ui32CurrentSubSec >> 16 )); +} + +//***************************************************************************** +// +// Get the current 64-bit value of the RTC counter. +// +//***************************************************************************** +uint64_t +AONRTCCurrent64BitValueGet( void ) +{ + union { + uint64_t returnValue ; + uint32_t secAndSubSec[ 2 ] ; + } currentRtc ; + uint32_t ui32SecondSecRead ; + + // Reading SEC both before and after SUBSEC in order to detect if SEC incremented while reading SUBSEC + // If SEC incremented, we can't be sure which SEC the SUBSEC belongs to, so repeating the sequence then. + do { + currentRtc.secAndSubSec[ 1 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + currentRtc.secAndSubSec[ 0 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SUBSEC ); + ui32SecondSecRead = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + } while ( currentRtc.secAndSubSec[ 1 ] != ui32SecondSecRead ); + + return ( currentRtc.returnValue ); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc.h new file mode 100644 index 0000000..eb98dec --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc.h @@ -0,0 +1,936 @@ +/****************************************************************************** +* Filename: aon_rtc.h +* Revised: 2017-08-16 15:13:43 +0200 (Wed, 16 Aug 2017) +* Revision: 49593 +* +* Description: Defines and prototypes for the AON RTC +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonrtc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_RTC_H__ +#define __AON_RTC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_rtc.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONRTCCurrentCompareValueGet NOROM_AONRTCCurrentCompareValueGet + #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet +#endif + +//***************************************************************************** +// +// Values that can be passed to most of the AON_RTC APIs as the ui32Channel +// parameter. +// +//***************************************************************************** +#define AON_RTC_CH_NONE 0x0 // RTC No channel +#define AON_RTC_CH0 0x1 // RTC Channel 0 +#define AON_RTC_CH1 0x2 // RTC Channel 1 +#define AON_RTC_CH2 0x4 // RTC Channel 2 +#define AON_RTC_ACTIVE 0x8 // RTC Active + +//***************************************************************************** +// +// Values that can be passed to AONRTCConfigDelay as the ui32Delay parameter. +// +//***************************************************************************** +#define AON_RTC_CONFIG_DELAY_NODELAY 0 // NO DELAY +#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle +#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles +#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles +#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles +#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles +#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles +#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles +#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles +#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles +#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles +#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles +#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles +#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles + +//***************************************************************************** +// +// Values that can be passed to AONRTCSetModeCH1 as the ui32Mode +// parameter. +// +//***************************************************************************** +#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode +#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode + +//***************************************************************************** +// +// Values that can be passed to AONRTCSetModeCH2 as the ui32Mode +// parameter. +// +//***************************************************************************** +#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode +#define AON_RTC_MODE_CH2_NORMALCOMPARE 0 // Normal compare mode + +//***************************************************************************** +// +// Mutliplication factor for converting from seconds to corresponding time in +// the "CompareValue" format. +// The factor correspond to the compare value format described in the registers +// \ref AON_RTC_O_CH0CMP, \ref AON_RTC_O_CH1CMP and \ref AON_RTC_O_CH2CMP. +// Example1: +// 4 milliseconds in CompareValue format can be written like this: +// ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT )) +// Example2: +// 4 seconds in CompareValue format can be written like this: +// ( 4 * FACTOR_SEC_TO_COMP_VAL_FORMAT ) +// +//***************************************************************************** +#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enable the RTC. +//! +//! Enable the AON Real Time Clock. +//! +//! \note Event generation for each of the three channels must also be enabled +//! using the function AONRTCChannelEnable(). +//! +//! \return None +//! +//! \sa AONRTCChannelEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCEnable(void) +{ + // Enable RTC. + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disable the RTC. +//! +//! Disable the AON Real Time Clock. +//! +//! \note Event generation for each of the three channels can also be disabled +//! using the function AONRTCChannelDisable(). +//! +//! \return None +//! +//! \sa AONRTCChannelDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCDisable(void) +{ + // Disable RTC + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Reset the RTC. +//! +//! Reset the AON Real Time Clock. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCReset(void) +{ + // Reset RTC. + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_RESET_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Check if the RTC is active (enabled). +//! +//! \return Returns the status of the RTC. +//! - false : RTC is disabled +//! - true : RTC is enabled +// +//***************************************************************************** +__STATIC_INLINE bool +AONRTCActive(void) +{ + // Read if RTC is enabled + return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN)); +} + +//***************************************************************************** +// +//! \brief Check if an RTC channel is active (enabled). +//! +//! \param ui32Channel specifies the RTC channel to check status of. +//! Parameter must be one (and only one) of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return Returns the status of the requested channel: +//! - false : Channel is disabled +//! - true : Channel is enabled +// +//***************************************************************************** +__STATIC_INLINE bool +AONRTCChannelActive(uint32_t ui32Channel) +{ + uint32_t uint32Status = 0; + + if(ui32Channel & AON_RTC_CH0) + { + uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN); + } + + if(ui32Channel & AON_RTC_CH1) + { + uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN); + } + + if(ui32Channel & AON_RTC_CH2) + { + uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN); + } + + return(uint32Status); +} + +//***************************************************************************** +// +//! \brief Configure Event Delay for the RTC. +//! +//! Each event from the three individual channels can generate a delayed +//! event. The delay time for these events is set using this function. +//! The delay is measured in clock cycles. +//! +//! \note There is only one delay setting shared for all three channels. +//! +//! \param ui32Delay specifies the delay time for delayed events. +//! Parameter must be one of the following: +//! - \ref AON_RTC_CONFIG_DELAY_NODELAY +//! - \ref AON_RTC_CONFIG_DELAY_1 +//! - \ref AON_RTC_CONFIG_DELAY_2 +//! - \ref AON_RTC_CONFIG_DELAY_4 +//! - \ref AON_RTC_CONFIG_DELAY_8 +//! - \ref AON_RTC_CONFIG_DELAY_16 +//! - \ref AON_RTC_CONFIG_DELAY_32 +//! - \ref AON_RTC_CONFIG_DELAY_48 +//! - \ref AON_RTC_CONFIG_DELAY_64 +//! - \ref AON_RTC_CONFIG_DELAY_80 +//! - \ref AON_RTC_CONFIG_DELAY_96 +//! - \ref AON_RTC_CONFIG_DELAY_112 +//! - \ref AON_RTC_CONFIG_DELAY_128 +//! - \ref AON_RTC_CONFIG_DELAY_144 +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCDelayConfig(uint32_t ui32Delay) +{ + uint32_t ui32Cfg; + + // Check the arguments. + ASSERT(ui32Delay <= AON_RTC_CONFIG_DELAY_144); + + + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg &= ~(AON_RTC_CTL_EV_DELAY_M); + ui32Cfg |= (ui32Delay << AON_RTC_CTL_EV_DELAY_S); + + HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg; +} + +//***************************************************************************** +// +//! \brief Configure the source of the combined event. +//! +//! A combined delayed event can be generated from a combination of the three +//! delayed events. Delayed events form the specified channels are OR'ed +//! together to generate the combined event. +//! +//! \param ui32Channels specifies the channels that are to be used for +//! generating the combined event. +//! The parameter must be the bitwise OR of any of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! - \ref AON_RTC_CH_NONE +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCCombinedEventConfig(uint32_t ui32Channels) +{ + uint32_t ui32Cfg; + + // Check the arguments. + ASSERT( (ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) || + (ui32Channels == AON_RTC_CH_NONE) ); + + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg &= ~(AON_RTC_CTL_COMB_EV_MASK_M); + ui32Cfg |= (ui32Channels << AON_RTC_CTL_COMB_EV_MASK_S); + + HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg; +} + +//***************************************************************************** +// +//! \brief Clear event from a specified channel. +//! +//! In case of an active event from the specified channel, the event +//! will be cleared (de-asserted). +//! +//! \param ui32Channel clears the event from one or more RTC channels: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCEventClear(uint32_t ui32Channel) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH0; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH1; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH2; + } +} + +//***************************************************************************** +// +//! \brief Get event status for a specified channel. +//! +//! In case of an active event from the specified channel, +//! this call will return \c true otherwise \c false. +//! +//! \param ui32Channel specifies the channel from which to query the event state. +//! The parameter must be one (and only one) of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return Returns \c true if an event has occurred for the given channel, +//! otherwise \c false. +// +//***************************************************************************** +__STATIC_INLINE bool +AONRTCEventGet(uint32_t ui32Channel) +{ + uint32_t uint32Event = 0; + + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH0_BITN); + } + + if(ui32Channel & AON_RTC_CH1) + { + uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH1_BITN); + } + + if(ui32Channel & AON_RTC_CH2) + { + uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH2_BITN); + } + + return(uint32Event); +} + +//***************************************************************************** +// +//! \brief Get integer part (seconds) of RTC free-running timer. +//! +//! Get the value in seconds of RTC free-running timer, i.e. the integer part. +//! The fractional part is returned from a call to AONRTCFractionGet(). +//! +//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead +//! of this function if the <16.16> format is sufficient. +//! +//! \note To read a consistent pair of integer and fractional parts, +//! \ref AONRTCSecGet() must be called first to trigger latching of the +//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts +//! must be disabled to ensure that these operations are performed atomically. +//! +//! \return Returns the integer part of RTC free running timer. +//! +//! \sa \ref AONRTCFractionGet() \ref AONRTCCurrentCompareValueGet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCSecGet(void) +{ + // The following read gets the seconds, but also latches the fractional + // part. + return(HWREG(AON_RTC_BASE + AON_RTC_O_SEC)); +} + +//***************************************************************************** +// +//! \brief Get fractional part (sub-seconds) of RTC free-running timer. +//! +//! Get the value of the fractional part of RTC free-running timer, i.e. the +//! sub-second part. +//! +//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead +//! of this function if the <16.16> format is sufficient. +//! +//! \note To read a consistent pair of integer and fractional parts, +//! \ref AONRTCSecGet() must be called first to trigger latching of the +//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts +//! must be disabled to ensure that these operations are performed atomically. +//! +//! \return Returns the fractional part of RTC free running timer. +//! +//! \sa \ref AONRTCSecGet() \ref AONRTCCurrentCompareValueGet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCFractionGet(void) +{ + // Note1: It is recommended to use AON RTCCurrentCompareValueGet() instead + // of this function if the <16.16> format is sufficient. + // Note2: AONRTCSecGet() must be called before this function to get a + // consistent reading. + // Note3: Interrupts must be disabled between the call to AONRTCSecGet() and this + // call since there are interrupt functions that reads AON_RTC_O_SEC + return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC)); +} + +//***************************************************************************** +// +//! \brief Get the sub second increment of the RTC. +//! +//! Get the value of the sub-second increment which is added to the RTC +//! absolute time on every clock tick. +//! +//! \note For a precise and temperature independent LF clock (e.g. an LF XTAL) +//! this value would stay the same across temperature. For temperatue +//! dependent clock sources like an RC oscillator, this value will change +//! over time if the application includes functionality for doing temperature +//! compensation of the RTC clock source. The default value corresponds to a +//! LF clock frequency of exactly 32.768 kHz. +//! +//! \return Returns the sub-second increment of the RTC added to the overall +//! value on every RTC clock tick. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCSubSecIncrGet(void) +{ + return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSECINC)); +} + +//***************************************************************************** +// +//! \brief Set operational mode of channel 1. +//! +//! Set the operational mode of channel 1. It can be capture or compare mode. +//! In capture mode, an external event causes the value of the free running +//! counter to be stored, to remember the time of the event. +//! +//! \note The default mode is compare. +//! +//! \param ui32Mode specifies the mode for channel 1. +//! The parameter must be one of the following: +//! - \ref AON_RTC_MODE_CH1_CAPTURE +//! - \ref AON_RTC_MODE_CH1_COMPARE +//! +//! \return None +//! +//! \sa AONRTCModeCh1Get() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCModeCh1Set(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == AON_RTC_MODE_CH1_CAPTURE) || + (ui32Mode == AON_RTC_MODE_CH1_COMPARE)); + + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN) = ui32Mode; +} + +//***************************************************************************** +// +//! \brief Get operational mode of channel 1. +//! +//! Get the operational mode of channel 1. It can be capture or compare mode. +//! In capture mode, an external event causes the value of the free running +//! counter to be stored, to remember the time of the event. +//! +//! \return Returns the operational mode of channel 1, one of: +//! - \ref AON_RTC_MODE_CH1_CAPTURE +//! - \ref AON_RTC_MODE_CH1_COMPARE +//! +//! \sa AONRTCModeCh1Set() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCModeCh1Get(void) +{ + return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN)); +} + +//***************************************************************************** +// +//! \brief Set operational mode of channel 2. +//! +//! Set the operational mode of channel 2. It can be in continuous compare +//! mode or normal compare mode. +//! In continuous mode, a value is automatically incremented to the channel 2 +//! compare register, upon a channel 2 compare event. This allows channel 2 to +//! generate a series of completely equidistant events. +//! The increment value is set by the AONRTCIncValueCh2Set() call. +//! +//! \note The default mode is normal compare. +//! +//! \param ui32Mode specifies the mode for channel 2. +//! The parameter must be one of the following: +//! - \ref AON_RTC_MODE_CH2_CONTINUOUS +//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE +//! +//! \return None +//! +//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCModeCh2Set(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) || + (ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE)); + + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN) = ui32Mode; +} + +//***************************************************************************** +// +//! \brief Get operational mode of channel 2. +//! +//! Get the operational mode of channel 2. It can be in continuous compare +//! mode or normal compare mode. +//! In continuous mode, a value is automatically incremented to the channel 2 +//! compare register, upon a channel 2 compare event. This allows channel 2 to +//! generate a series of completely equidistant events. +//! The increment value is set by the AONRTCIncValueCh2Set() call. +//! +//! \return Returns the operational mode of channel 2, i.e. one of: +//! - \ref AON_RTC_MODE_CH2_CONTINUOUS +//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE +//! +//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCModeCh2Get(void) +{ + return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN)); +} + +//***************************************************************************** +// +//! \brief Enable event operation for the specified channel. +//! +//! Enable the event generation for the specified channel. +//! +//! \note The RTC free running clock must also be enabled globally using the +//! AONRTCEnable() call. +//! +//! \param ui32Channel specifies one or more channels to enable: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return None +//! +//! \sa AONRTCEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCChannelEnable(uint32_t ui32Channel) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 1; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 1; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 1; + } +} + +//***************************************************************************** +// +//! \brief Disable event operation for the specified channel. +//! +//! Disable the event generation for the specified channel. +//! +//! \note The RTC free running clock can also be disabled globally using the +//! AONRTCDisable() call. +//! +//! \param ui32Channel specifies one or more channels to disable: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return None +//! +//! \sa AONRTCDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCChannelDisable(uint32_t ui32Channel) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 0; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 0; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 0; + } +} + +//***************************************************************************** +// +//! \brief Set the compare value for the given channel. +//! +//! Set compare value for the specified channel. +//! +//! The format of the compare value is a 16 bit integer and 16 bit fractional +//! format <16 sec.16 subsec>. The current value of the RTC counter +//! can be retrieved in a format compatible to the compare register using +//! \ref AONRTCCurrentCompareValueGet() +//! +//! \param ui32Channel specifies one or more channels to set compare value for: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! \param ui32CompValue is the compare value to set for the specified channel. +//! - Format: <16 sec.16 subsec> +//! +//! \return None +//! +//! \sa AONRTCCurrentCompareValueGet() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCCompareValueSet(uint32_t ui32Channel, uint32_t ui32CompValue) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP) = ui32CompValue; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP) = ui32CompValue; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP) = ui32CompValue; + } +} + +//***************************************************************************** +// +//! \brief Get the compare value for the given channel. +//! +//! Get compare value for the specified channel. +//! +//! \param ui32Channel specifies a channel. +//! The parameter must be one (and only one) of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return Returns the stored compare value for the given channel. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCCompareValueGet(uint32_t ui32Channel) +{ + uint32_t ui32Value = 0; + + // Check the arguments + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP); + } + + if(ui32Channel & AON_RTC_CH1) + { + ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP); + } + + if(ui32Channel & AON_RTC_CH2) + { + ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP); + } + + return(ui32Value); +} + +//***************************************************************************** +// +//! \brief Get the current value of the RTC counter in a format that matches +//! RTC compare values. +//! +//! The compare value registers contains 16 integer and 16 fractional bits. +//! This function will return the current value of the RTC counter in an +//! identical format. +//! +//! \note Reading SEC both before and after SUBSEC in order to detect if SEC +//! incremented while reading SUBSEC. If SEC incremented, we can't be sure +//! which SEC the SUBSEC belongs to, so repeating the sequence then. +//! +//! \return Returns the current value of the RTC counter in a <16.16> format +//! (SEC[15:0].SUBSEC[31:16]). +//! +//! \sa \ref AONRTCCompareValueSet() +// +//***************************************************************************** +extern uint32_t AONRTCCurrentCompareValueGet(void); + +//***************************************************************************** +// +//! \brief Get the current 64-bit value of the RTC counter. +//! +//! \note Reading SEC both before and after SUBSEC in order to detect if SEC +//! incremented while reading SUBSEC. If SEC incremented, we can't be sure +//! which SEC the SUBSEC belongs to, so repeating the sequence then. +//! +//! \return Returns the current value of the RTC counter in a 64-bits format +//! (SEC[31:0].SUBSEC[31:0]). +// +//***************************************************************************** +extern uint64_t AONRTCCurrent64BitValueGet(void); + +//***************************************************************************** +// +//! \brief Set the channel 2 increment value when operating in continuous mode. +//! +//! Set the channel 2 increment value when operating in continuous mode. +//! The specified value is automatically incremented to the channel 2 compare +//! register, upon a channel 2 compare event. This allows channel 2 to generate +//! a series of completely equidistant events. +//! +//! \param ui32IncValue is the increment value when operating in continuous mode. +//! +//! \return None +//! +//! \sa AONRTCIncValueCh2Get() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCIncValueCh2Set(uint32_t ui32IncValue) +{ + HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC) = ui32IncValue; +} + +//***************************************************************************** +// +//! \brief Get the channel2 increment value when operating in continuous mode. +//! +//! Get the channel 2 increment value, when channel 2 is operating in +//! continuous mode. +//! This value is automatically incremented to the channel 2 compare +//! register, upon a channel 2 compare event. This allows channel 2 to +//! generate a series of completely equidistant events. +//! +//! \return Returns the channel 2 increment value when operating in continuous +//! mode. +//! +//! \sa AONRTCIncValueCh2Set() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCIncValueCh2Get(void) +{ + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC)); +} + +//***************************************************************************** +// +//! \brief Get the channel 1 capture value. +//! +//! Get the channel 1 capture value. +//! The upper 16 bits of the returned value is the lower 16 bits of the +//! integer part of the RTC timer. The lower 16 bits of the returned part +//! is the upper 16 bits of the fractional part. +//! +//! \return Returns the channel 1 capture value. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCCaptureValueCh1Get(void) +{ + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH1CAPT)); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONRTCCurrentCompareValueGet + #undef AONRTCCurrentCompareValueGet + #define AONRTCCurrentCompareValueGet ROM_AONRTCCurrentCompareValueGet + #endif + #ifdef ROM_AONRTCCurrent64BitValueGet + #undef AONRTCCurrent64BitValueGet + #define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_RTC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc_doc.h new file mode 100644 index 0000000..b3c142b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc_doc.h @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: aon_rtc_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonrtc_api +//! @{ +//! \section sec_aonrtc Introduction +//! +//! \note If using TI-RTOS then only TI-RTOS is allowed to configure the RTC timer! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_wuc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_wuc.c new file mode 100644 index 0000000..290945e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_wuc.c @@ -0,0 +1,224 @@ +/****************************************************************************** +* Filename: aon_wuc.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the AON Wake-Up Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_wuc.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONWUCAuxReset + #define AONWUCAuxReset NOROM_AONWUCAuxReset + #undef AONWUCRechargeCtrlConfigSet + #define AONWUCRechargeCtrlConfigSet NOROM_AONWUCRechargeCtrlConfigSet + #undef AONWUCOscConfig + #define AONWUCOscConfig NOROM_AONWUCOscConfig +#endif + + +//***************************************************************************** +// +//! Reset the AUX domain +// +//***************************************************************************** +void +AONWUCAuxReset(void) +{ + // Reset the AUX domain. +// HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) |= AON_WUC_AUXCTL_RESET_REQ; // ROM version + HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_RESET_REQ_BITN) = 1; + + // Wait for AON interface to be in sync. + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); + + // De-assert reset on the AUX domain. +// HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) &= ~AON_WUC_AUXCTL_RESET_REQ; // ROM version + HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_RESET_REQ_BITN) = 0; + + // Wait for AON interface to be in sync. + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! Configure the recharge controller +// +//***************************************************************************** +void +AONWUCRechargeCtrlConfigSet(bool bAdaptEnable, uint32_t ui32AdaptRate, + uint32_t ui32Period, uint32_t ui32MaxPeriod) +{ + uint32_t ui32Shift; + uint32_t ui32C1; + uint32_t ui32C2; + uint32_t ui32Reg; + uint32_t ui32Exponent; + uint32_t ui32MaxExponent; + uint32_t ui32Mantissa; + uint32_t ui32MaxMantissa; + + // Check the arguments. + ASSERT((ui32AdaptRate >= RC_RATE_MIN) || + (ui32AdaptRate <= RC_RATE_MAX)); + + ui32C1 = 0; + ui32C2 = 0; + ui32Shift = 9; + + // Clear the previous values. + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG); + ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M | + AON_WUC_RECHARGECFG_ADAPTIVE_EN_M | AON_WUC_RECHARGECFG_PER_M_M | + AON_WUC_RECHARGECFG_PER_E_M | AON_WUC_RECHARGECFG_C1_M | + AON_WUC_RECHARGECFG_C2_M); + + // Check if the recharge controller adaptation algorithm should be active. + if(bAdaptEnable) + { + // Calculate adaptation parameters. + while(ui32AdaptRate) + { + if(ui32AdaptRate & (1 << ui32Shift)) + { + if(!ui32C1) + { + ui32C1 = ui32Shift; + } + else if(!ui32C2) + { + if((2 * ui32AdaptRate) > ((uint32_t)(3 << ui32Shift))) + { + ui32C2 = ui32Shift + 1; + } + else + { + ui32C2 = ui32Shift; + } + } + else + { + break; + } + ui32AdaptRate &= ~(1 << ui32Shift); + } + ui32Shift--; + } + if(!ui32C2) + { + ui32C2 = ui32C1 = ui32C1 - 1; + } + + ui32C1 = 10 - ui32C1; + ui32C2 = 10 - ui32C2; + + // Update the recharge rate parameters. + ui32Reg &= ~(AON_WUC_RECHARGECFG_C1_M | AON_WUC_RECHARGECFG_C2_M); + ui32Reg |= (ui32C1 << AON_WUC_RECHARGECFG_C1_S) | + (ui32C2 << AON_WUC_RECHARGECFG_C2_S) | + AON_WUC_RECHARGECFG_ADAPTIVE_EN_M; + } + + // Resolve the period into an exponent and mantissa. + ui32Period = (ui32Period >> 4); + ui32Exponent = 0; + while(ui32Period > (AON_WUC_RECHARGECFG_PER_M_M >> AON_WUC_RECHARGECFG_PER_M_S)) + { + ui32Period >>= 1; + ui32Exponent++; + } + ui32Mantissa = ui32Period; + + // Resolve the max period into an exponent and mantissa. + ui32MaxPeriod = (ui32MaxPeriod >> 4); + ui32MaxExponent = 0; + while(ui32MaxPeriod > (AON_WUC_RECHARGECFG_MAX_PER_M_M >> AON_WUC_RECHARGECFG_MAX_PER_M_S)) + { + ui32MaxPeriod >>= 1; + ui32MaxExponent++; + } + ui32MaxMantissa = ui32MaxPeriod; + + // Configure the controller. + ui32Reg |= ((ui32MaxMantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) | + (ui32MaxExponent << AON_WUC_RECHARGECFG_MAX_PER_E_S) | + (ui32Mantissa << AON_WUC_RECHARGECFG_PER_M_S) | + (ui32Exponent << AON_WUC_RECHARGECFG_PER_E_S)); + HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg; + +} + +//***************************************************************************** +// +//! Configure the interval for oscillator amplitude calibration +// +//***************************************************************************** +void +AONWUCOscConfig(uint32_t ui32Period) +{ + uint32_t ui32Mantissa; + uint32_t ui32Exponent; + uint32_t ui32Reg; + + // Resolve the period into a exponent and mantissa. + ui32Period = (ui32Period >> 4); + ui32Exponent = 0; + while(ui32Period > (AON_WUC_OSCCFG_PER_M_M >> AON_WUC_OSCCFG_PER_M_S)) + { + ui32Period >>= 1; + ui32Exponent++; + } + ui32Mantissa = ui32Period; + + // Update the period for the oscillator amplitude calibration. + HWREG(AON_WUC_BASE + AON_WUC_O_OSCCFG) = + (ui32Mantissa << AON_WUC_OSCCFG_PER_M_S) | + (ui32Exponent << AON_WUC_OSCCFG_PER_E_S); + + // Set the maximum recharge period equal to the oscillator amplitude + // calibration period. + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG); + ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M); + ui32Reg |= ((ui32Mantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) | + (ui32Exponent << AON_WUC_RECHARGECFG_MAX_PER_E_S)); + + // Write the configuration. + HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_wuc.h new file mode 100644 index 0000000..bb8dd13 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_wuc.h @@ -0,0 +1,838 @@ +/****************************************************************************** +* Filename: aon_wuc.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Defines and prototypes for the AON Wake-Up Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonwuc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_WUC_H__ +#define __AON_WUC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_aon_rtc.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONWUCAuxReset NOROM_AONWUCAuxReset + #define AONWUCRechargeCtrlConfigSet NOROM_AONWUCRechargeCtrlConfigSet + #define AONWUCOscConfig NOROM_AONWUCOscConfig +#endif + +//***************************************************************************** +// +// Defines the possible clock source for the MCU and AUX domain. +// +//***************************************************************************** +#define AONWUC_CLOCK_SRC_HF 0x00000003 // System clock high frequency - + // 48 MHz. +#define AONWUC_CLOCK_SRC_LF 0x00000001 // System clock low frequency - + // 32 kHz. +#define AONWUC_NO_CLOCK 0x00000000 // System clock low frequency - + // 32 kHz. + +//***************************************************************************** +// +// Defines the possible clock division factors for the AUX domain. +// +//***************************************************************************** +#define AUX_CLOCK_DIV_2 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 ) +#define AUX_CLOCK_DIV_4 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 ) +#define AUX_CLOCK_DIV_8 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 ) +#define AUX_CLOCK_DIV_16 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 ) +#define AUX_CLOCK_DIV_32 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 ) +#define AUX_CLOCK_DIV_64 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 ) +#define AUX_CLOCK_DIV_128 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 ) +#define AUX_CLOCK_DIV_256 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 ) +#define AUX_CLOCK_DIV_UNUSED ( AON_WUC_AUXCLK_SCLK_HF_DIV_M + ( 1 << AON_WUC_AUXCLK_SCLK_HF_DIV_S )) +#define AUX_CLOCK_DIV_M ( AON_WUC_AUXCLK_SCLK_HF_DIV_M ) + +//***************************************************************************** +// +// Defines used for configuring the power-off and wake up procedure. +// +//***************************************************************************** +#define MCU_VIRT_PWOFF_DISABLE 0x00000000 +#define MCU_VIRT_PWOFF_ENABLE 0x00020000 +#define MCU_IMM_WAKE_UP 0x00000000 +#define MCU_FIXED_WAKE_UP 0x00010000 +#define AUX_VIRT_PWOFF_DISABLE 0x00000000 +#define AUX_VIRT_PWOFF_ENABLE 0x00020000 +#define AUX_IMM_WAKE_UP 0x00000000 +#define AUX_FIXED_WAKE_UP 0x00010000 + +//***************************************************************************** +// +// Defines that can be be used to enable/disable the entire SRAM and the +// retention on the SRAM in both the MCU and the AUX domain. +// +//***************************************************************************** +#define MCU_RAM0_RETENTION 0x00000001 +#define MCU_RAM1_RETENTION 0x00000002 +#define MCU_RAM2_RETENTION 0x00000004 +#define MCU_RAM3_RETENTION 0x00000008 +#define MCU_RAM_BLOCK_RETENTION 0x0000000F +#define MCU_AUX_RET_ENABLE 0x00000001 + +//***************************************************************************** +// +// Defines for different wake up modes for AUX domain which can be set using +// AONWUCAuxWakeUpEvent() . +// +//***************************************************************************** +#define AONWUC_AUX_WAKEUP 0x00000001 +#define AONWUC_AUX_ALLOW_SLEEP 0x00000000 + +//***************************************************************************** +// +// Defines for all the different power modes available through +// AONWUCPowerStatusGet() . +// +//***************************************************************************** +#define AONWUC_OSC_GBIAS_REQ 0x00400000 // OSC is requesting GBias +#define AONWUC_AUX_GBIAS_REQ 0x00200000 // AUX is requesting GBias +#define AONWUC_MCU_GBIAS_REQ 0x00100000 // MCU is requesting GBias +#define AONWUC_OSC_BGAP_REQ 0x00040000 // OSC is requesting BGap +#define AONWUC_AUX_BGAP_REQ 0x00020000 // AUX is requesting BGap +#define AONWUC_MCU_BGAP_REQ 0x00010000 // MCU is requesting BGap +#define AONWUC_GBIAS_ON 0x00002000 // Global Bias is on +#define AONWUC_BGAP_ON 0x00001000 // Band Gap is on +#define AONWUC_AUX_POWER_DOWN 0x00000200 // AUX is in powerdown mode +#define AONWUC_MCU_POWER_DOWN 0x00000100 // MCU is in powerdown mode +#define AONWUC_JTAG_POWER_ON 0x00000040 // JTAG is powered on +#define AONWUC_AUX_POWER_ON 0x00000020 // AUX is powered on +#define AONWUC_MCU_POWER_ON 0x00000010 // MCU is powered on +#define AONWUC_SPLY_POWER_DOWN 0x00000001 // Power supply is in power down + + +//***************************************************************************** +// +// RAM repair status bits. Values are returned by AOXWUCRamRepairStatusGet() . +// +//***************************************************************************** +#define MCU_RAMREPAIR_DONE 0x00000001 +#define AUX_RAMREPAIR_DONE 0x00000002 + +//***************************************************************************** + +//***************************************************************************** +#define RC_RATE_MAX 768 // Maximum recharge rate for the + // recharge controller. +#define RC_RATE_MIN 2 // Minimum recharge rate for the + // recharge controller. + +//***************************************************************************** +#define AONWUC_MCU_RESET_SRC 0x00000002 // MCU reset source can be SW or + // JTAG +#define AONWUC_MCU_WARM_RESET 0x00000001 // MCU reset type and can be warm + // or not warm. + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure the power down clock for the MCU domain. +//! +//! Use this function to control which one of the clock sources that +//! is fed into the MCU domain when the system is in standby mode. When the +//! power is back in Active mode the clock source will automatically switch to +//! \ref AONWUC_CLOCK_SRC_HF. +//! +//! Each clock is fed 'as is' into the MCU domain, since the MCU domain +//! contains internal clock dividers controllable through the PRCM. +//! +//! \param ui32ClkSrc is the clock source for the MCU domain when in power +//! down. Values available as clock source: +//! - \ref AONWUC_NO_CLOCK +//! - \ref AONWUC_CLOCK_SRC_LF +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCMcuPowerDownConfig(uint32_t ui32ClkSrc) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT((ui32ClkSrc == AONWUC_NO_CLOCK) || + (ui32ClkSrc == AONWUC_CLOCK_SRC_LF)); + + // Set the clock source for the MCU domain when in power down. + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_MCUCLK); + ui32Reg &= ~AON_WUC_MCUCLK_PWR_DWN_SRC_M; + HWREG(AON_WUC_BASE + AON_WUC_O_MCUCLK) = ui32Reg | + (ui32ClkSrc << + AON_WUC_MCUCLK_PWR_DWN_SRC_S); +} + +//***************************************************************************** +// +//! \brief Configure the power down mode for the MCU domain. +//! +//! The parameter \c ui32Mode determines the power down mode of the MCU Voltage +//! Domain. When the AON WUC receives a request to power off the MCU domain it +//! can choose to power off completely or use a virtual power-off. In a virtual +//! power-off, reset is asserted and the clock is stopped but the power to the +//! domain is kept on. +//! +//! \param ui32Mode defines the power down mode of the MCU domain. +//! Allowed values for setting the virtual power-off are: +//! - \ref MCU_VIRT_PWOFF_DISABLE +//! - \ref MCU_VIRT_PWOFF_ENABLE +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCMcuPowerOffConfig(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == MCU_VIRT_PWOFF_ENABLE) || + (ui32Mode == MCU_VIRT_PWOFF_DISABLE)); + + // Set the powerdown mode. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_MCUCFG, AON_WUC_MCUCFG_VIRT_OFF_BITN) = (ui32Mode != 0); +} + +//***************************************************************************** +// +//! \brief Configure the wake-up procedure for the MCU domain. +//! +//! The MCU domain can wake up using two different procedures. Either it wakes +//! up immediately following the triggering event or wake-up is forced to +//! happen a fixed number of 32 KHz clocks following the triggering +//! event. The last can be used to compensate for any variable delays caused +//! by other activities going on at the time of wakeup (such as a recharge +//! event, etc.). +//! +//! \param ui32WakeUp determines the timing of the MCU wake up procedure. +//! - \ref MCU_IMM_WAKE_UP +//! - \ref MCU_FIXED_WAKE_UP +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCMcuWakeUpConfig(uint32_t ui32WakeUp) +{ + // Check the arguments. + ASSERT((ui32WakeUp == MCU_IMM_WAKE_UP) || + (ui32WakeUp == MCU_FIXED_WAKE_UP)); + + // Configure the wake up procedure. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_MCUCFG, AON_WUC_MCUCFG_FIXED_WU_EN_BITN) = (ui32WakeUp != 0); +} + +//***************************************************************************** +// +//! \brief Configure the retention on the block RAM in the MCU domain. +//! +//! MCU SRAM is partitioned into 4 banks of 1k x 32 each. The SRAM supports +//! retention on all 4 blocks. The retention on the SRAM can be turned on and +//! off. Use this function to enable the retention on the individual blocks. +//! +//! If a block is not represented in the parameter \c ui32Retention then the +//! the retention will be disabled for that block. +//! +//! \note Retention on the SRAM is not enabled by default. If retention is +//! turned off on all RAM blocks then the SRAM is powered off when it would +//! otherwise be put in retention mode. +//! +//! \param ui32Retention defines which RAM blocks to enable/disable retention on. +//! To enable retention on individual parts of the RAM use a bitwise OR'ed +//! combination of: +//! - \ref MCU_RAM0_RETENTION +//! - \ref MCU_RAM1_RETENTION +//! - \ref MCU_RAM2_RETENTION +//! - \ref MCU_RAM3_RETENTION +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCMcuSRamConfig(uint32_t ui32Retention) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32Retention & MCU_RAM_BLOCK_RETENTION); + ASSERT(!(ui32Retention & ~MCU_RAM_BLOCK_RETENTION)); + + // Configure the retention. + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_MCUCFG) & ~MCU_RAM_BLOCK_RETENTION; + ui32Reg |= ui32Retention; + HWREG(AON_WUC_BASE + AON_WUC_O_MCUCFG) = ui32Reg; +} + + +//***************************************************************************** +// +//! \brief Return the clock configuration for the AUX domain. +//! +//! The AUX domain does not have a local clock divider, so the AON WUC contains +//! a dedicated clock divider for AUX domain. Use this function to +//! get the setting of the clock divider. +//! +//! \return Return the clock configuration. Enumerated return values are: +//! - \ref AUX_CLOCK_DIV_2 +//! - \ref AUX_CLOCK_DIV_4 +//! - \ref AUX_CLOCK_DIV_8 +//! - \ref AUX_CLOCK_DIV_16 +//! - \ref AUX_CLOCK_DIV_32 +//! - \ref AUX_CLOCK_DIV_64 +//! - \ref AUX_CLOCK_DIV_128 +//! - \ref AUX_CLOCK_DIV_256 +//! +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONWUCAuxClockConfigGet(void) +{ + // Return the clock divider value. + return ((HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) & + AON_WUC_AUXCLK_SCLK_HF_DIV_M) >> + AON_WUC_AUXCLK_SCLK_HF_DIV_S); +} + +//***************************************************************************** +// +//! \brief Configure the power down mode for the AUX domain. +//! +//! Use this function to control which one of the clock sources that +//! is fed into the MCU domain when it is in Power Down mode. When the Power +//! is back in active mode the clock source will automatically switch to +//! \ref AONWUC_CLOCK_SRC_HF. +//! +//! Each clock is fed 'as is' into the AUX domain, since the AUX domain +//! contains internal clock dividers controllable through the PRCM. +//! +//! \param ui32ClkSrc is the clock source for the AUX domain when in power down. +//! - \ref AONWUC_NO_CLOCK +//! - \ref AONWUC_CLOCK_SRC_LF +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCAuxPowerDownConfig(uint32_t ui32ClkSrc) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT((ui32ClkSrc == AONWUC_NO_CLOCK) || + (ui32ClkSrc == AONWUC_CLOCK_SRC_LF)); + + // Set the clock source for the AUX domain when in power down. + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK); + ui32Reg &= ~AON_WUC_AUXCLK_PWR_DWN_SRC_M; + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg | + (ui32ClkSrc << + AON_WUC_AUXCLK_PWR_DWN_SRC_S); +} + + +//***************************************************************************** +// +//! \brief Configure the retention on the AUX SRAM. +//! +//! The AUX SRAM contains only one block which supports retention. The retention +//! on the SRAM can be turned on and off. Use this function to enable/disable +//! the retention on the entire RAM. +//! +//! \param ui32Retention either enables or disables AUX SRAM retention. +//! - 0 : Disable retention. +//! - 1 : Enable retention. +//! +//! \note Retention on the SRAM is not enabled by default. If retention is +//! turned off then the SRAM is powered off when it would otherwise be put in +//! retention mode. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCAuxSRamConfig(uint32_t ui32Retention) +{ + // Enable/disable the retention. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCFG, AON_WUC_AUXCFG_RAM_RET_EN_BITN) = ui32Retention; +} + +//***************************************************************************** +// +//! \brief Control the wake up procedure of the AUX domain. +//! +//! The AUX domain can be woken in two different modes. In both modes power +//! is turned on. In one mode a software event is generated for the +//! Sensor Controller and it is allowed to start processing. The second mode will +//! just force power on the Sensor Controller. If System CPU requires exclusive access +//! to the AUX domain resources, it is advised to ensure that the image in +//! the Sensor Controller memory is declared invalid. This can be achieved by +//! calling AONWUCAuxImageInvalid(). +//! +//! \note Any writes to the AON interface must pass a 32 kHz clock boundary, +//! and is therefore relatively slow. To ensure that a given write is +//! complete the value of the register can be read back after write. +// +//! \note When accessing the AUX domain from the System CPU, it is advised always to +//! have set the AUX in at least \ref AONWUC_AUX_WAKEUP. This overwrites any +//! instruction from the Sensor Controller and ensures that the AUX domain +//! is on so it won't leave the System CPU hanging. +//! +//! \param ui32Mode is the wake up mode for the AUX domain. +//! - \ref AONWUC_AUX_WAKEUP +//! - \ref AONWUC_AUX_ALLOW_SLEEP +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCAuxWakeupEvent(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == AONWUC_AUX_WAKEUP) || + (ui32Mode == AONWUC_AUX_ALLOW_SLEEP)); + + // Wake up the AUX domain. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_AUX_FORCE_ON_BITN) = ui32Mode; +} + +//***************************************************************************** +// +//! \brief Reset the AUX domain. +//! +//! Use this function to reset the entire AUX domain. The write to the AON_WUC +//! module must pass an 32 kHz clock boundary. By reading the +//! AON_RTC_O_SYNC register after each write, it is guaranteed that the AON +//! interface will be in sync and that both the assert and the de-assert of the +//! reset signal to AUX will propagate. +//! +//! \note This requires two writes and two reads on a 32 kHz clock boundary. +//! +//! \return None +// +//***************************************************************************** +extern void AONWUCAuxReset(void); + +//***************************************************************************** +// +//! \brief Tells the Sensor Controller that the image in memory is valid. +//! +//! Use this function to tell the sensor controller that the image in memory is +//! valid, and it is allowed to start executing the program. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCAuxImageValid(void) +{ + // Tell the Sensor Controller that the image in memory is valid. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_SCE_RUN_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Tells the Sensor Controller that the image in memory is invalid. +//! +//! Use this function to tell the sensor controller that the image in memory is +//! invalid. Sensor Controller might wake up, but it will stay idle. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCAuxImageInvalid(void) +{ + // Tell the Sensor Controller that the image in memory is invalid. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_SCE_RUN_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Get the power status of the device. +//! +//! The Always On (AON) domain is the only part of the device which is truly +//! "ALWAYS ON". The power status for the other device can always be read from +//! this status register. +//! +//! Possible power modes for the different parts of the device are: +//! +//! \return Returns the current power status of the device as a bitwise OR'ed +//! combination of these values: +//! - \ref AONWUC_AUX_POWER_DOWN +//! - \ref AONWUC_AUX_POWER_ON +//! - \ref AONWUC_JTAG_POWER_ON +//! - \ref AONWUC_MCU_POWER_ON +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONWUCPowerStatusGet(void) +{ + // Return the power status. + return (HWREG(AON_WUC_BASE + AON_WUC_O_PWRSTAT)); +} + +//***************************************************************************** +// +//! \brief Enable shut-down of the device. +//! +//! Use this function to enable shut-down of the device. This will force all I/O values to +//! be latched - possibly enabling I/O wakeup - then all internal power +//! supplies are turned off, effectively putting the device into shut-down mode. +//! +//! \note No action will take place before the System CPU is put to deep sleep. +//! +//! \note The shut-down command is ignored if the JTAG interface has been +//! activated. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCShutDownEnable(void) +{ + // Ensure the JTAG domain is turned off; + // otherwise MCU domain can't be turned off. + HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0; + + // Enable shutdown of the device. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_CTL0, AON_WUC_CTL0_PWR_DWN_DIS_BITN) = 0; + HWREG(AON_WUC_BASE + AON_WUC_O_SHUTDOWN) = AON_WUC_SHUTDOWN_EN; +} + +//***************************************************************************** +// +//! \brief Enable power down mode on AUX and MCU domain. +//! +//! Use this function to enable powerdown on the AUX and MCU domain. +//! +//! \note The powerdown command is ignored if the JTAG interface has been +//! activated. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCDomainPowerDownEnable(void) +{ + // Ensure the JTAG domain is turned off; + // otherwise MCU domain can't be turned off. + HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0; + + // Enable power down mode. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_CTL0, AON_WUC_CTL0_PWR_DWN_DIS_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Use this function to disable power down mode of the MCU and AUX domain. +//! +//! Disabling powerdown on the MCU and/or AUX will put the domains in a +//! virtual power down when requesting to be powered down. Logic is the same +//! but power is kept on. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCDomainPowerDownDisable(void) +{ + // Disable power down mode. + HWREGBITW(AON_WUC_BASE + AON_WUC_O_CTL0, AON_WUC_CTL0_PWR_DWN_DIS_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Use this function to clear specific status bits. +//! +//! Use this function to clear the bits that are set in the AON WUC status +//! register. This register requires a write 1 to clear. +//! +//! AON Wake Up Controller TAP can request a total/full Flash erase. If so, +//! the corresponding status bits will be set in the status register and can +//! be read using \ref AONWUCMcuResetStatusGet() or cleared using this function. The reset +//! source and type give information about what and how the latest reset +//! was performed. Access to these bits are identical to the flash erase +//! bits. +//! +//! \param ui32Status defines in a one-hot encoding which bits to clear in the +//! status register. Use OR'ed combinations of the following: +//! - \ref AONWUC_MCU_RESET_SRC +//! - \ref AONWUC_MCU_WARM_RESET +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCMcuResetClear(uint32_t ui32Status) +{ + // Check the arguments. + ASSERT((ui32Status & AONWUC_MCU_RESET_SRC) || + (ui32Status & AONWUC_MCU_WARM_RESET)); + + // Clear the status bits. + HWREG(AON_WUC_BASE + AON_WUC_O_CTL1) = ui32Status; +} + +//***************************************************************************** +// +//! \brief Return the reset status. +//! +//! This function returns the value of the AON_WUC_O_CTL1 register. +//! +//! \return Returns the status from the AON WUC. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONWUCMcuResetStatusGet(void) +{ + // Return the current status. + return (HWREG(AON_WUC_BASE + AON_WUC_O_CTL1)); +} + +//***************************************************************************** +// +//! \brief Configure the recharge controller. +//! +//! The parameter \c bAdaptEnable is used to enable or disable the adaptive +//! algorithm for the recharge controller. +//! The adaptive algorithm for the recharge controller is defined as +//! +/*! +\verbatim + + New_Period = Period * (1 + (AdaptRate / 1024) ) + + AdaptRate + ----------- = ( 2^(-C1) + 2^(-C2) ) + 1024 + +\endverbatim +*/ +//! +//! Where C1 is between 1 and 10 and C2 is between 2 and 10. The \c ui32AdaptRate +//! must be a number between 2 and 768 (\ref RC_RATE_MIN and \ref RC_RATE_MAX) +//! resulting in an adaptive rate between 0.2% and 75%. +//! +//! The \c ui32Period is the number of 32 KHz clocks between two recharges. The +//! length of the interval is defined by the formula: +//! +/*! +\verbatim + + Period = ({ulMantissa,5'b1111} << ui32Exponent) + +\endverbatim +*/ +//! +//! \note The maximum number of recharge cycles is required when enabling the +//! adaptive recharge algorithm. +//! +//! \note The maximum period between two recharges should never exceed the +//! period between two oscillator amplitude calibrations which is configured +//! using AONWUCOscConfig(). +//! +//! \param bAdaptEnable enables the adaptation algorithm for the controller. +//! \param ui32AdaptRate determines the adjustment value for the adoption +//! algorithm. +//! \param ui32Period determines the number of clock cycles between each +//! activation of the recharge controller. +//! \param ui32MaxPeriod determines the maximum number of clock cycles between +//! each activation of the recharge controller. +//! +//! \return None +// +//***************************************************************************** +extern void AONWUCRechargeCtrlConfigSet(bool bAdaptEnable, + uint32_t ui32AdaptRate, + uint32_t ui32Period, + uint32_t ui32MaxPeriod); + +//***************************************************************************** +// +//! \brief Get the current configuration of the recharge controller. +//! +//! This function returns the value of the register AON_WUC_O_RECHARGECFG. +//! +//! \return Returns the current configuration of the recharge controller. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONWUCRechargeCtrlConfigGet(void) +{ + // Return the current configuration. + return(HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG)); +} + +//***************************************************************************** +// +//! \brief Configure the interval for oscillator amplitude calibration. +//! +//! Use this function to set the number of 32 kHz clocks between oscillator +//! amplitude calibrations. +//! +//! The value of the interval is defined by the formula: +//! +/*! +\verbatim + + Period = ({ulMantissa,5'b1111} << ui32Exponent) + +\endverbatim +*/ +//! +//! \note When this counter expires an oscillator amplitude calibration is +//! triggered immediately in Active mode. When this counter expires in +//! Powerdown mode an internal flag is set that causes GBIAS to turn on +//! together with BGAP when the next recharge occurs, at the same time +//! triggering the oscillator amplitude calibration as well as a recharge of +//! the uLDO reference voltage. +//! +//! \note The oscillator amplitude calibration is performed at the same time +//! as the recharge for the uLDO reference voltage. So the maximum period +//! between each recharge operation should not exceed the number of clock +//! cycles for the amplitude calibration. +//! +//! \param ui32Period is the number of 32 kHz clock cycles in each interval. +//! +//! \return None +// +//***************************************************************************** +extern void AONWUCOscConfig(uint32_t ui32Period); + +//***************************************************************************** +// +//! \brief Request power off of the JTAG domain. +//! +//! The JTAG domain is automatically powered up on if a debugger is connected. +//! If a debugger is not connected this function can be used to power off the +//! JTAG domain. +//! +//! \note Achieving the lowest power modes (shutdown/powerdown) requires the +//! JTAG domain to be turned off. In general the JTAG domain should never be +//! powered in production code. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONWUCJtagPowerOff(void) +{ + // Request the power off of the Jtag domain + HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0; +} + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONWUCAuxReset + #undef AONWUCAuxReset + #define AONWUCAuxReset ROM_AONWUCAuxReset + #endif + #ifdef ROM_AONWUCRechargeCtrlConfigSet + #undef AONWUCRechargeCtrlConfigSet + #define AONWUCRechargeCtrlConfigSet ROM_AONWUCRechargeCtrlConfigSet + #endif + #ifdef ROM_AONWUCOscConfig + #undef AONWUCOscConfig + #define AONWUCOscConfig ROM_AONWUCOscConfig + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_WUC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_adc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_adc.c new file mode 100644 index 0000000..1a2d51f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_adc.c @@ -0,0 +1,337 @@ +/****************************************************************************** +* Filename: aux_adc.c +* Revised: 2017-11-20 14:31:35 +0100 (Mon, 20 Nov 2017) +* Revision: 50315 +* +* Description: Driver for the AUX Time to Digital Converter interface. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_adc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aux_wuc.h" +#include "../inc/hw_fcfg1.h" +#include "adi.h" +#include "event.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXADCDisable + #define AUXADCDisable NOROM_AUXADCDisable + #undef AUXADCEnableAsync + #define AUXADCEnableAsync NOROM_AUXADCEnableAsync + #undef AUXADCEnableSync + #define AUXADCEnableSync NOROM_AUXADCEnableSync + #undef AUXADCDisableInputScaling + #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling + #undef AUXADCFlushFifo + #define AUXADCFlushFifo NOROM_AUXADCFlushFifo + #undef AUXADCReadFifo + #define AUXADCReadFifo NOROM_AUXADCReadFifo + #undef AUXADCPopFifo + #define AUXADCPopFifo NOROM_AUXADCPopFifo + #undef AUXADCGetAdjustmentGain + #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain + #undef AUXADCGetAdjustmentOffset + #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset + #undef AUXADCValueToMicrovolts + #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts + #undef AUXADCMicrovoltsToValue + #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue + #undef AUXADCAdjustValueForGainAndOffset + #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset + #undef AUXADCUnadjustValueForGainAndOffset + #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset +#endif + +//***************************************************************************** +// +// Disables the ADC +// +//***************************************************************************** +void +AUXADCDisable(void) +{ + // Disable the ADC reference + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, ADI_4_AUX_ADCREF0_EN_M | ADI_4_AUX_ADCREF0_REF_ON_IDLE_M | ADI_4_AUX_ADCREF0_SRC_M); + + // Assert reset and disable the ADC + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M | ADI_4_AUX_ADC0_SMPL_MODE_M | ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M); + + // Ensure that scaling is enabled by default before next use of the ADC + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); + + // Flush the FIFO before disabling the clocks + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) + + // Disable the ADC clock (no need to wait since IOB_WUC_ADCCLKCTL_ACK goes low immediately) + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = 0; + + // Disable the ADC data interface + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = 0; +} + +//***************************************************************************** +// +// Enables the ADC for asynchronous operation +// +//***************************************************************************** +void +AUXADCEnableAsync(uint32_t refSource, uint32_t trigger) +{ + // Enable the ADC reference, with the following options: + // - SRC: Set when using relative reference + // - REF_ON_IDLE: Always cleared since there is no idle state in asynchronous operation + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, refSource | ADI_4_AUX_ADCREF0_EN_M); + + // Enable the ADC clock + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = AUX_WUC_ADCCLKCTL_REQ_M; + while (!(HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) & AUX_WUC_ADCCLKCTL_ACK_M)); + + // Enable the ADC data interface + if (trigger == AUXADC_TRIGGER_MANUAL) { + // Manual trigger: No need to configure event routing from GPT + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 | AUX_ANAIF_ADCCTL_CMD_EN; + } else { + // GPT trigger: Configure event routing via MCU_EV to the AUX domain + HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; + } + + // Configure the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_SMPL_MODE_M); + + // Release reset and enable the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); +} + +//***************************************************************************** +// +// Enables the ADC for synchronous operation +// +//***************************************************************************** +void +AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger) +{ + // Enable the ADC reference, with the following options: + // - SRC: Set when using relative reference + // - REF_ON_IDLE: Set when using fixed reference and sample time < 21.3 us + uint8_t adcref0 = refSource | ADI_4_AUX_ADCREF0_EN_M; + if (!refSource && (sampleTime < AUXADC_SAMPLE_TIME_21P3_US)) { + adcref0 |= ADI_4_AUX_ADCREF0_REF_ON_IDLE_M; + } + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, adcref0); + + // Enable the ADC clock + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = AUX_WUC_ADCCLKCTL_REQ_M; + while (!(HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) & AUX_WUC_ADCCLKCTL_ACK_M)); + + // Enable the ADC data interface + if (trigger == AUXADC_TRIGGER_MANUAL) { + // Manual trigger: No need to configure event routing from GPT + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 | AUX_ANAIF_ADCCTL_CMD_EN; + } else { + // GPT trigger: Configure event routing via MCU_EV to the AUX domain + HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; + } + + // Configure the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, sampleTime << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S); + + // Release reset and enable the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); +} + +//***************************************************************************** +// +// Disables scaling of the ADC input +// +//***************************************************************************** +void +AUXADCDisableInputScaling(void) +{ + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); +} + +//***************************************************************************** +// +// Flushes the ADC FIFO +// +//***************************************************************************** +void +AUXADCFlushFifo(void) +{ + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) +} + +//***************************************************************************** +// +// Waits for and returns the first sample in the ADC FIFO +// +//***************************************************************************** +uint32_t +AUXADCReadFifo(void) { + + // Wait until there is at least one sample in the FIFO + while (HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT) & AUX_ANAIF_ADCFIFOSTAT_EMPTY_M); + + // Return the first sample from the FIFO + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +//***************************************************************************** +// +// Returns the first sample in the ADC FIFO, without waiting +// +//***************************************************************************** +uint32_t +AUXADCPopFifo(void) { + + // Return the first sample from the FIFO. If the FIFO is empty, this + // generates ADC FIFO underflow + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +//***************************************************************************** +// +// Returns the gain value used when adjusting for ADC gain/offset +// +//***************************************************************************** +int32_t +AUXADCGetAdjustmentGain(uint32_t refSource) +{ + int32_t gain; + if (refSource == AUXADC_REF_FIXED) { + // AUXADC_REF_FIXED ==> ABS_GAIN + gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_ABS_GAIN) & FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S; + } else { + // AUXADC_REF_VDDS_REL ==> REL_GAIN + gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_REL_GAIN) & FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S; + } + return gain; +} + +//***************************************************************************** +// +// Returns the offset value used when adjusting for ADC gain/offset +// +//***************************************************************************** +int32_t +AUXADCGetAdjustmentOffset(uint32_t refSource) +{ + int8_t offset; + if ( refSource == AUXADC_REF_FIXED ) { + // AUXADC_REF_FIXED ==> ABS_OFFSET + offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S; + } else { + // AUXADC_REF_VDDS_REL ==> REL_OFFSET + offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S; + } + return offset; +} + +//***************************************************************************** +// +// Converts an "ideal" ADC value to microvolts +// +//***************************************************************************** +int32_t +AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue) +{ + // Chop off 4 bits during calculations to avoid 32-bit overflow + fixedRefVoltage >>= 4; + return (((adcValue * fixedRefVoltage) + 2047) / 4095) << 4; +} + +//***************************************************************************** +// +// Converts a number of microvolts to corresponding "ideal" ADC value +// +//***************************************************************************** +int32_t +AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts) +{ + // Chop off 4 bits during calculations to avoid 32-bit overflow + fixedRefVoltage >>= 4; + microvolts >>= 4; + return ((microvolts * 4095) + (fixedRefVoltage / 2)) / fixedRefVoltage; +} + +//***************************************************************************** +// +// Performs ADC value gain and offset adjustment +// +//***************************************************************************** +int32_t +AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) +{ + // Apply gain and offset adjustment + adcValue = (((adcValue + offset) * gain) + 16384) / 32768; + + // Saturate + if (adcValue < 0) { + return 0; + } else if (adcValue > 4095) { + return 4095; + } else { + return adcValue; + } +} + +//***************************************************************************** +// +// Performs the inverse of the ADC value gain and offset adjustment +// +//***************************************************************************** +int32_t +AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) +{ + // Apply inverse gain and offset adjustment + adcValue = (((adcValue * 32768) + (gain / 2)) / gain) - offset; + + // Saturate + if (adcValue < 0) { + return 0; + } else if (adcValue > 4095) { + return 4095; + } else { + return adcValue; + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_adc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_adc.h new file mode 100644 index 0000000..55631d7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_adc.h @@ -0,0 +1,590 @@ +/****************************************************************************** +* Filename: aux_adc.h +* Revised: 2018-02-07 09:45:39 +0100 (Wed, 07 Feb 2018) +* Revision: 51437 +* +* Description: Defines and prototypes for the AUX Analog-to-Digital +* Converter +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxadc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_ADC_H__ +#define __AUX_ADC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_event.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_4_aux.h" +#include "../inc/hw_aux_anaif.h" +#include "rom.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXADCDisable NOROM_AUXADCDisable + #define AUXADCEnableAsync NOROM_AUXADCEnableAsync + #define AUXADCEnableSync NOROM_AUXADCEnableSync + #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling + #define AUXADCFlushFifo NOROM_AUXADCFlushFifo + #define AUXADCReadFifo NOROM_AUXADCReadFifo + #define AUXADCPopFifo NOROM_AUXADCPopFifo + #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain + #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset + #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts + #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue + #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset + #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset +#endif + +//***************************************************************************** +// +// Defines for ADC reference sources. +// +//***************************************************************************** +#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S) +#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S) + +//***************************************************************************** +// +// Defines for the ADC FIFO status bits. +// +//***************************************************************************** +#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M) +#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M) +#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M) +#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M) +#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M) + +//***************************************************************************** +// +// Defines for supported ADC triggers. +// +//***************************************************************************** +#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE) +#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A) +#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B) +#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A) +#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B) +#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A) +#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B) +#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A) +#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B) + +//***************************************************************************** +// +// Defines for ADC sampling type for synchronous operation. +// +//***************************************************************************** +#define AUXADC_SAMPLE_TIME_2P7_US 3 +#define AUXADC_SAMPLE_TIME_5P3_US 4 +#define AUXADC_SAMPLE_TIME_10P6_US 5 +#define AUXADC_SAMPLE_TIME_21P3_US 6 +#define AUXADC_SAMPLE_TIME_42P6_US 7 +#define AUXADC_SAMPLE_TIME_85P3_US 8 +#define AUXADC_SAMPLE_TIME_170_US 9 +#define AUXADC_SAMPLE_TIME_341_US 10 +#define AUXADC_SAMPLE_TIME_682_US 11 +#define AUXADC_SAMPLE_TIME_1P37_MS 12 +#define AUXADC_SAMPLE_TIME_2P73_MS 13 +#define AUXADC_SAMPLE_TIME_5P46_MS 14 +#define AUXADC_SAMPLE_TIME_10P9_MS 15 + +//***************************************************************************** +// +// Equivalent voltages for fixed ADC reference, in microvolts. +// +//***************************************************************************** +#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000 +#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500 + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + + +//***************************************************************************** +// +//! \brief Disables the ADC. +//! +//! This function must be called: +//! - Before re-enabling the ADC using \ref AUXADCEnableAsync() or +//! \ref AUXADCEnableSync() +//! - Before entering system standby +// +//***************************************************************************** +extern void AUXADCDisable(void); + +//***************************************************************************** +// +//! \brief Enables the ADC for asynchronous operation. +//! +//! In asynchronous operation, the ADC samples continuously between +//! conversions. +//! +//! The ADC trigger starts the conversion. Note that the first conversion may +//! be invalid if the sampling period is too short. +//! +//! ADC input scaling is enabled by default after device reset, and is also re- +//! enabled by \ref AUXADCDisable(). To disable input scaling, call +//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableAsync(). +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! \param trigger +//! ADC conversion trigger: +//! - \ref AUXADC_TRIGGER_MANUAL +//! - \ref AUXADC_TRIGGER_GPT0A +//! - \ref AUXADC_TRIGGER_GPT0B +//! - \ref AUXADC_TRIGGER_GPT1A +//! - \ref AUXADC_TRIGGER_GPT1B +//! - \ref AUXADC_TRIGGER_GPT2A +//! - \ref AUXADC_TRIGGER_GPT2B +//! - \ref AUXADC_TRIGGER_GPT3A +//! - \ref AUXADC_TRIGGER_GPT3B +// +//***************************************************************************** +extern void AUXADCEnableAsync(uint32_t refSource, uint32_t trigger); + +//***************************************************************************** +// +//! \brief Enables the ADC for synchronous operation. +//! +//! In synchronous operation, the ADC is idle between a conversion and +//! subsequent samplings. +//! +//! The ADC trigger starts sampling with specified duration, followed by the +//! conversion. Note that the first conversion may be invalid if the initial +//! sampling period is too short. +//! +//! ADC input scaling is enabled by default after device reset, and is also re- +//! enabled by \ref AUXADCDisable(). To disable input scaling, call +//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableSync(). +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! \param sampleTime +//! ADC sampling time: +//! - \ref AUXADC_SAMPLE_TIME_2P7_US +//! - \ref AUXADC_SAMPLE_TIME_5P3_US +//! - \ref AUXADC_SAMPLE_TIME_10P6_US +//! - \ref AUXADC_SAMPLE_TIME_21P3_US +//! - \ref AUXADC_SAMPLE_TIME_42P6_US +//! - \ref AUXADC_SAMPLE_TIME_85P3_US +//! - \ref AUXADC_SAMPLE_TIME_170_US +//! - \ref AUXADC_SAMPLE_TIME_341_US +//! - \ref AUXADC_SAMPLE_TIME_682_US +//! - \ref AUXADC_SAMPLE_TIME_1P37_MS +//! - \ref AUXADC_SAMPLE_TIME_2P73_MS +//! - \ref AUXADC_SAMPLE_TIME_5P46_MS +//! - \ref AUXADC_SAMPLE_TIME_10P9_MS +//! \param trigger +//! ADC conversion trigger: +//! - \ref AUXADC_TRIGGER_MANUAL +//! - \ref AUXADC_TRIGGER_GPT0A +//! - \ref AUXADC_TRIGGER_GPT0B +//! - \ref AUXADC_TRIGGER_GPT1A +//! - \ref AUXADC_TRIGGER_GPT1B +//! - \ref AUXADC_TRIGGER_GPT2A +//! - \ref AUXADC_TRIGGER_GPT2B +//! - \ref AUXADC_TRIGGER_GPT3A +//! - \ref AUXADC_TRIGGER_GPT3B +// +//***************************************************************************** +extern void AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger); + +//***************************************************************************** +// +//! \brief Disables scaling of the ADC input. +//! +//! By default, the ADC operates internally on a version of the input signal +//! that has been scaled down by a factor 1408 / 4095. This function +//! disables that scaling, allowing for a trade-off between dynamic range and +//! and resolution. +//! +//! \note This function must only be called while the ADC is disabled, before +//! calling \ref AUXADCEnableSync() or \ref AUXADCEnableAsync(). +//! \note Different input maximum ratings apply when input scaling is disabled. +//! Violating these may damage the device. +// +//***************************************************************************** +extern void AUXADCDisableInputScaling(void); + +//***************************************************************************** +// +//! \brief Flushes the ADC FIFO. +//! +//! This empties the FIFO and clears the underflow/overflow flags. +//! +//! Note: This function must only be called while the ADC is enabled. +// +//***************************************************************************** +extern void AUXADCFlushFifo(void); + +//***************************************************************************** +// +//! \brief Generates a single manual ADC trigger. +//! +//! For synchronous mode, the trigger starts sampling followed by conversion. +//! For asynchronous mode, the trigger starts conversion. +// +//***************************************************************************** +__STATIC_INLINE void +AUXADCGenManualTrigger(void) +{ + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCTRIG) = 0; +} + +//***************************************************************************** +// +//! \brief Returns flags indicating the status of the ADC FIFO. +//! +//! The flags indicate FIFO empty, full and almost full, and whether +//! overflow/underflow has occurred. +//! +//! \return +//! A combination (bitwise OR) of the following flags: +//! - \ref AUXADC_FIFO_EMPTY_M +//! - \ref AUXADC_FIFO_ALMOST_FULL_M +//! - \ref AUXADC_FIFO_FULL_M +//! - \ref AUXADC_FIFO_UNDERFLOW_M +//! - \ref AUXADC_FIFO_OVERFLOW_M +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXADCGetFifoStatus(void) +{ + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT); +} + +//***************************************************************************** +// +//! \brief Waits for and returns the first sample in the ADC FIFO. +//! +//! This function waits until there is at least one sample in the ADC FIFO. It +//! then pops and returns the first sample from the FIFO. +//! +//! \note This procedure will deadlock if called without setting up ADC trigger +//! generation in advance. The trigger can either be manual or periodical +//! (using a GPT). +//! +//! \return The first (12-bit) sample from the ADC FIFO +// +//***************************************************************************** +extern uint32_t AUXADCReadFifo(void); + +//***************************************************************************** +// +//! \brief Returns the first sample in the ADC FIFO, without waiting. +//! +//! This function does not wait, and must only be called when there is at least +//! one sample in the ADC FIFO. Otherwise the call will generate FIFO underflow +//! (\ref AUXADC_FIFO_UNDERFLOW_M). +//! +//! \return The first (12-bit) sample from the ADC FIFO, or an undefined value +//! if the FIFO is empty +// +//***************************************************************************** +extern uint32_t AUXADCPopFifo(void); + +//***************************************************************************** +// +//! \brief Selects internal or external input for the ADC. +//! +//! Note that calling this function also selects the same input for AUX_COMPB. +//! +//! \param input +//! Internal/external input selection: +//! - \ref ADC_COMPB_IN_DCOUPL +//! - \ref ADC_COMPB_IN_VSS +//! - \ref ADC_COMPB_IN_VDDS +//! - \ref ADC_COMPB_IN_AUXIO7 +//! - \ref ADC_COMPB_IN_AUXIO6 +//! - \ref ADC_COMPB_IN_AUXIO5 +//! - \ref ADC_COMPB_IN_AUXIO4 +//! - \ref ADC_COMPB_IN_AUXIO3 +//! - \ref ADC_COMPB_IN_AUXIO2 +//! - \ref ADC_COMPB_IN_AUXIO1 +//! - \ref ADC_COMPB_IN_AUXIO0 +// +//***************************************************************************** +__STATIC_INLINE void +AUXADCSelectInput(uint32_t input) +{ + HapiSelectADCCompBInput(input); +} + +//***************************************************************************** +// +//! \brief Returns the gain value used when adjusting for ADC gain/offset. +//! +//! The function returns the gain value to be used with +//! \ref AUXADCAdjustValueForGainAndOffset() or +//! \ref AUXADCUnadjustValueForGainAndOffset(). The gain value is found during +//! chip manufacturing and is stored in the factory configuration, FCFG1. +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! +//! \return +//! The gain value to be used in adjustments +// +//***************************************************************************** +extern int32_t AUXADCGetAdjustmentGain(uint32_t refSource); + +//***************************************************************************** +// +//! \brief Returns the offset value used when adjusting for ADC gain/offset. +//! +//! The function returns the offset value to be used with +//! \ref AUXADCAdjustValueForGainAndOffset() or +//! \ref AUXADCUnadjustValueForGainAndOffset(). The offset value is found +//! during chip manufacturing and is stored in the factory configuration, +//! FCFG1. +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! +//! \return +//! The offset value to be used in adjustments +// +//***************************************************************************** +extern int32_t AUXADCGetAdjustmentOffset(uint32_t refSource); + +//***************************************************************************** +// +//! \brief Converts an "adjusted" ADC value to microvolts. +//! +//! This function can only be used when measuring with fixed ADC reference +//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for +//! whether the sampled ADC input is scaled down before conversion or not. +//! +//! \param fixedRefVoltage +//! Fixed reference voltage, in microvolts +//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal) +//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input +//! \param adcValue +//! The ADC value +//! +//! \return +//! The corresponding number of microvolts +// +//***************************************************************************** +extern int32_t AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue); + +//***************************************************************************** +// +//! \brief Converts a number of microvolts to corresponding "adjusted" ADC value. +//! +//! This function can only be used when measuring with fixed ADC reference +//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for +//! whether the sampled ADC input is scaled down before conversion or not. +//! +//! \param fixedRefVoltage +//! Fixed reference voltage, in microvolts +//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal) +//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input +//! \param microvolts +//! The number of microvolts +//! +//! \return +//! The corresponding expected ADC value (adjusted for ADC gain/offset) +// +//***************************************************************************** +extern int32_t AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts); + +//***************************************************************************** +// +//! \brief Performs ADC value gain and offset adjustment. +//! +//! This function takes a measured ADC value compensates for the internal gain +//! and offset in the ADC. +//! +//! \param adcValue +//! 12-bit ADC unadjusted value +//! \param gain +//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain() +//! \param offset +//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset() +//! +//! \return +//! 12-bit ADC adjusted value +// +//***************************************************************************** +extern int32_t AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset); + +//***************************************************************************** +// +//! \brief Performs the inverse of the ADC value gain and offset adjustment. +//! +//! This function finds the expected measured ADC value, without gain and +//! offset compensation, for a given "ideal" ADC value. The function can for +//! example be used to find ADC value thresholds to be used in Sensor +//! Controller task configurations. +//! +//! \param adcValue +//! 12-bit ADC adjusted value +//! \param gain +//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain() +//! \param offset +//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset() +//! +//! \return +//! 12-bit ADC unadjusted value +// +//***************************************************************************** +extern int32_t AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXADCDisable + #undef AUXADCDisable + #define AUXADCDisable ROM_AUXADCDisable + #endif + #ifdef ROM_AUXADCEnableAsync + #undef AUXADCEnableAsync + #define AUXADCEnableAsync ROM_AUXADCEnableAsync + #endif + #ifdef ROM_AUXADCEnableSync + #undef AUXADCEnableSync + #define AUXADCEnableSync ROM_AUXADCEnableSync + #endif + #ifdef ROM_AUXADCDisableInputScaling + #undef AUXADCDisableInputScaling + #define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling + #endif + #ifdef ROM_AUXADCFlushFifo + #undef AUXADCFlushFifo + #define AUXADCFlushFifo ROM_AUXADCFlushFifo + #endif + #ifdef ROM_AUXADCReadFifo + #undef AUXADCReadFifo + #define AUXADCReadFifo ROM_AUXADCReadFifo + #endif + #ifdef ROM_AUXADCPopFifo + #undef AUXADCPopFifo + #define AUXADCPopFifo ROM_AUXADCPopFifo + #endif + #ifdef ROM_AUXADCGetAdjustmentGain + #undef AUXADCGetAdjustmentGain + #define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain + #endif + #ifdef ROM_AUXADCGetAdjustmentOffset + #undef AUXADCGetAdjustmentOffset + #define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset + #endif + #ifdef ROM_AUXADCValueToMicrovolts + #undef AUXADCValueToMicrovolts + #define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts + #endif + #ifdef ROM_AUXADCMicrovoltsToValue + #undef AUXADCMicrovoltsToValue + #define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue + #endif + #ifdef ROM_AUXADCAdjustValueForGainAndOffset + #undef AUXADCAdjustValueForGainAndOffset + #define AUXADCAdjustValueForGainAndOffset ROM_AUXADCAdjustValueForGainAndOffset + #endif + #ifdef ROM_AUXADCUnadjustValueForGainAndOffset + #undef AUXADCUnadjustValueForGainAndOffset + #define AUXADCUnadjustValueForGainAndOffset ROM_AUXADCUnadjustValueForGainAndOffset + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_ADC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_smph.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_smph.c new file mode 100644 index 0000000..76dc0b1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_smph.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: aux_smph.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the AUX Semaphore. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_smph.h" + +// See aux_smph.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_smph.h new file mode 100644 index 0000000..4ff1314 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_smph.h @@ -0,0 +1,258 @@ +/****************************************************************************** +* Filename: aux_smph.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the AUX Semaphore +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxsmph_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_SMPH_H__ +#define __AUX_SMPH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_aux_smph.h" +#include "../inc/hw_memmap.h" +#include "debug.h" + +//***************************************************************************** +// +// General constants and defines +// +//***************************************************************************** +#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed + +//***************************************************************************** +// +// Values that can be passed to AUXSMPHAcquire and AUXSMPHRelease +// as the ui32Semaphore parameter. +// +//***************************************************************************** +#define AUX_SMPH_0 0 // AUX Semaphore 0 +#define AUX_SMPH_1 1 // AUX Semaphore 1 +#define AUX_SMPH_2 2 // AUX Semaphore 2 +#define AUX_SMPH_3 3 // AUX Semaphore 3 +#define AUX_SMPH_4 4 // AUX Semaphore 4 +#define AUX_SMPH_5 5 // AUX Semaphore 5 +#define AUX_SMPH_6 6 // AUX Semaphore 6 +#define AUX_SMPH_7 7 // AUX Semaphore 7 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Acquire an AUX semaphore. +//! +//! This function acquires the given AUX semaphore, blocking the call until +//! the semaphore is available. +//! +//! \note The semaphore can also be acquired by the dedicated Sensor Controller. +//! The System CPU master can thus be competing for the shared resource, i.e. +//! the specified semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref AUX_SMPH_0 +//! - \ref AUX_SMPH_1 +//! - \ref AUX_SMPH_2 +//! - \ref AUX_SMPH_3 +//! - \ref AUX_SMPH_4 +//! - \ref AUX_SMPH_5 +//! - \ref AUX_SMPH_6 +//! - \ref AUX_SMPH_7 +//! +//! \return None +//! +//! \sa AUXSMPHTryAcquire(), AUXSMPHRelease() +// +//***************************************************************************** +__STATIC_INLINE void +AUXSMPHAcquire(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == AUX_SMPH_0) || + (ui32Semaphore == AUX_SMPH_1) || + (ui32Semaphore == AUX_SMPH_2) || + (ui32Semaphore == AUX_SMPH_3) || + (ui32Semaphore == AUX_SMPH_4) || + (ui32Semaphore == AUX_SMPH_5) || + (ui32Semaphore == AUX_SMPH_6) || + (ui32Semaphore == AUX_SMPH_7)); + + // Wait for semaphore to be released such that it can be claimed + // Semaphore register reads 1 when lock was acquired otherwise 0 + // (i.e. AUX_SMPH_CLAIMED). + while(HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) == + AUX_SMPH_CLAIMED) + { + } +} + +//***************************************************************************** +// +//! \brief Try to acquire an AUX semaphore. +//! +//! This function tries to acquire the given AUX semaphore, if the semaphore +//! could not be claimed the function returns false. +//! +//! \note The semaphore can also be acquired by the dedicated Sensor Controller. +//! The System CPU master can thus be competing for the shared resource, i.e. +//! the specified semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref AUX_SMPH_0 +//! - \ref AUX_SMPH_1 +//! - \ref AUX_SMPH_2 +//! - \ref AUX_SMPH_3 +//! - \ref AUX_SMPH_4 +//! - \ref AUX_SMPH_5 +//! - \ref AUX_SMPH_6 +//! - \ref AUX_SMPH_7 +//! +//! \return Returns true if semaphore was acquired, false otherwise +//! +//! \sa AUXSMPHAcquire(), AUXSMPHRelease() +// +//***************************************************************************** +__STATIC_INLINE bool +AUXSMPHTryAcquire(uint32_t ui32Semaphore) +{ + uint32_t ui32SemaReg; + + // Check the arguments. + ASSERT((ui32Semaphore == AUX_SMPH_0) || + (ui32Semaphore == AUX_SMPH_1) || + (ui32Semaphore == AUX_SMPH_2) || + (ui32Semaphore == AUX_SMPH_3) || + (ui32Semaphore == AUX_SMPH_4) || + (ui32Semaphore == AUX_SMPH_5) || + (ui32Semaphore == AUX_SMPH_6) || + (ui32Semaphore == AUX_SMPH_7)); + + // AUX Semaphore register reads 1 if lock was acquired + // (i.e. SMPH_FREE when read) but subsequent reads will read 0. + ui32SemaReg = HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore); + + return (ui32SemaReg == AUX_SMPH_FREE); +} + +//***************************************************************************** +// +//! \brief Release an AUX semaphore by System CPU master. +//! +//! This function releases the given AUX semaphore. +//! +//! \note It is up to the application to provide the convention for clearing +//! semaphore. +//! +//! \note The semaphore can also be acquired by the dedicated Sensor Controller. +//! The System CPU master can thus be competing for the shared resource, i.e. +//! the specified semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref AUX_SMPH_0 +//! - \ref AUX_SMPH_1 +//! - \ref AUX_SMPH_2 +//! - \ref AUX_SMPH_3 +//! - \ref AUX_SMPH_4 +//! - \ref AUX_SMPH_5 +//! - \ref AUX_SMPH_6 +//! - \ref AUX_SMPH_7 +//! +//! \return None +//! +//! \sa AUXSMPHAcquire(), AUXSMPHTryAcquire() +// +//***************************************************************************** +__STATIC_INLINE void +AUXSMPHRelease(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == AUX_SMPH_0) || + (ui32Semaphore == AUX_SMPH_1) || + (ui32Semaphore == AUX_SMPH_2) || + (ui32Semaphore == AUX_SMPH_3) || + (ui32Semaphore == AUX_SMPH_4) || + (ui32Semaphore == AUX_SMPH_5) || + (ui32Semaphore == AUX_SMPH_6) || + (ui32Semaphore == AUX_SMPH_7)); + + // No check before release. It is up to the application to provide the + // conventions for who and when a semaphore can be released. + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) = + AUX_SMPH_FREE; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_SMPH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_tdc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_tdc.c new file mode 100644 index 0000000..4e6993e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_tdc.c @@ -0,0 +1,111 @@ +/****************************************************************************** +* Filename: aux_tdc.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the AUX Time to Digital Converter interface. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_tdc.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXTDCConfigSet + #define AUXTDCConfigSet NOROM_AUXTDCConfigSet + #undef AUXTDCMeasurementDone + #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone +#endif + +//***************************************************************************** +// +// Configure the operation of the AUX TDC +// +//***************************************************************************** +void +AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, + uint32_t ui32StopCondition) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Make sure the AUX TDC is in the idle state before changing the + // configuration. + while(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + } + + // Clear previous results. + HWREG(ui32Base + AUX_TDC_O_CTL) = 0x0; + + // Change the configuration. + HWREG(ui32Base + AUX_TDC_O_TRIGSRC) = ui32StartCondition | ui32StopCondition; +} + +//***************************************************************************** +// +// Check if the AUX TDC is done measuring +// +//***************************************************************************** +uint32_t +AUXTDCMeasurementDone(uint32_t ui32Base) +{ + uint32_t ui32Reg; + uint32_t ui32Status; + + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is done measuring. + ui32Reg = HWREG(ui32Base + AUX_TDC_O_STAT); + if(ui32Reg & AUX_TDC_STAT_DONE) + { + ui32Status = AUX_TDC_DONE; + } + else if(ui32Reg & AUX_TDC_STAT_SAT) + { + ui32Status = AUX_TDC_TIMEOUT; + } + else + { + ui32Status = AUX_TDC_BUSY; + } + + // Return the status. + return (ui32Status); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_tdc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_tdc.h new file mode 100644 index 0000000..a8f567f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_tdc.h @@ -0,0 +1,776 @@ +/****************************************************************************** +* Filename: aux_tdc.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Defines and prototypes for the AUX Time-to-Digital Converter +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxtdc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_TDC_H__ +#define __AUX_TDC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aux_tdc.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXTDCConfigSet NOROM_AUXTDCConfigSet + #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone +#endif + +//***************************************************************************** +// +// Defines for the status of a AUX TDC measurement. +// +//***************************************************************************** +#define AUX_TDC_BUSY 0x00000001 +#define AUX_TDC_TIMEOUT 0x00000002 +#define AUX_TDC_DONE 0x00000004 + +//***************************************************************************** +// +// Defines for the control of a AUX TDC. +// +//***************************************************************************** +#define AUX_TDC_RUNSYNC 0x00000001 +#define AUX_TDC_RUN 0x00000002 +#define AUX_TDC_ABORT 0x00000003 + +//***************************************************************************** +// +// Defines for possible states of the TDC internal state machine. +// +//***************************************************************************** +#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START) +#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN) +#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE) +#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT) +#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP) +#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN) +#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT) +#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR) +#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE) +#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL) +#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP) + +//***************************************************************************** +// +// Defines for controlling the AUX TDC. Values can be passed to AUXTDCConfigSet(). +// +//***************************************************************************** +#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event +#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event + +#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0) +#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1) +#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2) +#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3) +#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4) +#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5) +#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6) +#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7) +#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8) +#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9) +#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10) +#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11) +#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12) +#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13) +#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14) +#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15) +#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE) +#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL) +#define AUXTDC_STOP_AON_PROG_WU (AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU) +#define AUXTDC_STOP_AON_SW (AUX_TDC_TRIGSRC_STOP_SRC_AON_SW) +#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET) +#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0) +#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1) +#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE) +#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE) +#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV) +#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV) +#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2) +#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA) +#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB) +#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF) +#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV) + +#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event +#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event + +#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0) +#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1) +#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2) +#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3) +#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4) +#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5) +#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6) +#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7) +#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8) +#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9) +#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10) +#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11) +#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12) +#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13) +#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14) +#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15) +#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_ADC_DONE) +#define AUXTDC_START_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL) +#define AUXTDC_START_AON_PROG_WU (AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU) +#define AUXTDC_START_AON_SW (AUX_TDC_TRIGSRC_START_SRC_AON_SW) +#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET) +#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX0) +#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX1) +#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE) +#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_TDC_PRE) +#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV) +#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV) +#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2) +#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA) +#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB) +#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF) +#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV) + +//***************************************************************************** +// +// Defines for the possible saturation values set using AUXTDCLimitSet(). +// +//***************************************************************************** +#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12) +#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13) +#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14) +#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15) +#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16) +#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17) +#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18) +#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19) +#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20) +#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21) +#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22) +#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23) +#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24) +#define AUXTDC_NUM_SAT_VALS 16 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! \brief Checks an AUX TDC base address. +//! +//! This function determines if a AUX TDC port base address is valid. +//! +//! \param ui32Base is the base address of the AUX TDC port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +AUXTDCBaseValid(uint32_t ui32Base) +{ + return(ui32Base == AUX_TDC_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Get the status of the AUX TDC internal state machine. +//! +//! This function will return the current state of the AUX TDC internal state +//! machine. +//! \param ui32Base is base address of the AUX TDC +//! +//! \return Returns the current state of the state machine. +//! Possible states for the state machine are: +//! - \ref AUXTDC_WAIT_START +//! - \ref AUXTDC_WAIT_START_CNTEN +//! - \ref AUXTDC_IDLE +//! - \ref AUXTDC_CLRCNT +//! - \ref AUXTDC_WAIT_STOP +//! - \ref AUXTDC_WAIT_STOP_CNTDOWN +//! - \ref AUXTDC_GETRESULTS +//! - \ref AUXTDC_POR +//! - \ref AUXTDC_WAIT_CLRCNT_DONE +//! - \ref AUXTDC_START_FALL +//! - \ref AUXTDC_FORCE_STOP. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCStatusGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the status value for the correct ADI Slave. + return((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) >> + AUX_TDC_STAT_STATE_S); +} + +//***************************************************************************** +// +//! \brief Configure the operation of the AUX TDC. +//! +//! Use this function to configure the start and stop event for the AUX TDC. +//! +//! The \c ui32StartCondition must be a bitwise OR of the start event and the +//! polarity of the start event. The start events are: +//! - \ref AUXTDC_START_AUXIO0 +//! - \ref AUXTDC_START_AUXIO1 +//! - \ref AUXTDC_START_AUXIO2 +//! - \ref AUXTDC_START_AUXIO3 +//! - \ref AUXTDC_START_AUXIO4 +//! - \ref AUXTDC_START_AUXIO5 +//! - \ref AUXTDC_START_AUXIO6 +//! - \ref AUXTDC_START_AUXIO7 +//! - \ref AUXTDC_START_AUXIO8 +//! - \ref AUXTDC_START_AUXIO9 +//! - \ref AUXTDC_START_AUXIO10 +//! - \ref AUXTDC_START_AUXIO11 +//! - \ref AUXTDC_START_AUXIO12 +//! - \ref AUXTDC_START_AUXIO13 +//! - \ref AUXTDC_START_AUXIO14 +//! - \ref AUXTDC_START_AUXIO15 +//! - \ref AUXTDC_START_ADC_DONE +//! - \ref AUXTDC_START_ADC_FIFO_ALMOST_FULL +//! - \ref AUXTDC_START_AON_PROG_WU +//! - \ref AUXTDC_START_AON_SW +//! - \ref AUXTDC_START_ISRC_RESET +//! - \ref AUXTDC_START_OBSMUX0 +//! - \ref AUXTDC_START_OBSMUX1 +//! - \ref AUXTDC_START_SMPH_AUTOTAKE_DONE +//! - \ref AUXTDC_START_TDC_PRE +//! - \ref AUXTDC_START_TIMER0_EV +//! - \ref AUXTDC_START_TIMER1_EV +//! - \ref AUXTDC_START_AON_RTC_CH2 +//! - \ref AUXTDC_START_AUX_COMPA +//! - \ref AUXTDC_START_AUX_COMPB +//! - \ref AUXTDC_START_ACLK_REF +//! - \ref AUXTDC_START_MCU_EV +//! +//! The polarity of the start event is either rising \ref AUXTDC_STARTPOL_RIS +//! or falling \ref AUXTDC_STARTPOL_FALL. +//! +//! The \c ui32StopCondition must be a bitwise OR of the stop event and the +//! polarity of the stop event. The stop events are: +//! - \ref AUXTDC_STOP_AUXIO0 +//! - \ref AUXTDC_STOP_AUXIO1 +//! - \ref AUXTDC_STOP_AUXIO2 +//! - \ref AUXTDC_STOP_AUXIO3 +//! - \ref AUXTDC_STOP_AUXIO4 +//! - \ref AUXTDC_STOP_AUXIO5 +//! - \ref AUXTDC_STOP_AUXIO6 +//! - \ref AUXTDC_STOP_AUXIO7 +//! - \ref AUXTDC_STOP_AUXIO8 +//! - \ref AUXTDC_STOP_AUXIO9 +//! - \ref AUXTDC_STOP_AUXIO10 +//! - \ref AUXTDC_STOP_AUXIO11 +//! - \ref AUXTDC_STOP_AUXIO12 +//! - \ref AUXTDC_STOP_AUXIO13 +//! - \ref AUXTDC_STOP_AUXIO14 +//! - \ref AUXTDC_STOP_AUXIO15 +//! - \ref AUXTDC_STOP_ADC_DONE +//! - \ref AUXTDC_STOP_ADC_FIFO_ALMOST_FULL +//! - \ref AUXTDC_STOP_AON_PROG_WU +//! - \ref AUXTDC_STOP_AON_SW +//! - \ref AUXTDC_STOP_ISRC_RESET +//! - \ref AUXTDC_STOP_OBSMUX0 +//! - \ref AUXTDC_STOP_OBSMUX1 +//! - \ref AUXTDC_STOP_SMPH_AUTOTAKE_DONE +//! - \ref AUXTDC_STOP_TDC_PRE +//! - \ref AUXTDC_STOP_TIMER0_EV +//! - \ref AUXTDC_STOP_TIMER1_EV +//! - \ref AUXTDC_STOP_AON_RTC_CH2 +//! - \ref AUXTDC_STOP_AUX_COMPA +//! - \ref AUXTDC_STOP_AUX_COMPB +//! - \ref AUXTDC_STOP_ACLK_REF +//! - \ref AUXTDC_STOP_MCU_EV +//! +//! The polarity of the stop event is either rising \ref AUXTDC_STOPPOL_RIS +//! or falling \ref AUXTDC_STOPPOL_FALL. +//! +//! \note The AUX TDC should only be configured when the AUX TDC is in the Idle +//! state. To ensure that software does not lock up, it is recommended to +//! ensure that the AUX TDC is actually in idle when calling \ref AUXTDCConfigSet(). +//! This can be tested using \ref AUXTDCIdle(). +//! +//! \param ui32Base is base address of the AUX TDC. +//! \param ui32StartCondition is AUX TDC a bitwise OR of a start event and polarity. +//! \param ui32StopCondition is AUX TDC a bitwise OR of a stop event and polarity. +//! +//! \return None +//! +//! \sa \ref AUXTDCConfigSet(), \ref AUXTDCIdle() +// +//***************************************************************************** +extern void AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, + uint32_t ui32StopCondition); + +//***************************************************************************** +// +//! \brief Check if the AUX TDC is in idle mode. +//! +//! This function can be used to check whether the AUX TDC internal state +//! machine is in idle mode. This is required before setting the polarity +//! of the start and stop event. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return Returns \c true if state machine is in idle and returns \c false +//! if the state machine is in any other state. +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCIdle(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in the Idle state. + return (((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE) ? true : false); +} + +//***************************************************************************** +// +//! \brief Enable the AUX TDC for a measurement. +//! +//! This function is used for arming the AUX TDC to begin a measurement as +//! soon as the start condition is met. There are two run modes: +//! - \ref AUX_TDC_RUNSYNC will wait for a falling event of the start pulse before +//! starting measurement on next rising edge of start. This guarantees an edge +//! triggered start and is recommended for frequency measurements. If the +//! first falling edge is close to the start command it may be missed, but +//! the TDC shall catch later falling edges and in any case guarantee a +//! measurement start synchronous to the rising edge of the start event. +//! - The \ref AUX_TDC_RUN is asynchronous start and asynchronous stop mode. Using +//! this a TDC measurement may start immediately if start is high and hence it +//! may not give precise edge to edge measurements. This mode is only +//! recommended when start pulse is guaranteed to arrive at least 7 clock +//! periods after command. +//! +//! \note The AUX TDC should be configured and in Idle mode before calling this +//! function. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! \param ui32RunMode is the run mode for the AUX TDC. +//! - \ref AUX_TDC_RUNSYNC : Synchronous run mode. +//! - \ref AUX_TDC_RUN : Asynchronous run mode. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AUXTDCEnable(uint32_t ui32Base, uint32_t ui32RunMode) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + ASSERT((ui32RunMode == AUX_TDC_RUN) || + (ui32RunMode == AUX_TDC_RUNSYNC)); + + // Enable the AUX TDC. + HWREG(ui32Base + AUX_TDC_O_CTL) = ui32RunMode; +} + +//***************************************************************************** +// +//! \brief Force the AUX TDC back to Idle mode. +//! +//! This function will force the AUX TDC in Idle mode. The internal state +//! machine will not go directly to Idle mode, so it is left to the programmer to +//! ensure that the state machine is in Idle mode before doing any new +//! configuration. This can be checked using \ref AUXTDCIdle(). +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return None +//! +//! \sa \ref AUXTDCIdle() +// +//***************************************************************************** +__STATIC_INLINE void +AUXTDCIdleForce(uint32_t ui32Base) +{ + // Check the arguments + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Abort operation of AUX TDC and force into Idle mode. + HWREG(ui32Base + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_ABORT; +} + +//***************************************************************************** +// +//! \brief Check if the AUX TDC is done measuring. +//! +//! This function can be used to check whether the AUX TDC has finished a +//! measurement. The AUX TDC may have completed a measurement for two reasons. +//! Either it finish successfully \ref AUX_TDC_DONE or it failed due to a timeout +//! \ref AUX_TDC_TIMEOUT. If the AUX TDC is still measuring it this function +//! will return \ref AUX_TDC_BUSY. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return Returns the current status of a measurement: +//! - \ref AUX_TDC_DONE : An AUX TDC measurement finished successfully. +//! - \ref AUX_TDC_TIMEOUT : An AUX TDC measurement failed due to timeout. +//! - \ref AUX_TDC_BUSY : An AUX TDC measurement is being performed. +// +//***************************************************************************** +extern uint32_t AUXTDCMeasurementDone(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Get the value of the latest measurement. +//! +//! This function is used for retrieving the value of the latest measurement +//! performed by the AUX TDC. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return Returns the result of the latest measurement. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCMeasurementGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the measurement. + return (HWREG(ui32Base + AUX_TDC_O_RESULT)); +} + +//***************************************************************************** +// +//! \brief Set the saturation limit of the measurement. +//! +//! This function is used to set a saturation limit for the event accumulation +//! register. The saturation limit is defined as a bit width of the +//! accumulation register and therefore increases in power of 2. +//! +//! \param ui32Base is base address of the AUX TDC. +//! \param ui32Limit is the saturation limit. +//! - \ref AUXTDC_SAT_4096 +//! - \ref AUXTDC_SAT_8192 +//! - \ref AUXTDC_SAT_16384 +//! - \ref AUXTDC_SAT_32768 +//! - \ref AUXTDC_SAT_65536 +//! - \ref AUXTDC_SAT_131072 +//! - \ref AUXTDC_SAT_262144 +//! - \ref AUXTDC_SAT_524288 +//! - \ref AUXTDC_SAT_1048576 +//! - \ref AUXTDC_SAT_2097152 +//! - \ref AUXTDC_SAT_4194304 +//! - \ref AUXTDC_SAT_8388608 +//! - \ref AUXTDC_SAT_16777216 (default) +//! +//! \return None +//! +//! \note The actual value of the accumulation register might increase slightly beyond +//! the saturation value before the saturation takes effect. +//! +//! \sa \ref AUXTDCLimitGet() +// +//***************************************************************************** +__STATIC_INLINE void +AUXTDCLimitSet(uint32_t ui32Base, uint32_t ui32Limit) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + ASSERT(ui32Limit < AUXTDC_NUM_SAT_VALS); + + // Set the saturation limit. + HWREG(ui32Base + AUX_TDC_O_SATCFG) = ui32Limit; +} + +//***************************************************************************** +// +//! \brief Get the saturation limit of the measurement. +//! +//! This function is used to retrieve the current saturation for the +//! accumulator register. +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns the saturation limit. +//! - \ref AUXTDC_SAT_4096 +//! - \ref AUXTDC_SAT_8192 +//! - \ref AUXTDC_SAT_16384 +//! - \ref AUXTDC_SAT_32768 +//! - \ref AUXTDC_SAT_65536 +//! - \ref AUXTDC_SAT_131072 +//! - \ref AUXTDC_SAT_262144 +//! - \ref AUXTDC_SAT_524288 +//! - \ref AUXTDC_SAT_1048576 +//! - \ref AUXTDC_SAT_2097152 +//! - \ref AUXTDC_SAT_4194304 +//! - \ref AUXTDC_SAT_8388608 +//! - \ref AUXTDC_SAT_16777216 +//! +//! \sa \ref AUXTDCLimitSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCLimitGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the saturation limit. + return (HWREG(ui32Base + AUX_TDC_O_SATCFG)); +} + +//***************************************************************************** +// +//! \brief Enables the counter if possible. +//! +//! This function can be used to enable the AUX TDC stop/compare event counter. +//! The counter can be used to measure multiple periods of a clock signal. +//! For each stop/compare event the counter will be decremented by one and +//! the measurement will continue running until the value of the counter +//! reaches 0. The current value of the counter can be read using +//! \ref AUXTDCCounterGet(). The reset value of the counter can be set using +//! \ref AUXTDCCounterSet(). +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns \c true if the counter was successfully enabled. If the +//! AUX TDC is not in Idle mode, the counter can not be enabled, and the +//! return value will be \c false. +//! +//! \sa \ref AUXTDCCounterGet(), \ref AUXTDCCounterSet() +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCCounterEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in idle mode. If not in Idle mode, the counter + // will not be enabled. + if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + return false; + } + + // Enable the counter. + HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = AUX_TDC_TRIGCNTCFG_EN; + + // Counter successfully enabled. + return true; +} + +//***************************************************************************** +// +//! \brief Disables the counter if possible. +//! +//! This function can be used to disable the AUX TDC stop/compare event counter. +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns \c true if the counter was successfully disabled. If the +//! AUX TDC is not in Idle mode, the counter can not be disabled, and the +//! return value will be \c false. +//! +//! \sa \ref AUXTDCCounterEnable() for more information on how to use the counter. +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCCounterDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in Idle mode. If not in Idle mode, the counter + // will not be disabled. + if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + return false; + } + + // Disable the counter. + HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = 0; + + // Counter successfully disabled. + return true; +} + +//***************************************************************************** +// +//! \brief Set the reset number of counter compare/stop event to ignore before taking +//! a measurement. +//! +//! This function loads the reset value of the counter with the specified +//! number of events to ignore. A reset in this context means the counter +//! has been disabled and then enabled. +//! +//! \param ui32Base is base address of the AUX TDC. +//! \param ui32Events is the number of compare/stop events to load into the +//! counter. +//! +//! \return Returns \c true if the counter was successfully updated. If the +//! AUX TDC is not in Idle mode, the counter can not be updated, and the +//! return value will be \c false. +//! +//! \sa \ref AUXTDCCounterEnable() +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCCounterSet(uint32_t ui32Base, uint32_t ui32Events) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in idle mode. If not in idle mode, the counter + // will not be disabled. + if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + return false; + } + + // Update the reset counter value. + HWREG(ui32Base + AUX_TDC_O_TRIGCNTLOAD) = ui32Events; + + // Counter successfully updated. + return true; +} + +//***************************************************************************** +// +//! \brief Get the current number of counter compare/stop event to ignore before +//! taking a measurement. +//! +//! This function returns the current value of compare/stop events before +//! a measurement is registered. This value is decremented by one for each +//! registered compare/stop event and will always be less than or equal the +//! reset value of the counter set using \ref AUXTDCCounterSet(). +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns the current value of compare/stop events ignored before a +//! measurement is performed. +//! +//! \sa \ref AUXTDCCounterEnable(). +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCCounterGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the current counter value. + return (HWREG(ui32Base + AUX_TDC_O_TRIGCNT)); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXTDCConfigSet + #undef AUXTDCConfigSet + #define AUXTDCConfigSet ROM_AUXTDCConfigSet + #endif + #ifdef ROM_AUXTDCMeasurementDone + #undef AUXTDCMeasurementDone + #define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_TDC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_timer.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_timer.c new file mode 100644 index 0000000..0055159 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_timer.c @@ -0,0 +1,251 @@ +/****************************************************************************** +* Filename: aux_timer.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the AUX Timer Module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_timer.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXTimerConfigure + #define AUXTimerConfigure NOROM_AUXTimerConfigure + #undef AUXTimerStart + #define AUXTimerStart NOROM_AUXTimerStart + #undef AUXTimerStop + #define AUXTimerStop NOROM_AUXTimerStop + #undef AUXTimerPrescaleSet + #define AUXTimerPrescaleSet NOROM_AUXTimerPrescaleSet + #undef AUXTimerPrescaleGet + #define AUXTimerPrescaleGet NOROM_AUXTimerPrescaleGet +#endif + +//***************************************************************************** +// +// Configure AUX timer +// +//***************************************************************************** +void +AUXTimerConfigure(uint32_t ui32Timer, uint32_t ui32Config) +{ + uint32_t ui32Val; + + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + + // Configure Timer 0. + if(ui32Timer & AUX_TIMER_0) + { + // Stop timer 0. + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = 0; + + // Set mode. + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); + ui32Val &= ~(AUX_TIMER_T0CFG_MODE_M | AUX_TIMER_T0CFG_RELOAD_M); + ui32Val |= (ui32Config & (AUX_TIMER_T0CFG_MODE_M | + AUX_TIMER_T0CFG_RELOAD_M)); + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; + + // If edge counter, set rising/falling edge and tick source. + if(ui32Config & AUX_TIMER_T0CFG_MODE_M) + { + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); + ui32Val &= ~(AUX_TIMER_T0CFG_TICK_SRC_POL_M | + AUX_TIMER_T0CFG_TICK_SRC_M); + + // Set edge polarity. + if(ui32Config & AUX_TIMER_CFG_FALLING_EDGE) + { + ui32Val |= AUX_TIMER_T0CFG_TICK_SRC_POL; + } + + // Set tick source. + ui32Val |= (ui32Config & AUX_TIMER_T0CFG_TICK_SRC_M); + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; + } + } + + // Configure Timer 1. + if(ui32Timer & AUX_TIMER_1) + { + // Stop timer 1. + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = 0; + + // Set mode. + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); + ui32Val &= ~(AUX_TIMER_T1CFG_MODE_M | AUX_TIMER_T1CFG_RELOAD_M); + ui32Val |= ((ui32Config) & (AUX_TIMER_T1CFG_MODE_M | + AUX_TIMER_T1CFG_RELOAD_M)); + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; + + // If edge counter, set rising/falling edge and tick source. + if(ui32Config & AUX_TIMER_T1CFG_MODE) + { + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); + ui32Val &= ~(AUX_TIMER_T1CFG_TICK_SRC_POL_M | + AUX_TIMER_T1CFG_TICK_SRC_M); + + // Set edge polarity. + if(ui32Config & AUX_TIMER_CFG_FALLING_EDGE) + { + ui32Val |= AUX_TIMER_T1CFG_TICK_SRC_POL; + } + + // Set tick source. + ui32Val |= (ui32Config & AUX_TIMER_T1CFG_TICK_SRC_M); + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; + } + } +} + +//***************************************************************************** +// +// Start AUX timer +// +//***************************************************************************** +void +AUXTimerStart(uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || + (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + + if(ui32Timer & AUX_TIMER_0) + { + // Start timer 0. + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = AUX_TIMER_T0CTL_EN; + } + if(ui32Timer & AUX_TIMER_1) + { + // Start timer 1. + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = AUX_TIMER_T1CTL_EN; + } +} + +//***************************************************************************** +// +// Stop AUX timer +// +//***************************************************************************** +void +AUXTimerStop(uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || + (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + + if(ui32Timer & AUX_TIMER_0) + { + // Stop timer 0. + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = 0; + } + if(ui32Timer & AUX_TIMER_1) + { + // Stop timer 1. + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = 0; + } +} + +//***************************************************************************** +// +// Set AUX timer prescale value +// +//***************************************************************************** +void +AUXTimerPrescaleSet(uint32_t ui32Timer, uint32_t ui32PrescaleDiv) +{ + uint32_t ui32Val; + + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + ASSERT(ui32PrescaleDiv <= AUX_TIMER_PRESCALE_DIV_32768); + + if(ui32Timer & AUX_TIMER_0) + { + // Set timer 0 prescale value. + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); + ui32Val &= ~AUX_TIMER_T0CFG_PRE_M; + ui32Val |= ui32PrescaleDiv << AUX_TIMER_T0CFG_PRE_S; + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; + } + if(ui32Timer & AUX_TIMER_1) + { + // Set timer 1 prescale value. + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); + ui32Val &= ~AUX_TIMER_T1CFG_PRE_M; + ui32Val |= ui32PrescaleDiv << AUX_TIMER_T1CFG_PRE_S; + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; + } +} + +//***************************************************************************** +// +// Get AUX timer prescale value +// +//***************************************************************************** +uint32_t +AUXTimerPrescaleGet(uint32_t ui32Timer) +{ + uint32_t ui32Val; + uint32_t ui32PrescaleDiv; + + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); + + ui32Val = (HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG)); + if(ui32Timer & AUX_TIMER_0) + { + // Get timer 0 prescale value. + ui32PrescaleDiv = + (ui32Val & AUX_TIMER_T0CFG_PRE_M) >> AUX_TIMER_T0CFG_PRE_S; + } + else + { + // Get timer 1 prescale value. + ui32PrescaleDiv = + (ui32Val & AUX_TIMER_T1CFG_PRE_M) >> AUX_TIMER_T1CFG_PRE_S; + } + + return(ui32PrescaleDiv); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_timer.h new file mode 100644 index 0000000..b3266dd --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_timer.h @@ -0,0 +1,482 @@ +/****************************************************************************** +* Filename: aux_timer.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Defines and prototypes for the AUX Timer +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxtimer_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_TIMER_H__ +#define __AUX_TIMER_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aux_timer.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXTimerConfigure NOROM_AUXTimerConfigure + #define AUXTimerStart NOROM_AUXTimerStart + #define AUXTimerStop NOROM_AUXTimerStop + #define AUXTimerPrescaleSet NOROM_AUXTimerPrescaleSet + #define AUXTimerPrescaleGet NOROM_AUXTimerPrescaleGet +#endif + +//***************************************************************************** +// +// Values that can be passed to AUXTimerConfigure(). +// +//***************************************************************************** +#define AUX_TIMER_CFG_ONE_SHOT (AUX_TIMER_T0CFG_RELOAD_MAN) // One-shot timer mode +#define AUX_TIMER_CFG_PERIODIC (AUX_TIMER_T0CFG_RELOAD_CONT) // Period timer mode +#define AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_MAN) | (AUX_TIMER_T0CFG_MODE_TICK)) // One-shot timer with edge count +#define AUX_TIMER_CFG_PERIODIC_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_CONT) | (AUX_TIMER_T0CFG_MODE_TICK)) // Periodic timer with edge count +#define AUX_TIMER_CFG_RISING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_RISE) // Count rising edges (used with edge count mode) +#define AUX_TIMER_CFG_FALLING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_FALL) // Count falling edges (used with edge count mode) + +#define AUX_TIMER_CFG_TICK_SRC_RTC_EVENT (AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV) // AON wake-up event +#define AUX_TIMER_CFG_TICK_SRC_CMP_A (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA) // Comparator A +#define AUX_TIMER_CFG_TICK_SRC_CMP_B (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB) // Comparator B +#define AUX_TIMER_CFG_TICK_SRC_TDCDONE (AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE) // TDC Done +#define AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT (AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV) // Timer 0 event +#define AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT (AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV) // Timer 1 event +#define AUX_TIMER_CFG_TICK_SRC_SMPH_RELEASE (AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE) // Semaphore release +#define AUX_TIMER_CFG_TICK_SRC_ADC_DONE (AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE) // ADC done +#define AUX_TIMER_CFG_TICK_SRC_RTC_4KHZ (AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ) +#define AUX_TIMER_CFG_TICK_SRC_OBSMUX0 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0) +#define AUX_TIMER_CFG_TICK_SRC_OBSMUX1 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1) +#define AUX_TIMER_CFG_TICK_SRC_AON_SW (AUX_TIMER_T0CFG_TICK_SRC_AON_SW) +#define AUX_TIMER_CFG_TICK_SRC_AON_PROG_WU (AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU) +#define AUX_TIMER_CFG_TICK_SRC_AIO0 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO0) // AIO_DAT[ 0] +#define AUX_TIMER_CFG_TICK_SRC_AIO1 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO1) // AIO_DAT[ 1] +#define AUX_TIMER_CFG_TICK_SRC_AIO2 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO2) // AIO_DAT[ 2] +#define AUX_TIMER_CFG_TICK_SRC_AIO3 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO3) // AIO_DAT[ 3] +#define AUX_TIMER_CFG_TICK_SRC_AIO4 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO4) // AIO_DAT[ 4] +#define AUX_TIMER_CFG_TICK_SRC_AIO5 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO5) // AIO_DAT[ 5] +#define AUX_TIMER_CFG_TICK_SRC_AIO6 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO6) // AIO_DAT[ 6] +#define AUX_TIMER_CFG_TICK_SRC_AIO7 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO7) // AIO_DAT[ 7] +#define AUX_TIMER_CFG_TICK_SRC_AIO8 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO8) // AIO_DAT[ 8] +#define AUX_TIMER_CFG_TICK_SRC_AIO9 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO9) // AIO_DAT[ 9] +#define AUX_TIMER_CFG_TICK_SRC_AIO10 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO10) // AIO_DAT[10] +#define AUX_TIMER_CFG_TICK_SRC_AIO11 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO11) // AIO_DAT[11] +#define AUX_TIMER_CFG_TICK_SRC_AIO12 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO12) // AIO_DAT[12] +#define AUX_TIMER_CFG_TICK_SRC_AIO13 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO13) // AIO_DAT[13] +#define AUX_TIMER_CFG_TICK_SRC_AIO14 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO14) // AIO_DAT[14] +#define AUX_TIMER_CFG_TICK_SRC_AIO15 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO15) // AIO_DAT[15] +#define AUX_TIMER_CFG_TICK_SRC_ACLK_REF (AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF) // ACLK_REF_i +#define AUX_TIMER_CFG_TICK_SRC_MCU_EVENT (AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT) // MCU event +#define AUX_TIMER_CFG_TICK_SRC_ADC_IRQ (AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ) // DMA done + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ui32Timer +// parameter. +// +//***************************************************************************** +#define AUX_TIMER_0 0x0000FFFF // AUX Timer 0 +#define AUX_TIMER_1 0x00FF0000 // AUX Timer 1 +#define AUX_TIMER_BOTH 0x00FFFFFF // AUX Timer Both 0 and 1 + +//***************************************************************************** +// +// Values that can be passed to AUXTimerPrescaleSet and returned from +// AUXTimerPrescaleGet. +// +//***************************************************************************** +#define AUX_TIMER_PRESCALE_DIV_1 0x00000000 // Prescale division ratio 1 +#define AUX_TIMER_PRESCALE_DIV_2 0x00000001 // Prescale division ratio 2 +#define AUX_TIMER_PRESCALE_DIV_4 0x00000002 // Prescale division ratio 4 +#define AUX_TIMER_PRESCALE_DIV_8 0x00000003 // Prescale division ratio 8 +#define AUX_TIMER_PRESCALE_DIV_16 0x00000004 // Prescale division ratio 16 +#define AUX_TIMER_PRESCALE_DIV_32 0x00000005 // Prescale division ratio 32 +#define AUX_TIMER_PRESCALE_DIV_64 0x00000006 // Prescale division ratio 64 +#define AUX_TIMER_PRESCALE_DIV_128 0x00000007 // Prescale division ratio 128 +#define AUX_TIMER_PRESCALE_DIV_256 0x00000008 // Prescale division ratio 256 +#define AUX_TIMER_PRESCALE_DIV_512 0x00000009 // Prescale division ratio 512 +#define AUX_TIMER_PRESCALE_DIV_1028 0x0000000A // Prescale div. ratio 1028 +#define AUX_TIMER_PRESCALE_DIV_2048 0x0000000B // Prescale div. ratio 2048 +#define AUX_TIMER_PRESCALE_DIV_4096 0x0000000C // Prescale div. ratio 4096 +#define AUX_TIMER_PRESCALE_DIV_8192 0x0000000D // Prescale div. ratio 8192 +#define AUX_TIMER_PRESCALE_DIV_16384 0x0000000E // Prescale div. ratio 16384 +#define AUX_TIMER_PRESCALE_DIV_32768 0x0000000F // Prescale div. ratio 32768 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure AUX timer. +//! +//! This call configures the AUX timer selected by the \c ui32Timer. +//! The timer module is disabled before being configured and is left in the +//! disabled state. +//! +//! The configuration is specified in \c ui32Config as one of the following +//! values: +//! - \ref AUX_TIMER_CFG_ONE_SHOT : One-shot timer. +//! - \ref AUX_TIMER_CFG_PERIODIC : Periodic timer. +//! - \ref AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT : One-shot edge counter. +//! - \ref AUX_TIMER_CFG_PERIODIC_EDGE_COUNT : Periodic edge counter. +//! +//! When configured as timer, the counter is incremented based on the AUX clock +//! after the prescaler. The prescale division ratio is set +//! using \ref AUXTimerPrescaleSet(). +//! +//! When configured as an edge counter the counter is incremented only on edges +//! of the selected event. +//! The polarity of the event is selected by: +//! - \ref AUX_TIMER_CFG_RISING_EDGE : rising edge trigger +//! - \ref AUX_TIMER_CFG_FALLING_EDGE : falling edge trigger +//! +//! The event source is selected as one of the following defines: +//! - \ref AUX_TIMER_CFG_TICK_SRC_RTC_EVENT +//! - \ref AUX_TIMER_CFG_TICK_SRC_CMP_A +//! - \ref AUX_TIMER_CFG_TICK_SRC_CMP_B +//! - \ref AUX_TIMER_CFG_TICK_SRC_TDCDONE +//! - \ref AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT +//! - \ref AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT +//! - \ref AUX_TIMER_CFG_TICK_SRC_SMPH_RELEASE +//! - \ref AUX_TIMER_CFG_TICK_SRC_ADC_DONE +//! - \ref AUX_TIMER_CFG_TICK_SRC_RTC_4KHZ +//! - \ref AUX_TIMER_CFG_TICK_SRC_OBSMUX0 +//! - \ref AUX_TIMER_CFG_TICK_SRC_OBSMUX1 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AON_SW +//! - \ref AUX_TIMER_CFG_TICK_SRC_AON_PROG_WU +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO0 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO1 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO2 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO3 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO4 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO5 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO6 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO7 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO8 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO9 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO10 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO11 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO12 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO13 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO14 +//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO15 +//! - \ref AUX_TIMER_CFG_TICK_SRC_ACLK_REF +//! - \ref AUX_TIMER_CFG_TICK_SRC_MCU_EVENT +//! - \ref AUX_TIMER_CFG_TICK_SRC_ADC_IRQ +//! +//! The mode, event polarity and event source are configured by setting the +//! \c ui32Config parameter as the bitwise OR of the various settings. +//! Example: (\ref AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT | +//! \ref AUX_TIMER_CFG_RISING_EDGE | +//! \ref AUX_TIMER_CFG_TICK_SRC_RTC_EVENT). +//! +//! \note When used as an edge counter the prescaler should be set to +//! \ref AUX_TIMER_PRESCALE_DIV_1. +//! +//! \note A timer can not trigger itself thus timer 0 can \b not use +//! \ref AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT and timer 1 can \b not use +//! \ref AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT. +//! +//! \param ui32Timer is the timer to configure. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! - \ref AUX_TIMER_BOTH +//! \param ui32Config is the timer configuration. +//! +//! \return None +//! +//! \sa \ref AUXTimerPrescaleSet() +// +//***************************************************************************** +extern void AUXTimerConfigure(uint32_t ui32Timer, uint32_t ui32Config); + +//***************************************************************************** +// +//! \brief Start AUX timer(s). +//! +//! This call starts the selected AUX timer(s). +//! +//! \note The counter will start counting up from zero. +//! +//! \param ui32Timer is the timer to start. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! - \ref AUX_TIMER_BOTH +//! +//! \return None +//! +//! \sa \ref AUXTimerStop() +// +//***************************************************************************** +extern void AUXTimerStart(uint32_t ui32Timer); + +//***************************************************************************** +// +//! \brief Stop AUX timer(s). +//! +//! This call stops the selected AUX timer(s). +//! +//! \param ui32Timer is the timer to stop. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! - \ref AUX_TIMER_BOTH +//! +//! \return None +//! +//! \sa \ref AUXTimerStart() +// +//***************************************************************************** +extern void AUXTimerStop(uint32_t ui32Timer); + +//***************************************************************************** +// +//! \brief Set AUX timer target value. +//! +//! The timer counts from zero to the target value. When target value is +//! reached an event is generated. +//! +//! \param ui32Timer is the timer to set the target value for. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! \param ui32Target is the timer target value. +//! - For \ref AUX_TIMER_0 the target value must be an integer in the range 0..65535 (16 bit). +//! - For \ref AUX_TIMER_1 the target value must be an integer in the range 0..255 (8 bit). +//! +//! \return None +//! +//! \sa \ref AUXTimerTargetValGet() +// +//***************************************************************************** +__STATIC_INLINE void +AUXTimerTargetValSet(uint32_t ui32Timer, uint32_t ui32Target) +{ + uint32_t ui32Addr; + + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); + ASSERT(((ui32Timer & AUX_TIMER_0) && (ui32Target <= 65535)) || + ((ui32Timer & AUX_TIMER_1) && (ui32Target <= 255))); + + ui32Addr = (ui32Timer & AUX_TIMER_0) ? + (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : + (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET); + + HWREG(ui32Addr) = ui32Target; +} + +//***************************************************************************** +// +//! \brief Get AUX timer target value. +//! +//! The timer counts from zero to the target value. When target value is +//! reached an event is generated. This function returns the programmed target +//! value for the specified timer. +//! +//! \param ui32Timer is the timer to get the target value from. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! +//! \return Returns target value for the specified timer +//! +//! \sa \ref AUXTimerTargetValSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTimerTargetValGet(uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); + + return(HWREG((ui32Timer & AUX_TIMER_0) ? + (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : + (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET))); +} + +//***************************************************************************** +// +//! \brief Set AUX timer prescale value. +//! +//! When configured as timer, the counter is incremented based on the AUX clock +//! after the prescaler. +//! +//! \note Setting prescale value is \b not advised when the timer is running. +//! +//! \note When timer is used as an edge counter the prescaler should be +//! set to \ref AUX_TIMER_PRESCALE_DIV_1. +//! +//! \param ui32Timer is the timer to set the prescale on. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! - \ref AUX_TIMER_BOTH +//! \param ui32PrescaleDiv is the prescaler division ratio. +//! - \ref AUX_TIMER_PRESCALE_DIV_1 : Prescale division ratio 1 +//! - \ref AUX_TIMER_PRESCALE_DIV_2 : Prescale division ratio 2 +//! - \ref AUX_TIMER_PRESCALE_DIV_4 : Prescale division ratio 4 +//! - \ref AUX_TIMER_PRESCALE_DIV_16 : Prescale division ratio 16 +//! - \ref AUX_TIMER_PRESCALE_DIV_32 : Prescale division ratio 32 +//! - \ref AUX_TIMER_PRESCALE_DIV_64 : Prescale division ratio 64 +//! - \ref AUX_TIMER_PRESCALE_DIV_128 : Prescale division ratio 128 +//! - \ref AUX_TIMER_PRESCALE_DIV_256 : Prescale division ratio 256 +//! - \ref AUX_TIMER_PRESCALE_DIV_1028 : Prescale division ratio 1028 +//! - \ref AUX_TIMER_PRESCALE_DIV_2048 : Prescale division ratio 2048 +//! - \ref AUX_TIMER_PRESCALE_DIV_4096 : Prescale division ratio 4096 +//! - \ref AUX_TIMER_PRESCALE_DIV_8192 : Prescale division ratio 8192 +//! - \ref AUX_TIMER_PRESCALE_DIV_16384 : Prescale division ratio 16384 +//! - \ref AUX_TIMER_PRESCALE_DIV_32768 : Prescale division ratio 32768 +//! +//! \return None +//! +//! \sa \ref AUXTimerPrescaleGet() +// +//***************************************************************************** +extern void AUXTimerPrescaleSet(uint32_t ui32Timer, uint32_t ui32PrescaleDiv); + +//***************************************************************************** +// +//! \brief Get AUX timer prescale value. +//! +//! When configured as timer, the counter is incremented based on the AUX clock +//! after the prescaler. This call returns the setting of the prescale divide +//! ratio for the specified timer. +//! +//! \param ui32Timer is the timer to get the prescale value from. +//! - \ref AUX_TIMER_0 +//! - \ref AUX_TIMER_1 +//! +//! \return Returns the prescaler division ratio as one of the following values: +//! - \ref AUX_TIMER_PRESCALE_DIV_1 : Prescale division ratio 1 +//! - \ref AUX_TIMER_PRESCALE_DIV_2 : Prescale division ratio 2 +//! - \ref AUX_TIMER_PRESCALE_DIV_4 : Prescale division ratio 4 +//! - \ref AUX_TIMER_PRESCALE_DIV_16 : Prescale division ratio 16 +//! - \ref AUX_TIMER_PRESCALE_DIV_32 : Prescale division ratio 32 +//! - \ref AUX_TIMER_PRESCALE_DIV_64 : Prescale division ratio 64 +//! - \ref AUX_TIMER_PRESCALE_DIV_128 : Prescale division ratio 128 +//! - \ref AUX_TIMER_PRESCALE_DIV_256 : Prescale division ratio 256 +//! - \ref AUX_TIMER_PRESCALE_DIV_1028 : Prescale division ratio 1028 +//! - \ref AUX_TIMER_PRESCALE_DIV_2048 : Prescale division ratio 2048 +//! - \ref AUX_TIMER_PRESCALE_DIV_4096 : Prescale division ratio 4096 +//! - \ref AUX_TIMER_PRESCALE_DIV_8192 : Prescale division ratio 8192 +//! - \ref AUX_TIMER_PRESCALE_DIV_16384 : Prescale division ratio 16384 +//! - \ref AUX_TIMER_PRESCALE_DIV_32768 : Prescale division ratio 32768 +//! +//! \sa \ref AUXTimerPrescaleSet() +// +//***************************************************************************** +extern uint32_t AUXTimerPrescaleGet(uint32_t ui32Timer); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXTimerConfigure + #undef AUXTimerConfigure + #define AUXTimerConfigure ROM_AUXTimerConfigure + #endif + #ifdef ROM_AUXTimerStart + #undef AUXTimerStart + #define AUXTimerStart ROM_AUXTimerStart + #endif + #ifdef ROM_AUXTimerStop + #undef AUXTimerStop + #define AUXTimerStop ROM_AUXTimerStop + #endif + #ifdef ROM_AUXTimerPrescaleSet + #undef AUXTimerPrescaleSet + #define AUXTimerPrescaleSet ROM_AUXTimerPrescaleSet + #endif + #ifdef ROM_AUXTimerPrescaleGet + #undef AUXTimerPrescaleGet + #define AUXTimerPrescaleGet ROM_AUXTimerPrescaleGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_TIMER_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_wuc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_wuc.c new file mode 100644 index 0000000..b893e52 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_wuc.c @@ -0,0 +1,283 @@ +/****************************************************************************** +* Filename: aux_wuc.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the AUX Wakeup Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_wuc.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXWUCClockEnable + #define AUXWUCClockEnable NOROM_AUXWUCClockEnable + #undef AUXWUCClockDisable + #define AUXWUCClockDisable NOROM_AUXWUCClockDisable + #undef AUXWUCClockStatus + #define AUXWUCClockStatus NOROM_AUXWUCClockStatus + #undef AUXWUCPowerCtrl + #define AUXWUCPowerCtrl NOROM_AUXWUCPowerCtrl +#endif + +//**************************************************************************** +// +//! Enable clocks for peripherals in the AUX domain +// +//**************************************************************************** +void +AUXWUCClockEnable(uint32_t ui32Clocks) +{ + // Check the arguments. + ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || + (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || + (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || + (ui32Clocks & AUX_WUC_ANAIF_CLOCK) || + (ui32Clocks & AUX_WUC_TIMER_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || + (ui32Clocks & AUX_WUC_SMPH_CLOCK) || + (ui32Clocks & AUX_WUC_TDC_CLOCK) || + (ui32Clocks & AUX_WUC_ADC_CLOCK) || + (ui32Clocks & AUX_WUC_REF_CLOCK)); + + // Enable some of the clocks in the clock register. + HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) |= (ui32Clocks & + AUX_WUC_MODCLK_MASK); + + // Check the rest. + if(ui32Clocks & AUX_WUC_ADC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = + AUX_WUC_ADCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_TDC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) = + AUX_WUC_TDCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_REF_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = + AUX_WUC_REFCLKCTL_REQ; + } +} + +//**************************************************************************** +// +//! Disable clocks for peripherals in the AUX domain +// +//**************************************************************************** +void +AUXWUCClockDisable(uint32_t ui32Clocks) +{ + // Check the arguments. + ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || + (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || + (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || + (ui32Clocks & AUX_WUC_ANAIF_CLOCK) || + (ui32Clocks & AUX_WUC_TIMER_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || + (ui32Clocks & AUX_WUC_SMPH_CLOCK) || + (ui32Clocks & AUX_WUC_TDC_CLOCK) || + (ui32Clocks & AUX_WUC_ADC_CLOCK) || + (ui32Clocks & AUX_WUC_REF_CLOCK)); + + // Disable some of the clocks in the clock register. + HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) &= ~(ui32Clocks & + AUX_WUC_MODCLK_MASK); + + // Check the rest. + if(ui32Clocks & AUX_WUC_ADC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) &= + ~AUX_WUC_ADCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_TDC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) &= + ~AUX_WUC_TDCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_REF_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) &= + ~AUX_WUC_REFCLKCTL_REQ; + } +} + +//**************************************************************************** +// +//! Get the status of a clock +// +//**************************************************************************** +uint32_t +AUXWUCClockStatus(uint32_t ui32Clocks) +{ + bool bClockStatus; + uint32_t ui32ClockRegister; + + // Check the arguments. + ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || + (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || + (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || + (ui32Clocks & AUX_WUC_ANAIF_CLOCK) || + (ui32Clocks & AUX_WUC_TIMER_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || + (ui32Clocks & AUX_WUC_SMPH_CLOCK) || + (ui32Clocks & AUX_WUC_TDC_CLOCK) || + (ui32Clocks & AUX_WUC_ADC_CLOCK) || + (ui32Clocks & AUX_WUC_REF_CLOCK)); + + bClockStatus = true; + + // Read the status registers. + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0); + + // Check all requested clocks + if(ui32Clocks & AUX_WUC_ADI_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AUX_ADI4 ? + true : false); + } + if(ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AUX_DDI0_OSC ? + true : false); + } + if(ui32Clocks & AUX_WUC_TDCIF_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_TDC ? + true : false); + } + if(ui32Clocks & AUX_WUC_ANAIF_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_ANAIF ? + true : false); + } + if(ui32Clocks & AUX_WUC_TIMER_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_TIMER ? + true : false); + } + if(ui32Clocks & AUX_WUC_AIODIO0_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AIODIO0 ? + true : false); + } + if(ui32Clocks & AUX_WUC_AIODIO1_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AIODIO1 ? + true : false); + } + if(ui32Clocks & AUX_WUC_SMPH_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_SMPH ? + true : false); + } + if(ui32Clocks & AUX_WUC_ADC_CLOCK) + { + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL); + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_ADCCLKCTL_ACK ? + true : false); + } + if(ui32Clocks & AUX_WUC_TDC_CLOCK) + { + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL); + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_TDCCLKCTL_ACK ? + true : false); + } + if(ui32Clocks & AUX_WUC_REF_CLOCK) + { + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL); + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_REFCLKCTL_ACK ? + true : false); + } + + // Return the clock status. + return bClockStatus ? AUX_WUC_CLOCK_READY : AUX_WUC_CLOCK_OFF; +} + +//**************************************************************************** +// +//! Control the power to the AUX domain +// +//**************************************************************************** +void +AUXWUCPowerCtrl(uint32_t ui32PowerMode) +{ + // Check the arguments. + ASSERT((ui32PowerMode == AUX_WUC_POWER_OFF) || + (ui32PowerMode == AUX_WUC_POWER_DOWN) || + (ui32PowerMode == AUX_WUC_POWER_ACTIVE)); + + // Power on/off. + if(ui32PowerMode == AUX_WUC_POWER_OFF) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWROFFREQ) = AUX_WUC_PWROFFREQ_REQ; + HWREG(AUX_WUC_BASE + AUX_WUC_O_MCUBUSCTL) = AUX_WUC_MCUBUSCTL_DISCONNECT_REQ; + return; + } + else + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWROFFREQ) = 0x0; + } + + // Power down/active. + if(ui32PowerMode == AUX_WUC_POWER_DOWN) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWRDWNREQ) = AUX_WUC_PWRDWNREQ_REQ; + HWREG(AUX_WUC_BASE + AUX_WUC_O_MCUBUSCTL) = AUX_WUC_MCUBUSCTL_DISCONNECT_REQ; + } + else + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWRDWNREQ) = 0x0; + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_wuc.h new file mode 100644 index 0000000..532d1e9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_wuc.h @@ -0,0 +1,347 @@ +/****************************************************************************** +* Filename: aon_wuc.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Defines and prototypes for the AUX Wakeup Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//**************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxwuc_api +//! @{ +// +//**************************************************************************** + +#ifndef __AUX_WUC_H__ +#define __AUX_WUC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aux_wuc.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXWUCClockEnable NOROM_AUXWUCClockEnable + #define AUXWUCClockDisable NOROM_AUXWUCClockDisable + #define AUXWUCClockStatus NOROM_AUXWUCClockStatus + #define AUXWUCPowerCtrl NOROM_AUXWUCPowerCtrl +#endif + +//***************************************************************************** +// +// Defines for the AUX power control. +// +//***************************************************************************** +#define AUX_WUC_POWER_OFF 0x00000001 +#define AUX_WUC_POWER_DOWN 0x00000002 +#define AUX_WUC_POWER_ACTIVE 0x00000004 + +//***************************************************************************** +// +// Defines for the AUX peripherals clock control. +// +//***************************************************************************** +#define AUX_WUC_SMPH_CLOCK (AUX_WUC_MODCLKEN0_SMPH_EN) +#define AUX_WUC_AIODIO0_CLOCK (AUX_WUC_MODCLKEN0_AIODIO0_EN) +#define AUX_WUC_AIODIO1_CLOCK (AUX_WUC_MODCLKEN0_AIODIO1_EN) +#define AUX_WUC_TIMER_CLOCK (AUX_WUC_MODCLKEN0_TIMER_EN) +#define AUX_WUC_ANAIF_CLOCK (AUX_WUC_MODCLKEN0_ANAIF_EN) +#define AUX_WUC_TDCIF_CLOCK (AUX_WUC_MODCLKEN0_TDC_EN) +#define AUX_WUC_OSCCTRL_CLOCK (AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN) +#define AUX_WUC_ADI_CLOCK (AUX_WUC_MODCLKEN0_AUX_ADI4_EN) +#define AUX_WUC_MODCLK_MASK 0x000000FF + +#define AUX_WUC_TDC_CLOCK 0x00000100 +#define AUX_WUC_ADC_CLOCK 0x00000200 +#define AUX_WUC_REF_CLOCK 0x00000400 + +#define AUX_WUC_CLOCK_OFF 0x00000000 +#define AUX_WUC_CLOCK_UNSTABLE 0x00000001 +#define AUX_WUC_CLOCK_READY 0x00000011 + +#define AUX_WUC_CLOCK_HIFREQ 0x00000000 +#define AUX_WUC_CLOCK_LOFREQ 0x00000001 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//**************************************************************************** +// +//! \brief Enable clocks for peripherals in the AUX domain. +//! +//! Use this function to enable specific clocks in the AUX domain. +//! +//! \param ui32Clocks is a bitmap of clocks to enable. +//! Use a bitwise OR combination of the following values: +//! - \ref AUX_WUC_ADI_CLOCK +//! - \ref AUX_WUC_OSCCTRL_CLOCK +//! - \ref AUX_WUC_TDCIF_CLOCK +//! - \ref AUX_WUC_ANAIF_CLOCK +//! - \ref AUX_WUC_TIMER_CLOCK +//! - \ref AUX_WUC_AIODIO0_CLOCK +//! - \ref AUX_WUC_AIODIO1_CLOCK +//! - \ref AUX_WUC_SMPH_CLOCK +//! - \ref AUX_WUC_TDC_CLOCK +//! - \ref AUX_WUC_ADC_CLOCK +//! - \ref AUX_WUC_REF_CLOCK +//! +//! \return None +//! +//! \sa \ref AUXWUCClockDisable() +// +//**************************************************************************** +extern void AUXWUCClockEnable(uint32_t ui32Clocks); + +//**************************************************************************** +// +//! \brief Disable clocks for peripherals in the AUX domain. +//! +//! Use this function to enable specific clocks in the AUX domain. +//! +//! \param ui32Clocks a bitmap of clocks to disable. +//! Use a bitwise OR combination of the following values: +//! - \ref AUX_WUC_ADI_CLOCK +//! - \ref AUX_WUC_OSCCTRL_CLOCK +//! - \ref AUX_WUC_TDCIF_CLOCK +//! - \ref AUX_WUC_ANAIF_CLOCK +//! - \ref AUX_WUC_TIMER_CLOCK +//! - \ref AUX_WUC_AIODIO0_CLOCK +//! - \ref AUX_WUC_AIODIO1_CLOCK +//! - \ref AUX_WUC_SMPH_CLOCK +//! - \ref AUX_WUC_TDC_CLOCK +//! - \ref AUX_WUC_ADC_CLOCK +//! - \ref AUX_WUC_REF_CLOCK +//! +//! \return None +//! +//! \sa \ref AUXWUCClockEnable() +// +//**************************************************************************** +extern void AUXWUCClockDisable(uint32_t ui32Clocks); + +//**************************************************************************** +// +//! \brief Get the status of a clock. +//! +//! Use this function to poll the status of a specific clock in the AUX +//! domain. +//! +//! \param ui32Clocks is the clock for which to return status. +//! - \ref AUX_WUC_ADI_CLOCK +//! - \ref AUX_WUC_OSCCTRL_CLOCK +//! - \ref AUX_WUC_TDCIF_CLOCK +//! - \ref AUX_WUC_ANAIF_CLOCK +//! - \ref AUX_WUC_TIMER_CLOCK +//! - \ref AUX_WUC_AIODIO0_CLOCK +//! - \ref AUX_WUC_AIODIO1_CLOCK +//! - \ref AUX_WUC_SMPH_CLOCK +//! - \ref AUX_WUC_TDC_CLOCK +//! - \ref AUX_WUC_ADC_CLOCK +//! - \ref AUX_WUC_REF_CLOCK +//! +//! \return Returns the status of the clock as one of two states: +//! - \ref AUX_WUC_CLOCK_OFF +//! - \ref AUX_WUC_CLOCK_READY +// +//**************************************************************************** +extern uint32_t AUXWUCClockStatus(uint32_t ui32Clocks); + +//**************************************************************************** +// +//! \brief Request a high or low frequency clock source. +//! +//! Using this function it is possible to make a request to the System +//! Control to use a high or low frequency clock as clock source for the AUX +//! domain. +//! +//! \note A low frequency clock is always 32 kHz, while a high frequency clock +//! is really a large span of frequencies determined by the clock source (High +//! Frequency or Medium Frequency) and the setting for the clock divider for +//! the AUX domain in the System Control. +//! +//! \param ui32ClockFreq determines the clock source frequency. +//! - \ref AUX_WUC_CLOCK_LOFREQ : Request low frequency clock source for AUX domain. +//! - \ref AUX_WUC_CLOCK_HIFREQ : Request high frequency clock source for AUX domain. +//! +//! \return +// +//**************************************************************************** +__STATIC_INLINE void +AUXWUCClockFreqReq(uint32_t ui32ClockFreq) +{ + // Check the arguments. + ASSERT((ui32ClockFreq == AUX_WUC_CLOCK_HIFREQ) || + (ui32ClockFreq == AUX_WUC_CLOCK_LOFREQ)); + + // Set the request + HWREG(AUX_WUC_BASE + AUX_WUC_O_CLKLFREQ) = ui32ClockFreq; +} + +//**************************************************************************** +// +//! \brief Control the power to the AUX domain. +//! +//! Use this function to set the power mode of the entire AUX domain. +//! +//! \param ui32PowerMode control the desired power mode for the AUX domain. +//! The domain has three different power modes: +//! - \ref AUX_WUC_POWER_OFF +//! - \ref AUX_WUC_POWER_DOWN +//! - \ref AUX_WUC_POWER_ACTIVE +//! +//! \return None +// +//**************************************************************************** +extern void AUXWUCPowerCtrl(uint32_t ui32PowerMode); + +//***************************************************************************** +// +//! \brief Freeze the AUX IOs. +//! +//! To retain the values of the output IOs during a powerdown of the AUX domain +//! all IO latches in the AUX domain should be frozen in their current state. +//! This ensures that software can regain control of the IOs after a powerdown +//! without the IOs first falling back to the default values (i.e. input and +//! pull-up). +//! +//! \return None +//! +//! \sa AUXWUCFreezeDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AUXWUCFreezeEnable(void) +{ + // Set the AUX WUC latches as static. + HWREG(AUX_WUC_BASE + AUX_WUC_O_AUXIOLATCH) = 0x0; +} + +//***************************************************************************** +// +//! \brief Unfreeze the AUX IOs. +//! +//! When restarting the AUX domain after it has entered powerdown mode, the +//! software can regain control of the IOs by setting the IO latches as +//! transparent. +//! +//! \note The IOs should not be unfrozen before software has restored +//! the functionality of the IO. +//! +//! \return None +//! +//! \sa AUXWUCFreezeEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AUXWUCFreezeDisable(void) +{ + // Set the AUX WUC latches as transparent. + HWREG(AUX_WUC_BASE + AUX_WUC_O_AUXIOLATCH) = AUX_WUC_AUXIOLATCH_EN; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXWUCClockEnable + #undef AUXWUCClockEnable + #define AUXWUCClockEnable ROM_AUXWUCClockEnable + #endif + #ifdef ROM_AUXWUCClockDisable + #undef AUXWUCClockDisable + #define AUXWUCClockDisable ROM_AUXWUCClockDisable + #endif + #ifdef ROM_AUXWUCClockStatus + #undef AUXWUCClockStatus + #define AUXWUCClockStatus ROM_AUXWUCClockStatus + #endif + #ifdef ROM_AUXWUCPowerCtrl + #undef AUXWUCPowerCtrl + #define AUXWUCPowerCtrl ROM_AUXWUCPowerCtrl + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_WUC_H__ + +//**************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//**************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/bin/gcc/driverlib.lib b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/bin/gcc/driverlib.lib new file mode 100644 index 0000000..7089aaf Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/bin/gcc/driverlib.lib differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/bin/iar/driverlib.lib b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/bin/iar/driverlib.lib new file mode 100644 index 0000000..bab8ddd Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/bin/iar/driverlib.lib differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread.c new file mode 100644 index 0000000..c50f42f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: ccfgread.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: API for reading CCFG. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ccfgread.h" + +// See ccfgread.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread.h new file mode 100644 index 0000000..e3397e9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread.h @@ -0,0 +1,187 @@ +/****************************************************************************** +* Filename: ccfgread.h +* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) +* Revision: 47152 +* +* Description: API for reading CCFG. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup ccfgread_api +//! @{ +// +//***************************************************************************** + +#ifndef __CCFGREAD_H__ +#define __CCFGREAD_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ccfg.h" + +//***************************************************************************** +// +// General constants and defines +// +//***************************************************************************** + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Read DIS_GPRAM from CCFG. +//! +//! \return Value of CCFG field CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM +// +//***************************************************************************** +__STATIC_INLINE bool +CCFGRead_DIS_GPRAM( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) >> + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) ; +} + +//***************************************************************************** +// +//! \brief Read EXT_LF_CLK_DIO from CCFG. +//! +//! \return Value of CCFG field CCFG_EXT_LF_CLK_DIO +// +//***************************************************************************** +__STATIC_INLINE bool +CCFGRead_EXT_LF_CLK_DIO( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ) & + CCFG_EXT_LF_CLK_DIO_M ) >> + CCFG_EXT_LF_CLK_DIO_S ) ; +} + +//***************************************************************************** +// +// Defines the possible values returned from CCFGRead_SCLK_LF_OPTION() +// +//***************************************************************************** +#define CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_RCOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) + +//***************************************************************************** +// +//! \brief Read SCLK_LF_OPTION from CCFG. +//! +//! \return Returns the value of the CCFG field CCFG_MODE_CONF_SCLK_LF_OPTION field. +//! Returns one of the following: +//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF +//! - \ref CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF +//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_LF +//! - \ref CCFGREAD_SCLK_LF_OPTION_RCOSC_LF +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CCFGRead_SCLK_LF_OPTION( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & + CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> + CCFG_MODE_CONF_SCLK_LF_OPTION_S ) ; +} + +//***************************************************************************** +// +// Defines the possible values returned from CCFGRead_XOSC_FREQ() +// +//***************************************************************************** +#define CCFGREAD_XOSC_FREQ_24M ( CCFG_MODE_CONF_XOSC_FREQ_24M >> CCFG_MODE_CONF_XOSC_FREQ_S ) +#define CCFGREAD_XOSC_FREQ_48M ( CCFG_MODE_CONF_XOSC_FREQ_48M >> CCFG_MODE_CONF_XOSC_FREQ_S ) +#define CCFGREAD_XOSC_FREQ_HPOSC ( CCFG_MODE_CONF_XOSC_FREQ_HPOSC >> CCFG_MODE_CONF_XOSC_FREQ_S ) + +//***************************************************************************** +// +//! \brief Read XOSC_FREQ setting CCFG. +//! +//! \return Returns the value of the CCFG_MODE_CONF_XOSC_FREQ field. +//! Returns one of the following: +//! - \ref CCFGREAD_XOSC_FREQ_24M +//! - \ref CCFGREAD_XOSC_FREQ_48M +//! - \ref CCFGREAD_XOSC_FREQ_HPOSC +//! +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CCFGRead_XOSC_FREQ( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & + CCFG_MODE_CONF_XOSC_FREQ_M ) >> + CCFG_MODE_CONF_XOSC_FREQ_S ) ; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_SMPH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread_doc.h new file mode 100644 index 0000000..f3175fb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread_doc.h @@ -0,0 +1,51 @@ +/****************************************************************************** +* Filename: ccfgread_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup ccfgread_api +//! @{ +//! \section sec_ccfgread Introduction +//! +//! The values of customer configuration (CCFG) settings in flash are determined by ccfg.c and typically +//! a user application does not need to read these CCFG values as they are used mainly during ROM boot +//! and device trimming. However, a subset of the CCFG settings need to be read by application +//! code thus DriverLib provides this API to allow easy read access to these specific settings. +//! +//! The remaining settings not accessible through this API can of course be read directly at the CCFG +//! addresses in the flash (starting at CCFG_BASE) using the HWREG macro and the provided defines. +//! CCFG settings are documented as part of the register descriptions in the CPU memory map. +//! +//! \note CCFG settings are located in flash and should be considered read-only from an application +//! point-of-view. +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/chipinfo.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/chipinfo.c new file mode 100644 index 0000000..2a75a8f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/chipinfo.c @@ -0,0 +1,211 @@ +/****************************************************************************** +* Filename: chipinfo.c +* Revised: 2018-08-17 09:28:06 +0200 (Fri, 17 Aug 2018) +* Revision: 52354 +* +* Description: Collection of functions returning chip information. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "chipinfo.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef ChipInfo_GetSupportedProtocol_BV + #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV + #undef ChipInfo_GetPackageType + #define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType + #undef ChipInfo_GetChipType + #define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType + #undef ChipInfo_GetChipFamily + #define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily + #undef ChipInfo_GetHwRevision + #define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision + #undef ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated + #define ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated +#endif + +//***************************************************************************** +// +// ChipInfo_GetSupportedProtocol_BV() +// +//***************************************************************************** +ProtocolBitVector_t +ChipInfo_GetSupportedProtocol_BV( void ) +{ + return ((ProtocolBitVector_t)( HWREG( PRCM_BASE + 0x1D4 ) & 0x0E )); +} + +//***************************************************************************** +// +// ChipInfo_GetPackageType() +// +//***************************************************************************** +PackageType_t +ChipInfo_GetPackageType( void ) +{ + PackageType_t packType = (PackageType_t)(( + HWREG( FCFG1_BASE + FCFG1_O_USER_ID ) & + FCFG1_USER_ID_PKG_M ) >> + FCFG1_USER_ID_PKG_S ) ; + + if (( packType < PACKAGE_4x4 ) || + ( packType > PACKAGE_7x7_Q1 ) ) + { + packType = PACKAGE_Unknown; + } + + return ( packType ); +} + +//***************************************************************************** +// +// ChipInfo_GetChipFamily() +// +//***************************************************************************** +ChipFamily_t +ChipInfo_GetChipFamily( void ) +{ + uint32_t waferId ; + ChipFamily_t chipFam = FAMILY_Unknown ; + + waferId = (( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) & + FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M ) >> + FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S ) ; + + if ( waferId == 0xB99A ) { + if ( ChipInfo_GetDeviceIdHwRevCode() == 0xB ) { + chipFam = FAMILY_CC26x0R2 ; + } else { + chipFam = FAMILY_CC26x0 ; + } + } + + return ( chipFam ); +} + +//***************************************************************************** +// +// ChipInfo_GetChipType() +// +//***************************************************************************** +ChipType_t +ChipInfo_GetChipType( void ) +{ + ChipType_t chipType = CHIP_TYPE_Unknown ; + ChipFamily_t chipFam = ChipInfo_GetChipFamily() ; + uint32_t fcfg1UserId = ChipInfo_GetUserId() ; + uint32_t fcfg1Protocol = (( fcfg1UserId & FCFG1_USER_ID_PROTOCOL_M ) >> + FCFG1_USER_ID_PROTOCOL_S ) ; + + if ( chipFam == FAMILY_CC26x0 ) { + switch ( fcfg1Protocol ) { + case 0x2 : + chipType = CHIP_TYPE_CC2620 ; + break; + case 0x4 : + case 0xC : + chipType = CHIP_TYPE_CC2630 ; + break; + case 0x1 : + case 0x9 : + chipType = CHIP_TYPE_CC2640 ; + if ( fcfg1UserId & ( 1 << 23 )) { + chipType = CHIP_TYPE_CUSTOM_1 ; + } + break; + case 0xF : + chipType = CHIP_TYPE_CC2650 ; + if ( fcfg1UserId & ( 1 << 24 )) { + chipType = CHIP_TYPE_CUSTOM_0 ; + } + break; + } + } + + return ( chipType ); +} + +//***************************************************************************** +// +// ChipInfo_GetHwRevision() +// +//***************************************************************************** +HwRevision_t +ChipInfo_GetHwRevision( void ) +{ + HwRevision_t hwRev = HWREV_Unknown ; + uint32_t fcfg1Rev = ChipInfo_GetDeviceIdHwRevCode() ; + uint32_t minorHwRev = ChipInfo_GetMinorHwRev() ; + ChipFamily_t chipFam = ChipInfo_GetChipFamily() ; + + if ( chipFam == FAMILY_CC26x0 ) { + switch ( fcfg1Rev ) { + case 1 : // CC26x0 PG1.0 + hwRev = HWREV_1_0; + break; + case 3 : // CC26x0 PG2.0 + hwRev = HWREV_2_0; + break; + case 7 : // CC26x0 PG2.1 + hwRev = HWREV_2_1; + break; + case 8 : // CC26x0 PG2.2 (or later) + hwRev = (HwRevision_t)(((uint32_t)HWREV_2_2 ) + minorHwRev ); + break; + } + } + + return ( hwRev ); +} + +//***************************************************************************** +// ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated() +//***************************************************************************** +void +ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated( void ) +{ + if (( ! ChipInfo_ChipFamilyIs_CC26x0() ) || + ( ! ChipInfo_HwRevisionIs_GTEQ_2_2() ) ) + { + while(1) + { + // This driverlib version is for CC26x0 PG2.2 and later + // Do nothing - stay here forever + } + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/chipinfo.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/chipinfo.h new file mode 100644 index 0000000..2b4a258 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/chipinfo.h @@ -0,0 +1,685 @@ +/****************************************************************************** +* Filename: chipinfo.h +* Revised: 2018-06-18 10:26:12 +0200 (Mon, 18 Jun 2018) +* Revision: 52189 +* +* Description: Collection of functions returning chip information. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup ChipInfo +//! @{ +// +//***************************************************************************** + +#ifndef __CHIP_INFO_H__ +#define __CHIP_INFO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_fcfg1.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV + #define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType + #define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType + #define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily + #define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision + #define ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated +#endif + +//***************************************************************************** +// +//! \brief Enumeration identifying the protocols supported. +//! +//! \note +//! This is a bit vector enumeration that indicates supported protocols. +//! E.g: 0x06 means that the chip supports both BLE and IEEE 802.15.4 +// +//***************************************************************************** +typedef enum { + PROTOCOL_Unknown = 0 , //!< None of the known protocols are supported. + PROTOCOLBIT_BLE = 0x02, //!< Bit[1] set, indicates that Bluetooth Low Energy is supported. + PROTOCOLBIT_IEEE_802_15_4 = 0x04, //!< Bit[2] set, indicates that IEEE 802.15.4 is supported. + PROTOCOLBIT_Proprietary = 0x08 //!< Bit[3] set, indicates that proprietary protocols are supported. +} ProtocolBitVector_t; + +//***************************************************************************** +// +//! \brief Returns bit vector showing supported protocols. +//! +//! \return +//! Returns \ref ProtocolBitVector_t which is a bit vector indicating supported protocols. +// +//***************************************************************************** +extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV( void ); + +//***************************************************************************** +// +//! \brief Returns true if the chip supports the BLE protocol. +//! +//! \return +//! Returns \c true if supporting the BLE protocol, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_SupportsBLE( void ) +{ + return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_BLE ) != 0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if the chip supports the IEEE 802.15.4 protocol. +//! +//! \return +//! Returns \c true if supporting the IEEE 802.15.4 protocol, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_SupportsIEEE_802_15_4( void ) +{ + return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_IEEE_802_15_4 ) != 0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if the chip supports proprietary protocols. +//! +//! \return +//! Returns \c true if supporting proprietary protocols, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_SupportsPROPRIETARY( void ) +{ + return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_Proprietary ) != 0 ); +} + +//***************************************************************************** +// +//! \brief Package type enumeration +//! +//! \note +//! Packages available for a specific device are shown in the device datasheet. +// +//***************************************************************************** +typedef enum { + PACKAGE_Unknown = -1, //!< -1 means that current package type is unknown. + PACKAGE_4x4 = 0, //!< 0 means that this is a 4x4 mm QFN (RHB) package. + PACKAGE_5x5 = 1, //!< 1 means that this is a 5x5 mm QFN (RSM) package. + PACKAGE_7x7 = 2, //!< 2 means that this is a 7x7 mm QFN (RGZ) package. + PACKAGE_WAFER = 3, //!< 3 means that this is a wafer sale package (naked die). + PACKAGE_WCSP = 4, //!< 4 means that this is a 2.7x2.7 mm WCSP (YFV). + PACKAGE_7x7_Q1 = 5 //!< 5 means that this is a 7x7 mm QFN package with Wettable Flanks. +} PackageType_t; + +//***************************************************************************** +// +//! \brief Returns package type. +//! +//! \return +//! Returns \ref PackageType_t +// +//***************************************************************************** +extern PackageType_t ChipInfo_GetPackageType( void ); + +//***************************************************************************** +// +//! \brief Returns true if this is a 4x4mm chip. +//! +//! \return +//! Returns \c true if this is a 4x4mm chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs4x4( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_4x4 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a 5x5mm chip. +//! +//! \return +//! Returns \c true if this is a 5x5mm chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs5x5( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_5x5 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a 7x7mm chip. +//! +//! \return +//! Returns \c true if this is a 7x7mm chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs7x7( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_7x7 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a wafer sale chip (naked die). +//! +//! \return +//! Returns \c true if this is a wafer sale chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIsWAFER( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_WAFER ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a WCSP chip (flip chip). +//! +//! \return +//! Returns \c true if this is a WCSP chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIsWCSP( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_WCSP ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a 7x7 Q1 chip. +//! +//! \return +//! Returns \c true if this is a 7x7 Q1 chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs7x7Q1( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_7x7_Q1 ); +} + +//***************************************************************************** +// +//! \brief Returns the internal chip HW revision code. +//! +//! \return +//! Returns the internal chip HW revision code (in range 0-15) +//***************************************************************************** +__STATIC_INLINE uint32_t +ChipInfo_GetDeviceIdHwRevCode( void ) +{ + // Returns HwRevCode = FCFG1_O_ICEPICK_DEVICE_ID[31:28] + return ( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) >> 28 ); +} + +//***************************************************************************** +// +//! \brief Returns minor hardware revision number +//! +//! The minor revision number is set to 0 for the first market released chip +//! and thereafter incremented by 1 for each minor hardware change. +//! +//! \return +//! Returns the minor hardware revision number (in range 0-127) +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ChipInfo_GetMinorHwRev( void ) +{ + uint32_t minorRev = (( HWREG( FCFG1_BASE + FCFG1_O_MISC_CONF_1 ) & + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M ) >> + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S ) ; + + if ( minorRev >= 0x80 ) { + minorRev = 0; + } + + return( minorRev ); +} + +//***************************************************************************** +// +//! \brief Returns the 32 bits USER_ID field +//! +//! How to decode the USER_ID filed is described in the Technical Reference Manual (TRM) +//! +//! \return +//! Returns the 32 bits USER_ID field +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ChipInfo_GetUserId( void ) +{ + return ( HWREG( FCFG1_BASE + FCFG1_O_USER_ID )); +} + +//***************************************************************************** +// +//! \brief Chip type enumeration +// +//***************************************************************************** +typedef enum { + CHIP_TYPE_Unknown = -1, //!< -1 means that the chip type is unknown. + CHIP_TYPE_CC1310 = 0, //!< 0 means that this is a CC1310 chip. + CHIP_TYPE_CC1350 = 1, //!< 1 means that this is a CC1350 chip. + CHIP_TYPE_CC2620 = 2, //!< 2 means that this is a CC2620 chip. + CHIP_TYPE_CC2630 = 3, //!< 3 means that this is a CC2630 chip. + CHIP_TYPE_CC2640 = 4, //!< 4 means that this is a CC2640 chip. + CHIP_TYPE_CC2650 = 5, //!< 5 means that this is a CC2650 chip. + CHIP_TYPE_CUSTOM_0 = 6, //!< 6 means that this is a CUSTOM_0 chip. + CHIP_TYPE_CUSTOM_1 = 7, //!< 7 means that this is a CUSTOM_1 chip. + CHIP_TYPE_CC2640R2 = 8, //!< 8 means that this is a CC2640R2 chip. + CHIP_TYPE_CC2642 = 9, //!< 9 means that this is a CC2642 chip. + CHIP_TYPE_unused = 10,//!< 10 unused value + CHIP_TYPE_CC2652 = 11,//!< 11 means that this is a CC2652 chip. + CHIP_TYPE_CC1312 = 12,//!< 12 means that this is a CC1312 chip. + CHIP_TYPE_CC1352 = 13,//!< 13 means that this is a CC1352 chip. + CHIP_TYPE_CC1352P = 14 //!< 14 means that this is a CC1352P chip. +} ChipType_t; + +//***************************************************************************** +// +//! \brief Returns chip type. +//! +//! \return +//! Returns \ref ChipType_t +// +//***************************************************************************** +extern ChipType_t ChipInfo_GetChipType( void ); + +//***************************************************************************** +// +//! \brief Chip family enumeration +// +//***************************************************************************** +typedef enum { + FAMILY_Unknown = -1, //!< -1 means that the chip's family member is unknown. + FAMILY_CC26x0 = 0, //!< 0 means that the chip is a CC26x0 family member. + FAMILY_CC13x0 = 1, //!< 1 means that the chip is a CC13x0 family member. + FAMILY_CC26x1 = 2, //!< 2 means that the chip is a CC26x1 family member. + FAMILY_CC26x0R2 = 3, //!< 3 means that the chip is a CC26x0R2 family (new ROM contents). + FAMILY_CC13x2_CC26x2 = 4 //!< 4 means that the chip is a CC13x2, CC26x2 family member. +} ChipFamily_t; + +//***************************************************************************** +// +//! \brief Returns chip family member. +//! +//! \return +//! Returns \ref ChipFamily_t +// +//***************************************************************************** +extern ChipFamily_t ChipInfo_GetChipFamily( void ); + +//***************************************************************************** +// +// Options for the define THIS_DRIVERLIB_BUILD +// +//***************************************************************************** +#define DRIVERLIB_BUILD_CC26X0 0 //!< 0 is the driverlib build ID for the cc26x0 driverlib. +#define DRIVERLIB_BUILD_CC13X0 1 //!< 1 is the driverlib build ID for the cc13x0 driverlib. +#define DRIVERLIB_BUILD_CC26X1 2 //!< 2 is the driverlib build ID for the cc26x1 driverlib. +#define DRIVERLIB_BUILD_CC26X0R2 3 //!< 3 is the driverlib build ID for the cc26x0r2 driverlib. +#define DRIVERLIB_BUILD_CC13X2_CC26X2 4 //!< 4 is the driverlib build ID for the cc13x2_cc26x2 driverlib. + +//***************************************************************************** +// +//! \brief Define THIS_DRIVERLIB_BUILD, identifying current driverlib build ID. +//! +//! This driverlib build identifier can be useful for compile time checking/optimization (supporting C preprocessor expressions). +// +//***************************************************************************** +#define THIS_DRIVERLIB_BUILD DRIVERLIB_BUILD_CC26X0 + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC13x0 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC13x0 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC13x0( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC13x0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC26x0 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC26x0 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC26x0( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC26x0R2 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC26x0R2 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC26x0R2( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0R2 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC26x1 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC26x1 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC26x1( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC26x1 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC13x2, CC26x2 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC13x2, CC26x2 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC13x2_CC26x2( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC13x2_CC26x2 ); +} + +//***************************************************************************** +// +//! \brief HW revision enumeration. +// +//***************************************************************************** +typedef enum { + HWREV_Unknown = -1, //!< -1 means that the chip's HW revision is unknown. + HWREV_1_0 = 10, //!< 10 means that the chip's HW revision is 1.0 + HWREV_1_1 = 11, //!< 11 means that the chip's HW revision is 1.1 + HWREV_2_0 = 20, //!< 20 means that the chip's HW revision is 2.0 + HWREV_2_1 = 21, //!< 21 means that the chip's HW revision is 2.1 + HWREV_2_2 = 22, //!< 22 means that the chip's HW revision is 2.2 + HWREV_2_3 = 23, //!< 23 means that the chip's HW revision is 2.3 + HWREV_2_4 = 24 //!< 24 means that the chip's HW revision is 2.4 +} HwRevision_t; + +//***************************************************************************** +// +//! \brief Returns chip HW revision. +//! +//! \return +//! Returns \ref HwRevision_t +// +//***************************************************************************** +extern HwRevision_t ChipInfo_GetHwRevision( void ); + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 1.0. +//! +//! \return +//! Returns \c true if HW revision for this chip is 1.0, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_1_0( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_1_0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.0. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.0, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_2_0( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_2_0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.0 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.0 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_0( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.1. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.1, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_2_1( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_2_1 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.1 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.1 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_1( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_1 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.2. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.2, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_2_2( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_2_2 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.2 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.2 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_2( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_2 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.3 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.3 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_3( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_3 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.4 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.4 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_4( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_4 ); +} + +//***************************************************************************** +// +//! \brief Verifies that current chip is CC26x0 HwRev 2.2 or later and never returns if violated. +//! +//! \return None +// +//***************************************************************************** +extern void ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated( void ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_ChipInfo_GetSupportedProtocol_BV + #undef ChipInfo_GetSupportedProtocol_BV + #define ChipInfo_GetSupportedProtocol_BV ROM_ChipInfo_GetSupportedProtocol_BV + #endif + #ifdef ROM_ChipInfo_GetPackageType + #undef ChipInfo_GetPackageType + #define ChipInfo_GetPackageType ROM_ChipInfo_GetPackageType + #endif + #ifdef ROM_ChipInfo_GetChipType + #undef ChipInfo_GetChipType + #define ChipInfo_GetChipType ROM_ChipInfo_GetChipType + #endif + #ifdef ROM_ChipInfo_GetChipFamily + #undef ChipInfo_GetChipFamily + #define ChipInfo_GetChipFamily ROM_ChipInfo_GetChipFamily + #endif + #ifdef ROM_ChipInfo_GetHwRevision + #undef ChipInfo_GetHwRevision + #define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision + #endif + #ifdef ROM_ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated + #undef ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated + #define ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated ROM_ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CHIP_INFO_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu.c new file mode 100644 index 0000000..293767d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu.c @@ -0,0 +1,396 @@ +/****************************************************************************** +* Filename: cpu.c +* Revised: 2018-05-08 10:04:01 +0200 (Tue, 08 May 2018) +* Revision: 51972 +* +* Description: Instruction wrappers for special CPU instructions needed by +* the drivers. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "cpu.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef CPUcpsid + #define CPUcpsid NOROM_CPUcpsid + #undef CPUprimask + #define CPUprimask NOROM_CPUprimask + #undef CPUcpsie + #define CPUcpsie NOROM_CPUcpsie + #undef CPUbasepriGet + #define CPUbasepriGet NOROM_CPUbasepriGet + #undef CPUdelay + #define CPUdelay NOROM_CPUdelay +#endif + +//***************************************************************************** +// +// Disable all external interrupts +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUcpsid(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + mrs r0, PRIMASK; + cpsid i; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUcpsid(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK and disable interrupts + __asm volatile (" mrs %0, PRIMASK\n" + " cpsid i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif + +//***************************************************************************** +// +// Get the current interrupt state +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUprimask(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUprimask(void) +{ + // Read PRIMASK. + __asm(" mrs r0, PRIMASK\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUprimask(void) +{ + // Read PRIMASK. + mrs r0, PRIMASK; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUprimask(void) +{ + // Read PRIMASK. + __asm(" mrs r0, PRIMASK\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUprimask(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK + __asm volatile (" mrs %0, PRIMASK\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif + +//***************************************************************************** +// +// Enable all external interrupts +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUcpsie(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + mrs r0, PRIMASK; + cpsie i; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUcpsie(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK and enable interrupts. + __asm volatile (" mrs %0, PRIMASK\n" + " cpsie i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif + +//***************************************************************************** +// +// Get the interrupt priority disable level +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUbasepriGet(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUbasepriGet(void) +{ + // Read BASEPRI. + __asm(" mrs r0, BASEPRI\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUbasepriGet(void) +{ + // Read BASEPRI. + mrs r0, BASEPRI; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUbasepriGet(void) +{ + // Read BASEPRI. + __asm(" mrs r0, BASEPRI\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUbasepriGet(void) +{ + uint32_t ui32Ret; + + // Read BASEPRI. + __asm volatile (" mrs %0, BASEPRI\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif +//***************************************************************************** +// +// Provide a small delay +// +//***************************************************************************** +#if defined(DOXYGEN) +void +CPUdelay(uint32_t ui32Count) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +void +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times + __asm("CPUdelay:\n" + " subs r0, #1\n" + " bne.n CPUdelay\n" + " bx lr"); +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm void +CPUdelay(uint32_t ui32Count) +{ + // Delay the specified number of times (3 cycles pr. loop) +CPUdel + subs r0, #1; + bne CPUdel; + bx lr; +} +#elif defined(__TI_COMPILER_VERSION__) + // For CCS implement this function in pure assembly. This prevents the TI + // compiler from doing funny things with the optimizer. + + // Loop the specified number of times +__asm(" .sect \".text:NOROM_CPUdelay\"\n" + " .clink\n" + " .thumbfunc NOROM_CPUdelay\n" + " .thumb\n" + " .global NOROM_CPUdelay\n" + "NOROM_CPUdelay:\n" + " subs r0, #1\n" + " bne.n NOROM_CPUdelay\n" + " bx lr\n"); +#else +// GCC +void __attribute__((naked)) +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times + __asm volatile ("%=: subs %0, #1\n" + " bne %=b\n" + " bx lr\n" + : /* No output */ + : "r" (ui32Count) + ); +} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu.h new file mode 100644 index 0000000..e2b0561 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu.h @@ -0,0 +1,466 @@ +/****************************************************************************** +* Filename: cpu.h +* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) +* Revision: 52111 +* +* Description: Defines and prototypes for the CPU instruction wrapper +* functions. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup cpu_api +//! @{ +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_cpu_scs.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define CPUcpsid NOROM_CPUcpsid + #define CPUprimask NOROM_CPUprimask + #define CPUcpsie NOROM_CPUcpsie + #define CPUbasepriGet NOROM_CPUbasepriGet + #define CPUdelay NOROM_CPUdelay +#endif + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Disable all external interrupts. +//! +//! Use this function to disable all system interrupts. This function is +//! implemented as a wrapper function for the CPSID instruction. +//! +//! \return Returns the state of \b PRIMASK on entry +// +//***************************************************************************** +extern uint32_t CPUcpsid(void); + +//***************************************************************************** +// +//! \brief Get the current interrupt state. +//! +//! Use this function to retrieve the current state of the interrupts. This +//! function is implemented as a wrapper function returning the state of +//! PRIMASK. +//! +//! \return Returns the state of the \b PRIMASK (indicating whether interrupts +//! are enabled or disabled). +// +//***************************************************************************** +extern uint32_t CPUprimask(void); + +//***************************************************************************** +// +//! \brief Enable all external interrupts. +//! +//! Use this function to enable all system interrupts. This function is +//! implemented as a wrapper function for the CPSIE instruction. +//! +//! \return Returns the state of \b PRIMASK on entry. +// +//***************************************************************************** +extern uint32_t CPUcpsie(void); + +//***************************************************************************** +// +//! \brief Get the interrupt priority disable level. +//! +//! Use this function to get the level of priority that will disable +//! interrupts with a lower priority level. +//! +//! \return Returns the value of the \b BASEPRI register. +// +//***************************************************************************** +extern uint32_t CPUbasepriGet(void); + +//***************************************************************************** +// +//! \brief Provide a small non-zero delay using a simple loop counter. +//! +//! This function provides means for generating a constant length delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! \note It is not recommended using this function for long delays. +//! +//! Notice that interrupts can affect the delay if not manually disabled in advance. +//! +//! The delay depends on where code resides and the path for code fetching: +//! - Code in flash, cache enabled, prefetch enabled : 4 cycles per loop (Default) +//! - Code in flash, cache enabled, prefetch disabled : 5 cycles per loop +//! - Code in flash, cache disabled : 7 cycles per loop +//! - Code in SRAM : 6 cycles per loop +//! - Code in GPRAM : 3 cycles per loop +//! +//! \note If using an RTOS, consider using RTOS provided delay functions because +//! these will not block task scheduling and will potentially save power. +//! +//! Calculate delay count based on the wanted delay in microseconds (us): +//! - ui32Count = [delay in us] * [CPU clock in MHz] / [cycles per loop] +//! +//! Example: 250 us delay with code in flash and with cache and prefetch enabled: +//! - ui32Count = 250 * 48 / 4 = 3000 +//! +//! \param ui32Count is the number of delay loop iterations to perform. Number must be greater than zero. +//! +//! \return None +// +//***************************************************************************** +extern void CPUdelay(uint32_t ui32Count); + +//***************************************************************************** +// +//! \brief Wait for interrupt. +//! +//! Use this function to let the System CPU wait for the next interrupt. This +//! function is implemented as a wrapper function for the WFI instruction. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUwfi(void) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUwfi(void) +{ + // Wait for the next interrupt. + __asm(" wfi\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUwfi(void) +{ + // Wait for the next interrupt. + wfi; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUwfi(void) +{ + // Wait for the next interrupt. + __asm(" wfi\n"); +} +#else +__STATIC_INLINE void __attribute__((always_inline)) +CPUwfi(void) +{ + // Wait for the next interrupt. + __asm volatile (" wfi\n"); +} +#endif + +//***************************************************************************** +// +//! \brief Wait for event. +//! +//! Use this function to let the System CPU wait for the next event. This +//! function is implemented as a wrapper function for the WFE instruction. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUwfe(void) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUwfe(void) +{ + // Wait for the next event. + __asm(" wfe\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUwfe(void) +{ + // Wait for the next event. + wfe; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUwfe(void) +{ + // Wait for the next event. + __asm(" wfe\n"); +} +#else +__STATIC_INLINE void __attribute__((always_inline)) +CPUwfe(void) +{ + // Wait for the next event. + __asm volatile (" wfe\n"); +} +#endif + +//***************************************************************************** +// +//! \brief Send event. +//! +//! Use this function to let the System CPU send an event. This function is +//! implemented as a wrapper function for the SEV instruction. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUsev(void) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUsev(void) +{ + // Send event. + __asm(" sev\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUsev(void) +{ + // Send event. + sev; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUsev(void) +{ + // Send event. + __asm(" sev\n"); +} +#else +__STATIC_INLINE void __attribute__((always_inline)) +CPUsev(void) +{ + // Send event. + __asm volatile (" sev\n"); +} +#endif + + +//***************************************************************************** +// +//! \brief Update the interrupt priority disable level. +//! +//! Use this function to change the level of priority that will disable +//! interrupts with a lower priority level. +//! +//! \param ui32NewBasepri is the new basis priority level to set. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + __asm(" msr BASEPRI, r0\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + msr BASEPRI, r0; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + __asm(" msr BASEPRI, r0\n"); +} +#else +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wattributes" +__STATIC_INLINE void __attribute__ ((naked)) +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + __asm volatile (" msr BASEPRI, %0\n" + " bx lr\n" + : /* No output */ + : "r" (ui32NewBasepri) + ); +} +#pragma GCC diagnostic pop +#endif + +//***************************************************************************** +// +//! \brief Disable CPU write buffering (recommended for debug purpose only). +//! +//! This function helps debugging "bus fault crashes". +//! Disables write buffer use during default memory map accesses. +//! +//! This causes all bus faults to be precise bus faults but decreases the +//! performance of the processor because the stores to memory have to complete +//! before the next instruction can be executed. +//! +//! \return None +//! +//! \sa \ref CPU_WriteBufferEnable() +// +//***************************************************************************** +__STATIC_INLINE void +CPU_WriteBufferDisable( void ) +{ + HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1; +} + +//***************************************************************************** +// +//! \brief Enable CPU write buffering (default setting). +//! +//! Re-enables write buffer during default memory map accesses if +//! \ref CPU_WriteBufferDisable() has been used for bus fault debugging. +//! +//! \return None +//! +//! \sa \ref CPU_WriteBufferDisable() +// +//***************************************************************************** +__STATIC_INLINE void +CPU_WriteBufferEnable( void ) +{ + HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_CPUcpsid + #undef CPUcpsid + #define CPUcpsid ROM_CPUcpsid + #endif + #ifdef ROM_CPUprimask + #undef CPUprimask + #define CPUprimask ROM_CPUprimask + #endif + #ifdef ROM_CPUcpsie + #undef CPUcpsie + #define CPUcpsie ROM_CPUcpsie + #endif + #ifdef ROM_CPUbasepriGet + #undef CPUbasepriGet + #define CPUbasepriGet ROM_CPUbasepriGet + #endif + #ifdef ROM_CPUdelay + #undef CPUdelay + #define CPUdelay ROM_CPUdelay + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CPU_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu_doc.h new file mode 100644 index 0000000..7f17aa3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu_doc.h @@ -0,0 +1,44 @@ +/****************************************************************************** +* Filename: cpu_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup cpu_api +//! @{ +//! \section sec_cpu Introduction +//! +//! The CPU API provides a set of functions performing very low-level control of the system CPU. +//! All functions in this API are written in assembler in order to either access special registers +//! or avoid any compiler optimizations. Each function exists in several compiler specific versions: +//! One version for each supported compiler. +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/crypto.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/crypto.c new file mode 100644 index 0000000..d6617a2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/crypto.c @@ -0,0 +1,943 @@ +/****************************************************************************** +* Filename: crypto.c +* Revised: 2017-12-20 16:40:03 +0100 (Wed, 20 Dec 2017) +* Revision: 50869 +* +* Description: Driver for the Crypto module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "crypto.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef CRYPTOAesLoadKey + #define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey + #undef CRYPTOAesCbc + #define CRYPTOAesCbc NOROM_CRYPTOAesCbc + #undef CRYPTOAesCbcStatus + #define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus + #undef CRYPTOAesEcb + #define CRYPTOAesEcb NOROM_CRYPTOAesEcb + #undef CRYPTOAesEcbStatus + #define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus + #undef CRYPTOCcmAuthEncrypt + #define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt + #undef CRYPTOCcmAuthEncryptStatus + #define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus + #undef CRYPTOCcmAuthEncryptResultGet + #define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet + #undef CRYPTOCcmInvAuthDecrypt + #define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt + #undef CRYPTOCcmInvAuthDecryptStatus + #define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus + #undef CRYPTOCcmInvAuthDecryptResultGet + #define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet + #undef CRYPTODmaEnable + #define CRYPTODmaEnable NOROM_CRYPTODmaEnable + #undef CRYPTODmaDisable + #define CRYPTODmaDisable NOROM_CRYPTODmaDisable +#endif + +//***************************************************************************** +// +// Write the key into the Key Ram. +// +//***************************************************************************** +uint32_t +CRYPTOAesLoadKey(uint32_t *pui32AesKey, + uint32_t ui32KeyLocation) +{ + uint32_t returnStatus = AES_KEYSTORE_READ_ERROR; + + // Check the arguments. + ASSERT((ui32KeyLocation == CRYPTO_KEY_AREA_0) | + (ui32KeyLocation == CRYPTO_KEY_AREA_1) | + (ui32KeyLocation == CRYPTO_KEY_AREA_2) | + (ui32KeyLocation == CRYPTO_KEY_AREA_3) | + (ui32KeyLocation == CRYPTO_KEY_AREA_4) | + (ui32KeyLocation == CRYPTO_KEY_AREA_5) | + (ui32KeyLocation == CRYPTO_KEY_AREA_6) | + (ui32KeyLocation == CRYPTO_KEY_AREA_7)); + + // Disable the external interrupt to stop the interrupt form propagating + // from the module to the System CPU. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Clear any previously written key at the keyLocation + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << ui32KeyLocation); + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | + CRYPTO_IRQEN_RESULT_AVAIL; + + // Configure master control module. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_ALGSEL, CRYPTO_ALGSEL_KEY_STORE_BITN) = 1; + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Configure key store module for 128 bit operation. + // Do not write to the register if the correct key size is already set. + // Writing to this register causes all current keys to be invalidated. + if (HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) != KEY_STORE_SIZE_128) { + HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = KEY_STORE_SIZE_128; + } + + // Enable keys to write (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = (0x00000001 << ui32KeyLocation); + + // Enable Crypto DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the key in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32AesKey; + + // Total key length in bytes (e.g. 16 for 1 x 128-bit key). + // Writing the length of the key enables the DMA operation. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = KEY_BLENGTH; + + // Wait for the DMA operation to complete. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & + (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | + CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M | + CRYPTO_IRQSTAT_DMA_IN_DONE | + CRYPTO_IRQSTAT_RESULT_AVAIL_M))); + + // Check for errors in DMA and key store. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & + (CRYPTO_IRQSTAT_DMA_BUS_ERR | + CRYPTO_IRQSTAT_KEY_ST_WR_ERR)) == 0) + { + // Acknowledge/clear the interrupt and disable the master control. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + + // Check key status, return success if key valid. + if(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (0x00000001 << ui32KeyLocation)) + { + returnStatus = AES_SUCCESS; + } + } + + // Return status. + return returnStatus; +} + +//***************************************************************************** +// +// Start an AES-CBC operation (encryption or decryption). +// +//***************************************************************************** +uint32_t +CRYPTOAesCbc(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32MsgLength, + uint32_t *pui32Nonce, uint32_t ui32KeyLocation, + bool bEncrypt, bool bIntEnable) +{ + uint32_t ui32CtrlVal; + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; + + // Clear any outstanding interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Wait for interrupt lines from module to be cleared + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); + + // If using interrupts clear any pending interrupts and enable interrupts + // for the Crypto module. + if(bIntEnable) + { + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + // Configure Master Control module. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; + + //Wait until key is loaded to the AES module. + do + { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); + + // Check for Key store Read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) + { + return (AES_KEYSTORE_READ_ERROR); + } + + // Write initialization vector. + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = pui32Nonce[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = pui32Nonce[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = pui32Nonce[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = pui32Nonce[3]; + + // Configure AES engine for AES-CBC with 128-bit key size. + ui32CtrlVal = (CRYPTO_AESCTL_SAVE_CONTEXT | CRYPTO_AESCTL_CBC); + if(bEncrypt) + { + ui32CtrlVal |= CRYPTO_AES128_ENCRYPT; + } + else + { + ui32CtrlVal |= CRYPTO_AES128_DECRYPT; + } + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; + + // Write the length of the crypto block (plain text). + // Low and high part (high part is assumed to be always 0). + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32MsgLength; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; + HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = 0; + + // Enable Crypto DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the input data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn; + + // Input data length in bytes, equal to the message. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32MsgLength; + + // Enable Crypto DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Set up the address and length of the output data. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut; + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32MsgLength; + + // Return success + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Check the result of an AES CBC operation +// +//***************************************************************************** +uint32_t +CRYPTOAesCbcStatus(void) +{ + return(CRYPTOAesEcbStatus()); +} + +//***************************************************************************** +// +// Start an AES-ECB operation (encryption or decryption). +// +//***************************************************************************** +uint32_t +CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, + uint32_t ui32KeyLocation, bool bEncrypt, + bool bIntEnable) +{ + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; + + // Clear any outstanding interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Wait for interrupt lines from module to be cleared + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); + + // If using interrupts clear any pending interrupts and enable interrupts + // for the Crypto module. + if(bIntEnable) + { + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + // Configure Master Control module. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; + + //Wait until key is loaded to the AES module. + do + { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); + + // Check for Key store Read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) + { + return (AES_KEYSTORE_READ_ERROR); + } + + // Configure AES engine (program AES-ECB-128 encryption and no + // initialization vector - IV). + if(bEncrypt) + { + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_ENCRYPT; + } + else + { + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_DECRYPT; + } + + // Write the length of the data. + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = AES_ECB_LENGTH; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; + + // Enable Crypto DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the input data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn; + + // Input data length in bytes, equal to the message. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = AES_ECB_LENGTH; + + // Enable Crypto DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Set up the address and length of the output data. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut; + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = AES_ECB_LENGTH; + + // Return success + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Check the result of an AES ECB operation +// +//***************************************************************************** +uint32_t +CRYPTOAesEcbStatus(void) +{ + uint32_t ui32Status; + + // Get the current DMA status. + ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); + + // Check if DMA is still busy. + if(ui32Status & CRYPTO_DMA_BSY) + { + return (AES_DMA_BSY); + } + + // Check the status of the DMA operation - return error if not success. + if(ui32Status & CRYPTO_DMA_BUS_ERROR) + { + return (AES_DMA_BUS_ERROR); + } + + // Operation successful - disable interrupt and return success. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + return (AES_SUCCESS); +} + +//***************************************************************************** +// +// Start CCM operation +// +//***************************************************************************** +uint32_t +CRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength , + uint32_t *pui32Nonce, uint32_t *pui32PlainText, + uint32_t ui32PlainTextLength, uint32_t *pui32Header, + uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, + uint32_t ui32FieldLength, bool bIntEnable) +{ + uint32_t ui32CtrlVal; + uint32_t i; + uint32_t *pui32CipherText; + union { + uint32_t w[4]; + uint8_t b[16]; + } ui8InitVec; + + // Input address for the encryption engine is the same as the output. + pui32CipherText = pui32PlainText; + + // Disable global interrupt, enable local interrupt and clear any pending + // interrupts. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | + CRYPTO_IRQEN_RESULT_AVAIL; + + // Configure master control module for AES operation. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; + + // Wait until key is loaded to the AES module. + do + { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); + + // Check for Key store Read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) + { + return (AES_KEYSTORE_READ_ERROR); + } + + // Prepare the initialization vector (IV), + // Length of Nonce l(n) = 15 - ui32FieldLength. + ui8InitVec.b[0] = ui32FieldLength - 1; + for(i = 0; i < 12; i++) + { + ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i]; + } + if(ui32FieldLength == 2) + { + ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12]; + } + else + { + ui8InitVec.b[13] = 0; + } + ui8InitVec.b[14] = 0; + ui8InitVec.b[15] = 0; + + // Write initialization vector. + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3]; + + // Configure AES engine. + ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if ( ui32AuthLength >= 2 ) { + ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); + } + ui32CtrlVal |= CRYPTO_AESCTL_CCM; + ui32CtrlVal |= CRYPTO_AESCTL_CTR; + ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT; + ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S); + ui32CtrlVal |= (1 << CRYPTO_AESCTL_DIR_S); + ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S); + + // Write the configuration for 128 bit AES-CCM. + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; + + // Write the length of the crypto block (plain text). + // Low and high part (high part is assumed to be always 0). + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32PlainTextLength; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; + + // Write the length of the header field. + // Also called AAD - Additional Authentication Data. + HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength; + + // Check if any header information (AAD). + // If so configure the DMA controller to fetch the header. + if(ui32HeaderLength != 0) + { + // Enable DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Register the base address of the header (AAD). + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header; + + // Header length in bytes (may be non-block size aligned). + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength; + + // Wait for completion of the header data transfer, DMA_IN_DONE. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE)); + + // Check for DMA errors. + if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR) + { + return AES_DMA_BUS_ERROR; + } + } + + // Clear interrupt status. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Wait for interrupt lines from module to be cleared + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); + + // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only + // want interrupt to trigger once RESULT_AVAIL occurs. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE; + + + // Is using interrupts enable globally. + if(bIntEnable) + { + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + // Enable interrupts locally. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; + + // Perform encryption if requested. + if(bEncrypt) + { + // Enable DMA channel 0 + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = + (uint32_t)pui32PlainText; + + // Enable DMA channel 1 + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = + (uint32_t)pui32CipherText; + + // Payload data length in bytes, equal to the plaintext length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32PlainTextLength; + // Output data length in bytes, equal to the plaintext length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32PlainTextLength; + } + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Check the result of an AES CCM operation. +// +//***************************************************************************** +uint32_t +CRYPTOCcmAuthEncryptStatus(void) +{ + uint32_t ui32Status; + + // Get the current DMA status. + ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); + + // Check if DMA is still busy. + if(ui32Status & CRYPTO_DMA_BSY) + { + return (AES_DMA_BSY); + } + + // Check the status of the DMA operation - return error if not success. + if(ui32Status & CRYPTO_DMA_BUS_ERROR) + { + return (AES_DMA_BUS_ERROR); + } + + // Operation successful - disable interrupt and return success. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + return (AES_SUCCESS); +} + +//***************************************************************************** +// +// Get the result of an AES-CCM operation +// +//***************************************************************************** +uint32_t +CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, uint32_t *pui32CcmTag) +{ + uint32_t volatile ui32Tag[4]; + uint32_t ui32Idx; + + // Result has already been copied to the output buffer by DMA + // Disable master control. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + + // Read tag - wait for the context ready bit. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & + CRYPTO_AESCTL_SAVED_CONTEXT_RDY)); + + // Read the Tag registers. + ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); + ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); + ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); + ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); + + for(ui32Idx = 0; ui32Idx < ui32TagLength ; ui32Idx++) + { + *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx); + } + + // Operation successful - clear interrupt status. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Start a CCM Decryption and Inverse Authentication operation. +// +//***************************************************************************** +uint32_t +CRYPTOCcmInvAuthDecrypt(bool bDecrypt, uint32_t ui32AuthLength, + uint32_t *pui32Nonce, uint32_t *pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t *pui32Header, uint32_t ui32HeaderLength, + uint32_t ui32KeyLocation, + uint32_t ui32FieldLength, bool bIntEnable) +{ + uint32_t ui32CtrlVal; + uint32_t i; + uint32_t *pui32PlainText; + uint32_t ui32CryptoBlockLength; + union { + uint32_t w[4]; + uint8_t b[16]; + } ui8InitVec; + + // Input address for the encryption engine is the same as the output. + pui32PlainText = pui32CipherText; + + // Disable global interrupt, enable local interrupt and clear any pending. + // interrupts. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | + CRYPTO_IRQEN_RESULT_AVAIL; + + // Configure master control module for AES operation. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; + + // Wait until key is loaded to the AES module. + do + { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); + + // Check for Key store Read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) + { + return (AES_KEYSTORE_READ_ERROR); + } + + // Prepare the initialization vector (IV), + // Length of Nonce l(n) = 15 - ui32FieldLength. + ui8InitVec.b[0] = ui32FieldLength - 1; + for(i = 0; i < 12; i++) + { + ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i]; + } + if(ui32FieldLength == 2) + { + ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12]; + } + else + { + ui8InitVec.b[13] = 0; + } + ui8InitVec.b[14] = 0; + ui8InitVec.b[15] = 0; + + // Write initialization vector. + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3]; + + // Configure AES engine + ui32CryptoBlockLength = ui32CipherTextLength - ui32AuthLength; + ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if ( ui32AuthLength >= 2 ) { + ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); + } + ui32CtrlVal |= CRYPTO_AESCTL_CCM; + ui32CtrlVal |= CRYPTO_AESCTL_CTR; + ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT; + ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S); + ui32CtrlVal |= (0 << CRYPTO_AESCTL_DIR_S); + ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S); + + // Write the configuration for 128 bit AES-CCM. + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; + + // Write the length of the crypto block (plain text). + // Low and high part (high part is assumed to be always 0). + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32CryptoBlockLength; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; + + // Write the length of the header field. + // Also called AAD - Additional Authentication Data. + HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength; + + // Check if any header information (AAD). + // If so configure the DMA controller to fetch the header. + if(ui32HeaderLength != 0) + { + // Enable DMA channel 0. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Register the base address of the header (AAD). + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header; + + // Header length in bytes (may be non-block size aligned). + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength; + + // Wait for completion of the header data transfer, DMA_IN_DONE. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE)); + + // Check for DMA errors. + if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR) + { + return AES_DMA_BUS_ERROR; + } + } + + // Clear interrupt status. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Wait for interrupt lines from module to be cleared + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); + + // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only + // want interrupt to trigger once RESULT_AVAIL occurs. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE; + + // Is using interrupts - clear and enable globally. + if(bIntEnable) + { + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; + + // Perform decryption if requested. + if(bDecrypt) + { + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = + (uint32_t)pui32CipherText; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32CryptoBlockLength; + + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = + (uint32_t)pui32PlainText; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32CryptoBlockLength; + } + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Checks CCM decrypt and Inverse Authentication result. +// +//***************************************************************************** +uint32_t +CRYPTOCcmInvAuthDecryptStatus(void) +{ + uint32_t ui32Status; + + // Get the current DMA status. + ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); + + // Check if DMA is still busy. + if(ui32Status & CRYPTO_DMA_BSY) + { + return (AES_DMA_BSY); + } + + // Check the status of the DMA operation - return error if not success. + if(ui32Status & CRYPTO_DMA_BUS_ERROR) + { + return (AES_DMA_BUS_ERROR); + } + + // Operation successful - disable interrupt and return success + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + return (AES_SUCCESS); +} + +//***************************************************************************** +// +// Get the result of the CCM operation. +// +//***************************************************************************** +uint32_t +CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength, + uint32_t *pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t *pui32CcmTag) +{ + uint32_t volatile ui32Tag[4]; + uint32_t ui32TagIndex; + uint32_t i; + uint32_t ui32Idx; + + ui32TagIndex = ui32CipherTextLength - ui32AuthLength; + + // Result has already been copied to the output buffer by DMA + // Disable master control. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + + // Read tag - wait for the context ready bit. + do + { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & + CRYPTO_AESCTL_SAVED_CONTEXT_RDY)); + + // Read the Tag registers. + ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); + ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); + ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); + ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); + + for(ui32Idx = 0; ui32Idx < ui32AuthLength ; ui32Idx++) + { + *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx); + } + + // Operation successful - clear interrupt status. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | + CRYPTO_IRQCLR_RESULT_AVAIL); + + // Verify the Tag. + for(i = 0; i < ui32AuthLength; i++) + { + if(*((uint8_t *)pui32CcmTag + i) != + (*((uint8_t *)pui32CipherText + ui32TagIndex + i))) + { + return CCM_AUTHENTICATION_FAILED; + } + } + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Enable Crypto DMA operation +// +//***************************************************************************** +void +CRYPTODmaEnable(uint32_t ui32Channels) +{ + // Check the arguments. + ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) | + (ui32Channels & CRYPTO_DMA_CHAN1)); + + // Enable the selected channels, + if(ui32Channels & CRYPTO_DMA_CHAN0) + { + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + } + if(ui32Channels & CRYPTO_DMA_CHAN1) + { + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + } +} + +//***************************************************************************** +// +// Disable Crypto DMA operation +// +//***************************************************************************** +void +CRYPTODmaDisable(uint32_t ui32Channels) +{ + // Check the arguments. + ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) | + (ui32Channels & CRYPTO_DMA_CHAN1)); + + // Enable the selected channels. + if(ui32Channels & CRYPTO_DMA_CHAN0) + { + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 0; + } + if(ui32Channels & CRYPTO_DMA_CHAN1) + { + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 0; + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/crypto.h new file mode 100644 index 0000000..bb411ec --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/crypto.h @@ -0,0 +1,856 @@ +/****************************************************************************** +* Filename: crypto.h +* Revised: 2018-01-12 18:46:31 +0100 (Fri, 12 Jan 2018) +* Revision: 51161 +* +* Description: AES header file. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup crypto_api +//! @{ +// +//***************************************************************************** + +#ifndef __CRYPTO_H__ +#define __CRYPTO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_crypto.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey + #define CRYPTOAesCbc NOROM_CRYPTOAesCbc + #define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus + #define CRYPTOAesEcb NOROM_CRYPTOAesEcb + #define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus + #define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt + #define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus + #define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet + #define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt + #define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus + #define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet + #define CRYPTODmaEnable NOROM_CRYPTODmaEnable + #define CRYPTODmaDisable NOROM_CRYPTODmaDisable +#endif + +//***************************************************************************** +// +// Length of AES Electronic Code Book (ECB) block in bytes +// +//***************************************************************************** +#define AES_ECB_LENGTH 16 + +//***************************************************************************** +// +// Values that can be passed to CryptoIntEnable, CryptoIntDisable, and CryptoIntClear +// as the ui32IntFlags parameter, and returned from CryptoIntStatus. +// +//***************************************************************************** +#define CRYPTO_DMA_IN_DONE 0x00000002 // DMA done interrupt mask +#define CRYPTO_RESULT_RDY 0x00000001 // Result ready interrupt mask +#define CRYPTO_DMA_BUS_ERR 0x80000000 // DMA Bus error +#define CRYPTO_KEY_ST_WR_ERR 0x40000000 // Key Store Write failed +#define CRYPTO_KEY_ST_RD_ERR 0x20000000 // Key Store Read failed + +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 // Crypto Level interrupt enabled +#define CRYPTO_IRQTYPE_PULSE 0x00000000 // Crypto pulse interrupt enabled + +#define CRYPTO_DMA_CHAN0 0x00000001 // Crypto DMA Channel 0 +#define CRYPTO_DMA_CHAN1 0x00000002 // Crypto DMA Channel 1 + +#define CRYPTO_AES128_ENCRYPT 0x0000000C // +#define CRYPTO_AES128_DECRYPT 0x00000008 // + +#define CRYPTO_DMA_READY 0x00000000 // DMA ready +#define CRYPTO_DMA_BSY 0x00000003 // DMA busy +#define CRYPTO_DMA_BUS_ERROR 0x00020000 // DMA encountered bus error + +//***************************************************************************** +// +// General constants +// +//***************************************************************************** + +// AES module return codes +#define AES_SUCCESS 0 +#define AES_KEYSTORE_READ_ERROR 1 +#define AES_KEYSTORE_WRITE_ERROR 2 +#define AES_DMA_BUS_ERROR 3 +#define CCM_AUTHENTICATION_FAILED 4 +#define AES_ECB_TEST_ERROR 8 +#define AES_NULL_ERROR 9 +#define AES_CCM_TEST_ERROR 10 +#define AES_DMA_BSY 11 + +// Key store module defines +#define STATE_BLENGTH 16 // Number of bytes in State +#define KEY_BLENGTH 16 // Number of bytes in Key +#define KEY_EXP_LENGTH 176 // Nb * (Nr+1) * 4 + +#define KEY_STORE_SIZE_128 0x00000001 +#define KEY_STORE_SIZE_192 0x00000002 +#define KEY_STORE_SIZE_256 0x00000003 +#define KEY_STORE_SIZE_BITS 0x00000003 + +//***************************************************************************** +// +// For 128 bit key all 8 Key Area locations from 0 to 8 are valid +// However for 192 bit and 256 bit keys, only even Key Areas 0, 2, 4, 6 +// are valid. +// +//***************************************************************************** +#define CRYPTO_KEY_AREA_0 0 +#define CRYPTO_KEY_AREA_1 1 +#define CRYPTO_KEY_AREA_2 2 +#define CRYPTO_KEY_AREA_3 3 +#define CRYPTO_KEY_AREA_4 4 +#define CRYPTO_KEY_AREA_5 5 +#define CRYPTO_KEY_AREA_6 6 +#define CRYPTO_KEY_AREA_7 7 + +//***************************************************************************** +// +// Defines for the current AES operation +// +//***************************************************************************** +#define CRYPTO_AES_NONE 0 +#define CRYPTO_AES_KEYL0AD 1 +#define CRYPTO_AES_ECB 2 +#define CRYPTO_AES_CCM 3 +#define CRYPTO_AES_RNG 4 +#define CRYPTO_AES_CBC 5 + +//***************************************************************************** +// +// Defines for the AES-CTR mode counter width +// +//***************************************************************************** +#define CRYPTO_AES_CTR_32 0x0 +#define CRYPTO_AES_CTR_64 0x1 +#define CRYPTO_AES_CTR_96 0x2 +#define CRYPTO_AES_CTR_128 0x3 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Write the key into the Key Ram. +//! +//! The \c ui32KeyLocation parameter is an enumerated type which specifies +//! the Key Ram location in which the key is stored. +//! +//! The pointer \c pui8AesKey has the address where the Key is stored. +//! +//! \param pui32AesKey is a pointer to an AES Key. +//! \param ui32KeyLocation is the location of the key in Key RAM. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! +//! \return Returns status of the function: +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +// +//***************************************************************************** +extern uint32_t CRYPTOAesLoadKey(uint32_t *pui32AesKey, + uint32_t ui32KeyLocation); + +//***************************************************************************** +// +//! \brief Start an AES-CBC operation (encryption or decryption). +//! +//! The function starts an AES CBC mode encrypt or decrypt operation. +//! End operation can be detected by enabling interrupt or by polling +//! CRYPTOAesCbcStatus(). Result of operation is returned by CRYPTOAesCbcStatus(). +//! +//! \param pui32MsgIn is a pointer to the input data. +//! \param pui32MsgOut is a pointer to the output data. +//! \param ui32MsgLength is the length in bytes of the input data. +//! \param pui32Nonce is a pointer to 16-byte Nonce. +//! \param ui32KeyLocation is the location of the key in Key RAM. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! \param bEncrypt is set \c true to encrypt or set \c false to decrypt. +//! \param bIntEnable is set \c true to enable Crypto interrupts or \c false to +//! disable Crypto interrupt. +//! +//! \return Returns status of the AES-CBC operation: +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +//! +//! \sa \ref CRYPTOAesCbcStatus() +// +//***************************************************************************** +extern uint32_t CRYPTOAesCbc(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, + uint32_t ui32MsgLength, uint32_t *pui32Nonce, + uint32_t ui32KeyLocation, bool bEncrypt, + bool bIntEnable); + +//***************************************************************************** +// +//! \brief Check the result of an AES CBC operation. +//! +//! This function should be called after \ref CRYPTOAesCbc() function to +//! check if the AES CBC operation was successful. +//! +//! \return Returns the status of the AES CBC operation: +//! - \ref AES_SUCCESS : Successful. +//! - \ref AES_DMA_BUS_ERROR : Failed. +//! - \ref AES_DMA_BSY : Operation is ongoing. +//! +//! \sa \ref CRYPTOAesCbc() +// +//***************************************************************************** +extern uint32_t CRYPTOAesCbcStatus(void); + +//***************************************************************************** +// +//! \brief Start an AES-ECB operation (encryption or decryption). +//! +//! The \c ui32KeyLocation parameter is an enumerated type which specifies +//! the Key Ram location in which the key is stored. +//! +//! \param pui32MsgIn is a pointer to the input data. +//! \param pui32MsgOut is a pointer to the output data. +//! \param ui32KeyLocation is the location of the key in Key RAM. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! \param bEncrypt is set \c true to encrypt or set \c false to decrypt. +//! \param bIntEnable is set \c true to enable Crypto interrupts or \c false to +//! disable Crypto interrupt. +//! +//! \return Returns status of the AES-ECB operation: +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +//! +//! \sa \ref CRYPTOAesEcbStatus() +// +//***************************************************************************** +extern uint32_t CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, + uint32_t ui32KeyLocation, bool bEncrypt, + bool bIntEnable); + +//***************************************************************************** +// +//! \brief Check the result of an AES ECB operation. +//! +//! This function should be called after \ref CRYPTOAesEcb() function to +//! check if the AES ECB operation was successful. +//! +//! \return Returns the status of the AES ECB operation: +//! - \ref AES_SUCCESS : Successful. +//! - \ref AES_DMA_BUS_ERROR : Failed. +//! - \ref AES_DMA_BSY : Operation is ongoing. +//! +//! \sa \ref CRYPTOAesEcb() +// +//***************************************************************************** +extern uint32_t CRYPTOAesEcbStatus(void); + +//***************************************************************************** +// +//! \brief Finish the encryption operation by resetting the operation mode. +//! +//! This function should be called after \ref CRYPTOAesEcbStatus() has reported +//! that the operation is finished successfully. +//! +//! \return None +//! +//! \sa \ref CRYPTOAesEcbStatus() +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOAesEcbFinish(void) +{ + // Result has already been copied to the output buffer by DMA. + // Disable master control/DMA clock and clear the operating mode. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000; +} + +//***************************************************************************** +// +//! \brief Finish the encryption operation by resetting the operation mode. +//! +//! This function should be called after \ref CRYPTOAesCbcStatus() has reported +//! that the operation is finished successfully. +//! +//! \return None +//! +//! \sa \ref CRYPTOAesCbcStatus() +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOAesCbcFinish(void) +{ + // Result has already been copied to the output buffer by DMA. + // Disable master control/DMA clock and clear the operating mode. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000; +} + +//***************************************************************************** +// +//! \brief Start CCM operation. +//! +//! The \c ui32KeyLocation is an enumerated type which specifies the Key Ram +//! location in which the key is stored. +//! +//! \param bEncrypt determines whether to run encryption or not. +//! \param ui32AuthLength is the length of the authentication field - +//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. +//! \param pui32Nonce is a pointer to 13-byte or 12-byte Nonce (Number used once). +//! \param pui32PlainText is a pointer to the octet string input message. +//! \param ui32PlainTextLength is the length of the message. +//! \param pui32Header is the length of the header (Additional Authentication +//! Data or AAD). +//! \param ui32HeaderLength is the length of the header in octets. +//! \param ui32KeyLocation is the location in Key RAM where the key is stored. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! \param ui32FieldLength is the size of the length field (2 or 3). +//! \param bIntEnable enables interrupts. +//! +//! \return Returns the status of the CCM operation +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +//! - \ref AES_DMA_BUS_ERROR +//! +//! \sa \ref CRYPTOCcmAuthEncryptStatus() +// +//***************************************************************************** +extern uint32_t CRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength, + uint32_t *pui32Nonce, + uint32_t *pui32PlainText, + uint32_t ui32PlainTextLength, + uint32_t *pui32Header, + uint32_t ui32HeaderLength, + uint32_t ui32KeyLocation, + uint32_t ui32FieldLength, + bool bIntEnable); + +//***************************************************************************** +// +//! \brief Check the result of an AES CCM operation. +//! +//! This function should be called after \ref CRYPTOCcmAuthEncrypt() function to check +//! if the AES CCM operation was successful. +//! +//! \return Returns the status of the AES CCM operation: +//! - \ref AES_SUCCESS : Successful. +//! - \ref AES_DMA_BUS_ERROR : Failed. +//! - \ref AES_DMA_BSY : Operation is ongoing. +//! +//! \sa \ref CRYPTOCcmAuthEncrypt() +// +//***************************************************************************** +extern uint32_t CRYPTOCcmAuthEncryptStatus(void); + +//***************************************************************************** +// +//! \brief Get the result of an AES CCM operation. +//! +//! This function should be called after \ref CRYPTOCcmAuthEncryptStatus(). +//! +//! \param ui32TagLength is length of the Tag. +//! \param pui32CcmTag is the location of the authentication Tag. +//! +//! \return Returns \ref AES_SUCCESS if successful. +//! +//! \sa \ref CRYPTOCcmAuthEncryptStatus() +// +//***************************************************************************** +extern uint32_t CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, + uint32_t *pui32CcmTag); + +//***************************************************************************** +// +//! \brief Start a CCM Decryption and Inverse Authentication operation. +//! +//! The \c ui32KeyLocation is an enumerated type which specifies the Key Ram +//! location in which the key is stored. +//! +//! \param bDecrypt determines whether to run decryption or not. +//! \param ui32AuthLength is the length of the authentication field - +//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. +//! \param pui32Nonce is a pointer to 13-byte or 12-byte Nonce (Number used once). +//! \param pui32CipherText is a pointer to the octet string encrypted message. +//! \param ui32CipherTextLength is the length of the encrypted message. +//! \param pui32Header is the length of the header (Additional Authentication +//! Data or AAD). +//! \param ui32HeaderLength is the length of the header in octets. +//! \param ui32KeyLocation is the location in Key RAM where the key is stored. +//! This parameter can have any of the following values: +//! - \ref CRYPTO_KEY_AREA_0 +//! - \ref CRYPTO_KEY_AREA_1 +//! - \ref CRYPTO_KEY_AREA_2 +//! - \ref CRYPTO_KEY_AREA_3 +//! - \ref CRYPTO_KEY_AREA_4 +//! - \ref CRYPTO_KEY_AREA_5 +//! - \ref CRYPTO_KEY_AREA_6 +//! - \ref CRYPTO_KEY_AREA_7 +//! \param ui32FieldLength is the size of the length field (2 or 3). +//! \param bIntEnable enables interrupts. +//! +//! \return Returns the status of the operation: +//! - \ref AES_SUCCESS +//! - \ref AES_KEYSTORE_READ_ERROR +//! - \ref AES_DMA_BUS_ERROR +// +//***************************************************************************** +extern uint32_t CRYPTOCcmInvAuthDecrypt(bool bDecrypt, uint32_t ui32AuthLength, + uint32_t *pui32Nonce, + uint32_t *pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t *pui32Header, + uint32_t ui32HeaderLength, + uint32_t ui32KeyLocation, + uint32_t ui32FieldLength, + bool bIntEnable); + +//***************************************************************************** +// +//! \brief Checks CCM decrypt and Inverse Authentication result. +//! +//! \return Returns status of operation: +//! - \ref AES_SUCCESS : Operation was successful. +//! - \ref AES_DMA_BSY : Operation is busy. +//! - \ref AES_DMA_BUS_ERROR : An error is encountered. +// +//***************************************************************************** +extern uint32_t CRYPTOCcmInvAuthDecryptStatus(void); + +//***************************************************************************** +// +//! \brief Get the result of the CCM operation. +//! +//! \param ui32AuthLength is the length of the authentication field - +//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. +//! \param pui32CipherText is a pointer to the octet string encrypted message. +//! \param ui32CipherTextLength is the length of the encrypted message. +//! \param pui32CcmTag is the location of the authentication Tag. +//! +//! \return Returns AES_SUCCESS if successful. +// +//***************************************************************************** +extern uint32_t CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength, + uint32_t *pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t *pui32CcmTag); + +//***************************************************************************** +// +//! \brief Get the current status of the Crypto DMA controller. +//! +//! This function is used to poll the Crypto DMA controller to check if it is +//! ready for a new operation or if an error has occurred. +//! +//! The \ref CRYPTO_DMA_BUS_ERROR can also be caught using the crypto event +//! handler. +//! +//! \return Returns the current status of the DMA controller: +//! - \ref CRYPTO_DMA_READY : DMA ready for a new operation +//! - \ref CRYPTO_DMA_BSY : DMA is busy +//! - \ref CRYPTO_DMA_BUS_ERROR : DMA Bus error +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CRYPTODmaStatus(void) +{ + // Return the value of the status register. + return (HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT)); +} + +//***************************************************************************** +// +//! \brief Enable Crypto DMA operation. +//! +//! The specified Crypto DMA channels are enabled. +//! +//! \param ui32Channels is a bitwise OR of the channels to enable. +//! - \ref CRYPTO_DMA_CHAN0 +//! - \ref CRYPTO_DMA_CHAN1 +//! +//! \return None +// +//***************************************************************************** +extern void CRYPTODmaEnable(uint32_t ui32Channels); + +//***************************************************************************** +// +//! \brief Disable Crypto DMA operation. +//! +//! The specified Crypto DMA channels are disabled. +//! +//! \param ui32Channels is a bitwise OR of the channels to disable. +//! - \ref CRYPTO_DMA_CHAN0 +//! - \ref CRYPTO_DMA_CHAN1 +//! +//! \return None +// +//***************************************************************************** +extern void CRYPTODmaDisable(uint32_t ui32Channels); + +//***************************************************************************** +// +//! \brief Enables individual Crypto interrupt sources. +//! +//! This function enables the indicated Crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref CRYPTO_DMA_IN_DONE +//! - \ref CRYPTO_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntEnable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) | + (ui32IntFlags & CRYPTO_RESULT_RDY)); + + // Using level interrupt. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; + + // Enable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual CRYPTO interrupt sources. +//! +//! This function disables the indicated Crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref CRYPTO_DMA_IN_DONE +//! - \ref CRYPTO_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntDisable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) | + (ui32IntFlags & CRYPTO_RESULT_RDY)); + + // Disable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the specified Crypto. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param bMasked whether to use raw or masked interrupt status: +//! - \c false : Raw interrupt status is required. +//! - \c true : Masked interrupt status is required. +//! +//! \return Returns the current interrupt status: +//! - \ref CRYPTO_DMA_IN_DONE +//! - \ref CRYPTO_RESULT_RDY +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CRYPTOIntStatus(bool bMasked) +{ + uint32_t ui32Mask; + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + ui32Mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); + return(ui32Mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); + } + else + { + return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & 0x00000003); + } +} + +//***************************************************************************** +// +//! \brief Clears Crypto interrupt sources. +//! +//! The specified Crypto interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref CRYPTO_DMA_IN_DONE +//! - \ref CRYPTO_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntClear(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) | + (ui32IntFlags & CRYPTO_RESULT_RDY)); + + // Clear the requested interrupt sources, + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for a Crypto interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific UART interrupts must be enabled via \ref CRYPTOIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, pfnHandler); + + // Enable the UART interrupt. + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a Crypto interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a Crypto interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +CRYPTOIntUnregister(void) +{ + // Disable the interrupt. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_CRYPTOAesLoadKey + #undef CRYPTOAesLoadKey + #define CRYPTOAesLoadKey ROM_CRYPTOAesLoadKey + #endif + #ifdef ROM_CRYPTOAesCbc + #undef CRYPTOAesCbc + #define CRYPTOAesCbc ROM_CRYPTOAesCbc + #endif + #ifdef ROM_CRYPTOAesCbcStatus + #undef CRYPTOAesCbcStatus + #define CRYPTOAesCbcStatus ROM_CRYPTOAesCbcStatus + #endif + #ifdef ROM_CRYPTOAesEcb + #undef CRYPTOAesEcb + #define CRYPTOAesEcb ROM_CRYPTOAesEcb + #endif + #ifdef ROM_CRYPTOAesEcbStatus + #undef CRYPTOAesEcbStatus + #define CRYPTOAesEcbStatus ROM_CRYPTOAesEcbStatus + #endif + #ifdef ROM_CRYPTOCcmAuthEncrypt + #undef CRYPTOCcmAuthEncrypt + #define CRYPTOCcmAuthEncrypt ROM_CRYPTOCcmAuthEncrypt + #endif + #ifdef ROM_CRYPTOCcmAuthEncryptStatus + #undef CRYPTOCcmAuthEncryptStatus + #define CRYPTOCcmAuthEncryptStatus ROM_CRYPTOCcmAuthEncryptStatus + #endif + #ifdef ROM_CRYPTOCcmAuthEncryptResultGet + #undef CRYPTOCcmAuthEncryptResultGet + #define CRYPTOCcmAuthEncryptResultGet ROM_CRYPTOCcmAuthEncryptResultGet + #endif + #ifdef ROM_CRYPTOCcmInvAuthDecrypt + #undef CRYPTOCcmInvAuthDecrypt + #define CRYPTOCcmInvAuthDecrypt ROM_CRYPTOCcmInvAuthDecrypt + #endif + #ifdef ROM_CRYPTOCcmInvAuthDecryptStatus + #undef CRYPTOCcmInvAuthDecryptStatus + #define CRYPTOCcmInvAuthDecryptStatus ROM_CRYPTOCcmInvAuthDecryptStatus + #endif + #ifdef ROM_CRYPTOCcmInvAuthDecryptResultGet + #undef CRYPTOCcmInvAuthDecryptResultGet + #define CRYPTOCcmInvAuthDecryptResultGet ROM_CRYPTOCcmInvAuthDecryptResultGet + #endif + #ifdef ROM_CRYPTODmaEnable + #undef CRYPTODmaEnable + #define CRYPTODmaEnable ROM_CRYPTODmaEnable + #endif + #ifdef ROM_CRYPTODmaDisable + #undef CRYPTODmaDisable + #define CRYPTODmaDisable ROM_CRYPTODmaDisable + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CRYPTO_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi.c new file mode 100644 index 0000000..274a69c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi.c @@ -0,0 +1,214 @@ +/****************************************************************************** +* Filename: ddi.c +* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) +* Revision: 52111 +* +* Description: Driver for the DDI master interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ddi.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef DDI32RegWrite + #define DDI32RegWrite NOROM_DDI32RegWrite + #undef DDI16BitWrite + #define DDI16BitWrite NOROM_DDI16BitWrite + #undef DDI16BitfieldWrite + #define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite + #undef DDI16BitRead + #define DDI16BitRead NOROM_DDI16BitRead + #undef DDI16BitfieldRead + #define DDI16BitfieldRead NOROM_DDI16BitfieldRead +#endif + +//***************************************************************************** +// +// Write a 32 bit value to a register in the DDI slave. +// +//***************************************************************************** +void +DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Val) +{ + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Write the value to the register. + AuxAdiDdiSafeWrite(ui32Base + ui32Reg, ui32Val, 4); +} + +//***************************************************************************** +// +// Write a single bit using a 16-bit maskable write +// +//***************************************************************************** +void +DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32WrData) +{ + uint32_t ui32RegAddr; + uint32_t ui32Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(!((ui32Mask & 0xFFFF0000) ^ (ui32Mask & 0x0000FFFF))); + ASSERT(!(ui32WrData & 0xFFFF0000)); + + // DDI 16-bit target is on 32-bit boundary so double offset + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // Adjust for target bit in high half of the word. + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 4; + ui32Mask >>= 16; + } + + // Write mask if data is not zero (to set mask bit), else write '0'. + ui32Data = ui32WrData ? ui32Mask : 0x0; + + // Update the register. + AuxAdiDdiSafeWrite(ui32RegAddr, (ui32Mask << 16) | ui32Data, 4); +} + +//***************************************************************************** +// +// Write a bit field via the DDI using 16-bit maskable write +// +//***************************************************************************** +void +DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift, + uint16_t ui32Data) +{ + uint32_t ui32RegAddr; + uint32_t ui32WrData; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // 16-bit target is on 32-bit boundary so double offset. + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // Adjust for target bit in high half of the word. + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 4; + ui32Mask = ui32Mask >> 16; + } + + // Shift data in to position. + ui32WrData = ui32Data << ui32Shift; + + // Write data. + AuxAdiDdiSafeWrite(ui32RegAddr, (ui32Mask << 16) | ui32WrData, 4); +} + +//***************************************************************************** +// +// Read a bit via the DDI using 16-bit READ. +// +//***************************************************************************** +uint16_t +DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask) +{ + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // Calculate the address of the register. + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // Adjust for target bit in high half of the word. + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // Read a halfword on the DDI interface. + ui16Data = AuxAdiDdiSafeRead(ui32RegAddr, 2); + + // Mask data. + ui16Data = ui16Data & ui32Mask; + + // Return masked data. + return(ui16Data); +} + +//***************************************************************************** +// +// Read a bit field via the DDI using 16-bit read. +// +//***************************************************************************** +uint16_t +DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift) +{ + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // Calculate the register address. + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // Adjust for target bit in high half of the word. + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // Read the register. + ui16Data = AuxAdiDdiSafeRead(ui32RegAddr, 2); + + // Mask data and shift into place. + ui16Data &= ui32Mask; + ui16Data >>= ui32Shift; + + // Return data. + return(ui16Data); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi.h new file mode 100644 index 0000000..e3b63a0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi.h @@ -0,0 +1,559 @@ +/****************************************************************************** +* Filename: ddi.h +* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) +* Revision: 52111 +* +* Description: Defines and prototypes for the DDI master interface. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup analog_group +//! @{ +//! \addtogroup ddi_api +//! @{ +// +//***************************************************************************** + +#ifndef __DDI_H__ +#define __DDI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ddi.h" +#include "../inc/hw_aux_smph.h" +#include "debug.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define DDI32RegWrite NOROM_DDI32RegWrite + #define DDI16BitWrite NOROM_DDI16BitWrite + #define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite + #define DDI16BitRead NOROM_DDI16BitRead + #define DDI16BitfieldRead NOROM_DDI16BitfieldRead +#endif + +//***************************************************************************** +// +// Number of register in the DDI slave +// +//***************************************************************************** +#define DDI_SLAVE_REGS 64 + + +//***************************************************************************** +// +// Defines that is used to control the ADI slave and master +// +//***************************************************************************** +#define DDI_PROTECT 0x00000080 +#define DDI_ACK 0x00000001 +#define DDI_SYNC 0x00000000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + + +//***************************************************************************** +// +// Helper functions +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Safely write to AUX ADI/DDI interfaces using a semaphore. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param nAddr is the register address. +//! \param nData is the data to write to the register. +//! \param nSize is the register access size in bytes. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AuxAdiDdiSafeWrite(uint32_t nAddr, uint32_t nData, uint32_t nSize) +{ + // Disable interrupts and remember whether to re-enable + bool bIrqEnabled = !CPUcpsid(); + // Acquire semaphore for accessing ADI/DDI in AUX, perform access, release semaphore + while (!HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0)); + switch (nSize) { + case 1: HWREGB(nAddr) = (uint8_t)nData; break; + case 2: HWREGH(nAddr) = (uint16_t)nData; break; + case 4: default: HWREG(nAddr) = nData; break; + } + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0) = 1; + // Restore interrupt enable + if (bIrqEnabled) { + CPUcpsie(); + } +} + +//***************************************************************************** +// +//! \brief Safely read from AUX ADI/DDI interfaces using a semaphore. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param nAddr is the register address. +//! \param nSize is the register access size in bytes. +//! +//! \return Returns the data read. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AuxAdiDdiSafeRead(uint32_t nAddr, uint32_t nSize) +{ + uint32_t nRet; + // Disable interrupts and remember whether to re-enable + bool bIrqEnabled = !CPUcpsid(); + // Acquire semaphore for accessing ADI/DDI in AUX, perform access, release semaphore + while (!HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0)); + switch (nSize) { + case 1: nRet = HWREGB(nAddr); break; + case 2: nRet = HWREGH(nAddr); break; + case 4: default: nRet = HWREG(nAddr); break; + } + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0) = 1; + // Restore interrupt enable + if (bIrqEnabled) { + CPUcpsie(); + } + return nRet; +} + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Check a DDI base address. +//! +//! This function determines if a DDI port base address is valid. +//! +//! \param ui32Base is the base address of the DDI port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +//! +//! \endinternal +// +//***************************************************************************** +static bool +DDIBaseValid(uint32_t ui32Base) +{ + return(ui32Base == AUX_DDI0_OSC_BASE); +} +#endif + + +//***************************************************************************** +// +//! \brief Read the value in a 32 bit register. +//! +//! This function will read a register in the analog domain and return +//! the value as an \c uint32_t. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the 32 bit register to read. +//! +//! \return Returns the 32 bit value of the analog register. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +DDI32RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Read the register and return the value. + return AuxAdiDdiSafeRead(ui32Base + ui32Reg, 4); +} + +//***************************************************************************** +// +//! \brief Set specific bits in a DDI slave register. +//! +//! This function will set bits in a register in the analog domain. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in specific register in the +//! DDI slave. Only bits in the selected register are affected by the +//! operation. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to set in the register. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_SET; + + // Set the selected bits. + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + ui32Reg, ui32Val, 4); +} + +//***************************************************************************** +// +//! \brief Clear specific bits in a 32 bit DDI register. +//! +//! This function will clear bits in a register in the analog domain. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to clear in the register. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_CLR; + + // Clear the selected bits. + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + ui32Reg, ui32Val, 4); +} + +//***************************************************************************** +// +//! \brief Set a value on any 8 bits inside a 32 bit register in the DDI slave. +//! +//! This function allows byte (8 bit access) to the DDI slave registers. +//! +//! Use this function to write any value in the range 0-7 bits aligned on a +//! byte boundary. For example, for writing the value 0b101 to bits 1-3 set +//! ui16Val = 0x0A and ui16Mask = 0x0E. Bits 0 and 5-7 will +//! not be affected by the operation, as long as the corresponding bits are +//! not set in the \c ui16Mask. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is the Least Significant Register in the DDI slave that +//! will be affected by the write operation. +//! \param ui32Byte is the byte number to access within the 32 bit register. +//! \param ui16Mask is the mask defining which of the 8 bits that should be +//! overwritten. The mask must be defined in the lower half of the 16 bits. +//! \param ui16Val is the value to write. The value must be defined in the lower +//! half of the 16 bits. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Byte, + uint16_t ui16Mask, uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + ASSERT(!(ui16Val & 0xFF00)); + ASSERT(!(ui16Mask & 0xFF00)); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_MASK8B + (ui32Reg << 1) + (ui32Byte << 1); + + // Set the selected bits. + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset, (ui16Mask << 8) | ui16Val, 2); +} + +//***************************************************************************** +// +//! \brief Set a value on any 16 bits inside a 32 bit register aligned on a +//! half-word boundary in the DDI slave. +//! +//! This function allows 16 bit masked access to the DDI slave registers. +//! +//! Use this function to write any value in the range 0-15 bits aligned on a +//! half-word boundary. For example, for writing the value 0b101 to bits 1-3 set +//! ui32Val = 0x000A and ui32Mask = 0x000E. Bits 0 and 5-15 will not be +//! affected by the operation, as long as the corresponding bits are not set +//! in the \c ui32Mask. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param bWriteHigh defines which part of the register to write in. +//! \param ui32Mask is the mask defining which of the 16 bit that should be +//! overwritten. The mask must be defined in the lower half of the 32 bits. +//! \param ui32Val is the value to write. The value must be defined in the lower +//! half of the 32 bits. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh, + uint32_t ui32Mask, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + ASSERT(!(ui32Val & 0xFFFF0000)); + ASSERT(!(ui32Mask & 0xFFFF0000)); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_MASK16B + (ui32Reg << 1) + (bWriteHigh ? 4 : 0); + + // Set the selected bits. + AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset, (ui32Mask << 16) | ui32Val, 4); +} + +//***************************************************************************** +// +//! \brief Write a 32 bit value to a register in the DDI slave. +//! +//! This function will write a value to a register in the analog +//! domain. +//! +//! \note This operation is write only for the specified register. No +//! conservation of the previous value of the register will be kept (i.e. this +//! is NOT read-modify-write on the register). +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the register to write. +//! \param ui32Val is the 32 bit value to write to the register. +//! +//! \return None +// +//***************************************************************************** +extern void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val); + +//***************************************************************************** +// +//! \brief Write a single bit using a 16-bit maskable write. +//! +//! A '1' is written to the bit if \c ui32WrData is non-zero, else a '0' is written. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param ui32Mask is the mask defining which of the 16 bit that should be overwritten. +//! \param ui32WrData is the value to write. The value must be defined in the lower half of the 32 bits. +//! +//! \return None +// +//***************************************************************************** +extern void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32WrData); + + +//***************************************************************************** +// +//! \brief Write a bit field via the DDI using 16-bit maskable write. +//! +//! Requires that entire bit field is within the half word boundary. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten. +//! \param ui32Shift is the shift value for the bit field. +//! \param ui32Data is the data aligned to bit 0. +//! +//! \return None +// +//***************************************************************************** +extern void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift, + uint16_t ui32Data); + +//***************************************************************************** +// +//! \brief Read a bit via the DDI using 16-bit read. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the DDI module. +//! \param ui32Reg is the register to read. +//! \param ui32Mask defines the bit which should be read. +//! +//! \return Returns a zero if bit selected by mask is '0'. Else returns the mask. +// +//***************************************************************************** +extern uint16_t DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask); + +//***************************************************************************** +// +//! \brief Read a bit field via the DDI using 16-bit read. +//! +//! Requires that entire bit field is within the half word boundary. +//! +//! \note Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten. +//! \param ui32Shift defines the required shift of the data to align with bit 0. +//! +//! \return Returns data aligned to bit 0. +// +//***************************************************************************** +extern uint16_t DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_DDI32RegWrite + #undef DDI32RegWrite + #define DDI32RegWrite ROM_DDI32RegWrite + #endif + #ifdef ROM_DDI16BitWrite + #undef DDI16BitWrite + #define DDI16BitWrite ROM_DDI16BitWrite + #endif + #ifdef ROM_DDI16BitfieldWrite + #undef DDI16BitfieldWrite + #define DDI16BitfieldWrite ROM_DDI16BitfieldWrite + #endif + #ifdef ROM_DDI16BitRead + #undef DDI16BitRead + #define DDI16BitRead ROM_DDI16BitRead + #endif + #ifdef ROM_DDI16BitfieldRead + #undef DDI16BitfieldRead + #define DDI16BitfieldRead ROM_DDI16BitfieldRead + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DDI_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi_doc.h new file mode 100644 index 0000000..1c96d73 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi_doc.h @@ -0,0 +1,70 @@ +/****************************************************************************** +* Filename: ddi_doc.h +* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) +* Revision: 47080 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup ddi_api +//! @{ +//! \section sec_ddi Introduction +//! \n +//! +//! \section sec_ddi_api API +//! +//! The API functions can be grouped like this: +//! +//! Write: +//! - Direct (all bits): +//! - \ref DDI32RegWrite() +//! - Set individual bits: +//! - \ref DDI32BitsSet() +//! - Clear individual bits: +//! - \ref DDI32BitsClear() +//! - Masked: +//! - \ref DDI8SetValBit() +//! - \ref DDI16SetValBit() +//! - Special functions using masked write: +//! - \ref DDI16BitWrite() +//! - \ref DDI16BitfieldWrite() +//! +//! Read: +//! - Direct (all bits): +//! - \ref DDI32RegRead() +//! - Special functions using masked read: +//! - \ref DDI16BitRead() +//! - \ref DDI16BitfieldRead() +//! +//! AUX access using semaphores (used by both ADI and DDI APIs when necessary): +//! - \ref AuxAdiDdiSafeRead() +//! - \ref AuxAdiDdiSafeWrite() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/debug.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/debug.c new file mode 100644 index 0000000..5626638 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/debug.c @@ -0,0 +1,57 @@ +/****************************************************************************** +* Filename: debug.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the Debug functionality (NB. This is a stub which +* should never be included in a release). +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include +#include "../inc/hw_types.h" +#include "debug.h" + +//***************************************************************************** +// +// Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted. +// +//***************************************************************************** +void +__error__(char *pcFilename, uint32_t ui32Line) +{ + // Error catching. + // User can implement custom error handling for failing ASSERTs. + // Setting breakpoint here allows tracing of the failing ASSERT. + while( true ); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/debug.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/debug.h new file mode 100644 index 0000000..704fd5c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/debug.h @@ -0,0 +1,84 @@ +/****************************************************************************** +* Filename: debug.h +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Macros for assisting debug of the driver library. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup debug_api +//! @{ +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +//! Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted. +// +//***************************************************************************** +extern void __error__(char *pcFilename, uint32_t ui32Line); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DRIVERLIB_DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } + +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/driverlib_release.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/driverlib_release.c new file mode 100644 index 0000000..ca51532 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/driverlib_release.c @@ -0,0 +1,45 @@ +/****************************************************************************** +* Filename: driverlib_release.c +* Revised: $Date: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) $ +* Revision: $Revision: 47152 $ +* +* Description: Provides macros for ensuring that a specfic release of +* DriverLib is used. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#include "../driverlib/driverlib_release.h" + + + + +/// Declare the current DriverLib release +DRIVERLIB_DECLARE_RELEASE(0, 54539); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/driverlib_release.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/driverlib_release.h new file mode 100644 index 0000000..b7a0434 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/driverlib_release.h @@ -0,0 +1,156 @@ +/****************************************************************************** +* Filename: driverlib_release.h +* Revised: $Date: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015) $ +* Revision: $Revision: 44151 $ +* +* Description: Provides macros for ensuring that a specfic release of +* DriverLib is used. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup driverlib_release_api +//! @{ +// +//***************************************************************************** + +#ifndef __DRIVERLIB_RELEASE_H__ +#define __DRIVERLIB_RELEASE_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + + + + +/// DriverLib release group number +#define DRIVERLIB_RELEASE_GROUP 0 +/// DriverLib release build number +#define DRIVERLIB_RELEASE_BUILD 54539 + + + + +//***************************************************************************** +// +//! This macro is called internally from within DriverLib to declare the +//! DriverLib release locking object: +//! \param group is the DriverLib release group number. +//! \param build is the DriverLib release build number. +//! +//! This macro shall not be called in the application unless the intention is +//! to bypass the release locking (at own risk). +// +//***************************************************************************** +#define DRIVERLIB_DECLARE_RELEASE(group, build) \ + const volatile uint8_t driverlib_release_##group##_##build + +/// External declaration of the DriverLib release locking object +extern DRIVERLIB_DECLARE_RELEASE(0, 54539); + + + + +//***************************************************************************** +// +//! This macro shall be called once from within a function of a precompiled +//! software deliverable to lock the deliverable to a specific DriverLib +//! release. It is essential that the call is made from code that is not +//! optimized away. +//! +//! This macro locks to a specific DriverLib release: +//! \param group is the DriverLib release group number. +//! \param build is the DriverLib release build number. +//! +//! If attempting to use the precompiled deliverable with a different release +//! of DriverLib, a linker error will be produced, stating that +//! "driverlib_release_xx_yyyyy is undefined" or similar. +//! +//! To override the check, for example when upgrading DriverLib but not the +//! precompiled deliverables, or when mixing precompiled deliverables, +//! application developers may (at own risk) declare the missing DriverLib +//! release using the \ref DRIVERLIB_DECLARE_RELEASE() macro. +// +//***************************************************************************** +#define DRIVERLIB_ASSERT_RELEASE(group, build) \ + (driverlib_release_##group##_##build) + + + + +//***************************************************************************** +// +//! This macro shall be called once from within a function of a precompiled +//! software deliverable to lock the deliverable to a specific DriverLib +//! release. It is essential that the call is made from code that is not +//! optimized away. +//! +//! This macro locks to the current DriverLib release used at compile-time. +//! +//! If attempting to use the precompiled deliverable with a different release +//! of DriverLib, a linker error will be produced, stating that +//! "driverlib_release_xx_yyyyy is undefined" or similar. +//! +//! To override the check, for example when upgrading DriverLib but not the +//! precompiled deliverables, or when mixing precompiled deliverables, +//! application developers may (at own risk) declare the missing DriverLib +//! release using the \ref DRIVERLIB_DECLARE_RELEASE() macro. +// +//***************************************************************************** +#define DRIVERLIB_ASSERT_CURR_RELEASE() \ + DRIVERLIB_ASSERT_RELEASE(0, 54539) + + + + +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_RELEASE_H__ + + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event.c new file mode 100644 index 0000000..0d44d43 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: event.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the Event Fabric. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "event.h" + +// See event.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event.h new file mode 100644 index 0000000..2f84902 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event.h @@ -0,0 +1,267 @@ +/****************************************************************************** +* Filename: event.h +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Defines and prototypes for the Event Handler. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup event_api +//! @{ +// +//***************************************************************************** + +#ifndef __EVENT_H__ +#define __EVENT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_event.h" +#include "debug.h" + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Connects an event to an event subscriber via Event Fabric. +//! +//! This function connects event sources to event subscribers. +//! +//! It is not possible to read event status in this module (except software events). +//! Event status must be read in the module that contains the event source. How a +//! specific event subscriber reacts to an event is configured and documented in +//! the respective modules. +//! +//! For a full list of configurable and constant mapped event sources to event +//! subscribers see the register descriptions for +//! Event Fabric. +//! +//! Defines for event subscriber argument (\c ui32EventSubscriber) have the format: +//! - \ti_code{EVENT_O_[subscriber_name]} +//! +//! Defines for event source argument (\c ui32EventSource) must have the +//! following format where valid \c event_enum values are found in the +//! register description : +//! - \ti_code{EVENT_[subscriber_name]_EV_[event_enum]} +//! +//! Examples of valid defines for \c ui32EventSource: +//! - EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE +//! - EVENT_RFCSEL9_EV_AUX_COMPA +//! - EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD +//! +//! \note Each event subscriber can only receive a sub-set of the event sources! +//! +//! \note Switching the event source is not glitch free, so it is imperative +//! that the subscriber is disabled for interrupts when switching the event +//! source. The behavior is undefined if not disabled. +//! +//! \param ui32EventSubscriber is the \b configurable event subscriber to receive the event. +//! Click the event subscriber to see the list of valid event sources in the +//! register description. +//! - EVENT_O_CPUIRQSEL30 : System CPU interrupt 30 +//! - EVENT_O_RFCSEL9 : RF Core event 9 +//! - EVENT_O_GPT0ACAPTSEL : GPT 0A capture event +//! - EVENT_O_GPT0BCAPTSEL : GPT 0B capture event +//! - EVENT_O_GPT1ACAPTSEL : GPT 1A capture event +//! - EVENT_O_GPT1BCAPTSEL : GPT 1B capture event +//! - EVENT_O_GPT2ACAPTSEL : GPT 2A capture event +//! - EVENT_O_GPT2BCAPTSEL : GPT 2B capture event +//! - EVENT_O_GPT3ACAPTSEL : GPT 3A capture event +//! - EVENT_O_GPT3BCAPTSEL : GPT 3B capture event +//! - EVENT_O_UDMACH9SSEL : uDMA channel 9 single request +//! - EVENT_O_UDMACH9BSEL : uDMA channel 9 burst request +//! - EVENT_O_UDMACH10SSEL : uDMA channel 10 single request +//! - EVENT_O_UDMACH10BSEL : uDMA channel 10 burst request +//! - EVENT_O_UDMACH11SSEL : uDMA channel 11 single request +//! - EVENT_O_UDMACH11BSEL : uDMA channel 11 burst request +//! - EVENT_O_UDMACH12SSEL : uDMA channel 12 single request +//! - EVENT_O_UDMACH12BSEL : uDMA channel 12 burst request +//! - EVENT_O_UDMACH14BSEL : uDMA channel 14 single request +//! - EVENT_O_AUXSEL0 : AUX +//! - EVENT_O_I2SSTMPSEL0 : I2S +//! - EVENT_O_FRZSEL0 : Freeze modules (some modules can freeze on CPU Halt) +//! \param ui32EventSource is the specific event that must be acted upon. +//! - Format: \ti_code{EVENT_[subscriber_name]_EV_[event_enum]} (see explanation above) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +EventRegister(uint32_t ui32EventSubscriber, uint32_t ui32EventSource) +{ + // Check the arguments. + ASSERT(( ui32EventSubscriber == EVENT_O_CPUIRQSEL30 ) || + ( ui32EventSubscriber == EVENT_O_RFCSEL9 ) || + ( ui32EventSubscriber == EVENT_O_GPT0ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT0BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT1ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT1BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT2ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT2BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT3ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT3BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH9SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH9BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH10SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH10BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH11SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH11BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH12SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH12BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH14BSEL ) || + ( ui32EventSubscriber == EVENT_O_AUXSEL0 ) || + ( ui32EventSubscriber == EVENT_O_I2SSTMPSEL0 ) || + ( ui32EventSubscriber == EVENT_O_FRZSEL0 ) ); + + // Map the event source to the event subscriber + HWREG(EVENT_BASE + ui32EventSubscriber) = ui32EventSource; +} + +//***************************************************************************** +// +//! \brief Sets software event. +//! +//! Setting a software event triggers the event if the value was 0 before. +//! +//! \note The software event must be cleared manually after the event has +//! triggered the event subscriber. +//! +//! \param ui32SwEvent is the software event number. +//! - 0 : SW Event 0 +//! - 1 : SW Event 1 +//! - 2 : SW Event 2 +//! - 3 : SW Event 3 +//! +//! \return None +//! +//! \sa \ref EventSwEventClear() +// +//***************************************************************************** +__STATIC_INLINE void +EventSwEventSet(uint32_t ui32SwEvent) +{ + // Check the arguments. + ASSERT( ui32SwEvent <= 3 ); + + // Each software event is byte accessible + HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 1; +} + +//***************************************************************************** +// +//! \brief Clears software event. +//! +//! \param ui32SwEvent is the software event number. +//! - 0 : SW Event 0 +//! - 1 : SW Event 1 +//! - 2 : SW Event 2 +//! - 3 : SW Event 3 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +EventSwEventClear(uint32_t ui32SwEvent) +{ + // Check the arguments. + ASSERT( ui32SwEvent <= 3 ); + + // Each software event is byte accessible + HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 0; +} + +//***************************************************************************** +// +//! \brief Gets software event status. +//! +//! \param ui32SwEvent is the software event number. +//! - 0 : SW Event 0 +//! - 1 : SW Event 1 +//! - 2 : SW Event 2 +//! - 3 : SW Event 3 +//! +//! \return Returns current value of requested software event. +//! - 0 : Software event is de-asserted. +//! - 1 : Software event is asserted. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +EventSwEventGet(uint32_t ui32SwEvent) +{ + // Check the arguments. + ASSERT( ui32SwEvent <= 3 ); + + // Each software event is byte accessible + return( HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent)); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __EVENT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event_doc.h new file mode 100644 index 0000000..a17b238 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event_doc.h @@ -0,0 +1,58 @@ +/****************************************************************************** +* Filename: event_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup event_api +//! @{ +//! \section sec_event Introduction +//! +//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and +//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers +//! to the AON event fabric. For more information on AON event fabric, see [AON event API](@ref aonevent_api). +//! +//! The MCU event fabric is a combinational router between event sources and event subscribers. Most +//! event subscribers have statically routed event sources but several event subscribers have +//! configurable event sources which is configured in the MCU event fabric through this API. Although +//! configurable only a subset of event sources are available to each of the configurable event subscribers. +//! This is explained in more details in the function @ref EventRegister() which does all the event routing +//! configuration. +//! +//! MCU event fabric also contains four software events which allow software to trigger certain event +//! subscribers. Each of the four software events is an independent event source which must be set and +//! cleared in the MCU event fabric through the functions: +//! - @ref EventSwEventSet() +//! - @ref EventSwEventClear() +//! - @ref EventSwEventGet() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/flash.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/flash.c new file mode 100644 index 0000000..5fcd34d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/flash.c @@ -0,0 +1,672 @@ +/****************************************************************************** +* Filename: flash.c +* Revised: 2017-10-30 13:37:49 +0100 (Mon, 30 Oct 2017) +* Revision: 50105 +* +* Description: Driver for on chip Flash. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "flash.h" +#include "rom.h" +#include "chipinfo.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef FlashPowerModeSet + #define FlashPowerModeSet NOROM_FlashPowerModeSet + #undef FlashPowerModeGet + #define FlashPowerModeGet NOROM_FlashPowerModeGet + #undef FlashProtectionSet + #define FlashProtectionSet NOROM_FlashProtectionSet + #undef FlashProtectionGet + #define FlashProtectionGet NOROM_FlashProtectionGet + #undef FlashProtectionSave + #define FlashProtectionSave NOROM_FlashProtectionSave + #undef FlashSectorErase + #define FlashSectorErase NOROM_FlashSectorErase + #undef FlashProgram + #define FlashProgram NOROM_FlashProgram + #undef FlashEfuseReadRow + #define FlashEfuseReadRow NOROM_FlashEfuseReadRow + #undef FlashDisableSectorsForWrite + #define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite +#endif + + +//***************************************************************************** +// +// Defines for accesses to the security control in the customer configuration +// area in flash top sector. +// +//***************************************************************************** +#define CCFG_OFFSET_SECURITY CCFG_O_BL_CONFIG +#define CCFG_OFFSET_SECT_PROT CCFG_O_CCFG_PROT_31_0 +#define CCFG_SIZE_SECURITY 0x00000014 +#define CCFG_SIZE_SECT_PROT 0x00000004 + +//***************************************************************************** +// +// Default values for security control in customer configuration area in flash +// top sector. +// +//***************************************************************************** +const uint8_t g_pui8CcfgDefaultSec[] = {0xFF, 0xFF, 0xFF, 0xC5, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xC5, 0xFF, 0xFF, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF + }; + +typedef uint32_t (* FlashPrgPointer_t) (uint8_t *, uint32_t, uint32_t); + +typedef uint32_t (* FlashSectorErasePointer_t) (uint32_t); + +//***************************************************************************** +// +// Function prototypes for static functions +// +//***************************************************************************** +static void SetReadMode(void); + +//***************************************************************************** +// +// Set power mode +// +//***************************************************************************** +void +FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, + uint32_t ui32PumpGracePeriod) +{ + // Check the arguments. + ASSERT(ui32PowerMode == FLASH_PWR_ACTIVE_MODE || + ui32PowerMode == FLASH_PWR_OFF_MODE || + ui32PowerMode == FLASH_PWR_DEEP_STDBY_MODE); + ASSERT(ui32BankGracePeriod <= 0xFF); + ASSERT(ui32PumpGracePeriod <= 0xFFFF); + + switch(ui32PowerMode) + { + case FLASH_PWR_ACTIVE_MODE: + // Set bank power mode to ACTIVE. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = + (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_ACTIVE; + + // Set charge pump power mode to ACTIVE mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) = + (HWREG(FLASH_BASE + FLASH_O_FPAC1) & ~FLASH_FPAC1_PUMPPWR_M) | (1 << FLASH_FPAC1_PUMPPWR_S); + break; + + case FLASH_PWR_OFF_MODE: + // Set bank grace period. + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // Set pump grace period. + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // Set bank power mode to SLEEP. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= ~FLASH_FBFALLBACK_BANKPWR0_M; + + // Set charge pump power mode to SLEEP mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M; + break; + + case FLASH_PWR_DEEP_STDBY_MODE: + // Set bank grace period. + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // Set pump grace period. + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // Set bank power mode to DEEP STANDBY mode. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = + (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_DEEP_STDBY; + + // Set charge pump power mode to STANDBY mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) |= FLASH_FPAC1_PUMPPWR_M; + break; + } +} + +//***************************************************************************** +// +// Get current configured power mode +// +//***************************************************************************** +uint32_t +FlashPowerModeGet(void) +{ + uint32_t ui32PowerMode; + uint32_t ui32BankPwrMode; + + ui32BankPwrMode = HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + FLASH_FBFALLBACK_BANKPWR0_M; + + if(ui32BankPwrMode == FBFALLBACK_SLEEP) + { + ui32PowerMode = FLASH_PWR_OFF_MODE; + } + else if(ui32BankPwrMode == FBFALLBACK_DEEP_STDBY) + { + ui32PowerMode = FLASH_PWR_DEEP_STDBY_MODE; + } + else + { + ui32PowerMode = FLASH_PWR_ACTIVE_MODE; + } + + // Return power mode. + return(ui32PowerMode); +} + +//***************************************************************************** +// +// Set sector protection +// +//***************************************************************************** +void +FlashProtectionSet(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode) +{ + uint32_t ui32SectorNumber; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(ui32ProtectMode == FLASH_WRITE_PROTECT) + { + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / + FlashSectorSizeGet(); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + if(ui32SectorNumber <= 31) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber); + } + else if(ui32SectorNumber <= 63) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |= + (1 << (ui32SectorNumber & 0x1F)); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |= + (1 << (ui32SectorNumber & 0x1F)); + } + + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } +} + +//***************************************************************************** +// +// Get sector protection +// +//***************************************************************************** +uint32_t +FlashProtectionGet(uint32_t ui32SectorAddress) +{ + uint32_t ui32SectorProtect; + uint32_t ui32SectorNumber; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + ui32SectorProtect = FLASH_NO_PROTECT; + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + + if(ui32SectorNumber <= 31) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + else if(ui32SectorNumber <= 63) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) & + (1 << (ui32SectorNumber & 0x1F))) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) & + (1 << (ui32SectorNumber & 0x1F)))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + + return(ui32SectorProtect); +} + +//***************************************************************************** +// +// Save sector protection to make it permanent +// +//***************************************************************************** +uint32_t +FlashProtectionSave(uint32_t ui32SectorAddress) +{ + uint32_t ui32ErrorReturn; + uint32_t ui32SectorNumber; + uint32_t ui32CcfgSectorAddr; + uint32_t ui32ProgBuf; + + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(FlashProtectionGet(ui32SectorAddress) == FLASH_WRITE_PROTECT) + { + // Find sector number for specified sector. + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + ui32CcfgSectorAddr = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); + + // Adjust CCFG address to the 32-bit CCFG word holding the + // protect-bit for the specified sector. + ui32CcfgSectorAddr += (((ui32SectorNumber >> 5) * 4) + CCFG_OFFSET_SECT_PROT); + + // Find value to program by setting the protect-bit which + // corresponds to specified sector number, to 0. + // Leave other protect-bits unchanged. + ui32ProgBuf = (~(1 << (ui32SectorNumber & 0x1F))) & + *(uint32_t *)ui32CcfgSectorAddr; + + ui32ErrorReturn = FlashProgram((uint8_t*)&ui32ProgBuf, ui32CcfgSectorAddr, + CCFG_SIZE_SECT_PROT); + } + + // Return status. + return(ui32ErrorReturn); +} + +//***************************************************************************** +// +// Erase a flash sector +// +//***************************************************************************** +uint32_t +FlashSectorErase(uint32_t ui32SectorAddress) +{ + uint32_t ui32ErrorReturn; + FlashSectorErasePointer_t FuncPointer; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + // Call ROM function that handles the actual erase operation + FuncPointer = (uint32_t (*)(uint32_t)) (ROM_API_FLASH_TABLE[5]); + ui32ErrorReturn = FuncPointer(ui32SectorAddress); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); + +} + + +//***************************************************************************** +// +// Programs unprotected main bank flash sectors +// +//***************************************************************************** +uint32_t +FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) +{ + uint32_t ui32ErrorReturn; + FlashPrgPointer_t FuncPointer; + + // Check the arguments. + ASSERT((ui32Address + ui32Count) <= (FLASHMEM_BASE + FlashSizeGet())); + + // Call ROM function that handles the actual program operation + FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ROM_API_FLASH_TABLE[6]); + ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); + +} + +//***************************************************************************** +// +// Reads efuse data from specified row +// +//***************************************************************************** +bool +FlashEfuseReadRow(uint32_t *pui32EfuseData, uint32_t ui32RowAddress) +{ + bool bStatus; + + // Make sure the clock for the efuse is enabled + HWREG(FLASH_BASE + FLASH_O_CFG) &= ~FLASH_CFG_DIS_EFUSECLK; + + // Set timing for EFUSE read operations. + HWREG(FLASH_BASE + FLASH_O_EFUSEREAD) |= ((5 << FLASH_EFUSEREAD_READCLOCK_S) & + FLASH_EFUSEREAD_READCLOCK_M); + + // Clear status register. + HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) = 0; + + // Select the FuseROM block 0. + HWREG(FLASH_BASE + FLASH_O_EFUSEADDR) = 0x00000000; + + // Start the read operation. + HWREG(FLASH_BASE + FLASH_O_EFUSE) = + (DUMPWORD_INSTR << FLASH_EFUSE_INSTRUCTION_S) | + (ui32RowAddress & FLASH_EFUSE_DUMPWORD_M); + + // Wait for operation to finish. + while(!(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_DONE)) + { + } + + // Check if error reported. + if(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_CODE_M) + { + // Set error status. + bStatus = 1; + + // Clear data. + *pui32EfuseData = 0; + } + else + { + // Set ok status. + bStatus = 0; + + // No error. Get data from data register. + *pui32EfuseData = HWREG(FLASH_BASE + FLASH_O_DATALOWER); + } + + // Disable the efuse clock to conserve power + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_EFUSECLK; + + // Return the data. + return(bStatus); +} + + +//***************************************************************************** +// +// Disables all sectors for erase and programming on the active bank +// +//***************************************************************************** +void +FlashDisableSectorsForWrite(void) +{ + // Configure flash back to read mode + SetReadMode(); + + // Disable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + // Disable all sectors for erase and programming. + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; + + // Enable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Protect sectors from sector erase. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \internal +//! Used to set flash in read mode. +//! +//! Flash is configured with values loaded from OTP dependent on the current +//! regulator mode. +//! +//! \return None. +// +//***************************************************************************** +static void +SetReadMode(void) +{ + uint32_t ui32TrimValue; + uint32_t ui32Value; + + // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + // VIN_AT_X and VIN_BY_PASS for read mode + if(HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL) & + AON_SYSCTL_PWRCTL_EXT_REG_MODE) + { + // Select trim values for external regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 4). + // Configure DIS_IDLE (OTP offset 0x308 bit 3). + ui32Value |= ((ui32TrimValue & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // Wait for disabled sample and hold functionality to be stable. + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 2:0) + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } + else + { + // Select trim values for internal regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 12). + // Configure DIS_IDLE (OTP offset 0x308 bit 11). + ui32Value |= ((ui32TrimValue & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // Wait for disabled sample and hold functionality to be stable. + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 10:8) + ui32Value = (((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S); + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} + +//***************************************************************************** +// +// HAPI Flash program function +// +//***************************************************************************** +uint32_t +MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer, uint32_t ui32Address, + uint32_t ui32Count) +{ + uint32_t ui32ErrorReturn; + FlashPrgPointer_t FuncPointer; + uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (5 * 4)); + + // Call ROM function + FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ui32RomAddr); + ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); +} + +//***************************************************************************** +// +// HAPI Flash sector erase function +// +//***************************************************************************** +uint32_t +MemBusWrkAroundHapiEraseSector(uint32_t ui32Address) +{ + uint32_t ui32ErrorReturn; + + FlashSectorErasePointer_t FuncPointer; + uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (3 * 4)); + + // Call ROM function + FuncPointer = (uint32_t (*)(uint32_t)) (ui32RomAddr); + ui32ErrorReturn = FuncPointer(ui32Address); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/flash.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/flash.h new file mode 100644 index 0000000..75b7da4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/flash.h @@ -0,0 +1,817 @@ +/****************************************************************************** +* Filename: flash.h +* Revised: 2017-11-02 16:09:32 +0100 (Thu, 02 Nov 2017) +* Revision: 50166 +* +* Description: Defines and prototypes for the Flash driver. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_flash.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aon_sysctl.h" +#include "../inc/hw_fcfg1.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define FlashPowerModeSet NOROM_FlashPowerModeSet + #define FlashPowerModeGet NOROM_FlashPowerModeGet + #define FlashProtectionSet NOROM_FlashProtectionSet + #define FlashProtectionGet NOROM_FlashProtectionGet + #define FlashProtectionSave NOROM_FlashProtectionSave + #define FlashSectorErase NOROM_FlashSectorErase + #define FlashProgram NOROM_FlashProgram + #define FlashEfuseReadRow NOROM_FlashEfuseReadRow + #define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite +#endif + +//***************************************************************************** +// +// Values that can be returned from the API functions +// +//***************************************************************************** +#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully +#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy +#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready +#define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH \ + 0x00000003 // Incorrect parameter value +#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed + +//***************************************************************************** +// +// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and +// returned from FlashIntStatus(). +// +//***************************************************************************** +#define FLASH_INT_FSM_DONE 0x00400000 // FSM Done Interrupt Mask +#define FLASH_INT_RV 0x00010000 // Read Verify error Interrupt Mask + +//***************************************************************************** +// +// Values passed to FlashSetPowerMode() and returned from FlashGetPowerMode(). +// +//***************************************************************************** +#define FLASH_PWR_ACTIVE_MODE 0x00000000 +#define FLASH_PWR_OFF_MODE 0x00000001 +#define FLASH_PWR_DEEP_STDBY_MODE \ + 0x00000002 + +//***************************************************************************** +// +// Values passed to FlashSetProtection() and returned from FlashGetProtection(). +// +//***************************************************************************** +#define FLASH_NO_PROTECT 0x00000000 // Sector not protected +#define FLASH_WRITE_PROTECT 0x00000001 // Sector erase and program + // protected + +//***************************************************************************** +// +// Define used by the flash programming and erase functions +// +//***************************************************************************** +#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE) + +//***************************************************************************** +// +// Define used for access to factory configuration area. +// +//***************************************************************************** +#define FCFG1_OFFSET 0x1000 + +//***************************************************************************** +// +// Define for the clock frequency input to the flash module in number of MHz +// +//***************************************************************************** +#define FLASH_MODULE_CLK_FREQ 48 + +//***************************************************************************** +// +//! \brief Defined values for Flash State Machine commands +// +//***************************************************************************** +typedef enum +{ + FAPI_PROGRAM_DATA = 0x0002, //!< Program data. + FAPI_ERASE_SECTOR = 0x0006, //!< Erase sector. + FAPI_ERASE_BANK = 0x0008, //!< Erase bank. + FAPI_VALIDATE_SECTOR = 0x000E, //!< Validate sector. + FAPI_CLEAR_STATUS = 0x0010, //!< Clear status. + FAPI_PROGRAM_RESUME = 0x0014, //!< Program resume. + FAPI_ERASE_RESUME = 0x0016, //!< Erase resume. + FAPI_CLEAR_MORE = 0x0018, //!< Clear more. + FAPI_PROGRAM_SECTOR = 0x0020, //!< Program sector. + FAPI_ERASE_OTP = 0x0030 //!< Erase OTP. +} tFlashStateCommandsType; + +//***************************************************************************** +// +// Defines for values written to the FLASH_O_FSM_WR_ENA register +// +//***************************************************************************** +#define FSM_REG_WRT_ENABLE 5 +#define FSM_REG_WRT_DISABLE 2 + +//***************************************************************************** +// +// Defines for the bank power mode field the FLASH_O_FBFALLBACK register +// +//***************************************************************************** +#define FBFALLBACK_SLEEP 0 +#define FBFALLBACK_DEEP_STDBY 1 +#define FBFALLBACK_ACTIVE 3 + +//***************************************************************************** +// +// Defines for the bank grace period and pump grace period +// +//***************************************************************************** +#define FLASH_BAGP 0x14 +#define FLASH_PAGP 0x14 + +//***************************************************************************** +// +// Defines used by the FlashProgramPattern() function +// +//***************************************************************************** +#define PATTERN_BITS 0x20 // No of bits in data pattern to program + +//***************************************************************************** +// +// Defines for the FW flag bits in the FLASH_O_FWFLAG register +// +//***************************************************************************** +#define FW_WRT_TRIMMED 0x00000001 + +//***************************************************************************** +// +// Defines used by the flash programming functions +// +//***************************************************************************** +typedef volatile uint8_t tFwpWriteByte; +#define FWPWRITE_BYTE_ADDRESS ((tFwpWriteByte *)((FLASH_BASE + FLASH_O_FWPWRITE0))) + +//***************************************************************************** +// +// Define for efuse instruction +// +//***************************************************************************** +#define DUMPWORD_INSTR 0x04 + +//***************************************************************************** +// +// Define for FSM command execution +// +//***************************************************************************** +#define FLASH_CMD_EXEC 0x15 + +//***************************************************************************** +// +//! \brief Get size of a flash sector in number of bytes. +//! +//! This function will return the size of a flash sector in number of bytes. +//! +//! \return Returns size of a flash sector in number of bytes. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashSectorSizeGet(void) +{ + uint32_t ui32SectorSizeInKbyte; + + ui32SectorSizeInKbyte = (HWREG(FLASH_BASE + FLASH_O_FCFG_B0_SSIZE0) & + FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M) >> + FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S; + + // Return flash sector size in number of bytes. + return(ui32SectorSizeInKbyte * 1024); +} + +//***************************************************************************** +// +//! \brief Get the size of the flash. +//! +//! This function returns the size of the flash main bank in number of bytes. +//! +//! \return Returns the flash size in number of bytes. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashSizeGet(void) +{ + uint32_t ui32NoOfSectors; + + // Get number of flash sectors + ui32NoOfSectors = (HWREG(FLASH_BASE + FLASH_O_FLASH_SIZE) & + FLASH_FLASH_SIZE_SECTORS_M) >> + FLASH_FLASH_SIZE_SECTORS_S; + + // Return flash size in number of bytes + return(ui32NoOfSectors * FlashSectorSizeGet()); +} + +//***************************************************************************** +// +//! \brief Set power mode. +//! +//! This function will set the specified power mode. +//! +//! Any access to the bank causes a reload of the specified bank grace period +//! input value into the bank down counter. After the last access to the +//! flash bank, the down counter delays from 0 to 255 prescaled HCLK clock +//! cycles before putting the bank into one of the fallback power modes as +//! determined by \c ui32PowerMode. This value must be greater than 1 when the +//! fallback mode is not \ref FLASH_PWR_ACTIVE_MODE. +//! +//! Note: The prescaled clock used for the down counter is a clock divided by +//! 16 from input HCLK. The \c ui32BankGracePeriod parameter is ignored if +//! \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE. +//! Any access to flash memory causes the pump grace period down counter to +//! reload with value of \c ui32PumpGracePeriod. After the bank has gone to sleep, +//! the down counter delays this number of prescaled HCLK clock cycles before +//! entering one of the charge pump fallback power modes as determined by +//! \c ui32PowerMode. The prescaled clock used for the pump grace period down +//! counter is a clock divided by 16 from input HCLK. This parameter is ignored +//! if \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE. +//! +//! Changing the power mode of the flash module must be a part within a +//! device power mode transition requiring configuration of multiple modules. +//! Refer to documents describing the device power modes. +//! +//! \param ui32PowerMode is the wanted power mode. +//! The defined flash power modes are: +//! - \ref FLASH_PWR_ACTIVE_MODE +//! - \ref FLASH_PWR_OFF_MODE +//! - \ref FLASH_PWR_DEEP_STDBY_MODE +//! \param ui32BankGracePeriod is the starting count value for the bank grace +//! period down counter. +//! \param ui32PumpGracePeriod is the starting count value for the pump grace +//! period down counter. +//! +//! \return None +// +//***************************************************************************** +extern void FlashPowerModeSet(uint32_t ui32PowerMode, + uint32_t ui32BankGracePeriod, + uint32_t ui32PumpGracePeriod); + +//***************************************************************************** +// +//! \brief Get current configured power mode. +//! +//! This function will return the current configured power mode. +//! +//! \return Returns the current configured power mode. +//! The defined power modes are: +//! - \ref FLASH_PWR_ACTIVE_MODE +//! - \ref FLASH_PWR_OFF_MODE +//! - \ref FLASH_PWR_DEEP_STDBY_MODE +// +//***************************************************************************** +extern uint32_t FlashPowerModeGet(void); + +//***************************************************************************** +// +//! \brief Set sector protection. +//! +//! This function will set the specified protection on specified flash bank +//! sector. A sector can either have no protection or have write protection +//! which guards for both program and erase of that sector. +//! Sector protection can only be changed from \ref FLASH_NO_PROTECT to +//! \ref FLASH_WRITE_PROTECT! After write protecting a sector this sector can +//! only be set back to unprotected by a device reset. +//! +//! \param ui32SectorAddress is the start address of the sector to protect. +//! \param ui32ProtectMode is the enumerated sector protection mode. +//! - \ref FLASH_NO_PROTECT +//! - \ref FLASH_WRITE_PROTECT +//! +//! \return None +// +//***************************************************************************** +extern void FlashProtectionSet(uint32_t ui32SectorAddress, + uint32_t ui32ProtectMode); + +//***************************************************************************** +// +//! \brief Get sector protection. +//! +//! This return the protection mode for the specified flash bank sector. +//! +//! \param ui32SectorAddress is the start address of the desired sector. +//! +//! \return Returns the sector protection: +//! - \ref FLASH_NO_PROTECT +//! - \ref FLASH_WRITE_PROTECT +// +//***************************************************************************** +extern uint32_t FlashProtectionGet(uint32_t ui32SectorAddress); + +//***************************************************************************** +// +//! \brief Save sector protection to make it permanent. +//! +//! This function will save the current protection mode for the specified +//! flash bank sector. +//! +//! This function must only be executed from ROM or SRAM. +//! +//! \note A write protected sector will become permanent write +//! protected!! A device reset will not change the write protection! +//! +//! \param ui32SectorAddress is the start address of the sector to be protected. +//! +//! \return Returns the status of the sector protection: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_FSM_ERROR : An erase error is encountered. +// +//***************************************************************************** +extern uint32_t FlashProtectionSave(uint32_t ui32SectorAddress); + +//***************************************************************************** +// +//! \brief Checks if the Flash state machine has detected an error. +//! +//! This function returns the status of the Flash State Machine indicating if +//! an error is detected or not. Primary use is to check if an Erase or +//! Program operation has failed. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. This function must be called from ROM or +//! SRAM while any part of the flash is being programmed or erased. +//! +//! \return Returns status of Flash state machine: +//! - \ref FAPI_STATUS_FSM_ERROR +//! - \ref FAPI_STATUS_SUCCESS +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashCheckFsmForError(void) +{ + if(HWREG(FLASH_BASE + FLASH_O_FMSTAT) & FLASH_FMSTAT_CSTAT) + { + return(FAPI_STATUS_FSM_ERROR); + } + else + { + return(FAPI_STATUS_SUCCESS); + } +} + +//***************************************************************************** +// +//! \brief Checks if the Flash state machine is ready. +//! +//! This function returns the status of the Flash State Machine indicating if +//! it is ready to accept a new command or not. Primary use is to check if an +//! Erase or Program operation has finished. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. This function must be called from ROM or +//! SRAMh while any part of the flash is being programmed or erased. +//! +//! \return Returns readiness status of Flash state machine: +//! - \ref FAPI_STATUS_FSM_READY +//! - \ref FAPI_STATUS_FSM_BUSY +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashCheckFsmForReady(void) +{ + if(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_BUSY) + { + return(FAPI_STATUS_FSM_BUSY); + } + else + { + return(FAPI_STATUS_FSM_READY); + } +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the flash interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific FLASH interrupts must be enabled via \ref FlashIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the flash +//! interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_FLASH, pfnHandler); + + // Enable the flash interrupt. + IntEnable(INT_FLASH); +} + +//***************************************************************************** +// +//! \brief Unregisters the interrupt handler for the flash interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a FLASH interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntUnregister(void) +{ + // Disable the interrupts. + IntDisable(INT_FLASH); + + // Unregister the interrupt handler. + IntUnregister(INT_FLASH); +} + +//***************************************************************************** +// +//! \brief Enables flash controller interrupt sources. +//! +//! This function enables the flash controller interrupt sources. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt. +//! - \ref FLASH_INT_RV : Read verify error interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntEnable(uint32_t ui32IntFlags) +{ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= ui32IntFlags; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \brief Disables individual flash controller interrupt sources. +//! +//! This function disables the flash controller interrupt sources. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt. +//! - \ref FLASH_INT_RV : Read verify error interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntDisable(uint32_t ui32IntFlags) +{ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~ui32IntFlags; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the Flash. +//! +//! \return Returns the current interrupt status as values described in +//! \ref FlashIntEnable(). +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashIntStatus(void) +{ + uint32_t ui32IntFlags; + + ui32IntFlags = 0; + + // Check if FSM_DONE interrupt status is set. + if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_FSM_DONE) + { + ui32IntFlags = FLASH_INT_FSM_DONE; + } + + // Check if RVF_INT interrupt status is set. + if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_RVF_INT) + { + ui32IntFlags |= FLASH_INT_RV; + } + + return(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Clears flash controller interrupt source. +//! +//! The flash controller interrupt source is cleared, so that it no longer +//! asserts. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared. +//! Can be any of: +//! - \ref FLASH_INT_FSM_DONE +//! - \ref FLASH_INT_RV +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntClear(uint32_t ui32IntFlags) +{ + uint32_t ui32TempVal; + + ui32TempVal = 0; + + if(ui32IntFlags & FLASH_INT_FSM_DONE) + { + ui32TempVal = FLASH_FEDACSTAT_FSM_DONE; + } + + if(ui32IntFlags & FLASH_INT_RV) + { + ui32TempVal |= FLASH_FEDACSTAT_RVF_INT; + } + + // Clear the flash interrupt source. + HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) = ui32TempVal; +} + +//***************************************************************************** +// +//! \brief Erase a flash sector. +//! +//! This function will erase the specified flash sector. The function will +//! not return until the flash sector has been erased or an error condition +//! occurred. If flash top sector is erased the function will program the +//! the device security data bytes with default values. The device security +//! data located in the customer configuration area of the flash top sector, +//! must have valid values at all times. These values affect the configuration +//! of the device during boot. +//! +//! \warning Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. The application must disable interrupts that have +//! interrupt routines in flash. This function calls a ROM function which handles the +//! actual program operation. +//! +//! \param ui32SectorAddress is the starting address in flash of the sector to be +//! erased. +//! +//! \return Returns the status of the sector erase: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Invalid argument. +//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered. +// +//***************************************************************************** +extern uint32_t FlashSectorErase(uint32_t ui32SectorAddress); + + +//***************************************************************************** +// +//! \brief Programs unprotected flash sectors in the main bank. +//! +//! This function programs a sequence of bytes into the on-chip flash. +//! Programming each location consists of the result of an AND operation +//! of the new data and the existing data; in other words bits that contain +//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed +//! to 1. Therefore, a byte can be programmed multiple times as long as these +//! rules are followed; if a program operation attempts to change a 0 bit to +//! a 1 bit, that bit will not have its value changed. +//! +//! This function does not return until the data has been programmed or a +//! programming error occurs. +//! +//! \note It is recommended to disable cache and line buffer before programming the +//! flash. Cache and line buffer are not automatically updated if a flash program +//! causes a mismatch between new flash content and old content in cache and +//! line buffer. Remember to enable cache and line buffer when the program +//! operation completes. See \ref VIMSModeSafeSet(), \ref VIMSLineBufDisable(), +//! and \ref VIMSLineBufEnable() for more information. +//! +//! \warning Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. The application must disable interrupts that have +//! interrupt routines in flash. This function calls a ROM function which handles the +//! actual program operation. +//! +//! The \c pui8DataBuffer pointer can not point to flash. +//! +//! \param pui8DataBuffer is a pointer to the data to be programmed. +//! \param ui32Address is the starting address in flash to be programmed. +//! \param ui32Count is the number of bytes to be programmed. +//! +//! \return Returns status of the flash programming: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Too many bytes were requested. +//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered. +// +//***************************************************************************** +extern uint32_t FlashProgram(uint8_t *pui8DataBuffer, + uint32_t ui32Address, uint32_t ui32Count); + +//***************************************************************************** +// +//! \brief Reads efuse data from specified row. +//! +//! This function will read one efuse row. +//! It is assumed that any previous efuse operation has finished. +//! +//! \param pui32EfuseData is pointer to variable to be updated with efuse data. +//! \param ui32RowAddress is the efuse row number to be read. First row is row +//! number 0. +//! +//! \return Returns the status of the efuse read operation. +//! - \c false : OK status. +//! - \c true : Error status +// +//***************************************************************************** +extern bool FlashEfuseReadRow(uint32_t *pui32EfuseData, + uint32_t ui32RowAddress); + +//***************************************************************************** +// +//! \brief Disables all sectors for erase and programming on the active bank. +//! +//! This function disables all sectors for erase and programming on the active +//! bank and enables the Idle Reading Power reduction mode if no low power +//! mode is configured. Furthermore, an additional level of protection from +//! erase is enabled. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. +//! +//! \return None +// +//***************************************************************************** +extern void FlashDisableSectorsForWrite(void); + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_FlashPowerModeSet + #undef FlashPowerModeSet + #define FlashPowerModeSet ROM_FlashPowerModeSet + #endif + #ifdef ROM_FlashPowerModeGet + #undef FlashPowerModeGet + #define FlashPowerModeGet ROM_FlashPowerModeGet + #endif + #ifdef ROM_FlashProtectionSet + #undef FlashProtectionSet + #define FlashProtectionSet ROM_FlashProtectionSet + #endif + #ifdef ROM_FlashProtectionGet + #undef FlashProtectionGet + #define FlashProtectionGet ROM_FlashProtectionGet + #endif + #ifdef ROM_FlashProtectionSave + #undef FlashProtectionSave + #define FlashProtectionSave ROM_FlashProtectionSave + #endif + #ifdef ROM_FlashSectorErase + #undef FlashSectorErase + #define FlashSectorErase ROM_FlashSectorErase + #endif + #ifdef ROM_FlashProgram + #undef FlashProgram + #define FlashProgram ROM_FlashProgram + #endif + #ifdef ROM_FlashEfuseReadRow + #undef FlashEfuseReadRow + #define FlashEfuseReadRow ROM_FlashEfuseReadRow + #endif + #ifdef ROM_FlashDisableSectorsForWrite + #undef FlashDisableSectorsForWrite + #define FlashDisableSectorsForWrite ROM_FlashDisableSectorsForWrite + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio.c new file mode 100644 index 0000000..fcc316a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: gpio.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the GPIO +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "gpio.h" + +// see gpio.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio.h new file mode 100644 index 0000000..9a4bf16 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio.h @@ -0,0 +1,643 @@ +/****************************************************************************** +* Filename: gpio.h +* Revised: 2018-05-02 11:11:40 +0200 (Wed, 02 May 2018) +* Revision: 51951 +* +* Description: Defines and prototypes for the GPIO. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup gpio_api +//! @{ +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_gpio.h" +#include "debug.h" + +//***************************************************************************** +// +// Check for legal range of variable dioNumber +// +//***************************************************************************** +#ifdef DRIVERLIB_DEBUG +#include "../inc/hw_fcfg1.h" +#include "chipinfo.h" + +static bool +dioNumberLegal( uint32_t dioNumber ) +{ + uint32_t ioCount = + (( HWREG( FCFG1_BASE + FCFG1_O_IOCONF ) & + FCFG1_IOCONF_GPIO_CNT_M ) >> + FCFG1_IOCONF_GPIO_CNT_S ) ; + + // CC13x2 + CC26x2 + if ( ChipInfo_ChipFamilyIs_CC13x2_CC26x2() ) + { + return ( (dioNumber >= (31 - ioCount)) && (dioNumber < 31) ) + } + // Special handling of CC13x0 7x7, where IO_CNT = 30 and legal range is 1..30 + // for all other chips legal range is 0..(dioNumber-1) + else if (( ioCount == 30 ) && ChipInfo_ChipFamilyIs_CC13x0() ) + { + return (( dioNumber > 0 ) && ( dioNumber <= ioCount )); + } + else + { + return ( dioNumber < ioCount ); + } + +} +#endif + +//***************************************************************************** +// +// The following values define the bit field for the GPIO DIOs. +// +//***************************************************************************** +#define GPIO_DIO_0_MASK 0x00000001 // GPIO DIO 0 mask +#define GPIO_DIO_1_MASK 0x00000002 // GPIO DIO 1 mask +#define GPIO_DIO_2_MASK 0x00000004 // GPIO DIO 2 mask +#define GPIO_DIO_3_MASK 0x00000008 // GPIO DIO 3 mask +#define GPIO_DIO_4_MASK 0x00000010 // GPIO DIO 4 mask +#define GPIO_DIO_5_MASK 0x00000020 // GPIO DIO 5 mask +#define GPIO_DIO_6_MASK 0x00000040 // GPIO DIO 6 mask +#define GPIO_DIO_7_MASK 0x00000080 // GPIO DIO 7 mask +#define GPIO_DIO_8_MASK 0x00000100 // GPIO DIO 8 mask +#define GPIO_DIO_9_MASK 0x00000200 // GPIO DIO 9 mask +#define GPIO_DIO_10_MASK 0x00000400 // GPIO DIO 10 mask +#define GPIO_DIO_11_MASK 0x00000800 // GPIO DIO 11 mask +#define GPIO_DIO_12_MASK 0x00001000 // GPIO DIO 12 mask +#define GPIO_DIO_13_MASK 0x00002000 // GPIO DIO 13 mask +#define GPIO_DIO_14_MASK 0x00004000 // GPIO DIO 14 mask +#define GPIO_DIO_15_MASK 0x00008000 // GPIO DIO 15 mask +#define GPIO_DIO_16_MASK 0x00010000 // GPIO DIO 16 mask +#define GPIO_DIO_17_MASK 0x00020000 // GPIO DIO 17 mask +#define GPIO_DIO_18_MASK 0x00040000 // GPIO DIO 18 mask +#define GPIO_DIO_19_MASK 0x00080000 // GPIO DIO 19 mask +#define GPIO_DIO_20_MASK 0x00100000 // GPIO DIO 20 mask +#define GPIO_DIO_21_MASK 0x00200000 // GPIO DIO 21 mask +#define GPIO_DIO_22_MASK 0x00400000 // GPIO DIO 22 mask +#define GPIO_DIO_23_MASK 0x00800000 // GPIO DIO 23 mask +#define GPIO_DIO_24_MASK 0x01000000 // GPIO DIO 24 mask +#define GPIO_DIO_25_MASK 0x02000000 // GPIO DIO 25 mask +#define GPIO_DIO_26_MASK 0x04000000 // GPIO DIO 26 mask +#define GPIO_DIO_27_MASK 0x08000000 // GPIO DIO 27 mask +#define GPIO_DIO_28_MASK 0x10000000 // GPIO DIO 28 mask +#define GPIO_DIO_29_MASK 0x20000000 // GPIO DIO 29 mask +#define GPIO_DIO_30_MASK 0x40000000 // GPIO DIO 30 mask +#define GPIO_DIO_31_MASK 0x80000000 // GPIO DIO 31 mask +#define GPIO_DIO_ALL_MASK 0xFFFFFFFF // GPIO all DIOs mask + +//***************************************************************************** +// +// Define constants that shall be passed as the outputEnableValue parameter to +// GPIO_setOutputEnableDio() and will be returned from the function +// GPIO_getOutputEnableDio(). +// +//***************************************************************************** +#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled +#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Reads a specific DIO. +//! +//! \param dioNumber specifies the DIO to read (0-31). +//! +//! \return Returns 0 or 1 reflecting the input value of the specified DIO. +//! +//! \sa \ref GPIO_readMultiDio(), \ref GPIO_writeDio(), \ref GPIO_writeMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_readDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Return the input value from the specified DIO. + return (( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) >> dioNumber ) & 1 ); +} + +//***************************************************************************** +// +//! \brief Reads the input value for the specified DIOs. +//! +//! This function returns the input value for multiple DIOs. +//! The value returned is not shifted and hence matches the corresponding dioMask bits. +//! +//! \param dioMask is the bit-mask representation of the DIOs to read. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return Returns a bit vector reflecting the input value of the corresponding DIOs. +//! - 0 : Corresponding DIO is low. +//! - 1 : Corresponding DIO is high. +//! +//! \sa \ref GPIO_readDio(), \ref GPIO_writeDio(), \ref GPIO_writeMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_readMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Return the input value from the specified DIOs. + return ( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) & dioMask ); +} + +//***************************************************************************** +// +//! \brief Writes a value to a specific DIO. +//! +//! \param dioNumber specifies the DIO to update (0-31). +//! \param value specifies the value to write +//! - 0 : Logic zero (low) +//! - 1 : Logic one (high) +//! +//! \return None +//! +//! \sa \ref GPIO_writeMultiDio(), \ref GPIO_readDio(), \ref GPIO_readMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_writeDio( uint32_t dioNumber, uint32_t value ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + ASSERT(( value == 0 ) || ( value == 1 )); + + // Write 0 or 1 to the byte indexed DOUT map + HWREGB( GPIO_BASE + dioNumber ) = value; +} + +//***************************************************************************** +// +//! \brief Writes masked data to the specified DIOs. +//! +//! Enables for writing multiple bits simultaneously. +//! The value to write must be shifted so it matches the corresponding dioMask bits. +//! +//! \note Note that this is a read-modify-write operation and hence not atomic. +//! +//! \param dioMask is the bit-mask representation of the DIOs to write. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! \param bitVectoredValue holds the value to be written to the corresponding DIO-bits. +//! +//! \return None +//! +//! \sa \ref GPIO_writeDio(), \ref GPIO_readDio(), \ref GPIO_readMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_writeMultiDio( uint32_t dioMask, uint32_t bitVectoredValue ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) = + ( HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) & ~dioMask ) | + ( bitVectoredValue & dioMask ); +} + +//***************************************************************************** +// +//! \brief Sets a specific DIO to 1 (high). +//! +//! \param dioNumber specifies the DIO to set (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_setMultiDio(), \ref GPIO_clearDio(), \ref GPIO_clearMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Set the specified DIO. + HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +//! \brief Sets the specified DIOs to 1 (high). +//! +//! \param dioMask is the bit-mask representation of the DIOs to set. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return None +//! +//! \sa \ref GPIO_setDio(), \ref GPIO_clearDio(), \ref GPIO_clearMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Set the DIOs. + HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = dioMask; +} + +//***************************************************************************** +// +//! \brief Clears a specific DIO to 0 (low). +//! +//! \param dioNumber specifies the DIO to clear (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_clearMultiDio(), \ref GPIO_setDio(), \ref GPIO_setMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Clear the specified DIO. + HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +//! \brief Clears the specified DIOs to 0 (low). +//! +//! \param dioMask is the bit-mask representation of the DIOs to clear. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return None +//! +//! \sa \ref GPIO_clearDio(), \ref GPIO_setDio(), \ref GPIO_setMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Clear the DIOs. + HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = dioMask; +} + +//***************************************************************************** +// +//! \brief Toggles a specific DIO. +//! +//! \param dioNumber specifies the DIO to toggle (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_toggleMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_toggleDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Toggle the specified DIO. + HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +//! \brief Toggles the specified DIOs. +//! +//! \param dioMask is the bit-mask representation of the DIOs to toggle. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return None +//! +//! \sa \ref GPIO_toggleDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_toggleMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Toggle the DIOs. + HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = dioMask; +} + +//***************************************************************************** +// +//! \brief Gets the output enable status of a specific DIO. +//! +//! This function returns the output enable status for the specified DIO. +//! The DIO can be configured as either input or output under software control. +//! +//! \param dioNumber specifies the DIO to get the output enable setting from (0-31). +//! +//! \return Returns one of the enumerated data types (0 or 1): +//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled. +//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled. +//! +//! \sa \ref GPIO_getOutputEnableMultiDio(), \ref GPIO_setOutputEnableDio(), \ref GPIO_setOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getOutputEnableDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Return the output enable status for the specified DIO. + return (( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) >> dioNumber ) & 1 ); +} + +//***************************************************************************** +// +//! \brief Gets the output enable setting of the specified DIOs. +//! +//! This function returns the output enable setting for multiple DIOs. +//! The value returned is not shifted and hence matches the corresponding dioMask bits. +//! +//! \param dioMask is the bit-mask representation of the DIOs to return the output enable settings from. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return Returns the output enable setting for multiple DIOs as a bit vector corresponding to the dioMask bits. +//! - 0 : Corresponding DIO is configured with output disabled. +//! - 1 : Corresponding DIO is configured with output enabled. +//! +//! \sa \ref GPIO_getOutputEnableDio(), \ref GPIO_setOutputEnableDio(), \ref GPIO_setOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getOutputEnableMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Return the output enable value for the specified DIOs. + return ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & dioMask ); +} + +//***************************************************************************** +// +//! \brief Sets output enable of a specific DIO. +//! +//! This function sets the GPIO output enable bit for the specified DIO. +//! The DIO can be configured as either input or output under software control. +//! +//! \param dioNumber specifies the DIO to configure (0-31). +//! \param outputEnableValue specifies the output enable setting of the specified DIO: +//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled. +//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled. +//! +//! \return None +//! +//! \sa \ref GPIO_setOutputEnableMultiDio(), \ref GPIO_getOutputEnableDio(), \ref GPIO_getOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setOutputEnableDio( uint32_t dioNumber, uint32_t outputEnableValue ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + ASSERT(( outputEnableValue == GPIO_OUTPUT_DISABLE ) || + ( outputEnableValue == GPIO_OUTPUT_ENABLE ) ); + + // Update the output enable bit for the specified DIO. + HWREGBITW( GPIO_BASE + GPIO_O_DOE31_0, dioNumber ) = outputEnableValue; +} + +//***************************************************************************** +// +//! \brief Configures the output enable setting for all specified DIOs. +//! +//! This function configures the output enable setting for the specified DIOs. +//! The output enable setting must be shifted so it matches the corresponding dioMask bits. +//! The DIOs can be configured as either an input or output under software control. +//! +//! \note Note that this is a read-modify-write operation and hence not atomic. +//! +//! \param dioMask is the bit-mask representation of the DIOs on which to configure the +//! output enable setting. The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! \param bitVectoredOutputEnable holds the output enable setting the corresponding DIO-bits: +//! - 0 : Corresponding DIO is configured with output disabled. +//! - 1 : Corresponding DIO is configured with output enabled. +//! +//! \return None +//! +//! \sa \ref GPIO_setOutputEnableDio(), \ref GPIO_getOutputEnableDio(), \ref GPIO_getOutputEnableMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setOutputEnableMultiDio( uint32_t dioMask, uint32_t bitVectoredOutputEnable ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) = + ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & ~dioMask ) | + ( bitVectoredOutputEnable & dioMask ); +} + +//***************************************************************************** +// +//! \brief Gets the event status of a specific DIO. +//! +//! \param dioNumber specifies the DIO to get the event status from (0-31). +//! +//! \return Returns the current event status on the specified DIO. +//! - 0 : Non-triggered event. +//! - 1 : Triggered event. +//! +//! \sa \ref GPIO_getEventMultiDio(), \ref GPIO_clearEventDio(), \ref GPIO_clearEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getEventDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Return the event status for the specified DIO. + return (( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) >> dioNumber ) & 1 ); +} + +//***************************************************************************** +// +//! \brief Gets the event status of the specified DIOs. +//! +//! This function returns the event status for multiple DIOs. +//! The value returned is not shifted and hence matches the corresponding dioMask bits. +//! +//! \param dioMask is the bit-mask representation of the DIOs to get the +//! event status from (0-31). +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return Returns a bit vector with the current event status corresponding to the specified DIOs. +//! - 0 : Corresponding DIO has no triggered event. +//! - 1 : Corresponding DIO has a triggered event. +//! +//! \sa \ref GPIO_getEventDio(), \ref GPIO_clearEventDio(), \ref GPIO_clearEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getEventMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Return the event status for the specified DIO. + return ( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) & dioMask ); +} + +//***************************************************************************** +// +//! \brief Clears the IO event status of a specific DIO. +//! +//! \param dioNumber specifies the DIO on which to clear the event status (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_clearEventMultiDio(), \ref GPIO_getEventDio(), \ref GPIO_getEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearEventDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Clear the event status for the specified DIO. + HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +//! \brief Clears the IO event status on the specified DIOs. +//! +//! \param dioMask is the bit-mask representation of the DIOs on which to +//! clear the events status. +//! The parameter must be a bitwise OR'ed combination of the following: +//! - \ref GPIO_DIO_0_MASK +//! - ... +//! - \ref GPIO_DIO_31_MASK +//! +//! \return None +//! +//! \sa \ref GPIO_clearEventDio(), \ref GPIO_getEventDio(), \ref GPIO_getEventMultiDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearEventMultiDio( uint32_t dioMask ) +{ + // Check the arguments. + ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + + // Clear the event status for the specified DIOs. + HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = dioMask; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio_doc.h new file mode 100644 index 0000000..b4548af --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio_doc.h @@ -0,0 +1,90 @@ +/****************************************************************************** +* Filename: gpio_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup gpio_api +//! @{ +//! \section sec_gpio Introduction +//! +//! The GPIO module allows software to control the pins of the device directly if the IOC module has +//! been configured to route the GPIO signal to a physical pin (called DIO). Alternatively, pins can +//! be hardware controlled by other peripheral modules. For more information about the IOC module, +//! how to configure physical pins, and how to select between software controlled and hardware controlled, +//! see the [IOC API](\ref ioc_api). +//! +//! The System CPU can access the GPIO module to read the value of any DIO of the device and if the IOC +//! module has been configured such that one or more DIOs are GPIO controlled (software controlled) the +//! System CPU can write these DIOs through the GPIO module. +//! +//! The IOC module can also be configured to generate events on edge detection and these events can be +//! read and cleared in the GPIO module by the System CPU. +//! +//! \section sec_gpio_api API +//! +//! The API functions can be grouped like this: +//! +//! Set and get direction of DIO (output enable): +//! - \ref GPIO_setOutputEnableDio() +//! - \ref GPIO_setOutputEnableMultiDio() +//! - \ref GPIO_getOutputEnableDio() +//! - \ref GPIO_getOutputEnableMultiDio() +//! +//! Write DIO (requires IOC to be configured for GPIO usage): +//! - \ref GPIO_writeDio() +//! - \ref GPIO_writeMultiDio() +//! +//! Set, clear, or toggle DIO (requires IOC to be configured for GPIO usage): +//! - \ref GPIO_setDio() +//! - \ref GPIO_setMultiDio() +//! - \ref GPIO_clearDio() +//! - \ref GPIO_clearMultiDio() +//! - \ref GPIO_toggleDio() +//! - \ref GPIO_toggleMultiDio() +//! +//! Read DIO (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC): +//! - \ref GPIO_readDio() +//! - \ref GPIO_readMultiDio() +//! +//! Read or clear events (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC): +//! - \ref GPIO_getEventDio() +//! - \ref GPIO_getEventMultiDio() +//! - \ref GPIO_clearEventDio() +//! - \ref GPIO_clearEventMultiDio() +//! +//! The [IOC API](\ref ioc_api) provides two functions for easy configuration of DIOs as GPIO enabled using +//! typical settings. They also serve as examples on how to configure the IOC and GPIO modules for GPIO usage: +//! - \ref IOCPinTypeGpioInput() +//! - \ref IOCPinTypeGpioOutput() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_analog_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_analog_doc.h new file mode 100644 index 0000000..d6346b3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_analog_doc.h @@ -0,0 +1,107 @@ +/****************************************************************************** +* Filename: group_analog_doc.h +* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) +* Revision: 47080 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup analog_group +//! @{ +//! \section sec_analog Introduction +//! +//! Access to registers in the analog domain of the device goes through master modules controlling slave +//! modules which contain the actual registers. The master module is located in the digital domain of the +//! device. The interfaces between master and slave modules are called ADI (Analog-to-Digital Interface) +//! and DDI (Digital-to-Digital Interface) depending on the type of module to access and thus the slave +//! modules are referred to as ADI slave and DDI slave. +//! +//! The ADI and DDI APIs provide access to these registers: +//! - ADI_2_REFSYS : Reference System for generating reference voltages and reference currents. +//! - Reference system control +//! - SOC LDO control +//! - ADI_3_REFSYS : Reference System for generating reference voltages and reference currents. +//! - Reference system control +//! - DC/DC control +//! - ADI_4_AUX : Controlling analog peripherals of AUX. +//! - Multiplexers +//! - Current source +//! - Comparators +//! - ADCs +//! - DDI_0_OSC : Controlling the oscillators (via AUX domain) +//! +//! The register descriptions of CPU memory map document the ADI/DDI masters. The register descriptions of +//! analog memory map document the ADI/DDI slaves. The ADI/DDI APIs allow the programmer to focus on the +//! slave registers of interest without being concerned with the ADI/DDI master part of the interface. +//! +//! Although the ADI/DDI APIs make the master "transparent" it can be useful to know a few details about +//! the ADI/DDI protocol and how the master handles transactions as it can affect how the system CPU performs. +//! - ADI protocol uses 8-bit write bus compared to 32-bit write bus in DDI. ADI protocol uses 4-bit read +//! bus compared to 16-bit read bus in DDI. Hence a 32-bit read from an ADI register is translated into 8 +//! transactions in the ADI protocol. +//! - One transaction on the ADI/DDI protocol takes several clock cycles for the master to complete. +//! - Access to AUX ADI/DDI requires use of a semaphore. This is handled automatically by DriverLib which uses +//! \ref AuxAdiDdiSafeWrite() and \ref AuxAdiDdiSafeRead() whenever AUX is accessed. +//! - ADI slave registers are 8-bit wide. +//! - DDI slave registers are 32-bit wide. +//! - ADI/DDI master supports multiple data width accesses seen from the system CPU +//! (however, not all bit width accesses are supported by the APIs): +//! - Read: 8, 16, 32-bit +//! - Write +//! - Direct (write, set, clear): 8, 16, 32-bit +//! - Masked: 4, 8, 16-bit +//! +//! Making posted/buffered writes from the system CPU (default) to the ADI/DDI allows the system CPU to continue +//! while the ADI/DDI master handles the transactions on the ADI/DDI protocol. If using non-posted/non-buffered +//! writes the system CPU will wait for ADI/DDI master to complete the transactions to the slave before continuing +//! execution. +//! +//! Reading from ADI/DDI requires that all transactions on the ADI/DDI protocol have completed before the system CPU +//! receives the response thus the programmer must understand that the response time depends on the number of bytes +//! read. However, due to the 'set', 'clear' and 'masked write' features of the ADI/DDI most writes can be done +//! without the typical read-modify-write sequence thus reducing the need for reads to a minimum. +//! +//! Consequently, if making posted/buffered writes then the written value will not take effect in the +//! analog domain until some point later in time. An alternative to non-posted/non-buffered writes - in order to make +//! sure a written value has taken effect - is to read from the same ADI/DDI as the write as this will keep the system CPU +//! waiting until both the write and the read have completed. +//! +//! \note +//! Do NOT use masked write when writing bit fields spanning the "masked write boundary" i.e. the widest possible +//! masked write that the protocol supports (ADI = 4 bits, DDI = 16 bits). This will put the device into a +//! temporary state - which is potentially harmful to the device - as the bit field will be written over two transactions. +//! Thus to use masked writes: +//! - For ADI the bit field(s) must be within bit 0 to 3 (REG[3:0]) or bit 4 to 7 (REG[7:4]). +//! - For DDI the bit field(s) must be within bit 0 to 15 (REG[15:0]) or bit 16 to 31 (REG[31:16]). +//! +//! \note +//! If masked write is not allowed, a regular read-modify-write is necessary. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aon_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aon_doc.h new file mode 100644 index 0000000..c5056d9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aon_doc.h @@ -0,0 +1,76 @@ +/****************************************************************************** +* Filename: group_aon_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aon_group +//! @{ +//! \section sec_aon Introduction +//! +//! The Always-ON (AON) voltage domain contains the AUX power domain, AON power domain, and JTAG power domain. +//! The AON API includes functions to access the AON power domain. For functions accessing the AUX power domain +//! see the [AUX API](@ref aux_group). +//! +//! The AON power domain contains circuitry that is always enabled, except for the shutdown mode +//! (digital supply is off), and the AON power domain is clocked at 32-kHz. +//! +//! The AON API accesses the AON registers through a common module called AON Interface (AON IF) which handles the +//! actual transactions towards the much slower AON registers. Because accessing AON can cause a significant +//! delay in terms of system CPU clock cycles it is important to understand the basics about how the AON IF +//! operates. The following list describes a few of the most relevant properties of the AON IF seen from the system CPU: +//! - \ti_bold{Shadow registers}: The system CPU actually accesses a set of "shadow registers" which are being synchronized to the AON registers +//! by the AON IF every AON clock cycle. +//! - Writing an AON register via AON IF can take up to one AON clock cycle before taking effect in the AON domain. However, the system CPU can +//! continue executing without waiting for this. +//! - The AON IF supports multiple writes within the same AON clock cycle thus several registers/bit fields can be synchronized simultaneously. +//! - Reading from AON IF returns the value from last time the shadow registers were synchronized (if no writes to AON IF have occurred since) +//! thus the value can be up to one AON clock cycle old. +//! - Reading from AON IF after a write (but before synchronization has happened) will return the value from the shadow register +//! and not the last value from the AON register. Thus doing multiple read-modify-writes within one AON clock cycle is supported. +//! - \ti_bold{Read delay}: Due to an asynchronous interface to the AON IF, reading AON registers will generate a few wait cycles thus stalling +//! the system CPU until the read completes. There is no delay on writes to AON IF if using posted/buffered writes. +//! - \ti_bold{Synchronizing}: If it is required that a write to AON takes effect before continuing code execution it is possible to do a conditional "wait for +//! synchronization" by calling \ref SysCtrlAonSync(). This will wait for any pending writes to synchronize. +//! - \ti_bold{Updating}: It is also possible to do an unconditional "wait for synchronization", in case a new read +//! value is required, by calling \ref SysCtrlAonUpdate(). This is typically used after wake-up to make sure the AON IF has been +//! synchronized at least once before reading the values. +//! +//! Below are a few guidelines to write efficient code for AON access based on the properties of the interface to the AON registers. +//! - Avoid synchronizing unless required by the application. If synchronization is needed then try to group/arrange AON writes to +//! minimize the number of required synchronizations. +//! - If modifying several bit fields within a single AON register it is slightly faster to do a single read, modify the bit fields, +//! and then write it back rather than doing multiple independent read-modify-writes (due to the read delay). +//! - Using posted/buffered writes to AON (default) lets the system CPU continue execution immediately. Using non-posted/non-buffered +//! writes will generate a delay similar to a read access. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aux_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aux_doc.h new file mode 100644 index 0000000..63ddcfd --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aux_doc.h @@ -0,0 +1,58 @@ +/****************************************************************************** +* Filename: group_aux_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aux_group +//! @{ +//! \section sec_aux Introduction +//! +//! The AUX is a collective description of all the analog peripherals (ADC, comparators, and current source) and +//! the digital modules in the AUX power domain (AUX_PD) such as the sensor controller, timers, time-to-digital +//! converter, etc. AUX_PD is located within the AON voltage domain of the device. +//! +//! The sensor controller has the ability to +//! do its own power and clock management of AUX_PD, independently of the MCU domain. The sensor +//! controller can also continue doing tasks while the MCU subsystem is powered down, but with limited +//! resources compared to the larger MCU domain. +//! +//! The AUX power domain is connected to the MCU system through an asynchronous interface, ensuring +//! that all modules connected to the AUX bus are accessible from the system CPU. +//! Accessing the analog peripherals from the system CPU must be done by using TI-provided +//! drivers to ensure proper control of power management. +//! +//! \note To ease development of program code running on the sensor controller, TI provides a tool +//! chain for writing software for the controller, Sensor Controller Studio (SCS), which is a fully +//! integrated tool consisting of an IDE, compiler, assembler, and linker. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c.c new file mode 100644 index 0000000..0b52735 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c.c @@ -0,0 +1,172 @@ +/****************************************************************************** +* Filename: i2c.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the I2C module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "i2c.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef I2CMasterInitExpClk + #define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk + #undef I2CMasterErr + #define I2CMasterErr NOROM_I2CMasterErr + #undef I2CIntRegister + #define I2CIntRegister NOROM_I2CIntRegister + #undef I2CIntUnregister + #define I2CIntUnregister NOROM_I2CIntUnregister +#endif + +//***************************************************************************** +// +// Initializes the I2C Master block +// +//***************************************************************************** +void +I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast) +{ + uint32_t ui32SCLFreq; + uint32_t ui32TPR; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Must enable the device before doing anything else. + I2CMasterEnable(I2C0_BASE); + + // Get the desired SCL speed. + if(bFast == true) + { + ui32SCLFreq = 400000; + } + else + { + ui32SCLFreq = 100000; + } + + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biased to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / (2 * 10 * ui32SCLFreq)) - 1; + HWREG(I2C0_BASE + I2C_O_MTPR) = ui32TPR; +} + +//***************************************************************************** +// +// Gets the error status of the I2C Master module +// +//***************************************************************************** +uint32_t +I2CMasterErr(uint32_t ui32Base) +{ + uint32_t ui32Err; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the raw error state. + ui32Err = HWREG(I2C0_BASE + I2C_O_MSTAT); + + // If the I2C master is busy, then all the other status bits are invalid, + // and there is no error to report. + if(ui32Err & I2C_MSTAT_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // Check for errors. + if(ui32Err & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST)) + { + return(ui32Err & (I2C_MSTAT_ARBLST | I2C_MSTAT_DATACK_N | I2C_MSTAT_ADRACK_N)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} + +//***************************************************************************** +// +// Registers an interrupt handler for the I2C module +// +//***************************************************************************** +void +I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the interrupt number. + ui32Int = INT_I2C_IRQ; + + // Register the interrupt handler, returning an error if an error occurs. + IntRegister(ui32Int, pfnHandler); + + // Enable the I2C interrupt. + IntEnable(ui32Int); +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for the I2C module +// +//***************************************************************************** +void +I2CIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the interrupt number. + ui32Int = INT_I2C_IRQ; + + // Disable the interrupt. + IntDisable(ui32Int); + + // Unregister the interrupt handler. + IntUnregister(ui32Int); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c.h new file mode 100644 index 0000000..d1e2969 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c.h @@ -0,0 +1,974 @@ +/****************************************************************************** +* Filename: i2c.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and prototypes for the I2C. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup i2c_api +//! @{ +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_i2c.h" +#include "../inc/hw_sysctl.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk + #define I2CMasterErr NOROM_I2CMasterErr + #define I2CIntRegister NOROM_I2CIntRegister + #define I2CIntUnregister NOROM_I2CIntUnregister +#endif + +//***************************************************************************** +// +// I2C Master commands +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START \ + 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 + +//***************************************************************************** +// +// I2C Master error status +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte + +//***************************************************************************** +// +// I2C Slave interrupts +// +//***************************************************************************** +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an I2C base address. +//! +//! This function determines if a I2C port base address is valid. +//! +//! \param ui32Base is the base address of the I2C port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise +// +//***************************************************************************** +static bool +I2CBaseValid(uint32_t ui32Base) +{ + return(ui32Base == I2C0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Initializes the I2C Master block. +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master, and will have enabled the I2C Master block. +//! +//! If the parameter \c bFast is \c true, then the master block will be set up +//! to transfer data at 400 kbps; otherwise, it will be set up to transfer data +//! at 100 kbps. +//! +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32I2CClk is the rate of the clock supplied to the I2C module. +//! \param bFast set up for fast data transfers. +//! +//! \return None +// +//***************************************************************************** +extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast); + +//***************************************************************************** +// +//! \brief Controls the state of the I2C Master module. +//! +//! This function is used to control the state of the Master module send and +//! receive operations. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32Cmd is the command to be issued by the I2C Master module +//! The parameter can be one of the following values: +//! - \ref I2C_MASTER_CMD_SINGLE_SEND +//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE +//! - \ref I2C_MASTER_CMD_BURST_SEND_START +//! - \ref I2C_MASTER_CMD_BURST_SEND_CONT +//! - \ref I2C_MASTER_CMD_BURST_SEND_FINISH +//! - \ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) || + // (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || -> Equal to SINGLE_SEND + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP)); + + // Send the command. + HWREG(I2C0_BASE + I2C_O_MCTRL) = ui32Cmd; + + // Delay minimum four cycles in order to ensure that the I2C_O_MSTAT + // register has been correctly updated before function exit + CPUdelay(2); +} + +//***************************************************************************** +// +//! \brief Sets the address that the I2C Master will place on the bus. +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. When the \e bReceive parameter is set +//! to \b true, the address will indicate that the I2C Master is initiating a +//! read from the slave; otherwise the address will indicate that the I2C +//! Master is initiating a write to the slave. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8SlaveAddr is a 7-bit slave address +//! \param bReceive flag indicates the type of communication with the slave. +//! - \c true : I2C Master is initiating a read from the slave. +//! - \c false : I2C Master is initiating a write to the slave. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, + bool bReceive) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // Set the address of the slave with which the master will communicate. + HWREG(I2C0_BASE + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; +} + +//***************************************************************************** +// +//! \brief Enables the I2C Master block. +//! +//! This will enable operation of the I2C Master block. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Enable the clock for the master. + HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 1; + + // Enable the master block. + HWREG(I2C0_BASE + I2C_O_MCTRL) = I2C_MCTRL_RUN; +} + +//***************************************************************************** +// +//! \brief Disables the I2C master block. +//! +//! This will disable operation of the I2C master block. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Disable the master block. + HWREG(I2C0_BASE + I2C_O_MCTRL) = 0; + + // Disable the clock for the master. + HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C Master is busy. +//! +//! This function returns an indication of whether or not the I2C Master is +//! busy transmitting or receiving data. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns status of I2C Master: +//! - \c true : I2C Master is busy. +//! - \c false : I2C Master is not busy. +// +//***************************************************************************** +__STATIC_INLINE bool +I2CMasterBusy(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return the busy status. + if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C bus is busy. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function can be used in a multi-master environment to determine if +//! another master is currently using the bus. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns status of the I2C bus: +//! - \c true : I2C bus is busy. +//! - \c false : I2C bus is not busy. +// +//***************************************************************************** +__STATIC_INLINE bool +I2CMasterBusBusy(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return the bus busy status. + if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSBSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Master. +//! +//! This function reads a byte of data from the I2C Master Data Register. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns the byte received from by the I2C Master, cast as an +//! uint32_t. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CMasterDataGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Read a byte. + return(HWREG(I2C0_BASE + I2C_O_MDR)); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the I2C Master. +//! +//! This function will place the supplied data into I2C Master Data Register. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8Data is the data to be transmitted by the I2C Master +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Write the byte. + HWREG(I2C0_BASE + I2C_O_MDR) = ui8Data; +} + +//***************************************************************************** +// +//! \brief Gets the error status of the I2C Master module. +//! +//! This function is used to obtain the error status of the Master module send +//! and receive operations. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns the error status of the Master module: +//! - \ref I2C_MASTER_ERR_NONE +//! - \ref I2C_MASTER_ERR_ADDR_ACK +//! - \ref I2C_MASTER_ERR_DATA_ACK +//! - \ref I2C_MASTER_ERR_ARB_LOST +// +//***************************************************************************** +extern uint32_t I2CMasterErr(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables the I2C Master interrupt. +//! +//! Enables the I2C Master interrupt source. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterIntEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Enable the master interrupt. + HWREG(I2C0_BASE + I2C_O_MIMR) = I2C_MIMR_IM; +} + +//***************************************************************************** +// +//! \brief Disables the I2C Master interrupt. +//! +//! Disables the I2C Master interrupt source. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterIntDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Disable the master interrupt. + HWREG(I2C0_BASE + I2C_O_MIMR) = 0; +} + +//***************************************************************************** +// +//! \brief Clears I2C Master interrupt sources. +//! +//! The I2C Master interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterIntClear(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Clear the I2C master interrupt source. + HWREG(I2C0_BASE + I2C_O_MICR) = I2C_MICR_IC; +} + +//***************************************************************************** +// +//! \brief Gets the current I2C Master interrupt status. +//! +//! This returns the interrupt status for the I2C Master module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param bMasked selects either raw or masked interrupt status. +//! - \c false : Raw interrupt status is requested. +//! - \c true : Masked interrupt status is requested. +//! +//! \return Returns the current interrupt status. +//! - \c true : Active. +//! - \c false : Not active. +// +//***************************************************************************** +__STATIC_INLINE bool +I2CMasterIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return((HWREG(I2C0_BASE + I2C_O_MMIS)) ? true : false); + } + else + { + return((HWREG(I2C0_BASE + I2C_O_MRIS)) ? true : false); + } +} + +//***************************************************************************** +// +//! \brief Enables the I2C Slave block. +//! +//! This will enable operation of the I2C Slave block. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Enable the clock to the slave block. + HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 1; + + // Enable the slave. + HWREG(I2C0_BASE + I2C_O_SCTL) = I2C_SCTL_DA; +} + +//***************************************************************************** +// +//! \brief Initializes the I2C Slave block. +//! +//! This function initializes operation of the I2C Slave block. Upon +//! successful initialization of the I2C blocks, this function will have set +//! the slave address and have enabled the I2C Slave block. +//! +//! The parameter \c ui8SlaveAddr is the value that will be compared against the +//! slave address sent by an I2C master. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8SlaveAddr is the 7-bit slave address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // Must enable the device before doing anything else. + I2CSlaveEnable(I2C0_BASE); + + // Set up the slave address. + HWREG(I2C0_BASE + I2C_O_SOAR) = ui8SlaveAddr; +} + +//***************************************************************************** +// +//! \brief Sets the I2C slave address. +//! +//! This function writes the specified slave address. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8SlaveAddr is the 7-bit slave address +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8SlaveAddr) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // Set up the primary slave address. + HWREG(I2C0_BASE + I2C_O_SOAR) = ui8SlaveAddr; +} + +//***************************************************************************** +// +//! \brief Disables the I2C slave block. +//! +//! This will disable operation of the I2C slave block. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Disable the slave. + HWREG(I2C0_BASE + I2C_O_SCTL) = 0x0; + + // Disable the clock to the slave block. + HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Gets the I2C Slave module status. +//! +//! This function will return the action requested from a master, if any. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return Returns the status of the I2C Slave module: +//! - \ref I2C_SLAVE_ACT_NONE : No action has been requested of the I2C Slave module. +//! - \ref I2C_SLAVE_ACT_RREQ : An I2C master has sent data to the I2C Slave module. +//! - \ref I2C_SLAVE_ACT_TREQ : An I2C master has requested that the I2C Slave module send data. +//! - \ref I2C_SLAVE_ACT_RREQ_FBR : An I2C master has sent data to the I2C slave +//! and the first byte following the slave's own address has been received. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CSlaveStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return the slave status. + return(HWREG(I2C0_BASE + I2C_O_SSTAT)); +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Slave. +//! +//! This function reads a byte of data from the I2C Slave Data Register. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return Returns the byte received from by the I2C Slave, cast as an +//! uint32_t. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CSlaveDataGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Read a byte. + return(HWREG(I2C0_BASE + I2C_O_SDR)); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the I2C Slave. +//! +//! This function will place the supplied data into I2C Slave Data Register. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8Data data to be transmitted from the I2C Slave. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Write the byte. + HWREG(I2C0_BASE + I2C_O_SDR) = ui8Data; +} + +//***************************************************************************** +// +//! \brief Enables individual I2C Slave interrupt sources. +//! +//! Enables the indicated I2C Slave interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is the bit mask of the slave interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + uint32_t ui32Val; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START | + I2C_SLAVE_INT_DATA)); + + // Enable the slave interrupt. + ui32Val = HWREG(I2C0_BASE + I2C_O_SIMR); + ui32Val |= ui32IntFlags; + HWREG(I2C0_BASE + I2C_O_SIMR) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Disables individual I2C Slave interrupt sources. +//! +//! Disables the indicated I2C Slave interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + uint32_t ui32Val; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START | + I2C_SLAVE_INT_DATA)); + + // Disable the slave interrupt. + ui32Val = HWREG(I2C0_BASE + I2C_O_SIMR); + ui32Val &= ~ui32IntFlags; + HWREG(I2C0_BASE + I2C_O_SIMR) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Clears I2C Slave interrupt sources. +//! +//! The specified I2C Slave interrupt sources are cleared, so that they no +//! longer assert. This must be done in the interrupt handler to keep it from +//! being called again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Clear the I2C slave interrupt source. + HWREG(I2C0_BASE + I2C_O_SICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current I2C Slave interrupt status. +//! +//! This returns the interrupt status for the I2C Slave module. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param bMasked selects either raw or masked interrupt status. +//! - \c false : Raw interrupt status is requested. +//! - \c true : Masked interrupt status is requested. +//! +//! \return Returns the current interrupt status as an OR'ed combination of: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return(HWREG(I2C0_BASE + I2C_O_SMIS)); + } + else + { + return(HWREG(I2C0_BASE + I2C_O_SRIS)); + } +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the I2C module in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific I2C interrupts must be enabled via \ref I2CMasterIntEnable() and +//! \ref I2CSlaveIntEnable(). If necessary, it is the interrupt handler's +//! responsibility to clear the interrupt source via \ref I2CMasterIntClear() and +//! \ref I2CSlaveIntClear(). +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param pfnHandler is a pointer to the function to be called when the +//! I2C interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the I2C module in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when an I2C interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler no longer is called. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! \return None +//! +//! \sa \brief IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void I2CIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_I2CMasterInitExpClk + #undef I2CMasterInitExpClk + #define I2CMasterInitExpClk ROM_I2CMasterInitExpClk + #endif + #ifdef ROM_I2CMasterErr + #undef I2CMasterErr + #define I2CMasterErr ROM_I2CMasterErr + #endif + #ifdef ROM_I2CIntRegister + #undef I2CIntRegister + #define I2CIntRegister ROM_I2CIntRegister + #endif + #ifdef ROM_I2CIntUnregister + #undef I2CIntUnregister + #define I2CIntUnregister ROM_I2CIntUnregister + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c_doc.h new file mode 100644 index 0000000..c339318 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c_doc.h @@ -0,0 +1,162 @@ +/****************************************************************************** +* Filename: i2c_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup i2c_api +//! @{ +//! \section sec_i2c Introduction +//! +//! The Inter-Integrated Circuit (\i2c) API provides a set of functions for using +//! the \ti_device \i2c master and slave module. Functions are provided to perform +//! the following actions: +//! - Initialize the \i2c module. +//! - Send and receive data. +//! - Obtain status. +//! - Manage interrupts for the \i2c module. +//! +//! The \i2c master and slave module provide the ability to communicate to other IC +//! devices over an \i2c bus. The \i2c bus is specified to support devices that can +//! both transmit and receive (write and read) data. Also, devices on the \i2c bus +//! can be designated as either a master or a slave. The \ti_device \i2c module +//! supports both sending and receiving data as either a master or a slave, and also +//! support the simultaneous operation as both a master and a slave. Finally, the +//! \ti_device \i2c module can operate at two speeds: standard (100 kb/s) and fast +//! (400 kb/s). +//! +//! The master and slave \i2c module can generate interrupts. The \i2c master +//! module generates interrupts when a transmit or receive operation +//! completes (or aborts due to an error). +//! The \i2c slave module can generate interrupts when data is +//! sent or requested by a master and when a START or STOP condition is present. +//! +//! \section sec_i2c_master Master Operations +//! +//! When using this API to drive the \i2c master module, the user must first +//! initialize the \i2c master module with a call to \ref I2CMasterInitExpClk(). This +//! function sets the bus speed and enables the master module. +//! +//! The user may transmit or receive data after the successful initialization of +//! the \i2c master module. Data is transferred by first setting the slave address +//! using \ref I2CMasterSlaveAddrSet(). This function is also used to define whether +//! the transfer is a send (a write to the slave from the master) or a receive (a +//! read from the slave by the master). Then, if connected to an \i2c bus that has +//! multiple masters, the \ti_device \i2c master must first call \ref I2CMasterBusBusy() +//! before trying to initiate the desired transaction. After determining that +//! the bus is not busy, if trying to send data, the user must call the +//! \ref I2CMasterDataPut() function. The transaction can then be initiated on the bus +//! by calling the \ref I2CMasterControl() function with any of the following commands: +//! - \ref I2C_MASTER_CMD_SINGLE_SEND +//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE +//! - \ref I2C_MASTER_CMD_BURST_SEND_START +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START +//! +//! Any of these commands result in the master arbitrating for the bus, +//! driving the start sequence onto the bus, and sending the slave address and +//! direction bit across the bus. The remainder of the transaction can then be +//! driven using either a polling or interrupt-driven method. +//! +//! For the single send and receive cases, the polling method involves looping +//! on the return from \ref I2CMasterBusy(). Once the function indicates that the \i2c +//! master is no longer busy, the bus transaction is complete and can be +//! checked for errors using \ref I2CMasterErr(). If there are no errors, then the data +//! has been sent or is ready to be read using \ref I2CMasterDataGet(). For the burst +//! send and receive cases, the polling method also involves calling the +//! \ref I2CMasterControl() function for each byte transmitted or received +//! (using either the \ref I2C_MASTER_CMD_BURST_SEND_CONT or \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! commands), and for the last byte sent or received (using either the +//! \ref I2C_MASTER_CMD_BURST_SEND_FINISH or \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! commands). +//! +//! If any error is detected during the burst transfer, +//! the appropriate stop command (\ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP or +//! \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) should be used to call the +//! \ref I2CMasterControl() function. +//! +//! For the interrupt-driven transaction, the user must register an interrupt +//! handler for the \i2c devices and enable the \i2c master interrupt; the interrupt +//! occurs when the master is no longer busy. +//! +//! \section sec_i2c_slave Slave Operations +//! +//! When using this API to drive the \i2c slave module, the user must first +//! initialize the \i2c slave module with a call to \ref I2CSlaveInit(). This function +//! enables the \i2c slave module and initializes the address of the slave. After the +//! initialization completes, the user may poll the slave status using +//! \ref I2CSlaveStatus() to determine if a master requested a send or receive +//! operation. Depending on the type of operation requested, the user can call +//! \ref I2CSlaveDataPut() or \ref I2CSlaveDataGet() to complete the transaction. +//! Alternatively, the \i2c slave can handle transactions using an interrupt handler +//! registered with \ref I2CIntRegister(), and by enabling the \i2c slave interrupt. +//! +//! \section sec_i2c_api API +//! +//! The \i2c API is broken into three groups of functions: +//! those that handle status and initialization, those that +//! deal with sending and receiving data, and those that deal with +//! interrupts. +//! +//! Status and initialization functions for the \i2c module are: +//! - \ref I2CMasterInitExpClk() +//! - \ref I2CMasterEnable() +//! - \ref I2CMasterDisable() +//! - \ref I2CMasterBusBusy() +//! - \ref I2CMasterBusy() +//! - \ref I2CMasterErr() +//! - \ref I2CSlaveInit() +//! - \ref I2CSlaveEnable() +//! - \ref I2CSlaveDisable() +//! - \ref I2CSlaveStatus() +//! +//! Sending and receiving data from the \i2c module is handled by the following functions: +//! - \ref I2CMasterSlaveAddrSet() +//! - \ref I2CSlaveAddressSet() +//! - \ref I2CMasterControl() +//! - \ref I2CMasterDataGet() +//! - \ref I2CMasterDataPut() +//! - \ref I2CSlaveDataGet() +//! - \ref I2CSlaveDataPut() +//! +//! The \i2c master and slave interrupts are handled by the following functions: +//! - \ref I2CIntRegister() +//! - \ref I2CIntUnregister() +//! - \ref I2CMasterIntEnable() +//! - \ref I2CMasterIntDisable() +//! - \ref I2CMasterIntClear() +//! - \ref I2CMasterIntStatus() +//! - \ref I2CSlaveIntEnable() +//! - \ref I2CSlaveIntDisable() +//! - \ref I2CSlaveIntClear() +//! - \ref I2CSlaveIntStatus() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s.c new file mode 100644 index 0000000..55e935f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s.c @@ -0,0 +1,349 @@ +/****************************************************************************** +* Filename: i2s.c +* Revised: 2017-05-08 12:18:04 +0200 (Mon, 08 May 2017) +* Revision: 48924 +* +* Description: Driver for the I2S. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "i2s.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef I2SEnable + #define I2SEnable NOROM_I2SEnable + #undef I2SAudioFormatConfigure + #define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure + #undef I2SChannelConfigure + #define I2SChannelConfigure NOROM_I2SChannelConfigure + #undef I2SBufferConfig + #define I2SBufferConfig NOROM_I2SBufferConfig + #undef I2SPointerUpdate + #define I2SPointerUpdate NOROM_I2SPointerUpdate + #undef I2SPointerSet + #define I2SPointerSet NOROM_I2SPointerSet + #undef I2SSampleStampConfigure + #define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure + #undef I2SSampleStampGet + #define I2SSampleStampGet NOROM_I2SSampleStampGet +#endif + +//***************************************************************************** +// +// Global pointer to the current I2S data structure +// +//***************************************************************************** +I2SControlTable *g_pControlTable; + +//***************************************************************************** +// +// Enables the I2S module for operation +// +//***************************************************************************** +void +I2SEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Make sure the control table pointer is setup to a memory location. + if(!(g_pControlTable)) + { + return; + } + + // Write the address to the first input/output buffer. + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InBase; + g_pControlTable->ui32InOffset = 0; + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = g_pControlTable->ui32OutBase; + g_pControlTable->ui32OutOffset = 0; + + // Enable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = (uint32_t)g_pControlTable->ui16DMABufSize - 1; +} + +//***************************************************************************** +// +// Configures the I2S module +// +//***************************************************************************** +void +I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg, + uint32_t ui32BitClkDelay) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui32BitClkDelay <= 255); + + // Save the length of the audio words stored in memory. + g_pControlTable->ui16MemLen = (ui32FmtCfg & I2S_MEM_LENGTH_24) ? 24 : 16; + + // Write the configuration. + HWREG(I2S0_BASE + I2S_O_AIFFMTCFG) = ui32FmtCfg | (ui32BitClkDelay << I2S_AIFFMTCFG_DATA_DELAY_S); +} + +//**************************************************************************** +// +// Setup the audio channel configuration +// +//**************************************************************************** +void +I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg, + uint32_t ui32Chan1Cfg) +{ + uint32_t ui32InChan; + uint32_t ui32OutChan; + uint32_t ui32ChanMask; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui32Chan0Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK)) + ASSERT(ui32Chan1Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK)) + + ui32InChan = 0; + ui32OutChan = 0; + + // Configure input/output channels. + HWREG(I2S0_BASE + I2S_O_AIFDIRCFG) = ( + (( ui32Chan0Cfg << I2S_AIFDIRCFG_AD0_S) & I2S_AIFDIRCFG_AD0_M ) | + (( ui32Chan1Cfg << I2S_AIFDIRCFG_AD1_S) & I2S_AIFDIRCFG_AD1_M ) ); + + // Configure the valid channel mask. + HWREG(I2S0_BASE + I2S_O_AIFWMASK0) = (ui32Chan0Cfg >> 8) & I2S_AIFWMASK0_MASK_M; + HWREG(I2S0_BASE + I2S_O_AIFWMASK1) = (ui32Chan1Cfg >> 8) & I2S_AIFWMASK1_MASK_M; + + // Resolve and save the number of input and output channels. + ui32ChanMask = (ui32Chan0Cfg & I2S_CHAN_CFG_MASK) >> 8; + if(ui32Chan0Cfg & I2S_LINE_INPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32InChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + + } + else if(ui32Chan0Cfg & I2S_LINE_OUTPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32OutChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + } + + ui32ChanMask = (ui32Chan1Cfg & I2S_CHAN_CFG_MASK) >> 8; + if(ui32Chan1Cfg & I2S_LINE_INPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32InChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + } + else if(ui32Chan1Cfg & I2S_LINE_OUTPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32OutChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + } + + g_pControlTable->ui8InChan = (uint8_t)ui32InChan; + g_pControlTable->ui8OutChan = (uint8_t)ui32OutChan; +} + +//**************************************************************************** +// +// Set the input buffer pointers +// +//**************************************************************************** +void +I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase, + uint32_t ui32OutBufBase, uint16_t ui16DMABufSize, + uint16_t ui16ChanBufSize) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui16DMABufSize > 0); + + // Setup the input data pointer and buffer sizes. + g_pControlTable->ui16DMABufSize = ui16DMABufSize; + g_pControlTable->ui16ChBufSize = ui16ChanBufSize; + g_pControlTable->ui32InBase = ui32InBufBase; + g_pControlTable->ui32OutBase = ui32OutBufBase; +} + +//**************************************************************************** +// +// Set the buffer pointers +// +//**************************************************************************** +void +I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Update the next input/output pointer with the correct address. + if(bInput == true) + { + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = (uint32_t)pNextPointer; + } + else + { + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = (uint32_t)pNextPointer; + } +} + +//**************************************************************************** +// +// Update the buffer pointers +// +//**************************************************************************** +void +I2SPointerUpdate(uint32_t ui32Base, bool bInput) +{ + uint32_t ui32NextPtr; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Update the next input/output pointer with the correct address. + if(bInput == true) + { + ui32NextPtr = (g_pControlTable->ui8InChan * + (g_pControlTable->ui16MemLen >> 3)) * + g_pControlTable->ui16DMABufSize; + g_pControlTable->ui32InOffset = ((g_pControlTable->ui32InOffset + + ui32NextPtr) % + g_pControlTable->ui16ChBufSize); + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InOffset + + g_pControlTable->ui32InBase; + } + else + { + ui32NextPtr = (g_pControlTable->ui8OutChan * + (g_pControlTable->ui16MemLen >> 3)) * + g_pControlTable->ui16DMABufSize; + g_pControlTable->ui32OutOffset = ((g_pControlTable->ui32OutOffset + + ui32NextPtr) % + g_pControlTable->ui16ChBufSize); + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = + g_pControlTable->ui32OutOffset + + g_pControlTable->ui32OutBase; + } +} + +//***************************************************************************** +// +// Configure the sample stamp generator +// +//***************************************************************************** +void +I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, bool bOutput) +{ + uint32_t ui32Trigger; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + ui32Trigger = HWREG(I2S0_BASE + I2S_O_STMPWCNT); + ui32Trigger = (ui32Trigger + 2) % g_pControlTable->ui16ChBufSize; + + // Setup the sample stamp trigger for input streams. + if(bInput) + { + HWREG(I2S0_BASE + I2S_O_STMPINTRIG) = ui32Trigger; + } + + // Setup the sample stamp trigger for output streams. + if(bOutput) + { + HWREG(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui32Trigger; + } + +} + +//***************************************************************************** +// +// Get the current value of a sample stamp counter +// +//***************************************************************************** +uint32_t +I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel) +{ + uint32_t ui32FrameClkCnt; + uint32_t ui32SysClkCnt; + uint32_t ui32PeriodSysClkCnt; + uint32_t ui32SampleStamp; + + // Get the number of Frame clock counts since last stamp. + ui32FrameClkCnt = HWREG(I2S0_BASE + I2S_O_STMPWCNTCAPT0); + + // Get the number of system clock ticks since last frame clock edge. + ui32SysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXCNTCAPT0); + + // Get the number system clock ticks in the last frame clock period. + ui32PeriodSysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXPER); + + // Calculate the sample stamp. + ui32SampleStamp = (ui32SysClkCnt << 16) / ui32PeriodSysClkCnt; + ui32SampleStamp = (ui32SampleStamp > I2S_STMP_SATURATION) ? + I2S_STMP_SATURATION : ui32SampleStamp; + ui32SampleStamp |= (ui32FrameClkCnt << 16); + + return (ui32SampleStamp); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s.h new file mode 100644 index 0000000..ab50cd6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s.h @@ -0,0 +1,1359 @@ +/****************************************************************************** +* Filename: i2s.h +* Revised: 2018-11-16 11:16:53 +0100 (Fri, 16 Nov 2018) +* Revision: 53356 +* +* Description: Defines and prototypes for the I2S. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//**************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup i2s_api +//! @{ +// +//**************************************************************************** + +#ifndef __I2S_H__ +#define __I2S_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_i2s.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define I2SEnable NOROM_I2SEnable + #define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure + #define I2SChannelConfigure NOROM_I2SChannelConfigure + #define I2SBufferConfig NOROM_I2SBufferConfig + #define I2SPointerUpdate NOROM_I2SPointerUpdate + #define I2SPointerSet NOROM_I2SPointerSet + #define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure + #define I2SSampleStampGet NOROM_I2SSampleStampGet +#endif + +//***************************************************************************** +// +//! \brief A structure that defines an audio control table. Note: Memory for this +//! structure \b must be initialized by user application. See detailed description! +//! +//! \deprecated This structure will be removed in a future release. +//! +//! These fields are used by the I2S and normally it is not necessary for +//! software to directly read or write fields in the table. +//! +//! \note The control table must be defined by the user as a global variable and +//! the global pointer must then be assigned the address of the control table +//! inside a user function (but before calling any I2S-function). +//! +/*! +\verbatim + I2SControlTable g_controlTable; // Define global + g_pControlTable = &g_controlTable; // Assign pointer (inside a function) +\endverbatim +*/ +//! +// +//***************************************************************************** +#ifndef DEPRECATED +typedef struct +{ + uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples. + uint16_t ui16ChBufSize; //!< Size of Channel buffer. + uint8_t ui8InChan; //!< Input Channel. + uint8_t ui8OutChan; //!< Output Channel. + uint16_t ui16MemLen; //!< Length of the audio words stored in memory. + uint32_t ui32InBase; //!< Base address of the input buffer. + uint32_t ui32InOffset; //!< Value of the current input pointer offset. + uint32_t ui32OutBase; //!< Base address of the output buffer. + uint32_t ui32OutOffset; //!< Value of the current output pointer offset. +} I2SControlTable; +#endif + +//***************************************************************************** +// +// Declare global pointer to the I2S data structure. +// +// The control table must be defined by the user as a global variable and the +// global pointer must then be assigned the address of the control table: +// +// I2SControlTable g_controlTable; +// g_pControlTable = &g_controlTable; +// +//***************************************************************************** +#ifndef DEPRECATED +extern I2SControlTable *g_pControlTable; +#endif + +//***************************************************************************** +// +// Defines for the I2S DMA buffer sizes +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_DMA_BUF_SIZE_64 0x00000040 +#define I2S_DMA_BUF_SIZE_128 0x00000080 +#define I2S_DMA_BUF_SIZE_256 0x00000100 +#endif + +//***************************************************************************** +// +// Defines for the I2S audio clock configuration +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_EXT_WCLK 0x00000001 +#define I2S_INT_WCLK 0x00000002 +#define I2S_INVERT_WCLK 0x00000004 +#define I2S_NORMAL_WCLK 0x00000000 +#endif + +//***************************************************************************** +// +// Defines for the audio data line input/output configuration +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_LINE_UNUSED 0x00000000 +#define I2S_LINE_INPUT 0x00000001 +#define I2S_LINE_OUTPUT 0x00000002 +#define I2S_LINE_MASK 0x00000003 +#endif + +//***************************************************************************** +// +// Defines for activating an audio channel. +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_CHAN0_ACT 0x00000100 +#define I2S_CHAN1_ACT 0x00000200 +#define I2S_CHAN2_ACT 0x00000400 +#define I2S_CHAN3_ACT 0x00000800 +#define I2S_CHAN4_ACT 0x00001000 +#define I2S_CHAN5_ACT 0x00002000 +#define I2S_CHAN6_ACT 0x00004000 +#define I2S_CHAN7_ACT 0x00008000 +#define I2S_MONO_MODE 0x00000100 +#define I2S_STEREO_MODE 0x00000300 +#define I2S_CHAN_CFG_MASK 0x0000FF00 +#endif + +#define I2S_CHAN0_MASK 0x00000001 +#define I2S_CHAN1_MASK 0x00000002 +#define I2S_CHAN2_MASK 0x00000004 +#define I2S_CHAN3_MASK 0x00000008 +#define I2S_CHAN4_MASK 0x00000010 +#define I2S_CHAN5_MASK 0x00000020 +#define I2S_CHAN6_MASK 0x00000040 +#define I2S_CHAN7_MASK 0x00000080 + +//***************************************************************************** +// +// Defines for the audio format configuration +// +//***************************************************************************** +#define I2S_MEM_LENGTH_16 0x00000000 // 16 bit size of word in memory +#define I2S_MEM_LENGTH_24 0x00000080 // 24 bit size of word in memory +#define I2S_POS_EDGE 0x00000040 // Sample on positive edge +#define I2S_NEG_EDGE 0x00000000 // Sample on negative edge +#define I2S_DUAL_PHASE_FMT 0x00000020 // Dual Phased audio format +#define I2S_SINGLE_PHASE_FMT 0x00000000 // Single Phased audio format +#define I2S_WORD_LENGTH_8 0x00000008 // Word length is 8 bits +#define I2S_WORD_LENGTH_16 0x00000010 // Word length is 16 bits +#define I2S_WORD_LENGTH_24 0x00000018 // Word length is 24 bits + +//***************************************************************************** +// +// Defines for the sample stamp counters +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_STMP0 0x00000001 // Sample stamp counter channel 0 +#define I2S_STMP1 0x00000002 // Sample stamp counter channel 1 +#endif +#define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when + // calculating the sample stamp + +//***************************************************************************** +// +// Defines for the interrupt +// +//***************************************************************************** +#define I2S_INT_DMA_IN 0x00000020 // DMA output buffer full interrupt +#define I2S_INT_DMA_OUT 0x00000010 // DMA input buffer empty interrupt +#define I2S_INT_TIMEOUT 0x00000008 // Word Clock Timeout +#define I2S_INT_BUS_ERR 0x00000004 // DMA Bus error +#define I2S_INT_WCLK_ERR 0x00000002 // Word Clock error +#define I2S_INT_PTR_ERR 0x00000001 // Data pointer error (DMA data was not updated in time). +#define I2S_INT_ALL 0x0000003F // All interrupts + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an I2S base address. +//! +//! This function determines if an I2S port base address is valid. +//! +//! \param ui32Base is the base address of the I2S port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +I2SBaseValid(uint32_t ui32Base) +{ + return(ui32Base == I2S0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Enables the I2S module for operation. +//! +//! \deprecated This function will be removed in a future release. +//! +//! \note The module should only be enabled after configuration. When the +//! module is disabled, no data or clocks will be generated on the I2S signals. +//! +//! \note Immediately after enabling the module the programmer should update +//! the DMA data pointer registers using \ref I2SPointerUpdate() to ensure a new +//! pointer is written before the DMA transfer completes. Failure to update +//! the pointer in time will result in an \ref I2S_INT_PTR_ERR. +//! +//! \param ui32Base is the I2S module base address. +//! +//! \return None +// +//***************************************************************************** +#ifndef DEPRECATED +extern void I2SEnable(uint32_t ui32Base); +#endif + +//***************************************************************************** +// +//! \brief Disables the I2S module for operation. +//! +//! \deprecated This function will be removed in a future release. +//! +//! This function will immediately disable the I2S module. To ensure that +//! all buffer operations are completed before shutting down, the correct +//! procedure is: +//! 1. Do not update the data pointers using \ref I2SPointerUpdate(). +//! 2. Await next interrupt resulting in \ref I2S_INT_PTR_ERR. +//! 3. Disable the I2S using \ref I2SDisable() and clear the pointer error using +//! \ref I2SIntClear(). +//! 4. Disable bit clock source (done externally). +//! +//! \param ui32Base is the I2S module base address. +//! +//! \return None +// +//***************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x0; +} +#endif + +//***************************************************************************** +// +//! \brief Configures the I2S module. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The word length defines the size of the word transmitted on the data +//! lines. For single phased formats \c I2S_WORD_LENGTH_x is the exact number +//! of bits per word. In dual phased format this is the maximum number of bits +//! per word. The size is set using \ref I2S_WORD_LENGTH_8, +//! \ref I2S_WORD_LENGTH_16 or \ref I2S_WORD_LENGTH_24. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui32FmtCfg is the bitwise OR of several options: +//! - Sample size: +//! - \ref I2S_MEM_LENGTH_16 +//! - \ref I2S_MEM_LENGTH_24 +//! - Clock edge sampling: +//! - \ref I2S_POS_EDGE +//! - \ref I2S_NEG_EDGE +//! - Phase: +//! - \ref I2S_DUAL_PHASE_FMT +//! - \ref I2S_SINGLE_PHASE_FMT +//! - Word length: +//! - \ref I2S_WORD_LENGTH_8 +//! - \ref I2S_WORD_LENGTH_16 +//! - \ref I2S_WORD_LENGTH_24 +//! \param ui32BitClkDelay defines the bit clock delay by setting the number of bit clock periods between the +//! positive word clock edge and the MSB of the first word in a phase. The bit +//! clock delay is determined by the ratio between the bit clock and the frame +//! clock and the chosen audio format. The bit clock delay \b must be configured +//! depending on the chosen audio format: +//! - 0 : Left Justified Format (LJF). +//! - 1 : I2S and DSP format. +//! - 2-255 : Right Justified format (RJF). +//! +//! \return None +//! +//! \sa \ref I2SChannelConfigure() +// +//***************************************************************************** +#ifndef DEPRECATED +extern void I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg, + uint32_t ui32BitClkDelay); +#endif + +//**************************************************************************** +// +//! \brief Setup the audio channel configuration. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The channel configuration is a bitwise OR of the input/output mode of each +//! data line and the active audio channels within a specific audio frame. +//! +//! Setting up the input/output mode use one of: +//! - \ref I2S_LINE_UNUSED +//! - \ref I2S_LINE_INPUT +//! - \ref I2S_LINE_OUTPUT +//! +//! For dual phased audio (LJF,RJF,I2S) only mono and stereo modes are allowed. +//! For single phased audio format (DSP) up to 8 active channels are allowed +//! on a single data line. For setting up the active channels in a frame use: +//! - Single phased, use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_ACT +//! - \ref I2S_CHAN1_ACT +//! - \ref I2S_CHAN2_ACT +//! - \ref I2S_CHAN3_ACT +//! - \ref I2S_CHAN4_ACT +//! - \ref I2S_CHAN5_ACT +//! - \ref I2S_CHAN6_ACT +//! - \ref I2S_CHAN7_ACT +//! - Dual phased, use one of: +//! - \ref I2S_MONO_MODE (same as \ref I2S_CHAN0_ACT) +//! - \ref I2S_STEREO_MODE (same as \ref I2S_CHAN0_ACT | \ref I2S_CHAN1_ACT) +//! +//! \note The audio format and the clock configuration should be set using +//! \ref I2SAudioFormatConfigure() +//! +//! \param ui32Base is base address of the I2S module. +//! \param ui32Chan0Cfg defines the channel configuration for data line 0. +//! \param ui32Chan1Cfg defines the channel configuration for data line 1. +//! +//! \return None +//! +//! \sa \ref I2SAudioFormatConfigure() +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg, + uint32_t ui32Chan1Cfg); +#endif + +//**************************************************************************** +// +//! \brief Configure the I2S frame clock. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Configure I2S clock to be either internal or external and either normal +//! or inverted. +//! +//! \note The bit clock configuration is done externally, but the internal/ +//! external setting must match what is chosen internally in the I2S module +//! for the frame clock. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32ClkConfig is the clock configuration parameter. Bitwise OR'ed +//! combination of clock source and clock polarity: +//! - Clock source: +//! - \ref I2S_EXT_WCLK : External clock. +//! - \ref I2S_INT_WCLK : Internal clock. +//! - Clock polarity: +//! - \ref I2S_NORMAL_WCLK : Normal clock. +//! - \ref I2S_INVERT_WCLK : Inverted clock. +//! +//! \return None +// +//**************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup register WCLK Source. + HWREG(I2S0_BASE + I2S_O_AIFWCLKSRC) = ui32ClkConfig & + (I2S_AIFWCLKSRC_WCLK_INV_M | + I2S_AIFWCLKSRC_WCLK_SRC_M); +} +#endif + +//**************************************************************************** +// +//! \brief Set the input buffer pointers. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will +//! occur and all outputs will be disabled. +//! +//! \note At startup the next data pointer should be +//! written just before and just after calling the \ref I2SEnable(). +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32InBufBase is the address of the input buffer. +//! \param ui32OutBufBase is the address of the output buffer. +//! \param ui16DMABufSize is the size of the DMA buffers. Must be greater than 0! +//! \param ui16ChanBufSize is the size of the channel buffers. +//! +//! \return None +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase, + uint32_t ui32OutBufBase, uint16_t ui16DMABufSize, + uint16_t ui16ChanBufSize); +#endif + +//**************************************************************************** +// +//! \brief Update the buffer pointers. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur +//! and all outputs will be disabled. Nothing is preventing the pointers from +//! being identical, but this function relies on both pointers (input or +//! output pointers) are pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param bInput determines whether to update input or output pointer. +//! - \c true : Update input pointer. +//! - \c false : Update output pointer +//! +//! \return None +//! +//! \sa \ref I2SPointerSet() +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SPointerUpdate(uint32_t ui32Base, bool bInput); +#endif + +//**************************************************************************** +// +//! \brief Set a buffer pointer (input or output) directly. +//! +//! \deprecated This function will be removed in a future release. +//! +//! This function allows bypassing of the pointers in the global control table. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur +//! and all outputs will be disabled. Nothing is preventing the pointers from +//! being identical, but this function relies on both pointers (input or +//! output pointers) are pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param bInput determines whether to update input or output pointer. +//! - \c true : Update input pointer. +//! - \c false : Update output pointer +//! \param pNextPointer is a void pointer to user defined buffer. +//! +//! \return None +//! +//! \sa \ref I2SPointerUpdate() +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer); +#endif + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for an I2S interrupt in the dynamic interrupt table. +//! +//! \deprecated This function will be removed in a future release. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific I2S interrupts must be enabled via \ref I2SIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param pfnHandler is a pointer to the function to be called when the +//! I2S interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Register the interrupt handler. + IntRegister(INT_I2S_IRQ, pfnHandler); + + // Enable the I2S interrupt. + IntEnable(INT_I2S_IRQ); +} +#endif + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a I2S interrupt in the dynamic interrupt table. +//! +//! \deprecated This function will be removed in a future release. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when an I2S interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \param ui32Base is the base address of the I2S port. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SIntUnregister(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the interrupt. + IntDisable(INT_I2S_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_I2S_IRQ); +} +#endif + +//***************************************************************************** +// +//! \brief Configure the sample stamp generator. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param bInput enables triggering of the sample stamp generator on input. +//! \param bOutput enables triggering of the sample stamp generator on output. +//! +//! \return None +// +//***************************************************************************** +#ifndef DEPRECATED +extern void I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, + bool bOutput); +#endif + +//***************************************************************************** +// +//! \brief Enables individual I2S interrupt sources. +//! +//! This function enables the indicated I2S interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2S port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +//! - \ref I2S_INT_ALL (covers all the above) +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +I2SIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(I2S0_BASE + I2S_O_IRQMASK) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual I2S interrupt sources. +//! +//! This function disables the indicated I2S interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2S port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +//! - \ref I2S_INT_ALL (covers all the above) +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +I2SIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(I2S0_BASE + I2S_O_IRQMASK) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the specified I2S. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the I2S port +//! \param bMasked selects between raw and masked interrupt status: +//! - \c false : Raw interrupt status is required. +//! - \c true : Masked interrupt status is required. +//! +//! \return Returns the current interrupt status as a vector of: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2SIntStatus(uint32_t ui32Base, bool bMasked) +{ + uint32_t ui32Mask; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + ui32Mask = HWREG(I2S0_BASE + I2S_O_IRQFLAGS); + return(ui32Mask & HWREG(I2S0_BASE + I2S_O_IRQMASK)); + } + else + { + return(HWREG(I2S0_BASE + I2S_O_IRQFLAGS)); + } +} + +//***************************************************************************** +// +//! \brief Clears I2S interrupt sources. +//! +//! The specified I2S interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the I2S port. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +//! - \ref I2S_INT_ALL (covers all the above) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Clear the requested interrupt sources. + HWREG(I2S0_BASE + I2S_O_IRQCLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Enable the Sample Stamp generator. +//! +//! Use this function to enable the sample stamp generators. +//! +//! \note It is the user's responsibility to ensure that the sample stamp +//! generator is properly configured before it is enabled. It is the setting +//! of the Input and Output triggers configured using \ref I2SSampleStampConfigure() +//! that triggers the start point of the audio streams. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Set the enable bit. + HWREG(I2S0_BASE + I2S_O_STMPCTL) = I2S_STMPCTL_STMP_EN; +} + +//***************************************************************************** +// +//! \brief Disable the Sample Stamp generator. +//! +//! Use this function to disable the sample stamp generators. When the sample +//! stamp generator is disabled, the clock counters are automatically cleared. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Clear the enable bit. + HWREG(I2S0_BASE + I2S_O_STMPCTL) = 0; + +} + +//***************************************************************************** +// +//! \brief Get the current value of a sample stamp counter. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32Channel is the sample stamp counter to sample +//! +//! \return Returns the current value of the selected sample stamp channel. +// +//***************************************************************************** +extern uint32_t I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel); + +//***************************************************************************** +// +//! \brief Starts the I2S. +//! +//! I2S must be configured before it is started. +//! +//! \note Immediately after enabling the module the programmer must update +//! the DMA data pointer registers using \ref I2SInPointerSet() and +//! \ref I2SOutPointerSet() to ensure a new pointer is written before the DMA +//! transfer completes. Failure to update the pointer in time will result in +//! an \ref I2S_INT_PTR_ERR. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui8FixDMALength is the length of the DMA buffer: this will allow +//! the DMA to read ui8FixDMALength between to pointer refreshes. +//! +//! \return None +//! +//! \sa \ref I2SStop() +// +//***************************************************************************** +__STATIC_INLINE void I2SStart(uint32_t ui32Base, uint8_t ui8FixDMALength) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Enable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = ui8FixDMALength; +} + +//***************************************************************************** +// +//! \brief Stops the I2S module for operation. +//! +//! This function will immediately disable the I2S module. To ensure that +//! all buffer operations are completed before shutting down, the correct +//! procedure is: +//! 1. Do not update the data pointers using \ref I2SInPointerSet() and +//! \ref I2SOutPointerSet(). +//! 2. Await that values returned by \ref I2SInPointerNextGet(), +//! \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and \ref I2SOutPointerGet() +//! are zero. +//! 3. Disable the I2S using \ref I2SStop() and clear the pointer +//! error using \ref I2SIntClear(). +//! 4. Disable bit clock source (done externally). +//! +//! \param ui32Base is the I2S module base address. +//! +//! \return None +//! +//! \sa \ref I2SStart() +// +//***************************************************************************** +__STATIC_INLINE void I2SStop(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x00; +} + +//***************************************************************************** +// +//! \brief Configure the serial format of the I2S module. +//! +//! The word length defines the size of the word transmitted on the data +//! lines. For single phased formats \c ui8BitsPerSample is the exact number +//! of bits per word. In dual phased format this is the maximum number of bits +//! per word. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui8iDataDelay is the number of BCLK periods between the first WCLK +//! edge and the MSB of the first audio channel data transferred during +//! the phase. +//! \param ui8iMemory24Bits selects if the samples in memory are coded on 16 bits +//! or 24 bits. Possible values are: +//! - \ref I2S_MEM_LENGTH_16 +//! - \ref I2S_MEM_LENGTH_24 +//! \param ui8iSamplingEdge selects if sampling on falling or rising edges. +//! Possible values are: +//! - \ref I2S_NEG_EDGE +//! - \ref I2S_POS_EDGE +//! \param boolDualPhase must be set to true for dual phase and to false for +//! single phase and user-defined phase. +//! \param ui8BitsPerSample is the number of bits transmitted for each sample. +//! If this number does not match with the memory length selected +//! (16 bits or24 bits), samples will be truncated or padded. +//! \param ui16transmissionDelay is the number of WCLK periods before the first +//! transmission. +//! +//! \return None +//! +//! \sa \ref I2SFrameConfigure() +// +//***************************************************************************** +__STATIC_INLINE void +I2SFormatConfigure(uint32_t ui32Base, + uint8_t ui8iDataDelay, + uint8_t ui8iMemory24Bits, + uint8_t ui8iSamplingEdge, + bool boolDualPhase, + uint8_t ui8BitsPerSample, + uint16_t ui16transmissionDelay) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui8BitsPerSample <= I2S_AIFFMTCFG_WORD_LEN_MAX); + ASSERT(ui8BitsPerSample >= I2S_AIFFMTCFG_WORD_LEN_MIN); + + // Setup register AIFFMTCFG Source. + HWREGH(I2S0_BASE + I2S_O_AIFFMTCFG) = + (ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) | + (ui8iMemory24Bits << I2S_AIFFMTCFG_MEM_LEN_24_S) | + (ui8iSamplingEdge << I2S_AIFFMTCFG_SMPL_EDGE_S ) | + (boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) | + (ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S ); + + // Number of WCLK periods before the first read / write + HWREGH(I2S0_BASE + I2S_O_STMPWPER) = ui16transmissionDelay; +} + +//**************************************************************************** +// +//! \brief Setup the two interfaces SD0 and SD1 (also called AD0 and AD1). +//! +//! This function sets interface's direction and activated channels. +//! +//! \param ui32Base is base address of the I2S module. +//! \param ui8StatusAD0 defines the usage of AD0 +//! 0x00: AD0 is disabled +//! 0x01, AD0 is an input +//! 0x02, AD0 is an output +//! \param ui8ChanAD0 defines the channel mask for AD0. +//! Use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_MASK +//! - \ref I2S_CHAN1_MASK +//! - \ref I2S_CHAN2_MASK +//! - \ref I2S_CHAN3_MASK +//! - \ref I2S_CHAN4_MASK +//! - \ref I2S_CHAN5_MASK +//! - \ref I2S_CHAN6_MASK +//! - \ref I2S_CHAN7_MASK +//! \param ui8StatusAD1 defines the usage of AD1 +//! 0x00: AD1 is disabled +//! 0x10, AD1 is an input +//! 0x20, AD1 is an output +//! \param ui8ChanAD1 defines the channel mask for AD1. +//! Use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_MASK +//! - \ref I2S_CHAN1_MASK +//! - \ref I2S_CHAN2_MASK +//! - \ref I2S_CHAN3_MASK +//! - \ref I2S_CHAN4_MASK +//! - \ref I2S_CHAN5_MASK +//! - \ref I2S_CHAN6_MASK +//! - \ref I2S_CHAN7_MASK +//! +//! \return None +//! +//! \sa \ref I2SFormatConfigure() +// +//**************************************************************************** +__STATIC_INLINE void +I2SFrameConfigure(uint32_t ui32Base, + uint8_t ui8StatusAD0, uint8_t ui8ChanAD0, + uint8_t ui8StatusAD1, uint8_t ui8ChanAD1) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Configure input/output channels. + HWREGB(I2S0_BASE + I2S_O_AIFDIRCFG) = (ui8StatusAD0 | ui8StatusAD1); + + // Configure the valid channel mask. + HWREGB(I2S0_BASE + I2S_O_AIFWMASK0) = ui8ChanAD0; + HWREGB(I2S0_BASE + I2S_O_AIFWMASK1) = ui8ChanAD1; +} + +//**************************************************************************** +// +//! \brief Configure the I2S frame clock (also called WCLK or WS). +//! +//! Configure WCLK clock to be either internal (master) or external (slave). +//! Configure WCLK clock either normal or inverted. +//! +//! \note The bit clock configuration is done externally, but the internal/ +//! external setting must match what is chosen internally in the I2S module +//! for the frame clock. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param boolMaster false: the device is a slave (external clock) +//! true: the device is a master (internal clock) +//! \param boolWCLKInvert false: WCLK is not inverted +//! true: WCLK is internally inverted +//! +//! \return None +// +//**************************************************************************** +__STATIC_INLINE void +I2SWclkConfigure(uint32_t ui32Base, + bool boolMaster, + bool boolWCLKInvert) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui8ClkSource < I2S_AIFWCLKSRC_WCLK_SRC_RESERVED); + + // if(boolMaster == 0) then ui8ClkSource = 1 + // if(boolMaster == 1) then ui8ClkSource = 2 + uint8_t ui8ClkSource = (uint8_t)boolMaster + 0x01; + + // Setup register WCLK Source. + HWREGB(I2S0_BASE + I2S_O_AIFWCLKSRC) = + ((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) | + (boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S )); +} + +//**************************************************************************** +// +//! \brief Set the input buffer pointer. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR +//! will occur and all inputs and outputs will be disabled. +//! This function relies on pointer is pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32NextPointer is the adress of the data +//! +//! \return None +//! +//! \sa \ref I2SOutPointerSet() +// +//**************************************************************************** +__STATIC_INLINE void +I2SInPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = ui32NextPointer; +} + +//**************************************************************************** +// +//! \brief Set the output buffer pointer. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR +//! will occur and all inputs and outputs will be disabled. +//! This function relies on pointer is pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32NextPointer is the adress of the data +//! +//! \return None +//! +//! \sa \ref I2SInPointerSet() +// +//**************************************************************************** +__STATIC_INLINE void +I2SOutPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = ui32NextPointer; +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR NEXT IN register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR NEXT IN. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SInPointerNextGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT)); +} + + +//**************************************************************************** +// +//! \brief Get value stored in PTR NEXT OUT register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR NEXT OUT. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SOutPointerNextGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT)); +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR IN register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR IN. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SInPointerGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFINPTR)); +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR OUT register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR OUT. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SOutPointerGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTR)); +} + +//***************************************************************************** +// +//! \brief Configure the IN sample stamp generator. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui16TrigValue value used to set the trigger. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampInConfigure(uint32_t ui32Base, uint16_t ui16TrigValue) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup the sample stamp trigger for input streams. + HWREGH(I2S0_BASE + I2S_O_STMPINTRIG) = ui16TrigValue; +} + +//***************************************************************************** +// +//! \brief Configure the OUT sample stamp generator. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui16TrigValue value used to set the trigger. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampOutConfigure(uint32_t ui32Base, uint16_t ui16TrigValue) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup the sample stamp trigger for output streams. + HWREGH(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui16TrigValue; +} + +//***************************************************************************** +// +//! \brief Add the specified value to the WCLK count. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param i16Value is the offset to add to the counter (this value can be negative) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SWclkCounterConfigure(uint32_t ui32Base, int16_t i16Value) +{ + uint16_t ui16MinusValue; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + if (i16Value >= 0) + { + HWREGH(I2S0_BASE + I2S_O_STMPWADD) = i16Value; + } + else + { + ui16MinusValue = (uint16_t)(-i16Value); + HWREGH(I2S0_BASE + I2S_O_STMPWADD) = HWREGH(I2S0_BASE + I2S_O_STMPWPER) - ui16MinusValue; + } +} + +//***************************************************************************** +// +//! \brief Reset the WCLK count. +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SWclkCounterReset(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREGH(I2S0_BASE + I2S_O_STMPWSET) = 0; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_I2SEnable + #undef I2SEnable + #define I2SEnable ROM_I2SEnable + #endif + #ifdef ROM_I2SAudioFormatConfigure + #undef I2SAudioFormatConfigure + #define I2SAudioFormatConfigure ROM_I2SAudioFormatConfigure + #endif + #ifdef ROM_I2SChannelConfigure + #undef I2SChannelConfigure + #define I2SChannelConfigure ROM_I2SChannelConfigure + #endif + #ifdef ROM_I2SBufferConfig + #undef I2SBufferConfig + #define I2SBufferConfig ROM_I2SBufferConfig + #endif + #ifdef ROM_I2SPointerUpdate + #undef I2SPointerUpdate + #define I2SPointerUpdate ROM_I2SPointerUpdate + #endif + #ifdef ROM_I2SPointerSet + #undef I2SPointerSet + #define I2SPointerSet ROM_I2SPointerSet + #endif + #ifdef ROM_I2SSampleStampConfigure + #undef I2SSampleStampConfigure + #define I2SSampleStampConfigure ROM_I2SSampleStampConfigure + #endif + #ifdef ROM_I2SSampleStampGet + #undef I2SSampleStampGet + #define I2SSampleStampGet ROM_I2SSampleStampGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2S_H__ + +//**************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//**************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s_doc.h new file mode 100644 index 0000000..27ddceb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s_doc.h @@ -0,0 +1,141 @@ +/****************************************************************************** +* Filename: i2s_doc.h +* Revised: $$ +* Revision: $$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup i2s_api +//! @{ +//! \section sec_i2s Introduction +//! +//! The I2S API provides a set of functions for using the I2S module. +//! This module provides a standardized serial interface to transfer +//! audio samples from and to external audio devices such as a codec, +//! DAC, or ADC. +//! +//! The I2S module has the following features: +//! - Audio clock signals are internally generated by the PRCM module +//! or externally by another device. +//! - One or two data pins, which can be configured independently as +//! input or output +//! - Various data formats according to the settings of the module +//! - Up to two channels per data pin for dual phase formats and up +//! to eight channels per data pin for single phase formats +//! - DMA with double-buffered pointers +//! - Error detection for DMA and audio clock signal integrity +//! - A Samplestamp generator that allows maintaining of constant +//! audio latency +//! +//! The I2S module is configured through the functions \ref I2SFormatConfigure(), +//! \ref I2SFrameConfigure() and \ref I2SWclkConfigure(). +//! Transfers are enabled using \ref I2SStart(). Transfers are disabled using +//! \ref I2SStop(). Please note that a specific procedure exists in order +//! to disable transfers without losing data (refer to \ref I2SStop()). +//! +//! Data are transmitted using the two double-buffered pointers. +//! For each interface, two registers are set with the address of the data to +//! transfer. These registers are named INPTR and INPTRNEXT for the input +//! interface and OUTPTR and OUTPTRNEXT for the output. When PTR is consumed, +//! the hardware copies the content of PTRNEXT into PTR and the next transfer +//! begins. +//! The address of the next value to write or to read in memory (i.e. to receive +//! or to send out) is set using \ref I2SInPointerSet() and \ref I2SOutPointerSet(). +//! The values contented by INPTRNEXT, OUTPTRNEXT, INPTR and OUTPTR can be read using +//! \ref I2SInPointerNextGet(), \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and +//! \ref I2SOutPointerGet() functions. +//! +//! Interrupts can help the user to refresh pointers on time. Interrupts can also +//! be used to detect I2S errors. \ref I2SIntEnable() and \ref I2SIntDisable() +//! activate and deactivate interrupt(s). Interrupt status can be read through +//! \ref I2SIntStatus() and a pending interrupt can be acquitted by +//! \ref I2SIntClear() function. +//! +//! The sample stamps generator can be configured to slightly delay the +//! emission or the reception of the data (based on the number of WCLK +//! cycles) using \ref I2SSampleStampInConfigure(), \ref I2SSampleStampOutConfigure(), +//! \ref I2SWclkCounterReset() and \ref I2SWclkCounterConfigure(). The current sample stamp +//! can be computed using \ref I2SSampleStampGet(). +//! To finish, the sample stamps generator can be enable and disable using +//! the following functions: \ref I2SSampleStampEnable() and +//! \ref I2SSampleStampDisable(). +//! The sample stamps generator must be enabled prior to any transfer. +//! +//! Note: Other functions contained in the PRCM API are required to handle I2S. +//! +//! \section sec_i2s_api API +//! +//! Two APIs are coexisting. +//! It is recommended to only use the new API as the old one is deprecated and +//! will be removed soon. +//! +//! New API: +//! Functions to perform I2S configuration: +//! - \ref I2SStart() +//! - \ref I2SStop() +//! - \ref I2SFormatConfigure() +//! - \ref I2SFrameConfigure() +//! - \ref I2SWclkConfigure() +//! +//! Functions to perform transfers: +//! - \ref I2SInPointerSet() +//! - \ref I2SOutPointerSet() +//! - \ref I2SInPointerGet() +//! - \ref I2SOutPointerGet() +//! - \ref I2SInPointerNextGet() +//! - \ref I2SOutPointerNextGet() +//! +//! Functions to handle interruptions: +//! - \ref I2SIntEnable() +//! - \ref I2SIntDisable() +//! - \ref I2SIntStatus() +//! - \ref I2SIntClear() +//! +//! Functions to handle sample stamps +//! - \ref I2SSampleStampEnable() +//! - \ref I2SSampleStampDisable() +//! - \ref I2SSampleStampInConfigure() +//! - \ref I2SSampleStampOutConfigure() +//! - \ref I2SSampleStampGet() +//! - \ref I2SWclkCounterConfigure() +//! - \ref I2SWclkCounterReset() +//! +//! Old API: +//! \ref I2SEnable(), \ref I2SDisable(), \ref I2SAudioFormatConfigure(), +//! \ref I2SChannelConfigure(), \ref I2SClockConfigure(), +//! \ref I2SBufferConfig(), \ref I2SIntEnable(), \ref I2SIntDisable(), +//! \ref I2SIntStatus(), \ref I2SIntClear(), \ref I2SSampleStampEnable(), +//! \ref I2SSampleStampDisable(), \ref I2SSampleStampGet(), +//! \ref I2SPointerSet (), \ref I2SPointerUpdate(), +//! \ref I2SSampleStampConfigure(), \ref I2SIntRegister(), +//! \ref I2SIntUnregister() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt.c new file mode 100644 index 0000000..b902690 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt.c @@ -0,0 +1,469 @@ +/****************************************************************************** +* Filename: interrupt.c +* Revised: 2017-05-19 11:31:39 +0200 (Fri, 19 May 2017) +* Revision: 49017 +* +* Description: Driver for the NVIC Interrupt Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "interrupt.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef IntRegister + #define IntRegister NOROM_IntRegister + #undef IntUnregister + #define IntUnregister NOROM_IntUnregister + #undef IntPriorityGroupingSet + #define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet + #undef IntPriorityGroupingGet + #define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet + #undef IntPrioritySet + #define IntPrioritySet NOROM_IntPrioritySet + #undef IntPriorityGet + #define IntPriorityGet NOROM_IntPriorityGet + #undef IntEnable + #define IntEnable NOROM_IntEnable + #undef IntDisable + #define IntDisable NOROM_IntDisable + #undef IntPendSet + #define IntPendSet NOROM_IntPendSet + #undef IntPendGet + #define IntPendGet NOROM_IntPendGet + #undef IntPendClear + #define IntPendClear NOROM_IntPendClear +#endif + +//***************************************************************************** +// +//! This is a mapping between priority grouping encodings and the number of +//! preemption priority bits. +// +//***************************************************************************** +static const uint32_t g_pui32Priority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; + +//***************************************************************************** +// +//! This is a mapping between interrupt number and the register that contains +//! the priority encoding for that interrupt. +// +//***************************************************************************** +static const uint32_t g_pui32Regs[] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13 +}; + +//***************************************************************************** +// +//! \brief The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts should be disabled before unregistering the +//! corresponding handler, this should never be called. +//! +//! \return None +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // Go into an infinite loop. + while(1) + { + } +} + +//***************************************************************************** +// +//! \brief Global pointer to the (dynamic) interrupt vector table when placed in SRAM. +//! +//! Interrupt vector table is placed at "vtable_ram" defined in the linker file +//! provided by Texas Instruments. By default, this is at the beginning of SRAM. +//! +//! \note See \ti_code{interrupt.c} for compiler specific implementation! +// +//***************************************************************************** +#if defined(DOXYGEN) +// Dummy void pointer used as placeholder to generate Doxygen documentation. +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma data_alignment=256 +static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ ".vtable_ram"; +#elif defined(__TI_COMPILER_VERSION__) +#pragma DATA_ALIGN(g_pfnRAMVectors, 256) +#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable_ram") +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#elif defined (__CC_ARM) +static __attribute__((section("vtable_ram"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256))); +#else +static __attribute__((section("vtable_ram"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256))); +#endif + +//***************************************************************************** +// +// Registers a function to be called when an interrupt occurs. +// +//***************************************************************************** +void +IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)) +{ + uint32_t ui32Idx, ui32Value; + + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Make sure that the RAM vector table is correctly aligned. + ASSERT(((uint32_t)g_pfnRAMVectors & 0x000000ff) == 0); + + // See if the RAM vector table has been initialized. + if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors) + { + // Copy the vector table from the beginning of FLASH to the RAM vector + // table. + ui32Value = HWREG(NVIC_VTABLE); + for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++) + { + g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) + + ui32Value); + } + + // Point NVIC at the RAM vector table. + HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors; + } + + // Save the interrupt handler. + g_pfnRAMVectors[ui32Interrupt] = pfnHandler; +} + +//***************************************************************************** +// +// Unregisters the function to be called when an interrupt occurs. +// +//***************************************************************************** +void +IntUnregister(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Reset the interrupt handler. + g_pfnRAMVectors[ui32Interrupt] = IntDefaultHandler; +} + +//***************************************************************************** +// +// Sets the priority grouping of the interrupt controller. +// +//***************************************************************************** +void +IntPriorityGroupingSet(uint32_t ui32Bits) +{ + // Check the arguments. + ASSERT(ui32Bits < NUM_PRIORITY); + + // Set the priority grouping. + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; +} + +//***************************************************************************** +// +// Gets the priority grouping of the interrupt controller +// +//***************************************************************************** +uint32_t +IntPriorityGroupingGet(void) +{ + uint32_t ui32Loop, ui32Value; + + // Read the priority grouping. + ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // Loop through the priority grouping values. + for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++) + { + // Stop looping if this value matches. + if(ui32Value == g_pui32Priority[ui32Loop]) + { + break; + } + } + + // Return the number of priority bits. + return(ui32Loop); +} + +//***************************************************************************** +// +// Sets the priority of an interrupt +// +//***************************************************************************** +void +IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority) +{ + uint32_t ui32Temp; + + // Check the arguments. + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + ASSERT(ui8Priority <= INT_PRI_LEVEL7); + + // Set the interrupt priority. + ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); + ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3))); + ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3)); + HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; +} + +//***************************************************************************** +// +// Gets the priority of an interrupt +// +//***************************************************************************** +int32_t +IntPriorityGet(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + + // Return the interrupt priority. + return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) & + 0xFF); +} + +//***************************************************************************** +// +// Enables an interrupt +// +//***************************************************************************** +void +IntEnable(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to enable. + if(ui32Interrupt == INT_MEMMANAGE_FAULT) + { + // Enable the MemManage interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ui32Interrupt == INT_BUS_FAULT) + { + // Enable the bus fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ui32Interrupt == INT_USAGE_FAULT) + { + // Enable the usage fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Enable the System Tick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Enable the general interrupt. + HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Enable the general interrupt. + HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48); + } +} + +//***************************************************************************** +// +// Disables an interrupt +// +//***************************************************************************** +void +IntDisable(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to disable. + if(ui32Interrupt == INT_MEMMANAGE_FAULT) + { + // Disable the MemManage interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ui32Interrupt == INT_BUS_FAULT) + { + // Disable the bus fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ui32Interrupt == INT_USAGE_FAULT) + { + // Disable the usage fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Disable the System Tick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Disable the general interrupt. + HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Disable the general interrupt. + HWREG(NVIC_DIS1) = 1 << (ui32Interrupt - 48); + } +} + +//***************************************************************************** +// +// Pends an interrupt +// +//***************************************************************************** +void +IntPendSet(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to pend. + if(ui32Interrupt == INT_NMI_FAULT) + { + // Pend the NMI interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; + } + else if(ui32Interrupt == INT_PENDSV) + { + // Pend the PendSV interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Pend the SysTick interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Pend the general interrupt. + HWREG(NVIC_PEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Pend the general interrupt. + HWREG(NVIC_PEND1) = 1 << (ui32Interrupt - 48); + } +} + +//***************************************************************************** +// +// Query whether an interrupt is pending +// +//***************************************************************************** +bool +IntPendGet(uint32_t ui32Interrupt) +{ + uint32_t ui32IntPending; + + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Assume no interrupts are pending. + ui32IntPending = 0; + + // The lower 16 IRQ vectors are unsupported by this function + if (ui32Interrupt < 16) + { + + return 0; + } + + // Subtract lower 16 irq vectors + ui32Interrupt -= 16; + + // Check if the interrupt is pending + ui32IntPending = HWREG(NVIC_PEND0 + (ui32Interrupt / 32)); + ui32IntPending &= (1 << (ui32Interrupt & 31)); + + return ui32IntPending ? true : false; +} + +//***************************************************************************** +// +// Unpends an interrupt +// +//***************************************************************************** +void +IntPendClear(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to unpend. + if(ui32Interrupt == INT_PENDSV) + { + // Unpend the PendSV interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Unpend the SysTick interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Unpend the general interrupt. + HWREG(NVIC_UNPEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Unpend the general interrupt. + HWREG(NVIC_UNPEND1) = 1 << (ui32Interrupt - 48); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt.h new file mode 100644 index 0000000..3cb3969 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt.h @@ -0,0 +1,702 @@ +/****************************************************************************** +* Filename: interrupt.h +* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) +* Revision: 50272 +* +* Description: Defines and prototypes for the NVIC Interrupt Controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_types.h" +#include "../inc/hw_nvic.h" +#include "debug.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define IntRegister NOROM_IntRegister + #define IntUnregister NOROM_IntUnregister + #define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet + #define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet + #define IntPrioritySet NOROM_IntPrioritySet + #define IntPriorityGet NOROM_IntPriorityGet + #define IntEnable NOROM_IntEnable + #define IntDisable NOROM_IntDisable + #define IntPendSet NOROM_IntPendSet + #define IntPendGet NOROM_IntPendGet + #define IntPendClear NOROM_IntPendClear +#endif + +//***************************************************************************** +// +// Macro to generate an interrupt priority mask based on the number of bits +// of priority supported by the hardware. For CC26xx the number of priority +// bit is 3 as defined in hw_types.h. The priority mask is +// defined as +// +// INT_PRIORITY_MASK = ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) +// +//***************************************************************************** +#define INT_PRIORITY_MASK 0x000000E0 +#define INT_PRI_LEVEL0 0x00000000 +#define INT_PRI_LEVEL1 0x00000020 +#define INT_PRI_LEVEL2 0x00000040 +#define INT_PRI_LEVEL3 0x00000060 +#define INT_PRI_LEVEL4 0x00000080 +#define INT_PRI_LEVEL5 0x000000A0 +#define INT_PRI_LEVEL6 0x000000C0 +#define INT_PRI_LEVEL7 0x000000E0 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Registers a function as an interrupt handler in the dynamic vector table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function writes a function pointer to the dynamic interrupt vector table +//! in SRAM to register the function as an interrupt handler (ISR). When the corresponding +//! interrupt occurs, and it has been enabled (see \ref IntEnable()), the function +//! pointer is fetched from the dynamic vector table, and the System CPU will +//! execute the interrupt handler. +//! +//! \note The first call to this function (directly or indirectly via a peripheral +//! driver interrupt register function) copies the interrupt vector table from +//! Flash to SRAM. NVIC uses the static vector table (in Flash) until this function +//! is called. +//! +//! \param ui32Interrupt specifies the index in the vector table to modify. +//! - System exceptions (vectors 0 to 15): +//! - INT_NMI_FAULT +//! - INT_HARD_FAULT +//! - INT_MEMMANAGE_FAULT +//! - INT_BUS_FAULT +//! - INT_USAGE_FAULT +//! - INT_SVCALL +//! - INT_DEBUG +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts (vectors >15): +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_SPIS_COMB +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_SSI1_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! \param pfnHandler is a pointer to the function to register as interrupt handler. +//! +//! \return None. +//! +//! \sa \ref IntUnregister(), \ref IntEnable() +// +//***************************************************************************** +extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler in the dynamic vector table. +//! +//! This function removes an interrupt handler from the dynamic vector table and +//! replaces it with the default interrupt handler \ref IntDefaultHandler(). +//! +//! \note Remember to disable the interrupt before removing its interrupt handler +//! from the vector table. +//! +//! \param ui32Interrupt specifies the index in the vector table to modify. +//! - See \ref IntRegister() for list of valid arguments. +//! +//! \return None. +//! +//! \sa \ref IntRegister(), \ref IntDisable() +// +//***************************************************************************** +extern void IntUnregister(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Sets the priority grouping of the interrupt controller. +//! +//! This function specifies the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! Three bits are available for hardware interrupt prioritization thus priority +//! grouping values of three through seven have the same effect. +//! +//! \param ui32Bits specifies the number of bits of preemptable priority. +//! - 0 : No pre-emption priority, eight bits of subpriority. +//! - 1 : One bit of pre-emption priority, seven bits of subpriority +//! - 2 : Two bits of pre-emption priority, six bits of subpriority +//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority +//! +//! \return None +//! +//! \sa \ref IntPrioritySet() +// +//***************************************************************************** +extern void IntPriorityGroupingSet(uint32_t ui32Bits); + +//***************************************************************************** +// +//! \brief Gets the priority grouping of the interrupt controller. +//! +//! This function returns the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! \return Returns the number of bits of preemptable priority. +//! - 0 : No pre-emption priority, eight bits of subpriority. +//! - 1 : One bit of pre-emption priority, seven bits of subpriority +//! - 2 : Two bits of pre-emption priority, six bits of subpriority +//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority +// +//***************************************************************************** +extern uint32_t IntPriorityGroupingGet(void); + +//***************************************************************************** +// +//! \brief Sets the priority of an interrupt. +//! +//! This function sets the priority of an interrupt, including system exceptions. +//! When multiple interrupts are asserted simultaneously, the ones with the highest +//! priority are processed before the lower priority interrupts. Smaller numbers +//! correspond to higher interrupt priorities thus priority 0 is the highest +//! interrupt priority. +//! +//! \warning This function does not support setting priority of interrupt vectors +//! one through three which are: +//! - 1: Reset handler +//! - 2: NMI handler +//! - 3: Hard fault handler +//! +//! \param ui32Interrupt specifies the index in the vector table to change priority for. +//! - System exceptions: +//! - INT_MEMMANAGE_FAULT +//! - INT_BUS_FAULT +//! - INT_USAGE_FAULT +//! - INT_SVCALL +//! - INT_DEBUG +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_SPIS_COMB +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_SSI1_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! \param ui8Priority specifies the priority of the interrupt. +//! - \ref INT_PRI_LEVEL0 : Highest priority. +//! - \ref INT_PRI_LEVEL1 +//! - \ref INT_PRI_LEVEL2 +//! - \ref INT_PRI_LEVEL3 +//! - \ref INT_PRI_LEVEL4 +//! - \ref INT_PRI_LEVEL5 +//! - \ref INT_PRI_LEVEL6 +//! - \ref INT_PRI_LEVEL7 : Lowest priority. +//! +//! \return None +//! +//! \sa \ref IntPriorityGroupingSet() +// +//***************************************************************************** +extern void IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority); + +//***************************************************************************** +// +//! \brief Gets the priority of an interrupt. +//! +//! This function gets the priority of an interrupt. +//! +//! \warning This function does not support getting priority of interrupt vectors +//! one through three which are: +//! - 1: Reset handler +//! - 2: NMI handler +//! - 3: Hard fault handler +//! +//! \param ui32Interrupt specifies the index in the vector table to read priority of. +//! - See \ref IntPrioritySet() for list of valid arguments. +//! +//! \return Returns the interrupt priority: +//! - \ref INT_PRI_LEVEL0 : Highest priority. +//! - \ref INT_PRI_LEVEL1 +//! - \ref INT_PRI_LEVEL2 +//! - \ref INT_PRI_LEVEL3 +//! - \ref INT_PRI_LEVEL4 +//! - \ref INT_PRI_LEVEL5 +//! - \ref INT_PRI_LEVEL6 +//! - \ref INT_PRI_LEVEL7 : Lowest priority. +// +//***************************************************************************** +extern int32_t IntPriorityGet(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Enables an interrupt or system exception. +//! +//! This function enables the specified interrupt in the interrupt controller. +//! +//! \note If a fault condition occurs while the corresponding system exception +//! is disabled, the fault is treated as a Hard Fault. +//! +//! \param ui32Interrupt specifies the index in the vector table to enable. +//! - System exceptions: +//! - INT_MEMMANAGE_FAULT +//! - INT_BUS_FAULT +//! - INT_USAGE_FAULT +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_SPIS_COMB +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_SSI1_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! +//! \return None +//! +//! \sa \ref IntDisable() +// +//***************************************************************************** +extern void IntEnable(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Disables an interrupt or system exception. +//! +//! This function disables the specified interrupt in the interrupt controller. +//! +//! \param ui32Interrupt specifies the index in the vector table to disable. +//! - See \ref IntEnable() for list of valid arguments. +//! +//! \return None +//! +//! \sa \ref IntEnable() +// +//***************************************************************************** +extern void IntDisable(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Pends an interrupt. +//! +//! This function pends the specified interrupt in the interrupt controller. +//! This causes the interrupt controller to execute the corresponding interrupt +//! handler at the next available time, based on the current interrupt state +//! priorities. +//! +//! This interrupt controller automatically clears the pending interrupt once the +//! interrupt handler is executed. +//! +//! \param ui32Interrupt specifies the index in the vector table to pend. +//! - System exceptions: +//! - INT_NMI_FAULT +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_SPIS_COMB +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_SSI1_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! +//! \return None +//! +//! \sa \ref IntEnable() +// +//***************************************************************************** +extern void IntPendSet(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Checks if an interrupt is pending. +//! +//! This function checks the interrupt controller to see if an interrupt is pending. +//! +//! The interrupt must be enabled in order for the corresponding interrupt handler +//! to be executed, so an interrupt can be pending waiting to be enabled or waiting +//! for an interrupt of higher priority to be done executing. +//! +//! \note This function does not support reading pending status for system exceptions +//! (vector table indexes <16). +//! +//! \param ui32Interrupt specifies the index in the vector table to check pending +//! status for. +//! - See \ref IntPendSet() for list of valid arguments (except system exceptions). +//! +//! \return Returns: +//! - \c true : Specified interrupt is pending. +//! - \c false : Specified interrupt is not pending. +// +//***************************************************************************** +extern bool IntPendGet(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Unpends an interrupt. +//! +//! This function unpends the specified interrupt in the interrupt controller. +//! This causes any previously generated interrupts that have not been handled yet +//! (due to higher priority interrupts or the interrupt no having been enabled +//! yet) to be discarded. +//! +//! \note It is not possible to unpend the NMI because it takes effect +//! immediately when being pended. +//! +//! \param ui32Interrupt specifies the index in the vector table to unpend. +//! - See \ref IntPendSet() for list of valid arguments (except NMI). +//! +//! \return None +// +//***************************************************************************** +extern void IntPendClear(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Enables the CPU interrupt. +//! +//! Allows the CPU to respond to interrupts. +//! +//! \return Returns: +//! - \c true : Interrupts were disabled and are now enabled. +//! - \c false : Interrupts were already enabled when the function was called. +// +//***************************************************************************** +__STATIC_INLINE bool +IntMasterEnable(void) +{ + // Enable CPU interrupts. + return(CPUcpsie()); +} + +//***************************************************************************** +// +//! \brief Disables the CPU interrupts with configurable priority. +//! +//! Prevents the CPU from receiving interrupts except NMI and hard fault. This +//! does not affect the set of interrupts enabled in the interrupt controller; +//! it just gates the interrupt from the interrupt controller to the CPU. +//! +//! \return Returns: +//! - \c true : Interrupts were already disabled when the function was called. +//! - \c false : Interrupts were enabled and are now disabled. +// +//***************************************************************************** +__STATIC_INLINE bool +IntMasterDisable(void) +{ + // Disable CPU interrupts. + return(CPUcpsid()); +} + +//***************************************************************************** +// +//! \brief Sets the priority masking level. +//! +//! This function sets the interrupt priority masking level so that all +//! interrupts at the specified or lesser priority level are masked. This +//! can be used to globally disable a set of interrupts with priority below +//! a predetermined threshold. A value of 0 disables priority +//! masking. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 will allow interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! The device supports priority levels 0 through 7. +//! +//! \param ui32PriorityMask is the priority level that will be masked. +//! - 0 : Disable priority masking. +//! - 1 : Allow priority 0 interrupts, mask interrupts with priority 1-7. +//! - 2 : Allow priority 0-1 interrupts, mask interrupts with priority 2-7. +//! - 3 : Allow priority 0-2 interrupts, mask interrupts with priority 3-7. +//! - 4 : Allow priority 0-3 interrupts, mask interrupts with priority 4-7. +//! - 5 : Allow priority 0-4 interrupts, mask interrupts with priority 5-7. +//! - 6 : Allow priority 0-5 interrupts, mask interrupts with priority 6-7. +//! - 7 : Allow priority 0-6 interrupts, mask interrupts with priority 7. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +IntPriorityMaskSet(uint32_t ui32PriorityMask) +{ + CPUbasepriSet(ui32PriorityMask); +} + +//***************************************************************************** +// +//! \brief Gets the priority masking level. +//! +//! This function gets the current setting of the interrupt priority masking +//! level. The value returned is the priority level such that all interrupts +//! of that and lesser priority are masked. A value of 0 means that priority +//! masking is disabled. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 will allow interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! +//! \return Returns the value of the interrupt priority level mask. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +IntPriorityMaskGet(void) +{ + return(CPUbasepriGet()); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_IntRegister + #undef IntRegister + #define IntRegister ROM_IntRegister + #endif + #ifdef ROM_IntUnregister + #undef IntUnregister + #define IntUnregister ROM_IntUnregister + #endif + #ifdef ROM_IntPriorityGroupingSet + #undef IntPriorityGroupingSet + #define IntPriorityGroupingSet ROM_IntPriorityGroupingSet + #endif + #ifdef ROM_IntPriorityGroupingGet + #undef IntPriorityGroupingGet + #define IntPriorityGroupingGet ROM_IntPriorityGroupingGet + #endif + #ifdef ROM_IntPrioritySet + #undef IntPrioritySet + #define IntPrioritySet ROM_IntPrioritySet + #endif + #ifdef ROM_IntPriorityGet + #undef IntPriorityGet + #define IntPriorityGet ROM_IntPriorityGet + #endif + #ifdef ROM_IntEnable + #undef IntEnable + #define IntEnable ROM_IntEnable + #endif + #ifdef ROM_IntDisable + #undef IntDisable + #define IntDisable ROM_IntDisable + #endif + #ifdef ROM_IntPendSet + #undef IntPendSet + #define IntPendSet ROM_IntPendSet + #endif + #ifdef ROM_IntPendGet + #undef IntPendGet + #define IntPendGet ROM_IntPendGet + #endif + #ifdef ROM_IntPendClear + #undef IntPendClear + #define IntPendClear ROM_IntPendClear + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt_doc.h new file mode 100644 index 0000000..ff02174 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt_doc.h @@ -0,0 +1,162 @@ +/****************************************************************************** +* Filename: interrupt_doc.h +* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) +* Revision: 50272 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup interrupt_api +//! @{ +//! \section sec_interrupt Introduction +//! +//! The interrupt controller API provides a set of functions for dealing with the +//! Nested Vectored Interrupt Controller (NVIC). Functions are provided to enable +//! and disable interrupts, register interrupt handlers, and set the priority of +//! interrupts. +//! +//! The event sources that trigger the interrupt lines in the NVIC are controlled by +//! the MCU event fabric. All event sources are statically connected to the NVIC interrupt lines +//! except one which is programmable. For more information about the MCU event fabric, see the +//! [MCU event fabric API](\ref event_api). +//! +//! \section sec_interrupt_api API +//! +//! Interrupts and system exceptions must be individually enabled and disabled through: +//! - \ref IntEnable() +//! - \ref IntDisable() +//! +//! The global CPU interrupt can be enabled and disabled with the following functions: +//! - \ref IntMasterEnable() +//! - \ref IntMasterDisable() +//! +//! This does not affect the individual interrupt enable states. Masking of the CPU +//! interrupt can be used as a simple critical section (only an NMI can interrupt the +//! CPU while the CPU interrupt is disabled), although masking the CPU +//! interrupt can increase the interrupt response time. +//! +//! It is possible to access the NVIC to see if any interrupts are pending and manually +//! clear pending interrupts which have not yet been serviced or set a specific interrupt as +//! pending to be handled based on its priority. Pending interrupts are cleared automatically +//! when the interrupt is accepted and executed. However, the event source which caused the +//! interrupt might need to be cleared manually to avoid re-triggering the corresponding interrupt. +//! The functions to read, clear, and set pending interrupts are: +//! - \ref IntPendGet() +//! - \ref IntPendClear() +//! - \ref IntPendSet() +//! +//! The interrupt prioritization in the NVIC allows handling of higher priority interrupts +//! before lower priority interrupts, as well as allowing preemption of lower priority interrupt +//! handlers by higher priority interrupts. +//! The device supports eight priority levels from 0 to 7 with 0 being the highest priority. +//! The priority of each interrupt source can be set and examined using: +//! - \ref IntPrioritySet() +//! - \ref IntPriorityGet() +//! +//! Interrupts can be masked based on their priority such that interrupts with the same or lower +//! priority than the mask are effectively disabled. This can be configured with: +//! - \ref IntPriorityMaskSet() +//! - \ref IntPriorityMaskGet() +//! +//! Subprioritization is also possible. Instead of having three bits of preemptable +//! prioritization (eight levels), the NVIC can be configured for 3 - M bits of +//! preemptable prioritization and M bits of subpriority. In this scheme, two +//! interrupts with the same preemptable prioritization but different subpriorities +//! do not cause a preemption. Instead, tail chaining is used to process +//! the two interrupts back-to-back. +//! If two interrupts with the same priority (and subpriority if so configured) are +//! asserted at the same time, the one with the lower interrupt number is +//! processed first. +//! Subprioritization is handled by: +//! - \ref IntPriorityGroupingSet() +//! - \ref IntPriorityGroupingGet() +//! +//! \section sec_interrupt_table Interrupt Vector Table +//! +//! The interrupt vector table can be configured in one of two ways: +//! - Statically (at compile time): Vector table is placed in Flash and each entry has a fixed +//! pointer to an interrupt handler (ISR). +//! - Dynamically (at runtime): Vector table is placed in SRAM and each entry can be changed +//! (registered or unregistered) at runtime. This allows a single interrupt to trigger different +//! interrupt handlers (ISRs) depending on which interrupt handler is registered at the time the +//! System CPU responds to the interrupt. +//! +//! When configured, the interrupts must be explicitly enabled in the NVIC through \ref IntEnable() +//! before the CPU can respond to the interrupt (in addition to any interrupt enabling required +//! within the peripheral). +//! +//! \subsection sec_interrupt_table_static Static Vector Table +//! +//! Static registration of interrupt handlers is accomplished by editing the interrupt handler +//! table in the startup code of the application. Texas Instruments provides startup files for +//! each supported compiler ( \ti_code{startup_.c} ) and these startup files include +//! a default static interrupt vector table. +//! All entries, except ResetISR, are declared as \c extern with weak assignment to a default +//! interrupt handler. This allows the user to declare and define a function (in the user's code) +//! with the same name as an entry in the vector table. At compile time, the linker then replaces +//! the pointer to the default interrupt handler in the vector table with the pointer to the +//! interrupt handler defined by the user. +//! +//! Statically configuring the interrupt table provides the fastest interrupt response time +//! because the stacking operation (a write to SRAM on the data bus) is performed in parallel +//! with the interrupt handler table fetch (a read from Flash on the instruction bus), as well +//! as the prefetch of the interrupt handler (assuming it is also in Flash). +//! +//! \subsection sec_interrupt_table_dynamic Dynamic Vector Table +//! +//! Alternatively, interrupts can be registered in the vector table at runtime, thus dynamically. +//! The dynamic vector table is placed in SRAM and the code can then modify the pointers to +//! interrupt handlers throughout the application. +//! +//! DriverLib uses these two functions to modify the dynamic vector table: +//! - \ref IntRegister() : Write a pointer to an interrupt handler into the vector table. +//! - \ref IntUnregister() : Write pointer to default interrupt handler into the vector table. +//! +//! \note First call to \ref IntRegister() initializes the vector table in SRAM by copying the +//! static vector table from Flash and forcing the NVIC to use the dynamic vector table from +//! this point forward. If using the dynamic vector table it is highly recommended to +//! initialize it during the setup phase of the application. The NVIC uses the static vector +//! table in Flash until the application initializes the dynamic vector table in SRAM. +//! +//! Runtime configuration of interrupts adds a small latency to the interrupt response time +//! because the stacking operation (a write to SRAM on the data bus) and the interrupt handler +//! fetch from the vector table (a read from SRAM on the instruction bus) must be performed +//! sequentially. +//! +//! The dynamic vector table, \ref g_pfnRAMVectors, is placed in SRAM in the section called +//! \c vtable_ram which is a section defined in the linker file. By default the linker file +//! places this section at the start of the SRAM but this is configurable by the user. +//! +//! \warning Runtime configuration of interrupt handlers requires that the interrupt +//! handler table is placed on a 256-byte boundary in SRAM (typically, this is +//! at the beginning of SRAM). Failure to do so results in an incorrect vector +//! address being fetched in response to an interrupt. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc.c new file mode 100644 index 0000000..769d864 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc.c @@ -0,0 +1,645 @@ +/****************************************************************************** +* Filename: ioc.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the IOC. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ioc.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef IOCPortConfigureSet + #define IOCPortConfigureSet NOROM_IOCPortConfigureSet + #undef IOCPortConfigureGet + #define IOCPortConfigureGet NOROM_IOCPortConfigureGet + #undef IOCIOShutdownSet + #define IOCIOShutdownSet NOROM_IOCIOShutdownSet + #undef IOCIOModeSet + #define IOCIOModeSet NOROM_IOCIOModeSet + #undef IOCIOIntSet + #define IOCIOIntSet NOROM_IOCIOIntSet + #undef IOCIOPortPullSet + #define IOCIOPortPullSet NOROM_IOCIOPortPullSet + #undef IOCIOHystSet + #define IOCIOHystSet NOROM_IOCIOHystSet + #undef IOCIOInputSet + #define IOCIOInputSet NOROM_IOCIOInputSet + #undef IOCIOSlewCtrlSet + #define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet + #undef IOCIODrvStrengthSet + #define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet + #undef IOCIOPortIdSet + #define IOCIOPortIdSet NOROM_IOCIOPortIdSet + #undef IOCIntEnable + #define IOCIntEnable NOROM_IOCIntEnable + #undef IOCIntDisable + #define IOCIntDisable NOROM_IOCIntDisable + #undef IOCPinTypeGpioInput + #define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput + #undef IOCPinTypeGpioOutput + #define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput + #undef IOCPinTypeUart + #define IOCPinTypeUart NOROM_IOCPinTypeUart + #undef IOCPinTypeSsiMaster + #define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster + #undef IOCPinTypeSsiSlave + #define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave + #undef IOCPinTypeI2c + #define IOCPinTypeI2c NOROM_IOCPinTypeI2c + #undef IOCPinTypeAux + #define IOCPinTypeAux NOROM_IOCPinTypeAux +#endif + +//***************************************************************************** +// +// Set the configuration of an IO port +// +//***************************************************************************** +void +IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, + uint32_t ui32IOConfig) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the port. + HWREG(ui32Reg) = ui32IOConfig | ui32PortId; +} + +//***************************************************************************** +// +// Get the configuration of an IO port +// +//***************************************************************************** +uint32_t +IOCPortConfigureGet(uint32_t ui32IOId) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Return the IO configuration. + return HWREG(ui32Reg); +} + +//***************************************************************************** +// +// Set wake-up on an IO port +// +//***************************************************************************** +void +IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) || + (ui32IOShutdown == IOC_WAKE_ON_LOW) || + (ui32IOShutdown == IOC_WAKE_ON_HIGH)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_WU_CFG_M; + HWREG(ui32Reg) = ui32Config | ui32IOShutdown; +} + + +//***************************************************************************** +// +// Set the IO Mode of an IO Port +// +//***************************************************************************** +void +IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) || + (ui32IOMode == IOC_IOMODE_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_INV)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_IOMODE_M; + HWREG(ui32Reg) = ui32Config | ui32IOMode; +} + +//***************************************************************************** +// +// Setup interrupt detection on an IO Port +// +//***************************************************************************** +void +IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Int == IOC_INT_ENABLE) || + (ui32Int == IOC_INT_DISABLE)); + ASSERT((ui32EdgeDet == IOC_NO_EDGE) || + (ui32EdgeDet == IOC_FALLING_EDGE) || + (ui32EdgeDet == IOC_RISING_EDGE) || + (ui32EdgeDet == IOC_BOTH_EDGES)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_EDGE_IRQ_EN | IOC_IOCFG0_EDGE_DET_M); + HWREG(ui32IOReg) = ui32Config | ((ui32Int ? IOC_IOCFG0_EDGE_IRQ_EN : 0) | ui32EdgeDet); +} + +//***************************************************************************** +// +// Set the pull on an IO port +// +//***************************************************************************** +void +IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the argument. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Pull == IOC_NO_IOPULL) || + (ui32Pull == IOC_IOPULL_UP) || + (ui32Pull == IOC_IOPULL_DOWN)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PULL_CTL_M; + HWREG(ui32IOReg) = ui32Config | ui32Pull; +} + +//***************************************************************************** +// +// Configure hysteresis on and IO port +// +//***************************************************************************** +void +IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Hysteresis == IOC_HYST_ENABLE) || + (ui32Hysteresis == IOC_HYST_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_HYST_EN; + HWREG(ui32IOReg) = ui32Config | ui32Hysteresis; +} + +//***************************************************************************** +// +// Enable/disable IO port as input +// +//***************************************************************************** +void +IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Input == IOC_INPUT_ENABLE) || + (ui32Input == IOC_INPUT_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_IE; + HWREG(ui32IOReg) = ui32Config | ui32Input; +} + +//***************************************************************************** +// +// Enable/disable the slew control on an IO port +// +//***************************************************************************** +void +IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32SlewEnable == IOC_SLEW_ENABLE) || + (ui32SlewEnable == IOC_SLEW_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_SLEW_RED; + HWREG(ui32IOReg) = ui32Config | ui32SlewEnable; +} + +//***************************************************************************** +// +// Configure the drive strength and maximum current of an IO port +// +//***************************************************************************** +void +IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, + uint32_t ui32DrvStrength) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOCurrent == IOC_CURRENT_2MA) || + (ui32IOCurrent == IOC_CURRENT_4MA) || + (ui32IOCurrent == IOC_CURRENT_8MA)); + ASSERT((ui32DrvStrength == IOC_STRENGTH_MIN) || + (ui32DrvStrength == IOC_STRENGTH_MAX) || + (ui32DrvStrength == IOC_STRENGTH_MED) || + (ui32DrvStrength == IOC_STRENGTH_AUTO)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_IOCURR_M | IOC_IOCFG0_IOSTR_M); + HWREG(ui32IOReg) = ui32Config | (ui32IOCurrent | ui32DrvStrength); +} + +//***************************************************************************** +// +// Setup the Port ID for this IO +// +//***************************************************************************** +void +IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PORT_ID_M; + HWREG(ui32IOReg) = ui32Config | ui32PortId; +} + +//***************************************************************************** +// +// Enables individual IO edge detect interrupt +// +//***************************************************************************** +void +IOCIntEnable(uint32_t ui32IOId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Enable the specified interrupt. + ui32Config = HWREG(ui32IOReg); + ui32Config |= IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} + +//***************************************************************************** +// +// Disables individual IO edge interrupt sources +// +//***************************************************************************** +void +IOCIntDisable(uint32_t ui32IOId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Disable the specified interrupt. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} + +//***************************************************************************** +// +// Setup an IO for standard GPIO input +// +//***************************************************************************** +void +IOCPinTypeGpioInput(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Setup the IO for standard input. + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_INPUT); + + // Enable input mode in the GPIO module. + GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_DISABLE); +} + +//***************************************************************************** +// +// Setup an IO for standard GPIO output +// +//***************************************************************************** +void +IOCPinTypeGpioOutput(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Setup the IO for standard input. + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_OUTPUT); + + // Enable output mode in the GPIO module. + GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_ENABLE); +} + +//***************************************************************************** +// +// Configure a set of IOs for standard UART peripheral control +// +//***************************************************************************** +void +IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, + uint32_t ui32Cts, uint32_t ui32Rts) +{ + // Check the arguments. + ASSERT(ui32Base == UART0_BASE); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Cts <= IOID_31) || (ui32Cts == IOID_UNUSED)); + ASSERT((ui32Rts <= IOID_31) || (ui32Rts == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_UART0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_UART0_TX, IOC_STD_OUTPUT); + } + if(ui32Cts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Cts, IOC_PORT_MCU_UART0_CTS, IOC_STD_INPUT); + } + if(ui32Rts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rts, IOC_PORT_MCU_UART0_RTS, IOC_STD_OUTPUT); + } +} + +//***************************************************************************** +// +// Configure a set of IOs for standard SSI peripheral master control +// +//***************************************************************************** +void +IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // Check the arguments. + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_OUTPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_OUTPUT); + } + } +} + +//***************************************************************************** +// +// Configure a set of IOs for standard SSI peripheral slave control +// +//***************************************************************************** +void +IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // Check the arguments. + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_INPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_INPUT); + } + } +} + +//***************************************************************************** +// +// Configure a set of IOs for standard I2C peripheral control +// +//***************************************************************************** +void +IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk) +{ + uint32_t ui32IOConfig; + + // Check the arguments. + ASSERT((ui32Data <= IOID_31) || (ui32Data == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Define the IO configuration parameters. + ui32IOConfig = IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_IOPULL_UP | + IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | + IOC_INT_DISABLE | IOC_IOMODE_OPEN_DRAIN_NORMAL | + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE; + + // Setup the IOs in the desired configuration. + IOCPortConfigureSet(ui32Data, IOC_PORT_MCU_I2C_MSSDA, ui32IOConfig); + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_I2C_MSSCL, ui32IOConfig); +} + + +//***************************************************************************** +// +// Configure an IO for AUX control +// +//***************************************************************************** +void +IOCPinTypeAux(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT((ui32IOId <= IOID_31) || (ui32IOId == IOID_UNUSED)); + + // Setup the IO. + IOCPortConfigureSet(ui32IOId, IOC_PORT_AUX_IO, IOC_STD_INPUT); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc.h new file mode 100644 index 0000000..1b852a8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc.h @@ -0,0 +1,1154 @@ +/****************************************************************************** +* Filename: ioc.h +* Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) +* Revision: 50156 +* +* Description: Defines and prototypes for the IO Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup ioc_api +//! @{ +// +//***************************************************************************** + +#ifndef __IOC_H__ +#define __IOC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ioc.h" +#include "../inc/hw_ints.h" +#include "interrupt.h" +#include "debug.h" +#include "gpio.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define IOCPortConfigureSet NOROM_IOCPortConfigureSet + #define IOCPortConfigureGet NOROM_IOCPortConfigureGet + #define IOCIOShutdownSet NOROM_IOCIOShutdownSet + #define IOCIOModeSet NOROM_IOCIOModeSet + #define IOCIOIntSet NOROM_IOCIOIntSet + #define IOCIOPortPullSet NOROM_IOCIOPortPullSet + #define IOCIOHystSet NOROM_IOCIOHystSet + #define IOCIOInputSet NOROM_IOCIOInputSet + #define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet + #define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet + #define IOCIOPortIdSet NOROM_IOCIOPortIdSet + #define IOCIntEnable NOROM_IOCIntEnable + #define IOCIntDisable NOROM_IOCIntDisable + #define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput + #define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput + #define IOCPinTypeUart NOROM_IOCPinTypeUart + #define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster + #define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave + #define IOCPinTypeI2c NOROM_IOCPinTypeI2c + #define IOCPinTypeAux NOROM_IOCPinTypeAux +#endif + +//***************************************************************************** +// +// Number of IOs (max. total of 32) +// +//***************************************************************************** +#define NUM_IO_MAX 32 + +//***************************************************************************** +// +// The following fields are IO Id for the IOC module +// +//***************************************************************************** +#define IOID_0 0x00000000 // IO Id 0 +#define IOID_1 0x00000001 // IO Id 1 +#define IOID_2 0x00000002 // IO Id 2 +#define IOID_3 0x00000003 // IO Id 3 +#define IOID_4 0x00000004 // IO Id 4 +#define IOID_5 0x00000005 // IO Id 5 +#define IOID_6 0x00000006 // IO Id 6 +#define IOID_7 0x00000007 // IO Id 7 +#define IOID_8 0x00000008 // IO Id 8 +#define IOID_9 0x00000009 // IO Id 9 +#define IOID_10 0x0000000A // IO Id 10 +#define IOID_11 0x0000000B // IO Id 11 +#define IOID_12 0x0000000C // IO Id 12 +#define IOID_13 0x0000000D // IO Id 13 +#define IOID_14 0x0000000E // IO Id 14 +#define IOID_15 0x0000000F // IO Id 15 +#define IOID_16 0x00000010 // IO Id 16 +#define IOID_17 0x00000011 // IO Id 17 +#define IOID_18 0x00000012 // IO Id 18 +#define IOID_19 0x00000013 // IO Id 19 +#define IOID_20 0x00000014 // IO Id 20 +#define IOID_21 0x00000015 // IO Id 21 +#define IOID_22 0x00000016 // IO Id 22 +#define IOID_23 0x00000017 // IO Id 23 +#define IOID_24 0x00000018 // IO Id 24 +#define IOID_25 0x00000019 // IO Id 25 +#define IOID_26 0x0000001A // IO Id 26 +#define IOID_27 0x0000001B // IO Id 27 +#define IOID_28 0x0000001C // IO Id 28 +#define IOID_29 0x0000001D // IO Id 29 +#define IOID_30 0x0000001E // IO Id 30 +#define IOID_31 0x0000001F // IO Id 31 +#define IOID_UNUSED 0xFFFFFFFF // Unused IO Id + +#define IOC_IOID_MASK 0x000000FF // IOC IO Id bit mask + +//***************************************************************************** +// +// Number of IO ports +// +//***************************************************************************** +#define NUM_IO_PORTS 56 + +//***************************************************************************** +// +// IOC Peripheral Port Mapping +// +//***************************************************************************** +#define IOC_PORT_GPIO 0x00000000 // Default general purpose IO usage +#define IOC_PORT_AON_CLK32K 0x00000007 // AON External 32kHz clock +#define IOC_PORT_AUX_IO 0x00000008 // AUX IO Pin +#define IOC_PORT_MCU_SSI0_RX 0x00000009 // MCU SSI0 Receive Pin +#define IOC_PORT_MCU_SSI0_TX 0x0000000A // MCU SSI0 Transmit Pin +#define IOC_PORT_MCU_SSI0_FSS 0x0000000B // MCU SSI0 FSS Pin +#define IOC_PORT_MCU_SSI0_CLK 0x0000000C // MCU SSI0 Clock Pin +#define IOC_PORT_MCU_I2C_MSSDA 0x0000000D // MCU I2C Data Pin +#define IOC_PORT_MCU_I2C_MSSCL 0x0000000E // MCU I2C Clock Pin +#define IOC_PORT_MCU_UART0_RX 0x0000000F // MCU UART0 Receive Pin +#define IOC_PORT_MCU_UART0_TX 0x00000010 // MCU UART0 Transmit Pin +#define IOC_PORT_MCU_UART0_CTS 0x00000011 // MCU UART0 Clear To Send Pin +#define IOC_PORT_MCU_UART0_RTS 0x00000012 // MCU UART0 Request To Send Pin +#define IOC_PORT_MCU_PORT_EVENT0 0x00000017 // MCU PORT EVENT 0 +#define IOC_PORT_MCU_PORT_EVENT1 0x00000018 // MCU PORT EVENT 1 +#define IOC_PORT_MCU_PORT_EVENT2 0x00000019 // MCU PORT EVENT 2 +#define IOC_PORT_MCU_PORT_EVENT3 0x0000001A // MCU PORT EVENT 3 +#define IOC_PORT_MCU_PORT_EVENT4 0x0000001B // MCU PORT EVENT 4 +#define IOC_PORT_MCU_PORT_EVENT5 0x0000001C // MCU PORT EVENT 5 +#define IOC_PORT_MCU_PORT_EVENT6 0x0000001D // MCU PORT EVENT 6 +#define IOC_PORT_MCU_PORT_EVENT7 0x0000001E // MCU PORT EVENT 7 +#define IOC_PORT_MCU_SWV 0x00000020 // Serial Wire Viewer +#define IOC_PORT_MCU_SSI1_RX 0x00000021 // MCU SSI1 Receive Pin +#define IOC_PORT_MCU_SSI1_TX 0x00000022 // MCU SSI1 Transmit Pin +#define IOC_PORT_MCU_SSI1_FSS 0x00000023 // MCU SSI1 FSS Pin +#define IOC_PORT_MCU_SSI1_CLK 0x00000024 // MCU SSI1 Clock Pin +#define IOC_PORT_MCU_I2S_AD0 0x00000025 // MCU I2S Data Pin 0 +#define IOC_PORT_MCU_I2S_AD1 0x00000026 // MCU I2S Data Pin 1 +#define IOC_PORT_MCU_I2S_WCLK 0x00000027 // MCU I2S Frame/Word Clock +#define IOC_PORT_MCU_I2S_BCLK 0x00000028 // MCU I2S Bit Clock +#define IOC_PORT_MCU_I2S_MCLK 0x00000029 // MCU I2S Master clock 2 +#define IOC_PORT_RFC_TRC 0x0000002E // RF Core Tracer +#define IOC_PORT_RFC_GPO0 0x0000002F // RC Core Data Out Pin 0 +#define IOC_PORT_RFC_GPO1 0x00000030 // RC Core Data Out Pin 1 +#define IOC_PORT_RFC_GPO2 0x00000031 // RC Core Data Out Pin 2 +#define IOC_PORT_RFC_GPO3 0x00000032 // RC Core Data Out Pin 3 +#define IOC_PORT_RFC_GPI0 0x00000033 // RC Core Data In Pin 0 +#define IOC_PORT_RFC_GPI1 0x00000034 // RC Core Data In Pin 1 +#define IOC_PORT_RFC_SMI_DL_OUT 0x00000035 // RF Core SMI Data Link Out +#define IOC_PORT_RFC_SMI_DL_IN 0x00000036 // RF Core SMI Data Link in +#define IOC_PORT_RFC_SMI_CL_OUT 0x00000037 // RF Core SMI Command Link Out +#define IOC_PORT_RFC_SMI_CL_IN 0x00000038 // RF Core SMI Command Link In + +//***************************************************************************** +// +// Defines for enabling/disabling an IO +// +//***************************************************************************** +#define IOC_SLEW_ENABLE 0x00001000 +#define IOC_SLEW_DISABLE 0x00000000 +#define IOC_INPUT_ENABLE 0x20000000 +#define IOC_INPUT_DISABLE 0x00000000 +#define IOC_HYST_ENABLE 0x40000000 +#define IOC_HYST_DISABLE 0x00000000 + +//***************************************************************************** +// +// Defines that can be used to set the shutdown mode of an IO +// +//***************************************************************************** +#define IOC_NO_WAKE_UP 0x00000000 +#define IOC_WAKE_ON_LOW 0x10000000 +#define IOC_WAKE_ON_HIGH 0x18000000 + +//***************************************************************************** +// +// Defines that can be used to set the IO Mode of an IO +// +//***************************************************************************** +#define IOC_IOMODE_NORMAL 0x00000000 // Normal Input/Output +#define IOC_IOMODE_INV 0x01000000 // Inverted Input/Output +#define IOC_IOMODE_OPEN_DRAIN_NORMAL \ + 0x04000000 // Open Drain, Normal Input/Output +#define IOC_IOMODE_OPEN_DRAIN_INV \ + 0x05000000 // Open Drain, Inverted + // Input/Output +#define IOC_IOMODE_OPEN_SRC_NORMAL \ + 0x06000000 // Open Source, Normal Input/Output +#define IOC_IOMODE_OPEN_SRC_INV \ + 0x07000000 // Open Source, Inverted + // Input/Output + +//***************************************************************************** +// +// Defines that can be used to set the edge detection on an IO +// +//***************************************************************************** +#define IOC_NO_EDGE 0x00000000 // No edge detection +#define IOC_FALLING_EDGE 0x00010000 // Edge detection on falling edge +#define IOC_RISING_EDGE 0x00020000 // Edge detection on rising edge +#define IOC_BOTH_EDGES 0x00030000 // Edge detection on both edges +#define IOC_INT_ENABLE 0x00040000 // Enable interrupt on edge detect +#define IOC_INT_DISABLE 0x00000000 // Disable interrupt on edge detect +#define IOC_INT_M 0x00070000 // Int config mask + +//***************************************************************************** +// +// Defines that be used to set pull on an IO +// +//***************************************************************************** +#define IOC_NO_IOPULL 0x00006000 // No IO pull +#define IOC_IOPULL_UP 0x00004000 // Pull up +#define IOC_IOPULL_DOWN 0x00002000 // Pull down +#define IOC_IOPULL_M 0x00006000 // Pull config mask +#define IOC_IOPULL_M 0x00006000 + +//***************************************************************************** +// +// Defines that can be used to select the drive strength of an IO +// +//***************************************************************************** +#define IOC_CURRENT_2MA 0x00000000 // 2mA drive strength +#define IOC_CURRENT_4MA 0x00000400 // 4mA drive strength +#define IOC_CURRENT_8MA 0x00000800 // 4 or 8mA drive strength + +#define IOC_STRENGTH_AUTO 0x00000000 // Automatic Drive Strength + // (2/4/8 mA @ VVDS) +#define IOC_STRENGTH_MAX 0x00000300 // Maximum Drive Strength + // (2/4/8 mA @ 1.8V) +#define IOC_STRENGTH_MED 0x00000200 // Medium Drive Strength + // (2/4/8 mA @ 2.5V) +#define IOC_STRENGTH_MIN 0x00000100 // Minimum Drive Strength + // (2/4/8 mA @ 3.3V) + +//***************************************************************************** +// +// Defines for standard IO setup +// +//***************************************************************************** +#define IOC_STD_INPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE ) +#define IOC_STD_OUTPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_DISABLE ) + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Set the configuration of an IO port. +//! +//! This function is used to configure the functionality of an IO. +//! +//! The \c ui32IOId parameter specifies which IO to configure. +//! +//! The \c ui32PortId parameter specifies which functional peripheral to hook +//! up to this IO. +//! +//! The \c ui32IOConfig parameter consists of a bitwise OR'ed value of all +//! the available configuration modes +//! +//! \note All IO Ports are tied to a specific functionality in a sub module +//! except for the \ref IOC_PORT_AUX_IO. Each of the IOs in the AUX domain are +//! hardcoded to a specific IO. When enabling one or more pins for the AUX +//! domain, they should all be configured to using \ref IOC_PORT_AUX_IO. +//! +//! \param ui32IOId defines the IO to configure and must be one of the following: +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32PortId selects the functional IO port to connect. +//! The available IO ports are: +//! - \ref IOC_PORT_GPIO +//! - \ref IOC_PORT_AON_CLK32K +//! - \ref IOC_PORT_AUX_IO +//! - \ref IOC_PORT_MCU_SSI0_RX +//! - \ref IOC_PORT_MCU_SSI0_TX +//! - \ref IOC_PORT_MCU_SSI0_FSS +//! - \ref IOC_PORT_MCU_SSI0_CLK +//! - \ref IOC_PORT_MCU_I2C_MSSDA +//! - \ref IOC_PORT_MCU_I2C_MSSCL +//! - \ref IOC_PORT_MCU_UART0_RX +//! - \ref IOC_PORT_MCU_UART0_TX +//! - \ref IOC_PORT_MCU_UART0_CTS +//! - \ref IOC_PORT_MCU_UART0_RTS +//! - \ref IOC_PORT_MCU_PORT_EVENT0 +//! - \ref IOC_PORT_MCU_PORT_EVENT1 +//! - \ref IOC_PORT_MCU_PORT_EVENT2 +//! - \ref IOC_PORT_MCU_PORT_EVENT3 +//! - \ref IOC_PORT_MCU_PORT_EVENT4 +//! - \ref IOC_PORT_MCU_PORT_EVENT5 +//! - \ref IOC_PORT_MCU_PORT_EVENT6 +//! - \ref IOC_PORT_MCU_PORT_EVENT7 +//! - \ref IOC_PORT_MCU_SWV +//! - \ref IOC_PORT_MCU_SSI1_RX +//! - \ref IOC_PORT_MCU_SSI1_TX +//! - \ref IOC_PORT_MCU_SSI1_FSS +//! - \ref IOC_PORT_MCU_SSI1_CLK +//! - \ref IOC_PORT_MCU_I2S_AD0 +//! - \ref IOC_PORT_MCU_I2S_AD1 +//! - \ref IOC_PORT_MCU_I2S_WCLK +//! - \ref IOC_PORT_MCU_I2S_BCLK +//! - \ref IOC_PORT_MCU_I2S_MCLK +//! - \ref IOC_PORT_RFC_TRC +//! - \ref IOC_PORT_RFC_GPO0 +//! - \ref IOC_PORT_RFC_GPO1 +//! - \ref IOC_PORT_RFC_GPO2 +//! - \ref IOC_PORT_RFC_GPO3 +//! - \ref IOC_PORT_RFC_GPI0 +//! - \ref IOC_PORT_RFC_GPI1 +//! \param ui32IOConfig is the IO configuration consisting of +//! the bitwise OR of all configuration modes: +//! - Input/output mode: +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_IOMODE_INV +//! - \ref IOC_IOMODE_OPEN_DRAIN_NORMAL +//! - \ref IOC_IOMODE_OPEN_DRAIN_INV +//! - \ref IOC_IOMODE_OPEN_SRC_NORMAL +//! - \ref IOC_IOMODE_OPEN_SRC_INV +//! - Wake-up mode (from shutdown): +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_WAKE_ON_LOW +//! - \ref IOC_WAKE_ON_HIGH +//! - Edge detection mode: +//! - \ref IOC_NO_EDGE +//! - \ref IOC_FALLING_EDGE +//! - \ref IOC_RISING_EDGE +//! - \ref IOC_BOTH_EDGES +//! - Interrupt mode on edge detection: +//! - \ref IOC_INT_ENABLE +//! - \ref IOC_INT_DISABLE +//! - Pull mode: +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_IOPULL_UP +//! - \ref IOC_IOPULL_DOWN +//! - Input mode: +//! - \ref IOC_INPUT_ENABLE +//! - \ref IOC_INPUT_DISABLE +//! - Hysteresis mode: +//! - \ref IOC_HYST_ENABLE +//! - \ref IOC_HYST_DISABLE +//! - Slew rate reduction mode: +//! - \ref IOC_SLEW_ENABLE +//! - \ref IOC_SLEW_DISABLE +//! - Current mode (see \ref IOCIODrvStrengthSet() for more details): +//! - \ref IOC_CURRENT_2MA : Low-Current mode. Min 2 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_4MA : High-Current mode. Min 4 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_8MA : Extended-Current mode. Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - Drive strength mode: +//! - \ref IOC_STRENGTH_AUTO : Automatic drive strength based on battery voltage. +//! - \ref IOC_STRENGTH_MAX : Maximum drive strength, used for low supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MED : Medium drive strength, used for medium supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MIN : Minimum drive strength, used for high supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! +//! \return None +// +//***************************************************************************** +extern void IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, + uint32_t ui32IOConfig); + +//***************************************************************************** +// +//! \brief Get the configuration of an IO port. +//! +//! This function is used for getting the configuration of an IO. +//! +//! Each IO port has a dedicated register for setting up the IO. This function +//! returns the current configuration for the given IO. +//! +//! \param ui32IOId selects the IO to return the configuration for. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return Returns the IO Port configuration. +//! See \ref IOCPortConfigureSet() for configuration options. +// +//***************************************************************************** +extern uint32_t IOCPortConfigureGet(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Set wake-up mode from shutdown on an IO port. +//! +//! This function is used to set the wake-up mode from shutdown of an IO. +//! +//! IO must be configured as input in order for wakeup to work. See \ref IOCIOInputSet(). +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32IOShutdown enables wake-up from shutdown on LOW/HIGH by this IO port. +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_WAKE_ON_LOW +//! - \ref IOC_WAKE_ON_HIGH +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown); + + +//***************************************************************************** +// +//! \brief Set the IO Mode of an IO Port. +//! +//! This function is used to set the input/output mode of an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32IOMode sets the port IO Mode. +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_IOMODE_INV +//! - \ref IOC_IOMODE_OPEN_DRAIN_NORMAL +//! - \ref IOC_IOMODE_OPEN_DRAIN_INV +//! - \ref IOC_IOMODE_OPEN_SRC_NORMAL +//! - \ref IOC_IOMODE_OPEN_SRC_INV +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode); + +//***************************************************************************** +// +//! \brief Setup edge detection and interrupt generation on an IO Port. +//! +//! This function is used to setup the edge detection and interrupt generation on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Int enables/disables interrupt generation on this IO port. +//! - \ref IOC_INT_ENABLE +//! - \ref IOC_INT_DISABLE +//! \param ui32EdgeDet enables/disables edge detection events on this IO port. +//! - \ref IOC_NO_EDGE +//! - \ref IOC_FALLING_EDGE +//! - \ref IOC_RISING_EDGE +//! - \ref IOC_BOTH_EDGES +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, + uint32_t ui32EdgeDet); + +//***************************************************************************** +// +//! \brief Set the pull on an IO port. +//! +//! This function is used to configure the pull on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Pull enables/disables pull on this IO port. +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_IOPULL_UP +//! - \ref IOC_IOPULL_DOWN +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull); + +//***************************************************************************** +// +//! \brief Configure hysteresis on and IO port. +//! +//! This function is used to enable/disable hysteresis on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Hysteresis enable/disable input hysteresis on IO. +//! - \ref IOC_HYST_ENABLE +//! - \ref IOC_HYST_DISABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis); + +//***************************************************************************** +// +//! \brief Enable/disable IO port as input. +//! +//! This function is used to enable/disable input on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Input enable/disable input on IO. +//! - \ref IOC_INPUT_ENABLE +//! - \ref IOC_INPUT_DISABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input); + +//***************************************************************************** +// +//! \brief Configure slew rate on an IO port. +//! +//! This function is used to enable/disable reduced slew rate on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32SlewEnable enables/disables reduced slew rate on an output. +//! - \ref IOC_SLEW_ENABLE +//! - \ref IOC_SLEW_DISABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable); + +//***************************************************************************** +// +//! \brief Configure the drive strength source and current mode of an IO port. +//! +//! The drive strength of an IO is configured by a combination of multiple settings +//! in several modules. The drive strength source \ti_code{ui32DrvStrength} is used for controlling +//! drive strength at different supply levels. When set to AUTO the battery monitor +//! (BATMON) adjusts the drive strength to compensate for changes in supply voltage +//! in order to keep IO current constant. Alternatively, drive strength source can +//! be controlled manually by selecting one of three options each of which is configurable +//! in the AON IOC by \ref AONIOCDriveStrengthSet(). +//! +//! Each drive strength source has three current modes: Low-Current (LC), High-Current (HC), and +//! Extended-Current (EC), and typically drive strength doubles when selecting a higher mode. +//! I.e. EC = 2 x HC = 4 x LC. +//! +//! \note Not all IOs support Extended-Current mode. See datasheet for more information +//! on the specific device. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32IOCurrent selects the IO current mode. +//! - \ref IOC_CURRENT_2MA : Low-Current mode. Min 2 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_4MA : High-Current mode. Min 4 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_8MA : Extended-Current mode. Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! \param ui32DrvStrength sets the source for drive strength control of the IO port. +//! - \ref IOC_STRENGTH_AUTO : Automatic drive strength based on battery voltage. +//! - \ref IOC_STRENGTH_MAX : Maximum drive strength, used for low supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MED : Medium drive strength, used for medium supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MIN : Minimum drive strength, used for high supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! +//! \return None +// +//***************************************************************************** +extern void IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, + uint32_t ui32DrvStrength); + +//***************************************************************************** +// +//! \brief Setup the Port ID for this IO. +//! +//! The \c ui32PortId specifies which functional peripheral to hook up to this +//! IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32PortId selects the port to map to the IO. +//! - \ref IOC_PORT_GPIO +//! - \ref IOC_PORT_AON_CLK32K +//! - \ref IOC_PORT_AUX_IO +//! - \ref IOC_PORT_MCU_SSI0_RX +//! - \ref IOC_PORT_MCU_SSI0_TX +//! - \ref IOC_PORT_MCU_SSI0_FSS +//! - \ref IOC_PORT_MCU_SSI0_CLK +//! - \ref IOC_PORT_MCU_I2C_MSSDA +//! - \ref IOC_PORT_MCU_I2C_MSSCL +//! - \ref IOC_PORT_MCU_UART0_RX +//! - \ref IOC_PORT_MCU_UART0_TX +//! - \ref IOC_PORT_MCU_UART0_CTS +//! - \ref IOC_PORT_MCU_UART0_RTS +//! - \ref IOC_PORT_MCU_PORT_EVENT0 +//! - \ref IOC_PORT_MCU_PORT_EVENT1 +//! - \ref IOC_PORT_MCU_PORT_EVENT2 +//! - \ref IOC_PORT_MCU_PORT_EVENT3 +//! - \ref IOC_PORT_MCU_PORT_EVENT4 +//! - \ref IOC_PORT_MCU_PORT_EVENT5 +//! - \ref IOC_PORT_MCU_PORT_EVENT6 +//! - \ref IOC_PORT_MCU_PORT_EVENT7 +//! - \ref IOC_PORT_MCU_SWV +//! - \ref IOC_PORT_MCU_SSI1_RX +//! - \ref IOC_PORT_MCU_SSI1_TX +//! - \ref IOC_PORT_MCU_SSI1_FSS +//! - \ref IOC_PORT_MCU_SSI1_CLK +//! - \ref IOC_PORT_MCU_I2S_AD0 +//! - \ref IOC_PORT_MCU_I2S_AD1 +//! - \ref IOC_PORT_MCU_I2S_WCLK +//! - \ref IOC_PORT_MCU_I2S_BCLK +//! - \ref IOC_PORT_MCU_I2S_MCLK +//! - \ref IOC_PORT_RFC_TRC +//! - \ref IOC_PORT_RFC_GPO0 +//! - \ref IOC_PORT_RFC_GPO1 +//! - \ref IOC_PORT_RFC_GPO2 +//! - \ref IOC_PORT_RFC_GPO3 +//! - \ref IOC_PORT_RFC_GPI0 +//! - \ref IOC_PORT_RFC_GPI1 +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId); + +//***************************************************************************** +// +//! \brief Register an interrupt handler for an IO edge interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific IO interrupts must be enabled via \ref IOCIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! IOC interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +IOCIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_AON_GPIO_EDGE, pfnHandler); + + // Enable the IO edge interrupt. + IntEnable(INT_AON_GPIO_EDGE); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a IO edge interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when an IO edge interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +IOCIntUnregister(void) +{ + // Disable the interrupts. + IntDisable(INT_AON_GPIO_EDGE); + + // Unregister the interrupt handler. + IntUnregister(INT_AON_GPIO_EDGE); +} + +//***************************************************************************** +// +//! \brief Enables individual IO edge detect interrupt. +//! +//! This function enables the indicated IO edge interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IOId is the IO to enable edge detect interrupt for. +//! +//! \return None +// +//***************************************************************************** +extern void IOCIntEnable(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Disables individual IO edge interrupt sources. +//! +//! This function disables the indicated IO edge interrupt source. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IOId is the IO edge interrupt source to be disabled. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +extern void IOCIntDisable(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Clears the IO edge interrupt source. +//! +//! The specified IO edge interrupt source is cleared, so that it no longer +//! asserts. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IOId is the IO causing the interrupt. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +IOCIntClear(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Clear the requested interrupt source by clearing the event. + GPIO_clearEventDio(ui32IOId); +} + +//***************************************************************************** +// +//! \brief Returns the status of the IO interrupts. +//! +//! \param ui32IOId is the IO to get the status for. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE uint32_t +IOCIntStatus(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the event status. + return (GPIO_getEventDio(ui32IOId)); +} + + +//***************************************************************************** +// +//! \brief Setup an IO for standard GPIO input. +//! +//! Setup an IO for standard GPIO input with the following configuration: +//! - Port ID: +//! - \ref IOC_PORT_GPIO +//! - Configuration: +//! - \ref IOC_CURRENT_2MA +//! - \ref IOC_STRENGTH_AUTO +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_SLEW_DISABLE +//! - \ref IOC_HYST_DISABLE +//! - \ref IOC_NO_EDGE +//! - \ref IOC_INT_DISABLE +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_INPUT_ENABLE +//! +//! \param ui32IOId is the IO to setup for GPIO input +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeGpioInput(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Setup an IO for standard GPIO output. +//! +//! Setup an IO for standard GPIO output with the following configuration: +//! - Port ID: +//! - \ref IOC_PORT_GPIO +//! - Configuration: +//! - \ref IOC_CURRENT_2MA +//! - \ref IOC_STRENGTH_AUTO +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_SLEW_DISABLE +//! - \ref IOC_HYST_DISABLE +//! - \ref IOC_NO_EDGE +//! - \ref IOC_INT_DISABLE +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_INPUT_DISABLE +//! +//! \param ui32IOId is the IO to setup for GPIO output +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeGpioOutput(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard UART peripheral control. +//! +//! The UART pins must be properly configured for the UART peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s). Other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! \note If a UART pin is not intended to be used, then the parameter in the +//! function should be \ref IOID_UNUSED. +//! +//! \param ui32Base is the base address of the UART module. +//! \param ui32Rx is the IO Id of the IO to use as UART Receive. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Tx is the IO Id of the IO to use as UART Transmit. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Cts is the IO Id of the IO to use for UART Clear to send. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Rts is the IO Id of the IO to use for UART Request to send. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Cts, + uint32_t ui32Rts); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard SSI peripheral master control. +//! +//! \param ui32Base is the base address of the SSI module to connect to the IOs +//! \param ui32Rx is the IO to connect to the SSI MISO line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Tx is the IO to connect to the SSI MOSI line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Fss is the IO to connect to the SSI FSS line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Clk is the IO to connect to the SSI Clock output line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard SSI peripheral slave control. +//! +//! \param ui32Base is the base address of the SSI module to connect to the IOs +//! \param ui32Rx is the IO to connect to the SSI MOSI line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Tx is the IO to connect to the SSI MISO line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Fss is the IO to connect to the SSI FSS line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Clk is the IO to connect to the SSI Clock input line. +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard I2C peripheral control. +//! +//! \param ui32Base is the base address of the I2C module to connect to the IOs +//! \param ui32Data is the I2C data line +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Clk is the I2C input clock +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, + uint32_t ui32Clk); + + +//***************************************************************************** +// +//! \brief Configure an IO for AUX control. +//! +//! Use this function to enable AUX to control a specific IO. Please note, that +//! when using AUX to control the IO, the input/output control in the IOC is +//! bypassed and completely controlled by AUX, so enabling or disabling input +//! in the IOC has no effect. +//! +//! \note The IOs available for AUX control can vary from device to device. +//! +//! \param ui32IOId is the IO to setup for AUX usage. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeAux(uint32_t ui32IOId); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_IOCPortConfigureSet + #undef IOCPortConfigureSet + #define IOCPortConfigureSet ROM_IOCPortConfigureSet + #endif + #ifdef ROM_IOCPortConfigureGet + #undef IOCPortConfigureGet + #define IOCPortConfigureGet ROM_IOCPortConfigureGet + #endif + #ifdef ROM_IOCIOShutdownSet + #undef IOCIOShutdownSet + #define IOCIOShutdownSet ROM_IOCIOShutdownSet + #endif + #ifdef ROM_IOCIOModeSet + #undef IOCIOModeSet + #define IOCIOModeSet ROM_IOCIOModeSet + #endif + #ifdef ROM_IOCIOIntSet + #undef IOCIOIntSet + #define IOCIOIntSet ROM_IOCIOIntSet + #endif + #ifdef ROM_IOCIOPortPullSet + #undef IOCIOPortPullSet + #define IOCIOPortPullSet ROM_IOCIOPortPullSet + #endif + #ifdef ROM_IOCIOHystSet + #undef IOCIOHystSet + #define IOCIOHystSet ROM_IOCIOHystSet + #endif + #ifdef ROM_IOCIOInputSet + #undef IOCIOInputSet + #define IOCIOInputSet ROM_IOCIOInputSet + #endif + #ifdef ROM_IOCIOSlewCtrlSet + #undef IOCIOSlewCtrlSet + #define IOCIOSlewCtrlSet ROM_IOCIOSlewCtrlSet + #endif + #ifdef ROM_IOCIODrvStrengthSet + #undef IOCIODrvStrengthSet + #define IOCIODrvStrengthSet ROM_IOCIODrvStrengthSet + #endif + #ifdef ROM_IOCIOPortIdSet + #undef IOCIOPortIdSet + #define IOCIOPortIdSet ROM_IOCIOPortIdSet + #endif + #ifdef ROM_IOCIntEnable + #undef IOCIntEnable + #define IOCIntEnable ROM_IOCIntEnable + #endif + #ifdef ROM_IOCIntDisable + #undef IOCIntDisable + #define IOCIntDisable ROM_IOCIntDisable + #endif + #ifdef ROM_IOCPinTypeGpioInput + #undef IOCPinTypeGpioInput + #define IOCPinTypeGpioInput ROM_IOCPinTypeGpioInput + #endif + #ifdef ROM_IOCPinTypeGpioOutput + #undef IOCPinTypeGpioOutput + #define IOCPinTypeGpioOutput ROM_IOCPinTypeGpioOutput + #endif + #ifdef ROM_IOCPinTypeUart + #undef IOCPinTypeUart + #define IOCPinTypeUart ROM_IOCPinTypeUart + #endif + #ifdef ROM_IOCPinTypeSsiMaster + #undef IOCPinTypeSsiMaster + #define IOCPinTypeSsiMaster ROM_IOCPinTypeSsiMaster + #endif + #ifdef ROM_IOCPinTypeSsiSlave + #undef IOCPinTypeSsiSlave + #define IOCPinTypeSsiSlave ROM_IOCPinTypeSsiSlave + #endif + #ifdef ROM_IOCPinTypeI2c + #undef IOCPinTypeI2c + #define IOCPinTypeI2c ROM_IOCPinTypeI2c + #endif + #ifdef ROM_IOCPinTypeAux + #undef IOCPinTypeAux + #define IOCPinTypeAux ROM_IOCPinTypeAux + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __IOC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc_doc.h new file mode 100644 index 0000000..cd35eff --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc_doc.h @@ -0,0 +1,92 @@ +/****************************************************************************** +* Filename: ioc_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup ioc_api +//! @{ +//! \section sec_ioc Introduction +//! +//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO). +//! The IOC consists of two APIs: +//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it. +//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc. +//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is +//! routed to a DIO for external use. +//! +//! For more information on the AON IOC see the [AON IOC API](\ref aonioc_api). +//! +//! \note The output driver of a DIO is not configured by the IOC API (except for drive strength); instead, it is controlled by the +//! peripheral module which is selected to control the DIO. +//! +//! A DIO is considered "software controlled" if it is configured for GPIO control which allows the +//! System CPU to set the value of the DIO via the [GPIO API](\ref gpio_api). Alternatively, a DIO +//! can be "hardware controlled" if it is controlled by other modules than GPIO. +//! +//! \section sec_ioc_api API +//! +//! The API functions can be grouped like this: +//! +//! Configure all settings at the same time: +//! - \ref IOCPortConfigureSet() +//! - \ref IOCPortConfigureGet() +//! +//! Configure individual settings: +//! - \ref IOCIODrvStrengthSet() +//! - \ref IOCIOHystSet() +//! - \ref IOCIOInputSet() +//! - \ref IOCIOIntSet() +//! - \ref IOCIOModeSet() +//! - \ref IOCIOPortIdSet() +//! - \ref IOCIOPortPullSet() +//! - \ref IOCIOShutdownSet() +//! - \ref IOCIOSlewCtrlSet() +//! +//! Handle edge detection events: +//! - \ref IOCIntEnable() +//! - \ref IOCIntDisable() +//! - \ref IOCIntClear() +//! - \ref IOCIntStatus() +//! - \ref IOCIntRegister() +//! - \ref IOCIntUnregister() +//! +//! Configure IOCs for typical use cases (can also be used as example code): +//! - \ref IOCPinTypeAux() +//! - \ref IOCPinTypeGpioInput() +//! - \ref IOCPinTypeGpioOutput() +//! - \ref IOCPinTypeI2c() +//! - \ref IOCPinTypeSsiMaster() +//! - \ref IOCPinTypeSsiSlave() +//! - \ref IOCPinTypeUart() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/osc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/osc.c new file mode 100644 index 0000000..a695408 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/osc.c @@ -0,0 +1,468 @@ +/****************************************************************************** +* Filename: osc.c +* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) +* Revision: 54539 +* +* Description: Driver for setting up the system Oscillators +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_fcfg1.h" +#include "aon_batmon.h" +#include "aon_rtc.h" +#include "osc.h" +#include "setup_rom.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef OSCClockSourceSet + #define OSCClockSourceSet NOROM_OSCClockSourceSet + #undef OSCClockSourceGet + #define OSCClockSourceGet NOROM_OSCClockSourceGet + #undef OSCHF_GetStartupTime + #define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime + #undef OSCHF_TurnOnXosc + #define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc + #undef OSCHF_AttemptToSwitchToXosc + #define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc + #undef OSCHF_SwitchToRcOscTurnOffXosc + #define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc + #undef OSCHF_DebugGetCrystalAmplitude + #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude + #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude + #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #undef OSC_HPOSCRelativeFrequencyOffsetGet + #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet + #undef OSC_AdjustXoscHfCapArray + #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray + #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert +#endif + + +//***************************************************************************** +// +// OSCHF switch time calculator defines and globals +// +//***************************************************************************** + +#define RTC_CV_TO_MS(x) (( 1000 * ( x )) >> 16 ) +#define RTC_CV_TO_US(x) (( 1000000 * ( x )) >> 16 ) + +typedef struct { + uint32_t previousStartupTimeInUs ; + uint32_t timeXoscOff_CV ; + uint32_t timeXoscOn_CV ; + uint32_t timeXoscStable_CV ; + int32_t tempXoscOff ; +} OscHfGlobals_t; + +static OscHfGlobals_t oscHfGlobals; + +//***************************************************************************** +// +// Configure the oscillator input to the a source clock. +// +//***************************************************************************** +void +OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc) +{ + // Check the arguments. + ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || + (ui32SrcClk & OSC_SRC_CLK_MF) || + (ui32SrcClk & OSC_SRC_CLK_HF)); + ASSERT((ui32Osc == OSC_RCOSC_HF) || + (ui32Osc == OSC_RCOSC_LF) || + (ui32Osc == OSC_XOSC_HF) || + (ui32Osc == OSC_XOSC_LF)); + + // Request the high frequency source clock (using 24 MHz XTAL) + if(ui32SrcClk & OSC_SRC_CLK_HF) + { + // Enable the HF XTAL as HF clock source + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S, + ui32Osc); + } + + // Configure the medium frequency source clock + if(ui32SrcClk & OSC_SRC_CLK_MF) + { + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_S, + ui32Osc); + } + + // Configure the low frequency source clock. + if(ui32SrcClk & OSC_SRC_CLK_LF) + { + // Change the clock source. + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S, + ui32Osc); + } +} + +//***************************************************************************** +// +// Get the source clock settings +// +//***************************************************************************** +uint32_t +OSCClockSourceGet(uint32_t ui32SrcClk) +{ + uint32_t ui32ClockSource; + + // Check the arguments. + ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || + (ui32SrcClk & OSC_SRC_CLK_HF)); + + // Return the source for the selected clock. + if(ui32SrcClk == OSC_SRC_CLK_LF) + { + ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_SCLK_LF_SRC_M, + DDI_0_OSC_STAT0_SCLK_LF_SRC_S); + } + else + { + ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_SCLK_HF_SRC_M, + DDI_0_OSC_STAT0_SCLK_HF_SRC_S); + } + return (ui32ClockSource); +} + +//***************************************************************************** +// +// Returns maximum startup time (in microseconds) of XOSC_HF +// +//***************************************************************************** +uint32_t +OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ) +{ + uint32_t deltaTimeSinceXoscOnInMs ; + int32_t deltaTempSinceXoscOn ; + uint32_t newStartupTimeInUs ; + + deltaTimeSinceXoscOnInMs = RTC_CV_TO_MS( AONRTCCurrentCompareValueGet() - oscHfGlobals.timeXoscOn_CV ); + deltaTempSinceXoscOn = AONBatMonTemperatureGetDegC() - oscHfGlobals.tempXoscOff; + + if ( deltaTempSinceXoscOn < 0 ) { + deltaTempSinceXoscOn = -deltaTempSinceXoscOn; + } + + if ( (( timeUntilWakeupInMs + deltaTimeSinceXoscOnInMs ) > 3000 ) || + ( deltaTempSinceXoscOn > 5 ) || + ( oscHfGlobals.timeXoscStable_CV < oscHfGlobals.timeXoscOn_CV ) || + ( oscHfGlobals.previousStartupTimeInUs == 0 ) ) + { + newStartupTimeInUs = 2000; + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) { + newStartupTimeInUs = (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & + CCFG_MODE_CONF_1_XOSC_MAX_START_M ) >> + CCFG_MODE_CONF_1_XOSC_MAX_START_S ) * 125; + // Note: CCFG startup time is "in units of 100us" adding 25% margin results in *125 + } + } else { + newStartupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV ); + newStartupTimeInUs += ( newStartupTimeInUs >> 2 ); // Add 25 percent margin + if ( newStartupTimeInUs < oscHfGlobals.previousStartupTimeInUs ) { + newStartupTimeInUs = oscHfGlobals.previousStartupTimeInUs; + } + } + + if ( newStartupTimeInUs < 200 ) { + newStartupTimeInUs = 200; + } + if ( newStartupTimeInUs > 4000 ) { + newStartupTimeInUs = 4000; + } + return ( newStartupTimeInUs ); +} + + +//***************************************************************************** +// +// Turns on XOSC_HF (but without switching to XOSC_HF) +// +//***************************************************************************** +void +OSCHF_TurnOnXosc( void ) +{ +#if ( defined( ROM_OSCClockSourceSet )) + ROM_OSCClockSourceSet( OSC_SRC_CLK_HF | OSC_SRC_CLK_MF, OSC_XOSC_HF ); +#else + OSCClockSourceSet( OSC_SRC_CLK_HF | OSC_SRC_CLK_MF, OSC_XOSC_HF ); +#endif + oscHfGlobals.timeXoscOn_CV = AONRTCCurrentCompareValueGet(); +} + + +//***************************************************************************** +// +// Switch to XOSC_HF if XOSC_HF is ready. +// +//***************************************************************************** +bool +OSCHF_AttemptToSwitchToXosc( void ) +{ + uint32_t startupTimeInUs; + uint32_t prevLimmit25InUs; + +#if ( defined( ROM_OSCClockSourceGet )) + if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF ) +#else + if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF ) +#endif + { + // Already on XOSC - nothing to do + return ( 1 ); + } + if ( OSCHfSourceReady()) { + OSCHfSourceSwitch(); + + // Store startup time, but limit to 25 percent reduction each time. + oscHfGlobals.timeXoscStable_CV = AONRTCCurrentCompareValueGet(); + startupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV ); + prevLimmit25InUs = oscHfGlobals.previousStartupTimeInUs; + prevLimmit25InUs -= ( prevLimmit25InUs >> 2 ); // 25 percent margin + oscHfGlobals.previousStartupTimeInUs = startupTimeInUs; + if ( prevLimmit25InUs > startupTimeInUs ) { + oscHfGlobals.previousStartupTimeInUs = prevLimmit25InUs; + } + return ( 1 ); + } + return ( 0 ); +} + + +//***************************************************************************** +// +// Switch to RCOSC_HF and turn off XOSC_HF +// +//***************************************************************************** +void +OSCHF_SwitchToRcOscTurnOffXosc( void ) +{ + // Set SCLK_HF and SCLK_MF to RCOSC_HF without checking + // Doing this anyway to keep HF and MF in sync +#if ( defined( ROM_OSCClockSourceSet )) + ROM_OSCClockSourceSet( OSC_SRC_CLK_HF | OSC_SRC_CLK_MF, OSC_RCOSC_HF ); +#else + OSCClockSourceSet( OSC_SRC_CLK_HF | OSC_SRC_CLK_MF, OSC_RCOSC_HF ); +#endif + + // Do the switching if not already running on RCOSC_HF +#if ( defined( ROM_OSCClockSourceGet )) + if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF ) +#else + if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF ) +#endif + { + OSCHfSourceSwitch(); + } + + oscHfGlobals.timeXoscOff_CV = AONRTCCurrentCompareValueGet(); + oscHfGlobals.tempXoscOff = AONBatMonTemperatureGetDegC(); +} + +//***************************************************************************** +// +// Adjust the XOSC HF cap array relative to the factory setting +// +//***************************************************************************** +void +OSC_AdjustXoscHfCapArray( int32_t capArrDelta ) +{ + // read the MODE_CONF register in CCFG + uint32_t ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + // Clear CAP_MODE and the CAPARRAY_DELATA field + ccfg_ModeConfReg &= ~( CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M | CCFG_MODE_CONF_XOSC_CAP_MOD_M ); + // Insert new delta value + ccfg_ModeConfReg |= ((((uint32_t)capArrDelta) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) & CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ); + // Update the HW register with the new delta value + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg )); +} + +//***************************************************************************** +// +// Calculate the temperature dependent relative frequency offset of HPOSC +// +//***************************************************************************** +int32_t +OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ) +{ + // Estimate HPOSC frequency, using temperature and curve fitting parameters + + uint32_t fitParams = HWREG( FCFG1_BASE + FCFG1_O_FREQ_OFFSET ); + // Extract the P0,P1,P2 params, and sign extend them via shifting up/down + int32_t paramP0 = (((int32_t)( fitParams << ( 32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S ))) + >> ( 32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W )); + int32_t paramP1 = (((int32_t)( fitParams << ( 32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S ))) + >> ( 32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W )); + int32_t paramP2 = (((int32_t)( fitParams << ( 32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S ))) + >> ( 32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W )); + + uint32_t fitParP3 = HWREG( FCFG1_BASE + FCFG1_O_MISC_CONF_2 ); + // Extract the P3 param, and sign extend via shifting up/down + int32_t paramP3 = (((int32_t)( fitParP3 << ( 32 - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S ))) + >> ( 32 - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W )); + + // Now we can find the HPOSC freq offset, given as a signed variable d, expressed by: + // + // F_HPOSC = F_nom * (1 + d/(2^22)) , where: F_HPOSC = HPOSC frequency + // F_nom = nominal clock source frequency (e.g. 48.000 MHz) + // d = describes relative freq offset + + // We can estimate the d variable, using temperature compensation parameters: + // + // d = P0 + P1*(t - T0) + P2*(t - T0)^2 + P3*(t - T0)^3, where: P0,P1,P2,P3 are curve fitting parameters from FCFG1 + // t = current temperature (from temp sensor) in deg C + // T0 = 27 deg C (fixed temperature constant) + int32_t tempDelta = (tempDegC - 27); + int32_t tempDeltaX2 = tempDelta * tempDelta; + int32_t d = paramP0 + ((tempDelta*paramP1)>>3) + ((tempDeltaX2*paramP2)>>10) + ((tempDeltaX2*tempDelta*paramP3)>>18); + + return ( d ); +} + +//***************************************************************************** +// +// Converts the relative frequency offset of HPOSC to the RF Core parameter format. +// +//***************************************************************************** +int16_t +OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ) +{ + // The input argument, hereby referred to simply as "d", describes the frequency offset + // of the HPOSC relative to the nominal frequency in this way: + // + // F_HPOSC = F_nom * (1 + d/(2^22)) + // + // But for use by the radio, to compensate the frequency error, we need to find the + // frequency offset "rfcFreqOffset" defined in the following format: + // + // F_nom = F_HPOSC * (1 + rfCoreFreqOffset/(2^22)) + // + // To derive "rfCoreFreqOffset" from "d" we combine the two above equations and get: + // + // (1 + rfCoreFreqOffset/(2^22)) = (1 + d/(2^22))^-1 + // + // Which can be rewritten into: + // + // rfCoreFreqOffset = -d*(2^22) / ((2^22) + d) + // + // = -d * [ 1 / (1 + d/(2^22)) ] + // + // To avoid doing a 64-bit division due to the (1 + d/(2^22))^-1 expression, + // we can use Taylor series (Maclaurin series) to approximate it: + // + // 1 / (1 - x) ~= 1 + x + x^2 + x^3 + x^4 + ... etc (Maclaurin series) + // + // In our case, we have x = - d/(2^22), and we only include up to the first + // order term of the series, as the second order term ((d^2)/(2^44)) is very small: + // + // freqError ~= -d + d^2/(2^22) (+ small approximation error) + // + // The approximation error is negligible for our use. + + int32_t rfCoreFreqOffset = -HPOSC_RelFreqOffset + (( HPOSC_RelFreqOffset * HPOSC_RelFreqOffset ) >> 22 ); + + return ( rfCoreFreqOffset ); +} + +//***************************************************************************** +// +// Get crystal amplitude (assuming crystal is running). +// +//***************************************************************************** +uint32_t +OSCHF_DebugGetCrystalAmplitude( void ) +{ + uint32_t oscCfgRegCopy ; + uint32_t startTime ; + uint32_t deltaTime ; + uint32_t ampValue ; + + // The specified method is as follows: + // 1. Set minimum interval between oscillator amplitude calibrations. + // (Done by setting PER_M=0 and PER_E=1) + // 2. Wait approximately 4 milliseconds in order to measure over a + // moderately large number of calibrations. + // 3. Read out the crystal amplitude value from the peek detector. + // 4. Restore original oscillator amplitude calibrations interval. + // 5. Return crystal amplitude value converted to millivolt. + oscCfgRegCopy = HWREG( AON_WUC_BASE + AON_WUC_O_OSCCFG ); + HWREG( AON_WUC_BASE + AON_WUC_O_OSCCFG ) = ( 1 << AON_WUC_OSCCFG_PER_E_S ); + startTime = AONRTCCurrentCompareValueGet(); + do { + deltaTime = AONRTCCurrentCompareValueGet() - startTime; + } while ( deltaTime < ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT ))); + ampValue = ( HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_STAT1 ) & + DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M ) >> + DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S ; + HWREG( AON_WUC_BASE + AON_WUC_O_OSCCFG ) = oscCfgRegCopy; + + return ( ampValue * 15 ); +} + +//***************************************************************************** +// +// Get the expected average crystal amplitude. +// +//***************************************************************************** +uint32_t +OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ) +{ + uint32_t ampCompTh1 ; + uint32_t highThreshold ; + uint32_t lowThreshold ; + + ampCompTh1 = HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_AMPCOMPTH1 ); + highThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M ) >> + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S ; + lowThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M ) >> + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S ; + + return ((( highThreshold + lowThreshold ) * 15 ) >> 1 ); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/osc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/osc.h new file mode 100644 index 0000000..4281a96 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/osc.h @@ -0,0 +1,562 @@ +/****************************************************************************** +* Filename: osc.h +* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) +* Revision: 54539 +* +* Description: Defines and prototypes for the system oscillator control. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup osc_api +//! @{ +// +//***************************************************************************** + +#ifndef __OSC_H__ +#define __OSC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ddi.h" +#include "../inc/hw_ddi_0_osc.h" +#include "rom.h" +#include "ddi.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define OSCClockSourceSet NOROM_OSCClockSourceSet + #define OSCClockSourceGet NOROM_OSCClockSourceGet + #define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime + #define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc + #define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc + #define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc + #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude + #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet + #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray + #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert +#endif + +//***************************************************************************** +// +// Defines for the High Frequency XTAL Power mode +// +//***************************************************************************** +#define LOW_POWER_XOSC 1 +#define HIGH_POWER_XOSC 0 + +//***************************************************************************** +// +// Defines for the High Frequency XTAL Power mode +// +//***************************************************************************** +#define OSC_SRC_CLK_HF 0x00000001 +#define OSC_SRC_CLK_MF 0x00000002 +#define OSC_SRC_CLK_LF 0x00000004 + +#define OSC_RCOSC_HF 0x00000000 +#define OSC_XOSC_HF 0x00000001 +#define OSC_RCOSC_LF 0x00000002 +#define OSC_XOSC_LF 0x00000003 + +#define SCLK_HF_RCOSC_HF 0 +#define SCLK_HF_XOSC_HF 1 + +#define SCLK_MF_RCOSC_HF 0 +#define SCLK_MF_XOSC_HF 1 + +#define SCLK_LF_FROM_RCOSC_HF 0 +#define SCLK_LF_FROM_XOSC_HF 1 +#define SCLK_LF_FROM_RCOSC_LF 2 +#define SCLK_LF_FROM_XOSC_LF 3 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Set Power Mode for High Frequency XTAL Oscillator. +//! +//! \param ui32Mode is the power mode for the HF XTAL. +//! - \ref LOW_POWER_XOSC +//! - \ref HIGH_POWER_XOSC +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +OSCXHfPowerModeSet(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == LOW_POWER_XOSC) || + (ui32Mode == HIGH_POWER_XOSC)); + + // Change the power mode. + DDI16BitWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE, + ui32Mode); +} + +//***************************************************************************** +// +//! \brief Enables OSC clock loss event detection. +//! +//! Enables the clock loss event flag to be raised if a clock loss is detected. +//! +//! \note OSC clock loss event must be disabled before SCLK_LF clock source is +//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the +//! change is confirmed (by calling \ref OSCClockSourceGet()). +//! +//! \return None +//! +//! \sa \ref OSCClockLossEventDisable() +// +//***************************************************************************** +__STATIC_INLINE void +OSCClockLossEventEnable( void ) +{ + DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 1 ); +} + +//***************************************************************************** +// +//! \brief Disables OSC clock loss event detection. +//! +//! Disabling the OSC clock loss event does also clear the clock loss event flag. +//! +//! \note OSC clock loss event must be disabled before SCLK_LF clock source is +//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the +//! change is confirmed (by calling \ref OSCClockSourceGet()). +//! +//! \return None +//! +//! \sa \ref OSCClockLossEventEnable() +// +//***************************************************************************** +__STATIC_INLINE void +OSCClockLossEventDisable( void ) +{ + DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 0 ); +} + +//***************************************************************************** +// +//! \brief Configure the oscillator input to the a source clock. +//! +//! Use this function to set the oscillator source for one or more of the +//! system source clocks. +//! +//! When selecting the high frequency clock source (OSC_SRC_CLK_HF), this function will not do +//! the actual switch. Enabling the high frequency XTAL can take several hundred +//! micro seconds, so the actual switch is done in a separate function, \ref OSCHfSourceSwitch(), +//! leaving System CPU free to perform other tasks as the XTAL starts up. +//! +//! \note The High Frequency (\ref OSC_SRC_CLK_HF) and Medium Frequency +//! (\ref OSC_SRC_CLK_MF) can only be derived from the high frequency +//! oscillator. The Low Frequency source clock (\ref OSC_SRC_CLK_LF) can be +//! derived from all 4 oscillators. +//! +//! \note If enabling \ref OSC_XOSC_LF it is not safe to go to powerdown/shutdown +//! until the LF clock is running which can be checked using \ref OSCClockSourceGet(). +//! +//! \note Clock loss reset generation must be disabled before SCLK_LF (\ref OSC_SRC_CLK_LF) +//! clock source is changed and remain disabled until the change is confirmed. +//! +//! \param ui32SrcClk is the source clocks to configure. +//! - \ref OSC_SRC_CLK_HF +//! - \ref OSC_SRC_CLK_MF +//! - \ref OSC_SRC_CLK_LF +//! \param ui32Osc is the oscillator that drives the source clock. +//! - \ref OSC_RCOSC_HF +//! - \ref OSC_XOSC_HF +//! - \ref OSC_RCOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF) +//! - \ref OSC_XOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF) +//! +//! \sa \ref OSCClockSourceGet(), \ref OSCHfSourceSwitch() +//! +//! \return None +// +//***************************************************************************** +extern void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc); + +//***************************************************************************** +// +//! \brief Get the source clock settings. +//! +//! Use this function to get the oscillator source for one of the system source +//! clocks. +//! +//! \param ui32SrcClk is the source clock to check. +//! - \ref OSC_SRC_CLK_HF +//! - \ref OSC_SRC_CLK_MF +//! - \ref OSC_SRC_CLK_LF +//! +//! \return Returns the type of oscillator that drives the clock source. +//! - \ref OSC_RCOSC_HF +//! - \ref OSC_XOSC_HF +//! - \ref OSC_RCOSC_LF +//! - \ref OSC_XOSC_LF +//! +//! \sa \ref OSCClockSourceSet(), \ref OSCHfSourceSwitch() +// +//***************************************************************************** +extern uint32_t OSCClockSourceGet(uint32_t ui32SrcClk); + +//***************************************************************************** +// +//! \brief Check if the HF clock source is ready to be switched. +//! +//! If a request to switch the HF clock source has been made, this function +//! can be used to check if the clock source is ready to be switched. +//! +//! Once the HF clock source is ready the switch can be performed by calling +//! the \ref OSCHfSourceSwitch() +//! +//! \return Returns status of HF clock source: +//! - \c true : HF clock source is ready. +//! - \c false : HF clock source is \b not ready. +// +//***************************************************************************** +__STATIC_INLINE bool +OSCHfSourceReady(void) +{ + // Return the readiness of the HF clock source + return (DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M, + DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S)) ? + true : false; +} + +//***************************************************************************** +// +//! \brief Switch the high frequency clock. +//! +//! When switching the HF clock source the clock period might be prolonged +//! leaving the clock 'stuck-at' high or low for a few cycles. To ensure that +//! this does not coincide with a read access to the Flash, potentially +//! freezing the device, the HF clock source switch must be executed from ROM. +//! +//! \note This function will not return until the clock source has been +//! switched. It is left to the programmer to ensure, that there is a pending +//! request for a HF clock source switch before this function is called. +//! +//! \return None +//! +//! \sa \ref OSCClockSourceSet() +// +//***************************************************************************** +__STATIC_INLINE void +OSCHfSourceSwitch(void) +{ + // Switch the HF clock source + HapiHFSourceSafeSwitch(); +} + +//***************************************************************************** +// +//! \brief Returns maximum startup time (in microseconds) of XOSC_HF. +//! +//! The startup time depends on several factors. This function calculates the +//! maximum startup time based on statistical information. +//! +//! \param timeUntilWakeupInMs indicates how long time (milliseconds) to the +//! startup will occur. +//! +//! \return Time margin to use in microseconds. +// +//***************************************************************************** +extern uint32_t OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ); + +//***************************************************************************** +// +//! \brief Turns on XOSC_HF (but without switching to XOSC_HF). +//! +//! This function simply indicates the need for XOSC_HF to the hardware which +//! initiates the XOSC_HF startup. +//! +//! \return None +// +//***************************************************************************** +extern void OSCHF_TurnOnXosc( void ); + +//***************************************************************************** +// +//! \brief Switch to XOSC_HF if XOSC_HF is ready. +//! +//! This is a non-blocking function checking if the XOSC_HF is ready and +//! performs the switching if ready. The function is somewhat blocking in the +//! case where switching is performed. +//! +//! \return Returns status of the XOSC_HF switching: +//! - \c true : Switching to XOSC_HF has occurred. +//! - \c false : Switching has not occurred. +// +//***************************************************************************** +extern bool OSCHF_AttemptToSwitchToXosc( void ); + +//***************************************************************************** +// +//! \brief Switch to RCOSC_HF and turn off XOSC_HF. +//! +//! This operation takes approximately 50 microseconds (can be shorter if +//! RCOSC_HF already was running). +//! +//! \return None +// +//***************************************************************************** +extern void OSCHF_SwitchToRcOscTurnOffXosc( void ); + +//***************************************************************************** +// +//! \brief Get crystal amplitude (assuming crystal is running). +//! +//! \note This is a debug function only. +//! It is hence not recommended to call this function in normal operation. +//! +//! This function uses an on-chip ADC and peak detector for reading the crystal +//! amplitude. The measurement time is set to 4 milliseconds and this function +//! does not return before the measurement is done. +//! +//! Expected value is \ref OSCHF_DebugGetExpectedAverageCrystalAmplitude +/- 50 millivolt. +//! +//! \return Returns crystal amplitude in millivolt. +//! +//! \sa OSCHF_DebugGetExpectedAverageCrystalAmplitude() +// +//***************************************************************************** +extern uint32_t OSCHF_DebugGetCrystalAmplitude( void ); + +//***************************************************************************** +// +//! \brief Get the expected average crystal amplitude. +//! +//! \note This is a debug function only. +//! It is hence not recommended to call this function in normal operation. +//! +//! This function read the configured high and low thresholds and returns +//! the mean value converted to millivolt. +//! +//! \return Returns expected average crystal amplitude in millivolt. +//! +//! \sa OSCHF_DebugGetCrystalAmplitude() +// +//***************************************************************************** +extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ); + +//***************************************************************************** +// +//! \brief Calculate the temperature dependent relative frequency offset of HPOSC +//! +//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature. +//! The frequency offset from the nominal value can be predicted based on +//! second order linear interpolation using coefficients measured in chip +//! production and stored as factory configuration parameters. +//! +//! This function calculates the relative frequency offset, defined as: +//! 
+//!     F_HPOSC = F_nom * (1 + d/(2^22))
+//!
+//! where +//! - F_HPOSC is the current HPOSC frequency. +//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. +//! - d is the relative frequency offset (the value returned). +//! +//! By knowing the relative frequency offset it is then possible to compensate +//! any timing related values accordingly. +//! +//! \param tempDegC is the chip temperature in degrees Celsius. Use the +//! function \ref AONBatMonTemperatureGetDegC() to get current chip temperature. +//! +//! \return Returns the relative frequency offset parameter d. +//! +//! \sa OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(), AONBatMonTemperatureGetDegC() +// +//***************************************************************************** +extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ); + +//***************************************************************************** +// +//! \brief Adjust the XOSC HF cap array relative to the factory setting +//! +//! The cap array factory setting (FCFG) can be converted to a number in the range 0 - 63. +//! Both this function and the customer configuration (CCFG) setting can apply a delta to the FCFG setting. +//! The CCFG setting is automatically applied at boot time (See ../startup_files/ccfg.c). +//! Calling this function will discard the CCFG setting and adjust relative to the FCFG setting. +//! +//! \note Adjusted value will not take effect before XOSC_HF is stopped and restarted +//! +//! \param capArrDelta specifies number of step to adjust the cap array relative to the factory setting. +//! +//! \return None +// +//***************************************************************************** +extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta ); + +//***************************************************************************** +// +//! \brief Converts the relative frequency offset of HPOSC to the RF Core parameter format. +//! +//! The HPOSC (High Precision Oscillator) clock is used by the RF Core. +//! To compensate for a frequency offset in the frequency of the clock source, +//! a frequency offset parameter can be provided as part of the radio configuration +//! override setting list to enable compensation of the RF synthesizer frequency, +//! symbol timing, and radio timer to still achieve correct frequencies. +//! +//! The RF Core takes a relative frequency offset parameter defined differently +//! compared to the relative frequency offset parameter returned from function +//! \ref OSC_HPOSCRelativeFrequencyOffsetGet() and thus needs to be converted: +//! 
+//!     F_nom = F_HPOSC * (1 + RfCoreRelFreqOffset/(2^22))
+//!
+//! where +//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. +//! - F_HPOSC is the current HPOSC frequency. +//! - RfCoreRelFreqOffset is the relative frequency offset in the "RF Core" format (the value returned). +//! +//! \param HPOSC_RelFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet() +//! +//! \return Returns the relative frequency offset in RF Core format. +//! +//! \sa OSC_HPOSCRelativeFrequencyOffsetGet() +// +//***************************************************************************** +extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_OSCClockSourceSet + #undef OSCClockSourceSet + #define OSCClockSourceSet ROM_OSCClockSourceSet + #endif + #ifdef ROM_OSCClockSourceGet + #undef OSCClockSourceGet + #define OSCClockSourceGet ROM_OSCClockSourceGet + #endif + #ifdef ROM_OSCHF_GetStartupTime + #undef OSCHF_GetStartupTime + #define OSCHF_GetStartupTime ROM_OSCHF_GetStartupTime + #endif + #ifdef ROM_OSCHF_TurnOnXosc + #undef OSCHF_TurnOnXosc + #define OSCHF_TurnOnXosc ROM_OSCHF_TurnOnXosc + #endif + #ifdef ROM_OSCHF_AttemptToSwitchToXosc + #undef OSCHF_AttemptToSwitchToXosc + #define OSCHF_AttemptToSwitchToXosc ROM_OSCHF_AttemptToSwitchToXosc + #endif + #ifdef ROM_OSCHF_SwitchToRcOscTurnOffXosc + #undef OSCHF_SwitchToRcOscTurnOffXosc + #define OSCHF_SwitchToRcOscTurnOffXosc ROM_OSCHF_SwitchToRcOscTurnOffXosc + #endif + #ifdef ROM_OSCHF_DebugGetCrystalAmplitude + #undef OSCHF_DebugGetCrystalAmplitude + #define OSCHF_DebugGetCrystalAmplitude ROM_OSCHF_DebugGetCrystalAmplitude + #endif + #ifdef ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude + #define OSCHF_DebugGetExpectedAverageCrystalAmplitude ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #endif + #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetGet + #undef OSC_HPOSCRelativeFrequencyOffsetGet + #define OSC_HPOSCRelativeFrequencyOffsetGet ROM_OSC_HPOSCRelativeFrequencyOffsetGet + #endif + #ifdef ROM_OSC_AdjustXoscHfCapArray + #undef OSC_AdjustXoscHfCapArray + #define OSC_AdjustXoscHfCapArray ROM_OSC_AdjustXoscHfCapArray + #endif + #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __OSC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/prcm.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/prcm.c new file mode 100644 index 0000000..232c96c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/prcm.c @@ -0,0 +1,652 @@ +/****************************************************************************** +* Filename: prcm.c +* Revised: 2018-10-18 17:33:32 +0200 (Thu, 18 Oct 2018) +* Revision: 52954 +* +* Description: Driver for the PRCM. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "prcm.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef PRCMInfClockConfigureSet + #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet + #undef PRCMInfClockConfigureGet + #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet + #undef PRCMAudioClockConfigSet + #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet + #undef PRCMAudioClockConfigSetOverride + #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride + #undef PRCMAudioClockInternalSource + #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource + #undef PRCMAudioClockExternalSource + #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource + #undef PRCMPowerDomainOn + #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn + #undef PRCMPowerDomainOff + #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff + #undef PRCMPeripheralRunEnable + #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable + #undef PRCMPeripheralRunDisable + #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable + #undef PRCMPeripheralSleepEnable + #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable + #undef PRCMPeripheralSleepDisable + #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable + #undef PRCMPeripheralDeepSleepEnable + #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable + #undef PRCMPeripheralDeepSleepDisable + #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable + #undef PRCMPowerDomainStatus + #define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus + #undef PRCMDeepSleep + #define PRCMDeepSleep NOROM_PRCMDeepSleep +#endif + + +//***************************************************************************** +// +// Arrays that maps the "peripheral set" number (which is stored in +// bits[11:8] of the PRCM_PERIPH_* defines) to the PRCM register that +// contains the relevant bit for that peripheral. +// +//***************************************************************************** + +// Run mode registers +static const uint32_t g_pui32RCGCRegs[] = +{ + PRCM_O_GPTCLKGR , // Index 0 + PRCM_O_SSICLKGR , // Index 1 + PRCM_O_UARTCLKGR , // Index 2 + PRCM_O_I2CCLKGR , // Index 3 + PRCM_O_SECDMACLKGR , // Index 4 + PRCM_O_GPIOCLKGR , // Index 5 + PRCM_O_I2SCLKGR // Index 6 +}; + +// Sleep mode registers +static const uint32_t g_pui32SCGCRegs[] = +{ + PRCM_O_GPTCLKGS , // Index 0 + PRCM_O_SSICLKGS , // Index 1 + PRCM_O_UARTCLKGS , // Index 2 + PRCM_O_I2CCLKGS , // Index 3 + PRCM_O_SECDMACLKGS , // Index 4 + PRCM_O_GPIOCLKGS , // Index 5 + PRCM_O_I2SCLKGS // Index 6 +}; + +// Deep sleep mode registers +static const uint32_t g_pui32DCGCRegs[] = +{ + PRCM_O_GPTCLKGDS , // Index 0 + PRCM_O_SSICLKGDS , // Index 1 + PRCM_O_UARTCLKGDS , // Index 2 + PRCM_O_I2CCLKGDS , // Index 3 + PRCM_O_SECDMACLKGDS , // Index 4 + PRCM_O_GPIOCLKGDS , // Index 5 + PRCM_O_I2SCLKGDS // Index 6 +}; + +//***************************************************************************** +// +// This macro extracts the array index out of the peripheral number +// +//***************************************************************************** +#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf) + +//***************************************************************************** +// +// This macro extracts the peripheral instance number and generates bit mask +// +//***************************************************************************** +#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0x1f)) + + +//***************************************************************************** +// +// Configure the infrastructure clock. +// +//***************************************************************************** +void +PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode) +{ + uint32_t ui32Divisor; + + // Check the arguments. + ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || + (ui32ClkDiv == PRCM_CLOCK_DIV_2) || + (ui32ClkDiv == PRCM_CLOCK_DIV_8) || + (ui32ClkDiv == PRCM_CLOCK_DIV_32)); + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32Divisor = 0; + + // Find the correct division factor. + if(ui32ClkDiv == PRCM_CLOCK_DIV_1) + { + ui32Divisor = 0x0; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_2) + { + ui32Divisor = 0x1; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_8) + { + ui32Divisor = 0x2; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_32) + { + ui32Divisor = 0x3; + } + + // Determine the correct power mode set the division factor accordingly. + if(ui32PowerMode == PRCM_RUN_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor; + } +} + +//***************************************************************************** +// +// Use this function to get the infrastructure clock configuration +// +//***************************************************************************** +uint32_t +PRCMInfClockConfigureGet(uint32_t ui32PowerMode) +{ + uint32_t ui32ClkDiv; + uint32_t ui32Divisor; + + // Check the arguments. + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32ClkDiv = 0; + ui32Divisor = 0; + + // Determine the correct power mode. + if(ui32PowerMode == PRCM_RUN_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR); + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS); + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS); + } + + // Find the correct division factor. + if(ui32ClkDiv == 0x0) + { + ui32Divisor = PRCM_CLOCK_DIV_1; + } + else if(ui32ClkDiv == 0x1) + { + ui32Divisor = PRCM_CLOCK_DIV_2; + } + else if(ui32ClkDiv == 0x2) + { + ui32Divisor = PRCM_CLOCK_DIV_8; + } + else if(ui32ClkDiv == 0x3) + { + ui32Divisor = PRCM_CLOCK_DIV_32; + } + + // Return the clock division factor. + return ui32Divisor; +} + + +//***************************************************************************** +// +// Configure the audio clock generation +// +//***************************************************************************** +void +PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate) +{ + uint32_t ui32Reg; + uint32_t ui32MstDiv; + uint32_t ui32BitDiv; + uint32_t ui32WordDiv; + + // Check the arguments. + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) || + (ui32SampleRate == I2S_SAMPLE_RATE_24K) || + (ui32SampleRate == I2S_SAMPLE_RATE_32K) || + (ui32SampleRate == I2S_SAMPLE_RATE_48K)); + + ui32MstDiv = 0; + ui32BitDiv = 0; + ui32WordDiv = 0; + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Define the clock division factors for the audio interface. + switch(ui32SampleRate) + { + case I2S_SAMPLE_RATE_16K : + ui32MstDiv = 6; + ui32BitDiv = 60; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_24K : + ui32MstDiv = 4; + ui32BitDiv = 40; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_32K : + ui32MstDiv = 3; + ui32BitDiv = 30; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_48K : + ui32MstDiv = 2; + ui32BitDiv = 20; + ui32WordDiv = 25; + break; + } + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity. + ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} + +//***************************************************************************** +// +// Configure the audio clock generation with manual setting of clock divider. +// +//***************************************************************************** +void +PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, + uint32_t ui32BitDiv, uint32_t ui32WordDiv) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity. + ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} + +//***************************************************************************** +// +// Configure the audio clocks for I2S module +// +//***************************************************************************** +void +PRCMAudioClockConfigOverride(uint8_t ui8SamplingEdge, + uint8_t ui8WCLKPhase, + uint32_t ui32MstDiv, + uint32_t ui32BitDiv, + uint32_t ui32WordDiv) +{ + // Check the arguments. + ASSERT( ui8BitsPerSample == PRCM_WCLK_SINGLE_PHASE + || ui8BitsPerSample == PRCM_WCLK_DUAL_PHASE + || ui8BitsPerSample == PRCM_WCLK_USER_DEF); + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui8WCLKPhase) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity and enable it. + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = (ui8SamplingEdge << PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S) | + (ui8WCLKPhase << PRCM_I2SCLKCTL_WCLK_PHASE_S ) | + (1 << PRCM_I2SCLKCTL_EN_S ); +} + +//***************************************************************************** +// +// Configure the clocks as "internally generated". +// +//***************************************************************************** +void PRCMAudioClockInternalSource(void) +{ + HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 1; +} + +//***************************************************************************** +// +// Configure the clocks as "externally generated". +// +//***************************************************************************** +void PRCMAudioClockExternalSource(void) +{ + HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 0; +} + +//***************************************************************************** +// +// Turn power on in power domains in the MCU domain +// +//***************************************************************************** +void +PRCMPowerDomainOn(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Assert the request to power on the right domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 1; + // The PDCTL1RFC access is meant to "be used by RFC in autonomous mode", but keeping + // it for compatibility on already ROM'ed products (since this is a ROM function). + // RFC power domain is on if ( PRCM_O_PDCTL0RFC || PRCM_O_PDCTL1RFC ). + HWREG(PRCM_BASE + PRCM_O_PDCTL1RFC ) = 1; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 1; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 1; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 1; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 1; + } +} + +//***************************************************************************** +// +// Turn off a specific power domain +// +//***************************************************************************** +void +PRCMPowerDomainOff(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Assert the request to power off the right domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 0; + // The PDCTL1RFC access is meant to "be used by RFC in autonomous mode", but keeping + // it for compatibility on already ROM'ed products (since this is a ROM function). + // RFC power domain is on if ( PRCM_O_PDCTL0RFC || PRCM_O_PDCTL1RFC ). + HWREG(PRCM_BASE + PRCM_O_PDCTL1RFC ) = 0; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 0; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 0; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 0; + } +} + +//***************************************************************************** +// +// Enables a peripheral in Run mode +// +//***************************************************************************** +void +PRCMPeripheralRunEnable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable module in Run Mode. + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Disables a peripheral in Run mode +// +//***************************************************************************** +void +PRCMPeripheralRunDisable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable module in Run Mode. + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Enables a peripheral in sleep mode +// +//***************************************************************************** +void +PRCMPeripheralSleepEnable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable this peripheral in sleep mode. + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Disables a peripheral in sleep mode +// +//***************************************************************************** +void +PRCMPeripheralSleepDisable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable this peripheral in sleep mode + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Enables a peripheral in deep-sleep mode +// +//***************************************************************************** +void +PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable this peripheral in deep-sleep mode. + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Disables a peripheral in deep-sleep mode +// +//***************************************************************************** +void +PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable this peripheral in Deep Sleep mode. + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Get the status for a specific power domain +// +//***************************************************************************** +uint32_t +PRCMPowerDomainStatus(uint32_t ui32Domains) +{ + bool bStatus; + uint32_t ui32StatusRegister0; + uint32_t ui32StatusRegister1; + + // Check the arguments. + ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE | + PRCM_DOMAIN_SERIAL | + PRCM_DOMAIN_PERIPH))); + + bStatus = true; + ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0); + ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1); + + // Return the correct power status. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + bStatus = bStatus && + ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) || + (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON)); + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON); + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON); + } + + // Return the status. + return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF); +} + +//***************************************************************************** +// +// Put the processor into deep-sleep mode +// +//***************************************************************************** +void +PRCMDeepSleep(void) +{ + // Enable deep-sleep. + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // Wait for an interrupt. + CPUwfi(); + + // Disable deep-sleep so that a future sleep will work correctly. + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/prcm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/prcm.h new file mode 100644 index 0000000..663afd1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/prcm.h @@ -0,0 +1,1252 @@ +/****************************************************************************** +* Filename: prcm.h +* Revised: 2018-10-23 10:19:14 +0200 (Tue, 23 Oct 2018) +* Revision: 52979 +* +* Description: Defines and prototypes for the PRCM +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup prcm_api +//! @{ +// +//***************************************************************************** + +#ifndef __PRCM_H__ +#define __PRCM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_aon_rtc.h" +#include "interrupt.h" +#include "debug.h" +#include "cpu.h" + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet + #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet + #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet + #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride + #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource + #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource + #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn + #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff + #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable + #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable + #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable + #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable + #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable + #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable + #define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus + #define PRCMDeepSleep NOROM_PRCMDeepSleep +#endif + +//***************************************************************************** +// +// Defines for the different System CPU power modes. +// +//***************************************************************************** +#define PRCM_RUN_MODE 0x00000001 +#define PRCM_SLEEP_MODE 0x00000002 +#define PRCM_DEEP_SLEEP_MODE 0x00000004 + +//***************************************************************************** +// +// Defines used for setting the clock division factors +// +//***************************************************************************** +#define PRCM_CLOCK_DIV_1 PRCM_GPTCLKDIV_RATIO_DIV1 +#define PRCM_CLOCK_DIV_2 PRCM_GPTCLKDIV_RATIO_DIV2 +#define PRCM_CLOCK_DIV_4 PRCM_GPTCLKDIV_RATIO_DIV4 +#define PRCM_CLOCK_DIV_8 PRCM_GPTCLKDIV_RATIO_DIV8 +#define PRCM_CLOCK_DIV_16 PRCM_GPTCLKDIV_RATIO_DIV16 +#define PRCM_CLOCK_DIV_32 PRCM_GPTCLKDIV_RATIO_DIV32 +#define PRCM_CLOCK_DIV_64 PRCM_GPTCLKDIV_RATIO_DIV64 +#define PRCM_CLOCK_DIV_128 PRCM_GPTCLKDIV_RATIO_DIV128 +#define PRCM_CLOCK_DIV_256 PRCM_GPTCLKDIV_RATIO_DIV256 + +//***************************************************************************** +// +// Defines used for enabling and disabling domains and memories in the MCU +// domain +// +//***************************************************************************** +#define PRCM_DOMAIN_RFCORE 0x00000001 // RF Core domain ID for + // clock/power control. +#define PRCM_DOMAIN_SERIAL 0x00000002 // Serial domain ID for + // clock/power control. +#define PRCM_DOMAIN_PERIPH 0x00000004 // Peripheral domain ID for + // clock/power control. +#define PRCM_DOMAIN_SYSBUS 0x00000008 // Bus domain ID for clock/power + // control. +#define PRCM_DOMAIN_VIMS 0x00000010 // VIMS domain ID for clock/power + // control. +#define PRCM_DOMAIN_CPU 0x00000020 // CPU domain ID for clock/power + // control. +#define PRCM_DOMAIN_TIMER 0x00000040 // GPT domain ID for clock + // control. +#define PRCM_DOMAIN_CLKCTRL 0x00000080 // Clock Control domain ID for + // clock/power control. +#define PRCM_DOMAIN_MCU 0x00000100 // Reset control for entire MCU + // domain. +#define PRCM_DOMAIN_POWER_OFF 0x00000002 // The domain is powered off +#define PRCM_DOMAIN_POWER_ON 0x00000001 // The domain is powered on +#define PRCM_DOMAIN_POWER_DOWN_READY \ + 0x00000000 // The domain is ready to be + // powered down. + +//***************************************************************************** +// +// Defines for setting up the audio interface in the I2S module. +// +//***************************************************************************** +#define PRCM_WCLK_NEG_EDGE 0x00000008 +#define PRCM_WCLK_POS_EDGE 0x00000000 +#define PRCM_WCLK_SINGLE_PHASE 0x00000000 +#define PRCM_WCLK_DUAL_PHASE 0x00000002 +#define PRCM_WCLK_USER_DEF 0x00000004 +#define PRCM_I2S_WCLK_NEG_EDGE 0 +#define PRCM_I2S_WCLK_POS_EDGE 1 +#define PRCM_I2S_WCLK_SINGLE_PHASE 0 +#define PRCM_I2S_WCLK_DUAL_PHASE 1 +#define PRCM_I2S_WCLK_USER_DEF 2 + +#define I2S_SAMPLE_RATE_16K 0x00000001 +#define I2S_SAMPLE_RATE_24K 0x00000002 +#define I2S_SAMPLE_RATE_32K 0x00000004 +#define I2S_SAMPLE_RATE_48K 0x00000008 + +//***************************************************************************** +// +// Defines used for enabling and disabling peripheral modules in the MCU domain +// bits[11:8] Defines the index into the register offset constant tables: +// g_pui32RCGCRegs, g_pui32SCGCRegs and g_pui32DCGCRegs +// bits[4:0] Defines the bit position within the register pointet on in [11:8] +// +//***************************************************************************** +#define PRCM_PERIPH_TIMER0 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S )) // Peripheral ID for GPT module 0 +#define PRCM_PERIPH_TIMER1 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for GPT module 1 +#define PRCM_PERIPH_TIMER2 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 2 )) // Peripheral ID for GPT module 2 +#define PRCM_PERIPH_TIMER3 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 3 )) // Peripheral ID for GPT module 3 +#define PRCM_PERIPH_SSI0 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S )) // Peripheral ID for SSI module 0 +#define PRCM_PERIPH_SSI1 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S + 1 )) // Peripheral ID for SSI module 1 +#define PRCM_PERIPH_UART0 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S )) // Peripheral ID for UART module 0 +#define PRCM_PERIPH_I2C0 ( 0x00000300 | ( PRCM_I2CCLKGR_CLK_EN_S )) // Peripheral ID for I2C module 0 +#define PRCM_PERIPH_CRYPTO ( 0x00000400 | ( PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S )) // Peripheral ID for CRYPTO module +#define PRCM_PERIPH_TRNG ( 0x00000400 | ( PRCM_SECDMACLKGR_TRNG_CLK_EN_S )) // Peripheral ID for TRNG module +#define PRCM_PERIPH_UDMA ( 0x00000400 | ( PRCM_SECDMACLKGR_DMA_CLK_EN_S )) // Peripheral ID for UDMA module +#define PRCM_PERIPH_GPIO ( 0x00000500 | ( PRCM_GPIOCLKGR_CLK_EN_S )) // Peripheral ID for GPIO module +#define PRCM_PERIPH_I2S ( 0x00000600 | ( PRCM_I2SCLKGR_CLK_EN_S )) // Peripheral ID for I2S module + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \brief Checks a peripheral identifier. +//! +//! This function determines if a peripheral identifier is valid. +//! +//! \param ui32Peripheral is the peripheral identifier. +//! +//! \return Returns status of peripheral identifier: +//! - \b true : Peripheral identifier is valid. +//! - \b false : Peripheral identifier is invalid. +// +//***************************************************************************** +static bool +PRCMPeripheralValid(uint32_t ui32Peripheral) +{ + return((ui32Peripheral == PRCM_PERIPH_TIMER0) || + (ui32Peripheral == PRCM_PERIPH_TIMER1) || + (ui32Peripheral == PRCM_PERIPH_TIMER2) || + (ui32Peripheral == PRCM_PERIPH_TIMER3) || + (ui32Peripheral == PRCM_PERIPH_SSI0) || + (ui32Peripheral == PRCM_PERIPH_SSI1) || + (ui32Peripheral == PRCM_PERIPH_UART0) || + (ui32Peripheral == PRCM_PERIPH_I2C0) || + (ui32Peripheral == PRCM_PERIPH_CRYPTO) || + (ui32Peripheral == PRCM_PERIPH_TRNG) || + (ui32Peripheral == PRCM_PERIPH_UDMA) || + (ui32Peripheral == PRCM_PERIPH_GPIO) || + (ui32Peripheral == PRCM_PERIPH_I2S)); +} +#endif + +//***************************************************************************** +// +//! \brief Configure the infrastructure clock. +//! +//! Each System CPU power mode has its own infrastructure clock division factor. This +//! function can be used for setting up the division factor for the +//! infrastructure clock in the available power modes for the System CPU. The +//! infrastructure clock is used for all internal logic in the PRCM, and is +//! always running as long as power is on in the MCU voltage domain. +//! This can be enabled and disabled from the AON Wake Up Controller. +//! +//! \note If source clock is 48 MHz, minimum clock divider is \ref PRCM_CLOCK_DIV_2. +//! +//! \param ui32ClkDiv determines the division ratio for the infrastructure +//! clock when the device is in the specified mode. +//! Allowed division factors for all three System CPU power modes are: +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_32 +//! \param ui32PowerMode determines the System CPU operation mode for which to +//! modify the clock division factor. +//! The three allowed power modes are: +//! - \ref PRCM_RUN_MODE +//! - \ref PRCM_SLEEP_MODE +//! - \ref PRCM_DEEP_SLEEP_MODE +//! +//! \return None +// +//***************************************************************************** +extern void PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, + uint32_t ui32PowerMode); + +//***************************************************************************** +// +//! \brief Use this function to get the infrastructure clock configuration. +//! +//! \param ui32PowerMode determines which System CPU power mode to return the +//! infrastructure clock division ratio for. +//! The three allowed power modes are: +//! - \ref PRCM_RUN_MODE +//! - \ref PRCM_SLEEP_MODE +//! - \ref PRCM_DEEP_SLEEP_MODE +//! +//! \return Returns the infrastructure clock division factor for the specified +//! power mode. +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_32 +//! +//! \sa \ref PRCMInfClockConfigureSet(). +// +//***************************************************************************** +extern uint32_t PRCMInfClockConfigureGet(uint32_t ui32PowerMode); + +//***************************************************************************** +// +//! \brief Request a power off of the MCU voltage domain. +//! +//! Use this function to request a power off of the entire MCU voltage domain. +//! This request will have no affect until deepsleep mode is requested. +//! +//! \return None +//! +//! \sa \ref PRCMDeepSleep(), \ref PRCMMcuPowerOffCancel() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMMcuPowerOff(void) +{ + // Assert the power off request signal. + HWREGBITW(PRCM_BASE + PRCM_O_VDCTL, PRCM_VDCTL_MCU_VD_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Cancel a request for a power off of the MCU voltage domain. +//! +//! Use this function to cancel a request for power off of the entire MCU +//! voltage domain. This could be relevant if a transition to power down is +//! regretted and an application must backtrack. +//! +//! \return None +//! +//! \sa \ref PRCMDeepSleep(), \ref PRCMMcuPowerOff() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMMcuPowerOffCancel(void) +{ + // Assert the power off request signal. + HWREGBITW(PRCM_BASE + PRCM_O_VDCTL, PRCM_VDCTL_MCU_VD_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Assert or de-assert a request for the uLDO. +//! +//! Use this function to request to switch to the micro Low Voltage Dropout +//! regulator (uLDO). The uLDO has a much lower capacity for supplying power +//! to the system. It is therefore imperative and solely the programmers +//! responsibility to ensure that a sufficient amount of peripheral modules +//! have been turned of before requesting a switch to the uLDO. +//! +//! \note Asserting this bit has no effect until: +//! 1. FLASH has accepted to be powered down +//! 2. Deepsleep must be asserted +//! +//! \param ui32Enable +//! - 0 : Disable uLDO request +//! - 1 : Enable uLDO request +//! +//! \return None +//! +//! \sa \ref PRCMDeepSleep() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMMcuUldoConfigure(uint32_t ui32Enable) +{ + // Enable or disable the uLDO request signal. + HWREGBITW(PRCM_BASE + PRCM_O_VDCTL, PRCM_VDCTL_ULDO_BITN) = ui32Enable; +} + +//***************************************************************************** +// +//! \brief Setup the clock division factor for the GP-Timer domain. +//! +//! Use this function to set up the clock division factor on the GP-Timer. +//! +//! The division rate will be constant and ungated for Run / Sleep / DeepSleep mode when +//! it is slower than PRCM_GPTCLKDIV_RATIO setting. +//! When set faster than PRCM_GPTCLKDIV_RATIO setting PRCM_GPTCLKDIV_RATIO will be used. +//! Note that the register will contain the written content even though the setting is +//! faster than PRCM_GPTCLKDIV_RATIO setting. +//! +//! \note For change to take effect, \ref PRCMLoadSet() needs to be called +//! +//! \param clkDiv is the division factor to set. +//! The argument must be only one of the following values: +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_4 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_16 +//! - \ref PRCM_CLOCK_DIV_32 +//! - \ref PRCM_CLOCK_DIV_64 +//! - \ref PRCM_CLOCK_DIV_128 +//! - \ref PRCM_CLOCK_DIV_256 +//! +//! \return None +//! +//! \sa \ref PRCMGPTimerClockDivisionGet() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMGPTimerClockDivisionSet( uint32_t clkDiv ) +{ + ASSERT( clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256 ); + + HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ) = clkDiv; +} + +//***************************************************************************** +// +//! \brief Get the clock division factor for the GP-Timer domain. +//! +//! Use this function to get the clock division factor set for the GP-Timer. +//! +//! \return Returns one of the following values: +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_4 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_16 +//! - \ref PRCM_CLOCK_DIV_32 +//! - \ref PRCM_CLOCK_DIV_64 +//! - \ref PRCM_CLOCK_DIV_128 +//! - \ref PRCM_CLOCK_DIV_256 +//! +//! \sa \ref PRCMGPTimerClockDivisionSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +PRCMGPTimerClockDivisionGet( void ) +{ + return ( HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV )); +} + + +//***************************************************************************** +// +//! \brief Enable the audio clock generation. +//! +//! Use this function to enable the audio clock generation. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMAudioClockEnable(void) +{ + // Enable the audio clock generation. + HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disable the audio clock generation. +//! +//! Use this function to disable the audio clock generation. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMAudioClockDisable(void) +{ + // Disable the audio clock generation + HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Configure the audio clock generation. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Use this function to set the sample rate when using internal audio clock +//! generation for the I2S module. +//! +//! \note While other clocks are possible, the stability of the four sample +//! rates defined here are only guaranteed if the clock input to the I2S module +//! is 48MHz. +//! +//! \param ui32ClkConfig is the audio clock configuration. +//! The parameter is a bitwise OR'ed value consisting of: +//! - Phase +//! - \ref PRCM_WCLK_SINGLE_PHASE +//! - \ref PRCM_WCLK_DUAL_PHASE +//! - Clock polarity +//! - \ref PRCM_WCLK_NEG_EDGE +//! - \ref PRCM_WCLK_POS_EDGE +//! \param ui32SampleRate is the desired audio clock sample rate. +//! The supported sample rate configurations are: +//! - \ref I2S_SAMPLE_RATE_16K +//! - \ref I2S_SAMPLE_RATE_24K +//! - \ref I2S_SAMPLE_RATE_32K +//! - \ref I2S_SAMPLE_RATE_48K +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockConfigSetOverride() +// +//***************************************************************************** +#ifndef DEPRECATED +extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, + uint32_t ui32SampleRate); +#endif + +//***************************************************************************** +// +//! \brief Configure the audio clock generation with manual setting of clock divider. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Use this function to set the audio clock divider values manually. +//! +//! \note See hardware documentation before setting audio clock dividers manually. +//! +//! \param ui32ClkConfig is the audio clock configuration. +//! The parameter is a bitwise OR'ed value consisting of: +//! - Phase +//! - \ref PRCM_WCLK_SINGLE_PHASE +//! - \ref PRCM_WCLK_DUAL_PHASE +//! - Clock polarity +//! - \ref PRCM_WCLK_NEG_EDGE +//! - \ref PRCM_WCLK_POS_EDGE +//! \param ui32MstDiv is the desired master clock divider. +//! \param ui32WordDiv is the desired word clock divider. +//! \param ui32BitDiv is the desired bit clock divider. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockConfigSet() +// +//***************************************************************************** +#ifndef DEPRECATED +extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, + uint32_t ui32BitDiv, uint32_t ui32WordDiv); +#endif + +//***************************************************************************** +// +//! \brief Configure the audio clocks for I2S module. +//! +//! \note See hardware documentation before setting audio clock dividers. +//! This is user's responsability to provide valid clock dividers. +//! +//! \param ui8SamplingEdge Define the clock polarity: +//! - \ref PRCM_I2S_WCLK_NEG_EDGE +//! - \ref PRCM_I2S_WCLK_POS_EDGE +//! \param ui8WCLKPhase Define I2S phase used +//! - PRCM_I2S_WCLK_SINGLE_PHASE +//! - PRCM_I2S_WCLK_DUAL_PHASE +//! - PRCM_I2S_WCLK_USER_DEF +//! \param ui32MstDiv is the desired master clock divider. +//! \param ui32BitDiv is the desired bit clock divider. +//! \param ui32WordDiv is the desired word clock divider. +//! +//! \return None +//! +//***************************************************************************** +extern void PRCMAudioClockConfigOverride + (uint8_t ui8SamplingEdge, + uint8_t ui8WCLKPhase, + uint32_t ui32MstDiv, + uint32_t ui32BitDiv, + uint32_t ui32WordDiv); + +//***************************************************************************** +// +//! \brief Configure the audio clocks to be internally generated. +//! +//! Use this function to set the audio clocks as internal. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockExternalSource() +// +//***************************************************************************** +extern void PRCMAudioClockInternalSource(void); + +//***************************************************************************** +// +//! \brief Configure the audio clocks to be externally generated. +//! +//! Use this function to set the audio clocks as external. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockInternalSource() +// +//***************************************************************************** +extern void PRCMAudioClockExternalSource(void); + +//***************************************************************************** +// +//! \brief Use this function to synchronize the load settings. +//! +//! Most of the clock settings in the PRCM module should be updated +//! synchronously. This is ensured by the implementation of a load registers +//! that, when written to, will let the previous written update values for all +//! the relevant registers propagate through to hardware. +//! +//! The functions that require a synchronization of the clock settings are: +//! - \ref PRCMAudioClockConfigSet() +//! - \ref PRCMAudioClockConfigSetOverride() +//! - \ref PRCMAudioClockDisable() +//! - \ref PRCMDomainEnable() +//! - \ref PRCMDomainDisable() +//! - \ref PRCMPeripheralRunEnable() +//! - \ref PRCMPeripheralRunDisable() +//! - \ref PRCMPeripheralSleepEnable() +//! - \ref PRCMPeripheralSleepDisable() +//! - \ref PRCMPeripheralDeepSleepEnable() +//! - \ref PRCMPeripheralDeepSleepDisable() +//! +//! \return None +//! +//! \sa \ref PRCMLoadGet() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMLoadSet(void) +{ + // Enable the update of all load related registers. + HWREG(PRCM_NONBUF_BASE + PRCM_O_CLKLOADCTL) = PRCM_CLKLOADCTL_LOAD; +} + +//***************************************************************************** +// +//! \brief Check if any of the load sensitive register has been updated. +//! +//! \return Returns status of the load sensitive register: +//! - \c true : No registers have changed since the last load. +//! - \c false : Any register has changed. +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +__STATIC_INLINE bool +PRCMLoadGet(void) +{ + // Return the load status. + return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? + true : false); +} + +//***************************************************************************** +// +//! \brief Enable clock domains in the MCU voltage domain. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \note Clocks will only be running if the domain is powered. +//! +//! \param ui32Domains is a bit mask containing the clock domains to enable. +//! The independent clock domains inside the MCU voltage domain which can be +//! configured are: +//! - \ref PRCM_DOMAIN_RFCORE +//! - \ref PRCM_DOMAIN_VIMS +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMDomainEnable(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Enable the clock domain(s). + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = PRCM_RFCCLKG_CLK_EN; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = PRCM_VIMSCLKG_CLK_EN_M; + } +} + +//***************************************************************************** +// +//! \brief Disable clock domains in the MCU voltage domain. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \note Clocks will only be running if the domain is powered. +//! +//! \param ui32Domains is a bit mask containing the clock domains to disable. +//! The independent clock domains inside the MCU voltage domain are: +//! - \ref PRCM_DOMAIN_RFCORE +//! - \ref PRCM_DOMAIN_VIMS +//! +//! \return None +//! +//! \sa PRCMDomainEnable() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMDomainDisable(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Disable the power domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = 0x0; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = 0x0; + } +} + +//***************************************************************************** +// +//! \brief Turn power on in power domains in the MCU domain. +//! +//! Use this function to turn on power domains inside the MCU voltage domain. +//! +//! Power on and power off request has different implications for the +//! different power domains. +//! - RF Core power domain: +//! - Power On : Domain is on or in the process of turning on. +//! - Power Off : Domain is powered down when System CPU is in deep sleep. The third +//! option for the RF Core is to power down when the it is idle. +//! This can be set using \b PRCMRfPowerDownWhenIdle() +//! - SERIAL power domain: +//! - Power on : Domain is powered on. +//! - Power off : Domain is powered off. +//! - PERIPHERIAL power domain: +//! - Power on : Domain is powered on. +//! - Power off : Domain is powered off. +//! - VIMS power domain: +//! - Power On : Domain is powered if Bus domain is powered. +//! - Power Off : Domain is only powered when CPU domain is on. +//! - BUS power domain: +//! - Power On : Domain is on. +//! - Power Off : Domain is on if requested by RF Core or if CPU domain is on. +//! - CPU power domain: +//! - Power On : Domain is on. +//! - Power Off : Domain is powering down if System CPU is idle. This will also +//! initiate a power down of the SRAM and BUS power domains, unless +//! RF Core is requesting them to be on. +//! +//! \note After a call to this function the status of the power domain should +//! be checked using either \ref PRCMPowerDomainStatus(). +//! Any write operation to a power domain which is still not operational can +//! result in unexpected behavior. +//! +//! \param ui32Domains determines which power domains to turn on. +//! The domains that can be turned on/off are: +//! - \b PRCM_DOMAIN_RFCORE : RF Core +//! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 +//! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 +//! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM +//! - \b PRCM_DOMAIN_SYSBUS +//! - \b PRCM_DOMAIN_CPU +//! +//! \return None +// +//***************************************************************************** +extern void PRCMPowerDomainOn(uint32_t ui32Domains); + +//***************************************************************************** +// +//! \brief Turn off a specific power domain. +//! +//! Use this function to power down domains inside the MCU voltage domain. +//! +//! \note For specifics regarding on/off configuration please see +//! \ref PRCMPowerDomainOn(). +//! +//! \param ui32Domains determines which domain to request a power down for. +//! The domains that can be turned on/off are: +//! - \b PRCM_DOMAIN_RFCORE : RF Core +//! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 +//! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 +//! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM +//! - \b PRCM_DOMAIN_SYSBUS +//! - \b PRCM_DOMAIN_CPU +//! +//! \return None +// +//***************************************************************************** +extern void PRCMPowerDomainOff(uint32_t ui32Domains); + +//***************************************************************************** +// +//! \brief Configure RF core to power down when idle. +//! +//! Use this function to configure the RF core to power down when Idle. This +//! is handled automatically in hardware if the RF Core reports that it is +//! idle. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMRfPowerDownWhenIdle(void) +{ + // Configure the RF power domain. + HWREGBITW(PRCM_BASE + PRCM_O_PDCTL0RFC, PRCM_PDCTL0RFC_ON_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Enables a peripheral in Run mode. +//! +//! Peripherals are enabled with this function. At power-up, some peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! \note The actual enabling of the peripheral may be delayed until some +//! time after this function returns. Care should be taken to ensure that the +//! peripheral is not accessed until it is enabled. +//! When enabling Timers always make sure that the division factor for the +//! \b PERBUSCPUCLK is set. This will guarantee that the timers run at a +//! continuous rate even if the \b SYSBUSCLK is gated. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to enable. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralRunEnable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Disables a peripheral in Run mode +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \note The actual disabling of the peripheral may be delayed until some +//! time after this function returns. Care should be taken by the user to +//! ensure that the peripheral is not accessed in this interval as this might +//! cause the system to hang. +//! +//! \param ui32Peripheral is the peripheral to disable. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralRunDisable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Enables a peripheral in sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into sleep mode. Since the clocking configuration of the device does +//! not change, any peripheral can safely continue operating while the +//! processor is in sleep mode, and can therefore wake the processor from sleep +//! mode. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to enable in sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralSleepEnable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Disables a peripheral in sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into sleep mode. Disabling peripherals while in sleep mode helps to lower +//! the current draw of the device. If enabled (via \ref PRCMPeripheralRunEnable()), +//! the peripheral will automatically resume operation when the processor +//! leaves sleep mode, maintaining its entire state from before sleep mode was +//! entered. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to disable in sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralSleepDisable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Enables a peripheral in deep-sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into deep-sleep mode. Since the clocking configuration of the device +//! may change, not all peripherals can safely continue operating while the +//! processor is in sleep mode. This in turn depends on the chosen power mode. +//! It is the responsibility of the caller to make sensible choices. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to enable in deep-sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Disables a peripheral in deep-sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps +//! to lower the current draw of the device, and can keep peripherals that +//! require a particular clock frequency from operating when the clock changes +//! as a result of entering deep-sleep mode. If enabled (via +//! \ref PRCMPeripheralRunEnable()), the peripheral will automatically resume +//! operation when the processor leaves deep-sleep mode, maintaining its entire +//! state from before deep-sleep mode was entered. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to disable in deep-sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Get the status for a specific power domain. +//! +//! Use this function to retrieve the current power status of one or more +//! power domains. +//! +//! \param ui32Domains determines which domain to get the power status for. +//! The parameter must be an OR'ed combination of one or several of: +//! - \ref PRCM_DOMAIN_RFCORE : RF Core. +//! - \ref PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 +//! - \ref PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 +//! +//! \return Returns status of the requested domains: +//! - \ref PRCM_DOMAIN_POWER_ON : The specified domains are \b all powered up. +//! This status is unconditional and the powered up status is guaranteed. +//! - \ref PRCM_DOMAIN_POWER_OFF : Any of the domains are powered down. +// +//***************************************************************************** +extern uint32_t PRCMPowerDomainStatus(uint32_t ui32Domains); + +//***************************************************************************** +// +//! \brief Return the access status of the RF Core. +//! +//! Use this function to check if the RF Core is on and ready to be accessed. +//! Accessing register or memories that are not powered and clocked will +//! cause a bus fault. +//! +//! \return Returns access status of the RF Core. +//! - \c true : RF Core can be accessed. +//! - \c false : RF Core domain is not ready for access. +// +//***************************************************************************** +__STATIC_INLINE bool +PRCMRfReady(void) +{ + // Return the ready status of the RF Core. + return ((HWREG(PRCM_BASE + PRCM_O_PDSTAT1RFC) & + PRCM_PDSTAT1RFC_ON) ? true : false); +} + + +//***************************************************************************** +// +//! \brief Put the processor into sleep mode. +//! +//! This function places the processor into sleep mode; it does not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via PRCMPeripheralSleepEnable() continue to operate and can wake up the +//! processor. +//! +//! \return None +//! +//! \sa \ref PRCMPeripheralSleepEnable() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMSleep(void) +{ + // Wait for an interrupt. + CPUwfi(); +} + +//***************************************************************************** +// +//! \brief Put the processor into deep-sleep mode. +//! +//! This function places the processor into deep-sleep mode; it does not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via \ref PRCMPeripheralDeepSleepEnable() continue to operate and can wake up +//! the processor. +//! +//! \return None +//! +//! \sa \ref PRCMPeripheralDeepSleepEnable() +// +//***************************************************************************** +extern void PRCMDeepSleep(void); + +//***************************************************************************** +// +//! \brief Enable CACHE RAM retention +//! +//! Enables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMCacheRetentionEnable( void ) +{ + HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) |= PRCM_RAMRETEN_VIMS_M; +} + +//***************************************************************************** +// +//! \brief Disable CACHE RAM retention +//! +//! Disables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMCacheRetentionDisable( void ) +{ + HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) &= ~PRCM_RAMRETEN_VIMS_M; +} + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_PRCMInfClockConfigureSet + #undef PRCMInfClockConfigureSet + #define PRCMInfClockConfigureSet ROM_PRCMInfClockConfigureSet + #endif + #ifdef ROM_PRCMInfClockConfigureGet + #undef PRCMInfClockConfigureGet + #define PRCMInfClockConfigureGet ROM_PRCMInfClockConfigureGet + #endif + #ifdef ROM_PRCMAudioClockConfigSet + #undef PRCMAudioClockConfigSet + #define PRCMAudioClockConfigSet ROM_PRCMAudioClockConfigSet + #endif + #ifdef ROM_PRCMAudioClockConfigSetOverride + #undef PRCMAudioClockConfigSetOverride + #define PRCMAudioClockConfigSetOverride ROM_PRCMAudioClockConfigSetOverride + #endif + #ifdef ROM_PRCMAudioClockInternalSource + #undef PRCMAudioClockInternalSource + #define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource + #endif + #ifdef ROM_PRCMAudioClockExternalSource + #undef PRCMAudioClockExternalSource + #define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource + #endif + #ifdef ROM_PRCMPowerDomainOn + #undef PRCMPowerDomainOn + #define PRCMPowerDomainOn ROM_PRCMPowerDomainOn + #endif + #ifdef ROM_PRCMPowerDomainOff + #undef PRCMPowerDomainOff + #define PRCMPowerDomainOff ROM_PRCMPowerDomainOff + #endif + #ifdef ROM_PRCMPeripheralRunEnable + #undef PRCMPeripheralRunEnable + #define PRCMPeripheralRunEnable ROM_PRCMPeripheralRunEnable + #endif + #ifdef ROM_PRCMPeripheralRunDisable + #undef PRCMPeripheralRunDisable + #define PRCMPeripheralRunDisable ROM_PRCMPeripheralRunDisable + #endif + #ifdef ROM_PRCMPeripheralSleepEnable + #undef PRCMPeripheralSleepEnable + #define PRCMPeripheralSleepEnable ROM_PRCMPeripheralSleepEnable + #endif + #ifdef ROM_PRCMPeripheralSleepDisable + #undef PRCMPeripheralSleepDisable + #define PRCMPeripheralSleepDisable ROM_PRCMPeripheralSleepDisable + #endif + #ifdef ROM_PRCMPeripheralDeepSleepEnable + #undef PRCMPeripheralDeepSleepEnable + #define PRCMPeripheralDeepSleepEnable ROM_PRCMPeripheralDeepSleepEnable + #endif + #ifdef ROM_PRCMPeripheralDeepSleepDisable + #undef PRCMPeripheralDeepSleepDisable + #define PRCMPeripheralDeepSleepDisable ROM_PRCMPeripheralDeepSleepDisable + #endif + #ifdef ROM_PRCMPowerDomainStatus + #undef PRCMPowerDomainStatus + #define PRCMPowerDomainStatus ROM_PRCMPowerDomainStatus + #endif + #ifdef ROM_PRCMDeepSleep + #undef PRCMDeepSleep + #define PRCMDeepSleep ROM_PRCMDeepSleep + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PRCM_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/pwr_ctrl.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/pwr_ctrl.c new file mode 100644 index 0000000..18289c5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/pwr_ctrl.c @@ -0,0 +1,80 @@ +/****************************************************************************** +* Filename: pwr_ctrl.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Power Control driver. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "pwr_ctrl.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef PowerCtrlSourceSet + #define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet +#endif + + +//***************************************************************************** +// +// Set (Request) the main power source +// +//***************************************************************************** +void +PowerCtrlSourceSet(uint32_t ui32PowerConfig) +{ + // Check the arguments. + ASSERT((ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) || + (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) || + (ui32PowerConfig == PWRCTRL_PWRSRC_ULDO)); + + // Configure the power. + if(ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) { + HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL) |= + (AON_SYSCTL_PWRCTL_DCDC_EN | AON_SYSCTL_PWRCTL_DCDC_ACTIVE); + } + else if (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) + { + HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL) &= + ~(AON_SYSCTL_PWRCTL_DCDC_EN | AON_SYSCTL_PWRCTL_DCDC_ACTIVE); + } + else + { + PRCMMcuUldoConfigure(true); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/pwr_ctrl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/pwr_ctrl.h new file mode 100644 index 0000000..4cbff1b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/pwr_ctrl.h @@ -0,0 +1,296 @@ +/****************************************************************************** +* Filename: pwr_ctrl.h +* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) +* Revision: 50165 +* +* Description: Defines and prototypes for the System Power Control. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup pwrctrl_api +//! @{ +// +//***************************************************************************** + +#ifndef __PWR_CTRL_H__ +#define __PWR_CTRL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_aon_sysctl.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_adi_2_refsys.h" +#include "debug.h" +#include "interrupt.h" +#include "osc.h" +#include "cpu.h" +#include "prcm.h" +#include "aon_ioc.h" +#include "adi.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet +#endif + +//***************************************************************************** +// +// Defines for the system power states +// +//***************************************************************************** +#define PWRCTRL_ACTIVE 0x00000001 +#define PWRCTRL_STANDBY 0x00000002 +#define PWRCTRL_POWER_DOWN 0x00000004 +#define PWRCTRL_SHUTDOWN 0x00000008 + +//***************************************************************************** +// +// Defines for the power configuration in the AON System Control 1.2 V +// +//***************************************************************************** +#define PWRCTRL_IOSEG3_ENABLE 0x00000800 +#define PWRCTRL_IOSEG2_ENABLE 0x00000400 +#define PWRCTRL_IOSEG3_DISABLE 0x00000200 +#define PWRCTRL_IOSEG2_DISABLE 0x00000100 +#define PWRCTRL_PWRSRC_DCDC 0x00000001 +#define PWRCTRL_PWRSRC_GLDO 0x00000000 +#define PWRCTRL_PWRSRC_ULDO 0x00000002 + +//***************************************************************************** +// +// The following are defines for the various reset source for the device. +// +//***************************************************************************** +#define PWRCTRL_RST_POWER_ON 0x00000000 // Reset by power on +#define PWRCTRL_RST_PIN 0x00000001 // Pin reset +#define PWRCTRL_RST_VDDS_BOD 0x00000002 // VDDS Brown Out Detect +#define PWRCTRL_RST_VDD_BOD 0x00000003 // VDD Brown Out Detect +#define PWRCTRL_RST_VDDR_BOD 0x00000004 // VDDR Brown Out Detect +#define PWRCTRL_RST_CLK_LOSS 0x00000005 // Clock loss Reset +#define PWRCTRL_RST_SW_PIN 0x00000006 // SYSRESET or pin reset +#define PWRCTRL_RST_WARM 0x00000007 // Reset via PRCM warm reset request + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Set (Request) the main power source. +//! +//! \note The system will never allow a switch to the \ref PWRCTRL_PWRSRC_ULDO +//! when in active mode. This is only allowed when the system is in lower power +//! mode where no code is executing and no peripherals are active. +//! Assuming that there is an external capacitor available for the +//! \ref PWRCTRL_PWRSRC_DCDC the system can dynamically switch back and forth +//! between the two when in active mode. +//! +//! \note The system will automatically switch to the GLDO / DCDC when waking +//! up from a low power mode. +//! +//! \param ui32PowerConfig is a bitmask indicating the target power source. +//! - \ref PWRCTRL_PWRSRC_DCDC +//! - \ref PWRCTRL_PWRSRC_GLDO +//! - \ref PWRCTRL_PWRSRC_ULDO +//! +//! \return None +// +//***************************************************************************** +extern void PowerCtrlSourceSet(uint32_t ui32PowerConfig); + +//***************************************************************************** +// +//! \brief Get the main power source. +//! +//! Use this function to retrieve the current active power source. +//! +//! When the System CPU is active it can never be powered by uLDO as this +//! is too weak a power source. +//! +//! \note Using the DCDC power supply requires an external inductor. +//! +//! \return Returns the main power source. +//! - \ref PWRCTRL_PWRSRC_DCDC +//! - \ref PWRCTRL_PWRSRC_GLDO +// +//***************************************************************************** +__STATIC_INLINE uint32_t +PowerCtrlSourceGet(void) +{ + uint32_t ui32PowerConfig; + + // Return the current power source + ui32PowerConfig = HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL); + if(ui32PowerConfig & AON_SYSCTL_PWRCTL_DCDC_ACTIVE) + { + return (PWRCTRL_PWRSRC_DCDC); + } + else + { + return (PWRCTRL_PWRSRC_GLDO); + } +} + +//***************************************************************************** +// +//! \brief OBSOLETE: Get the last known reset source of the system. +//! +//! \deprecated This function will be removed in a future release. +//! Use \ref SysCtrlResetSourceGet() instead. +//! +//! This function returns reset source but does not cover if waking up from shutdown. +//! This function can be seen as a subset of function \ref SysCtrlResetSourceGet() +//! and will be removed in a future release. +//! +//! \return Returns one of the known reset values. +//! The possible reset sources are: +//! - \ref PWRCTRL_RST_POWER_ON +//! - \ref PWRCTRL_RST_PIN +//! - \ref PWRCTRL_RST_VDDS_BOD +//! - \ref PWRCTRL_RST_VDD_BOD +//! - \ref PWRCTRL_RST_VDDR_BOD +//! - \ref PWRCTRL_RST_CLK_LOSS +//! - \ref PWRCTRL_RST_SW_PIN +//! - \ref PWRCTRL_RST_WARM +//! +//! \sa \ref SysCtrlResetSourceGet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +PowerCtrlResetSourceGet(void) +{ + // Get the reset source. + return (( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) & + AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> + AON_SYSCTL_RESETCTL_RESET_SRC_S ) ; +} + +//***************************************************************************** +// +//! \brief Enables pad sleep in order to latch device outputs before shutdown. +//! +//! \return None +//! +//! \sa \ref PowerCtrlPadSleepDisable() +// +//***************************************************************************** +__STATIC_INLINE void +PowerCtrlPadSleepEnable(void) +{ + HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_SLEEPCTL) = 0; + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! \brief Disables pad sleep in order to unlatch device outputs after wakeup from shutdown. +//! +//! This function must be called by the application after the device wakes up +//! from shutdown. +//! +//! \return None +//! +//! \sa \ref PowerCtrlPadSleepEnable() +// +//***************************************************************************** +__STATIC_INLINE void +PowerCtrlPadSleepDisable(void) +{ + HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_SLEEPCTL) = 1; + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_PowerCtrlSourceSet + #undef PowerCtrlSourceSet + #define PowerCtrlSourceSet ROM_PowerCtrlSourceSet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PWR_CTRL_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_cmd.h new file mode 100644 index 0000000..668d69b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_cmd.h @@ -0,0 +1,1129 @@ +/****************************************************************************** +* Filename: rf_ble_cmd.h +* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) +* Revision: 18052 +* +* Description: CC26x0 API for Bluetooth Low Energy commands +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __BLE_CMD_H +#define __BLE_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup ble_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_bleRadioOp_s rfc_bleRadioOp_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s rfc_CMD_BLE_SLAVE_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s rfc_CMD_BLE_MASTER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_s rfc_CMD_BLE_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s rfc_CMD_BLE_ADV_DIR_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s rfc_CMD_BLE_ADV_NC_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s rfc_CMD_BLE_ADV_SCAN_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s rfc_CMD_BLE_SCANNER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s rfc_CMD_BLE_INITIATOR_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s rfc_CMD_BLE_GENERIC_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s rfc_CMD_BLE_TX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s rfc_CMD_BLE_ADV_PAYLOAD_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s rfc_CMD_BLE5_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_bleMasterSlavePar_s rfc_bleMasterSlavePar_t; +typedef struct __RFC_STRUCT rfc_bleMasterPar_s rfc_bleMasterPar_t; +typedef struct __RFC_STRUCT rfc_bleSlavePar_s rfc_bleSlavePar_t; +typedef struct __RFC_STRUCT rfc_bleAdvPar_s rfc_bleAdvPar_t; +typedef struct __RFC_STRUCT rfc_bleScannerPar_s rfc_bleScannerPar_t; +typedef struct __RFC_STRUCT rfc_bleInitiatorPar_s rfc_bleInitiatorPar_t; +typedef struct __RFC_STRUCT rfc_bleGenericRxPar_s rfc_bleGenericRxPar_t; +typedef struct __RFC_STRUCT rfc_bleTxTestPar_s rfc_bleTxTestPar_t; +typedef struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s rfc_bleMasterSlaveOutput_t; +typedef struct __RFC_STRUCT rfc_bleAdvOutput_s rfc_bleAdvOutput_t; +typedef struct __RFC_STRUCT rfc_bleScannerOutput_s rfc_bleScannerOutput_t; +typedef struct __RFC_STRUCT rfc_bleInitiatorOutput_s rfc_bleInitiatorOutput_t; +typedef struct __RFC_STRUCT rfc_bleGenericRxOutput_s rfc_bleGenericRxOutput_t; +typedef struct __RFC_STRUCT rfc_bleTxTestOutput_s rfc_bleTxTestOutput_t; +typedef struct __RFC_STRUCT rfc_bleWhiteListEntry_s rfc_bleWhiteListEntry_t; +typedef struct __RFC_STRUCT rfc_bleRxStatus_s rfc_bleRxStatus_t; + +//! \addtogroup bleRadioOp +//! @{ +struct __RFC_STRUCT rfc_bleRadioOp_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + uint8_t* pParams; //!< Pointer to command specific parameter structure + uint8_t* pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_SLAVE +//! @{ +#define CMD_BLE_SLAVE 0x1801 +//! BLE Slave Command +struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s { + uint16_t commandNo; //!< The command ID number 0x1801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleSlavePar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_MASTER +//! @{ +#define CMD_BLE_MASTER 0x1802 +//! BLE Master Command +struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s { + uint16_t commandNo; //!< The command ID number 0x1802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleMasterPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV +//! @{ +#define CMD_BLE_ADV 0x1803 +//! BLE Connectable Undirected Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_s { + uint16_t commandNo; //!< The command ID number 0x1803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_DIR +//! @{ +#define CMD_BLE_ADV_DIR 0x1804 +//! BLE Connectable Directed Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s { + uint16_t commandNo; //!< The command ID number 0x1804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_NC +//! @{ +#define CMD_BLE_ADV_NC 0x1805 +//! BLE Non-Connectable Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s { + uint16_t commandNo; //!< The command ID number 0x1805 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_SCAN +//! @{ +#define CMD_BLE_ADV_SCAN 0x1806 +//! BLE Scannable Undirected Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s { + uint16_t commandNo; //!< The command ID number 0x1806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_SCANNER +//! @{ +#define CMD_BLE_SCANNER 0x1807 +//! BLE Scanner Command +struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s { + uint16_t commandNo; //!< The command ID number 0x1807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleScannerPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleScannerOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_INITIATOR +//! @{ +#define CMD_BLE_INITIATOR 0x1808 +//! BLE Initiator Command +struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s { + uint16_t commandNo; //!< The command ID number 0x1808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleInitiatorPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleInitiatorOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_GENERIC_RX +//! @{ +#define CMD_BLE_GENERIC_RX 0x1809 +//! BLE Generic Receiver Command +struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s { + uint16_t commandNo; //!< The command ID number 0x1809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleGenericRxPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleGenericRxOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_TX_TEST +//! @{ +#define CMD_BLE_TX_TEST 0x180A +//! BLE PHY Test Transmitter Command +struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x180A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleTxTestPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleTxTestOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_PAYLOAD +//! @{ +#define CMD_BLE_ADV_PAYLOAD 0x1001 +//! BLE Update Advertising Payload Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s { + uint16_t commandNo; //!< The command ID number 0x1001 + uint8_t payloadType; //!< \brief 0: Advertising data
+ //!< 1: Scan response data + uint8_t newLen; //!< Length of the new payload + uint8_t* pNewData; //!< Pointer to the buffer containing the new data + rfc_bleAdvPar_t *pParams; //!< Pointer to the parameter structure to update +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_RADIO_SETUP +//! @{ +#define CMD_BLE5_RADIO_SETUP 0x1820 +//! Define only for compatibility with CC26XXR2F family. Command will result in error if sent. +struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s { + uint8_t dummy0; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleMasterSlavePar +//! @{ +struct __RFC_STRUCT rfc_bleMasterSlavePar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleMasterPar +//! @{ +//! Parameter structure for master (CMD_BLE_MASTER) + +struct __RFC_STRUCT rfc_bleMasterPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleSlavePar +//! @{ +//! Parameter structure for slave (CMD_BLE_SLAVE) + +struct __RFC_STRUCT rfc_bleSlavePar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first + //!< receive operation + uint16_t __dummy0; + uint8_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleAdvPar +//! @{ +//! Parameter structure for advertiser (CMD_BLE_ADV*) + +struct __RFC_STRUCT rfc_bleAdvPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t advFilterPolicy:2; //!< \brief Advertiser filter policy
+ //!< 0: Process scan and connect requests from all devices
+ //!< 1: Process connect requests from all devices and only scan requests from + //!< devices that are in the white list
+ //!< 2: Process scan requests from all devices and only connect requests from + //!< devices that are in the white list
+ //!< 3: Process scan and connect requests only from devices in the white list + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType:1; //!< Directed advertiser: The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t :2; + uint8_t rpaMode:1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } advConfig; + uint8_t advLen; //!< Size of advertiser data + uint8_t scanRspLen; //!< Size of scan response data + uint8_t* pAdvData; //!< Pointer to buffer containing ADV*_IND data + uint8_t* pScanRspData; //!< Pointer to buffer containing SCAN_RSP data + uint16_t* pDeviceAddress; //!< Pointer to device address used for this device + rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list or peer address (directed advertiser) + uint16_t __dummy0; + uint8_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the advertiser event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< advertiser event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleScannerPar +//! @{ +//! Parameter structure for scanner (CMD_BLE_SCANNER) + +struct __RFC_STRUCT rfc_bleScannerPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t scanFilterPolicy:1; //!< \brief Scanning filter policy
+ //!< 0: Accept all advertisement packets
+ //!< 1: Accept only advertisement packets from devices where the advertiser's address + //!< is in the White list. + uint8_t bActiveScan:1; //!< \brief 0: Passive scan
+ //!< 1: Active scan + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t :1; + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t bAutoWlIgnore:1; //!< 1: Automatically set ignore bit in white list + uint8_t bEndOnRpt:1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
+ //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP + uint8_t rpaMode:1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } scanConfig; + uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure + uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth 4.0 spec + struct { + uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure + uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit + //!< not changed + uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not + //!< changed + } backoffPar; + uint8_t scanReqLen; //!< Size of scan request data + uint8_t* pScanReqData; //!< Pointer to buffer containing SCAN_REQ data + uint16_t* pDeviceAddress; //!< Pointer to device address used for this device + rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list + uint16_t __dummy0; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleInitiatorPar +//! @{ +//! Parameter structure for initiator (CMD_BLE_INITIATOR) + +struct __RFC_STRUCT rfc_bleInitiatorPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t bUseWhiteList:1; //!< \brief Initiator filter policy
+ //!< 0: Use specific peer address
+ //!< 1: Use white list + uint8_t bDynamicWinOffset:1; //!< \brief 0: No dynamic WinOffset insertion
+ //!< 1: Use dynamic WinOffset insertion + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType:1; //!< The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + } initConfig; + uint8_t __dummy0; + uint8_t connectReqLen; //!< Size of connect request data + uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_REQ + uint16_t* pDeviceAddress; //!< Pointer to device address used for this device + rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list or peer address + ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. + //!< Set to the calculated value if a connection is made and to the next possible connection + //!< time if not. + uint16_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleGenericRxPar +//! @{ +//! Parameter structure for generic Rx (CMD_BLE_GENERIC_RX) + +struct __RFC_STRUCT rfc_bleGenericRxPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue. May be NULL; if so, received packets are not stored + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + uint8_t bRepeat; //!< \brief 0: End operation after receiving a packet
+ //!< 1: Restart receiver after receiving a packet + uint16_t __dummy0; + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Rx operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleTxTestPar +//! @{ +//! Parameter structure for Tx test (CMD_BLE_TX_TEST) + +struct __RFC_STRUCT rfc_bleTxTestPar_s { + uint16_t numPackets; //!< \brief Number of packets to transmit
+ //!< 0: Transmit unlimited number of packets + uint8_t payloadLength; //!< The number of payload bytes in each packet. + uint8_t packetType; //!< \brief The packet type to be used, encoded according to the Bluetooth 4.0 spec, Volume 2, Part E, + //!< Section 7.8.29 + ratmr_t period; //!< Number of radio timer cycles between the start of each packet + struct { + uint8_t bOverrideDefault:1; //!< \brief 0: Use default packet encoding
+ //!< 1: Override packet contents + uint8_t bUsePrbs9:1; //!< \brief If bOverride is 1:
+ //!< 1: Use PRBS9 encoding of packet + uint8_t bUsePrbs15:1; //!< \brief If bOverride is 1:
+ //!< 1: Use PRBS15 encoding of packet + } config; + uint8_t byteVal; //!< If config.bOverride is 1, value of each byte to be sent + uint8_t __dummy0; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Test Tx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Test Tx operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleMasterSlaveOutput +//! @{ +//! Output structure for master and slave (CMD_BLE_MASTER and CMD_BLE_SLAVE) + +struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s { + uint8_t nTx; //!< \brief Total number of packets (including auto-empty and retransmissions) that have been + //!< transmitted + uint8_t nTxAck; //!< Total number of transmitted packets (including auto-empty) that have been ACK'ed + uint8_t nTxCtrl; //!< Number of unique LL control packets from the Tx queue that have been transmitted + uint8_t nTxCtrlAck; //!< Number of LL control packets from the Tx queue that have been finished (ACK'ed) + uint8_t nTxCtrlAckAck; //!< \brief Number of LL control packets that have been ACK'ed and where an ACK has been sent in + //!< response + uint8_t nTxRetrans; //!< Number of retransmissions that has been done + uint8_t nTxEntryDone; //!< Number of packets from the Tx queue that have been finished (ACK'ed) + uint8_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint8_t nRxCtrl; //!< Number of LL control packets that have been received with CRC OK and not ignored + uint8_t nRxCtrlAck; //!< \brief Number of LL control packets that have been received with CRC OK and not ignored, and + //!< then ACK'ed + uint8_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< \brief Number of packets that have been received with CRC OK and ignored due to repeated + //!< sequence number + uint8_t nRxEmpty; //!< Number of packets that have been received with CRC OK and no payload + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + struct { + uint8_t bTimeStampValid:1; //!< 1 if a valid time stamp has been written to timeStamp; 0 otherwise + uint8_t bLastCrcErr:1; //!< 1 if the last received packet had CRC error; 0 otherwise + uint8_t bLastIgnored:1; //!< 1 if the last received packet with CRC OK was ignored; 0 otherwise + uint8_t bLastEmpty:1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise + uint8_t bLastCtrl:1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise + uint8_t bLastMd:1; //!< 1 if the last received packet with CRC OK had MD = 1; 0 otherwise + uint8_t bLastAck:1; //!< \brief 1 if the last received packet with CRC OK was an ACK of a transmitted packet; + //!< 0 otherwise + } pktStatus; + ratmr_t timeStamp; //!< Slave operation: Time stamp of first received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleAdvOutput +//! @{ +//! Output structure for advertiser (CMD_BLE_ADV*) + +struct __RFC_STRUCT rfc_bleAdvOutput_s { + uint16_t nTxAdvInd; //!< Number of ADV*_IND packets completely transmitted + uint8_t nTxScanRsp; //!< Number of SCAN_RSP packets transmitted + uint8_t nRxScanReq; //!< Number of SCAN_REQ packets received OK and not ignored + uint8_t nRxConnectReq; //!< Number of CONNECT_REQ packets received OK and not ignored + uint8_t __dummy0; + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxIgnored; //!< Number of packets received with CRC OK, but ignored + uint8_t nRxBufFull; //!< Number of packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet + ratmr_t timeStamp; //!< Time stamp of the last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleScannerOutput +//! @{ +//! Output structure for scanner (CMD_BLE_SCANNER) + +struct __RFC_STRUCT rfc_bleScannerOutput_s { + uint16_t nTxScanReq; //!< Number of transmitted SCAN_REQ packets + uint16_t nBackedOffScanReq; //!< Number of SCAN_REQ packets not sent due to backoff procedure + uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint16_t nRxScanRspOk; //!< Number of SCAN_RSP packets received with CRC OK and not ignored + uint16_t nRxScanRspIgnored; //!< Number of SCAN_RSP packets received with CRC OK, but ignored + uint16_t nRxScanRspNok; //!< Number of SCAN_RSP packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + uint8_t nRxScanRspBufFull; //!< Number of SCAN_RSP packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last successfully received ADV*_IND packet that was not ignored +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleInitiatorOutput +//! @{ +//! Output structure for initiator (CMD_BLE_INITIATOR) + +struct __RFC_STRUCT rfc_bleInitiatorOutput_s { + uint8_t nTxConnectReq; //!< Number of transmitted CONNECT_REQ packets + uint8_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet + ratmr_t timeStamp; //!< Time stamp of the received ADV*_IND packet that caused transmission of CONNECT_REQ +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleGenericRxOutput +//! @{ +//! Output structure for generic Rx (CMD_BLE_GENERIC_RX) + +struct __RFC_STRUCT rfc_bleGenericRxOutput_s { + uint16_t nRxOk; //!< Number of packets received with CRC OK + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< The RSSI of the last received packet + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleTxTestOutput +//! @{ +//! Output structure for Tx test (CMD_BLE_TX_TEST) + +struct __RFC_STRUCT rfc_bleTxTestOutput_s { + uint16_t nTx; //!< Number of packets transmitted +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleWhiteListEntry +//! @{ +//! White list entry structure + +struct __RFC_STRUCT rfc_bleWhiteListEntry_s { + uint8_t size; //!< Number of while list entries. Used in the first entry of the list only + struct { + uint8_t bEnable:1; //!< 1 if the entry is in use, 0 if the entry is not in use + uint8_t addrType:1; //!< The type address in the entry -- public (0) or random (1) + uint8_t bWlIgn:1; //!< \brief 1 if the entry is to be ignored by a scanner, 0 otherwise. Used to mask out + //!< entries that have already been scanned and reported. + uint8_t :1; + uint8_t bIrkValid:1; //!< \brief 1 if a valid IRK exists, so that the entry is to be ignored by an initiator, + //!< 0 otherwise + } conf; + uint16_t address; //!< Least significant 16 bits of the address contained in the entry + uint32_t addressHi; //!< Most significant 32 bits of the address contained in the entry +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleRxStatus +//! @{ +//! Receive status byte that may be appended to message in receive buffer + +struct __RFC_STRUCT rfc_bleRxStatus_s { + struct { + uint8_t channel:6; //!< \brief The channel on which the packet was received, provided channel is in the range + //!< 0--39; otherwise 0x3F + uint8_t bIgnore:1; //!< 1 if the packet is marked as ignored, 0 otherwise + uint8_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_mailbox.h new file mode 100644 index 0000000..4158977 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_mailbox.h @@ -0,0 +1,68 @@ +/****************************************************************************** +* Filename: rf_ble_mailbox.h +* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) +* Revision: 18032 +* +* Description: Definitions for BLE interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _BLE_MAILBOX_H +#define _BLE_MAILBOX_H + +/// \name Radio operation status +///@{ +/// \name Operation finished normally +///@{ +#define BLE_DONE_OK 0x1400 ///< Operation ended normally +#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window +#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx +#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other) +#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_REQ received or transmitted +#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded +#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger +#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command +#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command +///@} +/// \name Operation finished with error +///@{ +#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter +#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator) +#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attemted when not in BLE mode +#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attemted without frequency synth configured +#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time +#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation +#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation +///@} +///@} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_common_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_common_cmd.h new file mode 100644 index 0000000..0a0dba6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_common_cmd.h @@ -0,0 +1,942 @@ +/****************************************************************************** +* Filename: rf_common_cmd.h +* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) +* Revision: 18052 +* +* Description: CC26x0 API for common/generic commands +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __COMMON_CMD_H +#define __COMMON_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup common_cmd +//! @{ + +#include +#include "rf_mailbox.h" + +typedef struct __RFC_STRUCT rfc_command_s rfc_command_t; +typedef struct __RFC_STRUCT rfc_radioOp_s rfc_radioOp_t; +typedef struct __RFC_STRUCT rfc_CMD_NOP_s rfc_CMD_NOP_t; +typedef struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s rfc_CMD_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_s rfc_CMD_FS_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_OFF_s rfc_CMD_FS_OFF_t; +typedef struct __RFC_STRUCT rfc_CMD_RX_TEST_s rfc_CMD_RX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_TX_TEST_s rfc_CMD_TX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s rfc_CMD_SYNC_STOP_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s rfc_CMD_SYNC_START_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_COUNT_s rfc_CMD_COUNT_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s rfc_CMD_FS_POWERUP_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s rfc_CMD_FS_POWERDOWN_t; +typedef struct __RFC_STRUCT rfc_CMD_SCH_IMM_s rfc_CMD_SCH_IMM_t; +typedef struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s rfc_CMD_COUNT_BRANCH_t; +typedef struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s rfc_CMD_PATTERN_CHECK_t; +typedef struct __RFC_STRUCT rfc_CMD_ABORT_s rfc_CMD_ABORT_t; +typedef struct __RFC_STRUCT rfc_CMD_STOP_s rfc_CMD_STOP_t; +typedef struct __RFC_STRUCT rfc_CMD_GET_RSSI_s rfc_CMD_GET_RSSI_t; +typedef struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s rfc_CMD_UPDATE_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_TRIGGER_s rfc_CMD_TRIGGER_t; +typedef struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s rfc_CMD_GET_FW_INFO_t; +typedef struct __RFC_STRUCT rfc_CMD_START_RAT_s rfc_CMD_START_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_PING_s rfc_CMD_PING_t; +typedef struct __RFC_STRUCT rfc_CMD_READ_RFREG_s rfc_CMD_READ_RFREG_t; +typedef struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s rfc_CMD_ADD_DATA_ENTRY_t; +typedef struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s rfc_CMD_REMOVE_DATA_ENTRY_t; +typedef struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s rfc_CMD_FLUSH_QUEUE_t; +typedef struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s rfc_CMD_CLEAR_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s rfc_CMD_REMOVE_PENDING_ENTRIES_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s rfc_CMD_SET_RAT_CMP_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s rfc_CMD_SET_RAT_CPT_t; +typedef struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s rfc_CMD_DISABLE_RAT_CH_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s rfc_CMD_SET_RAT_OUTPUT_t; +typedef struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s rfc_CMD_ARM_RAT_CH_t; +typedef struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s rfc_CMD_DISARM_RAT_CH_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s rfc_CMD_SET_TX_POWER_t; +typedef struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s rfc_CMD_UPDATE_FS_t; +typedef struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s rfc_CMD_BUS_REQUEST_t; + +//! \addtogroup command +//! @{ +struct __RFC_STRUCT rfc_command_s { + uint16_t commandNo; //!< The command ID number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup radioOp +//! @{ +//! Common definition for radio operation commands + +struct __RFC_STRUCT rfc_radioOp_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_NOP +//! @{ +#define CMD_NOP 0x0801 +//! No Operation Command +struct __RFC_STRUCT rfc_CMD_NOP_s { + uint16_t commandNo; //!< The command ID number 0x0801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_RADIO_SETUP +//! @{ +#define CMD_RADIO_SETUP 0x0802 +//! Radio Setup Command for Pre-Defined Schemes +struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x0802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t mode; //!< \brief The main mode to use
+ //!< 0x00: BLE
+ //!< 0x01: IEEE 802.15.4
+ //!< 0x02: 2 Mbps GFSK
+ //!< 0x05: 5 Mbps coded 8-FSK
+ //!< 0xFF: Keep existing mode; update overrides only
+ //!< Others: Reserved + uint8_t __dummy0; + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< \brief Transmit power + //!< Bits 0--5: IB + //!< Value to write to the PA power control field at 25 °C + //!< Bits 6--7: GC + //!< Value to write to the gain control of the 1st stage of the PA + //!< Bits 8--15: tempCoeff + //!< Temperature coefficient for IB. 0: No temperature compensation + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS +//! @{ +#define CMD_FS 0x0803 +//! Frequency Synthesizer Programming Command +struct __RFC_STRUCT rfc_CMD_FS_s { + uint16_t commandNo; //!< The command ID number 0x0803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to + struct { + uint8_t bTxMode:1; //!< \brief 0: Start synth in RX mode
+ //!< 1: Start synth in TX mode + uint8_t refFreq:6; //!< Reserved + } synthConf; + uint8_t __dummy0; //!< Reserved, always write 0 + uint8_t __dummy1; //!< Reserved + uint8_t __dummy2; //!< Reserved + uint16_t __dummy3; //!< Reserved +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS_OFF +//! @{ +#define CMD_FS_OFF 0x0804 +//! Command for Turning off Frequency Synthesizer +struct __RFC_STRUCT rfc_CMD_FS_OFF_s { + uint16_t commandNo; //!< The command ID number 0x0804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_RX_TEST +//! @{ +#define CMD_RX_TEST 0x0807 +//! Receiver Test Command +struct __RFC_STRUCT rfc_CMD_RX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x0807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bEnaFifo:1; //!< \brief 0: Do not enable FIFO in modem, so that received data is not available
+ //!< 1: Enable FIFO in modem -- the data must be read out by the application + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bNoSync:1; //!< \brief 0: Run sync search as normal for the configured mode
+ //!< 1: Write correlation thresholds to the maximum value to avoid getting sync + } config; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for receiver + ratmr_t endTime; //!< Time to end the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_TX_TEST +//! @{ +#define CMD_TX_TEST 0x0808 +//! Transmitter Test Command +struct __RFC_STRUCT rfc_CMD_TX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x0808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bUseCw:1; //!< \brief 0: Send modulated signal
+ //!< 1: Send continuous wave + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t whitenMode:2; //!< \brief 0: No whitening
+ //!< 1: Default whitening
+ //!< 2: PRBS-15
+ //!< 3: PRBS-32 + } config; + uint8_t __dummy0; + uint16_t txWord; //!< Value to send to the modem before whitening + uint8_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for transmitter + ratmr_t endTime; //!< Time to end the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SYNC_STOP_RAT +//! @{ +#define CMD_SYNC_STOP_RAT 0x0809 +//! Synchronize and Stop Radio Timer Command +struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s { + uint16_t commandNo; //!< The command ID number 0x0809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The returned RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SYNC_START_RAT +//! @{ +#define CMD_SYNC_START_RAT 0x080A +//! Synchrously Start Radio Timer Command +struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s { + uint16_t commandNo; //!< The command ID number 0x080A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero. This parameter is returned by CMD_SYNC_STOP_RAT +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_COUNT +//! @{ +#define CMD_COUNT 0x080B +//! Counter Command +struct __RFC_STRUCT rfc_CMD_COUNT_s { + uint16_t commandNo; //!< The command ID number 0x080B + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS_POWERUP +//! @{ +#define CMD_FS_POWERUP 0x080C +//! Power up Frequency Syntheszier Command +struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s { + uint16_t commandNo; //!< The command ID number 0x080C + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS_POWERDOWN +//! @{ +#define CMD_FS_POWERDOWN 0x080D +//! Power down Frequency Syntheszier Command +struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s { + uint16_t commandNo; //!< The command ID number 0x080D + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SCH_IMM +//! @{ +#define CMD_SCH_IMM 0x0810 +//! Run Immidiate Command as Radio Operation Command +struct __RFC_STRUCT rfc_CMD_SCH_IMM_s { + uint16_t commandNo; //!< The command ID number 0x0810 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t cmdrVal; //!< Value as would be written to CMDR + uint32_t cmdstaVal; //!< Value as would be returned in CMDSTA +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_COUNT_BRANCH +//! @{ +#define CMD_COUNT_BRANCH 0x0812 +//! Counter Command with Branch of Command Chain +struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s { + uint16_t commandNo; //!< The command ID number 0x0812 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero + rfc_radioOp_t *pNextOpIfOk; //!< Pointer to next operation if counter did not expire +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PATTERN_CHECK +//! @{ +#define CMD_PATTERN_CHECK 0x0813 +//! Command for Checking a Value in Memory aginst a Pattern +struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s { + uint16_t commandNo; //!< The command ID number 0x0813 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t operation:2; //!< \brief Operation to perform
+ //!< 0: True if value == compareVal
+ //!< 1: True if value < compareVal
+ //!< 2: True if value > compareVal
+ //!< 3: Reserved + uint16_t bByteRev:1; //!< \brief If 1, interchange the four bytes of the value, so that they are read + //!< most-significant-byte-first. + uint16_t bBitRev:1; //!< If 1, perform bit reversal of the value + uint16_t signExtend:5; //!< \brief 0: Treat value and compareVal as unsigned
+ //!< 1--31: Treat value and compareVal as signed, where the value + //!< gives the number of the most significant bit in the signed number. + uint16_t bRxVal:1; //!< \brief 0: Use pValue as a pointer
+ //!< 1: Use pValue as a signed offset to the start of the last + //!< committed RX entry element + } patternOpt; //!< Options for comparison + rfc_radioOp_t *pNextOpIfOk; //!< Pointer to next operation if comparison result was true + uint8_t* pValue; //!< Pointer to read from, or offset from last RX entry if patternOpt.bRxVal == 1 + uint32_t mask; //!< Bit mask to apply before comparison + uint32_t compareVal; //!< Value to compare to +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_ABORT +//! @{ +#define CMD_ABORT 0x0401 +//! Abort Running Radio Operation Command +struct __RFC_STRUCT rfc_CMD_ABORT_s { + uint16_t commandNo; //!< The command ID number 0x0401 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_STOP +//! @{ +#define CMD_STOP 0x0402 +//! Stop Running Radio Operation Command Gracefully +struct __RFC_STRUCT rfc_CMD_STOP_s { + uint16_t commandNo; //!< The command ID number 0x0402 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_GET_RSSI +//! @{ +#define CMD_GET_RSSI 0x0403 +//! Read RSSI Command +struct __RFC_STRUCT rfc_CMD_GET_RSSI_s { + uint16_t commandNo; //!< The command ID number 0x0403 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_UPDATE_RADIO_SETUP +//! @{ +#define CMD_UPDATE_RADIO_SETUP 0x0001 +//! Update Radio Settings Command +struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x0001 + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_TRIGGER +//! @{ +#define CMD_TRIGGER 0x0404 +//! Generate Command Trigger +struct __RFC_STRUCT rfc_CMD_TRIGGER_s { + uint16_t commandNo; //!< The command ID number 0x0404 + uint8_t triggerNo; //!< Command trigger number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_GET_FW_INFO +//! @{ +#define CMD_GET_FW_INFO 0x0002 +//! Request Information on the RF Core ROM Firmware +struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s { + uint16_t commandNo; //!< The command ID number 0x0002 + uint16_t versionNo; //!< Firmware version number + uint16_t startOffset; //!< The start of free RAM + uint16_t freeRamSz; //!< The size of free RAM + uint16_t availRatCh; //!< Bitmap of available RAT channels +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_START_RAT +//! @{ +#define CMD_START_RAT 0x0405 +//! Asynchronously Start Radio Timer Command +struct __RFC_STRUCT rfc_CMD_START_RAT_s { + uint16_t commandNo; //!< The command ID number 0x0405 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PING +//! @{ +#define CMD_PING 0x0406 +//! Respond with Command ACK Only +struct __RFC_STRUCT rfc_CMD_PING_s { + uint16_t commandNo; //!< The command ID number 0x0406 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_READ_RFREG +//! @{ +#define CMD_READ_RFREG 0x0601 +//! Read RF Core Hardware Register +struct __RFC_STRUCT rfc_CMD_READ_RFREG_s { + uint16_t commandNo; //!< The command ID number 0x0601 + uint16_t address; //!< The offset from the start of the RF core HW register bank (0x40040000) + uint32_t value; //!< Returned value of the register +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_ADD_DATA_ENTRY +//! @{ +#define CMD_ADD_DATA_ENTRY 0x0005 +//! Add Data Entry to Queue +struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s { + uint16_t commandNo; //!< The command ID number 0x0005 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to which the entry will be added + uint8_t* pEntry; //!< Pointer to the entry +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_REMOVE_DATA_ENTRY +//! @{ +#define CMD_REMOVE_DATA_ENTRY 0x0006 +//! Remove First Data Entry from Queue +struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s { + uint16_t commandNo; //!< The command ID number 0x0006 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure from which the entry will be removed + uint8_t* pEntry; //!< Pointer to the entry that was removed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FLUSH_QUEUE +//! @{ +#define CMD_FLUSH_QUEUE 0x0007 +//! Flush Data Queue +struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s { + uint16_t commandNo; //!< The command ID number 0x0007 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_CLEAR_RX +//! @{ +#define CMD_CLEAR_RX 0x0008 +//! Clear all RX Queue Entries +struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s { + uint16_t commandNo; //!< The command ID number 0x0008 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be cleared +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_REMOVE_PENDING_ENTRIES +//! @{ +#define CMD_REMOVE_PENDING_ENTRIES 0x0009 +//! Remove Pending Entries from Queue +struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s { + uint16_t commandNo; //!< The command ID number 0x0009 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_RAT_CMP +//! @{ +#define CMD_SET_RAT_CMP 0x000A +//! Set Radio Timer Channel in Compare Mode +struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s { + uint16_t commandNo; //!< The command ID number 0x000A + uint8_t ratCh; //!< The radio timer channel number + uint8_t __dummy0; + ratmr_t compareTime; //!< The time at which the compare occurs +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_RAT_CPT +//! @{ +#define CMD_SET_RAT_CPT 0x0603 +//! Set Radio Timer Channel in Capture Mode +struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s { + uint16_t commandNo; //!< The command ID number 0x0603 + struct { + uint16_t :3; + uint16_t inputSrc:5; //!< Input source indicator + uint16_t ratCh:4; //!< The radio timer channel number + uint16_t bRepeated:1; //!< \brief 0: Single capture mode
+ //!< 1: Repeated capture mode + uint16_t inputMode:2; //!< \brief Input mode:
+ //!< 0: Capture on rising edge
+ //!< 1: Capture on falling edge
+ //!< 2: Capture on both edges
+ //!< 3: Reserved + } config; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_DISABLE_RAT_CH +//! @{ +#define CMD_DISABLE_RAT_CH 0x0408 +//! Disable Radio Timer Channel +struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s { + uint16_t commandNo; //!< The command ID number 0x0408 + uint8_t ratCh; //!< The radio timer channel number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_RAT_OUTPUT +//! @{ +#define CMD_SET_RAT_OUTPUT 0x0604 +//! Set Radio Timer Output to a Specified Mode +struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s { + uint16_t commandNo; //!< The command ID number 0x0604 + struct { + uint16_t :2; + uint16_t outputSel:3; //!< Output event indicator + uint16_t outputMode:3; //!< \brief 0: Set output line low as default; and pulse on event. Duration of pulse is one RF Core clock period (ca. 41.67 ns).
+ //!< 1: Set output line high on event
+ //!< 2: Set output line low on event
+ //!< 3: Toggle (invert) output line state on event
+ //!< 4: Immediately set output line to low (does not change upon event)
+ //!< 5: Immediately set output line to high (does not change upon event)
+ //!< Others: Reserved + uint16_t ratCh:4; //!< The radio timer channel number + } config; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_ARM_RAT_CH +//! @{ +#define CMD_ARM_RAT_CH 0x0409 +//! Arm Radio Timer Channel +struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s { + uint16_t commandNo; //!< The command ID number 0x0409 + uint8_t ratCh; //!< The radio timer channel number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_DISARM_RAT_CH +//! @{ +#define CMD_DISARM_RAT_CH 0x040A +//! Disarm Radio Timer Channel +struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s { + uint16_t commandNo; //!< The command ID number 0x040A + uint8_t ratCh; //!< The radio timer channel number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_TX_POWER +//! @{ +#define CMD_SET_TX_POWER 0x0010 +//! Set Transmit Power +struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s { + uint16_t commandNo; //!< The command ID number 0x0010 + uint16_t txPower; //!< \brief New TX power setting + //!< Bits 0--5: IB + //!< Value to write to the PA power control field at 25 °C + //!< Bits 6--7: GC + //!< Value to write to the gain control of the 1st stage of the PA + //!< Bits 8--15: tempCoeff + //!< Temperature coefficient for IB. 0: No temperature compensation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_UPDATE_FS +//! @{ +#define CMD_UPDATE_FS 0x0011 +//! Set New Synthesizer Frequency without Recalibration +struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s { + uint16_t commandNo; //!< The command ID number 0x0011 + uint16_t __dummy0; + uint32_t __dummy1; + uint32_t __dummy2; + uint16_t __dummy3; + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BUS_REQUEST +//! @{ +#define CMD_BUS_REQUEST 0x040E +//! Request System Bus to be Availbale +struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s { + uint16_t commandNo; //!< The command ID number 0x040E + uint8_t bSysBusNeeded; //!< \brief 0: System bus may sleep
+ //!< 1: System bus access needed +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_data_entry.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_data_entry.h new file mode 100644 index 0000000..026ba9d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_data_entry.h @@ -0,0 +1,219 @@ +/****************************************************************************** +* Filename: rf_data_entry.h +* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) +* Revision: 18052 +* +* Description: Definition of API for data exchange +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __DATA_ENTRY_H +#define __DATA_ENTRY_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup data_entry +//! @{ + +#include +#include "rf_mailbox.h" + +typedef struct __RFC_STRUCT rfc_dataEntry_s rfc_dataEntry_t; +typedef struct __RFC_STRUCT rfc_dataEntryGeneral_s rfc_dataEntryGeneral_t; +typedef struct __RFC_STRUCT rfc_dataEntryMulti_s rfc_dataEntryMulti_t; +typedef struct __RFC_STRUCT rfc_dataEntryPointer_s rfc_dataEntryPointer_t; +typedef struct __RFC_STRUCT rfc_dataEntryPartial_s rfc_dataEntryPartial_t; + +//! \addtogroup dataEntry +//! @{ +struct __RFC_STRUCT rfc_dataEntry_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryGeneral +//! @{ +//! General data entry structure (type = 0) + +struct __RFC_STRUCT rfc_dataEntryGeneral_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t data; //!< First byte of the data array to be received or transmitted +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryMulti +//! @{ +//! Multi-element data entry structure (type = 1) + +struct __RFC_STRUCT rfc_dataEntryMulti_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint16_t numElements; //!< Number of entry elements committed in the entry + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryPointer +//! @{ +//! Pointer data entry structure (type = 2) + +struct __RFC_STRUCT rfc_dataEntryPointer_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryPartial +//! @{ +//! Partial read data entry structure (type = 3) + +struct __RFC_STRUCT rfc_dataEntryPartial_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + struct { + uint16_t numElements:13; //!< Number of entry elements committed in the entry + uint16_t bEntryOpen:1; //!< 1 if the entry contains an element that is still open for appending data + uint16_t bFirstCont:1; //!< 1 if the first element is a continuation of the last packet from the previous entry + uint16_t bLastCont:1; //!< 1 if the packet in the last element continues in the next entry + } pktStatus; + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_cmd.h new file mode 100644 index 0000000..02bd359 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_cmd.h @@ -0,0 +1,628 @@ +/****************************************************************************** +* Filename: rf_ieee_cmd.h +* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) +* Revision: 18052 +* +* Description: CC26x0 API for IEEE 802.15.4 commands +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __IEEE_CMD_H +#define __IEEE_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup ieee_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_s rfc_CMD_IEEE_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s rfc_CMD_IEEE_ED_SCAN_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_TX_s rfc_CMD_IEEE_TX_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s rfc_CMD_IEEE_CSMA_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s rfc_CMD_IEEE_RX_ACK_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s rfc_CMD_IEEE_ABORT_BG_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s rfc_CMD_IEEE_MOD_CCA_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s rfc_CMD_IEEE_MOD_FILT_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s rfc_CMD_IEEE_MOD_SRC_MATCH_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s rfc_CMD_IEEE_ABORT_FG_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s rfc_CMD_IEEE_STOP_FG_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s rfc_CMD_IEEE_CCA_REQ_t; +typedef struct __RFC_STRUCT rfc_ieeeRxOutput_s rfc_ieeeRxOutput_t; +typedef struct __RFC_STRUCT rfc_shortAddrEntry_s rfc_shortAddrEntry_t; +typedef struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s rfc_ieeeRxCorrCrc_t; + +//! \addtogroup CMD_IEEE_RX +//! @{ +#define CMD_IEEE_RX 0x2801 +//! IEEE 802.15.4 Receive Command +struct __RFC_STRUCT rfc_CMD_IEEE_RX_s { + uint16_t commandNo; //!< The command ID number 0x2801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to tune to in the start of the operation
+ //!< 0: Use existing channel
+ //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
+ //!< 60--207: Frequency is (2300 + channel) MHz
+ //!< Others: Reserved + struct { + uint8_t bAutoFlushCrc:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushIgn:1; //!< If 1, automatically remove packets that can be ignored according to frame filtering from Rx queue + uint8_t bIncludePhyHdr:1; //!< If 1, include the received PHY header field in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendCorrCrc:1; //!< If 1, append a correlation value and CRC result byte to the packet in the Rx queue + uint8_t bAppendSrcInd:1; //!< If 1, append an index from the source matching algorithm + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; + dataQueue_t* pRxQ; //!< Pointer to receive queue + rfc_ieeeRxOutput_t *pOutput; //!< Pointer to output structure (NULL: Do not store results) + struct { + uint16_t frameFiltEn:1; //!< \brief 0: Disable frame filtering
+ //!< 1: Enable frame filtering + uint16_t frameFiltStop:1; //!< \brief 0: Receive all packets to the end
+ //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. + uint16_t autoAckEn:1; //!< \brief 0: Disable auto ACK
+ //!< 1: Enable auto ACK. + uint16_t slottedAckEn:1; //!< \brief 0: Non-slotted ACK
+ //!< 1: Slotted ACK. + uint16_t autoPendEn:1; //!< \brief 0: Auto-pend disabled
+ //!< 1: Auto-pend enabled + uint16_t defaultPend:1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend + uint16_t bPendDataReqOnly:1; //!< \brief 0: Use auto-pend for any packet
+ //!< 1: Use auto-pend for data request packets only + uint16_t bPanCoord:1; //!< \brief 0: Device is not PAN coordinator
+ //!< 1: Device is PAN coordinator + uint16_t maxFrameVersion:2; //!< Reject frames where the frame version field in the FCF is greater than this value + uint16_t fcfReservedMask:3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero + uint16_t modifyFtFilter:2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
+ //!< 0: No modification
+ //!< 1: Invert MSB
+ //!< 2: Set MSB to 0
+ //!< 3: Set MSB to 1 + uint16_t bStrictLenFilter:1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
+ //!< 1: Accept only acknowledgement frames of length 5 + } frameFiltOpt; //!< Frame filtering options + struct { + uint8_t bAcceptFt0Beacon:1; //!< \brief Treatment of frames with frame type 000 (beacon):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt1Data:1; //!< \brief Treatment of frames with frame type 001 (data):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt2Ack:1; //!< \brief Treatment of frames with frame type 010 (ACK):
+ //!< 0: Reject, unless running ACK receive command
+ //!< 1: Always accept + uint8_t bAcceptFt3MacCmd:1; //!< \brief Treatment of frames with frame type 011 (MAC command):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt4Reserved:1; //!< \brief Treatment of frames with frame type 100 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt5Reserved:1; //!< \brief Treatment of frames with frame type 101 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt6Reserved:1; //!< \brief Treatment of frames with frame type 110 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt7Reserved:1; //!< \brief Treatment of frames with frame type 111 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + } frameTypes; //!< Frame types to receive in frame filtering + struct { + uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } ccaOpt; //!< CCA options + int8_t ccaRssiThr; //!< RSSI threshold for CCA + uint8_t __dummy0; + uint8_t numExtEntries; //!< Number of extended address entries + uint8_t numShortEntries; //!< Number of short address entries + uint32_t* pExtEntryList; //!< Pointer to list of extended address entries + uint32_t* pShortEntryList; //!< Pointer to list of short address entries + uint64_t localExtAddr; //!< The extended address of the local device + uint16_t localShortAddr; //!< The short address of the local device + uint16_t localPanID; //!< The PAN ID of the local device + uint16_t __dummy1; + uint8_t __dummy2; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx + //!< operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_ED_SCAN +//! @{ +#define CMD_IEEE_ED_SCAN 0x2802 +//! IEEE 802.15.4 Energy Detect Scan Command +struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s { + uint16_t commandNo; //!< The command ID number 0x2802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to tune to in the start of the operation
+ //!< 0: Use existing channel
+ //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
+ //!< 60--207: Frequency is (2300 + channel) MHz
+ //!< Others: Reserved + struct { + uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } ccaOpt; //!< CCA options + int8_t ccaRssiThr; //!< RSSI threshold for CCA + uint8_t __dummy0; + int8_t maxRssi; //!< The maximum RSSI recorded during the ED scan + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx + //!< operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_TX +//! @{ +#define CMD_IEEE_TX 0x2C01 +//! IEEE 802.15.4 Transmit Command +struct __RFC_STRUCT rfc_CMD_IEEE_TX_s { + uint16_t commandNo; //!< The command ID number 0x2C01 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bIncludePhyHdr:1; //!< \brief 0: Find PHY header automatically
+ //!< 1: Insert PHY header from the buffer + uint8_t bIncludeCrc:1; //!< \brief 0: Append automatically calculated CRC
+ //!< 1: Insert FCS (CRC) from the buffer + uint8_t :1; + uint8_t payloadLenMsb:5; //!< \brief Most significant bits of payload length. Should only be non-zero to create long + //!< non-standard packets for test purposes + } txOpt; + uint8_t payloadLen; //!< Number of bytes in the payload + uint8_t* pPayload; //!< Pointer to payload buffer of size payloadLen + ratmr_t timeStamp; //!< Time stamp of transmitted frame +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_CSMA +//! @{ +#define CMD_IEEE_CSMA 0x2C02 +//! IEEE 802.15.4 CSMA-CA Command +struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s { + uint16_t commandNo; //!< The command ID number 0x2C02 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t randomState; //!< The state of the pseudo-random generator + uint8_t macMaxBE; //!< The IEEE 802.15.4 MAC parameter macMaxBE + uint8_t macMaxCSMABackoffs; //!< The IEEE 802.15.4 MAC parameter macMaxCSMABackoffs + struct { + uint8_t initCW:5; //!< The initialization value for the CW parameter + uint8_t bSlotted:1; //!< \brief 0: non-slotted CSMA
+ //!< 1: slotted CSMA + uint8_t rxOffMode:2; //!< \brief 0: RX stays on during CSMA backoffs
+ //!< 1: The CSMA-CA algorithm will suspend the receiver if no frame is being received
+ //!< 2: The CSMA-CA algorithm will suspend the receiver if no frame is being received, + //!< or after finishing it (including auto ACK) otherwise
+ //!< 3: The CSMA-CA algorithm will suspend the receiver immediately during back-offs + } csmaConfig; + uint8_t NB; //!< The NB parameter from the IEEE 802.15.4 CSMA-CA algorithm + uint8_t BE; //!< The BE parameter from the IEEE 802.15.4 CSMA-CA algorithm + uint8_t remainingPeriods; //!< The number of remaining periods from a paused backoff countdown + int8_t lastRssi; //!< RSSI measured at the last CCA operation + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the CSMA-CA operation + ratmr_t lastTimeStamp; //!< Time of the last CCA operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< CSMA-CA operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_RX_ACK +//! @{ +#define CMD_IEEE_RX_ACK 0x2C03 +//! IEEE 802.15.4 Receive Acknowledgement Command +struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s { + uint16_t commandNo; //!< The command ID number 0x2C03 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t seqNo; //!< Sequence number to expect + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to give up acknowledgement reception + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to give up + //!< acknowledgement reception +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_ABORT_BG +//! @{ +#define CMD_IEEE_ABORT_BG 0x2C04 +//! IEEE 802.15.4 Abort Background Level Command +struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s { + uint16_t commandNo; //!< The command ID number 0x2C04 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_MOD_CCA +//! @{ +#define CMD_IEEE_MOD_CCA 0x2001 +//! IEEE 802.15.4 Modify CCA Parameter Command +struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s { + uint16_t commandNo; //!< The command ID number 0x2001 + struct { + uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } newCcaOpt; //!< New value of ccaOpt for the running background level operation + int8_t newCcaRssiThr; //!< New value of ccaRssiThr for the running background level operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_MOD_FILT +//! @{ +#define CMD_IEEE_MOD_FILT 0x2002 +//! IEEE 802.15.4 Modify Frame Filtering Parameter Command +struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s { + uint16_t commandNo; //!< The command ID number 0x2002 + struct { + uint16_t frameFiltEn:1; //!< \brief 0: Disable frame filtering
+ //!< 1: Enable frame filtering + uint16_t frameFiltStop:1; //!< \brief 0: Receive all packets to the end
+ //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. + uint16_t autoAckEn:1; //!< \brief 0: Disable auto ACK
+ //!< 1: Enable auto ACK. + uint16_t slottedAckEn:1; //!< \brief 0: Non-slotted ACK
+ //!< 1: Slotted ACK. + uint16_t autoPendEn:1; //!< \brief 0: Auto-pend disabled
+ //!< 1: Auto-pend enabled + uint16_t defaultPend:1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend + uint16_t bPendDataReqOnly:1; //!< \brief 0: Use auto-pend for any packet
+ //!< 1: Use auto-pend for data request packets only + uint16_t bPanCoord:1; //!< \brief 0: Device is not PAN coordinator
+ //!< 1: Device is PAN coordinator + uint16_t maxFrameVersion:2; //!< Reject frames where the frame version field in the FCF is greater than this value + uint16_t fcfReservedMask:3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero + uint16_t modifyFtFilter:2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
+ //!< 0: No modification
+ //!< 1: Invert MSB
+ //!< 2: Set MSB to 0
+ //!< 3: Set MSB to 1 + uint16_t bStrictLenFilter:1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
+ //!< 1: Accept only acknowledgement frames of length 5 + } newFrameFiltOpt; //!< New value of frameFiltOpt for the running background level operation + struct { + uint8_t bAcceptFt0Beacon:1; //!< \brief Treatment of frames with frame type 000 (beacon):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt1Data:1; //!< \brief Treatment of frames with frame type 001 (data):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt2Ack:1; //!< \brief Treatment of frames with frame type 010 (ACK):
+ //!< 0: Reject, unless running ACK receive command
+ //!< 1: Always accept + uint8_t bAcceptFt3MacCmd:1; //!< \brief Treatment of frames with frame type 011 (MAC command):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt4Reserved:1; //!< \brief Treatment of frames with frame type 100 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt5Reserved:1; //!< \brief Treatment of frames with frame type 101 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt6Reserved:1; //!< \brief Treatment of frames with frame type 110 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt7Reserved:1; //!< \brief Treatment of frames with frame type 111 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + } newFrameTypes; //!< New value of frameTypes for the running background level operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_MOD_SRC_MATCH +//! @{ +#define CMD_IEEE_MOD_SRC_MATCH 0x2003 +//! IEEE 802.15.4 Enable/Disable Source Matching Entry Command +struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s { + uint16_t commandNo; //!< The command ID number 0x2003 + struct { + uint8_t bEnable:1; //!< \brief 0: Disable entry
+ //!< 1: Enable entry + uint8_t srcPend:1; //!< New value of the pending bit for the entry + uint8_t entryType:1; //!< \brief 0: Short address
+ //!< 1: Extended address + } options; + uint8_t entryNo; //!< Index of entry to enable or disable +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_ABORT_FG +//! @{ +#define CMD_IEEE_ABORT_FG 0x2401 +//! IEEE 802.15.4 Abort Foreground Level Command +struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s { + uint16_t commandNo; //!< The command ID number 0x2401 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_STOP_FG +//! @{ +#define CMD_IEEE_STOP_FG 0x2402 +//! IEEE 802.15.4 Gracefully Stop Foreground Level Command +struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s { + uint16_t commandNo; //!< The command ID number 0x2402 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_CCA_REQ +//! @{ +#define CMD_IEEE_CCA_REQ 0x2403 +//! IEEE 802.15.4 CCA and RSSI Information Request Command +struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s { + uint16_t commandNo; //!< The command ID number 0x2403 + int8_t currentRssi; //!< The RSSI currently observed on the channel + int8_t maxRssi; //!< The maximum RSSI observed on the channel since Rx was started + struct { + uint8_t ccaState:2; //!< \brief Value of the current CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaEnergy:2; //!< \brief Value of the current energy detect CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaCorr:2; //!< \brief Value of the current correlator based carrier sense CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaSync:1; //!< \brief Value of the current sync found based carrier sense CCA state
+ //!< 0: Idle
+ //!< 1: Busy + } ccaInfo; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ieeeRxOutput +//! @{ +//! Output structure for CMD_IEEE_RX + +struct __RFC_STRUCT rfc_ieeeRxOutput_s { + uint8_t nTxAck; //!< Total number of transmitted ACK frames + uint8_t nRxBeacon; //!< Number of received beacon frames + uint8_t nRxData; //!< Number of received data frames + uint8_t nRxAck; //!< Number of received acknowledgement frames + uint8_t nRxMacCmd; //!< Number of received MAC command frames + uint8_t nRxReserved; //!< Number of received frames with reserved frame type + uint8_t nRxNok; //!< Number of received frames with CRC error + uint8_t nRxIgnored; //!< Number of frames received that are to be ignored + uint8_t nRxBufFull; //!< Number of received frames discarded because the Rx buffer was full + int8_t lastRssi; //!< RSSI of last received frame + int8_t maxRssi; //!< Highest RSSI observed in the operation + uint8_t __dummy0; + ratmr_t beaconTimeStamp; //!< Time stamp of last received beacon frame +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup shortAddrEntry +//! @{ +//! Structure for short address entries + +struct __RFC_STRUCT rfc_shortAddrEntry_s { + uint16_t shortAddr; //!< Short address + uint16_t panId; //!< PAN ID +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ieeeRxCorrCrc +//! @{ +//! Receive status byte that may be appended to message in receive buffer + +struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s { + struct { + uint8_t corr:6; //!< The correlation value + uint8_t bIgnore:1; //!< 1 if the packet should be rejected by frame filtering, 0 otherwise + uint8_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_mailbox.h new file mode 100644 index 0000000..e3902c2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_mailbox.h @@ -0,0 +1,74 @@ +/****************************************************************************** +* Filename: rf_ieee_mailbox.h +* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) +* Revision: 18032 +* +* Description: Definitions for IEEE 802.15.4 interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _IEEE_MAILBOX_H +#define _IEEE_MAILBOX_H + +#include "rf_mailbox.h" + + +/// \name Radio operation status +///@{ +/// \name Operation not finished +///@{ +#define IEEE_SUSPENDED 0x2001 ///< Operation suspended +///@} +/// \name Operation finished normally +///@{ +#define IEEE_DONE_OK 0x2400 ///< Operation ended normally +#define IEEE_DONE_BUSY 0x2401 ///< CSMA-CA operation ended with failure +#define IEEE_DONE_STOPPED 0x2402 ///< Operation stopped after stop command +#define IEEE_DONE_ACK 0x2403 ///< ACK packet received with pending data bit cleared +#define IEEE_DONE_ACKPEND 0x2404 ///< ACK packet received with pending data bit set +#define IEEE_DONE_TIMEOUT 0x2405 ///< Operation ended due to timeout +#define IEEE_DONE_BGEND 0x2406 ///< FG operation ended because necessary background level + ///< operation ended +#define IEEE_DONE_ABORT 0x2407 ///< Operation aborted by command +///@} +/// \name Operation finished with error +///@{ +#define IEEE_ERROR_PAR 0x2800 ///< Illegal parameter +#define IEEE_ERROR_NO_SETUP 0x2801 ///< Operation using Rx or Tx attemted when not in 15.4 mode +#define IEEE_ERROR_NO_FS 0x2802 ///< Operation using Rx or Tx attemted without frequency synth configured +#define IEEE_ERROR_SYNTH_PROG 0x2803 ///< Synthesizer programming failed to complete on time +#define IEEE_ERROR_RXOVF 0x2804 ///< Receiver overflowed during operation +#define IEEE_ERROR_TXUNF 0x2805 ///< Transmitter underflowed during operation +///@} +///@} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_mailbox.h new file mode 100644 index 0000000..956e78d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_mailbox.h @@ -0,0 +1,340 @@ +/****************************************************************************** +* Filename: rf_mailbox.h +* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) +* Revision: 18032 +* +* Description: Definitions for interface between system and radio CPU +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _MAILBOX_H +#define _MAILBOX_H + +#include +#include + + +/// \name RF mode values +/// Defines used to indicate mode of operation to radio core. +///@{ +#define RF_MODE_BLE 0x01 +#define RF_MODE_IEEE_15_4 0x02 +#define RF_MODE_PROPRIETARY_2_4 0x03 +#define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4 +#define RF_MODE_MULTIPLE 0x05 +///@} + + +/// Type definition for RAT +typedef uint32_t ratmr_t; + + + +/// Type definition for a data queue +typedef struct { + uint8_t *pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue + uint8_t *pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue +} dataQueue_t; + + + +/// \name CPE interrupt definitions +/// Interrupt masks for the CPE interrupt in RDBELL. +///@{ +#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished +#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished +#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished +#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished +#define IRQN_TX_DONE 4 ///< Packet transmitted +#define IRQN_TX_ACK 5 ///< ACK packet transmitted +#define IRQN_TX_CTRL 6 ///< Control packet transmitted +#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet +#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet +#define IRQN_TX_RETRANS 9 ///< Packet retransmitted +#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished +#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete +#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored +#define IRQN_RX_NOK 17 ///< Packet received with CRC error +#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored +#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload +#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored +#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent +#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue +#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished +#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer +#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer +#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done +#define IRQN_RX_COLLISION_DETECTED 27 ///< A collision was indicated during packet reception +#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration +#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories +#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished + +#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed + +#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE) +#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE) +#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE) +#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE) + +#define IRQ_TX_DONE (1U << IRQN_TX_DONE) +#define IRQ_TX_ACK (1U << IRQN_TX_ACK) +#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL) +#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK) +#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK) +#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS) + +#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE) +#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED) + +#define IRQ_RX_OK (1U << IRQN_RX_OK) +#define IRQ_RX_NOK (1U << IRQN_RX_NOK) +#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED) +#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY) +#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL) +#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK) +#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL) +#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE) +#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN) +#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN) +#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED) +#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED) +#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK) +#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED) +#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE) +#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR) +///@} + + + +/// \name CMDSTA values +/// Values returned in result byte of CMDSTA +///@{ +#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed +#define CMDSTA_Done 0x01 ///< Command successfully parsed + +#define CMDSTA_IllegalPointer 0x81 ///< The pointer signaled in CMDR is not valid +#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown +#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the + ///< command is not a direct command +#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context + ///< where it is not supported +#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled + ///< while another operation was already running in the RF core +#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed + ///< on submission. +#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was + ///< not supported by the queue in its current state +#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry + ///< was busy +///@} + + + +/// \name Macros for sending direct commands +///@{ +/// Direct command with no parameter +#define CMDR_DIR_CMD(cmdId) (((cmdId) << 16) | 1) + +/// Direct command with 1-byte parameter +#define CMDR_DIR_CMD_1BYTE(cmdId, par) (((cmdId) << 16) | ((par) << 8) | 1) + +/// Direct command with 2-byte parameter +#define CMDR_DIR_CMD_2BYTE(cmdId, par) (((cmdId) << 16) | ((par) & 0xFFFC) | 1) + +///@} + + + +/// \name Definitions for trigger types +///@{ +#define TRIG_NOW 0 ///< Triggers immediately +#define TRIG_NEVER 1 ///< Never trigs +#define TRIG_ABSTIME 2 ///< Trigs at an absolute time +#define TRIG_REL_SUBMIT 3 ///< Trigs at a time relative to the command was submitted +#define TRIG_REL_START 4 ///< Trigs at a time relative to the command started +#define TRIG_REL_PREVSTART 5 ///< Trigs at a time relative to the previous command in the chain started +#define TRIG_REL_FIRSTSTART 6 ///< Trigs at a time relative to the first command in the chain started +#define TRIG_REL_PREVEND 7 ///< Trigs at a time relative to the previous command in the chain ended +#define TRIG_REL_EVT1 8 ///< Trigs at a time relative to the context defined "Event 1" +#define TRIG_REL_EVT2 9 ///< Trigs at a time relative to the context defined "Event 2" +#define TRIG_EXTERNAL 10 ///< Trigs at an external event to the radio timer +#define TRIG_PAST_BM 0x80 ///< Bitmask for setting pastTrig bit in order to trig immediately if + ///< trigger happened in the past +///@} + + +/// \name Definitions for conditional execution +///@{ +#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort) +#define COND_NEVER 1 ///< Never run next command +#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned + ///< False +#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned + ///< False +#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of + ///< commands if it returned False +#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next + ///< command if it returned False +///@} + + + +/// \name Radio operation status +///@{ +/// \name Operation not finished +///@{ +#define IDLE 0x0000 ///< Operation not started +#define PENDING 0x0001 ///< Start of command is pending +#define ACTIVE 0x0002 ///< Running +#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command +///@} +/// \name Operation finished normally +///@{ +#define DONE_OK 0x0400 ///< Operation ended normally +#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero +#define DONE_RXERR 0x0402 ///< Operation ended with CRC error +#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout +#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command +#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command +#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed +///@} +/// \name Operation finished with error +///@{ +#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past +#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter +#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation +#define ERROR_PAR 0x0803 ///< Error in a command specific parameter +#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation +#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio + ///< operation command +#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command +#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attemted without CMD_RADIO_SETUP +#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attemted without frequency synth configured +#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed +#define ERROR_TXUNF 0x080A ///< Tx underflow observed +#define ERROR_RXOVF 0x080B ///< Rx overflow observed +#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received +#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending +///@} +///@} + + +/// \name Data entry types +///@{ +#define DATA_ENTRY_TYPE_GEN 0 ///< General type: Tx entry or single element Rx entry +#define DATA_ENTRY_TYPE_MULTI 1 ///< Multi-element Rx entry type +#define DATA_ENTRY_TYPE_PTR 2 ///< Pointer entry type +#define DATA_ENTRY_TYPE_PARTIAL 3 ///< Partial read entry type +///@ + + +/// \name Data entry statuses +///@{ +#define DATA_ENTRY_PENDING 0 ///< Entry not yet used +#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU +#define DATA_ENTRY_BUSY 2 ///< Entry being updated +#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry +#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished +///@} + + + +/// \name Macros for RF register override +///@{ +/// Macro for ADI half-size value-mask combination +#define ADI_VAL_MASK(addr, mask, value) \ +(((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \ + ((((mask) & 0x0F) << 4) | ((value) & 0x0F))) +/// 32-bit write of 16-bit value +#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16)) +/// ADI register, full-size write +#define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \ +(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) +/// 2 ADI registers, full-size write +#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \ +(2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \ +(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) +/// ADI register, half-size read-modify-write +#define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \ +(((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) +/// 2 ADI registers, half-size read-modify-write +#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \ +(2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \ +(ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) + +/// 16-bit SW register as defined in radio_par_def.txt +#define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16)) +/// SW register as defined in radio_par_def.txt with added index (for use with registers > 16 bits). +#define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \ +(((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16)) +/// 8-bit SW register as defined in radio_par_def.txt +#define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \ +((uint32_t)(val) << 16)) +/// Two 8-bit SW registers as defined in radio_par_def.txt; the one given by field and the next byte. +#define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \ + (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24)) +#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \ +((uint32_t)(length) << 16) | (1U << 30)) +#define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \ +((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30)) +#define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \ +((uint32_t)(length) << 16) | (3U << 30)) +#define MCE_RFE_OVERRIDE(bMceRam, mceRomBank, mceMode, bRfeRam, rfeRomBank, rfeMode) \ + (7 | ((!!(bMceRam)) << 8) | (((mceRomBank) & 0x07) << 9) | ((!!(bRfeRam)) << 12) | (((rfeRomBank) & 0x07) << 13) | \ + (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24)) +#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \ + (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \ + (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \ + (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \ + (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \ + (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \ + (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \ + (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \ + (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \ + 0x09) << 4)) // Use illegal value for illegal address range +/// End of string for override register +#define END_OVERRIDE 0xFFFFFFFF + + +/// ADI address-value pair +#define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF)) +#define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value)) + +/// Low half-word +#define LOWORD(value) ((value) & 0xFFFF) +/// High half-word +#define HIWORD(value) ((value) >> 16) +///@} + + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_cmd.h new file mode 100644 index 0000000..d97d45d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_cmd.h @@ -0,0 +1,498 @@ +/****************************************************************************** +* Filename: rf_prop_cmd.h +* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) +* Revision: 18052 +* +* Description: CC26x0 API for Proprietary mode commands +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __PROP_CMD_H +#define __PROP_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup prop_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_s rfc_CMD_PROP_TX_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_s rfc_CMD_PROP_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s rfc_CMD_PROP_TX_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s rfc_CMD_PROP_RX_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s rfc_CMD_PROP_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s rfc_CMD_PROP_RADIO_DIV_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s rfc_CMD_PROP_SET_LEN_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s rfc_CMD_PROP_RESTART_RX_t; +typedef struct __RFC_STRUCT rfc_propRxOutput_s rfc_propRxOutput_t; +typedef struct __RFC_STRUCT rfc_propRxStatus_s rfc_propRxStatus_t; + +//! \addtogroup CMD_PROP_TX +//! @{ +#define CMD_PROP_TX 0x3801 +//! Proprietary Mode Transmit Command +struct __RFC_STRUCT rfc_CMD_PROP_TX_s { + uint16_t commandNo; //!< The command ID number 0x3801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t :2; + uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Transmit length as first byte + } pktConf; + uint8_t pktLen; //!< Packet length + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX +//! @{ +#define CMD_PROP_RX 0x3802 +//! Proprietary Mode Receive Command +struct __RFC_STRUCT rfc_CMD_PROP_RX_s { + uint16_t commandNo; //!< The command ID number 0x3802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bChkAddress:1; //!< \brief 0: No address check
+ //!< 1: Check address + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord; //!< Sync word to listen for + uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + uint8_t address0; //!< Address + uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept + //!< 0x00 as well) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_TX_ADV +//! @{ +#define CMD_PROP_TX_ADV 0x3803 +//! Proprietary Mode Advanced Transmit Command +struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s { + uint16_t commandNo; //!< The command ID number 0x3803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t :2; + uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bCrcIncSw:1; //!< \brief 0:Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + } pktConf; + uint8_t numHdrBits; //!< Number of bits in header (0--32) + uint16_t pktLen; //!< Packet length. 0: Unlimited + struct { + uint8_t bExtTxTrig:1; //!< \brief 0: Start packet on a fixed time from the command start trigger
+ //!< 1: Start packet on an external trigger (input event to RAT) + uint8_t inputMode:2; //!< \brief Input mode if external trigger is used for TX start
+ //!< 0: Rising edge
+ //!< 1: Falling edge
+ //!< 2: Both edges
+ //!< 3: Reserved + uint8_t source:5; //!< RAT input event number used for capture if external trigger is used for TX start + } startConf; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } preTrigger; //!< Trigger for transition from preamble to sync word + ratmr_t preTime; //!< \brief Time used together with preTrigger for transition from preamble to sync + //!< word. If preTrigger.triggerType is set to "now", one preamble as + //!< configured in the setup will be sent. Otherwise, the preamble will be repeated until + //!< this trigger is observed. + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet, or TX queue for unlimited length +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX_ADV +//! @{ +#define CMD_PROP_RX_ADV 0x3804 +//! Proprietary Mode Advanced Receive Command +struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s { + uint16_t commandNo; //!< The command ID number 0x3804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bCrcIncSw:1; //!< \brief 0: Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord0; //!< Sync word to listen for + uint32_t syncWord1; //!< Alternative sync word if non-zero + uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + struct { + uint16_t numHdrBits:6; //!< Number of bits in header (0--32) + uint16_t lenPos:5; //!< Position of length field in header (0--31) + uint16_t numLenBits:5; //!< Number of bits in length field (0--16) + } hdrConf; + struct { + uint16_t addrType:1; //!< \brief 0: Address after header
+ //!< 1: Address in header + uint16_t addrSize:5; //!< \brief If addrType = 0: Address size in bytes
+ //!< If addrType = 1: Address size in bits + uint16_t addrPos:5; //!< \brief If addrType = 1: Bit position of address in header
+ //!< If addrType = 0: Non-zero to extend address with sync word identifier + uint16_t numAddr:5; //!< Number of addresses in address list + } addrConf; + int8_t lenOffset; //!< Signed value to add to length field + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + uint8_t* pAddr; //!< Pointer to address list + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RADIO_SETUP +//! @{ +#define CMD_PROP_RADIO_SETUP 0x3806 +//! Proprietary Mode Radio Setup Command +struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x3806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t modType:3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< Others: Reserved + uint16_t deviation:13; //!< Deviation (250 Hz steps) + } modulation; + struct { + uint32_t preScale:4; //!< Prescaler value + uint32_t :4; + uint32_t rateWord:21; //!< Rate word + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct { + uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct { + uint16_t nSwBits:6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode:4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< Others: Reserved + uint16_t bOuterCode:1; //!< Reserved + uint16_t whitenMode:2; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved + uint16_t bAgcDisable:1; //!< Reserved + } formatConf; + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< \brief Transmit power + //!< Bits 0--5: IB + //!< Value to write to the PA power control field at 25 °C + //!< Bits 6--7: GC + //!< Value to write to the gain control of the 1st stage of the PA + //!< Bits 8--15: tempCoeff + //!< Temperature coefficient for IB. 0: No temperature compensation + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RADIO_DIV_SETUP +//! @{ +#define CMD_PROP_RADIO_DIV_SETUP 0x3807 +//! Define only for compatibility with CC13XX family. Command will result in error if sent. +struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s { + uint8_t dummy0; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_SET_LEN +//! @{ +#define CMD_PROP_SET_LEN 0x3401 +//! Set Packet Length Command +struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s { + uint16_t commandNo; //!< The command ID number 0x3401 + uint16_t rxLen; //!< Payload length to use +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RESTART_RX +//! @{ +#define CMD_PROP_RESTART_RX 0x3402 +//! Restart Packet Command +struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s { + uint16_t commandNo; //!< The command ID number 0x3402 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup propRxOutput +//! @{ +//! Output structure for RX operations + +struct __RFC_STRUCT rfc_propRxOutput_s { + uint16_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint16_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< Number of packets that have been received with CRC OK and ignored due to address mismatch + uint8_t nRxStopped; //!< Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1 + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + ratmr_t timeStamp; //!< Time stamp of last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup propRxStatus +//! @{ +//! Receive status byte that may be appended to message in receive buffer + +struct __RFC_STRUCT rfc_propRxStatus_s { + struct { + uint8_t addressInd:5; //!< Index of address found (0 if not applicable) + uint8_t syncWordId:1; //!< 0 for primary sync word, 1 for alternate sync word + uint8_t result:2; //!< \brief 0: Packet received correctly, not ignored
+ //!< 1: Packet received with CRC error
+ //!< 2: Packet received correctly, but can be ignored
+ //!< 3: Packet reception was aborted + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_mailbox.h new file mode 100644 index 0000000..7eb264b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_mailbox.h @@ -0,0 +1,71 @@ +/****************************************************************************** +* Filename: rf_prop_mailbox.h +* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) +* Revision: 18032 +* +* Description: Definitions for proprietary mode radio interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _PROP_MAILBOX_H +#define _PROP_MAILBOX_H + +/// \name Radio operation status +///@{ +/// \name Operation finished normally +///@{ +#define PROP_DONE_OK 0x3400 ///< Operation ended normally +#define PROP_DONE_RXTIMEOUT 0x3401 ///< Operation stopped after end trigger while waiting for sync +#define PROP_DONE_BREAK 0x3402 ///< Rx stopped due to timeout in the middle of a packet +#define PROP_DONE_ENDED 0x3403 ///< Operation stopped after end trigger during reception +#define PROP_DONE_STOPPED 0x3404 ///< Operation stopped after stop command +#define PROP_DONE_ABORT 0x3405 ///< Operation aborted by abort command +#define PROP_DONE_RXERR 0x3406 ///< Operation ended after receiving packet with CRC error +#define PROP_DONE_IDLE 0x3407 ///< Carrier sense operation ended because of idle channel +#define PROP_DONE_BUSY 0x3408 ///< Carrier sense operation ended because of busy channel +#define PROP_DONE_IDLETIMEOUT 0x3409 ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 1 +#define PROP_DONE_BUSYTIMEOUT 0x340A ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 0 + +///@} +/// \name Operation finished with error +///@{ +#define PROP_ERROR_PAR 0x3800 ///< Illegal parameter +#define PROP_ERROR_RXBUF 0x3801 ///< No available Rx buffer at the start of a packet +#define PROP_ERROR_RXFULL 0x3802 ///< Out of Rx buffer during reception in a partial read buffer +#define PROP_ERROR_NO_SETUP 0x3803 ///< Radio was not set up in proprietary mode +#define PROP_ERROR_NO_FS 0x3804 ///< Synth was not programmed when running Rx or Tx +#define PROP_ERROR_RXOVF 0x3805 ///< Rx overflow observed during operation +#define PROP_ERROR_TXUNF 0x3806 ///< Tx underflow observed during operation +///@} +///@} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rfc.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rfc.c new file mode 100644 index 0000000..4f69eca --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rfc.c @@ -0,0 +1,339 @@ +/****************************************************************************** +* Filename: rfc.c +* Revised: 2018-08-08 11:04:37 +0200 (Wed, 08 Aug 2018) +* Revision: 52334 +* +* Description: Driver for the RF Core. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "rfc.h" +#include "rf_mailbox.h" +#include + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef RFCCpeIntGetAndClear + #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear + #undef RFCDoorbellSendTo + #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo + #undef RFCSynthPowerDown + #define RFCSynthPowerDown NOROM_RFCSynthPowerDown + #undef RFCCpePatchReset + #define RFCCpePatchReset NOROM_RFCCpePatchReset + #undef RFCOverrideSearch + #define RFCOverrideSearch NOROM_RFCOverrideSearch + #undef RFCOverrideUpdate + #define RFCOverrideUpdate NOROM_RFCOverrideUpdate + #undef RFCHwIntGetAndClear + #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #undef RFCRfTrimRead + #define RFCRfTrimRead NOROM_RFCRfTrimRead + #undef RFCRfTrimSet + #define RFCRfTrimSet NOROM_RFCRfTrimSet + #undef RFCRTrim + #define RFCRTrim NOROM_RFCRTrim + #undef RFCAdi3VcoLdoVoltageMode + #define RFCAdi3VcoLdoVoltageMode NOROM_RFCAdi3VcoLdoVoltageMode +#endif + +// Definition of addresses and offsets +#define _CPERAM_START 0x21000000 +#define _PARSER_PATCH_TAB_OFFSET 0x0334 +#define _PATCH_TAB_OFFSET 0x033C +#define _IRQPATCH_OFFSET 0x03AC +#define _PATCH_VEC_OFFSET 0x0404 + +#define RFC_RTRIM_PATTERN 0x4038 +#define RFC_RTRIM_MASK 0xFFFF + +// Default interrupt table +static const uint16_t rfc_defaultIrqAddr[] = +{ + 0x398b, + 0x3805, + 0x3825, + 0x3839, + 0x0acf, + 0x3857, + 0x38d7, + 0x09dd, + 0x5819, + 0x0ab3, + 0x38f7, +}; + +//***************************************************************************** +// +// Get and clear CPE interrupt flags which match the provided bitmask +// +//***************************************************************************** +uint32_t +RFCCpeIntGetAndClear(uint32_t ui32Mask) +{ + // Read the CPE interrupt flags which match the provided bitmask + uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask; + + // Clear the interrupt flags + RFCCpeIntClear(ui32Ifg); + + // Return with the interrupt flags + return (ui32Ifg); +} + + +//***************************************************************************** +// +// Send a radio operation to the doorbell and wait for an acknowledgement +// +//***************************************************************************** +uint32_t +RFCDoorbellSendTo(uint32_t pOp) +{ + // Wait until the doorbell becomes available + while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) != 0); + RFCAckIntClear(); + + // Submit the command to the CM0 through the doorbell + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) = pOp; + + // Wait until the CM0 starts to parse the command + while(!HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG)); + RFCAckIntClear(); + + // Return with the content of status register + return(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDSTA)); +} + + +//***************************************************************************** +// +// Turn off the RF synthesizer. The radio will no longer respond to commands! +// +//***************************************************************************** +void +RFCSynthPowerDown(void) +{ + // Definition of reserved words + const uint32_t RFC_RESERVED0 = 0x40044108; + const uint32_t RFC_RESERVED1 = 0x40044114; + const uint32_t RFC_RESERVED2 = 0x4004410C; + const uint32_t RFC_RESERVED3 = 0x40044100; + + // Disable CPE clock, enable FSCA clock. + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = (HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) + & ~RFC_PWR_PWMCLKEN_CPE_M) | RFC_PWR_PWMCLKEN_FSCA_M; + + HWREG(RFC_RESERVED0) = 3; + HWREG(RFC_RESERVED1) = 0x1030; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED1) = 0x50; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED1) = 0x650; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED3) = 1; + +} + + +//***************************************************************************** +// +// Reset previously patched CPE RAM to a state where it can be patched again +// +//***************************************************************************** +void +RFCCpePatchReset(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_CPERAM_START + _PARSER_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *)(_CPERAM_START + _IRQPATCH_OFFSET); + + memset(pPatchTab, 0xFF, _IRQPATCH_OFFSET - _PARSER_PATCH_TAB_OFFSET); + + int i; + for (i = 0; i < sizeof(rfc_defaultIrqAddr)/sizeof(rfc_defaultIrqAddr[0]); i++) + { + pIrqPatch[i * 2 + 1] = rfc_defaultIrqAddr[i]; + } +} + + +//***************************************************************************** +// +// Function to search an override list for the provided pattern within the search depth. +// +//***************************************************************************** +uint8_t +RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth) +{ + // Search from start of the override list, to look for first override entry that matches search pattern + uint8_t override_index; + for(override_index = 0; (override_index < searchDepth) && (pOverride[override_index] != END_OVERRIDE); override_index++) + { + // Compare the value to the given pattern + if((pOverride[override_index] & mask) == pattern) + { + // Return with the index of override in case of match + return override_index; + } + } + + // Return with an invalid index + return 0xFF; +} + +//***************************************************************************** +// +// Update the override list based on values stored in FCFG1 +// +//***************************************************************************** +uint8_t +RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams) +{ + // Function is left blank for compatibility reasons. + return 0; +} + + +//***************************************************************************** +// +// Get and clear HW interrupt flags +// +//***************************************************************************** +uint32_t +RFCHwIntGetAndClear(uint32_t ui32Mask) +{ + // Read the CPE interrupt flags which match the provided bitmask + uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) & ui32Mask; + + // Clear the interupt flags + RFCHwIntClear(ui32Ifg); + + // Return with the interrupt flags + return (ui32Ifg); +} + + +//***************************************************************************** +// +// Read RF trim values from FCFG1 +// +//***************************************************************************** +void +RFCRfTrimRead(rfc_radioOp_t *pOpSetup, rfTrim_t* pRfTrim) +{ + // Definition of position and bitmask of divider value + const uint32_t CONFIG_MISC_ADC_DIVIDER = 27; + const uint32_t CONFIG_MISC_ADC_DIVIDER_BM = 0xF8000000U; + + // Read trim values from FCFG1 + pRfTrim->configIfAdc = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_IF_ADC); + pRfTrim->configRfFrontend = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND); + pRfTrim->configSynth = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH); + // Make sure configMiscAdc is not 0 by setting an unused bit to 1 + pRfTrim->configMiscAdc = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC) + & ~CONFIG_MISC_ADC_DIVIDER_BM) | (2U << CONFIG_MISC_ADC_DIVIDER); +} + + +//***************************************************************************** +// +// Write preloaded RF trim values to the CM0 +// +//***************************************************************************** +void +RFCRfTrimSet(rfTrim_t* pRfTrim) +{ + memcpy((void*)&HWREG(0x21000018), (void*)pRfTrim, sizeof(rfTrim_t)); +} + + +//***************************************************************************** +// +// Check Override RTrim vs FCFG RTrim +// +//***************************************************************************** +uint8_t +RFCRTrim(rfc_radioOp_t *pOpSetup) +{ + // Function is left blank for compatibility reasons. + return 0; +} + + +//***************************************************************************** +// +// Function to set VCOLDO reference to voltage mode +// +//***************************************************************************** +void +RFCAdi3VcoLdoVoltageMode(bool bEnable) +{ + // Function is left blank for compatibility reasons. +} + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef RFCCpeIntGetAndClear + #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear + #undef RFCDoorbellSendTo + #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo + #undef RFCSynthPowerDown + #define RFCSynthPowerDown NOROM_RFCSynthPowerDown + #undef RFCCpePatchReset + #define RFCCpePatchReset NOROM_RFCCpePatchReset + #undef RFCOverrideSearch + #define RFCOverrideSearch NOROM_RFCOverrideSearch + #undef RFCOverrideUpdate + #define RFCOverrideUpdate NOROM_RFCOverrideUpdate + #undef RFCHwIntGetAndClear + #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #undef RFCRfTrimRead + #define RFCRfTrimRead NOROM_RFCRfTrimRead + #undef RFCRfTrimSet + #define RFCRfTrimSet NOROM_RFCRfTrimSet + #undef RFCRTrim + #define RFCRTrim NOROM_RFCRTrim + #undef RFCAdi3VcoLdoVoltageMode + #define RFCAdi3VcoLdoVoltageMode NOROM_RFCAdi3VcoLdoVoltageMode +#endif + +// See rfc.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rfc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rfc.h new file mode 100644 index 0000000..6ad3a44 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rfc.h @@ -0,0 +1,483 @@ +/****************************************************************************** +* Filename: rfc.h +* Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018) +* Revision: 52338 +* +* Description: Defines and prototypes for the RF Core. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup rfc_api +//! @{ +// +//***************************************************************************** + +#ifndef __RFC_H__ +#define __RFC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_rfc_pwr.h" +#include "../inc/hw_rfc_dbell.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_adi.h" +#include "rf_common_cmd.h" +#include "rf_prop_cmd.h" +#include "rf_ble_cmd.h" + +// Definition of RFTRIM container +typedef struct { + uint32_t configIfAdc; + uint32_t configRfFrontend; + uint32_t configSynth; + uint32_t configMiscAdc; +} rfTrim_t; + +// Definition of maximum search depth used by the RFCOverrideUpdate function +#define RFC_MAX_SEARCH_DEPTH 5 + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear + #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo + #define RFCSynthPowerDown NOROM_RFCSynthPowerDown + #define RFCCpePatchReset NOROM_RFCCpePatchReset + #define RFCOverrideSearch NOROM_RFCOverrideSearch + #define RFCOverrideUpdate NOROM_RFCOverrideUpdate + #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #define RFCRfTrimRead NOROM_RFCRfTrimRead + #define RFCRfTrimSet NOROM_RFCRfTrimSet + #define RFCRTrim NOROM_RFCRTrim + #define RFCAdi3VcoLdoVoltageMode NOROM_RFCAdi3VcoLdoVoltageMode +#endif + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enable the RF core clocks. +//! +//! As soon as the RF core is started it will handle clock control +//! autonomously. No check should be performed to check the clocks. Instead +//! the radio can be ping'ed through the command interface. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +RFCClockEnable(void) +{ + // Enable basic clocks to get the CPE run + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM + | RFC_PWR_PWMCLKEN_CPE + | RFC_PWR_PWMCLKEN_RFC; +} + + +//***************************************************************************** +// +//! \brief Disable the RF core clocks. +//! +//! As soon as the RF core is started it will handle clock control +//! autonomously. No check should be performed to check the clocks. Instead +//! the radio can be ping'ed through the command interface. +//! +//! When disabling clocks it is the programmers responsibility that the +//! RF core clocks are safely gated. I.e. the RF core should be safely +//! 'parked'. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +RFCClockDisable(void) +{ + // Disable all clocks + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x0; +} + + +//***************************************************************************** +// +//! Clear HW interrupt flags +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpeIntClear(uint32_t ui32Mask) +{ + // Clear the masked pending interrupts. + do + { + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = ~ui32Mask; + }while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask); +} + + +//***************************************************************************** +// +//! Clear CPE interrupt flags. +// +//***************************************************************************** +__STATIC_INLINE void +RFCHwIntClear(uint32_t ui32Mask) +{ + // Clear the masked pending interrupts. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = ~ui32Mask; +} + + +//***************************************************************************** +// +//! Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector). +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe0IntSelect(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE0 IRQ. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) &= ~ui32Mask; +} + + +//***************************************************************************** +// +//! Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector). +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe1IntSelect(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE1 IRQ. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) |= ui32Mask; +} + + +//***************************************************************************** +// +//! Enable CPEx interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpeIntEnable(uint32_t ui32Mask) +{ + // Enable CPE interrupts from RF Core. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask; +} + + +//***************************************************************************** +// +//! Select, clear, and enable interrupt sources to CPE0. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe0IntSelectClearEnable(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE0 IRQ. + RFCCpe0IntSelect(ui32Mask); + + // Clear the masked interrupts. + RFCCpeIntClear(ui32Mask); + + // Enable the masked interrupts. + RFCCpeIntEnable(ui32Mask); +} + + +//***************************************************************************** +// +//! Select, clear, and enable interrupt sources to CPE1. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe1IntSelectClearEnable(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE1 IRQ. + RFCCpe1IntSelect(ui32Mask); + + // Clear the masked interrupts. + RFCCpeIntClear(ui32Mask); + + // Enable the masked interrupts. + RFCCpeIntEnable(ui32Mask); +} + + +//***************************************************************************** +// +//! Enable HW interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCHwIntEnable(uint32_t ui32Mask) +{ + // Enable the masked interrupts + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) |= ui32Mask; +} + + +//***************************************************************************** +// +//! Disable CPE interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpeIntDisable(uint32_t ui32Mask) +{ + // Disable the masked interrupts + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) &= ~ui32Mask; +} + + +//***************************************************************************** +// +//! Disable HW interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCHwIntDisable(uint32_t ui32Mask) +{ + // Disable the masked interrupts + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) &= ~ui32Mask; +} + + +//***************************************************************************** +// +//! Get and clear CPE interrupt flags. +// +//***************************************************************************** +extern uint32_t RFCCpeIntGetAndClear(uint32_t ui32Mask); + + +//***************************************************************************** +// +//! Clear ACK interrupt flag. +// +//***************************************************************************** +__STATIC_INLINE void +RFCAckIntClear(void) +{ + // Clear any pending interrupts. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0x0; +} + + +//***************************************************************************** +// +//! Send a radio operation to the doorbell and wait for an acknowledgment. +// +//***************************************************************************** +extern uint32_t RFCDoorbellSendTo(uint32_t pOp); + + +//***************************************************************************** +// +//! This function implements a fast way to turn off the synthesizer. +// +//***************************************************************************** +extern void RFCSynthPowerDown(void); + + +//***************************************************************************** +// +//! Reset previously patched CPE RAM to a state where it can be patched again. +// +//***************************************************************************** +extern void RFCCpePatchReset(void); + + +//***************************************************************************** +// +// Function to search an override list for the provided pattern within the search depth. +// +//***************************************************************************** +extern uint8_t RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth); + + +//***************************************************************************** +// +//! Function to update override list +// +//***************************************************************************** +extern uint8_t RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams); + + +//***************************************************************************** +// +//! Get and clear HW interrupt flags. +// +//***************************************************************************** +extern uint32_t RFCHwIntGetAndClear(uint32_t ui32Mask); + + +//***************************************************************************** +// +//! Get the type of currently selected PA. +// +//***************************************************************************** + + +//***************************************************************************** +// +//! Read RF trim from flash using CM3. +// +//***************************************************************************** +extern void RFCRfTrimRead(rfc_radioOp_t *pOpSetup, rfTrim_t* rfTrim); + + +//***************************************************************************** +// +//! Write preloaded RF trim values directly into CPE. +// +//***************************************************************************** +extern void RFCRfTrimSet(rfTrim_t* rfTrim); + + +//***************************************************************************** +// +//! Check Override RTrim vs FCFG RTrim. +// +//***************************************************************************** +extern uint8_t RFCRTrim(rfc_radioOp_t *pOpSetup); + + +//***************************************************************************** +// +//! Function to set VCOLDO reference to voltage mode. +// +//***************************************************************************** +extern void RFCAdi3VcoLdoVoltageMode(bool bEnable); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_RFCCpeIntGetAndClear + #undef RFCCpeIntGetAndClear + #define RFCCpeIntGetAndClear ROM_RFCCpeIntGetAndClear + #endif + #ifdef ROM_RFCDoorbellSendTo + #undef RFCDoorbellSendTo + #define RFCDoorbellSendTo ROM_RFCDoorbellSendTo + #endif + #ifdef ROM_RFCSynthPowerDown + #undef RFCSynthPowerDown + #define RFCSynthPowerDown ROM_RFCSynthPowerDown + #endif + #ifdef ROM_RFCCpePatchReset + #undef RFCCpePatchReset + #define RFCCpePatchReset ROM_RFCCpePatchReset + #endif + #ifdef ROM_RFCOverrideSearch + #undef RFCOverrideSearch + #define RFCOverrideSearch ROM_RFCOverrideSearch + #endif + #ifdef ROM_RFCOverrideUpdate + #undef RFCOverrideUpdate + #define RFCOverrideUpdate ROM_RFCOverrideUpdate + #endif + #ifdef ROM_RFCHwIntGetAndClear + #undef RFCHwIntGetAndClear + #define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear + #endif + #ifdef ROM_RFCRfTrimRead + #undef RFCRfTrimRead + #define RFCRfTrimRead ROM_RFCRfTrimRead + #endif + #ifdef ROM_RFCRfTrimSet + #undef RFCRfTrimSet + #define RFCRfTrimSet ROM_RFCRfTrimSet + #endif + #ifdef ROM_RFCRTrim + #undef RFCRTrim + #define RFCRTrim ROM_RFCRTrim + #endif + #ifdef ROM_RFCAdi3VcoLdoVoltageMode + #undef RFCAdi3VcoLdoVoltageMode + #define RFCAdi3VcoLdoVoltageMode ROM_RFCAdi3VcoLdoVoltageMode + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __RFC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom.h new file mode 100644 index 0000000..38a9519 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom.h @@ -0,0 +1,687 @@ +/****************************************************************************** +* Filename: rom.h +* Revised: 2018-11-02 13:54:49 +0100 (Fri, 02 Nov 2018) +* Revision: 53196 +* +* Description: Prototypes for the ROM utility functions. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ROM_H__ +#define __ROM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "../inc/hw_types.h" + +#ifndef __HAPI_H__ +#define __HAPI_H__ + +// Start address of the ROM hard API access table (located after the ROM FW rev field) +#define ROM_HAPI_TABLE_ADDR 0x10000048 + +// ROM Hard-API function interface types +typedef uint32_t (* FPTR_CRC32_T) ( uint8_t* /* pui8Data */,\ + uint32_t /* ui32ByteCount */,\ + uint32_t /* ui32RepeatCount */); + +typedef uint32_t (* FPTR_GETFLSIZE_T) ( void ); + +typedef uint32_t (* FPTR_GETCHIPID_T) ( void ); + +typedef uint32_t (* FPTR_RESERVED1_T) ( uint32_t ); + +typedef uint32_t (* FPTR_RESERVED2_T) ( void ); + +typedef uint32_t (* FPTR_RESERVED3_T) ( uint8_t* ,\ + uint32_t ,\ + uint32_t ); +typedef void (* FPTR_RESETDEV_T) ( void ); + +typedef uint32_t (* FPTR_FLETCHER32_T) ( uint16_t* /* pui16Data */,\ + uint16_t /* ui16WordCount */,\ + uint16_t /* ui16RepeatCount */); + +typedef uint32_t (* FPTR_MINVAL_T) ( uint32_t* /* ulpDataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef uint32_t (* FPTR_MAXVAL_T) ( uint32_t* /* pui32DataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef uint32_t (* FPTR_MEANVAL_T) ( uint32_t* /* pui32DataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef uint32_t (* FPTR_STDDVAL_T) ( uint32_t* /* pui32DataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef void (* FPTR_HFSOURCESAFESWITCH_T) ( void ); + +typedef void (* FPTR_RESERVED4_T) ( uint32_t ); + +typedef void (* FPTR_RESERVED5_T) ( uint32_t ); + +typedef void (* FPTR_COMPAIN_T) ( uint8_t /* ut8Signal */); + +typedef void (* FPTR_COMPAREF_T) ( uint8_t /* ut8Signal */); + +typedef void (* FPTR_ADCCOMPBIN_T) ( uint8_t /* ut8Signal */); + +typedef void (* FPTR_COMPBREF_T) ( uint8_t /* ut8Signal */); + +extern uint32_t MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer, + uint32_t ui32Address, + uint32_t ui32Count); + +extern uint32_t MemBusWrkAroundHapiEraseSector(uint32_t ui32Address); + +// ROM Hard-API access table type +typedef struct +{ + FPTR_CRC32_T Crc32; + FPTR_GETFLSIZE_T FlashGetSize; + FPTR_GETCHIPID_T GetChipId; + FPTR_RESERVED1_T ReservedLocation1; + FPTR_RESERVED2_T ReservedLocation2; + FPTR_RESERVED3_T ReservedLocation3; + FPTR_RESETDEV_T ResetDevice; + FPTR_FLETCHER32_T Fletcher32; + FPTR_MINVAL_T MinValue; + FPTR_MAXVAL_T MaxValue; + FPTR_MEANVAL_T MeanValue; + FPTR_STDDVAL_T StandDeviationValue; + FPTR_RESERVED4_T ReservedLocation4; + FPTR_RESERVED5_T ReservedLocation5; + FPTR_HFSOURCESAFESWITCH_T HFSourceSafeSwitch; + FPTR_COMPAIN_T SelectCompAInput; + FPTR_COMPAREF_T SelectCompARef; + FPTR_ADCCOMPBIN_T SelectADCCompBInput; + FPTR_COMPBREF_T SelectCompBRef; +} HARD_API_T; + +// Pointer to the ROM HAPI table +#define P_HARD_API ((HARD_API_T*) ROM_HAPI_TABLE_ADDR) + +// Add wrapper around the Hapi functions needing the "bus arbitration issue" workaround +extern void SafeHapiVoid( FPTR_VOID_VOID_T fPtr ); +extern void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ); + +#define HapiCrc32(a,b,c) P_HARD_API->Crc32(a,b,c) +#define HapiGetFlashSize() P_HARD_API->FlashGetSize() +#define HapiGetChipId() P_HARD_API->GetChipId() +#define HapiSectorErase(a) MemBusWrkAroundHapiEraseSector(a) +#define HapiProgramFlash(a,b,c) MemBusWrkAroundHapiProgramFlash(a,b,c) +#define HapiResetDevice() P_HARD_API->ResetDevice() +#define HapiFletcher32(a,b,c) P_HARD_API->Fletcher32(a,b,c) +#define HapiMinValue(a,b) P_HARD_API->MinValue(a,b) +#define HapiMaxValue(a,b) P_HARD_API->MaxValue(a,b) +#define HapiMeanValue(a,b) P_HARD_API->MeanValue(a,b) +#define HapiStandDeviationValue(a,b) P_HARD_API->StandDeviationValue(a,b) +#define HapiHFSourceSafeSwitch() SafeHapiVoid( P_HARD_API->HFSourceSafeSwitch ) +#define HapiSelectCompAInput(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectCompAInput , a ) +#define HapiSelectCompARef(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectCompARef , a ) +#define HapiSelectADCCompBInput(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectADCCompBInput, a ) +#define HapiSelectCompBRef(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectCompBRef , a ) + +// Defines for input parameter to the HapiSelectCompAInput function. +#define COMPA_IN_NC 0x00 +// Defines used in CC13x0/CC26x0 devices +#define COMPA_IN_AUXIO7 0x09 +#define COMPA_IN_AUXIO6 0x0A +#define COMPA_IN_AUXIO5 0x0B +#define COMPA_IN_AUXIO4 0x0C +#define COMPA_IN_AUXIO3 0x0D +#define COMPA_IN_AUXIO2 0x0E +#define COMPA_IN_AUXIO1 0x0F +#define COMPA_IN_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7 +#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6 +#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5 +#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4 +#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3 +#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2 +#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1 +#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0 + +// Defines for input parameter to the HapiSelectCompARef function. +#define COMPA_REF_NC 0x00 +#define COMPA_REF_DCOUPL 0x01 +#define COMPA_REF_VSS 0x02 +#define COMPA_REF_VDDS 0x03 +#define COMPA_REF_ADCVREFP 0x04 +// Defines used in CC13x0/CC26x0 devices +#define COMPA_REF_AUXIO7 0x09 +#define COMPA_REF_AUXIO6 0x0A +#define COMPA_REF_AUXIO5 0x0B +#define COMPA_REF_AUXIO4 0x0C +#define COMPA_REF_AUXIO3 0x0D +#define COMPA_REF_AUXIO2 0x0E +#define COMPA_REF_AUXIO1 0x0F +#define COMPA_REF_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7 +#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6 +#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5 +#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4 +#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3 +#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2 +#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1 +#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0 + +// Defines for input parameter to the HapiSelectADCCompBInput function. +#define ADC_COMPB_IN_NC 0x00 +#define ADC_COMPB_IN_DCOUPL 0x03 +#define ADC_COMPB_IN_VSS 0x04 +#define ADC_COMPB_IN_VDDS 0x05 +// Defines used in CC13x0/CC26x0 devices +#define ADC_COMPB_IN_AUXIO7 0x09 +#define ADC_COMPB_IN_AUXIO6 0x0A +#define ADC_COMPB_IN_AUXIO5 0x0B +#define ADC_COMPB_IN_AUXIO4 0x0C +#define ADC_COMPB_IN_AUXIO3 0x0D +#define ADC_COMPB_IN_AUXIO2 0x0E +#define ADC_COMPB_IN_AUXIO1 0x0F +#define ADC_COMPB_IN_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7 +#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6 +#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5 +#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4 +#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3 +#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2 +#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1 +#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0 + +// Defines for input parameter to the HapiSelectCompBRef function. +// The define values can not be changed! +#define COMPB_REF_NC 0x00 +#define COMPB_REF_DCOUPL 0x01 +#define COMPB_REF_VSS 0x02 +#define COMPB_REF_VDDS 0x03 + +#endif // __HAPI_H__ + +//***************************************************************************** +// +// Pointers to the main API tables. +// +//***************************************************************************** +#define ROM_API_TABLE ((uint32_t *) 0x10000180) +#define ROM_VERSION (ROM_API_TABLE[0]) + + +#define ROM_API_AON_EVENT_TABLE ((uint32_t*) (ROM_API_TABLE[1])) +#define ROM_API_AON_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[2])) +#define ROM_API_AON_RTC_TABLE ((uint32_t*) (ROM_API_TABLE[3])) +#define ROM_API_AON_WUC_TABLE ((uint32_t*) (ROM_API_TABLE[4])) +#define ROM_API_AUX_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[5])) +#define ROM_API_AUX_TDC_TABLE ((uint32_t*) (ROM_API_TABLE[6])) +#define ROM_API_AUX_TIMER_TABLE ((uint32_t*) (ROM_API_TABLE[7])) +#define ROM_API_AUX_WUC_TABLE ((uint32_t*) (ROM_API_TABLE[8])) +#define ROM_API_DDI_TABLE ((uint32_t*) (ROM_API_TABLE[9])) +#define ROM_API_FLASH_TABLE ((uint32_t*) (ROM_API_TABLE[10])) +#define ROM_API_I2C_TABLE ((uint32_t*) (ROM_API_TABLE[11])) +#define ROM_API_INTERRUPT_TABLE ((uint32_t*) (ROM_API_TABLE[12])) +#define ROM_API_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[13])) +#define ROM_API_PRCM_TABLE ((uint32_t*) (ROM_API_TABLE[14])) +#define ROM_API_SMPH_TABLE ((uint32_t*) (ROM_API_TABLE[15])) +#define ROM_API_SSI_TABLE ((uint32_t*) (ROM_API_TABLE[17])) +#define ROM_API_TIMER_TABLE ((uint32_t*) (ROM_API_TABLE[18])) +#define ROM_API_TRNG_TABLE ((uint32_t*) (ROM_API_TABLE[19])) +#define ROM_API_UART_TABLE ((uint32_t*) (ROM_API_TABLE[20])) +#define ROM_API_UDMA_TABLE ((uint32_t*) (ROM_API_TABLE[21])) +#define ROM_API_VIMS_TABLE ((uint32_t*) (ROM_API_TABLE[22])) + +// AON_EVENT FUNCTIONS +#define ROM_AONEventMcuWakeUpSet \ + ((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \ + ROM_API_AON_EVENT_TABLE[0]) + +#define ROM_AONEventMcuWakeUpGet \ + ((uint32_t (*)(uint32_t ui32MCUWUEvent)) \ + ROM_API_AON_EVENT_TABLE[1]) + +#define ROM_AONEventAuxWakeUpSet \ + ((void (*)(uint32_t ui32AUXWUEvent, uint32_t ui32EventSrc)) \ + ROM_API_AON_EVENT_TABLE[2]) + +#define ROM_AONEventAuxWakeUpGet \ + ((uint32_t (*)(uint32_t ui32AUXWUEvent)) \ + ROM_API_AON_EVENT_TABLE[3]) + +#define ROM_AONEventMcuSet \ + ((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \ + ROM_API_AON_EVENT_TABLE[4]) + +#define ROM_AONEventMcuGet \ + ((uint32_t (*)(uint32_t ui32MCUEvent)) \ + ROM_API_AON_EVENT_TABLE[5]) + + +// AON_WUC FUNCTIONS +#define ROM_AONWUCAuxReset \ + ((void (*)(void)) \ + ROM_API_AON_WUC_TABLE[3]) + +#define ROM_AONWUCRechargeCtrlConfigSet \ + ((void (*)(bool bAdaptEnable, uint32_t ui32AdaptRate, uint32_t ui32Period, uint32_t ui32MaxPeriod)) \ + ROM_API_AON_WUC_TABLE[4]) + +#define ROM_AONWUCOscConfig \ + ((void (*)(uint32_t ui32Period)) \ + ROM_API_AON_WUC_TABLE[5]) + + +// AUX_TDC FUNCTIONS +#define ROM_AUXTDCConfigSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \ + ROM_API_AUX_TDC_TABLE[0]) + +#define ROM_AUXTDCMeasurementDone \ + ((uint32_t (*)(uint32_t ui32Base)) \ + ROM_API_AUX_TDC_TABLE[1]) + + +// AUX_WUC FUNCTIONS +#define ROM_AUXWUCClockEnable \ + ((void (*)(uint32_t ui32Clocks)) \ + ROM_API_AUX_WUC_TABLE[0]) + +#define ROM_AUXWUCClockDisable \ + ((void (*)(uint32_t ui32Clocks)) \ + ROM_API_AUX_WUC_TABLE[1]) + +#define ROM_AUXWUCClockStatus \ + ((uint32_t (*)(uint32_t ui32Clocks)) \ + ROM_API_AUX_WUC_TABLE[2]) + +#define ROM_AUXWUCPowerCtrl \ + ((void (*)(uint32_t ui32PowerMode)) \ + ROM_API_AUX_WUC_TABLE[3]) + + +// FLASH FUNCTIONS +#define ROM_FlashPowerModeGet \ + ((uint32_t (*)(void)) \ + ROM_API_FLASH_TABLE[1]) + +#define ROM_FlashProtectionSet \ + ((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \ + ROM_API_FLASH_TABLE[2]) + +#define ROM_FlashProtectionGet \ + ((uint32_t (*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[3]) + +#define ROM_FlashProtectionSave \ + ((uint32_t (*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[4]) + +#define ROM_FlashEfuseReadRow \ + ((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \ + ROM_API_FLASH_TABLE[8]) + +#define ROM_FlashDisableSectorsForWrite \ + ((void (*)(void)) \ + ROM_API_FLASH_TABLE[9]) + + +// I2C FUNCTIONS +#define ROM_I2CMasterInitExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \ + ROM_API_I2C_TABLE[0]) + +#define ROM_I2CMasterErr \ + ((uint32_t (*)(uint32_t ui32Base)) \ + ROM_API_I2C_TABLE[1]) + + +// INTERRUPT FUNCTIONS +#define ROM_IntPriorityGroupingSet \ + ((void (*)(uint32_t ui32Bits)) \ + ROM_API_INTERRUPT_TABLE[0]) + +#define ROM_IntPriorityGroupingGet \ + ((uint32_t (*)(void)) \ + ROM_API_INTERRUPT_TABLE[1]) + +#define ROM_IntPrioritySet \ + ((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \ + ROM_API_INTERRUPT_TABLE[2]) + +#define ROM_IntPriorityGet \ + ((int32_t (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[3]) + +#define ROM_IntEnable \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[4]) + +#define ROM_IntDisable \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[5]) + +#define ROM_IntPendSet \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[6]) + +#define ROM_IntPendGet \ + ((bool (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[7]) + +#define ROM_IntPendClear \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[8]) + + +// IOC FUNCTIONS +#define ROM_IOCPortConfigureSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \ + ROM_API_IOC_TABLE[0]) + +#define ROM_IOCPortConfigureGet \ + ((uint32_t (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[1]) + +#define ROM_IOCIOShutdownSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \ + ROM_API_IOC_TABLE[2]) + +#define ROM_IOCIOModeSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \ + ROM_API_IOC_TABLE[4]) + +#define ROM_IOCIOIntSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \ + ROM_API_IOC_TABLE[5]) + +#define ROM_IOCIOPortPullSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \ + ROM_API_IOC_TABLE[6]) + +#define ROM_IOCIOHystSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \ + ROM_API_IOC_TABLE[7]) + +#define ROM_IOCIOInputSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \ + ROM_API_IOC_TABLE[8]) + +#define ROM_IOCIOSlewCtrlSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \ + ROM_API_IOC_TABLE[9]) + +#define ROM_IOCIODrvStrengthSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \ + ROM_API_IOC_TABLE[10]) + +#define ROM_IOCIOPortIdSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \ + ROM_API_IOC_TABLE[11]) + +#define ROM_IOCIntEnable \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[12]) + +#define ROM_IOCIntDisable \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[13]) + +#define ROM_IOCPinTypeGpioInput \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[14]) + +#define ROM_IOCPinTypeGpioOutput \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[15]) + +#define ROM_IOCPinTypeUart \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \ + ROM_API_IOC_TABLE[16]) + +#define ROM_IOCPinTypeSsiMaster \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ + ROM_API_IOC_TABLE[17]) + +#define ROM_IOCPinTypeSsiSlave \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ + ROM_API_IOC_TABLE[18]) + +#define ROM_IOCPinTypeI2c \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \ + ROM_API_IOC_TABLE[19]) + +#define ROM_IOCPinTypeAux \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[21]) + + +// PRCM FUNCTIONS +#define ROM_PRCMInfClockConfigureSet \ + ((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \ + ROM_API_PRCM_TABLE[0]) + +#define ROM_PRCMInfClockConfigureGet \ + ((uint32_t (*)(uint32_t ui32PowerMode)) \ + ROM_API_PRCM_TABLE[1]) + +#define ROM_PRCMAudioClockConfigSet \ + ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \ + ROM_API_PRCM_TABLE[4]) + +#define ROM_PRCMPowerDomainOn \ + ((void (*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[5]) + +#define ROM_PRCMPowerDomainOff \ + ((void (*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[6]) + +#define ROM_PRCMPeripheralRunEnable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[7]) + +#define ROM_PRCMPeripheralRunDisable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[8]) + +#define ROM_PRCMPeripheralSleepEnable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[9]) + +#define ROM_PRCMPeripheralSleepDisable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[10]) + +#define ROM_PRCMPeripheralDeepSleepEnable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[11]) + +#define ROM_PRCMPeripheralDeepSleepDisable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[12]) + +#define ROM_PRCMPowerDomainStatus \ + ((uint32_t (*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[13]) + +#define ROM_PRCMDeepSleep \ + ((void (*)(void)) \ + ROM_API_PRCM_TABLE[14]) + + +// SMPH FUNCTIONS +#define ROM_SMPHAcquire \ + ((void (*)(uint32_t ui32Semaphore)) \ + ROM_API_SMPH_TABLE[0]) + + +// SSI FUNCTIONS +#define ROM_SSIConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \ + ROM_API_SSI_TABLE[0]) + +#define ROM_SSIDataPut \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \ + ROM_API_SSI_TABLE[1]) + +#define ROM_SSIDataPutNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \ + ROM_API_SSI_TABLE[2]) + +#define ROM_SSIDataGet \ + ((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ + ROM_API_SSI_TABLE[3]) + +#define ROM_SSIDataGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ + ROM_API_SSI_TABLE[4]) + + +// TIMER FUNCTIONS +#define ROM_TimerConfigure \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \ + ROM_API_TIMER_TABLE[0]) + +#define ROM_TimerLevelControl \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \ + ROM_API_TIMER_TABLE[1]) + +#define ROM_TimerStallControl \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \ + ROM_API_TIMER_TABLE[3]) + +#define ROM_TimerWaitOnTriggerControl \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \ + ROM_API_TIMER_TABLE[4]) + + +// TRNG FUNCTIONS +#define ROM_TRNGNumberGet \ + ((uint32_t (*)(uint32_t ui32Word)) \ + ROM_API_TRNG_TABLE[1]) + + +// UART FUNCTIONS +#define ROM_UARTFIFOLevelGet \ + ((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \ + ROM_API_UART_TABLE[0]) + +#define ROM_UARTConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \ + ROM_API_UART_TABLE[1]) + +#define ROM_UARTConfigGetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \ + ROM_API_UART_TABLE[2]) + +#define ROM_UARTDisable \ + ((void (*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[3]) + +#define ROM_UARTCharGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[4]) + +#define ROM_UARTCharGet \ + ((int32_t (*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[5]) + +#define ROM_UARTCharPutNonBlocking \ + ((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \ + ROM_API_UART_TABLE[6]) + +#define ROM_UARTCharPut \ + ((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \ + ROM_API_UART_TABLE[7]) + + +// UDMA FUNCTIONS +#define ROM_uDMAChannelAttributeEnable \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ + ROM_API_UDMA_TABLE[0]) + +#define ROM_uDMAChannelAttributeDisable \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ + ROM_API_UDMA_TABLE[1]) + +#define ROM_uDMAChannelAttributeGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ + ROM_API_UDMA_TABLE[2]) + +#define ROM_uDMAChannelControlSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \ + ROM_API_UDMA_TABLE[3]) + +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \ + ROM_API_UDMA_TABLE[5]) + +#define ROM_uDMAChannelSizeGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[6]) + +#define ROM_uDMAChannelModeGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[7]) + + +// VIMS FUNCTIONS +#define ROM_VIMSConfigure \ + ((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \ + ROM_API_VIMS_TABLE[0]) + +#define ROM_VIMSModeSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \ + ROM_API_VIMS_TABLE[1]) + + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ROM_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom_crypto.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom_crypto.c new file mode 100644 index 0000000..84a4c26 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom_crypto.c @@ -0,0 +1,306 @@ +/******************************************************************************* +* Filename: rom_crypto.c +* Revised: 2018-09-17 08:57:21 +0200 (Mon, 17 Sep 2018) +* Revision: 52619 +* +* Description: This is the implementation for the API to the AES, ECC and +* SHA256 functions built into ROM on the CC26xx. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +*******************************************************************************/ + +#include +#include "rom_crypto.h" + +///////////////////////////////////* AES-128 *////////////////////////////////// + +/* AES - ECB */ +typedef void(*aes_ecb_encrypt_t)(uint8_t *, uint16_t, uint8_t *); +aes_ecb_encrypt_t aes_ecb_encrypt = (aes_ecb_encrypt_t)(0x10018a99); + +typedef void(*aes_ecb_decrypt_t)(uint8_t *, uint16_t, uint8_t *); +aes_ecb_decrypt_t aes_ecb_decrypt= (aes_ecb_decrypt_t)(0x10018ac5); + +//***************************************************************************** +// AES_ECB_EncryptData +//***************************************************************************** +void +AES_ECB_EncryptData(uint8_t *text, uint16_t textLen, uint8_t *aesKey) +{ + aes_ecb_encrypt(text, textLen, aesKey); +} + +//***************************************************************************** +// AES_ECB_DecryptData +//***************************************************************************** +void +AES_ECB_DecryptData(uint8_t *text, uint16_t textLen, uint8_t *aesKey) +{ + aes_ecb_decrypt(text, textLen, aesKey); +} + +/* AES - CCM */ +typedef int8_t(*aes_ccm_encrypt_t)(uint8_t, uint8_t, uint8_t *, uint8_t *, + uint16_t, uint8_t *, uint16_t, uint8_t *, + uint8_t *, uint8_t); +aes_ccm_encrypt_t aes_ccm_encrypt = (aes_ccm_encrypt_t)(0x10018a19); + +typedef int8_t(*aes_ccm_decrypt_t)(uint8_t, uint8_t, uint8_t *, uint8_t *, + uint16_t, uint8_t *, uint16_t, uint8_t *, + uint8_t *, uint8_t); +aes_ccm_decrypt_t aes_ccm_decrypt= (aes_ccm_decrypt_t)(0x10018a35); + +//***************************************************************************** +// AES_CCM_EncryptData +//***************************************************************************** +int8_t +AES_CCM_EncryptData(uint8_t encryptFlag, uint8_t MACLen, uint8_t *nonce, + uint8_t *plainText, uint16_t textLen, + uint8_t *addDataBuf, uint16_t addBufLen, + uint8_t *aesKey, uint8_t *MAC, uint8_t ccmLVal) +{ + return aes_ccm_encrypt(encryptFlag, MACLen, nonce, plainText, textLen, + addDataBuf, addBufLen, aesKey, MAC, ccmLVal); +} + +//***************************************************************************** +// AES_CCM_DecryptData +//***************************************************************************** +int8_t +AES_CCM_DecryptData(uint8_t decryptFlag, uint8_t MACLen, uint8_t *nonce, + uint8_t *cipherText, uint16_t textLen, + uint8_t *addDataBuf, uint16_t addBufLen, + uint8_t *aesKey, uint8_t *MAC, uint8_t ccmLVal) +{ + return aes_ccm_decrypt(decryptFlag, MACLen, nonce, cipherText, textLen, + addDataBuf, addBufLen, aesKey, MAC, ccmLVal); + +} + +/* AES - CTR */ +typedef uint8_t(*aes_ctr_encrypt_t)(uint8_t *, uint16_t, uint8_t *, uint8_t *, + uint8_t *); +aes_ctr_encrypt_t aes_ctr_encrypt = (aes_ctr_encrypt_t)(0x100175ed); + +typedef uint8_t(*aes_ctr_decrypt_t)(uint8_t *, uint16_t, uint8_t *, uint8_t *, + uint8_t *); +aes_ctr_decrypt_t aes_ctr_decrypt= (aes_ctr_decrypt_t)(0x10017771); + +//***************************************************************************** +// AES_CTR_EncryptData +//***************************************************************************** +uint8_t +AES_CTR_EncryptData(uint8_t *plainText, uint16_t textLen, + uint8_t *aesKey, uint8_t *nonce, + uint8_t *initVector) +{ + return aes_ctr_encrypt(plainText, textLen, aesKey, nonce, initVector); +} + +//***************************************************************************** +// AES_CTR_DecryptData +//***************************************************************************** +uint8_t +AES_CTR_DecryptData(uint8_t *cipherText, uint16_t textLen, + uint8_t *aesKey, uint8_t *nonce, + uint8_t *initVector) +{ + return aes_ctr_decrypt(cipherText, textLen, aesKey, nonce, initVector); +} + +////////////////////////////////////* ECC *//////////////////////////////////// +#ifdef ECC_PRIME_NIST256_CURVE +//#define TEST_NIST256 +//#define PARAM_P NIST256_p; +#define PARAM_P 0x10018b0c; + +//#define PARAM_R NIST256_r; +#define PARAM_R 0x10018b30; + +//#define PARAM_A NIST256_a; +#define PARAM_A 0x10018b54; + +//#define PARAM_B NIST256_b; +#define PARAM_B 0x10018b78; + +//#define PARAM_GX NIST256_Gx; +#define PARAM_GX 0x10018b9c; + +//#define PARAM_GY NIST256_Gy; +#define PARAM_GY 0x10018bc0; + +#endif + + +//***************************************************************************** +// ECC_initialize +//***************************************************************************** +void +ECC_initialize(uint32_t *pWorkzone) +{ + // Initialize curve parameters + //data_p = (uint32_t *)PARAM_P; + *((uint32_t **)0x20004f48) = (uint32_t *)PARAM_P; + + //data_r = (uint32_t *)PARAM_R; + *((uint32_t **)0x20004f4c) = (uint32_t *)PARAM_R; + + //data_a = (uint32_t *)PARAM_A; + *((uint32_t **)0x20004f50) = (uint32_t *)PARAM_A; + + //data_b = (uint32_t *)PARAM_B; + *((uint32_t **)0x20004fa8) = (uint32_t *)PARAM_B; + + //data_Gx = (uint32_t *)PARAM_GX; + *((uint32_t **)0x20004fa0) = (uint32_t *)PARAM_GX; + + //data_Gy = (uint32_t *)PARAM_GY; + *((uint32_t **)0x20004fa4) = (uint32_t *)PARAM_GY; + + // Initialize window size + //win = (uint8_t) ECC_WINDOW_SIZE; + *((uint8_t *)0x20004f40) = (uint8_t) ECC_WINDOW_SIZE; + + // Initialize work zone + //workzone = (uint32_t *) pWorkzone; + *((uint32_t **)0x20004f44) = (uint32_t *) pWorkzone; +} + +typedef uint8_t(*ecc_keygen_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *); +ecc_keygen_t ecc_generatekey = (ecc_keygen_t)(0x10017dbd); + +typedef uint8_t(*ecdsa_sign_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdsa_sign_t ecc_ecdsa_sign = (ecdsa_sign_t)(0x10017969); + +typedef uint8_t(*ecdsa_verify_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdsa_verify_t ecc_ecdsa_verify = (ecdsa_verify_t)(0x10017b01); + +typedef uint8_t(*ecdh_computeSharedSecret_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdh_computeSharedSecret_t ecdh_computeSharedSecret = (ecdh_computeSharedSecret_t)(0x10017ded); + +//***************************************************************************** +// ECC_generateKey +//***************************************************************************** +uint8_t +ECC_generateKey(uint32_t *randString, uint32_t *privateKey, + uint32_t *publicKey_x, uint32_t *publicKey_y) +{ + return (uint8_t)ecc_generatekey((uint32_t*)randString, (uint32_t*)privateKey, + (uint32_t*)publicKey_x, (uint32_t*)publicKey_y); + +} + +//***************************************************************************** +// ECC_ECDSA_sign +//***************************************************************************** +uint8_t +ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString, + uint32_t *sign1, uint32_t *sign2) +{ + return (uint8_t)ecc_ecdsa_sign((uint32_t*)secretKey, (uint32_t*)text, (uint32_t*)randString, + (uint32_t*)sign1, (uint32_t*)sign2); +} + +//***************************************************************************** +// ECC_ECDSA_verify +//***************************************************************************** +uint8_t +ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y, + uint32_t *text, uint32_t *sign1, uint32_t *sign2) +{ + return (uint8_t)ecc_ecdsa_verify((uint32_t*)publicKey_x, (uint32_t*)publicKey_y, (uint32_t*)text, + (uint32_t*)sign1, (uint32_t*)sign2); +} + +//***************************************************************************** +// ECC_ECDH_computeSharedSecret +//***************************************************************************** +uint8_t +ECC_ECDH_computeSharedSecret(uint32_t *privateKey, uint32_t *publicKey_x, + uint32_t *publicKey_y, uint32_t *sharedSecret_x, + uint32_t *sharedSecret_y) +{ + return (uint8_t)ecdh_computeSharedSecret((uint32_t*)privateKey, (uint32_t*)publicKey_x, + (uint32_t*)publicKey_y, (uint32_t*)sharedSecret_x, + (uint32_t*)sharedSecret_y); +} + + +//////////////////////////////////* SHA-256 */////////////////////////////////// + +typedef uint8_t(*sha256_full_t)(SHA256_memory_t *, uint8_t *, uint8_t *, uint32_t); +sha256_full_t sha256_runfullalg = (sha256_full_t)(0x10018129); + +typedef uint8_t(*sha256_init_t)(SHA256_memory_t *); +sha256_init_t sha256_initialize = (sha256_init_t)(0x10017ffd); + +typedef uint8_t(*sha256_process_t)(SHA256_memory_t *, uint8_t *, uint32_t); +sha256_process_t sha256_execute = (sha256_process_t)(0x10018019); + +typedef uint8_t(*sha256_final_t)(SHA256_memory_t *, uint8_t *); +sha256_final_t sha256_output = (sha256_final_t)(0x10018089); + +//***************************************************************************** +// SHA256_runFullAlgorithm +//***************************************************************************** +uint8_t +SHA256_runFullAlgorithm(SHA256_memory_t *memory, uint8_t *pBufIn, + uint32_t bufLen, uint8_t *pBufOut) +{ + return (uint8_t)sha256_runfullalg(memory, pBufOut, pBufIn, bufLen); +} + +//***************************************************************************** +// SHA256_initialize +//***************************************************************************** +uint8_t +SHA256_initialize(SHA256_memory_t *memory) +{ + return (uint8_t)sha256_initialize(memory); +} + +//***************************************************************************** +// SHA256_execute +//***************************************************************************** +uint8_t +SHA256_execute(SHA256_memory_t *memory, uint8_t *pBufIn, uint32_t bufLen) +{ + return (uint8_t)sha256_execute(memory,pBufIn, bufLen); +} + +//***************************************************************************** +// SHA256_output +//***************************************************************************** +uint8_t +SHA256_output(SHA256_memory_t *memory, uint8_t *pBufOut) +{ + return (uint8_t)sha256_output(memory, pBufOut); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom_crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom_crypto.h new file mode 100644 index 0000000..cfec1db --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom_crypto.h @@ -0,0 +1,397 @@ +/****************************************************************************** +* Filename: rom_crypto.h +* Revised: 2018-09-17 09:24:56 +0200 (Mon, 17 Sep 2018) +* Revision: 52624 +* +* Description: This header file is the API to the crypto functions +* built into ROM on the CC13xx/CC26xx. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +*******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup rom_crypto_api +//! @{ +// +//***************************************************************************** + +#ifndef ROM_CRYPTO_H +#define ROM_CRYPTO_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +///////////////////////////////////* AES-128 *////////////////////////////////// + +//***************************************************************************** +/*! + * \brief Use a random 128 bit key to encrypt data with the AES. + * + * \param text Pointer to data to encrypt. + * \param textLen Length of text. + * \param aesKey Pointer to 128 bit key used to encrypt text. + * + * \return None + */ +//***************************************************************************** +extern void AES_ECB_EncryptData(uint8_t *text, uint16_t textLen, uint8_t *aesKey); + +//***************************************************************************** +/*! + * \brief Use a random 128 bit key to decrypt data with the AES. + * + * \param text Pointer to data to decrypt. + * \param textLen Length of text. + * \param aesKey Pointer to 128 bit key used to decrypt. This is the same key + * that was used to originally encrypt this data. + * + * \return None + */ +//***************************************************************************** +extern void AES_ECB_DecryptData(uint8_t *text, uint16_t textLen, uint8_t *aesKey); + +//***************************************************************************** +/*! + * \brief Authenticate and optionally encrypt message plainText. + * + * \param encryptFlag Encryption flag. + * - set to \c true for authentication with encryption. + * - set to \c false for authentication only. + * \param MACLen Length of MAC in bytes. + * \param nonce Pointer to random nonce. Nonce length = 15 - ccmLVal. + * \param plainText Pointer to text to encrypt, input and output. + * \param textLen Length of text to encrypt. + * \param addDataBuf Pointer to additional data for authentication + * \param addBufLen Additional authentication buffer length. + * \param aesKey Pointer to the AES key or key expansion buffer. + * \param MAC Pointer to 16 byte Message Authentication Code output buffer. + * \param ccmLVal CCM L value to be used. Values {2,3}. + * + * \return Zero when successful. + */ +//***************************************************************************** +extern int8_t AES_CCM_EncryptData(uint8_t encryptFlag, uint8_t MACLen, uint8_t *nonce, + uint8_t *plainText, uint16_t textLen, + uint8_t *addDataBuf, uint16_t addBufLen, + uint8_t *aesKey, uint8_t *MAC, uint8_t ccmLVal); + +//***************************************************************************** +/*! + * \brief Authenticate and optionally decrypt message cipherText. + * + * \param decryptFlag Decryption flag. + * - \c true for authentication with decryption. + * - \c false for authentication only. + * \param MACLen Length of MAC in bytes. + * \param nonce Pointer to random nonce. Nonce length = 15 - ccmLVal. + * \param cipherText Pointer to text to decrypt, input and output. + * \param textLen Length of text to decrypt. + * \param addDataBuf Pointer to additional data for authentication + * \param addBufLen Additional authentication buffer length. + * \param aesKey Pointer to the AES key or key expansion buffer. + * \param MAC Pointer to 16 byte Message Authentication Code output buffer. + * \param ccmLVal CCM L value to be used. Values {2,3}. + * + * \return Zero when Successful. + */ +//***************************************************************************** +extern int8_t AES_CCM_DecryptData(uint8_t decryptFlag, uint8_t MACLen, uint8_t *nonce, + uint8_t *cipherText, uint16_t textLen, + uint8_t *addDataBuf, uint16_t addBufLen, + uint8_t *aesKey, uint8_t *MAC, uint8_t ccmLVal); + +//***************************************************************************** +/*! + * \brief Encrypt plaintext using the AES key, nonce and initialization vector. + * + * \param plainText Pointer to text to encrypt. + * \param textLen Length of text. + * \param aesKey Pointer to 128 bit key used to encrypt text. + * \param nonce Pointer to 4 byte nonce. + * \param initVector Pointer to 8 byte random initialization vector. + * + * \return None + */ +//***************************************************************************** +extern uint8_t AES_CTR_EncryptData(uint8_t *plainText, uint16_t textLen, + uint8_t *aesKey, uint8_t *nonce, + uint8_t *initVector); + +//***************************************************************************** +/*! + * \brief Decrypt ciphertext using the AES key, nonce and initialization vector. + * + * \param cipherText Pointer to text to decrypt + * \param textLen Length of text. + * \param aesKey Pointer to 128 bit key used to encrypt text. + * \param nonce Pointer to 4 byte nonce. + * \param initVector Pointer to 8 byte random initialization vector. + * + * \return None + */ +//***************************************************************************** +extern uint8_t AES_CTR_DecryptData(uint8_t *cipherText, uint16_t textLen, + uint8_t *aesKey, uint8_t *nonce, + uint8_t *initVector); + +////////////////////////////////////* ECC *///////////////////////////////////// + +/* Window size, valid values are 2,3,4,5. + * Higher the value, faster the computation at the expense of memory usage. + * + * Recommended workzone size (in 4-byte words) + * Window size: 3, Workzone size: 275 + * + */ +#define ECC_WINDOW_SIZE 3 + +/* + * ECC Supported Curves, define one: + * ECC_PRIME_NIST256_CURVE + */ +#define ECC_PRIME_NIST256_CURVE + +/* + * ECC Return Status Flags. + */ +// Scalar multiplication status +#define ECC_MODULUS_EVEN 0xDC +#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2 +#define ECC_MODULUS_LENGTH_ZERO 0x08 +#define ECC_MODULUS_MSW_IS_ZERO 0x30 +#define ECC_SCALAR_TOO_LONG 0x35 +#define ECC_SCALAR_LENGTH_ZERO 0x53 +#define ECC_ORDER_TOO_LONG 0xC6 +#define ECC_ORDER_LENGTH_ZERO 0x6C +#define ECC_X_COORD_TOO_LONG 0x3C +#define ECC_X_COORD_LENGTH_ZERO 0xC3 +#define ECC_Y_COORD_TOO_LONG 0x65 +#define ECC_Y_COORD_LENGTH_ZERO 0x56 +#define ECC_A_COEF_TOO_LONG 0x5C +#define ECC_A_COEF_LENGTH_ZERO 0xC5 +#define ECC_BAD_WINDOW_SIZE 0x66 +#define ECC_SCALAR_MUL_OK 0x99 + +// ECDSA and ECDH status +#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28 +#define ECC_ORDER_EVEN 0x82 +#define ECC_ORDER_MSW_IS_ZERO 0x23 +#define ECC_ECC_KEY_TOO_LONG 0x25 +#define ECC_ECC_KEY_LENGTH_ZERO 0x52 +#define ECC_DIGEST_TOO_LONG 0x27 +#define ECC_DIGEST_LENGTH_ZERO 0x72 +#define ECC_ECDSA_SIGN_OK 0x32 +#define ECC_ECDSA_INVALID_SIGNATURE 0x5A +#define ECC_ECDSA_VALID_SIGNATURE 0xA5 +#define ECC_SIG_P1_TOO_LONG 0x11 +#define ECC_SIG_P1_LENGTH_ZERO 0x12 +#define ECC_SIG_P2_TOO_LONG 0x22 +#define ECC_SIG_P2_LENGTH_ZERO 0x21 + +#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK + +//***************************************************************************** +/*! + * \brief Pass pointer to ECC memory allocation to ECC engine. + * + * This function can be called again to point the ECC workzone at + * a different memory buffer. + * + * \param pWorkzone Pointer to memory allocated for computations, input. + * See description at beginning of ECC section for + * memory requirements. + * + * \return None + */ +//***************************************************************************** + extern void ECC_initialize(uint32_t *pWorkzone); + +//***************************************************************************** + /*! + * \brief Generate a key. + * + * This is used for both ECDH and ECDSA. + * + * \param randString Pointer to random string, input. + * \param privateKey Pointer to the private key, output. + * \param publicKey_x Pointer to public key X-coordinate, output. + * \param publicKey_y Pointer to public key Y-coordinate, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_generateKey(uint32_t *randString, uint32_t *privateKey, + uint32_t *publicKey_x, uint32_t *publicKey_y); + +//***************************************************************************** +/*! + * \brief Sign data. + * + * \param secretKey Pointer to the secret key, input. + * \param text Pointer to the message, input. + * \param randString Pointer to random string, input. + * \param sign1 Pointer to signature part 1, output. + * \param sign2 Pointer to signature part 2, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString, + uint32_t *sign1, uint32_t *sign2); + +//***************************************************************************** +/*! + * \brief Verify signature. + * + * \param publicKey_x Pointer to public key X-coordinate, input. + * \param publicKey_y Pointer to public key Y-coordinate, input. + * \param text Pointer to message data, input. + * \param sign1 Pointer to signature part 1, input. + * \param sign2 Pointer to signature part 2, input. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y, + uint32_t *text, uint32_t *sign1, uint32_t *sign2); + +//***************************************************************************** +/*! + * \brief Compute the shared secret. + * + * \param privateKey Pointer to private key, input. + * \param publicKey_x Pointer to public key X-coordinate, input. + * \param publicKey_y Pointer to public key Y-coordinate, input. + * \param sharedSecret_x Pointer to shared secret X-coordinate, output. + * \param sharedSecret_y Pointer to shared secret Y-coordinate, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDH_computeSharedSecret(uint32_t *privateKey, + uint32_t *publicKey_x, + uint32_t *publicKey_y, + uint32_t *sharedSecret_x, + uint32_t *sharedSecret_y); + + +///////////////////////////////////* SHA-256 *////////////////////////////////// + +//! \brief A SHA256_memory_t variable of this type must be allocated before running any +//! SHA256 functions. +typedef struct +{ + uint32_t state[8]; + uint32_t textLen[2]; + uint32_t W[16]; +} SHA256_memory_t; + +//***************************************************************************** +/*! + * \brief Perform SHA256 on the input data. + * + * The input and output buffer can point to the same memory. + * This is the equivalent of calling \ref SHA256_initialize(), + * \ref SHA256_execute() and \ref SHA256_output() sequentially. + * + * \param memory Pointer to memory for operations, input. + * \param pBufIn Pointer to input buffer, input. + * \param bufLen Length of input. + * \param pBufOut Pointer to output buffer, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t SHA256_runFullAlgorithm(SHA256_memory_t *memory, uint8_t *pBufIn, + uint32_t bufLen, uint8_t *pBufOut); + +//***************************************************************************** +/*! + * \brief Intializes the SHA256 engine. + * + * This function must be called once before all other SHA256 functions other than + * \ref SHA256_runFullAlgorithm(). + * + * \param workZone Pointer to memory for operations, input. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t SHA256_initialize(SHA256_memory_t *workZone); + +//***************************************************************************** +/*! + * \brief Perform SHA256. + * + * Must call \ref SHA256_output() to receive output from this operation. + * + * \param config Pointer to memory for operations, input. + * \param pBufIn Pointer to input text, input. + * \param bufLen Length of input, input. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t SHA256_execute(SHA256_memory_t *config, uint8_t *pBufIn, + uint32_t bufLen); + +//***************************************************************************** +/*! + * \brief Complete the process by passing the modified data back. + * + * \param memory Pointer to memory for operations, input. + * \param pBufOut Pointer to output buffer, output. Buffer must be at least 32 bytes long. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t SHA256_output(SHA256_memory_t *memory, uint8_t *pBufOut); + +#ifdef __cplusplus +} +#endif + +#endif /* ROM_CRYPTO_H */ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup.c new file mode 100644 index 0000000..1dda53c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup.c @@ -0,0 +1,355 @@ +/****************************************************************************** +* Filename: setup.c +* Revised: 2018-11-06 15:08:57 +0100 (Tue, 06 Nov 2018) +* Revision: 53239 +* +* Description: Setup file for CC13xx/CC26xx devices. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +// Hardware headers +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_2_refsys.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_aon_ioc.h" +#include "../inc/hw_aon_sysctl.h" +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_aux_wuc.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_flash.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_vims.h" +// Driverlib headers +#include "aon_wuc.h" +#include "aux_wuc.h" +#include "chipinfo.h" +#include "setup.h" +#include "setup_rom.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SetupTrimDevice + #define SetupTrimDevice NOROM_SetupTrimDevice +#endif + + + +//***************************************************************************** +// +// Defined CPU delay macro with microseconds as input +// Quick check shows: (To be further investigated) +// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 5 cycles +// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 1, there is 4 cycles +// At 24 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 3 cycles +// +//***************************************************************************** +#define CPU_DELAY_MICRO_SECONDS( x ) \ + CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 ) + + +//***************************************************************************** +// +// Function declarations +// +//***************************************************************************** +static void TrimAfterColdReset( void ); +static void TrimAfterColdResetWakeupFromShutDown( uint32_t ui32Fcfg1Revision ); +static void TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void ); + +//***************************************************************************** +// +// Perform the necessary trim of the device which is not done in boot code +// +// This function should only execute coming from ROM boot. The current +// implementation does not take soft reset into account. However, it does no +// damage to execute it again. It only consumes time. +// +//***************************************************************************** +void +SetupTrimDevice(void) +{ + uint32_t ui32Fcfg1Revision; + uint32_t ui32AonSysResetctl; + + // Get layout revision of the factory configuration area + // (Handle undefined revision as revision = 0) + ui32Fcfg1Revision = HWREG(FCFG1_BASE + FCFG1_O_FCFG1_REVISION); + if ( ui32Fcfg1Revision == 0xFFFFFFFF ) { + ui32Fcfg1Revision = 0; + } + + // This driverlib version and setup file is for CC26x0 PG2.2 and later + // Halt if violated + ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated(); + + // Enable standby in flash bank + HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Clock must always be enabled for the semaphore module (due to ADI/DDI HW workaround) + HWREG( AUX_WUC_BASE + AUX_WUC_O_MODCLKEN1 ) = AUX_WUC_MODCLKEN1_SMPH; + + // Warm resets on CC13x0 and CC26x0 complicates software design because much of + // our software expect that initialization is done from a full system reset. + // This includes RTC setup, oscillator configuration and AUX setup. + // To ensure a full reset of the device is done when customers get e.g. a Watchdog + // reset, the following is set here: + HWREGBITW( PRCM_BASE + PRCM_O_WARMRESET, PRCM_WARMRESET_WR_TO_PINRESET_BITN ) = 1; + + // Select correct CACHE mode and set correct CACHE configuration +#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) + SetupSetCacheModeAccordingToCcfgSetting(); +#else + NOROM_SetupSetCacheModeAccordingToCcfgSetting(); +#endif + + // 1. Check for powerdown + // 2. Check for shutdown + // 3. Assume cold reset if none of the above. + // + // It is always assumed that the application will freeze the latches in + // AON_IOC when going to powerdown in order to retain the values on the IOs. + // + // NB. If this bit is not cleared before proceeding to powerdown, the IOs + // will all default to the reset configuration when restarting. + if( ! ( HWREGBITW( AON_IOC_BASE + AON_IOC_O_IOCLATCH, AON_IOC_IOCLATCH_EN_BITN ))) + { + // NB. This should be calling a ROM implementation of required trim and + // compensation + // e.g. TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown() + TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + } + // Check for shutdown + // + // When device is going to shutdown the hardware will automatically clear + // the SLEEPDIS bit in the SLEEP register in the AON_SYSCTL module. + // It is left for the application to assert this bit when waking back up, + // but not before the desired IO configuration has been re-established. + else if( ! ( HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_SLEEPCTL, AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN ))) + { + // NB. This should be calling a ROM implementation of required trim and + // compensation + // e.g. TrimAfterColdResetWakeupFromShutDown() --> + // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision); + TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + } + else + { + // Consider adding a check for soft reset to allow debugging to skip + // this section!!! + // + // NB. This should be calling a ROM implementation of required trim and + // compensation + // e.g. TrimAfterColdReset() --> + // TrimAfterColdResetWakeupFromShutDown() --> + // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown() + TrimAfterColdReset(); + TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision); + TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + + } + + // Set VIMS power domain control. + // PDCTL1VIMS = 0 ==> VIMS power domain is only powered when CPU power domain is powered + HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0; + + // Configure optimal wait time for flash FSM in cases where flash pump + // wakes up from sleep + HWREG(FLASH_BASE + FLASH_O_FPAC1) = (HWREG(FLASH_BASE + FLASH_O_FPAC1) & + ~FLASH_FPAC1_PSLEEPTDIS_M) | + (0x139<> + AON_SYSCTL_RESETCTL_BOOT_DET_0_S ) == 1 ) + { + ui32AonSysResetctl = ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) & + ~( AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M | + AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M )); + HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = ui32AonSysResetctl | AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M; + HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = ui32AonSysResetctl; + } + + // Make sure there are no ongoing VIMS mode change when leaving SetupTrimDevice() + // (There should typically be no wait time here, but need to be sure) + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for an eventual ongoing mode change to complete. + } +} + +//***************************************************************************** +// +//! \brief Trims to be applied when coming from POWER_DOWN (also called when +//! coming from SHUTDOWN and PIN_RESET). +//! +//! \return None +// +//***************************************************************************** +static void +TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void ) +{ + // Currently no specific trim for Powerdown +} + +//***************************************************************************** +// +//! \brief Trims to be applied when coming from SHUTDOWN (also called when +//! coming from PIN_RESET). +//! +//! \param ui32Fcfg1Revision +//! +//! \return None +// +//***************************************************************************** +static void +TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision) +{ + uint32_t ccfg_ModeConfReg ; + uint32_t mp1rev ; + + // Force AUX on and enable clocks + // + // No need to save the current status of the power/clock registers. + // At this point both AUX and AON should have been reset to 0x0. + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) = AON_WUC_AUXCTL_AUX_FORCE_ON; + + // Wait for power on on the AUX domain + while( ! ( HWREGBITW( AON_WUC_BASE + AON_WUC_O_PWRSTAT, AON_WUC_PWRSTAT_AUX_PD_ON_BITN ))); + + // Enable the clocks for AUX_DDI0_OSC and AUX_ADI4 + HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) = AUX_WUC_MODCLKEN0_AUX_DDI0_OSC | + AUX_WUC_MODCLKEN0_AUX_ADI4; + + // It's found to be optimal to override the FCFG1..DCDC_IPEAK setting as follows: + // if ( alternative DCDC setting in CCFG is enabled ) ADI3..IPEAK = CCFG..DCDC_IPEAK + // else ADI3..IPEAK = 2 + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) { + // ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19] (=ALT_DCDC_DITHER_EN) + // ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) = CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) + // Using a single 4-bit masked write since layout is equal for both source and destination + HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 | + ( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S )); + + } else { + HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = 0x72; + } + + // + // Enable for JTAG to be powered down (will still be powered on if debugger is connected) + AONWUCJtagPowerOff(); + + // read the MODE_CONF register in CCFG + ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + + // First part of trim done after cold reset and wakeup from shutdown: + // -Adjust the VDDR_TRIM_SLEEP value. + // -Configure DCDC. + SetupAfterColdResetWakeupFromShutDownCfg1( ccfg_ModeConfReg ); + + // Second part of trim done after cold reset and wakeup from shutdown: + // -Configure XOSC. +#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) + SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg ); +#else + NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg ); +#endif + + // Increased margin between digital supply voltage and VDD BOD during standby. + // VTRIM_UDIG: signed 4 bits value to be incremented by 2 (max = 7) + // VTRIM_BOD: unsigned 4 bits value to be decremented by 1 (min = 0) + // This applies to chips with mp1rev < 542 for cc13x0 and for mp1rev < 527 for cc26x0 + mp1rev = (( HWREG( FCFG1_BASE + FCFG1_O_TRIM_CAL_REVISION ) & FCFG1_TRIM_CAL_REVISION_MP1_M ) >> + FCFG1_TRIM_CAL_REVISION_MP1_S ) ; + if ( mp1rev < 527 ) { + uint32_t ldoTrimReg = HWREG( FCFG1_BASE + FCFG1_O_BAT_RC_LDO_TRIM ); + uint32_t vtrim_bod = (( ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M ) >> + FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_S ); // bit[27:24] unsigned + uint32_t vtrim_udig = (( ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M ) >> + FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_S ); // bit[19:16] signed but treated as unsigned + if ( vtrim_bod > 0 ) { + vtrim_bod -= 1; + } + if ( vtrim_udig != 7 ) { + if ( vtrim_udig == 6 ) { + vtrim_udig = 7; + } else { + vtrim_udig = (( vtrim_udig + 2 ) & 0xF ); + } + } + HWREGB( ADI2_BASE + ADI_2_REFSYS_O_SOCLDOCTL0 ) = + ( vtrim_udig << ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S ) | + ( vtrim_bod << ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S ) ; + } + + // Third part of trim done after cold reset and wakeup from shutdown: + // -Configure HPOSC. + // -Setup the LF clock. +#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) + SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg ); +#else + NOROM_SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg ); +#endif + + // Allow AUX to power down + AUXWUCPowerCtrl( AUX_WUC_POWER_DOWN ); + + // Leaving on AUX and clock for AUX_DDI0_OSC on but turn off clock for AUX_ADI4 + HWREG( AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0 ) = AUX_WUC_MODCLKEN0_AUX_DDI0_OSC; + + // Disable EFUSE clock + HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1; +} + + +//***************************************************************************** +// +//! \brief Trims to be applied when coming from PIN_RESET. +//! +//! \return None +// +//***************************************************************************** +static void +TrimAfterColdReset( void ) +{ + // Currently no specific trim for Cold Reset +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup.h new file mode 100644 index 0000000..496b17a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup.h @@ -0,0 +1,141 @@ +/****************************************************************************** +* Filename: setup.h +* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) +* Revision: 52993 +* +* Description: Prototypes and defines for the setup API. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup setup_api +//! @{ +// +//***************************************************************************** + +#ifndef __SETUP_H__ +#define __SETUP_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +// Hardware headers +#include "../inc/hw_types.h" +// Driverlib headers +// - None needed + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SetupTrimDevice NOROM_SetupTrimDevice +#endif + +//***************************************************************************** +// +//! \brief Performs the necessary trim of the device which is not done in ROM boot code. +//! +//! This function should only execute coming from ROM boot. +//! +//! The following is handled by this function: +//! - Checks if the driverlib variant used by the application is supported by the +//! device. Execution is halted in case of unsupported driverlib variant. +//! - Configures VIMS cache mode based on setting in CCFG. +//! - Configures functionalities like DCDC and XOSC dependent on startup modes like +//! cold reset, wakeup from shutdown and wakeup from from powerdown. +//! - Configures VIMS power domain control. +//! - Configures optimal wait time for flash FSM in cases where flash pump wakes up from sleep. +//! +//! \note The current implementation does not take soft reset into account. However, +//! it does no damage to execute it again. It only consumes time. +//! +//! \note This function is called by the compiler specific device startup codes +//! that are integrated in the SimpleLink SDKs for CC13xx/CC26XX devices. +//! +//! \return None +// +//***************************************************************************** +extern void SetupTrimDevice( void ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SetupTrimDevice + #undef SetupTrimDevice + #define SetupTrimDevice ROM_SetupTrimDevice + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SETUP_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_doc.h new file mode 100644 index 0000000..07ab97e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_doc.h @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: setup_doc.h +* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) +* Revision: 49096 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup setup_api +//! @{ +//! +//! This module contains functions for device setup which is not done in boot code. +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom.c new file mode 100644 index 0000000..02db337 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom.c @@ -0,0 +1,896 @@ +/****************************************************************************** +* Filename: setup_rom.c +* Revised: 2017-11-02 11:31:15 +0100 (Thu, 02 Nov 2017) +* Revision: 50143 +* +* Description: Setup file for CC13xx/CC26xx devices. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +// Hardware headers +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_2_refsys.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_adi_4_aux.h" +#include "../inc/hw_aon_batmon.h" +#include "../inc/hw_aon_sysctl.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ddi_0_osc.h" +#include "../inc/hw_fcfg1.h" +// Driverlib headers +#include "ddi.h" +#include "ioc.h" +#include "osc.h" +#include "sys_ctrl.h" +#include "setup_rom.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SetupAfterColdResetWakeupFromShutDownCfg1 + #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #undef SetupAfterColdResetWakeupFromShutDownCfg2 + #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #undef SetupAfterColdResetWakeupFromShutDownCfg3 + #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #undef SetupGetTrimForAdcShModeEn + #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn + #undef SetupGetTrimForAdcShVbufEn + #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn + #undef SetupGetTrimForAmpcompCtrl + #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl + #undef SetupGetTrimForAmpcompTh1 + #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 + #undef SetupGetTrimForAmpcompTh2 + #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 + #undef SetupGetTrimForAnabypassValue1 + #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 + #undef SetupGetTrimForDblrLoopFilterResetVoltage + #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage + #undef SetupGetTrimForRadcExtCfg + #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg + #undef SetupGetTrimForRcOscLfIBiasTrim + #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim + #undef SetupGetTrimForRcOscLfRtuneCtuneTrim + #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #undef SetupGetTrimForXoscHfCtl + #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl + #undef SetupGetTrimForXoscHfFastStart + #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart + #undef SetupGetTrimForXoscHfIbiastherm + #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm + #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #undef SetupSetCacheModeAccordingToCcfgSetting + #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting + #undef SetupSetAonRtcSubSecInc + #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc +#endif + +//***************************************************************************** +// +// Function declarations +// +//***************************************************************************** + +//***************************************************************************** +// +// SetupAfterColdResetWakeupFromShutDownCfg1 +// +//***************************************************************************** +void +SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ) +{ + int32_t i32VddrSleepTrim; + int32_t i32VddrSleepDelta; + + { + i32VddrSleepTrim = SetupSignExtendVddrTrimValue(( + HWREG( FCFG1_BASE + FCFG1_O_LDO_TRIM ) & + FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M ) >> + FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S ) ; + } + + // Adjust the VDDR_TRIM_SLEEP value with value adjustable by customer (CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA) + // Read and sign extend VddrSleepDelta (in range -8 to +7) + i32VddrSleepDelta = + (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ))) + >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W )); + // Calculate new VDDR sleep trim + i32VddrSleepTrim = ( i32VddrSleepTrim + i32VddrSleepDelta + 1 ); + if ( i32VddrSleepTrim > 21 ) i32VddrSleepTrim = 21; + if ( i32VddrSleepTrim < -10 ) i32VddrSleepTrim = -10; + // Write adjusted value using MASKED write (MASK8) + HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_DCDCCTL1 * 2 )) = (( ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M << 8 ) | + (( i32VddrSleepTrim << ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S ) & ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M )); + + // 1. + // Do not allow DCDC to be enabled if in external regulator mode. + // Preventing this by setting both the RECHARGE and the ACTIVE bits bit in the CCFG_MODE_CONF copy register (ccfg_ModeConfReg). + // + // 2. + // Adjusted battery monitor low limit in internal regulator mode. + // This is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode. + if ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE ) { + ccfg_ModeConfReg |= ( CCFG_MODE_CONF_DCDC_RECHARGE_M | CCFG_MODE_CONF_DCDC_ACTIVE_M ); + } else { + HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0; + } + + // set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE + // Note: Inverse polarity + HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL, AON_SYSCTL_PWRCTL_DCDC_EN_BITN ) = + ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_RECHARGE_S ) & 1 ) ^ 1 ); + + // set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE + // Note: Inverse polarity + HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL, AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN ) = + ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_ACTIVE_S ) & 1 ) ^ 1 ); +} + +//***************************************************************************** +// +// SetupAfterColdResetWakeupFromShutDownCfg2 +// +//***************************************************************************** +void +SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ) +{ + uint32_t ui32Trim; + + // Following sequence is required for using XOSCHF, if not included + // devices crashes when trying to switch to XOSCHF. + // + // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1 + // register + ui32Trim = SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg ); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim); + + // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and + // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register. + ui32Trim = SetupGetTrimForRcOscLfRtuneCtuneTrim(); + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL, + (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M | + DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M), + DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S, + ui32Trim); + + // Trim XOSCHF IBIAS THERM. Get and set trim value for the + // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other + // register bit fields are set to 0. + ui32Trim = SetupGetTrimForXoscHfIbiastherm(); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2, + ui32Trim< writing to bits[7:4] + ui32Trim = SetupGetTrimForAdcShModeEn( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = + ( 0x20 | ( ui32Trim << 1 )); + + // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance to FCFG1 setting + // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register + // Using MASK4 write + 1 => writing to bits[7:4] + ui32Trim = SetupGetTrimForAdcShVbufEn( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = + ( 0x10 | ( ui32Trim )); + + // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields + // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting. + // Remaining register bit fields are set to their reset values of 0. + ui32Trim = SetupGetTrimForXoscHfCtl(ui32Fcfg1Revision); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim); + + // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting + // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL) + // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4)) + // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and + // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000) + ui32Trim = SetupGetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) = + ( 0x60 | ( ui32Trim << 1 )); + + // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from + // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM + // This is DDI_0_OSC_O_ATESTCTL bit[7] + // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020)) + // Using MASK4 write + 1 => writing to bits[7:4] + ui32Trim = SetupGetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) = + ( 0x80 | ( ui32Trim << 3 )); + + // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and + // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write + // This can be simplified since the registers are packed together in the same + // order both in FCFG1 and in the HW register. + // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18] + // Using MASK8 write + 4 => writing to bits[23:16] + ui32Trim = SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision ); + HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) = + ( 0xFC00 | ( ui32Trim << 2 )); + + // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit + // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting. + // Remaining register bit fields are set to their reset values of 0. + ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim); + + // Setting FORCE_KICKSTART_EN (ref. CC26_V1_BUG00261). Should also be done for PG2 + // (This is bit 22 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_FORCE_KICKSTART_EN; +} + +//***************************************************************************** +// +// SetupAfterColdResetWakeupFromShutDownCfg3 +// +//***************************************************************************** +void +SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) +{ + uint32_t fcfg1OscConf; + uint32_t ui32Trim; + uint32_t currentHfClock; + uint32_t ccfgExtLfClk; + + // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC + switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) { + case 2 : + // XOSC source is a 48 MHz crystal + // Do nothing (since this is the reset setting) + break; + case 1 : + // XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, otherwise skip trimming and default to 24 MHz XOSC) + + fcfg1OscConf = HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ); + + if (( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION ) == 0 ) { + // This is a HPOSC chip, apply HPOSC settings + // Set bit DDI_0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_HPOSC_MODE_EN; + + // ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit) + // ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits) + // ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET = FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits) + // ADI_2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN (1 bit) + // ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits) + // ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP = FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits) + // ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS = FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit) + + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) & + ~( ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M | ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M ) ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S ) << ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M ) >> FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S ) << ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S ) ); + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) & ~( ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M ) ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S ) << ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S ) ); + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) & + ~( ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M | ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M | ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M | ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M )) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_FILTER_EN_M ) >> FCFG1_OSC_CONF_HPOSC_FILTER_EN_S ) << ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S ) << ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M ) >> FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S ) << ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M ) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S ) << ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S ) ); + break; + } + // Not a HPOSC chip - fall through to default + default : + // XOSC source is a 24 MHz crystal (default) + // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M; + break; + } + + // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO + // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used. + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) { + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS; + } + + // Clear DDI_0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 in DDI_0_OSC_O_CTL0. + // This is typically already 0 except on Lizard where it is set in ROM-boot + HWREG( AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN; + + // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1 + ui32Trim = SetupGetTrimForXoscHfFastStart(); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim ); + + // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION + switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) { + case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz) + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF ); + SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency + break; + case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT) + // Set SCLK_LF to use the same source as SCLK_HF + // Can be simplified a bit since possible return values for HF matches LF settings + currentHfClock = OSCClockSourceGet( OSC_SRC_CLK_HF ); + OSCClockSourceSet( OSC_SRC_CLK_LF, currentHfClock ); + while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != currentHfClock ) { + // Wait until switched + } + ccfgExtLfClk = HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ); + SetupSetAonRtcSubSecInc(( ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) >> CCFG_EXT_LF_CLK_RTC_INCREMENT_S ); + IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S, + IOC_PORT_AON_CLK32K, + IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis + // Set XOSC_LF in bypass mode to allow external 32 kHz clock + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS; + // Fall through to set XOSC_LF as SCLK_LF source + case 2 : // XOSC_LF -> SLCK_LF (32768 Hz) + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF ); + break; + default : // (=3) RCOSC_LF + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF ); + break; + } + + // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1 + HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) = + ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >> + FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) << + ADI_4_AUX_ADCREF1_VTRIM_S ) & + ADI_4_AUX_ADCREF1_VTRIM_M ); + + // Sync with AON + SysCtrlAonSync(); +} + +//***************************************************************************** +// +// SetupGetTrimForAnabypassValue1 +// +//***************************************************************************** +uint32_t +SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ) +{ + uint32_t ui32Fcfg1Value ; + uint32_t ui32XoscHfRow ; + uint32_t ui32XoscHfCol ; + uint32_t ui32TrimValue ; + + // Use device specific trim values located in factory configuration + // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in + // the ANABYPASS_VALUE1 register. Value for the other bit fields + // are set to 0. + + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP); + ui32XoscHfRow = (( ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S ); + ui32XoscHfCol = (( ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S ); + + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) { + // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation + // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg + // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by + // a define and sign extension must therefore be hard coded. + // ( A small test program is created verifying the code lines below: + // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c) + int32_t i32CustomerDeltaAdjust = + (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ))) + >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W )); + + while ( i32CustomerDeltaAdjust < 0 ) { + ui32XoscHfCol >>= 1; // COL 1 step down + if ( ui32XoscHfCol == 0 ) { // if COL below minimum + ui32XoscHfCol = 0xFFFF; // Set COL to maximum + ui32XoscHfRow >>= 1; // ROW 1 step down + if ( ui32XoscHfRow == 0 ) { // if ROW below minimum + ui32XoscHfRow = 1; // Set both ROW and COL + ui32XoscHfCol = 1; // to minimum + } + } + i32CustomerDeltaAdjust++; + } + while ( i32CustomerDeltaAdjust > 0 ) { + ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up + if ( ui32XoscHfCol > 0xFFFF ) { // if COL above maximum + ui32XoscHfCol = 1; // Set COL to minimum + ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up + if ( ui32XoscHfRow > 0xF ) { // if ROW above maximum + ui32XoscHfRow = 0xF; // Set both ROW and COL + ui32XoscHfCol = 0xFFFF; // to maximum + } + } + i32CustomerDeltaAdjust--; + } + } + + ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) | + ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) ); + + return (ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForRcOscLfRtuneCtuneTrim +// +//***************************************************************************** +uint32_t +SetupGetTrimForRcOscLfRtuneCtuneTrim( void ) +{ + uint32_t ui32TrimValue; + + // Use device specific trim values located in factory configuration + // area + ui32TrimValue = + ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<< + DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S; + + ui32TrimValue |= + ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<< + DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S; + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscHfIbiastherm +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscHfIbiastherm( void ) +{ + uint32_t ui32TrimValue; + + // Use device specific trim value located in factory configuration + // area + ui32TrimValue = + (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) & + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>> + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S; + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForAmpcompTh2 +// +//***************************************************************************** +uint32_t +SetupGetTrimForAmpcompTh2( void ) +{ + uint32_t ui32TrimValue; + uint32_t ui32Fcfg1Value; + + // Use device specific trim value located in factory configuration + // area. All defined register bit fields have corresponding trim + // value in the factory configuration area + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2); + ui32TrimValue = ((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>> + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<< + DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S; + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>> + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<< + DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<< + DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<< + DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S); + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForAmpcompTh1 +// +//***************************************************************************** +uint32_t +SetupGetTrimForAmpcompTh1( void ) +{ + uint32_t ui32TrimValue; + uint32_t ui32Fcfg1Value; + + // Use device specific trim values located in factory configuration + // area. All defined register bit fields have a corresponding trim + // value in the factory configuration area + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1); + ui32TrimValue = (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>> + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<< + DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S); + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForAmpcompCtrl +// +//***************************************************************************** +uint32_t +SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ) +{ + uint32_t ui32TrimValue ; + uint32_t ui32Fcfg1Value ; + uint32_t ibiasOffset ; + uint32_t ibiasInit ; + uint32_t modeConf1 ; + int32_t deltaAdjust ; + + // Use device specific trim values located in factory configuration + // area. Register bit fields without trim values in the factory + // configuration area will be set to the value of 0. + ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 ); + + ibiasOffset = ( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ; + ibiasInit = ( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ; + + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) { + // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG + modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ); + + // Both fields are signed 4-bit values. This is an assumption when doing the sign extension. + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W )); + deltaAdjust += (int32_t)ibiasOffset; + if ( deltaAdjust < 0 ) { + deltaAdjust = 0; + } + if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) { + deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ); + } + ibiasOffset = (uint32_t)deltaAdjust; + + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W )); + deltaAdjust += (int32_t)ibiasInit; + if ( deltaAdjust < 0 ) { + deltaAdjust = 0; + } + if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) { + deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ); + } + ibiasInit = (uint32_t)deltaAdjust; + } + ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) | + ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ; + + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>> + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<< + DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>> + FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<< + DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>> + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<< + DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S); + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + ui32TrimValue |= ((( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >> + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) << + DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S ); + } + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForDblrLoopFilterResetVoltage +// +//***************************************************************************** +uint32_t +SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ) +{ + uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) & + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >> + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S; + } + + return ( dblrLoopFilterResetVoltageValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForAdcShModeEn +// +//***************************************************************************** +uint32_t +SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForAdcShModeEnValue = 1; // Recommended default setting + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >> + FCFG1_OSC_CONF_ADC_SH_MODE_EN_S; + } + + return ( getTrimForAdcShModeEnValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForAdcShVbufEn +// +//***************************************************************************** +uint32_t +SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForAdcShVbufEnValue = 1; // Recommended default setting + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >> + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S; + } + + return ( getTrimForAdcShVbufEnValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscHfCtl +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForXoschfCtlValue = 0; // Recommended default setting + uint32_t fcfg1Data; + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); + getTrimForXoschfCtlValue = + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S); + + getTrimForXoschfCtlValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S); + + getTrimForXoschfCtlValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S); + } + + return ( getTrimForXoschfCtlValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscHfFastStart +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscHfFastStart( void ) +{ + uint32_t ui32XoscHfFastStartValue ; + + // Get value from FCFG1 + ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >> + FCFG1_OSC_CONF_XOSC_HF_FAST_START_S; + + return ( ui32XoscHfFastStartValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForRadcExtCfg +// +//***************************************************************************** +uint32_t +SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommended default setting + uint32_t fcfg1Data; + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); + getTrimForRadcExtCfgValue = + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >> + FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) << + DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S); + + getTrimForRadcExtCfgValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >> + FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) << + DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S); + + getTrimForRadcExtCfgValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >> + FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) << + DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S); + } + + return ( getTrimForRadcExtCfgValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForRcOscLfIBiasTrim +// +//***************************************************************************** +uint32_t +SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ) +{ + uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >> + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ; + } + + return ( trimForRcOscLfIBiasTrimValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ) +{ + uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M | + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >> + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ; + } + + return ( trimForXoscLfRegulatorAndCmirrwrRatioValue ); +} + +//***************************************************************************** +// +// SetupSetCacheModeAccordingToCcfgSetting +// +//***************************************************************************** +void +SetupSetCacheModeAccordingToCcfgSetting( void ) +{ + // - Make sure to enable aggressive VIMS clock gating for power optimization + // Only for PG2 devices. + // - Enable cache prefetch enable as default setting + // (Slightly higher power consumption, but higher CPU performance) + // - IF ( CCFG_..._DIS_GPRAM == 1 ) + // then: Enable cache (set cache mode = 1), even if set by ROM boot code + // (This is done because it's not set by boot code when running inside + // a debugger supporting the Halt In Boot (HIB) functionality). + // else: Set MODE_GPRAM if not already set (see inline comments as well) + uint32_t vimsCtlMode0 ; + + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for an eventual ongoing mode change to complete. + // (There should typically be no wait time here, but need to be sure) + } + + // Note that Mode=0 is equal to MODE_GPRAM + vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M ); + + + if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) { + // Enable cache (and hence disable GPRAM) + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE ); + } else if (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_GPRAM ) { + // GPRAM is enabled in CCFG but not selected + // Note: It is recommended to go via MODE_OFF when switching to MODE_GPRAM + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_OFF ); + while (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_OFF ) { + // Do nothing - wait for an eventual mode change to complete (This goes fast). + } + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + } else { + // Correct mode, but make sure PREF_EN and DYN_CG_EN always are set + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + } +} + +//***************************************************************************** +// +// SetupSetAonRtcSubSecInc +// +//***************************************************************************** +void +SetupSetAonRtcSubSecInc( uint32_t subSecInc ) +{ + // Loading a new RTCSUBSECINC value is done in 5 steps: + // 1. Write bit[15:0] of new SUBSECINC value to AUX_WUC_O_RTCSUBSECINC0 + // 2. Write bit[23:16] of new SUBSECINC value to AUX_WUC_O_RTCSUBSECINC1 + // 3. Set AUX_WUC_RTCSUBSECINCCTL_UPD_REQ + // 4. Wait for AUX_WUC_RTCSUBSECINCCTL_UPD_ACK + // 5. Clear AUX_WUC_RTCSUBSECINCCTL_UPD_REQ + HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC0 ) = (( subSecInc ) & AUX_WUC_RTCSUBSECINC0_INC15_0_M ); + HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_WUC_RTCSUBSECINC1_INC23_16_M ); + + HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL ) = AUX_WUC_RTCSUBSECINCCTL_UPD_REQ; + while( ! ( HWREGBITW( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL, AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN ))); + HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL ) = 0; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom.h new file mode 100644 index 0000000..f32a5a8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom.h @@ -0,0 +1,450 @@ +/****************************************************************************** +* Filename: setup_rom.h +* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) +* Revision: 52993 +* +* Description: Prototypes and defines for the setup API. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup setup_rom_api +//! @{ +// +//***************************************************************************** + +#ifndef __SETUP_ROM_H__ +#define __SETUP_ROM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +// Hardware headers +#include "../inc/hw_types.h" +// Driverlib headers +// - None needed + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn + #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn + #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl + #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 + #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 + #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 + #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage + #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg + #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim + #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl + #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart + #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm + #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting + #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc +#endif + +//***************************************************************************** +// +//! \brief First part of configuration required after cold reset and when waking up from shutdown. +//! +//! Configures the following based on settings in CCFG (Customer Configuration area: +//! - Boost mode for CC13xx devices +//! - Minimal VDDR voltage threshold used during sleep mode +//! - DCDC functionality: +//! - Selects if DCDC or GLDO regulator will be used for VDDR in active mode +//! - Selects if DCDC or GLDO regulator will be used for VDDR in sleep mode +//! +//! In addition the battery monitor low limit for internal regulator mode is set +//! to a hard coded value. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return None +// +//***************************************************************************** +extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Second part of configuration required after cold reset and when waking up from shutdown. +//! +//! Configures and trims functionalites required for use of XOSC_HF. +//! The configurations and trimmings are based on settings in FCFG1 (Factory +//! Configuration area) and partly on \c ccfg_ModeConfReg. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return None +// +//***************************************************************************** +extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Third part of configuration required after cold reset and when waking up from shutdown. +//! +//! Configures the following: +//! - XOSC source selection based on \c ccfg_ModeConfReg. If HPOSC is selected on a +//! HPOSC device the oscillator is configured based on settings in FCFG1 (Factory +//! Configuration area). +//! - Clock loss detection is disabled. Will be re-enabled by TIRTOS power driver. +//! - Duration of the XOSC_HF fast startup mode based on FCFG1 setting. +//! - SCLK_LF based on \c ccfg_ModeConfReg. +//! - Output voltage of ADC fixed reference based on FCFG1 setting. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return None +// +//***************************************************************************** +extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAmpcompTh1( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAmpcompTh2( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the +//! RCOSCLF_CTUNE_TRIM bit fields in the XOSCLF_RCOSCLF_CTRL register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscHfFastStart( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in +//! the ANABYPASS_VALUE2 register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscHfIbiastherm( void ); + +//***************************************************************************** +// +//! \brief Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet +//! spanning bits [5:0] in the returned value. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) +//! +//! \param ui32VddrTrimVal +//! +//! \return Returns Sign extended VDDR_TRIM setting. +// +//***************************************************************************** +__STATIC_INLINE int32_t +SetupSignExtendVddrTrimValue( uint32_t ui32VddrTrimVal ) +{ + // The VDDR trim value is 5 bits representing the range from -10 to +21 + // (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15) + int32_t i32SignedVddrVal = ui32VddrTrimVal; + if ( i32SignedVddrVal > 0x15 ) { + i32SignedVddrVal -= 0x20; + } + return ( i32SignedVddrVal ); +} + +//***************************************************************************** +// +//! \brief Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM) +//! +//! \return None +// +//***************************************************************************** +extern void SetupSetCacheModeAccordingToCcfgSetting( void ); + +//***************************************************************************** +// +//! \brief Doing the tricky stuff needed to enter new RTCSUBSECINC value +//! +//! \param subSecInc +//! +//! \return None +// +//***************************************************************************** +extern void SetupSetAonRtcSubSecInc( uint32_t subSecInc ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #undef SetupAfterColdResetWakeupFromShutDownCfg1 + #define SetupAfterColdResetWakeupFromShutDownCfg1 ROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #endif + #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #undef SetupAfterColdResetWakeupFromShutDownCfg2 + #define SetupAfterColdResetWakeupFromShutDownCfg2 ROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #endif + #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #undef SetupAfterColdResetWakeupFromShutDownCfg3 + #define SetupAfterColdResetWakeupFromShutDownCfg3 ROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #endif + #ifdef ROM_SetupGetTrimForAdcShModeEn + #undef SetupGetTrimForAdcShModeEn + #define SetupGetTrimForAdcShModeEn ROM_SetupGetTrimForAdcShModeEn + #endif + #ifdef ROM_SetupGetTrimForAdcShVbufEn + #undef SetupGetTrimForAdcShVbufEn + #define SetupGetTrimForAdcShVbufEn ROM_SetupGetTrimForAdcShVbufEn + #endif + #ifdef ROM_SetupGetTrimForAmpcompCtrl + #undef SetupGetTrimForAmpcompCtrl + #define SetupGetTrimForAmpcompCtrl ROM_SetupGetTrimForAmpcompCtrl + #endif + #ifdef ROM_SetupGetTrimForAmpcompTh1 + #undef SetupGetTrimForAmpcompTh1 + #define SetupGetTrimForAmpcompTh1 ROM_SetupGetTrimForAmpcompTh1 + #endif + #ifdef ROM_SetupGetTrimForAmpcompTh2 + #undef SetupGetTrimForAmpcompTh2 + #define SetupGetTrimForAmpcompTh2 ROM_SetupGetTrimForAmpcompTh2 + #endif + #ifdef ROM_SetupGetTrimForAnabypassValue1 + #undef SetupGetTrimForAnabypassValue1 + #define SetupGetTrimForAnabypassValue1 ROM_SetupGetTrimForAnabypassValue1 + #endif + #ifdef ROM_SetupGetTrimForDblrLoopFilterResetVoltage + #undef SetupGetTrimForDblrLoopFilterResetVoltage + #define SetupGetTrimForDblrLoopFilterResetVoltage ROM_SetupGetTrimForDblrLoopFilterResetVoltage + #endif + #ifdef ROM_SetupGetTrimForRadcExtCfg + #undef SetupGetTrimForRadcExtCfg + #define SetupGetTrimForRadcExtCfg ROM_SetupGetTrimForRadcExtCfg + #endif + #ifdef ROM_SetupGetTrimForRcOscLfIBiasTrim + #undef SetupGetTrimForRcOscLfIBiasTrim + #define SetupGetTrimForRcOscLfIBiasTrim ROM_SetupGetTrimForRcOscLfIBiasTrim + #endif + #ifdef ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #undef SetupGetTrimForRcOscLfRtuneCtuneTrim + #define SetupGetTrimForRcOscLfRtuneCtuneTrim ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #endif + #ifdef ROM_SetupGetTrimForXoscHfCtl + #undef SetupGetTrimForXoscHfCtl + #define SetupGetTrimForXoscHfCtl ROM_SetupGetTrimForXoscHfCtl + #endif + #ifdef ROM_SetupGetTrimForXoscHfFastStart + #undef SetupGetTrimForXoscHfFastStart + #define SetupGetTrimForXoscHfFastStart ROM_SetupGetTrimForXoscHfFastStart + #endif + #ifdef ROM_SetupGetTrimForXoscHfIbiastherm + #undef SetupGetTrimForXoscHfIbiastherm + #define SetupGetTrimForXoscHfIbiastherm ROM_SetupGetTrimForXoscHfIbiastherm + #endif + #ifdef ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #endif + #ifdef ROM_SetupSetCacheModeAccordingToCcfgSetting + #undef SetupSetCacheModeAccordingToCcfgSetting + #define SetupSetCacheModeAccordingToCcfgSetting ROM_SetupSetCacheModeAccordingToCcfgSetting + #endif + #ifdef ROM_SetupSetAonRtcSubSecInc + #undef SetupSetAonRtcSubSecInc + #define SetupSetAonRtcSubSecInc ROM_SetupSetAonRtcSubSecInc + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SETUP_ROM_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom_doc.h new file mode 100644 index 0000000..bafcf07 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom_doc.h @@ -0,0 +1,44 @@ +/****************************************************************************** +* Filename: setup_rom_doc.h +* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) +* Revision: 49096 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup setup_rom_api +//! @{ +//! +//! This module contains functions from the Setup API which are likely to be in ROM. +//! +//! \note Do not use functions from this module directly! This module is only to be used by +//! SetupTrimDevice(). +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph.c new file mode 100644 index 0000000..84df1f3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph.c @@ -0,0 +1,101 @@ +/****************************************************************************** +* Filename: smph.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the MCU Semaphore. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "smph.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SMPHAcquire + #define SMPHAcquire NOROM_SMPHAcquire +#endif + +//***************************************************************************** +// +// Acquire a semaphore +// +//***************************************************************************** +void +SMPHAcquire(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // Wait for semaphore to be release such that it can be claimed + // Semaphore register reads 1 when lock was acquired otherwise 0 + // (i.e. SMPH_CLAIMED). + while(HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) == + SMPH_CLAIMED) + { + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph.h new file mode 100644 index 0000000..636979d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph.h @@ -0,0 +1,312 @@ +/****************************************************************************** +* Filename: smph.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the MCU Semaphore. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup mcusemaphore_api +//! @{ +// +//***************************************************************************** + +#ifndef __SMPH_H__ +#define __SMPH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_smph.h" +#include "../inc/hw_memmap.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SMPHAcquire NOROM_SMPHAcquire +#endif + +//***************************************************************************** +// +// General constants and defines +// +//***************************************************************************** +#define SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed + +//***************************************************************************** +// +// Values that can be passed to SMPHAcquire, SMPHTryAcquire and SMPHRelease +// as the ui32Semaphore parameter. +// +//***************************************************************************** +#define SMPH_0 0 // MCU Semaphore 0 +#define SMPH_1 1 // MCU Semaphore 1 +#define SMPH_2 2 // MCU Semaphore 2 +#define SMPH_3 3 // MCU Semaphore 3 +#define SMPH_4 4 // MCU Semaphore 4 +#define SMPH_5 5 // MCU Semaphore 5 +#define SMPH_6 6 // MCU Semaphore 6 +#define SMPH_7 7 // MCU Semaphore 7 +#define SMPH_8 8 // MCU Semaphore 8 +#define SMPH_9 9 // MCU Semaphore 9 +#define SMPH_10 10 // MCU Semaphore 10 +#define SMPH_11 11 // MCU Semaphore 11 +#define SMPH_12 12 // MCU Semaphore 12 +#define SMPH_13 13 // MCU Semaphore 13 +#define SMPH_14 14 // MCU Semaphore 14 +#define SMPH_15 15 // MCU Semaphore 15 +#define SMPH_16 16 // MCU Semaphore 16 +#define SMPH_17 17 // MCU Semaphore 17 +#define SMPH_18 18 // MCU Semaphore 18 +#define SMPH_19 19 // MCU Semaphore 19 +#define SMPH_20 20 // MCU Semaphore 20 +#define SMPH_21 21 // MCU Semaphore 21 +#define SMPH_22 22 // MCU Semaphore 22 +#define SMPH_23 23 // MCU Semaphore 23 +#define SMPH_24 24 // MCU Semaphore 24 +#define SMPH_25 25 // MCU Semaphore 25 +#define SMPH_26 26 // MCU Semaphore 26 +#define SMPH_27 27 // MCU Semaphore 27 +#define SMPH_28 28 // MCU Semaphore 28 +#define SMPH_29 29 // MCU Semaphore 29 +#define SMPH_30 30 // MCU Semaphore 30 +#define SMPH_31 31 // MCU Semaphore 31 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Acquire a semaphore. +//! +//! This function acquires the given semaphore, blocking the call until +//! the semaphore is available. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref SMPH_0 +//! - \ref SMPH_1 +//! - ... +//! - \ref SMPH_31 +//! +//! \return None +// +//***************************************************************************** +extern void SMPHAcquire(uint32_t ui32Semaphore); + +//***************************************************************************** +// +//! \brief Try to Acquire a semaphore. +//! +//! This function tries to acquire the given semaphore, if the semaphore +//! could not be claimed the function returns false. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref SMPH_0 +//! - \ref SMPH_1 +//! - ... +//! - \ref SMPH_31 +//! +//! \return Returns if a semaphore was acquired +//! - \c true : Semaphore acquired. +//! - \c false : Semaphore \b not acquired. +// +//***************************************************************************** +__STATIC_INLINE bool +SMPHTryAcquire(uint32_t ui32Semaphore) +{ + uint32_t ui32SemaReg; + + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // Semaphore register reads 1 if lock was acquired + // (i.e. SMPH_FREE). + ui32SemaReg = HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore); + + return (ui32SemaReg == SMPH_FREE); +} + +//***************************************************************************** +// +//! \brief Release a semaphore. +//! +//! This function releases the given semaphore. +//! +//! \note It is up to the application to provide the convention for clearing +//! semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref SMPH_0 +//! - \ref SMPH_1 +//! - ... +//! - \ref SMPH_31 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SMPHRelease(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // No check before release, it is up to the application to provide the + // conventions for who and when a semaphore can be released. + HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) = SMPH_FREE; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SMPHAcquire + #undef SMPHAcquire + #define SMPHAcquire ROM_SMPHAcquire + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SMPH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph_doc.h new file mode 100644 index 0000000..c66ef84 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph_doc.h @@ -0,0 +1,57 @@ +/****************************************************************************** +* Filename: smph_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup mcusemaphore_api +//! @{ +//! \section sec_mcusemaphore Introduction +//! +//! The MCU Semaphore offers 32 semaphores that each can be claimed and released in an atomic operation. +//! One and only one semaphore can be handled during a transaction. +//! +//! Claiming a semaphore causes subsequent claims/reads to return '0' (i.e. "not available"). +//! How the semaphores are used and respected is decided by software. +//! +//! \section sec_mcusemaphore_api API +//! +//! The API functions can be grouped like this: +//! +//! Semaphore acquire: +//! - \ref SMPHAcquire() +//! - \ref SMPHTryAcquire() +//! +//! Semaphore release: +//! - \ref SMPHRelease() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ssi.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ssi.c new file mode 100644 index 0000000..76fc8e7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ssi.c @@ -0,0 +1,253 @@ +/****************************************************************************** +* Filename: ssi.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for Synchronous Serial Interface +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ssi.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SSIConfigSetExpClk + #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk + #undef SSIDataPut + #define SSIDataPut NOROM_SSIDataPut + #undef SSIDataPutNonBlocking + #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking + #undef SSIDataGet + #define SSIDataGet NOROM_SSIDataGet + #undef SSIDataGetNonBlocking + #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking + #undef SSIIntRegister + #define SSIIntRegister NOROM_SSIIntRegister + #undef SSIIntUnregister + #define SSIIntUnregister NOROM_SSIIntUnregister +#endif + +//***************************************************************************** +// +// Configures the synchronous serial port +// +//***************************************************************************** +void +SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, uint32_t ui32DataWidth) +{ + uint32_t ui32MaxBitRate; + uint32_t ui32RegVal; + uint32_t ui32PreDiv; + uint32_t ui32SCR; + uint32_t ui32SPH_SPO; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || + (ui32Protocol == SSI_FRF_MOTO_MODE_1) || + (ui32Protocol == SSI_FRF_MOTO_MODE_2) || + (ui32Protocol == SSI_FRF_MOTO_MODE_3) || + (ui32Protocol == SSI_FRF_TI) || + (ui32Protocol == SSI_FRF_NMW)); + ASSERT((ui32Mode == SSI_MODE_MASTER) || + (ui32Mode == SSI_MODE_SLAVE) || + (ui32Mode == SSI_MODE_SLAVE_OD)); + ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) || + ((ui32Mode != SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 12)))); + ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); + ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); + + // Set the mode. + ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; + + // Set the clock predivider. + ui32MaxBitRate = ui32SSIClk / ui32BitRate; + ui32PreDiv = 0; + do + { + ui32PreDiv += 2; + ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; + } + while(ui32SCR > 255); + HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; + + // Set protocol and clock rate. + ui32SPH_SPO = (ui32Protocol & 3) << 6; + ui32Protocol &= SSI_CR0_FRF_M; + ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | (ui32DataWidth - 1); + HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; +} + +//***************************************************************************** +// +// Puts a data element into the SSI transmit FIFO +// +//***************************************************************************** +int32_t +SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // Check for space to write. + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ui32Base + SSI_O_DR) = ui32Data; + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +// Puts a data element into the SSI transmit FIFO +// +//***************************************************************************** +void +SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // Wait until there is space. + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // Write the data to the SSI. + HWREG(ui32Base + SSI_O_DR) = ui32Data; +} + +//***************************************************************************** +// +// Gets a data element from the SSI receive FIFO +// +//***************************************************************************** +void +SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Wait until there is data to be read. + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // Read data from SSI. + *pui32Data = HWREG(ui32Base + SSI_O_DR); +} + +//***************************************************************************** +// +// Gets a data element from the SSI receive FIFO +// +//***************************************************************************** +int32_t +SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Check for data to read. + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) + { + *pui32Data = HWREG(ui32Base + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +// Registers an interrupt handler for the synchronous serial port +// +//***************************************************************************** +void +SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Determine the interrupt number based on the SSI port. + ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB; + + // Register the interrupt handler. + IntRegister(ui32Int, pfnHandler); + + // Enable the synchronous serial port interrupt. + IntEnable(ui32Int); +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for the synchronous serial port +// +//***************************************************************************** +void +SSIIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Determine the interrupt number based on the SSI port. + ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB; + + // Disable the interrupt. + IntDisable(ui32Int); + + // Unregister the interrupt handler. + IntUnregister(ui32Int); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ssi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ssi.h new file mode 100644 index 0000000..87a9745 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ssi.h @@ -0,0 +1,700 @@ +/****************************************************************************** +* Filename: ssi.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and macros for the SSI. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup ssi_api +//! @{ +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "../inc/hw_ssi.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk + #define SSIDataPut NOROM_SSIDataPut + #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking + #define SSIDataGet NOROM_SSIDataGet + #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking + #define SSIIntRegister NOROM_SSIIntRegister + #define SSIIntUnregister NOROM_SSIIntUnregister +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ui32IntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half full or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or more +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that are returned from SSIStatus +// +//***************************************************************************** +#define SSI_RX_FULL 0x00000008 // Receive FIFO full +#define SSI_RX_NOT_EMPTY 0x00000004 // Receive FIFO not empty +#define SSI_TX_NOT_FULL 0x00000002 // Transmit FIFO not full +#define SSI_TX_EMPTY 0x00000001 // Transmit FIFO empty +#define SSI_STATUS_MASK 0x0000000F + +//***************************************************************************** +// +// Values that can be passed to SSIConfigSetExpClk. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). +// +//***************************************************************************** +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an SSI base address. +//! +//! This function determines if an SSI module base address is valid. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +SSIBaseValid(uint32_t ui32Base) +{ + return(ui32Base == SSI0_BASE || ui32Base == SSI1_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Configures the synchronous serial port. +//! +//! This function configures the synchronous serial port. It sets +//! the SSI protocol, mode of operation, bit rate, and data width. +//! +//! The \c ui32Protocol parameter defines the data frame format. The Motorola +//! frame formats imply the following polarity and phase configurations: +//! +//! 
+//! Polarity Phase       Mode
+//!   0       0   SSI_FRF_MOTO_MODE_0
+//!   0       1   SSI_FRF_MOTO_MODE_1
+//!   1       0   SSI_FRF_MOTO_MODE_2
+//!   1       1   SSI_FRF_MOTO_MODE_3
+//!
+//! +//! The \c ui32Mode parameter defines the operating mode of the SSI module. +//! The SSI module can operate as a master or slave; if a slave, the SSI can be +//! configured to disable output on its serial output line. +//! +//! The \c ui32BitRate parameter defines the bit rate for the SSI. This bit +//! rate must satisfy the following clock ratio criteria: +//! - Master mode : FSSI >= 2 * bit rate +//! - Slave mode : FSSI >= 12 * bit rate +//! +//! where FSSI is the frequency of the clock supplied to the SSI module. +//! +//! The \c ui32DataWidth parameter defines the width of the data transfers, and +//! can be a value between 4 and 16, inclusive. +//! +//! \note The peripheral clock is not necessarily the same as the processor clock. +//! The frequency of the peripheral clock is set by the system control. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32SSIClk is the rate of the clock supplied to the SSI module. +//! \param ui32Protocol specifies the data transfer protocol. +//! The parameter can be one of the following values: +//! - \ref SSI_FRF_MOTO_MODE_0 +//! - \ref SSI_FRF_MOTO_MODE_1 +//! - \ref SSI_FRF_MOTO_MODE_2 +//! - \ref SSI_FRF_MOTO_MODE_3 +//! - \ref SSI_FRF_TI +//! - \ref SSI_FRF_NMW. +//! \param ui32Mode specifies the mode of operation. +//! The parameter can be one of the following values: +//! - \ref SSI_MODE_MASTER +//! - \ref SSI_MODE_SLAVE +//! - \ref SSI_MODE_SLAVE_OD +//! \param ui32BitRate specifies the clock rate. +//! \param ui32DataWidth specifies number of bits transferred per frame. +//! Must be a value between 4 and 16, both included. +//! +//! \return None +// +//***************************************************************************** +extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, uint32_t ui32DataWidth); + +//***************************************************************************** +// +//! \brief Enables the synchronous serial port. +//! +//! This function enables operation of the synchronous serial port. The +//! synchronous serial port must be configured before it is enabled. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Read-modify-write the enable bit. + HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE; +} + +//***************************************************************************** +// +//! \brief Disables the synchronous serial port. +//! +//! This function disables operation of the synchronous serial port. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Read-modify-write the enable bit. + HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE); +} + +//***************************************************************************** +// +//! \brief Puts a data element into the SSI transmit FIFO. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module. +//! +//! \note The upper 32 - N bits of the \c ui32Data are discarded by the +//! hardware, where N is the data width as configured by \ref SSIConfigSetExpClk(). +//! For example, if the interface is configured for 8-bit data width, the upper +//! 24 bits of \c ui32Data are discarded. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32Data is the data to be transmitted over the SSI interface. +//! +//! \return None +// +//***************************************************************************** +extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data); + +//***************************************************************************** +// +//! \brief Puts a data element into the SSI transmit FIFO. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module. If there is no space in the FIFO, then this function +//! returns a zero. +//! +//! \note The upper 32 - N bits of the \c ui32Data are discarded by the hardware, +//! where N is the data width as configured by \ref SSIConfigSetExpClk(). For +//! example, if the interface is configured for 8-bit data width, the upper 24 +//! bits of \c ui32Data are discarded. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32Data is the data to be transmitted over the SSI interface. +//! +//! \return Returns the number of elements written to the SSI transmit FIFO. +// +//***************************************************************************** +extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data); + +//***************************************************************************** +// +//! \brief Gets a data element from the SSI receive FIFO. +//! +//! This function gets received data from the receive FIFO of the specified +//! SSI module and places that data into the location specified by the +//! \c pui32Data parameter. +//! +//! \note Only the lower N bits of the value written to \c pui32Data contain +//! valid data, where N is the data width as configured by +//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to +//! \c pui32Data contain valid data. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pui32Data is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! \return None +// +//***************************************************************************** +extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data); + +//***************************************************************************** +// +//! \brief Gets a data element from the SSI receive FIFO. +//! +//! This function gets received data from the receive FIFO of the specified SSI +//! module and places that data into the location specified by the \c ui32Data +//! parameter. If there is no data in the FIFO, then this function returns a +//! zero. +//! +//! \note Only the lower N bits of the value written to \c pui32Data contain +//! valid data, where N is the data width as configured by +//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to \c pui32Data +//! contain valid data. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pui32Data is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! \return Returns the number of elements read from the SSI receive FIFO. +// +//***************************************************************************** +extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data); + +//***************************************************************************** +// +//! \brief Determines whether the SSI transmitter is busy or not. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \c false is returned, then the transmit FIFO +//! is empty and all bits of the last transmitted word have left the hardware +//! shift register. +//! +//! \param ui32Base is the base address of the SSI port. +//! +//! \return Returns status of the SSI transmit buffer. +//! - \c true : SSI is transmitting. +//! - \c false : SSI transmissions are complete. +// +//***************************************************************************** +__STATIC_INLINE bool +SSIBusy(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Determine if the SSI is busy. + return((HWREG(ui32Base + SSI_O_SR) & SSI_SR_BSY) ? true : false); +} + +//***************************************************************************** +// +//! \brief Get the status of the SSI data buffers. +//! +//! This function is used to poll the status of the internal FIFOs in the SSI +//! module. The status of both TX and RX FIFO is returned. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return Returns the current status of the internal SSI data buffers. +//! The status is a bitwise OR'ed combination of: +//! - \ref SSI_RX_FULL : Receive FIFO full. +//! - \ref SSI_RX_NOT_EMPTY : Receive FIFO not empty. +//! - \ref SSI_TX_NOT_FULL : Transmit FIFO not full. +//! - \ref SSI_TX_EMPTY : Transmit FIFO empty. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SSIStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Return the status + return (HWREG(ui32Base + SSI_O_SR) & SSI_STATUS_MASK); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific SSI interrupts must be enabled via \ref SSIIntEnable(). If necessary, +//! it is the interrupt handler's responsibility to clear the interrupt source +//! via \ref SSIIntClear(). +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial port interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when a SSI +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void SSIIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables individual SSI interrupt sources. +//! +//! Enables the indicated SSI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. +//! - \ref SSI_TXFF +//! - \ref SSI_RXFF +//! - \ref SSI_RXTO +//! - \ref SSI_RXOR +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(ui32Base + SSI_O_IMSC) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual SSI interrupt sources. +//! +//! Disables the indicated SSI interrupt sources. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. +//! - \ref SSI_TXFF +//! - \ref SSI_RXFF +//! - \ref SSI_RXTO +//! - \ref SSI_RXOR +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(ui32Base + SSI_O_IMSC) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Clears SSI interrupt sources. +//! +//! The specified SSI interrupt sources are cleared so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupts from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter can consist of either or both of: +//! - \ref SSI_RXTO : Timeout interrupt. +//! - \ref SSI_RXOR : Overrun interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Clear the requested interrupt sources. + HWREG(ui32Base + SSI_O_ICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the SSI module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param bMasked selects either raw or masked interrupt. +//! \c false : Raw interrupt status is required. +//! \c true : Masked interrupt status is required. +//! +//! \return Returns the current interrupt status as an OR'ed combination of: +//! - \ref SSI_TXFF +//! - \ref SSI_RXFF +//! - \ref SSI_RXTO +//! - \ref SSI_RXOR +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SSIIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return(HWREG(ui32Base + SSI_O_MIS)); + } + else + { + return(HWREG(ui32Base + SSI_O_RIS)); + } +} + +//***************************************************************************** +// +//! \brief Enable SSI DMA operation. +//! +//! The specified SSI DMA features are enabled. The SSI can be +//! configured to use DMA for transmit and/or receive data transfers. +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the SSI. +//! +//! \param ui32Base is the base address of the SSI port. +//! \param ui32DMAFlags is a bit mask of the DMA features to enable. +//! The parameter is the bitwise OR of any of the following values: +//! - \ref SSI_DMA_RX : Enable DMA for receive. +//! - \ref SSI_DMA_TX : Enable DMA for transmit. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Set the requested bits in the SSI DMA control register. + HWREG(ui32Base + SSI_O_DMACR) |= ui32DMAFlags; +} + +//***************************************************************************** +// +//! \brief Disable SSI DMA operation. +//! +//! This function is used to disable SSI DMA features that were enabled +//! by \ref SSIDMAEnable(). The specified SSI DMA features are disabled. +//! +//! \param ui32Base is the base address of the SSI port. +//! \param ui32DMAFlags is a bit mask of the DMA features to disable. +//! The parameter is the bitwise OR of any of the following values: +//! - \ref SSI_DMA_RX : Disable DMA for receive. +//! - \ref SSI_DMA_TX : Disable DMA for transmit. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Clear the requested bits in the SSI DMA control register. + HWREG(ui32Base + SSI_O_DMACR) &= ~ui32DMAFlags; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SSIConfigSetExpClk + #undef SSIConfigSetExpClk + #define SSIConfigSetExpClk ROM_SSIConfigSetExpClk + #endif + #ifdef ROM_SSIDataPut + #undef SSIDataPut + #define SSIDataPut ROM_SSIDataPut + #endif + #ifdef ROM_SSIDataPutNonBlocking + #undef SSIDataPutNonBlocking + #define SSIDataPutNonBlocking ROM_SSIDataPutNonBlocking + #endif + #ifdef ROM_SSIDataGet + #undef SSIDataGet + #define SSIDataGet ROM_SSIDataGet + #endif + #ifdef ROM_SSIDataGetNonBlocking + #undef SSIDataGetNonBlocking + #define SSIDataGetNonBlocking ROM_SSIDataGetNonBlocking + #endif + #ifdef ROM_SSIIntRegister + #undef SSIIntRegister + #define SSIIntRegister ROM_SSIIntRegister + #endif + #ifdef ROM_SSIIntUnregister + #undef SSIIntUnregister + #define SSIIntUnregister ROM_SSIIntUnregister + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_chacha.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_chacha.c new file mode 100644 index 0000000..50f46c8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_chacha.c @@ -0,0 +1,121 @@ +/****************************************************************************** +* Filename: sw_chacha.c +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* +chacha-ref.c version 20080118 +D. J. Bernstein +Public domain. +*/ + +#define ECRYPT_LITTLE_ENDIAN + +#include "sw_ecrypt-sync.h" + +#define ROTATE(v,c) (ROTL32(v,c)) +#define XOR(v,w) ((v) ^ (w)) +#define PLUS(v,w) (U32V((v) + (w))) +#define PLUSONE(v) (PLUS((v),1)) + +#define QUARTERROUND(a,b,c,d) \ + x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]),16); \ + x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]),12); \ + x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]), 8); \ + x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]), 7); + +static void salsa20_wordtobyte(u8 output[64],const u32 input[16]) +{ + u32 x[16]; + int i; + + for (i = 0;i < 16;++i) x[i] = input[i]; + for (i = 8;i > 0;i -= 2) { + QUARTERROUND( 0, 4, 8,12) + QUARTERROUND( 1, 5, 9,13) + QUARTERROUND( 2, 6,10,14) + QUARTERROUND( 3, 7,11,15) + QUARTERROUND( 0, 5,10,15) + QUARTERROUND( 1, 6,11,12) + QUARTERROUND( 2, 7, 8,13) + QUARTERROUND( 3, 4, 9,14) + } + for (i = 0;i < 16;++i) x[i] = PLUS(x[i],input[i]); + for (i = 0;i < 16;++i) U32TO8_LITTLE(output + 4 * i,x[i]); +} + +void ECRYPT_init(void) +{ + return; +} + +static const char sigma[16] = "expand 32-byte k"; +static const char tau[16] = "expand 16-byte k"; + +void ECRYPT_keysetup(ECRYPT_ctx *x,const u8 *k,u32 kbits,u32 ivbits) +{ + const char *constants; + + x->input[4] = U8TO32_LITTLE(k + 0); + x->input[5] = U8TO32_LITTLE(k + 4); + x->input[6] = U8TO32_LITTLE(k + 8); + x->input[7] = U8TO32_LITTLE(k + 12); + if (kbits == 256) { /* recommended */ + k += 16; + constants = sigma; + } else { /* kbits == 128 */ + constants = tau; + } + x->input[8] = U8TO32_LITTLE(k + 0); + x->input[9] = U8TO32_LITTLE(k + 4); + x->input[10] = U8TO32_LITTLE(k + 8); + x->input[11] = U8TO32_LITTLE(k + 12); + x->input[0] = U8TO32_LITTLE(constants + 0); + x->input[1] = U8TO32_LITTLE(constants + 4); + x->input[2] = U8TO32_LITTLE(constants + 8); + x->input[3] = U8TO32_LITTLE(constants + 12); +} + +void ECRYPT_ivsetup(ECRYPT_ctx *x,const u8 *iv) +{ + x->input[12] = 0; + x->input[13] = 0; + x->input[14] = U8TO32_LITTLE(iv + 0); + x->input[15] = U8TO32_LITTLE(iv + 4); +} + +void ECRYPT_encrypt_bytes(ECRYPT_ctx *x,const u8 *m,u8 *c,u32 bytes) +{ + u8 output[64]; + int i; + + if (!bytes) return; + for (;;) { + salsa20_wordtobyte(output,x->input); + x->input[12] = PLUSONE(x->input[12]); + if (!x->input[12]) { + x->input[13] = PLUSONE(x->input[13]); + /* stopping at 2^70 bytes per nonce is user's responsibility */ + } + if (bytes <= 64) { + for (i = 0;i < bytes;++i) c[i] = m[i] ^ output[i]; + return; + } + for (i = 0;i < 64;++i) c[i] = m[i] ^ output[i]; + bytes -= 64; + c += 64; + m += 64; + } +} + +void ECRYPT_decrypt_bytes(ECRYPT_ctx *x,const u8 *c,u8 *m,u32 bytes) +{ + ECRYPT_encrypt_bytes(x,c,m,bytes); +} + +void ECRYPT_keystream_bytes(ECRYPT_ctx *x,u8 *stream,u32 bytes) +{ + u32 i; + for (i = 0;i < bytes;++i) stream[i] = 0; + ECRYPT_encrypt_bytes(x,stream,stream,bytes); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-config.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-config.h new file mode 100644 index 0000000..e8885f7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-config.h @@ -0,0 +1,279 @@ +/****************************************************************************** +* Filename: sw_ecrypt-config.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* ecrypt-config.h */ + +/* *** Normally, it should not be necessary to edit this file. *** */ + +#ifndef ECRYPT_CONFIG +#define ECRYPT_CONFIG + +/* ------------------------------------------------------------------------- */ + +/* Guess the endianness of the target architecture. */ + +/* + * The LITTLE endian machines: + */ +#if ( ! defined(ECRYPT_LITTLE_ENDIAN)) +#if defined(__ultrix) /* Older MIPS */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__alpha) /* Alpha */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_M_IX86) /* x86 (MSC, Borland) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_MSC_VER) /* x86 (surely MSC) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */ +#define ECRYPT_LITTLE_ENDIAN + +/* + * The BIG endian machines: + */ +#elif defined(sun) /* Newer Sparc's */ +#define ECRYPT_BIG_ENDIAN +#elif defined(__ppc__) /* PowerPC */ +#define ECRYPT_BIG_ENDIAN + +/* + * Finally machines with UNKNOWN endianness: + */ +#elif defined (_AIX) /* RS6000 */ +#define ECRYPT_UNKNOWN +#elif defined(__hpux) /* HP-PA */ +#define ECRYPT_UNKNOWN +#elif defined(__aux) /* 68K */ +#define ECRYPT_UNKNOWN +#elif defined(__dgux) /* 88K (but P6 in latest boxes) */ +#define ECRYPT_UNKNOWN +#elif defined(__sgi) /* Newer MIPS */ +#define ECRYPT_UNKNOWN +#else /* Any other processor */ +#define ECRYPT_UNKNOWN +#endif +#endif + +/* ------------------------------------------------------------------------- */ + +/* + * Find minimal-width types to store 8-bit, 16-bit, 32-bit, and 64-bit + * integers. + * + * Note: to enable 64-bit types on 32-bit compilers, it might be + * necessary to switch from ISO C90 mode to ISO C99 mode (e.g., gcc + * -std=c99). + */ + +#include + +/* --- check char --- */ + +#if (UCHAR_MAX / 0xFU > 0xFU) +#ifndef I8T +#define I8T char +#define U8C(v) (v##U) + +#if (UCHAR_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (UCHAR_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T char +#define U16C(v) (v##U) +#endif + +#if (UCHAR_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T char +#define U32C(v) (v##U) +#endif + +#if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T char +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check short --- */ + +#if (USHRT_MAX / 0xFU > 0xFU) +#ifndef I8T +#define I8T short +#define U8C(v) (v##U) + +#if (USHRT_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (USHRT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T short +#define U16C(v) (v##U) +#endif + +#if (USHRT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T short +#define U32C(v) (v##U) +#endif + +#if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T short +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check int --- */ + +#if (UINT_MAX / 0xFU > 0xFU) +#ifndef I8T +#define I8T int +#define U8C(v) (v##U) + +#if (ULONG_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (UINT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T int +#define U16C(v) (v##U) +#endif + +#if (UINT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T int +#define U32C(v) (v##U) +#endif + +#if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T int +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check long --- */ + +#if (ULONG_MAX / 0xFUL > 0xFUL) +#ifndef I8T +#define I8T long +#define U8C(v) (v##UL) + +#if (ULONG_MAX == 0xFFUL) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (ULONG_MAX / 0xFFUL > 0xFFUL) +#ifndef I16T +#define I16T long +#define U16C(v) (v##UL) +#endif + +#if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL) +#ifndef I32T +#define I32T long +#define U32C(v) (v##UL) +#endif + +#if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL) +#ifndef I64T +#define I64T long +#define U64C(v) (v##UL) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check long long --- */ + +#ifdef ULLONG_MAX + +#if (ULLONG_MAX / 0xFULL > 0xFULL) +#ifndef I8T +#define I8T long long +#define U8C(v) (v##ULL) + +#if (ULLONG_MAX == 0xFFULL) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (ULLONG_MAX / 0xFFULL > 0xFFULL) +#ifndef I16T +#define I16T long long +#define U16C(v) (v##ULL) +#endif + +#if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL) +#ifndef I32T +#define I32T long long +#define U32C(v) (v##ULL) +#endif + +#if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL) +#ifndef I64T +#define I64T long long +#define U64C(v) (v##ULL) +#endif + +#endif +#endif +#endif +#endif + +#endif + +/* --- check __int64 --- */ + +#ifdef _UI64_MAX + +#if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64) +#ifndef I64T +#define I64T __int64 +#define U64C(v) (v##ui64) +#endif + +#endif + +#endif + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-machine.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-machine.h new file mode 100644 index 0000000..4d2a2e5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-machine.h @@ -0,0 +1,51 @@ +/****************************************************************************** +* Filename: sw_ecrypt-machine.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* ecrypt-machine.h */ + +/* + * This file is included by 'ecrypt-portable.h'. It allows to override + * the default macros for specific platforms. Please carefully check + * the machine code generated by your compiler (with optimisations + * turned on) before deciding to edit this file. + */ + +/* ------------------------------------------------------------------------- */ + +#if (defined(ECRYPT_DEFAULT_ROT) && !defined(ECRYPT_MACHINE_ROT)) + +#define ECRYPT_MACHINE_ROT + +#if (defined(WIN32) && defined(_MSC_VER)) + +#undef ROTL32 +#undef ROTR32 +#undef ROTL64 +#undef ROTR64 + +#include + +#define ROTL32(v, n) _lrotl(v, n) +#define ROTR32(v, n) _lrotr(v, n) +#define ROTL64(v, n) _rotl64(v, n) +#define ROTR64(v, n) _rotr64(v, n) + +#endif + +#endif + +/* ------------------------------------------------------------------------- */ + +#if (defined(ECRYPT_DEFAULT_SWAP) && !defined(ECRYPT_MACHINE_SWAP)) + +#define ECRYPT_MACHINE_SWAP + +/* + * If you want to overwrite the default swap macros, put it here. And so on. + */ + +#endif + +/* ------------------------------------------------------------------------- */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-portable.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-portable.h new file mode 100644 index 0000000..8ce940d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-portable.h @@ -0,0 +1,308 @@ +/****************************************************************************** +* Filename: sw_ecrypt-portable.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* ecrypt-portable.h */ + +/* + * WARNING: the conversions defined below are implemented as macros, + * and should be used carefully. They should NOT be used with + * parameters which perform some action. E.g., the following two lines + * are not equivalent: + * + * 1) ++x; y = ROTL32(x, n); + * 2) y = ROTL32(++x, n); + */ + +/* + * *** Please do not edit this file. *** + * + * The default macros can be overridden for specific architectures by + * editing 'ecrypt-machine.h'. + */ + +#ifndef ECRYPT_PORTABLE +#define ECRYPT_PORTABLE + +#include "sw_ecrypt-config.h" + +/* ------------------------------------------------------------------------- */ + +/* + * The following types are defined (if available): + * + * u8: unsigned integer type, at least 8 bits + * u16: unsigned integer type, at least 16 bits + * u32: unsigned integer type, at least 32 bits + * u64: unsigned integer type, at least 64 bits + * + * s8, s16, s32, s64 -> signed counterparts of u8, u16, u32, u64 + * + * The selection of minimum-width integer types is taken care of by + * 'ecrypt-config.h'. Note: to enable 64-bit types on 32-bit + * compilers, it might be necessary to switch from ISO C90 mode to ISO + * C99 mode (e.g., gcc -std=c99). + */ + +#ifdef I8T +typedef signed I8T s8; +typedef unsigned I8T u8; +#endif + +#ifdef I16T +typedef signed I16T s16; +typedef unsigned I16T u16; +#endif + +#ifdef I32T +typedef signed I32T s32; +typedef unsigned I32T u32; +#endif + +#ifdef I64T +typedef signed I64T s64; +typedef unsigned I64T u64; +#endif + +/* + * The following macros are used to obtain exact-width results. + */ + +#define U8V(v) ((u8)(v) & U8C(0xFF)) +#define U16V(v) ((u16)(v) & U16C(0xFFFF)) +#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF)) +#define U64V(v) ((u64)(v) & U64C(0xFFFFFFFFFFFFFFFF)) + +/* ------------------------------------------------------------------------- */ + +/* + * The following macros return words with their bits rotated over n + * positions to the left/right. + */ + +#define ECRYPT_DEFAULT_ROT + +#define ROTL8(v, n) \ + (U8V((v) << (n)) | ((v) >> (8 - (n)))) + +#define ROTL16(v, n) \ + (U16V((v) << (n)) | ((v) >> (16 - (n)))) + +#define ROTL32(v, n) \ + (U32V((v) << (n)) | ((v) >> (32 - (n)))) + +#define ROTL64(v, n) \ + (U64V((v) << (n)) | ((v) >> (64 - (n)))) + +#define ROTR8(v, n) ROTL8(v, 8 - (n)) +#define ROTR16(v, n) ROTL16(v, 16 - (n)) +#define ROTR32(v, n) ROTL32(v, 32 - (n)) +#define ROTR64(v, n) ROTL64(v, 64 - (n)) + +#include "sw_ecrypt-machine.h" + +/* ------------------------------------------------------------------------- */ + +/* + * The following macros return a word with bytes in reverse order. + */ + +#define ECRYPT_DEFAULT_SWAP + +#define SWAP16(v) \ + ROTL16(v, 8) + +#define SWAP32(v) \ + ((ROTL32(v, 8) & U32C(0x00FF00FF)) | \ + (ROTL32(v, 24) & U32C(0xFF00FF00))) + +#ifdef ECRYPT_NATIVE64 +#define SWAP64(v) \ + ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | \ + (ROTL64(v, 24) & U64C(0x0000FF000000FF00)) | \ + (ROTL64(v, 40) & U64C(0x00FF000000FF0000)) | \ + (ROTL64(v, 56) & U64C(0xFF000000FF000000))) +#else +#define SWAP64(v) \ + (((u64)SWAP32(U32V(v)) << 32) | (u64)SWAP32(U32V(v >> 32))) +#endif + +#include "sw_ecrypt-machine.h" + +#define ECRYPT_DEFAULT_WTOW + +#ifdef ECRYPT_LITTLE_ENDIAN +#define U16TO16_LITTLE(v) (v) +#define U32TO32_LITTLE(v) (v) +#define U64TO64_LITTLE(v) (v) + +#define U16TO16_BIG(v) SWAP16(v) +#define U32TO32_BIG(v) SWAP32(v) +#define U64TO64_BIG(v) SWAP64(v) +#endif + +#ifdef ECRYPT_BIG_ENDIAN +#define U16TO16_LITTLE(v) SWAP16(v) +#define U32TO32_LITTLE(v) SWAP32(v) +#define U64TO64_LITTLE(v) SWAP64(v) + +#define U16TO16_BIG(v) (v) +#define U32TO32_BIG(v) (v) +#define U64TO64_BIG(v) (v) +#endif + +#include "sw_ecrypt-machine.h" + +/* + * The following macros load words from an array of bytes with + * different types of endianness, and vice versa. + */ + +#define ECRYPT_DEFAULT_BTOW + +#if (!defined(ECRYPT_UNKNOWN) && defined(ECRYPT_I8T_IS_BYTE)) + +#define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16*)(p))[0]) +#define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32*)(p))[0]) +#define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64*)(p))[0]) + +#define U8TO16_BIG(p) U16TO16_BIG(((u16*)(p))[0]) +#define U8TO32_BIG(p) U32TO32_BIG(((u32*)(p))[0]) +#define U8TO64_BIG(p) U64TO64_BIG(((u64*)(p))[0]) + +#define U16TO8_LITTLE(p, v) (((u16*)(p))[0] = U16TO16_LITTLE(v)) +#define U32TO8_LITTLE(p, v) (((u32*)(p))[0] = U32TO32_LITTLE(v)) +#define U64TO8_LITTLE(p, v) (((u64*)(p))[0] = U64TO64_LITTLE(v)) + +#define U16TO8_BIG(p, v) (((u16*)(p))[0] = U16TO16_BIG(v)) +#define U32TO8_BIG(p, v) (((u32*)(p))[0] = U32TO32_BIG(v)) +#define U64TO8_BIG(p, v) (((u64*)(p))[0] = U64TO64_BIG(v)) + +#else + +#define U8TO16_LITTLE(p) \ + (((u16)((p)[0]) ) | \ + ((u16)((p)[1]) << 8)) + +#define U8TO32_LITTLE(p) \ + (((u32)((p)[0]) ) | \ + ((u32)((p)[1]) << 8) | \ + ((u32)((p)[2]) << 16) | \ + ((u32)((p)[3]) << 24)) + +#ifdef ECRYPT_NATIVE64 +#define U8TO64_LITTLE(p) \ + (((u64)((p)[0]) ) | \ + ((u64)((p)[1]) << 8) | \ + ((u64)((p)[2]) << 16) | \ + ((u64)((p)[3]) << 24) | \ + ((u64)((p)[4]) << 32) | \ + ((u64)((p)[5]) << 40) | \ + ((u64)((p)[6]) << 48) | \ + ((u64)((p)[7]) << 56)) +#else +#define U8TO64_LITTLE(p) \ + ((u64)U8TO32_LITTLE(p) | ((u64)U8TO32_LITTLE((p) + 4) << 32)) +#endif + +#define U8TO16_BIG(p) \ + (((u16)((p)[0]) << 8) | \ + ((u16)((p)[1]) )) + +#define U8TO32_BIG(p) \ + (((u32)((p)[0]) << 24) | \ + ((u32)((p)[1]) << 16) | \ + ((u32)((p)[2]) << 8) | \ + ((u32)((p)[3]) )) + +#ifdef ECRYPT_NATIVE64 +#define U8TO64_BIG(p) \ + (((u64)((p)[0]) << 56) | \ + ((u64)((p)[1]) << 48) | \ + ((u64)((p)[2]) << 40) | \ + ((u64)((p)[3]) << 32) | \ + ((u64)((p)[4]) << 24) | \ + ((u64)((p)[5]) << 16) | \ + ((u64)((p)[6]) << 8) | \ + ((u64)((p)[7]) )) +#else +#define U8TO64_BIG(p) \ + (((u64)U8TO32_BIG(p) << 32) | (u64)U8TO32_BIG((p) + 4)) +#endif + +#define U16TO8_LITTLE(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + } while (0) + +#define U32TO8_LITTLE(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + (p)[2] = U8V((v) >> 16); \ + (p)[3] = U8V((v) >> 24); \ + } while (0) + +#ifdef ECRYPT_NATIVE64 +#define U64TO8_LITTLE(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + (p)[2] = U8V((v) >> 16); \ + (p)[3] = U8V((v) >> 24); \ + (p)[4] = U8V((v) >> 32); \ + (p)[5] = U8V((v) >> 40); \ + (p)[6] = U8V((v) >> 48); \ + (p)[7] = U8V((v) >> 56); \ + } while (0) +#else +#define U64TO8_LITTLE(p, v) \ + do { \ + U32TO8_LITTLE((p), U32V((v) )); \ + U32TO8_LITTLE((p) + 4, U32V((v) >> 32)); \ + } while (0) +#endif + +#define U16TO8_BIG(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + } while (0) + +#define U32TO8_BIG(p, v) \ + do { \ + (p)[0] = U8V((v) >> 24); \ + (p)[1] = U8V((v) >> 16); \ + (p)[2] = U8V((v) >> 8); \ + (p)[3] = U8V((v) ); \ + } while (0) + +#ifdef ECRYPT_NATIVE64 +#define U64TO8_BIG(p, v) \ + do { \ + (p)[0] = U8V((v) >> 56); \ + (p)[1] = U8V((v) >> 48); \ + (p)[2] = U8V((v) >> 40); \ + (p)[3] = U8V((v) >> 32); \ + (p)[4] = U8V((v) >> 24); \ + (p)[5] = U8V((v) >> 16); \ + (p)[6] = U8V((v) >> 8); \ + (p)[7] = U8V((v) ); \ + } while (0) +#else +#define U64TO8_BIG(p, v) \ + do { \ + U32TO8_BIG((p), U32V((v) >> 32)); \ + U32TO8_BIG((p) + 4, U32V((v) )); \ + } while (0) +#endif + +#endif + +#include "sw_ecrypt-machine.h" + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-sync.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-sync.h new file mode 100644 index 0000000..dddb384 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-sync.h @@ -0,0 +1,284 @@ +/****************************************************************************** +* Filename: sw_ecrypt-sync.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* ecrypt-sync.h */ + +/* + * Header file for synchronous stream ciphers without authentication + * mechanism. + * + * *** Please only edit parts marked with "[edit]". *** + */ + +#ifndef ECRYPT_SYNC +#define ECRYPT_SYNC + +#include "sw_ecrypt-portable.h" + +/* ------------------------------------------------------------------------- */ + +/* Cipher parameters */ + +/* + * The name of your cipher. + */ +#define ECRYPT_NAME "ChaCha8" +#define ECRYPT_PROFILE "_____" + +/* + * Specify which key and IV sizes are supported by your cipher. A user + * should be able to enumerate the supported sizes by running the + * following code: + * + * for (i = 0; ECRYPT_KEYSIZE(i) <= ECRYPT_MAXKEYSIZE; ++i) + * { + * keysize = ECRYPT_KEYSIZE(i); + * + * ... + * } + * + * All sizes are in bits. + */ + +#define ECRYPT_MAXKEYSIZE 256 /* [edit] */ +#define ECRYPT_KEYSIZE(i) (128 + (i)*128) /* [edit] */ + +#define ECRYPT_MAXIVSIZE 64 /* [edit] */ +#define ECRYPT_IVSIZE(i) (64 + (i)*64) /* [edit] */ + +/* ------------------------------------------------------------------------- */ + +/* Data structures */ + +/* + * ECRYPT_ctx is the structure containing the representation of the + * internal state of your cipher. + */ + +typedef struct +{ + u32 input[16]; /* could be compressed */ + /* + * [edit] + * + * Put here all state variable needed during the encryption process. + */ +} ECRYPT_ctx; + +/* ------------------------------------------------------------------------- */ + +/* Mandatory functions */ + +/* + * Key and message independent initialization. This function will be + * called once when the program starts (e.g., to build expanded S-box + * tables). + */ +void ECRYPT_init(void); + +/* + * Key setup. It is the user's responsibility to select the values of + * keysize and ivsize from the set of supported values specified + * above. + */ +void ECRYPT_keysetup( + ECRYPT_ctx* ctx, + const u8* key, + u32 keysize, /* Key size in bits. */ + u32 ivsize); /* IV size in bits. */ + +/* + * IV setup. After having called ECRYPT_keysetup(), the user is + * allowed to call ECRYPT_ivsetup() different times in order to + * encrypt/decrypt different messages with the same key but different + * IV's. + */ +void ECRYPT_ivsetup( + ECRYPT_ctx* ctx, + const u8* iv); + +/* + * Encryption/decryption of arbitrary length messages. + * + * For efficiency reasons, the API provides two types of + * encrypt/decrypt functions. The ECRYPT_encrypt_bytes() function + * (declared here) encrypts byte strings of arbitrary length, while + * the ECRYPT_encrypt_blocks() function (defined later) only accepts + * lengths which are multiples of ECRYPT_BLOCKLENGTH. + * + * The user is allowed to make multiple calls to + * ECRYPT_encrypt_blocks() to incrementally encrypt a long message, + * but he is NOT allowed to make additional encryption calls once he + * has called ECRYPT_encrypt_bytes() (unless he starts a new message + * of course). For example, this sequence of calls is acceptable: + * + * ECRYPT_keysetup(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_bytes(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_blocks(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_bytes(); + * + * The following sequence is not: + * + * ECRYPT_keysetup(); + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_bytes(); + * ECRYPT_encrypt_blocks(); + */ + +void ECRYPT_encrypt_bytes( + ECRYPT_ctx* ctx, + const u8* plaintext, + u8* ciphertext, + u32 msglen); /* Message length in bytes. */ + +void ECRYPT_decrypt_bytes( + ECRYPT_ctx* ctx, + const u8* ciphertext, + u8* plaintext, + u32 msglen); /* Message length in bytes. */ + +/* ------------------------------------------------------------------------- */ + +/* Optional features */ + +/* + * For testing purposes it can sometimes be useful to have a function + * which immediately generates keystream without having to provide it + * with a zero plaintext. If your cipher cannot provide this function + * (e.g., because it is not strictly a synchronous cipher), please + * reset the ECRYPT_GENERATES_KEYSTREAM flag. + */ + +#define ECRYPT_GENERATES_KEYSTREAM +#ifdef ECRYPT_GENERATES_KEYSTREAM + +void ECRYPT_keystream_bytes( + ECRYPT_ctx* ctx, + u8* keystream, + u32 length); /* Length of keystream in bytes. */ + +#endif + +/* ------------------------------------------------------------------------- */ + +/* Optional optimizations */ + +/* + * By default, the functions in this section are implemented using + * calls to functions declared above. However, you might want to + * implement them differently for performance reasons. + */ + +/* + * All-in-one encryption/decryption of (short) packets. + * + * The default definitions of these functions can be found in + * "ecrypt-sync.c". If you want to implement them differently, please + * undef the ECRYPT_USES_DEFAULT_ALL_IN_ONE flag. + */ +#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */ + +void ECRYPT_encrypt_packet( + ECRYPT_ctx* ctx, + const u8* iv, + const u8* plaintext, + u8* ciphertext, + u32 msglen); + +void ECRYPT_decrypt_packet( + ECRYPT_ctx* ctx, + const u8* iv, + const u8* ciphertext, + u8* plaintext, + u32 msglen); + +/* + * Encryption/decryption of blocks. + * + * By default, these functions are defined as macros. If you want to + * provide a different implementation, please undef the + * ECRYPT_USES_DEFAULT_BLOCK_MACROS flag and implement the functions + * declared below. + */ + +#define ECRYPT_BLOCKLENGTH 64 /* [edit] */ + +#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */ +#ifdef ECRYPT_USES_DEFAULT_BLOCK_MACROS + +#define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \ + ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, \ + (blocks) * ECRYPT_BLOCKLENGTH) + +#define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \ + ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, \ + (blocks) * ECRYPT_BLOCKLENGTH) + +#ifdef ECRYPT_GENERATES_KEYSTREAM + +#define ECRYPT_keystream_blocks(ctx, keystream, blocks) \ + ECRYPT_keystream_bytes(ctx, keystream, \ + (blocks) * ECRYPT_BLOCKLENGTH) + +#endif + +#else + +void ECRYPT_encrypt_blocks( + ECRYPT_ctx* ctx, + const u8* plaintext, + u8* ciphertext, + u32 blocks); /* Message length in blocks. */ + +void ECRYPT_decrypt_blocks( + ECRYPT_ctx* ctx, + const u8* ciphertext, + u8* plaintext, + u32 blocks); /* Message length in blocks. */ + +#ifdef ECRYPT_GENERATES_KEYSTREAM + +void ECRYPT_keystream_blocks( + ECRYPT_ctx* ctx, + const u8* keystream, + u32 blocks); /* Keystream length in blocks. */ + +#endif + +#endif + +/* + * If your cipher can be implemented in different ways, you can use + * the ECRYPT_VARIANT parameter to allow the user to choose between + * them at compile time (e.g., gcc -DECRYPT_VARIANT=3 ...). Please + * only use this possibility if you really think it could make a + * significant difference and keep the number of variants + * (ECRYPT_MAXVARIANT) as small as possible (definitely not more than + * 10). Note also that all variants should have exactly the same + * external interface (i.e., the same ECRYPT_BLOCKLENGTH, etc.). + */ +#define ECRYPT_MAXVARIANT 1 /* [edit] */ + +#ifndef ECRYPT_VARIANT +#define ECRYPT_VARIANT 1 +#endif + +#if (ECRYPT_VARIANT > ECRYPT_MAXVARIANT) +#error this variant does not exist +#endif + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna-32.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna-32.h new file mode 100644 index 0000000..2aa2eeb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna-32.h @@ -0,0 +1,223 @@ +/****************************************************************************** +* Filename: sw_poly1305-donna-32.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ +/* + poly1305 implementation using 32 bit * 32 bit = 64 bit multiplication and 64 bit addition +*/ + +#if defined(_MSC_VER) + #define POLY1305_NOINLINE __declspec(noinline) +#elif defined(__GNUC__) + #define POLY1305_NOINLINE __attribute__((noinline)) +#else + #define POLY1305_NOINLINE +#endif + +#define poly1305_block_size 16 + +/* 17 + sizeof(size_t) + 14*sizeof(unsigned long) */ +typedef struct { + unsigned long r[5]; + unsigned long h[5]; + unsigned long pad[4]; + size_t leftover; + unsigned char buffer[poly1305_block_size]; + unsigned char final; +} poly1305_state_internal_t; + +/* interpret four 8 bit unsigned integers as a 32 bit unsigned integer in little endian */ +static unsigned long +U8TO32(const unsigned char *p) { + return + (((unsigned long)(p[0] & 0xff) ) | + ((unsigned long)(p[1] & 0xff) << 8) | + ((unsigned long)(p[2] & 0xff) << 16) | + ((unsigned long)(p[3] & 0xff) << 24)); +} + +/* store a 32 bit unsigned integer as four 8 bit unsigned integers in little endian */ +static void +U32TO8(unsigned char *p, unsigned long v) { + p[0] = (v ) & 0xff; + p[1] = (v >> 8) & 0xff; + p[2] = (v >> 16) & 0xff; + p[3] = (v >> 24) & 0xff; +} + +void +poly1305_init(poly1305_context *ctx, const unsigned char key[32]) { + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + + /* r &= 0xffffffc0ffffffc0ffffffc0fffffff */ + st->r[0] = (U8TO32(&key[ 0]) ) & 0x3ffffff; + st->r[1] = (U8TO32(&key[ 3]) >> 2) & 0x3ffff03; + st->r[2] = (U8TO32(&key[ 6]) >> 4) & 0x3ffc0ff; + st->r[3] = (U8TO32(&key[ 9]) >> 6) & 0x3f03fff; + st->r[4] = (U8TO32(&key[12]) >> 8) & 0x00fffff; + + /* h = 0 */ + st->h[0] = 0; + st->h[1] = 0; + st->h[2] = 0; + st->h[3] = 0; + st->h[4] = 0; + + /* save pad for later */ + st->pad[0] = U8TO32(&key[16]); + st->pad[1] = U8TO32(&key[20]); + st->pad[2] = U8TO32(&key[24]); + st->pad[3] = U8TO32(&key[28]); + + st->leftover = 0; + st->final = 0; +} + +static void +poly1305_blocks(poly1305_state_internal_t *st, const unsigned char *m, size_t bytes) { + const unsigned long hibit = (st->final) ? 0 : (1UL << 24); /* 1 << 128 */ + unsigned long r0,r1,r2,r3,r4; + unsigned long s1,s2,s3,s4; + unsigned long h0,h1,h2,h3,h4; + unsigned long long d0,d1,d2,d3,d4; + unsigned long c; + + r0 = st->r[0]; + r1 = st->r[1]; + r2 = st->r[2]; + r3 = st->r[3]; + r4 = st->r[4]; + + s1 = r1 * 5; + s2 = r2 * 5; + s3 = r3 * 5; + s4 = r4 * 5; + + h0 = st->h[0]; + h1 = st->h[1]; + h2 = st->h[2]; + h3 = st->h[3]; + h4 = st->h[4]; + + while (bytes >= poly1305_block_size) { + /* h += m[i] */ + h0 += (U8TO32(m+ 0) ) & 0x3ffffff; + h1 += (U8TO32(m+ 3) >> 2) & 0x3ffffff; + h2 += (U8TO32(m+ 6) >> 4) & 0x3ffffff; + h3 += (U8TO32(m+ 9) >> 6) & 0x3ffffff; + h4 += (U8TO32(m+12) >> 8) | hibit; + + /* h *= r */ + d0 = ((unsigned long long)h0 * r0) + ((unsigned long long)h1 * s4) + ((unsigned long long)h2 * s3) + ((unsigned long long)h3 * s2) + ((unsigned long long)h4 * s1); + d1 = ((unsigned long long)h0 * r1) + ((unsigned long long)h1 * r0) + ((unsigned long long)h2 * s4) + ((unsigned long long)h3 * s3) + ((unsigned long long)h4 * s2); + d2 = ((unsigned long long)h0 * r2) + ((unsigned long long)h1 * r1) + ((unsigned long long)h2 * r0) + ((unsigned long long)h3 * s4) + ((unsigned long long)h4 * s3); + d3 = ((unsigned long long)h0 * r3) + ((unsigned long long)h1 * r2) + ((unsigned long long)h2 * r1) + ((unsigned long long)h3 * r0) + ((unsigned long long)h4 * s4); + d4 = ((unsigned long long)h0 * r4) + ((unsigned long long)h1 * r3) + ((unsigned long long)h2 * r2) + ((unsigned long long)h3 * r1) + ((unsigned long long)h4 * r0); + + /* (partial) h %= p */ + c = (unsigned long)(d0 >> 26); h0 = (unsigned long)d0 & 0x3ffffff; + d1 += c; c = (unsigned long)(d1 >> 26); h1 = (unsigned long)d1 & 0x3ffffff; + d2 += c; c = (unsigned long)(d2 >> 26); h2 = (unsigned long)d2 & 0x3ffffff; + d3 += c; c = (unsigned long)(d3 >> 26); h3 = (unsigned long)d3 & 0x3ffffff; + d4 += c; c = (unsigned long)(d4 >> 26); h4 = (unsigned long)d4 & 0x3ffffff; + h0 += c * 5; c = (h0 >> 26); h0 = h0 & 0x3ffffff; + h1 += c; + + m += poly1305_block_size; + bytes -= poly1305_block_size; + } + + st->h[0] = h0; + st->h[1] = h1; + st->h[2] = h2; + st->h[3] = h3; + st->h[4] = h4; +} + +POLY1305_NOINLINE void +poly1305_finish(poly1305_context *ctx, unsigned char mac[16]) { + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + unsigned long h0,h1,h2,h3,h4,c; + unsigned long g0,g1,g2,g3,g4; + unsigned long long f; + unsigned long mask; + + /* process the remaining block */ + if (st->leftover) { + size_t i = st->leftover; + st->buffer[i++] = 1; + for (; i < poly1305_block_size; i++) + st->buffer[i] = 0; + st->final = 1; + poly1305_blocks(st, st->buffer, poly1305_block_size); + } + + /* fully carry h */ + h0 = st->h[0]; + h1 = st->h[1]; + h2 = st->h[2]; + h3 = st->h[3]; + h4 = st->h[4]; + + c = h1 >> 26; h1 = h1 & 0x3ffffff; + h2 += c; c = h2 >> 26; h2 = h2 & 0x3ffffff; + h3 += c; c = h3 >> 26; h3 = h3 & 0x3ffffff; + h4 += c; c = h4 >> 26; h4 = h4 & 0x3ffffff; + h0 += c * 5; c = h0 >> 26; h0 = h0 & 0x3ffffff; + h1 += c; + + /* compute h + -p */ + g0 = h0 + 5; c = g0 >> 26; g0 &= 0x3ffffff; + g1 = h1 + c; c = g1 >> 26; g1 &= 0x3ffffff; + g2 = h2 + c; c = g2 >> 26; g2 &= 0x3ffffff; + g3 = h3 + c; c = g3 >> 26; g3 &= 0x3ffffff; + g4 = h4 + c - (1UL << 26); + + /* select h if h < p, or h + -p if h >= p */ + mask = (g4 >> ((sizeof(unsigned long) * 8) - 1)) - 1; + g0 &= mask; + g1 &= mask; + g2 &= mask; + g3 &= mask; + g4 &= mask; + mask = ~mask; + h0 = (h0 & mask) | g0; + h1 = (h1 & mask) | g1; + h2 = (h2 & mask) | g2; + h3 = (h3 & mask) | g3; + h4 = (h4 & mask) | g4; + + /* h = h % (2^128) */ + h0 = ((h0 ) | (h1 << 26)) & 0xffffffff; + h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff; + h2 = ((h2 >> 12) | (h3 << 14)) & 0xffffffff; + h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff; + + /* mac = (h + pad) % (2^128) */ + f = (unsigned long long)h0 + st->pad[0] ; h0 = (unsigned long)f; + f = (unsigned long long)h1 + st->pad[1] + (f >> 32); h1 = (unsigned long)f; + f = (unsigned long long)h2 + st->pad[2] + (f >> 32); h2 = (unsigned long)f; + f = (unsigned long long)h3 + st->pad[3] + (f >> 32); h3 = (unsigned long)f; + + U32TO8(mac + 0, h0); + U32TO8(mac + 4, h1); + U32TO8(mac + 8, h2); + U32TO8(mac + 12, h3); + + /* zero out the state */ + st->h[0] = 0; + st->h[1] = 0; + st->h[2] = 0; + st->h[3] = 0; + st->h[4] = 0; + st->r[0] = 0; + st->r[1] = 0; + st->r[2] = 0; + st->r[3] = 0; + st->r[4] = 0; + st->pad[0] = 0; + st->pad[1] = 0; + st->pad[2] = 0; + st->pad[3] = 0; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna.c new file mode 100644 index 0000000..2c1680e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna.c @@ -0,0 +1,186 @@ +/****************************************************************************** +* Filename: sw_poly1305-donna.c +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ + +#include "sw_poly1305-donna.h" + +#include "sw_poly1305-donna-32.h" + +void +poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes) { + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + size_t i; + + /* handle leftover */ + if (st->leftover) { + size_t want = (poly1305_block_size - st->leftover); + if (want > bytes) + want = bytes; + for (i = 0; i < want; i++) + st->buffer[st->leftover + i] = m[i]; + bytes -= want; + m += want; + st->leftover += want; + if (st->leftover < poly1305_block_size) + return; + poly1305_blocks(st, st->buffer, poly1305_block_size); + st->leftover = 0; + } + + /* process full blocks */ + if (bytes >= poly1305_block_size) { + size_t want = (bytes & ~(poly1305_block_size - 1)); + poly1305_blocks(st, m, want); + m += want; + bytes -= want; + } + + /* store leftover */ + if (bytes) { + for (i = 0; i < bytes; i++) + st->buffer[st->leftover + i] = m[i]; + st->leftover += bytes; + } +} + +void +poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]) { + poly1305_context ctx; + poly1305_init(&ctx, key); + poly1305_update(&ctx, m, bytes); + poly1305_finish(&ctx, mac); +} + +int +poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]) { + size_t i; + unsigned int dif = 0; + for (i = 0; i < 16; i++) + dif |= (mac1[i] ^ mac2[i]); + dif = (dif - 1) >> ((sizeof(unsigned int) * 8) - 1); + return (dif & 1); +} + + +/* test a few basic operations */ +int +poly1305_power_on_self_test(void) { + /* example from nacl */ + static const unsigned char nacl_key[32] = { + 0xee,0xa6,0xa7,0x25,0x1c,0x1e,0x72,0x91, + 0x6d,0x11,0xc2,0xcb,0x21,0x4d,0x3c,0x25, + 0x25,0x39,0x12,0x1d,0x8e,0x23,0x4e,0x65, + 0x2d,0x65,0x1f,0xa4,0xc8,0xcf,0xf8,0x80 + }; + + static const unsigned char nacl_msg[131] = { + 0x8e,0x99,0x3b,0x9f,0x48,0x68,0x12,0x73, + 0xc2,0x96,0x50,0xba,0x32,0xfc,0x76,0xce, + 0x48,0x33,0x2e,0xa7,0x16,0x4d,0x96,0xa4, + 0x47,0x6f,0xb8,0xc5,0x31,0xa1,0x18,0x6a, + 0xc0,0xdf,0xc1,0x7c,0x98,0xdc,0xe8,0x7b, + 0x4d,0xa7,0xf0,0x11,0xec,0x48,0xc9,0x72, + 0x71,0xd2,0xc2,0x0f,0x9b,0x92,0x8f,0xe2, + 0x27,0x0d,0x6f,0xb8,0x63,0xd5,0x17,0x38, + 0xb4,0x8e,0xee,0xe3,0x14,0xa7,0xcc,0x8a, + 0xb9,0x32,0x16,0x45,0x48,0xe5,0x26,0xae, + 0x90,0x22,0x43,0x68,0x51,0x7a,0xcf,0xea, + 0xbd,0x6b,0xb3,0x73,0x2b,0xc0,0xe9,0xda, + 0x99,0x83,0x2b,0x61,0xca,0x01,0xb6,0xde, + 0x56,0x24,0x4a,0x9e,0x88,0xd5,0xf9,0xb3, + 0x79,0x73,0xf6,0x22,0xa4,0x3d,0x14,0xa6, + 0x59,0x9b,0x1f,0x65,0x4c,0xb4,0x5a,0x74, + 0xe3,0x55,0xa5 + }; + + static const unsigned char nacl_mac[16] = { + 0xf3,0xff,0xc7,0x70,0x3f,0x94,0x00,0xe5, + 0x2a,0x7d,0xfb,0x4b,0x3d,0x33,0x05,0xd9 + }; + + /* generates a final value of (2^130 - 2) == 3 */ + static const unsigned char wrap_key[32] = { + 0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + }; + + static const unsigned char wrap_msg[16] = { + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff + }; + + static const unsigned char wrap_mac[16] = { + 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + }; + + /* + mac of the macs of messages of length 0 to 256, where the key and messages + have all their values set to the length + */ + static const unsigned char total_key[32] = { + 0x01,0x02,0x03,0x04,0x05,0x06,0x07, + 0xff,0xfe,0xfd,0xfc,0xfb,0xfa,0xf9, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff + }; + + static const unsigned char total_mac[16] = { + 0x64,0xaf,0xe2,0xe8,0xd6,0xad,0x7b,0xbd, + 0xd2,0x87,0xf9,0x7c,0x44,0x62,0x3d,0x39 + }; + + poly1305_context ctx; + poly1305_context total_ctx; + unsigned char all_key[32]; + unsigned char all_msg[256]; + unsigned char mac[16]; + size_t i, j; + int result = 1; + + for (i = 0; i < sizeof(mac); i++) + mac[i] = 0; + poly1305_auth(mac, nacl_msg, sizeof(nacl_msg), nacl_key); + result &= poly1305_verify(nacl_mac, mac); + + for (i = 0; i < sizeof(mac); i++) + mac[i] = 0; + poly1305_init(&ctx, nacl_key); + poly1305_update(&ctx, nacl_msg + 0, 32); + poly1305_update(&ctx, nacl_msg + 32, 64); + poly1305_update(&ctx, nacl_msg + 96, 16); + poly1305_update(&ctx, nacl_msg + 112, 8); + poly1305_update(&ctx, nacl_msg + 120, 4); + poly1305_update(&ctx, nacl_msg + 124, 2); + poly1305_update(&ctx, nacl_msg + 126, 1); + poly1305_update(&ctx, nacl_msg + 127, 1); + poly1305_update(&ctx, nacl_msg + 128, 1); + poly1305_update(&ctx, nacl_msg + 129, 1); + poly1305_update(&ctx, nacl_msg + 130, 1); + poly1305_finish(&ctx, mac); + result &= poly1305_verify(nacl_mac, mac); + + for (i = 0; i < sizeof(mac); i++) + mac[i] = 0; + poly1305_auth(mac, wrap_msg, sizeof(wrap_msg), wrap_key); + result &= poly1305_verify(wrap_mac, mac); + + poly1305_init(&total_ctx, total_key); + for (i = 0; i < 256; i++) { + /* set key and message to 'i,i,i..' */ + for (j = 0; j < sizeof(all_key); j++) + all_key[j] = i; + for (j = 0; j < i; j++) + all_msg[j] = i; + poly1305_auth(mac, all_msg, i, all_key); + poly1305_update(&total_ctx, mac, 16); + } + poly1305_finish(&total_ctx, mac); + result &= poly1305_verify(total_mac, mac); + + return result; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna.h new file mode 100644 index 0000000..574efab --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna.h @@ -0,0 +1,25 @@ +/****************************************************************************** +* Filename: sw_poly1305-donna.h +* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) +* Revision: 47308 +******************************************************************************/ + +#ifndef POLY1305_DONNA_H +#define POLY1305_DONNA_H + +#include + +typedef struct { + size_t aligner; + unsigned char opaque[136]; +} poly1305_context; + +void poly1305_init(poly1305_context *ctx, const unsigned char key[32]); +void poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes); +void poly1305_finish(poly1305_context *ctx, unsigned char mac[16]); +void poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]); + +int poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]); +int poly1305_power_on_self_test(void); + +#endif /* POLY1305_DONNA_H */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sys_ctrl.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sys_ctrl.c new file mode 100644 index 0000000..e5c57e2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sys_ctrl.c @@ -0,0 +1,422 @@ +/****************************************************************************** +* Filename: sys_ctrl.c +* Revised: 2018-06-26 15:19:11 +0200 (Tue, 26 Jun 2018) +* Revision: 52220 +* +* Description: Driver for the System Control. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +// Hardware headers +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +// Driverlib headers +#include "aon_batmon.h" +#include "setup_rom.h" +#include "sys_ctrl.h" + + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SysCtrlSetRechargeBeforePowerDown + #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown + #undef SysCtrlAdjustRechargeAfterPowerDown + #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown + #undef SysCtrl_DCDC_VoltageConditionalControl + #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl + #undef SysCtrlResetSourceGet + #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet +#endif + +//***************************************************************************** +// +// Recharge calculator defines and globals +// +//***************************************************************************** + +#define PD_STATE_CACHE_RET 1 +#define PD_STATE_RFMEM_RET 2 +#define PD_STATE_XOSC_LPM 4 +#define PD_STATE_EXT_REG_MODE 8 + +typedef struct { + uint32_t pdTime ; + uint16_t pdRechargePeriod ; + uint8_t pdState ; + int8_t pdTemp ; +} PowerQualGlobals_t; + +static PowerQualGlobals_t powerQualGlobals; + + +//***************************************************************************** +// +// SysCtrlSetRechargeBeforePowerDown( xoscPowerMode ) +// +//***************************************************************************** +void +SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ) +{ + int32_t curTemp ; + int32_t shiftedTemp ; + int32_t deltaVddrSleepTrim ; + int32_t vddrTrimSleep ; + int32_t vddrTrimActve ; + int32_t diffVddrActiveSleep ; + uint32_t ccfg_ModeConfReg ; + uint32_t curState ; + uint32_t prcmRamRetention ; + uint32_t di ; + uint32_t dii ; + uint32_t ti ; + uint32_t cd ; + uint32_t cl ; + uint32_t load ; + uint32_t k ; + uint32_t vddrCap ; + uint32_t newRechargePeriod ; + uint32_t perE ; + uint32_t perM ; + const uint32_t * pLookupTable ; + + // If external regulator mode we shall: + // - Disable adaptive recharge (bit[31]=0) in AON_WUC_O_RECHARGECFG + // - Set recharge period to approximately 500 mS (perM=31, perE=5 => 0xFD) + // - Make sure you get a recalculation if leaving external regulator mode by setting powerQualGlobals.pdState accordingly + if ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE ) { + powerQualGlobals.pdState = PD_STATE_EXT_REG_MODE; + HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGECFG ) = 0x00A4FDFD; + return; + } + + //--- Spec. point 1 --- + curTemp = AONBatMonTemperatureGetDegC(); + curState = 0; + + // read the MODE_CONF register in CCFG + ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + // Get VDDR_TRIM_SLEEP_DELTA + 1 (sign extended) + deltaVddrSleepTrim = ((((int32_t) ccfg_ModeConfReg ) + << ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S )) + >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W )) + 1; + // Do temperature compensation if enabled + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC ) == 0 ) { + int32_t tcDelta = ( 62 - curTemp ) >> 3; + if ( tcDelta > 8 ) tcDelta = 8; + if ( tcDelta > deltaVddrSleepTrim ) deltaVddrSleepTrim = tcDelta; + } + { + vddrTrimSleep = SetupSignExtendVddrTrimValue(( + HWREG( FCFG1_BASE + FCFG1_O_LDO_TRIM ) & + FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M ) >> + FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S ) ; + vddrTrimActve = SetupSignExtendVddrTrimValue(( + HWREG( FCFG1_BASE + FCFG1_O_SHDW_ANA_TRIM ) & + FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M ) >> + FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S ) ; + } + vddrTrimSleep += deltaVddrSleepTrim; + if ( vddrTrimSleep > 21 ) vddrTrimSleep = 21; + if ( vddrTrimSleep < -10 ) vddrTrimSleep = -10; + // Write adjusted value using MASKED write (MASK8) + HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_DCDCCTL1 * 2 )) = (( ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M << 8 ) | + (( vddrTrimSleep << ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S ) & ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M )); + + prcmRamRetention = HWREG( PRCM_BASE + PRCM_O_RAMRETEN ); + if ( prcmRamRetention & PRCM_RAMRETEN_VIMS_M ) { + curState |= PD_STATE_CACHE_RET; + } + if ( prcmRamRetention & PRCM_RAMRETEN_RFC ) { + curState |= PD_STATE_RFMEM_RET; + } + if ( xoscPowerMode != XOSC_IN_HIGH_POWER_MODE ) { + curState |= PD_STATE_XOSC_LPM; + } + + //--- Spec. point 2 --- + if ((( curTemp - powerQualGlobals.pdTemp ) >= 5 ) || ( curState != powerQualGlobals.pdState )) { + //--- Spec. point 3 --- + shiftedTemp = curTemp - 15; + + //--- Spec point 4 --- + //4. Check for external VDDR load option (may not be supported): ext_load = (VDDR_EXT_LOAD=0 in CCFG) + // Currently not implementing external load handling + // if ( __ccfg.ulModeConfig & MODE_CONF_VDDR_EXT_LOAD ) { + // } + + pLookupTable = (uint32_t *)( FCFG1_BASE + FCFG1_O_PWD_CURR_20C ); + + //--- Spec point 5 --- + di = 0; + ti = 0; + if ( shiftedTemp >= 0 ) { + //--- Spec point 5.a --- + shiftedTemp += ( shiftedTemp << 4 ); + + //--- Spec point 5.b --- + ti = ( shiftedTemp >> 8 ); + if ( ti > 7 ) { + ti = 7; + } + dii = ti; + if ( dii > 6 ) { + dii = 6; + } + + //--- Spec point 5.c --- + cd = pLookupTable[ dii + 1 ] - pLookupTable[ dii ]; + + //--- Spec point 5.d --- + di = cd & 0xFF; + + //--- Spec point 5.e --- + if ( curState & PD_STATE_XOSC_LPM ) { + di += (( cd >> 8 ) & 0xFF ); + } + if ( curState & PD_STATE_RFMEM_RET ) { + di += (( cd >> 16 ) & 0xFF ); + } + if ( curState & PD_STATE_CACHE_RET ) { + di += (( cd >> 24 ) & 0xFF ); + } + + //--- Spec point 5.f --- + // Currently not implementing external load handling + } + + //--- Spec. point 6 --- + cl = pLookupTable[ ti ]; + + //--- Spec. point 7 --- + load = cl & 0xFF; + + //--- Spec. point 8 --- + if ( curState & PD_STATE_XOSC_LPM ) { + load += (( cl >> 8 ) & 0xFF ); + } + if ( curState & PD_STATE_RFMEM_RET ) { + load += (( cl >> 16 ) & 0xFF ); + } + if ( curState & PD_STATE_CACHE_RET ) { + load += (( cl >> 24 ) & 0xFF ); + } + + //--- Spec. point 9 --- + load += ((( di * ( shiftedTemp - ( ti << 8 ))) + 128 ) >> 8 ); + + // Currently not implementing external load handling + // if ( __ccfg.ulModeConfig & MODE_CONF_VDDR_EXT_LOAD ) { + //--- Spec. point 10 --- + // } else { + //--- Spec. point 11 --- + diffVddrActiveSleep = ( vddrTrimActve - vddrTrimSleep ); + if ( diffVddrActiveSleep < 1 ) diffVddrActiveSleep = 1; + k = ( diffVddrActiveSleep * 52 ); + // } + + //--- Spec. point 12 --- + + vddrCap = ( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_CAP_M ) >> CCFG_MODE_CONF_VDDR_CAP_S; + newRechargePeriod = ( vddrCap * k ) / load; + if ( newRechargePeriod > 0xFFFF ) { + newRechargePeriod = 0xFFFF; + } + powerQualGlobals.pdRechargePeriod = newRechargePeriod; + + //--- Spec. point 13 --- + if ( curTemp > 127 ) curTemp = 127; + if ( curTemp < -128 ) curTemp = -128; + powerQualGlobals.pdTemp = curTemp; + powerQualGlobals.pdState = curState; + } + + powerQualGlobals.pdTime = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + + // Calculate PER_E and PER_M (based on powerQualGlobals.pdRechargePeriod) + // Round downwards but make sure PER_E=0 and PER_M=1 is the minimum possible setting. + // (assuming that powerQualGlobals.pdRechargePeriod always are <= 0xFFFF) + perE = 0; + perM = powerQualGlobals.pdRechargePeriod; + if ( perM < 31 ) { + perM = 31; + powerQualGlobals.pdRechargePeriod = 31; + } + while ( perM > 511 ) { + perM >>= 1; + perE += 1; + } + perM = ( perM - 15 ) >> 4; + + HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGECFG ) = + ( 0x80A4E700 ) | + ( perM << AON_WUC_RECHARGECFG_PER_M_S ) | + ( perE << AON_WUC_RECHARGECFG_PER_E_S ) ; + HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGESTAT ) = 0; +} + + +//***************************************************************************** +// +// SysCtrlAdjustRechargeAfterPowerDown() +// +//***************************************************************************** +void +SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ) +{ + int32_t curTemp ; + uint32_t longestRechargePeriod ; + uint32_t deltaTime ; + uint32_t newRechargePeriod ; + + //--- Spec. point 2 --- + longestRechargePeriod = ( HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGESTAT ) & + AON_WUC_RECHARGESTAT_MAX_USED_PER_M ) >> + AON_WUC_RECHARGESTAT_MAX_USED_PER_S ; + + if ( longestRechargePeriod != 0 ) { + //--- Spec. changed (originally point 1) --- + curTemp = AONBatMonTemperatureGetDegC(); + if ( curTemp < powerQualGlobals.pdTemp ) { + if ( curTemp < -128 ) { + curTemp = -128; + } + powerQualGlobals.pdTemp = curTemp; + } + + // Add some margin between the longest previous recharge period and the + // next initial recharge period. Since it is a fixed margin, it will have a + // higher impact as a fraction of the converged recharge period at higher temperatures + // where it is needed more due to higher leakage. + if (longestRechargePeriod > vddrRechargeMargin) { + longestRechargePeriod -= vddrRechargeMargin; + } + else { + longestRechargePeriod = 1; + } + + //--- Spec. point 4 --- + if ( longestRechargePeriod < powerQualGlobals.pdRechargePeriod ) { + powerQualGlobals.pdRechargePeriod = longestRechargePeriod; + } else { + //--- Spec. point 5 --- + deltaTime = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ) - powerQualGlobals.pdTime + 2; + if ( deltaTime > 31 ) { + deltaTime = 31; + } + newRechargePeriod = powerQualGlobals.pdRechargePeriod + (( longestRechargePeriod - powerQualGlobals.pdRechargePeriod ) >> (deltaTime>>1)); + if ( newRechargePeriod > 0xFFFF ) { + newRechargePeriod = 0xFFFF; + } + powerQualGlobals.pdRechargePeriod = newRechargePeriod; + } + } +} + + +//***************************************************************************** +// +// SysCtrl_DCDC_VoltageConditionalControl() +// +//***************************************************************************** +void +SysCtrl_DCDC_VoltageConditionalControl( void ) +{ + uint32_t batThreshold ; // Fractional format with 8 fractional bits. + uint32_t aonBatmonBat ; // Fractional format with 8 fractional bits. + uint32_t ccfg_ModeConfReg ; // Holds a copy of the CCFG_O_MODE_CONF register. + uint32_t aonSysctlPwrctl ; // Reflect whats read/written to the AON_SYSCTL_O_PWRCTL register. + + // We could potentially call this function before any battery voltage measurement + // is made/available. In that case we must make sure that we do not turn off the DCDC. + // This can be done by doing nothing as long as the battery voltage is 0 (Since the + // reset value of the battery voltage register is 0). + aonBatmonBat = HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT ); + if ( aonBatmonBat != 0 ) { + // Check if Voltage Conditional Control is enabled + // It is enabled if all the following are true: + // - DCDC in use (either in active or recharge mode), (in use if one of the corresponding CCFG bits are zero). + // - Alternative DCDC settings are enabled ( DIS_ALT_DCDC_SETTING == 0 ) + // - Not in external regulator mode ( EXT_REG_MODE == 0 ) + ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + + if (((( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) || + (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) ) && + (( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE ) == 0 ) && + (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) ) + { + aonSysctlPwrctl = HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ); + batThreshold = (((( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & + CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) >> + CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) + 28 ) << 4 ); + + if ( aonSysctlPwrctl & ( AON_SYSCTL_PWRCTL_DCDC_EN_M | AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M )) { + // DCDC is ON, check if it should be switched off + if ( aonBatmonBat < batThreshold ) { + aonSysctlPwrctl &= ~( AON_SYSCTL_PWRCTL_DCDC_EN_M | AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M ); + + HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) = aonSysctlPwrctl; + } + } else { + // DCDC is OFF, check if it should be switched on + if ( aonBatmonBat > batThreshold ) { + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) aonSysctlPwrctl |= AON_SYSCTL_PWRCTL_DCDC_EN_M ; + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) aonSysctlPwrctl |= AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M ; + + HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) = aonSysctlPwrctl; + } + } + } + } +} + + +//***************************************************************************** +// +// SysCtrlResetSourceGet() +// +//***************************************************************************** +uint32_t +SysCtrlResetSourceGet( void ) +{ + uint32_t aonSysctlResetCtl = HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ); + + if ( aonSysctlResetCtl & AON_SYSCTL_RESETCTL_WU_FROM_SD_M ) { + return ( RSTSRC_WAKEUP_FROM_SHUTDOWN ); + } else { + return (( aonSysctlResetCtl & AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> AON_SYSCTL_RESETCTL_RESET_SRC_S ) ; + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sys_ctrl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sys_ctrl.h new file mode 100644 index 0000000..02d3789 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sys_ctrl.h @@ -0,0 +1,418 @@ +/****************************************************************************** +* Filename: sys_ctrl.h +* Revised: 2018-09-17 14:58:51 +0200 (Mon, 17 Sep 2018) +* Revision: 52634 +* +* Description: Defines and prototypes for the System Controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup sysctrl_api +//! @{ +// +//***************************************************************************** + +#ifndef __SYSCTRL_H__ +#define __SYSCTRL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_sysctl.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_aux_wuc.h" +#include "../inc/hw_aon_ioc.h" +#include "../inc/hw_ddi_0_osc.h" +#include "../inc/hw_rfc_pwr.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_aon_sysctl.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_fcfg1.h" +#include "interrupt.h" +#include "debug.h" +#include "pwr_ctrl.h" +#include "osc.h" +#include "prcm.h" +#include "aux_wuc.h" +#include "aon_wuc.h" +#include "adi.h" +#include "ddi.h" +#include "cpu.h" +#include "vims.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown + #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown + #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl + #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet +#endif + +//***************************************************************************** +// +// Defines for the settings of the main XOSC +// +//***************************************************************************** +#define SYSCTRL_SYSBUS_ON 0x00000001 +#define SYSCTRL_SYSBUS_OFF 0x00000000 + +//***************************************************************************** +// +// Defines for the different power modes of the System CPU +// +//***************************************************************************** +#define CPU_RUN 0x00000000 +#define CPU_SLEEP 0x00000001 +#define CPU_DEEP_SLEEP 0x00000002 + +//***************************************************************************** +// +// Defines for SysCtrlSetRechargeBeforePowerDown +// +//***************************************************************************** +#define XOSC_IN_HIGH_POWER_MODE 0 // When xosc_hf is in HIGH_POWER_XOSC +#define XOSC_IN_LOW_POWER_MODE 1 // When xosc_hf is in LOW_POWER_XOSC + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Get the CPU core clock frequency. +//! +//! Use this function to get the current clock frequency for the CPU. +//! +//! The CPU can run from 48 MHz and down to 750kHz. The frequency is defined +//! by the combined division factor of the SYSBUS and the CPU clock divider. +//! +//! \return Returns the current CPU core clock frequency. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SysCtrlClockGet( void ) +{ + // Return fixed clock speed + return( GET_MCU_CLOCK ); +} + +//***************************************************************************** +// +//! \brief Sync all accesses to the AON register interface. +//! +//! When this function returns, all writes to the AON register interface are +//! guaranteed to have propagated to hardware. The function will return +//! immediately if no AON writes are pending; otherwise, it will wait for the next +//! AON clock before returning. +//! +//! \return None +//! +//! \sa \ref SysCtrlAonUpdate() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlAonSync(void) +{ + // Sync the AON interface + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! \brief Update all interfaces to AON. +//! +//! When this function returns, at least 1 clock cycle has progressed on the +//! AON domain, so that any outstanding updates to and from the AON interface +//! is guaranteed to be in sync. +//! +//! \note This function should primarily be used after wakeup from sleep modes, +//! as it will guarantee that all shadow registers on the AON interface are updated +//! before reading any AON registers from the MCU domain. If a write has been +//! done to the AON interface it is sufficient to call the \ref SysCtrlAonSync(). +//! +//! \return None +//! +//! \sa \ref SysCtrlAonSync() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlAonUpdate(void) +{ + // Force a clock cycle on the AON interface to guarantee all registers are + // in sync. + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC) = 1; + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! \brief Set Recharge values before entering Power Down. +//! +//! This function shall be called just before entering Power Down. +//! It calculates an optimal and safe recharge setting of the adaptive recharge +//! controller. The results of previous setting are also taken into account. +//! +//! \note In order to make sure that the register writes are completed, \ref SysCtrlAonSync() +//! must be called before entering standby/power down. This is not done internally +//! in this function due to two reasons: +//! - 1) There might be other register writes that must be synchronized as well. +//! - 2) It is possible to save some time by doing other things before calling +//! \ref SysCtrlAonSync() since this call will not return before there are no +//! outstanding write requests between MCU and AON. +//! +//! \param xoscPowerMode (typically running in XOSC_IN_HIGH_POWER_MODE all the time). +//! - \ref XOSC_IN_HIGH_POWER_MODE : When xosc_hf is in HIGH_POWER_XOSC. +//! - \ref XOSC_IN_LOW_POWER_MODE : When xosc_hf is in LOW_POWER_XOSC. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ); + +//***************************************************************************** +// +//! \brief Adjust Recharge calculations to be used next. +//! +//! This function shall be called just after returning from Power Down. +//! +//! Reads the results from the adaptive recharge controller and current chip +//! temperature. This is used as additional information when calculating +//! optimal recharge controller settings next time (When +//! \ref SysCtrlSetRechargeBeforePowerDown() is called next time). +//! +//! \param vddrRechargeMargin margin in SCLK_LF periods to subtract from +//! previous longest recharge period experienced while in standby. +//! +//! \note +//! Special care must be taken to make sure that the AON registers read are +//! updated after the wakeup. Writing to an AON register and then calling +//! \ref SysCtrlAonSync() will handle this. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ); + +//***************************************************************************** +// +//! \brief Turns DCDC on or off depending of what is considered to be optimal usage. +//! +//! This function controls the DCDC only if both the following CCFG settings are \c true: +//! - DCDC is configured to be used. +//! - Alternative DCDC settings are defined and enabled. +//! +//! The DCDC is configured in accordance to the CCFG settings when turned on. +//! +//! This function should be called periodically. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrl_DCDC_VoltageConditionalControl( void ); + +//***************************************************************************** +// \name Return values from calling SysCtrlResetSourceGet() +//@{ +//***************************************************************************** +#define RSTSRC_PWR_ON (( AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_PIN_RESET (( AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_VDDS_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_VDDR_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_CLK_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_SYSRESET (( AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_WARMRESET (( AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_WAKEUP_FROM_SHUTDOWN ((( AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) + 1 ) +//@} + +//***************************************************************************** +// +//! \brief Returns the reset source (including "wakeup from shutdown"). +//! +//! In case of \ref RSTSRC_WAKEUP_FROM_SHUTDOWN the application is +//! responsible for unlatching the outputs (disable pad sleep). +//! See \ref PowerCtrlPadSleepDisable() for more information. +//! +//! \return Returns the reset source. +//! - \ref RSTSRC_PWR_ON +//! - \ref RSTSRC_PIN_RESET +//! - \ref RSTSRC_VDDS_LOSS +//! - \ref RSTSRC_VDDR_LOSS +//! - \ref RSTSRC_CLK_LOSS +//! - \ref RSTSRC_SYSRESET +//! - \ref RSTSRC_WARMRESET +//! - \ref RSTSRC_WAKEUP_FROM_SHUTDOWN +// +//***************************************************************************** +extern uint32_t SysCtrlResetSourceGet( void ); + +//***************************************************************************** +// +//! \brief Perform a full system reset. +//! +//! \return The chip will reset and hence never return from this call. +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlSystemReset( void ) +{ + // Disable CPU interrupts + CPUcpsid(); + // Write reset register + HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_SYSRESET_BITN ) = 1; + // Finally, wait until the above write propagates + while ( 1 ) { + // Do nothing, just wait for the reset (and never return from here) + } +} + +//***************************************************************************** +// +//! \brief Enables reset if OSC clock loss event is asserted. +//! +//! Clock loss circuit in analog domain must be enabled as well in order to +//! actually enable for a clock loss reset to occur +//! \ref OSCClockLossEventEnable(). +//! +//! \note This function shall typically not be called because the clock loss +//! reset functionality is controlled by the boot code (a factory configuration +//! defines whether it is set or not). +//! +//! \return None +//! +//! \sa \ref SysCtrlClockLossResetDisable(), \ref OSCClockLossEventEnable() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlClockLossResetEnable(void) +{ + // Set clock loss enable bit in AON_SYSCTRL using bit banding + HWREGBITW(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disables reset due to OSC clock loss event. +//! +//! \note This function shall typically not be called because the clock loss +//! reset functionality is controlled by the boot code (a factory configuration +//! defines whether it is set or not). +//! +//! \return None +//! +//! \sa \ref SysCtrlClockLossResetEnable() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlClockLossResetDisable(void) +{ + // Clear clock loss enable bit in AON_SYSCTRL using bit banding + HWREGBITW(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN) = 0; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SysCtrlSetRechargeBeforePowerDown + #undef SysCtrlSetRechargeBeforePowerDown + #define SysCtrlSetRechargeBeforePowerDown ROM_SysCtrlSetRechargeBeforePowerDown + #endif + #ifdef ROM_SysCtrlAdjustRechargeAfterPowerDown + #undef SysCtrlAdjustRechargeAfterPowerDown + #define SysCtrlAdjustRechargeAfterPowerDown ROM_SysCtrlAdjustRechargeAfterPowerDown + #endif + #ifdef ROM_SysCtrl_DCDC_VoltageConditionalControl + #undef SysCtrl_DCDC_VoltageConditionalControl + #define SysCtrl_DCDC_VoltageConditionalControl ROM_SysCtrl_DCDC_VoltageConditionalControl + #endif + #ifdef ROM_SysCtrlResetSourceGet + #undef SysCtrlResetSourceGet + #define SysCtrlResetSourceGet ROM_SysCtrlResetSourceGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTRL_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick.c new file mode 100644 index 0000000..29aa43b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: systick.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the SysTick timer in NVIC +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "systick.h" + +// See systick.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick.h new file mode 100644 index 0000000..735171d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick.h @@ -0,0 +1,287 @@ +/****************************************************************************** +* Filename: systick.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Prototypes for the SysTick driver. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_types.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// API Functions and Prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enables the SysTick counter. +//! +//! This will start the SysTick counter. If an interrupt handler has been +//! registered, it will be called when the SysTick counter rolls over. +//! +//! \note Calling this function will cause the SysTick counter to (re)commence +//! counting from its current value. The counter is not automatically reloaded +//! with the period as specified in a previous call to \ref SysTickPeriodSet(). If +//! an immediate reload is required, the NVIC_ST_CURRENT register must be +//! written to force this. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the supplied period on the next +//! clock. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickEnable(void) +{ + // Enable SysTick. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; +} + +//***************************************************************************** +// +//! \brief Disables the SysTick counter. +//! +//! This will stop the SysTick counter. If an interrupt handler has been +//! registered, it will no longer be called until SysTick is restarted. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickDisable(void) +{ + // Disable SysTick. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the SysTick interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler, returning an error if an error occurs. + IntRegister(INT_SYSTICK, pfnHandler); + + // Enable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! \brief Unregisters the interrupt handler for the SysTick interrupt in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntUnregister(void) +{ + // Disable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + + // Unregister the interrupt handler. + IntUnregister(INT_SYSTICK); +} + +//***************************************************************************** +// +//! \brief Enables the SysTick interrupt. +//! +//! This function will enable the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \note The SysTick interrupt handler does not need to clear the SysTick +//! interrupt source as this is done automatically by NVIC when the interrupt +//! handler is called. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntEnable(void) +{ + // Enable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! \brief Disables the SysTick interrupt. +//! +//! This function will disable the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntDisable(void) +{ + // Disable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); +} + +//***************************************************************************** +// +//! \brief Sets the period of the SysTick counter. +//! +//! This function sets the rate at which the SysTick counter wraps; this +//! equals to the number of processor clocks between interrupts. +//! +//! \note Calling this function does not cause the SysTick counter to reload +//! immediately. If an immediate reload is required, the NVIC_ST_CURRENT +//! register must be written. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the \c ui32Period supplied here +//! on the next clock after the SysTick is enabled. +//! +//! \param ui32Period is the number of clock ticks in each period of the +//! SysTick counter; must be between 1 and 16,777,216 (0x1000000), both included. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickPeriodSet(uint32_t ui32Period) +{ + // Check the arguments. + ASSERT((ui32Period > 0) && (ui32Period <= 16777216)); + + // Set the period of the SysTick counter. + HWREG(NVIC_ST_RELOAD) = ui32Period - 1; +} + +//***************************************************************************** +// +//! \brief Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps; this +//! equals to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SysTickPeriodGet(void) +{ + // Return the period of the SysTick counter. + return(HWREG(NVIC_ST_RELOAD) + 1); +} + +//***************************************************************************** +// +//! \brief Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter; this will +//! be a value between the (period - 1) and zero, both included. +//! +//! \return Returns the current value of the SysTick counter +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SysTickValueGet(void) +{ + // Return the current value of the SysTick counter. + return(HWREG(NVIC_ST_CURRENT)); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ + +//***************************************************************************** +// +//! Close the Doxygen group +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick_doc.h new file mode 100644 index 0000000..70848fc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick_doc.h @@ -0,0 +1,68 @@ +/****************************************************************************** +* Filename: systick_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup systick_api +//! @{ +//! \section sec_systick Introduction +//! +//! The system CPU includes a system timer, SysTick, integrated in the NVIC which provides a simple, 24-bit, +//! clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. +//! When enabled, the timer counts down on each clock from the reload value to 0, reloads (wraps) on +//! the next clock edge, then decrements on subsequent clocks. +//! +//! The SysTick counter runs on the system clock. If this clock signal is stopped for low-power mode, the +//! SysTick counter stops. +//! +//! When the processor is halted for debugging, the counter does not decrement. +//! +//! \section sec_systick_api API +//! +//! The API functions can be grouped like this: +//! +//! Configuration and status: +//! - \ref SysTickPeriodSet() +//! - \ref SysTickPeriodGet() +//! - \ref SysTickValueGet() +//! +//! Enable and disable: +//! - \ref SysTickEnable() +//! - \ref SysTickDisable() +//! +//! Interrupt configuration: +//! - \ref SysTickIntRegister() +//! - \ref SysTickIntUnregister() +//! - \ref SysTickIntEnable() +//! - \ref SysTickIntDisable() +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer.c new file mode 100644 index 0000000..86c484f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer.c @@ -0,0 +1,392 @@ +/****************************************************************************** +* Filename: timer.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the General Purpose Timer +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "timer.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef TimerConfigure + #define TimerConfigure NOROM_TimerConfigure + #undef TimerLevelControl + #define TimerLevelControl NOROM_TimerLevelControl + #undef TimerStallControl + #define TimerStallControl NOROM_TimerStallControl + #undef TimerWaitOnTriggerControl + #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl + #undef TimerIntRegister + #define TimerIntRegister NOROM_TimerIntRegister + #undef TimerIntUnregister + #define TimerIntUnregister NOROM_TimerIntUnregister + #undef TimerMatchUpdateMode + #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode + #undef TimerIntervalLoadMode + #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode +#endif + +//***************************************************************************** +// +//! \brief Gets the timer interrupt number. +//! +//! Given a timer base address, this function returns the corresponding +//! interrupt number. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return Returns a timer interrupt number, or -1 if \c ui32Base is invalid. +// +//***************************************************************************** +static uint32_t +TimerIntNumberGet(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // Loop through the table that maps timer base addresses to interrupt + // numbers. + switch(ui32Base) + { + case GPT0_BASE : + ui32Int = INT_GPT0A; + break; + case GPT1_BASE : + ui32Int = INT_GPT1A; + break; + case GPT2_BASE : + ui32Int = INT_GPT2A; + break; + case GPT3_BASE : + ui32Int = INT_GPT3A; + break; + default : + ui32Int = 0x0; + } + + // Return the interrupt number or (-1) if not base address is not matched. + return (ui32Int); +} + +//***************************************************************************** +// +// Configures the timer(s) +// +//***************************************************************************** +void +TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || + (ui32Config == TIMER_CFG_ONE_SHOT_UP) || + (ui32Config == TIMER_CFG_PERIODIC) || + (ui32Config == TIMER_CFG_PERIODIC_UP) || + ((ui32Config & 0xFF000000) == TIMER_CFG_SPLIT_PAIR)); + ASSERT(((ui32Config & 0xFF000000) != TIMER_CFG_SPLIT_PAIR) || + ((((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PWM)) && + (((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PWM)))); + + // Disable the timers. + HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); + + // Set the global timer configuration. + HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24; + + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE; + HWREG(ui32Base + GPT_O_TBMR) = + ((ui32Config >> 8) & 0xFF) | GPT_TBMR_TBPWMIE; +} + +//***************************************************************************** +// +// Controls the output level +// +//***************************************************************************** +void +TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the output levels as requested. + ui32Timer &= GPT_CTL_TAPWML | GPT_CTL_TBPWML; + HWREG(ui32Base + GPT_O_CTL) = (bInvert ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & + ~(ui32Timer))); +} + +//***************************************************************************** +// +// Controls the stall handling +// +//***************************************************************************** +void +TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the stall mode. + ui32Timer &= GPT_CTL_TASTALL | GPT_CTL_TBSTALL; + HWREG(ui32Base + GPT_O_CTL) = (bStall ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer))); +} + +//***************************************************************************** +// +// Controls the wait on trigger handling +// +//***************************************************************************** +void +TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the wait on trigger mode for timer A. + if(ui32Timer & TIMER_A) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAWOT; + } + else + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAWOT); + } + } + + // Set the wait on trigger mode for timer B. + if(ui32Timer & TIMER_B) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBWOT; + } + else + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBWOT); + } + } +} + +//***************************************************************************** +// +// Registers an interrupt handler for the timer interrupt +// +//***************************************************************************** +void +TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Get the interrupt number for this timer module. + ui32Int = TimerIntNumberGet(ui32Base); + + // Register an interrupt handler for timer A if requested. + if(ui32Timer & TIMER_A) + { + // Register the interrupt handler. + IntRegister(ui32Int, pfnHandler); + + // Enable the interrupt. + IntEnable(ui32Int); + } + + // Register an interrupt handler for timer B if requested. + if(ui32Timer & TIMER_B) + { + // Register the interrupt handler. + IntRegister(ui32Int + 1, pfnHandler); + + // Enable the interrupt. + IntEnable(ui32Int + 1); + } +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for the timer interrupt +// +//***************************************************************************** +void +TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Get the interrupt number for this timer module. + ui32Int = TimerIntNumberGet(ui32Base); + + // Unregister the interrupt handler for timer A if requested. + if(ui32Timer & TIMER_A) + { + // Disable the interrupt. + IntDisable(ui32Int); + + // Unregister the interrupt handler. + IntUnregister(ui32Int); + } + + // Unregister the interrupt handler for timer B if requested. + if(ui32Timer & TIMER_B) + { + // Disable the interrupt. + IntDisable(ui32Int + 1); + + // Unregister the interrupt handler. + IntUnregister(ui32Int + 1); + } +} + +//***************************************************************************** +// +// Sets the Match Register Update mode +// +//***************************************************************************** +void +TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); + ASSERT((ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) || (ui32Mode == TIMER_MATCHUPDATE_TIMEOUT)); + + // Set mode for timer A + if(ui32Timer & TIMER_A) + { + if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAMRSU); + } + else + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAMRSU; + } + } + + // Set mode for timer B + if(ui32Timer & TIMER_B) + { + if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBMRSU); + } + else + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBMRSU; + } + } +} + +//***************************************************************************** +// +// Sets the Interval Load mode +// +//***************************************************************************** +void +TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); + ASSERT((ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) || (ui32Mode == TIMER_INTERVALLOAD_TIMEOUT)); + + // Set mode for timer A + if(ui32Timer & TIMER_A) + { + if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAILD); + } + else + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAILD; + } + } + + // Set mode for timer B + if(ui32Timer & TIMER_B) + { + if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBILD); + } + else + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBILD; + } + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer.h new file mode 100644 index 0000000..da13074 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer.h @@ -0,0 +1,1176 @@ +/****************************************************************************** +* Filename: timer.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//**************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup timer_api +//! @{ +// +//**************************************************************************** + +#ifndef __GPT_H__ +#define __GPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_gpt.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define TimerConfigure NOROM_TimerConfigure + #define TimerLevelControl NOROM_TimerLevelControl + #define TimerStallControl NOROM_TimerStallControl + #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl + #define TimerIntRegister NOROM_TimerIntRegister + #define TimerIntUnregister NOROM_TimerIntUnregister + #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode + #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ui32Config parameter. +// +//***************************************************************************** +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ui32IntFlags parameter, and returned from +// TimerIntStatus. +// +//***************************************************************************** +#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ui32Event parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ui32Timer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000FF // Timer A +#define TIMER_B 0x0000FF00 // Timer B +#define TIMER_BOTH 0x0000FFFF // Timer Both + +//***************************************************************************** +// +// Values that can be passed to GPTSynchronize as the ui32Timers parameter +// +//***************************************************************************** +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B + +//***************************************************************************** +// +// Values that can be passed to TimerMatchUpdateMode +// +//***************************************************************************** +#define TIMER_MATCHUPDATE_NEXTCYCLE 0x00000000 // Apply match register on next cycle +#define TIMER_MATCHUPDATE_TIMEOUT 0x00000001 // Apply match register on next timeout + +//***************************************************************************** +// +// Values that can be passed to TimerIntervalLoad +// +//***************************************************************************** +#define TIMER_INTERVALLOAD_NEXTCYCLE 0x00000000 // Load TxR register with the value in the TxILR register on the next clock cycle +#define TIMER_INTERVALLOAD_TIMEOUT 0x00000001 // Load TxR register with the value in the TxILR register on next timeout + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks a timer base address. +//! +//! This function determines if a timer module base address is valid. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +TimerBaseValid(uint32_t ui32Base) +{ + return((ui32Base == GPT0_BASE) || (ui32Base == GPT1_BASE) || + (ui32Base == GPT2_BASE) || (ui32Base == GPT3_BASE)); +} +#endif + +//***************************************************************************** +// +//! \brief Enables the timer(s). +//! +//! This function enables operation of the timer module. The timer must be +//! configured before it is enabled. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to enable. Must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerEnable(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Enable the timer(s) module. + HWREG(ui32Base + GPT_O_CTL) |= ui32Timer & (GPT_CTL_TAEN | GPT_CTL_TBEN); +} + +//***************************************************************************** +// +//! \brief Disables the timer(s). +//! +//! This function disables operation of the timer module. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to disable. Must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerDisable(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Disable the timer module. + HWREG(ui32Base + GPT_O_CTL) &= ~(ui32Timer & + (GPT_CTL_TAEN | GPT_CTL_TBEN)); +} + +//***************************************************************************** +// +//! \brief Configures the timer(s). +//! +//! This function configures the operating mode of the timer(s). The timer +//! module is disabled before being configured and is left in the disabled +//! state. +//! +//! The timers are comprised of two 16-bit timers that can +//! operate independently or be concatenated to form a 32-bit timer. +//! +//! \note If the timers are used independently the length of timer can be +//! extended to 24 bit by use of an 8 bit prescale register set using +//! \ref TimerPrescaleSet(). +//! +//! When configuring for full-width timer \c ui32Config is set +//! as one of the following values: +//! - \ref TIMER_CFG_ONE_SHOT : Full-width one-shot timer. +//! - \ref TIMER_CFG_ONE_SHOT_UP : Full-width one-shot timer that counts up +//! instead of down. +//! - \ref TIMER_CFG_PERIODIC : Full-width periodic timer. +//! - \ref TIMER_CFG_PERIODIC_UP : Full-width periodic timer that counts up +//! instead of down. +//! +//! When configuring for a pair of half-width timers, each timer is separately +//! configured. The timers are configured by setting \c ui32Config to +//! the bitwise OR of one of each of the following three: +//! - Use half-width timers: +//! - \ref TIMER_CFG_SPLIT_PAIR +//! - Timer A: +//! - \ref TIMER_CFG_A_ONE_SHOT : Half-width one-shot timer +//! - \ref TIMER_CFG_A_ONE_SHOT_UP : Half-width one-shot timer that counts up +//! instead of down. +//! - \ref TIMER_CFG_A_PERIODIC : Half-width periodic timer +//! - \ref TIMER_CFG_A_PERIODIC_UP : Half-width periodic timer that counts up +//! instead of down. +//! - \ref TIMER_CFG_A_CAP_COUNT : Half-width edge count capture +//! - \ref TIMER_CFG_A_CAP_COUNT_UP : Half-width edge count capture that counts +//! up instead of down. +//! - \ref TIMER_CFG_A_CAP_TIME : Half-width edge time capture +//! - \ref TIMER_CFG_A_CAP_TIME_UP : Half-width edge time capture that counts up +//! instead of down. +//! - \ref TIMER_CFG_A_PWM : Half-width PWM output +//! - Timer B: +//! - Same as Timer A but using TIMER_CFG_B_* instead. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Config is the configuration for the timer. +//! +//! \return None +// +//***************************************************************************** +extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config); + +//***************************************************************************** +// +//! \brief Controls the output level. +//! +//! This function configures the PWM output level for the specified timer. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust. Must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param bInvert specifies the output level. +//! - \c true : Timer's output is active low. +//! - \c false : Timer's output is active high. +//! +//! \return None +// +//***************************************************************************** +extern void TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, + bool bInvert); + +//***************************************************************************** +// +//! \brief Controls the event type. +//! +//! This function configures the signal edge(s) that triggers the timer when +//! in capture mode. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Event specifies the type of event; must be one of: +//! - \ref TIMER_EVENT_POS_EDGE +//! - \ref TIMER_EVENT_NEG_EDGE +//! - \ref TIMER_EVENT_BOTH_EDGES +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerEventControl(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Event) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the event type. + ui32Timer &= GPT_CTL_TAEVENT_M | GPT_CTL_TBEVENT_M; + HWREG(ui32Base + GPT_O_CTL) = ((HWREG(ui32Base + GPT_O_CTL) & ~ui32Timer) | + (ui32Event & ui32Timer)); +} + +//***************************************************************************** +// +//! \brief Controls the stall handling. +//! +//! This function controls the stall response for the specified timer. If the +//! \e bStall parameter is \b true, then the timer stops counting if the +//! processor enters debug mode; otherwise the timer keeps running while in +//! debug mode. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param bStall specifies the response to a stall signal. +//! - \c true : Timer stops counting if the processor enters debug mode. +//! - \c false : Timer keeps running if the processor enters debug mode. +//! +//! \return None +// +//***************************************************************************** +extern void TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, + bool bStall); + +//***************************************************************************** +// +//! \brief Controls the wait on trigger handling. +//! +//! This function controls whether or not a timer waits for a trigger input to +//! start counting. When enabled, the previous timer in the trigger chain must +//! count to its timeout in order for this timer to start counting. Refer to +//! the part's data sheet for a description of the trigger chain. +//! +//! \note This function should not be used for Timer 0A or Wide Timer 0A. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param bWait specifies if the timer should wait for a trigger input. +//! - \c true : Wait for trigger. +//! - \c false : Do not wait for trigger. +//! +//! \return None +// +//***************************************************************************** +extern void TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, + bool bWait); + +//***************************************************************************** +// +//! \brief Set the timer prescale value. +//! +//! This function configures the value of the timer clock prescaler. The +//! prescaler is only operational when in half-width mode and is used to extend +//! the range of the half-width timer modes. +//! +//! When in one-shot or periodic down count modes, \b ui32Value defines the +//! prescaler for the timer counter. When acting as a true prescaler, the +//! prescaler counts down to 0 before the value in timer registers are incremented. +//! +//! In all other individual/split modes, \b ui32Value is a linear extension of +//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes +//! of the 16/32-bit timer. +//! +//! \note Because the prescaler counts down to 0 the timer division ratio equals +//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the timer prescale value which must be between 0 and 255 +//! (both included). +//! - 0 : Timer division ratio = 1 (disable prescaling). +//! - 1 : Timer division ratio = 2. +//! - ... +//! - 255 : Timer division ratio = 256. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + ASSERT(ui32Value < 256); + + // Set the timer A prescaler if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAPR) = ui32Value; + } + + // Set the timer B prescaler if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBPR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Get the timer prescale value. +//! +//! This function gets the value of the timer clock prescaler. The +//! prescaler is only operational when in half-width mode and is used to extend +//! the range of the half-width timer modes. +//! +//! When in one-shot or periodic down count modes, \b ui32Value defines the +//! prescaler for the timer counter. When acting as a true prescaler, the +//! prescaler counts down to 0 before the value in timer registers are incremented. +//! +//! In all other individual/split modes, \b ui32Value is a linear extension of +//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes +//! of the 16/32-bit timer. +//! +//! \note Because the prescaler counts down to 0 the timer division ratio equals +//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the value of the timer prescaler. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Return the appropriate prescale value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPR) : + HWREG(ui32Base + GPT_O_TBPR)); +} + +//***************************************************************************** +// +//! \brief Set the timer prescale match value. +//! +//! This function configures the value of the input clock prescaler match +//! value. When in a half-width mode that uses the counter match and the +//! prescaler, the prescale match effectively extends the range of the match. +//! The prescaler provides the least significant bits when counting down in +//! periodic and one-shot modes; in all other modes, the prescaler provides the +//! most significant bits. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the timer prescale match value which must be between 0 +//! and 255 (both included). +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + ASSERT(ui32Value < 256); + + // Set the timer A prescale match if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAPMR) = ui32Value; + } + + // Set the timer B prescale match if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBPMR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Get the timer prescale match value. +//! +//! This function gets the value of the input clock prescaler match value. +//! When in a half-width mode that uses the counter match and prescaler, the +//! prescale match effectively extends the range of the match. The prescaler +//! provides the least significant bits when counting down in periodic and +//! one-shot modes; in all other modes, the prescaler provides the most +//! significant bits. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the value of the timer prescale match. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate prescale match value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPMR) : + HWREG(ui32Base + GPT_O_TBPMR)); +} + +//***************************************************************************** +// +//! \brief Sets the timer load value. +//! +//! This function configures the timer load value; if the timer is running then +//! the value is immediately loaded into the timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the load value. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the timer A load value if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAILR) = ui32Value; + } + + // Set the timer B load value if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBILR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Gets the timer load value. +//! +//! This function gets the currently programmed interval load value for the +//! specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the load value for the timer +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate load value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAILR) : + HWREG(ui32Base + GPT_O_TBILR)); +} + +//***************************************************************************** +// +//! \brief Gets the current timer value. +//! +//! This function reads the current value of the specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate timer value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAR) : + HWREG(ui32Base + GPT_O_TBR)); +} + +//***************************************************************************** +// +//! \brief Sets the timer match value. +//! +//! This function configures the match value for a timer. This value is used +//! in capture count mode to determine when to interrupt the processor and in +//! PWM mode to determine the duty cycle of the output signal. Match interrupts +//! can also be generated in periodic and one-shot modes when the value of the +//! counter matches this register. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the match value. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the timer A match value if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAMATCHR) = ui32Value; + } + + // Set the timer B match value if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBMATCHR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Gets the timer match value. +//! +//! This function gets the match value for the specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return Returns the match value for the timer +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate match value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAMATCHR) : + HWREG(ui32Base + GPT_O_TBMATCHR)); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the timer interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific timer interrupts must be enabled via \ref TimerIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! \ref TimerIntClear(). +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s); must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param pfnHandler is a pointer to the function to be called when the timer +//! interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, + void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the timer interrupt in the dynamic interrupt table. +//! +//! This function unregisters the handler to be called when a timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s); must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer); + +//***************************************************************************** +// +//! \brief Enables individual timer interrupt sources. +//! +//! This function enables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter must be the bitwise OR of any combination of +//! the following: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(ui32Base + GPT_O_IMR) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual timer interrupt sources. +//! +//! This function disables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter must be the bitwise OR of any combination of +//! the following: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(ui32Base + GPT_O_IMR) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the timer module. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the timer module. +//! \param bMasked selects either raw or masked interrupt status: +//! - \c true : Masked interrupt. +//! - \c false : Raw interrupt. +//! +//! \return The current interrupt status, enumerated as a bit field of values: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + return(bMasked ? HWREG(ui32Base + GPT_O_MIS) : + HWREG(ui32Base + GPT_O_RIS)); +} + +//***************************************************************************** +// +//! \brief Clears timer interrupt sources. +//! +//! The specified timer interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter must be the bitwise OR of any combination of +//! the following: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Clear the requested interrupt sources. + HWREG(ui32Base + GPT_O_ICLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Synchronizes the counters in a set of timers. +//! +//! This function synchronizes the counters in a specified set of timers. +//! When a timer is running in half-width mode, each half can be included or +//! excluded in the synchronization event. When a timer is running in +//! full-width mode, only the A timer can be synchronized (specifying the B +//! timer has no effect). +//! +//! \param ui32Base is the base address of the timer module. This parameter must +//! be the base address of Timer0 (in other words, \b GPT0_BASE). +//! \param ui32Timers is the set of timers to synchronize. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TIMER_0A_SYNC +//! - \ref TIMER_0B_SYNC +//! - \ref TIMER_1A_SYNC +//! - \ref TIMER_1B_SYNC +//! - \ref TIMER_2A_SYNC +//! - \ref TIMER_2B_SYNC +//! - \ref TIMER_3A_SYNC +//! - \ref TIMER_3B_SYNC +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers) +{ + // Check the arguments. + ASSERT(ui32Base == GPT0_BASE); + + // Synchronize the specified timers. + HWREG(ui32Base + GPT_O_SYNC) = ui32Timers; +} + +//***************************************************************************** +// +//! \brief Enables AND'ing of the CCP outputs from Timer A and Timer B. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerCcpCombineEnable(uint32_t ui32Base) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + + // Set the bit + HWREG(ui32Base + GPT_O_ANDCCP) |= GPT_ANDCCP_CCP_AND_EN; +} + +//***************************************************************************** +// +//! \brief Disables AND'ing of the CCP outputs from Timer A and Timer B. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerCcpCombineDisable(uint32_t ui32Base) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + + // Clear the bit + HWREG(ui32Base + GPT_O_ANDCCP) &= ~(GPT_ANDCCP_CCP_AND_EN); +} + +//***************************************************************************** +// +//! \brief Sets the Match Register Update mode. +//! +//! This function controls when the Match Register value and Prescale Register value +//! are applied after writing these registers while a timer is enabled. +//! +//! \note If the timer is disabled when setting the update mode the Match Register +//! and Prescale Register values are applied immediately when enabling the timer. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to configure; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Mode sets the mode: +//! - \ref TIMER_MATCHUPDATE_NEXTCYCLE : Apply Match Register and Prescale Register on next clock +//! cycle after writing any of these registers. +//! - \ref TIMER_MATCHUPDATE_TIMEOUT : Apply Match Register and Prescale Register on next timeout +//! after writing any of these registers. +//! +//! \return None +// +//***************************************************************************** +extern void TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode); + +//***************************************************************************** +// +//! \brief Sets the Interval Load mode. +//! +//! This function controls when the Timer Register and Prescale Snap-shot (if used) +//! are updated. +//! +//! Timer Register (TAR/TBR) is updated when Interval Load Register (TAILR/TBILR) is written +//! and the Prescale Snap-shot (TAPS/TBPS) is updated when Prescale Register (TAPR/TBPR) is +//! written depending on the mode of operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to configure; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Mode sets the mode: +//! - \ref TIMER_INTERVALLOAD_NEXTCYCLE : Update Timer Register and Prescale Snap-shot on next clock +//! cycle after writing Interval Load Register or Prescale Register, respectively. +//! - \ref TIMER_INTERVALLOAD_TIMEOUT : Update Timer Register and Prescale Snap-shot on next timeout +//! after writing Interval Load Register or Prescale Register, respectively. +//! +//! \return None +// +//***************************************************************************** +extern void TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_TimerConfigure + #undef TimerConfigure + #define TimerConfigure ROM_TimerConfigure + #endif + #ifdef ROM_TimerLevelControl + #undef TimerLevelControl + #define TimerLevelControl ROM_TimerLevelControl + #endif + #ifdef ROM_TimerStallControl + #undef TimerStallControl + #define TimerStallControl ROM_TimerStallControl + #endif + #ifdef ROM_TimerWaitOnTriggerControl + #undef TimerWaitOnTriggerControl + #define TimerWaitOnTriggerControl ROM_TimerWaitOnTriggerControl + #endif + #ifdef ROM_TimerIntRegister + #undef TimerIntRegister + #define TimerIntRegister ROM_TimerIntRegister + #endif + #ifdef ROM_TimerIntUnregister + #undef TimerIntUnregister + #define TimerIntUnregister ROM_TimerIntUnregister + #endif + #ifdef ROM_TimerMatchUpdateMode + #undef TimerMatchUpdateMode + #define TimerMatchUpdateMode ROM_TimerMatchUpdateMode + #endif + #ifdef ROM_TimerIntervalLoadMode + #undef TimerIntervalLoadMode + #define TimerIntervalLoadMode ROM_TimerIntervalLoadMode + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer_doc.h new file mode 100644 index 0000000..d15c086 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer_doc.h @@ -0,0 +1,121 @@ +/****************************************************************************** +* Filename: timer_doc.h +* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) +* Revision: 45971 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup timer_api +//! @{ +//! \section sec_timer Introduction +//! +//! The timer API provides a set of functions for using the general-purpose timer module. +//! +//! The timer module contains four timer blocks with the following functional options: +//! - Operating modes: +//! - 16-bit with 8-bit prescaler or 32-bit programmable one-shot timer. +//! - 16-bit with 8-bit prescaler or 32-bit programmable periodic timer. +//! - Two capture compare PWM pins (CCP) for each 32-bit timer. +//! - 24-bit input-edge count or 24-bit time-capture modes. +//! - 24-bit PWM mode with software-programmable output inversion of the PWM signal. +//! - Count up or down. +//! - Daisy chaining of timer modules allows a single timer to initiate multiple timing events. +//! - Timer synchronization allows selected timers to start counting on the same clock cycle. +//! - User-enabled stalling when the System CPU asserts a CPU Halt flag during debug. +//! - Ability to determine the elapsed time between the assertion of the timer interrupt and +//! entry into the interrupt service routine. +//! +//! Each timer block provides two half-width timers/counters that can be configured +//! to operate independently as timers or event counters or to operate as a combined +//! full-width timer. +//! The timers provide 16-bit half-width timers and a 32-bit full-width timer. +//! For the purposes of this API, the two +//! half-width timers provided by a timer block are referred to as TimerA and +//! TimerB, and the full-width timer is referred to as TimerA. +//! +//! When in half-width mode, the timer can also be configured for event capture or +//! as a pulse width modulation (PWM) generator. When configured for event +//! capture, the timer acts as a counter. It can be configured to count either the +//! time between events or the events themselves. The type of event +//! being counted can be configured as a positive edge, a negative edge, or both +//! edges. When a timer is configured as a PWM generator, the input signal used to +//! capture events becomes an output signal, and the timer drives an +//! edge-aligned pulse onto that signal. +//! +//! Control is also provided over interrupt sources and events. Interrupts can be +//! generated to indicate that an event has been captured, or that a certain number +//! of events have been captured. Interrupts can also be generated when the timer +//! has counted down to 0 or when the timer matches a certain value. +//! +//! Timer configuration is handled by \ref TimerConfigure(), which performs the high +//! level setup of the timer module; that is, it is used to set up full- or +//! half-width modes, and to select between PWM, capture, and timer operations. +//! +//! \section sec_timer_api API +//! +//! The API functions can be grouped like this: +//! +//! Functions to perform timer control: +//! - \ref TimerConfigure() +//! - \ref TimerEnable() +//! - \ref TimerDisable() +//! - \ref TimerLevelControl() +//! - \ref TimerWaitOnTriggerControl() +//! - \ref TimerEventControl() +//! - \ref TimerStallControl() +//! - \ref TimerIntervalLoadMode() +//! - \ref TimerMatchUpdateMode() +//! - \ref TimerCcpCombineDisable() +//! - \ref TimerCcpCombineEnable() +//! +//! Functions to manage timer content: +//! - \ref TimerLoadSet() +//! - \ref TimerLoadGet() +//! - \ref TimerPrescaleSet() +//! - \ref TimerPrescaleGet() +//! - \ref TimerMatchSet() +//! - \ref TimerMatchGet() +//! - \ref TimerPrescaleMatchSet() +//! - \ref TimerPrescaleMatchGet() +//! - \ref TimerValueGet() +//! - \ref TimerSynchronize() +//! +//! Functions to manage the interrupt handler for the timer interrupt: +//! - \ref TimerIntRegister() +//! - \ref TimerIntUnregister() +//! +//! The individual interrupt sources within the timer module are managed with: +//! - \ref TimerIntEnable() +//! - \ref TimerIntDisable() +//! - \ref TimerIntStatus() +//! - \ref TimerIntClear() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/trng.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/trng.c new file mode 100644 index 0000000..7c1c4e1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/trng.c @@ -0,0 +1,112 @@ +/****************************************************************************** +* Filename: trng.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the TRNG module +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "trng.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef TRNGConfigure + #define TRNGConfigure NOROM_TRNGConfigure + #undef TRNGNumberGet + #define TRNGNumberGet NOROM_TRNGNumberGet +#endif + +//***************************************************************************** +// +// Configure the true random number generator +// +//***************************************************************************** +void +TRNGConfigure(uint32_t ui32MinSamplesPerCycle, + uint32_t ui32MaxSamplesPerCycle, + uint32_t ui32ClocksPerSample) +{ + uint32_t ui32Val; + + // Make sure the TRNG is disabled. + ui32Val = HWREG(TRNG_BASE + TRNG_O_CTL) & ~TRNG_CTL_TRNG_EN; + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // Configure the startup number of samples. + ui32Val &= ~TRNG_CTL_STARTUP_CYCLES_M; + ui32Val |= ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CTL_STARTUP_CYCLES_S ) & TRNG_CTL_STARTUP_CYCLES_M ); + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // Configure the minimum and maximum number of samples pr generated number + // and the number of clocks per sample. + HWREG(TRNG_BASE + TRNG_O_CFG0) = ( + ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CFG0_MAX_REFILL_CYCLES_S ) & TRNG_CFG0_MAX_REFILL_CYCLES_M ) | + ((( ui32ClocksPerSample ) << TRNG_CFG0_SMPL_DIV_S ) & TRNG_CFG0_SMPL_DIV_M ) | + ((( ui32MinSamplesPerCycle >> 6 ) << TRNG_CFG0_MIN_REFILL_CYCLES_S ) & TRNG_CFG0_MIN_REFILL_CYCLES_M ) ); +} + +//***************************************************************************** +// +// Get a random number from the generator +// +//***************************************************************************** +uint32_t +TRNGNumberGet(uint32_t ui32Word) +{ + uint32_t ui32RandomNumber; + + // Check the arguments. + ASSERT((ui32Word == TRNG_HI_WORD) || + (ui32Word == TRNG_LOW_WORD)); + + // Return the right requested part of the generated number. + if(ui32Word == TRNG_HI_WORD) + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT1); + } + else + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT0); + } + + // Initiate generation of new number. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1; + + // Return the random number. + return ui32RandomNumber; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/trng.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/trng.h new file mode 100644 index 0000000..08a485b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/trng.h @@ -0,0 +1,451 @@ +/****************************************************************************** +* Filename: trng.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and prototypes for the true random number gen. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup trng_api +//! @{ +// +//***************************************************************************** + +#ifndef __TRNG_H__ +#define __TRNG_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_trng.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define TRNGConfigure NOROM_TRNGConfigure + #define TRNGNumberGet NOROM_TRNGNumberGet +#endif + +//***************************************************************************** +// +// +// +//***************************************************************************** +#define TRNG_NUMBER_READY 0x00000001 // +#define TRNG_FRO_SHUTDOWN 0x00000002 // +#define TRNG_NEED_CLOCK 0x80000000 // + +#define TRNG_HI_WORD 0x00000001 +#define TRNG_LOW_WORD 0x00000002 + +//***************************************************************************** +// +// API Function and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure the true random number generator. +//! +//! Use this function to set the minimum and maximum number of samples required +//! in each generation of a new random number. +//! +//! \param ui32MinSamplesPerCycle is the minimum number of samples per each +//! generated random number. Constraints: +//! - Value must be bigger than or equal to 2^6 and less than 2^14. +//! - The 6 LSBs of the argument are truncated. +//! - If the value is zero, the number of samples is fixed to the value determined +//! by ui32MaxSamplesPerCycle. To ensure same entropy in all generated random +//! numbers the value 0 should be used. +//! \param ui32MaxSamplesPerCycle is the maximum number of samples per each +//! generated random number. Constraints: +//! - Value must be between 2^8 and 2^24 (both included). +//! - The 8 LSBs of the argument are truncated. +//! - Value 0 and 2^24 both give the highest possible value. +//! \param ui32ClocksPerSample is the number of clock cycles for each time +//! a new sample is generated from the FROs. +//! - 0 : Every sample. +//! - 1 : Every second sample. +//! - ... +//! - 15 : Every 16. sample. +//! +//! \return None +// +//***************************************************************************** +extern void TRNGConfigure(uint32_t ui32MinSamplesPerCycle, + uint32_t ui32MaxSamplesPerCycle, + uint32_t ui32ClocksPerSample); + +//***************************************************************************** +// +//! \brief Enable the TRNG. +//! +//! Enable the TRNG to start preparing a random number. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGEnable(void) +{ + // Enable the TRNG. + HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disable the TRNG module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGDisable(void) +{ + // Enable the TRNG + HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Get a random number from the generator. +//! +//! Use this function to get either the high or low part of the 64 bit +//! generated number. +//! +//! \note Data from this register is only valid if the TRNG has produced a +//! number. Use \ref TRNGStatusGet() to poll the for status. After calling this +//! function a new random number will be generated. +//! +//! \param ui32Word determines if whether to return the high or low 32 bits. +//! - \ref TRNG_HI_WORD +//! - \ref TRNG_LOW_WORD +//! +//! \return Return either the high or low part of the 64 bit generated random +//! number. +// +//***************************************************************************** +extern uint32_t TRNGNumberGet(uint32_t ui32Word); + +//***************************************************************************** +// +//! \brief Get the status of the TRNG. +//! +//! Use this function to retrieve the status of the TRNG. +//! +//! \return Returns the current status of the TRNG module. +//! The returned status is a bitwise OR'ed combination of: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! - \ref TRNG_NEED_CLOCK +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TRNGStatusGet(void) +{ + // Return the status. + return (HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); +} + +//***************************************************************************** +// +//! \brief Reset the TRNG. +//! +//! Use this function to reset the TRNG module. Reset will be low for +//! approximately 5 clock cycles. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGReset(void) +{ + // Reset the TRNG. + HWREG(TRNG_BASE + TRNG_O_SWRESET) = 1; +} + +//***************************************************************************** +// +//! \brief Enables individual TRNG interrupt sources. +//! +//! This function enables the indicated TRNG interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntEnable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || + (ui32IntFlags & TRNG_FRO_SHUTDOWN)); + + // Enable the specified interrupts. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual TRNG interrupt sources. +//! +//! This function disables the indicated TRNG interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntDisable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || + (ui32IntFlags & TRNG_FRO_SHUTDOWN)); + + // Disable the specified interrupts. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status of the TRNG module. +//! +//! This function returns the interrupt status for the specified TRNG. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param bMasked selects either raw or masked interrupt status. +//! - \c true : Masked interrupt. +//! - \c false : Raw interrupt. +//! +//! \return Returns the current interrupt status, enumerated as: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TRNGIntStatus(bool bMasked) +{ + uint32_t ui32Mask; + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + ui32Mask = HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK); + return(ui32Mask & HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); + } + else + { + return(HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT) & 0x00000003); + } +} + +//***************************************************************************** +// +//! \brief Clears TRNG interrupt sources. +//! +//! The specified TRNG interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntClear(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || + (ui32IntFlags & TRNG_FRO_SHUTDOWN)); + + // Clear the requested interrupt sources. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for a TRNG interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific TRNG interrupts must be enabled via \ref TRNGIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! TRNG interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_TRNG_IRQ, pfnHandler); + + // Enable the TRNG interrupt. + IntEnable(INT_TRNG_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a TRNG interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a Crypto interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntUnregister(void) +{ + // Disable the interrupt. + IntDisable(INT_TRNG_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_TRNG_IRQ); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_TRNGConfigure + #undef TRNGConfigure + #define TRNGConfigure ROM_TRNGConfigure + #endif + #ifdef ROM_TRNGNumberGet + #undef TRNGNumberGet + #define TRNGNumberGet ROM_TRNGNumberGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __TRNG_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart.c new file mode 100644 index 0000000..589e928 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart.c @@ -0,0 +1,296 @@ +/****************************************************************************** +* Filename: uart.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the UART. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "uart.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef UARTFIFOLevelGet + #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet + #undef UARTConfigSetExpClk + #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk + #undef UARTConfigGetExpClk + #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk + #undef UARTDisable + #define UARTDisable NOROM_UARTDisable + #undef UARTCharGetNonBlocking + #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking + #undef UARTCharGet + #define UARTCharGet NOROM_UARTCharGet + #undef UARTCharPutNonBlocking + #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking + #undef UARTCharPut + #define UARTCharPut NOROM_UARTCharPut + #undef UARTIntRegister + #define UARTIntRegister NOROM_UARTIntRegister + #undef UARTIntUnregister + #define UARTIntUnregister NOROM_UARTIntUnregister +#endif + +//***************************************************************************** +// +// Gets the FIFO level at which interrupts are generated +// +//***************************************************************************** +void +UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel) +{ + uint32_t ui32Temp; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Read the FIFO level register. + ui32Temp = HWREG(ui32Base + UART_O_IFLS); + + // Extract the transmit and receive FIFO levels. + *pui32TxLevel = ui32Temp & UART_IFLS_TXSEL_M; + *pui32RxLevel = ui32Temp & UART_IFLS_RXSEL_M; +} + +//***************************************************************************** +// +// Sets the configuration of a UART +// +//***************************************************************************** +void +UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config) +{ + uint32_t ui32Div; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT(ui32Baud != 0); + + // Stop the UART. + UARTDisable(ui32Base); + + // Compute the fractional baud rate divider. + ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; + + // Set the baud rate. + HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; + HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; + + // Set parity, data length, and number of stop bits. + HWREG(ui32Base + UART_O_LCRH) = ui32Config; +} + +//***************************************************************************** +// +// Gets the current configuration of a UART +// +//***************************************************************************** +void +UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config) +{ + uint32_t ui32Int, ui32Frac; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Compute the baud rate. + ui32Int = HWREG(ui32Base + UART_O_IBRD); + ui32Frac = HWREG(ui32Base + UART_O_FBRD); + *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); + + // Get the parity, data length, and number of stop bits. + *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | + UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +// Disables transmitting and receiving +// +//***************************************************************************** +void +UARTDisable(uint32_t ui32Base) +{ + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait for end of TX. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) + { + } + + // Disable the FIFO. + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); + + // Disable the UART. + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +// Receives a character from the specified port +// +//***************************************************************************** +int32_t +UARTCharGetNonBlocking(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // See if there are any characters in the receive FIFO. + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) + { + // Read and return the next character. + return(HWREG(ui32Base + UART_O_DR)); + } + else + { + // There are no characters, so return a failure. + return(-1); + } +} + +//***************************************************************************** +// +// Waits for a character from the specified port +// +//***************************************************************************** +int32_t +UARTCharGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait until a char is available. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) + { + } + + // Now get the character. + return(HWREG(ui32Base + UART_O_DR)); +} + +//***************************************************************************** +// +// Sends a character to the specified port +// +//***************************************************************************** +bool +UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // See if there is space in the transmit FIFO. + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) + { + // Write this character to the transmit FIFO. + HWREG(ui32Base + UART_O_DR) = ui8Data; + + // Success. + return(true); + } + else + { + // There is no space in the transmit FIFO, so return a failure. + return(false); + } +} + +//***************************************************************************** +// +// Waits to send a character from the specified port +// +//***************************************************************************** +void +UARTCharPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait until space is available. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) + { + } + + // Send the char. + HWREG(ui32Base + UART_O_DR) = ui8Data; +} + +//***************************************************************************** +// +// Registers an interrupt handler for a UART interrupt +// +//***************************************************************************** +void +UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Register the interrupt handler. + IntRegister(INT_UART0_COMB, pfnHandler); + + // Enable the UART interrupt. + IntEnable(INT_UART0_COMB); +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for a UART interrupt +// +//***************************************************************************** +void +UARTIntUnregister(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Disable the interrupt. + IntDisable(INT_UART0_COMB); + + // Unregister the interrupt handler. + IntUnregister(INT_UART0_COMB); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart.h new file mode 100644 index 0000000..e9e71ca --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart.h @@ -0,0 +1,1091 @@ +/****************************************************************************** +* Filename: uart.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Defines and prototypes for the UART. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_uart.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet + #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk + #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk + #define UARTDisable NOROM_UARTDisable + #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking + #define UARTCharGet NOROM_UARTCharGet + #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking + #define UARTCharPut NOROM_UARTCharPut + #define UARTIntRegister NOROM_UARTIntRegister + #define UARTIntUnregister NOROM_UARTIntUnregister +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ui32IntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE ( UART_IMSC_OEIM ) // Overrun Error Interrupt Mask +#define UART_INT_BE ( UART_IMSC_BEIM ) // Break Error Interrupt Mask +#define UART_INT_PE ( UART_IMSC_PEIM ) // Parity Error Interrupt Mask +#define UART_INT_FE ( UART_IMSC_FEIM ) // Framing Error Interrupt Mask +#define UART_INT_RT ( UART_IMSC_RTIM ) // Receive Timeout Interrupt Mask +#define UART_INT_TX ( UART_IMSC_TXIM ) // Transmit Interrupt Mask +#define UART_INT_RX ( UART_IMSC_RXIM ) // Receive Interrupt Mask +#define UART_INT_CTS ( UART_IMSC_CTSMIM ) // CTS Modem Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter +// and returned by UARTConfigGetExpClk in the pui32Config parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ui32Parity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32TxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32RxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 + +//***************************************************************************** +// +// Values returned from the UARTBusy(). +// +//***************************************************************************** +#define UART_BUSY 0x00000001 +#define UART_IDLE 0x00000000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks a UART base address. +//! +//! This function determines if a UART port base address is valid. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +UARTBaseValid(uint32_t ui32Base) +{ + return(( ui32Base == UART0_BASE ) || ( ui32Base == UART0_NONBUF_BASE )); +} +#endif + +//***************************************************************************** +// +//! \brief Sets the type of parity. +//! +//! This function sets the type of parity to use for transmitting and expect +//! when receiving. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Parity specifies the type of parity to use. The last two allow +//! direct control of the parity bit; it is always either one or zero based on +//! the mode. +//! - \ref UART_CONFIG_PAR_NONE +//! - \ref UART_CONFIG_PAR_EVEN +//! - \ref UART_CONFIG_PAR_ODD +//! - \ref UART_CONFIG_PAR_ONE +//! - \ref UART_CONFIG_PAR_ZERO +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) || + (ui32Parity == UART_CONFIG_PAR_EVEN) || + (ui32Parity == UART_CONFIG_PAR_ODD) || + (ui32Parity == UART_CONFIG_PAR_ONE) || + (ui32Parity == UART_CONFIG_PAR_ZERO)); + + // Set the parity mode. + HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & + ~(UART_LCRH_SPS | UART_LCRH_EPS | + UART_LCRH_PEN)) | ui32Parity); +} + +//***************************************************************************** +// +//! \brief Gets the type of parity currently being used. +//! +//! This function gets the type of parity used for transmitting data and +//! expected when receiving data. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns the current parity settings, specified as one of: +//! - \ref UART_CONFIG_PAR_NONE +//! - \ref UART_CONFIG_PAR_EVEN +//! - \ref UART_CONFIG_PAR_ODD +//! - \ref UART_CONFIG_PAR_ONE +//! - \ref UART_CONFIG_PAR_ZERO +// +//***************************************************************************** +__STATIC_INLINE uint32_t +UARTParityModeGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the current parity setting + return(HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +//! \brief Sets the FIFO level at which interrupts are generated. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one of: +//! - \ref UART_FIFO_TX1_8 +//! - \ref UART_FIFO_TX2_8 +//! - \ref UART_FIFO_TX4_8 +//! - \ref UART_FIFO_TX6_8 +//! - \ref UART_FIFO_TX7_8 +//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of: +//! - \ref UART_FIFO_RX1_8 +//! - \ref UART_FIFO_RX2_8 +//! - \ref UART_FIFO_RX4_8 +//! - \ref UART_FIFO_RX6_8 +//! - \ref UART_FIFO_RX7_8 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, + uint32_t ui32RxLevel) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32TxLevel == UART_FIFO_TX1_8) || + (ui32TxLevel == UART_FIFO_TX2_8) || + (ui32TxLevel == UART_FIFO_TX4_8) || + (ui32TxLevel == UART_FIFO_TX6_8) || + (ui32TxLevel == UART_FIFO_TX7_8)); + ASSERT((ui32RxLevel == UART_FIFO_RX1_8) || + (ui32RxLevel == UART_FIFO_RX2_8) || + (ui32RxLevel == UART_FIFO_RX4_8) || + (ui32RxLevel == UART_FIFO_RX6_8) || + (ui32RxLevel == UART_FIFO_RX7_8)); + + // Set the FIFO interrupt levels. + HWREG(ui32Base + UART_O_IFLS) = ui32TxLevel | ui32RxLevel; +} + +//***************************************************************************** +// +//! \brief Gets the FIFO level at which interrupts are generated. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of: +//! - \ref UART_FIFO_TX1_8 +//! - \ref UART_FIFO_TX2_8 +//! - \ref UART_FIFO_TX4_8 +//! - \ref UART_FIFO_TX6_8 +//! - \ref UART_FIFO_TX7_8 +//! \param pui32RxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of: +//! - \ref UART_FIFO_RX1_8 +//! - \ref UART_FIFO_RX2_8 +//! - \ref UART_FIFO_RX4_8 +//! - \ref UART_FIFO_RX6_8 +//! - \ref UART_FIFO_RX7_8 +//! +//! \return None +// +//***************************************************************************** +extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel); + +//***************************************************************************** +// +//! \brief Sets the configuration of a UART. +//! +//! This function configures the UART for operation in the specified data +//! format. +//! +//! \note The peripheral clock is not necessarily the same as the processor +//! clock. The frequency of the peripheral clock is set by the system control. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param ui32Baud is the desired baud rate. +//! - Minimum baud rate: ui32Baud >= ceil(ui32UARTClk / 1,048,559.875) +//! - Maximum baud rate: ui32Baud <= floor(ui32UARTClk / 15.875) +//! \param ui32Config is the data format for the port. +//! The parameter is the bitwise OR of three values: +//! - Number of data bits +//! - \ref UART_CONFIG_WLEN_8 : 8 data bits per byte. +//! - \ref UART_CONFIG_WLEN_7 : 7 data bits per byte. +//! - \ref UART_CONFIG_WLEN_6 : 6 data bits per byte. +//! - \ref UART_CONFIG_WLEN_5 : 5 data bits per byte. +//! - Number of stop bits +//! - \ref UART_CONFIG_STOP_ONE : One stop bit. +//! - \ref UART_CONFIG_STOP_TWO : Two stop bits. +//! - Parity +//! - \ref UART_CONFIG_PAR_NONE +//! - \ref UART_CONFIG_PAR_EVEN +//! - \ref UART_CONFIG_PAR_ODD +//! - \ref UART_CONFIG_PAR_ONE +//! - \ref UART_CONFIG_PAR_ZERO +//! +//! \return None +// +//***************************************************************************** +extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config); + +//***************************************************************************** +// +//! \brief Gets the current configuration of a UART. +//! +//! The baud rate and data format for the UART is determined, given an +//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an "official" baud rate. The data format returned in +//! \c pui32Config is enumerated the same as the \c ui32Config parameter of +//! \ref UARTConfigSetExpClk(). +//! +//! \note The peripheral clock is not necessarily the same as the processor +//! clock. The frequency of the peripheral clock is set by the system control. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param pui32Baud is a pointer to storage for the baud rate. +//! \param pui32Config is a pointer to storage for the data format. +//! +//! \return None +// +//***************************************************************************** +extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config); + +//***************************************************************************** +// +//! \brief Enables transmitting and receiving. +//! +//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit +//! and receive FIFOs. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Enable the FIFO. + HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; + + // Enable RX, TX, and the UART. + HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +//! \brief Disables transmitting and receiving. +//! +//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of +//! transmission of the current character, and flushes the transmit FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +extern void UARTDisable(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables the transmit and receive FIFOs. +//! +//! This functions enables the transmit and receive FIFOs in the UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTFIFOEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Enable the FIFO. + HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; +} + +//***************************************************************************** +// +//! \brief Disables the transmit and receive FIFOs. +//! +//! This functions disables the transmit and receive FIFOs in the UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTFIFODisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Disable the FIFO. + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); +} + +//***************************************************************************** +// +//! \brief Determines if there are any characters in the receive FIFO. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns status of the receive FIFO. +//! - \c true : There is data in the receive FIFO. +//! - \c false : There is no data in the receive FIFO. +// +//***************************************************************************** +__STATIC_INLINE bool +UARTCharsAvail(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the availability of characters. + return((HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) ? false : true); +} + +//***************************************************************************** +// +//! \brief Determines if there is any space in the transmit FIFO. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns status of the transmit FIFO. +//! - \c true : There is space available in the transmit FIFO. +//! - \c false : There is no space available in the transmit FIFO. +// +//***************************************************************************** +__STATIC_INLINE bool +UARTSpaceAvail(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the availability of space. + return((HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) ? false : true); +} + +//***************************************************************************** +// +//! \brief Receives a character from the specified port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. +//! +//! \note The \ref UARTCharsAvail() function should be called before +//! attempting to call this function. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns the character read from the specified port, cast as an +//! \c int32_t. A \c -1 is returned if there are no characters present in the +//! receive FIFO. +//! +//! \sa \ref UARTCharsAvail() +// +//***************************************************************************** +extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Waits for a character from the specified port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. If there are no characters available, this function waits until a +//! character is received before returning. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns the character read from the specified port, cast as an +//! \c int32_t. +// +//***************************************************************************** +extern int32_t UARTCharGet(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Sends a character to the specified port. +//! +//! This function writes the character \c ui8Data to the transmit FIFO for the +//! specified port. This function does not block, so if there is no space +//! available, then a \c false is returned, and the application must retry the +//! function later. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui8Data is the character to be transmitted. +//! +//! \return Returns status of the character transmit. +//! - \c true : The character was successfully placed in the transmit FIFO. +//! - \c false : There was no space available in the transmit FIFO. Try again later. +// +//***************************************************************************** +extern bool UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data); + +//***************************************************************************** +// +//! \brief Waits to send a character from the specified port. +//! +//! This function sends the character \c ui8Data to the transmit FIFO for the +//! specified port. If there is no space available in the transmit FIFO, this +//! function waits until there is space available before returning. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui8Data is the character to be transmitted. +//! +//! \return None +// +//***************************************************************************** +extern void UARTCharPut(uint32_t ui32Base, uint8_t ui8Data); + +//***************************************************************************** +// +//! \brief Determines whether the UART transmitter is busy or not. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \c false is returned, the transmit FIFO is +//! empty and all bits of the last transmitted character, including all stop +//! bits, have left the hardware shift register. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns status of UART transmitter. +//! - \c true : UART is transmitting. +//! - \c false : All transmissions are complete. +// +//***************************************************************************** +__STATIC_INLINE bool +UARTBusy(uint32_t ui32Base) +{ + // Check the argument. + ASSERT(UARTBaseValid(ui32Base)); + + // Determine if the UART is busy. + return((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? + UART_BUSY : UART_IDLE); +} + +//***************************************************************************** +// +//! \brief Causes a BREAK to be sent. +//! +//! \note For proper transmission of a break +//! command, the break must be asserted for at least two complete frames. +//! +//! \param ui32Base is the base address of the UART port. +//! \param bBreakState controls the output level. +//! - \c true : Asserts a break condition on the UART. +//! - \c false : Removes the break condition. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTBreakCtl(uint32_t ui32Base, bool bBreakState) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Set the break condition as requested. + HWREG(ui32Base + UART_O_LCRH) = + (bBreakState ? + (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : + (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for a UART interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific UART interrupts must be enabled via \ref UARTIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \param ui32Base is the base address of the UART module. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a UART interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a UART interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \param ui32Base is the base address of the UART module. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void UARTIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables individual UART interrupt sources. +//! +//! This function enables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(ui32Base + UART_O_IMSC) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual UART interrupt sources. +//! +//! This function disables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(ui32Base + UART_O_IMSC) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the specified UART. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the UART port. +//! \param bMasked selects either raw or masked interrupt. +//! - \c true : Masked interrupt status is required. +//! - \c false : Raw interrupt status is required. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of: +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +UARTIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return(HWREG(ui32Base + UART_O_MIS)); + } + else + { + return(HWREG(ui32Base + UART_O_RIS)); + } +} + +//***************************************************************************** +// +//! \brief Clears UART interrupt sources. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments + ASSERT(UARTBaseValid(ui32Base)); + + // Clear the requested interrupt sources + HWREG(ui32Base + UART_O_ICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Enable UART DMA operation. +//! +//! The specified UART DMA features are enabled. The UART can be +//! configured to use DMA for transmit or receive, and to disable +//! receive if an error occurs. +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the UART. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32DMAFlags is a bit mask of the DMA features to enable. +//! The parameter is the bitwise OR of any of the following values: +//! - UART_DMA_RX : Enable DMA for receive. +//! - UART_DMA_TX : Enable DMA for transmit. +//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Set the requested bits in the UART DMA control register. + HWREG(ui32Base + UART_O_DMACTL) |= ui32DMAFlags; +} + +//***************************************************************************** +// +//! \brief Disable UART DMA operation. +//! +//! This function is used to disable UART DMA features that were enabled +//! by \ref UARTDMAEnable(). The specified UART DMA features are disabled. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32DMAFlags is a bit mask of the DMA features to disable. +//! The parameter is the bitwise OR of any of the following values: +//! - UART_DMA_RX : Enable DMA for receive. +//! - UART_DMA_TX : Enable DMA for transmit. +//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Clear the requested bits in the UART DMA control register. + HWREG(ui32Base + UART_O_DMACTL) &= ~ui32DMAFlags; +} + +//***************************************************************************** +// +//! \brief Gets current receiver errors. +//! +//! This function returns the current state of each of the 4 receiver error +//! sources. The returned errors are equivalent to the four error bits +//! returned via the previous call to \ref UARTCharGet() or \ref UARTCharGetNonBlocking() +//! with the exception that the overrun error is set immediately the overrun +//! occurs rather than when a character is next read. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns a bitwise OR combination of the receiver error flags: +//! - \ref UART_RXERROR_FRAMING +//! - \ref UART_RXERROR_PARITY +//! - \ref UART_RXERROR_BREAK +//! - \ref UART_RXERROR_OVERRUN +// +//***************************************************************************** +__STATIC_INLINE uint32_t +UARTRxErrorGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the current value of the receive status register. + return(HWREG(ui32Base + UART_O_RSR) & 0x0000000F); +} + +//***************************************************************************** +// +//! \brief Clears all reported receiver errors. +//! +//! This function is used to clear all receiver error conditions reported via +//! \ref UARTRxErrorGet(). If using the overrun, framing error, parity error or +//! break interrupts, this function must be called after clearing the interrupt +//! to ensure that later errors of the same type trigger another interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTRxErrorClear(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Any write to the Error Clear Register will clear all bits which are + // currently set. + HWREG(ui32Base + UART_O_ECR) = 0; +} + +//***************************************************************************** +// +//! \brief Enables hardware flow control for both CTS and RTS +//! +//! Hardware flow control is disabled by default. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTHwFlowControlEnable( uint32_t ui32Base ) +{ + // Check the arguments. + ASSERT( UARTBaseValid( ui32Base )); + + HWREG( ui32Base + UART_O_CTL ) |= ( UART_CTL_CTSEN | UART_CTL_RTSEN ); +} + +//***************************************************************************** +// +//! \brief Disables hardware flow control for both CTS and RTS +//! +//! Hardware flow control is disabled by default. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTHwFlowControlDisable( uint32_t ui32Base ) +{ + // Check the arguments. + ASSERT( UARTBaseValid( ui32Base )); + + HWREG( ui32Base + UART_O_CTL ) &= ~( UART_CTL_CTSEN | UART_CTL_RTSEN ); +} + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_UARTFIFOLevelGet + #undef UARTFIFOLevelGet + #define UARTFIFOLevelGet ROM_UARTFIFOLevelGet + #endif + #ifdef ROM_UARTConfigSetExpClk + #undef UARTConfigSetExpClk + #define UARTConfigSetExpClk ROM_UARTConfigSetExpClk + #endif + #ifdef ROM_UARTConfigGetExpClk + #undef UARTConfigGetExpClk + #define UARTConfigGetExpClk ROM_UARTConfigGetExpClk + #endif + #ifdef ROM_UARTDisable + #undef UARTDisable + #define UARTDisable ROM_UARTDisable + #endif + #ifdef ROM_UARTCharGetNonBlocking + #undef UARTCharGetNonBlocking + #define UARTCharGetNonBlocking ROM_UARTCharGetNonBlocking + #endif + #ifdef ROM_UARTCharGet + #undef UARTCharGet + #define UARTCharGet ROM_UARTCharGet + #endif + #ifdef ROM_UARTCharPutNonBlocking + #undef UARTCharPutNonBlocking + #define UARTCharPutNonBlocking ROM_UARTCharPutNonBlocking + #endif + #ifdef ROM_UARTCharPut + #undef UARTCharPut + #define UARTCharPut ROM_UARTCharPut + #endif + #ifdef ROM_UARTIntRegister + #undef UARTIntRegister + #define UARTIntRegister ROM_UARTIntRegister + #endif + #ifdef ROM_UARTIntUnregister + #undef UARTIntUnregister + #define UARTIntUnregister ROM_UARTIntUnregister + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart_doc.h new file mode 100644 index 0000000..ba77f94 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart_doc.h @@ -0,0 +1,107 @@ +/****************************************************************************** +* Filename: uart_doc.h +* Revised: 2018-02-09 15:45:36 +0100 (fr, 09 feb 2018) +* Revision: 51470 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +/*! +\addtogroup uart_api +@{ + +\section sec_uart_printf Use printf() + +DriverLib only supports writing a single character at a time to the UART buffer but it is +possible to utilize the library function \c printf by overriding a few of the functions used by +\c printf with a device specific definition. However, the implementation of \c printf is +compiler specific and requires different functions to be overridden depending on the compiler. + +Using \c printf can increase code size significantly but some compilers provide a highly optimized +and configurable implementation suitable for embedded systems which makes the code size increase +acceptable for most applications. See the compiler's documentation for details about how to +configure the \c printf library function. + +It is required that the application configures and enables the UART module before using \c printf +function. + +\subsection sec_uart_printf_ccs Code Composer Studio + +In Code Composer Studio the functions \c fputc and \c fputs must be overridden. + +\code{.c} +#include +#include + +#define PRINTF_UART UART0_BASE + +// Override 'fputc' function in order to use printf() to output to UART +int fputc(int _c, register FILE *_fp) +{ + UARTCharPut(PRINTF_UART, (uint8_t)_c); + return _c; +} + +// Override 'fputs' function in order to use printf() to output to UART +int fputs(const char *_ptr, register FILE *_fp) +{ + unsigned int i, len; + + len = strlen(_ptr); + + for(i=0 ; i +#include + +#define PRINTF_UART UART0_BASE + +// Override 'putchar' function in order to use printf() to output to UART. +int putchar(int data) +{ + UARTCharPut(PRINTF_UART, (uint8_t)data); + return data; +} +\endcode + +@} +*/ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/udma.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/udma.c new file mode 100644 index 0000000..0665a42 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/udma.c @@ -0,0 +1,448 @@ +/****************************************************************************** +* Filename: udma.c +* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) +* Revision: 48852 +* +* Description: Driver for the uDMA controller +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "udma.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef uDMAChannelAttributeEnable + #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable + #undef uDMAChannelAttributeDisable + #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable + #undef uDMAChannelAttributeGet + #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet + #undef uDMAChannelControlSet + #define uDMAChannelControlSet NOROM_uDMAChannelControlSet + #undef uDMAChannelTransferSet + #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet + #undef uDMAChannelScatterGatherSet + #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet + #undef uDMAChannelSizeGet + #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet + #undef uDMAChannelModeGet + #define uDMAChannelModeGet NOROM_uDMAChannelModeGet +#endif + +//***************************************************************************** +// +// Enables attributes of a uDMA channel +// +//***************************************************************************** +void +uDMAChannelAttributeEnable(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32Attr) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Set the useburst bit for this channel if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_SETBURST) = 1 << ui32ChannelNum; + } + + // Set the alternate control select bit for this channel, + // if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // Set the high priority bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // Set the request mask bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_SETREQMASK) = 1 << ui32ChannelNum; + } +} + +//***************************************************************************** +// +// Disables attributes of an uDMA channel +// +//***************************************************************************** +void +uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32Attr) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Clear the useburst bit for this channel if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_CLEARBURST) = 1 << ui32ChannelNum; + } + + // Clear the alternate control select bit for this channel, if set in + // ululAttr. + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // Clear the high priority bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // Clear the request mask bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_CLEARREQMASK) = 1 << ui32ChannelNum; + } +} + +//***************************************************************************** +// +// Gets the enabled attributes of a uDMA channel +// +//***************************************************************************** +uint32_t +uDMAChannelAttributeGet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + uint32_t ui32Attr = 0; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Check to see if useburst bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETBURST) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_USEBURST; + } + + // Check to see if the alternate control bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_ALTSELECT; + } + + // Check to see if the high priority bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // Check to see if the request mask bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETREQMASK) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_REQMASK; + } + + // Return the configuration flags. + return(ui32Attr); +} + +//***************************************************************************** +// +// Sets the control parameters for a uDMA channel control structure +// +//***************************************************************************** +void +uDMAChannelControlSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, + uint32_t ui32Control) +{ + tDMAControlTable *pControlTable; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + pControlTable[ui32ChannelStructIndex].ui32Control = + ((pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_DST_INC_M | + UDMA_SRC_INC_M | + UDMA_SIZE_M | + UDMA_ARB_M | + UDMA_NEXT_USEBURST)) | + ui32Control); +} + +//***************************************************************************** +// +// Sets the transfer parameters for a uDMA channel control structure +// +//***************************************************************************** +void +uDMAChannelTransferSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, + uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, + uint32_t ui32TransferSize) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + uint32_t ui32Inc; + uint32_t ui32BufferBytes; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((uint32_t)pvSrcAddr >= SRAM_BASE); + ASSERT((uint32_t)pvDstAddr >= SRAM_BASE); + ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= UDMA_XFER_SIZE_MAX)); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off the mode and size + // fields. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // Adjust the mode if the alt control structure is selected. + if(ui32ChannelStructIndex & UDMA_ALT_SELECT) + { + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Mode |= UDMA_MODE_ALT_SELECT; + } + } + + // Set the transfer size and mode in the control word (but don't write the + // control word yet as it could kick off a transfer). + ui32Control |= ui32Mode | ((ui32TransferSize - 1) << UDMA_XFER_SIZE_S); + + // Get the address increment value for the source, from the control word. + ui32Inc = (ui32Control & UDMA_SRC_INC_M); + + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + if(ui32Inc != UDMA_SRC_INC_NONE) + { + ui32Inc = ui32Inc >> UDMA_SRC_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - (1 << ui32Inc)); + } + + // Load the source ending address into the control block. + pControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; + + // Get the address increment value for the destination, from the control + // word. + ui32Inc = ui32Control & UDMA_DST_INC_M; + + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + if(ui32Inc != UDMA_DST_INC_NONE) + { + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer needs to point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + pvDstAddr = + (void *)&pControlTable[ui32ChannelStructIndex | + UDMA_ALT_SELECT].ui32Spare; + } + // Not a scatter-gather transfer, calculate end pointer normally. + else + { + ui32Inc = ui32Inc >> UDMA_DST_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); + } + } + + // Load the destination ending address into the control block. + pControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; + + // Write the new control word value. + pControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; +} + +//***************************************************************************** +// +// Configures a uDMA channel for scatter-gather mode +// +//***************************************************************************** +void +uDMAChannelScatterGatherSet(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32TaskCount, void *pvTaskList, + uint32_t ui32IsPeriphSG) +{ + tDMAControlTable *pControlTable; + tDMAControlTable *pTaskTable; + + // Check the parameters. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(pvTaskList != 0); + ASSERT(ui32TaskCount <= UDMA_XFER_SIZE_MAX); + ASSERT(ui32TaskCount != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get a handy pointer to the task list. + pTaskTable = (tDMAControlTable *)pvTaskList; + + // Compute the ending address for the source pointer. This will be the + // last element of the last task in the task table. + pControlTable[ui32ChannelNum].pvSrcEndAddr = + &pTaskTable[ui32TaskCount - 1].ui32Spare; + + // Compute the ending address for the destination pointer. This will be + // the end of the alternate structure for this channel. + pControlTable[ui32ChannelNum].pvDstEndAddr = + &pControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; + + // Compute the control word. Most configurable items are fixed for + // scatter-gather. Item and increment sizes are all 32-bit and arb + // size must be 4. The count is the number of items in the task list + // times 4 (4 words per task). + pControlTable[ui32ChannelNum].ui32Control = + (UDMA_DST_INC_32 | UDMA_SRC_INC_32 | + UDMA_SIZE_32 | UDMA_ARB_4 | + (((ui32TaskCount * 4) - 1) << UDMA_XFER_SIZE_S) | + (ui32IsPeriphSG ? UDMA_MODE_PER_SCATTER_GATHER : + UDMA_MODE_MEM_SCATTER_GATHER)); + + // Scatter-gather operations can leave the alt bit set. So if doing + // back to back scatter-gather transfers, the second attempt may not + // work correctly because the alt bit is set. Therefore, clear the + // alt bit here to ensure that it is always cleared before a new SG + // transfer is started. + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + +} + +//***************************************************************************** +// +// Gets the current transfer size for a uDMA channel control structure +// +//***************************************************************************** +uint32_t +uDMAChannelSizeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off all but the size field + // and the mode field. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + (UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // If the size field and mode field are 0 then the transfer is finished + // and there are no more items to transfer. + if(ui32Control == 0) + { + return(0); + } + + // Otherwise, if either the size field or more field is non-zero, then + // not all the items have been transferred. + else + { + // Shift the size field and add one, then return to user. + return((ui32Control >> UDMA_XFER_SIZE_S) + 1); + } +} + +//***************************************************************************** +// +// Gets the transfer mode for a uDMA channel control structure +// +//***************************************************************************** +uint32_t +uDMAChannelModeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off all but the mode field. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + UDMA_MODE_M); + + // Check if scatter/gather mode, and if so, mask off the alt bit. + if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || + ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Control &= ~UDMA_MODE_ALT_SELECT; + } + + // Return the mode to the caller. + return(ui32Control); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/udma.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/udma.h new file mode 100644 index 0000000..443da6e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/udma.h @@ -0,0 +1,1240 @@ +/****************************************************************************** +* Filename: udma.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and prototypes for the uDMA controller. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup udma_api +//! @{ +// +//***************************************************************************** + +#ifndef __UDMA_H__ +#define __UDMA_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_udma.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable + #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable + #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet + #define uDMAChannelControlSet NOROM_uDMAChannelControlSet + #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet + #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet + #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet + #define uDMAChannelModeGet NOROM_uDMAChannelModeGet +#endif + +//***************************************************************************** +// +//! \brief A structure that defines an entry in the channel control table. +//! +//! These fields are used by the uDMA controller and normally it is not necessary for +//! software to directly read or write fields in the table. +// +//***************************************************************************** +typedef struct +{ + volatile void *pvSrcEndAddr; //!< The ending source address of the data transfer. + volatile void *pvDstEndAddr; //!< The ending destination address of the data transfer. + volatile uint32_t ui32Control; //!< The channel control mode. + volatile uint32_t ui32Spare; //!< An unused location. +} +tDMAControlTable; + +//***************************************************************************** +// +//! \brief A helper macro for building scatter-gather task table entries. +//! +//! This macro is intended to be used to help populate a table of uDMA tasks +//! for a scatter-gather transfer. This macro will calculate the values for +//! the fields of a task structure entry based on the input parameters. +//! +//! There are specific requirements for the values of each parameter. No +//! checking is done so it is up to the caller to ensure that correct values +//! are used for the parameters. +//! +//! This macro is intended to be used to initialize individual entries of +//! a structure of tDMAControlTable type, like this: +//! +/*! +\verbatim + tDMAControlTable MyTaskList[] = + { + uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, + UDMA_SRC_INC_8, MySourceBuf, + UDMA_DST_INC_8, MyDestBuf, + UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), + uDMATaskStructEntry(Task2Count, ... ), + } +\endverbatim +*/ +//! \param ui32TransferCount is the count of items to transfer for this task. +//! It must be in the range 1-1024. +//! \param ui32ItemSize is the bit size of the items to transfer for this task. +//! It must be one of: +//! - \ref UDMA_SIZE_8 +//! - \ref UDMA_SIZE_16 +//! - \ref UDMA_SIZE_32 +//! \param ui32SrcIncrement is the bit size increment for source data. +//! It must be one of: +//! - \ref UDMA_SRC_INC_8 +//! - \ref UDMA_SRC_INC_16 +//! - \ref UDMA_SRC_INC_32 +//! - \ref UDMA_SRC_INC_NONE +//! \param pvSrcAddr is the starting address of the data to transfer. +//! \param ui32DstIncrement is the bit size increment for destination data. +//! It must be one of: +//! - \ref UDMA_DST_INC_8 +//! - \ref UDMA_DST_INC_16 +//! - \ref UDMA_DST_INC_32 +//! - \ref UDMA_DST_INC_NONE +//! \param pvDstAddr is the starting address of the destination data. +//! \param ui32ArbSize is the arbitration size to use for the transfer task. +//! This is used to select the arbitration size in powers of 2, from 1 to 1024. +//! It must be one of: +//! - \ref UDMA_ARB_1 +//! - \ref UDMA_ARB_2 +//! - \ref UDMA_ARB_4 +//! - ... +//! - \ref UDMA_ARB_1024 +//! \param ui32Mode is the transfer mode for this task. +//! Note that normally all tasks will be one of the scatter-gather modes while the +//! last task is a task list will be AUTO or BASIC. +//! It must be one of: +//! - \ref UDMA_MODE_BASIC +//! - \ref UDMA_MODE_AUTO +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER +//! - \ref UDMA_MODE_PER_SCATTER_GATHER +//! +//! \return None (this is not a function) +// +//***************************************************************************** +#define uDMATaskStructEntry(ui32TransferCount, \ + ui32ItemSize, \ + ui32SrcIncrement, \ + pvSrcAddr, \ + ui32DstIncrement, \ + pvDstAddr, \ + ui32ArbSize, \ + ui32Mode) \ + { \ + (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : \ + ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \ + ((ui32SrcIncrement) >> 26)) - 1]))), \ + (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : \ + ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \ + ((ui32DstIncrement) >> 30)) - 1]))), \ + (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ + (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \ + ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ + ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ + (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \ + } + +//***************************************************************************** +// +// The hardware configured number of uDMA channels. +// +//***************************************************************************** +#define UDMA_NUM_CHANNELS 21 + +//***************************************************************************** +// +// The level of priority for the uDMA channels +// +//***************************************************************************** +#define UDMA_PRIORITY_LOW 0x00000000 +#define UDMA_PRIORITY_HIGH 0x00000001 + +//***************************************************************************** +// +// Flags that can be passed to uDMAChannelAttributeEnable(), +// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). +// +//***************************************************************************** +#define UDMA_ATTR_USEBURST 0x00000001 +#define UDMA_ATTR_ALTSELECT 0x00000002 +#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 +#define UDMA_ATTR_REQMASK 0x00000008 +#define UDMA_ATTR_ALL 0x0000000F + +//***************************************************************************** +// +// DMA control modes that can be passed to uDMAChannelModeSet() and returned +// uDMAChannelModeGet(). +// +//***************************************************************************** +#define UDMA_MODE_STOP 0x00000000 +#define UDMA_MODE_BASIC 0x00000001 +#define UDMA_MODE_AUTO 0x00000002 +#define UDMA_MODE_PINGPONG 0x00000003 +#define UDMA_MODE_MEM_SCATTER_GATHER \ + 0x00000004 +#define UDMA_MODE_PER_SCATTER_GATHER \ + 0x00000006 +#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_MODE_ALT_SELECT 0x00000001 + +//***************************************************************************** +// +// Channel configuration values that can be passed to uDMAControlSet(). +// +//***************************************************************************** +#define UDMA_DST_INC_8 0x00000000 +#define UDMA_DST_INC_16 0x40000000 +#define UDMA_DST_INC_32 0x80000000 +#define UDMA_DST_INC_NONE 0xC0000000 +#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment +#define UDMA_DST_INC_S 30 +#define UDMA_SRC_INC_8 0x00000000 +#define UDMA_SRC_INC_16 0x04000000 +#define UDMA_SRC_INC_32 0x08000000 +#define UDMA_SRC_INC_NONE 0x0c000000 +#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment +#define UDMA_SRC_INC_S 26 +#define UDMA_SIZE_8 0x00000000 +#define UDMA_SIZE_16 0x11000000 +#define UDMA_SIZE_32 0x22000000 +#define UDMA_SIZE_M 0x33000000 // Data Size +#define UDMA_SIZE_S 24 +#define UDMA_ARB_1 0x00000000 +#define UDMA_ARB_2 0x00004000 +#define UDMA_ARB_4 0x00008000 +#define UDMA_ARB_8 0x0000c000 +#define UDMA_ARB_16 0x00010000 +#define UDMA_ARB_32 0x00014000 +#define UDMA_ARB_64 0x00018000 +#define UDMA_ARB_128 0x0001c000 +#define UDMA_ARB_256 0x00020000 +#define UDMA_ARB_512 0x00024000 +#define UDMA_ARB_1024 0x00028000 +#define UDMA_ARB_M 0x0003C000 // Arbitration Size +#define UDMA_ARB_S 14 +#define UDMA_NEXT_USEBURST 0x00000008 +#define UDMA_XFER_SIZE_MAX 1024 +#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size +#define UDMA_XFER_SIZE_S 4 + +//***************************************************************************** +// +// Channel numbers to be passed to API functions that require a channel number +// ID. +// +//***************************************************************************** +#define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0 +#define UDMA_CHAN_UART0_RX 1 // UART0 RX Data +#define UDMA_CHAN_UART0_TX 2 // UART0 RX Data +#define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data +#define UDMA_CHAN_SSI0_TX 4 // SSI0 RX Data +#define UDMA_CHAN_AUX_ADC 7 // AUX ADC event +#define UDMA_CHAN_AUX_SW 8 // AUX Software event +#define UDMA_CHAN_TIMER0_A 9 // Timer0 A event +#define UDMA_CHAN_TIMER0_B 10 // Timer0 B event +#define UDMA_CHAN_TIMER1_A 11 +#define UDMA_CHAN_TIMER1_B 12 +#define UDMA_CHAN_AON_PROG2 13 +#define UDMA_CHAN_DMA_PROG 14 +#define UDMA_CHAN_AON_RTC 15 +#define UDMA_CHAN_SSI1_RX 16 +#define UDMA_CHAN_SSI1_TX 17 +#define UDMA_CHAN_SW_EVT1 18 +#define UDMA_CHAN_SW_EVT2 19 +#define UDMA_CHAN_SW_EVT3 20 + +//***************************************************************************** +// +// Flags to be OR'd with the channel ID to indicate if the primary or alternate +// control structure should be used. +// +//***************************************************************************** +#define UDMA_PRI_SELECT 0x00000000 +#define UDMA_ALT_SELECT 0x00000020 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks a uDMA base address. +//! +//! This function determines if a uDMA module base address is valid. +//! +//! \param ui32Base specifies the uDMA module base address. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +uDMABaseValid(uint32_t ui32Base) +{ + return(ui32Base == UDMA0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Enables the uDMA controller for use. +//! +//! This function enables the uDMA controller. The uDMA controller must be +//! enabled before it can be configured and used. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Set the master enable bit in the config register. + HWREG(ui32Base + UDMA_O_CFG) = UDMA_CFG_MASTERENABLE; +} + +//***************************************************************************** +// +//! \brief Disables the uDMA controller for use. +//! +//! This function disables the uDMA controller. Once disabled, the uDMA +//! controller will not operate until re-enabled with \ref uDMAEnable(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +uDMADisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Clear the master enable bit in the config register. + HWREG(ui32Base + UDMA_O_CFG) = 0; +} + +//***************************************************************************** +// +//! \brief Gets the uDMA error status. +//! +//! This function returns the uDMA error status. It should be called from +//! within the uDMA error interrupt handler to determine if a uDMA error +//! occurred. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Returns non-zero if a uDMA error is pending. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +uDMAErrorStatusGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Return the uDMA error status. + return(HWREG(ui32Base + UDMA_O_ERROR)); +} + +//***************************************************************************** +// +//! \brief Clears the uDMA error interrupt. +//! +//! This function clears a pending uDMA error interrupt. It should be called +//! from within the uDMA error interrupt handler to clear the interrupt. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAErrorStatusClear(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Clear the uDMA error interrupt. + HWREG(ui32Base + UDMA_O_ERROR) = UDMA_ERROR_STATUS; +} + +//***************************************************************************** +// +//! \brief Enables a uDMA channel for operation. +//! +//! This function enables a specific uDMA channel for use. This function must +//! be used to enable a channel before it can be used to perform a uDMA +//! transfer. +//! +//! When a uDMA transfer is completed, the channel will be automatically +//! disabled by the uDMA controller. Therefore, this function should be called +//! prior to starting up any new transfer. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number to enable. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelEnable(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the bit for this channel in the enable set register. + HWREG(ui32Base + UDMA_O_SETCHANNELEN) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Disables a uDMA channel for operation. +//! +//! This function disables a specific uDMA channel. Once disabled, a channel +//! will not respond to uDMA transfer requests until re-enabled via +//! \ref uDMAChannelEnable(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number to disable. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelDisable(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the bit for this channel in the enable clear register. + HWREG(ui32Base + UDMA_O_CLEARCHANNELEN) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Checks if a uDMA channel is enabled for operation. +//! +//! This function checks to see if a specific uDMA channel is enabled. This +//! can be used to check the status of a transfer, since the channel will +//! be automatically disabled at the end of a transfer. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number to check. +//! +//! \return Returns status of uDMA channel. +//! - \c true : Channel is enabled. +//! - \c false : Disabled. +// +//***************************************************************************** +__STATIC_INLINE bool +uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // AND the specified channel bit with the enable register, and return the + // result. + return((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ? + true : false); +} + +//***************************************************************************** +// +//! \brief Sets the base address for the channel control table. +//! +//! This function sets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. The table must be aligned on a 1024 byte boundary. The base +//! address must be set before any of the channel functions can be used. +//! Setting the base address of the primary control table will automatically +//! set the address for the alternate control table as the next memory +//! location after the primary control table. +//! +//! The size of the channel control table depends on the number of uDMA +//! channels, and which transfer modes are used. Refer to the introductory +//! text and the microcontroller datasheet for more information about the +//! channel control table. +//! +//! \note This register cannot be read when the controller is in the reset +//! state. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param pControlTable is a pointer to the 1024 byte aligned base address +//! of the uDMA channel control table. The address must be an absolute address +//! in system memory space. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAControlBaseSet(uint32_t ui32Base, void *pControlTable) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(((uint32_t)pControlTable & ~0x3FF) == + (uint32_t)pControlTable); + ASSERT((uint32_t)pControlTable >= SRAM_BASE); + + // Program the base address into the register. + HWREG(ui32Base + UDMA_O_CTRL) = (uint32_t)pControlTable; +} + +//***************************************************************************** +// +//! \brief Gets the base address for the channel control table. +//! +//! This function gets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Returns a pointer to the base address of the channel control table. +// +//***************************************************************************** +__STATIC_INLINE void * +uDMAControlBaseGet(uint32_t ui32Base) +{ + // Check the arguments. + + ASSERT(uDMABaseValid(ui32Base)); + // Read the current value of the control base register, and return it to + // the caller. + return((void *)HWREG(ui32Base + UDMA_O_CTRL)); +} + +//***************************************************************************** +// +//! \brief Gets the base address for the channel control table alternate structures. +//! +//! This function gets the base address of the second half of the channel +//! control table that holds the alternate control structures for each channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Returns a pointer to the base address of the second half of the +//! channel control table. +// +//***************************************************************************** +__STATIC_INLINE void * +uDMAControlAlternateBaseGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Read the current value of the control base register, and return it to + // the caller. + return((void *)HWREG(ui32Base + UDMA_O_ALTCTRL)); +} + +//***************************************************************************** +// +//! \brief Requests a uDMA channel to start a transfer. +//! +//! This function allows software to request a uDMA channel to begin a +//! transfer. This could be used for performing a memory to memory transfer, +//! or if for some reason a transfer needs to be initiated by software instead +//! of the peripheral associated with that channel. +//! +//! \note If the channel is a software channel and interrupts are used, then +//! the completion will be signaled on the uDMA dedicated interrupt. If a +//! peripheral channel is used, then the completion will be signaled on the +//! peripheral's interrupt. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number on which to request a uDMA +//! transfer. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelRequest(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the bit for this channel in the software uDMA request register. + HWREG(ui32Base + UDMA_O_SOFTREQ) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Enables attributes of a uDMA channel. +//! +//! This function is used to enable attributes of a uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel to configure. +//! \param ui32Attr is a combination of attributes for the channel. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelAttributeEnable(uint32_t ui32Base, + uint32_t ui32ChannelNum, + uint32_t ui32Attr); + +//***************************************************************************** +// +//! \brief Disables attributes of an uDMA channel. +//! +//! This function is used to disable attributes of a uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel to configure. +//! \param ui32Attr is a combination of attributes for the channel. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelAttributeDisable(uint32_t ui32Base, + uint32_t ui32ChannelNum, + uint32_t ui32Attr); + +//***************************************************************************** +// +//! \brief Gets the enabled attributes of a uDMA channel. +//! +//! This function returns a combination of flags representing the attributes of +//! the uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel to configure. +//! +//! \return Returns the bitwise OR of the attributes of the uDMA channel, which +//! can be any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +// +//***************************************************************************** +extern uint32_t uDMAChannelAttributeGet(uint32_t ui32Base, + uint32_t ui32ChannelNum); + +//***************************************************************************** +// +//! \brief Sets the control parameters for a uDMA channel control structure. +//! +//! This function is used to set control parameters for a uDMA transfer. These +//! are typically parameters that are not changed often. +//! +//! \note The address increment cannot be smaller than the data size. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT : Use primary data structure. +//! - \ref UDMA_ALT_SELECT : Use alternate data structure. +//! \param ui32Control is the bitwise OR of five values: +//! - Data size +//! - \ref UDMA_SIZE_8 : 8 bits. +//! - \ref UDMA_SIZE_16 : 16 bits. +//! - \ref UDMA_SIZE_32 : 32 bits. +//! - Source address increment +//! - \ref UDMA_SRC_INC_8 : 8 bits. +//! - \ref UDMA_SRC_INC_16 : 16 bits. +//! - \ref UDMA_SRC_INC_32 : 32 bits. +//! - \ref UDMA_SRC_INC_NONE : Non-incrementing. +//! - Destination address increment +//! - \ref UDMA_DST_INC_8 : 8 bits. +//! - \ref UDMA_DST_INC_16 : 16 bits. +//! - \ref UDMA_DST_INC_32 : 32 bits. +//! - \ref UDMA_DST_INC_NONE : Non-incrementing. +//! - Arbitration size. Determines how many items are transferred before +//! the uDMA controller re-arbitrates for the bus. In power of 2. +//! - \ref UDMA_ARB_1 +//! - \ref UDMA_ARB_2 +//! - \ref UDMA_ARB_4 +//! - \ref UDMA_ARB_8 +//! - ... +//! - \ref UDMA_ARB_1024 +//! - Force the channel to only respond to burst requests at the tail end of a scatter-gather transfer. +//! - \ref UDMA_NEXT_USEBURST +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelControlSet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex, + uint32_t ui32Control); + +//***************************************************************************** +// +//! \brief Sets the transfer parameters for a uDMA channel control structure. +//! +//! This function is used to set the parameters for a uDMA transfer. These are +//! typically parameters that are changed often. The function +//! \ref uDMAChannelControlSet() MUST be called at least once for this channel prior +//! to calling this function. +//! +//! The \c pvSrcAddr and \c pvDstAddr parameters are pointers to the first +//! location of the data to be transferred. These addresses should be aligned +//! according to the item size. The compiler will take care of this if the +//! pointers are pointing to storage of the appropriate data type. +//! +//! The two scatter/gather modes, MEMORY and PERIPHERAL, are actually different +//! depending on whether the primary or alternate control structure is +//! selected. This function will look for the \ref UDMA_PRI_SELECT and +//! \ref UDMA_ALT_SELECT flag along with the channel number and will set the +//! scatter/gather mode as appropriate for the primary or alternate control +//! structure. +//! +//! The channel must also be enabled using \ref uDMAChannelEnable() after calling +//! this function. The transfer will not begin until the channel has been set +//! up and enabled. Note that the channel is automatically disabled after the +//! transfer is completed, meaning that \ref uDMAChannelEnable() must be called +//! again after setting up the next transfer. +//! +//! \note Great care must be taken to not modify a channel control structure +//! that is in use or else the results will be unpredictable, including the +//! possibility of undesired data transfers to or from memory or peripherals. +//! For BASIC and AUTO modes, it is safe to make changes when the channel is +//! disabled, or the \ref uDMAChannelModeGet() returns \ref UDMA_MODE_STOP. For +//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the +//! primary or alternate control structure only when the other is being used. +//! The \ref uDMAChannelModeGet() function will return \ref UDMA_MODE_STOP when a +//! channel control structure is inactive and safe to modify. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT : Use primary data structure. +//! - \ref UDMA_ALT_SELECT : Use alternate data structure. +//! \param ui32Mode is the type of uDMA transfer. +//! The parameter should be one of the following values: +//! - \ref UDMA_MODE_STOP : Stops the uDMA transfer. The controller sets the mode +//! to this value at the end of a transfer. +//! - \ref UDMA_MODE_BASIC : Perform a basic transfer based on request. +//! - \ref UDMA_MODE_AUTO to perform a transfer that will always complete once +//! started even if request is removed. +//! - \ref UDMA_MODE_PINGPONG : Set up a transfer that switches between the +//! primary and alternate control structures for the channel. This allows +//! use of ping-pong buffering for uDMA transfers. +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER : Set up a memory scatter-gather transfer. +//! - \ref UDMA_MODE_PER_SCATTER_GATHER : Set up a peripheral scatter-gather transfer. +//! \param pvSrcAddr is the source address for the transfer. +//! \param pvDstAddr is the destination address for the transfer. +//! \param ui32TransferSize is the number of data items to transfer (\b NOT bytes). +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelTransferSet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex, + uint32_t ui32Mode, void *pvSrcAddr, + void *pvDstAddr, uint32_t ui32TransferSize); + +//***************************************************************************** +// +//! \brief Configures a uDMA channel for scatter-gather mode. +//! +//! This function is used to configure a channel for scatter-gather mode. +//! The caller must have already set up a task list, and pass a pointer to +//! the start of the task list as the \c pvTaskList parameter. +//! +//! The \c ui32TaskCount parameter is the count of tasks in the task list, not the +//! size of the task list. +//! +//! The flag \c bIsPeriphSG should be used to indicate +//! if the scatter-gather should be configured for a peripheral or memory +//! scatter-gather operation. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the uDMA channel number. +//! \param ui32TaskCount is the number of scatter-gather tasks to execute. +//! \param pvTaskList is a pointer to the beginning of the scatter-gather +//! task list. +//! \param ui32IsPeriphSG is a flag to indicate it is a peripheral +//! scatter-gather transfer (else it will be memory scatter-gather transfer) +//! +//! \return None +//! +//! \sa \ref uDMATaskStructEntry() +// +//***************************************************************************** +extern void uDMAChannelScatterGatherSet(uint32_t ui32Base, + uint32_t ui32ChannelNum, + uint32_t ui32TaskCount, + void *pvTaskList, + uint32_t ui32IsPeriphSG); + +//***************************************************************************** +// +//! \brief Gets the current transfer size for a uDMA channel control structure. +//! +//! This function is used to get the uDMA transfer size for a channel. The +//! transfer size is the number of items to transfer, where the size of an item +//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, +//! then the number of remaining items will be returned. If the transfer is +//! complete, then 0 will be returned. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT +//! - \ref UDMA_ALT_SELECT +//! +//! \return Returns the number of items remaining to transfer. +// +//***************************************************************************** +extern uint32_t uDMAChannelSizeGet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex); + +//***************************************************************************** +// +//! \brief Gets the transfer mode for a uDMA channel control structure. +//! +//! This function is used to get the transfer mode for the uDMA channel. It +//! can be used to query the status of a transfer on a channel. When the +//! transfer is complete the mode will be \ref UDMA_MODE_STOP. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT +//! - \ref UDMA_ALT_SELECT +//! +//! \return Returns the transfer mode of the specified channel and control +//! structure, which will be one of the following values: +//! - \ref UDMA_MODE_STOP +//! - \ref UDMA_MODE_BASIC +//! - \ref UDMA_MODE_AUTO +//! - \ref UDMA_MODE_PINGPONG +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER +//! - \ref UDMA_MODE_PER_SCATTER_GATHER +// +//***************************************************************************** +extern uint32_t uDMAChannelModeGet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex); + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the uDMA controller in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! \note The interrupt handler for uDMA is for transfer completion when the +//! software channel is used, and for error interrupts. The interrupts for each +//! peripheral channel are handled through the individual peripheral interrupt +//! handlers. +//! +//! \param ui32Base is the base address of the uDMA module. +//! \param ui32IntChannel specifies which uDMA interrupt is to be registered. +//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts +//! from the uDMA software channel. +//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error +//! interrupts. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntRegister(uint32_t ui32Base, uint32_t ui32IntChannel, + void (*pfnHandler)(void)) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(pfnHandler); + ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR)); + + // Register the interrupt handler. + IntRegister(ui32IntChannel, pfnHandler); + + // Enable the memory management fault. + IntEnable(ui32IntChannel); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the uDMA controller in the dynamic interrupt table. +//! +//! This function will disable and clear the handler to be called for the +//! specified uDMA interrupt. +//! +//! \param ui32Base is the base address of the uDMA module. +//! \param ui32IntChannel specifies which uDMA interrupt to unregister. +//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts +//! from the uDMA software channel. +//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error +//! interrupts. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntUnregister(uint32_t ui32Base, uint32_t ui32IntChannel) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR)); + + // Disable the interrupt. + IntDisable(ui32IntChannel); + + // Unregister the interrupt handler. + IntUnregister(ui32IntChannel); +} + +//***************************************************************************** +// +//! \brief Clears uDMA interrupt done status. +//! +//! Clears bits in the uDMA interrupt status register according to which bits +//! are set in \c ui32ChanMask. There is one bit for each channel. If a a bit +//! is set in \c ui32ChanMask, then that corresponding channel's interrupt +//! status will be cleared (if it was set). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntClear(uint32_t ui32Base, uint32_t ui32ChanMask) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Clear the requested bits in the uDMA interrupt status register. + HWREG(ui32Base + UDMA_O_REQDONE) = ui32ChanMask; +} + +//***************************************************************************** +// +//! \brief Get the uDMA interrupt status. +//! +//! This function returns the interrupt status for the specified UDMA. This +//! function does not differentiate between software or hardware activated +//! interrupts. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE uint32_t +uDMAIntStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Return the uDMA interrupt status register. + return (HWREG(ui32Base + UDMA_O_REQDONE)); +} + +//***************************************************************************** +// +//! \brief Enable interrupt on software event driven uDMA transfers. +//! +//! \note The main purpose of this function is to prevent propagation of uDMA +//! status signals to a peripheral, if a peripheral and a software event is +//! sharing the uDMA channel. If it is desired to initiate a transfer by +//! writing to a register inside the uDMA (this means a software driven +//! channel), then the uDMA status signals propagation need to be blocked to +//! the hardware peripherals. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32IntChannel identifies which uDMA interrupt to enable software +//! interrupts for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntSwEventEnable(uint32_t ui32Base, uint32_t ui32IntChannel) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS); + + // Enable the channel. + HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 1; +} + +//***************************************************************************** +// +//! \brief Disable interrupt on software event driven uDMA transfers. +//! +//! This register disables the blocking of the uDMA status signals propagation +//! to the hardware peripheral connected to the uDMA on the \c ui32IntChannel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32IntChannel identifies which uDMA interrupt to disable software +//! interrupts for. +//! +//! \return None +//! +//! \sa \ref uDMAIntSwEventEnable() +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntSwEventDisable(uint32_t ui32Base, uint32_t ui32IntChannel) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS); + + // Disable the SW channel. + HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 0; +} + +//***************************************************************************** +// +//! \brief Return the status of the uDMA module. +//! +//! \note This status register cannot be read when the controller is in the reset state. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Current status of the uDMA module. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +uDMAGetStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Read and return the status register. + return HWREG(ui32Base + UDMA_O_STATUS); +} + +//***************************************************************************** +// +//! \brief Set the priority of a uDMA channel. +//! +//! \note Writing 0 to a bit has no effect on the priority. To reset a channel +//! priority to the default value use \ref uDMAChannelPriorityClear(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is uDMA channel to set the priority for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelPrioritySet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the channel priority to high. + HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Get the priority of a uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum The uDMA channel to get the priority for. +//! +//! \return Returns one of: +//! - \ref UDMA_PRIORITY_HIGH +//! - \ref UDMA_PRIORITY_LOW +// +//***************************************************************************** +__STATIC_INLINE bool +uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Return the channel priority. + return(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ? + UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW); +} + +//***************************************************************************** +// +//! \brief Clear the priority of a uDMA channel. +//! +//! \note Writing 0 to a bit has no effect on the priority. To set a channel +//! priority to high use \ref uDMAChannelPrioritySet(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum The uDMA channel to clear the priority for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Clear the channel priority. + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_uDMAChannelAttributeEnable + #undef uDMAChannelAttributeEnable + #define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable + #endif + #ifdef ROM_uDMAChannelAttributeDisable + #undef uDMAChannelAttributeDisable + #define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable + #endif + #ifdef ROM_uDMAChannelAttributeGet + #undef uDMAChannelAttributeGet + #define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet + #endif + #ifdef ROM_uDMAChannelControlSet + #undef uDMAChannelControlSet + #define uDMAChannelControlSet ROM_uDMAChannelControlSet + #endif + #ifdef ROM_uDMAChannelTransferSet + #undef uDMAChannelTransferSet + #define uDMAChannelTransferSet ROM_uDMAChannelTransferSet + #endif + #ifdef ROM_uDMAChannelScatterGatherSet + #undef uDMAChannelScatterGatherSet + #define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet + #endif + #ifdef ROM_uDMAChannelSizeGet + #undef uDMAChannelSizeGet + #define uDMAChannelSizeGet ROM_uDMAChannelSizeGet + #endif + #ifdef ROM_uDMAChannelModeGet + #undef uDMAChannelModeGet + #define uDMAChannelModeGet ROM_uDMAChannelModeGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UDMA_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/vims.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/vims.c new file mode 100644 index 0000000..8acad07 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/vims.c @@ -0,0 +1,189 @@ +/****************************************************************************** +* Filename: vims.c +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Description: Driver for the VIMS. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "vims.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef VIMSConfigure + #define VIMSConfigure NOROM_VIMSConfigure + #undef VIMSModeSet + #define VIMSModeSet NOROM_VIMSModeSet + #undef VIMSModeGet + #define VIMSModeGet NOROM_VIMSModeGet + #undef VIMSModeSafeSet + #define VIMSModeSafeSet NOROM_VIMSModeSafeSet +#endif + +//***************************************************************************** +// +// Configures the VIMS. +// +//***************************************************************************** +void +VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG); + if(bRoundRobin) + { + ui32Reg |= VIMS_CTL_ARB_CFG; + } + if(bPrefetch) + { + ui32Reg |= VIMS_CTL_PREF_EN; + } + + // Set the Arbitration and prefetch mode. + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +//***************************************************************************** +// +// Set the operational mode of the VIMS +// +//***************************************************************************** +void +VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ASSERT((ui32Mode == VIMS_MODE_DISABLED) || + (ui32Mode == VIMS_MODE_ENABLED) || + (ui32Mode == VIMS_MODE_OFF)); + + // Set the mode. + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~VIMS_CTL_MODE_M; + ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M); + + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +//***************************************************************************** +// +// Get the current operational mode of the VIMS. +// +//***************************************************************************** +uint32_t +VIMSModeGet(uint32_t ui32Base) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_STAT); + if(ui32Reg & VIMS_STAT_MODE_CHANGING) + { + return (VIMS_MODE_CHANGING); + } + else + { + return (ui32Reg & VIMS_STAT_MODE_M); + } +} + +//***************************************************************************** +// +// Safe setting of new VIMS mode +// - Function might be blocking +// - Can be called for any mode change (also if actually not changing mode) +// +//***************************************************************************** +void +VIMSModeSafeSet( uint32_t ui32Base, uint32_t ui32NewMode, bool blocking ) +{ + uint32_t currentMode; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + ASSERT((ui32NewMode == VIMS_MODE_DISABLED) || + (ui32NewMode == VIMS_MODE_ENABLED) || + (ui32NewMode == VIMS_MODE_OFF)); + + // Make sure that only the mode bits are set in the input parameter + // (done just for security since it is critical to the code flow) + ui32NewMode &= VIMS_CTL_MODE_M; + + // Wait for any pending change to complete and get current VIMS mode + // (This is a blocking point but will typically only be a blocking point + // only if mode is changed multiple times with blocking=0) + do { + currentMode = VIMSModeGet( ui32Base ); + } while ( currentMode == VIMS_MODE_CHANGING ); + + // First check that it actually is a mode change request + if ( ui32NewMode != currentMode ) { + // Due to a hw-problem it is strongly recommended to go via VIMS_MODE_OFF + // when leaving VIMS_MODE_ENABLED (=VIMS_CTL_MODE_CACHE) + // (And no need to go via OFF, if OFF is the final state and will be set later) + if (( currentMode == VIMS_CTL_MODE_CACHE ) && + ( ui32NewMode != VIMS_CTL_MODE_OFF ) ) + { + VIMSModeSet( ui32Base, VIMS_MODE_OFF ); + + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for change to complete. + // (Needed blocking point but it takes only some few cycles) + } + } + // Set new mode + VIMSModeSet( ui32Base, ui32NewMode ); + + // Wait for final mode change to complete - if blocking is requested + if ( blocking ) { + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for change to complete. + } + } + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/vims.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/vims.h new file mode 100644 index 0000000..9e6ecaf --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/vims.h @@ -0,0 +1,371 @@ +/****************************************************************************** +* Filename: vims.h +* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) +* Revision: 47343 +* +* Description: Defines and prototypes for the VIMS. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup vims_api +//! @{ +// +//***************************************************************************** + +#ifndef __VIMS_H__ +#define __VIMS_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_vims.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define VIMSConfigure NOROM_VIMSConfigure + #define VIMSModeSet NOROM_VIMSModeSet + #define VIMSModeGet NOROM_VIMSModeGet + #define VIMSModeSafeSet NOROM_VIMSModeSafeSet +#endif + +//***************************************************************************** +// +// Values that can be passed to VIMSModeSet() as the ui32IntFlags parameter, +// and returned from VIMSModeGet(). +// +//***************************************************************************** +#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE + // can not be changed at moment. +#define VIMS_MODE_DISABLED (VIMS_CTL_MODE_GPRAM) // Disabled mode (GPRAM enabled). +#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached. +#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \brief Checks a VIMS base address. +//! +//! This function determines if the VIMS base address is valid. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +VIMSBaseValid(uint32_t ui32Base) +{ + return(ui32Base == VIMS_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Configures the VIMS. +//! +//! This function sets general control settings of the VIMS system. +//! +//! \note The VIMS mode must be set using the \ref VIMSModeSet() call. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param bRoundRobin specifies the arbitration method. +//! - \c true : Round Robin arbitration between the two available read/write interfaces +//! (i.e. Icode/Dcode and Sysbus) is to be used. +//! - \c false : Strict arbitration will be used, where Icode/Dcode +//! is preferred over the Sysbus. +//! \param bPrefetch specifies if prefetching is to be used. +//! - \c true : Cache is to prefetch tag data for the following address. +//! - \c false : No prefetch. +//! +//! \return None +//! +//! \sa \ref VIMSModeSet() +// +//***************************************************************************** +extern void VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, + bool bPrefetch); + +//***************************************************************************** +// +//! \brief Set the operational mode of the VIMS. +//! +//! This function sets the operational mode of the VIMS. +//! +//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. +//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will not be operational. +//! Reads and writes to flash will be uncached. +//! After a short delay (approx. 1029 clock cycles) the VIMS will +//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). +//! +//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is +//! accessible: +//! The GP RAM will be accessible. +//! The Cache will not be operational. +//! Reads from flash will be uncached. +//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). +//! +//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will be operational for SYSCODE space. +//! Reads from flash in USERCODE space will be uncached. +//! +//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. +//! +//! \note The VIMS must be invalidated when switching mode. +//! This is done by setting VIMS_MODE_OFF before setting any new mode. +//! This is automatically handled in \ref VIMSModeSafeSet() +//! +//! \note It is highly recommended that the VIMS is put in disabled mode before +//! \b writing to flash, since the cache will not be updated nor invalidated +//! by flash writes. The line buffers should also be disabled when updating the +//! flash. Once \ref VIMSModeSet() is used to set the VIMS in +//! \ref VIMS_MODE_CHANGING mode, the user should check using +//! \ref VIMSModeGet() when the mode switches to \ref VIMS_MODE_DISABLED. Only when +//! the mode has changed the cache has been completely invalidated. +//! +//! \note Access from System Bus is never cached. Only access through ICODE +//! DCODE bus from the System CPU is cached. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param ui32Mode is the operational mode. +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! +//! \return None +//! +//! \sa \ref VIMSModeGet() and \ref VIMSModeSafeSet() +// +//***************************************************************************** +extern void VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode); + +//***************************************************************************** +// +//! \brief Get the current operational mode of the VIMS. +//! +//! This function returns the operational mode of the VIMS. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return Returns one of: +//! - \ref VIMS_MODE_CHANGING +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! +//! \sa \ref VIMSModeSet() +// +//***************************************************************************** +extern uint32_t VIMSModeGet(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Set the operational mode of the VIMS in a safe sequence. +//! +//! This function sets the operational mode of the VIMS in a safe sequence +//! +//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. +//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will not be operational (read/write to flash will be uncached). +//! After a short delay (approx. 1029 clock cycles) the VIMS will +//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). +//! +//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is +//! accessible: +//! The GP RAM will be accessible. +//! The Cache will not be operational. +//! Reads from flash will be uncached. +//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). +//! +//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will be operational for SYSCODE space. +//! Reads from flash in USERCODE space will be uncached. +//! +//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. +//! +//! \note The VIMS must be invalidated when switching mode. +//! This is done by setting VIMS_MODE_OFF before setting any new mode. +//! This is automatically handled in this function. +//! +//! \note It is highly recommended that the VIMS is put in disabled mode before +//! \b writing to flash, since the cache will not be updated nor invalidated +//! by flash writes. The line buffers should also be disabled when updating the +//! flash. +//! +//! \note Access from System Bus is never cached. Only access through ICODE +//! DCODE bus from the System CPU is cached. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param ui32NewMode is the new operational mode: +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! \param blocking shall be set to TRUE if further code execution shall be +//! blocked (delayed) until mode change is completed. +//! +//! \return None +//! +//! \sa \ref VIMSModeSet() and \ref VIMSModeGet() +// +//***************************************************************************** +extern void VIMSModeSafeSet( uint32_t ui32Base , + uint32_t ui32NewMode , + bool blocking ); + +//***************************************************************************** +// +//! \brief Disable VIMS linebuffers. +//! +//! Linebuffers should only be disabled when attempting to update the flash, to +//! ensure that the content of the buffers is not stale. As soon as flash is +//! updated the linebuffers should be reenabled. Failing to enable +//! will have a performance impact. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +VIMSLineBufDisable(uint32_t ui32Base) +{ + // Disable line buffers + HWREG(ui32Base + VIMS_O_CTL) |= VIMS_CTL_IDCODE_LB_DIS_M | + VIMS_CTL_SYSBUS_LB_DIS_M; +} + +//***************************************************************************** +// +//! \brief Enable VIMS linebuffers. +//! +//! Linebuffers should only be disabled when attempting to update the flash, to +//! ensure that the content of the buffers is not stale. As soon as flash is +//! updated the linebuffers should be reenabled. Failing to enable +//! will have a performance impact. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +VIMSLineBufEnable(uint32_t ui32Base) +{ + // Enable linebuffers + HWREG(ui32Base + VIMS_O_CTL) &= ~(VIMS_CTL_IDCODE_LB_DIS_M | + VIMS_CTL_SYSBUS_LB_DIS_M); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_VIMSConfigure + #undef VIMSConfigure + #define VIMSConfigure ROM_VIMSConfigure + #endif + #ifdef ROM_VIMSModeSet + #undef VIMSModeSet + #define VIMSModeSet ROM_VIMSModeSet + #endif + #ifdef ROM_VIMSModeGet + #undef VIMSModeGet + #define VIMSModeGet ROM_VIMSModeGet + #endif + #ifdef ROM_VIMSModeSafeSet + #undef VIMSModeSafeSet + #define VIMSModeSafeSet ROM_VIMSModeSafeSet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __VIMS_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog.c new file mode 100644 index 0000000..054febd --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog.c @@ -0,0 +1,41 @@ +/****************************************************************************** +* Filename: wdt.c +* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) +* Revision: 47179 +* +* Description: Driver for the Watchdog Timer. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "watchdog.h" + +// See watchdog.h for implementation diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog.h new file mode 100644 index 0000000..373fb52 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog.h @@ -0,0 +1,520 @@ +/****************************************************************************** +* Filename: wdt.h +* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) +* Revision: 49048 +* +* Description: Defines and prototypes for the Watchdog Timer. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup wdt_api +//! @{ +// +//***************************************************************************** + +#ifndef __WDT_H__ +#define __WDT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_wdt.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//***************************************************************************** +#define WATCHDOG_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WATCHDOG_LOCK_LOCKED 0x00000001 // Locked +#define WATCHDOG_LOCK_UNLOCK 0x1ACCE551 // Unlocks the Watchdog Timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and +// WDT_MIS registers. +// +//***************************************************************************** +#define WATCHDOG_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The type of interrupt that can be generated by the watchdog. +// +//***************************************************************************** +#define WATCHDOG_INT_TYPE_INT 0x00000000 +#define WATCHDOG_INT_TYPE_NMI 0x00000004 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Determines if the watchdog timer is enabled. +//! +//! This function checks to see if the watchdog timer is enabled. +//! +//! \return Returns status of Watchdog Timer: +//! - \c true : Watchdog timer is enabled. +//! - \c false : Watchdog timer is disabled. +// +//***************************************************************************** +__STATIC_INLINE bool +WatchdogRunning(void) +{ + // See if the watchdog timer module is enabled, and return. + return((HWREG(WDT_BASE + WDT_O_CTL) & WDT_CTL_INTEN) ? true : false); +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer. +//! +//! This function enables the watchdog timer counter and interrupt. +//! +//! Once enabled, the watchdog interrupt can only be disabled by a hardware reset. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogEnable(void) +{ + // Enable the watchdog timer module. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTEN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer reset. +//! +//! This function enables the capability of the watchdog timer to issue a reset +//! to the processor after a second timeout condition. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogResetEnable(void) +{ + // Enable the watchdog reset. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disables the watchdog timer reset. +//! +//! This function disables the capability of the watchdog timer to issue a +//! reset to the processor after a second timeout condition. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogResetDisable(void) +{ + // Disable the watchdog reset. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer lock mechanism. +//! +//! This function locks out write access to the watchdog timer configuration +//! registers. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogLock(void) +{ + // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK + // register causes the lock to go into effect. + HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_LOCKED; +} + +//***************************************************************************** +// +//! \brief Disables the watchdog timer lock mechanism. +//! +//! This function enables write access to the watchdog timer configuration +//! registers. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogUnlock(void) +{ + // Unlock watchdog register writes. + HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_UNLOCK; +} + +//***************************************************************************** +// +//! \brief Gets the state of the watchdog timer lock mechanism. +//! +//! This function returns the lock state of the watchdog timer registers. +//! +//! \return Returns state of lock mechanism. +//! - \c true : Watchdog timer registers are locked. +//! - \c false : Registers are not locked. +// +//***************************************************************************** +__STATIC_INLINE bool +WatchdogLockState(void) +{ + // Get the lock state. + return((HWREG(WDT_BASE + WDT_O_LOCK) == WATCHDOG_LOCK_LOCKED) ? + true : false); +} + +//***************************************************************************** +// +//! \brief Sets the watchdog timer reload value. +//! +//! This function configures the value to load into the watchdog timer when the +//! count reaches zero for the first time; if the watchdog timer is running +//! when this function is called, then the value is immediately loaded into the +//! watchdog timer counter. If the \c ui32LoadVal parameter is 0, then an +//! interrupt is immediately generated. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \param ui32LoadVal is the load value for the watchdog timer. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock(), \ref WatchdogReloadGet() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogReloadSet(uint32_t ui32LoadVal) +{ + // Set the load register. + HWREG(WDT_BASE + WDT_O_LOAD) = ui32LoadVal; +} + +//***************************************************************************** +// +//! \brief Gets the watchdog timer reload value. +//! +//! This function gets the value that is loaded into the watchdog timer when +//! the count reaches zero for the first time. +//! +//! \return None +//! +//! \sa \ref WatchdogReloadSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +WatchdogReloadGet(void) +{ + // Get the load register. + return(HWREG(WDT_BASE + WDT_O_LOAD)); +} + +//***************************************************************************** +// +//! \brief Gets the current watchdog timer value. +//! +//! This function reads the current value of the watchdog timer. +//! +//! \return Returns the current value of the watchdog timer. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +WatchdogValueGet(void) +{ + // Get the current watchdog timer register value. + return(HWREG(WDT_BASE + WDT_O_VALUE)); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! The watchdog timer interrupt must be enabled via \ref WatchdogIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! \ref WatchdogIntClear(). +//! +//! \note This function registers the standard watchdog interrupt handler. To +//! register the NMI watchdog handler, use \ref IntRegister() to register the +//! handler for the \b INT_NMI_FAULT interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! watchdog timer interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_WDT_IRQ, pfnHandler); + + // Enable the watchdog timer interrupt. + IntEnable(INT_WDT_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. This +//! function clears the handler to be called when a watchdog timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \note This function registers the standard watchdog interrupt handler. To +//! register the NMI watchdog handler, use \ref IntRegister() to register the +//! handler for the \b INT_NMI_FAULT interrupt. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntUnregister(void) +{ + // Disable the interrupt. + IntDisable(INT_WDT_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_WDT_IRQ); +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer. +//! +//! This function enables the watchdog timer interrupt by calling \ref WatchdogEnable(). +//! +//! \return None +//! +//! \sa \ref WatchdogEnable() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntEnable(void) +{ + // Enable the Watchdog interrupt. + WatchdogEnable(); +} + +//***************************************************************************** +// +//! \brief Gets the current watchdog timer interrupt status. +//! +//! This function returns the interrupt status for the watchdog timer module. +//! +//! \return Returns the interrupt status. +//! - 1 : Watchdog time-out has occurred. +//! - 0 : Watchdog time-out has not occurred. +//! +//! \sa \ref WatchdogIntClear(); +// +//***************************************************************************** +__STATIC_INLINE uint32_t +WatchdogIntStatus(void) +{ + // Return either the interrupt status or the raw interrupt status as + // requested. + return(HWREG(WDT_BASE + WDT_O_RIS)); +} + +//***************************************************************************** +// +//! \brief Clears the watchdog timer interrupt. +//! +//! The watchdog timer interrupt source is cleared, so that it no longer +//! asserts. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntClear(void) +{ + // Clear the interrupt source. + HWREG(WDT_BASE + WDT_O_ICR) = WATCHDOG_INT_TIMEOUT; +} + +//***************************************************************************** +// +//! \brief Sets the type of interrupt generated by the watchdog. +//! +//! This function sets the type of interrupt that is generated if the watchdog +//! timer expires. +//! +//! When configured to generate an NMI, the watchdog interrupt must still be +//! enabled with \ref WatchdogIntEnable(), and it must still be cleared inside the +//! NMI handler with \ref WatchdogIntClear(). +//! +//! \param ui32Type is the type of interrupt to generate. +//! - \ref WATCHDOG_INT_TYPE_INT : Generate a standard interrupt (default). +//! - \ref WATCHDOG_INT_TYPE_NMI : Generate a non-maskable interrupt (NMI). +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntTypeSet(uint32_t ui32Type) +{ + // Check the arguments. + ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) || + (ui32Type == WATCHDOG_INT_TYPE_NMI)); + + // Set the interrupt type. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTTYPE_BITN) = (ui32Type == WATCHDOG_INT_TYPE_INT)? 0 : 1; +} + +//***************************************************************************** +// +//! \brief Enables stalling of the watchdog timer during debug events. +//! +//! This function allows the watchdog timer to stop counting when the processor +//! is stopped by the debugger. By doing so, the watchdog is prevented from +//! expiring and resetting the system (if reset is enabled). The watchdog instead expires +//! after the appropriate number of processor cycles have been executed while +//! debugging (or at the appropriate time after the processor has been +//! restarted). +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogStallEnable(void) +{ + // Enable timer stalling. + HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disables stalling of the watchdog timer during debug events. +//! +//! This function disables the debug mode stall of the watchdog timer. By +//! doing so, the watchdog timer continues to count regardless of the processor +//! debug state. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogStallDisable(void) +{ + // Disable timer stalling. + HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 0; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __WDT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog_doc.h new file mode 100644 index 0000000..877bab7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog_doc.h @@ -0,0 +1,121 @@ +/****************************************************************************** +* Filename: watchdog_doc.h +* Revised: 2018-02-09 15:45:36 +0100 (Fri, 09 Feb 2018) +* Revision: 51470 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup wdt_api +//! @{ +//! \section sec_wdt Introduction +//! +//! The Watchdog Timer (WDT) allows the application to regain control if the system stalls due to +//! unexpected software behavior. The WDT can generate a normal interrupt or a non-maskable interrupt +//! on the first time-out and a system reset on the following time-out if the application fails to +//! restart the WDT. +//! +//! WDT has the following features: +//! - 32-bit down counter with a configurable load register. +//! - Configurable interrupt generation logic with interrupt masking and optional NMI function. +//! - Optional reset generation. +//! - Register protection from runaway software (lock). +//! - User-enabled stalling when the system CPU asserts the CPU Halt flag during debug. +//! +//! The WDT runs at system HF clock divided by 32; however, when in powerdown it runs at +//! LF clock (32 kHz) - if the LF clock to the MCU domain is enabled. +//! +//! If application does not restart the WDT, using \ref WatchdogIntClear(), before a time-out: +//! - At the first time-out the WDT asserts the interrupt, reloads the 32-bit counter with the load +//! value, and resumes counting down from that value. +//! - If the WDT counts down to zero again before the application clears the interrupt, and the +//! reset signal has been enabled, the WDT asserts its reset signal to the system. +//! +//! \note By default, a "warm reset" triggers a pin reset and thus reboots the device. +//! +//! A reset caused by the WDT can be detected as a "warm reset" using \ref SysCtrlResetSourceGet(). +//! However, it is not possible to detect which of the warm reset sources that caused the reset. +//! +//! Typical use case: +//! - Use \ref WatchdogIntTypeSet() to select either standard interrupt or non-maskable interrupt on +//! first time-out. +//! - The application must implement an interrupt handler for the selected interrupt type. If +//! application uses the \e static vector table (see startup_.c) the interrupt +//! handlers for standard interrupt and non-maskable interrupt are named WatchdogIntHandler() +//! and NmiSR() respectively. For more information about \e static and \e dynamic vector table, +//! see \ref sec_interrupt_table. +//! - Use \ref WatchdogResetEnable() to enable reset on second time-out. +//! - Use \ref WatchdogReloadSet() to set (re)load value of the counter. +//! - Use \ref WatchdogEnable() to start the WDT counter. The WDT counts down from the load value. +//! - Use \ref WatchdogLock() to lock WDT configuration to prevent unintended re-configuration. +//! - Application must use \ref WatchdogIntClear() to restart the counter before WDT times out. +//! - If application does not restart the counter before it reaches zero (times out) the WDT asserts +//! the selected type of interrupt, reloads the counter, and starts counting down again. +//! - The interrupt handler triggered by the first time-out can be used to log debug information +//! or try to enter a safe "pre-reset" state in order to have a more graceful reset when the WDT +//! times out the second time. +//! - It is \b not recommended that the WDT interrupt handler clears the WDT interrupt and thus +//! reloads the WDT counter. This means that the WDT interrupt handler never returns. +//! - If the application does not clear the WDT interrupt and the WDT times out when the interrupt +//! is still asserted then WDT triggers a reset (if enabled). +//! +//! \section sec_wdt_api API +//! +//! The API functions can be grouped like this: +//! +//! Watchdog configuration: +//! - \ref WatchdogIntTypeSet() +//! - \ref WatchdogResetEnable() +//! - \ref WatchdogResetDisable() +//! - \ref WatchdogReloadSet() +//! - \ref WatchdogEnable() +//! +//! Status: +//! - \ref WatchdogRunning() +//! - \ref WatchdogValueGet() +//! - \ref WatchdogReloadGet() +//! - \ref WatchdogIntStatus() +//! +//! Interrupt configuration: +//! - \ref WatchdogIntEnable() +//! - \ref WatchdogIntClear() +//! - \ref WatchdogIntRegister() +//! - \ref WatchdogIntUnregister() +//! +//! Register protection: +//! - \ref WatchdogLock() +//! - \ref WatchdogLockState() +//! - \ref WatchdogUnlock() +//! +//! Stall configuration for debugging: +//! - \ref WatchdogStallDisable() +//! - \ref WatchdogStallEnable() +//! +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/asmdefs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/asmdefs.h new file mode 100644 index 0000000..1768b4c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/asmdefs.h @@ -0,0 +1,151 @@ +/****************************************************************************** +* Filename: asmdefs.h +* Revised: 2015-06-05 14:39:10 +0200 (Fri, 05 Jun 2015) +* Revision: 43803 +* +* Description: Macros to allow assembly code be portable among tool chains. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef __IAR_SYSTEMS_ICC__ + +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) +#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) + +// +// Assembler mnemonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data + +#endif // __IAR_SYSTEMS_ICC__ + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#if defined(__GNUC__) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler mnemonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // __GNUC__ + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#if defined(__CC_ARM) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 +#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 + +// +// Assembler mnemonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ + +#endif // __CC_ARM + + +#endif // __ASMDEF_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi.h new file mode 100644 index 0000000..d55fe0f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi.h @@ -0,0 +1,1182 @@ +/****************************************************************************** +* Filename: hw_adi.h +* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) +* Revision: 42365 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_H__ +#define __HW_ADI_H__ + +//***************************************************************************** +// +// This file contains macros for controlling the ADI master and +// accessing ADI slave registers via the ADI Master. +// There are 3 categories of macros in this file: +// - macros that provide an offset to a register +// located within the DDI Master itself. +// - macros that define bits or bitfields +// within the DDI Master Registers. +// - macros that provide an "instruction offset" +// that are used when accessing a ADI Slave. +// +// The macros that that provide ADI Master register offsets and +// define bits and bitfields for those registers are the typical +// macros that appear in most hw_.h header files. In +// the following example ADI_O_SLAVECONF is a macro for a +// register offset and ADI_SLAVECONF_WAITFORACK is a macro for +// a bit in that register. This example code will set the WAITFORACK +// bit in register ADI_O_SLAVECONF of the ADI Master. (Note: this +// access the Master not the Slave). +// +// HWREG(ADI3_BASE + ADI_O_SLAVECONF) |= ADI_SLAVECONF_WAITFORACK; +// +// The "instruction offset" macros are used to pass an instruction to +// the ADI Master when accessing ADI slave registers. These macros are +// only used when accessing ADI Slave Registers. (Remember ADI +// Master Registers are accessed normally). +// +// The instructions supported when accessing an ADI Slave Register follow: +// - Direct Access to an ADI Slave register. I.e. read or +// write the register. +// - Set the specified bits in a ADI Slave register. +// - Clear the specified bits in a ADI Slave register. +// - Mask write of 4 bits to the a ADI Slave register. +// - Mask write of 8 bits to the a ADI Slave register. +// - Mask write of 16 bits to the a ADI Slave register. +// +// Note: only the "Direct Access" offset should be used when reading +// a ADI Slave register. Only 4-bit reads are supported and 8 bits write are +// supported natively. If accessing wider bitfields, the read/write operation +// will be spread out over a number of transactions. This is hidden for the +// user, but can potentially be very timeconsuming. Especially of running +// on a slow clock. +// +// The generic format of using these macros for a read follows: +// // Read low 8-bits in ADI_SLAVE_OFF +// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); +// +// // Read high 8-bits in ADI_SLAVE_OFF (data[31:16]) +// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); +// +// Notes: In the above example: +// - ADI_MASTER_BASE is the base address of the ADI Master defined +// in the hw_memmap.h header file. +// - ADI_SLAVE_OFF is the ADI Slave offset defined in the +// hw_.h header file (e.g. hw_adi_3_refsys_top.h for the refsys +// module). +// - ADI_O_DIR is the "instruction offset" macro defined in this +// file that specifies the Direct Access instruction. +// +// Writes can use any of the "instruction macros". +// The following examples do a "direct write" to an ADI Slave register +// ADI_SLAVE_OFF using different size operands: +// +// // ---------- DIRECT WRITES ---------- +// // Write 32-bits aligned +// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x12345678; +// +// // Write 16-bits aligned to high 16-bits then low 16-bits +// // Add 2 to get to high 16-bits. +// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0xabcd; +// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0xef01; +// +// // Write each byte at ADI_SLAVE_OFF, one at a time. +// // Add 1,2,or 3 to get to bytes 1,2, or 3. +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x33; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 1) = 0x44; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0x55; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 3) = 0x66; +// +// // ---------- SET/CLR ---------- +// The set and clear functions behave similarly to eachother. Each +// can be performed on an 8-, 16-, or 32-bit operand. +// Examples follow: +// // Set all odd bits in a 32-bit words +// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_SET) = 0xaaaaaaaa; +// +// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand +// HWREG(DDI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_CLR) = 0x00ff0000; +// +// // Set even bits in byte 2 (data[23:16]) using 8-bit operand +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + 2 + ADI_O_CLR) = 0x55; +// +// // ---------- MASKED WRITES ---------- +// The mask writes are a bit different. They operate on nibbles, +// bytes, and 16-bit elements. Two operands are required; a 'mask' +// and 'data'; The operands are concatenated and written to the master. +// e.g. the mask and data are combined as follows for a 16 bit masked +// write: +// (mask << 16) | data; +// Examples follow: +// +// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). +// // Byte write is needed. +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_MASK4B01) = 0xf7; +// +// // Do an 4 bit masked write of 4 to data[7:4]). +// // Add 1 for next nibble +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + ADI_O_MASK4B01 + 1) = 0xf4; +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the ADI master instruction offsets. +// +//***************************************************************************** +#define ADI_O_DIR 0x00000000 // Offset for the direct access + // instruction +#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. +#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. +#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). + // Bits 7:4 are mask. Bits 3:0 are data. + // Requires 'byte' write. +#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). Bits 15:8 are + // mask. Bits 7:0 are data. Requires + // 'short' write. +#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). Bits 31:16 + // are mask. Bits 15:0 are data. + // Requires 'long' write. + +//***************************************************************************** +// +// The following are defines for the ADI register offsets. +// +//***************************************************************************** +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVESTAT register. +// +//***************************************************************************** +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ + // signal. Writing 0 to this bit + // forces a sync with slave, + // ensuring that req will be 0. It + // is recommended to write 0 to + // this register before power down + // of the master. +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK + // signal +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVECONF register. +// +//***************************************************************************** +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer + // accessible when this bit is set. + // (unless sticky_bit_overwrite is + // asserted on top module) +#define ADI_SLAVECONF_CONFLOCK_M \ + 0x00000080 +#define ADI_SLAVECONF_CONFLOCK_S 7 +#define ADI_SLAVECONF_WAITFORACK \ + 0x00000004 // A transaction on the ADI + // interface does not end until ack + // has been received from the slave + // when this bit is set. + +#define ADI_SLAVECONF_WAITFORACK_M \ + 0x00000004 +#define ADI_SLAVECONF_WAITFORACK_S 2 +#define ADI_SLAVECONF_ADICLKSPEED_M \ + 0x00000003 // Sets the period of an ADI + // transactions. All transactions + // takes an even number of clock + // cycles,- ADI clock rising edge + // occurs in the middle of the + // period. Data and ctrl to slave + // is set up in beginning of cycle, + // and data from slave is read in + // after the transaction 00: An ADI + // transaction takes 2 master clock + // cyclkes 01: An ADI transaction + // takes 4 master clock cycles 10: + // And ADI Transaction takes 8 + // master clock cycles 11: An ADI + // transaction takes 16 master + // clock cycles + +#define ADI_SLAVECONF_ADICLKSPEED_S 0 + +//***************************************************************************** +// +// The following are defines pseudo-magic numbers that should go away. +// New code should not use these registers and old code should be ported +// to not use these. +// +//***************************************************************************** +#define ADI_O_DIR03 0x00000000 // Direct access for adi byte + // offsets 0 to 3 +#define ADI_O_DIR47 0x00000004 // Direct access for adi byte + // offsets 4 to 7 +#define ADI_O_DIR811 0x00000008 // Direct access for adi byte + // offsets 8 to 11 +#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte + // offsets 12 to 15 +#define ADI_O_SET03 0x00000010 // Set register for ADI byte + // offsets 0 to 3 +#define ADI_O_SET47 0x00000014 // Set register for ADI byte + // offsets 4 to 7 +#define ADI_O_SET811 0x00000018 // Set register for ADI byte + // offsets 8 to 11 +#define ADI_O_SET1215 0x0000001C // Set register for ADI byte + // offsets 12 to 15 +#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte + // offsets 0 to 3 +#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte + // offsets 4 to 7 +#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte + // offsets 8 to 11 +#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte + // offsets 12 to 15 +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration + // register +#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI + // Registers at byte offsets 14 and + // 15 +#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI + // Registers at byte offsets 14 and + // 15 +#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI + // Registers at byte offsets 14 and + // 15 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR03 register. +// +//***************************************************************************** +#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 +#define ADI_DIR03_B3_S 24 +#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 +#define ADI_DIR03_B2_S 16 +#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 +#define ADI_DIR03_B1_S 8 +#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 +#define ADI_DIR03_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR47 register. +// +//***************************************************************************** +#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 +#define ADI_DIR47_B3_S 24 +#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 +#define ADI_DIR47_B2_S 16 +#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 +#define ADI_DIR47_B1_S 8 +#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 +#define ADI_DIR47_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR811 register. +// +//***************************************************************************** +#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register + // 11 +#define ADI_DIR811_B3_S 24 +#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register + // 10 +#define ADI_DIR811_B2_S 16 +#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 +#define ADI_DIR811_B1_S 8 +#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 +#define ADI_DIR811_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR1215 register. +// +//***************************************************************************** +#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register + // 15 +#define ADI_DIR1215_B3_S 24 +#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register + // 14 +#define ADI_DIR1215_B2_S 16 +#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register + // 13 +#define ADI_DIR1215_B1_S 8 +#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register + // 12 +#define ADI_DIR1215_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET03 register. +// +//***************************************************************************** +#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 3. Read returns 0. +#define ADI_SET03_S3_S 24 +#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 2. Read returns 0. +#define ADI_SET03_S2_S 16 +#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 1. Read returns 0. +#define ADI_SET03_S1_S 8 +#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 0. Read returns 0. +#define ADI_SET03_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET47 register. +// +//***************************************************************************** +#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 7. Read returns 0. +#define ADI_SET47_S3_S 24 +#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 6. Read returns 0. +#define ADI_SET47_S2_S 16 +#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 5. Read returns 0. +#define ADI_SET47_S1_S 8 +#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 4. Read returns 0. +#define ADI_SET47_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET811 register. +// +//***************************************************************************** +#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 11. Read returns 0. +#define ADI_SET811_S3_S 24 +#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 10. Read returns 0. +#define ADI_SET811_S2_S 16 +#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 9. Read returns 0. +#define ADI_SET811_S1_S 8 +#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 8. Read returns 0. +#define ADI_SET811_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET1215 register. +// +//***************************************************************************** +#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 15. Read returns 0. +#define ADI_SET1215_S3_S 24 +#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 14. Read returns 0. +#define ADI_SET1215_S2_S 16 +#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 13. Read returns 0. +#define ADI_SET1215_S1_S 8 +#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 12. Read returns 0. +#define ADI_SET1215_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR03 register. +// +//***************************************************************************** +#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 3 +#define ADI_CLR03_S3_S 24 +#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 2 +#define ADI_CLR03_S2_S 16 +#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 1 +#define ADI_CLR03_S1_S 8 +#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 0 +#define ADI_CLR03_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR47 register. +// +//***************************************************************************** +#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 7 +#define ADI_CLR47_S3_S 24 +#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 6 +#define ADI_CLR47_S2_S 16 +#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 5 +#define ADI_CLR47_S1_S 8 +#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 4 +#define ADI_CLR47_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR811 register. +// +//***************************************************************************** +#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 11 +#define ADI_CLR811_S3_S 24 +#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 10 +#define ADI_CLR811_S2_S 16 +#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 9 +#define ADI_CLR811_S1_S 8 +#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 8 +#define ADI_CLR811_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR1215 register. +// +//***************************************************************************** +#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 15 +#define ADI_CLR1215_S3_S 24 +#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 14 +#define ADI_CLR1215_S2_S 16 +#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 13 +#define ADI_CLR1215_S1_S 8 +#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 12 +#define ADI_CLR1215_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVESTAT register. +// +//***************************************************************************** +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ + // signal. Writing 0 to this bit + // forces a sync with slave, + // ensuring that req will be 0. It + // is recommended to write 0 to + // this register before power down + // of the master. +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK + // signal +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVECONF register. +// +//***************************************************************************** +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer + // accessible when this bit is set. + // (unless sticky_bit_overwrite is + // asserted on top module) +#define ADI_SLAVECONF_CONFLOCK_M \ + 0x00000080 +#define ADI_SLAVECONF_CONFLOCK_S 7 +#define ADI_SLAVECONF_WAITFORACK \ + 0x00000004 // A transaction on the ADI + // interface does not end until ack + // has been received from the slave + // when this bit is set. + +#define ADI_SLAVECONF_WAITFORACK_M \ + 0x00000004 +#define ADI_SLAVECONF_WAITFORACK_S 2 +#define ADI_SLAVECONF_ADICLKSPEED_M \ + 0x00000003 // Sets the period of an ADI + // transactions. All transactions + // takes an even number of clock + // cycles,- ADI clock rising edge + // occurs in the middle of the + // period. Data and ctrl to slave + // is set up in beginning of cycle, + // and data from slave is read in + // after the transaction 00: An ADI + // transaction takes 2 master clock + // cyclkes 01: An ADI transaction + // takes 4 master clock cycles 10: + // And ADI Transaction takes 8 + // master clock cycles 11: An ADI + // transaction takes 16 master + // clock cycles + +#define ADI_SLAVECONF_ADICLKSPEED_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B01 register. +// +//***************************************************************************** +#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 1 +#define ADI_MASK4B01_M1H_S 28 +#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 1, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B01_D1H_S 24 +#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 1 +#define ADI_MASK4B01_M1L_S 20 +#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 1, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B01_D1L_S 16 +#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 0 +#define ADI_MASK4B01_M0H_S 12 +#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 0, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B01_D0H_S 8 +#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 0 +#define ADI_MASK4B01_M0L_S 4 +#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 0, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B01_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B23 register. +// +//***************************************************************************** +#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 3 +#define ADI_MASK4B23_M1H_S 28 +#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 3, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B23_D1H_S 24 +#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 3 +#define ADI_MASK4B23_M1L_S 20 +#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 3, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B23_D1L_S 16 +#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 2 +#define ADI_MASK4B23_M0H_S 12 +#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 2, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B23_D0H_S 8 +#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 2 +#define ADI_MASK4B23_M0L_S 4 +#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 2, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B23_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B45 register. +// +//***************************************************************************** +#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 5 +#define ADI_MASK4B45_M1H_S 28 +#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 5, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B45_D1H_S 24 +#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 5 +#define ADI_MASK4B45_M1L_S 20 +#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 5, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B45_D1L_S 16 +#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 4 +#define ADI_MASK4B45_M0H_S 12 +#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 4, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B45_D0H_S 8 +#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 4 +#define ADI_MASK4B45_M0L_S 4 +#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 4, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B45_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B67 register. +// +//***************************************************************************** +#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 7 +#define ADI_MASK4B67_M1H_S 28 +#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 7, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B67_D1H_S 24 +#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 7 +#define ADI_MASK4B67_M1L_S 20 +#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 7, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B67_D1L_S 16 +#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 6 +#define ADI_MASK4B67_M0H_S 12 +#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 6, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B67_D0H_S 8 +#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 6 +#define ADI_MASK4B67_M0L_S 4 +#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 6, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B67_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B89 register. +// +//***************************************************************************** +#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 9 +#define ADI_MASK4B89_M1H_S 28 +#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 9, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B89_D1H_S 24 +#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 9 +#define ADI_MASK4B89_M1L_S 20 +#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 9, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B89_D1L_S 16 +#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 8 +#define ADI_MASK4B89_M0H_S 12 +#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 8, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B89_D0H_S 8 +#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 8 +#define ADI_MASK4B89_M0L_S 4 +#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 8, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B89_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1011 register. +// +//***************************************************************************** +#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 11 +#define ADI_MASK4B1011_M1H_S 28 +#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 11, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1011_D1H_S 24 +#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 11 +#define ADI_MASK4B1011_M1L_S 20 +#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 11, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1011_D1L_S 16 +#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 10 +#define ADI_MASK4B1011_M0H_S 12 +#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 10, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1011_D0H_S 8 +#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 10 +#define ADI_MASK4B1011_M0L_S 4 +#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 10, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1011_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1213 register. +// +//***************************************************************************** +#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 13 +#define ADI_MASK4B1213_M1H_S 28 +#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 13, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1213_D1H_S 24 +#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 13 +#define ADI_MASK4B1213_M1L_S 20 +#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 13, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1213_D1L_S 16 +#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 12 +#define ADI_MASK4B1213_M0H_S 12 +#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 12, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1213_D0H_S 8 +#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 12 +#define ADI_MASK4B1213_M0L_S 4 +#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 12, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1213_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1415 register. +// +//***************************************************************************** +#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 15 +#define ADI_MASK4B1415_M1H_S 28 +#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 15, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1415_D1H_S 24 +#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 15 +#define ADI_MASK4B1415_M1L_S 20 +#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 15, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1415_D1L_S 16 +#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 14 +#define ADI_MASK4B1415_M0H_S 12 +#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 14, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1415_D0H_S 8 +#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 14 +#define ADI_MASK4B1415_M0L_S 4 +#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 14, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1415_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B01 register. +// +//***************************************************************************** +#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 +#define ADI_MASK8B01_M1_S 24 +#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B01_D1_S 16 +#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 +#define ADI_MASK8B01_M0_S 8 +#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B01_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B23 register. +// +//***************************************************************************** +#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 +#define ADI_MASK8B23_M1_S 24 +#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B23_D1_S 16 +#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 +#define ADI_MASK8B23_M0_S 8 +#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B23_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B45 register. +// +//***************************************************************************** +#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 +#define ADI_MASK8B45_M1_S 24 +#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B45_D1_S 16 +#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 +#define ADI_MASK8B45_M0_S 8 +#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B45_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B67 register. +// +//***************************************************************************** +#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 +#define ADI_MASK8B67_M1_S 24 +#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B67_D1_S 16 +#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 +#define ADI_MASK8B67_M0_S 8 +#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B67_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B89 register. +// +//***************************************************************************** +#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 +#define ADI_MASK8B89_M1_S 24 +#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B89_D1_S 16 +#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 +#define ADI_MASK8B89_M0_S 8 +#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B89_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1011 register. +// +//***************************************************************************** +#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 +#define ADI_MASK8B1011_M1_S 24 +#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1011_D1_S 16 +#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 +#define ADI_MASK8B1011_M0_S 8 +#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1011_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1213 register. +// +//***************************************************************************** +#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 +#define ADI_MASK8B1213_M1_S 24 +#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1213_D1_S 16 +#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 +#define ADI_MASK8B1213_M0_S 8 +#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1213_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1415 register. +// +//***************************************************************************** +#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 +#define ADI_MASK8B1415_M1_S 24 +#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1415_D1_S 16 +#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 +#define ADI_MASK8B1415_M0_S 8 +#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1415_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B01 register. +// +//***************************************************************************** +#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 +#define ADI_MASK16B01_M_S 16 +#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at + // offsets 0 and 1, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B01_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B23 register. +// +//***************************************************************************** +#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 +#define ADI_MASK16B23_M_S 16 +#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at + // offsets 2 and 3, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B23_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B45 register. +// +//***************************************************************************** +#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 +#define ADI_MASK16B45_M_S 16 +#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at + // offsets 4 and 5, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B45_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B67 register. +// +//***************************************************************************** +#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 +#define ADI_MASK16B67_M_S 16 +#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at + // offsets 6 and 7, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B67_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B89 register. +// +//***************************************************************************** +#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 +#define ADI_MASK16B89_M_S 16 +#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at + // offsets 8 and 9, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B89_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1011 register. +// +//***************************************************************************** +#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 +#define ADI_MASK16B1011_M_S 16 +#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at + // offsets 10 and 11, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1011_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1213 register. +// +//***************************************************************************** +#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 +#define ADI_MASK16B1213_M_S 16 +#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at + // offsets 12 and 13, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1213_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1415 register. +// +//***************************************************************************** +#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 +#define ADI_MASK16B1415_M_S 16 +#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at + // offsets 14 and 15, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1415_D_S 0 + +#endif // __HW_ADI_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_2_refsys.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_2_refsys.h new file mode 100644 index 0000000..72ae2eb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_2_refsys.h @@ -0,0 +1,362 @@ +/****************************************************************************** +* Filename: hw_adi_2_refsys_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_2_REFSYS_H__ +#define __HW_ADI_2_REFSYS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_2_REFSYS component +// +//***************************************************************************** +// Internal +#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_REFSYSCTL0 +// +//***************************************************************************** +// Field: [4:0] TRIM_IREF +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL0 +// +//***************************************************************************** +// Field: [7:4] VTRIM_UDIG +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 + +// Field: [3:0] VTRIM_BOD +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL1 +// +//***************************************************************************** +// Field: [7:4] VTRIM_COARSE +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 + +// Field: [3:0] VTRIM_DIG +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL2 +// +//***************************************************************************** +// Field: [2:0] VTRIM_DELTA +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL3 +// +//***************************************************************************** +// Field: [7:6] ITRIM_DIGLDO_LOAD +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 + +// Field: [5:3] ITRIM_DIGLDO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BIAS_120P Internal. Only to be used through TI provided API. +// BIAS_100P Internal. Only to be used through TI provided API. +// BIAS_80P Internal. Only to be used through TI provided API. +// BIAS_60P Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 + +// Field: [2:0] ITRIM_UDIGLDO +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL4 +// +//***************************************************************************** +// Field: [6:5] UDIG_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 + +// Field: [4:2] DIG_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 + +// Field: [1] BIAS_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 + +// Field: [0] UDIG_LDO_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL5 +// +//***************************************************************************** +// Field: [3] IMON_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 + +// Field: [2:0] TESTSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDD_AON Internal. Only to be used through TI provided API. +// VREF_AMP Internal. Only to be used through TI provided API. +// ITEST Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL0 +// +//***************************************************************************** +// Field: [7] FILTER_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 + +// Field: [6:5] BIAS_RECHARGE_DLY +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// MIN_DLY_X8 Internal. Only to be used through TI provided API. +// MIN_DLY_X4 Internal. Only to be used through TI provided API. +// MIN_DLY_X2 Internal. Only to be used through TI provided API. +// MIN_DLY_X1 Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 + +// Field: [4:3] TUNE_CAP +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SHIFT_M108 Internal. Only to be used through TI provided API. +// SHIFT_M70 Internal. Only to be used through TI provided API. +// SHIFT_M35 Internal. Only to be used through TI provided API. +// SHIFT_0 Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 + +// Field: [2:1] SERIES_CAP +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 + +// Field: [0] DIV3_BYPASS +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// HPOSC_2520MHZ Internal. Only to be used through TI provided API. +// HPOSC_840MHZ Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL1 +// +//***************************************************************************** +// Field: [5] BIAS_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 + +// Field: [4] PWRDET_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 + +// Field: [3:0] BIAS_RES_SET +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL2 +// +//***************************************************************************** +// Field: [7] BIAS_HOLD_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 + +// Field: [6] TESTMUX_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 + +// Field: [5:4] ATEST_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 + +// Field: [3:0] CURRMIRR_RATIO +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 + + +#endif // __ADI_2_REFSYS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_3_refsys.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_3_refsys.h new file mode 100644 index 0000000..deedeba --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_3_refsys.h @@ -0,0 +1,481 @@ +/****************************************************************************** +* Filename: hw_adi_3_refsys_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_3_REFSYS_H__ +#define __HW_ADI_3_REFSYS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_3_REFSYS component +// +//***************************************************************************** +// Analog Test Control +#define ADI_3_REFSYS_O_SPARE0 0x00000001 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 + +// DCDC Control 0 +#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 + +// DCDC Control 1 +#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 + +// DCDC Control 2 +#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 + +// DCDC Control 3 +#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 + +// Internal +#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A + +// Internal +#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_SPARE0 +// +//***************************************************************************** +// Field: [7:0] SPARE0 +// +// Software should not rely on the value of a reserved. Writing any other value +// than the reset value may result in undefined behavior. +#define ADI_3_REFSYS_SPARE0_SPARE0_W 8 +#define ADI_3_REFSYS_SPARE0_SPARE0_M 0x000000FF +#define ADI_3_REFSYS_SPARE0_SPARE0_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL0 +// +//***************************************************************************** +// Field: [7:0] TESTCTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BMCOMPOUT Internal. Only to be used through TI provided API. +// VTEMP Internal. Only to be used through TI provided API. +// VREF0P8V Internal. Only to be used through TI provided API. +// VBGUNBUFF Internal. Only to be used through TI provided API. +// VBG Internal. Only to be used through TI provided API. +// IREF4U Internal. Only to be used through TI provided API. +// IVREF4U Internal. Only to be used through TI provided API. +// IPTAT2U Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL1 +// +//***************************************************************************** +// Field: [7:3] TRIM_VDDS_BOD +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// POS_27 Internal. Only to be used through TI provided API. +// POS_26 Internal. Only to be used through TI provided API. +// POS_25 Internal. Only to be used through TI provided API. +// POS_24 Internal. Only to be used through TI provided API. +// POS_31 Internal. Only to be used through TI provided API. +// POS_30 Internal. Only to be used through TI provided API. +// POS_29 Internal. Only to be used through TI provided API. +// POS_28 Internal. Only to be used through TI provided API. +// POS_19 Internal. Only to be used through TI provided API. +// POS_18 Internal. Only to be used through TI provided API. +// POS_17 Internal. Only to be used through TI provided API. +// POS_16 Internal. Only to be used through TI provided API. +// POS_23 Internal. Only to be used through TI provided API. +// POS_22 Internal. Only to be used through TI provided API. +// POS_21 Internal. Only to be used through TI provided API. +// POS_20 Internal. Only to be used through TI provided API. +// POS_11 Internal. Only to be used through TI provided API. +// POS_10 Internal. Only to be used through TI provided API. +// POS_9 Internal. Only to be used through TI provided API. +// POS_8 Internal. Only to be used through TI provided API. +// POS_15 Internal. Only to be used through TI provided API. +// POS_14 Internal. Only to be used through TI provided API. +// POS_13 Internal. Only to be used through TI provided API. +// POS_12 Internal. Only to be used through TI provided API. +// POS_3 Internal. Only to be used through TI provided API. +// POS_2 Internal. Only to be used through TI provided API. +// POS_1 Internal. Only to be used through TI provided API. +// POS_0 Internal. Only to be used through TI provided API. +// POS_7 Internal. Only to be used through TI provided API. +// POS_6 Internal. Only to be used through TI provided API. +// POS_5 Internal. Only to be used through TI provided API. +// POS_4 Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 + +// Field: [2] BATMON_COMP_TEST_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 + +// Field: [1:0] TESTCTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// IPTAT1U Internal. Only to be used through TI provided API. +// BMCOMPIN Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL2 +// +//***************************************************************************** +// Field: [7:4] TRIM_VREF +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 + +// Field: [1:0] TRIM_TSENSE +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL3 +// +//***************************************************************************** +// Field: [7] BOD_BG_TRIM_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 + +// Field: [6] VTEMP_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 + +// Field: [5:0] TRIM_VBG +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL0 +// +//***************************************************************************** +// Field: [7:5] GLDO_ISRC +// +// Set charge and re-charge current level. +// 2's complement encoding. +// +// 0x0: Default 11mA. +// 0x3: Max 15mA. +// 0x4: Max 5mA +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 + +// Field: [4:0] VDDR_TRIM +// +// Set the VDDR voltage. +// Proprietary encoding. +// +// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. +// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. +// Step size = 16mV +// +// 0x00: Default, about 1.63V. +// 0x05: Typical voltage after trim voltage 1.71V. +// 0x15: Max voltage 1.96V. +// 0x16: Min voltage 1.47V. +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL1 +// +//***************************************************************************** +// Field: [7:6] IPTAT_TRIM +// +// Trim GLDO bias current. +// Proprietary encoding. +// +// 0x0: Default +// 0x1: Increase GLDO bias by 1.3x. +// 0x2: Increase GLDO bias by 1.6x. +// 0x3: Decrease GLDO bias by 0.7x. +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 + +// Field: [5] VDDR_OK_HYST +// +// Increase the hysteresis for when VDDR is considered ok. +// +// 0: Hysteresis = 60mV +// 1: Hysteresis = 70mV +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 + +// Field: [4:0] VDDR_TRIM_SLEEP +// +// Set the min VDDR voltage threshold during sleep mode. +// Proprietary encoding. +// +// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. +// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. +// Step size = 16mV +// +// 0x00: Default, about 1.63V. +// 0x19: Typical voltage after trim voltage 1.52V. +// 0x15: Max voltage 1.96V. +// 0x16: Min voltage 1.47V. +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL2 +// +//***************************************************************************** +// Field: [6] TURNON_EA_SW +// +// Turn on erroramp switch +// +// 0: Erroramp Off (Default) +// 1: Erroramp On. Turns on GLDO error amp switch. +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 + +// Field: [5] TEST_VDDR +// +// Connect VDDR to ATEST bus +// +// 0: Not connected. +// 1: Connected +// +// Set TESTSEL = 0x0 first before setting this bit. +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 + +// Field: [4] BIAS_DIS +// +// Disable dummy bias current. +// +// 0: Dummy bias current on (Default) +// 1: Dummy bias current off +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 + +// Field: [3:0] TESTSEL +// +// Select signal for test bus, one hot. +// ENUMs: +// VDDROK VDDR_OK connected to test bus. +// IB1U 1uA bias current connected to test bus. +// PASSGATE Pass transistor gate voltage connected to test +// bus. +// ERRAMP_OUT Error amp output voltage connected to test bus. +// NC No signal connected to test bus. +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL4 +// +//***************************************************************************** +// Field: [7:6] DEADTIME_TRIM +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 + +// Field: [5:3] LOW_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 + +// Field: [2:0] HIGH_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL5 +// +//***************************************************************************** +// Field: [5] TESTN +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 + +// Field: [4] TESTP +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 + +// Field: [3] DITHER_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 + +// Field: [2:0] IPEAK +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 + + +#endif // __ADI_3_REFSYS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_4_aux.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_4_aux.h new file mode 100644 index 0000000..af14ac4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_4_aux.h @@ -0,0 +1,490 @@ +/****************************************************************************** +* Filename: hw_adi_4_aux_h +* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) +* Revision: 48904 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_4_AUX_H__ +#define __HW_ADI_4_AUX_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_4_AUX component +// +//***************************************************************************** +// Internal +#define ADI_4_AUX_O_MUX0 0x00000000 + +// Internal +#define ADI_4_AUX_O_MUX1 0x00000001 + +// Internal +#define ADI_4_AUX_O_MUX2 0x00000002 + +// Internal +#define ADI_4_AUX_O_MUX3 0x00000003 + +// Current Source +#define ADI_4_AUX_O_ISRC 0x00000004 + +// Comparator +#define ADI_4_AUX_O_COMP 0x00000005 + +// Internal +#define ADI_4_AUX_O_MUX4 0x00000007 + +// ADC Control 0 +#define ADI_4_AUX_O_ADC0 0x00000008 + +// ADC Control 1 +#define ADI_4_AUX_O_ADC1 0x00000009 + +// ADC Reference 0 +#define ADI_4_AUX_O_ADCREF0 0x0000000A + +// ADC Reference 1 +#define ADI_4_AUX_O_ADCREF1 0x0000000B + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX0 +// +//***************************************************************************** +// Field: [3:0] COMPA_REF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// ADCVREFP Internal. Only to be used through TI provided API. +// VDDS Internal. Only to be used through TI provided API. +// VSS Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX0_COMPA_REF_W 4 +#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F +#define ADI_4_AUX_MUX0_COMPA_REF_S 0 +#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008 +#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004 +#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002 +#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX1 +// +//***************************************************************************** +// Field: [7:0] COMPA_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO0 Internal. Only to be used through TI provided API. +// AUXIO1 Internal. Only to be used through TI provided API. +// AUXIO2 Internal. Only to be used through TI provided API. +// AUXIO3 Internal. Only to be used through TI provided API. +// AUXIO4 Internal. Only to be used through TI provided API. +// AUXIO5 Internal. Only to be used through TI provided API. +// AUXIO6 Internal. Only to be used through TI provided API. +// AUXIO7 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX1_COMPA_IN_W 8 +#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF +#define ADI_4_AUX_MUX1_COMPA_IN_S 0 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX2 +// +//***************************************************************************** +// Field: [7:3] ADCCOMPB_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDDS Internal. Only to be used through TI provided API. +// VSS Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// ATEST1 Internal. Only to be used through TI provided API. +// ATEST0 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000 + +// Field: [2:0] COMPB_REF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDDS Internal. Only to be used through TI provided API. +// VSS Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX2_COMPB_REF_W 3 +#define ADI_4_AUX_MUX2_COMPB_REF_M 0x00000007 +#define ADI_4_AUX_MUX2_COMPB_REF_S 0 +#define ADI_4_AUX_MUX2_COMPB_REF_VDDS 0x00000004 +#define ADI_4_AUX_MUX2_COMPB_REF_VSS 0x00000002 +#define ADI_4_AUX_MUX2_COMPB_REF_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX2_COMPB_REF_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX3 +// +//***************************************************************************** +// Field: [7:0] ADCCOMPB_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO0 Internal. Only to be used through TI provided API. +// AUXIO1 Internal. Only to be used through TI provided API. +// AUXIO2 Internal. Only to be used through TI provided API. +// AUXIO3 Internal. Only to be used through TI provided API. +// AUXIO4 Internal. Only to be used through TI provided API. +// AUXIO5 Internal. Only to be used through TI provided API. +// AUXIO6 Internal. Only to be used through TI provided API. +// AUXIO7 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ISRC +// +//***************************************************************************** +// Field: [7:2] TRIM +// +// Adjust current from current source. +// +// Output currents may be combined to get desired total current. +// ENUMs: +// 11P75U 11.75 uA +// 4P5U 4.5 uA +// 2P0U 2.0 uA +// 1P0U 1.0 uA +// 0P5U 0.5 uA +// 0P25U 0.25 uA +// NC No current connected +#define ADI_4_AUX_ISRC_TRIM_W 6 +#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC +#define ADI_4_AUX_ISRC_TRIM_S 2 +#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080 +#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040 +#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020 +#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010 +#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008 +#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004 +#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000 + +// Field: [0] EN +// +// Current source enable +#define ADI_4_AUX_ISRC_EN 0x00000001 +#define ADI_4_AUX_ISRC_EN_M 0x00000001 +#define ADI_4_AUX_ISRC_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_COMP +// +//***************************************************************************** +// Field: [7] COMPA_REF_RES_EN +// +// Enables 400kohm resistance from COMPA reference node to ground. Used with +// COMPA_REF_CURR_EN to generate voltage reference for cap-sense. +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7 + +// Field: [6] COMPA_REF_CURR_EN +// +// Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires +// ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for +// cap-sense. +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 + +// Field: [5:3] COMPB_TRIM +// +// COMPB voltage reference trim temperature coded: +// ENUMs: +// DIV4 Divide reference by 4 +// DIV3 Divide reference by 3 +// DIV2 Divide reference by 2 +// DIV1 No reference division +#define ADI_4_AUX_COMP_COMPB_TRIM_W 3 +#define ADI_4_AUX_COMP_COMPB_TRIM_M 0x00000038 +#define ADI_4_AUX_COMP_COMPB_TRIM_S 3 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV4 0x00000038 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV3 0x00000018 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV2 0x00000008 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV1 0x00000000 + +// Field: [2] COMPB_EN +// +// COMPB enable +#define ADI_4_AUX_COMP_COMPB_EN 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_S 2 + +// Field: [0] COMPA_EN +// +// COMPA enable +#define ADI_4_AUX_COMP_COMPA_EN 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX4 +// +//***************************************************************************** +// Field: [7:0] COMPA_REF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO0 Internal. Only to be used through TI provided API. +// AUXIO1 Internal. Only to be used through TI provided API. +// AUXIO2 Internal. Only to be used through TI provided API. +// AUXIO3 Internal. Only to be used through TI provided API. +// AUXIO4 Internal. Only to be used through TI provided API. +// AUXIO5 Internal. Only to be used through TI provided API. +// AUXIO6 Internal. Only to be used through TI provided API. +// AUXIO7 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX4_COMPA_REF_W 8 +#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF +#define ADI_4_AUX_MUX4_COMPA_REF_S 0 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADC0 +// +//***************************************************************************** +// Field: [7] SMPL_MODE +// +// ADC Sampling mode: +// +// 0: Synchronous mode +// 1: Asynchronous mode +// +// The ADC does a sample-and-hold before conversion. In synchronous mode the +// sampling starts when the ADC clock detects a rising edge on the trigger +// signal. Jitter/uncertainty will be inferred in the detection if the trigger +// signal originates from a domain that is asynchronous to the ADC clock. +// SMPL_CYCLE_EXP determines the the duration of sampling. +// Conversion starts immediately after sampling ends. +// +// In asynchronous mode the sampling is continuous when enabled. Sampling ends +// and conversion starts immediately with the rising edge of the trigger +// signal. Sampling restarts when the conversion has finished. +// Asynchronous mode is useful when it is important to avoid jitter in the +// sampling instant of an externally driven signal +#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_S 7 + +// Field: [6:3] SMPL_CYCLE_EXP +// +// Controls the sampling duration before conversion when the ADC is operated in +// synchronous mode (SMPL_MODE = 0). The setting has no effect in asynchronous +// mode. The sampling duration is given as 2^(SMPL_CYCLE_EXP + 1) / 6 us. +// ENUMs: +// 10P9_MS 65536x 6 MHz clock periods = 10.9ms +// 5P46_MS 32768x 6 MHz clock periods = 5.46ms +// 2P73_MS 16384x 6 MHz clock periods = 2.73ms +// 1P37_MS 8192x 6 MHz clock periods = 1.37ms +// 682_US 4096x 6 MHz clock periods = 682us +// 341_US 2048x 6 MHz clock periods = 341us +// 170_US 1024x 6 MHz clock periods = 170us +// 85P3_US 512x 6 MHz clock periods = 85.3us +// 42P6_US 256x 6 MHz clock periods = 42.6us +// 21P3_US 128x 6 MHz clock periods = 21.3us +// 10P6_US 64x 6 MHz clock periods = 10.6us +// 5P3_US 32x 6 MHz clock periods = 5.3us +// 2P7_US 16x 6 MHz clock periods = 2.7us +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018 + +// Field: [1] RESET_N +// +// Reset ADC digital subchip, active low. ADC must be reset every time it is +// reconfigured. +// +// 0: Reset +// 1: Normal operation +#define ADI_4_AUX_ADC0_RESET_N 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_S 1 + +// Field: [0] EN +// +// ADC Enable +// +// 0: Disable +// 1: Enable +#define ADI_4_AUX_ADC0_EN 0x00000001 +#define ADI_4_AUX_ADC0_EN_M 0x00000001 +#define ADI_4_AUX_ADC0_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADC1 +// +//***************************************************************************** +// Field: [0] SCALE_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADCREF0 +// +//***************************************************************************** +// Field: [6] REF_ON_IDLE +// +// Keep ADCREF powered up in IDLE state when ADC0.SMPL_MODE = 0. +// +// Set to 1 if ADC0.SMPL_CYCLE_EXP is less than 6 (21.3us sampling time) +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 + +// Field: [5] IOMUX +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_S 5 + +// Field: [4] EXT +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADCREF0_EXT 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_S 4 + +// Field: [3] SRC +// +// ADC reference source: +// +// 0: Fixed reference = 4.3V +// 1: Relative reference = VDDS +#define ADI_4_AUX_ADCREF0_SRC 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_S 3 + +// Field: [0] EN +// +// ADC reference module enable: +// +// 0: ADC reference module powered down +// 1: ADC reference module enabled +#define ADI_4_AUX_ADCREF0_EN 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_M 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADCREF1 +// +//***************************************************************************** +// Field: [5:0] VTRIM +// +// Trim output voltage of ADC fixed reference (64 steps, 2's complement). +// Applies only for ADCREF0.SRC = 0. +// +// Examples: +// 0x00 - nominal voltage 1.43V +// 0x01 - nominal + 0.4% 1.435V +// 0x3F - nominal - 0.4% 1.425V +// 0x1F - maximum voltage 1.6V +// 0x20 - minimum voltage 1.3V +#define ADI_4_AUX_ADCREF1_VTRIM_W 6 +#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F +#define ADI_4_AUX_ADCREF1_VTRIM_S 0 + + +#endif // __ADI_4_AUX__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_batmon.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_batmon.h new file mode 100644 index 0000000..f09256d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_batmon.h @@ -0,0 +1,340 @@ +/****************************************************************************** +* Filename: hw_aon_batmon_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_BATMON_H__ +#define __HW_AON_BATMON_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_BATMON component +// +//***************************************************************************** +// Internal +#define AON_BATMON_O_CTL 0x00000000 + +// Internal +#define AON_BATMON_O_MEASCFG 0x00000004 + +// Internal +#define AON_BATMON_O_TEMPP0 0x0000000C + +// Internal +#define AON_BATMON_O_TEMPP1 0x00000010 + +// Internal +#define AON_BATMON_O_TEMPP2 0x00000014 + +// Internal +#define AON_BATMON_O_BATMONP0 0x00000018 + +// Internal +#define AON_BATMON_O_BATMONP1 0x0000001C + +// Internal +#define AON_BATMON_O_IOSTRP0 0x00000020 + +// Internal +#define AON_BATMON_O_FLASHPUMPP0 0x00000024 + +// Last Measured Battery Voltage +#define AON_BATMON_O_BAT 0x00000028 + +// Battery Update +#define AON_BATMON_O_BATUPD 0x0000002C + +// Temperature +#define AON_BATMON_O_TEMP 0x00000030 + +// Temperature Update +#define AON_BATMON_O_TEMPUPD 0x00000034 + +//***************************************************************************** +// +// Register: AON_BATMON_O_CTL +// +//***************************************************************************** +// Field: [1] CALC_EN +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_CTL_CALC_EN 0x00000002 +#define AON_BATMON_CTL_CALC_EN_BITN 1 +#define AON_BATMON_CTL_CALC_EN_M 0x00000002 +#define AON_BATMON_CTL_CALC_EN_S 1 + +// Field: [0] MEAS_EN +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_CTL_MEAS_EN 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_BITN 0 +#define AON_BATMON_CTL_MEAS_EN_M 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_MEASCFG +// +//***************************************************************************** +// Field: [1:0] PER +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 32CYC Internal. Only to be used through TI provided API. +// 16CYC Internal. Only to be used through TI provided API. +// 8CYC Internal. Only to be used through TI provided API. +// CONT Internal. Only to be used through TI provided API. +#define AON_BATMON_MEASCFG_PER_W 2 +#define AON_BATMON_MEASCFG_PER_M 0x00000003 +#define AON_BATMON_MEASCFG_PER_S 0 +#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003 +#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002 +#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001 +#define AON_BATMON_MEASCFG_PER_CONT 0x00000000 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP0 +// +//***************************************************************************** +// Field: [7:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP0_CFG_W 8 +#define AON_BATMON_TEMPP0_CFG_M 0x000000FF +#define AON_BATMON_TEMPP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP1 +// +//***************************************************************************** +// Field: [5:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP1_CFG_W 6 +#define AON_BATMON_TEMPP1_CFG_M 0x0000003F +#define AON_BATMON_TEMPP1_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP2 +// +//***************************************************************************** +// Field: [4:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP2_CFG_W 5 +#define AON_BATMON_TEMPP2_CFG_M 0x0000001F +#define AON_BATMON_TEMPP2_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATMONP0 +// +//***************************************************************************** +// Field: [5:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_BATMONP0_CFG_W 6 +#define AON_BATMON_BATMONP0_CFG_M 0x0000003F +#define AON_BATMON_BATMONP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATMONP1 +// +//***************************************************************************** +// Field: [5:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_BATMONP1_CFG_W 6 +#define AON_BATMON_BATMONP1_CFG_M 0x0000003F +#define AON_BATMON_BATMONP1_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_IOSTRP0 +// +//***************************************************************************** +// Field: [5:4] CFG2 +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_IOSTRP0_CFG2_W 2 +#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030 +#define AON_BATMON_IOSTRP0_CFG2_S 4 + +// Field: [3:0] CFG1 +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_IOSTRP0_CFG1_W 4 +#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F +#define AON_BATMON_IOSTRP0_CFG1_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_FLASHPUMPP0 +// +//***************************************************************************** +// Field: [8] FALLB +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8 +#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_S 8 + +// Field: [7:6] HIGHLIM +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6 + +// Field: [5] LOWLIM +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5 + +// Field: [4] OVR +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4 +#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_S 4 + +// Field: [3:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_CFG_W 4 +#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F +#define AON_BATMON_FLASHPUMPP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BAT +// +//***************************************************************************** +// Field: [10:8] INT +// +// Integer part: +// +// 0x0: 0V + fractional part +// ... +// 0x3: 3V + fractional part +// 0x4: 4V + fractional part +#define AON_BATMON_BAT_INT_W 3 +#define AON_BATMON_BAT_INT_M 0x00000700 +#define AON_BATMON_BAT_INT_S 8 + +// Field: [7:0] FRAC +// +// Fractional part, standard binary fractional encoding. +// +// 0x00: .0V +// ... +// 0x20: 1/8 = .125V +// 0x40: 1/4 = .25V +// 0x80: 1/2 = .5V +// ... +// 0xA0: 1/2 + 1/8 = .625V +// ... +// 0xFF: Max +#define AON_BATMON_BAT_FRAC_W 8 +#define AON_BATMON_BAT_FRAC_M 0x000000FF +#define AON_BATMON_BAT_FRAC_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATUPD +// +//***************************************************************************** +// Field: [0] STAT +// +// +// 0: No update since last clear +// 1: New battery voltage is present. +// +// Write 1 to clear the status. +#define AON_BATMON_BATUPD_STAT 0x00000001 +#define AON_BATMON_BATUPD_STAT_BITN 0 +#define AON_BATMON_BATUPD_STAT_M 0x00000001 +#define AON_BATMON_BATUPD_STAT_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMP +// +//***************************************************************************** +// Field: [16:8] INT +// +// Integer part (signed) of temperature value. +// Total value = INTEGER + FRACTIONAL +// 2's complement encoding +// +// 0x100: Min value +// 0x1D8: -40C +// 0x1FF: -1C +// 0x00: 0C +// 0x1B: 27C +// 0x55: 85C +// 0xFF: Max value +#define AON_BATMON_TEMP_INT_W 9 +#define AON_BATMON_TEMP_INT_M 0x0001FF00 +#define AON_BATMON_TEMP_INT_S 8 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPUPD +// +//***************************************************************************** +// Field: [0] STAT +// +// +// 0: No update since last clear +// 1: New temperature is present. +// +// Write 1 to clear the status. +#define AON_BATMON_TEMPUPD_STAT 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_BITN 0 +#define AON_BATMON_TEMPUPD_STAT_M 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_S 0 + + +#endif // __AON_BATMON__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_event.h new file mode 100644 index 0000000..2896b81 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_event.h @@ -0,0 +1,1533 @@ +/****************************************************************************** +* Filename: hw_aon_event_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_EVENT_H__ +#define __HW_AON_EVENT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_EVENT component +// +//***************************************************************************** +// Wake-up Selector For MCU +#define AON_EVENT_O_MCUWUSEL 0x00000000 + +// Wake-up Selector For AUX +#define AON_EVENT_O_AUXWUSEL 0x00000004 + +// Event Selector For MCU Event Fabric +#define AON_EVENT_O_EVTOMCUSEL 0x00000008 + +// RTC Capture Event Selector For AON_RTC +#define AON_EVENT_O_RTCSEL 0x0000000C + +//***************************************************************************** +// +// Register: AON_EVENT_O_MCUWUSEL +// +//***************************************************************************** +// Field: [29:24] WU3_EV +// +// MCU Wakeup Source #3 +// +// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the +// MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_MCUWUSEL_WU3_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_S 24 +#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD31 0x1F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD30 0x1E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD29 0x1D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD28 0x1C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD27 0x1B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD26 0x1A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD25 0x19000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD24 0x18000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD23 0x17000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD22 0x16000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD21 0x15000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD20 0x14000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD19 0x13000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD18 0x12000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD17 0x11000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD16 0x10000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD15 0x0F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD14 0x0E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD13 0x0D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD12 0x0C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD11 0x0B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD10 0x0A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD9 0x09000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD8 0x08000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD7 0x07000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD6 0x06000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD5 0x05000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD4 0x04000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD3 0x03000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD2 0x02000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD1 0x01000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD0 0x00000000 + +// Field: [21:16] WU2_EV +// +// MCU Wakeup Source #2 +// +// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the +// MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_MCUWUSEL_WU2_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_S 16 +#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD31 0x001F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD30 0x001E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD29 0x001D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD28 0x001C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD27 0x001B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD26 0x001A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD25 0x00190000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD24 0x00180000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD23 0x00170000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD22 0x00160000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD21 0x00150000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD20 0x00140000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD19 0x00130000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD18 0x00120000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD17 0x00110000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD16 0x00100000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD15 0x000F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD14 0x000E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD13 0x000D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD12 0x000C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD11 0x000B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD10 0x000A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD9 0x00090000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD8 0x00080000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD7 0x00070000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD6 0x00060000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD5 0x00050000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD4 0x00040000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD3 0x00030000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD2 0x00020000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD1 0x00010000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD0 0x00000000 + +// Field: [13:8] WU1_EV +// +// MCU Wakeup Source #1 +// +// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the +// MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_MCUWUSEL_WU1_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_S 8 +#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD31 0x00001F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD30 0x00001E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD29 0x00001D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD28 0x00001C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD27 0x00001B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD26 0x00001A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD25 0x00001900 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD24 0x00001800 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD23 0x00001700 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD22 0x00001600 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD21 0x00001500 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD20 0x00001400 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD19 0x00001300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD18 0x00001200 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD17 0x00001100 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD16 0x00001000 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD15 0x00000F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD14 0x00000E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD13 0x00000D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD12 0x00000C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD11 0x00000B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD10 0x00000A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD9 0x00000900 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD8 0x00000800 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD7 0x00000700 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD6 0x00000600 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD5 0x00000500 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD4 0x00000400 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD3 0x00000300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD2 0x00000200 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD1 0x00000100 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD0 0x00000000 + +// Field: [5:0] WU0_EV +// +// MCU Wakeup Source #0 +// +// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the +// MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_MCUWUSEL_WU0_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_S 0 +#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD31 0x0000001F +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD30 0x0000001E +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD29 0x0000001D +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD28 0x0000001C +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD27 0x0000001B +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD26 0x0000001A +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD25 0x00000019 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD24 0x00000018 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD23 0x00000017 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD22 0x00000016 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD21 0x00000015 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD20 0x00000014 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD19 0x00000013 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD18 0x00000012 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD17 0x00000011 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD16 0x00000010 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD15 0x0000000F +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD14 0x0000000E +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD13 0x0000000D +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD12 0x0000000C +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD11 0x0000000B +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD10 0x0000000A +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD9 0x00000009 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD8 0x00000008 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD7 0x00000007 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD6 0x00000006 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD5 0x00000005 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD4 0x00000004 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD3 0x00000003 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD2 0x00000002 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD1 0x00000001 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD0 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_AUXWUSEL +// +//***************************************************************************** +// Field: [21:16] WU2_EV +// +// AUX Wakeup Source #2 +// +// AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the +// AUX domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_AUXWUSEL_WU2_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU2_EV_M 0x003F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_S 16 +#define AON_EVENT_AUXWUSEL_WU2_EV_NONE 0x003F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_JTAG 0x002B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD 0x00200000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD31 0x001F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD30 0x001E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD29 0x001D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD28 0x001C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD27 0x001B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD26 0x001A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD25 0x00190000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD24 0x00180000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD23 0x00170000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD22 0x00160000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD21 0x00150000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD20 0x00140000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD19 0x00130000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD18 0x00120000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD17 0x00110000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD16 0x00100000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD15 0x000F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD14 0x000E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD13 0x000D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD12 0x000C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD11 0x000B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD10 0x000A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD9 0x00090000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD8 0x00080000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD7 0x00070000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD6 0x00060000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD5 0x00050000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD4 0x00040000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD3 0x00030000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD2 0x00020000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD1 0x00010000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD0 0x00000000 + +// Field: [13:8] WU1_EV +// +// AUX Wakeup Source #1 +// +// AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the +// AUX domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_AUXWUSEL_WU1_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU1_EV_M 0x00003F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_S 8 +#define AON_EVENT_AUXWUSEL_WU1_EV_NONE 0x00003F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_JTAG 0x00002B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD 0x00002000 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD31 0x00001F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD30 0x00001E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD29 0x00001D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD28 0x00001C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD27 0x00001B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD26 0x00001A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD25 0x00001900 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD24 0x00001800 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD23 0x00001700 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD22 0x00001600 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD21 0x00001500 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD20 0x00001400 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD19 0x00001300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD18 0x00001200 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD17 0x00001100 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD16 0x00001000 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD15 0x00000F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD14 0x00000E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD13 0x00000D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD12 0x00000C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD11 0x00000B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD10 0x00000A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD9 0x00000900 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD8 0x00000800 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD7 0x00000700 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD6 0x00000600 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD5 0x00000500 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD4 0x00000400 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD3 0x00000300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD2 0x00000200 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD1 0x00000100 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD0 0x00000000 + +// Field: [5:0] WU0_EV +// +// AUX Wakeup Source #0 +// +// AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the +// AUX domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_AUXWUSEL_WU0_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU0_EV_M 0x0000003F +#define AON_EVENT_AUXWUSEL_WU0_EV_S 0 +#define AON_EVENT_AUXWUSEL_WU0_EV_NONE 0x0000003F +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_AUXWUSEL_WU0_EV_JTAG 0x0000002B +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD 0x00000020 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD31 0x0000001F +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD30 0x0000001E +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD29 0x0000001D +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD28 0x0000001C +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD27 0x0000001B +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD26 0x0000001A +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD25 0x00000019 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD24 0x00000018 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD23 0x00000017 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD22 0x00000016 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD21 0x00000015 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD20 0x00000014 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD19 0x00000013 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD18 0x00000012 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD17 0x00000011 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD16 0x00000010 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD15 0x0000000F +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD14 0x0000000E +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD13 0x0000000D +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD12 0x0000000C +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD11 0x0000000B +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD10 0x0000000A +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD9 0x00000009 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD8 0x00000008 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD7 0x00000007 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD6 0x00000006 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD5 0x00000005 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD4 0x00000004 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD3 0x00000003 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD2 0x00000002 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD1 0x00000001 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD0 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_EVTOMCUSEL +// +//***************************************************************************** +// Field: [21:16] AON_PROG2_EV +// +// Event selector for AON_PROG2 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG2 event. +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD31 0x001F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD30 0x001E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD29 0x001D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD28 0x001C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD27 0x001B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD26 0x001A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD25 0x00190000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD24 0x00180000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD23 0x00170000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD22 0x00160000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD21 0x00150000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD20 0x00140000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD19 0x00130000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD18 0x00120000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD17 0x00110000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD16 0x00100000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD15 0x000F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD14 0x000E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD13 0x000D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD12 0x000C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD11 0x000B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD10 0x000A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD9 0x00090000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD8 0x00080000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD7 0x00070000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD6 0x00060000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD5 0x00050000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD4 0x00040000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD3 0x00030000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD2 0x00020000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD1 0x00010000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD0 0x00000000 + +// Field: [13:8] AON_PROG1_EV +// +// Event selector for AON_PROG1 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG1 event. +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD31 0x00001F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD30 0x00001E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD29 0x00001D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD28 0x00001C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD27 0x00001B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD26 0x00001A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD25 0x00001900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD24 0x00001800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD23 0x00001700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD22 0x00001600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD21 0x00001500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD20 0x00001400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD19 0x00001300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD18 0x00001200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD17 0x00001100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD16 0x00001000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD15 0x00000F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD14 0x00000E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD13 0x00000D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD12 0x00000C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD11 0x00000B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD10 0x00000A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD9 0x00000900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD8 0x00000800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD7 0x00000700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD6 0x00000600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD5 0x00000500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD4 0x00000400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD3 0x00000300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD2 0x00000200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD1 0x00000100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD0 0x00000000 + +// Field: [5:0] AON_PROG0_EV +// +// Event selector for AON_PROG0 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG0 event. +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD31 0x0000001F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD30 0x0000001E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD29 0x0000001D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD28 0x0000001C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD27 0x0000001B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD26 0x0000001A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD25 0x00000019 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD24 0x00000018 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD23 0x00000017 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD22 0x00000016 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD21 0x00000015 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD20 0x00000014 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD19 0x00000013 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD18 0x00000012 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD17 0x00000011 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD16 0x00000010 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD15 0x0000000F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD14 0x0000000E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD13 0x0000000D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD12 0x0000000C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD11 0x0000000B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD10 0x0000000A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD9 0x00000009 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD8 0x00000008 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD7 0x00000007 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD6 0x00000006 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD5 0x00000005 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD4 0x00000004 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD3 0x00000003 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD2 0x00000002 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD1 0x00000001 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD0 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_RTCSEL +// +//***************************************************************************** +// Field: [5:0] RTC_CH1_CAPT_EV +// +// AON Event Source id# for RTCSEL event which is fed to AON_RTC. Please refer +// to AON_RTC:CH1CAPT +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// PAD31 Edge detect on PAD31 +// PAD30 Edge detect on PAD30 +// PAD29 Edge detect on PAD29 +// PAD28 Edge detect on PAD28 +// PAD27 Edge detect on PAD27 +// PAD26 Edge detect on PAD26 +// PAD25 Edge detect on PAD25 +// PAD24 Edge detect on PAD24 +// PAD23 Edge detect on PAD23 +// PAD22 Edge detect on PAD22 +// PAD21 Edge detect on PAD21 +// PAD20 Edge detect on PAD20 +// PAD19 Edge detect on PAD19 +// PAD18 Edge detect on PAD18 +// PAD17 Edge detect on PAD17 +// PAD16 Edge detect on PAD16 +// PAD15 Edge detect on PAD15 +// PAD14 Edge detect on PAD14 +// PAD13 Edge detect on PAD13 +// PAD12 Edge detect on PAD12 +// PAD11 Edge detect on PAD11 +// PAD10 Edge detect on PAD10 +// PAD9 Edge detect on PAD9 +// PAD8 Edge detect on PAD8 +// PAD7 Edge detect on PAD7 +// PAD6 Edge detect on PAD6 +// PAD5 Edge detect on PAD5 +// PAD4 Edge detect on PAD4 +// PAD3 Edge detect on PAD3 +// PAD2 Edge detect on PAD2 +// PAD1 Edge detect on PAD1 +// PAD0 Edge detect on PAD0 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD31 0x0000001F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD30 0x0000001E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD29 0x0000001D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD28 0x0000001C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD27 0x0000001B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD26 0x0000001A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD25 0x00000019 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD24 0x00000018 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD23 0x00000017 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD22 0x00000016 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD21 0x00000015 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD20 0x00000014 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD19 0x00000013 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD18 0x00000012 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD17 0x00000011 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD16 0x00000010 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD15 0x0000000F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD14 0x0000000E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD13 0x0000000D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD12 0x0000000C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD11 0x0000000B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD10 0x0000000A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD9 0x00000009 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD8 0x00000008 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD7 0x00000007 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD6 0x00000006 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD5 0x00000005 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD4 0x00000004 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD3 0x00000003 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD2 0x00000002 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD1 0x00000001 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD0 0x00000000 + + +#endif // __AON_EVENT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_ioc.h new file mode 100644 index 0000000..98ecbed --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_ioc.h @@ -0,0 +1,141 @@ +/****************************************************************************** +* Filename: hw_aon_ioc_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_IOC_H__ +#define __HW_AON_IOC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_IOC component +// +//***************************************************************************** +// Internal +#define AON_IOC_O_IOSTRMIN 0x00000000 + +// Internal +#define AON_IOC_O_IOSTRMED 0x00000004 + +// Internal +#define AON_IOC_O_IOSTRMAX 0x00000008 + +// IO Latch Control +#define AON_IOC_O_IOCLATCH 0x0000000C + +// SCLK_LF External Output Control +#define AON_IOC_O_CLK32KCTL 0x00000010 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMIN +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMED +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMED_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMED_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMAX +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOCLATCH +// +//***************************************************************************** +// Field: [0] EN +// +// Controls latches between MCU IOC and AON_IOC. +// +// The latches are transparent by default. +// +// They must be closed prior to power off the domain(s) controlling the IOs in +// order to preserve IO values on external pins. +// ENUMs: +// TRANSP Latches are transparent, meaning the value of the +// IO is directly controlled by the GPIO or +// peripheral value +// STATIC Latches are static, meaning the current value on +// the IO pin is frozen by latches and kept even +// if GPIO module or a peripheral module is turned +// off +#define AON_IOC_IOCLATCH_EN 0x00000001 +#define AON_IOC_IOCLATCH_EN_BITN 0 +#define AON_IOC_IOCLATCH_EN_M 0x00000001 +#define AON_IOC_IOCLATCH_EN_S 0 +#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001 +#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000 + +//***************************************************************************** +// +// Register: AON_IOC_O_CLK32KCTL +// +//***************************************************************************** +// Field: [0] OE_N +// +// 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (e.g. +// IOC:IOCFG0.PORT_ID) set to AON_CLK32K. +// 1: Output enable not active +#define AON_IOC_CLK32KCTL_OE_N 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_BITN 0 +#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_S 0 + + +#endif // __AON_IOC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_rtc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_rtc.h new file mode 100644 index 0000000..521504d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_rtc.h @@ -0,0 +1,508 @@ +/****************************************************************************** +* Filename: hw_aon_rtc_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_RTC_H__ +#define __HW_AON_RTC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_RTC component +// +//***************************************************************************** +// Control +#define AON_RTC_O_CTL 0x00000000 + +// Event Flags, RTC Status +#define AON_RTC_O_EVFLAGS 0x00000004 + +// Second Counter Value, Integer Part +#define AON_RTC_O_SEC 0x00000008 + +// Second Counter Value, Fractional Part +#define AON_RTC_O_SUBSEC 0x0000000C + +// Subseconds Increment +#define AON_RTC_O_SUBSECINC 0x00000010 + +// Channel Configuration +#define AON_RTC_O_CHCTL 0x00000014 + +// Channel 0 Compare Value +#define AON_RTC_O_CH0CMP 0x00000018 + +// Channel 1 Compare Value +#define AON_RTC_O_CH1CMP 0x0000001C + +// Channel 2 Compare Value +#define AON_RTC_O_CH2CMP 0x00000020 + +// Channel 2 Compare Value Auto-increment +#define AON_RTC_O_CH2CMPINC 0x00000024 + +// Channel 1 Capture Value +#define AON_RTC_O_CH1CAPT 0x00000028 + +// AON Synchronization +#define AON_RTC_O_SYNC 0x0000002C + +//***************************************************************************** +// +// Register: AON_RTC_O_CTL +// +//***************************************************************************** +// Field: [18:16] COMB_EV_MASK +// +// Eventmask selecting which delayed events that form the combined event. +// ENUMs: +// CH2 Use Channel 2 delayed event in combined event +// CH1 Use Channel 1 delayed event in combined event +// CH0 Use Channel 0 delayed event in combined event +// NONE No event is selected for combined event. +#define AON_RTC_CTL_COMB_EV_MASK_W 3 +#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 +#define AON_RTC_CTL_COMB_EV_MASK_S 16 +#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 +#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 +#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 +#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 + +// Field: [11:8] EV_DELAY +// +// Number of SCLK_LF clock cycles waited before generating delayed events. +// (Common setting for all RTC cannels) the delayed event is delayed +// ENUMs: +// D144 Delay by 144 clock cycles +// D128 Delay by 128 clock cycles +// D112 Delay by 112 clock cycles +// D96 Delay by 96 clock cycles +// D80 Delay by 80 clock cycles +// D64 Delay by 64 clock cycles +// D48 Delay by 48 clock cycles +// D32 Delay by 32 clock cycles +// D16 Delay by 16 clock cycles +// D8 Delay by 8 clock cycles +// D4 Delay by 4 clock cycles +// D2 Delay by 2 clock cycles +// D1 Delay by 1 clock cycles +// D0 No delay on delayed event +#define AON_RTC_CTL_EV_DELAY_W 4 +#define AON_RTC_CTL_EV_DELAY_M 0x00000F00 +#define AON_RTC_CTL_EV_DELAY_S 8 +#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 +#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 +#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 +#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 +#define AON_RTC_CTL_EV_DELAY_D80 0x00000900 +#define AON_RTC_CTL_EV_DELAY_D64 0x00000800 +#define AON_RTC_CTL_EV_DELAY_D48 0x00000700 +#define AON_RTC_CTL_EV_DELAY_D32 0x00000600 +#define AON_RTC_CTL_EV_DELAY_D16 0x00000500 +#define AON_RTC_CTL_EV_DELAY_D8 0x00000400 +#define AON_RTC_CTL_EV_DELAY_D4 0x00000300 +#define AON_RTC_CTL_EV_DELAY_D2 0x00000200 +#define AON_RTC_CTL_EV_DELAY_D1 0x00000100 +#define AON_RTC_CTL_EV_DELAY_D0 0x00000000 + +// Field: [7] RESET +// +// RTC Counter reset. +// +// Writing 1 to this bit will reset the RTC counter. +// +// This bit is cleared when reset takes effect +#define AON_RTC_CTL_RESET 0x00000080 +#define AON_RTC_CTL_RESET_BITN 7 +#define AON_RTC_CTL_RESET_M 0x00000080 +#define AON_RTC_CTL_RESET_S 7 + +// Field: [2] RTC_4KHZ_EN +// +// RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 +// which is used by AUX timer. +// +// 0: RTC_4KHZ signal is forced to 0 +// 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) +#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 +#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_S 2 + +// Field: [1] RTC_UPD_EN +// +// RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is +// SCLK_LF divided by 2 +// +// 0: RTC_UPD signal is forced to 0 +// 1: RTC_UPD signal is toggling @16 kHz +#define AON_RTC_CTL_RTC_UPD_EN 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_BITN 1 +#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_S 1 + +// Field: [0] EN +// +// Enable RTC counter +// +// 0: Halted (frozen) +// 1: Running +#define AON_RTC_CTL_EN 0x00000001 +#define AON_RTC_CTL_EN_BITN 0 +#define AON_RTC_CTL_EN_M 0x00000001 +#define AON_RTC_CTL_EN_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_EVFLAGS +// +//***************************************************************************** +// Field: [16] CH2 +// +// Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or +// passes the CH2CMP value. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH2CMP provided that the channel is enabled and the new value matches any +// time between next RTC value and 1 second in the past +// +// Writing 1 clears this flag. Note that a new event can not occur on this +// channel in first 2 SCLK_LF cycles after a clearance. +// +// AUX_SCE can read the flag through AUX_WUC:WUEVFLAGS.AON_RTC_CH2 and clear it +// using AUX_WUC:WUEVCLR.AON_RTC_CH2. +#define AON_RTC_EVFLAGS_CH2 0x00010000 +#define AON_RTC_EVFLAGS_CH2_BITN 16 +#define AON_RTC_EVFLAGS_CH2_M 0x00010000 +#define AON_RTC_EVFLAGS_CH2_S 16 + +// Field: [8] CH1 +// +// Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following: +// - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP +// value. +// - CHCTL.CH1_CAPT_EN = 1 and capture occurs. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH1CMP provided that the channel is enabled, in compare mode and the new +// value matches any time between next RTC value and 1 second in the past. +// +// Writing 1 clears this flag. Note that a new event can not occur on this +// channel in first 2 SCLK_LF cycles after a clearance. +#define AON_RTC_EVFLAGS_CH1 0x00000100 +#define AON_RTC_EVFLAGS_CH1_BITN 8 +#define AON_RTC_EVFLAGS_CH1_M 0x00000100 +#define AON_RTC_EVFLAGS_CH1_S 8 + +// Field: [0] CH0 +// +// Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or +// passes the CH0CMP value. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH0CMP provided that the channels is enabled and the new value matches any +// time between next RTC value and 1 second in the past. +// +// Writing 1 clears this flag. Note that a new event can not occur on this +// channel in first 2 SCLK_LF cycles after a clearance. +#define AON_RTC_EVFLAGS_CH0 0x00000001 +#define AON_RTC_EVFLAGS_CH0_BITN 0 +#define AON_RTC_EVFLAGS_CH0_M 0x00000001 +#define AON_RTC_EVFLAGS_CH0_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SEC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// Unsigned integer representing Real Time Clock in seconds. +// +// When reading this register the content of SUBSEC.VALUE is simultaneously +// latched. A consistent reading of the combined Real Time Clock can be +// obtained by first reading this register, then reading SUBSEC register. +#define AON_RTC_SEC_VALUE_W 32 +#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SEC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SUBSEC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// Unsigned integer representing Real Time Clock in fractions of a second +// (VALUE/2^32 seconds) at the time when SEC register was read. +// +// Examples : +// - 0x0000_0000 = 0.0 sec +// - 0x4000_0000 = 0.25 sec +// - 0x8000_0000 = 0.5 sec +// - 0xC000_0000 = 0.75 sec +#define AON_RTC_SUBSEC_VALUE_W 32 +#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SUBSEC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SUBSECINC +// +//***************************************************************************** +// Field: [23:0] VALUEINC +// +// This value compensates for a SCLK_LF clock which has an offset from 32768 +// Hz. +// +// The compensation value can be found as 2^38 / freq, where freq is SCLK_LF +// clock frequency in Hertz +// +// This value is added to SUBSEC.VALUE on every cycle, and carry of this is +// added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with +// SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a +// hidden 6-bit register that generates a carry into the above mentioned +// addition on overflow. +// The default value corresponds to incrementing by precisely 1/32768 of a +// second. +// +// NOTE: This register is read only. Modification of the register value must be +// done using registers AUX_WUC:RTCSUBSECINC1 , AUX_WUC:RTCSUBSECINC0 and +// AUX_WUC:RTCSUBSECINCCTL +#define AON_RTC_SUBSECINC_VALUEINC_W 24 +#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF +#define AON_RTC_SUBSECINC_VALUEINC_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CHCTL +// +//***************************************************************************** +// Field: [18] CH2_CONT_EN +// +// Set to enable continuous operation of Channel 2 +#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 +#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_S 18 + +// Field: [16] CH2_EN +// +// RTC Channel 2 Enable +// +// 0: Disable RTC Channel 2 +// 1: Enable RTC Channel 2 +#define AON_RTC_CHCTL_CH2_EN 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_BITN 16 +#define AON_RTC_CHCTL_CH2_EN_M 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_S 16 + +// Field: [9] CH1_CAPT_EN +// +// Set Channel 1 mode +// +// 0: Compare mode (default) +// 1: Capture mode +#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 +#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 + +// Field: [8] CH1_EN +// +// RTC Channel 1 Enable +// +// 0: Disable RTC Channel 1 +// 1: Enable RTC Channel 1 +#define AON_RTC_CHCTL_CH1_EN 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_BITN 8 +#define AON_RTC_CHCTL_CH1_EN_M 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_S 8 + +// Field: [0] CH0_EN +// +// RTC Channel 0 Enable +// +// 0: Disable RTC Channel 0 +// 1: Enable RTC Channel 0 +#define AON_RTC_CHCTL_CH0_EN 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_BITN 0 +#define AON_RTC_CHCTL_CH0_EN_M 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH0CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 0 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to 2 SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH0CMP_VALUE_W 32 +#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH0CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH1CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 1 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to 2 SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH1CMP_VALUE_W 32 +#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH1CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH2CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 2 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to 2 SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH2CMP_VALUE_W 32 +#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH2CMPINC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every +// channel 2 compare event. +#define AON_RTC_CH2CMPINC_VALUE_W 32 +#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMPINC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH1CAPT +// +//***************************************************************************** +// Field: [31:16] SEC +// +// Value of SEC.VALUE bits 15:0 at capture time. +#define AON_RTC_CH1CAPT_SEC_W 16 +#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 +#define AON_RTC_CH1CAPT_SEC_S 16 + +// Field: [15:0] SUBSEC +// +// Value of SUBSEC.VALUE bits 31:16 at capture time. +#define AON_RTC_CH1CAPT_SUBSEC_W 16 +#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF +#define AON_RTC_CH1CAPT_SUBSEC_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SYNC +// +//***************************************************************************** +// Field: [0] WBUSY +// +// This register will always return 0,- however it will not return the value +// until there are no outstanding write requests between MCU and AON +// +// Note: Writing to this register prior to reading will force a wait until next +// SCLK_LF edge. This is recommended for syncing read registers from AON when +// waking up from sleep +// Failure to do so may result in reading AON values from prior to going to +// sleep +#define AON_RTC_SYNC_WBUSY 0x00000001 +#define AON_RTC_SYNC_WBUSY_BITN 0 +#define AON_RTC_SYNC_WBUSY_M 0x00000001 +#define AON_RTC_SYNC_WBUSY_S 0 + + +#endif // __AON_RTC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_sysctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_sysctl.h new file mode 100644 index 0000000..c8352c1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_sysctl.h @@ -0,0 +1,348 @@ +/****************************************************************************** +* Filename: hw_aon_sysctl_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_SYSCTL_H__ +#define __HW_AON_SYSCTL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_SYSCTL component +// +//***************************************************************************** +// Power Management +#define AON_SYSCTL_O_PWRCTL 0x00000000 + +// Reset Management +#define AON_SYSCTL_O_RESETCTL 0x00000004 + +// Sleep Mode +#define AON_SYSCTL_O_SLEEPCTL 0x00000008 + +//***************************************************************************** +// +// Register: AON_SYSCTL_O_PWRCTL +// +//***************************************************************************** +// Field: [2] DCDC_ACTIVE +// +// Select to use DCDC regulator for VDDR in active mode +// +// 0: Use GLDO for regulation of VDDRin active mode. +// 1: Use DCDC for regulation of VDDRin active mode. +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE 0x00000004 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN 2 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_S 2 + +// Field: [1] EXT_REG_MODE +// +// Status of source for VDDRsupply: +// +// 0: DCDC/GLDO are generating VDDR +// 1: DCDC/GLDO are bypassed, external regulator supplies VDDR +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE 0x00000002 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_BITN 1 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_S 1 + +// Field: [0] DCDC_EN +// +// Select to use DCDC regulator during recharge of VDDR +// +// 0: Use GLDO for recharge of VDDR +// 1: Use DCDC for recharge of VDDR +// +// Note: This bitfield should be set to the same as DCDC_ACTIVE +#define AON_SYSCTL_PWRCTL_DCDC_EN 0x00000001 +#define AON_SYSCTL_PWRCTL_DCDC_EN_BITN 0 +#define AON_SYSCTL_PWRCTL_DCDC_EN_M 0x00000001 +#define AON_SYSCTL_PWRCTL_DCDC_EN_S 0 + +//***************************************************************************** +// +// Register: AON_SYSCTL_O_RESETCTL +// +//***************************************************************************** +// Field: [31] SYSRESET +// +// Cold reset register. Writing 1 to this bitfield will reset the entire chip +// and cause boot code to run again. +// +// 0: No effect +// 1: Generate system reset. Appears as SYSRESET in RESET_SRC. +#define AON_SYSCTL_RESETCTL_SYSRESET 0x80000000 +#define AON_SYSCTL_RESETCTL_SYSRESET_BITN 31 +#define AON_SYSCTL_RESETCTL_SYSRESET_M 0x80000000 +#define AON_SYSCTL_RESETCTL_SYSRESET_S 31 + +// Field: [25] BOOT_DET_1_CLR +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_S 25 + +// Field: [24] BOOT_DET_0_CLR +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_S 24 + +// Field: [17] BOOT_DET_1_SET +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_S 17 + +// Field: [16] BOOT_DET_0_SET +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_S 16 + +// Field: [15] WU_FROM_SD +// +// A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from +// SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin +// being forced low) +// +// Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup +// sources. +// +// 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC +// 1: A wakeup has occurred from SHUTDOWN +// +// Note: This flag can not be cleared and will therefor remain valid untill +// poweroff/reset +#define AON_SYSCTL_RESETCTL_WU_FROM_SD 0x00008000 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_BITN 15 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_M 0x00008000 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_S 15 + +// Field: [14] GPIO_WU_FROM_SD +// +// A wakeup from SHUTDOWN on an IO event has occurred +// +// Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup +// sources. +// +// 0: The wakeup did not occur from SHUTDOWN on an IO event +// 1: A wakeup from SHUTDOWN occurred from an IO event +// +// The case where WU_FROM_SD is asserted but this bitfield is not asserted will +// only occur in a debug session. The boot code will not proceed with wakeup +// from SHUTDOWN procedure until this bitfield is asserted as well. +// +// Note: This flag can not be cleared and will therefor remain valid untill +// poweroff/reset +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 + +// Field: [13] BOOT_DET_1 +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_1 0x00002000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_BITN 13 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_M 0x00002000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_S 13 + +// Field: [12] BOOT_DET_0 +// +// Internal. Only to be used through TI provided API. +#define AON_SYSCTL_RESETCTL_BOOT_DET_0 0x00001000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_BITN 12 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_M 0x00001000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_S 12 + +// Field: [11] VDDS_LOSS_EN_OVR +// +// Override of VDDS_LOSS_EN +// +// 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN=1 +// 1: Brown out detect of VDDS generates system reset (regardless of +// VDDS_LOSS_EN) +// +// This bit can be locked +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR 0x00000800 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_BITN 11 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_M 0x00000800 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_S 11 + +// Field: [10] VDDR_LOSS_EN_OVR +// +// Override of VDDR_LOSS_EN +// +// 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN=1 +// 1: Brown out detect of VDDR generates system reset (regardless of +// VDDR_LOSS_EN) +// +// This bit can be locked +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR 0x00000400 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_BITN 10 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_M 0x00000400 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_S 10 + +// Field: [9] VDD_LOSS_EN_OVR +// +// Override of VDD_LOSS_EN +// +// 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN=1 +// 1: Brown out detect of VDD generates system reset (regardless of +// VDD_LOSS_EN) +// +// This bit can be locked +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR 0x00000200 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_BITN 9 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_M 0x00000200 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_S 9 + +// Field: [7] VDDS_LOSS_EN +// +// Controls reset generation in case VDDS is lost +// +// 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 +// 1: Brown out detect of VDDS generates system reset +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN 0x00000080 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_BITN 7 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000080 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_S 7 + +// Field: [6] VDDR_LOSS_EN +// +// Controls reset generation in case VDDR is lost +// +// 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 +// 1: Brown out detect of VDDR generates system reset +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN 0x00000040 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN 6 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000040 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_S 6 + +// Field: [5] VDD_LOSS_EN +// +// Controls reset generation in case VDD is lost +// +// 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 +// 1: Brown out detect of VDD generates system reset +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN 0x00000020 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_BITN 5 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_M 0x00000020 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_S 5 + +// Field: [4] CLK_LOSS_EN +// +// Controls reset generation in case SCLK_LF is lost. (provided that clock +// loss detection is enabled by DDI_0_OSC:CTL0.CLK_LOSS_EN) +// +// Note: Clock loss reset generation must be disabled before SCLK_LF clock +// source is changed in DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL and remain disabled +// untill the change is confirmed in DDI_0_OSC:STAT0.SCLK_LF_SRC. Failure to do +// so may result in a spurious system reset. Clock loss reset generation can be +// disabled through this bitfield or by clearing DDI_0_OSC:CTL0.CLK_LOSS_EN +// +// 0: Clock loss is ignored +// 1: Clock loss generates system reset +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN 0x00000010 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN 4 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_M 0x00000010 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_S 4 + +// Field: [3:1] RESET_SRC +// +// Shows the source of the last system reset: +// Occurrence of one of the reset sources may trigger several other reset +// sources as essential parts of the system are undergoing reset. This field +// will report the root cause of the reset (not the other resets that are +// consequence of the system reset). +// To support this feature the actual register is not captured before the reset +// source being released. If a new reset source is triggered, in a window of +// four 32 kHz periods after the previous has been released, this register +// may indicate Power on reset as source. +// ENUMs: +// WARMRESET Software reset via PRCM warm reset request +// SYSRESET Software reset via SYSRESET register +// CLK_LOSS Clock loss detect +// VDDR_LOSS Brown out detect on VDDR +// VDD_LOSS Brown out detect on VDD +// VDDS_LOSS Brown out detect on VDDS +// PIN_RESET Reset pin +// PWR_ON Power on reset +#define AON_SYSCTL_RESETCTL_RESET_SRC_W 3 +#define AON_SYSCTL_RESETCTL_RESET_SRC_M 0x0000000E +#define AON_SYSCTL_RESETCTL_RESET_SRC_S 1 +#define AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E +#define AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C +#define AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDD_LOSS 0x00000006 +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 +#define AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 +#define AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 + +//***************************************************************************** +// +// Register: AON_SYSCTL_O_SLEEPCTL +// +//***************************************************************************** +// Field: [0] IO_PAD_SLEEP_DIS +// +// Controls the I/O pad sleep mode. The boot code will set this bitfield +// automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is set +// ). +// +// 0: I/O pad sleep mode is enabled, ie all pads are latched and can not +// toggle. +// 1: I/O pad sleep mode is disabled +// +// Application software may want to reconfigure the state for all IO's before +// setting this bitfield upon waking up from a SHUTDOWN. +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 + + +#endif // __AON_SYSCTL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_wuc.h new file mode 100644 index 0000000..9642cae --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_wuc.h @@ -0,0 +1,674 @@ +/****************************************************************************** +* Filename: hw_aon_wuc_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_WUC_H__ +#define __HW_AON_WUC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_WUC component +// +//***************************************************************************** +// MCU Clock Management +#define AON_WUC_O_MCUCLK 0x00000000 + +// AUX Clock Management +#define AON_WUC_O_AUXCLK 0x00000004 + +// MCU Configuration +#define AON_WUC_O_MCUCFG 0x00000008 + +// AUX Configuration +#define AON_WUC_O_AUXCFG 0x0000000C + +// AUX Control +#define AON_WUC_O_AUXCTL 0x00000010 + +// Power Status +#define AON_WUC_O_PWRSTAT 0x00000014 + +// Shutdown Control +#define AON_WUC_O_SHUTDOWN 0x00000018 + +// Control 0 +#define AON_WUC_O_CTL0 0x00000020 + +// Control 1 +#define AON_WUC_O_CTL1 0x00000024 + +// Recharge Controller Configuration +#define AON_WUC_O_RECHARGECFG 0x00000030 + +// Recharge Controller Status +#define AON_WUC_O_RECHARGESTAT 0x00000034 + +// Oscillator Configuration +#define AON_WUC_O_OSCCFG 0x00000038 + +// JTAG Configuration +#define AON_WUC_O_JTAGCFG 0x00000040 + +// JTAG USERCODE +#define AON_WUC_O_JTAGUSERCODE 0x00000044 + +//***************************************************************************** +// +// Register: AON_WUC_O_MCUCLK +// +//***************************************************************************** +// Field: [2] RCOSC_HF_CAL_DONE +// +// MCU bootcode will set this bit when RCOSC_HF is calibrated. The FLASH can +// not be used until this bit is set. +// +// 1: RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up. +// 0: RCOSC_HF is not yet calibrated, ie FLASH must not assume that the SCLK_HF +// is safe +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE 0x00000004 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_BITN 2 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_M 0x00000004 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_S 2 + +// Field: [1:0] PWR_DWN_SRC +// +// Controls the clock source for the entire MCU domain while MCU is requesting +// powerdown. +// +// When MCU requests powerdown with SCLK_HF as source, then WUC will switch +// over to this clock source during powerdown, and automatically switch back to +// SCLK_HF when MCU is no longer requesting powerdown and system is back in +// active mode. +// ENUMs: +// SCLK_LF Use SCLK_LF in Powerdown +// NONE No clock in Powerdown +#define AON_WUC_MCUCLK_PWR_DWN_SRC_W 2 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_M 0x00000003 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_S 0 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_SCLK_LF 0x00000001 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AON_WUC_O_AUXCLK +// +//***************************************************************************** +// Field: [12:11] PWR_DWN_SRC +// +// When AUX requests powerdown with SCLK_HF as source, then WUC will switch +// over to this clock source during powerdown, and automatically switch back to +// SCLK_HF when AUX system is back in active mode +// ENUMs: +// SCLK_LF Use SCLK_LF in Powerdown +// NONE No clock in Powerdown +#define AON_WUC_AUXCLK_PWR_DWN_SRC_W 2 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_M 0x00001800 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_S 11 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_SCLK_LF 0x00000800 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_NONE 0x00000000 + +// Field: [10:8] SCLK_HF_DIV +// +// Select the AUX clock divider for SCLK_HF +// +// NB: It is not supported to change the AUX clock divider while SCLK_HF is +// active source for AUX +// ENUMs: +// DIV256 Divide by 256 +// DIV128 Divide by 128 +// DIV64 Divide by 64 +// DIV32 Divide by 32 +// DIV16 Divide by 16 +// DIV8 Divide by 8 +// DIV4 Divide by 4 +// DIV2 Divide by 2 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_W 3 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_M 0x00000700 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_S 8 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 0x00000700 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 0x00000600 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 0x00000500 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 0x00000400 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 0x00000300 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 0x00000200 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 0x00000100 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 0x00000000 + +// Field: [2:0] SRC +// +// Selects the clock source for AUX: +// +// NB: Switching the clock source is guaranteed to be glitchless +// ENUMs: +// SCLK_LF LF Clock (SCLK_LF) +// SCLK_HF HF Clock (SCLK_HF) +#define AON_WUC_AUXCLK_SRC_W 3 +#define AON_WUC_AUXCLK_SRC_M 0x00000007 +#define AON_WUC_AUXCLK_SRC_S 0 +#define AON_WUC_AUXCLK_SRC_SCLK_LF 0x00000004 +#define AON_WUC_AUXCLK_SRC_SCLK_HF 0x00000001 + +//***************************************************************************** +// +// Register: AON_WUC_O_MCUCFG +// +//***************************************************************************** +// Field: [17] VIRT_OFF +// +// Internal. Only to be used through TI provided API. +#define AON_WUC_MCUCFG_VIRT_OFF 0x00020000 +#define AON_WUC_MCUCFG_VIRT_OFF_BITN 17 +#define AON_WUC_MCUCFG_VIRT_OFF_M 0x00020000 +#define AON_WUC_MCUCFG_VIRT_OFF_S 17 + +// Field: [16] FIXED_WU_EN +// +// Internal. Only to be used through TI provided API. +#define AON_WUC_MCUCFG_FIXED_WU_EN 0x00010000 +#define AON_WUC_MCUCFG_FIXED_WU_EN_BITN 16 +#define AON_WUC_MCUCFG_FIXED_WU_EN_M 0x00010000 +#define AON_WUC_MCUCFG_FIXED_WU_EN_S 16 + +// Field: [3:0] SRAM_RET_EN +// +// MCU SRAM is partitioned into 4 banks . This register controls which of the +// banks that has retention during MCU power off +// ENUMs: +// RET_FULL Retention on for all banks (SRAM:BANK0, SRAM:BANK1 +// ,SRAM:BANK2 and SRAM:BANK3) +// RET_LEVEL3 Retention on for SRAM:BANK0, SRAM:BANK1 and +// SRAM:BANK2 +// RET_LEVEL2 Retention on for SRAM:BANK0 and SRAM:BANK1 +// RET_LEVEL1 Retention on for SRAM:BANK0 +// RET_NONE Retention is disabled +#define AON_WUC_MCUCFG_SRAM_RET_EN_W 4 +#define AON_WUC_MCUCFG_SRAM_RET_EN_M 0x0000000F +#define AON_WUC_MCUCFG_SRAM_RET_EN_S 0 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_FULL 0x0000000F +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL3 0x00000007 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL2 0x00000003 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL1 0x00000001 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AON_WUC_O_AUXCFG +// +//***************************************************************************** +// Field: [0] RAM_RET_EN +// +// This bit controls retention mode for the AUX_RAM:BANK0: +// +// 0: Retention is disabled +// 1: Retention is enabled +// +// NB: If retention is disabled, the AUX_RAM will be powered off when it would +// otherwise be put in retention mode +#define AON_WUC_AUXCFG_RAM_RET_EN 0x00000001 +#define AON_WUC_AUXCFG_RAM_RET_EN_BITN 0 +#define AON_WUC_AUXCFG_RAM_RET_EN_M 0x00000001 +#define AON_WUC_AUXCFG_RAM_RET_EN_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_AUXCTL +// +//***************************************************************************** +// Field: [31] RESET_REQ +// +// Reset request for AUX. Writing 1 to this register will assert reset to AUX. +// The reset will be held until the bit is cleared again. +// +// 0: AUX reset pin will be deasserted +// 1: AUX reset pin will be asserted +#define AON_WUC_AUXCTL_RESET_REQ 0x80000000 +#define AON_WUC_AUXCTL_RESET_REQ_BITN 31 +#define AON_WUC_AUXCTL_RESET_REQ_M 0x80000000 +#define AON_WUC_AUXCTL_RESET_REQ_S 31 + +// Field: [2] SCE_RUN_EN +// +// Enables (1) or disables (0) AUX_SCE execution. AUX_SCE execution will begin +// when AUX Domain is powered and either this or AUX_SCE:CTL.CLK_EN is set. +// +// Setting this bit will assure that AUX_SCE execution starts as soon as AUX +// power domain is woken up. ( AUX_SCE:CTL.CLK_EN will be reset to 0 if AUX +// power domain has been off) +// +// 0: AUX_SCE execution will be disabled if AUX_SCE:CTL.CLK_EN is 0 +// 1: AUX_SCE execution is enabled. +#define AON_WUC_AUXCTL_SCE_RUN_EN 0x00000004 +#define AON_WUC_AUXCTL_SCE_RUN_EN_BITN 2 +#define AON_WUC_AUXCTL_SCE_RUN_EN_M 0x00000004 +#define AON_WUC_AUXCTL_SCE_RUN_EN_S 2 + +// Field: [1] SWEV +// +// Writing 1 sets the software event to the AUX domain, which can be read +// through AUX_WUC:WUEVFLAGS.AON_SW. +// +// This event is normally cleared by AUX_SCE through the +// AUX_WUC:WUEVCLR.AON_SW. It can also be cleared by writing 0 to this +// register. +// +// Reading 0 means that there is no outstanding software event for AUX. +// +// Note that it can take up to 1,5 SCLK_LF clock cycles to clear the event from +// AUX. +#define AON_WUC_AUXCTL_SWEV 0x00000002 +#define AON_WUC_AUXCTL_SWEV_BITN 1 +#define AON_WUC_AUXCTL_SWEV_M 0x00000002 +#define AON_WUC_AUXCTL_SWEV_S 1 + +// Field: [0] AUX_FORCE_ON +// +// Forces the AUX domain into active mode, overriding the requests from +// AUX_WUC:PWROFFREQ, AUX_WUC:PWRDWNREQ and AUX_WUC:MCUBUSCTL. +// Note that an ongoing AUX_WUC:PWROFFREQ will complete before this bit will +// set the AUX domain into active mode. +// +// MCU must set this bit in order to access the AUX peripherals. +// The AUX domain status can be read from PWRSTAT.AUX_PD_ON +// +// 0: AUX is allowed to Power Off, Power Down or Disconnect. +// 1: AUX Power OFF, Power Down or Disconnect requests will be overruled +#define AON_WUC_AUXCTL_AUX_FORCE_ON 0x00000001 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_BITN 0 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_M 0x00000001 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_PWRSTAT +// +//***************************************************************************** +// Field: [9] AUX_PWR_DWN +// +// Indicates the AUX powerdown state when AUX domain is powered up. +// +// 0: Active mode +// 1: AUX Powerdown request has been granted +#define AON_WUC_PWRSTAT_AUX_PWR_DWN 0x00000200 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_BITN 9 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_M 0x00000200 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_S 9 + +// Field: [6] JTAG_PD_ON +// +// Indicates JTAG power state: +// +// 0: JTAG is powered off +// 1: JTAG is powered on +#define AON_WUC_PWRSTAT_JTAG_PD_ON 0x00000040 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_BITN 6 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_M 0x00000040 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_S 6 + +// Field: [5] AUX_PD_ON +// +// Indicates AUX power state: +// +// 0: AUX is not ready for use ( may be powered off or in power state +// transition ) +// 1: AUX is powered on, connected to bus and ready for use, +#define AON_WUC_PWRSTAT_AUX_PD_ON 0x00000020 +#define AON_WUC_PWRSTAT_AUX_PD_ON_BITN 5 +#define AON_WUC_PWRSTAT_AUX_PD_ON_M 0x00000020 +#define AON_WUC_PWRSTAT_AUX_PD_ON_S 5 + +// Field: [4] MCU_PD_ON +// +// Indicates MCU power state: +// +// 0: MCU Power sequencing is not yet finalized and MCU_AONIF registers may not +// be reliable +// 1: MCU Power sequencing is finalized and all MCU_AONIF registers are +// reliable +#define AON_WUC_PWRSTAT_MCU_PD_ON 0x00000010 +#define AON_WUC_PWRSTAT_MCU_PD_ON_BITN 4 +#define AON_WUC_PWRSTAT_MCU_PD_ON_M 0x00000010 +#define AON_WUC_PWRSTAT_MCU_PD_ON_S 4 + +// Field: [2] AUX_BUS_CONNECTED +// +// Indicates that AUX Bus is connected: +// +// 0: AUX bus is not connected +// 1: AUX bus is connected ( idle_ack = 0 ) +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED 0x00000004 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_BITN 2 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_M 0x00000004 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_S 2 + +// Field: [1] AUX_RESET_DONE +// +// Indicates Reset Done from AUX: +// +// 0: AUX is being reset +// 1: AUX reset is released +#define AON_WUC_PWRSTAT_AUX_RESET_DONE 0x00000002 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_BITN 1 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_M 0x00000002 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_S 1 + +//***************************************************************************** +// +// Register: AON_WUC_O_SHUTDOWN +// +//***************************************************************************** +// Field: [0] EN +// +// Writing a 1 to this bit forces a shutdown request to be registered and all +// I/O values to be latched - in the PAD ring, possibly enabling I/O wakeup. +// Writing 0 will cancel a registered shutdown request and open th I/O latches +// residing in the PAD ring. +// +// A registered shutdown request takes effect the next time power down +// conditions exists. At this time, the will not enter Powerdown mode, but +// instead it will turn off all internal powersupplies, effectively putting the +// device into Shutdown mode. +#define AON_WUC_SHUTDOWN_EN 0x00000001 +#define AON_WUC_SHUTDOWN_EN_BITN 0 +#define AON_WUC_SHUTDOWN_EN_M 0x00000001 +#define AON_WUC_SHUTDOWN_EN_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_CTL0 +// +//***************************************************************************** +// Field: [8] PWR_DWN_DIS +// +// Controls whether MCU and AUX requesting to be powered off will enable a +// transition to powerdown: +// +// 0: Enabled +// 1: Disabled +#define AON_WUC_CTL0_PWR_DWN_DIS 0x00000100 +#define AON_WUC_CTL0_PWR_DWN_DIS_BITN 8 +#define AON_WUC_CTL0_PWR_DWN_DIS_M 0x00000100 +#define AON_WUC_CTL0_PWR_DWN_DIS_S 8 + +// Field: [3] AUX_SRAM_ERASE +// +// Internal. Only to be used through TI provided API. +#define AON_WUC_CTL0_AUX_SRAM_ERASE 0x00000008 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_BITN 3 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_M 0x00000008 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_S 3 + +// Field: [2] MCU_SRAM_ERASE +// +// Internal. Only to be used through TI provided API. +#define AON_WUC_CTL0_MCU_SRAM_ERASE 0x00000004 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_BITN 2 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_M 0x00000004 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_S 2 + +//***************************************************************************** +// +// Register: AON_WUC_O_CTL1 +// +//***************************************************************************** +// Field: [1] MCU_RESET_SRC +// +// Indicates source of last MCU Voltage Domain warm reset request: +// +// 0: MCU SW reset +// 1: JTAG reset +// +// This bit can only be cleared by writing a 1 to it +#define AON_WUC_CTL1_MCU_RESET_SRC 0x00000002 +#define AON_WUC_CTL1_MCU_RESET_SRC_BITN 1 +#define AON_WUC_CTL1_MCU_RESET_SRC_M 0x00000002 +#define AON_WUC_CTL1_MCU_RESET_SRC_S 1 + +// Field: [0] MCU_WARM_RESET +// +// Indicates type of last MCU Voltage Domain reset: +// +// 0: Last MCU reset was not a warm reset +// 1: Last MCU reset was a warm reset (requested from MCU or JTAG as indicated +// in MCU_RESET_SRC) +// +// This bit can only be cleared by writing a 1 to it +#define AON_WUC_CTL1_MCU_WARM_RESET 0x00000001 +#define AON_WUC_CTL1_MCU_WARM_RESET_BITN 0 +#define AON_WUC_CTL1_MCU_WARM_RESET_M 0x00000001 +#define AON_WUC_CTL1_MCU_WARM_RESET_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_RECHARGECFG +// +//***************************************************************************** +// Field: [31] ADAPTIVE_EN +// +// Enable adaptive recharge +// +// Note: Recharge can be turned completely of by setting MAX_PER_E=7 and +// MAX_PER_M=31 and this bitfield to 0 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN 0x80000000 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_BITN 31 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_M 0x80000000 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_S 31 + +// Field: [23:20] C2 +// +// Gain factor for adaptive recharge algorithm +// +// period_new=period * ( 1+/-(2^-C1+2^-C2) ) +// Valid values for C2 is 2 to 10 +// +// Note: Rounding may cause adaptive recharge not to start for very small +// values of both Gain and Initial period. Criteria for algorithm to start is +// MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 +#define AON_WUC_RECHARGECFG_C2_W 4 +#define AON_WUC_RECHARGECFG_C2_M 0x00F00000 +#define AON_WUC_RECHARGECFG_C2_S 20 + +// Field: [19:16] C1 +// +// Gain factor for adaptive recharge algorithm +// +// period_new=period * ( 1+/-(2^-C1+2^-C2) ) +// Valid values for C1 is 1 to 10 +// +// Note: Rounding may cause adaptive recharge not to start for very small +// values of both Gain and Initial period. Criteria for algorithm to start is +// MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 +#define AON_WUC_RECHARGECFG_C1_W 4 +#define AON_WUC_RECHARGECFG_C1_M 0x000F0000 +#define AON_WUC_RECHARGECFG_C1_S 16 + +// Field: [15:11] MAX_PER_M +// +// This register defines the maximum period that the recharge algorithm can +// take, i.e. it defines the maximum number of cycles between 2 recharges. +// The maximum number of cycles is specified with a 5 bit mantissa and 3 bit +// exponent: +// MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E +// This field sets the mantissa of MAXCYCLES +#define AON_WUC_RECHARGECFG_MAX_PER_M_W 5 +#define AON_WUC_RECHARGECFG_MAX_PER_M_M 0x0000F800 +#define AON_WUC_RECHARGECFG_MAX_PER_M_S 11 + +// Field: [10:8] MAX_PER_E +// +// This register defines the maximum period that the recharge algorithm can +// take, i.e. it defines the maximum number of cycles between 2 recharges. +// The maximum number of cycles is specified with a 5 bit mantissa and 3 bit +// exponent: +// MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E +// This field sets the exponent MAXCYCLES +#define AON_WUC_RECHARGECFG_MAX_PER_E_W 3 +#define AON_WUC_RECHARGECFG_MAX_PER_E_M 0x00000700 +#define AON_WUC_RECHARGECFG_MAX_PER_E_S 8 + +// Field: [7:3] PER_M +// +// Number of 32 KHz clocks between activation of recharge controller +// For recharge algorithm, PERIOD is the initial period when entering powerdown +// mode. The adaptive recharge algorithm will not change this register +// PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 +// bit exponent: +// This field sets the Mantissa of the Period. +// PERIOD=(PER_M*16+15)*2^PER_E +#define AON_WUC_RECHARGECFG_PER_M_W 5 +#define AON_WUC_RECHARGECFG_PER_M_M 0x000000F8 +#define AON_WUC_RECHARGECFG_PER_M_S 3 + +// Field: [2:0] PER_E +// +// Number of 32 KHz clocks between activation of recharge controller +// For recharge algorithm, PERIOD is the initial period when entering powerdown +// mode. The adaptive recharge algorithm will not change this register +// PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 +// bit exponent: +// This field sets the Exponent of the Period. +// PERIOD=(PER_M*16+15)*2^PER_E +#define AON_WUC_RECHARGECFG_PER_E_W 3 +#define AON_WUC_RECHARGECFG_PER_E_M 0x00000007 +#define AON_WUC_RECHARGECFG_PER_E_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_RECHARGESTAT +// +//***************************************************************************** +// Field: [19:16] VDDR_SMPLS +// +// The last 4 VDDR samples, bit 0 being the newest. +// +// The register is being updated in every recharge period with a shift left, +// and bit 0 is updated with the last VDDR sample, ie a 1 is shiftet in in case +// VDDR > VDDR_threshold just before recharge starts. Otherwise a 0 will be +// shifted in. +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_W 4 +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_S 16 + +// Field: [15:0] MAX_USED_PER +// +// The maximum value of recharge period seen with VDDR>threshold. +// +// The VDDR voltage is compared against the threshold voltage at just before +// each recharge. If VDDR is above threshold, MAX_USED_PER is updated with max +// ( current recharge peride; MAX_USED_PER ) This way MAX_USED_PER can track +// the recharge period where VDDR is decharged to the threshold value. We can +// therefore use the value as an indication of the leakage current during +// recharge. +// +// This bitfield is cleared to 0 when writing this register. +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_W 16 +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_OSCCFG +// +//***************************************************************************** +// Field: [7:3] PER_M +// +// Number of 32 KHz clocks between oscillator amplitude calibrations. +// When this counter expires, an oscillator amplitude compensation is triggered +// immediately in Active mode. When this counter expires in Powerdown mode an +// internal flag is set such that the amplitude compensation is postponed until +// the next recharge occurs. +// +// The Period will effectively be a 16 bit value coded in a 5 bit mantissa and +// 3 bit exponent +// PERIOD=(PER_M*16+15)*2^PER_E +// This field sets the mantissa +// Note: Oscillator amplitude calibration is turned of when both this bitfield +// and PER_E are set to 0 +#define AON_WUC_OSCCFG_PER_M_W 5 +#define AON_WUC_OSCCFG_PER_M_M 0x000000F8 +#define AON_WUC_OSCCFG_PER_M_S 3 + +// Field: [2:0] PER_E +// +// Number of 32 KHz clocks between oscillator amplitude calibrations. +// When this counter expires, an oscillator amplitude compensation is triggered +// immediately in Active mode. When this counter expires in Powerdown mode an +// internal flag is set such that the amplitude compensation is postponed until +// the next recharge occurs. +// The Period will effectively be a 16 bit value coded in a 5 bit mantissa and +// 3 bit exponent +// PERIOD=(PER_M*16+15)*2^PER_E +// This field sets the exponent +// Note: Oscillator amplitude calibration is turned of when both PER_M and +// this bitfield are set to 0 +#define AON_WUC_OSCCFG_PER_E_W 3 +#define AON_WUC_OSCCFG_PER_E_M 0x00000007 +#define AON_WUC_OSCCFG_PER_E_S 0 + +//***************************************************************************** +// +// Register: AON_WUC_O_JTAGCFG +// +//***************************************************************************** +// Field: [8] JTAG_PD_FORCE_ON +// +// Controls JTAG PowerDomain power state: +// +// 0: Controlled exclusively by debug subsystem. (JTAG Powerdomain will be +// powered off unless a debugger is attached) +// 1: JTAG Power Domain is forced on, independent of debug subsystem. +// +// NB: The reset value causes JTAG Power Domain to be powered on by default. +// Software must clear this bit to turn off the JTAG Power Domain +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_S 8 + +//***************************************************************************** +// +// Register: AON_WUC_O_JTAGUSERCODE +// +//***************************************************************************** +// Field: [31:0] USER_CODE +// +// 32-bit JTAG USERCODE register feeding main JTAG TAP +// NB: This field can be locked +#define AON_WUC_JTAGUSERCODE_USER_CODE_W 32 +#define AON_WUC_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF +#define AON_WUC_JTAGUSERCODE_USER_CODE_S 0 + + +#endif // __AON_WUC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_aiodio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_aiodio.h new file mode 100644 index 0000000..7d6b08f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_aiodio.h @@ -0,0 +1,481 @@ +/****************************************************************************** +* Filename: hw_aux_aiodio_h +* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) +* Revision: 49005 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_AIODIO_H__ +#define __HW_AUX_AIODIO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_AIODIO component +// +//***************************************************************************** +// General Purpose Input Output Data Out +#define AUX_AIODIO_O_GPIODOUT 0x00000000 + +// Input Output Mode +#define AUX_AIODIO_O_IOMODE 0x00000004 + +// General Purpose Input Output Data In +#define AUX_AIODIO_O_GPIODIN 0x00000008 + +// General Purpose Input Output Data Out Set +#define AUX_AIODIO_O_GPIODOUTSET 0x0000000C + +// General Purpose Input Output Data Out Clear +#define AUX_AIODIO_O_GPIODOUTCLR 0x00000010 + +// General Purpose Input Output Data Out Toggle +#define AUX_AIODIO_O_GPIODOUTTGL 0x00000014 + +// General Purpose Input Output Digital Input Enable +#define AUX_AIODIO_O_GPIODIE 0x00000018 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUT +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. +// Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. +#define AUX_AIODIO_GPIODOUT_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUT_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IOMODE +// +//***************************************************************************** +// Field: [15:14] IO7 +// +// Select mode for AUXIO[8i+7]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 7 is 0: +// AUXIO[8i+7] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 7 is 1: +// AUXIO[8i+7] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 7 is 0: +// AUXIO[8i+7] is driven low. +// +// When GPIODOUT bit 7 is 1: +// AUXIO[8i+7] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 7 is 0: +// AUXIO[8i+7] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 7 is 1: +// AUXIO[8i+7] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 7 drives +// AUXIO[8i+7]. +#define AUX_AIODIO_IOMODE_IO7_W 2 +#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_S 14 +#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 +#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 +#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 + +// Field: [13:12] IO6 +// +// Select mode for AUXIO[8i+6]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 6 is 0: +// AUXIO[8i+6] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 6 is 1: +// AUXIO[8i+6] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 6 is 0: +// AUXIO[8i+6] is driven low. +// +// When GPIODOUT bit 6 is 1: +// AUXIO[8i+6] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 6 is 0: +// AUXIO[8i+6] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 6 is 1: +// AUXIO[8i+6] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 6 drives +// AUXIO[8i+6]. +#define AUX_AIODIO_IOMODE_IO6_W 2 +#define AUX_AIODIO_IOMODE_IO6_M 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_S 12 +#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 +#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 +#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 + +// Field: [11:10] IO5 +// +// Select mode for AUXIO[8i+5]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 5 is 0: +// AUXIO[8i+5] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 5 is 1: +// AUXIO[8i+5] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 5 is 0: +// AUXIO[8i+5] is driven low. +// +// When GPIODOUT bit 5 is 1: +// AUXIO[8i+5] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 5 is 0: +// AUXIO[8i+5] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 5 is 1: +// AUXIO[8i+5] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 5 drives +// AUXIO[8i+5]. +#define AUX_AIODIO_IOMODE_IO5_W 2 +#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_S 10 +#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 +#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 +#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 + +// Field: [9:8] IO4 +// +// Select mode for AUXIO[8i+4]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 4 is 0: +// AUXIO[8i+4] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 4 is 1: +// AUXIO[8i+4] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 4 is 0: +// AUXIO[8i+4] is driven low. +// +// When GPIODOUT bit 4 is 1: +// AUXIO[8i+4] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 4 is 0: +// AUXIO[8i+4] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 4 is 1: +// AUXIO[8i+4] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 4 drives +// AUXIO[8i+4]. +#define AUX_AIODIO_IOMODE_IO4_W 2 +#define AUX_AIODIO_IOMODE_IO4_M 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_S 8 +#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 +#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 +#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 + +// Field: [7:6] IO3 +// +// Select mode for AUXIO[8i+3]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 3 is 0: +// AUXIO[8i+3] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 3 is 1: +// AUXIO[8i+3] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 3 is 0: +// AUXIO[8i+3] is driven low. +// +// When GPIODOUT bit 3 is 1: +// AUXIO[8i+3] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 3 is 0: +// AUXIO[8i+3] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 3 is 1: +// AUXIO[8i+3] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 3 drives +// AUXIO[8i+3]. +#define AUX_AIODIO_IOMODE_IO3_W 2 +#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_S 6 +#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 +#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 +#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 + +// Field: [5:4] IO2 +// +// Select mode for AUXIO[8i+2]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 2 is 0: +// AUXIO[8i+2] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 2 is 1: +// AUXIO[8i+2] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 2 is 0: +// AUXIO[8i+2] is driven low. +// +// When GPIODOUT bit 2 is 1: +// AUXIO[8i+2] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 2 is 0: +// AUXIO[8i+2] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 2 is 1: +// AUXIO[8i+2] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 2 drives +// AUXIO[8i+2]. +#define AUX_AIODIO_IOMODE_IO2_W 2 +#define AUX_AIODIO_IOMODE_IO2_M 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_S 4 +#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 +#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 +#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 + +// Field: [3:2] IO1 +// +// Select mode for AUXIO[8i+1]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 1 is 0: +// AUXIO[8i+1] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 1 is 1: +// AUXIO[8i+1] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 1 is 0: +// AUXIO[8i+1] is driven low. +// +// When GPIODOUT bit 1 is 1: +// AUXIO[8i+1] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 1 is 0: +// AUXIO[8i+1] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 1 is 1: +// AUXIO[8i+1] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 1 drives +// AUXIO[8i+1]. +#define AUX_AIODIO_IOMODE_IO1_W 2 +#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_S 2 +#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 +#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 +#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 + +// Field: [1:0] IO0 +// +// Select mode for AUXIO[8i+0]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When GPIODOUT bit 0 is 0: +// AUXIO[8i+0] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When GPIODOUT bit 0 is 1: +// AUXIO[8i+0] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When GPIODOUT bit 0 is 0: +// AUXIO[8i+0] is driven low. +// +// When GPIODOUT bit 0 is 1: +// AUXIO[8i+0] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 0 is 0: +// AUXIO[8i+0] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 0 is 1: +// AUXIO[8i+0] is enabled for digital input. +// OUT Output Mode: +// +// GPIODOUT bit 0 drives +// AUXIO[8i+0]. +#define AUX_AIODIO_IOMODE_IO0_W 2 +#define AUX_AIODIO_IOMODE_IO0_M 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_S 0 +#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 +#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 +#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODIN +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit +// n is set. Otherwise, bit n value is old. +#define AUX_AIODIO_GPIODIN_IO7_0_W 8 +#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIN_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTSET +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to set GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTCLR +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTTGL +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODIE +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to enable digital input buffer for +// AUXIO[8i+n]. +// Write 0 to bit index n in this bit vector to disable digital input buffer +// for AUXIO[8i+n]. +// +// You must enable the digital input buffer for AUXIO[8i+n] to read the pin +// value in GPIODIN. +// You must disable the digital input buffer for analog input or pins that +// float to avoid current leakage. +#define AUX_AIODIO_GPIODIE_IO7_0_W 8 +#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIE_IO7_0_S 0 + + +#endif // __AUX_AIODIO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_anaif.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_anaif.h new file mode 100644 index 0000000..f96db07 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_anaif.h @@ -0,0 +1,305 @@ +/****************************************************************************** +* Filename: hw_aux_anaif_h +* Revised: 2017-05-30 11:42:02 +0200 (Tue, 30 May 2017) +* Revision: 49074 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_ANAIF_H__ +#define __HW_AUX_ANAIF_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_ANAIF component +// +//***************************************************************************** +// ADC Control +#define AUX_ANAIF_O_ADCCTL 0x00000010 + +// ADC FIFO Status +#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 + +// ADC FIFO +#define AUX_ANAIF_O_ADCFIFO 0x00000018 + +// ADC Trigger +#define AUX_ANAIF_O_ADCTRIG 0x0000001C + +// Current Source Control +#define AUX_ANAIF_O_ISRCCTL 0x00000020 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCCTL +// +//***************************************************************************** +// Field: [13] START_POL +// +// Select active polarity for START_SRC event. +// ENUMs: +// FALL Set ADC trigger on falling edge of event source. +// RISE Set ADC trigger on rising edge of event source. +#define AUX_ANAIF_ADCCTL_START_POL 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_BITN 13 +#define AUX_ANAIF_ADCCTL_START_POL_M 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_S 13 +#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 + +// Field: [12:8] START_SRC +// +// Select ADC trigger event source from the asynchronous AUX event bus. +// +// Set START_SRC to NO_EVENT if you want to trigger the ADC manually through +// ADCTRIG.START. +// ENUMs: +// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ +// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// NO_EVENT1 No event. +// NO_EVENT0 No event. +// RESERVED1 Reserved - Do not use. +// RESERVED0 Reserved - Do not use. +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// TDC_DONE AUX_EVCTL:EVSTAT0.TDC_DONE +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_ANAIF_ADCCTL_START_SRC_W 5 +#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00001F00 +#define AUX_ANAIF_ADCCTL_START_SRC_S 8 +#define AUX_ANAIF_ADCCTL_START_SRC_ADC_IRQ 0x00001F00 +#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00001E00 +#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00001D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00001C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00001B00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00001A00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00001900 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00001800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00001700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00001600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00001500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00001400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00001300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00001200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00001100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00001000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000E00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_PROG_WU 0x00000C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_SW 0x00000B00 +#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT1 0x00000A00 +#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 0x00000900 +#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED1 0x00000800 +#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED0 0x00000700 +#define AUX_ANAIF_ADCCTL_START_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_ANAIF_ADCCTL_START_SRC_TIMER1_EV 0x00000500 +#define AUX_ANAIF_ADCCTL_START_SRC_TIMER0_EV 0x00000400 +#define AUX_ANAIF_ADCCTL_START_SRC_TDC_DONE 0x00000300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00000200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00000100 +#define AUX_ANAIF_ADCCTL_START_SRC_RTC_CH2_EV 0x00000000 + +// Field: [1:0] CMD +// +// ADC interface command. +// +// Non-enumerated values are not supported. The written value is returned when +// read. +// ENUMs: +// FLUSH Flush ADC FIFO. +// +// You must set CMD to EN or +// DIS after flush. +// +// System CPU must wait two +// clock cycles before it sets CMD to EN or DIS. +// EN Enable ADC interface. +// DIS Disable ADC interface. +#define AUX_ANAIF_ADCCTL_CMD_W 2 +#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_S 0 +#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 +#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCFIFOSTAT +// +//***************************************************************************** +// Field: [4] OVERFLOW +// +// FIFO overflow flag. +// +// 0: FIFO has not overflowed. +// 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. +// +// When the flag is set, the ADC FIFO write pointer is static. It is not +// possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 + +// Field: [3] UNDERFLOW +// +// FIFO underflow flag. +// +// 0: FIFO has not underflowed. +// 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. +// +// When the flag is set, the ADC FIFO read pointer is static. Read returns the +// previous sample that was read. Flush FIFO to clear the flag. +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 + +// Field: [2] FULL +// +// FIFO full flag. +// +// 0: FIFO is not full, there is less than 4 samples in the FIFO. +// 1: FIFO is full, there are 4 samples in the FIFO. +// +// When the flag is set, it is not possible to add more samples to the ADC +// FIFO. An attempt to add samples sets the OVERFLOW flag. +#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 + +// Field: [1] ALMOST_FULL +// +// FIFO almost full flag. +// +// 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL +// flag is also asserted in the latter case. +// 1: There are 3 samples in the FIFO, there is room for one more sample. +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 + +// Field: [0] EMPTY +// +// FIFO empty flag. +// +// 0: FIFO contains one or more samples. +// 1: FIFO is empty. +// +// When the flag is set, read returns the previous sample that was read and +// sets the UNDERFLOW flag. +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCFIFO +// +//***************************************************************************** +// Field: [11:0] DATA +// +// FIFO data. +// +// Read: +// Get oldest ADC sample from FIFO. +// +// Write: +// Write dummy sample to FIFO. This is useful for code development when you do +// not have real ADC samples. +#define AUX_ANAIF_ADCFIFO_DATA_W 12 +#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF +#define AUX_ANAIF_ADCFIFO_DATA_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCTRIG +// +//***************************************************************************** +// Field: [0] START +// +// Manual ADC trigger. +// +// 0: No effect. +// 1: Single ADC trigger. +// +// To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to +// avoid conflict with event-driven ADC trigger. +#define AUX_ANAIF_ADCTRIG_START 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_BITN 0 +#define AUX_ANAIF_ADCTRIG_START_M 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ISRCCTL +// +//***************************************************************************** +// Field: [0] RESET_N +// +// ISRC reset control. +// +// 0: ISRC drives 0 uA. +// 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. +#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 +#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_S 0 + + +#endif // __AUX_ANAIF__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_evctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_evctl.h new file mode 100644 index 0000000..0969dfc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_evctl.h @@ -0,0 +1,1852 @@ +/****************************************************************************** +* Filename: hw_aux_evctl_h +* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) +* Revision: 49005 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_EVCTL_H__ +#define __HW_AUX_EVCTL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_EVCTL component +// +//***************************************************************************** +// Vector Configuration 0 +#define AUX_EVCTL_O_VECCFG0 0x00000000 + +// Vector Configuration 1 +#define AUX_EVCTL_O_VECCFG1 0x00000004 + +// Sensor Controller Engine Wait Event Selection +#define AUX_EVCTL_O_SCEWEVSEL 0x00000008 + +// Events To AON Flags +#define AUX_EVCTL_O_EVTOAONFLAGS 0x0000000C + +// Events To AON Polarity +#define AUX_EVCTL_O_EVTOAONPOL 0x00000010 + +// Direct Memory Access Control +#define AUX_EVCTL_O_DMACTL 0x00000014 + +// Software Event Set +#define AUX_EVCTL_O_SWEVSET 0x00000018 + +// Event Status 0 +#define AUX_EVCTL_O_EVSTAT0 0x0000001C + +// Event Status 1 +#define AUX_EVCTL_O_EVSTAT1 0x00000020 + +// Event To MCU Polarity +#define AUX_EVCTL_O_EVTOMCUPOL 0x00000024 + +// Events to MCU Flags +#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000028 + +// Combined Event To MCU Mask +#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000002C + +// Vector Flags +#define AUX_EVCTL_O_VECFLAGS 0x00000034 + +// Events To MCU Flags Clear +#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038 + +// Events To AON Clear +#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000003C + +// Vector Flags Clear +#define AUX_EVCTL_O_VECFLAGSCLR 0x00000040 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_VECCFG0 +// +//***************************************************************************** +// Field: [14] VEC1_POL +// +// Vector 1 trigger event polarity. +// +// To manually trigger vector 1 execution: +// - AUX_SCE must sleep. +// - Set VEC1_EV to a known static value. +// - Toggle VEC1_POL twice. +// ENUMs: +// FALL Falling edge triggers vector 1 execution. +// RISE Rising edge triggers vector 1 execution. +#define AUX_EVCTL_VECCFG0_VEC1_POL 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_BITN 14 +#define AUX_EVCTL_VECCFG0_VEC1_POL_M 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_S 14 +#define AUX_EVCTL_VECCFG0_VEC1_POL_FALL 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_RISE 0x00000000 + +// Field: [13] VEC1_EN +// +// Vector 1 trigger enable. +// +// When enabled, VEC1_EV event with VEC1_POL polarity triggers a jump to vector +// # 1 when AUX_SCE sleeps. +// +// Lower vectors (0) have priority. +// ENUMs: +// EN Enable vector 1 trigger. +// DIS Disable vector 1 trigger. +#define AUX_EVCTL_VECCFG0_VEC1_EN 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_BITN 13 +#define AUX_EVCTL_VECCFG0_VEC1_EN_M 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_S 13 +#define AUX_EVCTL_VECCFG0_VEC1_EN_EN 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_DIS 0x00000000 + +// Field: [12:8] VEC1_EV +// +// Select vector 1 trigger source event. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_VECCFG0_VEC1_EV_W 5 +#define AUX_EVCTL_VECCFG0_VEC1_EV_M 0x00001F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_S 8 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_IRQ 0x00001F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_MCU_EV 0x00001E00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ACLK_REF 0x00001D00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO15 0x00001C00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO14 0x00001B00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO13 0x00001A00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO12 0x00001900 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO11 0x00001800 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO10 0x00001700 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO9 0x00001600 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO8 0x00001500 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO7 0x00001400 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO6 0x00001300 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO5 0x00001200 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO4 0x00001100 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO3 0x00001000 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO2 0x00000F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO1 0x00000E00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO0 0x00000D00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_PROG_WU 0x00000C00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_SW 0x00000B00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX1 0x00000A00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX0 0x00000900 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_DONE 0x00000700 +#define AUX_EVCTL_VECCFG0_VEC1_EV_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER1_EV 0x00000500 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER0_EV 0x00000400 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TDC_DONE 0x00000300 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPB 0x00000200 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPA 0x00000100 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_RTC_CH2 0x00000000 + +// Field: [6] VEC0_POL +// +// Vector 0 trigger event polarity. +// +// To manually trigger vector 0 execution: +// - AUX_SCE must sleep. +// - Set VEC0_EV to a known static value. +// - Toggle VEC0_POL twice. +// ENUMs: +// FALL Falling edge triggers vector 0 execution. +// RISE Rising edge triggers vector 0 execution. +#define AUX_EVCTL_VECCFG0_VEC0_POL 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_BITN 6 +#define AUX_EVCTL_VECCFG0_VEC0_POL_M 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_S 6 +#define AUX_EVCTL_VECCFG0_VEC0_POL_FALL 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_RISE 0x00000000 + +// Field: [5] VEC0_EN +// +// Vector 0 trigger enable. +// +// When enabled, VEC0_EV event with VEC0_POL polarity triggers a jump to vector +// # 0 when AUX_SCE sleeps. +// ENUMs: +// EN Enable vector 0 trigger. +// DIS Disable vector 0 trigger. +#define AUX_EVCTL_VECCFG0_VEC0_EN 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_BITN 5 +#define AUX_EVCTL_VECCFG0_VEC0_EN_M 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_S 5 +#define AUX_EVCTL_VECCFG0_VEC0_EN_EN 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_DIS 0x00000000 + +// Field: [4:0] VEC0_EV +// +// Select vector 0 trigger source event. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_VECCFG0_VEC0_EV_W 5 +#define AUX_EVCTL_VECCFG0_VEC0_EV_M 0x0000001F +#define AUX_EVCTL_VECCFG0_VEC0_EV_S 0 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_VECCFG0_VEC0_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_VECCFG0_VEC0_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_SW 0x0000000B +#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_VECCFG0_VEC0_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_VECCFG1 +// +//***************************************************************************** +// Field: [14] VEC3_POL +// +// Vector 3 trigger event polarity. +// +// To manually trigger vector 3 execution: +// - AUX_SCE must sleep. +// - Set VEC3_EV to a known static value. +// - Toggle VEC3_POL twice. +// ENUMs: +// FALL Falling edge triggers vector 3 execution. +// RISE Rising edge triggers vector 3 execution. +#define AUX_EVCTL_VECCFG1_VEC3_POL 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_BITN 14 +#define AUX_EVCTL_VECCFG1_VEC3_POL_M 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_S 14 +#define AUX_EVCTL_VECCFG1_VEC3_POL_FALL 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_RISE 0x00000000 + +// Field: [13] VEC3_EN +// +// Vector 3 trigger enable. +// +// When enabled, VEC3_EV event with VEC3_POL polarity triggers a jump to vector +// # 3 when AUX_SCE sleeps. +// +// Lower vectors (0, 1, and 2) have priority. +// ENUMs: +// EN Enable vector 3 trigger. +// DIS Disable vector 3 trigger. +#define AUX_EVCTL_VECCFG1_VEC3_EN 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_BITN 13 +#define AUX_EVCTL_VECCFG1_VEC3_EN_M 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_S 13 +#define AUX_EVCTL_VECCFG1_VEC3_EN_EN 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_DIS 0x00000000 + +// Field: [12:8] VEC3_EV +// +// Select vector 3 trigger source event. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_VECCFG1_VEC3_EV_W 5 +#define AUX_EVCTL_VECCFG1_VEC3_EV_M 0x00001F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_S 8 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_IRQ 0x00001F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_MCU_EV 0x00001E00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ACLK_REF 0x00001D00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO15 0x00001C00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO14 0x00001B00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO13 0x00001A00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO12 0x00001900 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO11 0x00001800 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO10 0x00001700 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO9 0x00001600 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO8 0x00001500 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO7 0x00001400 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO6 0x00001300 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO5 0x00001200 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO4 0x00001100 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO3 0x00001000 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO2 0x00000F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO1 0x00000E00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO0 0x00000D00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_PROG_WU 0x00000C00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_SW 0x00000B00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX1 0x00000A00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX0 0x00000900 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_DONE 0x00000700 +#define AUX_EVCTL_VECCFG1_VEC3_EV_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER1_EV 0x00000500 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER0_EV 0x00000400 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TDC_DONE 0x00000300 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPB 0x00000200 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPA 0x00000100 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_RTC_CH2 0x00000000 + +// Field: [6] VEC2_POL +// +// Vector 2 trigger event polarity. +// +// To manually trigger vector 2 execution: +// - AUX_SCE must sleep. +// - Set VEC2_EV to a known static value. +// - Toggle VEC2_POL twice. +// ENUMs: +// FALL Falling edge triggers vector 2 execution. +// RISE Rising edge triggers vector 2 execution. +#define AUX_EVCTL_VECCFG1_VEC2_POL 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_BITN 6 +#define AUX_EVCTL_VECCFG1_VEC2_POL_M 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_S 6 +#define AUX_EVCTL_VECCFG1_VEC2_POL_FALL 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_RISE 0x00000000 + +// Field: [5] VEC2_EN +// +// Vector 2 trigger enable. +// +// When enabled, VEC2_EV event with VEC2_POL polarity triggers a jump to vector +// # 2 when AUX_SCE sleeps. +// +// Lower vectors (0 and 1) have priority. +// ENUMs: +// EN Enable vector 2 trigger. +// DIS Disable vector 2 trigger. +#define AUX_EVCTL_VECCFG1_VEC2_EN 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_BITN 5 +#define AUX_EVCTL_VECCFG1_VEC2_EN_M 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_S 5 +#define AUX_EVCTL_VECCFG1_VEC2_EN_EN 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_DIS 0x00000000 + +// Field: [4:0] VEC2_EV +// +// Select vector 2 trigger source event. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_VECCFG1_VEC2_EV_W 5 +#define AUX_EVCTL_VECCFG1_VEC2_EV_M 0x0000001F +#define AUX_EVCTL_VECCFG1_VEC2_EV_S 0 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_VECCFG1_VEC2_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_VECCFG1_VEC2_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_SW 0x0000000B +#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_VECCFG1_VEC2_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_SCEWEVSEL +// +//***************************************************************************** +// Field: [4:0] WEV7_EV +// +// Select event source to connect to AUX_SCE:WUSTAT.EV_SIGNALS bit 7. +// ENUMs: +// ADC_IRQ EVSTAT1.ADC_IRQ +// MCU_EV EVSTAT1.MCU_EV +// ACLK_REF EVSTAT1.ACLK_REF +// AUXIO15 EVSTAT1.AUXIO15 +// AUXIO14 EVSTAT1.AUXIO14 +// AUXIO13 EVSTAT1.AUXIO13 +// AUXIO12 EVSTAT1.AUXIO12 +// AUXIO11 EVSTAT1.AUXIO11 +// AUXIO10 EVSTAT1.AUXIO10 +// AUXIO9 EVSTAT1.AUXIO9 +// AUXIO8 EVSTAT1.AUXIO8 +// AUXIO7 EVSTAT1.AUXIO7 +// AUXIO6 EVSTAT1.AUXIO6 +// AUXIO5 EVSTAT1.AUXIO5 +// AUXIO4 EVSTAT1.AUXIO4 +// AUXIO3 EVSTAT1.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +// AON_PROG_WU EVSTAT0.AON_PROG_WU +// AON_SW EVSTAT0.AON_SW +// OBSMUX1 EVSTAT0.OBSMUX1 +// OBSMUX0 EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV EVSTAT0.TIMER1_EV +// TIMER0_EV EVSTAT0.TIMER0_EV +// TDC_DONE EVSTAT0.TDC_DONE +// AUX_COMPB EVSTAT0.AUX_COMPB +// AUX_COMPA EVSTAT0.AUX_COMPA +// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_W 5 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_M 0x0000001F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_S 0 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_SW 0x0000000B +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONFLAGS +// +//***************************************************************************** +// Field: [8] TIMER1_EV +// +// This event flag is set when level selected by EVTOAONPOL.TIMER1_EV occurs on +// EVSTAT0.TIMER1_EV. +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_S 8 + +// Field: [7] TIMER0_EV +// +// This event flag is set when level selected by EVTOAONPOL.TIMER0_EV occurs on +// EVSTAT0.TIMER0_EV. +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_S 7 + +// Field: [6] TDC_DONE +// +// This event flag is set when level selected by EVTOAONPOL.TDC_DONE occurs on +// EVSTAT0.TDC_DONE. +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_S 6 + +// Field: [5] ADC_DONE +// +// This event flag is set when level selected by EVTOAONPOL.ADC_DONE occurs on +// EVSTAT0.ADC_DONE. +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_S 5 + +// Field: [4] AUX_COMPB +// +// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on +// EVSTAT0.AUX_COMPB. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4 + +// Field: [3] AUX_COMPA +// +// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on +// EVSTAT0.AUX_COMPA. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3 + +// Field: [2] SWEV2 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV2. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV1. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV0. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONPOL +// +//***************************************************************************** +// Field: [8] TIMER1_EV +// +// Select the level of EVSTAT0.TIMER1_EV that sets EVTOAONFLAGS.TIMER1_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_LOW 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_HIGH 0x00000000 + +// Field: [7] TIMER0_EV +// +// Select the level of EVSTAT0.TIMER0_EV that sets EVTOAONFLAGS.TIMER0_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_LOW 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_HIGH 0x00000000 + +// Field: [6] TDC_DONE +// +// Select level of EVSTAT0.TDC_DONE that sets EVTOAONFLAGS.TDC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_HIGH 0x00000000 + +// Field: [5] ADC_DONE +// +// Select the level of EVSTAT0.ADC_DONE that sets EVTOAONFLAGS.ADC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_LOW 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_HIGH 0x00000000 + +// Field: [4] AUX_COMPB +// +// Select the edge of EVSTAT0.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB. +// ENUMs: +// LOW Falling edge +// HIGH Rising edge +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_LOW 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_HIGH 0x00000000 + +// Field: [3] AUX_COMPA +// +// Select the edge of EVSTAT0.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA. +// ENUMs: +// LOW Falling edge +// HIGH Rising edge +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_LOW 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_HIGH 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_DMACTL +// +//***************************************************************************** +// Field: [2] REQ_MODE +// +// UDMA0 Request mode +// ENUMs: +// SINGLE Single requests are generated on UDMA0 channel 7 +// when the condition configured in SEL is met. +// BURST Burst requests are generated on UDMA0 channel 7 +// when the condition configured in SEL is met. +#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_S 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000 + +// Field: [1] EN +// +// uDMA ADC interface enable. +// +// 0: Disable UDMA0 interface to ADC. +// 1: Enable UDMA0 interface to ADC. +#define AUX_EVCTL_DMACTL_EN 0x00000002 +#define AUX_EVCTL_DMACTL_EN_BITN 1 +#define AUX_EVCTL_DMACTL_EN_M 0x00000002 +#define AUX_EVCTL_DMACTL_EN_S 1 + +// Field: [0] SEL +// +// Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO +// data. +// ENUMs: +// FIFO_ALMOST_FULL UDMA0 trigger event will be generated when the ADC +// FIFO is almost full (3/4 full). +// FIFO_NOT_EMPTY UDMA0 trigger event will be generated when there +// are samples in the ADC FIFO. +#define AUX_EVCTL_DMACTL_SEL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_BITN 0 +#define AUX_EVCTL_DMACTL_SEL_M 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_S 0 +#define AUX_EVCTL_DMACTL_SEL_FIFO_ALMOST_FULL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_SWEVSET +// +//***************************************************************************** +// Field: [2] SWEV2 +// +// Software event flag 2. +// +// 0: No effect. +// 1: Set software event flag 2. +#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2 +#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// Software event flag 1. +// +// 0: No effect. +// 1: Set software event flag 1. +#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1 +#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// Software event flag 0. +// +// 0: No effect. +// 1: Set software event flag 0. +#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0 +#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT0 +// +//***************************************************************************** +// Field: [15] AUXIO2 +// +// AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 15 +#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO2_S 15 + +// Field: [14] AUXIO1 +// +// AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 14 +#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO1_S 14 + +// Field: [13] AUXIO0 +// +// AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 13 +#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO0_S 13 + +// Field: [12] AON_PROG_WU +// +// AON_EVENT:AUXWUSEL.WU2_EV OR AON_EVENT:AUXWUSEL.WU1_EV OR +// AON_EVENT:AUXWUSEL.WU0_EV +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU 0x00001000 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_BITN 12 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_M 0x00001000 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_S 12 + +// Field: [11] AON_SW +// +// AON_WUC:AUXCTL.SWEV +#define AUX_EVCTL_EVSTAT0_AON_SW 0x00000800 +#define AUX_EVCTL_EVSTAT0_AON_SW_BITN 11 +#define AUX_EVCTL_EVSTAT0_AON_SW_M 0x00000800 +#define AUX_EVCTL_EVSTAT0_AON_SW_S 11 + +// Field: [10] OBSMUX1 +// +// Observation input 1 from IOC. +// This event is configured by IOC:OBSAUXOUTPUT.SEL1. +#define AUX_EVCTL_EVSTAT0_OBSMUX1 0x00000400 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_BITN 10 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_M 0x00000400 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_S 10 + +// Field: [9] OBSMUX0 +// +// Observation input 0 from IOC. +// This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by +// IOC:OBSAUXOUTPUT.SEL_MISC. +#define AUX_EVCTL_EVSTAT0_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_S 9 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] ADC_DONE +// +// AUX_ANAIF ADC conversion done event. +#define AUX_EVCTL_EVSTAT0_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_S 7 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// See AUX_SMPH:AUTOTAKE.SMPH_ID for description. +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] TIMER1_EV +// +// AUX_TIMER1_EV event, see AUX_TIMER:T1TARGET for description. +#define AUX_EVCTL_EVSTAT0_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_S 5 + +// Field: [4] TIMER0_EV +// +// AUX_TIMER0_EV event, see AUX_TIMER:T0TARGET for description. +#define AUX_EVCTL_EVSTAT0_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_S 4 + +// Field: [3] TDC_DONE +// +// AUX_TDC:STAT.DONE +#define AUX_EVCTL_EVSTAT0_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// Comparator B output +#define AUX_EVCTL_EVSTAT0_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// Comparator A output +#define AUX_EVCTL_EVSTAT0_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_S 1 + +// Field: [0] AON_RTC_CH2 +// +// AON_RTC:EVFLAGS.CH2 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2 0x00000001 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_BITN 0 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_M 0x00000001 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT1 +// +//***************************************************************************** +// Field: [15] ADC_IRQ +// +// The logical function for this event is configurable. +// +// When DMACTL.EN = 1 : +// Event = UDMA0 Channel 7 done event OR +// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW +// +// When DMACTL.EN = 0 : +// Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR +// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW +// +// Bit 7 in UDMA0:DONEMASK must be 0. +#define AUX_EVCTL_EVSTAT1_ADC_IRQ 0x00008000 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_BITN 15 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_M 0x00008000 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_S 15 + +// Field: [14] MCU_EV +// +// Event from EVENT configured by EVENT:AUXSEL0. +#define AUX_EVCTL_EVSTAT1_MCU_EV 0x00004000 +#define AUX_EVCTL_EVSTAT1_MCU_EV_BITN 14 +#define AUX_EVCTL_EVSTAT1_MCU_EV_M 0x00004000 +#define AUX_EVCTL_EVSTAT1_MCU_EV_S 14 + +// Field: [13] ACLK_REF +// +// TDC reference clock. +// It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by +// AUX_WUC:REFCLKCTL.REQ. +#define AUX_EVCTL_EVSTAT1_ACLK_REF 0x00002000 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_BITN 13 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_M 0x00002000 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_S 13 + +// Field: [12] AUXIO15 +// +// AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT1_AUXIO15 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO15_BITN 12 +#define AUX_EVCTL_EVSTAT1_AUXIO15_M 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO15_S 12 + +// Field: [11] AUXIO14 +// +// AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT1_AUXIO14 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO14_BITN 11 +#define AUX_EVCTL_EVSTAT1_AUXIO14_M 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO14_S 11 + +// Field: [10] AUXIO13 +// +// AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT1_AUXIO13 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO13_BITN 10 +#define AUX_EVCTL_EVSTAT1_AUXIO13_M 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO13_S 10 + +// Field: [9] AUXIO12 +// +// AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT1_AUXIO12 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO12_BITN 9 +#define AUX_EVCTL_EVSTAT1_AUXIO12_M 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO12_S 9 + +// Field: [8] AUXIO11 +// +// AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT1_AUXIO11 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO11_BITN 8 +#define AUX_EVCTL_EVSTAT1_AUXIO11_M 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO11_S 8 + +// Field: [7] AUXIO10 +// +// AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT1_AUXIO10 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO10_BITN 7 +#define AUX_EVCTL_EVSTAT1_AUXIO10_M 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO10_S 7 + +// Field: [6] AUXIO9 +// +// AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT1_AUXIO9 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO9_BITN 6 +#define AUX_EVCTL_EVSTAT1_AUXIO9_M 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO9_S 6 + +// Field: [5] AUXIO8 +// +// AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT1_AUXIO8 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO8_BITN 5 +#define AUX_EVCTL_EVSTAT1_AUXIO8_M 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO8_S 5 + +// Field: [4] AUXIO7 +// +// AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT1_AUXIO7 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO7_BITN 4 +#define AUX_EVCTL_EVSTAT1_AUXIO7_M 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO7_S 4 + +// Field: [3] AUXIO6 +// +// AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT1_AUXIO6 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO6_BITN 3 +#define AUX_EVCTL_EVSTAT1_AUXIO6_M 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO6_S 3 + +// Field: [2] AUXIO5 +// +// AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT1_AUXIO5 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO5_BITN 2 +#define AUX_EVCTL_EVSTAT1_AUXIO5_M 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO5_S 2 + +// Field: [1] AUXIO4 +// +// AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT1_AUXIO4 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO4_BITN 1 +#define AUX_EVCTL_EVSTAT1_AUXIO4_M 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO4_S 1 + +// Field: [0] AUXIO3 +// +// AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT1_AUXIO3 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO3_BITN 0 +#define AUX_EVCTL_EVSTAT1_AUXIO3_M 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO3_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUPOL +// +//***************************************************************************** +// Field: [10] ADC_IRQ +// +// Select the event source level that sets EVTOMCUFLAGS.ADC_IRQ. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_LOW 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_HIGH 0x00000000 + +// Field: [9] OBSMUX0 +// +// Select the event source level that sets EVTOMCUFLAGS.OBSMUX0. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_LOW 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_HIGH 0x00000000 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// Select the event source level that sets EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_LOW 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000 + +// Field: [7] ADC_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.ADC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_LOW 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_HIGH 0x00000000 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_HIGH 0x00000000 + +// Field: [5] TIMER1_EV +// +// Select the event source level that sets EVTOMCUFLAGS.TIMER1_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_LOW 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_HIGH 0x00000000 + +// Field: [4] TIMER0_EV +// +// Select the event source level that sets EVTOMCUFLAGS.TIMER0_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_LOW 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_HIGH 0x00000000 + +// Field: [3] TDC_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.TDC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_LOW 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_HIGH 0x00000000 + +// Field: [2] AUX_COMPB +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_COMPB. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_LOW 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_HIGH 0x00000000 + +// Field: [1] AUX_COMPA +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_COMPA. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_LOW 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_HIGH 0x00000000 + +// Field: [0] AON_WU_EV +// +// Select the event source level that sets EVTOMCUFLAGS.AON_WU_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_LOW 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_HIGH 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUFLAGS +// +//***************************************************************************** +// Field: [10] ADC_IRQ +// +// This event flag is set when level selected by EVTOMCUPOL.ADC_IRQ occurs on +// EVSTAT0.ADC_IRQ. +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_S 10 + +// Field: [9] OBSMUX0 +// +// This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs +// on EVSTAT0.MCU_OBSMUX0. +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_S 9 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// This event flag is set when level selected by +// EVTOMCUPOL.ADC_FIFO_ALMOST_FULL occurs on EVSTAT0.ADC_FIFO_ALMOST_FULL. +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] ADC_DONE +// +// This event flag is set when level selected by EVTOMCUPOL.ADC_DONE occurs on +// EVSTAT0.ADC_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_S 7 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// This event flag is set when level selected by EVTOMCUPOL.SMPH_AUTOTAKE_DONE +// occurs on EVSTAT0.SMPH_AUTOTAKE_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] TIMER1_EV +// +// This event flag is set when level selected by EVTOMCUPOL.TIMER1_EV occurs on +// EVSTAT0.TIMER1_EV. +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_S 5 + +// Field: [4] TIMER0_EV +// +// This event flag is set when level selected by EVTOMCUPOL.TIMER0_EV occurs on +// EVSTAT0.TIMER0_EV. +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_S 4 + +// Field: [3] TDC_DONE +// +// This event flag is set when level selected by EVTOMCUPOL.TDC_DONE occurs on +// EVSTAT0.TDC_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on +// EVSTAT0.AUX_COMPB. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on +// EVSTAT0.AUX_COMPA. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1 + +// Field: [0] AON_WU_EV +// +// This event flag is set when level selected by EVTOMCUPOL.AON_WU_EV occurs on +// the reduction-OR of the AUX_EVCTL:EVSTAT0.RTC_CH2_EV, +// AUX_EVCTL:EVSTAT0.AON_SW, and AUX_EVCTL:EVSTAT0.AON_PROG_WU events. +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_COMBEVTOMCUMASK +// +//***************************************************************************** +// Field: [10] ADC_IRQ +// +// EVTOMCUFLAGS.ADC_IRQ contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_BITN 10 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_S 10 + +// Field: [9] OBSMUX0 +// +// EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_BITN 9 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_S 9 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] ADC_DONE +// +// EVTOMCUFLAGS.ADC_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_BITN 7 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_S 7 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] TIMER1_EV +// +// EVTOMCUFLAGS.TIMER1_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_BITN 5 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_S 5 + +// Field: [4] TIMER0_EV +// +// EVTOMCUFLAGS.TIMER0_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_BITN 4 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_S 4 + +// Field: [3] TDC_DONE +// +// EVTOMCUFLAGS.TDC_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_BITN 3 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event. +// +// 0: Exclude +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1 + +// Field: [0] AON_WU_EV +// +// EVTOMCUFLAGS.AON_WU_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_BITN 0 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_VECFLAGS +// +//***************************************************************************** +// Field: [3] VEC3 +// +// Vector flag 3. +// +// The vector flag is set if the edge selected VECCFG1.VEC3_POL occurs on the +// event selected in VECCFG1.VEC3_EV. +// +// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to +// VECFLAGSCLR.VEC3. +#define AUX_EVCTL_VECFLAGS_VEC3 0x00000008 +#define AUX_EVCTL_VECFLAGS_VEC3_BITN 3 +#define AUX_EVCTL_VECFLAGS_VEC3_M 0x00000008 +#define AUX_EVCTL_VECFLAGS_VEC3_S 3 + +// Field: [2] VEC2 +// +// Vector flag 2. +// +// The vector flag is set if the edge selected VECCFG1.VEC2_POL occurs on the +// event selected in VECCFG1.VEC2_EV. +// +// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to +// VECFLAGSCLR.VEC2. +#define AUX_EVCTL_VECFLAGS_VEC2 0x00000004 +#define AUX_EVCTL_VECFLAGS_VEC2_BITN 2 +#define AUX_EVCTL_VECFLAGS_VEC2_M 0x00000004 +#define AUX_EVCTL_VECFLAGS_VEC2_S 2 + +// Field: [1] VEC1 +// +// Vector flag 1. +// +// The vector flag is set if the edge selected VECCFG0.VEC1_POL occurs on the +// event selected in VECCFG0.VEC1_EV. +// +// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to +// VECFLAGSCLR.VEC1. +#define AUX_EVCTL_VECFLAGS_VEC1 0x00000002 +#define AUX_EVCTL_VECFLAGS_VEC1_BITN 1 +#define AUX_EVCTL_VECFLAGS_VEC1_M 0x00000002 +#define AUX_EVCTL_VECFLAGS_VEC1_S 1 + +// Field: [0] VEC0 +// +// Vector flag 0. +// +// The vector flag is set if the edge selected VECCFG0.VEC0_POL occurs on the +// event selected in VECCFG0.VEC0_EV. +// +// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to +// VECFLAGSCLR.VEC0. +#define AUX_EVCTL_VECFLAGS_VEC0 0x00000001 +#define AUX_EVCTL_VECFLAGS_VEC0_BITN 0 +#define AUX_EVCTL_VECFLAGS_VEC0_M 0x00000001 +#define AUX_EVCTL_VECFLAGS_VEC0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUFLAGSCLR +// +//***************************************************************************** +// Field: [10] ADC_IRQ +// +// Write 1 to clear EVTOMCUFLAGS.ADC_IRQ. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_S 10 + +// Field: [9] OBSMUX0 +// +// Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_S 9 + +// Field: [8] ADC_FIFO_ALMOST_FULL +// +// Write 1 to clear EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] ADC_DONE +// +// Write 1 to clear EVTOMCUFLAGS.ADC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_S 7 + +// Field: [6] SMPH_AUTOTAKE_DONE +// +// Write 1 to clear EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] TIMER1_EV +// +// Write 1 to clear EVTOMCUFLAGS.TIMER1_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_S 5 + +// Field: [4] TIMER0_EV +// +// Write 1 to clear EVTOMCUFLAGS.TIMER0_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_S 4 + +// Field: [3] TDC_DONE +// +// Write 1 to clear EVTOMCUFLAGS.TDC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1 + +// Field: [0] AON_WU_EV +// +// Write 1 to clear EVTOMCUFLAGS.AON_WU_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONFLAGSCLR +// +//***************************************************************************** +// Field: [8] TIMER1_EV +// +// Write 1 to clear EVTOAONFLAGS.TIMER1_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_S 8 + +// Field: [7] TIMER0_EV +// +// Write 1 to clear EVTOAONFLAGS.TIMER0_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_S 7 + +// Field: [6] TDC_DONE +// +// Write 1 to clear EVTOAONFLAGS.TDC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_S 6 + +// Field: [5] ADC_DONE +// +// Write 1 to clear EVTOAONFLAGS.ADC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_S 5 + +// Field: [4] AUX_COMPB +// +// Write 1 to clear EVTOAONFLAGS.AUX_COMPB. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4 + +// Field: [3] AUX_COMPA +// +// Write 1 to clear EVTOAONFLAGS.AUX_COMPA. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3 + +// Field: [2] SWEV2 +// +// Write 1 to clear EVTOAONFLAGS.SWEV2. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// Write 1 to clear EVTOAONFLAGS.SWEV1. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// Write 1 to clear EVTOAONFLAGS.SWEV0. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_VECFLAGSCLR +// +//***************************************************************************** +// Field: [3] VEC3 +// +// Clear vector flag 3. +// +// 0: No effect. +// 1: Clear VECFLAGS.VEC3. +// +// Read value is 0. +#define AUX_EVCTL_VECFLAGSCLR_VEC3 0x00000008 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_BITN 3 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_M 0x00000008 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_S 3 + +// Field: [2] VEC2 +// +// Clear vector flag 2. +// +// 0: No effect. +// 1: Clear VECFLAGS.VEC2. +// +// Read value is 0. +#define AUX_EVCTL_VECFLAGSCLR_VEC2 0x00000004 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_BITN 2 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_M 0x00000004 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_S 2 + +// Field: [1] VEC1 +// +// Clear vector flag 1. +// +// 0: No effect. +// 1: Clear VECFLAGS.VEC1. +// +// Read value is 0. +#define AUX_EVCTL_VECFLAGSCLR_VEC1 0x00000002 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_BITN 1 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_M 0x00000002 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_S 1 + +// Field: [0] VEC0 +// +// Clear vector flag 0. +// +// 0: No effect. +// 1: Clear VECFLAGS.VEC0. +// +// Read value is 0. +#define AUX_EVCTL_VECFLAGSCLR_VEC0 0x00000001 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_BITN 0 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_M 0x00000001 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_S 0 + + +#endif // __AUX_EVCTL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_sce.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_sce.h new file mode 100644 index 0000000..002242a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_sce.h @@ -0,0 +1,381 @@ +/****************************************************************************** +* Filename: hw_aux_sce_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SCE_H__ +#define __HW_AUX_SCE_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SCE component +// +//***************************************************************************** +// Internal +#define AUX_SCE_O_CTL 0x00000000 + +// Internal +#define AUX_SCE_O_FETCHSTAT 0x00000004 + +// Internal +#define AUX_SCE_O_CPUSTAT 0x00000008 + +// Internal +#define AUX_SCE_O_WUSTAT 0x0000000C + +// Internal +#define AUX_SCE_O_REG1_0 0x00000010 + +// Internal +#define AUX_SCE_O_REG3_2 0x00000014 + +// Internal +#define AUX_SCE_O_REG5_4 0x00000018 + +// Internal +#define AUX_SCE_O_REG7_6 0x0000001C + +// Internal +#define AUX_SCE_O_LOOPADDR 0x00000020 + +// Internal +#define AUX_SCE_O_LOOPCNT 0x00000024 + +//***************************************************************************** +// +// Register: AUX_SCE_O_CTL +// +//***************************************************************************** +// Field: [31:24] FORCE_EV_LOW +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_EV_LOW_W 8 +#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000 +#define AUX_SCE_CTL_FORCE_EV_LOW_S 24 + +// Field: [23:16] FORCE_EV_HIGH +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8 +#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000 +#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16 + +// Field: [11:8] RESET_VECTOR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_RESET_VECTOR_W 4 +#define AUX_SCE_CTL_RESET_VECTOR_M 0x00000F00 +#define AUX_SCE_CTL_RESET_VECTOR_S 8 + +// Field: [6] DBG_FREEZE_EN +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6 +#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6 + +// Field: [5] FORCE_WU_LOW +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5 +#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_S 5 + +// Field: [4] FORCE_WU_HIGH +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4 +#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4 + +// Field: [3] RESTART +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_RESTART 0x00000008 +#define AUX_SCE_CTL_RESTART_BITN 3 +#define AUX_SCE_CTL_RESTART_M 0x00000008 +#define AUX_SCE_CTL_RESTART_S 3 + +// Field: [2] SINGLE_STEP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_SINGLE_STEP 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_BITN 2 +#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_S 2 + +// Field: [1] SUSPEND +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_SUSPEND 0x00000002 +#define AUX_SCE_CTL_SUSPEND_BITN 1 +#define AUX_SCE_CTL_SUSPEND_M 0x00000002 +#define AUX_SCE_CTL_SUSPEND_S 1 + +// Field: [0] CLK_EN +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_CLK_EN 0x00000001 +#define AUX_SCE_CTL_CLK_EN_BITN 0 +#define AUX_SCE_CTL_CLK_EN_M 0x00000001 +#define AUX_SCE_CTL_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_FETCHSTAT +// +//***************************************************************************** +// Field: [31:16] OPCODE +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_FETCHSTAT_OPCODE_W 16 +#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000 +#define AUX_SCE_FETCHSTAT_OPCODE_S 16 + +// Field: [15:0] PC +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_FETCHSTAT_PC_W 16 +#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF +#define AUX_SCE_FETCHSTAT_PC_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_CPUSTAT +// +//***************************************************************************** +// Field: [11] BUS_ERROR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11 +#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11 + +// Field: [10] SLEEP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_SLEEP 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_BITN 10 +#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_S 10 + +// Field: [9] WEV +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_WEV 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_BITN 9 +#define AUX_SCE_CPUSTAT_WEV_M 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_S 9 + +// Field: [8] SELF_STOP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_SELF_STOP 0x00000100 +#define AUX_SCE_CPUSTAT_SELF_STOP_BITN 8 +#define AUX_SCE_CPUSTAT_SELF_STOP_M 0x00000100 +#define AUX_SCE_CPUSTAT_SELF_STOP_S 8 + +// Field: [3] V_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3 +#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_S 3 + +// Field: [2] C_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2 +#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_S 2 + +// Field: [1] N_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1 +#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_S 1 + +// Field: [0] Z_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0 +#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_WUSTAT +// +//***************************************************************************** +// Field: [17:16] EXC_VECTOR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_EXC_VECTOR_W 2 +#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00030000 +#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16 + +// Field: [8] WU_SIGNAL +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8 +#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8 + +// Field: [7:0] EV_SIGNALS +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8 +#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF +#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG1_0 +// +//***************************************************************************** +// Field: [31:16] REG1 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG1_0_REG1_W 16 +#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000 +#define AUX_SCE_REG1_0_REG1_S 16 + +// Field: [15:0] REG0 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG1_0_REG0_W 16 +#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF +#define AUX_SCE_REG1_0_REG0_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG3_2 +// +//***************************************************************************** +// Field: [31:16] REG3 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG3_2_REG3_W 16 +#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000 +#define AUX_SCE_REG3_2_REG3_S 16 + +// Field: [15:0] REG2 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG3_2_REG2_W 16 +#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF +#define AUX_SCE_REG3_2_REG2_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG5_4 +// +//***************************************************************************** +// Field: [31:16] REG5 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG5_4_REG5_W 16 +#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000 +#define AUX_SCE_REG5_4_REG5_S 16 + +// Field: [15:0] REG4 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG5_4_REG4_W 16 +#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF +#define AUX_SCE_REG5_4_REG4_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG7_6 +// +//***************************************************************************** +// Field: [31:16] REG7 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG7_6_REG7_W 16 +#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000 +#define AUX_SCE_REG7_6_REG7_S 16 + +// Field: [15:0] REG6 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG7_6_REG6_W 16 +#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF +#define AUX_SCE_REG7_6_REG6_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_LOOPADDR +// +//***************************************************************************** +// Field: [31:16] STOP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPADDR_STOP_W 16 +#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000 +#define AUX_SCE_LOOPADDR_STOP_S 16 + +// Field: [15:0] START +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPADDR_START_W 16 +#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF +#define AUX_SCE_LOOPADDR_START_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_LOOPCNT +// +//***************************************************************************** +// Field: [7:0] ITER_LEFT +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8 +#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF +#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0 + + +#endif // __AUX_SCE__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_smph.h new file mode 100644 index 0000000..ec7fa57 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_smph.h @@ -0,0 +1,282 @@ +/****************************************************************************** +* Filename: hw_aux_smph_h +* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) +* Revision: 49005 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SMPH_H__ +#define __HW_AUX_SMPH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SMPH component +// +//***************************************************************************** +// Semaphore 0 +#define AUX_SMPH_O_SMPH0 0x00000000 + +// Semaphore 1 +#define AUX_SMPH_O_SMPH1 0x00000004 + +// Semaphore 2 +#define AUX_SMPH_O_SMPH2 0x00000008 + +// Semaphore 3 +#define AUX_SMPH_O_SMPH3 0x0000000C + +// Semaphore 4 +#define AUX_SMPH_O_SMPH4 0x00000010 + +// Semaphore 5 +#define AUX_SMPH_O_SMPH5 0x00000014 + +// Semaphore 6 +#define AUX_SMPH_O_SMPH6 0x00000018 + +// Semaphore 7 +#define AUX_SMPH_O_SMPH7 0x0000001C + +// Auto Take +#define AUX_SMPH_O_AUTOTAKE 0x00000020 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH0_STAT 0x00000001 +#define AUX_SMPH_SMPH0_STAT_BITN 0 +#define AUX_SMPH_SMPH0_STAT_M 0x00000001 +#define AUX_SMPH_SMPH0_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH1_STAT 0x00000001 +#define AUX_SMPH_SMPH1_STAT_BITN 0 +#define AUX_SMPH_SMPH1_STAT_M 0x00000001 +#define AUX_SMPH_SMPH1_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH2_STAT 0x00000001 +#define AUX_SMPH_SMPH2_STAT_BITN 0 +#define AUX_SMPH_SMPH2_STAT_M 0x00000001 +#define AUX_SMPH_SMPH2_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH3_STAT 0x00000001 +#define AUX_SMPH_SMPH3_STAT_BITN 0 +#define AUX_SMPH_SMPH3_STAT_M 0x00000001 +#define AUX_SMPH_SMPH3_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH4_STAT 0x00000001 +#define AUX_SMPH_SMPH4_STAT_BITN 0 +#define AUX_SMPH_SMPH4_STAT_M 0x00000001 +#define AUX_SMPH_SMPH4_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH5_STAT 0x00000001 +#define AUX_SMPH_SMPH5_STAT_BITN 0 +#define AUX_SMPH_SMPH5_STAT_M 0x00000001 +#define AUX_SMPH_SMPH5_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH6_STAT 0x00000001 +#define AUX_SMPH_SMPH6_STAT_BITN 0 +#define AUX_SMPH_SMPH6_STAT_M 0x00000001 +#define AUX_SMPH_SMPH6_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH7_STAT 0x00000001 +#define AUX_SMPH_SMPH7_STAT_BITN 0 +#define AUX_SMPH_SMPH7_STAT_M 0x00000001 +#define AUX_SMPH_SMPH7_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_AUTOTAKE +// +//***************************************************************************** +// Field: [2:0] SMPH_ID +// +// Write the semaphore ID,0x0-0x7, to SMPH_ID to request this semaphore until +// it is granted. +// +// When semaphore SMPH_ID is granted, event +// AUX_EVCTL:EVSTAT0.AUX_SMPH_AUTOTAKE_DONE becomes 1. +// +// The event becomes 0 when software releases the semaphore or writes a new +// value to SMPH_ID. +// +// To avoid corrupted semaphores: +// - Usage of this functionality must be restricted to one CPU core. +// - Software must wait until AUX_EVCTL:EVSTAT0.AUX_SMPH_AUTOTAKE_DONE is 1 +// before it writes a new value to SMPH_ID. +#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0 + + +#endif // __AUX_SMPH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_tdc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_tdc.h new file mode 100644 index 0000000..21d490e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_tdc.h @@ -0,0 +1,694 @@ +/****************************************************************************** +* Filename: hw_aux_tdc_h +* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) +* Revision: 49005 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_TDC_H__ +#define __HW_AUX_TDC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_TDC component +// +//***************************************************************************** +// Control +#define AUX_TDC_O_CTL 0x00000000 + +// Status +#define AUX_TDC_O_STAT 0x00000004 + +// Result +#define AUX_TDC_O_RESULT 0x00000008 + +// Saturation Configuration +#define AUX_TDC_O_SATCFG 0x0000000C + +// Trigger Source +#define AUX_TDC_O_TRIGSRC 0x00000010 + +// Trigger Counter +#define AUX_TDC_O_TRIGCNT 0x00000014 + +// Trigger Counter Load +#define AUX_TDC_O_TRIGCNTLOAD 0x00000018 + +// Trigger Counter Configuration +#define AUX_TDC_O_TRIGCNTCFG 0x0000001C + +// Prescaler Control +#define AUX_TDC_O_PRECTL 0x00000020 + +// Prescaler Counter +#define AUX_TDC_O_PRECNT 0x00000024 + +//***************************************************************************** +// +// Register: AUX_TDC_O_CTL +// +//***************************************************************************** +// Field: [1:0] CMD +// +// TDC commands. +// ENUMs: +// ABORT Force TDC state machine back to IDLE state. +// +// Never write this command +// while AUX_TDC:STAT.STATE equals CLR_CNT or +// WAIT_CLR_CNT_DONE. +// RUN Asynchronous counter start. +// +// The counter starts to +// count when the start event is high. To achieve +// precise edge-to-edge measurements you must +// ensure that the start event is low for at least +// 420 ns after you write this command. +// RUN_SYNC_START Synchronous counter start. +// +// The counter looks for the +// opposite edge of the selected start event +// before it starts to count when the selected +// edge occurs. This guarantees an edge-triggered +// start and is recommended for frequency +// measurements. +// CLR_RESULT Clear STAT.SAT, STAT.DONE, and RESULT.VALUE. +// +// This is not needed as +// prerequisite for a measurement. Reliable clear +// is only guaranteed from IDLE state. +#define AUX_TDC_CTL_CMD_W 2 +#define AUX_TDC_CTL_CMD_M 0x00000003 +#define AUX_TDC_CTL_CMD_S 0 +#define AUX_TDC_CTL_CMD_ABORT 0x00000003 +#define AUX_TDC_CTL_CMD_RUN 0x00000002 +#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 +#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_STAT +// +//***************************************************************************** +// Field: [7] SAT +// +// TDC measurement saturation flag. +// +// 0: Conversion has not saturated. +// 1: Conversion stopped due to saturation. +// +// This field is cleared when a new measurement is started or when CLR_RESULT +// is written to CTL.CMD. +#define AUX_TDC_STAT_SAT 0x00000080 +#define AUX_TDC_STAT_SAT_BITN 7 +#define AUX_TDC_STAT_SAT_M 0x00000080 +#define AUX_TDC_STAT_SAT_S 7 + +// Field: [6] DONE +// +// TDC measurement complete flag. +// +// 0: TDC measurement has not yet completed. +// 1: TDC measurement has completed. +// +// This field clears when a new TDC measurement starts or when you write +// CLR_RESULT to CTL.CMD. +#define AUX_TDC_STAT_DONE 0x00000040 +#define AUX_TDC_STAT_DONE_BITN 6 +#define AUX_TDC_STAT_DONE_M 0x00000040 +#define AUX_TDC_STAT_DONE_S 6 + +// Field: [5:0] STATE +// +// TDC state machine status. +// ENUMs: +// FORCE_STOP Current state is TDC_FORCESTOP. +// You wrote ABORT to +// CTL.CMD to abort the TDC measurement. +// START_FALL Current state is TDC_WAIT_STARTFALL. +// The fast-counter circuit +// waits for a falling edge on the start event. +// WAIT_CLR_CNT_DONE Current state is TDC_STATE_WAIT_CLRCNT_DONE. +// The state machine waits +// for fast-counter circuit to finish reset. +// POR Current state is TDC_STATE_POR. +// This is the reset state. +// GET_RESULT Current state is TDC_STATE_GETRESULTS. +// The state machine copies +// the counter value from the fast-counter +// circuit. +// WAIT_STOP_CNTDWN Current state is TDC_STATE_WAIT_STOPCNTDOWN. +// The fast-counter circuit +// looks for the stop condition. It will ignore a +// number of stop events configured in +// TRIGCNTLOAD.CNT. +// WAIT_STOP Current state is TDC_STATE_WAIT_STOP. +// The state machine waits +// for the fast-counter circuit to stop. +// CLR_CNT Current state is TDC_STATE_CLRCNT. The +// fast-counter circuit is reset. +// IDLE Current state is TDC_STATE_IDLE. +// This is the default state +// after reset and abortion. State will change +// when you write CTL.CMD to either RUN_SYNC_START +// or RUN. +// WAIT_START_STOP_CNT_EN Current state is TDC_STATE_WAIT_STARTSTOPCNTEN. +// The fast-counter circuit +// looks for the start condition. The state +// machine waits for the fast-counter to +// increment. +// WAIT_START Current state is TDC_STATE_WAIT_START. +// The fast-counter circuit +// looks for the start condition. The state +// machine waits for the fast-counter to +// increment. +#define AUX_TDC_STAT_STATE_W 6 +#define AUX_TDC_STAT_STATE_M 0x0000003F +#define AUX_TDC_STAT_STATE_S 0 +#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E +#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E +#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 +#define AUX_TDC_STAT_STATE_POR 0x0000000F +#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E +#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C +#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 +#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 +#define AUX_TDC_STAT_STATE_IDLE 0x00000006 +#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 +#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_RESULT +// +//***************************************************************************** +// Field: [24:0] VALUE +// +// TDC conversion result. +// +// The result of the TDC conversion is given in number of clock edges of the +// clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and +// falling edges are counted. +// +// If TDC counter saturates, VALUE is slightly higher than SATCFG.LIMIT, as it +// takes a non-zero time to stop the measurement. Hence, the maximum value of +// this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT +// to R24. +#define AUX_TDC_RESULT_VALUE_W 25 +#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF +#define AUX_TDC_RESULT_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_SATCFG +// +//***************************************************************************** +// Field: [3:0] LIMIT +// +// Saturation limit. +// +// The flag STAT.SAT is set when the TDC counter saturates. +// +// Values not enumerated are not supported +// ENUMs: +// R24 Result bit 24: TDC conversion saturates and stops +// when RESULT.VALUE[24] is set. +// R23 Result bit 23: TDC conversion saturates and stops +// when RESULT.VALUE[23] is set. +// R22 Result bit 22: TDC conversion saturates and stops +// when RESULT.VALUE[22] is set. +// R21 Result bit 21: TDC conversion saturates and stops +// when RESULT.VALUE[21] is set. +// R20 Result bit 20: TDC conversion saturates and stops +// when RESULT.VALUE[20] is set. +// R19 Result bit 19: TDC conversion saturates and stops +// when RESULT.VALUE[19] is set. +// R18 Result bit 18: TDC conversion saturates and stops +// when RESULT.VALUE[18] is set. +// R17 Result bit 17: TDC conversion saturates and stops +// when RESULT.VALUE[17] is set. +// R16 Result bit 16: TDC conversion saturates and stops +// when RESULT.VALUE[16] is set. +// R15 Result bit 15: TDC conversion saturates and stops +// when RESULT.VALUE[15] is set. +// R14 Result bit 14: TDC conversion saturates and stops +// when RESULT.VALUE[14] is set. +// R13 Result bit 13: TDC conversion saturates and stops +// when RESULT.VALUE[13] is set. +// R12 Result bit 12: TDC conversion saturates and stops +// when RESULT.VALUE[12] is set. +#define AUX_TDC_SATCFG_LIMIT_W 4 +#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_S 0 +#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E +#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D +#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C +#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B +#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A +#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 +#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 +#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 +#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 +#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 +#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 +#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGSRC +// +//***************************************************************************** +// Field: [13] STOP_POL +// +// Polarity of stop source. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// LOW TDC conversion stops when low level is detected. +// HIGH TDC conversion stops when high level is detected. +#define AUX_TDC_TRIGSRC_STOP_POL 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_BITN 13 +#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_S 13 +#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 + +// Field: [12:8] STOP_SRC +// +// Select stop source from the asynchronous AUX event bus. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// TDC_PRE Select TDC Prescaler event which is generated by +// configuration of PRECTL. +// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TDC_TRIGSRC_STOP_SRC_W 5 +#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00001F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_S 8 +#define AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE 0x00001F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00001E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00001D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00001C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00001B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00001A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00001900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00001800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00001700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00001600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00001500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00001400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00001300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00001200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00001100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00001000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_SW 0x00000B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1 0x00000A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0 0x00000900 +#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE 0x00000700 +#define AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV 0x00000500 +#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV 0x00000400 +#define AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET 0x00000300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00000200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00000100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00000000 + +// Field: [5] START_POL +// +// Polarity of start source. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// LOW TDC conversion starts when low level is detected. +// HIGH TDC conversion starts when high level is detected. +#define AUX_TDC_TRIGSRC_START_POL 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_BITN 5 +#define AUX_TDC_TRIGSRC_START_POL_M 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_S 5 +#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 + +// Field: [4:0] START_SRC +// +// Select start source from the asynchronous AUX event bus. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// TDC_PRE Select TDC Prescaler event which is generated by +// configuration of PRECTL. +// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TDC_TRIGSRC_START_SRC_W 5 +#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000001F +#define AUX_TDC_TRIGSRC_START_SRC_S 0 +#define AUX_TDC_TRIGSRC_START_SRC_TDC_PRE 0x0000001F +#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000001E +#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000001D +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000001C +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000001B +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000001A +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x00000019 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x00000018 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x00000017 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000016 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000015 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000014 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000013 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000012 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000011 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000010 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x0000000F +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x0000000E +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x0000000D +#define AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU 0x0000000C +#define AUX_TDC_TRIGSRC_START_SRC_AON_SW 0x0000000B +#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX1 0x0000000A +#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX0 0x00000009 +#define AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_TDC_TRIGSRC_START_SRC_ADC_DONE 0x00000007 +#define AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV 0x00000005 +#define AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV 0x00000004 +#define AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET 0x00000003 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x00000002 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x00000001 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNT +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. +// +// Read CNT to get the remaining number of stop events to ignore during a TDC +// measurement. +// +// Write CNT to update the remaining number of stop events to ignore during a +// TDC measurement. The TDC measurement ignores updates of CNT if there are no +// more stop events left to ignore. +// +// When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the +// start of the measurement. +#define AUX_TDC_TRIGCNT_CNT_W 16 +#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNT_CNT_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNTLOAD +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. +// +// To measure frequency of an event source: +// - Set start event equal to stop event. +// - Set CNT to number of periods to measure. Both 0 and 1 values measures a +// single event source period. +// +// To measure pulse width of an event source: +// - Set start event source equal to stop event source. +// - Select different polarity for start and stop event. +// - Set CNT to 0. +// +// To measure time from the start event to the Nth stop event when N > 1: +// - Select different start and stop event source. +// - Set CNT to (N-1). +// +// See the Technical Reference Manual for event timing requirements. +// +// When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start +// of the measurement. +#define AUX_TDC_TRIGCNTLOAD_CNT_W 16 +#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNTLOAD_CNT_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNTCFG +// +//***************************************************************************** +// Field: [0] EN +// +// Enable stop-counter. +// +// 0: Disable stop-counter. +// 1: Enable stop-counter. +// +// Change only while STAT.STATE is IDLE. +#define AUX_TDC_TRIGCNTCFG_EN 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_BITN 0 +#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_PRECTL +// +//***************************************************************************** +// Field: [7] RESET_N +// +// Prescaler reset. +// +// 0: Reset prescaler. +// 1: Release reset of prescaler. +// +// AUX_TDC_PRE event becomes 0 when you reset the prescaler. +#define AUX_TDC_PRECTL_RESET_N 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_BITN 7 +#define AUX_TDC_PRECTL_RESET_N_M 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_S 7 + +// Field: [6] RATIO +// +// Prescaler ratio. +// +// This controls how often the AUX_TDC_PRE event is generated by the prescaler. +// ENUMs: +// DIV64 Prescaler divides input by 64. +// +// AUX_TDC_PRE event has a +// rising edge for every 64 rising edges of the +// input. AUX_TDC_PRE event toggles on every 32nd +// rising edge of the input. +// DIV16 Prescaler divides input by 16. +// +// AUX_TDC_PRE event has a +// rising edge for every 16 rising edges of the +// input. AUX_TDC_PRE event toggles on every 8th +// rising edge of the input. +#define AUX_TDC_PRECTL_RATIO 0x00000040 +#define AUX_TDC_PRECTL_RATIO_BITN 6 +#define AUX_TDC_PRECTL_RATIO_M 0x00000040 +#define AUX_TDC_PRECTL_RATIO_S 6 +#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 +#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 + +// Field: [4:0] SRC +// +// Prescaler event source. +// +// Select an event from the asynchronous AUX event bus to connect to the +// prescaler input. +// +// Configure only while RESET_N is 0. +// ENUMs: +// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ +// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TDC_PRECTL_SRC_W 5 +#define AUX_TDC_PRECTL_SRC_M 0x0000001F +#define AUX_TDC_PRECTL_SRC_S 0 +#define AUX_TDC_PRECTL_SRC_ADC_IRQ 0x0000001F +#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000001E +#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000001D +#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000001C +#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000001B +#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000001A +#define AUX_TDC_PRECTL_SRC_AUXIO12 0x00000019 +#define AUX_TDC_PRECTL_SRC_AUXIO11 0x00000018 +#define AUX_TDC_PRECTL_SRC_AUXIO10 0x00000017 +#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000016 +#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000015 +#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000014 +#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000013 +#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000012 +#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000011 +#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000010 +#define AUX_TDC_PRECTL_SRC_AUXIO2 0x0000000F +#define AUX_TDC_PRECTL_SRC_AUXIO1 0x0000000E +#define AUX_TDC_PRECTL_SRC_AUXIO0 0x0000000D +#define AUX_TDC_PRECTL_SRC_AON_PROG_WU 0x0000000C +#define AUX_TDC_PRECTL_SRC_AON_SW 0x0000000B +#define AUX_TDC_PRECTL_SRC_OBSMUX1 0x0000000A +#define AUX_TDC_PRECTL_SRC_OBSMUX0 0x00000009 +#define AUX_TDC_PRECTL_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_TDC_PRECTL_SRC_ADC_DONE 0x00000007 +#define AUX_TDC_PRECTL_SRC_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_TDC_PRECTL_SRC_TIMER1_EV 0x00000005 +#define AUX_TDC_PRECTL_SRC_TIMER0_EV 0x00000004 +#define AUX_TDC_PRECTL_SRC_ISRC_RESET 0x00000003 +#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x00000002 +#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x00000001 +#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_PRECNT +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Prescaler counter value. +// +// Write a value to CNT to capture the value of the 16-bit prescaler counter +// into CNT. Read CNT to get the captured value. +// +// The read value gets 1 LSB uncertainty if the event source level rises when +// you release the reset. +// +// You must capture the prescaler counter value when the event source level is +// stable, either high or low: +// - Disable AUX I/O input buffer to clamp AUXIO event low. +// - Disable COMPA to clamp AUX_COMPA event low. +// The read value can in general get 1 LSB uncertainty when you gate the event +// source asynchronously. +// +// Please note the following: +// - The prescaler counter is reset to 2 by PRECTL.RESET_N. +// - The captured value is 2 when the number of rising edges on prescaler input +// is less than 3. Otherwise, captured value equals number of event pulses - 1. +#define AUX_TDC_PRECNT_CNT_W 16 +#define AUX_TDC_PRECNT_CNT_M 0x0000FFFF +#define AUX_TDC_PRECNT_CNT_S 0 + + +#endif // __AUX_TDC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_timer.h new file mode 100644 index 0000000..ad0aa1e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_timer.h @@ -0,0 +1,447 @@ +/****************************************************************************** +* Filename: hw_aux_timer_h +* Revised: 2017-05-22 18:50:33 +0200 (Mon, 22 May 2017) +* Revision: 49040 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_TIMER_H__ +#define __HW_AUX_TIMER_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_TIMER component +// +//***************************************************************************** +// Timer 0 Configuration +#define AUX_TIMER_O_T0CFG 0x00000000 + +// Timer 1 Configuration +#define AUX_TIMER_O_T1CFG 0x00000004 + +// Timer 0 Control +#define AUX_TIMER_O_T0CTL 0x00000008 + +// Timer 0 Target +#define AUX_TIMER_O_T0TARGET 0x0000000C + +// Timer 1 Target +#define AUX_TIMER_O_T1TARGET 0x00000010 + +// Timer 1 Control +#define AUX_TIMER_O_T1CTL 0x00000014 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T0CFG +// +//***************************************************************************** +// Field: [13] TICK_SRC_POL +// +// Tick source polarity for Timer 0. +// ENUMs: +// FALL Count on falling edges of TICK_SRC. +// RISE Count on rising edges of TICK_SRC. +#define AUX_TIMER_T0CFG_TICK_SRC_POL 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_BITN 13 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_M 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_S 13 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_FALL 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_RISE 0x00000000 + +// Field: [12:8] TICK_SRC +// +// Select Timer 0 tick source from the synchronous event bus. +// ENUMs: +// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ +// MCU_EVENT AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// RTC_4KHZ AON_RTC:SUBSEC.VALUE bit 19. +// AON_RTC:CTL.RTC_4KHZ_EN enables this event. +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV +// TDC_DONE AUX_EVCTL:EVSTAT0.TDC_DONE +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TIMER_T0CFG_TICK_SRC_W 5 +#define AUX_TIMER_T0CFG_TICK_SRC_M 0x00001F00 +#define AUX_TIMER_T0CFG_TICK_SRC_S 8 +#define AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ 0x00001F00 +#define AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT 0x00001E00 +#define AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF 0x00001D00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO15 0x00001C00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO14 0x00001B00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO13 0x00001A00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO12 0x00001900 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO11 0x00001800 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO10 0x00001700 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO9 0x00001600 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO8 0x00001500 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO7 0x00001400 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO6 0x00001300 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO5 0x00001200 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO4 0x00001100 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO3 0x00001000 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO2 0x00000F00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO1 0x00000E00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO0 0x00000D00 +#define AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TIMER_T0CFG_TICK_SRC_AON_SW 0x00000B00 +#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1 0x00000A00 +#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0 0x00000900 +#define AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ 0x00000800 +#define AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE 0x00000700 +#define AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV 0x00000500 +#define AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE 0x00000300 +#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB 0x00000200 +#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA 0x00000100 +#define AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV 0x00000000 + +// Field: [7:4] PRE +// +// Prescaler division ratio is 2^PRE: +// +// 0x0: Divide by 1. +// 0x1: Divide by 2. +// 0x2: Divide by 4. +// ... +// 0xF: Divide by 32,768. +#define AUX_TIMER_T0CFG_PRE_W 4 +#define AUX_TIMER_T0CFG_PRE_M 0x000000F0 +#define AUX_TIMER_T0CFG_PRE_S 4 + +// Field: [1] MODE +// +// Timer 0 mode. +// +// Configure source for Timer 0 prescaler. +// ENUMs: +// TICK Use event set by TICK_SRC as source for prescaler. +// CLK Use AUX clock as source for prescaler. +#define AUX_TIMER_T0CFG_MODE 0x00000002 +#define AUX_TIMER_T0CFG_MODE_BITN 1 +#define AUX_TIMER_T0CFG_MODE_M 0x00000002 +#define AUX_TIMER_T0CFG_MODE_S 1 +#define AUX_TIMER_T0CFG_MODE_TICK 0x00000002 +#define AUX_TIMER_T0CFG_MODE_CLK 0x00000000 + +// Field: [0] RELOAD +// +// Timer 0 reload mode. +// ENUMs: +// CONT Continuous mode. +// +// Timer 0 restarts when the +// counter value becomes equal to or greater than +// ( T0TARGET.VALUE - 1). +// MAN Manual mode. +// +// Timer 0 stops and +// T0CTL.EN becomes 0 when the counter value +// becomes equal to or greater than +// T0TARGET.VALUE. +#define AUX_TIMER_T0CFG_RELOAD 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_BITN 0 +#define AUX_TIMER_T0CFG_RELOAD_M 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_S 0 +#define AUX_TIMER_T0CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_MAN 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T1CFG +// +//***************************************************************************** +// Field: [13] TICK_SRC_POL +// +// Tick source polarity for Timer 1. +// ENUMs: +// FALL Count on falling edges of TICK_SRC. +// RISE Count on rising edges of TICK_SRC. +#define AUX_TIMER_T1CFG_TICK_SRC_POL 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_BITN 13 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_M 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_S 13 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_FALL 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_RISE 0x00000000 + +// Field: [12:8] TICK_SRC +// +// Select Timer 1 tick source from the synchronous event bus. +// ENUMs: +// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ +// MCU_EVENT AUX_EVCTL:EVSTAT1.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF +// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU +// AON_SW AUX_EVCTL:EVSTAT0.AON_SW +// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 +// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 +// RTC_4KHZ AON_RTC:SUBSEC.VALUE bit 19. +// AON_RTC:CTL.RTC_4KHZ_EN enables this event. +// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE +// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE +// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV +// TDC_DONE AUX_EVCTL:EVSTAT0.TDC_DONE +// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA +// RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 +#define AUX_TIMER_T1CFG_TICK_SRC_W 5 +#define AUX_TIMER_T1CFG_TICK_SRC_M 0x00001F00 +#define AUX_TIMER_T1CFG_TICK_SRC_S 8 +#define AUX_TIMER_T1CFG_TICK_SRC_ADC_IRQ 0x00001F00 +#define AUX_TIMER_T1CFG_TICK_SRC_MCU_EVENT 0x00001E00 +#define AUX_TIMER_T1CFG_TICK_SRC_ACLK_REF 0x00001D00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO15 0x00001C00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO14 0x00001B00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO13 0x00001A00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO12 0x00001900 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO11 0x00001800 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO10 0x00001700 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO9 0x00001600 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO8 0x00001500 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO7 0x00001400 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO6 0x00001300 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO5 0x00001200 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO4 0x00001100 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO3 0x00001000 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO2 0x00000F00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO1 0x00000E00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO0 0x00000D00 +#define AUX_TIMER_T1CFG_TICK_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TIMER_T1CFG_TICK_SRC_AON_SW 0x00000B00 +#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX1 0x00000A00 +#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX0 0x00000900 +#define AUX_TIMER_T1CFG_TICK_SRC_RTC_4KHZ 0x00000800 +#define AUX_TIMER_T1CFG_TICK_SRC_ADC_DONE 0x00000700 +#define AUX_TIMER_T1CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV 0x00000400 +#define AUX_TIMER_T1CFG_TICK_SRC_TDC_DONE 0x00000300 +#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPB 0x00000200 +#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPA 0x00000100 +#define AUX_TIMER_T1CFG_TICK_SRC_RTC_CH2_EV 0x00000000 + +// Field: [7:4] PRE +// +// Prescaler division ratio is 2^PRE: +// +// 0x0: Divide by 1. +// 0x1: Divide by 2. +// 0x2: Divide by 4. +// ... +// 0xF: Divide by 32,768. +#define AUX_TIMER_T1CFG_PRE_W 4 +#define AUX_TIMER_T1CFG_PRE_M 0x000000F0 +#define AUX_TIMER_T1CFG_PRE_S 4 + +// Field: [1] MODE +// +// Timer 1 mode. +// +// Configure source for Timer 1 prescaler. +// ENUMs: +// TICK Use event set by TICK_SRC as source for prescaler. +// CLK Use AUX clock as source for prescaler. +#define AUX_TIMER_T1CFG_MODE 0x00000002 +#define AUX_TIMER_T1CFG_MODE_BITN 1 +#define AUX_TIMER_T1CFG_MODE_M 0x00000002 +#define AUX_TIMER_T1CFG_MODE_S 1 +#define AUX_TIMER_T1CFG_MODE_TICK 0x00000002 +#define AUX_TIMER_T1CFG_MODE_CLK 0x00000000 + +// Field: [0] RELOAD +// +// Timer 1 reload mode. +// ENUMs: +// CONT Continuous mode. +// +// Timer 1 restarts when the +// counter value becomes equal to or greater than +// ( T1TARGET.VALUE - 1). +// MAN Manual mode. +// +// Timer 1 stops and +// T1CTL.EN becomes 0 when the counter value +// becomes equal to or greater than +// T1TARGET.VALUE. +#define AUX_TIMER_T1CFG_RELOAD 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_BITN 0 +#define AUX_TIMER_T1CFG_RELOAD_M 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_S 0 +#define AUX_TIMER_T1CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_MAN 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T0CTL +// +//***************************************************************************** +// Field: [0] EN +// +// Timer 0 enable. +// +// 0: Disable Timer 0. +// 1: Enable Timer 0. +// +// The counter restarts from 0 when you enable Timer 0. +#define AUX_TIMER_T0CTL_EN 0x00000001 +#define AUX_TIMER_T0CTL_EN_BITN 0 +#define AUX_TIMER_T0CTL_EN_M 0x00000001 +#define AUX_TIMER_T0CTL_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T0TARGET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Timer 0 target value. +// +// Manual Reload Mode: +// - Timer 0 increments until the counter value becomes equal to or greater +// than VALUE. +// - AUX_TIMER0_EV pulses high for 1 AUX clock period when the counter value is +// equal to or greater than VALUE. +// +// Note: When VALUE is 0, Timer 0 counts to 1. AUX_TIMER0_EV pulses high for 1 +// AUX clock period. +// +// Continuous Reload Mode: +// - Timer 0 increments until the counter value becomes equal to or greater +// than ( VALUE - 1), then restarts from 0. +// - AUX_TIMER0_EV pulses high for 1 AUX clock period when the counter value is +// 0, except for when you enable the timer. +// +// Note: When VALUE is less than 2, Timer 0 counter value remains 0. +// AUX_TIMER0_EV goes high and remains high 1 AUX clock period after you enable +// the timer. +// +// +// It is allowed to update the VALUE while the timer runs. +#define AUX_TIMER_T0TARGET_VALUE_W 16 +#define AUX_TIMER_T0TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER_T0TARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T1TARGET +// +//***************************************************************************** +// Field: [7:0] VALUE +// +// Timer 1 target value. +// +// Manual Reload Mode: +// - Timer 1 increments until the counter value becomes equal to or greater +// than VALUE. +// - AUX_TIMER1_EV pulses high for 1 AUX clock period when the counter value is +// equal to or greater than VALUE. +// +// Note: When VALUE is 0, Timer 1 counts to 1. AUX_TIMER1_EV pulses high for 1 +// AUX clock period. +// +// Continuous Reload Mode: +// - Timer 1 increments until the counter value becomes equal to or greater +// than ( VALUE - 1), then restarts from 0. +// - AUX_TIMER1_EV pulses high for 1 AUX clock period when the counter value is +// 0, except for when you enable the timer. +// +// Note: When VALUE is less than 2, Timer 1 counter value remains 0. +// AUX_TIMER1_EV goes high and remains high 1 AUX clock period after you enable +// the timer. +// +// +// It is allowed to update the VALUE while the timer runs. +#define AUX_TIMER_T1TARGET_VALUE_W 8 +#define AUX_TIMER_T1TARGET_VALUE_M 0x000000FF +#define AUX_TIMER_T1TARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER_O_T1CTL +// +//***************************************************************************** +// Field: [0] EN +// +// Timer 1 enable. +// +// 0: Disable Timer 1. +// 1: Enable Timer 1. +// +// The counter restarts from 0 when you enable Timer 1. +#define AUX_TIMER_T1CTL_EN 0x00000001 +#define AUX_TIMER_T1CTL_EN_BITN 0 +#define AUX_TIMER_T1CTL_EN_M 0x00000001 +#define AUX_TIMER_T1CTL_EN_S 0 + + +#endif // __AUX_TIMER__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_wuc.h new file mode 100644 index 0000000..f7dd3b0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_wuc.h @@ -0,0 +1,705 @@ +/****************************************************************************** +* Filename: hw_aux_wuc_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_WUC_H__ +#define __HW_AUX_WUC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_WUC component +// +//***************************************************************************** +// Module Clock Enable +#define AUX_WUC_O_MODCLKEN0 0x00000000 + +// Power Off Request +#define AUX_WUC_O_PWROFFREQ 0x00000004 + +// Power Down Request +#define AUX_WUC_O_PWRDWNREQ 0x00000008 + +// Power Down Acknowledgment +#define AUX_WUC_O_PWRDWNACK 0x0000000C + +// Low Frequency Clock Request +#define AUX_WUC_O_CLKLFREQ 0x00000010 + +// Low Frequency Clock Acknowledgment +#define AUX_WUC_O_CLKLFACK 0x00000014 + +// Wake-up Event Flags +#define AUX_WUC_O_WUEVFLAGS 0x00000028 + +// Wake-up Event Clear +#define AUX_WUC_O_WUEVCLR 0x0000002C + +// ADC Clock Control +#define AUX_WUC_O_ADCCLKCTL 0x00000030 + +// TDC Clock Control +#define AUX_WUC_O_TDCCLKCTL 0x00000034 + +// Reference Clock Control +#define AUX_WUC_O_REFCLKCTL 0x00000038 + +// Real Time Counter Sub Second Increment 0 +#define AUX_WUC_O_RTCSUBSECINC0 0x0000003C + +// Real Time Counter Sub Second Increment 1 +#define AUX_WUC_O_RTCSUBSECINC1 0x00000040 + +// Real Time Counter Sub Second Increment Control +#define AUX_WUC_O_RTCSUBSECINCCTL 0x00000044 + +// MCU Bus Control +#define AUX_WUC_O_MCUBUSCTL 0x00000048 + +// MCU Bus Status +#define AUX_WUC_O_MCUBUSSTAT 0x0000004C + +// AON Domain Control Status +#define AUX_WUC_O_AONCTLSTAT 0x00000050 + +// AUX Input Output Latch +#define AUX_WUC_O_AUXIOLATCH 0x00000054 + +// Module Clock Enable 1 +#define AUX_WUC_O_MODCLKEN1 0x0000005C + +//***************************************************************************** +// +// Register: AUX_WUC_O_MODCLKEN0 +// +//***************************************************************************** +// Field: [7] AUX_ADI4 +// +// Enables (1) or disables (0) clock for AUX_ADI4. +// ENUMs: +// EN System CPU has requested clock for AUX_ADI4 +// DIS System CPU has not requested clock for AUX_ADI4 +#define AUX_WUC_MODCLKEN0_AUX_ADI4 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_BITN 7 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_M 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_S 7 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_EN 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_DIS 0x00000000 + +// Field: [6] AUX_DDI0_OSC +// +// Enables (1) or disables (0) clock for AUX_DDI0_OSC. +// ENUMs: +// EN System CPU has requested clock for AUX_DDI0_OSC +// DIS System CPU has not requested clock for +// AUX_DDI0_OSC +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_BITN 6 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_M 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_S 6 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_DIS 0x00000000 + +// Field: [5] TDC +// +// Enables (1) or disables (0) clock for AUX_TDCIF. +// +// Note that the TDC counter and reference clock sources must be requested +// separately using TDCCLKCTL and REFCLKCTL, respectively. +// ENUMs: +// EN System CPU has requested clock for TDC +// DIS System CPU has not requested clock for TDC +#define AUX_WUC_MODCLKEN0_TDC 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_BITN 5 +#define AUX_WUC_MODCLKEN0_TDC_M 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_S 5 +#define AUX_WUC_MODCLKEN0_TDC_EN 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_DIS 0x00000000 + +// Field: [4] ANAIF +// +// Enables (1) or disables (0) clock for AUX_ANAIF. +// +// Note that the ADC internal clock must be requested separately using +// ADCCLKCTL. +// ENUMs: +// EN System CPU has requested clock for ANAIF +// DIS System CPU has not requested clock for ANAIF +#define AUX_WUC_MODCLKEN0_ANAIF 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_BITN 4 +#define AUX_WUC_MODCLKEN0_ANAIF_M 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_S 4 +#define AUX_WUC_MODCLKEN0_ANAIF_EN 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_DIS 0x00000000 + +// Field: [3] TIMER +// +// Enables (1) or disables (0) clock for AUX_TIMER. +// ENUMs: +// EN System CPU has requested clock for TIMER +// DIS System CPU has not requested clock for TIMER +#define AUX_WUC_MODCLKEN0_TIMER 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_BITN 3 +#define AUX_WUC_MODCLKEN0_TIMER_M 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_S 3 +#define AUX_WUC_MODCLKEN0_TIMER_EN 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_DIS 0x00000000 + +// Field: [2] AIODIO1 +// +// Enables (1) or disables (0) clock for AUX_AIODIO1. +// ENUMs: +// EN System CPU has requested clock for AIODIO1 +// DIS System CPU has not requested clock for AIODIO1 +#define AUX_WUC_MODCLKEN0_AIODIO1 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_BITN 2 +#define AUX_WUC_MODCLKEN0_AIODIO1_M 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_S 2 +#define AUX_WUC_MODCLKEN0_AIODIO1_EN 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_DIS 0x00000000 + +// Field: [1] AIODIO0 +// +// Enables (1) or disables (0) clock for AUX_AIODIO0. +// ENUMs: +// EN System CPU has requested clock for AIODIO0 +// DIS System CPU has not requested clock for AIODIO0 +#define AUX_WUC_MODCLKEN0_AIODIO0 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_BITN 1 +#define AUX_WUC_MODCLKEN0_AIODIO0_M 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_S 1 +#define AUX_WUC_MODCLKEN0_AIODIO0_EN 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_DIS 0x00000000 + +// Field: [0] SMPH +// +// Enables (1) or disables (0) clock for AUX_SMPH. +// ENUMs: +// EN System CPU has requested clock for SMPH +// DIS System CPU has not requested clock for SMPH +#define AUX_WUC_MODCLKEN0_SMPH 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_BITN 0 +#define AUX_WUC_MODCLKEN0_SMPH_M 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_S 0 +#define AUX_WUC_MODCLKEN0_SMPH_EN 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_WUC_O_PWROFFREQ +// +//***************************************************************************** +// Field: [0] REQ +// +// Power off request +// +// 0: No action +// 1: Request to power down AUX. Once set, this bit shall not be cleared. The +// bit will be reset again when AUX is powered up again. +// +// The request will only happen if AONCTLSTAT.AUX_FORCE_ON = 0 and +// MCUBUSSTAT.DISCONNECTED=1. +#define AUX_WUC_PWROFFREQ_REQ 0x00000001 +#define AUX_WUC_PWROFFREQ_REQ_BITN 0 +#define AUX_WUC_PWROFFREQ_REQ_M 0x00000001 +#define AUX_WUC_PWROFFREQ_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_PWRDWNREQ +// +//***************************************************************************** +// Field: [0] REQ +// +// Power down request +// +// 0: Request for system to be in active mode +// 1: Request for system to be in power down mode +// +// When REQ is 1 one shall assume that the system is in power down, and that +// current supply is limited. When setting REQ = 0, one shall assume that the +// system is in power down until PWRDWNACK.ACK = 0 +#define AUX_WUC_PWRDWNREQ_REQ 0x00000001 +#define AUX_WUC_PWRDWNREQ_REQ_BITN 0 +#define AUX_WUC_PWRDWNREQ_REQ_M 0x00000001 +#define AUX_WUC_PWRDWNREQ_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_PWRDWNACK +// +//***************************************************************************** +// Field: [0] ACK +// +// Power down acknowledgment. Indicates whether the power down request given by +// PWRDWNREQ.REQ is captured by the AON domain or not +// +// 0: AUX can assume that the system is in active mode +// 1: The request for power down is acknowledged and the AUX must act like the +// system is in power down mode and power supply is limited +// +// The system CPU cannot use this bit since the bus bridge between MCU domain +// and AUX domain is always disconnected when this bit is set. For AUX_SCE use +// only +#define AUX_WUC_PWRDWNACK_ACK 0x00000001 +#define AUX_WUC_PWRDWNACK_ACK_BITN 0 +#define AUX_WUC_PWRDWNACK_ACK_M 0x00000001 +#define AUX_WUC_PWRDWNACK_ACK_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_CLKLFREQ +// +//***************************************************************************** +// Field: [0] REQ +// +// Low frequency request +// +// 0: Request clock frequency to be controlled by AON_WUC:AUXCLK and the system +// state +// 1: Request low frequency clock SCLK_LF as the clock source for AUX +// +// This bit must not be modified unless CLKLFACK.ACK matches the current value +#define AUX_WUC_CLKLFREQ_REQ 0x00000001 +#define AUX_WUC_CLKLFREQ_REQ_BITN 0 +#define AUX_WUC_CLKLFREQ_REQ_M 0x00000001 +#define AUX_WUC_CLKLFREQ_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_CLKLFACK +// +//***************************************************************************** +// Field: [0] ACK +// +// Acknowledgment of CLKLFREQ.REQ +// +// 0: Acknowledgement that clock frequency is controlled by AON_WUC:AUXCLK and +// the system state +// 1: Acknowledgement that the low frequency clock SCLK_LF is the clock source +// for AUX +#define AUX_WUC_CLKLFACK_ACK 0x00000001 +#define AUX_WUC_CLKLFACK_ACK_BITN 0 +#define AUX_WUC_CLKLFACK_ACK_M 0x00000001 +#define AUX_WUC_CLKLFACK_ACK_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_WUEVFLAGS +// +//***************************************************************************** +// Field: [2] AON_RTC_CH2 +// +// Indicates pending event from AON_RTC_CH2 compare. Note that this flag will +// be set whenever the AON_RTC_CH2 event happens, but that does not mean that +// this event is a wake-up event. To make the AON_RTC_CH2 a wake-up event for +// the AUX domain configure it as a wake-up event in AON_EVENT:AUXWUSEL.WU0_EV, +// AON_EVENT:AUXWUSEL.WU1_EV or AON_EVENT:AUXWUSEL.WU2_EV. +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2 0x00000004 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_BITN 2 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_M 0x00000004 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_S 2 + +// Field: [1] AON_SW +// +// Indicates pending event triggered by system CPU writing a 1 to +// AON_WUC:AUXCTL.SWEV. +#define AUX_WUC_WUEVFLAGS_AON_SW 0x00000002 +#define AUX_WUC_WUEVFLAGS_AON_SW_BITN 1 +#define AUX_WUC_WUEVFLAGS_AON_SW_M 0x00000002 +#define AUX_WUC_WUEVFLAGS_AON_SW_S 1 + +// Field: [0] AON_PROG_WU +// +// Indicates pending event triggered by the sources selected in +// AON_EVENT:AUXWUSEL.WU0_EV, AON_EVENT:AUXWUSEL.WU1_EV and +// AON_EVENT:AUXWUSEL.WU2_EV. +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU 0x00000001 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_BITN 0 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_M 0x00000001 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_WUEVCLR +// +//***************************************************************************** +// Field: [2] AON_RTC_CH2 +// +// Set to clear the WUEVFLAGS.AON_RTC_CH2 wake-up event. Note that if RTC +// channel 2 is also set as source for AON_PROG_WU this field can also clear +// WUEVFLAGS.AON_PROG_WU +// +// This bit must remain set until WUEVFLAGS.AON_RTC_CH2 returns to 0. +#define AUX_WUC_WUEVCLR_AON_RTC_CH2 0x00000004 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_BITN 2 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_M 0x00000004 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_S 2 + +// Field: [1] AON_SW +// +// Set to clear the WUEVFLAGS.AON_SW wake-up event. +// +// This bit must remain set until WUEVFLAGS.AON_SW returns to 0. +#define AUX_WUC_WUEVCLR_AON_SW 0x00000002 +#define AUX_WUC_WUEVCLR_AON_SW_BITN 1 +#define AUX_WUC_WUEVCLR_AON_SW_M 0x00000002 +#define AUX_WUC_WUEVCLR_AON_SW_S 1 + +// Field: [0] AON_PROG_WU +// +// Set to clear the WUEVFLAGS.AON_PROG_WU wake-up event. Note only if an IO +// event is selected as wake-up event, is it possible to use this field to +// clear the source. Other sources cannot be cleared using this field. +// +// The IO pin needs to be assigned to AUX in the IOC and the input enable for +// the pin needs to be set in AIODIO0 or AIODIO1 for this clearing to take +// effect. +// +// This bit must remain set until WUEVFLAGS.AON_PROG_WU returns to 0. +#define AUX_WUC_WUEVCLR_AON_PROG_WU 0x00000001 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_BITN 0 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_M 0x00000001 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_ADCCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// Acknowledges the last value written to REQ. +#define AUX_WUC_ADCCLKCTL_ACK 0x00000002 +#define AUX_WUC_ADCCLKCTL_ACK_BITN 1 +#define AUX_WUC_ADCCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_ADCCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// Enables(1) or disables (0) the ADC internal clock. +// +// This bit must not be modified unless ACK matches the current value. +#define AUX_WUC_ADCCLKCTL_REQ 0x00000001 +#define AUX_WUC_ADCCLKCTL_REQ_BITN 0 +#define AUX_WUC_ADCCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_ADCCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_TDCCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// Acknowledges the last value written to REQ. +#define AUX_WUC_TDCCLKCTL_ACK 0x00000002 +#define AUX_WUC_TDCCLKCTL_ACK_BITN 1 +#define AUX_WUC_TDCCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_TDCCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// Enables(1) or disables (0) the TDC counter clock source. +// +// This bit must not be modified unless ACK matches the current value. +#define AUX_WUC_TDCCLKCTL_REQ 0x00000001 +#define AUX_WUC_TDCCLKCTL_REQ_BITN 0 +#define AUX_WUC_TDCCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_TDCCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_REFCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// Acknowledges the last value written to REQ. +#define AUX_WUC_REFCLKCTL_ACK 0x00000002 +#define AUX_WUC_REFCLKCTL_ACK_BITN 1 +#define AUX_WUC_REFCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_REFCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// Enables(1) or disables (0) the TDC reference clock source. +// +// This bit must not be modified unless ACK matches the current value. +#define AUX_WUC_REFCLKCTL_REQ 0x00000001 +#define AUX_WUC_REFCLKCTL_REQ_BITN 0 +#define AUX_WUC_REFCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_REFCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_RTCSUBSECINC0 +// +//***************************************************************************** +// Field: [15:0] INC15_0 +// +// Bits 15:0 of the RTC sub-second increment value. +#define AUX_WUC_RTCSUBSECINC0_INC15_0_W 16 +#define AUX_WUC_RTCSUBSECINC0_INC15_0_M 0x0000FFFF +#define AUX_WUC_RTCSUBSECINC0_INC15_0_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_RTCSUBSECINC1 +// +//***************************************************************************** +// Field: [7:0] INC23_16 +// +// Bits 23:16 of the RTC sub-second increment value. +#define AUX_WUC_RTCSUBSECINC1_INC23_16_W 8 +#define AUX_WUC_RTCSUBSECINC1_INC23_16_M 0x000000FF +#define AUX_WUC_RTCSUBSECINC1_INC23_16_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_RTCSUBSECINCCTL +// +//***************************************************************************** +// Field: [1] UPD_ACK +// +// Acknowledgment of the UPD_REQ. +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK 0x00000002 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN 1 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_S 1 + +// Field: [0] UPD_REQ +// +// Signal that a new real time counter sub second increment value is available +// +// 0: New sub second increment is not available +// 1: New sub second increment is available +// +// This bit must not be modified unless UPD_ACK matches the current value. +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ 0x00000001 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_BITN 0 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_MCUBUSCTL +// +//***************************************************************************** +// Field: [0] DISCONNECT_REQ +// +// Requests the AUX domain bus to be disconnected from the MCU domain bus. The +// request has no effect when AON_WUC:AUX_CTL.AUX_FORCE_ON is set. +// +// The disconnection status can be monitored through MCUBUSSTAT. Note however +// that this register cannot be read by the system CPU while disconnected. +// +// It is recommended that this bit is set and remains set after initial +// power-up, and that the system CPU uses AON_WUC:AUX_CTL.AUX_FORCE_ON to +// connect/disconnect the bus. +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ 0x00000001 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_BITN 0 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_M 0x00000001 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_MCUBUSSTAT +// +//***************************************************************************** +// Field: [1] DISCONNECTED +// +// Indicates whether the AUX domain and MCU domain buses are currently +// disconnected (1) or connected (0). +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED 0x00000002 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_BITN 1 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_M 0x00000002 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_S 1 + +// Field: [0] DISCONNECT_ACK +// +// Acknowledges reception of the bus disconnection request, by matching the +// value of MCUBUSCTL.DISCONNECT_REQ. +// +// Note that if AON_WUC:AUXCTL.AUX_FORCE_ON = 1 a reconnect to the MCU domain +// bus will be made regardless of the state of MCUBUSCTL.DISCONNECT_REQ +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK 0x00000001 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_BITN 0 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_M 0x00000001 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_AONCTLSTAT +// +//***************************************************************************** +// Field: [1] AUX_FORCE_ON +// +// Status of AON_WUC:AUX_CTL.AUX_FORCE_ON. +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON 0x00000002 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_BITN 1 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_M 0x00000002 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_S 1 + +// Field: [0] SCE_RUN_EN +// +// Status of AON_WUC:AUX_CTL.SCE_RUN_EN. +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN 0x00000001 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_BITN 0 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_M 0x00000001 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_WUC_O_AUXIOLATCH +// +//***************************************************************************** +// Field: [0] EN +// +// Opens (1) or closes (0) the AUX_AIODIO0/AUX_AIODIO1 signal latching. +// +// At startup, set EN = TRANSP before configuring AUX_AIODIO0/AUX_AIODIO1 and +// subsequently selecting AUX mode in the AON_IOC. +// +// When powering off the AUX domain (using PWROFFREQ.REQ), set EN = STATIC in +// advance preserve the current state (mode and output value) of the I/O pins. +// ENUMs: +// TRANSP Latches are transparent ( open ) +// STATIC Latches are static ( closed ) +#define AUX_WUC_AUXIOLATCH_EN 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_BITN 0 +#define AUX_WUC_AUXIOLATCH_EN_M 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_S 0 +#define AUX_WUC_AUXIOLATCH_EN_TRANSP 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_STATIC 0x00000000 + +//***************************************************************************** +// +// Register: AUX_WUC_O_MODCLKEN1 +// +//***************************************************************************** +// Field: [7] AUX_ADI4 +// +// Enables (1) or disables (0) clock for AUX_ADI4. +// ENUMs: +// EN AUX_SCE has requested clock for AUX_ADI4 +// DIS AUX_SCE has not requested clock for AUX_ADI4 +#define AUX_WUC_MODCLKEN1_AUX_ADI4 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_BITN 7 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_M 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_S 7 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_EN 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_DIS 0x00000000 + +// Field: [6] AUX_DDI0_OSC +// +// Enables (1) or disables (0) clock for AUX_DDI0_OSC. +// ENUMs: +// EN AUX_SCE has requested clock for AUX_DDI0_OSC +// DIS AUX_SCE has not requested clock for AUX_DDI0_OSC +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_BITN 6 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_M 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_S 6 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_EN 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_DIS 0x00000000 + +// Field: [4] ANAIF +// +// Enables (1) or disables (0) clock for AUX_ANAIF. +// ENUMs: +// EN AUX_SCE has requested clock for ANAIF +// DIS AUX_SCE has not requested clock for ANAIF +#define AUX_WUC_MODCLKEN1_ANAIF 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_BITN 4 +#define AUX_WUC_MODCLKEN1_ANAIF_M 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_S 4 +#define AUX_WUC_MODCLKEN1_ANAIF_EN 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_DIS 0x00000000 + +// Field: [3] TIMER +// +// Enables (1) or disables (0) clock for AUX_TIMER. +// ENUMs: +// EN AUX_SCE has requested clock for TIMER +// DIS AUX_SCE has not requested clock for TIMER +#define AUX_WUC_MODCLKEN1_TIMER 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_BITN 3 +#define AUX_WUC_MODCLKEN1_TIMER_M 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_S 3 +#define AUX_WUC_MODCLKEN1_TIMER_EN 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_DIS 0x00000000 + +// Field: [2] AIODIO1 +// +// Enables (1) or disables (0) clock for AUX_AIODIO1. +// ENUMs: +// EN AUX_SCE has requested clock for AIODIO1 +// DIS AUX_SCE has not requested clock for AIODIO1 +#define AUX_WUC_MODCLKEN1_AIODIO1 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_BITN 2 +#define AUX_WUC_MODCLKEN1_AIODIO1_M 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_S 2 +#define AUX_WUC_MODCLKEN1_AIODIO1_EN 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_DIS 0x00000000 + +// Field: [1] AIODIO0 +// +// Enables (1) or disables (0) clock for AUX_AIODIO0. +// ENUMs: +// EN AUX_SCE has requested clock for AIODIO0 +// DIS AUX_SCE has not requested clock for AIODIO0 +#define AUX_WUC_MODCLKEN1_AIODIO0 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_BITN 1 +#define AUX_WUC_MODCLKEN1_AIODIO0_M 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_S 1 +#define AUX_WUC_MODCLKEN1_AIODIO0_EN 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_DIS 0x00000000 + +// Field: [0] SMPH +// +// Enables (1) or disables (0) clock for AUX_SMPH. +// ENUMs: +// EN AUX_SCE has requested clock for SMPH +// DIS AUX_SCE has not requested clock for SMPH +#define AUX_WUC_MODCLKEN1_SMPH 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_BITN 0 +#define AUX_WUC_MODCLKEN1_SMPH_M 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_S 0 +#define AUX_WUC_MODCLKEN1_SMPH_EN 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_DIS 0x00000000 + + +#endif // __AUX_WUC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg.h new file mode 100644 index 0000000..31b9b2a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg.h @@ -0,0 +1,1919 @@ +/****************************************************************************** +* Filename: hw_ccfg_h +* Revised: 2017-02-06 19:32:22 +0100 (Mon, 06 Feb 2017) +* Revision: 48408 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CCFG_H__ +#define __HW_CCFG_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CCFG component +// +//***************************************************************************** +// Extern LF clock configuration +#define CCFG_O_EXT_LF_CLK 0x00000FA8 + +// Mode Configuration 1 +#define CCFG_O_MODE_CONF_1 0x00000FAC + +// CCFG Size and Disable Flags +#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00000FB0 + +// Mode Configuration 0 +#define CCFG_O_MODE_CONF 0x00000FB4 + +// Voltage Load 0 +#define CCFG_O_VOLT_LOAD_0 0x00000FB8 + +// Voltage Load 1 +#define CCFG_O_VOLT_LOAD_1 0x00000FBC + +// Real Time Clock Offset +#define CCFG_O_RTC_OFFSET 0x00000FC0 + +// Frequency Offset +#define CCFG_O_FREQ_OFFSET 0x00000FC4 + +// IEEE MAC Address 0 +#define CCFG_O_IEEE_MAC_0 0x00000FC8 + +// IEEE MAC Address 1 +#define CCFG_O_IEEE_MAC_1 0x00000FCC + +// IEEE BLE Address 0 +#define CCFG_O_IEEE_BLE_0 0x00000FD0 + +// IEEE BLE Address 1 +#define CCFG_O_IEEE_BLE_1 0x00000FD4 + +// Bootloader Configuration +#define CCFG_O_BL_CONFIG 0x00000FD8 + +// Erase Configuration +#define CCFG_O_ERASE_CONF 0x00000FDC + +// TI Options +#define CCFG_O_CCFG_TI_OPTIONS 0x00000FE0 + +// Test Access Points Enable 0 +#define CCFG_O_CCFG_TAP_DAP_0 0x00000FE4 + +// Test Access Points Enable 1 +#define CCFG_O_CCFG_TAP_DAP_1 0x00000FE8 + +// Image Valid +#define CCFG_O_IMAGE_VALID_CONF 0x00000FEC + +// Protect Sectors 0-31 +#define CCFG_O_CCFG_PROT_31_0 0x00000FF0 + +// Protect Sectors 32-63 +#define CCFG_O_CCFG_PROT_63_32 0x00000FF4 + +// Protect Sectors 64-95 +#define CCFG_O_CCFG_PROT_95_64 0x00000FF8 + +// Protect Sectors 96-127 +#define CCFG_O_CCFG_PROT_127_96 0x00000FFC + +//***************************************************************************** +// +// Register: CCFG_O_EXT_LF_CLK +// +//***************************************************************************** +// Field: [31:24] DIO +// +// Unsigned integer, selecting the DIO to supply external 32kHz clock as +// SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO +// will be marked as reserved by the pin driver (TI-RTOS environment) and hence +// not selectable for other usage. +#define CCFG_EXT_LF_CLK_DIO_W 8 +#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 +#define CCFG_EXT_LF_CLK_DIO_S 24 + +// Field: [23:0] RTC_INCREMENT +// +// Unsigned integer, defining the input frequency of the external clock and is +// written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: +// EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: +// RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_MODE_CONF_1 +// +//***************************************************************************** +// Field: [23:20] ALT_DCDC_VMIN +// +// Minimum voltage for when DC/DC should be used if alternate DC/DC setting is +// enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). +// Voltage = (28 + ALT_DCDC_VMIN) / 16. +// 0: 1.75V +// 1: 1.8125V +// ... +// 14: 2.625V +// 15: 2.6875V +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 + +// Field: [19] ALT_DCDC_DITHER_EN +// +// Enable DC/DC dithering if alternate DC/DC setting is enabled +// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). +// 0: Dither disable +// 1: Dither enable +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 + +// Field: [18:16] ALT_DCDC_IPEAK +// +// Inductor peak current if alternate DC/DC setting is enabled +// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external +// inductor! +// Peak current = 31 + ( 4 * ALT_DCDC_IPEAK ) : +// 0: 31mA (min) +// ... +// 4: 47mA +// ... +// 7: 59mA (max) +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 + +// Field: [15:12] DELTA_IBIAS_INIT +// +// Signed delta value for IBIAS_INIT. Delta value only applies if +// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +// See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 + +// Field: [11:8] DELTA_IBIAS_OFFSET +// +// Signed delta value for IBIAS_OFFSET. Delta value only applies if +// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +// See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 + +// Field: [7:0] XOSC_MAX_START +// +// Unsigned value of maximum XOSC startup time (worst case) in units of 100us. +// Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 +#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF +#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_SIZE_AND_DIS_FLAGS +// +//***************************************************************************** +// Field: [31:16] SIZE_OF_CCFG +// +// Total size of CCFG in bytes. +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 + +// Field: [15:4] DISABLE_FLAGS +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 + +// Field: [3] DIS_TCXO +// +// Disable TCXO. +// 0: TCXO functionality enabled. +// 1: TCXO functionality disabled. +// Note: +// An external TCXO is required if DIS_TCXO = 0. +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 + +// Field: [2] DIS_GPRAM +// +// Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). +// 0: GPRAM is enabled and hence CACHE disabled. +// 1: GPRAM is disabled and instead CACHE is enabled (default). +// Notes: +// - Disabling CACHE will reduce CPU execution speed (up to 60%). +// - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if +// enabled. +// See: +// VIMS:CTL.MODE +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 + +// Field: [1] DIS_ALT_DCDC_SETTING +// +// Disable alternate DC/DC settings. +// 0: Enable alternate DC/DC settings. +// 1: Disable alternate DC/DC settings. +// See: +// MODE_CONF_1.ALT_DCDC_VMIN +// MODE_CONF_1.ALT_DCDC_DITHER_EN +// MODE_CONF_1.ALT_DCDC_IPEAK +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 + +// Field: [0] DIS_XOSC_OVR +// +// Disable XOSC override functionality. +// 0: Enable XOSC override functionality. +// 1: Disable XOSC override functionality. +// See: +// MODE_CONF_1.DELTA_IBIAS_INIT +// MODE_CONF_1.DELTA_IBIAS_OFFSET +// MODE_CONF_1.XOSC_MAX_START +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_MODE_CONF +// +//***************************************************************************** +// Field: [31:28] VDDR_TRIM_SLEEP_DELTA +// +// Signed delta value to apply to the +// VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H. +// 0x8 (-8) : Delta = -7 +// ... +// 0xF (-1) : Delta = 0 +// 0x0 (0) : Delta = +1 +// ... +// 0x7 (7) : Delta = +8 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 + +// Field: [27] DCDC_RECHARGE +// +// DC/DC during recharge in powerdown. +// 0: Use the DC/DC during recharge in powerdown. +// 1: Do not use the DC/DC during recharge in powerdown (default). +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 +#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 + +// Field: [26] DCDC_ACTIVE +// +// DC/DC in active mode. +// 0: Use the DC/DC during active mode. +// 1: Do not use the DC/DC during active mode (default). +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 +#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 + +// Field: [25] VDDR_EXT_LOAD +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 + +// Field: [24] VDDS_BOD_LEVEL +// +// VDDS BOD level. +// 0: VDDS BOD level is 2.0 V (necessary for maximum PA output power on +// CC13x0). +// 1: VDDS BOD level is 1.8 V (or 1.7 V for external regulator mode) (default). +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 + +// Field: [23:22] SCLK_LF_OPTION +// +// Select source for SCLK_LF. +// ENUMs: +// RCOSC_LF Low frequency RCOSC (default) +// XOSC_LF 32.768kHz low frequency XOSC +// EXTERNAL_LF External low frequency clock on DIO defined by +// EXT_LF_CLK.DIO. The RTC tick speed +// AON_RTC:SUBSECINC is updated to +// EXT_LF_CLK.RTC_INCREMENT (done in the +// trimDevice() xxWare boot function). External +// clock must always be running when the chip is +// in standby for VDDR recharge timing. +// XOSC_HF_DLF 31.25kHz clock derived from 24MHz XOSC (dividing +// by 768 in HW). The RTC tick speed +// [AON_RTC.SUBSECINC.*] is updated to 0x8637BD, +// corresponding to a 31.25kHz clock (done in the +// trimDevice() xxWare boot function). Standby +// power mode is not supported when using this +// clock source. +#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 + +// Field: [21] VDDR_TRIM_SLEEP_TC +// +// 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated +// 0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time +// standby mode is entered. This improves low-temperature RCOSC_LF frequency +// stability in standby mode. +// +// When temperature compensation is performed, the delta is calculates this +// way: +// Delta = max (delta, min(8, floor(62-temp)/8)) +// Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current +// temperature in degrees C. +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 + +// Field: [20] RTC_COMP +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_RTC_COMP 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_BITN 20 +#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_S 20 + +// Field: [19:18] XOSC_FREQ +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +// ENUMs: +// 24M 24 MHz XOSC_HF +// 48M 48 MHz XOSC_HF +// HPOSC HPOSC +#define CCFG_MODE_CONF_XOSC_FREQ_W 2 +#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_S 18 +#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 +#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 + +// Field: [17] XOSC_CAP_MOD +// +// Enable modification (delta) to XOSC cap-array. Value specified in +// XOSC_CAPARRAY_DELTA. +// 0: Apply cap-array delta +// 1: Do not apply cap-array delta (default) +#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 + +// Field: [16] HF_COMP +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_HF_COMP 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_BITN 16 +#define CCFG_MODE_CONF_HF_COMP_M 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_S 16 + +// Field: [15:8] XOSC_CAPARRAY_DELTA +// +// Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. +// Enabled by XOSC_CAP_MOD. +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 + +// Field: [7:0] VDDR_CAP +// +// Unsigned 8-bit integer, representing the minimum decoupling capacitance +// (worst case) on VDDR, in units of 100nF. This should take into account +// capacitor tolerance and voltage dependent capacitance variation. This bit +// affects the recharge period calculation when going into powerdown or +// standby. +// +// NOTE! If using the following functions this field must be configured (used +// by TI RTOS): +// SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() +#define CCFG_MODE_CONF_VDDR_CAP_W 8 +#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF +#define CCFG_MODE_CONF_VDDR_CAP_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_VOLT_LOAD_0 +// +//***************************************************************************** +// Field: [31:24] VDDR_EXT_TP45 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 + +// Field: [23:16] VDDR_EXT_TP25 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 + +// Field: [15:8] VDDR_EXT_TP5 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 + +// Field: [7:0] VDDR_EXT_TM15 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_VOLT_LOAD_1 +// +//***************************************************************************** +// Field: [31:24] VDDR_EXT_TP125 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 + +// Field: [23:16] VDDR_EXT_TP105 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 + +// Field: [15:8] VDDR_EXT_TP85 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 + +// Field: [7:0] VDDR_EXT_TP65 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_RTC_OFFSET +// +//***************************************************************************** +// Field: [31:16] RTC_COMP_P0 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 + +// Field: [15:8] RTC_COMP_P1 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 + +// Field: [7:0] RTC_COMP_P2 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF +#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_FREQ_OFFSET +// +//***************************************************************************** +// Field: [31:16] HF_COMP_P0 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 + +// Field: [15:8] HF_COMP_P1 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 + +// Field: [7:0] HF_COMP_P2 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF +#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_MAC_0 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[31:0] of the 64-bits custom IEEE MAC address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_MAC_0_ADDR_W 32 +#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_0_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_MAC_1 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[63:32] of the 64-bits custom IEEE MAC address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_MAC_1_ADDR_W 32 +#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_1_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_BLE_0 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[31:0] of the 64-bits custom IEEE BLE address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_BLE_0_ADDR_W 32 +#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_0_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_BLE_1 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[63:32] of the 64-bits custom IEEE BLE address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_BLE_1_ADDR_W 32 +#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_1_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_BL_CONFIG +// +//***************************************************************************** +// Field: [31:24] BOOTLOADER_ENABLE +// +// Bootloader enable. Boot loader can be accessed if +// IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and +// conditions for boot loader backdoor are met). +// 0xC5: Boot loader is enabled. +// Any other value: Boot loader is disabled. +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 + +// Field: [16] BL_LEVEL +// +// Sets the active level of the selected DIO number BL_PIN_NUMBER if boot +// loader backdoor is enabled by the BL_ENABLE field. +// 0: Active low. +// 1: Active high. +#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 +#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_S 16 + +// Field: [15:8] BL_PIN_NUMBER +// +// DIO number that is level checked if the boot loader backdoor is enabled by +// the BL_ENABLE field. +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 + +// Field: [7:0] BL_ENABLE +// +// Enables the boot loader backdoor. +// 0xC5: Boot loader backdoor is enabled. +// Any other value: Boot loader backdoor is disabled. +// +// NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader +// backdoor is enabled. +#define CCFG_BL_CONFIG_BL_ENABLE_W 8 +#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF +#define CCFG_BL_CONFIG_BL_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_ERASE_CONF +// +//***************************************************************************** +// Field: [8] CHIP_ERASE_DIS_N +// +// Chip erase. +// This bit controls if a chip erase requested through the JTAG WUC TAP will be +// ignored in a following boot caused by a reset of the MCU VD. +// A successful chip erase operation will force the content of the flash main +// bank back to the state as it was when delivered by TI. +// 0: Disable. Any chip erase request detected during boot will be ignored. +// 1: Enable. Any chip erase request detected during boot will be performed by +// the boot FW. +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 + +// Field: [0] BANK_ERASE_DIS_N +// +// Bank erase. +// This bit controls if the ROM serial boot loader will accept a received Bank +// Erase command (COMMAND_BANK_ERASE). +// A successful Bank Erase operation will erase all main bank sectors not +// protected by write protect configuration bits in CCFG. +// 0: Disable the boot loader bank erase function. +// 1: Enable the boot loader bank erase function. +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TI_OPTIONS +// +//***************************************************************************** +// Field: [7:0] TI_FA_ENABLE +// +// TI Failure Analysis. +// 0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) +// option with the unlock code. +// All other values: Disable the functionality of unlocking the TI FA option +// with the unlock code. +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TAP_DAP_0 +// +//***************************************************************************** +// Field: [23:16] CPU_DAP_ENABLE +// +// Enable CPU DAP. +// 0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM +// boot FW. +// Any other value: Main CPU DAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 + +// Field: [15:8] PRCM_TAP_ENABLE +// +// Enable PRCM TAP. +// 0xC5: PRCM TAP access is enabled during power-up/system-reset by ROM boot FW +// if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PRCM TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_S 8 + +// Field: [7:0] TEST_TAP_ENABLE +// +// Enable Test TAP. +// 0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW +// if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: TEST TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TAP_DAP_1 +// +//***************************************************************************** +// Field: [23:16] PBIST2_TAP_ENABLE +// +// Enable PBIST2 TAP. +// 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot +// FW if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PBIST2 TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 + +// Field: [15:8] PBIST1_TAP_ENABLE +// +// Enable PBIST1 TAP. +// 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot +// FW if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PBIST1 TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 + +// Field: [7:0] WUC_TAP_ENABLE +// +// Enable WUC TAP +// 0xC5: WUC TAP access is enabled during power-up/system-reset by ROM boot FW +// if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: WUC TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IMAGE_VALID_CONF +// +//***************************************************************************** +// Field: [31:0] IMAGE_VALID +// +// This field must have a value of 0x00000000 in order for enabling the boot +// sequence to transfer control to a flash image. +// A non-zero value forces the boot sequence to call the boot loader. +// +// For CC2640R2: +// This field must have the address value of the start of the flash vector +// table in order for enabling the boot sequence to transfer control to a flash +// image. +// Any illegal vector table start address value forces the boot sequence to +// call the boot loader. +// Note that if any other legal vector table start address value than 0x0 is +// selected the PRCM:WARMRESET.WR_TO_PINRESET must be set to 1. +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_31_0 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_31 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 + +// Field: [30] WRT_PROT_SEC_30 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 + +// Field: [29] WRT_PROT_SEC_29 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 + +// Field: [28] WRT_PROT_SEC_28 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 + +// Field: [27] WRT_PROT_SEC_27 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 + +// Field: [26] WRT_PROT_SEC_26 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 + +// Field: [25] WRT_PROT_SEC_25 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 + +// Field: [24] WRT_PROT_SEC_24 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 + +// Field: [23] WRT_PROT_SEC_23 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 + +// Field: [22] WRT_PROT_SEC_22 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 + +// Field: [21] WRT_PROT_SEC_21 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 + +// Field: [20] WRT_PROT_SEC_20 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 + +// Field: [19] WRT_PROT_SEC_19 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 + +// Field: [18] WRT_PROT_SEC_18 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 + +// Field: [17] WRT_PROT_SEC_17 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 + +// Field: [16] WRT_PROT_SEC_16 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 + +// Field: [15] WRT_PROT_SEC_15 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 + +// Field: [14] WRT_PROT_SEC_14 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 + +// Field: [13] WRT_PROT_SEC_13 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 + +// Field: [12] WRT_PROT_SEC_12 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 + +// Field: [11] WRT_PROT_SEC_11 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 + +// Field: [10] WRT_PROT_SEC_10 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 + +// Field: [9] WRT_PROT_SEC_9 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 + +// Field: [8] WRT_PROT_SEC_8 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 + +// Field: [7] WRT_PROT_SEC_7 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 + +// Field: [6] WRT_PROT_SEC_6 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 + +// Field: [5] WRT_PROT_SEC_5 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 + +// Field: [4] WRT_PROT_SEC_4 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 + +// Field: [3] WRT_PROT_SEC_3 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 + +// Field: [2] WRT_PROT_SEC_2 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 + +// Field: [1] WRT_PROT_SEC_1 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 + +// Field: [0] WRT_PROT_SEC_0 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_63_32 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_63 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 + +// Field: [30] WRT_PROT_SEC_62 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 + +// Field: [29] WRT_PROT_SEC_61 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 + +// Field: [28] WRT_PROT_SEC_60 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 + +// Field: [27] WRT_PROT_SEC_59 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 + +// Field: [26] WRT_PROT_SEC_58 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 + +// Field: [25] WRT_PROT_SEC_57 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 + +// Field: [24] WRT_PROT_SEC_56 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 + +// Field: [23] WRT_PROT_SEC_55 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 + +// Field: [22] WRT_PROT_SEC_54 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 + +// Field: [21] WRT_PROT_SEC_53 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 + +// Field: [20] WRT_PROT_SEC_52 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 + +// Field: [19] WRT_PROT_SEC_51 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 + +// Field: [18] WRT_PROT_SEC_50 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 + +// Field: [17] WRT_PROT_SEC_49 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 + +// Field: [16] WRT_PROT_SEC_48 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 + +// Field: [15] WRT_PROT_SEC_47 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 + +// Field: [14] WRT_PROT_SEC_46 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 + +// Field: [13] WRT_PROT_SEC_45 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 + +// Field: [12] WRT_PROT_SEC_44 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 + +// Field: [11] WRT_PROT_SEC_43 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 + +// Field: [10] WRT_PROT_SEC_42 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 + +// Field: [9] WRT_PROT_SEC_41 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 + +// Field: [8] WRT_PROT_SEC_40 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 + +// Field: [7] WRT_PROT_SEC_39 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 + +// Field: [6] WRT_PROT_SEC_38 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 + +// Field: [5] WRT_PROT_SEC_37 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 + +// Field: [4] WRT_PROT_SEC_36 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 + +// Field: [3] WRT_PROT_SEC_35 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 + +// Field: [2] WRT_PROT_SEC_34 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 + +// Field: [1] WRT_PROT_SEC_33 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 + +// Field: [0] WRT_PROT_SEC_32 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_95_64 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_95 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 + +// Field: [30] WRT_PROT_SEC_94 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 + +// Field: [29] WRT_PROT_SEC_93 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 + +// Field: [28] WRT_PROT_SEC_92 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 + +// Field: [27] WRT_PROT_SEC_91 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 + +// Field: [26] WRT_PROT_SEC_90 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 + +// Field: [25] WRT_PROT_SEC_89 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 + +// Field: [24] WRT_PROT_SEC_88 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 + +// Field: [23] WRT_PROT_SEC_87 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 + +// Field: [22] WRT_PROT_SEC_86 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 + +// Field: [21] WRT_PROT_SEC_85 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 + +// Field: [20] WRT_PROT_SEC_84 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 + +// Field: [19] WRT_PROT_SEC_83 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 + +// Field: [18] WRT_PROT_SEC_82 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 + +// Field: [17] WRT_PROT_SEC_81 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 + +// Field: [16] WRT_PROT_SEC_80 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 + +// Field: [15] WRT_PROT_SEC_79 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 + +// Field: [14] WRT_PROT_SEC_78 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 + +// Field: [13] WRT_PROT_SEC_77 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 + +// Field: [12] WRT_PROT_SEC_76 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 + +// Field: [11] WRT_PROT_SEC_75 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 + +// Field: [10] WRT_PROT_SEC_74 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 + +// Field: [9] WRT_PROT_SEC_73 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 + +// Field: [8] WRT_PROT_SEC_72 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 + +// Field: [7] WRT_PROT_SEC_71 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 + +// Field: [6] WRT_PROT_SEC_70 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 + +// Field: [5] WRT_PROT_SEC_69 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 + +// Field: [4] WRT_PROT_SEC_68 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 + +// Field: [3] WRT_PROT_SEC_67 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 + +// Field: [2] WRT_PROT_SEC_66 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 + +// Field: [1] WRT_PROT_SEC_65 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 + +// Field: [0] WRT_PROT_SEC_64 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_127_96 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_127 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 + +// Field: [30] WRT_PROT_SEC_126 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 + +// Field: [29] WRT_PROT_SEC_125 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 + +// Field: [28] WRT_PROT_SEC_124 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 + +// Field: [27] WRT_PROT_SEC_123 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 + +// Field: [26] WRT_PROT_SEC_122 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 + +// Field: [25] WRT_PROT_SEC_121 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 + +// Field: [24] WRT_PROT_SEC_120 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 + +// Field: [23] WRT_PROT_SEC_119 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 + +// Field: [22] WRT_PROT_SEC_118 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 + +// Field: [21] WRT_PROT_SEC_117 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 + +// Field: [20] WRT_PROT_SEC_116 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 + +// Field: [19] WRT_PROT_SEC_115 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 + +// Field: [18] WRT_PROT_SEC_114 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 + +// Field: [17] WRT_PROT_SEC_113 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 + +// Field: [16] WRT_PROT_SEC_112 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 + +// Field: [15] WRT_PROT_SEC_111 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 + +// Field: [14] WRT_PROT_SEC_110 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 + +// Field: [13] WRT_PROT_SEC_109 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 + +// Field: [12] WRT_PROT_SEC_108 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 + +// Field: [11] WRT_PROT_SEC_107 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 + +// Field: [10] WRT_PROT_SEC_106 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 + +// Field: [9] WRT_PROT_SEC_105 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 + +// Field: [8] WRT_PROT_SEC_104 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 + +// Field: [7] WRT_PROT_SEC_103 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 + +// Field: [6] WRT_PROT_SEC_102 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 + +// Field: [5] WRT_PROT_SEC_101 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 + +// Field: [4] WRT_PROT_SEC_100 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 + +// Field: [3] WRT_PROT_SEC_99 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 + +// Field: [2] WRT_PROT_SEC_98 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 + +// Field: [1] WRT_PROT_SEC_97 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 + +// Field: [0] WRT_PROT_SEC_96 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 + + +#endif // __CCFG__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg_simple_struct.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg_simple_struct.h new file mode 100644 index 0000000..12cfc01 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg_simple_struct.h @@ -0,0 +1,81 @@ +/****************************************************************************** +* Filename: hw_ccfg_simple_struct_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CCFG_SIMPLE_STRUCT_H__ +#define __HW_CCFG_SIMPLE_STRUCT_H__ + +//***************************************************************************** +// +// Customer configuration (ccfg) typedef. +// The implementation of this struct is required by device ROM boot code +// and must be placed at the end of flash. Do not modify this struct! +// +//***************************************************************************** +typedef struct +{ // Mapped to address + uint32_t CCFG_EXT_LF_CLK ; // 0x50003FA8 + uint32_t CCFG_MODE_CONF_1 ; // 0x50003FAC + uint32_t CCFG_SIZE_AND_DIS_FLAGS ; // 0x50003FB0 + uint32_t CCFG_MODE_CONF ; // 0x50003FB4 + uint32_t CCFG_VOLT_LOAD_0 ; // 0x50003FB8 + uint32_t CCFG_VOLT_LOAD_1 ; // 0x50003FBC + uint32_t CCFG_RTC_OFFSET ; // 0x50003FC0 + uint32_t CCFG_FREQ_OFFSET ; // 0x50003FC4 + uint32_t CCFG_IEEE_MAC_0 ; // 0x50003FC8 + uint32_t CCFG_IEEE_MAC_1 ; // 0x50003FCC + uint32_t CCFG_IEEE_BLE_0 ; // 0x50003FD0 + uint32_t CCFG_IEEE_BLE_1 ; // 0x50003FD4 + uint32_t CCFG_BL_CONFIG ; // 0x50003FD8 + uint32_t CCFG_ERASE_CONF ; // 0x50003FDC + uint32_t CCFG_CCFG_TI_OPTIONS ; // 0x50003FE0 + uint32_t CCFG_CCFG_TAP_DAP_0 ; // 0x50003FE4 + uint32_t CCFG_CCFG_TAP_DAP_1 ; // 0x50003FE8 + uint32_t CCFG_IMAGE_VALID_CONF ; // 0x50003FEC + uint32_t CCFG_CCFG_PROT_31_0 ; // 0x50003FF0 + uint32_t CCFG_CCFG_PROT_63_32 ; // 0x50003FF4 + uint32_t CCFG_CCFG_PROT_95_64 ; // 0x50003FF8 + uint32_t CCFG_CCFG_PROT_127_96 ; // 0x50003FFC +} ccfg_t; + +//***************************************************************************** +// +// Define the extern ccfg structure (__ccfg) +// +//***************************************************************************** +extern const ccfg_t __ccfg; + + +#endif // __HW_CCFG_SIMPLE_STRUCT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_chip_def.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_chip_def.h new file mode 100644 index 0000000..6bc9c99 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_chip_def.h @@ -0,0 +1,237 @@ +/****************************************************************************** +* Filename: hw_chip_def.h +* Revised: 2017-06-26 09:33:33 +0200 (Mon, 26 Jun 2017) +* Revision: 49227 +* +* Description: Defines for device properties. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup config_api +//! @{ +// +//***************************************************************************** + +#ifndef __HW_CHIP_DEF_H__ +#define __HW_CHIP_DEF_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Define CC_CHIP_ID code used in the following macros defined at the bottom: +// CC_GET_CHIP_FAMILY/DEVICE/PACKAGE/HWREV +// +//***************************************************************************** +/* CC2620F128 */ +#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21) + #define CC_CHIP_ID 0x26200720 +#elif defined(CC2620F128RHB_R20) || defined(CC2620F128RHB_R21) + #define CC_CHIP_ID 0x26200520 +#elif defined(CC2620F128RSM_R20) || defined(CC2620F128RSM_R21) + #define CC_CHIP_ID 0x26200420 +#elif defined(CC2620F128_R20) || defined(CC2620F128_R21) + #define CC_CHIP_ID 0x26200020 +#elif defined(CC2620F128RGZ_R22) || defined(CC2620F128RGZ) + #define CC_CHIP_ID 0x26200722 +#elif defined(CC2620F128RHB_R22) || defined(CC2620F128RHB) + #define CC_CHIP_ID 0x26200522 +#elif defined(CC2620F128RSM_R22) || defined(CC2620F128RSM) + #define CC_CHIP_ID 0x26200422 +#elif defined(CC2620F128_R22) || defined(CC2620F128) + #define CC_CHIP_ID 0x26200022 +/* CC2630F128 */ +#elif defined(CC2630F128RGZ_R20) || defined(CC2630F128RGZ_R21) + #define CC_CHIP_ID 0x26300720 +#elif defined(CC2630F128RHB_R20) || defined(CC2630F128RHB_R21) + #define CC_CHIP_ID 0x26300520 +#elif defined(CC2630F128RSM_R20) || defined(CC2630F128RSM_R21) + #define CC_CHIP_ID 0x26300420 +#elif defined(CC2630F128_R20) || defined(CC2630F128_R21) + #define CC_CHIP_ID 0x26300020 +#elif defined(CC2630F128RGZ_R22) || defined(CC2630F128RGZ) + #define CC_CHIP_ID 0x26300722 +#elif defined(CC2630F128RHB_R22) || defined(CC2630F128RHB) + #define CC_CHIP_ID 0x26300522 +#elif defined(CC2630F128RSM_R22) || defined(CC2630F128RSM) + #define CC_CHIP_ID 0x26300422 +#elif defined(CC2630F128_R22) || defined(CC2630F128) + #define CC_CHIP_ID 0x26300022 +/* CC2640F128 */ +#elif defined(CC2640F128RGZ_R20) || defined(CC2640F128RGZ_R21) + #define CC_CHIP_ID 0x26400720 +#elif defined(CC2640F128RHB_R20) || defined(CC2640F128RHB_R21) + #define CC_CHIP_ID 0x26400520 +#elif defined(CC2640F128RSM_R20) || defined(CC2640F128RSM_R21) + #define CC_CHIP_ID 0x26400420 +#elif defined(CC2640F128_R20) || defined(CC2640F128_R21) + #define CC_CHIP_ID 0x26400020 +#elif defined(CC2640F128RGZ_R22) || defined(CC2640F128RGZ) + #define CC_CHIP_ID 0x26400722 +#elif defined(CC2640F128RHB_R22) || defined(CC2640F128RHB) + #define CC_CHIP_ID 0x26400522 +#elif defined(CC2640F128RSM_R22) || defined(CC2640F128RSM) + #define CC_CHIP_ID 0x26400422 +#elif defined(CC2640F128_R22) || defined(CC2640F128) + #define CC_CHIP_ID 0x26400022 +/* CC2650F128 */ +#elif defined(CC2650F128RGZ_R20) || defined(CC2650F128RGZ_R21) + #define CC_CHIP_ID 0x26500720 +#elif defined(CC2650F128RHB_R20) || defined(CC2650F128RHB_R21) + #define CC_CHIP_ID 0x26500520 +#elif defined(CC2650F128RSM_R20) || defined(CC2650F128RSM_R21) + #define CC_CHIP_ID 0x26500420 +#elif defined(CC2650F128_R20) || defined(CC2650F128_R21) + #define CC_CHIP_ID 0x26500020 +#elif defined(CC2650F128RGZ_R22) || defined(CC2650F128RGZ) + #define CC_CHIP_ID 0x26500722 +#elif defined(CC2650F128RHB_R22) || defined(CC2650F128RHB) + #define CC_CHIP_ID 0x26500522 +#elif defined(CC2650F128RSM_R22) || defined(CC2650F128RSM) + #define CC_CHIP_ID 0x26500422 +#elif defined(CC2650F128_R22) || defined(CC2650F128) + #define CC_CHIP_ID 0x26500022 +/* CC2650L128 (OTP) */ +#elif defined(CC2650L128) + #define CC_CHIP_ID 0x26501710 +/* CC1310F128 */ +#elif defined(CC1310F128RGZ_R20) || defined(CC1310F128RGZ) + #define CC_CHIP_ID 0x13100720 +#elif defined(CC1310F128RHB_R20) || defined(CC1310F128RHB) + #define CC_CHIP_ID 0x13100520 +#elif defined(CC1310F128RSM_R20) || defined(CC1310F128RSM) + #define CC_CHIP_ID 0x13100420 +#elif defined(CC1310F128_R20) || defined(CC1310F128) + #define CC_CHIP_ID 0x13100020 +/* CC1350F128 */ +#elif defined(CC1350F128RGZ_R20) || defined(CC1350F128RGZ) + #define CC_CHIP_ID 0x13500720 +#elif defined(CC1350F128RHB_R20) || defined(CC1350F128RHB) + #define CC_CHIP_ID 0x13500520 +#elif defined(CC1350F128RSM_R20) || defined(CC1350F128RSM) + #define CC_CHIP_ID 0x13500420 +#elif defined(CC1350F128_R20) || defined(CC1350F128) + #define CC_CHIP_ID 0x13500020 +/* CC2640R2F */ +#elif defined(CC2640R2FRGZ_R25) || defined(CC2640R2FRGZ) + #define CC_CHIP_ID 0x26401710 +#elif defined(CC2640R2FRHB_R25) || defined(CC2640R2FRHB) + #define CC_CHIP_ID 0x26401510 +#elif defined(CC2640R2FRSM_R25) || defined(CC2640R2FRSM) + #define CC_CHIP_ID 0x26401410 +#elif defined(CC2640R2F_R25) || defined(CC2640R2F) + #define CC_CHIP_ID 0x26401010 +/* CC2652R1F */ +#elif defined(CC2652R1FRGZ_R10) || defined(CC2652R1FRGZ) + #define CC_CHIP_ID 0x26523710 +#elif defined(CC2652R1F_R10) || defined(CC2652R1F) + #define CC_CHIP_ID 0x26523010 +/* CC2644R1F */ +#elif defined(CC2644R1FRGZ_R10) || defined(CC2644R1FRGZ) + #define CC_CHIP_ID 0x26443710 +#elif defined(CC2644R1F_R10) || defined(CC2644R1F) + #define CC_CHIP_ID 0x26443010 +/* CC2642R1F */ +#elif defined(CC2642R1FRGZ_R10) || defined(CC2642R1FRGZ) + #define CC_CHIP_ID 0x26423710 +#elif defined(CC2642R1F_R10) || defined(CC2642R1F) + #define CC_CHIP_ID 0x26423010 +/* CC1354R1F */ +#elif defined(CC1354R1FRGZ_R10) || defined(CC1354R1FRGZ) + #define CC_CHIP_ID 0x13543710 +#elif defined(CC1354R1F_R10) || defined(CC1354R1F) + #define CC_CHIP_ID 0x13543010 +/* CC1352R1F */ +#elif defined(CC1352R1FRGZ_R10) || defined(CC1352R1FRGZ) + #define CC_CHIP_ID 0x13523710 +#elif defined(CC1352R1F_R10) || defined(CC1352R1F) + #define CC_CHIP_ID 0x13523010 +/* CC1312R1F */ +#elif defined(CC1312R1FRGZ_R10) || defined(CC1312R1FRGZ) + #define CC_CHIP_ID 0x13123710 +#elif defined(CC1312R1F_R10) || defined(CC1312R1F) + #define CC_CHIP_ID 0x13123010 +#endif + +#define CC_GET_CHIP_FAMILY 0x26 +#define CC_GET_CHIP_OPTION 0x0 +#define CC_GET_CHIP_HWREV 0x22 + +#ifdef CC_CHIP_ID + /* Define chip package only if specified */ + #if (CC_CHIP_ID & 0x00000F00) != 0 + #define CC_GET_CHIP_PACKAGE (((CC_CHIP_ID) & 0x00000F00) >> 8) + #endif + + /* Define chip device */ + #define CC_GET_CHIP_DEVICE (((CC_CHIP_ID) & 0xFFFF0000) >> 16) + + /* The chip family, option and package shall match the DriverLib release */ + #if (CC_GET_CHIP_FAMILY != ((CC_CHIP_ID & 0xFF000000) >> 24)) + #error "Specified chip family does not match DriverLib release" + #endif + #if (CC_GET_CHIP_OPTION != ((CC_CHIP_ID & 0x0000F000) >> 12)) + #error "Specified chip option does not match DriverLib release" + #endif + #if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0)) + #error "Specified chip hardware revision does not match DriverLib release" + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __HW_CHIP_DEF_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_dwt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_dwt.h new file mode 100644 index 0000000..1721748 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_dwt.h @@ -0,0 +1,856 @@ +/****************************************************************************** +* Filename: hw_cpu_dwt_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_DWT_H__ +#define __HW_CPU_DWT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_DWT component +// +//***************************************************************************** +// Control +#define CPU_DWT_O_CTRL 0x00000000 + +// Current PC Sampler Cycle Count +#define CPU_DWT_O_CYCCNT 0x00000004 + +// CPI Count +#define CPU_DWT_O_CPICNT 0x00000008 + +// Exception Overhead Count +#define CPU_DWT_O_EXCCNT 0x0000000C + +// Sleep Count +#define CPU_DWT_O_SLEEPCNT 0x00000010 + +// LSU Count +#define CPU_DWT_O_LSUCNT 0x00000014 + +// Fold Count +#define CPU_DWT_O_FOLDCNT 0x00000018 + +// Program Counter Sample +#define CPU_DWT_O_PCSR 0x0000001C + +// Comparator 0 +#define CPU_DWT_O_COMP0 0x00000020 + +// Mask 0 +#define CPU_DWT_O_MASK0 0x00000024 + +// Function 0 +#define CPU_DWT_O_FUNCTION0 0x00000028 + +// Comparator 1 +#define CPU_DWT_O_COMP1 0x00000030 + +// Mask 1 +#define CPU_DWT_O_MASK1 0x00000034 + +// Function 1 +#define CPU_DWT_O_FUNCTION1 0x00000038 + +// Comparator 2 +#define CPU_DWT_O_COMP2 0x00000040 + +// Mask 2 +#define CPU_DWT_O_MASK2 0x00000044 + +// Function 2 +#define CPU_DWT_O_FUNCTION2 0x00000048 + +// Comparator 3 +#define CPU_DWT_O_COMP3 0x00000050 + +// Mask 3 +#define CPU_DWT_O_MASK3 0x00000054 + +// Function 3 +#define CPU_DWT_O_FUNCTION3 0x00000058 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CTRL +// +//***************************************************************************** +// Field: [25] NOCYCCNT +// +// When set, CYCCNT is not supported. +#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 +#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_S 25 + +// Field: [24] NOPRFCNT +// +// When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. +#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 +#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_S 24 + +// Field: [22] CYCEVTENA +// +// Enables Cycle count event. Emits an event when the POSTCNT counter triggers +// it. See CYCTAP and POSTPRESET for details. This event is only emitted if +// PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. +// +// 0: Cycle count events disabled +// 1: Cycle count events enabled +#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 +#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_S 22 + +// Field: [21] FOLDEVTENA +// +// Enables Folded instruction count event. Emits an event when FOLDCNT +// overflows (every 256 cycles of folded instructions). A folded instruction is +// one that does not incur even one cycle to execute. For example, an IT +// instruction is folded away and so does not use up one cycle. +// +// 0: Folded instruction count events disabled. +// 1: Folded instruction count events enabled. +#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 +#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_S 21 + +// Field: [20] LSUEVTENA +// +// Enables LSU count event. Emits an event when LSUCNT overflows (every 256 +// cycles of LSU operation). LSU counts include all LSU costs after the initial +// cycle for the instruction. +// +// 0: LSU count events disabled. +// 1: LSU count events enabled. +#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 +#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_S 20 + +// Field: [19] SLEEPEVTENA +// +// Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 +// cycles that the processor is sleeping). +// +// 0: Sleep count events disabled. +// 1: Sleep count events enabled. +#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 +#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 + +// Field: [18] EXCEVTENA +// +// Enables Interrupt overhead event. Emits an event when EXCCNT overflows +// (every 256 cycles of interrupt overhead). +// +// 0x0: Interrupt overhead event disabled. +// 0x1: Interrupt overhead event enabled. +#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 +#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_S 18 + +// Field: [17] CPIEVTENA +// +// Enables CPI count event. Emits an event when CPICNT overflows (every 256 +// cycles of multi-cycle instructions). +// +// 0: CPI counter events disabled. +// 1: CPI counter events enabled. +#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 +#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_S 17 + +// Field: [16] EXCTRCENA +// +// Enables Interrupt event tracing. +// +// 0: Interrupt event trace disabled. +// 1: Interrupt event trace enabled. +#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 +#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_S 16 + +// Field: [12] PCSAMPLEENA +// +// Enables PC Sampling event. A PC sample event is emitted when the POSTCNT +// counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this +// bit overrides CYCEVTENA. +// +// 0: PC Sampling event disabled. +// 1: Sampling event enabled. +#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 +#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 + +// Field: [11:10] SYNCTAP +// +// Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA +// must also be enabled for this feature. +// Synchronization packets (if enabled) are generated on tap transitions (0 to1 +// or 1 to 0). +// ENUMs: +// BIT28 Tap at bit 28 of CYCCNT +// BIT26 Tap at bit 26 of CYCCNT +// BIT24 Tap at bit 24 of CYCCNT +// DIS Disabled. No synchronization packets +#define CPU_DWT_CTRL_SYNCTAP_W 2 +#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_S 10 +#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 +#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 +#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 + +// Field: [9] CYCTAP +// +// Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the +// selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the +// POSTCNT, post-scalar counter. That counter then counts down. On a bit change +// when post-scalar is 0, it triggers an event for PC sampling or cycle count +// event (see details in CYCEVTENA). +// ENUMs: +// BIT10 Selects bit [10] to tap +// BIT6 Selects bit [6] to tap +#define CPU_DWT_CTRL_CYCTAP 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BITN 9 +#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_S 9 +#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 + +// Field: [8:5] POSTCNT +// +// Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 +// to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it +// triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the +// value from POSTPRESET. +#define CPU_DWT_CTRL_POSTCNT_W 4 +#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 +#define CPU_DWT_CTRL_POSTCNT_S 5 + +// Field: [4:1] POSTPRESET +// +// Reload value for post-scalar counter POSTCNT. When 0, events are triggered +// on each tap change (a power of 2). If this field has a non-0 value, it forms +// a count-down value, to be reloaded into POSTCNT each time it reaches 0. For +// example, a value 1 in this register means an event is formed every other tap +// change. +#define CPU_DWT_CTRL_POSTPRESET_W 4 +#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E +#define CPU_DWT_CTRL_POSTPRESET_S 1 + +// Field: [0] CYCCNTENA +// +// Enable CYCCNT, allowing it to increment and generate synchronization and +// count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. +#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 +#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CYCCNT +// +//***************************************************************************** +// Field: [31:0] CYCCNT +// +// Current PC Sampler Cycle Counter count value. When enabled, this counter +// counts the number of core cycles, except when the core is halted. The cycle +// counter is a free running counter, counting upwards (this counter will not +// advance in power modes where free-running clock to CPU stops). It wraps +// around to 0 on overflow. The debugger must initialize this to 0 when first +// enabling. +#define CPU_DWT_CYCCNT_CYCCNT_W 32 +#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF +#define CPU_DWT_CYCCNT_CYCCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CPICNT +// +//***************************************************************************** +// Field: [7:0] CPICNT +// +// Current CPI counter value. Increments on the additional cycles (the first +// cycle is not counted) required to execute all instructions except those +// recorded by LSUCNT. This counter also increments on all instruction fetch +// stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter +// overflows. This counter initializes to 0 when it is enabled using +// CTRL.CPIEVTENA. +#define CPU_DWT_CPICNT_CPICNT_W 8 +#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF +#define CPU_DWT_CPICNT_CPICNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_EXCCNT +// +//***************************************************************************** +// Field: [7:0] EXCCNT +// +// Current interrupt overhead counter value. Counts the total cycles spent in +// interrupt processing (for example entry stacking, return unstacking, +// pre-emption). An event is emitted on counter overflow (every 256 cycles). +// This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. +#define CPU_DWT_EXCCNT_EXCCNT_W 8 +#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF +#define CPU_DWT_EXCCNT_EXCCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_SLEEPCNT +// +//***************************************************************************** +// Field: [7:0] SLEEPCNT +// +// Sleep counter. Counts the number of cycles during which the processor is +// sleeping. An event is emitted on counter overflow (every 256 cycles). This +// counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note +// that the sleep counter is clocked using CPU's free-running clock. In some +// power modes the free-running clock to CPU is gated to minimize power +// consumption. This means that the sleep counter will be invalid in these +// power modes. +#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 +#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF +#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_LSUCNT +// +//***************************************************************************** +// Field: [7:0] LSUCNT +// +// LSU counter. This counts the total number of cycles that the processor is +// processing an LSU operation. The initial execution cost of the instruction +// is not counted. For example, an LDR that takes two cycles to complete +// increments this counter one cycle. Equivalently, an LDR that stalls for two +// cycles (i.e. takes four cycles to execute), increments this counter three +// times. An event is emitted on counter overflow (every 256 cycles). This +// counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. +#define CPU_DWT_LSUCNT_LSUCNT_W 8 +#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF +#define CPU_DWT_LSUCNT_LSUCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FOLDCNT +// +//***************************************************************************** +// Field: [7:0] FOLDCNT +// +// This counts the total number folded instructions. This counter initializes +// to 0 when it is enabled using CTRL.FOLDEVTENA. +#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 +#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF +#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_PCSR +// +//***************************************************************************** +// Field: [31:0] EIASAMPLE +// +// Execution instruction address sample, or 0xFFFFFFFF if the core is halted. +#define CPU_DWT_PCSR_EIASAMPLE_W 32 +#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF +#define CPU_DWT_PCSR_EIASAMPLE_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP0 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler +// Counter (CYCCNT). +#define CPU_DWT_COMP0_COMP_W 32 +#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP0_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK0 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP0. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP0. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK0_MASK_W 4 +#define CPU_DWT_MASK0_MASK_M 0x0000000F +#define CPU_DWT_MASK0_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION0 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_S 24 + +// Field: [7] CYCMATCH +// +// This bit is only available in comparator 0. When set, COMP0 will compare +// against the cycle counter (CYCCNT). +#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 +#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION0_FUNCTION_W 4 +#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION0_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP1 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION1. +// Comparator 1 can also compare data values. So this register can contain +// reference values for data matching. +#define CPU_DWT_COMP1_COMP_W 32 +#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP1_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK1 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP1. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP1. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK1_MASK_W 4 +#define CPU_DWT_MASK1_MASK_M 0x0000000F +#define CPU_DWT_MASK1_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION1 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_S 24 + +// Field: [19:16] DATAVADDR1 +// +// Identity of a second linked address comparator for data value matching when +// DATAVMATCH == 1 and LNK1ENA == 1. +#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 +#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 + +// Field: [15:12] DATAVADDR0 +// +// Identity of a linked address comparator for data value matching when +// DATAVMATCH == 1. +#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 +#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 + +// Field: [11:10] DATAVSIZE +// +// Defines the size of the data in the COMP1 register that is to be matched: +// +// 0x0: Byte +// 0x1: Halfword +// 0x2: Word +// 0x3: Unpredictable. +#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 +#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 +#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 + +// Field: [9] LNK1ENA +// +// Read only bit-field only supported in comparator 1. +// +// 0: DATAVADDR1 not supported +// 1: DATAVADDR1 supported (enabled) +#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 +#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 + +// Field: [8] DATAVMATCH +// +// Data match feature: +// +// 0: Perform address comparison +// 1: Perform data value compare. The comparators given by DATAVADDR0 and +// DATAVADDR1 provide the address for the data comparison. The FUNCTION setting +// for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and +// those comparators only provide the address match for the data comparison. +// +// This bit is only available in comparator 1. +#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 +#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings: +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and +// DATAVADDR1 if DATAVMATCH is also set. The comparators given by DATAVADDR0 +// and DATAVADDR1 can then only perform address comparator matches for +// comparator 1 data matches. +// Note 4: If the data matching functionality is not included during +// implementation it is not possible to set DATAVADDR0, DATAVADDR1, or +// DATAVMATCH. This means that the data matching functionality is not available +// in the implementation. Test the availability of data matching by writing and +// reading DATAVMATCH. If it is not settable then data matching is unavailable. +// Note 5: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION1_FUNCTION_W 4 +#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION1_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP2 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION2. +#define CPU_DWT_COMP2_COMP_W 32 +#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP2_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK2 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP2. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP2. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK2_MASK_W 4 +#define CPU_DWT_MASK2_MASK_M 0x0000000F +#define CPU_DWT_MASK2_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION2 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_S 24 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION2_FUNCTION_W 4 +#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION2_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP3 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION3. +#define CPU_DWT_COMP3_COMP_W 32 +#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP3_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK3 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP3. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP3. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK3_MASK_W 4 +#define CPU_DWT_MASK3_MASK_M 0x0000000F +#define CPU_DWT_MASK3_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION3 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_S 24 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION3_FUNCTION_W 4 +#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION3_FUNCTION_S 0 + + +#endif // __CPU_DWT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_fpb.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_fpb.h new file mode 100644 index 0000000..f70d8bd --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_fpb.h @@ -0,0 +1,443 @@ +/****************************************************************************** +* Filename: hw_cpu_fpb_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_FPB_H__ +#define __HW_CPU_FPB_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_FPB component +// +//***************************************************************************** +// Control +#define CPU_FPB_O_CTRL 0x00000000 + +// Remap +#define CPU_FPB_O_REMAP 0x00000004 + +// Comparator 0 +#define CPU_FPB_O_COMP0 0x00000008 + +// Comparator 1 +#define CPU_FPB_O_COMP1 0x0000000C + +// Comparator 2 +#define CPU_FPB_O_COMP2 0x00000010 + +// Comparator 3 +#define CPU_FPB_O_COMP3 0x00000014 + +// Comparator 4 +#define CPU_FPB_O_COMP4 0x00000018 + +// Comparator 5 +#define CPU_FPB_O_COMP5 0x0000001C + +// Comparator 6 +#define CPU_FPB_O_COMP6 0x00000020 + +// Comparator 7 +#define CPU_FPB_O_COMP7 0x00000024 + +//***************************************************************************** +// +// Register: CPU_FPB_O_CTRL +// +//***************************************************************************** +// Field: [13:12] NUM_CODE2 +// +// Number of full banks of code comparators, sixteen comparators per bank. +// Where less than sixteen code comparators are provided, the bank count is +// zero, and the number present indicated by NUM_CODE1. This read only field +// contains 3'b000 to indicate 0 banks for Cortex-M processor. +#define CPU_FPB_CTRL_NUM_CODE2_W 2 +#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 +#define CPU_FPB_CTRL_NUM_CODE2_S 12 + +// Field: [11:8] NUM_LIT +// +// Number of literal slots field. +// +// 0x0: No literal slots +// 0x2: Two literal slots +#define CPU_FPB_CTRL_NUM_LIT_W 4 +#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 +#define CPU_FPB_CTRL_NUM_LIT_S 8 + +// Field: [7:4] NUM_CODE1 +// +// Number of code slots field. +// +// 0x0: No code slots +// 0x2: Two code slots +// 0x6: Six code slots +#define CPU_FPB_CTRL_NUM_CODE1_W 4 +#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 +#define CPU_FPB_CTRL_NUM_CODE1_S 4 + +// Field: [1] KEY +// +// Key field. In order to write to this register, this bit-field must be +// written to '1'. This bit always reads 0. +#define CPU_FPB_CTRL_KEY 0x00000002 +#define CPU_FPB_CTRL_KEY_BITN 1 +#define CPU_FPB_CTRL_KEY_M 0x00000002 +#define CPU_FPB_CTRL_KEY_S 1 + +// Field: [0] ENABLE +// +// Flash patch unit enable bit +// +// 0x0: Flash patch unit disabled +// 0x1: Flash patch unit enabled +#define CPU_FPB_CTRL_ENABLE 0x00000001 +#define CPU_FPB_CTRL_ENABLE_BITN 0 +#define CPU_FPB_CTRL_ENABLE_M 0x00000001 +#define CPU_FPB_CTRL_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_REMAP +// +//***************************************************************************** +// Field: [28:5] REMAP +// +// Remap base address field. +#define CPU_FPB_REMAP_REMAP_W 24 +#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 +#define CPU_FPB_REMAP_REMAP_S 5 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP0 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP0_REPLACE_W 2 +#define CPU_FPB_COMP0_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP0_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP0_COMP_W 27 +#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP0_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 0. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 0 disabled +// 0x1: Compare and remap for comparator 0 enabled +#define CPU_FPB_COMP0_ENABLE 0x00000001 +#define CPU_FPB_COMP0_ENABLE_BITN 0 +#define CPU_FPB_COMP0_ENABLE_M 0x00000001 +#define CPU_FPB_COMP0_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP1 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP1_REPLACE_W 2 +#define CPU_FPB_COMP1_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP1_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP1_COMP_W 27 +#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP1_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 1. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 1 disabled +// 0x1: Compare and remap for comparator 1 enabled +#define CPU_FPB_COMP1_ENABLE 0x00000001 +#define CPU_FPB_COMP1_ENABLE_BITN 0 +#define CPU_FPB_COMP1_ENABLE_M 0x00000001 +#define CPU_FPB_COMP1_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP2 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP2_REPLACE_W 2 +#define CPU_FPB_COMP2_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP2_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP2_COMP_W 27 +#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP2_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 2. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 2 disabled +// 0x1: Compare and remap for comparator 2 enabled +#define CPU_FPB_COMP2_ENABLE 0x00000001 +#define CPU_FPB_COMP2_ENABLE_BITN 0 +#define CPU_FPB_COMP2_ENABLE_M 0x00000001 +#define CPU_FPB_COMP2_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP3 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP3_REPLACE_W 2 +#define CPU_FPB_COMP3_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP3_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP3_COMP_W 27 +#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP3_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 3. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 3 disabled +// 0x1: Compare and remap for comparator 3 enabled +#define CPU_FPB_COMP3_ENABLE 0x00000001 +#define CPU_FPB_COMP3_ENABLE_BITN 0 +#define CPU_FPB_COMP3_ENABLE_M 0x00000001 +#define CPU_FPB_COMP3_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP4 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP4_REPLACE_W 2 +#define CPU_FPB_COMP4_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP4_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP4_COMP_W 27 +#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP4_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 4. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 4 disabled +// 0x1: Compare and remap for comparator 4 enabled +#define CPU_FPB_COMP4_ENABLE 0x00000001 +#define CPU_FPB_COMP4_ENABLE_BITN 0 +#define CPU_FPB_COMP4_ENABLE_M 0x00000001 +#define CPU_FPB_COMP4_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP5 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP5_REPLACE_W 2 +#define CPU_FPB_COMP5_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP5_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP5_COMP_W 27 +#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP5_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 5. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 5 disabled +// 0x1: Compare and remap for comparator 5 enabled +#define CPU_FPB_COMP5_ENABLE 0x00000001 +#define CPU_FPB_COMP5_ENABLE_BITN 0 +#define CPU_FPB_COMP5_ENABLE_M 0x00000001 +#define CPU_FPB_COMP5_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP6 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Comparator 6 is +// a literal comparator and the only supported setting is 0x0. Other settings +// will be ignored. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP6_REPLACE_W 2 +#define CPU_FPB_COMP6_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP6_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP6_COMP_W 27 +#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP6_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 6. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 6 disabled +// 0x1: Compare and remap for comparator 6 enabled +#define CPU_FPB_COMP6_ENABLE 0x00000001 +#define CPU_FPB_COMP6_ENABLE_BITN 0 +#define CPU_FPB_COMP6_ENABLE_M 0x00000001 +#define CPU_FPB_COMP6_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP7 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Comparator 7 is +// a literal comparator and the only supported setting is 0x0. Other settings +// will be ignored. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP7_REPLACE_W 2 +#define CPU_FPB_COMP7_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP7_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP7_COMP_W 27 +#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP7_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 7. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 7 disabled +// 0x1: Compare and remap for comparator 7 enabled +#define CPU_FPB_COMP7_ENABLE 0x00000001 +#define CPU_FPB_COMP7_ENABLE_BITN 0 +#define CPU_FPB_COMP7_ENABLE_M 0x00000001 +#define CPU_FPB_COMP7_ENABLE_S 0 + + +#endif // __CPU_FPB__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_itm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_itm.h new file mode 100644 index 0000000..9996da5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_itm.h @@ -0,0 +1,1122 @@ +/****************************************************************************** +* Filename: hw_cpu_itm_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_ITM_H__ +#define __HW_CPU_ITM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_ITM component +// +//***************************************************************************** +// Stimulus Port 0 +#define CPU_ITM_O_STIM0 0x00000000 + +// Stimulus Port 1 +#define CPU_ITM_O_STIM1 0x00000004 + +// Stimulus Port 2 +#define CPU_ITM_O_STIM2 0x00000008 + +// Stimulus Port 3 +#define CPU_ITM_O_STIM3 0x0000000C + +// Stimulus Port 4 +#define CPU_ITM_O_STIM4 0x00000010 + +// Stimulus Port 5 +#define CPU_ITM_O_STIM5 0x00000014 + +// Stimulus Port 6 +#define CPU_ITM_O_STIM6 0x00000018 + +// Stimulus Port 7 +#define CPU_ITM_O_STIM7 0x0000001C + +// Stimulus Port 8 +#define CPU_ITM_O_STIM8 0x00000020 + +// Stimulus Port 9 +#define CPU_ITM_O_STIM9 0x00000024 + +// Stimulus Port 10 +#define CPU_ITM_O_STIM10 0x00000028 + +// Stimulus Port 11 +#define CPU_ITM_O_STIM11 0x0000002C + +// Stimulus Port 12 +#define CPU_ITM_O_STIM12 0x00000030 + +// Stimulus Port 13 +#define CPU_ITM_O_STIM13 0x00000034 + +// Stimulus Port 14 +#define CPU_ITM_O_STIM14 0x00000038 + +// Stimulus Port 15 +#define CPU_ITM_O_STIM15 0x0000003C + +// Stimulus Port 16 +#define CPU_ITM_O_STIM16 0x00000040 + +// Stimulus Port 17 +#define CPU_ITM_O_STIM17 0x00000044 + +// Stimulus Port 18 +#define CPU_ITM_O_STIM18 0x00000048 + +// Stimulus Port 19 +#define CPU_ITM_O_STIM19 0x0000004C + +// Stimulus Port 20 +#define CPU_ITM_O_STIM20 0x00000050 + +// Stimulus Port 21 +#define CPU_ITM_O_STIM21 0x00000054 + +// Stimulus Port 22 +#define CPU_ITM_O_STIM22 0x00000058 + +// Stimulus Port 23 +#define CPU_ITM_O_STIM23 0x0000005C + +// Stimulus Port 24 +#define CPU_ITM_O_STIM24 0x00000060 + +// Stimulus Port 25 +#define CPU_ITM_O_STIM25 0x00000064 + +// Stimulus Port 26 +#define CPU_ITM_O_STIM26 0x00000068 + +// Stimulus Port 27 +#define CPU_ITM_O_STIM27 0x0000006C + +// Stimulus Port 28 +#define CPU_ITM_O_STIM28 0x00000070 + +// Stimulus Port 29 +#define CPU_ITM_O_STIM29 0x00000074 + +// Stimulus Port 30 +#define CPU_ITM_O_STIM30 0x00000078 + +// Stimulus Port 31 +#define CPU_ITM_O_STIM31 0x0000007C + +// Trace Enable +#define CPU_ITM_O_TER 0x00000E00 + +// Trace Privilege +#define CPU_ITM_O_TPR 0x00000E40 + +// Trace Control +#define CPU_ITM_O_TCR 0x00000E80 + +// Lock Access +#define CPU_ITM_O_LAR 0x00000FB0 + +// Lock Status +#define CPU_ITM_O_LSR 0x00000FB4 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM0 +// +//***************************************************************************** +// Field: [31:0] STIM0 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM0_STIM0_W 32 +#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF +#define CPU_ITM_STIM0_STIM0_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM1 +// +//***************************************************************************** +// Field: [31:0] STIM1 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM1_STIM1_W 32 +#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF +#define CPU_ITM_STIM1_STIM1_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM2 +// +//***************************************************************************** +// Field: [31:0] STIM2 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM2_STIM2_W 32 +#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF +#define CPU_ITM_STIM2_STIM2_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM3 +// +//***************************************************************************** +// Field: [31:0] STIM3 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM3_STIM3_W 32 +#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF +#define CPU_ITM_STIM3_STIM3_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM4 +// +//***************************************************************************** +// Field: [31:0] STIM4 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM4_STIM4_W 32 +#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF +#define CPU_ITM_STIM4_STIM4_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM5 +// +//***************************************************************************** +// Field: [31:0] STIM5 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM5_STIM5_W 32 +#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF +#define CPU_ITM_STIM5_STIM5_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM6 +// +//***************************************************************************** +// Field: [31:0] STIM6 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM6_STIM6_W 32 +#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF +#define CPU_ITM_STIM6_STIM6_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM7 +// +//***************************************************************************** +// Field: [31:0] STIM7 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM7_STIM7_W 32 +#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF +#define CPU_ITM_STIM7_STIM7_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM8 +// +//***************************************************************************** +// Field: [31:0] STIM8 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM8_STIM8_W 32 +#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF +#define CPU_ITM_STIM8_STIM8_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM9 +// +//***************************************************************************** +// Field: [31:0] STIM9 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM9_STIM9_W 32 +#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF +#define CPU_ITM_STIM9_STIM9_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM10 +// +//***************************************************************************** +// Field: [31:0] STIM10 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM10_STIM10_W 32 +#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF +#define CPU_ITM_STIM10_STIM10_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM11 +// +//***************************************************************************** +// Field: [31:0] STIM11 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM11_STIM11_W 32 +#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF +#define CPU_ITM_STIM11_STIM11_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM12 +// +//***************************************************************************** +// Field: [31:0] STIM12 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM12_STIM12_W 32 +#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF +#define CPU_ITM_STIM12_STIM12_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM13 +// +//***************************************************************************** +// Field: [31:0] STIM13 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM13_STIM13_W 32 +#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF +#define CPU_ITM_STIM13_STIM13_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM14 +// +//***************************************************************************** +// Field: [31:0] STIM14 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM14_STIM14_W 32 +#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF +#define CPU_ITM_STIM14_STIM14_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM15 +// +//***************************************************************************** +// Field: [31:0] STIM15 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM15_STIM15_W 32 +#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF +#define CPU_ITM_STIM15_STIM15_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM16 +// +//***************************************************************************** +// Field: [31:0] STIM16 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM16_STIM16_W 32 +#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF +#define CPU_ITM_STIM16_STIM16_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM17 +// +//***************************************************************************** +// Field: [31:0] STIM17 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM17_STIM17_W 32 +#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF +#define CPU_ITM_STIM17_STIM17_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM18 +// +//***************************************************************************** +// Field: [31:0] STIM18 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM18_STIM18_W 32 +#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF +#define CPU_ITM_STIM18_STIM18_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM19 +// +//***************************************************************************** +// Field: [31:0] STIM19 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM19_STIM19_W 32 +#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF +#define CPU_ITM_STIM19_STIM19_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM20 +// +//***************************************************************************** +// Field: [31:0] STIM20 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM20_STIM20_W 32 +#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF +#define CPU_ITM_STIM20_STIM20_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM21 +// +//***************************************************************************** +// Field: [31:0] STIM21 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM21_STIM21_W 32 +#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF +#define CPU_ITM_STIM21_STIM21_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM22 +// +//***************************************************************************** +// Field: [31:0] STIM22 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM22_STIM22_W 32 +#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF +#define CPU_ITM_STIM22_STIM22_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM23 +// +//***************************************************************************** +// Field: [31:0] STIM23 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM23_STIM23_W 32 +#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF +#define CPU_ITM_STIM23_STIM23_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM24 +// +//***************************************************************************** +// Field: [31:0] STIM24 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM24_STIM24_W 32 +#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF +#define CPU_ITM_STIM24_STIM24_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM25 +// +//***************************************************************************** +// Field: [31:0] STIM25 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM25_STIM25_W 32 +#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF +#define CPU_ITM_STIM25_STIM25_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM26 +// +//***************************************************************************** +// Field: [31:0] STIM26 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM26_STIM26_W 32 +#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF +#define CPU_ITM_STIM26_STIM26_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM27 +// +//***************************************************************************** +// Field: [31:0] STIM27 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM27_STIM27_W 32 +#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF +#define CPU_ITM_STIM27_STIM27_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM28 +// +//***************************************************************************** +// Field: [31:0] STIM28 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM28_STIM28_W 32 +#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF +#define CPU_ITM_STIM28_STIM28_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM29 +// +//***************************************************************************** +// Field: [31:0] STIM29 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM29_STIM29_W 32 +#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF +#define CPU_ITM_STIM29_STIM29_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM30 +// +//***************************************************************************** +// Field: [31:0] STIM30 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM30_STIM30_W 32 +#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF +#define CPU_ITM_STIM30_STIM30_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM31 +// +//***************************************************************************** +// Field: [31:0] STIM31 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM31_STIM31_W 32 +#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF +#define CPU_ITM_STIM31_STIM31_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TER +// +//***************************************************************************** +// Field: [31] STIMENA31 +// +// Bit mask to enable tracing on ITM stimulus port 31. +#define CPU_ITM_TER_STIMENA31 0x80000000 +#define CPU_ITM_TER_STIMENA31_BITN 31 +#define CPU_ITM_TER_STIMENA31_M 0x80000000 +#define CPU_ITM_TER_STIMENA31_S 31 + +// Field: [30] STIMENA30 +// +// Bit mask to enable tracing on ITM stimulus port 30. +#define CPU_ITM_TER_STIMENA30 0x40000000 +#define CPU_ITM_TER_STIMENA30_BITN 30 +#define CPU_ITM_TER_STIMENA30_M 0x40000000 +#define CPU_ITM_TER_STIMENA30_S 30 + +// Field: [29] STIMENA29 +// +// Bit mask to enable tracing on ITM stimulus port 29. +#define CPU_ITM_TER_STIMENA29 0x20000000 +#define CPU_ITM_TER_STIMENA29_BITN 29 +#define CPU_ITM_TER_STIMENA29_M 0x20000000 +#define CPU_ITM_TER_STIMENA29_S 29 + +// Field: [28] STIMENA28 +// +// Bit mask to enable tracing on ITM stimulus port 28. +#define CPU_ITM_TER_STIMENA28 0x10000000 +#define CPU_ITM_TER_STIMENA28_BITN 28 +#define CPU_ITM_TER_STIMENA28_M 0x10000000 +#define CPU_ITM_TER_STIMENA28_S 28 + +// Field: [27] STIMENA27 +// +// Bit mask to enable tracing on ITM stimulus port 27. +#define CPU_ITM_TER_STIMENA27 0x08000000 +#define CPU_ITM_TER_STIMENA27_BITN 27 +#define CPU_ITM_TER_STIMENA27_M 0x08000000 +#define CPU_ITM_TER_STIMENA27_S 27 + +// Field: [26] STIMENA26 +// +// Bit mask to enable tracing on ITM stimulus port 26. +#define CPU_ITM_TER_STIMENA26 0x04000000 +#define CPU_ITM_TER_STIMENA26_BITN 26 +#define CPU_ITM_TER_STIMENA26_M 0x04000000 +#define CPU_ITM_TER_STIMENA26_S 26 + +// Field: [25] STIMENA25 +// +// Bit mask to enable tracing on ITM stimulus port 25. +#define CPU_ITM_TER_STIMENA25 0x02000000 +#define CPU_ITM_TER_STIMENA25_BITN 25 +#define CPU_ITM_TER_STIMENA25_M 0x02000000 +#define CPU_ITM_TER_STIMENA25_S 25 + +// Field: [24] STIMENA24 +// +// Bit mask to enable tracing on ITM stimulus port 24. +#define CPU_ITM_TER_STIMENA24 0x01000000 +#define CPU_ITM_TER_STIMENA24_BITN 24 +#define CPU_ITM_TER_STIMENA24_M 0x01000000 +#define CPU_ITM_TER_STIMENA24_S 24 + +// Field: [23] STIMENA23 +// +// Bit mask to enable tracing on ITM stimulus port 23. +#define CPU_ITM_TER_STIMENA23 0x00800000 +#define CPU_ITM_TER_STIMENA23_BITN 23 +#define CPU_ITM_TER_STIMENA23_M 0x00800000 +#define CPU_ITM_TER_STIMENA23_S 23 + +// Field: [22] STIMENA22 +// +// Bit mask to enable tracing on ITM stimulus port 22. +#define CPU_ITM_TER_STIMENA22 0x00400000 +#define CPU_ITM_TER_STIMENA22_BITN 22 +#define CPU_ITM_TER_STIMENA22_M 0x00400000 +#define CPU_ITM_TER_STIMENA22_S 22 + +// Field: [21] STIMENA21 +// +// Bit mask to enable tracing on ITM stimulus port 21. +#define CPU_ITM_TER_STIMENA21 0x00200000 +#define CPU_ITM_TER_STIMENA21_BITN 21 +#define CPU_ITM_TER_STIMENA21_M 0x00200000 +#define CPU_ITM_TER_STIMENA21_S 21 + +// Field: [20] STIMENA20 +// +// Bit mask to enable tracing on ITM stimulus port 20. +#define CPU_ITM_TER_STIMENA20 0x00100000 +#define CPU_ITM_TER_STIMENA20_BITN 20 +#define CPU_ITM_TER_STIMENA20_M 0x00100000 +#define CPU_ITM_TER_STIMENA20_S 20 + +// Field: [19] STIMENA19 +// +// Bit mask to enable tracing on ITM stimulus port 19. +#define CPU_ITM_TER_STIMENA19 0x00080000 +#define CPU_ITM_TER_STIMENA19_BITN 19 +#define CPU_ITM_TER_STIMENA19_M 0x00080000 +#define CPU_ITM_TER_STIMENA19_S 19 + +// Field: [18] STIMENA18 +// +// Bit mask to enable tracing on ITM stimulus port 18. +#define CPU_ITM_TER_STIMENA18 0x00040000 +#define CPU_ITM_TER_STIMENA18_BITN 18 +#define CPU_ITM_TER_STIMENA18_M 0x00040000 +#define CPU_ITM_TER_STIMENA18_S 18 + +// Field: [17] STIMENA17 +// +// Bit mask to enable tracing on ITM stimulus port 17. +#define CPU_ITM_TER_STIMENA17 0x00020000 +#define CPU_ITM_TER_STIMENA17_BITN 17 +#define CPU_ITM_TER_STIMENA17_M 0x00020000 +#define CPU_ITM_TER_STIMENA17_S 17 + +// Field: [16] STIMENA16 +// +// Bit mask to enable tracing on ITM stimulus port 16. +#define CPU_ITM_TER_STIMENA16 0x00010000 +#define CPU_ITM_TER_STIMENA16_BITN 16 +#define CPU_ITM_TER_STIMENA16_M 0x00010000 +#define CPU_ITM_TER_STIMENA16_S 16 + +// Field: [15] STIMENA15 +// +// Bit mask to enable tracing on ITM stimulus port 15. +#define CPU_ITM_TER_STIMENA15 0x00008000 +#define CPU_ITM_TER_STIMENA15_BITN 15 +#define CPU_ITM_TER_STIMENA15_M 0x00008000 +#define CPU_ITM_TER_STIMENA15_S 15 + +// Field: [14] STIMENA14 +// +// Bit mask to enable tracing on ITM stimulus port 14. +#define CPU_ITM_TER_STIMENA14 0x00004000 +#define CPU_ITM_TER_STIMENA14_BITN 14 +#define CPU_ITM_TER_STIMENA14_M 0x00004000 +#define CPU_ITM_TER_STIMENA14_S 14 + +// Field: [13] STIMENA13 +// +// Bit mask to enable tracing on ITM stimulus port 13. +#define CPU_ITM_TER_STIMENA13 0x00002000 +#define CPU_ITM_TER_STIMENA13_BITN 13 +#define CPU_ITM_TER_STIMENA13_M 0x00002000 +#define CPU_ITM_TER_STIMENA13_S 13 + +// Field: [12] STIMENA12 +// +// Bit mask to enable tracing on ITM stimulus port 12. +#define CPU_ITM_TER_STIMENA12 0x00001000 +#define CPU_ITM_TER_STIMENA12_BITN 12 +#define CPU_ITM_TER_STIMENA12_M 0x00001000 +#define CPU_ITM_TER_STIMENA12_S 12 + +// Field: [11] STIMENA11 +// +// Bit mask to enable tracing on ITM stimulus port 11. +#define CPU_ITM_TER_STIMENA11 0x00000800 +#define CPU_ITM_TER_STIMENA11_BITN 11 +#define CPU_ITM_TER_STIMENA11_M 0x00000800 +#define CPU_ITM_TER_STIMENA11_S 11 + +// Field: [10] STIMENA10 +// +// Bit mask to enable tracing on ITM stimulus port 10. +#define CPU_ITM_TER_STIMENA10 0x00000400 +#define CPU_ITM_TER_STIMENA10_BITN 10 +#define CPU_ITM_TER_STIMENA10_M 0x00000400 +#define CPU_ITM_TER_STIMENA10_S 10 + +// Field: [9] STIMENA9 +// +// Bit mask to enable tracing on ITM stimulus port 9. +#define CPU_ITM_TER_STIMENA9 0x00000200 +#define CPU_ITM_TER_STIMENA9_BITN 9 +#define CPU_ITM_TER_STIMENA9_M 0x00000200 +#define CPU_ITM_TER_STIMENA9_S 9 + +// Field: [8] STIMENA8 +// +// Bit mask to enable tracing on ITM stimulus port 8. +#define CPU_ITM_TER_STIMENA8 0x00000100 +#define CPU_ITM_TER_STIMENA8_BITN 8 +#define CPU_ITM_TER_STIMENA8_M 0x00000100 +#define CPU_ITM_TER_STIMENA8_S 8 + +// Field: [7] STIMENA7 +// +// Bit mask to enable tracing on ITM stimulus port 7. +#define CPU_ITM_TER_STIMENA7 0x00000080 +#define CPU_ITM_TER_STIMENA7_BITN 7 +#define CPU_ITM_TER_STIMENA7_M 0x00000080 +#define CPU_ITM_TER_STIMENA7_S 7 + +// Field: [6] STIMENA6 +// +// Bit mask to enable tracing on ITM stimulus port 6. +#define CPU_ITM_TER_STIMENA6 0x00000040 +#define CPU_ITM_TER_STIMENA6_BITN 6 +#define CPU_ITM_TER_STIMENA6_M 0x00000040 +#define CPU_ITM_TER_STIMENA6_S 6 + +// Field: [5] STIMENA5 +// +// Bit mask to enable tracing on ITM stimulus port 5. +#define CPU_ITM_TER_STIMENA5 0x00000020 +#define CPU_ITM_TER_STIMENA5_BITN 5 +#define CPU_ITM_TER_STIMENA5_M 0x00000020 +#define CPU_ITM_TER_STIMENA5_S 5 + +// Field: [4] STIMENA4 +// +// Bit mask to enable tracing on ITM stimulus port 4. +#define CPU_ITM_TER_STIMENA4 0x00000010 +#define CPU_ITM_TER_STIMENA4_BITN 4 +#define CPU_ITM_TER_STIMENA4_M 0x00000010 +#define CPU_ITM_TER_STIMENA4_S 4 + +// Field: [3] STIMENA3 +// +// Bit mask to enable tracing on ITM stimulus port 3. +#define CPU_ITM_TER_STIMENA3 0x00000008 +#define CPU_ITM_TER_STIMENA3_BITN 3 +#define CPU_ITM_TER_STIMENA3_M 0x00000008 +#define CPU_ITM_TER_STIMENA3_S 3 + +// Field: [2] STIMENA2 +// +// Bit mask to enable tracing on ITM stimulus port 2. +#define CPU_ITM_TER_STIMENA2 0x00000004 +#define CPU_ITM_TER_STIMENA2_BITN 2 +#define CPU_ITM_TER_STIMENA2_M 0x00000004 +#define CPU_ITM_TER_STIMENA2_S 2 + +// Field: [1] STIMENA1 +// +// Bit mask to enable tracing on ITM stimulus port 1. +#define CPU_ITM_TER_STIMENA1 0x00000002 +#define CPU_ITM_TER_STIMENA1_BITN 1 +#define CPU_ITM_TER_STIMENA1_M 0x00000002 +#define CPU_ITM_TER_STIMENA1_S 1 + +// Field: [0] STIMENA0 +// +// Bit mask to enable tracing on ITM stimulus port 0. +#define CPU_ITM_TER_STIMENA0 0x00000001 +#define CPU_ITM_TER_STIMENA0_BITN 0 +#define CPU_ITM_TER_STIMENA0_M 0x00000001 +#define CPU_ITM_TER_STIMENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TPR +// +//***************************************************************************** +// Field: [3:0] PRIVMASK +// +// Bit mask to enable unprivileged (User) access to ITM stimulus ports: +// +// Bit [0] enables stimulus ports 0, 1, ..., and 7. +// Bit [1] enables stimulus ports 8, 9, ..., and 15. +// Bit [2] enables stimulus ports 16, 17, ..., and 23. +// Bit [3] enables stimulus ports 24, 25, ..., and 31. +// +// 0: User access allowed to stimulus ports +// 1: Privileged access only to stimulus ports +#define CPU_ITM_TPR_PRIVMASK_W 4 +#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F +#define CPU_ITM_TPR_PRIVMASK_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TCR +// +//***************************************************************************** +// Field: [23] BUSY +// +// Set when ITM events present and being drained. +#define CPU_ITM_TCR_BUSY 0x00800000 +#define CPU_ITM_TCR_BUSY_BITN 23 +#define CPU_ITM_TCR_BUSY_M 0x00800000 +#define CPU_ITM_TCR_BUSY_S 23 + +// Field: [22:16] ATBID +// +// Trace Bus ID for CoreSight system. Optional identifier for multi-source +// trace stream formatting. If multi-source trace is in use, this field must be +// written with a non-zero value. +#define CPU_ITM_TCR_ATBID_W 7 +#define CPU_ITM_TCR_ATBID_M 0x007F0000 +#define CPU_ITM_TCR_ATBID_S 16 + +// Field: [9:8] TSPRESCALE +// +// Timestamp prescaler +// ENUMs: +// DIV64 Divide by 64 +// DIV16 Divide by 16 +// DIV4 Divide by 4 +// NOPRESCALING No prescaling +#define CPU_ITM_TCR_TSPRESCALE_W 2 +#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_S 8 +#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 +#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 +#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 + +// Field: [4] SWOENA +// +// Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If +// TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of +// the timestamp counter. +// +// 0x0: Mode disabled. Timestamp counter uses system clock from the core and +// counts continuously. +// 0x1: Timestamp counter uses lineout (data related) clock from TPIU +// interface. The timestamp counter is held in reset while the output line is +// idle. +#define CPU_ITM_TCR_SWOENA 0x00000010 +#define CPU_ITM_TCR_SWOENA_BITN 4 +#define CPU_ITM_TCR_SWOENA_M 0x00000010 +#define CPU_ITM_TCR_SWOENA_S 4 + +// Field: [3] DWTENA +// +// Enables the DWT stimulus (hardware event packet emission to the TPIU from +// the DWT) +#define CPU_ITM_TCR_DWTENA 0x00000008 +#define CPU_ITM_TCR_DWTENA_BITN 3 +#define CPU_ITM_TCR_DWTENA_M 0x00000008 +#define CPU_ITM_TCR_DWTENA_S 3 + +// Field: [2] SYNCENA +// +// Enables synchronization packet transmission for a synchronous TPIU. +// CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization +// speed. +#define CPU_ITM_TCR_SYNCENA 0x00000004 +#define CPU_ITM_TCR_SYNCENA_BITN 2 +#define CPU_ITM_TCR_SYNCENA_M 0x00000004 +#define CPU_ITM_TCR_SYNCENA_S 2 + +// Field: [1] TSENA +// +// Enables differential timestamps. Differential timestamps are emitted when a +// packet is written to the FIFO with a non-zero timestamp counter, and when +// the timestamp counter overflows. Timestamps are emitted during idle times +// after a fixed number of two million cycles. This provides a time reference +// for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps +// are triggered by activity on the internal trace bus only. In this case there +// is no regular timestamp output when the ITM is idle. +#define CPU_ITM_TCR_TSENA 0x00000002 +#define CPU_ITM_TCR_TSENA_BITN 1 +#define CPU_ITM_TCR_TSENA_M 0x00000002 +#define CPU_ITM_TCR_TSENA_S 1 + +// Field: [0] ITMENA +// +// Enables ITM. This is the master enable, and must be set before ITM Stimulus +// and Trace Enable registers can be written. +#define CPU_ITM_TCR_ITMENA 0x00000001 +#define CPU_ITM_TCR_ITMENA_BITN 0 +#define CPU_ITM_TCR_ITMENA_M 0x00000001 +#define CPU_ITM_TCR_ITMENA_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_LAR +// +//***************************************************************************** +// Field: [31:0] LOCK_ACCESS +// +// A privileged write of 0xC5ACCE55 enables more write access to Control +// Registers TER, TPR and TCR. An invalid write removes write access. +#define CPU_ITM_LAR_LOCK_ACCESS_W 32 +#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF +#define CPU_ITM_LAR_LOCK_ACCESS_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_LSR +// +//***************************************************************************** +// Field: [2] BYTEACC +// +// Reads 0 which means 8-bit lock access is not be implemented. +#define CPU_ITM_LSR_BYTEACC 0x00000004 +#define CPU_ITM_LSR_BYTEACC_BITN 2 +#define CPU_ITM_LSR_BYTEACC_M 0x00000004 +#define CPU_ITM_LSR_BYTEACC_S 2 + +// Field: [1] ACCESS +// +// Write access to component is blocked. All writes are ignored, reads are +// permitted. +#define CPU_ITM_LSR_ACCESS 0x00000002 +#define CPU_ITM_LSR_ACCESS_BITN 1 +#define CPU_ITM_LSR_ACCESS_M 0x00000002 +#define CPU_ITM_LSR_ACCESS_S 1 + +// Field: [0] PRESENT +// +// Indicates that a lock mechanism exists for this component. +#define CPU_ITM_LSR_PRESENT 0x00000001 +#define CPU_ITM_LSR_PRESENT_BITN 0 +#define CPU_ITM_LSR_PRESENT_M 0x00000001 +#define CPU_ITM_LSR_PRESENT_S 0 + + +#endif // __CPU_ITM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_rom_table.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_rom_table.h new file mode 100644 index 0000000..43c9a9f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_rom_table.h @@ -0,0 +1,220 @@ +/****************************************************************************** +* Filename: hw_cpu_rom_table_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_ROM_TABLE_H__ +#define __HW_CPU_ROM_TABLE_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_ROM_TABLE component +// +//***************************************************************************** +// System Control Space Component +#define CPU_ROM_TABLE_O_SCS 0x00000000 + +// Data Watchpoint and Trace Component +#define CPU_ROM_TABLE_O_DWT 0x00000004 + +// Flash Patch and Breakpoint Component +#define CPU_ROM_TABLE_O_FPB 0x00000008 + +// Instrumentation Trace Component +#define CPU_ROM_TABLE_O_ITM 0x0000000C + +// Trace Port Interface Component +#define CPU_ROM_TABLE_O_TPIU 0x00000010 + +// Enhanced Trace Component +#define CPU_ROM_TABLE_O_ETM 0x00000014 + +// End Marker +#define CPU_ROM_TABLE_O_END 0x00000018 + +// System Memory Map Access for DAP +#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_SCS +// +//***************************************************************************** +// Field: [31:0] SCS +// +// Points to the SCS at 0xE000E000. +// (SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000. +#define CPU_ROM_TABLE_SCS_SCS_W 32 +#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF +#define CPU_ROM_TABLE_SCS_SCS_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_DWT +// +//***************************************************************************** +// Field: [31:1] DWT +// +// Points to the Data Watchpoint and Trace block at 0xE0001000. +// (2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000. +#define CPU_ROM_TABLE_DWT_DWT_W 31 +#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE +#define CPU_ROM_TABLE_DWT_DWT_S 1 + +// Field: [0] DWT_PRESENT +// +// 0: DWT is not present +// 1: DWT is present. +#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_FPB +// +//***************************************************************************** +// Field: [31:1] FPB +// +// Points to the Flash Patch and Breakpoint block at 0xE0002000. +// (2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000. +#define CPU_ROM_TABLE_FPB_FPB_W 31 +#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE +#define CPU_ROM_TABLE_FPB_FPB_S 1 + +// Field: [0] FPB_PRESENT +// +// 0: FPB is not present +// 1: FPB is present. +#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_ITM +// +//***************************************************************************** +// Field: [31:1] ITM +// +// Points to the Instrumentation Trace block at 0xE0000000. +// (2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000. +#define CPU_ROM_TABLE_ITM_ITM_W 31 +#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ITM_ITM_S 1 + +// Field: [0] ITM_PRESENT +// +// 0: ITM is not present +// 1: ITM is present. +#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_TPIU +// +//***************************************************************************** +// Field: [31:1] TPIU +// +// Points to the TPIU. TPIU is at 0xE0040000. +// (2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000. +#define CPU_ROM_TABLE_TPIU_TPIU_W 31 +#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE +#define CPU_ROM_TABLE_TPIU_TPIU_S 1 + +// Field: [0] TPIU_PRESENT +// +// 0: TPIU is not present +// 1: TPIU is present. +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_ETM +// +//***************************************************************************** +// Field: [31:1] ETM +// +// Points to the ETM. ETM is at 0xE0041000. +// (2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000. +#define CPU_ROM_TABLE_ETM_ETM_W 31 +#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ETM_ETM_S 1 + +// Field: [0] ETM_PRESENT +// +// 0: ETM is not present +// 1: ETM is present. +#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_END +// +//***************************************************************************** +// Field: [31:0] END +// +// End of the ROM table +#define CPU_ROM_TABLE_END_END_W 32 +#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF +#define CPU_ROM_TABLE_END_END_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_SYSTEM_ACCESS +// +//***************************************************************************** +// Field: [0] SYSTEM_ACCESS +// +// 1: The system memory map is accessible using the DAP +// 0: Only debug resources are accessible using the DAP +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 + + +#endif // __CPU_ROM_TABLE__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_scs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_scs.h new file mode 100644 index 0000000..c7fa660 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_scs.h @@ -0,0 +1,3885 @@ +/****************************************************************************** +* Filename: hw_cpu_scs_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_SCS_H__ +#define __HW_CPU_SCS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_SCS component +// +//***************************************************************************** +// Interrupt Control Type +#define CPU_SCS_O_ICTR 0x00000004 + +// Auxiliary Control +#define CPU_SCS_O_ACTLR 0x00000008 + +// SysTick Control and Status +#define CPU_SCS_O_STCSR 0x00000010 + +// SysTick Reload Value +#define CPU_SCS_O_STRVR 0x00000014 + +// SysTick Current Value +#define CPU_SCS_O_STCVR 0x00000018 + +// SysTick Calibration Value +#define CPU_SCS_O_STCR 0x0000001C + +// Irq 0 to 31 Set Enable +#define CPU_SCS_O_NVIC_ISER0 0x00000100 + +// Irq 32 to 63 Set Enable +#define CPU_SCS_O_NVIC_ISER1 0x00000104 + +// Irq 0 to 31 Clear Enable +#define CPU_SCS_O_NVIC_ICER0 0x00000180 + +// Irq 32 to 63 Clear Enable +#define CPU_SCS_O_NVIC_ICER1 0x00000184 + +// Irq 0 to 31 Set Pending +#define CPU_SCS_O_NVIC_ISPR0 0x00000200 + +// Irq 32 to 63 Set Pending +#define CPU_SCS_O_NVIC_ISPR1 0x00000204 + +// Irq 0 to 31 Clear Pending +#define CPU_SCS_O_NVIC_ICPR0 0x00000280 + +// Irq 32 to 63 Clear Pending +#define CPU_SCS_O_NVIC_ICPR1 0x00000284 + +// Irq 0 to 31 Active Bit +#define CPU_SCS_O_NVIC_IABR0 0x00000300 + +// Irq 32 to 63 Active Bit +#define CPU_SCS_O_NVIC_IABR1 0x00000304 + +// Irq 0 to 3 Priority +#define CPU_SCS_O_NVIC_IPR0 0x00000400 + +// Irq 4 to 7 Priority +#define CPU_SCS_O_NVIC_IPR1 0x00000404 + +// Irq 8 to 11 Priority +#define CPU_SCS_O_NVIC_IPR2 0x00000408 + +// Irq 12 to 15 Priority +#define CPU_SCS_O_NVIC_IPR3 0x0000040C + +// Irq 16 to 19 Priority +#define CPU_SCS_O_NVIC_IPR4 0x00000410 + +// Irq 20 to 23 Priority +#define CPU_SCS_O_NVIC_IPR5 0x00000414 + +// Irq 24 to 27 Priority +#define CPU_SCS_O_NVIC_IPR6 0x00000418 + +// Irq 28 to 31 Priority +#define CPU_SCS_O_NVIC_IPR7 0x0000041C + +// Irq 32 to 35 Priority +#define CPU_SCS_O_NVIC_IPR8 0x00000420 + +// CPUID Base +#define CPU_SCS_O_CPUID 0x00000D00 + +// Interrupt Control State +#define CPU_SCS_O_ICSR 0x00000D04 + +// Vector Table Offset +#define CPU_SCS_O_VTOR 0x00000D08 + +// Application Interrupt/Reset Control +#define CPU_SCS_O_AIRCR 0x00000D0C + +// System Control +#define CPU_SCS_O_SCR 0x00000D10 + +// Configuration Control +#define CPU_SCS_O_CCR 0x00000D14 + +// System Handlers 4-7 Priority +#define CPU_SCS_O_SHPR1 0x00000D18 + +// System Handlers 8-11 Priority +#define CPU_SCS_O_SHPR2 0x00000D1C + +// System Handlers 12-15 Priority +#define CPU_SCS_O_SHPR3 0x00000D20 + +// System Handler Control and State +#define CPU_SCS_O_SHCSR 0x00000D24 + +// Configurable Fault Status +#define CPU_SCS_O_CFSR 0x00000D28 + +// Hard Fault Status +#define CPU_SCS_O_HFSR 0x00000D2C + +// Debug Fault Status +#define CPU_SCS_O_DFSR 0x00000D30 + +// Mem Manage Fault Address +#define CPU_SCS_O_MMFAR 0x00000D34 + +// Bus Fault Address +#define CPU_SCS_O_BFAR 0x00000D38 + +// Auxiliary Fault Status +#define CPU_SCS_O_AFSR 0x00000D3C + +// Processor Feature 0 +#define CPU_SCS_O_ID_PFR0 0x00000D40 + +// Processor Feature 1 +#define CPU_SCS_O_ID_PFR1 0x00000D44 + +// Debug Feature 0 +#define CPU_SCS_O_ID_DFR0 0x00000D48 + +// Auxiliary Feature 0 +#define CPU_SCS_O_ID_AFR0 0x00000D4C + +// Memory Model Feature 0 +#define CPU_SCS_O_ID_MMFR0 0x00000D50 + +// Memory Model Feature 1 +#define CPU_SCS_O_ID_MMFR1 0x00000D54 + +// Memory Model Feature 2 +#define CPU_SCS_O_ID_MMFR2 0x00000D58 + +// Memory Model Feature 3 +#define CPU_SCS_O_ID_MMFR3 0x00000D5C + +// ISA Feature 0 +#define CPU_SCS_O_ID_ISAR0 0x00000D60 + +// ISA Feature 1 +#define CPU_SCS_O_ID_ISAR1 0x00000D64 + +// ISA Feature 2 +#define CPU_SCS_O_ID_ISAR2 0x00000D68 + +// ISA Feature 3 +#define CPU_SCS_O_ID_ISAR3 0x00000D6C + +// ISA Feature 4 +#define CPU_SCS_O_ID_ISAR4 0x00000D70 + +// Coprocessor Access Control +#define CPU_SCS_O_CPACR 0x00000D88 + +// Debug Halting Control and Status +#define CPU_SCS_O_DHCSR 0x00000DF0 + +// Deubg Core Register Selector +#define CPU_SCS_O_DCRSR 0x00000DF4 + +// Debug Core Register Data +#define CPU_SCS_O_DCRDR 0x00000DF8 + +// Debug Exception and Monitor Control +#define CPU_SCS_O_DEMCR 0x00000DFC + +// Software Trigger Interrupt +#define CPU_SCS_O_STIR 0x00000F00 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ICTR +// +//***************************************************************************** +// Field: [2:0] INTLINESNUM +// +// Total number of interrupt lines in groups of 32. +// +// 0: 0...32 +// 1: 33...64 +// 2: 65...96 +// 3: 97...128 +// 4: 129...160 +// 5: 161...192 +// 6: 193...224 +// 7: 225...256 +#define CPU_SCS_ICTR_INTLINESNUM_W 3 +#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 +#define CPU_SCS_ICTR_INTLINESNUM_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ACTLR +// +//***************************************************************************** +// Field: [2] DISFOLD +// +// Disables folding of IT instruction. +#define CPU_SCS_ACTLR_DISFOLD 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_BITN 2 +#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_S 2 + +// Field: [1] DISDEFWBUF +// +// Disables write buffer use during default memory map accesses. This causes +// all bus faults to be precise bus faults but decreases the performance of the +// processor because the stores to memory have to complete before the next +// instruction can be executed. +#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 +#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 + +// Field: [0] DISMCYCINT +// +// Disables interruption of multi-cycle instructions. This increases the +// interrupt latency of the processor becuase LDM/STM completes before +// interrupt stacking occurs. +#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 +#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCSR +// +//***************************************************************************** +// Field: [16] COUNTFLAG +// +// Returns 1 if timer counted to 0 since last time this was read. Clears on +// read by application of any part of the SysTick Control and Status Register. +// If read by the debugger using the DAP, this bit is cleared on read-only if +// the MasterType bit in the **AHB-AP** Control Register is set to 0. +// Otherwise, COUNTFLAG is not changed by the debugger read. +#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 +#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_S 16 + +// Field: [2] CLKSOURCE +// +// Clock source: +// +// 0: External reference clock. +// 1: Core clock +// +// External clock is not available in this device. Writes to this field will be +// ignored. +#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 +#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_S 2 + +// Field: [1] TICKINT +// +// 0: Counting down to zero does not pend the SysTick handler. Software can use +// COUNTFLAG to determine if the SysTick handler has ever counted to zero. +// 1: Counting down to zero pends the SysTick handler. +#define CPU_SCS_STCSR_TICKINT 0x00000002 +#define CPU_SCS_STCSR_TICKINT_BITN 1 +#define CPU_SCS_STCSR_TICKINT_M 0x00000002 +#define CPU_SCS_STCSR_TICKINT_S 1 + +// Field: [0] ENABLE +// +// Enable SysTick counter +// +// 0: Counter disabled +// 1: Counter operates in a multi-shot way. That is, counter loads with the +// Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it +// sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on +// TICKINT. It then loads STRVR.RELOAD again, and begins counting. +#define CPU_SCS_STCSR_ENABLE 0x00000001 +#define CPU_SCS_STCSR_ENABLE_BITN 0 +#define CPU_SCS_STCSR_ENABLE_M 0x00000001 +#define CPU_SCS_STCSR_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STRVR +// +//***************************************************************************** +// Field: [23:0] RELOAD +// +// Value to load into the SysTick Current Value Register STCVR.CURRENT when the +// counter reaches 0. +#define CPU_SCS_STRVR_RELOAD_W 24 +#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF +#define CPU_SCS_STRVR_RELOAD_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCVR +// +//***************************************************************************** +// Field: [23:0] CURRENT +// +// Current value at the time the register is accessed. No read-modify-write +// protection is provided, so change with care. Writing to it with any value +// clears the register to 0. Clearing this register also clears +// STCSR.COUNTFLAG. +#define CPU_SCS_STCVR_CURRENT_W 24 +#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF +#define CPU_SCS_STCVR_CURRENT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCR +// +//***************************************************************************** +// Field: [31] NOREF +// +// Reads as one. Indicates that no separate reference clock is provided. +#define CPU_SCS_STCR_NOREF 0x80000000 +#define CPU_SCS_STCR_NOREF_BITN 31 +#define CPU_SCS_STCR_NOREF_M 0x80000000 +#define CPU_SCS_STCR_NOREF_S 31 + +// Field: [30] SKEW +// +// Reads as one. The calibration value is not exactly 10ms because of clock +// frequency. This could affect its suitability as a software real time clock. +#define CPU_SCS_STCR_SKEW 0x40000000 +#define CPU_SCS_STCR_SKEW_BITN 30 +#define CPU_SCS_STCR_SKEW_M 0x40000000 +#define CPU_SCS_STCR_SKEW_S 30 + +// Field: [23:0] TENMS +// +// An optional Reload value to be used for 10ms (100Hz) timing, subject to +// system clock skew errors. The value read is valid only when core clock is at +// 48MHz. +#define CPU_SCS_STCR_TENMS_W 24 +#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF +#define CPU_SCS_STCR_TENMS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISER0 +// +//***************************************************************************** +// Field: [31] SETENA31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 +#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 + +// Field: [30] SETENA30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 +#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 + +// Field: [29] SETENA29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 +#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 + +// Field: [28] SETENA28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 +#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 + +// Field: [27] SETENA27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 +#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 + +// Field: [26] SETENA26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 +#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 + +// Field: [25] SETENA25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 +#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 + +// Field: [24] SETENA24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 +#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 + +// Field: [23] SETENA23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 +#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 + +// Field: [22] SETENA22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 +#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 + +// Field: [21] SETENA21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 +#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 + +// Field: [20] SETENA20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 +#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 + +// Field: [19] SETENA19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 +#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 + +// Field: [18] SETENA18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 +#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 + +// Field: [17] SETENA17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 +#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 + +// Field: [16] SETENA16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 +#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 + +// Field: [15] SETENA15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 +#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 + +// Field: [14] SETENA14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 +#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 + +// Field: [13] SETENA13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 +#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 + +// Field: [12] SETENA12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 +#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 + +// Field: [11] SETENA11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 +#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 + +// Field: [10] SETENA10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 +#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 + +// Field: [9] SETENA9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 +#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 + +// Field: [8] SETENA8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 +#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 + +// Field: [7] SETENA7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 +#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 + +// Field: [6] SETENA6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 +#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 + +// Field: [5] SETENA5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 +#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 + +// Field: [4] SETENA4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 +#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 + +// Field: [3] SETENA3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 +#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 + +// Field: [2] SETENA2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 +#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 + +// Field: [1] SETENA1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 +#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 + +// Field: [0] SETENA0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 +#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISER1 +// +//***************************************************************************** +// Field: [1] SETENA33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 +#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 + +// Field: [0] SETENA32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 +#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICER0 +// +//***************************************************************************** +// Field: [31] CLRENA31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 +#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 + +// Field: [30] CLRENA30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 +#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 + +// Field: [29] CLRENA29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 +#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 + +// Field: [28] CLRENA28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 +#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 + +// Field: [27] CLRENA27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 +#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 + +// Field: [26] CLRENA26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 +#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 + +// Field: [25] CLRENA25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 +#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 + +// Field: [24] CLRENA24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 +#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 + +// Field: [23] CLRENA23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 +#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 + +// Field: [22] CLRENA22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 +#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 + +// Field: [21] CLRENA21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 +#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 + +// Field: [20] CLRENA20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 +#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 + +// Field: [19] CLRENA19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 +#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 + +// Field: [18] CLRENA18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 +#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 + +// Field: [17] CLRENA17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 +#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 + +// Field: [16] CLRENA16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 +#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 + +// Field: [15] CLRENA15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 +#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 + +// Field: [14] CLRENA14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 +#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 + +// Field: [13] CLRENA13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 +#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 + +// Field: [12] CLRENA12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 +#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 + +// Field: [11] CLRENA11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 +#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 + +// Field: [10] CLRENA10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 +#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 + +// Field: [9] CLRENA9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 +#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 + +// Field: [8] CLRENA8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 +#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 + +// Field: [7] CLRENA7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 +#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 + +// Field: [6] CLRENA6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 +#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 + +// Field: [5] CLRENA5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 +#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 + +// Field: [4] CLRENA4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 +#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 + +// Field: [3] CLRENA3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 +#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 + +// Field: [2] CLRENA2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 +#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 + +// Field: [1] CLRENA1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 +#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 + +// Field: [0] CLRENA0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 +#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICER1 +// +//***************************************************************************** +// Field: [1] CLRENA33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 +#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 + +// Field: [0] CLRENA32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 +#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISPR0 +// +//***************************************************************************** +// Field: [31] SETPEND31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 + +// Field: [30] SETPEND30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 + +// Field: [29] SETPEND29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 + +// Field: [28] SETPEND28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 + +// Field: [27] SETPEND27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 + +// Field: [26] SETPEND26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 + +// Field: [25] SETPEND25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 + +// Field: [24] SETPEND24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 + +// Field: [23] SETPEND23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 + +// Field: [22] SETPEND22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 + +// Field: [21] SETPEND21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 + +// Field: [20] SETPEND20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 + +// Field: [19] SETPEND19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 + +// Field: [18] SETPEND18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 + +// Field: [17] SETPEND17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 + +// Field: [16] SETPEND16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 + +// Field: [15] SETPEND15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 + +// Field: [14] SETPEND14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 + +// Field: [13] SETPEND13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 + +// Field: [12] SETPEND12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 + +// Field: [11] SETPEND11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 + +// Field: [10] SETPEND10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 + +// Field: [9] SETPEND9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 + +// Field: [8] SETPEND8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 + +// Field: [7] SETPEND7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 + +// Field: [6] SETPEND6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 + +// Field: [5] SETPEND5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 + +// Field: [4] SETPEND4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 + +// Field: [3] SETPEND3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 + +// Field: [2] SETPEND2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 + +// Field: [1] SETPEND1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 + +// Field: [0] SETPEND0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISPR1 +// +//***************************************************************************** +// Field: [1] SETPEND33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 + +// Field: [0] SETPEND32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICPR0 +// +//***************************************************************************** +// Field: [31] CLRPEND31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 + +// Field: [30] CLRPEND30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 + +// Field: [29] CLRPEND29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 + +// Field: [28] CLRPEND28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 + +// Field: [27] CLRPEND27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 + +// Field: [26] CLRPEND26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 + +// Field: [25] CLRPEND25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 + +// Field: [24] CLRPEND24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 + +// Field: [23] CLRPEND23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 + +// Field: [22] CLRPEND22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 + +// Field: [21] CLRPEND21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 + +// Field: [20] CLRPEND20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 + +// Field: [19] CLRPEND19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 + +// Field: [18] CLRPEND18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 + +// Field: [17] CLRPEND17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 + +// Field: [16] CLRPEND16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 + +// Field: [15] CLRPEND15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 + +// Field: [14] CLRPEND14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 + +// Field: [13] CLRPEND13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 + +// Field: [12] CLRPEND12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 + +// Field: [11] CLRPEND11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 + +// Field: [10] CLRPEND10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 + +// Field: [9] CLRPEND9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 + +// Field: [8] CLRPEND8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 + +// Field: [7] CLRPEND7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 + +// Field: [6] CLRPEND6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 + +// Field: [5] CLRPEND5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 + +// Field: [4] CLRPEND4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 + +// Field: [3] CLRPEND3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 + +// Field: [2] CLRPEND2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 + +// Field: [1] CLRPEND1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 + +// Field: [0] CLRPEND0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICPR1 +// +//***************************************************************************** +// Field: [1] CLRPEND33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 + +// Field: [0] CLRPEND32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IABR0 +// +//***************************************************************************** +// Field: [31] ACTIVE31 +// +// Reading 0 from this bit implies that interrupt line 31 is not active. +// Reading 1 from this bit implies that the interrupt line 31 is active (See +// EVENT:CPUIRQSEL31.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 + +// Field: [30] ACTIVE30 +// +// Reading 0 from this bit implies that interrupt line 30 is not active. +// Reading 1 from this bit implies that the interrupt line 30 is active (See +// EVENT:CPUIRQSEL30.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 + +// Field: [29] ACTIVE29 +// +// Reading 0 from this bit implies that interrupt line 29 is not active. +// Reading 1 from this bit implies that the interrupt line 29 is active (See +// EVENT:CPUIRQSEL29.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 + +// Field: [28] ACTIVE28 +// +// Reading 0 from this bit implies that interrupt line 28 is not active. +// Reading 1 from this bit implies that the interrupt line 28 is active (See +// EVENT:CPUIRQSEL28.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 + +// Field: [27] ACTIVE27 +// +// Reading 0 from this bit implies that interrupt line 27 is not active. +// Reading 1 from this bit implies that the interrupt line 27 is active (See +// EVENT:CPUIRQSEL27.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 + +// Field: [26] ACTIVE26 +// +// Reading 0 from this bit implies that interrupt line 26 is not active. +// Reading 1 from this bit implies that the interrupt line 26 is active (See +// EVENT:CPUIRQSEL26.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 + +// Field: [25] ACTIVE25 +// +// Reading 0 from this bit implies that interrupt line 25 is not active. +// Reading 1 from this bit implies that the interrupt line 25 is active (See +// EVENT:CPUIRQSEL25.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 + +// Field: [24] ACTIVE24 +// +// Reading 0 from this bit implies that interrupt line 24 is not active. +// Reading 1 from this bit implies that the interrupt line 24 is active (See +// EVENT:CPUIRQSEL24.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 + +// Field: [23] ACTIVE23 +// +// Reading 0 from this bit implies that interrupt line 23 is not active. +// Reading 1 from this bit implies that the interrupt line 23 is active (See +// EVENT:CPUIRQSEL23.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 + +// Field: [22] ACTIVE22 +// +// Reading 0 from this bit implies that interrupt line 22 is not active. +// Reading 1 from this bit implies that the interrupt line 22 is active (See +// EVENT:CPUIRQSEL22.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 + +// Field: [21] ACTIVE21 +// +// Reading 0 from this bit implies that interrupt line 21 is not active. +// Reading 1 from this bit implies that the interrupt line 21 is active (See +// EVENT:CPUIRQSEL21.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 + +// Field: [20] ACTIVE20 +// +// Reading 0 from this bit implies that interrupt line 20 is not active. +// Reading 1 from this bit implies that the interrupt line 20 is active (See +// EVENT:CPUIRQSEL20.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 + +// Field: [19] ACTIVE19 +// +// Reading 0 from this bit implies that interrupt line 19 is not active. +// Reading 1 from this bit implies that the interrupt line 19 is active (See +// EVENT:CPUIRQSEL19.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 + +// Field: [18] ACTIVE18 +// +// Reading 0 from this bit implies that interrupt line 18 is not active. +// Reading 1 from this bit implies that the interrupt line 18 is active (See +// EVENT:CPUIRQSEL18.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 + +// Field: [17] ACTIVE17 +// +// Reading 0 from this bit implies that interrupt line 17 is not active. +// Reading 1 from this bit implies that the interrupt line 17 is active (See +// EVENT:CPUIRQSEL17.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 + +// Field: [16] ACTIVE16 +// +// Reading 0 from this bit implies that interrupt line 16 is not active. +// Reading 1 from this bit implies that the interrupt line 16 is active (See +// EVENT:CPUIRQSEL16.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 + +// Field: [15] ACTIVE15 +// +// Reading 0 from this bit implies that interrupt line 15 is not active. +// Reading 1 from this bit implies that the interrupt line 15 is active (See +// EVENT:CPUIRQSEL15.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 + +// Field: [14] ACTIVE14 +// +// Reading 0 from this bit implies that interrupt line 14 is not active. +// Reading 1 from this bit implies that the interrupt line 14 is active (See +// EVENT:CPUIRQSEL14.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 + +// Field: [13] ACTIVE13 +// +// Reading 0 from this bit implies that interrupt line 13 is not active. +// Reading 1 from this bit implies that the interrupt line 13 is active (See +// EVENT:CPUIRQSEL13.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 + +// Field: [12] ACTIVE12 +// +// Reading 0 from this bit implies that interrupt line 12 is not active. +// Reading 1 from this bit implies that the interrupt line 12 is active (See +// EVENT:CPUIRQSEL12.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 + +// Field: [11] ACTIVE11 +// +// Reading 0 from this bit implies that interrupt line 11 is not active. +// Reading 1 from this bit implies that the interrupt line 11 is active (See +// EVENT:CPUIRQSEL11.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 + +// Field: [10] ACTIVE10 +// +// Reading 0 from this bit implies that interrupt line 10 is not active. +// Reading 1 from this bit implies that the interrupt line 10 is active (See +// EVENT:CPUIRQSEL10.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 + +// Field: [9] ACTIVE9 +// +// Reading 0 from this bit implies that interrupt line 9 is not active. Reading +// 1 from this bit implies that the interrupt line 9 is active (See +// EVENT:CPUIRQSEL9.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 + +// Field: [8] ACTIVE8 +// +// Reading 0 from this bit implies that interrupt line 8 is not active. Reading +// 1 from this bit implies that the interrupt line 8 is active (See +// EVENT:CPUIRQSEL8.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 + +// Field: [7] ACTIVE7 +// +// Reading 0 from this bit implies that interrupt line 7 is not active. Reading +// 1 from this bit implies that the interrupt line 7 is active (See +// EVENT:CPUIRQSEL7.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 + +// Field: [6] ACTIVE6 +// +// Reading 0 from this bit implies that interrupt line 6 is not active. Reading +// 1 from this bit implies that the interrupt line 6 is active (See +// EVENT:CPUIRQSEL6.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 + +// Field: [5] ACTIVE5 +// +// Reading 0 from this bit implies that interrupt line 5 is not active. Reading +// 1 from this bit implies that the interrupt line 5 is active (See +// EVENT:CPUIRQSEL5.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 + +// Field: [4] ACTIVE4 +// +// Reading 0 from this bit implies that interrupt line 4 is not active. Reading +// 1 from this bit implies that the interrupt line 4 is active (See +// EVENT:CPUIRQSEL4.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 + +// Field: [3] ACTIVE3 +// +// Reading 0 from this bit implies that interrupt line 3 is not active. Reading +// 1 from this bit implies that the interrupt line 3 is active (See +// EVENT:CPUIRQSEL3.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 + +// Field: [2] ACTIVE2 +// +// Reading 0 from this bit implies that interrupt line 2 is not active. Reading +// 1 from this bit implies that the interrupt line 2 is active (See +// EVENT:CPUIRQSEL2.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 + +// Field: [1] ACTIVE1 +// +// Reading 0 from this bit implies that interrupt line 1 is not active. Reading +// 1 from this bit implies that the interrupt line 1 is active (See +// EVENT:CPUIRQSEL1.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 + +// Field: [0] ACTIVE0 +// +// Reading 0 from this bit implies that interrupt line 0 is not active. Reading +// 1 from this bit implies that the interrupt line 0 is active (See +// EVENT:CPUIRQSEL0.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IABR1 +// +//***************************************************************************** +// Field: [1] ACTIVE33 +// +// Reading 0 from this bit implies that interrupt line 33 is not active. +// Reading 1 from this bit implies that the interrupt line 33 is active (See +// EVENT:CPUIRQSEL33.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 + +// Field: [0] ACTIVE32 +// +// Reading 0 from this bit implies that interrupt line 32 is not active. +// Reading 1 from this bit implies that the interrupt line 32 is active (See +// EVENT:CPUIRQSEL32.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR0 +// +//***************************************************************************** +// Field: [31:24] PRI_3 +// +// Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 +#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 + +// Field: [23:16] PRI_2 +// +// Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 + +// Field: [15:8] PRI_1 +// +// Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 + +// Field: [7:0] PRI_0 +// +// Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF +#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR1 +// +//***************************************************************************** +// Field: [31:24] PRI_7 +// +// Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 +#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 + +// Field: [23:16] PRI_6 +// +// Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 + +// Field: [15:8] PRI_5 +// +// Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 + +// Field: [7:0] PRI_4 +// +// Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF +#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR2 +// +//***************************************************************************** +// Field: [31:24] PRI_11 +// +// Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 + +// Field: [23:16] PRI_10 +// +// Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 + +// Field: [15:8] PRI_9 +// +// Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 + +// Field: [7:0] PRI_8 +// +// Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF +#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR3 +// +//***************************************************************************** +// Field: [31:24] PRI_15 +// +// Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 + +// Field: [23:16] PRI_14 +// +// Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 + +// Field: [15:8] PRI_13 +// +// Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 + +// Field: [7:0] PRI_12 +// +// Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF +#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR4 +// +//***************************************************************************** +// Field: [31:24] PRI_19 +// +// Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 +#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 + +// Field: [23:16] PRI_18 +// +// Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 + +// Field: [15:8] PRI_17 +// +// Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 + +// Field: [7:0] PRI_16 +// +// Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF +#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR5 +// +//***************************************************************************** +// Field: [31:24] PRI_23 +// +// Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 +#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 + +// Field: [23:16] PRI_22 +// +// Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 + +// Field: [15:8] PRI_21 +// +// Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 + +// Field: [7:0] PRI_20 +// +// Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF +#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR6 +// +//***************************************************************************** +// Field: [31:24] PRI_27 +// +// Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 +#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 + +// Field: [23:16] PRI_26 +// +// Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 + +// Field: [15:8] PRI_25 +// +// Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 + +// Field: [7:0] PRI_24 +// +// Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF +#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR7 +// +//***************************************************************************** +// Field: [31:24] PRI_31 +// +// Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 +#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 + +// Field: [23:16] PRI_30 +// +// Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 + +// Field: [15:8] PRI_29 +// +// Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 + +// Field: [7:0] PRI_28 +// +// Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF +#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR8 +// +//***************************************************************************** +// Field: [15:8] PRI_33 +// +// Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 + +// Field: [7:0] PRI_32 +// +// Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF +#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CPUID +// +//***************************************************************************** +// Field: [31:24] IMPLEMENTER +// +// Implementor code. +#define CPU_SCS_CPUID_IMPLEMENTER_W 8 +#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 +#define CPU_SCS_CPUID_IMPLEMENTER_S 24 + +// Field: [23:20] VARIANT +// +// Implementation defined variant number. +#define CPU_SCS_CPUID_VARIANT_W 4 +#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 +#define CPU_SCS_CPUID_VARIANT_S 20 + +// Field: [19:16] CONSTANT +// +// Reads as 0xF +#define CPU_SCS_CPUID_CONSTANT_W 4 +#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 +#define CPU_SCS_CPUID_CONSTANT_S 16 + +// Field: [15:4] PARTNO +// +// Number of processor within family. +#define CPU_SCS_CPUID_PARTNO_W 12 +#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 +#define CPU_SCS_CPUID_PARTNO_S 4 + +// Field: [3:0] REVISION +// +// Implementation defined revision number. +#define CPU_SCS_CPUID_REVISION_W 4 +#define CPU_SCS_CPUID_REVISION_M 0x0000000F +#define CPU_SCS_CPUID_REVISION_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ICSR +// +//***************************************************************************** +// Field: [31] NMIPENDSET +// +// Set pending NMI bit. Setting this bit pends and activates an NMI. Because +// NMI is the highest-priority interrupt, it takes effect as soon as it +// registers. +// +// 0: No action +// 1: Set pending NMI +#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 +#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_S 31 + +// Field: [28] PENDSVSET +// +// Set pending pendSV bit. +// +// 0: No action +// 1: Set pending PendSV +#define CPU_SCS_ICSR_PENDSVSET 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_BITN 28 +#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_S 28 + +// Field: [27] PENDSVCLR +// +// Clear pending pendSV bit +// +// 0: No action +// 1: Clear pending pendSV +#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 +#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_S 27 + +// Field: [26] PENDSTSET +// +// Set a pending SysTick bit. +// +// 0: No action +// 1: Set pending SysTick +#define CPU_SCS_ICSR_PENDSTSET 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_BITN 26 +#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_S 26 + +// Field: [25] PENDSTCLR +// +// Clear pending SysTick bit +// +// 0: No action +// 1: Clear pending SysTick +#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 +#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_S 25 + +// Field: [23] ISRPREEMPT +// +// This field can only be used at debug time. It indicates that a pending +// interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, +// the interrupt is serviced. +// +// 0: A pending exception is not serviced. +// 1: A pending exception is serviced on exit from the debug halt state +#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 +#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_S 23 + +// Field: [22] ISRPENDING +// +// Interrupt pending flag. Excludes NMI and faults. +// +// 0x0: Interrupt not pending +// 0x1: Interrupt pending +#define CPU_SCS_ICSR_ISRPENDING 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_BITN 22 +#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_S 22 + +// Field: [17:12] VECTPENDING +// +// Pending ISR number field. This field contains the interrupt number of the +// highest priority pending ISR. +#define CPU_SCS_ICSR_VECTPENDING_W 6 +#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 +#define CPU_SCS_ICSR_VECTPENDING_S 12 + +// Field: [11] RETTOBASE +// +// Indicates whether there are preempted active exceptions: +// +// 0: There are preempted active exceptions to execute +// 1: There are no active exceptions, or the currently-executing exception is +// the only active exception. +#define CPU_SCS_ICSR_RETTOBASE 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_BITN 11 +#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_S 11 + +// Field: [8:0] VECTACTIVE +// +// Active ISR number field. Reset clears this field. +#define CPU_SCS_ICSR_VECTACTIVE_W 9 +#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF +#define CPU_SCS_ICSR_VECTACTIVE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_VTOR +// +//***************************************************************************** +// Field: [29:7] TBLOFF +// +// Bits 29 down to 7 of the vector table base offset. +#define CPU_SCS_VTOR_TBLOFF_W 23 +#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 +#define CPU_SCS_VTOR_TBLOFF_S 7 + +//***************************************************************************** +// +// Register: CPU_SCS_O_AIRCR +// +//***************************************************************************** +// Field: [31:16] VECTKEY +// +// Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. +// Otherwise the write value is ignored. Read always returns 0xFA05. +#define CPU_SCS_AIRCR_VECTKEY_W 16 +#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 +#define CPU_SCS_AIRCR_VECTKEY_S 16 + +// Field: [15] ENDIANESS +// +// Data endianness bit +// ENUMs: +// BIG Big endian +// LITTLE Little endian +#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 +#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_S 15 +#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 + +// Field: [10:8] PRIGROUP +// +// Interrupt priority grouping field. This field is a binary point position +// indicator for creating subpriorities for exceptions that share the same +// pre-emption level. It divides the PRI_n field in the Interrupt Priority +// Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption +// level and a subpriority level. The binary point is a left-of value. This +// means that the PRIGROUP value represents a point starting at the left of the +// Least Significant Bit (LSB). The lowest value might not be 0 depending on +// the number of bits allocated for priorities, and implementation choices. +#define CPU_SCS_AIRCR_PRIGROUP_W 3 +#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 +#define CPU_SCS_AIRCR_PRIGROUP_S 8 + +// Field: [2] SYSRESETREQ +// +// Requests a warm reset. Setting this bit does not prevent Halting Debug from +// running. +#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 +#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 + +// Field: [1] VECTCLRACTIVE +// +// Clears all active state information for active NMI, fault, and interrupts. +// It is the responsibility of the application to reinitialize the stack. This +// bit is for returning to a known state during debug. The bit self-clears. +// IPSR is not cleared by this operation. So, if used by an application, it +// must only be used at the base level of activation, or within a system +// handler whose active bit can be set. +#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 + +// Field: [0] VECTRESET +// +// System Reset bit. Resets the system, with the exception of debug components. +// This bit is reserved for debug use and can be written to 1 only when the +// core is halted. The bit self-clears. Writing this bit to 1 while core is not +// halted may result in unpredictable behavior. +#define CPU_SCS_AIRCR_VECTRESET 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_BITN 0 +#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SCR +// +//***************************************************************************** +// Field: [4] SEVONPEND +// +// Send Event on Pending bit: +// +// 0: Only enabled interrupts or events can wakeup the processor, disabled +// interrupts are excluded +// 1: Enabled events and all interrupts, including disabled interrupts, can +// wakeup the processor. +// +// When an event or interrupt enters pending state, the event signal wakes up +// the processor from WFE. If +// the processor is not waiting for an event, the event is registered and +// affects the next WFE. +// The processor also wakes up on execution of an SEV instruction. +#define CPU_SCS_SCR_SEVONPEND 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_BITN 4 +#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_S 4 + +// Field: [2] SLEEPDEEP +// +// Controls whether the processor uses sleep or deep sleep as its low power +// mode +// ENUMs: +// DEEPSLEEP Deep sleep +// SLEEP Sleep +#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 +#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_S 2 +#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 + +// Field: [1] SLEEPONEXIT +// +// Sleep on exit when returning from Handler mode to Thread mode. Enables +// interrupt driven applications to avoid returning to empty main application. +// +// 0: Do not sleep when returning to thread mode +// 1: Sleep on ISR exit +#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 +#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_S 1 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CCR +// +//***************************************************************************** +// Field: [9] STKALIGN +// +// Stack alignment bit. +// +// 0: Only 4-byte alignment is guaranteed for the SP used prior to the +// exception on exception entry. +// 1: On exception entry, the SP used prior to the exception is adjusted to be +// 8-byte aligned and the context to restore it is saved. The SP is restored on +// the associated exception return. +#define CPU_SCS_CCR_STKALIGN 0x00000200 +#define CPU_SCS_CCR_STKALIGN_BITN 9 +#define CPU_SCS_CCR_STKALIGN_M 0x00000200 +#define CPU_SCS_CCR_STKALIGN_S 9 + +// Field: [8] BFHFNMIGN +// +// Enables handlers with priority -1 or -2 to ignore data BusFaults caused by +// load and store instructions. This applies to the HardFault, NMI, and +// FAULTMASK escalated handlers: +// +// 0: Data BusFaults caused by load and store instructions cause a lock-up +// 1: Data BusFaults caused by load and store instructions are ignored. +// +// Set this bit to 1 only when the handler and its data are in absolutely safe +// memory. The normal use +// of this bit is to probe system devices and bridges to detect problems. +#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 +#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_S 8 + +// Field: [4] DIV_0_TRP +// +// Enables faulting or halting when the processor executes an SDIV or UDIV +// instruction with a divisor of 0: +// +// 0: Do not trap divide by 0. In this mode, a divide by zero returns a +// quotient of 0. +// 1: Trap divide by 0. The relevant Usage Fault Status Register bit is +// CFSR.DIVBYZERO. +#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 +#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_S 4 + +// Field: [3] UNALIGN_TRP +// +// Enables unaligned access traps: +// +// 0: Do not trap unaligned halfword and word accesses +// 1: Trap unaligned halfword and word accesses. The relevant Usage Fault +// Status Register bit is CFSR.UNALIGNED. +// +// If this bit is set to 1, an unaligned access generates a UsageFault. +// Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of +// the value in UNALIGN_TRP. +#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 +#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_S 3 + +// Field: [1] USERSETMPEND +// +// Enables unprivileged software access to STIR: +// +// 0: User code is not allowed to write to the Software Trigger Interrupt +// register (STIR). +// 1: User code can write the Software Trigger Interrupt register (STIR) to +// trigger (pend) a Main exception, which is associated with the Main stack +// pointer. +#define CPU_SCS_CCR_USERSETMPEND 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_BITN 1 +#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_S 1 + +// Field: [0] NONBASETHREDENA +// +// Indicates how the processor enters Thread mode: +// +// 0: Processor can enter Thread mode only when no exception is active. +// 1: Processor can enter Thread mode from any level using the appropriate +// return value (EXC_RETURN). +// +// Exception returns occur when one of the following instructions loads a value +// of 0xFXXXXXXX into the PC while in Handler mode: +// - POP/LDM which includes loading the PC. +// - LDR with PC as a destination. +// - BX with any register. +// The value written to the PC is intercepted and is referred to as the +// EXC_RETURN value. +#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 +#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR1 +// +//***************************************************************************** +// Field: [23:16] PRI_6 +// +// Priority of system handler 6. UsageFault +#define CPU_SCS_SHPR1_PRI_6_W 8 +#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_SHPR1_PRI_6_S 16 + +// Field: [15:8] PRI_5 +// +// Priority of system handler 5: BusFault +#define CPU_SCS_SHPR1_PRI_5_W 8 +#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_SHPR1_PRI_5_S 8 + +// Field: [7:0] PRI_4 +// +// Priority of system handler 4: MemManage +#define CPU_SCS_SHPR1_PRI_4_W 8 +#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF +#define CPU_SCS_SHPR1_PRI_4_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR2 +// +//***************************************************************************** +// Field: [31:24] PRI_11 +// +// Priority of system handler 11. SVCall +#define CPU_SCS_SHPR2_PRI_11_W 8 +#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_SHPR2_PRI_11_S 24 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR3 +// +//***************************************************************************** +// Field: [31:24] PRI_15 +// +// Priority of system handler 15. SysTick exception +#define CPU_SCS_SHPR3_PRI_15_W 8 +#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_SHPR3_PRI_15_S 24 + +// Field: [23:16] PRI_14 +// +// Priority of system handler 14. Pend SV +#define CPU_SCS_SHPR3_PRI_14_W 8 +#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_SHPR3_PRI_14_S 16 + +// Field: [7:0] PRI_12 +// +// Priority of system handler 12. Debug Monitor +#define CPU_SCS_SHPR3_PRI_12_W 8 +#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF +#define CPU_SCS_SHPR3_PRI_12_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHCSR +// +//***************************************************************************** +// Field: [18] USGFAULTENA +// +// Usage fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 +#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_S 18 +#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 + +// Field: [17] BUSFAULTENA +// +// Bus fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 + +// Field: [16] MEMFAULTENA +// +// MemManage fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 + +// Field: [15] SVCALLPENDED +// +// SVCall pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 + +// Field: [14] BUSFAULTPENDED +// +// BusFault pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [13] MEMFAULTPENDED +// +// MemManage exception pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [12] USGFAULTPENDED +// +// Usage fault pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [11] SYSTICKACT +// +// SysTick active flag. +// +// 0x0: Not active +// 0x1: Active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 +#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_S 11 +#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 + +// Field: [10] PENDSVACT +// +// PendSV active +// +// 0x0: Not active +// 0x1: Active +#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 +#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_S 10 + +// Field: [8] MONITORACT +// +// Debug monitor active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_MONITORACT 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_BITN 8 +#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_S 8 +#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 + +// Field: [7] SVCALLACT +// +// SVCall active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 +#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_S 7 +#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 + +// Field: [3] USGFAULTACT +// +// UsageFault exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 +#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_S 3 +#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 + +// Field: [1] BUSFAULTACT +// +// BusFault exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 + +// Field: [0] MEMFAULTACT +// +// MemManage exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CFSR +// +//***************************************************************************** +// Field: [25] DIVBYZERO +// +// When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is +// enabled and an SDIV or UDIV instruction is used with a divisor of 0, this +// fault occurs The instruction is executed and the return PC points to it. If +// CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. +#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 +#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_S 25 + +// Field: [24] UNALIGNED +// +// When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an +// unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD +// instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. +#define CPU_SCS_CFSR_UNALIGNED 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_BITN 24 +#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_S 24 + +// Field: [19] NOCP +// +// Attempt to use a coprocessor instruction. The processor does not support +// coprocessor instructions. +#define CPU_SCS_CFSR_NOCP 0x00080000 +#define CPU_SCS_CFSR_NOCP_BITN 19 +#define CPU_SCS_CFSR_NOCP_M 0x00080000 +#define CPU_SCS_CFSR_NOCP_S 19 + +// Field: [18] INVPC +// +// Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid +// context, invalid value. The return PC points to the instruction that tried +// to set the PC. +#define CPU_SCS_CFSR_INVPC 0x00040000 +#define CPU_SCS_CFSR_INVPC_BITN 18 +#define CPU_SCS_CFSR_INVPC_M 0x00040000 +#define CPU_SCS_CFSR_INVPC_S 18 + +// Field: [17] INVSTATE +// +// Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX +// type instruction has changed state). This includes state change after entry +// to or return from exception, as well as from inter-working instructions. +// Return PC points to faulting instruction, with the invalid state. +#define CPU_SCS_CFSR_INVSTATE 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_BITN 17 +#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_S 17 + +// Field: [16] UNDEFINSTR +// +// This bit is set when the processor attempts to execute an undefined +// instruction. This is an instruction that the processor cannot decode. The +// return PC points to the undefined instruction. +#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 +#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_S 16 + +// Field: [15] BFARVALID +// +// This bit is set if the Bus Fault Address Register (BFAR) contains a valid +// address. This is true after a bus fault where the address is known. Other +// faults can clear this bit, such as a Mem Manage fault occurring later. If a +// Bus fault occurs that is escalated to a Hard Fault because of priority, the +// Hard Fault handler must clear this bit. This prevents problems if returning +// to a stacked active Bus fault handler whose BFAR value has been overwritten. +#define CPU_SCS_CFSR_BFARVALID 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_BITN 15 +#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_S 15 + +// Field: [12] STKERR +// +// Stacking from exception has caused one or more bus faults. The SP is still +// adjusted and the values in the context area on the stack might be incorrect. +// BFAR is not written. +#define CPU_SCS_CFSR_STKERR 0x00001000 +#define CPU_SCS_CFSR_STKERR_BITN 12 +#define CPU_SCS_CFSR_STKERR_M 0x00001000 +#define CPU_SCS_CFSR_STKERR_S 12 + +// Field: [11] UNSTKERR +// +// Unstack from exception return has caused one or more bus faults. This is +// chained to the handler, so that the original return stack is still present. +// SP is not adjusted from failing return and new save is not performed. BFAR +// is not written. +#define CPU_SCS_CFSR_UNSTKERR 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_BITN 11 +#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_S 11 + +// Field: [10] IMPRECISERR +// +// Imprecise data bus error. It is a BusFault, but the Return PC is not related +// to the causing instruction. This is not a synchronous fault. So, if detected +// when the priority of the current activation is higher than the Bus Fault, it +// only pends. Bus fault activates when returning to a lower priority +// activation. If a precise fault occurs before returning to a lower priority +// exception, the handler detects both IMPRECISERR set and one of the precise +// fault status bits set at the same time. BFAR is not written. +#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 +#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_S 10 + +// Field: [9] PRECISERR +// +// Precise data bus error return. +#define CPU_SCS_CFSR_PRECISERR 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_BITN 9 +#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_S 9 + +// Field: [8] IBUSERR +// +// Instruction bus error flag. This flag is set by a prefetch error. The fault +// stops on the instruction, so if the error occurs under a branch shadow, no +// fault occurs. BFAR is not written. +#define CPU_SCS_CFSR_IBUSERR 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_BITN 8 +#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_S 8 + +// Field: [7] MMARVALID +// +// Memory Manage Address Register (MMFAR) address valid flag. A later-arriving +// fault, such as a bus fault, can clear a memory manage fault.. If a MemManage +// fault occurs that is escalated to a Hard Fault because of priority, the Hard +// Fault handler must clear this bit. This prevents problems on return to a +// stacked active MemManage handler whose MMFAR value has been overwritten. +#define CPU_SCS_CFSR_MMARVALID 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_BITN 7 +#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_S 7 + +// Field: [4] MSTKERR +// +// Stacking from exception has caused one or more access violations. The SP is +// still adjusted and the values in the context area on the stack might be +// incorrect. MMFAR is not written. +#define CPU_SCS_CFSR_MSTKERR 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_BITN 4 +#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_S 4 + +// Field: [3] MUNSTKERR +// +// Unstack from exception return has caused one or more access violations. This +// is chained to the handler, so that the original return stack is still +// present. SP is not adjusted from failing return and new save is not +// performed. MMFAR is not written. +#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 +#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_S 3 + +// Field: [1] DACCVIOL +// +// Data access violation flag. Attempting to load or store at a location that +// does not permit the operation sets this flag. The return PC points to the +// faulting instruction. This error loads MMFAR with the address of the +// attempted access. +#define CPU_SCS_CFSR_DACCVIOL 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_BITN 1 +#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_S 1 + +// Field: [0] IACCVIOL +// +// Instruction access violation flag. Attempting to fetch an instruction from a +// location that does not permit execution sets this flag. This occurs on any +// access to an XN region, even when the MPU is disabled or not present. The +// return PC points to the faulting instruction. MMFAR is not written. +#define CPU_SCS_CFSR_IACCVIOL 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_BITN 0 +#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_HFSR +// +//***************************************************************************** +// Field: [31] DEBUGEVT +// +// This bit is set if there is a fault related to debug. This is only possible +// when halting debug is not enabled. For monitor enabled debug, it only +// happens for BKPT when the current priority is higher than the monitor. When +// both halting and monitor debug are disabled, it only happens for debug +// events that are not ignored (minimally, BKPT). The Debug Fault Status +// Register is updated. +#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 +#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_S 31 + +// Field: [30] FORCED +// +// Hard Fault activated because a Configurable Fault was received and cannot +// activate because of priority or because the Configurable Fault is disabled. +// The Hard Fault handler then has to read the other fault status registers to +// determine cause. +#define CPU_SCS_HFSR_FORCED 0x40000000 +#define CPU_SCS_HFSR_FORCED_BITN 30 +#define CPU_SCS_HFSR_FORCED_M 0x40000000 +#define CPU_SCS_HFSR_FORCED_S 30 + +// Field: [1] VECTTBL +// +// This bit is set if there is a fault because of vector table read on +// exception processing (Bus Fault). This case is always a Hard Fault. The +// return PC points to the pre-empted instruction. +#define CPU_SCS_HFSR_VECTTBL 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_BITN 1 +#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_S 1 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DFSR +// +//***************************************************************************** +// Field: [4] EXTERNAL +// +// External debug request flag. The processor stops on next instruction +// boundary. +// +// 0x0: External debug request signal not asserted +// 0x1: External debug request signal asserted +#define CPU_SCS_DFSR_EXTERNAL 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_BITN 4 +#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_S 4 + +// Field: [3] VCATCH +// +// Vector catch flag. When this flag is set, a flag in one of the local fault +// status registers is also set to indicate the type of fault. +// +// 0x0: No vector catch occurred +// 0x1: Vector catch occurred +#define CPU_SCS_DFSR_VCATCH 0x00000008 +#define CPU_SCS_DFSR_VCATCH_BITN 3 +#define CPU_SCS_DFSR_VCATCH_M 0x00000008 +#define CPU_SCS_DFSR_VCATCH_S 3 + +// Field: [2] DWTTRAP +// +// Data Watchpoint and Trace (DWT) flag. The processor stops at the current +// instruction or at the next instruction. +// +// 0x0: No DWT match +// 0x1: DWT match +#define CPU_SCS_DFSR_DWTTRAP 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_BITN 2 +#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_S 2 + +// Field: [1] BKPT +// +// BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, +// and also by normal code. Return PC points to breakpoint containing +// instruction. +// +// 0x0: No BKPT instruction execution +// 0x1: BKPT instruction execution +#define CPU_SCS_DFSR_BKPT 0x00000002 +#define CPU_SCS_DFSR_BKPT_BITN 1 +#define CPU_SCS_DFSR_BKPT_M 0x00000002 +#define CPU_SCS_DFSR_BKPT_S 1 + +// Field: [0] HALTED +// +// Halt request flag. The processor is halted on the next instruction. +// +// 0x0: No halt request +// 0x1: Halt requested by NVIC, including step +#define CPU_SCS_DFSR_HALTED 0x00000001 +#define CPU_SCS_DFSR_HALTED_BITN 0 +#define CPU_SCS_DFSR_HALTED_M 0x00000001 +#define CPU_SCS_DFSR_HALTED_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MMFAR +// +//***************************************************************************** +// Field: [31:0] ADDRESS +// +// Mem Manage fault address field. +// This field is the data address of a faulted load or store attempt. When an +// unaligned access faults, the address is the actual address that faulted. +// Because an access can be split into multiple parts, each aligned, this +// address can be any offset in the range of the requested size. Flags +// CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination +// with CFSR.MMARVALIDindicate the cause of the fault. +#define CPU_SCS_MMFAR_ADDRESS_W 32 +#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_MMFAR_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_BFAR +// +//***************************************************************************** +// Field: [31:0] ADDRESS +// +// Bus fault address field. This field is the data address of a faulted load or +// store attempt. When an unaligned access faults, the address is the address +// requested by the instruction, even if that is not the address that faulted. +// Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and +// CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the +// fault. +#define CPU_SCS_BFAR_ADDRESS_W 32 +#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_BFAR_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_AFSR +// +//***************************************************************************** +// Field: [31:0] IMPDEF +// +// Implementation defined. The bits map directly onto the signal assignment to +// the auxiliary fault inputs. Tied to 0 +#define CPU_SCS_AFSR_IMPDEF_W 32 +#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF +#define CPU_SCS_AFSR_IMPDEF_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_PFR0 +// +//***************************************************************************** +// Field: [7:4] STATE1 +// +// State1 (T-bit == 1) +// +// 0x0: N/A +// 0x1: N/A +// 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit +// Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit +// instructions can be added using the appropriate instruction attribute, but +// other 32-bit basic instructions cannot.) +// 0x3: Thumb-2 encoding with all Thumb-2 basic instructions +#define CPU_SCS_ID_PFR0_STATE1_W 4 +#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 +#define CPU_SCS_ID_PFR0_STATE1_S 4 + +// Field: [3:0] STATE0 +// +// State0 (T-bit == 0) +// +// 0x0: No ARM encoding +// 0x1: N/A +#define CPU_SCS_ID_PFR0_STATE0_W 4 +#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F +#define CPU_SCS_ID_PFR0_STATE0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_PFR1 +// +//***************************************************************************** +// Field: [11:8] MICROCONTROLLER_PROGRAMMERS_MODEL +// +// Microcontroller programmer's model +// +// 0x0: Not supported +// 0x2: Two-stack support +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_DFR0 +// +//***************************************************************************** +// Field: [23:20] MICROCONTROLLER_DEBUG_MODEL +// +// Microcontroller Debug Model - memory mapped +// +// 0x0: Not supported +// 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_AFR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR2 +// +//***************************************************************************** +// Field: [24] WAIT_FOR_INTERRUPT_STALLING +// +// wait for interrupt stalling +// +// 0x0: Not supported +// 0x1: Wait for interrupt supported +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR4 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_CPACR +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_DHCSR +// +//***************************************************************************** +// Field: [25] S_RESET_ST +// +// Indicates that the core has been reset, or is now being reset, since the +// last time this bit was read. This a sticky bit that clears on read. So, +// reading twice and getting 1 then 0 means it was reset in the past. Reading +// twice and getting 1 both times means that it is being reset now (held in +// reset still). +// When writing to this register, 0 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 +#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_S 25 + +// Field: [24] S_RETIRE_ST +// +// Indicates that an instruction has completed since last read. This is a +// sticky bit that clears on read. This determines if the core is stalled on a +// load/store or fetch. +// When writing to this register, 0 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 +#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 + +// Field: [19] S_LOCKUP +// +// Reads as one if the core is running (not halted) and a lockup condition is +// present. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 +#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_S 19 + +// Field: [18] S_SLEEP +// +// Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must +// use C_HALT to gain control or wait for interrupt to wake-up. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 +#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_S 18 + +// Field: [17] S_HALT +// +// The core is in debug state when this bit is set. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_HALT 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_BITN 17 +#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_S 17 + +// Field: [16] S_REGRDY +// +// Register Read/Write on the Debug Core Register Selector register is +// available. Last transfer is complete. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 +#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_S 16 + +// Field: [5] C_SNAPSTALL +// +// If the core is stalled on a load/store operation the stall ceases and the +// instruction is forced to complete. This enables Halting debug to gain +// control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. +// The core reads S_RETIRE_ST as 0. This indicates that no instruction has +// advanced. This prevents misuse. The bus state is Unpredictable when this is +// used. S_RETIRE_ST can detect core stalls on load/store operations. +#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 +#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 + +// Field: [3] C_MASKINTS +// +// Mask interrupts when stepping or running in halted debug. This masking does +// not affect NMI, fault exceptions and SVC caused by execution of the +// instructions. This bit must only be modified when the processor is halted +// (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released +// (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must +// be separate). Modifying C_MASKINTS while the system is running with halting +// debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable +// behavior. +#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 +#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_S 3 + +// Field: [2] C_STEP +// +// Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. +// Must only be modified when the processor is halted (S_HALT == 1). +// Modifying C_STEP while the system is running with halting debug support +// enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. +#define CPU_SCS_DHCSR_C_STEP 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_BITN 2 +#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_S 2 + +// Field: [1] C_HALT +// +// Halts the core. This bit is set automatically when the core Halts. For +// example Breakpoint. This bit clears on core reset. +#define CPU_SCS_DHCSR_C_HALT 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_BITN 1 +#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_S 1 + +// Field: [0] C_DEBUGEN +// +// Enables debug. This can only be written by AHB-AP and not by the core. It is +// ignored when written by the core, which cannot set or clear it. The core +// must write a 1 to it when writing C_HALT to halt itself. +// The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when +// C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will +// be unknown to software when C_DEBUGEN = 0. +#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 +#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DCRSR +// +//***************************************************************************** +// Field: [16] REGWNR +// +// 1: Write +// 0: Read +#define CPU_SCS_DCRSR_REGWNR 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_BITN 16 +#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_S 16 + +// Field: [4:0] REGSEL +// +// Register select +// +// 0x00: R0 +// 0x01: R1 +// 0x02: R2 +// 0x03: R3 +// 0x04: R4 +// 0x05: R5 +// 0x06: R6 +// 0x07: R7 +// 0x08: R8 +// 0x09: R9 +// 0x0A: R10 +// 0x0B: R11 +// 0x0C: R12 +// 0x0D: Current SP +// 0x0E: LR +// 0x0F: DebugReturnAddress +// 0x10: XPSR/flags, execution state information, and exception number +// 0x11: MSP (Main SP) +// 0x12: PSP (Process SP) +// 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK +#define CPU_SCS_DCRSR_REGSEL_W 5 +#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F +#define CPU_SCS_DCRSR_REGSEL_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DCRDR +// +//***************************************************************************** +// Field: [31:0] DCRDR +// +// This register holds data for reading and writing registers to and from the +// processor. This is the data value written to the register selected by DCRSR. +// When the processor receives a request from DCRSR, this register is read or +// written by the processor using a normal load-store unit operation. If core +// register transfers are not being performed, software-based debug monitors +// can use this register for communication in non-halting debug. This enables +// flags and bits to acknowledge state and indicate if commands have been +// accepted to, replied to, or accepted and replied to. +#define CPU_SCS_DCRDR_DCRDR_W 32 +#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF +#define CPU_SCS_DCRDR_DCRDR_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DEMCR +// +//***************************************************************************** +// Field: [24] TRCENA +// +// This bit must be set to 1 to enable use of the trace and debug blocks: DWT, +// ITM, ETM and TPIU. This enables control of power usage unless tracing is +// required. The application can enable this, for ITM use, or use by a +// debugger. +#define CPU_SCS_DEMCR_TRCENA 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_BITN 24 +#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_S 24 + +// Field: [19] MON_REQ +// +// This enables the monitor to identify how it wakes up. This bit clears on a +// Core Reset. +// +// 0x0: Woken up by debug exception. +// 0x1: Woken up by MON_PEND +#define CPU_SCS_DEMCR_MON_REQ 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_BITN 19 +#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_S 19 + +// Field: [18] MON_STEP +// +// When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. +// This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped +// according to the priority of the monitor and settings of PRIMASK, FAULTMASK, +// or BASEPRI. +#define CPU_SCS_DEMCR_MON_STEP 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_BITN 18 +#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_S 18 + +// Field: [17] MON_PEND +// +// Pend the monitor to activate when priority permits. This can wake up the +// monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for +// Monitor debug. This register does not reset on a system reset. It is only +// reset by a power-on reset. Software in the reset handler or later, or by the +// DAP must enable the debug monitor. +#define CPU_SCS_DEMCR_MON_PEND 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_BITN 17 +#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_S 17 + +// Field: [16] MON_EN +// +// Enable the debug monitor. +// When enabled, the System handler priority register controls its priority +// level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN +// overrides this bit. Vector catching is semi-synchronous. When a matching +// event is seen, a Halt is requested. Because the processor can only halt on +// an instruction boundary, it must wait until the next instruction boundary. +// As a result, it stops on the first instruction of the exception handler. +// However, two special cases exist when a vector catch has triggered: 1. If a +// fault is taken during vectoring, vector read or stack push error, the halt +// occurs on the corresponding fault handler, for the vector error or stack +// push. 2. If a late arriving interrupt comes in during vectoring, it is not +// taken. That is, an implementation that supports the late arrival +// optimization must suppress it in this case. +#define CPU_SCS_DEMCR_MON_EN 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_BITN 16 +#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_S 16 + +// Field: [10] VC_HARDERR +// +// Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 +#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_S 10 + +// Field: [9] VC_INTERR +// +// Debug trap on a fault occurring during an exception entry or return +// sequence. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 +#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_S 9 + +// Field: [8] VC_BUSERR +// +// Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 +#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_S 8 + +// Field: [7] VC_STATERR +// +// Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is +// cleared. +#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 +#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_S 7 + +// Field: [6] VC_CHKERR +// +// Debug trap on Usage Fault enabled checking errors. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 +#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_S 6 + +// Field: [5] VC_NOCPERR +// +// Debug trap on a UsageFault access to a Coprocessor. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 +#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 + +// Field: [4] VC_MMERR +// +// Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is +// cleared. +#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 +#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_S 4 + +// Field: [0] VC_CORERESET +// +// Reset Vector Catch. Halt running system if Core reset occurs. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 +#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STIR +// +//***************************************************************************** +// Field: [8:0] INTID +// +// Interrupt ID field. Writing a value to this bit-field is the same as +// manually pending an interrupt by setting the corresponding interrupt bit in +// an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. +#define CPU_SCS_STIR_INTID_W 9 +#define CPU_SCS_STIR_INTID_M 0x000001FF +#define CPU_SCS_STIR_INTID_S 0 + + +#endif // __CPU_SCS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tiprop.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tiprop.h new file mode 100644 index 0000000..3b011f7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tiprop.h @@ -0,0 +1,83 @@ +/****************************************************************************** +* Filename: hw_cpu_tiprop_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_TIPROP_H__ +#define __HW_CPU_TIPROP_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_TIPROP component +// +//***************************************************************************** +// Internal +#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8 + +// Internal +#define CPU_TIPROP_O_DYN_CG 0x00000FFC + +//***************************************************************************** +// +// Register: CPU_TIPROP_O_TRACECLKMUX +// +//***************************************************************************** +// Field: [0] TRACECLK_N_SWV +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// TRACECLK Internal. Only to be used through TI provided API. +// SWV Internal. Only to be used through TI provided API. +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000 + +//***************************************************************************** +// +// Register: CPU_TIPROP_O_DYN_CG +// +//***************************************************************************** +// Field: [1:0] DYN_CG +// +// Internal. Only to be used through TI provided API. +#define CPU_TIPROP_DYN_CG_DYN_CG_W 2 +#define CPU_TIPROP_DYN_CG_DYN_CG_M 0x00000003 +#define CPU_TIPROP_DYN_CG_DYN_CG_S 0 + + +#endif // __CPU_TIPROP__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tpiu.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tpiu.h new file mode 100644 index 0000000..b91c2e8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tpiu.h @@ -0,0 +1,347 @@ +/****************************************************************************** +* Filename: hw_cpu_tpiu_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_TPIU_H__ +#define __HW_CPU_TPIU_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_TPIU component +// +//***************************************************************************** +// Supported Sync Port Sizes +#define CPU_TPIU_O_SSPSR 0x00000000 + +// Current Sync Port Size +#define CPU_TPIU_O_CSPSR 0x00000004 + +// Async Clock Prescaler +#define CPU_TPIU_O_ACPR 0x00000010 + +// Selected Pin Protocol +#define CPU_TPIU_O_SPPR 0x000000F0 + +// Formatter and Flush Status +#define CPU_TPIU_O_FFSR 0x00000300 + +// Formatter and Flush Control +#define CPU_TPIU_O_FFCR 0x00000304 + +// Formatter Synchronization Counter +#define CPU_TPIU_O_FSCR 0x00000308 + +// Claim Tag Mask +#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 + +// Claim Tag Set +#define CPU_TPIU_O_CLAIMSET 0x00000FA0 + +// Current Claim Tag +#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 + +// Claim Tag Clear +#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 + +// Device ID +#define CPU_TPIU_O_DEVID 0x00000FC8 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_SSPSR +// +//***************************************************************************** +// Field: [3] FOUR +// +// 4-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_FOUR 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_BITN 3 +#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_S 3 + +// Field: [2] THREE +// +// 3-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_THREE 0x00000004 +#define CPU_TPIU_SSPSR_THREE_BITN 2 +#define CPU_TPIU_SSPSR_THREE_M 0x00000004 +#define CPU_TPIU_SSPSR_THREE_S 2 + +// Field: [1] TWO +// +// 2-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_TWO 0x00000002 +#define CPU_TPIU_SSPSR_TWO_BITN 1 +#define CPU_TPIU_SSPSR_TWO_M 0x00000002 +#define CPU_TPIU_SSPSR_TWO_S 1 + +// Field: [0] ONE +// +// 1-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_ONE 0x00000001 +#define CPU_TPIU_SSPSR_ONE_BITN 0 +#define CPU_TPIU_SSPSR_ONE_M 0x00000001 +#define CPU_TPIU_SSPSR_ONE_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CSPSR +// +//***************************************************************************** +// Field: [3] FOUR +// +// 4-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_FOUR 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_BITN 3 +#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_S 3 + +// Field: [2] THREE +// +// 3-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_THREE 0x00000004 +#define CPU_TPIU_CSPSR_THREE_BITN 2 +#define CPU_TPIU_CSPSR_THREE_M 0x00000004 +#define CPU_TPIU_CSPSR_THREE_S 2 + +// Field: [1] TWO +// +// 2-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_TWO 0x00000002 +#define CPU_TPIU_CSPSR_TWO_BITN 1 +#define CPU_TPIU_CSPSR_TWO_M 0x00000002 +#define CPU_TPIU_CSPSR_TWO_S 1 + +// Field: [0] ONE +// +// 1-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_ONE 0x00000001 +#define CPU_TPIU_CSPSR_ONE_BITN 0 +#define CPU_TPIU_CSPSR_ONE_M 0x00000001 +#define CPU_TPIU_CSPSR_ONE_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_ACPR +// +//***************************************************************************** +// Field: [12:0] PRESCALER +// +// Divisor for input trace clock is (PRESCALER + 1). +#define CPU_TPIU_ACPR_PRESCALER_W 13 +#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF +#define CPU_TPIU_ACPR_PRESCALER_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_SPPR +// +//***************************************************************************** +// Field: [1:0] PROTOCOL +// +// Trace output protocol +// ENUMs: +// SWO_NRZ SerialWire Output (NRZ) +// SWO_MANCHESTER SerialWire Output (Manchester). This is the reset +// value. +// TRACEPORT TracePort mode +#define CPU_TPIU_SPPR_PROTOCOL_W 2 +#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 +#define CPU_TPIU_SPPR_PROTOCOL_S 0 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 +#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FFSR +// +//***************************************************************************** +// Field: [3] FTNONSTOP +// +// 0: Formatter can be stopped +// 1: Formatter cannot be stopped +#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 +#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_S 3 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FFCR +// +//***************************************************************************** +// Field: [8] TRIGIN +// +// Indicates that triggers are inserted when a trigger pin is asserted. +#define CPU_TPIU_FFCR_TRIGIN 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_BITN 8 +#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_S 8 + +// Field: [1] ENFCONT +// +// Enable continuous formatting: +// +// 0: Continuous formatting disabled +// 1: Continuous formatting enabled +#define CPU_TPIU_FFCR_ENFCONT 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_BITN 1 +#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_S 1 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FSCR +// +//***************************************************************************** +// Field: [31:0] FSCR +// +// The global synchronization trigger is generated by the Program Counter (PC) +// Sampler block. This means that there is no synchronization counter in the +// TPIU. +#define CPU_TPIU_FSCR_FSCR_W 32 +#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF +#define CPU_TPIU_FSCR_FSCR_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMMASK +// +//***************************************************************************** +// Field: [31:0] CLAIMMASK +// +// This register forms one half of the Claim Tag value. When reading this +// register returns the number of bits that can be set (each bit is considered +// separately): +// +// 0: This claim tag bit is not implemented +// 1: This claim tag bit is not implemented +// +// The behavior when writing to this register is described in CLAIMSET. +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMSET +// +//***************************************************************************** +// Field: [31:0] CLAIMSET +// +// This register forms one half of the Claim Tag value. Writing to this +// location allows individual bits to be set (each bit is considered +// separately): +// +// 0: No effect +// 1: Set this bit in the claim tag +// +// The behavior when reading from this location is described in CLAIMMASK. +#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 +#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMTAG +// +//***************************************************************************** +// Field: [31:0] CLAIMTAG +// +// This register forms one half of the Claim Tag value. Reading this register +// returns the current Claim Tag value. +// Reading CLAIMMASK determines how many bits from this register must be used. +// +// The behavior when writing to this register is described in CLAIMCLR. +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMCLR +// +//***************************************************************************** +// Field: [31:0] CLAIMCLR +// +// This register forms one half of the Claim Tag value. Writing to this +// location enables individual bits to be cleared (each bit is considered +// separately): +// +// 0: No effect +// 1: Clear this bit in the claim tag. +// +// The behavior when reading from this location is described in CLAIMTAG. +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_DEVID +// +//***************************************************************************** +// Field: [31:0] DEVID +// +// This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no +// ETM present. +#define CPU_TPIU_DEVID_DEVID_W 32 +#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF +#define CPU_TPIU_DEVID_DEVID_S 0 + + +#endif // __CPU_TPIU__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_crypto.h new file mode 100644 index 0000000..80bc5fc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_crypto.h @@ -0,0 +1,1914 @@ +/****************************************************************************** +* Filename: hw_crypto_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CRYPTO_H__ +#define __HW_CRYPTO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CRYPTO component +// +//***************************************************************************** +// DMA Channel 0 Control +#define CRYPTO_O_DMACH0CTL 0x00000000 + +// DMA Channel 0 External Address +#define CRYPTO_O_DMACH0EXTADDR 0x00000004 + +// DMA Channel 0 Length +#define CRYPTO_O_DMACH0LEN 0x0000000C + +// DMA Controller Status +#define CRYPTO_O_DMASTAT 0x00000018 + +// DMA Controller Software Reset +#define CRYPTO_O_DMASWRESET 0x0000001C + +// DMA Channel 1 Control +#define CRYPTO_O_DMACH1CTL 0x00000020 + +// DMA Channel 1 External Address +#define CRYPTO_O_DMACH1EXTADDR 0x00000024 + +// DMA Channel 1 Length +#define CRYPTO_O_DMACH1LEN 0x0000002C + +// DMA Controller Master Configuration +#define CRYPTO_O_DMABUSCFG 0x00000078 + +// DMA Controller Port Error +#define CRYPTO_O_DMAPORTERR 0x0000007C + +// DMA Controller Version +#define CRYPTO_O_DMAHWVER 0x000000FC + +// Key Write Area +#define CRYPTO_O_KEYWRITEAREA 0x00000400 + +// Key Written Area Status +#define CRYPTO_O_KEYWRITTENAREA 0x00000404 + +// Key Size +#define CRYPTO_O_KEYSIZE 0x00000408 + +// Key Read Area +#define CRYPTO_O_KEYREADAREA 0x0000040C + +// Clear AES_KEY2/GHASH Key +#define CRYPTO_O_AESKEY20 0x00000500 + +// Clear AES_KEY2/GHASH Key +#define CRYPTO_O_AESKEY21 0x00000504 + +// Clear AES_KEY2/GHASH Key +#define CRYPTO_O_AESKEY22 0x00000508 + +// Clear AES_KEY2/GHASH Key +#define CRYPTO_O_AESKEY23 0x0000050C + +// Clear AES_KEY3 +#define CRYPTO_O_AESKEY30 0x00000510 + +// Clear AES_KEY3 +#define CRYPTO_O_AESKEY31 0x00000514 + +// Clear AES_KEY3 +#define CRYPTO_O_AESKEY32 0x00000518 + +// Clear AES_KEY3 +#define CRYPTO_O_AESKEY33 0x0000051C + +// AES Initialization Vector +#define CRYPTO_O_AESIV0 0x00000540 + +// AES Initialization Vector +#define CRYPTO_O_AESIV1 0x00000544 + +// AES Initialization Vector +#define CRYPTO_O_AESIV2 0x00000548 + +// AES Initialization Vector +#define CRYPTO_O_AESIV3 0x0000054C + +// AES Input/Output Buffer Control +#define CRYPTO_O_AESCTL 0x00000550 + +// Crypto Data Length LSW +#define CRYPTO_O_AESDATALEN0 0x00000554 + +// Crypto Data Length MSW +#define CRYPTO_O_AESDATALEN1 0x00000558 + +// AES Authentication Length +#define CRYPTO_O_AESAUTHLEN 0x0000055C + +// Data Input/Output +#define CRYPTO_O_AESDATAOUT0 0x00000560 + +// AES Data Input/Output 0 +#define CRYPTO_O_AESDATAIN0 0x00000560 + +// AES Data Input/Output 3 +#define CRYPTO_O_AESDATAOUT1 0x00000564 + +// AES Data Input/Output 1 +#define CRYPTO_O_AESDATAIN1 0x00000564 + +// AES Data Input/Output 2 +#define CRYPTO_O_AESDATAOUT2 0x00000568 + +// AES Data Input/Output 2 +#define CRYPTO_O_AESDATAIN2 0x00000568 + +// AES Data Input/Output 3 +#define CRYPTO_O_AESDATAOUT3 0x0000056C + +// Data Input/Output +#define CRYPTO_O_AESDATAIN3 0x0000056C + +// AES Tag Output +#define CRYPTO_O_AESTAGOUT0 0x00000570 + +// AES Tag Output +#define CRYPTO_O_AESTAGOUT1 0x00000574 + +// AES Tag Output +#define CRYPTO_O_AESTAGOUT2 0x00000578 + +// AES Tag Output +#define CRYPTO_O_AESTAGOUT3 0x0000057C + +// Master Algorithm Select +#define CRYPTO_O_ALGSEL 0x00000700 + +// Master Protection Control +#define CRYPTO_O_DMAPROTCTL 0x00000704 + +// Software Reset +#define CRYPTO_O_SWRESET 0x00000740 + +// Control Interrupt Configuration +#define CRYPTO_O_IRQTYPE 0x00000780 + +// Interrupt Enable +#define CRYPTO_O_IRQEN 0x00000784 + +// Interrupt Clear +#define CRYPTO_O_IRQCLR 0x00000788 + +// Interrupt Set +#define CRYPTO_O_IRQSET 0x0000078C + +// Interrupt Status +#define CRYPTO_O_IRQSTAT 0x00000790 + +// CTRL Module Version +#define CRYPTO_O_HWVER 0x000007FC + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0CTL +// +//***************************************************************************** +// Field: [1] PRIO +// +// Channel priority: +// +// A channel with high priority will be served before a channel with low +// priority in cases with simultaneous access requests. If both channels have +// the same priority access of the channels to the external port is arbitrated +// using a Round Robin scheme. +// ENUMs: +// HIGH Priority high +// LOW Priority low +#define CRYPTO_DMACH0CTL_PRIO 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_BITN 1 +#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_S 1 +#define CRYPTO_DMACH0CTL_PRIO_HIGH 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_LOW 0x00000000 + +// Field: [0] EN +// +// DMA Channel 0 Control +// ENUMs: +// EN Channel enabled +// DIS Channel disabled +#define CRYPTO_DMACH0CTL_EN 0x00000001 +#define CRYPTO_DMACH0CTL_EN_BITN 0 +#define CRYPTO_DMACH0CTL_EN_M 0x00000001 +#define CRYPTO_DMACH0CTL_EN_S 0 +#define CRYPTO_DMACH0CTL_EN_EN 0x00000001 +#define CRYPTO_DMACH0CTL_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0EXTADDR +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Channel external address value. +// Holds the last updated external address after being sent to the master +// interface. +#define CRYPTO_DMACH0EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH0EXTADDR_ADDR_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0LEN +// +//***************************************************************************** +// Field: [15:0] LEN +// +// DMA transfer length in bytes. +// During configuration, this register contains the DMA transfer length in +// bytes. During operation, it contains the last updated value of the DMA +// transfer length after being sent to the master interface. +// Note: Writing a non-zero value to this register field starts the transfer if +// the channel is enabled by setting DMACH0CTL.EN. +#define CRYPTO_DMACH0LEN_LEN_W 16 +#define CRYPTO_DMACH0LEN_LEN_M 0x0000FFFF +#define CRYPTO_DMACH0LEN_LEN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMASTAT +// +//***************************************************************************** +// Field: [17] PORT_ERR +// +// Reflects possible transfer errors on the AHB port. +#define CRYPTO_DMASTAT_PORT_ERR 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_BITN 17 +#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_S 17 + +// Field: [1] CH1_ACTIVE +// +// This register field indicates if DMA channel 1 is active or not. +// 0: Not active +// 1: Active +#define CRYPTO_DMASTAT_CH1_ACTIVE 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACTIVE_BITN 1 +#define CRYPTO_DMASTAT_CH1_ACTIVE_M 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACTIVE_S 1 + +// Field: [0] CH0_ACTIVE +// +// This register field indicates if DMA channel 0 is active or not. +// 0: Not active +// 1: Active +#define CRYPTO_DMASTAT_CH0_ACTIVE 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACTIVE_BITN 0 +#define CRYPTO_DMASTAT_CH0_ACTIVE_M 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACTIVE_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMASWRESET +// +//***************************************************************************** +// Field: [0] RESET +// +// Software reset enable +// +// 0: Disable +// 1: Enable (self-cleared to zero). +// +// Note: Completion of the software reset must be checked in DMASTAT.CH0_ACTIVE +// and DMASTAT.CH1_ACTIVE. +#define CRYPTO_DMASWRESET_RESET 0x00000001 +#define CRYPTO_DMASWRESET_RESET_BITN 0 +#define CRYPTO_DMASWRESET_RESET_M 0x00000001 +#define CRYPTO_DMASWRESET_RESET_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1CTL +// +//***************************************************************************** +// Field: [1] PRIO +// +// Channel priority: +// +// A channel with high priority will be served before a channel with low +// priority in cases with simultaneous access requests. If both channels have +// the same priority access of the channels to the external port is arbitrated +// using a Round Robin scheme. +// ENUMs: +// HIGH Priority high +// LOW Priority low +#define CRYPTO_DMACH1CTL_PRIO 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_BITN 1 +#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_S 1 +#define CRYPTO_DMACH1CTL_PRIO_HIGH 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_LOW 0x00000000 + +// Field: [0] EN +// +// Channel enable: +// +// Note: Disabling an active channel will interrupt the DMA operation. The +// ongoing block transfer will be completed, but no new transfers will be +// requested. +// ENUMs: +// EN Channel enabled +// DIS Channel disabled +#define CRYPTO_DMACH1CTL_EN 0x00000001 +#define CRYPTO_DMACH1CTL_EN_BITN 0 +#define CRYPTO_DMACH1CTL_EN_M 0x00000001 +#define CRYPTO_DMACH1CTL_EN_S 0 +#define CRYPTO_DMACH1CTL_EN_EN 0x00000001 +#define CRYPTO_DMACH1CTL_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1EXTADDR +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Channel external address value. +// Holds the last updated external address after being sent to the master +// interface. +#define CRYPTO_DMACH1EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH1EXTADDR_ADDR_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1LEN +// +//***************************************************************************** +// Field: [15:0] LEN +// +// DMA transfer length in bytes. +// During configuration, this register contains the DMA transfer length in +// bytes. During operation, it contains the last updated value of the DMA +// transfer length after being sent to the master interface. +// Note: Writing a non-zero value to this register field starts the transfer if +// the channel is enabled by setting DMACH1CTL.EN. +#define CRYPTO_DMACH1LEN_LEN_W 16 +#define CRYPTO_DMACH1LEN_LEN_M 0x0000FFFF +#define CRYPTO_DMACH1LEN_LEN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMABUSCFG +// +//***************************************************************************** +// Field: [15:12] AHB_MST1_BURST_SIZE +// +// Maximum burst size that can be performed on the AHB bus +// ENUMs: +// 64_BYTE 64 bytes +// 32_BYTE 32 bytes +// 16_BYTE 16 bytes +// 8_BYTE 8 bytes +// 4_BYTE 4 bytes +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 + +// Field: [11] AHB_MST1_IDLE_EN +// +// Idle transfer insertion between consecutive burst transfers on AHB +// ENUMs: +// IDLE Idle transfer insertion enabled +// NO_IDLE Do not insert idle transfers. +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 + +// Field: [10] AHB_MST1_INCR_EN +// +// Burst length type of AHB transfer +// ENUMs: +// SPECIFIED Fixed length bursts or single transfers +// UNSPECIFIED Unspecified length burst transfers +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 + +// Field: [9] AHB_MST1_LOCK_EN +// +// Locked transform on AHB +// ENUMs: +// LOCKED Transfers are locked +// NOT_LOCKED Transfers are not locked +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 + +// Field: [8] AHB_MST1_BIGEND +// +// Endianess for the AHB master +// ENUMs: +// BIG_ENDIAN Big Endian +// LITTLE_ENDIAN Little Endian +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAPORTERR +// +//***************************************************************************** +// Field: [12] AHB_ERR +// +// A 1 indicates that the Crypto peripheral has detected an AHB bus error +#define CRYPTO_DMAPORTERR_AHB_ERR 0x00001000 +#define CRYPTO_DMAPORTERR_AHB_ERR_BITN 12 +#define CRYPTO_DMAPORTERR_AHB_ERR_M 0x00001000 +#define CRYPTO_DMAPORTERR_AHB_ERR_S 12 + +// Field: [9] LAST_CH +// +// Indicates which channel was serviced last (channel 0 or channel 1) by the +// AHB master port. +#define CRYPTO_DMAPORTERR_LAST_CH 0x00000200 +#define CRYPTO_DMAPORTERR_LAST_CH_BITN 9 +#define CRYPTO_DMAPORTERR_LAST_CH_M 0x00000200 +#define CRYPTO_DMAPORTERR_LAST_CH_S 9 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAHWVER +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VER +// +// Major version number +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_W 4 +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_M 0x0F000000 +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_S 24 + +// Field: [23:20] HW_MINOR_VER +// +// Minor version number +#define CRYPTO_DMAHWVER_HW_MINOR_VER_W 4 +#define CRYPTO_DMAHWVER_HW_MINOR_VER_M 0x00F00000 +#define CRYPTO_DMAHWVER_HW_MINOR_VER_S 20 + +// Field: [19:16] HW_PATCH_LVL +// +// Patch level. +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_W 4 +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_M 0x000F0000 +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_S 16 + +// Field: [15:8] VER_NUM_COMPL +// +// Bit-by-bit complement of the VER_NUM field bits. +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_W 8 +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_M 0x0000FF00 +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_S 8 + +// Field: [7:0] VER_NUM +// +// Version number of the DMA Controller (209) +#define CRYPTO_DMAHWVER_VER_NUM_W 8 +#define CRYPTO_DMAHWVER_VER_NUM_M 0x000000FF +#define CRYPTO_DMAHWVER_VER_NUM_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYWRITEAREA +// +//***************************************************************************** +// Field: [7] RAM_AREA7 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 + +// Field: [6] RAM_AREA6 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 + +// Field: [5] RAM_AREA5 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 + +// Field: [4] RAM_AREA4 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 + +// Field: [3] RAM_AREA3 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 + +// Field: [2] RAM_AREA2 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 + +// Field: [1] RAM_AREA1 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 + +// Field: [0] RAM_AREA0 +// +// Represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written. +// +// Writing to multiple RAM locations is only possible when the selected RAM +// areas are sequential. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYWRITTENAREA +// +//***************************************************************************** +// Field: [7] RAM_AREA_WRITTEN7 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 + +// Field: [6] RAM_AREA_WRITTEN6 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 + +// Field: [5] RAM_AREA_WRITTEN5 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 + +// Field: [4] RAM_AREA_WRITTEN4 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 + +// Field: [3] RAM_AREA_WRITTEN3 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 + +// Field: [2] RAM_AREA_WRITTEN2 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 + +// Field: [1] RAM_AREA_WRITTEN1 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 + +// Field: [0] RAM_AREA_WRITTEN0 +// +// On read this bit returns the key area written status. +// +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_WRITTEN 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_NOT_WRITTEN 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYSIZE +// +//***************************************************************************** +// Field: [1:0] SIZE +// +// Key size +// +// When writing to this register, KEYWRITTENAREA will be reset. +// +// Note: For the Crypto peripheral this field is fixed to 128 bits. For +// software compatibility KEYWRITTENAREA will be reset when writing to this +// register. +// ENUMs: +// 256_BIT Not supported +// 192_BIT Not supported +// 128_BIT 128 bits +#define CRYPTO_KEYSIZE_SIZE_W 2 +#define CRYPTO_KEYSIZE_SIZE_M 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_S 0 +#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 +#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYREADAREA +// +//***************************************************************************** +// Field: [31] BUSY +// +// Key store operation busy status flag (read only) +// +// 0: operation is completed. +// 1: operation is not completed and the key store is busy. +#define CRYPTO_KEYREADAREA_BUSY 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_BITN 31 +#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_S 31 + +// Field: [3:0] RAM_AREA +// +// Selects the area of the key store RAM from where the key needs to be read +// that will be written to the AES engine. +// +// Only RAM areas that contain valid written keys can be selected. +// ENUMs: +// NO_RAM No RAM +// RAM_AREA7 RAM Area 7 +// RAM_AREA6 RAM Area 6 +// RAM_AREA5 RAM Area 5 +// RAM_AREA4 RAM Area 4 +// RAM_AREA3 RAM Area 3 +// RAM_AREA2 RAM Area 2 +// RAM_AREA1 RAM Area 1 +// RAM_AREA0 RAM Area 0 +#define CRYPTO_KEYREADAREA_RAM_AREA_W 4 +#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F +#define CRYPTO_KEYREADAREA_RAM_AREA_S 0 +#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY20 +// +//***************************************************************************** +// Field: [31:0] KEY2 +// +// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register array. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY20_KEY2_W 32 +#define CRYPTO_AESKEY20_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY20_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY21 +// +//***************************************************************************** +// Field: [31:0] KEY2 +// +// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register array. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY21_KEY2_W 32 +#define CRYPTO_AESKEY21_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY21_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY22 +// +//***************************************************************************** +// Field: [31:0] KEY2 +// +// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register array. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY22_KEY2_W 32 +#define CRYPTO_AESKEY22_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY22_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY23 +// +//***************************************************************************** +// Field: [31:0] KEY2 +// +// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register array. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY23_KEY2_W 32 +#define CRYPTO_AESKEY23_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY23_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY30 +// +//***************************************************************************** +// Field: [31:0] KEY3 +// +// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register arrary. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY30_KEY3_W 32 +#define CRYPTO_AESKEY30_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY30_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY31 +// +//***************************************************************************** +// Field: [31:0] KEY3 +// +// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register arrary. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY31_KEY3_W 32 +#define CRYPTO_AESKEY31_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY31_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY32 +// +//***************************************************************************** +// Field: [31:0] KEY3 +// +// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register arrary. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY32_KEY3_W 32 +#define CRYPTO_AESKEY32_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY32_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY33 +// +//***************************************************************************** +// Field: [31:0] KEY3 +// +// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, +// 96 ordered from the LSW entry of this 4-deep register arrary. +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESKEY33_KEY3_W 32 +#define CRYPTO_AESKEY33_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY33_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV0 +// +//***************************************************************************** +// Field: [31:0] IV +// +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESIV0_IV_W 32 +#define CRYPTO_AESIV0_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV0_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV1 +// +//***************************************************************************** +// Field: [31:0] IV +// +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESIV1_IV_W 32 +#define CRYPTO_AESIV1_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV1_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV2 +// +//***************************************************************************** +// Field: [31:0] IV +// +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESIV2_IV_W 32 +#define CRYPTO_AESIV2_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV2_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV3 +// +//***************************************************************************** +// Field: [31:0] IV +// +// The interpretation of this field depends on the crypto operation mode. +#define CRYPTO_AESIV3_IV_W 32 +#define CRYPTO_AESIV3_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV3_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESCTL +// +//***************************************************************************** +// Field: [31] CONTEXT_RDY +// +// If 1, this status bit indicates that the context data registers can be +// overwritten and the Host is permitted to write the next context. Writing a +// context means writing either a mode, the crypto length or +// AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length registers +#define CRYPTO_AESCTL_CONTEXT_RDY 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_RDY_BITN 31 +#define CRYPTO_AESCTL_CONTEXT_RDY_M 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_RDY_S 31 + +// Field: [30] SAVED_CONTEXT_RDY +// +// If read as 1, this status bit indicates that an AES authentication TAG +// and/or IV block(s) is/are available for the Host to retrieve. This bit is +// only asserted if SAVE_CONTEXT is set to 1. The bit is mutually exclusive +// with CONTEXT_RDY. +// +// Writing 1 clears the bit to zero, indicating the Crypto peripheral can start +// its next operation. This bit is also cleared when the 4th word of the output +// TAG and/or IV is read. +// +// Note: All other mode bit writes will be ignored when this mode bit is +// written with 1. +// +// Note: This bit is controlled automatically by the Crypto peripheral for TAG +// read DMA operations. +// +// For typical use, this bit does NOT need to be written, but is used for +// status reading only. In this case, this status bit is automatically +// maintained by the Crypto peripheral. +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 + +// Field: [29] SAVE_CONTEXT +// +// IV must be read before the AES engine can start a new operation. +#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 +#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 + +// Field: [24:22] CCM_M +// +// Defines M that indicates the length of the authentication field for CCM +// operations; the authentication field length equals two times the value of +// CCM_M plus one. +// Note: The Crypto peripheral always returns a 128-bit authentication field, +// of which the M least significant bytes are valid. All values are supported. +#define CRYPTO_AESCTL_CCM_M_W 3 +#define CRYPTO_AESCTL_CCM_M_M 0x01C00000 +#define CRYPTO_AESCTL_CCM_M_S 22 + +// Field: [21:19] CCM_L +// +// Defines L that indicates the width of the length field for CCM operations; +// the length field in bytes equals the value of CMM_L plus one. All values are +// supported. +#define CRYPTO_AESCTL_CCM_L_W 3 +#define CRYPTO_AESCTL_CCM_L_M 0x00380000 +#define CRYPTO_AESCTL_CCM_L_S 19 + +// Field: [18] CCM +// +// AES-CCM mode enable. +// AES-CCM is a combined mode, using AES for both authentication and +// encryption. +// Note: Selecting AES-CCM mode requires writing of AESDATALEN1.LEN_MSW and +// AESDATALEN0.LEN_LSW after all other registers. +// Note: The CTR mode bit in this register must also be set to 1 to enable +// AES-CTR; selecting other AES modes than CTR mode is invalid. +#define CRYPTO_AESCTL_CCM 0x00040000 +#define CRYPTO_AESCTL_CCM_BITN 18 +#define CRYPTO_AESCTL_CCM_M 0x00040000 +#define CRYPTO_AESCTL_CCM_S 18 + +// Field: [15] CBC_MAC +// +// MAC mode enable. +// The DIR bit must be set to 1 for this mode. +// Selecting this mode requires writing the AESDATALEN1.LEN_MSW and +// AESDATALEN0.LEN_LSW registers after all other registers. +#define CRYPTO_AESCTL_CBC_MAC 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_BITN 15 +#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_S 15 + +// Field: [8:7] CTR_WIDTH +// +// Specifies the counter width for AES-CTR mode +// ENUMs: +// 128_BIT 128 bits +// 96_BIT 96 bits +// 64_BIT 64 bits +// 32_BIT 32 bits +#define CRYPTO_AESCTL_CTR_WIDTH_W 2 +#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_S 7 +#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 +#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 +#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 + +// Field: [6] CTR +// +// AES-CTR mode enable +// This bit must also be set for CCM, when encryption/decryption is required. +#define CRYPTO_AESCTL_CTR 0x00000040 +#define CRYPTO_AESCTL_CTR_BITN 6 +#define CRYPTO_AESCTL_CTR_M 0x00000040 +#define CRYPTO_AESCTL_CTR_S 6 + +// Field: [5] CBC +// +// CBC mode enable +#define CRYPTO_AESCTL_CBC 0x00000020 +#define CRYPTO_AESCTL_CBC_BITN 5 +#define CRYPTO_AESCTL_CBC_M 0x00000020 +#define CRYPTO_AESCTL_CBC_S 5 + +// Field: [4:3] KEY_SIZE +// +// This field specifies the key size. +// The key size is automatically configured when a new key is loaded via the +// key store module. +// 00 = N/A - reserved +// 01 = 128 bits +// 10 = N/A - reserved +// 11 = N/A - reserved +// For the Crypto peripheral this field is fixed to 128 bits. +#define CRYPTO_AESCTL_KEY_SIZE_W 2 +#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 +#define CRYPTO_AESCTL_KEY_SIZE_S 3 + +// Field: [2] DIR +// +// Direction. +// 0 : Decrypt operation is performed. +// 1 : Encrypt operation is performed. +// +// This bit must be written with a 1 when CBC-MAC is selected. +#define CRYPTO_AESCTL_DIR 0x00000004 +#define CRYPTO_AESCTL_DIR_BITN 2 +#define CRYPTO_AESCTL_DIR_M 0x00000004 +#define CRYPTO_AESCTL_DIR_S 2 + +// Field: [1] INPUT_RDY +// +// If read as 1, this status bit indicates that the 16-byte AES input buffer is +// empty. The Host is permitted to write the next block of data. +// +// Writing a 0 clears the bit to zero and indicates that the AES engine can use +// the provided input data block. +// +// Writing a 1 to this bit will be ignored. +// +// Note: For DMA operations, this bit is automatically controlled by the Crypto +// peripheral. +// After reset, this bit is 0. After writing a context (note 1), this bit will +// become 1. +// +// For typical use, this bit does NOT need to be written, but is used for +// status reading only. In this case, this status bit is automatically +// maintained by the Crypto peripheral. +#define CRYPTO_AESCTL_INPUT_RDY 0x00000002 +#define CRYPTO_AESCTL_INPUT_RDY_BITN 1 +#define CRYPTO_AESCTL_INPUT_RDY_M 0x00000002 +#define CRYPTO_AESCTL_INPUT_RDY_S 1 + +// Field: [0] OUTPUT_RDY +// +// If read as 1, this status bit indicates that an AES output block is +// available to be retrieved by the Host. +// +// Writing a 0 clears the bit to zero and indicates that output data is read by +// the Host. The AES engine can provide a next output data block. +// +// Writing a 1 to this bit will be ignored. +// +// Note: For DMA operations, this bit is automatically controlled by the Crypto +// peripheral. +// +// For typical use, this bit does NOT need to be written, but is used for +// status reading only. In this case, this status bit is automatically +// maintained by the Crypto peripheral. +#define CRYPTO_AESCTL_OUTPUT_RDY 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_RDY_BITN 0 +#define CRYPTO_AESCTL_OUTPUT_RDY_M 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_RDY_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATALEN0 +// +//***************************************************************************** +// Field: [31:0] LEN_LSW +// +// Used to write the Length values to the Crypto peripheral. +// +// This register contains bits [31:0] of the combined data length. +#define CRYPTO_AESDATALEN0_LEN_LSW_W 32 +#define CRYPTO_AESDATALEN0_LEN_LSW_M 0xFFFFFFFF +#define CRYPTO_AESDATALEN0_LEN_LSW_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATALEN1 +// +//***************************************************************************** +// Field: [28:0] LEN_MSW +// +// Bits [60:32] of the combined data length. +// +// Bits [60:0] of the crypto length registers AESDATALEN1 and AESDATALEN0 store +// the cryptographic data length in bytes for all modes. Once processing with +// this context is started, this length decrements to zero. Data lengths up to +// (2^61 - 1) bytes are allowed. +// For GCM, any value up to 2^36 - 32 bytes can be used. This is because a +// 32-bit counter mode is used; the maximum number of 128-bit blocks is 2^32 - +// 2, resulting in a maximum number of bytes of 2^36 - 32. +// Writing to this register triggers the engine to start using this context. +// This is valid for all modes except GCM and CCM. +// Note: For the combined modes (GCM and CCM), this length does not include the +// authentication only data; the authentication length is specified in the +// AESAUTHLEN.LEN. +// All modes must have a length > 0. For the combined modes, it is allowed to +// have one of the lengths equal to zero. +// For the basic encryption modes (ECB/CBC/CTR) it is allowed to program zero +// to the length field; in that case the length is assumed infinite. +// All data must be byte (8-bit) aligned for stream cipher modes; bit aligned +// data streams are not supported by the Crypto peripheral. For block cipher +// modes, the data length must be programmed in multiples of the block cipher +// size, 16 bytes. +#define CRYPTO_AESDATALEN1_LEN_MSW_W 29 +#define CRYPTO_AESDATALEN1_LEN_MSW_M 0x1FFFFFFF +#define CRYPTO_AESDATALEN1_LEN_MSW_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESAUTHLEN +// +//***************************************************************************** +// Field: [31:0] LEN +// +// Authentication data length in bytes for combined mode, CCM only. +// Supported AAD-lengths for CCM are from 0 to (216 - 28) bytes. Once +// processing with this context is started, this length decrements to zero. +// Writing this register triggers the engine to start using this context for +// CCM. +#define CRYPTO_AESAUTHLEN_LEN_W 32 +#define CRYPTO_AESAUTHLEN_LEN_M 0xFFFFFFFF +#define CRYPTO_AESAUTHLEN_LEN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT0 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data register 0 for output block data from the Crypto peripheral. +// These bits = AES Output Data[31:0] of {127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must +// be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT0_DATA_W 32 +#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT0_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN0 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for input block data to the Crypto peripheral. +// These bits = AES Input Data[31:0] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host write operation, these registers must be written with the 128-bit +// input block for the next AES operation. Writing at a word-aligned offset +// within this address range will store the word (4 bytes) of data into the +// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data +// input buffer. This buffer is used for the next AES operation. If the last +// data block is not completely filled with valid data (see notes below), it is +// allowed to write only the words with valid data. Next AES operation is +// triggered by writing to AESCTL.INPUT_RDY. +// +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. +// For GCM/CCM, the last block of both AAD and message data may contain less +// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically +// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and +// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is +// ignored. +#define CRYPTO_AESDATAIN0_DATA_W 32 +#define CRYPTO_AESDATAIN0_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN0_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT1 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for output block data from the Crypto peripheral. +// These bits = AES Output Data[63:32] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must +// be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT1_DATA_W 32 +#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT1_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN1 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for input block data to the Crypto peripheral. +// These bits = AES Input Data[63:32] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host write operation, these registers must be written with the 128-bit +// input block for the next AES operation. Writing at a word-aligned offset +// within this address range will store the word (4 bytes) of data into the +// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data +// input buffer. This buffer is used for the next AES operation. If the last +// data block is not completely filled with valid data (see notes below), it is +// allowed to write only the words with valid data. Next AES operation is +// triggered by writing to AESCTL.INPUT_RDY. +// +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. +// For GCM/CCM, the last block of both AAD and message data may contain less +// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically +// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and +// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is +// ignored. +#define CRYPTO_AESDATAIN1_DATA_W 32 +#define CRYPTO_AESDATAIN1_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN1_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT2 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for output block data from the Crypto peripheral. +// These bits = AES Output Data[95:64] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must +// be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT2_DATA_W 32 +#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT2_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN2 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for input block data to the Crypto peripheral. +// These bits = AES Input Data[95:64] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host write operation, these registers must be written with the 128-bit +// input block for the next AES operation. Writing at a word-aligned offset +// within this address range will store the word (4 bytes) of data into the +// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data +// input buffer. This buffer is used for the next AES operation. If the last +// data block is not completely filled with valid data (see notes below), it is +// allowed to write only the words with valid data. Next AES operation is +// triggered by writing to AESCTL.INPUT_RDY. +// +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. +// For GCM/CCM, the last block of both AAD and message data may contain less +// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically +// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and +// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is +// ignored. +#define CRYPTO_AESDATAIN2_DATA_W 32 +#define CRYPTO_AESDATAIN2_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN2_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT3 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for output block data from the Crypto peripheral. +// These bits = AES Output Data[127:96] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must +// be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT3_DATA_W 32 +#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT3_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN3 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data registers for input block data to the Crypto peripheral. +// These bits = AES Input Data[127:96] of [127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host write operation, these registers must be written with the 128-bit +// input block for the next AES operation. Writing at a word-aligned offset +// within this address range will store the word (4 bytes) of data into the +// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data +// input buffer. This buffer is used for the next AES operation. If the last +// data block is not completely filled with valid data (see notes below), it is +// allowed to write only the words with valid data. Next AES operation is +// triggered by writing to AESCTL.INPUT_RDY. +// +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. +// For GCM/CCM, the last block of both AAD and message data may contain less +// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically +// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and +// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is +// ignored. +#define CRYPTO_AESDATAIN3_DATA_W 32 +#define CRYPTO_AESDATAIN3_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN3_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT0 +// +//***************************************************************************** +// Field: [31:0] TAG +// +// This register contains the authentication TAG for the combined and +// authentication-only modes. +#define CRYPTO_AESTAGOUT0_TAG_W 32 +#define CRYPTO_AESTAGOUT0_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT0_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT1 +// +//***************************************************************************** +// Field: [31:0] TAG +// +// This register contains the authentication TAG for the combined and +// authentication-only modes. +#define CRYPTO_AESTAGOUT1_TAG_W 32 +#define CRYPTO_AESTAGOUT1_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT1_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT2 +// +//***************************************************************************** +// Field: [31:0] TAG +// +// This register contains the authentication TAG for the combined and +// authentication-only modes. +#define CRYPTO_AESTAGOUT2_TAG_W 32 +#define CRYPTO_AESTAGOUT2_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT2_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT3 +// +//***************************************************************************** +// Field: [31:0] TAG +// +// This register contains the authentication TAG for the combined and +// authentication-only modes. +#define CRYPTO_AESTAGOUT3_TAG_W 32 +#define CRYPTO_AESTAGOUT3_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT3_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_ALGSEL +// +//***************************************************************************** +// Field: [31] TAG +// +// If this bit is cleared to 0, the DMA operation involves only data. +// If this bit is set, the DMA operation includes a TAG (Authentication Result +// / Digest). +#define CRYPTO_ALGSEL_TAG 0x80000000 +#define CRYPTO_ALGSEL_TAG_BITN 31 +#define CRYPTO_ALGSEL_TAG_M 0x80000000 +#define CRYPTO_ALGSEL_TAG_S 31 + +// Field: [1] AES +// +// If set to 1, the AES data is loaded via DMA +// Both Read and Write maximum transfer size to DMA engine is set to 16 bytes +#define CRYPTO_ALGSEL_AES 0x00000002 +#define CRYPTO_ALGSEL_AES_BITN 1 +#define CRYPTO_ALGSEL_AES_M 0x00000002 +#define CRYPTO_ALGSEL_AES_S 1 + +// Field: [0] KEY_STORE +// +// If set to 1, selects the Key Store to be loaded via DMA. +// The maximum transfer size to DMA engine is set to 32 bytes (however +// transfers of 16, 24 and 32 bytes are allowed) +#define CRYPTO_ALGSEL_KEY_STORE 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_BITN 0 +#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAPROTCTL +// +//***************************************************************************** +// Field: [0] EN +// +// Select AHB transfer protection control for DMA transfers using the key store +// area as destination. +// 0 : transfers use 'USER' type access. +// 1 : transfers use 'PRIVILEGED' type access. +#define CRYPTO_DMAPROTCTL_EN 0x00000001 +#define CRYPTO_DMAPROTCTL_EN_BITN 0 +#define CRYPTO_DMAPROTCTL_EN_M 0x00000001 +#define CRYPTO_DMAPROTCTL_EN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_SWRESET +// +//***************************************************************************** +// Field: [0] RESET +// +// If this bit is set to 1, the following modules are reset: +// - Master control internal state is reset. That includes interrupt, error +// status register and result available interrupt generation FSM. +// - Key store module state is reset. That includes clearing the Written Area +// flags; therefore the keys must be reloaded to the key store module. +// Writing 0 has no effect. +// The bit is self cleared after executing the reset. +#define CRYPTO_SWRESET_RESET 0x00000001 +#define CRYPTO_SWRESET_RESET_BITN 0 +#define CRYPTO_SWRESET_RESET_M 0x00000001 +#define CRYPTO_SWRESET_RESET_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQTYPE +// +//***************************************************************************** +// Field: [0] LEVEL +// +// If this bit is 0, the interrupt output is a pulse. +// If this bit is set to 1, the interrupt is a level interrupt that must be +// cleared by writing the interrupt clear register. +// This bit is applicable for both interrupt output signals. +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_BITN 0 +#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQEN +// +//***************************************************************************** +// Field: [1] DMA_IN_DONE +// +// This bit enables IRQSTAT.DMA_IN_DONE as source for IRQ. +#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// This bit enables IRQSTAT.RESULT_AVAIL as source for IRQ. +#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQCLR +// +//***************************************************************************** +// Field: [31] DMA_BUS_ERR +// +// If 1 is written to this bit, IRQSTAT.DMA_BUS_ERR is cleared. +#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 + +// Field: [30] KEY_ST_WR_ERR +// +// If 1 is written to this bit, IRQSTAT.KEY_ST_WR_ERR is cleared. +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 + +// Field: [29] KEY_ST_RD_ERR +// +// If 1 is written to this bit, IRQSTAT.KEY_ST_RD_ERR is cleared. +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 + +// Field: [1] DMA_IN_DONE +// +// If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared. +#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared. +#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQSET +// +//***************************************************************************** +// Field: [1] DMA_IN_DONE +// +// If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set. +// Writing 0 has no effect. +#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set. +// Writing 0 has no effect. +#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQSTAT +// +//***************************************************************************** +// Field: [31] DMA_BUS_ERR +// +// This bit is set when a DMA bus error is detected during a DMA operation. The +// value of this register is held until it is cleared via IRQCLR.DMA_BUS_ERR +// Note: This error is asserted if an error is detected on the AHB master +// interface during a DMA operation. +// Note: This is not an interrupt source. +#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 + +// Field: [30] KEY_ST_WR_ERR +// +// This bit is set when a write error is detected during the DMA write +// operation to the key store memory. The value of this register is held until +// it is cleared via IRQCLR.KEY_ST_WR_ERR +// Note: This error is asserted if a DMA operation does not cover a full key +// area or more areas are written than expected. +// Note: This is not an interrupt source. +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 + +// Field: [29] KEY_ST_RD_ERR +// +// This bit will be set when a read error is detected during the read of a key +// from the key store, while copying it to the AES engine. The value of this +// register is held until it is cleared via IRQCLR.KEY_ST_RD_ERR. +// Note: This error is asserted if a key location is selected in the key store +// that is not available. +// Note: This is not an interrupt source. +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 + +// Field: [1] DMA_IN_DONE +// +// This bit returns the status of DMA data in done interrupt. +#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// This bit is set high when the Crypto peripheral has a result available. +#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HWVER +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VER +// +// Major version number +#define CRYPTO_HWVER_HW_MAJOR_VER_W 4 +#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 +#define CRYPTO_HWVER_HW_MAJOR_VER_S 24 + +// Field: [23:20] HW_MINOR_VER +// +// Minor version number +#define CRYPTO_HWVER_HW_MINOR_VER_W 4 +#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 +#define CRYPTO_HWVER_HW_MINOR_VER_S 20 + +// Field: [19:16] HW_PATCH_LVL +// +// Patch level, starts at 0 at first delivery of this version. +#define CRYPTO_HWVER_HW_PATCH_LVL_W 4 +#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 +#define CRYPTO_HWVER_HW_PATCH_LVL_S 16 + +// Field: [15:8] VER_NUM_COMPL +// +// These bits simply contain the complement of VER_NUM (0x87), used by a driver +// to ascertain that the Crypto peripheral register is indeed read. +#define CRYPTO_HWVER_VER_NUM_COMPL_W 8 +#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 +#define CRYPTO_HWVER_VER_NUM_COMPL_S 8 + +// Field: [7:0] VER_NUM +// +// The version number for the Crypto peripheral, this field contains the value +// 120 (decimal) or 0x78. +#define CRYPTO_HWVER_VER_NUM_W 8 +#define CRYPTO_HWVER_VER_NUM_M 0x000000FF +#define CRYPTO_HWVER_VER_NUM_S 0 + + +#endif // __CRYPTO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi.h new file mode 100644 index 0000000..a83653f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi.h @@ -0,0 +1,197 @@ +/****************************************************************************** +* Filename: hw_ddi.h +* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) +* Revision: 49096 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_DDI_H__ +#define __HW_DDI_H__ + +//***************************************************************************** +// +// This file contains macros for controlling the DDI master and +// accessing DDI Slave registers via the DDI Master. +// There are 3 categories of macros in this file: +// - macros that provide an offset to a register +// located within the DDI Master itself. +// - macros that define bits or bitfields +// within the DDI Master Registers. +// - macros that provide an "instruction offset" +// that are used when accessing a DDI Slave. +// +// The macros that that provide DDI Master register offsets and +// define bits and bitfields for those registers are the typical +// macros that appear in most hw_.h header files. In +// the following example DDI_O_CFG is a macro for a +// register offset and DDI_CFG_WAITFORACK is a macro for +// a bit in that register. This example code will set the WAITFORACK +// bit in register DDI_O_CFG of the DDI Master. (Note: this +// access the Master not the Slave). +// +// HWREG(AUX_OSCDDI_BASE + DDI_O_CFG) |= DDI_CFG_WAITFORACK; +// +// +// The "instruction offset" macros are used to pass an instruction to +// the DDI Master when accessing DDI slave registers. These macros are +// only used when accessing DDI Slave Registers. (Remember DDI +// Master Registers are accessed normally). +// +// The instructions supported when accessing a DDI Slave Regsiter follow: +// - Direct Access to a DDI Slave register. I.e. read or +// write the register. +// - Set the specified bits in a DDI Slave register. +// - Clear the specified bits in a DDI Slave register. +// - Mask write of 4 bits to the a DDI Slave register. +// - Mask write of 8 bits to the a DDI Slave register. +// - Mask write of 16 bits to the a DDI Slave register. +// +// Note: only the "Direct Access" offset should be used when reading +// a DDI Slave register. Only 8- and 16-bit reads are supported. +// +// The generic format of using this marcos for a read follows: +// // read low 16-bits in DDI_SLAVE_OFF +// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR); +// +// // read high 16-bits in DDI_SLAVE_OFF +// // add 2 for data[31:16] +// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_DIR); + +// // read data[31:24] byte in DDI_SLAVE_OFF +// // add 3 for data[31:24] +// myuchar = HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 3 + DDI_O_DIR); +// +// Notes: In the above example: +// - DDI_MASTER_BASE is the base address of the DDI Master defined +// in the hw_memmap.h header file. +// - DDI_SLAVE_OFF is the DDI Slave offset defined in the +// hw_.h header file (e.g. hw_osc_top.h for the oscsc +// oscillator modules. +// - DDI_O_DIR is the "instruction offset" macro defined in this +// file that specifies the Direct Access instruction. +// +// Writes can use any of the "instruction macros". +// The following examples do a "direct write" to DDI Slave register +// DDI_SLAVE_OFF using different size operands: +// +// // ---------- DIRECT WRITES ---------- +// // Write 32-bits aligned +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x12345678; + +// // Write 16-bits aligned to high 16-bits then low 16-bits +// // Add 2 to get to high 16-bits. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0xabcd; +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0xef01; +// +// // Write each byte at DDI_SLAVE_OFF, one at a time. +// // Add 1,2,or 3 to get to bytes 1,2, or 3. +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x33; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 1) = 0x44; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0x55; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 3) = 0x66; +// +// // ---------- SET/CLR ---------- +// The set and clear functions behave similarly to eachother. Each +// can be performed on an 8-, 16-, or 32-bit operand. +// Examples follow: +// // Set all odd bits in a 32-bit words +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_SET) = 0xaaaaaaaa; +// +// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_CLR) = 0x00ff0000; +// +// // Set even bits in byte 2 (data[23:16]) using 8-bit operand +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_CLR) = 0x55; +// +// // ---------- MASKED WRITES ---------- +// The mask writes are a bit different. They operate on nibbles, +// bytes, and 16-bit elements. Two operands are required; a 'mask' +// and 'data'; The operands are concatenated and written to the master. +// e.g. the mask and data are combined as follows for a 16 bit masked +// write: +// (mask << 16) | data; +// Examples follow: +// +// // Write 5555 to low 16-bits of DDI_SLAVE_OFF register +// // a long write is needed (32-bits). +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xffff5555; + +// // Write 1AA to data bits 24:16 in high 16-bits of DDI_SLAVE_OFF register +// // Note add 4 for high 16-bits at DDI_SLAVE_OFF; mask is 1ff! +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 4) = 0x01ff01aa; +// +// // Do an 8 bit masked write of 00 to low byte of register (data[7:0]). +// // a short write is needed (16-bits). +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xff00; +// +// // Do an 8 bit masked write of 11 to byte 1 of register (data[15:8]). +// // add 2 to get to byte 1. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 2) = 0xff11; +// +// // Do an 8 bit masked write of 33 to high byte of register (data[31:24]). +// // add 6 to get to byte 3. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 6) = 0xff33; +// +// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). +// // Byte write is needed. +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xf7; +// +// // Do an 4 bit masked write of 4 to data[7:4]). +// // Add 1 for next nibble +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 1) = 0xf4; +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the DDI master instruction offsets. +// +//***************************************************************************** +#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction +#define DDI_O_SET 0x00000040 // Offset for 'Set' instruction. +#define DDI_O_CLR 0x00000080 // Offset for 'Clear' instruction. +#define DDI_O_MASK4B 0x00000100 // Offset for 4-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 7:4 are mask. Bits 3:0 are data. + // Requires 'byte' write. +#define DDI_O_MASK8B 0x00000180 // Offset for 8-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 15:8 are mask. Bits 7:0 are data. + // Requires 'short' write. +#define DDI_O_MASK16B 0x00000200 // Offset for 16-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 31:16 are mask. Bits 15:0 are data. + // Requires 'long' write. + + + +#endif // __HW_DDI_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi_0_osc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi_0_osc.h new file mode 100644 index 0000000..9363ec1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi_0_osc.h @@ -0,0 +1,1071 @@ +/****************************************************************************** +* Filename: hw_ddi_0_osc_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_DDI_0_OSC_H__ +#define __HW_DDI_0_OSC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// DDI_0_OSC component +// +//***************************************************************************** +// Control 0 +#define DDI_0_OSC_O_CTL0 0x00000000 + +// Control 1 +#define DDI_0_OSC_O_CTL1 0x00000004 + +// RADC External Configuration +#define DDI_0_OSC_O_RADCEXTCFG 0x00000008 + +// Amplitude Compensation Control +#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C + +// Amplitude Compensation Threshold 1 +#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 + +// Amplitude Compensation Threshold 2 +#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 + +// Analog Bypass Values 1 +#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 + +// Internal +#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C + +// Analog Test Control +#define DDI_0_OSC_O_ATESTCTL 0x00000020 + +// ADC Doubler Nanoamp Control +#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 + +// XOSCHF Control +#define DDI_0_OSC_O_XOSCHFCTL 0x00000028 + +// Low Frequency Oscillator Control +#define DDI_0_OSC_O_LFOSCCTL 0x0000002C + +// RCOSCHF Control +#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 + +// Status 0 +#define DDI_0_OSC_O_STAT0 0x00000034 + +// Status 1 +#define DDI_0_OSC_O_STAT1 0x00000038 + +// Status 2 +#define DDI_0_OSC_O_STAT2 0x0000003C + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_CTL0 +// +//***************************************************************************** +// Field: [31] XTAL_IS_24M +// +// Set based on the accurate high frequency XTAL. +// ENUMs: +// 24M Internal. Only to be used through TI provided API. +// 48M Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 + +// Field: [29] BYPASS_XOSC_LF_CLK_QUAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 + +// Field: [28] BYPASS_RCOSC_LF_CLK_QUAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 + +// Field: [27:26] DOUBLER_START_DURATION +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 + +// Field: [25] DOUBLER_RESET_DURATION +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 + +// Field: [22] FORCE_KICKSTART_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN 0x00400000 +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_M 0x00400000 +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_S 22 + +// Field: [16] ALLOW_SCLK_HF_SWITCHING +// +// 0: Default - Switching of HF clock source is disabled . +// 1: Allows switching of sclk_hf source. +// +// Provided to prevent switching of the SCLK_HF source when running from flash +// (a long period during switching could corrupt flash). When sclk_hf +// switching is disabled, a new source can be started when SCLK_HF_SRC_SEL is +// changed, but the switch will not occur until this bit is set. This bit +// should be set to enable clock switching after STAT0.PENDINGSCLKHFSWITCHING +// indicates the new HF clock is ready. When switching completes (also +// indicated by STAT0.PENDINGSCLKHFSWITCHING) sclk_hf switching should be +// disabled to prevent flash corruption. Switching should not be enabled when +// running from flash. +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING 0x00010000 +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_M 0x00010000 +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_S 16 + +// Field: [14] HPOSC_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 + +// Field: [12] RCOSC_LF_TRIMMED +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 + +// Field: [11] XOSC_HF_POWER_MODE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 + +// Field: [10] XOSC_LF_DIG_BYPASS +// +// Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf +// clock. +// +// 0: Use 32kHz XOSC as xosc_lf clock source +// 1: Use digital input (from AON) as xosc_lf clock source. +// +// This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf +// as the sclk_lf source. The muxing performed by this bit is not glitch free. +// The following procedure must be followed when changing this field to avoid +// glitches on sclk_lf. +// +// 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock +// source. +// 2) Set or clear this bit to bypass or not bypass the xosc_lf. +// 3) Set SCLK_LF_SRC_SEL to use xosc_lf. +// +// It is recommended that either the rcosc_hf or xosc_hf (whichever is +// currently active) be selected as the source in step 1 above. This provides a +// faster clock change. +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 + +// Field: [9] CLK_LOSS_EN +// +// Enable clock loss detection and hence the indicators to system controller. +// Checks both SCLK_HF and SCLK_LF clock loss indicators. +// +// 0: Disable +// 1: Enable +// +// Clock loss detection must be disabled when changing the sclk_lf source. +// STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf +// source has completed. +#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 + +// Field: [8:7] ACLK_TDC_SRC_SEL +// +// Source select for aclk_tdc. +// +// 00: RCOSC_HF (48MHz) +// 01: RCOSC_HF (24MHz) +// 10: XOSC_HF (24MHz) +// 11: Not used +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 + +// Field: [6:5] ACLK_REF_SRC_SEL +// +// Source select for aclk_ref +// +// 00: RCOSC_HF derived (31.25kHz) +// 01: XOSC_HF derived (31.25kHz) +// 10: RCOSC_LF (32kHz) +// 11: XOSC_LF (32.768kHz) +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000060 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 5 + +// Field: [3:2] SCLK_LF_SRC_SEL +// +// Source select for sclk_lf +// ENUMs: +// XOSCLF Low frequency XOSC +// RCOSCLF Low frequency RCOSC +// XOSCHFDLF Low frequency clock derived from High Frequency +// XOSC +// RCOSCHFDLF Low frequency clock derived from High Frequency +// RCOSC +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 + +// Field: [1] SCLK_MF_SRC_SEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// XCOSCHFDMF Medium frequency clock derived from high frequency +// XOSC. +// RCOSCHFDMF Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_M 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_S 1 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_XCOSCHFDMF 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_RCOSCHFDMF 0x00000000 + +// Field: [0] SCLK_HF_SRC_SEL +// +// Source select for sclk_hf. XOSC option is supported for test and debug only +// and should be used when the XOSC_HF is running. +// ENUMs: +// XOSC High frequency XOSC clk +// RCOSC High frequency RCOSC clock +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_CTL1 +// +//***************************************************************************** +// Field: [22:18] RCOSCHFCTRIMFRACT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 + +// Field: [17] RCOSCHFCTRIMFRACT_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 + +// Field: [1:0] XOSC_HF_FAST_START +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_RADCEXTCFG +// +//***************************************************************************** +// Field: [31:22] HPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 + +// Field: [21:16] LPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 + +// Field: [15:12] IDAC_STEP +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 + +// Field: [11:6] RADC_DAC_TH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 + +// Field: [5] RADC_MODE_IS_SAR +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPCTL +// +//***************************************************************************** +// Field: [30] AMPCOMP_REQ_MODE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 + +// Field: [29:28] AMPCOMP_FSM_UPDATE_RATE +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 250KHZ Internal. Only to be used through TI provided API. +// 500KHZ Internal. Only to be used through TI provided API. +// 1MHZ Internal. Only to be used through TI provided API. +// 2MHZ Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 + +// Field: [27] AMPCOMP_SW_CTRL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 + +// Field: [26] AMPCOMP_SW_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 + +// Field: [23:20] IBIAS_OFFSET +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 + +// Field: [19:16] IBIAS_INIT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 + +// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 + +// Field: [7:4] CAP_STEP +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 + +// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPTH1 +// +//***************************************************************************** +// Field: [23:18] HPMRAMP3_LTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 + +// Field: [15:10] HPMRAMP3_HTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 + +// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 + +// Field: [5:0] HPMRAMP1_TH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPTH2 +// +//***************************************************************************** +// Field: [31:26] LPMUPDATE_LTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 + +// Field: [23:18] LPMUPDATE_HTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 + +// Field: [15:10] ADC_COMP_AMPTH_LPM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 + +// Field: [7:2] ADC_COMP_AMPTH_HPM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ANABYPASSVAL1 +// +//***************************************************************************** +// Field: [19:16] XOSC_HF_ROW_Q12 +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 + +// Field: [15:0] XOSC_HF_COLUMN_Q12 +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ANABYPASSVAL2 +// +//***************************************************************************** +// Field: [13:0] XOSC_HF_IBIASTHERM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ATESTCTL +// +//***************************************************************************** +// Field: [29] SCLK_LF_AUX_EN +// +// Enable 32 kHz clock to AUX_COMPB. +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x20000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x20000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 29 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL +// +//***************************************************************************** +// Field: [24] NANOAMP_BIAS_ENABLE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 + +// Field: [23] SPARE23 +// +// Software should not rely on the value of a reserved. Writing any other value +// than the reset value may result in undefined behavior +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 + +// Field: [5] ADC_SH_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 + +// Field: [4] ADC_SH_VBUF_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 + +// Field: [1:0] ADC_IREF_CTRL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_XOSCHFCTL +// +//***************************************************************************** +// Field: [9:8] PEAK_DET_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 + +// Field: [6] BYPASS +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 + +// Field: [4:2] HP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 + +// Field: [1:0] LP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_LFOSCCTL +// +//***************************************************************************** +// Field: [23:22] XOSCLF_REGULATOR_TRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 + +// Field: [21:18] XOSCLF_CMIRRWR_RATIO +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 + +// Field: [9:8] RCOSCLF_RTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 6P0MEG Internal. Only to be used through TI provided API. +// 6P5MEG Internal. Only to be used through TI provided API. +// 7P0MEG Internal. Only to be used through TI provided API. +// 7P5MEG Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 + +// Field: [7:0] RCOSCLF_CTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_RCOSCHFCTL +// +//***************************************************************************** +// Field: [15:8] RCOSCHF_CTRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT0 +// +//***************************************************************************** +// Field: [30:29] SCLK_LF_SRC +// +// Indicates source for the sclk_lf +// ENUMs: +// XOSCLF Low frequency XOSC +// RCOSCLF Low frequency RCOSC +// XOSCHFDLF Low frequency clock derived from High Frequency +// XOSC +// RCOSCHFDLF Low frequency clock derived from High Frequency +// RCOSC +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 + +// Field: [28] SCLK_HF_SRC +// +// Indicates source for the sclk_hf +// ENUMs: +// XOSC High frequency XOSC +// RCOSC High frequency RCOSC clock +#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 + +// Field: [22] RCOSC_HF_EN +// +// RCOSC_HF_EN +#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 + +// Field: [21] RCOSC_LF_EN +// +// RCOSC_LF_EN +#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 + +// Field: [20] XOSC_LF_EN +// +// XOSC_LF_EN +#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 + +// Field: [19] CLK_DCDC_RDY +// +// CLK_DCDC_RDY +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 + +// Field: [18] CLK_DCDC_RDY_ACK +// +// CLK_DCDC_RDY_ACK +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 + +// Field: [17] SCLK_HF_LOSS +// +// Indicates sclk_hf is lost +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 + +// Field: [16] SCLK_LF_LOSS +// +// Indicates sclk_lf is lost +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 + +// Field: [15] XOSC_HF_EN +// +// Indicates that XOSC_HF is enabled. +#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 + +// Field: [13] XB_48M_CLK_EN +// +// Indicates that the 48MHz clock from the DOUBLER is enabled. +// +// It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler +// bypass for the 48MHz crystal). +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 + +// Field: [11] XOSC_HF_LP_BUF_EN +// +// XOSC_HF_LP_BUF_EN +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 + +// Field: [10] XOSC_HF_HP_BUF_EN +// +// XOSC_HF_HP_BUF_EN +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 + +// Field: [8] ADC_THMET +// +// ADC_THMET +#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_S 8 + +// Field: [7] ADC_DATA_READY +// +// indicates when adc_data is ready. +#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 + +// Field: [6:1] ADC_DATA +// +// adc_data +#define DDI_0_OSC_STAT0_ADC_DATA_W 6 +#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E +#define DDI_0_OSC_STAT0_ADC_DATA_S 1 + +// Field: [0] PENDINGSCLKHFSWITCHING +// +// Indicates when sclk_hf is ready to be switched +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT1 +// +//***************************************************************************** +// Field: [31:28] RAMPSTATE +// +// AMPCOMP FSM State +// ENUMs: +// FAST_START_SETTLE FAST_START_SETTLE +// FAST_START FAST_START +// DUMMY_TO_INIT_1 DUMMY_TO_INIT_1 +// IDAC_DEC_W_MEASURE IDAC_DECREMENT_WITH_MEASURE +// IBIAS_INC IBIAS_INCREMENT +// LPM_UPDATE LPM_UPDATE +// IBIAS_DEC_W_MEASURE IBIAS_DECREMENT_WITH_MEASURE +// IBIAS_CAP_UPDATE IBIAS_CAP_UPDATE +// IDAC_INCREMENT IDAC_INCREMENT +// HPM_UPDATE HPM_UPDATE +// HPM_RAMP3 HPM_RAMP3 +// HPM_RAMP2 HPM_RAMP2 +// HPM_RAMP1 HPM_RAMP1 +// INITIALIZATION INITIALIZATION +// RESET RESET +#define DDI_0_OSC_STAT1_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_S 28 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 + +// Field: [27:22] HPM_UPDATE_AMP +// +// OSC amplitude during HPM_UPDATE state. +// When amplitude compensation of XOSC_HF is enabled in high performance mode, +// this value is the amplitude of the crystal oscillations measured by the +// on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 +// would indicate that the amplitude of the crystal is approximately 480 mV. +// To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero +// value. +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 + +// Field: [21:16] LPM_UPDATE_AMP +// +// OSC amplitude during LPM_UPDATE state +// When amplitude compensation of XOSC_HF is enabled in low power mode, this +// value is the amplitude of the crystal oscillations measured by the on-chip +// oscillator ADC, divided by 15 mV. For example, a value of 0x20 would +// indicate that the amplitude of the crystal is approximately 480 mV. To +// enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero +// value. +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 + +// Field: [15] FORCE_RCOSC_HF +// +// force_rcosc_hf +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 + +// Field: [14] SCLK_HF_EN +// +// SCLK_HF_EN +#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 + +// Field: [13] SCLK_MF_EN +// +// SCLK_MF_EN +#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 + +// Field: [12] ACLK_ADC_EN +// +// ACLK_ADC_EN +#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 + +// Field: [11] ACLK_TDC_EN +// +// ACLK_TDC_EN +#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 + +// Field: [10] ACLK_REF_EN +// +// ACLK_REF_EN +#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 + +// Field: [9] CLK_CHP_EN +// +// CLK_CHP_EN +#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 + +// Field: [8] CLK_DCDC_EN +// +// CLK_DCDC_EN +#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 + +// Field: [7] SCLK_HF_GOOD +// +// SCLK_HF_GOOD +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 + +// Field: [6] SCLK_MF_GOOD +// +// SCLK_MF_GOOD +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 + +// Field: [5] SCLK_LF_GOOD +// +// SCLK_LF_GOOD +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 + +// Field: [4] ACLK_ADC_GOOD +// +// ACLK_ADC_GOOD +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 + +// Field: [3] ACLK_TDC_GOOD +// +// ACLK_TDC_GOOD +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 + +// Field: [2] ACLK_REF_GOOD +// +// ACLK_REF_GOOD +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 + +// Field: [1] CLK_CHP_GOOD +// +// CLK_CHP_GOOD +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 + +// Field: [0] CLK_DCDC_GOOD +// +// CLK_DCDC_GOOD +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT2 +// +//***************************************************************************** +// Field: [31:26] ADC_DCBIAS +// +// DC Bias read by RADC during SAR mode +// The value is an unsigned integer. It is used for debug only. +#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 + +// Field: [25] HPM_RAMP1_THMET +// +// Indication of threshold is met for hpm_ramp1 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 + +// Field: [24] HPM_RAMP2_THMET +// +// Indication of threshold is met for hpm_ramp2 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 + +// Field: [23] HPM_RAMP3_THMET +// +// Indication of threshold is met for hpm_ramp3 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 + +// Field: [15:12] RAMPSTATE +// +// xosc_hf amplitude compensation FSM +// +// This is identical to STAT1.RAMPSTATE. See that description for encoding. +#define DDI_0_OSC_STAT2_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 +#define DDI_0_OSC_STAT2_RAMPSTATE_S 12 + +// Field: [3] AMPCOMP_REQ +// +// ampcomp_req +#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 + +// Field: [2] XOSC_HF_AMPGOOD +// +// amplitude of xosc_hf is within the required threshold (set by DDI). Not used +// for anything just for debug/status +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 + +// Field: [1] XOSC_HF_FREQGOOD +// +// frequency of xosc_hf is good to use for the digital clocks +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 + +// Field: [0] XOSC_HF_RF_FREQGOOD +// +// frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio +// operations. Used for SW to start synthesizer. +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 + + +#endif // __DDI_0_OSC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_device.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_device.h new file mode 100644 index 0000000..0214c00 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_device.h @@ -0,0 +1,168 @@ +/****************************************************************************** +* Filename: hw_device.h +* Revised: 2017-06-21 10:06:25 +0200 (Wed, 21 Jun 2017) +* Revision: 49177 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_DEVICE_H__ +#define __HW_DEVICE_H__ + +#include "../inc/hw_chip_def.h" + +#ifdef CC_GET_CHIP_PACKAGE + +#if ( CC_GET_CHIP_PACKAGE == 0x7 ) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 7x7 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 18 +#define AON_EVENT_DIO1 17 +#define AON_EVENT_DIO2 16 +#define AON_EVENT_DIO3 15 +#define AON_EVENT_DIO4 14 +#define AON_EVENT_DIO5 13 +#define AON_EVENT_DIO6 12 +#define AON_EVENT_DIO7 11 +#define AON_EVENT_DIO8 10 +#define AON_EVENT_DIO9 9 +#define AON_EVENT_DIO10 8 +#define AON_EVENT_DIO11 7 +#define AON_EVENT_DIO12 6 +#define AON_EVENT_DIO13 5 +#define AON_EVENT_DIO14 4 +#define AON_EVENT_DIO15 3 +#define AON_EVENT_DIO16 2 +#define AON_EVENT_DIO17 1 +#define AON_EVENT_DIO18 31 +#define AON_EVENT_DIO19 30 +#define AON_EVENT_DIO20 29 +#define AON_EVENT_DIO21 28 +#define AON_EVENT_DIO22 27 +#define AON_EVENT_DIO23 26 +#define AON_EVENT_DIO24 25 +#define AON_EVENT_DIO25 24 +#define AON_EVENT_DIO26 23 +#define AON_EVENT_DIO27 22 +#define AON_EVENT_DIO28 21 +#define AON_EVENT_DIO29 20 +#define AON_EVENT_DIO30 19 +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x7 ) + +#if ( CC_GET_CHIP_PACKAGE == 0x5 ) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 5x5 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 15 +#define AON_EVENT_DIO1 14 +#define AON_EVENT_DIO2 13 +#define AON_EVENT_DIO3 12 +#define AON_EVENT_DIO4 11 +#define AON_EVENT_DIO5 2 +#define AON_EVENT_DIO6 1 +#define AON_EVENT_DIO7 26 +#define AON_EVENT_DIO8 25 +#define AON_EVENT_DIO9 23 +#define AON_EVENT_DIO10 24 +#define AON_EVENT_DIO11 22 +#define AON_EVENT_DIO12 21 +#define AON_EVENT_DIO13 20 +#define AON_EVENT_DIO14 19 +#define AON_EVENT_DIO15 0x3F +#define AON_EVENT_DIO16 0x3F +#define AON_EVENT_DIO17 0x3F +#define AON_EVENT_DIO18 0x3F +#define AON_EVENT_DIO19 0x3F +#define AON_EVENT_DIO20 0x3F +#define AON_EVENT_DIO21 0x3F +#define AON_EVENT_DIO22 0x3F +#define AON_EVENT_DIO23 0x3F +#define AON_EVENT_DIO24 0x3F +#define AON_EVENT_DIO25 0x3F +#define AON_EVENT_DIO26 0x3F +#define AON_EVENT_DIO27 0x3F +#define AON_EVENT_DIO28 0x3F +#define AON_EVENT_DIO29 0x3F +#define AON_EVENT_DIO30 0x3F +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x5 ) + +#if ( CC_GET_CHIP_PACKAGE == 0x4 ) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 4x4 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 13 +#define AON_EVENT_DIO1 12 +#define AON_EVENT_DIO2 11 +#define AON_EVENT_DIO3 2 +#define AON_EVENT_DIO4 1 +#define AON_EVENT_DIO5 26 +#define AON_EVENT_DIO6 25 +#define AON_EVENT_DIO7 24 +#define AON_EVENT_DIO8 23 +#define AON_EVENT_DIO9 22 +#define AON_EVENT_DIO10 0x3F +#define AON_EVENT_DIO11 0x3F +#define AON_EVENT_DIO12 0x3F +#define AON_EVENT_DIO13 0x3F +#define AON_EVENT_DIO14 0x3F +#define AON_EVENT_DIO15 0x3F +#define AON_EVENT_DIO16 0x3F +#define AON_EVENT_DIO17 0x3F +#define AON_EVENT_DIO18 0x3F +#define AON_EVENT_DIO19 0x3F +#define AON_EVENT_DIO20 0x3F +#define AON_EVENT_DIO21 0x3F +#define AON_EVENT_DIO22 0x3F +#define AON_EVENT_DIO23 0x3F +#define AON_EVENT_DIO24 0x3F +#define AON_EVENT_DIO25 0x3F +#define AON_EVENT_DIO26 0x3F +#define AON_EVENT_DIO27 0x3F +#define AON_EVENT_DIO28 0x3F +#define AON_EVENT_DIO29 0x3F +#define AON_EVENT_DIO30 0x3F +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x4 ) + +#endif // defined( CC_GET_CHIP_PACKAGE ) +#endif // __HW_DEVICE_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_event.h new file mode 100644 index 0000000..288b54b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_event.h @@ -0,0 +1,3301 @@ +/****************************************************************************** +* Filename: hw_event_h +* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) +* Revision: 48904 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_EVENT_H__ +#define __HW_EVENT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// EVENT component +// +//***************************************************************************** +// Output Selection for CPU Interrupt 0 +#define EVENT_O_CPUIRQSEL0 0x00000000 + +// Output Selection for CPU Interrupt 1 +#define EVENT_O_CPUIRQSEL1 0x00000004 + +// Output Selection for CPU Interrupt 2 +#define EVENT_O_CPUIRQSEL2 0x00000008 + +// Output Selection for CPU Interrupt 3 +#define EVENT_O_CPUIRQSEL3 0x0000000C + +// Output Selection for CPU Interrupt 4 +#define EVENT_O_CPUIRQSEL4 0x00000010 + +// Output Selection for CPU Interrupt 5 +#define EVENT_O_CPUIRQSEL5 0x00000014 + +// Output Selection for CPU Interrupt 6 +#define EVENT_O_CPUIRQSEL6 0x00000018 + +// Output Selection for CPU Interrupt 7 +#define EVENT_O_CPUIRQSEL7 0x0000001C + +// Output Selection for CPU Interrupt 8 +#define EVENT_O_CPUIRQSEL8 0x00000020 + +// Output Selection for CPU Interrupt 9 +#define EVENT_O_CPUIRQSEL9 0x00000024 + +// Output Selection for CPU Interrupt 10 +#define EVENT_O_CPUIRQSEL10 0x00000028 + +// Output Selection for CPU Interrupt 11 +#define EVENT_O_CPUIRQSEL11 0x0000002C + +// Output Selection for CPU Interrupt 12 +#define EVENT_O_CPUIRQSEL12 0x00000030 + +// Output Selection for CPU Interrupt 13 +#define EVENT_O_CPUIRQSEL13 0x00000034 + +// Output Selection for CPU Interrupt 14 +#define EVENT_O_CPUIRQSEL14 0x00000038 + +// Output Selection for CPU Interrupt 15 +#define EVENT_O_CPUIRQSEL15 0x0000003C + +// Output Selection for CPU Interrupt 16 +#define EVENT_O_CPUIRQSEL16 0x00000040 + +// Output Selection for CPU Interrupt 17 +#define EVENT_O_CPUIRQSEL17 0x00000044 + +// Output Selection for CPU Interrupt 18 +#define EVENT_O_CPUIRQSEL18 0x00000048 + +// Output Selection for CPU Interrupt 19 +#define EVENT_O_CPUIRQSEL19 0x0000004C + +// Output Selection for CPU Interrupt 20 +#define EVENT_O_CPUIRQSEL20 0x00000050 + +// Output Selection for CPU Interrupt 21 +#define EVENT_O_CPUIRQSEL21 0x00000054 + +// Output Selection for CPU Interrupt 22 +#define EVENT_O_CPUIRQSEL22 0x00000058 + +// Output Selection for CPU Interrupt 23 +#define EVENT_O_CPUIRQSEL23 0x0000005C + +// Output Selection for CPU Interrupt 24 +#define EVENT_O_CPUIRQSEL24 0x00000060 + +// Output Selection for CPU Interrupt 25 +#define EVENT_O_CPUIRQSEL25 0x00000064 + +// Output Selection for CPU Interrupt 26 +#define EVENT_O_CPUIRQSEL26 0x00000068 + +// Output Selection for CPU Interrupt 27 +#define EVENT_O_CPUIRQSEL27 0x0000006C + +// Output Selection for CPU Interrupt 28 +#define EVENT_O_CPUIRQSEL28 0x00000070 + +// Output Selection for CPU Interrupt 29 +#define EVENT_O_CPUIRQSEL29 0x00000074 + +// Output Selection for CPU Interrupt 30 +#define EVENT_O_CPUIRQSEL30 0x00000078 + +// Output Selection for CPU Interrupt 31 +#define EVENT_O_CPUIRQSEL31 0x0000007C + +// Output Selection for CPU Interrupt 32 +#define EVENT_O_CPUIRQSEL32 0x00000080 + +// Output Selection for CPU Interrupt 33 +#define EVENT_O_CPUIRQSEL33 0x00000084 + +// Output Selection for RFC Event 0 +#define EVENT_O_RFCSEL0 0x00000100 + +// Output Selection for RFC Event 1 +#define EVENT_O_RFCSEL1 0x00000104 + +// Output Selection for RFC Event 2 +#define EVENT_O_RFCSEL2 0x00000108 + +// Output Selection for RFC Event 3 +#define EVENT_O_RFCSEL3 0x0000010C + +// Output Selection for RFC Event 4 +#define EVENT_O_RFCSEL4 0x00000110 + +// Output Selection for RFC Event 5 +#define EVENT_O_RFCSEL5 0x00000114 + +// Output Selection for RFC Event 6 +#define EVENT_O_RFCSEL6 0x00000118 + +// Output Selection for RFC Event 7 +#define EVENT_O_RFCSEL7 0x0000011C + +// Output Selection for RFC Event 8 +#define EVENT_O_RFCSEL8 0x00000120 + +// Output Selection for RFC Event 9 +#define EVENT_O_RFCSEL9 0x00000124 + +// Output Selection for GPT0 0 +#define EVENT_O_GPT0ACAPTSEL 0x00000200 + +// Output Selection for GPT0 1 +#define EVENT_O_GPT0BCAPTSEL 0x00000204 + +// Output Selection for GPT1 0 +#define EVENT_O_GPT1ACAPTSEL 0x00000300 + +// Output Selection for GPT1 1 +#define EVENT_O_GPT1BCAPTSEL 0x00000304 + +// Output Selection for GPT2 0 +#define EVENT_O_GPT2ACAPTSEL 0x00000400 + +// Output Selection for GPT2 1 +#define EVENT_O_GPT2BCAPTSEL 0x00000404 + +// Output Selection for DMA Channel 1 SREQ +#define EVENT_O_UDMACH1SSEL 0x00000508 + +// Output Selection for DMA Channel 1 REQ +#define EVENT_O_UDMACH1BSEL 0x0000050C + +// Output Selection for DMA Channel 2 SREQ +#define EVENT_O_UDMACH2SSEL 0x00000510 + +// Output Selection for DMA Channel 2 REQ +#define EVENT_O_UDMACH2BSEL 0x00000514 + +// Output Selection for DMA Channel 3 SREQ +#define EVENT_O_UDMACH3SSEL 0x00000518 + +// Output Selection for DMA Channel 3 REQ +#define EVENT_O_UDMACH3BSEL 0x0000051C + +// Output Selection for DMA Channel 4 SREQ +#define EVENT_O_UDMACH4SSEL 0x00000520 + +// Output Selection for DMA Channel 4 REQ +#define EVENT_O_UDMACH4BSEL 0x00000524 + +// Output Selection for DMA Channel 5 SREQ +#define EVENT_O_UDMACH5SSEL 0x00000528 + +// Output Selection for DMA Channel 5 REQ +#define EVENT_O_UDMACH5BSEL 0x0000052C + +// Output Selection for DMA Channel 6 SREQ +#define EVENT_O_UDMACH6SSEL 0x00000530 + +// Output Selection for DMA Channel 6 REQ +#define EVENT_O_UDMACH6BSEL 0x00000534 + +// Output Selection for DMA Channel 7 SREQ +#define EVENT_O_UDMACH7SSEL 0x00000538 + +// Output Selection for DMA Channel 7 REQ +#define EVENT_O_UDMACH7BSEL 0x0000053C + +// Output Selection for DMA Channel 8 SREQ +#define EVENT_O_UDMACH8SSEL 0x00000540 + +// Output Selection for DMA Channel 8 REQ +#define EVENT_O_UDMACH8BSEL 0x00000544 + +// Output Selection for DMA Channel 9 SREQ +#define EVENT_O_UDMACH9SSEL 0x00000548 + +// Output Selection for DMA Channel 9 REQ +#define EVENT_O_UDMACH9BSEL 0x0000054C + +// Output Selection for DMA Channel 10 SREQ +#define EVENT_O_UDMACH10SSEL 0x00000550 + +// Output Selection for DMA Channel 10 REQ +#define EVENT_O_UDMACH10BSEL 0x00000554 + +// Output Selection for DMA Channel 11 SREQ +#define EVENT_O_UDMACH11SSEL 0x00000558 + +// Output Selection for DMA Channel 11 REQ +#define EVENT_O_UDMACH11BSEL 0x0000055C + +// Output Selection for DMA Channel 12 SREQ +#define EVENT_O_UDMACH12SSEL 0x00000560 + +// Output Selection for DMA Channel 12 REQ +#define EVENT_O_UDMACH12BSEL 0x00000564 + +// Output Selection for DMA Channel 13 REQ +#define EVENT_O_UDMACH13BSEL 0x0000056C + +// Output Selection for DMA Channel 14 REQ +#define EVENT_O_UDMACH14BSEL 0x00000574 + +// Output Selection for DMA Channel 15 REQ +#define EVENT_O_UDMACH15BSEL 0x0000057C + +// Output Selection for DMA Channel 16 SREQ +#define EVENT_O_UDMACH16SSEL 0x00000580 + +// Output Selection for DMA Channel 16 REQ +#define EVENT_O_UDMACH16BSEL 0x00000584 + +// Output Selection for DMA Channel 17 SREQ +#define EVENT_O_UDMACH17SSEL 0x00000588 + +// Output Selection for DMA Channel 17 REQ +#define EVENT_O_UDMACH17BSEL 0x0000058C + +// Output Selection for DMA Channel 21 SREQ +#define EVENT_O_UDMACH21SSEL 0x000005A8 + +// Output Selection for DMA Channel 21 REQ +#define EVENT_O_UDMACH21BSEL 0x000005AC + +// Output Selection for DMA Channel 22 SREQ +#define EVENT_O_UDMACH22SSEL 0x000005B0 + +// Output Selection for DMA Channel 22 REQ +#define EVENT_O_UDMACH22BSEL 0x000005B4 + +// Output Selection for DMA Channel 23 SREQ +#define EVENT_O_UDMACH23SSEL 0x000005B8 + +// Output Selection for DMA Channel 23 REQ +#define EVENT_O_UDMACH23BSEL 0x000005BC + +// Output Selection for DMA Channel 24 SREQ +#define EVENT_O_UDMACH24SSEL 0x000005C0 + +// Output Selection for DMA Channel 24 REQ +#define EVENT_O_UDMACH24BSEL 0x000005C4 + +// Output Selection for GPT3 0 +#define EVENT_O_GPT3ACAPTSEL 0x00000600 + +// Output Selection for GPT3 1 +#define EVENT_O_GPT3BCAPTSEL 0x00000604 + +// Output Selection for AUX Subscriber 0 +#define EVENT_O_AUXSEL0 0x00000700 + +// Output Selection for NMI Subscriber 0 +#define EVENT_O_CM3NMISEL0 0x00000800 + +// Output Selection for I2S Subscriber 0 +#define EVENT_O_I2SSTMPSEL0 0x00000900 + +// Output Selection for FRZ Subscriber +#define EVENT_O_FRZSEL0 0x00000A00 + +// Set or Clear Software Events +#define EVENT_O_SWEV 0x00000F00 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +#define EVENT_CPUIRQSEL0_EV_W 7 +#define EVENT_CPUIRQSEL0_EV_M 0x0000007F +#define EVENT_CPUIRQSEL0_EV_S 0 +#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL1 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// I2C_IRQ Interrupt event from I2C +#define EVENT_CPUIRQSEL1_EV_W 7 +#define EVENT_CPUIRQSEL1_EV_M 0x0000007F +#define EVENT_CPUIRQSEL1_EV_S 0 +#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL2 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +#define EVENT_CPUIRQSEL2_EV_W 7 +#define EVENT_CPUIRQSEL2_EV_M 0x0000007F +#define EVENT_CPUIRQSEL2_EV_S 0 +#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL4 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +#define EVENT_CPUIRQSEL4_EV_W 7 +#define EVENT_CPUIRQSEL4_EV_M 0x0000007F +#define EVENT_CPUIRQSEL4_EV_S 0 +#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL5 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +#define EVENT_CPUIRQSEL5_EV_W 7 +#define EVENT_CPUIRQSEL5_EV_M 0x0000007F +#define EVENT_CPUIRQSEL5_EV_S 0 +#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL6 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SWEV0 AUX software event 0, triggered by +// AUX_EVCTL:SWEVSET.SWEV0, also available as +// AUX_EVENT0 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +// AUX domain wakeup control +// AON_EVENT:AUXWUSEL +#define EVENT_CPUIRQSEL6_EV_W 7 +#define EVENT_CPUIRQSEL6_EV_M 0x0000007F +#define EVENT_CPUIRQSEL6_EV_S 0 +#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL7 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +#define EVENT_CPUIRQSEL7_EV_W 7 +#define EVENT_CPUIRQSEL7_EV_M 0x0000007F +#define EVENT_CPUIRQSEL7_EV_S 0 +#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL8 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +#define EVENT_CPUIRQSEL8_EV_W 7 +#define EVENT_CPUIRQSEL8_EV_M 0x0000007F +#define EVENT_CPUIRQSEL8_EV_S 0 +#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL9 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +#define EVENT_CPUIRQSEL9_EV_W 7 +#define EVENT_CPUIRQSEL9_EV_M 0x0000007F +#define EVENT_CPUIRQSEL9_EV_S 0 +#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL10 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +#define EVENT_CPUIRQSEL10_EV_W 7 +#define EVENT_CPUIRQSEL10_EV_M 0x0000007F +#define EVENT_CPUIRQSEL10_EV_S 0 +#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL11 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +#define EVENT_CPUIRQSEL11_EV_W 7 +#define EVENT_CPUIRQSEL11_EV_M 0x0000007F +#define EVENT_CPUIRQSEL11_EV_S 0 +#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL12 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// I2S_IRQ Interrupt event from I2S +#define EVENT_CPUIRQSEL12_EV_W 7 +#define EVENT_CPUIRQSEL12_EV_M 0x0000007F +#define EVENT_CPUIRQSEL12_EV_S 0 +#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL13 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SWEV1 AUX software event 1, triggered by +// AUX_EVCTL:SWEVSET.SWEV1, also available as +// AUX_EVENT2 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +// AUX domain wakeup control +// AON_EVENT:AUXWUSEL +#define EVENT_CPUIRQSEL13_EV_W 7 +#define EVENT_CPUIRQSEL13_EV_M 0x0000007F +#define EVENT_CPUIRQSEL13_EV_S 0 +#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL14 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +#define EVENT_CPUIRQSEL14_EV_W 7 +#define EVENT_CPUIRQSEL14_EV_M 0x0000007F +#define EVENT_CPUIRQSEL14_EV_S 0 +#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL15 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +#define EVENT_CPUIRQSEL15_EV_W 7 +#define EVENT_CPUIRQSEL15_EV_M 0x0000007F +#define EVENT_CPUIRQSEL15_EV_S 0 +#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL16 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +#define EVENT_CPUIRQSEL16_EV_W 7 +#define EVENT_CPUIRQSEL16_EV_M 0x0000007F +#define EVENT_CPUIRQSEL16_EV_S 0 +#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL17 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +#define EVENT_CPUIRQSEL17_EV_W 7 +#define EVENT_CPUIRQSEL17_EV_M 0x0000007F +#define EVENT_CPUIRQSEL17_EV_S 0 +#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL18 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +#define EVENT_CPUIRQSEL18_EV_W 7 +#define EVENT_CPUIRQSEL18_EV_M 0x0000007F +#define EVENT_CPUIRQSEL18_EV_S 0 +#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL19 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +#define EVENT_CPUIRQSEL19_EV_W 7 +#define EVENT_CPUIRQSEL19_EV_M 0x0000007F +#define EVENT_CPUIRQSEL19_EV_S 0 +#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL20 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +#define EVENT_CPUIRQSEL20_EV_W 7 +#define EVENT_CPUIRQSEL20_EV_M 0x0000007F +#define EVENT_CPUIRQSEL20_EV_S 0 +#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL21 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +#define EVENT_CPUIRQSEL21_EV_W 7 +#define EVENT_CPUIRQSEL21_EV_M 0x0000007F +#define EVENT_CPUIRQSEL21_EV_S 0 +#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL22 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +#define EVENT_CPUIRQSEL22_EV_W 7 +#define EVENT_CPUIRQSEL22_EV_M 0x0000007F +#define EVENT_CPUIRQSEL22_EV_S 0 +#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL23 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +#define EVENT_CPUIRQSEL23_EV_W 7 +#define EVENT_CPUIRQSEL23_EV_M 0x0000007F +#define EVENT_CPUIRQSEL23_EV_S 0 +#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL24 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +#define EVENT_CPUIRQSEL24_EV_W 7 +#define EVENT_CPUIRQSEL24_EV_M 0x0000007F +#define EVENT_CPUIRQSEL24_EV_S 0 +#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL25 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS +#define EVENT_CPUIRQSEL25_EV_W 7 +#define EVENT_CPUIRQSEL25_EV_M 0x0000007F +#define EVENT_CPUIRQSEL25_EV_S 0 +#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL26 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +#define EVENT_CPUIRQSEL26_EV_W 7 +#define EVENT_CPUIRQSEL26_EV_M 0x0000007F +#define EVENT_CPUIRQSEL26_EV_S 0 +#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL27 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_CPUIRQSEL27_EV_W 7 +#define EVENT_CPUIRQSEL27_EV_M 0x0000007F +#define EVENT_CPUIRQSEL27_EV_S 0 +#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL28 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +#define EVENT_CPUIRQSEL28_EV_W 7 +#define EVENT_CPUIRQSEL28_EV_M 0x0000007F +#define EVENT_CPUIRQSEL28_EV_S 0 +#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL29 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +#define EVENT_CPUIRQSEL29_EV_W 7 +#define EVENT_CPUIRQSEL29_EV_M 0x0000007F +#define EVENT_CPUIRQSEL29_EV_S 0 +#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL30 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg +// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled +// by CRYPTO:IRQEN.DMA_IN_DONE +// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, +// see UDMA0:SOFTREQ +// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see +// UDMA0:SOFTREQ +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2S_IRQ Interrupt event from I2S +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// NONE Always inactive +#define EVENT_CPUIRQSEL30_EV_W 7 +#define EVENT_CPUIRQSEL30_EV_M 0x0000007F +#define EVENT_CPUIRQSEL30_EV_S 0 +#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 +#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B +#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 +#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 +#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 +#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL31 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +#define EVENT_CPUIRQSEL31_EV_W 7 +#define EVENT_CPUIRQSEL31_EV_M 0x0000007F +#define EVENT_CPUIRQSEL31_EV_S 0 +#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL32 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +#define EVENT_CPUIRQSEL32_EV_W 7 +#define EVENT_CPUIRQSEL32_EV_M 0x0000007F +#define EVENT_CPUIRQSEL32_EV_S 0 +#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL33 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN +#define EVENT_CPUIRQSEL33_EV_W 7 +#define EVENT_CPUIRQSEL33_EV_M 0x0000007F +#define EVENT_CPUIRQSEL33_EV_S 0 +#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +#define EVENT_RFCSEL0_EV_W 7 +#define EVENT_RFCSEL0_EV_M 0x0000007F +#define EVENT_RFCSEL0_EV_S 0 +#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL1 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +#define EVENT_RFCSEL1_EV_W 7 +#define EVENT_RFCSEL1_EV_M 0x0000007F +#define EVENT_RFCSEL1_EV_S 0 +#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL2 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +#define EVENT_RFCSEL2_EV_W 7 +#define EVENT_RFCSEL2_EV_M 0x0000007F +#define EVENT_RFCSEL2_EV_S 0 +#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL3 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +#define EVENT_RFCSEL3_EV_W 7 +#define EVENT_RFCSEL3_EV_M 0x0000007F +#define EVENT_RFCSEL3_EV_S 0 +#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL4 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +#define EVENT_RFCSEL4_EV_W 7 +#define EVENT_RFCSEL4_EV_M 0x0000007F +#define EVENT_RFCSEL4_EV_S 0 +#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL5 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +#define EVENT_RFCSEL5_EV_W 7 +#define EVENT_RFCSEL5_EV_M 0x0000007F +#define EVENT_RFCSEL5_EV_S 0 +#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL6 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +#define EVENT_RFCSEL6_EV_W 7 +#define EVENT_RFCSEL6_EV_M 0x0000007F +#define EVENT_RFCSEL6_EV_S 0 +#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL7 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +#define EVENT_RFCSEL7_EV_W 7 +#define EVENT_RFCSEL7_EV_M 0x0000007F +#define EVENT_RFCSEL7_EV_S 0 +#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL8 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +#define EVENT_RFCSEL8_EV_W 7 +#define EVENT_RFCSEL8_EV_M 0x0000007F +#define EVENT_RFCSEL8_EV_S 0 +#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL9 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2S_IRQ Interrupt event from I2S +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +// NONE Always inactive +#define EVENT_RFCSEL9_EV_W 7 +#define EVENT_RFCSEL9_EV_M 0x0000007F +#define EVENT_RFCSEL9_EV_S 0 +#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B +#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A +#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_RFCSEL9_EV_SWEV1 0x00000065 +#define EVENT_RFCSEL9_EV_SWEV0 0x00000064 +#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 +#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 +#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 +#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 +#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 +#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 +#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 +#define EVENT_RFCSEL9_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT0ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT0ACAPTSEL_EV_W 7 +#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0ACAPTSEL_EV_S 0 +#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT0BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT0BCAPTSEL_EV_W 7 +#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0BCAPTSEL_EV_S 0 +#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT1ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT1ACAPTSEL_EV_W 7 +#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1ACAPTSEL_EV_S 0 +#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT1BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT1BCAPTSEL_EV_W 7 +#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1BCAPTSEL_EV_S 0 +#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT2ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT2ACAPTSEL_EV_W 7 +#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2ACAPTSEL_EV_S 0 +#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT2BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT2BCAPTSEL_EV_W 7 +#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2BCAPTSEL_EV_S 0 +#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH1SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by +// UART0:DMACTL.RXDMAE +#define EVENT_UDMACH1SSEL_EV_W 7 +#define EVENT_UDMACH1SSEL_EV_M 0x0000007F +#define EVENT_UDMACH1SSEL_EV_S 0 +#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH1BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by +// UART0:DMACTL.RXDMAE +#define EVENT_UDMACH1BSEL_EV_W 7 +#define EVENT_UDMACH1BSEL_EV_M 0x0000007F +#define EVENT_UDMACH1BSEL_EV_S 0 +#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH2SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by +// UART0:DMACTL.TXDMAE +#define EVENT_UDMACH2SSEL_EV_W 7 +#define EVENT_UDMACH2SSEL_EV_M 0x0000007F +#define EVENT_UDMACH2SSEL_EV_S 0 +#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH2BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by +// UART0:DMACTL.TXDMAE +#define EVENT_UDMACH2BSEL_EV_W 7 +#define EVENT_UDMACH2BSEL_EV_M 0x0000007F +#define EVENT_UDMACH2BSEL_EV_S 0 +#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH3SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH3SSEL_EV_W 7 +#define EVENT_UDMACH3SSEL_EV_M 0x0000007F +#define EVENT_UDMACH3SSEL_EV_S 0 +#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH3BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH3BSEL_EV_W 7 +#define EVENT_UDMACH3BSEL_EV_M 0x0000007F +#define EVENT_UDMACH3BSEL_EV_S 0 +#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH4SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH4SSEL_EV_W 7 +#define EVENT_UDMACH4SSEL_EV_M 0x0000007F +#define EVENT_UDMACH4SSEL_EV_S 0 +#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH4BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH4BSEL_EV_W 7 +#define EVENT_UDMACH4BSEL_EV_M 0x0000007F +#define EVENT_UDMACH4BSEL_EV_S 0 +#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH5SSEL +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_UDMACH5BSEL +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_UDMACH6SSEL +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_UDMACH6BSEL +// +//***************************************************************************** +//***************************************************************************** +// +// Register: EVENT_O_UDMACH7SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_DMASREQ DMA single request event from AUX, configured by +// AUX_EVCTL:DMACTL +#define EVENT_UDMACH7SSEL_EV_W 7 +#define EVENT_UDMACH7SSEL_EV_M 0x0000007F +#define EVENT_UDMACH7SSEL_EV_S 0 +#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH7BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_DMABREQ DMA burst request event from AUX, configured by +// AUX_EVCTL:DMACTL +#define EVENT_UDMACH7BSEL_EV_W 7 +#define EVENT_UDMACH7BSEL_EV_M 0x0000007F +#define EVENT_UDMACH7BSEL_EV_S 0 +#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH8SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +#define EVENT_UDMACH8SSEL_EV_W 7 +#define EVENT_UDMACH8SSEL_EV_M 0x0000007F +#define EVENT_UDMACH8SSEL_EV_S 0 +#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH8BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +#define EVENT_UDMACH8BSEL_EV_W 7 +#define EVENT_UDMACH8BSEL_EV_M 0x0000007F +#define EVENT_UDMACH8BSEL_EV_S 0 +#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH9SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH9SSEL_EV_W 7 +#define EVENT_UDMACH9SSEL_EV_M 0x0000007F +#define EVENT_UDMACH9SSEL_EV_S 0 +#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 +#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH9BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH9BSEL_EV_W 7 +#define EVENT_UDMACH9BSEL_EV_M 0x0000007F +#define EVENT_UDMACH9BSEL_EV_S 0 +#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH10SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH10SSEL_EV_W 7 +#define EVENT_UDMACH10SSEL_EV_M 0x0000007F +#define EVENT_UDMACH10SSEL_EV_S 0 +#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 +#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH10BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH10BSEL_EV_W 7 +#define EVENT_UDMACH10BSEL_EV_M 0x0000007F +#define EVENT_UDMACH10BSEL_EV_S 0 +#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH11SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH11SSEL_EV_W 7 +#define EVENT_UDMACH11SSEL_EV_M 0x0000007F +#define EVENT_UDMACH11SSEL_EV_S 0 +#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 +#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH11BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH11BSEL_EV_W 7 +#define EVENT_UDMACH11BSEL_EV_M 0x0000007F +#define EVENT_UDMACH11BSEL_EV_S 0 +#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH12SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH12SSEL_EV_W 7 +#define EVENT_UDMACH12SSEL_EV_M 0x0000007F +#define EVENT_UDMACH12SSEL_EV_S 0 +#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 +#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH12BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH12BSEL_EV_W 7 +#define EVENT_UDMACH12BSEL_EV_M 0x0000007F +#define EVENT_UDMACH12BSEL_EV_S 0 +#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH13BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +#define EVENT_UDMACH13BSEL_EV_W 7 +#define EVENT_UDMACH13BSEL_EV_M 0x0000007F +#define EVENT_UDMACH13BSEL_EV_S 0 +#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH14BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// CPU_HALTED CPU halted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_DMABREQ DMA burst request event from AUX, configured by +// AUX_EVCTL:DMACTL +// AUX_DMASREQ DMA single request event from AUX, configured by +// AUX_EVCTL:DMACTL +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +// WDT_NMI Watchdog non maskable interrupt event, controlled +// by WDT:CTL.INTTYPE +// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg +// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled +// by CRYPTO:IRQEN.DMA_IN_DONE +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by +// UART0:DMACTL.TXDMAE +// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by +// UART0:DMACTL.TXDMAE +// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by +// UART0:DMACTL.RXDMAE +// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by +// UART0:DMACTL.RXDMAE +// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// AUX_SWEV1 AUX software event 1, triggered by +// AUX_EVCTL:SWEVSET.SWEV1, also available as +// AUX_EVENT2 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +// AUX domain wakeup control +// AON_EVENT:AUXWUSEL +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, +// see UDMA0:SOFTREQ +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see +// UDMA0:SOFTREQ +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2C_IRQ Interrupt event from I2C +// I2S_IRQ Interrupt event from I2S +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +// NONE Always inactive +#define EVENT_UDMACH14BSEL_EV_W 7 +#define EVENT_UDMACH14BSEL_EV_M 0x0000007F +#define EVENT_UDMACH14BSEL_EV_S 0 +#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 +#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 +#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 +#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 +#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 +#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 +#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 +#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 +#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 +#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 +#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 +#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 +#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 +#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F +#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E +#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D +#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C +#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B +#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 +#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 +#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 +#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH15BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +#define EVENT_UDMACH15BSEL_EV_W 7 +#define EVENT_UDMACH15BSEL_EV_M 0x0000007F +#define EVENT_UDMACH15BSEL_EV_S 0 +#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH16SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH16SSEL_EV_W 7 +#define EVENT_UDMACH16SSEL_EV_M 0x0000007F +#define EVENT_UDMACH16SSEL_EV_S 0 +#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH16BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH16BSEL_EV_W 7 +#define EVENT_UDMACH16BSEL_EV_M 0x0000007F +#define EVENT_UDMACH16BSEL_EV_S 0 +#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH17SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH17SSEL_EV_W 7 +#define EVENT_UDMACH17SSEL_EV_M 0x0000007F +#define EVENT_UDMACH17SSEL_EV_S 0 +#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH17BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH17BSEL_EV_W 7 +#define EVENT_UDMACH17BSEL_EV_M 0x0000007F +#define EVENT_UDMACH17BSEL_EV_S 0 +#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH21SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_UDMACH21SSEL_EV_W 7 +#define EVENT_UDMACH21SSEL_EV_M 0x0000007F +#define EVENT_UDMACH21SSEL_EV_S 0 +#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH21BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_UDMACH21BSEL_EV_W 7 +#define EVENT_UDMACH21BSEL_EV_M 0x0000007F +#define EVENT_UDMACH21BSEL_EV_S 0 +#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH22SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +#define EVENT_UDMACH22SSEL_EV_W 7 +#define EVENT_UDMACH22SSEL_EV_M 0x0000007F +#define EVENT_UDMACH22SSEL_EV_S 0 +#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH22BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +#define EVENT_UDMACH22BSEL_EV_W 7 +#define EVENT_UDMACH22BSEL_EV_M 0x0000007F +#define EVENT_UDMACH22BSEL_EV_S 0 +#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH23SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +#define EVENT_UDMACH23SSEL_EV_W 7 +#define EVENT_UDMACH23SSEL_EV_M 0x0000007F +#define EVENT_UDMACH23SSEL_EV_S 0 +#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH23BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +#define EVENT_UDMACH23BSEL_EV_W 7 +#define EVENT_UDMACH23BSEL_EV_M 0x0000007F +#define EVENT_UDMACH23BSEL_EV_S 0 +#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH24SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +#define EVENT_UDMACH24SSEL_EV_W 7 +#define EVENT_UDMACH24SSEL_EV_M 0x0000007F +#define EVENT_UDMACH24SSEL_EV_S 0 +#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH24BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +#define EVENT_UDMACH24BSEL_EV_W 7 +#define EVENT_UDMACH24BSEL_EV_M 0x0000007F +#define EVENT_UDMACH24BSEL_EV_S 0 +#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 + +//***************************************************************************** +// +// Register: EVENT_O_GPT3ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT3ACAPTSEL_EV_W 7 +#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3ACAPTSEL_EV_S 0 +#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT3BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags +// are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the +// AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, corresponds flags are here +// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT3BCAPTSEL_EV_W 7 +#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3BCAPTSEL_EV_S 0 +#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_AUXSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +// NONE Always inactive +#define EVENT_AUXSEL0_EV_W 7 +#define EVENT_AUXSEL0_EV_M 0x0000007F +#define EVENT_AUXSEL0_EV_S 0 +#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_AUXSEL0_EV_GPT1B 0x00000013 +#define EVENT_AUXSEL0_EV_GPT1A 0x00000012 +#define EVENT_AUXSEL0_EV_GPT0B 0x00000011 +#define EVENT_AUXSEL0_EV_GPT0A 0x00000010 +#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F +#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E +#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D +#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C +#define EVENT_AUXSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_CM3NMISEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// WDT_NMI Watchdog non maskable interrupt event, controlled +// by WDT:CTL.INTTYPE +#define EVENT_CM3NMISEL0_EV_W 7 +#define EVENT_CM3NMISEL0_EV_M 0x0000007F +#define EVENT_CM3NMISEL0_EV_S 0 +#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 + +//***************************************************************************** +// +// Register: EVENT_O_I2SSTMPSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// NONE Always inactive +#define EVENT_I2SSTMPSEL0_EV_W 7 +#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F +#define EVENT_I2SSTMPSEL0_EV_S 0 +#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_FRZSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// CPU_HALTED CPU halted +// NONE Always inactive +#define EVENT_FRZSEL0_EV_W 7 +#define EVENT_FRZSEL0_EV_M 0x0000007F +#define EVENT_FRZSEL0_EV_S 0 +#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 +#define EVENT_FRZSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_SWEV +// +//***************************************************************************** +// Field: [24] SWEV3 +// +// Writing "1" to this bit when the value is "0" triggers the Software 3 event. +#define EVENT_SWEV_SWEV3 0x01000000 +#define EVENT_SWEV_SWEV3_BITN 24 +#define EVENT_SWEV_SWEV3_M 0x01000000 +#define EVENT_SWEV_SWEV3_S 24 + +// Field: [16] SWEV2 +// +// Writing "1" to this bit when the value is "0" triggers the Software 2 event. +#define EVENT_SWEV_SWEV2 0x00010000 +#define EVENT_SWEV_SWEV2_BITN 16 +#define EVENT_SWEV_SWEV2_M 0x00010000 +#define EVENT_SWEV_SWEV2_S 16 + +// Field: [8] SWEV1 +// +// Writing "1" to this bit when the value is "0" triggers the Software 1 event. +#define EVENT_SWEV_SWEV1 0x00000100 +#define EVENT_SWEV_SWEV1_BITN 8 +#define EVENT_SWEV_SWEV1_M 0x00000100 +#define EVENT_SWEV_SWEV1_S 8 + +// Field: [0] SWEV0 +// +// Writing "1" to this bit when the value is "0" triggers the Software 0 event. +#define EVENT_SWEV_SWEV0 0x00000001 +#define EVENT_SWEV_SWEV0_BITN 0 +#define EVENT_SWEV_SWEV0_M 0x00000001 +#define EVENT_SWEV_SWEV0_S 0 + + +#endif // __EVENT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_fcfg1.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_fcfg1.h new file mode 100644 index 0000000..0862ecb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_fcfg1.h @@ -0,0 +1,2921 @@ +/****************************************************************************** +* Filename: hw_fcfg1_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_FCFG1_H__ +#define __HW_FCFG1_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// FCFG1 component +// +//***************************************************************************** +// Misc configurations +#define FCFG1_O_MISC_CONF_1 0x000000A0 + +// Internal +#define FCFG1_O_MISC_CONF_2 0x000000A4 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV5 0x000000C4 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV6 0x000000C8 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV10 0x000000CC + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV12 0x000000D0 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV15 0x000000D4 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV30 0x000000D8 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000DC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV6 0x000000E0 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000E4 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV12 0x000000E8 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV15 0x000000EC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV30 0x000000F0 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV5 0x000000F4 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV6 0x000000F8 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV10 0x000000FC + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV12 0x00000100 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV15 0x00000104 + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC_DIV30 0x00000108 + +// Shadow of EFUSE:DIE_ID_0 +#define FCFG1_O_SHDW_DIE_ID_0 0x00000118 + +// Shadow of EFUSE:DIE_ID_1 +#define FCFG1_O_SHDW_DIE_ID_1 0x0000011C + +// Shadow of EFUSE:DIE_ID_2 +#define FCFG1_O_SHDW_DIE_ID_2 0x00000120 + +// Shadow of EFUSE:DIE_ID_3 +#define FCFG1_O_SHDW_DIE_ID_3 0x00000124 + +// Internal +#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x00000138 + +// Internal +#define FCFG1_O_SHDW_ANA_TRIM 0x0000013C + +#define FCFG1_O_FLASH_NUMBER 0x00000164 + +#define FCFG1_O_FLASH_COORDINATE 0x0000016C + +// Internal +#define FCFG1_O_FLASH_E_P 0x00000170 + +// Internal +#define FCFG1_O_FLASH_C_E_P_R 0x00000174 + +// Internal +#define FCFG1_O_FLASH_P_R_PV 0x00000178 + +// Internal +#define FCFG1_O_FLASH_EH_SEQ 0x0000017C + +// Internal +#define FCFG1_O_FLASH_VHV_E 0x00000180 + +// Internal +#define FCFG1_O_FLASH_PP 0x00000184 + +// Internal +#define FCFG1_O_FLASH_PROG_EP 0x00000188 + +// Internal +#define FCFG1_O_FLASH_ERA_PW 0x0000018C + +// Internal +#define FCFG1_O_FLASH_VHV 0x00000190 + +// Internal +#define FCFG1_O_FLASH_VHV_PV 0x00000194 + +// Internal +#define FCFG1_O_FLASH_V 0x00000198 + +// User Identification. +#define FCFG1_O_USER_ID 0x00000294 + +// Internal +#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 + +// Internal +#define FCFG1_O_ANA2_TRIM 0x000002B4 + +// Internal +#define FCFG1_O_LDO_TRIM 0x000002B8 + +// Internal +#define FCFG1_O_BAT_RC_LDO_TRIM 0x000002BC + +// MAC BLE Address 0 +#define FCFG1_O_MAC_BLE_0 0x000002E8 + +// MAC BLE Address 1 +#define FCFG1_O_MAC_BLE_1 0x000002EC + +// MAC IEEE 802.15.4 Address 0 +#define FCFG1_O_MAC_15_4_0 0x000002F0 + +// MAC IEEE 802.15.4 Address 1 +#define FCFG1_O_MAC_15_4_1 0x000002F4 + +// Internal +#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 + +// Miscellaneous Trim Parameters +#define FCFG1_O_MISC_TRIM 0x0000030C + +// Internal +#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 + +// Internal +#define FCFG1_O_TRIM_CAL_REVISION 0x00000314 + +// IcePick Device Identification +#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 + +// Factory Configuration (FCFG1) Revision +#define FCFG1_O_FCFG1_REVISION 0x0000031C + +// Misc OTP Data +#define FCFG1_O_MISC_OTP_DATA 0x00000320 + +// IO Configuration +#define FCFG1_O_IOCONF 0x00000344 + +// Internal +#define FCFG1_O_CONFIG_IF_ADC 0x0000034C + +// Internal +#define FCFG1_O_CONFIG_OSC_TOP 0x00000350 + +// Internal +#define FCFG1_O_CONFIG_RF_FRONTEND 0x00000354 + +// Internal +#define FCFG1_O_CONFIG_SYNTH 0x00000358 + +// AUX_ADC Gain in Absolute Reference Mode +#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C + +// AUX_ADC Gain in Relative Reference Mode +#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 + +// AUX_ADC Temperature Offsets in Absolute Reference Mode +#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 + +// Internal +#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C + +// Internal +#define FCFG1_O_AMPCOMP_TH1 0x00000370 + +// Internal +#define FCFG1_O_AMPCOMP_TH2 0x00000374 + +// Internal +#define FCFG1_O_AMPCOMP_CTRL1 0x00000378 + +// Internal +#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C + +// Internal +#define FCFG1_O_CONFIG_MISC_ADC 0x00000380 + +// Internal +#define FCFG1_O_VOLT_TRIM 0x00000388 + +// OSC Configuration +#define FCFG1_O_OSC_CONF 0x0000038C + +// Internal +#define FCFG1_O_FREQ_OFFSET 0x00000390 + +// Internal +#define FCFG1_O_CAP_TRIM 0x00000394 + +// Internal +#define FCFG1_O_MISC_OTP_DATA_1 0x00000398 + +// Power Down Current Control 20C +#define FCFG1_O_PWD_CURR_20C 0x0000039C + +// Power Down Current Control 35C +#define FCFG1_O_PWD_CURR_35C 0x000003A0 + +// Power Down Current Control 50C +#define FCFG1_O_PWD_CURR_50C 0x000003A4 + +// Power Down Current Control 65C +#define FCFG1_O_PWD_CURR_65C 0x000003A8 + +// Power Down Current Control 80C +#define FCFG1_O_PWD_CURR_80C 0x000003AC + +// Power Down Current Control 95C +#define FCFG1_O_PWD_CURR_95C 0x000003B0 + +// Power Down Current Control 110C +#define FCFG1_O_PWD_CURR_110C 0x000003B4 + +// Power Down Current Control 125C +#define FCFG1_O_PWD_CURR_125C 0x000003B8 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_CONF_1 +// +//***************************************************************************** +// Field: [7:0] DEVICE_MINOR_REV +// +// HW minor revision number (a value of 0xFF shall be treated equally to 0x00). +// Any test of this field by SW should be implemented as a 'greater or equal' +// comparison as signed integer. +// Value may change without warning. +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_CONF_2 +// +//***************************************************************************** +// Field: [7:0] HPOSC_COMP_P3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV5 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV6 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV10 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV12 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV15 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV30 +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_S 14 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV5 +// +//***************************************************************************** +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV6 +// +//***************************************************************************** +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV10 +// +//***************************************************************************** +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV12 +// +//***************************************************************************** +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV15 +// +//***************************************************************************** +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV30 +// +//***************************************************************************** +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Trim value for RF Core. +// Value is read by RF Core ROM FW during RF Core initialization. +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV5 +// +//***************************************************************************** +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV6 +// +//***************************************************************************** +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV10 +// +//***************************************************************************** +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV12 +// +//***************************************************************************** +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV15 +// +//***************************************************************************** +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC_DIV30 +// +//***************************************************************************** +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_0 +// +//***************************************************************************** +// Field: [31:0] ID_31_0 +// +// Shadow of DIE_ID_0 register in eFuse row number 3 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_1 +// +//***************************************************************************** +// Field: [31:0] ID_63_32 +// +// Shadow of DIE_ID_1 register in eFuse row number 4 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_2 +// +//***************************************************************************** +// Field: [31:0] ID_95_64 +// +// Shadow of DIE_ID_2 register in eFuse row number 5 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_3 +// +//***************************************************************************** +// Field: [31:0] ID_127_96 +// +// Shadow of DIE_ID_3 register in eFuse row number 6 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM +// +//***************************************************************************** +// Field: [28:27] SET_RCOSC_HF_COARSE_RESISTOR +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_W \ + 2 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_M \ + 0x18000000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_S \ + 27 + +// Field: [26:23] TRIMMAG +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 + +// Field: [22:18] TRIMIREF +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 + +// Field: [17:16] ITRIM_DIG_LDO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 + +// Field: [15:12] VTRIM_DIG +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 + +// Field: [11:8] VTRIM_COARSE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 + +// Field: [7:0] RCOSCHF_CTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_ANA_TRIM +// +//***************************************************************************** +// Field: [26:25] BOD_BANDGAP_TRIM_CNF +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 + +// Field: [24] VDDR_ENABLE_PG1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 + +// Field: [23] VDDR_OK_HYS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 + +// Field: [22:21] IPTAT_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 + +// Field: [20:16] VDDR_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 + +// Field: [15:11] TRIMBOD_INTMODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 + +// Field: [10:6] TRIMBOD_EXTMODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 + +// Field: [5:0] TRIMTEMP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_NUMBER +// +//***************************************************************************** +// Field: [31:0] LOT_NUMBER +// +// Number of the manufacturing lot that produced this unit. +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_COORDINATE +// +//***************************************************************************** +// Field: [31:16] XCOORDINATE +// +// X coordinate of this unit on the wafer. +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 + +// Field: [15:0] YCOORDINATE +// +// Y coordinate of this unit on the wafer. +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_E_P +// +//***************************************************************************** +// Field: [31:24] PSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_PSU_W 8 +#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 +#define FCFG1_FLASH_E_P_PSU_S 24 + +// Field: [23:16] ESU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_ESU_W 8 +#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 +#define FCFG1_FLASH_E_P_ESU_S 16 + +// Field: [15:8] PVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_PVSU_W 8 +#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 +#define FCFG1_FLASH_E_P_PVSU_S 8 + +// Field: [7:0] EVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_EVSU_W 8 +#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF +#define FCFG1_FLASH_E_P_EVSU_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_C_E_P_R +// +//***************************************************************************** +// Field: [31:24] RVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_RVSU_W 8 +#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 +#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 + +// Field: [23:16] PV_ACCESS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 + +// Field: [15:12] A_EXEZ_SETUP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 + +// Field: [11:0] CVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_CVSU_W 12 +#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF +#define FCFG1_FLASH_C_E_P_R_CVSU_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_P_R_PV +// +//***************************************************************************** +// Field: [31:24] PH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PH_W 8 +#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 +#define FCFG1_FLASH_P_R_PV_PH_S 24 + +// Field: [23:16] RH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_RH_W 8 +#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 +#define FCFG1_FLASH_P_R_PV_RH_S 16 + +// Field: [15:8] PVH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PVH_W 8 +#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 +#define FCFG1_FLASH_P_R_PV_PVH_S 8 + +// Field: [7:0] PVH2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PVH2_W 8 +#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF +#define FCFG1_FLASH_P_R_PV_PVH2_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_EH_SEQ +// +//***************************************************************************** +// Field: [31:24] EH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_EH_W 8 +#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 +#define FCFG1_FLASH_EH_SEQ_EH_S 24 + +// Field: [23:16] SEQ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_SEQ_W 8 +#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 +#define FCFG1_FLASH_EH_SEQ_SEQ_S 16 + +// Field: [15:12] VSTAT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 +#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 +#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 + +// Field: [11:0] SM_FREQUENCY +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV_E +// +//***************************************************************************** +// Field: [31:16] VHV_E_START +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 +#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 + +// Field: [15:0] VHV_E_STEP_HIGHT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_PP +// +//***************************************************************************** +// Field: [31:24] PUMP_SU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PP_PUMP_SU_W 8 +#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 +#define FCFG1_FLASH_PP_PUMP_SU_S 24 + +// Field: [15:0] MAX_PP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PP_MAX_PP_W 16 +#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF +#define FCFG1_FLASH_PP_MAX_PP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_PROG_EP +// +//***************************************************************************** +// Field: [31:16] MAX_EP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 +#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 +#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 + +// Field: [15:0] PROGRAM_PW +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_ERA_PW +// +//***************************************************************************** +// Field: [31:0] ERASE_PW +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 +#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF +#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV +// +//***************************************************************************** +// Field: [27:24] TRIM13_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_TRIM13_P_W 4 +#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 +#define FCFG1_FLASH_VHV_TRIM13_P_S 24 + +// Field: [19:16] VHV_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_VHV_P_W 4 +#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 +#define FCFG1_FLASH_VHV_VHV_P_S 16 + +// Field: [11:8] TRIM13_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_TRIM13_E_W 4 +#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 +#define FCFG1_FLASH_VHV_TRIM13_E_S 8 + +// Field: [3:0] VHV_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_VHV_E_W 4 +#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F +#define FCFG1_FLASH_VHV_VHV_E_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV_PV +// +//***************************************************************************** +// Field: [27:24] TRIM13_PV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 + +// Field: [19:16] VHV_PV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 +#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 +#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 + +// Field: [15:8] VCG2P5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 +#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 +#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 + +// Field: [7:0] VINH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VINH_W 8 +#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF +#define FCFG1_FLASH_VHV_PV_VINH_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_V +// +//***************************************************************************** +// Field: [31:24] VSL_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_VSL_P_W 8 +#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 +#define FCFG1_FLASH_V_VSL_P_S 24 + +// Field: [23:16] VWL_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_VWL_P_W 8 +#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 +#define FCFG1_FLASH_V_VWL_P_S 16 + +// Field: [15:8] V_READ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_V_READ_W 8 +#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 +#define FCFG1_FLASH_V_V_READ_S 8 + +//***************************************************************************** +// +// Register: FCFG1_O_USER_ID +// +//***************************************************************************** +// Field: [31:28] PG_REV +// +// Field used to distinguish revisions of the device. +#define FCFG1_USER_ID_PG_REV_W 4 +#define FCFG1_USER_ID_PG_REV_M 0xF0000000 +#define FCFG1_USER_ID_PG_REV_S 28 + +// Field: [27:26] VER +// +// Version number. +// +// 0x0: Bits [25:12] of this register has the stated meaning. +// +// Any other setting indicate a different encoding of these bits. +#define FCFG1_USER_ID_VER_W 2 +#define FCFG1_USER_ID_VER_M 0x0C000000 +#define FCFG1_USER_ID_VER_S 26 + +// Field: [22:19] SEQUENCE +// +// Sequence. +// +// Used to differentiate between marketing/orderable product where other fields +// of USER_ID is the same (temp range, flash size, voltage range etc) +#define FCFG1_USER_ID_SEQUENCE_W 4 +#define FCFG1_USER_ID_SEQUENCE_M 0x00780000 +#define FCFG1_USER_ID_SEQUENCE_S 19 + +// Field: [18:16] PKG +// +// Package type. +// +// 0x0: 4x4mm QFN (RHB) package +// 0x1: 5x5mm QFN (RSM) package +// 0x2: 7x7mm QFN (RGZ) package +// 0x3: Wafer sale package (naked die) +// 0x4: 2.7x2.7mm WCSP (YFV) +// 0x5: 7x7mm QFN package with Wettable Flanks +// +// Other values are reserved for future use. +// Packages available for a specific device are shown in the device datasheet. +#define FCFG1_USER_ID_PKG_W 3 +#define FCFG1_USER_ID_PKG_M 0x00070000 +#define FCFG1_USER_ID_PKG_S 16 + +// Field: [15:12] PROTOCOL +// +// Protocols supported. +// +// 0x1: BLE +// 0x2: RF4CE +// 0x4: Zigbee/6lowpan +// 0x8: Proprietary +// +// More than one protocol can be supported on same device - values above are +// then combined. +#define FCFG1_USER_ID_PROTOCOL_W 4 +#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 +#define FCFG1_USER_ID_PROTOCOL_S 12 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_OTP_DATA3 +// +//***************************************************************************** +// Field: [31:23] EC_STEP_SIZE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 + +// Field: [22] DO_PRECOND +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 + +// Field: [21:18] MAX_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 + +// Field: [17:16] TRIM_1P7 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 + +// Field: [15:8] FLASH_SIZE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 + +// Field: [7:0] WAIT_SYSCODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ANA2_TRIM +// +//***************************************************************************** +// Field: [31] RCOSCHFCTRIMFRACT_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 + +// Field: [30:26] RCOSCHFCTRIMFRACT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 + +// Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 + +// Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 + +// Field: [21:16] NANOAMP_RES_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 6 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F0000 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 16 + +// Field: [11] DITHER_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 +#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_S 11 + +// Field: [10:8] DCDC_IPEAK +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 + +// Field: [7:6] DEAD_TIME_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 + +// Field: [5:3] DCDC_LOW_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 + +// Field: [2:0] DCDC_HIGH_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_LDO_TRIM +// +//***************************************************************************** +// Field: [28:24] VDDR_TRIM_SLEEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 + +// Field: [18:16] GLDO_CURSRC +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 + +// Field: [12:11] ITRIM_DIGLDO_LOAD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 + +// Field: [10:8] ITRIM_UDIGLDO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 + +// Field: [2:0] VTRIM_DELTA +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_BAT_RC_LDO_TRIM +// +//***************************************************************************** +// Field: [27:24] VTRIM_BOD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M 0x0F000000 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_S 24 + +// Field: [19:16] VTRIM_UDIG +// +// Internal. Only to be used through TI provided API. +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M 0x000F0000 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_S 16 + +// Field: [11:8] RCOSCHF_ITUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_M 0x00000F00 +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_S 8 + +// Field: [1:0] MEASUREPER +// +// Internal. Only to be used through TI provided API. +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_W 2 +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_M 0x00000003 +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_BLE_0 +// +//***************************************************************************** +// Field: [31:0] ADDR_0_31 +// +// The first 32-bits of the 64-bit MAC BLE address +#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 +#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_BLE_1 +// +//***************************************************************************** +// Field: [31:0] ADDR_32_63 +// +// The last 32-bits of the 64-bit MAC BLE address +#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 +#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_15_4_0 +// +//***************************************************************************** +// Field: [31:0] ADDR_0_31 +// +// The first 32-bits of the 64-bit MAC 15.4 address +#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 +#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_15_4_1 +// +//***************************************************************************** +// Field: [31:0] ADDR_32_63 +// +// The last 32-bits of the 64-bit MAC 15.4 address +#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 +#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_OTP_DATA4 +// +//***************************************************************************** +// Field: [31] STANDBY_MODE_SEL_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 + +// Field: [30:29] STANDBY_PW_SEL_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 + +// Field: [28] DIS_STANDBY_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 + +// Field: [27] DIS_IDLE_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 + +// Field: [26:24] VIN_AT_X_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 + +// Field: [23] STANDBY_MODE_SEL_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 + +// Field: [22:21] STANDBY_PW_SEL_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 + +// Field: [20] DIS_STANDBY_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 + +// Field: [19] DIS_IDLE_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 + +// Field: [18:16] VIN_AT_X_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 + +// Field: [15] STANDBY_MODE_SEL_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 + +// Field: [14:13] STANDBY_PW_SEL_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 + +// Field: [12] DIS_STANDBY_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 + +// Field: [11] DIS_IDLE_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 + +// Field: [10:8] VIN_AT_X_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 + +// Field: [7] STANDBY_MODE_SEL_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 + +// Field: [6:5] STANDBY_PW_SEL_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 + +// Field: [4] DIS_STANDBY_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 + +// Field: [3] DIS_IDLE_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 + +// Field: [2:0] VIN_AT_X_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_TRIM +// +//***************************************************************************** +// Field: [7:0] TEMPVSLOPE +// +// Signed byte value representing the TEMP slope with battery voltage, in +// degrees C / V, with four fractional bits. +#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 +#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF +#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_RCOSC_HF_TEMPCOMP +// +//***************************************************************************** +// Field: [31:24] FINE_RESISTOR +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 + +// Field: [23:16] CTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 + +// Field: [15:8] CTRIMFRACT_QUAD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 + +// Field: [7:0] CTRIMFRACT_SLOPE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_TRIM_CAL_REVISION +// +//***************************************************************************** +// Field: [31:16] FT1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_TRIM_CAL_REVISION_FT1_W 16 +#define FCFG1_TRIM_CAL_REVISION_FT1_M 0xFFFF0000 +#define FCFG1_TRIM_CAL_REVISION_FT1_S 16 + +// Field: [15:0] MP1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_TRIM_CAL_REVISION_MP1_W 16 +#define FCFG1_TRIM_CAL_REVISION_MP1_M 0x0000FFFF +#define FCFG1_TRIM_CAL_REVISION_MP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ICEPICK_DEVICE_ID +// +//***************************************************************************** +// Field: [31:28] PG_REV +// +// Field used to distinguish revisions of the device. +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 + +// Field: [27:12] WAFER_ID +// +// Field used to identify silicon die. +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 + +// Field: [11:0] MANUFACTURER_ID +// +// Manufacturer code. +// +// 0x02F: Texas Instruments +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FCFG1_REVISION +// +//***************************************************************************** +// Field: [31:0] REV +// +// The revision number of the FCFG1 layout. This value will be read by +// application SW in order to determine which FCFG1 parameters that have valid +// values. This revision number must be incremented by 1 before any devices are +// to be produced if the FCFG1 layout has changed since the previous production +// of devices. +// Value migth change without warning. +#define FCFG1_FCFG1_REVISION_REV_W 32 +#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF +#define FCFG1_FCFG1_REVISION_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_OTP_DATA +// +//***************************************************************************** +// Field: [31:28] RCOSC_HF_ITUNE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 + +// Field: [27:20] RCOSC_HF_CRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 + +// Field: [19:15] PER_M +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_PER_M_W 5 +#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 +#define FCFG1_MISC_OTP_DATA_PER_M_S 15 + +// Field: [14:12] PER_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_PER_E_W 3 +#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 +#define FCFG1_MISC_OTP_DATA_PER_E_S 12 + +// Field: [11:8] PO_TAIL_RES_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_W 4 +#define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_M 0x00000F00 +#define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_S 8 + +// Field: [7:0] TEST_PROGRAM_REV +// +// The revision of the test program used in the production process when FCFG1 +// was programmed. +// Value migth change without warning. +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_W 8 +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_M 0x000000FF +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_IOCONF +// +//***************************************************************************** +// Field: [6:0] GPIO_CNT +// +// Number of available DIOs. +#define FCFG1_IOCONF_GPIO_CNT_W 7 +#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F +#define FCFG1_IOCONF_GPIO_CNT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_IF_ADC +// +//***************************************************************************** +// Field: [31:28] FF2ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 + +// Field: [27:24] FF3ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 + +// Field: [23:20] INT3ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 + +// Field: [19:16] FF1ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 + +// Field: [15:14] AAFCAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 + +// Field: [13:10] INT2ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 + +// Field: [9:5] IFDIGLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 + +// Field: [4:0] IFANALDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_OSC_TOP +// +//***************************************************************************** +// Field: [29:26] XOSC_HF_ROW_Q12 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 + +// Field: [25:10] XOSC_HF_COLUMN_Q12 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 + +// Field: [9:2] RCOSCLF_CTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 + +// Field: [1:0] RCOSCLF_RTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_FRONTEND +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_S 14 + +// Field: [13] PATRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N 0x00002000 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_BITN 13 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_M 0x00002000 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_S 13 + +// Field: [6:0] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH +// +//***************************************************************************** +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5:0] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_ABS_GAIN +// +//***************************************************************************** +// Field: [15:0] SOC_ADC_ABS_GAIN_TEMP1 +// +// SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated +// in production test.. +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_REL_GAIN +// +//***************************************************************************** +// Field: [15:0] SOC_ADC_REL_GAIN_TEMP1 +// +// SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated +// in production test.. +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_OFFSET_INT +// +//***************************************************************************** +// Field: [23:16] SOC_ADC_REL_OFFSET_TEMP1 +// +// SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed +// 8-bit number. Calculated in production test.. +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 + +// Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1 +// +// SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed +// 8-bit number. Calculated in production test.. +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT +// +//***************************************************************************** +// Field: [5:0] SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_W \ + 6 +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_M \ + 0x0000003F +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S \ + 0 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_TH1 +// +//***************************************************************************** +// Field: [23:18] HPMRAMP3_LTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 + +// Field: [15:10] HPMRAMP3_HTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 + +// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 + +// Field: [5:0] HPMRAMP1_TH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_TH2 +// +//***************************************************************************** +// Field: [31:26] LPMUPDATE_LTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 + +// Field: [23:18] LPMUPDATE_HTM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 + +// Field: [15:10] ADC_COMP_AMPTH_LPM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 + +// Field: [7:2] ADC_COMP_AMPTH_HPM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_CTRL1 +// +//***************************************************************************** +// Field: [30] AMPCOMP_REQ_MODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 + +// Field: [23:20] IBIAS_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 + +// Field: [19:16] IBIAS_INIT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 + +// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 + +// Field: [7:4] CAP_STEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 + +// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ANABYPASS_VALUE2 +// +//***************************************************************************** +// Field: [13:0] XOSC_HF_IBIASTHERM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_MISC_ADC +// +//***************************************************************************** +// Field: [17] RSSITRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N 0x00020000 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_BITN 17 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_M 0x00020000 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_S 17 + +// Field: [16:9] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_VOLT_TRIM +// +//***************************************************************************** +// Field: [28:24] VDDR_TRIM_HH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 + +// Field: [20:16] VDDR_TRIM_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 + +// Field: [12:8] VDDR_TRIM_SLEEP_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 + +// Field: [4:0] TRIMBOD_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 +#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F +#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_OSC_CONF +// +//***************************************************************************** +// Field: [29] ADC_SH_VBUF_EN +// +// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 + +// Field: [28] ADC_SH_MODE_EN +// +// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 + +// Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM +// +// Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 + +// Field: [26:25] XOSCLF_REGULATOR_TRIM +// +// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 + +// Field: [24:21] XOSCLF_CMIRRWR_RATIO +// +// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 + +// Field: [20:19] XOSC_HF_FAST_START +// +// Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 + +// Field: [18] XOSC_OPTION +// +// 0: XOSC_HF unavailable (may not be bonded out) +// 1: XOSC_HF available (default) +#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 +#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_S 18 + +// Field: [17] HPOSC_OPTION +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 +#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 + +// Field: [16] HPOSC_BIAS_HOLD_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 + +// Field: [15:12] HPOSC_CURRMIRR_RATIO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 + +// Field: [11:8] HPOSC_BIAS_RES_SET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 + +// Field: [7] HPOSC_FILTER_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 + +// Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 + +// Field: [2:1] HPOSC_SERIES_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 + +// Field: [0] HPOSC_DIV3_BYPASS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FREQ_OFFSET +// +//***************************************************************************** +// Field: [31:16] HPOSC_COMP_P0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 + +// Field: [15:8] HPOSC_COMP_P1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 + +// Field: [7:0] HPOSC_COMP_P2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CAP_TRIM +// +//***************************************************************************** +// Field: [31:16] FLUX_CAP_0P28_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_W 16 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_M 0xFFFF0000 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_S 16 + +// Field: [15:0] FLUX_CAP_0P4_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_W 16 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_M 0x0000FFFF +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_OTP_DATA_1 +// +//***************************************************************************** +// Field: [28:27] PEAK_DET_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 + +// Field: [26:24] HP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 + +// Field: [23:22] LP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 + +// Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 + +// Field: [19:10] HPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 + +// Field: [9:4] LPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 + +// Field: [3:0] IDAC_STEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_20C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_20C_BASELINE_W 8 +#define FCFG1_PWD_CURR_20C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_20C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_35C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_35C_BASELINE_W 8 +#define FCFG1_PWD_CURR_35C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_35C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_50C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_50C_BASELINE_W 8 +#define FCFG1_PWD_CURR_50C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_50C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_65C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_65C_BASELINE_W 8 +#define FCFG1_PWD_CURR_65C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_65C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_80C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_80C_BASELINE_W 8 +#define FCFG1_PWD_CURR_80C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_80C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_95C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_95C_BASELINE_W 8 +#define FCFG1_PWD_CURR_95C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_95C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_110C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_110C_BASELINE_W 8 +#define FCFG1_PWD_CURR_110C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_110C_BASELINE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_PWD_CURR_125C +// +//***************************************************************************** +// Field: [31:24] DELTA_CACHE_REF +// +// Additional maximum current, in units of 1uA, with cache retention +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_S 24 + +// Field: [23:16] DELTA_RFMEM_RET +// +// Additional maximum current, in 1uA units, with RF memory retention +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_S 16 + +// Field: [15:8] DELTA_XOSC_LPM +// +// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power +// mode +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_S 8 + +// Field: [7:0] BASELINE +// +// Worst-case baseline maximum powerdown current, in units of 0.5uA +#define FCFG1_PWD_CURR_125C_BASELINE_W 8 +#define FCFG1_PWD_CURR_125C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_125C_BASELINE_S 0 + + +#endif // __FCFG1__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_flash.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_flash.h new file mode 100644 index 0000000..03ce768 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_flash.h @@ -0,0 +1,3475 @@ +/****************************************************************************** +* Filename: hw_flash_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// FLASH component +// +//***************************************************************************** +// FMC and Efuse Status +#define FLASH_O_STAT 0x0000001C + +// Internal +#define FLASH_O_CFG 0x00000024 + +// Internal +#define FLASH_O_SYSCODE_START 0x00000028 + +// Internal +#define FLASH_O_FLASH_SIZE 0x0000002C + +// Internal +#define FLASH_O_FWLOCK 0x0000003C + +// Internal +#define FLASH_O_FWFLAG 0x00000040 + +// Internal +#define FLASH_O_EFUSE 0x00001000 + +// Internal +#define FLASH_O_EFUSEADDR 0x00001004 + +// Internal +#define FLASH_O_DATAUPPER 0x00001008 + +// Internal +#define FLASH_O_DATALOWER 0x0000100C + +// Internal +#define FLASH_O_EFUSECFG 0x00001010 + +// Internal +#define FLASH_O_EFUSESTAT 0x00001014 + +// Internal +#define FLASH_O_ACC 0x00001018 + +// Internal +#define FLASH_O_BOUNDARY 0x0000101C + +// Internal +#define FLASH_O_EFUSEFLAG 0x00001020 + +// Internal +#define FLASH_O_EFUSEKEY 0x00001024 + +// Internal +#define FLASH_O_EFUSERELEASE 0x00001028 + +// Internal +#define FLASH_O_EFUSEPINS 0x0000102C + +// Internal +#define FLASH_O_EFUSECRA 0x00001030 + +// Internal +#define FLASH_O_EFUSEREAD 0x00001034 + +// Internal +#define FLASH_O_EFUSEPROGRAM 0x00001038 + +// Internal +#define FLASH_O_EFUSEERROR 0x0000103C + +// Internal +#define FLASH_O_SINGLEBIT 0x00001040 + +// Internal +#define FLASH_O_TWOBIT 0x00001044 + +// Internal +#define FLASH_O_SELFTESTCYC 0x00001048 + +// Internal +#define FLASH_O_SELFTESTSIGN 0x0000104C + +// Internal +#define FLASH_O_FRDCTL 0x00002000 + +// Internal +#define FLASH_O_FSPRD 0x00002004 + +// Internal +#define FLASH_O_FEDACCTL1 0x00002008 + +// Internal +#define FLASH_O_FEDACSTAT 0x0000201C + +// Internal +#define FLASH_O_FBPROT 0x00002030 + +// Internal +#define FLASH_O_FBSE 0x00002034 + +// Internal +#define FLASH_O_FBBUSY 0x00002038 + +// Internal +#define FLASH_O_FBAC 0x0000203C + +// Internal +#define FLASH_O_FBFALLBACK 0x00002040 + +// Internal +#define FLASH_O_FBPRDY 0x00002044 + +// Internal +#define FLASH_O_FPAC1 0x00002048 + +// Internal +#define FLASH_O_FPAC2 0x0000204C + +// Internal +#define FLASH_O_FMAC 0x00002050 + +// Internal +#define FLASH_O_FMSTAT 0x00002054 + +// Internal +#define FLASH_O_FLOCK 0x00002064 + +// Internal +#define FLASH_O_FVREADCT 0x00002080 + +// Internal +#define FLASH_O_FVHVCT1 0x00002084 + +// Internal +#define FLASH_O_FVHVCT2 0x00002088 + +// Internal +#define FLASH_O_FVHVCT3 0x0000208C + +// Internal +#define FLASH_O_FVNVCT 0x00002090 + +// Internal +#define FLASH_O_FVSLP 0x00002094 + +// Internal +#define FLASH_O_FVWLCT 0x00002098 + +// Internal +#define FLASH_O_FEFUSECTL 0x0000209C + +// Internal +#define FLASH_O_FEFUSESTAT 0x000020A0 + +// Internal +#define FLASH_O_FEFUSEDATA 0x000020A4 + +// Internal +#define FLASH_O_FSEQPMP 0x000020A8 + +// Internal +#define FLASH_O_FBSTROBES 0x00002100 + +// Internal +#define FLASH_O_FPSTROBES 0x00002104 + +// Internal +#define FLASH_O_FBMODE 0x00002108 + +// Internal +#define FLASH_O_FTCR 0x0000210C + +// Internal +#define FLASH_O_FADDR 0x00002110 + +// Internal +#define FLASH_O_FTCTL 0x0000211C + +// Internal +#define FLASH_O_FWPWRITE0 0x00002120 + +// Internal +#define FLASH_O_FWPWRITE1 0x00002124 + +// Internal +#define FLASH_O_FWPWRITE2 0x00002128 + +// Internal +#define FLASH_O_FWPWRITE3 0x0000212C + +// Internal +#define FLASH_O_FWPWRITE4 0x00002130 + +// Internal +#define FLASH_O_FWPWRITE5 0x00002134 + +// Internal +#define FLASH_O_FWPWRITE6 0x00002138 + +// Internal +#define FLASH_O_FWPWRITE7 0x0000213C + +// Internal +#define FLASH_O_FWPWRITE_ECC 0x00002140 + +// Internal +#define FLASH_O_FSWSTAT 0x00002144 + +// Internal +#define FLASH_O_FSM_GLBCTL 0x00002200 + +// Internal +#define FLASH_O_FSM_STATE 0x00002204 + +// Internal +#define FLASH_O_FSM_STAT 0x00002208 + +// Internal +#define FLASH_O_FSM_CMD 0x0000220C + +// Internal +#define FLASH_O_FSM_PE_OSU 0x00002210 + +// Internal +#define FLASH_O_FSM_VSTAT 0x00002214 + +// Internal +#define FLASH_O_FSM_PE_VSU 0x00002218 + +// Internal +#define FLASH_O_FSM_CMP_VSU 0x0000221C + +// Internal +#define FLASH_O_FSM_EX_VAL 0x00002220 + +// Internal +#define FLASH_O_FSM_RD_H 0x00002224 + +// Internal +#define FLASH_O_FSM_P_OH 0x00002228 + +// Internal +#define FLASH_O_FSM_ERA_OH 0x0000222C + +// Internal +#define FLASH_O_FSM_SAV_PPUL 0x00002230 + +// Internal +#define FLASH_O_FSM_PE_VH 0x00002234 + +// Internal +#define FLASH_O_FSM_PRG_PW 0x00002240 + +// Internal +#define FLASH_O_FSM_ERA_PW 0x00002244 + +// Internal +#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254 + +// Internal +#define FLASH_O_FSM_TIMER 0x00002258 + +// Internal +#define FLASH_O_FSM_MODE 0x0000225C + +// Internal +#define FLASH_O_FSM_PGM 0x00002260 + +// Internal +#define FLASH_O_FSM_ERA 0x00002264 + +// Internal +#define FLASH_O_FSM_PRG_PUL 0x00002268 + +// Internal +#define FLASH_O_FSM_ERA_PUL 0x0000226C + +// Internal +#define FLASH_O_FSM_STEP_SIZE 0x00002270 + +// Internal +#define FLASH_O_FSM_PUL_CNTR 0x00002274 + +// Internal +#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 + +// Internal +#define FLASH_O_FSM_ST_MACHINE 0x0000227C + +// Internal +#define FLASH_O_FSM_FLES 0x00002280 + +// Internal +#define FLASH_O_FSM_WR_ENA 0x00002288 + +// Internal +#define FLASH_O_FSM_ACC_PP 0x0000228C + +// Internal +#define FLASH_O_FSM_ACC_EP 0x00002290 + +// Internal +#define FLASH_O_FSM_ADDR 0x000022A0 + +// Internal +#define FLASH_O_FSM_SECTOR 0x000022A4 + +// Internal +#define FLASH_O_FMC_REV_ID 0x000022A8 + +// Internal +#define FLASH_O_FSM_ERR_ADDR 0x000022AC + +// Internal +#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0 + +// Internal +#define FLASH_O_FSM_EXECUTE 0x000022B4 + +// Internal +#define FLASH_O_FSM_SECTOR1 0x000022C0 + +// Internal +#define FLASH_O_FSM_SECTOR2 0x000022C4 + +// Internal +#define FLASH_O_FSM_BSLE0 0x000022E0 + +// Internal +#define FLASH_O_FSM_BSLE1 0x000022E4 + +// Internal +#define FLASH_O_FSM_BSLP0 0x000022F0 + +// Internal +#define FLASH_O_FSM_BSLP1 0x000022F4 + +// Internal +#define FLASH_O_FCFG_BANK 0x00002400 + +// Internal +#define FLASH_O_FCFG_WRAPPER 0x00002404 + +// Internal +#define FLASH_O_FCFG_BNK_TYPE 0x00002408 + +// Internal +#define FLASH_O_FCFG_B0_START 0x00002410 + +// Internal +#define FLASH_O_FCFG_B1_START 0x00002414 + +// Internal +#define FLASH_O_FCFG_B2_START 0x00002418 + +// Internal +#define FLASH_O_FCFG_B3_START 0x0000241C + +// Internal +#define FLASH_O_FCFG_B4_START 0x00002420 + +// Internal +#define FLASH_O_FCFG_B5_START 0x00002424 + +// Internal +#define FLASH_O_FCFG_B6_START 0x00002428 + +// Internal +#define FLASH_O_FCFG_B7_START 0x0000242C + +// Internal +#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 + +//***************************************************************************** +// +// Register: FLASH_O_STAT +// +//***************************************************************************** +// Field: [15] EFUSE_BLANK +// +// Efuse scanning detected if fuse ROM is blank: +// 0 : Not blank +// 1 : Blank +#define FLASH_STAT_EFUSE_BLANK 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_BITN 15 +#define FLASH_STAT_EFUSE_BLANK_M 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_S 15 + +// Field: [14] EFUSE_TIMEOUT +// +// Efuse scanning resulted in timeout error. +// 0 : No Timeout error +// 1 : Timeout Error +#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14 +#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_S 14 + +// Field: [13] EFUSE_CRC_ERROR +// +// Efuse scanning resulted in scan chain CRC error. +// 0 : No CRC error +// 1 : CRC Error +#define FLASH_STAT_EFUSE_CRC_ERROR 0x00002000 +#define FLASH_STAT_EFUSE_CRC_ERROR_BITN 13 +#define FLASH_STAT_EFUSE_CRC_ERROR_M 0x00002000 +#define FLASH_STAT_EFUSE_CRC_ERROR_S 13 + +// Field: [12:8] EFUSE_ERRCODE +// +// Same as EFUSEERROR.CODE +#define FLASH_STAT_EFUSE_ERRCODE_W 5 +#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00 +#define FLASH_STAT_EFUSE_ERRCODE_S 8 + +// Field: [2] SAMHOLD_DIS +// +// Status indicator of flash sample and hold sequencing logic. This bit will go +// to 1 some delay after CFG.DIS_IDLE is set to 1. +// 0: Not disabled +// 1: Sample and hold disabled and stable +#define FLASH_STAT_SAMHOLD_DIS 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_BITN 2 +#define FLASH_STAT_SAMHOLD_DIS_M 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_S 2 + +// Field: [1] BUSY +// +// Fast version of the FMC FMSTAT.BUSY bit. +// This flag is valid immediately after the operation setting it (FMSTAT.BUSY +// is delayed some cycles) +// 0 : Not busy +// 1 : Busy +#define FLASH_STAT_BUSY 0x00000002 +#define FLASH_STAT_BUSY_BITN 1 +#define FLASH_STAT_BUSY_M 0x00000002 +#define FLASH_STAT_BUSY_S 1 + +// Field: [0] POWER_MODE +// +// Power state of the flash sub-system. +// 0 : Active +// 1 : Low power +#define FLASH_STAT_POWER_MODE 0x00000001 +#define FLASH_STAT_POWER_MODE_BITN 0 +#define FLASH_STAT_POWER_MODE_M 0x00000001 +#define FLASH_STAT_POWER_MODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_CFG +// +//***************************************************************************** +// Field: [8] STANDBY_MODE_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8 +#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_S 8 + +// Field: [7:6] STANDBY_PW_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_STANDBY_PW_SEL_W 2 +#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 +#define FLASH_CFG_STANDBY_PW_SEL_S 6 + +// Field: [5] DIS_EFUSECLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_EFUSECLK 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_BITN 5 +#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_S 5 + +// Field: [4] DIS_READACCESS +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_READACCESS 0x00000010 +#define FLASH_CFG_DIS_READACCESS_BITN 4 +#define FLASH_CFG_DIS_READACCESS_M 0x00000010 +#define FLASH_CFG_DIS_READACCESS_S 4 + +// Field: [3] ENABLE_SWINTF +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_ENABLE_SWINTF 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_BITN 3 +#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_S 3 + +// Field: [1] DIS_STANDBY +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_STANDBY 0x00000002 +#define FLASH_CFG_DIS_STANDBY_BITN 1 +#define FLASH_CFG_DIS_STANDBY_M 0x00000002 +#define FLASH_CFG_DIS_STANDBY_S 1 + +// Field: [0] DIS_IDLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_IDLE 0x00000001 +#define FLASH_CFG_DIS_IDLE_BITN 0 +#define FLASH_CFG_DIS_IDLE_M 0x00000001 +#define FLASH_CFG_DIS_IDLE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SYSCODE_START +// +//***************************************************************************** +// Field: [4:0] SYSCODE_START +// +// Internal. Only to be used through TI provided API. +#define FLASH_SYSCODE_START_SYSCODE_START_W 5 +#define FLASH_SYSCODE_START_SYSCODE_START_M 0x0000001F +#define FLASH_SYSCODE_START_SYSCODE_START_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FLASH_SIZE +// +//***************************************************************************** +// Field: [7:0] SECTORS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FLASH_SIZE_SECTORS_W 8 +#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF +#define FLASH_FLASH_SIZE_SECTORS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWLOCK +// +//***************************************************************************** +// Field: [2:0] FWLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWLOCK_FWLOCK_W 3 +#define FLASH_FWLOCK_FWLOCK_M 0x00000007 +#define FLASH_FWLOCK_FWLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWFLAG +// +//***************************************************************************** +// Field: [2:0] FWFLAG +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWFLAG_FWFLAG_W 3 +#define FLASH_FWFLAG_FWFLAG_M 0x00000007 +#define FLASH_FWFLAG_FWFLAG_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSE +// +//***************************************************************************** +// Field: [28:24] INSTRUCTION +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSE_INSTRUCTION_W 5 +#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000 +#define FLASH_EFUSE_INSTRUCTION_S 24 + +// Field: [15:0] DUMPWORD +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSE_DUMPWORD_W 16 +#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF +#define FLASH_EFUSE_DUMPWORD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEADDR +// +//***************************************************************************** +// Field: [15:11] BLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEADDR_BLOCK_W 5 +#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800 +#define FLASH_EFUSEADDR_BLOCK_S 11 + +// Field: [10:0] ROW +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEADDR_ROW_W 11 +#define FLASH_EFUSEADDR_ROW_M 0x000007FF +#define FLASH_EFUSEADDR_ROW_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_DATAUPPER +// +//***************************************************************************** +// Field: [7:3] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_SPARE_W 5 +#define FLASH_DATAUPPER_SPARE_M 0x000000F8 +#define FLASH_DATAUPPER_SPARE_S 3 + +// Field: [2] P +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_P 0x00000004 +#define FLASH_DATAUPPER_P_BITN 2 +#define FLASH_DATAUPPER_P_M 0x00000004 +#define FLASH_DATAUPPER_P_S 2 + +// Field: [1] R +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_R 0x00000002 +#define FLASH_DATAUPPER_R_BITN 1 +#define FLASH_DATAUPPER_R_M 0x00000002 +#define FLASH_DATAUPPER_R_S 1 + +// Field: [0] EEN +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_EEN 0x00000001 +#define FLASH_DATAUPPER_EEN_BITN 0 +#define FLASH_DATAUPPER_EEN_M 0x00000001 +#define FLASH_DATAUPPER_EEN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_DATALOWER +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATALOWER_DATA_W 32 +#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF +#define FLASH_DATALOWER_DATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSECFG +// +//***************************************************************************** +// Field: [8] IDLEGATING +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_IDLEGATING 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_BITN 8 +#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_S 8 + +// Field: [4:3] SLAVEPOWER +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_SLAVEPOWER_W 2 +#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018 +#define FLASH_EFUSECFG_SLAVEPOWER_S 3 + +// Field: [0] GATING +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_GATING 0x00000001 +#define FLASH_EFUSECFG_GATING_BITN 0 +#define FLASH_EFUSECFG_GATING_M 0x00000001 +#define FLASH_EFUSECFG_GATING_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSESTAT +// +//***************************************************************************** +// Field: [0] RESETDONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSESTAT_RESETDONE 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_BITN 0 +#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_ACC +// +//***************************************************************************** +// Field: [23:0] ACCUMULATOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_ACC_ACCUMULATOR_W 24 +#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF +#define FLASH_ACC_ACCUMULATOR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_BOUNDARY +// +//***************************************************************************** +// Field: [23] DISROW0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_DISROW0 0x00800000 +#define FLASH_BOUNDARY_DISROW0_BITN 23 +#define FLASH_BOUNDARY_DISROW0_M 0x00800000 +#define FLASH_BOUNDARY_DISROW0_S 23 + +// Field: [22] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SPARE 0x00400000 +#define FLASH_BOUNDARY_SPARE_BITN 22 +#define FLASH_BOUNDARY_SPARE_M 0x00400000 +#define FLASH_BOUNDARY_SPARE_S 22 + +// Field: [21] EFC_SELF_TEST_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21 + +// Field: [20] EFC_INSTRUCTION_INFO +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20 + +// Field: [19] EFC_INSTRUCTION_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19 + +// Field: [18] EFC_AUTOLOAD_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18 + +// Field: [17:14] OUTPUTENABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_OUTPUTENABLE_W 4 +#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000 +#define FLASH_BOUNDARY_OUTPUTENABLE_S 14 + +// Field: [13] SYS_ECC_SELF_TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13 + +// Field: [12] SYS_ECC_OVERRIDE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12 + +// Field: [11] EFC_FDI +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_FDI 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_BITN 11 +#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_S 11 + +// Field: [10] SYS_DIEID_AUTOLOAD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10 + +// Field: [9:8] SYS_REPAIR_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8 + +// Field: [7:4] SYS_WS_READ_STATES +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4 + +// Field: [3:0] INPUTENABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_INPUTENABLE_W 4 +#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F +#define FLASH_BOUNDARY_INPUTENABLE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEFLAG +// +//***************************************************************************** +// Field: [0] KEY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEFLAG_KEY 0x00000001 +#define FLASH_EFUSEFLAG_KEY_BITN 0 +#define FLASH_EFUSEFLAG_KEY_M 0x00000001 +#define FLASH_EFUSEFLAG_KEY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEKEY +// +//***************************************************************************** +// Field: [31:0] CODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEKEY_CODE_W 32 +#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF +#define FLASH_EFUSEKEY_CODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSERELEASE +// +//***************************************************************************** +// Field: [31:25] ODPYEAR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPYEAR_W 7 +#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000 +#define FLASH_EFUSERELEASE_ODPYEAR_S 25 + +// Field: [24:21] ODPMONTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPMONTH_W 4 +#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000 +#define FLASH_EFUSERELEASE_ODPMONTH_S 21 + +// Field: [20:16] ODPDAY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPDAY_W 5 +#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000 +#define FLASH_EFUSERELEASE_ODPDAY_S 16 + +// Field: [15:9] EFUSEYEAR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7 +#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00 +#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9 + +// Field: [8:5] EFUSEMONTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4 +#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0 +#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5 + +// Field: [4:0] EFUSEDAY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEDAY_W 5 +#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F +#define FLASH_EFUSERELEASE_EFUSEDAY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEPINS +// +//***************************************************************************** +// Field: [15] EFC_SELF_TEST_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15 + +// Field: [14] EFC_SELF_TEST_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14 + +// Field: [13] SYS_ECC_SELF_TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13 + +// Field: [12] EFC_INSTRUCTION_INFO +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12 + +// Field: [11] EFC_INSTRUCTION_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11 + +// Field: [10] EFC_AUTOLOAD_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10 + +// Field: [9] SYS_ECC_OVERRIDE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9 + +// Field: [8] EFC_READY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_READY 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_BITN 8 +#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_S 8 + +// Field: [7] EFC_FCLRZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7 +#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7 + +// Field: [6] SYS_DIEID_AUTOLOAD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6 + +// Field: [5:4] SYS_REPAIR_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4 + +// Field: [3:0] SYS_WS_READ_STATES +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4 +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSECRA +// +//***************************************************************************** +// Field: [5:0] DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECRA_DATA_W 6 +#define FLASH_EFUSECRA_DATA_M 0x0000003F +#define FLASH_EFUSECRA_DATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEREAD +// +//***************************************************************************** +// Field: [9:8] DATABIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_DATABIT_W 2 +#define FLASH_EFUSEREAD_DATABIT_M 0x00000300 +#define FLASH_EFUSEREAD_DATABIT_S 8 + +// Field: [7:4] READCLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_READCLOCK_W 4 +#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0 +#define FLASH_EFUSEREAD_READCLOCK_S 4 + +// Field: [3] DEBUG +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_DEBUG 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_BITN 3 +#define FLASH_EFUSEREAD_DEBUG_M 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_S 3 + +// Field: [2] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_SPARE 0x00000004 +#define FLASH_EFUSEREAD_SPARE_BITN 2 +#define FLASH_EFUSEREAD_SPARE_M 0x00000004 +#define FLASH_EFUSEREAD_SPARE_S 2 + +// Field: [1:0] MARGIN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_MARGIN_W 2 +#define FLASH_EFUSEREAD_MARGIN_M 0x00000003 +#define FLASH_EFUSEREAD_MARGIN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEPROGRAM +// +//***************************************************************************** +// Field: [30] COMPAREDISABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30 + +// Field: [29:14] CLOCKSTALL +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14 + +// Field: [13] VPPTOVDD +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13 + +// Field: [12:9] ITERATIONS +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4 +#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00 +#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9 + +// Field: [8:0] WRITECLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9 +#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF +#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEERROR +// +//***************************************************************************** +// Field: [5] DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEERROR_DONE 0x00000020 +#define FLASH_EFUSEERROR_DONE_BITN 5 +#define FLASH_EFUSEERROR_DONE_M 0x00000020 +#define FLASH_EFUSEERROR_DONE_S 5 + +// Field: [4:0] CODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEERROR_CODE_W 5 +#define FLASH_EFUSEERROR_CODE_M 0x0000001F +#define FLASH_EFUSEERROR_CODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SINGLEBIT +// +//***************************************************************************** +// Field: [31:1] FROMN +// +// Internal. Only to be used through TI provided API. +#define FLASH_SINGLEBIT_FROMN_W 31 +#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE +#define FLASH_SINGLEBIT_FROMN_S 1 + +// Field: [0] FROM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_SINGLEBIT_FROM0 0x00000001 +#define FLASH_SINGLEBIT_FROM0_BITN 0 +#define FLASH_SINGLEBIT_FROM0_M 0x00000001 +#define FLASH_SINGLEBIT_FROM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_TWOBIT +// +//***************************************************************************** +// Field: [31:1] FROMN +// +// Internal. Only to be used through TI provided API. +#define FLASH_TWOBIT_FROMN_W 31 +#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE +#define FLASH_TWOBIT_FROMN_S 1 + +// Field: [0] FROM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_TWOBIT_FROM0 0x00000001 +#define FLASH_TWOBIT_FROM0_BITN 0 +#define FLASH_TWOBIT_FROM0_M 0x00000001 +#define FLASH_TWOBIT_FROM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SELFTESTCYC +// +//***************************************************************************** +// Field: [31:0] CYCLES +// +// Internal. Only to be used through TI provided API. +#define FLASH_SELFTESTCYC_CYCLES_W 32 +#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF +#define FLASH_SELFTESTCYC_CYCLES_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SELFTESTSIGN +// +//***************************************************************************** +// Field: [31:0] SIGNATURE +// +// Internal. Only to be used through TI provided API. +#define FLASH_SELFTESTSIGN_SIGNATURE_W 32 +#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF +#define FLASH_SELFTESTSIGN_SIGNATURE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FRDCTL +// +//***************************************************************************** +// Field: [11:8] RWAIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FRDCTL_RWAIT_W 4 +#define FLASH_FRDCTL_RWAIT_M 0x00000F00 +#define FLASH_FRDCTL_RWAIT_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSPRD +// +//***************************************************************************** +// Field: [15:8] RMBSEM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RMBSEM_W 8 +#define FLASH_FSPRD_RMBSEM_M 0x0000FF00 +#define FLASH_FSPRD_RMBSEM_S 8 + +// Field: [1] RM1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RM1 0x00000002 +#define FLASH_FSPRD_RM1_BITN 1 +#define FLASH_FSPRD_RM1_M 0x00000002 +#define FLASH_FSPRD_RM1_S 1 + +// Field: [0] RM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RM0 0x00000001 +#define FLASH_FSPRD_RM0_BITN 0 +#define FLASH_FSPRD_RM0_M 0x00000001 +#define FLASH_FSPRD_RM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEDACCTL1 +// +//***************************************************************************** +// Field: [24] SUSP_IGNR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24 +#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_S 24 + +//***************************************************************************** +// +// Register: FLASH_O_FEDACSTAT +// +//***************************************************************************** +// Field: [25] RVF_INT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACSTAT_RVF_INT 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_BITN 25 +#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_S 25 + +// Field: [24] FSM_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACSTAT_FSM_DONE 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_BITN 24 +#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_S 24 + +//***************************************************************************** +// +// Register: FLASH_O_FBPROT +// +//***************************************************************************** +// Field: [0] PROTL1DIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPROT_PROTL1DIS 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_BITN 0 +#define FLASH_FBPROT_PROTL1DIS_M 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBSE +// +//***************************************************************************** +// Field: [15:0] BSE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSE_BSE_W 16 +#define FLASH_FBSE_BSE_M 0x0000FFFF +#define FLASH_FBSE_BSE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBBUSY +// +//***************************************************************************** +// Field: [7:0] BUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBBUSY_BUSY_W 8 +#define FLASH_FBBUSY_BUSY_M 0x000000FF +#define FLASH_FBBUSY_BUSY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBAC +// +//***************************************************************************** +// Field: [16] OTPPROTDIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_OTPPROTDIS 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_BITN 16 +#define FLASH_FBAC_OTPPROTDIS_M 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_S 16 + +// Field: [15:8] BAGP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_BAGP_W 8 +#define FLASH_FBAC_BAGP_M 0x0000FF00 +#define FLASH_FBAC_BAGP_S 8 + +// Field: [7:0] VREADS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_VREADS_W 8 +#define FLASH_FBAC_VREADS_M 0x000000FF +#define FLASH_FBAC_VREADS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBFALLBACK +// +//***************************************************************************** +// Field: [27:24] FSM_PWRSAV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4 +#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000 +#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24 + +// Field: [19:16] REG_PWRSAV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_REG_PWRSAV_W 4 +#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000 +#define FLASH_FBFALLBACK_REG_PWRSAV_S 16 + +// Field: [15:14] BANKPWR7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR7_W 2 +#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000 +#define FLASH_FBFALLBACK_BANKPWR7_S 14 + +// Field: [13:12] BANKPWR6 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR6_W 2 +#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000 +#define FLASH_FBFALLBACK_BANKPWR6_S 12 + +// Field: [11:10] BANKPWR5 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR5_W 2 +#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00 +#define FLASH_FBFALLBACK_BANKPWR5_S 10 + +// Field: [9:8] BANKPWR4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR4_W 2 +#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300 +#define FLASH_FBFALLBACK_BANKPWR4_S 8 + +// Field: [7:6] BANKPWR3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR3_W 2 +#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0 +#define FLASH_FBFALLBACK_BANKPWR3_S 6 + +// Field: [5:4] BANKPWR2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR2_W 2 +#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030 +#define FLASH_FBFALLBACK_BANKPWR2_S 4 + +// Field: [3:2] BANKPWR1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR1_W 2 +#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C +#define FLASH_FBFALLBACK_BANKPWR1_S 2 + +// Field: [1:0] BANKPWR0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR0_W 2 +#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003 +#define FLASH_FBFALLBACK_BANKPWR0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBPRDY +// +//***************************************************************************** +// Field: [16] BANKBUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_BANKBUSY 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_BITN 16 +#define FLASH_FBPRDY_BANKBUSY_M 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_S 16 + +// Field: [15] PUMPRDY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_PUMPRDY 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_BITN 15 +#define FLASH_FBPRDY_PUMPRDY_M 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_S 15 + +// Field: [0] BANKRDY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_BANKRDY 0x00000001 +#define FLASH_FBPRDY_BANKRDY_BITN 0 +#define FLASH_FBPRDY_BANKRDY_M 0x00000001 +#define FLASH_FBPRDY_BANKRDY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FPAC1 +// +//***************************************************************************** +// Field: [27:16] PSLEEPTDIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PSLEEPTDIS_W 12 +#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000 +#define FLASH_FPAC1_PSLEEPTDIS_S 16 + +// Field: [15:4] PUMPRESET_PW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PUMPRESET_PW_W 12 +#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0 +#define FLASH_FPAC1_PUMPRESET_PW_S 4 + +// Field: [1:0] PUMPPWR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PUMPPWR_W 2 +#define FLASH_FPAC1_PUMPPWR_M 0x00000003 +#define FLASH_FPAC1_PUMPPWR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FPAC2 +// +//***************************************************************************** +// Field: [15:0] PAGP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC2_PAGP_W 16 +#define FLASH_FPAC2_PAGP_M 0x0000FFFF +#define FLASH_FPAC2_PAGP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMAC +// +//***************************************************************************** +// Field: [2:0] BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMAC_BANK_W 3 +#define FLASH_FMAC_BANK_M 0x00000007 +#define FLASH_FMAC_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMSTAT +// +//***************************************************************************** +// Field: [17] RVSUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RVSUSP 0x00020000 +#define FLASH_FMSTAT_RVSUSP_BITN 17 +#define FLASH_FMSTAT_RVSUSP_M 0x00020000 +#define FLASH_FMSTAT_RVSUSP_S 17 + +// Field: [16] RDVER +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RDVER 0x00010000 +#define FLASH_FMSTAT_RDVER_BITN 16 +#define FLASH_FMSTAT_RDVER_M 0x00010000 +#define FLASH_FMSTAT_RDVER_S 16 + +// Field: [15] RVF +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RVF 0x00008000 +#define FLASH_FMSTAT_RVF_BITN 15 +#define FLASH_FMSTAT_RVF_M 0x00008000 +#define FLASH_FMSTAT_RVF_S 15 + +// Field: [14] ILA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ILA 0x00004000 +#define FLASH_FMSTAT_ILA_BITN 14 +#define FLASH_FMSTAT_ILA_M 0x00004000 +#define FLASH_FMSTAT_ILA_S 14 + +// Field: [13] DBF +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_DBF 0x00002000 +#define FLASH_FMSTAT_DBF_BITN 13 +#define FLASH_FMSTAT_DBF_M 0x00002000 +#define FLASH_FMSTAT_DBF_S 13 + +// Field: [12] PGV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PGV 0x00001000 +#define FLASH_FMSTAT_PGV_BITN 12 +#define FLASH_FMSTAT_PGV_M 0x00001000 +#define FLASH_FMSTAT_PGV_S 12 + +// Field: [11] PCV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PCV 0x00000800 +#define FLASH_FMSTAT_PCV_BITN 11 +#define FLASH_FMSTAT_PCV_M 0x00000800 +#define FLASH_FMSTAT_PCV_S 11 + +// Field: [10] EV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_EV 0x00000400 +#define FLASH_FMSTAT_EV_BITN 10 +#define FLASH_FMSTAT_EV_M 0x00000400 +#define FLASH_FMSTAT_EV_S 10 + +// Field: [9] CV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_CV 0x00000200 +#define FLASH_FMSTAT_CV_BITN 9 +#define FLASH_FMSTAT_CV_M 0x00000200 +#define FLASH_FMSTAT_CV_S 9 + +// Field: [8] BUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_BUSY 0x00000100 +#define FLASH_FMSTAT_BUSY_BITN 8 +#define FLASH_FMSTAT_BUSY_M 0x00000100 +#define FLASH_FMSTAT_BUSY_S 8 + +// Field: [7] ERS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ERS 0x00000080 +#define FLASH_FMSTAT_ERS_BITN 7 +#define FLASH_FMSTAT_ERS_M 0x00000080 +#define FLASH_FMSTAT_ERS_S 7 + +// Field: [6] PGM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PGM 0x00000040 +#define FLASH_FMSTAT_PGM_BITN 6 +#define FLASH_FMSTAT_PGM_M 0x00000040 +#define FLASH_FMSTAT_PGM_S 6 + +// Field: [5] INVDAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_INVDAT 0x00000020 +#define FLASH_FMSTAT_INVDAT_BITN 5 +#define FLASH_FMSTAT_INVDAT_M 0x00000020 +#define FLASH_FMSTAT_INVDAT_S 5 + +// Field: [4] CSTAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_CSTAT 0x00000010 +#define FLASH_FMSTAT_CSTAT_BITN 4 +#define FLASH_FMSTAT_CSTAT_M 0x00000010 +#define FLASH_FMSTAT_CSTAT_S 4 + +// Field: [3] VOLSTAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_VOLSTAT 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_BITN 3 +#define FLASH_FMSTAT_VOLSTAT_M 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_S 3 + +// Field: [2] ESUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ESUSP 0x00000004 +#define FLASH_FMSTAT_ESUSP_BITN 2 +#define FLASH_FMSTAT_ESUSP_M 0x00000004 +#define FLASH_FMSTAT_ESUSP_S 2 + +// Field: [1] PSUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PSUSP 0x00000002 +#define FLASH_FMSTAT_PSUSP_BITN 1 +#define FLASH_FMSTAT_PSUSP_M 0x00000002 +#define FLASH_FMSTAT_PSUSP_S 1 + +// Field: [0] SLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_SLOCK 0x00000001 +#define FLASH_FMSTAT_SLOCK_BITN 0 +#define FLASH_FMSTAT_SLOCK_M 0x00000001 +#define FLASH_FMSTAT_SLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FLOCK +// +//***************************************************************************** +// Field: [15:0] ENCOM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FLOCK_ENCOM_W 16 +#define FLASH_FLOCK_ENCOM_M 0x0000FFFF +#define FLASH_FLOCK_ENCOM_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVREADCT +// +//***************************************************************************** +// Field: [3:0] VREADCT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVREADCT_VREADCT_W 4 +#define FLASH_FVREADCT_VREADCT_M 0x0000000F +#define FLASH_FVREADCT_VREADCT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT1 +// +//***************************************************************************** +// Field: [23:20] TRIM13_E +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_TRIM13_E_W 4 +#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 +#define FLASH_FVHVCT1_TRIM13_E_S 20 + +// Field: [19:16] VHVCT_E +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_VHVCT_E_W 4 +#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 +#define FLASH_FVHVCT1_VHVCT_E_S 16 + +// Field: [7:4] TRIM13_PV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_TRIM13_PV_W 4 +#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 +#define FLASH_FVHVCT1_TRIM13_PV_S 4 + +// Field: [3:0] VHVCT_PV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_VHVCT_PV_W 4 +#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F +#define FLASH_FVHVCT1_VHVCT_PV_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT2 +// +//***************************************************************************** +// Field: [23:20] TRIM13_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT2_TRIM13_P_W 4 +#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 +#define FLASH_FVHVCT2_TRIM13_P_S 20 + +// Field: [19:16] VHVCT_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT2_VHVCT_P_W 4 +#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 +#define FLASH_FVHVCT2_VHVCT_P_S 16 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT3 +// +//***************************************************************************** +// Field: [19:16] WCT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT3_WCT_W 4 +#define FLASH_FVHVCT3_WCT_M 0x000F0000 +#define FLASH_FVHVCT3_WCT_S 16 + +// Field: [3:0] VHVCT_READ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT3_VHVCT_READ_W 4 +#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F +#define FLASH_FVHVCT3_VHVCT_READ_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVNVCT +// +//***************************************************************************** +// Field: [12:8] VCG2P5CT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVNVCT_VCG2P5CT_W 5 +#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 +#define FLASH_FVNVCT_VCG2P5CT_S 8 + +// Field: [4:0] VIN_CT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVNVCT_VIN_CT_W 5 +#define FLASH_FVNVCT_VIN_CT_M 0x0000001F +#define FLASH_FVNVCT_VIN_CT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVSLP +// +//***************************************************************************** +// Field: [15:12] VSL_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVSLP_VSL_P_W 4 +#define FLASH_FVSLP_VSL_P_M 0x0000F000 +#define FLASH_FVSLP_VSL_P_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FVWLCT +// +//***************************************************************************** +// Field: [4:0] VWLCT_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVWLCT_VWLCT_P_W 5 +#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F +#define FLASH_FVWLCT_VWLCT_P_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSECTL +// +//***************************************************************************** +// Field: [26:24] CHAIN_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_CHAIN_SEL_W 3 +#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000 +#define FLASH_FEFUSECTL_CHAIN_SEL_S 24 + +// Field: [17] WRITE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_WRITE_EN 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_BITN 17 +#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_S 17 + +// Field: [16] BP_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_BP_SEL 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_BITN 16 +#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_S 16 + +// Field: [8] EF_CLRZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8 +#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_S 8 + +// Field: [4] EF_TEST +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EF_TEST 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_BITN 4 +#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_S 4 + +// Field: [3:0] EFUSE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EFUSE_EN_W 4 +#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F +#define FLASH_FEFUSECTL_EFUSE_EN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSESTAT +// +//***************************************************************************** +// Field: [0] SHIFT_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0 +#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSEDATA +// +//***************************************************************************** +// Field: [31:0] FEFUSEDATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32 +#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF +#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSEQPMP +// +//***************************************************************************** +// Field: [27:24] TRIM_3P4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_3P4_W 4 +#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000 +#define FLASH_FSEQPMP_TRIM_3P4_S 24 + +// Field: [21:20] TRIM_1P7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_1P7_W 2 +#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 +#define FLASH_FSEQPMP_TRIM_1P7_S 20 + +// Field: [19:16] TRIM_0P8 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_0P8_W 4 +#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000 +#define FLASH_FSEQPMP_TRIM_0P8_S 16 + +// Field: [14:12] VIN_AT_X +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_VIN_AT_X_W 3 +#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 +#define FLASH_FSEQPMP_VIN_AT_X_S 12 + +// Field: [8] VIN_BY_PASS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8 +#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FBSTROBES +// +//***************************************************************************** +// Field: [24] ECBIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_ECBIT 0x01000000 +#define FLASH_FBSTROBES_ECBIT_BITN 24 +#define FLASH_FBSTROBES_ECBIT_M 0x01000000 +#define FLASH_FBSTROBES_ECBIT_S 24 + +// Field: [18] RWAIT2_FLCLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18 + +// Field: [17] RWAIT_FLCLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17 +#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17 + +// Field: [16] FLCLKEN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_FLCLKEN 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_BITN 16 +#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_S 16 + +// Field: [8] CTRLENZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_CTRLENZ 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_BITN 8 +#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_S 8 + +// Field: [6] NOCOLRED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_NOCOLRED 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_BITN 6 +#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_S 6 + +// Field: [5] PRECOL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_PRECOL 0x00000020 +#define FLASH_FBSTROBES_PRECOL_BITN 5 +#define FLASH_FBSTROBES_PRECOL_M 0x00000020 +#define FLASH_FBSTROBES_PRECOL_S 5 + +// Field: [4] TI_OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_TI_OTP 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_BITN 4 +#define FLASH_FBSTROBES_TI_OTP_M 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_S 4 + +// Field: [3] OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_OTP 0x00000008 +#define FLASH_FBSTROBES_OTP_BITN 3 +#define FLASH_FBSTROBES_OTP_M 0x00000008 +#define FLASH_FBSTROBES_OTP_S 3 + +// Field: [2] TEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_TEZ 0x00000004 +#define FLASH_FBSTROBES_TEZ_BITN 2 +#define FLASH_FBSTROBES_TEZ_M 0x00000004 +#define FLASH_FBSTROBES_TEZ_S 2 + +//***************************************************************************** +// +// Register: FLASH_O_FPSTROBES +// +//***************************************************************************** +// Field: [8] EXECUTEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_EXECUTEZ 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_BITN 8 +#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_S 8 + +// Field: [1] V3PWRDNZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1 +#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_S 1 + +// Field: [0] V5PWRDNZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0 +#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBMODE +// +//***************************************************************************** +// Field: [2:0] MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBMODE_MODE_W 3 +#define FLASH_FBMODE_MODE_M 0x00000007 +#define FLASH_FBMODE_MODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FTCR +// +//***************************************************************************** +// Field: [6:0] TCR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCR_TCR_W 7 +#define FLASH_FTCR_TCR_M 0x0000007F +#define FLASH_FTCR_TCR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FADDR +// +//***************************************************************************** +// Field: [31:0] FADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FADDR_FADDR_W 32 +#define FLASH_FADDR_FADDR_M 0xFFFFFFFF +#define FLASH_FADDR_FADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FTCTL +// +//***************************************************************************** +// Field: [16] WDATA_BLK_CLR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16 +#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_S 16 + +// Field: [1] TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCTL_TEST_EN 0x00000002 +#define FLASH_FTCTL_TEST_EN_BITN 1 +#define FLASH_FTCTL_TEST_EN_M 0x00000002 +#define FLASH_FTCTL_TEST_EN_S 1 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE0 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE0_FWPWRITE0_W 32 +#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF +#define FLASH_FWPWRITE0_FWPWRITE0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE1 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE1_FWPWRITE1_W 32 +#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF +#define FLASH_FWPWRITE1_FWPWRITE1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE2 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE2_FWPWRITE2_W 32 +#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF +#define FLASH_FWPWRITE2_FWPWRITE2_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE3 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE3_FWPWRITE3_W 32 +#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF +#define FLASH_FWPWRITE3_FWPWRITE3_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE4 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE4_FWPWRITE4_W 32 +#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF +#define FLASH_FWPWRITE4_FWPWRITE4_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE5 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE5 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE5_FWPWRITE5_W 32 +#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF +#define FLASH_FWPWRITE5_FWPWRITE5_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE6 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE6 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE6_FWPWRITE6_W 32 +#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF +#define FLASH_FWPWRITE6_FWPWRITE6_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE7 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE7_FWPWRITE7_W 32 +#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF +#define FLASH_FWPWRITE7_FWPWRITE7_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE_ECC +// +//***************************************************************************** +// Field: [31:24] ECCBYTES07_00 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24 + +// Field: [23:16] ECCBYTES15_08 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16 + +// Field: [15:8] ECCBYTES23_16 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8 + +// Field: [7:0] ECCBYTES31_24 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSWSTAT +// +//***************************************************************************** +// Field: [0] SAFELV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSWSTAT_SAFELV 0x00000001 +#define FLASH_FSWSTAT_SAFELV_BITN 0 +#define FLASH_FSWSTAT_SAFELV_M 0x00000001 +#define FLASH_FSWSTAT_SAFELV_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_GLBCTL +// +//***************************************************************************** +// Field: [0] CLKSEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0 +#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STATE +// +//***************************************************************************** +// Field: [11] CTRLENZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_CTRLENZ 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_BITN 11 +#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_S 11 + +// Field: [10] EXECUTEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_EXECUTEZ 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_BITN 10 +#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_S 10 + +// Field: [8] FSM_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_FSM_ACT 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_BITN 8 +#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_S 8 + +// Field: [7] TIOTP_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7 +#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_S 7 + +// Field: [6] OTP_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_OTP_ACT 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_BITN 6 +#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_S 6 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STAT +// +//***************************************************************************** +// Field: [2] NON_OP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_NON_OP 0x00000004 +#define FLASH_FSM_STAT_NON_OP_BITN 2 +#define FLASH_FSM_STAT_NON_OP_M 0x00000004 +#define FLASH_FSM_STAT_NON_OP_S 2 + +// Field: [1] OVR_PUL_CNT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1 +#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1 + +// Field: [0] INV_DAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_INV_DAT 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_BITN 0 +#define FLASH_FSM_STAT_INV_DAT_M 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_CMD +// +//***************************************************************************** +// Field: [5:0] FSMCMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_CMD_FSMCMD_W 6 +#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F +#define FLASH_FSM_CMD_FSMCMD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_OSU +// +//***************************************************************************** +// Field: [15:8] PGM_OSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_OSU_PGM_OSU_W 8 +#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 +#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 + +// Field: [7:0] ERA_OSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_OSU_ERA_OSU_W 8 +#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF +#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_VSTAT +// +//***************************************************************************** +// Field: [15:12] VSTAT_CNT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4 +#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 +#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_VSU +// +//***************************************************************************** +// Field: [15:8] PGM_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VSU_PGM_VSU_W 8 +#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 +#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 + +// Field: [7:0] ERA_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VSU_ERA_VSU_W 8 +#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF +#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_CMP_VSU +// +//***************************************************************************** +// Field: [15:12] ADD_EXZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EX_VAL +// +//***************************************************************************** +// Field: [15:8] REP_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EX_VAL_REP_VSU_W 8 +#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 +#define FLASH_FSM_EX_VAL_REP_VSU_S 8 + +// Field: [7:0] EXE_VALD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EX_VAL_EXE_VALD_W 8 +#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF +#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_RD_H +// +//***************************************************************************** +// Field: [7:0] RD_H +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_RD_H_RD_H_W 8 +#define FLASH_FSM_RD_H_RD_H_M 0x000000FF +#define FLASH_FSM_RD_H_RD_H_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_P_OH +// +//***************************************************************************** +// Field: [15:8] PGM_OH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_P_OH_PGM_OH_W 8 +#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 +#define FLASH_FSM_P_OH_PGM_OH_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_OH +// +//***************************************************************************** +// Field: [15:0] ERA_OH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_OH_ERA_OH_W 16 +#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF +#define FLASH_FSM_ERA_OH_ERA_OH_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SAV_PPUL +// +//***************************************************************************** +// Field: [11:0] SAV_P_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12 +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_VH +// +//***************************************************************************** +// Field: [15:8] PGM_VH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VH_PGM_VH_W 8 +#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 +#define FLASH_FSM_PE_VH_PGM_VH_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PRG_PW +// +//***************************************************************************** +// Field: [15:0] PROG_PUL_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16 +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_PW +// +//***************************************************************************** +// Field: [31:0] FSM_ERA_PW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32 +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SAV_ERA_PUL +// +//***************************************************************************** +// Field: [11:0] SAV_ERA_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12 +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_TIMER +// +//***************************************************************************** +// Field: [31:0] FSM_TIMER +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_TIMER_FSM_TIMER_W 32 +#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF +#define FLASH_FSM_TIMER_FSM_TIMER_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_MODE +// +//***************************************************************************** +// Field: [19:18] RDV_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_RDV_SUBMODE_W 2 +#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000 +#define FLASH_FSM_MODE_RDV_SUBMODE_S 18 + +// Field: [17:16] PGM_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_PGM_SUBMODE_W 2 +#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000 +#define FLASH_FSM_MODE_PGM_SUBMODE_S 16 + +// Field: [15:14] ERA_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_ERA_SUBMODE_W 2 +#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000 +#define FLASH_FSM_MODE_ERA_SUBMODE_S 14 + +// Field: [13:12] SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SUBMODE_W 2 +#define FLASH_FSM_MODE_SUBMODE_M 0x00003000 +#define FLASH_FSM_MODE_SUBMODE_S 12 + +// Field: [11:9] SAV_PGM_CMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3 +#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00 +#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9 + +// Field: [8:6] SAV_ERA_MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3 +#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0 +#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6 + +// Field: [5:3] MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_MODE_W 3 +#define FLASH_FSM_MODE_MODE_M 0x00000038 +#define FLASH_FSM_MODE_MODE_S 3 + +// Field: [2:0] CMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_CMD_W 3 +#define FLASH_FSM_MODE_CMD_M 0x00000007 +#define FLASH_FSM_MODE_CMD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PGM +// +//***************************************************************************** +// Field: [25:23] PGM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_PGM_BANK_W 3 +#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000 +#define FLASH_FSM_PGM_PGM_BANK_S 23 + +// Field: [22:0] PGM_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_PGM_ADDR_W 23 +#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF +#define FLASH_FSM_PGM_PGM_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA +// +//***************************************************************************** +// Field: [25:23] ERA_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_ERA_BANK_W 3 +#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000 +#define FLASH_FSM_ERA_ERA_BANK_S 23 + +// Field: [22:0] ERA_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_ERA_ADDR_W 23 +#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF +#define FLASH_FSM_ERA_ERA_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PRG_PUL +// +//***************************************************************************** +// Field: [19:16] BEG_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 + +// Field: [11:0] MAX_PRG_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12 +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_PUL +// +//***************************************************************************** +// Field: [19:16] MAX_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 + +// Field: [11:0] MAX_ERA_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12 +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STEP_SIZE +// +//***************************************************************************** +// Field: [24:16] EC_STEP_SIZE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PUL_CNTR +// +//***************************************************************************** +// Field: [24:16] CUR_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16 + +// Field: [11:0] PUL_CNTR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12 +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EC_STEP_HEIGHT +// +//***************************************************************************** +// Field: [3:0] EC_STEP_HEIGHT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4 +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ST_MACHINE +// +//***************************************************************************** +// Field: [23] DO_PRECOND +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 + +// Field: [22] FSM_INT_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22 + +// Field: [21] ALL_BANKS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21 + +// Field: [20] CMPV_ALLOWED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20 + +// Field: [19] RANDOM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19 +#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_S 19 + +// Field: [18] RV_SEC_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18 + +// Field: [17] RV_RES +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17 +#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_S 17 + +// Field: [16] RV_INT_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16 + +// Field: [14] ONE_TIME_GOOD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14 + +// Field: [11] DO_REDU_COL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11 + +// Field: [10:7] DBG_SHORT_ROW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7 + +// Field: [5] PGM_SEC_COF_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5 + +// Field: [4] PREC_STOP_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4 + +// Field: [3] DIS_TST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3 + +// Field: [2] CMD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2 +#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2 + +// Field: [1] INV_DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1 +#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1 + +// Field: [0] OVERRIDE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_FLES +// +//***************************************************************************** +// Field: [11:8] BLK_TIOTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_FLES_BLK_TIOTP_W 4 +#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00 +#define FLASH_FSM_FLES_BLK_TIOTP_S 8 + +// Field: [7:0] BLK_OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_FLES_BLK_OTP_W 8 +#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF +#define FLASH_FSM_FLES_BLK_OTP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_WR_ENA +// +//***************************************************************************** +// Field: [2:0] WR_ENA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_WR_ENA_WR_ENA_W 3 +#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007 +#define FLASH_FSM_WR_ENA_WR_ENA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ACC_PP +// +//***************************************************************************** +// Field: [31:0] FSM_ACC_PP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32 +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ACC_EP +// +//***************************************************************************** +// Field: [15:0] ACC_EP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ACC_EP_ACC_EP_W 16 +#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF +#define FLASH_FSM_ACC_EP_ACC_EP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ADDR +// +//***************************************************************************** +// Field: [30:28] BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ADDR_BANK_W 3 +#define FLASH_FSM_ADDR_BANK_M 0x70000000 +#define FLASH_FSM_ADDR_BANK_S 28 + +// Field: [27:0] CUR_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ADDR_CUR_ADDR_W 28 +#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF +#define FLASH_FSM_ADDR_CUR_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR +// +//***************************************************************************** +// Field: [31:16] SECT_ERASED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SECT_ERASED_W 16 +#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000 +#define FLASH_FSM_SECTOR_SECT_ERASED_S 16 + +// Field: [15:8] FSM_SECTOR_EXTENSION +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8 + +// Field: [7:4] SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SECTOR_W 4 +#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0 +#define FLASH_FSM_SECTOR_SECTOR_S 4 + +// Field: [3:0] SEC_OUT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SEC_OUT_W 4 +#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F +#define FLASH_FSM_SECTOR_SEC_OUT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMC_REV_ID +// +//***************************************************************************** +// Field: [31:12] MOD_VERSION +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMC_REV_ID_MOD_VERSION_W 20 +#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000 +#define FLASH_FMC_REV_ID_MOD_VERSION_S 12 + +// Field: [11:0] CONFIG_CRC +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12 +#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF +#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERR_ADDR +// +//***************************************************************************** +// Field: [31:8] FSM_ERR_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0xFFFFFF00 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 8 + +// Field: [3:0] FSM_ERR_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 4 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x0000000F +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PGM_MAXPUL +// +//***************************************************************************** +// Field: [11:0] FSM_PGM_MAXPUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12 +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EXECUTE +// +//***************************************************************************** +// Field: [19:16] SUSPEND_NOW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16 + +// Field: [4:0] FSMEXECUTE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5 +#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F +#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR1 +// +//***************************************************************************** +// Field: [31:0] FSM_SECTOR1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32 +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR2 +// +//***************************************************************************** +// Field: [31:0] FSM_SECTOR2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32 +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLE0 +// +//***************************************************************************** +// Field: [31:0] FSM_BSLE0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32 +#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF +#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLE1 +// +//***************************************************************************** +// Field: [31:0] FSM_BSL1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLE1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLE1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLE1_FSM_BSL1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLP0 +// +//***************************************************************************** +// Field: [31:0] FSM_BSLP0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32 +#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF +#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLP1 +// +//***************************************************************************** +// Field: [31:0] FSM_BSL1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLP1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLP1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLP1_FSM_BSL1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_BANK +// +//***************************************************************************** +// Field: [31:20] EE_BANK_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20 + +// Field: [19:16] EE_NUM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000 +#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16 + +// Field: [15:4] MAIN_BANK_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 + +// Field: [3:0] MAIN_NUM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_WRAPPER +// +//***************************************************************************** +// Field: [31:24] FAMILY_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24 + +// Field: [20] MEM_MAP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20 +#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20 + +// Field: [19:16] CPU2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_CPU2_W 4 +#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000 +#define FLASH_FCFG_WRAPPER_CPU2_S 16 + +// Field: [15:12] EE_IN_MAIN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12 + +// Field: [11] ROM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_ROM 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_BITN 11 +#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_S 11 + +// Field: [10] IFLUSH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10 +#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_S 10 + +// Field: [9] SIL3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_SIL3 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_BITN 9 +#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_S 9 + +// Field: [8] ECCA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_ECCA 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_BITN 8 +#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_S 8 + +// Field: [7:6] AUTO_SUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6 + +// Field: [5:4] UERR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_UERR_W 2 +#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030 +#define FLASH_FCFG_WRAPPER_UERR_S 4 + +// Field: [3:0] CPU_TYPE1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4 +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_BNK_TYPE +// +//***************************************************************************** +// Field: [31:28] B7_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28 + +// Field: [27:24] B6_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24 + +// Field: [23:20] B5_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20 + +// Field: [19:16] B4_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16 + +// Field: [15:12] B3_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12 + +// Field: [11:8] B2_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8 + +// Field: [7:4] B1_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4 + +// Field: [3:0] B0_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B0_START +// +//***************************************************************************** +// Field: [31:28] B0_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28 + +// Field: [27:24] B0_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24 + +// Field: [23:0] B0_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24 +#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B1_START +// +//***************************************************************************** +// Field: [31:28] B1_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28 + +// Field: [27:24] B1_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24 + +// Field: [23:0] B1_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24 +#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B2_START +// +//***************************************************************************** +// Field: [31:28] B2_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28 + +// Field: [27:24] B2_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24 + +// Field: [23:0] B2_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24 +#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B3_START +// +//***************************************************************************** +// Field: [31:28] B3_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28 + +// Field: [27:24] B3_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24 + +// Field: [23:0] B3_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24 +#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B4_START +// +//***************************************************************************** +// Field: [31:28] B4_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28 + +// Field: [27:24] B4_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24 + +// Field: [23:0] B4_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24 +#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B5_START +// +//***************************************************************************** +// Field: [31:28] B5_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28 + +// Field: [27:24] B5_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24 + +// Field: [23:0] B5_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24 +#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B6_START +// +//***************************************************************************** +// Field: [31:28] B6_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28 + +// Field: [27:24] B6_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24 + +// Field: [23:0] B6_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24 +#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B7_START +// +//***************************************************************************** +// Field: [31:28] B7_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28 + +// Field: [27:24] B7_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24 + +// Field: [23:0] B7_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24 +#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B0_SSIZE0 +// +//***************************************************************************** +// Field: [27:16] B0_NUM_SECTORS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16 + +// Field: [3:0] B0_SECT_SIZE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4 +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 + + +#endif // __FLASH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpio.h new file mode 100644 index 0000000..98f51c9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpio.h @@ -0,0 +1,2247 @@ +/****************************************************************************** +* Filename: hw_gpio_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// GPIO component +// +//***************************************************************************** +// Data Out 0 to 3 +#define GPIO_O_DOUT3_0 0x00000000 + +// Data Out 4 to 7 +#define GPIO_O_DOUT7_4 0x00000004 + +// Data Out 8 to 11 +#define GPIO_O_DOUT11_8 0x00000008 + +// Data Out 12 to 15 +#define GPIO_O_DOUT15_12 0x0000000C + +// Data Out 16 to 19 +#define GPIO_O_DOUT19_16 0x00000010 + +// Data Out 20 to 23 +#define GPIO_O_DOUT23_20 0x00000014 + +// Data Out 24 to 27 +#define GPIO_O_DOUT27_24 0x00000018 + +// Data Out 28 to 31 +#define GPIO_O_DOUT31_28 0x0000001C + +// Data Output for DIO 0 to 31 +#define GPIO_O_DOUT31_0 0x00000080 + +// Data Out Set +#define GPIO_O_DOUTSET31_0 0x00000090 + +// Data Out Clear +#define GPIO_O_DOUTCLR31_0 0x000000A0 + +// Data Out Toggle +#define GPIO_O_DOUTTGL31_0 0x000000B0 + +// Data Input from DIO 0 to 31 +#define GPIO_O_DIN31_0 0x000000C0 + +// Data Output Enable for DIO 0 to 31 +#define GPIO_O_DOE31_0 0x000000D0 + +// Event Register for DIO 0 to 31 +#define GPIO_O_EVFLAGS31_0 0x000000E0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT3_0 +// +//***************************************************************************** +// Field: [24] DIO3 +// +// Sets the state of the pin that is configured as DIO#3, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO3 0x01000000 +#define GPIO_DOUT3_0_DIO3_BITN 24 +#define GPIO_DOUT3_0_DIO3_M 0x01000000 +#define GPIO_DOUT3_0_DIO3_S 24 + +// Field: [16] DIO2 +// +// Sets the state of the pin that is configured as DIO#2, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO2 0x00010000 +#define GPIO_DOUT3_0_DIO2_BITN 16 +#define GPIO_DOUT3_0_DIO2_M 0x00010000 +#define GPIO_DOUT3_0_DIO2_S 16 + +// Field: [8] DIO1 +// +// Sets the state of the pin that is configured as DIO#1, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO1 0x00000100 +#define GPIO_DOUT3_0_DIO1_BITN 8 +#define GPIO_DOUT3_0_DIO1_M 0x00000100 +#define GPIO_DOUT3_0_DIO1_S 8 + +// Field: [0] DIO0 +// +// Sets the state of the pin that is configured as DIO#0, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO0 0x00000001 +#define GPIO_DOUT3_0_DIO0_BITN 0 +#define GPIO_DOUT3_0_DIO0_M 0x00000001 +#define GPIO_DOUT3_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT7_4 +// +//***************************************************************************** +// Field: [24] DIO7 +// +// Sets the state of the pin that is configured as DIO#7, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO7 0x01000000 +#define GPIO_DOUT7_4_DIO7_BITN 24 +#define GPIO_DOUT7_4_DIO7_M 0x01000000 +#define GPIO_DOUT7_4_DIO7_S 24 + +// Field: [16] DIO6 +// +// Sets the state of the pin that is configured as DIO#6, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO6 0x00010000 +#define GPIO_DOUT7_4_DIO6_BITN 16 +#define GPIO_DOUT7_4_DIO6_M 0x00010000 +#define GPIO_DOUT7_4_DIO6_S 16 + +// Field: [8] DIO5 +// +// Sets the state of the pin that is configured as DIO#5, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO5 0x00000100 +#define GPIO_DOUT7_4_DIO5_BITN 8 +#define GPIO_DOUT7_4_DIO5_M 0x00000100 +#define GPIO_DOUT7_4_DIO5_S 8 + +// Field: [0] DIO4 +// +// Sets the state of the pin that is configured as DIO#4, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO4 0x00000001 +#define GPIO_DOUT7_4_DIO4_BITN 0 +#define GPIO_DOUT7_4_DIO4_M 0x00000001 +#define GPIO_DOUT7_4_DIO4_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT11_8 +// +//***************************************************************************** +// Field: [24] DIO11 +// +// Sets the state of the pin that is configured as DIO#11, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO11 0x01000000 +#define GPIO_DOUT11_8_DIO11_BITN 24 +#define GPIO_DOUT11_8_DIO11_M 0x01000000 +#define GPIO_DOUT11_8_DIO11_S 24 + +// Field: [16] DIO10 +// +// Sets the state of the pin that is configured as DIO#10, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO10 0x00010000 +#define GPIO_DOUT11_8_DIO10_BITN 16 +#define GPIO_DOUT11_8_DIO10_M 0x00010000 +#define GPIO_DOUT11_8_DIO10_S 16 + +// Field: [8] DIO9 +// +// Sets the state of the pin that is configured as DIO#9, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO9 0x00000100 +#define GPIO_DOUT11_8_DIO9_BITN 8 +#define GPIO_DOUT11_8_DIO9_M 0x00000100 +#define GPIO_DOUT11_8_DIO9_S 8 + +// Field: [0] DIO8 +// +// Sets the state of the pin that is configured as DIO#8, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO8 0x00000001 +#define GPIO_DOUT11_8_DIO8_BITN 0 +#define GPIO_DOUT11_8_DIO8_M 0x00000001 +#define GPIO_DOUT11_8_DIO8_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT15_12 +// +//***************************************************************************** +// Field: [24] DIO15 +// +// Sets the state of the pin that is configured as DIO#15, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO15 0x01000000 +#define GPIO_DOUT15_12_DIO15_BITN 24 +#define GPIO_DOUT15_12_DIO15_M 0x01000000 +#define GPIO_DOUT15_12_DIO15_S 24 + +// Field: [16] DIO14 +// +// Sets the state of the pin that is configured as DIO#14, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO14 0x00010000 +#define GPIO_DOUT15_12_DIO14_BITN 16 +#define GPIO_DOUT15_12_DIO14_M 0x00010000 +#define GPIO_DOUT15_12_DIO14_S 16 + +// Field: [8] DIO13 +// +// Sets the state of the pin that is configured as DIO#13, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO13 0x00000100 +#define GPIO_DOUT15_12_DIO13_BITN 8 +#define GPIO_DOUT15_12_DIO13_M 0x00000100 +#define GPIO_DOUT15_12_DIO13_S 8 + +// Field: [0] DIO12 +// +// Sets the state of the pin that is configured as DIO#12, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO12 0x00000001 +#define GPIO_DOUT15_12_DIO12_BITN 0 +#define GPIO_DOUT15_12_DIO12_M 0x00000001 +#define GPIO_DOUT15_12_DIO12_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT19_16 +// +//***************************************************************************** +// Field: [24] DIO19 +// +// Sets the state of the pin that is configured as DIO#19, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO19 0x01000000 +#define GPIO_DOUT19_16_DIO19_BITN 24 +#define GPIO_DOUT19_16_DIO19_M 0x01000000 +#define GPIO_DOUT19_16_DIO19_S 24 + +// Field: [16] DIO18 +// +// Sets the state of the pin that is configured as DIO#18, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO18 0x00010000 +#define GPIO_DOUT19_16_DIO18_BITN 16 +#define GPIO_DOUT19_16_DIO18_M 0x00010000 +#define GPIO_DOUT19_16_DIO18_S 16 + +// Field: [8] DIO17 +// +// Sets the state of the pin that is configured as DIO#17, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO17 0x00000100 +#define GPIO_DOUT19_16_DIO17_BITN 8 +#define GPIO_DOUT19_16_DIO17_M 0x00000100 +#define GPIO_DOUT19_16_DIO17_S 8 + +// Field: [0] DIO16 +// +// Sets the state of the pin that is configured as DIO#16, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO16 0x00000001 +#define GPIO_DOUT19_16_DIO16_BITN 0 +#define GPIO_DOUT19_16_DIO16_M 0x00000001 +#define GPIO_DOUT19_16_DIO16_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT23_20 +// +//***************************************************************************** +// Field: [24] DIO23 +// +// Sets the state of the pin that is configured as DIO#23, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO23 0x01000000 +#define GPIO_DOUT23_20_DIO23_BITN 24 +#define GPIO_DOUT23_20_DIO23_M 0x01000000 +#define GPIO_DOUT23_20_DIO23_S 24 + +// Field: [16] DIO22 +// +// Sets the state of the pin that is configured as DIO#22, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO22 0x00010000 +#define GPIO_DOUT23_20_DIO22_BITN 16 +#define GPIO_DOUT23_20_DIO22_M 0x00010000 +#define GPIO_DOUT23_20_DIO22_S 16 + +// Field: [8] DIO21 +// +// Sets the state of the pin that is configured as DIO#21, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO21 0x00000100 +#define GPIO_DOUT23_20_DIO21_BITN 8 +#define GPIO_DOUT23_20_DIO21_M 0x00000100 +#define GPIO_DOUT23_20_DIO21_S 8 + +// Field: [0] DIO20 +// +// Sets the state of the pin that is configured as DIO#20, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO20 0x00000001 +#define GPIO_DOUT23_20_DIO20_BITN 0 +#define GPIO_DOUT23_20_DIO20_M 0x00000001 +#define GPIO_DOUT23_20_DIO20_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT27_24 +// +//***************************************************************************** +// Field: [24] DIO27 +// +// Sets the state of the pin that is configured as DIO#27, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO27 0x01000000 +#define GPIO_DOUT27_24_DIO27_BITN 24 +#define GPIO_DOUT27_24_DIO27_M 0x01000000 +#define GPIO_DOUT27_24_DIO27_S 24 + +// Field: [16] DIO26 +// +// Sets the state of the pin that is configured as DIO#26, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO26 0x00010000 +#define GPIO_DOUT27_24_DIO26_BITN 16 +#define GPIO_DOUT27_24_DIO26_M 0x00010000 +#define GPIO_DOUT27_24_DIO26_S 16 + +// Field: [8] DIO25 +// +// Sets the state of the pin that is configured as DIO#25, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO25 0x00000100 +#define GPIO_DOUT27_24_DIO25_BITN 8 +#define GPIO_DOUT27_24_DIO25_M 0x00000100 +#define GPIO_DOUT27_24_DIO25_S 8 + +// Field: [0] DIO24 +// +// Sets the state of the pin that is configured as DIO#24, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO24 0x00000001 +#define GPIO_DOUT27_24_DIO24_BITN 0 +#define GPIO_DOUT27_24_DIO24_M 0x00000001 +#define GPIO_DOUT27_24_DIO24_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT31_28 +// +//***************************************************************************** +// Field: [24] DIO31 +// +// Sets the state of the pin that is configured as DIO#31, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO31 0x01000000 +#define GPIO_DOUT31_28_DIO31_BITN 24 +#define GPIO_DOUT31_28_DIO31_M 0x01000000 +#define GPIO_DOUT31_28_DIO31_S 24 + +// Field: [16] DIO30 +// +// Sets the state of the pin that is configured as DIO#30, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO30 0x00010000 +#define GPIO_DOUT31_28_DIO30_BITN 16 +#define GPIO_DOUT31_28_DIO30_M 0x00010000 +#define GPIO_DOUT31_28_DIO30_S 16 + +// Field: [8] DIO29 +// +// Sets the state of the pin that is configured as DIO#29, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO29 0x00000100 +#define GPIO_DOUT31_28_DIO29_BITN 8 +#define GPIO_DOUT31_28_DIO29_M 0x00000100 +#define GPIO_DOUT31_28_DIO29_S 8 + +// Field: [0] DIO28 +// +// Sets the state of the pin that is configured as DIO#28, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO28 0x00000001 +#define GPIO_DOUT31_28_DIO28_BITN 0 +#define GPIO_DOUT31_28_DIO28_M 0x00000001 +#define GPIO_DOUT31_28_DIO28_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data output for DIO 31 +#define GPIO_DOUT31_0_DIO31 0x80000000 +#define GPIO_DOUT31_0_DIO31_BITN 31 +#define GPIO_DOUT31_0_DIO31_M 0x80000000 +#define GPIO_DOUT31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data output for DIO 30 +#define GPIO_DOUT31_0_DIO30 0x40000000 +#define GPIO_DOUT31_0_DIO30_BITN 30 +#define GPIO_DOUT31_0_DIO30_M 0x40000000 +#define GPIO_DOUT31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data output for DIO 29 +#define GPIO_DOUT31_0_DIO29 0x20000000 +#define GPIO_DOUT31_0_DIO29_BITN 29 +#define GPIO_DOUT31_0_DIO29_M 0x20000000 +#define GPIO_DOUT31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data output for DIO 28 +#define GPIO_DOUT31_0_DIO28 0x10000000 +#define GPIO_DOUT31_0_DIO28_BITN 28 +#define GPIO_DOUT31_0_DIO28_M 0x10000000 +#define GPIO_DOUT31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data output for DIO 27 +#define GPIO_DOUT31_0_DIO27 0x08000000 +#define GPIO_DOUT31_0_DIO27_BITN 27 +#define GPIO_DOUT31_0_DIO27_M 0x08000000 +#define GPIO_DOUT31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data output for DIO 26 +#define GPIO_DOUT31_0_DIO26 0x04000000 +#define GPIO_DOUT31_0_DIO26_BITN 26 +#define GPIO_DOUT31_0_DIO26_M 0x04000000 +#define GPIO_DOUT31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data output for DIO 25 +#define GPIO_DOUT31_0_DIO25 0x02000000 +#define GPIO_DOUT31_0_DIO25_BITN 25 +#define GPIO_DOUT31_0_DIO25_M 0x02000000 +#define GPIO_DOUT31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data output for DIO 24 +#define GPIO_DOUT31_0_DIO24 0x01000000 +#define GPIO_DOUT31_0_DIO24_BITN 24 +#define GPIO_DOUT31_0_DIO24_M 0x01000000 +#define GPIO_DOUT31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data output for DIO 23 +#define GPIO_DOUT31_0_DIO23 0x00800000 +#define GPIO_DOUT31_0_DIO23_BITN 23 +#define GPIO_DOUT31_0_DIO23_M 0x00800000 +#define GPIO_DOUT31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data output for DIO 22 +#define GPIO_DOUT31_0_DIO22 0x00400000 +#define GPIO_DOUT31_0_DIO22_BITN 22 +#define GPIO_DOUT31_0_DIO22_M 0x00400000 +#define GPIO_DOUT31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data output for DIO 21 +#define GPIO_DOUT31_0_DIO21 0x00200000 +#define GPIO_DOUT31_0_DIO21_BITN 21 +#define GPIO_DOUT31_0_DIO21_M 0x00200000 +#define GPIO_DOUT31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data output for DIO 20 +#define GPIO_DOUT31_0_DIO20 0x00100000 +#define GPIO_DOUT31_0_DIO20_BITN 20 +#define GPIO_DOUT31_0_DIO20_M 0x00100000 +#define GPIO_DOUT31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data output for DIO 19 +#define GPIO_DOUT31_0_DIO19 0x00080000 +#define GPIO_DOUT31_0_DIO19_BITN 19 +#define GPIO_DOUT31_0_DIO19_M 0x00080000 +#define GPIO_DOUT31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data output for DIO 18 +#define GPIO_DOUT31_0_DIO18 0x00040000 +#define GPIO_DOUT31_0_DIO18_BITN 18 +#define GPIO_DOUT31_0_DIO18_M 0x00040000 +#define GPIO_DOUT31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data output for DIO 17 +#define GPIO_DOUT31_0_DIO17 0x00020000 +#define GPIO_DOUT31_0_DIO17_BITN 17 +#define GPIO_DOUT31_0_DIO17_M 0x00020000 +#define GPIO_DOUT31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data output for DIO 16 +#define GPIO_DOUT31_0_DIO16 0x00010000 +#define GPIO_DOUT31_0_DIO16_BITN 16 +#define GPIO_DOUT31_0_DIO16_M 0x00010000 +#define GPIO_DOUT31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data output for DIO 15 +#define GPIO_DOUT31_0_DIO15 0x00008000 +#define GPIO_DOUT31_0_DIO15_BITN 15 +#define GPIO_DOUT31_0_DIO15_M 0x00008000 +#define GPIO_DOUT31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data output for DIO 14 +#define GPIO_DOUT31_0_DIO14 0x00004000 +#define GPIO_DOUT31_0_DIO14_BITN 14 +#define GPIO_DOUT31_0_DIO14_M 0x00004000 +#define GPIO_DOUT31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data output for DIO 13 +#define GPIO_DOUT31_0_DIO13 0x00002000 +#define GPIO_DOUT31_0_DIO13_BITN 13 +#define GPIO_DOUT31_0_DIO13_M 0x00002000 +#define GPIO_DOUT31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data output for DIO 12 +#define GPIO_DOUT31_0_DIO12 0x00001000 +#define GPIO_DOUT31_0_DIO12_BITN 12 +#define GPIO_DOUT31_0_DIO12_M 0x00001000 +#define GPIO_DOUT31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data output for DIO 11 +#define GPIO_DOUT31_0_DIO11 0x00000800 +#define GPIO_DOUT31_0_DIO11_BITN 11 +#define GPIO_DOUT31_0_DIO11_M 0x00000800 +#define GPIO_DOUT31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data output for DIO 10 +#define GPIO_DOUT31_0_DIO10 0x00000400 +#define GPIO_DOUT31_0_DIO10_BITN 10 +#define GPIO_DOUT31_0_DIO10_M 0x00000400 +#define GPIO_DOUT31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data output for DIO 9 +#define GPIO_DOUT31_0_DIO9 0x00000200 +#define GPIO_DOUT31_0_DIO9_BITN 9 +#define GPIO_DOUT31_0_DIO9_M 0x00000200 +#define GPIO_DOUT31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data output for DIO 8 +#define GPIO_DOUT31_0_DIO8 0x00000100 +#define GPIO_DOUT31_0_DIO8_BITN 8 +#define GPIO_DOUT31_0_DIO8_M 0x00000100 +#define GPIO_DOUT31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data output for DIO 7 +#define GPIO_DOUT31_0_DIO7 0x00000080 +#define GPIO_DOUT31_0_DIO7_BITN 7 +#define GPIO_DOUT31_0_DIO7_M 0x00000080 +#define GPIO_DOUT31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data output for DIO 6 +#define GPIO_DOUT31_0_DIO6 0x00000040 +#define GPIO_DOUT31_0_DIO6_BITN 6 +#define GPIO_DOUT31_0_DIO6_M 0x00000040 +#define GPIO_DOUT31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data output for DIO 5 +#define GPIO_DOUT31_0_DIO5 0x00000020 +#define GPIO_DOUT31_0_DIO5_BITN 5 +#define GPIO_DOUT31_0_DIO5_M 0x00000020 +#define GPIO_DOUT31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data output for DIO 4 +#define GPIO_DOUT31_0_DIO4 0x00000010 +#define GPIO_DOUT31_0_DIO4_BITN 4 +#define GPIO_DOUT31_0_DIO4_M 0x00000010 +#define GPIO_DOUT31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data output for DIO 3 +#define GPIO_DOUT31_0_DIO3 0x00000008 +#define GPIO_DOUT31_0_DIO3_BITN 3 +#define GPIO_DOUT31_0_DIO3_M 0x00000008 +#define GPIO_DOUT31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data output for DIO 2 +#define GPIO_DOUT31_0_DIO2 0x00000004 +#define GPIO_DOUT31_0_DIO2_BITN 2 +#define GPIO_DOUT31_0_DIO2_M 0x00000004 +#define GPIO_DOUT31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data output for DIO 1 +#define GPIO_DOUT31_0_DIO1 0x00000002 +#define GPIO_DOUT31_0_DIO1_BITN 1 +#define GPIO_DOUT31_0_DIO1_M 0x00000002 +#define GPIO_DOUT31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data output for DIO 0 +#define GPIO_DOUT31_0_DIO0 0x00000001 +#define GPIO_DOUT31_0_DIO0_BITN 0 +#define GPIO_DOUT31_0_DIO0_M 0x00000001 +#define GPIO_DOUT31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTSET31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Set bit 31 +#define GPIO_DOUTSET31_0_DIO31 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_BITN 31 +#define GPIO_DOUTSET31_0_DIO31_M 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Set bit 30 +#define GPIO_DOUTSET31_0_DIO30 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_BITN 30 +#define GPIO_DOUTSET31_0_DIO30_M 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Set bit 29 +#define GPIO_DOUTSET31_0_DIO29 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_BITN 29 +#define GPIO_DOUTSET31_0_DIO29_M 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Set bit 28 +#define GPIO_DOUTSET31_0_DIO28 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_BITN 28 +#define GPIO_DOUTSET31_0_DIO28_M 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Set bit 27 +#define GPIO_DOUTSET31_0_DIO27 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_BITN 27 +#define GPIO_DOUTSET31_0_DIO27_M 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Set bit 26 +#define GPIO_DOUTSET31_0_DIO26 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_BITN 26 +#define GPIO_DOUTSET31_0_DIO26_M 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Set bit 25 +#define GPIO_DOUTSET31_0_DIO25 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_BITN 25 +#define GPIO_DOUTSET31_0_DIO25_M 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Set bit 24 +#define GPIO_DOUTSET31_0_DIO24 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_BITN 24 +#define GPIO_DOUTSET31_0_DIO24_M 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Set bit 23 +#define GPIO_DOUTSET31_0_DIO23 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_BITN 23 +#define GPIO_DOUTSET31_0_DIO23_M 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Set bit 22 +#define GPIO_DOUTSET31_0_DIO22 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_BITN 22 +#define GPIO_DOUTSET31_0_DIO22_M 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Set bit 21 +#define GPIO_DOUTSET31_0_DIO21 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_BITN 21 +#define GPIO_DOUTSET31_0_DIO21_M 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Set bit 20 +#define GPIO_DOUTSET31_0_DIO20 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_BITN 20 +#define GPIO_DOUTSET31_0_DIO20_M 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Set bit 19 +#define GPIO_DOUTSET31_0_DIO19 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_BITN 19 +#define GPIO_DOUTSET31_0_DIO19_M 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Set bit 18 +#define GPIO_DOUTSET31_0_DIO18 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_BITN 18 +#define GPIO_DOUTSET31_0_DIO18_M 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Set bit 17 +#define GPIO_DOUTSET31_0_DIO17 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_BITN 17 +#define GPIO_DOUTSET31_0_DIO17_M 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Set bit 16 +#define GPIO_DOUTSET31_0_DIO16 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_BITN 16 +#define GPIO_DOUTSET31_0_DIO16_M 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Set bit 15 +#define GPIO_DOUTSET31_0_DIO15 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_BITN 15 +#define GPIO_DOUTSET31_0_DIO15_M 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Set bit 14 +#define GPIO_DOUTSET31_0_DIO14 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_BITN 14 +#define GPIO_DOUTSET31_0_DIO14_M 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Set bit 13 +#define GPIO_DOUTSET31_0_DIO13 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_BITN 13 +#define GPIO_DOUTSET31_0_DIO13_M 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Set bit 12 +#define GPIO_DOUTSET31_0_DIO12 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_BITN 12 +#define GPIO_DOUTSET31_0_DIO12_M 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Set bit 11 +#define GPIO_DOUTSET31_0_DIO11 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_BITN 11 +#define GPIO_DOUTSET31_0_DIO11_M 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Set bit 10 +#define GPIO_DOUTSET31_0_DIO10 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_BITN 10 +#define GPIO_DOUTSET31_0_DIO10_M 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Set bit 9 +#define GPIO_DOUTSET31_0_DIO9 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_BITN 9 +#define GPIO_DOUTSET31_0_DIO9_M 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Set bit 8 +#define GPIO_DOUTSET31_0_DIO8 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_BITN 8 +#define GPIO_DOUTSET31_0_DIO8_M 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Set bit 7 +#define GPIO_DOUTSET31_0_DIO7 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_BITN 7 +#define GPIO_DOUTSET31_0_DIO7_M 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Set bit 6 +#define GPIO_DOUTSET31_0_DIO6 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_BITN 6 +#define GPIO_DOUTSET31_0_DIO6_M 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Set bit 5 +#define GPIO_DOUTSET31_0_DIO5 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_BITN 5 +#define GPIO_DOUTSET31_0_DIO5_M 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Set bit 4 +#define GPIO_DOUTSET31_0_DIO4 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_BITN 4 +#define GPIO_DOUTSET31_0_DIO4_M 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Set bit 3 +#define GPIO_DOUTSET31_0_DIO3 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_BITN 3 +#define GPIO_DOUTSET31_0_DIO3_M 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Set bit 2 +#define GPIO_DOUTSET31_0_DIO2 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_BITN 2 +#define GPIO_DOUTSET31_0_DIO2_M 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Set bit 1 +#define GPIO_DOUTSET31_0_DIO1 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_BITN 1 +#define GPIO_DOUTSET31_0_DIO1_M 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Set bit 0 +#define GPIO_DOUTSET31_0_DIO0 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_BITN 0 +#define GPIO_DOUTSET31_0_DIO0_M 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTCLR31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Clears bit 31 +#define GPIO_DOUTCLR31_0_DIO31 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_BITN 31 +#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Clears bit 30 +#define GPIO_DOUTCLR31_0_DIO30 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_BITN 30 +#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Clears bit 29 +#define GPIO_DOUTCLR31_0_DIO29 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_BITN 29 +#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Clears bit 28 +#define GPIO_DOUTCLR31_0_DIO28 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_BITN 28 +#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Clears bit 27 +#define GPIO_DOUTCLR31_0_DIO27 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_BITN 27 +#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Clears bit 26 +#define GPIO_DOUTCLR31_0_DIO26 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_BITN 26 +#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Clears bit 25 +#define GPIO_DOUTCLR31_0_DIO25 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_BITN 25 +#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Clears bit 24 +#define GPIO_DOUTCLR31_0_DIO24 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_BITN 24 +#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Clears bit 23 +#define GPIO_DOUTCLR31_0_DIO23 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_BITN 23 +#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Clears bit 22 +#define GPIO_DOUTCLR31_0_DIO22 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_BITN 22 +#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Clears bit 21 +#define GPIO_DOUTCLR31_0_DIO21 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_BITN 21 +#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Clears bit 20 +#define GPIO_DOUTCLR31_0_DIO20 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_BITN 20 +#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Clears bit 19 +#define GPIO_DOUTCLR31_0_DIO19 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_BITN 19 +#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Clears bit 18 +#define GPIO_DOUTCLR31_0_DIO18 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_BITN 18 +#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Clears bit 17 +#define GPIO_DOUTCLR31_0_DIO17 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_BITN 17 +#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Clears bit 16 +#define GPIO_DOUTCLR31_0_DIO16 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_BITN 16 +#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Clears bit 15 +#define GPIO_DOUTCLR31_0_DIO15 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_BITN 15 +#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Clears bit 14 +#define GPIO_DOUTCLR31_0_DIO14 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_BITN 14 +#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Clears bit 13 +#define GPIO_DOUTCLR31_0_DIO13 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_BITN 13 +#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Clears bit 12 +#define GPIO_DOUTCLR31_0_DIO12 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_BITN 12 +#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Clears bit 11 +#define GPIO_DOUTCLR31_0_DIO11 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_BITN 11 +#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Clears bit 10 +#define GPIO_DOUTCLR31_0_DIO10 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_BITN 10 +#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Clears bit 9 +#define GPIO_DOUTCLR31_0_DIO9 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_BITN 9 +#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Clears bit 8 +#define GPIO_DOUTCLR31_0_DIO8 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_BITN 8 +#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Clears bit 7 +#define GPIO_DOUTCLR31_0_DIO7 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_BITN 7 +#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Clears bit 6 +#define GPIO_DOUTCLR31_0_DIO6 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_BITN 6 +#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Clears bit 5 +#define GPIO_DOUTCLR31_0_DIO5 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_BITN 5 +#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Clears bit 4 +#define GPIO_DOUTCLR31_0_DIO4 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_BITN 4 +#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Clears bit 3 +#define GPIO_DOUTCLR31_0_DIO3 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_BITN 3 +#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Clears bit 2 +#define GPIO_DOUTCLR31_0_DIO2 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_BITN 2 +#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Clears bit 1 +#define GPIO_DOUTCLR31_0_DIO1 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_BITN 1 +#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Clears bit 0 +#define GPIO_DOUTCLR31_0_DIO0 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_BITN 0 +#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTTGL31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Toggles bit 31 +#define GPIO_DOUTTGL31_0_DIO31 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_BITN 31 +#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Toggles bit 30 +#define GPIO_DOUTTGL31_0_DIO30 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_BITN 30 +#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Toggles bit 29 +#define GPIO_DOUTTGL31_0_DIO29 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_BITN 29 +#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Toggles bit 28 +#define GPIO_DOUTTGL31_0_DIO28 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_BITN 28 +#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Toggles bit 27 +#define GPIO_DOUTTGL31_0_DIO27 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_BITN 27 +#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Toggles bit 26 +#define GPIO_DOUTTGL31_0_DIO26 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_BITN 26 +#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Toggles bit 25 +#define GPIO_DOUTTGL31_0_DIO25 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_BITN 25 +#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Toggles bit 24 +#define GPIO_DOUTTGL31_0_DIO24 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_BITN 24 +#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Toggles bit 23 +#define GPIO_DOUTTGL31_0_DIO23 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_BITN 23 +#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Toggles bit 22 +#define GPIO_DOUTTGL31_0_DIO22 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_BITN 22 +#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Toggles bit 21 +#define GPIO_DOUTTGL31_0_DIO21 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_BITN 21 +#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Toggles bit 20 +#define GPIO_DOUTTGL31_0_DIO20 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_BITN 20 +#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Toggles bit 19 +#define GPIO_DOUTTGL31_0_DIO19 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_BITN 19 +#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Toggles bit 18 +#define GPIO_DOUTTGL31_0_DIO18 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_BITN 18 +#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Toggles bit 17 +#define GPIO_DOUTTGL31_0_DIO17 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_BITN 17 +#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Toggles bit 16 +#define GPIO_DOUTTGL31_0_DIO16 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_BITN 16 +#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Toggles bit 15 +#define GPIO_DOUTTGL31_0_DIO15 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_BITN 15 +#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Toggles bit 14 +#define GPIO_DOUTTGL31_0_DIO14 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_BITN 14 +#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Toggles bit 13 +#define GPIO_DOUTTGL31_0_DIO13 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_BITN 13 +#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Toggles bit 12 +#define GPIO_DOUTTGL31_0_DIO12 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_BITN 12 +#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Toggles bit 11 +#define GPIO_DOUTTGL31_0_DIO11 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_BITN 11 +#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Toggles bit 10 +#define GPIO_DOUTTGL31_0_DIO10 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_BITN 10 +#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Toggles bit 9 +#define GPIO_DOUTTGL31_0_DIO9 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_BITN 9 +#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Toggles bit 8 +#define GPIO_DOUTTGL31_0_DIO8 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_BITN 8 +#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Toggles bit 7 +#define GPIO_DOUTTGL31_0_DIO7 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_BITN 7 +#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Toggles bit 6 +#define GPIO_DOUTTGL31_0_DIO6 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_BITN 6 +#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Toggles bit 5 +#define GPIO_DOUTTGL31_0_DIO5 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_BITN 5 +#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Toggles bit 4 +#define GPIO_DOUTTGL31_0_DIO4 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_BITN 4 +#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Toggles bit 3 +#define GPIO_DOUTTGL31_0_DIO3 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_BITN 3 +#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Toggles bit 2 +#define GPIO_DOUTTGL31_0_DIO2 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_BITN 2 +#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Toggles bit 1 +#define GPIO_DOUTTGL31_0_DIO1 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_BITN 1 +#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Toggles bit 0 +#define GPIO_DOUTTGL31_0_DIO0 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_BITN 0 +#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DIN31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data input from DIO 31 +#define GPIO_DIN31_0_DIO31 0x80000000 +#define GPIO_DIN31_0_DIO31_BITN 31 +#define GPIO_DIN31_0_DIO31_M 0x80000000 +#define GPIO_DIN31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data input from DIO 30 +#define GPIO_DIN31_0_DIO30 0x40000000 +#define GPIO_DIN31_0_DIO30_BITN 30 +#define GPIO_DIN31_0_DIO30_M 0x40000000 +#define GPIO_DIN31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data input from DIO 29 +#define GPIO_DIN31_0_DIO29 0x20000000 +#define GPIO_DIN31_0_DIO29_BITN 29 +#define GPIO_DIN31_0_DIO29_M 0x20000000 +#define GPIO_DIN31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data input from DIO 28 +#define GPIO_DIN31_0_DIO28 0x10000000 +#define GPIO_DIN31_0_DIO28_BITN 28 +#define GPIO_DIN31_0_DIO28_M 0x10000000 +#define GPIO_DIN31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data input from DIO 27 +#define GPIO_DIN31_0_DIO27 0x08000000 +#define GPIO_DIN31_0_DIO27_BITN 27 +#define GPIO_DIN31_0_DIO27_M 0x08000000 +#define GPIO_DIN31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data input from DIO 26 +#define GPIO_DIN31_0_DIO26 0x04000000 +#define GPIO_DIN31_0_DIO26_BITN 26 +#define GPIO_DIN31_0_DIO26_M 0x04000000 +#define GPIO_DIN31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data input from DIO 25 +#define GPIO_DIN31_0_DIO25 0x02000000 +#define GPIO_DIN31_0_DIO25_BITN 25 +#define GPIO_DIN31_0_DIO25_M 0x02000000 +#define GPIO_DIN31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data input from DIO 24 +#define GPIO_DIN31_0_DIO24 0x01000000 +#define GPIO_DIN31_0_DIO24_BITN 24 +#define GPIO_DIN31_0_DIO24_M 0x01000000 +#define GPIO_DIN31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data input from DIO 23 +#define GPIO_DIN31_0_DIO23 0x00800000 +#define GPIO_DIN31_0_DIO23_BITN 23 +#define GPIO_DIN31_0_DIO23_M 0x00800000 +#define GPIO_DIN31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data input from DIO 22 +#define GPIO_DIN31_0_DIO22 0x00400000 +#define GPIO_DIN31_0_DIO22_BITN 22 +#define GPIO_DIN31_0_DIO22_M 0x00400000 +#define GPIO_DIN31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data input from DIO 21 +#define GPIO_DIN31_0_DIO21 0x00200000 +#define GPIO_DIN31_0_DIO21_BITN 21 +#define GPIO_DIN31_0_DIO21_M 0x00200000 +#define GPIO_DIN31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data input from DIO 20 +#define GPIO_DIN31_0_DIO20 0x00100000 +#define GPIO_DIN31_0_DIO20_BITN 20 +#define GPIO_DIN31_0_DIO20_M 0x00100000 +#define GPIO_DIN31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data input from DIO 19 +#define GPIO_DIN31_0_DIO19 0x00080000 +#define GPIO_DIN31_0_DIO19_BITN 19 +#define GPIO_DIN31_0_DIO19_M 0x00080000 +#define GPIO_DIN31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data input from DIO 18 +#define GPIO_DIN31_0_DIO18 0x00040000 +#define GPIO_DIN31_0_DIO18_BITN 18 +#define GPIO_DIN31_0_DIO18_M 0x00040000 +#define GPIO_DIN31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data input from DIO 17 +#define GPIO_DIN31_0_DIO17 0x00020000 +#define GPIO_DIN31_0_DIO17_BITN 17 +#define GPIO_DIN31_0_DIO17_M 0x00020000 +#define GPIO_DIN31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data input from DIO 16 +#define GPIO_DIN31_0_DIO16 0x00010000 +#define GPIO_DIN31_0_DIO16_BITN 16 +#define GPIO_DIN31_0_DIO16_M 0x00010000 +#define GPIO_DIN31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data input from DIO 15 +#define GPIO_DIN31_0_DIO15 0x00008000 +#define GPIO_DIN31_0_DIO15_BITN 15 +#define GPIO_DIN31_0_DIO15_M 0x00008000 +#define GPIO_DIN31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data input from DIO 14 +#define GPIO_DIN31_0_DIO14 0x00004000 +#define GPIO_DIN31_0_DIO14_BITN 14 +#define GPIO_DIN31_0_DIO14_M 0x00004000 +#define GPIO_DIN31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data input from DIO 13 +#define GPIO_DIN31_0_DIO13 0x00002000 +#define GPIO_DIN31_0_DIO13_BITN 13 +#define GPIO_DIN31_0_DIO13_M 0x00002000 +#define GPIO_DIN31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data input from DIO 12 +#define GPIO_DIN31_0_DIO12 0x00001000 +#define GPIO_DIN31_0_DIO12_BITN 12 +#define GPIO_DIN31_0_DIO12_M 0x00001000 +#define GPIO_DIN31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data input from DIO 11 +#define GPIO_DIN31_0_DIO11 0x00000800 +#define GPIO_DIN31_0_DIO11_BITN 11 +#define GPIO_DIN31_0_DIO11_M 0x00000800 +#define GPIO_DIN31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data input from DIO 10 +#define GPIO_DIN31_0_DIO10 0x00000400 +#define GPIO_DIN31_0_DIO10_BITN 10 +#define GPIO_DIN31_0_DIO10_M 0x00000400 +#define GPIO_DIN31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data input from DIO 9 +#define GPIO_DIN31_0_DIO9 0x00000200 +#define GPIO_DIN31_0_DIO9_BITN 9 +#define GPIO_DIN31_0_DIO9_M 0x00000200 +#define GPIO_DIN31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data input from DIO 8 +#define GPIO_DIN31_0_DIO8 0x00000100 +#define GPIO_DIN31_0_DIO8_BITN 8 +#define GPIO_DIN31_0_DIO8_M 0x00000100 +#define GPIO_DIN31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data input from DIO 7 +#define GPIO_DIN31_0_DIO7 0x00000080 +#define GPIO_DIN31_0_DIO7_BITN 7 +#define GPIO_DIN31_0_DIO7_M 0x00000080 +#define GPIO_DIN31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data input from DIO 6 +#define GPIO_DIN31_0_DIO6 0x00000040 +#define GPIO_DIN31_0_DIO6_BITN 6 +#define GPIO_DIN31_0_DIO6_M 0x00000040 +#define GPIO_DIN31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data input from DIO 5 +#define GPIO_DIN31_0_DIO5 0x00000020 +#define GPIO_DIN31_0_DIO5_BITN 5 +#define GPIO_DIN31_0_DIO5_M 0x00000020 +#define GPIO_DIN31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data input from DIO 4 +#define GPIO_DIN31_0_DIO4 0x00000010 +#define GPIO_DIN31_0_DIO4_BITN 4 +#define GPIO_DIN31_0_DIO4_M 0x00000010 +#define GPIO_DIN31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data input from DIO 3 +#define GPIO_DIN31_0_DIO3 0x00000008 +#define GPIO_DIN31_0_DIO3_BITN 3 +#define GPIO_DIN31_0_DIO3_M 0x00000008 +#define GPIO_DIN31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data input from DIO 2 +#define GPIO_DIN31_0_DIO2 0x00000004 +#define GPIO_DIN31_0_DIO2_BITN 2 +#define GPIO_DIN31_0_DIO2_M 0x00000004 +#define GPIO_DIN31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data input from DIO 1 +#define GPIO_DIN31_0_DIO1 0x00000002 +#define GPIO_DIN31_0_DIO1_BITN 1 +#define GPIO_DIN31_0_DIO1_M 0x00000002 +#define GPIO_DIN31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data input from DIO 0 +#define GPIO_DIN31_0_DIO0 0x00000001 +#define GPIO_DIN31_0_DIO0_BITN 0 +#define GPIO_DIN31_0_DIO0_M 0x00000001 +#define GPIO_DIN31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOE31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data output enable for DIO 31 +#define GPIO_DOE31_0_DIO31 0x80000000 +#define GPIO_DOE31_0_DIO31_BITN 31 +#define GPIO_DOE31_0_DIO31_M 0x80000000 +#define GPIO_DOE31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data output enable for DIO 30 +#define GPIO_DOE31_0_DIO30 0x40000000 +#define GPIO_DOE31_0_DIO30_BITN 30 +#define GPIO_DOE31_0_DIO30_M 0x40000000 +#define GPIO_DOE31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data output enable for DIO 29 +#define GPIO_DOE31_0_DIO29 0x20000000 +#define GPIO_DOE31_0_DIO29_BITN 29 +#define GPIO_DOE31_0_DIO29_M 0x20000000 +#define GPIO_DOE31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data output enable for DIO 28 +#define GPIO_DOE31_0_DIO28 0x10000000 +#define GPIO_DOE31_0_DIO28_BITN 28 +#define GPIO_DOE31_0_DIO28_M 0x10000000 +#define GPIO_DOE31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data output enable for DIO 27 +#define GPIO_DOE31_0_DIO27 0x08000000 +#define GPIO_DOE31_0_DIO27_BITN 27 +#define GPIO_DOE31_0_DIO27_M 0x08000000 +#define GPIO_DOE31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data output enable for DIO 26 +#define GPIO_DOE31_0_DIO26 0x04000000 +#define GPIO_DOE31_0_DIO26_BITN 26 +#define GPIO_DOE31_0_DIO26_M 0x04000000 +#define GPIO_DOE31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data output enable for DIO 25 +#define GPIO_DOE31_0_DIO25 0x02000000 +#define GPIO_DOE31_0_DIO25_BITN 25 +#define GPIO_DOE31_0_DIO25_M 0x02000000 +#define GPIO_DOE31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data output enable for DIO 24 +#define GPIO_DOE31_0_DIO24 0x01000000 +#define GPIO_DOE31_0_DIO24_BITN 24 +#define GPIO_DOE31_0_DIO24_M 0x01000000 +#define GPIO_DOE31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data output enable for DIO 23 +#define GPIO_DOE31_0_DIO23 0x00800000 +#define GPIO_DOE31_0_DIO23_BITN 23 +#define GPIO_DOE31_0_DIO23_M 0x00800000 +#define GPIO_DOE31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data output enable for DIO 22 +#define GPIO_DOE31_0_DIO22 0x00400000 +#define GPIO_DOE31_0_DIO22_BITN 22 +#define GPIO_DOE31_0_DIO22_M 0x00400000 +#define GPIO_DOE31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data output enable for DIO 21 +#define GPIO_DOE31_0_DIO21 0x00200000 +#define GPIO_DOE31_0_DIO21_BITN 21 +#define GPIO_DOE31_0_DIO21_M 0x00200000 +#define GPIO_DOE31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data output enable for DIO 20 +#define GPIO_DOE31_0_DIO20 0x00100000 +#define GPIO_DOE31_0_DIO20_BITN 20 +#define GPIO_DOE31_0_DIO20_M 0x00100000 +#define GPIO_DOE31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data output enable for DIO 19 +#define GPIO_DOE31_0_DIO19 0x00080000 +#define GPIO_DOE31_0_DIO19_BITN 19 +#define GPIO_DOE31_0_DIO19_M 0x00080000 +#define GPIO_DOE31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data output enable for DIO 18 +#define GPIO_DOE31_0_DIO18 0x00040000 +#define GPIO_DOE31_0_DIO18_BITN 18 +#define GPIO_DOE31_0_DIO18_M 0x00040000 +#define GPIO_DOE31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data output enable for DIO 17 +#define GPIO_DOE31_0_DIO17 0x00020000 +#define GPIO_DOE31_0_DIO17_BITN 17 +#define GPIO_DOE31_0_DIO17_M 0x00020000 +#define GPIO_DOE31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data output enable for DIO 16 +#define GPIO_DOE31_0_DIO16 0x00010000 +#define GPIO_DOE31_0_DIO16_BITN 16 +#define GPIO_DOE31_0_DIO16_M 0x00010000 +#define GPIO_DOE31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data output enable for DIO 15 +#define GPIO_DOE31_0_DIO15 0x00008000 +#define GPIO_DOE31_0_DIO15_BITN 15 +#define GPIO_DOE31_0_DIO15_M 0x00008000 +#define GPIO_DOE31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data output enable for DIO 14 +#define GPIO_DOE31_0_DIO14 0x00004000 +#define GPIO_DOE31_0_DIO14_BITN 14 +#define GPIO_DOE31_0_DIO14_M 0x00004000 +#define GPIO_DOE31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data output enable for DIO 13 +#define GPIO_DOE31_0_DIO13 0x00002000 +#define GPIO_DOE31_0_DIO13_BITN 13 +#define GPIO_DOE31_0_DIO13_M 0x00002000 +#define GPIO_DOE31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data output enable for DIO 12 +#define GPIO_DOE31_0_DIO12 0x00001000 +#define GPIO_DOE31_0_DIO12_BITN 12 +#define GPIO_DOE31_0_DIO12_M 0x00001000 +#define GPIO_DOE31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data output enable for DIO 11 +#define GPIO_DOE31_0_DIO11 0x00000800 +#define GPIO_DOE31_0_DIO11_BITN 11 +#define GPIO_DOE31_0_DIO11_M 0x00000800 +#define GPIO_DOE31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data output enable for DIO 10 +#define GPIO_DOE31_0_DIO10 0x00000400 +#define GPIO_DOE31_0_DIO10_BITN 10 +#define GPIO_DOE31_0_DIO10_M 0x00000400 +#define GPIO_DOE31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data output enable for DIO 9 +#define GPIO_DOE31_0_DIO9 0x00000200 +#define GPIO_DOE31_0_DIO9_BITN 9 +#define GPIO_DOE31_0_DIO9_M 0x00000200 +#define GPIO_DOE31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data output enable for DIO 8 +#define GPIO_DOE31_0_DIO8 0x00000100 +#define GPIO_DOE31_0_DIO8_BITN 8 +#define GPIO_DOE31_0_DIO8_M 0x00000100 +#define GPIO_DOE31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data output enable for DIO 7 +#define GPIO_DOE31_0_DIO7 0x00000080 +#define GPIO_DOE31_0_DIO7_BITN 7 +#define GPIO_DOE31_0_DIO7_M 0x00000080 +#define GPIO_DOE31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data output enable for DIO 6 +#define GPIO_DOE31_0_DIO6 0x00000040 +#define GPIO_DOE31_0_DIO6_BITN 6 +#define GPIO_DOE31_0_DIO6_M 0x00000040 +#define GPIO_DOE31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data output enable for DIO 5 +#define GPIO_DOE31_0_DIO5 0x00000020 +#define GPIO_DOE31_0_DIO5_BITN 5 +#define GPIO_DOE31_0_DIO5_M 0x00000020 +#define GPIO_DOE31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data output enable for DIO 4 +#define GPIO_DOE31_0_DIO4 0x00000010 +#define GPIO_DOE31_0_DIO4_BITN 4 +#define GPIO_DOE31_0_DIO4_M 0x00000010 +#define GPIO_DOE31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data output enable for DIO 3 +#define GPIO_DOE31_0_DIO3 0x00000008 +#define GPIO_DOE31_0_DIO3_BITN 3 +#define GPIO_DOE31_0_DIO3_M 0x00000008 +#define GPIO_DOE31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data output enable for DIO 2 +#define GPIO_DOE31_0_DIO2 0x00000004 +#define GPIO_DOE31_0_DIO2_BITN 2 +#define GPIO_DOE31_0_DIO2_M 0x00000004 +#define GPIO_DOE31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data output enable for DIO 1 +#define GPIO_DOE31_0_DIO1 0x00000002 +#define GPIO_DOE31_0_DIO1_BITN 1 +#define GPIO_DOE31_0_DIO1_M 0x00000002 +#define GPIO_DOE31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data output enable for DIO 0 +#define GPIO_DOE31_0_DIO0 0x00000001 +#define GPIO_DOE31_0_DIO0_BITN 0 +#define GPIO_DOE31_0_DIO0_M 0x00000001 +#define GPIO_DOE31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_EVFLAGS31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Event for DIO 31 +#define GPIO_EVFLAGS31_0_DIO31 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_BITN 31 +#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Event for DIO 30 +#define GPIO_EVFLAGS31_0_DIO30 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_BITN 30 +#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Event for DIO 29 +#define GPIO_EVFLAGS31_0_DIO29 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_BITN 29 +#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Event for DIO 28 +#define GPIO_EVFLAGS31_0_DIO28 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_BITN 28 +#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Event for DIO 27 +#define GPIO_EVFLAGS31_0_DIO27 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_BITN 27 +#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Event for DIO 26 +#define GPIO_EVFLAGS31_0_DIO26 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_BITN 26 +#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Event for DIO 25 +#define GPIO_EVFLAGS31_0_DIO25 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_BITN 25 +#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Event for DIO 24 +#define GPIO_EVFLAGS31_0_DIO24 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_BITN 24 +#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Event for DIO 23 +#define GPIO_EVFLAGS31_0_DIO23 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_BITN 23 +#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Event for DIO 22 +#define GPIO_EVFLAGS31_0_DIO22 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_BITN 22 +#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Event for DIO 21 +#define GPIO_EVFLAGS31_0_DIO21 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_BITN 21 +#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Event for DIO 20 +#define GPIO_EVFLAGS31_0_DIO20 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_BITN 20 +#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Event for DIO 19 +#define GPIO_EVFLAGS31_0_DIO19 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_BITN 19 +#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Event for DIO 18 +#define GPIO_EVFLAGS31_0_DIO18 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_BITN 18 +#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Event for DIO 17 +#define GPIO_EVFLAGS31_0_DIO17 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_BITN 17 +#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Event for DIO 16 +#define GPIO_EVFLAGS31_0_DIO16 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_BITN 16 +#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Event for DIO 15 +#define GPIO_EVFLAGS31_0_DIO15 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_BITN 15 +#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Event for DIO 14 +#define GPIO_EVFLAGS31_0_DIO14 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_BITN 14 +#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Event for DIO 13 +#define GPIO_EVFLAGS31_0_DIO13 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_BITN 13 +#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Event for DIO 12 +#define GPIO_EVFLAGS31_0_DIO12 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_BITN 12 +#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Event for DIO 11 +#define GPIO_EVFLAGS31_0_DIO11 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_BITN 11 +#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Event for DIO 10 +#define GPIO_EVFLAGS31_0_DIO10 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_BITN 10 +#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Event for DIO 9 +#define GPIO_EVFLAGS31_0_DIO9 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_BITN 9 +#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Event for DIO 8 +#define GPIO_EVFLAGS31_0_DIO8 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_BITN 8 +#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Event for DIO 7 +#define GPIO_EVFLAGS31_0_DIO7 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_BITN 7 +#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Event for DIO 6 +#define GPIO_EVFLAGS31_0_DIO6 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_BITN 6 +#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Event for DIO 5 +#define GPIO_EVFLAGS31_0_DIO5 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_BITN 5 +#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Event for DIO 4 +#define GPIO_EVFLAGS31_0_DIO4 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_BITN 4 +#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Event for DIO 3 +#define GPIO_EVFLAGS31_0_DIO3 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_BITN 3 +#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Event for DIO 2 +#define GPIO_EVFLAGS31_0_DIO2 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_BITN 2 +#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Event for DIO 1 +#define GPIO_EVFLAGS31_0_DIO1 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_BITN 1 +#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Event for DIO 0 +#define GPIO_EVFLAGS31_0_DIO0 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_BITN 0 +#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_S 0 + + +#endif // __GPIO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpt.h new file mode 100644 index 0000000..710edd8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpt.h @@ -0,0 +1,1686 @@ +/****************************************************************************** +* Filename: hw_gpt_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_GPT_H__ +#define __HW_GPT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// GPT component +// +//***************************************************************************** +// Configuration +#define GPT_O_CFG 0x00000000 + +// Timer A Mode +#define GPT_O_TAMR 0x00000004 + +// Timer B Mode +#define GPT_O_TBMR 0x00000008 + +// Control +#define GPT_O_CTL 0x0000000C + +// Synch Register +#define GPT_O_SYNC 0x00000010 + +// Interrupt Mask +#define GPT_O_IMR 0x00000018 + +// Raw Interrupt Status +#define GPT_O_RIS 0x0000001C + +// Masked Interrupt Status +#define GPT_O_MIS 0x00000020 + +// Interrupt Clear +#define GPT_O_ICLR 0x00000024 + +// Timer A Interval Load Register +#define GPT_O_TAILR 0x00000028 + +// Timer B Interval Load Register +#define GPT_O_TBILR 0x0000002C + +// Timer A Match Register +#define GPT_O_TAMATCHR 0x00000030 + +// Timer B Match Register +#define GPT_O_TBMATCHR 0x00000034 + +// Timer A Pre-scale +#define GPT_O_TAPR 0x00000038 + +// Timer B Pre-scale +#define GPT_O_TBPR 0x0000003C + +// Timer A Pre-scale Match +#define GPT_O_TAPMR 0x00000040 + +// Timer B Pre-scale Match +#define GPT_O_TBPMR 0x00000044 + +// Timer A Register +#define GPT_O_TAR 0x00000048 + +// Timer B Register +#define GPT_O_TBR 0x0000004C + +// Timer A Value +#define GPT_O_TAV 0x00000050 + +// Timer B Value +#define GPT_O_TBV 0x00000054 + +// Timer A Pre-scale Snap-shot +#define GPT_O_TAPS 0x0000005C + +// Timer B Pre-scale Snap-shot +#define GPT_O_TBPS 0x00000060 + +// Timer A Pre-scale Value +#define GPT_O_TAPV 0x00000064 + +// Timer B Pre-scale Value +#define GPT_O_TBPV 0x00000068 + +// DMA Event +#define GPT_O_DMAEV 0x0000006C + +// Peripheral Version +#define GPT_O_VERSION 0x00000FB0 + +// Combined CCP Output +#define GPT_O_ANDCCP 0x00000FB4 + +//***************************************************************************** +// +// Register: GPT_O_CFG +// +//***************************************************************************** +// Field: [2:0] CFG +// +// GPT Configuration +// 0x2- 0x3 - Reserved +// 0x5- 0x7 - Reserved +// ENUMs: +// 16BIT_TIMER 16-bit timer configuration. +// Configure for two 16-bit +// timers. +// Also see TAMR.TAMR and +// TBMR.TBMR. +// 32BIT_TIMER 32-bit timer configuration +#define GPT_CFG_CFG_W 3 +#define GPT_CFG_CFG_M 0x00000007 +#define GPT_CFG_CFG_S 0 +#define GPT_CFG_CFG_16BIT_TIMER 0x00000004 +#define GPT_CFG_CFG_32BIT_TIMER 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_TAMR +// +//***************************************************************************** +// Field: [15:13] TCACT +// +// Timer Compare Action Select +// ENUMs: +// CLRSET_ON_TO Clear CCP output pin immediately and set on +// Time-Out +// SETCLR_ON_TO Set CCP output pin immediately and clear on +// Time-Out +// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on +// Time-Out +// SETTOG_ON_TO Set CCP output pin immediately and toggle on +// Time-Out +// SET_ON_TO Set CCP output pin on Time-Out +// CLR_ON_TO Clear CCP output pin on Time-Out +// TOG_ON_TO Toggle State on Time-Out +// DIS_CMP Disable compare operations +#define GPT_TAMR_TCACT_W 3 +#define GPT_TAMR_TCACT_M 0x0000E000 +#define GPT_TAMR_TCACT_S 13 +#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TAMR_TCACT_DIS_CMP 0x00000000 + +// Field: [12] TACINTD +// +// One-Shot/Periodic Interrupt Disable +// ENUMs: +// DIS_TO_INTR Time-out interrupt are disabled +// EN_TO_INTR Time-out interrupt function as normal +#define GPT_TAMR_TACINTD 0x00001000 +#define GPT_TAMR_TACINTD_BITN 12 +#define GPT_TAMR_TACINTD_M 0x00001000 +#define GPT_TAMR_TACINTD_S 12 +#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 +#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 + +// Field: [11] TAPLO +// +// GPTM Timer A PWM Legacy Operation +// +// 0 Legacy operation with CCP pin driven Low when the TAILR +// register is reloaded after the timer reaches 0. +// +// 1 CCP is driven High when the TAILR register is reloaded after the timer +// reaches 0. +// +// This bit is only valid in PWM mode. +// ENUMs: +// CCP_ON_TO CCP output pin is set to 1 on time-out +// LEGACY Legacy operation +#define GPT_TAMR_TAPLO 0x00000800 +#define GPT_TAMR_TAPLO_BITN 11 +#define GPT_TAMR_TAPLO_M 0x00000800 +#define GPT_TAMR_TAPLO_S 11 +#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 +#define GPT_TAMR_TAPLO_LEGACY 0x00000000 + +// Field: [10] TAMRSU +// +// Timer A Match Register Update mode +// +// This bit defines when the TAMATCHR and TAPR registers are updated. +// +// If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and +// TAPR are updated when the timer is enabled. +// If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and +// TAPR are updated according to the configuration of this bit. +// ENUMs: +// TOUPDATE Update TAMATCHR and TAPR, if used, on the next +// time-out. +// CYCLEUPDATE Update TAMATCHR and TAPR, if used, on the next +// cycle. +#define GPT_TAMR_TAMRSU 0x00000400 +#define GPT_TAMR_TAMRSU_BITN 10 +#define GPT_TAMR_TAMRSU_M 0x00000400 +#define GPT_TAMR_TAMRSU_S 10 +#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 +#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 + +// Field: [9] TAPWMIE +// +// GPTM Timer A PWM Interrupt Enable +// This bit enables interrupts in PWM mode on rising, falling, or both edges of +// the CCP output, as defined by the CTL.TAEVENT +// In addition, when this bit is set and a capture event occurs, Timer A +// automatically generates triggers to the DMA if the trigger capability is +// enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit +// respectively. +// +// 0 Capture event interrupt is disabled. +// 1 Capture event interrupt is enabled. +// This bit is only valid in PWM mode. +// ENUMs: +// EN Interrupt is enabled. This bit is only valid in +// PWM mode. +// DIS Interrupt is disabled. +#define GPT_TAMR_TAPWMIE 0x00000200 +#define GPT_TAMR_TAPWMIE_BITN 9 +#define GPT_TAMR_TAPWMIE_M 0x00000200 +#define GPT_TAMR_TAPWMIE_S 9 +#define GPT_TAMR_TAPWMIE_EN 0x00000200 +#define GPT_TAMR_TAPWMIE_DIS 0x00000000 + +// Field: [8] TAILD +// +// GPT Timer A PWM Interval Load Write +// ENUMs: +// TOUPDATE Update the TAR register with the value in the +// TAILR register on the next timeout. If the +// prescaler is used, update the TAPS register +// with the value in the TAPR register on the next +// timeout. +// CYCLEUPDATE Update the TAR register with the value in the +// TAILR register on the next clock cycle. If the +// pre-scaler is used, update the TAPS register +// with the value in the TAPR register on the next +// clock cycle. +#define GPT_TAMR_TAILD 0x00000100 +#define GPT_TAMR_TAILD_BITN 8 +#define GPT_TAMR_TAILD_M 0x00000100 +#define GPT_TAMR_TAILD_S 8 +#define GPT_TAMR_TAILD_TOUPDATE 0x00000100 +#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 + +// Field: [7] TASNAPS +// +// GPT Timer A Snap-Shot Mode +// ENUMs: +// EN If Timer A is configured in the periodic mode, the +// actual free-running value of Timer A is loaded +// at the time-out event into the GPT Timer A +// (TAR) register. +// DIS Snap-shot mode is disabled. +#define GPT_TAMR_TASNAPS 0x00000080 +#define GPT_TAMR_TASNAPS_BITN 7 +#define GPT_TAMR_TASNAPS_M 0x00000080 +#define GPT_TAMR_TASNAPS_S 7 +#define GPT_TAMR_TASNAPS_EN 0x00000080 +#define GPT_TAMR_TASNAPS_DIS 0x00000000 + +// Field: [6] TAWOT +// +// GPT Timer A Wait-On-Trigger +// ENUMs: +// WAIT If Timer A is enabled (CTL.TAEN = 1), Timer A does +// not begin counting until it receives a trigger +// from the timer in the previous position in the +// daisy chain. This bit must be clear for GPT +// Module 0, Timer A. This function is valid for +// one-shot, periodic, and PWM modes +// NOWAIT Timer A begins counting as soon as it is enabled. +#define GPT_TAMR_TAWOT 0x00000040 +#define GPT_TAMR_TAWOT_BITN 6 +#define GPT_TAMR_TAWOT_M 0x00000040 +#define GPT_TAMR_TAWOT_S 6 +#define GPT_TAMR_TAWOT_WAIT 0x00000040 +#define GPT_TAMR_TAWOT_NOWAIT 0x00000000 + +// Field: [5] TAMIE +// +// GPT Timer A Match Interrupt Enable +// ENUMs: +// EN An interrupt is generated when the match value in +// TAMATCHR is reached in the one-shot and +// periodic modes. +// DIS The match interrupt is disabled for match events. +// Additionally, output triggers on match events +// are prevented. +#define GPT_TAMR_TAMIE 0x00000020 +#define GPT_TAMR_TAMIE_BITN 5 +#define GPT_TAMR_TAMIE_M 0x00000020 +#define GPT_TAMR_TAMIE_S 5 +#define GPT_TAMR_TAMIE_EN 0x00000020 +#define GPT_TAMR_TAMIE_DIS 0x00000000 + +// Field: [4] TACDIR +// +// GPT Timer A Count Direction +// ENUMs: +// UP The timer counts up. When counting up, the timer +// starts from a value of 0x0. +// DOWN The timer counts down. +#define GPT_TAMR_TACDIR 0x00000010 +#define GPT_TAMR_TACDIR_BITN 4 +#define GPT_TAMR_TACDIR_M 0x00000010 +#define GPT_TAMR_TACDIR_S 4 +#define GPT_TAMR_TACDIR_UP 0x00000010 +#define GPT_TAMR_TACDIR_DOWN 0x00000000 + +// Field: [3] TAAMS +// +// GPT Timer A Alternate Mode +// +// Note: To enable PWM mode, you must also clear TACM and then configure TAMR +// field to 0x2. +// ENUMs: +// PWM PWM mode is enabled +// CAP_COMP Capture/Compare mode is enabled. +#define GPT_TAMR_TAAMS 0x00000008 +#define GPT_TAMR_TAAMS_BITN 3 +#define GPT_TAMR_TAAMS_M 0x00000008 +#define GPT_TAMR_TAAMS_S 3 +#define GPT_TAMR_TAAMS_PWM 0x00000008 +#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 + +// Field: [2] TACM +// +// GPT Timer A Capture Mode +// ENUMs: +// EDGTIME Edge-Time mode +// EDGCNT Edge-Count mode +#define GPT_TAMR_TACM 0x00000004 +#define GPT_TAMR_TACM_BITN 2 +#define GPT_TAMR_TACM_M 0x00000004 +#define GPT_TAMR_TACM_S 2 +#define GPT_TAMR_TACM_EDGTIME 0x00000004 +#define GPT_TAMR_TACM_EDGCNT 0x00000000 + +// Field: [1:0] TAMR +// +// GPT Timer A Mode +// +// 0x0 Reserved +// 0x1 One-Shot Timer mode +// 0x2 Periodic Timer mode +// 0x3 Capture mode +// The Timer mode is based on the timer configuration defined by bits 2:0 in +// the CFG register +// ENUMs: +// CAPTURE Capture mode +// PERIODIC Periodic Timer mode +// ONE_SHOT One-Shot Timer mode +#define GPT_TAMR_TAMR_W 2 +#define GPT_TAMR_TAMR_M 0x00000003 +#define GPT_TAMR_TAMR_S 0 +#define GPT_TAMR_TAMR_CAPTURE 0x00000003 +#define GPT_TAMR_TAMR_PERIODIC 0x00000002 +#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 + +//***************************************************************************** +// +// Register: GPT_O_TBMR +// +//***************************************************************************** +// Field: [15:13] TCACT +// +// Timer Compare Action Select +// ENUMs: +// CLRSET_ON_TO Clear CCP output pin immediately and set on +// Time-Out +// SETCLR_ON_TO Set CCP output pin immediately and clear on +// Time-Out +// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on +// Time-Out +// SETTOG_ON_TO Set CCP output pin immediately and toggle on +// Time-Out +// SET_ON_TO Set CCP output pin on Time-Out +// CLR_ON_TO Clear CCP output pin on Time-Out +// TOG_ON_TO Toggle State on Time-Out +// DIS_CMP Disable compare operations +#define GPT_TBMR_TCACT_W 3 +#define GPT_TBMR_TCACT_M 0x0000E000 +#define GPT_TBMR_TCACT_S 13 +#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TBMR_TCACT_DIS_CMP 0x00000000 + +// Field: [12] TBCINTD +// +// One-Shot/Periodic Interrupt Mode +// ENUMs: +// DIS_TO_INTR Mask Time-Out Interrupt +// EN_TO_INTR Normal Time-Out Interrupt +#define GPT_TBMR_TBCINTD 0x00001000 +#define GPT_TBMR_TBCINTD_BITN 12 +#define GPT_TBMR_TBCINTD_M 0x00001000 +#define GPT_TBMR_TBCINTD_S 12 +#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 +#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 + +// Field: [11] TBPLO +// +// GPTM Timer B PWM Legacy Operation +// +// 0 Legacy operation with CCP pin driven Low when the TBILR +// register is reloaded after the timer reaches 0. +// +// 1 CCP is driven High when the TBILR register is reloaded after the timer +// reaches 0. +// +// This bit is only valid in PWM mode. +// ENUMs: +// CCP_ON_TO CCP output pin is set to 1 on time-out +// LEGACY Legacy operation +#define GPT_TBMR_TBPLO 0x00000800 +#define GPT_TBMR_TBPLO_BITN 11 +#define GPT_TBMR_TBPLO_M 0x00000800 +#define GPT_TBMR_TBPLO_S 11 +#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 +#define GPT_TBMR_TBPLO_LEGACY 0x00000000 + +// Field: [10] TBMRSU +// +// Timer B Match Register Update mode +// +// This bit defines when the TBMATCHR and TBPR registers are updated +// +// If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR +// and TBPR are updated when the timer is enabled. +// If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR +// and TBPR are updated according to the configuration of this bit. +// ENUMs: +// TOUPDATE Update TBMATCHR and TBPR, if used, on the next +// time-out. +// CYCLEUPDATE Update TBMATCHR and TBPR, if used, on the next +// cycle. +#define GPT_TBMR_TBMRSU 0x00000400 +#define GPT_TBMR_TBMRSU_BITN 10 +#define GPT_TBMR_TBMRSU_M 0x00000400 +#define GPT_TBMR_TBMRSU_S 10 +#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 +#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 + +// Field: [9] TBPWMIE +// +// GPTM Timer B PWM Interrupt Enable +// This bit enables interrupts in PWM mode on rising, falling, or both edges of +// the CCP output, as defined by the CTL.TBEVENT +// In addition, when this bit is set and a capture event occurs, Timer A +// automatically generates triggers to the DMA if the trigger capability is +// enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit +// respectively. +// +// 0 Capture event interrupt is disabled. +// 1 Capture event interrupt is enabled. +// This bit is only valid in PWM mode. +// ENUMs: +// EN Interrupt is enabled. This bit is only valid in +// PWM mode. +// DIS Interrupt is disabled. +#define GPT_TBMR_TBPWMIE 0x00000200 +#define GPT_TBMR_TBPWMIE_BITN 9 +#define GPT_TBMR_TBPWMIE_M 0x00000200 +#define GPT_TBMR_TBPWMIE_S 9 +#define GPT_TBMR_TBPWMIE_EN 0x00000200 +#define GPT_TBMR_TBPWMIE_DIS 0x00000000 + +// Field: [8] TBILD +// +// GPT Timer B PWM Interval Load Write +// ENUMs: +// TOUPDATE Update the TBR register with the value in the +// TBILR register on the next timeout. If the +// prescaler is used, update the TBPS register +// with the value in the TBPR register on the next +// timeout. +// CYCLEUPDATE Update the TBR register with the value in the +// TBILR register on the next clock cycle. If the +// pre-scaler is used, update the TBPS register +// with the value in the TBPR register on the next +// clock cycle. +#define GPT_TBMR_TBILD 0x00000100 +#define GPT_TBMR_TBILD_BITN 8 +#define GPT_TBMR_TBILD_M 0x00000100 +#define GPT_TBMR_TBILD_S 8 +#define GPT_TBMR_TBILD_TOUPDATE 0x00000100 +#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 + +// Field: [7] TBSNAPS +// +// GPT Timer B Snap-Shot Mode +// ENUMs: +// EN If Timer B is configured in the periodic mode +// DIS Snap-shot mode is disabled. +#define GPT_TBMR_TBSNAPS 0x00000080 +#define GPT_TBMR_TBSNAPS_BITN 7 +#define GPT_TBMR_TBSNAPS_M 0x00000080 +#define GPT_TBMR_TBSNAPS_S 7 +#define GPT_TBMR_TBSNAPS_EN 0x00000080 +#define GPT_TBMR_TBSNAPS_DIS 0x00000000 + +// Field: [6] TBWOT +// +// GPT Timer B Wait-On-Trigger +// ENUMs: +// WAIT If Timer B is enabled (CTL.TBEN is set), Timer B +// does not begin counting until it receives a +// trigger from the timer in the previous position +// in the daisy chain. This function is valid for +// one-shot, periodic, and PWM modes +// NOWAIT Timer B begins counting as soon as it is enabled. +#define GPT_TBMR_TBWOT 0x00000040 +#define GPT_TBMR_TBWOT_BITN 6 +#define GPT_TBMR_TBWOT_M 0x00000040 +#define GPT_TBMR_TBWOT_S 6 +#define GPT_TBMR_TBWOT_WAIT 0x00000040 +#define GPT_TBMR_TBWOT_NOWAIT 0x00000000 + +// Field: [5] TBMIE +// +// GPT Timer B Match Interrupt Enable. +// ENUMs: +// EN An interrupt is generated when the match value in +// the TBMATCHR register is reached in the +// one-shot and periodic modes. +// DIS The match interrupt is disabled for match events. +// Additionally, output triggers on match events +// are prevented. +#define GPT_TBMR_TBMIE 0x00000020 +#define GPT_TBMR_TBMIE_BITN 5 +#define GPT_TBMR_TBMIE_M 0x00000020 +#define GPT_TBMR_TBMIE_S 5 +#define GPT_TBMR_TBMIE_EN 0x00000020 +#define GPT_TBMR_TBMIE_DIS 0x00000000 + +// Field: [4] TBCDIR +// +// GPT Timer B Count Direction +// ENUMs: +// UP The timer counts up. When counting up, the timer +// starts from a value of 0x0. +// DOWN The timer counts down. +#define GPT_TBMR_TBCDIR 0x00000010 +#define GPT_TBMR_TBCDIR_BITN 4 +#define GPT_TBMR_TBCDIR_M 0x00000010 +#define GPT_TBMR_TBCDIR_S 4 +#define GPT_TBMR_TBCDIR_UP 0x00000010 +#define GPT_TBMR_TBCDIR_DOWN 0x00000000 + +// Field: [3] TBAMS +// +// GPT Timer B Alternate Mode +// +// Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR +// field to 0x2. +// ENUMs: +// PWM PWM mode is enabled +// CAP_COMP Capture/Compare mode is enabled. +#define GPT_TBMR_TBAMS 0x00000008 +#define GPT_TBMR_TBAMS_BITN 3 +#define GPT_TBMR_TBAMS_M 0x00000008 +#define GPT_TBMR_TBAMS_S 3 +#define GPT_TBMR_TBAMS_PWM 0x00000008 +#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 + +// Field: [2] TBCM +// +// GPT Timer B Capture Mode +// ENUMs: +// EDGTIME Edge-Time mode +// EDGCNT Edge-Count mode +#define GPT_TBMR_TBCM 0x00000004 +#define GPT_TBMR_TBCM_BITN 2 +#define GPT_TBMR_TBCM_M 0x00000004 +#define GPT_TBMR_TBCM_S 2 +#define GPT_TBMR_TBCM_EDGTIME 0x00000004 +#define GPT_TBMR_TBCM_EDGCNT 0x00000000 + +// Field: [1:0] TBMR +// +// GPT Timer B Mode +// +// 0x0 Reserved +// 0x1 One-Shot Timer mode +// 0x2 Periodic Timer mode +// 0x3 Capture mode +// The Timer mode is based on the timer configuration defined by bits 2:0 in +// the CFG register +// ENUMs: +// CAPTURE Capture mode +// PERIODIC Periodic Timer mode +// ONE_SHOT One-Shot Timer mode +#define GPT_TBMR_TBMR_W 2 +#define GPT_TBMR_TBMR_M 0x00000003 +#define GPT_TBMR_TBMR_S 0 +#define GPT_TBMR_TBMR_CAPTURE 0x00000003 +#define GPT_TBMR_TBMR_PERIODIC 0x00000002 +#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 + +//***************************************************************************** +// +// Register: GPT_O_CTL +// +//***************************************************************************** +// Field: [14] TBPWML +// +// GPT Timer B PWM Output Level +// +// 0: Output is unaffected. +// 1: Output is inverted. +// ENUMs: +// INVERTED Inverted +// NORMAL Not inverted +#define GPT_CTL_TBPWML 0x00004000 +#define GPT_CTL_TBPWML_BITN 14 +#define GPT_CTL_TBPWML_M 0x00004000 +#define GPT_CTL_TBPWML_S 14 +#define GPT_CTL_TBPWML_INVERTED 0x00004000 +#define GPT_CTL_TBPWML_NORMAL 0x00000000 + +// Field: [11:10] TBEVENT +// +// GPT Timer B Event Mode +// +// The values in this register are defined as follows: +// Value Description +// 0x0 Positive edge +// 0x1 Negative edge +// 0x2 Reserved +// 0x3 Both edges +// Note: If PWM output inversion is enabled, edge detection interrupt +// behavior is reversed. Thus, if a positive-edge interrupt trigger +// has been set and the PWM inversion generates a postive +// edge, no event-trigger interrupt asserts. Instead, the interrupt +// is generated on the negative edge of the PWM signal. +// ENUMs: +// BOTH Both edges +// NEG Negative edge +// POS Positive edge +#define GPT_CTL_TBEVENT_W 2 +#define GPT_CTL_TBEVENT_M 0x00000C00 +#define GPT_CTL_TBEVENT_S 10 +#define GPT_CTL_TBEVENT_BOTH 0x00000C00 +#define GPT_CTL_TBEVENT_NEG 0x00000400 +#define GPT_CTL_TBEVENT_POS 0x00000000 + +// Field: [9] TBSTALL +// +// GPT Timer B Stall Enable +// ENUMs: +// EN Timer B freezes counting while the processor is +// halted by the debugger. +// DIS Timer B continues counting while the processor is +// halted by the debugger. +#define GPT_CTL_TBSTALL 0x00000200 +#define GPT_CTL_TBSTALL_BITN 9 +#define GPT_CTL_TBSTALL_M 0x00000200 +#define GPT_CTL_TBSTALL_S 9 +#define GPT_CTL_TBSTALL_EN 0x00000200 +#define GPT_CTL_TBSTALL_DIS 0x00000000 + +// Field: [8] TBEN +// +// GPT Timer B Enable +// ENUMs: +// EN Timer B is enabled and begins counting or the +// capture logic is enabled based on CFG register. +// DIS Timer B is disabled. +#define GPT_CTL_TBEN 0x00000100 +#define GPT_CTL_TBEN_BITN 8 +#define GPT_CTL_TBEN_M 0x00000100 +#define GPT_CTL_TBEN_S 8 +#define GPT_CTL_TBEN_EN 0x00000100 +#define GPT_CTL_TBEN_DIS 0x00000000 + +// Field: [6] TAPWML +// +// GPT Timer A PWM Output Level +// ENUMs: +// INVERTED Inverted +// NORMAL Not inverted +#define GPT_CTL_TAPWML 0x00000040 +#define GPT_CTL_TAPWML_BITN 6 +#define GPT_CTL_TAPWML_M 0x00000040 +#define GPT_CTL_TAPWML_S 6 +#define GPT_CTL_TAPWML_INVERTED 0x00000040 +#define GPT_CTL_TAPWML_NORMAL 0x00000000 + +// Field: [3:2] TAEVENT +// +// GPT Timer A Event Mode +// +// The values in this register are defined as follows: +// Value Description +// 0x0 Positive edge +// 0x1 Negative edge +// 0x2 Reserved +// 0x3 Both edges +// Note: If PWM output inversion is enabled, edge detection interrupt +// behavior is reversed. Thus, if a positive-edge interrupt trigger +// has been set and the PWM inversion generates a postive +// edge, no event-trigger interrupt asserts. Instead, the interrupt +// is generated on the negative edge of the PWM signal. +// ENUMs: +// BOTH Both edges +// NEG Negative edge +// POS Positive edge +#define GPT_CTL_TAEVENT_W 2 +#define GPT_CTL_TAEVENT_M 0x0000000C +#define GPT_CTL_TAEVENT_S 2 +#define GPT_CTL_TAEVENT_BOTH 0x0000000C +#define GPT_CTL_TAEVENT_NEG 0x00000004 +#define GPT_CTL_TAEVENT_POS 0x00000000 + +// Field: [1] TASTALL +// +// GPT Timer A Stall Enable +// ENUMs: +// EN Timer A freezes counting while the processor is +// halted by the debugger. +// DIS Timer A continues counting while the processor is +// halted by the debugger. +#define GPT_CTL_TASTALL 0x00000002 +#define GPT_CTL_TASTALL_BITN 1 +#define GPT_CTL_TASTALL_M 0x00000002 +#define GPT_CTL_TASTALL_S 1 +#define GPT_CTL_TASTALL_EN 0x00000002 +#define GPT_CTL_TASTALL_DIS 0x00000000 + +// Field: [0] TAEN +// +// GPT Timer A Enable +// ENUMs: +// EN Timer A is enabled and begins counting or the +// capture logic is enabled based on the CFG +// register. +// DIS Timer A is disabled. +#define GPT_CTL_TAEN 0x00000001 +#define GPT_CTL_TAEN_BITN 0 +#define GPT_CTL_TAEN_M 0x00000001 +#define GPT_CTL_TAEN_S 0 +#define GPT_CTL_TAEN_EN 0x00000001 +#define GPT_CTL_TAEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_SYNC +// +//***************************************************************************** +// Field: [7:6] SYNC3 +// +// Synchronize GPT Timer 3. +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT3 is triggered +// TIMERB A timeout event for Timer B of GPT3 is triggered +// TIMERA A timeout event for Timer A of GPT3 is triggered +// NOSYNC No Sync. GPT3 is not affected. +#define GPT_SYNC_SYNC3_W 2 +#define GPT_SYNC_SYNC3_M 0x000000C0 +#define GPT_SYNC_SYNC3_S 6 +#define GPT_SYNC_SYNC3_BOTH 0x000000C0 +#define GPT_SYNC_SYNC3_TIMERB 0x00000080 +#define GPT_SYNC_SYNC3_TIMERA 0x00000040 +#define GPT_SYNC_SYNC3_NOSYNC 0x00000000 + +// Field: [5:4] SYNC2 +// +// Synchronize GPT Timer 2. +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT2 is triggered +// TIMERB A timeout event for Timer B of GPT2 is triggered +// TIMERA A timeout event for Timer A of GPT2 is triggered +// NOSYNC No Sync. GPT2 is not affected. +#define GPT_SYNC_SYNC2_W 2 +#define GPT_SYNC_SYNC2_M 0x00000030 +#define GPT_SYNC_SYNC2_S 4 +#define GPT_SYNC_SYNC2_BOTH 0x00000030 +#define GPT_SYNC_SYNC2_TIMERB 0x00000020 +#define GPT_SYNC_SYNC2_TIMERA 0x00000010 +#define GPT_SYNC_SYNC2_NOSYNC 0x00000000 + +// Field: [3:2] SYNC1 +// +// Synchronize GPT Timer 1 +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT1 is triggered +// TIMERB A timeout event for Timer B of GPT1 is triggered +// TIMERA A timeout event for Timer A of GPT1 is triggered +// NOSYNC No Sync. GPT1 is not affected. +#define GPT_SYNC_SYNC1_W 2 +#define GPT_SYNC_SYNC1_M 0x0000000C +#define GPT_SYNC_SYNC1_S 2 +#define GPT_SYNC_SYNC1_BOTH 0x0000000C +#define GPT_SYNC_SYNC1_TIMERB 0x00000008 +#define GPT_SYNC_SYNC1_TIMERA 0x00000004 +#define GPT_SYNC_SYNC1_NOSYNC 0x00000000 + +// Field: [1:0] SYNC0 +// +// Synchronize GPT Timer 0 +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT0 is triggered +// TIMERB A timeout event for Timer B of GPT0 is triggered +// TIMERA A timeout event for Timer A of GPT0 is triggered +// NOSYNC No Sync. GPT0 is not affected. +#define GPT_SYNC_SYNC0_W 2 +#define GPT_SYNC_SYNC0_M 0x00000003 +#define GPT_SYNC_SYNC0_S 0 +#define GPT_SYNC_SYNC0_BOTH 0x00000003 +#define GPT_SYNC_SYNC0_TIMERB 0x00000002 +#define GPT_SYNC_SYNC0_TIMERA 0x00000001 +#define GPT_SYNC_SYNC0_NOSYNC 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_IMR +// +//***************************************************************************** +// Field: [13] DMABIM +// +// Enabling this bit will make the RIS.DMABRIS interrupt propagate to +// MIS.DMABMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_DMABIM 0x00002000 +#define GPT_IMR_DMABIM_BITN 13 +#define GPT_IMR_DMABIM_M 0x00002000 +#define GPT_IMR_DMABIM_S 13 +#define GPT_IMR_DMABIM_EN 0x00002000 +#define GPT_IMR_DMABIM_DIS 0x00000000 + +// Field: [11] TBMIM +// +// Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TBMIM 0x00000800 +#define GPT_IMR_TBMIM_BITN 11 +#define GPT_IMR_TBMIM_M 0x00000800 +#define GPT_IMR_TBMIM_S 11 +#define GPT_IMR_TBMIM_EN 0x00000800 +#define GPT_IMR_TBMIM_DIS 0x00000000 + +// Field: [10] CBEIM +// +// Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CBEIM 0x00000400 +#define GPT_IMR_CBEIM_BITN 10 +#define GPT_IMR_CBEIM_M 0x00000400 +#define GPT_IMR_CBEIM_S 10 +#define GPT_IMR_CBEIM_EN 0x00000400 +#define GPT_IMR_CBEIM_DIS 0x00000000 + +// Field: [9] CBMIM +// +// Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CBMIM 0x00000200 +#define GPT_IMR_CBMIM_BITN 9 +#define GPT_IMR_CBMIM_M 0x00000200 +#define GPT_IMR_CBMIM_S 9 +#define GPT_IMR_CBMIM_EN 0x00000200 +#define GPT_IMR_CBMIM_DIS 0x00000000 + +// Field: [8] TBTOIM +// +// Enabling this bit will make the RIS.TBTORIS interrupt propagate to +// MIS.TBTOMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TBTOIM 0x00000100 +#define GPT_IMR_TBTOIM_BITN 8 +#define GPT_IMR_TBTOIM_M 0x00000100 +#define GPT_IMR_TBTOIM_S 8 +#define GPT_IMR_TBTOIM_EN 0x00000100 +#define GPT_IMR_TBTOIM_DIS 0x00000000 + +// Field: [5] DMAAIM +// +// Enabling this bit will make the RIS.DMAARIS interrupt propagate to +// MIS.DMAAMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_DMAAIM 0x00000020 +#define GPT_IMR_DMAAIM_BITN 5 +#define GPT_IMR_DMAAIM_M 0x00000020 +#define GPT_IMR_DMAAIM_S 5 +#define GPT_IMR_DMAAIM_EN 0x00000020 +#define GPT_IMR_DMAAIM_DIS 0x00000000 + +// Field: [4] TAMIM +// +// Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TAMIM 0x00000010 +#define GPT_IMR_TAMIM_BITN 4 +#define GPT_IMR_TAMIM_M 0x00000010 +#define GPT_IMR_TAMIM_S 4 +#define GPT_IMR_TAMIM_EN 0x00000010 +#define GPT_IMR_TAMIM_DIS 0x00000000 + +// Field: [2] CAEIM +// +// Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CAEIM 0x00000004 +#define GPT_IMR_CAEIM_BITN 2 +#define GPT_IMR_CAEIM_M 0x00000004 +#define GPT_IMR_CAEIM_S 2 +#define GPT_IMR_CAEIM_EN 0x00000004 +#define GPT_IMR_CAEIM_DIS 0x00000000 + +// Field: [1] CAMIM +// +// Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CAMIM 0x00000002 +#define GPT_IMR_CAMIM_BITN 1 +#define GPT_IMR_CAMIM_M 0x00000002 +#define GPT_IMR_CAMIM_S 1 +#define GPT_IMR_CAMIM_EN 0x00000002 +#define GPT_IMR_CAMIM_DIS 0x00000000 + +// Field: [0] TATOIM +// +// Enabling this bit will make the RIS.TATORIS interrupt propagate to +// MIS.TATOMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TATOIM 0x00000001 +#define GPT_IMR_TATOIM_BITN 0 +#define GPT_IMR_TATOIM_M 0x00000001 +#define GPT_IMR_TATOIM_S 0 +#define GPT_IMR_TATOIM_EN 0x00000001 +#define GPT_IMR_TATOIM_DIS 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_RIS +// +//***************************************************************************** +// Field: [13] DMABRIS +// +// GPT Timer B DMA Done Raw Interrupt Status +// +// 0: Transfer has not completed +// 1: Transfer has completed +#define GPT_RIS_DMABRIS 0x00002000 +#define GPT_RIS_DMABRIS_BITN 13 +#define GPT_RIS_DMABRIS_M 0x00002000 +#define GPT_RIS_DMABRIS_S 13 + +// Field: [11] TBMRIS +// +// GPT Timer B Match Raw Interrupt +// +// 0: The match value has not been reached +// 1: The match value is reached. +// +// TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR +// have been reached when configured in one-shot or periodic mode. +#define GPT_RIS_TBMRIS 0x00000800 +#define GPT_RIS_TBMRIS_BITN 11 +#define GPT_RIS_TBMRIS_M 0x00000800 +#define GPT_RIS_TBMRIS_S 11 + +// Field: [10] CBERIS +// +// GPT Timer B Capture Mode Event Raw Interrupt +// +// 0: The event has not occured. +// 1: The event has occured. +// +// This interrupt asserts when the subtimer is configured in Input Edge-Time +// mode +#define GPT_RIS_CBERIS 0x00000400 +#define GPT_RIS_CBERIS_BITN 10 +#define GPT_RIS_CBERIS_M 0x00000400 +#define GPT_RIS_CBERIS_S 10 + +// Field: [9] CBMRIS +// +// GPT Timer B Capture Mode Match Raw Interrupt +// +// 0: The capture mode match for Timer B has not occurred. +// 1: A capture mode match has occurred for Timer B. This interrupt +// asserts when the values in the TBR and TBPR +// match the values in the TBMATCHR and TBPMR +// when configured in Input Edge-Time mode. +// +// This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. +#define GPT_RIS_CBMRIS 0x00000200 +#define GPT_RIS_CBMRIS_BITN 9 +#define GPT_RIS_CBMRIS_M 0x00000200 +#define GPT_RIS_CBMRIS_S 9 + +// Field: [8] TBTORIS +// +// GPT Timer B Time-out Raw Interrupt +// +// 0: Timer B has not timed out +// 1: Timer B has timed out. +// +// This interrupt is asserted when a one-shot or periodic mode timer reaches +// its count limit. The count limit is 0 or the value loaded into TBILR, +// depending on the count direction. +#define GPT_RIS_TBTORIS 0x00000100 +#define GPT_RIS_TBTORIS_BITN 8 +#define GPT_RIS_TBTORIS_M 0x00000100 +#define GPT_RIS_TBTORIS_S 8 + +// Field: [5] DMAARIS +// +// GPT Timer A DMA Done Raw Interrupt Status +// +// 0: Transfer has not completed +// 1: Transfer has completed +#define GPT_RIS_DMAARIS 0x00000020 +#define GPT_RIS_DMAARIS_BITN 5 +#define GPT_RIS_DMAARIS_M 0x00000020 +#define GPT_RIS_DMAARIS_S 5 + +// Field: [4] TAMRIS +// +// GPT Timer A Match Raw Interrupt +// +// 0: The match value has not been reached +// 1: The match value is reached. +// +// TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR +// have been reached when configured in one-shot or periodic mode. +#define GPT_RIS_TAMRIS 0x00000010 +#define GPT_RIS_TAMRIS_BITN 4 +#define GPT_RIS_TAMRIS_M 0x00000010 +#define GPT_RIS_TAMRIS_S 4 + +// Field: [2] CAERIS +// +// GPT Timer A Capture Mode Event Raw Interrupt +// +// 0: The event has not occured. +// 1: The event has occured. +// +// This interrupt asserts when the subtimer is configured in Input Edge-Time +// mode +#define GPT_RIS_CAERIS 0x00000004 +#define GPT_RIS_CAERIS_BITN 2 +#define GPT_RIS_CAERIS_M 0x00000004 +#define GPT_RIS_CAERIS_S 2 + +// Field: [1] CAMRIS +// +// GPT Timer A Capture Mode Match Raw Interrupt +// +// 0: The capture mode match for Timer A has not occurred. +// 1: A capture mode match has occurred for Timer A. This interrupt +// asserts when the values in the TAR and TAPR +// match the values in the TAMATCHR and TAPMR +// when configured in Input Edge-Time mode. +// +// This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. +#define GPT_RIS_CAMRIS 0x00000002 +#define GPT_RIS_CAMRIS_BITN 1 +#define GPT_RIS_CAMRIS_M 0x00000002 +#define GPT_RIS_CAMRIS_S 1 + +// Field: [0] TATORIS +// +// GPT Timer A Time-out Raw Interrupt +// +// 0: Timer A has not timed out +// 1: Timer A has timed out. +// +// This interrupt is asserted when a one-shot or periodic mode timer reaches +// its count limit. The count limit is 0 or the value loaded into TAILR, +// depending on the count direction. +#define GPT_RIS_TATORIS 0x00000001 +#define GPT_RIS_TATORIS_BITN 0 +#define GPT_RIS_TATORIS_M 0x00000001 +#define GPT_RIS_TATORIS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_MIS +// +//***************************************************************************** +// Field: [13] DMABMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 +#define GPT_MIS_DMABMIS 0x00002000 +#define GPT_MIS_DMABMIS_BITN 13 +#define GPT_MIS_DMABMIS_M 0x00002000 +#define GPT_MIS_DMABMIS_S 13 + +// Field: [11] TBMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 +#define GPT_MIS_TBMMIS 0x00000800 +#define GPT_MIS_TBMMIS_BITN 11 +#define GPT_MIS_TBMMIS_M 0x00000800 +#define GPT_MIS_TBMMIS_S 11 + +// Field: [10] CBEMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 +#define GPT_MIS_CBEMIS 0x00000400 +#define GPT_MIS_CBEMIS_BITN 10 +#define GPT_MIS_CBEMIS_M 0x00000400 +#define GPT_MIS_CBEMIS_S 10 + +// Field: [9] CBMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 +#define GPT_MIS_CBMMIS 0x00000200 +#define GPT_MIS_CBMMIS_BITN 9 +#define GPT_MIS_CBMMIS_M 0x00000200 +#define GPT_MIS_CBMMIS_S 9 + +// Field: [8] TBTOMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 +#define GPT_MIS_TBTOMIS 0x00000100 +#define GPT_MIS_TBTOMIS_BITN 8 +#define GPT_MIS_TBTOMIS_M 0x00000100 +#define GPT_MIS_TBTOMIS_S 8 + +// Field: [5] DMAAMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 +#define GPT_MIS_DMAAMIS 0x00000020 +#define GPT_MIS_DMAAMIS_BITN 5 +#define GPT_MIS_DMAAMIS_M 0x00000020 +#define GPT_MIS_DMAAMIS_S 5 + +// Field: [4] TAMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 +#define GPT_MIS_TAMMIS 0x00000010 +#define GPT_MIS_TAMMIS_BITN 4 +#define GPT_MIS_TAMMIS_M 0x00000010 +#define GPT_MIS_TAMMIS_S 4 + +// Field: [2] CAEMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 +#define GPT_MIS_CAEMIS 0x00000004 +#define GPT_MIS_CAEMIS_BITN 2 +#define GPT_MIS_CAEMIS_M 0x00000004 +#define GPT_MIS_CAEMIS_S 2 + +// Field: [1] CAMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 +#define GPT_MIS_CAMMIS 0x00000002 +#define GPT_MIS_CAMMIS_BITN 1 +#define GPT_MIS_CAMMIS_M 0x00000002 +#define GPT_MIS_CAMMIS_S 1 + +// Field: [0] TATOMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 +#define GPT_MIS_TATOMIS 0x00000001 +#define GPT_MIS_TATOMIS_BITN 0 +#define GPT_MIS_TATOMIS_M 0x00000001 +#define GPT_MIS_TATOMIS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_ICLR +// +//***************************************************************************** +// Field: [13] DMABINT +// +// 0: Do nothing. +// 1: Clear RIS.DMABRIS and MIS.DMABMIS +#define GPT_ICLR_DMABINT 0x00002000 +#define GPT_ICLR_DMABINT_BITN 13 +#define GPT_ICLR_DMABINT_M 0x00002000 +#define GPT_ICLR_DMABINT_S 13 + +// Field: [11] TBMCINT +// +// 0: Do nothing. +// 1: Clear RIS.TBMRIS and MIS.TBMMIS +#define GPT_ICLR_TBMCINT 0x00000800 +#define GPT_ICLR_TBMCINT_BITN 11 +#define GPT_ICLR_TBMCINT_M 0x00000800 +#define GPT_ICLR_TBMCINT_S 11 + +// Field: [10] CBECINT +// +// 0: Do nothing. +// 1: Clear RIS.CBERIS and MIS.CBEMIS +#define GPT_ICLR_CBECINT 0x00000400 +#define GPT_ICLR_CBECINT_BITN 10 +#define GPT_ICLR_CBECINT_M 0x00000400 +#define GPT_ICLR_CBECINT_S 10 + +// Field: [9] CBMCINT +// +// 0: Do nothing. +// 1: Clear RIS.CBMRIS and MIS.CBMMIS +#define GPT_ICLR_CBMCINT 0x00000200 +#define GPT_ICLR_CBMCINT_BITN 9 +#define GPT_ICLR_CBMCINT_M 0x00000200 +#define GPT_ICLR_CBMCINT_S 9 + +// Field: [8] TBTOCINT +// +// 0: Do nothing. +// 1: Clear RIS.TBTORIS and MIS.TBTOMIS +#define GPT_ICLR_TBTOCINT 0x00000100 +#define GPT_ICLR_TBTOCINT_BITN 8 +#define GPT_ICLR_TBTOCINT_M 0x00000100 +#define GPT_ICLR_TBTOCINT_S 8 + +// Field: [5] DMAAINT +// +// 0: Do nothing. +// 1: Clear RIS.DMAARIS and MIS.DMAAMIS +#define GPT_ICLR_DMAAINT 0x00000020 +#define GPT_ICLR_DMAAINT_BITN 5 +#define GPT_ICLR_DMAAINT_M 0x00000020 +#define GPT_ICLR_DMAAINT_S 5 + +// Field: [4] TAMCINT +// +// 0: Do nothing. +// 1: Clear RIS.TAMRIS and MIS.TAMMIS +#define GPT_ICLR_TAMCINT 0x00000010 +#define GPT_ICLR_TAMCINT_BITN 4 +#define GPT_ICLR_TAMCINT_M 0x00000010 +#define GPT_ICLR_TAMCINT_S 4 + +// Field: [2] CAECINT +// +// 0: Do nothing. +// 1: Clear RIS.CAERIS and MIS.CAEMIS +#define GPT_ICLR_CAECINT 0x00000004 +#define GPT_ICLR_CAECINT_BITN 2 +#define GPT_ICLR_CAECINT_M 0x00000004 +#define GPT_ICLR_CAECINT_S 2 + +// Field: [1] CAMCINT +// +// 0: Do nothing. +// 1: Clear RIS.CAMRIS and MIS.CAMMIS +#define GPT_ICLR_CAMCINT 0x00000002 +#define GPT_ICLR_CAMCINT_BITN 1 +#define GPT_ICLR_CAMCINT_M 0x00000002 +#define GPT_ICLR_CAMCINT_S 1 + +// Field: [0] TATOCINT +// +// 0: Do nothing. +// 1: Clear RIS.TATORIS and MIS.TATOMIS +#define GPT_ICLR_TATOCINT 0x00000001 +#define GPT_ICLR_TATOCINT_BITN 0 +#define GPT_ICLR_TATOCINT_M 0x00000001 +#define GPT_ICLR_TATOCINT_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAILR +// +//***************************************************************************** +// Field: [31:0] TAILR +// +// GPT Timer A Interval Load Register +// +// Writing this field loads the counter for Timer A. A read returns the current +// value of TAILR. +#define GPT_TAILR_TAILR_W 32 +#define GPT_TAILR_TAILR_M 0xFFFFFFFF +#define GPT_TAILR_TAILR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBILR +// +//***************************************************************************** +// Field: [31:0] TBILR +// +// GPT Timer B Interval Load Register +// +// Writing this field loads the counter for Timer B. A read returns the current +// value of TBILR. +#define GPT_TBILR_TBILR_W 32 +#define GPT_TBILR_TBILR_M 0xFFFFFFFF +#define GPT_TBILR_TBILR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAMATCHR +// +//***************************************************************************** +// Field: [31:0] TAMATCHR +// +// GPT Timer A Match Register +#define GPT_TAMATCHR_TAMATCHR_W 32 +#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF +#define GPT_TAMATCHR_TAMATCHR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBMATCHR +// +//***************************************************************************** +// Field: [15:0] TBMATCHR +// +// GPT Timer B Match Register +#define GPT_TBMATCHR_TBMATCHR_W 16 +#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF +#define GPT_TBMATCHR_TBMATCHR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPR +// +//***************************************************************************** +// Field: [7:0] TAPSR +// +// Timer A Pre-scale. +// +// Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: +// +// 0: Prescaler ratio = 1 +// 1: Prescaler ratio = 2 +// 2: Prescaler ratio = 3 +// ... +// 255: Prescaler ratio = 256 +#define GPT_TAPR_TAPSR_W 8 +#define GPT_TAPR_TAPSR_M 0x000000FF +#define GPT_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPR +// +//***************************************************************************** +// Field: [7:0] TBPSR +// +// Timer B Pre-scale. +// +// Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: +// +// 0: Prescaler ratio = 1 +// 1: Prescaler ratio = 2 +// 2: Prescaler ratio = 3 +// ... +// 255: Prescaler ratio = 256 +#define GPT_TBPR_TBPSR_W 8 +#define GPT_TBPR_TBPSR_M 0x000000FF +#define GPT_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPMR +// +//***************************************************************************** +// Field: [7:0] TAPSMR +// +// GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. +#define GPT_TAPMR_TAPSMR_W 8 +#define GPT_TAPMR_TAPSMR_M 0x000000FF +#define GPT_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPMR +// +//***************************************************************************** +// Field: [7:0] TBPSMR +// +// GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits +// 23 to 16. +#define GPT_TBPMR_TBPSMR_W 8 +#define GPT_TBPMR_TBPSMR_M 0x000000FF +#define GPT_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAR +// +//***************************************************************************** +// Field: [31:0] TAR +// +// GPT Timer A Register +// +// Based on the value in the register field TAMR.TAILD, this register is +// updated with the value from TAILR register either on the next cycle or on +// the next timeout. +// +// A read returns the current value of the Timer A Count Register, in all cases +// except for Input Edge count and Timer modes. +// In the Input Edge Count Mode, this register contains the number of edges +// that have occurred. In the Input Edge Time mode, this register contains the +// time at which the last edge event took place. +#define GPT_TAR_TAR_W 32 +#define GPT_TAR_TAR_M 0xFFFFFFFF +#define GPT_TAR_TAR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBR +// +//***************************************************************************** +// Field: [31:0] TBR +// +// GPT Timer B Register +// +// Based on the value in the register field TBMR.TBILD, this register is +// updated with the value from TBILR register either on the next cycle or on +// the next timeout. +// +// A read returns the current value of the Timer B Count Register, in all cases +// except for Input Edge count and Timer modes. +// In the Input Edge Count Mode, this register contains the number of edges +// that have occurred. In the Input Edge Time mode, this register contains the +// time at which the last edge event took place. +#define GPT_TBR_TBR_W 32 +#define GPT_TBR_TBR_M 0xFFFFFFFF +#define GPT_TBR_TBR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAV +// +//***************************************************************************** +// Field: [31:0] TAV +// +// GPT Timer A Register +// A read returns the current, free-running value of Timer A in all modes. +// When written, the value written into this register is loaded into the +// TAR register on the next clock cycle. +// Note: In 16-bit mode, only the lower 16-bits of this +// register can be written with a new value. Writes to the prescaler bits have +// no effect +#define GPT_TAV_TAV_W 32 +#define GPT_TAV_TAV_M 0xFFFFFFFF +#define GPT_TAV_TAV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBV +// +//***************************************************************************** +// Field: [31:0] TBV +// +// GPT Timer B Register +// A read returns the current, free-running value of Timer B in all modes. +// When written, the value written into this register is loaded into the +// TBR register on the next clock cycle. +// Note: In 16-bit mode, only the lower 16-bits of this +// register can be written with a new value. Writes to the prescaler bits have +// no effect +#define GPT_TBV_TBV_W 32 +#define GPT_TBV_TBV_M 0xFFFFFFFF +#define GPT_TBV_TBV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPS +// +//***************************************************************************** +// Field: [7:0] PSS +// +// GPT Timer A Pre-scaler +#define GPT_TAPS_PSS_W 8 +#define GPT_TAPS_PSS_M 0x000000FF +#define GPT_TAPS_PSS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPS +// +//***************************************************************************** +// Field: [7:0] PSS +// +// GPT Timer B Pre-scaler +#define GPT_TBPS_PSS_W 8 +#define GPT_TBPS_PSS_M 0x000000FF +#define GPT_TBPS_PSS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPV +// +//***************************************************************************** +// Field: [7:0] PSV +// +// GPT Timer A Pre-scaler Value +#define GPT_TAPV_PSV_W 8 +#define GPT_TAPV_PSV_M 0x000000FF +#define GPT_TAPV_PSV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPV +// +//***************************************************************************** +// Field: [7:0] PSV +// +// GPT Timer B Pre-scaler Value +#define GPT_TBPV_PSV_W 8 +#define GPT_TBPV_PSV_M 0x000000FF +#define GPT_TBPV_PSV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_DMAEV +// +//***************************************************************************** +// Field: [11] TBMDMAEN +// +// GPT Timer B Match DMA Trigger Enable +#define GPT_DMAEV_TBMDMAEN 0x00000800 +#define GPT_DMAEV_TBMDMAEN_BITN 11 +#define GPT_DMAEV_TBMDMAEN_M 0x00000800 +#define GPT_DMAEV_TBMDMAEN_S 11 + +// Field: [10] CBEDMAEN +// +// GPT Timer B Capture Event DMA Trigger Enable +#define GPT_DMAEV_CBEDMAEN 0x00000400 +#define GPT_DMAEV_CBEDMAEN_BITN 10 +#define GPT_DMAEV_CBEDMAEN_M 0x00000400 +#define GPT_DMAEV_CBEDMAEN_S 10 + +// Field: [9] CBMDMAEN +// +// GPT Timer B Capture Match DMA Trigger Enable +#define GPT_DMAEV_CBMDMAEN 0x00000200 +#define GPT_DMAEV_CBMDMAEN_BITN 9 +#define GPT_DMAEV_CBMDMAEN_M 0x00000200 +#define GPT_DMAEV_CBMDMAEN_S 9 + +// Field: [8] TBTODMAEN +// +// GPT Timer B Time-Out DMA Trigger Enable +#define GPT_DMAEV_TBTODMAEN 0x00000100 +#define GPT_DMAEV_TBTODMAEN_BITN 8 +#define GPT_DMAEV_TBTODMAEN_M 0x00000100 +#define GPT_DMAEV_TBTODMAEN_S 8 + +// Field: [4] TAMDMAEN +// +// GPT Timer A Match DMA Trigger Enable +#define GPT_DMAEV_TAMDMAEN 0x00000010 +#define GPT_DMAEV_TAMDMAEN_BITN 4 +#define GPT_DMAEV_TAMDMAEN_M 0x00000010 +#define GPT_DMAEV_TAMDMAEN_S 4 + +// Field: [2] CAEDMAEN +// +// GPT Timer A Capture Event DMA Trigger Enable +#define GPT_DMAEV_CAEDMAEN 0x00000004 +#define GPT_DMAEV_CAEDMAEN_BITN 2 +#define GPT_DMAEV_CAEDMAEN_M 0x00000004 +#define GPT_DMAEV_CAEDMAEN_S 2 + +// Field: [1] CAMDMAEN +// +// GPT Timer A Capture Match DMA Trigger Enable +#define GPT_DMAEV_CAMDMAEN 0x00000002 +#define GPT_DMAEV_CAMDMAEN_BITN 1 +#define GPT_DMAEV_CAMDMAEN_M 0x00000002 +#define GPT_DMAEV_CAMDMAEN_S 1 + +// Field: [0] TATODMAEN +// +// GPT Timer A Time-Out DMA Trigger Enable +#define GPT_DMAEV_TATODMAEN 0x00000001 +#define GPT_DMAEV_TATODMAEN_BITN 0 +#define GPT_DMAEV_TATODMAEN_M 0x00000001 +#define GPT_DMAEV_TATODMAEN_S 0 + +//***************************************************************************** +// +// Register: GPT_O_VERSION +// +//***************************************************************************** +// Field: [31:0] VERSION +// +// Timer Revision. +#define GPT_VERSION_VERSION_W 32 +#define GPT_VERSION_VERSION_M 0xFFFFFFFF +#define GPT_VERSION_VERSION_S 0 + +//***************************************************************************** +// +// Register: GPT_O_ANDCCP +// +//***************************************************************************** +// Field: [0] CCP_AND_EN +// +// Enables AND operation of the CCP outputs for timers A and B. +// +// 0 : PWM outputs of Timer A and Timer B are the internal generated PWM +// signals of the respective timers. +// 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM +// signals and Timer B PWM ouput is Timer B PWM signal only. +#define GPT_ANDCCP_CCP_AND_EN 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_BITN 0 +#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_S 0 + + +#endif // __GPT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2c.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2c.h new file mode 100644 index 0000000..9d0d30e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2c.h @@ -0,0 +1,728 @@ +/****************************************************************************** +* Filename: hw_i2c_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// I2C component +// +//***************************************************************************** +// Slave Own Address +#define I2C_O_SOAR 0x00000000 + +// Slave Status +#define I2C_O_SSTAT 0x00000004 + +// Slave Control +#define I2C_O_SCTL 0x00000004 + +// Slave Data +#define I2C_O_SDR 0x00000008 + +// Slave Interrupt Mask +#define I2C_O_SIMR 0x0000000C + +// Slave Raw Interrupt Status +#define I2C_O_SRIS 0x00000010 + +// Slave Masked Interrupt Status +#define I2C_O_SMIS 0x00000014 + +// Slave Interrupt Clear +#define I2C_O_SICR 0x00000018 + +// Master Salve Address +#define I2C_O_MSA 0x00000800 + +// Master Status +#define I2C_O_MSTAT 0x00000804 + +// Master Control +#define I2C_O_MCTRL 0x00000804 + +// Master Data +#define I2C_O_MDR 0x00000808 + +// I2C Master Timer Period +#define I2C_O_MTPR 0x0000080C + +// Master Interrupt Mask +#define I2C_O_MIMR 0x00000810 + +// Master Raw Interrupt Status +#define I2C_O_MRIS 0x00000814 + +// Master Masked Interrupt Status +#define I2C_O_MMIS 0x00000818 + +// Master Interrupt Clear +#define I2C_O_MICR 0x0000081C + +// Master Configuration +#define I2C_O_MCR 0x00000820 + +//***************************************************************************** +// +// Register: I2C_O_SOAR +// +//***************************************************************************** +// Field: [6:0] OAR +// +// I2C slave own address +// This field specifies bits a6 through a0 of the slave address. +#define I2C_SOAR_OAR_W 7 +#define I2C_SOAR_OAR_M 0x0000007F +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SSTAT +// +//***************************************************************************** +// Field: [2] FBR +// +// First byte received +// +// 0: The first byte has not been received. +// 1: The first byte following the slave's own address has been received. +// +// This bit is only valid when the RREQ bit is set and is automatically cleared +// when data has been read from the SDR register. +// Note: This bit is not used for slave transmit operations. +#define I2C_SSTAT_FBR 0x00000004 +#define I2C_SSTAT_FBR_BITN 2 +#define I2C_SSTAT_FBR_M 0x00000004 +#define I2C_SSTAT_FBR_S 2 + +// Field: [1] TREQ +// +// Transmit request +// +// 0: No outstanding transmit request. +// 1: The I2C controller has been addressed as a slave transmitter and is using +// clock stretching to delay the master until data has been written to the SDR +// register. +#define I2C_SSTAT_TREQ 0x00000002 +#define I2C_SSTAT_TREQ_BITN 1 +#define I2C_SSTAT_TREQ_M 0x00000002 +#define I2C_SSTAT_TREQ_S 1 + +// Field: [0] RREQ +// +// Receive request +// +// 0: No outstanding receive data +// 1: The I2C controller has outstanding receive data from the I2C master and +// is using clock stretching to delay the master until data has been read from +// the SDR register. +#define I2C_SSTAT_RREQ 0x00000001 +#define I2C_SSTAT_RREQ_BITN 0 +#define I2C_SSTAT_RREQ_M 0x00000001 +#define I2C_SSTAT_RREQ_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SCTL +// +//***************************************************************************** +// Field: [0] DA +// +// Device active +// +// 0: Disables the I2C slave operation +// 1: Enables the I2C slave operation +#define I2C_SCTL_DA 0x00000001 +#define I2C_SCTL_DA_BITN 0 +#define I2C_SCTL_DA_M 0x00000001 +#define I2C_SCTL_DA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SDR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// Data for transfer +// This field contains the data for transfer during a slave receive or transmit +// operation. When written the register data is used as transmit data. When +// read, this register returns the last data received. +// Data is stored until next update, either by a system write for transmit or +// by an external master for receive. +#define I2C_SDR_DATA_W 8 +#define I2C_SDR_DATA_M 0x000000FF +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SIMR +// +//***************************************************************************** +// Field: [2] STOPIM +// +// Stop condition interrupt mask +// +// 0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt +// controller. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_SIMR_STOPIM 0x00000004 +#define I2C_SIMR_STOPIM_BITN 2 +#define I2C_SIMR_STOPIM_M 0x00000004 +#define I2C_SIMR_STOPIM_S 2 +#define I2C_SIMR_STOPIM_EN 0x00000004 +#define I2C_SIMR_STOPIM_DIS 0x00000000 + +// Field: [1] STARTIM +// +// Start condition interrupt mask +// +// 0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt +// controller. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_SIMR_STARTIM 0x00000002 +#define I2C_SIMR_STARTIM_BITN 1 +#define I2C_SIMR_STARTIM_M 0x00000002 +#define I2C_SIMR_STARTIM_S 1 +#define I2C_SIMR_STARTIM_EN 0x00000002 +#define I2C_SIMR_STARTIM_DIS 0x00000000 + +// Field: [0] DATAIM +// +// Data interrupt mask +// +// 0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt +// controller. +#define I2C_SIMR_DATAIM 0x00000001 +#define I2C_SIMR_DATAIM_BITN 0 +#define I2C_SIMR_DATAIM_M 0x00000001 +#define I2C_SIMR_DATAIM_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SRIS +// +//***************************************************************************** +// Field: [2] STOPRIS +// +// Stop condition raw interrupt status +// +// 0: No interrupt +// 1: A Stop condition interrupt is pending. +// +// This bit is cleared by writing a 1 to SICR.STOPIC. +#define I2C_SRIS_STOPRIS 0x00000004 +#define I2C_SRIS_STOPRIS_BITN 2 +#define I2C_SRIS_STOPRIS_M 0x00000004 +#define I2C_SRIS_STOPRIS_S 2 + +// Field: [1] STARTRIS +// +// Start condition raw interrupt status +// +// 0: No interrupt +// 1: A Start condition interrupt is pending. +// +// This bit is cleared by writing a 1 to SICR.STARTIC. +#define I2C_SRIS_STARTRIS 0x00000002 +#define I2C_SRIS_STARTRIS_BITN 1 +#define I2C_SRIS_STARTRIS_M 0x00000002 +#define I2C_SRIS_STARTRIS_S 1 + +// Field: [0] DATARIS +// +// Data raw interrupt status +// +// 0: No interrupt +// 1: A data received or data requested interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.DATAIC. +#define I2C_SRIS_DATARIS 0x00000001 +#define I2C_SRIS_DATARIS_BITN 0 +#define I2C_SRIS_DATARIS_M 0x00000001 +#define I2C_SRIS_DATARIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SMIS +// +//***************************************************************************** +// Field: [2] STOPMIS +// +// Stop condition masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked Stop condition interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.STOPIC. +#define I2C_SMIS_STOPMIS 0x00000004 +#define I2C_SMIS_STOPMIS_BITN 2 +#define I2C_SMIS_STOPMIS_M 0x00000004 +#define I2C_SMIS_STOPMIS_S 2 + +// Field: [1] STARTMIS +// +// Start condition masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked Start condition interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.STARTIC. +#define I2C_SMIS_STARTMIS 0x00000002 +#define I2C_SMIS_STARTMIS_BITN 1 +#define I2C_SMIS_STARTMIS_M 0x00000002 +#define I2C_SMIS_STARTMIS_S 1 + +// Field: [0] DATAMIS +// +// Data masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked data received or data requested interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.DATAIC. +#define I2C_SMIS_DATAMIS 0x00000001 +#define I2C_SMIS_DATAMIS_BITN 0 +#define I2C_SMIS_DATAMIS_M 0x00000001 +#define I2C_SMIS_DATAMIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SICR +// +//***************************************************************************** +// Field: [2] STOPIC +// +// Stop condition interrupt clear +// +// Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. +#define I2C_SICR_STOPIC 0x00000004 +#define I2C_SICR_STOPIC_BITN 2 +#define I2C_SICR_STOPIC_M 0x00000004 +#define I2C_SICR_STOPIC_S 2 + +// Field: [1] STARTIC +// +// Start condition interrupt clear +// +// Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. +#define I2C_SICR_STARTIC 0x00000002 +#define I2C_SICR_STARTIC_BITN 1 +#define I2C_SICR_STARTIC_M 0x00000002 +#define I2C_SICR_STARTIC_S 1 + +// Field: [0] DATAIC +// +// Data interrupt clear +// +// Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. +#define I2C_SICR_DATAIC 0x00000001 +#define I2C_SICR_DATAIC_BITN 0 +#define I2C_SICR_DATAIC_M 0x00000001 +#define I2C_SICR_DATAIC_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MSA +// +//***************************************************************************** +// Field: [7:1] SA +// +// I2C master slave address +// Defines which slave is addressed for the transaction in master mode +#define I2C_MSA_SA_W 7 +#define I2C_MSA_SA_M 0x000000FE +#define I2C_MSA_SA_S 1 + +// Field: [0] RS +// +// Receive or Send +// This bit-field specifies if the next operation is a receive (high) or a +// transmit/send (low) from the addressed slave SA. +// ENUMs: +// RX Receive data from slave +// TX Transmit/send data to slave +#define I2C_MSA_RS 0x00000001 +#define I2C_MSA_RS_BITN 0 +#define I2C_MSA_RS_M 0x00000001 +#define I2C_MSA_RS_S 0 +#define I2C_MSA_RS_RX 0x00000001 +#define I2C_MSA_RS_TX 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MSTAT +// +//***************************************************************************** +// Field: [6] BUSBSY +// +// Bus busy +// +// 0: The I2C bus is idle. +// 1: The I2C bus is busy. +// +// The bit changes based on the MCTRL.START and MCTRL.STOP conditions. +#define I2C_MSTAT_BUSBSY 0x00000040 +#define I2C_MSTAT_BUSBSY_BITN 6 +#define I2C_MSTAT_BUSBSY_M 0x00000040 +#define I2C_MSTAT_BUSBSY_S 6 + +// Field: [5] IDLE +// +// I2C idle +// +// 0: The I2C controller is not idle. +// 1: The I2C controller is idle. +#define I2C_MSTAT_IDLE 0x00000020 +#define I2C_MSTAT_IDLE_BITN 5 +#define I2C_MSTAT_IDLE_M 0x00000020 +#define I2C_MSTAT_IDLE_S 5 + +// Field: [4] ARBLST +// +// Arbitration lost +// +// 0: The I2C controller won arbitration. +// 1: The I2C controller lost arbitration. +#define I2C_MSTAT_ARBLST 0x00000010 +#define I2C_MSTAT_ARBLST_BITN 4 +#define I2C_MSTAT_ARBLST_M 0x00000010 +#define I2C_MSTAT_ARBLST_S 4 + +// Field: [3] DATACK_N +// +// Data Was Not Acknowledge +// +// 0: The transmitted data was acknowledged. +// 1: The transmitted data was not acknowledged. +#define I2C_MSTAT_DATACK_N 0x00000008 +#define I2C_MSTAT_DATACK_N_BITN 3 +#define I2C_MSTAT_DATACK_N_M 0x00000008 +#define I2C_MSTAT_DATACK_N_S 3 + +// Field: [2] ADRACK_N +// +// Address Was Not Acknowledge +// +// 0: The transmitted address was acknowledged. +// 1: The transmitted address was not acknowledged. +#define I2C_MSTAT_ADRACK_N 0x00000004 +#define I2C_MSTAT_ADRACK_N_BITN 2 +#define I2C_MSTAT_ADRACK_N_M 0x00000004 +#define I2C_MSTAT_ADRACK_N_S 2 + +// Field: [1] ERR +// +// Error +// +// 0: No error was detected on the last operation. +// 1: An error occurred on the last operation. +#define I2C_MSTAT_ERR 0x00000002 +#define I2C_MSTAT_ERR_BITN 1 +#define I2C_MSTAT_ERR_M 0x00000002 +#define I2C_MSTAT_ERR_S 1 + +// Field: [0] BUSY +// +// I2C busy +// +// 0: The controller is idle. +// 1: The controller is busy. +// +// When this bit-field is set, the other status bits are not valid. +// +// Note: The I2C controller requires four SYSBUS clock cycles to assert the +// BUSY status after I2C master operation has been initiated through MCTRL +// register. +// Hence after programming MCTRL register, application is requested to wait for +// four SYSBUS clock cycles before issuing a controller status inquiry through +// MSTAT register. +// Any prior inquiry would result in wrong status being reported. +#define I2C_MSTAT_BUSY 0x00000001 +#define I2C_MSTAT_BUSY_BITN 0 +#define I2C_MSTAT_BUSY_M 0x00000001 +#define I2C_MSTAT_BUSY_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MCTRL +// +//***************************************************************************** +// Field: [3] ACK +// +// Data acknowledge enable +// +// 0: The received data byte is not acknowledged automatically by the master. +// 1: The received data byte is acknowledged automatically by the master. +// +// This bit-field must be cleared when the I2C bus controller requires no +// further data to be transmitted from the slave transmitter. +// ENUMs: +// EN Enable acknowledge +// DIS Disable acknowledge +#define I2C_MCTRL_ACK 0x00000008 +#define I2C_MCTRL_ACK_BITN 3 +#define I2C_MCTRL_ACK_M 0x00000008 +#define I2C_MCTRL_ACK_S 3 +#define I2C_MCTRL_ACK_EN 0x00000008 +#define I2C_MCTRL_ACK_DIS 0x00000000 + +// Field: [2] STOP +// +// This bit-field determines if the cycle stops at the end of the data cycle or +// continues on to a repeated START condition. +// +// 0: The controller does not generate the Stop condition. +// 1: The controller generates the Stop condition. +// ENUMs: +// EN Enable STOP +// DIS Disable STOP +#define I2C_MCTRL_STOP 0x00000004 +#define I2C_MCTRL_STOP_BITN 2 +#define I2C_MCTRL_STOP_M 0x00000004 +#define I2C_MCTRL_STOP_S 2 +#define I2C_MCTRL_STOP_EN 0x00000004 +#define I2C_MCTRL_STOP_DIS 0x00000000 + +// Field: [1] START +// +// This bit-field generates the Start or Repeated Start condition. +// +// 0: The controller does not generate the Start condition. +// 1: The controller generates the Start condition. +// ENUMs: +// EN Enable START +// DIS Disable START +#define I2C_MCTRL_START 0x00000002 +#define I2C_MCTRL_START_BITN 1 +#define I2C_MCTRL_START_M 0x00000002 +#define I2C_MCTRL_START_S 1 +#define I2C_MCTRL_START_EN 0x00000002 +#define I2C_MCTRL_START_DIS 0x00000000 + +// Field: [0] RUN +// +// I2C master enable +// +// 0: The master is disabled. +// 1: The master is enabled to transmit or receive data. +// ENUMs: +// EN Enable Master +// DIS Disable Master +#define I2C_MCTRL_RUN 0x00000001 +#define I2C_MCTRL_RUN_BITN 0 +#define I2C_MCTRL_RUN_M 0x00000001 +#define I2C_MCTRL_RUN_S 0 +#define I2C_MCTRL_RUN_EN 0x00000001 +#define I2C_MCTRL_RUN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MDR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// When Read: Last RX Data is returned +// When Written: Data is transferred during TX transaction +#define I2C_MDR_DATA_W 8 +#define I2C_MDR_DATA_M 0x000000FF +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MTPR +// +//***************************************************************************** +// Field: [7] TPR_7 +// +// Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. +#define I2C_MTPR_TPR_7 0x00000080 +#define I2C_MTPR_TPR_7_BITN 7 +#define I2C_MTPR_TPR_7_M 0x00000080 +#define I2C_MTPR_TPR_7_S 7 + +// Field: [6:0] TPR +// +// SCL clock period +// This field specifies the period of the SCL clock. +// SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD +// where: +// SCL_PRD is the SCL line period (I2C clock). +// TPR is the timer period register value (range of 1 to 127) +// SCL_LP is the SCL low period (fixed at 6). +// SCL_HP is the SCL high period (fixed at 4). +// CLK_PRD is the system clock period in ns. +#define I2C_MTPR_TPR_W 7 +#define I2C_MTPR_TPR_M 0x0000007F +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MIMR +// +//***************************************************************************** +// Field: [0] IM +// +// Interrupt mask +// +// 0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The master interrupt is sent to the interrupt controller when the +// MRIS.RIS is set. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_MIMR_IM 0x00000001 +#define I2C_MIMR_IM_BITN 0 +#define I2C_MIMR_IM_M 0x00000001 +#define I2C_MIMR_IM_S 0 +#define I2C_MIMR_IM_EN 0x00000001 +#define I2C_MIMR_IM_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MRIS +// +//***************************************************************************** +// Field: [0] RIS +// +// Raw interrupt status +// +// 0: No interrupt +// 1: A master interrupt is pending. +// +// This bit is cleared by writing 1 to the MICR.IC bit . +#define I2C_MRIS_RIS 0x00000001 +#define I2C_MRIS_RIS_BITN 0 +#define I2C_MRIS_RIS_M 0x00000001 +#define I2C_MRIS_RIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MMIS +// +//***************************************************************************** +// Field: [0] MIS +// +// Masked interrupt status +// +// 0: An interrupt has not occurred or is masked. +// 1: A master interrupt is pending. +// +// This bit is cleared by writing 1 to the MICR.IC bit . +#define I2C_MMIS_MIS 0x00000001 +#define I2C_MMIS_MIS_BITN 0 +#define I2C_MMIS_MIS_M 0x00000001 +#define I2C_MMIS_MIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MICR +// +//***************************************************************************** +// Field: [0] IC +// +// Interrupt clear +// Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . +// +// Reading this register returns no meaningful data. +#define I2C_MICR_IC 0x00000001 +#define I2C_MICR_IC_BITN 0 +#define I2C_MICR_IC_M 0x00000001 +#define I2C_MICR_IC_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MCR +// +//***************************************************************************** +// Field: [5] SFE +// +// I2C slave function enable +// ENUMs: +// EN Slave mode is enabled. +// DIS Slave mode is disabled. +#define I2C_MCR_SFE 0x00000020 +#define I2C_MCR_SFE_BITN 5 +#define I2C_MCR_SFE_M 0x00000020 +#define I2C_MCR_SFE_S 5 +#define I2C_MCR_SFE_EN 0x00000020 +#define I2C_MCR_SFE_DIS 0x00000000 + +// Field: [4] MFE +// +// I2C master function enable +// ENUMs: +// EN Master mode is enabled. +// DIS Master mode is disabled. +#define I2C_MCR_MFE 0x00000010 +#define I2C_MCR_MFE_BITN 4 +#define I2C_MCR_MFE_M 0x00000010 +#define I2C_MCR_MFE_S 4 +#define I2C_MCR_MFE_EN 0x00000010 +#define I2C_MCR_MFE_DIS 0x00000000 + +// Field: [0] LPBK +// +// I2C loopback +// +// 0: Normal operation +// 1: Loopback operation (test mode) +// ENUMs: +// EN Enable Test Mode +// DIS Disable Test Mode +#define I2C_MCR_LPBK 0x00000001 +#define I2C_MCR_LPBK_BITN 0 +#define I2C_MCR_LPBK_M 0x00000001 +#define I2C_MCR_LPBK_S 0 +#define I2C_MCR_LPBK_EN 0x00000001 +#define I2C_MCR_LPBK_DIS 0x00000000 + + +#endif // __I2C__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2s.h new file mode 100644 index 0000000..ee850c7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2s.h @@ -0,0 +1,967 @@ +/****************************************************************************** +* Filename: hw_i2s_h +* Revised: 2017-11-02 10:21:28 +0100 (Thu, 02 Nov 2017) +* Revision: 50141 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_I2S_H__ +#define __HW_I2S_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// I2S component +// +//***************************************************************************** +// WCLK Source Selection +#define I2S_O_AIFWCLKSRC 0x00000000 + +// DMA Buffer Size Configuration +#define I2S_O_AIFDMACFG 0x00000004 + +// Pin Direction +#define I2S_O_AIFDIRCFG 0x00000008 + +// Serial Interface Format Configuration +#define I2S_O_AIFFMTCFG 0x0000000C + +// Word Selection Bit Mask for Pin 0 +#define I2S_O_AIFWMASK0 0x00000010 + +// Word Selection Bit Mask for Pin 1 +#define I2S_O_AIFWMASK1 0x00000014 + +// Audio Interface PWM Debug Value +#define I2S_O_AIFPWMVALUE 0x0000001C + +// DMA Input Buffer Next Pointer +#define I2S_O_AIFINPTRNEXT 0x00000020 + +// DMA Input Buffer Current Pointer +#define I2S_O_AIFINPTR 0x00000024 + +// DMA Output Buffer Next Pointer +#define I2S_O_AIFOUTPTRNEXT 0x00000028 + +// DMA Output Buffer Current Pointer +#define I2S_O_AIFOUTPTR 0x0000002C + +// Samplestamp Generator Control Register +#define I2S_O_STMPCTL 0x00000034 + +// Captured XOSC Counter Value, Capture Channel 0 +#define I2S_O_STMPXCNTCAPT0 0x00000038 + +// XOSC Period Value +#define I2S_O_STMPXPER 0x0000003C + +// Captured WCLK Counter Value, Capture Channel 0 +#define I2S_O_STMPWCNTCAPT0 0x00000040 + +// WCLK Counter Period Value +#define I2S_O_STMPWPER 0x00000044 + +// WCLK Counter Trigger Value for Input Pins +#define I2S_O_STMPINTRIG 0x00000048 + +// WCLK Counter Trigger Value for Output Pins +#define I2S_O_STMPOUTTRIG 0x0000004C + +// WCLK Counter Set Operation +#define I2S_O_STMPWSET 0x00000050 + +// WCLK Counter Add Operation +#define I2S_O_STMPWADD 0x00000054 + +// XOSC Minimum Period Value +#define I2S_O_STMPXPERMIN 0x00000058 + +// Current Value of WCNT +#define I2S_O_STMPWCNT 0x0000005C + +// Current Value of XCNT +#define I2S_O_STMPXCNT 0x00000060 + +// Internal +#define I2S_O_STMPXCNTCAPT1 0x00000064 + +// Internal +#define I2S_O_STMPWCNTCAPT1 0x00000068 + +// Interrupt Mask Register +#define I2S_O_IRQMASK 0x00000070 + +// Raw Interrupt Status Register +#define I2S_O_IRQFLAGS 0x00000074 + +// Interrupt Set Register +#define I2S_O_IRQSET 0x00000078 + +// Interrupt Clear Register +#define I2S_O_IRQCLR 0x0000007C + +//***************************************************************************** +// +// Register: I2S_O_AIFWCLKSRC +// +//***************************************************************************** +// Field: [2] WCLK_INV +// +// Inverts WCLK source (pad or internal) when set. +// +// 0: Not inverted +// 1: Inverted +#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 +#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_S 2 + +// Field: [1:0] WCLK_SRC +// +// Selects WCLK source for AIF (should be the same as the BCLK source). The +// BCLK source is defined in the PRCM:I2SBCLKSEL.SRC +// ENUMs: +// RESERVED Not supported. Will give same WCLK as 'NONE' +// ('00') +// INT Internal WCLK generator, from module PRCM +// EXT External WCLK generator, from pad +// NONE None ('0') +#define I2S_AIFWCLKSRC_WCLK_SRC_W 2 +#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_S 0 +#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 +#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 +#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 + +//***************************************************************************** +// +// Register: I2S_O_AIFDMACFG +// +//***************************************************************************** +// Field: [7:0] END_FRAME_IDX +// +// Defines the length of the DMA buffer. Writing a non-zero value to this +// register field enables and initializes AIF. Note that before doing so, all +// other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must +// have been loaded. +#define I2S_AIFDMACFG_END_FRAME_IDX_W 8 +#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF +#define I2S_AIFDMACFG_END_FRAME_IDX_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFDIRCFG +// +//***************************************************************************** +// Field: [5:4] AD1 +// +// Configures the AD1 audio data pin usage: +// +// 0x3: Reserved +// ENUMs: +// OUT Output mode +// IN Input mode +// DIS Not in use (disabled) +#define I2S_AIFDIRCFG_AD1_W 2 +#define I2S_AIFDIRCFG_AD1_M 0x00000030 +#define I2S_AIFDIRCFG_AD1_S 4 +#define I2S_AIFDIRCFG_AD1_OUT 0x00000020 +#define I2S_AIFDIRCFG_AD1_IN 0x00000010 +#define I2S_AIFDIRCFG_AD1_DIS 0x00000000 + +// Field: [1:0] AD0 +// +// Configures the AD0 audio data pin usage: +// +// 0x3: Reserved +// ENUMs: +// OUT Output mode +// IN Input mode +// DIS Not in use (disabled) +#define I2S_AIFDIRCFG_AD0_W 2 +#define I2S_AIFDIRCFG_AD0_M 0x00000003 +#define I2S_AIFDIRCFG_AD0_S 0 +#define I2S_AIFDIRCFG_AD0_OUT 0x00000002 +#define I2S_AIFDIRCFG_AD0_IN 0x00000001 +#define I2S_AIFDIRCFG_AD0_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2S_O_AIFFMTCFG +// +//***************************************************************************** +// Field: [15:8] DATA_DELAY +// +// The number of BCLK periods between a WCLK edge and MSB of the first word in +// a phase: +// +// 0x00: LJF and DSP format +// 0x01: I2S and DSP format +// 0x02: RJF format +// ... +// 0xFF: RJF format +// +// Note: When 0, MSB of the next word will be output in the idle period between +// LSB of the previous word and the start of the next word. Otherwise logical 0 +// will be output until the data delay has expired. +#define I2S_AIFFMTCFG_DATA_DELAY_W 8 +#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 +#define I2S_AIFFMTCFG_DATA_DELAY_S 8 + +// Field: [7] MEM_LEN_24 +// +// The size of each word stored to or loaded from memory: +// ENUMs: +// 24BIT 24-bit (one 8 bit and one 16 bit locked access per +// sample) +// 16BIT 16-bit (one 16 bit access per sample) +#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_S 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 + +// Field: [6] SMPL_EDGE +// +// On the serial audio interface, data (and wclk) is sampled and clocked out on +// opposite edges of BCLK. +// ENUMs: +// POS Data is sampled on the positive edge and clocked +// out on the negative edge. +// NEG Data is sampled on the negative edge and clocked +// out on the positive edge. +#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_S 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 + +// Field: [5] DUAL_PHASE +// +// Selects dual- or single-phase format. +// +// 0: Single-phase: DSP format +// 1: Dual-phase: I2S, LJF and RJF formats +#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 +#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_S 5 + +// Field: [4:0] WORD_LEN +// +// Number of bits per word (8-24): +// In single-phase format, this is the exact number of bits per word. +// In dual-phase format, this is the maximum number of bits per word. +// +// Values below 8 and above 24 give undefined behavior. Data written to memory +// is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that +// differ from this alignment will either be truncated or zero padded. +#define I2S_AIFFMTCFG_WORD_LEN_W 5 +#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F +#define I2S_AIFFMTCFG_WORD_LEN_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFWMASK0 +// +//***************************************************************************** +// Field: [7:0] MASK +// +// Bit-mask indicating valid channels in a frame on AD0. +// +// In single-phase mode, each bit represents one channel, starting with LSB for +// the first word in the frame. A frame can contain up to 8 channels. Channels +// that are not included in the mask will not be sampled and stored in memory, +// and clocked out as '0'. +// +// In dual-phase mode, only the two LSBs are considered. For a stereo +// configuration, set both bits. For a mono configuration, set bit 0 only. In +// mono mode, only channel 0 will be sampled and stored to memory, and channel +// 0 will be repeated when clocked out. +// +// In mono mode, only channel 0 will be sampled and stored to memory, and +// channel 0 will be repeated in the second phase when clocked out. +// +// If all bits are zero, no input words will be stored to memory, and the +// output data lines will be constant '0'. This can be utilized when PWM debug +// output is desired without any actively used output pins. +#define I2S_AIFWMASK0_MASK_W 8 +#define I2S_AIFWMASK0_MASK_M 0x000000FF +#define I2S_AIFWMASK0_MASK_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFWMASK1 +// +//***************************************************************************** +// Field: [7:0] MASK +// +// Bit-mask indicating valid channels in a frame on AD1. +// +// In single-phase mode, each bit represents one channel, starting with LSB for +// the first word in the frame. A frame can contain up to 8 channels. Channels +// that are not included in the mask will not be sampled and stored in memory, +// and clocked out as '0'. +// +// In dual-phase mode, only the two LSBs are considered. For a stereo +// configuration, set both bits. For a mono configuration, set bit 0 only. In +// mono mode, only channel 0 will be sampled and stored to memory, and channel +// 0 will be repeated when clocked out. +// +// In mono mode, only channel 0 will be sampled and stored to memory, and +// channel 0 will be repeated in the second phase when clocked out. +// +// If all bits are zero, no input words will be stored to memory, and the +// output data lines will be constant '0'. This can be utilized when PWM debug +// output is desired without any actively used output pins. +#define I2S_AIFWMASK1_MASK_W 8 +#define I2S_AIFWMASK1_MASK_M 0x000000FF +#define I2S_AIFWMASK1_MASK_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFPWMVALUE +// +//***************************************************************************** +// Field: [15:0] PULSE_WIDTH +// +// The value written to this register determines the width of the active high +// PWM pulse (pwm_debug), which starts together with MSB of the first output +// word in a DMA buffer: +// +// 0x0000: Constant low +// 0x0001: Width of the pulse (number of BCLK cycles, here 1). +// ... +// 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). +// 0xFFFF: Constant high +#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 +#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF +#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFINPTRNEXT +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Pointer to the first byte in the next DMA input buffer. +// +// The read value equals the last written value until the currently used DMA +// input buffer is completed, and then becomes null when the last written value +// is transferred to the DMA controller to start on the next buffer. This event +// is signalized by IRQFLAGS.AIF_DMA_IN. +// +// At startup, the value must be written once before and once after configuring +// the DMA buffer size in AIFDMACFG. +// +// The next pointer must be written to this register while the DMA function +// uses the previously written pointer. If not written in time, +// IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. +#define I2S_AIFINPTRNEXT_PTR_W 32 +#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTRNEXT_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFINPTR +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Value of the DMA input buffer pointer currently used by the DMA controller. +// Incremented by 1 (byte) or 2 (word) for each AHB access. +#define I2S_AIFINPTR_PTR_W 32 +#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTR_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFOUTPTRNEXT +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Pointer to the first byte in the next DMA output buffer. +// +// The read value equals the last written value until the currently used DMA +// output buffer is completed, and then becomes null when the last written +// value is transferred to the DMA controller to start on the next buffer. This +// event is signalized by IRQFLAGS.AIF_DMA_OUT. +// +// At startup, the value must be written once before and once after configuring +// the DMA buffer size in AIFDMACFG. At this time, the first two samples will +// be fetched from memory. +// +// The next pointer must be written to this register while the DMA function +// uses the previously written pointer. If not written in time, +// IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. +#define I2S_AIFOUTPTRNEXT_PTR_W 32 +#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTRNEXT_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFOUTPTR +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Value of the DMA output buffer pointer currently used by the DMA controller +// Incremented by 1 (byte) or 2 (word) for each AHB access. +#define I2S_AIFOUTPTR_PTR_W 32 +#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTR_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPCTL +// +//***************************************************************************** +// Field: [2] OUT_RDY +// +// Low until the output pins are ready to be started by the samplestamp +// generator. When started (that is STMPOUTTRIG equals the WCLK counter) the +// bit goes back low. +#define I2S_STMPCTL_OUT_RDY 0x00000004 +#define I2S_STMPCTL_OUT_RDY_BITN 2 +#define I2S_STMPCTL_OUT_RDY_M 0x00000004 +#define I2S_STMPCTL_OUT_RDY_S 2 + +// Field: [1] IN_RDY +// +// Low until the input pins are ready to be started by the samplestamp +// generator. When started (that is STMPINTRIG equals the WCLK counter) the bit +// goes back low. +#define I2S_STMPCTL_IN_RDY 0x00000002 +#define I2S_STMPCTL_IN_RDY_BITN 1 +#define I2S_STMPCTL_IN_RDY_M 0x00000002 +#define I2S_STMPCTL_IN_RDY_S 1 + +// Field: [0] STMP_EN +// +// Enables the samplestamp generator. The samplestamp generator must only be +// enabled after it has been properly configured. +// When cleared, all samplestamp generator counters and capture values are +// cleared. +#define I2S_STMPCTL_STMP_EN 0x00000001 +#define I2S_STMPCTL_STMP_EN_BITN 0 +#define I2S_STMPCTL_STMP_EN_M 0x00000001 +#define I2S_STMPCTL_STMP_EN_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNTCAPT0 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an +// event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for +// channel 0). This number corresponds to the number of 24 MHz clock cycles +// since the last positive edge of the selected WCLK. +// The value is cleared when STMPCTL.STMP_EN = 0. +// Note: Due to buffering and synchronization, WCLK is delayed by a small +// number of BCLK periods and clk periods. +// Note: When calculating the fractional part of the sample stamp, STMPXPER may +// be less than this bit field. +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXPER +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// The number of 24 MHz clock cycles in the previous WCLK period (that is - +// the next value of the XOSC counter at the positive WCLK edge, had it not +// been reset to 0). +// The value is cleared when STMPCTL.STMP_EN = 0. +#define I2S_STMPXPER_VALUE_W 16 +#define I2S_STMPXPER_VALUE_M 0x0000FFFF +#define I2S_STMPXPER_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNTCAPT0 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an +// event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel +// 0). This number corresponds to the number of positive WCLK edges since the +// samplestamp generator was enabled (not taking modification through +// STMPWADD/STMPWSET into account). +// The value is cleared when STMPCTL.STMP_EN = 0. +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWPER +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Used to define when STMPWCNT is to be reset so number of WCLK edges are +// found for the size of the sample buffer. This is thus a modulo value for the +// WCLK counter. This number must correspond to the size of the sample buffer +// used by the system (that is the index of the last sample plus 1). +#define I2S_STMPWPER_VALUE_W 16 +#define I2S_STMPWPER_VALUE_M 0x0000FFFF +#define I2S_STMPWPER_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPINTRIG +// +//***************************************************************************** +// Field: [15:0] IN_START_WCNT +// +// Compare value used to start the incoming audio streams. +// This bit field shall equal the WCLK counter value during the WCLK period in +// which the first input word(s) are sampled and stored to memory (that is the +// sample at the start of the very first DMA input buffer). +// +// The value of this register takes effect when the following conditions are +// met: +// - One or more pins are configured as inputs in AIFDIRCFG. +// - AIFDMACFG has been configured for the correct buffer size, and at least 32 +// BCLK cycle ticks have happened. +// +// Note: To avoid false triggers, this bit field should be set higher than +// STMPWPER.VALUE. +#define I2S_STMPINTRIG_IN_START_WCNT_W 16 +#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF +#define I2S_STMPINTRIG_IN_START_WCNT_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPOUTTRIG +// +//***************************************************************************** +// Field: [15:0] OUT_START_WCNT +// +// Compare value used to start the outgoing audio streams. +// +// This bit field must equal the WCLK counter value during the WCLK period in +// which the first output word(s) read from memory are clocked out (that is the +// sample at the start of the very first DMA output buffer). +// +// The value of this register takes effect when the following conditions are +// met: +// - One or more pins are configured as outputs in AIFDIRCFG. +// - AIFDMACFG has been configured for the correct buffer size, and 32 BCLK +// cycle ticks have happened. +// - 2 samples have been preloaded from memory (examine the AIFOUTPTR register +// if necessary). +// Note: The memory read access is only performed when required, that is +// channels 0/1 must be selected in AIFWMASK0/AIFWMASK1. +// +// Note: To avoid false triggers, this bit field should be set higher than +// STMPWPER.VALUE. +#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 +#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF +#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWSET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// WCLK counter modification: Sets the running WCLK counter equal to the +// written value. +#define I2S_STMPWSET_VALUE_W 16 +#define I2S_STMPWSET_VALUE_M 0x0000FFFF +#define I2S_STMPWSET_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWADD +// +//***************************************************************************** +// Field: [15:0] VALUE_INC +// +// WCLK counter modification: Adds the written value to the running WCLK +// counter. If a positive edge of WCLK occurs at the same time as the +// operation, this will be taken into account. +// To add a negative value, write "STMPWPER.VALUE - value". +// +#define I2S_STMPWADD_VALUE_INC_W 16 +#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF +#define I2S_STMPWADD_VALUE_INC_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXPERMIN +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Each time STMPXPER is updated, the value is also loaded into this register, +// provided that the value is smaller than the current value in this register. +// When written, the register is reset to 0xFFFF (65535), regardless of the +// value written. +// The minimum value can be used to detect extra WCLK pulses (this registers +// value will be significantly smaller than STMPXPER.VALUE). +#define I2S_STMPXPERMIN_VALUE_W 16 +#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF +#define I2S_STMPXPERMIN_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNT +// +//***************************************************************************** +// Field: [15:0] CURR_VALUE +// +// Current value of the WCLK counter +#define I2S_STMPWCNT_CURR_VALUE_W 16 +#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPWCNT_CURR_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNT +// +//***************************************************************************** +// Field: [15:0] CURR_VALUE +// +// Current value of the XOSC counter, latched when reading STMPWCNT. +#define I2S_STMPXCNT_CURR_VALUE_W 16 +#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPXCNT_CURR_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNTCAPT1 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// Internal. Only to be used through TI provided API. +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNTCAPT1 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// Internal. Only to be used through TI provided API. +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQMASK +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// IRQFLAGS.AIF_DMA_IN interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_AIF_DMA_IN 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_BITN 5 +#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// IRQFLAGS.AIF_DMA_OUT interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 +#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// IRQFLAGS.WCLK_TIMEOUT interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// IRQFLAGS.BUS_ERR interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_BUS_ERR 0x00000004 +#define I2S_IRQMASK_BUS_ERR_BITN 2 +#define I2S_IRQMASK_BUS_ERR_M 0x00000004 +#define I2S_IRQMASK_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// IRQFLAGS.WCLK_ERR interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_WCLK_ERR 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_BITN 1 +#define I2S_IRQMASK_WCLK_ERR_M 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// IRQFLAGS.PTR_ERR interrupt mask. +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_PTR_ERR 0x00000001 +#define I2S_IRQMASK_PTR_ERR_BITN 0 +#define I2S_IRQMASK_PTR_ERR_M 0x00000001 +#define I2S_IRQMASK_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQFLAGS +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// Set when condition for this bit field event occurs (auto cleared when input +// pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register +// for details. +#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 +#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// Set when condition for this bit field event occurs (auto cleared when output +// pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT +// register for details +#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 +#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// Set when the sample stamp generator does not detect a positive WCLK edge for +// 65535 clk periods. This signalizes that the internal or external BCLK and +// WCLK generator source has been disabled. +// +// The bit is sticky and may only be cleared by software (by writing '1' to +// IRQCLR.WCLK_TIMEOUT). +#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// Set when a DMA operation is not completed in time (that is audio output +// buffer underflow, or audio input buffer overflow). +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.BUS_ERR). +// +// Note that DMA initiated transactions to illegal addresses will not trigger +// an interrupt. The response to such transactions is undefined. +#define I2S_IRQFLAGS_BUS_ERR 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_BITN 2 +#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// Set when: +// - An unexpected WCLK edge occurs during the data delay period of a phase. +// Note unexpected WCLK edges during the word and idle periods of the phase are +// not detected. +// - In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles +// apart. +// - In single-phase mode, when a WCLK pulse occurs before the last channel. +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.WCLK_ERR). +#define I2S_IRQFLAGS_WCLK_ERR 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_BITN 1 +#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next +// block address in time. +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.PTR_ERR). +#define I2S_IRQFLAGS_PTR_ERR 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_BITN 0 +#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQSET +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria +// was given at the same time, in which the set will be ignored) +#define I2S_IRQSET_AIF_DMA_IN 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_BITN 5 +#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria +// was given at the same time, in which the set will be ignored) +#define I2S_IRQSET_AIF_DMA_OUT 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_BITN 4 +#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT +#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// 1: Sets the interrupt of IRQFLAGS.BUS_ERR +#define I2S_IRQSET_BUS_ERR 0x00000004 +#define I2S_IRQSET_BUS_ERR_BITN 2 +#define I2S_IRQSET_BUS_ERR_M 0x00000004 +#define I2S_IRQSET_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// 1: Sets the interrupt of IRQFLAGS.WCLK_ERR +#define I2S_IRQSET_WCLK_ERR 0x00000002 +#define I2S_IRQSET_WCLK_ERR_BITN 1 +#define I2S_IRQSET_WCLK_ERR_M 0x00000002 +#define I2S_IRQSET_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// 1: Sets the interrupt of IRQFLAGS.PTR_ERR +#define I2S_IRQSET_PTR_ERR 0x00000001 +#define I2S_IRQSET_PTR_ERR_BITN 0 +#define I2S_IRQSET_PTR_ERR_M 0x00000001 +#define I2S_IRQSET_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQCLR +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_AIF_DMA_IN 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_BITN 5 +#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 +#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given +// at the same time in which the clear will be ignored) +#define I2S_IRQCLR_BUS_ERR 0x00000004 +#define I2S_IRQCLR_BUS_ERR_BITN 2 +#define I2S_IRQCLR_BUS_ERR_M 0x00000004 +#define I2S_IRQCLR_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_WCLK_ERR 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_BITN 1 +#define I2S_IRQCLR_WCLK_ERR_M 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given +// at the same time in which the clear will be ignored) +#define I2S_IRQCLR_PTR_ERR 0x00000001 +#define I2S_IRQCLR_PTR_ERR_BITN 0 +#define I2S_IRQCLR_PTR_ERR_M 0x00000001 +#define I2S_IRQCLR_PTR_ERR_S 0 + + +#endif // __I2S__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ints.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ints.h new file mode 100644 index 0000000..3d38283 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ints.h @@ -0,0 +1,113 @@ +/****************************************************************************** +* Filename: hw_ints_h +* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) +* Revision: 48904 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_NMI_FAULT 2 // NMI Fault +#define INT_HARD_FAULT 3 // Hard Fault +#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage) + // Fault +#define INT_BUS_FAULT 5 // Bus Fault +#define INT_USAGE_FAULT 6 // Usage Fault +#define INT_SVCALL 11 // Supervisor Call (SVCall) +#define INT_DEBUG 12 // Debug Monitor +#define INT_PENDSV 14 // Pending Service Call (PendSV) +#define INT_SYSTICK 15 // SysTick Interrupt from the + // System Timer in NVIC. +#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC +#define INT_I2C_IRQ 17 // Interrupt event from I2C +#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE + // Generated events +#define INT_AON_RTC_COMB 20 // Event from AON_RTC +#define INT_UART0_COMB 21 // UART0 combined interrupt +#define INT_AUX_SWEV0 22 // AUX software event 0 +#define INT_SSI0_COMB 23 // SSI0 combined interrupt +#define INT_SSI1_COMB 24 // SSI1 combined interrupt +#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE + // Generated events +#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt +#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command + // Acknowledgement Interrupt +#define INT_I2S_IRQ 28 // Interrupt event from I2S +#define INT_AUX_SWEV1 29 // AUX software event 1 +#define INT_WDT_IRQ 30 // Watchdog interrupt event +#define INT_GPT0A 31 // GPT0A interrupt event +#define INT_GPT0B 32 // GPT0B interrupt event +#define INT_GPT1A 33 // GPT1A interrupt event +#define INT_GPT1B 34 // GPT1B interrupt event +#define INT_GPT2A 35 // GPT2A interrupt event +#define INT_GPT2B 36 // GPT2B interrupt event +#define INT_GPT3A 37 // GPT3A interrupt event +#define INT_GPT3B 38 // GPT3B interrupt event +#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt + // event +#define INT_DMA_DONE_COMB 40 // Combined DMA done +#define INT_DMA_ERR 41 // DMA bus error +#define INT_FLASH 42 // FLASH controller error event +#define INT_SWEV0 43 // Software event 0 +#define INT_AUX_COMB 44 // AUX combined event +#define INT_AON_PROG0 45 // AON programmable event 0 +#define INT_PROG0 46 // Programmable Interrupt 0 +#define INT_AUX_COMPA 47 // AUX Compare A event +#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event +#define INT_TRNG_IRQ 49 // TRNG Interrupt event + +//***************************************************************************** +// +// The following are defines for number of interrupts and priority levels. +// +//***************************************************************************** +#define NUM_INTERRUPTS 50 // Number of interrupts +#define NUM_PRIORITY_BITS 3 // Number of Priority bits +#define NUM_PRIORITY 8 // Number of priority levels + + +//***************************************************************************** +// +// Aliases for backwards compatibility with Sensor Controller Studio 1.1.0 +// +//***************************************************************************** + +#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0 +#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1 + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ioc.h new file mode 100644 index 0000000..16a800a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ioc.h @@ -0,0 +1,9839 @@ +/****************************************************************************** +* Filename: hw_ioc_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_IOC_H__ +#define __HW_IOC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// IOC component +// +//***************************************************************************** +// Configuration of DIO0 +#define IOC_O_IOCFG0 0x00000000 + +// Configuration of DIO1 +#define IOC_O_IOCFG1 0x00000004 + +// Configuration of DIO2 +#define IOC_O_IOCFG2 0x00000008 + +// Configuration of DIO3 +#define IOC_O_IOCFG3 0x0000000C + +// Configuration of DIO4 +#define IOC_O_IOCFG4 0x00000010 + +// Configuration of DIO5 +#define IOC_O_IOCFG5 0x00000014 + +// Configuration of DIO6 +#define IOC_O_IOCFG6 0x00000018 + +// Configuration of DIO7 +#define IOC_O_IOCFG7 0x0000001C + +// Configuration of DIO8 +#define IOC_O_IOCFG8 0x00000020 + +// Configuration of DIO9 +#define IOC_O_IOCFG9 0x00000024 + +// Configuration of DIO10 +#define IOC_O_IOCFG10 0x00000028 + +// Configuration of DIO11 +#define IOC_O_IOCFG11 0x0000002C + +// Configuration of DIO12 +#define IOC_O_IOCFG12 0x00000030 + +// Configuration of DIO13 +#define IOC_O_IOCFG13 0x00000034 + +// Configuration of DIO14 +#define IOC_O_IOCFG14 0x00000038 + +// Configuration of DIO15 +#define IOC_O_IOCFG15 0x0000003C + +// Configuration of DIO16 +#define IOC_O_IOCFG16 0x00000040 + +// Configuration of DIO17 +#define IOC_O_IOCFG17 0x00000044 + +// Configuration of DIO18 +#define IOC_O_IOCFG18 0x00000048 + +// Configuration of DIO19 +#define IOC_O_IOCFG19 0x0000004C + +// Configuration of DIO20 +#define IOC_O_IOCFG20 0x00000050 + +// Configuration of DIO21 +#define IOC_O_IOCFG21 0x00000054 + +// Configuration of DIO22 +#define IOC_O_IOCFG22 0x00000058 + +// Configuration of DIO23 +#define IOC_O_IOCFG23 0x0000005C + +// Configuration of DIO24 +#define IOC_O_IOCFG24 0x00000060 + +// Configuration of DIO25 +#define IOC_O_IOCFG25 0x00000064 + +// Configuration of DIO26 +#define IOC_O_IOCFG26 0x00000068 + +// Configuration of DIO27 +#define IOC_O_IOCFG27 0x0000006C + +// Configuration of DIO28 +#define IOC_O_IOCFG28 0x00000070 + +// Configuration of DIO29 +#define IOC_O_IOCFG29 0x00000074 + +// Configuration of DIO30 +#define IOC_O_IOCFG30 0x00000078 + +// Configuration of DIO31 +#define IOC_O_IOCFG31 0x0000007C + +//***************************************************************************** +// +// Register: IOC_O_IOCFG0 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG0_HYST_EN 0x40000000 +#define IOC_IOCFG0_HYST_EN_BITN 30 +#define IOC_IOCFG0_HYST_EN_M 0x40000000 +#define IOC_IOCFG0_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG0_IE 0x20000000 +#define IOC_IOCFG0_IE_BITN 29 +#define IOC_IOCFG0_IE_M 0x20000000 +#define IOC_IOCFG0_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG0_WU_CFG_W 2 +#define IOC_IOCFG0_WU_CFG_M 0x18000000 +#define IOC_IOCFG0_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input/output +// OPENSRC Open Source +// Normal input / outut +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG0_IOMODE_W 3 +#define IOC_IOCFG0_IOMODE_M 0x07000000 +#define IOC_IOCFG0_IOMODE_S 24 +#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG0_IOMODE_INV 0x01000000 +#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG0_EDGE_DET_W 2 +#define IOC_IOCFG0_EDGE_DET_M 0x00030000 +#define IOC_IOCFG0_EDGE_DET_S 16 +#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG0_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG0_PULL_CTL_W 2 +#define IOC_IOCFG0_PULL_CTL_M 0x00006000 +#define IOC_IOCFG0_PULL_CTL_S 13 +#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG0_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG0_SLEW_RED 0x00001000 +#define IOC_IOCFG0_SLEW_RED_BITN 12 +#define IOC_IOCFG0_SLEW_RED_M 0x00001000 +#define IOC_IOCFG0_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG0_IOCURR_W 2 +#define IOC_IOCFG0_IOCURR_M 0x00000C00 +#define IOC_IOCFG0_IOCURR_S 10 +#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG0_IOCURR_4MA 0x00000400 +#define IOC_IOCFG0_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG0_IOSTR_W 2 +#define IOC_IOCFG0_IOSTR_M 0x00000300 +#define IOC_IOCFG0_IOSTR_S 8 +#define IOC_IOCFG0_IOSTR_MAX 0x00000300 +#define IOC_IOCFG0_IOSTR_MED 0x00000200 +#define IOC_IOCFG0_IOSTR_MIN 0x00000100 +#define IOC_IOCFG0_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO0 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG0_PORT_ID_W 6 +#define IOC_IOCFG0_PORT_ID_M 0x0000003F +#define IOC_IOCFG0_PORT_ID_S 0 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG1 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG1_HYST_EN 0x40000000 +#define IOC_IOCFG1_HYST_EN_BITN 30 +#define IOC_IOCFG1_HYST_EN_M 0x40000000 +#define IOC_IOCFG1_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG1_IE 0x20000000 +#define IOC_IOCFG1_IE_BITN 29 +#define IOC_IOCFG1_IE_M 0x20000000 +#define IOC_IOCFG1_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG1_WU_CFG_W 2 +#define IOC_IOCFG1_WU_CFG_M 0x18000000 +#define IOC_IOCFG1_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG1_IOMODE_W 3 +#define IOC_IOCFG1_IOMODE_M 0x07000000 +#define IOC_IOCFG1_IOMODE_S 24 +#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG1_IOMODE_INV 0x01000000 +#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG1_EDGE_DET_W 2 +#define IOC_IOCFG1_EDGE_DET_M 0x00030000 +#define IOC_IOCFG1_EDGE_DET_S 16 +#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG1_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG1_PULL_CTL_W 2 +#define IOC_IOCFG1_PULL_CTL_M 0x00006000 +#define IOC_IOCFG1_PULL_CTL_S 13 +#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG1_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG1_SLEW_RED 0x00001000 +#define IOC_IOCFG1_SLEW_RED_BITN 12 +#define IOC_IOCFG1_SLEW_RED_M 0x00001000 +#define IOC_IOCFG1_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG1_IOCURR_W 2 +#define IOC_IOCFG1_IOCURR_M 0x00000C00 +#define IOC_IOCFG1_IOCURR_S 10 +#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG1_IOCURR_4MA 0x00000400 +#define IOC_IOCFG1_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG1_IOSTR_W 2 +#define IOC_IOCFG1_IOSTR_M 0x00000300 +#define IOC_IOCFG1_IOSTR_S 8 +#define IOC_IOCFG1_IOSTR_MAX 0x00000300 +#define IOC_IOCFG1_IOSTR_MED 0x00000200 +#define IOC_IOCFG1_IOSTR_MIN 0x00000100 +#define IOC_IOCFG1_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO1 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG1_PORT_ID_W 6 +#define IOC_IOCFG1_PORT_ID_M 0x0000003F +#define IOC_IOCFG1_PORT_ID_S 0 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG2 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG2_HYST_EN 0x40000000 +#define IOC_IOCFG2_HYST_EN_BITN 30 +#define IOC_IOCFG2_HYST_EN_M 0x40000000 +#define IOC_IOCFG2_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG2_IE 0x20000000 +#define IOC_IOCFG2_IE_BITN 29 +#define IOC_IOCFG2_IE_M 0x20000000 +#define IOC_IOCFG2_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG2_WU_CFG_W 2 +#define IOC_IOCFG2_WU_CFG_M 0x18000000 +#define IOC_IOCFG2_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG2_IOMODE_W 3 +#define IOC_IOCFG2_IOMODE_M 0x07000000 +#define IOC_IOCFG2_IOMODE_S 24 +#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG2_IOMODE_INV 0x01000000 +#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG2_EDGE_DET_W 2 +#define IOC_IOCFG2_EDGE_DET_M 0x00030000 +#define IOC_IOCFG2_EDGE_DET_S 16 +#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG2_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG2_PULL_CTL_W 2 +#define IOC_IOCFG2_PULL_CTL_M 0x00006000 +#define IOC_IOCFG2_PULL_CTL_S 13 +#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG2_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG2_SLEW_RED 0x00001000 +#define IOC_IOCFG2_SLEW_RED_BITN 12 +#define IOC_IOCFG2_SLEW_RED_M 0x00001000 +#define IOC_IOCFG2_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG2_IOCURR_W 2 +#define IOC_IOCFG2_IOCURR_M 0x00000C00 +#define IOC_IOCFG2_IOCURR_S 10 +#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG2_IOCURR_4MA 0x00000400 +#define IOC_IOCFG2_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG2_IOSTR_W 2 +#define IOC_IOCFG2_IOSTR_M 0x00000300 +#define IOC_IOCFG2_IOSTR_S 8 +#define IOC_IOCFG2_IOSTR_MAX 0x00000300 +#define IOC_IOCFG2_IOSTR_MED 0x00000200 +#define IOC_IOCFG2_IOSTR_MIN 0x00000100 +#define IOC_IOCFG2_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO2 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG2_PORT_ID_W 6 +#define IOC_IOCFG2_PORT_ID_M 0x0000003F +#define IOC_IOCFG2_PORT_ID_S 0 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG3 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG3_HYST_EN 0x40000000 +#define IOC_IOCFG3_HYST_EN_BITN 30 +#define IOC_IOCFG3_HYST_EN_M 0x40000000 +#define IOC_IOCFG3_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG3_IE 0x20000000 +#define IOC_IOCFG3_IE_BITN 29 +#define IOC_IOCFG3_IE_M 0x20000000 +#define IOC_IOCFG3_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG3_WU_CFG_W 2 +#define IOC_IOCFG3_WU_CFG_M 0x18000000 +#define IOC_IOCFG3_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG3_IOMODE_W 3 +#define IOC_IOCFG3_IOMODE_M 0x07000000 +#define IOC_IOCFG3_IOMODE_S 24 +#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG3_IOMODE_INV 0x01000000 +#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG3_EDGE_DET_W 2 +#define IOC_IOCFG3_EDGE_DET_M 0x00030000 +#define IOC_IOCFG3_EDGE_DET_S 16 +#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG3_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG3_PULL_CTL_W 2 +#define IOC_IOCFG3_PULL_CTL_M 0x00006000 +#define IOC_IOCFG3_PULL_CTL_S 13 +#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG3_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG3_SLEW_RED 0x00001000 +#define IOC_IOCFG3_SLEW_RED_BITN 12 +#define IOC_IOCFG3_SLEW_RED_M 0x00001000 +#define IOC_IOCFG3_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG3_IOCURR_W 2 +#define IOC_IOCFG3_IOCURR_M 0x00000C00 +#define IOC_IOCFG3_IOCURR_S 10 +#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG3_IOCURR_4MA 0x00000400 +#define IOC_IOCFG3_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG3_IOSTR_W 2 +#define IOC_IOCFG3_IOSTR_M 0x00000300 +#define IOC_IOCFG3_IOSTR_S 8 +#define IOC_IOCFG3_IOSTR_MAX 0x00000300 +#define IOC_IOCFG3_IOSTR_MED 0x00000200 +#define IOC_IOCFG3_IOSTR_MIN 0x00000100 +#define IOC_IOCFG3_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO3 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG3_PORT_ID_W 6 +#define IOC_IOCFG3_PORT_ID_M 0x0000003F +#define IOC_IOCFG3_PORT_ID_S 0 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG4 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG4_HYST_EN 0x40000000 +#define IOC_IOCFG4_HYST_EN_BITN 30 +#define IOC_IOCFG4_HYST_EN_M 0x40000000 +#define IOC_IOCFG4_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG4_IE 0x20000000 +#define IOC_IOCFG4_IE_BITN 29 +#define IOC_IOCFG4_IE_M 0x20000000 +#define IOC_IOCFG4_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG4_WU_CFG_W 2 +#define IOC_IOCFG4_WU_CFG_M 0x18000000 +#define IOC_IOCFG4_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG4_IOMODE_W 3 +#define IOC_IOCFG4_IOMODE_M 0x07000000 +#define IOC_IOCFG4_IOMODE_S 24 +#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG4_IOMODE_INV 0x01000000 +#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG4_EDGE_DET_W 2 +#define IOC_IOCFG4_EDGE_DET_M 0x00030000 +#define IOC_IOCFG4_EDGE_DET_S 16 +#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG4_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG4_PULL_CTL_W 2 +#define IOC_IOCFG4_PULL_CTL_M 0x00006000 +#define IOC_IOCFG4_PULL_CTL_S 13 +#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG4_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG4_SLEW_RED 0x00001000 +#define IOC_IOCFG4_SLEW_RED_BITN 12 +#define IOC_IOCFG4_SLEW_RED_M 0x00001000 +#define IOC_IOCFG4_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG4_IOCURR_W 2 +#define IOC_IOCFG4_IOCURR_M 0x00000C00 +#define IOC_IOCFG4_IOCURR_S 10 +#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG4_IOCURR_4MA 0x00000400 +#define IOC_IOCFG4_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG4_IOSTR_W 2 +#define IOC_IOCFG4_IOSTR_M 0x00000300 +#define IOC_IOCFG4_IOSTR_S 8 +#define IOC_IOCFG4_IOSTR_MAX 0x00000300 +#define IOC_IOCFG4_IOSTR_MED 0x00000200 +#define IOC_IOCFG4_IOSTR_MIN 0x00000100 +#define IOC_IOCFG4_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO4 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG4_PORT_ID_W 6 +#define IOC_IOCFG4_PORT_ID_M 0x0000003F +#define IOC_IOCFG4_PORT_ID_S 0 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG5 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG5_HYST_EN 0x40000000 +#define IOC_IOCFG5_HYST_EN_BITN 30 +#define IOC_IOCFG5_HYST_EN_M 0x40000000 +#define IOC_IOCFG5_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG5_IE 0x20000000 +#define IOC_IOCFG5_IE_BITN 29 +#define IOC_IOCFG5_IE_M 0x20000000 +#define IOC_IOCFG5_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG5_WU_CFG_W 2 +#define IOC_IOCFG5_WU_CFG_M 0x18000000 +#define IOC_IOCFG5_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG5_IOMODE_W 3 +#define IOC_IOCFG5_IOMODE_M 0x07000000 +#define IOC_IOCFG5_IOMODE_S 24 +#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG5_IOMODE_INV 0x01000000 +#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG5_EDGE_DET_W 2 +#define IOC_IOCFG5_EDGE_DET_M 0x00030000 +#define IOC_IOCFG5_EDGE_DET_S 16 +#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG5_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG5_PULL_CTL_W 2 +#define IOC_IOCFG5_PULL_CTL_M 0x00006000 +#define IOC_IOCFG5_PULL_CTL_S 13 +#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG5_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG5_SLEW_RED 0x00001000 +#define IOC_IOCFG5_SLEW_RED_BITN 12 +#define IOC_IOCFG5_SLEW_RED_M 0x00001000 +#define IOC_IOCFG5_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG5_IOCURR_W 2 +#define IOC_IOCFG5_IOCURR_M 0x00000C00 +#define IOC_IOCFG5_IOCURR_S 10 +#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG5_IOCURR_4MA 0x00000400 +#define IOC_IOCFG5_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG5_IOSTR_W 2 +#define IOC_IOCFG5_IOSTR_M 0x00000300 +#define IOC_IOCFG5_IOSTR_S 8 +#define IOC_IOCFG5_IOSTR_MAX 0x00000300 +#define IOC_IOCFG5_IOSTR_MED 0x00000200 +#define IOC_IOCFG5_IOSTR_MIN 0x00000100 +#define IOC_IOCFG5_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO5 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG5_PORT_ID_W 6 +#define IOC_IOCFG5_PORT_ID_M 0x0000003F +#define IOC_IOCFG5_PORT_ID_S 0 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG6 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG6_HYST_EN 0x40000000 +#define IOC_IOCFG6_HYST_EN_BITN 30 +#define IOC_IOCFG6_HYST_EN_M 0x40000000 +#define IOC_IOCFG6_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG6_IE 0x20000000 +#define IOC_IOCFG6_IE_BITN 29 +#define IOC_IOCFG6_IE_M 0x20000000 +#define IOC_IOCFG6_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG6_WU_CFG_W 2 +#define IOC_IOCFG6_WU_CFG_M 0x18000000 +#define IOC_IOCFG6_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG6_IOMODE_W 3 +#define IOC_IOCFG6_IOMODE_M 0x07000000 +#define IOC_IOCFG6_IOMODE_S 24 +#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG6_IOMODE_INV 0x01000000 +#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG6_EDGE_DET_W 2 +#define IOC_IOCFG6_EDGE_DET_M 0x00030000 +#define IOC_IOCFG6_EDGE_DET_S 16 +#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG6_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG6_PULL_CTL_W 2 +#define IOC_IOCFG6_PULL_CTL_M 0x00006000 +#define IOC_IOCFG6_PULL_CTL_S 13 +#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG6_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG6_SLEW_RED 0x00001000 +#define IOC_IOCFG6_SLEW_RED_BITN 12 +#define IOC_IOCFG6_SLEW_RED_M 0x00001000 +#define IOC_IOCFG6_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG6_IOCURR_W 2 +#define IOC_IOCFG6_IOCURR_M 0x00000C00 +#define IOC_IOCFG6_IOCURR_S 10 +#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG6_IOCURR_4MA 0x00000400 +#define IOC_IOCFG6_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG6_IOSTR_W 2 +#define IOC_IOCFG6_IOSTR_M 0x00000300 +#define IOC_IOCFG6_IOSTR_S 8 +#define IOC_IOCFG6_IOSTR_MAX 0x00000300 +#define IOC_IOCFG6_IOSTR_MED 0x00000200 +#define IOC_IOCFG6_IOSTR_MIN 0x00000100 +#define IOC_IOCFG6_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO6 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG6_PORT_ID_W 6 +#define IOC_IOCFG6_PORT_ID_M 0x0000003F +#define IOC_IOCFG6_PORT_ID_S 0 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG7 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG7_HYST_EN 0x40000000 +#define IOC_IOCFG7_HYST_EN_BITN 30 +#define IOC_IOCFG7_HYST_EN_M 0x40000000 +#define IOC_IOCFG7_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG7_IE 0x20000000 +#define IOC_IOCFG7_IE_BITN 29 +#define IOC_IOCFG7_IE_M 0x20000000 +#define IOC_IOCFG7_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG7_WU_CFG_W 2 +#define IOC_IOCFG7_WU_CFG_M 0x18000000 +#define IOC_IOCFG7_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG7_IOMODE_W 3 +#define IOC_IOCFG7_IOMODE_M 0x07000000 +#define IOC_IOCFG7_IOMODE_S 24 +#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG7_IOMODE_INV 0x01000000 +#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG7_EDGE_DET_W 2 +#define IOC_IOCFG7_EDGE_DET_M 0x00030000 +#define IOC_IOCFG7_EDGE_DET_S 16 +#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG7_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG7_PULL_CTL_W 2 +#define IOC_IOCFG7_PULL_CTL_M 0x00006000 +#define IOC_IOCFG7_PULL_CTL_S 13 +#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG7_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG7_SLEW_RED 0x00001000 +#define IOC_IOCFG7_SLEW_RED_BITN 12 +#define IOC_IOCFG7_SLEW_RED_M 0x00001000 +#define IOC_IOCFG7_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG7_IOCURR_W 2 +#define IOC_IOCFG7_IOCURR_M 0x00000C00 +#define IOC_IOCFG7_IOCURR_S 10 +#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG7_IOCURR_4MA 0x00000400 +#define IOC_IOCFG7_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG7_IOSTR_W 2 +#define IOC_IOCFG7_IOSTR_M 0x00000300 +#define IOC_IOCFG7_IOSTR_S 8 +#define IOC_IOCFG7_IOSTR_MAX 0x00000300 +#define IOC_IOCFG7_IOSTR_MED 0x00000200 +#define IOC_IOCFG7_IOSTR_MIN 0x00000100 +#define IOC_IOCFG7_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO7 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG7_PORT_ID_W 6 +#define IOC_IOCFG7_PORT_ID_M 0x0000003F +#define IOC_IOCFG7_PORT_ID_S 0 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG8 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG8_HYST_EN 0x40000000 +#define IOC_IOCFG8_HYST_EN_BITN 30 +#define IOC_IOCFG8_HYST_EN_M 0x40000000 +#define IOC_IOCFG8_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG8_IE 0x20000000 +#define IOC_IOCFG8_IE_BITN 29 +#define IOC_IOCFG8_IE_M 0x20000000 +#define IOC_IOCFG8_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG8_WU_CFG_W 2 +#define IOC_IOCFG8_WU_CFG_M 0x18000000 +#define IOC_IOCFG8_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG8_IOMODE_W 3 +#define IOC_IOCFG8_IOMODE_M 0x07000000 +#define IOC_IOCFG8_IOMODE_S 24 +#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG8_IOMODE_INV 0x01000000 +#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG8_EDGE_DET_W 2 +#define IOC_IOCFG8_EDGE_DET_M 0x00030000 +#define IOC_IOCFG8_EDGE_DET_S 16 +#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG8_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG8_PULL_CTL_W 2 +#define IOC_IOCFG8_PULL_CTL_M 0x00006000 +#define IOC_IOCFG8_PULL_CTL_S 13 +#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG8_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG8_SLEW_RED 0x00001000 +#define IOC_IOCFG8_SLEW_RED_BITN 12 +#define IOC_IOCFG8_SLEW_RED_M 0x00001000 +#define IOC_IOCFG8_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG8_IOCURR_W 2 +#define IOC_IOCFG8_IOCURR_M 0x00000C00 +#define IOC_IOCFG8_IOCURR_S 10 +#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG8_IOCURR_4MA 0x00000400 +#define IOC_IOCFG8_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG8_IOSTR_W 2 +#define IOC_IOCFG8_IOSTR_M 0x00000300 +#define IOC_IOCFG8_IOSTR_S 8 +#define IOC_IOCFG8_IOSTR_MAX 0x00000300 +#define IOC_IOCFG8_IOSTR_MED 0x00000200 +#define IOC_IOCFG8_IOSTR_MIN 0x00000100 +#define IOC_IOCFG8_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO8 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG8_PORT_ID_W 6 +#define IOC_IOCFG8_PORT_ID_M 0x0000003F +#define IOC_IOCFG8_PORT_ID_S 0 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG9 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG9_HYST_EN 0x40000000 +#define IOC_IOCFG9_HYST_EN_BITN 30 +#define IOC_IOCFG9_HYST_EN_M 0x40000000 +#define IOC_IOCFG9_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG9_IE 0x20000000 +#define IOC_IOCFG9_IE_BITN 29 +#define IOC_IOCFG9_IE_M 0x20000000 +#define IOC_IOCFG9_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG9_WU_CFG_W 2 +#define IOC_IOCFG9_WU_CFG_M 0x18000000 +#define IOC_IOCFG9_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG9_IOMODE_W 3 +#define IOC_IOCFG9_IOMODE_M 0x07000000 +#define IOC_IOCFG9_IOMODE_S 24 +#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG9_IOMODE_INV 0x01000000 +#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG9_EDGE_DET_W 2 +#define IOC_IOCFG9_EDGE_DET_M 0x00030000 +#define IOC_IOCFG9_EDGE_DET_S 16 +#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG9_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG9_PULL_CTL_W 2 +#define IOC_IOCFG9_PULL_CTL_M 0x00006000 +#define IOC_IOCFG9_PULL_CTL_S 13 +#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG9_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG9_SLEW_RED 0x00001000 +#define IOC_IOCFG9_SLEW_RED_BITN 12 +#define IOC_IOCFG9_SLEW_RED_M 0x00001000 +#define IOC_IOCFG9_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG9_IOCURR_W 2 +#define IOC_IOCFG9_IOCURR_M 0x00000C00 +#define IOC_IOCFG9_IOCURR_S 10 +#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG9_IOCURR_4MA 0x00000400 +#define IOC_IOCFG9_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG9_IOSTR_W 2 +#define IOC_IOCFG9_IOSTR_M 0x00000300 +#define IOC_IOCFG9_IOSTR_S 8 +#define IOC_IOCFG9_IOSTR_MAX 0x00000300 +#define IOC_IOCFG9_IOSTR_MED 0x00000200 +#define IOC_IOCFG9_IOSTR_MIN 0x00000100 +#define IOC_IOCFG9_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO9 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG9_PORT_ID_W 6 +#define IOC_IOCFG9_PORT_ID_M 0x0000003F +#define IOC_IOCFG9_PORT_ID_S 0 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG10 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG10_HYST_EN 0x40000000 +#define IOC_IOCFG10_HYST_EN_BITN 30 +#define IOC_IOCFG10_HYST_EN_M 0x40000000 +#define IOC_IOCFG10_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG10_IE 0x20000000 +#define IOC_IOCFG10_IE_BITN 29 +#define IOC_IOCFG10_IE_M 0x20000000 +#define IOC_IOCFG10_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG10_WU_CFG_W 2 +#define IOC_IOCFG10_WU_CFG_M 0x18000000 +#define IOC_IOCFG10_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG10_IOMODE_W 3 +#define IOC_IOCFG10_IOMODE_M 0x07000000 +#define IOC_IOCFG10_IOMODE_S 24 +#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG10_IOMODE_INV 0x01000000 +#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG10_EDGE_DET_W 2 +#define IOC_IOCFG10_EDGE_DET_M 0x00030000 +#define IOC_IOCFG10_EDGE_DET_S 16 +#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG10_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG10_PULL_CTL_W 2 +#define IOC_IOCFG10_PULL_CTL_M 0x00006000 +#define IOC_IOCFG10_PULL_CTL_S 13 +#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG10_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG10_SLEW_RED 0x00001000 +#define IOC_IOCFG10_SLEW_RED_BITN 12 +#define IOC_IOCFG10_SLEW_RED_M 0x00001000 +#define IOC_IOCFG10_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG10_IOCURR_W 2 +#define IOC_IOCFG10_IOCURR_M 0x00000C00 +#define IOC_IOCFG10_IOCURR_S 10 +#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG10_IOCURR_4MA 0x00000400 +#define IOC_IOCFG10_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG10_IOSTR_W 2 +#define IOC_IOCFG10_IOSTR_M 0x00000300 +#define IOC_IOCFG10_IOSTR_S 8 +#define IOC_IOCFG10_IOSTR_MAX 0x00000300 +#define IOC_IOCFG10_IOSTR_MED 0x00000200 +#define IOC_IOCFG10_IOSTR_MIN 0x00000100 +#define IOC_IOCFG10_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO10 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG10_PORT_ID_W 6 +#define IOC_IOCFG10_PORT_ID_M 0x0000003F +#define IOC_IOCFG10_PORT_ID_S 0 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG11 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG11_HYST_EN 0x40000000 +#define IOC_IOCFG11_HYST_EN_BITN 30 +#define IOC_IOCFG11_HYST_EN_M 0x40000000 +#define IOC_IOCFG11_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG11_IE 0x20000000 +#define IOC_IOCFG11_IE_BITN 29 +#define IOC_IOCFG11_IE_M 0x20000000 +#define IOC_IOCFG11_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG11_WU_CFG_W 2 +#define IOC_IOCFG11_WU_CFG_M 0x18000000 +#define IOC_IOCFG11_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG11_IOMODE_W 3 +#define IOC_IOCFG11_IOMODE_M 0x07000000 +#define IOC_IOCFG11_IOMODE_S 24 +#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG11_IOMODE_INV 0x01000000 +#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG11_EDGE_DET_W 2 +#define IOC_IOCFG11_EDGE_DET_M 0x00030000 +#define IOC_IOCFG11_EDGE_DET_S 16 +#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG11_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG11_PULL_CTL_W 2 +#define IOC_IOCFG11_PULL_CTL_M 0x00006000 +#define IOC_IOCFG11_PULL_CTL_S 13 +#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG11_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG11_SLEW_RED 0x00001000 +#define IOC_IOCFG11_SLEW_RED_BITN 12 +#define IOC_IOCFG11_SLEW_RED_M 0x00001000 +#define IOC_IOCFG11_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG11_IOCURR_W 2 +#define IOC_IOCFG11_IOCURR_M 0x00000C00 +#define IOC_IOCFG11_IOCURR_S 10 +#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG11_IOCURR_4MA 0x00000400 +#define IOC_IOCFG11_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG11_IOSTR_W 2 +#define IOC_IOCFG11_IOSTR_M 0x00000300 +#define IOC_IOCFG11_IOSTR_S 8 +#define IOC_IOCFG11_IOSTR_MAX 0x00000300 +#define IOC_IOCFG11_IOSTR_MED 0x00000200 +#define IOC_IOCFG11_IOSTR_MIN 0x00000100 +#define IOC_IOCFG11_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO11 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG11_PORT_ID_W 6 +#define IOC_IOCFG11_PORT_ID_M 0x0000003F +#define IOC_IOCFG11_PORT_ID_S 0 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG12 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG12_HYST_EN 0x40000000 +#define IOC_IOCFG12_HYST_EN_BITN 30 +#define IOC_IOCFG12_HYST_EN_M 0x40000000 +#define IOC_IOCFG12_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG12_IE 0x20000000 +#define IOC_IOCFG12_IE_BITN 29 +#define IOC_IOCFG12_IE_M 0x20000000 +#define IOC_IOCFG12_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG12_WU_CFG_W 2 +#define IOC_IOCFG12_WU_CFG_M 0x18000000 +#define IOC_IOCFG12_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG12_IOMODE_W 3 +#define IOC_IOCFG12_IOMODE_M 0x07000000 +#define IOC_IOCFG12_IOMODE_S 24 +#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG12_IOMODE_INV 0x01000000 +#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG12_EDGE_DET_W 2 +#define IOC_IOCFG12_EDGE_DET_M 0x00030000 +#define IOC_IOCFG12_EDGE_DET_S 16 +#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG12_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG12_PULL_CTL_W 2 +#define IOC_IOCFG12_PULL_CTL_M 0x00006000 +#define IOC_IOCFG12_PULL_CTL_S 13 +#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG12_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG12_SLEW_RED 0x00001000 +#define IOC_IOCFG12_SLEW_RED_BITN 12 +#define IOC_IOCFG12_SLEW_RED_M 0x00001000 +#define IOC_IOCFG12_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG12_IOCURR_W 2 +#define IOC_IOCFG12_IOCURR_M 0x00000C00 +#define IOC_IOCFG12_IOCURR_S 10 +#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG12_IOCURR_4MA 0x00000400 +#define IOC_IOCFG12_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG12_IOSTR_W 2 +#define IOC_IOCFG12_IOSTR_M 0x00000300 +#define IOC_IOCFG12_IOSTR_S 8 +#define IOC_IOCFG12_IOSTR_MAX 0x00000300 +#define IOC_IOCFG12_IOSTR_MED 0x00000200 +#define IOC_IOCFG12_IOSTR_MIN 0x00000100 +#define IOC_IOCFG12_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO12 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG12_PORT_ID_W 6 +#define IOC_IOCFG12_PORT_ID_M 0x0000003F +#define IOC_IOCFG12_PORT_ID_S 0 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG13 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG13_HYST_EN 0x40000000 +#define IOC_IOCFG13_HYST_EN_BITN 30 +#define IOC_IOCFG13_HYST_EN_M 0x40000000 +#define IOC_IOCFG13_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG13_IE 0x20000000 +#define IOC_IOCFG13_IE_BITN 29 +#define IOC_IOCFG13_IE_M 0x20000000 +#define IOC_IOCFG13_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG13_WU_CFG_W 2 +#define IOC_IOCFG13_WU_CFG_M 0x18000000 +#define IOC_IOCFG13_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG13_IOMODE_W 3 +#define IOC_IOCFG13_IOMODE_M 0x07000000 +#define IOC_IOCFG13_IOMODE_S 24 +#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG13_IOMODE_INV 0x01000000 +#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG13_EDGE_DET_W 2 +#define IOC_IOCFG13_EDGE_DET_M 0x00030000 +#define IOC_IOCFG13_EDGE_DET_S 16 +#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG13_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG13_PULL_CTL_W 2 +#define IOC_IOCFG13_PULL_CTL_M 0x00006000 +#define IOC_IOCFG13_PULL_CTL_S 13 +#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG13_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG13_SLEW_RED 0x00001000 +#define IOC_IOCFG13_SLEW_RED_BITN 12 +#define IOC_IOCFG13_SLEW_RED_M 0x00001000 +#define IOC_IOCFG13_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG13_IOCURR_W 2 +#define IOC_IOCFG13_IOCURR_M 0x00000C00 +#define IOC_IOCFG13_IOCURR_S 10 +#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG13_IOCURR_4MA 0x00000400 +#define IOC_IOCFG13_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG13_IOSTR_W 2 +#define IOC_IOCFG13_IOSTR_M 0x00000300 +#define IOC_IOCFG13_IOSTR_S 8 +#define IOC_IOCFG13_IOSTR_MAX 0x00000300 +#define IOC_IOCFG13_IOSTR_MED 0x00000200 +#define IOC_IOCFG13_IOSTR_MIN 0x00000100 +#define IOC_IOCFG13_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO13 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG13_PORT_ID_W 6 +#define IOC_IOCFG13_PORT_ID_M 0x0000003F +#define IOC_IOCFG13_PORT_ID_S 0 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG14 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG14_HYST_EN 0x40000000 +#define IOC_IOCFG14_HYST_EN_BITN 30 +#define IOC_IOCFG14_HYST_EN_M 0x40000000 +#define IOC_IOCFG14_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG14_IE 0x20000000 +#define IOC_IOCFG14_IE_BITN 29 +#define IOC_IOCFG14_IE_M 0x20000000 +#define IOC_IOCFG14_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG14_WU_CFG_W 2 +#define IOC_IOCFG14_WU_CFG_M 0x18000000 +#define IOC_IOCFG14_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG14_IOMODE_W 3 +#define IOC_IOCFG14_IOMODE_M 0x07000000 +#define IOC_IOCFG14_IOMODE_S 24 +#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG14_IOMODE_INV 0x01000000 +#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG14_EDGE_DET_W 2 +#define IOC_IOCFG14_EDGE_DET_M 0x00030000 +#define IOC_IOCFG14_EDGE_DET_S 16 +#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG14_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG14_PULL_CTL_W 2 +#define IOC_IOCFG14_PULL_CTL_M 0x00006000 +#define IOC_IOCFG14_PULL_CTL_S 13 +#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG14_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG14_SLEW_RED 0x00001000 +#define IOC_IOCFG14_SLEW_RED_BITN 12 +#define IOC_IOCFG14_SLEW_RED_M 0x00001000 +#define IOC_IOCFG14_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG14_IOCURR_W 2 +#define IOC_IOCFG14_IOCURR_M 0x00000C00 +#define IOC_IOCFG14_IOCURR_S 10 +#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG14_IOCURR_4MA 0x00000400 +#define IOC_IOCFG14_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG14_IOSTR_W 2 +#define IOC_IOCFG14_IOSTR_M 0x00000300 +#define IOC_IOCFG14_IOSTR_S 8 +#define IOC_IOCFG14_IOSTR_MAX 0x00000300 +#define IOC_IOCFG14_IOSTR_MED 0x00000200 +#define IOC_IOCFG14_IOSTR_MIN 0x00000100 +#define IOC_IOCFG14_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO14 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG14_PORT_ID_W 6 +#define IOC_IOCFG14_PORT_ID_M 0x0000003F +#define IOC_IOCFG14_PORT_ID_S 0 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG15 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG15_HYST_EN 0x40000000 +#define IOC_IOCFG15_HYST_EN_BITN 30 +#define IOC_IOCFG15_HYST_EN_M 0x40000000 +#define IOC_IOCFG15_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG15_IE 0x20000000 +#define IOC_IOCFG15_IE_BITN 29 +#define IOC_IOCFG15_IE_M 0x20000000 +#define IOC_IOCFG15_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG15_WU_CFG_W 2 +#define IOC_IOCFG15_WU_CFG_M 0x18000000 +#define IOC_IOCFG15_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG15_IOMODE_W 3 +#define IOC_IOCFG15_IOMODE_M 0x07000000 +#define IOC_IOCFG15_IOMODE_S 24 +#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG15_IOMODE_INV 0x01000000 +#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG15_EDGE_DET_W 2 +#define IOC_IOCFG15_EDGE_DET_M 0x00030000 +#define IOC_IOCFG15_EDGE_DET_S 16 +#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG15_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG15_PULL_CTL_W 2 +#define IOC_IOCFG15_PULL_CTL_M 0x00006000 +#define IOC_IOCFG15_PULL_CTL_S 13 +#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG15_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG15_SLEW_RED 0x00001000 +#define IOC_IOCFG15_SLEW_RED_BITN 12 +#define IOC_IOCFG15_SLEW_RED_M 0x00001000 +#define IOC_IOCFG15_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG15_IOCURR_W 2 +#define IOC_IOCFG15_IOCURR_M 0x00000C00 +#define IOC_IOCFG15_IOCURR_S 10 +#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG15_IOCURR_4MA 0x00000400 +#define IOC_IOCFG15_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG15_IOSTR_W 2 +#define IOC_IOCFG15_IOSTR_M 0x00000300 +#define IOC_IOCFG15_IOSTR_S 8 +#define IOC_IOCFG15_IOSTR_MAX 0x00000300 +#define IOC_IOCFG15_IOSTR_MED 0x00000200 +#define IOC_IOCFG15_IOSTR_MIN 0x00000100 +#define IOC_IOCFG15_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO15 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG15_PORT_ID_W 6 +#define IOC_IOCFG15_PORT_ID_M 0x0000003F +#define IOC_IOCFG15_PORT_ID_S 0 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG16 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG16_HYST_EN 0x40000000 +#define IOC_IOCFG16_HYST_EN_BITN 30 +#define IOC_IOCFG16_HYST_EN_M 0x40000000 +#define IOC_IOCFG16_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG16_IE 0x20000000 +#define IOC_IOCFG16_IE_BITN 29 +#define IOC_IOCFG16_IE_M 0x20000000 +#define IOC_IOCFG16_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG16_WU_CFG_W 2 +#define IOC_IOCFG16_WU_CFG_M 0x18000000 +#define IOC_IOCFG16_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG16_IOMODE_W 3 +#define IOC_IOCFG16_IOMODE_M 0x07000000 +#define IOC_IOCFG16_IOMODE_S 24 +#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG16_IOMODE_INV 0x01000000 +#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG16_EDGE_DET_W 2 +#define IOC_IOCFG16_EDGE_DET_M 0x00030000 +#define IOC_IOCFG16_EDGE_DET_S 16 +#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG16_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG16_PULL_CTL_W 2 +#define IOC_IOCFG16_PULL_CTL_M 0x00006000 +#define IOC_IOCFG16_PULL_CTL_S 13 +#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG16_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG16_SLEW_RED 0x00001000 +#define IOC_IOCFG16_SLEW_RED_BITN 12 +#define IOC_IOCFG16_SLEW_RED_M 0x00001000 +#define IOC_IOCFG16_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG16_IOCURR_W 2 +#define IOC_IOCFG16_IOCURR_M 0x00000C00 +#define IOC_IOCFG16_IOCURR_S 10 +#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG16_IOCURR_4MA 0x00000400 +#define IOC_IOCFG16_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG16_IOSTR_W 2 +#define IOC_IOCFG16_IOSTR_M 0x00000300 +#define IOC_IOCFG16_IOSTR_S 8 +#define IOC_IOCFG16_IOSTR_MAX 0x00000300 +#define IOC_IOCFG16_IOSTR_MED 0x00000200 +#define IOC_IOCFG16_IOSTR_MIN 0x00000100 +#define IOC_IOCFG16_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO16 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG16_PORT_ID_W 6 +#define IOC_IOCFG16_PORT_ID_M 0x0000003F +#define IOC_IOCFG16_PORT_ID_S 0 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG17 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG17_HYST_EN 0x40000000 +#define IOC_IOCFG17_HYST_EN_BITN 30 +#define IOC_IOCFG17_HYST_EN_M 0x40000000 +#define IOC_IOCFG17_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG17_IE 0x20000000 +#define IOC_IOCFG17_IE_BITN 29 +#define IOC_IOCFG17_IE_M 0x20000000 +#define IOC_IOCFG17_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG17_WU_CFG_W 2 +#define IOC_IOCFG17_WU_CFG_M 0x18000000 +#define IOC_IOCFG17_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG17_IOMODE_W 3 +#define IOC_IOCFG17_IOMODE_M 0x07000000 +#define IOC_IOCFG17_IOMODE_S 24 +#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG17_IOMODE_INV 0x01000000 +#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG17_EDGE_DET_W 2 +#define IOC_IOCFG17_EDGE_DET_M 0x00030000 +#define IOC_IOCFG17_EDGE_DET_S 16 +#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG17_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG17_PULL_CTL_W 2 +#define IOC_IOCFG17_PULL_CTL_M 0x00006000 +#define IOC_IOCFG17_PULL_CTL_S 13 +#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG17_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG17_SLEW_RED 0x00001000 +#define IOC_IOCFG17_SLEW_RED_BITN 12 +#define IOC_IOCFG17_SLEW_RED_M 0x00001000 +#define IOC_IOCFG17_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG17_IOCURR_W 2 +#define IOC_IOCFG17_IOCURR_M 0x00000C00 +#define IOC_IOCFG17_IOCURR_S 10 +#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG17_IOCURR_4MA 0x00000400 +#define IOC_IOCFG17_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG17_IOSTR_W 2 +#define IOC_IOCFG17_IOSTR_M 0x00000300 +#define IOC_IOCFG17_IOSTR_S 8 +#define IOC_IOCFG17_IOSTR_MAX 0x00000300 +#define IOC_IOCFG17_IOSTR_MED 0x00000200 +#define IOC_IOCFG17_IOSTR_MIN 0x00000100 +#define IOC_IOCFG17_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO17 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG17_PORT_ID_W 6 +#define IOC_IOCFG17_PORT_ID_M 0x0000003F +#define IOC_IOCFG17_PORT_ID_S 0 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG18 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG18_HYST_EN 0x40000000 +#define IOC_IOCFG18_HYST_EN_BITN 30 +#define IOC_IOCFG18_HYST_EN_M 0x40000000 +#define IOC_IOCFG18_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG18_IE 0x20000000 +#define IOC_IOCFG18_IE_BITN 29 +#define IOC_IOCFG18_IE_M 0x20000000 +#define IOC_IOCFG18_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG18_WU_CFG_W 2 +#define IOC_IOCFG18_WU_CFG_M 0x18000000 +#define IOC_IOCFG18_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG18_IOMODE_W 3 +#define IOC_IOCFG18_IOMODE_M 0x07000000 +#define IOC_IOCFG18_IOMODE_S 24 +#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG18_IOMODE_INV 0x01000000 +#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG18_EDGE_DET_W 2 +#define IOC_IOCFG18_EDGE_DET_M 0x00030000 +#define IOC_IOCFG18_EDGE_DET_S 16 +#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG18_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG18_PULL_CTL_W 2 +#define IOC_IOCFG18_PULL_CTL_M 0x00006000 +#define IOC_IOCFG18_PULL_CTL_S 13 +#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG18_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG18_SLEW_RED 0x00001000 +#define IOC_IOCFG18_SLEW_RED_BITN 12 +#define IOC_IOCFG18_SLEW_RED_M 0x00001000 +#define IOC_IOCFG18_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG18_IOCURR_W 2 +#define IOC_IOCFG18_IOCURR_M 0x00000C00 +#define IOC_IOCFG18_IOCURR_S 10 +#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG18_IOCURR_4MA 0x00000400 +#define IOC_IOCFG18_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG18_IOSTR_W 2 +#define IOC_IOCFG18_IOSTR_M 0x00000300 +#define IOC_IOCFG18_IOSTR_S 8 +#define IOC_IOCFG18_IOSTR_MAX 0x00000300 +#define IOC_IOCFG18_IOSTR_MED 0x00000200 +#define IOC_IOCFG18_IOSTR_MIN 0x00000100 +#define IOC_IOCFG18_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO18 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG18_PORT_ID_W 6 +#define IOC_IOCFG18_PORT_ID_M 0x0000003F +#define IOC_IOCFG18_PORT_ID_S 0 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG19 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG19_HYST_EN 0x40000000 +#define IOC_IOCFG19_HYST_EN_BITN 30 +#define IOC_IOCFG19_HYST_EN_M 0x40000000 +#define IOC_IOCFG19_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG19_IE 0x20000000 +#define IOC_IOCFG19_IE_BITN 29 +#define IOC_IOCFG19_IE_M 0x20000000 +#define IOC_IOCFG19_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG19_WU_CFG_W 2 +#define IOC_IOCFG19_WU_CFG_M 0x18000000 +#define IOC_IOCFG19_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG19_IOMODE_W 3 +#define IOC_IOCFG19_IOMODE_M 0x07000000 +#define IOC_IOCFG19_IOMODE_S 24 +#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG19_IOMODE_INV 0x01000000 +#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG19_EDGE_DET_W 2 +#define IOC_IOCFG19_EDGE_DET_M 0x00030000 +#define IOC_IOCFG19_EDGE_DET_S 16 +#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG19_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG19_PULL_CTL_W 2 +#define IOC_IOCFG19_PULL_CTL_M 0x00006000 +#define IOC_IOCFG19_PULL_CTL_S 13 +#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG19_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG19_SLEW_RED 0x00001000 +#define IOC_IOCFG19_SLEW_RED_BITN 12 +#define IOC_IOCFG19_SLEW_RED_M 0x00001000 +#define IOC_IOCFG19_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG19_IOCURR_W 2 +#define IOC_IOCFG19_IOCURR_M 0x00000C00 +#define IOC_IOCFG19_IOCURR_S 10 +#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG19_IOCURR_4MA 0x00000400 +#define IOC_IOCFG19_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG19_IOSTR_W 2 +#define IOC_IOCFG19_IOSTR_M 0x00000300 +#define IOC_IOCFG19_IOSTR_S 8 +#define IOC_IOCFG19_IOSTR_MAX 0x00000300 +#define IOC_IOCFG19_IOSTR_MED 0x00000200 +#define IOC_IOCFG19_IOSTR_MIN 0x00000100 +#define IOC_IOCFG19_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO19 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG19_PORT_ID_W 6 +#define IOC_IOCFG19_PORT_ID_M 0x0000003F +#define IOC_IOCFG19_PORT_ID_S 0 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG20 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG20_HYST_EN 0x40000000 +#define IOC_IOCFG20_HYST_EN_BITN 30 +#define IOC_IOCFG20_HYST_EN_M 0x40000000 +#define IOC_IOCFG20_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG20_IE 0x20000000 +#define IOC_IOCFG20_IE_BITN 29 +#define IOC_IOCFG20_IE_M 0x20000000 +#define IOC_IOCFG20_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG20_WU_CFG_W 2 +#define IOC_IOCFG20_WU_CFG_M 0x18000000 +#define IOC_IOCFG20_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG20_IOMODE_W 3 +#define IOC_IOCFG20_IOMODE_M 0x07000000 +#define IOC_IOCFG20_IOMODE_S 24 +#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG20_IOMODE_INV 0x01000000 +#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG20_EDGE_DET_W 2 +#define IOC_IOCFG20_EDGE_DET_M 0x00030000 +#define IOC_IOCFG20_EDGE_DET_S 16 +#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG20_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG20_PULL_CTL_W 2 +#define IOC_IOCFG20_PULL_CTL_M 0x00006000 +#define IOC_IOCFG20_PULL_CTL_S 13 +#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG20_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG20_SLEW_RED 0x00001000 +#define IOC_IOCFG20_SLEW_RED_BITN 12 +#define IOC_IOCFG20_SLEW_RED_M 0x00001000 +#define IOC_IOCFG20_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG20_IOCURR_W 2 +#define IOC_IOCFG20_IOCURR_M 0x00000C00 +#define IOC_IOCFG20_IOCURR_S 10 +#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG20_IOCURR_4MA 0x00000400 +#define IOC_IOCFG20_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG20_IOSTR_W 2 +#define IOC_IOCFG20_IOSTR_M 0x00000300 +#define IOC_IOCFG20_IOSTR_S 8 +#define IOC_IOCFG20_IOSTR_MAX 0x00000300 +#define IOC_IOCFG20_IOSTR_MED 0x00000200 +#define IOC_IOCFG20_IOSTR_MIN 0x00000100 +#define IOC_IOCFG20_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO20 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG20_PORT_ID_W 6 +#define IOC_IOCFG20_PORT_ID_M 0x0000003F +#define IOC_IOCFG20_PORT_ID_S 0 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG21 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG21_HYST_EN 0x40000000 +#define IOC_IOCFG21_HYST_EN_BITN 30 +#define IOC_IOCFG21_HYST_EN_M 0x40000000 +#define IOC_IOCFG21_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG21_IE 0x20000000 +#define IOC_IOCFG21_IE_BITN 29 +#define IOC_IOCFG21_IE_M 0x20000000 +#define IOC_IOCFG21_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG21_WU_CFG_W 2 +#define IOC_IOCFG21_WU_CFG_M 0x18000000 +#define IOC_IOCFG21_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG21_IOMODE_W 3 +#define IOC_IOCFG21_IOMODE_M 0x07000000 +#define IOC_IOCFG21_IOMODE_S 24 +#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG21_IOMODE_INV 0x01000000 +#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG21_EDGE_DET_W 2 +#define IOC_IOCFG21_EDGE_DET_M 0x00030000 +#define IOC_IOCFG21_EDGE_DET_S 16 +#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG21_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG21_PULL_CTL_W 2 +#define IOC_IOCFG21_PULL_CTL_M 0x00006000 +#define IOC_IOCFG21_PULL_CTL_S 13 +#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG21_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG21_SLEW_RED 0x00001000 +#define IOC_IOCFG21_SLEW_RED_BITN 12 +#define IOC_IOCFG21_SLEW_RED_M 0x00001000 +#define IOC_IOCFG21_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG21_IOCURR_W 2 +#define IOC_IOCFG21_IOCURR_M 0x00000C00 +#define IOC_IOCFG21_IOCURR_S 10 +#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG21_IOCURR_4MA 0x00000400 +#define IOC_IOCFG21_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG21_IOSTR_W 2 +#define IOC_IOCFG21_IOSTR_M 0x00000300 +#define IOC_IOCFG21_IOSTR_S 8 +#define IOC_IOCFG21_IOSTR_MAX 0x00000300 +#define IOC_IOCFG21_IOSTR_MED 0x00000200 +#define IOC_IOCFG21_IOSTR_MIN 0x00000100 +#define IOC_IOCFG21_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO21 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG21_PORT_ID_W 6 +#define IOC_IOCFG21_PORT_ID_M 0x0000003F +#define IOC_IOCFG21_PORT_ID_S 0 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG22 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG22_HYST_EN 0x40000000 +#define IOC_IOCFG22_HYST_EN_BITN 30 +#define IOC_IOCFG22_HYST_EN_M 0x40000000 +#define IOC_IOCFG22_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG22_IE 0x20000000 +#define IOC_IOCFG22_IE_BITN 29 +#define IOC_IOCFG22_IE_M 0x20000000 +#define IOC_IOCFG22_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG22_WU_CFG_W 2 +#define IOC_IOCFG22_WU_CFG_M 0x18000000 +#define IOC_IOCFG22_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG22_IOMODE_W 3 +#define IOC_IOCFG22_IOMODE_M 0x07000000 +#define IOC_IOCFG22_IOMODE_S 24 +#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG22_IOMODE_INV 0x01000000 +#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG22_EDGE_DET_W 2 +#define IOC_IOCFG22_EDGE_DET_M 0x00030000 +#define IOC_IOCFG22_EDGE_DET_S 16 +#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG22_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG22_PULL_CTL_W 2 +#define IOC_IOCFG22_PULL_CTL_M 0x00006000 +#define IOC_IOCFG22_PULL_CTL_S 13 +#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG22_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG22_SLEW_RED 0x00001000 +#define IOC_IOCFG22_SLEW_RED_BITN 12 +#define IOC_IOCFG22_SLEW_RED_M 0x00001000 +#define IOC_IOCFG22_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG22_IOCURR_W 2 +#define IOC_IOCFG22_IOCURR_M 0x00000C00 +#define IOC_IOCFG22_IOCURR_S 10 +#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG22_IOCURR_4MA 0x00000400 +#define IOC_IOCFG22_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG22_IOSTR_W 2 +#define IOC_IOCFG22_IOSTR_M 0x00000300 +#define IOC_IOCFG22_IOSTR_S 8 +#define IOC_IOCFG22_IOSTR_MAX 0x00000300 +#define IOC_IOCFG22_IOSTR_MED 0x00000200 +#define IOC_IOCFG22_IOSTR_MIN 0x00000100 +#define IOC_IOCFG22_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO22 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG22_PORT_ID_W 6 +#define IOC_IOCFG22_PORT_ID_M 0x0000003F +#define IOC_IOCFG22_PORT_ID_S 0 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG23 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG23_HYST_EN 0x40000000 +#define IOC_IOCFG23_HYST_EN_BITN 30 +#define IOC_IOCFG23_HYST_EN_M 0x40000000 +#define IOC_IOCFG23_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG23_IE 0x20000000 +#define IOC_IOCFG23_IE_BITN 29 +#define IOC_IOCFG23_IE_M 0x20000000 +#define IOC_IOCFG23_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG23_WU_CFG_W 2 +#define IOC_IOCFG23_WU_CFG_M 0x18000000 +#define IOC_IOCFG23_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG23_IOMODE_W 3 +#define IOC_IOCFG23_IOMODE_M 0x07000000 +#define IOC_IOCFG23_IOMODE_S 24 +#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG23_IOMODE_INV 0x01000000 +#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG23_EDGE_DET_W 2 +#define IOC_IOCFG23_EDGE_DET_M 0x00030000 +#define IOC_IOCFG23_EDGE_DET_S 16 +#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG23_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG23_PULL_CTL_W 2 +#define IOC_IOCFG23_PULL_CTL_M 0x00006000 +#define IOC_IOCFG23_PULL_CTL_S 13 +#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG23_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG23_SLEW_RED 0x00001000 +#define IOC_IOCFG23_SLEW_RED_BITN 12 +#define IOC_IOCFG23_SLEW_RED_M 0x00001000 +#define IOC_IOCFG23_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG23_IOCURR_W 2 +#define IOC_IOCFG23_IOCURR_M 0x00000C00 +#define IOC_IOCFG23_IOCURR_S 10 +#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG23_IOCURR_4MA 0x00000400 +#define IOC_IOCFG23_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG23_IOSTR_W 2 +#define IOC_IOCFG23_IOSTR_M 0x00000300 +#define IOC_IOCFG23_IOSTR_S 8 +#define IOC_IOCFG23_IOSTR_MAX 0x00000300 +#define IOC_IOCFG23_IOSTR_MED 0x00000200 +#define IOC_IOCFG23_IOSTR_MIN 0x00000100 +#define IOC_IOCFG23_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO23 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG23_PORT_ID_W 6 +#define IOC_IOCFG23_PORT_ID_M 0x0000003F +#define IOC_IOCFG23_PORT_ID_S 0 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG24 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG24_HYST_EN 0x40000000 +#define IOC_IOCFG24_HYST_EN_BITN 30 +#define IOC_IOCFG24_HYST_EN_M 0x40000000 +#define IOC_IOCFG24_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG24_IE 0x20000000 +#define IOC_IOCFG24_IE_BITN 29 +#define IOC_IOCFG24_IE_M 0x20000000 +#define IOC_IOCFG24_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG24_WU_CFG_W 2 +#define IOC_IOCFG24_WU_CFG_M 0x18000000 +#define IOC_IOCFG24_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG24_IOMODE_W 3 +#define IOC_IOCFG24_IOMODE_M 0x07000000 +#define IOC_IOCFG24_IOMODE_S 24 +#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG24_IOMODE_INV 0x01000000 +#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG24_EDGE_DET_W 2 +#define IOC_IOCFG24_EDGE_DET_M 0x00030000 +#define IOC_IOCFG24_EDGE_DET_S 16 +#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG24_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG24_PULL_CTL_W 2 +#define IOC_IOCFG24_PULL_CTL_M 0x00006000 +#define IOC_IOCFG24_PULL_CTL_S 13 +#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG24_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG24_SLEW_RED 0x00001000 +#define IOC_IOCFG24_SLEW_RED_BITN 12 +#define IOC_IOCFG24_SLEW_RED_M 0x00001000 +#define IOC_IOCFG24_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG24_IOCURR_W 2 +#define IOC_IOCFG24_IOCURR_M 0x00000C00 +#define IOC_IOCFG24_IOCURR_S 10 +#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG24_IOCURR_4MA 0x00000400 +#define IOC_IOCFG24_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG24_IOSTR_W 2 +#define IOC_IOCFG24_IOSTR_M 0x00000300 +#define IOC_IOCFG24_IOSTR_S 8 +#define IOC_IOCFG24_IOSTR_MAX 0x00000300 +#define IOC_IOCFG24_IOSTR_MED 0x00000200 +#define IOC_IOCFG24_IOSTR_MIN 0x00000100 +#define IOC_IOCFG24_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO24 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG24_PORT_ID_W 6 +#define IOC_IOCFG24_PORT_ID_M 0x0000003F +#define IOC_IOCFG24_PORT_ID_S 0 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG25 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG25_HYST_EN 0x40000000 +#define IOC_IOCFG25_HYST_EN_BITN 30 +#define IOC_IOCFG25_HYST_EN_M 0x40000000 +#define IOC_IOCFG25_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG25_IE 0x20000000 +#define IOC_IOCFG25_IE_BITN 29 +#define IOC_IOCFG25_IE_M 0x20000000 +#define IOC_IOCFG25_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG25_WU_CFG_W 2 +#define IOC_IOCFG25_WU_CFG_M 0x18000000 +#define IOC_IOCFG25_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG25_IOMODE_W 3 +#define IOC_IOCFG25_IOMODE_M 0x07000000 +#define IOC_IOCFG25_IOMODE_S 24 +#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG25_IOMODE_INV 0x01000000 +#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG25_EDGE_DET_W 2 +#define IOC_IOCFG25_EDGE_DET_M 0x00030000 +#define IOC_IOCFG25_EDGE_DET_S 16 +#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG25_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG25_PULL_CTL_W 2 +#define IOC_IOCFG25_PULL_CTL_M 0x00006000 +#define IOC_IOCFG25_PULL_CTL_S 13 +#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG25_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG25_SLEW_RED 0x00001000 +#define IOC_IOCFG25_SLEW_RED_BITN 12 +#define IOC_IOCFG25_SLEW_RED_M 0x00001000 +#define IOC_IOCFG25_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG25_IOCURR_W 2 +#define IOC_IOCFG25_IOCURR_M 0x00000C00 +#define IOC_IOCFG25_IOCURR_S 10 +#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG25_IOCURR_4MA 0x00000400 +#define IOC_IOCFG25_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG25_IOSTR_W 2 +#define IOC_IOCFG25_IOSTR_M 0x00000300 +#define IOC_IOCFG25_IOSTR_S 8 +#define IOC_IOCFG25_IOSTR_MAX 0x00000300 +#define IOC_IOCFG25_IOSTR_MED 0x00000200 +#define IOC_IOCFG25_IOSTR_MIN 0x00000100 +#define IOC_IOCFG25_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO25 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG25_PORT_ID_W 6 +#define IOC_IOCFG25_PORT_ID_M 0x0000003F +#define IOC_IOCFG25_PORT_ID_S 0 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG26 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG26_HYST_EN 0x40000000 +#define IOC_IOCFG26_HYST_EN_BITN 30 +#define IOC_IOCFG26_HYST_EN_M 0x40000000 +#define IOC_IOCFG26_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG26_IE 0x20000000 +#define IOC_IOCFG26_IE_BITN 29 +#define IOC_IOCFG26_IE_M 0x20000000 +#define IOC_IOCFG26_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG26_WU_CFG_W 2 +#define IOC_IOCFG26_WU_CFG_M 0x18000000 +#define IOC_IOCFG26_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG26_IOMODE_W 3 +#define IOC_IOCFG26_IOMODE_M 0x07000000 +#define IOC_IOCFG26_IOMODE_S 24 +#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG26_IOMODE_INV 0x01000000 +#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG26_EDGE_DET_W 2 +#define IOC_IOCFG26_EDGE_DET_M 0x00030000 +#define IOC_IOCFG26_EDGE_DET_S 16 +#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG26_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG26_PULL_CTL_W 2 +#define IOC_IOCFG26_PULL_CTL_M 0x00006000 +#define IOC_IOCFG26_PULL_CTL_S 13 +#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG26_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG26_SLEW_RED 0x00001000 +#define IOC_IOCFG26_SLEW_RED_BITN 12 +#define IOC_IOCFG26_SLEW_RED_M 0x00001000 +#define IOC_IOCFG26_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG26_IOCURR_W 2 +#define IOC_IOCFG26_IOCURR_M 0x00000C00 +#define IOC_IOCFG26_IOCURR_S 10 +#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG26_IOCURR_4MA 0x00000400 +#define IOC_IOCFG26_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG26_IOSTR_W 2 +#define IOC_IOCFG26_IOSTR_M 0x00000300 +#define IOC_IOCFG26_IOSTR_S 8 +#define IOC_IOCFG26_IOSTR_MAX 0x00000300 +#define IOC_IOCFG26_IOSTR_MED 0x00000200 +#define IOC_IOCFG26_IOSTR_MIN 0x00000100 +#define IOC_IOCFG26_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO26 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG26_PORT_ID_W 6 +#define IOC_IOCFG26_PORT_ID_M 0x0000003F +#define IOC_IOCFG26_PORT_ID_S 0 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG27 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG27_HYST_EN 0x40000000 +#define IOC_IOCFG27_HYST_EN_BITN 30 +#define IOC_IOCFG27_HYST_EN_M 0x40000000 +#define IOC_IOCFG27_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG27_IE 0x20000000 +#define IOC_IOCFG27_IE_BITN 29 +#define IOC_IOCFG27_IE_M 0x20000000 +#define IOC_IOCFG27_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG27_WU_CFG_W 2 +#define IOC_IOCFG27_WU_CFG_M 0x18000000 +#define IOC_IOCFG27_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG27_IOMODE_W 3 +#define IOC_IOCFG27_IOMODE_M 0x07000000 +#define IOC_IOCFG27_IOMODE_S 24 +#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG27_IOMODE_INV 0x01000000 +#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG27_EDGE_DET_W 2 +#define IOC_IOCFG27_EDGE_DET_M 0x00030000 +#define IOC_IOCFG27_EDGE_DET_S 16 +#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG27_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG27_PULL_CTL_W 2 +#define IOC_IOCFG27_PULL_CTL_M 0x00006000 +#define IOC_IOCFG27_PULL_CTL_S 13 +#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG27_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG27_SLEW_RED 0x00001000 +#define IOC_IOCFG27_SLEW_RED_BITN 12 +#define IOC_IOCFG27_SLEW_RED_M 0x00001000 +#define IOC_IOCFG27_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG27_IOCURR_W 2 +#define IOC_IOCFG27_IOCURR_M 0x00000C00 +#define IOC_IOCFG27_IOCURR_S 10 +#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG27_IOCURR_4MA 0x00000400 +#define IOC_IOCFG27_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG27_IOSTR_W 2 +#define IOC_IOCFG27_IOSTR_M 0x00000300 +#define IOC_IOCFG27_IOSTR_S 8 +#define IOC_IOCFG27_IOSTR_MAX 0x00000300 +#define IOC_IOCFG27_IOSTR_MED 0x00000200 +#define IOC_IOCFG27_IOSTR_MIN 0x00000100 +#define IOC_IOCFG27_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO27 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG27_PORT_ID_W 6 +#define IOC_IOCFG27_PORT_ID_M 0x0000003F +#define IOC_IOCFG27_PORT_ID_S 0 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG28 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG28_HYST_EN 0x40000000 +#define IOC_IOCFG28_HYST_EN_BITN 30 +#define IOC_IOCFG28_HYST_EN_M 0x40000000 +#define IOC_IOCFG28_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG28_IE 0x20000000 +#define IOC_IOCFG28_IE_BITN 29 +#define IOC_IOCFG28_IE_M 0x20000000 +#define IOC_IOCFG28_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG28_WU_CFG_W 2 +#define IOC_IOCFG28_WU_CFG_M 0x18000000 +#define IOC_IOCFG28_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG28_IOMODE_W 3 +#define IOC_IOCFG28_IOMODE_M 0x07000000 +#define IOC_IOCFG28_IOMODE_S 24 +#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG28_IOMODE_INV 0x01000000 +#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG28_EDGE_DET_W 2 +#define IOC_IOCFG28_EDGE_DET_M 0x00030000 +#define IOC_IOCFG28_EDGE_DET_S 16 +#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG28_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG28_PULL_CTL_W 2 +#define IOC_IOCFG28_PULL_CTL_M 0x00006000 +#define IOC_IOCFG28_PULL_CTL_S 13 +#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG28_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG28_SLEW_RED 0x00001000 +#define IOC_IOCFG28_SLEW_RED_BITN 12 +#define IOC_IOCFG28_SLEW_RED_M 0x00001000 +#define IOC_IOCFG28_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG28_IOCURR_W 2 +#define IOC_IOCFG28_IOCURR_M 0x00000C00 +#define IOC_IOCFG28_IOCURR_S 10 +#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG28_IOCURR_4MA 0x00000400 +#define IOC_IOCFG28_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG28_IOSTR_W 2 +#define IOC_IOCFG28_IOSTR_M 0x00000300 +#define IOC_IOCFG28_IOSTR_S 8 +#define IOC_IOCFG28_IOSTR_MAX 0x00000300 +#define IOC_IOCFG28_IOSTR_MED 0x00000200 +#define IOC_IOCFG28_IOSTR_MIN 0x00000100 +#define IOC_IOCFG28_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO28 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG28_PORT_ID_W 6 +#define IOC_IOCFG28_PORT_ID_M 0x0000003F +#define IOC_IOCFG28_PORT_ID_S 0 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG29 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG29_HYST_EN 0x40000000 +#define IOC_IOCFG29_HYST_EN_BITN 30 +#define IOC_IOCFG29_HYST_EN_M 0x40000000 +#define IOC_IOCFG29_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG29_IE 0x20000000 +#define IOC_IOCFG29_IE_BITN 29 +#define IOC_IOCFG29_IE_M 0x20000000 +#define IOC_IOCFG29_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG29_WU_CFG_W 2 +#define IOC_IOCFG29_WU_CFG_M 0x18000000 +#define IOC_IOCFG29_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG29_IOMODE_W 3 +#define IOC_IOCFG29_IOMODE_M 0x07000000 +#define IOC_IOCFG29_IOMODE_S 24 +#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG29_IOMODE_INV 0x01000000 +#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG29_EDGE_DET_W 2 +#define IOC_IOCFG29_EDGE_DET_M 0x00030000 +#define IOC_IOCFG29_EDGE_DET_S 16 +#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG29_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG29_PULL_CTL_W 2 +#define IOC_IOCFG29_PULL_CTL_M 0x00006000 +#define IOC_IOCFG29_PULL_CTL_S 13 +#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG29_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG29_SLEW_RED 0x00001000 +#define IOC_IOCFG29_SLEW_RED_BITN 12 +#define IOC_IOCFG29_SLEW_RED_M 0x00001000 +#define IOC_IOCFG29_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG29_IOCURR_W 2 +#define IOC_IOCFG29_IOCURR_M 0x00000C00 +#define IOC_IOCFG29_IOCURR_S 10 +#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG29_IOCURR_4MA 0x00000400 +#define IOC_IOCFG29_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG29_IOSTR_W 2 +#define IOC_IOCFG29_IOSTR_M 0x00000300 +#define IOC_IOCFG29_IOSTR_S 8 +#define IOC_IOCFG29_IOSTR_MAX 0x00000300 +#define IOC_IOCFG29_IOSTR_MED 0x00000200 +#define IOC_IOCFG29_IOSTR_MIN 0x00000100 +#define IOC_IOCFG29_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO29 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG29_PORT_ID_W 6 +#define IOC_IOCFG29_PORT_ID_M 0x0000003F +#define IOC_IOCFG29_PORT_ID_S 0 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG30 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG30_HYST_EN 0x40000000 +#define IOC_IOCFG30_HYST_EN_BITN 30 +#define IOC_IOCFG30_HYST_EN_M 0x40000000 +#define IOC_IOCFG30_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG30_IE 0x20000000 +#define IOC_IOCFG30_IE_BITN 29 +#define IOC_IOCFG30_IE_M 0x20000000 +#define IOC_IOCFG30_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG30_WU_CFG_W 2 +#define IOC_IOCFG30_WU_CFG_M 0x18000000 +#define IOC_IOCFG30_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG30_IOMODE_W 3 +#define IOC_IOCFG30_IOMODE_M 0x07000000 +#define IOC_IOCFG30_IOMODE_S 24 +#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG30_IOMODE_INV 0x01000000 +#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG30_EDGE_DET_W 2 +#define IOC_IOCFG30_EDGE_DET_M 0x00030000 +#define IOC_IOCFG30_EDGE_DET_S 16 +#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG30_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG30_PULL_CTL_W 2 +#define IOC_IOCFG30_PULL_CTL_M 0x00006000 +#define IOC_IOCFG30_PULL_CTL_S 13 +#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG30_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG30_SLEW_RED 0x00001000 +#define IOC_IOCFG30_SLEW_RED_BITN 12 +#define IOC_IOCFG30_SLEW_RED_M 0x00001000 +#define IOC_IOCFG30_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG30_IOCURR_W 2 +#define IOC_IOCFG30_IOCURR_M 0x00000C00 +#define IOC_IOCFG30_IOCURR_S 10 +#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG30_IOCURR_4MA 0x00000400 +#define IOC_IOCFG30_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG30_IOSTR_W 2 +#define IOC_IOCFG30_IOSTR_M 0x00000300 +#define IOC_IOCFG30_IOSTR_S 8 +#define IOC_IOCFG30_IOSTR_MAX 0x00000300 +#define IOC_IOCFG30_IOSTR_MED 0x00000200 +#define IOC_IOCFG30_IOSTR_MIN 0x00000100 +#define IOC_IOCFG30_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO30 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG30_PORT_ID_W 6 +#define IOC_IOCFG30_PORT_ID_M 0x0000003F +#define IOC_IOCFG30_PORT_ID_S 0 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG31 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG31_HYST_EN 0x40000000 +#define IOC_IOCFG31_HYST_EN_BITN 30 +#define IOC_IOCFG31_HYST_EN_M 0x40000000 +#define IOC_IOCFG31_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG31_IE 0x20000000 +#define IOC_IOCFG31_IE_BITN 29 +#define IOC_IOCFG31_IE_M 0x20000000 +#define IOC_IOCFG31_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 +// or >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX ie. PORT_ID +// 0x01-0x08, this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG31_WU_CFG_W 2 +#define IOC_IOCFG31_WU_CFG_M 0x18000000 +#define IOC_IOCFG31_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG31_IOMODE_W 3 +#define IOC_IOCFG31_IOMODE_M 0x07000000 +#define IOC_IOCFG31_IOMODE_S 24 +#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG31_IOMODE_INV 0x01000000 +#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG31_EDGE_DET_W 2 +#define IOC_IOCFG31_EDGE_DET_M 0x00030000 +#define IOC_IOCFG31_EDGE_DET_S 16 +#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG31_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG31_PULL_CTL_W 2 +#define IOC_IOCFG31_PULL_CTL_M 0x00006000 +#define IOC_IOCFG31_PULL_CTL_S 13 +#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG31_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG31_SLEW_RED 0x00001000 +#define IOC_IOCFG31_SLEW_RED_BITN 12 +#define IOC_IOCFG31_SLEW_RED_M 0x00001000 +#define IOC_IOCFG31_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG31_IOCURR_W 2 +#define IOC_IOCFG31_IOCURR_M 0x00000C00 +#define IOC_IOCFG31_IOCURR_S 10 +#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG31_IOCURR_4MA 0x00000400 +#define IOC_IOCFG31_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG31_IOSTR_W 2 +#define IOC_IOCFG31_IOSTR_M 0x00000300 +#define IOC_IOCFG31_IOSTR_S 8 +#define IOC_IOCFG31_IOSTR_MAX 0x00000300 +#define IOC_IOCFG31_IOSTR_MED 0x00000200 +#define IOC_IOCFG31_IOSTR_MIN 0x00000100 +#define IOC_IOCFG31_IOSTR_AUTO 0x00000000 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO31 +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it via registers +// in the EVENT module, e.g. +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// etc +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG31_PORT_ID_W 6 +#define IOC_IOCFG31_PORT_ID_M 0x0000003F +#define IOC_IOCFG31_PORT_ID_S 0 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 + + +#endif // __IOC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_memmap.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_memmap.h new file mode 100644 index 0000000..6377d81 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_memmap.h @@ -0,0 +1,158 @@ +/****************************************************************************** +* Filename: hw_memmap_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals on the CPU_MMAP interface +// +//***************************************************************************** +#define FLASHMEM_BASE 0x00000000 // FLASHMEM +#define BROM_BASE 0x10000000 // BROM +#define GPRAM_BASE 0x11000000 // GPRAM +#define SRAM_BASE 0x20000000 // SRAM +#define RFC_RAM_BASE 0x21000000 // RFC_RAM +#define SSI0_BASE 0x40000000 // SSI +#define UART0_BASE 0x40001000 // UART +#define I2C0_BASE 0x40002000 // I2C +#define SSI1_BASE 0x40008000 // SSI +#define GPT0_BASE 0x40010000 // GPT +#define GPT1_BASE 0x40011000 // GPT +#define GPT2_BASE 0x40012000 // GPT +#define GPT3_BASE 0x40013000 // GPT +#define UDMA0_BASE 0x40020000 // UDMA +#define I2S0_BASE 0x40021000 // I2S +#define GPIO_BASE 0x40022000 // GPIO +#define CRYPTO_BASE 0x40024000 // CRYPTO +#define TRNG_BASE 0x40028000 // TRNG +#define FLASH_BASE 0x40030000 // FLASH +#define VIMS_BASE 0x40034000 // VIMS +#define RFC_PWR_BASE 0x40040000 // RFC_PWR +#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL +#define RFC_RAT_BASE 0x40043000 // RFC_RAT +#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA +#define WDT_BASE 0x40080000 // WDT +#define IOC_BASE 0x40081000 // IOC +#define PRCM_BASE 0x40082000 // PRCM +#define EVENT_BASE 0x40083000 // EVENT +#define SMPH_BASE 0x40084000 // SMPH +#define ADI2_BASE 0x40086000 // ADI +#define ADI3_BASE 0x40086200 // ADI +#define AON_SYSCTL_BASE 0x40090000 // AON_SYSCTL +#define AON_WUC_BASE 0x40091000 // AON_WUC +#define AON_RTC_BASE 0x40092000 // AON_RTC +#define AON_EVENT_BASE 0x40093000 // AON_EVENT +#define AON_IOC_BASE 0x40094000 // AON_IOC +#define AON_BATMON_BASE 0x40095000 // AON_BATMON +#define AUX_AIODIO0_BASE 0x400C1000 // AUX_AIODIO +#define AUX_AIODIO1_BASE 0x400C2000 // AUX_AIODIO +#define AUX_TDC_BASE 0x400C4000 // AUX_TDC +#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL +#define AUX_WUC_BASE 0x400C6000 // AUX_WUC +#define AUX_TIMER_BASE 0x400C7000 // AUX_TIMER +#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH +#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF +#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI +#define AUX_ADI4_BASE 0x400CB000 // ADI +#define AUX_RAM_BASE 0x400E0000 // AUX_RAM +#define AUX_SCE_BASE 0x400E1000 // AUX_SCE +#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP +#define FCFG1_BASE 0x50001000 // FCFG1 +#define FCFG2_BASE 0x50002000 // FCFG2 +#ifndef CCFG_BASE +#define CCFG_BASE 0x50003000 // CCFG +#endif +#define CCFG_BASE_DEFAULT 0x50003000 // CCFG +#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base +#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base +#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base +#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base +#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base +#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base +#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base +#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base +#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base +#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base +#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base +#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base +#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base +#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base +#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base +#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base +#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base +#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base +#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base +#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base +#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base +#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base +#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base +#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base +#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base +#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base +#define AON_SYSCTL_NONBUF_BASE 0x60090000 // AON_SYSCTL CPU nonbuf base +#define AON_WUC_NONBUF_BASE 0x60091000 // AON_WUC CPU nonbuf base +#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base +#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base +#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base +#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base +#define AUX_AIODIO0_NONBUF_BASE \ + 0x600C1000 // AUX_AIODIO CPU nonbuf base +#define AUX_AIODIO1_NONBUF_BASE \ + 0x600C2000 // AUX_AIODIO CPU nonbuf base +#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base +#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base +#define AUX_WUC_NONBUF_BASE 0x600C6000 // AUX_WUC CPU nonbuf base +#define AUX_TIMER_NONBUF_BASE 0x600C7000 // AUX_TIMER CPU nonbuf base +#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base +#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base +#define AUX_DDI0_OSC_NONBUF_BASE \ + 0x600CA000 // DDI CPU nonbuf base +#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base +#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base +#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base +#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base +#define CPU_ITM_BASE 0xE0000000 // CPU_ITM +#define CPU_DWT_BASE 0xE0001000 // CPU_DWT +#define CPU_FPB_BASE 0xE0002000 // CPU_FPB +#define CPU_SCS_BASE 0xE000E000 // CPU_SCS +#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU +#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP +#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE + +#endif // __HW_MEMMAP__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_nvic.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_nvic.h new file mode 100644 index 0000000..3bdeb8b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_nvic.h @@ -0,0 +1,1026 @@ +/****************************************************************************** +* Filename: hw_nvic.h +* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) +* Revision: 42365 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number +#undef NVIC_INT_CTRL_VEC_PEN_M +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number +#undef NVIC_INT_CTRL_VEC_ACT_M +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset +#undef NVIC_VTABLE_OFFSET_M +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 9 +#undef NVIC_VTABLE_OFFSET_S +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_prcm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_prcm.h new file mode 100644 index 0000000..7974ad0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_prcm.h @@ -0,0 +1,1636 @@ +/****************************************************************************** +* Filename: hw_prcm_h +* Revised: 2017-09-14 10:33:07 +0200 (Thu, 14 Sep 2017) +* Revision: 49733 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_PRCM_H__ +#define __HW_PRCM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// PRCM component +// +//***************************************************************************** +// Infrastructure Clock Division Factor For Run Mode +#define PRCM_O_INFRCLKDIVR 0x00000000 + +// Infrastructure Clock Division Factor For Sleep Mode +#define PRCM_O_INFRCLKDIVS 0x00000004 + +// Infrastructure Clock Division Factor For DeepSleep Mode +#define PRCM_O_INFRCLKDIVDS 0x00000008 + +// MCU Voltage Domain Control +#define PRCM_O_VDCTL 0x0000000C + +// Load PRCM Settings To CLKCTRL Power Domain +#define PRCM_O_CLKLOADCTL 0x00000028 + +// RFC Clock Gate +#define PRCM_O_RFCCLKG 0x0000002C + +// VIMS Clock Gate +#define PRCM_O_VIMSCLKG 0x00000030 + +// TRNG, CRYPTO And UDMA Clock Gate For Run Mode +#define PRCM_O_SECDMACLKGR 0x0000003C + +// TRNG, CRYPTO And UDMA Clock Gate For Sleep Mode +#define PRCM_O_SECDMACLKGS 0x00000040 + +// TRNG, CRYPTO And UDMA Clock Gate For Deep Sleep Mode +#define PRCM_O_SECDMACLKGDS 0x00000044 + +// GPIO Clock Gate For Run Mode +#define PRCM_O_GPIOCLKGR 0x00000048 + +// GPIO Clock Gate For Sleep Mode +#define PRCM_O_GPIOCLKGS 0x0000004C + +// GPIO Clock Gate For Deep Sleep Mode +#define PRCM_O_GPIOCLKGDS 0x00000050 + +// GPT Clock Gate For Run Mode +#define PRCM_O_GPTCLKGR 0x00000054 + +// GPT Clock Gate For Sleep Mode +#define PRCM_O_GPTCLKGS 0x00000058 + +// GPT Clock Gate For Deep Sleep Mode +#define PRCM_O_GPTCLKGDS 0x0000005C + +// I2C Clock Gate For Run Mode +#define PRCM_O_I2CCLKGR 0x00000060 + +// I2C Clock Gate For Sleep Mode +#define PRCM_O_I2CCLKGS 0x00000064 + +// I2C Clock Gate For Deep Sleep Mode +#define PRCM_O_I2CCLKGDS 0x00000068 + +// UART Clock Gate For Run Mode +#define PRCM_O_UARTCLKGR 0x0000006C + +// UART Clock Gate For Sleep Mode +#define PRCM_O_UARTCLKGS 0x00000070 + +// UART Clock Gate For Deep Sleep Mode +#define PRCM_O_UARTCLKGDS 0x00000074 + +// SSI Clock Gate For Run Mode +#define PRCM_O_SSICLKGR 0x00000078 + +// SSI Clock Gate For Sleep Mode +#define PRCM_O_SSICLKGS 0x0000007C + +// SSI Clock Gate For Deep Sleep Mode +#define PRCM_O_SSICLKGDS 0x00000080 + +// I2S Clock Gate For Run Mode +#define PRCM_O_I2SCLKGR 0x00000084 + +// I2S Clock Gate For Sleep Mode +#define PRCM_O_I2SCLKGS 0x00000088 + +// I2S Clock Gate For Deep Sleep Mode +#define PRCM_O_I2SCLKGDS 0x0000008C + +// Internal +#define PRCM_O_CPUCLKDIV 0x000000B8 + +// I2S Clock Control +#define PRCM_O_I2SBCLKSEL 0x000000C8 + +// GPT Scalar +#define PRCM_O_GPTCLKDIV 0x000000CC + +// I2S Clock Control +#define PRCM_O_I2SCLKCTL 0x000000D0 + +// MCLK Division Ratio +#define PRCM_O_I2SMCLKDIV 0x000000D4 + +// BCLK Division Ratio +#define PRCM_O_I2SBCLKDIV 0x000000D8 + +// WCLK Division Ratio +#define PRCM_O_I2SWCLKDIV 0x000000DC + +// SW Initiated Resets +#define PRCM_O_SWRESET 0x0000010C + +// WARM Reset Control And Status +#define PRCM_O_WARMRESET 0x00000110 + +// Power Domain Control +#define PRCM_O_PDCTL0 0x0000012C + +// RFC Power Domain Control +#define PRCM_O_PDCTL0RFC 0x00000130 + +// SERIAL Power Domain Control +#define PRCM_O_PDCTL0SERIAL 0x00000134 + +// PERIPH Power Domain Control +#define PRCM_O_PDCTL0PERIPH 0x00000138 + +// Power Domain Status +#define PRCM_O_PDSTAT0 0x00000140 + +// RFC Power Domain Status +#define PRCM_O_PDSTAT0RFC 0x00000144 + +// SERIAL Power Domain Status +#define PRCM_O_PDSTAT0SERIAL 0x00000148 + +// PERIPH Power Domain Status +#define PRCM_O_PDSTAT0PERIPH 0x0000014C + +// Power Domain Control +#define PRCM_O_PDCTL1 0x0000017C + +// CPU Power Domain Direct Control +#define PRCM_O_PDCTL1CPU 0x00000184 + +// RFC Power Domain Direct Control +#define PRCM_O_PDCTL1RFC 0x00000188 + +// VIMS Mode Direct Control +#define PRCM_O_PDCTL1VIMS 0x0000018C + +// Power Manager Status +#define PRCM_O_PDSTAT1 0x00000194 + +// BUS Power Domain Direct Read Status +#define PRCM_O_PDSTAT1BUS 0x00000198 + +// RFC Power Domain Direct Read Status +#define PRCM_O_PDSTAT1RFC 0x0000019C + +// CPU Power Domain Direct Read Status +#define PRCM_O_PDSTAT1CPU 0x000001A0 + +// VIMS Mode Direct Read Status +#define PRCM_O_PDSTAT1VIMS 0x000001A4 + +// Control To RFC +#define PRCM_O_RFCBITS 0x000001CC + +// Selected RFC Mode +#define PRCM_O_RFCMODESEL 0x000001D0 + +// Allowed RFC Modes +#define PRCM_O_RFCMODEHWOPT 0x000001D4 + +// Power Profiler Register +#define PRCM_O_PWRPROFSTAT 0x000001E0 + +// Memory Retention Control +#define PRCM_O_RAMRETEN 0x00000224 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVR +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in run mode. Division ratio affects both infrastructure clock and +// perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVR_RATIO_W 2 +#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_S 0 +#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVS +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in sleep mode. Division ratio affects both infrastructure clock and +// perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVS_RATIO_W 2 +#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_S 0 +#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVDS +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in seepsleep mode. Division ratio affects both infrastructure clock +// and perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVDS_RATIO_W 2 +#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_S 0 +#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_VDCTL +// +//***************************************************************************** +// Field: [2] MCU_VD +// +// Request WUC to power down the MCU voltage domain +// +// 0: No request +// 1: Assert request when possible. An asserted power down request will result +// in a boot of the MCU system when powered up again. +// +// The bit will have no effect before the following requirements are met: +// 1. PDCTL1.CPU_ON = 0 +// 2. PDCTL1.VIMS_MODE = 0 +// 3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded with +// CLKLOADCTL.LOAD) +// 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with +// CLKLOADCTL.LOAD) +// 5. RFC do no request access to BUS +// 6. System CPU in deepsleep +#define PRCM_VDCTL_MCU_VD 0x00000004 +#define PRCM_VDCTL_MCU_VD_BITN 2 +#define PRCM_VDCTL_MCU_VD_M 0x00000004 +#define PRCM_VDCTL_MCU_VD_S 2 + +// Field: [0] ULDO +// +// Request WUC to switch to uLDO. +// +// 0: No request +// 1: Assert request when possible +// +// The bit will have no effect before the following requirements are met: +// 1. PDCTL1.CPU_ON = 0 +// 2. PDCTL1.VIMS_MODE = 0 +// 3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded with +// CLKLOADCTL.LOAD) +// 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with +// CLKLOADCTL.LOAD) +// 5. RFC do no request access to BUS +// 6. System CPU in deepsleep +#define PRCM_VDCTL_ULDO 0x00000001 +#define PRCM_VDCTL_ULDO_BITN 0 +#define PRCM_VDCTL_ULDO_M 0x00000001 +#define PRCM_VDCTL_ULDO_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_CLKLOADCTL +// +//***************************************************************************** +// Field: [1] LOAD_DONE +// +// Status of LOAD. +// Will be cleared to 0 when any of the registers requiring a LOAD is written +// to, and be set to 1 when a LOAD is done. +// Note that writing no change to a register will result in the LOAD_DONE being +// cleared. +// +// 0 : One or more registers have been write accessed after last LOAD +// 1 : No registers are write accessed after last LOAD +#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 +#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_S 1 + +// Field: [0] LOAD +// +// 0: No action +// 1: Load settings to CLKCTRL. Bit is HW cleared. +// +// Multiple changes to settings may be done before LOAD is written once so all +// changes takes place at the same time. LOAD can also be done after single +// setting updates. +// +// Registers that needs to be followed by LOAD before settings being applied +// are: +// - RFCCLKG +// - VIMSCLKG +// - SECDMACLKGR +// - SECDMACLKGS +// - SECDMACLKGDS +// - GPIOCLKGR +// - GPIOCLKGS +// - GPIOCLKGDS +// - GPTCLKGR +// - GPTCLKGS +// - GPTCLKGDS +// - GPTCLKDIV +// - I2CCLKGR +// - I2CCLKGS +// - I2CCLKGDS +// - SSICLKGR +// - SSICLKGS +// - SSICLKGDS +// - UARTCLKGR +// - UARTCLKGS +// - UARTCLKGDS +// - I2SCLKGR +// - I2SCLKGS +// - I2SCLKGDS +// - I2SBCLKSEL +// - I2SCLKCTL +// - I2SMCLKDIV +// - I2SBCLKDIV +// - I2SWCLKDIV +#define PRCM_CLKLOADCTL_LOAD 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_BITN 0 +#define PRCM_CLKLOADCTL_LOAD_M 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCCLKG +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock if RFC power domain is on +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_RFCCLKG_CLK_EN 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_BITN 0 +#define PRCM_RFCCLKG_CLK_EN_M 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_VIMSCLKG +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 00: Disable clock +// 01: Disable clock when system CPU is in DeepSleep +// 11: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_VIMSCLKG_CLK_EN_W 2 +#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 +#define PRCM_VIMSCLKG_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGR +// +//***************************************************************************** +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGS +// +//***************************************************************************** +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGDS +// +//***************************************************************************** +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGR +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGR_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGR +// +//***************************************************************************** +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGR_CLK_EN_W 4 +#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGR_CLK_EN_S 0 +#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGS +// +//***************************************************************************** +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGS_CLK_EN_W 4 +#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGS_CLK_EN_S 0 +#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGDS +// +//***************************************************************************** +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGDS_CLK_EN_W 4 +#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGDS_CLK_EN_S 0 +#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGR +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGR_CLK_EN 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_BITN 0 +#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGR +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_UARTCLKGR_CLK_EN 0x00000001 +#define PRCM_UARTCLKGR_CLK_EN_BITN 0 +#define PRCM_UARTCLKGR_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_UARTCLKGS_CLK_EN 0x00000001 +#define PRCM_UARTCLKGS_CLK_EN_BITN 0 +#define PRCM_UARTCLKGS_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_UARTCLKGDS_CLK_EN 0x00000001 +#define PRCM_UARTCLKGDS_CLK_EN_BITN 0 +#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGR +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGR_CLK_EN_W 2 +#define PRCM_SSICLKGR_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGR_CLK_EN_S 0 +#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGS_CLK_EN_W 2 +#define PRCM_SSICLKGS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGS_CLK_EN_S 0 +#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGDS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGDS_CLK_EN_W 2 +#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGDS_CLK_EN_S 0 +#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGR +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGR_CLK_EN 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_BITN 0 +#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_CPUCLKDIV +// +//***************************************************************************** +// Field: [0] RATIO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DIV2 Internal. Only to be used through TI provided API. +// DIV1 Internal. Only to be used through TI provided API. +#define PRCM_CPUCLKDIV_RATIO 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_BITN 0 +#define PRCM_CPUCLKDIV_RATIO_M 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_S 0 +#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_I2SBCLKSEL +// +//***************************************************************************** +// Field: [0] SRC +// +// BCLK source selector +// +// 0: Use external BCLK +// 1: Use internally generated clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SBCLKSEL_SRC 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_BITN 0 +#define PRCM_I2SBCLKSEL_SRC_M 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKDIV +// +//***************************************************************************** +// Field: [3:0] RATIO +// +// Scalar used for GPTs. The division rate will be constant and ungated for Run +// / Sleep / DeepSleep mode. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// Other values are not supported. +// ENUMs: +// DIV256 Divide by 256 +// DIV128 Divide by 128 +// DIV64 Divide by 64 +// DIV32 Divide by 32 +// DIV16 Divide by 16 +// DIV8 Divide by 8 +// DIV4 Divide by 4 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_GPTCLKDIV_RATIO_W 4 +#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F +#define PRCM_GPTCLKDIV_RATIO_S 0 +#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKCTL +// +//***************************************************************************** +// Field: [3] SMPL_ON_POSEDGE +// +// On the I2S serial interface, data and WCLK is sampled and clocked out on +// opposite edges of BCLK. +// +// 0 - data and WCLK are sampled on the negative edge and clocked out on the +// positive edge. +// 1 - data and WCLK are sampled on the positive edge and clocked out on the +// negative edge. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 + +// Field: [2:1] WCLK_PHASE +// +// Decides how the WCLK division ratio is calculated and used to generate +// different duty cycles (See I2SWCLKDIV.WDIV). +// +// 0: Single phase +// 1: Dual phase +// 2: User Defined +// 3: Reserved/Undefined +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 +#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 +#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 + +// Field: [0] EN +// +// +// 0: MCLK, BCLK and WCLK will be static low +// 1: Enables the generation of MCLK, BCLK and WCLK +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_EN 0x00000001 +#define PRCM_I2SCLKCTL_EN_BITN 0 +#define PRCM_I2SCLKCTL_EN_M 0x00000001 +#define PRCM_I2SCLKCTL_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SMCLKDIV +// +//***************************************************************************** +// Field: [9:0] MDIV +// +// An unsigned factor of the division ratio used to generate MCLK [2-1024]: +// +// MCLK = MCUCLK/MDIV[Hz] +// MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined +// by AON_WUC:MCUCLK.PWR_DWN_SRC +// +// A value of 0 is interpreted as 1024. +// A value of 1 is invalid. +// If MDIV is odd the low phase of the clock is one MCUCLK period longer than +// the high phase. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SMCLKDIV_MDIV_W 10 +#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF +#define PRCM_I2SMCLKDIV_MDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SBCLKDIV +// +//***************************************************************************** +// Field: [9:0] BDIV +// +// An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: +// +// BCLK = MCUCLK/BDIV[Hz] +// MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined +// by AON_WUC:MCUCLK.PWR_DWN_SRC +// +// A value of 0 is interpreted as 1024. +// A value of 1 is invalid. +// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock +// is one MCUCLK period longer than the high phase. +// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the +// clock is one MCUCLK period longer than the low phase. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SBCLKDIV_BDIV_W 10 +#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF +#define PRCM_I2SBCLKDIV_BDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SWCLKDIV +// +//***************************************************************************** +// Field: [15:0] WDIV +// +// If I2SCLKCTL.WCLK_PHASE = 0, Single phase. +// WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK +// periods. +// +// WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] +// MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined +// by AON_WUC:MCUCLK.PWR_DWN_SRC +// +// If I2SCLKCTL.WCLK_PHASE = 1, Dual phase. +// Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK +// periods. +// +// WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] +// +// If I2SCLKCTL.WCLK_PHASE = 2, User defined. +// WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] +// (unsigned, [1-255]) BCLK periods. +// +// WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SWCLKDIV_WDIV_W 16 +#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF +#define PRCM_I2SWCLKDIV_WDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SWRESET +// +//***************************************************************************** +// Field: [2] MCU +// +// Internal. Only to be used through TI provided API. +#define PRCM_SWRESET_MCU 0x00000004 +#define PRCM_SWRESET_MCU_BITN 2 +#define PRCM_SWRESET_MCU_M 0x00000004 +#define PRCM_SWRESET_MCU_S 2 + +//***************************************************************************** +// +// Register: PRCM_O_WARMRESET +// +//***************************************************************************** +// Field: [2] WR_TO_PINRESET +// +// 0: No action +// 1: A warm system reset event triggered by the below listed sources will +// result in an emulated pin reset. +// +// Warm reset sources included: +// ICEPick sysreset +// System CPU reset request, CPU_SCS:AIRCR.SYSRESETREQ +// System CPU Lockup +// WDT timeout +// +// An active ICEPick block system reset will gate all sources except ICEPick +// sysreset +// +// SW can read AON_SYSCTL:RESETCTL.RESET_SRC to find the source of the last +// reset resulting in a full power up sequence. WARMRESET in this register is +// set in the scenario that WR_TO_PINRESET=1 and one of the above listed +// sources is triggered. +#define PRCM_WARMRESET_WR_TO_PINRESET 0x00000004 +#define PRCM_WARMRESET_WR_TO_PINRESET_BITN 2 +#define PRCM_WARMRESET_WR_TO_PINRESET_M 0x00000004 +#define PRCM_WARMRESET_WR_TO_PINRESET_S 2 + +// Field: [1] LOCKUP_STAT +// +// +// 0: No registred event +// 1: A system CPU LOCKUP event has occured since last SW clear of the +// register. +// +// A read of this register clears both WDT_STAT and LOCKUP_STAT. +#define PRCM_WARMRESET_LOCKUP_STAT 0x00000002 +#define PRCM_WARMRESET_LOCKUP_STAT_BITN 1 +#define PRCM_WARMRESET_LOCKUP_STAT_M 0x00000002 +#define PRCM_WARMRESET_LOCKUP_STAT_S 1 + +// Field: [0] WDT_STAT +// +// +// 0: No registered event +// 1: A WDT event has occured since last SW clear of the register. +// +// A read of this register clears both WDT_STAT and LOCKUP_STAT. +#define PRCM_WARMRESET_WDT_STAT 0x00000001 +#define PRCM_WARMRESET_WDT_STAT_BITN 0 +#define PRCM_WARMRESET_WDT_STAT_M 0x00000001 +#define PRCM_WARMRESET_WDT_STAT_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0 +// +//***************************************************************************** +// Field: [2] PERIPH_ON +// +// PERIPH Power domain. +// +// 0: PERIPH power domain is powered down +// 1: PERIPH power domain is powered up +#define PRCM_PDCTL0_PERIPH_ON 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_BITN 2 +#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_S 2 + +// Field: [1] SERIAL_ON +// +// SERIAL Power domain. +// +// 0: SERIAL power domain is powered down +// 1: SERIAL power domain is powered up +#define PRCM_PDCTL0_SERIAL_ON 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_BITN 1 +#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_S 1 + +// Field: [0] RFC_ON +// +// +// 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 +// 1: RFC power domain powered on +#define PRCM_PDCTL0_RFC_ON 0x00000001 +#define PRCM_PDCTL0_RFC_ON_BITN 0 +#define PRCM_PDCTL0_RFC_ON_M 0x00000001 +#define PRCM_PDCTL0_RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0RFC +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.RFC_ON +#define PRCM_PDCTL0RFC_ON 0x00000001 +#define PRCM_PDCTL0RFC_ON_BITN 0 +#define PRCM_PDCTL0RFC_ON_M 0x00000001 +#define PRCM_PDCTL0RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0SERIAL +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.SERIAL_ON +#define PRCM_PDCTL0SERIAL_ON 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_BITN 0 +#define PRCM_PDCTL0SERIAL_ON_M 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0PERIPH +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.PERIPH_ON +#define PRCM_PDCTL0PERIPH_ON 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_BITN 0 +#define PRCM_PDCTL0PERIPH_ON_M 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0 +// +//***************************************************************************** +// Field: [2] PERIPH_ON +// +// PERIPH Power domain. +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_PERIPH_ON 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_BITN 2 +#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_S 2 + +// Field: [1] SERIAL_ON +// +// SERIAL Power domain. +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_SERIAL_ON 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_BITN 1 +#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_S 1 + +// Field: [0] RFC_ON +// +// RFC Power domain +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_RFC_ON 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_BITN 0 +#define PRCM_PDSTAT0_RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0RFC +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.RFC_ON +#define PRCM_PDSTAT0RFC_ON 0x00000001 +#define PRCM_PDSTAT0RFC_ON_BITN 0 +#define PRCM_PDSTAT0RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0SERIAL +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.SERIAL_ON +#define PRCM_PDSTAT0SERIAL_ON 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_BITN 0 +#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0PERIPH +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.PERIPH_ON +#define PRCM_PDSTAT0PERIPH_ON 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_BITN 0 +#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1 +// +//***************************************************************************** +// Field: [3] VIMS_MODE +// +// +// 0: VIMS power domain is only powered when CPU power domain is powered. +// 1: VIMS power domain is powered whenever the BUS power domain is powered. +#define PRCM_PDCTL1_VIMS_MODE 0x00000008 +#define PRCM_PDCTL1_VIMS_MODE_BITN 3 +#define PRCM_PDCTL1_VIMS_MODE_M 0x00000008 +#define PRCM_PDCTL1_VIMS_MODE_S 3 + +// Field: [2] RFC_ON +// +// +// 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 +// 1: RFC power domain powered on +// +// Bit shall be used by RFC in autonomus mode but there is no HW restrictions +// fom system CPU to access the bit. +#define PRCM_PDCTL1_RFC_ON 0x00000004 +#define PRCM_PDCTL1_RFC_ON_BITN 2 +#define PRCM_PDCTL1_RFC_ON_M 0x00000004 +#define PRCM_PDCTL1_RFC_ON_S 2 + +// Field: [1] CPU_ON +// +// +// 0: Causes a power down of the CPU power domain when system CPU indicates it +// is idle. +// 1: Initiates power-on of the CPU power domain. +// +// This bit is automatically set by a WIC power-on event. +#define PRCM_PDCTL1_CPU_ON 0x00000002 +#define PRCM_PDCTL1_CPU_ON_BITN 1 +#define PRCM_PDCTL1_CPU_ON_M 0x00000002 +#define PRCM_PDCTL1_CPU_ON_S 1 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1CPU +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDCTL1.CPU_ON +#define PRCM_PDCTL1CPU_ON 0x00000001 +#define PRCM_PDCTL1CPU_ON_BITN 0 +#define PRCM_PDCTL1CPU_ON_M 0x00000001 +#define PRCM_PDCTL1CPU_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1RFC +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDCTL1.RFC_ON +#define PRCM_PDCTL1RFC_ON 0x00000001 +#define PRCM_PDCTL1RFC_ON_BITN 0 +#define PRCM_PDCTL1RFC_ON_M 0x00000001 +#define PRCM_PDCTL1RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1VIMS +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDCTL1.VIMS_MODE +#define PRCM_PDCTL1VIMS_ON 0x00000001 +#define PRCM_PDCTL1VIMS_ON_BITN 0 +#define PRCM_PDCTL1VIMS_ON_M 0x00000001 +#define PRCM_PDCTL1VIMS_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1 +// +//***************************************************************************** +// Field: [4] BUS_ON +// +// +// 0: BUS domain not accessible +// 1: BUS domain is currently accessible +#define PRCM_PDSTAT1_BUS_ON 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_BITN 4 +#define PRCM_PDSTAT1_BUS_ON_M 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_S 4 + +// Field: [3] VIMS_MODE +// +// +// 0: VIMS domain not accessible +// 1: VIMS domain is currently accessible +#define PRCM_PDSTAT1_VIMS_MODE 0x00000008 +#define PRCM_PDSTAT1_VIMS_MODE_BITN 3 +#define PRCM_PDSTAT1_VIMS_MODE_M 0x00000008 +#define PRCM_PDSTAT1_VIMS_MODE_S 3 + +// Field: [2] RFC_ON +// +// +// 0: RFC domain not accessible +// 1: RFC domain is currently accessible +#define PRCM_PDSTAT1_RFC_ON 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_BITN 2 +#define PRCM_PDSTAT1_RFC_ON_M 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_S 2 + +// Field: [1] CPU_ON +// +// +// 0: CPU and BUS domain not accessible +// 1: CPU and BUS domains are both currently accessible +#define PRCM_PDSTAT1_CPU_ON 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_BITN 1 +#define PRCM_PDSTAT1_CPU_ON_M 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_S 1 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1BUS +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.BUS_ON +#define PRCM_PDSTAT1BUS_ON 0x00000001 +#define PRCM_PDSTAT1BUS_ON_BITN 0 +#define PRCM_PDSTAT1BUS_ON_M 0x00000001 +#define PRCM_PDSTAT1BUS_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1RFC +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.RFC_ON +#define PRCM_PDSTAT1RFC_ON 0x00000001 +#define PRCM_PDSTAT1RFC_ON_BITN 0 +#define PRCM_PDSTAT1RFC_ON_M 0x00000001 +#define PRCM_PDSTAT1RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1CPU +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.CPU_ON +#define PRCM_PDSTAT1CPU_ON 0x00000001 +#define PRCM_PDSTAT1CPU_ON_BITN 0 +#define PRCM_PDSTAT1CPU_ON_M 0x00000001 +#define PRCM_PDSTAT1CPU_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1VIMS +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.VIMS_MODE +#define PRCM_PDSTAT1VIMS_ON 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_BITN 0 +#define PRCM_PDSTAT1VIMS_ON_M 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCBITS +// +//***************************************************************************** +// Field: [31:0] READ +// +// Control bits for RFC. The RF core CPE processor will automatically check +// this register when it boots, and it can be used to immediately instruct CPE +// to perform some tasks at its start-up. The supported functionality is +// ROM-defined and may vary. See the technical reference manual for more +// details. +#define PRCM_RFCBITS_READ_W 32 +#define PRCM_RFCBITS_READ_M 0xFFFFFFFF +#define PRCM_RFCBITS_READ_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCMODESEL +// +//***************************************************************************** +// Field: [2:0] CURR +// +// Selects the set of commands that the RFC will accept. Only modes permitted +// by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for +// details. +// ENUMs: +// MODE7 Select Mode 7 +// MODE6 Select Mode 6 +// MODE5 Select Mode 5 +// MODE4 Select Mode 4 +// MODE3 Select Mode 3 +// MODE2 Select Mode 2 +// MODE1 Select Mode 1 +// MODE0 Select Mode 0 +#define PRCM_RFCMODESEL_CURR_W 3 +#define PRCM_RFCMODESEL_CURR_M 0x00000007 +#define PRCM_RFCMODESEL_CURR_S 0 +#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 +#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 +#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 +#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 +#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 +#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 +#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 +#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_RFCMODEHWOPT +// +//***************************************************************************** +// Field: [7:0] AVAIL +// +// Permitted RFC modes. More than one mode can be permitted. +// ENUMs: +// MODE7 Mode 7 permitted +// MODE6 Mode 6 permitted +// MODE5 Mode 5 permitted +// MODE4 Mode 4 permitted +// MODE3 Mode 3 permitted +// MODE2 Mode 2 permitted +// MODE1 Mode 1 permitted +// MODE0 Mode 0 permitted +#define PRCM_RFCMODEHWOPT_AVAIL_W 8 +#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF +#define PRCM_RFCMODEHWOPT_AVAIL_S 0 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_PWRPROFSTAT +// +//***************************************************************************** +// Field: [7:0] VALUE +// +// SW can use these bits to timestamp the application. These bits are also +// available through the testtap and can thus be used by the emulator to +// profile in real time. +#define PRCM_PWRPROFSTAT_VALUE_W 8 +#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF +#define PRCM_PWRPROFSTAT_VALUE_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RAMRETEN +// +//***************************************************************************** +// Field: [2] RFC +// +// +// 0: Retention for RFC SRAM disabled +// 1: Retention for RFC SRAM enabled +// +// Memories controlled: CPERAM MCERAM RFERAM +#define PRCM_RAMRETEN_RFC 0x00000004 +#define PRCM_RAMRETEN_RFC_BITN 2 +#define PRCM_RAMRETEN_RFC_M 0x00000004 +#define PRCM_RAMRETEN_RFC_S 2 + +// Field: [1:0] VIMS +// +// +// 0: Memory retention disabled +// 1: Memory retention enabled +// +// Bit 0: VIMS_TRAM +// Bit 1: VIMS_CRAM +// +// Legal modes depend on settings in VIMS:CTL.MODE +// +// 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to +// CACHE or SPLIT mode after waking up again +// 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in +// GPRAM mode after wake up, alternatively select OFF mode first and then CACHE +// or SPILT mode. +// 10: Illegal mode +// 11: No restrictions +#define PRCM_RAMRETEN_VIMS_W 2 +#define PRCM_RAMRETEN_VIMS_M 0x00000003 +#define PRCM_RAMRETEN_VIMS_S 0 + + +#endif // __PRCM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_dbell.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_dbell.h new file mode 100644 index 0000000..9ac876c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_dbell.h @@ -0,0 +1,1671 @@ +/****************************************************************************** +* Filename: hw_rfc_dbell_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_DBELL_H__ +#define __HW_RFC_DBELL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_DBELL component +// +//***************************************************************************** +// Doorbell Command Register +#define RFC_DBELL_O_CMDR 0x00000000 + +// Doorbell Command Status Register +#define RFC_DBELL_O_CMDSTA 0x00000004 + +// Interrupt Flags From RF Hardware Modules +#define RFC_DBELL_O_RFHWIFG 0x00000008 + +// Interrupt Enable For RF Hardware Modules +#define RFC_DBELL_O_RFHWIEN 0x0000000C + +// Interrupt Flags For Command and Packet Engine Generated Interrupts +#define RFC_DBELL_O_RFCPEIFG 0x00000010 + +// Interrupt Enable For Command and Packet Engine Generated Interrupts +#define RFC_DBELL_O_RFCPEIEN 0x00000014 + +// Interrupt Vector Selection For Command and Packet Engine Generated +// Interrupts +#define RFC_DBELL_O_RFCPEISL 0x00000018 + +// Doorbell Command Acknowledgement Interrupt Flag +#define RFC_DBELL_O_RFACKIFG 0x0000001C + +// RF Core General Purpose Output Control +#define RFC_DBELL_O_SYSGPOCTL 0x00000020 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_CMDR +// +//***************************************************************************** +// Field: [31:0] CMD +// +// Command register. Raises an interrupt to the Command and packet engine (CPE) +// upon write. +#define RFC_DBELL_CMDR_CMD_W 32 +#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF +#define RFC_DBELL_CMDR_CMD_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_CMDSTA +// +//***************************************************************************** +// Field: [31:0] STAT +// +// Status of the last command used +#define RFC_DBELL_CMDSTA_STAT_W 32 +#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF +#define RFC_DBELL_CMDSTA_STAT_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFHWIFG +// +//***************************************************************************** +// Field: [19] RATCH7 +// +// Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_S 19 + +// Field: [18] RATCH6 +// +// Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_S 18 + +// Field: [17] RATCH5 +// +// Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_S 17 + +// Field: [16] RATCH4 +// +// Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_S 16 + +// Field: [15] RATCH3 +// +// Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_S 15 + +// Field: [14] RATCH2 +// +// Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_S 14 + +// Field: [13] RATCH1 +// +// Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_S 13 + +// Field: [12] RATCH0 +// +// Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_S 12 + +// Field: [11] RFESOFT2 +// +// RF engine software defined interrupt 2 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 + +// Field: [10] RFESOFT1 +// +// RF engine software defined interrupt 1 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 + +// Field: [9] RFESOFT0 +// +// RF engine software defined interrupt 0 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 + +// Field: [8] RFEDONE +// +// RF engine command done interrupt flag. Write zero to clear flag. Write to +// one has no effect. +#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_S 8 + +// Field: [6] TRCTK +// +// Debug tracer system tick interrupt flag. Write zero to clear flag. Write to +// one has no effect. +#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_S 6 + +// Field: [5] MDMSOFT +// +// Modem synchronization word detection interrupt flag. This interrupt will be +// raised by modem when the synchronization word is received. The CPE may +// decide to reject the packet based on its header (protocol specific). Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 + +// Field: [4] MDMOUT +// +// Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has +// no effect. +#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_S 4 + +// Field: [3] MDMIN +// +// Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has +// no effect. +#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_S 3 + +// Field: [2] MDMDONE +// +// Modem command done interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_S 2 + +// Field: [1] FSCA +// +// Frequency synthesizer calibration accelerator interrupt flag. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFHWIFG_FSCA 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_BITN 1 +#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_S 1 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFHWIEN +// +//***************************************************************************** +// Field: [19] RATCH7 +// +// Interrupt enable for RFHWIFG.RATCH7. +#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_S 19 + +// Field: [18] RATCH6 +// +// Interrupt enable for RFHWIFG.RATCH6. +#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_S 18 + +// Field: [17] RATCH5 +// +// Interrupt enable for RFHWIFG.RATCH5. +#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_S 17 + +// Field: [16] RATCH4 +// +// Interrupt enable for RFHWIFG.RATCH4. +#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_S 16 + +// Field: [15] RATCH3 +// +// Interrupt enable for RFHWIFG.RATCH3. +#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_S 15 + +// Field: [14] RATCH2 +// +// Interrupt enable for RFHWIFG.RATCH2. +#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_S 14 + +// Field: [13] RATCH1 +// +// Interrupt enable for RFHWIFG.RATCH1. +#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_S 13 + +// Field: [12] RATCH0 +// +// Interrupt enable for RFHWIFG.RATCH0. +#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_S 12 + +// Field: [11] RFESOFT2 +// +// Interrupt enable for RFHWIFG.RFESOFT2. +#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 + +// Field: [10] RFESOFT1 +// +// Interrupt enable for RFHWIFG.RFESOFT1. +#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 + +// Field: [9] RFESOFT0 +// +// Interrupt enable for RFHWIFG.RFESOFT0. +#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 + +// Field: [8] RFEDONE +// +// Interrupt enable for RFHWIFG.RFEDONE. +#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_S 8 + +// Field: [6] TRCTK +// +// Interrupt enable for RFHWIFG.TRCTK. +#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_S 6 + +// Field: [5] MDMSOFT +// +// Interrupt enable for RFHWIFG.MDMSOFT. +#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 + +// Field: [4] MDMOUT +// +// Interrupt enable for RFHWIFG.MDMOUT. +#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_S 4 + +// Field: [3] MDMIN +// +// Interrupt enable for RFHWIFG.MDMIN. +#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_S 3 + +// Field: [2] MDMDONE +// +// Interrupt enable for RFHWIFG.MDMDONE. +#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_S 2 + +// Field: [1] FSCA +// +// Interrupt enable for RFHWIFG.FSCA. +#define RFC_DBELL_RFHWIEN_FSCA 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_BITN 1 +#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_S 1 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEIFG +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Interrupt flag 31. The command and packet engine (CPE) has observed an +// unexpected error. A reset of the CPE is needed. This can be done by +// switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 + +// Field: [30] BOOT_DONE +// +// Interrupt flag 30. The command and packet engine (CPE) boot is finished. +// Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 + +// Field: [29] MODULES_UNLOCKED +// +// Interrupt flag 29. As part of command and packet engine (CPE) boot process, +// it has opened access to RF Core modules and memories. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 + +// Field: [28] SYNTH_NO_LOCK +// +// Interrupt flag 28. The phase-locked loop in frequency synthesizer has +// reported loss of lock. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 + +// Field: [27] IRQ27 +// +// Interrupt flag 27. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_S 27 + +// Field: [26] RX_ABORTED +// +// Interrupt flag 26. Packet reception stopped before packet was done. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Interrupt flag 25. Specified number of bytes written to partial read Rx +// buffer. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 + +// Field: [24] RX_DATA_WRITTEN +// +// Interrupt flag 24. Data written to partial read Rx buffer. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 + +// Field: [23] RX_ENTRY_DONE +// +// Interrupt flag 23. Rx queue data entry changing state to finished. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 + +// Field: [22] RX_BUF_FULL +// +// Interrupt flag 22. Packet received that did not fit in Rx queue. BLE mode: +// Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame +// received that did not fit in the Rx queue. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 + +// Field: [21] RX_CTRL_ACK +// +// Interrupt flag 21. BLE mode only: LL control packet received with CRC OK, +// not to be ignored, then acknowledgement sent. Write zero to clear flag. +// Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 + +// Field: [20] RX_CTRL +// +// Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, +// not to be ignored. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 + +// Field: [19] RX_EMPTY +// +// Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be +// ignored, no payload. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 + +// Field: [18] RX_IGNORED +// +// Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet +// received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received +// with ignore flag set. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 + +// Field: [17] RX_NOK +// +// Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received +// with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 + +// Field: [16] RX_OK +// +// Interrupt flag 16. Packet received correctly. BLE mode: Packet received with +// CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received +// with CRC OK. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_S 16 + +// Field: [15] IRQ15 +// +// Interrupt flag 15. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_S 15 + +// Field: [14] IRQ14 +// +// Interrupt flag 14. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_S 14 + +// Field: [13] IRQ13 +// +// Interrupt flag 13. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEIFG_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEIFG_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEIFG_IRQ13_S 13 + +// Field: [12] IRQ12 +// +// Interrupt flag 12. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEIFG_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEIFG_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEIFG_IRQ12_S 12 + +// Field: [11] TX_BUFFER_CHANGED +// +// Interrupt flag 11. BLE mode only: A buffer change is complete after +// CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 + +// Field: [10] TX_ENTRY_DONE +// +// Interrupt flag 10. Tx queue data entry state changed to finished. Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 + +// Field: [9] TX_RETRANS +// +// Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted +// LL control packet, and acknowledgement transmitted for that packet. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 + +// Field: [7] TX_CTRL_ACK +// +// Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL +// control packet. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 + +// Field: [6] TX_CTRL +// +// Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 + +// Field: [5] TX_ACK +// +// Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted +// packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 + +// Field: [4] TX_DONE +// +// Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been +// transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio +// operation command in a chain of commands has finished. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 + +// Field: [2] FG_COMMAND_DONE +// +// Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation +// command has finished. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 + +// Field: [1] LAST_COMMAND_DONE +// +// Interrupt flag 1. The last radio operation command in a chain of commands +// has finished. (IEEE 802.15.4 mode: The last background level radio operation +// command in a chain of commands has finished.) Write zero to clear flag. +// Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 + +// Field: [0] COMMAND_DONE +// +// Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A +// background level radio operation command has finished.) Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEIEN +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Interrupt enable for RFCPEIFG.INTERNAL_ERROR. +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 + +// Field: [30] BOOT_DONE +// +// Interrupt enable for RFCPEIFG.BOOT_DONE. +#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 + +// Field: [29] MODULES_UNLOCKED +// +// Interrupt enable for RFCPEIFG.MODULES_UNLOCKED. +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 + +// Field: [28] SYNTH_NO_LOCK +// +// Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK. +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 + +// Field: [27] IRQ27 +// +// Interrupt enable for RFCPEIFG.IRQ27. +#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_S 27 + +// Field: [26] RX_ABORTED +// +// Interrupt enable for RFCPEIFG.RX_ABORTED. +#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN. +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 + +// Field: [24] RX_DATA_WRITTEN +// +// Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN. +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 + +// Field: [23] RX_ENTRY_DONE +// +// Interrupt enable for RFCPEIFG.RX_ENTRY_DONE. +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 + +// Field: [22] RX_BUF_FULL +// +// Interrupt enable for RFCPEIFG.RX_BUF_FULL. +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 + +// Field: [21] RX_CTRL_ACK +// +// Interrupt enable for RFCPEIFG.RX_CTRL_ACK. +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 + +// Field: [20] RX_CTRL +// +// Interrupt enable for RFCPEIFG.RX_CTRL. +#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 + +// Field: [19] RX_EMPTY +// +// Interrupt enable for RFCPEIFG.RX_EMPTY. +#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 + +// Field: [18] RX_IGNORED +// +// Interrupt enable for RFCPEIFG.RX_IGNORED. +#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 + +// Field: [17] RX_NOK +// +// Interrupt enable for RFCPEIFG.RX_NOK. +#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 + +// Field: [16] RX_OK +// +// Interrupt enable for RFCPEIFG.RX_OK. +#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_S 16 + +// Field: [15] IRQ15 +// +// Interrupt enable for RFCPEIFG.IRQ15. +#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_S 15 + +// Field: [14] IRQ14 +// +// Interrupt enable for RFCPEIFG.IRQ14. +#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_S 14 + +// Field: [13] IRQ13 +// +// Interrupt enable for RFCPEIFG.IRQ13. +#define RFC_DBELL_RFCPEIEN_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEIEN_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEIEN_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEIEN_IRQ13_S 13 + +// Field: [12] IRQ12 +// +// Interrupt enable for RFCPEIFG.IRQ12. +#define RFC_DBELL_RFCPEIEN_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEIEN_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEIEN_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEIEN_IRQ12_S 12 + +// Field: [11] TX_BUFFER_CHANGED +// +// Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED. +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 + +// Field: [10] TX_ENTRY_DONE +// +// Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 + +// Field: [9] TX_RETRANS +// +// Interrupt enable for RFCPEIFG.TX_RETRANS. +#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 + +// Field: [7] TX_CTRL_ACK +// +// Interrupt enable for RFCPEIFG.TX_CTRL_ACK. +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 + +// Field: [6] TX_CTRL +// +// Interrupt enable for RFCPEIFG.TX_CTRL. +#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 + +// Field: [5] TX_ACK +// +// Interrupt enable for RFCPEIFG.TX_ACK. +#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 + +// Field: [4] TX_DONE +// +// Interrupt enable for RFCPEIFG.TX_DONE. +#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 + +// Field: [2] FG_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.FG_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 + +// Field: [1] LAST_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 + +// Field: [0] COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEISL +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 + +// Field: [30] BOOT_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 + +// Field: [29] MODULES_UNLOCKED +// +// Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 + +// Field: [28] SYNTH_NO_LOCK +// +// Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 + +// Field: [27] IRQ27 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_S 27 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 + +// Field: [26] RX_ABORTED +// +// Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 + +// Field: [24] RX_DATA_WRITTEN +// +// Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 + +// Field: [23] RX_ENTRY_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 + +// Field: [22] RX_BUF_FULL +// +// Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 + +// Field: [21] RX_CTRL_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 + +// Field: [20] RX_CTRL +// +// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 + +// Field: [19] RX_EMPTY +// +// Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 + +// Field: [18] RX_IGNORED +// +// Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 + +// Field: [17] RX_NOK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_S 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 + +// Field: [16] RX_OK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_S 16 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 + +// Field: [15] IRQ15 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_S 15 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 + +// Field: [14] IRQ14 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_S 14 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 + +// Field: [13] IRQ13 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ13 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEISL_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_S 13 +#define RFC_DBELL_RFCPEISL_IRQ13_CPE1 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_CPE0 0x00000000 + +// Field: [12] IRQ12 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ12 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEISL_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_S 12 +#define RFC_DBELL_RFCPEISL_IRQ12_CPE1 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_CPE0 0x00000000 + +// Field: [11] TX_BUFFER_CHANGED +// +// Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 + +// Field: [10] TX_ENTRY_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 + +// Field: [9] TX_RETRANS +// +// Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 + +// Field: [7] TX_CTRL_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 + +// Field: [6] TX_CTRL +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 + +// Field: [5] TX_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_S 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 + +// Field: [4] TX_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_S 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE +// interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 + +// Field: [2] FG_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 + +// Field: [1] LAST_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 + +// Field: [0] COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFACKIFG +// +//***************************************************************************** +// Field: [0] ACKFLAG +// +// Interrupt flag for Command ACK +#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 +#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_SYSGPOCTL +// +//***************************************************************************** +// Field: [15:12] GPOCTL3 +// +// RF Core GPO control bit 3. Selects which signal to output on the RF Core GPO +// line 3. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 + +// Field: [11:8] GPOCTL2 +// +// RF Core GPO control bit 2. Selects which signal to output on the RF Core GPO +// line 2. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 + +// Field: [7:4] GPOCTL1 +// +// RF Core GPO control bit 1. Selects which signal to output on the RF Core GPO +// line 1. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 + +// Field: [3:0] GPOCTL0 +// +// RF Core GPO control bit 0. Selects which signal to output on the RF Core GPO +// line 0. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 + + +#endif // __RFC_DBELL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_pwr.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_pwr.h new file mode 100644 index 0000000..ad91fb3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_pwr.h @@ -0,0 +1,153 @@ +/****************************************************************************** +* Filename: hw_rfc_pwr_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_PWR_H__ +#define __HW_RFC_PWR_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_PWR component +// +//***************************************************************************** +// RF Core Power Management and Clock Enable +#define RFC_PWR_O_PWMCLKEN 0x00000000 + +//***************************************************************************** +// +// Register: RFC_PWR_O_PWMCLKEN +// +//***************************************************************************** +// Field: [10] RFCTRC +// +// Enable clock to the RF Core Tracer (RFCTRC) module. +#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 +#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_S 10 + +// Field: [9] FSCA +// +// Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) +// module. +#define RFC_PWR_PWMCLKEN_FSCA 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_BITN 9 +#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_S 9 + +// Field: [8] PHA +// +// Enable clock to the Packet Handling Accelerator (PHA) module. +#define RFC_PWR_PWMCLKEN_PHA 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_BITN 8 +#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_S 8 + +// Field: [7] RAT +// +// Enable clock to the Radio Timer (RAT) module. +#define RFC_PWR_PWMCLKEN_RAT 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_BITN 7 +#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_S 7 + +// Field: [6] RFERAM +// +// Enable clock to the RF Engine RAM module. +#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 +#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_S 6 + +// Field: [5] RFE +// +// Enable clock to the RF Engine (RFE) module. +#define RFC_PWR_PWMCLKEN_RFE 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_BITN 5 +#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_S 5 + +// Field: [4] MDMRAM +// +// Enable clock to the Modem RAM module. +#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 +#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_S 4 + +// Field: [3] MDM +// +// Enable clock to the Modem (MDM) module. +#define RFC_PWR_PWMCLKEN_MDM 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_BITN 3 +#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_S 3 + +// Field: [2] CPERAM +// +// Enable clock to the Command and Packet Engine (CPE) RAM module. As part of +// RF Core initialization, set this bit together with CPE bit to enable CPE to +// boot. +#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 +#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_S 2 + +// Field: [1] CPE +// +// Enable processor clock (hclk) to the Command and Packet Engine (CPE). As +// part of RF Core initialization, set this bit together with CPERAM bit to +// enable CPE to boot. +#define RFC_PWR_PWMCLKEN_CPE 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_BITN 1 +#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_S 1 + +// Field: [0] RFC +// +// Enable essential clocks for the RF Core interface. This includes the +// interconnect, the radio doorbell DBELL command interface, the power +// management (PWR) clock control module, and bus clock (sclk) for the CPE. To +// remove possibility of locking yourself out from the RF Core, this bit can +// not be cleared. If you need to disable all clocks to the RF Core, see the +// PRCM:RFCCLKG.CLK_EN register. +#define RFC_PWR_PWMCLKEN_RFC 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_BITN 0 +#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_S 0 + + +#endif // __RFC_PWR__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_rat.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_rat.h new file mode 100644 index 0000000..83f131c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_rat.h @@ -0,0 +1,190 @@ +/****************************************************************************** +* Filename: hw_rfc_rat_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_RAT_H__ +#define __HW_RFC_RAT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_RAT component +// +//***************************************************************************** +// Radio Timer Counter Value +#define RFC_RAT_O_RATCNT 0x00000004 + +// Timer Channel 0 Capture/Compare Register +#define RFC_RAT_O_RATCH0VAL 0x00000080 + +// Timer Channel 1 Capture/Compare Register +#define RFC_RAT_O_RATCH1VAL 0x00000084 + +// Timer Channel 2 Capture/Compare Register +#define RFC_RAT_O_RATCH2VAL 0x00000088 + +// Timer Channel 3 Capture/Compare Register +#define RFC_RAT_O_RATCH3VAL 0x0000008C + +// Timer Channel 4 Capture/Compare Register +#define RFC_RAT_O_RATCH4VAL 0x00000090 + +// Timer Channel 5 Capture/Compare Register +#define RFC_RAT_O_RATCH5VAL 0x00000094 + +// Timer Channel 6 Capture/Compare Register +#define RFC_RAT_O_RATCH6VAL 0x00000098 + +// Timer Channel 7 Capture/Compare Register +#define RFC_RAT_O_RATCH7VAL 0x0000009C + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCNT +// +//***************************************************************************** +// Field: [31:0] CNT +// +// Counter value. This is not writable while radio timer counter is enabled. +#define RFC_RAT_RATCNT_CNT_W 32 +#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF +#define RFC_RAT_RATCNT_CNT_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH0VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH0VAL_VAL_W 32 +#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH0VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH1VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH1VAL_VAL_W 32 +#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH1VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH2VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH2VAL_VAL_W 32 +#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH2VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH3VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH3VAL_VAL_W 32 +#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH3VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH4VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH4VAL_VAL_W 32 +#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH4VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH5VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH5VAL_VAL_W 32 +#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH5VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH6VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH6VAL_VAL_W 32 +#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH6VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH7VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. The system CPU can safely read this register, but it +// is recommended to use the CPE API commands to configure it for compare mode. +#define RFC_RAT_RATCH7VAL_VAL_W 32 +#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH7VAL_VAL_S 0 + + +#endif // __RFC_RAT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_smph.h new file mode 100644 index 0000000..669eb26 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_smph.h @@ -0,0 +1,1455 @@ +/****************************************************************************** +* Filename: hw_smph_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SMPH_H__ +#define __HW_SMPH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SMPH component +// +//***************************************************************************** +// MCU SEMAPHORE 0 +#define SMPH_O_SMPH0 0x00000000 + +// MCU SEMAPHORE 1 +#define SMPH_O_SMPH1 0x00000004 + +// MCU SEMAPHORE 2 +#define SMPH_O_SMPH2 0x00000008 + +// MCU SEMAPHORE 3 +#define SMPH_O_SMPH3 0x0000000C + +// MCU SEMAPHORE 4 +#define SMPH_O_SMPH4 0x00000010 + +// MCU SEMAPHORE 5 +#define SMPH_O_SMPH5 0x00000014 + +// MCU SEMAPHORE 6 +#define SMPH_O_SMPH6 0x00000018 + +// MCU SEMAPHORE 7 +#define SMPH_O_SMPH7 0x0000001C + +// MCU SEMAPHORE 8 +#define SMPH_O_SMPH8 0x00000020 + +// MCU SEMAPHORE 9 +#define SMPH_O_SMPH9 0x00000024 + +// MCU SEMAPHORE 10 +#define SMPH_O_SMPH10 0x00000028 + +// MCU SEMAPHORE 11 +#define SMPH_O_SMPH11 0x0000002C + +// MCU SEMAPHORE 12 +#define SMPH_O_SMPH12 0x00000030 + +// MCU SEMAPHORE 13 +#define SMPH_O_SMPH13 0x00000034 + +// MCU SEMAPHORE 14 +#define SMPH_O_SMPH14 0x00000038 + +// MCU SEMAPHORE 15 +#define SMPH_O_SMPH15 0x0000003C + +// MCU SEMAPHORE 16 +#define SMPH_O_SMPH16 0x00000040 + +// MCU SEMAPHORE 17 +#define SMPH_O_SMPH17 0x00000044 + +// MCU SEMAPHORE 18 +#define SMPH_O_SMPH18 0x00000048 + +// MCU SEMAPHORE 19 +#define SMPH_O_SMPH19 0x0000004C + +// MCU SEMAPHORE 20 +#define SMPH_O_SMPH20 0x00000050 + +// MCU SEMAPHORE 21 +#define SMPH_O_SMPH21 0x00000054 + +// MCU SEMAPHORE 22 +#define SMPH_O_SMPH22 0x00000058 + +// MCU SEMAPHORE 23 +#define SMPH_O_SMPH23 0x0000005C + +// MCU SEMAPHORE 24 +#define SMPH_O_SMPH24 0x00000060 + +// MCU SEMAPHORE 25 +#define SMPH_O_SMPH25 0x00000064 + +// MCU SEMAPHORE 26 +#define SMPH_O_SMPH26 0x00000068 + +// MCU SEMAPHORE 27 +#define SMPH_O_SMPH27 0x0000006C + +// MCU SEMAPHORE 28 +#define SMPH_O_SMPH28 0x00000070 + +// MCU SEMAPHORE 29 +#define SMPH_O_SMPH29 0x00000074 + +// MCU SEMAPHORE 30 +#define SMPH_O_SMPH30 0x00000078 + +// MCU SEMAPHORE 31 +#define SMPH_O_SMPH31 0x0000007C + +// MCU SEMAPHORE 0 ALIAS +#define SMPH_O_PEEK0 0x00000800 + +// MCU SEMAPHORE 1 ALIAS +#define SMPH_O_PEEK1 0x00000804 + +// MCU SEMAPHORE 2 ALIAS +#define SMPH_O_PEEK2 0x00000808 + +// MCU SEMAPHORE 3 ALIAS +#define SMPH_O_PEEK3 0x0000080C + +// MCU SEMAPHORE 4 ALIAS +#define SMPH_O_PEEK4 0x00000810 + +// MCU SEMAPHORE 5 ALIAS +#define SMPH_O_PEEK5 0x00000814 + +// MCU SEMAPHORE 6 ALIAS +#define SMPH_O_PEEK6 0x00000818 + +// MCU SEMAPHORE 7 ALIAS +#define SMPH_O_PEEK7 0x0000081C + +// MCU SEMAPHORE 8 ALIAS +#define SMPH_O_PEEK8 0x00000820 + +// MCU SEMAPHORE 9 ALIAS +#define SMPH_O_PEEK9 0x00000824 + +// MCU SEMAPHORE 10 ALIAS +#define SMPH_O_PEEK10 0x00000828 + +// MCU SEMAPHORE 11 ALIAS +#define SMPH_O_PEEK11 0x0000082C + +// MCU SEMAPHORE 12 ALIAS +#define SMPH_O_PEEK12 0x00000830 + +// MCU SEMAPHORE 13 ALIAS +#define SMPH_O_PEEK13 0x00000834 + +// MCU SEMAPHORE 14 ALIAS +#define SMPH_O_PEEK14 0x00000838 + +// MCU SEMAPHORE 15 ALIAS +#define SMPH_O_PEEK15 0x0000083C + +// MCU SEMAPHORE 16 ALIAS +#define SMPH_O_PEEK16 0x00000840 + +// MCU SEMAPHORE 17 ALIAS +#define SMPH_O_PEEK17 0x00000844 + +// MCU SEMAPHORE 18 ALIAS +#define SMPH_O_PEEK18 0x00000848 + +// MCU SEMAPHORE 19 ALIAS +#define SMPH_O_PEEK19 0x0000084C + +// MCU SEMAPHORE 20 ALIAS +#define SMPH_O_PEEK20 0x00000850 + +// MCU SEMAPHORE 21 ALIAS +#define SMPH_O_PEEK21 0x00000854 + +// MCU SEMAPHORE 22 ALIAS +#define SMPH_O_PEEK22 0x00000858 + +// MCU SEMAPHORE 23 ALIAS +#define SMPH_O_PEEK23 0x0000085C + +// MCU SEMAPHORE 24 ALIAS +#define SMPH_O_PEEK24 0x00000860 + +// MCU SEMAPHORE 25 ALIAS +#define SMPH_O_PEEK25 0x00000864 + +// MCU SEMAPHORE 26 ALIAS +#define SMPH_O_PEEK26 0x00000868 + +// MCU SEMAPHORE 27 ALIAS +#define SMPH_O_PEEK27 0x0000086C + +// MCU SEMAPHORE 28 ALIAS +#define SMPH_O_PEEK28 0x00000870 + +// MCU SEMAPHORE 29 ALIAS +#define SMPH_O_PEEK29 0x00000874 + +// MCU SEMAPHORE 30 ALIAS +#define SMPH_O_PEEK30 0x00000878 + +// MCU SEMAPHORE 31 ALIAS +#define SMPH_O_PEEK31 0x0000087C + +//***************************************************************************** +// +// Register: SMPH_O_SMPH0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH0_STAT 0x00000001 +#define SMPH_SMPH0_STAT_BITN 0 +#define SMPH_SMPH0_STAT_M 0x00000001 +#define SMPH_SMPH0_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH1_STAT 0x00000001 +#define SMPH_SMPH1_STAT_BITN 0 +#define SMPH_SMPH1_STAT_M 0x00000001 +#define SMPH_SMPH1_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH2_STAT 0x00000001 +#define SMPH_SMPH2_STAT_BITN 0 +#define SMPH_SMPH2_STAT_M 0x00000001 +#define SMPH_SMPH2_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH3_STAT 0x00000001 +#define SMPH_SMPH3_STAT_BITN 0 +#define SMPH_SMPH3_STAT_M 0x00000001 +#define SMPH_SMPH3_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH4_STAT 0x00000001 +#define SMPH_SMPH4_STAT_BITN 0 +#define SMPH_SMPH4_STAT_M 0x00000001 +#define SMPH_SMPH4_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH5_STAT 0x00000001 +#define SMPH_SMPH5_STAT_BITN 0 +#define SMPH_SMPH5_STAT_M 0x00000001 +#define SMPH_SMPH5_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH6_STAT 0x00000001 +#define SMPH_SMPH6_STAT_BITN 0 +#define SMPH_SMPH6_STAT_M 0x00000001 +#define SMPH_SMPH6_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH7_STAT 0x00000001 +#define SMPH_SMPH7_STAT_BITN 0 +#define SMPH_SMPH7_STAT_M 0x00000001 +#define SMPH_SMPH7_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH8 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH8_STAT 0x00000001 +#define SMPH_SMPH8_STAT_BITN 0 +#define SMPH_SMPH8_STAT_M 0x00000001 +#define SMPH_SMPH8_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH9 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH9_STAT 0x00000001 +#define SMPH_SMPH9_STAT_BITN 0 +#define SMPH_SMPH9_STAT_M 0x00000001 +#define SMPH_SMPH9_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH10 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH10_STAT 0x00000001 +#define SMPH_SMPH10_STAT_BITN 0 +#define SMPH_SMPH10_STAT_M 0x00000001 +#define SMPH_SMPH10_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH11 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH11_STAT 0x00000001 +#define SMPH_SMPH11_STAT_BITN 0 +#define SMPH_SMPH11_STAT_M 0x00000001 +#define SMPH_SMPH11_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH12 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH12_STAT 0x00000001 +#define SMPH_SMPH12_STAT_BITN 0 +#define SMPH_SMPH12_STAT_M 0x00000001 +#define SMPH_SMPH12_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH13 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH13_STAT 0x00000001 +#define SMPH_SMPH13_STAT_BITN 0 +#define SMPH_SMPH13_STAT_M 0x00000001 +#define SMPH_SMPH13_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH14 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH14_STAT 0x00000001 +#define SMPH_SMPH14_STAT_BITN 0 +#define SMPH_SMPH14_STAT_M 0x00000001 +#define SMPH_SMPH14_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH15 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH15_STAT 0x00000001 +#define SMPH_SMPH15_STAT_BITN 0 +#define SMPH_SMPH15_STAT_M 0x00000001 +#define SMPH_SMPH15_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH16 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH16_STAT 0x00000001 +#define SMPH_SMPH16_STAT_BITN 0 +#define SMPH_SMPH16_STAT_M 0x00000001 +#define SMPH_SMPH16_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH17 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH17_STAT 0x00000001 +#define SMPH_SMPH17_STAT_BITN 0 +#define SMPH_SMPH17_STAT_M 0x00000001 +#define SMPH_SMPH17_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH18 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH18_STAT 0x00000001 +#define SMPH_SMPH18_STAT_BITN 0 +#define SMPH_SMPH18_STAT_M 0x00000001 +#define SMPH_SMPH18_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH19 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH19_STAT 0x00000001 +#define SMPH_SMPH19_STAT_BITN 0 +#define SMPH_SMPH19_STAT_M 0x00000001 +#define SMPH_SMPH19_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH20 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH20_STAT 0x00000001 +#define SMPH_SMPH20_STAT_BITN 0 +#define SMPH_SMPH20_STAT_M 0x00000001 +#define SMPH_SMPH20_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH21 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH21_STAT 0x00000001 +#define SMPH_SMPH21_STAT_BITN 0 +#define SMPH_SMPH21_STAT_M 0x00000001 +#define SMPH_SMPH21_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH22 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH22_STAT 0x00000001 +#define SMPH_SMPH22_STAT_BITN 0 +#define SMPH_SMPH22_STAT_M 0x00000001 +#define SMPH_SMPH22_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH23 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH23_STAT 0x00000001 +#define SMPH_SMPH23_STAT_BITN 0 +#define SMPH_SMPH23_STAT_M 0x00000001 +#define SMPH_SMPH23_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH24 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH24_STAT 0x00000001 +#define SMPH_SMPH24_STAT_BITN 0 +#define SMPH_SMPH24_STAT_M 0x00000001 +#define SMPH_SMPH24_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH25 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH25_STAT 0x00000001 +#define SMPH_SMPH25_STAT_BITN 0 +#define SMPH_SMPH25_STAT_M 0x00000001 +#define SMPH_SMPH25_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH26 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH26_STAT 0x00000001 +#define SMPH_SMPH26_STAT_BITN 0 +#define SMPH_SMPH26_STAT_M 0x00000001 +#define SMPH_SMPH26_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH27 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH27_STAT 0x00000001 +#define SMPH_SMPH27_STAT_BITN 0 +#define SMPH_SMPH27_STAT_M 0x00000001 +#define SMPH_SMPH27_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH28 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH28_STAT 0x00000001 +#define SMPH_SMPH28_STAT_BITN 0 +#define SMPH_SMPH28_STAT_M 0x00000001 +#define SMPH_SMPH28_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH29 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH29_STAT 0x00000001 +#define SMPH_SMPH29_STAT_BITN 0 +#define SMPH_SMPH29_STAT_M 0x00000001 +#define SMPH_SMPH29_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH30 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH30_STAT 0x00000001 +#define SMPH_SMPH30_STAT_BITN 0 +#define SMPH_SMPH30_STAT_M 0x00000001 +#define SMPH_SMPH30_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH31 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH31_STAT 0x00000001 +#define SMPH_SMPH31_STAT_BITN 0 +#define SMPH_SMPH31_STAT_M 0x00000001 +#define SMPH_SMPH31_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK0_STAT 0x00000001 +#define SMPH_PEEK0_STAT_BITN 0 +#define SMPH_PEEK0_STAT_M 0x00000001 +#define SMPH_PEEK0_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK1_STAT 0x00000001 +#define SMPH_PEEK1_STAT_BITN 0 +#define SMPH_PEEK1_STAT_M 0x00000001 +#define SMPH_PEEK1_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK2_STAT 0x00000001 +#define SMPH_PEEK2_STAT_BITN 0 +#define SMPH_PEEK2_STAT_M 0x00000001 +#define SMPH_PEEK2_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK3_STAT 0x00000001 +#define SMPH_PEEK3_STAT_BITN 0 +#define SMPH_PEEK3_STAT_M 0x00000001 +#define SMPH_PEEK3_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK4_STAT 0x00000001 +#define SMPH_PEEK4_STAT_BITN 0 +#define SMPH_PEEK4_STAT_M 0x00000001 +#define SMPH_PEEK4_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK5_STAT 0x00000001 +#define SMPH_PEEK5_STAT_BITN 0 +#define SMPH_PEEK5_STAT_M 0x00000001 +#define SMPH_PEEK5_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK6_STAT 0x00000001 +#define SMPH_PEEK6_STAT_BITN 0 +#define SMPH_PEEK6_STAT_M 0x00000001 +#define SMPH_PEEK6_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK7_STAT 0x00000001 +#define SMPH_PEEK7_STAT_BITN 0 +#define SMPH_PEEK7_STAT_M 0x00000001 +#define SMPH_PEEK7_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK8 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK8_STAT 0x00000001 +#define SMPH_PEEK8_STAT_BITN 0 +#define SMPH_PEEK8_STAT_M 0x00000001 +#define SMPH_PEEK8_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK9 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK9_STAT 0x00000001 +#define SMPH_PEEK9_STAT_BITN 0 +#define SMPH_PEEK9_STAT_M 0x00000001 +#define SMPH_PEEK9_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK10 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK10_STAT 0x00000001 +#define SMPH_PEEK10_STAT_BITN 0 +#define SMPH_PEEK10_STAT_M 0x00000001 +#define SMPH_PEEK10_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK11 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK11_STAT 0x00000001 +#define SMPH_PEEK11_STAT_BITN 0 +#define SMPH_PEEK11_STAT_M 0x00000001 +#define SMPH_PEEK11_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK12 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK12_STAT 0x00000001 +#define SMPH_PEEK12_STAT_BITN 0 +#define SMPH_PEEK12_STAT_M 0x00000001 +#define SMPH_PEEK12_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK13 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK13_STAT 0x00000001 +#define SMPH_PEEK13_STAT_BITN 0 +#define SMPH_PEEK13_STAT_M 0x00000001 +#define SMPH_PEEK13_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK14 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK14_STAT 0x00000001 +#define SMPH_PEEK14_STAT_BITN 0 +#define SMPH_PEEK14_STAT_M 0x00000001 +#define SMPH_PEEK14_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK15 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK15_STAT 0x00000001 +#define SMPH_PEEK15_STAT_BITN 0 +#define SMPH_PEEK15_STAT_M 0x00000001 +#define SMPH_PEEK15_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK16 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK16_STAT 0x00000001 +#define SMPH_PEEK16_STAT_BITN 0 +#define SMPH_PEEK16_STAT_M 0x00000001 +#define SMPH_PEEK16_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK17 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK17_STAT 0x00000001 +#define SMPH_PEEK17_STAT_BITN 0 +#define SMPH_PEEK17_STAT_M 0x00000001 +#define SMPH_PEEK17_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK18 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK18_STAT 0x00000001 +#define SMPH_PEEK18_STAT_BITN 0 +#define SMPH_PEEK18_STAT_M 0x00000001 +#define SMPH_PEEK18_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK19 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK19_STAT 0x00000001 +#define SMPH_PEEK19_STAT_BITN 0 +#define SMPH_PEEK19_STAT_M 0x00000001 +#define SMPH_PEEK19_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK20 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK20_STAT 0x00000001 +#define SMPH_PEEK20_STAT_BITN 0 +#define SMPH_PEEK20_STAT_M 0x00000001 +#define SMPH_PEEK20_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK21 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK21_STAT 0x00000001 +#define SMPH_PEEK21_STAT_BITN 0 +#define SMPH_PEEK21_STAT_M 0x00000001 +#define SMPH_PEEK21_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK22 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK22_STAT 0x00000001 +#define SMPH_PEEK22_STAT_BITN 0 +#define SMPH_PEEK22_STAT_M 0x00000001 +#define SMPH_PEEK22_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK23 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK23_STAT 0x00000001 +#define SMPH_PEEK23_STAT_BITN 0 +#define SMPH_PEEK23_STAT_M 0x00000001 +#define SMPH_PEEK23_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK24 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK24_STAT 0x00000001 +#define SMPH_PEEK24_STAT_BITN 0 +#define SMPH_PEEK24_STAT_M 0x00000001 +#define SMPH_PEEK24_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK25 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK25_STAT 0x00000001 +#define SMPH_PEEK25_STAT_BITN 0 +#define SMPH_PEEK25_STAT_M 0x00000001 +#define SMPH_PEEK25_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK26 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK26_STAT 0x00000001 +#define SMPH_PEEK26_STAT_BITN 0 +#define SMPH_PEEK26_STAT_M 0x00000001 +#define SMPH_PEEK26_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK27 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK27_STAT 0x00000001 +#define SMPH_PEEK27_STAT_BITN 0 +#define SMPH_PEEK27_STAT_M 0x00000001 +#define SMPH_PEEK27_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK28 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK28_STAT 0x00000001 +#define SMPH_PEEK28_STAT_BITN 0 +#define SMPH_PEEK28_STAT_M 0x00000001 +#define SMPH_PEEK28_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK29 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK29_STAT 0x00000001 +#define SMPH_PEEK29_STAT_BITN 0 +#define SMPH_PEEK29_STAT_M 0x00000001 +#define SMPH_PEEK29_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK30 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK30_STAT 0x00000001 +#define SMPH_PEEK30_STAT_BITN 0 +#define SMPH_PEEK30_STAT_M 0x00000001 +#define SMPH_PEEK30_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK31 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK31_STAT 0x00000001 +#define SMPH_PEEK31_STAT_BITN 0 +#define SMPH_PEEK31_STAT_M 0x00000001 +#define SMPH_PEEK31_STAT_S 0 + + +#endif // __SMPH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ssi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ssi.h new file mode 100644 index 0000000..a83b856 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ssi.h @@ -0,0 +1,544 @@ +/****************************************************************************** +* Filename: hw_ssi_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SSI component +// +//***************************************************************************** +// Control 0 +#define SSI_O_CR0 0x00000000 + +// Control 1 +#define SSI_O_CR1 0x00000004 + +// Data +#define SSI_O_DR 0x00000008 + +// Status +#define SSI_O_SR 0x0000000C + +// Clock Prescale +#define SSI_O_CPSR 0x00000010 + +// Interrupt Mask Set and Clear +#define SSI_O_IMSC 0x00000014 + +// Raw Interrupt Status +#define SSI_O_RIS 0x00000018 + +// Masked Interrupt Status +#define SSI_O_MIS 0x0000001C + +// Interrupt Clear +#define SSI_O_ICR 0x00000020 + +// DMA Control +#define SSI_O_DMACR 0x00000024 + +//***************************************************************************** +// +// Register: SSI_O_CR0 +// +//***************************************************************************** +// Field: [15:8] SCR +// +// Serial clock rate: +// This is used to generate the transmit and receive bit rate of the SSI. The +// bit rate is +// (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). +// SCR is a value from 0-255. +#define SSI_CR0_SCR_W 8 +#define SSI_CR0_SCR_M 0x0000FF00 +#define SSI_CR0_SCR_S 8 + +// Field: [7] SPH +// +// CLKOUT phase (Motorola SPI frame format only) +// This bit selects the clock edge that captures data and enables it to change +// state. It +// has the most impact on the first bit transmitted by either permitting or not +// permitting a clock transition before the first data capture edge. +// ENUMs: +// 2ND_CLK_EDGE Data is captured on the second clock edge +// transition. +// 1ST_CLK_EDGE Data is captured on the first clock edge +// transition. +#define SSI_CR0_SPH 0x00000080 +#define SSI_CR0_SPH_BITN 7 +#define SSI_CR0_SPH_M 0x00000080 +#define SSI_CR0_SPH_S 7 +#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 +#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 + +// Field: [6] SPO +// +// CLKOUT polarity (Motorola SPI frame format only) +// ENUMs: +// HIGH SSI produces a steady state HIGH value on the +// CLKOUT pin when data is not being transferred. +// LOW SSI produces a steady state LOW value on the +// CLKOUT pin when data is +// not being transferred. +#define SSI_CR0_SPO 0x00000040 +#define SSI_CR0_SPO_BITN 6 +#define SSI_CR0_SPO_M 0x00000040 +#define SSI_CR0_SPO_S 6 +#define SSI_CR0_SPO_HIGH 0x00000040 +#define SSI_CR0_SPO_LOW 0x00000000 + +// Field: [5:4] FRF +// +// Frame format. +// The supported frame formats are Motorola SPI, TI synchronous serial and +// National Microwire. +// Value 0'b11 is reserved and shall not be used. +// ENUMs: +// NATIONAL_MICROWIRE National Microwire frame format +// TI_SYNC_SERIAL TI synchronous serial frame format +// MOTOROLA_SPI Motorola SPI frame format +#define SSI_CR0_FRF_W 2 +#define SSI_CR0_FRF_M 0x00000030 +#define SSI_CR0_FRF_S 4 +#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 +#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 +#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 + +// Field: [3:0] DSS +// +// Data Size Select. +// Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used. +// ENUMs: +// 16_BIT 16-bit data +// 15_BIT 15-bit data +// 14_BIT 14-bit data +// 13_BIT 13-bit data +// 12_BIT 12-bit data +// 11_BIT 11-bit data +// 10_BIT 10-bit data +// 9_BIT 9-bit data +// 8_BIT 8-bit data +// 7_BIT 7-bit data +// 6_BIT 6-bit data +// 5_BIT 5-bit data +// 4_BIT 4-bit data +#define SSI_CR0_DSS_W 4 +#define SSI_CR0_DSS_M 0x0000000F +#define SSI_CR0_DSS_S 0 +#define SSI_CR0_DSS_16_BIT 0x0000000F +#define SSI_CR0_DSS_15_BIT 0x0000000E +#define SSI_CR0_DSS_14_BIT 0x0000000D +#define SSI_CR0_DSS_13_BIT 0x0000000C +#define SSI_CR0_DSS_12_BIT 0x0000000B +#define SSI_CR0_DSS_11_BIT 0x0000000A +#define SSI_CR0_DSS_10_BIT 0x00000009 +#define SSI_CR0_DSS_9_BIT 0x00000008 +#define SSI_CR0_DSS_8_BIT 0x00000007 +#define SSI_CR0_DSS_7_BIT 0x00000006 +#define SSI_CR0_DSS_6_BIT 0x00000005 +#define SSI_CR0_DSS_5_BIT 0x00000004 +#define SSI_CR0_DSS_4_BIT 0x00000003 + +//***************************************************************************** +// +// Register: SSI_O_CR1 +// +//***************************************************************************** +// Field: [3] SOD +// +// Slave-mode output disabled +// This bit is relevant only in the slave mode, MS=1. In multiple-slave +// systems, it is possible for an SSI master to broadcast a message to all +// slaves in the system while ensuring that only one slave drives data onto its +// serial output line. In such systems the RXD lines from multiple slaves could +// be tied together. To operate in such systems, this bitfield can be set if +// the SSI slave is not supposed to drive the TXD line: +// +// 0: SSI can drive the TXD output in slave mode. +// 1: SSI cannot drive the TXD output in slave mode. +#define SSI_CR1_SOD 0x00000008 +#define SSI_CR1_SOD_BITN 3 +#define SSI_CR1_SOD_M 0x00000008 +#define SSI_CR1_SOD_S 3 + +// Field: [2] MS +// +// Master or slave mode select. This bit can be modified only when SSI is +// disabled, SSE=0. +// ENUMs: +// SLAVE Device configured as slave +// MASTER Device configured as master +#define SSI_CR1_MS 0x00000004 +#define SSI_CR1_MS_BITN 2 +#define SSI_CR1_MS_M 0x00000004 +#define SSI_CR1_MS_S 2 +#define SSI_CR1_MS_SLAVE 0x00000004 +#define SSI_CR1_MS_MASTER 0x00000000 + +// Field: [1] SSE +// +// Synchronous serial interface enable. +// ENUMs: +// SSI_ENABLED Operation enabled +// SSI_DISABLED Operation disabled +#define SSI_CR1_SSE 0x00000002 +#define SSI_CR1_SSE_BITN 1 +#define SSI_CR1_SSE_M 0x00000002 +#define SSI_CR1_SSE_S 1 +#define SSI_CR1_SSE_SSI_ENABLED 0x00000002 +#define SSI_CR1_SSE_SSI_DISABLED 0x00000000 + +// Field: [0] LBM +// +// Loop back mode: +// +// 0: Normal serial port operation enabled. +// 1: Output of transmit serial shifter is connected to input of receive serial +// shifter internally. +#define SSI_CR1_LBM 0x00000001 +#define SSI_CR1_LBM_BITN 0 +#define SSI_CR1_LBM_M 0x00000001 +#define SSI_CR1_LBM_S 0 + +//***************************************************************************** +// +// Register: SSI_O_DR +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Transmit/receive data +// The values read from this field or written to this field must be +// right-justified when SSI is programmed for a data size that is less than 16 +// bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit +// logic. The receive logic automatically right-justifies. +#define SSI_DR_DATA_W 16 +#define SSI_DR_DATA_M 0x0000FFFF +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// Register: SSI_O_SR +// +//***************************************************************************** +// Field: [4] BSY +// +// Serial interface busy: +// +// 0: SSI is idle +// 1: SSI is currently transmitting and/or receiving a frame or the transmit +// FIFO is not empty. +#define SSI_SR_BSY 0x00000010 +#define SSI_SR_BSY_BITN 4 +#define SSI_SR_BSY_M 0x00000010 +#define SSI_SR_BSY_S 4 + +// Field: [3] RFF +// +// Receive FIFO full: +// +// 0: Receive FIFO is not full. +// 1: Receive FIFO is full. +#define SSI_SR_RFF 0x00000008 +#define SSI_SR_RFF_BITN 3 +#define SSI_SR_RFF_M 0x00000008 +#define SSI_SR_RFF_S 3 + +// Field: [2] RNE +// +// Receive FIFO not empty +// +// 0: Receive FIFO is empty. +// 1: Receive FIFO is not empty. +#define SSI_SR_RNE 0x00000004 +#define SSI_SR_RNE_BITN 2 +#define SSI_SR_RNE_M 0x00000004 +#define SSI_SR_RNE_S 2 + +// Field: [1] TNF +// +// Transmit FIFO not full: +// +// 0: Transmit FIFO is full. +// 1: Transmit FIFO is not full. +#define SSI_SR_TNF 0x00000002 +#define SSI_SR_TNF_BITN 1 +#define SSI_SR_TNF_M 0x00000002 +#define SSI_SR_TNF_S 1 + +// Field: [0] TFE +// +// Transmit FIFO empty: +// +// 0: Transmit FIFO is not empty. +// 1: Transmit FIFO is empty. +#define SSI_SR_TFE 0x00000001 +#define SSI_SR_TFE_BITN 0 +#define SSI_SR_TFE_M 0x00000001 +#define SSI_SR_TFE_S 0 + +//***************************************************************************** +// +// Register: SSI_O_CPSR +// +//***************************************************************************** +// Field: [7:0] CPSDVSR +// +// Clock prescale divisor: +// This field specifies the division factor by which the input system clock to +// SSI must be internally divided before further use. +// The value programmed into this field must be an even non-zero number +// (2-254). The least significant bit of the programmed number is hard-coded to +// zero. If an odd number is written to this register, data read back from +// this register has the least significant bit as zero. +#define SSI_CPSR_CPSDVSR_W 8 +#define SSI_CPSR_CPSDVSR_M 0x000000FF +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// Register: SSI_O_IMSC +// +//***************************************************************************** +// Field: [3] TXIM +// +// Transmit FIFO interrupt mask: +// A read returns the current mask for transmit FIFO interrupt. On a write of +// 1, the mask for transmit FIFO interrupt is set which means the interrupt +// state will be reflected in MIS.TXMIS. A write of 0 clears the mask which +// means MIS.TXMIS will not reflect the interrupt. +#define SSI_IMSC_TXIM 0x00000008 +#define SSI_IMSC_TXIM_BITN 3 +#define SSI_IMSC_TXIM_M 0x00000008 +#define SSI_IMSC_TXIM_S 3 + +// Field: [2] RXIM +// +// Receive FIFO interrupt mask: +// A read returns the current mask for receive FIFO interrupt. On a write of 1, +// the mask for receive FIFO interrupt is set which means the interrupt state +// will be reflected in MIS.RXMIS. A write of 0 clears the mask which means +// MIS.RXMIS will not reflect the interrupt. +#define SSI_IMSC_RXIM 0x00000004 +#define SSI_IMSC_RXIM_BITN 2 +#define SSI_IMSC_RXIM_M 0x00000004 +#define SSI_IMSC_RXIM_S 2 + +// Field: [1] RTIM +// +// Receive timeout interrupt mask: +// A read returns the current mask for receive timeout interrupt. On a write of +// 1, the mask for receive timeout interrupt is set which means the interrupt +// state will be reflected in MIS.RTMIS. A write of 0 clears the mask which +// means MIS.RTMIS will not reflect the interrupt. +#define SSI_IMSC_RTIM 0x00000002 +#define SSI_IMSC_RTIM_BITN 1 +#define SSI_IMSC_RTIM_M 0x00000002 +#define SSI_IMSC_RTIM_S 1 + +// Field: [0] RORIM +// +// Receive overrun interrupt mask: +// A read returns the current mask for receive overrun interrupt. On a write of +// 1, the mask for receive overrun interrupt is set which means the interrupt +// state will be reflected in MIS.RORMIS. A write of 0 clears the mask which +// means MIS.RORMIS will not reflect the interrupt. +#define SSI_IMSC_RORIM 0x00000001 +#define SSI_IMSC_RORIM_BITN 0 +#define SSI_IMSC_RORIM_M 0x00000001 +#define SSI_IMSC_RORIM_S 0 + +//***************************************************************************** +// +// Register: SSI_O_RIS +// +//***************************************************************************** +// Field: [3] TXRIS +// +// Raw transmit FIFO interrupt status: +// The transmit interrupt is asserted when there are four or fewer valid +// entries in the transmit FIFO. The transmit interrupt is not qualified with +// the SSI enable signal. Therefore one of the following ways can be used: +// - data can be written to the transmit FIFO prior to enabling the SSI and +// the +// interrupts. +// - SSI and interrupts can be enabled so that data can be written to the +// transmit FIFO by an interrupt service routine. +#define SSI_RIS_TXRIS 0x00000008 +#define SSI_RIS_TXRIS_BITN 3 +#define SSI_RIS_TXRIS_M 0x00000008 +#define SSI_RIS_TXRIS_S 3 + +// Field: [2] RXRIS +// +// Raw interrupt state of receive FIFO interrupt: +// The receive interrupt is asserted when there are four or more valid entries +// in the receive FIFO. +#define SSI_RIS_RXRIS 0x00000004 +#define SSI_RIS_RXRIS_BITN 2 +#define SSI_RIS_RXRIS_M 0x00000004 +#define SSI_RIS_RXRIS_S 2 + +// Field: [1] RTRIS +// +// Raw interrupt state of receive timeout interrupt: +// The receive timeout interrupt is asserted when the receive FIFO is not empty +// and SSI has remained idle for a fixed 32 bit period. This mechanism can be +// used to notify the user that data is still present in the receive FIFO and +// requires servicing. This interrupt is deasserted if the receive FIFO becomes +// empty by subsequent reads, or if new data is received on RXD. +// It can also be cleared by writing to ICR.RTIC. +#define SSI_RIS_RTRIS 0x00000002 +#define SSI_RIS_RTRIS_BITN 1 +#define SSI_RIS_RTRIS_M 0x00000002 +#define SSI_RIS_RTRIS_S 1 + +// Field: [0] RORRIS +// +// Raw interrupt state of receive overrun interrupt: +// The receive overrun interrupt is asserted when the FIFO is already full and +// an additional data frame is received, causing an overrun of the FIFO. Data +// is over-written in the +// receive shift register, but not the FIFO so the FIFO contents stay valid. +// It can also be cleared by writing to ICR.RORIC. +#define SSI_RIS_RORRIS 0x00000001 +#define SSI_RIS_RORRIS_BITN 0 +#define SSI_RIS_RORRIS_M 0x00000001 +#define SSI_RIS_RORRIS_S 0 + +//***************************************************************************** +// +// Register: SSI_O_MIS +// +//***************************************************************************** +// Field: [3] TXMIS +// +// Masked interrupt state of transmit FIFO interrupt: +// This field returns the masked interrupt state of transmit FIFO interrupt +// which is the AND product of raw interrupt state RIS.TXRIS and the mask +// setting IMSC.TXIM. +#define SSI_MIS_TXMIS 0x00000008 +#define SSI_MIS_TXMIS_BITN 3 +#define SSI_MIS_TXMIS_M 0x00000008 +#define SSI_MIS_TXMIS_S 3 + +// Field: [2] RXMIS +// +// Masked interrupt state of receive FIFO interrupt: +// This field returns the masked interrupt state of receive FIFO interrupt +// which is the AND product of raw interrupt state RIS.RXRIS and the mask +// setting IMSC.RXIM. +#define SSI_MIS_RXMIS 0x00000004 +#define SSI_MIS_RXMIS_BITN 2 +#define SSI_MIS_RXMIS_M 0x00000004 +#define SSI_MIS_RXMIS_S 2 + +// Field: [1] RTMIS +// +// Masked interrupt state of receive timeout interrupt: +// This field returns the masked interrupt state of receive timeout interrupt +// which is the AND product of raw interrupt state RIS.RTRIS and the mask +// setting IMSC.RTIM. +#define SSI_MIS_RTMIS 0x00000002 +#define SSI_MIS_RTMIS_BITN 1 +#define SSI_MIS_RTMIS_M 0x00000002 +#define SSI_MIS_RTMIS_S 1 + +// Field: [0] RORMIS +// +// Masked interrupt state of receive overrun interrupt: +// This field returns the masked interrupt state of receive overrun interrupt +// which is the AND product of raw interrupt state RIS.RORRIS and the mask +// setting IMSC.RORIM. +#define SSI_MIS_RORMIS 0x00000001 +#define SSI_MIS_RORMIS_BITN 0 +#define SSI_MIS_RORMIS_M 0x00000001 +#define SSI_MIS_RORMIS_S 0 + +//***************************************************************************** +// +// Register: SSI_O_ICR +// +//***************************************************************************** +// Field: [1] RTIC +// +// Clear the receive timeout interrupt: +// Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 +// has no effect. +#define SSI_ICR_RTIC 0x00000002 +#define SSI_ICR_RTIC_BITN 1 +#define SSI_ICR_RTIC_M 0x00000002 +#define SSI_ICR_RTIC_S 1 + +// Field: [0] RORIC +// +// Clear the receive overrun interrupt: +// Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). +// Writing 0 has no effect. +#define SSI_ICR_RORIC 0x00000001 +#define SSI_ICR_RORIC_BITN 0 +#define SSI_ICR_RORIC_M 0x00000001 +#define SSI_ICR_RORIC_S 0 + +//***************************************************************************** +// +// Register: SSI_O_DMACR +// +//***************************************************************************** +// Field: [1] TXDMAE +// +// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is +// enabled. +#define SSI_DMACR_TXDMAE 0x00000002 +#define SSI_DMACR_TXDMAE_BITN 1 +#define SSI_DMACR_TXDMAE_M 0x00000002 +#define SSI_DMACR_TXDMAE_S 1 + +// Field: [0] RXDMAE +// +// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is +// enabled. +#define SSI_DMACR_RXDMAE 0x00000001 +#define SSI_DMACR_RXDMAE_BITN 0 +#define SSI_DMACR_RXDMAE_M 0x00000001 +#define SSI_DMACR_RXDMAE_S 0 + + +#endif // __SSI__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_sysctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_sysctl.h new file mode 100644 index 0000000..1ddd6bb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_sysctl.h @@ -0,0 +1,49 @@ +/****************************************************************************** +* Filename: hw_sysctl.h +* Revised: 2015-03-16 14:43:45 +0100 (Mon, 16 Mar 2015) +* Revision: 42989 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + + +//***************************************************************************** +// +// The following are initial defines for the MCU clock +// +//***************************************************************************** +#define GET_MCU_CLOCK 48000000 + + +#endif // __HW_SYSCTL_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_trng.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_trng.h new file mode 100644 index 0000000..21aa93c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_trng.h @@ -0,0 +1,609 @@ +/****************************************************************************** +* Filename: hw_trng_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_TRNG_H__ +#define __HW_TRNG_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// TRNG component +// +//***************************************************************************** +// Random Number Lower Word Readout Value +#define TRNG_O_OUT0 0x00000000 + +// Random Number Upper Word Readout Value +#define TRNG_O_OUT1 0x00000004 + +// Interrupt Status +#define TRNG_O_IRQFLAGSTAT 0x00000008 + +// Interrupt Mask +#define TRNG_O_IRQFLAGMASK 0x0000000C + +// Interrupt Flag Clear +#define TRNG_O_IRQFLAGCLR 0x00000010 + +// Control +#define TRNG_O_CTL 0x00000014 + +// Configuration 0 +#define TRNG_O_CFG0 0x00000018 + +// Alarm Control +#define TRNG_O_ALARMCNT 0x0000001C + +// FRO Enable +#define TRNG_O_FROEN 0x00000020 + +// FRO De-tune Bit +#define TRNG_O_FRODETUNE 0x00000024 + +// Alarm Event +#define TRNG_O_ALARMMASK 0x00000028 + +// Alarm Shutdown +#define TRNG_O_ALARMSTOP 0x0000002C + +// LFSR Readout Value +#define TRNG_O_LFSR0 0x00000030 + +// LFSR Readout Value +#define TRNG_O_LFSR1 0x00000034 + +// LFSR Readout Value +#define TRNG_O_LFSR2 0x00000038 + +// TRNG Engine Options Information +#define TRNG_O_HWOPT 0x00000078 + +// HW Version 0 +#define TRNG_O_HWVER0 0x0000007C + +// Interrupt Status After Masking +#define TRNG_O_IRQSTATMASK 0x00001FD8 + +// HW Version 1 +#define TRNG_O_HWVER1 0x00001FE0 + +// Interrupt Set +#define TRNG_O_IRQSET 0x00001FEC + +// SW Reset Control +#define TRNG_O_SWRESET 0x00001FF0 + +// Interrupt Status +#define TRNG_O_IRQSTAT 0x00001FF8 + +//***************************************************************************** +// +// Register: TRNG_O_OUT0 +// +//***************************************************************************** +// Field: [31:0] VALUE_31_0 +// +// LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. +#define TRNG_OUT0_VALUE_31_0_W 32 +#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF +#define TRNG_OUT0_VALUE_31_0_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_OUT1 +// +//***************************************************************************** +// Field: [31:0] VALUE_63_32 +// +// MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. +#define TRNG_OUT1_VALUE_63_32_W 32 +#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF +#define TRNG_OUT1_VALUE_63_32_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGSTAT +// +//***************************************************************************** +// Field: [31] NEED_CLOCK +// +// 1: Indicates that the TRNG is busy generating entropy or is in one of its +// test modes - clocks may not be turned off and the power supply voltage must +// be kept stable. +// 0: TRNG is idle and can be shut down +#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 + +// Field: [1] SHUTDOWN_OVF +// +// 1: The number of FROs shut down (i.e. the number of '1' bits in the +// ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR +// +// Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Data are available in OUT0 and OUT1. +// +// Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears this bit to +// '0'. +// If a new number is already available in the internal register of the TRNG, +// the number is directly clocked into the result register. In this case the +// status bit is asserted again, after one clock cycle. +#define TRNG_IRQFLAGSTAT_RDY 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_BITN 0 +#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGMASK +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this +// module. +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. +#define TRNG_IRQFLAGMASK_RDY 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_BITN 0 +#define TRNG_IRQFLAGMASK_RDY_M 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGCLR +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Clear IRQFLAGSTAT.RDY. +#define TRNG_IRQFLAGCLR_RDY 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_BITN 0 +#define TRNG_IRQFLAGCLR_RDY_M 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_CTL +// +//***************************************************************************** +// Field: [31:16] STARTUP_CYCLES +// +// This field determines the number of samples (between 2^8 and 2^24) taken to +// gather entropy from the FROs during startup. If the written value of this +// field is zero, the number of samples is 2^24, otherwise the number of +// samples equals the written value times 2^8. +// +// 0x0000: 2^24 samples +// 0x0001: 1*2^8 samples +// 0x0002: 2*2^8 samples +// 0x0003: 3*2^8 samples +// ... +// 0x8000: 32768*2^8 samples +// 0xC000: 49152*2^8 samples +// ... +// 0xFFFF: 65535*2^8 samples +// +// This field can only be modified while TRNG_EN is 0. If 1 an update will be +// ignored. +#define TRNG_CTL_STARTUP_CYCLES_W 16 +#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 +#define TRNG_CTL_STARTUP_CYCLES_S 16 + +// Field: [10] TRNG_EN +// +// 0: Forces all TRNG logic back into the idle state immediately. +// 1: Starts TRNG, gathering entropy from the FROs for the number of samples +// determined by STARTUP_CYCLES. +#define TRNG_CTL_TRNG_EN 0x00000400 +#define TRNG_CTL_TRNG_EN_BITN 10 +#define TRNG_CTL_TRNG_EN_M 0x00000400 +#define TRNG_CTL_TRNG_EN_S 10 + +// Field: [2] NO_LFSR_FB +// +// 1: Remove XNOR feedback from the main LFSR, converting it into a normal +// shift register for the XOR-ed outputs of the FROs (shifting data in on the +// LSB side). A '1' also forces the LFSR to sample continuously. +// +// This bit can only be set to '1' when TEST_MODE is also set to '1' and should +// not be used for other than test purposes +#define TRNG_CTL_NO_LFSR_FB 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_BITN 2 +#define TRNG_CTL_NO_LFSR_FB_M 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_S 2 + +// Field: [1] TEST_MODE +// +// 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2 registers (the latter +// are automatically cleared before enabling access) and keeps +// IRQFLAGSTAT.NEED_CLOCK at '1'. +// +// This bit shall not be used unless you need to change the LFSR seed prior to +// creating a new random value. All other testing is done external to register +// control. +#define TRNG_CTL_TEST_MODE 0x00000002 +#define TRNG_CTL_TEST_MODE_BITN 1 +#define TRNG_CTL_TEST_MODE_M 0x00000002 +#define TRNG_CTL_TEST_MODE_S 1 + +//***************************************************************************** +// +// Register: TRNG_O_CFG0 +// +//***************************************************************************** +// Field: [31:16] MAX_REFILL_CYCLES +// +// This field determines the maximum number of samples (between 2^8 and 2^24) +// taken to re-generate entropy from the FROs after reading out a 64 bits +// random number. If the written value of this field is zero, the number of +// samples is 2^24, otherwise the number of samples equals the written value +// times 2^8. +// +// 0x0000: 2^24 samples +// 0x0001: 1*2^8 samples +// 0x0002: 2*2^8 samples +// 0x0003: 3*2^8 samples +// ... +// 0x8000: 32768*2^8 samples +// 0xC000: 49152*2^8 samples +// ... +// 0xFFFF: 65535*2^8 samples +// +// This field can only be modified while CTL.TRNG_EN is 0. +#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 +#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 +#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 + +// Field: [11:8] SMPL_DIV +// +// This field directly controls the number of clock cycles between samples +// taken from the FROs. Default value 0 indicates that samples are taken every +// clock cycle, +// maximum value 0xF takes one sample every 16 clock cycles. +// This field must be set to a value such that the slowest FRO (even under +// worst-case +// conditions) has a cycle time less than twice the sample period. +// +// This field can only be modified while CTL.TRNG_EN is '0'. +#define TRNG_CFG0_SMPL_DIV_W 4 +#define TRNG_CFG0_SMPL_DIV_M 0x00000F00 +#define TRNG_CFG0_SMPL_DIV_S 8 + +// Field: [7:0] MIN_REFILL_CYCLES +// +// This field determines the minimum number of samples (between 2^6 and 2^14) +// taken to re-generate entropy from the FROs after reading out a 64 bits +// random number. If the value of this field is zero, the number of samples is +// fixed to the value determined by the MAX_REFILL_CYCLES field, otherwise the +// minimum number of samples equals the written value times 64 (which can be up +// to 2^14). To ensure same entropy in all generated random numbers the value 0 +// should be used. Then MAX_REFILL_CYCLES controls the minimum refill interval. +// The number of samples defined here cannot be higher than the number defined +// by the 'max_refill_cycles' field (i.e. that field takes precedence). No +// random value will be created if min refill > max refill. +// +// This field can only be modified while CTL.TRNG_EN = 0. +// +// 0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers have same entropy) +// 0x01: 1*2^6 samples +// 0x02: 2*2^6 samples +// ... +// 0xFF: 255*2^6 samples +#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 +#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF +#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMCNT +// +//***************************************************************************** +// Field: [29:24] SHUTDOWN_CNT +// +// Read-only, indicates the number of '1' bits in ALARMSTOP register. +// The maximum value equals the number of FROs. +#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 + +// Field: [20:16] SHUTDOWN_THR +// +// Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The +// interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. +#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 +#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 +#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 + +// Field: [7:0] ALARM_THR +// +// Alarm detection threshold for the repeating pattern detectors on each FRO. +// An FRO 'alarm event' is declared when a repeating pattern (of up to four +// samples length) is detected continuously for the number of samples defined +// by this field's value. Reset value 0xFF should keep the number of 'alarm +// events' to a manageable level. +#define TRNG_ALARMCNT_ALARM_THR_W 8 +#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF +#define TRNG_ALARMCNT_ALARM_THR_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_FROEN +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'. +// Default state is all '1's to enable all FROs after power-up. Note that they +// are not actually started up before the CTL.TRNG_EN bit is set to '1'. +// +// Bits are automatically forced to '0' here (and cannot be written to '1') +// while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. +#define TRNG_FROEN_FRO_MASK_W 24 +#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF +#define TRNG_FROEN_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_FRODETUNE +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run +// approximately 5% faster. The value of one of these bits may only be changed +// while the corresponding FRO is turned off (by temporarily writing a '0' in +// the corresponding +// bit of the FROEN.FRO_MASK register). +#define TRNG_FRODETUNE_FRO_MASK_W 24 +#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF +#define TRNG_FRODETUNE_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMMASK +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] +// indicates FRO 'n' experienced an 'alarm event'. +#define TRNG_ALARMMASK_FRO_MASK_W 24 +#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF +#define TRNG_ALARMMASK_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMSTOP +// +//***************************************************************************** +// Field: [23:0] FRO_FLAGS +// +// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] +// indicates FRO 'n' experienced more than one 'alarm event' in quick +// succession and has been turned off. A '1' in this field forces the +// corresponding bit in FROEN.FRO_MASK to '0'. +#define TRNG_ALARMSTOP_FRO_FLAGS_W 24 +#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF +#define TRNG_ALARMSTOP_FRO_FLAGS_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR0 +// +//***************************************************************************** +// Field: [31:0] LFSR_31_0 +// +// Bits [31:0] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR0_LFSR_31_0_W 32 +#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF +#define TRNG_LFSR0_LFSR_31_0_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR1 +// +//***************************************************************************** +// Field: [31:0] LFSR_63_32 +// +// Bits [63:32] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR1_LFSR_63_32_W 32 +#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF +#define TRNG_LFSR1_LFSR_63_32_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR2 +// +//***************************************************************************** +// Field: [16:0] LFSR_80_64 +// +// Bits [80:64] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR2_LFSR_80_64_W 17 +#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF +#define TRNG_LFSR2_LFSR_80_64_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_HWOPT +// +//***************************************************************************** +// Field: [11:6] NR_OF_FROS +// +// Number of FROs implemented in this TRNG, value 24 (decimal). +#define TRNG_HWOPT_NR_OF_FROS_W 6 +#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 +#define TRNG_HWOPT_NR_OF_FROS_S 6 + +//***************************************************************************** +// +// Register: TRNG_O_HWVER0 +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VER +// +// 4 bits binary encoding of the major hardware revision number. +#define TRNG_HWVER0_HW_MAJOR_VER_W 4 +#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 +#define TRNG_HWVER0_HW_MAJOR_VER_S 24 + +// Field: [23:20] HW_MINOR_VER +// +// 4 bits binary encoding of the minor hardware revision number. +#define TRNG_HWVER0_HW_MINOR_VER_W 4 +#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 +#define TRNG_HWVER0_HW_MINOR_VER_S 20 + +// Field: [19:16] HW_PATCH_LVL +// +// 4 bits binary encoding of the hardware patch level, initial release will +// carry value zero. +#define TRNG_HWVER0_HW_PATCH_LVL_W 4 +#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 +#define TRNG_HWVER0_HW_PATCH_LVL_S 16 + +// Field: [15:8] EIP_NUM_COMPL +// +// Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. +#define TRNG_HWVER0_EIP_NUM_COMPL_W 8 +#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 +#define TRNG_HWVER0_EIP_NUM_COMPL_S 8 + +// Field: [7:0] EIP_NUM +// +// 8 bits binary encoding of the module number. This TRNG gives 0x4B. +#define TRNG_HWVER0_EIP_NUM_W 8 +#define TRNG_HWVER0_EIP_NUM_M 0x000000FF +#define TRNG_HWVER0_EIP_NUM_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSTATMASK +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with +// IRQFLAGMASK.SHUTDOWN_OVF) +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// New random value available (result of IRQFLAGSTAT.RDY AND'ed with +// IRQFLAGMASK.RDY) +#define TRNG_IRQSTATMASK_RDY 0x00000001 +#define TRNG_IRQSTATMASK_RDY_BITN 0 +#define TRNG_IRQSTATMASK_RDY_M 0x00000001 +#define TRNG_IRQSTATMASK_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_HWVER1 +// +//***************************************************************************** +// Field: [7:0] REV +// +// The revision number of this module is Rev 2.0. +#define TRNG_HWVER1_REV_W 8 +#define TRNG_HWVER1_REV_M 0x000000FF +#define TRNG_HWVER1_REV_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSET +// +//***************************************************************************** +//***************************************************************************** +// +// Register: TRNG_O_SWRESET +// +//***************************************************************************** +// Field: [0] RESET +// +// Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 +// for reset to be completed. +#define TRNG_SWRESET_RESET 0x00000001 +#define TRNG_SWRESET_RESET_BITN 0 +#define TRNG_SWRESET_RESET_M 0x00000001 +#define TRNG_SWRESET_RESET_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSTAT +// +//***************************************************************************** +// Field: [0] STAT +// +// TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and +// IRQFLAGSTAT.RDY +#define TRNG_IRQSTAT_STAT 0x00000001 +#define TRNG_IRQSTAT_STAT_BITN 0 +#define TRNG_IRQSTAT_STAT_M 0x00000001 +#define TRNG_IRQSTAT_STAT_S 0 + + +#endif // __TRNG__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_types.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_types.h new file mode 100644 index 0000000..dfa4281 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_types.h @@ -0,0 +1,123 @@ +/****************************************************************************** +* Filename: hw_types.h +* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) +* Revision: 47152 +* +* Description: Common types and macros. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +#include +#include +#include "../inc/hw_chip_def.h" + +//***************************************************************************** +// +// Common driverlib types +// +//***************************************************************************** +typedef void (* FPTR_VOID_VOID_T) (void); +typedef void (* FPTR_VOID_UINT8_T) (uint8_t); + +//***************************************************************************** +// +// This symbol forces simple driverlib functions to be inlined in the code +// instead of using function calls. +// +//***************************************************************************** +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +//***************************************************************************** +// +// C99 types only allows bitfield defintions on certain datatypes. +// +//***************************************************************************** +typedef unsigned int __UINT32; + +//***************************************************************************** +// +// Macros for direct hardware access. +// +// If using these macros the programmer should be aware of any limitations to +// the address accessed i.e. if it supports word and/or byte access. +// +//***************************************************************************** +// Word (32 bit) access to address x +// Read example : my32BitVar = HWREG(base_addr + offset) ; +// Write example : HWREG(base_addr + offset) = my32BitVar ; +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) + +// Half word (16 bit) access to address x +// Read example : my16BitVar = HWREGH(base_addr + offset) ; +// Write example : HWREGH(base_addr + offset) = my16BitVar ; +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) + +// Byte (8 bit) access to address x +// Read example : my8BitVar = HWREGB(base_addr + offset) ; +// Write example : HWREGB(base_addr + offset) = my8BitVar ; +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) + +//***************************************************************************** +// +// Macros for hardware access to bit-band supported addresses via the bit-band region. +// +// Macros calculate the corresponding address to access in the bit-band region +// based on the actual address of the memory/register and the bit number. +// +// Do NOT use these macros to access the bit-band region directly! +// +//***************************************************************************** +// Bit-band access to address x bit number b using word access (32 bit) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +// Bit-band access to address x bit number b using half word access (16 bit) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +// Bit-band access to address x bit number b using byte access (8 bit) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + + +#endif // __HW_TYPES_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_uart.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_uart.h new file mode 100644 index 0000000..05c49a7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_uart.h @@ -0,0 +1,1044 @@ +/****************************************************************************** +* Filename: hw_uart_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// UART component +// +//***************************************************************************** +// Data +#define UART_O_DR 0x00000000 + +// Status +#define UART_O_RSR 0x00000004 + +// Error Clear +#define UART_O_ECR 0x00000004 + +// Flag +#define UART_O_FR 0x00000018 + +// Integer Baud-Rate Divisor +#define UART_O_IBRD 0x00000024 + +// Fractional Baud-Rate Divisor +#define UART_O_FBRD 0x00000028 + +// Line Control +#define UART_O_LCRH 0x0000002C + +// Control +#define UART_O_CTL 0x00000030 + +// Interrupt FIFO Level Select +#define UART_O_IFLS 0x00000034 + +// Interrupt Mask Set/Clear +#define UART_O_IMSC 0x00000038 + +// Raw Interrupt Status +#define UART_O_RIS 0x0000003C + +// Masked Interrupt Status +#define UART_O_MIS 0x00000040 + +// Interrupt Clear +#define UART_O_ICR 0x00000044 + +// DMA Control +#define UART_O_DMACTL 0x00000048 + +//***************************************************************************** +// +// Register: UART_O_DR +// +//***************************************************************************** +// Field: [11] OE +// +// UART Overrun Error: +// This bit is set to 1 if data is received and the receive FIFO is already +// full. The FIFO contents remain valid because no more data is written when +// the FIFO is full, , only the contents of the shift register are overwritten. +// This is cleared to 0 once there is an empty space in the FIFO and a new +// character can be written to it. +#define UART_DR_OE 0x00000800 +#define UART_DR_OE_BITN 11 +#define UART_DR_OE_M 0x00000800 +#define UART_DR_OE_S 11 + +// Field: [10] BE +// +// UART Break Error: +// This bit is set to 1 if a break condition was detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (i.e., the oldest received data character since last read). When a +// break occurs, a 0 character is loaded into the FIFO. The next character is +// enabled after the receive data input (UARTRXD input pin) goes to a 1 +// (marking state), and the next valid start bit is received. +#define UART_DR_BE 0x00000400 +#define UART_DR_BE_BITN 10 +#define UART_DR_BE_M 0x00000400 +#define UART_DR_BE_S 10 + +// Field: [9] PE +// +// UART Parity Error: +// When set to 1, it indicates that the parity of the received data character +// does not match the parity that the LCRH.EPS and LCRH.SPS select. +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (i.e., the oldest received data character since last read). +#define UART_DR_PE 0x00000200 +#define UART_DR_PE_BITN 9 +#define UART_DR_PE_M 0x00000200 +#define UART_DR_PE_S 9 + +// Field: [8] FE +// +// UART Framing Error: +// When set to 1, it indicates that the received character did not have a valid +// stop bit (a valid stop bit is 1). +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (i.e., the oldest received data character since last read). +#define UART_DR_FE 0x00000100 +#define UART_DR_FE_BITN 8 +#define UART_DR_FE_M 0x00000100 +#define UART_DR_FE_S 8 + +// Field: [7:0] DATA +// +// Data transmitted or received: +// On writes, the transmit data character is pushed into the FIFO. +// On reads, the oldest received data character since the last read is +// returned. +#define UART_DR_DATA_W 8 +#define UART_DR_DATA_M 0x000000FF +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// Register: UART_O_RSR +// +//***************************************************************************** +// Field: [3] OE +// +// UART Overrun Error: +// This bit is set to 1 if data is received and the receive FIFO is already +// full. The FIFO contents remain valid because no more data is written when +// the FIFO is full, , only the contents of the shift register are overwritten. +// This is cleared to 0 once there is an empty space in the FIFO and a new +// character can be written to it. +#define UART_RSR_OE 0x00000008 +#define UART_RSR_OE_BITN 3 +#define UART_RSR_OE_M 0x00000008 +#define UART_RSR_OE_S 3 + +// Field: [2] BE +// +// UART Break Error: +// This bit is set to 1 if a break condition was detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +// When a break occurs, a 0 character is loaded into the FIFO. The next +// character is enabled after the receive data input (UARTRXD input pin) goes +// to a 1 (marking state), and the next valid start bit is received. +#define UART_RSR_BE 0x00000004 +#define UART_RSR_BE_BITN 2 +#define UART_RSR_BE_M 0x00000004 +#define UART_RSR_BE_S 2 + +// Field: [1] PE +// +// UART Parity Error: +// When set to 1, it indicates that the parity of the received data character +// does not match the parity that the LCRH.EPS and LCRH.SPS select. +#define UART_RSR_PE 0x00000002 +#define UART_RSR_PE_BITN 1 +#define UART_RSR_PE_M 0x00000002 +#define UART_RSR_PE_S 1 + +// Field: [0] FE +// +// UART Framing Error: +// When set to 1, it indicates that the received character did not have a valid +// stop bit (a valid stop bit is 1). +#define UART_RSR_FE 0x00000001 +#define UART_RSR_FE_BITN 0 +#define UART_RSR_FE_M 0x00000001 +#define UART_RSR_FE_S 0 + +//***************************************************************************** +// +// Register: UART_O_ECR +// +//***************************************************************************** +// Field: [3] OE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_OE 0x00000008 +#define UART_ECR_OE_BITN 3 +#define UART_ECR_OE_M 0x00000008 +#define UART_ECR_OE_S 3 + +// Field: [2] BE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_BE 0x00000004 +#define UART_ECR_BE_BITN 2 +#define UART_ECR_BE_M 0x00000004 +#define UART_ECR_BE_S 2 + +// Field: [1] PE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_PE 0x00000002 +#define UART_ECR_PE_BITN 1 +#define UART_ECR_PE_M 0x00000002 +#define UART_ECR_PE_S 1 + +// Field: [0] FE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_FE 0x00000001 +#define UART_ECR_FE_BITN 0 +#define UART_ECR_FE_M 0x00000001 +#define UART_ECR_FE_S 0 + +//***************************************************************************** +// +// Register: UART_O_FR +// +//***************************************************************************** +// Field: [7] TXFE +// +// UART Transmit FIFO Empty: +// The meaning of this bit depends on the state of LCRH.FEN . +// - If the FIFO is disabled, this bit is set when the transmit holding +// register is empty. +// - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. +// This bit does not indicate if there is data in the transmit shift register. +#define UART_FR_TXFE 0x00000080 +#define UART_FR_TXFE_BITN 7 +#define UART_FR_TXFE_M 0x00000080 +#define UART_FR_TXFE_S 7 + +// Field: [6] RXFF +// +// UART Receive FIFO Full: +// The meaning of this bit depends on the state of LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the receive holding +// register is full. +// - If the FIFO is enabled, this bit is set when the receive FIFO is full. +#define UART_FR_RXFF 0x00000040 +#define UART_FR_RXFF_BITN 6 +#define UART_FR_RXFF_M 0x00000040 +#define UART_FR_RXFF_S 6 + +// Field: [5] TXFF +// +// UART Transmit FIFO Full: +// Transmit FIFO full. The meaning of this bit depends on the state of +// LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the transmit holding +// register is full. +// - If the FIFO is enabled, this bit is set when the transmit FIFO is full. +#define UART_FR_TXFF 0x00000020 +#define UART_FR_TXFF_BITN 5 +#define UART_FR_TXFF_M 0x00000020 +#define UART_FR_TXFF_S 5 + +// Field: [4] RXFE +// +// UART Receive FIFO Empty: +// Receive FIFO empty. The meaning of this bit depends on the state of +// LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the receive holding +// register is empty. +// - If the FIFO is enabled, this bit is set when the receive FIFO is empty. +#define UART_FR_RXFE 0x00000010 +#define UART_FR_RXFE_BITN 4 +#define UART_FR_RXFE_M 0x00000010 +#define UART_FR_RXFE_S 4 + +// Field: [3] BUSY +// +// UART Busy: +// If this bit is set to 1, the UART is busy transmitting data. This bit +// remains set until the complete byte, including all the stop bits, has been +// sent from the shift register. +// This bit is set as soon as the transmit FIFO becomes non-empty, regardless +// of whether the UART is enabled or not. +#define UART_FR_BUSY 0x00000008 +#define UART_FR_BUSY_BITN 3 +#define UART_FR_BUSY_M 0x00000008 +#define UART_FR_BUSY_S 3 + +// Field: [0] CTS +// +// Clear To Send: +// This bit is the complement of the active-low UART CTS input pin. +// That is, the bit is 1 when CTS input pin is LOW. +#define UART_FR_CTS 0x00000001 +#define UART_FR_CTS_BITN 0 +#define UART_FR_CTS_M 0x00000001 +#define UART_FR_CTS_S 0 + +//***************************************************************************** +// +// Register: UART_O_IBRD +// +//***************************************************************************** +// Field: [15:0] DIVINT +// +// The integer baud rate divisor: +// The baud rate divisor is calculated using the formula below: +// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) +// Baud rate divisor must be minimum 1 and maximum 65535. +// That is, DIVINT=0 does not give a valid baud rate. +// Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be +// illegal. +// A valid value must be written to this field before the UART can be used for +// RX or TX operations. +#define UART_IBRD_DIVINT_W 16 +#define UART_IBRD_DIVINT_M 0x0000FFFF +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// Register: UART_O_FBRD +// +//***************************************************************************** +// Field: [5:0] DIVFRAC +// +// Fractional Baud-Rate Divisor: +// The baud rate divisor is calculated using the formula below: +// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) +// Baud rate divisor must be minimum 1 and maximum 65535. +// That is, IBRD.DIVINT=0 does not give a valid baud rate. +// Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be +// illegal. +// A valid value must be written to this field before the UART can be used for +// RX or TX operations. +#define UART_FBRD_DIVFRAC_W 6 +#define UART_FBRD_DIVFRAC_M 0x0000003F +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// Register: UART_O_LCRH +// +//***************************************************************************** +// Field: [7] SPS +// +// UART Stick Parity Select: +// +// 0: Stick parity is disabled +// 1: The parity bit is transmitted and checked as invert of EPS field (i.e. +// the parity bit is transmitted and checked as 1 when EPS = 0). +// +// This bit has no effect when PEN disables parity checking and generation. +#define UART_LCRH_SPS 0x00000080 +#define UART_LCRH_SPS_BITN 7 +#define UART_LCRH_SPS_M 0x00000080 +#define UART_LCRH_SPS_S 7 + +// Field: [6:5] WLEN +// +// UART Word Length: +// These bits indicate the number of data bits transmitted or received in a +// frame. +// ENUMs: +// 8 Word Length 8 bits +// 7 Word Length 7 bits +// 6 Word Length 6 bits +// 5 Word Length 5 bits +#define UART_LCRH_WLEN_W 2 +#define UART_LCRH_WLEN_M 0x00000060 +#define UART_LCRH_WLEN_S 5 +#define UART_LCRH_WLEN_8 0x00000060 +#define UART_LCRH_WLEN_7 0x00000040 +#define UART_LCRH_WLEN_6 0x00000020 +#define UART_LCRH_WLEN_5 0x00000000 + +// Field: [4] FEN +// +// UART Enable FIFOs +// ENUMs: +// EN Transmit and receive FIFO buffers are enabled +// (FIFO mode) +// DIS FIFOs are disabled (character mode) that is, the +// FIFOs become 1-byte-deep holding registers. +#define UART_LCRH_FEN 0x00000010 +#define UART_LCRH_FEN_BITN 4 +#define UART_LCRH_FEN_M 0x00000010 +#define UART_LCRH_FEN_S 4 +#define UART_LCRH_FEN_EN 0x00000010 +#define UART_LCRH_FEN_DIS 0x00000000 + +// Field: [3] STP2 +// +// UART Two Stop Bits Select: +// If this bit is set to 1, two stop bits are transmitted at the end of the +// frame. The receive logic does not check for two stop bits being received. +#define UART_LCRH_STP2 0x00000008 +#define UART_LCRH_STP2_BITN 3 +#define UART_LCRH_STP2_M 0x00000008 +#define UART_LCRH_STP2_S 3 + +// Field: [2] EPS +// +// UART Even Parity Select +// ENUMs: +// EVEN Even parity: The UART generates or checks for an +// even number of 1s in the data and parity bits. +// ODD Odd parity: The UART generates or checks for an +// odd number of 1s in the data and parity bits. +#define UART_LCRH_EPS 0x00000004 +#define UART_LCRH_EPS_BITN 2 +#define UART_LCRH_EPS_M 0x00000004 +#define UART_LCRH_EPS_S 2 +#define UART_LCRH_EPS_EVEN 0x00000004 +#define UART_LCRH_EPS_ODD 0x00000000 + +// Field: [1] PEN +// +// UART Parity Enable +// This bit controls generation and checking of parity bit. +// ENUMs: +// EN Parity checking and generation is enabled. +// DIS Parity is disabled and no parity bit is added to +// the data frame +#define UART_LCRH_PEN 0x00000002 +#define UART_LCRH_PEN_BITN 1 +#define UART_LCRH_PEN_M 0x00000002 +#define UART_LCRH_PEN_S 1 +#define UART_LCRH_PEN_EN 0x00000002 +#define UART_LCRH_PEN_DIS 0x00000000 + +// Field: [0] BRK +// +// UART Send Break +// If this bit is set to 1, a low-level is continually output on the UARTTXD +// output pin, after completing transmission of the current character. For the +// proper execution of the break command, the +// software must set this bit for at least two complete frames. For normal use, +// this bit must be cleared to 0. +#define UART_LCRH_BRK 0x00000001 +#define UART_LCRH_BRK_BITN 0 +#define UART_LCRH_BRK_M 0x00000001 +#define UART_LCRH_BRK_S 0 + +//***************************************************************************** +// +// Register: UART_O_CTL +// +//***************************************************************************** +// Field: [15] CTSEN +// +// CTS hardware flow control enable +// ENUMs: +// EN CTS hardware flow control enabled +// DIS CTS hardware flow control disabled +#define UART_CTL_CTSEN 0x00008000 +#define UART_CTL_CTSEN_BITN 15 +#define UART_CTL_CTSEN_M 0x00008000 +#define UART_CTL_CTSEN_S 15 +#define UART_CTL_CTSEN_EN 0x00008000 +#define UART_CTL_CTSEN_DIS 0x00000000 + +// Field: [14] RTSEN +// +// RTS hardware flow control enable +// ENUMs: +// EN RTS hardware flow control enabled +// DIS RTS hardware flow control disabled +#define UART_CTL_RTSEN 0x00004000 +#define UART_CTL_RTSEN_BITN 14 +#define UART_CTL_RTSEN_M 0x00004000 +#define UART_CTL_RTSEN_S 14 +#define UART_CTL_RTSEN_EN 0x00004000 +#define UART_CTL_RTSEN_DIS 0x00000000 + +// Field: [11] RTS +// +// Request to Send +// This bit is the complement of the active-low UART RTS output. That is, when +// the bit is programmed to a 1 then RTS output on the pins is LOW. +#define UART_CTL_RTS 0x00000800 +#define UART_CTL_RTS_BITN 11 +#define UART_CTL_RTS_M 0x00000800 +#define UART_CTL_RTS_S 11 + +// Field: [9] RXE +// +// UART Receive Enable +// If the UART is disabled in the middle of reception, it completes the current +// character before stopping. +// ENUMs: +// EN UART Receive enabled +// DIS UART Receive disabled +#define UART_CTL_RXE 0x00000200 +#define UART_CTL_RXE_BITN 9 +#define UART_CTL_RXE_M 0x00000200 +#define UART_CTL_RXE_S 9 +#define UART_CTL_RXE_EN 0x00000200 +#define UART_CTL_RXE_DIS 0x00000000 + +// Field: [8] TXE +// +// UART Transmit Enable +// If the UART is disabled in the middle of transmission, it completes the +// current character before stopping. +// ENUMs: +// EN UART Transmit enabled +// DIS UART Transmit disabled +#define UART_CTL_TXE 0x00000100 +#define UART_CTL_TXE_BITN 8 +#define UART_CTL_TXE_M 0x00000100 +#define UART_CTL_TXE_S 8 +#define UART_CTL_TXE_EN 0x00000100 +#define UART_CTL_TXE_DIS 0x00000000 + +// Field: [7] LBE +// +// UART Loop Back Enable: +// Enabling the loop-back mode connects the UARTTXD output from the UART to +// UARTRXD input of the UART. +// ENUMs: +// EN Loop Back enabled +// DIS Loop Back disabled +#define UART_CTL_LBE 0x00000080 +#define UART_CTL_LBE_BITN 7 +#define UART_CTL_LBE_M 0x00000080 +#define UART_CTL_LBE_S 7 +#define UART_CTL_LBE_EN 0x00000080 +#define UART_CTL_LBE_DIS 0x00000000 + +// Field: [0] UARTEN +// +// UART Enable +// ENUMs: +// EN UART enabled +// DIS UART disabled +#define UART_CTL_UARTEN 0x00000001 +#define UART_CTL_UARTEN_BITN 0 +#define UART_CTL_UARTEN_M 0x00000001 +#define UART_CTL_UARTEN_S 0 +#define UART_CTL_UARTEN_EN 0x00000001 +#define UART_CTL_UARTEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: UART_O_IFLS +// +//***************************************************************************** +// Field: [5:3] RXSEL +// +// Receive interrupt FIFO level select: +// This field sets the trigger points for the receive interrupt. Values +// 0b101-0b111 are reserved. +// ENUMs: +// 7_8 Receive FIFO becomes >= 7/8 full +// 6_8 Receive FIFO becomes >= 3/4 full +// 4_8 Receive FIFO becomes >= 1/2 full +// 2_8 Receive FIFO becomes >= 1/4 full +// 1_8 Receive FIFO becomes >= 1/8 full +#define UART_IFLS_RXSEL_W 3 +#define UART_IFLS_RXSEL_M 0x00000038 +#define UART_IFLS_RXSEL_S 3 +#define UART_IFLS_RXSEL_7_8 0x00000020 +#define UART_IFLS_RXSEL_6_8 0x00000018 +#define UART_IFLS_RXSEL_4_8 0x00000010 +#define UART_IFLS_RXSEL_2_8 0x00000008 +#define UART_IFLS_RXSEL_1_8 0x00000000 + +// Field: [2:0] TXSEL +// +// Transmit interrupt FIFO level select: +// This field sets the trigger points for the transmit interrupt. Values +// 0b101-0b111 are reserved. +// ENUMs: +// 7_8 Transmit FIFO becomes <= 7/8 full +// 6_8 Transmit FIFO becomes <= 3/4 full +// 4_8 Transmit FIFO becomes <= 1/2 full +// 2_8 Transmit FIFO becomes <= 1/4 full +// 1_8 Transmit FIFO becomes <= 1/8 full +#define UART_IFLS_TXSEL_W 3 +#define UART_IFLS_TXSEL_M 0x00000007 +#define UART_IFLS_TXSEL_S 0 +#define UART_IFLS_TXSEL_7_8 0x00000004 +#define UART_IFLS_TXSEL_6_8 0x00000003 +#define UART_IFLS_TXSEL_4_8 0x00000002 +#define UART_IFLS_TXSEL_2_8 0x00000001 +#define UART_IFLS_TXSEL_1_8 0x00000000 + +//***************************************************************************** +// +// Register: UART_O_IMSC +// +//***************************************************************************** +// Field: [10] OEIM +// +// Overrun error interrupt mask. A read returns the current mask for UART's +// overrun error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not +// reflect the interrupt. +#define UART_IMSC_OEIM 0x00000400 +#define UART_IMSC_OEIM_BITN 10 +#define UART_IMSC_OEIM_M 0x00000400 +#define UART_IMSC_OEIM_S 10 + +// Field: [9] BEIM +// +// Break error interrupt mask. A read returns the current mask for UART's break +// error interrupt. On a write of 1, the mask of the overrun error interrupt is +// set which means the interrupt state will be reflected in MIS.BEMIS. A write +// of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. +#define UART_IMSC_BEIM 0x00000200 +#define UART_IMSC_BEIM_BITN 9 +#define UART_IMSC_BEIM_M 0x00000200 +#define UART_IMSC_BEIM_S 9 + +// Field: [8] PEIM +// +// Parity error interrupt mask. A read returns the current mask for UART's +// parity error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not +// reflect the interrupt. +#define UART_IMSC_PEIM 0x00000100 +#define UART_IMSC_PEIM_BITN 8 +#define UART_IMSC_PEIM_M 0x00000100 +#define UART_IMSC_PEIM_S 8 + +// Field: [7] FEIM +// +// Framing error interrupt mask. A read returns the current mask for UART's +// framing error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not +// reflect the interrupt. +#define UART_IMSC_FEIM 0x00000080 +#define UART_IMSC_FEIM_BITN 7 +#define UART_IMSC_FEIM_M 0x00000080 +#define UART_IMSC_FEIM_S 7 + +// Field: [6] RTIM +// +// Receive timeout interrupt mask. A read returns the current mask for UART's +// receive timeout interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not +// reflect the interrupt. +// The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the +// mask is set (RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. +#define UART_IMSC_RTIM 0x00000040 +#define UART_IMSC_RTIM_BITN 6 +#define UART_IMSC_RTIM_M 0x00000040 +#define UART_IMSC_RTIM_S 6 + +// Field: [5] TXIM +// +// Transmit interrupt mask. A read returns the current mask for UART's transmit +// interrupt. On a write of 1, the mask of the overrun error interrupt is set +// which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 +// clears the mask which means MIS.TXMIS will not reflect the interrupt. +#define UART_IMSC_TXIM 0x00000020 +#define UART_IMSC_TXIM_BITN 5 +#define UART_IMSC_TXIM_M 0x00000020 +#define UART_IMSC_TXIM_S 5 + +// Field: [4] RXIM +// +// Receive interrupt mask. A read returns the current mask for UART's receive +// interrupt. On a write of 1, the mask of the overrun error interrupt is set +// which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 +// clears the mask which means MIS.RXMIS will not reflect the interrupt. +#define UART_IMSC_RXIM 0x00000010 +#define UART_IMSC_RXIM_BITN 4 +#define UART_IMSC_RXIM_M 0x00000010 +#define UART_IMSC_RXIM_S 4 + +// Field: [1] CTSMIM +// +// Clear to Send (CTS) modem interrupt mask. A read returns the current mask +// for UART's clear to send interrupt. On a write of 1, the mask of the overrun +// error interrupt is set which means the interrupt state will be reflected in +// MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not +// reflect the interrupt. +#define UART_IMSC_CTSMIM 0x00000002 +#define UART_IMSC_CTSMIM_BITN 1 +#define UART_IMSC_CTSMIM_M 0x00000002 +#define UART_IMSC_CTSMIM_S 1 + +//***************************************************************************** +// +// Register: UART_O_RIS +// +//***************************************************************************** +// Field: [10] OERIS +// +// Overrun error interrupt status: +// This field returns the raw interrupt state of UART's overrun error +// interrupt. Overrun error occurs if data is received and the receive FIFO is +// full. +#define UART_RIS_OERIS 0x00000400 +#define UART_RIS_OERIS_BITN 10 +#define UART_RIS_OERIS_M 0x00000400 +#define UART_RIS_OERIS_S 10 + +// Field: [9] BERIS +// +// Break error interrupt status: +// This field returns the raw interrupt state of UART's break error interrupt. +// Break error is set when a break condition is detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +#define UART_RIS_BERIS 0x00000200 +#define UART_RIS_BERIS_BITN 9 +#define UART_RIS_BERIS_M 0x00000200 +#define UART_RIS_BERIS_S 9 + +// Field: [8] PERIS +// +// Parity error interrupt status: +// This field returns the raw interrupt state of UART's parity error interrupt. +// Parity error is set if the parity of the received data character does not +// match the parity that the LCRH.EPS and LCRH.SPS select. +#define UART_RIS_PERIS 0x00000100 +#define UART_RIS_PERIS_BITN 8 +#define UART_RIS_PERIS_M 0x00000100 +#define UART_RIS_PERIS_S 8 + +// Field: [7] FERIS +// +// Framing error interrupt status: +// This field returns the raw interrupt state of UART's framing error +// interrupt. Framing error is set if the received character does not have a +// valid stop bit (a valid stop bit is 1). +#define UART_RIS_FERIS 0x00000080 +#define UART_RIS_FERIS_BITN 7 +#define UART_RIS_FERIS_M 0x00000080 +#define UART_RIS_FERIS_S 7 + +// Field: [6] RTRIS +// +// Receive timeout interrupt status: +// This field returns the raw interrupt state of UART's receive timeout +// interrupt. The receive timeout interrupt is asserted when the receive FIFO +// is not empty, and no more data is received during a 32-bit period. The +// receive timeout interrupt is cleared either when the FIFO becomes empty +// through reading all the data, or when a 1 is written to ICR.RTIC. +// The raw interrupt for receive timeout cannot be set unless the mask is set +// (IMSC.RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from MIS.RTMIS and RTRIS. +#define UART_RIS_RTRIS 0x00000040 +#define UART_RIS_RTRIS_BITN 6 +#define UART_RIS_RTRIS_M 0x00000040 +#define UART_RIS_RTRIS_S 6 + +// Field: [5] TXRIS +// +// Transmit interrupt status: +// This field returns the raw interrupt state of UART's transmit interrupt. +// When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if +// the number of bytes in transmit FIFO is equal to or lower than the +// programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by +// writing data to the transmit FIFO until it becomes greater than the trigger +// level, or by clearing the interrupt through ICR.TXIC. +// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one +// location, the transmit interrupt is asserted if there is no data present in +// the transmitters single location. It is cleared by performing a single write +// to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. +#define UART_RIS_TXRIS 0x00000020 +#define UART_RIS_TXRIS_BITN 5 +#define UART_RIS_TXRIS_M 0x00000020 +#define UART_RIS_TXRIS_S 5 + +// Field: [4] RXRIS +// +// Receive interrupt status: +// This field returns the raw interrupt state of UART's receive interrupt. +// When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if +// the receive FIFO reaches the programmed trigger +// level (IFLS.RXSEL). The receive interrupt is cleared by reading data from +// the receive FIFO until it becomes less than the trigger level, or by +// clearing the interrupt through ICR.RXIC. +// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one +// location, the receive interrupt is asserted if data is received +// thereby filling the location. The receive interrupt is cleared by performing +// a single read of the receive FIFO, or by clearing the interrupt through +// ICR.RXIC. +#define UART_RIS_RXRIS 0x00000010 +#define UART_RIS_RXRIS_BITN 4 +#define UART_RIS_RXRIS_M 0x00000010 +#define UART_RIS_RXRIS_S 4 + +// Field: [1] CTSRMIS +// +// Clear to Send (CTS) modem interrupt status: +// This field returns the raw interrupt state of UART's clear to send +// interrupt. +#define UART_RIS_CTSRMIS 0x00000002 +#define UART_RIS_CTSRMIS_BITN 1 +#define UART_RIS_CTSRMIS_M 0x00000002 +#define UART_RIS_CTSRMIS_S 1 + +//***************************************************************************** +// +// Register: UART_O_MIS +// +//***************************************************************************** +// Field: [10] OEMIS +// +// Overrun error masked interrupt status: +// This field returns the masked interrupt state of the overrun interrupt which +// is the AND product of raw interrupt state RIS.OERIS and the mask setting +// IMSC.OEIM. +#define UART_MIS_OEMIS 0x00000400 +#define UART_MIS_OEMIS_BITN 10 +#define UART_MIS_OEMIS_M 0x00000400 +#define UART_MIS_OEMIS_S 10 + +// Field: [9] BEMIS +// +// Break error masked interrupt status: +// This field returns the masked interrupt state of the break error interrupt +// which is the AND product of raw interrupt state RIS.BERIS and the mask +// setting IMSC.BEIM. +#define UART_MIS_BEMIS 0x00000200 +#define UART_MIS_BEMIS_BITN 9 +#define UART_MIS_BEMIS_M 0x00000200 +#define UART_MIS_BEMIS_S 9 + +// Field: [8] PEMIS +// +// Parity error masked interrupt status: +// This field returns the masked interrupt state of the parity error interrupt +// which is the AND product of raw interrupt state RIS.PERIS and the mask +// setting IMSC.PEIM. +#define UART_MIS_PEMIS 0x00000100 +#define UART_MIS_PEMIS_BITN 8 +#define UART_MIS_PEMIS_M 0x00000100 +#define UART_MIS_PEMIS_S 8 + +// Field: [7] FEMIS +// +// Framing error masked interrupt status: Returns the masked interrupt state of +// the framing error interrupt which is the AND product of raw interrupt state +// RIS.FERIS and the mask setting IMSC.FEIM. +#define UART_MIS_FEMIS 0x00000080 +#define UART_MIS_FEMIS_BITN 7 +#define UART_MIS_FEMIS_M 0x00000080 +#define UART_MIS_FEMIS_S 7 + +// Field: [6] RTMIS +// +// Receive timeout masked interrupt status: +// Returns the masked interrupt state of the receive timeout interrupt. +// The raw interrupt for receive timeout cannot be set unless the mask is set +// (IMSC.RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from RTMIS and RIS.RTRIS. +#define UART_MIS_RTMIS 0x00000040 +#define UART_MIS_RTMIS_BITN 6 +#define UART_MIS_RTMIS_M 0x00000040 +#define UART_MIS_RTMIS_S 6 + +// Field: [5] TXMIS +// +// Transmit masked interrupt status: +// This field returns the masked interrupt state of the transmit interrupt +// which is the AND product of raw interrupt state RIS.TXRIS and the mask +// setting IMSC.TXIM. +#define UART_MIS_TXMIS 0x00000020 +#define UART_MIS_TXMIS_BITN 5 +#define UART_MIS_TXMIS_M 0x00000020 +#define UART_MIS_TXMIS_S 5 + +// Field: [4] RXMIS +// +// Receive masked interrupt status: +// This field returns the masked interrupt state of the receive interrupt +// which is the AND product of raw interrupt state RIS.RXRIS and the mask +// setting IMSC.RXIM. +#define UART_MIS_RXMIS 0x00000010 +#define UART_MIS_RXMIS_BITN 4 +#define UART_MIS_RXMIS_M 0x00000010 +#define UART_MIS_RXMIS_S 4 + +// Field: [1] CTSMMIS +// +// Clear to Send (CTS) modem masked interrupt status: +// This field returns the masked interrupt state of the clear to send interrupt +// which is the AND product of raw interrupt state RIS.CTSRMIS and the mask +// setting IMSC.CTSMIM. +#define UART_MIS_CTSMMIS 0x00000002 +#define UART_MIS_CTSMMIS_BITN 1 +#define UART_MIS_CTSMMIS_M 0x00000002 +#define UART_MIS_CTSMMIS_S 1 + +//***************************************************************************** +// +// Register: UART_O_ICR +// +//***************************************************************************** +// Field: [10] OEIC +// +// Overrun error interrupt clear: +// Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). +// Writing 0 has no effect. +#define UART_ICR_OEIC 0x00000400 +#define UART_ICR_OEIC_BITN 10 +#define UART_ICR_OEIC_M 0x00000400 +#define UART_ICR_OEIC_S 10 + +// Field: [9] BEIC +// +// Break error interrupt clear: +// Writing 1 to this field clears the break error interrupt (RIS.BERIS). +// Writing 0 has no effect. +#define UART_ICR_BEIC 0x00000200 +#define UART_ICR_BEIC_BITN 9 +#define UART_ICR_BEIC_M 0x00000200 +#define UART_ICR_BEIC_S 9 + +// Field: [8] PEIC +// +// Parity error interrupt clear: +// Writing 1 to this field clears the parity error interrupt (RIS.PERIS). +// Writing 0 has no effect. +#define UART_ICR_PEIC 0x00000100 +#define UART_ICR_PEIC_BITN 8 +#define UART_ICR_PEIC_M 0x00000100 +#define UART_ICR_PEIC_S 8 + +// Field: [7] FEIC +// +// Framing error interrupt clear: +// Writing 1 to this field clears the framing error interrupt (RIS.FERIS). +// Writing 0 has no effect. +#define UART_ICR_FEIC 0x00000080 +#define UART_ICR_FEIC_BITN 7 +#define UART_ICR_FEIC_M 0x00000080 +#define UART_ICR_FEIC_S 7 + +// Field: [6] RTIC +// +// Receive timeout interrupt clear: +// Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). +// Writing 0 has no effect. +#define UART_ICR_RTIC 0x00000040 +#define UART_ICR_RTIC_BITN 6 +#define UART_ICR_RTIC_M 0x00000040 +#define UART_ICR_RTIC_S 6 + +// Field: [5] TXIC +// +// Transmit interrupt clear: +// Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 +// has no effect. +#define UART_ICR_TXIC 0x00000020 +#define UART_ICR_TXIC_BITN 5 +#define UART_ICR_TXIC_M 0x00000020 +#define UART_ICR_TXIC_S 5 + +// Field: [4] RXIC +// +// Receive interrupt clear: +// Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 +// has no effect. +#define UART_ICR_RXIC 0x00000010 +#define UART_ICR_RXIC_BITN 4 +#define UART_ICR_RXIC_M 0x00000010 +#define UART_ICR_RXIC_S 4 + +// Field: [1] CTSMIC +// +// Clear to Send (CTS) modem interrupt clear: +// Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). +// Writing 0 has no effect. +#define UART_ICR_CTSMIC 0x00000002 +#define UART_ICR_CTSMIC_BITN 1 +#define UART_ICR_CTSMIC_M 0x00000002 +#define UART_ICR_CTSMIC_S 1 + +//***************************************************************************** +// +// Register: UART_O_DMACTL +// +//***************************************************************************** +// Field: [2] DMAONERR +// +// DMA on error. If this bit is set to 1, the DMA receive request outputs (for +// single and burst requests) are disabled when the UART error interrupt is +// asserted (more specifically if any of the error interrupts RIS.PERIS, +// RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). +#define UART_DMACTL_DMAONERR 0x00000004 +#define UART_DMACTL_DMAONERR_BITN 2 +#define UART_DMACTL_DMAONERR_M 0x00000004 +#define UART_DMACTL_DMAONERR_S 2 + +// Field: [1] TXDMAE +// +// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is +// enabled. +#define UART_DMACTL_TXDMAE 0x00000002 +#define UART_DMACTL_TXDMAE_BITN 1 +#define UART_DMACTL_TXDMAE_M 0x00000002 +#define UART_DMACTL_TXDMAE_S 1 + +// Field: [0] RXDMAE +// +// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is +// enabled. +#define UART_DMACTL_RXDMAE 0x00000001 +#define UART_DMACTL_RXDMAE_BITN 0 +#define UART_DMACTL_RXDMAE_M 0x00000001 +#define UART_DMACTL_RXDMAE_S 0 + + +#endif // __UART__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_udma.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_udma.h new file mode 100644 index 0000000..63d0a54 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_udma.h @@ -0,0 +1,575 @@ +/****************************************************************************** +* Filename: hw_udma_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_UDMA_H__ +#define __HW_UDMA_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// UDMA component +// +//***************************************************************************** +// Status +#define UDMA_O_STATUS 0x00000000 + +// Configuration +#define UDMA_O_CFG 0x00000004 + +// Channel Control Data Base Pointer +#define UDMA_O_CTRL 0x00000008 + +// Channel Alternate Control Data Base Pointer +#define UDMA_O_ALTCTRL 0x0000000C + +// Channel Wait On Request Status +#define UDMA_O_WAITONREQ 0x00000010 + +// Channel Software Request +#define UDMA_O_SOFTREQ 0x00000014 + +// Channel Set UseBurst +#define UDMA_O_SETBURST 0x00000018 + +// Channel Clear UseBurst +#define UDMA_O_CLEARBURST 0x0000001C + +// Channel Set Request Mask +#define UDMA_O_SETREQMASK 0x00000020 + +// Clear Channel Request Mask +#define UDMA_O_CLEARREQMASK 0x00000024 + +// Set Channel Enable +#define UDMA_O_SETCHANNELEN 0x00000028 + +// Clear Channel Enable +#define UDMA_O_CLEARCHANNELEN 0x0000002C + +// Channel Set Primary-Alternate +#define UDMA_O_SETCHNLPRIALT 0x00000030 + +// Channel Clear Primary-Alternate +#define UDMA_O_CLEARCHNLPRIALT 0x00000034 + +// Set Channel Priority +#define UDMA_O_SETCHNLPRIORITY 0x00000038 + +// Clear Channel Priority +#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C + +// Error Status and Clear +#define UDMA_O_ERROR 0x0000004C + +// Channel Request Done +#define UDMA_O_REQDONE 0x00000504 + +// Channel Request Done Mask +#define UDMA_O_DONEMASK 0x00000520 + +//***************************************************************************** +// +// Register: UDMA_O_STATUS +// +//***************************************************************************** +// Field: [31:28] TEST +// +// +// 0x0: Controller does not include the integration test logic +// 0x1: Controller includes the integration test logic +// 0x2: Undefined +// ... +// 0xF: Undefined +#define UDMA_STATUS_TEST_W 4 +#define UDMA_STATUS_TEST_M 0xF0000000 +#define UDMA_STATUS_TEST_S 28 + +// Field: [20:16] TOTALCHANNELS +// +// Register value returns number of available uDMA channels minus one. For +// example a read out value of: +// +// 0x00: Show that the controller is configured to use 1 uDMA channel +// 0x01: Shows that the controller is configured to use 2 uDMA channels +// ... +// 0x1F: Shows that the controller is configured to use 32 uDMA channels +// (32-1=31=0x1F) +#define UDMA_STATUS_TOTALCHANNELS_W 5 +#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 +#define UDMA_STATUS_TOTALCHANNELS_S 16 + +// Field: [7:4] STATE +// +// Current state of the control state machine. State can be one of the +// following: +// +// 0x0: Idle +// 0x1: Reading channel controller data +// 0x2: Reading source data end pointer +// 0x3: Reading destination data end pointer +// 0x4: Reading source data +// 0x5: Writing destination data +// 0x6: Waiting for uDMA request to clear +// 0x7: Writing channel controller data +// 0x8: Stalled +// 0x9: Done +// 0xA: Peripheral scatter-gather transition +// 0xB: Undefined +// ... +// 0xF: Undefined. +#define UDMA_STATUS_STATE_W 4 +#define UDMA_STATUS_STATE_M 0x000000F0 +#define UDMA_STATUS_STATE_S 4 + +// Field: [0] MASTERENABLE +// +// Shows the enable status of the controller as configured by CFG.MASTERENABLE: +// +// 0: Controller is disabled +// 1: Controller is enabled +#define UDMA_STATUS_MASTERENABLE 0x00000001 +#define UDMA_STATUS_MASTERENABLE_BITN 0 +#define UDMA_STATUS_MASTERENABLE_M 0x00000001 +#define UDMA_STATUS_MASTERENABLE_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CFG +// +//***************************************************************************** +// Field: [7:5] PRTOCTRL +// +// Sets the AHB-Lite bus protocol protection state by controlling the AHB +// signal HProt[3:1] as follows: +// +// Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring. +// Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring. +// Bit [5] Controls HProt[1] to indicate if a privileged access is occurring. +// +// When bit [n] = 1 then the corresponding HProt bit is high. +// When bit [n] = 0 then the corresponding HProt bit is low. +// +// This field controls HProt[3:1] signal for all transactions initiated by uDMA +// except two transactions below: +// - the read from the address indicated by source address pointer +// - the write to the address indicated by destination address pointer +// HProt[3:1] for these two exceptions can be controlled by dedicated fields in +// the channel configutation descriptor. +#define UDMA_CFG_PRTOCTRL_W 3 +#define UDMA_CFG_PRTOCTRL_M 0x000000E0 +#define UDMA_CFG_PRTOCTRL_S 5 + +// Field: [0] MASTERENABLE +// +// Enables the controller: +// +// 0: Disables the controller +// 1: Enables the controller +#define UDMA_CFG_MASTERENABLE 0x00000001 +#define UDMA_CFG_MASTERENABLE_BITN 0 +#define UDMA_CFG_MASTERENABLE_M 0x00000001 +#define UDMA_CFG_MASTERENABLE_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CTRL +// +//***************************************************************************** +// Field: [31:10] BASEPTR +// +// This register point to the base address for the primary data structures of +// each DMA channel. This is not stored in module, but in system memory, thus +// space must be allocated for this usage when DMA is in usage +#define UDMA_CTRL_BASEPTR_W 22 +#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 +#define UDMA_CTRL_BASEPTR_S 10 + +//***************************************************************************** +// +// Register: UDMA_O_ALTCTRL +// +//***************************************************************************** +// Field: [31:0] BASEPTR +// +// This register shows the base address for the alternate data structures and +// is calculated by module, thus read only +#define UDMA_ALTCTRL_BASEPTR_W 32 +#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF +#define UDMA_ALTCTRL_BASEPTR_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_WAITONREQ +// +//***************************************************************************** +// Field: [31:0] CHNLSTATUS +// +// Channel wait on request status: +// +// Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, +// this channel may come out of active state even if request is still present. +// Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it +// keeps channel Ch in active state until the requests are deasserted. This +// handshake is necessary for channels where the requester is in an +// asynchronous domain or can run at slower clock speed than uDMA +#define UDMA_WAITONREQ_CHNLSTATUS_W 32 +#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF +#define UDMA_WAITONREQ_CHNLSTATUS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SOFTREQ +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to generate a software uDMA request on the +// corresponding uDMA channel +// +// Bit [Ch] = 0: Does not create a uDMA request for channel Ch +// Bit [Ch] = 1: Creates a uDMA request for channel Ch +// +// Writing to a bit where a uDMA channel is not implemented does not create a +// uDMA request for that channel +#define UDMA_SOFTREQ_CHNLS_W 32 +#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF +#define UDMA_SOFTREQ_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETBURST +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the useburst status, or disables individual channels from generating +// single uDMA requests. The value R is the arbitration rate and stored in the +// controller data structure. +// +// Read as: +// +// Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on +// channel C. The controller performs 2^R, or single, bus transfers. +// +// Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. +// The controller only responds to burst transfer requests and performs 2^R +// transfers. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0. +// Bit [Ch] = 1: Disables single transfer requests on channel Ch. The +// controller performs 2^R transfers for burst requests. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETBURST_CHNLS_W 32 +#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_SETBURST_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARBURST +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to enable single transfer requests. +// +// Write as: +// +// Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer +// requests. +// +// Bit [Ch] = 1: Enables single transfer requests on channel Ch. +// +// Writing to a bit where a DMA channel is not implemented has no effect. +#define UDMA_CLEARBURST_CHNLS_W 32 +#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARBURST_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETREQMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the burst and single request mask status, or disables the +// corresponding channel from generating uDMA requests. +// +// Read as: +// Bit [Ch] = 0: External requests are enabled for channel Ch. +// Bit [Ch] = 1: External requests are disabled for channel Ch. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests. +// Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA single +// request channel [C] input from generating uDMA requests. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETREQMASK_CHNLS_W 32 +#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_SETREQMASK_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARREQMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to enable DMA request for the channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel C from +// generating requests. +// Bit [Ch] = 1: Enables channel [C] to generate DMA requests. +// +// Writing to a bit where a DMA channel is not implemented has no effect. +#define UDMA_CLEARREQMASK_CHNLS_W 32 +#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARREQMASK_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHANNELEN +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the enable status of the channels, or enables the corresponding +// channels. +// +// Read as: +// Bit [Ch] = 0: Channel Ch is disabled. +// Bit [Ch] = 1: Channel Ch is enabled. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel +// Bit [Ch] = 1: Enables channel Ch +// +// Writing to a bit where a DMA channel is not implemented has no effect +#define UDMA_SETCHANNELEN_CHNLS_W 32 +#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHANNELEN_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHANNELEN +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to disable the corresponding uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels. +// Bit [Ch] = 1: Disables channel Ch +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHANNELEN_CHNLS_W 32 +#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHANNELEN_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHNLPRIALT +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the channel control data structure status, or selects the alternate +// data structure for the corresponding uDMA channel. +// +// Read as: +// Bit [Ch] = 0: uDMA channel Ch is using the primary data structure. +// Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel +// Bit [Ch] = 1: Selects the alternate data structure for channel Ch +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETCHNLPRIALT_CHNLS_W 32 +#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIALT_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHNLPRIALT +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Clears the appropriate bit to select the primary data structure for the +// corresponding uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate +// data structure. +// Bit [Ch] = 1: Selects the primary data structure for channel Ch. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHNLPRIORITY +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the channel priority mask status, or sets the channel priority to +// high. +// +// Read as: +// Bit [Ch] = 0: uDMA channel Ch is using the default priority level. +// Bit [Ch] = 1: uDMA channel Ch is using a high priority level. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch +// to the default priority level. +// Bit [Ch] = 1: Channel Ch uses the high priority level. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETCHNLPRIORITY_CHNLS_W 32 +#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIORITY_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHNLPRIORITY +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Clear the appropriate bit to select the default priority level for the +// specified uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to +// the high priority level. +// Bit [Ch] = 1: Channel Ch uses the default priority level. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_ERROR +// +//***************************************************************************** +// Field: [0] STATUS +// +// Returns the status of bus error flag in uDMA, or clears this bit +// +// Read as: +// +// 0: No bus error detected +// 1: Bus error detected +// +// Write as: +// +// 0: No effect, status of bus error flag is unchanged. +// 1: Clears the bus error flag. +#define UDMA_ERROR_STATUS 0x00000001 +#define UDMA_ERROR_STATUS_BITN 0 +#define UDMA_ERROR_STATUS_M 0x00000001 +#define UDMA_ERROR_STATUS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_REQDONE +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Reflects the uDMA done status for the given channel, channel [Ch]. It's a +// sticky done bit. Unless cleared by writing a 1, it holds the value of 1. +// +// Read as: +// Bit [Ch] = 0: Request has not completed for channel Ch +// Bit [Ch] = 1: Request has completed for the channel Ch +// +// Writing a 1 to individual bits would clear the corresponding bit. +// +// Write as: +// Bit [Ch] = 0: No effect. +// Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 +#define UDMA_REQDONE_CHNLS_W 32 +#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF +#define UDMA_REQDONE_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_DONEMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Controls the propagation of the uDMA done and active state to the assigned +// peripheral. Specifically used for software channels. +// +// Read as: +// Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from +// reaching to the peripherals. +// Note that the uDMA done state for channel [Ch] is blocked from contributing +// to generation of combined uDMA done signal +// +// Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from +// reaching to the peripherals. +// Note that the uDMA done state for channel [Ch] is not blocked from +// contributing to generation of combined uDMA done signal +// +// Write as: +// Bit [Ch] = 0: Allows uDMA done and active stat to propagate to the +// peripherals. +// Note that this disables uDMA done state for channel [Ch] from contributing +// to generation of combined uDMA done signal +// +// Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the +// peripherals. +// Note that this enables uDMA done for channel [Ch] to contribute to +// generation of combined uDMA done signal. +#define UDMA_DONEMASK_CHNLS_W 32 +#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_DONEMASK_CHNLS_S 0 + + +#endif // __UDMA__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_vims.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_vims.h new file mode 100644 index 0000000..8ba5b60 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_vims.h @@ -0,0 +1,206 @@ +/****************************************************************************** +* Filename: hw_vims_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_VIMS_H__ +#define __HW_VIMS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// VIMS component +// +//***************************************************************************** +// Status +#define VIMS_O_STAT 0x00000000 + +// Control +#define VIMS_O_CTL 0x00000004 + +//***************************************************************************** +// +// Register: VIMS_O_STAT +// +//***************************************************************************** +// Field: [5] IDCODE_LB_DIS +// +// Icode/Dcode flash line buffer status +// +// 0: Enabled or in transition to disabled +// 1: Disabled and flushed +#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 +#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_S 5 + +// Field: [4] SYSBUS_LB_DIS +// +// Sysbus flash line buffer control +// +// 0: Enabled or in transition to disabled +// 1: Disabled and flushed +#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 +#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_S 4 + +// Field: [3] MODE_CHANGING +// +// VIMS mode change status +// +// 0: VIMS is in the mode defined by MODE +// 1: VIMS is in the process of changing to the mode given in CTL.MODE +#define VIMS_STAT_MODE_CHANGING 0x00000008 +#define VIMS_STAT_MODE_CHANGING_BITN 3 +#define VIMS_STAT_MODE_CHANGING_M 0x00000008 +#define VIMS_STAT_MODE_CHANGING_S 3 + +// Field: [2] INV +// +// This bit is set when invalidation of the cache memory is active / ongoing +#define VIMS_STAT_INV 0x00000004 +#define VIMS_STAT_INV_BITN 2 +#define VIMS_STAT_INV_M 0x00000004 +#define VIMS_STAT_INV_S 2 + +// Field: [1:0] MODE +// +// Current VIMS mode +// ENUMs: +// OFF VIMS Off mode +// CACHE VIMS Cache mode +// GPRAM VIMS GPRAM mode +#define VIMS_STAT_MODE_W 2 +#define VIMS_STAT_MODE_M 0x00000003 +#define VIMS_STAT_MODE_S 0 +#define VIMS_STAT_MODE_OFF 0x00000003 +#define VIMS_STAT_MODE_CACHE 0x00000001 +#define VIMS_STAT_MODE_GPRAM 0x00000000 + +//***************************************************************************** +// +// Register: VIMS_O_CTL +// +//***************************************************************************** +// Field: [31] STATS_CLR +// +// Set this bit to clear statistic counters. +#define VIMS_CTL_STATS_CLR 0x80000000 +#define VIMS_CTL_STATS_CLR_BITN 31 +#define VIMS_CTL_STATS_CLR_M 0x80000000 +#define VIMS_CTL_STATS_CLR_S 31 + +// Field: [30] STATS_EN +// +// Set this bit to enable statistic counters. +#define VIMS_CTL_STATS_EN 0x40000000 +#define VIMS_CTL_STATS_EN_BITN 30 +#define VIMS_CTL_STATS_EN_M 0x40000000 +#define VIMS_CTL_STATS_EN_S 30 + +// Field: [29] DYN_CG_EN +// +// 0: The in-built clock gate functionality is bypassed. +// 1: The in-built clock gate functionality is enabled, automatically gating +// the clock when not needed. +#define VIMS_CTL_DYN_CG_EN 0x20000000 +#define VIMS_CTL_DYN_CG_EN_BITN 29 +#define VIMS_CTL_DYN_CG_EN_M 0x20000000 +#define VIMS_CTL_DYN_CG_EN_S 29 + +// Field: [5] IDCODE_LB_DIS +// +// Icode/Dcode flash line buffer control +// +// 0: Enable +// 1: Disable +#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 +#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_S 5 + +// Field: [4] SYSBUS_LB_DIS +// +// Sysbus flash line buffer control +// +// 0: Enable +// 1: Disable +#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 +#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_S 4 + +// Field: [3] ARB_CFG +// +// Icode/Dcode and sysbus arbitation scheme +// +// 0: Static arbitration (icode/docde > sysbus) +// 1: Round-robin arbitration +#define VIMS_CTL_ARB_CFG 0x00000008 +#define VIMS_CTL_ARB_CFG_BITN 3 +#define VIMS_CTL_ARB_CFG_M 0x00000008 +#define VIMS_CTL_ARB_CFG_S 3 + +// Field: [2] PREF_EN +// +// Tag prefetch control +// +// 0: Disabled +// 1: Enabled +#define VIMS_CTL_PREF_EN 0x00000004 +#define VIMS_CTL_PREF_EN_BITN 2 +#define VIMS_CTL_PREF_EN_M 0x00000004 +#define VIMS_CTL_PREF_EN_S 2 + +// Field: [1:0] MODE +// +// VIMS mode request. +// Write accesses to this field will be blocked while STAT.MODE_CHANGING is set +// to 1. +// Note: Transaction from CACHE mode to GPRAM mode should be done through OFF +// mode to minimize flash block delay. +// ENUMs: +// OFF VIMS Off mode +// CACHE VIMS Cache mode +// GPRAM VIMS GPRAM mode +#define VIMS_CTL_MODE_W 2 +#define VIMS_CTL_MODE_M 0x00000003 +#define VIMS_CTL_MODE_S 0 +#define VIMS_CTL_MODE_OFF 0x00000003 +#define VIMS_CTL_MODE_CACHE 0x00000001 +#define VIMS_CTL_MODE_GPRAM 0x00000000 + + +#endif // __VIMS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_wdt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_wdt.h new file mode 100644 index 0000000..3a67579 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_wdt.h @@ -0,0 +1,290 @@ +/****************************************************************************** +* Filename: hw_wdt_h +* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) +* Revision: 48345 +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_WDT_H__ +#define __HW_WDT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// WDT component +// +//***************************************************************************** +// Configuration +#define WDT_O_LOAD 0x00000000 + +// Current Count Value +#define WDT_O_VALUE 0x00000004 + +// Control +#define WDT_O_CTL 0x00000008 + +// Interrupt Clear +#define WDT_O_ICR 0x0000000C + +// Raw Interrupt Status +#define WDT_O_RIS 0x00000010 + +// Masked Interrupt Status +#define WDT_O_MIS 0x00000014 + +// Test Mode +#define WDT_O_TEST 0x00000418 + +// Interrupt Cause Test Mode +#define WDT_O_INT_CAUS 0x0000041C + +// Lock +#define WDT_O_LOCK 0x00000C00 + +//***************************************************************************** +// +// Register: WDT_O_LOAD +// +//***************************************************************************** +// Field: [31:0] WDTLOAD +// +// This register is the 32-bit interval value used by the 32-bit counter. When +// this register is written, the value is immediately loaded and the counter is +// restarted to count down from the new value. If this register is loaded with +// 0x0000.0000, an interrupt is immediately generated. +#define WDT_LOAD_WDTLOAD_W 32 +#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF +#define WDT_LOAD_WDTLOAD_S 0 + +//***************************************************************************** +// +// Register: WDT_O_VALUE +// +//***************************************************************************** +// Field: [31:0] WDTVALUE +// +// This register contains the current count value of the timer. +#define WDT_VALUE_WDTVALUE_W 32 +#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF +#define WDT_VALUE_WDTVALUE_S 0 + +//***************************************************************************** +// +// Register: WDT_O_CTL +// +//***************************************************************************** +// Field: [2] INTTYPE +// +// WDT Interrupt Type +// +// 0: WDT interrupt is a standard interrupt. +// 1: WDT interrupt is a non-maskable interrupt. +// ENUMs: +// NONMASKABLE Non-maskable interrupt +// MASKABLE Maskable interrupt +#define WDT_CTL_INTTYPE 0x00000004 +#define WDT_CTL_INTTYPE_BITN 2 +#define WDT_CTL_INTTYPE_M 0x00000004 +#define WDT_CTL_INTTYPE_S 2 +#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 +#define WDT_CTL_INTTYPE_MASKABLE 0x00000000 + +// Field: [1] RESEN +// +// WDT Reset Enable. Defines the function of the WDT reset source (see +// PRCM:WARMRESET.WDT_STAT if enabled) +// +// 0: Disabled. +// 1: Enable the Watchdog reset output. +// ENUMs: +// EN Reset output Enabled +// DIS Reset output Disabled +#define WDT_CTL_RESEN 0x00000002 +#define WDT_CTL_RESEN_BITN 1 +#define WDT_CTL_RESEN_M 0x00000002 +#define WDT_CTL_RESEN_S 1 +#define WDT_CTL_RESEN_EN 0x00000002 +#define WDT_CTL_RESEN_DIS 0x00000000 + +// Field: [0] INTEN +// +// WDT Interrupt Enable +// +// 0: Interrupt event disabled. +// 1: Interrupt event enabled. Once set, this bit can only be cleared by a +// hardware reset. +// ENUMs: +// EN Interrupt Enabled +// DIS Interrupt Disabled +#define WDT_CTL_INTEN 0x00000001 +#define WDT_CTL_INTEN_BITN 0 +#define WDT_CTL_INTEN_M 0x00000001 +#define WDT_CTL_INTEN_S 0 +#define WDT_CTL_INTEN_EN 0x00000001 +#define WDT_CTL_INTEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: WDT_O_ICR +// +//***************************************************************************** +// Field: [31:0] WDTICR +// +// This register is the interrupt clear register. A write of any value to this +// register clears the WDT interrupt and reloads the 32-bit counter from the +// LOAD register. +#define WDT_ICR_WDTICR_W 32 +#define WDT_ICR_WDTICR_M 0xFFFFFFFF +#define WDT_ICR_WDTICR_S 0 + +//***************************************************************************** +// +// Register: WDT_O_RIS +// +//***************************************************************************** +// Field: [0] WDTRIS +// +// This register is the raw interrupt status register. WDT interrupt events can +// be monitored via this register if the controller interrupt is masked. +// +// Value Description +// +// 0: The WDT has not timed out +// 1: A WDT time-out event has occurred +// +#define WDT_RIS_WDTRIS 0x00000001 +#define WDT_RIS_WDTRIS_BITN 0 +#define WDT_RIS_WDTRIS_M 0x00000001 +#define WDT_RIS_WDTRIS_S 0 + +//***************************************************************************** +// +// Register: WDT_O_MIS +// +//***************************************************************************** +// Field: [0] WDTMIS +// +// This register is the masked interrupt status register. The value of this +// register is the logical AND of the raw interrupt bit and the WDT interrupt +// enable bit CTL.INTEN. +// +// Value Description +// +// 0: The WDT has not timed out or is masked. +// 1: An unmasked WDT time-out event has occurred. +#define WDT_MIS_WDTMIS 0x00000001 +#define WDT_MIS_WDTMIS_BITN 0 +#define WDT_MIS_WDTMIS_M 0x00000001 +#define WDT_MIS_WDTMIS_S 0 + +//***************************************************************************** +// +// Register: WDT_O_TEST +// +//***************************************************************************** +// Field: [8] STALL +// +// WDT Stall Enable +// +// 0: The WDT timer continues counting if the CPU is stopped with a debugger. +// 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the +// CPU is restarted, the WDT resumes counting. +// ENUMs: +// EN Enable STALL +// DIS Disable STALL +#define WDT_TEST_STALL 0x00000100 +#define WDT_TEST_STALL_BITN 8 +#define WDT_TEST_STALL_M 0x00000100 +#define WDT_TEST_STALL_S 8 +#define WDT_TEST_STALL_EN 0x00000100 +#define WDT_TEST_STALL_DIS 0x00000000 + +// Field: [0] TEST_EN +// +// The test enable bit +// +// 0: Enable external reset +// 1: Disables the generation of an external reset. Instead bit 1 of the +// INT_CAUS register is set and an interrupt is generated +// ENUMs: +// EN Test mode Enabled +// DIS Test mode Disabled +#define WDT_TEST_TEST_EN 0x00000001 +#define WDT_TEST_TEST_EN_BITN 0 +#define WDT_TEST_TEST_EN_M 0x00000001 +#define WDT_TEST_TEST_EN_S 0 +#define WDT_TEST_TEST_EN_EN 0x00000001 +#define WDT_TEST_TEST_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: WDT_O_INT_CAUS +// +//***************************************************************************** +// Field: [1] CAUSE_RESET +// +// Indicates that the cause of an interrupt was a reset generated but blocked +// due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). +#define WDT_INT_CAUS_CAUSE_RESET 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_BITN 1 +#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_S 1 + +// Field: [0] CAUSE_INTR +// +// Replica of RIS.WDTRIS +#define WDT_INT_CAUS_CAUSE_INTR 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_BITN 0 +#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_S 0 + +//***************************************************************************** +// +// Register: WDT_O_LOCK +// +//***************************************************************************** +// Field: [31:0] WDTLOCK +// +// WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers +// for write access. A write of any other value reapplies the lock, preventing +// any register updates (NOTE: TEST.TEST_EN bit is not lockable). +// +// A read of this register returns the following values: +// +// 0x0000.0000: Unlocked +// 0x0000.0001: Locked +#define WDT_LOCK_WDTLOCK_W 32 +#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF +#define WDT_LOCK_WDTLOCK_S 0 + + +#endif // __WDT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble.h new file mode 100644 index 0000000..393d9cb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble.h @@ -0,0 +1,264 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_ble.h +* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ +* Revision: $Revision: 18438 $ +* +* Description: RF Core patch file for CC26x0 +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_BLE_H +#define _RF_PATCH_CPE_BLE_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageBle[] = { + 0x210004b9, + 0x21000539, + 0x2100047d, + 0x2100058f, + 0x4c17b5f0, + 0x18612140, + 0x280278c8, + 0x4809d005, + 0x60012100, + 0x47884908, + 0x6e25bdf0, + 0x60354e07, + 0x43280760, + 0x68276620, + 0x480e6024, + 0x60274780, + 0xbdf06035, + 0x4004112c, + 0x000065a5, + 0x40044028, + 0x4c07b510, + 0x29007da1, + 0x2101d105, + 0x024875a1, + 0x393e4904, + 0x68204788, + 0xd0002800, + 0xbd104780, + 0x21000254, + 0x0000398b, + 0x4905b510, + 0xb6724a05, + 0x280178c8, + 0x2001dc02, + 0x1d127048, + 0x4710b662, + 0x21000294, + 0x0000476d, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01dfb085, + 0x47204c01, + 0x00003d5b, + 0x00003f23, + 0x4e1ab5f8, + 0x6b314605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6334, + 0x07c00a40, + 0x2001d00c, + 0x6af10380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x490762f1, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x21000296, + 0x00003cdf, + 0x40044040, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597c49, + 0x689b4b09, + 0xff8df7ff, + 0xb510bd10, + 0xff84f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003a39, + 0x40045080, + 0x21000280, + 0x40044000, +}; +#define _NWORD_PATCHIMAGE_BLE 107 + +#define _NWORD_PATCHSYS_BLE 0 + +#define _IRQ_PATCH_0 0x21000415 +#define _IRQ_PATCH_1 0x21000455 + + +#ifndef _BLE_SYSRAM_START +#define _BLE_SYSRAM_START 0x20000000 +#endif + +#ifndef _BLE_CPERAM_START +#define _BLE_CPERAM_START 0x21000000 +#endif + +#define _BLE_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _BLE_PARSER_PATCH_TAB_OFFSET 0x0334 +#define _BLE_PATCH_TAB_OFFSET 0x033C +#define _BLE_IRQPATCH_OFFSET 0x03AC +#define _BLE_PATCH_VEC_OFFSET 0x0404 + +PATCH_FUN_SPEC void enterBleCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_BLE > 0) + uint32_t *pPatchVec = (uint32_t *) (_BLE_CPERAM_START + _BLE_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageBle, sizeof(patchImageBle)); +#endif +} + +PATCH_FUN_SPEC void enterBleSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureBlePatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_BLE_CPERAM_START + _BLE_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_BLE_CPERAM_START + _BLE_IRQPATCH_OFFSET); + + + pPatchTab[103] = 0; + pPatchTab[60] = 1; + pPatchTab[48] = 2; + pPatchTab[43] = 3; + + pIrqPatch[1] = _IRQ_PATCH_0; + pIrqPatch[9] = _IRQ_PATCH_1; +} + +PATCH_FUN_SPEC void applyBlePatch(void) +{ + enterBleSysPatch(); + enterBleCpePatch(); + configureBlePatch(); +} + +PATCH_FUN_SPEC void refreshBlePatch(void) +{ + enterBleCpePatch(); + configureBlePatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_ble(void) +{ + applyBlePatch(); +} + +#undef _IRQ_PATCH_0 +#undef _IRQ_PATCH_1 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_BLE_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h new file mode 100644 index 0000000..a4a36cf --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h @@ -0,0 +1,359 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_ble_priv_1_2.h +* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ +* Revision: $Revision: 18438 $ +* +* Description: RF Core patch file for CC26x0 Bluetooth Low Energy with privacy 1.2 support +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_BLE_PRIV_1_2_H +#define _RF_PATCH_CPE_BLE_PRIV_1_2_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageBlePriv12[] = { + 0x210005e5, + 0x21000631, + 0x210006b1, + 0x21000481, + 0x21000707, + 0x4c17b5f0, + 0x18612140, + 0x280278c8, + 0x4809d005, + 0x60012100, + 0x47884908, + 0x6e25bdf0, + 0x60354e07, + 0x43280760, + 0x68276620, + 0x480e6024, + 0x60274780, + 0xbdf06035, + 0x4004112c, + 0x000065a5, + 0x40044028, + 0x4c07b510, + 0x29007da1, + 0x2101d105, + 0x024875a1, + 0x393e4904, + 0x68204788, + 0xd0002800, + 0xbd104780, + 0x21000254, + 0x0000398b, + 0x4905b510, + 0xb6724a05, + 0x280178c8, + 0x2001dc02, + 0x1d127048, + 0x4710b662, + 0x21000294, + 0x0000476d, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01dfb085, + 0x47204c01, + 0x00003d5b, + 0x00003f23, + 0x4d53b5fe, + 0x462c4628, + 0x90003040, + 0x7e014627, + 0x78383760, + 0xd0022900, + 0xd10707c0, + 0x09c1e050, + 0x07c0d04e, + 0x7d20d14c, + 0xd5490640, + 0x31724629, + 0x20064a48, + 0x98004790, + 0x28007e00, + 0x7d20d007, + 0xd5010640, + 0xe0002003, + 0x26132001, + 0x6f68e008, + 0x28010f80, + 0x2006d002, + 0xe0014606, + 0x26072003, + 0x02312201, + 0x1a890412, + 0x02008a7a, + 0x43020412, + 0x35806f6b, + 0x68a89501, + 0x47a84d37, + 0x2e062201, + 0x2e07d002, + 0xe007d002, + 0xe00543c0, + 0x70797839, + 0x70394311, + 0x61089901, + 0xda012800, + 0x55022039, + 0x7e809800, + 0xd0022800, + 0x201e2106, + 0x6a61e002, + 0x201f1f89, + 0x6ca162a1, + 0x64e04788, + 0xbdfe2000, + 0x47804826, + 0x4822bdfe, + 0x78413060, + 0xd0022900, + 0x21007001, + 0x48217041, + 0x470038b0, + 0x4e1cb5f8, + 0x4635481f, + 0x7fec3540, + 0x09e14637, + 0x6db1d01a, + 0xd0172901, + 0x29007f69, + 0x07a1d002, + 0xe011d502, + 0xd10f07e1, + 0x06497d39, + 0x2103d50c, + 0x77e94321, + 0x6f314780, + 0x29010f89, + 0x2100d002, + 0x76793720, + 0xbdf877ec, + 0xbdf84780, + 0x31404909, + 0x28157508, + 0x281bd008, + 0x281dd008, + 0x490ad008, + 0x18400080, + 0x47706980, + 0x47704808, + 0x47704808, + 0x47704808, + 0x21000144, + 0x0000b8af, + 0x0000a001, + 0x0000be03, + 0x0000b98d, + 0x0000ccc0, + 0x21000599, + 0x21000583, + 0x210004bd, + 0x4e1ab5f8, + 0x6b314605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6334, + 0x07c00a40, + 0x2001d00c, + 0x6af10380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x490762f1, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x21000296, + 0x00003cdf, + 0x40044040, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597c49, + 0x689b4b09, + 0xfed3f7ff, + 0xb510bd10, + 0xfecaf7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003a39, + 0x40045080, + 0x21000280, + 0x40044000, +}; +#define _NWORD_PATCHIMAGE_BLE_PRIV_1_2 201 + +#define _NWORD_PATCHSYS_BLE_PRIV_1_2 0 + +#define _IRQ_PATCH_0 0x21000419 +#define _IRQ_PATCH_1 0x21000459 + + +#ifndef _BLE_PRIV_1_2_SYSRAM_START +#define _BLE_PRIV_1_2_SYSRAM_START 0x20000000 +#endif + +#ifndef _BLE_PRIV_1_2_CPERAM_START +#define _BLE_PRIV_1_2_CPERAM_START 0x21000000 +#endif + +#define _BLE_PRIV_1_2_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _BLE_PRIV_1_2_PARSER_PATCH_TAB_OFFSET 0x0334 +#define _BLE_PRIV_1_2_PATCH_TAB_OFFSET 0x033C +#define _BLE_PRIV_1_2_IRQPATCH_OFFSET 0x03AC +#define _BLE_PRIV_1_2_PATCH_VEC_OFFSET 0x0404 + +PATCH_FUN_SPEC void enterBlePriv12CpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_BLE_PRIV_1_2 > 0) + uint32_t *pPatchVec = (uint32_t *) (_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageBlePriv12, sizeof(patchImageBlePriv12)); +#endif +} + +PATCH_FUN_SPEC void enterBlePriv12SysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureBlePriv12Patch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_IRQPATCH_OFFSET); + + + pPatchTab[1] = 0; + pPatchTab[103] = 1; + pPatchTab[60] = 2; + pPatchTab[48] = 3; + pPatchTab[43] = 4; + + pIrqPatch[1] = _IRQ_PATCH_0; + pIrqPatch[9] = _IRQ_PATCH_1; +} + +PATCH_FUN_SPEC void applyBlePriv12Patch(void) +{ + enterBlePriv12SysPatch(); + enterBlePriv12CpePatch(); + configureBlePriv12Patch(); +} + +PATCH_FUN_SPEC void refreshBlePriv12Patch(void) +{ + enterBlePriv12CpePatch(); + configureBlePriv12Patch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_ble_priv_1_2(void) +{ + applyBlePriv12Patch(); +} + +#undef _IRQ_PATCH_0 +#undef _IRQ_PATCH_1 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_BLE_PRIV_1_2_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_genfsk.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_genfsk.h new file mode 100644 index 0000000..f92413f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_genfsk.h @@ -0,0 +1,254 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_genfsk.h +* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ +* Revision: $Revision: 18438 $ +* +* Description: RF core patch for CC26x0 Generic FSK +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_GENFSK_H +#define _RF_PATCH_CPE_GENFSK_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageGenfsk[] = { + 0x21000495, + 0x21000515, + 0x2100056b, + 0x4c17b5f0, + 0x18612140, + 0x280278c8, + 0x4809d005, + 0x60012100, + 0x47884908, + 0x6e25bdf0, + 0x60354e07, + 0x43280760, + 0x68276620, + 0x480e6024, + 0x60274780, + 0xbdf06035, + 0x4004112c, + 0x000065a5, + 0x40044028, + 0x4c07b510, + 0x29007da1, + 0x2101d105, + 0x024875a1, + 0x393e4904, + 0x68204788, + 0xd0002800, + 0xbd104780, + 0x21000254, + 0x0000398b, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01dfb085, + 0x47204c01, + 0x00003d5b, + 0x00003f23, + 0x4e1ab5f8, + 0x6b314605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6334, + 0x07c00a40, + 0x2001d00c, + 0x6af10380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x490762f1, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x21000296, + 0x00003cdf, + 0x40044040, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597c49, + 0x689b4b09, + 0xff8df7ff, + 0xb510bd10, + 0xff84f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003a39, + 0x40045080, + 0x21000280, + 0x40044000, +}; +#define _NWORD_PATCHIMAGE_GENFSK 98 + +#define _NWORD_PATCHSYS_GENFSK 0 + +#define _IRQ_PATCH_0 0x21000411 +#define _IRQ_PATCH_1 0x21000451 + + +#ifndef _GENFSK_SYSRAM_START +#define _GENFSK_SYSRAM_START 0x20000000 +#endif + +#ifndef _GENFSK_CPERAM_START +#define _GENFSK_CPERAM_START 0x21000000 +#endif + +#define _GENFSK_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _GENFSK_PARSER_PATCH_TAB_OFFSET 0x0334 +#define _GENFSK_PATCH_TAB_OFFSET 0x033C +#define _GENFSK_IRQPATCH_OFFSET 0x03AC +#define _GENFSK_PATCH_VEC_OFFSET 0x0404 + +PATCH_FUN_SPEC void enterGenfskCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_GENFSK > 0) + uint32_t *pPatchVec = (uint32_t *) (_GENFSK_CPERAM_START + _GENFSK_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageGenfsk, sizeof(patchImageGenfsk)); +#endif +} + +PATCH_FUN_SPEC void enterGenfskSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureGenfskPatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_GENFSK_CPERAM_START + _GENFSK_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_GENFSK_CPERAM_START + _GENFSK_IRQPATCH_OFFSET); + + + pPatchTab[103] = 0; + pPatchTab[60] = 1; + pPatchTab[43] = 2; + + pIrqPatch[1] = _IRQ_PATCH_0; + pIrqPatch[9] = _IRQ_PATCH_1; +} + +PATCH_FUN_SPEC void applyGenfskPatch(void) +{ + enterGenfskSysPatch(); + enterGenfskCpePatch(); + configureGenfskPatch(); +} + +PATCH_FUN_SPEC void refreshGenfskPatch(void) +{ + enterGenfskCpePatch(); + configureGenfskPatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_genfsk(void) +{ + applyGenfskPatch(); +} + +#undef _IRQ_PATCH_0 +#undef _IRQ_PATCH_1 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_GENFSK_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ieee.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ieee.h new file mode 100644 index 0000000..f134e29 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ieee.h @@ -0,0 +1,298 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_ieee.h +* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ +* Revision: $Revision: 18438 $ +* +* Description: RF Core patch file for CC26x0 IEEE 802.15.4 PHY +* +* Copyright (c) 2015, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_CPE_IEEE_H +#define _RF_PATCH_CPE_IEEE_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageIeee[] = { + 0x2100050f, + 0x2100041d, + 0x21000539, + 0x210005b9, + 0x210004b5, + 0x2100060f, + 0x22024823, + 0x421a7dc3, + 0xd0034472, + 0x1dc04678, + 0xb5f84686, + 0x4c1f4710, + 0x200834ae, + 0x490347a0, + 0x60082008, + 0x3cec6008, + 0xbdf847a0, + 0x40045004, + 0x4c17b5f0, + 0x18612140, + 0x280278c8, + 0x4809d005, + 0x60012100, + 0x47884908, + 0x6e25bdf0, + 0x60354e07, + 0x43280760, + 0x68276620, + 0x480e6024, + 0x60274780, + 0xbdf06035, + 0x4004112c, + 0x000065a5, + 0x40044028, + 0x4c07b510, + 0x29007da1, + 0x2101d105, + 0x024875a1, + 0x393e4904, + 0x68204788, + 0xd0002800, + 0xbd104780, + 0x21000254, + 0x0000398b, + 0x6a034807, + 0x46784907, + 0x46861dc0, + 0x4788b5f8, + 0x009b089b, + 0x6a014802, + 0xd10007c9, + 0xbdf86203, + 0x40045040, + 0x0000f1ab, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01dfb085, + 0x47204c01, + 0x00003d5b, + 0x00003f23, + 0x6a00480b, + 0xd00407c0, + 0x2201480a, + 0x43117801, + 0x48097001, + 0x72c84700, + 0xd006280d, + 0x00802285, + 0x18800252, + 0x60486840, + 0x48044770, + 0x0000e7fb, + 0x40045040, + 0x21000268, + 0x0000ff39, + 0x210004f9, + 0x4e1ab5f8, + 0x6b314605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6334, + 0x07c00a40, + 0x2001d00c, + 0x6af10380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x490762f1, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x21000296, + 0x00003cdf, + 0x40044040, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597c49, + 0x689b4b09, + 0xff6df7ff, + 0xb510bd10, + 0xff64f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003a39, + 0x40045080, + 0x21000280, + 0x40044000, +}; +#define _NWORD_PATCHIMAGE_IEEE 139 + +#define _NWORD_PATCHSYS_IEEE 0 + +#define _IRQ_PATCH_0 0x2100044d +#define _IRQ_PATCH_1 0x2100048d + + +#ifndef _IEEE_SYSRAM_START +#define _IEEE_SYSRAM_START 0x20000000 +#endif + +#ifndef _IEEE_CPERAM_START +#define _IEEE_CPERAM_START 0x21000000 +#endif + +#define _IEEE_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _IEEE_PARSER_PATCH_TAB_OFFSET 0x0334 +#define _IEEE_PATCH_TAB_OFFSET 0x033C +#define _IEEE_IRQPATCH_OFFSET 0x03AC +#define _IEEE_PATCH_VEC_OFFSET 0x0404 + +PATCH_FUN_SPEC void enterIeeeCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_IEEE > 0) + uint32_t *pPatchVec = (uint32_t *) (_IEEE_CPERAM_START + _IEEE_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageIeee, sizeof(patchImageIeee)); +#endif +} + +PATCH_FUN_SPEC void enterIeeeSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureIeeePatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_IEEE_CPERAM_START + _IEEE_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_IEEE_CPERAM_START + _IEEE_IRQPATCH_OFFSET); + + + pPatchTab[5] = 0; + pPatchTab[52] = 1; + pPatchTab[103] = 2; + pPatchTab[60] = 3; + pPatchTab[38] = 4; + pPatchTab[43] = 5; + + pIrqPatch[1] = _IRQ_PATCH_0; + pIrqPatch[9] = _IRQ_PATCH_1; +} + +PATCH_FUN_SPEC void applyIeeePatch(void) +{ + enterIeeeSysPatch(); + enterIeeeCpePatch(); + configureIeeePatch(); +} + +PATCH_FUN_SPEC void refreshIeeePatch(void) +{ + enterIeeeCpePatch(); + configureIeeePatch(); +} + +PATCH_FUN_SPEC void rf_patch_cpe_ieee(void) +{ + applyIeeePatch(); +} + +#undef _IRQ_PATCH_0 +#undef _IRQ_PATCH_1 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_IEEE_H + diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_genfsk.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_genfsk.h new file mode 100644 index 0000000..e9fe2ae --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_genfsk.h @@ -0,0 +1,567 @@ +/****************************************************************************** +* Filename: rf_patch_mce_genfsk.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC26x0 Generic FSK +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_GENFSK_H +#define _RF_PATCH_MCE_GENFSK_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchGenfskMce[460] = { + 0x2fcf603c, + 0x030c3f9d, + 0x070c680a, + 0x003f0387, + 0x00fffff0, + 0x0000ff00, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00070003, + 0x00003d1f, + 0x04000000, + 0x0000000f, + 0x000b0387, + 0x004340f4, + 0x80828000, + 0x00000670, + 0x0510091e, + 0x00050054, + 0x3e100200, + 0x00000061, + 0x3030002f, + 0x0000027f, + 0x00000000, + 0x0000aa00, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72487220, + 0x7303a32d, + 0x72037305, + 0x73067304, + 0x73767204, + 0xc7c07276, + 0x00018001, + 0x90109001, + 0x90010801, + 0x720d720c, + 0xb0c0720e, + 0xb0f07100, + 0x7218a0c0, + 0x10208132, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60796c01, + 0x60ec607b, + 0x60796352, + 0x60796079, + 0x6079607a, + 0x60ec607b, + 0x60796352, + 0x60796079, + 0x1210607a, + 0x730f7220, + 0x73117310, + 0x00108181, + 0xb0709180, + 0x606f6051, + 0xc030606f, + 0xc1416791, + 0xc470c282, + 0x6f131820, + 0x16116e23, + 0x68811612, + 0x9ab07830, + 0x9ac07840, + 0x9ad07850, + 0x9ae07860, + 0xc5a0c482, + 0x40961820, + 0x6e231203, + 0x68931612, + 0x8160606f, + 0x81409490, + 0x2a703980, + 0x16111001, + 0x84448432, + 0xc0f5c0f3, + 0x1c01c200, + 0xc10040bb, + 0x40b11c10, + 0x10134cb3, + 0x18301803, + 0x1a101a13, + 0x68ae3912, + 0x13f360bb, + 0x13f360bb, + 0xc1001015, + 0x1a151850, + 0x39141a10, + 0xb0d868b9, + 0xb1087100, + 0xb200a0d8, + 0xb003b480, + 0xb002b013, + 0x7229b012, + 0x7100b0d0, + 0x8140b100, + 0x71009290, + 0x8140b100, + 0x44cb22f0, + 0x1c0313f0, + 0x929340d7, + 0x71009492, + 0x9295b100, + 0x71009494, + 0xb0d0b100, + 0x7000a480, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0x7000a002, + 0x7310730f, + 0x6791c040, + 0x91c0c100, + 0xb4836497, + 0xb0c3b0f3, + 0xa0c37100, + 0x606f64de, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x78728400, + 0x81430420, + 0x2a733983, + 0xc1f29473, + 0x31621832, + 0x31511021, + 0x00200012, + 0x10309400, + 0x10011610, + 0x39303121, + 0x41172210, + 0x31501220, + 0x31801003, + 0x16300010, + 0x12029350, + 0x22731204, + 0x8430412a, + 0x87d297c0, + 0x84501a82, + 0x87d497c0, + 0x612c1a84, + 0x41372263, + 0x97c08440, + 0x1a8087d0, + 0x84601402, + 0x87d097c0, + 0x14041a80, + 0x84406143, + 0x041078a1, + 0x87d297c0, + 0x84601a42, + 0x041078a1, + 0x87d497c0, + 0x31521a44, + 0x39633154, + 0x16130633, + 0x38343832, + 0x39823182, + 0x00423184, + 0x78109572, + 0x90509030, + 0x90407820, + 0xb2059060, + 0x83038ae2, + 0xc00c9302, + 0x8140c00b, + 0x39803180, + 0x81413940, + 0x0431c0f3, + 0x1441c014, + 0x1412c002, + 0x31226965, + 0xc010847d, + 0x312d140d, + 0x8ace142d, + 0x311e318e, + 0x8ac9397e, + 0x39793149, + 0x31293949, + 0xb072109a, + 0xb06ea04e, + 0xb06cb011, + 0x7276978a, + 0xa764b764, + 0x9762c662, + 0x66d3c04f, + 0x22f18ab1, + 0x8ad1458b, + 0x458b22f1, + 0x71006231, + 0xb760b073, + 0x220780b7, + 0xa76045c2, + 0x22f18ab1, + 0x2237419c, + 0xb113419c, + 0x223080b0, + 0x61aa4597, + 0x41af22e1, + 0x22508090, + 0xb0f541af, + 0x22208210, + 0x9789418b, + 0xa764b764, + 0x618bb0f6, + 0xb764978d, + 0xb0f6a764, + 0x8ad0618b, + 0x41bb22f0, + 0x41bb2237, + 0xb113b075, + 0x223080b0, + 0xb08745b5, + 0x22d1618b, + 0x80904316, + 0x43162220, + 0x618b6699, + 0xc7f3978f, + 0x31808410, + 0x31833980, + 0x94100030, + 0xa0e3b087, + 0xa0c2b0f2, + 0xa0c5b0f5, + 0xb0c1b0f1, + 0xb110a0c6, + 0x80b0b113, + 0x45d32200, + 0x45d32230, + 0x12607100, + 0xb0f19780, + 0x8961b88f, + 0x18018570, + 0x8a609551, + 0xa4888a71, + 0xc022a487, + 0x1c211801, + 0x14124df3, + 0x61f449f1, + 0x41f41c01, + 0xb4874df3, + 0xb48861f4, + 0xb061b041, + 0x22e08ad0, + 0x821041fc, + 0x45772220, + 0xb04e7100, + 0x80b1b06e, + 0x468b2201, + 0x468b2231, + 0xb0f67276, + 0x31218471, + 0x1410c260, + 0xc7e09780, + 0xc6f09760, + 0xb0f69760, + 0xa0c1b0c6, + 0x8a63b7b0, + 0x8a838a74, + 0x71008a94, + 0x220180b1, + 0x2231468b, + 0x8ab0468b, + 0x462322c0, + 0x22018991, + 0x81c14177, + 0x91c0c000, + 0x81a28470, + 0x91c16a27, + 0x9070c300, + 0xa0e0b201, + 0xa044a0e3, + 0x71007000, + 0xb760b073, + 0x220780b7, + 0x22374650, + 0xa760466e, + 0x22e18ab1, + 0x80904249, + 0x42492250, + 0x8210b0f5, + 0x42312220, + 0xb764978d, + 0xb0f6a764, + 0x22d16231, + 0x80904316, + 0x43162220, + 0x62316699, + 0xb0f2978f, + 0xb0f5a0c2, + 0xb0f1a0c5, + 0xa0c6b0c1, + 0xb113b110, + 0x220080b0, + 0x22304658, + 0x71004658, + 0x97801260, + 0xb88fb0f1, + 0x85708961, + 0x3d803180, + 0x95511801, + 0x8a718a60, + 0x61e5a182, + 0xb0f2978f, + 0xb0f5a0c2, + 0xb0f1a0c5, + 0xa0c6b0c1, + 0xb113b110, + 0x220080b0, + 0x22304676, + 0x71004676, + 0x97801260, + 0xb88fb0f1, + 0x85708961, + 0x18013d80, + 0x8a809551, + 0xb1828a91, + 0xb07361e5, + 0xb760a760, + 0xb072a7b0, + 0xb06ea04e, + 0x8ab0b011, + 0x45c222f0, + 0x46502201, + 0x8ab0626e, + 0x469f22b0, + 0x46d11e3b, + 0x1e7b62a1, + 0xc00b46d1, + 0x8940b889, + 0x3d803180, + 0x3d301610, + 0x80b0140c, + 0x42ad2200, + 0x8ab37000, + 0x06f33983, + 0xcff08ab1, + 0x30310401, + 0x4ec91c1c, + 0x18101200, + 0x4acb1c0c, + 0x220080b0, + 0x700042be, + 0x161210c2, + 0x8ae13c32, + 0x22108320, + 0x62cf42cd, + 0xb0f29301, + 0x101c7000, + 0x100c62ba, + 0x182162ba, + 0x142162c6, + 0x161b62c6, + 0xb0f662c7, + 0xb110b0f1, + 0xb0f5b113, + 0x720cb0f2, + 0x720e720d, + 0xb0e3b0e0, + 0x22f28ab2, + 0xb0c642e4, + 0x62e7b763, + 0x22f08ad0, + 0xb4054307, + 0xb428a404, + 0xcaa0a429, + 0xcaa13180, + 0x94510001, + 0x8ad39461, + 0x39833183, + 0x31808410, + 0x31833980, + 0x94100030, + 0x31508400, + 0x8ad33950, + 0x06f33983, + 0x1834c1f4, + 0x31343184, + 0x94000040, + 0x22e2b089, + 0x8aca4311, + 0x398a394a, + 0x978a312a, + 0xb0c6b0c5, + 0x8ab2b763, + 0x431522d2, + 0x7000b0c2, + 0xa0e0b20f, + 0x978ea0e3, + 0xa764b764, + 0xb110b0f6, + 0x8210b113, + 0x431f22f0, + 0x8002b0f5, + 0xa006a004, + 0x7203a001, + 0xc0507204, + 0x71006791, + 0xb0f6b764, + 0xa20fb0c5, + 0xb0f57100, + 0x7810a0c5, + 0x90029030, + 0x90407820, + 0xb0729060, + 0x66d3a20f, + 0xa764978a, + 0x6184b0f6, + 0x8180b88c, + 0x392489a4, + 0x00043184, + 0xc0609184, + 0x73766791, + 0x72487276, + 0x72027206, + 0x73057204, + 0x606f7306, + 0x91b01300, + 0xc070b32d, + 0xb0f86791, + 0x120064fa, + 0x97801a10, + 0x9760c380, + 0x9760c280, + 0xb0c6a0c1, + 0x22008090, + 0x81544451, + 0x43621e04, + 0xb0f69784, + 0xd0808552, + 0x67919862, + 0x22118991, + 0x8a824378, + 0xe0908a93, + 0x98739862, + 0x637e6791, + 0x8a738a62, + 0x9862e0a0, + 0x67919873, + 0x87818790, + 0x4b8e1c01, + 0x1ef11801, + 0x87814b8c, + 0x97811af1, + 0xb0f67100, + 0x978116f1, + 0x7100a205, + 0xa0c6b0f6, + 0x98506340, + 0x22008840, + 0xb8304792, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_mce_genfsk(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 460; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchGenfskMce[i]; + } +#else + const uint32_t *pS = patchGenfskMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 57; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_ieee_s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_ieee_s.h new file mode 100644 index 0000000..cfce70c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_ieee_s.h @@ -0,0 +1,354 @@ +/****************************************************************************** +* Filename: rf_patch_mce_ieee_s.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC26x0 IEEE 802.15.4 Single Ended Output +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_IEEE_S_H +#define _RF_PATCH_MCE_IEEE_S_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchZigbeeXsIsMce[256] = { + 0xf703605f, + 0x70399b3a, + 0x039bb3af, + 0x39b33af7, + 0x9b3aaf70, + 0xb3aff703, + 0x3af77039, + 0xaf70039b, + 0x08fcb9b3, + 0x8fc664c5, + 0xfc644c50, + 0xc64cc508, + 0x64c5508f, + 0x4c5008fc, + 0xc5088fc6, + 0x508ffc64, + 0x0fcfc64c, + 0x7f7f079c, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000003, + 0x0000001f, + 0x80000000, + 0x0004000c, + 0x000114c4, + 0x00000009, + 0x00008000, + 0x002b0670, + 0x0a11121d, + 0x0b600000, + 0x40100000, + 0x00000040, + 0x1e1e0006, + 0x0000001e, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72200000, + 0x720d720c, + 0x7248720e, + 0x7203a32d, + 0x73057204, + 0x73767306, + 0xc7c07276, + 0xb0c09010, + 0xa0c07100, + 0x7218b0f0, + 0x10208132, + 0x06703952, + 0x16300020, + 0x14011101, + 0x609b6c01, + 0x60c860a9, + 0x6147612c, + 0x609b609b, + 0x609b609c, + 0x609b609b, + 0x609b609b, + 0x609b609b, + 0x609b609c, + 0x609b609b, + 0x609b609b, + 0x609b609b, + 0x609b609c, + 0x609b609b, + 0x609b609b, + 0x609b609b, + 0x60a0609c, + 0x60a0664e, + 0x60a11220, + 0x730f1210, + 0x73117310, + 0x00108181, + 0xb0709180, + 0xc301606d, + 0xc420c282, + 0x6f131820, + 0x16116e23, + 0x68ad1612, + 0xc810c482, + 0x40ba1820, + 0x6e231203, + 0x68b71612, + 0x60a072ab, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc1307276, + 0xb0f391c0, + 0xb0d8b108, + 0xb1087100, + 0xb200a0d8, + 0x1e008ab0, + 0xb76040da, + 0xb0f19780, + 0x7100b0c1, + 0xb013b483, + 0xb012b003, + 0xb0f1b002, + 0x7276a0c1, + 0x7100b0c3, + 0xa0c3b0f3, + 0xc0301000, + 0xc0209760, + 0xb0c19780, + 0xb0f17100, + 0x7276a0c1, + 0xa0037248, + 0x7248a002, + 0x73067305, + 0x72767376, + 0x9010c7c0, + 0x000060a0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0307276, + 0xb00291b0, + 0xb006b004, + 0x90507a10, + 0x7a209030, + 0x90409060, + 0x94507810, + 0x94607820, + 0xc0f18160, + 0xc0120410, + 0x14023110, + 0x94306f20, + 0x6f201612, + 0x84209440, + 0x84213180, + 0x39813181, + 0x94100010, + 0xb2051200, + 0x31858165, + 0x39853145, + 0x120e3945, + 0x12061217, + 0x940012f0, + 0x9400c190, + 0xb119b011, + 0xa0ecb0e9, + 0x7100b089, + 0xa0e9b119, + 0xb0ecb11c, + 0x7100a404, + 0x659bb11c, + 0x417e1e76, + 0x45471eaf, + 0x1c90c140, + 0x12054d47, + 0x12761202, + 0x9070c300, + 0xc070b200, + 0xc0c065fa, + 0x7a309400, + 0x61859410, + 0x919f1647, + 0x1e008150, + 0x1c704185, + 0x7100498a, + 0x22008090, + 0x61684470, + 0x7276a205, + 0x72047203, + 0x73067305, + 0xa004a002, + 0x7248a006, + 0x73067305, + 0x72767376, + 0x9010c7c0, + 0x120960a0, + 0xc0cc120a, + 0xb88e120d, + 0x1c898928, + 0x1c8a49a6, + 0x61b34dac, + 0x12001089, + 0x100a1880, + 0x61b310db, + 0x1200108a, + 0x10091880, + 0x168b10db, + 0x161d61b3, + 0x41b81e8d, + 0x619f908c, + 0x1e8210bf, + 0x149541c3, + 0x1e821612, + 0x312545c3, + 0x00058180, + 0x1e8b9185, + 0x1a8b49c6, + 0x18b0c070, + 0x11011630, + 0x6c011401, + 0x908c908c, + 0x908c908c, + 0x908c908c, + 0x908c908c, + 0x1000b082, + 0x8923b88e, + 0xb083b083, + 0xb88e1000, + 0x1e8f8924, + 0x1ca349e4, + 0x1ca449e9, + 0x700049eb, + 0x4de91c93, + 0x4deb1c94, + 0x1a1e7000, + 0x161e61ed, + 0xc04061ed, + 0x49f41ce0, + 0x164010e0, + 0x700049f7, + 0xb085c00e, + 0xc00e7000, + 0x7000b084, + 0x88409850, + 0x45fb2200, + 0x7000b830 +}; + +PATCH_FUN_SPEC void rf_patch_mce_ieee_s(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 256; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchZigbeeXsIsMce[i]; + } +#else + const uint32_t *pS = patchZigbeeXsIsMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 32; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ble.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ble.h new file mode 100644 index 0000000..969f21f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ble.h @@ -0,0 +1,421 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_ble.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC26x0 BLE +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_BLE_H +#define _RF_PATCH_RFE_BLE_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchBleRfe[315] = { + 0x00006154, + 0x0002147f, + 0x00050006, + 0x0008000f, + 0x00520048, + 0x003fff80, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x00000000, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x00000000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0x00000007, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x40632241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x686f1614, + 0x10257000, + 0x9100c050, + 0xc140c3f4, + 0x6f031420, + 0x04411031, + 0x22f08250, + 0x26514084, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x64537000, + 0x1031c052, + 0x31610631, + 0x645602c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006456, + 0x9101c051, + 0xc0e2cc01, + 0x64536456, + 0xc0c2c111, + 0xb0546456, + 0xa0547100, + 0x80f0b064, + 0x40b52200, + 0x90b01240, + 0xc2f0b032, + 0xc11168c0, + 0x6456c122, + 0x68c5c0b0, + 0x9101c051, + 0x3182c0e2, + 0x00028260, + 0xb1109132, + 0x39538253, + 0x649d3953, + 0x68d3c050, + 0x12800000, + 0xb03290b0, + 0x64537000, + 0xc122c101, + 0xc1016456, + 0x6456c0c2, + 0x649d8253, + 0x90b012c0, + 0x7000b032, + 0xc2726453, + 0x6456c081, + 0xc111c122, + 0xc0026456, + 0x6456c111, + 0xc331c062, + 0xc3626456, + 0x6456c111, + 0xc111c302, + 0x82536456, + 0x649d3953, + 0x645bc3e2, + 0x40fc2211, + 0xc881c242, + 0xc2526456, + 0x6456c111, + 0xcee1c272, + 0xc2026456, + 0x6456c881, + 0xc801c202, + 0xc0b06456, + 0x70006910, + 0xc2426453, + 0x6456c801, + 0xc011c252, + 0xc2726456, + 0x6456c0e1, + 0xc101c002, + 0xc0626456, + 0x6456c301, + 0xc101c122, + 0xc3626456, + 0x6456c101, + 0xc101c302, + 0x82536456, + 0x7000649d, + 0x3162c102, + 0x80a0c001, + 0x41361e00, + 0x61381a10, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006938, + 0x82d092e0, + 0x453f2200, + 0x7000b2c0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xb0608081, + 0x8092a050, + 0x92f1eff0, + 0x653e9302, + 0x45782241, + 0xc1f18080, + 0x16300410, + 0x14011101, + 0x618b6c01, + 0x618d618c, + 0x618f618e, + 0x61916190, + 0x61956193, + 0x61996197, + 0x62736270, + 0xc0f28091, + 0x31210421, + 0x2a428082, + 0x16321412, + 0x14211101, + 0x61a66c01, + 0x61ac61c7, + 0x61a66273, + 0x61ac61c7, + 0x619b6273, + 0x619b619b, + 0x619b619b, + 0x64ac619b, + 0x64d9619b, + 0x64e6619b, + 0x6512619b, + 0x652e619b, + 0x8082619b, + 0x92f2dfe0, + 0xb0b0653e, + 0xb0b161a2, + 0x72057306, + 0x6158b030, + 0x653ecfd0, + 0xc003c284, + 0x6468c3c0, + 0x91507890, + 0x31107860, + 0x14107861, + 0x78509200, + 0x78613140, + 0x31400010, + 0x00107871, + 0x78b09210, + 0x78819260, + 0x78309221, + 0x78413140, + 0x92300010, + 0x91f0c010, + 0xa054619b, + 0x225080f0, + 0x804045cf, + 0x46662200, + 0xc80061c7, + 0x81599160, + 0x8091b050, + 0x462e2241, + 0x653ecfc0, + 0x31828212, + 0x39423982, + 0x64771028, + 0x12f18212, + 0x102f0412, + 0x142f311f, + 0x1420c140, + 0x396d6f0d, + 0xc3f410de, + 0xc082044e, + 0x002e3182, + 0xc0a2396d, + 0x002d3182, + 0x398a821a, + 0x31808220, + 0xc00b3980, + 0x78ac180b, + 0x39408230, + 0xc0111002, + 0xc0103001, + 0x18021801, + 0x00213182, + 0x919126c1, + 0xb013b003, + 0xb053b063, + 0x14398203, + 0x22018041, + 0x81b44666, + 0x81d591c4, + 0x1cb51895, + 0x1cc54e1c, + 0x91654a54, + 0x221080f0, + 0x622c420c, + 0xb110913d, + 0xb110913e, + 0x920f9165, + 0x14f98159, + 0x10bc18ab, + 0x225080f0, + 0x221041c7, + 0x620c462c, + 0x653ecfb0, + 0x8230b063, + 0xc0f21000, + 0x10020420, + 0x3001c011, + 0x1801c010, + 0x31821802, + 0x26c10021, + 0x91919191, + 0xb003b013, + 0xb053b063, + 0xb054b064, + 0x80417100, + 0x46662201, + 0xb064b063, + 0x225080f0, + 0x81b141c7, + 0x81d191c1, + 0x91611891, + 0x6244b031, + 0x31828212, + 0x39423982, + 0x64771028, + 0x82058159, + 0x82201459, + 0x180bc00b, + 0xc08078ac, + 0xb0637100, + 0x620c6a62, + 0x81628201, + 0x3d823182, + 0x92f1efa0, + 0x653e9302, + 0x619ba003, + 0x647780a2, + 0xb050619b, + 0x619b7100 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_ble(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 315; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchBleRfe[i]; + } +#else + const uint32_t *pS = patchBleRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 39; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_genfsk.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_genfsk.h new file mode 100644 index 0000000..350b3ae --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_genfsk.h @@ -0,0 +1,545 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_genfsk.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC26x0 Generic FSK +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_GENFSK_H +#define _RF_PATCH_RFE_GENFSK_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchGenfskRfe[431] = { + 0x000061a9, + 0x1307147f, + 0x00080053, + 0x1f2e24f1, + 0x0ab03f13, + 0xff07003f, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x22f08250, + 0x26514070, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x659d658e, + 0x8220c088, + 0x39803950, + 0x40a31e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40ad1e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40b32200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6489, + 0xc122c111, + 0xc1706442, + 0xc11168c6, + 0x6442c0c2, + 0x68cbc170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276576, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26576, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f7c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x72276582, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x6582101a, + 0xb061a051, + 0xc0b07227, + 0x643f691c, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64898253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64893953, + 0x6447c3e2, + 0x41442211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006958, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006489, + 0x7100b061, + 0x1c231412, + 0x91334d7e, + 0x7000b110, + 0xb1109132, + 0x70006976, + 0x7100b061, + 0x1c321813, + 0x9132498a, + 0x7000b110, + 0xb1109133, + 0x70006982, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478b0, + 0xc0e67000, + 0x82613186, + 0x0401cc00, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c9, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61dd61dc, + 0x61df61de, + 0x61e161e0, + 0x61e461e2, + 0x61e861e6, + 0x633961ea, + 0x8091633c, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x621161f3, + 0x633c61f9, + 0x621161f3, + 0x633c61f9, + 0x61eb61eb, + 0x61eb61eb, + 0x61eb61eb, + 0x61eb6498, + 0x61eb64fd, + 0x61eb652e, + 0x61eb655a, + 0x121061eb, + 0x720e90b0, + 0x72057306, + 0x90301210, + 0xcff061ad, + 0xc1d4673f, + 0xc3c0c003, + 0x78406454, + 0x78609150, + 0x78709210, + 0x78809220, + 0x78909230, + 0x78a09240, + 0x78509260, + 0x783091f0, + 0x82109190, + 0x06f03940, + 0x31101001, + 0x92001410, + 0xa0bc61eb, + 0xa054a0e2, + 0x225080f0, + 0x8040461b, + 0x472e2200, + 0xa0406213, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673f, + 0x66cdb003, + 0xb050b053, + 0xb064b054, + 0x66abb013, + 0x22e08210, + 0x66b4463e, + 0x80417100, + 0x472e2201, + 0x221080f0, + 0x22f04651, + 0xb064471b, + 0x423e2231, + 0x66d3b063, + 0x22e08210, + 0x6676463e, + 0xb064623e, + 0x318f816f, + 0xdfd03d8f, + 0x673f92ff, + 0x80417100, + 0x472e2201, + 0x80f0b064, + 0x426b2250, + 0x8211b063, + 0x466622c1, + 0x670866d3, + 0x22d18211, + 0x66764658, + 0x81616258, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x6211673f, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e85, + 0x1ce31613, + 0x91c34aaa, + 0x143b81e3, + 0x1cba6296, + 0x1e234691, + 0x1ce34a91, + 0xb2904e91, + 0x42912207, + 0x1a1ba290, + 0x1ce3629c, + 0x91c34aaa, + 0x183b81e3, + 0x4ea61cab, + 0x4aa81c9b, + 0x42aa1cbc, + 0x821010b2, + 0x42a322d0, + 0x221080f0, + 0x646346aa, + 0x62aa66ab, + 0x629a10ab, + 0x629a109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aae, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4ac41c12, + 0xb032b0e2, + 0x673fcfb0, + 0x1421c7f1, + 0xc8124ec8, + 0x91729162, + 0xb0e1b031, + 0x12087000, + 0xc800c006, + 0x91709160, + 0x82017000, + 0x91c081b0, + 0x181081d0, + 0x18108151, + 0x80e11406, + 0x31828242, + 0x1c203d82, + 0xb0e24ae7, + 0x46eb2221, + 0xcfa0b032, + 0x2221673f, + 0xa0e242eb, + 0x8231b032, + 0xc0f03941, + 0x1e010401, + 0x161842f9, + 0x3010c010, + 0x47071c08, + 0x3c101060, + 0xc7f11006, + 0x4efd1461, + 0x9166c816, + 0x31818171, + 0x1c163d81, + 0x91764b04, + 0xc006b031, + 0x70001208, + 0x31818161, + 0x82403d81, + 0x18013980, + 0x4b1a1cf1, + 0x80b01401, + 0x471a22c0, + 0xb033b0bc, + 0x92f1ef90, + 0x673f930f, + 0xa0037000, + 0xb064b063, + 0x655ab0ef, + 0x80407100, + 0x472e2200, + 0x652eb064, + 0x7100a0ef, + 0x22008040, + 0xb064472e, + 0x623eb003, + 0x81628201, + 0x3d823182, + 0x92f1ef80, + 0x673f9302, + 0x655aa003, + 0x80a261eb, + 0x61eb6463, + 0x7100b050, + 0x92e061eb, + 0x220082d0, + 0xb2c04740, + 0x80a07000, + 0x435c22f0, + 0xc102b030, + 0xc0013162, + 0x1e0080a0, + 0x22f04355, + 0xf5d04356, + 0x39603160, + 0x10206356, + 0x6f131a10, + 0x16116e23, + 0x6b571612, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_genfsk(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 431; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchGenfskRfe[i]; + } +#else + const uint32_t *pS = patchGenfskRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 53; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee.h new file mode 100644 index 0000000..b8637b7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee.h @@ -0,0 +1,403 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_ieee.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC26x0 IEEE 802.15.4. Contains fix to correct RSSIMAXVAL calculation. +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_IEEE_H +#define _RF_PATCH_RFE_IEEE_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchZigbeeXsIsRfe[304] = { + 0x00006154, + 0x07f7177f, + 0x004507ff, + 0x0000000f, + 0x002e0004, + 0x0000003f, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x00000000, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x00000000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0x00000007, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x40632241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x686f1614, + 0x10257000, + 0x9100c050, + 0xc140c3f4, + 0x6f031420, + 0x04411031, + 0x22f08250, + 0x26514084, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x64537000, + 0x1031c052, + 0x31610631, + 0x645602c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006456, + 0x9101c051, + 0xc0e2cc01, + 0x64536456, + 0xc0c2c111, + 0xb0546456, + 0xa0547100, + 0x80f0b064, + 0x40b52200, + 0xc122c111, + 0xc0516456, + 0xc0e29101, + 0x82603182, + 0x91320002, + 0xc300b110, + 0x645368c8, + 0x90b01240, + 0xc300b032, + 0xc24068ce, + 0x128068d0, + 0xb03290b0, + 0x64537000, + 0xc122c101, + 0xc1016456, + 0x6456c0c2, + 0x649d8253, + 0x90b012c0, + 0x7000b032, + 0xc2726453, + 0x6456c081, + 0xc111c122, + 0xc0026456, + 0x6456c111, + 0xc331c062, + 0xc3626456, + 0x6456c111, + 0xc111c302, + 0x82536456, + 0x649d3953, + 0x645bc3e2, + 0x40f82211, + 0xc881c242, + 0xc2526456, + 0x6456c111, + 0xcee1c272, + 0xc2026456, + 0x6456c881, + 0xc801c202, + 0xc0b06456, + 0x7000690c, + 0xc2426453, + 0x6456c801, + 0xc011c252, + 0xc2726456, + 0x6456c0e1, + 0xc101c002, + 0xc0626456, + 0x6456c301, + 0xc101c122, + 0xc3626456, + 0x6456c101, + 0xc101c302, + 0x82536456, + 0x7000649d, + 0x3162c102, + 0x80a0c001, + 0x41321e00, + 0x61341a10, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006934, + 0x82d092e0, + 0x453b2200, + 0x7000b2c0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xb0608081, + 0x8092a050, + 0x92f1ef90, + 0x653a9302, + 0x45782241, + 0xc1f18080, + 0x16300410, + 0x14011101, + 0x61896c01, + 0x618b618a, + 0x618d618c, + 0x618f618e, + 0x61936191, + 0x61976195, + 0x625d625a, + 0x31218091, + 0x2a428082, + 0x16321412, + 0x14211101, + 0x61a76c01, + 0x61ad61c1, + 0x61a7625d, + 0x61ad61c1, + 0x6199625d, + 0x61996199, + 0x61996199, + 0x64ac6199, + 0x64d56199, + 0x64e26199, + 0x650e6199, + 0x652a6199, + 0x80826199, + 0x92f2df80, + 0x1210653a, + 0x61a290b0, + 0x90b01220, + 0x72057306, + 0x90301210, + 0xcf706158, + 0xc284653a, + 0xc3c0c003, + 0x78506468, + 0x78609150, + 0x78613110, + 0x92001410, + 0x31407880, + 0x00107861, + 0x78713140, + 0x92100010, + 0x92207890, + 0x926078a0, + 0xa0546199, + 0x225080f0, + 0x804045c9, + 0x46502200, + 0xcf6061c1, + 0x821e653a, + 0x06f910e9, + 0x10ea394e, + 0x10ac06fa, + 0x06fe394e, + 0x647710c2, + 0x10cb822d, + 0x91907820, + 0xb013661b, + 0xb063b053, + 0xb054b050, + 0xb003b064, + 0x225080f0, + 0x710041c1, + 0x22018041, + 0x22414650, + 0xb06441ec, + 0x81b0b063, + 0x81df91c0, + 0x220080f0, + 0x8090464e, + 0x464e2240, + 0x18d310f3, + 0x0bf34e01, + 0x1ce31613, + 0x91c34a4e, + 0x143b81e3, + 0x1ce36206, + 0x91c34a4e, + 0x183b81e3, + 0x4e171cab, + 0x4a191c9b, + 0x424e1cbc, + 0x10b210bc, + 0x662b6477, + 0xb063662b, + 0xb0637100, + 0xb0637100, + 0x10ab61e2, + 0x109b620a, + 0x7837620a, + 0x18707840, + 0xc0011a10, + 0x16176e71, + 0x78376a20, + 0xc0061208, + 0x9160c800, + 0x10007000, + 0x10f01000, + 0x18108201, + 0x6d716d71, + 0x14061816, + 0x16176e70, + 0x1c177841, + 0x78374638, + 0x1e881618, + 0x1060464b, + 0x81513d30, + 0x80f11810, + 0x41c12251, + 0x81719160, + 0x3d813181, + 0x4a491c10, + 0xb0319170, + 0x70001278, + 0x10001000, + 0x61e2662b, + 0x81628201, + 0x3d823182, + 0x92f1ef50, + 0x653a9302, + 0x6199a003, + 0x647780a2, + 0xb0506199, + 0x61997100 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_ieee(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 304; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchZigbeeXsIsRfe[i]; + } +#else + const uint32_t *pS = patchZigbeeXsIsRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 38; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee_s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee_s.h new file mode 100644 index 0000000..19c30bb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee_s.h @@ -0,0 +1,403 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_ieee_s.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for CC26x0 IEEE 802.15.4 Single Ended Output +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_IEEE_S_H +#define _RF_PATCH_RFE_IEEE_S_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchZigbeeXsIsRfe[304] = { + 0x00006154, + 0x07f7177f, + 0x004507ff, + 0x0000000f, + 0x002e0004, + 0x0000003f, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x00000000, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x00000000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0x00000007, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x40632241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x686f1614, + 0x10257000, + 0x9100c050, + 0xc140c3f4, + 0x6f031420, + 0x04411031, + 0x22f08250, + 0x26514084, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x64537000, + 0x1031c052, + 0x31610631, + 0x645602c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006456, + 0x9101c051, + 0xc0e2cc01, + 0x64536456, + 0xc0c2c111, + 0xb0546456, + 0xa0547100, + 0x80f0b064, + 0x40b52200, + 0xc122c111, + 0xc0516456, + 0xc0e29101, + 0x82603182, + 0x91320002, + 0xc300b110, + 0x645368c8, + 0x90b01240, + 0xc300b032, + 0xc24068ce, + 0x128068d0, + 0xb03290b0, + 0x64537000, + 0xc122c101, + 0xc1016456, + 0x6456c0c2, + 0x649d8253, + 0x90b012c0, + 0x7000b032, + 0xc2726453, + 0x6456c081, + 0xc111c122, + 0xc0026456, + 0x6456c111, + 0xc331c062, + 0xc3626456, + 0x6456c111, + 0xc111c302, + 0x82536456, + 0x649d3953, + 0x645bc3e2, + 0x40f82211, + 0xc881c242, + 0xc2526456, + 0x6456c111, + 0xcee1c272, + 0xc2026456, + 0x6456c881, + 0xc801c202, + 0xc0b06456, + 0x7000690c, + 0xc2426453, + 0x6456c801, + 0xc011c252, + 0xc2726456, + 0x6456c0e1, + 0xc101c002, + 0xc0626456, + 0x6456c301, + 0xc101c122, + 0xc3626456, + 0x6456c101, + 0xc101c302, + 0x82536456, + 0x7000649d, + 0x3162c102, + 0x80a0c001, + 0x41321e00, + 0x61341a10, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006934, + 0x82d092e0, + 0x453b2200, + 0x7000b2c0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xb0608081, + 0x8092a050, + 0x92f1ef90, + 0x653a9302, + 0x45782241, + 0xc1f18080, + 0x16300410, + 0x14011101, + 0x61896c01, + 0x618b618a, + 0x618d618c, + 0x618f618e, + 0x61936191, + 0x61976195, + 0x625d625a, + 0x31218091, + 0x2a428082, + 0x16321412, + 0x14211101, + 0x61a76c01, + 0x61ad61c1, + 0x61a7625d, + 0x61ad61c1, + 0x6199625d, + 0x61996199, + 0x61996199, + 0x64ac6199, + 0x64d56199, + 0x64e26199, + 0x650e6199, + 0x652a6199, + 0x80826199, + 0x92f2df80, + 0x1210653a, + 0x61a290b0, + 0x90b01220, + 0x72057306, + 0x90301210, + 0xcf706158, + 0xc284653a, + 0xc3c0c003, + 0x78506468, + 0x78609150, + 0x78613110, + 0x92001410, + 0x31407880, + 0x00107861, + 0x78713140, + 0x92100010, + 0x92207890, + 0x926078a0, + 0xa0546199, + 0x225080f0, + 0x804045c9, + 0x46502200, + 0xcf6061c1, + 0x821e653a, + 0x06f910e9, + 0x10ea394e, + 0x10ac06fa, + 0x06fe394e, + 0x647710c2, + 0x10cb822d, + 0x91907820, + 0xb013661b, + 0xb063b053, + 0xb054b050, + 0xb003b064, + 0x225080f0, + 0x710041c1, + 0x22018041, + 0x22414650, + 0xb06441ec, + 0x81b0b063, + 0x81df91c0, + 0x220080f0, + 0x8090464e, + 0x464e2240, + 0x18d310f3, + 0x0bf34e01, + 0x1ce31613, + 0x91c34a4e, + 0x143b81e3, + 0x1ce36206, + 0x91c34a4e, + 0x183b81e3, + 0x4e171cab, + 0x4a191c9b, + 0x424e1cbc, + 0x10b210bc, + 0x662b6477, + 0xb063662b, + 0xb0637100, + 0xb0637100, + 0x10ab61e2, + 0x109b620a, + 0x7837620a, + 0x18707840, + 0xc0011a10, + 0x16176e71, + 0x78376a20, + 0xc0061208, + 0x9160c800, + 0x10007000, + 0x10f01000, + 0x18108201, + 0x6d716d71, + 0x14061816, + 0x16176e70, + 0x1c177841, + 0x78374638, + 0x1e881618, + 0x1060464b, + 0x81513d30, + 0x80f11810, + 0x41c12251, + 0x81719160, + 0x3d813181, + 0x4a491c10, + 0xb0319170, + 0x70001278, + 0x10001000, + 0x61e2662b, + 0x81628201, + 0x3d823182, + 0x92f1ef50, + 0x653a9302, + 0x6199a003, + 0x647780a2, + 0xb0506199, + 0x61997100 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_ieee_s(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 304; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchZigbeeXsIsRfe[i]; + } +#else + const uint32_t *pS = patchZigbeeXsIsRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 38; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); +#endif +} + +#endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rom/driverlib.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rom/driverlib.c new file mode 100644 index 0000000..c8d20d9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rom/driverlib.c @@ -0,0 +1,7823 @@ +//##### AUTO GENERATED FILE...DO NOT EDIT ##### +// +// This file is autogenerated from the project definition +// and module includes defined in the 'APITable.xls' +// +//##### AUTO GENERATED FILE...DO NOT EDIT ##### +#undef DEBUG +#include "lib_src/hw_ioc.h" +#include "lib_src/hw_nvic.h" +#include "lib_src/hw_gpio.h" +#include "lib_src/hw_flash.h" +#include "lib_src/hw_device.h" +#include "lib_src/hw_aux_tdc.h" +#include "lib_src/hw_ints.h" +#include "lib_src/hw_i2c.h" +#include "lib_src/hw_trng.h" +#include "lib_src/hw_gpt.h" +#include "lib_src/hw_uart.h" +#include "lib_src/hw_smph.h" +#include "lib_src/hw_aon_rtc.h" +#include "lib_src/hw_aon_wuc.h" +#include "lib_src/hw_vims.h" +#include "lib_src/hw_aon_event.h" +#include "lib_src/hw_memmap.h" +#include "lib_src/hw_aon_ioc.h" +#include "lib_src/hw_aux_wuc.h" +#include "lib_src/hw_sysctl.h" +#include "lib_src/hw_udma.h" +#include "lib_src/hw_ssi.h" +#include "lib_src/hw_aux_sce.h" +#include "lib_src/hw_aon_sysctl.h" +#include "lib_src/hw_factory_cfg.h" +#include "lib_src/hw_types.h" +#include "lib_src/hw_ddi.h" +#include "lib_src/hw_aux_timer.h" +#include "lib_src/hw_spis.h" +#include "lib_src/hw_prcm.h" +#include "lib_src/aon_event.h" +#include "lib_src/aon_ioc.h" +#include "lib_src/aon_rtc.h" +#include "lib_src/aon_wuc.h" +#include "lib_src/aux_ctrl.h" +#include "lib_src/aux_tdc.h" +#include "lib_src/aux_timer.h" +#include "lib_src/aux_wuc.h" +#include "lib_src/ddi.h" +#include "lib_src/flash.h" +#include "lib_src/i2c.h" +#include "lib_src/interrupt.h" +#include "lib_src/ioc.h" +#include "lib_src/prcm.h" +#include "lib_src/smph.h" +#include "lib_src/spis.h" +#include "lib_src/ssi.h" +#include "lib_src/timer.h" +#include "lib_src/trng.h" +#include "lib_src/uart.h" +#include "lib_src/udma.h" +#include "lib_src/vims.h" +#include "lib_src/cpu.h" +#include "lib_src/gpio.h" +#include "lib_src/debug.h" +// +// Include interrupt functions for based ROM code +// +//***************************************************************************** +// +//! Disable all external interrupts +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) +uint32_t __attribute__((naked)) +CPUcpsid(void) +{ + uint32_t ui32Ret; + + // + // Read PRIMASK and disable interrupts + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n" + : "=r"(ui32Ret)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ui32Ret); +} +#endif +#if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN) +uint32_t +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + mrs r0, PRIMASK; + cpsid i; + bx lr +} +#endif +#if defined(__TI_COMPILER_VERSION__) +uint32_t +CPUcpsid(void) +{ + // + // Read PRIMASK and disable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Enable all external interrupts +// +//***************************************************************************** +#if defined(codered) || defined(gcc) || defined(sourcerygxx) + uint32_t __attribute__((naked)) +CPUcpsie(void) +{ + uint32_t ui32Ret; + + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n" + : "=r"(ui32Ret)); + + // + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + // + return(ui32Ret); +} +#endif +#if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN) + uint32_t +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n"); + + // + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. + // +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + mrs r0, PRIMASK; + cpsie i; + bx lr +} +#endif +#if defined(__TI_COMPILER_VERSION__) + uint32_t +CPUcpsie(void) +{ + // + // Read PRIMASK and enable interrupts. + // + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n"); + + // + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + // + return(0); +} +#endif +//! \\addtogroup aon_event_api +//! @{ +//***************************************************************************** +// +//! Select event source for the specified MCU wakeup programmable event +// +//***************************************************************************** +void +AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // + // Check the arguments. + // + ASSERT((ui32MCUWUEvent == AON_EVENT_MCU_WU0) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU1) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU2) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU3)); + ASSERT(ui32EventSrc <= AON_EVENT_NULL); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL); + + if(ui32MCUWUEvent == AON_EVENT_MCU_WU0) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU0_EV_S; + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU1) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU1_EV_S; + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU2) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU2_EV_S; + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU3) + { + ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU3_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU3_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) = ui32Ctrl; +} +//***************************************************************************** +// +//! Get event source for the specified MCU wakeup programmable event +// +//***************************************************************************** +uint32_t +AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent) +{ + uint32_t ui32EventSrc; + + // + // Check the arguments. + // + ASSERT((ui32MCUWUEvent == AON_EVENT_MCU_WU0) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU1) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU2) || + (ui32MCUWUEvent == AON_EVENT_MCU_WU3)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL); + + if(ui32MCUWUEvent == AON_EVENT_MCU_WU0) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU0_EV_M) >> + AON_EVENT_MCUWUSEL_WU0_EV_S); + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU1) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU1_EV_M) >> + AON_EVENT_MCUWUSEL_WU1_EV_S); + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU2) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU2_EV_M) >> + AON_EVENT_MCUWUSEL_WU2_EV_S); + } + else if(ui32MCUWUEvent == AON_EVENT_MCU_WU3) + { + return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU3_EV_M) >> + AON_EVENT_MCUWUSEL_WU3_EV_S); + } + + // + // Should never get to this statement, but suppress warning. + // + ASSERT(0); + return(0); +} +//***************************************************************************** +// +//! Select event source for the specified AUX wakeup programmable event +// +//***************************************************************************** +void +AONEventAuxWakeUpSet(uint32_t ui32AUXWUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // + // Check the arguments. + // + ASSERT((ui32AUXWUEvent == AON_EVENT_AUX_WU0) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU1) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU2)); + ASSERT(ui32EventSrc <= AON_EVENT_NULL); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL); + + if(ui32AUXWUEvent == AON_EVENT_AUX_WU0) + { + ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU0_EV_S; + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU1) + { + ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU1_EV_S; + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU2) + { + ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU2_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL) = ui32Ctrl; +} +//***************************************************************************** +// +//! Get event source for the specified AUX wakeup programmable event +// +//***************************************************************************** +uint32_t +AONEventAuxWakeUpGet(uint32_t ui32AUXWUEvent) +{ + uint32_t ui32EventSrc; + + // + // Check the arguments. + // + ASSERT((ui32AUXWUEvent == AON_EVENT_AUX_WU0) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU1) || + (ui32AUXWUEvent == AON_EVENT_AUX_WU2)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL); + + if(ui32AUXWUEvent == AON_EVENT_AUX_WU0) + { + return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU0_EV_M) >> + AON_EVENT_AUXWUSEL_WU0_EV_S); + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU1) + { + return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU1_EV_M) >> + AON_EVENT_AUXWUSEL_WU1_EV_S); + } + else if(ui32AUXWUEvent == AON_EVENT_AUX_WU2) + { + return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU2_EV_M) >> + AON_EVENT_AUXWUSEL_WU2_EV_S); + } + + // + // Should never get to this statement, but suppress warning. + // + ASSERT(0); + return(0); +} +//***************************************************************************** +// +//! Select event source for the specified programmable event forwarded to the +//! MCU event fabric +// +//***************************************************************************** +void +AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // + // Check the arguments. + // + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + ASSERT(ui32EventSrc <= AON_EVENT_NULL); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL) = ui32Ctrl; +} +//***************************************************************************** +// +//! Get source for the specified programmable event forwarded to the MCU event +//! fabric. +// +//***************************************************************************** +uint32_t +AONEventMcuGet(uint32_t ui32MCUEvent) +{ + uint32_t ui32EventSrc; + + // + // Check the arguments. + // + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S); + } + + // + // Should never get to this statement, but supress warning. + // + ASSERT(0); + return(0); +} +//! @} +//! \\addtogroup aon_ioc_api +//! @{ +//***************************************************************************** +// +//! Setup the drive strength for all IOs on the chip +// +//***************************************************************************** +void +AONIOCDriveStrengthSet(uint32_t ui32LowDrvStr, uint32_t ui32MedDrvStr, + uint32_t ui32MaxDrvStr) +{ + ASSERT((ui32LowDrvStr == AONIOC_DRV_STR5_7_14) || + (ui32LowDrvStr == AONIOC_DRV_STR5_10_20) || + (ui32LowDrvStr == AONIOC_DRV_STR7_14_28) || + (ui32LowDrvStr == AONIOC_DRV_STR10_20_40) || + (ui32LowDrvStr == AONIOC_DRV_STR14_28_56) || + (ui32LowDrvStr == AONIOC_DRV_STR20_40_80) || + (ui32LowDrvStr == AONIOC_DRV_STR28_56_112) || + (ui32LowDrvStr == AONIOC_DRV_STR40_80_112)); + ASSERT((ui32MedDrvStr == AONIOC_DRV_STR5_7_14) || + (ui32MedDrvStr == AONIOC_DRV_STR5_10_20) || + (ui32MedDrvStr == AONIOC_DRV_STR7_14_28) || + (ui32MedDrvStr == AONIOC_DRV_STR10_20_40) || + (ui32MedDrvStr == AONIOC_DRV_STR14_28_56) || + (ui32MedDrvStr == AONIOC_DRV_STR20_40_80) || + (ui32MedDrvStr == AONIOC_DRV_STR28_56_112) || + (ui32MedDrvStr == AONIOC_DRV_STR40_80_112)); + ASSERT((ui32MaxDrvStr == AONIOC_DRV_STR5_7_14) || + (ui32MaxDrvStr == AONIOC_DRV_STR5_10_20) || + (ui32MaxDrvStr == AONIOC_DRV_STR7_14_28) || + (ui32MaxDrvStr == AONIOC_DRV_STR10_20_40) || + (ui32MaxDrvStr == AONIOC_DRV_STR14_28_56) || + (ui32MaxDrvStr == AONIOC_DRV_STR20_40_80) || + (ui32MaxDrvStr == AONIOC_DRV_STR28_56_112) || + (ui32MaxDrvStr == AONIOC_DRV_STR40_80_112)); + + // + // Set the minimum drive strength. + // + HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMIN) = ui32LowDrvStr & + AON_IOC_IOSTRMIN_GRAY_CODE_M; + // + // Set the medium drive strength. + // + HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMED) = ui32MedDrvStr & + AON_IOC_IOSTRMED_GRAY_CODE_M; + // + // Set the maximum drive strength. + // + HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMAX) = ui32MaxDrvStr & + AON_IOC_IOSTRMAX_GRAY_CODE_M; + +} +//***************************************************************************** +// +//! Get a specific drive level setting for all IOs +// +//***************************************************************************** +uint32_t +AONIOCDriveStrengthGet(uint32_t ui32DriveLevel) +{ + uint32_t ui32DrvStr; + + // + // Check the arguments. + // + ASSERT((ui32DriveLevel == AONIOC_MAX_DRIVE) || + (ui32DriveLevel == AONIOC_MED_DRIVE) || + (ui32DriveLevel == AONIOC_MIN_DRIVE)); + + // + // Get the specified drive strength level. + // + if(ui32DriveLevel == AONIOC_MAX_DRIVE) + { + ui32DrvStr = HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMAX); + } + else if(ui32DriveLevel == AONIOC_MED_DRIVE) + { + ui32DrvStr = HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMED); + } + else + { + ui32DrvStr = HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMIN); + } + + // + // Return the drive strength value. + // + return(ui32DrvStr); +} +//! @} +//! \\addtogroup aon_rtc_api +//! @{ +//***************************************************************************** +// +//! Check if the AON Real Time Clock is running. +// +//***************************************************************************** +uint32_t +AONRTCStatus(void) +{ + uint32_t ui32ChannelStatus; + uint32_t ui32RtcStatus; + + // + // Read out the status' + // + ui32ChannelStatus = HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL); + ui32RtcStatus = HWREG(AON_RTC_BASE + AON_RTC_O_CTL) & + AON_RTC_CTL_EN ? AON_RTC_ACTIVE : 0; + + // + // Return the status + // + ui32RtcStatus |= (ui32ChannelStatus & AON_RTC_CHCTL_CH2_EN ? + AON_RTC_CH2 : 0) | + (ui32ChannelStatus & AON_RTC_CHCTL_CH1_EN ? + AON_RTC_CH1 : 0) | + (ui32ChannelStatus & AON_RTC_CHCTL_CH0_EN ? + AON_RTC_CH0 : 0); + return ui32RtcStatus; +} +//***************************************************************************** +// +//! Clear event from a specified channel +// +//***************************************************************************** +void +AONRTCEventClear(uint32_t ui32Channel) +{ + // + // Check the arguments. + // + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH0; + } + else if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH1; + } + else if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH2; + } +} +//***************************************************************************** +// +//! Get event status for a specified channel +// +//***************************************************************************** +bool +AONRTCEventGet(uint32_t ui32Channel) +{ + // + // Check the arguments. + // + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + return ((HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) & + AON_RTC_EVFLAGS_CH0) ? true : false); + } + else if(ui32Channel & AON_RTC_CH1) + { + return ((HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) & + AON_RTC_EVFLAGS_CH1) ? true : false); + } + else if(ui32Channel & AON_RTC_CH2) + { + return ((HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) & + AON_RTC_EVFLAGS_CH2) ? true : false); + } + + return(false); +} +//***************************************************************************** +// +//! Set operational mode of channel 1 +// +//***************************************************************************** +void +AONRTCModeCh1Set(uint32_t ui32Mode) +{ + // + // Check the arguments. + // + ASSERT((ui32Mode == AON_RTC_MODE_CH1_CAPTURE) || + (ui32Mode == AON_RTC_MODE_CH1_COMPARE)); + + if(ui32Mode == AON_RTC_MODE_CH1_CAPTURE) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH1_CAPT_EN; + } + else if(ui32Mode == AON_RTC_MODE_CH1_COMPARE) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH1_CAPT_EN); + } +} +//***************************************************************************** +// +//! Get operational mode of channel 1 +// +//***************************************************************************** +uint32_t +AONRTCModeCh1Get(void) +{ + if(HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) & AON_RTC_CHCTL_CH1_CAPT_EN) + { + return(AON_RTC_MODE_CH1_CAPTURE); + } + else + { + return(AON_RTC_MODE_CH1_COMPARE); + } +} +//***************************************************************************** +// +//! Set operational mode of channel 2 +// +//***************************************************************************** +void +AONRTCModeCh2Set(uint32_t ui32Mode) +{ + // + // Check the arguments. + // + ASSERT((ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) || + (ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE)); + + if(ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH2_CONT_EN; + } + else if(ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH2_CONT_EN); + } +} +//***************************************************************************** +// +//! Get operational mode of channel 2 +// +//***************************************************************************** +uint32_t +AONRTCModeCh2Get(void) +{ + if(HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) & AON_RTC_CHCTL_CH2_CONT_EN) + { + return(AON_RTC_MODE_CH2_CONTINUOUS); + } + else + { + return(AON_RTC_MODE_CH2_NORMALCOMPARE); + } +} +//***************************************************************************** +// +//! Enable event operation for the specified channel +// +//***************************************************************************** +void +AONRTCChannelEnable(uint32_t ui32Channel) +{ + // + // Check the arguments. + // + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH0_EN; + } + else if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH1_EN; + } + else if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH2_EN; + } +} +//***************************************************************************** +// +//! Disable event operation for the specified channel +// +//***************************************************************************** +void +AONRTCChannelDisable(uint32_t ui32Channel) +{ + // + // Check the arguments. + // + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH0_EN); + } + else if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH1_EN); + } + else if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH2_EN); + } +} +//***************************************************************************** +// +//! Set the compare value for the given channel +// +//***************************************************************************** +void +AONRTCCompareValueSet(uint32_t ui32Channel, uint32_t ui32CompValue) +{ + // + // Check the arguments. + // + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP) = ui32CompValue; + } + else if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP) = ui32CompValue; + } + else if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP) = ui32CompValue; + } +} +//***************************************************************************** +// +//! Get the compare value for the given channel +// +//***************************************************************************** +uint32_t +AONRTCCompareValueGet(uint32_t ui32Channel) +{ + // + // Check the arguments + // + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP)); + } + else if(ui32Channel & AON_RTC_CH1) + { + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP)); + } + else if(ui32Channel & AON_RTC_CH2) + { + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP)); + } + // + // Should never return from here! + // + return(0); +} +//***************************************************************************** +// +//! Get the current value of the RTC counter in a format compatible to the +//! compare registers. +// +//***************************************************************************** +uint32_t +AONRTCCurrentCompareValueGet(void) +{ + uint32_t ui32CurrentSec0; + uint32_t ui32CurrentSec1; + uint32_t ui32CurrentSubSec; + + // + // Read the integer part of the RTC counter + // + ui32CurrentSec0 = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + + // + // Read the fractional part of the RTC counter. Make sure the fractional + // part has not rolled over and incremented the integer part. + // + do { + ui32CurrentSubSec = HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC); + ui32CurrentSec1 = ui32CurrentSec0; + ui32CurrentSec0 = HWREG(AON_RTC_BASE + AON_RTC_O_SEC); + } while(ui32CurrentSec0 != ui32CurrentSec1); + + // + // Return the RTC value in the correct format + // + return ((ui32CurrentSec0 << 16) | (ui32CurrentSubSec >> 16)); +} +//! @} +//! \\addtogroup aon_wuc_api +//! @{ +//***************************************************************************** +// +//! Set the clock source for the AUX domain +// +//***************************************************************************** +void +AONWUCAuxClockConfigSet(uint32_t ui32ClkSrc, uint32_t ui32ClkDiv) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT((ui32ClkSrc == AONWUC_CLOCK_SRC_HF) || + (ui32ClkSrc == AONWUC_CLOCK_SRC_MF) || + (ui32ClkSrc == AONWUC_CLOCK_SRC_LF)); + ASSERT((ui32ClkDiv == AUX_CLOCK_DIV_2) || + (ui32ClkDiv == AUX_CLOCK_DIV_4) || + (ui32ClkDiv == AUX_CLOCK_DIV_8) || + (ui32ClkDiv == AUX_CLOCK_DIV_16) || + (ui32ClkDiv == AUX_CLOCK_DIV_32) || + (ui32ClkDiv == AUX_CLOCK_DIV_64) || + (ui32ClkDiv == AUX_CLOCK_DIV_128) || + (ui32ClkDiv == AUX_CLOCK_DIV_256) || + (ui32ClkDiv == AUX_CLOCK_DIV_UNUSED)); + + // + // Configure the clock for the AUX domain. + // + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK); + + // + // Check if we need to update the clock division factor + // + if(ui32ClkDiv != AUX_CLOCK_DIV_UNUSED) + { + ui32Reg = (ui32Reg & ~AON_WUC_AUXCLK_SCLK_HF_DIV_M) | ui32ClkDiv; + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg; + + // If switching to a HF clocks source for AUX it is necessary to + // synchronize the write on the AON RTC to ensure the clock division is + // updated before requesting the clock source + // + if(ui32ClkSrc == AONWUC_CLOCK_SRC_HF) + { + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); + } + } + + // + // Configure the clock for the AUX domain. + // + ui32Reg &= ~AON_WUC_AUXCLK_SRC_M; + if(ui32ClkSrc == AONWUC_CLOCK_SRC_HF) + { + ui32Reg |= AON_WUC_AUXCLK_SRC_SCLK_HF; + } + else if(ui32ClkSrc == AONWUC_CLOCK_SRC_MF) + { + ui32Reg |= AON_WUC_AUXCLK_SRC_SCLK_MF; + } + else if(ui32ClkSrc == AONWUC_CLOCK_SRC_LF) + { + ui32Reg |= AON_WUC_AUXCLK_SRC_SCLK_LF; + } + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg; +} +//***************************************************************************** +// +//! Configure the rentention on the AUX SRAM +// +//***************************************************************************** +void +AONWUCAuxSRamConfig(uint32_t ui32Retention) +{ + + // + // Enable/disable the retention. + // + if(ui32Retention) + { + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCFG) |= AON_WUC_AUXCFG_SRAM_RET_EN; + } + else + { + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCFG) &= ~AON_WUC_AUXCFG_SRAM_RET_EN; + } +} +//***************************************************************************** +// +//! Control the wake up procedure of the AUX domain +// +//***************************************************************************** +void +AONWUCAuxWakeupEvent(uint32_t ui32Mode) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT((ui32Mode == AONWUC_AUX_WAKEUP_SWEVT) || + (ui32Mode == AONWUC_AUX_WAKEUP) || + (ui32Mode == AONWUC_AUX_ALLOW_SLEEP)); + + // + // Wake up the AUX domain. + // + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL); + + if(ui32Mode == AONWUC_AUX_ALLOW_SLEEP) + { + ui32Reg &= ~AON_WUC_AUXCTL_AUX_FORCE_ON; + } + else + { + ui32Reg |= ui32Mode; + } + + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) = ui32Reg; +} +//***************************************************************************** +// +//! Reset the AUX domain +// +//***************************************************************************** +void +AONWUCAuxReset(void) +{ + // + // Reset the AUX domain. + // + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) |= AON_WUC_AUXCTL_RESET_REQ; + + // + // Wait for AON interface to be in sync. + // + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); + + // + // De-assert reset on the AUX domain. + // + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) &= ~AON_WUC_AUXCTL_RESET_REQ; + + // + // Wait for AON interface to be in sync. + // + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} +//***************************************************************************** +// +//! Configure the recharge controller +// +//***************************************************************************** +void +AONWUCRechargeCtrlConfigSet(bool bAdaptEnable, uint32_t ui32AdaptRate, + uint32_t ui32Period, uint32_t ui32MaxPeriod) +{ + uint32_t ui32Shift; + uint32_t ui32C1; + uint32_t ui32C2; + uint32_t ui32Reg; + uint32_t ui32Exponent; + uint32_t ui32MaxExponent; + uint32_t ui32Mantissa; + uint32_t ui32MaxMantissa; + + // + // Check the arguments. + // + ASSERT((ui32AdaptRate >= RC_RATE_MIN) || + (ui32AdaptRate <= RC_RATE_MAX)); + + ui32C1 = 0; + ui32C2 = 0; + ui32Shift = 9; + + // + // Clear the previous values. + // + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG); + ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M | + AON_WUC_RECHARGECFG_ADAPTIVE_EN_M | AON_WUC_RECHARGECFG_PER_M_M | + AON_WUC_RECHARGECFG_PER_E_M | AON_WUC_RECHARGECFG_C1_M | + AON_WUC_RECHARGECFG_C2_M); + + // + // Check if the recharge controller adaption algorithm should be active. + // + if(bAdaptEnable) + { + // + // Calculate adaption parameters. + // + while(ui32AdaptRate) + { + if(ui32AdaptRate & (1 << ui32Shift)) + { + if(!ui32C1) + { + ui32C1 = ui32Shift; + } + else if(!ui32C2) + { + if((2 * ui32AdaptRate) > ((uint32_t)(3 << ui32Shift))) + { + ui32C2 = ui32Shift + 1; + } + else + { + ui32C2 = ui32Shift; + } + } + else + { + break; + } + ui32AdaptRate &= ~(1 << ui32Shift); + } + ui32Shift--; + } + if(!ui32C2) + { + ui32C2 = ui32C1 = ui32C1 - 1; + } + + ui32C1 = 10 - ui32C1; + ui32C2 = 10 - ui32C2; + + // + // Update the recharge rate parameters. + // + ui32Reg &= ~(AON_WUC_RECHARGECFG_C1_M | AON_WUC_RECHARGECFG_C2_M); + ui32Reg |= (ui32C1 << AON_WUC_RECHARGECFG_C1_S) | + (ui32C2 << AON_WUC_RECHARGECFG_C2_S) | + AON_WUC_RECHARGECFG_ADAPTIVE_EN_M; + } + + // + // Resolve the period into an exponent and mantissa. + // + ui32Period = (ui32Period >> 4); + ui32Exponent = 0; + while(ui32Period > (AON_WUC_RECHARGECFG_PER_M_M >> AON_WUC_RECHARGECFG_PER_M_S)) + { + ui32Period >>= 1; + ui32Exponent++; + } + ui32Mantissa = ui32Period; + + // + // Resolve the max period into an exponent and mantissa. + // + ui32MaxPeriod = (ui32MaxPeriod >> 4); + ui32MaxExponent = 0; + while(ui32MaxPeriod > (AON_WUC_RECHARGECFG_MAX_PER_M_M >> AON_WUC_RECHARGECFG_MAX_PER_M_S)) + { + ui32MaxPeriod >>= 1; + ui32MaxExponent++; + } + ui32MaxMantissa = ui32MaxPeriod; + + + // + // Configure the controller. + // + ui32Reg |= ((ui32MaxMantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) | + (ui32MaxExponent << AON_WUC_RECHARGECFG_MAX_PER_E_S) | + (ui32Mantissa << AON_WUC_RECHARGECFG_PER_M_S) | + (ui32Exponent << AON_WUC_RECHARGECFG_PER_E_S)); + HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg; + +} +//***************************************************************************** +// +//! Configure the interval for oscillator amplitude calibration +// +//***************************************************************************** +void +AONWUCOscConfig(uint32_t ui32Period) +{ + uint32_t ui32Mantissa; + uint32_t ui32Exponent; + uint32_t ui32Reg; + + // + // Resolve the period into a exponent and mantissa. + // + ui32Period = (ui32Period >> 4); + ui32Exponent = 0; + while(ui32Period > (AON_WUC_OSCCFG_PER_M_M >> AON_WUC_OSCCFG_PER_M_S)) + { + ui32Period >>= 1; + ui32Exponent++; + } + ui32Mantissa = ui32Period; + + // + // Update the period for the oscillator amplitude calibration. + // + HWREG(AON_WUC_BASE + AON_WUC_O_OSCCFG) = + (ui32Mantissa << AON_WUC_OSCCFG_PER_M_S) | + (ui32Exponent << AON_WUC_OSCCFG_PER_E_S); + + // + // Set the maximum reacharge period equal to the oscillator amplitude + // calibration period. + // + ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG); + ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M); + ui32Reg |= ((ui32Mantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) | + (ui32Exponent << AON_WUC_RECHARGECFG_MAX_PER_E_S)); + + // + // Write the configuration. + // + HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg; +} +//! @} +//! \\addtogroup aux_ctrl_api +//! @{ +//***************************************************************************** +// +//! Load AUX controller Firmware into dedicated RAM +// +//***************************************************************************** +void +AUXCTRLImageLoad(uint16_t *pui16Image, uint32_t ui32StartAddr, + uint32_t ui32Size) +{ + uint16_t* pui16Src16; + uint16_t* pui16Dst16; + uint32_t ui32WordCnt; + + // + // Check the arguments. + // + ASSERT(ui32StartAddr < 512); + ASSERT(ui32Size <= 1024); + ASSERT((ui32Size / 2 + ui32StartAddr) <= 512); + + // + // Copy image to AUX RAM. + // + ui32WordCnt = (ui32Size >> 1); + pui16Src16 = pui16Image; + pui16Dst16 = (uint16_t*)(AUX_RAM_BASE + (ui32StartAddr << 1)); + + while(ui32WordCnt--) + { + *pui16Dst16++ = *pui16Src16++; + } +} +//! @} +//! \\addtogroup aux_tdc_api +//! @{ +//***************************************************************************** +// +//! Configure the operation of the AUX TDC +// +//***************************************************************************** +void +AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, + uint32_t ui32StopCondition) +{ + // + // Check the arguments. + // + ASSERT(AUXTDCBaseValid(ui32Base)); + + // + // Make sure the AUX TDC is in the idle state before changing the + // configuration. + // + while(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + } + + // + // Clear previous results. + // + HWREG(ui32Base + AUX_TDC_O_CTL) = 0x0; + + // + // Change the configuration. + // + HWREG(ui32Base + AUX_TDC_O_TRIGSRC) = ui32StartCondition | ui32StopCondition; +} +//***************************************************************************** +// +//! Check if the AUX TDC is done measuring +// +//***************************************************************************** +uint32_t +AUXTDCMeasurementDone(uint32_t ui32Base) +{ + uint32_t ui32Reg; + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(AUXTDCBaseValid(ui32Base)); + + // + // Check if the AUX TDC is done measuring. + // + ui32Reg = HWREG(ui32Base + AUX_TDC_O_STAT); + if(ui32Reg & AUX_TDC_STAT_DONE) + { + ui32Status = AUX_TDC_DONE; + } + else if(ui32Reg & AUX_TDC_STAT_SAT) + { + ui32Status = AUX_TDC_TIMEOUT; + } + else + { + ui32Status = AUX_TDC_BUSY; + } + + // + // Return the status. + // + return (ui32Status); +} +//! @} +//! \\addtogroup aux_timer_api +//! @{ +//***************************************************************************** +// +//! Configure AUX timer +// +//***************************************************************************** +void +AUXTimerConfigure(uint32_t ui32Timer, uint32_t ui32Config) +{ + uint32_t ui32Val; + + // + // Check the arguments. + // + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + ASSERT(((ui32Config & 0x0000000F) == AUX_TIMER_CFG_ONE_SHOT) || + ((ui32Config & 0x0000000F) == AUX_TIMER_CFG_PERIODIC) || + ((ui32Config & 0x0000000F) == AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT) || + ((ui32Config & 0x0000000F) == AUX_TIMER_CFG_PERIODIC_EDGE_COUNT) || + ((ui32Config & 0x000000F0) == AUX_TIMER_CFG_RISING_EDGE) || + ((ui32Config & 0x000000F0) == AUX_TIMER_CFG_FALLING_EDGE) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_RTC_EVENT) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_CMP_A) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_CMP_B) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_TDCDONE) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_SMPH_RELEASE) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_ADC_DONE) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO0) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO1) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO2) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO3) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO4) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO5) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO6) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO7) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO8) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO9) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO10) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO11) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO12) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO13) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO14) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO15) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_ACLK_REF) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_MCU_EVENT) || + ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_ADC_IRQ)); + + // + // Configure Timer 0. + // + if(ui32Timer & AUX_TIMER_0) + { + // + // Stop timer 0. + // + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = 0; + + // + // Set mode. + // + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); + ui32Val &= ~(AUX_TIMER_T0CFG_MODE_M | AUX_TIMER_T0CFG_RELOAD_M); + ui32Val |= (ui32Config & (AUX_TIMER_T0CFG_MODE_M | + AUX_TIMER_T0CFG_RELOAD_M)); + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; + + // + // If edge counter, set rising/falling edge and tick source. + // + if(ui32Config & AUX_TIMER_T0CFG_MODE_M) + { + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); + ui32Val &= ~(AUX_TIMER_T0CFG_TICK_SRC_POL_M | + AUX_TIMER_T0CFG_TICK_SRC_M); + + // + // Set edge polarity. + // + if(ui32Config & AUX_TIMER_CFG_FALLING_EDGE) + { + ui32Val |= AUX_TIMER_T0CFG_TICK_SRC_POL; + } + + // + // Set tick source. + // + ui32Val |= ((ui32Config & 0x00000F00) >> 8) << + AUX_TIMER_T0CFG_TICK_SRC_S; + + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; + } + } + + // + // Configure Timer 1. + // + if(ui32Timer & AUX_TIMER_1) + { + // + // Stop timer 1. + // + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = 0; + + // + // Set mode. + // + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); + ui32Val &= ~(AUX_TIMER_T1CFG_MODE_M | AUX_TIMER_T1CFG_RELOAD_M); + ui32Val |= ((ui32Config) & (AUX_TIMER_T1CFG_MODE_M | + AUX_TIMER_T1CFG_RELOAD_M)); + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; + + // + // If edge counter, set rising/falling edge and tick source. + // + if(ui32Config & AUX_TIMER_T1CFG_MODE) + { + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); + ui32Val &= ~(AUX_TIMER_T1CFG_TICK_SRC_POL_M | + AUX_TIMER_T1CFG_TICK_SRC_M); + + // + // Set edge polarity. + // + if(ui32Config & AUX_TIMER_CFG_FALLING_EDGE) + { + ui32Val |= AUX_TIMER_T1CFG_TICK_SRC_POL; + } + + // + // Set tick source. + // + ui32Val |= ((ui32Config & 0x00000F00) >> 8) << + AUX_TIMER_T1CFG_TICK_SRC_S; + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; + } + } +} +//***************************************************************************** +// +//! Start AUX timer +// +//***************************************************************************** +void +AUXTimerStart(uint32_t ui32Timer) +{ + // + // Check the arguments. + // + ASSERT((ui32Timer == AUX_TIMER_0) || + (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + + if(ui32Timer & AUX_TIMER_0) + { + // + // Start timer 0. + // + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = AUX_TIMER_T0CTL_EN; + } + if(ui32Timer & AUX_TIMER_1) + { + // + // Start timer 1. + // + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = AUX_TIMER_T1CTL_EN; + } +} +//***************************************************************************** +// +//! Stop AUX timer +// +//***************************************************************************** +void +AUXTimerStop(uint32_t ui32Timer) +{ + // + // Check the arguments. + // + ASSERT((ui32Timer == AUX_TIMER_0) || + (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + + if(ui32Timer & AUX_TIMER_0) + { + // + // Stop timer 0. + // + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = 0; + } + if(ui32Timer & AUX_TIMER_1) + { + // + // Stop timer 1. + // + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = 0; + } +} +//***************************************************************************** +// +//! Set AUX timer prescale value +// +//***************************************************************************** +void +AUXTimerPrescaleSet(uint32_t ui32Timer, uint32_t ui32PrescaleDiv) +{ + uint32_t ui32Val; + + // + // Check the arguments. + // + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1) || + (ui32Timer == AUX_TIMER_BOTH)); + ASSERT(ui32PrescaleDiv <= AUX_TIMER_PRESCALE_DIV_32768); + + if(ui32Timer & AUX_TIMER_0) + { + // + // Set timer 0 prescale value. + // + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); + ui32Val &= ~AUX_TIMER_T0CFG_PRE_M; + ui32Val |= ui32PrescaleDiv << AUX_TIMER_T0CFG_PRE_S; + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; + } + if(ui32Timer & AUX_TIMER_1) + { + // + // Set timer 1 prescale value. + // + ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); + ui32Val &= ~AUX_TIMER_T1CFG_PRE_M; + ui32Val |= ui32PrescaleDiv << AUX_TIMER_T1CFG_PRE_S; + HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; + } +} +//***************************************************************************** +// +//! Get AUX timer prescale value +// +//***************************************************************************** +uint32_t +AUXTimerPrescaleGet(uint32_t ui32Timer) +{ + uint32_t ui32Val; + uint32_t ui32PrescaleDiv; + + // + // Check the arguments. + // + ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); + + ui32Val = (HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG)); + if(ui32Timer & AUX_TIMER_0) + { + // + // Get timer 0 prescale value. + // + ui32PrescaleDiv = + (ui32Val & AUX_TIMER_T0CFG_PRE_M) >> AUX_TIMER_T0CFG_PRE_S; + } + else + { + // + // Get timer 1 prescale value. + // + ui32PrescaleDiv = + (ui32Val & AUX_TIMER_T1CFG_PRE_M) >> AUX_TIMER_T1CFG_PRE_S; + } + + return(ui32PrescaleDiv); +} +//! @} +//! \\addtogroup aux_wuc_api +//! @{ +//**************************************************************************** +// +//! Enable clocks for peripherals in the AUX domain +// +//**************************************************************************** +void +AUXWUCClockEnable(uint32_t ui32Clocks) +{ + // + // Check the arguments. + // + ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || + (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || + (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || + (ui32Clocks & AUX_WUC_SOC_CLOCK) || + (ui32Clocks & AUX_WUC_TIMER_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || + (ui32Clocks & AUX_WUC_SMPH_CLOCK) || + (ui32Clocks & AUX_WUC_TDC_CLOCK) || + (ui32Clocks & AUX_WUC_ADC_CLOCK) || + (ui32Clocks & AUX_WUC_REF_CLOCK)); + + // + // Enable some of the clocks in the clock register. + // + HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) |= (ui32Clocks & + AUX_WUC_MODCLK_MASK); + + // + // Check the rest. + // + if(ui32Clocks & AUX_WUC_ADC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = + AUX_WUC_ADCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_TDC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) = + AUX_WUC_TDCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_REF_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = + AUX_WUC_REFCLKCTL_REQ; + } +} +//**************************************************************************** +// +//! Disable clocks for peripherals in the AUX domain +// +//**************************************************************************** +void +AUXWUCClockDisable(uint32_t ui32Clocks) +{ + // + // Check the arguments. + // + ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || + (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || + (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || + (ui32Clocks & AUX_WUC_SOC_CLOCK) || + (ui32Clocks & AUX_WUC_TIMER_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || + (ui32Clocks & AUX_WUC_SMPH_CLOCK) || + (ui32Clocks & AUX_WUC_TDC_CLOCK) || + (ui32Clocks & AUX_WUC_ADC_CLOCK) || + (ui32Clocks & AUX_WUC_REF_CLOCK)); + + // + // Disable some of the clocks in the clock register. + // + HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) &= ~(ui32Clocks & + AUX_WUC_MODCLK_MASK); + + // + // Check the rest. + // + if(ui32Clocks & AUX_WUC_ADC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) &= + ~AUX_WUC_ADCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_TDC_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) &= + ~AUX_WUC_TDCCLKCTL_REQ; + } + if(ui32Clocks & AUX_WUC_REF_CLOCK) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) &= + ~AUX_WUC_REFCLKCTL_REQ; + } +} +//**************************************************************************** +// +//! Get the status of a clock +// +//**************************************************************************** +uint32_t +AUXWUCClockStatus(uint32_t ui32Clocks) +{ + bool bClockStatus; + uint32_t ui32ClockRegister; + + // + // Check the arguments. + // + ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || + (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || + (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || + (ui32Clocks & AUX_WUC_SOC_CLOCK) || + (ui32Clocks & AUX_WUC_TIMER_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || + (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || + (ui32Clocks & AUX_WUC_SMPH_CLOCK) || + (ui32Clocks & AUX_WUC_TDC_CLOCK) || + (ui32Clocks & AUX_WUC_ADC_CLOCK) || + (ui32Clocks & AUX_WUC_REF_CLOCK)); + + bClockStatus = true; + + // + // Read the status registers. + // + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0); + + // + // Check all requested clocks + // + if(ui32Clocks & AUX_WUC_ADI_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AUX_ADI ? + true : false); + } + if(ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_OSCCTL ? + true : false); + } + if(ui32Clocks & AUX_WUC_TDCIF_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_TDC ? + true : false); + } + if(ui32Clocks & AUX_WUC_SOC_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_SOC ? + true : false); + } + if(ui32Clocks & AUX_WUC_TIMER_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_TIMER ? + true : false); + } + if(ui32Clocks & AUX_WUC_AIODIO0_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AIODIO0 ? + true : false); + } + if(ui32Clocks & AUX_WUC_AIODIO1_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_AIODIO1 ? + true : false); + } + if(ui32Clocks & AUX_WUC_SMPH_CLOCK) + { + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_MODCLKEN0_SMPH ? + true : false); + } + if(ui32Clocks & AUX_WUC_ADC_CLOCK) + { + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL); + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_ADCCLKCTL_ACK ? + true : false); + } + if(ui32Clocks & AUX_WUC_TDC_CLOCK) + { + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL); + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_TDCCLKCTL_ACK ? + true : false); + } + if(ui32Clocks & AUX_WUC_REF_CLOCK) + { + ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL); + bClockStatus = bClockStatus && (ui32ClockRegister & + AUX_WUC_REFCLKCTL_ACK ? + true : false); + } + + // + // Return the clock status. + // + return bClockStatus ? AUX_WUC_CLOCK_READY : AUX_WUC_CLOCK_OFF; +} +//**************************************************************************** +// +//! Control the power to the AUX domain +// +//**************************************************************************** +void +AUXWUCPowerCtrl(uint32_t ui32PowerMode) +{ + // + // Check the arguments. + // + ASSERT((ui32PowerMode == AUX_WUC_POWER_OFF) || + (ui32PowerMode == AUX_WUC_POWER_DOWN) || + (ui32PowerMode == AUX_WUC_POWER_ACTIVE)); + + // + // Power on/off. + // + if(ui32PowerMode == AUX_WUC_POWER_OFF) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWROFFREQ) = AUX_WUC_PWROFFREQ_REQ; + HWREG(AUX_WUC_BASE + AUX_WUC_O_MCUBUSCTL) = AUX_WUC_MCUBUSCTL_DISCONNECT_REQ; + return; + } + else + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWROFFREQ) = 0x0; + } + + // + // Power down/active. + // + if(ui32PowerMode == AUX_WUC_POWER_DOWN) + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWRDWNREQ) = + AUX_WUC_PWRDWNREQ_REQ; + HWREG(AUX_WUC_BASE + AUX_WUC_O_MCUBUSCTL) = AUX_WUC_MCUBUSCTL_DISCONNECT_REQ; + } + else + { + HWREG(AUX_WUC_BASE + AUX_WUC_O_PWRDWNREQ) = 0x0; + } +} +//! @} +//! \\addtogroup ddi_api +//! @{ +//***************************************************************************** +// +//! Write a single bit using a 16-bit maskable write +// +//***************************************************************************** +void +DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32WrData) +{ + uint32_t ui32RegAddr; + uint32_t ui32Data; + + // + // Check the arguments. + // + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(!((ui32Mask & 0xFFFF0000) ^ (ui32Mask & 0x0000FFFF))); + ASSERT(!(ui32WrData & 0xFFFF0000)); + + // + // DDI 16-bit target is on 32-bit boundary so double offset + // + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // + // Adjust for target bit in high half of the word. + // + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 4; + ui32Mask >>= 16; + } + + // + // Write mask if data is not zero (to set mask bit), else write '0'. + // + ui32Data = ui32WrData ? ui32Mask : 0x0; + + // + // Update the register. + // + HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32Data; +} +//***************************************************************************** +// +//! Write a bitfield via the DDI using 16-bit maskable write +// +//***************************************************************************** +void +DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift, + uint16_t ui32Data) +{ + uint32_t ui32RegAddr; + uint32_t ui32WrData; + + // + // Check the arguments. + // + ASSERT(DDIBaseValid(ui32Base)); + + // + // 16-bit target is on 32-bit boundary so double offset. + // + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // + // Adjust for target bit in high half of the word. + // + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 4; + ui32Mask = ui32Mask >> 16; + } + + // + // Shift data in to position. + // + ui32WrData = ui32Data << ui32Shift; + + // + // Write data. + // + HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32WrData; +} +//***************************************************************************** +// +//! Read a bit via the DDI using 16-bit READ. +// +//***************************************************************************** +uint16_t +DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask) +{ + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // + // Check the arguments. + // + ASSERT(DDIBaseValid(ui32Base)); + + // + // Calculate the address of the register. + // + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // + // Adjust for target bit in high half of the word. + // + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // + // Read a halfword on the DDI interface. + // + ui16Data = HWREGH(ui32RegAddr); + + // + // Mask data. + // + ui16Data = ui16Data & ui32Mask; + + // + // Return masked data. + // + return(ui16Data); +} +//***************************************************************************** +// +//! Read a bitfield via the DDI using 16-bit read. +// +//***************************************************************************** +uint16_t +DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift) +{ + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // + // Check the arguments. + // + ASSERT(DDIBaseValid(ui32Base)); + + // + // Calculate the register address. + // + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // + // Adjust for target bit in high half of the word. + // + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // + // Read the register. + // + ui16Data = HWREGH(ui32RegAddr); + + // + // Mask data and shift into place. + // + ui16Data &= ui32Mask; + ui16Data >>= ui32Shift; + + // + // Return data. + // + return(ui16Data); +} +//! @} +//! \\addtogroup flash_api +//! @{ +//***************************************************************************** +// +// Default values for security control in customer configuration area in flash +// top sector. TBD! It must be asured that layout corresponds with CCFG. +// +//***************************************************************************** +const uint8_t g_pui8CcfgDefaultSec[] = {0xFF, 0xFF, 0xFF, 0xC5, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xC5, 0xFF, 0xFF, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF + }; + +//***************************************************************************** +// +// Function prototypes for static functions +// +//***************************************************************************** +static void IssueFsmCommand(tFlashStateCommandsType eCommand); +static void EnableSectorsForWrite(void); +static uint32_t ScaleCycleValues(uint32_t ui32SpecifiedTiming, + uint32_t ui32ScaleValue); +static void SetWriteMode(void); +static void SetReadMode(void); +static void TrimForWrite(void); +//***************************************************************************** +// +//! \internal +//! Issues a command to the Flash State Machine. +//! +//! \param eCommand specifies the FSM command. +//! +//! Issues a command to the Flash State Machine. +//! +//! \return None +// +//***************************************************************************** +static void +IssueFsmCommand(tFlashStateCommandsType eCommand) +{ + // + // Check the arguments. + // + ASSERT( + eCommand == FAPI_ERASE_SECTOR || eCommand == FAPI_ERASE_BANK || + eCommand == FAPI_VALIDATE_SECTOR || eCommand == FAPI_CLEAR_STATUS || + eCommand == FAPI_PROGRAM_RESUME || eCommand == FAPI_ERASE_RESUME || + eCommand == FAPI_CLEAR_MORE || eCommand == FAPI_PROGRAM_SECTOR || + eCommand == FAPI_PROGRAM_DATA || eCommand == FAPI_ERASE_OTP); + + // + // Enable write to FSM register. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + // + // Issue FSM command. + // + HWREG(FLASH_BASE + FLASH_O_FSM_CMD) = eCommand; + + // + // Start command execute. + // + HWREG(FLASH_BASE + FLASH_O_FSM_EXECUTE) = FLASH_CMD_EXEC; + + // + // Disable write to FSM register. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \internal +//! Enables all sectors for erase and programming on the active bank. +//! +//! This function disables the idle reading power reduction mode, selects the +//! flash bank and enables all sectors for erase and programming on the active +//! bank. +//! Sectores may be protected from programming depending on the value of the +//! FLASH_O_FSM_BSLPx registers. +//! Sectores may be protected from erase depending on the value of the +//! FLASH_O_FSM_BSLEx registers. Additional sector erase protection is set by +//! the FLASH_O_FSM_SECTOR1 register. +//! +//! \return None +// +//***************************************************************************** +static void +EnableSectorsForWrite(void) +{ + // + // Trim flash module for program/erase operation. + // + TrimForWrite(); + + // + // Configure flash to write mode + // + SetWriteMode(); + + // + // Select flash bank. + // + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + + // + // Disable Level 1 Protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + // + // Enable all sectors for erase and programming. + // + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0xFFFF; + + // + // Enable Level 1 Protection + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; +} + +//***************************************************************************** +// +//! \internal +//! Trims the Flash Bank and Flash Pump for program/erase functionality +//! +//! This trimming will make it possible to perform erase and program operations +//! of the flash. Trim values are loaded from factory configuration area +//! (referred to as FCGF1). The trimming done by this function is valid until +//! reset of the flash module. +//! +//! Some registers shall be written with a value that is a number of FCLK +//! cycles. The trim values controlling these registers have a value of +//! number of half us. FCLK = SysClk / ((RWAIT+1) x 2). +//! In order to calculate the register value for these registers the +//! following calculation must be done: +//! +//! OtpValue SysClkMHz +//! -------- us OtpValue x --------- +//! 2 (RWAIT+1) +//! RegValue_in_no_of_clk_cycles = ----------------- = --------------------- +//! 1 4 +//! -------------- +//! SysClkMHz +//! ------------ +//! (RWAIT+1)x 2 +//! +//! This is equevivalent to: +//! +//! 16 x SysClkMHz +//! OtpValue x --------------- +//! (RWAIT+1) +//! RegValue_in_no_of_clk_cycles = ---------------------------- +//! 64 +//! +//! 16 x SysClkMHz +//! A scaling factor is set equal to: ui32FclkScale = -------------- +//! (RWAIT+1) +//! +//! which gives: +//! OtpValue x ui32FclkScale +//! RegValue_in_no_of_clk_cycles = ------------------------ +//! 64 +//! +//! \return None. +// +//***************************************************************************** +static void +TrimForWrite(void) +{ + uint32_t ui32Value; + uint32_t ui32TempVal; + uint32_t ui32FclkScale; + uint32_t ui32RWait; + + // + // Return if flash is already trimmed for program/erase operations. + // + if(HWREG(FLASH_BASE + FLASH_O_FWFLAG) & FW_WRT_TRIMMED) + { + return; + } + + //***********************************************************************// + // // + // Configure the FSM registers // + // // + //***********************************************************************// + + // + // Enable access to the FSM registers. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + // + // Determine the scaling value to be used on timing related trim values. + // The scaling value is based on the flash module clock frequency and RWAIT + // + ui32RWait = (HWREG(FLASH_BASE + FLASH_O_FRDCTL) & + FLASH_FRDCTL_RWAIT_M) >> FLASH_FRDCTL_RWAIT_S; + ui32FclkScale = (16 * FLASH_MODULE_CLK_FREQ) / (ui32RWait + 1); + + // + // Configure Program puls width bits 15:0. + // (FCFG1 offset 0x188 bits 15:0). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_PROG_EP) & + FACTORY_CFG_FLASH_PROG_EP_PROGRAM_PW_M) >> + FACTORY_CFG_FLASH_PROG_EP_PROGRAM_PW_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) & + ~FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M) | + ((ui32Value << FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S) & + FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M); + + // + // Configure Erase puls width bits 31:0. + // (FCFG1 offset 0x18C bits 31:0). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_ERA_PW) & + FACTORY_CFG_FLASH_ERA_PW_ERASE_PW_M) >> + FACTORY_CFG_FLASH_ERA_PW_ERASE_PW_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) & + ~FLASH_FSM_ERA_PW_FSM_ERA_PW_M) | + ((ui32Value << FLASH_FSM_ERA_PW_FSM_ERA_PW_S) & + FLASH_FSM_ERA_PW_FSM_ERA_PW_M); + + + // + // Configure no of flash clock cycles from EXECUTEZ going low to the + // verify data can be read in the program verify mode bits 7:0. + // (FCFG1 offset 0x174 bits 23:16). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_C_E_P_R) & + FACTORY_CFG_FLASH_C_E_P_R_PV_ACCESS_M) >> + FACTORY_CFG_FLASH_C_E_P_R_PV_ACCESS_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & + ~FLASH_FSM_EX_VAL_EXE_VALD_M) | + ((ui32Value << FLASH_FSM_EX_VAL_EXE_VALD_S) & + FLASH_FSM_EX_VAL_EXE_VALD_M); + + // + // Configure the number of flash clocks from the start of the Read mode at + // the end of the operations until the FSM clears the BUSY bit in FMSTAT. + // (FCFG1 offset 0x178 bits 23:16). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_P_R_PV) & + FACTORY_CFG_FLASH_P_R_PV_RH_M) >> + FACTORY_CFG_FLASH_P_R_PV_RH_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) = + (HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) & + ~FLASH_FSM_RD_H_RD_H_M) | + ((ui32Value << FLASH_FSM_RD_H_RD_H_S) & + FLASH_FSM_RD_H_RD_H_M); + + // + // Configure Program hold time + // (FCFG1 offset 0x178 bits 31:24). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_P_R_PV) & + FACTORY_CFG_FLASH_P_R_PV_PH_M) >> + FACTORY_CFG_FLASH_P_R_PV_PH_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) & + ~FLASH_FSM_P_OH_PGM_OH_M) | + ((ui32Value << FLASH_FSM_P_OH_PGM_OH_S) & + FLASH_FSM_P_OH_PGM_OH_M); + + // + // Configure Erase hold time + // (FCFG1 offset 0x17C bits 31:24). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_EH_SEQ) & + FACTORY_CFG_FLASH_EH_SEQ_EH_M) >> + FACTORY_CFG_FLASH_EH_SEQ_EH_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) & + ~FLASH_FSM_ERA_OH_ERA_OH_M) | + ((ui32Value << FLASH_FSM_ERA_OH_ERA_OH_S) & + FLASH_FSM_ERA_OH_ERA_OH_M); + + // + // Configure Program verify row switch time + // (FCFG1 offset0x178 bits 15:8). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_P_R_PV) & + FACTORY_CFG_FLASH_P_R_PV_PVH_M) >> + FACTORY_CFG_FLASH_P_R_PV_PVH_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) & + ~FLASH_FSM_PE_VH_PGM_VH_M) | + ((ui32Value << FLASH_FSM_PE_VH_PGM_VH_S) & + FLASH_FSM_PE_VH_PGM_VH_M); + + // + // Configure Program Operation Setup time + // (FCFG1 offset 0x170 bits 31:24). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_E_P) & + FACTORY_CFG_FLASH_E_P_PSU_M) >> + FACTORY_CFG_FLASH_E_P_PSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & + ~FLASH_FSM_PE_OSU_PGM_OSU_M) | + ((ui32Value << FLASH_FSM_PE_OSU_PGM_OSU_S) & + FLASH_FSM_PE_OSU_PGM_OSU_M); + + // + // Configure Erase Operation Setup time + // (FCGF1 offset 0x170 bits 23:16). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_E_P) & + FACTORY_CFG_FLASH_E_P_ESU_M) >> + FACTORY_CFG_FLASH_E_P_ESU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & + ~FLASH_FSM_PE_OSU_ERA_OSU_M) | + ((ui32Value << FLASH_FSM_PE_OSU_ERA_OSU_S) & + FLASH_FSM_PE_OSU_ERA_OSU_M); + + // + // Confgure Program Verify Setup time + // (FCFG1 offset 0x170 bits 15:8). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_E_P) & + FACTORY_CFG_FLASH_E_P_PVSU_M) >> + FACTORY_CFG_FLASH_E_P_PVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & + ~FLASH_FSM_PE_VSU_PGM_VSU_M) | + ((ui32Value << FLASH_FSM_PE_VSU_PGM_VSU_S) & + FLASH_FSM_PE_VSU_PGM_VSU_M); + + // + // Configure Erase Verify Setup time + // (FCFG1 offset 0x170 bits 7:0). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_E_P) & + FACTORY_CFG_FLASH_E_P_EVSU_M) >> + FACTORY_CFG_FLASH_E_P_EVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & + ~FLASH_FSM_PE_VSU_ERA_VSU_M) | + ((ui32Value << FLASH_FSM_PE_VSU_ERA_VSU_S) & + FLASH_FSM_PE_VSU_ERA_VSU_M); + + // + // Configure Addr to EXECUTEZ low setup time + // (FCFG1 offset 0x174 bits 15:12). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_C_E_P_R) & + FACTORY_CFG_FLASH_C_E_P_R_A_EXEZ_SETUP_M) >> + FACTORY_CFG_FLASH_C_E_P_R_A_EXEZ_SETUP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) & + ~FLASH_FSM_CMP_VSU_ADD_EXZ_M) | + ((ui32Value << FLASH_FSM_CMP_VSU_ADD_EXZ_S) & + FLASH_FSM_CMP_VSU_ADD_EXZ_M); + + // + // Configure Voltage Status Count + // (FCFG1 offset 0x17C bits 15:12). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_EH_SEQ) & + FACTORY_CFG_FLASH_EH_SEQ_VSTAT_M) >> + FACTORY_CFG_FLASH_EH_SEQ_VSTAT_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) = + (HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) & + ~FLASH_FSM_VSTAT_VSTAT_CNT_M) | + ((ui32Value << FLASH_FSM_VSTAT_VSTAT_CNT_S) & + FLASH_FSM_VSTAT_VSTAT_CNT_M); + + // + // Configure Repeat Verify action setup + // (FCFG1 offset 0x174 bits 31:24). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_C_E_P_R) & + FACTORY_CFG_FLASH_C_E_P_R_RVSU_M) >> + FACTORY_CFG_FLASH_C_E_P_R_RVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & + ~FLASH_FSM_EX_VAL_REP_VSU_M) | + ((ui32Value << FLASH_FSM_EX_VAL_REP_VSU_S) & + FLASH_FSM_EX_VAL_REP_VSU_M); + + // + // Configure Maximum Programming Pulses + // (FCFG1 offset 0x184 bits 15:0). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_PP) & + FACTORY_CFG_FLASH_PP_MAX_PP_M) >> + FACTORY_CFG_FLASH_PP_MAX_PP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & + ~FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M) | + ((ui32Value << FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S) & + FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M); + + // + // Configure Beginning level for VHVCT used during erase modes + // (FCFG1 offset 0x180 bits 31:16). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV_E) & + FACTORY_CFG_FLASH_VHV_E_VHV_E_START_M) >> + FACTORY_CFG_FLASH_VHV_E_VHV_E_START_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & + ~FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M) | + ((ui32Value << FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S) & + FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M); + + // + // Configure Maximum EC Level + // (FCFG1 offset 0x2B0 bits 21:18). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA3) & + FACTORY_CFG_FLASH_OTP_DATA3_MAX_EC_LEVEL_M) >> + FACTORY_CFG_FLASH_OTP_DATA3_MAX_EC_LEVEL_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & + ~FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M) | + ((ui32Value << FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S) & + FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M); + + // + // Configure Maximum Erase Pulses + // (FCFG1 offset 0x188 bits 31:16). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_PROG_EP) & + FACTORY_CFG_FLASH_PROG_EP_MAX_EP_M) >> + FACTORY_CFG_FLASH_PROG_EP_MAX_EP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & + ~FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M) | + ((ui32Value << FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S) & + FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M); + + // + // Configure the VHVCT Step Size. This is the number of erase pulses that + // must be completed for each level before the FSM increments the + // CUR_EC_LEVEL to the next higher level. Actual erase pulses per level + // equals (EC_STEP_SIZE +1). The stepping is only needed for the VHVCT + // voltage. + // (FCFG1 offset 0x2B0 bits 31:23). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA3) & + FACTORY_CFG_FLASH_OTP_DATA3_EC_STEP_SIZE_M) >> + FACTORY_CFG_FLASH_OTP_DATA3_EC_STEP_SIZE_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) = + (HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) & + ~FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M) | + ((ui32Value << FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S) & + FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M); + + // + // Configure the hight of each EC step. This is the number of counts that + // the CUR_EC_LEVEL will increment when going to a new level. Actual count + // size equals (EC_STEP_HEIGHT + 1). The stepping applies only to the VHVCT + // voltage. + // The read trim value is decremented by 1 before written to the register + // since actual counts equals (register value + 1). + // (FCFG1 offset 0x180 bits 15:0). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV_E) & + FACTORY_CFG_FLASH_VHV_E_VHV_E_STEP_HIGHT_M) >> + FACTORY_CFG_FLASH_VHV_E_VHV_E_STEP_HIGHT_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_EC_STEP_HEIGHT) = ((ui32Value - 1) & + FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M); + + // + // Configure Precondition used in erase operations + // (FCFG1 offset 0x2B0 bit 22). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA3) & + FACTORY_CFG_FLASH_OTP_DATA3_DO_PRECOND_M) >> + FACTORY_CFG_FLASH_OTP_DATA3_DO_PRECOND_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) & + ~FLASH_FSM_ST_MACHINE_DO_PRECOND_M) | + ((ui32Value << FLASH_FSM_ST_MACHINE_DO_PRECOND_S) & + FLASH_FSM_ST_MACHINE_DO_PRECOND_M); + + // + // Enable the recommended Good Time function. + // + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD; + + // + // Disable write access to FSM registers. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + + //***********************************************************************// + // // + // Configure the voltage registers // + // // + //***********************************************************************// + + // + // Unlock voltage registers (0x2080 - 0x2098). + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + + // + // Configure voltage level for the specified pump voltage of high + // voltage supply input during erase operation VHVCT_E and the TRIM13_E + // (FCFG1 offset 0x190 bits[3:0] and bits[11:8]). + // + ui32TempVal = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV); + + ui32Value = ((ui32TempVal & FACTORY_CFG_FLASH_VHV_TRIM13_E_M)>> + FACTORY_CFG_FLASH_VHV_TRIM13_E_S) << FLASH_FVHVCT1_TRIM13_E_S; + ui32Value |= ((ui32TempVal & FACTORY_CFG_FLASH_VHV_VHV_E_M)>> + FACTORY_CFG_FLASH_VHV_VHV_E_S) << FLASH_FVHVCT1_VHVCT_E_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & + ~(FLASH_FVHVCT1_TRIM13_E_M | FLASH_FVHVCT1_VHVCT_E_M)) | ui32Value; + + // + // Configure voltage level for the specified pump voltage of high voltage + // supply input during program verify operation VHVCT_PV and the TRIM13_PV + // (OTP offset 0x194 bits[19:16] and bits[27:24]). + // + ui32TempVal = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV_PV); + + ui32Value = ((ui32TempVal & FACTORY_CFG_FLASH_VHV_PV_TRIM13_PV_M)>> + FACTORY_CFG_FLASH_VHV_PV_TRIM13_PV_S) << + FLASH_FVHVCT1_TRIM13_PV_S; + ui32Value |= ((ui32TempVal & FACTORY_CFG_FLASH_VHV_PV_VHV_PV_M)>> + FACTORY_CFG_FLASH_VHV_PV_VHV_PV_S) << + FLASH_FVHVCT1_VHVCT_PV_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & + ~(FLASH_FVHVCT1_TRIM13_PV_M | FLASH_FVHVCT1_VHVCT_PV_M)) | ui32Value; + + // + // Configure voltage level for the specified pump voltage of high voltage + // supply input during program operation VHVCT_P and TRIM13_P + // (FCFG1 offset 0x190 bits[19:16] and bits[27:24]). + // + ui32TempVal = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV); + + ui32Value = ((ui32TempVal & FACTORY_CFG_FLASH_VHV_TRIM13_P_M)>> + FACTORY_CFG_FLASH_VHV_TRIM13_P_S) << FLASH_FVHVCT2_TRIM13_P_S; + ui32Value |= ((ui32TempVal & FACTORY_CFG_FLASH_VHV_VHV_P_M)>> + FACTORY_CFG_FLASH_VHV_VHV_P_S) << FLASH_FVHVCT2_VHVCT_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT2) = + (HWREG(FLASH_BASE + FLASH_O_FVHVCT2) & + ~(FLASH_FVHVCT2_TRIM13_P_M | FLASH_FVHVCT2_VHVCT_P_M)) | ui32Value; + + // + // Configure voltage level for the specified pump voltage of wordline power + // supply for read mode + // (FCFG1 offset 0x198 Bits 15:8). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_V) & + FACTORY_CFG_FLASH_V_V_READ_M) >> + FACTORY_CFG_FLASH_V_V_READ_S; + + HWREG(FLASH_BASE + FLASH_O_FVREADCT) = + (HWREG(FLASH_BASE + FLASH_O_FVREADCT) & + ~FLASH_FVREADCT_VREADCT_M) | + ((ui32Value << FLASH_FVREADCT_VREADCT_S) & + FLASH_FVREADCT_VREADCT_M); + + // + // Configure the voltage level for the VCG 2.5 CT pump voltage + // (FCFG1 offset 0x194 bits 15:8). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV_PV) & + FACTORY_CFG_FLASH_VHV_PV_VCG2P5_M) >> + FACTORY_CFG_FLASH_VHV_PV_VCG2P5_S; + + HWREG(FLASH_BASE + FLASH_O_FVNVCT) = + (HWREG(FLASH_BASE + FLASH_O_FVNVCT) & + ~FLASH_FVNVCT_VCG2P5CT_M) | + ((ui32Value << FLASH_FVNVCT_VCG2P5CT_S) & + FLASH_FVNVCT_VCG2P5CT_M); + + // + // Configure the voltage level for the specified pump voltage of high + // current power input during program operation + // (FCFG1 offset 0x198 bits 31:24). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_V) & + FACTORY_CFG_FLASH_V_VSL_P_M) >> + FACTORY_CFG_FLASH_V_VSL_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVSLP) = + (HWREG(FLASH_BASE + FLASH_O_FVSLP) & + ~FLASH_FVSLP_VSL_P_M) | + ((ui32Value << FLASH_FVSLP_VSL_P_S) & + FLASH_FVSLP_VSL_P_M); + + // + // Configure the voltage level for the specified pump voltage of wordline + // power supply during programming operations + // (OTP offset 0x198 bits 23:16). + // + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_V) & + FACTORY_CFG_FLASH_V_VWL_P_M) >> + FACTORY_CFG_FLASH_V_VWL_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVWLCT) = + (HWREG(FLASH_BASE + FLASH_O_FVWLCT) & + ~FLASH_FVWLCT_VWLCT_P_M) | + ((ui32Value << FLASH_FVWLCT_VWLCT_P_S) & + FLASH_FVWLCT_VWLCT_P_M); + + // + // Configure the pump's TRIM_1P7 port pins. + // (FCFG1 offset 0x2B0 bits 17:16). + // + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA3) & + FACTORY_CFG_FLASH_OTP_DATA3_TRIM_1P7_M) >> + FACTORY_CFG_FLASH_OTP_DATA3_TRIM_1P7_S; + + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~FLASH_FSEQPMP_TRIM_1P7_M) | + ((ui32Value << FLASH_FSEQPMP_TRIM_1P7_S) & + FLASH_FSEQPMP_TRIM_1P7_M); + + // + // Lock the voltage registers. + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // + // Set trimmed flag. + // + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; + HWREG(FLASH_BASE + FLASH_O_FWFLAG) |= FW_WRT_TRIMMED; + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; +} + +//***************************************************************************** +// +//! \internal +//! Used to scale the TI OTP values based on the FClk scaling value. +//! +//! \param ui32SpecifiedTiming +//! \param ui32ScaleValue +//! +//! Used to scale the TI OTP values based on the FClk scaling value. +//! +//! \return Returns the scaled value +// +//***************************************************************************** +static uint32_t +ScaleCycleValues(uint32_t ui32SpecifiedTiming, uint32_t ui32ScaleValue) +{ + return((ui32SpecifiedTiming * ui32ScaleValue) >> 6); +} + +//***************************************************************************** +// +//! \internal +//! Used to set flash in read mode. +//! +//! Flash is configured with values loaded from OTP dependent on the current +//! regulator mode. +//! +//! \return None. +// +//***************************************************************************** +static void +SetReadMode(void) +{ + uint32_t ui32TrimValue; + uint32_t ui32Value; + + // + // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + // VIN_AT_X and VIN_BY_PASS for read mode + // + if(HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL) & + AON_SYSCTL_PWRCTL_EXT_REG_MODE) + { + // Select trim values for external regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 4). + // Configure DIS_IDLE (OTP offset 0x308 bit 3). + ui32Value |= ((ui32TrimValue & + (FACTORY_CFG_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M | + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >> + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // + // Wait for disabled sample and hold functionality to be stable. + // + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 2:0) + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } + else + { + // Select trim values for internal regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 12). + // Configure DIS_IDLE (OTP offset 0x308 bit 11). + ui32Value |= ((ui32TrimValue & + (FACTORY_CFG_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M | + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >> + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // + // Wait for disabled sample and hold functionality to be stable. + // + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 10:8) + ui32Value = (((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S); + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} + +//***************************************************************************** +// +//! \internal +//! Used to set flash in write mode. +//! +//! Flash is configured with values loaded from OTP dependent on the current +//! regulator mode. +//! +//! \return None. +// +//***************************************************************************** +static void +SetWriteMode(void) +{ + uint32_t ui32TrimValue; + uint32_t ui32Value; + + // + // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + // VIN_AT_X and VIN_BY_PASS for program/erase mode + // + if(HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL) & + AON_SYSCTL_PWRCTL_EXT_REG_MODE) + { + // Select trim values for external regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 23) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 22:21) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 20). + // Configure DIS_IDLE (OTP offset 0x308 bit 19). + ui32Value |= ((ui32TrimValue & + (FACTORY_CFG_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M | + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M)) >> + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // + // Wait for disabled sample and hold functionality to be stable. + // + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 18:16) + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } + else + { + // Select trim values for internal regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 31) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 30:29) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 28). + // Configure DIS_IDLE (OTP offset 0x308 bit 27). + ui32Value |= ((ui32TrimValue & + (FACTORY_CFG_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M | + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M)) >> + FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S) << + FLASH_CFG_DIS_IDLE_S; + + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | + FLASH_CFG_DIS_IDLE_M)) | ui32Value; + + // Check if sample and hold functionality is disabled. + if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) + { + // + // Wait for disabled sample and hold functionality to be stable. + // + while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + { + } + } + + // Configure VIN_AT_X (OTP offset 0x308 bits 26:24) + ui32Value = ((ui32TrimValue & + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M) >> + FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} +//***************************************************************************** +// +//! Set power mode +// +//***************************************************************************** +void +FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriode, + uint32_t ui32PumpGracePeriode) +{ + // + // Check the arguments. + // + ASSERT(ui32PowerMode == FLASH_PWR_ACTIVE_MODE || + ui32PowerMode == FLASH_PWR_OFF_MODE || + ui32PowerMode == FLASH_PWR_DEEP_STDBY_MODE); + ASSERT(ui32BankGracePeriode <= 0xFF); + ASSERT(ui32PumpGracePeriode <= 0xFFFF); + + switch(ui32PowerMode) + { + case FLASH_PWR_ACTIVE_MODE: + // + // Set bank power mode to ACTIVE. + // + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= + (~FLASH_FBFALLBACK_BANKPWR0_M | FBFALLBACK_ACTIVE); + + // + // Set charge pump power mode to ACTIVE mode. + // + HWREG(FLASH_BASE + FLASH_O_FPAC1) |= 1 << FLASH_FPAC1_PUMPPWR_S; + break; + + case FLASH_PWR_OFF_MODE: + // + // Set bank grace periode. + // + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriode << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // + // Set pump grace periode. + // + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriode << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // + // Set bank power mode to SLEEP. + // + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= + (~FLASH_FBFALLBACK_BANKPWR0_M | FBFALLBACK_SLEEP); + + // + // Set charge pump power mode to SLEEP mode. + // + HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M; + break; + + case FLASH_PWR_DEEP_STDBY_MODE: + // + // Set bank grace periode. + // + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriode << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // + // Set pump grace periode. + // + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriode << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // + // Set bank power mode to DEEP STANDBY mode. + // + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= + (~FLASH_FBFALLBACK_BANKPWR0_M | FBFALLBACK_DEEP_STDBY); + + // + // Set charge pump power mode to SLEEP mode. + // + HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M; + break; + } +} +//***************************************************************************** +// +//! Get current configured power mode +// +//***************************************************************************** +uint32_t +FlashPowerModeGet(void) +{ + uint32_t ui32PowerMode; + uint32_t ui32BankPwrMode; + + ui32BankPwrMode = HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + FLASH_FBFALLBACK_BANKPWR0_M; + + if(ui32BankPwrMode == FBFALLBACK_SLEEP) + { + ui32PowerMode = FLASH_PWR_OFF_MODE; + } + else if(ui32BankPwrMode == FBFALLBACK_DEEP_STDBY) + { + ui32PowerMode = FLASH_PWR_DEEP_STDBY_MODE; + } + else + { + ui32PowerMode = FLASH_PWR_ACTIVE_MODE; + } + + // + // Return power mode. + // + return(ui32PowerMode); +} +//***************************************************************************** +// +//! Set sector protection +// +//***************************************************************************** +void +FlashProtectionSet(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode) +{ + uint32_t ui32SectorNumber; + + // + // Check the arguments. + // + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(ui32ProtectMode == FLASH_WRITE_PROTECT) + { + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / + FlashSectorSizeGet(); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + if(ui32SectorNumber <= 31) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber); + } + else if(ui32SectorNumber <= 63) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |= + (1 << (ui32SectorNumber & 0x1F)); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |= + (1 << (ui32SectorNumber & 0x1F)); + } + + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } +} +//***************************************************************************** +// +//! Get sector protection +// +//***************************************************************************** +uint32_t +FlashProtectionGet(uint32_t ui32SectorAddress) +{ + uint32_t ui32SectorProtect; + uint32_t ui32SectorNumber; + + // + // Check the arguments. + // + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + ui32SectorProtect = FLASH_NO_PROTECT; + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + + if(ui32SectorNumber <= 31) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + else if(ui32SectorNumber <= 63) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) & + (1 << (ui32SectorNumber & 0x1F))) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) & + (1 << (ui32SectorNumber & 0x1F)))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + + return(ui32SectorProtect); +} +//***************************************************************************** +// +//! Save sector protection to make it permanent +// +//***************************************************************************** +uint32_t +FlashProtectionSave(uint32_t ui32SectorAddress) +{ + uint32_t ui32ErrorReturn; + uint32_t ui32SectorNumber; + uint32_t ui32CcfgSectorAddr; + uint8_t pui8ProgBuf[4]; + + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // + // Check the arguments. + // + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(FlashProtectionGet(ui32SectorAddress) == FLASH_WRITE_PROTECT) + { + // + // Find sector number for specified sector. + // + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + ui32CcfgSectorAddr = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); + + // + // Adjust CCFG address to the 32-bit CCFG word holding the + // protect-bit for the specified sector. + // + ui32CcfgSectorAddr += (((ui32SectorNumber >> 5) * 4) + CCFG_OFFSET_SECT_PROT); + + // + // Find value to program by setting the protect-bit which + // corresponds to specified sector number, to 0. + // Leave other protect-bits unchanged. + // + *(uint32_t *)pui8ProgBuf = (~(1 << (ui32SectorNumber & 0x1F))) & + *(uint32_t *)ui32CcfgSectorAddr; + + ui32ErrorReturn = FlashProgram(pui8ProgBuf, ui32CcfgSectorAddr, + CCFG_SIZE_SECT_PROT); + } + + // + // Return status. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Erase a flash sector +// +//***************************************************************************** +uint32_t +FlashSectorErase(uint32_t ui32SectorAddress) +{ + uint32_t ui32ErrorReturn; + uint32_t ui32Error; + uint32_t ui32SectorBit; + uint32_t ui32SectorNumber; + + // + // Check the arguments. + // + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + // + // Enable all sectors for erase. + // + EnableSectorsForWrite(); + + // + // Check the arguments. + // + if((ui32SectorAddress > + (FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet())) || + ((ui32SectorAddress & (FlashSectorSizeGet() - 1)) != 00)) + { + // + // Invalid arguments. Exit function! + // + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Unprotect sector to be erased. + // + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + ui32SectorBit = 1 << (ui32SectorNumber & 0x1F); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + if(ui32SectorNumber < 0x20) + { + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = ~ui32SectorBit; + } + else + { + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = ~ui32SectorBit; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Write the address to the FSM. + // + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32SectorAddress + ADDR_OFFSET; + + // + // Issue the sector erase command to the FSM. + // + IssueFsmCommand(FAPI_ERASE_SECTOR); + + // + // Wait for erase to finish. + // + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // + // Update status. + // + ui32ErrorReturn = FlashCheckFsmForError(); + + // + // Disable sectors for erase. + // + FlashDisableSectorsForWrite(); + + // + // Check if flash top sector was erased. + // + if(ui32SectorAddress == (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())) + { + // + // Program security data to default values in the customer configuration + // area within the flash top sector. + // + ui32Error = FlashProgram((uint8_t *)g_pui8CcfgDefaultSec, + (ui32SectorAddress + CCFG_OFFSET_SECURITY), + CCFG_SIZE_SECURITY); + + if((ui32Error != FAPI_STATUS_SUCCESS) && + (ui32ErrorReturn == FAPI_STATUS_SUCCESS)) + { + ui32ErrorReturn = ui32Error; + } + } + + // + // Return status of operation. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Programs unprotected main bank flash sectors +// +//***************************************************************************** +uint32_t +FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) +{ + uint32_t ui32StartIndex; + uint32_t ui32StopIndex; + uint32_t ui32Index; + uint8_t ui8BankWidth; + uint8_t ui8NoOfBytes; + tFwpWriteByte *oFwpWriteByte; + uint32_t ui32ErrorReturn; + + // + // Check the arguments. + // + ASSERT((ui32Address + ui32Count) <= (FLASHMEM_BASE + FlashSizeGet())); + + // + // Enable sectors for programming. + // + EnableSectorsForWrite(); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // + // Check the arguments. + // + if((ui32Address + ui32Count) > (FLASHMEM_BASE + FlashSizeGet())) + { + // + // Invalid arguments. Exit function! + // + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // + // Set the status to indicate success. + // + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // + // Find flash bank width in number of bytes. + // + ui8BankWidth = + (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // + // Loop over the bytes to be programmed. + // + while(ui32Count) + { + // + // Setup the start position within the write data registers. + // + ui32StartIndex = ui32Address & (uint32_t)(ui8BankWidth - 1); + + // + // Setup number of bytes to program. + // + ui8NoOfBytes = ui8BankWidth - ui32StartIndex; + if(ui8NoOfBytes > ui32Count) + { + ui8NoOfBytes = ui32Count; + } + + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Write address to FADDR register. + // + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32Address + ADDR_OFFSET; + + // + // Setup the stop position within the write data registers. + // + ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); + + // + // Write each byte to the FWPWrite registers. + // + for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) + { + oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); + } + + // + // Issue the Program command to the FSM. + // + IssueFsmCommand(FAPI_PROGRAM_DATA); + + // + // Wait until the word has been programmed. + // + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // + // Exit if an access violation occurred. + // + ui32ErrorReturn = FlashCheckFsmForError(); + if(ui32ErrorReturn != FAPI_STATUS_SUCCESS) + { + break; + } + + // + // Prepare for next data burst. + // + ui32Count -= ((ui32StopIndex - ui32StartIndex) + 1); + ui32Address += ((ui32StopIndex - ui32StartIndex) + 1); + } + + // + // Disable sectors for programming. + // + FlashDisableSectorsForWrite(); + + // + // Return status of operation. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Starts programming within unprotected main bank flash sector and returns +// +//***************************************************************************** +uint32_t +FlashProgramNowait(uint32_t ui32StartAddress, uint8_t *pui8DataBuffer, + uint8_t ui8NoOfBytes) +{ + uint32_t ui32StartIndex; + uint32_t ui32StopIndex; + uint32_t ui32Index; + uint32_t ui32BankWidth; + uint32_t ui32ErrorReturn; + tFwpWriteByte *oFwpWriteByte; + + // + // Check the arguments. + // + ASSERT((ui32StartAddress + ui8NoOfBytes) <= (FLASHMEM_BASE + FlashSizeGet())); + + // + // Enable sectors for programming. + // + EnableSectorsForWrite(); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // + // Check the arguments. + // + if((ui32StartAddress + ui8NoOfBytes) > (FLASHMEM_BASE + FlashSizeGet())) + { + // + // Invalid arguments. Exit function! + // + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // + // Set status to indicate success + // + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // + // Find flash bank width in number of bytes. + // + ui32BankWidth = (((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // + // Setup the start position within the write data registers. + // + ui32StartIndex = ui32StartAddress & (ui32BankWidth - 1); + + // + // Check to see if there is more data in the buffer than the register. + // width. + // + if((ui8NoOfBytes == 0) || ((ui32StartIndex + ui8NoOfBytes) > ui32BankWidth)) + { + ui32ErrorReturn = FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH; + } + + if(ui32ErrorReturn == FAPI_STATUS_SUCCESS) + { + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Write address to FADDR register. + // + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32StartAddress + ADDR_OFFSET; + + // + // Setup the stop position within the write data registers. + // + ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); + + // + // Write each byte to the FWPWrite registers. + // + for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) + { + oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); + } + + // + // Issue the Program command to the FSM. + // + IssueFsmCommand(FAPI_PROGRAM_DATA); + } + + // + // Return the function status. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Reads efuse data from specified row +// +//***************************************************************************** +bool +FlashEfuseReadRow(uint32_t *pui32EfuseData, uint32_t ui32RowAddress) +{ + bool bStatus; + + // + // Make sure the clock for the efuse is enabled + // + HWREG(FLASH_BASE + FLASH_O_CFG) &= ~FLASH_CFG_DIS_EFUSECLK; + + // + // Set timing for EFUSE read operations. + // + HWREG(FLASH_BASE + FLASH_O_EFUSEREAD) |= ((5 << FLASH_EFUSEREAD_READCLOCK_S) & + FLASH_EFUSEREAD_READCLOCK_M); + + // + // Clear status register. + // + HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) = 0; + + // + // Select the FuseROM block 0. + // + HWREG(FLASH_BASE + FLASH_O_EFUSEADDR) = 0x00000000; + + // + // Start the read operation. + // + HWREG(FLASH_BASE + FLASH_O_EFUSE) = + (DUMPWORD_INSTR << FLASH_EFUSE_INSTRUCTION_S) | + (ui32RowAddress & FLASH_EFUSE_DUMPWORD_M); + + // + // Wait for operation to finish. + // + while(!(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_DONE)) + { + } + + // + // Check if error reported. + // + if(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_CODE_M) + { + // + // Set error status. + // + bStatus = 1; + + // + // Clear data. + // + *pui32EfuseData = 0; + } + else + { + // + // Set ok status. + // + bStatus = 0; + + // + // No error. Get data from data register. + // + *pui32EfuseData = HWREG(FLASH_BASE + FLASH_O_DATALOWER); + } + + // + // Disable the efuse clock to conserve power + // + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_EFUSECLK; + + // + // Return the data. + // + return(bStatus); +} +//***************************************************************************** +// +//! Disables all sectors for erase and programming on the active bank +// +//***************************************************************************** +void +FlashDisableSectorsForWrite(void) +{ + // + // Configure flash back to read mode + // + SetReadMode(); + + // + // Disable Level 1 Protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + // + // Disable all sectors for erase and programming. + // + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; + + // + // Enable Level 1 Protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Protect sectors from sector erase. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} +//***************************************************************************** +// +//! Erase all unprotected sectors in the flash main bank +// +//***************************************************************************** +uint32_t +FlashBankErase(bool bForcePrecondition) +{ + uint32_t ui32ErrorReturn; + uint32_t ui32Error; + uint32_t ui32SectorAddress; + uint32_t ui32RegVal; + + // + // Enable all sectors for erase. + // + EnableSectorsForWrite(); + + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Enable erase of all sectors and enable precondition if required. + // + ui32RegVal = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000; + if(bForcePrecondition) + { + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + FLASH_FSM_ST_MACHINE_DO_PRECOND; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Issue the bank erase command to the FSM. + // + IssueFsmCommand(FAPI_ERASE_BANK); + + // + // Wait for erase to finish. + // + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // + // Update status. + // + ui32ErrorReturn = FlashCheckFsmForError(); + + // + // Disable sectors for erase. + // + FlashDisableSectorsForWrite(); + + // + // Set configured precondition mode since it may have been forced on. + // + if(!(ui32RegVal & FLASH_FSM_ST_MACHINE_DO_PRECOND)) + { + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= + ~FLASH_FSM_ST_MACHINE_DO_PRECOND; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } + + // + // Program security data to default values in the customer configuration + // area within the flash top sector. + // + ui32SectorAddress = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); + ui32Error = FlashProgram((uint8_t *)g_pui8CcfgDefaultSec, + (ui32SectorAddress + CCFG_OFFSET_SECURITY), + CCFG_SIZE_SECURITY); + + if((ui32Error != FAPI_STATUS_SUCCESS) && + (ui32ErrorReturn == FAPI_STATUS_SUCCESS)) + { + ui32ErrorReturn = ui32Error; + } + + // + // Return status of operation. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Erase flash OTP/ENGR areas. +// +//***************************************************************************** +uint32_t +FlashhOtpEngrErase(void) +{ + uint32_t ui32ErrorReturn; + uint32_t ui32RegVal; + + // + // Enable all sectors for erase. + // + EnableSectorsForWrite(); + + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Disable OTP protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) |= FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Enable test commands. + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // + // Set address to OTP. + // + HWREG(FLASH_BASE + FLASH_O_FADDR) = 0xF0000000; + + // + // Enable for FSM test commands and erase precondition. + // + ui32RegVal = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + (FLASH_FSM_ST_MACHINE_CMD_EN | FLASH_FSM_ST_MACHINE_DO_PRECOND); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Issue the erase command to the FSM. + // + IssueFsmCommand(FAPI_ERASE_OTP); + + // + // Wait for erase to finish. + // + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // + // Update status. + // + ui32ErrorReturn = FlashCheckFsmForError(); + + // + // Disable sectors for erase. + // + FlashDisableSectorsForWrite(); + + // + // Disable test commands. + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // + // Renable OTP protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Disable FSM test command mode. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + + // + // Set configured precondition mode since it may have been changed. + // + if(!(ui32RegVal & FLASH_FSM_ST_MACHINE_DO_PRECOND)) + { + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= + ~FLASH_FSM_ST_MACHINE_DO_PRECOND; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Return status of operation. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Programs a data pattern in a main bank flash sector. +// +//***************************************************************************** +uint32_t +FlashProgramPattern(uint32_t ui32SectorAddress, uint32_t ui32DataPattern, + bool bInvertData) +{ + uint8_t ui8Index; + uint8_t ui8BankWidth; + tFwpWriteByte *oFwpWriteByte; + uint32_t ui32ErrorReturn; + + // + // Check the arguments. + // + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + // + // Enable sectors for programming. + // + EnableSectorsForWrite(); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // + // Check the arguments. + // + if((ui32SectorAddress > + (FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet())) || + ((ui32SectorAddress & (FlashSectorSizeGet() - 1)) != 00)) + { + // + // Invalid arguments. Exit function! + // + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // + // Find flash bank width in number of bytes. + // + ui8BankWidth = + (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Write address to FADDR register. + // + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32SectorAddress + ADDR_OFFSET; + + // + // Write each byte of the pattern to the FWPWrite registers. + // + for(ui8Index = 0; ui8Index < ui8BankWidth; ui8Index++) + { + oFwpWriteByte[ui8Index] = ui32DataPattern >> ((ui8Index * 8) & + (PATTERN_BITS - 1)); + } + + // + // Enable for FSM test command and enable the Invert Data option if + // required. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; + if(bInvertData) + { + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_INV_DATA; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Issue the Program command to the FSM. + // + IssueFsmCommand(FAPI_PROGRAM_SECTOR); + + // + // Wait until the sector has been programmed. + // + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // + // Update status of the program operation. + // + ui32ErrorReturn = FlashCheckFsmForError(); + + // + // Disable sectors for programming. + // + FlashDisableSectorsForWrite(); + + // + // Disable FSM test command mode and the Invert Data option. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_INV_DATA; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Return status of operation. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! Programs flash ENGR area +// +//***************************************************************************** +uint32_t +FlashProgramEngr(uint8_t *pui8DataBuffer, uint32_t ui32AddressOffset, + uint32_t ui32Count) +{ + uint32_t ui32StartIndex; + uint32_t ui32StopIndex; + uint32_t ui32Index; + uint8_t ui8BankWidth; + uint8_t ui8NoOfBytes; + tFwpWriteByte *oFwpWriteByte; + uint32_t ui32ErrorReturn; + + // + // Check the arguments. + // + ASSERT((ui32AddressOffset + ui32Count) <= 1024); + + // + // Enable sectors for programming. + // + EnableSectorsForWrite(); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // + // Check the arguments. + // + if((ui32AddressOffset + ui32Count) > 1024) + { + // + // Invalid arguments. Exit function! + // + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // + // Set the status to indicate success. + // + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // + // Find flash bank width in number of bytes. + // + ui8BankWidth = + (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // + // Disable OTP protection. + // + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) |= FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Enable test commands. + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // + // Enable for FSM test command. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Loop over the bytes to be programmed. + // + while(ui32Count) + { + // + // Setup the start position within the write data registers. + // + ui32StartIndex = ui32AddressOffset & (uint32_t)(ui8BankWidth - 1); + + // + // Setup number of bytes to program. + // + ui8NoOfBytes = ui8BankWidth - ui32StartIndex; + if(ui8NoOfBytes > ui32Count) + { + ui8NoOfBytes = ui32Count; + } + + // + // Clear the Status register. + // + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // + // Write address to FADDR register. + // + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32AddressOffset + 0xF0080000; + + // + // Setup the stop position within the write data registers. + // + ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); + + // + // Write each byte to the FWPWrite registers. + // + for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) + { + oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); + } + + // + // Issue programming command. + // + IssueFsmCommand(FAPI_PROGRAM_DATA); + + // + // Wait until the word has been programmed. + // + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // + // Update error status and exit if an error occurred. + // + ui32ErrorReturn = FlashCheckFsmForError(); + if(ui32ErrorReturn != FAPI_STATUS_SUCCESS) + { + break; + } + + // + // Prepare for next data burst. + // + ui32Count -= ((ui32StopIndex - ui32StartIndex) + 1); + ui32AddressOffset += ((ui32StopIndex - ui32StartIndex) + 1); + } + + // + // Disable sectors for programming. + // + FlashDisableSectorsForWrite(); + + // + // Reenable OTP protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Disable test commands. + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // + // Disable FSM test command mode. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // + // Return status of operation. + // + return(ui32ErrorReturn); +} +//***************************************************************************** +// +//! FlashOtpProgramEraseSetup prepares program and erase of the OTP/ENGR +//! sector. +// +//***************************************************************************** +void +FlashOtpProgramEraseSetup(void) +{ + // + // Disable OTP protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) |= FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Enable test commands by performing the following steps: + // - Enable SW Interface mode + // - Enable for test commands + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x0000AAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x000055AA; + + // + // Enable for FSM test commands. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} +//***************************************************************************** +// +//! FlashOtpProgramEraseCleanup restores to default program and erase +//! protection. +// +//***************************************************************************** +void +FlashOtpProgramEraseCleanup(void) +{ + // + // Reenable OTP protection. + // + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // + // Disable test commands and turn off SW interface mode. + // + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x0000AAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // + // Disable FSM test command mode. + // + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} +//! @} +//! \\addtogroup i2c_api +//! @{ +//***************************************************************************** +// +//! Initializes the I2C Master block +// +//***************************************************************************** +void +I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast) +{ + uint32_t ui32SCLFreq; + uint32_t ui32TPR; + + // + // Check the arguments. + // + ASSERT(I2CBaseValid(ui32Base)); + + // + // Must enable the device before doing anything else. + // + I2CMasterEnable(ui32Base); + + // + // Get the desired SCL speed. + // + if(bFast == true) + { + ui32SCLFreq = 400000; + } + else + { + ui32SCLFreq = 100000; + } + + // + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biased to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + // + ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / (2 * 10 * ui32SCLFreq)) - 1; + HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; +} +//***************************************************************************** +// +//! Gets the error status of the I2C Master module +// +//***************************************************************************** +uint32_t +I2CMasterErr(uint32_t ui32Base) +{ + uint32_t ui32Err; + + // + // Check the arguments. + // + ASSERT(I2CBaseValid(ui32Base)); + + // + // Get the raw error state. + // + ui32Err = HWREG(ui32Base + I2C_O_MSTAT); + + // + // If the I2C master is busy, then all the other status bits are invalid, + // and there is no error to report. + // + if(ui32Err & I2C_MSTAT_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // + // Check for errors. + // + if(ui32Err & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST)) + { + return(ui32Err & (I2C_MSTAT_ARBLST | I2C_MSTAT_DATACK | I2C_MSTAT_ADRACK)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} +//! @} +//! \\addtogroup interrupt_api +//! @{ +//***************************************************************************** +// +//! This is a mapping between priority grouping encodings and the number of +//! preemption priority bits. +// +//***************************************************************************** +static const uint32_t g_pui32Priority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; + +//***************************************************************************** +// +//! This is a mapping between interrupt number and the register that contains +//! the priority encoding for that interrupt. +// +//***************************************************************************** +static const uint32_t g_pui32Regs[] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13 +}; +//***************************************************************************** +// +//! Sets the priority grouping of the interrupt controller. +// +//***************************************************************************** +void +IntPriorityGroupingSet(uint32_t ui32Bits) +{ + // + // Check the arguments. + // + ASSERT(ui32Bits < NUM_PRIORITY); + + // + // Set the priority grouping. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; +} +//***************************************************************************** +// +//! Gets the priority grouping of the interrupt controller +// +//***************************************************************************** +uint32_t +IntPriorityGroupingGet(void) +{ + uint32_t ui32Loop, ui32Value; + + // + // Read the priority grouping. + // + ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // + // Loop through the priority grouping values. + // + for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++) + { + // + // Stop looping if this value matches. + // + if(ui32Value == g_pui32Priority[ui32Loop]) + { + break; + } + } + + // + // Return the number of priority bits. + // + return(ui32Loop); +} +//***************************************************************************** +// +//! Sets the priority of an interrupt +// +//***************************************************************************** +void +IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority) +{ + uint32_t ui32Temp; + + // + // Check the arguments. + // + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + ASSERT(ui8Priority <= INT_PRI_LEVEL7); + + // + // Set the interrupt priority. + // + ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); + ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3))); + ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3)); + HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; +} +//***************************************************************************** +// +//! Gets the priority of an interrupt +// +//***************************************************************************** +int32_t +IntPriorityGet(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + + // + // Return the interrupt priority. + // + return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) & + 0xFF); +} +//***************************************************************************** +// +//! Enables an interrupt +// +//***************************************************************************** +void +IntEnable(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to enable. + // + if(ui32Interrupt == FAULT_MPU) + { + // + // Enable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ui32Interrupt == FAULT_BUS) + { + // + // Enable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ui32Interrupt == FAULT_USAGE) + { + // + // Enable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ui32Interrupt == FAULT_SYSTICK) + { + // + // Enable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // + // Enable the general interrupt. + // + HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // + // Enable the general interrupt. + // + HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48); + } +} +//***************************************************************************** +// +//! Disables an interrupt +// +//***************************************************************************** +void +IntDisable(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to disable. + // + if(ui32Interrupt == FAULT_MPU) + { + // + // Disable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ui32Interrupt == FAULT_BUS) + { + // + // Disable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ui32Interrupt == FAULT_USAGE) + { + // + // Disable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ui32Interrupt == FAULT_SYSTICK) + { + // + // Disable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // + // Disable the general interrupt. + // + HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // + // Disable the general interrupt. + // + HWREG(NVIC_DIS1) = 1 << (ui32Interrupt - 48); + } +} +//***************************************************************************** +// +//! Pends an interrupt +// +//***************************************************************************** +void +IntPendSet(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to pend. + // + if(ui32Interrupt == FAULT_NMI) + { + // + // Pend the NMI interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; + } + else if(ui32Interrupt == FAULT_PENDSV) + { + // + // Pend the PendSV interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; + } + else if(ui32Interrupt == FAULT_SYSTICK) + { + // + // Pend the SysTick interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // + // Pend the general interrupt. + // + HWREG(NVIC_PEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // + // Pend the general interrupt. + // + HWREG(NVIC_PEND1) = 1 << (ui32Interrupt - 48); + } +} +//***************************************************************************** +// +//! Query whether an interrupt is pending +// +//***************************************************************************** +bool +IntPendGet(uint32_t ui32Interrupt) +{ + uint32_t ui32IntPending; + + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Assume no interrupts are pending. + // + ui32IntPending = 0; + + // + // The lower 16 IRQ vectors are unsupported by this function + // + if (ui32Interrupt < 16) + { + + return 0; + } + + // + // Subtract lower 16 irq vectors + // + ui32Interrupt -= 16; + + // + // Check if the interrupt is pending + // + ui32IntPending = HWREG(NVIC_PEND0 + (ui32Interrupt / 32)); + ui32IntPending &= (1 << (ui32Interrupt & 31)); + + return ui32IntPending ? true : false; +} +//***************************************************************************** +// +//! Unpends an interrupt +// +//***************************************************************************** +void +IntPendClear(uint32_t ui32Interrupt) +{ + // + // Check the arguments. + // + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to unpend. + // + if(ui32Interrupt == FAULT_PENDSV) + { + // + // Unpend the PendSV interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; + } + else if(ui32Interrupt == FAULT_SYSTICK) + { + // + // Unpend the SysTick interrupt. + // + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // + // Unpend the general interrupt. + // + HWREG(NVIC_UNPEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // + // Unpend the general interrupt. + // + HWREG(NVIC_UNPEND1) = 1 << (ui32Interrupt - 48); + } +} +//! @} +//! \\addtogroup ioc_api +//! @{ +//***************************************************************************** +// +// This is the mapping between an IO and the corresponding configuration +// register. +// +//***************************************************************************** +static const uint32_t g_pui32IOCfgReg[] = +{ + IOC_O_IOCFG0, IOC_O_IOCFG1, IOC_O_IOCFG2, IOC_O_IOCFG3, IOC_O_IOCFG4, + IOC_O_IOCFG5, IOC_O_IOCFG6, IOC_O_IOCFG7, IOC_O_IOCFG8, IOC_O_IOCFG9, + IOC_O_IOCFG10, IOC_O_IOCFG11, IOC_O_IOCFG12, IOC_O_IOCFG13, IOC_O_IOCFG14, + IOC_O_IOCFG15, IOC_O_IOCFG16, IOC_O_IOCFG17, IOC_O_IOCFG18, IOC_O_IOCFG19, + IOC_O_IOCFG20, IOC_O_IOCFG21, IOC_O_IOCFG22, IOC_O_IOCFG23, IOC_O_IOCFG24, + IOC_O_IOCFG25, IOC_O_IOCFG26, IOC_O_IOCFG27, IOC_O_IOCFG28, IOC_O_IOCFG29, + IOC_O_IOCFG30, IOC_O_IOCFG31 +}; +//***************************************************************************** +// +//! Set the configuration of an IO port +// +//***************************************************************************** +void +IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, + uint32_t ui32IOConfig) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_SMI_CL_IN); + + // + // Get the register address. + // + ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the port. + // + HWREG(ui32Reg) = ui32IOConfig | ui32PortId; +} +//***************************************************************************** +// +//! Get the configuration of an IO port +// +//***************************************************************************** +uint32_t +IOCPortConfigureGet(uint32_t ui32IOId) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + + // + // Get the register address. + // + ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Return the IO configuration. + // + return HWREG(ui32Reg); +} +//***************************************************************************** +// +//! Set wake-up on an IO port +// +//***************************************************************************** +void +IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) || + (ui32IOShutdown == IOC_WAKE_ON_LOW) || + (ui32IOShutdown == IOC_WAKE_ON_HIGH)); + + // + // Get the register address. + // + ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_WU_CFG_M; + HWREG(ui32Reg) = ui32Config | ui32IOShutdown; +} +//***************************************************************************** +// +//! Set wake-up on an IO port +// +//***************************************************************************** +void +IOCIOJTagSet(uint32_t ui32IOId, uint32_t ui32IOJTag) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOJTag == IOC_JTAG_TDO_ENABLE) || + (ui32IOJTag == IOC_JTAG_TDI_ENABLE) || + (ui32IOJTag == IOC_JTAG_DISABLE)); + + // + // Get the register address. + // + ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32Reg); + ui32Config &= ~(IOC_IOCFG0_TDI | IOC_IOCFG0_TDO); + HWREG(ui32Reg) = ui32Config | ui32IOJTag; +} +//***************************************************************************** +// +//! Set the IO Mode of an IO Port +// +//***************************************************************************** +void +IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) || + (ui32IOMode == IOC_IOMODE_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_INV)); + + // + // Get the register address. + // + ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_IOMODE_M; + HWREG(ui32Reg) = ui32Config | ui32IOMode; +} +//***************************************************************************** +// +//! Setup interrupt detection on an IO Port +// +//***************************************************************************** +void +IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Int == IOC_INT_ENABLE) || + (ui32Int == IOC_INT_DISABLE)); + ASSERT((ui32EdgeDet == IOC_NO_EDGE) || + (ui32EdgeDet == IOC_FALLING_EDGE) || + (ui32EdgeDet == IOC_RISING_EDGE) || + (ui32EdgeDet == IOC_BOTH_EDGES)); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_EDGE_IRQ_EN | IOC_IOCFG0_EDGE_DET_M); + HWREG(ui32IOReg) = ui32Config | ((ui32Int ? IOC_IOCFG0_EDGE_IRQ_EN : 0) | ui32EdgeDet); +} +//***************************************************************************** +// +//! Set the pull on an IO port +// +//***************************************************************************** +void +IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the argument. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Pull == IOC_NO_IOPULL) || + (ui32Pull == IOC_IOPULL_UP) || + (ui32Pull == IOC_IOPULL_DOWN)); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PULL_CTL_M; + HWREG(ui32IOReg) = ui32Config | ui32Pull; +} +//***************************************************************************** +// +//! Configure hysteresis on and IO port +// +//***************************************************************************** +void +IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Hysteresis == IOC_HYST_ENABLE) || + (ui32Hysteresis == IOC_HYST_DISABLE)); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_HYST_EN; + HWREG(ui32IOReg) = ui32Config | ui32Hysteresis; +} +//***************************************************************************** +// +//! Enable/disable IO port as input +// +//***************************************************************************** +void +IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Input == IOC_INPUT_ENABLE) || + (ui32Input == IOC_INPUT_DISABLE)); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_IE; + HWREG(ui32IOReg) = ui32Config | ui32Input; +} +//***************************************************************************** +// +//! Enable/disable the slew control on an IO port +// +//***************************************************************************** +void +IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32SlewEnable == IOC_SLEW_ENABLE) || + (ui32SlewEnable == IOC_SLEW_DISABLE)); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_SLEW_RED; + HWREG(ui32IOReg) = ui32Config | ui32SlewEnable; +} +//***************************************************************************** +// +//! Configure the drive strength and maxium current of an IO port +// +//***************************************************************************** +void +IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, + uint32_t ui32DrvStrength) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOCurrent == IOC_CURRENT_2MA) || + (ui32IOCurrent == IOC_CURRENT_4MA) || + (ui32IOCurrent == IOC_CURRENT_8MA) || + (ui32IOCurrent == IOC_CURRENT_16MA)); + ASSERT((ui32DrvStrength == IOC_STRENGTH_MIN) || + (ui32DrvStrength == IOC_STRENGTH_MAX) || + (ui32DrvStrength == IOC_STRENGTH_MED) || + (ui32DrvStrength == IOC_STRENGTH_AUTO)); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_IOCURR_M | IOC_IOCFG0_IOSTR_M); + HWREG(ui32IOReg) = ui32Config | (ui32IOCurrent | ui32DrvStrength); +} +//***************************************************************************** +// +//! Setup the Port ID for this IO +// +//***************************************************************************** +void +IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_SMI_CL_IN); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Configure the IO. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PORT_ID_M; + HWREG(ui32IOReg) = ui32Config | ui32PortId; +} +//***************************************************************************** +// +//! Enables individual IO edge detect interrupt +//! +//! \param ui32IOId is the IO to enable edge detect interrupt for. +//! +//! This function enables the indicated IO edge interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None +// +//***************************************************************************** +void +IOCIntEnable(uint32_t ui32IOId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Enable the specified interrupt. + // + ui32Config = HWREG(ui32IOReg); + ui32Config |= IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} +//***************************************************************************** +// +//! Disables individual IO edge interrupt sources +// +//***************************************************************************** +void +IOCIntDisable(uint32_t ui32IOId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + + // + // Get the register address. + // + ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; + + // + // Disable the specified interrupt. + // + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} +//***************************************************************************** +// +//! Setup an IO for standard GPIO input +// +//***************************************************************************** +void +IOCPinTypeGpioInput(uint32_t ui32IOId) +{ + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + + // + // Setup the IO for standard input. + // + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_INPUT); + + // + // Enable input mode in the GPIO module. + // + GPIODirModeSet(1 << ui32IOId, GPIO_DIR_MODE_IN); +} +//***************************************************************************** +// +//! Setup an IO for standard GPIO output +// +//***************************************************************************** +void +IOCPinTypeGpioOutput(uint32_t ui32IOId) +{ + // + // Check the arguments. + // + ASSERT(ui32IOId <= IOID_31); + + // + // Setup the IO for standard input. + // + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_OUTPUT); + + // + // Enable output mode in the GPIO module. + // + GPIODirModeSet(1 << ui32IOId, GPIO_DIR_MODE_OUT); +} +//***************************************************************************** +// +//! Configure a set of IOs for standard UART peripheral control +// +//***************************************************************************** +void +IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, + uint32_t ui32Cts, uint32_t ui32Rts) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == UART0_BASE); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Cts <= IOID_31) || (ui32Cts == IOID_UNUSED)); + ASSERT((ui32Rts <= IOID_31) || (ui32Rts == IOID_UNUSED)); + + // + // Setup the IOs in the desired configuration. + // + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_UART0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_UART0_TX, IOC_STD_OUTPUT); + } + if(ui32Cts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Cts, IOC_PORT_MCU_UART0_CTS, IOC_STD_INPUT); + } + if(ui32Rts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rts, IOC_PORT_MCU_UART0_RTS, IOC_STD_OUTPUT); + } +} +//***************************************************************************** +// +//! Configure a set of IOs for standard SSI peripheral master control +// +//***************************************************************************** +void +IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // + // Setup the IOs in the desired configuration. + // + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_OUTPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_OUTPUT); + } + } +} +//***************************************************************************** +// +//! Configure a set of IOs for standard SSI peripheral slave control +// +//***************************************************************************** +void +IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // + // Setup the IOs in the desired configuration. + // + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_INPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_INPUT); + } + } +} +//***************************************************************************** +// +//! Configure a set of IOs for standard I2C peripheral control +// +//***************************************************************************** +void +IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk) +{ + uint32_t ui32IOConfig; + + // + // Check the arguments. + // + ASSERT((ui32Data <= IOID_31) || (ui32Data == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // + // Define the IO configuration parameters. + // + ui32IOConfig = IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_IOPULL_UP | + IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | + IOC_INT_DISABLE | IOC_IOMODE_OPEN_DRAIN_NORMAL | + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE; + + // + // Setup the IOs in the desired configuration. + // + IOCPortConfigureSet(ui32Data, IOC_PORT_MCU_I2C_MSSDA, ui32IOConfig); + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_I2C_MSSCL, ui32IOConfig); +} +//***************************************************************************** +// +//! Configure a set of IOs for standard SPIS peripheral control +// +//***************************************************************************** +void +IOCPinTypeSpis(uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // + // Check the arguments. + // + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // + // Setup the IOs in the desired configuration. + // + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_AON_SDI, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_AON_SDO, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_AON_SCS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_AON_SCK, IOC_STD_INPUT); + } +} +//***************************************************************************** +// +//! Configure an IO for AUX control +// +//***************************************************************************** +void +IOCPinTypeAux(uint32_t ui32IOId) +{ + // + // Check the arguments. + // + ASSERT((ui32IOId <= IOID_31) || (ui32IOId == IOID_UNUSED)); + + // + // Setup the IO. + // + IOCPortConfigureSet(ui32IOId, IOC_PORT_AUX_IO, IOC_STD_INPUT); +} +//! @} +//! \\addtogroup prcm_api +//! @{ + +//***************************************************************************** +// +// Arrays that maps the "peripheral set" number (which is stored in the +// third nibble of the PRCM_PERIPH_* defines) to the PRCM register that +// contains the relevant bit for that peripheral. +// +//***************************************************************************** + +// Run mode registers +static const uint32_t g_pui32RCGCRegs[] = +{ + PRCM_O_GPTCLKGR, + PRCM_O_SSICLKGR, + PRCM_O_UARTCLKGR, + PRCM_O_I2CCLKGR, + PRCM_O_SECDMACLKGR, + PRCM_O_GPIOCLKGR, + PRCM_O_I2SCLKGR +}; + +// Sleep mode registers +static const uint32_t g_pui32SCGCRegs[] = +{ + PRCM_O_GPTCLKGS, + PRCM_O_SSICLKGS, + PRCM_O_UARTCLKGS, + PRCM_O_I2CCLKGS, + PRCM_O_SECDMASCLKG, + PRCM_O_GPIOCLKGS, + PRCM_O_I2SCLKGS +}; + +// Deep sleep mode registers +static const uint32_t g_pui32DCGCRegs[] = +{ + PRCM_O_GPTCLKGDS, + PRCM_O_SSICLKGDS, + PRCM_O_UARTCLKGDS, + PRCM_O_I2CCLKGDS, + PRCM_O_SECDMACLKGDS, + PRCM_O_GPIOCLKGDS, + PRCM_O_I2SCLKGDS +}; + +//***************************************************************************** +// +// This macro extracts the array index out of the peripheral number +// +//***************************************************************************** +#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf) + +//***************************************************************************** +// +// This macro extracts the peripheral instance number and generates bit mask +// +//***************************************************************************** +#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0xf)) + +//***************************************************************************** +// +//! Configure the infrastructure clock. +// +//***************************************************************************** +void +PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode) +{ + uint32_t ui32Divisor; + + // + // Check the arguments. + // + ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || + (ui32ClkDiv == PRCM_CLOCK_DIV_2) || + (ui32ClkDiv == PRCM_CLOCK_DIV_8) || + (ui32ClkDiv == PRCM_CLOCK_DIV_32)); + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32Divisor = 0; + + // + // Find the correct division factor. + // + if(ui32ClkDiv == PRCM_CLOCK_DIV_1) + { + ui32Divisor = 0x0; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_2) + { + ui32Divisor = 0x1; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_8) + { + ui32Divisor = 0x2; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_32) + { + ui32Divisor = 0x3; + } + + // + // Determine the correct power mode set the division factor accordingly. + // + if(ui32PowerMode == PRCM_RUN_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor; + } +} +//***************************************************************************** +// +//! Use this function to retreive the set infrastructure clock configuration +// +//***************************************************************************** +uint32_t +PRCMInfClockConfigureGet(uint32_t ui32PowerMode) +{ + uint32_t ui32ClkDiv; + uint32_t ui32Divisor; + + // + // Check the arguments. + // + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32ClkDiv = 0; + ui32Divisor = 0; + + // + // Determine the correct power mode. + // + if(ui32PowerMode == PRCM_RUN_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR); + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS); + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS); + } + + // + // Find the correct division factor. + // + if(ui32ClkDiv == 0x0) + { + ui32Divisor = PRCM_CLOCK_DIV_1; + } + else if(ui32ClkDiv == 0x1) + { + ui32Divisor = PRCM_CLOCK_DIV_2; + } + else if(ui32ClkDiv == 0x2) + { + ui32Divisor = PRCM_CLOCK_DIV_8; + } + else if(ui32ClkDiv == 0x3) + { + ui32Divisor = PRCM_CLOCK_DIV_32; + } + + // + // Return the clock divison factor. + // + return ui32Divisor; +} +//***************************************************************************** +// +//! Setup the clock division factor for a subsystem in the MCU voltage +//! domain. +// +//***************************************************************************** +void +PRCMClockConfigureSet(uint32_t ui32Domains, uint32_t ui32ClkDiv) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT((ui32Domains & PRCM_DOMAIN_SYSBUS) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_TIMER) || + (ui32Domains & PRCM_DOMAIN_SERIAL)); + ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || + (ui32ClkDiv == PRCM_CLOCK_DIV_2) || + (ui32ClkDiv == PRCM_CLOCK_DIV_4) || + (ui32ClkDiv == PRCM_CLOCK_DIV_8) || + (ui32ClkDiv == PRCM_CLOCK_DIV_16) || + (ui32ClkDiv == PRCM_CLOCK_DIV_32) || + (ui32ClkDiv == PRCM_CLOCK_DIV_64) || + (ui32ClkDiv == PRCM_CLOCK_DIV_128) || + (ui32ClkDiv == PRCM_CLOCK_DIV_256)); + + // + // Configure the selected clock dividers. + // + if(ui32Domains & PRCM_DOMAIN_SYSBUS) + { + ui32Reg = PRCM_O_SYSBUSCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + ui32Reg = PRCM_O_CPUCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + ui32Reg = PRCM_O_PERBUSCPUCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + ui32Reg = PRCM_O_PERDMACLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_TIMER) + { + ui32Reg = PRCM_O_GPTCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } +} +//***************************************************************************** +// +//! Get the clock configuration for a specific sub system in the MCU Voltage +//! Domain. +// +//***************************************************************************** +uint32_t +PRCMClockConfigureGet(uint32_t ui32Domain) +{ + uint32_t ui32ClkDiv; + + // + // Check the arguments. + // + ASSERT((ui32Domain == PRCM_DOMAIN_SYSBUS) || + (ui32Domain == PRCM_DOMAIN_CPU) || + (ui32Domain == PRCM_DOMAIN_PERIPH) || + (ui32Domain == PRCM_DOMAIN_TIMER) || + (ui32Domain == PRCM_DOMAIN_SERIAL)); + + ui32ClkDiv = 0; + + // + // Find the correct sub system. + // + if(ui32Domain == PRCM_DOMAIN_SYSBUS) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_SYSBUSCLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_CPU) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_CPUCLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_PERIPH) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_PERBUSCPUCLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_SERIAL) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_PERDMACLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_TIMER) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_GPTCLKDIV); + } + + // + // Return the clock configuration. + // + return(ui32ClkDiv); +} +//***************************************************************************** +// +//! Configure the audio clock generation +// +//***************************************************************************** +void +PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate) +{ + uint32_t ui32Reg; + uint32_t ui32MstDiv; + uint32_t ui32BitDiv; + uint32_t ui32WordDiv; + + // + // Check the arguments. + // + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) || + (ui32SampleRate == I2S_SAMPLE_RATE_24K) || + (ui32SampleRate == I2S_SAMPLE_RATE_32K) || + (ui32SampleRate == I2S_SAMPLE_RATE_48K)); + + ui32MstDiv = 0; + ui32BitDiv = 0; + ui32WordDiv = 0; + + // + // Make sure the audio clock generation is disabled before reconfiguring. + // + PRCMAudioClockDisable(); + + // + // Define the clock division factors for the audio interface. + // + switch(ui32SampleRate) + { + case I2S_SAMPLE_RATE_16K : + ui32MstDiv = 6; + ui32BitDiv = 60; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_24K : + ui32MstDiv = 4; + ui32BitDiv = 40; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_32K : + ui32MstDiv = 3; + ui32BitDiv = 30; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_48K : + ui32MstDiv = 2; + ui32BitDiv = 20; + ui32WordDiv = 25; + break; + } + + // + // Make sure to compensate the Frame clock division factor if using single + // phase format. + // + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // + // Write the clock divison factors. + // + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // + // Configure the Word clock format and polarity. + // + ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} +//***************************************************************************** +// +//! Turn power on in power domains in the MCU domain +// +//***************************************************************************** +void +PRCMPowerDomainOn(uint32_t ui32Domains) +{ + // + // Check the arguments. + // + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // + // Assert the request to power on the right domains. + // + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + + PRCM_O_PDCTL0RFC) |= PRCM_PDCTL0RFC_ON; + HWREG(PRCM_BASE + PRCM_O_PDCTL1RFC) |= PRCM_PDCTL1RFC_ON; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + + PRCM_O_PDCTL0SERIAL) |= PRCM_PDCTL0SERIAL_ON; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + + PRCM_O_PDCTL0PERIPH) |= PRCM_PDCTL0PERIPH_ON; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) |= + PRCM_PDCTL1VIMS_ON; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU) |= PRCM_PDCTL1CPU_ON; + } +} +//***************************************************************************** +// +//! Turn off a specific power domain +// +//***************************************************************************** +void +PRCMPowerDomainOff(uint32_t ui32Domains) +{ + // + // Check the arguments. + // + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // + // Assert the request to power off the right domains. + // + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + + PRCM_O_PDCTL0RFC) &= ~PRCM_PDCTL0RFC_ON; + HWREG(PRCM_BASE + PRCM_O_PDCTL1RFC) &= ~PRCM_PDCTL1RFC_ON; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + + PRCM_O_PDCTL0SERIAL) &= ~PRCM_PDCTL0SERIAL_ON; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + + PRCM_O_PDCTL0PERIPH) &= ~PRCM_PDCTL0PERIPH_ON; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) &= + ~PRCM_PDCTL1VIMS_ON; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU) &= ~PRCM_PDCTL1CPU_ON; + } +} +//***************************************************************************** +// +//! Enables a peripheral in Run mode +// +//***************************************************************************** +void +PRCMPeripheralRunEnable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // + // Enable module in Run Mode. + // + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} +//***************************************************************************** +// +//! Disables a peripheral in Run mode +// +//***************************************************************************** +void +PRCMPeripheralRunDisable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // + // Disable module in Run Mode. + // + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} +//***************************************************************************** +// +//! Enables a peripheral in sleep mode +// +//***************************************************************************** +void +PRCMPeripheralSleepEnable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // + // Enable this peripheral in sleep mode. + // + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} +//***************************************************************************** +// +//! Disables a peripheral in sleep mode +// +//***************************************************************************** +void +PRCMPeripheralSleepDisable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // + // Disable this peripheral in sleep mode + // + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} +//***************************************************************************** +// +//! Enables a peripheral in deep-sleep mode +// +//***************************************************************************** +void +PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // + // Enable this peripheral in deep-sleep mode. + // + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} +//***************************************************************************** +// +//! Disables a peripheral in deep-sleep mode +// +//***************************************************************************** +void +PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral) +{ + // + // Check the arguments. + // + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // + // Disable this peripheral in Deep Sleep mode. + // + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} +//***************************************************************************** +// +//! Get the status for a specific power domain +// +//***************************************************************************** +uint32_t +PRCMPowerDomainStatus(uint32_t ui32Domains) +{ + bool bStatus; + uint32_t ui32StatusRegister0; + uint32_t ui32StatusRegister1; + + // + // Check the arguments. + // + ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE | + PRCM_DOMAIN_SERIAL | + PRCM_DOMAIN_PERIPH))); + + bStatus = true; + ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0); + ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1); + + // + // Return the correct power status. + // + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + bStatus = bStatus && + ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) || + (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON)); + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON); + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON); + } + + // + // Return the status. + // + return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF); +} +//***************************************************************************** +// +//! Put the processor into deep-sleep mode +// +//***************************************************************************** +void +PRCMDeepSleep(void) +{ + // + // Enable deep-sleep. + // + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // + // Wait for an interrupt. + // + CPUwfi(); + + // + // Disable deep-sleep so that a future sleep will work correctly. + // + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} +//***************************************************************************** +// +//! Enable retention on specific power domains +// +//***************************************************************************** +void +PRCMRetentionEnable(uint32_t ui32PowerDomain) +{ + uint32_t ui32Retention; + + // + // Check the arguments. + // + ASSERT((PRCM_DOMAIN_PERIPH & ui32PowerDomain) || + (PRCM_DOMAIN_CPU & ui32PowerDomain)); + + // + // Get the current register. + // + ui32Retention = HWREG(PRCM_BASE + PRCM_O_PDRETEN); + + // + // Set the bits. + // + if(PRCM_DOMAIN_PERIPH & ui32PowerDomain) + { + ui32Retention |= PRCM_PDRETEN_PERIPH; + } + if(PRCM_DOMAIN_CPU & ui32PowerDomain) + { + ui32Retention |= PRCM_PDRETEN_CPU; + } + + // + // Reconfigure retention. + // + HWREG(PRCM_BASE + PRCM_O_PDRETEN) = ui32Retention; + + // + // Get the current register values. + // + ui32Retention = HWREG(PRCM_BASE + PRCM_O_RAMRETEN); + + // + // Enable retention on RF core SRAM. + // + if(PRCM_DOMAIN_RFCORE & ui32PowerDomain) + { + ui32Retention |= PRCM_RAMRETEN_RFC_M; + } + + // + // Enable retention on VIMS cache. + // + if(PRCM_DOMAIN_VIMS & ui32PowerDomain) + { + ui32Retention |= PRCM_RAMRETEN_VIMS_M; + } + + // + // Reconfigure retention. + // + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention; +} +//***************************************************************************** +// +//! Disable retention on power domains +// +//***************************************************************************** +void +PRCMRetentionDisable(uint32_t ui32PowerDomain) +{ + uint32_t ui32Retention; + + // + // Check the arguments. + // + ASSERT((PRCM_DOMAIN_PERIPH & ui32PowerDomain) || + (PRCM_DOMAIN_CPU & ui32PowerDomain)); + + // + // Get the current register. + // + ui32Retention = HWREG(PRCM_BASE + PRCM_O_PDRETEN); + + // + // Clear the bits. + // + if(PRCM_DOMAIN_PERIPH & ui32PowerDomain) + { + ui32Retention &= ~PRCM_PDRETEN_PERIPH; + } + if(PRCM_DOMAIN_CPU & ui32PowerDomain) + { + ui32Retention &= ~PRCM_PDRETEN_CPU; + } + + // + // Reconfigure retention. + // + HWREG(PRCM_BASE + PRCM_O_PDRETEN) = ui32Retention; + + // + // Get the current register values + // + ui32Retention = HWREG(PRCM_BASE + PRCM_O_RAMRETEN); + + // + // Disable retention on RF core SRAM + // + if(PRCM_DOMAIN_RFCORE & ui32PowerDomain) + { + ui32Retention &= ~PRCM_RAMRETEN_RFC_M; + } + + // + // Disable retention on VIMS cache + // + if(PRCM_DOMAIN_VIMS & ui32PowerDomain) + { + ui32Retention &= ~PRCM_RAMRETEN_VIMS_M; + } + + // + // Reconfigure retention. + // + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention; +} +//! @} +//! \\addtogroup smph_api +//! @{ +//***************************************************************************** +// +//! Acquire a semaphore +// +//***************************************************************************** +void +SMPHAcquire(uint32_t ui32Semaphore) +{ + // + // Check the arguments. + // + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // + // Wait for semaphore to be release such that it can be claimed + // Semaphore register reads 1 when lock was acquired otherwise 0 + // (i.e. SMPH_CLAIMED). + // + while(HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) == + SMPH_CLAIMED) + { + } +} +//! @} +//! \\addtogroup spis_api +//! @{ +//***************************************************************************** +// +// This is the mapping between an TX Fifo index and the corresponding +// register. +// +//***************************************************************************** +static const uint32_t g_pui32SPISTxFifo[] = +{ + SPIS_O_TXFMEM0, SPIS_O_TXFMEM1, SPIS_O_TXFMEM2, SPIS_O_TXFMEM3, SPIS_O_TXFMEM4, + SPIS_O_TXFMEM5, SPIS_O_TXFMEM6, SPIS_O_TXFMEM7, SPIS_O_TXFMEM8, SPIS_O_TXFMEM9, + SPIS_O_TXFMEM10, SPIS_O_TXFMEM11, SPIS_O_TXFMEM12, SPIS_O_TXFMEM13, + SPIS_O_TXFMEM14, SPIS_O_TXFMEM15 +}; + +//***************************************************************************** +// +// This is the mapping between an RX Fifo index and the corresponding +// register. +// +//***************************************************************************** +static const uint32_t g_pui32SPISRxFifo[] = +{ + SPIS_O_RXFMEM0, SPIS_O_RXFMEM1, SPIS_O_RXFMEM2, SPIS_O_RXFMEM3, SPIS_O_RXFMEM4, + SPIS_O_RXFMEM5, SPIS_O_RXFMEM6, SPIS_O_RXFMEM7, SPIS_O_RXFMEM8, SPIS_O_RXFMEM9, + SPIS_O_RXFMEM10, SPIS_O_RXFMEM11, SPIS_O_RXFMEM12, SPIS_O_RXFMEM13, + SPIS_O_RXFMEM14, SPIS_O_RXFMEM15 +}; +//***************************************************************************** +// +//! Puts a data element into the SPIS transmit FIFO +// +//***************************************************************************** +void +SPISDataPut(uint32_t ui32Data) +{ + // + // Wait until there is space. + // + while(HWREG(SPIS_BASE + SPIS_O_TXFSTAT) & SPIS_TXFSTAT_FULL) + { + } + + // + // Write the data to the SPIS Tx Fifo. + // + HWREG(SPIS_BASE + SPIS_O_TXFPUSH) = ui32Data; +} +//***************************************************************************** +// +//! Get a specific value in the Tx Fifo +// +//***************************************************************************** +uint32_t +SPISTxGetValue(uint32_t ui32Index) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(ui32Index < TX_FIFO_SIZE); + + // + // Find the correct register. + // + ui32Reg = g_pui32SPISTxFifo[ui32Index]; + + // + // Return the value of the TX Fifo at the specified index. + // + return HWREG(SPIS_BASE + ui32Reg); +} +//***************************************************************************** +// +//! Gets a data element from the SPIS Rx FIFO +// +//***************************************************************************** +void +SPISDataGet(uint32_t *pui32Data) +{ + // + // Wait until there is data to be read. + // + while(!(HWREG(SPIS_BASE + SPIS_O_RXFSTAT) & SPIS_RXFSTAT_NOT_EMPTY)) + { + } + + // + // Read data from SPIS Rx Fifo. + // + *pui32Data = HWREG(SPIS_BASE + SPIS_O_RXFPOP); +} +//***************************************************************************** +// +//! Get a specific value in the Rx Fifo +// +//***************************************************************************** +uint32_t +SPISRxGetValue(uint32_t ui32Index) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(ui32Index < RX_FIFO_SIZE); + + // + // Find the correct register. + // + ui32Reg = g_pui32SPISRxFifo[ui32Index]; + + // + // Return the value of the RX Fifo at the specified index. + // + return HWREG(SPIS_BASE + ui32Reg); +} +//***************************************************************************** +// +//! Gets the current interrupt status +//! +//! \param bMasked is \b false if the raw interrupt status is required or +//! \b true if the masked interrupt status is required. +//! +//! This function returns the interrupt status for the SPIS module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status consisting of a bitwise OR value +//! of the available interrupts sources as described in \b SPISIntEnable(). +// +//***************************************************************************** +uint32_t +SPISIntStatus(bool bMasked) +{ + uint32_t ui32IntStatus, ui32Tmp; + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + ui32Tmp = HWREG(SPIS_BASE + SPIS_O_TXFFLAGSCLRN); + ui32IntStatus = ui32Tmp & HWREG(SPIS_BASE + SPIS_O_TXFFLAGSMASK); + ui32Tmp = HWREG(SPIS_BASE + SPIS_O_RXFFLAGSCLRN); + ui32IntStatus |= (ui32Tmp & HWREG(SPIS_BASE + SPIS_O_RXFFLAGSMASK)) << 8; + ui32Tmp = HWREG(SPIS_BASE + SPIS_O_GPFLAGS); + ui32IntStatus |= (ui32Tmp & HWREG(SPIS_BASE + SPIS_O_GPFLAGSMASK)) << 16; + } + else + { + ui32IntStatus = HWREG(SPIS_BASE + SPIS_O_TXFFLAGSCLRN) & SPIS_TX_MASK; + ui32IntStatus |= (HWREG(SPIS_BASE + SPIS_O_RXFFLAGSCLRN) << 8) & SPIS_RX_MASK; + ui32IntStatus |= (HWREG(SPIS_BASE + SPIS_O_GPFLAGS) << 16) & SPIS_GP_MASK; + } + return ui32IntStatus; +} +//! @} +//! \\addtogroup ssi_api +//! @{ +//***************************************************************************** +// +//! Configures the synchronous serial port +// +//***************************************************************************** +void +SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, uint32_t ui32DataWidth) +{ + uint32_t ui32MaxBitRate; + uint32_t ui32RegVal; + uint32_t ui32PreDiv; + uint32_t ui32SCR; + uint32_t ui32SPH_SPO; + + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || + (ui32Protocol == SSI_FRF_MOTO_MODE_1) || + (ui32Protocol == SSI_FRF_MOTO_MODE_2) || + (ui32Protocol == SSI_FRF_MOTO_MODE_3) || + (ui32Protocol == SSI_FRF_TI) || + (ui32Protocol == SSI_FRF_NMW)); + ASSERT((ui32Mode == SSI_MODE_MASTER) || + (ui32Mode == SSI_MODE_SLAVE) || + (ui32Mode == SSI_MODE_SLAVE_OD)); + ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) || + ((ui32Mode != SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 12)))); + ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); + ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); + + // + // Set the mode. + // + ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; + + // + // Set the clock predivider. + // + ui32MaxBitRate = ui32SSIClk / ui32BitRate; + ui32PreDiv = 0; + do + { + ui32PreDiv += 2; + ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; + } + while(ui32SCR > 255); + HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; + + // + // Set protocol and clock rate. + // + ui32SPH_SPO = (ui32Protocol & 3) << 6; + ui32Protocol &= SSI_CR0_FRF_M; + ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | (ui32DataWidth - 1); + HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; +} +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO +// +//***************************************************************************** +void +SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // + // Wait until there is space. + // + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // + // Write the data to the SSI. + // + HWREG(ui32Base + SSI_O_DR) = ui32Data; +} +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO +// +//***************************************************************************** +int32_t +SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // + // Check for space to write. + // + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ui32Base + SSI_O_DR) = ui32Data; + return(1); + } + else + { + return(0); + } +} +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO +// +//***************************************************************************** +void +SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ui32Base)); + + // + // Wait until there is data to be read. + // + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // + // Read data from SSI. + // + *pui32Data = HWREG(ui32Base + SSI_O_DR); +} +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pui32Data is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! This function gets received data from the receive FIFO of the specified SSI +//! module and places that data into the location specified by the \e ui32Data +//! parameter. If there is no data in the FIFO, then this function returns a +//! zero. +//! +//! \note Only the lower N bits of the value written to \e pui32Data contain +//! valid data, where N is the data width as configured by \sa +//! SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to \e pui32Data +//! contain valid data. +//! +//! \return Returns the number of elements read from the SSI receive FIFO. +// +//***************************************************************************** +int32_t +SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) +{ + // + // Check the arguments. + // + ASSERT(SSIBaseValid(ui32Base)); + + // + // Check for data to read. + // + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) + { + *pui32Data = HWREG(ui32Base + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} +//! @} +//! \\addtogroup timer_api +//! @{ +//***************************************************************************** +// +//! Configures the timer(s) +// +//***************************************************************************** +void +TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || + (ui32Config == TIMER_CFG_ONE_SHOT_UP) || + (ui32Config == TIMER_CFG_PERIODIC) || + (ui32Config == TIMER_CFG_PERIODIC_UP) || + (ui32Config == TIMER_CFG_RTC) || + ((ui32Config & 0xFF000000) == TIMER_CFG_SPLIT_PAIR)); + ASSERT(((ui32Config & 0xFF000000) != TIMER_CFG_SPLIT_PAIR) || + ((((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PWM)) && + (((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PWM)))); + + // + // Disable the timers. + // + HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); + + // + // Set the global timer configuration. + // + HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24; + + // + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + // + HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE; + HWREG(ui32Base + GPT_O_TBMR) = + ((ui32Config >> 8) & 0xFF) | GPT_TBMR_TBPWMIE; +} +//***************************************************************************** +// +//! Controls the output level +// +//***************************************************************************** +void +TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Set the output levels as requested. + // + ui32Timer &= GPT_CTL_TAPWML | GPT_CTL_TBPWML; + HWREG(ui32Base + GPT_O_CTL) = (bInvert ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & + ~(ui32Timer))); +} +//***************************************************************************** +// +//! Enables or disables the ADC trigger output +// +//***************************************************************************** +void +TimerTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bEnable) +{ + uint32_t ui32Val; + + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Determine which bits to set or clear in GPTM_ADCEV. + // + ui32Val = (GPT_ADCEV_TATOADCEN | GPT_ADCEV_TBTOADCEN); + ui32Val &= ui32Timer; + + // + // Write the GPTM ADC Event register to enable or disable the trigger. + // to the ADC. + // + HWREG(ui32Base + GPT_O_ADCEV) = (bEnable ? + (HWREG(ui32Base + GPT_O_ADCEV) | ui32Val) : + (HWREG(ui32Base + GPT_O_ADCEV) & + ~(ui32Val))); + + // + // Set the trigger output as requested. + // Set the ADC trigger output as requested. + // + ui32Timer &= GPT_CTL_TAOTE | GPT_CTL_TBOTE; + HWREG(ui32Base + GPT_O_CTL) = (bEnable ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & + ~(ui32Timer))); +} +//***************************************************************************** +// +//! Controls the stall handling +// +//***************************************************************************** +void +TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Set the stall mode. + // + ui32Timer &= GPT_CTL_TASTALL | GPT_CTL_TBSTALL; + HWREG(ui32Base + GPT_O_CTL) = (bStall ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer))); +} +//***************************************************************************** +// +//! Controls the wait on trigger handling +// +//***************************************************************************** +void +TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait) +{ + // + // Check the arguments. + // + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // + // Set the wait on trigger mode for timer A. + // + if(ui32Timer & TIMER_A) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAWOT; + } + else + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAWOT); + } + } + + // + // Set the wait on trigger mode for timer B. + // + if(ui32Timer & TIMER_B) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBWOT; + } + else + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBWOT); + } + } +} +//! @} +//! \\addtogroup trng_api +//! @{ +//***************************************************************************** +// +//! Configure the true random number generator +// +//***************************************************************************** +void +TRNGConfigure(uint32_t ui32MinSamplesPerCycle, + uint32_t ui32MaxSamplesPerCycle, + uint32_t ui32ClocksPerSample) +{ + uint32_t ui32Val; + + // + // Make sure the TRNG is disabled. + // + ui32Val = HWREG(TRNG_BASE + TRNG_O_CTL) & ~TRNG_CTL_TRNG_EN; + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // + // Configure the startup number of samples. + // + ui32Val &= ~TRNG_CTL_STARTUP_CYCLES_M; + ui32Val |= ((ui32MaxSamplesPerCycle >> 8) & 0xFFFF) << 16; + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // + // Configure the minimum and maximum number of samples pr generated number + // and the number of clocks per sample. + // + HWREG(TRNG_BASE + TRNG_O_CFG0) = + (((ui32MaxSamplesPerCycle >> 8) & 0xFFFF) << 16) | + ((ui32ClocksPerSample & 0xFF) << 8) | + ((ui32MinSamplesPerCycle >> 6) & 0xFF); +} +//***************************************************************************** +// +//! Get a random number from the generator +// +//***************************************************************************** +uint32_t +TRNGNumberGet(uint32_t ui32Word) +{ + uint32_t ui32RandomNumber; + + // + // Check the arguments. + // + ASSERT((ui32Word == TRNG_HI_WORD) || + (ui32Word == TRNG_LOW_WORD)); + + // + // Return the right requested part of the generated number. + // + if(ui32Word == TRNG_HI_WORD) + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT1); + } + else + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT0); + } + + // + // Initiate generation of new number. + // + HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1; + + // + // Return the random number. + // + return ui32RandomNumber; +} +//! @} +//! \\addtogroup uart_api +//! @{ +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated +// +//***************************************************************************** +void +UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel) +{ + uint32_t ui32Temp; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Read the FIFO level register. + // + ui32Temp = HWREG(ui32Base + UART_O_IFLS); + + // + // Extract the transmit and receive FIFO levels. + // + *pui32TxLevel = ui32Temp & UART_IFLS_TXSEL_M; + *pui32RxLevel = ui32Temp & UART_IFLS_RXSEL_M; +} +//***************************************************************************** +// +//! Sets the configuration of a UART +// +//***************************************************************************** +void +UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config) +{ + uint32_t ui32Div; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + ASSERT(ui32Baud != 0); + + // + // Stop the UART. + // + UARTDisable(ui32Base); + + // + // Compute the fractional baud rate divider. + // + ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; + + // + // Set the baud rate. + // + HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; + HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; + + // + // Set parity, data length, and number of stop bits. + // + HWREG(ui32Base + UART_O_LCRH) = ui32Config; + + // + // Clear the flags register. + // + HWREG(ui32Base + UART_O_FR) = 0; +} +//***************************************************************************** +// +//! Gets the current configuration of a UART +// +//***************************************************************************** +void +UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config) +{ + uint32_t ui32Int, ui32Frac; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Compute the baud rate. + // + ui32Int = HWREG(ui32Base + UART_O_IBRD); + ui32Frac = HWREG(ui32Base + UART_O_FBRD); + *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); + + // + // Get the parity, data length, and number of stop bits. + // + *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | + UART_LCRH_EPS | UART_LCRH_PEN)); +} +//***************************************************************************** +// +//! Disables transmitting and receiving +// +//***************************************************************************** +void +UARTDisable(uint32_t ui32Base) +{ + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Wait for end of TX. + // + while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) + { + } + + // + // Disable the FIFO. + // + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); + + // + // Disable the UART. + // + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} +//***************************************************************************** +// +//! Receives a character from the specified port +// +//***************************************************************************** +int32_t +UARTCharGetNonBlocking(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // See if there are any characters in the receive FIFO. + // + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) + { + // + // Read and return the next character. + // + return(HWREG(ui32Base + UART_O_DR)); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } +} +//***************************************************************************** +// +//! Waits for a character from the specified port +// +//***************************************************************************** +int32_t +UARTCharGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Wait until a char is available. + // + while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) + { + } + + // + // Now get the character. + // + return(HWREG(ui32Base + UART_O_DR)); +} +//***************************************************************************** +// +//! Sends a character to the specified port +// +//***************************************************************************** +bool +UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // See if there is space in the transmit FIFO. + // + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) + { + // + // Write this character to the transmit FIFO. + // + HWREG(ui32Base + UART_O_DR) = ui8Data; + + // + // Success. + // + return(true); + } + else + { + // + // There is no space in the transmit FIFO, so return a failure. + // + return(false); + } +} +//***************************************************************************** +// +//! Waits to send a character from the specified port +// +//***************************************************************************** +void +UARTCharPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Wait until space is available. + // + while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) + { + } + + // + // Send the char. + // + HWREG(ui32Base + UART_O_DR) = ui8Data; +} +//! @} +//! \\addtogroup udma_api +//! @{ +//***************************************************************************** +// +//! Enables attributes of a uDMA channel +// +//***************************************************************************** +void +uDMAChannelAttributeEnable(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32Attr) +{ + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // Set the useburst bit for this channel if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_SETBURST) = 1 << ui32ChannelNum; + } + + // + // Set the alternate control select bit for this channel, + // if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // + // Set the high priority bit for this channel, if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // + // Set the request mask bit for this channel, if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_SETREQMASK) = 1 << ui32ChannelNum; + } +} +//***************************************************************************** +// +//! Disables attributes of an uDMA channel +// +//***************************************************************************** +void +uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32Attr) +{ + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // + // Clear the useburst bit for this channel if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_CLEARBURST) = 1 << ui32ChannelNum; + } + + // + // Clear the alternate control select bit for this channel, if set in + // ululAttr. + // + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // + // Clear the high priority bit for this channel, if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // + // Clear the request mask bit for this channel, if set in ui32Attr. + // + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_CLEARREQMASK) = 1 << ui32ChannelNum; + } +} +//***************************************************************************** +// +//! Gets the enabled attributes of a uDMA channel +// +//***************************************************************************** +uint32_t +uDMAChannelAttributeGet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + uint32_t ui32Attr = 0; + + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // + // Check to see if useburst bit is set for this channel. + // + if(HWREG(ui32Base + UDMA_O_SETBURST) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_USEBURST; + } + + // + // Check to see if the alternate control bit is set for this channel. + // + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_ALTSELECT; + } + + // + // Check to see if the high priority bit is set for this channel. + // + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // + // Check to see if the request mask bit is set for this channel. + // + if(HWREG(ui32Base + UDMA_O_SETREQMASK) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_REQMASK; + } + + // + // Return the configuration flags. + // + return(ui32Attr); +} +//***************************************************************************** +// +//! Sets the control parameters for a uDMA channel control structure +// +//***************************************************************************** +void +uDMAChannelControlSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, + uint32_t ui32Control) +{ + tDMAControlTable *pControlTable; + + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + // + pControlTable[ui32ChannelStructIndex].ui32Control = + ((pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_DST_INC_M | + UDMA_SRC_INC_M | + UDMA_SIZE_M | + UDMA_ARB_M | + UDMA_NEXT_USEBURST)) | + ui32Control); +} +//***************************************************************************** +// +//! Sets the transfer parameters for a uDMA channel control structure +// +//***************************************************************************** +void +uDMAChannelTransferSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, + uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, + uint32_t ui32TransferSize) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + uint32_t ui32Inc; + uint32_t ui32BufferBytes; + + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((uint32_t)pvSrcAddr >= SRAM_BASE); + ASSERT((uint32_t)pvDstAddr >= SRAM_BASE); + ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= UDMA_XFER_SIZE_MAX)); + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // + // Get the current control word value and mask off the mode and size + // fields. + // + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // + // Adjust the mode if the alt control structure is selected. + // + if(ui32ChannelStructIndex & UDMA_ALT_SELECT) + { + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Mode |= UDMA_MODE_ALT_SELECT; + } + } + + // + // Set the transfer size and mode in the control word (but don't write the + // control word yet as it could kick off a transfer). + // + ui32Control |= ui32Mode | ((ui32TransferSize - 1) << UDMA_XFER_SIZE_S); + + // + // Get the address increment value for the source, from the control word. + // + ui32Inc = (ui32Control & UDMA_SRC_INC_M); + + // + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + // + if(ui32Inc != UDMA_SRC_INC_NONE) + { + ui32Inc = ui32Inc >> UDMA_SRC_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - 1); + } + + // + // Load the source ending address into the control block. + // + pControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; + + // + // Get the address increment value for the destination, from the control + // word. + // + ui32Inc = ui32Control & UDMA_DST_INC_M; + + // + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + // + if(ui32Inc != UDMA_DST_INC_NONE) + { + // + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer needs to point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + // + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + pvDstAddr = + (void *)&pControlTable[ui32ChannelStructIndex | + UDMA_ALT_SELECT].ui32Spare; + } + // + // Not a scatter-gather transfer, calculate end pointer normally. + // + else + { + ui32Inc = ui32Inc >> UDMA_DST_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); + } + } + + // + // Load the destination ending address into the control block. + // + pControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; + + // + // Write the new control word value. + // + pControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; +} +//***************************************************************************** +// +//! Configures a uDMA channel for scatter-gather mode +// +//***************************************************************************** +void +uDMAChannelScatterGatherSet(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32TaskCount, void *pvTaskList, + uint32_t ui32IsPeriphSG) +{ + tDMAControlTable *pControlTable; + tDMAControlTable *pTaskTable; + + // + // Check the parameters. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(pvTaskList != 0); + ASSERT(ui32TaskCount <= UDMA_XFER_SIZE_MAX); + ASSERT(ui32TaskCount != 0); + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // + // Get a handy pointer to the task list. + // + pTaskTable = (tDMAControlTable *)pvTaskList; + + // + // Compute the ending address for the source pointer. This will be the + // last element of the last task in the task table. + // + pControlTable[ui32ChannelNum].pvSrcEndAddr = + &pTaskTable[ui32TaskCount - 1].ui32Spare; + + // + // Compute the ending address for the destination pointer. This will be + // the end of the alternate structure for this channel. + // + pControlTable[ui32ChannelNum].pvDstEndAddr = + &pControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; + + // + // Compute the control word. Most configurable items are fixed for + // scatter-gather. Item and increment sizes are all 32-bit and arb + // size must be 4. The count is the number of items in the task list + // times 4 (4 words per task). + // + pControlTable[ui32ChannelNum].ui32Control = + (UDMA_DST_INC_32 | UDMA_SRC_INC_32 | + UDMA_SIZE_32 | UDMA_ARB_4 | + (((ui32TaskCount * 4) - 1) << UDMA_XFER_SIZE_S) | + (ui32IsPeriphSG ? UDMA_MODE_PER_SCATTER_GATHER : + UDMA_MODE_MEM_SCATTER_GATHER)); + + // + // Scatter-gather operations can leave the alt bit set. So if doing + // back to back scatter-gather transfers, the second attempt may not + // work correctly because the alt bit is set. Therefore, clear the + // alt bit here to ensure that it is always cleared before a new SG + // transfer is started. + // + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; + +} +//***************************************************************************** +// +//! Gets the current transfer size for a uDMA channel control structure +// +//***************************************************************************** +uint32_t +uDMAChannelSizeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // + // Get the current control word value and mask off all but the size field + // and the mode field. + // + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + (UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // + // If the size field and mode field are 0 then the transfer is finished + // and there are no more items to transfer. + // + if(ui32Control == 0) + { + return(0); + } + + // + // Otherwise, if either the size field or more field is non-zero, then + // not all the items have been transferred. + // + else + { + // + // Shift the size field and add one, then return to user. + // + return((ui32Control >> UDMA_XFER_SIZE_S) + 1); + } +} +//***************************************************************************** +// +//! Gets the transfer mode for a uDMA channel control structure +// +//***************************************************************************** +uint32_t +uDMAChannelModeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // + // Check the arguments. + // + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // + // Get the base address of the control table. + // + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // + // Get the current control word value and mask off all but the mode field. + // + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + UDMA_MODE_M); + + // + // Check if scatter/gather mode, and if so, mask off the alt bit. + // + if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || + ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Control &= ~UDMA_MODE_ALT_SELECT; + } + + // + // Return the mode to the caller. + // + return(ui32Control); +} +//! @} +//! \\addtogroup vims_api +//! @{ +//***************************************************************************** +// +//! Configures the VIMS. +// +//***************************************************************************** +void +VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG); + if(bRoundRobin) + { + ui32Reg |= VIMS_CTL_ARB_CFG; + } + if(bPrefetch) + { + ui32Reg |= VIMS_CTL_PREF_EN; + } + + // + // Set the Arbitration and prefetch mode. + // + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} +//***************************************************************************** +// +//! Set the operational mode of the VIMS +// +//***************************************************************************** +void +VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(VIMSBaseValid(ui32Base)); + + ASSERT((ui32Mode == VIMS_MODE_INVALIDATE) || + (ui32Mode == VIMS_MODE_DISABLED) || + (ui32Mode == VIMS_MODE_ENABLED) || + (ui32Mode == VIMS_MODE_OFF) || + (ui32Mode == VIMS_MODE_SPLIT)); + + // + // Set the mode. + // + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~VIMS_CTL_MODE_M; + ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M); + + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} +//***************************************************************************** +// +//! Get the current operational mode of the VIMS. +// +//***************************************************************************** +uint32_t +VIMSModeGet(uint32_t ui32Base) +{ + uint32_t ui32Reg; + + // + // Check the arguments. + // + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_STAT); + if(ui32Reg & VIMS_STAT_INV) + { + return (VIMS_MODE_INVALIDATE); + } + else + { + return (ui32Reg & VIMS_STAT_MODE_M); + } +} +//! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rom/driverlib.elf b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rom/driverlib.elf new file mode 100644 index 0000000..95e00d4 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rom/driverlib.elf differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rom/readme.txt b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rom/readme.txt new file mode 100644 index 0000000..baec5e2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rom/readme.txt @@ -0,0 +1,32 @@ +Debugging sessions in IAR Embedded Workbench (IAR) and Code Composer Studio (CCS) +can load symbol information covering the code in ROM. +Symbols are loaded by selecting the ELF files found in the same folder as this +readme.txt file. +In addition the source code for the driverlib functions in ROM is found in the +driverlib.c file in this folder. + +Loading ROM code symbols in CCS debug session: +- Start a debug session in your project +- Select Run > Load > Add Symbols to create additional symbols +- Browse to and select each ELF file in this folder in the 'Program file' field +- Set the value of 0 in the 'Code offset' field for each ELF file +- If you enter a driverlib function in ROM during your debuging session and + get this information: + 'Can't find a source file at "..//driverlib.c"' + you can navigate to the driverlib.c file in this folder by selecting + the 'Locate File..' button. + +Loading ROM code symbols for use in IAR debug session: +- In your project select the following before starting debug session: + Project > Options.. > Debugger and then select the 'Images'-tab +- In the 'Images'-tab do the following for each of the ELF files + located in the same folder as this reame.txt file: + -- Select the 'Download extra image' box + -- Browse to the ELF file in the 'Path:' field + -- Set the value of 0 in the 'Offset:' field + -- Select the 'Debug info only' box +- If you during a debug session enters a driverlib function in ROM you will + be notified by this message: + 'Could not find following file: ..//driverlib.c' + Select the browse button and select the driverlib.c file located in this + folder. diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/startup_files/ccfg.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/startup_files/ccfg.c new file mode 100644 index 0000000..b4f3d22 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/startup_files/ccfg.c @@ -0,0 +1,501 @@ +/****************************************************************************** +* Filename: ccfg.c +* Revised: $Date: 2017-08-08 15:34:36 +0200 (ti, 08 aug 2017) $ +* Revision: $Revision: 17873 $ +* +* Description: Customer Configuration for CC26x0 device family (HW rev 2). +* +* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __CCFC_C__ +#define __CCFC_C__ + +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ccfg_simple_struct.h" + +//***************************************************************************** +// +// Introduction +// +// This file contains fields used by Boot ROM, startup code, and SW radio +// stacks to configure chip behavior. +// +// Fields are documented in more details in hw_ccfg.h and CCFG.html in +// DriverLib documentation (doc_overview.html -> CPU Domain Memory Map -> CCFG). +// +// PLEASE NOTE: +// It is not recommended to do modifications inside the ccfg.c file. +// This file is part of the CoreSDK release and future releases may have +// important modifications and new fields added without notice. +// The recommended method to modify the CCFG settings is to have a separate +// .c file that defines the specific CCFG values to be +// overridden and then include the TI provided ccfg.c at the very end, +// giving default values for non-overriden settings. +// +// Example: +// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC +// //---- Use default values for all others ---- +// #include "/source/ti/devices//startup_files/ccfg.c" +// +//***************************************************************************** + +//***************************************************************************** +// +// Set the values of the individual bit fields. +// +//***************************************************************************** + +//##################################### +// Alternative DC/DC settings +//##################################### + +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0 // Alternative DC/DC setting enabled +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x1 // Alternative DC/DC setting disabled +#endif + +#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0x8 // 2.25V +#endif + +#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0 // Disable +// #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x1 // Enable +#endif + +#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x2 // 39mA +#endif + +//##################################### +// XOSC override settings +//##################################### + +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x0 // Enable override +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1 // Disable override +#endif + +#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT +#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 0x0 // Delta = 0 +#endif + +#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET +#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0 // Delta = 0 +#endif + +#ifndef SET_CCFG_MODE_CONF_1_XOSC_MAX_START +#define SET_CCFG_MODE_CONF_1_XOSC_MAX_START 0x10 // 1600us +#endif + +//##################################### +// Power settings +//##################################### + +#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA +#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF // Signed delta value +1 to apply to the VDDR_TRIM_SLEEP target (0xF=-1=default=no compensation) +#endif + +#ifndef SET_CCFG_MODE_CONF_DCDC_RECHARGE +#define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x0 // Use the DC/DC during recharge in powerdown +// #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x1 // Do not use the DC/DC during recharge in powerdown +#endif + +#ifndef SET_CCFG_MODE_CONF_DCDC_ACTIVE +#define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x0 // Use the DC/DC during active mode +// #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x1 // Do not use the DC/DC during active mode +#endif + +#ifndef SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL +// #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x0 // VDDS BOD level is 2.0V +#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // VDDS BOD level is 1.8V (or 1.65V for external regulator mode) +#endif + +#ifndef SET_CCFG_MODE_CONF_VDDR_CAP +#define SET_CCFG_MODE_CONF_VDDR_CAP 0x3A // Unsigned 8-bit integer representing the min. decoupling capacitance on VDDR in units of 100nF +#endif + +#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC +#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1 // Temperature compensation on VDDR sleep trim disabled (default) +// #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x0 // Temperature compensation on VDDR sleep trim enabled +#endif + +//##################################### +// Clock settings +//##################################### + +#ifndef SET_CCFG_MODE_CONF_SCLK_LF_OPTION +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x0 // LF clock derived from High Frequency XOSC +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x1 // External LF clock +#define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC +#endif + +#ifndef SET_CCFG_MODE_CONF_XOSC_CAP_MOD +// #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x0 // Apply cap-array delta +#define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x1 // Don't apply cap-array delta +#endif + +#ifndef SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA +#define SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF // Signed 8-bit value, directly modifying trimmed XOSC cap-array value +#endif + +#ifndef SET_CCFG_EXT_LF_CLK_DIO +#define SET_CCFG_EXT_LF_CLK_DIO 0x01 // DIO number if using external LF clock +#endif + +#ifndef SET_CCFG_EXT_LF_CLK_RTC_INCREMENT +#define SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 0x800000 // RTC increment representing the external LF clock frequency +#endif + +//##################################### +// Special HF clock source setting +//##################################### +#ifndef SET_CCFG_MODE_CONF_XOSC_FREQ +// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x1 // Use HPOSC as HF source (if executing on a HPOSC chip, otherwise using default (=0x3)) +// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x2 // HF source is a 48 MHz xtal +#define SET_CCFG_MODE_CONF_XOSC_FREQ 0x3 // HF source is a 24 MHz xtal (default) +#endif + +//##################################### +// Bootloader settings +//##################################### + +#ifndef SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE +#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00 // Disable ROM boot loader +// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader +#endif + +#ifndef SET_CCFG_BL_CONFIG_BL_LEVEL +// #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x0 // Active low to open boot loader backdoor +#define SET_CCFG_BL_CONFIG_BL_LEVEL 0x1 // Active high to open boot loader backdoor +#endif + +#ifndef SET_CCFG_BL_CONFIG_BL_PIN_NUMBER +#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0xFF // DIO number for boot loader backdoor +#endif + +#ifndef SET_CCFG_BL_CONFIG_BL_ENABLE +// #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 // Enabled boot loader backdoor +#define SET_CCFG_BL_CONFIG_BL_ENABLE 0xFF // Disabled boot loader backdoor +#endif + +//##################################### +// Debug access settings +//##################################### + +#ifndef SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE +#define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0x00 // Disable unlocking of TI FA option. +// #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0xC5 // Enable unlocking of TI FA option with the unlock code +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE +// #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0x00 // Access disabled +#define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE +// #define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00 // Access disabled +#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +//##################################### +// Alternative IEEE 802.15.4 MAC address +//##################################### +#ifndef SET_CCFG_IEEE_MAC_0 +#define SET_CCFG_IEEE_MAC_0 0xFFFFFFFF // Bits [31:0] +#endif + +#ifndef SET_CCFG_IEEE_MAC_1 +#define SET_CCFG_IEEE_MAC_1 0xFFFFFFFF // Bits [63:32] +#endif + +//##################################### +// Alternative BLE address +//##################################### +#ifndef SET_CCFG_IEEE_BLE_0 +#define SET_CCFG_IEEE_BLE_0 0xFFFFFFFF // Bits [31:0] +#endif + +#ifndef SET_CCFG_IEEE_BLE_1 +#define SET_CCFG_IEEE_BLE_1 0xFFFFFFFF // Bits [63:32] +#endif + +//##################################### +// Flash erase settings +//##################################### + +#ifndef SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N +// #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x0 // Any chip erase request detected during boot will be ignored +#define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x1 // Any chip erase request detected during boot will be performed by the boot FW +#endif + +#ifndef SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N +// #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x0 // Disable the boot loader bank erase function +#define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x1 // Enable the boot loader bank erase function +#endif + +//##################################### +// Flash image valid +//##################################### +#ifndef SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID +#define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 0x00000000 // Flash image is valid +// #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID // Flash image is invalid. ROM boot loader is called. +#endif + +//##################################### +// Flash sector write protection +//##################################### +#ifndef SET_CCFG_CCFG_PROT_31_0 +#define SET_CCFG_CCFG_PROT_31_0 0xFFFFFFFF +#endif + +#ifndef SET_CCFG_CCFG_PROT_63_32 +#define SET_CCFG_CCFG_PROT_63_32 0xFFFFFFFF +#endif + +#ifndef SET_CCFG_CCFG_PROT_95_64 +#define SET_CCFG_CCFG_PROT_95_64 0xFFFFFFFF +#endif + +#ifndef SET_CCFG_CCFG_PROT_127_96 +#define SET_CCFG_CCFG_PROT_127_96 0xFFFFFFFF +#endif + +//##################################### +// Select between cache or GPRAM +//##################################### +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0 // Cache is disabled and GPRAM is available at 0x11000000-0x11001FFF +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1 // Cache is enabled and GPRAM is disabled (unavailable) +#endif + +//##################################### +// Select TCXO +//##################################### +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1 // Disable TCXO +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x0 // Enable TXCO +#endif + +//***************************************************************************** +// +// CCFG values that should not be modified. +// +//***************************************************************************** +#define SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058 +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS (CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M >> CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S) + +#define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x1 +#define SET_CCFG_MODE_CONF_RTC_COMP 0x1 +#define SET_CCFG_MODE_CONF_HF_COMP 0x1 + +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 0xFF +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 0xFF +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 0xFF +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 0xFF + +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 0xFF +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 0xFF +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 0xFF +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 0xFF + +#define SET_CCFG_RTC_OFFSET_RTC_COMP_P0 0xFFFF +#define SET_CCFG_RTC_OFFSET_RTC_COMP_P1 0xFF +#define SET_CCFG_RTC_OFFSET_RTC_COMP_P2 0xFF + +#define SET_CCFG_FREQ_OFFSET_HF_COMP_P0 0xFFFF +#define SET_CCFG_FREQ_OFFSET_HF_COMP_P1 0xFF +#define SET_CCFG_FREQ_OFFSET_HF_COMP_P2 0xFF + +//***************************************************************************** +// +// Concatenate bit fields to words. +// DO NOT EDIT! +// +//***************************************************************************** +#define DEFAULT_CCFG_EXT_LF_CLK ( \ + ((((uint32_t)( SET_CCFG_EXT_LF_CLK_DIO )) << CCFG_EXT_LF_CLK_DIO_S ) | ~CCFG_EXT_LF_CLK_DIO_M ) & \ + ((((uint32_t)( SET_CCFG_EXT_LF_CLK_RTC_INCREMENT )) << CCFG_EXT_LF_CLK_RTC_INCREMENT_S ) | ~CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) ) + +#define DEFAULT_CCFG_MODE_CONF_1 ( \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN )) << CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN )) << CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK )) << CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT )) << CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET )) << CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_XOSC_MAX_START )) << CCFG_MODE_CONF_1_XOSC_MAX_START_S ) | ~CCFG_MODE_CONF_1_XOSC_MAX_START_M ) ) + +#define DEFAULT_CCFG_SIZE_AND_DIS_FLAGS ( \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG )) << CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS )) << CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) ) + +#define DEFAULT_CCFG_MODE_CONF ( \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_RECHARGE )) << CCFG_MODE_CONF_DCDC_RECHARGE_S ) | ~CCFG_MODE_CONF_DCDC_RECHARGE_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_ACTIVE )) << CCFG_MODE_CONF_DCDC_ACTIVE_S ) | ~CCFG_MODE_CONF_DCDC_ACTIVE_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_EXT_LOAD )) << CCFG_MODE_CONF_VDDR_EXT_LOAD_S ) | ~CCFG_MODE_CONF_VDDR_EXT_LOAD_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL )) << CCFG_MODE_CONF_VDDS_BOD_LEVEL_S ) | ~CCFG_MODE_CONF_VDDS_BOD_LEVEL_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_SCLK_LF_OPTION )) << CCFG_MODE_CONF_SCLK_LF_OPTION_S ) | ~CCFG_MODE_CONF_SCLK_LF_OPTION_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_RTC_COMP )) << CCFG_MODE_CONF_RTC_COMP_S ) | ~CCFG_MODE_CONF_RTC_COMP_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_FREQ )) << CCFG_MODE_CONF_XOSC_FREQ_S ) | ~CCFG_MODE_CONF_XOSC_FREQ_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAP_MOD )) << CCFG_MODE_CONF_XOSC_CAP_MOD_S ) | ~CCFG_MODE_CONF_XOSC_CAP_MOD_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_HF_COMP )) << CCFG_MODE_CONF_HF_COMP_S ) | ~CCFG_MODE_CONF_HF_COMP_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA )) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) | ~CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_CAP )) << CCFG_MODE_CONF_VDDR_CAP_S ) | ~CCFG_MODE_CONF_VDDR_CAP_M ) ) + +#define DEFAULT_CCFG_VOLT_LOAD_0 ( \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M ) ) + +#define DEFAULT_CCFG_VOLT_LOAD_1 ( \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M ) ) + +#define DEFAULT_CCFG_RTC_OFFSET ( \ + ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P0 )) << CCFG_RTC_OFFSET_RTC_COMP_P0_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P0_M ) & \ + ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P1 )) << CCFG_RTC_OFFSET_RTC_COMP_P1_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P1_M ) & \ + ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P2 )) << CCFG_RTC_OFFSET_RTC_COMP_P2_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P2_M ) ) + +#define DEFAULT_CCFG_FREQ_OFFSET ( \ + ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P0 )) << CCFG_FREQ_OFFSET_HF_COMP_P0_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P0_M ) & \ + ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P1 )) << CCFG_FREQ_OFFSET_HF_COMP_P1_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P1_M ) & \ + ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P2 )) << CCFG_FREQ_OFFSET_HF_COMP_P2_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P2_M ) ) + +#define DEFAULT_CCFG_IEEE_MAC_0 SET_CCFG_IEEE_MAC_0 +#define DEFAULT_CCFG_IEEE_MAC_1 SET_CCFG_IEEE_MAC_1 +#define DEFAULT_CCFG_IEEE_BLE_0 SET_CCFG_IEEE_BLE_0 +#define DEFAULT_CCFG_IEEE_BLE_1 SET_CCFG_IEEE_BLE_1 + +#define DEFAULT_CCFG_BL_CONFIG ( \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE )) << CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S ) | ~CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_LEVEL )) << CCFG_BL_CONFIG_BL_LEVEL_S ) | ~CCFG_BL_CONFIG_BL_LEVEL_M ) & \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_PIN_NUMBER )) << CCFG_BL_CONFIG_BL_PIN_NUMBER_S ) | ~CCFG_BL_CONFIG_BL_PIN_NUMBER_M ) & \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_ENABLE )) << CCFG_BL_CONFIG_BL_ENABLE_S ) | ~CCFG_BL_CONFIG_BL_ENABLE_M ) ) + +#define DEFAULT_CCFG_ERASE_CONF ( \ + ((((uint32_t)( SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N )) << CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M ) & \ + ((((uint32_t)( SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N )) << CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M ) ) + +#define DEFAULT_CCFG_CCFG_TI_OPTIONS ( \ + ((((uint32_t)( SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE )) << CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S ) | ~CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M ) ) + +#define DEFAULT_CCFG_CCFG_TAP_DAP_0 ( \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M ) ) + +#define DEFAULT_CCFG_CCFG_TAP_DAP_1 ( \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_M ) ) + +#define DEFAULT_CCFG_IMAGE_VALID_CONF SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID + +#define DEFAULT_CCFG_CCFG_PROT_31_0 SET_CCFG_CCFG_PROT_31_0 +#define DEFAULT_CCFG_CCFG_PROT_63_32 SET_CCFG_CCFG_PROT_63_32 +#define DEFAULT_CCFG_CCFG_PROT_95_64 SET_CCFG_CCFG_PROT_95_64 +#define DEFAULT_CCFG_CCFG_PROT_127_96 SET_CCFG_CCFG_PROT_127_96 + +//***************************************************************************** +// +// Customer Configuration Area in Lock Page +// +//***************************************************************************** +#if defined(__IAR_SYSTEMS_ICC__) +__root const ccfg_t __ccfg @ ".ccfg" = +#elif defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(__ccfg, ".ccfg") +#pragma RETAIN(__ccfg) +const ccfg_t __ccfg = +#else +const ccfg_t __ccfg __attribute__((section(".ccfg"))) __attribute__((used)) = +#endif +{ // Mapped to address + DEFAULT_CCFG_EXT_LF_CLK , // 0x50003FA8 (0x50003xxx maps to last + DEFAULT_CCFG_MODE_CONF_1 , // 0x50003FAC sector in FLASH. + DEFAULT_CCFG_SIZE_AND_DIS_FLAGS , // 0x50003FB0 Independent of FLASH size) + DEFAULT_CCFG_MODE_CONF , // 0x50003FB4 + DEFAULT_CCFG_VOLT_LOAD_0 , // 0x50003FB8 + DEFAULT_CCFG_VOLT_LOAD_1 , // 0x50003FBC + DEFAULT_CCFG_RTC_OFFSET , // 0x50003FC0 + DEFAULT_CCFG_FREQ_OFFSET , // 0x50003FC4 + DEFAULT_CCFG_IEEE_MAC_0 , // 0x50003FC8 + DEFAULT_CCFG_IEEE_MAC_1 , // 0x50003FCC + DEFAULT_CCFG_IEEE_BLE_0 , // 0x50003FD0 + DEFAULT_CCFG_IEEE_BLE_1 , // 0x50003FD4 + DEFAULT_CCFG_BL_CONFIG , // 0x50003FD8 + DEFAULT_CCFG_ERASE_CONF , // 0x50003FDC + DEFAULT_CCFG_CCFG_TI_OPTIONS , // 0x50003FE0 + DEFAULT_CCFG_CCFG_TAP_DAP_0 , // 0x50003FE4 + DEFAULT_CCFG_CCFG_TAP_DAP_1 , // 0x50003FE8 + DEFAULT_CCFG_IMAGE_VALID_CONF , // 0x50003FEC + DEFAULT_CCFG_CCFG_PROT_31_0 , // 0x50003FF0 + DEFAULT_CCFG_CCFG_PROT_63_32 , // 0x50003FF4 + DEFAULT_CCFG_CCFG_PROT_95_64 , // 0x50003FF8 + DEFAULT_CCFG_CCFG_PROT_127_96 , // 0x50003FFC +}; + +#endif // __CCFC_C__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADC.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADC.c new file mode 100644 index 0000000..c408cc8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADC.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2016-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ADC.c ======== + */ + +#include +#include +#include + +#include +#include + +extern const ADC_Config ADC_config[]; +extern const uint_least8_t ADC_count; + +/* Default ADC parameters structure */ +const ADC_Params ADC_defaultParams = { + .custom = NULL, + .isProtected = true +}; + +static bool isInitialized = false; + +/* + * ======== ADC_close ======== + */ +void ADC_close(ADC_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== ADC_control ======== + */ +int_fast16_t ADC_control(ADC_Handle handle, uint_fast16_t cmd, void *arg) +{ + return (handle->fxnTablePtr->controlFxn(handle, cmd, arg)); +} + +/* + * ======== ADC_convert ======== + */ +int_fast16_t ADC_convert(ADC_Handle handle, uint16_t *value) +{ + return (handle->fxnTablePtr->convertFxn(handle, value)); +} + +/* + * ======== ADC_convertToMicroVolts ======== + */ +uint32_t ADC_convertToMicroVolts(ADC_Handle handle, uint16_t adcValue) +{ + return (handle->fxnTablePtr->convertToMicroVolts(handle, adcValue)); +} + +/* + * ======== ADC_init ======== + */ +void ADC_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + + key = HwiP_disable(); + + if (!isInitialized) { + isInitialized = (bool) true; + + /* Call each driver's init function */ + for (i = 0; i < ADC_count; i++) { + ADC_config[i].fxnTablePtr->initFxn((ADC_Handle)&(ADC_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== ADC_open ======== + */ +ADC_Handle ADC_open(uint_least8_t index, ADC_Params *params) +{ + ADC_Handle handle = NULL; + + if (isInitialized && (index < ADC_count)) { + /* If params are NULL use defaults */ + if (params == NULL) { + params = (ADC_Params *) &ADC_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (ADC_Handle) &(ADC_config[index]); + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== ADC_Params_init ======== + */ +void ADC_Params_init(ADC_Params *params) +{ + *params = ADC_defaultParams; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADC.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADC.h new file mode 100644 index 0000000..3fd196c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADC.h @@ -0,0 +1,468 @@ +/* + * Copyright (c) 2016-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ADC.h + * @brief Analog to Digital Conversion (ADC) Input Driver + * + * @anchor ti_drivers_ADC_Overview + * # Overview + * + * The ADC driver allows you to manage an Analog to Digital peripheral via + * simple and portable APIs. This driver supports sampling and converting + * raw values into microvolts. + * + *
+ * @anchor ti_drivers_ADC_Usage + * # Usage + * + * This documentation provides a basic @ref ti_drivers_ADC_Synopsis + * "usage summary" and a set of @ref ti_drivers_ADC_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor ti_drivers_ADC_Synopsis + * ## Synopsis + * @anchor ti_drivers_ADC_Synopsis_Code + * @code + * // Import ADC Driver definitions + * #include + * + * // Define name for ADC channel index + * #define THERMOCOUPLE_OUT 0 + * + * // One-time init of ADC driver + * ADC_init(); + * + * // initialize optional ADC parameters + * ADC_Params params; + * ADC_Params_init(¶ms); + * params.isProtected = true; + * + * // Open ADC channels for usage + * ADC_Handle adcHandle = ADC_open(THERMOCOUPLE_OUT, ¶ms); + * + * // Sample the analog output from the Thermocouple + * ADC_convert(adcHandle, &result); + * + * // Convert the sample to microvolts + * resultUv = ADC_convertToMicroVolts(adcHandle, result); + * + * ADC_close(adcHandle); + * @endcode + * + *
+ * @anchor ti_drivers_ADC_Examples + * # Examples + * + * @li @ref ti_drivers_ADC_Examples_open "Opening an ADC instance" + * @li @ref ti_drivers_ADC_Examples_convert "Taking an ADC sample" + * @li @ref ti_drivers_ADC_Examples_convert_microvolts "Converting a sample to microvolts" + * + * @anchor ti_drivers_ADC_Examples_open + * ## Opening an ADC instance + * + * @code + * ADC_Handle adc; + * ADC_Params params; + * + * ADC_Params_init(¶ms); + * + * adc = ADC_open(0, ¶ms); + * if (adc == NULL) { + * // ADC_open() failed + * while (1) {} + * } + * @endcode + * + * @anchor ti_drivers_ADC_Examples_convert + * ## Taking an ADC sample + * + * An ADC conversion with an ADC peripheral is started by calling + * ADC_convert(). The result value is returned by ADC_convert() + * once the conversion is finished. + * + * @code + * int_fast16_t res; + * uint_fast16_t adcValue; + * + * res = ADC_convert(adc, &adcValue); + * if (res == ADC_STATUS_SUCCESS) + * { + * print(adcValue); + * } + * @endcode + * + * @anchor ti_drivers_ADC_Examples_convert_microvolts + * ## Converting a sample to microvolts + * + * The result value returned by ADC_convert() is a raw value. The + * following uses ADC_convertToMicroVolts() to convert the raw value + * into microvolts. + * @code + * int_fast16_t res; + * uint_fast16_t adcValue; + * uint32_t adcValueUv; + * + * res = ADC_convert(adc, &adcValue); + * if (res == ADC_STATUS_SUCCESS) + * { + * adcValueUv = ADC_convertToMicroVolts(adc, adcValue); + * } + * @endcode + * + *
+ * @anchor ti_drivers_ADC_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_ADC__include +#define ti_drivers_ADC__include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @deprecated ADC_convertRawToMicroVolts() is succeeded by + * ADC_convertToMicroVolts(). + */ +#define ADC_convertRawToMicroVolts ADC_convertToMicroVolts + +/*! + * @defgroup ADC_CONTROL ADC_control command and status codes + * These ADC macros are reservations for ADC.h + * @{ + */ + +/*! + * @hideinitializer + * Common ADC_control command code reservation offset. + * ADC driver implementations should offset command codes with ADC_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define ADCXYZ_CMD_COMMAND0 ADC_CMD_RESERVED + 0 + * #define ADCXYZ_CMD_COMMAND1 ADC_CMD_RESERVED + 1 + * @endcode + */ +#define ADC_CMD_RESERVED (32) + +/*! + * @hideinitializer + * Common ADC_control status code reservation offset. + * ADC driver implementations should offset status codes with + * ADC_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ADCXYZ_STATUS_ERROR0 ADC_STATUS_RESERVED - 0 + * #define ADCXYZ_STATUS_ERROR1 ADC_STATUS_RESERVED - 1 + * #define ADCXYZ_STATUS_ERROR2 ADC_STATUS_RESERVED - 2 + * @endcode + */ +#define ADC_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code returned by ADC_control(). + * + * ADC_control() returns ADC_STATUS_SUCCESS if the control code was executed + * successfully. + * @{ + * @ingroup ADC_CONTROL + */ +#define ADC_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by ADC_control(). + * + * ADC_control() returns ADC_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define ADC_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by ADC_control() for undefined + * command codes. + * + * ADC_control() returns ADC_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define ADC_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup ADC_CMD Command Codes + * ADC_CMD_* macros are general command codes for ADC_control(). Not all ADC + * driver implementations support these command codes. + * @{ + * @ingroup ADC_CONTROL + */ + +/* Add ADC_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief A handle that is returned from an ADC_open() call. + */ +typedef struct ADC_Config *ADC_Handle; + +/*! + * @brief ADC Parameters used with ADC_open(). + * + * ADC_Params_init() must be called prior to setting fields in + * this structure. + * + * @sa ADC_Params_init() + */ +typedef struct { + void *custom; /*!< Custom argument used by driver + implementation */ + bool isProtected; /*!< By default ADC uses a semaphore + to guarantee thread safety. Setting + this parameter to 'false' will eliminate + the usage of a semaphore for thread + safety. The user is then responsible + for ensuring that parallel invocations + of ADC_convert() are thread safe. */ +} ADC_Params; + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADC_close(). + */ +typedef void (*ADC_CloseFxn) (ADC_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADC_control(). + */ +typedef int_fast16_t (*ADC_ControlFxn) (ADC_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADC_ConvertFxn(). + */ +typedef int_fast16_t (*ADC_ConvertFxn) (ADC_Handle handle, uint16_t *value); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADC_convertToMicroVolts(). + */ +typedef uint32_t (*ADC_ConvertToMicroVoltsFxn) (ADC_Handle handle, + uint16_t adcValue); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADC_init(). + */ +typedef void (*ADC_InitFxn) (ADC_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADC_open(). + */ +typedef ADC_Handle (*ADC_OpenFxn) (ADC_Handle handle, ADC_Params *params); + +/*! + * @brief The definition of an ADC function table that contains the + * required set of functions to control a specific ADC driver + * implementation. + */ +typedef struct { + /*! Function to close the specified peripheral */ + ADC_CloseFxn closeFxn; + + /*! Function to perform implementation specific features */ + ADC_ControlFxn controlFxn; + + /*! Function to initiate an ADC single channel conversion */ + ADC_ConvertFxn convertFxn; + + /*! Function to convert ADC result to microvolts */ + ADC_ConvertToMicroVoltsFxn convertToMicroVolts; + + /*! Function to initialize the given data object */ + ADC_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + ADC_OpenFxn openFxn; +} ADC_FxnTable; + +/*! + * @brief ADC driver's custom @ref driver_configuration "configuration" + * structure. + * + * @sa ADC_init() + * @sa ADC_open() + */ +typedef struct ADC_Config { + /*! Pointer to a @ref driver_function_table "function pointer table" + * with driver-specific implementations of ADC APIs */ + ADC_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific @ref driver_objects "data object". */ + void *object; + + /*! Pointer to a driver specific @ref driver_hardware_attributes + * "hardware attributes structure". */ + void const *hwAttrs; +} ADC_Config; + +/*! + * @brief Function to close an ADC driver instance + * + * @pre ADC_open() has to be called first. + * + * @param[in] handle An #ADC_Handle returned from ADC_open() + */ +extern void ADC_close(ADC_Handle handle); + +/*! + * @brief Function performs implementation specific features on a + * driver instance. + * + * @pre ADC_open() has to be called first. + * + * @param[in] handle An #ADC_Handle returned from ADC_open() + * + * @param[in] cmd A command value defined by the device specific + * implementation + * + * @param[in] arg An optional R/W (read/write) argument that is + * accompanied with @p cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @retval #ADC_STATUS_SUCCESS The call was successful. + * @retval #ADC_STATUS_UNDEFINEDCMD The @p cmd value is not supported by + * the device specific implementation. + */ +extern int_fast16_t ADC_control(ADC_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief Function to perform an ADC conversion + * + * Function to perform a single channel sample conversion. + * + * @pre ADC_open() has been called + * + * @param[in] handle An #ADC_Handle returned from ADC_open() + * @param[in,out] value A pointer to a uint16_t to store the conversion + * result + * + * @retval #ADC_STATUS_SUCCESS The conversion was successful. + * @retval #ADC_STATUS_ERROR The conversion failed and @p value is + * invalid. + * + * @sa ADC_convertToMicroVolts() + */ +extern int_fast16_t ADC_convert(ADC_Handle handle, uint16_t *value); + +/*! + * @brief Function to convert a raw ADC sample into microvolts. + * + * @pre ADC_convert() has to be called first. + * + * @param[in] handle An #ADC_Handle returned from ADC_open() + * + * @param[in] adcValue A sampling result return from ADC_convert() + * + * @return @p adcValue converted into microvolts + * + * @sa ADC_convert() + */ +extern uint32_t ADC_convertToMicroVolts(ADC_Handle handle, + uint16_t adcValue); + +/*! + * @brief Function to initialize the ADC driver. + * + * This function must also be called before any other ADC driver APIs. + */ +extern void ADC_init(void); + +/*! + * @brief Function to initialize the ADC peripheral + * + * Function to initialize the ADC peripheral specified by the + * particular index value. + * + * @pre ADC_init() has been called + * + * @param[in] index Index in the @p ADC_Config[] array. + * @param[in] params Pointer to an initialized #ADC_Params structure. + * If NULL, the default #ADC_Params values are used. + * + * @return An #ADC_Handle on success or NULL on error. + * + * @sa ADC_init() + * @sa ADC_close() + */ +extern ADC_Handle ADC_open(uint_least8_t index, ADC_Params *params); + +/*! + * @brief Initialize an #ADC_Params structure to its default values. + * + * @param[in] params A pointer to an #ADC_Params structure. + * + * Default values are: + * @arg #ADC_Params.custom = NULL + * @arg #ADC_Params.isProtected = true + */ +extern void ADC_Params_init(ADC_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ADC__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADCBuf.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADCBuf.c new file mode 100644 index 0000000..a61028b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADCBuf.c @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ADCBuf.c ======== + */ + +#include +#include +#include + +#include +#include + +extern const ADCBuf_Config ADCBuf_config[]; +extern const uint_least8_t ADCBuf_count; + +/* Default ADC parameters structure */ +const ADCBuf_Params ADCBuf_defaultParams = { + .returnMode = ADCBuf_RETURN_MODE_BLOCKING, /*!< Blocking mode */ + .blockingTimeout = 25000, /*!< Timeout of 25000 RTOS ticks */ + .callbackFxn = NULL, /*!< No callback function */ + .recurrenceMode = ADCBuf_RECURRENCE_MODE_ONE_SHOT, /*!< One-shot measurement */ + .samplingFrequency = 10000, /*!< Take samples at 10kHz */ + .custom = NULL +}; + +static bool isInitialized = false; + +/* + * ======== ADCBuf_close ======== + */ +void ADCBuf_close(ADCBuf_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== ADCBuf_control ======== + */ +int_fast16_t ADCBuf_control(ADCBuf_Handle handle, uint_fast16_t cmd, void *cmdArg) +{ + return handle->fxnTablePtr->controlFxn(handle, cmd, cmdArg); +} + +/* + * ======== ADCBuf_init ======== + */ +void ADCBuf_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + + key = HwiP_disable(); + + if (!isInitialized) { + isInitialized = (bool) true; + + /* Call each driver's init function */ + for (i = 0; i < ADCBuf_count; i++) { + ADCBuf_config[i].fxnTablePtr->initFxn((ADCBuf_Handle) & (ADCBuf_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== ADCBuf_open ======== + */ +ADCBuf_Handle ADCBuf_open(uint_least8_t index, ADCBuf_Params *params) +{ + ADCBuf_Handle handle = NULL; + + /* Verify driver index and state */ + if (isInitialized && (index < ADCBuf_count)) { + /* If params are NULL use defaults */ + if (params == NULL) { + params = (ADCBuf_Params *)&ADCBuf_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (ADCBuf_Handle)&(ADCBuf_config[index]); + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== ADCBuf_Params_init ======== + */ +void ADCBuf_Params_init(ADCBuf_Params *params) +{ + *params = ADCBuf_defaultParams; +} + +/* + * ======== ADCBuf_convert ======== + */ +int_fast16_t ADCBuf_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount) +{ + return (handle->fxnTablePtr->convertFxn(handle, conversions, channelCount)); +} + +/* + * ======== ADCBuf_convertCancel ======== + */ +int_fast16_t ADCBuf_convertCancel(ADCBuf_Handle handle) +{ + return (handle->fxnTablePtr->convertCancelFxn(handle)); +} + +/* + * ======== ADCBuf_getResolution ======== + */ +uint_fast8_t ADCBuf_getResolution(ADCBuf_Handle handle) +{ + return (handle->fxnTablePtr->getResolutionFxn(handle)); +} + +/* + * ======== ADCBuf_adjustRawValues ======== + */ +int_fast16_t ADCBuf_adjustRawValues(ADCBuf_Handle handle, void *sampleBuf, uint_fast16_t sampleCount, uint32_t adcChan) +{ + return (handle->fxnTablePtr->adjustRawValuesFxn(handle, sampleBuf, sampleCount, adcChan)); +} + +/* + * ======== ADCBuf_convertAdjustedToMicroVolts ======== + */ +int_fast16_t ADCBuf_convertAdjustedToMicroVolts(ADCBuf_Handle handle, uint32_t adcChan, void *adjustedSampleBuffer, uint32_t outputMicroVoltBuffer[], uint_fast16_t sampleCount) +{ + return (handle->fxnTablePtr->convertAdjustedToMicroVoltsFxn(handle, adcChan, adjustedSampleBuffer, outputMicroVoltBuffer, sampleCount)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADCBuf.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADCBuf.h new file mode 100644 index 0000000..bd2637e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADCBuf.h @@ -0,0 +1,831 @@ +/* + * Copyright (c) 2016-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file ADCBuf.h + * @brief Analog to Digital Conversion Buffer (ADCBuf) Input Driver + * + * @anchor ti_drivers_ADCBuf_Overview + * # Overview + * + * The ADCBuf driver allows you to sample and convert analog signals + * at a specified frequency. The resulting samples are placed in + * a buffer provided by the application. The driver can either take @p N + * samples once or continuously sample by double-buffering and providing a + * callback to process each finished buffer. + * + *
+ * @anchor ti_drivers_ADCBuf_Usage + * # Usage + * + * This documentation provides a basic @ref ti_drivers_ADCBuf_Synopsis + * "usage summary" and a set of @ref ti_drivers_ADCBuf_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor ti_drivers_ADCBuf_Synopsis + * ## Synopsis + * @anchor ti_drivers_ADCBuf_Synopsis_Code + * @code + * // Import ADCBuf Driver definitions + * #include + * + * // Define name for ADCBuf channel index + * #define PIEZOMETER_OUT 0 + * + * // Create buffer for samples + * #define ADCBUFFERSIZE 10 + * uint16_t buffer[ADCBUFFERSIZE]; + * uint32_t microvoltBuffer[ADCBUFFERSIZE]; + * + * // One time init of ADCBuf driver + * ADCBuf_init(); + * + * // Initialize optional ADCBuf parameters + * ADCBuf_Params params; + * ADCBuf_Params_init(¶ms); + * params.returnMode = ADCBuf_RETURN_MODE_BLOCKING; + * params.recurrenceMode = ADCBuf_RECURRENCE_MODE_ONE_SHOT; + * + * // Open ADCBuf driver + * adcBuf = ADCBuf_open(Board_ADCBUF0, ¶ms); + * + * // Setup conversion structure + * ADCBuf_Conversion conversion = {0}; + * conversion.samplesRequestedCount = ADCBUFFERSIZE; + * conversion.sampleBuffer = buffer; + * conversion.adcChannel = PIEZOMETER_OUT; + * + * // Start ADCBuf conversion + * ADCBuf_convert(adcBuf, &conversion, 1) + * + * // Adjust raw ADC values and convert them to microvolts + * ADCBuf_adjustRawValues(handle, buffer, ADCBUFFERSIZE, PIEZOMETER_OUT); + * ADCBuf_convertAdjustedToMicroVolts(handle, PIEZOMETER_OUT, buffer, + * microvoltBuffer, ADCBUFFERSIZE); + * + * // Close ADCBuf driver + * ADCBuf_close(adcbuf); + * @endcode + * + *
+ * @anchor ti_drivers_ADCBuf_Examples + * # Examples + * + * @li @ref ti_drivers_ADCBuf_Examples_open "Opening an ADCBuf instance" + * @li @ref ti_drivers_ADCBuf_Examples_blocking "Using a blocking conversion" + * @li @ref ti_drivers_ADCBuf_Examples_callback "Using a callback conversion" + * + * @anchor ti_drivers_ADCBuf_Examples_open + * ## Opening an ADCBuf instance + * + * @code + * ADCBuf_Handle adcBufHandle; + * ADCBuf_Params adcBufParams; + * + * ADCBuf_init(); + * + * ADCBuf_Params_init(&adcBufParams); + * + * adcBufHandle = ADCBuf_open(0, &adcBufParams); + * if (adcBufHandle == NULL) + * { + * //ADCBuf_open() failed. + * while (1) {} + * } + * @endcode + * + * @anchor ti_drivers_ADCBuf_Examples_blocking + * ## Using a blocking conversion + * + * @code + * ADCBuf_Handle adcbuf; + * ADCBuf_Params params; + * + * ADCBuf_init(); + * + * ADCBuf_Params_init(¶ms); + * params.returnMode = ADCBuf_RETURN_MODE_BLOCKING; + * params.recurrenceMode = ADCBuf_RECURRENCE_MODE_ONE_SHOT; + * adcbuf = ADCBuf_open(0, ¶ms); + * if (adcbuf != NULL) + * { + * ADCBuf_Conversion conversion = {0}; + * conversion.adcChannel = PIEZOMETER_OUT; + * conversion.sampleBuffer = buffer; + * conversion.samplesRequestedCount = ADCBUFFERSIZE; + * + * if (ADCBuf_convert(adcbuf, &conversion, 1) != ADCBuf_STATUS_SUCCESS) + * { + * // ADCBuf_conver() failed + * } + * } + * @endcode + * + * @anchor ti_drivers_ADCBuf_Examples_callback + * ## Using a callback conversion + * + * @code + * // ADCBuf callback function + * void adcBufCallbackFxn(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, + * void *buffer, uint32_t channel); + * + * main() + * { + * ADCBuf_Handle adcbuf; + * ADCBuf_Params params; + * + * ADCBuf_init(); + * + * ADCBuf_Params_init(¶ms); + * params.returnMode = ADCBuf_RETURN_MODE_CALLBACK; + * params.recurrenceMode = ADCBuf_RECURRENCE_MODE_ONE_SHOT; + * params.callbackFxn = adcBufCallbackFxn; + * adcbuf = ADCBuf_open(0, ¶ms); + * + * ADCBuf_Conversion conversion = {0}; + * conversion.adcChannel = PIEZOMETER_OUT; + * conversion.sampleBuffer = buffer; + * conversion.samplesRequestedCount = ADCBUFFERSIZE; + * + * if (ADCBuf_convert(adcbuf, &conversion, 1) != ADCBuf_STATUS_SUCCESS) + * { + * // ADCBuf_convert() failed + * } + * + * // Pend on a semaphore + * } + * + * void adcBufCallbackFxn(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, + * void *buffer, uint32_t channel) + * { + * // Adjust raw ADC values and convert them to microvolts + * ADCBuf_adjustRawValues(handle, buffer, ADCBUFFERSIZE, + * channel); + * ADCBuf_convertAdjustedToMicroVolts(handle, channel, + * buffer, microvoltBuffer, ADCBUFFERSIZE); + * + * // Post a semaphore + * } + * + * @endcode + * + *
+ * @anchor ti_drivers_ADCBuf_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_adcbuf__include +#define ti_drivers_adcbuf__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @defgroup ADCBuf_CONTROL ADCBuf_control command and status codes + * These ADCBuf macros are reservations for ADCBuf.h + * @{ + */ + +/*! + * Common ADCBuf_control command code reservation offset. + * ADC driver implementations should offset command codes with + * ADCBuf_CMD_RESERVED growing positively + * + * Example implementation specific command codes: + * @code + * #define ADCXYZ_COMMAND0 ADCBuf_CMD_RESERVED + 0 + * #define ADCXYZ_COMMAND1 ADCBuf_CMD_RESERVED + 1 + * @endcode + */ +#define ADCBuf_CMD_RESERVED (32) + +/*! + * Common ADCBuf_control status code reservation offset. + * ADC driver implementations should offset status codes with + * ADCBuf_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ADCXYZ_STATUS_ERROR0 ADCBuf_STATUS_RESERVED - 0 + * #define ADCXYZ_STATUS_ERROR1 ADCBuf_STATUS_RESERVED - 1 + * #define ADCXYZ_STATUS_ERROR2 ADCBuf_STATUS_RESERVED - 2 + * @endcode + */ +#define ADCBuf_STATUS_RESERVED (-32) + +/*! + * @brief Success status code returned by: + * ADCBuf_control() + * + * Functions return ADCBuf_STATUS_SUCCESS if the call was executed + * successfully. + * @{ + * @ingroup ADCBuf_CONTROL + */ +#define ADCBuf_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by ADCBuf_control(). + * + * ADCBuf_control() returns #ADCBuf_STATUS_ERROR if the control code was + * not executed successfully. + */ +#define ADCBuf_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by ADCBuf_control() for undefined + * command codes. + * + * ADCBuf_control() returns ADCBuf_STATUS_UNDEFINEDCMD if the control code is + * not recognized by the driver implementation. + */ +#define ADCBuf_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief An error status code returned if the function is not supported + * by a particular driver implementation. + */ +#define ADCBuf_STATUS_UNSUPPORTED (-3) +/** @}*/ + +/** + * @defgroup ADCBuf_CMD Command Codes + * ADCBuf_CMD_* macros are general command codes for I2C_control(). Not all + * ADCBuf driver implementations support these command codes. + * @{ + * @ingroup ADCBuf_CONTROL + */ + +/* Add ADCBuf_CMD_ here */ + +/** @}*/ + +/** @}*/ + + +/*! + * @brief A handle that is returned from an ADCBuf_open() call. + */ +typedef struct ADCBuf_Config *ADCBuf_Handle; + +/*! + * @brief Defines a conversion to be used with ADCBuf_convert(). + * + * @sa ADCBuf_convert() + * @sa #ADCBuf_Recurrence_Mode + * @sa #ADCBuf_Return_Mode + */ +typedef struct +{ + /*! + * Defines the number of samples to be performed on the + * ADCBuf_Conversion.channel. The application buffers provided by + * #ADCBuf_Conversion.sampleBuffer and #ADCBuf_Conversion.sampleBufferTwo + * must be large enough to hold @p samplesRequestedCount samples. + */ + uint16_t samplesRequestedCount; + + /*! + * Buffer to store ADCBuf conversion results. This buffer must be at least + * (#ADCBuf_Conversion.samplesRequestedCount * 2) bytes. When using + * #ADCBuf_RECURRENCE_MODE_ONE_SHOT, only this buffer is used. + */ + void *sampleBuffer; + + /*! + * Buffer to store ADCBuf conversion results. This buffer must be at least + * (#ADCBuf_Conversion.samplesRequestedCount * 2) bytes. When using + * #ADCBuf_RECURRENCE_MODE_ONE_SHOT, this buffer is not used. When + * using #ADCBuf_RECURRENCE_MODE_CONTINUOUS, this must point to + * a valid buffer. + * + * @sa #ADCBuf_RECURRENCE_MODE_CONTINUOUS + */ + void *sampleBufferTwo; + + /*! + * Pointer to a custom argument to be passed to the #ADCBuf_Callback + * function via the #ADCBuf_Conversion structure. + * + * @note The #ADCBuf_Callback function is only called when operating in + * #ADCBuf_RETURN_MODE_CALLBACK. + * + * @sa #ADCBuf_RETURN_MODE_CALLBACK + * @sa #ADCBuf_Callback + */ + void *arg; + + /*! + * ADCBuf channel to perform conversions on. Mapping of channel to pin or + * internal signal is device specific. Refer to the device specific + * implementation. + */ + uint32_t adcChannel; +} ADCBuf_Conversion; + +/*! + * @brief The definition of a callback function. + * + * When operating in #ADCBuf_RETURN_MODE_CALLBACK, the callback function + * is called when an #ADCBuf_Conversion completes. The application is + * responsible for declaring a #ADCBuf_Callback and providing a pointer + * in #ADCBuf_Params.callbackFxn. + * + * @warning The callback function is called from an interrupt context. + * + * @param[out] handle #ADCBuf_Handle used with the initial call to + * ADCBuf_convert() + * + * @param[out] conversion Pointer to the #ADCBuf_Conversion structure used + * with the initial call to ADCBuf_convert(). This structure also contains + * the custom argument specified by @p conversion.arg. + * + * @param[out] completedADCBuffer Pointer to a buffer containing + * @p conversion.samplesRequestedCount ADC samples. + * + * @param[out] completedChannel ADCBuf channel the samples were + * performed on. + * + * @sa ADCBuf_convert() + * @sa ADCBuf_Conversion + * @sa ADCBuf_Recurrence_Mode + * @sa ADCBuf_RETURN_MODE_CALLBACK + */ +typedef void (*ADCBuf_Callback) (ADCBuf_Handle handle, + ADCBuf_Conversion *conversion, + void *completedADCBuffer, + uint32_t completedChannel); + +/*! + * @brief Recurrence behavior of a #ADCBuf_Conversion specified in the + * #ADCBuf_Params. + * + * This enumeration defines the recurrence mode of a #ADCBuf_Conversion. + * After a call to ADCBuf_convert(), #ADCBuf_Conversion may either be done + * once or reoccur. + */ +typedef enum +{ + /*! + * When operating in #ADCBuf_RECURRENCE_MODE_ONE_SHOT, calls to + * ADCBuf_convert() will pend on a semaphore until + * #ADCBuf_Conversion.samplesRequestedCount samples are completed or + * after a duration of #ADCBuf_Params.blockingTimeout. + * + * @note When using #ADCBuf_RECURRENCE_MODE_ONE_SHOT, ADCBuf_convert() + * must be called from a thread context. #ADCBuf_RECURRENCE_MODE_ONE_SHOT + * can only be used in combination with #ADCBuf_RETURN_MODE_BLOCKING. + */ + ADCBuf_RECURRENCE_MODE_ONE_SHOT, + + /*! + * When operating in #ADCBuf_RECURRENCE_MODE_CONTINUOUS, calls to + * ADCBuf_convert() will return immediately. The driver will continuously + * perform #ADCBuf_Conversion.samplesRequestedCount samples and call the + * #ADCBuf_Callback function when completed. The driver + * will automatically alternate between #ADCBuf_Conversion.sampleBuffer + * and #ADCBuf_Conversion.sampleBufferTwo. A + * #ADCBuf_RECURRENCE_MODE_CONTINUOUS conversion can only be terminated + * using ADCBuf_convertCancel(). + * + * @note #ADCBuf_RECURRENCE_MODE_CONTINUOUS can only be used in + * combination with #ADCBuf_RETURN_MODE_CALLBACK. + * + * @sa #ADCBuf_RETURN_MODE_CALLBACK + * @sa ADCBuf_convertCancel() + */ + ADCBuf_RECURRENCE_MODE_CONTINUOUS +} ADCBuf_Recurrence_Mode; + +/*! + * @brief Return behavior for ADCBuf_convert() specified in the + * #ADCBuf_Params + * + * This enumeration defines the return behavior for ADCBuf_convert(). + * A call to ADCBuf_convert() may either block or return immediately. + * + * @sa ADCBuf_convert + */ +typedef enum +{ + /*! + * When operating in #ADCBuf_RETURN_MODE_BLOCKING, calls to + * ADCBuf_convert() will pend on a semaphore until + * #ADCBuf_Conversion.samplesRequestedCount samples are completed or + * after a duration of #ADCBuf_Params.blockingTimeout. + * + * @note When using #ADCBuf_RETURN_MODE_BLOCKING, ADCBuf_convert() + * must be called from a thread context. #ADCBuf_RETURN_MODE_BLOCKING + * can only be used in combination with #ADCBuf_RECURRENCE_MODE_ONE_SHOT. + */ + ADCBuf_RETURN_MODE_BLOCKING, + + /*! + * When operating in #ADCBuf_RETURN_MODE_CALLBACK, calls to + * ADCBuf_convert() will return immediately. When + * #ADCBuf_Conversion.samplesRequestedCount samples are completed, + * the #ADCBuf_Params.callbackFxn function is called. + * + * @note #ADCBuf_RECURRENCE_MODE_CONTINUOUS can only be used in + * combination with #ADCBuf_RETURN_MODE_CALLBACK. + * + * @sa #ADCBuf_RECURRENCE_MODE_CONTINUOUS + */ + ADCBuf_RETURN_MODE_CALLBACK +} ADCBuf_Return_Mode; + +/*! + * @brief ADCBuf parameters used with ADCBuf_open(). + * + * #ADCBuf_Params_init() must be called prior to setting fields in + * this structure. + * + * @sa ADCBuf_Params_init() + */ +typedef struct +{ + /*! + * Timeout in system clock ticks. This value is only valid when using + * #ADCBuf_RETURN_MODE_BLOCKING. A call to ADCBuf_convert() will block + * for a duration up to @p blockingTimeout ticks. The call to + * ADCBuf_convert() will return prior if the requested number of samples + * in #ADCBuf_Conversion.samplesRequestedCount are completed. The + * @p blockingTimeout should be large enough to allow for + * #ADCBuf_Conversion.samplesRequestedCount samples to be collected + * given the #ADCBuf_Params.samplingFrequency. + * + * @sa #ADCBuf_RETURN_MODE_BLOCKING + */ + uint32_t blockingTimeout; + + /*! + * The frequency at which the ADC will sample in Hertz (Hz). After a + * call to ADCBuf_convert(), the ADC will perform @p samplingFrequency + * samples per second. + */ + uint32_t samplingFrequency; + + /*! #ADCBuf_Return_Mode for all conversions. */ + ADCBuf_Return_Mode returnMode; + + /*! + * Pointer to a #ADCBuf_Callback function to be invoked after a + * conversion completes when operating in #ADCBuf_RETURN_MODE_CALLBACK. + */ + ADCBuf_Callback callbackFxn; + + /*! #ADCBuf_Recurrence_Mode for all conversions. */ + ADCBuf_Recurrence_Mode recurrenceMode; + + /*! Pointer to a device specific extension of the #ADCBuf_Params */ + void *custom; +} ADCBuf_Params; + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_close(). + */ +typedef void (*ADCBuf_CloseFxn) (ADCBuf_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_open(). + */ +typedef ADCBuf_Handle (*ADCBuf_OpenFxn) (ADCBuf_Handle handle, + const ADCBuf_Params *params); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_control(). + */ +typedef int_fast16_t (*ADCBuf_ControlFxn) (ADCBuf_Handle handle, + uint_fast8_t cmd, + void *arg); +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_init(). + */ +typedef void (*ADCBuf_InitFxn) (ADCBuf_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_convert(). + */ +typedef int_fast16_t (*ADCBuf_ConvertFxn) (ADCBuf_Handle handle, + ADCBuf_Conversion conversions[], + uint_fast8_t channelCount); +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_convertCancel(). + */ +typedef int_fast16_t (*ADCBuf_ConvertCancelFxn)(ADCBuf_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_GetResolution(); + */ +typedef uint_fast8_t (*ADCBuf_GetResolutionFxn) (ADCBuf_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_adjustRawValues(); + */ +typedef int_fast16_t (*ADCBuf_adjustRawValuesFxn)(ADCBuf_Handle handle, + void *sampleBuffer, + uint_fast16_t sampleCount, + uint32_t adcChannel); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_convertAdjustedToMicroVolts(); + */ +typedef int_fast16_t (*ADCBuf_convertAdjustedToMicroVoltsFxn) ( + ADCBuf_Handle handle, + uint32_t adcChannel, + void *adjustedSampleBuffer, + uint32_t outputMicroVoltBuffer[], + uint_fast16_t sampleCount); + +/*! + * @brief The definition of an ADCBuf function table that contains the + * required set of functions to control a specific ADC driver + * implementation. + */ +typedef struct +{ + /*! Function to close the specified peripheral */ + ADCBuf_CloseFxn closeFxn; + /*! Function to driver implementation specific control function */ + ADCBuf_ControlFxn controlFxn; + /*! Function to initialize the given data object */ + ADCBuf_InitFxn initFxn; + /*! Function to open the specified peripheral */ + ADCBuf_OpenFxn openFxn; + /*! Function to start an ADC conversion with the specified peripheral */ + ADCBuf_ConvertFxn convertFxn; + /*! Function to abort a conversion being carried out by the specified + peripheral */ + ADCBuf_ConvertCancelFxn convertCancelFxn; + /*! Function to get the resolution in bits of the ADC */ + ADCBuf_GetResolutionFxn getResolutionFxn; + /*! Function to adjust raw ADC return bit values to values comparable + between devices of the same type */ + ADCBuf_adjustRawValuesFxn adjustRawValuesFxn; + /*! Function to convert adjusted ADC values to microvolts */ + ADCBuf_convertAdjustedToMicroVoltsFxn convertAdjustedToMicroVoltsFxn; +} ADCBuf_FxnTable; + +/*! + * @brief ADC driver's custom @ref driver_configuration "configuration" + * structure. + * + * @sa ADCBuf_init() + * @sa ADCBuf_open() + */ +typedef struct ADCBuf_Config +{ + /*! Pointer to a @ref driver_function_table "function pointer table" + * with driver-specific implementations of ADC APIs */ + const ADCBuf_FxnTable *fxnTablePtr; + + /*! Pointer to a driver specific @ref driver_objects "data object". */ + void *object; + + /*! Pointer to a driver specific @ref driver_hardware_attributes + * "hardware attributes structure". */ + void const *hwAttrs; +} ADCBuf_Config; + +/*! + * @brief Function to close an ADCBuf driver instance + * + * @pre ADCBuf_open() has to be called first. + * + * @pre In #ADCBuf_RECURRENCE_MODE_CONTINUOUS, the application must call + * ADCBuf_convertCancel() first. + * + * @param[in] handle An #ADCBuf_Handle returned from ADCBuf_open() + * + */ +extern void ADCBuf_close(ADCBuf_Handle handle); + +/*! + * @brief Function performs implementation specific features on a + * driver instance. + * + * @pre ADCBuf_open() has to be called first. + * + * @param[in] handle An #ADCBuf_Handle returned from ADCBuf_open() + * + * @param[in] cmd A command value defined by the device specific + * implementation + * + * @param[in] cmdArg An optional R/W (read/write) argument that is + * accompanied with @p cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @retval #ADCBuf_STATUS_SUCCESS The call was successful. + * + * @retval #ADCBuf_STATUS_UNDEFINEDCMD The @p cmd value is not supported by + * the device specific implementation. + */ +extern int_fast16_t ADCBuf_control(ADCBuf_Handle handle, + uint_fast16_t cmd, + void *cmdArg); + +/*! + * @brief Function to initialize the ADCBuf driver. + * + * This function must also be called before any other ADCBuf driver APIs. + */ +extern void ADCBuf_init(void); + +/*! + * @brief Initialize an #ADCBuf_Params structure to its default values. + * + * @param[in] params A pointer to #ADCBuf_Params structure for + * initialization + * + * Default values are: + * @arg #ADCBuf_Params.returnMode = #ADCBuf_RETURN_MODE_BLOCKING, + * @arg #ADCBuf_Params.blockingTimeout = 25000, + * @arg #ADCBuf_Params.callbackFxn = NULL, + * @arg #ADCBuf_Params.recurrenceMode = #ADCBuf_RECURRENCE_MODE_ONE_SHOT, + * @arg #ADCBuf_Params.samplingFrequency = 10000, + * @arg #ADCBuf_Params.custom = NULL + */ +extern void ADCBuf_Params_init(ADCBuf_Params *params); + +/*! + * @brief This function opens a given ADCBuf peripheral. + * + * @param[in] index Index in the @p ADCBuf_Config[] array. + * + * @param[in] params Pointer to an initialized #ADCBuf_Params structure. + * If NULL, the default #ADCBuf_Params values are used. + * + * @return An #ADCBuf_Handle on success or NULL on error. + * + * @sa ADCBuf_close() + */ +extern ADCBuf_Handle ADCBuf_open(uint_least8_t index, ADCBuf_Params *params); + +/*! + * @brief Starts ADCBuf conversions on one or more channels. + * + * @note When using #ADCBuf_RETURN_MODE_BLOCKING, this must be called from a + * thread context. + * + * @param[in] handle An ADCBuf handle returned from ADCBuf_open() + * + * @param[in] conversions A pointer to an array of #ADCBuf_Conversion + * structures. + * + * @param[in] channelCount The number of channels to convert on in this + * call. Should be the length of the @p conversions array. Depending on the + * device, multiple simultaneous conversions may not be supported. See device + * specific implementation. + * + * @retval #ADCBuf_STATUS_SUCCESS The conversion was successful. + * @retval #ADCBuf_STATUS_ERROR The conversion failed. + * + * @pre ADCBuf_open() must have been called. + * + * @sa ADCBuf_convertCancel() + * @sa ADCBuf_Return_Mode + * @sa ADCBuf_Recurrence_Mode + * @sa ADCBuf_Conversion + */ +extern int_fast16_t ADCBuf_convert(ADCBuf_Handle handle, + ADCBuf_Conversion conversions[], + uint_fast8_t channelCount); + +/*! + * @brief Cancels all ADCBuf conversions in progress. + * + * @param[in] handle An #ADCBuf_Handle returned from ADCBuf_open() + * + * @retval #ADCBuf_STATUS_SUCCESS The cancel was successful. + * @retval #ADCBuf_STATUS_ERROR The cancel failed. + * + * @sa ADCBuf_convert() + */ +extern int_fast16_t ADCBuf_convertCancel(ADCBuf_Handle handle); + +/*! + * @brief Returns the resolution in bits of the specified ADCBuf instance. + * + * @param[in] handle An #ADCBuf_Handle returned from ADCBuf_open(). + * + * @return The resolution in bits of the specified ADC. + * + * @pre ADCBuf_open() must have been called prior. + */ +extern uint_fast8_t ADCBuf_getResolution(ADCBuf_Handle handle); + + /*! + * @brief Adjust a raw ADC output buffer. The function does + * the adjustment in-place. + * + * @param[in] handle An ADCBuf_Handle returned from ADCBuf_open(). + * + * @param[in,out] sampleBuf A buffer full of raw sample values. + * + * @param[in] sampleCount The number of samples to adjust. + * + * @param[in] adcChan The channel the buffer was sampled on. + * + * @retval #ADCBuf_STATUS_SUCCESS The operation was successful. + * @p sampleBuf contains valid values. + * + * @retval #ADCBuf_STATUS_ERROR if an error occurred. + * + * @retval #ADCBuf_STATUS_UNSUPPORTED The function is not supported by the + * device specific implementation. + * + * @pre ADCBuf_convert() must have returned a valid buffer with samples. + */ +extern int_fast16_t ADCBuf_adjustRawValues(ADCBuf_Handle handle, + void *sampleBuf, + uint_fast16_t sampleCount, + uint32_t adcChan); + + /*! + * @brief Convert an adjusted ADC output buffer to microvolts. + * + * @param[in] handle An ADCBuf_Handle returned from ADCBuf_open() + * + * @param[in] adcChan The ADC channel the samples were performed on. + * + * @param[in] adjustedSampleBuffer A buffer full of adjusted samples. + * + * @param[in,out] outputMicroVoltBuffer The output buffer. + * + * @param[in] sampleCount The number of samples to convert. + * + * @retval #ADCBuf_STATUS_SUCCESS The operation was successful. + * @p outputMicroVoltBuffer contains valid values. + * + * @retval #ADCBuf_STATUS_ERROR The operation failed. + * + * @pre ADCBuf_adjustRawValues() must be called on @p adjustedSampleBuffer. + */ +extern int_fast16_t ADCBuf_convertAdjustedToMicroVolts( + ADCBuf_Handle handle, + uint32_t adcChan, + void *adjustedSampleBuffer, + uint32_t outputMicroVoltBuffer[], + uint_fast16_t sampleCount); + +#ifdef __cplusplus +} +#endif +#endif /* ti_drivers_adcbuf__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCBC.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCBC.c new file mode 100644 index 0000000..2dcea24 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCBC.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESCBC.c ======== + * + * This file contains default values for the AESCBC_Params struct. + * + */ + +#include +#include +#include + +#include +#include + +const AESCBC_Params AESCBC_defaultParams = { + .returnBehavior = AESCBC_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESCBC_Params_init ======== + */ +void AESCBC_Params_init(AESCBC_Params *params){ + *params = AESCBC_defaultParams; +} + +/* + * ======== AESCBC_Operation_init ======== + */ +void AESCBC_Operation_init(AESCBC_Operation *operationStruct) { + memset(operationStruct, 0x00, sizeof(AESCBC_Operation)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCBC.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCBC.h new file mode 100644 index 0000000..7c289af --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCBC.h @@ -0,0 +1,644 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCBC.h + * + * @brief AESCBC driver header + * + * @warning This is a beta API. It may change in future releases. + * + * @anchor ti_drivers_AESCBC_Overview + * # Overview # + * The Cipher Block Chaining (CBC) mode of operation is a generic + * block cipher mode of operation. It can be used with any block cipher + * including AES. + * + * CBC mode encrypts messages of any practical length that have a length + * evenly divisibly by the block size. Unlike ECB, it guarantees + * confidentiality of the entire message when the message is larger than + * one block. + * + * ## Operation # + * In CBC encryption, the initialization vector (IV) is XOR'd with a block of + * plaintext and then encrypted. The output ciphertext block is then XOR'd with + * the next plaintext block and the result is encryped. This process is repeated + * until the final block of plaintext has been encrypted. + * + * To decrypt the message, decrypt the first block of ciphertext and XOR the result + * with the IV. The result is the first plaintext block. For subsequent ciphertext + * blocks, decrypt each block and XOR the previous block of the encrypted message + * into the result. + * + * ## Padding # + * CBC operates on entire blocks of ciphertext and plaintext at a time. This + * means that message lengths must be a multiple of the block cipher block size. + * AES has a block size of 16 bytes no matter the key size. Since messages do + * not necessarily always have a length that is a multiple of 16 bytes, it may + * be necessary to pad the message to a 16-byte boundary. Padding requires + * the sender and receiver to implicitly agree on the padding convention. + * Improperly designed or implemented padding schemes may leak information + * to an attacker through a padding oracle attack for example. + * + * ## Initialization Vectors # + * The IV is generated by the party performing the encryption operation. + * Within the scope of any encryption key, the IV value must be unique. + * The IV does not need to be kept secret and is usually transmitted together + * with the ciphertext to the decryting party. + * In CBC mode, the IVs must not be predictable. Two recommended ways to + * generate IVs is to either: + * + * - Apply the block cipher (AESECB), using the same key used with CBC, + * to a nonce. This nonce must be unique for each key-message pair. + * A counter will usually suffice. If the same symmetric key is used + * by both parties to encrypt messages, they should agree to use a + * nonce scheme that avoids generating the same nonce and thus IV twice. + * Incrementing the counter by two and making one party use even numbers + * and the other odd numbers is a common method to avoid such collisions. + * - Use a TRNG (True Random Number Generator) or PRNG + * (Pseudo-Random Number Generator) to generate a random number for use + * as IV. + * + * ## Drawbacks # + * CBC mode has several drawbacks. Unless interfacing with legacy devices, + * it is recommended to use an AEAD (Authenticated Encryption with Associated Data) + * mode such as CCM or GCM. Below is a non-exhaustive list of reasons to use + * a different block cipher mode of operation. + * + * - CBC mode does not offer authentication or integrity guarantees. In practice, + * this means that attackers can intercept the encrypted message and manipulate + * the ciphertext before sending the message on to the receiver. While this + * does not break confidentiality and reveal the plaintext, it has enabled several + * attacks in the past. This is especially problematic given that changing the + * ciphertext of a block will only corrupt the block itself and the subsequent + * block of resultant plaintext. This property may be used to manipulate only + * certain parts of the message. + * + * - CBC mode requires message lengths to be evenly divisible by the block size. + * This necessitates a padding scheme. Improperly implemented padding schemes + * may lead to vulnerabilities that can be exploited by attackers. It often + * makes more sense to use a dedicated stream cipher such as CTR (Counter) that + * does not have this restriction. CCM and GCM both use CTR for encryption. + * + * @anchor ti_drivers_AESCBC_Usage + * # Usage # + * ## Before starting a CBC operation # + * + * Before starting a CBC operation, the application must do the following: + * - Call #AESCBC_init() to initialize the driver + * - Call #AESCBC_Params_init() to initialize the #AESCBC_Params to default values. + * - Modify the #AESCBC_Params as desired + * - Call #AESCBC_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store, key blob), the CryptoKey must be + * initialized differently. The AESCBC API can handle all types of CryptoKey. + * However, not all device-specific implementions support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialise the #AESCBC_Operation using #AESCBC_Operation_init() and set all + * length, key, and buffer fields. + * + * ## Starting a CBC operation # + * + * The #AESCBC_oneStepEncrypt and #AESCBC_oneStepDecrypt functions perform a CBC operation + * in a single call. They will always be the most highly optimized routines with the + * least overhead and the fastest runtime. However, they require all plaintext + * or ciphertext to be available to the function at the start of the call. + * All devices support single call operations. + * + * ## After the CBC operation completes # + * + * After the CBC operation completes, the application should either start + * another operation or close the driver by calling #AESCBC_close(). + * + * @anchor ti_drivers_AESCBC_Synopsis + * ## Synopsis + * @anchor ti_drivers_AESCBC_Synopsis_Code + * @code + * // Import AESCBC Driver definitions + * #include + * + * // Define name for AESCBC channel index + * #define AESCBC_INSTANCE 0 + * + * AESCBC_init(); + * + * handle = AESCBC_open(AESCBC_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESCBC_Operation + * AESCBC_Operation_init(&operation); + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.iv = iv; + * + * encryptionResult = AESCBC_oneStepEncrypt(handle, &operation); + * + * AESCBC_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCBC_Examples + * ## Examples + * + * ### Single call CBC encryption with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * AESCBC_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * + * // For example purposes only. Generate IVs in a non-static way in practice. + * // Test vector 0 from NIST CAPV set CBCMMT128 + * uint8_t iv[16] = {0x2f, 0xe2, 0xb3, 0x33, 0xce, 0xda, 0x8f, 0x98, + * 0xf4, 0xa9, 0x9b, 0x40, 0xd2, 0xcd, 0x34, 0xa8}; + * uint8_t plaintext[16] = {0x45, 0xcf, 0x12, 0x96, 0x4f, 0xc8, 0x24, 0xab, + * 0x76, 0x61, 0x6a, 0xe2, 0xf4, 0xbf, 0x08, 0x22}; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x1f, 0x8e, 0x49, 0x73, 0x95, 0x3f, 0x3f, 0xb0, + * 0xbd, 0x6b, 0x16, 0x66, 0x2e, 0x9a, 0x3c, 0x17}; + * + * // The ciphertext should be the following after the encryption operation: + * // 0x0f, 0x61, 0xc4, 0xd4, 0x4c, 0x51, 0x47, 0xc0 + * // 0x3c, 0x19, 0x5a, 0xd7, 0xe2, 0xcc, 0x12, 0xb2 + * + * + * handle = AESCBC_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCBC_Operation operation; + * AESCBC_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.iv = iv; + * + * encryptionResult = AESCBC_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCBC_close(handle); + * + * @endcode + * + * ### Single call CBC decryption with plaintext CryptoKey in callback return mode # + * @code + * + * #include + * #include + * + * ... + * + * // Test vector 0 from NIST CAPV set CBCMMT256 + * + * uint8_t iv[16] = {0xdd, 0xbb, 0xb0, 0x17, 0x3f, 0x1e, 0x2d, 0xeb, + * 0x23, 0x94, 0xa6, 0x2a, 0xa2, 0xa0, 0x24, 0x0e}; + * uint8_t ciphertext[16] = {0xd5, 0x1d, 0x19, 0xde, 0xd5, 0xca, 0x4a, 0xe1, + * 0x4b, 0x2b, 0x20, 0xb0, 0x27, 0xff, 0xb0, 0x20}; + * uint8_t keyingMaterial[] = {0x43, 0xe9, 0x53, 0xb2, 0xae, 0xa0, 0x8a, 0x3a, + * 0xd5, 0x2d, 0x18, 0x2f, 0x58, 0xc7, 0x2b, 0x9c, + * 0x60, 0xfb, 0xe4, 0xa9, 0xca, 0x46, 0xa3, 0xcb, + * 0x89, 0xe3, 0x86, 0x38, 0x45, 0xe2, 0x2c, 0x9e}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // 0x07, 0x27, 0x0d, 0x0e, 0x63, 0xaa, 0x36, 0xda + * // 0xed, 0x8c, 0x6a, 0xde, 0x13, 0xac, 0x1a, 0xf1 + * + * + * void cbcCallback(AESCBC_Handle handle, + * int_fast16_t returnValue, + * AESCBC_Operation *operation, + * AESCBC_OperationType operationType) { + * + * if (returnValue != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * } + * + * AESCBC_Operation operation; + * + * void cbcStartFunction(void) { + * AESCBC_Handle handle; + * AESCBC_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESCBC_Params_init(¶ms); + * params.returnBehavior = AESCBC_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = cbcCallback; + * + * handle = AESCBC_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCBC_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.iv = iv; + * + * decryptionResult = AESCBC_oneStepDecrypt(handle, &operation); + * + * if (decryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while CBC operation completes in the background + * } + * + * @endcode + */ + +#ifndef ti_drivers_AESCBC__include +#define ti_drivers_AESCBC__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include + +/*! + * Common AESCBC status code reservation offset. + * AESCBC driver implementations should offset status codes with + * #AESCBC_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESCBCXYZ_STATUS_ERROR0 AESCBC_STATUS_RESERVED - 0 + * #define AESCBCXYZ_STATUS_ERROR1 AESCBC_STATUS_RESERVED - 1 + * #define AESCBCXYZ_STATUS_ERROR2 AESCBC_STATUS_RESERVED - 2 + * @endcode + */ +#define AESCBC_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return #AESCBC_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESCBC_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return #AESCBC_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESCBC_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESCBC driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESCBC_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESCBC_STATUS_CANCELED (-3) + + +/*! + * @brief A handle that is returned from an #AESCBC_open() call. + */ +typedef struct AESCBC_Config *AESCBC_Handle; + +/*! + * @brief The way in which CBC function calls return after performing an + * encryption or decryption operation. + * + * Not all CBC operations exhibit the specified return behavor. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specfied return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESCBC functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |AESCBC_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESCBC_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESCBC_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum { + AESCBC_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * CBC operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESCBC_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the CBC operation goes + * on in the background. CBC operation results are available + * after the function returns. + */ + AESCBC_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while CBC + * operation goes on in the background. CBC operation results + * are available after the function returns. + */ +} AESCBC_ReturnBehavior; + +/*! + * @brief Enum for the direction of the CBC operation. + */ +typedef enum { + AESCBC_MODE_ENCRYPT = 1, + AESCBC_MODE_DECRYPT = 2, +} AESCBC_Mode; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * a message. + */ +typedef struct { + CryptoKey *key; /*!< A previously initialized CryptoKey. */ + const uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be + * encrypted in the CBC operation. + * - Decryption: The ciphertext to be decrypted. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that + * the encrypted plaintext is copied to. + * - Decryption: The plaintext derived from the + * decrypted ciphertext is copied here. + */ + uint8_t *iv; /*!< A buffer containing an IV. IVs must be unique to + * each CBC operation and may not be reused. If + * ivInternallyGenerated is set, the iv will be + * generated by this function call and copied to + * this buffer. + */ + size_t inputLength; /*!< Length of the input and output in bytes. */ + bool ivInternallyGenerated; /*!< When true, the iv buffer passed into #AESCBC_oneStepEncrypt() functions + * will be overwritten with a randomly generated iv. + * Not supported by all implementations. + */ +} AESCBC_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum { + AESCBC_OPERATION_TYPE_ENCRYPT = 1, + AESCBC_OPERATION_TYPE_DECRYPT = 2, +} AESCBC_OperationType; + +/*! + * @brief AESCBC Global configuration + * + * The #AESCBC_Config structure contains a set of pointers used to characterize + * the AESCBC driver implementation. + * + * This structure needs to be defined before calling #AESCBC_init() and it must + * not be changed thereafter. + * + * @sa #AESCBC_init() + */ +typedef struct AESCBC_Config { + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} AESCBC_Config; + +/*! + * @brief The definition of a callback function used by the AESCBC driver + * when used in ::AESCBC_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the CBC operation. + * + * @param returnValue The result of the CBC operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operation A pointer to an operation struct. + * + * @param operationType This parameter determines which operation the + * callback refers to. + */ +typedef void (*AESCBC_CallbackFxn) (AESCBC_Handle handle, + int_fast16_t returnValue, + AESCBC_Operation *operation, + AESCBC_OperationType operationType); + +/*! + * @brief CBC Parameters + * + * CBC Parameters are used to with the #AESCBC_open() call. Default values for + * these parameters are set using #AESCBC_Params_init(). + * + * @sa #AESCBC_Params_init() + */ +typedef struct { + AESCBC_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESCBC_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESCBC_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESCBC_Params; + +/*! + * @brief Default #AESCBC_Params structure + * + * @sa #AESCBC_Params_init() + */ +extern const AESCBC_Params AESCBC_defaultParams; + +/*! + * @brief This function initializes the CBC module. + * + * @pre The AESCBC_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other CBC driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESCBC_init(void); + +/*! + * @brief Function to initialize the #AESCBC_Params struct to its defaults + * + * @param params An pointer to #AESCBC_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESCBC_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESCBC_Params_init(AESCBC_Params *params); + +/*! + * @brief This function opens a given CBC peripheral. + * + * @pre CBC controller has been initialized using #AESCBC_init() + * + * @param index Logical peripheral number for the CBC indexed into + * the AESCBC_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An #AESCBC_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa #AESCBC_init() + * @sa #AESCBC_close() + */ +AESCBC_Handle AESCBC_open(uint_least8_t index, AESCBC_Params *params); + +/*! + * @brief Function to close a CBC peripheral specified by the CBC handle + * + * @pre #AESCBC_open() has to be called first. + * + * @param handle A CBC handle returned from #AESCBC_open() + * + * @sa #AESCBC_open() + */ +void AESCBC_close(AESCBC_Handle handle); + +/*! + * @brief Function to initialize an #AESCBC_Operation struct to its defaults + * + * @param operationStruct A pointer to an #AESCBC_Operation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESCBC_Operation_init(AESCBC_Operation *operationStruct); + +/*! + * @brief Function to perform an AESCBC encryption operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted ciphertext. + * + * @pre #AESCBC_open() and #AESCBC_Operation_init() must be called first. + * + * @param [in] handle A CBC handle returned from #AESCBC_open() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESCBC_STATUS_SUCCESS The operation succeeded. + * @retval #AESCBC_STATUS_ERROR The operation failed. + * @retval #AESCBC_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCBC_STATUS_CANCELED The operation was canceled. + * + * @sa #AESCBC_oneStepDecrypt() + */ +int_fast16_t AESCBC_oneStepEncrypt(AESCBC_Handle handle, AESCBC_Operation *operationStruct); + +/*! + * @brief Function to perform an AESCBC decryption operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted plaintext. + * + * @pre AESCBC_open() and AESCBC_Operation_init() must be called first. + * + * @param [in] handle A CBC handle returned from AESCBC_open() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESCBC_STATUS_SUCCESS The operation succeeded. + * @retval #AESCBC_STATUS_ERROR The operation failed. + * @retval #AESCBC_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCBC_STATUS_CANCELED The operation was canceled. + * + * @sa AESCBC_oneStepEncrypt() + */ +int_fast16_t AESCBC_oneStepDecrypt(AESCBC_Handle handle, AESCBC_Operation *operationStruct); + +/*! + * @brief Cancels an ongoing AESCBC operation. + * + * Asynchronously cancels an AESCBC operation. Only available when using + * AESCBC_RETURN_BEHAVIOR_CALLBACK or AESCBC_RETURN_BEHAVIOR_BLOCKING. + * The operation will terminate as though an error occured. The + * return status code of the operation will be AESCBC_STATUS_CANCELED. + * + * @param [in] handle Handle of the operation to cancel + * + * @retval #AESCBC_STATUS_SUCCESS The operation was canceled. + * @retval #AESCBC_STATUS_ERROR The operation was not canceled. There may be no operation to cancel. + */ +int_fast16_t AESCBC_cancelOperation(AESCBC_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCBC__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCCM.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCCM.c new file mode 100644 index 0000000..e4298db --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCCM.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESCCM.c ======== + * + * This file contains default values for the AESCCM_Params struct. + * + */ + +#include +#include +#include + +#include +#include + +const AESCCM_Params AESCCM_defaultParams = { + .returnBehavior = AESCCM_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESCCM_Params_init ======== + */ +void AESCCM_Params_init(AESCCM_Params *params){ + *params = AESCCM_defaultParams; +} + +/* + * ======== AESCCM_Operation_init ======== + */ +void AESCCM_Operation_init(AESCCM_Operation *operationStruct) { + memset(operationStruct, 0x00, sizeof(AESCCM_Operation)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCCM.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCCM.h new file mode 100644 index 0000000..b7181ce --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCCM.h @@ -0,0 +1,696 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCCM.h + * + * @brief AESCCM driver header + * + * @warning This is a beta API. It may change in future releases. + * + * @anchor ti_drivers_AESCCM_Overview + * # Overview # + * The Counter with CBC-MAC (CCM) mode of operation is a generic + * authenticated encryption block cipher mode. It can be used with + * any block cipher. + * AESCCM combines CBC-MAC with an AES block cipher in CTR mode of operation. + * + * This combination of block cipher modes enables CCM to encrypt messages of any + * length and not only multiples of the block cipher block size. + * + * CTR provides confidentiality. The defined application of CBC-MAC provides + * message integrity and authentication. + * + * AESCCM has the following inputs and outputs: + * + * + * + * + * + * + * + * + * + * + * + * + * + *
AES-CCM input and output parameters
EncryptionDecryption
Input
Shared AES key Shared AES key
NonceNonce
CleartextCiphertext
MAC
AAD (optional)AAD (optional)
Output
CiphertextCleartext
MAC
+ * + * The AES key is a shared secret between the two parties and has a length + * between 128, 192, or 256 bits. + * + * The nonce is generated by the party performing the authenticated + * encryption operation. Within the scope of any authenticated + * encryption key, the nonce value must be unique. That is, the set of + * nonce values used with any given key must not contain any duplicate + * values. Using the same nonce for two different messages encrypted + * with the same key destroys the security properties. + * + * The length of the nonce determines the maximum number of messages that may + * be encrypted and authenticated before you must regenerate the key. + * Reasonable session key rotation schemes will regenerate the key before reaching + * this limit. + * There is a trade-off between the nonce-length and the maximum length of + * the plaintext to encrypt and authenticate per nonce. This is because + * CTR concatenates the nonce and an internal counter into one 16-byte + * IV. The counter is incremented after generating an AES-block-sized + * pseudo-random bitstream. This bitstream is XOR'd with the plaintext. + * The counter would eventually roll over for a sufficiently long message. + * This is must not happen. Hence, the longer the nonce and the more messages + * you can send before needing to rotate the key, the shorter the + * lengths of invidual messages sent may be. The minimum and maximum + * nonce length defined by the CCM standard provide for both a reasonable + * number of messages before key rotation and a reasonable maximum message length. + * Check NIST SP 800-38C for details. + * + * The optional additional authentication data (AAD) is authenticated + * but not encrypted. Thus, the AAD is not included in the AES-CCM output. + * It can be used to authenticate packet headers. + * + * After the encryption operation, the ciphertext contains the encrypted + * data. The message authentication code (MAC) is also provided. + * + * # CCM Variations # + * The AESCCM driver supports both classic CCM as defined by NIST SP 800-38C and + * the CCM* variant used in IEEE 802.15.4. + * CCM* allows for unauthenticated encryption using CCM by permitting a MAC length + * of 0. It also imposes the requirement that the MAC length be embedded in + * the nonce used for each message if the MAC length varies within the protocol + * using CCM*. + * + * @anchor ti_drivers_AESCCM_Usage + * # Usage # + * + * ## Before starting a CCM operation # + * + * Before starting a CCM operation, the application must do the following: + * - Call AESCCM_init() to initialize the driver + * - Call AESCCM_Params_init() to initialize the AESCCM_Params to default values. + * - Modify the AESCCM_Params as desired + * - Call AESCCM_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque datastructures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store, key blob), the CryptoKey must be + * initialized differently. The AESCCM API can handle all types of CryptoKey. + * However, not all device-specific implementions support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialise the AESCCM_Operation using AESCCM_Operation_init() and set all + * length, key, and buffer fields. + * + * ## Starting a CCM operation # + * + * The AESCCM_oneStepEncrypt and AESCCM_oneStepDecrypt functions do a CCM operation in a single call. + * They will always be the most highly optimized routines with the least overhead and the fastest + * runtime. However, they require all AAD and plaintext or ciphertext data to be + * available to the function at the start of the call. + * All devices support single call operations. + * + * When performing a decryption operation with AESCCM_oneStepDecrypt(), the MAC is + * automatically verified. + * + * ## After the CCM operation completes # + * + * After the CCM operation completes, the application should either start another operation + * or close the driver by calling AESCCM_close() + * + * @anchor ti_drivers_AESCCM_Synopsis + * ## Synopsis + * + * @anchor ti_drivers_AESCCM_Synopsis_Code + * @code + * + * // Import AESCCM Driver definitions + * #include + * + * // Define name for AESCCM channel index + * #define AESCCM_INSTANCE 0 + * + * AESCCM_init(); + * + * handle = AESCCM_open(AESCCM_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESCCM_Operation + * AESCCM_Operation_init(&operation); + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.nonce = nonce; + * operation.nonceLength = sizeof(nonce); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * encryptionResult = AESCCM_oneStepEncrypt(handle, &operation); + * + * AESCCM_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCCM_Examples + * ## Examples + * + * ### Single call CCM encryption + authentication with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * AESCCM_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * uint8_t nonce[] = "Thisisanonce"; + * uint8_t aad[] = "This string will be authenticated but not encrypted."; + * uint8_t plaintext[] = "This string will be encrypted and authenticated."; + * uint8_t mac[16]; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[32] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + * 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F} + * + * handle = AESCCM_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCCM_Operation operation; + * AESCCM_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.nonce = nonce; + * operation.nonceLength = sizeof(nonce); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * encryptionResult = AESCCM_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_close(handle); + * + * @endcode + * + * ### Single call CCM decryption + verification with plaintext CryptoKey in callback return mode # + * @code + * + * #include + * #include + * + * ... + * + * // The following test vector is Packet Vector 1 from RFC 3610 of the IETF. + * + * uint8_t nonce[] = {0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0xA0, + * 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}; + * uint8_t aad[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}; + * uint8_t mac[] = {0x17, 0xE8, 0xD1, 0x2C, 0xFD, 0xF9, 0x26, 0xE0}; + * uint8_t ciphertext[] = {0x58, 0x8C, 0x97, 0x9A, 0x61, 0xC6, 0x63, 0xD2, + * 0xF0, 0x66, 0xD0, 0xC2, 0xC0, 0xF9, 0x89, 0x80, + * 0x6D, 0x5F, 0x6B, 0x61, 0xDA, 0xC3, 0x84}; + * uint8_t keyingMaterial[] = {0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, + * 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // {0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * // 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * // 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E} + * + * + * void ccmCallback(AESCCM_Handle handle, + * int_fast16_t returnValue, + * AESCCM_Operation *operation, + * AESCCM_OperationType operationType) { + * + * if (returnValue != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * } + * + * AESCCM_Operation operation; + * + * void ccmStartFunction(void) { + * AESCCM_Handle handle; + * AESCCM_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESCCM_Params_init(¶ms); + * params.returnBehavior = AESCCM_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ccmCallback; + * + * handle = AESCCM_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCCM_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.nonce = nonce; + * operation.nonceLength = sizeof(nonce); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * decryptionResult = AESCCM_oneStepDecrypt(handle, &operation); + * + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while CCM operation completes in the background + * + * } + * + * + * @endcode + */ + +#ifndef ti_drivers_AESCCM__include +#define ti_drivers_AESCCM__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include + +/*! + * Common AESCCM status code reservation offset. + * AESCCM driver implementations should offset status codes with + * AESCCM_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESCCMXYZ_STATUS_ERROR0 AESCCM_STATUS_RESERVED - 0 + * #define AESCCMXYZ_STATUS_ERROR1 AESCCM_STATUS_RESERVED - 1 + * #define AESCCMXYZ_STATUS_ERROR2 AESCCM_STATUS_RESERVED - 2 + * @endcode + */ +#define AESCCM_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return AESCCM_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESCCM_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return AESCCM_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESCCM_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESCCM driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESCCM_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief An error status code returned if the MAC provided by the application for + * a decryption operation does not match the one calculated during the operation. + * + * This code is returned by AESCCM_oneStepDecrypt() if the verification of the + * MAC fails. + */ +#define AESCCM_STATUS_MAC_INVALID (-3) + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESCCM_STATUS_CANCELED (-4) + +/*! + * @brief A handle that is returned from an AESCCM_open() call. + */ +typedef struct AESCCM_Config *AESCCM_Handle; + +/*! + * @brief The way in which CCM function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all CCM operations exhibit the specified return behavor. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specfied return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESCCM functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |AESCCM_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESCCM_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESCCM_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum { + AESCCM_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * CCM operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESCCM_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the CCM operation goes + * on in the background. CCM operation results are available + * after the function returns. + */ + AESCCM_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while CCM + * operation goes on in the background. CCM operation results + * are available after the function returns. + */ +} AESCCM_ReturnBehavior; + +/*! + * @brief Enum for the direction of the CCM operation. + */ +typedef enum { + AESCCM_MODE_ENCRYPT = 1, + AESCCM_MODE_DECRYPT = 2, +} AESCCM_Mode; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * and authenticating/verifying a message. + */ +typedef struct { + CryptoKey *key; /*!< A previously initialized CryptoKey */ + uint8_t *aad; /*!< A buffer of length \c aadLength containing additional + * authentication data to be authenticated/verified but not + * encrypted/decrypted. + */ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be encrypted and authenticated + * in the CCM operation. + * - Decryption: The ciphertext to be decrypted and verified. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted and verified + * ciphertext is copied here. + */ + uint8_t *nonce; /*!< A buffer containing a nonce. Nonces must be unique to + * each CCM operation and may not be reused. If + * nonceInternallyGenerated is set the nonce will be + * generated by this function call and copied to + * this buffer. + */ + uint8_t *mac; /*!< + * - Encryption: The buffer where the message authentication + * code is copied. + * - Decryption: The buffer containing the received message + * authentication code. + */ + size_t aadLength; /*!< Length of \c aad in bytes. Either \c aadLength or + * \c plaintextLength must benon-zero. + * encrypted. + */ + size_t inputLength; /*!< Length of the input and output in bytes. Either \c aadLength or + * \c inputLength must be + * non-zero. + */ + uint8_t nonceLength; /*!< Length of \c nonce in bytes. + * Valid nonce lengths are [7, 8, ... 13]. + */ + uint8_t macLength; /*!< Length of \c mac in bytes. + * Valid MAC lengths are [0, 4, 6, 8, 10, 12, 14, 16]. + * A length of 0 disables authentication and verification. This is + * only permitted when using CCM*. + */ + bool nonceInternallyGenerated; /*!< When true, the nonce buffer passed into the AESCCM_setupEncrypt() + * and AESCCM_oneStepEncrypt() functions will be overwritten with a + * randomly generated nonce. Not supported by all implementations. + */ +} AESCCM_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum { + AESCCM_OPERATION_TYPE_ENCRYPT = 1, + AESCCM_OPERATION_TYPE_DECRYPT = 2, +} AESCCM_OperationType; + +/*! + * @brief AESCCM Global configuration + * + * The AESCCM_Config structure contains a set of pointers used to characterize + * the AESCCM driver implementation. + * + * This structure needs to be defined before calling AESCCM_init() and it must + * not be changed thereafter. + * + * @sa AESCCM_init() + */ +typedef struct AESCCM_Config { + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} AESCCM_Config; + +/*! + * @brief The definition of a callback function used by the AESCCM driver + * when used in ::AESCCM_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the CCM operation. + * + * @param returnValue The result of the CCM operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operation A pointer to an operation struct. + * + * @param operationType This parameter determines which operation the + * callback refers to. + */ +typedef void (*AESCCM_CallbackFxn) (AESCCM_Handle handle, + int_fast16_t returnValue, + AESCCM_Operation *operation, + AESCCM_OperationType operationType); + +/*! + * @brief CCM Parameters + * + * CCM Parameters are used to with the AESCCM_open() call. Default values for + * these parameters are set using AESCCM_Params_init(). + * + * @sa AESCCM_Params_init() + */ +typedef struct { + AESCCM_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESCCM_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESCCM_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESCCM_Params; + +/*! + * @brief Default AESCCM_Params structure + * + * @sa AESCCM_Params_init() + */ +extern const AESCCM_Params AESCCM_defaultParams; + +/*! + * @brief This function initializes the CCM module. + * + * @pre The AESCCM_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other CCM driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESCCM_init(void); + +/*! + * @brief Function to initialize the AESCCM_Params struct to its defaults + * + * @param params An pointer to AESCCM_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESCCM_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESCCM_Params_init(AESCCM_Params *params); + +/*! + * @brief This function opens a given CCM peripheral. + * + * @pre CCM controller has been initialized using AESCCM_init() + * + * @param index Logical peripheral number for the CCM indexed into + * the AESCCM_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An AESCCM_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa AESCCM_init() + * @sa AESCCM_close() + */ +AESCCM_Handle AESCCM_open(uint_least8_t index, AESCCM_Params *params); + +/*! + * @brief Function to close a CCM peripheral specified by the CCM handle + * + * @pre AESCCM_open() has to be called first. + * + * @param handle A CCM handle returned from AESCCM_open() + * + * @sa AESCCM_open() + */ +void AESCCM_close(AESCCM_Handle handle); + +/*! + * @brief Function to initialize an AESCCM_Operation struct to its defaults + * + * @param operationStruct A pointer to an AESCCM_Operation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESCCM_Operation_init(AESCCM_Operation *operationStruct); + +/*! + * @brief Function to perform an AESCCM encryption + authentication operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted ciphertext or incorrect authentication. + * + * @pre AESCCM_open() and AESCCM_Operation_init() have to be called first. + * + * @param [in] handle A CCM handle returned from AESCCM_open() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCCM_STATUS_CANCELED The operation was canceled. + * + * @sa AESCCM_oneStepDecrypt() + */ +int_fast16_t AESCCM_oneStepEncrypt(AESCCM_Handle handle, AESCCM_Operation *operationStruct); + +/*! + * @brief Function to perform an AESCCM decryption + verification operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted plaintext or incorrectly failed verification. + * + * @pre AESCCM_open() and AESCCM_Operation_init() have to be called first. + * + * @param [in] handle A CCM handle returned from AESCCM_open() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCCM_STATUS_CANCELED The operation was canceled. + * @retval #AESCCM_STATUS_MAC_INVALID The provided MAC did no match the recomputed one. + * + * @sa AESCCM_oneStepEncrypt() + */ +int_fast16_t AESCCM_oneStepDecrypt(AESCCM_Handle handle, AESCCM_Operation *operationStruct); + +/*! + * @brief Cancels an ongoing AESCCM operation. + * + * Asynchronously cancels an AESCCM operation. Only available when using + * AESCCM_RETURN_BEHAVIOR_CALLBACK or AESCCM_RETURN_BEHAVIOR_BLOCKING. + * The operation will terminate as though an error occured. The + * return status code of the operation will be AESCCM_STATUS_CANCELED. + * + * @param [in] handle Handle of the operation to cancel + * + * @retval #AESCBC_STATUS_SUCCESS The operation was canceled. + * @retval #AESCBC_STATUS_ERROR The operation was not canceled. + */ +int_fast16_t AESCCM_cancelOperation(AESCCM_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCCM__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTR.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTR.c new file mode 100644 index 0000000..0838fbf --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTR.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESCTR.c ======== + * + * This file contains default values for the AESCTR_Params struct. + * + */ + +#include +#include +#include + +#include +#include + +const AESCTR_Params AESCTR_defaultParams = { + .returnBehavior = AESCTR_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESCTR_Params_init ======== + */ +void AESCTR_Params_init(AESCTR_Params *params){ + *params = AESCTR_defaultParams; +} + +/* + * ======== AESCTR_Operation_init ======== + */ +void AESCTR_Operation_init(AESCTR_Operation *operationStruct) { + memset(operationStruct, 0x00, sizeof(AESCTR_Operation)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTR.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTR.h new file mode 100644 index 0000000..4096141 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTR.h @@ -0,0 +1,636 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCTR.h + * + * @brief AESCTR driver header + * + * @warning This is a beta API. It may change in future releases. + * + * @anchor ti_drivers_AESCTR_Overview + *

Overview

+ * The Counter (CTR) mode of operation is a generic block cipher mode of operation + * that can be used with any block cipher including AES. + * + * CTR mode encrypts and decrypts messages. It is not required for the message + * length to be evenly divisible by the cipher block size. This also means + * that padding the message is not required. + * + *

Operation

+ * CTR encryption and decryption perform the following steps: + * -# Set the counter value to the initial counter value + * -# Encrypt the counter value under the symmetric key + * -# XOR the encrypted counter value with the input block (plaintext or ciphertext) + * -# Increment the counter value. Interpret the byte array as a big-endian number. + * -# Repeat steps 2 to 4 until the input is completely processed. If the + * input is not evenly divisible by the block size, XOR the last + * (u = input length % block size) input bytes with the most significant + * u bytes of the last encrypted counter value. + * + * CTR performs the same steps regardless of whether it is used to + * encrypt or decrypt a message. The input merely changes. + * + *

Choosing Initial Counter Values

+ * CTR requires that each counter value used to encrypt a block of a message + * is unique for each key used. If this requirement is not kept, the + * confidentiality of that message block may be compromised. + * + * There are two general strategies when choosing the initial counter value + * of a CTR operation to ensure this requirement holds. + * + * The first is to choose an initial counter value for the first message + * and increment the initial counter value for a subsequent message by + * by message length % block length (16-bytes for AES). This effectively + * turns a sequence of messages into one long message. If 0 is chosen + * as the initial counter value, up to 2^128 - 1 blocks may be encrypted before + * key rotation is mandatory. + * + * The second is to split the initial counter value into a nonce and + * counter section. The nonce of length n bits must be unique per message. + * This allows for up to 2^n - 1 messages to be encrypted before + * key rotation is required. The counter section of length c is incremented + * as usual. This limits messages to a length of at most 2^c - 1 blocks. + * n and c must be chosen such that n + c = block length in bits + * (128 bits for AES) holds. + * + * @anchor ti_drivers_AESCTR_Usage + *

Usage

+ *

Before starting a CTR operation

+ * + * Before starting a CTR operation, the application must do the following: + * - Call #AESCTR_init() to initialize the driver + * - Call #AESCTR_Params_init() to initialize the #AESCTR_Params to default values. + * - Modify the #AESCTR_Params as desired + * - Call #AESCTR_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store, key blob), the CryptoKey must be + * initialized differently. The AESCTR API can handle all types of CryptoKey. + * However, not all device-specific implementions support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize the #AESCTR_Operation using #AESCTR_Operation_init() and set all + * length, key, and buffer fields. + * + *

Starting a CTR operation

+ * + * The AESCTR_oneStepEncrypt() and AESCTR_oneStepDecrypt() functions perform a CTR operation + * in a single call. + * + *

After the CTR operation completes

+ * + * After the CTR operation completes, the application should either start + * another operation or close the driver by calling #AESCTR_close(). + * + * @anchor ti_drivers_AESCTR_Synopsis + * ## Synopsis + * + * @anchor ti_drivers_AESCTR_Synopsis_Code + * @code + * + * // Import AESCTR Driver definitions + * #include + * + * // Define name for AESCTR channel index + * #define AESCTR_INSTANCE 0 + * + * AESCTR_init(); + * + * handle = AESCTR_open(AESCTR_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESCTR_Operation + * AESCTR_Operation_init(&operation); + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.iv = iv; + * + * encryptionResult = AESCTR_oneStepEncrypt(handle, &operation); + * + * AESCTR_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCTR_Examples + *

Examples

+ * + *
Single call CTR encryption with plaintext CryptoKey in blocking return mode
+ * @code + * + * #include + * #include + * + * ... + * + * AESCTR_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * + * // For example purposes only. Generate IVs in a non-static way in practice. + * // Test vector from NIST SP 800-38A + * uint8_t initialCounter[16] = {0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + * 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff}; + * uint8_t plaintext[64] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, + * 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51, + * 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11, + * 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef, + * 0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17, + * 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10}; + * ruint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, + * 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}; + * + * handle = AESCTR_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * while(1); + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCTR_Operation operation; + * AESCTR_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.initialCounter = initialCounter; + * + * encryptionResult = AESCTR_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESCTR_STATUS_SUCCESS) { + * // handle error + * while(1); + * } + * + * // The ciphertext should be the following after the encryption operation: + * // 0x87, 0x4d, 0x61, 0x91, 0xb6, 0x20, 0xe3, 0x26, + * // 0x1b, 0xef, 0x68, 0x64, 0x99, 0x0d, 0xb6, 0xce, + * // 0x98, 0x06, 0xf6, 0x6b, 0x79, 0x70, 0xfd, 0xff, + * // 0x86, 0x17, 0x18, 0x7b, 0xb9, 0xff, 0xfd, 0xff, + * // 0x5a, 0xe4, 0xdf, 0x3e, 0xdb, 0xd5, 0xd3, 0x5e, + * // 0x5b, 0x4f, 0x09, 0x02, 0x0d, 0xb0, 0x3e, 0xab, + * // 0x1e, 0x03, 0x1d, 0xda, 0x2f, 0xbe, 0x03, 0xd1, + * // 0x79, 0x21, 0x70, 0xa0, 0xf3, 0x00, 0x9c, 0xee + * + * AESCTR_close(handle); + * + * @endcode + * + *
Single call CTR decryption with plaintext CryptoKey in callback return mode
+ * @code + * + * #include + * #include + * + * ... + * + * + * void ctrCallback(AESCTR_Handle handle, + * int_fast16_t returnValue, + * AESCTR_Operation *operation, + * AESCTR_OperationType operationType) { + * + * if (returnValue != AESCTR_STATUS_SUCCESS) { + * // handle error + * while(1); + * } + * } + * AESCTR_Operation operation; + * + * void ctrStartFunction(void) { + * uint8_t initialCounter[16] = {0x00, 0xE0, 0x01, 0x7B, 0x27, 0x77, 0x7F, 0x3F, + * 0x4A, 0x17, 0x86, 0xF0, 0x00, 0x00, 0x00, 0x01}; + * uint8_t ciphertext[] = {0xC1, 0xCF, 0x48, 0xA8, 0x9F, 0x2F, 0xFD, 0xD9, + * 0xCF, 0x46, 0x52, 0xE9, 0xEF, 0xDB, 0x72, 0xD7, + * 0x45, 0x40, 0xA4, 0x2B, 0xDE, 0x6D, 0x78, 0x36, + * 0xD5, 0x9A, 0x5C, 0xEA, 0xAE, 0xF3, 0x10, 0x53, + * 0x25, 0xB2, 0x07, 0x2F}; + * uint8_t keyingMaterial[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, + * 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * AESCTR_Handle handle; + * AESCTR_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESCTR_Operation operation; + * + * AESCTR_Params_init(¶ms); + * params.returnBehavior = AESCTR_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ctrCallback; + * + * handle = AESCTR_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * while(1); + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCTR_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = ciphertext; + * operation.output = plaintext; + * operation.inputLength = sizeof(ciphertext); + * operation.initialCounter = initialCounter; + * + * decryptionResult = AESCTR_oneStepDecrypt(handle, &operation); + * + * if (decryptionResult != AESCTR_STATUS_SUCCESS) { + * // handle error + * while(1); + * } + * + * // do other things while CTR operation completes in the background + * + * // After the operation completes and the callback is invoked, the resultant + * // plaintext should be + * // 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + * // 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * // 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * // 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + * // 0x20, 0x21, 0x22, 0x23 + * } + * + * @endcode + */ + +#ifndef ti_drivers_AESCTR__include +#define ti_drivers_AESCTR__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/*! + * Common AESCTR status code reservation offset. + * AESCTR driver implementations should offset status codes with + * #AESCTR_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESCTRXYZ_STATUS_ERROR0 AESCTR_STATUS_RESERVED - 0 + * #define AESCTRXYZ_STATUS_ERROR1 AESCTR_STATUS_RESERVED - 1 + * #define AESCTRXYZ_STATUS_ERROR2 AESCTR_STATUS_RESERVED - 2 + * @endcode + */ +#define AESCTR_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return #AESCTR_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESCTR_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return #AESCTR_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESCTR_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESCTR driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESCTR_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESCTR_STATUS_CANCELED (-3) + + +/*! + * @brief The way in which CTR function calls return after performing an + * encryption or decryption operation. + * + * Not all CTR operations exhibit the specified return behavor. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specfied return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESCTR functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |AESCTR_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESCTR_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESCTR_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum { + AESCTR_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * CTR operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESCTR_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the CTR operation goes + * on in the background. CTR operation results are available + * after the function returns. + */ + AESCTR_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while CTR + * operation goes on in the background. CTR operation results + * are available after the function returns. + */ +} AESCTR_ReturnBehavior; + +/*! + * @brief Enum for the direction of the CTR operation. + */ +typedef enum { + AESCTR_MODE_ENCRYPT = 1, + AESCTR_MODE_DECRYPT = 2, +} AESCTR_Mode; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * a message. + * + * The driver may access it at any point during the operation. It must remain + * in scope for the entire duration of the operation. + */ +typedef struct { + const CryptoKey *key; /*!< A previously initialized CryptoKey. */ + const uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be + * encrypted in the CTR operation. + * - Decryption: The ciphertext to be decrypted. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that + * the encrypted plaintext is copied to. + * - Decryption: The plaintext derived from the + * decrypted ciphertext is copied here. + */ + const uint8_t *initialCounter; /*!< A buffer containing an initial counter. Under + * the same key, each counter value may only be + * used to encrypt or decrypt a single input + * block. + */ + size_t inputLength; /*!< Length of the input and output in bytes. */ +} AESCTR_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum { + AESCTR_OPERATION_TYPE_ENCRYPT = 1, + AESCTR_OPERATION_TYPE_DECRYPT = 2, +} AESCTR_OperationType; + +/*! + * @brief AESCTR Global configuration + * + * The #AESCTR_Config structure contains a set of pointers used to characterize + * the AESCTR driver implementation. + * + * This structure needs to be defined before calling #AESCTR_init() and it must + * not be changed thereafter. + * + * @sa #AESCTR_init() + */ +typedef struct AESCTR_Config { + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} AESCTR_Config; + +/*! + * @brief A handle that is returned from an #AESCTR_open() call. + */ +typedef AESCTR_Config *AESCTR_Handle; + +/*! + * @brief The definition of a callback function used by the AESCTR driver + * when used in ::AESCTR_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the CTR operation. + * + * @param returnValue The result of the CTR operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operation A pointer to an operation struct. + * + * @param operationType This parameter determines which operation the + * callback refers to. + */ +typedef void (*AESCTR_CallbackFxn) (AESCTR_Handle handle, + int_fast16_t returnValue, + AESCTR_Operation *operation, + AESCTR_OperationType operationType); + +/*! + * @brief CTR Parameters + * + * CTR Parameters are used to with the #AESCTR_open() call. Default values for + * these parameters are set using #AESCTR_Params_init(). + * + * @sa #AESCTR_Params_init() + */ +typedef struct { + AESCTR_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESCTR_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESCTR_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESCTR_Params; + +/*! + * @brief Default #AESCTR_Params structure + * + * @sa #AESCTR_Params_init() + */ +extern const AESCTR_Params AESCTR_defaultParams; + +/*! + * @brief This function initializes the CTR module. + * + * @pre The AESCTR_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other CTR driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESCTR_init(void); + +/*! + * @brief Function to initialize the #AESCTR_Params struct to its defaults + * + * @param params An pointer to #AESCTR_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESCTR_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESCTR_Params_init(AESCTR_Params *params); + +/*! + * @brief This function opens a given AESCTR peripheral. + * + * @pre AESCTR driver has been initialized using #AESCTR_init() + * + * @param index Logical peripheral number for the CTR indexed into + * the AESCTR_config table + * + * @param params Pointer to a parameter block, if NULL it will use + * default values. + * + * @return A #AESCTR_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa #AESCTR_init() + * @sa #AESCTR_close() + */ +AESCTR_Handle AESCTR_open(uint_least8_t index, const AESCTR_Params *params); + +/*! + * @brief Function to close a CTR peripheral specified by the CTR handle + * + * @pre #AESCTR_open() has to be called first. + * + * @param handle A CTR handle returned from #AESCTR_open() + * + * @sa #AESCTR_open() + */ +void AESCTR_close(AESCTR_Handle handle); + +/*! + * @brief Function to initialize an #AESCTR_Operation struct to its defaults + * + * @param operationStruct A pointer to an #AESCTR_Operation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESCTR_Operation_init(AESCTR_Operation *operationStruct); + +/*! + * @brief Function to perform an AESCTR encryption operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted ciphertext. + * + * @pre #AESCTR_open() and #AESCTR_Operation_init() must be called first. + * + * @param [in] handle A CTR handle returned from #AESCTR_open() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESCTR_STATUS_SUCCESS The operation succeeded. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * @retval #AESCTR_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCTR_STATUS_CANCELED The operation was canceled. + * + * @sa #AESCTR_oneStepDecrypt() + */ +int_fast16_t AESCTR_oneStepEncrypt(AESCTR_Handle handle, AESCTR_Operation *operationStruct); + +/*! + * @brief Function to perform an AESCTR decryption operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted plaintext. + * + * @pre AESCTR_open() and AESCTR_Operation_init() must be called first. + * + * @param [in] handle A CTR handle returned from AESCTR_open() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESCTR_STATUS_SUCCESS The operation succeeded. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * @retval #AESCTR_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCTR_STATUS_CANCELED + * + * @sa AESCTR_oneStepEncrypt() + */ +int_fast16_t AESCTR_oneStepDecrypt(AESCTR_Handle handle, AESCTR_Operation *operationStruct); + +/*! + * @brief Cancels an ongoing AESCTR operation. + * + * Asynchronously cancels an AESCTR operation. Only available when using + * AESCTR_RETURN_BEHAVIOR_CALLBACK or AESCTR_RETURN_BEHAVIOR_BLOCKING. + * The operation will terminate as though an error occured. The + * return status code of the operation will be AESCTR_STATUS_CANCELED. + * + * @param handle Handle of the operation to cancel + * + * @retval #AESCTR_STATUS_SUCCESS The operation was canceled. + * @retval #AESCTR_STATUS_ERROR The operation was not canceled. There may be no operation to cancel. + */ +int_fast16_t AESCTR_cancelOperation(AESCTR_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCTR__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTRDRBG.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTRDRBG.c new file mode 100644 index 0000000..09e3c5d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTRDRBG.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESCTRDRBG.c ======== + * + * This file contains default values for the AESCTRDRBG_Params struct. + * + */ + +#include +#include +#include + +#include +#include + +const AESCTRDRBG_Params AESCTRDRBG_defaultParams = { + .keyLength = AESCTRDRBG_AES_KEY_LENGTH_128, + .reseedInterval = 10000, + .seed = NULL, + .personalizationData = NULL, + .personalizationDataLength = 0, + .returnBehavior = AESCTRDRBG_RETURN_BEHAVIOR_POLLING, + .custom = NULL, +}; + +/* + * ======== AESCTRDRBG_Params_init ======== + */ +void AESCTRDRBG_Params_init(AESCTRDRBG_Params *params){ + *params = AESCTRDRBG_defaultParams; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTRDRBG.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTRDRBG.h new file mode 100644 index 0000000..ba4bdd3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTRDRBG.h @@ -0,0 +1,516 @@ +/* + * Copyright (c) 2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCTRDRBG.h + * + * @brief AESCTRDRBG driver header + * + * @warning This is a beta API. It may change in future releases. + * + * @anchor ti_drivers_AESCTRDRBG_Overview + *

Overview

+ * AES_CTR_DRBG is a cryptographically secure deterministic random bit generator + * that is used to efficiently generate random numbers for use in keying material + * or other security related purposes. It is based on the AES block cipher + * operating in Counter (CTR) mode and is defined by NIST SP 800-90A. + * + * AES_CTR_DRBG derives a sequence of pseudo-random numbers based on an initial + * secret seed and additional, non-secret personalization data provided during + * instantiation. A sequence of random bits generated by AES_CTR_DRBG will have + * an equivalent entropy content of MIN(sequenceLength, security strength). + * The security strength is based on the seed length and the AES key length used + * in the AES_CTR_DRBG instance. + * + * | | AES-128 | AES-192 | AES-256 | + * |---------------------------------------|---------|---------|---------| + * | Security Strength (bits) | 128 | 192 | 256 | + * | Seed Length (bits) | 192 | 320 | 384 | + * | Personalization String Length (bits) | <= 192 | <= 320 | <= 384 | + * | Max Requests Between Reseeds | 2^48 | 2^48 | 2^48 | + * | Max Request Length (bits) | 2^19 | 2^19 | 2^19 | + * + *

Security Strength

+ * The seed must be sourced from a cryptographically secure source such as + * a true random number generator and contain seed length bits of entropy. + * Since the seed length is always larger than the security strength for + * any one AES key length, the output of one AES_CTR_DRBG instance may not + * be used to seed another instance of the same or higher security strength. + * + *

Reseeding

+ * Because of the way AES CTR operates, there are a limited number of output + * bitstreams that may be generated before the AES_CTR_DRBG instance must be + * reseeded. The time between reseeding is set by the number of random bit + * sequences generated not by their individual or combined lengths. Each time + * random bits are requested of the AES_CTR_DRBG instance by the application, + * the reseed counter is incremented by one regardless of how many bits at a + * time are requested. When this counter reaches the configured reseed limit, + * the AES_CTR_DRBG instance will return #AESCTRDRBG_STATUS_RESEED_REQUIRED + * until it is reseeded. + * + * The maximum permitted number of requests between reseeds is 2^48. + * The default counter is only 2^32 long for ease of implementation. + * A more conservative reseed limit may be configured by the application + * for increased security. + * + * A previously used seed may never be reused to reseed an AESCTRDRBG instance. + * The seed used to instantiate or reseed an instance must be generated by + * an approved entropy source and never be reused. + * + *

Derivation Function

+ * NIST specifies the the use of an optional derivation function to reduced + * enctropy and personalizationg string lengths longer than the seed + * length down to the seed length. This feature is not presently supported. + * + * @anchor ti_drivers_AESCTRDRBG_Usage + *

Usage

+ * + * This documentation provides a basic @ref ti_drivers_AESCTRDRBG_Synopsis + * "usage summary" and a set of @ref ti_drivers_AESCTRDRBG_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor ti_drivers_AESCTRDRBG_Synopsis + *

Synopsis

+ * @anchor ti_drivers_AESCTRDRBG_Synopsis_Code + * @code + * #include + * + * AESCTRDRBG_init(); + * + * // Instantiate the AESCTRDRBG instance + * AESCTRDRBG_Params_init(¶ms); + * params.keyLength = AESCTRDRBG_AES_KEY_LENGTH_128; + * params.reseedInterval = 0xFFFFFFFF; + * params.seed = seedBuffer; + * + * handle = AESCTRDRBG_open(0, ¶ms); + * + * result = AESCTRDRBG_getBytes(handle, &resultKey); + * + * reseedResult = AESCTRDRBG_reseed(handle, reseedBuffer, NULL, 0); + * + * AESCTRDRBG_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCTRDRBG_Examples + *

Examples

+ * + *

Instantiating an AESCTRDRBG Instance with TRNG

+ * @code + * + * #include + * #include + * #include + * + * ... + * + * AESCTRDRBG_Handle handle; + * AESCTRDRBG_Params params; + * TRNG_Handle trngHandle; + * CryptoKey seedKey; + * int_fast16_t result; + * + * uint8_t seedBuffer[AESCTRDRBG_SEED_LENGTH_AES_128]; + * + * // Generate the seed + * trngHandle = TRNG_open(0, NULL); + * + * if (trngHandle == NULL) { + * // Handle error + * while(1); + * } + * + * CryptoKeyPlaintext_initBlankKey(&seedKey, seedBuffer, AESCTRDRBG_SEED_LENGTH_AES_128); + * + * result = TRNG_generateEntropy(trngHandle, &seedKey); + * if (result != TRNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * TRNG_close(trngHandle); + * + * // Instantiate the AESCTRDRBG instance + * AESCTRDRBG_Params_init(¶ms); + * params.keyLength = AESCTRDRBG_AES_KEY_LENGTH_128; + * params.reseedInterval = 0xFFFFFFFF; + * params.seed = seedBuffer; + * + * handle = AESCTRDRBG_open(0, ¶ms); + * if (handle == NULL) { + * // Handle error + * while(1); + * } + * @endcode + * + *

Generating Random Data with Reseeding

+ * + * @code + * + * #include + * #include + * #include + * + * ... + * + * #define ENTROPY_REQUEST_LENGTH 256 + * + * AESCTRDRBG_Handle handle; + * TRNG_Handle trngHandle; + * CryptoKey entropyKey; + * int_fast16_t result; + * + * uint8_t entropyBuffer[ENTROPY_REQUEST_LENGTH]; + * + * // Initialise the AESCTRDRBG instance here + * ... + * + * // Start generating random numbers + * CryptoKeyPlaintext_initBlankKey(&entropyKey, entropyBuffer, ENTROPY_REQUEST_LENGTH); + * + * result = AESCTRDRBG_getBytes(handle, &resultKey); + * + * // Check return value and reseed if needed. This should happen only after many invocations + * // of AESCTRDRBG_getBytes(). + * if (result == AESCTRDRBG_STATUS_RESEED_REQUIRED) { + * TRNG_Handle trngHandle; + * CryptoKey seedKey; + * int_fast16_t reseedResult; + * uint8_t reseedBuffer[AESCTRDRBG_SEED_LENGTH_AES_128]; + * + * CryptoKeyPlaintext_initBlankKey(&seedKey, reseedBuffer, AESCTRDRBG_SEED_LENGTH_AES_128); + * + * reseedResult = TRNG_generateEntropy(trngHandle, &seedKey); + * if (reseedResult != TRNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * TRNG_close(trngHandle); + * + * reseedResult = AESCTRDRBG_reseed(handle, reseedBuffer, NULL, 0); + * if (reseedResult != AESCTRDRBG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * } + * else if (result != AESCTRDRBG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * @endcode + * + */ + +#ifndef ti_drivers_AESCTRDRBG__include +#define ti_drivers_AESCTRDRBG__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/*! + * Common AESCTRDRBG status code reservation offset. + * AESCTRDRBG driver implementations should offset status codes with + * #AESCTRDRBG_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESCTRDRBGXYZ_STATUS_ERROR0 AESCTRDRBG_STATUS_RESERVED - 0 + * #define AESCTRDRBGXYZ_STATUS_ERROR1 AESCTRDRBG_STATUS_RESERVED - 1 + * #define AESCTRDRBGXYZ_STATUS_ERROR2 AESCTRDRBG_STATUS_RESERVED - 2 + * @endcode + */ +#define AESCTRDRBG_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return #AESCTRDRBG_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESCTRDRBG_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return #AESCTRDRBG_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESCTRDRBG_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESCTRDRBG driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief The AESCTRDRBG instance must be reseeded. + * + * An AESCTRDRBG instance may only service a limited number of bit + * generation requests before reseeding with more entropy is required. + */ +#define AESCTRDRBG_STATUS_RESEED_REQUIRED (-3) + +/*! + * @brief The AES block size in bytes. + */ +#define AESCTRDRBG_AES_BLOCK_SIZE_BYTES 16 + +/*! + * @brief Length in bytes of the internal AES key used by an instance + */ +typedef enum { + AESCTRDRBG_AES_KEY_LENGTH_128 = 16, + AESCTRDRBG_AES_KEY_LENGTH_256 = 32, +} AESCTRDRBG_AES_KEY_LENGTH; + +/*! + * @brief Length in bytes of seed used to instantiate or reseed instance + */ +typedef enum { + AESCTRDRBG_SEED_LENGTH_AES_128 = AESCTRDRBG_AES_KEY_LENGTH_128 + AESCTRDRBG_AES_BLOCK_SIZE_BYTES, + AESCTRDRBG_SEED_LENGTH_AES_256 = AESCTRDRBG_AES_KEY_LENGTH_256 + AESCTRDRBG_AES_BLOCK_SIZE_BYTES, +} AESCTRDRBG_SEED_LENGTH; + +/*! + * @brief The way in which AESCTRDRBG function calls return after generating + * the requested entropy. + * + * Not all AESCTRDRBG operations exhibit the specified return behavor. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specfied return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESCTRDRBG functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |-------------------------------------|-------|-------|-------| + * |#AESCTRDRBG_RETURN_BEHAVIOR_BLOCKING | X | | | + * |#AESCTRDRBG_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum AESCTRDRBG_ReturnBehavior_ { + /*!< The function call will block while AESCTRDRBG operation goes + * on in the background. AESCTRDRBG operation results are available + * after the function returns. + */ + AESCTRDRBG_RETURN_BEHAVIOR_BLOCKING = AESCTR_RETURN_BEHAVIOR_BLOCKING, + /*!< The function call will continuously poll a flag while AESCTRDRBG + * operation goes on in the background. AESCTRDRBG operation results + * are available after the function returns. + */ + AESCTRDRBG_RETURN_BEHAVIOR_POLLING = AESCTR_RETURN_BEHAVIOR_POLLING, +} AESCTRDRBG_ReturnBehavior; + +/*! + * @brief AESCTRDRBG Global configuration + * + * The #AESCTRDRBG_Config structure contains a set of pointers used to characterize + * the AESCTRDRBG driver implementation. + * + * This structure needs to be defined before calling #AESCTRDRBG_init() and it must + * not be changed thereafter. + * + * @sa #AESCTRDRBG_init() + */ +typedef struct { + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} AESCTRDRBG_Config; + +/*! + * @brief A handle that is returned from an #AESCTRDRBG_open() call. + */ +typedef AESCTRDRBG_Config *AESCTRDRBG_Handle; + +/*! + * @brief AESCTRDRBG Parameters + * + * AESCTRDRBG Parameters are used to with the #AESCTRDRBG_open() call. Default values for + * these parameters are set using #AESCTRDRBG_Params_init(). + * + * @sa #AESCTRDRBG_Params_init() + */ +typedef struct { + AESCTRDRBG_AES_KEY_LENGTH keyLength; /*!< Length of the internal AES key + * of the driver instance. + */ + uint32_t reseedInterval; /*!< Number of random number generation + * requests before the application is + * required to reseed the driver. + */ + const void *seed; /*!< Entropy used to seed the internal + * state of the driver. Must be one of + * #AESCTRDRBG_SEED_LENGTH long depending + * on \c keyLength. + */ + const void *personalizationData; /*!< Optional non-secret personalization + * data to mix into the driver's internal + * state. + */ + size_t personalizationDataLength; /*!< Length of the optional + * \c personalizationData. Must satisfy + * 0 <= \c personalizationDataLength <= seed length. + */ + AESCTRDRBG_ReturnBehavior returnBehavior; /*!< Return behavior of the driver instance. + * #AESCTRDRBG_RETURN_BEHAVIOR_POLLING is + * strongly recommended unless requests + * for > 500 bytes with AES-256 or + * 1250 bytes for AES-128 will be common + * usecases for this driver instance. + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESCTRDRBG_Params; + +/*! + * @brief Default #AESCTRDRBG_Params structure + * + * @sa #AESCTRDRBG_Params_init() + */ +extern const AESCTRDRBG_Params AESCTRDRBG_defaultParams; + +/*! + * @brief This function initializes the AESCTRDRBG driver. + * + * @pre The #AESCTRDRBG_Config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other AESCTRDRBG driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESCTRDRBG_init(void); + +/*! + * @brief Function to initialize the #AESCTRDRBG_Params struct to its defaults + * + * @param [out] params Pointer to #AESCTRDRBG_Params structure for + * initialization + */ +void AESCTRDRBG_Params_init(AESCTRDRBG_Params *params); + +/*! + * @brief This function opens a given AESCTRDRBG instance. + * + * @pre AESCTRDRBG controller has been initialized using #AESCTRDRBG_init() + * + * @param [in] index Logical peripheral number for the AESCTRDRBG indexed into + * the #AESCTRDRBG_Config table + * + * @param [in] params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An #AESCTRDRBG_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa #AESCTRDRBG_init() + * @sa #AESCTRDRBG_close() + */ +AESCTRDRBG_Handle AESCTRDRBG_open(uint_least8_t index, const AESCTRDRBG_Params *params); + +/*! + * @brief Function to close an AESCTRDRBG peripheral specified by the #AESCTRDRBG_Handle + * + * @pre #AESCTRDRBG_open() has to be called first. + * + * @param [in] handle An #AESCTRDRBG_Handle returned from #AESCTRDRBG_open() + * + * @sa #AESCTRDRBG_open() + */ +void AESCTRDRBG_close(AESCTRDRBG_Handle handle); + +/*! + * @brief Generate a requested number of random bytes + * + * @param [in] handle An #AESCTRDRBG_Handle returned from #AESCTRDRBG_open() + * + * @param [in,out] randomBytes #CryptoKey describing how many random bytes are requested and + * where to put them. + * + * @retval #AESCTRDRBG_STATUS_SUCCESS Random bytes generated. + * @retval #AESCTRDRBG_STATUS_ERROR Random bytes not generated. + * @retval #AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE The requires hardware was unavailable. + * @retval #AESCTRDRBG_STATUS_RESEED_REQUIRED Reseed counter >= reseed limit. Reseed required. + */ +int_fast16_t AESCTRDRBG_getBytes(AESCTRDRBG_Handle handle, CryptoKey *randomBytes); + +/*! + * @brief Reseed an AESCTRDRBG instance. + * + * @param [in] handle An #AESCTRDRBG_Handle returned from #AESCTRDRBG_open() + * + * @param [in] seed Entropy to mix into the AESCTRDRBG instance state + * + * @param [in] additionalData Optional non-secret additional data to mix into the + * instance state. + * + * @param [in] additionalDataLength Length of the optional additional data. + * 0 <= \c additionalDataLength <= seed length of the + * instance. + * + * @retval #AESCTRDRBG_STATUS_SUCCESS Reseed successful. Reseed counter reset. + * @retval #AESCTRDRBG_STATUS_ERROR Reseed not successful. Reseed counter not reset. + * @retval #AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE The requires hardware was unavailable. + */ +int_fast16_t AESCTRDRBG_reseed(AESCTRDRBG_Handle handle, + const void *seed, + const void *additionalData, + size_t additionalDataLength); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCTRDRBG__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESECB.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESECB.c new file mode 100644 index 0000000..6b60de8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESECB.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESECB.c ======== + * + * This file contains default values for the AESECB_Params struct. + * + */ + +#include +#include +#include + +#include +#include + +const AESECB_Params AESECB_defaultParams = { + .returnBehavior = AESECB_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESECB_Params_init ======== + */ +void AESECB_Params_init(AESECB_Params *params){ + *params = AESECB_defaultParams; +} + +/* + * ======== AESECB_Operation_init ======== + */ +void AESECB_Operation_init(AESECB_Operation *operationStruct) { + memset(operationStruct, 0x00, sizeof(AESECB_Operation)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESECB.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESECB.h new file mode 100644 index 0000000..f1eee09 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESECB.h @@ -0,0 +1,578 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESECB.h + * + * @brief AESECB driver header + * + * @warning This is a beta API. It may change in future releases. + * + * @anchor ti_drivers_AESECB_Overview + * # Overview # + * The Electronic Code Book (ECB) mode of operation is a generic + * encryption block cipher mode. It can be used with any block cipher. + * AESECB encrypts or decrypts one or multiple blocks of plaintext or ciphertext + * using the Advanced Encryption Standard (AES) block cipher. + * Each input block is individually encrypted or decrypted. This means that + * blocks of ciphertext can be decrypted individually and out of order. + * Encrypting the same plaintext using the same key yields identical ciphertext. + * This raises several security issues. For this reason, it is not recommended + * that ECB be used unless interfacing with unupdatable legacy systems + * or where a standard specifies its use. Better alternatives would be an + * authenticated encryption with associated data (AEAD) mode such as + * CCM or GCM. + * + * The AES key is a shared secret between the two parties and has a length + * of 128, 192, or 256 bits. + * + * @anchor ti_drivers_AESECB_Usage + * # Usage # + * + * ## Before starting an ECB operation # + * + * Before starting an ECB operation, the application must do the following: + * - Call AESECB_init() to initialize the driver + * - Call AESECB_Params_init() to initialize the AESECB_Params to default values. + * - Modify the AESECB_Params as desired + * - Call AESECB_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque datastructures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store, key blob), the CryptoKey must be + * initialized differently. The AESECB API can handle all types of CryptoKey. + * However, not all device-specific implementions support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize the AESECB_Operation using AESECB_Operation_init() and set all + * length, key, and buffer fields. + * + * ## Starting an ECB operation # + * + * The AESECB_oneStepEncrypt and AESECB_oneStepDecrypt functions do an ECB operation in a single call. + * They will always be the most highly optimized routines with the least overhead and the fastest + * runtime. Since ECB plaintext blocks are simply encrypted with the block cipher block by block, + * there is no difference in the ciphertext between encrypting two blocks in one go or encypting + * each block individually. + * + * ## After the ECB operation completes # + * + * After the ECB operation completes, the application should either start another operation + * or close the driver by calling AESECB_close() + * + * @anchor ti_drivers_AESECB_Synopsis + * ## Synopsis + * @anchor ti_drivers_AESECB_Synopsis_Code + * @code + * // Import AESECB Driver definitions + * #include + * + * AESECB_init(); + * + * // Define name for AESECB channel index + * #define AESECB_INSTANCE 0 + * + * handle = AESECB_open(AESECB_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESECB_Operation + * AESECB_Operation_init(&operation); + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.iv = iv; + * + * encryptionResult = AESECB_oneStepEncrypt(handle, &operation); + * + * AESECB_close(handle); + * @endcode + * + * @anchor ti_drivers_AESECB_Examples + * + * ## Examples + * + * ### Encyption of multiple plaintext blocks in blocking mode # + * @code + * + * #include + * #include + * + * ... + * + * AESECB_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * uint8_t plaintext[] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, + * 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51}; + * uint8_t ciphertext[sizof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, + * 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c} + * + * handle = AESECB_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESECB_Operation operation; + * AESECB_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * + * encryptionResult = AESECB_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * // The resultant ciphertext should be: + * // 0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60, + * // 0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97, + * // 0xf5, 0xd3, 0xd5, 0x85, 0x03, 0xb9, 0x69, 0x9d, + * // 0xe7, 0x85, 0x89, 0x5a, 0x96, 0xfd, 0xba, 0xaf + * + * + * AESECB_close(handle); + * + * @endcode + * + * ### Single call ECB decryption in callback mode # + * @code + * + * #include + * #include + * + * ... + * + * uint8_t ciphertext[] = {0xf3, 0xee, 0xd1, 0xbd, 0xb5, 0xd2, 0xa0, 0x3c, + * 0x06, 0x4b, 0x5a, 0x7e, 0x3d, 0xb1, 0x81, 0xf8}; + * uint8_t keyingMaterial[32] = {0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, + * 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81, + * 0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7, + * 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * // 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * + * + * void ecbCallback(AESECB_Handle handle, + * int_fast16_t returnValue, + * AESECB_Operation *operation, + * AESECB_OperationType operationType) { + * + * if (returnValue != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * } + * + * AESECB_Operation operation; + * + * void ecbStartFunction(void) { + * AESECB_Handle handle; + * AESECB_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESECB_Params_init(¶ms); + * params.returnBehavior = AESECB_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ecbCallback; + * + * handle = AESECB_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESECB_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * + * decryptionResult = AESECB_oneStepDecrypt(handle, &operation); + * + * if (decryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while ECB operation completes in the background + * + * } + * + * + * @endcode + */ + +#ifndef ti_drivers_AESECB__include +#define ti_drivers_AESECB__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include + +/*! + * Common AESECB status code reservation offset. + * AESECB driver implementations should offset status codes with + * AESECB_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESECBXYZ_STATUS_ERROR0 AESECB_STATUS_RESERVED - 0 + * #define AESECBXYZ_STATUS_ERROR1 AESECB_STATUS_RESERVED - 1 + * #define AESECBXYZ_STATUS_ERROR2 AESECB_STATUS_RESERVED - 2 + * @endcode + */ +#define AESECB_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return AESECB_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESECB_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return AESECB_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESECB_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESECB driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESECB_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESECB_STATUS_CANCELED (-3) + +/*! + * @brief A handle that is returned from an AESECB_open() call. + */ +typedef struct AESECB_Config *AESECB_Handle; + +/*! + * @brief The way in which ECB function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all ECB operations exhibit the specified return behavor. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specfied return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESECB functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |AESECB_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESECB_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESECB_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum { + AESECB_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * ECB operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESECB_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECB operation goes + * on in the background. ECB operation results are available + * after the function returns. + */ + AESECB_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECB + * operation goes on in the background. ECB operation results + * are available after the function returns. + */ +} AESECB_ReturnBehavior; + +/*! + * @brief Enum for the direction of the ECB operation. + */ +typedef enum { + AESECB_MODE_ENCRYPT = 1, + AESECB_MODE_DECRYPT = 2, +} AESECB_Mode; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * and a message. + */ +typedef struct { + CryptoKey *key; /*!< A previously initialized CryptoKey */ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be encrypted + * in the ECB operation. + * - Decryption: The ciphertext to be decrypted. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted + * ciphertext is copied here. + */ + size_t inputLength; /*!< Length of the input and output in bytes. Must be a multiple of the + * AES block size (16 bytes) + */ +} AESECB_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum { + AESECB_OPERATION_TYPE_ENCRYPT = 1, + AESECB_OPERATION_TYPE_DECRYPT = 2, +} AESECB_OperationType; + +/*! + * @brief AESECB Global configuration + * + * The AESECB_Config structure contains a set of pointers used to characterize + * the AESECB driver implementation. + * + * This structure needs to be defined before calling AESECB_init() and it must + * not be changed thereafter. + * + * @sa AESECB_init() + */ +typedef struct AESECB_Config { + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} AESECB_Config; + +/*! + * @brief The definition of a callback function used by the AESECB driver + * when used in ::AESECB_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the ECB operation. + * + * @param returnValue The result of the CCM operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operation A pointer to an operation struct. + * + * @param operationType This parameter determines which operation the + * callback refers to. + */ +typedef void (*AESECB_CallbackFxn) (AESECB_Handle handle, + int_fast16_t returnValue, + AESECB_Operation *operation, + AESECB_OperationType operationType); + +/*! + * @brief ECB Parameters + * + * ECB Parameters are used to with the AESECB_open() call. Default values for + * these parameters are set using AESECB_Params_init(). + * + * @sa AESECB_Params_init() + */ +typedef struct { + AESECB_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESECB_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESECB_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESECB_Params; + +/*! + * @brief Default AESECB_Params structure + * + * @sa AESECB_Params_init() + */ +extern const AESECB_Params AESECB_defaultParams; + +/*! + * @brief This function initializes the ECB module. + * + * @pre The AESECB_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other ECB driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESECB_init(void); + +/*! + * @brief Function to initialize the AESECB_Params struct to its defaults + * + * @param params An pointer to AESECB_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESECB_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESECB_Params_init(AESECB_Params *params); + +/*! + * @brief This function opens a given ECB peripheral. + * + * @pre ECB controller has been initialized using AESECB_init() + * + * @param index Logical peripheral number for the ECB indexed into + * the AESECB_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An AESECB_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa AESECB_init() + * @sa AESECB_close() + */ +AESECB_Handle AESECB_open(uint_least8_t index, AESECB_Params *params); + +/*! + * @brief Function to close an ECB peripheral specified by the ECB handle + * + * @pre AESECB_open() has to be called first. + * + * @param handle An ECB handle returned from AESECB_open() + * + * @sa AESECB_open() + */ +void AESECB_close(AESECB_Handle handle); + +/*! + * @brief Function to initialize an AESECB_Operation struct to its defaults + * + * @param operationStruct An pointer to AESECB_Operation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESECB_Operation_init(AESECB_Operation *operationStruct); + +/*! + * @brief Function to perform an AESECB encryption operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted ciphertext or incorrect authentication. + * + * @pre AESECB_open() and AESECB_Operation_init() have to be called first. + * + * @param [in] handle An ECB handle returned from AESECB_open() + * + * @param [in] operation A pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESECB_STATUS_SUCCESS The operation succeeded. + * @retval #AESECB_STATUS_ERROR The operation failed. + * @retval #AESECB_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESECB_STATUS_CANCELED The operation was canceled. + * + * @sa AESECB_oneStepDecrypt() + */ +int_fast16_t AESECB_oneStepEncrypt(AESECB_Handle handle, AESECB_Operation *operation); + +/*! + * @brief Function to perform an AESECB decryption in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted plaintext or incorrectly failed verification. + * + * @pre AESECB_open() and AESECB_Operation_init() have to be called first. + * + * @param [in] handle An ECB handle returned from AESECB_open() + * + * @param [in] operation A pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESECB_STATUS_SUCCESS The operation succeeded. + * @retval #AESECB_STATUS_ERROR The operation failed. + * @retval #AESECB_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESECB_STATUS_CANCELED The operation was canceled. + * + * @sa AESECB_oneStepEncrypt() + */ +int_fast16_t AESECB_oneStepDecrypt(AESECB_Handle handle, AESECB_Operation *operation); + +/*! + * @brief Cancels an ongoing AESECB operation. + * + * Asynchronously cancels an AESECB operation. Only available when using + * AESECB_RETURN_BEHAVIOR_CALLBACK or AESECB_RETURN_BEHAVIOR_BLOCKING. + * The operation will terminate as though an error occured. The + * return status code of the operation will be AESECB_STATUS_CANCELED. + * + * @param handle Handle of the operation to cancel + * + * @retval #AESECB_STATUS_SUCCESS The operation was canceled. + * @retval #AESECB_STATUS_ERROR The operation was not canceled. There may be no operation to cancel. + */ +int_fast16_t AESECB_cancelOperation(AESECB_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESECB__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESGCM.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESGCM.c new file mode 100644 index 0000000..cd60870 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESGCM.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESGCM.c ======== + * + * This file contains default values for the AESGCM_Params struct. + * + */ + +#include +#include +#include + +#include +#include + +const AESGCM_Params AESGCM_defaultParams = { + .returnBehavior = AESGCM_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESGCM_Params_init ======== + */ +void AESGCM_Params_init(AESGCM_Params *params){ + *params = AESGCM_defaultParams; +} + +/* + * ======== AESGCM_Operation_init ======== + */ +void AESGCM_Operation_init(AESGCM_Operation *operationStruct) { + memset(operationStruct, 0x00, sizeof(AESGCM_Operation)); + + /* The only supported ivLength is 12 for now */ + operationStruct->ivLength = 12; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESGCM.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESGCM.h new file mode 100644 index 0000000..d3fe33f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESGCM.h @@ -0,0 +1,676 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * + * @file AESGCM.h + * + * @brief AESGCM driver header + * + * @warning This is a beta API. It may change in future releases. + * + * @anchor ti_drivers_AESGCM_Overview + * ### Overview # + * + * The Galois Counter Mode (GCM) mode of operation is a generic + * authenticated encryption with associated data (AEAD) block cipher mode. + * It can be implemented with any block cipher. + * AESGCM combines GHASH with the AES block cipher in CTR mode of operation. + * + * This combination of block cipher modes enables GCM to encrypt messages of any + * length and not only multiples of the block cipher block size. + * + * CTR provides confidentiality. The using GHASH and encrypting the result provides + * message integrity and authentication. + * + * The AES key is a shared secret between the two parties and has a length + * of 128, 192, or 256 bits. + * + * The IV is generated by the party performing the authenticated + * encryption operation. Within the scope of any authenticated + * encryption key, the IV value must be unique. That is, the set of + * IV values used with any given key must not contain any duplicate + * values. Using the same IV for two different messages encrypted + * with the same key destroys the security properties of GCM. + * + * The optional additional authentication data (AAD) is authenticated + * but not encrypted. Thus, the AAD is not included in the AES-GCM output. + * It can be used to authenticate packet headers, timestamps and other + * metadata. + * + * After the encryption operation, the ciphertext contains the encrypted + * data and the message authentication code (MAC). + * + * GCM is highly performant for an AEAD mode. Counter with CBC-MAC requires + * one invocation per block of AAD and two invocations of the block cipher + * per proccessed block of input; one to compute the CBC-MAC and one to + * perform CTR. GCM substitutes the block cipher invocation during CBC-MAC + * computation with computing GHASH over the same input. GHASH is significantly + * faster per block than AES. In turn, this gives GCM a performance edge + * over CCM. + * + * ### Security Considerations + * + * In each operation, GCM limits the length of the input and AAD to guarantee + * its security properties: + * - inputLength <= 2^36 - 32 bytes + * - aadLength <= 2^61 - 1 bytes + * + * The security properties of GCM rely on the MAC size. While MAC lengths of + * [4, 8, 12, 13, 14, 15, 16] bytes are permitted, it is recommended to + * use the full 16-byte MAC. + * + * See NIST SP 800-38D for more a more detailed discussion of security + * considerations. + * + * @anchor ti_drivers_AESGCM_Usage + * ### Usage # + * + * #### Before starting a GCM operation # + * + * Before starting a GCM operation, the application must do the following: + * - Call AESGCM_init() to initialize the driver + * - Call AESGCM_Params_init() to initialize the #AESGCM_Params to default values. + * - Modify the #AESGCM_Params as desired + * - Call AESGCM_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque datastructures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store, key blob), the CryptoKey must be + * initialized differently. The AESGCM API can handle all types of CryptoKey. + * However, not all device-specific implementions support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialise the #AESGCM_Operation using AESGCM_Operation_init() and set all + * length, key, and buffer fields. + * + * #### Starting a GCM operation # + * + * The AESGCM_oneStepEncrypt() and AESGCM_oneStepDecrypt() functions perform a GCM operation in a single call. + * + * When performing a decryption operation with AESGCM_oneStepDecrypt(), the MAC is + * automatically verified. + * + * #### After the GCM operation completes # + * + * After the GCM operation completes, the application should either start another operation + * or close the driver by calling AESGCM_close() + * + * @anchor ti_drivers_AESGCM_Synopsis + * ## Synopsis + * + * @anchor ti_drivers_AESGCM_Synopsis_Code + * @code + * + * // Import AESGCM Driver definitions + * #include + * + * // Define name for AESGCM channel index + * #define AESGCM_INSTANCE 0 + * + * AESGCM_init(); + * + * handle = AESGCM_open(AESGCM_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESGCM_Operation + * AESGCM_Operation_init(&operation); + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.nonce = nonce; + * operation.nonceLength = sizeof(nonce); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * encryptionResult = AESGCM_oneStepEncrypt(handle, &operation); + * + * AESGCM_close(handle); + * @endcode + * + * @anchor ti_drivers_AESGCM_Examples + * #### Examples + * + * ##### Single call GCM encryption + authentication with plaintext CryptoKey in blocking return mode # + * + * @code + * + * #include + * #include + * + * ... + * + * AESGCM_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * uint8_t iv[12] = "12-byte IV "; + * uint8_t aad[] = "This string will be authenticated but not encrypted."; + * uint8_t plaintext[] = "This string will be encrypted and authenticated."; + * uint8_t mac[16]; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[32] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + * 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; + * + * handle = AESGCM_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESGCM_Operation operation; + * AESGCM_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.iv = iv; + * operation.ivLength = 12; + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * encryptionResult = AESGCM_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESGCM_close(handle); + * + * @endcode + * + * ##### Single call GCM decryption + verification with plaintext CryptoKey in callback return mode # + * + * @code + * + * #include + * #include + * + * ... + * + * // The following test vector is Packet Vector 1 from RFC 3610 of the IETF. + * + * uint8_t iv[] = {0x1f, 0x80, 0x3c, 0x52, 0xca, 0xc4, 0x97, 0xe1, + * 0x55, 0xaa, 0x55, 0x2d}; + * uint8_t aad[] = {0x3b, 0xba, 0x31, 0x28, 0x9d, 0x05, 0xf5, 0x0f, + * 0xed, 0x6c, 0x53, 0x35, 0x3c, 0x1f, 0x74, 0xd8, + * 0x28, 0xa9, 0x96, 0xb8, 0xd6, 0x84, 0xfe, 0x64, + * 0x7f, 0x7c, 0x40, 0xc0, 0xd5, 0x68, 0x8c, 0x89, + * 0x68, 0x1a, 0x33, 0xb1, 0x0c, 0xb7, 0x14, 0xb6, + * 0x49, 0x0b, 0xdf, 0x1f, 0x16, 0x60, 0x60, 0xa7}; + * uint8_t mac[] = {0x39, 0x03, 0xe4, 0xdc, 0xa4, 0xe7, 0xc8, 0x21, + * 0x62, 0x1a, 0xbb, 0xb2, 0x37, 0x2c, 0x97}; + * uint8_t ciphertext[] = {0xf8, 0x7e, 0xf7, 0x99, 0x4a, 0x86, 0xf3, 0xe9, + * 0xa3, 0xab, 0x6a, 0x6f, 0x2d, 0x34, 0x3b, 0xbd}; + * uint8_t keyingMaterial[] = {0x4f, 0xd7, 0xf2, 0x09, 0xdf, 0xb0, 0xdf, 0xbd, + * 0xd9, 0x8d, 0x2d, 0xb4, 0x98, 0x66, 0x4c, 0x88}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // 0x17, 0x9d, 0xcb, 0x79, 0x5c, 0x09, 0x8f, 0xc5, 0x31, 0x4b, 0xde, 0x0d, 0x39, 0x9d, 0x7a, 0x10 + * + * + * void gcmCallback(AESGCM_Handle handle, + * int_fast16_t returnValue, + * AESGCM_Operation *operation, + * AESGCM_OperationType operationType) { + * + * if (returnValue != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * } + * + * AESGCM_Operation operation; + * CryptoKey cryptoKey; + * + * void gcmStartFunction(void) { + * AESGCM_Handle handle; + * AESGCM_Params params; + * int_fast16_t decryptionResult; + * + * AESGCM_Params_init(¶ms); + * params.returnBehavior = AESGCM_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = gcmCallback; + * + * handle = AESGCM_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESGCM_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = ciphertext; + * operation.output = plaintext; + * operation.inputLength = sizeof(ciphertext); + * operation.iv = iv; + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * decryptionResult = AESGCM_oneStepDecrypt(handle, &operation); + * + * if (decryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while GCM operation completes in the background + * + * } + * @endcode + */ + +#ifndef ti_drivers_AESGCM__include +#define ti_drivers_AESGCM__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common AESGCM status code reservation offset. + * AESGCM driver implementations should offset status codes with + * AESGCM_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESGCMXYZ_STATUS_ERROR0 AESGCM_STATUS_RESERVED - 0 + * #define AESGCMXYZ_STATUS_ERROR1 AESGCM_STATUS_RESERVED - 1 + * #define AESGCMXYZ_STATUS_ERROR2 AESGCM_STATUS_RESERVED - 2 + * @endcode + */ +#define AESGCM_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return AESGCM_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESGCM_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return AESGCM_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESGCM_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESGCM driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESGCM_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief An error status code returned if the MAC provided by the application for + * a decryption operation does not match the one calculated during the operation. + * + * This code is returned by AESGCM_oneStepDecrypt() if the verification of the + * MAC fails. + */ +#define AESGCM_STATUS_MAC_INVALID (-3) + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESGCM_STATUS_CANCELED (-4) + +/*! + * @brief A handle that is returned from an AESGCM_open() call. + */ +typedef struct AESGCM_Config *AESGCM_Handle; + +/*! + * @brief The way in which GCM function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all GCM operations exhibit the specified return behavor. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specfied return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESGCM functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |AESGCM_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESGCM_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESGCM_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum { + AESGCM_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * GCM operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESGCM_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the GCM operation goes + * on in the background. GCM operation results are available + * after the function returns. + */ + AESGCM_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while GCM + * operation goes on in the background. GCM operation results + * are available after the function returns. + */ +} AESGCM_ReturnBehavior; + +/*! + * @brief Enum for the direction of the GCM operation. + */ +typedef enum { + AESGCM_MODE_ENCRYPT = 1, + AESGCM_MODE_DECRYPT = 2, +} AESGCM_Mode; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * and authenticating/verifying a message. + */ +typedef struct { + CryptoKey *key; /*!< A previously initialized CryptoKey */ + uint8_t *aad; /*!< A buffer of length \c aadLength containing additional + * authentication data to be authenticated/verified but not + * encrypted/decrypted. + */ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be encrypted and authenticated + * in the GCM operation. + * - Decryption: The ciphertext to be decrypted and verified. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted and verified + * ciphertext is copied here. + */ + uint8_t *iv; /*!< A buffer containing an IV. IVs must be unique to + * each GCM operation and may not be reused. If + * ivInternallyGenerated is set, the IV will be + * generated by this function call and copied to + * this buffer. + */ + uint8_t *mac; /*!< + * - Encryption: The buffer where the message authentication + * code is copied. + * - Decryption: The buffer containing the received message + * authentication code. + */ + size_t aadLength; /*!< Length of \c aad in bytes. Either \c aadLength or + * \c plaintextLength must benon-zero. + * encrypted. + */ + size_t inputLength; /*!< Length of the input and output in bytes. Either \c aadLength or + * \c inputLength must be + * non-zero. + */ + uint8_t ivLength; /*!< Length of \c IV in bytes. + * The only currently supported IV length is 12 bytes. + */ + uint8_t macLength; /*!< Length of \c mac in bytes. + * Valid MAC lengths are [4, 8, 12, 13, 14, 15, 16]. + */ + bool ivInternallyGenerated; /*!< When true, the IV buffer passed into the AESGCM_setupEncrypt() + * and AESGCM_oneStepEncrypt() functions will be overwritten with a + * randomly generated IV. Not supported by all implementations. + */ +} AESGCM_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum { + AESGCM_OPERATION_TYPE_ENCRYPT = 1, + AESGCM_OPERATION_TYPE_DECRYPT = 2, +} AESGCM_OperationType; + +/*! + * @brief AESGCM Global configuration + * + * The AESGCM_Config structure contains a set of pointers used to characterize + * the AESGCM driver implementation. + * + * This structure needs to be defined before calling AESGCM_init() and it must + * not be changed thereafter. + * + * @sa AESGCM_init() + */ +typedef struct AESGCM_Config { + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} AESGCM_Config; + +/*! + * @brief The definition of a callback function used by the AESGCM driver + * when used in ::AESGCM_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the GCM operation. + * + * @param returnValue The result of the GCM operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operation A pointer to an operation struct. + * + * @param operationType This parameter determines which operation the + * callback refers to. + */ +typedef void (*AESGCM_CallbackFxn) (AESGCM_Handle handle, + int_fast16_t returnValue, + AESGCM_Operation *operation, + AESGCM_OperationType operationType); + +/*! + * @brief GCM Parameters + * + * GCM Parameters are used to with the AESGCM_open() call. Default values for + * these parameters are set using AESGCM_Params_init(). + * + * @sa AESGCM_Params_init() + */ +typedef struct { + AESGCM_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESGCM_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESGCM_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESGCM_Params; + +/*! + * @brief Default AESGCM_Params structure + * + * @sa AESGCM_Params_init() + */ +extern const AESGCM_Params AESGCM_defaultParams; + +/*! + * @brief This function initializes the GCM module. + * + * @pre The AESGCM_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other GCM driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESGCM_init(void); + +/*! + * @brief Function to initialize the AESGCM_Params struct to its defaults + * + * @param params An pointer to AESGCM_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESGCM_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESGCM_Params_init(AESGCM_Params *params); + +/*! + * @brief This function opens a given GCM peripheral. + * + * @pre GCM controller has been initialized using AESGCM_init() + * + * @param index Logical peripheral number for the GCM indexed into + * the AESGCM_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An AESGCM_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa AESGCM_init() + * @sa AESGCM_close() + */ +AESGCM_Handle AESGCM_open(uint_least8_t index, AESGCM_Params *params); + +/*! + * @brief Function to close a GCM peripheral specified by the GCM handle + * + * @pre AESGCM_open() has to be called first. + * + * @param handle A GCM handle returned from AESGCM_open() + * + * @sa AESGCM_open() + */ +void AESGCM_close(AESGCM_Handle handle); + +/*! + * @brief Function to initialize an AESGCM_Operation struct to its defaults + * + * @param operationStruct A pointer to an AESGCM_Operation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESGCM_Operation_init(AESGCM_Operation *operationStruct); + +/*! + * @brief Function to perform an AESGCM encryption + authentication operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted ciphertext or incorrect authentication. + * + * @pre AESGCM_open() and AESGCM_Operation_init() have to be called first. + * + * @param [in] handle A GCM handle returned from AESGCM_open() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESGCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESGCM_STATUS_ERROR The operation failed. + * @retval #AESGCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESGCM_STATUS_CANCELED The operation was canceled. + * + * @sa AESGCM_oneStepDecrypt() + */ +int_fast16_t AESGCM_oneStepEncrypt(AESGCM_Handle handle, AESGCM_Operation *operationStruct); + +/*! + * @brief Function to perform an AESGCM decryption + verification operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted plaintext or incorrectly failed verification. + * + * @pre AESGCM_open() and AESGCM_Operation_init() have to be called first. + * + * @param [in] handle A GCM handle returned from AESGCM_open() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESGCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESGCM_STATUS_ERROR The operation failed. + * @retval #AESGCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESGCM_STATUS_CANCELED The operation was canceled. + * @retval #AESGCM_STATUS_MAC_INVALID The provided MAC did no match the recomputed one. + * + * @sa AESGCM_oneStepEncrypt() + */ +int_fast16_t AESGCM_oneStepDecrypt(AESGCM_Handle handle, AESGCM_Operation *operationStruct); + +/*! + * @brief Cancels an ongoing AESGCM operation. + * + * Asynchronously cancels an AESGCM operation. Only available when using + * AESGCM_RETURN_BEHAVIOR_CALLBACK or AESGCM_RETURN_BEHAVIOR_BLOCKING. + * The operation will terminate as though an error occured. The + * return status code of the operation will be AESGCM_STATUS_CANCELED. + * + * @param handle Handle of the operation to cancel + * + * @retval #AESCBC_STATUS_SUCCESS The operation was canceled. + * @retval #AESCBC_STATUS_ERROR The operation was not canceled. + */ +int_fast16_t AESGCM_cancelOperation(AESGCM_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESGCM__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Board.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Board.h new file mode 100644 index 0000000..bb9f047 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Board.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!**************************************************************************** + * @file Board.h + * @brief Portable board-specific symbols + * + * The Board header file should be included in an application as follows: + * @code + * #include "Board.h" + * @endcode + * + * This header serves as device-independent interface for applications using + * peripherals connected to the device via standard digital interfaces; e.g, + * GPIO, SPI, I2C, UART, etc. Its purpose is to enable application code that + * references a peripheral to be portable to any device and board that + * supports the peripheral. + * + * ## Usage ## + * + * @anchor ti_drivers_Board_Synopsis + * ### Synopsis # + * @anchor ti_drivers_Board_Synopsis_Code + * @code + * #include "Board.h" + * + * void main(void) + * { + * Board_init(); + * : + * } + * @endcode + * + * ## Initializing the hardware ## + * + * \p Board_init() must be called before any other driver API. This function + * calls the device specific initialization code that is required to as soon + * as possible after a device reset; e.g., to initialize clocks and power + * management functionality. + * + * ## Portable peripheral usage + * + * Each driver module declares symbols in \p Board.h that, if used, will + * improve code portability between both different devices and boards. + * + * @anchor ti_drivers_I2C_Example_portable + * For example, the I2C driver adds \p Board.h symbol definitions of the form + * * bus_name - the I2C bus instance ID, + * * bus_name_MAXBITRATE - the maximum supported BITRATE for the bus + * bus_name, and + * * Board_I2C_comp_name_ADDR - the slave address for the named I2C + * component + * where comp_name is the name given to an I2C peripheral by the + * board manufacturer, and bus_name is the user defined name of the + * I2C bus instance. These symbols enable applications to portably acquire + * an I2C bus handle and control an I2C slave on that bus. + * @code + * #include + * #include "Board.h" + * + * // portably open an I2C bus instance + * I2C_Params i2cParams; + * I2C_Params_init(&i2cParams); + * i2cParams.bitRate = Board_I2C0_MAXBITRATE; // bus name == Board_I2C0 + * i2cHandle = I2C_open(Board_I2C0, &i2cParams); + * + * // portably read from an I2C slave + * I2C_Transaction trans; + * trans.slaveAddress = Board_I2C_TMP006_ADDR; // component name = TMP006 + * trans.readBuf = ...; + * trans.readCount = ...; + * trans.writeCount = 0; + * I2C_transfer(i2cHandle, &trans); + * @endcode + ****************************************************************************** + */ + +#ifndef ti_boards_Board__include +#define ti_boards_Board__include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Performs "early" board-level initialization required by TI-DRIVERS + * + * Board_init() must be called before any other TI-DRIVER API. This function + * calls all device and board specific initialization functions needed by + * TI-DRIVERS; e.g., to initialize clocks and power management functionality. + * + * This function should only be called once and as early in the application's + * startup as possible. In most applications, a call to Board_init() is the + * first statement in \p main(). + * + * @pre \p Board_init must be called after every CPU reset and _prior_ to + * enabling any interrupts. + */ +extern void Board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_boards_Board_include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDH.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDH.c new file mode 100644 index 0000000..8cce5a4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDH.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ECDH.c ======== + * + * This file contains default values for the ECDH_Params struct + * + */ + +#include +#include + +#include +#include + +const ECDH_Params ECDH_defaultParams = { + .returnBehavior = ECDH_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== ECDH_OperationGeneratePublicKey_init ======== + */ +void ECDH_OperationGeneratePublicKey_init(ECDH_OperationGeneratePublicKey *operation){ + memset(operation, 0x00, sizeof(ECDH_OperationGeneratePublicKey)); +} +/* + * ======== ECDH_OperationComputeSharedSecret_init ======== + */ +void ECDH_OperationComputeSharedSecret_init(ECDH_OperationComputeSharedSecret *operation){ + memset(operation, 0x00, sizeof(ECDH_OperationComputeSharedSecret)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDH.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDH.h new file mode 100644 index 0000000..dd01626 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDH.h @@ -0,0 +1,696 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ECDH.h + * + * @brief TI Driver for Elliptic Curve Diffie-Hellman key agreement scheme. + * + * @warning This is a beta API. It may change in future releases. + * + * @anchor ti_drivers_ECDH_Overview + * # Overview # + * + * Elliptic Curve Diffie-Hellman (ECDH) is a key agreement scheme between + * two parties based on the Diffie-Hellman key exchange protocol. + * + * It provides a means of generating a shared secret and derived symmetric key + * between the two parties over an insecure channel. + * + * It does not provide authentication. As such, it does not guarantee that the + * party you are exchanging keys with is truly the party you wish to establish a + * secured channel with. + * + * The two parties each generate a private key and a public key. The private key + * is a random integer in the interval [1, n - 1], where n is the order of a + * previously agreed upon curve. The public key is generated + * by multiplying the private key by the generator point of a previously agreed + * upon elliptic curve such as NISTP256 or Curve 25519. The public key is itself + * a point upon the elliptic curve. Each public key is then transmitted to the + * other party over a potentially insecure channel. The other party's public key + * is then multiplied with the private key, generating a shared secret. This + * shared secret is also a point on the curve. However, the entropy in the secret + * is not spread evenly throughout the shared secret. In order to generate one or more + * shared symmetric keys, the shared secret must be run through a key derivation + * function (KDF) that was previously agreed upon. Usually, only the X coordinate + * is processed in this way as it contains all the entropy of the shared secret and + * some curve implementations only provide the X coordinate. The key derivation function + * can take many forms, from simply hashing the X coordinate of the shared secret + * with SHA2 and truncating the result to generating multiple symmetric keys with + * HKDF, an HMAC based KDF. + * + * Key derivation functions in the context of symmetric key generation after + * elliptic curve based key exchange differ from KDFs used to generate keys from + * passwords a user provides in a login. Those KDFs such as bcrypt purposefully + * add additional computation to increase a system's resistance against brute + * force or dictionary attacks. + * + * @anchor ti_drivers_ECDH_Usage + * # Usage # + * + * ## Before starting an ECDH operation # + * + * Before starting an ECDH operation, the application must do the following: + * - Call ECDH_init() to initialize the driver + * - Call ECDH_Params_init() to initialize the ECDH_Params to default values. + * - Modify the ECDH_Params as desired + * - Call ECDH_open() to open an instance of the driver + * + * ## Generating your public-private key pair # + * To generate a public-private key pair for an agreed upon curve, the application + * must do the following: + * - Generate the keying material for the private key. This keying material must + * be an integer in the interval [1, n - 1], where n is the order of the curve. + * It should be stored in an array with the least significant byte of the integer + * hex representation stored in the lowest address of the array (little-endian). + * The array should be the same length as the curve parameters of the curve used. + * The driver validates private keys against the provided curve by default. + * - Initialize the private key CryptoKey. CryptoKeys are opaque datastructures and representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store, key blob), the CryptoKey must be + * initialized differently. The ECDH API can handle all types of CryptoKey. + * However, not all device-specific implementions support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize a blank CryptoKey for the public key. The CryptoKey will keep track + * of where the keying material for the public key should be copied and how + * long it is. It should have twice the length of the private key. + * - Initialize the ECDH_OperationGeneratePublicKey struct and then populate it. + * - Call ECDH_generatePublicKey(). The generated keying material will be copied + * according the the CryptoKey passed in as the public key parameter. The CryptoKey + * will no longer be considered 'blank' after the operation. + * + * ## Calculating a shared secret # + * After trading public keys with the other party, the application should do the following + * to calculate the shared secret: + * - Initialize a CryptoKey as public key with the keying material received from the other + * party. + * - Initialize a blank CryptoKey with the same size as the previously initialized + * public key. + * - Initialize the ECDH_OperationComputeSharedSecret struct and then populate it. + * - Call ECDH_computeSharedSecret(). The shared secret will be copied to a location + * according to the shared secret CryptoKey passed to the function call. The driver + * will validate the supplied public key and reject invalid ones. + * + * ## Creating one or more symmetric keys from the shared secret # + * After calculating the shared secret between the application and the other party, + * the entropy in the shared secret must be evened out and stretched as needed. There are + * uncountable methods and algorithms to stretch an original seed entropy (the share secret) + * to generate symmetric keys. + * - Run the X coordinate of the resulting entropy through a key derivation function (KDF) + * + * ## After a key exchange # + * After the ECDH key exchange completes, the application should either start another operation + * or close the driver by calling ECDH_close() + * + * ## General usage # + * The API expects elliptic curves as defined in ti/drivers/cryptoutils/ecc/ECCParams.h. + * Several commonly used curves are provided. Check the device-specific ECDH documentation + * for curve type (short Weierstrass, Montgomery, Edwards) support for your device. + * ECDH support for a curve type on a device does not imply curve-type support for + * other ECC schemes. + * + * Public keys and shared secrets are points on an elliptic curve. These points can + * be expressed in several ways. The most common one is in affine coordinates as an + * X,Y pair. + * This API uses points expressed in affine coordinates. + * The point is stored as a concatenated array of X followed by Y in a location + * described by its CryptoKey. Some implementations do not require or yield + * the Y coordinate for ECDH on certain curves. It is recommended that the full + * keying material buffer of twice the curve param length is used to facilitate + * code-reuse. Implementations that do not use the Y coordinate will zero-out + * the Y-coordinate whenever they write a point to the CryptoKey. + * + * This API accepts and returns the keying material of public keys according + * to the following table: + * + * | Curve Type | Keying Material Array | Array Length | + * |--------------------|-----------------------|---------------------------| + * | Short Weierstrass | [X, Y] | 2 * Curve Param Length | + * | Montgomery | [X, Y] | 2 * Curve Param Length | + * | Edwards | [X, Y] | 2 * Curve Param Length | + * + * @anchor ti_drivers_ECDH_Synopsis + * ## Synopsis + * @anchor ti_drivers_ECDH_Synopsis_Code + * @code + * // Import ECDH Driver definitions + * #include + * + * ECDH_init(); + * + * // Since we are using default ECDH_Params, we just pass in NULL for that parameter. + * ecdhHandle = ECDH_open(0, NULL); + * + * // Initialize myPrivateKey and myPublicKey + * CryptoKeyPlaintext_initKey(&myPrivateKey, myPrivateKeyingMaterial, sizeof(myPrivateKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&myPublicKey, myPublicKeyingMaterial, sizeof(myPublicKeyingMaterial)); + * + * ECDH_OperationGeneratePublicKey_init(&operationGeneratePublicKey); + * operationGeneratePublicKey.curve = &ECCParams_NISTP256; + * operationGeneratePublicKey.myPrivateKey = &myPrivateKey; + * operationGeneratePublicKey.myPublicKey = &myPublicKey; + * + * // Generate the keying material for myPublicKey and store it in myPublicKeyingMaterial + * operationResult = ECDH_generatePublicKey(ecdhHandle, &operationGeneratePublicKey); + * + * // Now send the content of myPublicKeyingMaterial to theother party, + * // receive their public key, and copy their public keying material to theirPublicKeyingMaterial + * + * // Initialise their public CryptoKey and the shared secret CryptoKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, theirPublicKeyingMaterial, sizeof(theirPublicKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&sharedSecret, sharedSecretKeyingMaterial, sizeof(sharedSecretKeyingMaterial)); + * + * // The ECC_NISTP256 struct is provided in ti/drivers/types/EccParams.h and the corresponding device-specific implementation + * ECDH_OperationComputeSharedSecret_init(&operationComputeSharedSecret); + * operationComputeSharedSecret.curve = &ECCParams_NISTP256; + * operationComputeSharedSecret.myPrivateKey = &myPrivateKey; + * operationComputeSharedSecret.theirPublicKey = &theirPublicKey; + * operationComputeSharedSecret.sharedSecret = &sharedSecret; + * + * // Compute the shared secret and copy it to sharedSecretKeyingMaterial + * operationResult = ECDH_computeSharedSecret(ecdhHandle, &operationComputeSharedSecret); + * + * // Close the driver + * ECDH_close(ecdhHandle); + * + * @endcode + * + * @anchor ti_drivers_ECDH_Examples + * # Examples # + * + * ## ECDH exchange with plaintext CryptoKeys # + * + * @code + * + * #include + * #include + * + * ... + * + * // Our private key is 0x0000000000000000000000000000000000000000000000000000000000000001 + * // In practice, this value should come from a TRNG, PRNG, PUF, or device-specific pre-seeded key + * uint8_t myPrivateKeyingMaterial[32] = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + * 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + * 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + * 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + * uint8_t myPublicKeyingMaterial[64] = {0}; + * uint8_t theirPublicKeyingMaterial[64] = {0}; + * uint8_t sharedSecretKeyingMaterial[64] = {0}; + * uint8_t symmetricKeyingMaterial[16] = {0}; + * + * CryptoKey myPrivateKey; + * CryptoKey myPublicKey; + * CryptoKey theirPublicKey; + * CryptoKey sharedSecret; + * CryptoKey symmetricKey; + * + * ECDH_Handle ecdhHandle; + * + * int_fast16_t operationResult; + * + * ECDH_OperationGeneratePublicKey operationGeneratePublicKey; + * + * // Since we are using default ECDH_Params, we just pass in NULL for that parameter. + * ecdhHandle = ECDH_open(0, NULL); + * + * if (!ecdhHandle) { + * // Handle error + * } + * + * // Initialize myPrivateKey and myPublicKey + * CryptoKeyPlaintext_initKey(&myPrivateKey, myPrivateKeyingMaterial, sizeof(myPrivateKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&myPublicKey, myPublicKeyingMaterial, sizeof(myPublicKeyingMaterial)); + * + * ECDH_OperationGeneratePublicKey_init(&operationGeneratePublicKey); + * operationGeneratePublicKey.curve = &ECCParams_NISTP256; + * operationGeneratePublicKey.myPrivateKey = &myPrivateKey; + * operationGeneratePublicKey.myPublicKey = &myPublicKey; + * + * // Generate the keying material for myPublicKey and store it in myPublicKeyingMaterial + * operationResult = ECDH_generatePublicKey(ecdhHandle, &operationGeneratePublicKey); + * + * if (operationResult != ECDH_STATUS_SUCCESS) { + * // Handle error + * } + * + * // Now send the content of myPublicKeyingMaterial to theother party, + * // receive their public key, and copy their public keying material to theirPublicKeyingMaterial + * + * // Initialise their public CryptoKey and the shared secret CryptoKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, theirPublicKeyingMaterial, sizeof(theirPublicKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&sharedSecret, sharedSecretKeyingMaterial, sizeof(sharedSecretKeyingMaterial)); + * + * // The ECC_NISTP256 struct is provided in ti/drivers/types/EccParams.h and the corresponding device-specific implementation + * ECDH_OperationComputeSharedSecret_init(&operationComputeSharedSecret); + * operationComputeSharedSecret.curve = &ECCParams_NISTP256; + * operationComputeSharedSecret.myPrivateKey = &myPrivateKey; + * operationComputeSharedSecret.theirPublicKey = &theirPublicKey; + * operationComputeSharedSecret.sharedSecret = &sharedSecret; + * + * // Compute the shared secret and copy it to sharedSecretKeyingMaterial + * operationResult = ECDH_computeSharedSecret(ecdhHandle, &operationComputeSharedSecret); + * + * if (operationResult != ECDH_STATUS_SUCCESS) { + * // Handle error + * } + * + * CryptoKeyPlaintext_initBlankKey(&symmetricKey, symmetricKeyingMaterial, sizeof(symmetricKeyingMaterial)); + * + * // Set up a KDF such as HKDF and open the requisite cryptographic primitive driver to implement it + * // HKDF and SHA2 were chosen as an example and may not be available directly + * + * // At this point, you and the other party have both created the content within symmetricKeyingMaterial without + * // someone else listening to your communication channel being able to do so + * + * @endcode + * + * + */ + + +#ifndef ti_drivers_ECDH__include +#define ti_drivers_ECDH__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include +#include + +/*! + * Common ECDH status code reservation offset. + * ECC driver implementations should offset status codes with + * ECDH_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ECCXYZ_STATUS_ERROR0 ECDH_STATUS_RESERVED - 0 + * #define ECCXYZ_STATUS_ERROR1 ECDH_STATUS_RESERVED - 1 + * #define ECCXYZ_STATUS_ERROR2 ECDH_STATUS_RESERVED - 2 + * @endcode + */ +#define ECDH_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return ECDH_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define ECDH_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return ECDH_STATUS_ERROR if the function was not executed + * successfully. + */ +#define ECDH_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * ECC driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define ECDH_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief The result of the operation is the point at infinity. + * + * The operation yielded the point at infinity on this curve. This point is + * not permitted for further use in ECC operations. + */ +#define ECDH_STATUS_POINT_AT_INFINITY (-3) + +/*! + * @brief The private key passed in is larger than the order of the curve. + * + * Private keys must be integers in the interval [1, n - 1], where n is the + * order of the curve. + */ +#define ECDH_STATUS_PRIVATE_KEY_LARGER_EQUAL_ORDER (-4) + +/*! + * @brief The private key passed in is zero. + * + * Private keys must be integers in the interval [1, n - 1], where n is the + * order of the curve. + */ +#define ECDH_STATUS_PRIVATE_KEY_ZERO (-5) + +/*! + * @brief The public key of the other party does not lie upon the curve. + * + * The public key received from the other party does not lie upon the agreed upon + * curve. + */ +#define ECDH_STATUS_PUBLIC_KEY_NOT_ON_CURVE (-6) + +/*! + * @brief A coordinate of the public key of the other party is too large. + * + * A coordinate of the public key received from the other party is larger than + * the prime of the curve. This implies that the point was not correctly + * generated on that curve. + */ +#define ECDH_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME (-7) + +/*! + * @brief The ongoing operation was canceled. + */ +#define ECDH_STATUS_CANCELED (-8) + +/*! + * @brief A handle that is returned from an ECDH_open() call. + */ +typedef struct ECDH_Config *ECDH_Handle; + +/*! + * @brief The way in which ECC function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all ECC operations exhibit the specified return behavor. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specfied return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * ECC functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |ECDH_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |ECDH_RETURN_BEHAVIOR_BLOCKING | X | | | + * |ECDH_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum { + ECDH_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * ECC operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + ECDH_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECC operation goes + * on in the background. ECC operation results are available + * after the function returns. + */ + ECDH_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECC + * operation goes on in the background. ECC operation results + * are available after the function returns. + */ +} ECDH_ReturnBehavior; + + +/*! + * @brief ECC Global configuration + * + * The ECDH_Config structure contains a set of pointers used to characterize + * the ECC driver implementation. + * + * This structure needs to be defined before calling ECDH_init() and it must + * not be changed thereafter. + * + * @sa ECDH_init() + */ +typedef struct ECDH_Config { + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} ECDH_Config; + +/*! + * @brief Struct containing the parameters required to generate a public key. + */ +typedef struct { + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters for myPrivateKey */ + const CryptoKey *myPrivateKey; /*!< A pointer to the private ECC key from which the new public + * key will be generated. (maybe your static key) + */ + CryptoKey *myPublicKey; /*!< A pointer to a public ECC key which has been initialized blank. + * Newly generated key will be placed in this location. + */ +} ECDH_OperationGeneratePublicKey; + +/*! + * @brief Struct containing the parameters required to compute the shared secret. + */ +typedef struct { + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters for myPrivateKey. + * If ECDH_generateKey() was used, this should be the same private key. + */ + const CryptoKey *myPrivateKey; /*!< A pointer to the private ECC key which will be used in to + * compute the shared secret. + */ + const CryptoKey *theirPublicKey; /*!< A pointer to the public key of the party with whom the + * shared secret will be generated. + */ + CryptoKey *sharedSecret; /*!< A pointer to a CryptoKey which has been initialized blank. + * The shared secret will be placed here. + */ +} ECDH_OperationComputeSharedSecret; + +/*! + * @brief Union containing pointers to all supported operation structs. + */ +typedef union { + ECDH_OperationGeneratePublicKey *generatePublicKey; /*!< A pointer to an ECDH_OperationGeneratePublicKey struct */ + ECDH_OperationComputeSharedSecret *computeSharedSecret; /*!< A pointer to an ECDH_OperationGeneratePublicKey struct */ +} ECDH_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum { + ECDH_OPERATION_TYPE_GENERATE_PUBLIC_KEY = 1, + ECDH_OPERATION_TYPE_COMPUTE_SHARED_SECRET = 2, +} ECDH_OperationType; + +/*! + * @brief The definition of a callback function used by the ECDH driver + * when used in ::ECDH_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the ECDH operation. + * + * @param returnStatus The result of the ECDH operation. May contain an error code + * if the result is the point at infinity for example. + * + * @param operation A union of pointers to operation structs. Only one type + * of pointer is valid per call to the callback function. Which type + * is currently valid is determined by /c operationType. The union + * allows easier access to the struct's fields without the need to + * typecase the result. + * + * @param operationType This parameter determined which operation the + * callback refers to and which type to access through /c operation. + */ +typedef void (*ECDH_CallbackFxn) (ECDH_Handle handle, + int_fast16_t returnStatus, + ECDH_Operation operation, + ECDH_OperationType operationType); + +/*! + * @brief ECC Parameters + * + * ECC Parameters are used to with the ECDH_open() call. Default values for + * these parameters are set using ECDH_Params_init(). + * + * @sa ECDH_Params_init() + */ +typedef struct { + ECDH_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + ECDH_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout of the operation */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} ECDH_Params; + +/*! + * @brief Default ECDH_Params structure + * + * @sa ECDH_Params_init() + */ +extern const ECDH_Params ECDH_defaultParams; + +/*! + * @brief This function initializes the ECC module. + * + * @pre The ECDH_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other ECC driver APIs. This function call does not modify any + * peripheral registers. + */ +void ECDH_init(void); + +/*! + * @brief Function to initialize the ECDH_Params struct to its defaults + * + * @param params An pointer to ECDH_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = ECDH_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void ECDH_Params_init(ECDH_Params *params); + +/*! + * @brief This function opens a given ECC peripheral. + * + * @pre ECC controller has been initialized using ECDH_init() + * + * @param index Logical peripheral number for the ECC indexed into + * the ECDH_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An ECDH_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa ECDH_init() + * @sa ECDH_close() + */ +ECDH_Handle ECDH_open(uint_least8_t index, ECDH_Params *params); + +/*! + * @brief Function to close an ECC peripheral specified by the ECC handle + * + * @pre ECDH_open() has to be called first. + * + * @param handle An ECC handle returned from ECDH_open() + * + * @sa ECDH_open() + */ +void ECDH_close(ECDH_Handle handle); + +/*! + * @brief Function to initialize an ECDH_OperationGeneratePublicKey struct to its defaults + * + * @param operation A pointer to ECDH_OperationGeneratePublicKey structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECDH_OperationGeneratePublicKey_init(ECDH_OperationGeneratePublicKey *operation); + +/*! + * @brief Function to initialize an ECDH_OperationComputeSharedSecret struct to its defaults + * + * @param operation A pointer to ECDH_OperationComputeSharedSecret structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECDH_OperationComputeSharedSecret_init(ECDH_OperationComputeSharedSecret *operation); + +/*! + * @brief Generates a public key for use in key agreement. + * + * ECDH_generateKey() can be used for generating ephemeral keys. + * + * @param handle A ECC handle returned from ECDH_open() + * + * @param operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre Call ECDH_OperationGeneratePublicKey_init() on \c operation. + * + * @post ECDH_computeSharedSecret() + * + * @retval #ECDH_STATUS_SUCCESS The operation succeeded. + * @retval #ECDH_STATUS_ERROR The operation failed. + * @retval #ECDH_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECDH_STATUS_CANCELED The operation was canceled. + * @retval #ECDH_STATUS_POINT_AT_INFINITY The computed public key is the point at infinity. + * @retval #ECDH_STATUS_PRIVATE_KEY_ZERO The provided private key is zero. + * + */ +int_fast16_t ECDH_generatePublicKey(ECDH_Handle handle, ECDH_OperationGeneratePublicKey *operation); + +/*! + * @brief Computes a shared secret + * + * This secret can be used to generate shared keys for encryption and authentication. + * + * @param handle A ECC handle returned from ECDH_open() + * + * @param operation A pointer to a struct containing the requisite + * + * @pre Call ECDH_OperationComputeSharedSecret_init() on \c operation. + * Generate a shared secret off-chip or using ECDH_generatePublicKey() + * + * @retval #ECDH_STATUS_SUCCESS The operation succeeded. + * @retval #ECDH_STATUS_ERROR The operation failed. + * @retval #ECDH_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECDH_STATUS_CANCELED The operation was canceled. + * @retval #ECDH_STATUS_PUBLIC_KEY_NOT_ON_CURVE The foreign public key is not a point on the specified curve. + * @retval #ECDH_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME One of the public key coordinates is larger the the curve's prime. + */ +int_fast16_t ECDH_computeSharedSecret(ECDH_Handle handle, ECDH_OperationComputeSharedSecret *operation); + +/*! + * @brief Cancels an ongoing ECDH operation. + * + * Asynchronously cancels an ECDH operation. Only available when using + * ECDH_RETURN_BEHAVIOR_CALLBACK or ECDH_RETURN_BEHAVIOR_BLOCKING. + * The operation will terminate as though an error occured. The + * return status code of the operation will be ECDH_STATUS_CANCELED. + * + * @param handle Handle of the operation to cancel + * + * @retval #ECDH_STATUS_SUCCESS The operation was canceled. + * @retval #ECDH_STATUS_ERROR The operation was not canceled. There may be no operation to cancel. + */ +int_fast16_t ECDH_cancelOperation(ECDH_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ECDH__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDSA.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDSA.c new file mode 100644 index 0000000..080bfc0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDSA.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ECDSA.c ======== + * + * This file contains default values for the ECDSA_Params struct + * + */ + +#include +#include + +#include +#include + +const ECDSA_Params ECDSA_defaultParams = { + .returnBehavior = ECDSA_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== ECDSA_Params_init ======== + */ +void ECDSA_Params_init(ECDSA_Params *params){ + *params = ECDSA_defaultParams; +} + +/* + * ======== ECDSA_OperationSign_init ======== + */ +void ECDSA_OperationSign_init(ECDSA_OperationSign *operation){ + memset(operation, 0x00, sizeof(ECDSA_OperationSign)); +} + +/* + * ======== ECDSA_OperationVerify_init ======== + */ +void ECDSA_OperationVerify_init(ECDSA_OperationVerify *operation){ + memset(operation, 0x00, sizeof(ECDSA_OperationVerify)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDSA.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDSA.h new file mode 100644 index 0000000..5776b1b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDSA.h @@ -0,0 +1,757 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ECDSA.h + * + * @brief TI Driver for Elliptic Curve Digital Signature Algorithm. + * + * + * @anchor ti_drivers_ECDSA_Overview + * # Overview # + * + * The Elliptic Curve Digital Signature Algorithm (ECDSA) is a message + * authentication scheme between two parties based on operation on elliptic + * curves over finite fields. + * + * Signing a message with ECDSA proves to the recipient that the sender of + * the message is in possession of the private key corresponding to the + * transmitted public key used during verification. + * For most practical systems, this ensures message authentication and + * integrity. + * + * # Steps involved # + * - The sender hashes the message they wish to authenticate and + * truncates it to the length of the curve parameters of the + * elliptic curve used by both parties. + * - The sender generates a per-message secret number (PMSN) where + * 0 < PMSN < N. This number must (!) be unique for each message and be + * kept secret. If a PMSN is reused to authenticate more than one message, + * the secret key of the sender can be derived from these two messages + * and signatures! + * - The sender generates r and s where 0 < r, s < N. These two integers + * constitute the actual signature of the message. + * - The sender transmits the message, r, s, and the public key to the + * recipient. + * - The recipient calculates the hash of the message using an agreed + * upon hash function and truncates it to the length of the curve + * parameters of the elliptic curve used by both parties + * - The recipient uses the hash, s, and the sender's public key to + * recalculate r. + * - The recipient accepts the signature if the received and calculated r + * match. Otherwise, they reject the signature. + * + * @anchor ti_drivers_ECDSA_Usage + * # Usage # + * + * ## Before starting an ECDSA operation # + * + * Before starting an ECDSA operation, the application must do the following: + * - Call ECDSA_init() to initialize the driver + * - Call ECDSA_Params_init() to initialize the ECDSA_Params to default values. + * - Modify the ECDSA_Params as desired + * - Call ECDSA_open() to open an instance of the driver + * + * ## Signing a message # + * To sign a message using an agreed upon hash function and elliptic curve, the + * application must do the following: + * - Initialize an ECDSA_OperationSign struct by calling ECDSA_OperationSign_init(). + * - Generate the keying material for the private key. This keying material must + * be an integer in the interval [1, n - 1], where n is the order of the curve. + * It should be stored in an array with the least significant byte of the integer + * hex representation stored in the lowest address of the array (little-endian). + * The array should be the same length as the curve parameters of the curve used. + * The driver can be configured to validate public and private keys against the + * provided curve. + * - Initialize the private key CryptoKey. CryptoKeys are opaque datastructures and representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store, key blob), the CryptoKey must be + * initialized differently. The ECDSA API can handle all types of CryptoKey. + * However, not all device-specific implementions support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize the pmsn CryptoKey. The PMSN itself should be a 0-padded integer of + * the same length as the curve parameters of the agreed upon curve and + * where 0 < PMSN < N. The driver will enforce this restriction and reject invalid + * PMSNs. + * - Hash the message using a previously agreed upon hash function and truncate + * the hash to the length of the curve parameters of the agreed upon curve. + * - Call ECDSA_sign(). The r and s vectors will be written to the buffers + * provided in the function call. Ensure the return value is + * ECDSA_STATUS_SUCCESS. + * + * ## Verifying a message # + * After receiving the message, public key, r, and s, the application should + * do the following to verify the signature: + * - Initialize an ECDSA_OperationVerify struct by calling ECDSA_OperationVerify_init(). + * - Hash the message using a previously agreed upon hash function and truncate + * the hash to the length of the curve parameters of the agreed upon curve. + * - Initialize a CryptoKey as public key with the keying material received from the other + * party. + * - Call ECDSA_verify(). Ensure the return value is ECDSA_STATUS_SUCCESS. The + * driver will validate the received public key against the provided curve. + * + * ## General usage # + * The API expects elliptic curves as defined in ti/drivers/cryptoutils/ecc/ECCParams.h. + * Several commonly used curves are provided. Check the device-specific ECDSA documentation + * for curve type (short Weierstrass, Montgomery, Edwards) support for your device. + * ECDSA support for a curve type on a device does not imply curve-type support for + * other ECC schemes. + * + * Public keys and shared secrets are points on an elliptic curve. These points can + * be expressed in several ways. The most common one is in affine coordinates as an + * X,Y pair. + * This API uses points expressed in affine coordinates. + * The point is stored as a concatenated array of X followed by Y in a location + * described by its CryptoKey. + * + * This API accepts and returns the keying material of public keys according + * to the following table: + * + * | Curve Type | Keying Material Array | Array Length | + * |--------------------|-----------------------|---------------------------| + * | Short Weierstrass | [X, Y] | 2 * Curve Param Length | + * | Montgomery | [X, Y] | 2 * Curve Param Length | + * | Edwards | [X, Y] | 2 * Curve Param Length | + * + * @anchor ti_drivers_ECDSA_Synopsis + * ## Synopsis + * @anchor ti_drivers_ECDSA_Synopsis_Code + * @code + * // Import ECDSA Driver definitions + * #include + * + * // Since we are using default ECDSA_Params, we just pass in NULL for that parameter. + * ecdsaHandle = ECDSA_open(0, NULL); + * + * if (!ecdsaHandle) { + * // Handle error + * } + * + * // Initialize myPrivateKey + * CryptoKeyPlaintext_initKey(&myPrivateKey, myPrivateKeyingMaterial, sizeof(myPrivateKeyingMaterial)); + * CryptoKeyPlaintext_initKey(&pmsnKey, pmsn, sizeof(pmsn)); + * + * // Initialize the operation + * ECDSA_OperationSign_init(&operationSign); + * operationSign.curve = &ECCParams_NISTP256; + * operationSign.myPrivateKey = &myPrivateKey; + * operationSign.pmsn = &pmsnKey; + * operationSign.hash = messageHash; + * operationSign.r = r; + * operationSign.s = s; + * + * // Generate the signature + * operationResult = ECDSA_sign(ecdsaHandle, &operationSign); + * + * // Initialize theirPublicKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, theirPublicKeyingMaterial, sizeof(theirPublicKeyingMaterial)); + * + * ECDSA_OperationVerify_init(&operationVerify); + * operationVerify.curve = &ECCParams_NISTP256; + * operationVerify.theirPublicKey = &theirPublicKey; + * operationVerify.hash = messageHash; + * operationVerify.r = r; + * operationVerify.s = s; + * + * // Generate the keying material for myPublicKey and store it in myPublicKeyingMaterial + * operationResult = ECDSA_verify(ecdsaHandle, &operationVerify); + * + * // Close the driver + * ECDSA_close(ecdsaHandle); + * + * @anchor ti_drivers_ECDSA_Examples + * + * # Examples # + * + * ## ECDSA sign with plaintext CryotoKeys # + * + * @code + * + * #include + * #include + * + * ... + * + * // This vector is taken from the NIST ST toolkit examples from ECDSA_Prime.pdf + * uint8_t myPrivateKeyingMaterial[32] = {0x96, 0xBF, 0x85, 0x49, 0xC3, 0x79, 0xE4, 0x04, + * 0xED, 0xA1, 0x08, 0xA5, 0x51, 0xF8, 0x36, 0x23, + * 0x12, 0xD8, 0xD1, 0xB2, 0xA5, 0xFA, 0x57, 0x06, + * 0xE2, 0xCC, 0x22, 0x5C, 0xF6, 0xF9, 0x77, 0xC4}; + * uint8_t messageHashSHA256[32] = {0xC4, 0xA8, 0xC8, 0x99, 0x28, 0xCF, 0x80, 0xB6, + * 0xE4, 0x42, 0xD5, 0xBD, 0x28, 0x4D, 0xE3, 0xFD, + * 0x3A, 0x13, 0xD8, 0x65, 0x0C, 0x41, 0x1C, 0x21, + * 0x48, 0x95, 0x79, 0x2A, 0xA1, 0x41, 0x1A, 0xA4}; + * uint8_t pmsn[32] = {0xAE, 0x50, 0xEE, 0xFA, 0x27, 0xB4, 0xDB, 0x14, + * 0x9F, 0xE1, 0xFB, 0x04, 0xF2, 0x4B, 0x50, 0x58, + * 0x91, 0xE3, 0xAC, 0x4D, 0x2A, 0x5D, 0x43, 0xAA, + * 0xCA, 0xC8, 0x7F, 0x79, 0x52, 0x7E, 0x1A, 0x7A}; + * uint8_t r[32] = {0}; + * uint8_t s[32] = {0}; + * + * + * CryptoKey myPrivateKey; + * CryptoKey pmsnKey; + * + * ECDSA_Handle ecdsaHandle; + * + * int_fast16_t operationResult; + * + * // Since we are using default ECDSA_Params, we just pass in NULL for that parameter. + * ecdsaHandle = ECDSA_open(0, NULL); + * + * if (!ecdsaHandle) { + * // Handle error + * } + * + * // Initialize myPrivateKey + * CryptoKeyPlaintext_initKey(&myPrivateKey, myPrivateKeyingMaterial, sizeof(myPrivateKeyingMaterial)); + * CryptoKeyPlaintext_initKey(&pmsnKey, pmsn, sizeof(pmsn)); + * + * // Initialize the operation + * ECDSA_OperationSign_init(&operationSign); + * operationSign.curve = &ECCParams_NISTP256; + * operationSign.myPrivateKey = &myPrivateKey; + * operationSign.pmsn = &pmsnKey; + * operationSign.hash = messageHash; + * operationSign.r = r; + * operationSign.s = s; + * + * // Generate the signature + * operationResult = ECDSA_sign(ecdsaHandle, &operationSign); + * + * if (operationResult != ECDSA_STATUS_SUCCESS) { + * // Handle error + * } + * + * // Send out signature + * // r should be 0x4F, 0x10, 0x46, 0xCA, 0x9A, 0xB6, 0x25, 0x73, + * // 0xF5, 0x3E, 0x0B, 0x1F, 0x6F, 0x31, 0x4C, 0xE4, + * // 0x81, 0x0F, 0x50, 0xB1, 0xF3, 0xD1, 0x65, 0xFF, + * // 0x65, 0x41, 0x7F, 0xD0, 0x76, 0xF5, 0x42, 0x2B + * // + * // s should be 0xF1, 0xFA, 0x63, 0x6B, 0xDB, 0x9B, 0x32, 0x4B, + * // 0x2C, 0x26, 0x9D, 0xE6, 0x6F, 0x88, 0xC1, 0x98, + * // 0x81, 0x2A, 0x50, 0x89, 0x3A, 0x99, 0x3A, 0x3E, + * // 0xCD, 0x92, 0x63, 0x2D, 0x12, 0xC2, 0x42, 0xDC + * + * @endcode + * + * + * ## ECDSA verify with plaintext CryotoKeys # + * + * @code + * + * #include + * #include + * + * ... + * + * // This vector is taken from the NIST ST toolkit examples from ECDSA_Prime.pdf + * uint8_t theirPublicKeyingMaterial[64] = {0x19, 0x7A, 0xBC, 0x89, 0x08, 0xCD, 0x01, 0x82, + * 0xA3, 0xA2, 0x9E, 0x1E, 0xAD, 0xA0, 0xB3, 0x62, + * 0x1C, 0xBA, 0x98, 0x47, 0x73, 0x8C, 0xDC, 0xF1, + * 0xD3, 0xBA, 0x94, 0xFE, 0xFD, 0x8A, 0xE0, 0xB7, + * 0x09, 0x5E, 0xCC, 0x06, 0xC6, 0xBB, 0x63, 0xB5, + * 0x61, 0x9E, 0x52, 0x43, 0xAE, 0xC7, 0xAD, 0x63, + * 0x90, 0x72, 0x28, 0x19, 0xE4, 0x26, 0xB2, 0x4B, + * 0x7A, 0xBF, 0x9D, 0x95, 0x47, 0xF7, 0x03, 0x36}; + * uint8_t messageHashSHA256[32] = {0xC4, 0xA8, 0xC8, 0x99, 0x28, 0xCF, 0x80, 0xB6, + * 0xE4, 0x42, 0xD5, 0xBD, 0x28, 0x4D, 0xE3, 0xFD, + * 0x3A, 0x13, 0xD8, 0x65, 0x0C, 0x41, 0x1C, 0x21, + * 0x48, 0x95, 0x79, 0x2A, 0xA1, 0x41, 0x1A, 0xA4}; + * uint8_t r[32] = {0x4F, 0x10, 0x46, 0xCA, 0x9A, 0xB6, 0x25, 0x73, + * 0xF5, 0x3E, 0x0B, 0x1F, 0x6F, 0x31, 0x4C, 0xE4, + * 0x81, 0x0F, 0x50, 0xB1, 0xF3, 0xD1, 0x65, 0xFF, + * 0x65, 0x41, 0x7F, 0xD0, 0x76, 0xF5, 0x42, 0x2B}; + * uint8_t s[32] = {0xF1, 0xFA, 0x63, 0x6B, 0xDB, 0x9B, 0x32, 0x4B, + * 0x2C, 0x26, 0x9D, 0xE6, 0x6F, 0x88, 0xC1, 0x98, + * 0x81, 0x2A, 0x50, 0x89, 0x3A, 0x99, 0x3A, 0x3E, + * 0xCD, 0x92, 0x63, 0x2D, 0x12, 0xC2, 0x42, 0xDC}; + * + * + * CryptoKey theirPublicKey; + * + * ECDSA_Handle ecdsaHandle; + * + * int_fast16_t operationResult; + * + * ECDSA_OperationVerify operationVerify; + * + * // Since we are using default ECDSA_Params, we just pass in NULL for that parameter. + * ecdsaHandle = ECDSA_open(0, NULL); + * + * if (!ecdsaHandle) { + * // Handle error + * } + * + * // Initialize theirPublicKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, theirPublicKeyingMaterial, sizeof(theirPublicKeyingMaterial)); + * + * ECDSA_OperationVerify_init(&operationVerify); + * operationVerify.curve = &ECCParams_NISTP256; + * operationVerify.theirPublicKey = &theirPublicKey; + * operationVerify.hash = messageHash; + * operationVerify.r = r; + * operationVerify.s = s; + * + * // Generate the keying material for myPublicKey and store it in myPublicKeyingMaterial + * operationResult = ECDSA_verify(ecdsaHandle, &operationVerify); + * + * if (operationResult != ECDSA_STATUS_SUCCESS) { + * // Handle error + * } + * + * @endcode + * + * + */ + + +#ifndef ti_drivers_ECDSA__include +#define ti_drivers_ECDSA__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include +#include + +/*! + * Common ECDSA status code reservation offset. + * ECDSA driver implementations should offset status codes with + * ECDSA_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ECDSAXYZ_STATUS_ERROR0 ECDSA_STATUS_RESERVED - 0 + * #define ECDSAXYZ_STATUS_ERROR1 ECDSA_STATUS_RESERVED - 1 + * #define ECDSAXYZ_STATUS_ERROR2 ECDSA_STATUS_RESERVED - 2 + * @endcode + */ +#define ECDSA_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return ECDSA_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define ECDSA_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return ECDSA_STATUS_ERROR if the function was not executed + * successfully. + */ +#define ECDSA_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * ECDSA driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define ECDSA_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief The PMSN passed into the the call is invalid. + * + * PMSNs must be integers in the interval [1, n - 1], where n is the + * order of the curve. + */ +#define ECDSA_STATUS_INVALID_PMSN (-3) + +/*! + * @brief The r value passed in is larger than the order of the curve. + * + * Signature components (r and s) must be integers in the interval [1, n - 1], where n is the + * order of the curve. + */ +#define ECDSA_STATUS_R_LARGER_THAN_ORDER (-4) + +/*! + * @brief The s value passed in is larger than the order of the curve. + * + * Signature components (r and s) must be integers in the interval [1, n - 1], where n is the + * order of the curve. + */ +#define ECDSA_STATUS_S_LARGER_THAN_ORDER (-5) + +/*! + * @brief The public key of the other party does not lie upon the curve. + * + * The public key received from the other party does not lie upon the agreed upon + * curve. + */ +#define ECDSA_STATUS_PUBLIC_KEY_NOT_ON_CURVE (-6) + +/*! + * @brief A coordinate of the public key of the other party is too large. + * + * A coordinate of the public key received from the other party is larger than + * the prime of the curve. This implies that the point was not correctly + * generated on that curve. + */ +#define ECDSA_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME (-7) + +/*! + * @brief The public key to verify against is the point at infinity. + * + * The point at infinity is not a valid input. + */ +#define ECDSA_STATUS_POINT_AT_INFINITY (-8) + +/*! + * @brief The ongoing operation was canceled. + */ +#define ECDSA_STATUS_CANCELED (-9) + +/*! + * @brief A handle that is returned from an ECDSA_open() call. + */ +typedef struct ECDSA_Config *ECDSA_Handle; + +/*! + * @brief The way in which ECDSA function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all ECDSA operations exhibit the specified return behavor. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specfied return behavior is + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * ECDSA functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |ECDSA_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |ECDSA_RETURN_BEHAVIOR_BLOCKING | X | | | + * |ECDSA_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum { + ECDSA_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * ECDSA operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + ECDSA_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECDSA operation goes + * on in the background. ECDSA operation results are available + * after the function returns. + */ + ECDSA_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECDSA + * operation goes on in the background. ECDSA operation results + * are available after the function returns. + */ +} ECDSA_ReturnBehavior; + +/*! + * @brief ECDSA Global configuration + * + * The ECDSA_Config structure contains a set of pointers used to characterize + * the ECDSA driver implementation. + * + * This structure needs to be defined before calling ECDSA_init() and it must + * not be changed thereafter. + * + * @sa ECDSA_init() + */ +typedef struct ECDSA_Config { + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} ECDSA_Config; + +/*! + * @brief Struct containing the parameters required for signing a message. + */ +typedef struct { + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters */ + const CryptoKey *myPrivateKey; /*!< A pointer to the private ECC key that will + * sign the hash of the message + */ + const CryptoKey *pmsn; /*!< A pointer to a per message secret number (PMSN). + * The number must be provided by the + * application and be (0 < PMSN < curve order). + * Must be of the same length as + * other params of the curve used. + */ + const uint8_t *hash; /*!< A pointer to the hash of the message. + * Must be the same length as the other curve parameters. + */ + uint8_t *r; /*!< A pointer to the buffer the r component of + * the signature will be written to. + * Must be of the same length as other + * params of the curve used. + */ + uint8_t *s; /*!< A pointer to the buffer the s component of + * the signature will be written to. + * Must be of the same length as other + * params of the curve used. + */ +} ECDSA_OperationSign; + +/*! + * @brief Struct containing the parameters required for verifying a message. + */ +typedef struct { + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters */ + const CryptoKey *theirPublicKey; /*!< A pointer to the public key of the party + * that signed the hash of the message + */ + const uint8_t *hash; /*!< A pointer to the hash of the message. + * Must be the same length as the other curve parameters. + */ + const uint8_t *r; /*!< A pointer to the r component of the received + * signature. Must be of the same length + * as other params of the curve used. + */ + const uint8_t *s; /*!< A pointer to the s component of the received + * signature. Must be of the same length + * as other params of the curve used. + */ +} ECDSA_OperationVerify; + +/*! + * @brief Union containing pointers to all supported operation structs. + */ +typedef union { + ECDSA_OperationSign *sign; /*!< A pointer to an ECDSA_OperationSign struct */ + ECDSA_OperationVerify *verify; /*!< A pointer to an ECDSA_OperationVerify struct */ +} ECDSA_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum { + ECDSA_OPERATION_TYPE_SIGN = 1, + ECDSA_OPERATION_TYPE_VERIFY = 2, +} ECDSA_OperationType; + +/*! + * @brief The definition of a callback function used by the ECDSA driver + * when used in ::ECDSA_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the ECDSA operation. + * + * @param returnStatus The result of the ECDSA operation. May contain an error code + * if the result is the point at infinity for example. + * + * @param operation A union of pointers to operation structs. Only one type + * of pointer is valid per call to the callback function. Which type + * is currently valid is determined by /c operationType. The union + * allows easier access to the struct's fields without the need to + * typecase the result. + * + * @param operationType This parameter determined which operation the + * callback refers to and which type to access through /c operation. + */ +typedef void (*ECDSA_CallbackFxn) (ECDSA_Handle handle, + int_fast16_t returnStatus, + ECDSA_Operation operation, + ECDSA_OperationType operationType); + +/*! + * @brief ECDSA Parameters + * + * ECDSA Parameters are used to with the ECDSA_open() call. Default values for + * these parameters are set using ECDSA_Params_init(). + * + * @sa ECDSA_Params_init() + */ +typedef struct { + ECDSA_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + ECDSA_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout in system ticks before the operation fails + * and returns + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} ECDSA_Params; + +/*! + * @brief This function initializes the ECDSA module. + * + * @pre The ECDSA_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other ECDSA driver APIs. This function call does not modify any + * peripheral registers. + */ +void ECDSA_init(void); + +/*! + * @brief Function to close an ECDSA peripheral specified by the ECDSA handle + * + * @pre ECDSA_open() has to be called first. + * + * @param handle An ECDSA handle returned from ECDSA_open() + * + * @sa ECDSA_open() + */ +void ECDSA_close(ECDSA_Handle handle); + +/*! + * @brief This function opens a given ECDSA peripheral. + * + * @pre ECDSA controller has been initialized using ECDSA_init() + * + * @param index Logical peripheral number for the ECDSA indexed into + * the ECDSA_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An ECDSA_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa ECDSA_init() + * @sa ECDSA_close() + */ +ECDSA_Handle ECDSA_open(uint_least8_t index, ECDSA_Params *params); + +/*! + * @brief Function to initialize the ECDSA_Params struct to its defaults + * + * @param params An pointer to ECDSA_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = ECDSA_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void ECDSA_Params_init(ECDSA_Params *params); + +/*! + * @brief Function to initialize an ECDSA_OperationSign struct to its defaults + * + * @param operation A pointer to ECDSA_OperationSign structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECDSA_OperationSign_init(ECDSA_OperationSign *operation); + +/*! + * @brief Function to initialize an ECDSA_OperationSign struct to its defaults + * + * @param operation An pointer to ECDSA_OperationSign structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECDSA_OperationVerify_init(ECDSA_OperationVerify *operation); + +/*! + * @brief Signs a hashed message. + * + * ECDSA_sign() generates a signature (\c r, \c s) of a \c hash of a message. + * + * @pre ECDSA_OperationSign_init() must be called on \c operation first. + * The driver must have been opened by calling ECDSA_open() first. + * + * @param [in] handle An ECDSA handle returned from ECDSA_open() + * + * @param [in] operation A struct containing the pointers to the + * buffers necessary to perform the operation + * @sa ECDSA_verify() + * + * @retval #ECDSA_STATUS_SUCCESS The operation succeeded. + * @retval #ECDSA_STATUS_ERROR The operation failed. + * @retval #ECDSA_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECDSA_STATUS_CANCELED The operation was canceled. + * @retval #ECDSA_STATUS_INVALID_PMSN The PMSN passed into the the call is invalid. + */ +int_fast16_t ECDSA_sign(ECDSA_Handle handle, ECDSA_OperationSign *operation); + +/*! + * @brief Verifies a received signature matches a hash and public key + * + * @pre ECDSA_OperationVerify_init() must be called on \c operation first. + * The driver must have been opened by calling ECDSA_open() first. + * + * @param [in] handle An ECDSA handle returned from ECDSA_open() + * + * @param [in] operation A struct containing the pointers to the + * buffers necessary to perform the operation + * + * @sa ECDSA_sign() + * + * @retval #ECDSA_STATUS_SUCCESS The operation succeeded. + * @retval #ECDSA_STATUS_ERROR The operation failed. This is the return status if the signature did not match. + * @retval #ECDSA_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECDSA_STATUS_CANCELED The operation was canceled. + * @retval #ECDSA_STATUS_R_LARGER_THAN_ORDER The r value passed in is larger than the order of the curve. + * @retval #ECDSA_STATUS_S_LARGER_THAN_ORDER The s value passed in is larger than the order of the curve. + * @retval #ECDSA_STATUS_PUBLIC_KEY_NOT_ON_CURVE The public key of the other party does not lie upon the curve. + * @retval #ECDSA_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME One of the public key coordinates is larger the the curve's prime. + * @retval #ECDSA_STATUS_POINT_AT_INFINITY The public key to verify against is the point at infinity. + */ +int_fast16_t ECDSA_verify(ECDSA_Handle handle, ECDSA_OperationVerify *operation); + +/*! + * @brief Cancels an ongoing ECDSA operation. + * + * Asynchronously cancels an ECDSA operation. Only available when using + * ECDSA_RETURN_BEHAVIOR_CALLBACK or ECDSA_RETURN_BEHAVIOR_BLOCKING. + * The operation will terminate as though an error occured. The + * return status code of the operation will be ECDSA_STATUS_CANCELED. + * + * @param handle Handle of the operation to cancel + * + * @retval #ECDSA_STATUS_SUCCESS The operation was canceled. + * @retval #ECDSA_STATUS_ERROR The operation was not canceled. There may be no operation to cancel. + */ +int_fast16_t ECDSA_cancelOperation(ECDSA_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ECDSA__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECJPAKE.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECJPAKE.c new file mode 100644 index 0000000..a0880e7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECJPAKE.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ECJPAKE.c ======== + * + * This file contains default values for the ECJPAKE_Params struct + * + */ + +#include +#include + +#include +#include + +const ECJPAKE_Params ECJPAKE_defaultParams = { + .returnBehavior = ECJPAKE_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== ECJPAKE_Params_init ======== + */ +void ECJPAKE_Params_init(ECJPAKE_Params *params){ + *params = ECJPAKE_defaultParams; +} + +/* + * ======== ECJPAKE_OperationRoundOneGenerateKeys_init ======== + */ +void ECJPAKE_OperationRoundOneGenerateKeys_init(ECJPAKE_OperationRoundOneGenerateKeys *operation){ + memset(operation, 0x00, sizeof(ECJPAKE_OperationRoundOneGenerateKeys)); +} + +/* + * ======== ECJPAKE_OperationGenerateZKP_init ======== + */ +void ECJPAKE_OperationGenerateZKP_init(ECJPAKE_OperationGenerateZKP *operation){ + memset(operation, 0x00, sizeof(ECJPAKE_OperationGenerateZKP)); +} + +/* + * ======== ECJPAKE_OperationVerifyZKP_init ======== + */ +void ECJPAKE_OperationVerifyZKP_init(ECJPAKE_OperationVerifyZKP *operation){ + memset(operation, 0x00, sizeof(ECJPAKE_OperationVerifyZKP)); +} + +/* + * ======== ECJPAKE_OperationRoundTwoGenerateKeys_init ======== + */ +void ECJPAKE_OperationRoundTwoGenerateKeys_init(ECJPAKE_OperationRoundTwoGenerateKeys *operation){ + memset(operation, 0x00, sizeof(ECJPAKE_OperationRoundTwoGenerateKeys)); +} + +/* + * ======== ECJPAKE_OperationComputeSharedSecret_init ======== + */ +void ECJPAKE_OperationComputeSharedSecret_init(ECJPAKE_OperationComputeSharedSecret *operation){ + memset(operation, 0x00, sizeof(ECJPAKE_OperationComputeSharedSecret)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECJPAKE.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECJPAKE.h new file mode 100644 index 0000000..af69ddc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECJPAKE.h @@ -0,0 +1,1339 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ECJPAKE.h + * + * @brief TI Driver for Elliptic Curve Password Authenticated Key Exchange + * by Juggling. + * + * @anchor ti_drivers_ECJPAKE_Overview + * # Overview # + * Elliptic Curve Password Authenticated Key Exchange by Juggling (EC-JPAKE) + * is a key agreement scheme that establishes a secure channel over an insecure + * network. It only requires sharing a password offline and does not require + * public key infrastructure or trusted third parties such as certificate + * authorities. + * + * At the end of the EC-JPAKE scheme, both parties derive a shared secret + * from which a session key is derived. + * + * The scheme is symmetric. Both parties perform the exact same operations + * to end up with the shared secret. + * + * # Steps involved # + * Since the scheme is symmetric, the steps involved will be illustrated + * using Alice and Bob as relevant parties. + * + * -# Alice and Bob decide on some pre-shared secret, the password, and + * negotiate this through some offline means such as during commissioning. + * + * -# Alice generates private keys x1, x2, v1, and v2 uniformly at random from [1, n - 1], + * where n is the order of the curve. + * -# Alice generates public keys X1 = x1 * G, X2 = x2 * G, V1 = v1 * G, and V2 = v2 * G. + * -# Alice generates Zero-Knowledge Proofs (ZKPs) for (X1, x1) and (X2, x2). + * The required hash is computed by concatenating G, V, the public key + * the ZKP authenticates, and the UserID of the authenticator and hashing + * the new bitstring. The exact order and formatting of all parameters and + * any extra information such as length words must be agreed upon by both + * parties to yield the same result. + * -# Alice sends X1, X2, V1, V2, r1, r2, and her UserID to Bob. + * + * -# Bob generates private keys x3, x4, v3, and v4 uniformly at random from [1, n - 1], + * where n is the order of the curve. + * -# Bob generates public keys X3 = x3 * G, X4 = x4 * G, V3 = v3 * G, and V4 = v4 * G. + * -# Bob generates Zero-Knowledge Proofs (ZKPs) for (X3, x3) and (X4, x4). + * -# Bob sends X3, X4, V3, V4, r3, r4, and his UserID to Bob. + * + * -# Alice and Bob verify the other parties ZKPs and break off the scheme if they + * do not check out. + * + * -# Alice computes the new generator point G2 = (X1 + X3 + X4). + * -# Alice computes the combined private key x5 = x2 * s, where s is the pre-shared + * secret. + * -# Alice computes the combined public key X5 = x5 * G2. + * -# Alice computes a ZKP for (X5, x5) using G2 as the generator point of the ZKP. + * -# Alice sends X5, V5, r5, and her UserID to Bob. + * + * -# Bob computes the new generator point G3 = (X3 + X1 + X2). + * -# Bob computes the combined private key x6 = x4 * s, where s is the pre-shared + * secret. + * -# Bob computes the combined public key X6 = x6 * G3. + * -# Bob computes a ZKP for (X6, x6) using G3 as the generator point of the ZKP. + * -# Bob sends X6, V6, r6, and his UserID to Alice. + * + * -# Alice and Bob verify the other parties ZKPs and break off the scheme if they + * do not check out. This involves computing the other parties generator point. + * + * -# Alice computes shared secret K = (X6 - (X4 * x5)) * x2. + * + * -# Bob computes shared secret K = (X5 - (X2 * x6)) * x4. + * + * -# Alice and Bob each run K through a mutually agreed upon key derivation + * function to compute the symmetric session key. + * + * @anchor ti_drivers_ECJPAKE_Usage + * # Usage # + * + * ## Before starting an ECJPAKE operation # + * + * Before starting an ECJPAKE operation, the application must do the following: + * -# Call ECJPAKE_init() to initialize the driver + * -# Call ECJPAKE_Params_init() to initialize the ECJPAKE_Params to default values. + * -# Modify the ECJPAKE_Params as desired + * -# Call ECJPAKE_open() to open an instance of the driver + * + * ## Round one # + * -# Initialize the following private key CryptoKeys. + * Seed them with keying material uniformly drawn from [1, n - 1] + * - myPrivateKey1 + * - myPrivateKey2 + * - myPrivateV1 + * - myPrivateV2 + * -# Initialize the following blank public key CryptoKeys: + * - myPublicKey1 + * - myPublicKey2 + * - myPublicV1 + * - myPublicV2 + * - theirPublicKey1 + * - theirPublicKey2 + * - theirPublicV1 + * - theirPublicV2 + * -# Call ECJPAKE_roundOneGenerateKeys() to generate all round one keys as needed. + * -# Generate the hashes for the ZKPs using previously agreed upon formatting. + * Use the default generator point of the curve in the first round. + * -# Generate your two ZKPs by calling ECJPAKE_generateZKP() once per ZKP. + * -# Exchange public keys, UserIDs, and ZKP signatures. Write the received keying + * material into the relevant buffers or load them into key stores as specified + * by the CryptoKeys initialised earlier. + * -# Verify the other party's ZKPs after computing their ZKP hash by calling + * ECJPAKE_verifyZKP() once per ZKP. + * -# You can now let all V keys, myPrivateKey1, and all ZKP signatures go out of scope + * and re-use their memory. + * + * ## Round two # + * -# Initialize the following private key CryptoKeys. + * Seed myPrivateV with keying material uniformly drawn from [1, n - 1]. + * Initialise the preSharedSecret with the common keying material previously + * shared between you and the other party. + * - preSharedSecret + * - myCombinedPrivateKey + * -# Initialize the following blank public key CryptoKeys: + * - theirNewGenerator + * - myNewGenerator + * - myCombinedPublicKey + * - myPublicV + * -# Call ECJPAKE_roundTwoGenerateKeys() to generate the remaining round two keys. + * -# Generate the hash for your ZKP use myNewGenerator as your generator point. + * -# Exchange public keys, UserIDs, and ZKP signatures. Write the received keying + * material into the relevant buffers or load them into key stores as specified + * by the CryptoKeys initialised earlier. + * -# Verify the other party's ZKP after computing their ZKP hash b calling + * ECJPAKE_verifyZKP(). Use theirNewGenerator as the generator point for this + * ZKP. + * -# You can now let all keys and keying material but myCombinedPrivateKey, + * theirCombinedPublicKey, theirPublicKey2, and myPrivateKey2 go out of scope. + * + * ## Computing the shared secret # + * -# Initialize the following blank public key CryptoKey: + * - sharedSecret + * -# Call ECJPAKE_computeSharedSecret(). + * -# Run sharedSecret through a key derivation function to compute the shared + * symmetric session key. + * + * ## General usage # + * The API expects elliptic curves as defined in ti/drivers/cryptoutils/ecc/ECCParams.h. + * Several commonly used curves are provided. Check the device-specific ECJPAKE documentation + * for curve type (short Weierstrass, Montgomery, Edwards) support for your device. + * ECJPAKE support for a curve type on a device does not imply curve-type support for + * other ECC schemes. + * + * Public keys and shared secrets are points on an elliptic curve. These points can + * be expressed in several ways. The most common one is in affine coordinates as an + * X,Y pair. + * This API uses points expressed in affine coordinates. + * The point is stored as a concatenated array of X followed by Y in a location + * described by its CryptoKey. + * + * This API accepts and returns the keying material of public keys according + * to the following table: + * + * | Curve Type | Keying Material Array | Array Length | + * |--------------------|-----------------------|---------------------------| + * | Short Weierstrass | [X, Y] | 2 * Curve Param Length | + * | Montgomery | [X, Y] | 2 * Curve Param Length | + * | Edwards | [X, Y] | 2 * Curve Param Length | + * + * @anchor ti_drivers_ECJPAKE_Synopsis + * ## Synopsis + * + * @anchor ti_drivers_ECJPAKE_Synopsis_Code + * @code + * // Import ECJPAKE Driver definitions + * #include + * + * ECJPAKE_init(); + * + * // Since we are using default ECJPAKE_Params, we just pass in NULL for that parameter. + * ecjpakeHandle = ECJPAKE_open(0, NULL); + + * ECJPAKE_Handle handle = ECJPAKE_open(0, ¶ms); + * + * ECJPAKE_OperationRoundOneGenerateKeys operationRoundOneGenerateKeys; + * ECJPAKE_OperationRoundTwoGenerateKeys operationRoundTwoGenerateKeys; + * ECJPAKE_OperationGenerateZKP operationGenerateZKP; + * ECJPAKE_OperationVerifyZKP operationVerifyZKP; + * ECJPAKE_OperationComputeSharedSecret operationComputeSharedSecret; + * + * // Generate my round one keys + * ECJPAKE_OperationRoundOneGenerateKeys_init(&operationRoundOneGenerateKeys); + * operationRoundOneGenerateKeys.curve = &ECCParams_NISTP256; + * operationRoundOneGenerateKeys.myPrivateKey1 = &myPrivateCryptoKey1; + * operationRoundOneGenerateKeys.myPrivateKey2 = &myPrivateCryptoKey2; + * operationRoundOneGenerateKeys.myPublicKey1 = &myPublicCryptoKey1; + * operationRoundOneGenerateKeys.myPublicKey2 = &myPublicCryptoKey2; + * operationRoundOneGenerateKeys.myPrivateV1 = &myPrivateCryptoV1; + * operationRoundOneGenerateKeys.myPrivateV2 = &myPrivateCryptoV2; + * operationRoundOneGenerateKeys.myPublicV1 = &myPublicCryptoV1; + * operationRoundOneGenerateKeys.myPublicV2 = &myPublicCryptoV2; + * + * result = ECJPAKE_roundOneGenerateKeys(handle, &operationRoundOneGenerateKeys); + * + * // Generate hashes here + * + * // generate my round one ZKPs + * ECJPAKE_OperationGenerateZKP_init(&operationGenerateZKP); + * operationGenerateZKP.curve = &ECCParams_NISTP256; + * operationGenerateZKP.myPrivateKey = &myPrivateCryptoKey1; + * operationGenerateZKP.myPrivateV = &myPrivateCryptoV1; + * operationGenerateZKP.hash = myHash1; + * operationGenerateZKP.r = myR1; + * + * result = ECJPAKE_generateZKP(handle, &operationGenerateZKP); + * + * ECJPAKE_OperationGenerateZKP_init(&operationGenerateZKP); + * operationGenerateZKP.curve = &ECCParams_NISTP256; + * operationGenerateZKP.myPrivateKey = &myPrivateCryptoKey2; + * operationGenerateZKP.myPrivateV = &myPrivateCryptoV2; + * operationGenerateZKP.hash = myHash2; + * operationGenerateZKP.r = myR2; + * + * result = ECJPAKE_generateZKP(handle, &operationGenerateZKP); + * + * // Do ZKP and key transmission here + * + * // Verify their round one ZKPs + * // Generate their hashes here + * + * ECJPAKE_OperationVerifyZKP_init(&operationVerifyZKP); + * operationVerifyZKP.curve = &ECCParams_NISTP256; + * operationVerifyZKP.theirGenerator = &nistP256GeneratorCryptoKey; + * operationVerifyZKP.theirPublicKey = &theirPublicCryptoKey1; + * operationVerifyZKP.theirPublicV = &theirPublicCryptoV1; + * operationVerifyZKP.hash = theirHash1; + * operationVerifyZKP.r = theirR1; + * + * result = ECJPAKE_verifyZKP(handle, &operationVerifyZKP); + * + * ECJPAKE_OperationVerifyZKP_init(&operationVerifyZKP); + * operationVerifyZKP.curve = &ECCParams_NISTP256; + * operationVerifyZKP.theirGenerator = &nistP256GeneratorCryptoKey; + * operationVerifyZKP.theirPublicKey = &theirPublicCryptoKey2; + * operationVerifyZKP.theirPublicV = &theirPublicCryptoV2; + * operationVerifyZKP.hash = theirHash2; + * operationVerifyZKP.r = theirR2; + * + * result = ECJPAKE_verifyZKP(handle,&operationVerifyZKP); + * + * // Round two starts now + * + * // Generate my round two keys + * ECJPAKE_OperationRoundTwoGenerateKeys_init(&operationRoundTwoGenerateKeys); + * operationRoundTwoGenerateKeys.curve = &ECCParams_NISTP256; + * operationRoundTwoGenerateKeys.myPrivateKey2 = &myPrivateCryptoKey2; + * operationRoundTwoGenerateKeys.myPublicKey1 = &myPublicCryptoKey1; + * operationRoundTwoGenerateKeys.myPublicKey2 = &myPublicCryptoKey2; + * operationRoundTwoGenerateKeys.theirPublicKey1 = &theirPublicCryptoKey1; + * operationRoundTwoGenerateKeys.theirPublicKey2 = &theirPublicCryptoKey2; + * operationRoundTwoGenerateKeys.preSharedSecret = &preSharedSecretCryptoKey; + * operationRoundTwoGenerateKeys.theirNewGenerator = &theirGeneratorKey; + * operationRoundTwoGenerateKeys.myNewGenerator = &myGeneratorKey; + * operationRoundTwoGenerateKeys.myCombinedPrivateKey = &myCombinedPrivateKey; + * operationRoundTwoGenerateKeys.myCombinedPublicKey = &myCombinedPublicKey; + * operationRoundTwoGenerateKeys.myPrivateV = &myPrivateCryptoV3; + * operationRoundTwoGenerateKeys.myPublicV = &myPublicCryptoV3; + * + * result = ECJPAKE_roundTwoGenerateKeys(handle, &operationRoundTwoGenerateKeys); + * + * // Generate my round two ZKP + * // Generate the round two hash here + * + * ECJPAKE_OperationGenerateZKP_init(&operationGenerateZKP); + * operationGenerateZKP.curve = &ECCParams_NISTP256; + * operationGenerateZKP.myPrivateKey = &myCombinedPrivateKey; + * operationGenerateZKP.myPrivateV = &myPrivateCryptoV3; + * operationGenerateZKP.hash = myHash3; + * operationGenerateZKP.r = myR3; + * + * result = ECJPAKE_generateZKP(handle, &operationGenerateZKP); + * + * // Exchange keys and ZKPs again + * + * // Verify their second round ZKP + * // Generate their round two hash here + * + * ECJPAKE_OperationVerifyZKP_init(&operationVerifyZKP); + * operationVerifyZKP.curve = &ECCParams_NISTP256; + * operationVerifyZKP.theirGenerator = &theirGeneratorKey; + * operationVerifyZKP.theirPublicKey = &theirCombinedPublicKey; + * operationVerifyZKP.theirPublicV = &theirPublicCryptoV3; + * operationVerifyZKP.hash = theirHash3; + * operationVerifyZKP.r = theirR3; + * + * result = ECJPAKE_verifyZKP(handle, &operationVerifyZKP); + * + * // Generate shared secret + * ECJPAKE_OperationComputeSharedSecret_init(&operationComputeSharedSecret); + * operationComputeSharedSecret.curve = &ECCParams_NISTP256; + * operationComputeSharedSecret.myCombinedPrivateKey = &myCombinedPrivateKey; + * operationComputeSharedSecret.theirCombinedPublicKey = &theirCombinedPublicKey; + * operationComputeSharedSecret.theirPublicKey2 = &theirPublicCryptoKey2; + * operationComputeSharedSecret.myPrivateKey2 = &myPrivateCryptoKey2; + * operationComputeSharedSecret.sharedSecret = &sharedSecretCryptoKey; + * + * result = ECJPAKE_computeSharedSecret(handle, &operationComputeSharedSecret); + * + * // Close the driver + * ECJPAKE_close(handle); + * @endcode + * + * @anchor ti_drivers_ECJPAKE_Examples + * # Examples # + * + * ## Basic ECJPAKE exchange # + * + * @code + * + * + * // My fixed keying material + * uint8_t myPrivateKeyMaterial1[32]; + * uint8_t myPrivateKeyMaterial2[32]; + * uint8_t myPrivateVMaterial1[32]; + * uint8_t myPrivateVMaterial2[32]; + * uint8_t myPrivateVMaterial3[32]; + * uint8_t myHash1[32]; + * uint8_t myHash2[32]; + * uint8_t myHash3[32]; + * // My derived keying material + * uint8_t myR1[32]; + * uint8_t myR2[32]; + * uint8_t myR3[32]; + * uint8_t myPublicKeyMaterial1[64]; + * uint8_t myPublicKeyMaterial2[64]; + * uint8_t myPublicVMaterial1[64]; + * uint8_t myPublicVMaterial2[64]; + * uint8_t myPublicVMaterial3[64]; + * uint8_t myCombinedPublicKeyMaterial1[64]; + * uint8_t myCombinedPrivateKeyMaterial1[32]; + * uint8_t myGenerator[64]; + * + * // Their fixed keying material + * uint8_t theirHash1[32]; + * uint8_t theirHash2[32]; + * uint8_t theirHash3[32]; + * + * // Their derived keying material + * uint8_t theirR1[32]; + * uint8_t theirR2[32]; + * uint8_t theirR3[32]; + * uint8_t theirPublicKeyMaterial1[64]; + * uint8_t theirPublicKeyMaterial2[64]; + * uint8_t theirPublicVMaterial1[64]; + * uint8_t theirPublicVMaterial2[64]; + * uint8_t theirPublicVMaterial3[64]; + * uint8_t theirCombinedPublicKeyMaterial1[64]; + * uint8_t theirGenerator[64]; + * + * // Shared secrets + * uint8_t preSharedSecretKeyingMaterial[32] = "This is our password"; + * uint8_t sharedSecretKeyingMaterial1[64]; + * + * // CryptoKeys + * CryptoKey nistP256GeneratorCryptoKey; + * + * // Pre-Shared Secret Key + * CryptoKey preSharedSecretCryptoKey; + * + * // Final shared secret keys + * CryptoKey sharedSecretCryptoKey; + * + * // My's keys + * CryptoKey myPrivateCryptoKey1; + * CryptoKey myPrivateCryptoKey2; + * CryptoKey myPrivateCryptoV1; + * CryptoKey myPrivateCryptoV2; + * CryptoKey myPrivateCryptoV3; + * CryptoKey myCombinedPrivateKey; + * + * CryptoKey myPublicCryptoKey1; + * CryptoKey myPublicCryptoKey2; + * CryptoKey myPublicCryptoV1; + * CryptoKey myPublicCryptoV2; + * CryptoKey myPublicCryptoV3; + * CryptoKey myCombinedPublicKey; + * CryptoKey myGeneratorKey; + * + * // Their's Keys + * CryptoKey theirPublicCryptoKey1; + * CryptoKey theirPublicCryptoKey2; + * CryptoKey theirPublicCryptoV1; + * CryptoKey theirPublicCryptoV2; + * CryptoKey theirPublicCryptoV3; + * CryptoKey theirCombinedPublicKey; + * CryptoKey theirGeneratorKey; + * + * // NISTP256 generator + * CryptoKeyPlaintext_initKey(&nistP256GeneratorCryptoKey, ECCParams_NISTP256.generatorX, sizeof(ECCParams_NISTP256.length * 2)); + * + * // Pre-shared secret + * CryptoKeyPlaintext_initKey(&preSharedSecretCryptoKey, preSharedSecretKeyingMaterial, sizeof(preSharedSecretKeyingMaterial)); + * + * // Final shared secret key + * CryptoKeyPlaintext_initKey(&sharedSecretCryptoKey, sharedSecretKeyingMaterial1, sizeof(sharedSecretKeyingMaterial1)); + * CryptoKeyPlaintext_initKey(&sharedSecretCryptoKey2, sharedSecretKeyingMaterial2, sizeof(sharedSecretKeyingMaterial2)); + * + * + * // My keys + * CryptoKeyPlaintext_initKey(&myPrivateCryptoKey1, myPrivateKeyMaterial1, sizeof(myPrivateKeyMaterial1)); + * CryptoKeyPlaintext_initKey(&myPrivateCryptoKey2, myPrivateKeyMaterial2, sizeof(myPrivateKeyMaterial2)); + * CryptoKeyPlaintext_initKey(&myPrivateCryptoV1, myPrivateVMaterial1, sizeof(myPrivateVMaterial1)); + * CryptoKeyPlaintext_initKey(&myPrivateCryptoV2, myPrivateVMaterial2, sizeof(myPrivateVMaterial2)); + * CryptoKeyPlaintext_initKey(&myPrivateCryptoV3, myPrivateVMaterial3, sizeof(myPrivateVMaterial3)); + * + * CryptoKeyPlaintext_initBlankKey(&myPublicCryptoKey1, myPublicKeyMaterial1, sizeof(myPublicKeyMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&myPublicCryptoKey2, myPublicKeyMaterial2, sizeof(myPublicKeyMaterial2)); + * CryptoKeyPlaintext_initBlankKey(&myPublicCryptoV1, myPublicVMaterial1, sizeof(myPublicVMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&myPublicCryptoV2, myPublicVMaterial2, sizeof(myPublicVMaterial2)); + * CryptoKeyPlaintext_initBlankKey(&myPublicCryptoV3, myPublicVMaterial3, sizeof(myPublicVMaterial3)); + * CryptoKeyPlaintext_initBlankKey(&myCombinedPrivateKey, myCombinedPrivateKeyMaterial1, sizeof(myCombinedPrivateKeyMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&myCombinedPublicKey, myCombinedPublicKeyMaterial1, sizeof(myCombinedPublicKeyMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&myGeneratorKey, myGenerator, sizeof(myGenerator)); + * + * // Their keys + * CryptoKeyPlaintext_initBlankKey(&theirPublicCryptoKey1, theirPublicKeyMaterial1, sizeof(theirPublicKeyMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&theirPublicCryptoKey2, theirPublicKeyMaterial2, sizeof(theirPublicKeyMaterial2)); + * CryptoKeyPlaintext_initBlankKey(&theirPublicCryptoV1, theirPublicVMaterial1, sizeof(theirPublicVMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&theirPublicCryptoV2, theirPublicVMaterial2, sizeof(theirPublicVMaterial2)); + * CryptoKeyPlaintext_initBlankKey(&theirPublicCryptoV3, theirPublicVMaterial3, sizeof(theirPublicVMaterial3)); + * CryptoKeyPlaintext_initBlankKey(&theirCombinedPublicKey, theirCombinedPublicKeyMaterial1, sizeof(theirCombinedPublicKeyMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&theirGeneratorKey, theirGenerator, sizeof(theirGenerator)); + * + * // Initial driver setup + * ECJPAKE_Params params; + * ECJPAKE_Params_init(¶ms); + * + * + * ECJPAKE_Handle handle = ECJPAKE_open(0, ¶ms); + * + * ECJPAKE_OperationRoundOneGenerateKeys operationRoundOneGenerateKeys; + * ECJPAKE_OperationRoundTwoGenerateKeys operationRoundTwoGenerateKeys; + * ECJPAKE_OperationGenerateZKP operationGenerateZKP; + * ECJPAKE_OperationVerifyZKP operationVerifyZKP; + * ECJPAKE_OperationComputeSharedSecret operationComputeSharedSecret; + * + * // Generate my round one keys + * ECJPAKE_OperationRoundOneGenerateKeys_init(&operationRoundOneGenerateKeys); + * operationRoundOneGenerateKeys.curve = &ECCParams_NISTP256; + * operationRoundOneGenerateKeys.myPrivateKey1 = &myPrivateCryptoKey1; + * operationRoundOneGenerateKeys.myPrivateKey2 = &myPrivateCryptoKey2; + * operationRoundOneGenerateKeys.myPublicKey1 = &myPublicCryptoKey1; + * operationRoundOneGenerateKeys.myPublicKey2 = &myPublicCryptoKey2; + * operationRoundOneGenerateKeys.myPrivateV1 = &myPrivateCryptoV1; + * operationRoundOneGenerateKeys.myPrivateV2 = &myPrivateCryptoV2; + * operationRoundOneGenerateKeys.myPublicV1 = &myPublicCryptoV1; + * operationRoundOneGenerateKeys.myPublicV2 = &myPublicCryptoV2; + * + * int_fast16_t result = ECJPAKE_roundOneGenerateKeys(handle, &operationRoundOneGenerateKeys); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * // Generate hashes here + * + * // generate my round one ZKPs + * ECJPAKE_OperationGenerateZKP_init(&operationGenerateZKP); + * operationGenerateZKP.curve = &ECCParams_NISTP256; + * operationGenerateZKP.myPrivateKey = &myPrivateCryptoKey1; + * operationGenerateZKP.myPrivateV = &myPrivateCryptoV1; + * operationGenerateZKP.hash = myHash1; + * operationGenerateZKP.r = myR1; + * + * result = ECJPAKE_generateZKP(handle, &operationGenerateZKP); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * ECJPAKE_OperationGenerateZKP_init(&operationGenerateZKP); + * operationGenerateZKP.curve = &ECCParams_NISTP256; + * operationGenerateZKP.myPrivateKey = &myPrivateCryptoKey2; + * operationGenerateZKP.myPrivateV = &myPrivateCryptoV2; + * operationGenerateZKP.hash = myHash2; + * operationGenerateZKP.r = myR2; + * + * result = ECJPAKE_generateZKP(handle, &operationGenerateZKP); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * // Do ZKP and key transmission here + * + * // Verify their round one ZKPs + * // Generate their hashes here + * + * ECJPAKE_OperationVerifyZKP_init(&operationVerifyZKP); + * operationVerifyZKP.curve = &ECCParams_NISTP256; + * operationVerifyZKP.theirGenerator = &nistP256GeneratorCryptoKey; + * operationVerifyZKP.theirPublicKey = &theirPublicCryptoKey1; + * operationVerifyZKP.theirPublicV = &theirPublicCryptoV1; + * operationVerifyZKP.hash = theirHash1; + * operationVerifyZKP.r = theirR1; + * + * result = ECJPAKE_verifyZKP(handle, &operationVerifyZKP); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * ECJPAKE_OperationVerifyZKP_init(&operationVerifyZKP); + * operationVerifyZKP.curve = &ECCParams_NISTP256; + * operationVerifyZKP.theirGenerator = &nistP256GeneratorCryptoKey; + * operationVerifyZKP.theirPublicKey = &theirPublicCryptoKey2; + * operationVerifyZKP.theirPublicV = &theirPublicCryptoV2; + * operationVerifyZKP.hash = theirHash2; + * operationVerifyZKP.r = theirR2; + * + * result = ECJPAKE_verifyZKP(handle,&operationVerifyZKP); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * // Round two starts now + * + * // Generate my round two keys + * ECJPAKE_OperationRoundTwoGenerateKeys_init(&operationRoundTwoGenerateKeys); + * operationRoundTwoGenerateKeys.curve = &ECCParams_NISTP256; + * operationRoundTwoGenerateKeys.myPrivateKey2 = &myPrivateCryptoKey2; + * operationRoundTwoGenerateKeys.myPublicKey1 = &myPublicCryptoKey1; + * operationRoundTwoGenerateKeys.myPublicKey2 = &myPublicCryptoKey2; + * operationRoundTwoGenerateKeys.theirPublicKey1 = &theirPublicCryptoKey1; + * operationRoundTwoGenerateKeys.theirPublicKey2 = &theirPublicCryptoKey2; + * operationRoundTwoGenerateKeys.preSharedSecret = &preSharedSecretCryptoKey; + * operationRoundTwoGenerateKeys.theirNewGenerator = &theirGeneratorKey; + * operationRoundTwoGenerateKeys.myNewGenerator = &myGeneratorKey; + * operationRoundTwoGenerateKeys.myCombinedPrivateKey = &myCombinedPrivateKey; + * operationRoundTwoGenerateKeys.myCombinedPublicKey = &myCombinedPublicKey; + * operationRoundTwoGenerateKeys.myPrivateV = &myPrivateCryptoV3; + * operationRoundTwoGenerateKeys.myPublicV = &myPublicCryptoV3; + * + * result = ECJPAKE_roundTwoGenerateKeys(handle, &operationRoundTwoGenerateKeys); + * + * // Generate my round two ZKP + * // Generate the round two hash here + * + * ECJPAKE_OperationGenerateZKP_init(&operationGenerateZKP); + * operationGenerateZKP.curve = &ECCParams_NISTP256; + * operationGenerateZKP.myPrivateKey = &myCombinedPrivateKey; + * operationGenerateZKP.myPrivateV = &myPrivateCryptoV3; + * operationGenerateZKP.hash = myHash3; + * operationGenerateZKP.r = myR3; + * + * result = ECJPAKE_generateZKP(handle, &operationGenerateZKP); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * // Exchange keys and ZKPs again + * + * // Verify their second round ZKP + * // Generate their round two hash here + * + * ECJPAKE_OperationVerifyZKP_init(&operationVerifyZKP); + * operationVerifyZKP.curve = &ECCParams_NISTP256; + * operationVerifyZKP.theirGenerator = &theirGeneratorKey; + * operationVerifyZKP.theirPublicKey = &theirCombinedPublicKey; + * operationVerifyZKP.theirPublicV = &theirPublicCryptoV3; + * operationVerifyZKP.hash = theirHash3; + * operationVerifyZKP.r = theirR3; + * + * result = ECJPAKE_verifyZKP(handle, &operationVerifyZKP); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * + * // Generate shared secret + * ECJPAKE_OperationComputeSharedSecret_init(&operationComputeSharedSecret); + * operationComputeSharedSecret.curve = &ECCParams_NISTP256; + * operationComputeSharedSecret.myCombinedPrivateKey = &myCombinedPrivateKey; + * operationComputeSharedSecret.theirCombinedPublicKey = &theirCombinedPublicKey; + * operationComputeSharedSecret.theirPublicKey2 = &theirPublicCryptoKey2; + * operationComputeSharedSecret.myPrivateKey2 = &myPrivateCryptoKey2; + * operationComputeSharedSecret.sharedSecret = &sharedSecretCryptoKey; + * + * result = ECJPAKE_computeSharedSecret(handle, &operationComputeSharedSecret); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * // Run sharedSecretCryptoKey through a key derivation function and + * // confirm to the other party that we have derived the same key + * + * + * @endcode + * + * + */ + + +#ifndef ti_drivers_ECJPAKE__include +#define ti_drivers_ECJPAKE__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include +#include + +/*! + * Common ECJPAKE status code reservation offset. + * ECJPAKE driver implementations should offset status codes with + * ECJPAKE_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ECJPAKEXYZ_STATUS_ERROR0 ECJPAKE_STATUS_RESERVED - 0 + * #define ECJPAKEXYZ_STATUS_ERROR1 ECJPAKE_STATUS_RESERVED - 1 + * #define ECJPAKEXYZ_STATUS_ERROR2 ECJPAKE_STATUS_RESERVED - 2 + * @endcode + */ +#define ECJPAKE_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return ECJPAKE_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define ECJPAKE_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return ECJPAKE_STATUS_ERROR if the function was not executed + * successfully. + */ +#define ECJPAKE_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * ECJPAKE driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define ECJPAKE_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief The public key of the other party is not valid. + * + * The public key received from the other party is not valid. + */ +#define ECJPAKE_STATUS_INVALID_PUBLIC_KEY (-3) + +/*! + * @brief The public key of the other party does not lie upon the curve. + * + * The public key received from the other party does not lie upon the agreed upon + * curve. + */ +#define ECJPAKE_STATUS_PUBLIC_KEY_NOT_ON_CURVE (-4) + +/*! + * @brief A coordinate of the public key of the other party is too large. + * + * A coordinate of the public key received from the other party is larger than + * the prime of the curve. This implies that the point was not correctly + * generated on that curve. + */ +#define ECJPAKE_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME (-5) + +/*! + * @brief The result of the operation is the point at infinity. + * + * The operation yielded the point at infinity on this curve. This point is + * not permitted for further use in ECC operations. + */ +#define ECJPAKE_STATUS_POINT_AT_INFINITY (-6) + +/*! + * @brief The private key passed into the the call is invalid. + * + * Private keys must be integers in the interval [1, n - 1], where n is the + * order of the curve. + */ +#define ECJPAKE_STATUS_INVALID_PRIVATE_KEY (-7) + +/*! + * @brief The private v passed into the the call is invalid. + * + * Private v must be integers in the interval [1, n - 1], where n is the + * order of the curve. + */ +#define ECJPAKE_STATUS_INVALID_PRIVATE_V (-8) + +/*! + * @brief The ongoing operation was canceled. + */ +#define ECJPAKE_STATUS_CANCELED (-9) + +/*! + * @brief A handle that is returned from an ECJPAKE_open() call. + */ +typedef struct ECJPAKE_Config *ECJPAKE_Handle; + +/*! + * @brief The way in which ECJPAKE function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all ECJPAKE operations exhibit the specified return behavor. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specfied return behavior is + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * ECJPAKE functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |----------------------------------|-------|-------|-------| + * |ECJPAKE_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |ECJPAKE_RETURN_BEHAVIOR_BLOCKING | X | | | + * |ECJPAKE_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum { + ECJPAKE_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * ECJPAKE operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + ECJPAKE_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECJPAKE operation goes + * on in the background. ECJPAKE operation results are available + * after the function returns. + */ + ECJPAKE_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECJPAKE + * operation goes on in the background. ECJPAKE operation results + * are available after the function returns. + */ +} ECJPAKE_ReturnBehavior; + +/*! + * @brief ECJPAKE Global configuration + * + * The ECJPAKE_Config structure contains a set of pointers used to characterize + * the ECJPAKE driver implementation. + * + * This structure needs to be defined before calling ECJPAKE_init() and it must + * not be changed thereafter. + * + * @sa ECJPAKE_init() + */ +typedef struct ECJPAKE_Config { + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} ECJPAKE_Config; + +/*! + * @brief Struct containing the parameters required to generate the first round of keys. + */ +typedef struct { + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + CryptoKey *myPrivateKey1; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. + */ + CryptoKey *myPrivateKey2; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. + */ + CryptoKey *myPublicKey1; /*!< A pointer to the blank public key of \c + * myPrivateKey1. The keying material will be + * written to the buffer specified in the + * CryptoKey. + */ + CryptoKey *myPublicKey2; /*!< A pointer to the blank public key of \c + * myPrivateKey2. The keying material will be + * written to the buffer specified in the + * CryptoKey. + */ + CryptoKey *myPrivateV1; /*!< A pointer to a private ECC key used in the + * first Schnorr ZKP. + * Must be of the same length as other params + * of the curve used. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the ZKP. + */ + CryptoKey *myPrivateV2; /*!< A pointer to a private ECC key used in the + * second Schnorr ZKP. + * Must be of the same length as other params + * of the curve used. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the ZKP. + */ + CryptoKey *myPublicV1; /*!< A pointer to the blank public key of \c + * myPrivateV1. The keying material will be + * written to the buffer specified in the + * CryptoKey. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the hash and sending \c myPublicV2 + * to the other party with the rest of the + * parameters. + */ + CryptoKey *myPublicV2; /*!< A pointer to the blank public key of \c + * myPrivateV2. The keying material will be + * written to the buffer specified in the + * CryptoKey. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the hash and sending \c myPublicV2 + * to the other party with the rest of the + * parameters. + */ +} ECJPAKE_OperationRoundOneGenerateKeys; + +/*! + * @brief Struct containing the parameters required to generate a ZKP. + */ +typedef struct { + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + const CryptoKey *myPrivateKey; /*!< A pointer to a private ECC key to be signed. Must + * be of the same length as other params + * of the curve used. + */ + const CryptoKey *myPrivateV; /*!< A pointer to a private ECC key that will be + * used only to generate a ZKP signature. + * Must be of the same length as other params + * of the curve used. + */ + const uint8_t *hash; /*!< A pointer to the hash of the message. + * Must be of the same length as other params + * of the curve used. + */ + uint8_t *r; /*!< A pointer to where the r component of the + * ZKP will be written to. + */ +} ECJPAKE_OperationGenerateZKP; + +/*! + * @brief Struct containing the parameters required to verify a ZKP. + */ +typedef struct { + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + const CryptoKey *theirGenerator; /*!< A CryptoKey describing the generator point + * to be used. In the first round, this will + * be the default generator of the curve. + * In the second round, this parameter is + * computed by ECJPAKE_roundTwoGenerateKeys(). + */ + const CryptoKey *theirPublicKey; /*!< A CryptoKey describing the public key + * received from the other party that the + * ZKP to be verified supposedly signed. + */ + const CryptoKey *theirPublicV; /*!< A CryptoKey describing the public V of the + * ZKP. Received from the other party. + */ + const uint8_t *hash; /*!< The hash of the ZKP generated as the + * other party generated it to compute r. + */ + const uint8_t *r; /*!< R component of the ZKP signature. Received + * from the other party. + */ +} ECJPAKE_OperationVerifyZKP; + +/*! + * @brief Struct containing the parameters required to generate the second round keys. + */ +typedef struct { + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + const CryptoKey *myPrivateKey2; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. Generated in round one. + */ + const CryptoKey *myPublicKey1; /*!< A pointer to the public key of + * myPrivateKey1. Generated in round one. + */ + const CryptoKey *myPublicKey2; /*!< A pointer to the second public key. + * Generated in round one. + */ + const CryptoKey *theirPublicKey1; /*!< A CryptoKey describing the first public key + * received from the other party. + */ + const CryptoKey *theirPublicKey2; /*!< A CryptoKey describing the second public key + * received from the other party. + */ + const CryptoKey *preSharedSecret; /*!< A CryptoKey describing the secret shared between + * the two parties prior to starting the scheme. + * This exchange would have happened through some + * offline commissioning scheme most likely. + * The driver expects an integer of the same length + * as the curve parameters of the curve in use as + * keying material even if the original pre-shared + * secret is shorter than this length. + */ + CryptoKey *theirNewGenerator; /*!< A blank CryptoKey describing the generator point + * used by the other party in the second round. + * After it is computed, the keying material will + * be written to the location described in the + * CryptoKey. + */ + CryptoKey *myNewGenerator; /*!< A blank CryptoKey describing the generator point + * used by the application in the second round. + * After it is computed, the keying material will + * be written to the location described in the + * CryptoKey. + */ + CryptoKey *myCombinedPrivateKey; /*!< A pointer to a public ECC key. Must + * be of the same length as other params + * of the curve used. Result of multiplying + * \c myCombinedPrivateKey by \c myNewGenerator. + */ + CryptoKey *myCombinedPublicKey; /*!< A pointer to a public ECC key. Result of multiplying + * \c myCombinedPrivateKey by \c myNewGenerator. + */ + CryptoKey *myPrivateV; /*!< A pointer to a private ECC key used in the + * only second-round Schnorr ZKP. + * Must be of the same length as other params + * of the curve used. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the ZKP. + */ + CryptoKey *myPublicV; /*!< A pointer to the blank public key of \c + * myPrivateV. The keying material will be + * written to the buffer specified in the + * CryptoKey. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the hash and sending \c myPublicV2 + * to the other party with the rest of the + * parameters. + */ +} ECJPAKE_OperationRoundTwoGenerateKeys; + +/*! + * @brief Struct containing the parameters required to compute the shared secret. + */ +typedef struct { + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + const CryptoKey *myCombinedPrivateKey; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. Generated in round one. + */ + const CryptoKey *theirCombinedPublicKey; /*!< A CryptoKey describing the second public key + * received from the other party. + */ + const CryptoKey *theirPublicKey2; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. Result of multiplying + * \c myPrivateKey2 by \c preSharedSecret. + */ + const CryptoKey *myPrivateKey2; /*!< Combined public key received in the second + * round and verified by the application against + * the second round ZKP signature. + */ + CryptoKey *sharedSecret; /*!< The shared secret that is identical between both + * parties. + */ +} ECJPAKE_OperationComputeSharedSecret; + + +/*! + * @brief Union containing pointers to all supported operation structs. + */ +typedef union { + ECJPAKE_OperationRoundOneGenerateKeys *generateRoundOneKeys; /*!< A pointer to an ECJPAKE_OperationRoundOneGenerateKeys struct */ + ECJPAKE_OperationGenerateZKP *generateZKP; /*!< A pointer to an ECJPAKE_OperationGenerateZKP struct */ + ECJPAKE_OperationVerifyZKP *verifyZKP; /*!< A pointer to an ECJPAKE_OperationVerifyZKP struct */ + ECJPAKE_OperationRoundTwoGenerateKeys *generateRoundTwoKeys; /*!< A pointer to an ECJPAKE_OperationRoundTwoGenerateKeys struct */ + ECJPAKE_OperationComputeSharedSecret *computeSharedSecret; /*!< A pointer to an ECJPAKE_OperationComputeSharedSecret struct */ +} ECJPAKE_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum { + ECJPAKE_OPERATION_TYPE_ROUND_ONE_GENERATE_KEYS = 1, + ECJPAKE_OPERATION_TYPE_GENERATE_ZKP = 2, + ECJPAKE_OPERATION_TYPE_VERIFY_ZKP = 3, + ECJPAKE_OPERATION_TYPE_ROUND_TWO_GENERATE_KEYS = 4, + ECJPAKE_OPERATION_TYPE_COMPUTE_SHARED_SECRET = 5, +} ECJPAKE_OperationType; + +/*! + * @brief The definition of a callback function used by the ECJPAKE driver + * when used in ::ECJPAKE_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the ECJPAKE operation. + * + * @param returnStatus The result of the ECJPAKE operation. May contain an error code + * if the result is the point at infinity for example. + * + * @param operation A union of pointers to operation structs. Only one type + * of pointer is valid per call to the callback function. Which type + * is currently valid is determined by /c operationType. The union + * allows easier access to the struct's fields without the need to + * typecase the result. + * + * @param operationType This parameter determined which operation the + * callback refers to and which type to access through /c operation. + */ +typedef void (*ECJPAKE_CallbackFxn) (ECJPAKE_Handle handle, + int_fast16_t returnStatus, + ECJPAKE_Operation operation, + ECJPAKE_OperationType operationType); + +/*! + * @brief ECJPAKE Parameters + * + * ECJPAKE Parameters are used to with the ECJPAKE_open() call. Default values for + * these parameters are set using ECJPAKE_Params_init(). + * + * @sa ECJPAKE_Params_init() + */ +typedef struct { + ECJPAKE_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + ECJPAKE_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout in system ticks before the operation fails + * and returns + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} ECJPAKE_Params; + +/*! + * @brief This function initializes the ECJPAKE module. + * + * @pre The ECJPAKE_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other ECJPAKE driver APIs. This function call does not modify any + * peripheral registers. + */ +void ECJPAKE_init(void); + +/*! + * @brief Function to initialize an ECJPAKE_OperationRoundOneGenerateKeys struct to its defaults + * + * @param operation A pointer to ECJPAKE_OperationRoundOneGenerateKeys structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECJPAKE_OperationRoundOneGenerateKeys_init(ECJPAKE_OperationRoundOneGenerateKeys *operation); + +/*! + * @brief Function to initialize an ECJPAKE_OperationGenerateZKP struct to its defaults + * + * @param operation A pointer to ECJPAKE_OperationGenerateZKP structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECJPAKE_OperationGenerateZKP_init(ECJPAKE_OperationGenerateZKP *operation); + +/*! + * @brief Function to initialize an ECJPAKE_OperationVerifyZKP struct to its defaults + * + * @param operation A pointer to ECJPAKE_OperationVerifyZKP structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECJPAKE_OperationVerifyZKP_init(ECJPAKE_OperationVerifyZKP *operation); + +/*! + * @brief Function to initialize an ECJPAKE_OperationRoundTwoGenerateKeys struct to its defaults + * + * @param operation A pointer to ECJPAKE_OperationRoundTwoGenerateKeys structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECJPAKE_OperationRoundTwoGenerateKeys_init(ECJPAKE_OperationRoundTwoGenerateKeys *operation); + + +/*! + * @brief Function to initialize an ECJPAKE_OperationComputeSharedSecret struct to its defaults + * + * @param operation A pointer to ECJPAKE_OperationComputeSharedSecret structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECJPAKE_OperationComputeSharedSecret_init(ECJPAKE_OperationComputeSharedSecret *operation); + +/*! + * @brief Function to close an ECJPAKE peripheral specified by the ECJPAKE handle + * + * @pre ECJPAKE_open() has to be called first. + * + * @param handle An ECJPAKE handle returned from ECJPAKE_open() + * + * @sa ECJPAKE_open() + */ +void ECJPAKE_close(ECJPAKE_Handle handle); + +/*! + * @brief This function opens a given ECJPAKE peripheral. + * + * @pre ECJPAKE controller has been initialized using ECJPAKE_init() + * + * @param index Logical peripheral number for the ECJPAKE indexed into + * the ECJPAKE_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An ECJPAKE_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa ECJPAKE_init() + * @sa ECJPAKE_close() + */ +ECJPAKE_Handle ECJPAKE_open(uint_least8_t index, ECJPAKE_Params *params); + +/*! + * @brief Function to initialize the ECJPAKE_Params struct to its defaults + * + * @param params An pointer to ECJPAKE_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = ECJPAKE_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void ECJPAKE_Params_init(ECJPAKE_Params *params); + +/*! + * @brief Generates all public and private keying material for the first round of + * the EC-JPAKE scheme. + * + * This function generates all public and private keying material required for + * the first round of the EC-JPAKE scheme. + * + * @param [in] handle An ECJPAKE handle returned from ECJPAKE_open() + * + * @param [in] operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre Call ECJPAKE_OperationRoundOneGenerateKeys_init() on /c operation. + * + * @post Generate the two sets of hashes and ZKPs for the two public/private key pairs. + * + * @retval #ECJPAKE_STATUS_SUCCESS The operation succeeded. + * @retval #ECJPAKE_STATUS_ERROR The operation failed. + * @retval #ECJPAKE_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECJPAKE_STATUS_CANCELED The operation was canceled. + * @retval #ECJPAKE_STATUS_POINT_AT_INFINITY The computed public key is the point at infinity. + * @retval #ECJPAKE_STATUS_INVALID_PRIVATE_KEY The private key passed into the the call is invalid. + * @retval #ECJPAKE_STATUS_INVALID_PRIVATE_V The private v passed into the the call is invalid. + * + */ +int_fast16_t ECJPAKE_roundOneGenerateKeys(ECJPAKE_Handle handle, ECJPAKE_OperationRoundOneGenerateKeys *operation); + +/*! + * @brief Generates the \c r component of a Schnorr Zero-Knowledge Proof (ZKP) signature. + * + * This function generates the \c r component of a ZKP using the hash and private + * keys. The hash must be computed prior. + * This function does not compute the hash for the application. There is no strictly + * defined bit-level implementation guideline for generating the hash in the EC-JPAKE + * scheme. Hence, interoperability could not be guaranteed between different EC-JPAKE + * implementations. Usually, the hash will be a concatenation of the public V, public + * key, generator point, and user ID. There may be other components such as length + * fields mixed in. + * + * @param [in] handle An ECJPAKE handle returned from ECJPAKE_open() + * + * @param [in] operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre If in round one, ECJPAKE_roundOneGenerateKeys() must be called prior. + * Else, ECJPAKE_roundTwoGenerateKeys() must be called prior. The hash + * must also have been computed prior to calling this function. + * Call ECJPAKE_OperationGenerateZKP_init() on /c operation. + * + * + * @post Send all ZKP signatures (\c r, public V, user ID) together with the + * public keys to the other party. + * + * + * @retval #ECJPAKE_STATUS_SUCCESS The operation succeeded. + * @retval #ECJPAKE_STATUS_ERROR The operation failed. + * @retval #ECJPAKE_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECJPAKE_STATUS_CANCELED The operation was canceled. + */ +int_fast16_t ECJPAKE_generateZKP(ECJPAKE_Handle handle, ECJPAKE_OperationGenerateZKP *operation); + + /*! + * @brief Verifies a Schnorr Zero-Knowledge Proof (ZKP) signature. + * + * This function computes if a received Schnorr ZKP correctly verifies + * a received public key. + * + * @param [in] handle An ECJPAKE handle returned from ECJPAKE_open() + * + * @param [in] operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre Receive the relevant ZKP signature parameters. Compute the hash. + * If in the second round, compute the generator first by calling + * ECJPAKE_roundTwoGenerateKeys(). + * Call ECJPAKE_OperationVerifyZKP_init() on /c operation. + * + * @retval #ECJPAKE_STATUS_SUCCESS The operation succeeded. + * @retval #ECJPAKE_STATUS_ERROR The operation failed. Signature did not verify correctly. + * @retval #ECJPAKE_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECJPAKE_STATUS_CANCELED The operation was canceled. + * @retval #ECJPAKE_STATUS_PUBLIC_KEY_NOT_ON_CURVE The public key of the other party does not lie upon the curve. + * @retval #ECJPAKE_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME A coordinate of the public key of the other party is too large. + */ +int_fast16_t ECJPAKE_verifyZKP(ECJPAKE_Handle handle, ECJPAKE_OperationVerifyZKP *operation); + +/*! + * @brief Generates all public and private keying material for the first round of + * the EC-JPAKE scheme. + * + * This function generates all public and private keying material required for + * the first round of the EC-JPAKE scheme. + * + * @param [in] handle An ECJPAKE handle returned from ECJPAKE_open() + * + * @param [in] operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre Call ECJPAKE_OperationRoundTwoGenerateKeys_init() on /c operation. + * + * @post Generate the hash and ZKP signature for the second round public/private key. + * + * @retval #ECJPAKE_STATUS_SUCCESS The operation succeeded. + * @retval #ECJPAKE_STATUS_ERROR The operation failed. + * @retval #ECJPAKE_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECJPAKE_STATUS_CANCELED The operation was canceled. + * @retval #ECJPAKE_STATUS_INVALID_PRIVATE_KEY The private key passed into the the call is invalid. + * @retval #ECJPAKE_STATUS_INVALID_PRIVATE_V The private v passed into the the call is invalid. + */ +int_fast16_t ECJPAKE_roundTwoGenerateKeys(ECJPAKE_Handle handle, ECJPAKE_OperationRoundTwoGenerateKeys *operation); + +/*! + * @brief Computes the shared secret. + * + * This function computes the shared secret between both parties. The shared + * secret is a point on the elliptic curve and is used to further derive the + * symmetric session key via a key derivation function. + * + * @param [in] handle An ECJPAKE handle returned from ECJPAKE_open() + * + * @param [in] operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre Call ECJPAKE_OperationComputeSharedSecret_init() on /c operation. + * + * @post The shared secret must be processed by a key derivation function to + * compute the symmetric session key. It is recommended that the two parties + * prove to each other that they are in posession of the symmetric session + * key. While this should be implied by the successful verification of + * the three ZKPs in the scheme, it is nonetheless good practice. + * + * @retval #ECJPAKE_STATUS_SUCCESS The operation succeeded. + * @retval #ECJPAKE_STATUS_ERROR The operation failed. + * @retval #ECJPAKE_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECJPAKE_STATUS_CANCELED The operation was canceled. + */ +int_fast16_t ECJPAKE_computeSharedSecret(ECJPAKE_Handle handle, ECJPAKE_OperationComputeSharedSecret *operation); + +/*! + * @brief Cancels an ongoing ECJPAKE operation. + * + * Asynchronously cancels an ECJPAKE operation. Only available when using + * ECJPAKE_RETURN_BEHAVIOR_CALLBACK or ECJPAKE_RETURN_BEHAVIOR_BLOCKING. + * The operation will terminate as though an error occured. The + * return status code of the operation will be ECJPAKE_STATUS_CANCELED. + * + * @param handle Handle of the operation to cancel + * + * @retval #ECJPAKE_STATUS_SUCCESS The operation was canceled. + * @retval #ECJPAKE_STATUS_ERROR The operation was not canceled. There may be no operation to cancel. + */ +int_fast16_t ECJPAKE_cancelOperation(ECJPAKE_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ECJPAKE__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/GPIO.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/GPIO.h new file mode 100644 index 0000000..7462f8b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/GPIO.h @@ -0,0 +1,555 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file GPIO.h + * + * @brief General Purpose I/O driver interface. + * + * The GPIO header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * The GPIO module allows you to manage General Purpose I/O pins via simple + * and portable APIs. GPIO pin behavior is usually configured statically, + * but can also be configured or reconfigured at runtime. + * + * Because of its simplicity, the GPIO driver does not follow the model of + * other TI-RTOS drivers in which a driver application interface has + * separate device-specific implementations. This difference is most + * apparent in the GPIOxxx_Config structure, which does not require you to + * specify a particular function table or object. + * + * # Usage # + * This section provides a basic \ref ti_drivers_GPIO_Synopsis + * "usage summary" and a set of \ref ti_drivers_GPIO_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * GPIO APIs and their effect are provided in subsequent sections. + * + * @anchor ti_drivers_GPIO_Synopsis + * ### Synopsis # + * @anchor ti_drivers_GPIO_Synopsis_Code + * @code + * // Import GPIO Driver definitions + * #include + * + * // Define names for GPIO pin indexes + * #define BUTTON 0 + * #define LED 1 + * + * // One-time init of GPIO driver + * GPIO_init(); + * + * // Read GPIO pin + * unsigned int state = GPIO_read(BUTTON); + * + * // Write to GPIO pin + * GPIO_write(LED, state); + * @endcode + * + * @anchor ti_drivers_GPIO_Examples + * ### Examples # + * * @ref ti_drivers_GPIO_Example_callback "Creating an input callback" + * * @ref ti_drivers_GPIO_Example_reconfigure "Runtime pin configuration" + * + * @anchor ti_drivers_GPIO_Example_callback + * **Creating an input callback**: The following example demonstrates how + * to configure a GPIO pin to generate an interrupt and how to toggle an + * an LED on and off within the registered interrupt callback function. + * @code + * // Driver header file + * #include + * + * // Portable user-defined board-level symbols + * #include "Board.h" + * + * // GPIO button call back function + * void gpioButton0Fxn(uint_least8_t index); + * + * main() + * { + * // One-time TI-DRIVERS Board initialization + * Board_init(); + * + * // One-time init of GPIO driver + * GPIO_init(); + * + * // Turn on user LED + * GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); + * + * // install Button callback + * GPIO_setCallback(Board_GPIO_BUTTON0, gpioButton0Fxn); + * + * // Enable interrupts + * GPIO_enableInt(Board_GPIO_BUTTON0); + * } + * + * // + * // ======== gpioButton0Fxn ======== + * // Callback function for the GPIO interrupt on Board_GPIO_BUTTON0 + * // + * // Note: index is the GPIO id for the button which is not used here + * // + * void gpioButton0Fxn(uint_least8_t index) + * { + * // Toggle the LED + * GPIO_toggle(Board_GPIO_LED0); + * } + * @endcode + * + * @anchor ti_drivers_GPIO_Example_reconfigure + * **Runtime pin configuration**: The following example demonstrates how + * to (re)configure GPIO pins. + * @code + * // Driver header file + * #include + * + * // Portable board-level symbols + * #include "Board.h" + * + * #define LED Board_GPIO_LED0 + * #define BUTTON Board_GPIO_BUTTON0 + * + * void main() + * { + * // One-time init of GPIO driver + * GPIO_init(); + * + * // Configure a button input pin + * GPIO_setConfig(BUTTON, GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING); + * + * // Configure an LED output pin + * GPIO_setConfig(LED, GPIO_CFG_OUT_STD | GPIO_CFG_OUT_LOW); + * } + * @endcode + * + * ### GPIO Driver Configuration # + * + * In order to use the GPIO APIs, the application is required + * to provide 3 structures in the Board.c file: + * 1. An array of @ref GPIO_PinConfig elements that defines the + * initial configuration of each pin used by the application. A + * pin is referenced in the application by its corresponding index in this + * array. The pin type (that is, INPUT/OUTPUT), its initial state (that is + * OUTPUT_HIGH or LOW), interrupt behavior (RISING/FALLING edge, etc.), and + * device specific pin identification are configured in each element + * of this array (see @ref GPIO_PinConfigSettings). + * Below is an MSP432 device specific example of the GPIO_PinConfig array: + * @code + * // + * // Array of Pin configurations + * // NOTE: The order of the pin configurations must coincide with what was + * // defined in MSP_EXP432P401R.h + * // NOTE: Pins not used for interrupts should be placed at the end of the + * // array. Callback entries can be omitted from callbacks array to + * // reduce memory usage. + * // + * GPIO_PinConfig gpioPinConfigs[] = { + * // Input pins + * // MSP_EXP432P401R_GPIO_S1 + * GPIOMSP432_P1_1 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING, + * // MSP_EXP432P401R_GPIO_S2 + * GPIOMSP432_P1_4 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING, + * + * // Output pins + * // MSP_EXP432P401R_GPIO_LED1 + * GPIOMSP432_P1_0 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + * // MSP_EXP432P401R_GPIO_LED_RED + * GPIOMSP432_P2_0 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + * }; + * @endcode + * + * 2. An array of @ref GPIO_CallbackFxn elements that is used to store + * callback function pointers for GPIO pins configured with interrupts. + * The indexes for these array elements correspond to the pins defined + * in the GPIO_pinConfig array. These function pointers can be defined + * statically by referencing the callback function name in the array + * element, or dynamically, by setting the array element to NULL and using + * GPIO_setCallback() at runtime to plug the callback entry. + * Pins not used for interrupts can be omitted from the callback array to + * reduce memory usage (if they are placed at the end of GPIO_pinConfig + * array). The callback function syntax should match the following: + * @code + * void (*GPIO_CallbackFxn)(uint_least8_t index); + * @endcode + * The index parameter is the same index that was passed to + * GPIO_setCallback(). This allows the same callback function to be used + * for multiple GPIO interrupts, by using the index to identify the GPIO + * that caused the interrupt. + * Keep in mind that the callback functions will be called in the context of + * an interrupt service routine and should be designed accordingly. When an + * interrupt is triggered, the interrupt status of all (interrupt enabled) pins + * on a port will be read, cleared, and the respective callbacks will be + * executed. Callbacks will be called in order from least significant bit to + * most significant bit. + * Below is an MSP432 device specific example of the GPIO_CallbackFxn array: + * @code + * // + * // Array of callback function pointers + * // NOTE: The order of the pin configurations must coincide with what was + * // defined in MSP_EXP432P401R.h + * // NOTE: Pins not used for interrupts can be omitted from callbacks array + * // to reduce memory usage (if placed at end of gpioPinConfigs + * // array). + * // + * GPIO_CallbackFxn gpioCallbackFunctions[] = { + * // MSP_EXP432P401R_GPIO_S1 + * NULL, + * // MSP_EXP432P401R_GPIO_S2 + * NULL + * }; + * @endcode + * + * 3. A device specific GPIOxxx_Config structure that tells the GPIO + * driver where the two aforementioned arrays are and the number of elements + * in each. The interrupt priority of all pins configured to generate + * interrupts is also specified here. Values for the interrupt priority are + * device-specific. You should be well-acquainted with the interrupt + * controller used in your device before setting this parameter to a + * non-default value. The sentinel value of (~0) (the default value) is + * used to indicate that the lowest possible priority should be used. + * Below is an MSP432 device specific example of a GPIOxxx_Config + * structure: + * @code + * // + * // MSP432 specific GPIOxxx_Config structure + * // + * const GPIOMSP432_Config GPIOMSP432_config = { + * .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, + * .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, + * .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig), + * .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), + * .intPriority = (~0) + * }; + * @endcode + * + * ### Initializing the GPIO Driver # + * + * GPIO_init() must be called before any other GPIO APIs. This function + * configures each GPIO pin in the user-provided @ref GPIO_PinConfig + * array according to the defined settings. The user can also reconfigure + * a pin dynamically after GPIO_init() is called by using the + * GPIO_setConfig(), and GPIO_setCallback() APIs. + * + * # Implementation # + * + * Unlike most other TI-RTOS drivers, the GPIO driver has no generic function + * table with pointers to device-specific API implementations. All the generic + * GPIO APIs are implemented by the device-specific GPIO driver module. + * Additionally, there is no notion of an instance 'handle' with the GPIO + * driver. + * + * GPIO pins are referenced by their numeric index in the GPIO_PinConfig + * array. This design approach was used to enhance runtime and memory + * efficiency. + * + ****************************************************************************** + */ + +#ifndef ti_drivers_GPIO__include +#define ti_drivers_GPIO__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @name GPIO_STATUS_* macros are general status codes returned by GPIO driver APIs. + * @{ + */ + +/*! + * @brief Common GPIO status code reservation offset. + * + * GPIO driver implementations should offset status codes with + * GPIO_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define GPIOTXYZ_STATUS_ERROR1 GPIO_STATUS_RESERVED - 1 + * #define GPIOTXYZ_STATUS_ERROR0 GPIO_STATUS_RESERVED - 0 + * #define GPIOTXYZ_STATUS_ERROR2 GPIO_STATUS_RESERVED - 2 + * @endcode + */ +#define GPIO_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code returned by GPI_setConfig(). + * + * GPI_setConfig() returns GPIO_STATUS_SUCCESS if the API was executed + * successfully. + */ +#define GPIO_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by GPI_setConfig(). + * + * GPI_setConfig() returns GPIO_STATUS_ERROR if the API was not executed + * successfully. + */ +#define GPIO_STATUS_ERROR (-1) +/** @}*/ + +/*! + * @brief GPIO pin configuration settings + * + * The upper 16 bits of the 32 bit PinConfig is reserved + * for pin configuration settings. + * + * The lower 16 bits are reserved for device-specific + * port/pin identifications + */ +typedef uint32_t GPIO_PinConfig; + +/*! + * @cond NODOC + * Internally used configuration bit access macros. + */ +#define GPIO_CFG_IO_MASK 0x00ff0000 +#define GPIO_CFG_IO_LSB 16 +#define GPIO_CFG_OUT_TYPE_MASK 0x00060000 +#define GPIO_CFG_OUT_TYPE_LSB 17 +#define GPIO_CFG_IN_TYPE_MASK 0x00060000 +#define GPIO_CFG_IN_TYPE_LSB 17 +#define GPIO_CFG_OUT_STRENGTH_MASK 0x00f00000 +#define GPIO_CFG_OUT_STRENGTH_LSB 20 +#define GPIO_CFG_INT_MASK 0x07000000 +#define GPIO_CFG_INT_LSB 24 +#define GPIO_CFG_OUT_BIT 19 +/*! @endcond */ + +/*! + * \defgroup GPIO_PinConfigSettings Macros used to configure GPIO pins + * @{ + */ +/** @name GPIO_PinConfig output pin configuration macros + * @{ + */ +#define GPIO_CFG_OUTPUT (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an output. */ +#define GPIO_CFG_OUT_STD (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is actively driven high and low */ +#define GPIO_CFG_OUT_OD_NOPULL (((uint32_t) 2) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain */ +#define GPIO_CFG_OUT_OD_PU (((uint32_t) 4) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull up */ +#define GPIO_CFG_OUT_OD_PD (((uint32_t) 6) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull dn */ + +#define GPIO_CFG_OUT_STR_LOW (((uint32_t) 0) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strength to low */ +#define GPIO_CFG_OUT_STR_MED (((uint32_t) 1) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strength to medium */ +#define GPIO_CFG_OUT_STR_HIGH (((uint32_t) 2) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strength to high */ + +#define GPIO_CFG_OUT_HIGH (((uint32_t) 1) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 1. */ +#define GPIO_CFG_OUT_LOW (((uint32_t) 0) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 0. */ +/** @} */ + +/** @name GPIO_PinConfig input pin configuration macros + * @{ + */ +#define GPIO_CFG_INPUT (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an input. */ +#define GPIO_CFG_IN_NOPULL (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with no internal PU/PD */ +#define GPIO_CFG_IN_PU (((uint32_t) 3) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PU */ +#define GPIO_CFG_IN_PD (((uint32_t) 5) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PD */ +/** @} */ + +/** @name GPIO_PinConfig interrupt configuration macros + * @{ + */ +#define GPIO_CFG_IN_INT_NONE (((uint32_t) 0) << GPIO_CFG_INT_LSB) /*!< @hideinitializer No Interrupt */ +#define GPIO_CFG_IN_INT_FALLING (((uint32_t) 1) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on falling edge */ +#define GPIO_CFG_IN_INT_RISING (((uint32_t) 2) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on rising edge */ +#define GPIO_CFG_IN_INT_BOTH_EDGES (((uint32_t) 3) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on both edges */ +#define GPIO_CFG_IN_INT_LOW (((uint32_t) 4) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on low level */ +#define GPIO_CFG_IN_INT_HIGH (((uint32_t) 5) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on high level */ +/** @} */ + +/** @name Special GPIO_PinConfig configuration macros + * @{ + */ + +/*! + * @brief 'Or' in this @ref GPIO_PinConfig definition to inform GPIO_setConfig() + * to only configure the interrupt attributes of a GPIO input pin. + */ +#define GPIO_CFG_IN_INT_ONLY (((uint32_t) 1) << 27) /*!< @hideinitializer configure interrupt only */ + +/*! + * @brief Use this @ref GPIO_PinConfig definition to inform GPIO_init() + * NOT to configure the corresponding pin + */ +#define GPIO_DO_NOT_CONFIG 0x40000000 /*!< @hideinitializer Do not configure this Pin */ + +/** @} */ +/** @} end of GPIO_PinConfigSettings group */ + +/*! + * @brief GPIO callback function type + * + * @param index GPIO index. This is the same index that + * was passed to GPIO_setCallback(). This allows + * you to use the same callback function for multiple + * GPIO interrupts, by using the index to identify + * the GPIO that caused the interrupt. + */ +typedef void (*GPIO_CallbackFxn)(uint_least8_t index); + +/*! + * @brief Clear a GPIO pin interrupt flag + * + * Clears the GPIO interrupt for the specified index. + * + * Note: It is not necessary to call this API within a + * callback assigned to a pin. + * + * @param index GPIO index + */ +extern void GPIO_clearInt(uint_least8_t index); + +/*! + * @brief Disable a GPIO pin interrupt + * + * Disables interrupts for the specified GPIO index. + * + * @param index GPIO index + */ +extern void GPIO_disableInt(uint_least8_t index); + +/*! + * @brief Enable a GPIO pin interrupt + * + * Enables GPIO interrupts for the selected index to occur. + * + * Note: Prior to enabling a GPIO pin interrupt, make sure + * that a corresponding callback function has been provided. + * Use the GPIO_setCallback() API for this purpose at runtime. + * Alternatively, the callback function can be statically + * configured in the GPIO_CallbackFxn array provided. + * + * @param index GPIO index + */ +extern void GPIO_enableInt(uint_least8_t index); + +/*! + * @brief Get the current configuration for a gpio pin + * + * The pin configuration is provided in the static GPIO_PinConfig array, + * but can be changed with GPIO_setConfig(). GPIO_getConfig() gets the + * current pin configuration. + * + * @param index GPIO index + * @param pinConfig Location to store device specific pin + * configuration settings + */ +extern void GPIO_getConfig(uint_least8_t index, GPIO_PinConfig *pinConfig); + +/*! + * @brief Initializes the GPIO module + * + * The pins defined in the application-provided *GPIOXXX_config* structure + * are initialized accordingly. + * + * @pre The GPIO_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other GPIO driver APIs. + */ +extern void GPIO_init(); + +/*! + * @brief Reads the value of a GPIO pin + * + * The value returned will either be zero or one depending on the + * state of the pin. + * + * @param index GPIO index + * + * @return 0 or 1, depending on the state of the pin. + */ +extern uint_fast8_t GPIO_read(uint_least8_t index); + +/*! + * @brief Bind a callback function to a GPIO pin interrupt + * + * Associate a callback function with a particular GPIO pin interrupt. + * + * Callbacks can be changed at any time, making it easy to switch between + * efficient, state-specific interrupt handlers. + * + * Note: The callback function is called within the context of an interrupt + * handler. + * + * Note: This API does not enable the GPIO pin interrupt. + * Use GPIO_enableInt() and GPIO_disableInt() to enable + * and disable the pin interrupt as necessary. + * + * Note: it is not necessary to call GPIO_clearInt() within a callback. + * That operation is performed internally before the callback is invoked. + * + * @param index GPIO index + * @param callback address of the callback function + */ +extern void GPIO_setCallback(uint_least8_t index, GPIO_CallbackFxn callback); + +/*! + * @brief Configure the gpio pin + * + * Dynamically configure a gpio pin to a device specific setting. + * For many applications, the pin configurations provided in the static + * GPIO_PinConfig array is sufficient. + * + * For input pins with interrupt configurations, a corresponding interrupt + * object will be created as needed. + * + * @param index GPIO index + * @param pinConfig device specific pin configuration settings + */ +extern int_fast16_t GPIO_setConfig(uint_least8_t index, + GPIO_PinConfig pinConfig); + +/*! + * @brief Toggles the current state of a GPIO + * + * @param index GPIO index + */ +extern void GPIO_toggle(uint_least8_t index); + +/*! + * @brief Writes the value to a GPIO pin + * + * @param index GPIO index + * @param value must be either 0 or 1 + */ +extern void GPIO_write(uint_least8_t index, unsigned int value); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_GPIO__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2C.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2C.c new file mode 100644 index 0000000..f28b2ac --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2C.c @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== I2C.c ======== + */ + +#include +#include +#include + +#include +#include + +extern const I2C_Config I2C_config[]; +extern const uint_least8_t I2C_count; + +/* Default I2C parameters structure */ +const I2C_Params I2C_defaultParams = { + I2C_MODE_BLOCKING, /* transferMode */ + NULL, /* transferCallbackFxn */ + I2C_100kHz, /* bitRate */ + NULL /* custom */ +}; + +static bool isInitialized = false; + +/* + * ======== I2C_cancel ======== + */ +void I2C_cancel(I2C_Handle handle) +{ + handle->fxnTablePtr->cancelFxn(handle); +} + +/* + * ======== I2C_close ======== + */ +void I2C_close(I2C_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== I2C_control ======== + */ +int_fast16_t I2C_control(I2C_Handle handle, uint_fast16_t cmd, void *controlArg) +{ + return (handle->fxnTablePtr->controlFxn(handle, cmd, controlArg)); +} + +/* + * ======== I2C_init ======== + */ +void I2C_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + + key = HwiP_disable(); + + if (!isInitialized) { + isInitialized = (bool) true; + + /* Call each driver's init function */ + for (i = 0; i < I2C_count; i++) { + I2C_config[i].fxnTablePtr->initFxn((I2C_Handle)&(I2C_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== I2C_open ======== + */ +I2C_Handle I2C_open(uint_least8_t index, I2C_Params *params) +{ + I2C_Handle handle = NULL; + + if (isInitialized && (index < I2C_count)) { + /* If params are NULL use defaults. */ + if (params == NULL) { + params = (I2C_Params *) &I2C_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (I2C_Handle)&(I2C_config[index]); + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== I2C_Params_init ======= + */ +void I2C_Params_init(I2C_Params *params) +{ + *params = I2C_defaultParams; +} + +/* + * ======== I2C_transfer ======== + */ +bool I2C_transfer(I2C_Handle handle, I2C_Transaction *transaction) +{ + return (handle->fxnTablePtr->transferFxn(handle, transaction)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2C.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2C.h new file mode 100644 index 0000000..f5f6350 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2C.h @@ -0,0 +1,763 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file I2C.h + * @brief Inter-Integrated Circuit (I2C) Driver + * + * @anchor ti_drivers_I2C_Overview + * # Overview + * + * The I2C driver is designed to operate as an I2C master and will not + * function as an I2C slave. Multi-master arbitration is not supported; + * therefore, this driver assumes it is the only I2C master on the bus. + * This I2C driver's API set provides the ability to transmit and receive + * data over an I2C bus between the I2C master and I2C slave(s). The + * application is responsible for manipulating and interpreting the data. + * + * + *
+ * @anchor ti_drivers_I2C_Usage + * # Usage + * + * This section provides a basic @ref ti_drivers_I2C_Synopsis + * "usage summary" and a set of @ref ti_drivers_I2C_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * I2C APIs and their effect are provided in subsequent sections. + * + * @anchor ti_drivers_I2C_Synopsis + * ## Synopsis # + * @anchor ti_drivers_I2C_Synopsis_Code + * @code + * // Import I2C Driver definitions + * #include + * + * // Define name for an index of an I2C bus + * #define SENSORS 0 + * + * // Define the slave address of device on the SENSORS bus + * #define OPT_ADDR 0x47 + * + * // One-time init of I2C driver + * I2C_init(); + * + * // initialize optional I2C bus parameters + * I2C_Params params; + * I2C_Params_init(¶ms); + * params.bitRate = I2C_400kHz; + * + * // Open I2C bus for usage + * I2C_Handle i2cHandle = I2C_open(SENSORS, ¶ms); + * + * // Initialize slave address of transaction + * I2C_Transaction transaction = {0}; + * transaction.slaveAddress = OPT_ADDR; + * + * // Read from I2C slave device + * transaction.readBuf = data; + * transaction.readCount = sizeof(data); + * transaction.writeCount = 0; + * I2C_transfer(i2cHandle, &transaction); + * + * // Write to I2C slave device + * transaction.writeBuf = command; + * transaction.writeCount = sizeof(command); + * transaction.readCount = 0; + * I2C_transfer(i2cHandle, &transaction); + * + * // Close I2C + * I2C_close(i2cHandle); + * @endcode + * + * @anchor ti_drivers_I2C_Examples + * ## Examples + * + * @li @ref ti_drivers_I2C_Example_open "Getting an I2C bus handle" + * @li @ref ti_drivers_I2C_Example_write3bytes "Sending 3 bytes" + * @li @ref ti_drivers_I2C_Example_read5bytes "Reading 5 bytes" + * @li @ref ti_drivers_I2C_Example_writeread "Writing then reading in a single transaction" + * @li @ref ti_drivers_I2C_Example_callback "Using Callback mode" + * + * @anchor ti_drivers_I2C_Example_open + * ## Opening the I2C Driver + * + * After calling I2C_init(), the application can open an I2C instance by + * calling I2C_open().The following code example opens an I2C instance with + * default parameters by passing @p NULL for the #I2C_Params argument. + * + * @code + * I2C_Handle i2cHandle; + * + * i2cHandle = I2C_open(0, NULL); + * + * if (i2cHandle == NULL) { + * // Error opening I2C + * while (1) {} + * } + * @endcode + * + * @anchor ti_drivers_I2C_Example_write3bytes + * ## Sending three bytes of data. + * + * @code + * I2C_Transaction i2cTransaction = {0}; + * uint8_t writeBuffer[3]; + * + * writeBuffer[0] = 0xAB; + * writeBuffer[1] = 0xCD; + * writeBuffer[2] = 0xEF; + * + * i2cTransaction.slaveAddress = 0x50; + * i2cTransaction.writeBuf = writeBuffer; + * i2cTransaction.writeCount = 3; + * i2cTransaction.readBuf = NULL; + * i2cTransaction.readCount = 0; + * + * status = I2C_transfer(i2cHandle, &i2cTransaction); + * + * if (status == false) { + * // Unsuccessful I2C transfer + * } + * @endcode + * + * @anchor ti_drivers_I2C_Example_read5bytes + * ## Reading five bytes of data. + * + * @code + * I2C_Transaction i2cTransaction = {0}; + * uint8_t readBuffer[5]; + * + * i2cTransaction.slaveAddress = 0x50; + * i2cTransaction.writeBuf = NULL; + * i2cTransaction.writeCount = 0; + * i2cTransaction.readBuf = readBuffer; + * i2cTransaction.readCount = 5; + * + * status = I2C_transfer(i2cHandle, &i2cTransaction); + * + * if (status == false) { + * // Unsuccessful I2C transfer + * } + * @endcode + * + * @anchor ti_drivers_I2C_Example_writeread + * ## Writing two bytes and reading four bytes in a single transaction. + * + * @code + * I2C_Transaction i2cTransaction = {0}; + * uint8_t readBuffer[4]; + * uint8_t writeBuffer[2]; + * + * writeBuffer[0] = 0xAB; + * writeBuffer[1] = 0xCD; + * + * i2cTransaction.slaveAddress = 0x50; + * i2cTransaction.writeBuf = writeBuffer; + * i2cTransaction.writeCount = 2; + * i2cTransaction.readBuf = readBuffer; + * i2cTransaction.readCount = 4; + * + * status = I2C_transfer(i2cHandle, &i2cTransaction); + * + * if (status == false) { + * // Unsuccessful I2C transfer + * } + * @endcode + * + * @anchor ti_drivers_I2C_Example_callback + * ## Using callback mode + * This final example shows usage of #I2C_MODE_CALLBACK, with queuing + * of multiple transactions. Because multiple transactions are simultaneously + * queued, separate #I2C_Transaction structures must be used. Each + * #I2C_Transaction will contain a custom application argument of a + * semaphore handle. The #I2C_Transaction.arg will point to the semaphore + * handle. When the callback function is called, the #I2C_Transaction.arg is + * checked for @p NULL. If this value is not @p NULL, then it can be assumed + * the @p arg is pointing to a valid semaphore handle. The semaphore handle + * is then used to call @p sem_post(). Hypothetically, this can be used to + * signal transaction completion to the task(s) that queued the + * transaction(s). + * + * @code + * void callbackFxn(I2C_Handle handle, I2C_Transaction *msg, bool status) + * { + * + * if (status == false) { + * //transaction failed + * } + * + * // Check for a semaphore handle + * if (msg->arg != NULL) { + * + * // Perform a semaphore post + * sem_post((sem_t *) (msg->arg)); + * } + * } + * @endcode + * + * Snippets of the thread code that initiates the transactions are shown below. + * Note the use of multiple #I2C_Transaction structures. The handle of the + * semaphore to be posted is specified via @p i2cTransaction2.arg. + * I2C_transfer() is called three times to initiate each transaction. + * Since callback mode is used, these functions return immediately. After + * the transactions have been queued, other work can be done. Eventually, + * @p sem_wait() is called causing the thread to block until the transaction + * completes. When the transaction completes, the application's callback + * function, @p callbackFxn will be called. Once #I2C_CallbackFxn posts the + * semaphore, the thread will be unblocked and can resume execution. + * + * @code + * void thread(arg0, arg1) + * { + * + * I2C_Transaction i2cTransaction0 = {0}; + * I2C_Transaction i2cTransaction1 = {0}; + * I2C_Transaction i2cTransaction2 = {0}; + * + * // ... + * + * i2cTransaction0.arg = NULL; + * i2cTransaction1.arg = NULL; + * i2cTransaction2.arg = semaphoreHandle; + * + * // ... + * + * I2C_transfer(i2c, &i2cTransaction0); + * I2C_transfer(i2c, &i2cTransaction1); + * I2C_transfer(i2c, &i2cTransaction2); + * + * // ... + * + * sem_wait(semaphoreHandle); + * } + * @endcode + * + *
+ * @anchor ti_drivers_I2C_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_I2C__include +#define ti_drivers_I2C__include + +/*! @cond */ +#include +#include +#include +/*! @endcond */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup I2C_CONTROL I2C_control command and status codes + * These I2C macros are reservations for I2C.h + * @{ + */ + +/*! @cond */ +/*! + * @private + * Common I2C_control command code reservation offset. + * I2C driver implementations should offset command codes with + * #I2C_CMD_RESERVED growing positively + * + * Example implementation specific command codes: + * @code + * #define I2CXYZ_CMD_COMMAND0 I2C_CMD_RESERVED + 0 + * #define I2CXYZ_CMD_COMMAND1 I2C_CMD_RESERVED + 1 + * @endcode + */ +#define I2C_CMD_RESERVED (32) + +/*! + * @private + * Common I2C_control status code reservation offset. + * I2C driver implementations should offset status codes with + * #I2C_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define I2CXYZ_STATUS_ERROR0 I2C_STATUS_RESERVED - 0 + * #define I2CXYZ_STATUS_ERROR1 I2C_STATUS_RESERVED - 1 + * #define I2CXYZ_STATUS_ERROR2 I2C_STATUS_RESERVED - 2 + * @endcode + */ +#define I2C_STATUS_RESERVED (-32) +/*! @endcond */ + +/** + * @defgroup I2C_STATUS Status Codes + * I2C_STATUS_* macros are general status codes returned by I2C_control() + * @{ + * @ingroup I2C_CONTROL + */ + +/*! + * @brief Successful status code returned by I2C_control(). + * + * I2C_control() returns #I2C_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define I2C_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by I2C_control(). + * + * I2C_control() returns #I2C_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define I2C_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by I2C_control() for undefined + * command codes. + * + * I2C_control() returns #I2C_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define I2C_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup I2C_CMD Command Codes + * I2C_CMD_* macros are general command codes for I2C_control(). Not all I2C + * driver implementations support these command codes. + * @{ + * @ingroup I2C_CONTROL + */ + +/* Add I2C_CMD_ here */ + +/** @} end I2C commands */ + +/** @} end I2C_CONTROL group */ + +/*! + * @brief A handle that is returned from an I2C_open() call. + */ +typedef struct I2C_Config_ *I2C_Handle; + +/*! + * @brief Defines a transaction to be used with I2C_transfer() + * + * @sa I2C_transfer() + */ +typedef struct { + /*! + * Pointer to a buffer of at least #I2C_Transaction.writeCount bytes. + * If #I2C_Transaction.writeCount is 0, this pointer is not used. + */ + void *writeBuf; + + /*! + * Number of bytes to write to the I2C slave device. A value of 0 + * indicates no data will be written to the slave device and only a read + * will occur. If this value + * is not 0, the driver will always perform the write transfer first. + * The data written to the I2C bus is preceded by the + * #I2C_Transaction.slaveAddress with the write bit set. If + * @p writeCount bytes are successfully sent and + * acknowledged, the transfer will complete or perform a read--depending + * on #I2C_Transaction.readCount. + * + * @note Both #I2C_Transaction.writeCount and #I2C_Transaction.readCount + * can not be 0. + */ + size_t writeCount; + + /*! + * Pointer to a buffer of at least #I2C_Transaction.readCount bytes. + * If #I2C_Transaction.readCount is 0, this pointer is not used. + */ + void *readBuf; + + /*! + * Number of bytes to read from the I2C slave device. A value of 0 + * indicates no data will be read and only a write will occur. If + * #I2C_Transaction.writeCount is not 0, this driver will perform the + * write first, followed by the read. The data read from the bus is + * preceded by the #I2C_Transaction.slaveAddress with the read bit set. + * After @p readCount bytes are successfully read, the transfer will + * complete. + * + * @note Both #I2C_Transaction.writeCount and #I2C_Transaction.readCount + * can not be 0. + */ + size_t readCount; + + /*! + * I2C slave address used for the transaction. The slave address is + * the first byte transmitted during an I2C transfer. The read/write bit + * is automatically set based upon the #I2C_Transaction.writeCount and + * #I2C_Transaction.readCount. + */ + uint_least8_t slaveAddress; + + /*! + * Pointer to a custom argument to be passed to the #I2C_CallbackFxn + * function via the #I2C_Transaction structure. + * + * @note The #I2C_CallbackFxn function is only called when operating in + * #I2C_MODE_CALLBACK. + * + * @sa #I2C_MODE_CALLBACK + * @sa #I2C_CallbackFxn + */ + void *arg; + + /*! + * @private This is reserved for use by the driver and must never be + * modified by the application. + */ + void *nextPtr; +} I2C_Transaction; + +/*! + * @brief Return behavior of I2C_Transfer() specified in the #I2C_Params. + * + * This enumeration defines the return behaviors for a call to I2C_transfer(). + * + * @sa #I2C_Params + */ +typedef enum { + /*! + * In #I2C_MODE_BLOCKING, calls to I2C_transfer() block until the + * #I2C_Transaction completes. Other threads calling I2C_transfer() + * while a transaction is in progress are also placed into a blocked + * state. If multiple threads are blocked, the thread with the highest + * priority will be unblocked first. This implies that arbitration + * will not be executed in chronological order. + * + * @note When using #I2C_MODE_BLOCKING, I2C_transfer() must be called + * from a thread context. + */ + I2C_MODE_BLOCKING, + + /*! + * In #I2C_MODE_CALLBACK, calls to I2C_transfer() return immediately. The + * application's callback function, #I2C_Params.transferCallbackFxn, is + * called when the transaction is complete. Sequential calls to + * I2C_transfer() will place #I2C_Transaction structures into an + * internal queue. Queued transactions are automatically started after the + * previous transaction has completed. This queuing occurs regardless of + * any error state from previous transactions. The transactions are + * always executed in chronological order. The + * #I2C_Params.transferCallbackFxn function will be called asynchronously + * as each transaction is completed. + */ + I2C_MODE_CALLBACK +} I2C_TransferMode; + +/*! + * @brief The definition of a callback function. + * + * When operating in #I2C_MODE_CALLBACK, the callback function is called + * when an I2C_transfer() completes. The application is responsible for + * declaring an #I2C_CallbackFxn function and providing a pointer + * in #I2C_Params.transferCallbackFxn. + * + * @warning The callback function is called from an interrupt context. + * + * @param[out] handle #I2C_Handle used with the initial call to + * I2C_transfer() + * + * @param[out] transaction Pointer to the #I2C_Transaction structure used + * with the initial call to I2C_transfer(). This structure also contains the + * custom argument specified by @p transaction.arg. + * + * @param[out] transferStatus Boolean indicating if the I2C transaction + * was successful. If @p true, the transaction was successful. If @p false, + * the transaction failed. + */ +typedef void (*I2C_CallbackFxn)(I2C_Handle handle, I2C_Transaction *transaction, + bool transferStatus); + +/*! + * @brief Bit rate for an I2C driver instance specified in the #I2C_Params. + * + * This enumeration defines the bit rates used with an I2C_transfer(). + * + * @note You must check that the device specific implementation supports the + * desired #I2C_BitRate. + */ +typedef enum { + I2C_100kHz = 0, /*!< I2C Standard-mode. Up to 100 kbit/s. */ + I2C_400kHz = 1, /*!< I2C Fast-mode. Up to 400 kbit/s. */ + I2C_1000kHz = 2, /*!< I2C Fast-mode Plus. Up to 1Mbit/s. */ + I2C_3330kHz = 3, /*!< I2C High-speed mode. Up to 3.4Mbit/s. */ + I2C_3400kHz = 3, /*!< I2C High-speed mode. Up to 3.4Mbit/s. */ +} I2C_BitRate; + +/*! + * @brief I2C parameters used with I2C_open(). + * + * I2C_Params_init() must be called prior to setting fields in + * this structure. + * + * @sa I2C_Params_init() + */ +typedef struct { + /*! #I2C_TransferMode for all I2C transfers. */ + I2C_TransferMode transferMode; + + /*! + * Pointer to a #I2C_CallbackFxn to be invoked after a + * I2C_transfer() completes when operating in #I2C_MODE_CALLBACK. + */ + I2C_CallbackFxn transferCallbackFxn; + + /*! + * A #I2C_BitRate specifying the frequency at which the I2C peripheral + * will transmit data during a I2C_transfer(). + */ + I2C_BitRate bitRate; + + /*! Pointer to a device specific extension of the #I2C_Params */ + void *custom; +} I2C_Params; + +/*! + * @private + * @brief A function pointer to a driver-specific implementation of + * I2C_cancel(). + */ +typedef void (*I2C_CancelFxn) (I2C_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver-specific implementation of + * I2C_close(). + */ +typedef void (*I2C_CloseFxn) (I2C_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver-specific implementation of + * I2C_control(). + */ +typedef int_fast16_t (*I2C_ControlFxn) (I2C_Handle handle, uint_fast16_t cmd, + void *controlArg); + +/*! + * @private + * @brief A function pointer to a driver-specific implementation of + * I2C_init(). + */ +typedef void (*I2C_InitFxn) (I2C_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver-specific implementation of + * I2C_open(). + */ +typedef I2C_Handle (*I2C_OpenFxn) (I2C_Handle handle, I2C_Params *params); + +/*! + * @private + * @brief A function pointer to a driver-specific implementation of + * I2C_transfer(). + */ +typedef bool (*I2C_TransferFxn) (I2C_Handle handle, + I2C_Transaction *transaction); + +/*! + * @brief The definition of an I2C function table that contains the + * required set of functions to control a specific I2C driver + * implementation. + */ +typedef struct I2C_FxnTable_ { + I2C_CancelFxn cancelFxn; + I2C_CloseFxn closeFxn; + I2C_ControlFxn controlFxn; + I2C_InitFxn initFxn; + I2C_OpenFxn openFxn; + I2C_TransferFxn transferFxn; +} I2C_FxnTable; + +/*! + * @brief I2C driver's custom @ref driver_configuration "configuration" + * structure. + * + * @sa I2C_init() + * @sa I2C_open() + */ +typedef struct I2C_Config_ { + /*! Pointer to a @ref driver_function_table "function pointer table" + * with driver-specific implementations of I2C APIs */ + I2C_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific @ref driver_objects "data object". */ + void *object; + + /*! Pointer to a driver specific @ref driver_hardware_attributes + * "hardware attributes structure". */ + void const *hwAttrs; +} I2C_Config; + +/*! + * @brief Cancels all I2C transfers + * + * This function will cancel asynchronous I2C_transfer() operations, and is + * applicable only for #I2C_MODE_CALLBACK mode. The in progress transfer, as + * well as any queued transfers, will be canceled. The individual callback + * functions for each transfer will be called in chronological order. The + * callback functions are called in the same context as the I2C_cancel(). + * + * @pre I2C_Transfer() has been called. + * + * @param[in] handle An #I2C_Handle returned from I2C_open() + * + * @note Different I2C slave devices will behave differently when an + * in-progress transfer fails and needs to be canceled. The slave + * may need to be reset, or there may be other slave-specific + * steps that can be used to successfully resume communication. + * + * @sa I2C_transfer() + * @sa #I2C_MODE_CALLBACK + */ +extern void I2C_cancel(I2C_Handle handle); + +/*! + * @brief Function to close an I2C driver instance + * + * @pre I2C_open() has been called. + * + * @param[in] handle An #I2C_Handle returned from I2C_open() + */ +extern void I2C_close(I2C_Handle handle); + +/*! + * @brief Function performs implementation specific features on a + * driver instance. + * + * @pre I2C_open() has to be called first. + * + * @param[in] handle An #I2C_Handle returned from I2C_open() + * + * @param[in] cmd A command value defined by the device specific + * implementation + * + * @param[in] controlArg An optional R/W (read/write) argument that is + * accompanied with @p cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @retval #I2C_STATUS_SUCCESS The call was successful. + * @retval #I2C_STATUS_UNDEFINEDCMD The @p cmd value is not supported by + * the device specific implementation. + */ +extern int_fast16_t I2C_control(I2C_Handle handle, uint_fast16_t cmd, + void *controlArg); + +/*! + * @brief Function to initialize the I2C driver. + * + * This function must also be called before any otherI2C driver APIs. + */ +extern void I2C_init(void); + +/*! + * @brief Open an I2C driver instance. + * + * @pre I2C_init() has been called. + * + * @param[in] index Index in the @p I2C_Config[] array. + * + * @param[in] params Pointer to an initialized #I2C_Params structure. + * If NULL, the default #I2C_Params values are used. + * + * @return An #I2C_Handle on success, or @p NULL on an error. + * + * @sa I2C_init() + * @sa I2C_close() + */ +extern I2C_Handle I2C_open(uint_least8_t index, I2C_Params *params); + +/*! + * @brief Initialize an #I2C_Params structure to its default values. + * + * @param[in] params A pointer to #I2C_Params structure for + * initialization. + * + * Defaults values are: + * @arg #I2C_Params.transferMode = #I2C_MODE_BLOCKING + * @arg #I2C_Params.transferCallbackFxn = @p NULL + * @arg #I2C_Params.bitRate = #I2C_100kHz + * @arg #I2C_Params.custom = @p NULL + */ +extern void I2C_Params_init(I2C_Params *params); + +/*! + * @brief Perform an I2C transaction with an I2C slave peripheral. + * + * This function will perform an I2C transfer, as specified by an + * #I2C_Transaction structure. + * + * @note When using #I2C_MODE_BLOCKING, this must be called from a thread + * context. + * + * @param[in] handle An #I2C_Handle returned from I2C_open() + * + * @param[in] transaction A pointer to an #I2C_Transaction. The application + * is responsible for allocating and initializing an #I2C_Transaction + * structure prior to passing it to I2C_Transfer(). This + * structure must persist in memory unmodified until the transfer is complete. + * + * @note #I2C_Transaction structures cannot be re-used until the previous + * transaction has completed. + * + * @return In #I2C_MODE_BLOCKING: @p true for a successful transfer; @p false + * for an error (for example, an I2C bus fault (NACK)). + * + * @return In #I2C_MODE_CALLBACK: always @p true. The #I2C_CallbackFxn @p bool + * argument will be @p true to indicate success, and @p false to + * indicate an error. + * + * @pre I2C_open() has been called. + * + * @sa I2C_open() + * @sa I2C_Transaction + */ +extern bool I2C_transfer(I2C_Handle handle, I2C_Transaction *transaction); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_I2C__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2S.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2S.c new file mode 100644 index 0000000..735585c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2S.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== I2S.c ======== + */ + +#include + +extern const I2S_Config I2S_config[]; +extern const uint_least8_t I2S_count; + +/* Default I2S parameters structure */ +const I2S_Params I2S_defaultParams = { + .samplingFrequency = 8000, /* Sampling Freq */ + .memorySlotLength = I2S_MEMORY_LENGTH_16BITS, /* Memory slot length */ + .moduleRole = I2S_MASTER, /* Master / Slave selection */ + .invertWS = (bool)true, /* WS inversion */ + .isMSBFirst = (bool)true, /* Endianness selection*/ + .isDMAUnused = (bool)false, /* Selection between DMA and CPU transmissions*/ + .samplingEdge = I2S_SAMPLING_EDGE_RISING, /* Sampling edge*/ + .beforeWordPadding = 0, /* Before sample padding */ + .bitsPerWord = 16, /* Bits/Sample */ + .afterWordPadding = 0, /* After sample padding */ + .fixedBufferLength = 1, /* Fixed Buffer Length */ + .SD0Use = I2S_SD0_OUTPUT, /* SD0Use */ + .SD1Use = I2S_SD1_INPUT, /* SD1Use */ + .SD0Channels = I2S_CHANNELS_STEREO, /* Channels activated on SD0 */ + .SD1Channels = I2S_CHANNELS_STEREO, /* Channels activated on SD1 */ + .phaseType = I2S_PHASE_TYPE_DUAL, /* Phase type */ + .startUpDelay = 0, /* Start up delay */ + .MCLKDivider = 40, /* MCLK divider */ + .readCallback = NULL, /* Read callback */ + .writeCallback = NULL, /* Write callback */ + .errorCallback = NULL, /* Error callback */ + .custom = NULL, /* customParams */ +}; + +/* + * ======== I2S_Params_init ======== + */ +void I2S_Params_init(I2S_Params *params) +{ + *params = I2S_defaultParams; +} + +/* + * ======== I2S_Transaction_init ======== + */ +void I2S_Transaction_init(I2S_Transaction *transaction) +{ + transaction->bufPtr = NULL; + transaction->bufSize = 0; + transaction->bytesTransferred = 0; + transaction->untransferredBytes = 0; + transaction->numberOfCompletions = 0; + transaction->arg = (uintptr_t)NULL; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2S.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2S.h new file mode 100644 index 0000000..690a952 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2S.h @@ -0,0 +1,1188 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file I2S.h + * @brief Inter-Integrated Circuit Sound (I2S) Bus Driver + * + * The I2S header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * @anchor ti_drivers_I2S_Overview + * # Overview # + * + * The I2S driver facilitates the use of Inter-IC Sound (I2S), which is + * used to connect digital audio devices so that audio signals can be + * communicated between devices. The I2S driver simplifies reading and + * writing to any of the Multichannel Audio Serial Port (McASP) peripherals + * on the board with Receive and Transmit support. These include read and + * write characters on the McASP peripheral. + * + * I2S interfaces typically consist of 4 or 5 signals. The 5th signal is not + * systematically used. + * @li Serial Clock (SCK) also called Bit Clock (BCLK) or Multichannel + * Audio Frame Synchronization (McAFSX) + * @li Word Select (WS) also called Word Clock (WCLK), Left Right + * Clock (LRCLK) or Multichannel Audio Clock (McACLK) + * @li Serial Data (SD0) also called AD0, AD1, McAXR0, or possibly SDI + * @li Serial Data (SD1) also called AD1, ADI, McAXR1, or possibly SDI + * @li Master Clock (MCLK) + * + *
+ * @anchor ti_drivers_I2S_Usage + * # Usage # + * + * The I2S driver provides the following APIs: + * @li I2S_init(): @copybrief I2S_init + * @li I2S_open(): @copybrief I2S_open + * @li I2S_Params_init(): @copybrief I2S_Params_init + * @li I2S_Transaction_init(): @copybrief I2S_Transaction_init + * @li I2S_setReadQueueHead(): @copybrief I2S_setReadQueueHead + * @li I2S_startClocks(): @copybrief I2S_startClocks + * @li I2S_startRead(): @copybrief I2S_startRead + * @li I2S_stopRead(): @copybrief I2S_stopRead + * @li I2S_stopClocks(): @copybrief I2S_stopClocks + * @li I2S_close(): @copybrief I2S_close + * + *
+ * @anchor ti_drivers_I2S_Driver_Transactions + * ### Transactions # + * + * Data transfers are achieved through #I2S_Transaction structures. Application is + * responsible to maintain the transactions queues. The I2S driver completes the + * transactions one by one. When a transaction is over, the I2S driver takes in + * consideration the next transaction (if the next transaction is NULL, the I2S + * drivers signals this to the user). + * The I2S driver relies on the following fields of the #I2S_Transaction to + * complete it: + * - the buffer + * - the length of the buffer + * - a pointer on the next transaction to achieve (kept in a List_Elem structure) + * . + * The I2S driver provides the following elements (fields of the #I2S_Transaction): + * - the number of untransferred bytes: the driver is designed to avoid memory corruption and will + * not complete an incomplete transaction (meaning a transaction where the buffer size would not + * permit to send or receive a whole number of samples). In this case, the system considers the + * samples of the beginning of the buffer and read/write as much as possible samples and ignore the + * end of the buffer. The number of untransafered bytes is the number of bytes left at the end of + * the buffer) + * - the number of completions of the transaction. This value is basically incremented by one + * every time the transaction is completed. + * . + * Please note that these two fields are valid only when the transaction has been completed. + * Consult examples to get more details on the transaction usage. + * + *
+ * @anchor ti_drivers_I2S_Driver_ProvidingData + * ### Providing data to the I2S driver # + * Application is responsible to handle the queues of transactions. + * Application is also responsible to provide to the driver a pointer on + * the first transaction to consider (considering that all the following + * transactions are correctly queued). + * #I2S_setReadQueueHead() and #I2S_setWriteQueueHead() allow the user to + * set the first transaction to consider. These functions should be used only + * when no transaction is running on the considered interface. + * + *
+ * @anchor ti_drivers_I2S_Driver_StartStopClocks + * ### Start and stop clocks and transactions # + * Clocks can be started and stopped by the application. + * Read and write can be started and stopped independently. + * To start a transfer, clocks must be running. + * To stop the clocks no transfer must be running. + * Refer to the following functions for more details: + * @li I2S_startClocks() @li I2S_startRead() @li I2S_startWrite() + * @li I2S_stopRead() @li I2S_stopWrite() @li I2S_stopClocks() + * + * @note + * @li In #I2S_SLAVE mode, clocks must be started and stopped exactly like + * it is done in #I2S_MASTER mode. + * @li If the queue of transaction is not empty, the calls to #I2S_stopRead() + * and #I2S_stopWrite() are blocking and potentially long. + * + *
+ * @anchor ti_drivers_I2S_Examples + * ## Examples # + * + * @li @ref ti_drivers_I2S_Example_PlayAndStop "Play and Stop" + * @li @ref ti_drivers_I2S_Example_Streaming "Streaming" + * @li @ref ti_drivers_I2S_Example_RepeatMode "Repeat" + * + *
+ * @anchor ti_drivers_I2S_Example_PlayAndStop + * ### Mode Play and Stop # + * The following example shows how to simultaneously receive and send out a given amount of data. + * + *
+ * @anchor ti_drivers_I2S_Example_PlayAndStop_Code + * @code + * static I2S_Handle i2sHandle; + * static I2S_Config i2sConfig; + * + * static uint16_t readBuf1[500]; // the data read will end up in this buffer + * static uint16_t readBuf2[500]; // the data read will end up in this buffer + * static uint16_t readBuf3[500]; // the data read will end up in this buffer + * static uint16_t writeBuf1[250] = {...some data...}; // this buffer will be sent out + * static uint16_t writeBuf2[250] = {...some data...}; // this buffer will be sent out + * static uint16_t writeBuf3[250] = {...some data...}; // this buffer will be sent out + * + * static I2S_Transaction i2sRead1; + * static I2S_Transaction i2sRead2; + * static I2S_Transaction i2sRead3; + * static I2S_Transaction i2sWrite1; + * static I2S_Transaction i2sWrite2; + * static I2S_Transaction i2sWrite3; + * + * List_List i2sReadList; + * List_List i2sWriteList; + * + * static volatile bool readStopped = (bool)true; + * static volatile bool writeStopped = (bool)true; + * + * static void writeCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * if(status & I2S_ALL_TRANSACTIONS_SUCCESS){ + * + * //Note: You should normally avoid to use I2S_stopRead() / I2S_stopWrite() in the callback. + * //However, here we do not have any transaction left in the queue (cf. status' value) so + * //the call to I2S_stoWrite() will not block. + * //Moreover, by delaying I2S_stopWrite() the driver could raise an error (data underflow). + * + * I2S_stopWrite(i2sHandle); + * writeStopped = (bool)true; + * } + * } + * + * static void readCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * if(status & I2S_ALL_TRANSACTIONS_SUCCESS){ + * + * //Note: You should normally avoid to use I2S_stopRead() / I2S_stopWrite() in the callback. + * //However, here we do not have any transaction left in the queue (cf. status' value) so + * //the call to I2S_stopRead() will not block. + * //Moreover, by delaying I2S_stopRead() the driver could raise an error (data overflow). + * + * I2S_stopRead(i2sHandle); + * readStopped = (bool)true; + * } + * } + * + * static void errCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * I2S_stopRead(handle); + * I2S_stopWrite(handle); + * I2S_stopClocks(handle); + * I2S_close(handle); + * } + * + * void *modePlayAndStopThread(void *arg0) + * { + * I2S_Params i2sParams; + * + * I2S_init(); + * + * // Initialize I2S opening parameters + * I2S_Params_init(&i2sParams); + * i2sParams.fixedBufferLength = 500; // fixedBufferLength is the greatest common + * // divisor of all the different buffers + * // (here buffers' size are 500 and 1000 bytes) + * i2sParams.writeCallback = writeCallbackFxn ; + * i2sParams.readCallback = readCallbackFxn ; + * i2sParams.errorCallback = errCallbackFxn; + * + * i2sHandle = I2S_open(Board_I2S0, &i2sParams); + * + * // Initialize the read-transactions + * I2S_Transaction_init(&i2sRead1); + * I2S_Transaction_init(&i2sRead2); + * I2S_Transaction_init(&i2sRead3); + * i2sRead1.bufPtr = readBuf1; + * i2sRead2.bufPtr = readBuf2; + * i2sRead3.bufPtr = readBuf3; + * i2sRead1.bufSize = sizeof(readBuf1); + * i2sRead2.bufSize = sizeof(readBuf2); + * i2sRead3.bufSize = sizeof(readBuf3); + * List_put(&i2sReadList, (List_Elem*)&i2sRead1); + * List_put(&i2sReadList, (List_Elem*)&i2sRead2); + * List_put(&i2sReadList, (List_Elem*)&i2sRead3); + * + * I2S_setReadQueueHead(i2sHandle, &i2sRead1); + * + * // Initialize the write-transactions + * I2S_Transaction_init(&i2sWrite1); + * I2S_Transaction_init(&i2sWrite2); + * I2S_Transaction_init(&i2sWrite3); + * i2sWrite1.bufPtr = writeBuf1; + * i2sWrite2.bufPtr = writeBuf2; + * i2sWrite3.bufPtr = writeBuf3; + * i2sWrite1.bufSize = sizeof(writeBuf1); + * i2sWrite2.bufSize = sizeof(writeBuf2); + * i2sWrite3.bufSize = sizeof(writeBuf3); + * List_put(&i2sWriteList, (List_Elem*)&i2sWrite1); + * List_put(&i2sWriteList, (List_Elem*)&i2sWrite2); + * List_put(&i2sWriteList, (List_Elem*)&i2sWrite3); + * + * I2S_setWriteQueueHead(i2sHandle, &i2sWrite1); + * + * I2S_startClocks(i2sHandle); + * I2S_startWrite(i2sHandle); + * I2S_startRead(i2sHandle); + * + * readStopped = (bool)false; + * writeStopped = (bool)false; + * + * while(1) { + * + * if(readStopped && writeStopped) { + * I2S_stopClocks(i2sHandle); + * I2S_close(i2sHandle); + * while(1); + * } + * } + * } + * @endcode + * + * \note If you desire to put only one transaction in the queue, fixedBufferLength must be inferior to half the length (in bytes) of the buffer to transfer. + * + *
+ * @anchor ti_drivers_I2S_Example_Streaming + * ### Writing Data in Continuous Streaming Mode # + * The following example shows how to read and write data in streaming mode. + * A dummy treatment of the data is also done. + * This example is not complete (semaphore and tasks creation are not shown) + * + *
+ * @anchor ti_drivers_I2S_Example_Streaming_Code + * @code + * static I2S_Handle i2sHandle; + * static I2S_Config i2sConfig; + * + * // These buffers will successively be written, treated and sent out + * static uint16_t readBuf1[500]; + * static uint16_t readBuf2[500]; + * static uint16_t readBuf3[500]; + * static uint16_t readBuf4[500]; + * static uint16_t writeBuf1[500]={0}; + * static uint16_t writeBuf2[500]={0}; + * static uint16_t writeBuf3[500]={0}; + * static uint16_t writeBuf4[500]={0}; + * + * // These transactions will successively be part of the + * // i2sReadList, the treatmentList and the i2sWriteList + * static I2S_Transaction i2sRead1; + * static I2S_Transaction i2sRead2; + * static I2S_Transaction i2sRead3; + * static I2S_Transaction i2sRead4; + * static I2S_Transaction i2sWrite1; + * static I2S_Transaction i2sWrite2; + * static I2S_Transaction i2sWrite3; + * static I2S_Transaction i2sWrite4; + * + * List_List i2sReadList; + * List_List treatmentList; + * List_List i2sWriteList; + * + * static void writeCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * // We must remove the previous transaction (the current one is not over) + * I2S_Transaction *transactionFinished = (I2S_Transaction*)List_prev(&transactionPtr->queueElement); + * + * if(transactionFinished != NULL){ + * // Remove the finished transaction from the write queue + * List_remove(&i2sWriteList, (List_Elem*)transactionFinished); + * + * // This transaction must now feed the read queue (we do not need anymore the data of this transaction) + * transactionFinished->queueElement.next = NULL; + * List_put(&i2sReadList, (List_Elem*)transactionFinished); + * + * // We need to queue a new transaction: let's take one in the treatment queue + * I2S_Transaction *newTransaction = (I2S_Transaction*)List_head(&treatmentList); + * if(newTransaction != NULL){ + * List_remove(&treatmentList, (List_Elem*)newTransaction); + * newTransaction->queueElement.next = NULL; + * List_put(&i2sWriteList, (List_Elem*)newTransaction); + * } + * } + * } + * + * static void readCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * // We must remove the previous transaction (the current one is not over) + * I2S_Transaction *transactionFinished = (I2S_Transaction*)List_prev(&transactionPtr->queueElement); + * + * if(transactionFinished != NULL){ + * // The finished transaction contains data that must be treated + * List_remove(&i2sReadList, (List_Elem*)transactionFinished); + * transactionFinished->queueElement.next = NULL; + * List_put(&treatmentList, (List_Elem*)transactionFinished); + * + * // Start the treatment of the data + * Semaphore_post(dataReadyForTreatment); + * + * // We do not need to queue transaction here: writeCallbackFxn takes care of this :) + * } + * } + * + * static void errCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * } + * + * void *myTreatmentThread(void *arg0){ + * + * int k; + * + * while(1) { + * Semaphore_pend(dataReadyForTreatment, BIOS_WAIT_FOREVER); + * + * if(lastAchievedReadTransaction != NULL) { + * + * // Need a critical section to be sure to have corresponding bufPtr and bufSize + * uintptr_t key = HwiP_disable(); + * uint16_t *buf = lastAchievedReadTransaction->bufPtr; + * uint16_t bufLength = lastAchievedReadTransaction->bufSize / sizeof(uint16_t); + * HwiP_restore(key); + * + * // My dummy data treatment... + * for(k=0; k + * @anchor ti_drivers_I2S_Example_RepeatMode + * ### Writing Data in repeat Mode # + * The following example shows how to read and write data in repeat mode. + * The same buffers are continuously written and send out while the driver is not stopped. + * Here, we decide to only stop sending out after an arbitrary number of sending. + * + *
+ * @anchor ti_drivers_I2S_Example_RepeatMode_Code + * @code + * static I2S_Handle i2sHandle; + * static I2S_Config i2sConfig; + * static I2SCC26XX_Object i2sObject; + * + * // This buffer will be continuously re-written + * static uint16_t readBuf[500]; + * // This data will be continuously sent out + * static uint16_t writeBuf[500] = {...some cool data...}; + * + * static I2S_Transaction i2sRead; + * static I2S_Transaction i2sWrite; + * + * List_List i2sReadList; + * List_List i2sWriteList; + * + * static volatile bool writeFinished = (bool)false; + * static void writeCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * // Nothing to do here: the buffer(s) are queued in a ring list, the transfers are + * // executed without any action from the application. + * + * // We must consider the previous transaction (ok, when you have only one transaction it's the same) + * I2S_Transaction *transactionFinished = (I2S_Transaction*)List_prev(&transactionPtr->queueElement); + * + * if(transactionFinished != NULL){ + * // After an arbitrary number of completion of the transaction, we will stop writting + * if(transactionFinished->numberOfCompletions >= 10) { + * + * // Note: You should avoid to use I2S_stopRead() / I2S_stopWrite() in the callback, + * // especially if you do not want to stop both read and write transfers. + * // The execution of these functions is potentially blocking and can mess up the + * // other transfers. + * + * writeFinished = (bool)true; + * } + * } + * } + * + * static void readCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * // Nothing to do here: the buffer(s) are queued in a ring list, the transfers are + * // executed without any action from the application. + * } + * + * static void errCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * } + * + * void *modeRepeat(void *arg0) + * { + * I2S_Params i2sParams; + * + * // Initialize I2S opening parameters + * I2S_Params_init(&i2sParams); + * i2sParams.fixedBufferLength = 1000; // No problem here: the driver consider + * // the list as an infinite list. + * i2sParams.writeCallback = writeCallbackFxn ; + * i2sParams.readCallback = readCallbackFxn ; + * i2sParams.errorCallback = errCallbackFxn; + * + * i2sHandle = I2S_open(0, &i2sParams); + * + * // Initialize the read-transactions + * I2S_Transaction_init(&i2sRead); + * i2sRead.bufPtr = readBuf; + * i2sRead.bufSize = sizeof(readBuf); + * List_put(&i2sReadList, (List_Elem*)&i2sRead); + * List_tail(&i2sReadList)->next = List_head(&i2sReadList);// Read buffers are queued in a ring-list + * List_head(&i2sReadList)->prev = List_tail(&i2sReadList); + * + * I2S_setReadQueueHead(i2sHandle, &i2sRead); + * + * // Initialize the write-transactions + * I2S_Transaction_init(&i2sWrite); + * i2sWrite.bufPtr = writeBuf; + * i2sWrite.bufSize = sizeof(writeBuf); + * List_put(&i2sWriteList, (List_Elem*)&i2sWrite); + * List_tail(&i2sWriteList)->next = List_head(&i2sWriteList); // Write buffers are queued in a ring-list + * List_head(&i2sWriteList)->prev = List_tail(&i2sWriteList); + * + * I2S_setWriteQueueHead(i2sHandle, &i2sWrite); + * + * I2S_startClocks(i2sHandle); + * I2S_startWrite(i2sHandle); + * I2S_startRead(i2sHandle); + * + * while(1){ + * + * if(writeFinished){ + * writeFinished = (bool)false; + * I2S_stopWrite(i2sHandle); + * } + * } + * } + * @endcode + * + * @note In the case of circular lists, there is no problem to put only + * one buffer in the queue. + * + *
+ * @anchor ti_drivers_I2S_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_I2S__include +#define ti_drivers_I2S__include + +#include +#include +#include + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + /** + * @defgroup I2S_STATUS Status Codes + * I2S_STATUS_* macros are general status codes used when user callback is called + * @{ + * @ingroup I2S_CONTROL + */ + + /*! + * @brief Successful status code returned by I2S driver functions. + * + * I2S driver functions return I2S_ALL_TRANSACTION_SUCCESS if ALL the queued transactions + * were executed successfully. + */ + #define I2S_ALL_TRANSACTIONS_SUCCESS (0x0001U) + + /*! + * @brief Successful status code returned by I2S driver functions. + * + * I2S driver functions return I2S_TRANSACTION_SUCCESS if ONE queued transaction + * was executed successfully. + */ + #define I2S_TRANSACTION_SUCCESS (0x0002U) + + /*! + * @brief Error status code returned by I2S driver functions. + * + * I2S driver functions return I2S_TIMEOUT_ERROR if I2S module lost the audio clock. + * If this error has been raised, I2S module must be reseted and restarted. + */ + #define I2S_TIMEOUT_ERROR (0x0100U) + + /*! + * @brief Error status code returned by I2S driver functions. + * + * I2S driver functions return I2S_BUS_ERROR if I2S module faced problem with the DMA + * bus (DMA transfer not completed in time). + * If this error has been raised, I2S module must be reseted and restarted. + */ + #define I2S_BUS_ERROR (0x0200U) + + /*! + * @brief Error status code returned by I2S driver functions. + * + * I2S driver functions return I2S_WS_ERROR if I2S module detect noise on the WS signal. + * If this error has been raised, I2S module must be reseted and restarted. + */ + #define I2S_WS_ERROR (0x0400U) + + /*! + * @brief Error status code returned by I2S driver functions. + * + * I2S driver functions return I2S_PTR_READ_ERROR if I2S module ran out of data + * on the read interface (DMA pointer not loaded in time). + * If this error has been raised, I2S module must be reseted and restarted. + */ + #define I2S_PTR_READ_ERROR (0x0800U) + + /*! + * @brief Error status code returned by I2S driver functions. + * + * I2S driver functions return I2S_PTR_WRITE_ERROR if I2S module ran out of data + * on the write interface (DMA pointer not loaded in time). + * If this error has been raised, I2S module must be reseted and restarted. + */ + #define I2S_PTR_WRITE_ERROR (0x1000U) + /** @}*/ + +/*! + * @brief A handle that is returned from a I2S_open() call. + */ +typedef struct I2S_Config_ *I2S_Handle; + +/*! + * @brief I2S transaction descriptor. + */ +typedef struct I2S_Transaction_ { + /*! Used internally to link descriptors together */ + List_Elem queueElement; + /*! Pointer to the buffer */ + void *bufPtr; + /*! Size of the buffer. */ + size_t bufSize; + /*! Internal use only. Number of bytes written to or read from the buffer. */ + size_t bytesTransferred; + /*! Number of non-transfered bytes at transaction's end. */ + size_t untransferredBytes; + /*! Parameter incremented each time the transaction is completed. */ + uint16_t numberOfCompletions; + /*! Internal argument. Application must not modify this element. */ + uintptr_t arg; +} I2S_Transaction; + +/*! + * @brief The definition of a user-callback function used by the I2S driver + * + * @param I2S_Handle I2S_Handle + * + * @param status Status of the operation (possible values are : + * :I2S_STATUS_SUCCESS, :I2S_STATUS_ERROR, + * :I2S_STATUS_BUFFER_UNAVAILABLE, :I2S_STATUS_TIMEOUT) + * + * @param I2S_Transaction *transactionPtr: Pointer on the transaction just completed. + * For error calbacks, transactionPtr points on NULL. + * + */ +typedef void (*I2S_Callback)(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr); + +/*! + * @brief The definition of a function used to set the I2S register + * + * @param uint32_t ui32Base: base address of the I2S module. + * + * @param uint32_t ui32NextPointer: pointer on an I2S buffer. + * + */ +typedef void (*I2S_RegUpdate)(uint32_t ui32Base, uint32_t ui32NextPointer); + +/*! + * @brief I2S slot memory length setting + * + * The enum defines if the module uses a 16 bits or a 24 bits buffer in memory. + * This value has no influence on the number of bit transmitted. + */ +typedef enum I2S_MemoryLength_ { + + I2S_MEMORY_LENGTH_8BITS = 8U, /*!< Buffer used is 8 bits length. Not available for CC26XX. */ + I2S_MEMORY_LENGTH_16BITS = 16U, /*!< Buffer used is 16 bits length. */ + I2S_MEMORY_LENGTH_24BITS = 24U, /*!< Buffer used is 24 bits length. */ + I2S_MEMORY_LENGTH_32BITS = 32U /*!< Buffer used is 32 bits length. Not available for CC26XX. */ + +} I2S_MemoryLength; + +/*! + * @brief I2S master / slave selection + * + * The enum defines if the module acts like a master (clocks are internally generated) + * or a slave (the clocks are externally generated). + */ +typedef enum I2S_Role_ { + + I2S_SLAVE = 0, /*!< Module is a slave, clocks are externally generated. */ + I2S_MASTER = 1 /*!< Module is a master, clocks are internally generated. */ + +} I2S_Role; + +/*! + * @brief I2S sampling setting + * + * The enum defines if sampling is done on BLCK rising or falling edges. + */ +typedef enum I2S_SamplingEdge_ { + + I2S_SAMPLING_EDGE_FALLING = 0, /*!< Sampling on falling edges. */ + I2S_SAMPLING_EDGE_RISING = 1 /*!< Sampling on rising edges. */ + +} I2S_SamplingEdge; + +/*! + * @brief I2S phase setting + * + * The enum defines if the I2S if set with single or dual phase. + */ +typedef enum I2S_PhaseType_ { + + I2S_PHASE_TYPE_SINGLE = 0U, /*!< Single phase */ + I2S_PHASE_TYPE_DUAL = 1U, /*!< Dual phase */ + +} I2S_PhaseType; + +/*! + * @brief I2S data interface configuration + * + * The enum defines the different settings for the data interfaces (SD0 and SD1). + */ +typedef enum I2S_DataInterfaceUse_ { + + I2S_SD0_DISABLED = 0x00U, /*!< SD0 is disabled */ + I2S_SD0_INPUT = 0x01U, /*!< SD0 is an input */ + I2S_SD0_OUTPUT = 0x02U, /*!< SD0 is an output */ + I2S_SD1_DISABLED = 0x00U, /*!< SD1 is disabled */ + I2S_SD1_INPUT = 0x10U, /*!< SD1 is an input */ + I2S_SD1_OUTPUT = 0x20U /*!< SD1 is an output */ + +} I2S_DataInterfaceUse; + +/*! + * @brief Channels used selection + * + * The enum defines different settings to activate the expected channels. + */ +typedef enum I2S_ChannelConfig_ { + + I2S_CHANNELS_NONE = 0x00U, /*!< No channel activated */ + I2S_CHANNELS_MONO = 0x01U, /*!< MONO: only channel one is activated */ + I2S_CHANNELS_MONO_INV = 0x02U, /*!< MONO INVERERTED: only channel two is activated */ + I2S_CHANNELS_STEREO = 0x03U, /*!< STEREO: channels one and two are activated */ + I2S_1_CHANNEL = 0x01U, /*!< 1 channel is activated */ + I2S_2_CHANNELS = 0x03U, /*!< 2 channels are activated */ + I2S_3_CHANNELS = 0x07U, /*!< 3 channels are activated */ + I2S_4_CHANNELS = 0x0FU, /*!< 4 channels are activated */ + I2S_5_CHANNELS = 0x1FU, /*!< 5 channels are activated */ + I2S_6_CHANNELS = 0x3FU, /*!< 6 channels are activated */ + I2S_7_CHANNELS = 0x7FU, /*!< 7 channels are activated */ + I2S_8_CHANNELS = 0xFFU, /*!< 8 channels are activated */ + I2S_CHANNELS_ALL = 0xFFU /*!< All the eight channels are activated */ + +} I2S_ChannelConfig; + +/*! + * @brief Basic I2S Parameters + * + * I2S parameters are used to with the I2S_open() call. Default values for + * these parameters are set using I2S_Params_init(). + * + * @sa I2S_Params_init() + */ +typedef struct I2S_Params_ { + + bool invertWS; + /*!< WS must be internally inverted when using I2S data format. + * false: The WS signal is not internally inverted. + * true: The WS signal is internally inverted. */ + + bool isMSBFirst; + /*!< Endianness selection. Not available on CC26XX. + * false: The samples are transmitted LSB first. + * true: The samples are transmitted MSB first. */ + + bool isDMAUnused; + /*!< Selection between DMA transmissions and CPU transmissions. + * false: Transmission are performed by DMA. + * true: Transmission are performed by CPU. + * Not available for CC26XX: all transmissions are performed by CPU. */ + + I2S_MemoryLength memorySlotLength; + /*!< Memory buffer used. + * #I2S_MEMORY_LENGTH_8BITS: Memory length is 8 bits (not available for CC26XX). + * #I2S_MEMORY_LENGTH_16BITS: Memory length is 16 bits. + * #I2S_MEMORY_LENGTH_24BITS: Memory length is 24 bits. + * #I2S_MEMORY_LENGTH_32BITS: Memory length is 32 bits (not available for CC26XX).*/ + + uint8_t beforeWordPadding; + /*!< Number of SCK periods between the first WS edge and the MSB of the first audio channel data transferred during the phase.*/ + + uint8_t afterWordPadding; + /*!< Number of SCK periods between the first WS edge and the MSB of the first audio channel data transferred during the phase.*/ + + uint8_t bitsPerWord; + /*!< Bits per sample (Word length): must be between 8 and 24 bits. */ + + I2S_Role moduleRole; + /*!< Select if the I2S module is a Slave or a Master. + * - #I2S_SLAVE: The device is a slave (clocks are generated externally). + * - #I2S_MASTER: The device is a master (clocks are generated internally). */ + + I2S_SamplingEdge samplingEdge; + /*!< Select edge sampling type. + * - #I2S_SAMPLING_EDGE_FALLING: Sampling on falling edges (for DSP data format). + * - #I2S_SAMPLING_EDGE_RISING: Sampling on rising edges (for I2S, LJF and RJF data formats). */ + + I2S_DataInterfaceUse SD0Use; + /*!< Select if SD0 is an input, an output or disabled. + * - #I2S_SD0_DISABLED: Disabled. + * - #I2S_SD0_INPUT: Input. + * - #I2S_SD0_OUTPUT: Output. */ + + I2S_DataInterfaceUse SD1Use; + /*!< Select if SD1 is an input, an output or disabled. + * - #I2S_SD1_DISABLED: Disabled. + * - #I2S_SD1_INPUT: Input. + * - #I2S_SD1_OUTPUT: Output. */ + + I2S_ChannelConfig SD0Channels; + /*!< This parameter is a bit mask indicating which channels are valid on SD0. + * If phase type is "dual", maximum channels number is two. + * Valid channels on SD1 and SD0 can be different. + * For dual phase mode: + * - #I2S_CHANNELS_NONE: No channel activated: + * read -> I2S does not receive anything (no buffer consumption) + * write -> I2S does not send anything (no buffer consumption) + * - #I2S_CHANNELS_MONO: Only channel 1 is activated: + * read -> I2S only reads channel 1 + * write -> I2S transmits the data on channel 1 and duplicates it on channel 2 + * - #I2S_CHANNELS_MONO_INV: Only channel 2 is activated: + * read -> I2S only reads channel 2 + * write -> I2S transmits the data on channel 2 and duplicates it on the channel 1 of the next word + * - #I2S_CHANNELS_STEREO: STEREO: + * read -> I2S reads both channel 1 and channel 2 + * write -> I2S transmits data both on channel 1 and channel 2 + * . + * For single phase mode: + * - Various number of channels can be activated using: #I2S_1_CHANNEL, #I2S_2_CHANNELS, #I2S_3_CHANNELS, #I2S_4_CHANNELS, + * #I2S_5_CHANNELS, #I2S_6_CHANNELS, #I2S_7_CHANNELS, #I2S_8_CHANNELS. + * - #I2S_CHANNELS_ALL: The eight channels are activated */ + + I2S_ChannelConfig SD1Channels; + /*!< This parameter is a bit mask indicating which channels are valid on SD1. + * If phase type is "dual", maximum channels number is two. + * Valid channels on SD1 and SD0 can be different. + * For dual phase mode: + * - #I2S_CHANNELS_NONE: No channel activated: + * read -> I2S does not receive anything (no buffer consumption) + * write -> I2S does not send anything (no buffer consumption) + * - #I2S_CHANNELS_MONO: Only channel 1 is activated: + * read -> I2S only reads channel 1 + * write -> I2S transmits the data on channel 1 and duplicates it on channel 2 + * - #I2S_CHANNELS_MONO_INV: Only channel 2 is activated: + * read -> I2S only reads channel 2 + * write -> I2S transmits the data on channel 2 and duplicates it on the channel 1 of the next word + * - #I2S_CHANNELS_STEREO: STEREO: + * read -> I2S reads both channel 1 and channel 2 + * write -> I2S transmits data both on channel 1 and channel 2 + * . + * For single phase mode: + * - Various number of channels can be activated using: #I2S_1_CHANNEL, #I2S_2_CHANNELS, #I2S_3_CHANNELS, #I2S_4_CHANNELS, + * #I2S_5_CHANNELS, #I2S_6_CHANNELS, #I2S_7_CHANNELS, #I2S_8_CHANNELS. + * - #I2S_CHANNELS_ALL: The eight channels are activated */ + + I2S_PhaseType phaseType; + /*!< Select phase type. + * - #I2S_PHASE_TYPE_SINGLE: Single phase (for DSP format): up to eight channels are usable. + * - #I2S_PHASE_TYPE_DUAL: Dual phase (for I2S, LJF and RJF data formats): up to two channels are usable. + * . + * This parameter must not be considered on CC32XX. This chip only allows dual phase formats.*/ + + uint16_t fixedBufferLength; + /*!< Number of consecutive bytes of the samples buffers. This field must be set to a value x different from 0. + * All the data buffers used (both for input and output) must contain N*x bytes (with N an integer verifying N>0). */ + + uint16_t startUpDelay; + /*!< Time (in number of WS cycles) to wait before the first transfer. */ + + uint16_t MCLKDivider; + /*!< Select the frequency divider for MCLK signal. Final value of MCLK is 48MHz/MCLKDivider. Value must be selected between 2 and 1024. */ + + uint32_t samplingFrequency; + /*!< I2S sampling frequency configuration in samples/second. + * SCK frequency limits: + *- For CC26XX, SCK frequency should be between 47 kHz and 4 MHz. + *- For CC32XX, SCK frequency should be between 57 Hz and 8 MHz. */ + + I2S_Callback readCallback; + /*!< Pointer to read callback. Cannot be NULL if a read interface is activated. */ + + I2S_Callback writeCallback; + /*!< Pointer to write callback. Cannot be NULL if a write interface is activated. */ + + I2S_Callback errorCallback; + /*!< Pointer to error callback. Cannot be NULL. */ + + void *custom; + /*!< Pointer to device specific custom params */ +} I2S_Params; + +/*! + * @brief Default I2S_Params structure + * + * @sa I2S_Params_init() + */ +extern const I2S_Params I2S_defaultParams; + +/*! @brief I2S Global configuration + * + * The I2S_Config structure contains a set of pointers used to characterize + * the I2S driver implementation. + * + * This structure needs to be defined before calling I2S_init() and it must + * not be changed thereafter. + * + * @sa I2S_init() + */ +typedef struct I2S_Config_ { + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} I2S_Config; + +/*! + * @brief Function to close a given I2S peripheral specified by the I2S + * handle. + * + * @pre I2S_open() had to be called first. + * + * @param [in] handle An I2S_Handle returned from I2S_open + * + * @sa I2S_open() + */ +extern void I2S_close(I2S_Handle handle); + +/*! + * @brief Function to initializes the I2S module + * + * @pre The I2S_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other I2S driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void I2S_init(void); + +/*! + * @brief Function to initialize a given I2S peripheral specified by the + * particular index value. The parameter specifies which mode the I2S + * will operate. + * + * @pre I2S controller has been initialized + * + * @param [inout] index Logical peripheral number for the I2S indexed into + * the I2S_config table + * + * @param [in] params Pointer to an parameter block. + * All the fields in this structure are RO (read-only). + * Provide a NULL pointer cannot open the module. + * + * @return An I2S_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa I2S_init() + * @sa I2S_close() + */ +extern I2S_Handle I2S_open(uint_least8_t index, I2S_Params *params); + +/*! + * @brief Function to initialize the I2S_Params struct to its defaults + * + * @param [out] params An pointer to I2S_Params structure for + * initialization + * + * Defaults values are: + * @code + * params.samplingFrequency = 8000; + * params.isMemory24Bits = I2S_MEMORY_LENGTH_16BITS; + * params.isMaster = I2S_MASTER; + * params.invertWS = (bool)true; + * params.isMSBFirst = (bool)true; + * params.isDMAUnused = (bool)false; + * params.samplingEdge = I2S_SAMPLING_EDGE_RISING; + * params.beforeWordPadding = 0; + * params.bitsPerWord = 16; + * params.afterWordPadding = 0; + * params.fixedBufferLength = 1; + * params.SD0Use = I2S_SD0_OUTPUT; + * params.SD1Use = I2S_SD1_INPUT; + * params.SD0Channels = I2S_CHANNELS_STEREO; + * params.SD1Channels = I2S_CHANNELS_STEREO; + * params.phaseType = I2S_PHASE_TYPE_DUAL; + * params.startUpDelay = 0; + * params.MCLKDivider = 40; + * params.readCallback = NULL; + * params.writeCallback = NULL; + * params.errorCallback = NULL; + * params.custom = NULL; + * @endcode + * + * @param params Parameter structure to initialize + */ +extern void I2S_Params_init(I2S_Params *params); + +/*! + * @brief Initialize an I2S_Transaction struct to known state. + * + * The I2S_Transaction struct is put in a known state. The application is + * still responsible for populating some of the fields. + * For example, the user is responsible to provide the buffer containing the + * data and the size of it. + * User provided buffer's size must matche with the I2S settings. + * If the buffer size is not adapted, the I2S module will truncate it. + * Authorized buffer sizes depend on the number of activated outputs, the number + * of channels activated, the memory slots length (16 or 24 bits), and the + * fixed-buffer-size eventually provided. + * Authorized buffer sizes are all the multiple values of the value of + * handle->object->memoryStepOut. + * + * @param [out] transaction Transaction struct to initialize. + */ +extern void I2S_Transaction_init(I2S_Transaction *transaction); + +/*! + * @brief Function to set the first read-transaction to consider + * + * At the end of each transaction, I2S driver takes in consideration the next + * transaction. Application is responsible to handle the queue. + * + * @param [in] handle An I2S_Handle. + * + * @param [in] transaction A pointer to an I2S_Transaction object. The bufPtr + * and bufSize fields must be set to a buffer and the + * size of the buffer before passing to this function. + * + * @return void + * + * @sa I2S_setWriteQueueHead() + */ +extern void I2S_setReadQueueHead(I2S_Handle handle, I2S_Transaction *transaction); + +/*! + * @brief Function to set the first write-transaction to consider + * + * At the end of each transaction, I2S driver takes in consideration the next + * transaction. Application is responsible to handle the queue. + * + * @param [in] handle An I2S_Handle. + * + * @param [in] transaction A pointer to an I2S_Transaction object. The bufPtr + * and bufSize fields must be set to a buffer and the + * size of the buffer before passing to this function. + * + * @return void + * + * @sa I2S_setReadQueueHead() + */ +extern void I2S_setWriteQueueHead(I2S_Handle handle, I2S_Transaction *transaction); + +/*! + * @brief Start the WS, SCK and MCLK clocks. + * + * This function enable WS, SCK and MCLK (if activated) clocks. This is required before starting + * any reading or a writing transaction. + * This function is supposed to be executed both in slave and master mode. + * + * @param [in] handle An I2S_Handle. + * + * @return void + * + * @sa I2S_stopClocks() + */ +extern void I2S_startClocks(I2S_Handle handle); + +/*! + * @brief Stops the WS, SCK and MCLK clocks. + * + * This function disable WS, SCK and MCLK clocks. + * This function must be executed only if no transaction is in progress. + * This function is supposed to be executed both in slave and master mode. + * + * @param [in] handle An I2S_Handle. + * + * @return void + * + * @sa I2S_stopRead() + * @sa I2S_stopWrite() + */ +extern void I2S_stopClocks(I2S_Handle handle); + +/*! + * @brief Start read transactions. + * + * This function starts reception of the transactions stored in the read-queue. + * and returns immediately. At the end of the transaction(s) the readCallback + * provided is executed. + * Clocks must be running before calling this function. + * + * @param [in] handle An I2S_Handle. + * + * @return void + * + * @sa I2S_stopRead() + */ +extern void I2S_startRead(I2S_Handle handle); + +/*! + * @brief Start write transactions. + * + * This function starts transmission of the transactions stored in the write-queue + * and returns immediately. At the end of the transaction(s) the writeCallback + * provided is executed. + * Clocks must be running before calling this function. + * + * @param [in] handle An I2S_Handle. + * + * @return void + * + * @sa I2S_startClocks + */ +extern void I2S_startWrite(I2S_Handle handle); + +/*! + * @brief Stop read transactions. + * + * This function stops reception of the transactions stored in the read-queue. + * To avoid the apparition of errors, this function blocks while currently + * received sample is not completely done. + * + * @param [in] handle An I2S_Handle. + * + * @return void + */ +extern void I2S_stopRead(I2S_Handle handle); + +/*! + * @brief Stop write transactions. + * + * This function stops transmission of the transactions stored in the write-queue. + * To avoid the apparition of errors, this function blocks while currently + * transmitted sample is not completely done. + * + * @param [in] handle An I2S_Handle. + * + * @return void + */ +extern void I2S_stopWrite(I2S_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_I2S__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/NVS.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/NVS.c new file mode 100644 index 0000000..bdff5e1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/NVS.c @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== NVS.c ======== + */ +#include +#include +#include +#include + +#include +#include + +extern NVS_Config NVS_config[]; +extern const uint8_t NVS_count; + +static bool isInitialized = false; + +/* Default NVS parameters structure */ +const NVS_Params NVS_defaultParams = { + NULL /* custom */ +}; + +/* + * ======== NVS_close ======= + */ +void NVS_close(NVS_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== NVS_control ======== + */ +int_fast16_t NVS_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg) +{ + return (handle->fxnTablePtr->controlFxn(handle, cmd, arg)); +} + +/* + * ======== NVS_erase ======= + */ +int_fast16_t NVS_erase(NVS_Handle handle, size_t offset, size_t size) +{ + return (handle->fxnTablePtr->eraseFxn(handle, offset, size)); +} + +/* + * ======== NVS_getAttrs ======= + */ +void NVS_getAttrs(NVS_Handle handle, NVS_Attrs *attrs) +{ + handle->fxnTablePtr->getAttrsFxn(handle, attrs); +} + +/* + * ======== NVS_init ======= + */ +void NVS_init(void) +{ + uint_least8_t i; + + /* Call each driver's init function */ + for (i = 0; i < NVS_count; i++) { + NVS_config[i].fxnTablePtr->initFxn(); + } + + isInitialized = true; +} + +/* + * ======== NVS_lock ======= + */ +int_fast16_t NVS_lock(NVS_Handle handle, uint32_t timeout) +{ + return (handle->fxnTablePtr->lockFxn(handle, timeout)); +} + +/* + * ======== NVS_open ======= + */ +NVS_Handle NVS_open(uint_least8_t index, NVS_Params *params) +{ + NVS_Handle handle = NULL; + + /* do init if not done yet */ + if (!isInitialized) { + NVS_init(); + } + + if (index < NVS_count) { + if (params == NULL) { + /* No params passed in, so use the defaults */ + params = (NVS_Params *)&NVS_defaultParams; + } + handle = NVS_config[index].fxnTablePtr->openFxn(index, params); + } + + return (handle); +} + +/* + * ======== NVS_Params_init ======= + */ +void NVS_Params_init(NVS_Params *params) +{ + *params = NVS_defaultParams; +} + +/* + * ======== NVS_read ======= + */ +int_fast16_t NVS_read(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize) +{ + return (handle->fxnTablePtr->readFxn(handle, offset, buffer, bufferSize)); +} + +/* + * ======== NVS_unlock ======= + */ +void NVS_unlock(NVS_Handle handle) +{ + handle->fxnTablePtr->unlockFxn(handle); +} + +/* + * ======== NVS_write ======= + */ +int_fast16_t NVS_write(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize, uint_fast16_t flags) +{ + return (handle->fxnTablePtr->writeFxn(handle, offset, buffer, + bufferSize, flags)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/NVS.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/NVS.h new file mode 100644 index 0000000..dcfcbff --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/NVS.h @@ -0,0 +1,843 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file NVS.h + * @brief Non-Volatile Storage driver interface + * + * @anchor ti_drivers_NVS_Overview + * # Overview # + * + * The NVS module allows you to manage non-volatile memory. Using the + * NVS APIs, you can read and write data from and to persistent storage. + * + * Each NVS object is used to manage a region of non-volatile memory. + * The size of the region is specified in the device specific driver's + * hardware attributes. + * A sector is the smallest unit of non-volatile storage that can be erased + * at one time. The size of the sector, or sector size, is hardware specific + * and may be meaningless for some non-volatile storage hardware. For flash + * memory devices, the region must be aligned with the sector size. That is, + * the region must start on a sector boundary. Additionally, the overall size + * of the region must be an integer multiple of the sector size. + * + *
+ * @anchor ti_drivers_NVS_Usage + * # Usage + * + * This section provides a basic @ref ti_drivers_NVS_Synopsis + * "usage summary" and a set of @ref ti_drivers_NVS_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + + * The NVS driver interface provides device independent APIs, data types, + * and macros. The following code example opens an NVS region instance, + * writes a string into it, then prints the string after reading it back + * into a local buffer, and also prints the string from its directly + * addressable location in flash memory. + * + * @anchor ti_drivers_NVS_Synopsis + * ## Synopsis + * @anchor ti_drivers_NVS_Synopsis_Code + * @code + * // Import NVS Driver definitions + * #include + * + * // One time init of NVS driver + * NVS_init(); + * + * // Initialize optional NVS parameters + * NVS_Params_init(&nvsParams); + * + * // Open NVS driver instance + * nvsRegion = NVS_open(config_NVS0, &nvsParams); + * + * // write "Hello" to the base address of region 0, verify after write + * status = NVS_write(nvsRegion, 0, "Hello", strlen("Hello")+1, NVS_POST_VERIFY); + * + * // Close NVS region + * NVS_close(nvsRegion); + * + * @endcode + * + *
+ * @anchor ti_drivers_NVS_Examples + * # Examples + * + * @li @ref ti_drivers_NVS_Examples_open "Opening an NVS region instance" + * @li @ref ti_drivers_NVS_Examples_typical "Typical NVS region operations" + * + * @anchor ti_drivers_NVS_Examples_open + * ## Opening an NVS region instance + * + * @code + * NVS_Handle nvsRegion; + * NVS_Params nvsParams; + * + * NVS_Params_init(&nvsParams); + * nvsRegion = NVS_open(Board_NVS0, &nvsParams); + * @endcode + * + * @anchor ti_drivers_NVS_Examples_typical + * ## Erasing, writing, reading an NVS region + * + * The following code example opens an NVS region instance, erases the first + * sector of that region, writes a string into it, then prints the string + * after reading it back into a local buffer. If the string is directly CPU + * addressable (i.e. not in SPI flash), the string is printed from + * its location in flash memory. + * + * @code + * + * // Import NVS Driver definitions + * #include + * + * NVS_Handle nvsRegion; + * NVS_Attrs regionAttrs; + * + * uint_fast16_t status; + * char buf[32]; + * + * // initialize the NVS driver + * NVS_init(); + * + * // + * // Open the NVS region specified by the 0th element in the NVS_config[] + * // array defined in Board.c. + * // + * // Use default NVS_Params to open this memory region, hence 'NULL' + * // + * nvsRegion = NVS_open(Board_NVS0, NULL); + * + * // Confirm that the NVS region opened properly + * if (nvsRegion == NULL) { + * // Error handling code + * } + * + * // Fetch the generic NVS region attributes for nvsRegion + * NVS_getAttrs(nvsRegion, ®ionAttrs); + * + * // Erase the first sector of nvsRegion + * status = NVS_erase(nvsRegion, 0, regionAttrs.sectorSize); + * if (status != NVS_STATUS_SUCCESS) { + * // Error handling code + * } + * + * // Write "Hello" to the base address of nvsRegion, verify after write + * status = NVS_write(nvsRegion, 0, "Hello", strlen("Hello")+1, NVS_POST_VERIFY); + * if (status != NVS_STATUS_SUCCESS) { + * // Error handling code + * } + * + * // Copy "Hello" from nvsRegion into local 'buf' + * status = NVS_read(nvsRegion, 0, buf, strlen("Hello")+1); + * if (status != NVS_STATUS_SUCCESS) { + * // Error handling code + * } + * + * // Print the string from fetched NVS storage + * System_printf("%s\n", buf); + * + * // + * // Print the string using direct flash address reference if valid + * // + * // When the NVS driver is managing SPI flash non volatile + * // storage, the regionBase attribute will be `NVS_REGION_NOT_ADDRESSABLE` + * // + * if (regionAttrs.regionBase != NVS_REGION_NOT_ADDRESSABLE) { + * System_printf("%s\n", regionAttrs.regionBase); + * } + * + * // close the region + * NVS_close(nvsRegion); + * + * @endcode + * + *
+ * @anchor ti_drivers_NVS_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ * + * # Example discussion + * + * Details for the @ref ti_drivers_NVS_Examples_typical "Typical NVS region operations" + * example code above are described in the following subsections. + * + * ### NVS Driver Configuration # + * + * In order to use the NVS APIs, the application is required + * to provide device-specific NVS configuration in the Board.c file. + * The NVS driver interface defines a configuration data structure, + * #NVS_Config. + * + * The application must declare an array of #NVS_Config elements, named + * \p NVS_config[]. Each element of \p NVS_config[] is populated with + * pointers to a device specific NVS driver implementation's function + * table, driver object, and hardware attributes. The hardware attributes + * define properties such as the NVS region's base address and size, + * Each element in \p NVS_config[] corresponds to a NVS instance, and none + * of the elements should have NULL pointers. + * + * You will need to check the device-specific NVS driver implementation's + * header file for example configuration. Please also refer to the + * Board.c file of any of the provided examples to see the NVS configuration. + * + * ### Initializing the NVS Driver # + * + * NVS_init() must be called before any other NVS APIs. This function + * calls the device implementation's NVS initialization function, for each + * element of \p NVS_config[]. + * + * ### Opening the NVS Driver # + * + * Opening a NVS requires four steps: + * 1. Optionally create and initialize a #NVS_Params structure. + * 2. Fill in the desired parameters. + * 3. Call NVS_open(), passing the index of the NVS region in the #NVS_Config + * structure, and the address of the #NVS_Params structure. + * 4. Check that the #NVS_Handle returned by NVS_open() is non-NULL, + * and save it. The handle will be used to read and write to the + * NVS you just opened. + * + * \note Each NVS index can only be opened exclusively. Calling NVS_open() + * multiple times with the same index will result in an error. The index can + * be re-used if NVS_close() is called first. + * + *
+ * # Thread Safety # + * + * All NVS APIs are globally thread safe. Consequently, only one write, + * erase (or read in the case of SPI flash) operation is allowed to be + * performed at a time, even for distinct NVS regions. Threads initiating + * new NVS writes or erases will block until any current operation completes. + * + * # Interrupt Latency During Flash Operations # + * + * When writing to or erasing internal flash, interrupts must be disabled + * to avoid executing code in flash while the flash is being reprogrammed. + * This constraint is met internally by the driver. User code does not need + * to safeguard against this. + * + * Care must be taken by the user to not perform flash write or erase + * operations during latency critical phases of an application. See the + * NVS_lock() and NVS_unlock() API descriptions for more information. + * + ***************************************************************************** + */ + +#ifndef ti_drivers_NVS__include +#define ti_drivers_NVS__include + +#include +#include +#include + +#if defined (__cplusplus) +extern "C" { +#endif + +/** + * @defgroup NVS_CONTROL NVS_control command and status codes + * These NVS macros are reservations for NVS.h + * @{ + */ + +/*! + * Common NVS_control command code reservation offset. + * NVS driver implementations should offset command codes with NVS_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define NVSXYZ_CMD_COMMAND0 NVS_CMD_RESERVED + 0 + * #define NVSXYZ_CMD_COMMAND1 NVS_CMD_RESERVED + 1 + * @endcode + */ +#define NVS_CMD_RESERVED (32) + +/*! + * Common NVS_control status code reservation offset. + * NVS driver implementations should offset status codes with + * NVS_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define NVSXYZ_STATUS_ERROR0 NVS_STATUS_RESERVED - 0 + * #define NVSXYZ_STATUS_ERROR1 NVS_STATUS_RESERVED - 1 + * #define NVSXYZ_STATUS_ERROR2 NVS_STATUS_RESERVED - 2 + * @endcode + */ +#define NVS_STATUS_RESERVED (-32) + +/** + * @defgroup NVS_STATUS Status Codes + * NVS_STATUS_* macros are general status codes returned by NVS_control() + * @{ + * @ingroup NVS_CONTROL + */ + +/*! + * @brief Successful status code returned by: + * NVS_control(), NVS_read(), NVS_write(), NVS_erase(), or + * NVS_lock(). + * + * APIs returns NVS_STATUS_SUCCESS if the API was executed + * successfully. + */ +#define NVS_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by: + * NVS_control(), NVS_erase(), or NVS_write(), + * + * APIs return NVS_STATUS_ERROR if the API was not executed + * successfully. + */ +#define NVS_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by NVS_control() for undefined + * command codes. + * + * NVS_control() returns #NVS_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define NVS_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief An error status code returned by NVS_lock() + * + * NVS_lock() will return this value if the @p timeout has expired + */ +#define NVS_STATUS_TIMEOUT (-3) + +/*! + * @brief An error status code returned by NVS_read(), NVS_write(), or + * NVS_erase() + * + * Error status code returned if the @p offset argument is invalid + * (e.g., when offset + bufferSize exceeds the size of the region). + */ +#define NVS_STATUS_INV_OFFSET (-4) + +/*! + * @brief An error status code + * + * Error status code returned by NVS_erase() if the @p offset argument is + * not aligned on a flash sector address. + */ +#define NVS_STATUS_INV_ALIGNMENT (-5) + +/*! + * @brief An error status code returned by NVS_erase() and NVS_write() + * + * Error status code returned by NVS_erase() if the @p size argument is + * not a multiple of the flash sector size, or if @p offset + @p size + * extends past the end of the region. + */ +#define NVS_STATUS_INV_SIZE (-6) + +/*! + * @brief An error status code returned by NVS_write() + * + * NVS_write() will return this value if #NVS_WRITE_PRE_VERIFY is + * requested and a flash location can not be changed to the value + * desired. + */ +#define NVS_STATUS_INV_WRITE (-7) + +/** @}*/ + +/** + * @defgroup NVS_CMD Command Codes + * NVS_CMD_* macros are general command codes for NVS_control(). Not all NVS + * driver implementations support these command codes. + * @{ + * @ingroup NVS_CONTROL + */ + +/* Add NVS_CMD_ here */ + +/** @} end NVS commands */ + +/** @} end NVS_CONTROL group */ + + +/*! + * @brief NVS write flags + * + * The following flags can be or'd together and passed as a bit mask + * to NVS_write. + * @{ + */ + +/*! + * @brief Erase write flag. + * + * If #NVS_WRITE_ERASE is set in the flags passed to NVS_write(), the + * affected destination flash sectors will be erased prior to the + * start of the write operation. + */ +#define NVS_WRITE_ERASE (0x1) + +/*! + * @brief Validate write flag. + * + * If #NVS_WRITE_PRE_VERIFY is set in the flags passed to NVS_write(), the + * destination address range will be pre-tested to guarantee that the source + * data can be successfully written. If #NVS_WRITE_ERASE is also requested in + * the write flags, then the #NVS_WRITE_PRE_VERIFY modifier is ignored. + */ +#define NVS_WRITE_PRE_VERIFY (0x2) + +/*! + * @brief Validate write flag. + * + * If #NVS_WRITE_POST_VERIFY is set in the flags passed to NVS_write(), the + * destination address range will be tested after the write is finished to + * verify that the write operation was completed successfully. + */ +#define NVS_WRITE_POST_VERIFY (0x4) + +/** @} */ + +/*! + * @brief Special NVS_lock() timeout values + * @{ + */ + + /*! + * @brief NVS_lock() Wait forever define + */ +#define NVS_LOCK_WAIT_FOREVER (~(0U)) + +/*! + * @brief NVS_lock() No wait define + */ +#define NVS_LOCK_NO_WAIT (0U) + +/** @} */ + +/*! + * @brief Special NVS_Attrs.regionBase value + * @{ + */ + + /*! + * @brief This region is not directly addressable (e.g.,: SPI flash region) + * + * The NVS_Attrs.regionBase field returned by NVS_getAttrs() is set to this + * value by the NVSSPI driver to indicate that the region is not directly + * addressable. + */ +#define NVS_REGION_NOT_ADDRESSABLE ((void *)(~(0U))) + +/** @} */ + +/*! + * @brief NVS Parameters + * + * NVS parameters are used with the NVS_open() call. Default values for + * these parameters are set using NVS_Params_init(). + * + * @sa NVS_Params_init() + */ +typedef struct +{ + void *custom; /*!< Custom argument used by driver implementation */ +} NVS_Params; + +/*! + * @brief NVS attributes + * + * The address of an NVS_Attrs structure is passed to NVS_getAttrs(). + * + * @sa NVS_getAttrs() + */ +typedef struct +{ + void *regionBase; /*!< Base address of the NVS region. If the NVS + region is not directly accessible by the MCU + (such as SPI flash), this field will be set to + #NVS_REGION_NOT_ADDRESSABLE. */ + size_t regionSize; /*!< NVS region size in bytes. */ + size_t sectorSize; /*!< Erase sector size in bytes. This attribute is + device specific. */ +} NVS_Attrs; + +/*! + * @brief A handle that is returned from the NVS_open() call. + */ +typedef struct NVS_Config_ *NVS_Handle; + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_close(). + */ +typedef void (*NVS_CloseFxn) (NVS_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_control(). + */ +typedef int_fast16_t (*NVS_ControlFxn) (NVS_Handle handle, uint_fast16_t cmd, + uintptr_t arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_erase(). + */ +typedef int_fast16_t (*NVS_EraseFxn) (NVS_Handle handle, size_t offset, + size_t size); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_getAttrs(). + */ +typedef void (*NVS_GetAttrsFxn) (NVS_Handle handle, NVS_Attrs *attrs); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_init(). + */ +typedef void (*NVS_InitFxn) (void); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_open(). + */ +typedef NVS_Handle (*NVS_OpenFxn) (uint_least8_t index, NVS_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_read(). + */ +typedef int_fast16_t (*NVS_ReadFxn) (NVS_Handle handle, size_t offset, + void *buffer, size_t bufferSize); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_write(). + */ +typedef int_fast16_t (*NVS_WriteFxn) (NVS_Handle handle, size_t offset, + void *buffer, size_t bufferSize, + uint_fast16_t flags); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_lock(). + */ +typedef int_fast16_t (*NVS_LockFxn) (NVS_Handle handle, uint32_t timeout); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_unlock(). + */ +typedef void (*NVS_UnlockFxn) (NVS_Handle handle); + +/*! + * @brief The definition of an NVS function table that contains the + * required set of functions to control a specific NVS driver + * implementation. + */ +typedef struct +{ + /*! Function to close the specified NVS region */ + NVS_CloseFxn closeFxn; + + /*! Function to apply control command to the specified NVS region */ + NVS_ControlFxn controlFxn; + + /*! Function to erase a portion of the specified NVS region */ + NVS_EraseFxn eraseFxn; + + /*! Function to get the NVS device-specific attributes */ + NVS_GetAttrsFxn getAttrsFxn; + + /*! Function to initialize the NVS module */ + NVS_InitFxn initFxn; + + /*! Function to lock the specified NVS flash region */ + NVS_LockFxn lockFxn; + + /*! Function to open an NVS region */ + NVS_OpenFxn openFxn; + + /*! Function to read from the specified NVS region */ + NVS_ReadFxn readFxn; + + /*! Function to unlock the specified NVS flash region */ + NVS_UnlockFxn unlockFxn; + + /*! Function to write to the specified NVS region */ + NVS_WriteFxn writeFxn; +} NVS_FxnTable; + +/*! + * @brief NVS Global configuration + * + * The NVS_Config structure contains a set of pointers used to characterize + * the NVS driver implementation. + * + * This structure needs to be defined before calling NVS_init() and it must + * not be changed thereafter. + * + * @sa NVS_init() + */ +typedef struct NVS_Config_ +{ + /*! Pointer to a table of driver-specific implementations of NVS APIs */ + NVS_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} NVS_Config; + +/*! + * @brief Function to close an #NVS_Handle. + * + * @param handle A handle returned from NVS_open() + * + * @sa NVS_open() + */ +extern void NVS_close(NVS_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * #NVS_Handle. + * + * @pre NVS_open() must be called first. + * + * @param handle An #NVS_Handle returned from NVS_open() + * + * @param cmd A command value defined by the driver specific + * implementation + * + * @param arg An optional read or write argument that is + * accompanied with @p cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa NVS_open() + */ +extern int_fast16_t NVS_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg); + +/*! + * @brief Erase @p size bytes of the region beginning at @p offset bytes + * from the base of the region referenced by the #NVS_Handle. + * + * @warning Erasing internal flash on most devices can introduce + * significant interrupt latencies while the erase operation is in + * in progress. The user may want to surround certain real-time + * critical code sections with NVS_lock() and NVS_unlock() calls in order + * to prevent uncoordinated flash erase operations from negatively + * impacting performance. + * + * @param handle A handle returned from NVS_open() + * + * @param offset The byte offset into the NVS region to start + * erasing from (must be erase sector aligned) + * + * @param size The number of bytes to erase (must be integer + * multiple of sector size) + * + * @retval #NVS_STATUS_SUCCESS Success. + * @retval #NVS_STATUS_INV_ALIGNMENT If @p offset is not aligned on + * a sector boundary + * @retval #NVS_STATUS_INV_OFFSET If @p offset exceeds region size + * @retval #NVS_STATUS_INV_SIZE If @p size or @p offset + @p size + * exceeds region size, or if @p size + * is not an integer multiple of + * the flash sector size. + * @retval #NVS_STATUS_ERROR If an internal error occurred + * erasing the flash. + */ +extern int_fast16_t NVS_erase(NVS_Handle handle, size_t offset, size_t size); + +/*! + * @brief Function to get the NVS attributes + * + * This function will populate a #NVS_Attrs structure with attributes + * specific to the memory region associated with the #NVS_Handle. + * + * @param handle A handle returned from NVS_open() + * + * @param attrs Location to store attributes. + */ +extern void NVS_getAttrs(NVS_Handle handle, NVS_Attrs *attrs); + +/*! + * @brief Function to initialize the NVS module + * + * @pre The NVS_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other NVS APIs. + */ +extern void NVS_init(void); + +/*! + * @brief Function to lock the NVS driver + * + * This function is provided in the event that the user needs to + * perform some flash related operation not provided by the NVS + * driver API set or if the user simply needs to block flash operations + * for a period of time. + * + * For example, the interrupt latency introduced + * by an uncoordinated flash write operation could interfere with some + * critical operation being performed by the application. + * + * NVS_lock() prevents any other thread from initiating + * read, write, or erase operations while the user is performing an + * operation which is incompatible with those functions. + * + * When the application no longer needs to block flash operations by + * other threads, NVS_unlock() must be called to allow NVS write or erase + * APIs to complete. + * + * @param handle A handle returned from NVS_open() + * + * @param timeout Timeout (in milliseconds) to wait, + * or #NVS_LOCK_WAIT_FOREVER, #NVS_LOCK_NO_WAIT + * + * @retval #NVS_STATUS_SUCCESS Success. + * @retval #NVS_STATUS_TIMEOUT If @p timeout has expired. + */ +extern int_fast16_t NVS_lock(NVS_Handle handle, uint32_t timeout); + +/*! + * @brief Open an NVS region for reading and writing. + * + * @pre NVS_init() was called. + * + * @param index Index in the #NVS_Config table of the region + * to manage. + * + * @param params Pointer to a parameter region. If NULL, default + * parameter values will be used. + * + * @return A non-zero handle on success, else NULL. + */ +extern NVS_Handle NVS_open(uint_least8_t index, NVS_Params *params); + +/*! + * @brief Function to initialize the NVS_Params struct to its defaults + * + * @param params A pointer to NVS_Params structure for + * initialization. + */ +extern void NVS_Params_init(NVS_Params *params); + +/*! + * @brief Read data from the NVS region associated with the #NVS_Handle. + * + * @param handle A handle returned from NVS_open() + * + * @param offset The byte offset into the NVS region to start + * reading from. + * + * @param buffer A buffer to copy the data to. + * + * @param bufferSize The size of the buffer (number of bytes to read). + * + * @retval #NVS_STATUS_SUCCESS Success. + * @retval #NVS_STATUS_INV_OFFSET If @p offset + @p size exceed the size + * of the region. + */ +extern int_fast16_t NVS_read(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize); + +/*! + * @brief Function to unlock the NVS driver + * + * This function allows NVS write and erase operations to proceed after being + * temporarily inhibited by a call to NVS_lock(). + * + * @param handle A handle returned from NVS_open() + */ +extern void NVS_unlock(NVS_Handle handle); + +/*! + * @brief Write data to the NVS region associated with the #NVS_Handle. + * + * @warning Writing to internal flash on most devices can introduce + * significant interrupt latencies while the write operation is in + * in progress. The user may want to surround certain real-time + * critical code sections with NVS_lock() and NVS_unlock() calls in order + * to prevent uncoordinated flash write operations from negatively + * impacting performance. + * + * @param handle A handle returned from NVS_open() + * + * @param offset The byte offset into the NVS region to start + * writing. + * + * @param buffer A buffer containing data to write to + * the NVS region. + * + * @param bufferSize The size of the buffer (number of bytes to write). + * + * @param flags Write flags (#NVS_WRITE_ERASE, #NVS_WRITE_PRE_VERIFY, + * #NVS_WRITE_POST_VERIFY). + * + * @retval #NVS_STATUS_SUCCESS Success. + * @retval #NVS_STATUS_ERROR If the internal flash write operation + * failed, or if #NVS_WRITE_POST_VERIFY + * was requested and the destination flash + * range does not match the source + * @p buffer data. + * @retval #NVS_STATUS_INV_OFFSET If @p offset + @p size exceed the size + * of the region. + * @retval #NVS_STATUS_INV_WRITE If #NVS_WRITE_PRE_VERIFY is requested + * and the destination flash address range + * cannot be change to the values desired. + * @retval #NVS_STATUS_INV_ALIGNMENT If #NVS_WRITE_ERASE is requested + * and @p offset is not aligned on + * a sector boundary + * + * @remark This call may lock a region to ensure atomic access to the region. + */ +extern int_fast16_t NVS_write(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize, uint_fast16_t flags); + +#if defined (__cplusplus) +} +#endif /* defined (__cplusplus) */ + +/*@}*/ +#endif /* ti_drivers_NVS__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PIN.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PIN.h new file mode 100644 index 0000000..a59460a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PIN.h @@ -0,0 +1,1079 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!***************************************************************************** + * @file PIN.h + * @brief Generic PIN & GPIO driver + * + * To use the PIN driver ensure that the correct TI-RTOS driver library for your + * device is linked in and include this header file: + * @code + * #include + * @endcode + * + * In order to use device-specific functionality or to use the size/speed- + * optimized versions of some of the PIN driver functions that circumvent error + * and resource checking, link in the correct TI-RTOS driver library for your + * device and include the device-specific PIN driver header file (which in turn + * includes PIN.h). As an example for the CC26xx family of devices: + * @code + * #include + * @endcode + * + * # Overview # + * The PIN driver allows clients (applications or other drivers) to allocate + * and control the I/O pins on the device. The pins can either be software- + * controlled general-purpose I/O (GPIO) or connected to hardware peripherals. + * Furthermore, the PIN driver allows clients to configure interrupt + * functionality on the pins to receive callbacks (and potentially wake up from + * the standby or idle power modes) on configurable signal edges. + * + * Most other drivers rely on functionality in the PIN driver. + * + * ## Structure ## + * In order to provide a generic driver interface, this file (PIN.h) only + * defines the API and some common data types and macros of the driver. A PIN + * client (application or driver) can in most cases only use the generic PIN + * API, however, for more advanced usage where device-specific pin + * configuration is used or device-specific PIN driver API extensions are + * used must use the device-specific PIN driver API. + * + * The device-independent API is implemented as function calls with pin + * access control based on the PIN client handle. For time-critical + * applications the device-specific API can be used directly, as these + * API functions are implemented as inlined functions without access control. + * + * ## Functionality ## + * The PIN module provides the following functionality: + * - Initialize I/O pins upon boot to a default configuration (possibly + * user-generated) + * - Provides atomic manipulation of I/O pin hardware registers to allow safe + * simultaneous use of I/O pin resources + * - I/O pin allocation + * - A set of pins can be allocated receiving a pin set handle. + * Typically each peripheral driver will allocate a set of pins and an + * application must allocate the pins it uses too + * - When a pin set is deallocated all the pins in it revert to the state + * they were initialized to at boot + * - General-purpose I/O (GPIO) services + * - Read input buffer value + * - Read and set output buffer value + * - Read and set output buffer enable + * - Access as single pin or port (muliple pins simultaneously) + * - Protect pin manipulation + * - Pins in an allocated set can only be manipulated using the corresponding + * handle. + * - No handle is needed to read input and output buffer values + * - I/O buffer/driver control + * - Input mode (detached, hysteresis, pull-up, pull-down) + * - Output mode (tristated, push-pull, open drain, open source) + * - Output driver strength control + * - Output driver slew rate control + * - I/O source/target selection (device-specific driver only) + * - Map pin to GPIO, peripheral or HW observation signal + * - Configuration of I/O interrupt and wakeup from standby + * - Interrupt configuration: signal edge to interrupt on, interrupt mask, + * callback function registration + * - Pins that have enabled interrupts will also wake up the device from low- + * power modes like standby and idle upon events + * - Provides data types and enums/defines for use in pin configurations + * definitions in board files, drivers and applications + * + * ## Pin Allocation ## + * The purpose of being able to allocate pins to a pin set is to: + * - Manage pin resources + * - Give exclusive, protected access to these pins + * - Establish a driver state in connection with these pins that allow + * functionality such as I/O interrupt callback and I/O port operations + * in a safe manner + * + * | API function | Description | + * |--------------------|------------------------------------------------------| + * | PIN_open() | Allocate pins to a set, returns handle | + * | PIN_add() | Add pin to pin set for open PIN handle | + * | PIN_remove() | Removes pin from pin set for open PIN handle | + * | PIN_close() | Deallocate pin set, revert to original GPIO state | + * + * ## GPIO ## + * Pins that are to be used as software-controlled general-purpose I/O (GPIO) + * need to be allocated in the same manner as for pins that will be mapped to + * hardware peripheral ports. A pin set requested with a PIN_open() call may + * contain a mix of pins to be used for GPIO and hardware-mapped pins. + * + * When a pin is deallocated using PIN_close() it reverts to the GPIO + * configuration it was given in the initial call to PIN_init(). + * + * | API function | Description | + * |----------------------|---------------------------------------------------| + * | PIN_init() | Initialize I/O pins to a safe GPIO state | + * | PIN_open() | Allocate pins to a set, returns handle | + * | PIN_close() | Deallocate pin set, revert to original GPIO state | + * | PIN_setConfig() | Sets parts of or complete pin configuration | + * | PIN_getConfig() | Returns pin configuration | + * | PIN_setOutputEnable()| Control output enable of GPIO pin | + * | PIN_getInputValue() | Read input value on pin | + * | PIN_setOutputValue() | Set output value of GPIO pin | + * | PIN_getOutputValue() | Get current output value of GPIO pin | + * + * ## GPIO Ports ## + * Sometimes it is necessary to be able to read from, write to or control + * multiple pins simultaneously (in time). The PIN driver allows a set of + * allocated pins, if they reside on the same GPIO port in the underlying + * hardware, to be manipulated simultaneously. + * + * | API function | Description | + * |--------------------------|---------------------------------------------------| + * | PIN_open() | Allocate pins to a set, returns handle | + * | PIN_close() | Deallocate pin set, revert to original GPIO state | + * | PIN_getPortMask() | Returns bitmask for allocated pins in GPIO port | + * | PIN_getPortInputValue() | Returns input value of whole GPIO port | + * | PIN_setPortOutputValue() | Sets output value of whole GPIO port (masked) | + * | PIN_getPortOutputValue() | Get current output value of whole GPIO port | + * | PIN_setPortOutputValue() | Sets output value of whole GPIO port (masked) | + * | PIN_setPortOutputEnable()| Sets output enable of whole GPIO port (masked) | + * + * ## I/O Pin Configuration ## + * Different devices provide different levels of configurability of I/O pins. + * The PIN driver provides a fairly extensive set of @ref PIN_GENERIC_FLAGS + * "generic IO configuration options" that are device-independent, all of which + * might not be supported by the underlying device-specific PIN driver and + * hardware. Likewise, the underlying device-specific PIN driver and hardware + * might support additional configuration options not covered by the generic + * options. + * + * To allow both independence from and flexibility to use features on the target + * device, the #PIN_Config entries used by the PIN driver allows use of either + * a set of @ref PIN_GENERIC_FLAGS "generic PIN configuration options" or a + * device-specific set of PIN configuration options defined in the underlying + * device-specific PIN driver (e.g. PINCC26XX.h) + * + * ### Mapping to GPIO or Peripheral ### + * Since the amount of flexibilty in which peripherals can be mapped to which + * pins and the manner in which this needs to be set up is highly + * device-specific, functions for configuring this is not part of the generic + * PIN driver API but is left to be implemented by device-specific PIN drivers. + * See the relevant device-specific PIN driver (e.g. PINCC26XX.h) for details. + * + * ### Input Mode ### + * The input mode of a pin controls: + * - Input buffer enable + * - Pull-ups or pull-downs + * - Hysteresis of input buffer + * - Inversion of logical input level + * - Potentially, device-specific options + * The input mode is set initially with PIN_init() or at a later stage with + * PIN_setConfig() and a bitmask with the relevant options + * + * | API function | Description | + * |------------------|-------------------------------------------------------| + * | PIN_init() | Initialize IOs to a safe GPIO state | + * | PIN_getConfig() | Returns pin configuration | + * | PIN_setConfig() | Sets parts of or complete pin configuration | + * + * ### Output Mode ### + * The output mode of a pin controls: + * - Output buffer enable + * - Output driver mode (push-pull, open-drain, open-source) + * - Output driver slew control + * - Output driver current (drive strength) + * - Inversion of logical output level + * - Potentially, device-specific options + * + * | API function | Description | + * |----------------------|---------------------------------------------------| + * | PIN_init() | Initialize IOs to a safe GPIO state | + * | PIN_setOutputEnable()| Control output enable of GPIO pins | + * | PIN_getConfig() | Returns pin configuration | + * | PIN_setConfig() | Sets parts of or complete pin configuration | + * + * ### Pin Interrupt and Pin Wakeup ### + * Pin interrupts are used to process asynchronous signal edge events on pins + * and potentially wake the device up from low power sleep modes. To use pin + * interrupts the relevant pins must be allocated and a interrupt callback + * registered by the client. The callback function will be called in a SWI + * context. + * + * | API function | Description | + * |---------------------|----------------------------------------------------| + * | PIN_init() | Initialize IOs to a safe GPIO state | + * | PIN_getConfig() | Returns pin configuration | + * | PIN_setConfig() | Sets parts of or complete pin configuration | + * | PIN_setInterrupt() | Control interrupt enable and edge for pin | + * | PIN_registerIntCb() | Register callback function for a set of pins | + * | PIN_setUserArg() | Sets a user argument associated with the handle | + * | PIN_getUserArg() | Gets a user argument associated with the handle | + * + * ## PIN Data Types ## + * The PIN driver defines the following data types: + * - #PIN_Id: identifies a pin in arguments or lists + * - #PIN_Config: provides I/O configuration options for a pin and also embeds + * a #PIN_Id identifier. See @ref PIN_GENERIC_FLAGS "available flags/fields" + * + * ## PIN Config Flags/Fields and Bitmasks ## + * The PIN driver uses the #PIN_Config data type many places and it merits some + * additional attention. A #PIN_Config value consists of a collection of flags + * and fields that define how an I/O pin and its attached GPIO interface should + * behave electrically and logically. In addition a #PIN_Config value also + * embeds a #PIN_Id pin ID, identifying which pin it refers to. + * + * A #PIN_Config value can use one of two mutually exclusive sets of flags and + * fields: @ref PIN_GENERIC_FLAGS "device-independent options" defined in + * PIN.h or device-dependent options defined in the device-specific + * implementation of the PIN driver interface. Any function that uses + * #PIN_Config will accept both option types, just not at the same time. + * PIN_getConfig() always returns device-independent options, an additional + * device-specific version (e.g. PINCC26XX_getConfig()) might return + * device-specific options. + * + * The bitmask argument for PIN_setConfig() decides which of the options the + * call should affect. All other options are kept at their current values in + * hardware. Thus PIN_setConfig(hPins, PIN_BM_PULLING, PIN_BM_PULLUP) will only + * change the pullup/pulldown configuration of the pin, leaving everything + * else, such as for instance output enable, input hysteresis or output value, + * untouched. For #PIN_Config lists (as supplied to PIN_init() for instance) + * there is no mask, so all options will affect the pin. + * + * Some of the options affect the pin regardless of whether it is mapped to + * a hardware peripheral or GPIO and some options only take effect when it is + * mapped to GPIO. These latter options have \_GPIO_ in their names. + * + * The default value for a flag/field is indicated with a star (*) in the + * description of the options and will be applied if any explicit value is + * not supplied for a flag/field that is masked. + * + * The available options can be grouped into categories as follows: + * + * ### Input Mode Options ### + * | Option | Option bitmask | HW/GPIO | Description | + * |--------------------|-----------------------|---------|--------------------------------| + * |#PIN_INPUT_EN (*) |#PIN_BM_INPUT_EN | Both | Enable pin input buffer | + * |#PIN_INPUT_DIS |#PIN_BM_INPUT_EN | Both | Disable pin input buffer | + * |#PIN_HYSTERESIS |#PIN_BM_HYSTERESIS | Both | Enable hysteresis on input | + * |#PIN_NOPULL (*) |#PIN_BM_PULLING | Both | No pullup/pulldown | + * |#PIN_PULLUP |#PIN_BM_PULLING | Both | Enable pullup | + * |#PIN_PULLDOWN |#PIN_BM_PULLING | Both | Enable pulldown | + * | |#PIN_BM_INPUT_MODE | | Mask for all input mode options| + * + * ### Output Mode Options ### + * | Option | Option bitmask | HW/GPIO | Description | + * |------------------------|------------------------|---------|----------------------------------| + * |#PIN_GPIO_OUTPUT_DIS (*)|#PIN_BM_GPIO_OUTPUT_EN | GPIO | Disable GPIO output buffer | + * |#PIN_GPIO_OUTPUT_EN |#PIN_BM_GPIO_OUTPUT_EN | GPIO | Enable GPIO output buffer | + * |#PIN_GPIO_LOW (*) |#PIN_BM_GPIO_OUTPUT_VAL | GPIO | Output 0 when GPIO | + * |#PIN_GPIO_HIGH |#PIN_BM_GPIO_OUTPUT_VAL | GPIO | Output 1 when GPIO | + * |#PIN_PUSHPULL (*) |#PIN_BM_OUTPUT_BUF | Both | Use push-pull output buffer | + * |#PIN_OPENDRAIN |#PIN_BM_OUTPUT_BUF | Both | Use open drain output buffer | + * |#PIN_OPENSOURCE |#PIN_BM_OUTPUT_BUF | Both | Use open source output buffer | + * |#PIN_SLEWCTRL |#PIN_BM_SLEWCTRL | Both | Enable output buffer slew control| + * |#PIN_DRVSTR_MIN (*) |#PIN_BM_DRVSTR | Both | Output buffer uses min drive | + * |#PIN_DRVSTR_MED |#PIN_BM_DRVSTR | Both | Output buffer uses medium drive | + * |#PIN_DRVSTR_MAX |#PIN_BM_DRVSTR | Both | Output buffer uses max drive | + * | |#PIN_BM_OUTPUT_MODE | | Mask for all output mode options | + * + * ### Misc Options ### + * | Option | Option bitmask | HW/GPIO | Description | + * |-------------------|------------------|---------|----------------------------------| + * |#PIN_INV_INOUT |#PIN_BM_INV_INOUT | Both | Invert input/output | + * |#PIN_IRQ_DIS (*) |#PIN_BM_IRQ | Both | Disable pin interrupts | + * |#PIN_IRQ_NEGEDGE |#PIN_BM_IRQ | Both | Pin interrupts on negative edges | + * |#PIN_IRQ_POSEDGE |#PIN_BM_IRQ | Both | Pin interrupts on negative edges | + * |#PIN_IRQ_BOTHEDGES |#PIN_BM_IRQ | Both | Pin interrupts on both edges | + * | |#PIN_BM_ALL | | Mask for *all* options | + * + * ## Initialization ## + * The PIN driver must be initialized before any other drivers are initialized. + * In order for IO pins to get a safe value as soon as possible PIN_init() + * should be called as early as possible in the boot sequence. Typically, + * PIN_init() is called at the start of main() before TI-RTOS is started with + * BIOS_start(). + * + * PIN_init() takes as an argument a #PIN_Config list containing default pin + * configurations. Typically the #PIN_Config list defined in the board files + * is used: + * @code + * PIN_init(BoardGpioInitTable); + * @endcode + * It is possible, however, to use another #PIN_Config list if desired. + * + * ## Power Management Interaction ## + * No specific interaction with power management module, as PIN is independent + * of power mode. + * + * ## Functionality Not Supported ## + * There is no known unsupported functionality. + * + * ## Instrumentation ## + * The pin driver does not use any of the instrumentation facilities. + * + * # Usage Examples # + * + * ## Initialization and Pin Allocation ## + * Example that illustrates when and how to call PIN_init(), PIN_open(), PIN_add(), PIN_close() + * @code + * // Default pin configuration. Typically resides in Board.c file. + * // IOs not mentioned here configured to default: input/output/pull disabled + * PIN_Config BoardGpioInitTable[] = { + * // DIO11: LED A (initially off) + * PIN_ID(11) | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_DRVSTR_MAX, + * // DIO10: LED B (initially off) + * PIN_ID(10) | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_DRVSTR_MAX, + * // DIO23: BUTTON A (ensure pull-up as button A is also used by other ICs) + * PIN_ID(23) | PIN_INPUT_EN | PIN_PULLUP | PIN_HYSTERESIS, + * // DIO3: LCD controller reset line (make sure LCD is in reset) + * PIN_ID(3) | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL, + * // Terminate list + * PIN_TERMINATE + * }; + * + * //Stack size in bytes + * #define THREADSTACKSIZE 1024 + * + * // PIN_init() should be called as early as possible in boot + * void main() { + * + * pthread_t thread; + * pthread_attr_t attrs; + * struct sched_param priParam; + * int retc; + * int detachState; + * + * //Board_initGeneral() will call PIN_init(BoardGpioInitTable) + * Board_initGeneral(); + * + * // Set priority and stack size attributes + * pthread_attr_init(&attrs); + * priParam.sched_priority = 1; + * + * detachState = PTHREAD_CREATE_DETACHED; + * retc = pthread_attr_setdetachstate(&attrs, detachState); + * if (retc != 0) { + * // pthread_attr_setdetachstate() failed + * while (1); + * } + * + * pthread_attr_setschedparam(&attrs, &priParam); + * + * retc |= pthread_attr_setstacksize(&attrs, THREADSTACKSIZE); + * if (retc != 0) { + * // pthread_attr_setstacksize() failed + * while (1); + * } + * + * retc = pthread_create(&thread, &attrs, mainThread, NULL); + * if (retc != 0) { + * // pthread_create() failed + * while (1); + * } + * + * // Start kernel + * Add_Kernel_Start_Call(); + * + * return (0); + * } + * + * // Human user interface PIN state/handle + * PIN_State hStateHui; + * #define HUI_LED_A PIN_ID(11) + * #define HUI_LED_B PIN_ID(10) + * #define HUI_LED_C PIN_ID(9) + * #define HUI_BUTTON_A PIN_ID(23) + * #define HUI_BUTTON_B PIN_ID(24) + * + * static void taskStartFxn(UArg a0, UArg a1) { + * // Define pins used by Human user interface and initial configuration + * const PIN_Config pinListHui[] = { + * HUI_LED_A | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_DRVSTR_MAX, + * HUI_LED_B | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_DRVSTR_MAX, + * HUI_BUTTON_A | PIN_INPUT_EN | PIN_PULLUP | PIN_HYSTERESIS, + * HUI_BUTTON_B | PIN_INPUT_EN | PIN_PULLUP | PIN_HYSTERESIS, + * PIN_TERMINATE + * }; + * + * // Get handle to this collection of pins + * if (!PIN_open(&hStateHui, pinListHui)) { + * // Handle allocation error + * } + * + * // ... + * + * // We can also add (and remove) pins to a set at run time + * PIN_Status status = PIN_add( + * &hStateHui, + * HUI_LED_C | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_DRVSTR_MAX, + * ); + * if (status != PIN_SUCCESS) { + * // Handling allocation error is especially important with PIN_add() + * } + * + * // ... + * huiDoSomething(); + * + * // Before ending task, make sure to deallocate pins. They will return + * // to the default configurations provided in PIN_init() + * PIN_close(&hStateHui); + * } + * @endcode + * + * ## Application use of GPIO ## + * An example of using GPIO that builds on the previous example. Illustrates how + * to read input values, set output values and control output enable + * @code + * void huiDoSomething() { + * // Running lights on LEDs A-B-C (left to right). Button A causes left + * // movement, button B causes right movement, both simultaneously aborts + * // and disables LED output drivers + * + * // LED initial state (A off, B off, C on). Only our outputs are affected + * PIN_setPortOutputValue(&hStateHui, (1<0 right + * while (moveDir) { + * // Update LEDs + * if (moveDir<0) { + * // Left movement + * uint32_t t = PIN_getOutputValue(HUI_LED_A); + * PIN_setOutputValue(&hStateHui, HUI_LED_A, PIN_getOutputValue(HUI_LED_B)); + * PIN_setOutputValue(&hStateHui, HUI_LED_B, PIN_getOutputValue(HUI_LED_C)); + * PIN_setOutputValue(&hStateHui, HUI_LED_C, t); + * } else { + * // Right movement + * uint32_t t = PIN_getOutputValue(HUI_LED_C); + * PIN_setOutputValue(&hStateHui, HUI_LED_C, PIN_getOutputValue(HUI_LED_B)); + * PIN_setOutputValue(&hStateHui, HUI_LED_B, PIN_getOutputValue(HUI_LED_A)); + * PIN_setOutputValue(&hStateHui, HUI_LED_A, t); + * } + * + * // Sleep for 333 ms + * Task_sleep(333000/10); + * + * // Read input from both buttons simultaneously + * uint32_t buttons = PIN_getPortInputValue(&hStateHui); + * if (buttons&(1<0 right + * + * // Pin interrupt callback + * void huiPinIntCb(PIN_Handle handle, PIN_Id pinId) { + * // Ignore pinId and read input from both buttons simultaneously + * uint32_t buttons = PIN_getPortInputValue(&hStateHui); + * if (buttons&(1<0 right + * + * // Setup pin interrupts and register callback + * PIN_registerIntCb(&hStateHui, huiPinIntCb); + * PIN_setInterrupt(&hStateHui, HUI_BUTTON_A | PIN_IRQ_NEGEDGE); + * PIN_setInterrupt(&hStateHui, HUI_BUTTON_B | PIN_IRQ_NEGEDGE); + * + * while (moveDir) { + * // Update LEDs + * if (moveDir<0) { + * // Left movement + * uint32_t t = PIN_getOutputValue(HUI_LED_A); + * PIN_setOutputValue(&hStateHui, HUI_LED_A, PIN_getOutputValue(HUI_LED_B)); + * PIN_setOutputValue(&hStateHui, HUI_LED_B, PIN_getOutputValue(HUI_LED_C)); + * PIN_setOutputValue(&hStateHui, HUI_LED_C, t); + * } else { + * // Right movement + * uint32_t t = PIN_getOutputValue(HUI_LED_C); + * PIN_setOutputValue(&hStateHui, HUI_LED_C, PIN_getOutputValue(HUI_LED_B)); + * PIN_setOutputValue(&hStateHui, HUI_LED_B, PIN_getOutputValue(HUI_LED_A)); + * PIN_setOutputValue(&hStateHui, HUI_LED_A, t); + * } + * + * // Sleep for 333 ms (we will likely go into standby) + * Task_sleep(333000/10); + * } + * // Disable output enable for all pins (only our pins affected) + * PIN_setPortOutputEnable(&hStateHui, 0); + * // Disable pin interrupts + * PIN_setInterrupt(&hStateHui, HUI_BUTTON_A | PIN_IRQ_DIS); + * PIN_setInterrupt(&hStateHui, HUI_BUTTON_B | PIN_IRQ_DIS); + * } + * @endcode + * + ******************************************************************************* + */ + +#ifndef ti_drivers_PIN__include +#define ti_drivers_PIN__include +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** @brief Pin identifier data type + * + * Data type used to identify a pin through an index between 0 to 254. + * Typically the index does not refer to the physical device pin number but + * rather to the index of the subset of pins that are under software-control + * (e.g. index 3 refers to DIO3). + * This data type is used as arguments in API functions to identify which pin + * is affected or used in lists (terminated by #PIN_TERMINATE entry) identifying + * multiple pins + * @sa PIN_ID + */ +typedef uint8_t PIN_Id; + +/// Pin ID used to indicate no pin +#define PIN_UNASSIGNED 0xFF +/// Pin ID used to terminate a list of PIN_Id or PIN_Config entries +#define PIN_TERMINATE 0xFE + +/** @brief Pin configuration data type with embedded pin identifier + * + * A data type used to specify I/O-pin configuration options. The lower 8b + * contain an embedded pin ID (see #PIN_Id) and the top 24b contain + * flags/fields that affect I/O configuration. #PIN_Config entries can either + * use a @ref PIN_GENERIC_FLAGS "set of device-independent options" or + * device-specific options defined in PIN driver (e.g. PINCC26XX.h), but cannot + * mix the two. + * + * This data type is used as arguments or return values in API functions that + * manipulate pin configuration or used in lists (terminated by a + * #PIN_TERMINATE entry) for configuring multiple pins at a time. + */ +typedef uint32_t PIN_Config; + +/** @brief Macro for inserting or extracting a #PIN_Id in a #PIN_Config entry + * @par Usage + * @code + * PIN_Config pinCfg = PIN_ID(5) | PIN_GPIO_OUTPUT_EN | PIN_PUSHPULL | + * PIN_GPIO_HIGH | PIN_IRQ_POSEDGE; + * PIN_setConfig(hPins, PIN_BM_OUTPUT_MODE, pinCfg); + * // Trigger IRQ + * PIN_setOutputValue(hPins, PIN_ID(pinCfg), 1); + * @endcode + */ +#define PIN_ID(x) ((x)&0xFF) + + +/** @anchor PIN_GENERIC_FLAGS + * @name Generic PIN_Config flags/fields + * Generic (i.e. not device-specific) fields/flags for I/O configuration for + * use in #PIN_Config entries. All of these generic options may not be + * supported by the underlying device-specific PIN driver. A #PIN_Config + * entry may use either these generic fields/flags or device-specific ones + * defined in the device-specific PIN-driver, but may not mix the two. + * + * The entries starting with PIN_BM_ are bitmasks used to extract individual + * fields obtained from PIN_getConfig() or to pass as a parameter to + * PIN_setConfig()to define which options it should set. + * + * A star (*) in the descriptions below means the default if no option is + * supplied. + * \{ + */ +#define PIN_GEN (((uint32_t)1) << 31) ///< Flags that generic options are used + +#define PIN_INPUT_EN (PIN_GEN | (0 << 29)) ///< (*) Enable input buffer +#define PIN_INPUT_DIS (PIN_GEN | (1 << 29)) ///< Disable input buffer +#define PIN_HYSTERESIS (PIN_GEN | (1 << 30)) ///< Enable input buffer hysteresis +#define PIN_NOPULL (PIN_GEN | (0 << 13)) ///< (*) No pull-up or pull-down resistor +#define PIN_PULLUP (PIN_GEN | (1 << 13)) ///< Pull-up resistor enabled +#define PIN_PULLDOWN (PIN_GEN | (2 << 13)) ///< Pull-down resistor enabled +#define PIN_BM_INPUT_EN (1 << 29) ///< Bitmask for input enable option +#define PIN_BM_HYSTERESIS (1 << 30) ///< Bitmask input hysteresis option +#define PIN_BM_PULLING (0x3 << 13) ///< Bitmask for pull-up/pull-down options + +/// Bitmask for all input mode options +#define PIN_BM_INPUT_MODE (PIN_BM_INPUT_EN|PIN_BM_HYSTERESIS|PIN_BM_PULLING) + +#define PIN_GPIO_OUTPUT_DIS (PIN_GEN | (0 << 23)) ///< (*) Disable output buffer when GPIO +#define PIN_GPIO_OUTPUT_EN (PIN_GEN | (1 << 23)) ///< Enable output buffer when GPIO +#define PIN_GPIO_LOW (PIN_GEN | (0 << 22)) ///< Output buffer drives to VSS when GPIO +#define PIN_GPIO_HIGH (PIN_GEN | (1 << 22)) ///< Output buffer drives to VDD when GPIO +#define PIN_PUSHPULL (PIN_GEN | (0 << 25)) ///< (*) Output buffer mode: push/pull +#define PIN_OPENDRAIN (PIN_GEN | (2 << 25)) ///< Output buffer mode: open drain +#define PIN_OPENSOURCE (PIN_GEN | (3 << 25)) ///< Output buffer mode: open source +#define PIN_SLEWCTRL (PIN_GEN | (1 << 12)) ///< Enable output buffer slew control +#define PIN_DRVSTR_MIN (PIN_GEN | (0x0 << 8)) ///< (*) Lowest drive strength +#define PIN_DRVSTR_MED (PIN_GEN | (0x4 << 8)) ///< Medium drive strength +#define PIN_DRVSTR_MAX (PIN_GEN | (0x8 << 8)) ///< Highest drive strength +#define PIN_BM_GPIO_OUTPUT_EN (1 << 23) ///< Bitmask for output enable option +#define PIN_BM_GPIO_OUTPUT_VAL (1 << 22) ///< Bitmask for output value option +#define PIN_BM_OUTPUT_BUF (0x3 << 25) ///< Bitmask for output buffer options +#define PIN_BM_SLEWCTRL (0x1 << 12) ///< Bitmask for slew control options +#define PIN_BM_DRVSTR (0xF << 8) ///< Bitmask for drive strength options + +/// Bitmask for all output mode options +#define PIN_BM_OUTPUT_MODE (PIN_BM_GPIO_OUTPUT_VAL | PIN_BM_GPIO_OUTPUT_EN | \ + PIN_BM_OUTPUT_BUF | PIN_BM_SLEWCTRL | PIN_BM_DRVSTR) + +#define PIN_INV_INOUT (PIN_GEN | (1 << 24)) ///< Logically invert input and output +#define PIN_BM_INV_INOUT (1 << 24) ///< Bitmask for input/output inversion option + +#define PIN_IRQ_DIS (PIN_GEN | (0x0 << 16)) ///< (*) Disable IRQ on pin +#define PIN_IRQ_NEGEDGE (PIN_GEN | (0x5 << 16)) ///< Enable IRQ on negative edge +#define PIN_IRQ_POSEDGE (PIN_GEN | (0x6 << 16)) ///< Enable IRQ on positive edge +#define PIN_IRQ_BOTHEDGES (PIN_GEN | (0x7 << 16)) ///< Enable IRQ on both edges +#define PIN_BM_IRQ (0x7 << 16) ///< Bitmask for pin interrupt option + +/// Bitmask for all options at once +#define PIN_BM_ALL (PIN_BM_INPUT_MODE | PIN_BM_OUTPUT_MODE | PIN_BM_INV_INOUT | PIN_BM_IRQ) +/** \} (PIN_GENERIC_FLAGS) + */ + + +/** @brief Struct used to store PIN client state + * Pointer to a PIN_State is used as handles (#PIN_Handle) in interactions with + * the I/O driver + * @note Must reside in persistent memory + * @note Fields must never be modified directly + */ +typedef struct PIN_State_s PIN_State; + + +/** @brief A handle that is returned from a PIN_open() call + * Used for further PIN client interaction with the PIN driver + */ +typedef PIN_State *PIN_Handle; + + +/** @brief I/O Interrupt callback function pointer type + * One PIN Interrupt callback can be registered by each PIN client and it + * will be called when one of the pins allocated by the client has an interrupt + * event. The callback is called from HWI context with handle and pin ID as + * arguments. + * @remark The callback must, as it runs in HWI context, execute and return + * quickly. Any lengthy operations should be performed in SWIs or tasks + * triggered by the callback + */ +typedef void (*PIN_IntCb)(PIN_Handle handle, PIN_Id pinId); + + +/** @brief underlying data structure for type #PIN_State + */ +struct PIN_State_s { + PIN_IntCb callbackFxn; ///< Pointer to interrupt callback function + uint32_t portMask; ///< Bitmask for pins allocated in port + uintptr_t userArg; ///< User argument for whole handle + // TODO: add driver-specific field for extensions? +}; + +/// @brief Return value for many functions in the PIN driver interface +typedef enum { + PIN_SUCCESS = 0, ///< Operation succeeded + PIN_ALREADY_ALLOCATED = 1, ///< Operation failed, some pin already allocated + PIN_NO_ACCESS = 2, ///< Operation failed, client does not have access to pin + PIN_UNSUPPORTED = 3 ///< Operation not supported +} PIN_Status; + + +/** @brief PIN module initialization + * + * Must be called early in the boot sequence to ensure that I/O pins have safe + * configurations. This initialization sets up pins as GPIO as defined in an + * array (possibly user-generated) that typically resides in a board file. All + * pins not mentioned in aPinCfg[] are configured to be input/output/pull + * disabled. + * + * @note Function *cannot* be called more than once. + * + * @param aPinCfg[] Pointer to array of PIN_Config entries, one per pin + * that needs configuration. List terminates when a + * #PIN_TERMINATE entry is encountered. + * @return #PIN_SUCCESS if successful, else an error code. + */ +extern PIN_Status PIN_init(const PIN_Config aPinCfg[]); + + +/** @brief Allocate one or more pins for a driver or an application + * + * Allows a PIN client (driver or application) to allocate a set of pins, thus + * ensuring that they cannot be reconfigured/controlled by anyone else. The + * pins are identified by and reconfigured according to the #PIN_Config + * entries in pinList. + * + * @param state Pointer to a PIN_State object that will hold the state for + * this IO client. The object must be in persistent memory + * @param pinList[] Pointer to array of #PIN_Config entries, one per pin to + * allocate. List terminates when #PIN_TERMINATE entry is + * encountered. + * @return A handle for further PIN driver calls or NULL if an error occurred + * (already allocated pin in pinList or non-existent pin in pinList) + */ +extern PIN_Handle PIN_open(PIN_State *state, const PIN_Config pinList[]); + + +/** @brief Add pin to pin set for open PIN handle + * + * If the requested pin is unallocated it will be added, else an error code + * will be returned. + * @param handle handle retrieved through an earlier call to PIN_open(). + * @param pinCfg Pin ID/configuration for pin to add. + * @return Error code if unsuccessful, else PIN_SUCCESS + */ +extern PIN_Status PIN_add(PIN_Handle handle, PIN_Config pinCfg); + + +/** @brief Removes pin from pin set foropen PIN handle + * + * If the requested pin is allocated to handle it will be removed from the pin + * set, else an error code will be returned. + * @param handle handle retrieved through an earlier call to PIN_open(). + * @param pinId Pin ID for pin to remove. + * @return Error code if unsuccessful, else PIN_SUCCESS + */ +extern PIN_Status PIN_remove(PIN_Handle handle, PIN_Id pinId); + + +/** @brief Deallocate all pins previously allocated with a call to PIN_open(). + * + * Deallocate pins allocated to handle and restore these pins to the + * pool of unallocated pins. Also restores the pin configuration to what it was + * set to when PIN_init() was called. + * @param handle handle retrieved through an earlier call to PIN_open(). + */ +extern void PIN_close(PIN_Handle handle); + + +/** @brief Sets a user argument associated with the handle + * + * Allows the application to store some data, for example a pointer to some + * data structure, with each PIN handle + * @param handle handle retrieved through an earlier call to PIN_open(). + * @param arg User argument + */ +static inline void PIN_setUserArg(PIN_Handle handle, uintptr_t arg) { + if (handle) { + handle->userArg = arg; + } +} + + +/** @brief Gets a user argument associated with the handle + * + * Allows the application to store some data, for example a pointer to some + * data structure, with each PIN handle + * @param handle handle retrieved through an earlier call to PIN_open(). + * @return User argument. Has the value 0 if never initialized + */ +static inline uintptr_t PIN_getUserArg(PIN_Handle handle) { + return handle->userArg; +} + + +/** @name Pin Manipulation/Configuration Functions + * Functions that are used to manipulate the configuration of I/O pins and to + * get input values and set output values. + * \{ + */ + +/** @brief Get pin input value (0/1) + * + * Input values of all pins are available to everyone so no handle required + * @param pinId ID of pin to get input value from + * @return Current input buffer value + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + * @par Usage + * @code + * myPin = PIN_getInputValue(PIN_ID(5)); + * @endcode + */ +extern uint32_t PIN_getInputValue(PIN_Id pinId); + + +/** @brief Control output enable for GPIO pin + * + * @param handle Handle provided by previous call to PIN_open() + * @param pinId #PIN_Id entry identifying pin + * @param outputEnable Enable output buffer when true, else disable + * @return #PIN_SUCCESS if successful, else error code + * @remark This function is included for consistency with the corresponding + * port function and to provide a more efficient/directed approach. + * PIN_setConfig() can be used to achieve same result. + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + * @par Usage + * @code + * PIN_setOutputEnable(hPins, PIN_ID(11), 0); + * @endcode + */ +extern PIN_Status PIN_setOutputEnable(PIN_Handle handle, PIN_Id pinId, bool outputEnable); + + +/** @brief Control output value for GPIO pin + * + * @param handle Handle provided by previous call to PIN_open() + * @param pinId Pin ID + * @param val Output value (0/1) + * @return #PIN_SUCCESS if successful, else error code + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + * @par Usage + * @code + * PIN_setOutputValue(hPins, PIN_ID(4), 1); + * @endcode + */ +extern PIN_Status PIN_setOutputValue(PIN_Handle handle, PIN_Id pinId, uint32_t val); + + +/** @brief Get value of GPIO pin output buffer + * + * Output values of all pins are available to everyone so no handle required + * @param pinId Pin ID + * @return Output value (0/1) + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + * @par Usage + * @code + * PIN_setOutputValue(hpins, PIN_ID(4), PIN_getOutputValue(PIN_ID(6))); + * @endcode + */ +extern uint32_t PIN_getOutputValue(PIN_Id pinId); + + +/** @brief Control interrupt enable and edge for pin + * + * @param handle Handle provided by previous call to PIN_open() + * @param pinCfg #PIN_Config entry identifying pin ID and relevant pin + * configuration as combinations of: + * - #PIN_IRQ_DIS (default) + * - #PIN_IRQ_POSEDGE + * - #PIN_IRQ_NEGEDGE + * - #PIN_IRQ_BOTHEDGES + * @return #PIN_SUCCESS if successful, else error code + * @note Any pending interrupts on pins that have not had interrupt enabled + * will be cleared when enabling interrupts + * @par Usage + * @code + * PIN_setInterrupt(hPins, PIN_ID(8)|PIN_IRQ_POSEDGE); + * @endcode + */ +extern PIN_Status PIN_setInterrupt(PIN_Handle handle, PIN_Config pinCfg); + + +/** @brief Clear pending interrupt for pin, if any + * + * @param handle Handle provided by previous call to PIN_open() + * @param pinId #PIN_Id for pin to clear pending interrupt for + * @return #PIN_SUCCESS if successful, else error code + * @par Usage + * @code + * PIN_ClrPendInterrupt(hPins, PIN_ID(8)); + * @endcode + */ +extern PIN_Status PIN_clrPendInterrupt(PIN_Handle handle, PIN_Id pinId); + + +/** @brief Register callback function for a set of pins + * + * Registers a callback function (see #PIN_IntCb for details) for the client + * identified by handle that will be called from HWI context upon an interrupt + * event on one or more of the allocated pins that have interrupts enabled + * @param handle Handle provided by previous call to PIN_open() + * @param callbackFxn Function pointer to a #PIN_IntCb function. + * @return #PIN_SUCCESS if successful, else error code + * @note Pin interrupts are serviced one at a time in pin order when + * simultaneous. Pin hardware interrupt flags are automatically cleared + * by PIN driver. + * @par Usage + * @code + * void pinIntHandler(PIN_Handle handle, PIN_Id pinId) { + * // Handle pin interrupt + * } + * ... + * PIN_registerIntCb(hPins, pinIntHandler); + * @endcode + */ +extern PIN_Status PIN_registerIntCb(PIN_Handle handle, PIN_IntCb callbackFxn); + + + +/** @brief Returns pin configuration + * + * @param pinId Pin ID + * @return Current pin configuration as a device-independent #PIN_Config + * value + * @note The pin ID is embedded in return value. + * @note There is usually a device-specific version of this function that + * returns device-specific options + * @par Usage + * @code + * // Get config of pin 14 to be able to revert later + * myPinConfig = PIN_getConfig(PIN_ID(14)); + * // ... + * // Lots of pin reconfigurations + * // ... + * // Restore previous configuration + * PIN_setConfig(hPins, PIN_BM_ALL, myPinConfig); + * @endcode + */ +extern PIN_Config PIN_getConfig(PIN_Id pinId); + + +/** @brief Sets complete pin configuration + * + * @param handle Handle provided by previous call to PIN_open() + * @param updateMask Bitmask specifying which fields in cfg that should take + * effect, the rest keep their current value. + * @param pinCfg #PIN_Config entry with pin ID and pin configuration + * @return #PIN_SUCCESS if successful, else error code + * @par Usage + * @code + * // Set drive strength on pin 15 + * PIN_setConfig(hPins, PIN_BM_DRVSTR, PIN_ID(15)|PIN_DRVSTR_MAX); + * @endcode + */ +extern PIN_Status PIN_setConfig(PIN_Handle handle, PIN_Config updateMask, PIN_Config pinCfg); + + +/** \} (IO Manipulation/Configuration Functions) + */ + + +/** @name IO Port Functions + * Functions used to get input values for, set ouput values for and set output + * enables for multiple pins at a time. The size of so-called I/O ports that + * allows such multiple-pin operations are highly device dependent. In order to + * use the I/O port functions a set of pins that reside in the same I/O port + * must have been allocated previously with PIN_open(). + * \{ + */ + + +/** @brief Returns bitmask indicating pins allocated to client in GPIO port + * + * @param handle Handle provided by previous call to PIN_open() + * @return A bitmask indicating which bit positions in an I/O port the + * allocated I/O pins lie on, or zero if I/O port operations are not + * supported or the allocated pins span multiple I/O ports. The + * bitmask maps lowest pin index to the rightmost mask bit + */ +extern uint32_t PIN_getPortMask(PIN_Handle handle); + + +/** @brief Read input value of whole GPIO port + * + * @param handle Handle provided by previous call to PIN_open() + * @return The simultaneous input value for the whole I/O port masked by the + * bit mask for the client's allocated pins + * @sa PIN_getPortMask() + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + */ +extern uint32_t PIN_getPortInputValue(PIN_Handle handle); + + +/** @brief Returns value of whole GPIO port's output buffers + * + * The I/O port is identified by the pins allocated by client in a previous + * call to PIN_open() + * @param handle Handle provided by previous call to PIN_open() + * @return The current output value for whole I/O port + * @sa PIN_getPortMask() + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + */ +extern uint32_t PIN_getPortOutputValue(PIN_Handle handle); + + +/** @brief Simultaneous write output buffer values of all allocated pins in GPIO port + * + * @param handle Handle provided by previous call to PIN_open() + * @param outputValueMask Bitmask indicating the desired output value for the whole + * port, only the pins allocated to the client will be + * affected + * @return #PIN_SUCCESS if successful, else error code + * @sa PIN_getPortMask() + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + * @par Usage + * @code + * // Invert all pins allocated to client + * PIN_setPortOutputVal(hPins, ~PIN_getPortOutputVals(hPins)); + * @endcode + */ +extern PIN_Status PIN_setPortOutputValue(PIN_Handle handle, uint32_t outputValueMask); + + +/** @brief Set output enable for all pins allocated to client in GPIO port + * + * @param handle Handle provided by previous call to PIN_open() + * @param outputEnableMask Bitmask indicating the desired output enable configuration + * for the whole port, only the pins allocated to the client + * will be affected + * @return #PIN_SUCCESS if successful, else error code + * @sa PIN_getPortMask() + * @remark This function typically has an inlined sibling function in the + * device-specific driver that may be used for higher efficiency + * @par Usage + * @code + * // Set output to 0 on all allocated pins, then enable the output drivers + * pin_setPortOutputVal(hPins, 0); + * pin_setPortOutputEnable(hPins, PIN_getPortMask()); + * @endcode + */ +extern PIN_Status PIN_setPortOutputEnable(PIN_Handle handle, uint32_t outputEnableMask); + + +/** \} (IO Port Functions) + */ + +#ifdef __cplusplus +} +#endif +#endif /* ti_drivers_PIN__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PWM.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PWM.c new file mode 100644 index 0000000..373a330 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PWM.c @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PWM.c ======== + */ + +#include +#include +#include + +#include +#include + +extern const PWM_Config PWM_config[]; +extern const uint_least8_t PWM_count; + +/* Default PWM parameters structure */ +const PWM_Params PWM_defaultParams = { + .periodUnits = PWM_PERIOD_HZ, /* Period is defined in Hz */ + .periodValue = 1e6, /* 1MHz */ + .dutyUnits = PWM_DUTY_FRACTION, /* Duty is fraction of period */ + .dutyValue = 0, /* 0% duty cycle */ + .idleLevel = PWM_IDLE_LOW, /* Low idle level */ + .custom = NULL /* No custom params */ +}; + +static bool isInitialized = false; + +/* + * ======== PWM_close ======== + */ +void PWM_close(PWM_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== PWM_control ======== + */ +int_fast16_t PWM_control(PWM_Handle handle, uint_fast16_t cmd, void *arg) +{ + return handle->fxnTablePtr->controlFxn(handle, cmd, arg); +} + +/* + * ======== PWM_init ======== + */ +void PWM_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + + key = HwiP_disable(); + + if (!isInitialized) { + isInitialized = (bool) true; + + /* Call each driver's init function */ + for (i = 0; i < PWM_count; i++) { + PWM_config[i].fxnTablePtr->initFxn((PWM_Handle) &(PWM_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== PWM_open ======== + */ +PWM_Handle PWM_open(uint_least8_t index, PWM_Params *params) +{ + PWM_Handle handle = NULL; + + if (isInitialized && (index < PWM_count)) { + /* If params are NULL use defaults */ + if (params == NULL) { + params = (PWM_Params *) &PWM_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (PWM_Handle) &(PWM_config[index]); + + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== PWM_Params_init ======== + */ +void PWM_Params_init(PWM_Params *params) +{ + *params = PWM_defaultParams; +} + +/* + * ======== PWM_setDuty ======== + */ +int_fast16_t PWM_setDuty(PWM_Handle handle, uint32_t duty) +{ + return(handle->fxnTablePtr->setDutyFxn(handle, duty)); +} + +/* + * ======== PWM_setDuty ======== + */ +int_fast16_t PWM_setPeriod(PWM_Handle handle, uint32_t period) +{ + return(handle->fxnTablePtr->setPeriodFxn(handle, period)); +} +/* + * ======== PWM_setDutyandPeriod ======== + */ +int_fast16_t PWM_setDutyAndPeriod(PWM_Handle handle, uint32_t duty, uint32_t period) +{ + return(handle->fxnTablePtr->setDutyAndPeriodFxn(handle, duty, period)); +} + +/* + * ======== PWM_start ======== + */ +void PWM_start(PWM_Handle handle) +{ + handle->fxnTablePtr->startFxn(handle); +} + +/* + * ======== PWM_stop ======== + */ +void PWM_stop(PWM_Handle handle) +{ + handle->fxnTablePtr->stopFxn(handle); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PWM.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PWM.h new file mode 100644 index 0000000..ff22ada --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PWM.h @@ -0,0 +1,623 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file PWM.h + * @brief Pulse Width Modulation (PWM) driver + * + * @anchor ti_drivers_PWM_Overview + * # Overview # + * The PWM driver in TI-RTOS facilitates the generation of Pulse Width + * Modulated signals via simple and portable APIs. + * + * When a PWM instance is opened, the period, duty cycle and idle level are + * configured and the PWM is stopped (waveforms not generated until PWM_start() + * is called). The maximum period and duty supported is device dependent; + * refer to the implementation specific documentation for values. + * + * PWM outputs are active-high, meaning the duty will control the duration of + * high output on the pin (at 0% duty, the output is always low, at 100% duty, + * the output is always high). + * + *
+ * @anchor ti_drivers_PWM_Usage + * # Usage + * + * This documentation provides a basic @ref ti_drivers_PWM_Synopsis + * "usage summary" and a set of @ref ti_drivers_PWM_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor ti_drivers_PWM_Synopsis + * ## Synopsis + * @anchor ti_drivers_PWM_Synopsis_Code + * @code + * // Import PWM Driver definitions + * #include + * + * PWM_Handle pwm; + * PWM_Params pwmParams; + * uint32_t dutyValue; + * + * // Initialize the PWM driver. + * PWM_init(); + * + * // Initialize the PWM parameters + * PWM_Params_init(&pwmParams); + * pwmParams.idleLevel = PWM_IDLE_LOW; // Output low when PWM is not running + * pwmParams.periodUnits = PWM_PERIOD_HZ; // Period is in Hz + * pwmParams.periodValue = 1e6; // 1MHz + * pwmParams.dutyUnits = PWM_DUTY_FRACTION; // Duty is in fractional percentage + * pwmParams.dutyValue = 0; // 0% initial duty cycle + * + * // Open the PWM instance + * pwm = PWM_open(Board_PWM0, &pwmParams); + * + * if (pwm == NULL) { + * // PWM_open() failed + * while (1); + * } + * + * PWM_start(pwm); // start PWM with 0% duty cycle + * + * dutyValue = (uint32_t) (((uint64_t) PWM_DUTY_FRACTION_MAX * 37) / 100); + * PWM_setDuty(pwm, dutyValue); // set duty cycle to 37% + * @endcode + * + *
+ * @anchor ti_drivers_PWM_Examples + * # Examples + * + * @li @ref ti_drivers_PWM_Examples_open "Opening a PWM instance" + * @li @ref ti_drivers_PWM_Examples_duty "Setting PWM duty" + * @li @ref ti_drivers_PWM_Examples_dutyperiod "Setting PWM Duty and Period" + * + * @anchor ti_drivers_PWM_Examples_open + * # Opening a PWM instance + * + * @code + * + * PWM_Handle pwm; + * PWM_Params pwmParams; + * + * PWM_init(); + * + * PWM_Params_init(&pwmParams); + * pwmParams.idleLevel = PWM_IDLE_LOW; + * pwmParams.periodUnits = PWM_PERIOD_HZ; + * pwmParams.periodValue = 1e6; + * pwmParams.dutyUnits = PWM_DUTY_FRACTION; + * pwmParams.dutyValue = 0; + * + * pwm = PWM_open(Board_PWM0, &pwmParams); + * + * if (pwm == NULL) { + * // PWM_open() failed + * while (1); + * } + * @endcode + * + * @anchor ti_drivers_PWM_Examples_duty + * # Setting PWM duty + * + * Once the PWM instance has been opened and started, the primary API used + * by the application will be #PWM_setDuty() to control the duty cycle of a + * PWM pin: + * + * Below demonstrates setting the duty cycle to 45%. + * + * @code + * uint32_t dutyCycle; + * + * dutyCycle = (uint32_t) (((uint64_t) PWM_DUTY_FRACTION_MAX * 45) / 100); + * PWM_setDuty(pwm, dutyCycle); + * @endcode + * + * @anchor ti_drivers_PWM_Examples_dutyperiod + * # Setting PWM Duty and Period + * + * If an application needs to modify the duty and period of a running timer, + * an API is available to set both with as little interim time as possible. + * This minimises the possibility that a timeout will occur between one set + * call and the other. For low periods or for instances close to timeout, this + * API will pause the instance output briefly and must only be called when the + * PWM is already running. + * + * Below demonstrates setting the duty cycle to 75% of the new period (100us). + * + * @code + * uint32_t dutyCycle; + * uint32_t periodUs = 100; + * + * dutyCycle = (uint32_t) (((uint64_t) PWM_DUTY_FRACTION_MAX * 75) / 100); + * PWM_setDutyAndPeriod(pwm, dutyCycle, periodUs); + * @endcode + * + * ### Modes of Operation # + * + * A PWM instance can be configured to interpret the period as one of three + * units: + * - #PWM_PERIOD_US: The period is in microseconds. + * - #PWM_PERIOD_HZ: The period is in (reciprocal) Hertz. + * - #PWM_PERIOD_COUNTS: The period is in timer counts. + * + * A PWM instance can be configured to interpret the duty as one of three + * units: + * - #PWM_DUTY_US: The duty is in microseconds. + * - #PWM_DUTY_FRACTION: The duty is in a fractional part of the period + * where 0 is 0% and #PWM_DUTY_FRACTION_MAX is 100%. + * - #PWM_DUTY_COUNTS: The period is in timer counts and must be less than + * the period. + * + * The idle level parameter is used to set the output to high/low when the + * PWM is not running (stopped or not started). The idle level can be + * set to: + * - #PWM_IDLE_LOW + * - #PWM_IDLE_HIGH + * + * The default PWM configuration is to set a duty of 0% with a 1MHz frequency. + * The default period units are in #PWM_PERIOD_HZ and the default duty units + * are in #PWM_DUTY_FRACTION. Finally, the default output idle level is + * #PWM_IDLE_LOW. It is the application's responsibility to set the duty for + * each PWM output used. + * + *
+ * @anchor ti_drivers_PWM_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ ***************************************************************************** + */ + +#ifndef ti_drivers_PWM__include +#define ti_drivers_PWM__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/*! + * @brief Maximum duty (100%) when configuring duty cycle as a fraction of + * period. + */ +#define PWM_DUTY_FRACTION_MAX ((uint32_t) ~0) + +/*! + * Common PWM_control command code reservation offset. + * PWM driver implementations should offset command codes with #PWM_CMD_RESERVED + * growing positively. + * + * Example implementation specific command codes: + * @code + * #define PWMXYZ_COMMAND0 (PWM_CMD_RESERVED + 0) + * #define PWMXYZ_COMMAND1 (PWM_CMD_RESERVED + 1) + * @endcode + */ +#define PWM_CMD_RESERVED (32) + +/*! + * Common PWM_control status code reservation offset. + * PWM driver implementations should offset status codes with + * #PWM_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define PWMXYZ_STATUS_ERROR0 (PWM_STATUS_RESERVED - 0) + * #define PWMXYZ_STATUS_ERROR1 (PWM_STATUS_RESERVED - 1) + * #define PWMXYZ_STATUS_ERROR2 (PWM_STATUS_RESERVED - 2) + * @endcode + */ +#define PWM_STATUS_RESERVED (-32) + +/*! + * @brief Success status code returned by: + * #PWM_control(), #PWM_setDuty(), #PWM_setPeriod(). + * + * Functions return #PWM_STATUS_SUCCESS if the call was executed + * successfully. + */ +#define PWM_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by #PWM_control(). + * + * #PWM_control() returns #PWM_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define PWM_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by #PWM_control() for undefined + * command codes. + * + * #PWM_control() returns #PWM_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define PWM_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief An error status code returned by #PWM_setPeriod(). + * + * #PWM_setPeriod() returns #PWM_STATUS_INVALID_PERIOD if the period argument is + * invalid for the current configuration. + */ +#define PWM_STATUS_INVALID_PERIOD (-3) + +/*! + * @brief An error status code returned by #PWM_setDuty(). + * + * #PWM_setDuty() returns #PWM_STATUS_INVALID_DUTY if the duty cycle argument is + * invalid for the current configuration. + */ +#define PWM_STATUS_INVALID_DUTY (-4) + +/*! + * @brief PWM period unit definitions. Refer to device specific + * implementation if using #PWM_PERIOD_COUNTS (raw PWM/Timer counts). + */ +typedef enum { + PWM_PERIOD_US, /*!< Period in microseconds */ + PWM_PERIOD_HZ, /*!< Period in (reciprocal) Hertz + (for example 2MHz = 0.5us period) */ + PWM_PERIOD_COUNTS /*!< Period in timer counts */ +} PWM_Period_Units; + +/*! + * @brief PWM duty cycle unit definitions. Refer to device specific + * implementation if using PWM_DUTY_COUNTS (raw PWM/Timer counts). + */ +typedef enum { + PWM_DUTY_US, /*!< Duty cycle in microseconds */ + PWM_DUTY_FRACTION, /*!< Duty as a fractional part of #PWM_DUTY_FRACTION_MAX. + * A duty cycle value of 0 will yield a 0% duty cycle + * while a duty cycle value of #PWM_DUTY_FRACTION_MAX + * will yield a duty cycle value of 100%. */ + PWM_DUTY_COUNTS /*!< Duty in timer counts */ +} PWM_Duty_Units; + +/*! + * @brief Idle output level when PWM is not running (stopped / not started). + */ +typedef enum { + PWM_IDLE_LOW = 0, + PWM_IDLE_HIGH = 1, +} PWM_IdleLevel; + +/*! + * @brief PWM Parameters + * + * PWM Parameters are used to with the PWM_open() call. Default values for + * these parameters are set using PWM_Params_init(). + * + * @sa PWM_Params_init() + */ +typedef struct { + PWM_Period_Units periodUnits; /*!< Units in which the period is specified */ + uint32_t periodValue; /*!< PWM initial period */ + PWM_Duty_Units dutyUnits; /*!< Units in which the duty is specified */ + uint32_t dutyValue; /*!< PWM initial duty */ + PWM_IdleLevel idleLevel; /*!< Pin output when PWM is stopped. */ + void *custom; /*!< Custom argument used by driver + implementation */ +} PWM_Params; + +/*! + * @brief A handle that is returned from a PWM_open() call. + */ +typedef struct PWM_Config_ *PWM_Handle; + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_close(). + */ +typedef void (*PWM_CloseFxn) (PWM_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_control(). + */ +typedef int_fast16_t (*PWM_ControlFxn) (PWM_Handle handle, uint_fast16_t cmd, + void *arg); +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_init(). + */ +typedef void (*PWM_InitFxn) (PWM_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_open(). + */ +typedef PWM_Handle (*PWM_OpenFxn) (PWM_Handle handle, PWM_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_setDuty(). + */ +typedef int_fast16_t (*PWM_SetDutyFxn) (PWM_Handle handle, + uint32_t duty); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_setPeriod(). + */ +typedef int_fast16_t (*PWM_SetPeriodFxn) (PWM_Handle handle, + uint32_t period); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_setDutyAndPeriod(). + */ +typedef int_fast16_t (*PWM_SetDutyAndPeriodFxn) (PWM_Handle handle, + uint32_t duty, uint32_t period); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_start(). + */ +typedef void (*PWM_StartFxn) (PWM_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_stop(). + */ +typedef void (*PWM_StopFxn) (PWM_Handle handle); + +/*! + * @brief The definition of a PWM function table that contains the + * required set of functions to control a specific PWM driver + * implementation. + */ +typedef struct PWM_FxnTable_ { + /*! Function to close the specified instance */ + PWM_CloseFxn closeFxn; + /*! Function to driver implementation specific control function */ + PWM_ControlFxn controlFxn; + /*! Function to initialize the given data object */ + PWM_InitFxn initFxn; + /*! Function to open the specified instance */ + PWM_OpenFxn openFxn; + /*! Function to set the duty cycle for a specific instance */ + PWM_SetDutyFxn setDutyFxn; + /*! Function to set the period for a specific instance */ + PWM_SetPeriodFxn setPeriodFxn; + /*! Function to set the duty and the period for a specific instance */ + PWM_SetDutyAndPeriodFxn setDutyAndPeriodFxn; + /*! Function to start the PWM output for a specific instance */ + PWM_StartFxn startFxn; + /*! Function to stop the PWM output for a specific instance */ + PWM_StopFxn stopFxn; +} PWM_FxnTable; + +/*! + * @brief PWM Global configuration. + * + * The PWM_Config structure contains a set of pointers used to characterize + * the PWM driver implementation. + * + */ +typedef struct PWM_Config_ { + /*! Pointer to a table of driver-specific implementations of PWM APIs */ + PWM_FxnTable const *fxnTablePtr; + /*! Pointer to a driver specific data object */ + void *object; + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} PWM_Config; + +/*! + * @brief Function to close a PWM instance specified by the PWM handle. + * + * @pre PWM_open() must have been called first. + * @pre PWM_stop() must have been called first if PWM was started. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @sa PWM_open() + * @sa PWM_start() + * @sa PWM_stop() + */ +extern void PWM_close(PWM_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * PWM_Handle. + * + * @pre PWM_open() must have been called first. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @param[in] cmd A command value defined by the driver specific + * implementation. + * + * @param[in] arg A pointer to an optional R/W (read/write) argument that + * is accompanied with cmd. + * + * @retval #PWM_STATUS_SUCCESS The control call was successful. + * @retval #PWM_STATUS_ERROR The control call failed. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_control(PWM_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief This function initializes the PWM module. + * + * @pre The PWM_config structure must exist and be persistent before this + * function can be called. This function must be called before any + * other PWM driver APIs. This function does not modify any peripheral + * registers & should only be called once. + */ +extern void PWM_init(void); + +/*! + * @brief This function opens a given PWM instance and sets the period, + * duty and idle level to those specified in the params argument. + * + * @param[in] index Logical instance number for the PWM indexed into + * the PWM_config table. + * + * @param[in] params Pointer to an parameter structure. If NULL default + * values are used. + * + * @return A #PWM_Handle if successful or NULL on an error or if it has been + * opened already. If NULL is returned further PWM API calls will + * result in undefined behavior. + * + * @sa PWM_close() + */ +extern PWM_Handle PWM_open(uint_least8_t index, PWM_Params *params); + +/*! + * @brief Function to initialize the PWM_Params structure to default values. + * + * @param[in] params A pointer to PWM_Params structure for initialization. + * + * Defaults values are: + * Period units: PWM_PERIOD_HZ + * Period: 1e6 (1MHz) + * Duty cycle units: PWM_DUTY_FRACTION + * Duty cycle: 0% + * Idle level: PWM_IDLE_LOW + */ +extern void PWM_Params_init(PWM_Params *params); + +/*! + * @brief Function to set the duty cycle of the specified PWM handle. PWM + * instances run in active high output mode; 0% is always low output, + * 100% is always high output. This API can be called while the PWM + * is running & duty must always be lower than or equal to the period. + * If an error occurs while calling the function the PWM duty cycle + * will remain unchanged. + * + * @pre PWM_open() must have been called first. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @param[in] duty Duty cycle in the units specified by the params used + * in PWM_open(). + * + * @retval #PWM_STATUS_SUCCESS The duty was set successfully. + * @retval #PWM_STATUS_ERROR The duty was not set and remains unchanged. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_setDuty(PWM_Handle handle, uint32_t duty); + +/*! + * @brief Function to set the period of the specified PWM handle. This API + * can be called while the PWM is running & the period must always be + * larger than the duty cycle. + * If an error occurs while calling the function the PWM period + * will remain unchanged. + * + * @pre PWM_open() must have been called first. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @param[in] period Period in the units specified by the params used + * in PWM_open(). + * + * @retval #PWM_STATUS_SUCCESS The period was set successfully. + * @retval #PWM_STATUS_ERROR The period was not set and remains unchanged. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_setPeriod(PWM_Handle handle, uint32_t period); + +/*! + * @brief Function to set both the period and the duty cycle of the specified PWM handle. + * This API must be called while the PWM is running & the period must always be + * larger than the duty cycle. + * If an error occurs while calling the function the period and duty + * will remain unchanged. + * + * @note This API should only be called while the PWM is running. + * + * @note If the period is lower than a certain platform-specific amount, the output of the + * PWM timer may be paused to set these values. Some implementations may also pause + * the PWM if the remaining time before the next timeout is less than this value. This + * is to guard against an edge case where a timeout happens in between setting period + * and duty. + * + * @pre PWM_open() must have been called first. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @param[in] duty Duty cycle in the units specified by the params used + * in PWM_open(). + * + * @param[in] period Period in the units specified by the params used + * in PWM_open(). + * + * @retval #PWM_STATUS_SUCCESS The duty and period was set successfully. + * @retval #PWM_STATUS_ERROR The duty and period was not set and + remains unchanged. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_setDutyAndPeriod(PWM_Handle handle, uint32_t duty, uint32_t period); + +/*! + * @brief Function to start the specified PWM handle with current settings. + * + * @pre PWM_open() has to have been called first. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @sa PWM_open() + * @sa PWM_stop() + */ +extern void PWM_start(PWM_Handle handle); + +/*! + * @brief Function to stop the specified PWM handle. Output will set to the + * idle level specified by params in PWM_open(). + * + * @pre PWM_open() has to have been called first. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @sa PWM_open() + * @sa PWM_start() + */ +extern void PWM_stop(PWM_Handle handle); + +#ifdef __cplusplus +} +#endif +#endif /* ti_drivers_PWM__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Power.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Power.h new file mode 100644 index 0000000..24d8a6e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Power.h @@ -0,0 +1,970 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file Power.h + * @brief Power Manager + * + * @anchor ti_drivers_Power_Overview + * # Overview + * + * The Power Manager facilitates the transition of the MCU from active states + * to sleep states and vice versa. It provides other drivers the + * ability to set and release dependencies on hardware resources, and keeps + * reference counts on each resource to know when to enable or disable the + * resource. It provides drivers the ability to register callback functions + * to be invoked upon specific power events. In addition, drivers and + * applications can set or release constraints to prevent the MCU from + * transitioning into specific active or sleep states. Refer to the device + * specific power driver header file device specific information. + * + *
+ * @anchor ti_drivers_Power_Usage + * # Usage + * + * This documentation provides a basic @ref ti_drivers_Power_Synopsis + * "usage summary" and a set of @ref ti_drivers_Power_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * @anchor ti_drivers_Power_Synopsis + * ## Synopsis + * @anchor ti_drivers_Power_Synopsis_Code + * + * @note The following example demonstrates usage of some of the Power + * driver APIs.This example is intended for reference only and is not intended + * for application use. You should refer to the device specific Power driver + * header for valid API usage and arguments. + * + * + * @code + * // Import Power Driver definitions + * #include + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Set power dependency on a resource + * status = Power_setDependency(resourceId); + * if (status != Power_SOK) { + * // Error occurred + * } + * + * // Set a power constraint + * status = Power_setConstraint(constraintId); + * if (status != Power_SOK) { + * // Error occurred + * } + * + * // Other application code + * + * // Release a previously set power constraint + * status = Power_releaseConstraint(constraintId); + * if (status != Power_SOK) { + * // Error occurred + * } + * + * status = Power_releaseDependency(resourceId); + * if (status != Power_SOK) { + * // Error occurred + * } + * @endcode + * + * + *
+ * @anchor ti_drivers_Power_Examples + * # Examples + * + * @note + * The following examples are intended for reference only and are not + * intended for application use. You should refer to the device specific + * Power driver header file for more usage information. + * + * @li @ref ti_drivers_Power_Examples_enable "Enabling power policy" + * @li @ref ti_drivers_Power_Examples_disable "Disabling power policy" + * @li @ref ti_drivers_Power_Examples_constraint "Using power constraints" + * @li @ref ti_drivers_Power_Examples_dependency "Using power dependency" + * @li @ref ti_drivers_Power_Examples_notify "Using power notify" + * @li @ref ti_drivers_Power_Examples_transistion "Power transitions" + * + * + * @anchor ti_drivers_Power_Examples_enable + * ## Enabling Power Policy + * + * @code + * // Import Power Driver definitions + * #include + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Enable power policy + * Power_enablePolicy(); + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_disable + * ## Disabling Power Policy + * + * @code + * // Import Power Driver definitions + * #include + * + * bool flag; + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Disable power policy + * flag = Power_disablePolicy(); + * if (flag == false) { + * // Power policy was already disabled + * } + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_constraint + * ## Using Power Constraints + * + * @code + * // Import Power Driver definitions + * #include + * + * uint32_t mask; + * int16_t status; + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Set a power constraint + * status = Power_setConstraint(constraintId); + * if (status != Power_SOK) { + * // Error occurred setting constraint + * } + * + * // Read mask of currently set power constraints + * mask = Power_getConstraintMask(); + * + * // Release previously set constraint + * status = Power_releaseConstraint(constraintId); + * if (status != Power_SOK) { + * // Error occurred releasing constraint + * } + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_dependency + * ## Using Power Dependency + * + * @code + * // Import Power Driver definitions + * #include + * + * int16_t count; + * int16_t status; + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Set a power dependency + * status = Power_setDependency(resourceId); + * if (status != Power_SOK) { + * // Error occurred setting dependency + * } + * + * // Get the dependency count of the resource + * count = Power_getDependencyCount(resourceId); + * if (count == Power_EINVALIDINPUT) { + * // Invalid resourceId used + * } + * + * if (count > 0) { + * // At least 1 dependency exists for the resource. + * // Regardless, we may safely release the dependency when we + * // no longer need the resource. + * } + * + * // Release a power dependency + * status = Power_releaseDependency(resourceId); + * if (status != Power_SOK) { + * // Error occurred releasing dependency + * } + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_notify + * ## Using Power Notify + * + * The application must define a #Power_NotifyFxn function and + * allocate memory for the #Power_NotifyObj object. + * + * @code + * // Import Power Driver definitions + * #include + * + * // Application Power_NotifyObj object + * Power_NotifyObj powerNotifyObj; + * + * // Application Power_NotifyFxn function prototype + * static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + * uintptr_t clientArg); + * @endcode + * + * The application must register for the event. Here, we use pseudo event + * names. You should refer to the device specific power driver header file + * for eventTypes. Inside the infinite loop, we wait for a semaphore to be + * post from our notification callback. + * + * @code + * // Application thread + * void thread(void) + * { + * int16_t status; + * unsigned int eventTypes = LOW_POWER_EXIT | LOW_POWER_ENTER; + * uintptr_t clientArg = semaphoreHandle; + * + * status = Power_registerNotify(&powerNotifyObj, eventTypes, + * postNotifyFxn, clientArg); + * + * while (1) + * { + * sem_wait(semaphoreHandle); + * // Do something + * + * // Unregister for the notification. After this call, + * // our postNotifyFxn() will never be called again unless + * // we use Power_registerNotify() again. + * Power_unregisterNotify(&powerNotifyObj); + * + * break; + * } + * } + * @endcode + * + * The application may implement the power notify function to fit their + * needs. The #Power_NotifyFxn should always return #Power_NOTIFYDONE or + * #Power_NOTIFYERROR. + * + * @code + * // Application Power_NotifyFxn function implementation + * static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + * uintptr_t clientArg) + * { + * sem_t semaphoreHandle = (sem_t) clientArg; + * + * if (eventType == LOW_POWER_EXIT) { + * sem_post(semaphoreHandle); + * return (Power_NOTIFYDONE); + * } + * + * if (eventType == LOW_POWER_ENTER) { + * // Store something in RAM + * return (Power_NOTIFYDONE); + * } + * + * // We received an unexpected event type + * return (Power_NOTIFYERROR); + * } + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_transistion + * ## Power transitions + * + * @code + * // Import Power Driver definitions + * #include + * + * uint32_t totalLatency, resumeLatency; + * int16_t status; + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Get the current power transition state + * status = Power_getTransitionState(); + * + * switch (status) + * { + * case Power_ACTIVE: + * // No transitions in progress + * break; + * case Power_ENTERING_SLEEP: + * // Transition to sleep in progress + * break; + * case Power_EXITING_SLEEP: + * // Transition from sleep in progress + * break; + * case Power_CHANGING_PERF_LEVEL: + * // Performance level change in progress + * break; + * } + * + * // Get the Power_TOTAL and Power_RESUME transition latency for a + * // device specific sleepState. Latency is in microseconds. + * totalLatency = Power_getTransitionLatency(sleepState, Power_TOTAL); + * resumeLatency = Power_getTransitionLatency(sleepState, Power_RESUME); + * @endcode + * + * + *
+ * @anchor ti_drivers_Power_Configuration + * # Configuration + * + * @note The Power Manager APIs and configuration parameters are described here. + * For a detailed description of terms and concepts, and usage by different + * types of software components (peripheral drivers, power policies, + * and applications) please see the + * SimpleLink SDK Power Management User's Guide. + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_Power__include +#define ti_drivers_Power__include + +/* @cond */ +#include +#include +/* @endcond */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @addtogroup Power_Latency_Type + * @{ + */ +#define Power_TOTAL (1U) /*!< total latency */ +#define Power_RESUME (2U) /*!< resume latency */ +/*! @}*/ + +/*! @addtogroup Power_Notify_Response + * @{ + */ +#define Power_NOTIFYDONE (0) /*!< OK, notify completed */ +#define Power_NOTIFYERROR (-1) /*!< an error occurred during notify */ +/*! @}*/ + +/*! @addtogroup Power_Status + * @{ + */ +#define Power_SOK (0) /*!< OK, operation succeeded */ +#define Power_EFAIL (-1) /*!< general failure */ +#define Power_EINVALIDINPUT (-2) /*!< invalid data value */ +#define Power_EINVALIDPOINTER (-3) /*!< invalid pointer */ +#define Power_ECHANGE_NOT_ALLOWED (-4) /*!< change is not allowed */ +#define Power_EBUSY (-5) /*!< busy with another transition */ +/*! @}*/ + +/*! @addtogroup Power_Transition_State + * @{ + */ +#define Power_ACTIVE (1U) /*!< normal active state */ +#define Power_ENTERING_SLEEP (2U) /*!< entering a sleep state */ +#define Power_EXITING_SLEEP (3U) /*!< exiting a sleep state */ +#define Power_ENTERING_SHUTDOWN (4U) /*!< entering a shutdown state */ +#define Power_CHANGING_PERF_LEVEL (5U) /*!< moving to new performance level */ +/*! @}*/ + +/*! + * @brief Power policy initialization function pointer + */ +typedef void (*Power_PolicyInitFxn)(void); + +/*! + * @brief Power policy function pointer + */ +typedef void (*Power_PolicyFxn)(void); + +/*! + * @brief Power notify callback function used with the + * Power_registerNotify() + * + * @param[in] eventType The eventTypes parameter identifies the type of + * power event for which the notify callback function was called. + * + * @param[in] eventArg An optional @p eventType specific argument. + * + * @param[in] clientArg Pointer to a custom argument. + * + * @retval #Power_NOTIFYDONE if the client processed the notification + * successfully + * + * @retval #Power_NOTIFYERROR if an error occurred during notification. + * + * @sa Power_registerNotify() + * @sa Power_unregisterNotify() + * @sa Power_NotifyObj + * @sa @ref ti_drivers_Power_Examples_notify "Using power notify" + */ +typedef int_fast16_t (*Power_NotifyFxn)(uint_fast16_t eventType, + uintptr_t eventArg, uintptr_t clientArg); + +/*! + * @brief Power notify object structure. + * + * This structure specification is for internal use. Notification clients must + * pre-allocate a notify object when registering for a notification; + * Power_registerNotify() will take care initializing the internal elements + * appropriately. + * + * @sa @ref ti_drivers_Power_Examples_notify "Using power notify" + */ +typedef struct { + List_Elem link; /*!< for placing on the notify list */ + uint_fast16_t eventTypes; /*!< the event type */ + Power_NotifyFxn notifyFxn; /*!< notification function */ + uintptr_t clientArg; /*!< argument provided by client */ +} Power_NotifyObj; + +/*! + * @brief Disable the configured power policy from running when the CPU is + * idle + * + * Calling this function clears the flag that controls whether the configured + * power policy function is invoked on each pass through the Idle loop. + * This function call will override both a 'true' setting of the + * "enablePolicy" setting in the Power Manager configuration object, as well + * as a previous runtime call to the Power_enablePolicy() function. + * + * @return The old value of "enablePolicy". + * + * @sa Power_enablePolicy() + * @sa @ref ti_drivers_Power_Examples_enable "Enabling power policy" + * @sa @ref ti_drivers_Power_Examples_disable "Disabling power policy" + */ +bool Power_disablePolicy(void); + +/*! + * @brief Enable the configured power policy to run when the CPU is idle + * + * Calling this function sets a flag that will cause the configured power + * policy function to be invoked on each pass through the Idle loop. This + * function call will override both a 'false' setting of the "enablePolicy" + * setting in the Power Manager configuration object, as well as a previous + * runtime call to the Power_disablePolicy() function. + * + * For some processor families, automatic power transitions can make initial + * application development more difficult, as well as being at odds with + * basic debugger operation. This convenience function allows an application + * to be initially configured, built, and debugged, without automatic power + * transitions during idle time. When the application is found to be working, + * this function can be called (typically in main()) to enable the policy + * to run, without having to change the application configuration. + * + * @sa Power_disablePolicy() + * @sa @ref ti_drivers_Power_Examples_enable "Enabling power policy" + * @sa @ref ti_drivers_Power_Examples_disable "Disabling power policy" + */ +void Power_enablePolicy(void); + +/*! + * @brief Get the constraints that have been declared with Power + * + * This function returns a bitmask indicating the constraints that are + * currently declared to the Power Manager (via previous calls to + * Power_setConstraint()). For each constraint that is currently declared, + * the corresponding bit in the bitmask will be set. For example, if two + * clients have independently declared two different constraints, the returned + * bitmask will have two bits set. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * MSP432 are defined in PowerMSP432.h. The corresponding bit in the + * bitmask returned by this function can be derived by a left-shift using + * the constraint identifier. For example, for MSP432, for the corresponding + * bit for the PowerMSP432_DISALLOW_SLEEP constraint, the bit position is + * determined by the operation: (1 << PowerMSP432_DISALLOW_SLEEP) + * + * @return A bitmask of the currently declared constraints. + * + * @sa Power_setConstraint() + * @sa @ref ti_drivers_Power_Examples_constraint "Using power constraints" + */ +uint_fast32_t Power_getConstraintMask(void); + +/*! + * @brief Get the current dependency count for a resource + * + * This function returns the number of dependencies that are currently + * declared upon a resource. + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. For example, the resources for + * CC32XX are defined in PowerCC32XX.h. + * + * @param[in] resourceId resource id + * + * @return The number of dependencies declared for the resource. + * + * @retval #Power_EINVALIDINPUT if the @p resourceId is invalid or this + * function is not supported by the device specific implementation. + * + * @sa Power_setDependency() + * @sa @ref ti_drivers_Power_Examples_dependency "Using power dependency" + */ +int_fast16_t Power_getDependencyCount(uint_fast16_t resourceId); + +/*! + * @brief Get the current performance level + * + * This function returns the current device performance level in effect. + * + * If performance scaling is not supported for the device, this function + * will always indicate a performance level of zero. + * + * @return The current performance level. + * + * @sa Power_setPerformanceLevel() + */ +uint_fast16_t Power_getPerformanceLevel(void); + +/*! + * @brief Get the hardware transition latency for a sleep state + * + * This function reports the minimal hardware transition latency for a specific + * sleep state. The reported latency is that for a direct transition, and does + * not include any additional latency that might occur due to software-based + * notifications. + * + * Sleep states are device specific, and defined in the device-specific Power + * include file. For example, the sleep states for CC32XX are defined in + * PowerCC32XX.h. + * + * This function is typically called by the power policy function. The latency + * is reported in units of microseconds. + * + * @param[in] sleepState the sleep state + * + * @param[in] type @ref Power_Latency_Type (#Power_TOTAL or #Power_RESUME) + * + * @return The latency value, in units of microseconds. + * + * @sa @ref ti_drivers_Power_Examples_transistion "Power transitions" + */ +uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, + uint_fast16_t type); + +/*! + * @brief Get the current transition state of the Power Manager + * + * @return The current @ref Power_Transition_State. + * + * @retval #Power_ACTIVE returned when no transitions are in progress. + * + * @retval #Power_ENTERING_SLEEP returned during the transition to + * sleep, before sleep has occurred. + * + * @retval #Power_EXITING_SLEEP returned after wakeup, as the device is + * being transitioned back to #Power_ACTIVE. + * + * @retval #Power_CHANGING_PERF_LEVEL returned when a change is being made + * to the performance level. + * + * @sa @ref ti_drivers_Power_Examples_transistion "Power transitions" + */ +uint_fast16_t Power_getTransitionState(void); + +/*! + * @brief Power function to be added to the application idle loop + * + * This function should be added to the application idle loop. (The method to + * do this depends upon the operating system being used.) This function + * will invoke the configured power policy function when appropriate. The + * specific policy function to be invoked is configured as the 'policyFxn' + * in the application-defined Power configuration object. + * + */ +void Power_idleFunc(void); + +/*! + * @brief Power initialization function + * + * This function initializes Power Manager internal state. + * + * @warning The application is responsible for ensuring this function is + * called prior to any other Power API. Additionally, this function must be + * be called prior to any other TI-Driver's APIs. This function is normally + * called prior to any operating system initialization. + * + * @return #Power_SOK + */ +int_fast16_t Power_init(void); + +/*! + * @brief Register a function to be called upon a specific power event + * + * This function registers a function to be called when a Power event occurs. + * Registrations and the corresponding notifications are processed in + * first-in-first-out (FIFO) order. The function registered must behave as + * described later, below. + * + * The pNotifyObj parameter is a pointer to a pre-allocated, opaque object + * that will be used by Power to support the notification. This object could + * be dynamically allocated, or declared as a global object. This function + * will properly initialized the object's fields as appropriate; the caller + * just needs to provide a pointer to this pre-existing object. + * + * The eventTypes parameter identifies the type of power event(s) for which + * the notify function being registered is to be called. (Event identifiers are + * device specific, and defined in the device-specific Power include file. + * For example, the events for MSP432 are defined in PowerMSP432.h.) The + * eventTypes parameter for this function call is treated as a bitmask, so + * multiple event types can be registered at once, using a common callback + * function. For example, to call the specified notifyFxn when both + * the entering deepsleep and awake from deepsleep events occur, eventTypes + * should be specified as: PowerMSP432_ENTERING_DEEPSLEEP | + * PowerMSP432_AWAKE_DEEPSLEEP + * + * The notifyFxn parameter specifies a callback function to be called when the + * specified Power event occurs. The notifyFxn must implement the following + * signature: + * status = notifyFxn(eventType, eventArg, clientArg); + * + * Where: eventType identifies the event being signaled, eventArg is an + * optional event-specific argument, and clientArg is an arbitrary argument + * specified by the client at registration. Note that multiple types of events + * can be specified when registering the notification callback function, + * but when the callback function is actually called by Power, only a + * single eventType will be specified for the callback (i.e., the current + * event). The status returned by the client notification function must + * be one of the following constants: Power_NOTIFYDONE if the client processed + * the notification successfully, or Power_NOTIFYERROR if an error occurred + * during notification. + * + * The clientArg parameter is an arbitrary, client-defined argument to be + * passed back to the client upon notification. This argument may allow one + * notify function to be used by multiple instances of a driver (that is, the + * clientArg can be used to identify the instance of the driver that is being + * notified). + * + * @param[in] pNotifyObj #Power_NotifyObj preallocated by caller + * + * @param[in] eventTypes event type or types + * + * @param[in] notifyFxn client's #Power_NotifyFxn function + * + * @param[in] clientArg client-specified argument to pass with + * notification + * + * @retval #Power_SOK on success. + * + * @retval #Power_EINVALIDPOINTER if either @p pNotifyObj or @p notifyFxn + * are NULL. + * + * @sa Power_unregisterNotify() + * @sa @ref ti_drivers_Power_Examples_notify "Using power notify" + */ +int_fast16_t Power_registerNotify(Power_NotifyObj *pNotifyObj, + uint_fast16_t eventTypes, + Power_NotifyFxn notifyFxn, + uintptr_t clientArg); + +/*! + * @brief Release a previously declared constraint + * + * This function releases a constraint that was previously declared with + * Power_setConstraint(). For example, if a device driver is starting an I/O + * transaction and wants to prohibit activation of a sleep state during the + * transaction, it uses Power_setConstraint() to declare the constraint, + * before starting the transaction. When the transaction completes, the + * driver calls this function to release the constraint, to allow the Power + * manager to once again allow transitions to sleep. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * MSP432 are defined in PowerMSP432.h. + * + * Only one constraint can be specified with each call to this function; to + * release multiple constraints this function must be called multiple times. + * + * It is critical that clients call Power_releaseConstraint() when operational + * constraints no longer exists. Otherwise, Power may be left unnecessarily + * restricted from activating power savings. + * + * @pre Power_setConstraint() must have been called first. + * + * @param[in] constraintId constraint id + * + * @return CC26XX/CC13XX only: #Power_SOK. To minimize code size + * asserts are used internally to check that the constraintId is + * valid,valid, and that the constraint count is not already zero; + * the function always returns #Power_SOK. + * + * @return All other devices: #Power_SOK on success, + * #Power_EINVALIDINPUT if the constraintId is invalid, and + * #Power_EFAIL if the constraint count is already zero. + * + * @sa Power_setConstraint() + * @sa @ref ti_drivers_Power_Examples_constraint "Using power constraints" + */ +int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId); + +/*! + * @brief Release a previously declared dependency + * + * This function releases a dependency that had been previously declared upon + * a resource (by a call to Power_setDependency()). + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. For example, the resources for + * CC32XX are defined in PowerCC32XX.h. + * + * @param[in] resourceId resource id + * + * @return CC26XX/CC13XX only: #Power_SOK. To minimize code size + * asserts are used internally to check that the resourceId is valid, + * and that the resource reference count is not already zero; + * the function always returns #Power_SOK. + * + * @return All other devices: #Power_SOK on success, + * #Power_EINVALIDINPUT if the resourceId is invalid, and #Power_EFAIL + * if the resource reference count is already zero. + * + * @sa Power_setDependency() + * @sa @ref ti_drivers_Power_Examples_dependency "Using power dependency" + */ +int_fast16_t Power_releaseDependency(uint_fast16_t resourceId); + +/*! + * @brief Declare an operational constraint + * + * Before taking certain actions, the Power Manager checks to see if the + * requested action would conflict with a client-declared constraint. If the + * action does conflict, Power will not proceed with the request. This is the + * function that allows clients to declare their constraints with Power. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * MSP432 are defined in PowerMSP432.h. + * + * Only one constraint can be specified with each call to this function; to + * declare multiple constraints this function must be called multiple times. + * + * @param[in] constraintId constraint id + * + * @return CC26XX/CC13XX only: #Power_SOK. To minimize code size an + * assert is used internally to check that the constraintId is valid; + * the function always returns #Power_SOK. + * + * @return All other devices: #Power_SOK on success, + * #Power_EINVALIDINPUT if the constraintId is invalid. + * + * @sa Power_releaseConstraint() + * @sa @ref ti_drivers_Power_Examples_constraint "Using power constraints" + */ +int_fast16_t Power_setConstraint(uint_fast16_t constraintId); + +/*! + * @brief Declare a dependency upon a resource + * + * This function declares a dependency upon a resource. For example, if a + * UART driver needs a specific UART peripheral, it uses this function to + * declare this to the Power Manager. If the resource had been inactive, + * then Power will activate the peripheral during this function call. + * + * What is needed to make a peripheral resource 'active' will vary by device + * family. For some devices this may be a simple enable of a clock to the + * specified peripheral. For others it may also require a power on of a + * power domain. In either case, the Power Manager will take care of these + * details, and will also implement reference counting for resources and their + * interdependencies. For example, if multiple UART peripherals reside in + * a shared serial power domain, the Power Manager will power up the serial + * domain when it is first needed, and then automatically power the domain off + * later, when all related dependencies for the relevant peripherals are + * released. + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. For example, the resources for + * CC32XX are defined in PowerCC32XX.h. + * + * @param[in] resourceId resource id + * + * @return CC26XX/CC13XX only: #Power_SOK. To minimize code size an + * assert is used internally to check that the resourceId is valid; + * the function always returns #Power_SOK. + * + * @return All other devices: #Power_SOK on success, + * #Power_EINVALIDINPUT if the reseourceId is invalid. + * + * @sa Power_releaseDependency() + * @sa @ref ti_drivers_Power_Examples_dependency "Using power dependency" + */ +int_fast16_t Power_setDependency(uint_fast16_t resourceId); + +/*! + * @brief Set the MCU performance level + * + * This function manages a transition to a new device performance level. + * Before the actual transition is initiated, notifications will be sent to + * any clients who've registered with Power_registerNotify() for a + * 'start change performance level' notification. The event name is device + * specific, and defined in the device-specific Power include file. For + * example, for MSP432, the event is "PowerMSP432_START_CHANGE_PERF_LEVEL", + * which is defined in PowerMSP432.h. Once notifications have been completed, + * the change to the performance level is initiated. After the level change + * is completed, there is a comparable event that can be used to signal a + * client that the change has completed. For example, on MSP432 the + * "PowerMSP432_DONE_CHANGE_PERF_LEVEL" event can be used to signal + * completion. + * + * This function will not return until the new performance level is in effect. + * If performance scaling is not supported for the device, or is prohibited + * by an active constraint, or if the specified level is invalid, then an + * error status will be returned. + * + * @param[in] level the new performance level + * + * @retval #Power_SOK on success. + * + * @retval #Power_EINVALIDINPUT if the specified performance level is out of + * range of valid levels. + * + * @retval #Power_EBUSY if another transition is already in progress, or if + * a single constraint is set to prohibit any change to the + * performance level. + * + * @retval #Power_ECHANGE_NOT_ALLOWED if a level-specific constraint prohibits + * a change to the requested level. + * + * @retval #Power_EFAIL if performance scaling is not supported, if an + * error occurred during initialization, or if an error occurred + * during client notifications. + * + * @sa Power_getPerformanceLevel() + */ +int_fast16_t Power_setPerformanceLevel(uint_fast16_t level); + +/*! + * @brief Set a new Power policy + * + * This function allows a new #Power_PolicyFxn function to be selected at + * runtime. + * + * @param[in] policy the new #Power_PolicyFxn function + */ +void Power_setPolicy(Power_PolicyFxn policy); + +/*! + * @brief Put the device into a shutdown state + * + * This function will transition the device into a shutdown state. + * Before the actual transition is initiated, notifications will be sent to + * any clients who've registered (with Power_registerNotify()) for an + * 'entering shutdown' event. The event name is device specific, and defined + * in the device-specific Power include file. For example, for CC32XX, the + * event is "PowerCC32XX_ENTERING_SHUTDOWN", which is defined in + * PowerCC32XX.h. Once notifications have been completed, the device shutdown + * will commence. + * + * If the device is successfully transitioned to shutdown, this function + * call will never return. Upon wakeup, the device and application will + * be rebooted (through a device reset). If the transition is not + * successful, one of the error codes listed below will be returned. + * + * On some devices a timed wakeup from shutdown can be specified, using + * the shutdownTime parameter. This enables an autonomous application reboot + * at a future time. For example, an application can go to shutdown, and then + * automatically reboot at a future time to do some work. And once that work + * is done, the application can shutdown again, for another timed interval. + * The time interval is specified via the shutdownTime parameter. (On devices + * that do not support this feature, any value specified for shutdownTime will + * be ignored.) If the specified shutdownTime is zero, or otherwise less than + * the total shutdown latency for the device, the shutdownTime parameter will + * be ignored. The shutdown latency for the device can be found in the + * device-specific Power include file. For example, for the CC32XX, this + * latency is defined in PowerCC32XX.h, as "PowerCC32XX_TOTALTIMESHUTDOWN".) + * + * @param[in] shutdownState the device-specific shutdown state + * + * @param[in] shutdownTime the amount of time (in milliseconds) to keep + * the the device in the shutdown state; this parameter is not supported on + * all device families. + * + * @retval #Power_ECHANGE_NOT_ALLOWED if a constraint is prohibiting + * shutdown. + * + * @retval #Power_EFAIL if an error occurred during client notifications. + * + * @retval #Power_EINVALIDINPUT if the shutdownState is invalid. + * + * @retval #Power_EBUSY if another transition is already in progress. + */ +int_fast16_t Power_shutdown(uint_fast16_t shutdownState, + uint_fast32_t shutdownTime); + +/*! + * @brief Transition the device into a sleep state + * + * This function is called from the power policy when it has made a decision + * to put the device in a specific sleep state. This function returns to the + * caller (the policy function) once the device has awoken from sleep. + * + * @warning This function must be called with interrupts disabled, and + * should not be called directly by the application, or by any drivers. + * This function does not check declared constraints; the policy function + * must check constraints before calling this function to initiate sleep. + * + * @param[in] sleepState the sleep state + * + * @retval #Power_SOK on success, the device has slept and is awake again. + * + * @retval #Power_EFAIL if an error occurred during client notifications, or + * if a general failure occurred. + * + * @retval #Power_EINVALIDINPUT if the @p sleepState is invalid. + * + * @retval #Power_EBUSY if another transition is already in progress. + */ +int_fast16_t Power_sleep(uint_fast16_t sleepState); + +/*! + * @brief Unregister previously registered notifications + * + * This function unregisters for event notifications that were previously + * registered with Power_registerNotify(). The caller must specify a pointer + * to the same notification object used during registration. + * + * @param[in] pNotifyObj The #Power_NotifyObj used with the original + * call to Power_registerNotify() + * + * @sa Power_registerNotify() + * @sa @ref ti_drivers_Power_Examples_notify "Using power notify" + */ +void Power_unregisterNotify(Power_NotifyObj *pNotifyObj); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Power__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SD.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SD.c new file mode 100644 index 0000000..f12abc6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SD.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2016-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include + +extern const SD_Config SD_config[]; +extern const uint_least8_t SD_count; + +/* Default SD parameters structure */ +const SD_Params SD_defaultParams = { + NULL /* custom */ +}; + +static bool isInitialized = false; + +/* + * ======== SD_close ======== + */ +void SD_close(SD_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== SD_control ======== + */ +int_fast16_t SD_control(SD_Handle handle, uint_fast16_t cmd, void *arg) +{ + return (handle->fxnTablePtr->controlFxn(handle, cmd, arg)); +} + +/* + * ======== SD_getNumSectors ======== + */ +uint_fast32_t SD_getNumSectors(SD_Handle handle) +{ + return (handle->fxnTablePtr->getNumSectorsFxn(handle)); +} + +/* + * ======== SD_getSectorSize ======== + */ +uint_fast32_t SD_getSectorSize(SD_Handle handle) +{ + return (handle->fxnTablePtr->getSectorSizeFxn(handle)); +} + +/* + * ======== SD_init ======== + */ +void SD_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + + key = HwiP_disable(); + + if (!isInitialized) { + isInitialized = (bool) true; + + /* Call each driver's init function */ + for (i = 0; i < SD_count; i++) { + SD_config[i].fxnTablePtr->initFxn((SD_Handle)&(SD_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== SD_initialize ======== + */ +int_fast16_t SD_initialize(SD_Handle handle) +{ + return (handle->fxnTablePtr->initializeFxn(handle)); +} + +/* + * ======== SD_open ======== + */ +SD_Handle SD_open(uint_least8_t index, SD_Params *params) +{ + SD_Handle handle = NULL; + + /* Verify driver index and state */ + if (isInitialized && (index < SD_count)) { + /* If params are NULL use defaults */ + if (params == NULL) { + params = (SD_Params *) &SD_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (SD_Handle)&(SD_config[index]); + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== SD_Params_init ======== + */ +void SD_Params_init(SD_Params *params) +{ + *params = SD_defaultParams; +} + +/* + * ======== SD_read ======== + */ +int_fast16_t SD_read(SD_Handle handle, void *buf, + int_fast32_t sector, uint_fast32_t secCount) +{ + return (handle->fxnTablePtr->readFxn(handle, buf, sector, secCount)); +} + +/* + * ======== SD_write ======== + */ +int_fast16_t SD_write(SD_Handle handle, const void *buf, + int_fast32_t sector, uint_fast32_t secCount) +{ + return (handle->fxnTablePtr->writeFxn(handle, buf, sector, secCount)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SD.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SD.h new file mode 100644 index 0000000..ab05d92 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SD.h @@ -0,0 +1,509 @@ +/* + * Copyright (c) 2016-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!*************************************************************************** + * @file SD.h + * @brief Secure Digital (SD) Driver + * + * @anchor ti_drivers_SD_Overview + * # Overview + * + * The SD driver is designed to serve as an interface to perform basic + * transfers directly to the SD card. + * + *
+ * @anchor ti_drivers_SD_Usage + * # Usage + * This section will cover driver usage. + * + * @anchor ti_drivers_SD_Synopsis + * ## Synopsis + * @anchor ti_drivers_SD_Synopsis_Code + * @code + * SD_Handle handle; + * uint16_t status; + * + * SD_init(); + * + * // Open SD and initialize card + * handle = SD_open(Board_SD0, NULL); + * status = SD_initialize(handle); + * if (handle == NULL || status != SD_STATUS_SUCCESS) { + * //Error opening SD driver + * while (1); + * } + * + * // Write and read back the first sector + * status = SD_write(handle, sendBuffer, 0, 1); + * if (status == SD_STATUS_SUCCESS) { + * status = SD_read(handle, readBuffer, 0 , 1); + * } + * + * SD_close(handle); + * @endcode + * + * @anchor ti_drivers_SD_Examples + * # Examples + * - @ref ti_drivers_SD_Synopsis "Overview" + * - @ref ti_drivers_SD_Example_getCardSpace "Get SD card size" + * + * Get total capacity of an SD card: + * @anchor ti_drivers_SD_Example_getCardSpace + * @code + * SD_Handle handle; + * Display_Handle display; + * uint_fast32_t sectorSize, sectorCount; + * + * // Init, open, etc + * ... + * + * sectorSize = SD_getSectorSize(handle); + * sectorCount = SD_getNumSectors(handle); + * + * Display_printf(display, 0, 0,"SD card total capacity is %lu bytes.", + * sectorSize * sectorCount); + * @endcode + * + *
+ * @anchor ti_drivers_SD_Configuration + * # Configuration + * Refer to the @ref driver_configuration "Driver's Configuration" + * section for driver configuration information. + * + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_SD__include +#define ti_drivers_SD__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @defgroup SD_CONTROL SD_control command and status codes + * @{ + */ + +/*! + * Common SD_control() command code reservation offset. + * SD driver implementations should offset command codes with + * SD_CMD_RESERVED growing positively. + * + * Example implementation specific command codes: + * @code + * #define SDXYZ_CMD_COMMAND0 (SD_CMD_RESERVED + 0) + * #define SDXYZ_CMD_COMMAND1 (SD_CMD_RESERVED + 1) + * @endcode + */ +#define SD_CMD_RESERVED (32) + +/*! + * Common SD_control status code reservation offset. + * SD driver implementations should offset status codes with + * SD_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define SDXYZ_STATUS_ERROR0 (SD_STATUS_RESERVED - 0) + * #define SDXYZ_STATUS_ERROR1 (SD_STATUS_RESERVED - 1) + * #define SDXYZ_STATUS_ERROR2 (SD_STATUS_RESERVED - 2) + * @endcode + */ +#define SD_STATUS_RESERVED (-32) + +/** + * @defgroup SD_STATUS Status Codes + * SD_STATUS_* macros are general status codes returned by SD_control() + * @{ + * @ingroup SD_CONTROL + */ + +/*! + * @brief Successful status code returned by SD_control(). + * + * SD_control() returns SD_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define SD_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by SD_control(). + * + * SD_control() returns SD_STATUS_ERROR if the control code + * was not executed successfully. + */ +#define SD_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by SD_control() for + * undefined command codes. + * + * SD_control() returns SD_STATUS_UNDEFINEDCMD if the + * control code is not recognized by the driver implementation. + */ +#define SD_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup SD_CMD Command Codes + * SD_CMD_* macros are general command codes for SD_control(). Not all SD + * driver implementations support these command codes. + * @{ + * @ingroup SD_CONTROL + */ + +/* Add SD_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief SD Card type inserted + */ +typedef enum SD_CardType_ { + SD_NOCARD = 0, /*!< Unrecognized Card */ + SD_MMC = 1, /*!< Multi-media Memory Card (MMC) */ + SD_SDSC = 2, /*!< Standard SDCard (SDSC) */ + SD_SDHC = 3 /*!< High Capacity SDCard (SDHC) */ +} SD_CardType; + +/*! + * @brief A handle that is returned from a SD_open() call. + */ +typedef struct SD_Config_ *SD_Handle; + +/*! + * @brief SD Parameters + * + * SD Parameters are used to with the SD_open() call. + * Default values for these parameters are set using SD_Params_init(). + * + * @sa SD_Params_init() + */ + +/* SD Parameters */ +typedef struct SD_Params_ { + void *custom; /*!< Custom argument used by driver implementation */ +} SD_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_CloseFxn(). + */ +typedef void (*SD_CloseFxn) (SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_controlFxn(). + */ +typedef int_fast16_t (*SD_ControlFxn) (SD_Handle handle, + uint_fast16_t cmd, void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_getNumSectorsFxn(). + */ +typedef uint_fast32_t (*SD_getNumSectorsFxn) (SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_getSectorSizeFxn(). + */ +typedef uint_fast32_t (*SD_getSectorSizeFxn) (SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_InitFxn(). + */ +typedef void (*SD_InitFxn) (SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_initializeFxn(). + */ +typedef int_fast16_t (*SD_InitializeFxn) (SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_OpenFxn(). + */ +typedef SD_Handle (*SD_OpenFxn) (SD_Handle handle, SD_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_readFxn(). + */ +typedef int_fast16_t (*SD_ReadFxn) (SD_Handle handle, void *buf, + int_fast32_t sector, uint_fast32_t secCount); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_writeFxn(). + */ +typedef int_fast16_t (*SD_WriteFxn) (SD_Handle handle, const void *buf, + int_fast32_t sector, uint_fast32_t secCount); + +/*! + * @brief The definition of a SD function table that contains the + * required set of functions to control a specific SD driver + * implementation. + */ +typedef struct SD_FxnTable_ { + /*! Function to close the specified peripheral */ + SD_CloseFxn closeFxn; + /*! Function to implementation specific control function */ + SD_ControlFxn controlFxn; + /*! Function to return the total number of sectors on the SD card */ + SD_getNumSectorsFxn getNumSectorsFxn; + /*! Function to return the sector size used to address the SD card */ + SD_getSectorSizeFxn getSectorSizeFxn; + /*! Function to initialize the given data object */ + SD_InitFxn initFxn; + /*! Function to initialize the SD card */ + SD_InitializeFxn initializeFxn; + /*! Function to open the specified peripheral */ + SD_OpenFxn openFxn; + /*! Function to read from the SD card */ + SD_ReadFxn readFxn; + /*! Function to write to the SD card */ + SD_WriteFxn writeFxn; +} SD_FxnTable; + +/*! + * @brief SD Global configuration + * + * The SD_Config structure contains a set of pointers used + * to characterize the SD driver implementation. + * + * This structure needs to be defined before calling SD_init() and it must + * not be changed thereafter. + * + * @sa SD_init() + */ +typedef struct SD_Config_ { + /*! Pointer to a table of driver-specific implementations of SD APIs */ + SD_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} SD_Config; + +/*! + * @brief Function to close a SD peripheral specified by the SD handle. + * + * @pre SD_open() had to be called first. + * + * @param handle A #SD_Handle returned from SD_open() + * + * @sa SD_open() + */ +extern void SD_close(SD_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * #SD_Handle. + * + * Commands for SD_control can originate from SD.h or from implementation + * specific SD*.h files. + * While commands from SD.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific SD*.h files add + * unique driver capabilities but are not API portable across all SD driver + * implementations. + * + * Commands supported by SD.h follow a SD*_CMD naming + * convention. + * + * Commands supported by SD*.h follow a SD*_CMD naming + * convention. + * Each control command defines arg differently. The types of arg are + * documented with each command. + * + * See @ref SD_CMD "SD_control command codes" for command codes. + * + * See @ref SD_STATUS "SD_control return status codes" for status codes. + * + * @pre SD_open() has to be called first. + * + * @param handle A #SD_Handle returned from SD_open(). + * + * @param cmd SD.h or SD*.h commands. + * + * @param arg An optional R/W (read/write) command argument + * accompanied with cmd. + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa SD_open() + */ +extern int_fast16_t SD_control(SD_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_getNumSectors(). + * Note: Total Card capacity is the (NumberOfSectors * SectorSize). + * + * @pre SD Card has been initialized using SD_initialize(). + * + * @param handle A #SD_Handle returned from SD_open(). + * + * @return The total number of sectors on the SD card, + * or 0 if an error occurred. + * + * @sa SD_initialize() + */ +extern uint_fast32_t SD_getNumSectors(SD_Handle handle); + +/*! + * @brief Function to obtain the sector size used to access the SD card. + * + * @pre SD Card has been initialized using SD_initialize(). + * + * @param handle A #SD_Handle returned from SD_open(). + * + * @return The sector size set for use during SD card read/write operations. + * + * @sa SD_initialize() + */ +extern uint_fast32_t SD_getSectorSize(SD_Handle handle); + +/*! + * @brief This function initializes the SD driver. + * + * @pre The SD_config[] array must exist and be persistent before this + * function can be called. This function must also be called before + * any other SD driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void SD_init(void); + +/*! + * @brief Function to initialize the #SD_Params struct to its defaults. + * + * @param params A pointer to #SD_Params structure for initialization. + */ +extern void SD_Params_init(SD_Params *params); + + /*! + * @brief A function pointer to a driver specific implementation of + * SD_initialize(). + * + * @pre SD controller has been opened by calling SD_open(). + * + * @param handle A #SD_Handle returned from SD_open(). + * + * @return #SD_STATUS_SUCCESS if no errors occurred during the initialization, + * #SD_STATUS_ERROR otherwise. + */ +extern int_fast16_t SD_initialize(SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_open(). + * + * @pre SD controller has been initialized using SD_init(). + * + * @param index Logical peripheral number for the SD indexed into + * the SD_config[] table. + * + * @param params Pointer to a parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A #SD_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa SD_init() + * @sa SD_close() + */ +extern SD_Handle SD_open(uint_least8_t index, SD_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_read(). + * + * @pre SD controller has been opened and initialized by calling SD_open() + * followed by SD_initialize(). + * + * @param handle A #SD_Handle returned from SD_open(). + * + * @param buf Pointer to a buffer to read data into. + * + * @param sector Starting sector on the disk to read from. + * + * @param secCount Number of sectors to be read. + * + * @return #SD_STATUS_SUCCESS if no errors occurred during the write, + * #SD_STATUS_ERROR otherwise. + * + * @sa SD_initialize() + */ +extern int_fast16_t SD_read(SD_Handle handle, void *buf, + int_fast32_t sector, uint_fast32_t secCount); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_write(). + * + * @pre SD controller has been opened and initialized by calling SD_open() + * followed by SD_initialize(). + * + * @param handle A #SD_Handle returned from SD_open(). + * + * @param buf Pointer to a buffer containing data to write to disk. + * + * @param sector Starting sector on the disk to write to. + * + * @param secCount Number of sectors to be written. + * + * @return #SD_STATUS_SUCCESS if no errors occurred during the write, + * #SD_STATUS_ERROR otherwise. + * + * @sa SD_initialize() + */ +extern int_fast16_t SD_write(SD_Handle handle, const void *buf, + int_fast32_t sector, uint_fast32_t secCount); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_SD__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SDFatFS.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SDFatFS.c new file mode 100644 index 0000000..12fcf10 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SDFatFS.c @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2016-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/* + * By default disable both asserts and log for this module. + * This must be done before DebugP.h is included. + */ +#ifndef DebugP_ASSERT_ENABLED +#define DebugP_ASSERT_ENABLED 0 +#endif +#ifndef DebugP_LOG_ENABLED +#define DebugP_LOG_ENABLED 0 +#endif + +#include +#include +#include +#include + +#include + +/* SDFatFS Specific Defines */ +#define DRIVE_NOT_MOUNTED (~(0U)) + +extern const SDFatFS_Config SDFatFS_config[]; +extern const uint_least8_t SDFatFS_count; + +static bool isInitialized = false; + +/* + * Array of SDFatFS_Handles to determine the association of the + * FatFs drive number with a SDFatFS_Handle. + * FF_VOLUMES is defined in . + */ +static SDFatFS_Handle sdFatFSHandles[FF_VOLUMES]; + +/* FatFS function prototypes */ +DSTATUS SDFatFS_diskInitialize(BYTE drive); +DRESULT SDFatFS_diskIOctrl(BYTE drive, BYTE ctrl, void *buffer); +DRESULT SDFatFS_diskRead(BYTE drive, BYTE *buffer, + DWORD sector, UINT secCount); +DSTATUS SDFatFS_diskStatus(BYTE drive); +DRESULT SDFatFS_diskWrite(BYTE drive, const BYTE *buffer, + DWORD sector, UINT secCount); + +/* + * ======== SDFatFS_close ======== + */ +void SDFatFS_close(SDFatFS_Handle handle) +{ + TCHAR path[3]; + DRESULT dresult; + FRESULT fresult; + SDFatFS_Object *obj = handle->object; + + /* Construct base directory path */ + path[0] = (TCHAR)'0' + obj->driveNum; + path[1] = (TCHAR)':'; + path[2] = (TCHAR)'\0'; + + /* Close the SD driver */ + SD_close(obj->sdHandle); + + /* Unmount the FatFs drive */ + fresult = f_mount(NULL, path, 0); + if (fresult != FR_OK) { + DebugP_log1("SDFatFS: Could not unmount FatFs volume @ drive" + " number %d", obj->driveNum); + } + + /* Unregister the disk_*() functions */ + dresult = disk_unregister(obj->driveNum); + if (dresult != RES_OK) { + DebugP_log1("SDFatFS: Error unregistering disk" + " functions @ drive number %d", obj->driveNum); + } + + obj->driveNum = DRIVE_NOT_MOUNTED; + DebugP_log0("SDFatFS closed"); +} + +/* + * ======== SDFatFS_diskInitialize ======== + */ +DSTATUS SDFatFS_diskInitialize(BYTE drive) +{ + int_fast8_t result; + SDFatFS_Object *obj = sdFatFSHandles[drive]->object; + + result = SD_initialize(obj->sdHandle); + + /* Convert lower level driver status code */ + if (result == SD_STATUS_SUCCESS) { + obj->diskState = ((DSTATUS) obj->diskState) & ~((DSTATUS)STA_NOINIT); + } + + return (obj->diskState); +} + +/* + * ======== SDFatFS_diskIOctrl ======== + * Function to perform specified disk operations. This function is called by the + * FatFs module and must not be called by the application! + */ +DRESULT SDFatFS_diskIOctrl(BYTE drive, BYTE ctrl, void *buffer) +{ + SDFatFS_Object *obj = sdFatFSHandles[drive]->object; + DRESULT fatfsRes = RES_ERROR; + + switch (ctrl) { + case CTRL_SYNC: + fatfsRes = RES_OK; + break; + + case (BYTE)GET_SECTOR_COUNT: + *(uint32_t*)buffer = (uint32_t)SD_getNumSectors(obj->sdHandle); + + DebugP_log1("SDFatFS: Disk IO control: sector count: %d", + *(uint32_t*)buffer); + fatfsRes = RES_OK; + break; + + case (BYTE)GET_SECTOR_SIZE: + *(WORD*)buffer = (WORD)SD_getSectorSize(obj->sdHandle); + DebugP_log1("SDFatFS: Disk IO control: sector size: %d", + *(WORD*)buffer); + fatfsRes = RES_OK; + break; + + case (BYTE)GET_BLOCK_SIZE: + *(WORD*)buffer = (WORD)SD_getSectorSize(obj->sdHandle); + DebugP_log1("SDFatFS: Disk IO control: block size: %d", + *(WORD*)buffer); + fatfsRes = RES_OK; + break; + + default: + DebugP_log0("SDFatFS: Disk IO control parameter error"); + fatfsRes = RES_PARERR; + break; + } + return (fatfsRes); +} + +/* + * ======== SDFatFS_diskRead ======== + * Function to perform a disk read from the SDCard. This function is called by + * the FatFs module and must not be called by the application! + */ +DRESULT SDFatFS_diskRead(BYTE drive, BYTE *buffer, + DWORD sector, UINT secCount) +{ + int_fast32_t result; + DRESULT fatfsRes = RES_ERROR; + SDFatFS_Object *obj = sdFatFSHandles[drive]->object; + + /* Return if disk not initialized */ + if ((obj->diskState & (DSTATUS)STA_NOINIT) != 0) { + fatfsRes = RES_PARERR; + } + else { + result = SD_read(obj->sdHandle, (uint_least8_t *)buffer, + (int_least32_t)sector, (uint_least32_t)secCount); + + /* Convert lower level driver status code */ + if (result == SD_STATUS_SUCCESS) { + fatfsRes = RES_OK; + } + } + + return (fatfsRes); +} + +/* + * ======== SDFatFS_diskStatus ======== + * Function to return the current disk status. This function is called by + * the FatFs module and must not be called by the application! + */ +DSTATUS SDFatFS_diskStatus(BYTE drive) +{ + return (((SDFatFS_Object *)sdFatFSHandles[drive]->object)->diskState); +} + + +#if (_READONLY == 0) +/* + * ======== SDFatFS_diskWrite ======== + * Function to perform a write to the SDCard. This function is called by + * the FatFs module and must not be called by the application! + */ +DRESULT SDFatFS_diskWrite(BYTE drive, const BYTE *buffer, DWORD sector, + UINT secCount) +{ + int_fast32_t result; + DRESULT fatfsRes = RES_ERROR; + SDFatFS_Object *obj = sdFatFSHandles[drive]->object; + + /* Return if disk not initialized */ + if ((obj->diskState & (DSTATUS)STA_NOINIT) != 0) { + fatfsRes = RES_PARERR; + } + else { + result = SD_write(obj->sdHandle, (const uint_least8_t *)buffer, + (int_least32_t)sector, (uint_least32_t)secCount); + + /* Convert lower level driver status code */ + if (result == SD_STATUS_SUCCESS) { + fatfsRes = RES_OK; + } + } + + return (fatfsRes); +} +#endif + +/* + * ======== SDFatFS_init ======== + */ +void SDFatFS_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + SDFatFS_Object *obj; + + key = HwiP_disable(); + + if (!isInitialized) { + isInitialized = (bool) true; + + /* Initialize each SDFatFS object */ + for (i = 0; i < SDFatFS_count; i++) { + obj = ((SDFatFS_Handle)&(SDFatFS_config[i]))->object; + + obj->diskState = STA_NOINIT; + obj->driveNum = DRIVE_NOT_MOUNTED; + } + + /* Initialize the SD Driver */ + SD_init(); + } + + HwiP_restore(key); +} + + +/* + * ======== SDFatFS_open ======== + * Note: The index passed into this function must correspond directly + * to the SD driver index. + */ +SDFatFS_Handle SDFatFS_open(uint_least8_t idx, uint_least8_t drive) +{ + uintptr_t key; + DRESULT dresult; + FRESULT fresult; + TCHAR path[3]; + SDFatFS_Handle handle = NULL; + SDFatFS_Object *obj; + + /* Verify driver index and state */ + if (isInitialized && (idx < SDFatFS_count)) { + /* Get handle for this driver instance */ + handle = (SDFatFS_Handle)&(SDFatFS_config[idx]); + obj = handle->object; + + /* Determine if the device was already opened */ + key = HwiP_disable(); + if (obj->driveNum != DRIVE_NOT_MOUNTED) { + HwiP_restore(key); + DebugP_log1("SDFatFS Drive %d already in use!", obj->driveNum); + handle = NULL; + } + else { + obj->driveNum = drive; + + /* Open SD Driver */ + obj->sdHandle = SD_open(idx, NULL); + + HwiP_restore(key); + + if (obj->sdHandle == NULL) { + obj->driveNum = DRIVE_NOT_MOUNTED; + /* Error occurred in lower level driver */ + handle = NULL; + } + else { + + /* Register FATFS Functions */ + dresult = disk_register(obj->driveNum, + SDFatFS_diskInitialize, + SDFatFS_diskStatus, + SDFatFS_diskRead, + SDFatFS_diskWrite, + SDFatFS_diskIOctrl); + + /* Check for drive errors */ + if (dresult != RES_OK) { + DebugP_log0("SDFatFS: Disk functions not registered"); + SDFatFS_close(handle); + handle = NULL; + } + else { + + /* Construct base directory path */ + path[0] = (TCHAR)'0' + obj->driveNum; + path[1] = (TCHAR)':'; + path[2] = (TCHAR)'\0'; + + /* + * Register the filesystem with FatFs. This operation does + * not access the SDCard yet. + */ + fresult = f_mount(&(obj->filesystem), path, 0); + if (fresult != FR_OK) { + DebugP_log1("SDFatFS: Drive %d not mounted", + obj->driveNum); + + SDFatFS_close(handle); + handle = NULL; + } + else { + + /* + * Store the new sdfatfs handle for the input drive + * number + */ + sdFatFSHandles[obj->driveNum] = handle; + + DebugP_log0("SDFatFS: opened"); + } + } + } + } + } + + return (handle); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SDFatFS.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SDFatFS.h new file mode 100644 index 0000000..4f74643 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SDFatFS.h @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2016-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file SDFatFS.h + * + * @brief File Allocation Table File System (FATFS) Driver + * + * The SDFatFS header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * @anchor ti_drivers_SDFatFS_Overview + * # Overview # + * + * The SDFatFS driver is designed to hook into FatFs by implementing a + * set of functions that FatFs needs to call to perform basic block data + * transfers. This driver makes use of the SD driver for lower level disk IO + * operations. + * + * The only functions that should be called by the application are the + * standard driver framework functions (_open, _close, etc...). + * + * The application may use the FatFs APIs or the standard C + * runtime file I/O calls (fopen, fclose, etc...) given that SDFatFS_open has + * has been successfully called. After the SDFatFS_close API is called, + * ensure the application does NOT make any file I/O calls. + * + * ## Opening the driver # + * + * @code + * SDFatFS_Handle handle; + * + * handle = SDFatFS_open(Board_SDFatFS0, driveNum, NULL); + * if (handle == NULL) { + * //Error opening SDFatFS driver + * while (1); + * } + * @endcode + * + * # Instrumentation # + * + * The SDFatFS driver interface produces log statements if + * instrumentation is enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic operations performed | + * Diags_USER2 | detailed operations performed | + * ============================================================================ + */ + +#ifndef ti_drivers_SDFatFS__include +#define ti_drivers_SDFatFS__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#include + +#include +#include + +/*! + * @brief SDFatFS Object + * The application must not access any member variables of this structure! + */ +typedef struct SDFatFS_Object_ { + uint_fast32_t driveNum; + DSTATUS diskState; + FATFS filesystem; /* FATFS data object */ + SD_Handle sdHandle; +} SDFatFS_Object; + +/*! + * @brief A handle that is returned from a SDFatFS_open() call. + */ +typedef struct SDFatFS_Config_ *SDFatFS_Handle; + + +/*! + * @brief SDFatFS Global configuration + * + * The #SDFatFS_Config structure contains a single pointer used to characterize + * the SDFatFS driver implementation. + * + * This structure needs to be defined before calling SDFatFS_init() and it must + * not be changed thereafter. + * + * @sa SDFatFS_init() + */ +typedef struct SDFatFS_Config_ { + /*! Pointer to a SDFatFS object */ + void *object; +} SDFatFS_Config; + +/*! + * @brief Function to open a SDFatFS instance on the specified drive. + * + * Function to mount the FatFs filesystem and register the SDFatFS disk + * I/O functions with the FatFS module. + * + * @param idx Logical peripheral number indexed into the HWAttrs + * table. + * @param drive Drive Number + */ +extern SDFatFS_Handle SDFatFS_open(uint_least8_t idx, uint_least8_t drive); + +/*! + * @brief Function to close a SDFatFS instance specified by the SDFatFS + * handle. + * + * This function unmounts the file system mounted by SDFatFS_open() and + * unregisters the SDFatFS driver from the FatFs module. + * + * @pre SDFatFS_open() had to be called first. + * + * @param handle A #SDFatFS_Handle returned from SDFatFS_open() + * + * @sa SDFatFS_open() + */ +extern void SDFatFS_close(SDFatFS_Handle handle); + +/*! + * Function to initialize a SDFatFS instance + */ +extern void SDFatFS_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_SDFatFS__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SHA2.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SHA2.c new file mode 100644 index 0000000..08df2c8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SHA2.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2017, 2018 Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== SHA2.c ======== + * + * This file contains default values for the SHA2_Params struct. + * + */ + +#include +#include + +const SHA2_Params SHA2_defaultParams = +{ + .hashType = SHA2_HASH_TYPE_256, + .returnBehavior = SHA2_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = (uint32_t)SemaphoreP_WAIT_FOREVER, +}; + +void SHA2_Params_init(SHA2_Params *params) +{ + *params = SHA2_defaultParams; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SHA2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SHA2.h new file mode 100644 index 0000000..29e6366 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SHA2.h @@ -0,0 +1,612 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file SHA2.h + * + * @brief SHA2 driver header + * + * @warning This is a beta API. It may change in future releases. + * + * @anchor ti_drivers_SHA2_Overview + * # Overview # + * + * SHA2 (Secure Hash Algorithm 2) is a cryptographic hashing algorithm that + * maps an input of arbitrary length to a fixed-length output with negligible + * probability of collision. A collision would occur when two different inputs + * map to the same output. + * + * It is not currently technologicaly feasible to derive an input from + * the hash digest (output) itself. + * + * Hashes are often used to ensure the integrity of messages. They are also + * used to as constituent parts of more complicated cyptographic schemes. + * HMAC is a message authentication code that is based on hash functions such + * as SHA2 rather than a block cipher. + * Hashes may themselves be used as or form a part of key derivation functions + * used to derive symmetric keys from sources of entropy such as an Elliptic + * Curve Diffie-Helman key exchange (ECDH). + * + * SHA2 is not actually a single algorithm, but a suite of similar algorithms + * that produce hash digests of different lengths. 224, 256, 384, and 512-bit + * outputs are available. + * + * "Hash" may refer to either the process of hashing when used as a verb and + * the output digest when used as a noun. + * + * @anchor ti_drivers_SHA2_Usage + * # Usage # + * + * Before starting a SHA2 operation, the application must do the following: + * - Call #SHA2_init() to initialize the driver + * - Call #SHA2_Params_init() to initialize the SHA2_Params to default values. + * - Modify the #SHA2_Params as desired + * - Call #SHA2_open() to open an instance of the driver + * + * There are two general ways to execute a SHA2 operation: + * + * - one-step (in one operation) + * - multi-step (multiple partial operations) + + * @anchor ti_drivers_SHA2_Synopsis + * # Synopsis + * + * @anchor ti_drivers_SHA2_Synopsis_Code + * @code + * + * // Import SHA2 Driver definitions + * #include + * + * // Define name for SHA2 channel index + * #define SHA2_INSTANCE 0 + * + * SHA2_init(); + * + * handle = SHA2_open(SHA2_INSTANCE, NULL); + * + * result = SHA2_hashData(handle, message, strlen(message), actualDigest); + * + * SHA2_close(handle); + * @endcode + * + * @anchor ti_drivers_SHA2_Examples + * # Examples # + * + * ## One-step hash operation # + * + * The #SHA2_hashData() function can perform a SHA2 operation in a single call. + * It will always use the most highly optimized routine with the least overhead and + * the fastest runtime. However, it requires that the entire input message is + * available to the function in a contiguous location at the start of the call. + * The single call operation is required when hashing a message with a length smaller + * than or equal to one hash-block length. All devices support single call operations. + * + * After a SHA2 operation completes, the application may either start + * another operation or close the driver by calling #SHA2_close(). + * + * @code + * SHA2_Params params; + * SHA2_Handle handle; + * int_fast16_t result; + * + * char message[] = "A Ferengi without profit is no Ferengi at all."; + * + * uint8_t actualDigest[SHA2_DIGEST_LENGTH_BYTES_256]; + * uint8_t expectedDigest[] = { + * 0x93, 0xD6, 0x5C, 0x07, + * 0xA6, 0x26, 0x88, 0x9C, + * 0x87, 0xCC, 0x82, 0x24, + * 0x47, 0xC6, 0xE4, 0x28, + * 0xC0, 0xBD, 0xC6, 0xED, + * 0xAA, 0x8C, 0xD2, 0x53, + * 0x77, 0xAA, 0x73, 0x14, + * 0xA3, 0xE2, 0xDE, 0x43 + * }; + * + * SHA2_init(); + * + * SHA2_Params_init(¶ms); + * params.returnBehavior = SHA2_RETURN_BEHAVIOR_BLOCKING; + * handle = SHA2_open(0, ¶ms); + * assert(handle != NULL); + * + * result = SHA2_hashData(handle, message, strlen(message), actualDigest); + * assert(result == SHA2_STATUS_SUCCESS); + * + * result = memcmp(actualDigest, expectedDigest, SHA2_DIGEST_LENGTH_BYTES_256); + * assert(result == 0); + * + * SHA2_close(handle); + * @endcode + * + * ## Partial hash operation # + * + * When trying to operate on data that is too large to fit into available memory, + * partial processing is more advisable. The segments are processed with + * #SHA2_addData() whereas the final digest is computed by #SHA2_finalize(). + * + * @code + * SHA2_Handle handle; + * int_fast16_t result; + * SHA2_Params params; + * + * const char message[] = + * "Premature optimization is the root of all evil (or at least most of it) in programming."; + * + * uint8_t actualDigest[SHA2_DIGEST_LENGTH_BYTES_256]; + * uint8_t expectedDigest[] = { + * 0xF2, 0x6A, 0xFF, 0x01, + * 0x11, 0x6B, 0xF6, 0x77, + * 0x63, 0x91, 0xFE, 0xD9, + * 0x47, 0x56, 0x99, 0xB2, + * 0xAD, 0x7D, 0x64, 0x16, + * 0xF7, 0x40, 0x1A, 0x5B, + * 0xCC, 0xC7, 0x08, 0x3D, + * 0xE8, 0x6B, 0x35, 0x6D, + * }; + * + * SHA2_init(); + * + * SHA2_Params_init(¶ms); + * params.returnBehavior = SHA2_RETURN_BEHAVIOR_BLOCKING; + * handle = SHA2_open(0, ¶ms); + * assert(handle != NULL); + * + * // We can configure the driver even after SHA2_open() + * result = SHA2_setHashType(handle, SHA2_HASH_TYPE_256); + * assert(result == SHA2_STATUS_SUCCESS); + * + * // Process data in chunks. The driver buffers incomplete blocks internally. + * result = SHA2_addData(handle, &message[0], 17); + * assert(result == SHA2_STATUS_SUCCESS); + * + * result = SHA2_addData(handle, &message[17], strlen(message) - 17); + * assert(result == SHA2_STATUS_SUCCESS); + * + * // Compute the resulting digest + * result = SHA2_finalize(handle, actualDigest); + * assert(result == SHA2_STATUS_SUCCESS); + * + * // Verify + * result = memcmp(actualDigest, expectedDigest, SHA2_DIGEST_LENGTH_BYTES_256); + * assert(result == 0); + * + * SHA2_close(handle); + * @endcode + * + */ + +#ifndef ti_drivers_SHA2__include +#define ti_drivers_SHA2__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common SHA2 status code reservation offset. + * SHA2 driver implementations should offset status codes with + * SHA2_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define SHA2XYZ_STATUS_ERROR0 SHA2_STATUS_RESERVED - 0 + * #define SHA2XYZ_STATUS_ERROR1 SHA2_STATUS_RESERVED - 1 + * #define SHA2XYZ_STATUS_ERROR2 SHA2_STATUS_RESERVED - 2 + * @endcode + */ +#define SHA2_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return SHA2_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define SHA2_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return SHA2_STATUS_ERROR if the function was not executed + * successfully and no more specific error is applicable. + */ +#define SHA2_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * SHA2 driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define SHA2_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief The ongoing operation was canceled. + */ +#define SHA2_STATUS_CANCELED (-3) + +/*! + * @brief The way in which SHA2 function calls return after performing an + * operation. + * + * Not all SHA2 operations exhibit the specified return behavor. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specfied return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * SHA2 functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |SHA2_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |SHA2_RETURN_BEHAVIOR_BLOCKING | X | | | + * |SHA2_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum { + SHA2_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * SHA2 operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + SHA2_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the SHA2 operation goes + * on in the background. SHA2 operation results are available + * after the function returns. + */ + SHA2_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while the SHA2 + * operation goes on in the background. SHA2 operation results + * are available after the function returns. + */ +} SHA2_ReturnBehavior; + +/*! + * @brief Enum for the hash types supported by the driver. + */ +typedef enum { + SHA2_HASH_TYPE_224 = 0, + SHA2_HASH_TYPE_256 = 1, + SHA2_HASH_TYPE_384 = 2, + SHA2_HASH_TYPE_512 = 3, +} SHA2_HashType; + +/*! + * @brief Enum for the hash digest lengths in bytes supported by the driver. + */ +typedef enum { + SHA2_DIGEST_LENGTH_BYTES_224 = 28, + SHA2_DIGEST_LENGTH_BYTES_256 = 32, + SHA2_DIGEST_LENGTH_BYTES_384 = 48, + SHA2_DIGEST_LENGTH_BYTES_512 = 64, +} SHA2_DigestLengthBytes; + +/*! + * @brief Enum for the block sizes of the algorithms. + * + * SHA2 iteratively consumes segments of the block + * size and computes intermediate digests which are + * fed back into the algorithm together with the next + * segment to compute the next intermediate or final + * digest. + * The block sizes of the algorithms differ from their + * digest lengths. When performing partial hashes, + * the segment lengths for all but the last segment + * must be multiples of the relevant block size. + */ +typedef enum { + SHA2_BLOCK_SIZE_BYTES_224 = 64, + SHA2_BLOCK_SIZE_BYTES_256 = 64, + SHA2_BLOCK_SIZE_BYTES_384 = 128, + SHA2_BLOCK_SIZE_BYTES_512 = 128, +} SHA2_BlockSizeBytes; + +/*! + * @brief SHA2 Global configuration + * + * The %SHA2_Config structure contains a set of pointers used to characterize + * the SHA2 driver implementation. + * + * This structure needs to be defined before calling #SHA2_init() and it must + * not be changed thereafter. + * + * @sa SHA2_init() + */ +typedef struct SHA2_Config { + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} SHA2_Config; + +/*! + * @brief A handle that is returned from an SHA2_open() call. + */ +typedef SHA2_Config* SHA2_Handle; + +/*! + * @brief The definition of a callback function used by the SHA2 driver + * when used in ::SHA2_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the SHA2 operation. + * + * @param returnStatus The result of the SHA2 operation. May contain an error code. + * Informs the application of why the callback function was + * called. + */ +typedef void (*SHA2_CallbackFxn) (SHA2_Handle handle, int_fast16_t returnStatus); + +/*! + * @brief SHA2 Parameters + * + * SHA2 Parameters are used to with the SHA2_open() call. Default values for + * these parameters are set using SHA2_Params_init(). + * + * @sa SHA2_Params_init() + */ +typedef struct { + SHA2_HashType hashType; /*!< SHA2 variant to use. This determines the output digest + * length. + */ + SHA2_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + SHA2_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::SHA2_RETURN_BEHAVIOR_BLOCKING + */ +} SHA2_Params; + +/*! + * \brief Global SHA2 configuration struct. + * + * Specifies context objects and hardware attributes for every + * driver instance. + * + * This variable is supposed to be defined in the board file. + */ +extern const SHA2_Config SHA2_config[]; + +/*! + * \brief Global SHA2 configuration count. + * + * Specifies the amount of available SHA2 driver instances. + * + * This variable is supposed to be defined in the board file. + */ +extern const uint_least8_t SHA2_count; + +/*! + * @brief Default SHA2_Params structure + * + * @sa #SHA2_Params_init() + */ +extern const SHA2_Params SHA2_defaultParams; + + +/*! + * @brief Initializes the SHA2 driver module. + * + * @pre The #SHA2_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other SHA2 driver APIs. This function call does not modify any + * peripheral registers. + */ +void SHA2_init(void); + +/*! + * @brief Initializes \a params with default values. + * + * @param params A pointer to #SHA2_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = SHA2_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void SHA2_Params_init(SHA2_Params *params); + +/*! + * @brief Initializes a SHA2 driver instance and returns a handle. + * + * @pre SHA2 controller has been initialized using #SHA2_init() + * + * @param index Logical peripheral number for the SHA2 indexed into + * the #SHA2_config table + * + * @param params Pointer to a parameter block, if NULL it will use + * default values. + * + * @return A #SHA2_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa #SHA2_init(), #SHA2_close() + */ +SHA2_Handle SHA2_open(uint_least8_t index, const SHA2_Params *params); + +/*! + * @brief Closes a SHA2 peripheral specified by \a handle. + * + * @pre #SHA2_open() has to be called first. + * + * @param handle A #SHA2_Handle returned from SHA2_open() + * + * @sa #SHA2_open() + */ +void SHA2_close(SHA2_Handle handle); + +/*! + * @brief Adds a segment of \a data with a \a length in bytes to the cryptographic hash. + * + * %SHA2_addData() may be called arbitrary times before finishing the operation with + * #SHA2_finalize(). + * + * This function blocks until the final digest hash been computed. + * It returns immediately when ::SHA2_RETURN_BEHAVIOR_CALLBACK is set. + * + * + * @pre #SHA2_open() has to be called first. + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @param data Pointer to the location to read from. + * There might be alignment restrictions on different platforms. + * + * @param length Length of the message segment to hash, in bytes. + * + * @retval #SHA2_STATUS_SUCCESS The hash operation succeeded. + * @retval #SHA2_STATUS_ERROR The hash operation failed. + * @retval #SHA2_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #SHA2_STATUS_CANCELED The hash operation was canceled. + * + * @sa #SHA2_open(), #SHA2_reset(), #SHA2_finalize() + */ +int_fast16_t SHA2_addData(SHA2_Handle handle, const void* data, size_t length); + +/*! + * @brief Hashes a segment of \a data with a \a size in bytes and writes the + * resulting hash to \a digest. + * + * The digest content is computed in one step. Intermediate data from a previous + * partial operation started with #SHA2_addData() is discarded. + * + * This function blocks until the final digest hash been computed. + * It returns immediately when ::SHA2_RETURN_BEHAVIOR_CALLBACK is set. + * + * @pre #SHA2_open() has to be called first. + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @param data Pointer to the location to read from. + * There might be alignment restrictions on different platforms. + * + * @param size Length of the message segment to hash, in bytes. + * + * @param digest Pointer to the location to write the digest to. + * There might be alignment restrictions on different platforms. + * + * @retval #SHA2_STATUS_SUCCESS The hash operation succeeded. + * @retval #SHA2_STATUS_ERROR The hash operation failed. + * @retval #SHA2_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #SHA2_STATUS_CANCELED The hash operation was canceled. + * + * @sa #SHA2_open() + */ +int_fast16_t SHA2_hashData(SHA2_Handle handle, const void* data, size_t size, void *digest); + +/*! + * @brief Finishes hash a operation and writes the result to \a digest. + * + * This function finishes a hash operation that has been previously started + * by #SHA2_addData(). + * + * This function blocks until the final digest hash been computed. + * It returns immediately when ::SHA2_RETURN_BEHAVIOR_CALLBACK is set. + * + * @pre #SHA2_addData() has to be called first. + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @param digest Pointer to the location to write the digest to. + * + * @retval #SHA2_STATUS_SUCCESS The hash operation succeeded. + * @retval #SHA2_STATUS_ERROR The hash operation failed. + * @retval #SHA2_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #SHA2_STATUS_CANCELED The hash operation was canceled. + * + * @sa #SHA2_open(), #SHA2_addData() + */ +int_fast16_t SHA2_finalize(SHA2_Handle handle, void *digest); + +/*! + * @brief Clears internal buffers and aborts an ongoing SHA2 operation. + * + * Clears all internal buffers and the intermediate digest of this driver instance. + * If an asynchronous operation is ongoing, the behavior is the same as for + * #SHA2_cancelOperation(). + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @sa #SHA2_cancelOperation() + */ +void SHA2_reset(SHA2_Handle handle); + +/*! + * @brief Aborts an ongoing SHA2 operation and clears internal buffers. + * + * Aborts an ongoing hash operation of this driver instance. The operation will + * terminate as though an error occured and the status code of the operation will be + * #SHA2_STATUS_CANCELED in this case. + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @retval #SHA2_STATUS_SUCCESS The operation was canceled. + * @retval #SHA2_STATUS_ERROR The operation was not canceled. There may be no operation to cancel. + */ +int_fast16_t SHA2_cancelOperation(SHA2_Handle handle); + +/*! + * @brief Selects a new hash algorithm \a type. + * + * This function changes the hash algorithm type of the hash digest at + * run-time. The hash type is usually specified during #SHA2_open(). + * + * Neither is it allowed to call this function during a running hash operation + * nor during an incomplete multistep hash operation. In this case + * #SHA2_STATUS_ERROR would be returned. + * + * @pre #SHA2_open() has to be called first. + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @param type New hash algorithm type + * + * @retval #SHA2_STATUS_SUCCESS Hash type set correctly. + * @retval #SHA2_STATUS_ERROR Error. Platform may not support this hash type. + */ +int_fast16_t SHA2_setHashType(SHA2_Handle handle, SHA2_HashType type); + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_SHA2__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SPI.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SPI.c new file mode 100644 index 0000000..947d1b0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SPI.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== SPI.c ======== + */ + +#include +#include +#include +#include + +#include +#include + +extern const SPI_Config SPI_config[]; +extern const uint_least8_t SPI_count; + +/* Default SPI parameters structure */ +const SPI_Params SPI_defaultParams = { + SPI_MODE_BLOCKING, /* transferMode */ + SPI_WAIT_FOREVER, /* transferTimeout */ + NULL, /* transferCallbackFxn */ + SPI_MASTER, /* mode */ + 1000000, /* bitRate */ + 8, /* dataSize */ + SPI_POL0_PHA0, /* frameFormat */ + NULL /* custom */ +}; + +static bool isInitialized = false; + +/* + * ======== SPI_close ======== + */ +void SPI_close(SPI_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== SPI_control ======== + */ +int_fast16_t SPI_control(SPI_Handle handle, uint_fast16_t cmd, void *controlArg) +{ + return (handle->fxnTablePtr->controlFxn(handle, cmd, controlArg)); +} + +/* + * ======== SPI_init ======== + */ +void SPI_init(void) +{ + uint_least8_t i; + uint_fast8_t key; + + key = HwiP_disable(); + + if (!isInitialized) { + isInitialized = (bool) true; + + /* Call each driver's init function */ + for (i = 0; i < SPI_count; i++) { + SPI_config[i].fxnTablePtr->initFxn((SPI_Handle)&(SPI_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== SPI_open ======== + */ +SPI_Handle SPI_open(uint_least8_t index, SPI_Params *params) +{ + SPI_Handle handle = NULL; + + if (isInitialized && (index < SPI_count)) { + /* If params are NULL use defaults */ + if (params == NULL) { + params = (SPI_Params *) &SPI_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (SPI_Handle)&(SPI_config[index]); + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== SPI_Params_init ======== + */ +void SPI_Params_init(SPI_Params *params) +{ + *params = SPI_defaultParams; +} + +/* + * ======== SPI_transfer ======== + */ +bool SPI_transfer(SPI_Handle handle, SPI_Transaction *transaction) +{ + return (handle->fxnTablePtr->transferFxn(handle, transaction)); +} + +/* + * ======== SPI_transferCancel ======== + */ +void SPI_transferCancel(SPI_Handle handle) +{ + handle->fxnTablePtr->transferCancelFxn(handle); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SPI.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SPI.h new file mode 100644 index 0000000..329b93c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SPI.h @@ -0,0 +1,921 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file SPI.h + * + * @brief Serial Peripheral Interface (SPI) Driver Interface + * + * @anchor ti_drivers_SPI_Overview + * # Overview + * The Serial Peripheral Interface (SPI) driver is a generic, full-duplex + * driver that transmits and receives data on a SPI bus. SPI is sometimes + * called SSI (Synchronous Serial Interface). + * The SPI protocol defines the format of a data transfer over the SPI bus, + * but it leaves flow control, data formatting, and handshaking mechanisms + * to higher-level software layers. + * + * The SPI driver operates on some key definitions and assumptions: + * - The driver operates transparently from the chip select. Some SPI + * controllers feature a hardware chip select to assert SPI slave + * peripherals. See the specific device implementations on chip + * select requirements. + * + * - The SPI protocol does not account for a built-in handshaking mechanism + * and neither does this SPI driver. Therefore, when operating in + * #SPI_SLAVE mode, the application must provide such a mechanism to + * ensure that the SPI slave is ready for the SPI master. The SPI slave + * must call #SPI_transfer() *before* the SPI master starts transmitting. + * Some example application mechanisms could include: + * - Timed delays on the SPI master to guarantee the SPI slave is ready + * for a SPI transaction. + * - A form of GPIO flow control from the slave to the SPI master to notify + * the master when ready. + * + *
+ * @anchor ti_drivers_SPI_Usage + * # Usage + * + * To use the SPI driver to send data over the SPI bus, the application + * calls the following APIs: + * - SPI_init(): Initialize the SPI driver. + * - SPI_Params_init(): Initialize a #SPI_Params structure with default + * values. Then change the parameters from non-default values as + * needed. + * - SPI_open(): Open an instance of the SPI driver, passing the + * initialized parameters, or NULL, and an index to the configuration to + * open (detailed later). + * - SPI_transfer(): Transmit/receive data. This function takes a + * #SPI_Transaction argument that describes the transfer that is requested. + * - SPI_close(): De-initialize the SPI instance. + * + * @anchor ti_drivers_SPI_Synopsis + * ## Synopsis + * The following code example opens a SPI instance as a master SPI, + * and issues a transaction. + * + * @code + * SPI_Handle spi; + * SPI_Params spiParams; + * SPI_Transaction spiTransaction; + * uint8_t transmitBuffer[MSGSIZE]; + * uint8_t receiveBuffer[MSGSIZE]; + * bool transferOK; + * + * SPI_init(); // Initialize the SPI driver + * + * SPI_Params_init(&spiParams); // Initialize SPI parameters + * spiParams.dataSize = 8; // 8-bit data size + * + * spi = SPI_open(Board_SPI0, &spiParams); + * if (spi == NULL) { + * while (1); // SPI_open() failed + * } + * + * // Fill in transmitBuffer + * spiTransaction.count = MSGSIZE; + * spiTransaction.txBuf = (void *)transmitBuffer; + * spiTransaction.rxBuf = (void *)receiveBuffer; + * + * transferOK = SPI_transfer(spi, &spiTransaction); + * if (!transferOK) { + * // Error in SPI or transfer already in progress. + * while (1); + * } + * @endcode + * + * More details on usage are provided in the following subsections. + * + * @anchor ti_drivers_SPI_Examples + * ## Examples # + * * @ref ti_drivers_SPI_Synopsis "Usage Synopsis" + * * @ref ti_drivers_SPI_Example_openblocking "Open in blocking mode" + * * @ref ti_drivers_SPI_Example_opencallback "Open in callback mode" + * * @ref ti_drivers_SPI_Example_6bitframes "Sending 6 bit frames" + * * @ref ti_drivers_SPI_Example_12bitframes "Sending 12 bit frames" + * * @ref ti_drivers_SPI_Example_callbackarg "Callback function using arg" + * + * ## Initializing the SPI Driver + * + * SPI_init() must be called before any other SPI APIs. This function + * iterates through the elements of the @p SPI_config[] array, calling + * the element's device implementation SPI initialization function. + * + * ## Opening the SPI Driver + * After initializing the SPI driver by calling SPI_init(), the application + * can open a SPI instance by calling SPI_open(). This function + * takes an index into the @p SPI_config[] array, and a SPI parameters data + * structure. The SPI instance is specified by the index of the SPI in + * @p SPI_config[]. Calling SPI_open() a second time with the same index + * previously passed to SPI_open() will result in an error. You can, + * though, re-use the index if the instance is closed via SPI_close(). + * + * If no #SPI_Params structure is passed to SPI_open(), default values are + * used. If the open call is successful, it returns a non-NULL value. + * + * @anchor ti_drivers_SPI_Example_openblocking + * Example opening a SPI driver instance in blocking mode: + * @code + * SPI_Handle spi; + * SPI_Params spiParams; + * + * SPI_Params_init(&spiParams); + * spiParams.transferMode = SPI_MODE_BLOCKING; + * spi = SPI_open(Board_SPI0, &spiParams); + * + * if (spi == NULL) { + * // Error opening SPI + * while(1); + * } + * @endcode + * + * @anchor ti_drivers_SPI_Example_opencallback + * Example opening a SPI driver instance in callback mode: + * @code + * SPI_Handle spi; + * SPI_Params spiParams; + * + * SPI_Params_init(&spiParams); + * spiParams.transferMode = SPI_MODE_CALLBACK; + * spiParams.transferCallbackFxn = UserCallbackFxn; + * + * spi = SPI_open(Board_SPI0, &spiParams); + * if (spi == NULL) { + * // Error opening SPI + * while (1); + * } + * @endcode + * + * ## SPI Parameters + * + * The #SPI_Params structure is passed to the SPI_open() call. If NULL + * is passed for the parameters, SPI_open() uses default parameters. + * A #SPI_Params structure is initialized with default values by passing + * it to SPI_Params_init(). + * Some of the SPI parameters are described below. To see brief descriptions + * of all the parameters, see #SPI_Params. + * + * ### SPI Mode + * The SPI driver operates in both SPI master and SPI slave modes. + * Logically, the implementation is identical, however the difference + * between these two modes is driven by hardware. The default mode is + * #SPI_MASTER, but can be set to slave mode by setting #SPI_Params.mode + * to #SPI_SLAVE in the parameters passed to SPI_open(). See + * @ref ti_drivers_SPI_MasterSlaveModes "Master/Slave Modes" for further + * details. + * + * ### SPI Transfer Mode + * The SPI driver supports two transfer modes of operation: blocking and + * callback. The transfer mode is determined by the transferMode parameter + * in the #SPI_Params data structure. The SPI driver + * defaults to blocking mode, if the application does not set it. + * Once a SPI driver is opened, the only way to change the operation mode + * is to close and re-open the SPI instance with the new transfer mode. + * + * In blocking mode, a task's code execution is blocked until a SPI + * transaction has completed or a timeout has occurred. This ensures + * that only one SPI transfer operates at a given time. Other tasks requesting + * SPI transfers while a transfer is currently taking place will receive + * a FALSE return value. If a timeout occurs the transfer is canceled, the + * task is unblocked & will receive a FALSE return value. The transaction + * count field will have the amount of frames which were transferred + * successfully before the timeout. In blocking mode, transfers cannot be + * performed in software or hardware ISR context. + * + * In callback mode, a SPI transaction functions asynchronously, which + * means that it does not block code execution. After a SPI transaction + * has been completed, the SPI driver calls a user-provided hook function. + * Callback mode is supported in the execution context of tasks and + * hardware interrupt routines. + * + * ### SPI Frame Formats and Data Size + * The SPI driver can configure the device's SPI peripheral to transfer + * data in several SPI format options: SPI (with various polarity and phase + * settings), TI, and Micro-wire. The frame format is set with + * #SPI_Params.frameFormat. Some SPI implementations may not support all frame + * formats & the SPI driver will fail to opened. Refer to the device specific + * implementation documentation for details on which frame formats are + * supported. + * + * The smallest single unit of data transmitted onto the SPI bus is called + * a SPI frame and is of size #SPI_Params.dataSize. A series of SPI frames + * transmitted/received on a SPI bus is referred to as a SPI transaction. + * + * ## SPI Transactions + * + * A SPI transaction consists of a series of SPI frames + * transmitted/received on a SPI bus. A SPI transaction is performed + * using SPI_transfer(). SPI_transfer() accepts a pointer to a + * #SPI_Transaction structure that dictates the quantity of data to be + * sent and received. + * The #SPI_Transaction.txBuf and #SPI_Transaction.rxBuf are both pointers + * to data buffers. If txBuf is NULL, the driver sends SPI frames with all + * data set to the default value specified in the hardware attributes. If + * rxBuf is NULL, the driver discards all SPI frames received. SPI_transfer() + * of a SPI transaction is performed atomically. + * + * @warning The use of NULL as a sentinel txBuf or rxBuf value to determine + * whether the SPI transaction includes a tx or rx component implies + * that it is not possible to perform a transmit or receive transfer + * directly from/to a buffer with a base address of 0x00000000. To support + * this rare use-case, the application will have to manually copy the + * contents of location 0x00000000 to/from a temporary buffer before/after + * the tx/rx SPI transaction. + * + * When the SPI is opened, the dataSize value determines the element types + * of txBuf and rxBuf. If the dataSize is from 4 to 8 bits, the driver + * assumes the data buffers are of type uint8_t (unsigned char). If the + * dataSize is from 8 to 16 bits, the driver assumes the data buffers are + * of type uint16_t (unsigned short). If the dataSize is greater than + * 16 bits, the driver assumes the data buffers are uint32_t (unsigned long). + * Some SPI driver implementations may not support all data sizes; refer + * to device specific SPI implementation documentation for details on + * what data sizes are supported. + * + * The optional #SPI_Transaction.arg variable can only be used when the + * SPI driver has been opened in callback mode. This variable is used to + * pass a user-defined value into the user-defined callback function. + * + * SPI_transfer() always performs full-duplex SPI transactions. This means + * the SPI simultaneously receives data as it transmits data. The application + * is responsible for formatting the data to be transmitted as well as + * determining whether the data received is meaningful. + * Specifics about SPI frame formatting and data sizes are provided in + * device-specific data sheets and technical reference manuals. + * + * The following code snippets perform SPI transactions. + * + * @anchor ti_drivers_SPI_Example_6bitframes + * Example transferring 6-bit SPI frames. The transmit and receive + * buffers are of type uint8_t. + * @code + * SPI_Transaction spiTransaction; + * uint8_t transmitBuffer[BUFSIZE]; + * uint8_t receiveBuffer[BUFSIZE]; + * bool transferOK; + * + * SPI_Params_init(&spiParams); + * spiParams.dataSize = 6; + * spi = SPI_open(Board_SPI0, &spiParams); + * ... + * spiTransaction.count = someIntegerValue; + * spiTransaction.txBuf = transmitBuffer; + * spiTransaction.rxBuf = receiveBuffer; + * + * transferOK = SPI_transfer(spi, &spiTransaction); + * if (!transferOK) { + * // Error in SPI or transfer already in progress. + * } + * @endcode + * + * @anchor ti_drivers_SPI_Example_12bitframes + * Example transferring 12-bit SPI frames. The transmit and receive + * buffers are of type uint16_t. + * @code + * SPI_Transaction spiTransaction; + * uint16_t transmitBuffer[BUFSIZE]; + * uint16_t receiveBuffer[BUFSIZE]; + * bool transferOK; + * + * SPI_Params_init(&spiParams); + * spiParams.dataSize = 12; + * spi = SPI_open(Board_SPI0, &spiParams); + * ... + * spiTransaction.count = someIntegerValue; + * spiTransaction.txBuf = transmitBuffer; + * spiTransaction.rxBuf = receiveBuffer; + * + * transferOK = SPI_transfer(spi, &spiTransaction); + * if (!transferOK) { + * // Error in SPI or transfer already in progress. + * } + * @endcode + * + * The following example shows an example of a callback function that + * utilizes the arg parameter. + * @anchor ti_drivers_SPI_Example_callbackarg + * @code + * // SPI is opened with callback function as seen in other examples + * // Our goal is to post a semaphore when transfer with sufficient size + * // completes. + * ... + * // Pass pointer to an initialized semaphore to callback via arg + * spiTransaction.count = someIntegerValue; + * spiTransaction.txBuf = transmitBuffer; + * spiTransaction.rxBuf = receiveBuffer; + * spiTransaction.arg = &mySemaphore; + * + * ... + * + * // Our callback function is defined here + * void spiCallbackFxn(SPI_Handle spi, SPI_Transaction *tran) + * { + * sem_t *semPtr = (sem_t *)(tran->arg); + * + * // Post the semaphore if our transaction was more than LIMIT + * if (tran->status == SPI_STATUS_SUCCESS && + * tran->count > LIMIT) { + * sem_post(semPtr); + * } + * } + * @endcode + * + * ## Canceling a transaction + * SPI_transferCancel() is used to cancel a SPI transaction when the driver is + * used in #SPI_MODE_CALLBACK mode. + * + * Calling this API while no transfer is in progress has no effect. If a + * transfer is in progress, it is canceled and the callback functions is + * called. + * The #SPI_Status status field in the #SPI_Transaction structure + * can be examined within the callback to determine if the transaction + * succeeded. + * + * Example: + * @code + * SPI_transferCancel(spi); + * @endcode + * + * @anchor ti_drivers_SPI_MasterSlaveModes + * ## Master/Slave Modes + * This SPI driver functions in both SPI master and SPI slave modes. + * Logically, the implementation is identical, however the difference between + * these two modes is driven by hardware. As a SPI master, the peripheral is + * in control of the clock signal and therefore will commence communications + * to the SPI slave immediately. As a SPI slave, the SPI driver prepares + * the peripheral to transmit and receive data in a way such that the + * peripheral is ready to transfer data when the SPI master initiates a + * transaction. + * + * ## Asserting on Chip Select + * The SPI protocol requires that the SPI master asserts a SPI slave's chip + * select pin prior to starting a SPI transaction. While this protocol is + * generally followed, various types of SPI peripherals have different + * timing requirements as to when and for how long the chip select pin must + * remain asserted for a SPI transaction. + * + * Commonly, the SPI master uses a hardware chip select to assert and + * de-assert the SPI slave for every data frame. In other cases, a SPI slave + * imposes the requirement of asserting the chip select over several SPI + * data frames. This is generally accomplished by using a regular, + * general-purpose output pin. Due to the complexity of such SPI peripheral + * implementations, this SPI driver has been designed to operate + * transparently to the SPI chip select. When the hardware chip + * select is used, the peripheral automatically selects/enables the + * peripheral. When using a software chip select, the application needs to + * handle the proper chip select and pin configuration. Chip select support + * will vary per SPI peripheral, refer to the device specific implementation + * documentation for details on chip select support. + * + * - _Hardware chip select_ No additional action by the application is + * required. + * - _Software chip select_ The application needs to handle the chip select + * assertion and de-assertion for the proper SPI peripheral. + * + *
+ * @anchor ti_drivers_SPI_Configuration + * # Configuration + * + * In order to use the SPI APIs, the application is required + * to provide device-specific SPI configuration in the Board.c file. + * The SPI driver interface defines a configuration data structure: + * + * @code + * typedef struct { + * SPI_FxnTable const *fxnTablePtr; + * void *object; + * void const *hwAttrs; + * } SPI_Config; + * @endcode + * + * The application must declare an array of #SPI_Config elements, named + * @p SPI_config[]. Each element of @p SPI_config[] must be populated with + * pointers to a device specific SPI driver implementation's function + * table, driver object, and hardware attributes. The hardware attributes + * define properties such as the SPI peripheral's base address, and + * the MOSI and MISO pins. Each element in @p SPI_config[] corresponds to + * a SPI instance, and none of the elements should have NULL pointers. + * There is no correlation between the index and the + * peripheral designation (such as SPI0 or SPI1). For example, it is + * possible to use SPI_config[0] for SPI1. + * + * Because the SPI configuration is very device dependent, you will need to + * check the doxygen for the device specific SPI implementation. There you + * will find a description of the SPI hardware attributes. Please also + * refer to the Board.c file of any of your examples to see the SPI + * configuration. + * + ******************************************************************************* + */ + +#ifndef ti_drivers_SPI__include +#define ti_drivers_SPI__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * @defgroup SPI_CONTROL SPI_control command and status codes + * These SPI macros are reservations for SPI.h + * @{ + */ + +/*! + * Common SPI_control() command code reservation offset. + * SPI driver implementations should offset command codes with #SPI_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define SPIXYZ_CMD_COMMAND0 SPI_CMD_RESERVED + 0 + * #define SPIXYZ_CMD_COMMAND1 SPI_CMD_RESERVED + 1 + * @endcode + */ +#define SPI_CMD_RESERVED (32) + +/*! + * Common SPI_control status code reservation offset. + * SPI driver implementations should offset status codes with + * #SPI_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define SPIXYZ_STATUS_ERROR0 SPI_STATUS_RESERVED - 0 + * #define SPIXYZ_STATUS_ERROR1 SPI_STATUS_RESERVED - 1 + * #define SPIXYZ_STATUS_ERROR2 SPI_STATUS_RESERVED - 2 + * @endcode + */ +#define SPI_STATUS_RESERVED (-32) + +/** + * @defgroup SPI_STATUS Status Codes + * SPI_STATUS_* macros are general status codes returned by SPI_control() + * @{ + * @ingroup SPI_CONTROL + */ + +/*! + * @brief Successful status code returned by SPI_control(). + * + * This value is returned from SPI_control() if the control code was executed + * successfully. + */ +#define SPI_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by SPI_control(). + * + * This value is returned from SPI_control() if the control code was not + * executed successfully. + */ +#define SPI_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by SPI_control() for undefined + * command codes. + * + * This value is returned from SPI_control() if the control code is not + * recognized by the driver implementation. + */ +#define SPI_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup SPI_CMD Command Codes + * SPI_CMD_* macros are general command codes for SPI_control(). Not all SPI + * driver implementations support these command codes. + * @{ + * @ingroup SPI_CONTROL + */ + +/* Add SPI_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief Wait forever define used to specify timeouts. + */ +#define SPI_WAIT_FOREVER (~(0U)) + +/*! + * @brief A handle that is returned from a SPI_open() call. + */ +typedef struct SPI_Config_ *SPI_Handle; + +/*! + * @brief Status codes that are set by the SPI driver. + */ +typedef enum { + SPI_TRANSFER_COMPLETED = 0, /*!< SPI transfer completed */ + SPI_TRANSFER_STARTED, /*!< SPI transfer started and in progress */ + SPI_TRANSFER_CANCELED, /*!< SPI transfer was canceled */ + SPI_TRANSFER_FAILED, /*!< SPI transfer failed */ + SPI_TRANSFER_CSN_DEASSERT, /*!< SPI chip select was de-asserted (only + applicable in return partial mode) */ + SPI_TRANSFER_PEND_CSN_ASSERT, /*!< SPI transfer is pending until the chip + select is asserted */ + SPI_TRANSFER_QUEUED /*!< SPI transfer added to transaction queue */ +} SPI_Status; + +/*! + * @brief + * A #SPI_Transaction data structure is used with SPI_transfer(). It indicates + * how many #SPI_FrameFormat frames are sent and received from the buffers + * pointed to txBuf and rxBuf. + * The arg variable is an user-definable argument which gets passed to the + * #SPI_CallbackFxn when the SPI driver is in #SPI_MODE_CALLBACK. + */ +typedef struct { + /* User input (write-only) fields */ + size_t count; /*!< Number of frames for this transaction */ + void *txBuf; /*!< void * to a buffer with data to be transmitted */ + void *rxBuf; /*!< void * to a buffer to receive data */ + void *arg; /*!< Argument to be passed to the callback function */ + + /* User output (read-only) fields */ + SPI_Status status; /*!< #SPI_Status code set by SPI_transfer */ + + void *nextPtr; /*!< Field used internally by the driver and must + never be accessed by the application. */ +} SPI_Transaction; + +/*! + * @brief The definition of a callback function used by the SPI driver + * when used in #SPI_MODE_CALLBACK + * + * @param SPI_Handle A #SPI_Handle + * @param SPI_Transaction* Pointer to a #SPI_Transaction + */ +typedef void (*SPI_CallbackFxn) (SPI_Handle handle, + SPI_Transaction *transaction); +/*! + * @brief + * Definitions for various SPI modes of operation. + */ +typedef enum { + SPI_MASTER = 0, /*!< SPI in master mode */ + SPI_SLAVE = 1 /*!< SPI in slave mode */ +} SPI_Mode; + +/*! + * @brief + * Definitions for various SPI data frame formats. + */ +typedef enum { + SPI_POL0_PHA0 = 0, /*!< SPI mode Polarity 0 Phase 0 */ + SPI_POL0_PHA1 = 1, /*!< SPI mode Polarity 0 Phase 1 */ + SPI_POL1_PHA0 = 2, /*!< SPI mode Polarity 1 Phase 0 */ + SPI_POL1_PHA1 = 3, /*!< SPI mode Polarity 1 Phase 1 */ + SPI_TI = 4, /*!< TI mode (not supported on all + implementations) */ + SPI_MW = 5 /*!< Micro-wire mode (not supported on all + implementations) */ +} SPI_FrameFormat; + +/*! + * @brief + * + * SPI transfer mode determines the whether the SPI controller operates + * synchronously or asynchronously. In #SPI_MODE_BLOCKING mode SPI_transfer() + * blocks code execution until the SPI transaction has completed. In + * #SPI_MODE_CALLBACK SPI_transfer() does not block code execution and instead + * calls a #SPI_CallbackFxn callback function when the transaction has + * completed (successfully or not). + */ +typedef enum { + /*! + * SPI_transfer() blocks execution. This mode can only be used when called + * within a Task context + */ + SPI_MODE_BLOCKING, + /*! + * SPI_transfer() does not block code execution and will call a + * #SPI_CallbackFxn. This mode can be used in a Task, software or hardware + * interrupt context. + */ + SPI_MODE_CALLBACK +} SPI_TransferMode; + +/*! + * @brief SPI Parameters + * + * SPI Parameters are used to with the SPI_open() call. Default values for + * these parameters are set using SPI_Params_init(). + * + * @sa SPI_Params_init() + */ +typedef struct { + SPI_TransferMode transferMode; /*!< Blocking or Callback mode */ + uint32_t transferTimeout; /*!< Transfer timeout in system + ticks */ + SPI_CallbackFxn transferCallbackFxn;/*!< Callback function pointer */ + SPI_Mode mode; /*!< Master or Slave mode */ + /*! @brief SPI bit rate in Hz + * + * Maximum bit rates supported by hardware: + * Device Family | Slave Max (MHz) | Master Max (MHz) | + * ------------- | ------------------ | ---------------- | + * MSP432P4 | 16 MHz | 24 MHz | + * MSP432E4 | 10 MHz | 60 MHz | + * CC13XX/CC26XX | 4 MHz | 12 MHz | + * CC32XX | 20 MHz | 20 MHz | + * + * Please note that depending on the specific use case, the driver may not + * support the hardware's maximum bit rate. + */ + uint32_t bitRate; + uint32_t dataSize; /*!< SPI data frame size in bits */ + SPI_FrameFormat frameFormat; /*!< SPI frame format */ + void *custom; /*!< Custom argument used by driver + implementation */ +} SPI_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_close(). + */ +typedef void (*SPI_CloseFxn) (SPI_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_control(). + */ +typedef int_fast16_t (*SPI_ControlFxn) (SPI_Handle handle, uint_fast16_t cmd, + void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_init(). + */ +typedef void (*SPI_InitFxn) (SPI_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_open(). + */ +typedef SPI_Handle (*SPI_OpenFxn) (SPI_Handle handle, SPI_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_transfer(). + */ +typedef bool (*SPI_TransferFxn) (SPI_Handle handle, + SPI_Transaction *transaction); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_transferCancel(). + */ +typedef void (*SPI_TransferCancelFxn) (SPI_Handle handle); + +/*! + * @brief The definition of a SPI function table that contains the + * required set of functions to control a specific SPI driver + * implementation. + */ +typedef struct { + /*! Function to close the specified peripheral */ + SPI_CloseFxn closeFxn; + + /*! Function to implementation specific control function */ + SPI_ControlFxn controlFxn; + + /*! Function to initialize the given data object */ + SPI_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + SPI_OpenFxn openFxn; + + /*! Function to initiate a SPI data transfer */ + SPI_TransferFxn transferFxn; + + /*! Function to cancel SPI data transfer */ + SPI_TransferCancelFxn transferCancelFxn; +} SPI_FxnTable; + +/*! + * @brief SPI Global configuration + * + * The #SPI_Config structure contains a set of pointers used to characterize + * the SPI driver implementation. + * + * This structure needs to be defined before calling SPI_init() and it must + * not be changed thereafter. + * + * @sa SPI_init() + */ +typedef struct SPI_Config_{ + /*! Pointer to a table of driver-specific implementations of SPI APIs */ + SPI_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} SPI_Config; + +/*! + * @brief Function to close a SPI peripheral specified by the SPI handle + * + * @pre SPI_open() has to be called first. + * + * @param handle A #SPI_Handle returned from SPI_open() + * + * @sa SPI_open() + */ +extern void SPI_close(SPI_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * #SPI_Handle. + * + * Commands for SPI_control can originate from SPI.h or from implementation + * specific SPI*.h (SPICC26XXDMA.h, SPIMSP432DMA.h, etc.. ) files. + * While commands from SPI.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific SPI*.h files add + * unique driver capabilities but are not API portable across all SPI driver + * implementations. + * + * Commands supported by SPI.h follow a SPI_CMD_\ naming + * convention.
+ * Commands supported by SPI*.h follow a SPI*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref SPI_CMD "SPI_control command codes" for command codes. + * + * See @ref SPI_STATUS "SPI_control return status codes" for status codes. + * + * @pre SPI_open() has to be called first. + * + * @param handle A #SPI_Handle returned from SPI_open() + * + * @param cmd SPI.h or SPI*.h commands. + * + * @param controlArg An optional R/W (read/write) command argument + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa SPI_open() + */ +extern int_fast16_t SPI_control(SPI_Handle handle, uint_fast16_t cmd, + void *controlArg); + +/*! + * @brief This function initializes the SPI module. + * + * @pre The SPI_config[] array must exist and be persistent before this + * function can be called. This function must also be called before + * any other SPI driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void SPI_init(void); + +/*! + * @brief This function opens a given SPI peripheral. + * + * @pre SPI controller has been initialized using SPI_init() + * + * @param index Index of config to use in the *SPI_config* array + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A #SPI_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa SPI_init() + * @sa SPI_close() + */ +extern SPI_Handle SPI_open(uint_least8_t index, SPI_Params *params); + +/*! + * @brief Function to initialize the #SPI_Params struct to its defaults + * + * @param params An pointer to #SPI_Params structure for + * initialization + * + * Defaults values are: + * * SPI_Params.transferMode = #SPI_MODE_BLOCKING + * * SPI_Params.transferTimeout = #SPI_WAIT_FOREVER + * * SPI_Params.transferCallbackFxn = NULL + * * SPI_Params.mode = #SPI_MASTER + * * SPI_Params.bitRate = 1000000 (Hz) + * * SPI_Params.dataSize = 8 (bits) + * * SPI_Params.frameFormat = #SPI_POL0_PHA0 + */ +extern void SPI_Params_init(SPI_Params *params); + +/*! + * @brief Function to perform SPI transactions + * + * If the SPI is in #SPI_MASTER mode, it will immediately start the + * transaction. If the SPI is in #SPI_SLAVE mode, it prepares the driver for + * a transaction with a SPI master device. The device will then wait until + * the master begins the transfer. + * + * In #SPI_MODE_BLOCKING, #SPI_transfer() will block task execution until the + * transaction has completed or a timeout has occurred. + * + * In #SPI_MODE_CALLBACK, %SPI_transfer() does not block task execution, but + * calls a #SPI_CallbackFxn once the transfer has finished. This makes + * %SPI_tranfer() safe to be used within a Task, software or hardware + * interrupt context. If queued transactions are supported SPI_Transfer may + * be called multiple times to queue multiple transactions. If the driver does + * not support this functionality additional calls will return false. Refer to + * device specific SPI driver documentation for support information. + * + * From calling #SPI_transfer() until transfer completion, the #SPI_Transaction + * structure must stay persistent and must not be altered by application code. + * It is also forbidden to modify the content of the #SPI_Transaction.txBuf + * during a transaction, even though the physical transfer might not have + * started yet. Doing this can result in data corruption. This is especially + * important for slave operations where SPI_transfer() might be called a long + * time before the actual data transfer begins. + * + * @param handle A #SPI_Handle + * + * @param transaction A pointer to a #SPI_Transaction. All of the fields within + * transaction except #SPI_Transaction.count and + * #SPI_Transaction.status are WO (write-only) unless + * otherwise noted in the driver implementations. If a + * transaction timeout has occurred, #SPI_Transaction.count + * will contain the number of frames that were transferred. + * Neither is it allowed to modify the transaction object nor + * the content of #SPI_Transaction.txBuf until the transfer + * has completed. + * + * @return @p true if started successfully; else @p false + * + * @sa #SPI_open + * @sa #SPI_transferCancel + */ +extern bool SPI_transfer(SPI_Handle handle, SPI_Transaction *transaction); + +/*! + * @brief Function to cancel SPI transactions + * + * In #SPI_MODE_BLOCKING, SPI_transferCancel has no effect. + * + * In #SPI_MODE_CALLBACK, SPI_transferCancel() will stop an SPI transfer if + * if one is in progress. + * If a transaction was in progress, its callback function will be called + * in context from which this API is called from. The #SPI_CallbackFxn + * function can determine if the transaction was successful or not by reading + * the #SPI_Status status value in the #SPI_Transaction structure. + * + * @pre SPI_init(), SPI_open(), SPI_transfer() are called + * + * @param handle A #SPI_Handle + * + * @sa #SPI_open + * @sa #SPI_transfer + */ +extern void SPI_transferCancel(SPI_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_SPI__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/TRNG.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/TRNG.c new file mode 100644 index 0000000..39bca4d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/TRNG.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== TRNG.c ======== + * + * This file contains default values for the TRNG_Params struct + * + */ + +#include +#include + +#include +#include + +const TRNG_Params TRNG_defaultParams = { + .returnBehavior = TRNG_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== TRNG_Params_init ======== + */ +void TRNG_Params_init(TRNG_Params *params){ + *params = TRNG_defaultParams; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/TRNG.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/TRNG.h new file mode 100644 index 0000000..c344c5a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/TRNG.h @@ -0,0 +1,447 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file TRNG.h + * + * @brief TRNG driver header + * + * @warning This is a beta API. It may change in future releases. + * + * @anchor ti_drivers_TRNG_Overview + * # Overview # + * The True Random Number Generator (TRNG) module generates numbers of variable + * lengths from a source of entropy. The output is suitable for applications + * requiring cryptographically random numbers such as keying material for + * private or symmetric keys. + * + * @anchor ti_drivers_TRNG_Usage + * # Usage # + * + * ## Before starting a TRNG operation # + * + * Before starting a TRNG operation, the application must do the following: + * - Call TRNG_init() to initialize the driver. + * - Call TRNG_Params_init() to initialize the TRNG_Params to default values. + * - Modify the TRNG_Params as desired. + * - Call TRNG_open() to open an instance of the driver. + * - Initialize a blank CryptoKey. These opaque datastructures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store, key blob), the CryptoKey must be + * initialized differently. The TRNG API can handle all types of CryptoKey. + * However, not all device-specific implementions support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * + * ## TRNG operations # + * + * TRNG_generateEntropy() provides the most basic functionality. Use it to + * generate random numbers of a specified width without further restrictions. + * An example use-case would be generating a symmetric key for AES encryption + * and / or authentication. + * + * To generate an ECC private key, you should use rejection sampling to ensure + * that the keying material is in the interval [1, n - 1]. The ECDH public key + * genreation APIs will reject private keys that are outside of this interval. + * This information may be used to generate keying material until a suitable + * key is generated. For most curves, it is improbable to generate a random number + * outside of this interval because n is a large number close to the maximum + * number that would fit in the k-byte keying material array. An example + * of how to do this is given below. + * + * ## After the TRNG operation completes # + * + * After the TRNG operation completes, the application should either start another operation + * or close the driver by calling TRNG_close(). + * + * @anchor ti_drivers_TRNG_Synopsis + * ## Synopsis + * @anchor ti_drivers_TRNG_Synopsis_Code + * @code + * // Import TRNG Driver definitions + * #include + * #include + * + * // Define name for TRNG channel index + * #define TRNG_INSTANCE 0 + * + * #define KEY_LENGTH_BYTES 16 + * + * TRNG_init(); + * + * handle = TRNG_open(TRNG_INSTANCE, NULL); + * + * CryptoKeyPlaintext_initBlankKey(&entropyKey, entropyBuffer, KEY_LENGTH_BYTES); + * + * result = TRNG_generateEntropy(handle, &entropyKey); + * + * TRNG_close(handle); + * + * @endcode + * + * @anchor ti_drivers_TRNG_Examples + * ## Examples + * + * ### Generate symmetric encryption key # + * @code + * + * #include + * #include + * + * #define KEY_LENGTH_BYTES 16 + * + * TRNG_Handle handle; + * int_fast16_t result; + * + * CryptoKey entropyKey; + * uint8_t entropyBuffer[KEY_LENGTH_BYTES]; + * + * handle = TRNG_open(0, NULL); + * + * if (!handle) { + * // Handle error + * while(1); + * } + * + * CryptoKeyPlaintext_initBlankKey(&entropyKey, entropyBuffer, KEY_LENGTH_BYTES); + * + * result = TRNG_generateEntropy(handle, &entropyKey); + * + * if (result != TRNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * TRNG_close(handle); + * + * @endcode + * + * ### Generate ECC private and public key using rejection sampling # + * @code + * + * #include + * #include + * #include + * #include + * + * TRNG_Handle trngHandle; + * ECDH_Handle ecdhHandle; + * + * CryptoKey privateKey; + * CryptoKey publicKey; + * + * int_fast16_t trngResult; + * int_fast16_t ecdhResult; + * + * uint8_t privateKeyingMaterial[32]; + * uint8_t publicKeyingMaterial[64]; + * + * ECDH_OperationGeneratePublicKey genPubKeyOperation; + * + * trngHandle = TRNG_open(0, NULL); + * if (!trngHandle) { + * while(1); + * } + * + * ecdhHandle = ECDH_open(0, NULL); + * if (!ecdhHandle) { + * while(1); + * } + * + * // Repeatedly generate random numbers until they are in the range [1, n - 1]. + * // Since the NIST-P256 order is so close to 2^256, the probability of needing + * // to generate more than one random number is incredibly low but not non-zero. + * do { + * + * CryptoKeyPlaintext_initBlankKey(&privateKey, privateKeyingMaterial, ECCParams_NISTP256.length); + * CryptoKeyPlaintext_initBlankKey(&publicKey, publicKeyingMaterial, 2 * ECCParams_NISTP256.length); + * + * trngResult = TRNG_generateEntropy(trngHandle, &privateKey); + * + * if (trngResult != TRNG_STATUS_SUCCESS) { + * while(1); + * } + * + * ECDH_OperationGeneratePublicKey_init(&genPubKeyOperation); + * genPubKeyOperation.curve = &ECCParams_NISTP256; + * genPubKeyOperation.myPrivateKey = &privateKey; + * genPubKeyOperation.myPublicKey = &publicKey; + * + * ecdhResult = ECDH_generatePublicKey(ecdhHandle, &genPubKeyOperation); + * + * } while(ecdhResult == ECDH_STATUS_PRIVATE_KEY_LARGER_EQUAL_ORDER || ecdhResult == ECDH_STATUS_PRIVATE_KEY_ZERO); + * + * TRNG_close(trngHandle); + * ECDH_close(ecdhHandle); + * + * @endcode + */ + +#ifndef ti_drivers_TRNG__include +#define ti_drivers_TRNG__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include + +/*! + * Common TRNG status code reservation offset. + * TRNG driver implementations should offset status codes with + * TRNG_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define TRNGXYZ_STATUS_ERROR0 TRNG_STATUS_RESERVED - 0 + * #define TRNGXYZ_STATUS_ERROR1 TRNG_STATUS_RESERVED - 1 + * #define TRNGXYZ_STATUS_ERROR2 TRNG_STATUS_RESERVED - 2 + * @endcode + */ +#define TRNG_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return TRNG_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define TRNG_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return TRNG_STATUS_ERROR if the function was not executed + * successfully. + */ +#define TRNG_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * TRNG driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define TRNG_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief A handle that is returned from a TRNG_open() call. + */ +typedef struct TRNG_Config *TRNG_Handle; + +/*! + * @brief The way in which TRNG function calls return after generating + * the requested entropy. + * + * Not all TRNG operations exhibit the specified return behavor. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specfied return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * TRNG functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |------------------------------|-------|-------|-------| + * |TRNG_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |TRNG_RETURN_BEHAVIOR_BLOCKING | X | | | + * |TRNG_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum { + TRNG_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * TRNG operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + TRNG_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while TRNG operation goes + * on in the background. TRNG operation results are available + * after the function returns. + */ + TRNG_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while TRNG + * operation goes on in the background. TRNG operation results + * are available after the function returns. + */ +} TRNG_ReturnBehavior; + +/*! + * @brief TRNG Global configuration + * + * The TRNG_Config structure contains a set of pointers used to characterize + * the TRNG driver implementation. + * + * This structure needs to be defined before calling TRNG_init() and it must + * not be changed thereafter. + * + * @sa TRNG_init() + */ +typedef struct TRNG_Config { + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} TRNG_Config; + +/*! + * @brief The definition of a callback function used by the TRNG driver + * when used in ::TRNG_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the TRNG operation. + * + * @param returnValue Return status code describing the outcome of the operation. + * + * @param entropy The CryptoKey that describes the location the generated + * entropy will be copied to. + */ +typedef void (*TRNG_CallbackFxn) (TRNG_Handle handle, + int_fast16_t returnValue, + CryptoKey *entropy); + +/*! + * @brief TRNG Parameters + * + * TRNG Parameters are used to with the TRNG_open() call. Default values for + * these parameters are set using TRNG_Params_init(). + * + * @sa TRNG_Params_init() + */ +typedef struct { + TRNG_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + TRNG_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::TRNG_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} TRNG_Params; + +/*! + * @brief Default TRNG_Params structure + * + * @sa TRNG_Params_init() + */ +extern const TRNG_Params TRNG_defaultParams; + +/*! + * @brief This function initializes the TRNG module. + * + * @pre The TRNG_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other TRNG driver APIs. This function call does not modify any + * peripheral registers. + */ +void TRNG_init(void); + +/*! + * @brief Function to initialize the TRNG_Params struct to its defaults + * + * @param params An pointer to TRNG_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = TRNG_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void TRNG_Params_init(TRNG_Params *params); + +/*! + * @brief This function opens a given TRNG peripheral. + * + * @pre TRNG controller has been initialized using TRNG_init() + * + * @param index Logical peripheral number for the TRNG indexed into + * the TRNG_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return A TRNG_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa TRNG_init() + * @sa TRNG_close() + */ +TRNG_Handle TRNG_open(uint_least8_t index, TRNG_Params *params); + +/*! + * @brief Function to close a TRNG peripheral specified by the TRNG handle + * + * @pre TRNG_open() has to be called first. + * + * @param handle A TRNG handle returned from TRNG_open() + * + * @sa TRNG_open() + */ +void TRNG_close(TRNG_Handle handle); + +/*! + * @brief Generate a random number + * + * Generates a random bitstream of the size defined in the \c entropy + * CryptoKey in the range 0 <= \c entropy buffer < 2 ^ (entropy length * 8). + * The entropy will be generated and stored according to the storage requirements + * defined in the CryptoKey. + * + * @pre TRNG_open() has to be called first. + * + * @param handle A TRNG handle returned from TRNG_open(). + * + * @param entropy A blank, initialized CryptoKey describing the target location + * the entropy shall be stored in. + * + * @retval #TRNG_STATUS_SUCCESS The operation succeeded. + * @retval #TRNG_STATUS_ERROR The operation failed. + * @retval #TRNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + */ +int_fast16_t TRNG_generateEntropy(TRNG_Handle handle, CryptoKey *entropy); + + + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_TRNG__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/UART.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/UART.c new file mode 100644 index 0000000..10a09be --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/UART.c @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== UART.c ======== + */ + +#include +#include +#include +#include + +#include +#include + +extern const UART_Config UART_config[]; +extern const uint_least8_t UART_count; + +/* Default UART parameters structure */ +const UART_Params UART_defaultParams = { + UART_MODE_BLOCKING, /* readMode */ + UART_MODE_BLOCKING, /* writeMode */ + UART_WAIT_FOREVER, /* readTimeout */ + UART_WAIT_FOREVER, /* writeTimeout */ + NULL, /* readCallback */ + NULL, /* writeCallback */ + UART_RETURN_NEWLINE, /* readReturnMode */ + UART_DATA_TEXT, /* readDataMode */ + UART_DATA_TEXT, /* writeDataMode */ + UART_ECHO_ON, /* readEcho */ + 115200, /* baudRate */ + UART_LEN_8, /* dataLength */ + UART_STOP_ONE, /* stopBits */ + UART_PAR_NONE, /* parityType */ + NULL /* custom */ +}; + +static bool isInitialized = false; + +/* + * ======== UART_close ======== + */ +void UART_close(UART_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== UART_control ======== + */ +int_fast16_t UART_control(UART_Handle handle, uint_fast16_t cmd, void *arg) +{ + return (handle->fxnTablePtr->controlFxn(handle, cmd, arg)); +} + +/* + * ======== UART_init ======== + */ +void UART_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + + key = HwiP_disable(); + + if (!isInitialized) { + isInitialized = (bool) true; + + /* Call each driver's init function */ + for (i = 0; i < UART_count; i++) { + UART_config[i].fxnTablePtr->initFxn((UART_Handle) &(UART_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== UART_open ======== + */ +UART_Handle UART_open(uint_least8_t index, UART_Params *params) +{ + UART_Handle handle = NULL; + + if (isInitialized && (index < UART_count)) { + /* If params are NULL use defaults */ + if (params == NULL) { + params = (UART_Params *) &UART_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (UART_Handle)&(UART_config[index]); + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== UART_Params_init ======== + */ +void UART_Params_init(UART_Params *params) +{ + *params = UART_defaultParams; +} + +/* + * ======== UART_read ======== + */ +int_fast32_t UART_read(UART_Handle handle, void *buffer, size_t size) +{ + return (handle->fxnTablePtr->readFxn(handle, buffer, size)); +} + +/* + * ======== UART_readPolling ======== + */ +int_fast32_t UART_readPolling(UART_Handle handle, void *buffer, size_t size) +{ + return (handle->fxnTablePtr->readPollingFxn(handle, buffer, size)); +} + +/* + * ======== UART_readCancel ======== + */ +void UART_readCancel(UART_Handle handle) +{ + handle->fxnTablePtr->readCancelFxn(handle); +} + +/* + * ======== UART_write ======== + */ +int_fast32_t UART_write(UART_Handle handle, const void *buffer, size_t size) +{ + return (handle->fxnTablePtr->writeFxn(handle, buffer, size)); +} + +/* + * ======== UART_writePolling ======== + */ +int_fast32_t UART_writePolling(UART_Handle handle, const void *buffer, + size_t size) +{ + return (handle->fxnTablePtr->writePollingFxn(handle, buffer, size)); +} + +/* + * ======== UART_writeCancel ======== + */ +void UART_writeCancel(UART_Handle handle) +{ + handle->fxnTablePtr->writeCancelFxn(handle); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/UART.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/UART.h new file mode 100644 index 0000000..5955ce3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/UART.h @@ -0,0 +1,956 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file UART.h + * @brief Universal Asynchronous Receiver-Transmitter (UART) Driver + * + * To use the UART driver, ensure that the correct driver library for your + * device is linked in and include this header file as follows: + * @code + * #include + * @endcode + * + * This module serves as the main interface for applications. Its purpose + * is to redirect the UART APIs to specific driver implementations + * which are specified using a pointer to a #UART_FxnTable. + * + * @anchor ti_drivers_UART_Overview + * # Overview + * A UART is used to translate data between the chip and a serial port. + * The UART driver simplifies reading and writing to any of the UART + * peripherals on the board, with multiple modes of operation and performance. + * These include blocking, non-blocking, and polling, as well as text/binary + * mode, echo and return characters. + * + * The UART driver interface provides device independent APIs, data types, + * and macros. The APIs in this driver serve as an interface to a typical RTOS + * application. The specific peripheral implementations are responsible for + * creating all the RTOS specific primitives to allow for thread-safe + * operation. + * + *
+ * @anchor ti_drivers_UART_Usage + * # Usage + * + * This documentation provides a basic @ref ti_drivers_UART_Synopsis + * "usage summary" and a set of @ref ti_drivers_UART_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor ti_drivers_UART_Synopsis + * ## Synopsis + * @anchor ti_drivers_UART_Synopsis_Code + * @code + * // Import the UART driver definitions + * #include + * + * // One-time initialization of UART driver + * UART_init(); + * + * // Initialize UART parameters + * UART_Params params; + * UART_Params_init(¶ms); + * params.baudRate = 9600; + * params.readMode = UART_MODE_BLOCKING; + * params.writeMode = UART_MODE_BLOCKING; + * params.readTimeout = UART_WAIT_FOREVER; + * params.writeTimeout = UART_WAIT_FOREVER; + * + * // Open the UART + * UART_Handle uart; + * uart = UART_open(Board_UART0, ¶ms); + * + * // Read from the UART + * int32_t readCount; + * uint8_t buffer[BUFSIZE]; + * readCount = UART_read(uart, buffer, BUFSIZE); + * + * // Write to the UART + * UART_write(uart, buffer, BUFSIZE); + * + * // Close the UART + * UART_close(uart); + * @endcode + * + *
+ * @anchor ti_drivers_UART_Examples + * # Examples + * The following code example opens a UART instance, reads + * a byte from the UART, and then writes the byte back to the UART. + * + * @code + * char input; + * UART_Handle uart; + * UART_Params uartParams; + * + * // Initialize the UART driver. UART_init() must be called before + * // calling any other UART APIs. + * UART_init(); + * + * // Create a UART with data processing off. + * UART_Params_init(&uartParams); + * uartParams.writeDataMode = UART_DATA_BINARY; + * uartParams.readDataMode = UART_DATA_BINARY; + * uartParams.readReturnMode = UART_RETURN_FULL; + * uartParams.readEcho = UART_ECHO_OFF; + * uartParams.baudRate = 115200; + * + * // Open an instance of the UART drivers + * uart = UART_open(Board_UART0, &uartParams); + * + * if (uart == NULL) { + * // UART_open() failed + * while (1); + * } + * + * // Loop forever echoing + * while (1) { + * UART_read(uart, &input, 1); + * UART_write(uart, &input, 1); + * } + * @endcode + * + * Details for the example code above are described in the following + * subsections. + * + * ### Opening the UART Driver # + * + * Opening a UART requires four steps: + * 1. Create and initialize a UART_Params structure. + * 2. Fill in the desired parameters. + * 3. Call UART_open(), passing the index of the UART in the UART_config + * structure, and the address of the UART_Params structure. The + * UART instance is specified by the index in the UART_config structure. + * 4. Check that the UART handle returned by UART_open() is non-NULL, + * and save it. The handle will be used to read and write to the + * UART you just opened. + * + * Only one UART index can be used at a time; calling UART_open() a second + * time with the same index previosly passed to UART_open() will result in + * an error. You can, though, re-use the index if the instance is closed + * via UART_close(). + * In the example code, Board_UART0 is passed to UART_open(). This macro + * is defined in the example's Board.h file. + * + * + * ### Modes of Operation # + * + * The UART driver can operate in blocking mode or callback mode, by + * setting the writeMode and readMode parameters passed to UART_open(). + * If these parameters are not set, as in the example code, the UART + * driver defaults to blocking mode. Options for the writeMode and + * readMode parameters are #UART_MODE_BLOCKING and #UART_MODE_CALLBACK: + * + * - #UART_MODE_BLOCKING uses a semaphore to block while data is being sent. + * The context of calling UART_read() or UART_write() must be a Task when + * using #UART_MODE_BLOCKING. The UART_write() or UART_read() call + * will block until all data is sent or received, or the write timeout or + * read timeout expires, whichever happens first. + * + * - #UART_MODE_CALLBACK is non-blocking and UART_read() and UART_write() + * will return while data is being sent in the context of a hardware + * interrupt. When the read or write finishes, the UART driver will call + * the user's callback function. In some cases, the UART data transfer + * may have been canceled, or a newline may have been received, so the + * number of bytes sent/received are passed to the callback function. Your + * implementation of the callback function can use this information + * as needed. Since the user's callback may be called in the context of an + * ISR, the callback function must not make any RTOS blocking calls. + * The buffer passed to UART_write() in #UART_MODE_CALLBACK is not copied. + * The buffer must remain coherent until all the characters have been sent + * (ie until the tx callback has been called with a byte count equal to + * that passed to UART_write()). + * + * The example sets the writeDataMode and readDataMode parameters to + * #UART_DATA_BINARY. Options for these parameters are #UART_DATA_BINARY + * and #UART_DATA_TEXT: + * + * - #UART_DATA_BINARY: The data is passed as is, without processing. + * + * - #UART_DATA_TEXT: Write actions add a carriage return before a + * newline character, and read actions replace a return with a newline. + * This effectively treats all device line endings as LF and all host + * PC line endings as CRLF. + * + * Other parameters set by the example are readReturnMode and readEcho. + * Options for the readReturnMode parameter are #UART_RETURN_FULL and + * #UART_RETURN_NEWLINE: + * + * - #UART_RETURN_FULL: The read action unblocks or returns when the buffer + * is full. + * - #UART_RETURN_NEWLINE: The read action unblocks or returns when a + * newline character is read, before the buffer is full. + * + * Options for the readEcho parameter are #UART_ECHO_OFF and #UART_ECHO_ON. + * This parameter determines whether the driver echoes data back to the + * UART. When echo is turned on, each character that is read by the target + * is written back, independent of any write operations. If data is + * received in the middle of a write and echo is turned on, the echoed + * characters will be mixed in with the write data. + * + * ### Reading and Writing data # + * + * The example code reads one byte frome the UART instance, and then writes + * one byte back to the same instance: + * + * @code + * UART_read(uart, &input, 1); + * UART_write(uart, &input, 1); + * @endcode + * + * The UART driver allows full duplex data transfers. Therefore, it is + * possible to call UART_read() and UART_write() at the same time (for + * either blocking or callback modes). It is not possible, however, + * to issue multiple concurrent operations in the same direction. + * For example, if one thread calls UART_read(uart0, buffer0...), + * any other thread attempting UART_read(uart0, buffer1...) will result in + * an error of UART_STATUS_ERROR, until all the data from the first UART_read() + * has been transferred to buffer0. This applies to both blocking and + * and callback modes. So applications must either synchronize + * UART_read() (or UART_write()) calls that use the same UART handle, or + * check for the UART_STATUS_ERROR return code indicating that a transfer is + * still ongoing. + * + *
+ * @anchor ti_drivers_UART_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ * + * ============================================================================ + */ + +#ifndef ti_drivers_UART__include +#define ti_drivers_UART__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * @defgroup UART_CONTROL UART_control command and status codes + * These UART macros are reservations for UART.h + * @{ + */ + +/*! + * Common UART_control command code reservation offset. + * UART driver implementations should offset command codes with + * UART_CMD_RESERVED growing positively + * + * Example implementation specific command codes: + * @code + * #define UARTXYZ_CMD_COMMAND0 UART_CMD_RESERVED + 0 + * #define UARTXYZ_CMD_COMMAND1 UART_CMD_RESERVED + 1 + * @endcode + */ +#define UART_CMD_RESERVED (32) + +/*! + * Common UART_control status code reservation offset. + * UART driver implementations should offset status codes with + * UART_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define UARTXYZ_STATUS_ERROR0 UART_STATUS_RESERVED - 0 + * #define UARTXYZ_STATUS_ERROR1 UART_STATUS_RESERVED - 1 + * #define UARTXYZ_STATUS_ERROR2 UART_STATUS_RESERVED - 2 + * @endcode + */ +#define UART_STATUS_RESERVED (-32) + +/** + * @defgroup UART_STATUS Status Codes + * UART_STATUS_* macros are general status codes returned by UART_control() + * @{ + * @ingroup UART_CONTROL + */ + +/*! + * @brief Successful status code returned by UART_control(). + * + * UART_control() returns UART_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define UART_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by UART_control(). + * + * UART_control() returns UART_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define UART_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by UART_control() for undefined + * command codes. + * + * UART_control() returns UART_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define UART_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup UART_CMD Command Codes + * UART_CMD_* macros are general command codes for UART_control(). Not all UART + * driver implementations support these command codes. + * @{ + * @ingroup UART_CONTROL + */ + +/*! + * @brief Command code used by UART_control() to read the next unsigned char. + * + * This command is used to read the next unsigned char from the UART's circular + * buffer without removing it. With this command code, @b arg is a pointer to an + * integer. @b *arg contains the next @c unsigned @c char read if data is + * present, else @b *arg is set to #UART_STATUS_ERROR. + */ +#define UART_CMD_PEEK (0) + +/*! + * @brief Command code used by UART_control() to determine if the read buffer + * is empty. + * + * This command is used to determine if there are any unsigned chars available + * to read from the UART's circular buffer using UART_read(). With this command + * code, @b arg is a pointer to a @c bool. @b *arg contains @c true if data is + * available, else @c false. + */ +#define UART_CMD_ISAVAILABLE (1) + +/*! + * @brief Command code used by UART_control() to determine how many unsigned + * chars are in the read buffer. + * + * This command is used to determine how many @c unsigned @c chars are available + * to read from the UART's circular buffer using UART_read(). With this command + * code, @b arg is a pointer to an @a integer. @b *arg contains the number of + * @c unsigned @c chars available to read. + */ +#define UART_CMD_GETRXCOUNT (2) + +/*! + * @brief Command code used by UART_control() to enable data receive by the + * UART. + * + * This command is used to enable the UART in such a way that it stores received + * unsigned chars into the circular buffer. For drivers that support power + * management, this typically means that the UART will set a power constraint + * while receive is enabled. UART_open() will always have this option + * enabled. With this command code, @b arg is @a don't @a care. + */ +#define UART_CMD_RXENABLE (3) + +/*! + * @brief Command code used by UART_control() to disable data received by the + * UART. + * + * This command is used to disable the UART in such a way that ignores the data + * it receives. For drivers that support power management, this typically means + * that the driver will release any power constraints, to permit the system to + * enter low power modes. With this command code, @b arg is @a don't @a care. + * + * @warning A call to UART_read() does @b NOT re-enable receive. + */ +#define UART_CMD_RXDISABLE (4) +/** @}*/ + +/** @}*/ + +#define UART_ERROR (UART_STATUS_ERROR) + +/*! + * @brief Wait forever define + */ +#define UART_WAIT_FOREVER (~(0U)) + +/*! + * @brief A handle that is returned from a UART_open() call. + */ +typedef struct UART_Config_ *UART_Handle; + +/*! + * @brief The definition of a callback function used by the UART driver + * when used in #UART_MODE_CALLBACK + * The callback can occur in task or HWI context. + * + * @param UART_Handle UART_Handle + * + * @param buf Pointer to read/write buffer + * + * @param count Number of elements read/written + */ +typedef void (*UART_Callback) (UART_Handle handle, void *buf, size_t count); + +/*! + * @brief UART mode settings + * + * This enum defines the read and write modes for the configured UART. + */ +typedef enum UART_Mode_ { + /*! + * Uses a semaphore to block while data is being sent. Context of the call + * must be a Task. + */ + UART_MODE_BLOCKING, + + /*! + * Non-blocking and will return immediately. When UART_write() or + * UART_read() has finished, the callback function is called from either + * the caller's context or from an interrupt context. + */ + UART_MODE_CALLBACK +} UART_Mode; + +/*! + * @brief UART return mode settings + * + * This enumeration defines the return modes for UART_read() and + * UART_readPolling(). This mode only functions when in #UART_DATA_TEXT mode. + * + * #UART_RETURN_FULL unblocks or performs a callback when the read buffer has + * been filled. + * #UART_RETURN_NEWLINE unblocks or performs a callback whenever a newline + * character has been received. + * + * UART operation | UART_RETURN_FULL | UART_RETURN_NEWLINE | + * -------------- | ---------------- | ------------------- | + * UART_read() | Returns when buffer is full | Returns when buffer is full or newline was read | + * UART_write() | Sends data as is | Sends data with an additional newline at the end | + * + * @pre UART driver must be used in #UART_DATA_TEXT mode. + */ +typedef enum UART_ReturnMode_ { + /*! Unblock/callback when buffer is full. */ + UART_RETURN_FULL, + + /*! Unblock/callback when newline character is received. */ + UART_RETURN_NEWLINE +} UART_ReturnMode; + +/*! + * @brief UART data mode settings + * + * This enumeration defines the data mode for reads and writes. + * + * In #UART_DATA_BINARY, data is passed as is, with no processing. + * + * In #UART_DATA_TEXT mode, the driver will examine the #UART_ReturnMode + * value, to determine whether or not to unblock/callback when a newline + * is received. Read actions replace a carriage return with a newline, + * and write actions add a carriage return before a newline. This + * effectively treats all device line endings as LF, and all host PC line + * endings as CRLF. + */ +typedef enum UART_DataMode_ { + UART_DATA_BINARY = 0, /*!< Data is not processed */ + UART_DATA_TEXT = 1 /*!< Data is processed according to above */ +} UART_DataMode; + +/*! + * @brief UART echo settings + * + * This enumeration defines if the driver will echo data when uses in + * #UART_DATA_TEXT mode. This only applies to data received by the UART. + * + * #UART_ECHO_ON will echo back characters it received while in #UART_DATA_TEXT + * mode. + * #UART_ECHO_OFF will not echo back characters it received in #UART_DATA_TEXT + * mode. + * + * @pre UART driver must be used in #UART_DATA_TEXT mode. + */ +typedef enum UART_Echo_ { + UART_ECHO_OFF = 0, /*!< Data is not echoed */ + UART_ECHO_ON = 1 /*!< Data is echoed */ +} UART_Echo; + +/*! + * @brief UART data length settings + * + * This enumeration defines the UART data lengths. + */ +typedef enum UART_LEN_ { + UART_LEN_5 = 0, /*!< Data length is 5 bits */ + UART_LEN_6 = 1, /*!< Data length is 6 bits */ + UART_LEN_7 = 2, /*!< Data length is 7 bits */ + UART_LEN_8 = 3 /*!< Data length is 8 bits */ +} UART_LEN; + +/*! + * @brief UART stop bit settings + * + * This enumeration defines the UART stop bits. + */ +typedef enum UART_STOP_ { + UART_STOP_ONE = 0, /*!< One stop bit */ + UART_STOP_TWO = 1 /*!< Two stop bits */ +} UART_STOP; + +/*! + * @brief UART parity type settings + * + * This enumeration defines the UART parity types. + */ +typedef enum UART_PAR_ { + UART_PAR_NONE = 0, /*!< No parity */ + UART_PAR_EVEN = 1, /*!< Parity bit is even */ + UART_PAR_ODD = 2, /*!< Parity bit is odd */ + UART_PAR_ZERO = 3, /*!< Parity bit is always zero */ + UART_PAR_ONE = 4 /*!< Parity bit is always one */ +} UART_PAR; + +/*! + * @brief UART Parameters + * + * UART parameters are used with the UART_open() call. Default values for + * these parameters are set using UART_Params_init(). + * + * @sa UART_Params_init() + */ +typedef struct UART_Params_ { + UART_Mode readMode; /*!< Mode for all read calls */ + UART_Mode writeMode; /*!< Mode for all write calls */ + uint32_t readTimeout; /*!< Timeout for read calls in blocking mode. */ + uint32_t writeTimeout; /*!< Timeout for write calls in blocking mode. */ + UART_Callback readCallback; /*!< Pointer to read callback function for callback mode. */ + UART_Callback writeCallback; /*!< Pointer to write callback function for callback mode. */ + UART_ReturnMode readReturnMode; /*!< Receive return mode */ + UART_DataMode readDataMode; /*!< Type of data being read */ + UART_DataMode writeDataMode; /*!< Type of data being written */ + UART_Echo readEcho; /*!< Echo received data back */ + uint32_t baudRate; /*!< Baud rate for UART */ + UART_LEN dataLength; /*!< Data length for UART */ + UART_STOP stopBits; /*!< Stop bits for UART */ + UART_PAR parityType; /*!< Parity bit type for UART */ + void *custom; /*!< Custom argument used by driver implementation */ +} UART_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_CloseFxn(). + */ +typedef void (*UART_CloseFxn) (UART_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_ControlFxn(). + */ +typedef int_fast16_t (*UART_ControlFxn) (UART_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_InitFxn(). + */ +typedef void (*UART_InitFxn) (UART_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_OpenFxn(). + */ +typedef UART_Handle (*UART_OpenFxn) (UART_Handle handle, UART_Params *params); +/*! + * @brief A function pointer to a driver specific implementation of + * UART_ReadFxn(). + */ +typedef int_fast32_t (*UART_ReadFxn) (UART_Handle handle, void *buffer, + size_t size); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_ReadPollingFxn(). + */ +typedef int_fast32_t (*UART_ReadPollingFxn) (UART_Handle handle, void *buffer, + size_t size); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_ReadCancelFxn(). + */ +typedef void (*UART_ReadCancelFxn) (UART_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_WriteFxn(). + */ +typedef int_fast32_t (*UART_WriteFxn) (UART_Handle handle, const void *buffer, + size_t size); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_WritePollingFxn(). + */ +typedef int_fast32_t (*UART_WritePollingFxn) (UART_Handle handle, + const void *buffer, size_t size); + +/*! + * @brief A function pointer to a driver specific implementation of + * UART_WriteCancelFxn(). + */ +typedef void (*UART_WriteCancelFxn) (UART_Handle handle); + +/*! + * @brief The definition of a UART function table that contains the + * required set of functions to control a specific UART driver + * implementation. + */ +typedef struct UART_FxnTable_ { + /*! Function to close the specified peripheral */ + UART_CloseFxn closeFxn; + + /*! Function to implementation specific control function */ + UART_ControlFxn controlFxn; + + /*! Function to initialize the given data object */ + UART_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + UART_OpenFxn openFxn; + + /*! Function to read from the specified peripheral */ + UART_ReadFxn readFxn; + + /*! Function to read via polling from the specified peripheral */ + UART_ReadPollingFxn readPollingFxn; + + /*! Function to cancel a read from the specified peripheral */ + UART_ReadCancelFxn readCancelFxn; + + /*! Function to write from the specified peripheral */ + UART_WriteFxn writeFxn; + + /*! Function to write via polling from the specified peripheral */ + UART_WritePollingFxn writePollingFxn; + + /*! Function to cancel a write from the specified peripheral */ + UART_WriteCancelFxn writeCancelFxn; +} UART_FxnTable; + +/*! + * @brief UART Global configuration + * + * The UART_Config structure contains a set of pointers used to characterize + * the UART driver implementation. + * + * This structure needs to be defined before calling UART_init() and it must + * not be changed thereafter. + * + * @sa UART_init() + */ +typedef struct UART_Config_ { + /*! Pointer to a table of driver-specific implementations of UART APIs */ + UART_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} UART_Config; + +/*! + * @brief Function to close a UART peripheral specified by the UART handle + * + * @pre UART_open() has been called. + * @pre Ongoing asynchronous read or write have been canceled using + * UART_readCancel() or UART_writeCancel() respectively. + * + * @param handle A #UART_Handle returned from UART_open() + * + * @sa UART_open() + */ +extern void UART_close(UART_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * #UART_Handle. + * + * Commands for %UART_control() can originate from UART.h or from implementation + * specific UART*.h (_UARTCC26XX.h_, _UARTMSP432.h_, etc.. ) files. + * While commands from UART.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific UART*.h files add + * unique driver capabilities but are not API portable across all UART driver + * implementations. + * + * Commands supported by UART.h follow a UART_CMD_\ naming + * convention.
+ * Commands supported by UART*.h follow a UART*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref UART_CMD "UART_control command codes" for command codes. + * + * See @ref UART_STATUS "UART_control return status codes" for status codes. + * + * @pre UART_open() has to be called. + * + * @param handle A UART handle returned from UART_open() + * + * @param cmd UART.h or UART*.h commands. + * + * @param arg An optional R/W (read/write) command argument + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa UART_open() + */ +extern int_fast16_t UART_control(UART_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief Function to initialize the UART module + * + * @pre The UART_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other UART driver APIs. + */ +extern void UART_init(void); + +/*! + * @brief Function to initialize a given UART peripheral + * + * Function to initialize a given UART peripheral specified by the + * particular index value. + * + * @pre UART_init() has been called + * + * @param index Logical peripheral number for the UART indexed into + * the UART_config table + * + * @param params Pointer to a parameter block. If NULL, default + * parameter values will be used. All the fields in + * this structure are RO (read-only). + * + * @return A #UART_Handle upon success. NULL if an error occurs, or if the + * indexed UART peripheral is already opened. + * + * @sa UART_init() + * @sa UART_close() + */ +extern UART_Handle UART_open(uint_least8_t index, UART_Params *params); + +/*! + * @brief Function to initialize the UART_Params struct to its defaults + * + * @param params An pointer to UART_Params structure for + * initialization + * + * Defaults values are: + * readMode = UART_MODE_BLOCKING; + * writeMode = UART_MODE_BLOCKING; + * readTimeout = UART_WAIT_FOREVER; + * writeTimeout = UART_WAIT_FOREVER; + * readCallback = NULL; + * writeCallback = NULL; + * readReturnMode = UART_RETURN_NEWLINE; + * readDataMode = UART_DATA_TEXT; + * writeDataMode = UART_DATA_TEXT; + * readEcho = UART_ECHO_ON; + * baudRate = 115200; + * dataLength = UART_LEN_8; + * stopBits = UART_STOP_ONE; + * parityType = UART_PAR_NONE; + */ +extern void UART_Params_init(UART_Params *params); + +/*! + * @brief Function that writes data to a UART with interrupts enabled. + * + * %UART_write() writes data from a memory buffer to the UART interface. + * The source is specified by \a buffer and the number of bytes to write + * is given by \a size. + * + * In #UART_MODE_BLOCKING, UART_write() blocks task execution until all + * the data in buffer has been written. + * + * In #UART_MODE_CALLBACK, %UART_write() does not block task execution. + * Instead, a callback function specified by UART_Params::writeCallback is + * called when the transfer is finished. The buffer passed to UART_write() + * in #UART_MODE_CALLBACK is not copied. The buffer must remain coherent + * until all the characters have been sent (ie until the tx callback has + * been called with a byte count equal to that passed to UART_write()). + * The callback function can occur in the caller's task context or in a HWI or + * SWI context, depending on the device implementation. + * An unfinished asynchronous write operation must always be canceled using + * UART_writeCancel() before calling UART_close(). + * + * %UART_write() is mutually exclusive to UART_writePolling(). For an opened + * UART peripheral, either UART_write() or UART_writePolling() can be used, + * but not both. + * + * @warning Do not call %UART_write() from its own callback function when in + * #UART_MODE_CALLBACK. + * + * @sa UART_writePolling() + * + * @param handle A #UART_Handle returned by UART_open() + * + * @param buffer A read-only pointer to buffer containing data to + * be written to the UART + * + * @param size The number of bytes in the buffer that should be written + * to the UART + * + * @return Returns the number of bytes that have been written to the UART. + * If an error occurs, #UART_STATUS_ERROR is returned. + * In #UART_MODE_CALLBACK mode, the return value is always 0. + */ +extern int_fast32_t UART_write(UART_Handle handle, const void *buffer, size_t size); + +/*! + * @brief Function that writes data to a UART, polling the peripheral to + * wait until new data can be written. Usage of this API is mutually + * exclusive with usage of UART_write(). + * + * This function initiates an operation to write data to a UART controller. + * + * UART_writePolling() will not return until all the data was written to the + * UART (or to its FIFO if applicable). + * + * @sa UART_write() + * + * @param handle A #UART_Handle returned by UART_open() + * + * @param buffer A read-only pointer to the buffer containing the data to + * be written to the UART + * + * @param size The number of bytes in the buffer that should be written + * to the UART + * + * @return Returns the number of bytes that have been written to the UART. + * If an error occurs, #UART_STATUS_ERROR is returned. + */ +extern int_fast32_t UART_writePolling(UART_Handle handle, const void *buffer, size_t size); + +/*! + * @brief Function that cancels a UART_write() function call. + * + * This function cancels an asynchronous UART_write() operation and is only + * applicable in #UART_MODE_CALLBACK. + * UART_writeCancel() calls the registered TX callback function no matter how many bytes + * were sent. It is the application's responsibility to check the count argument in + * the callback function and handle cases where only a subset of the bytes were sent. + * + * @param handle A #UART_Handle returned by UART_open() + */ +extern void UART_writeCancel(UART_Handle handle); + +/*! + * @brief Function that reads data from a UART with interrupt enabled. + * + * %UART_read() reads data from a UART controller. The destination is specified + * by \a buffer and the number of bytes to read is given by \a size. + * + * In #UART_MODE_BLOCKING, %UART_read() blocks task execution until all + * the data in buffer has been read. + * + * In #UART_MODE_CALLBACK, %UART_read() does not block task execution. + * Instead, a callback function specified by UART_Params::readCallback + * is called when the transfer is finished. + * The callback function can occur in the caller's context or in HWI or SWI + * context, depending on the device-specific implementation. + * An unfinished asynchronous read operation must always be canceled using + * UART_readCancel() before calling UART_close(). + * + * %UART_read() is mutually exclusive to UART_readPolling(). For an opened + * UART peripheral, either %UART_read() or UART_readPolling() can be used, + * but not both. + * + * @warning Do not call %UART_read() from its own callback function when in + * #UART_MODE_CALLBACK. + * + * @sa UART_readPolling() + * + * @param handle A #UART_Handle returned by UART_open() + * + * @param buffer A pointer to an empty buffer to which + * received data should be written + * + * @param size The number of bytes to be written into buffer + * + * @return Returns the number of bytes that have been read from the UART, + * #UART_STATUS_ERROR on an error. + */ +extern int_fast32_t UART_read(UART_Handle handle, void *buffer, size_t size); + +/*! + * @brief Function that reads data from a UART without interrupts. This API + * must be used mutually exclusive with UART_read(). + * + * This function initiates an operation to read data from a UART peripheral. + * + * %UART_readPolling() will not return until size data was read to the UART. + * + * @sa UART_read() + * + * @param handle A #UART_Handle returned by UART_open() + * + * @param buffer A pointer to an empty buffer in which + * received data should be written to + * + * @param size The number of bytes to be written into buffer + * + * @return Returns the number of bytes that have been read from the UART, + * #UART_STATUS_ERROR on an error. + */ +extern int_fast32_t UART_readPolling(UART_Handle handle, void *buffer, size_t size); + +/*! + * @brief Function that cancels a UART_read() function call. + * + * This function cancels an asynchronous UART_read() operation and is only + * applicable in #UART_MODE_CALLBACK. + * UART_readCancel() calls the registered RX callback function no matter how many bytes + * were received. It is the application's responsibility to check the count argument in + * the callback function and handle cases where only a subset of the bytes were received. + * + * @param handle A #UART_Handle returned by UART_open() + */ +extern void UART_readCancel(UART_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_UART__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Watchdog.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Watchdog.c new file mode 100644 index 0000000..50c4e19 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Watchdog.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== Watchdog.c ======== + */ + +#include +#include +#include + +#include +#include + +extern const Watchdog_Config Watchdog_config[]; +extern const uint_least8_t Watchdog_count; + +/* Default Watchdog parameters structure */ +const Watchdog_Params Watchdog_defaultParams = { + NULL, /* callbackFxn */ + Watchdog_RESET_ON, /* resetMode */ + Watchdog_DEBUG_STALL_ON, /* debugStallMode */ + NULL /* custom */ +}; + +static bool isInitialized = false; + +/* + * ======== Watchdog_clear ======== + */ +void Watchdog_clear(Watchdog_Handle handle) +{ + handle->fxnTablePtr->watchdogClear(handle); +} + +/* + * ======== Watchdog_close ======== + */ +void Watchdog_close(Watchdog_Handle handle) +{ + handle->fxnTablePtr->watchdogClose(handle); +} + +/* + * ======== Watchdog_control ======== + */ +int_fast16_t Watchdog_control(Watchdog_Handle handle, uint_fast16_t cmd, + void *arg) +{ + return (handle->fxnTablePtr->watchdogControl(handle, cmd, arg)); +} + +/* + * ======== Watchdog_init ======== + */ +void Watchdog_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + + key = HwiP_disable(); + + if (!isInitialized) { + isInitialized = (bool) true; + + /* Call each driver's init function */ + for (i = 0; i < Watchdog_count; i++) { + Watchdog_config[i].fxnTablePtr->watchdogInit((Watchdog_Handle)&(Watchdog_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== Watchdog_open ======== + */ +Watchdog_Handle Watchdog_open(uint_least8_t index, Watchdog_Params *params) +{ + Watchdog_Handle handle = NULL; + + /* Verify driver index and state */ + if (isInitialized && (index < Watchdog_count)) { + /* If params are NULL use defaults */ + if (params == NULL) { + params = (Watchdog_Params *) &Watchdog_defaultParams; + } + + handle = (Watchdog_Handle)&(Watchdog_config[index]); + handle = handle->fxnTablePtr->watchdogOpen(handle, params); + } + + return (handle); +} + +/* + * ======== Watchdog_Params_init ======== + */ +void Watchdog_Params_init(Watchdog_Params *params) +{ + *params = Watchdog_defaultParams; +} + + +/* + * ======== Watchdog_setReload ======== + */ +int_fast16_t Watchdog_setReload(Watchdog_Handle handle, uint32_t ticks) +{ + return (handle->fxnTablePtr->watchdogSetReload(handle, ticks)); +} + +/* + * ======== Watchdog_convertMsToTicks ======== + */ +uint32_t Watchdog_convertMsToTicks(Watchdog_Handle handle, uint32_t milliseconds) +{ + return (handle->fxnTablePtr->watchdogConvertMsToTicks(handle, milliseconds)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Watchdog.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Watchdog.h new file mode 100644 index 0000000..18fc14f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Watchdog.h @@ -0,0 +1,555 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file Watchdog.h + * + * @brief Watchdog driver interface + * + * @anchor ti_drivers_Watchdog_Overview + * # Overview # + * + * A watchdog timer can be used to generate a reset signal if a system has + * become unresponsive. The Watchdog driver simplifies configuring and + * starting the watchdog peripherals. The watchdog peripheral can be + * configured with resets either on or off and a user-specified timeout + * period. + * + * When the watchdog peripheral is configured not to generate a reset, it + * can be used to cause a hardware interrupt at a programmable interval. + * The driver provides the ability to specify a user-provided callback + * function that is called when the watchdog causes an interrupt. + * + * The Watchdog driver simplifies configuring and starting the Watchdog + * peripherals. The Watchdog can be set up to produce a reset signal after a + * timeout, or simply cause a hardware interrupt at a programmable interval. + * The driver provides the ability to specify a callback function that is + * called when the Watchdog causes an interrupt. + * + * When resets are turned on, it is the user application's responsibility to + * call Watchdog_clear() in order to clear the Watchdog and prevent a reset. + * Watchdog_clear() can be called at any time. + * + * @anchor ti_drivers_Watchdog_Usage + * # Usage # + * + * This section will cover driver usage. + * @anchor ti_drivers_Watchdog_Synopsis + * ## Synopsis # + * + * Open the driver with default settings: + * @code + * Watchdog_Handle watchdogHandle; + * + * Watchdog_init(); + * watchdogHandle = Watchdog_open(WATCHDOG_INDEX, NULL); + * if (watchdogHandle == NULL) { + * // Spin forever + * while(1); + * } + * @endcode + * + * The Watchdog driver must be initialized by calling Watchdog_init(), + * before any other Watchdog APIs can be called. + * Once the watchdog is initialized, a Watchdog object can be created + * through the following steps: + * - Create and initialize the #Watchdog_Params structure. + * - Assign desired values to parameters. + * - Call Watchdog_open(). + * - Save the Watchdog_Handle returned by Watchdog_open(). This will be + * used to interact with the Watchdog object just created. + * + * To have a user-defined function run at the hardware interrupt caused by + * a watchdog timer timeout, define a function of the following type: + * @code + * typedef void (*Watchdog_Callback)(uintptr_t); + * @endcode + * Then pass the function to Watchdog_open() through the #Watchdog_Params + * structure. + * + * An example of the Watchdog creation process that uses a callback + * function: + * @anchor ti_drivers_Watchdog_example_callback + * @code + * void UserCallbackFxn(Watchdog_Handle handle) + * { + * printf("Watchdog timer triggered!\n"); + * releaseResources(); + * } + * + * ... + * + * Watchdog_Params params; + * Watchdog_Handle watchdogHandle; + * + * Watchdog_init(); + * + * Watchdog_Params_init(¶ms); + * params.resetMode = Watchdog_RESET_ON; + * params.callbackFxn = (Watchdog_Callback) UserCallbackFxn; + * + * watchdogHandle = Watchdog_open(Board_WATCHDOG0, ¶ms); + * if (watchdogHandle == NULL) { + * // Error opening Watchdog + * while (1); + * } + * + * @endcode + * + * If no #Watchdog_Params structure is passed to Watchdog_open(), the + * default values are used. By default, the Watchdog driver has resets + * turned on, no callback function specified, and stalls the timer at + * breakpoints during debugging. + * + * Options for the resetMode parameter are #Watchdog_RESET_ON and + * #Watchdog_RESET_OFF. The latter allows the watchdog to be used like + * another timer interrupt. When resetMode is #Watchdog_RESET_ON, it is up + * to the application to call Watchdog_clear() to clear the Watchdog + * interrupt flag to prevent a reset. Watchdog_clear() can be called at + * any time. + * + * @anchor ti_drivers_Watchdog_Examples + * # Examples + * - @ref ti_drivers_Watchdog_Synopsis "Default Example" + * - @ref ti_drivers_Watchdog_example_callback "Callback Function before watchdog reset" + * + * @anchor ti_drivers_Watchdog_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for more information. + * + ******************************************************************************* + */ + +#ifndef ti_drivers_Watchdog__include +#define ti_drivers_Watchdog__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @defgroup Watchdog_CONTROL Watchdog_control command and status codes + * These Watchdog macros are reservations for Watchdog.h + * @{ + */ + +/*! + * Common Watchdog_control command code reservation offset. + * Watchdog driver implementations should offset command codes with + * Watchdog_CMD_RESERVED growing positively + * + * Example implementation specific command codes: + * @code + * #define WatchdogXYZ_CMD_COMMAND0 Watchdog_CMD_RESERVED + 0 + * #define WatchdogXYZ_CMD_COMMAND1 Watchdog_CMD_RESERVED + 1 + * @endcode + */ +#define Watchdog_CMD_RESERVED (32) + +/*! + * Common Watchdog_control status code reservation offset. + * Watchdog driver implementations should offset status codes with + * Watchdog_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define WatchdogXYZ_STATUS_ERROR0 Watchdog_STATUS_RESERVED - 0 + * #define WatchdogXYZ_STATUS_ERROR1 Watchdog_STATUS_RESERVED - 1 + * #define WatchdogXYZ_STATUS_ERROR2 Watchdog_STATUS_RESERVED - 2 + * @endcode + */ +#define Watchdog_STATUS_RESERVED (-32) + +/** + * @defgroup Watchdog_STATUS Status Codes + * Watchdog_STATUS_* macros are general status codes returned by Watchdog_control() + * @{ + * @ingroup Watchdog_CONTROL + */ + +/*! + * @brief Successful status code returned by Watchdog_control(). + * + * Watchdog_control() returns Watchdog_STATUS_SUCCESS if the control code was + * executed successfully. + */ +#define Watchdog_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by Watchdog_control(). + * + * Watchdog_control() returns Watchdog_STATUS_ERROR if the control code was not + * executed successfully. + */ +#define Watchdog_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by Watchdog_control() for undefined + * command codes. + * + * Watchdog_control() returns Watchdog_STATUS_UNDEFINEDCMD if the control code + * is not recognized by the driver implementation. + */ +#define Watchdog_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief An error status code returned by Watchdog_setReload() for drivers + * which do not support the aforementioned API. + * + * Watchdog_setReload() returns Watchdog_STATUS_UNSUPPORTED if the driver + * implementation does not support the aforementioned API. + */ +#define Watchdog_STATUS_UNSUPPORTED (-3) +/** @}*/ + +/** + * @defgroup Watchdog_CMD Command Codes + * Watchdog_CMD_* macros are general command codes for Watchdog_control(). Not all Watchdog + * driver implementations support these command codes. + * @{ + * @ingroup Watchdog_CONTROL + */ + +/* Add Watchdog_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! +* @brief Watchdog Handle +*/ +typedef struct Watchdog_Config_ *Watchdog_Handle; + +/*! + * @brief Watchdog debug stall settings + * + * This enumeration defines the debug stall modes for the Watchdog. On some + * targets, the Watchdog timer will continue to count down while a debugging + * session is halted. To avoid unwanted resets, the Watchdog can be set to + * stall while the processor is stopped by the debugger. + */ +typedef enum Watchdog_DebugMode_ { + Watchdog_DEBUG_STALL_ON, /*!< Watchdog will be stalled at breakpoints */ + Watchdog_DEBUG_STALL_OFF /*!< Watchdog will keep running at breakpoints */ +} Watchdog_DebugMode; + +/*! + * @brief Watchdog reset mode settings + * + * This enumeration defines the reset modes for the Watchdog. The Watchdog can + * be configured to either generate a reset upon timeout or simply produce a + * periodic interrupt. + */ +typedef enum Watchdog_ResetMode_ { + Watchdog_RESET_OFF, /*!< Timeouts generate interrupts only */ + Watchdog_RESET_ON /*!< Generates reset after timeout */ +} Watchdog_ResetMode; + +/*! + * @brief Watchdog callback pointer + * + * This is the typedef for the function pointer that will allow a callback + * function to be specified in the #Watchdog_Params structure. The function + * will take a #Watchdog_Handle of the Watchdog causing the interrupt (cast as + * a uintptr_t) as an argument. + */ +typedef void (*Watchdog_Callback)(uintptr_t handle); + +/*! + * @brief Watchdog Parameters + * + * Watchdog parameters are used to with the Watchdog_open() call. Default + * values for these parameters are set using Watchdog_Params_init(). + * + * @sa Watchdog_Params_init() + */ +typedef struct Watchdog_Params_ { + Watchdog_Callback callbackFxn; /*!< Pointer to callback. Not supported + on all targets. */ + Watchdog_ResetMode resetMode; /*!< Mode to enable resets. + Not supported on all targets. */ + Watchdog_DebugMode debugStallMode; /*!< Mode to stall WDT at breakpoints. + Not supported on all targets. */ + void *custom; /*!< Custom argument used by driver + implementation */ +} Watchdog_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_clear(). + */ +typedef void (*Watchdog_ClearFxn) (Watchdog_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_close(). + */ +typedef void (*Watchdog_CloseFxn) (Watchdog_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_control(). + */ +typedef int_fast16_t (*Watchdog_ControlFxn) (Watchdog_Handle handle, + uint_fast16_t cmd, + void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_init(). + */ +typedef void (*Watchdog_InitFxn) (Watchdog_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_open(). + */ +typedef Watchdog_Handle (*Watchdog_OpenFxn) (Watchdog_Handle handle, + Watchdog_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_setReload(). + */ +typedef int_fast16_t (*Watchdog_SetReloadFxn)(Watchdog_Handle handle, + uint32_t ticks); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_ConvertMsToTicksFxn(). + */ +typedef uint32_t (*Watchdog_ConvertMsToTicksFxn) (Watchdog_Handle handle, + uint32_t milliseconds); + +/*! + * @brief The definition of a Watchdog function table that contains the + * required set of functions to control a specific Watchdog driver + * implementation. + */ +typedef struct Watchdog_FxnTable_ { + Watchdog_ClearFxn watchdogClear; + Watchdog_CloseFxn watchdogClose; + Watchdog_ControlFxn watchdogControl; + Watchdog_InitFxn watchdogInit; + Watchdog_OpenFxn watchdogOpen; + Watchdog_SetReloadFxn watchdogSetReload; + Watchdog_ConvertMsToTicksFxn watchdogConvertMsToTicks; +} Watchdog_FxnTable; + +/*! + * @brief Watchdog Global configuration + * + * The Watchdog_Config structure contains a set of pointers used to + * characterize the Watchdog driver implementation. + * + * This structure needs to be defined before calling Watchdog_init() and + * it must not be changed thereafter. + * + * @sa Watchdog_init() + */ +typedef struct Watchdog_Config_ { + /*! + * Pointer to a table of driver-specific implementations of Watchdog APIs + */ + Watchdog_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} Watchdog_Config; + +/*! + * @brief Clears the Watchdog + * + * Clears the Watchdog to to prevent a reset signal from being generated if the + * module is in #Watchdog_RESET_ON reset mode. + * + * @param handle A #Watchdog_Handle + */ +extern void Watchdog_clear(Watchdog_Handle handle); + +/*! + * @brief Function to close a Watchdog peripheral specified by the Watchdog + * handle.It stops (holds) the Watchdog counting on applicable + * platforms. + * + * @pre Watchdog_open() has to be called first. + * + * @param handle A #Watchdog_Handle returned from Watchdog_open() + * + * @sa Watchdog_open() + */ +extern void Watchdog_close(Watchdog_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * #Watchdog_Handle. + * + * Commands for Watchdog_control can originate from Watchdog.h or from implementation + * specific Watchdog*.h files. + * While commands from Watchdog.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific Watchdog*.h files add + * unique driver capabilities but are not API portable across all Watchdog driver + * implementations. + * + * Commands supported by Watchdog.h follow a Watchdog_CMD_\ naming + * convention.
+ * Commands supported by Watchdog*.h follow a Watchdog*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref Watchdog_CMD "Watchdog_control command codes" for command codes. + * + * See @ref Watchdog_STATUS "Watchdog_control return status codes" for status codes. + * + * @pre Watchdog_open() has to be called first. + * + * @param handle A #Watchdog_Handle returned from Watchdog_open() + * + * @param cmd Watchdog.h or Watchdog*.h commands. + * + * @param arg An optional R/W (read/write) command argument + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa Watchdog_open() + */ +extern int_fast16_t Watchdog_control(Watchdog_Handle handle, + uint_fast16_t cmd, + void *arg); + +/*! + * @brief Initializes the Watchdog module + * + * The application-provided Watchdog_config must be present before the + * Watchdog_init() function is called. The Watchdog_config must be persistent + * and not changed after Watchdog_init is called. This function must be called + * before any of the other Watchdog driver APIs. + */ +extern void Watchdog_init(void); + +/*! + * @brief Opens a Watchdog + * + * Opens a Watchdog object with the index and parameters specified, and + * returns a #Watchdog_Handle. + * + * @param index Logical peripheral number for the Watchdog indexed + * into the Watchdog_config table + * + * @param params Pointer to a #Watchdog_Params, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A #Watchdog_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa Watchdog_init() + * @sa Watchdog_close() + */ +extern Watchdog_Handle Watchdog_open(uint_least8_t index, Watchdog_Params *params); + +/*! + * @brief Function to initialize the #Watchdog_Params structure to its defaults + * + * @param params An pointer to #Watchdog_Params structure for + * initialization + * + * Default parameters: + * callbackFxn = NULL + * resetMode = #Watchdog_RESET_ON + * debugStallMode = #Watchdog_DEBUG_STALL_ON + */ +extern void Watchdog_Params_init(Watchdog_Params *params); + +/*! + * @brief Sets the Watchdog reload value + * + * Sets the value from which the Watchdog will countdown after it reaches + * zero. This is how the reload value can be changed after the Watchdog has + * already been opened. The new reload value will be loaded into the Watchdog + * timer when this function is called. Watchdog_setReload is not reentrant. + * For CC13XX/CC26XX, if the parameter 'ticks' is set to zero (0), a Watchdog + * interrupt is immediately generated. + * + * This API is not applicable for all platforms. See the page for your + * specific driver implementation for details. + * + * @param handle A #Watchdog_Handle + * + * @param ticks Value to be loaded into Watchdog timer + * Unit is in Watchdog clock ticks + * + * @return #Watchdog_STATUS_SUCCESS on success, #Watchdog_STATUS_UNSUPPORTED + * if driver does not support this API. + */ +extern int_fast16_t Watchdog_setReload(Watchdog_Handle handle, uint32_t ticks); + +/*! + * @brief Converts milliseconds to Watchdog clock ticks + * + * Converts the input value into number of Watchdog clock ticks as close as + * possible. If the converted value exceeds 32 bits, a zero (0) will be + * returned to indicate overflow. The converted value can be used as the + * function parameter 'ticks' in Watchdog_setReload(). + * + * This API is not applicable for all platforms. See the page for your + * specific driver implementation for details. + * + * @param handle A #Watchdog_Handle + * + * @param milliseconds Value to be converted + * + * @return Converted value in number of Watchdog clock ticks + * A value of zero (0) means the converted value exceeds 32 bits + * or that the operation is not supported for the specific device. + * + * @sa Watchdog_setReload() + */ +extern uint32_t Watchdog_convertMsToTicks(Watchdog_Handle handle, + uint32_t milliseconds); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Watchdog__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adc/ADCCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adc/ADCCC26XX.c new file mode 100644 index 0000000..9bfc829 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adc/ADCCC26XX.c @@ -0,0 +1,371 @@ +/* + * Copyright (c) 2016-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include + +/* Kernel services */ +#include +#include +#include + +/* TI-RTOS drivers */ +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_aux_evctl.h) +#include DeviceFamily_constructPath(driverlib/aux_adc.h) +#include DeviceFamily_constructPath(driverlib/aux_smph.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) + #include DeviceFamily_constructPath(driverlib/aux_wuc.h) +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) + #define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE + #define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ +#endif + + +/* + * ============================================================================= + * Public Function Declarations + * ============================================================================= + */ +void ADCCC26XX_close(ADC_Handle handle); +void ADCCC26XX_init(ADC_Handle handle); +ADC_Handle ADCCC26XX_open(ADC_Handle handle, ADC_Params *params); +int_fast16_t ADCCC26XX_convert(ADC_Handle handle, uint16_t *value); +int_fast16_t ADCCC26XX_control(ADC_Handle handle, uint_fast16_t cmd, void *arg); +uint32_t ADCCC26XX_convertToMicroVolts(ADC_Handle handle, uint16_t adcValue); + +/* + * ============================================================================= + * Private Function Declarations + * ============================================================================= + */ + +/* + * ============================================================================= + * Constants + * ============================================================================= + */ + +/* ADC function table for ADCCC26XX implementation */ +const ADC_FxnTable ADCCC26XX_fxnTable = { + ADCCC26XX_close, + ADCCC26XX_control, + ADCCC26XX_convert, + ADCCC26XX_convertToMicroVolts, + ADCCC26XX_init, + ADCCC26XX_open +}; + +/* + * ============================================================================= + * Private Global Variables + * ============================================================================= + */ + +/* Keep track the adc handle instance to create and delete adcSemaphore */ +static uint16_t adcInstance = 0; + +/* Semaphore to arbitrate access to the single ADC peripheral between multiple handles */ +static SemaphoreP_Struct adcSemaphore; + +/* + * ============================================================================= + * Function Definitions + * ============================================================================= + */ + +/* + * ======== ADCCC26XX_close ======== + */ +void ADCCC26XX_close(ADC_Handle handle){ + ADCCC26XX_Object *object; + + DebugP_assert(handle); + + object = handle->object; + + uint32_t key = HwiP_disable(); + + if (object->isOpen) { + adcInstance--; + if (adcInstance == 0) { + SemaphoreP_destruct(&adcSemaphore); + } + DebugP_log0("ADC: Object closed"); + } + else { + return; + } + object->isOpen = false; + HwiP_restore(key); + + /* Deallocate pins */ + if (object->pinHandle){ + PIN_close(object->pinHandle); + } +} + + +/* + * ======== ADCCC26XX_control ======== + */ +int_fast16_t ADCCC26XX_control(ADC_Handle handle, uint_fast16_t cmd, void *arg){ + /* No implementation yet */ + return ADC_STATUS_UNDEFINEDCMD; +} + +/* + * ======== ADCCC26XX_convert ======== + */ +int_fast16_t ADCCC26XX_convert(ADC_Handle handle, uint16_t *value){ + ADCCC26XX_HWAttrs const *hwAttrs; + ADCCC26XX_Object *object; + int_fast16_t conversionResult = ADC_STATUS_ERROR; + uint16_t conversionValue = 0; + uint32_t interruptStatus = 0; + + DebugP_assert(handle); + + /* Get handle */ + hwAttrs = handle->hwAttrs; + + /* Get the object */ + object = handle->object; + + if (object->isProtected) { + /* Acquire the lock for this particular ADC handle */ + SemaphoreP_pend(&adcSemaphore, SemaphoreP_WAIT_FOREVER); + } + + /* Set constraints to guarantee operation */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Acquire the ADC hw semaphore. Return an error if the hw semaphore is not + * available. There is only one interrupt available for the hw semaphores and it + * is used by the TDC already. Busy-wait polling might lock up the device and starting + * timeout clocks would add overhead and be clunky. It is better if such functionality + * is implemented at application level if desired. + */ + if(!AUXSMPHTryAcquire(AUX_SMPH_2)){ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + if (object->isProtected) { + SemaphoreP_post(&adcSemaphore); + } + return conversionResult; + } + + /* Specify input in ADC module */ + AUXADCSelectInput(hwAttrs->adcCompBInput); + + /* Flush the ADC FIFO in case we have triggered prior to this call */ + AUXADCFlushFifo(); + + /* If input scaling is set to disabled in the params, disable it */ + if (!hwAttrs->inputScalingEnabled){ + AUXADCDisableInputScaling(); + } + + /* Use synchronous sampling mode and prepare for trigger */ + AUXADCEnableSync(hwAttrs->refSource, hwAttrs->samplingDuration, hwAttrs->triggerSource); + + /* Manually trigger the ADC once */ + AUXADCGenManualTrigger(); + + /* Poll until the sample is ready */ + conversionValue = AUXADCReadFifo(); + + /* Get the status of the ADC_IRQ line and ADC_DONE. + * Despite not using the interrupt line, we need to clear it so that the + * ADCBuf driver does not call Hwi_construct and have thte interrupt fire + * immediately. + */ + interruptStatus = HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGS) & + (AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ | + AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE); + + /* Clear the ADC_IRQ flag in AUX_EVTCTL */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = interruptStatus; + + /* Clear the ADC_IRQ within the NVIC as AUX_EVTCTL will only set the + * relevant flag in the NVIC it will not clear it. + */ + HwiP_clearInterrupt(INT_AUX_ADC_IRQ); + + conversionResult = ADC_STATUS_SUCCESS; + + /* Shut down the ADC peripheral */ + AUXADCDisable(); + + /* Release the ADC hw semaphore */ + AUXSMPHRelease(AUX_SMPH_2); + + /* Allow entering standby again after ADC conversion complete */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (object->isProtected) { + /* Release the lock for this particular ADC handle */ + SemaphoreP_post(&adcSemaphore); + } + + /* If we want to return the trimmed value, calculate it here. */ + if (hwAttrs->returnAdjustedVal) { + uint32_t gain = AUXADCGetAdjustmentGain(hwAttrs->refSource); + uint32_t offset = AUXADCGetAdjustmentOffset(hwAttrs->refSource); + conversionValue = AUXADCAdjustValueForGainAndOffset(conversionValue, gain, offset); + } + + *value = conversionValue; + + /* Return the number of bytes transfered by the ADC */ + return conversionResult; +} + + +/* + * ======== ADCCC26XX_convertToMicroVolts ======== + */ +uint32_t ADCCC26XX_convertToMicroVolts(ADC_Handle handle, uint16_t adcValue){ + ADCCC26XX_HWAttrs const *hwAttrs; + uint32_t adjustedValue; + + DebugP_assert(handle); + + /* Get the pointer to the hwAttrs */ + hwAttrs = handle->hwAttrs; + + /* Only apply trim if specified*/ + if (hwAttrs->returnAdjustedVal) { + adjustedValue = adcValue; + } + else { + uint32_t gain = AUXADCGetAdjustmentGain(hwAttrs->refSource); + uint32_t offset = AUXADCGetAdjustmentOffset(hwAttrs->refSource); + adjustedValue = AUXADCAdjustValueForGainAndOffset(adcValue, gain, offset); + } + + return AUXADCValueToMicrovolts((hwAttrs->inputScalingEnabled ? AUXADC_FIXED_REF_VOLTAGE_NORMAL : AUXADC_FIXED_REF_VOLTAGE_UNSCALED), adjustedValue); +} + +/* + * ======== ADCCC26XX_init ======== + */ +void ADCCC26XX_init(ADC_Handle handle){ + ADCCC26XX_Object *object; + + /* Get the object */ + object = handle->object; + + /* Mark the object as available */ + object->isOpen = false; +} + +/* + * ======== ADCCC26XX_open ======== + */ +ADC_Handle ADCCC26XX_open(ADC_Handle handle, ADC_Params *params){ + ADCCC26XX_Object *object; + ADCCC26XX_HWAttrs const *hwAttrs; + PIN_Config adcPinTable[2]; + + DebugP_assert(handle); + + /* Get object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Determine if the driver was already opened */ + uint32_t key = HwiP_disable(); + + if (object->isOpen){ + DebugP_log0("ADC: Error! Already in use."); + HwiP_restore(key); + return NULL; + } + object->isOpen = true; + + /* remember thread safety protection setting */ + object->isProtected = params->isProtected; + + /* If this is the first handle requested, set up the semaphore as well */ + if (adcInstance == 0) { + /* Setup semaphore */ + SemaphoreP_constructBinary(&adcSemaphore, 1); + } + adcInstance++; + + /* On Chameleon, ANAIF must be clocked to use it. On Agama, the register inferface is always available. */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) + /* Turn on the ANAIF clock. ANIAF contains the aux ADC. */ + AUXWUCClockEnable(AUX_WUC_ANAIF_CLOCK); + AUXWUCClockEnable(AUX_WUC_ADI_CLOCK); +#endif + + HwiP_restore(key); + + /* Reserve the DIO defined in the hwAttrs */ + uint8_t i = 0; + + /* Add pin to measure on */ + adcPinTable[i++] = hwAttrs->adcDIO | + PIN_NOPULL | + PIN_INPUT_DIS | + PIN_GPIO_OUTPUT_DIS | + PIN_IRQ_DIS | + PIN_DRVSTR_MIN; + + /* Terminate pin list */ + adcPinTable[i] = PIN_TERMINATE; + object->pinHandle = PIN_open(&object->pinState, adcPinTable); + if (!object->pinHandle){ + DebugP_log0("ADC: Error! Already in use."); + object->isOpen = false; + return NULL; + } + + DebugP_log0("ADC: Object opened"); + + return handle; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adc/ADCCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adc/ADCCC26XX.h new file mode 100644 index 0000000..65fef67 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adc/ADCCC26XX.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2016-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ADCCC26XX.h + * @brief ADC driver implementation for the ADC peripheral on CC26XX + * + * This ADC driver implementation is designed to operate on a ADC peripheral + * for CC26XX. + * + * Refer to @ref ADC.h for a complete description of APIs & example of use. + * + ****************************************************************************** + */ +#ifndef ti_drivers_adc_ADCCC26XX__include +#define ti_drivers_adc_ADCCC26XX__include + +#include +#include + +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aux_adc.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Amount of time the ADC spends sampling the analogue input. + * + * The analogue to digital conversion process consists of two phases in the CC26XX ADC, + * the sampling and conversion phases. During the sampling phase, the ADC samples the + * analogue input signal. The duration of the sampling phase is configurable. + * Larger input loads require longer sample times for the most accurate + * results. + */ +typedef enum ADCCC26XX_Sampling_Duration { + ADCCC26XX_SAMPLING_DURATION_2P7_US = AUXADC_SAMPLE_TIME_2P7_US, + ADCCC26XX_SAMPLING_DURATION_5P3_US = AUXADC_SAMPLE_TIME_5P3_US, + ADCCC26XX_SAMPLING_DURATION_10P6_US = AUXADC_SAMPLE_TIME_10P6_US, + ADCCC26XX_SAMPLING_DURATION_21P3_US = AUXADC_SAMPLE_TIME_21P3_US, + ADCCC26XX_SAMPLING_DURATION_42P6_US = AUXADC_SAMPLE_TIME_42P6_US, + ADCCC26XX_SAMPLING_DURATION_85P3_US = AUXADC_SAMPLE_TIME_85P3_US, + ADCCC26XX_SAMPLING_DURATION_170_US = AUXADC_SAMPLE_TIME_170_US, + ADCCC26XX_SAMPLING_DURATION_341_US = AUXADC_SAMPLE_TIME_341_US, + ADCCC26XX_SAMPLING_DURATION_682_US = AUXADC_SAMPLE_TIME_682_US, + ADCCC26XX_SAMPLING_DURATION_1P37_MS = AUXADC_SAMPLE_TIME_1P37_MS, + ADCCC26XX_SAMPLING_DURATION_2P73_MS = AUXADC_SAMPLE_TIME_2P73_MS, + ADCCC26XX_SAMPLING_DURATION_5P46_MS = AUXADC_SAMPLE_TIME_5P46_MS, + ADCCC26XX_SAMPLING_DURATION_10P9_MS = AUXADC_SAMPLE_TIME_10P9_MS +} ADCCC26XX_Sampling_Duration; + +/*! + * @brief Specifies whether the internal reference of the ADC is sourced from the battery voltage or a fixed internal source. + * + * - In practice, using the internal fixed voltage reference sets the upper range of the ADC to a fixed value. That value is 4.3V with + * input scaling enabled and ~1.4785V with input scaling disabled. In this mode, the output is a function of the input voltage multiplied + * by the resolution in alternatives (not bits) divided by the upper voltage range of the ADC. Output = Input (V) * 2^12 / (ADC range (V)) + * + * - Using VDDS as a reference scales the upper range of the ADC with the battery voltage. As the battery depletes and its voltage drops, so does + * the range of the ADC. This is helpful when measuring signals that are generated relative to the battery voltage. In this mode, the output is + * a function of the input voltage multiplied by the resolution in alternatives (not bits) divided by VDDS multiplied by a scaling factor derived + * from the input scaling. Output = Input (V) * 2^12 / (VDDS (V) * Scaling factor), where the scaling factor is ~1.4785/4.3 for input scaling + * disabled and 1 for input scaling enabled. + * + * @note The actual reference values are slightly different for each device and are higher than the values specified above. This gain is saved in + * the FCFG. The function ::ADC_convertToMicroVolts() must be used to derive actual voltage values. Do not attempt to compare raw values + * between devices or derive a voltage from them yourself. The results of doing so will only be approximately correct. + * + * @warning Even though the upper voltage range of the ADC is 4.3 volts in fixed mode with input scaling enabled, the input should never exceed + * VDDS as per the data sheet. + */ +typedef enum ADCCC26XX_Reference_Source { + ADCCC26XX_FIXED_REFERENCE = AUXADC_REF_FIXED, + ADCCC26XX_VDDS_REFERENCE = AUXADC_REF_VDDS_REL +} ADCCC26XX_Reference_Source; + +/*! + * @brief List of sources the ADC can be configured to trigger off of. + * + * The ADC driver currently only supports the driver manually triggering a conversion. + * Support for other trigger sources may be added later. + */ +typedef enum ADCCC26XX_Trigger_Source { + ADCCC26XX_TRIGGER_MANUAL = AUXADC_TRIGGER_MANUAL, +} ADCCC26XX_Trigger_Source; + +/* ADC function table pointer */ +extern const ADC_FxnTable ADCCC26XX_fxnTable; + +/*! + * @brief ADCCC26XX Hardware attributes + * These fields are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. + * + */ +typedef struct ADCCC26XX_HWAttrs { + uint8_t adcDIO; /*!< DIO that the ADC is routed to */ + uint8_t adcCompBInput; /*!< Internal signal routed to comparator B */ + bool returnAdjustedVal; /*!< Should the raw output be trimmed before returning it */ + bool inputScalingEnabled; /*!< Is input scaling enabled */ + ADCCC26XX_Reference_Source refSource; /*!< Reference source for the ADC to use */ + ADCCC26XX_Sampling_Duration samplingDuration; /*!< Time the ADC spends sampling. This is load dependent */ + ADCCC26XX_Trigger_Source triggerSource; /*!< Source that the ADC triggers off of. Currently only supports AUXADC_TRIGGER_MANUAL */ +} ADCCC26XX_HWAttrs; + +/*! + * @brief ADCCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct ADCCC26XX_Object { + PIN_State pinState; /*!< Pin state object */ + PIN_Handle pinHandle; /*!< Pin handle */ + bool isOpen; /*!< Flag if the instance is in use */ + bool isProtected; /*!< Flag to indicate if thread safety is ensured by the driver */ +} ADCCC26XX_Object; + + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_adc_ADCCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26X2.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26X2.c new file mode 100644 index 0000000..afbeca0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26X2.c @@ -0,0 +1,877 @@ +/* + * Copyright (c) 2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* Kernel services */ +#include +#include +#include +#include +#include + +/* TI-RTOS drivers */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_aux_evctl.h) +#include DeviceFamily_constructPath(inc/hw_gpt.h) +#include DeviceFamily_constructPath(inc/hw_event.h) +#include DeviceFamily_constructPath(driverlib/aux_adc.h) +#include DeviceFamily_constructPath(driverlib/aux_smph.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) + +#define AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_NOT_EMPTY +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ + +/* + * ============================================================================= + * Public Function Declarations + * ============================================================================= + */ +void ADCBufCC26X2_init(ADCBuf_Handle handle); +ADCBuf_Handle ADCBufCC26X2_open(ADCBuf_Handle handle, const ADCBuf_Params *params); +int_fast16_t ADCBufCC26X2_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount); +int_fast16_t ADCBufCC26X2_convertCancel(ADCBuf_Handle handle); +void ADCBufCC26X2_close(ADCBuf_Handle handle); +uint_fast8_t ADCBufCC26X2_getResolution(ADCBuf_Handle handle); +int_fast16_t ADCBufCC26X2_adjustRawValues(ADCBuf_Handle handle, void *sampleBuffer, uint_fast16_t sampleCount, uint32_t adcChannel); +int_fast16_t ADCBufCC26X2_convertAdjustedToMicroVolts(ADCBuf_Handle handle, uint32_t adcChannel, void *adjustedSampleBuffer, uint32_t outputMicroVoltBuffer[], uint_fast16_t sampleCount); +int_fast16_t ADCBufCC26X2_control(ADCBuf_Handle handle, uint_fast16_t cmd, void *arg); + +/* + * ============================================================================= + * Private Function Declarations + * ============================================================================= + */ +static bool ADCBufCC26X2_acquireADCSemaphore(ADCBuf_Handle handle); +static bool ADCBufCC26X2_releaseADCSemaphore(ADCBuf_Handle handle); +static void ADCBufCC26X2_configDMA(ADCBuf_Handle handle, ADCBuf_Conversion *conversion); +static void ADCBufCC26X2_hwiFxn (uintptr_t arg); +static void ADCBufCC26X2_swiFxn (uintptr_t arg0, uintptr_t arg1); +static void ADCBufCC26X2_conversionCallback(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, void *completedADCBuffer, uint32_t completedChannel); +static uint32_t ADCBufCC26X2_freqToCounts(uint32_t frequency); +static void ADCBufCC26X2_cleanADC(ADCBuf_Handle handle); +static void ADCBufCC26X2_loadDMAControlTableEntry(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, bool primaryEntry); + +/* + * ============================================================================= + * Constants + * ============================================================================= + */ + +const ADCBuf_FxnTable ADCBufCC26X2_fxnTable = { + /*! Function to close the specified peripheral */ + ADCBufCC26X2_close, + /*! Function to driver implementation specific control function */ + ADCBufCC26X2_control, + /*! Function to initialize the given data object */ + ADCBufCC26X2_init, + /*! Function to open the specified peripheral */ + ADCBufCC26X2_open, + /*! Function to start an ADC conversion with the specified peripheral */ + ADCBufCC26X2_convert, + /*! Function to abort a conversion being carried out by the specified peripheral */ + ADCBufCC26X2_convertCancel, + /*! Function to get the resolution in bits of the ADC */ + ADCBufCC26X2_getResolution, + /*! Function to adjust raw ADC output values to values comparable between devices of the same type */ + ADCBufCC26X2_adjustRawValues, + /*! Function to convert adjusted ADC values to microvolts */ + ADCBufCC26X2_convertAdjustedToMicroVolts +}; + + +/* + * ============================================================================= + * Private Global Variables + * ============================================================================= + */ + +/* Allocate space for DMA control table entry */ +ALLOCATE_CONTROL_TABLE_ENTRY(dmaADCPriControlTableEntry, (UDMA_CHAN_AUX_ADC + UDMA_PRI_SELECT)); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaADCAltControlTableEntry, (UDMA_CHAN_AUX_ADC + UDMA_ALT_SELECT)); + +/* + * ============================================================================= + * Function Definitions + * ============================================================================= + */ + +/* + * ======== ADCBufCC26X2_init ======== + */ +void ADCBufCC26X2_init(ADCBuf_Handle handle) { + ADCBufCC26X2_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + /* Mark the object as available */ + object->isOpen = false; +} + + +/* + * ======== ADCBufCC26X2_open ======== + */ +ADCBuf_Handle ADCBufCC26X2_open(ADCBuf_Handle handle, const ADCBuf_Params *params) { + /* Use union to save on stack allocation */ + union { + HwiP_Params hwiParams; + SwiP_Params swiParams; + GPTimerCC26XX_Params timerParams; + } paramsUnion; + ADCBufCC26X2_Object *object; + ADCBufCC26X2_HWAttrs const *hwAttrs; + uint32_t key; + uint32_t adcPeriodCounts; + uint32_t gptConfig; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable preemption while checking if the ADC is open. */ + key = HwiP_disable(); + + /* Check if the ADC is open already with the base addr. */ + if (object->isOpen == true) { + HwiP_restore(key); + + DebugP_log0("ADCBuf: already in use."); + + return (NULL); + } + + /* Mark the handle as being used */ + object->isOpen = true; + + HwiP_restore(key); + + /* Initialise the ADC object */ + /* Initialise params section of object */ + object->conversionInProgress = false; + object->semaphoreTimeout = params->blockingTimeout; + object->samplingFrequency = params->samplingFrequency; + object->returnMode = params->returnMode; + object->recurrenceMode = params->recurrenceMode; + object->keepADCSemaphore = false; + object->adcSemaphoreInPossession = false; + + if (params->custom) { + /* If CC26X2 specific params were specified, use them */ + object->samplingDuration = ((ADCBufCC26X2_ParamsExtension *)(params->custom))->samplingDuration; + object->refSource = ((ADCBufCC26X2_ParamsExtension *)(params->custom))->refSource; + object->samplingMode = ((ADCBufCC26X2_ParamsExtension *)(params->custom))->samplingMode; + object->inputScalingEnabled = ((ADCBufCC26X2_ParamsExtension *)(params->custom))->inputScalingEnabled; + } + else { + /* Initialise CC26X2 specific settings to defaults */ + object->inputScalingEnabled = true; + object->refSource = ADCBufCC26X2_FIXED_REFERENCE; + object->samplingMode = ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS; + object->samplingDuration = ADCBufCC26X2_SAMPLING_DURATION_2P7_US; + } + + /* Open timer resource */ + GPTimerCC26XX_Params_init(¶msUnion.timerParams); + paramsUnion.timerParams.width = GPT_CONFIG_16BIT; + paramsUnion.timerParams.mode = GPT_MODE_PERIODIC_UP; + paramsUnion.timerParams.debugStallMode = GPTimerCC26XX_DEBUG_STALL_OFF; + object->timerHandle = GPTimerCC26XX_open(hwAttrs->gpTimerUnit, ¶msUnion.timerParams); + + if (object->timerHandle == NULL) { + /* We did not manage to open the GPTimer we wanted */ + return NULL; + } + + /* Enable capture toggle event on timeout. The ADC will trigger a + conversion on the rising edge of the event pulse. */ + gptConfig = HWREG(object->timerHandle->hwAttrs->baseAddr + GPT_O_TAMR); + HWREG(object->timerHandle->hwAttrs->baseAddr + GPT_O_TAMR) = (gptConfig & 0xFF) | GPT_TAMR_TCACT_TOG_ON_TO; + + /* Calculate period count for the GPT using double the sample freqency. + The GPT need to generate two events each ADC period to create + the trigger pulse. */ + adcPeriodCounts = ADCBufCC26X2_freqToCounts(params->samplingFrequency * 2); + GPTimerCC26XX_setLoadValue(object->timerHandle, adcPeriodCounts); + + if (params->returnMode == ADCBuf_RETURN_MODE_BLOCKING) { + /* Continuous trigger mode and blocking return mode is an illegal combination */ + DebugP_assert(!(params->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS)); + + /* Create a semaphore to block task execution for the duration of the ADC conversions */ + SemaphoreP_constructBinary(&(object->conversionComplete), 0); + + /* Store internal callback function */ + object->callbackFxn = ADCBufCC26X2_conversionCallback; + } + else { + /* Callback mode without a callback function defined */ + DebugP_assert(params->callbackFxn); + + /* Save the callback function pointer */ + object->callbackFxn = params->callbackFxn; + } + + /* Create the Hwi for this ADC peripheral. */ + HwiP_Params_init(¶msUnion.hwiParams); + paramsUnion.hwiParams.arg = (uintptr_t) handle; + paramsUnion.hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), INT_AUX_ADC_IRQ, ADCBufCC26X2_hwiFxn, ¶msUnion.hwiParams); + + /* Create the Swi object for this ADC peripheral */ + SwiP_Params_init(¶msUnion.swiParams); + paramsUnion.swiParams.arg0 = (uintptr_t)handle; + paramsUnion.swiParams.priority = hwAttrs->swiPriority; + SwiP_construct(&(object->swi), ADCBufCC26X2_swiFxn, &(paramsUnion.swiParams)); + + /* Declare the dependency on the UDMA driver */ + object->udmaHandle = UDMACC26XX_open(); + + /* Return the handle after finishing initialisation of the driver */ + DebugP_log0("ADC: opened"); + return handle; +} + + +/*! + * @brief HWI ISR of the ADC triggered when the DMA transaction is complete + * + * @param arg An ADCBufCC26X2_Handle + * + */ +static void ADCBufCC26X2_hwiFxn (uintptr_t arg) { + ADCBufCC26X2_Object *object; + ADCBuf_Conversion *conversion; + uint32_t intStatus; + + /* Get the pointer to the object and current conversion*/ + object = ((ADCBuf_Handle)arg)->object; + conversion = object->currentConversion; + + /* Set activeSampleBuffer to primary as default */ + object->activeSampleBuffer = conversion->sampleBuffer; + + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) { + /* Disable the ADC */ + AUXADCDisable(); + /* Disable ADC DMA if we are only doing one conversion and clear DMA done interrupt. */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_DMACTL) = AUX_EVCTL_DMACTL_REQ_MODE_SINGLE | AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY ; + } + else if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS) { + /* Reload the finished DMA control table entry */ + if (HWREG(UDMA0_BASE + UDMA_O_SETCHNLPRIALT) & (1 << UDMA_CHAN_AUX_ADC)) { + /* We are currently using the alternate entry -> we just finished the primary entry -> reload primary entry */ + ADCBufCC26X2_loadDMAControlTableEntry((ADCBuf_Handle)arg, conversion, true); + } + else { + /* We are currently using the primary entry -> we just finished the alternate entry -> reload the alternate entry */ + ADCBufCC26X2_loadDMAControlTableEntry((ADCBuf_Handle)arg, conversion, false); + object->activeSampleBuffer = conversion->sampleBufferTwo; + } + } + /* Clear DMA interrupts */ + UDMACC26XX_clearInterrupt(object->udmaHandle, (1 << UDMA_CHAN_AUX_ADC)); + + /* Get the status of the ADC_IRQ line and ADC_DONE */ + intStatus = HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGS) & (AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ | AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE); + /* Clear the ADC_IRQ flag if it triggered the ISR */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = intStatus; + + /* Post SWI to handle remaining clean up and invocation of callback */ + SwiP_post(&(object->swi)); +} + +/*! + * @brief SWI ISR of the ADC triggered when the DMA transaction is complete + * + * @param arg0 An ADCBufCC26X2_Handle + * + */ +static void ADCBufCC26X2_swiFxn (uintptr_t arg0, uintptr_t arg1) { + uint32_t key; + ADCBuf_Conversion *conversion; + ADCBufCC26X2_Object *object; + uint16_t *sampleBuffer; + uint8_t channel; + + /* Get the pointer to the object */ + object = ((ADCBuf_Handle)arg0)->object; + + DebugP_log0("ADC: swi interrupt context start"); + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Use a temporary pointers in case the callback function + * attempts to perform another ADCBuf_transfer call + */ + conversion = object->currentConversion; + sampleBuffer = object->activeSampleBuffer; + channel = object->currentChannel; + + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) { + /* Clean up ADC and DMA */ + ADCBufCC26X2_cleanADC(((ADCBuf_Handle)arg0)); + /* Indicate we are done with this transfer */ + object->currentConversion = NULL; + } + + /* Restore interrupts */ + HwiP_restore(key); + + /* Perform callback */ + object->callbackFxn((ADCBuf_Handle)arg0, conversion, sampleBuffer, channel); + + DebugP_log0("ADC: swi interrupt context end"); +} + +/*! + * @brief CC26X2 internal callback function that posts the semaphore in blocking mode + * + * @param handle An ADCBufCC26X2_Handle + * + * @param conversion A pointer to the current ADCBuf_Conversion + * + */ +static void ADCBufCC26X2_conversionCallback(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, void *completedADCBuffer, uint32_t completedChannel) { + ADCBufCC26X2_Object *object; + + DebugP_log0("ADC DMA: posting conversionComplete semaphore"); + + /* Get the pointer to the object */ + object = handle->object; + + /* Post the semaphore */ + SemaphoreP_post(&(object->conversionComplete)); +} + +/* + * ======== ADCBufCC26X2_convert ======== + */ +int_fast16_t ADCBufCC26X2_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount) { + uint32_t key; + ADCBufCC26X2_Object *object; + ADCBufCC26X2_HWAttrs const *hwAttrs; + PIN_Config adcPinTable[2]; + uint8_t i = 0; + + DebugP_assert(handle); + + /* Get the pointer to the object */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + DebugP_assert(channelCount == 1); + DebugP_assert((conversions->samplesRequestedCount <= UDMA_XFER_SIZE_MAX)); + DebugP_assert(conversions->sampleBuffer); + DebugP_assert(!(object->recurrenceMode == (ADCBuf_RECURRENCE_MODE_CONTINUOUS && !(conversions->sampleBufferTwo)))); + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Check if ADC is open and that no other transfer is in progress */ + if (!(object->isOpen) || object->conversionInProgress) { + /* Restore interrupts */ + HwiP_restore(key); + DebugP_log0("ADCBuf: conversion failed"); + return ADCBuf_STATUS_ERROR; + } + object->conversionInProgress = true; + + /* Restore interrupts*/ + HwiP_restore(key); + + /* Specify input in ADC module */ + AUXADCSelectInput(hwAttrs->adcChannelLut[conversions->adcChannel].compBInput); + + /* Add pin to measure on */ + adcPinTable[i++] = (hwAttrs->adcChannelLut[conversions->adcChannel].dio) | + PIN_NOPULL | + PIN_INPUT_DIS | + PIN_GPIO_OUTPUT_DIS | + PIN_IRQ_DIS | + PIN_DRVSTR_MIN; + + /* Terminate pin list */ + adcPinTable[i] = PIN_TERMINATE; + object->pinHandle = PIN_open(&object->pinState, adcPinTable); + if (!object->pinHandle) { + object->conversionInProgress = false; + return ADCBuf_STATUS_ERROR; + } + + /* Save which channel we are converting on for the callbackFxn */ + object->currentChannel = conversions->adcChannel; + + /* Try to acquire the ADC semaphore if we do not already have it. */ + if (object->adcSemaphoreInPossession == false) { + if (!AUXSMPHTryAcquire(AUX_SMPH_2)) { + PIN_close(object->pinHandle); + object->conversionInProgress = false; + DebugP_log0("ADCBuf: failed to acquire semaphore"); + return ADCBuf_STATUS_ERROR; + } + object->adcSemaphoreInPossession = true; + } + + /* Store location of the current conversion */ + object->currentConversion = conversions; + + /* Configure and arm the DMA and AUX DMA control */ + ADCBufCC26X2_configDMA(handle, conversions); + + /* Flush the ADC FIFO in case we have triggered prior to this call */ + AUXADCFlushFifo(); + + /* If input scaling is set to disabled in the params, disable it */ + if (!object->inputScalingEnabled) { + AUXADCDisableInputScaling(); + } + + /* Arm the ADC in preparation for incoming conversion triggers */ + if (object->samplingMode == ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS) { + /* ADCBufCC26X2_SYNCHRONOUS sampling mode */ + AUXADCEnableSync(object->refSource, object->samplingDuration, AUXADC_TRIGGER_GPT0A_CMP); + } + else { + /* ADCBufCC26X2_ASYNCHRONOUS sampling mode */ + AUXADCEnableAsync(object->refSource, AUXADC_TRIGGER_GPT0A_CMP); + } + + /* Start the GPTimer to create ADC triggers */ + GPTimerCC26XX_start(object->timerHandle); + + /* Set constraints to guarantee operation */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (object->returnMode == ADCBuf_RETURN_MODE_BLOCKING) { + DebugP_log0("ADCBuf: transfer pending on conversionComplete " + "semaphore"); + + if (SemaphoreP_OK != SemaphoreP_pend(&(object->conversionComplete), + object->semaphoreTimeout)) { + /* Cancel the transfer if we experience a timeout */ + ADCBufCC26X2_convertCancel(handle); + /* + * ADCBufCC26X2_convertCancel peforms a callback which posts a + * conversionComplete semaphore. This call consumes this extra post. + */ + SemaphoreP_pend(&(object->conversionComplete), SemaphoreP_NO_WAIT); + return ADCBuf_STATUS_ERROR; + } + } + + + return ADCBuf_STATUS_SUCCESS; +} + +/* + * ======== ADCBufCC26X2_convertCancel ======== + */ +int_fast16_t ADCBufCC26X2_convertCancel(ADCBuf_Handle handle) { + ADCBufCC26X2_Object *object; + ADCBuf_Conversion *conversion; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs*/ + object = handle->object; + + /* Check if ADC is open and that no other transfer is in progress */ + if (!(object->conversionInProgress)) { + DebugP_log0("ADCBuf: a conversion must be in progress to cancel one"); + return ADCBuf_STATUS_ERROR; + } + + /* Stop triggering a conversion on trigger events */ + AUXADCDisable(); + + /* Set hardware and software configuration to default and turn off driver */ + ADCBufCC26X2_cleanADC(handle); + + /* Use a temporary transaction pointer in case the callback function + * attempts to perform another ADCBuf_convert call + */ + conversion = object->currentConversion; + + /* Perform callback if we are in one-shot mode. In continuous mode, ADCBuf_convertCancel will probably be called from the callback functon itself. No need to call it again. */ + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) { + object->callbackFxn(handle, conversion, conversion->sampleBuffer, object->currentChannel); + } + + return ADCBuf_STATUS_SUCCESS; +} + +/* + * ======== ADCBufCC26X2_close ======== + */ +void ADCBufCC26X2_close(ADCBuf_Handle handle) { + ADCBufCC26X2_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object */ + object = handle->object; + + /* Check if the ADC is running and abort conversion if necessary. */ + if (object->conversionInProgress) { + ADCBuf_convertCancel(handle); + } + + /* Get the pointer to the object */ + object = handle->object; + + /* Release the uDMA dependency and potentially power down uDMA. */ + UDMACC26XX_close(object->udmaHandle); + + /* Destroy the Hwi */ + HwiP_destruct(&(object->hwi)); + + /* Destroy the Swi */ + SwiP_destruct(&(object->swi)); + + /* Close the timer */ + GPTimerCC26XX_close(object->timerHandle); + + if (object->returnMode == ADCBuf_RETURN_MODE_BLOCKING) { + SemaphoreP_destruct(&(object->conversionComplete)); + } + + /* Mark the module as available */ + object->isOpen = false; + + DebugP_log0("ADCBuf: closed"); +} + +/* + * ======== ADCBufCC26X2_getResolution ======== + */ +uint_fast8_t ADCBufCC26X2_getResolution(ADCBuf_Handle handle) { + return (ADCBufCC26X2_RESOLUTION); +} + +/* + * ======== ADCBufCC26X2_adjustRawValues ======== + */ +int_fast16_t ADCBufCC26X2_adjustRawValues(ADCBuf_Handle handle, void *sampleBuffer, uint_fast16_t sampleCount, uint32_t adcChannel) { + ADCBufCC26X2_Object *object; + uint32_t gain; + uint32_t offset; + uint16_t i; + + object = handle->object; + + gain = AUXADCGetAdjustmentGain(object->refSource); + offset = AUXADCGetAdjustmentOffset(object->refSource); + + for (i = 0; i < sampleCount; i++) { + uint16_t tmpRawADCVal = ((uint16_t *)sampleBuffer)[i]; + ((uint16_t *)sampleBuffer)[i] = AUXADCAdjustValueForGainAndOffset(tmpRawADCVal, gain, offset); + } + + return ADCBuf_STATUS_SUCCESS; +} + +/* + * ======== ADCBufCC26X2_convertAdjustedToMicroVolts ======== + */ +int_fast16_t ADCBufCC26X2_convertAdjustedToMicroVolts(ADCBuf_Handle handle, uint32_t adcChannel, void *adjustedSampleBuffer, uint32_t outputMicroVoltBuffer[], uint_fast16_t sampleCount) { + ADCBufCC26X2_Object *object; + uint16_t i; + uint32_t voltageRef; + + object = handle->object; + + voltageRef = (object->inputScalingEnabled) ? AUXADC_FIXED_REF_VOLTAGE_NORMAL : AUXADC_FIXED_REF_VOLTAGE_UNSCALED; + + for (i = 0; i < sampleCount; i++) { + outputMicroVoltBuffer[i] = AUXADCValueToMicrovolts(voltageRef, ((uint16_t *)adjustedSampleBuffer)[i]); + } + + return ADCBuf_STATUS_SUCCESS; +} + +/*! + * @brief Function to configure the DMA to automatically transfer ADC output data into a provided array + * + * @pre ADCBufCC26X2_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26X2 handle returned from ADCBufCC26X2_open() + * + * @param conversion A pointer to an ADCBuf_Conversion + * + */ +static void ADCBufCC26X2_configDMA(ADCBuf_Handle handle, ADCBuf_Conversion *conversion) { + ADCBufCC26X2_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Set configure control table entry */ + ADCBufCC26X2_loadDMAControlTableEntry(handle, conversion, true); + + /* If we are operating in continous mode, load the alternate DMA control table data structure */ + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS) { + ADCBufCC26X2_loadDMAControlTableEntry(handle, conversion, false); + } + + /* Enable the channels */ + UDMACC26XX_channelEnable(object->udmaHandle, 1 << UDMA_CHAN_AUX_ADC); + + /* Configure DMA settings in AUX_EVCTL */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_DMACTL) = AUX_EVCTL_DMACTL_REQ_MODE_SINGLE | AUX_EVCTL_DMACTL_EN | AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY; + + DebugP_log0("ADCBuf: DMA transfer enabled"); +} + +/*! + * @brief Function to configure the adc DMA control table entry for basic or ping pong mode + * + * @pre ADCBufCC26X2_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26X2 handle returned from ADCBufCC26X2_open() + * + * @param conversion A pointer to an ADCBuf_Conversion + * + * @param primaryEntry Is this supposed to modify the primary or the alternate control table entry + * + */ +static void ADCBufCC26X2_loadDMAControlTableEntry(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, bool primaryEntry) { + ADCBufCC26X2_Object *object; + volatile tDMAControlTable *dmaControlTableEntry; + uint32_t numberOfBytes; + + /* Get the pointer to the object*/ + object = handle->object; + + /* Calculate the number of bytes for the transfer */ + numberOfBytes = (uint16_t)(conversion->samplesRequestedCount) * ADCBufCC26X2_BYTES_PER_SAMPLE; + + /* Set configure control table entry */ + dmaControlTableEntry = primaryEntry ? &dmaADCPriControlTableEntry : &dmaADCAltControlTableEntry; + dmaControlTableEntry->ui32Control = ((object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) ? UDMA_MODE_BASIC : UDMA_MODE_PINGPONG) | + UDMA_SIZE_16 | + UDMA_SRC_INC_NONE | + UDMA_DST_INC_16 | + UDMA_ARB_1 | + UDMACC26XX_SET_TRANSFER_SIZE((uint16_t)conversion->samplesRequestedCount); + dmaControlTableEntry->pvDstEndAddr = (void *)((uint32_t)(primaryEntry ? conversion->sampleBuffer : conversion->sampleBufferTwo) + numberOfBytes - 1); + dmaControlTableEntry->pvSrcEndAddr = (void *)(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +/*! + * @brief Function to undo all configurations done by the ADC driver + * + * @pre ADCBuf_open() has to be called first. + * + * @pre ADCBuf_convert() has to be called first. + * + * @param handle An ADCBufCC26X2 handle returned from ADCBufCC26X2_open() + * + */ +static void ADCBufCC26X2_cleanADC(ADCBuf_Handle handle) { + ADCBufCC26X2_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Stop the timer to stop generating triggers */ + GPTimerCC26XX_stop(object->timerHandle); + + /* Set constraints to guarantee operation */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (object->adcSemaphoreInPossession && !object->keepADCSemaphore) { + /* Release the ADC semaphore */ + AUXSMPHRelease(AUX_SMPH_2); + object->adcSemaphoreInPossession = false; + } + + /* Disable the UDMA channels */ + UDMACC26XX_channelDisable(object->udmaHandle, (1 << UDMA_CHAN_AUX_ADC)); + + /* Deallocate pins */ + PIN_close(object->pinHandle); + + /* Disable UDMA mode for ADC */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_DMACTL) = AUX_EVCTL_DMACTL_REQ_MODE_SINGLE | AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY ; + + /* Note that the driver is no longer converting */ + object->conversionInProgress = false; +} + +/* Return period in timer counts */ +static uint32_t ADCBufCC26X2_freqToCounts(uint32_t frequency) +{ + ClockP_FreqHz freq; + ClockP_getCpuFreq(&freq); + + uint32_t periodCounts = (freq.lo / frequency) - 1; + + return periodCounts; +} + +/*! + * @brief Function to acquire the semaphore that arbitrates access to the ADC + * between the CM3 and the sensor controller + * + * @pre ADCBufCC26X2_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26X2 handle returned from ADCBufCC26X2_open() + * + */ +static bool ADCBufCC26X2_acquireADCSemaphore(ADCBuf_Handle handle) { + uint32_t key; + bool semaphoreAvailable; + ADCBufCC26X2_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Set semaphoreAvailable false at default */ + semaphoreAvailable = false; + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Check if ADC is closed or a conversion is in progress */ + if (!(object->isOpen) || object->conversionInProgress) { + DebugP_log0("ADC: driver must be open and no conversion must be in progress to disable input scaling"); + } + /* This is a non-blocking call to acquire the ADC semaphore. */ + else if (AUXSMPHTryAcquire(AUX_SMPH_2)) { + object->adcSemaphoreInPossession = true; + semaphoreAvailable = true; + } + + /* Restore interrupts */ + HwiP_restore(key); + + return semaphoreAvailable; +} + +/*! + * @brief This function releases the ADC semaphore + * + * @pre ADCBufCC26X2_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26X2 handle returned from ADCBufCC26X2_open() + * + */ +static bool ADCBufCC26X2_releaseADCSemaphore(ADCBuf_Handle handle) { + uint32_t key; + bool semaphoreReleased; + ADCBufCC26X2_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Set semaphoreReleased true at default */ + semaphoreReleased = true; + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Check if ADC is closed or a conversion is in progress */ + if (!(object->isOpen) || object->conversionInProgress) { + DebugP_log0("ADC: driver must be open and no conversion must be in progress to disable input scaling"); + semaphoreReleased = false; + } + else { + /* Release the ADC semaphore */ + AUXSMPHRelease(AUX_SMPH_2); + object->adcSemaphoreInPossession = false; + } + + /* Restore interrupts */ + HwiP_restore(key); + + return semaphoreReleased; +} + +/* + * ======== ADCBufCC26X2_control ======== + */ +int_fast16_t ADCBufCC26X2_control(ADCBuf_Handle handle, uint_fast16_t cmd, void * arg) { + ADCBufCC26X2_Object *object = handle->object; + int status = ADCBuf_STATUS_ERROR; + + DebugP_assert(handle); + + switch (cmd) { + case ADCBufCC26X2_CMD_ACQUIRE_ADC_SEMAPHORE: + if (ADCBufCC26X2_acquireADCSemaphore(handle)) { + status = ADCBuf_STATUS_SUCCESS; + } + break; + case ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE: + object->keepADCSemaphore = true; + status = ADCBuf_STATUS_SUCCESS; + break; + case ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE_DISABLE: + object->keepADCSemaphore = false; + status = ADCBuf_STATUS_SUCCESS; + break; + case ADCBufCC26X2_CMD_RELEASE_ADC_SEMAPHORE: + if (ADCBufCC26X2_releaseADCSemaphore(handle)) { + status = ADCBuf_STATUS_SUCCESS; + } + break; + default: + status = ADCBuf_STATUS_UNDEFINEDCMD; + break; + } + return status; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26X2.h new file mode 100644 index 0000000..eb7dad6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26X2.h @@ -0,0 +1,595 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ADCBufCC26X2.h + * + * @brief ADCBuf driver implementation for a CC26X2 analog-to-digital converter + * + * # Driver include # + * The ADCBuf header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * # Overview # + * This is a CC26X2 specific implementation of the generic TI-RTOS ADCBuf driver. + * The generic ADCBuf API specified in ti/drivers/ADCBuf.h should be called by the application, + * not the device specific implementation in ti/drivers/adcbuf/ADCBufCC26X2. + * The board file defines the device specific configuration and casting in the general + * API ensures the correct device specific functions are called. You should specify an + * ADCBufCC26X2_ParamsExtension in the custom field of the ADCBuf_Params that suits + * your application. The default settings work for many, but not all, usecases. + * + * # General Behavior # + * A timer and the DMA are used to trigger the ADC and fill a buffer in the background (in hardware) at a specified frequency. + * The application may execute other tasks while the hardware handles the conversions. + * In contrast to the standard ti/drivers/ADC driver, this driver allows for precise sampling of waveforms. + * + * | Driver | Number of samples needed in one call | + * |----------------|-----------------------------------------| + * | ADC.h | 1 | + * | ADCBuf.h | > 1 | + * + * This ADCBuf driver provides an API interface to using the analog-to-digital converter + * directly from the CM3 without going through the sensor controller. + * The sensor controller can still use the ADC, support for sharing the ADC resource between the + * sensor controller and the CM3 is built into the driver. There is a hardware semaphore that the + * driver must acquire before beginning any number of conversions. This same hardware semaphore also + * prevents the simultaneous use of this driver and the basic ADC driver. + * + * The ADC drivers supports making between one and 1024 measurements once or continuous + * measuring with returned buffer sizes between one and 1024 measurements. + * + * The application should call ADCBuf_init() once by the application to set the isOpened + * flag to false, indicating that the driver is ready to use. + * + * The ADC driver is opened by calling ADCBuf_open() which will + * set up interrupts and configure the internal components of the driver. + * However, the ADC hardware or analog pins are not yet configured, since the sensor + * controller or basic ADC driver might be using the ADC. + * + * In order to perform an ADC conversion, the application should call + * ADCBuf_convert(). This call will request the ADC resource, configure the ADC, set up the DMA and GPTimer, + * and perform the requested ADC conversions on the selected DIO or internal signal. The DIO or internal signal is defined by the + * ADCBuf_Conversion structure in the application code and adcBufCC26x2Objects in the board file. + * + * @warning If the ADCBUF driver is setup in ADCBuf_RECURRENCE_MODE_CONTINUOUS mode, the user must assure that the provided callback + * function is completed before the next conversion completes. If the next conversion completes before the callback function finishes, + * the DMA will clobber the previous buffer with new data. + * + * If the sensor controller is using the ADC when the driver requests it at the start of the ADC_convert() call, + * the conversion will fail and return false. + * The ADC resource may be pre-acquired by calling the control function ADCBufCC26X2_CMD_ACQUIRE_ADC_SEMAPHORE. + * It will be released again automatically after the next conversion completes. + * + * In both ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS mode and ADCBufCC26X2_SAMPING_MODE_ASYNCHRONOUS mode, enough sampling + * time must be provided between conversions that each measurement may be completed before the next trigger arrives. + * + * @note The ADCBuf driver requires GPTimer0A to function correctly. It will be unavailable for other uses. + * + * # Supported ADC pins # + * Below is a table of the supported ADC IO pins for each package size, for both CC26x2 and CC13x2. + * It maps a DIO to its corresponding driverlib define for the CompBInput that it is hardwired to. + * This table can be used to create virtual channel entries in the ADCBufCC26X2_adcChannelLut table in the board file. + * + * | DIO | CC26x2 7x7 AUXIO CompBInput | CC13x2 7x7 AUXIO CompBInput + * |--------|-------------------------------|------------------------------- + * | 0 | No | No + * | 1 | No | No + * | 2 | No | No + * | 3 | No | No + * | 4 | No | No + * | 5 | No | No + * | 6 | No | No + * | 7 | No | No + * | 8 | No | No + * | 9 | No | No + * | 10 | No | No + * | 11 | No | No + * | 12 | No | No + * | 13 | No | No + * | 14 | No | No + * | 15-22 | No | No + * | 23 | ADC_COMPB_IN_AUXIO7 | ADC_COMPB_IN_AUXIO7 + * | 24 | ADC_COMPB_IN_AUXIO6 | ADC_COMPB_IN_AUXIO6 + * | 25 | ADC_COMPB_IN_AUXIO5 | ADC_COMPB_IN_AUXIO5 + * | 26 | ADC_COMPB_IN_AUXIO4 | ADC_COMPB_IN_AUXIO4 + * | 27 | ADC_COMPB_IN_AUXIO3 | ADC_COMPB_IN_AUXIO3 + * | 28 | ADC_COMPB_IN_AUXIO2 | ADC_COMPB_IN_AUXIO2 + * | 29 | ADC_COMPB_IN_AUXIO1 | ADC_COMPB_IN_AUXIO1 + * | 30 | ADC_COMPB_IN_AUXIO0 | ADC_COMPB_IN_AUXIO0 + * + * # Supported Internal Signals # + * Below is a table of internal signals that can be measured using the ADC. + * Since we are not connecting to a DIO, there is no DIO to internal signal mapping. The DIO field in the channel lookup table should be marked PIN_UNASSIGNED. + * This table can be used to create virtual channel entries in the ADCBufCC26X2_adcChannelLut table in the board file. + * + * | DIO | Internal Signal CompBInput | + * |--------------------|-------------------------------| + * | PIN_UNASSIGNED | ADC_COMPB_IN_DCOUPL | + * | PIN_UNASSIGNED | ADC_COMPB_IN_VSS | + * | PIN_UNASSIGNED | ADC_COMPB_IN_VDDS | + * + * # Error handling # + * The following errors may occur when opening the ADC without assertions enabled: + * - The ADC handle is already open. + * + * The following errors may occur when requesting an ADC conversion: + * - The ADC is currently already doing a conversion. + * - The ADC was not available (used by sensor controller or basic ADC). + * + * + * # Power Management # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * While converting, the ADCBufCC26X2 driver sets a power constraint to keep + * the device out of standby. When the conversion has finished, the power + * constraint is released. The driver also sets a dependency on the DMA to enable + * background transfers from the ADC FIFO to memory. + * The following statements are valid: + * - After ADCBuf_convert(): the device cannot enter standby. + * - After ADCBuf_convertCancel(): the device can enter standby again. + * - After a conversion finishes: the device can enter standby again. + * + * + * # Supported Functions # + * | API function | Description | + * |------------------------------------|-----------------------------------------------------------------------| + * | ADCBuf_init() | Initialize ADC driver | + * | ADCBuf_open() | Open the ADC driver and configure driver | + * | ADCBuf_convert() | Perform ADC conversion | + * | ADCBuf_convertCancel() | Cancel ongoing ADC conversion | + * | ADCBuf_close() | Close ADC driver | + * | ADCBuf_Params_init() | Initialise ADCBuf_Params structure to default values | + * | ADCBuf_getResolution() | Get the resolution of the ADC of the current device | + * | ADCBuf_adjustRawValues() | Adjust the values in a returned buffer for manufacturing tolerances | + * | ADCBuf_convertAdjustedToMicroVolts | Convert a buffer of adjusted values to microvolts | + * | ADCBuf_control() | Execute device specific functions | + * + * + * # Not Supported Functionality # + * - Performing conversions on multiple channels simultaneously is not supported. + * In other words, the parameter channelCount must always be set to 1 when calling ADCBuf_convert(). + * The ADC on CC26XX devices does not support time-division multiplexing of channels or pins in hardware. + * + * # Use Cases # + * ## Basic one-shot conversion # + * Perform one conversion on Board_ADCCHANNEL_A1 in ::ADCBuf_RETURN_MODE_BLOCKING. + * @code + * #include + * + * #define ADCBUFFERSIZE 100 + * + * ADCBuf_Handle adcBufHandle; + * ADCBuf_Params adcBufParams; + * ADCBuf_Conversion blockingConversion; + * uint16_t sampleBufferOne[ADCBUFFERSIZE]; + * + * ADCBuf_Params_init(&adcBufParams); + * adcBufHandle = ADCBuf_open(Board_ADCBuf0, &adcBufParams); + * if (adcBufHandle == NULL) { + * // handle error + * } + * + * blockingConversion.arg = NULL; + * blockingConversion.adcChannel = Board_ADCCHANNEL_A1; + * blockingConversion.sampleBuffer = sampleBufferOne; + * blockingConversion.sampleBufferTwo = NULL; + * blockingConversion.samplesRequestedCount = ADCBUFFERSIZE; + * + * if (ADCBuf_convert(adcBufHandle, &blockingConversion, 1) != ADCBuf_STATUS_SUCCESS) { + * // handle error + * } + * @endcode + * + * ## Using ADCBufCC26X2_ParamsExtension # + * This specific configuration performs one conversion on Board_ADCCHANNEL_A1 in ::ADCBuf_RETURN_MODE_BLOCKING. + * The custom parameters used here are identical to the defaults parameters. + * Users can of course define their own parameters. + * @code + * #include + * + * #define ADCBUFFERSIZE 100 + * + * ADCBuf_Handle adcBufHandle; + * ADCBuf_Params adcBufParams; + * ADCBuf_Conversion blockingConversion; + * uint16_t sampleBufferOne[ADCBUFFERSIZE]; + * ADCBufCC26X2_ParamsExtension customParams; + * + * ADCBuf_Params_init(&adcBufParams); + * customParams.samplingDuration = ADCBufCC26X2_SAMPLING_DURATION_2P7_US; + * customParams.refSource = ADCBufCC26X2_FIXED_REFERENCE; + * customParams.samplingMode = ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS; + * customParams.inputScalingEnabled = true; + * + * adcBufParams.custom = &customParams; + * + * adcBufHandle = ADCBuf_open(Board_ADCBuf0, &adcBufParams); + * if (adcBufHandle == NULL) { + * // handle error + * } + * + * blockingConversion.arg = NULL; + * blockingConversion.adcChannel = Board_ADCCHANNEL_A1; + * blockingConversion.sampleBuffer = sampleBufferOne; + * blockingConversion.sampleBufferTwo = NULL; + * blockingConversion.samplesRequestedCount = ADCBUFFERSIZE; + * + * if (ADCBuf_convert(adcBufHandle, &blockingConversion, 1) != ADCBuf_STATUS_SUCCESS) { + * // handle error + * } + * @endcode + * + * # Instrumentation # + * The ADC driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic ADCBuf operations performed | + * Diags_USER2 | detailed ADCBuf operations performed | + * + ****************************************************************************** + */ + +#ifndef ti_drivers_adc_adcbufcc26xx__include +#define ti_drivers_adc_adcbufcc26xx__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aux_adc.h) + +#include +#include +#include +#include + +/** @}*/ + +/** + * @addtogroup ADCBuf_CMD + * ADCBufCC26X2_CMD_* macros are command codes only defined in the ADCBufCC26X2.h + * driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add ADCBufCC26X2_CMD_* macros here */ + +/*! + * @brief This control function acquires the semaphore that arbitrates access to the ADC + * between the CM3 and the sensor controller + * + * This function pre-acquires the ADC semaphore before ADCBuf_convert() is called by the application. + * Normally, the ADC driver acquires the ADC semaphore when calling ADCBufCC26X2_convert(). + * The driver may need to wait for the sensor controller to release the semaphore in order to + * access the ADC hardware module. Consequently, the time at which the conversion is actually + * made is normally non-deterministic. + * Pre-acquiring the semaphore makes the ADCBuf_convert() call deterministic. + * + * @note This function returns an error if the handle is not open or a transfer is in progress + */ +#define ADCBufCC26X2_CMD_ACQUIRE_ADC_SEMAPHORE ADCBuf_CMD_RESERVED + 1 + +/*! + * @brief This function makes the ADC driver keep the ADC semaphore until released + * + * Calling this function will make the ADC driver keep the ADC semaphore until it is released by + * the application by calling the control function ADCBufCC26X2_CMD_RELEASE_ADC_SEMAPHORE. + * This enables multiple deterministic conversions to be made. + * Usually, the driver will release the semaphore after the conversion finishes. + * + * @warning The sensor controller can no longer access the ADC until the semaphore is released by + * the application manually. + * + * @sa ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE_DISABLE + */ +#define ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE ADCBuf_CMD_RESERVED + 2 + +/*! + * @brief This function makes the ADC driver no longer keep the ADC semaphore until released + * + * This function effectively reverses a call to ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE_DISABLE. + * + * @sa ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE + */ +#define ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE_DISABLE ADCBuf_CMD_RESERVED + 3 + +/*! + * @brief This function releases the ADC semaphore + * + * @note This function returns an error if the handle is not open or a transfer is in progress + */ +#define ADCBufCC26X2_CMD_RELEASE_ADC_SEMAPHORE ADCBuf_CMD_RESERVED + 4 + +/** @}*/ + +/*! + * @brief Resolution in bits of the CC26X2 ADC + */ +#define ADCBufCC26X2_RESOLUTION 12 + +#define ADCBufCC26X2_BYTES_PER_SAMPLE 2 + +/* + * ============================================================================= + * Constants + * ============================================================================= + */ + +/* ADCBuf function table pointer */ +extern const ADCBuf_FxnTable ADCBufCC26X2_fxnTable; + + +/* + * ============================================================================= + * Enumerations + * ============================================================================= + */ + +/*! + * @brief Specifies whether the internal reference of the ADC is sourced from the battery voltage or a fixed internal source. + * + * The CC26X2 ADC can operate in two different ways with regards to the sampling phase of the ADC conversion process: + * - It can spend a fixed amount of time sampling the signal after getting the start conversion trigger. + * - It can constantly keep sampling and immediately start the conversion process after getting the trigger. + * + * In ADCBufCC26X2_SYNCHRONOUS mode, the ADC goes into IDLE in between conversions and uses less power. + * The minimum sample time for full precision in ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS is dependent on the input load. + */ +typedef enum ADCBufCC26X2_Sampling_Mode { + ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS, + ADCBufCC26X2_SAMPING_MODE_ASYNCHRONOUS +} ADCBufCC26X2_Sampling_Mode; + +/*! + * @brief Amount of time the ADC spends sampling the analogue input. + * + * The analogue to digital conversion process consists of two phases in the CC26X2 ADC, + * the sampling and conversion phases. During the sampling phase, the ADC samples the + * analogue input signal. Larger input loads require longer sample times for the most accurate + * results. In ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS mode, this enum specifies the sampling times available. + */ +typedef enum ADCBufCC26X2_Sampling_Duration { + ADCBufCC26X2_SAMPLING_DURATION_2P7_US = AUXADC_SAMPLE_TIME_2P7_US, + ADCBufCC26X2_SAMPLING_DURATION_5P3_US = AUXADC_SAMPLE_TIME_5P3_US, + ADCBufCC26X2_SAMPLING_DURATION_10P6_US = AUXADC_SAMPLE_TIME_10P6_US, + ADCBufCC26X2_SAMPLING_DURATION_21P3_US = AUXADC_SAMPLE_TIME_21P3_US, + ADCBufCC26X2_SAMPLING_DURATION_42P6_US = AUXADC_SAMPLE_TIME_42P6_US, + ADCBufCC26X2_SAMPLING_DURATION_85P3_US = AUXADC_SAMPLE_TIME_85P3_US, + ADCBufCC26X2_SAMPLING_DURATION_170_US = AUXADC_SAMPLE_TIME_170_US, + ADCBufCC26X2_SAMPLING_DURATION_341_US = AUXADC_SAMPLE_TIME_341_US, + ADCBufCC26X2_SAMPLING_DURATION_682_US = AUXADC_SAMPLE_TIME_682_US, + ADCBufCC26X2_SAMPLING_DURATION_1P37_MS = AUXADC_SAMPLE_TIME_1P37_MS, + ADCBufCC26X2_SAMPLING_DURATION_2P73_MS = AUXADC_SAMPLE_TIME_2P73_MS, + ADCBufCC26X2_SAMPLING_DURATION_5P46_MS = AUXADC_SAMPLE_TIME_5P46_MS, + ADCBufCC26X2_SAMPLING_DURATION_10P9_MS = AUXADC_SAMPLE_TIME_10P9_MS +} ADCBufCC26X2_Sampling_Duration; + + +/*! + * @brief Specifies whether the internal reference of the ADC is sourced from the battery voltage or a fixed internal source. + * + * - In practice, using the internal fixed voltage reference sets the upper range of the ADC to a fixed value. That value is 4.3V with + * input scaling enabled and ~1.4785V with input scaling disabled. In this mode, the output is a function of the input voltage multiplied + * by the resolution in alternatives (not bits) divided by the upper voltage range of the ADC. Output = Input (V) * 2^12 / (ADC range (V)) + * + * - Using VDDS as a reference scales the upper range of the ADC with the battery voltage. As the battery depletes and its voltage drops, so does + * the range of the ADC. This is helpful when measuring signals that are generated relative to the battery voltage. In this mode, the output is + * a function of the input voltage multiplied by the resolution in alternatives (not bits) divided by VDDS multiplied by a scaling factor derived + * from the input scaling. Output = Input (V) * 2^12 / (VDDS (V) * Scaling factor), where the scaling factor is ~1.4785/4.3 for input scaling + * disabled and 1 for input scaling enabled. + * + * @note The actual reference values are slightly different for each device and are higher than the values specified above. This gain is saved in + * the FCFG. The function ADCBuf_convertRawToMicroVolts() must be used to derive actual voltage values. Do not attempt to compare raw values + * between devices or derive a voltage from them yourself. The results of doing so will only be approximately correct. + * + * @warning Even though the upper voltage range of the ADC is 4.3 volts in fixed mode with input scaling enabled, the input should never exceed + * VDDS as per the data sheet. + */ +typedef enum ADCBufCC26X2_Reference_Source { + ADCBufCC26X2_FIXED_REFERENCE = AUXADC_REF_FIXED, + ADCBufCC26X2_VDDS_REFERENCE = AUXADC_REF_VDDS_REL +} ADCBufCC26X2_Reference_Source; + + + +/* + * ============================================================================= + * Structs + * ============================================================================= + */ + + /*! + * @brief Table entry that maps a virtual adc channel to a dio and its corresponding internal analogue signal + * + * Non-dio signals can be used as well. To do this, compBInput is set to the driverlib define corresponding to the + * desired non-dio signal and dio is set to PIN_UNASSIGNED. + */ +typedef struct ADCBufCC26X2_AdcChannelLutEntry{ + uint8_t dio; /*!< DIO that this virtual channel is mapped to */ + uint8_t compBInput; /*!< CompBInput that this virtual channel is mapped to */ +} ADCBufCC26X2_AdcChannelLutEntry; + +/*! + * @brief CC26X2 specfic extension to ADCBuf_Params + * + * To use non-default CC26X2 specific parameters when calling ADCBuf_open(), a pointer + * to an instance of this struct must be specified in ADCBuf_Params::custom. Alternatively, + * these values can be set using the control function after calling ADCBuf_open(). + */ +typedef struct ADCBufCC26X2_ParamsExtension{ + /*! Amount of time the ADC spends sampling the analogue input */ + ADCBufCC26X2_Sampling_Duration samplingDuration; + /*! Specifies whether the ADC spends a fixed amount of time sampling or the entire time since the last conversion */ + ADCBufCC26X2_Sampling_Mode samplingMode; + /*! Specifies whether the internal reference of the ADC is sourced from the battery voltage or a fixed internal source */ + ADCBufCC26X2_Reference_Source refSource; + /*! + * Disable input scaling. Input scaling scales an external analogue + * signal between 0 and 4.3V to an internal signal of 0 to ~1.4785V. + * Since the largest permissible input to any pin is VDDS, the maximum + * range of the ADC is effectively less than 3.8V and continues to shrink + * as the battery voltage drops. + * With input scaling disabled, the external analogue signal is passed + * on directly to the internal electronics. Signals larger than ~1.4785V + * will damage the device with input scaling disabled. + * + * | Input scaling status | Maximum permissible ADC input voltage | + * |---------------------------|---------------------------------------| + * | Enabled | VDDS (Battery voltage level) | + * | Disabled | 1.4785V | + */ + bool inputScalingEnabled; +} ADCBufCC26X2_ParamsExtension; + +/*! + * @brief ADCBufCC26X2 Hardware Attributes + * + * These fields are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC26xxWare these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * A sample structure is shown below: + * @code + * const ADCBufCC26X2_HWAttrs ADCBufCC26X2HWAttrs[] = { + * { + * .intPriority = ~0, + * .swiPriority = 0, + * } + * }; + * @endcode + */ +typedef struct ADCBufCC26X2_HWAttrs{ + /*! @brief ADC SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! @brief ADC peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! Pointer to a table of ADCBufCC26X2_AdcChannelLutEntry's mapping internal CompBInput to DIO */ + ADCBufCC26X2_AdcChannelLutEntry const *adcChannelLut; + /*! GPTimer unit index (0A, 0B, 1A..). Currently only the 0A unit index is supported. */ + uint8_t gpTimerUnit; +} ADCBufCC26X2_HWAttrs; + + + +/*! + * @brief ADCBufCC26X2 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct ADCBufCC26X2_Object{ + /* ADC control variables */ + bool isOpen; /*!< Has the obj been opened */ + bool conversionInProgress; /*!< Is the ADC currently doing conversions */ + bool inputScalingEnabled; /*!< Is the analogue input scaled */ + bool keepADCSemaphore; /*!< Should the driver keep the ADC semaphore after a conversion */ + bool adcSemaphoreInPossession; /*!< Does the driver currently possess the ADC semaphore */ + uint8_t currentChannel; /*!< The current virtual channel the ADCBuf driver is sampling on */ + ADCBufCC26X2_Reference_Source refSource; /*!< Reference source for the ADC to use */ + ADCBufCC26X2_Sampling_Mode samplingMode; /*!< Synchronous or asynchronous sampling mode */ + ADCBufCC26X2_Sampling_Duration samplingDuration; /*!< Time the ADC spends sampling in ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS */ + ADCBuf_Callback callbackFxn; /*!< Pointer to callback function */ + ADCBuf_Recurrence_Mode recurrenceMode; /*!< Should we convert continuously or one-shot */ + ADCBuf_Return_Mode returnMode; /*!< Mode for all conversions */ + uint16_t *activeSampleBuffer; /*!< The last complete sample buffer used by the DMA */ + + /* ADC SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object */ + SwiP_Struct swi; /*!< Swi object */ + SemaphoreP_Struct conversionComplete; /*!< ADC semaphore */ + + ADCBuf_Conversion *currentConversion; /*!< Pointer to the current conversion struct */ + + /* PIN driver state object and handle */ + PIN_State pinState; /*!< Pin state object */ + PIN_Handle pinHandle; /*!< Pin handle */ + + /* UDMA driver handle */ + UDMACC26XX_Handle udmaHandle; /*!< UDMA handle */ + + /* GPTimer driver handle */ + GPTimerCC26XX_Handle timerHandle; /*!< Handle to underlying GPTimer peripheral */ + + uint32_t semaphoreTimeout; /*!< Timeout for read semaphore in ::ADCBuf_RETURN_MODE_BLOCKING */ + uint32_t samplingFrequency; /*!< Frequency in Hz at which the ADC is triggered */ +} ADCBufCC26X2_Object, *ADCBufCC26X2_Handle; + +/* + * ============================================================================= + * Functions + * ============================================================================= + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_adc_ADCBufCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26XX.c new file mode 100644 index 0000000..940caeb --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26XX.c @@ -0,0 +1,971 @@ +/* + * Copyright (c) 2016-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* Kernel services */ +#include +#include +#include +#include +#include + +/* TI-RTOS drivers */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_aux_evctl.h) +#include DeviceFamily_constructPath(driverlib/aux_adc.h) +#include DeviceFamily_constructPath(driverlib/aux_smph.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) + #include DeviceFamily_constructPath(driverlib/aux_wuc.h) +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) + #define AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_NOT_EMPTY + #define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE + #define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ +#endif + +/* + * ============================================================================= + * Public Function Declarations + * ============================================================================= + */ +void ADCBufCC26XX_init(ADCBuf_Handle handle); +ADCBuf_Handle ADCBufCC26XX_open(ADCBuf_Handle handle, const ADCBuf_Params *params); +int_fast16_t ADCBufCC26XX_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount); +int_fast16_t ADCBufCC26XX_convertCancel(ADCBuf_Handle handle); +void ADCBufCC26XX_close(ADCBuf_Handle handle); +uint_fast8_t ADCBufCC26XX_getResolution(ADCBuf_Handle handle); +int_fast16_t ADCBufCC26XX_adjustRawValues(ADCBuf_Handle handle, void *sampleBuffer, uint_fast16_t sampleCount, uint32_t adcChannel); +int_fast16_t ADCBufCC26XX_convertAdjustedToMicroVolts(ADCBuf_Handle handle, uint32_t adcChannel, void *adjustedSampleBuffer, uint32_t outputMicroVoltBuffer[], uint_fast16_t sampleCount); +int_fast16_t ADCBufCC26XX_control(ADCBuf_Handle handle, uint_fast16_t cmd, void *arg); + +/* + * ============================================================================= + * Private Function Declarations + * ============================================================================= + */ +static bool ADCBufCC26XX_acquireADCSemaphore(ADCBuf_Handle handle); +static bool ADCBufCC26XX_releaseADCSemaphore(ADCBuf_Handle handle); +static void ADCBufCC26XX_configDMA(ADCBuf_Handle handle, ADCBuf_Conversion *conversion); +static void ADCBufCC26XX_hwiFxn (uintptr_t arg); +static void ADCBufCC26XX_swiFxn (uintptr_t arg0, uintptr_t arg1); +static void ADCBufCC26XX_conversionCallback(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, void *completedADCBuffer, uint32_t completedChannel); +static uint32_t ADCBufCC26XX_freqToCounts(uint32_t frequency); +static void ADCBufCC26XX_configGPTDMA(ADCBuf_Handle handle, ADCBuf_Conversion *conversion); +static void ADCBufCC26XX_cleanADC(ADCBuf_Handle handle); +static void ADCBufCC26XX_loadDMAControlTableEntry(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, bool primaryEntry); +static void ADCBufCC26XX_loadGPTDMAControlTableEntry(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, bool primaryEntry); + +/* + * ============================================================================= + * Constants + * ============================================================================= + */ + +const ADCBuf_FxnTable ADCBufCC26XX_fxnTable = { + /*! Function to close the specified peripheral */ + ADCBufCC26XX_close, + /*! Function to driver implementation specific control function */ + ADCBufCC26XX_control, + /*! Function to initialize the given data object */ + ADCBufCC26XX_init, + /*! Function to open the specified peripheral */ + ADCBufCC26XX_open, + /*! Function to start an ADC conversion with the specified peripheral */ + ADCBufCC26XX_convert, + /*! Function to abort a conversion being carried out by the specified peripheral */ + ADCBufCC26XX_convertCancel, + /*! Function to get the resolution in bits of the ADC */ + ADCBufCC26XX_getResolution, + /*! Function to adjust raw ADC output values to values comparable between devices of the same type */ + ADCBufCC26XX_adjustRawValues, + /*! Function to convert adjusted ADC values to microvolts */ + ADCBufCC26XX_convertAdjustedToMicroVolts +}; + + +/* + * ============================================================================= + * Private Global Variables + * ============================================================================= + */ + +/* Allocate space for DMA control table entry */ +ALLOCATE_CONTROL_TABLE_ENTRY(dmaADCPriControlTableEntry, (UDMA_CHAN_AUX_ADC + UDMA_PRI_SELECT)); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaADCAltControlTableEntry, (UDMA_CHAN_AUX_ADC + UDMA_ALT_SELECT)); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaGPT0APriControlTableEntry, (UDMA_CHAN_TIMER0_A + UDMA_PRI_SELECT)); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaGPT0AAltControlTableEntry, (UDMA_CHAN_TIMER0_A + UDMA_ALT_SELECT)); + +/*! + * Timeout interrupt bitmask of the GPT that the DMA copies into GPT_O_ICLR + * to bring the DMA trigger event low. + * Needs to go into RAM not flash to prevent system from hanging in edge cases. + */ +static uint8_t gptClear = GPT_ICLR_TATOCINT; + +/* + * ============================================================================= + * Function Definitions + * ============================================================================= + */ + +/* + * ======== ADCBufCC26XX_init ======== + */ +void ADCBufCC26XX_init(ADCBuf_Handle handle) { + ADCBufCC26XX_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + /* Mark the object as available */ + object->isOpen = false; +} + + +/* + * ======== ADCBufCC26XX_open ======== + */ +ADCBuf_Handle ADCBufCC26XX_open(ADCBuf_Handle handle, + const ADCBuf_Params *params) { + /* Use union to save on stack allocation */ + union { + HwiP_Params hwiParams; + SwiP_Params swiParams; + GPTimerCC26XX_Params timerParams; + } paramsUnion; + ADCBufCC26XX_Object *object; + ADCBufCC26XX_HWAttrs const *hwAttrs; + uint32_t key; + uint32_t adcPeriodCounts; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable preemption while checking if the ADC is open. */ + key = HwiP_disable(); + + /* Check if the ADC is open already with the base addr. */ + if (object->isOpen == true) { + HwiP_restore(key); + + DebugP_log0("ADCBuf: already in use."); + + return (NULL); + } + + /* Mark the handle as being used */ + object->isOpen = true; + + /* On Chameleon, ANAIF must be clocked to use it. On Agama, the register inferface is always available. */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) + /* Turn on the ANAIF clock. ANIAF contains the AUX ADC. */ + AUXWUCClockEnable(AUX_WUC_ANAIF_CLOCK); + AUXWUCClockEnable(AUX_WUC_ADI_CLOCK); +#endif + + HwiP_restore(key); + + /* Initialise the ADC object */ + /* Initialise params section of object */ + object->conversionInProgress = false; + object->semaphoreTimeout = params->blockingTimeout; + object->samplingFrequency = params->samplingFrequency; + object->returnMode = params->returnMode; + object->recurrenceMode = params->recurrenceMode; + object->keepADCSemaphore = false; + object->adcSemaphoreInPossession = false; + + if (params->custom) { + /* If CC26XX specific params were specified, use them */ + object->samplingDuration = ((ADCBufCC26XX_ParamsExtension *)(params->custom))->samplingDuration; + object->refSource = ((ADCBufCC26XX_ParamsExtension *)(params->custom))->refSource; + object->samplingMode = ((ADCBufCC26XX_ParamsExtension *)(params->custom))->samplingMode; + object->inputScalingEnabled = ((ADCBufCC26XX_ParamsExtension *)(params->custom))->inputScalingEnabled; + } + else { + /* Initialise CC26XX specific settings to defaults */ + object->inputScalingEnabled = true; + object->refSource = ADCBufCC26XX_FIXED_REFERENCE; + object->samplingMode = ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS; + object->samplingDuration = ADCBufCC26XX_SAMPLING_DURATION_2P7_US; + } + + /* Open timer resource */ + GPTimerCC26XX_Params_init(¶msUnion.timerParams); + paramsUnion.timerParams.width = GPT_CONFIG_16BIT; + paramsUnion.timerParams.mode = GPT_MODE_PERIODIC_UP; + paramsUnion.timerParams.debugStallMode = GPTimerCC26XX_DEBUG_STALL_OFF; + /* Open position 0 of the GPT config table - by convention this is timer 0A. */ + object->timerHandle = GPTimerCC26XX_open(0, ¶msUnion.timerParams); + + if (object->timerHandle == NULL) { + /* We did not manage to open the GPTimer we wanted */ + return NULL; + } + + adcPeriodCounts = ADCBufCC26XX_freqToCounts(params->samplingFrequency); + GPTimerCC26XX_setLoadValue(object->timerHandle, adcPeriodCounts); + + GPTimerCC26XX_enableInterrupt(object->timerHandle, GPT_INT_TIMEOUT); + + if (params->returnMode == ADCBuf_RETURN_MODE_BLOCKING) { + /* Continuous trigger mode and blocking return mode is an illegal combination */ + DebugP_assert(!(params->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS)); + + /* Create a semaphore to block task execution for the duration of the ADC conversions */ + SemaphoreP_constructBinary(&(object->conversionComplete), 0); + + /* Store internal callback function */ + object->callbackFxn = ADCBufCC26XX_conversionCallback; + } + else { + /* Callback mode without a callback function defined */ + DebugP_assert(params->callbackFxn); + + /* Save the callback function pointer */ + object->callbackFxn = params->callbackFxn; + } + + /* Create the Hwi for this ADC peripheral. */ + HwiP_Params_init(¶msUnion.hwiParams); + paramsUnion.hwiParams.arg = (uintptr_t) handle; + paramsUnion.hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), INT_AUX_ADC_IRQ, ADCBufCC26XX_hwiFxn, ¶msUnion.hwiParams); + + /* Create the Swi object for this ADC peripheral */ + SwiP_Params_init(¶msUnion.swiParams); + paramsUnion.swiParams.arg0 = (uintptr_t)handle; + paramsUnion.swiParams.priority = hwAttrs->swiPriority; + SwiP_construct(&(object->swi), ADCBufCC26XX_swiFxn, &(paramsUnion.swiParams)); + + + + /* Declare the dependency on the UDMA driver */ + object->udmaHandle = UDMACC26XX_open(); + + /* Return the handle after finishing initialisation of the driver */ + DebugP_log0("ADC: opened"); + return handle; + +} + + +/*! + * @brief HWI ISR of the ADC triggered when the DMA transaction is complete + * + * @param arg An ADCBufCC26XX_Handle + * + */ +static void ADCBufCC26XX_hwiFxn (uintptr_t arg) { + ADCBufCC26XX_Object *object; + ADCBuf_Conversion *conversion; + uint32_t intStatus; + + /* Get the pointer to the object and current conversion*/ + object = ((ADCBuf_Handle)arg)->object; + conversion = object->currentConversion; + + /* Set activeSampleBuffer to primary as default */ + object->activeSampleBuffer = conversion->sampleBuffer; + + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) { + /* Disable the ADC */ + AUXADCDisable(); + /* Disable ADC DMA if we are only doing one conversion and clear DMA done interrupt. */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_DMACTL) = AUX_EVCTL_DMACTL_REQ_MODE_SINGLE | AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY ; + } + else if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS) { + /* Reload the finished DMA control table entry */ + if (HWREG(UDMA0_BASE + UDMA_O_SETCHNLPRIALT) & (1 << UDMA_CHAN_AUX_ADC)) { + /* We are currently using the alternate entry -> we just finished the primary entry -> reload primary entry */ + ADCBufCC26XX_loadDMAControlTableEntry((ADCBuf_Handle)arg, conversion, true); + ADCBufCC26XX_loadGPTDMAControlTableEntry((ADCBuf_Handle)arg, conversion, true); + } + else { + /* We are currently using the primary entry -> we just finished the alternate entry -> reload the alternate entry */ + ADCBufCC26XX_loadDMAControlTableEntry((ADCBuf_Handle)arg, conversion, false); + ADCBufCC26XX_loadGPTDMAControlTableEntry((ADCBuf_Handle)arg, conversion, false); + object->activeSampleBuffer = conversion->sampleBufferTwo; + } + } + /* Clear DMA interrupts */ + UDMACC26XX_clearInterrupt(object->udmaHandle, (1 << UDMA_CHAN_AUX_ADC) | (1 << UDMA_CHAN_TIMER0_A)); + + /* Get the status of the ADC_IRQ line and ADC_DONE */ + intStatus = HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGS) & (AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ | AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE); + /* Clear the ADC_IRQ flag if it triggered the ISR */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = intStatus; + + /* Post SWI to handle remaining clean up and invocation of callback */ + SwiP_post(&(object->swi)); +} + +/*! + * @brief SWI ISR of the ADC triggered when the DMA transaction is complete + * + * @param arg0 An ADCBufCC26XX_Handle + * + */ +static void ADCBufCC26XX_swiFxn (uintptr_t arg0, uintptr_t arg1) { + uint32_t key; + ADCBuf_Conversion *conversion; + ADCBufCC26XX_Object *object; + uint16_t *sampleBuffer; + uint8_t channel; + + /* Get the pointer to the object */ + object = ((ADCBuf_Handle)arg0)->object; + + DebugP_log0("ADC: swi interrupt context start"); + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Use a temporary pointers in case the callback function + * attempts to perform another ADCBuf_transfer call + */ + conversion = object->currentConversion; + sampleBuffer = object->activeSampleBuffer; + channel = object->currentChannel; + + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) { + /* Clean up ADC and DMA */ + ADCBufCC26XX_cleanADC(((ADCBuf_Handle)arg0)); + /* Indicate we are done with this transfer */ + object->currentConversion = NULL; + } + + /* Restore interrupts */ + HwiP_restore(key); + + /* Perform callback */ + object->callbackFxn((ADCBuf_Handle)arg0, conversion, sampleBuffer, channel); + + DebugP_log0("ADC: swi interrupt context end"); +} + +/*! + * @brief CC26XX internal callback function that posts the semaphore in blocking mode + * + * @param handle An ADCBufCC26XX_Handle + * + * @param conversion A pointer to the current ADCBuf_Conversion + * + */ +static void ADCBufCC26XX_conversionCallback(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, void *completedADCBuffer, uint32_t completedChannel) { + ADCBufCC26XX_Object *object; + + DebugP_log0("ADC DMA: posting conversionComplete semaphore"); + + /* Get the pointer to the object */ + object = handle->object; + + /* Post the semaphore */ + SemaphoreP_post(&(object->conversionComplete)); +} + +/* + * ======== ADCBufCC26XX_convert ======== + */ +int_fast16_t ADCBufCC26XX_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount) { + uint32_t key; + ADCBufCC26XX_Object *object; + ADCBufCC26XX_HWAttrs const *hwAttrs; + PIN_Config adcPinTable[2]; + uint8_t i = 0; + + DebugP_assert(handle); + + /* Get the pointer to the object */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + DebugP_assert(channelCount == 1); + DebugP_assert((conversions->samplesRequestedCount <= UDMA_XFER_SIZE_MAX)); + DebugP_assert(conversions->sampleBuffer); + DebugP_assert(!(object->recurrenceMode == (ADCBuf_RECURRENCE_MODE_CONTINUOUS && !(conversions->sampleBufferTwo)))); + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Check if ADC is open and that no other transfer is in progress */ + if (!(object->isOpen) || object->conversionInProgress) { + /* Restore interrupts */ + HwiP_restore(key); + DebugP_log0("ADCBuf: conversion failed"); + return ADCBuf_STATUS_ERROR; + } + object->conversionInProgress = true; + + /* Restore interrupts*/ + HwiP_restore(key); + + /* Specify input in ADC module */ + AUXADCSelectInput(hwAttrs->adcChannelLut[conversions->adcChannel].compBInput); + + /* Add pin to measure on */ + adcPinTable[i++] = (hwAttrs->adcChannelLut[conversions->adcChannel].dio) | + PIN_NOPULL | + PIN_INPUT_DIS | + PIN_GPIO_OUTPUT_DIS | + PIN_IRQ_DIS | + PIN_DRVSTR_MIN; + + /* Terminate pin list */ + adcPinTable[i] = PIN_TERMINATE; + object->pinHandle = PIN_open(&object->pinState, adcPinTable); + if (!object->pinHandle) { + object->conversionInProgress = false; + return ADCBuf_STATUS_ERROR; + } + + /* Save which channel we are converting on for the callbackFxn */ + object->currentChannel = conversions->adcChannel; + + /* Try to acquire the ADC semaphore if we do not already have it. */ + if (object->adcSemaphoreInPossession == false) { + if (!AUXSMPHTryAcquire(AUX_SMPH_2)) { + PIN_close(object->pinHandle); + object->conversionInProgress = false; + DebugP_log0("ADCBuf: failed to acquire semaphore"); + return ADCBuf_STATUS_ERROR; + } + object->adcSemaphoreInPossession = true; + } + + /* Store location of the current conversion */ + object->currentConversion = conversions; + + /* Configure and arm the DMA and AUX DMA control */ + ADCBufCC26XX_configDMA(handle, conversions); + + /* Configure and arm the GPT DMA channel to clear the level-based GPT IRQ signal */ + ADCBufCC26XX_configGPTDMA(handle, conversions); + + /* Flush the ADC FIFO in case we have triggered prior to this call */ + AUXADCFlushFifo(); + + /* If input scaling is set to disabled in the params, disable it */ + if (!object->inputScalingEnabled) { + AUXADCDisableInputScaling(); + } + + /* Arm the ADC in preparation for incoming conversion triggers */ + if (object->samplingMode == ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS) { + /* ADCBufCC26XX_SYNCHRONOUS sampling mode */ + AUXADCEnableSync(object->refSource, object->samplingDuration, AUXADC_TRIGGER_GPT0A); + } + else { + /* ADCBufCC26XX_ASYNCHRONOUS sampling mode */ + AUXADCEnableAsync(object->refSource, AUXADC_TRIGGER_GPT0A); + } + + /* Start the GPTimer to create ADC triggers */ + GPTimerCC26XX_start(object->timerHandle); + + /* Set constraints to guarantee operation */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (object->returnMode == ADCBuf_RETURN_MODE_BLOCKING) { + DebugP_log0("ADCBuf: transfer pending on conversionComplete " + "semaphore"); + + if (SemaphoreP_OK != SemaphoreP_pend(&(object->conversionComplete), + object->semaphoreTimeout)) { + /* Cancel the transfer if we experience a timeout */ + ADCBufCC26XX_convertCancel(handle); + /* + * ADCBufCC26XX_convertCancel peforms a callback which posts a + * conversionComplete semaphore. This call consumes this extra post. + */ + SemaphoreP_pend(&(object->conversionComplete), SemaphoreP_NO_WAIT); + return ADCBuf_STATUS_ERROR; + } + } + + + return ADCBuf_STATUS_SUCCESS; +} + + +/* + * ======== ADCBufCC26XX_convertCancel ======== + */ +int_fast16_t ADCBufCC26XX_convertCancel(ADCBuf_Handle handle) { + ADCBufCC26XX_Object *object; + ADCBuf_Conversion *conversion; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs*/ + object = handle->object; + + /* Check if ADC is open and that no other transfer is in progress */ + if (!(object->conversionInProgress)) { + DebugP_log0("ADCBuf: a conversion must be in progress to cancel one"); + return ADCBuf_STATUS_ERROR; + } + + /* Stop triggering a conversion on trigger events */ + AUXADCDisable(); + + /* Set hardware and software configuration to default and turn off driver */ + ADCBufCC26XX_cleanADC(handle); + + /* Use a temporary transaction pointer in case the callback function + * attempts to perform another ADCBuf_convert call + */ + conversion = object->currentConversion; + + /* Perform callback if we are in one-shot mode. In continuous mode, ADCBuf_convertCancel will probably be called from the callback functon itself. No need to call it again. */ + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) { + object->callbackFxn(handle, conversion, conversion->sampleBuffer, object->currentChannel); + } + + return ADCBuf_STATUS_SUCCESS; +} + + +/* + * ======== ADCBufCC26XX_close ======== + */ +void ADCBufCC26XX_close(ADCBuf_Handle handle) { + ADCBufCC26XX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object */ + object = handle->object; + + /* Check if the ADC is running and abort conversion if necessary. */ + if (object->conversionInProgress) { + ADCBuf_convertCancel(handle); + } + + /* Get the pointer to the object */ + object = handle->object; + + /* Release the uDMA dependency and potentially power down uDMA. */ + UDMACC26XX_close(object->udmaHandle); + + /* Destroy the Hwi */ + HwiP_destruct(&(object->hwi)); + + /* Destroy the Swi */ + SwiP_destruct(&(object->swi)); + + /* Close the timer */ + GPTimerCC26XX_close(object->timerHandle); + + if (object->returnMode == ADCBuf_RETURN_MODE_BLOCKING) { + SemaphoreP_destruct(&(object->conversionComplete)); + } + + /* Mark the module as available */ + object->isOpen = false; + + DebugP_log0("ADCBuf: closed"); +} + +/* + * ======== ADCBufCC26XX_getResolution ======== + */ +uint_fast8_t ADCBufCC26XX_getResolution(ADCBuf_Handle handle) { + return (ADCBufCC26XX_RESOLUTION); +} + + +/* + * ======== ADCBufCC26XX_adjustRawValues ======== + */ +int_fast16_t ADCBufCC26XX_adjustRawValues(ADCBuf_Handle handle, void *sampleBuffer, uint_fast16_t sampleCount, uint32_t adcChannel) { + ADCBufCC26XX_Object *object; + uint32_t gain; + uint32_t offset; + uint16_t i; + + object = handle->object; + + gain = AUXADCGetAdjustmentGain(object->refSource); + offset = AUXADCGetAdjustmentOffset(object->refSource); + + for (i = 0; i < sampleCount; i++) { + uint16_t tmpRawADCVal = ((uint16_t *)sampleBuffer)[i]; + ((uint16_t *)sampleBuffer)[i] = AUXADCAdjustValueForGainAndOffset(tmpRawADCVal, gain, offset); + } + + return ADCBuf_STATUS_SUCCESS; +} + +/* + * ======== ADCBufCC26XX_convertAdjustedToMicroVolts ======== + */ +int_fast16_t ADCBufCC26XX_convertAdjustedToMicroVolts(ADCBuf_Handle handle, uint32_t adcChannel, void *adjustedSampleBuffer, uint32_t outputMicroVoltBuffer[], uint_fast16_t sampleCount) { + ADCBufCC26XX_Object *object; + uint16_t i; + uint32_t voltageRef; + + object = handle->object; + + voltageRef = (object->inputScalingEnabled) ? AUXADC_FIXED_REF_VOLTAGE_NORMAL : AUXADC_FIXED_REF_VOLTAGE_UNSCALED; + + for (i = 0; i < sampleCount; i++) { + outputMicroVoltBuffer[i] = AUXADCValueToMicrovolts(voltageRef, ((uint16_t *)adjustedSampleBuffer)[i]); + } + + return ADCBuf_STATUS_SUCCESS; +} + +/*! + * @brief Function to configure the DMA to automatically transfer ADC output data into a provided array + * + * @pre ADCBufCC26XX_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + * @param conversion A pointer to an ADCBuf_Conversion + * + */ +static void ADCBufCC26XX_configDMA(ADCBuf_Handle handle, ADCBuf_Conversion *conversion) { + ADCBufCC26XX_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Set configure control table entry */ + ADCBufCC26XX_loadDMAControlTableEntry(handle, conversion, true); + + /* If we are operating in continous mode, load the alternate DMA control table data structure */ + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS) { + ADCBufCC26XX_loadDMAControlTableEntry(handle, conversion, false); + } + + /* Enable the channels */ + UDMACC26XX_channelEnable(object->udmaHandle, 1 << UDMA_CHAN_AUX_ADC); + + /* Configure DMA settings in AUX_EVCTL */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_DMACTL) = AUX_EVCTL_DMACTL_REQ_MODE_SINGLE | AUX_EVCTL_DMACTL_EN | AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY; + + DebugP_log0("ADCBuf: DMA transfer enabled"); +} + +/*! + * @brief Function to configure the adc DMA control table entry for basic or ping pong mode + * + * @pre ADCBufCC26XX_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + * @param conversion A pointer to an ADCBuf_Conversion + * + * @param primaryEntry Is this supposed to modify the primary or the alternate control table entry + * + */ +static void ADCBufCC26XX_loadDMAControlTableEntry(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, bool primaryEntry) { + ADCBufCC26XX_Object *object; + volatile tDMAControlTable *dmaControlTableEntry; + uint32_t numberOfBytes; + + /* Get the pointer to the object*/ + object = handle->object; + + /* Calculate the number of bytes for the transfer */ + numberOfBytes = (uint16_t)(conversion->samplesRequestedCount) * ADCBufCC26XX_BYTES_PER_SAMPLE; + + /* Set configure control table entry */ + dmaControlTableEntry = primaryEntry ? &dmaADCPriControlTableEntry : &dmaADCAltControlTableEntry; + dmaControlTableEntry->ui32Control = ((object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) ? UDMA_MODE_BASIC : UDMA_MODE_PINGPONG) | + UDMA_SIZE_16 | + UDMA_SRC_INC_NONE | + UDMA_DST_INC_16 | + UDMA_ARB_1 | + UDMACC26XX_SET_TRANSFER_SIZE((uint16_t)conversion->samplesRequestedCount); + dmaControlTableEntry->pvDstEndAddr = (void *)((uint32_t)(primaryEntry ? conversion->sampleBuffer : conversion->sampleBufferTwo) + numberOfBytes - 1); + dmaControlTableEntry->pvSrcEndAddr = (void *)(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +/*! + * @brief Function to configure the DMA to automatically clear the GPT_IRQ line that the ADC triggers off of without using an interrupt handler + * + * @pre ADCBufCC26XX_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + * @param conversion A pointer to an ADCBuf_Conversion + * + */ +static void ADCBufCC26XX_configGPTDMA(ADCBuf_Handle handle, ADCBuf_Conversion *conversion) { + ADCBufCC26XX_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Set configure control table entry */ + ADCBufCC26XX_loadGPTDMAControlTableEntry(handle, conversion, true); + + /* If we are operating in continous mode, load the alternate DMA control table data structure */ + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS) { + ADCBufCC26XX_loadGPTDMAControlTableEntry(handle, conversion, false); + } + + /* Enable the channels */ + UDMACC26XX_channelEnable(object->udmaHandle, 1 << UDMA_CHAN_TIMER0_A); + + /* Enable event signal */ + HWREG(object->timerHandle->hwAttrs->baseAddr + GPT_O_DMAEV) = GPT_DMAEV_TATODMAEN; + +} + +/*! + * @brief Function to configure the GPT DMA control table entry for basic or ping pong mode + * + * @pre ADCBufCC26XX_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + * @param conversion A pointer to an ADCBuf_Conversion + * + * @param primaryEntry Is this supposed to modify the primary or the alternate control table entry + * + */ +static void ADCBufCC26XX_loadGPTDMAControlTableEntry(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, bool primaryEntry) { + ADCBufCC26XX_Object *object; + volatile tDMAControlTable *dmaControlTableEntry; + + /* Get the pointer to the object */ + object = handle->object; + + /* Set configure control table entry */ + dmaControlTableEntry = primaryEntry ? &dmaGPT0APriControlTableEntry : &dmaGPT0AAltControlTableEntry; + dmaControlTableEntry->ui32Control = ((object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) ? UDMA_MODE_BASIC : UDMA_MODE_PINGPONG) | + UDMA_SIZE_8 | + UDMA_SRC_INC_NONE | + UDMA_DST_INC_NONE | + UDMA_ARB_1 | + UDMACC26XX_SET_TRANSFER_SIZE((uint16_t)conversion->samplesRequestedCount); + dmaControlTableEntry->pvDstEndAddr = (void *)((uint32_t)(object->timerHandle->hwAttrs->baseAddr + GPT_O_ICLR)); + dmaControlTableEntry->pvSrcEndAddr = (void *)(&gptClear); +} + +/*! + * @brief Function to undo all configurations done by the ADC driver + * + * @pre ADCBuf_open() has to be called first. + * + * @pre ADCBuf_convert() has to be called first. + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + */ +static void ADCBufCC26XX_cleanADC(ADCBuf_Handle handle) { + ADCBufCC26XX_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Stop the timer to stop generating triggers */ + GPTimerCC26XX_stop(object->timerHandle); + + /* Set constraints to guarantee operation */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (object->adcSemaphoreInPossession && !object->keepADCSemaphore) { + /* Release the ADC semaphore */ + AUXSMPHRelease(AUX_SMPH_2); + object->adcSemaphoreInPossession = false; + } + + /* Disable the UDMA channels */ + UDMACC26XX_channelDisable(object->udmaHandle, (1 << UDMA_CHAN_AUX_ADC) | (1 << UDMA_CHAN_TIMER0_A)); + + /* Deallocate pins */ + PIN_close(object->pinHandle); + + /* Disable UDMA mode for ADC */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_DMACTL) = AUX_EVCTL_DMACTL_REQ_MODE_SINGLE | AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY ; + + /* Clear any remaining GPT_IRQ flags */ + HWREG(object->timerHandle->hwAttrs->baseAddr + GPT_O_ICLR) = GPT_ICLR_DMAAINT + GPT_ICLR_TATOCINT; + + /* Note that the driver is no longer converting */ + object->conversionInProgress = false; +} + +/* Return period in timer counts */ +static uint32_t ADCBufCC26XX_freqToCounts(uint32_t frequency) +{ + ClockP_FreqHz freq; + ClockP_getCpuFreq(&freq); + + uint32_t periodCounts = (freq.lo / frequency) - 1; + + return periodCounts; +} + +/*! + * @brief Function to acquire the semaphore that arbitrates access to the ADC + * between the CM3 and the sensor controller + * + * @pre ADCBufCC26XX_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + */ +static bool ADCBufCC26XX_acquireADCSemaphore(ADCBuf_Handle handle) { + uint32_t key; + bool semaphoreAvailable; + ADCBufCC26XX_Object *object; + + object = handle->object; + + /* Set semaphoreAvailable false at default */ + semaphoreAvailable = false; + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Check if ADC is closed or a conversion is in progress */ + if (!(object->isOpen) || object->conversionInProgress) { + DebugP_log0("ADC: driver must be open and no conversion must be in progress to disable input scaling"); + } + /* This is a non-blocking call to acquire the ADC semaphore. */ + else if (AUXSMPHTryAcquire(AUX_SMPH_2)) { + object->adcSemaphoreInPossession = true; + semaphoreAvailable = true; + } + + /* Restore interrupts */ + HwiP_restore(key); + + return semaphoreAvailable; +} + +/*! + * @brief This function releases the ADC semaphore + * + * @pre ADCBufCC26XX_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + */ +static bool ADCBufCC26XX_releaseADCSemaphore(ADCBuf_Handle handle) { + uint32_t key; + bool semaphoreReleased; + ADCBufCC26XX_Object *object; + + object= handle->object; + + /* Set semaphoreReleased true at default */ + semaphoreReleased = true; + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Check if ADC is closed or a conversion is in progress */ + if (!(object->isOpen) || object->conversionInProgress) { + DebugP_log0("ADC: driver must be open and no conversion must be in progress to disable input scaling"); + semaphoreReleased = false; + } + else { + /* Release the ADC semaphore */ + AUXSMPHRelease(AUX_SMPH_2); + object->adcSemaphoreInPossession = false; + } + + /* Restore interrupts */ + HwiP_restore(key); + + return semaphoreReleased; +} + +/* + * ======== ADCBufCC26XX_control ======== + */ +int_fast16_t ADCBufCC26XX_control(ADCBuf_Handle handle, uint_fast16_t cmd, void * arg) { + ADCBufCC26XX_Object *object = handle->object; + int status = ADCBuf_STATUS_ERROR; + + DebugP_assert(handle); + + switch (cmd) { + case ADCBufCC26XX_CMD_ACQUIRE_ADC_SEMAPHORE: + if (ADCBufCC26XX_acquireADCSemaphore(handle)) { + status = ADCBuf_STATUS_SUCCESS; + } + break; + case ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE: + object->keepADCSemaphore = true; + status = ADCBuf_STATUS_SUCCESS; + break; + case ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE_DISABLE: + object->keepADCSemaphore = false; + status = ADCBuf_STATUS_SUCCESS; + break; + case ADCBufCC26XX_CMD_RELEASE_ADC_SEMAPHORE: + if (ADCBufCC26XX_releaseADCSemaphore(handle)) { + status = ADCBuf_STATUS_SUCCESS; + } + break; + default: + status = ADCBuf_STATUS_UNDEFINEDCMD; + break; + } + return status; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26XX.h new file mode 100644 index 0000000..81a789b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26XX.h @@ -0,0 +1,596 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ADCBufCC26XX.h + * + * @brief ADCBuf driver implementation for a CC26XX analog-to-digital converter + * + * # Driver include # + * The ADCBuf header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * # Overview # + * This is a CC26XX specific implementation of the generic TI-RTOS ADCBuf driver. + * The generic ADCBuf API specified in ti/drivers/ADCBuf.h should be called by the application, + * not the device specific implementation in ti/drivers/adcbuf/ADCBufCC26XX. + * The board file defines the device specific configuration and casting in the general + * API ensures the correct device specific functions are called. You should specify an + * ADCBufCC26XX_ParamsExtension in the custom field of the ADCBuf_Params that suits + * your application. The default settings work for many, but not all, usecases. + * + * # General Behavior # + * A timer and the DMA are used to trigger the ADC and fill a buffer in the background (in hardware) at a specified frequency. + * The application may execute other tasks while the hardware handles the conversions. + * In contrast to the standard ti/drivers/ADC driver, this driver allows for precise sampling of waveforms. + * + * | Driver | Number of samples needed in one call | + * |----------------|-----------------------------------------| + * | ADC.h | 1 | + * | ADCBuf.h | > 1 | + * + * This ADCBuf driver provides an API interface to using the analog-to-digital converter + * directly from the CM3 without going through the sensor controller. + * The sensor controller can still use the ADC, support for sharing the ADC resource between the + * sensor controller and the CM3 is built into the driver. There is a hardware semaphore that the + * driver must acquire before beginning any number of conversions. This same hardware semaphore also + * prevents the simultaneous use of this driver and the basic ADC driver. + * + * The ADC drivers supports making between one and 1024 measurements once or continuous + * measuring with returned buffer sizes between one and 1024 measurements. + * + * The application should call ADCBuf_init() once by the application to set the isOpened + * flag to false, indicating that the driver is ready to use. + * + * The ADC driver is opened by calling ADCBuf_open() which will + * set up interrupts and configure the internal components of the driver. + * However, the ADC hardware or analog pins are not yet configured, since the sensor + * controller or basic ADC driver might be using the ADC. + * + * In order to perform an ADC conversion, the application should call + * ADCBuf_convert(). This call will request the ADC resource, configure the ADC, set up the DMA and GPTimer, + * and perform the requested ADC conversions on the selected DIO or internal signal. The DIO or internal signal is defined by the + * ADCBuf_Conversion structure in the application code and adcBufCC26xxObjects in the board file. + * + * @warning If the ADCBUF driver is setup in ADCBuf_RECURRENCE_MODE_CONTINUOUS mode, the user must assure that the provided callback + * function is completed before the next conversion completes. If the next conversion completes before the callback function finishes, + * the DMA will clobber the previous buffer with new data. + * + * If the sensor controller is using the ADC when the driver requests it at the start of the ADC_convert() call, + * the conversion will fail and return false. + * The ADC resource may be pre-acquired by calling the control function ADCBufCC26XX_CMD_ACQUIRE_ADC_SEMAPHORE. + * It will be released again automatically after the next conversion completes. + * + * In both ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS mode and ADCBufCC26XX_SAMPING_MODE_ASYNCHRONOUS mode, enough sampling + * time must be provided between conversions that each measurement may be completed before the next trigger arrives. + * + * @note The ADCBuf driver requires GPTimer0A to function correctly. It expects it to be configured as position 0 in the GPTimer Config Table. + * GPTimer0A will be unavailable for other uses. + * + * # Supported ADC pins # + * Below is a table of the supported ADC IO pins for each package size, for both CC26xx and CC13xx. + * It maps a DIO to its corresponding driverlib define for the CompBInput that it is hardwired to. + * This table can be used to create virtual channel entries in the ADCBufCC26XX_adcChannelLut table in the board file. + * + * | DIO | CC26xx 7x7 AUXIO CompBInput | CC13xx 7x7 AUXIO CompBInput | CC26xx 5x5 AUXIO CompBInput | CC13xx 5x5 AUXIO CompBInput | CC26xx 4x4 AUXIO CompBInput | CC13xx 4x4 AUXIO CompBInput + * |--------|-------------------------------|-------------------------------|-------------------------------|-------------------------------|-------------------------------|----------------------------- + * | 0 | No | No | No | No | No | No + * | 1 | No | No | No | No | No | No + * | 2 | No | No | No | No | No | No + * | 3 | No | No | No | No | No | No + * | 4 | No | No | No | No | No | No + * | 5 | No | No | No | No | ADC_COMPB_IN_AUXIO7 | ADC_COMPB_IN_AUXIO7 + * | 6 | No | No | No | No | ADC_COMPB_IN_AUXIO6 | ADC_COMPB_IN_AUXIO6 + * | 7 | No | No | ADC_COMPB_IN_AUXIO7 | ADC_COMPB_IN_AUXIO7 | ADC_COMPB_IN_AUXIO5 | ADC_COMPB_IN_AUXIO5 + * | 8 | No | No | ADC_COMPB_IN_AUXIO6 | ADC_COMPB_IN_AUXIO6 | ADC_COMPB_IN_AUXIO4 | ADC_COMPB_IN_AUXIO4 + * | 9 | No | No | ADC_COMPB_IN_AUXIO4 | ADC_COMPB_IN_AUXIO4 | ADC_COMPB_IN_AUXIO3 | ADC_COMPB_IN_AUXIO3 + * | 10 | No | No | ADC_COMPB_IN_AUXIO5 | ADC_COMPB_IN_AUXIO5 | No | No + * | 11 | No | No | ADC_COMPB_IN_AUXIO3 | ADC_COMPB_IN_AUXIO3 | No | No + * | 12 | No | No | ADC_COMPB_IN_AUXIO2 | ADC_COMPB_IN_AUXIO2 | No | No + * | 13 | No | No | ADC_COMPB_IN_AUXIO1 | ADC_COMPB_IN_AUXIO1 | No | No + * | 14 | No | No | ADC_COMPB_IN_AUXIO0 | ADC_COMPB_IN_AUXIO0 | No | No + * | 15-22 | No | No | No | No | No | No + * | 23 | ADC_COMPB_IN_AUXIO7 | ADC_COMPB_IN_AUXIO7 | No | No | No | No + * | 24 | ADC_COMPB_IN_AUXIO6 | ADC_COMPB_IN_AUXIO6 | No | No | No | No + * | 25 | ADC_COMPB_IN_AUXIO5 | ADC_COMPB_IN_AUXIO5 | No | No | No | No + * | 26 | ADC_COMPB_IN_AUXIO4 | ADC_COMPB_IN_AUXIO4 | No | No | No | No + * | 27 | ADC_COMPB_IN_AUXIO3 | ADC_COMPB_IN_AUXIO3 | No | No | No | No + * | 28 | ADC_COMPB_IN_AUXIO2 | ADC_COMPB_IN_AUXIO2 | No | No | No | No + * | 29 | ADC_COMPB_IN_AUXIO1 | ADC_COMPB_IN_AUXIO1 | No | No | No | No + * | 30 | ADC_COMPB_IN_AUXIO0 | ADC_COMPB_IN_AUXIO0 | No | No | No | No + * + * # Supported Internal Signals # + * Below is a table of internal signals that can be measured using the ADC. + * Since we are not connecting to a DIO, there is no DIO to internal signal mapping. The DIO field in the channel lookup table should be marked PIN_UNASSIGNED. + * This table can be used to create virtual channel entries in the ADCBufCC26XX_adcChannelLut table in the board file. + * + * | DIO | Internal Signal CompBInput | + * |--------------------|-------------------------------| + * | PIN_UNASSIGNED | ADC_COMPB_IN_DCOUPL | + * | PIN_UNASSIGNED | ADC_COMPB_IN_VSS | + * | PIN_UNASSIGNED | ADC_COMPB_IN_VDDS | + * + * # Error handling # + * The following errors may occur when opening the ADC without assertions enabled: + * - The ADC handle is already open. + * + * The following errors may occur when requesting an ADC conversion: + * - The ADC is currently already doing a conversion. + * - The ADC was not available (used by sensor controller or basic ADC). + * + * + * # Power Management # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * While converting, the ADCBufCC26XX driver sets a power constraint to keep + * the device out of standby. When the conversion has finished, the power + * constraint is released. The driver also sets a dependency on the DMA to enable + * background transfers from the ADC FIFO to memory and to clear the GPTimer interrupt. + * The following statements are valid: + * - After ADCBuf_convert(): the device cannot enter standby. + * - After ADCBuf_convertCancel(): the device can enter standby again. + * - After a conversion finishes: the device can enter standby again. + * + * + * # Supported Functions # + * | API function | Description | + * |------------------------------------|-----------------------------------------------------------------------| + * | ADCBuf_init() | Initialize ADC driver | + * | ADCBuf_open() | Open the ADC driver and configure driver | + * | ADCBuf_convert() | Perform ADC conversion | + * | ADCBuf_convertCancel() | Cancel ongoing ADC conversion | + * | ADCBuf_close() | Close ADC driver | + * | ADCBuf_Params_init() | Initialise ADCBuf_Params structure to default values | + * | ADCBuf_getResolution() | Get the resolution of the ADC of the current device | + * | ADCBuf_adjustRawValues() | Adjust the values in a returned buffer for manufacturing tolerances | + * | ADCBuf_convertAdjustedToMicroVolts | Convert a buffer of adjusted values to microvolts | + * | ADCBuf_control() | Execute device specific functions | + * + * + * # Not Supported Functionality # + * - Performing conversions on multiple channels simultaneously is not supported. + * In other words, the parameter channelCount must always be set to 1 when calling ADCBuf_convert(). + * The ADC on CC26XX devices does not support time-division multiplexing of channels or pins in hardware. + * + * # Use Cases # + * ## Basic one-shot conversion # + * Perform one conversion on Board_ADCCHANNEL_A1 in ::ADCBuf_RETURN_MODE_BLOCKING. + * @code + * #include + * + * #define ADCBUFFERSIZE 100 + * + * ADCBuf_Handle adcBufHandle; + * ADCBuf_Params adcBufParams; + * ADCBuf_Conversion blockingConversion; + * uint16_t sampleBufferOne[ADCBUFFERSIZE]; + * + * ADCBuf_Params_init(&adcBufParams); + * adcBufHandle = ADCBuf_open(Board_ADCBuf0, &adcBufParams); + * if (adcBufHandle == NULL) { + * // handle error + * } + * + * blockingConversion.arg = NULL; + * blockingConversion.adcChannel = Board_ADCCHANNEL_A1; + * blockingConversion.sampleBuffer = sampleBufferOne; + * blockingConversion.sampleBufferTwo = NULL; + * blockingConversion.samplesRequestedCount = ADCBUFFERSIZE; + * + * if (ADCBuf_convert(adcBufHandle, &blockingConversion, 1) != ADCBuf_STATUS_SUCCESS) { + * // handle error + * } + * @endcode + * + * ## Using ADCBufCC26XX_ParamsExtension # + * This specific configuration performs one conversion on Board_ADCCHANNEL_A1 in ::ADCBuf_RETURN_MODE_BLOCKING. + * The custom parameters used here are identical to the defaults parameters. + * Users can of course define their own parameters. + * @code + * #include + * + * #define ADCBUFFERSIZE 100 + * + * ADCBuf_Handle adcBufHandle; + * ADCBuf_Params adcBufParams; + * ADCBuf_Conversion blockingConversion; + * uint16_t sampleBufferOne[ADCBUFFERSIZE]; + * ADCBufCC26XX_ParamsExtension customParams; + * + * ADCBuf_Params_init(&adcBufParams); + * customParams.samplingDuration = ADCBufCC26XX_SAMPLING_DURATION_2P7_US; + * customParams.refSource = ADCBufCC26XX_FIXED_REFERENCE; + * customParams.samplingMode = ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS; + * customParams.inputScalingEnabled = true; + * + * adcBufParams.custom = &customParams; + * + * adcBufHandle = ADCBuf_open(Board_ADCBuf0, &adcBufParams); + * if (adcBufHandle == NULL) { + * // handle error + * } + * + * blockingConversion.arg = NULL; + * blockingConversion.adcChannel = Board_ADCCHANNEL_A1; + * blockingConversion.sampleBuffer = sampleBufferOne; + * blockingConversion.sampleBufferTwo = NULL; + * blockingConversion.samplesRequestedCount = ADCBUFFERSIZE; + * + * if (ADCBuf_convert(adcBufHandle, &blockingConversion, 1) != ADCBuf_STATUS_SUCCESS) { + * // handle error + * } + * @endcode + * + * # Instrumentation # + * The ADC driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic ADCBuf operations performed | + * Diags_USER2 | detailed ADCBuf operations performed | + * + ****************************************************************************** + */ + +#ifndef ti_drivers_adc_adcbufcc26xx__include +#define ti_drivers_adc_adcbufcc26xx__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aux_adc.h) + +#include +#include +#include +#include + +/** @}*/ + +/** + * @addtogroup ADCBuf_CMD + * ADCBufCC26XX_CMD_* macros are command codes only defined in the ADCBufCC26XX.h + * driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add ADCBufCC26XX_CMD_* macros here */ + +/*! + * @brief This control function acquires the semaphore that arbitrates access to the ADC + * between the CM3 and the sensor controller + * + * This function pre-acquires the ADC semaphore before ADCBuf_convert() is called by the application. + * Normally, the ADC driver acquires the ADC semaphore when calling ADCBufCC26XX_convert(). + * The driver may need to wait for the sensor controller to release the semaphore in order to + * access the ADC hardware module. Consequently, the time at which the conversion is actually + * made is normally non-deterministic. + * Pre-acquiring the semaphore makes the ADCBuf_convert() call deterministic. + * + * @note This function returns an error if the handle is not open or a transfer is in progress + */ +#define ADCBufCC26XX_CMD_ACQUIRE_ADC_SEMAPHORE ADCBuf_CMD_RESERVED + 1 + +/*! + * @brief This function makes the ADC driver keep the ADC semaphore until released + * + * Calling this function will make the ADC driver keep the ADC semaphore until it is released by + * the application by calling the control function ADCBufCC26XX_CMD_RELEASE_ADC_SEMAPHORE. + * This enables multiple deterministic conversions to be made. + * Usually, the driver will release the semaphore after the conversion finishes. + * + * @warning The sensor controller can no longer access the ADC until the semaphore is released by + * the application manually. + * + * @sa ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE_DISABLE + */ +#define ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE ADCBuf_CMD_RESERVED + 2 + +/*! + * @brief This function makes the ADC driver no longer keep the ADC semaphore until released + * + * This function effectively reverses a call to ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE_DISABLE. + * + * @sa ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE + */ +#define ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE_DISABLE ADCBuf_CMD_RESERVED + 3 + +/*! + * @brief This function releases the ADC semaphore + * + * @note This function returns an error if the handle is not open or a transfer is in progress + */ +#define ADCBufCC26XX_CMD_RELEASE_ADC_SEMAPHORE ADCBuf_CMD_RESERVED + 4 + +/** @}*/ + +/*! + * @brief Resolution in bits of the CC26XX ADC + */ +#define ADCBufCC26XX_RESOLUTION 12 + +#define ADCBufCC26XX_BYTES_PER_SAMPLE 2 + +/* + * ============================================================================= + * Constants + * ============================================================================= + */ + +/* ADCBuf function table pointer */ +extern const ADCBuf_FxnTable ADCBufCC26XX_fxnTable; + + +/* + * ============================================================================= + * Enumerations + * ============================================================================= + */ + +/*! + * @brief Specifies whether the internal reference of the ADC is sourced from the battery voltage or a fixed internal source. + * + * The CC26XX ADC can operate in two different ways with regards to the sampling phase of the ADC conversion process: + * - It can spend a fixed amount of time sampling the signal after getting the start conversion trigger. + * - It can constantly keep sampling and immediately start the conversion process after getting the trigger. + * + * In ADCBufCC26XX_SYNCHRONOUS mode, the ADC goes into IDLE in between conversions and uses less power. + * The minimum sample time for full precision in ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS is dependent on the input load. + */ +typedef enum ADCBufCC26XX_Sampling_Mode { + ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS, + ADCBufCC26XX_SAMPING_MODE_ASYNCHRONOUS +} ADCBufCC26XX_Sampling_Mode; + +/*! + * @brief Amount of time the ADC spends sampling the analogue input. + * + * The analogue to digital conversion process consists of two phases in the CC26XX ADC, + * the sampling and conversion phases. During the sampling phase, the ADC samples the + * analogue input signal. Larger input loads require longer sample times for the most accurate + * results. In ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS mode, this enum specifies the sampling times available. + */ +typedef enum ADCBufCC26XX_Sampling_Duration { + ADCBufCC26XX_SAMPLING_DURATION_2P7_US = AUXADC_SAMPLE_TIME_2P7_US, + ADCBufCC26XX_SAMPLING_DURATION_5P3_US = AUXADC_SAMPLE_TIME_5P3_US, + ADCBufCC26XX_SAMPLING_DURATION_10P6_US = AUXADC_SAMPLE_TIME_10P6_US, + ADCBufCC26XX_SAMPLING_DURATION_21P3_US = AUXADC_SAMPLE_TIME_21P3_US, + ADCBufCC26XX_SAMPLING_DURATION_42P6_US = AUXADC_SAMPLE_TIME_42P6_US, + ADCBufCC26XX_SAMPLING_DURATION_85P3_US = AUXADC_SAMPLE_TIME_85P3_US, + ADCBufCC26XX_SAMPLING_DURATION_170_US = AUXADC_SAMPLE_TIME_170_US, + ADCBufCC26XX_SAMPLING_DURATION_341_US = AUXADC_SAMPLE_TIME_341_US, + ADCBufCC26XX_SAMPLING_DURATION_682_US = AUXADC_SAMPLE_TIME_682_US, + ADCBufCC26XX_SAMPLING_DURATION_1P37_MS = AUXADC_SAMPLE_TIME_1P37_MS, + ADCBufCC26XX_SAMPLING_DURATION_2P73_MS = AUXADC_SAMPLE_TIME_2P73_MS, + ADCBufCC26XX_SAMPLING_DURATION_5P46_MS = AUXADC_SAMPLE_TIME_5P46_MS, + ADCBufCC26XX_SAMPLING_DURATION_10P9_MS = AUXADC_SAMPLE_TIME_10P9_MS +} ADCBufCC26XX_Sampling_Duration; + + +/*! + * @brief Specifies whether the internal reference of the ADC is sourced from the battery voltage or a fixed internal source. + * + * - In practice, using the internal fixed voltage reference sets the upper range of the ADC to a fixed value. That value is 4.3V with + * input scaling enabled and ~1.4785V with input scaling disabled. In this mode, the output is a function of the input voltage multiplied + * by the resolution in alternatives (not bits) divided by the upper voltage range of the ADC. Output = Input (V) * 2^12 / (ADC range (V)) + * + * - Using VDDS as a reference scales the upper range of the ADC with the battery voltage. As the battery depletes and its voltage drops, so does + * the range of the ADC. This is helpful when measuring signals that are generated relative to the battery voltage. In this mode, the output is + * a function of the input voltage multiplied by the resolution in alternatives (not bits) divided by VDDS multiplied by a scaling factor derived + * from the input scaling. Output = Input (V) * 2^12 / (VDDS (V) * Scaling factor), where the scaling factor is ~1.4785/4.3 for input scaling + * disabled and 1 for input scaling enabled. + * + * @note The actual reference values are slightly different for each device and are higher than the values specified above. This gain is saved in + * the FCFG. The function ADCBuf_convertRawToMicroVolts() must be used to derive actual voltage values. Do not attempt to compare raw values + * between devices or derive a voltage from them yourself. The results of doing so will only be approximately correct. + * + * @warning Even though the upper voltage range of the ADC is 4.3 volts in fixed mode with input scaling enabled, the input should never exceed + * VDDS as per the data sheet. + */ +typedef enum ADCBufCC26XX_Reference_Source { + ADCBufCC26XX_FIXED_REFERENCE = AUXADC_REF_FIXED, + ADCBufCC26XX_VDDS_REFERENCE = AUXADC_REF_VDDS_REL +} ADCBufCC26XX_Reference_Source; + + + +/* + * ============================================================================= + * Structs + * ============================================================================= + */ + + /*! + * @brief Table entry that maps a virtual adc channel to a dio and its corresponding internal analogue signal + * + * Non-dio signals can be used as well. To do this, compBInput is set to the driverlib define corresponding to the + * desired non-dio signal and dio is set to PIN_UNASSIGNED. + */ +typedef struct ADCBufCC26XX_AdcChannelLutEntry{ + uint8_t dio; /*!< DIO that this virtual channel is mapped to */ + uint8_t compBInput; /*!< CompBInput that this virtual channel is mapped to */ +} ADCBufCC26XX_AdcChannelLutEntry; + +/*! + * @brief CC26XX specfic extension to ADCBuf_Params + * + * To use non-default CC26XX specific parameters when calling ADCBuf_open(), a pointer + * to an instance of this struct must be specified in ADCBuf_Params::custom. Alternatively, + * these values can be set using the control function after calling ADCBuf_open(). + */ +typedef struct ADCBufCC26XX_ParamsExtension{ + /*! Amount of time the ADC spends sampling the analogue input */ + ADCBufCC26XX_Sampling_Duration samplingDuration; + /*! Specifies whether the ADC spends a fixed amount of time sampling or the entire time since the last conversion */ + ADCBufCC26XX_Sampling_Mode samplingMode; + /*! Specifies whether the internal reference of the ADC is sourced from the battery voltage or a fixed internal source */ + ADCBufCC26XX_Reference_Source refSource; + /*! + * Disable input scaling. Input scaling scales an external analogue + * signal between 0 and 4.3V to an internal signal of 0 to ~1.4785V. + * Since the largest permissible input to any pin is VDDS, the maximum + * range of the ADC is effectively less than 3.8V and continues to shrink + * as the battery voltage drops. + * With input scaling disabled, the external analogue signal is passed + * on directly to the internal electronics. Signals larger than ~1.4785V + * will damage the device with input scaling disabled. + * + * | Input scaling status | Maximum permissible ADC input voltage | + * |---------------------------|---------------------------------------| + * | Enabled | VDDS (Battery voltage level) | + * | Disabled | 1.4785V | + */ + bool inputScalingEnabled; +} ADCBufCC26XX_ParamsExtension; + +/*! + * @brief ADCBufCC26XX Hardware Attributes + * + * These fields are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC26xxWare these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * A sample structure is shown below: + * @code + * const ADCBufCC26XX_HWAttrs ADCBufCC26XXHWAttrs[] = { + * { + * .intPriority = ~0, + * .swiPriority = 0, + * .gpTimerUnit = CC2650_GPTIMER0A, + * .gptDMAChannelMask = 1 << UDMA_CHAN_TIMER0_A, + * } + * }; + * @endcode + */ +typedef struct ADCBufCC26XX_HWAttrs{ + /*! @brief ADC SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! @brief ADC peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! Pointer to a table of ADCBufCC26XX_AdcChannelLutEntry's mapping internal CompBInput to DIO */ + ADCBufCC26XX_AdcChannelLutEntry const *adcChannelLut; +} ADCBufCC26XX_HWAttrs; + + + +/*! + * @brief ADCBufCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct ADCBufCC26XX_Object{ + /* ADC control variables */ + bool isOpen; /*!< Has the obj been opened */ + bool conversionInProgress; /*!< Is the ADC currently doing conversions */ + bool inputScalingEnabled; /*!< Is the analogue input scaled */ + bool keepADCSemaphore; /*!< Should the driver keep the ADC semaphore after a conversion */ + bool adcSemaphoreInPossession; /*!< Does the driver currently possess the ADC semaphore */ + uint8_t currentChannel; /*!< The current virtual channel the ADCBuf driver is sampling on */ + ADCBufCC26XX_Reference_Source refSource; /*!< Reference source for the ADC to use */ + ADCBufCC26XX_Sampling_Mode samplingMode; /*!< Synchronous or asynchronous sampling mode */ + ADCBufCC26XX_Sampling_Duration samplingDuration; /*!< Time the ADC spends sampling in ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS */ + ADCBuf_Callback callbackFxn; /*!< Pointer to callback function */ + ADCBuf_Recurrence_Mode recurrenceMode; /*!< Should we convert continuously or one-shot */ + ADCBuf_Return_Mode returnMode; /*!< Mode for all conversions */ + uint16_t *activeSampleBuffer; /*!< The last complete sample buffer used by the DMA */ + + /* ADC SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object */ + SwiP_Struct swi; /*!< Swi object */ + SemaphoreP_Struct conversionComplete; /*!< ADC semaphore */ + + ADCBuf_Conversion *currentConversion; /*!< Pointer to the current conversion struct */ + + /* PIN driver state object and handle */ + PIN_State pinState; /*!< Pin state object */ + PIN_Handle pinHandle; /*!< Pin handle */ + + /* UDMA driver handle */ + UDMACC26XX_Handle udmaHandle; /*!< UDMA handle */ + + /* GPTimer driver handle */ + GPTimerCC26XX_Handle timerHandle; /*!< Handle to underlying GPTimer peripheral */ + + uint32_t semaphoreTimeout; /*!< Timeout for read semaphore in ::ADCBuf_RETURN_MODE_BLOCKING */ + uint32_t samplingFrequency; /*!< Frequency in Hz at which the ADC is triggered */ +} ADCBufCC26XX_Object, *ADCBufCC26XX_Handle; + +/* + * ============================================================================= + * Functions + * ============================================================================= + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_adc_ADCBufCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aescbc/AESCBCCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aescbc/AESCBCCC26XX.c new file mode 100644 index 0000000..cf23dca --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aescbc/AESCBCCC26XX.c @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) + +/* Forward declarations */ +static void AESCBC_hwiFxn (uintptr_t arg0); +static int_fast16_t AESCBC_startOperation(AESCBC_Handle handle, + AESCBC_Operation *operation, + AESCBC_OperationType operationType); +static int_fast16_t AESCBC_waitForResult(AESCBC_Handle handle); +static void AESCBC_cleanup(AESCBC_Handle handle); + +/* Extern globals */ +extern const AESCBC_Config AESCBC_config[]; +extern const uint_least8_t AESCBC_count; + +/* Static globals */ +static bool isInitialized = false; + +/* + * ======== AESCBC_hwiFxn ======== + */ +static void AESCBC_hwiFxn (uintptr_t arg0) { + AESCBCCC26XX_Object *object = ((AESCBC_Handle)arg0)->object; + uint32_t key; + + key = HwiP_disable(); + if (!object->operationCanceled) { + + /* Mark that we are done with the operation so that AESCBC_cancelOperation + * knows not to try canceling. + */ + object->operationInProgress = false; + + HwiP_restore(key); + } + else { + HwiP_restore(key); + return; + } + + /* Propagate the DMA error from driverlib to the application */ + if (AESIntStatusRaw() & AES_DMA_BUS_ERR) { + object->returnStatus = AESCBC_STATUS_ERROR; + } + + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + /* Handle cleaning up of the operation. Invalidate the key, + * release the Power constraints, and post the access semaphore. + */ + AESCBC_cleanup((AESCBC_Handle)arg0); + + if (object->returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING) { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else { + /* Call the callback function provided by the application. + */ + object->callbackFxn((AESCBC_Handle)arg0, + object->returnStatus, + object->operation, + object->operationType); + } + +} + +/* + * ======== AESCBC_cleanup ======== + */ +static void AESCBC_cleanup(AESCBC_Handle handle) { + + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides small + * power savings. + */ + AESSelectAlgorithm(0x00); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); +} + +/* + * ======== AESCBC_init ======== + */ +void AESCBC_init(void) { + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== AESCBC_open ======== + */ +AESCBC_Handle AESCBC_open(uint_least8_t index, AESCBC_Params *params) { + AESCBC_Handle handle; + AESCBCCC26XX_Object *object; + uint_fast8_t key; + + handle = (AESCBC_Handle)&(AESCBC_config[index]); + object = handle->object; + + DebugP_assert(index < AESCBC_count); + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* If params are NULL, use defaults */ + if (params == NULL) { + params = (AESCBC_Params *)&AESCBC_defaultParams; + } + + /* This is currently not supported. */ + DebugP_assert(!params->nonceInternallyGenerated); + DebugP_assert(params->returnBehavior == AESCBC_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + object->semaphoreTimeout = params->returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING ? params->timeout : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for Crypto (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== AESCBC_close ======== + */ +void AESCBC_close(AESCBC_Handle handle) { + AESCBCCC26XX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on Crypto Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); + +} + +/* + * ======== AESCBC_startOperation ======== + */ +static int_fast16_t AESCBC_startOperation(AESCBC_Handle handle, + AESCBC_Operation *operation, + AESCBC_OperationType operationType) { + AESCBCCC26XX_Object *object = handle->object; + AESCBCCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + SemaphoreP_Status resourceAcquired; + + /* Only plaintext CryptoKeys are supported for now */ + uint16_t keyLength = operation->key->u.plaintext.keyLength; + uint8_t *keyingMaterial = operation->key->u.plaintext.keyMaterial; + + DebugP_assert(handle); + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, + object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) { + return AESCBC_STATUS_RESOURCE_UNAVAILABLE; + } + + object->operationType = operationType; + object->operation = operation; + /* We will only change the returnStatus if there is an error */ + object->returnStatus = AESCBC_STATUS_SUCCESS; + object->operationCanceled = false; + + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESCBC_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* Load the key from RAM or flash into the key store at a hardcoded and reserved location */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) { + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + return AESCBC_STATUS_ERROR; + } + + + /* If we are in AESCBC_RETURN_BEHAVIOR_POLLING, we do not want an interrupt to trigger. + * AESWriteToKeyStore() disables and then re-enables the CRYPTO IRQ in the NVIC so we + * need to disable it before kicking off the operation. + */ + if (object->returnBehavior == AESCBC_RETURN_BEHAVIOR_POLLING) { + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* Load the key from the key store into the internal register banks of the AES sub-module */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) { + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + return AESCBC_STATUS_ERROR; + } + + /* Disallow standby. We are about to configure and start the accelerator. + * Setting the constraint should happen after all opportunities to fail out of the + * function. This way, we do not need to undo it each time we exit with a failure. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + AESSetInitializationVector((uint32_t *)operation->iv); + + AESSetCtrl(CRYPTO_AESCTL_CBC | + (operationType == AESCBC_OPERATION_TYPE_ENCRYPT ? CRYPTO_AESCTL_DIR : 0)); + + AESSetDataLength(operation->inputLength); + AESSetAuthLength(0); + + AESStartDMAOperation(operation->input, operation->inputLength, operation->output, operation->inputLength); + + return AESCBC_waitForResult(handle); +} + +/* + * ======== AESCBC_waitForResult ======== + */ +static int_fast16_t AESCBC_waitForResult(AESCBC_Handle handle){ + AESCBCCC26XX_Object *object = handle->object; + + object->operationInProgress = true; + + if (object->returnBehavior == AESCBC_RETURN_BEHAVIOR_POLLING) { + /* Wait until the operation is complete and check for DMA errors. */ + if(AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR){ + object->returnStatus = AESCBC_STATUS_ERROR; + } + + /* Mark that we are done with the operation */ + object->operationInProgress = false; + + /* Make sure to also clear DMA_IN_DONE as it is not cleared above + * but will be set none-the-less. + */ + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + /* Instead of posting the swi to handle cleanup, we will execute + * the core of the function here + */ + AESCBC_cleanup(handle); + + return object->returnStatus; + } + else if (object->returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING) { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + return object->returnStatus; + } + else { + return AESCBC_STATUS_SUCCESS; + } +} + +/* + * ======== AESCBC_oneStepEncrypt ======== + */ +int_fast16_t AESCBC_oneStepEncrypt(AESCBC_Handle handle, AESCBC_Operation *operationStruct) { + + return AESCBC_startOperation(handle, operationStruct, AESCBC_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESCBC_oneStepDecrypt ======== + */ +int_fast16_t AESCBC_oneStepDecrypt(AESCBC_Handle handle, AESCBC_Operation *operationStruct) { + + return AESCBC_startOperation(handle, operationStruct, AESCBC_OPERATION_TYPE_DECRYPT); +} + +/* + * ======== AESCBC_cancelOperation ======== + */ +int_fast16_t AESCBC_cancelOperation(AESCBC_Handle handle) { + AESCBCCC26XX_Object *object = handle->object; + uint32_t key; + + key = HwiP_disable(); + + if (!object->operationInProgress) { + HwiP_restore(key); + return AESCBC_STATUS_ERROR; + } + + /* Reset the accelerator. Immediately stops ongoing operations. */ + AESReset(); + + /* Consume any outstanding interrupts we may have accrued + * since disabling interrupts. + */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->operationCanceled = true; + object->returnStatus = AESCBC_STATUS_CANCELED; + + HwiP_restore(key); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + if (object->returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING) { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, + AESCBC_STATUS_CANCELED, + object->operation, + object->operationType); + } + + return AESCBC_STATUS_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aescbc/AESCBCCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aescbc/AESCBCCC26XX.h new file mode 100644 index 0000000..351e057 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aescbc/AESCBCCC26XX.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESCBCCC26XX.h + * + * @brief AESCBC driver implementation for the CC26XX family + * + * @warning This is a beta API. It may change in future releases. + * + * This file should only be included in the board file to fill the AESCBC_config + * struct. + * + * # Hardware Accelerator # + * The CC26XX family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation including CBC. Only one operation + * can be carried out on the accelerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted to ensure + * sensible access timeouts are set. + * + * # Key Store # + * The CC26XX crypto module contains a key store. The only way to load a key into + * the AES accelerator is to first load it into the key store. To guarantee availability + * of open key locations in the key store for AES operations, the last two key + * locations (6 and 7) are reserved for ad-hoc operations. The key is loaded into the + * key store, the AES operation is carried out, and the key is deleted from the key store. + * Since the key store does not have retention and the keys can not survive going into + * standby, the key store is only used to load keys into the AES accelerator rather + * than store keys. Support for pre-loading keys into the key store and using them + * in an AES operation is not supported in this driver. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * - This implementation does not support internal generation of IVs. + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aescbc_AESCBCCC26XX__include +#define ti_drivers_aescbc_AESCBCCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include + +#include + +/*! + * @brief AESCBCCC26XX Hardware Attributes + * + * AESCBC26XX hardware attributes should be included in the board file + * and pointed to by the AESCBC_config struct. + */ +typedef struct AESCBCCC26XX_HWAttrs { + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; +} AESCBCCC26XX_HWAttrs; + +/*! + * @brief AESCBCCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct AESCBCCC26XX_Object { + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t returnStatus; + AESCBC_ReturnBehavior returnBehavior; + AESCBC_OperationType operationType; + uint32_t semaphoreTimeout; + AESCBC_CallbackFxn callbackFxn; + AESCBC_Operation *operation; +} AESCBCCC26XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aescbc_AESCBCCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesccm/AESCCMCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesccm/AESCCMCC26XX.c new file mode 100644 index 0000000..ca6311f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesccm/AESCCMCC26XX.c @@ -0,0 +1,445 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/smph.h) + + +/* Forward declarations */ +static void AESCCM_hwiFxn (uintptr_t arg0); +static int_fast16_t AESCCM_startOperation(AESCCM_Handle handle, + AESCCM_Operation *operation, + AESCCM_OperationType operationType); +static int_fast16_t AESCCM_waitForResult(AESCCM_Handle handle); +static void AESCCM_cleanup(AESCCM_Handle handle); + +/* Extern globals */ +extern const AESCCM_Config AESCCM_config[]; +extern const uint_least8_t AESCCM_count; + +/* Static globals */ +static bool isInitialized = false; + +/* + * ======== AESCCM_hwiFxn ======== + */ +static void AESCCM_hwiFxn (uintptr_t arg0) { + AESCCMCC26XX_Object *object = ((AESCCM_Handle)arg0)->object; + uint32_t key; + + key = HwiP_disable(); + if (!object->operationCanceled) { + + /* Mark that we are done with the operation so that AESCCM_cancelOperation + * knows not to try canceling. + */ + object->operationInProgress = false; + + HwiP_restore(key); + } + else { + HwiP_restore(key); + return; + } + + /* Propagate the DMA error from driverlib to the application */ + if (AESIntStatusRaw() & AES_DMA_BUS_ERR) { + object->returnStatus = AESCCM_STATUS_ERROR; + } + + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + /* Handle cleaning up of the operation. Read out the tag + * or verify it against the provided one, invalidate the key, + * release the Power constraints, and post the access semaphore. + */ + AESCCM_cleanup((AESCCM_Handle)arg0); + + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else { + /* Call the callback function provided by the application. + */ + object->callbackFxn((AESCCM_Handle)arg0, + object->returnStatus, + object->operation, + object->operationType); + } +} + +static void AESCCM_cleanup(AESCCM_Handle handle) { + AESCCMCC26XX_Object *object = handle->object; + + /* We need to copy / verify the MAC now so that it is not clobbered when we + * release the CryptoResourceCC26XX_accessSemaphore semaphore. + */ + if (object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT) { + /* If we are encrypting and authenticating a message, we only want to + * copy the MAC to the target buffer + */ + AESReadTag(object->operation->mac, object->operation->macLength); + } + else { + /* If we are decrypting and verifying a message, we must now verify that the provided + * MAC matches the one calculated in the decryption operation. + */ + uint32_t verifyResult = AESVerifyTag(object->operation->mac, object->operation->macLength); + + object->returnStatus = (verifyResult == AES_SUCCESS) ? object->returnStatus : AESCCM_STATUS_MAC_INVALID; + } + + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides small + * power savings. + */ + AESSelectAlgorithm(0x00); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); +} + +/* + * ======== AESCCM_init ======== + */ +void AESCCM_init(void) { + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== AESCCM_open ======== + */ +AESCCM_Handle AESCCM_open(uint_least8_t index, AESCCM_Params *params) { + AESCCM_Handle handle; + AESCCMCC26XX_Object *object; + uint_fast8_t key; + + handle = (AESCCM_Handle)&(AESCCM_config[index]); + object = handle->object; + + DebugP_assert(index < AESCCM_count); + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* If params are NULL, use defaults */ + if (params == NULL) { + params = (AESCCM_Params *)&AESCCM_defaultParams; + } + + /* This is currently not supported. Eventually it will make the TRNG generate the nonce */ + DebugP_assert(!params->nonceInternallyGenerated); + DebugP_assert(params->returnBehavior == AESCCM_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + object->semaphoreTimeout = params->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING ? params->timeout : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for Crypto (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== AESCCM_close ======== + */ +void AESCCM_close(AESCCM_Handle handle) { + AESCCMCC26XX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on Crypto Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESCCM_startOperation ======== + */ +static int_fast16_t AESCCM_startOperation(AESCCM_Handle handle, + AESCCM_Operation *operation, + AESCCM_OperationType operationType) { + AESCCMCC26XX_Object *object = handle->object; + AESCCMCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + SemaphoreP_Status resourceAcquired; + + /* Only plaintext CryptoKeys are supported for now */ + uint16_t keyLength = operation->key->u.plaintext.keyLength; + uint8_t *keyingMaterial = operation->key->u.plaintext.keyMaterial; + + DebugP_assert(handle); + DebugP_assert(key); + DebugP_assert(nonce && (nonceLength >= 7 && nonceLength <= 13)); + DebugP_assert((aad && aadLength) || (input && inputLength)); + DebugP_assert(mac && (macLength <= 16)); + DebugP_assert(key->encoding == CryptoKey_PLAINTEXT); + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, + object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + + object->operationType = operationType; + object->operation = operation; + /* We will only change the returnStatus if there is an error */ + object->returnStatus = AESCCM_STATUS_SUCCESS; + object->operationCanceled = false; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESCCM_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* Load the key from RAM or flash into the key store at a hardcoded and reserved location */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) { + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + return AESCCM_STATUS_ERROR; + } + + /* If we are in AESCCM_RETURN_BEHAVIOR_POLLING, we do not want an interrupt to trigger. + * AESWriteToKeyStore() disables and then re-enables the CRYPTO IRQ in the NVIC so we + * need to disable it before kicking off the operation. + */ + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_POLLING) { + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* Load the key from the key store into the internal register banks of the AES sub-module */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) { + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + return AESCCM_STATUS_ERROR; + } + + /* Disallow standby. We are about to configure and start the accelerator. + * Setting the constraint should happen after all opportunities to fail out of the + * function. This way, we do not need to undo it each time we exit with a failure. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + AESWriteCCMInitializationVector(operation->nonce, operation->nonceLength); + + AESConfigureCCMCtrl(operation->nonceLength, operation->macLength, operationType == AESCCM_OPERATION_TYPE_ENCRYPT); + + AESSetDataLength(operation->inputLength); + AESSetAuthLength(operation->aadLength); + + if (operation->aadLength) { + /* If aadLength were 0, AESWaitForIRQFlags() would never return as the AES_DMA_IN_DONE flag + * would never trigger. + */ + AESStartDMAOperation(operation->aad, operation->aadLength, NULL, 0); + AESWaitForIRQFlags(AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + } + + AESStartDMAOperation(operation->input, operation->inputLength, operation->output, operation->inputLength); + + + return AESCCM_waitForResult(handle); +} + +/* + * ======== AESCCM_waitForResult ======== + */ +static int_fast16_t AESCCM_waitForResult(AESCCM_Handle handle) { + AESCCMCC26XX_Object *object = handle->object; + + object->operationInProgress = true; + + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_POLLING) { + /* Wait until the operation is complete and check for DMA errors. */ + if(AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR){ + object->returnStatus = AESCCM_STATUS_ERROR; + } + + /* Mark that we are done with the operation */ + object->operationInProgress = false; + + /* Make sure to also clear DMA_IN_DONE as it is not cleared above + * but will be set none-the-less. + */ + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + /* Instead of posting the swi to handle cleanup, we will execute + * the core of the function here */ + AESCCM_cleanup(handle); + + return object->returnStatus; + } + else if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + return object->returnStatus; + } + else { + return AESCCM_STATUS_SUCCESS; + } +} + +/* + * ======== AESCCM_oneStepEncrypt ======== + */ +int_fast16_t AESCCM_oneStepEncrypt(AESCCM_Handle handle, AESCCM_Operation *operationStruct) { + + return AESCCM_startOperation(handle, operationStruct, AESCCM_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESCCM_oneStepDecrypt ======== + */ +int_fast16_t AESCCM_oneStepDecrypt(AESCCM_Handle handle, AESCCM_Operation *operationStruct) { + + return AESCCM_startOperation(handle, operationStruct, AESCCM_OPERATION_TYPE_DECRYPT); +} + +/* + * ======== AESCCM_cancelOperation ======== + */ +int_fast16_t AESCCM_cancelOperation(AESCCM_Handle handle) { + AESCCMCC26XX_Object *object = handle->object; + uint32_t key; + + key = HwiP_disable(); + + if (!object->operationInProgress) { + HwiP_restore(key); + return AESCCM_STATUS_ERROR; + } + + /* Reset the accelerator. Immediately stops ongoing operations. */ + AESReset(); + + /* Consume any outstanding interrupts we may have accrued + * since disabling interrupts. + */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->operationCanceled = true; + object->returnStatus = AESCCM_STATUS_CANCELED; + + HwiP_restore(key); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, + AESCCM_STATUS_CANCELED, + object->operation, + object->operationType); + } + + return AESCCM_STATUS_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesccm/AESCCMCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesccm/AESCCMCC26XX.h new file mode 100644 index 0000000..2dbe174 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesccm/AESCCMCC26XX.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESCCMCC26XX.h + * + * @brief AESCCM driver implementation for the CC26XX family + * + * @warning This is a beta API. It may change in future releases. + * + * This file should only be included in the board file to fill the AESCCM_config + * struct. + * + * # Hardware Accelerator # + * The CC26XX family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation including CCM. Only one operation + * can be carried out on the accerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted to ensure that + * sensible access timeouts are set. + * + * # Key Store # + * The CC26XX crypto module contains a key store. The only way to load a key into + * the AES accelerator is to first load it into the key store. To guarantee availability + * of open key locations in the key store for AES operations, the last two key + * locations (6 and 7) are reserved for ad-hoc operations. The key is loaded into the + * key store, the AES operation is carried out, and the key is deleted from the key store. + * Since the key store does not have retention and the keys can not survive going into + * standby, the key store is only used to load keys into the AES accelerator rather + * than store keys. Support for pre-loading keys into the key store and using them + * in an AES operation is not supported in this driver. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * - This implementation does not support internal generation of IVs + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aesccm_AESCCMCC26XX__include +#define ti_drivers_aesccm_AESCCMCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include + +#include +#include +#include + +/*! + * @brief AESCCMCC26XX Hardware Attributes + * + * AESCCM26XX hardware attributes should be included in the board file + * and pointed to by the AESCCM_config struct. + */ +typedef struct AESCCMCC26XX_HWAttrs { + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; +} AESCCMCC26XX_HWAttrs; + +/*! + * @brief AESCCMCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct AESCCMCC26XX_Object { + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t returnStatus; + AESCCM_ReturnBehavior returnBehavior; + AESCCM_OperationType operationType; + uint32_t semaphoreTimeout; + AESCCM_CallbackFxn callbackFxn; + AESCCM_Operation *operation; +} AESCCMCC26XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesccm_AESCCMCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctr/AESCTRCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctr/AESCTRCC26XX.c new file mode 100644 index 0000000..9d7dd5a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctr/AESCTRCC26XX.c @@ -0,0 +1,445 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) + +/* Forward declarations */ +static void AESCTR_hwiFxn (uintptr_t arg0); +static int_fast16_t AESCTR_startOperation(AESCTR_Handle handle, + AESCTR_Operation *operation, + AESCTR_OperationType operationType); +static int_fast16_t AESCTR_waitForResult(AESCTR_Handle handle); +static void AESCTR_cleanup(AESCTR_Handle handle); + +/* Non-public functions required by other drivers */ +bool AESCTR_acquireLock(AESCTR_Handle handle); +void AESCTR_releaseLock(AESCTR_Handle handle); +void AESCTR_enableThreadSafety(AESCTR_Handle handle); +void AESCTR_disableThreadSafety(AESCTR_Handle handle); + +/* Extern globals */ +extern const AESCTR_Config AESCTR_config[]; +extern const uint_least8_t AESCTR_count; + +/* Static globals */ +static bool isInitialized = false; + +/* + * ======== AESCTR_hwiFxn ======== + */ +static void AESCTR_hwiFxn (uintptr_t arg0) { + AESCTRCC26XX_Object *object = ((AESCTR_Handle)arg0)->object; + uint32_t key; + + key = HwiP_disable(); + if (!object->operationCanceled) { + + /* Mark that we are done with the operation so that AESCTR_cancelOperation + * knows not to try canceling. + */ + object->operationInProgress = false; + + HwiP_restore(key); + } + else { + HwiP_restore(key); + return; + } + + /* Propagate the DMA error from driverlib to the application */ + if (AESIntStatusRaw() & AES_DMA_BUS_ERR) { + object->returnStatus = AESCTR_STATUS_ERROR; + } + + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + /* Handle cleaning up of the operation. Invalidate the key, + * release the Power constraints, and post the access semaphore. + */ + AESCTR_cleanup((AESCTR_Handle)arg0); + + if (object->returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING) { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else { + /* Call the callback function provided by the application. + */ + object->callbackFxn((AESCTR_Handle)arg0, + object->returnStatus, + object->operation, + object->operationType); + } + +} + +/* + * ======== AESCTR_cleanup ======== + */ +static void AESCTR_cleanup(AESCTR_Handle handle) { + AESCTRCC26XX_Object *object = handle->object; + + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides small + * power savings. + */ + AESSelectAlgorithm(0x00); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + if (object->threadSafe) { + CryptoResourceCC26XX_releaseLock(); + } +} + +/* + * ======== AESCTR_init ======== + */ +void AESCTR_init(void) { + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== AESCTR_open ======== + */ +AESCTR_Handle AESCTR_open(uint_least8_t index, const AESCTR_Params *params) { + AESCTR_Handle handle; + AESCTRCC26XX_Object *object; + uint_fast8_t key; + + handle = (AESCTR_Config*)&AESCTR_config[index]; + object = handle->object; + + DebugP_assert(index < AESCTR_count); + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* If params are NULL, use defaults */ + if (params == NULL) { + params = &AESCTR_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESCTR_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + object->semaphoreTimeout = params->returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING ? params->timeout : SemaphoreP_NO_WAIT; + object->threadSafe = true; + + /* Set power dependency - i.e. power up and enable clock for Crypto (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== AESCTR_close ======== + */ +void AESCTR_close(AESCTR_Handle handle) { + AESCTRCC26XX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on Crypto Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESCTR_startOperation ======== + */ +static int_fast16_t AESCTR_startOperation(AESCTR_Handle handle, + AESCTR_Operation *operation, + AESCTR_OperationType operationType) { + AESCTRCC26XX_Object *object = handle->object; + AESCTRCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + bool resourceAcquired; + + /* Only plaintext CryptoKeys are supported for now */ + uint16_t keyLength = operation->key->u.plaintext.keyLength; + uint8_t *keyingMaterial = operation->key->u.plaintext.keyMaterial; + + DebugP_assert(handle); + + if (object->threadSafe) { + /* Try and obtain access to the crypto module */ + resourceAcquired = CryptoResourceCC26XX_acquireLock(object->semaphoreTimeout); + + if (!resourceAcquired) { + return AESCTR_STATUS_RESOURCE_UNAVAILABLE; + } + } + + object->operationType = operationType; + object->operation = operation; + /* We will only change the returnStatus if there is an error */ + object->returnStatus = AESCTR_STATUS_SUCCESS; + object->operationCanceled = false; + + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESCTR_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* Disallow standby. We are about to configure and start the accelerator. + * Setting the constraint should happen after all opportunities to fail out of the + * function. This way, we do not need to undo it each time we exit with a failure. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Load the key from RAM or flash into the key store at a hardcoded and reserved location */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) { + /* Wipe keys, release STANDBY constraint, power off AES sub-module, + * and release acclerator lock + */ + AESCTR_cleanup(handle); + + return AESCTR_STATUS_ERROR; + } + + /* If we are in AESCTR_RETURN_BEHAVIOR_POLLING, we do not want an interrupt to trigger. + * AESWriteToKeyStore() disables and then re-enables the CRYPTO IRQ in the NVIC so we + * need to disable it before kicking off the operation. + */ + if (object->returnBehavior == AESCTR_RETURN_BEHAVIOR_POLLING) { + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* Load the key from the key store into the internal register banks of the AES sub-module */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) { + /* Wipe keys, release STANDBY constraint, power off AES sub-module, + * and release acclerator lock + */ + AESCTR_cleanup(handle); + + return AESCTR_STATUS_ERROR; + } + + if (operation->initialCounter) { + /* If an initial counter is provided, load it. */ + AESSetInitializationVector((uint32_t *)operation->initialCounter); + } + else { + /* Otherwise, use an initial counter of 0 */ + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = 0x00000000; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = 0x00000000; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = 0x00000000; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = 0x00000000; + } + + AESSetCtrl(CRYPTO_AESCTL_CTR | + CRYPTO_AESCTL_CTR_WIDTH_128_BIT | + (operationType == AESCTR_OPERATION_TYPE_ENCRYPT ? CRYPTO_AESCTL_DIR : 0)); + + AESSetDataLength(operation->inputLength); + AESSetAuthLength(0); + + AESStartDMAOperation(operation->input, operation->inputLength, operation->output, operation->inputLength); + + return AESCTR_waitForResult(handle); +} + +/* + * ======== AESCTR_waitForResult ======== + */ +static int_fast16_t AESCTR_waitForResult(AESCTR_Handle handle){ + AESCTRCC26XX_Object *object = handle->object; + + object->operationInProgress = true; + + if (object->returnBehavior == AESCTR_RETURN_BEHAVIOR_POLLING) { + /* Wait until the operation is complete and check for DMA errors. */ + if(AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR){ + object->returnStatus = AESCTR_STATUS_ERROR; + } + + /* Mark that we are done with the operation */ + object->operationInProgress = false; + + /* Make sure to also clear DMA_IN_DONE as it is not cleared above + * but will be set none-the-less. + */ + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + /* Instead of handling cleanup in the hwi, we will execute + * the core of the function here + */ + AESCTR_cleanup(handle); + + return object->returnStatus; + } + else if (object->returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING) { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + return object->returnStatus; + } + else { + return AESCTR_STATUS_SUCCESS; + } +} + +/* + * ======== AESCTR_oneStepEncrypt ======== + */ +int_fast16_t AESCTR_oneStepEncrypt(AESCTR_Handle handle, AESCTR_Operation *operationStruct) { + + return AESCTR_startOperation(handle, operationStruct, AESCTR_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESCTR_oneStepDecrypt ======== + */ +int_fast16_t AESCTR_oneStepDecrypt(AESCTR_Handle handle, AESCTR_Operation *operationStruct) { + + return AESCTR_startOperation(handle, operationStruct, AESCTR_OPERATION_TYPE_DECRYPT); +} + +/* + * ======== AESCTR_cancelOperation ======== + */ +int_fast16_t AESCTR_cancelOperation(AESCTR_Handle handle) { + AESCTRCC26XX_Object *object = handle->object; + uint32_t key; + + key = HwiP_disable(); + + if (!object->operationInProgress) { + HwiP_restore(key); + return AESCTR_STATUS_ERROR; + } + + /* Reset the accelerator. Immediately stops ongoing operations. */ + AESReset(); + + /* Consume any outstanding interrupts we may have accrued + * since disabling interrupts. + */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + object->operationCanceled = true; + object->returnStatus = AESCTR_STATUS_CANCELED; + + HwiP_restore(key); + + /* Wipe keys, release STANDBY constraint, power off AES sub-module, + * and release acclerator lock + */ + AESCTR_cleanup(handle); + + if (object->returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING) { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, + AESCTR_STATUS_CANCELED, + object->operation, + object->operationType); + } + + return AESCTR_STATUS_SUCCESS; +} + +bool AESCTR_acquireLock(AESCTR_Handle handle) { + AESCTRCC26XX_Object *object = handle->object; + + return CryptoResourceCC26XX_acquireLock(object->semaphoreTimeout); +} + +void AESCTR_releaseLock(AESCTR_Handle handle) { + CryptoResourceCC26XX_releaseLock(); +} + +void AESCTR_enableThreadSafety(AESCTR_Handle handle) { + AESCTRCC26XX_Object *object = handle->object; + + object->threadSafe = true; +} +void AESCTR_disableThreadSafety(AESCTR_Handle handle) { + AESCTRCC26XX_Object *object = handle->object; + + object->threadSafe = false; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctr/AESCTRCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctr/AESCTRCC26XX.h new file mode 100644 index 0000000..c8edaae --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctr/AESCTRCC26XX.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESCTRCC26XX.h + * + * @brief AESCTR driver implementation for the CC26XX family + * + * @warning This is a beta API. It may change in future releases. + * + * This file should only be included in the board file to fill the AESCTR_config + * struct. + * + * # Hardware Accelerator # + * The CC26XX family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation including CTR. Only one operation + * can be carried out on the accelerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted to ensure + * sensible access timeouts are set. + * + * # Key Store # + * The CC26XX crypto module contains a key store. The only way to load a key into + * the AES accelerator is to first load it into the key store. To guarantee availability + * of open key locations in the key store for AES operations, the last two key + * locations (6 and 7) are reserved for ad-hoc operations. The key is loaded into the + * key store, the AES operation is carried out, and the key is deleted from the key store. + * Since the key store does not have retention and the keys can not survive going into + * standby, the key store is only used to load keys into the AES accelerator rather + * than store keys. Support for pre-loading keys into the key store and using them + * in an AES operation is not supported in this driver. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aesctr_AESCTRCC26XX__include +#define ti_drivers_aesctr_AESCTRCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include + +/*! + * @brief AESCTRCC26XX Hardware Attributes + * + * AESCTR26XX hardware attributes should be included in the board file + * and pointed to by the AESCTR_config struct. + */ +typedef struct { + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; +} AESCTRCC26XX_HWAttrs; + +/*! + * @brief AESCTRCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct { + bool isOpen; + bool operationInProgress; + bool operationCanceled; + bool threadSafe; + int_fast16_t returnStatus; + AESCTR_ReturnBehavior returnBehavior; + AESCTR_OperationType operationType; + uint32_t semaphoreTimeout; + AESCTR_CallbackFxn callbackFxn; + AESCTR_Operation *operation; +} AESCTRCC26XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesctr_AESCTRCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.c new file mode 100644 index 0000000..c1ef2cf --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.c @@ -0,0 +1,398 @@ +/* + * Copyright (c) 2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +/* Forward declarations */ +void addBigendCounter(uint8_t *counter, uint32_t increment); +int_fast16_t updateState(AESCTRDRBG_Handle handle, + const void *additionalData, + size_t additionalDataLength); + +/* Extern functions */ + +/* These non-public functions are required to ensure thread-safe behavior + * across multiple calls. + */ +extern bool AESCTR_acquireLock(AESCTR_Handle handle); +extern void AESCTR_releaseLock(AESCTR_Handle handle); +extern void AESCTR_enableThreadSafety(AESCTR_Handle handle); +extern void AESCTR_disableThreadSafety(AESCTR_Handle handle); + +/* Extern globals */ +extern const AESCTRDRBG_Config AESCTRDRBG_config[]; +extern const uint_least8_t AESCTRDRBG_count; + +/* Static globals */ +static bool isInitialized = false; + +#define CEIL(x, y) (1 + (((x) - 1) / (y))) + +/* + * ======== AESCTRDRBG_init ======== + */ +void AESCTRDRBG_init(void) { + AESCTR_init(); + + isInitialized = true; +} + +/* + * ======== updateState ======== + */ +int_fast16_t updateState(AESCTRDRBG_Handle handle, const void *additionalData, size_t additionalDataLength) { + AESCTRDRBGXX_Object *object; + AESCTR_Operation operation; + uint8_t tmp[AESCTRDRBG_MAX_SEED_LENGTH] = {0}; + + object = handle->object; + + /* We need to increment the counter here since regular AESCTR + * only increments the counter after encrypting it while + * AESCTRDRBG increments the counter before encrypting it. + * We do not need to worry about the counter being 1 over afterwards + * as we will replace the global counter with part of the + * encrypted result. + */ + addBigendCounter(object->counter, 1); + + /* Copy over any additional data and operate on tmp in place. + * This way we can have the case where additionalDataLength < seedLength. + * This is useful in AESCTRDRBG_getBytes() to avoid allocating a spare + * empty buffer + */ + memcpy(tmp, + additionalData, + additionalDataLength); + + operation.key = &object->key; + operation.input = tmp; + operation.output = tmp; + operation.initialCounter = object->counter; + operation.inputLength = object->key.u.plaintext.keyLength + AESCTRDRBG_AES_BLOCK_SIZE_BYTES; + + if (AESCTR_oneStepEncrypt(object->ctrHandle, &operation) != AESCTR_STATUS_SUCCESS) { + return AESCTRDRBG_STATUS_ERROR; + } + + /* Copy the left most keyLength bytes of the computed result */ + memcpy(object->keyingMaterial, + tmp, + object->key.u.plaintext.keyLength); + + /* Copy new counter value as the right most 16 bytes of the + * computed result. + */ + memcpy(object->counter, + tmp + object->key.u.plaintext.keyLength, + AESCTRDRBG_AES_BLOCK_SIZE_BYTES); + + /* Wipe the stack buffer */ + memset(tmp, 0, object->seedLength); + + return AESCTRDRBG_STATUS_SUCCESS; +} + +/* + * ======== reverseBufferBytewise ======== + */ +static void reverseBufferBytewise(void * buffer, size_t bufferLength) { + uint8_t *bufferLow = buffer; + uint8_t *bufferHigh = bufferLow + bufferLength - 1; + uint8_t tmp; + + while (bufferLow < bufferHigh) { + tmp = *bufferLow; + *bufferLow = *bufferHigh; + *bufferHigh = tmp; + bufferLow++; + bufferHigh--; + } +} + +/* + * ======== addBigendCounter ======== + */ +void addBigendCounter(uint8_t *counter, uint32_t increment) { + uint64_t *counter64 = (uint64_t *)counter; + uint64_t prior; + + /* Turn it into a little-endian counter */ + reverseBufferBytewise(counter64, AESCTRDRBG_AES_BLOCK_SIZE_BYTES); + + prior = counter64[0]; + + /* Increment as a 64-bit number */ + counter64[0] += increment; + + /* Check if we wrapped and need to increment the upper 64 bits */ + if (counter64[0] < prior) { + counter64[1]++; + } + + /* Turn it back into a big-endian integer */ + reverseBufferBytewise(counter64, AESCTRDRBG_AES_BLOCK_SIZE_BYTES); +} + +/* + * ======== AESCTRDRBG_open ======== + */ +AESCTRDRBG_Handle AESCTRDRBG_open(uint_least8_t index, const AESCTRDRBG_Params *params) { + AESCTRDRBG_Handle handle; + AESCTRDRBGXX_Object *object; + const AESCTRDRBGXX_HWAttrs *hwAttrs; + AESCTR_Params ctrParams; + uintptr_t key; + int_fast16_t status; + + handle = (AESCTRDRBG_Handle)&(AESCTRDRBG_config[index]); + object = handle->object; + hwAttrs = handle->hwAttrs; + + DebugP_assert(index < AESCTRDRBG_count); + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* There are no valid default params for this driver */ + if (params == NULL) { + return NULL; + } + + /* personalizationDataLength must be within + * [0, AESCTRDRBG_AES_BLOCK_SIZE_BYTES] bytes. + */ + if (params->personalizationDataLength > + params->keyLength + AESCTRDRBG_AES_BLOCK_SIZE_BYTES) { + return NULL; + } + + /* Open the driver's AESCTR instance */ + AESCTR_Params_init(&ctrParams); + ctrParams.returnBehavior = (AESCTR_ReturnBehavior)(params->returnBehavior); + + object->ctrHandle = AESCTR_open(hwAttrs->aesctrIndex, &ctrParams); + + if (object->ctrHandle == NULL) { + object->isOpen = false; + + return NULL; + } + + /* Initialise CryptoKey for later use */ + CryptoKeyPlaintext_initKey(&object->key, object->keyingMaterial, params->keyLength); + + /* Zero-out counter and keyingMaterial */ + memset(object->counter, 0, AESCTRDRBG_AES_BLOCK_SIZE_BYTES); + memset(object->keyingMaterial, 0, params->keyLength); + + /* Store constants for later */ + object->seedLength = params->keyLength + AESCTRDRBG_AES_BLOCK_SIZE_BYTES; + object->reseedInterval = params->reseedInterval; + + /* Reseed the instance to generate the initial (counter, keyingMaterial) pair */ + status = AESCTRDRBG_reseed(handle, + params->seed, + params->personalizationData, + params->personalizationDataLength); + + if (status != AESCTRDRBG_STATUS_SUCCESS) { + AESCTR_close(object->ctrHandle); + object->isOpen = false; + + return NULL; + } + + return handle; +} + +/* + * ======== AESCTRDRBG_close ======== + */ +void AESCTRDRBG_close(AESCTRDRBG_Handle handle) { + AESCTRDRBGXX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + AESCTR_close(object->ctrHandle); + + memset(object->keyingMaterial, 0, object->key.u.plaintext.keyLength); + + /* Mark the module as available */ + object->isOpen = false; +} + +/* + * ======== AESCTRDRBG_getBytes ======== + */ +int_fast16_t AESCTRDRBG_getBytes(AESCTRDRBG_Handle handle, CryptoKey *randomBytes) { + AESCTRDRBGXX_Object *object; + AESCTR_Operation operation; + int_fast16_t status; + bool lockAcquired; + + object = handle->object; + + if (object->reseedCounter >= object->reseedInterval) { + return AESCTRDRBG_STATUS_RESEED_REQUIRED; + } + + lockAcquired = AESCTR_acquireLock(object->ctrHandle); + if (!lockAcquired) { + return AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE; + } + + AESCTR_disableThreadSafety(object->ctrHandle); + + /* Set the keying material of the CryptoKey to 0. + * If we use AESCTR to encrypt a buffer full of zeros, + * the resultant output will be the bitstream of the + * encrypted counters. That is what is used as + * random bits by AESCTRDRBG. + * Zeroing out the keying material and performing + * the AESCTR encryption in place saves us from + * allocating a buffer of the right length full + * of zeros or repeatedly encrypting a 16-byte + * buffer full of zeros. + */ + memset(randomBytes->u.plaintext.keyMaterial, 0, randomBytes->u.plaintext.keyLength); + + /* We need to increment the counter here since regular AESCTR + * only increments the counter after encrypting it while + * AESCTRDRBG increments the counter before encrypting it. + */ + addBigendCounter(object->counter, 1); + + operation.key = &object->key; + operation.input = randomBytes->u.plaintext.keyMaterial; + operation.output = randomBytes->u.plaintext.keyMaterial; + operation.initialCounter = object->counter; + operation.inputLength = randomBytes->u.plaintext.keyLength; + + status = AESCTR_oneStepEncrypt(object->ctrHandle, &operation); + + if (status != AESCTR_STATUS_SUCCESS) { + return AESCTRDRBG_STATUS_ERROR; + } + + /* Add the number of counter blocks we produced to the + * internal counter. We already incremented by one above + * so we increment by one less here. + */ + addBigendCounter(object->counter, + CEIL(randomBytes->u.plaintext.keyLength, AESCTRDRBG_AES_BLOCK_SIZE_BYTES) - 1); + + status = updateState(handle, NULL, 0); + + AESCTR_enableThreadSafety(object->ctrHandle); + AESCTR_releaseLock(object->ctrHandle); + + if (status != AESCTRDRBG_STATUS_SUCCESS) { + return status; + } + + object->reseedCounter += 1; + + return AESCTRDRBG_STATUS_SUCCESS; +} + +/* + * ======== AESCTRDRBG_reseed ======== + */ +int_fast16_t AESCTRDRBG_reseed(AESCTRDRBG_Handle handle, + const void *seed, + const void *additionalData, + size_t additionalDataLength) { + AESCTRDRBGXX_Object *object; + int_fast16_t status; + uint8_t tmp[AESCTRDRBG_MAX_SEED_LENGTH]; + uint32_t i; + bool lockAcquired; + + object = handle->object; + + if (additionalDataLength > object->seedLength) { + return AESCTRDRBG_STATUS_ERROR; + } + + lockAcquired = AESCTR_acquireLock(object->ctrHandle); + if (!lockAcquired) { + return AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE; + } + + AESCTR_disableThreadSafety(object->ctrHandle); + + /* Set temporary buffer as additionalData padded with zeros */ + memset(tmp, 0, object->seedLength); + memcpy(tmp, additionalData, additionalDataLength); + + /* XOR-in the seed. It should always be a multiple of 32 bits */ + for (i = 0; i < object->seedLength / sizeof(uint32_t); i++){ + ((uint32_t *)tmp)[i] ^= ((uint32_t *)seed)[i]; + } + + /* Use the combined seed to generate a new (counter, keyingMaterial) pair */ + status = updateState(handle, tmp, object->seedLength); + + AESCTR_enableThreadSafety(object->ctrHandle); + AESCTR_releaseLock(object->ctrHandle); + + if(status != AESCTRDRBG_STATUS_SUCCESS) { + return status; + } + + object->reseedCounter = 1; + + return AESCTRDRBG_STATUS_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h new file mode 100644 index 0000000..3632b32 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCTRDRBGXX.h + * + * @brief Generic AESCTRDRBG implementation based on the AESCTR driver + * + * @warning This is a beta API. It may change in future releases. + * + * This file should only be included in the board file to fill the AESCTR_config + * struct. + * + * # Use of AESCTR # + * This implementation uses the AESCTR driver to generate the random bitstream + * required to mutate the internal AESCTRDRBG state and provide random output + * bits. The driver will open an instance of the AESCTR driver based on the index + * specified in #AESCTRDRBGXX_HWAttrs:aesctrIndex. Mutual exclusion and hardware + * access are all handled by the AESCTR driver instance. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aesctrdrbg_AESCTRDRBGXX__include +#define ti_drivers_aesctrdrbg_AESCTRDRBGXX__include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @brief Define that specifies the maximum AES key length required + * + * This define defines what the largest AES key length used in an application is. + * Since this implementation needs to support all AES key lengths by default, + * temporary buffers and the internal driver state are sized to accomodate AES-256. + * If only AES-128 is used in an application, the driver can be recompiled + * with a different #AESCTRDRBG_MAX_KEY_LENGTH to save RAM in the #AESCTRDRBGXX_Object + * and reducing stack size requirements. + */ +#ifndef AESCTRDRBG_MAX_KEY_LENGTH + #define AESCTRDRBG_MAX_KEY_LENGTH AESCTRDRBG_AES_KEY_LENGTH_256 +#endif + +/*! @brief Define that specifies the maximum seed length used by the driver */ +#define AESCTRDRBG_MAX_SEED_LENGTH (AESCTRDRBG_MAX_KEY_LENGTH + AESCTRDRBG_AES_BLOCK_SIZE_BYTES) + +/*! + * @brief AESCTRDRBGXX Hardware Attributes + * + * AESCTR26XX hardware attributes should be included in the board file + * and pointed to by the AESCTR_config struct. + */ +typedef struct { + uint_least8_t aesctrIndex; /*! Index into AESCTR_config array */ +} AESCTRDRBGXX_HWAttrs; + +/*! + * @brief AESCTRDRBGXX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct { + uint8_t keyingMaterial[AESCTRDRBG_AES_KEY_LENGTH_256]; + uint8_t counter[AESCTRDRBG_AES_BLOCK_SIZE_BYTES]; + CryptoKey key; + AESCTR_Handle ctrHandle; + size_t seedLength; + uint32_t reseedCounter; + uint32_t reseedInterval; + int_fast16_t returnStatus; + bool isOpen; +} AESCTRDRBGXX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesctrdrbg_AESCTRDRBGXX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesecb/AESECBCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesecb/AESECBCC26XX.c new file mode 100644 index 0000000..3a68a6c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesecb/AESECBCC26XX.c @@ -0,0 +1,410 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/smph.h) + + +/* Forward declarations */ +static void AESECB_hwiFxn (uintptr_t arg0); +static int_fast16_t AESECB_waitForResult(AESECB_Handle handle); +static void AESECB_cleanup(AESECB_Handle handle); +static int_fast16_t AESECB_startOperation(AESECB_Handle handle, + AESECB_Operation *operation, + AESECB_OperationType operationType); + +/* Extern globals */ +extern const AESECB_Config AESECB_config[]; +extern const uint_least8_t AESECB_count; + +/* Static globals */ +static bool isInitialized = false; + +/* + * ======== AESECB_hwiFxn ======== + */ +static void AESECB_hwiFxn (uintptr_t arg0) { + AESECBCC26XX_Object *object = ((AESECB_Handle)arg0)->object; + uint32_t key; + + key = HwiP_disable(); + if (!object->operationCanceled) { + + /* Mark that we are done with the operation so that AESECB_cancelOperation + * knows not to try canceling. + */ + object->operationInProgress = false; + + HwiP_restore(key); + } + else { + HwiP_restore(key); + return; + } + + if (AESIntStatusRaw() & AES_DMA_BUS_ERR) { + object->returnStatus = AESECB_STATUS_ERROR; + } + + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + AESECB_cleanup((AESECB_Handle)arg0); + + if (object->returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING) { + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else { + object->callbackFxn((AESECB_Handle)arg0, + object->returnStatus, + object->operation, + object->operationType); + } +} + +/* + * ======== AESECB_cleanup ======== + */ +static void AESECB_cleanup(AESECB_Handle handle) { + + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides small + * power savings. + */ + AESSelectAlgorithm(0x00); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/* + * ======== AESECB_init ======== + */ +void AESECB_init(void) { + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== AESECB_open ======== + */ +AESECB_Handle AESECB_open(uint_least8_t index, AESECB_Params *params) { + AESECB_Handle handle; + AESECBCC26XX_Object *object; + uint_fast8_t key; + + handle = (AESECB_Handle)&(AESECB_config[index]); + object = handle->object; + + DebugP_assert(index < AESECB_count); + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* If params are NULL, use defaults */ + if (params == NULL) { + params = (AESECB_Params *)&AESECB_defaultParams; + } + + /* This is currently not supported. Eventually it will make the TRNG generate the nonce */ + DebugP_assert(!params->nonceInternallyGenerated); + DebugP_assert(params->returnBehavior == AESECB_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + object->semaphoreTimeout = params->returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING ? params->timeout : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for Crypto (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== AESECB_close ======== + */ +void AESECB_close(AESECB_Handle handle) { + AESECBCC26XX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on Crypto Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESECB_waitForResult ======== + */ +int_fast16_t AESECB_waitForResult(AESECB_Handle handle){ + AESECBCC26XX_Object *object = handle->object; + + object->operationInProgress = true; + + if (object->returnBehavior == AESECB_RETURN_BEHAVIOR_POLLING) { + /* Wait until the operation is complete and check for DMA errors. */ + if(AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR){ + object->returnStatus = AESECB_STATUS_ERROR; + } + + /* Mark that we are done with the operation */ + object->operationInProgress = false; + + /* Make sure to also clear DMA_IN_DONE as it is not cleared above + * but will be set none-the-less. + */ + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + /* Instead of posting the swi to handle cleanup, we will execute + * the core of the function here */ + AESECB_cleanup(handle); + + return object->returnStatus; + } + else if (object->returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING) { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + return object->returnStatus; + } + else { + return AESECB_STATUS_SUCCESS; + } +} + +/* + * ======== AESECB_startOperation ======== + */ +static int_fast16_t AESECB_startOperation(AESECB_Handle handle, + AESECB_Operation *operation, + AESECB_OperationType operationType) { + AESECBCC26XX_Object *object = handle->object; + AESECBCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + SemaphoreP_Status resourceAcquired; + + /* Only plaintext CryptoKeys are supported for now */ + uint16_t keyLength = operation->key->u.plaintext.keyLength; + uint8_t *keyingMaterial = operation->key->u.plaintext.keyMaterial; + + DebugP_assert(handle); + DebugP_assert(operation); + DebugP_assert(operationType == AESECB_OPERATION_TYPE_DECRYPT || + operationType == AESECB_OPERATION_TYPE_ENCRYPT); + DebugP_assert(keyingMaterial); + DebugP_assert(keyLength == 16 || + keyLength == 32); + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, + object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) { + return AESECB_STATUS_RESOURCE_UNAVAILABLE; + } + + object->operationType = operationType; + object->operation = operation; + /* We will only change the returnStatus if there is an error */ + object->returnStatus = AESECB_STATUS_SUCCESS; + object->operationCanceled = false; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESECB_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* Load the key from RAM or flash into the key store at a hardcoded and reserved location */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) { + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + return AESECB_STATUS_ERROR; + } + + /* If we are in AESECB_RETURN_BEHAVIOR_POLLING, we do not want an interrupt to trigger. + * AESWriteToKeyStore() disables and then re-enables the CRYPTO IRQ in the NVIC so we + * need to disable it before kicking off the operation. + */ + if (object->returnBehavior == AESECB_RETURN_BEHAVIOR_POLLING) { + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* Load the key from the key store into the internal register banks of the AES sub-module */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) { + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + return AESECB_STATUS_ERROR; + } + + /* Disallow standby. We are about to configure and start the accelerator. + * Setting the constraint should happen after all opportunities to fail out of the + * function. This way, we do not need to undo it each time we exit with a failure. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Set direction of operation. */ + AESSetCtrl(operationType == AESECB_OPERATION_TYPE_DECRYPT ? 0 : CRYPTO_AESCTL_DIR); + + AESSetDataLength(operation->inputLength); + + AESStartDMAOperation(operation->input, operation->inputLength, operation->output, operation->inputLength); + + return AESECB_waitForResult(handle); +} + +/* + * ======== AESECB_oneStepEncrypt ======== + */ +int_fast16_t AESECB_oneStepEncrypt(AESECB_Handle handle, AESECB_Operation *operationStruct) { + + return AESECB_startOperation(handle, operationStruct, AESECB_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESECB_oneStepDecrypt ======== + */ +int_fast16_t AESECB_oneStepDecrypt(AESECB_Handle handle, AESECB_Operation *operationStruct) { + + return AESECB_startOperation(handle, operationStruct, AESECB_OPERATION_TYPE_DECRYPT); +} + +/* + * ======== AESECB_cancelOperation ======== + */ +int_fast16_t AESECB_cancelOperation(AESECB_Handle handle) { + AESECBCC26XX_Object *object = handle->object; + uint32_t key; + + key = HwiP_disable(); + + if (!object->operationInProgress) { + HwiP_restore(key); + return AESECB_STATUS_ERROR; + } + + /* Reset the accelerator. Immediately stops ongoing operations. */ + AESReset(); + + /* Consume any outstanding interrupts we may have accrued + * since disabling interrupts. + */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->operationCanceled = true; + object->returnStatus = AESECB_STATUS_CANCELED; + + HwiP_restore(key); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + if (object->returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING) { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, + AESECB_STATUS_CANCELED, + object->operation, + object->operationType); + } + + return AESECB_STATUS_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesecb/AESECBCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesecb/AESECBCC26XX.h new file mode 100644 index 0000000..0c06721 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesecb/AESECBCC26XX.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESECBCC26XX.h + * + * @brief AESECB driver implementation for the CC26XX family + * + * @warning This is a beta API. It may change in future releases. + * + * This file should only be included in the board file to fill the AESECB_config + * struct. + * + * # Hardware Accelerator # + * The CC26XX family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation including ECB. Only one operation + * can be carried out on the accerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted ensure + * sensible access timeouts are set. + * + * # Key Store # + * The CC26XX crypto module contains a key store. The only way to load a key into + * the AES accelerator is to first load it into the key store. To guarantee availability + * of open key locations in the key store for AES operations, the last two key + * locations (6 and 7) are reserved for ad-hoc operations. The key is loaded into the + * key store, the AES operation is carried out, and the key is deleted from the key store. + * Since the key store does not have retention and the keys can not survive going into + * standby, the key store is only used to load keys into the AES accelerator rather + * than store keys. Support for pre-loading keys into the key store and using them + * in an AES operation is not supported in this driver. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * - This implementation does not support internal generation of IVs + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aesecb_AESECBCC26XX__include +#define ti_drivers_aesecb_AESECBCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include + +#include +#include +#include + +/*! + * @brief AESECBCC26XX Hardware Attributes + * + * AESECB26XX hardware attributes should be included in the board file + * and pointed to by the AESECB_config struct. + */ +typedef struct AESECBCC26XX_HWAttrs { + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; +} AESECBCC26XX_HWAttrs; + +/*! + * @brief AESECBCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct AESECBCC26XX_Object { + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t returnStatus; + AESECB_ReturnBehavior returnBehavior; + AESECB_OperationType operationType; + uint32_t semaphoreTimeout; + AESECB_CallbackFxn callbackFxn; + AESECB_Operation *operation; +} AESECBCC26XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesecb_AESECBCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesgcm/AESGCMCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesgcm/AESGCMCC26XX.c new file mode 100644 index 0000000..cc7436b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesgcm/AESGCMCC26XX.c @@ -0,0 +1,456 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) + + +/* Forward declarations */ +static void AESGCM_hwiFxn (uintptr_t arg0); +static int_fast16_t AESGCM_startOperation(AESGCM_Handle handle, + AESGCM_Operation *operation, + AESGCM_OperationType operationType); +static int_fast16_t AESGCM_waitForResult(AESGCM_Handle handle); +static void AESGCM_cleanup(AESGCM_Handle handle); + +/* Extern globals */ +extern const AESGCM_Config AESGCM_config[]; +extern const uint_least8_t AESGCM_count; + +/* Static globals */ +static bool isInitialized = false; + + +/* + * ======== AESGCM_hwiFxn ======== + */ +static void AESGCM_hwiFxn (uintptr_t arg0) { + AESGCMCC26XX_Object *object = ((AESGCM_Handle)arg0)->object; + uint32_t key; + + key = HwiP_disable(); + if (!object->operationCanceled) { + + /* Mark that we are done with the operation so that AESGCM_cancelOperation + * knows not to try canceling. + */ + object->operationInProgress = false; + + HwiP_restore(key); + } + else { + HwiP_restore(key); + return; + } + + /* Propagate the DMA error from driverlib to the application */ + if (AESIntStatusRaw() & AES_DMA_BUS_ERR) { + object->returnStatus = AESGCM_STATUS_ERROR; + } + + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + /* Handle cleaning up of the operation. Read out the tag + * or verify it against the provided one, invalidate the key, + * release the Power constraints, and post the access semaphore. + */ + AESGCM_cleanup((AESGCM_Handle)arg0); + + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else { + /* Call the callback function provided by the application. + */ + object->callbackFxn((AESGCM_Handle)arg0, + object->returnStatus, + object->operation, + object->operationType); + } +} + +static void AESGCM_cleanup(AESGCM_Handle handle) { + AESGCMCC26XX_Object *object = handle->object; + + /* We need to copy / verify the MAC now so that it is not clobbered when we + * release the CryptoResourceCC26XX_accessSemaphore semaphore. + */ + if (object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT) { + /* If we are encrypting and authenticating a message, we only want to + * copy the MAC to the target buffer + */ + AESReadTag(object->operation->mac, object->operation->macLength); + } + else { + /* If we are decrypting and verifying a message, we must now verify that the provided + * MAC matches the one calculated in the decryption operation. + */ + uint32_t verifyResult = AESVerifyTag(object->operation->mac, object->operation->macLength); + + object->returnStatus = (verifyResult == AES_SUCCESS) ? object->returnStatus : AESGCM_STATUS_MAC_INVALID; + } + + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides small + * power savings. + */ + AESSelectAlgorithm(0x00); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); +} + +/* + * ======== AESGCM_init ======== + */ +void AESGCM_init(void) { + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== AESGCM_open ======== + */ +AESGCM_Handle AESGCM_open(uint_least8_t index, AESGCM_Params *params) { + AESGCM_Handle handle; + AESGCMCC26XX_Object *object; + uint_fast8_t key; + + handle = (AESGCM_Handle)&(AESGCM_config[index]); + object = handle->object; + + DebugP_assert(index < AESGCM_count); + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* If params are NULL, use defaults */ + if (params == NULL) { + params = (AESGCM_Params *)&AESGCM_defaultParams; + } + + /* This is currently not supported. Eventually it will make the TRNG generate the iv */ + DebugP_assert(!params->ivInternallyGenerated); + DebugP_assert(params->returnBehavior == AESGCM_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + object->semaphoreTimeout = params->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING ? params->timeout : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for Crypto (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== AESGCM_close ======== + */ +void AESGCM_close(AESGCM_Handle handle) { + AESGCMCC26XX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on Crypto Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESGCM_startOperation ======== + */ +static int_fast16_t AESGCM_startOperation(AESGCM_Handle handle, + AESGCM_Operation *operation, + AESGCM_OperationType operationType) { + AESGCMCC26XX_Object *object = handle->object; + AESGCMCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + SemaphoreP_Status resourceAcquired; + uint32_t aesCtrl; + + /* Only plaintext CryptoKeys are supported for now */ + uint16_t keyLength = operation->key->u.plaintext.keyLength; + uint8_t *keyingMaterial = operation->key->u.plaintext.keyMaterial; + + DebugP_assert(handle); + DebugP_assert(key); + DebugP_assert(iv && ivLength == 12); + DebugP_assert((aad && aadLength) || (input && inputLength)); + DebugP_assert(mac && (macLength <= 16)); + DebugP_assert(key->encoding == CryptoKey_PLAINTEXT); + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, + object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) { + return AESGCM_STATUS_RESOURCE_UNAVAILABLE; + } + + object->operationType = operationType; + object->operation = operation; + /* We will only change the returnStatus if there is an error */ + object->returnStatus = AESGCM_STATUS_SUCCESS; + object->operationCanceled = false; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESGCM_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* Load the key from RAM or flash into the key store at a hardcoded and reserved location */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) { + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + return AESGCM_STATUS_ERROR; + } + + /* If we are in AESGCM_RETURN_BEHAVIOR_POLLING, we do not want an interrupt to trigger. + * AESWriteToKeyStore() disables and then re-enables the CRYPTO IRQ in the NVIC so we + * need to disable it before kicking off the operation. + */ + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_POLLING) { + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* Load the key from the key store into the internal register banks of the AES sub-module */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) { + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + return AESGCM_STATUS_ERROR; + } + + /* Disallow standby. We are about to configure and start the accelerator. + * Setting the constraint should happen after all opportunities to fail out of the + * function. This way, we do not need to undo it each time we exit with a failure. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ((uint32_t *)operation->iv)[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ((uint32_t *)operation->iv)[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ((uint32_t *)operation->iv)[2]; + /* Set initial counter value to 1. Counter is interpreted as big-endian number of last + * four bytes of IV + */ + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = 0x01000000; + + /* We need to split building aesCtrl into multiple calls. + * Trying to combine all of the below leads to the compiler removing the GCM flag + * for some reason. + * Unlike CCM, GCM CTR only increments the 32-bit counter at the end of the IV not + * the entire 16-byte IV itself. + */ + aesCtrl = CRYPTO_AESCTL_GCM_M | + CRYPTO_AESCTL_CTR | + CRYPTO_AESCTL_SAVE_CONTEXT | + CRYPTO_AESCTL_CTR_WIDTH_32_BIT; + aesCtrl |= operationType == AESGCM_OPERATION_TYPE_ENCRYPT ? CRYPTO_AESCTL_DIR : 0; + AESSetCtrl(aesCtrl); + + AESSetDataLength(operation->inputLength); + AESSetAuthLength(operation->aadLength); + + if (operation->aadLength) { + /* If aadLength were 0, AESWaitForIRQFlags() would never return as the AES_DMA_IN_DONE flag + * would never trigger. + */ + AESStartDMAOperation(operation->aad, operation->aadLength, NULL, 0); + AESWaitForIRQFlags(AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + } + + AESStartDMAOperation(operation->input, operation->inputLength, operation->output, operation->inputLength); + + + return AESGCM_waitForResult(handle); +} + +/* + * ======== AESGCM_waitForResult ======== + */ +static int_fast16_t AESGCM_waitForResult(AESGCM_Handle handle) { + AESGCMCC26XX_Object *object = handle->object; + + object->operationInProgress = true; + + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_POLLING) { + /* Wait until the operation is complete and check for DMA errors. */ + if(AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR){ + object->returnStatus = AESGCM_STATUS_ERROR; + } + + /* Mark that we are done with the operation */ + object->operationInProgress = false; + + /* Make sure to also clear DMA_IN_DONE as it is not cleared above + * but will be set none-the-less. + */ + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + /* Instead of posting the swi to handle cleanup, we will execute + * the core of the function here */ + AESGCM_cleanup(handle); + + return object->returnStatus; + } + else if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + return object->returnStatus; + } + else { + return AESGCM_STATUS_SUCCESS; + } +} + +/* + * ======== AESGCM_oneStepEncrypt ======== + */ +int_fast16_t AESGCM_oneStepEncrypt(AESGCM_Handle handle, AESGCM_Operation *operationStruct) { + + return AESGCM_startOperation(handle, operationStruct, AESGCM_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESGCM_oneStepDecrypt ======== + */ +int_fast16_t AESGCM_oneStepDecrypt(AESGCM_Handle handle, AESGCM_Operation *operationStruct) { + + return AESGCM_startOperation(handle, operationStruct, AESGCM_OPERATION_TYPE_DECRYPT); +} + +/* + * ======== AESGCM_cancelOperation ======== + */ +int_fast16_t AESGCM_cancelOperation(AESGCM_Handle handle) { + AESGCMCC26XX_Object *object = handle->object; + uint32_t key; + + key = HwiP_disable(); + + if (!object->operationInProgress) { + HwiP_restore(key); + return AESGCM_STATUS_ERROR; + } + + /* Reset the accelerator. Immediately stops ongoing operations. */ + AESReset(); + + /* Consume any outstanding interrupts we may have accrued + * since disabling interrupts. + */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->operationCanceled = true; + object->returnStatus = AESGCM_STATUS_CANCELED; + + HwiP_restore(key); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, + AESGCM_STATUS_CANCELED, + object->operation, + object->operationType); + } + + return AESGCM_STATUS_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesgcm/AESGCMCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesgcm/AESGCMCC26XX.h new file mode 100644 index 0000000..43cf364 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesgcm/AESGCMCC26XX.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESGCMCC26XX.h + * + * @brief AESGCM driver implementation for the CC26XX family + * + * @warning This is a beta API. It may change in future releases. + * + * This file should only be included in the board file to fill the AESGCM_config + * struct. + * + * # Hardware Accelerator # + * The CC26XX family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation including GCM. Only one operation + * can be carried out on the accerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted ensure + * sensible access timeouts are set. + * + * # Key Store # + * The CC26XX crypto module contains a key store. The only way to load a key into + * the AES accelerator is to first load it into the key store. To guarantee availability + * of open key locations in the key store for AES operations, the last two key + * locations (6 and 7) are reserved for ad-hoc operations. The key is loaded into the + * key store, the AES operation is carried out, and the key is deleted from the key store. + * Since the key store does not have retention and the keys can not survive going into + * standby, the key store is only used to load keys into the AES accelerator rather + * than store keys. Support for pre-loading keys into the key store and using them + * in an AES operation is not supported in this driver. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * - This implementation does not support internal generation of IVs + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aesgcm_AESGCMCC26XX__include +#define ti_drivers_aesgcm_AESGCMCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include + +#include +#include +#include + +/*! + * @brief AESGCMCC26XX Hardware Attributes + * + * AESGCM26XX hardware attributes should be included in the board file + * and pointed to by the AESGCM_config struct. + */ +typedef struct AESGCMCC26XX_HWAttrs { + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; +} AESGCMCC26XX_HWAttrs; + +/*! + * @brief AESGCMCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct AESGCMCC26XX_Object { + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t returnStatus; + AESGCM_ReturnBehavior returnBehavior; + AESGCM_OperationType operationType; + uint32_t semaphoreTimeout; + AESGCM_CallbackFxn callbackFxn; + AESGCM_Operation *operation; +} AESGCMCC26XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesgcm_AESGCMCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/crypto/CryptoCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/crypto/CryptoCC26XX.c new file mode 100644 index 0000000..4d6687f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/crypto/CryptoCC26XX.c @@ -0,0 +1,738 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/crypto.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/smph.h) + +/* Externs */ +/* + * CryptoCC26XX configuration - initialized in the board file. + * + * @code + * // Include drivers + * #include + * + * // Crypto objects + * CryptoCC26XX_Object cryptoCC26XXObjects[CC2650_CRYPTOCOUNT]; + * + * // Crypto configuration structure, describing which pins are to be used + * const CryptoCC26XX_HWAttrs cryptoCC26XXHWAttrs[CC2650_CRYPTOCOUNT] = { + * { + * .baseAddr = CRYPTO_BASE, + * .powerMngrId = PERIPH_CRYPTO, + * .intNum = INT_CRYPTO, + * .intPriority = ~0 + * } + * }; + * + * // Crypto configuration structure + * const CryptoCC26XX_Config CryptoCC26XX_config[] = { + * {&cryptoCC26XXObjects[0], &cryptoCC26XXHWAttrs[0]}, + * {NULL, NULL} + * }; + * @endcode + */ +extern const CryptoCC26XX_Config CryptoCC26XX_config[]; + +/* Forward declarations */ +static int cryptoPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg); +static bool cryptoTransactionPend(CryptoCC26XX_Handle handle); +static bool cryptoTransactionPoll(void); +static int cryptoTransactionExecute(CryptoCC26XX_Handle handle, CryptoCC26XX_Transaction *transaction, bool polling); + +/* Flag to signal interrupt has happened */ +static volatile bool hwiIntFlag; + +static bool isInitialized = false; + +/* + * ======== CryptoCC26XX_hwiIntFxn ======== + * Hwi function that processes CryptoCC26XX interrupts. + * + * @param(arg) The CryptoCC26XX_Handle for this Hwi. + */ +void CryptoCC26XX_hwiIntFxn(uintptr_t arg) +{ + CryptoCC26XX_Object *object; + + /* Get the pointer to the object */ + object = ((CryptoCC26XX_Handle)arg)->object; + + /* Clear interrupts */ + CRYPTOIntClear(CRYPTO_DMA_IN_DONE | CRYPTO_RESULT_RDY); + + /* Set hwi flag */ + hwiIntFlag = true; + if(object->currentTransact->mode == CRYPTOCC26XX_MODE_BLOCKING) { + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } +} + +/* + * ======== CryptoCC26XX_init ======== + */ +void CryptoCC26XX_init(void) +{ + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== CryptoCC26XX_Params_init ======== + */ +void CryptoCC26XX_Params_init(CryptoCC26XX_Params *params) +{ + DebugP_assert(params != NULL); + + params->timeout = SemaphoreP_WAIT_FOREVER; +} + +/* + * ======== CryptoCC26XX_AESCCM_Transac_init ======== + */ +void CryptoCC26XX_Transac_init(CryptoCC26XX_Transaction *trans, CryptoCC26XX_Operation opType) +{ + DebugP_assert(trans != NULL); + + trans->opType = opType; +} + +/* + * ======== CryptoCC26XX_open ======== + */ +CryptoCC26XX_Handle CryptoCC26XX_open(unsigned int index, bool exclusiveAccess, CryptoCC26XX_Params *params) +{ + unsigned int key; + CryptoCC26XX_Handle handle; + CryptoCC26XX_Object *object; + CryptoCC26XX_HWAttrs const *hwAttrs; + CryptoCC26XX_Params cryptoParams; + + /* Ensure that Crypto driver has been successfully initialized */ + DebugP_assert(isInitialized == true); + + // Ensure that only one client at a time can call CryptoCC26XX_open() + SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, SemaphoreP_WAIT_FOREVER); + + /* Get handle for this driver instance */ + handle = (CryptoCC26XX_Handle)&(CryptoCC26XX_config[index]); + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable preemption while checking if the CryptoCC26XX is open. */ + key = HwiP_disable(); + + if (isInitialized == false) { + HwiP_restore(key); + /* Release semaphore */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + return (NULL); + } + + /* Check if the CryptoCC26XX is open already with exclusive access or + * if Crypto is already open and new client want exclusive access. + */ + if (object->openCnt < 0) { + HwiP_restore(key); + DebugP_log1("CryptoCC26XX:(%p) in use with exclusive access.", hwAttrs->baseAddr); + /* Release semaphore */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + return (NULL); + } + + if (object->openCnt > 0 && exclusiveAccess == true) { + HwiP_restore(key); + DebugP_log1("CryptoCC26XX:(%p) already in use, exclusive access is not possible.", hwAttrs->baseAddr); + /* Release semaphore */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + return (NULL); + } + + /* Update openCnt */ + if (exclusiveAccess) { + /* If we have come this far and exclusiveAccess is set, set openCnt to negative value */ + object->openCnt = -1; + } else { + /* If not exclusive, increment openCnt */ + object->openCnt += 1; + } + + /* Re-enable the hwis */ + HwiP_restore(key); + + /* Check if the CryptoCC26XX is open already with the base addr. */ + if (object->openCnt > 1) { + /* Release semaphore */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + /* Crypto is already configured, return handle */ + return (handle); + } + + /* If params are NULL use defaults. */ + if (params == NULL) { + CryptoCC26XX_Params_init(&cryptoParams); + params = &cryptoParams; + } + object->timeout = params->timeout; + + /* Reserve key slots 6 and 7 for use by other drivers */ + object->keyStore = 1 << 6 | 1 << 7; + + /* Set power dependency - i.e. power up and enable clock for Crypto (CryptoCC26XX) module. */ + Power_setDependency(hwAttrs->powerMngrId); + + /* Register notification function */ + Power_registerNotify(&object->cryptoNotiObj, PowerCC26XX_AWAKE_STANDBY, (Power_NotifyFxn)cryptoPostNotify, (uint32_t)handle); + + DebugP_log1("CryptoCC26XX:(%p) opened", hwAttrs->baseAddr); + + /* Release semaphore */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + /* Return the handle */ + return (handle); +} + +/* + * ======== CryptoCC26XX_close ======== + */ +int CryptoCC26XX_close(CryptoCC26XX_Handle handle) +{ + unsigned int key; + CryptoCC26XX_Object *object; + CryptoCC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* If openCnt is zero and someone tries to close, return error*/ + if (object->openCnt == 0) { + return CRYPTOCC26XX_STATUS_ERROR; + } + + /* Disable preemption while updating opened count. */ + key = HwiP_disable(); + + if (object->openCnt < 0) { + /* If the openCnt is less than zero(-1), it is exclusiveAccess */ + object->openCnt = 0; + } else { + object->openCnt -= 1; + } + + /* Re-enable the hwis */ + HwiP_restore(key); + + if(object->openCnt == 0) { + /* Release power dependency - i.e. potentially power down peripheral domain. */ + Power_releaseDependency(hwAttrs->powerMngrId); + /* Unregister power notification object */ + Power_unregisterNotify(&object->cryptoNotiObj); + } + + DebugP_log1("CryptoCC26XX:(%p) closed", hwAttrs->baseAddr); + return CRYPTOCC26XX_STATUS_SUCCESS; +} + +/* + * ======== CryptoCC26XX_releaseKey ======== + */ +int CryptoCC26XX_releaseKey(CryptoCC26XX_Handle handle, int *keyIndex) +{ + unsigned int hwikey; + CryptoCC26XX_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Disable preemption while updating opened count. */ + hwikey = HwiP_disable(); + + /* Clear key index in key store */ + object->keyStore &= ~(1<<(*keyIndex)); + *keyIndex = -1; + + /* Re-enable the hwis */ + HwiP_restore(hwikey); + + return CRYPTOCC26XX_STATUS_SUCCESS; +} + +/* + * ======== CryptoCC26XX_allocateKey ======== + */ +int CryptoCC26XX_allocateKey(CryptoCC26XX_Handle handle, CryptoCC26XX_KeyLocation keyLocation, const uint32_t *keySrc) +{ + unsigned long res; + int keyIndex; + CryptoCC26XX_Object *object; + int i; + + object = handle->object; + keyIndex = CRYPTOCC26XX_STATUS_ERROR; + + /* Wait for the HW module to become available */ + SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, SemaphoreP_WAIT_FOREVER); + + /* KEY_ANY means first available kay starting from highest index will be used */ + if (keyLocation == CRYPTOCC26XX_KEY_ANY) { + for (i = CRYPTOCC26XX_KEY_5; i >= 0 ; i--) { + /* Search for first available key in store */ + if (!(object->keyStore & (1<keyStore |= (1<keyStore & (1<keyStore |= (1<keyStore &= ~(1<object; + + /* Blocking is allowed if we are in task context. + * If blocking is allowed, we should block based on the timeout + * and otherwise use NO_WAIT instead if in Hwi or Swi . + */ + blockingAllowed = !(SwiP_inISR() || HwiP_inISR()); + + /* Try to acquire the semaphore */ + semaphoreAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, blockingAllowed ? object->timeout : SemaphoreP_NO_WAIT); + + /* Check if we acquired the semaphore */ + if(semaphoreAcquired == SemaphoreP_OK) { + if(keyIndex != CRYPTOCC26XX_STATUS_ERROR){ + /* We are not allowed to switch to XOSC_HF while other bus transactions are ongoing */ + Power_setConstraint(PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING); + /* Write key to crypto RAM */ + uint32_t tmpReturnVal = CRYPTOAesLoadKey((uint32_t*) keySrc, keyIndex); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING); + + if(tmpReturnVal == AES_SUCCESS){ + loadKeyStatus = CRYPTOCC26XX_STATUS_SUCCESS; + } + } + /* Release semaphore */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + } + + return (loadKeyStatus); +} + + +/* + * ======== CryptoCC26XX_transact ======== + */ +int CryptoCC26XX_transact(CryptoCC26XX_Handle handle, CryptoCC26XX_Transaction *transaction) +{ + return cryptoTransactionExecute(handle, transaction, false); +} + +/* +* ======== CryptoCC26XX_transactPolling ======== +*/ +int CryptoCC26XX_transactPolling(CryptoCC26XX_Handle handle, CryptoCC26XX_Transaction *transaction) +{ + return cryptoTransactionExecute(handle, transaction, true); +} + +/* +* ======== CryptoCC26XX_transactBlocking ======== +*/ +int CryptoCC26XX_transactCallback(CryptoCC26XX_Handle handle, CryptoCC26XX_Transaction *transaction) +{ + return (CRYPTOCC26XX_STATUS_UNDEFINEDCMD); +} + +/* + * ======== cryptoPostNotify ======== + * This functions is called to notify the CRYPTO driver of an ongoing transition + * out of standby mode. + * + * @pre Function assumes that the CRYPTO handle (clientArg) is pointing to a + * hardware module which has already been opened. + */ +static int cryptoPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg) +{ + CryptoCC26XX_Object *object; + /* Currently only subscribing to AWAKE_STANDBY notification, so if notified */ + /* we are returning from standby. Reset the keyStore since the RAM content is lost */ + object = ((CryptoCC26XX_Handle) clientArg)->object; + object->keyStore = 1 << 6 | 1 << 7; + + return Power_NOTIFYDONE; +} + +/* + * ======== cryptoTransactionPend ======== + * This function pends on a semaphore posted by the crypto hwi after the crypto operation is completed. + */ +static bool cryptoTransactionPend(CryptoCC26XX_Handle handle){ + CryptoCC26XX_Object *object; + object = handle->object; + bool transactionCompleted = false; + + /* Pend on blocking mode semaphore and wait for Hwi to finish. */ + if (SemaphoreP_OK != SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, object->timeout)) + { + /* Semaphore timed out */ + DebugP_log1("CryptoCC26XX:(%p) AES transaction timed out", + (((CryptoCC26XX_HWAttrs *)handle->hwAttrs)->baseAddr)); + /* Release constraint since transaction is done */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + Power_releaseConstraint(PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING); + /* Release semaphore */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + transactionCompleted = false; + } + else{ + transactionCompleted = true; + } + return transactionCompleted; +} + +/* + * ======== cryptoTransactionPoll ======== + * This function polls a global variable that is set in the crypto hwi. This allows for a crypto transaction to be called from a different hwi. + */ +static bool cryptoTransactionPoll(void){ + /* Polling mode, wait for intterupt */ + do { + CPUdelay(1); + } while(!hwiIntFlag); + return true; +} + +/* + * ======== cryptoTransactionPoll ======== + * This function handles all supported crypto modes and interfaces with driverlib to configure the hardware correctly. + */ +static int cryptoTransactionExecute(CryptoCC26XX_Handle handle, CryptoCC26XX_Transaction *transaction, bool polling){ + CryptoCC26XX_Object *object; + const CryptoCC26XX_HWAttrs *hwAttrs; + unsigned int key; + int res; + uint8_t transactionCompleted; + union { + CryptoCC26XX_AESCCM_Transaction *aesccm; + CryptoCC26XX_AESECB_Transaction *aesecb; + CryptoCC26XX_AESCBC_Transaction *aescbc; + } transUnion; + + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Check if the crypto is active already (grab semaphore) */ + if (SemaphoreP_OK != SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, + polling ? SemaphoreP_NO_WAIT : SemaphoreP_WAIT_FOREVER)) { + DebugP_log0("CryptoCC26XX: CryptoCC26XX_transactPolling() was called when crypto module is already busy."); + return AES_DMA_BSY; + } + + /* Set interrupt flag to unhandled */ + hwiIntFlag = false; + + /* Set current transaction as head and tail */ + object->currentTransact = transaction; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, CryptoCC26XX_hwiIntFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + if (polling) { + /* Set mode of the transaction */ + transaction->mode = CRYPTOCC26XX_MODE_POLLING; + } + else { + /* Set mode of the transaction */ + transaction->mode = CRYPTOCC26XX_MODE_BLOCKING; + /* Set constraints to guarantee transaction */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + Power_setConstraint(PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING); + } + + /* Check type field to decide which transact/operation to perform */ + /* TODO: To queue or not to queue? */ + switch (transaction->opType) { +#ifndef CRYPTOCC26XX_EXCLUDE_AES_CCM_ENCRYPT + case CRYPTOCC26XX_OP_AES_CCM_ENCRYPT : + case CRYPTOCC26XX_OP_AES_CCM_ENCRYPT_AAD_ONLY : + /* Do some typecasting to get the right fields */ + transUnion.aesccm = (CryptoCC26XX_AESCCM_Transaction *) transaction; + + /* + * Disable HWIs + * Ensure no preemption issue with driverlib implementation + * although it's already protected with semaphore. + */ + key = HwiP_disable(); + + /* Do the transaction/operation */ + res = CRYPTOCcmAuthEncrypt((transaction->opType) == CRYPTOCC26XX_OP_AES_CCM_ENCRYPT, + transUnion.aesccm->authLength, + (uint32_t*) transUnion.aesccm->nonce, + (uint32_t*) transUnion.aesccm->msgIn, + transUnion.aesccm->msgInLength, + (uint32_t*) transUnion.aesccm->header, + transUnion.aesccm->headerLength, + transUnion.aesccm->keyIndex, + transUnion.aesccm->fieldLength, + true); + + /* Restore HWIs */ + HwiP_restore(key); + + /* If operation setup failed, break out and return error */ + if (res != AES_SUCCESS) { + break; + } + + transactionCompleted = polling ? cryptoTransactionPoll() : cryptoTransactionPend(handle); + if(!transactionCompleted){ + return CRYPTOCC26XX_TIMEOUT; + } + + /* Get CCM status */ + res = CRYPTOCcmAuthEncryptStatus(); + if(res == AES_SUCCESS) { + res = CRYPTOCcmAuthEncryptResultGet(transUnion.aesccm->authLength, + (uint32_t*) transUnion.aesccm->msgOut); + } + /* CCM finished */ + break; +#endif +#ifndef CRYPTOCC26XX_EXCLUDE_AES_CCM_DECRYPT + case CRYPTOCC26XX_OP_AES_CCM_DECRYPT : + case CRYPTOCC26XX_OP_AES_CCM_DECRYPT_AAD_ONLY : + /* Do some typecasting to get the right fields */ + transUnion.aesccm = (CryptoCC26XX_AESCCM_Transaction *) transaction; + + /* + * Disable HWIs + * Ensure no preemption issue with driverlib implementation + * although it's already protected with semaphore. + */ + key = HwiP_disable(); + + /* Do the transaction/operation */ + res = CRYPTOCcmInvAuthDecrypt((transaction->opType) == CRYPTOCC26XX_OP_AES_CCM_DECRYPT, + transUnion.aesccm->authLength, + (uint32_t*) transUnion.aesccm->nonce, + (uint32_t*) transUnion.aesccm->msgIn, + transUnion.aesccm->msgInLength, + (uint32_t*) transUnion.aesccm->header, + transUnion.aesccm->headerLength, + transUnion.aesccm->keyIndex, + transUnion.aesccm->fieldLength, + true); + + /* Restore HWIs */ + HwiP_restore(key); + + /* If operation setup failed, break out and return error */ + if (res != AES_SUCCESS){ + break; + } + + transactionCompleted = polling ? cryptoTransactionPoll() : cryptoTransactionPend(handle); + if(!transactionCompleted){ + return CRYPTOCC26XX_TIMEOUT; + } + + /* Get CCMINV status */ + res = CRYPTOCcmInvAuthDecryptStatus(); + if(res == AES_SUCCESS) + { + res = CRYPTOCcmInvAuthDecryptResultGet(transUnion.aesccm->authLength, + (uint32_t*) transUnion.aesccm->msgIn, + transUnion.aesccm->msgInLength, + (uint32_t*) transUnion.aesccm->msgOut); + } + /* CCMINV finished */ + break; +#endif +#ifndef CRYPTOCC26XX_EXCLUDE_AES_ECB + case CRYPTOCC26XX_OP_AES_ECB_ENCRYPT : + case CRYPTOCC26XX_OP_AES_ECB_DECRYPT : + /* Do some typecasting to get the right fields */ + transUnion.aesecb = (CryptoCC26XX_AESECB_Transaction *) transaction; + + /* + * Disable HWIs + * Ensure no preemption issue with driverlib implementation + * although it's already protected with semaphore. + */ + key = HwiP_disable(); + + /* Do the transaction/operation */ + res = CRYPTOAesEcb(transUnion.aesecb->msgIn, + transUnion.aesecb->msgOut, + transUnion.aesecb->keyIndex, + (transaction->opType) == CRYPTOCC26XX_OP_AES_ECB_ENCRYPT, + true); + + /* Restore HWIs */ + HwiP_restore(key); + + /* If operation setup failed, break out and return error */ + if (res != AES_SUCCESS){ + break; + } + + transactionCompleted = polling ? cryptoTransactionPoll() : cryptoTransactionPend(handle); + if(!transactionCompleted){ + return CRYPTOCC26XX_TIMEOUT; + } + + /* Get ECB status */ + res = CRYPTOAesEcbStatus(); + CRYPTOAesEcbFinish(); + /* ECB finished */ + break; +#endif +#ifndef CRYPTOCC26XX_EXCLUDE_AES_CBC + case CRYPTOCC26XX_OP_AES_CBC_ENCRYPT: + case CRYPTOCC26XX_OP_AES_CBC_DECRYPT: + /* Do some typecasting to get the right fields */ + transUnion.aescbc = (CryptoCC26XX_AESCBC_Transaction *) transaction; + + /* + * Disable HWIs + * Ensure no preemption issue with driverlib implementation + * although it's already protected with semaphore. + */ + key = HwiP_disable(); + + /* Do the transaction/operation */ + res = CRYPTOAesCbc(transUnion.aescbc->msgIn, + transUnion.aescbc->msgOut, + transUnion.aescbc->msgInLength, + transUnion.aescbc->nonce, + transUnion.aescbc->keyIndex, + (transaction->opType) == CRYPTOCC26XX_OP_AES_CBC_ENCRYPT, + true); + + /* Restore HWIs */ + HwiP_restore(key); + + /* If operation setup failed, break out and return error */ + if (res != AES_SUCCESS){ + break; + } + + transactionCompleted = polling ? cryptoTransactionPoll() : cryptoTransactionPend(handle); + if(!transactionCompleted){ + return CRYPTOCC26XX_TIMEOUT; + } + + /* Get CBC status */ + res = CRYPTOAesCbcStatus(); + CRYPTOAesCbcFinish(); + /* CBC finished */ + break; +#endif + default : + DebugP_log1("CryptoCC26XX: Could not recognize transaction (%p).", + (transaction->opType)); + res = CRYPTOCC26XX_STATUS_ERROR; + } + + /* Release constraint since transaction is done */ + if(!polling){ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + Power_releaseConstraint(PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING); + } + /* Release semaphore */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + return (res); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/crypto/CryptoCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/crypto/CryptoCC26XX.h new file mode 100644 index 0000000..9de0b44 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/crypto/CryptoCC26XX.h @@ -0,0 +1,1002 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CryptoCC26XX.h + * + * @brief Crypto driver implementation for a CC26XX Crypto controller + * + * # Driver Include # + * The Crypto header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * @anchor ti_drivers_Crypto_Overview + * # Overview # + * + * The CryptoCC26XX driver simplifies reading and writing to the CryptoCC26XX + * peripheral on the board with multiple modes of operation and performance. + * These include blocking and polling. A timeout can be configured in blocking mode. + * The driver supports encryption and decryption for both AES-ECB and AES-CCM. + * + * @anchor ti_drivers_Crypto_Usage + * ## Usage # + * + * @warning The application should not attempt to encrypt a value stored in flash or use a + * key stored in flash if the application might switch to the XOSC_HF, + * the high frequency external oscillator, during the operation. + * + * ### Opening the driver # + * - The application initializes the CryptoCC26XX driver by + * calling CryptoCC26XX_init() and is then ready to open a CryptoCC26XX by calling + * CryptoCC26XX_open(). + * - If one client (the first) calls the CryptoCC26XX_open() with the exclusiveAccess + * flag set, all subsequent calls to open will fail (i.e. return a NULL pointer). + * The first client can use the Crypto module exclusively. + * - Only one client can call CryptoCC26XX_open() at the same time, a second client + * will pend until the first client's call will release a semaphore. + * - The number of clients are counted with openCnt in ::CryptoCC26XX_Object. + * . + * @code + * // Declaration (typically done in a task) + * CryptoCC26XX_Handle handle; + * CryptoCC26XX_Params params; + * bool exclusiveAccess = false; + * + * // Initialize Crypto driver + * CryptoCC26XX_init(); + * + * // Configure CryptoCC26XX parameters. + * CryptoCC26XX_Params_init(¶ms); + * + * // Attempt to open CryptoCC26XX. + * handle = CryptoCC26XX_open(Board_CRYPTO0, exclusiveAccess, ¶ms); + * if (!handle) { + * System_printf("CryptoCC26XX did not open"); + * } + * @endcode + * + * ### Before starting a crypto operation # + * - Before any encryption/decryption operation starts, the key store must have at + * least one key loaded. + * - To get access to a location in the key store, the caller must allocated it by + * calling CryptoCC26XX_allocateKey(). + * - If the requested key location is available, the client will get a key index + * (uint8_t) returned. + * - If the requested key location is already occupied, the CryptoCC26XX_allocateKey() + * will fail and return ::CRYPTOCC26XX_STATUS_ERROR. + * - The key locations available are defined in ::CryptoCC26XX_KeyLocation. + * - To select any available key location, call the allocate function with key + * location set to CRYPTOCC26XX_KEY_ANY. + * . + * ### Performing a crypto operation # + * - The supported crypto operations are defined in ::CryptoCC26XX_Operation. + * - The operation is initiated by calling a transaction function. + * - The type of operation is decided by the transaction pointer passed to the + * transaction function. + * - The mode of the transaction (i.e. blocking/polling) is decided by selecting the + * corresponding transact function (see Supported transaction modes below). + * - The key index is passed to the encryption/decryption transaction functions as + * part of the transaction object. + * - When a transaction starts, a semaphore is used to ensure that only one transaction + * is performed at a given time. The polling transaction is using 0 wait time, and + * will return immediately with ::CRYPTOCC26XX_STATUS_ERROR if the semaphore is not granted. + * - In blocking mode a constraint is set to ensure that the device only enters idle mode + * if the CPU becomes inactive. + * - When the transaction ends, the device might enter standby. + * - A key location can be deallocated by calling CryptoCC26XX_releaseKey(). + * . + * ### Supported transaction modes # + * - ::CRYPTOCC26XX_MODE_BLOCKING, typically used from task context. Selected by calling the + * CryptoCC26XX_transact() function. + * - ::CRYPTOCC26XX_MODE_POLLING, typically used from hwi/swi context. Selected by calling the + * CryptoCC26XX_transactPolling() function. This mode should be replaced by a + * callback mode in a future release. + * . + * ### Closing the driver # + * The crypto driver is closed by calling CryptoCC26XX_close() function. When the openCnt + * is decremented to zero, the crypto related bios modules are destructed. + * @code + * CryptoCC26XX_close(handle); + * @endcode + * + * ## Error handling ## + * If an error occur during encryption/decryption, the operation will return the + * error code and the device might enter standby. + * + * ## Power Management ## + * During a transaction in blocking mode, the Power_DISALLOW_STANDBY + * constraint is set to block the system from entering standby mode. During + * this period the system will enter idle mode if no tasks are running. + * + * A system dependency on crypto will be active as long as there are + * clients with an open handle to the crypto. + * + * @note When coming out of standby the key store RAM has lost it's content, so the + * keyStore in ::CryptoCC26XX_Object will be cleared and the clients will have to + * allocate the key over again. + * + * ## Unsupported functionality: + * Functionality that currently not supported: + * - Callback mode + * - Queued transactions for use in callback mode + * + * ## Supported Operations ## + * | Operation Type | Description | + * |-----------------------------------------------|---------------------------------------------------------------------------| + * | ::CRYPTOCC26XX_OP_AES_CCM_ENCRYPT | AES-CCM encryption of plaintext and authentication of AAD and plaintext | + * | ::CRYPTOCC26XX_OP_AES_CCM_ENCRYPT_AAD_ONLY | AES-CCM authentication of AAD only. No payload. | + * | ::CRYPTOCC26XX_OP_AES_CCM_DECRYPT | AES-CCM decryption of plaintext and verification of AAD and plaintext | + * | ::CRYPTOCC26XX_OP_AES_CCM_DECRYPT_AAD_ONLY | AES-CCM verification of AAD only. No payload. | + * | ::CRYPTOCC26XX_OP_AES_ECB_ENCRYPT | AES-ECB encryption | + * | ::CRYPTOCC26XX_OP_AES_ECB_DECRYPT | AES-ECB decryption | + * | ::CRYPTOCC26XX_OP_AES_CBC_ENCRYPT | AES-CBC encryption | + * | ::CRYPTOCC26XX_OP_AES_CBC_DECRYPT | AES-CBC decryption | + * + * @anchor ti_drivers_Crypto_Synopsis + * ## Synopsis + * @anchor ti_drivers_Crypto_Synopsis_Code + * @code + * // Import Crypto Driver definitions + * #include + * + * // Define name for Crypto channel index + * #define Crypto_INSTANCE 0 + * + * // Initialize Crypto driver + * CryptoCC26XX_init(); + * + * + * // Attempt to open CryptoCC26XX. + * handle = CryptoCC26XX_open(Board_CRYPTO0, false, NULL); + * + * keyIndex = CryptoCC26XX_allocateKey(handle, ecbExample.keyLocation, + * (const uint32_t *) ecbExample.key); + * + * // Initialize transaction + * CryptoCC26XX_Transac_init((CryptoCC26XX_Transaction *) &trans, CRYPTOCC26XX_OP_AES_ECB_ENCRYPT); + * + * // Setup transaction + * trans.keyIndex = keyIndex; + * trans.msgIn = (uint32_t *) ecbExample.clearText; + * trans.msgOut = (uint32_t *) ecbExample.msgOut; + * + * + * // Encrypt the plaintext with AES ECB + * status = CryptoCC26XX_transact(handle, (CryptoCC26XX_Transaction *) &trans); + * + * // Initialize transaction + * CryptoCC26XX_Transac_init((CryptoCC26XX_Transaction *) &trans, CRYPTOCC26XX_OP_AES_ECB_DECRYPT); + * + * // Setup transaction + * trans.keyIndex = keyIndex; + * trans.msgIn = (uint32_t *) ecbExample.msgOut; + * trans.msgOut = (uint32_t *) ecbExample.clearText; + * + * // Decrypt the plaintext with AES ECB + * status = CryptoCC26XX_transact(handle, (CryptoCC26XX_Transaction *) &trans); + * + * CryptoCC26XX_releaseKey(handle, &keyIndex); + * + * Crypto_close(handle); + * + * @endcode + * + * @anchor ti_drivers_Crypto_Examples + * ## Examples ## + * ### AES ECB operation # + * Perform a crypto operation with AES-ECB in ::CRYPTOCC26XX_MODE_BLOCKING. + + * @code + * // AES-ECB example struct + * typedef struct + * { + * uint8_t key[16]; // Stores the Aes Key + * CryptoCC26XX_KeyLocation keyLocation; // Location in Key RAM + * uint8_t clearText[AES_ECB_LENGTH]; // Input message - cleartext + * uint8_t msgOut[AES_ECB_LENGTH]; // Output message + * } AESECBExample; + * + * // AES ECB example data + * AESECBExample ecbExample = + * { + * { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, + * 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }, + * CRYPTOCC26XX_KEY_0, + * {'t','h','i','s','i','s','a','p','l','a','i','n','t','e','x','t'}, + * { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + * }; + * + * // Declaration (typically done in a task) + * CryptoCC26XX_Handle handle; + * int32_t keyIndex; + * int32_t status; + * CryptoCC26XX_AESECB_Transaction trans; + * + * // Initialize Crypto driver + * CryptoCC26XX_init(); + * + * + * // Attempt to open CryptoCC26XX. + * handle = CryptoCC26XX_open(Board_CRYPTO0, false, NULL); + * if (!handle) { + * System_abort("Crypto module could not be opened."); + * } + * + * keyIndex = CryptoCC26XX_allocateKey(handle, ecbExample.keyLocation, + * (const uint32_t *) ecbExample.key); + * + * if (keyIndex == CRYPTOCC26XX_STATUS_ERROR) { + * System_abort("Key Location was not allocated."); + * } + * + * // Initialize transaction + * CryptoCC26XX_Transac_init((CryptoCC26XX_Transaction *) &trans, CRYPTOCC26XX_OP_AES_ECB_ENCRYPT); + * + * // Setup transaction + * trans.keyIndex = keyIndex; + * trans.msgIn = (uint32_t *) ecbExample.clearText; + * trans.msgOut = (uint32_t *) ecbExample.msgOut; + * + * + * // Encrypt the plaintext with AES ECB + * status = CryptoCC26XX_transact(handle, (CryptoCC26XX_Transaction *) &trans); + * if(status != CRYPTOCC26XX_STATUS_SUCCESS){ + * System_abort("Encryption failed."); + * } + * + * // Initialize transaction + * CryptoCC26XX_Transac_init((CryptoCC26XX_Transaction *) &trans, CRYPTOCC26XX_OP_AES_ECB_DECRYPT); + * + * // Setup transaction + * trans.keyIndex = keyIndex; + * trans.msgIn = (uint32_t *) ecbExample.msgOut; + * trans.msgOut = (uint32_t *) ecbExample.clearText; + * + * // Zero original clear text before decrypting the cypher text into the ecbExample.clearText array + * memset(ecbExample.clearText, 0x0, AES_ECB_LENGTH); + * + * // Decrypt the plaintext with AES ECB + * status = CryptoCC26XX_transact(handle, (CryptoCC26XX_Transaction *) &trans); + * if(status != CRYPTOCC26XX_STATUS_SUCCESS){ + * System_abort("Encryption failed."); + * } + * + * CryptoCC26XX_releaseKey(handle, &keyIndex); + * @endcode + * + * + * ### AES CCM operation # + * Perform a crypto and authentication operation with AES-CCM in ::CRYPTOCC26XX_MODE_BLOCKING. + * + * @code + * #define macLength (4) + * #define clearTextLength (16) + * #define cipherTextLength (macLength + clearTextLength) + * #define nonceLength (12) + * #define aadLength (14) + * + * // Holds the AES-CCM setup for this example + * typedef struct + * { + * uint8_t key[16]; // A 128 Bit AES key + * CryptoCC26XX_KeyLocation keyLocation; // One of 8 key locations in the hardware + * uint8_t clearAndCipherText[cipherTextLength]; // Holds the cleartext before, and the ciphertext + * // after the encryption operation. + * // Ciphertext = encrypted text + message authentication code (MAC). + * uint8_t nonce[nonceLength]; // A value that is used only once (cryptographic term 'nonce') + * uint8_t header[aadLength]; // A header that is not encrypted but is authenticated in the operation (AAD). + * uint8_t verificationMAC[macLength]; // Location that the recalculated and encrypted MAC is stored during decryption. + * } AesCcmExample; + * + * AesCcmExample ccmSetup = + * { + * .key = { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, + * 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }, + * .keyLocation = CRYPTOCC26XX_KEY_0, + * .clearAndCipherText = { 't','h','i','s','i','s','a','p','l','a','i','n','t','e','x','t','0','0','0','0' }, + * .nonce = { 't','h','i','s','i','s','a','n','o','n','c','e' }, + * .header = { 't','h','i','s','i','s','a','h','e','a','d','e','r','1' } + * }; + * + * CryptoCC26XX_Handle handle; + * int32_t keyIndex; + * CryptoCC26XX_AESCCM_Transaction trans; + * int32_t status; + * + * // Initialize Crypto driver structures + * CryptoCC26XX_init(); + * + * // Open the crypto hardware with non-exclusive access and default parameters. + * handle = CryptoCC26XX_open(Board_CRYPTO0, false, NULL); + * if (handle == NULL) { + * System_abort("CryptoCC26XX did not open"); + * } + * + * // Allocate a key storage location in the hardware + * keyIndex = CryptoCC26XX_allocateKey(handle, ccmSetup.keyLocation, (const uint32_t *) ccmSetup.key); + * if (keyIndex == CRYPTOCC26XX_STATUS_ERROR) { + * System_abort("Key Location was not allocated."); + * } + * + * // Encrypt and authenticate the message + * CryptoCC26XX_Transac_init((CryptoCC26XX_Transaction *) &trans, CRYPTOCC26XX_OP_AES_CCM); + * trans.keyIndex = keyIndex; + * trans.authLength = macLength; + * trans.nonce = (char *) ccmSetup.nonce; + * trans.header = (char *) ccmSetup.header; + * trans.fieldLength = 3; + * trans.msgInLength = clearTextLength; + * trans.headerLength = aadLength; + * trans.msgIn = (char *) &(ccmSetup.clearAndCipherText[0]); // Message is encrypted in place + * trans.msgOut = (char *) &(ccmSetup.clearAndCipherText[clearTextLength]); // MAC will be written to this position + * status = CryptoCC26XX_transact(handle, (CryptoCC26XX_Transaction *) &trans); + * if (status != CRYPTOCC26XX_STATUS_SUCCESS) { + * System_abort("Encryption and signing failed."); + * } + * + * // Decrypt and authenticate message + * CryptoCC26XX_Transac_init((CryptoCC26XX_Transaction *) &trans, CRYPTOCC26XX_OP_AES_CCMINV); + * trans.keyIndex = keyIndex; + * trans.authLength = macLength; + * trans.nonce = (char *) ccmSetup.nonce; + * trans.header = (char *) ccmSetup.header; + * trans.fieldLength = 3; + * trans.msgInLength = cipherTextLength; + * trans.headerLength = aadLength; + * trans.msgIn = (char *) &(ccmSetup.clearAndCipherText[0]); // Message is decrypted in place + * trans.msgOut = (char *) ccmSetup.verificationMAC; + * + * // Do AES-CCM decryption and authentication + * status = CryptoCC26XX_transact(handle, (CryptoCC26XX_Transaction *) &trans); + * if(status != CRYPTOCC26XX_STATUS_SUCCESS){ + * System_abort("Decryption and authentication failed."); + * } + * + * // Release the key location + * status = CryptoCC26XX_releaseKey(handle, &keyIndex); + * if (status != CRYPTOCC26XX_STATUS_SUCCESS) { + * System_abort("Key release was not successful."); + * } + * + * @endcode + * + * # Instrumentation # + * The CryptoCC26XX driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ------------------------------------------ | + * Diags_USER1 | Basic CryptoCC26XX operations performed | + * Diags_USER2 | Detailed CryptoCC26XX operations performed | + * + * ============================================================================ + */ + +#ifndef ti_drivers_crypto_CryptoCC26XX__include +#define ti_drivers_crypto_CryptoCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(driverlib/crypto.h) + +#if DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 + #warning "This driver is deprecated for the CC26x2 and CC13x2 families.\ + It is superceded by AESECB and AESCCM." +#endif + +/** + * @addtogroup Crypto_STATUS + * CryptoCC26XX_STATUS_* macros are command codes only defined in the + * CryptoCC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add CryptoCC26XX_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup Crypto_CMD + * CryptoCC26XX_CMD_* macros are command codes only defined in the + * CryptoCC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add CryptoCC26XX_CMD_* macros here */ + +/** @}*/ + +#define CRYPTOCC26XX_TIMEOUT 20 /*!< Timeout Return Code */ + +#define CRYPTOCC26XX_STATUS_SUCCESS 0 /*!< Success Return Code */ +#define CRYPTOCC26XX_STATUS_ERROR -1 /*!< Error Return Code */ +#define CRYPTOCC26XX_STATUS_UNDEFINEDCMD -2 /*!< Command Undefined Return Code */ + +#define CRYPTOCC26XX_OP_AES_CCM_ENCRYPT 0 /*!< AES-CCM encryption of both AAD and plain text */ +#define CRYPTOCC26XX_OP_AES_CCM_ENCRYPT_AAD_ONLY 1 /*!< AES-CCM authentication of ADD only */ +#define CRYPTOCC26XX_OP_AES_CCM_DECRYPT 2 /*!< AES-CCM decryption of both AAD and plain text and verification of both */ +#define CRYPTOCC26XX_OP_AES_CCM_DECRYPT_AAD_ONLY 3 /*!< AES-CCM verification of ADD only */ +#define CRYPTOCC26XX_OP_AES_ECB_ENCRYPT 4 /*!< AES-ECB encryption */ +#define CRYPTOCC26XX_OP_AES_ECB_DECRYPT 5 /*!< AES-ECB decryption */ +#define CRYPTOCC26XX_OP_AES_CBC_ENCRYPT 6 /*!< AES-CBC encryption */ +#define CRYPTOCC26XX_OP_AES_CBC_DECRYPT 7 /*!< AES-CBC decryption */ + +/* Deprecated operation mode names */ +#define CRYPTOCC26XX_OP_AES_CCM CRYPTOCC26XX_OP_AES_CCM_ENCRYPT +#define CRYPTOCC26XX_OP_AES_CCM_NOCRYPT CRYPTOCC26XX_OP_AES_CCM_ENCRYPT_AAD_ONLY +#define CRYPTOCC26XX_OP_AES_CCMINV CRYPTOCC26XX_OP_AES_CCM_DECRYPT +#define CRYPTOCC26XX_OP_AES_CCMINV_NOCRYPT CRYPTOCC26XX_OP_AES_CCM_DECRYPT_AAD_ONLY +#define CRYPTOCC26XX_OP_AES_ECB CRYPTOCC26XX_OP_AES_ECB_ENCRYPT +#define CRYPTOCC26XX_OP_AES_ECB_NOCRYPT CRYPTOCC26XX_OP_AES_ECB_DECRYPT + + +#include +#include + +/*! + * @brief A handle that is returned from a CryptoCC26XX_open() call. + */ +typedef struct CryptoCC26XX_Config *CryptoCC26XX_Handle; + +/*! + * @brief CryptoCC26XX Mode Settings + * + * This enum defines the read and write modes for the + * configured CryptoCC26XX. + */ +typedef enum CryptoCC26XX_Mode { + /*! + * Uses a semaphore to block while data is being sent. Context of the call + * must be a Task. + */ + CRYPTOCC26XX_MODE_BLOCKING, + + /*! + * Will return when the operation has finished. Call can be made from + * hwi and swi context. + */ + CRYPTOCC26XX_MODE_POLLING +} CryptoCC26XX_Mode; + +/*! + * @brief CryptoCC26XX Operation Type + * + * This type holds the CryptoCC26XX operation. + * + * Currently supported types are + * + * | Encryption | Decryption | + * |-----------------------------------------------|-----------------------------------------------| + * | ::CRYPTOCC26XX_OP_AES_CCM_ENCRYPT | ::CRYPTOCC26XX_OP_AES_CCM_DECRYPT | + * | ::CRYPTOCC26XX_OP_AES_CCM_ENCRYPT_AAD_ONLY | ::CRYPTOCC26XX_OP_AES_CCM_DECRYPT_AAD_ONLY | + * | ::CRYPTOCC26XX_OP_AES_ECB_ENCRYPT | ::CRYPTOCC26XX_OP_AES_ECB_DECRYPT | + * | ::CRYPTOCC26XX_OP_AES_CBC_ENCRYPT | ::CRYPTOCC26XX_OP_AES_CBC_DECRYPT | + */ +typedef uint8_t CryptoCC26XX_Operation; + +/*! + * @brief CryptoCC26XX Key Store Location + * + * This enumeration defines the possible key locations in CryptoCC26XX. + * + */ +typedef enum CryptoCC26XX_KeyLocation { + CRYPTOCC26XX_KEY_0 = 0, + CRYPTOCC26XX_KEY_1, + CRYPTOCC26XX_KEY_2, + CRYPTOCC26XX_KEY_3, + CRYPTOCC26XX_KEY_4, + CRYPTOCC26XX_KEY_5, + CRYPTOCC26XX_KEY_COUNT, + CRYPTOCC26XX_KEY_ANY, +} CryptoCC26XX_KeyLocation; + +/*! + * @brief CryptoCC26XX Parameters + */ +typedef struct CryptoCC26XX_Params { + uint32_t timeout; /*!< Timeout for read semaphore */ +} CryptoCC26XX_Params; + +/*! + * @brief CryptoCC26XX Key + * + * This holds allocation information for the keys in the key store. + */ +typedef uint8_t CryptoCC26XX_KeyStore; + +/*! + * @brief CryptoCC26XX Transaction + * + * This structure defines the nature of a general crypto transaction. An operation + * specific object, e.g. CryptoCC26XX_AESCCM_Transaction, must be used by the clients. + * All transaction must be typecasted to this common type when calling the transact + * functions. The first data of all transactions must hold a type field indicating + * which type of transaction to be performed. + */ +typedef struct CryptoCC26XX_Transaction { + CryptoCC26XX_Operation opType; /*!< The type of the crypto operation */ + CryptoCC26XX_Mode mode; /*!< The mode of current transaction */ + uint8_t data[]; /*!< A void pointer to rest of transaction (transac. specific) */ +} CryptoCC26XX_Transaction; + +/*! + * @brief CryptoCC26XX AES-CCM Transaction + * + * The Counter with CBC-MAC (CCM) mode of operation is a generic + * authenticated encryption block cipher mode. It can be used with + * any 128-bit block cipher. + * AES-CCM combines CBC-MAC with an AES block cipher. + * + * AES-CCM encryption has the following inputs and outputs: + * + * + * + * + * + * + * + * + * + * + * + *
AES-CCM input and output parameters
EncryptionDecryption
Input
Shared AES key Shared AES key
NonceNonce
CleartextCiphertext (encrypted cleartext + MAC)
AAD (optional)AAD (optional)
Output
Ciphertext (encrypted cleartext + MAC)Cleartext
+ * + * The AES key is a shared secret between the two parties and has a length + * of 128 Bit. The key is stored in the dedicated RAM of the AES hardware + * unit before the crypto operation. + * + * The nonce is generated by the party performing the authenticated + * encryption operation. Within the scope of any authenticated + * encryption key, the nonce value must be unique. That is, the set of + * nonce values used with any given key must not contain any duplicate + * values. Using the same nonce for two different messages encrypted + * with the same key destroys the security properties. + * + * The optional AAD is authenticated, but not encrypted. Thus, the AAD + * is not included in the AES-CCM output. It can be used to authenticate + * packet headers for transport layer security. + * + * After the encryption operation, the ciphertext contains the encrypted + * data and the message authentication code (MAC). The MAC can be seen as an + * encrypted fingerprint of the message header and content. + * + * AES-CCM works in both ways: encryption and decryption. When a message is + * decrypted, then ciphertext, AAD and nonce are used as inputs while + * the output comprises the cleartext only. The decryption operation is + * successful, when the received ciphertext, the nonce and the AAD + * can reproduce the containing MAC. + * + * The CryptoCC26XX_AESCCM_Transaction structure defines all necessary + * parameters for a AES-CCM transaction. + */ +typedef struct CryptoCC26XX_AESCCM_Transaction { + CryptoCC26XX_Operation opType; /*!< The type of the crypto operation */ + CryptoCC26XX_Mode mode; /*!< The mode of current transaction. Set by transact function. */ + uint8_t keyIndex; /*!< The key store index to be used */ + uint8_t authLength; /*!< Is the the length of the authentication field */ + /*!< 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. */ + char *nonce; /*!< A pointer to a nonce. It must satisfy the equation 15 = q + n, + * where q is the fieldLength and n is the length of the nonce. + * + * The minimum size of the array containing the nonce is 12 bytes. + * When using nonces of length < 12 bytes, the nonce must be zero-padded + * to 12 bytes. The driverlib implementation in ROM was written + * with 12 and 13-byte nonces in mind. It constructs the IV's + * internally and hence copies either 12 or 13 bytes into another buffer. + * Providing a nonce buffer with less than 12 bytes would result in + * whatever is after the nonce in memory being incorrectly copied + * into the IV's. + * + * As long as the correct fieldLength is set for the < 12-bytes nonce, + * the correct nonce-length will be used. + * + * Valid nonce lengths are {7, 8, 9, 10, 11, 12, 13}. + */ + char *msgIn; /*!< + * - Encryption: A pointer to the octet string input message and after the transaction, + * the location of the encrypted cleartext. The cleatext is encrypted in place. + * - Decryption: A pointer to the encrypted ciphertext composed of the encrypted cleartext + * concatenated with the encrypted message authentication code. + */ + char *header; /*!< The Additional Authentication Data (AAD). This header is authenticated but not encrypted. */ + void *msgOut; /*!< A pointer to where the encrypted CBC-MAC shall be written to. + * - Encryption: It is recommended to set this to msgIn + msgInLength. The cyphertext sent out + * must be the concatenation of the encrypted message and encrypted MAC anyway. + * - Decyption: Do NOT set msgOut to the same location as the received MAC in the + * cyphertext within msgIn! Doing this effectively disables verification. + */ + uint8_t fieldLength; /*!< This parameter specifies the size in bytes of the message length field. + * (Not the length of the message itself!) + * + * It sets the maximum length of the message + * according to p < 2^(8*q) where p is the message length and q is the fieldLength. + * + * It must satisfy the equation 15 = q + n where q is the fieldLength and n is the + * length of the nonce. + * + * Valid values are {2, 3, 4, 5, 6, 7, 8}. + */ + uint16_t msgInLength; /*!< - Encryption: The length of the cleartext. + - Decryption: The length of the ciphertext. */ + uint16_t headerLength; /*!< The length of the header in octets */ +} CryptoCC26XX_AESCCM_Transaction; + +/*! + * @brief CryptoCC26XX AES-CBC Transaction + * + * This structure defines the nature of the AES-CBC transaction. An object of this structure must + * be initialized by calling CryptoCC26XX_Transac_init(). + */ +typedef struct CryptoCC26XX_AESCBC_Transaction { + CryptoCC26XX_Operation opType; /*!< The type of the crypto operation */ + CryptoCC26XX_Mode mode; /*!< The mode of current transaction. Set by transact function. */ + uint8_t keyIndex; /*!< The key store index to be used */ + void *nonce; /*!< A pointer to 16 byte Nonce. */ + void *msgIn; /*!< A pointer to the octet string input message */ + void *msgOut; /*!< A pointer to the output message location */ + uint16_t msgInLength; /*!< The length of the message */ +} CryptoCC26XX_AESCBC_Transaction; + +/*! + * @brief CryptoCC26XX AES-ECB Transaction + * + * This structure defines the nature of the AES-ECB transaction. An object of this structure must + * be initialized by calling CryptoCC26XX_Transac_init(). + */ +typedef struct CryptoCC26XX_AESECB_Transaction { + CryptoCC26XX_Operation opType; /*!< The type of the crypto operation */ + CryptoCC26XX_Mode mode; /*!< The mode of current transaction. Set by transact function. */ + uint8_t keyIndex; /*!< The key store index to be used. */ + void *msgIn; /*!< A poiner to the octet string input message */ + void *msgOut; /*!< A pointer to the output message location */ +} CryptoCC26XX_AESECB_Transaction; + +/*! + * @brief CryptoCC26XX Hardware Attributes + * + * These fields, with the exception of intPriority, + * are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC26XXWare these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * intPriority is the Crypto peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * + * A sample structure is shown below: + * @code + * const CryptoCC26XX_HWAttrs cryptoCC26XXHWAttrs[] = { + * { + * .baseAddr = CRYPTO_BASE, + * .powerMngrId = PERIPH_CRYPTO, + * .intNum = INT_CRYPTO, + * .intPriority = (~0) + * } + * }; + * @endcode + */ +typedef struct CryptoCC26XX_HWAttrs { + /*! Crypto Peripheral's base address */ + uint32_t baseAddr; + /*! Crypto Peripheral's power manager ID */ + int powerMngrId; + /*! Crypto Peripheral's interrupt vector */ + int intNum; + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; +} CryptoCC26XX_HWAttrs; + +/*! + * @brief CryptoCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct CryptoCC26XX_Object { + /* CryptoCC26XX control variables */ + int openCnt; /*!< Counting number of clients */ + uint32_t timeout; /*!< Timeout for encrypt/decrypt operation */ + CryptoCC26XX_KeyStore keyStore; /*!< Key store for Crypto */ + CryptoCC26XX_Transaction *currentTransact; /*!< Pointer to ongoing transaction */ + + /*! Crypto notification object */ + Power_NotifyObj cryptoNotiObj; + + /* CryptoCC26XX SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object */ +} CryptoCC26XX_Object; + +/*! @brief CryptoCC26XX Global Configuration */ +typedef struct CryptoCC26XX_Config { + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} CryptoCC26XX_Config; + +/*! + * @brief Function to closes a given CryptoCC26XX peripheral specified by the CryptoCC26XX + * handle. + * + * @pre CryptoCC26XX_open() had to be called first. + * Calling context: Task + * + * @param handle A CryptoCC26XX_Handle returned from CryptoCC26XX_open(). + * + * @return Returns CRYPTOCC26XX_STATUS_SUCCESS if successful, otherwise will return + * CRYPTOCC26XX_STATUS_ERROR. + * + * @sa CryptoCC26XX_open + */ +int CryptoCC26XX_close(CryptoCC26XX_Handle handle); + +/*! + * @brief Function to initialize CryptoCC26XX driver. + * Users of this module must call init(). + * Multiple users/libraries may call init(), though subsequent calls may be benign. + * + * @pre This function must be called before any other CryptoCC26XX driver APIs. + * Calling context: Task and Main. + * + */ +void CryptoCC26XX_init(void); + +/*! + * @brief Function to initialize a given CryptoCC26XX peripheral specified by the + * particular index value. The parameter specifies which mode the CryptoCC26XX + * will operate. + * + * @pre The CryptoCC26XX_Config structure must exist and be persistent before this + * function can be called. CryptoCC26XX has been initialized with CryptoCC26XX_init(). + * Calling context: Task. + * + * @param index Logical peripheral number indexed into the HWAttrs + * table. This is usually provided in the Board support + * file. + * + * @param exclusiveAccess Boolean flag to get exclusive access, if true all + * subsequent calls to CryptoCC26XX_open() will fail. + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return A CryptoCC26XX_Handle on success or a NULL on an error or if it has been + * already opened with exclusiveAccess set. + * + * @sa CryptoCC26XX_close(), CryptoCC26XX_init() + */ +CryptoCC26XX_Handle CryptoCC26XX_open(unsigned int index, bool exclusiveAccess, CryptoCC26XX_Params *params); + +/*! + * @brief Function to initialize the CryptoCC26XX_Params struct to its defaults. + * + * @pre Calling context: Hwi, Swi and Task. + * + * Defaults values are: + * timeout = BIOS_WAIT_FOREVER; + * + * @param params Parameter structure to initialize. + */ +void CryptoCC26XX_Params_init(CryptoCC26XX_Params *params); + +/*! + * @brief Function to initialize the CryptoCC26XX_Transaction struct to its defaults. + * + * @pre Calling context: Hwi, Swi and Task. + * + * @param trans Transaction structure to initialize. + * + * @param opType Cryto Operation type to perform in the transaction. See + * ::CryptoCC26XX_Operation for currently supported types. + */ +void CryptoCC26XX_Transac_init(CryptoCC26XX_Transaction *trans, CryptoCC26XX_Operation opType); + +/*! + * @brief Function that allocates key, writes key into key store RAM and returns + * a handle to CryptoCC26XX Key. + * + * This function tries to allocate the wanted key location, initiates an operation to + * write a key into one of the keystore RAM entries and returns a key index integer + * to the calling client. The allocated key index shall be used when building a + * transaction data object, e.g. ::CryptoCC26XX_AESCCM_Transaction.keyIndex. + * The function blocks the task calling it until the crypto hardware is available. + * + * @pre CryptoCC26XX_open() has to be called first. + * Calling context: Hwi, Swi and Task. + * + * @param handle A CryptoCC26XX_Handle returned by CryptoCC26XX_open(). + * + * @param keyLocation The key location in key store to allocate. If set to + * CRYPTOCC26XX_KEY_ANY, the first available key, starting + * from highest index, will be allocated. + * + * @param keySrc A pointer to buffer containing key to be written. If this pointer is NULL, + * the key store will be reserved for the handle, but no key will be written to the key store. + * + * @return An integer representing the index allocated in key store or a + * CRYPTOCC26XX_STATUS_ERROR on an error. + * + * @sa CryptoCC26XX_releaseKey() + * @sa CryptoCC26XX_loadKey() + */ +int CryptoCC26XX_allocateKey(CryptoCC26XX_Handle handle, CryptoCC26XX_KeyLocation keyLocation, const uint32_t *keySrc); + + +/*! + * @brief Function that writes a given key into a key store + * + * This function loads a key into a keystore without needing to release the key store and + * re-allocate it using CryptoCC26XX_releaseKey() and CryptoCC26XX_allocateKey(). + * If called in task context, the function blocks for as long as specified in the timeout. + * If called in Swi or Hwi context, the function returns an error immediately if it cannot + * acquire the semaphore. + * + * @pre CryptoCC26XX_open() and CryptoCC26XX_allocateKey() have to be called first. + * Calling context: Hwi, Swi and Task. + * + * @param handle A CryptoCC26XX_Handle returned by CryptoCC26XX_open(). + * + * @param keyIndex A key index returned by a previous call to CryptoCC26XX_allocateKey(). + * + * @param keySrc A pointer to buffer containing a key. + * + * @return An integer representing success (::CRYPTOCC26XX_STATUS_SUCCESS) or an error (::CRYPTOCC26XX_STATUS_ERROR). + * + * @sa CryptoCC26XX_releaseKey() + * @sa CryptoCC26XX_loadKey() + */ +int CryptoCC26XX_loadKey(CryptoCC26XX_Handle handle, int keyIndex, const uint32_t *keySrc); + +/*! + * @brief Function that releases the specified CryptoCC26XX Key. + * + * This function releases the crypto key, so it can be used by other clients. + * + * @pre Driver must have been opened and the key must have been allocated first. + * Calling context: Hwi, Swi and Task. + * + * @param handle A CryptoCC26XX_Handle returned by CryptoCC26XX_open(). + * + * @param keyIndex A pointer to the keyIndex to be released. + * + * @return Returns CRYPTOCC26XX_STATUS_SUCCESS if successful, otherwise will return + * CRYPTOCC26XX_STATUS_ERROR. + * + * @sa CryptoCC26XX_allocateKey() + */ +int CryptoCC26XX_releaseKey(CryptoCC26XX_Handle handle, int *keyIndex); + +/*! + * @brief Function to do a Crypto operation (encryption or decryption) in blocking mode. + * + * This function initiates a blocking crypto operation. + * + * CryptoCC26XX_transact() will block task execution until all + * the data has been encrypted or decrypted, a task switch could be done + * when pending on a semaphore. + * + * @pre Driver must have been opened and a key must have been allocated first. + * Calling context: Task. + * + * @param handle A CryptoCC26XX_Handle returned by CryptoCC26XX_open(). + * + * @param transaction Pointer to a transaction descriptor. + * + * @return Returns CRYPTOCC26XX_STATUS_SUCCESS if successful, error code if not. + * + * @sa CryptoCC26XX_open(), CryptoCC26XX_allocateKey(), CryptoCC26XX_transactPolling() + */ +int CryptoCC26XX_transact(CryptoCC26XX_Handle handle, CryptoCC26XX_Transaction *transaction); + +/*! + * @brief Function to do a Crypto transaction operation (encryption or decryption) in polling mode. + * + * This function initiates a polling crypto operation. + * + * CryptoCC26XX_transactPolling() blocks task execution and does not pend + * on a semaphore, consequently no task switch will be done as a result of pending. + * + * @pre Driver must have been opened and a key must have been allocated first. + * Calling context: Hwi, Swi and Task. + * + * @param handle An CryptoCC26XX_Handle returned by CryptoCC26XX_open(). + * + * @param transaction Pointer to a transaction descriptor. + * + * @return Returns CRYPTOCC26XX_STATUS_SUCCESS if successful, error code if not. + * + * @sa CryptoCC26XX_open(), CryptoCC26XX_allocateKey(), CryptoCC26XX_transact() + */ +int CryptoCC26XX_transactPolling(CryptoCC26XX_Handle handle, CryptoCC26XX_Transaction *transaction); + +/*! + * @brief Function to do a Crypto transaction operation (encryption or decryption) in + * callback mode. Currently not supported. + * + * This function initiates a callback crypto operation. + * + * CryptoCC26XX_transactCallback() will continue task execution (i.e. does not pend + * on a semaphore). A callback function must be defined, and will be called when the + * crypto operation has finished. + * + * @pre Driver must have been opened and a key must have been allocated first. + * Calling context: Hwi, Swi and Task. + * + * @param handle An CryptoCC26XX_Handle returned by CryptoCC26XX_open(). + * + * @param transaction Pointer to a transaction descriptor. + * + * @return Returns CRYPTOCC26XX_STATUS_SUCCESS if successful, error code if not. + * + * @note Currently not supported. Will replace CryptoCC26XX_transactPolling in the future. + * + * @sa CryptoCC26XX_open(), CryptoCC26XX_allocateKey(), CryptoCC26XX_transact() + */ +int CryptoCC26XX_transactCallback(CryptoCC26XX_Handle handle, CryptoCC26XX_Transaction *transaction); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_crypto_CryptoCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h new file mode 100644 index 0000000..531a8a9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CryptoKey.h + * + * @brief The CryptoKey type is an opaque representation of a cryptographic key. + * + * @warning This is a beta API. It may change in future releases. + * + * Cryptographic keying material may be stored on an embedded system multiple ways. + * - plaintext: in plaintext in flash or RAM + * - keyblob: in encrypted form in flash or RAM + * - key store: in a dedicated hardware database whose entries can not be directly + * read out. + * + * Each storage option requires different approaches to handling the keying material + * when performing a crypto operation. In order to separate these concerns from + * the API of the various crypto drivers available with TI-RTOS, the CryptoKey + * type abstracts away from these details. It does not contain any cryptographic + * keying material itself but instead contains the details necessary for drivers to use the + * keying material. The driver implementation handles preparing and moving the keying + * material as necessary to perform the desired crypto operation. + * + * The same CryptoKey may be passed to crypto APIs of different modes subject to + * restrictions placed on the key by their storage types. Plaintext keys may be used + * without restriction while key store and keyblob keys have their permitted uses + * restricted when the keying material is loaded or the keyblob is encrypted respectively. + * These restrictions are specified in a CryptoKey_SecurityPolicy that is device-specific + * and depends on the hardware capability of the device. + * + * An application should never access a field within a CryptoKey struct itself. + * Where needed, helper functions are provided to do so. + * + * Before using a CryptoKey in another crypto API call, it must be initialized + * with a call to one of the initialization functions. + * - CryptoKeyPlaintext_initKey() + * - CryptoKeyPlaintext_initBlankKey() + * - CryptoKeyKeyStore_initKey() + * - CryptoKeyKeyStore_initBlankKey() + * - CryptoKeyKeyBlob_initKey() + * - CryptoKeyKeyBlob_initBlankKey() + * + * The keyblob and keystore CryptoKeys may be used to create a keyblob or + * load a key into a key store after their respective _init call. + * + * CryptoKeys can be initialized "blank", without keying material but with an empty buffer + * or key store entry, to encode the destination of a key to be created in the + * future. This way, keys may be generated securely within a key store + * for example and never even be stored in RAM temporarily. + * + * Not all devices support all CryptoKey functionality. This is hardware-dependent. + * + */ + +#ifndef ti_drivers_cryptoutils_cyptokey_CryptoKey__include +#define ti_drivers_cryptoutils_cyptokey_CryptoKey__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/*! + + */ + + /** + * @defgroup CryptoKey_CONTROL Status codes + * These CryptoKey macros are reservations for CryptoKey.h + * @{ + */ + + +/*! + * Common CryptoKey_control status code reservation offset. + * CryptoKey driver implementations should offset status codes with + * CryptoKey_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define CryptoKeyXYZ_STATUS_ERROR0 CryptoKey_STATUS_RESERVED - 0 + * #define CryptoKeyXYZ_STATUS_ERROR1 CryptoKey_STATUS_RESERVED - 1 + * #define CryptoKeyXYZ_STATUS_ERROR2 CryptoKey_STATUS_RESERVED - 2 + * @endcode + */ +#define CryptoKey_STATUS_RESERVED (-32) + +/** + * @defgroup CryptoKey_STATUS Status Codes + * CryptoKey_STATUS_* macros are general status codes returned by CryptoKey_control() + * @{ + * @ingroup CryptoKey_CONTROL + */ + +/*! + * @brief Successful status code + * + * CryptoKey_control() returns CryptoKey_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define CryptoKey_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code + * + * CryptoKey_control() returns CryptoKey_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define CryptoKey_STATUS_ERROR (-1) + +/*! + * @brief Returned if the encoding of a CryptoKey is not a CryptoKey_Encoding value + * + * CryptoKey_control() returns CryptoKey_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define CryptoKey_STATUS_UNDEFINED_ENCODING (-2) + + +/** @}*/ + +/** @}*/ + +/*! + * @brief List of the different types of CryptoKey. + * + */ +typedef enum CryptoKey_Encoding_ { + CryptoKey_PLAINTEXT = 1 << 1, + CryptoKey_BLANK_PLAINTEXT = 1 << 2, + CryptoKey_KEYSTORE = 1 << 3, + CryptoKey_BLANK_KEYSTORE = 1 << 4, + CryptoKey_KEYBLOB = 1 << 5, + CryptoKey_BLANK_KEYBLOB = 1 << 6, +} CryptoKey_Encoding; + +/*! + * @brief Plaintext CryptoKey datastructure. + * + * This structure contains all the information necessary to access keying material stored + * in plaintext form in flash or RAM. + */ +typedef struct CryptoKey_Plaintext_ { + uint8_t *keyMaterial; + uint16_t keyLength; +} CryptoKey_Plaintext; + +/*! + * @brief Key store CryptoKey datastructure. + * + * This structure contains all the information necessary to access keying material stored + * in a dedicated key store or key database with memory access controls. + */ +typedef struct CryptoKey_KeyStore_ { + void* keyStore; + uint16_t keyLength; + uint32_t keyIndex; +} CryptoKey_KeyStore; + +/*! + * @brief Keyblob CryptoKey datastructure. + * + * This structure contains all the information necessary to access keying material stored + * in an encrypted structure in flash or RAM. + */ +typedef struct CryptoKey_KeyBlob_ { + uint8_t *keyBlob; + uint32_t keyBlobLength; +} CryptoKey_KeyBlob; + +/*! + * @brief CryptoKey datastructure. + * + * This structure contains a CryptoKey_Encoding and one of + * - CryptoKey_Plaintext + * - CryptoKey_KeyStore + * - CryptoKey_KeyBlob + */ +typedef struct CryptoKey_ { + CryptoKey_Encoding encoding; + union { + CryptoKey_Plaintext plaintext; + CryptoKey_KeyStore keyStore; + CryptoKey_KeyBlob keyBlob; + } u; +} CryptoKey; + + +/*! + * @brief Structure that specifies the restrictions on a CryptoKey + * + * This structure is device-specific and declared here in incomplete form. + * The structure is fully defined in CryptoKeyDEVICE.h. This creates a link-time binding + * when using the structure with key store or keyblob functions. If the instance + * of the CryptoKey_SecurityPolicy is kept in a device-specific application-file, + * the gernic application code may still use references to it despite being + * an incomplete type in the generic application file at compile time. + */ +typedef struct CryptoKey_SecurityPolicy_ CryptoKey_SecurityPolicy; + +/*! + * @brief Gets the key type of the CryptoKey + * + * @param [in] keyHandle Pointer to a CryptoKey + * @param [out] keyType Type of the CryptoKey + * + * @return Returns a status code + */ +int_fast16_t CryptoKey_getCryptoKeyType(CryptoKey *keyHandle, CryptoKey_Encoding *keyType); + +/*! + * @brief Wheather the CryptoKey is 'blank' or represents valid keying material + * + * @param [in] keyHandle Pointer to a CryptoKey + * @param [out] isBlank Wheather the CryptoKey is 'blank' or not + * + * @return Returns a status code + */ +int_fast16_t CryptoKey_isBlank(CryptoKey *keyHandle, bool *isBlank); + +/*! + * @brief Marks a CryptoKey as 'blank'. + * + * The CryptoKey will be unlinked from any previously connected keying material + * + * @param [in] keyHandle Pointer to a CryptoKey + * + * @return Returns a status code + */ +int_fast16_t CryptoKey_markAsBlank(CryptoKey *keyHandle); + +/*! + * @brief Function to initialize the CryptoKey_SecurityPolicy struct to its defaults + * + * This will zero-out all fields that cannot be set to safe defaults + * + * @param [in] policy Pointer to a CryptoKey_SecurityPolicy + * + * @return Returns a status code + */ +int_fast16_t CryptoKey_initSecurityPolicy(CryptoKey_SecurityPolicy *policy); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_cyptokey_CryptoKey__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h new file mode 100644 index 0000000..023299f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CryptoKeyPlaintext.h + * + * @warning This is a beta API. It may change in future releases. + * + * # Overview # + * This file contains the APIs to initialize and access plaintext CryptoKeys. + * Plaintext CryptoKeys point to keying material stored in flash or RAM and + * are not subject to enforced usage restrictions. That only means that calling + * a function that requires an assymmetric public key with a symmetric key will + * not return an error. It will likely not yield the desired results. + * + * # Usage # + * + * Plaintext keys are the simplest of the CryptoKeys. All they do is store the length + * of and a pointer to the keying material. Their use is hence simple as well. After + * calling the initialization function, the CryptoKey may be used in any of the + * crypto operation APIs that take a CryptoKey as an input. + * + * @code + * + * uint8_t keyingMaterial[16]; + * CryptoKey cryptoKey; + * + * // Initialise the CryptoKey + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Use the CryptoKey in another crypto operation + * + * @endcode + * + */ + +#ifndef ti_drivers_cryptoutils_cyptokey_CryptoKeyPlaintext__include +#define ti_drivers_cryptoutils_cyptokey_CryptoKeyPlaintext__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initializes a CryptoKey type + * + * @param [in] keyHandle Pointer to a CryptoKey which will be initialized to type CryptoKey_PLAINTEXT + * and ready for use + * @param [in] key Pointer to keying material + * + * @param [in] keyLength Length of keying material in bytes + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_initKey(CryptoKey *keyHandle, uint8_t *key, size_t keyLength); + + +/*! + * @brief Initializes an empty plaintext CryptoKey type + * + * @param [in] keyHandle Pointer to a CryptoKey which will be initialized to type + * CryptoKey_BLANK_PLAINTEXT + * + * @param [in] keyLocation Pointer to location where plaintext keying material can be stored + * + * @param [in] keyLength Length of keying material, in bytes + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_initBlankKey(CryptoKey *keyHandle, uint8_t *keyLocation, size_t keyLength); + +/*! + * @brief Gets the length of a plaintext key + * + * @param [in] keyHandle Pointer to a plaintext CryptoKey + * + * @param [out] length Length of the keying material, in bytes + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_getKeyLength(CryptoKey *keyHandle, size_t *length); + +/*! + * @brief Sets the CryptoKey keyMaterial pointer + * + * Updates the key location for a plaintext CryptoKey. + * Does not modify data at the pointer location. + * + * @param [in] keyHandle Pointer to a plaintext CryptoKey who's key data pointer will be modified + * + * @param [in] location Pointer to key data location + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_setKeyLocation(CryptoKey *keyHandle, uint8_t *location); + + +/*! + * @brief Gets the length of a plaintext key + * + * @param [in] keyHandle Pointer to a CryptoKey + * + * @param [out] length Length value will be updated to CryptoKey length, in bytes + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_getKeyLength(CryptoKey *keyHandle, size_t *length); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_cyptoKey_CryptoKeyPlaintext__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintextCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintextCC26XX.c new file mode 100644 index 0000000..26b2b85 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintextCC26XX.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include +#include + +#include + +/*! + * \brief Initializes a CryptoKey type + * + * + * @param[in] keyHandle Pointer to a CryptoKey which will be initialized to type CryptoKey_PLAINTEXT + * and ready for use + * @param[in] key Pointer to key value + * @param[in] keyLength Length of key, in bytes + * + */ +int_fast16_t CryptoKeyPlaintext_initKey(CryptoKey *keyHandle, uint8_t *key, size_t keyLength){ + keyHandle->encoding = CryptoKey_PLAINTEXT; + keyHandle->u.plaintext.keyMaterial = key; + keyHandle->u.plaintext.keyLength = keyLength; + + return CryptoKey_STATUS_SUCCESS; +} + + +/*! + * \brief Initializes an empty plaintext CryptoKey type + * + * + * @param[in] keyHandle Pointer to a CryptoKey which will be initialized to type + * CryptoKey_BLANK_PLAINTEXT + * @param[in] keyLocation Pointer to location where plaintext key can be stored + * @param[in] keyLength Length of array allocated at key, in bytes + * + */ +int_fast16_t CryptoKeyPlaintext_initBlankKey(CryptoKey *keyHandle, uint8_t *keyLocation, size_t keyLength){ + return CryptoKeyPlaintext_initKey(keyHandle, keyLocation, keyLength); +} + + + +/*! + * \brief Sets the CryptoKey.keyLocation pointer + * + * Updates the key location for a plaintext CryptoKey. + * Does not modify data at the pointer location. + * + * @param[in] keyHandle Pointer to a plaintext CryptoKey who's key data pointer will be modified + * @param[in] location Pointer to key data location + */ +int_fast16_t CryptoKeyPlaintext_setKeyLocation(CryptoKey *keyHandle, uint8_t *location){ + keyHandle->u.plaintext.keyMaterial = location; + + return CryptoKey_STATUS_SUCCESS; +} + + +/*! + * \brief Gets the length of a plaintext key + * + * @param[in] keyHandle Pointer to a plaintext CryptoKey + * @param[in] length Length value will be updated to CryptoKey length, in bytes + */ +int_fast16_t CryptoKeyPlaintext_getKeyLength(CryptoKey *keyHandle, size_t *length){ + *length = keyHandle->u.plaintext.keyLength; + + return CryptoKey_STATUS_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/ecc/ECCParams.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/ecc/ECCParams.h new file mode 100644 index 0000000..61542f3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/ecc/ECCParams.h @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECCParams.h + * + * This file contains a common definition for eliptic curve structures used + * throughout the ECC based drivers. + */ + +#ifndef ti_drivers_cryptoutils_ecc_ECCParams__include +#define ti_drivers_cryptoutils_ecc_ECCParams__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include + +/* Error status codes for the utility functions */ + +/*! + * @brief Successful status code. + * + * Function return ECCParams_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define ECCParams_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return ECCParams_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define ECCParams_STATUS_ERROR (-1) + +/*! + * @brief Enumeration of curve equations supported. + * + * Elliptic curves can be expressed using multiple equations of polynomials over + * finite fields. + * All forms can be converted to one another using parameter substitution. + * Each curve has a default curve equations it was designed to use. + * + * Some curve implementations have restrictions on which algorithms and schemes + * they work with. For example, Curve25519 was explicitely designed with ECDH in mind. + * It only uses and yields the X coordinate of a point on the elliptic curve in common + * implementations. Some implementations do provide X and Y affine coordinates but most + * do not. + * Therefore, ECDSA and ECJPAKE do not have compatible implementations + * for Curve25519 on some devices as the Y coordinate is required by them. + * + * Check the header files of each device-specific implementation for information + * regarding curve-support for specific schemes on a device. + * + * | Name | Equation | + * |-------------------|-------------------------------| + * | Short Weierstrass | y^3 = x^2 + a*x + b mod p | + * | Montgomery | By^2 = x^3 + Ax^2 + x mod p | + * | Edwards | x^2 + y^2 = 1 + dx^2y^2 mod p | + * + */ +typedef enum ECCParams_CurveType_ { + ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS = 0, + ECCParams_CURVE_TYPE_MONTGOMERY, + ECCParams_CURVE_TYPE_EDWARDS, +} ECCParams_CurveType; + +/*! + * + * @brief A structure containing the parameters of an elliptic curve in short Weierstrass form. + * + * Elliptical Curve Cryptography (ECC) prime curve. + * + * The equation used to define the curve is expressed in the short Weierstrass + * form y^3 = x^2 + a*x + b + * + */ +typedef struct ECCParams_CurveParams_ { + const ECCParams_CurveType curveType; + const size_t length; //!< Length of the curve in bytes. All other buffers have this length. + const uint8_t *prime; //!< The prime that defines the field of the curve. + const uint8_t *order; //!< Order of the curve. + const uint8_t *a; //!< Coefficient a of the equation. + const uint8_t *b; //!< Coefficient b of the equation. + const uint8_t *generatorX; //!< X coordinate of the generator point of the curve. + const uint8_t *generatorY; //!< Y coordinate of the generator point of the curve. +} +ECCParams_CurveParams; + + + +/* Short Weierstrass curves */ + +/*! + * + * @brief The NISTP224 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP224; + +/*! + * + * @brief The NISTP256 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP256; + +/*! + * + * @brief The NISTP384 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP384; + +/*! + * + * @brief The NISTP521 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP521; + +/*! + * + * @brief The BrainpoolP256R1 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_BrainpoolP256R1; + +/*! + * + * @brief The BrainpoolP384R1 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_BrainpoolP384R1; + +/*! + * + * @brief The BrainpoolP512R1 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_BrainpoolP512R1; + + + +/* Montgomery curves */ + +/*! + * + * @brief The Curve25519 curve in Montgomery form. + * + */ +extern const ECCParams_CurveParams ECCParams_Curve25519; + + + +/* Edwards curves */ + +/* Utility functions */ + +/*! + * @brief Formats a CryptoKey to conform to Curve25519 private key requirements. + * + * Curve25519 has specific private key requirements specified by the curve definition. + * Specifically, the bottom three and the top bit may not be set and the second to + * last bit must be set. + * + * @param myPrivateKey An initialized CryptoKey describing the entropy for a + * Curve25519 private key. Platform-specific restrictions + * for the location of the keying material apply. Some + * implementations do not support modifying keying material + * in flash for example. + * + * @pre Initialize the CryptoKey with a 32-byte buffer in a compliant location. + */ +int_fast16_t ECCParams_FormatCurve25519PrivateKey(CryptoKey *myPrivateKey); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_ecc_ECCParams__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X2.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X2.c new file mode 100644 index 0000000..dcc4414 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X2.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ECCParamsCC26X2.c ======== + * + * This file contains structure definitions for various ECC curves for use + * on CC26X2 devices. + */ + +#include +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/pka.h) + +const ECCParams_CurveParams ECCParams_NISTP224 = { + .curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS, + .length = NISTP224_PARAM_SIZE_BYTES, + .prime = NISTP224_prime.byte, + .order = NISTP224_order.byte, + .a = NISTP224_a.byte, + .b = NISTP224_b.byte, + .generatorX = NISTP224_generator.x.byte, + .generatorY = NISTP224_generator.y.byte +}; + +const ECCParams_CurveParams ECCParams_NISTP256 = { + .curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS, + .length = NISTP256_PARAM_SIZE_BYTES, + .prime = NISTP256_prime.byte, + .order = NISTP256_order.byte, + .a = NISTP256_a.byte, + .b = NISTP256_b.byte, + .generatorX = NISTP256_generator.x.byte, + .generatorY = NISTP256_generator.y.byte +}; + +const ECCParams_CurveParams ECCParams_NISTP384 = { + .curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS, + .length = NISTP384_PARAM_SIZE_BYTES, + .prime = NISTP384_prime.byte, + .order = NISTP384_order.byte, + .a = NISTP384_a.byte, + .b = NISTP384_b.byte, + .generatorX = NISTP384_generator.x.byte, + .generatorY = NISTP384_generator.y.byte +}; + +const ECCParams_CurveParams ECCParams_NISTP521 = { + .curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS, + .length = NISTP521_PARAM_SIZE_BYTES, + .prime = NISTP521_prime.byte, + .order = NISTP521_order.byte, + .a = NISTP521_a.byte, + .b = NISTP521_b.byte, + .generatorX = NISTP521_generator.x.byte, + .generatorY = NISTP521_generator.y.byte +}; + +const ECCParams_CurveParams ECCParams_BrainpoolP256R1 = { + .curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS, + .length = BrainpoolP256R1_PARAM_SIZE_BYTES, + .prime = BrainpoolP256R1_prime.byte, + .order = BrainpoolP256R1_order.byte, + .a = BrainpoolP256R1_a.byte, + .b = BrainpoolP256R1_b.byte, + .generatorX = BrainpoolP256R1_generator.x.byte, + .generatorY = BrainpoolP256R1_generator.y.byte +}; + +const ECCParams_CurveParams ECCParams_BrainpoolP384R1 = { + .curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS, + .length = BrainpoolP384R1_PARAM_SIZE_BYTES, + .prime = BrainpoolP384R1_prime.byte, + .order = BrainpoolP384R1_order.byte, + .a = BrainpoolP384R1_a.byte, + .b = BrainpoolP384R1_b.byte, + .generatorX = BrainpoolP384R1_generator.x.byte, + .generatorY = BrainpoolP384R1_generator.y.byte +}; + +const ECCParams_CurveParams ECCParams_BrainpoolP512R1 = { + .curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS, + .length = BrainpoolP512R1_PARAM_SIZE_BYTES, + .prime = BrainpoolP512R1_prime.byte, + .order = BrainpoolP512R1_order.byte, + .a = BrainpoolP512R1_a.byte, + .b = BrainpoolP512R1_b.byte, + .generatorX = BrainpoolP512R1_generator.x.byte, + .generatorY = BrainpoolP512R1_generator.y.byte +}; + +const ECCParams_CurveParams ECCParams_Curve25519 = { + .curveType = ECCParams_CURVE_TYPE_MONTGOMERY, + .length = 32, + .prime = Curve25519_prime.byte, + .order = Curve25519_order.byte, + .a = Curve25519_a.byte, + .b = Curve25519_b.byte, + .generatorX = Curve25519_generator.x.byte, + .generatorY = Curve25519_generator.y.byte +}; + +/* + * ======== ECCParams_FormatCurve25519PrivateKey ======== + */ +int_fast16_t ECCParams_FormatCurve25519PrivateKey(CryptoKey *myPrivateKey){ + myPrivateKey->u.plaintext.keyMaterial[0] &= 0xF8; + myPrivateKey->u.plaintext.keyMaterial[31] &= 0x7F; + myPrivateKey->u.plaintext.keyMaterial[31] |= 0x40; + + return ECCParams_STATUS_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.c new file mode 100644 index 0000000..fa62933 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) + +/* Crypto driver semaphore used to synchronize accesses to the keyStore, AES, and SHA2 engine */ +SemaphoreP_Struct CryptoResourceCC26XX_accessSemaphore; +SemaphoreP_Struct CryptoResourceCC26XX_operationSemaphore; + +volatile bool CryptoResourceCC26XX_pollingFlag = 0; + +HwiP_Struct CryptoResourceCC26XX_hwi; + +static bool isInitialized = false; + +static void errorSpin(uintptr_t arg) { + while(1); +} + +void CryptoResourceCC26XX_constructRTOSObjects(void) { + HwiP_Params hwiParams; + uint_fast8_t key; + + key = HwiP_disable(); + + if (!isInitialized){ + /* Construct the common Hwi with a dummy ISR function. This should not matter as the function is set + * whenever we start an operation after pending on CryptoResourceCC26XX_accessSemaphore + */ + HwiP_Params_init(&hwiParams); + hwiParams.priority = ~0; + hwiParams.enableInt = false; + HwiP_construct(&(CryptoResourceCC26XX_hwi), INT_CRYPTO_RESULT_AVAIL_IRQ, errorSpin, &hwiParams); + + SemaphoreP_constructBinary(&CryptoResourceCC26XX_accessSemaphore, 1); + SemaphoreP_constructBinary(&CryptoResourceCC26XX_operationSemaphore, 0); + + isInitialized = true; + } + + HwiP_restore(key); +} + +bool CryptoResourceCC26XX_acquireLock(uint32_t timeout) { + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, + timeout); + + return resourceAcquired == SemaphoreP_OK; +} + +void CryptoResourceCC26XX_releaseLock() { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.h new file mode 100644 index 0000000..466516b --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CryptoResourceCC26XX.h + * + * @brief Shared resources to arbitrate access to the keyStore, AES, and SHA2 engine + * + */ + +#ifndef ti_drivers_cryptoutils_sharedresources_CryptoResourceCC26XX__include +#define ti_drivers_cryptoutils_sharedresources_CryptoResourceCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include + +/* Crypto driver semaphore used to synchronize accesses to the keyStore, AES, and SHA2 engine */ +extern SemaphoreP_Struct CryptoResourceCC26XX_accessSemaphore; +extern SemaphoreP_Struct CryptoResourceCC26XX_operationSemaphore; + +extern volatile bool CryptoResourceCC26XX_pollingFlag; + +extern HwiP_Struct CryptoResourceCC26XX_hwi; + + + +void CryptoResourceCC26XX_constructRTOSObjects(void); +void CryptoResourceCC26XX_destructRTOSObjects(void); +bool CryptoResourceCC26XX_acquireLock(); +void CryptoResourceCC26XX_releaseLock(); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_sharedresources_CryptoResourceCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.c new file mode 100644 index 0000000..3157f0c --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) + +/* PKA driver semaphore used to synchronize accesses to the keyStore, AES, and SHA2 engine */ +SemaphoreP_Struct PKAResourceCC26XX_accessSemaphore; +SemaphoreP_Struct PKAResourceCC26XX_operationSemaphore; + +volatile bool PKAResourceCC26XX_pollingFlag = 0; + +HwiP_Struct PKAResourceCC26XX_hwi; + +static bool isInitialized = false; + +static void errorSpin(uintptr_t arg) { + while(1); +} + +void PKAResourceCC26XX_constructRTOSObjects(void) { + HwiP_Params hwiParams; + uint_fast8_t key; + + key = HwiP_disable(); + + if (!isInitialized){ + /* Construct the common Hwi with a dummy ISR function. This should not matter as the function is set + * whenever we start an operation after pending on PKAResourceCC26XX_accessSemaphore + */ + HwiP_Params_init(&hwiParams); + hwiParams.priority = ~0; + hwiParams.enableInt = false; + HwiP_construct(&(PKAResourceCC26XX_hwi), INT_PKA_IRQ, errorSpin, &hwiParams); + + SemaphoreP_constructBinary(&PKAResourceCC26XX_accessSemaphore, 1); + SemaphoreP_constructBinary(&PKAResourceCC26XX_operationSemaphore, 0); + + isInitialized = true; + } + + HwiP_restore(key); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.h new file mode 100644 index 0000000..e8f1b07 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file PKAResourceCC26XX.h + * + * @brief Shared resources to arbitrate access to the PKA engine + * + */ + +#ifndef ti_drivers_cryptoutils_sharedresources_PKAResourceCC26XX__include +#define ti_drivers_cryptoutils_sharedresources_PKAResourceCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include + +/* PKA driver semaphore used to synchronize accesses to the PKA engine */ +extern SemaphoreP_Struct PKAResourceCC26XX_accessSemaphore; +extern SemaphoreP_Struct PKAResourceCC26XX_operationSemaphore; + +extern volatile bool PKAResourceCC26XX_pollingFlag; + +extern HwiP_Struct PKAResourceCC26XX_hwi; + + + +void PKAResourceCC26XX_constructRTOSObjects(void); +void PKAResourceCC26XX_destructRTOSObjects(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_sharedresources_PKAResourceCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dma/UDMACC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dma/UDMACC26XX.c new file mode 100644 index 0000000..2134407 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dma/UDMACC26XX.c @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(driverlib/udma.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) + +/* Externs */ +extern const UDMACC26XX_Config UDMACC26XX_config[]; + +static void UDMACC26XX_initHw(UDMACC26XX_Handle handle); + +/* + * ======== UDMACC26XX_errorDMAHwi ======== + */ + +/*! + * @brief Handler called if the DMA gets an error during transfer. + * + * This function will clear the error. + * + * @param arg A user defined argument. + * + * @return none + */ +void UDMACC26XX_hwiIntFxn(uintptr_t arg) +{ + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the hwAttrs */ + hwAttrs = ((UDMACC26XX_Handle)arg)->hwAttrs; + + /* Log the error and clear it */ + DebugP_log1("DMA error code: %d\n", uDMAErrorStatusGet(hwAttrs->baseAddr)); + uDMAErrorStatusClear(hwAttrs->baseAddr); +} + +/* + * ======== UDMACC26XX_open ======== + * + */ +UDMACC26XX_Handle UDMACC26XX_open() +{ + HwiP_Params hwiParams; + unsigned int key; + UDMACC26XX_Object *object; + UDMACC26XX_HWAttrs const *hwAttrs; + UDMACC26XX_Handle handle; + + /* Get the pointer to the object and the hwAttrs */ + handle = (UDMACC26XX_Handle)&(UDMACC26XX_config[0]); + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Power up and enable clocks for uDMA. */ + Power_setDependency(hwAttrs->powerMngrId); + + /* Disable preemption while checking if the UDMACC26XX is open. */ + key = HwiP_disable(); + + if(!object->isOpen){ + HwiP_Params_init(&hwiParams); + hwiParams.arg = (uintptr_t) handle; + hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), (int) hwAttrs->intNum, UDMACC26XX_hwiIntFxn, &hwiParams); + + /* make sure to mark the uDMA as opened */ + object->isOpen = true; + + /* initialize the UDMACC26XX hardware */ + UDMACC26XX_initHw(handle); + } + + HwiP_restore(key); + return (handle); +} + +/* + * ======== UDMACC26XX_close ======== + * + */ +void UDMACC26XX_close(UDMACC26XX_Handle handle) +{ + unsigned int key; + UDMACC26XX_Object *object; + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Disable preemption while checking if the UDMACC26XX is open. */ + key = HwiP_disable(); + + /* Only consider to take anything down if uDMA is initialized. */ + if (object->isOpen) { + if (Power_getDependencyCount(hwAttrs->powerMngrId) == 1) { + uDMADisable(hwAttrs->baseAddr); + HwiP_destruct(&(object->hwi)); + object->isOpen = false; + } + Power_releaseDependency(hwAttrs->powerMngrId); + } + + HwiP_restore(key); +} + +/* + * ======== UDMACC26XX_initHw ======== + * This functions initializes the UDMACC26XX hardware module. + * + */ +static void UDMACC26XX_initHw(UDMACC26XX_Handle handle) +{ + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the hwAttrs */ + hwAttrs = handle->hwAttrs; + + /* Disable all channels */ + UDMACC26XX_channelDisable(handle, 0xFFFFFFFF); + + /* Set the base for the channel control table. */ + uDMAControlBaseSet(hwAttrs->baseAddr, (void *) UDMACC26XX_CONFIG_BASE); + + /* Enable uDMA. */ + uDMAEnable(hwAttrs->baseAddr); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dma/UDMACC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dma/UDMACC26XX.h new file mode 100644 index 0000000..c829783 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dma/UDMACC26XX.h @@ -0,0 +1,438 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file UDMACC26XX.h + * + * @brief UDMACC26XX driver implementation. + * + * # Driver include # + * The UDMACC26XX header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * The UDMACC26XX driver currently only supports being used by the SPICC26XXDMA.h. module. + * In other words, the application should never call any of the functions in this file. + * + * # General Behavior # + * This driver is used implicitly by the SPICC26XXDMA.h driver so user should not + * have to interface to this driver from the application. + * The uDMA HW makes use of a control table in RAM which must be 1024 bytes aligned. + * The default base address of this control table is 0x20000400, however this + * can be changed by simply changing UDMACC26XX_CONFIG_BASE. + * The SPICC26XXDMA.h supports SPI0 and SPI1, and uses both TX and RX DMA channels. + * Each control table entry is 16 bytes, so if an application uses both SSI0 and SSI1 + * the total RAM usage will be 4*16=64 bytes. If only one SSI module is used + * only 2*16=32 bytes of RAM is used. Please see [Use cases] (@ref USE_CASE) for example. + * + * # Error handling # + * Error handling is handled by the overlying driver which uses the DMA, currently + * this is only SPICC26XXDMA.h + * + * # Power management # + * Power management is handled by the overlying driver which uses the DMA, currently + * this is only SPICC26XXDMA.h + * + * # Supported functions # + * Note that these functions should never be called from the application, they + * are only called from other drivers. They are however included here for completeness: + * + * | API function | Description | + * |------------------------- |----------------------------------------------------------------| + * | UDMACC26XX_open() | Initialize and enable the uDMA HW and set system dependencies. | + * | UDMACC26XX_close() | Disable uUDMA HW and release system dependencies | + * + * @note These functions should not be called by code. These functions are called + * by drivers who're using the DMA. + * + * # Unsupported Functionality # + * No known limitations + * + * # Use Cases @anchor USE_CASE # + * The DMA is only used together with the SPICC26XXDMA.h driver, so the application + * should never call any of the functions in this driver directly. + * The only thing that the application is allowed to modify is the base address + * of the DMA control table in RAM. (Default value is 0x2000_0400) + * Remember it must be 1024 bytes aligned. + * @code + * #define UDMACC26XX_CONFIG_BASE 0x2000_0400 + * @endcode + * + * - If only SSI0 is used, this will allocate 2*16=32 RAM bytes at address:\n + * [0x2000_0430-0x2000_044F] = SSI0 RX/TX DMA channels + * - If only SSI1 is used, this will allocate 2*16=32 RAM bytes at address:\n + * [0x2000_0500-0x2000_051F] = SSI1 RX/TX DMA channels + * - If both SSI0 and SSI1 are used, this will allocate 4*16=64 RAM bytes at addresses:\n + * [0x2000_0430-0x2000_044F] = SSI0 RX/TX DMA channels\n + * [0x2000_0500-0x2000_051F] = SSI1 RX/TX DMA channels + * + * # Instrumentation # + * The SPI driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic SPI operations performed | + * Diags_USER2 | detailed SPI operations performed | + * + * ============================================================================ + */ + +#ifndef ti_drivers_UDMACC26XX__include +#define ti_drivers_UDMACC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/udma.h) + +/** + * @addtogroup DMA_STATUS + * UDMACC26XX_STATUS_* macros are command codes only defined in the + * UDMACC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add DMACC26XX_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup DMA_CMD + * UDMACC26XX_CMD_* macros are command codes only defined in the + * UDMACC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add DMACC26XX_CMD_* macros here */ + +/** @}*/ + +/*! Base address for the DMA control table, must be 1024 bytes aligned */ +#if !defined(UDMACC26XX_CONFIG_BASE) && (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) + #define UDMACC26XX_CONFIG_BASE 0x20001800 +#elif !defined(UDMACC26XX_CONFIG_BASE) + #define UDMACC26XX_CONFIG_BASE 0x20000400 +#endif + +/*! Make sure DMA control table base address is 1024 bytes aligned */ +#if(UDMACC26XX_CONFIG_BASE & 0x3FF) + #error "Base address for DMA control table 'UDMACC26XX_CONFIG_BASE' must be 1024 bytes aligned." +#endif + +/*! Compiler specific macros to allocate DMA control table entries */ +#if defined(__IAR_SYSTEMS_ICC__) +#define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ +__no_init static volatile tDMAControlTable ENTRY_NAME @ UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable) +#elif defined(__TI_COMPILER_VERSION__) +#define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ +PRAGMA(LOCATION( ENTRY_NAME , UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable) );)\ +static volatile tDMAControlTable ENTRY_NAME +#define PRAGMA(x) _Pragma(#x) +#elif defined(__GNUC__) +#define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ + extern int UDMACC26XX_ ## ENTRY_NAME ## _is_placed; __attribute__ ((section("."#ENTRY_NAME))) static volatile tDMAControlTable ENTRY_NAME = {&UDMACC26XX_ ## ENTRY_NAME ## _is_placed} +#else +#error "don't know how to define ALLOCATE_CONTROL_TABLE_ENTRY for this toolchain" +#endif + +/*! Sets the DMA transfer size in number of items */ +#define UDMACC26XX_SET_TRANSFER_SIZE(SIZE) (((SIZE - 1) << UDMA_XFER_SIZE_S) & UDMA_XFER_SIZE_M) +/*! Gets the DMA transfer size in number of items*/ +#define UDMACC26XX_GET_TRANSFER_SIZE(CONTROL) (((CONTROL & UDMA_XFER_SIZE_M) >> UDMA_XFER_SIZE_S) + 1) + +/*! + * @brief UDMACC26XX object + */ +typedef struct UDMACC26XX_Object { + bool isOpen; /*!< Flag for open/close status */ + HwiP_Struct hwi; /*!< Embedded Hwi Object */ +} UDMACC26XX_Object; + +/*! + * @brief UDMACC26XX hardware attributes + */ +typedef struct UDMACC26XX_HWAttrs { + uint32_t baseAddr; /*!< Base adddress for UDMACC26XX */ + PowerCC26XX_Resource powerMngrId; /*!< UDMACC26XX Peripheral's power manager ID */ + uint8_t intNum; /*!< UDMACC26XX error interrupt number */ + /*! @brief UDMACC26XX error interrupt priority. + * intPriority is the DMA peripheral's interrupt priority, as + * defined by the underlying OS. It is passed unmodified to the + * underlying OS's interrupt handler creation code, so you need to + * refer to the OS documentation for usage. If the + * driver uses the ti.dpl interface instead of making OS + * calls directly, then the HwiP port handles the interrupt priority + * in an OS specific way. In the case of the SYS/BIOS port, + * intPriority is passed unmodified to Hwi_create(). + * + * The CC26xx uses three of the priority bits, + * meaning ~0 has the same effect as (7 << 5). + * + * (7 << 5) will apply the lowest priority. + * + * (1 << 5) will apply the highest priority. + * + * Setting the priority to 0 is not supported by this driver. + * + * HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; +} UDMACC26XX_HWAttrs; + +/*! + * @brief UDMACC26XX Global configuration + */ +typedef struct UDMACC26XX_Config { + void *object; /*!< Pointer to UDMACC26XX object */ + void const *hwAttrs; /*!< Pointer to hardware attribute */ +} UDMACC26XX_Config; + +/*! + * @brief A handle that is returned from a UDMACC26XX_open() call. + */ +typedef struct UDMACC26XX_Config *UDMACC26XX_Handle; + +/* Extern'd hwiIntFxn */ +extern void UDMACC26XX_hwiIntFxn(uintptr_t callbacks); + +/*! + * @brief Function to initialize the CC26XX DMA driver + * + * The function will set the isOpen flag to false, and should be called prior + * to opening the DMA driver. + * + * @pre Calling context: Hwi, Swi, Task + * + * @return none + * + * @sa UDMACC26XX_open() + */ +__STATIC_INLINE void UDMACC26XX_init(UDMACC26XX_Handle handle) +{ + UDMACC26XX_Object *object; + + /* Get the pointer to the object */ + object = (UDMACC26XX_Object *)(handle->object); + + /* mark the module as available */ + object->isOpen = false; +} + +/*! + * @brief Function to initialize the CC26XX DMA peripheral + * + * The function will set a dependency on the peripheral power domain, i.e. power up the + * module and enable the clock. + * Note this function always uses the first DMA entry in the global UDMACC26XX_config list. + * + * @pre UDMACC26XX_init() has to be called first. + * Calling context: Task + * + * @return UDMACC26XX_Handle on success or NULL if error or if it has been + * already opened + * + * @sa UDMACC26XX_close() + */ +extern UDMACC26XX_Handle UDMACC26XX_open(); + +/*! + * @internal + * @brief Function to enable a given DMA channel + * + * @pre UDMACC26XX_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A SPI_Handle returned from SPI_open() + * + * @param params A 32-bit bitmask of the channels to enable. + * + * @sa UDMACC26XX_channelDisable + */ +__STATIC_INLINE void UDMACC26XX_channelEnable(UDMACC26XX_Handle handle, uint32_t channelBitMask) +{ + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the hwAttrs */ + hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs); + + /* Enable DMA channel */ + HWREG(hwAttrs->baseAddr + UDMA_O_SETCHANNELEN) = channelBitMask; +} + +/*! + * @internal + * @brief Function to see if a given DMA channel is done. + * + * Will read the request done signal for the give channels + * and return true if all channels are done, otherwise false. + * + * @pre UDMACC26XX_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A SPI_Handle returned from SPI_open() + * + * @param params A 32-bit bitmask of the channels to check for if are done. + * + * @return True if the channels are done, false otherwise. + * + * @sa SPICC26XXDMA_open, UDMACC26XX_channelDisable + */ +__STATIC_INLINE bool UDMACC26XX_channelDone(UDMACC26XX_Handle handle, uint32_t channelBitMask) +{ + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the hwAttrs */ + hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs); + + /* Check if REQDONE is set for a specific channel */ + return (uDMAIntStatus(hwAttrs->baseAddr) & channelBitMask) ? true : false; +} + +/*! + * @internal + * @brief Function to clear a given DMA channel interrupt. + * + * Will clear the DMA interrupt(s) for the given bitmask provided. + * + * @pre UDMACC26XX_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A SPI_Handle returned from SPI_open() + * + * @param params A 32-bit bitmask of the channels to check for if are done. + * + * @param channelBitMask A 32-bit bitmask of the channels to clear interrupts for. + * + * @return none + */ +__STATIC_INLINE void UDMACC26XX_clearInterrupt(UDMACC26XX_Handle handle, uint32_t channelBitMask) +{ + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the hwAttrs and object */ + hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs); + + /* Clear UDMA done interrupt */ + uDMAIntClear(hwAttrs->baseAddr, channelBitMask); +} + +/*! + * @internal + * @brief Function to disable one or more DMA channels. + * + * Will disable the channel(s) for the given bitmask provided. + * + * @pre UDMACC26XX_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A SPI_Handle returned from SPI_open() + * + * @param params A 32-bit bitmask of the channels to disable. + * + * @return none + * + * @sa UDMACC26XX_channelEnable + */ +__STATIC_INLINE void UDMACC26XX_channelDisable(UDMACC26XX_Handle handle, uint32_t channelBitMask) +{ + UDMACC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + HWREG(hwAttrs->baseAddr + UDMA_O_CLEARCHANNELEN) = channelBitMask; +} + +/*! + * @internal + * @brief Function to disable a DMA channel's attributes. + * + * Will disable a channel's attributes. + * + * @pre UDMACC26XX_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A UDMACC26XX_Handle returned from UDMACC26XX_open() + * + * @param channelNum the channel to configure. + * + * @param attr Channel attribute to disable. + * + * + * @return none + * + * @sa UDMACC26XX_channelEnable + */ +__STATIC_INLINE void UDMACC26XX_disableAttribute(UDMACC26XX_Handle handle, + uint32_t channelNum, uint32_t attr) +{ + UDMACC26XX_HWAttrs const *hwAttrs = (UDMACC26XX_HWAttrs *) handle->hwAttrs; + + uDMAChannelAttributeDisable(hwAttrs->baseAddr, channelNum, attr); +} + +/*! + * @brief Function to close the DMA driver. + * + * Will disable the DMA hardware, release the power dependency and destruct + * the HWI interrupt. + * + * @pre UDMACC26XX_open() has to be called first. + * Calling context: Task + * + * @param handle A SPI_Handle returned from SPI_open() + * + * @return none + * + * @sa SPICC26XXDMA_open + */ +extern void UDMACC26XX_close(UDMACC26XX_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_UDMACC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/ClockP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/ClockP.h new file mode 100644 index 0000000..76a0bd8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/ClockP.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2016-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ClockP.h + * + * @brief Clock interface for the RTOS Porting Interface + * + * The ClockP module can be used to schedule functions that run at intervals + * specified in the underlying kernel's system ticks. ClockP instances are + * one-shot. The one-shot function will be run once + * after the specified period has elapsed since calling ClockP_start(). + * + * The ClockP module can also be used to obtain the period of the kernel's + * system tick in microseconds. This is useful for determining the number of + * ticks needed for setting a Clock object's period. + * + * When using the TI-RTOS kernel, ClockP functions are run at software + * interrupt level. With FreeRTOS, the ClockP functions are run by a timer + * service task with priority configured by the application. + * + * A common use case is to post a semaphore in the clock function. There is a + * specific API for this: Semaphore_postFromClock(). This must be used in a + * clock function (instead of Semaphore_post). + * + * ============================================================================ + */ + +#ifndef ti_dpl_ClockP__include +#define ti_dpl_ClockP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * ClockP object. + * + * nortos: 32 (biggest of the HW-specific ClockP instance structs) + * SysBIOS: 36 + */ +#define ClockP_STRUCT_SIZE (36) + +/*! + * @brief ClockP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific ClockP objects. + */ +typedef union ClockP_Struct { + uint32_t dummy; /*!< Align object */ + char data[ClockP_STRUCT_SIZE]; +} ClockP_Struct; + +/*! + * @brief Frequency-in-hertz struct + */ +typedef struct ClockP_FreqHz { + uint32_t hi; /*!< most significant 32-bits of frequency */ + uint32_t lo; /*!< least significant 32-bits of frequency */ +} ClockP_FreqHz; + +/*! + * @brief Status codes for ClockP APIs + */ +typedef enum ClockP_Status { + ClockP_OK = 0, + ClockP_FAILURE = -1 +} ClockP_Status; + +/*! + * @brief Opaque client reference to an instance of a ClockP + * + * A ClockP_Handle returned from the ::ClockP_create represents that instance. + * and then is used in the other instance based functions (e.g. ::ClockP_start, + * ::ClockP_stop, etc.). + */ +typedef void *ClockP_Handle; + +#define ClockP_handle(x) ((ClockP_Handle)(x)) + +extern uint32_t ClockP_tickPeriod; + +/*! + * @brief Prototype for a ClockP function. + */ +typedef void (*ClockP_Fxn)(uintptr_t arg); + +/*! + * @brief Basic ClockP Parameters + * + * Structure that contains the parameters passed into ::ClockP_create + * when creating a ClockP instance. The ::ClockP_Params_init function should + * be used to initialize the fields to default values before the application + * sets the fields manually. The ClockP default parameters are noted in + * ClockP_Params_init. + * The default startFlag is false, meaning the user will have to call + * ClockP_start(). If startFlag is true, the clock instance will be + * started automatically when it is created. + * + * The default value of period is 0, indicating a one-shot clock object. + * A non-zero period indicates the clock function will be called + * periodically at the period rate (in system clock ticks), after the + * clock is initially started and set to expire with the 'timeout' + * argument. + */ +typedef struct ClockP_Params { + bool startFlag; /*!< Start immediately after instance is created. */ + uint32_t period; /*!< Period of clock object. */ + uintptr_t arg; /*!< Argument passed into the clock function. */ +} ClockP_Params; + + +/*! + * @brief Function to construct a clock object. + * + * @param clockP Pointer to ClockP_Struct object. + * @param timeout The startup timeout, if supported by the RTOS. + * @param clockFxn Function called when timeout or period expires. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The ClockP default + * parameters are noted in ::SwiP_Params_init. + * + * @return A ClockP_Handle on success or a NULL on an error + */ +extern ClockP_Handle ClockP_construct(ClockP_Struct *clockP, + ClockP_Fxn clockFxn, + uint32_t timeout, + ClockP_Params *params); + +/*! + * @brief Function to destruct a clock object + * + * @param clockP Pointer to a ClockP_Struct object that was passed to + * ClockP_construct(). + * + * @return + */ +extern void ClockP_destruct(ClockP_Struct *clockP); + +/*! + * @brief Function to create a clock object. + * + * @param clockFxn Function called when timeout or period expires. + * @param timeout The startup timeout, if supported by the RTOS. + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The ClockP default + * parameters are noted in ::ClockP_Params_init. + * + * @return A ClockP_Handle on success or a NULL on an error. This handle can + * be passed to ClockP_start() + */ +extern ClockP_Handle ClockP_create(ClockP_Fxn clockFxn, + uint32_t timeout, + ClockP_Params *params); + +/*! + * @brief Function to delete a clock. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + */ +extern void ClockP_delete(ClockP_Handle handle); + +/*! + * @brief Get CPU frequency in Hz + * + * @param freq Pointer to the FreqHz structure + */ +extern void ClockP_getCpuFreq(ClockP_FreqHz *freq); + +/*! + * @brief Get the system tick period in microseconds. + * + * @return The kernel's system tick period in microseconds. + */ +extern uint32_t ClockP_getSystemTickPeriod(); + +/*! + * @brief Get the current tick value + * + * The value returned will wrap back to zero after it reaches the max + * value that can be stored in 32 bits. + * + * @return Time in system clock ticks + */ +extern uint32_t ClockP_getSystemTicks(); + +/*! + * @brief Get number of ClockP tick periods expected to expire between + * now and the next interrupt from the timer peripheral + * + * Returns the number of ClockP tick periods that are expected to expore + * between now and the next interrupt from the timer peripheral. + * + * Used internally by PowerCC26XX module + * + * @return count in ticks + */ +extern uint32_t ClockP_getTicksUntilInterrupt(); + +/*! + * @brief Get timeout of clock instance. + * + * Returns the remaining time in clock ticks if the instance has + * been started. If the clock is not active, the initial timeout value + * is returned. + * + * @return remaining timeout in clock ticks. + * + * Cannot change the initial timeout if the clock has been started. + */ +extern uint32_t ClockP_getTimeout(ClockP_Handle handle); + +/*! + * @brief Determine if a clock object is currently active (i.e., running) + * + * Returns true if the clock object is currently active, otherwise + * returns false. + * + * @return active state + */ +extern bool ClockP_isActive(ClockP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - name: NULL + * - arg: 0 + * + * @param params Pointer to the instance configuration parameters. + */ +extern void ClockP_Params_init(ClockP_Params *params); + +/*! + * @brief Set the initial timeout + * + * @param timeout Initial timeout in ClockP ticks + * + * Cannot change the initial timeout if the clock has been started. + */ +extern void ClockP_setTimeout(ClockP_Handle handle, uint32_t timeout); + +/*! + * @brief Function to start a clock. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + */ +extern void ClockP_start(ClockP_Handle handle); + +/*! + * @brief Function to stop a clock. + * + * @param handle A ClockP_Handle returned from ::ClockP_create + * + * It is ok to call ClockP_stop() for a clock that has not been started. + * + * @return Status of the functions + * - ClockP_OK: Stopped the clock function successfully + * - ClockP_FAILURE: The API failed. + */ +extern void ClockP_stop(ClockP_Handle handle); + +extern void ClockP_timestamp(ClockP_Handle handle); + +/*! + * @brief Set delay in microseconds + * + * @param usec A duration in micro seconds + * + * @return ClockP_OK + */ +extern void ClockP_usleep(uint32_t usec); + +/*! + * @brief Set delay in seconds + * + * @param sec A duration in seconds + * + * @return ClockP_OK + */ +extern void ClockP_sleep(uint32_t sec); + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_ClockP__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/DebugP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/DebugP.h new file mode 100644 index 0000000..51faa02 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/DebugP.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file DebugP.h + * + * @brief Debug support + * + * The DebugP module allows application to do logging and assert checking. + * + * DebugP_assert calls can be added into code. If the code + * is compiled with the compiler define DebugP_ASSERT_ENABLED set to a + * non-zero value, the call is passed onto the underlying assert checking. + * If DebugP_ASSERT_ENABLED is zero (or not defined), the calls are + * resolved to nothing. + * + * This module sits on top of the assert checking of the underlying + * RTOS. Please refer to the underlying RTOS port implementation for + * more details. + * + * Similarly, DebugP_logN calls can be added into code. If the code + * is compiled with the compiler define DebugP_LOG_ENABLED set to a + * non-zero value, the call is passed onto the underlying assert checking. + * If DebugP_LOG_ENABLED is zero (or not defined), the calls are + * resolved to nothing. + + * This module sits on top of the logging of the underlying + * RTOS. Please refer to the underlying RTOS port implementation for + * more details. + * + * ============================================================================ + */ + +#ifndef ti_dpl_DebugP__include +#define ti_dpl_DebugP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef DebugP_ASSERT_ENABLED +#define DebugP_ASSERT_ENABLED 0 +#endif + +#ifndef DebugP_LOG_ENABLED +#define DebugP_LOG_ENABLED 0 +#endif + +#if DebugP_ASSERT_ENABLED +extern void _DebugP_assert(int expression, const char *file, int line); +/*! + * @brief Assert checking function + * + * If the expression is evaluated to true, the API does nothing. + * If it is evaluated to false, the underlying RTOS port implementation + * handles the assert via its mechanisms. + * + * @param expression Expression to evaluate + */ +#define DebugP_assert(expression) (_DebugP_assert(expression, \ + __FILE__, __LINE__)) +#else +#define DebugP_assert(expression) +#endif + +#if DebugP_LOG_ENABLED +/*! + * @brief Debug log function with 0 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + */ +extern void DebugP_log0(const char *format); + +/*! + * @brief Debug log function with 1 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + */ +extern void DebugP_log1(const char *format, uintptr_t p1); + +/*! + * @brief Debug log function with 2 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + */ +extern void DebugP_log2(const char *format, uintptr_t p1, uintptr_t p2); + +/*! + * @brief Debug log function with 3 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + * @param p3 third parameter to format string + */ +extern void DebugP_log3(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3); + +/*! + * @brief Debug log function with 4 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + * @param p3 third parameter to format string + * @param p4 fourth parameter to format string + */ +extern void DebugP_log4(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3, uintptr_t p4); +#else +#define DebugP_log0(format) +#define DebugP_log1(format, p1) +#define DebugP_log2(format, p1, p2) +#define DebugP_log3(format, p1, p2, p3) +#define DebugP_log4(format, p1, p2, p3, p4) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_DebugP__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/HwiP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/HwiP.h new file mode 100644 index 0000000..fa6f126 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/HwiP.h @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file HwiP.h + * + * @brief Hardware Interrupt module for the RTOS Porting Interface + * + * The ::HwiP_disable/::HwiP_restore APIs can be called recursively. The order + * of the HwiP_restore calls, must be in reversed order. For example: + * @code + * uintptr_t key1, key2; + * key1 = HwiP_disable(); + * key2 = HwiP_disable(); + * HwiP_restore(key2); + * HwiP_restore(key1); + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_dpl_HwiP__include +#define ti_dpl_HwiP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * HwiP object. + * + * nortos: 12 + * SysBIOS: 28 + */ +#define HwiP_STRUCT_SIZE (28) + +/*! + * @brief HwiP structure. + * + * Opaque structure that should be large enough to hold any of the RTOS + * specific HwiP objects. + */ +typedef union HwiP_Struct { + uint32_t dummy; /*!< Align object */ + char data[HwiP_STRUCT_SIZE]; +} HwiP_Struct; + +/*! + * @brief Opaque client reference to an instance of a HwiP + * + * A HwiP_Handle returned from the ::HwiP_create represents that instance. + */ +typedef void *HwiP_Handle; + +/*! + * @brief Status codes for HwiP APIs + */ +typedef enum HwiP_Status { + HwiP_OK = 0, + HwiP_FAILURE = -1 +} HwiP_Status; + +/*! + * @brief Prototype for the entry function for a hardware interrupt + */ +typedef void (*HwiP_Fxn)(uintptr_t arg); + +/*! + * @brief Basic HwiP Parameters + * + * Structure that contains the parameters passed into ::HwiP_create + * when creating a HwiP instance. The ::HwiP_Params_init function should + * be used to initialize the fields to default values before the application sets + * the fields manually. The HwiP default parameters are noted in + * HwiP_Params_init. + * + * Parameter enableInt specifies if the interrupt should be enabled + * upon creation of the HwiP object. The default is true. + */ +typedef struct HwiP_Params { + uintptr_t arg; /*!< Argument passed into the Hwi function. */ + uint32_t priority; /*!< Device specific priority. */ + bool enableInt; /*!< Enable interrupt on creation. */ +} HwiP_Params; + +/*! + * @brief Interrupt number posted by SwiP + * + * The SwiP module needs its scheduler to run at key points in SwiP + * processing. This is accomplished via an interrupt that is configured + * at the lowest possible interrupt priority level and is plugged with + * the SwiP scheduler. This interrupt must be the *only* interrupt at + * that lowest priority. SwiP will post this interrupt whenever its + * scheduler needs to run. + * + * The default value for your device should suffice, but if a different + * interrupt is needed to be used for SwiP scheduling then HwiP_swiPIntNum + * can be assigned with this interrupt (early on, before HwiPs are created + * and before any SwiP gets posted). + */ +extern int HwiP_swiPIntNum; + +/*! + * @brief Function to construct a hardware interrupt object. + * + * @param hwiP Pointer to HwiP_Struct object. + * @param interruptNum Interrupt Vector Id + * @param hwiFxn entry function of the hardware interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The HwiP default + * parameters are noted in ::HwiP_Params_init. + * + * @return A HwiP_Handle on success or a NULL on an error + */ +extern HwiP_Handle HwiP_construct(HwiP_Struct *hwiP, int interruptNum, + HwiP_Fxn hwiFxn, HwiP_Params *params); + +/*! + * @brief Function to destruct a hardware interrupt object + * + * @param hwiP Pointer to a HwiP_Struct object that was passed to + * HwiP_construct(). + * + * @return + */ +extern void HwiP_destruct(HwiP_Struct *hwiP); + +/*! + * @brief Function to clear a single interrupt + * + * @param interruptNum interrupt number to clear + */ +extern void HwiP_clearInterrupt(int interruptNum); + +/*! + * @brief Function to create an interrupt on CortexM devices + * + * @param interruptNum Interrupt Vector Id + * + * @param hwiFxn entry function of the hardware interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The HwiP default + * parameters are noted in ::HwiP_Params_init. + * + * @return A HwiP_Handle on success or a NULL on an error + */ +extern HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, + HwiP_Params *params); + +/*! + * @brief Function to delete an interrupt on CortexM devices + * + * @param handle returned from the HwiP_create call + * + * @return + */ +extern void HwiP_delete(HwiP_Handle handle); + +/*! + * @brief Function to disable interrupts to enter a critical region + * + * This function can be called multiple times, but must unwound in the reverse + * order. For example + * @code + * uintptr_t key1, key2; + * key1 = HwiP_disable(); + * key2 = HwiP_disable(); + * HwiP_restore(key2); + * HwiP_restore(key1); + * @endcode + * + * @return A key that must be passed to HwiP_restore to re-enable interrupts. + */ +extern uintptr_t HwiP_disable(void); + +/*! + * @brief Function to enable interrupts + */ +extern void HwiP_enable(void); + +/*! + * @brief Function to disable a single interrupt + * + * @param interruptNum interrupt number to disable + */ +extern void HwiP_disableInterrupt(int interruptNum); + +/*! + * @brief Function to enable a single interrupt + * + * @param interruptNum interrupt number to enable + */ +extern void HwiP_enableInterrupt(int interruptNum); + +/*! + * @brief Function to return a status based on whether it is in an interrupt + * context. + * + * @return A status: indicating whether the function was called in an + * ISR (true) or at thread level (false). + */ +extern bool HwiP_inISR(void); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - arg: 0 + * - priority: ~0 + * - enableInt: true + * + * @param params Pointer to the instance configuration parameters. + */ +extern void HwiP_Params_init(HwiP_Params *params); + +/*! + * @brief Function to plug an interrupt vector + * + * @param interruptNum ID of interrupt to plug + * @param fxn ISR that services plugged interrupt + */ +extern void HwiP_plug(int interruptNum, void *fxn); + +/*! + * @brief Function to generate an interrupt + * + * @param interruptNum ID of interrupt to generate + */ +extern void HwiP_post(int interruptNum); + +/*! + * @brief Function to restore interrupts to exit a critical region + * + * @param key return from HwiP_disable + */ +extern void HwiP_restore(uintptr_t key); + +/*! + * @brief Function to overwrite HwiP function and arg + * + * @param hwiP handle returned from the HwiP_create or construct call + * @param fxn pointer to ISR function + * @param arg argument to ISR function + */ +extern void HwiP_setFunc(HwiP_Handle hwiP, HwiP_Fxn fxn, uintptr_t arg); + +/*! + * @brief Function to set the priority of a hardware interrupt + * + * @param interruptNum id of the interrupt to change + * @param priority new priority + */ +extern void HwiP_setPriority(int interruptNum, uint32_t priority); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_HwiP__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/MutexP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/MutexP.h new file mode 100644 index 0000000..037bb55 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/MutexP.h @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file MutexP.h + * + * @brief Mutex module for the RTOS Porting Interface + * + * The MutexP module allows task to maintain critical region segments. The + * MutexP module has two main functions: ::MutexP_lock and ::MutexP_unlock. + * + * The MutexP module supports recursive calls to the MutexP_lock API by a + * single task. The same number of MutexP_unlock calls must be done for the + * mutex to be release. Note: the returned key must be provided in the LIFO + * order. For example: + * @code + * uintptr_t key1, key2; + * key1 = MutexP_lock(); + * key2 = MutexP_lock(); + * MutexP_lock(key2); + * MutexP_lock(key1); + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_dpl_MutexP__include +#define ti_dpl_MutexP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * MutexP object. + * + * nortos: 12 + * SysBIOS: 40 + */ +#define MutexP_STRUCT_SIZE (40) + +/*! + * @brief MutexP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific MutexP objects. + */ +typedef union MutexP_Struct { + uint32_t dummy; /*!< Align object */ + char data[MutexP_STRUCT_SIZE]; +} MutexP_Struct; + +/*! + * @brief Status codes for MutexP APIs + */ +typedef enum MutexP_Status { + /*! API completed successfully */ + MutexP_OK = 0, + /*! API failed */ + MutexP_FAILURE = -1 +} MutexP_Status; + +/*! + * @brief Opaque client reference to an instance of a MutexP + * + * A MutexP_Handle returned from the ::MutexP_create represents that instance. + * and then is used in the other instance based functions (e.g. ::MutexP_lock, + * ::MutexP_unlock, etc.). + */ +typedef void *MutexP_Handle; + +/*! + * @brief Basic MutexP Parameters + * + * Structure that contains the parameters are passed into ::MutexP_create + * when creating a MutexP instance. The ::MutexP_Params_init function should + * be used to initialize the fields to default values before the application + * sets the fields manually. The MutexP default parameters are noted in + * ::MutexP_Params_init. + */ +typedef struct MutexP_Params { + void (*callback)(void); /*!< Callback while waiting for mutex unlock */ +} MutexP_Params; + + +/*! + * @brief Function to construct a mutex. + * + * @param handle Pointer to a MutexP_Struct object + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters (MutexP default + * parameters as noted in ::MutexP_Params_init. + * + * @return A MutexP_Handle on success or a NULL on an error + */ +extern MutexP_Handle MutexP_construct(MutexP_Struct *handle, + MutexP_Params *params); + +/*! + * @brief Function to destruct a mutex object + * + * @param mutexP Pointer to a MutexP_Struct object that was passed to + * MutexP_construct(). + * + * @return + */ +extern void MutexP_destruct(MutexP_Struct *mutexP); + +/*! + * @brief Function to create a mutex. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The MutexP default + * parameters are noted in ::MutexP_Params_init. + * + * @return A MutexP_Handle on success or a NULL on an error + */ +extern MutexP_Handle MutexP_create(MutexP_Params *params); + +/*! + * @brief Function to delete a mutex. + * + * @param handle A MutexP_Handle returned from MutexP_create + */ +extern void MutexP_delete(MutexP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * callback - NULL. + * + * @param params Pointer to the instance configuration parameters. + */ +extern void MutexP_Params_init(MutexP_Params *params); + +/*! + * @brief Function to lock a mutex. + * + * This function can only be called from a Task. It cannot be called from + * an interrupt. The lock will block until the mutex is available. + * + * Users of a mutex should make every attempt to minimize the duration that + * that they have it locked. This is to minimize latency. It is recommended + * that the users of the mutex do not block while they have the mutex locked. + * + * This function unlocks the mutex. If the mutex is locked multiple times + * by the caller, the same number of unlocks must be called. + * + * @param handle A MutexP_Handle returned from ::MutexP_create + * + * @return A key is returned. This key must be passed into ::MutexP_unlock. + */ +extern uintptr_t MutexP_lock(MutexP_Handle handle); + +/*! + * @brief Function to unlock a mutex + * + * This function unlocks the mutex. If the mutex is locked multiple times + * by the caller, the same number of unlocks must be called. The order of + * the keys must be reversed. For example + * @code + * uintptr_t key1, key2; + * key1 = MutexP_lock(); + * key2 = MutexP_lock(); + * MutexP_lock(key2); + * MutexP_lock(key1); + * @endcode + * + * @param handle A MutexP_Handle returned from ::MutexP_create + * + * @param key Return from ::MutexP_lock. + */ +extern void MutexP_unlock(MutexP_Handle handle, uintptr_t key); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_MutexP__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SemaphoreP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SemaphoreP.h new file mode 100644 index 0000000..7753e2d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SemaphoreP.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SemaphoreP.h + * + * @brief Semaphore module for the RTOS Porting Interface + * + * Semaphores can be counting semaphores or binary semaphores. Counting + * semaphores keep track of the number of times the semaphore has been posted + * with post functions. This is useful, for example, if you have a group of + * resources that are shared between tasks. Such tasks might call pend() to see + * if a resource is available before using one. A count of zero for a counting + * semaphore denotes that it is not available. A positive count denotes + * how many times a SemaphoreP_pend can be called before it is blocked (or + * returns SemaphoreP_TIMEOUT). + * + * Binary semaphores can have only two states: available (count = 1) and + * unavailable (count = 0). They can be used to share a single resource + * between tasks. They can also be used for a basic signalling mechanism, where + * the semaphore can be posted multiple times. Binary semaphores do not keep + * track of the count; they simply track whether the semaphore has been posted + * or not. + * + * ============================================================================ + */ + +#ifndef ti_dpl_SemaphoreP__include +#define ti_dpl_SemaphoreP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * SemaphoreP object. + * + * nortos: 16 + * SysBIOS: 28 + */ +#define SemaphoreP_STRUCT_SIZE (28) + +/*! + * @brief SemaphoreP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific SemaphoreP objects. + */ +typedef union SemaphoreP_Struct { + uint32_t dummy; /*!< Align object */ + char data[SemaphoreP_STRUCT_SIZE]; +} SemaphoreP_Struct; + +/*! + * @brief Wait forever define + */ +#define SemaphoreP_WAIT_FOREVER ~(0) + +/*! + * @brief No wait define + */ +#define SemaphoreP_NO_WAIT (0) + +/*! + * @brief Status codes for SemaphoreP APIs (for backwards compatibility) + */ +typedef enum SemaphoreP_Status { + /*! API completed successfully */ + SemaphoreP_OK = 0, + /*! API failed because of a timeout */ + SemaphoreP_TIMEOUT = -1 +} SemaphoreP_Status; + +/*! + * @brief Opaque client reference to an instance of a SemaphoreP + * + * A SemaphoreP_Handle returned from the ::SemaphoreP_create represents that + * instance and is used in the other instance based functions (e.g. + * ::SemaphoreP_post or ::SemaphoreP_pend, etc.). + */ +typedef void *SemaphoreP_Handle; + +/*! + * @brief Mode of the semaphore + */ +typedef enum SemaphoreP_Mode { + SemaphoreP_Mode_COUNTING = 0x0, + SemaphoreP_Mode_BINARY = 0x1 +} SemaphoreP_Mode; + +/*! + * @brief Basic SemaphoreP Parameters + * + * Structure that contains the parameters are passed into ::SemaphoreP_create + * when creating a SemaphoreP instance. The ::SemaphoreP_Params_init function + * should be used to initialize the fields to default values before the + * application sets the fields manually. The SemaphoreP default parameters are + * noted in SemaphoreP_Params_init. + */ +typedef struct SemaphoreP_Params { + SemaphoreP_Mode mode; /*!< Mode for the semaphore */ + void (*callback)(void); /*!< Callback while pending for semaphore post */ +} SemaphoreP_Params; + +/*! + * @brief Default SemaphoreP instance parameters + * + * SemaphoreP_defaultParams represents the default parameters that are + * used when creating or constructing a SemaphoreP instance. + * SemaphoreP_Params_init() will use the contents of this structure for + * initializing the SemaphoreP_Params instance. + * + * SemaphoreP_defaultParams is exposed to the application for the purpose + * of allowing the application to change the default parameters for all + * SemaphoreP instances created thereafter. The main intent for allowing + * the default parameters to be changed is for setting a semaphore's + * callback function to Power_idleFunc(), so that the SOC can enter low + * power mode when pending on a semaphore. + */ +extern SemaphoreP_Params SemaphoreP_defaultParams; + + +/* + * SemaphoreP construct APIs can only be used if one of the OS's + * is defined. For FreeRTOS, configSUPPORT_STATIC_ALLOCATION also + * has to be set to 1 in FreeRTOSConfig.h. + */ +extern SemaphoreP_Handle SemaphoreP_construct(SemaphoreP_Struct *handle, + unsigned int count, SemaphoreP_Params *params); + +extern SemaphoreP_Handle SemaphoreP_constructBinary(SemaphoreP_Struct *handle, + unsigned int count); + +extern void SemaphoreP_destruct(SemaphoreP_Struct *semP); + +/*! + * @brief Function to create a semaphore. + * + * @param count Initial count of the semaphore. For binary semaphores, + * only values of 0 or 1 are valid. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters (SemaphoreP default + * parameters as noted in ::SemaphoreP_Params_init. + * + * @return A SemaphoreP_Handle on success or a NULL on an error + */ +extern SemaphoreP_Handle SemaphoreP_create(unsigned int count, + SemaphoreP_Params *params); + +/*! + * @brief Function to create a binary semaphore. + * + * This can be used instead of SemaphoreP_create() to create a binary + * semaphore. + * + * @param count Initial count of the binary semaphore. Only values + * of 0 or 1 are valid. + * + * @return A SemaphoreP_Handle on success or a NULL on an error + */ +extern SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count); + +/*! + * @brief Function to create a binary semaphore. + * + * This can be used instead of SemaphoreP_create() to create a binary + * semaphore. + * + * @param count Initial count of the binary semaphore. Only values + * of 0 or 1 are valid. + * + * @return A SemaphoreP_Handle on success or a NULL on an error + */ +extern SemaphoreP_Handle SemaphoreP_createBinaryCallback(unsigned int count, + void (*callback)(void)); + +/*! + * @brief Function to delete a semaphore. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + */ +extern void SemaphoreP_delete(SemaphoreP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - mode: SemaphoreP_Mode_COUNTING + * - name: NULL + * + * @param params Pointer to the instance configuration parameters. + */ +extern void SemaphoreP_Params_init(SemaphoreP_Params *params); + +/*! + * @brief Function to pend (wait) on a semaphore. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + * + * @param timeout Timeout (in ClockP ticks) to wait for the semaphore to + * be posted (signalled). + * + * @return Status of the functions + * - SemaphoreP_OK: Obtained the semaphore + * - SemaphoreP_TIMEOUT: Timed out. Semaphore was not obtained. + */ +extern SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, + uint32_t timeout); + +/*! + * @brief Function to post (signal) a semaphore from task of ISR context. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + */ +extern void SemaphoreP_post(SemaphoreP_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_SemaphoreP__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SwiP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SwiP.h new file mode 100644 index 0000000..4f2b3f1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SwiP.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SwiP.h + * + * @brief Software Interrupt module for the RTOS Porting Interface + * + * ============================================================================ + */ + +#ifndef ti_dpl_SwiP__include +#define ti_dpl_SwiP__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * SwiP object. + * + * nortos: 40 + * SysBIOS: 52 + */ +#define SwiP_STRUCT_SIZE (52) + +/*! + * @brief SemaphoreP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific SwiP objects. + */ +typedef union SwiP_Struct { + uint32_t dummy; /*!< Align object */ + char data[SwiP_STRUCT_SIZE]; +} SwiP_Struct; + +#include +#include +#include + +/*! + * @brief Opaque client reference to an instance of a SwiP + * + * A SwiP_Handle returned from the ::SwiP_create represents that instance. + */ +typedef void *SwiP_Handle; + +/*! + * @brief Status codes for SwiP APIs + * TODO: See if we need more error codes. + */ +typedef enum SwiP_Status { + SwiP_OK = 0, + SwiP_FAILURE = -1 +} SwiP_Status; + +/*! + * @brief Prototype for the entry function for a hardware interrupt + */ +typedef void (*SwiP_Fxn)(uintptr_t arg0, uintptr_t arg1); + +/*! + * @brief Basic SwiP Parameters + * + * Structure that contains the parameters passed into ::SwiP_create + * and ::SwiP_construct when creating or constructing a SwiP instance. + * The ::SwiP_Params_init function should be used to initialize the + * fields to default values before the application sets the fields + * manually. The SwiP default parameters are noted in ::SwiP_Params_init. + * + * Each SwiP object has a "trigger" used either to determine whether to + * post the SwiP or as a value that can be evaluated within the SwiP's + * function. + * + * The SwiP_andn and SwiP_dec functions post the SwiP + * if the trigger value transitions to 0. The SwiP_or and + * SwiP_inc functions also modify the trigger value. SwiP_or + * sets bits, and SwiP_andn clears bits. + */ +typedef struct SwiP_Params { + uintptr_t arg0; /*!< Argument passed into the SwiP function. */ + uintptr_t arg1; /*!< Argument passed into the SwiP function. */ + uint32_t priority; /*!< priority, 0 is min, 1, 2, ..., ~0 for max */ + uint32_t trigger; /*!< Initial SwiP trigger value. */ +} SwiP_Params; + +/*! + * @brief Function to construct a software interrupt object. + * + * @param swiP Pointer to SwiP_Struct object. + * @param swiFxn entry function of the software interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The SwiP default + * parameters are noted in ::SwiP_Params_init. + * + * @return A SwiP_Handle on success or a NULL on an error + */ +extern SwiP_Handle SwiP_construct(SwiP_Struct *swiP, SwiP_Fxn swiFxn, + SwiP_Params *params); + +/*! + * @brief Function to destruct a software interrupt object + * + * @param swiP Pointer to a SwiP_Struct object that was passed to + * SwiP_construct(). + * + * @return + */ +extern void SwiP_destruct(SwiP_Struct *swiP); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - name: NULL + * + * @param params Pointer to the instance configuration parameters. + */ +extern void SwiP_Params_init(SwiP_Params *params); + +/*! + * @brief Function to create a software interrupt object. + * + * @param swiFxn entry function of the software interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The SwiP default + * parameters are noted in ::SwiP_Params_init. + * + * @return A SwiP_Handle on success or a NULL on an error + */ +extern SwiP_Handle SwiP_create(SwiP_Fxn swiFxn, + SwiP_Params *params); + +/*! + * @brief Function to delete a software interrupt object + * + * @param handle returned from the SwiP_create call + * + */ +extern void SwiP_delete(SwiP_Handle handle); + +/*! + * @brief Function to disable software interrupts + * + * This function can be called multiple times, but must unwound in the reverse + * order. For example + * @code + * uintptr_t key1, key2; + * key1 = SwiP_disable(); + * key2 = SwiP_disable(); + * SwiP_restore(key2); + * SwiP_restore(key1); + * @endcode + * + * @return A key that must be passed to SwiP_restore to re-enable interrupts. + */ +extern uintptr_t SwiP_disable(void); + +/*! + * @brief Function to get the trigger value of the currently running SwiP. + * + */ +extern uint32_t SwiP_getTrigger(); + +/*! + * @brief Clear bits in SwiP's trigger. Post SwiP if trigger becomes 0. + * + * @param handle returned from the SwiP_create or SwiP_construct call + * @param mask inverse value to be ANDed + */ +extern void SwiP_andn(SwiP_Handle handle, uint32_t mask); + +/*! + * @brief Decrement SwiP's trigger value. Post SwiP if trigger becomes 0. + * + * @param handle returned from the SwiP_create or SwiP_construct call + */ +extern void SwiP_dec(SwiP_Handle handle); + +/*! + * @brief Increment the SwiP's trigger value and post the SwiP. + * + * @param handle returned from the SwiP_create or SwiP_construct call + */ +extern void SwiP_inc(SwiP_Handle handle); + +/*! + * @brief Function to return a status based on whether it is in a + * software interrupt context. + * + * @return A status: indicating whether the function was called in a + * software interrupt routine (true) or not (false). + */ +extern bool SwiP_inISR(void); + +/*! + * @brief Or the mask with the SwiP's trigger value and post the SwiP. + * + * @param handle returned from the SwiP_create or SwiP_construct call + * @param mask value to be ORed + */ +extern void SwiP_or(SwiP_Handle handle, uint32_t mask); + +/*! + * @brief Unconditionally post a software interrupt. + * + * @param handle returned from the SwiP_create or SwiP_construct call + */ +extern void SwiP_post(SwiP_Handle handle); + +/*! + * @brief Function to restore software interrupts + * + * @param key return from SwiP_disable + */ +extern void SwiP_restore(uintptr_t key); + +/*! + * @brief Function to set the priority of a software interrupt + * + * @param handle returned from the SwiP_create or SwiP_construct call + * @param priority new priority + */ +extern void SwiP_setPriority(SwiP_Handle handle, uint32_t priority); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_SwiP__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SystemP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SystemP.h new file mode 100644 index 0000000..b5aa4c1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SystemP.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** =========================================================================== + * @file SystemP.h + * + * @brief System module for the RTOS Porting Interface + * + * Basic system services for supporting printf-like output. + * + * =========================================================================== + */ + +#ifndef ti_dpl_SystemP__include +#define ti_dpl_SystemP__include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern int SystemP_snprintf(char *buf, size_t n, const char *format,...); +extern int SystemP_vsnprintf(char *buf, size_t n, const char *format, va_list va); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_SemaphoreP__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdh/ECDHCC26X2.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdh/ECDHCC26X2.c new file mode 100644 index 0000000..c30834a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdh/ECDHCC26X2.c @@ -0,0 +1,643 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/smph.h) + + +/* Forward declarations */ +static void ECDHCC26X2_hwiFxn (uintptr_t arg0); +static void ECDHCC26X2_internalCallbackFxn (ECDH_Handle handle, + int_fast16_t returnStatus, + ECDH_Operation operation, + ECDH_OperationType operationType); +static int_fast16_t ECDHCC26X2_waitForAccess(ECDH_Handle handle); +static int_fast16_t ECDHCC26X2_waitForResult(ECDH_Handle handle); +static int_fast16_t ECDHCC26X2_runFSM(ECDH_Handle handle); +static int_fast16_t ECDHCC26X2_convertReturnValue(uint32_t pkaResult); + +/* Extern globals */ +extern const ECDH_Config ECDH_config[]; +extern const uint_least8_t ECDH_count; + +/* Static globals */ +static bool isInitialized = false; +static uint32_t resultAddress; + +/* + * ======== ECDHCC26X2_internalCallbackFxn ======== + */ +static void ECDHCC26X2_internalCallbackFxn (ECDH_Handle handle, + int_fast16_t returnStatus, + ECDH_Operation operation, + ECDH_OperationType operationType) { + ECDHCC26X2_Object *object = handle->object; + + /* This function is only ever registered when in ECDH_RETURN_BEHAVIOR_BLOCKING + * or ECDH_RETURN_BEHAVIOR_POLLING. + */ + if (object->returnBehavior == ECDH_RETURN_BEHAVIOR_BLOCKING) { + SemaphoreP_post(&PKAResourceCC26XX_operationSemaphore); + } + else { + PKAResourceCC26XX_pollingFlag = 1; + } +} + +/* + * ======== ECDHCC26X2_hwiFxn ======== + */ +static void ECDHCC26X2_hwiFxn (uintptr_t arg0) { + ECDHCC26X2_Object *object = ((ECDH_Handle)arg0)->object; + int_fast16_t operationStatus; + ECDH_Operation operation; + ECDH_OperationType operationType; + uint32_t key; + + /* Disable interrupt again. It may be reenabled in the FSM function. */ + IntDisable(INT_PKA_IRQ); + + /* Execute next states */ + do { + object->operationStatus = ECDHCC26X2_runFSM((ECDH_Handle)arg0); + object->fsmState++; + } while (object->operationStatus == ECDHCC26X2_STATUS_FSM_RUN_FSM); + + /* We need a critical section here in case the operation is canceled + * asynchronously. + */ + key = HwiP_disable(); + + if(object->operationCanceled) { + /* Set function register to 0. This should stop the current operation */ + HWREG(PKA_BASE + PKA_O_FUNCTION) = 0; + + object->operationStatus = ECDH_STATUS_CANCELED; + } + + switch (object->operationStatus) { + case ECDHCC26X2_STATUS_FSM_RUN_PKA_OP: + + HwiP_restore(key); + + /* Do nothing. The PKA or TRNG hardware + * will execute in the background and post + * this SWI when it is done. + */ + break; + case ECDH_STATUS_SUCCESS: + /* Intentional fall through */ + case ECDH_STATUS_ERROR: + /* Intentional fall through */ + case ECDH_STATUS_CANCELED: + /* Intentional fall through */ + default: + + /* Mark this operation as complete */ + object->operationInProgress = false; + + /* Clear any pending interrupt in case a transaction kicked off + * above already finished + */ + IntDisable(INT_PKA_IRQ); + IntPendClear(INT_PKA_IRQ); + + /* We can end the critical section since the operation may no + * longer be canceled + */ + HwiP_restore(key); + + /* Make sure there is no keying material remaining in PKA RAM */ + PKAClearPkaRam(); + + /* Save all inputs to the callbackFxn on the stack + * in case a higher priority hwi comes in and + * starts a new operation after we have released the + * access semaphore. + */ + operationStatus = object->operationStatus; + operation = object->operation; + operationType = object->operationType; + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. This does have the drawback that another hwi + * can come in and start an operation before the original + * on finished completely. This should be prevented by + * customers only starting operations with the same + * handle from a single context and waiting for + * the callback of the original operation to + * be executed in callback return mode. + */ + SemaphoreP_post(&PKAResourceCC26XX_accessSemaphore); + + + object->callbackFxn((ECDH_Handle)arg0, + operationStatus, + operation, + operationType); + } +} + +int_fast16_t ECDHCC26X2_runFSM(ECDH_Handle handle) { + ECDHCC26X2_Object *object = handle->object; + uint32_t pkaResult; + + switch (object->fsmState) { + case ECDHCC26X2_FSM_GEN_PUB_KEY_VALIDATE_PRIVATE_KEY: + /* We need to verify that private key in [1, n] for arbitrary short Weierstrass curves. */ + if (PKAArrayAllZeros(object->operation.generatePublicKey->myPrivateKey->u.plaintext.keyMaterial, + object->operation.generatePublicKey->curve->length)) { + return ECDH_STATUS_PRIVATE_KEY_ZERO; + } + + PKABigNumCmpStart(object->operation.generatePublicKey->myPrivateKey->u.plaintext.keyMaterial, + object->operation.generatePublicKey->curve->order, + object->operation.generatePublicKey->curve->length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + return ECDHCC26X2_convertReturnValue(pkaResult); + + case ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR: + + /* Perform an elliptic curve multiplication on a short Weierstrass curve */ + PKAEccMultiplyStart(object->operation.generatePublicKey->myPrivateKey->u.plaintext.keyMaterial, + object->operation.generatePublicKey->curve->generatorX, + object->operation.generatePublicKey->curve->generatorY, + object->operation.generatePublicKey->curve->prime, + object->operation.generatePublicKey->curve->a, + object->operation.generatePublicKey->curve->b, + object->operation.generatePublicKey->curve->length, + &resultAddress); + + break; + + case ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR_RESULT: + + /* Get X and Y coordinates for short Weierstrass curves */ + pkaResult = PKAEccMultiplyGetResult(object->operation.generatePublicKey->myPublicKey->u.plaintext.keyMaterial, + object->operation.generatePublicKey->myPublicKey->u.plaintext.keyMaterial + + object->operation.generatePublicKey->curve->length, + resultAddress, + object->operation.generatePublicKey->curve->length); + + return ECDHCC26X2_convertReturnValue(pkaResult); + + case ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR_MONTGOMERY: + + /* Perform an elliptic curve multiplication on a Montgomery curve. Likely Curve25519. */ + PKAEccMontgomeryMultiplyStart(object->operation.generatePublicKey->myPrivateKey->u.plaintext.keyMaterial, + object->operation.generatePublicKey->curve->generatorX, + object->operation.generatePublicKey->curve->prime, + object->operation.generatePublicKey->curve->a, + object->operation.generatePublicKey->curve->length, + &resultAddress); + + + break; + + case ECDHCC26X2_FSM_GEN_PUB_KEY_VALIDATE_PRIVATE_KEY_MONTGOMERY: + /* Curve25519 private keys must be formatted according to cr.yp.to/ecdh.html. + * Since the keying material may not be altered (because the array is in flash e.g.), + * we need to reject any non-conforming private keys. + */ + if (object->operation.generatePublicKey->myPrivateKey->u.plaintext.keyMaterial[0] & 0x07 || + object->operation.generatePublicKey->myPrivateKey->u.plaintext.keyMaterial[31] & 0x80 || + !(object->operation.generatePublicKey->myPrivateKey->u.plaintext.keyMaterial[31] & 0x40)) { + /* If the bottom three bits or the top bit are set or the second to last bit is not set, + * throw an error. + */ + return ECDH_STATUS_ERROR; + } + else { + return ECDHCC26X2_STATUS_FSM_RUN_FSM; + } + + case ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR_RESULT_MONTGOMERY: + + /* The PKA hw only returns the X coordinate for Montgomery multiplications. This is fine for Curve25519 */ + pkaResult = PKAEccMultiplyGetResult(object->operation.generatePublicKey->myPublicKey->u.plaintext.keyMaterial, + NULL, + resultAddress, + object->operation.generatePublicKey->curve->length); + + /* Zero-out the Y coordinate */ + memset(object->operation.generatePublicKey->myPublicKey->u.plaintext.keyMaterial + + object->operation.generatePublicKey->curve->length, + 0x00, + object->operation.generatePublicKey->curve->length); + + return ECDHCC26X2_convertReturnValue(pkaResult); + + case ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_VALIDATE_PUB_KEY: + + /* If we are using a short Weierstrass curve, we need to validate the public key */ + pkaResult = PKAEccVerifyPublicKeyWeierstrassStart(object->operation.computeSharedSecret->theirPublicKey->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->theirPublicKey->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length, + object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->a, + object->operation.computeSharedSecret->curve->b, + object->operation.computeSharedSecret->curve->order, + object->operation.computeSharedSecret->curve->length); + + /* Break out early since no PKA operation was started by the verify fxn */ + return ECDHCC26X2_convertReturnValue(pkaResult); + + + case ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY: + + /* Perform an elliptic curve multiplication on a short Weierstrass curve */ + PKAEccMultiplyStart(object->operation.computeSharedSecret->myPrivateKey->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->theirPublicKey->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->theirPublicKey->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length, + object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->a, + object->operation.computeSharedSecret->curve->b, + object->operation.computeSharedSecret->curve->length, + &resultAddress); + + + break; + + case ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_RESULT: + + /* Get X and Y coordinates for short Weierstrass curves */ + pkaResult = PKAEccMultiplyGetResult(object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length, + resultAddress, + object->operation.computeSharedSecret->curve->length); + + + return ECDHCC26X2_convertReturnValue(pkaResult); + + case ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_MONTGOMERY: + + /* Perform an elliptic curve multiplication on a Montgomery curve. Likely Curve25519. */ + PKAEccMontgomeryMultiplyStart(object->operation.computeSharedSecret->myPrivateKey->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->theirPublicKey->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->a, + object->operation.computeSharedSecret->curve->length, + &resultAddress); + + break; + + case ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_RESULT_MONTGOMERY: + + /* The PKA hw only returns the X coordinate for Montgomery multiplications. This is fine for Curve25519 */ + pkaResult = PKAEccMultiplyGetResult(object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial, + NULL, + resultAddress, + object->operation.computeSharedSecret->curve->length); + + /* Zero-out the Y coordinate */ + memset(object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length, + 0x00, + object->operation.computeSharedSecret->curve->length); + + + return ECDHCC26X2_convertReturnValue(pkaResult); + + case ECDHCC26X2_FSM_GEN_PUB_KEY_RETURN: + case ECDHCC26X2_FSM_GEN_PUB_KEY_RETURN_MONTGOMERY: + case ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_RETURN: + case ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_RETURN_MONTGOMERY: + return ECDH_STATUS_SUCCESS; + default: + return ECDH_STATUS_ERROR; + } + + // If we get to this point, we want to perform another PKA operation + IntPendClear(INT_PKA_IRQ); + IntEnable(INT_PKA_IRQ); + + return ECDHCC26X2_STATUS_FSM_RUN_PKA_OP; +} + +/* + * ======== ECDHCC26X2_convertReturnValue ======== + */ +static int_fast16_t ECDHCC26X2_convertReturnValue(uint32_t pkaResult) { + switch (pkaResult) { + case PKA_STATUS_SUCCESS: + case PKA_STATUS_A_LESS_THAN_B: + /* A less than B only comes up when checking private + * key values. It indicates a key within the correct range. + */ + return ECDHCC26X2_STATUS_FSM_RUN_FSM; + + case PKA_STATUS_A_GREATER_THAN_B: + case PKA_STATUS_EQUAL: + /* This indicates a private key >= n which is not permitted. */ + return ECDH_STATUS_PRIVATE_KEY_LARGER_EQUAL_ORDER; + + case PKA_STATUS_X_ZERO: + case PKA_STATUS_Y_ZERO: + case PKA_STATUS_RESULT_0: + /* Theoretically, PKA_STATUS_RESULT_0 might be caused by other + * operations failing but the only one that really should yield + * 0 is ECC multiplication with invalid inputs that yield the + * point at infinity. + */ + return ECDH_STATUS_POINT_AT_INFINITY; + + case PKA_STATUS_X_LARGER_THAN_PRIME: + case PKA_STATUS_Y_LARGER_THAN_PRIME: + return ECDH_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME; + + case PKA_STATUS_POINT_NOT_ON_CURVE: + return ECDH_STATUS_PUBLIC_KEY_NOT_ON_CURVE; + + default: + return ECDH_STATUS_ERROR; + } +} + +/* + * ======== ECDH_init ======== + */ +void ECDH_init(void) { + PKAResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== ECDH_Params_init ======== + */ +void ECDH_Params_init(ECDH_Params *params){ + *params = ECDH_defaultParams; +} + +/* + * ======== ECDH_open ======== + */ +ECDH_Handle ECDH_open(uint_least8_t index, ECDH_Params *params) { + ECDH_Handle handle; + ECDHCC26X2_Object *object; + uint_fast8_t key; + + handle = (ECDH_Handle)&(ECDH_config[index]); + object = handle->object; + + DebugP_assert(index < ECDH_count); + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + // If params are NULL, use defaults + if (params == NULL) { + params = (ECDH_Params *)&ECDH_defaultParams; + } + + DebugP_assert((params->returnBehavior == ECDH_RETURN_BEHAVIOR_CALLBACK) ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->returnBehavior == ECDH_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : ECDHCC26X2_internalCallbackFxn; + object->semaphoreTimeout = params->timeout; + + // Set power dependency - i.e. power up and enable clock for PKA (PKAResourceCC26XX) module. + Power_setDependency(PowerCC26X2_PERIPH_PKA); + + return handle; +} + +/* + * ======== ECDH_close ======== + */ +void ECDH_close(ECDH_Handle handle) { + ECDHCC26X2_Object *object; + + DebugP_assert(handle); + + // Get the pointer to the object + object = handle->object; + + // Mark the module as available + object->isOpen = false; + + // Release power dependency on PKA Module. + Power_releaseDependency(PowerCC26X2_PERIPH_PKA); +} + + +/* + * ======== ECDHCC26X2_waitForAccess ======== + */ +static int_fast16_t ECDHCC26X2_waitForAccess(ECDH_Handle handle) { + ECDHCC26X2_Object *object = handle->object; + uint32_t timeout; + + // Set to SemaphoreP_NO_WAIT to start operations from SWI or HWI context + timeout = object->returnBehavior == ECDH_RETURN_BEHAVIOR_BLOCKING ? object->semaphoreTimeout : SemaphoreP_NO_WAIT; + + return SemaphoreP_pend(&PKAResourceCC26XX_accessSemaphore, timeout); +} + +/* + * ======== ECDHCC26X2_waitForResult ======== + */ +static int_fast16_t ECDHCC26X2_waitForResult(ECDH_Handle handle){ + ECDHCC26X2_Object *object = handle->object; + + object->operationInProgress = true; + + switch (object->returnBehavior) { + case ECDH_RETURN_BEHAVIOR_POLLING: + while(!PKAResourceCC26XX_pollingFlag); + return object->operationStatus; + case ECDH_RETURN_BEHAVIOR_BLOCKING: + SemaphoreP_pend(&PKAResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + return object->operationStatus; + case ECDH_RETURN_BEHAVIOR_CALLBACK: + return ECDH_STATUS_SUCCESS; + default: + return ECDH_STATUS_ERROR; + } +} + +/* + * ======== ECDH_generatePublicKey ======== + */ +int_fast16_t ECDH_generatePublicKey(ECDH_Handle handle, ECDH_OperationGeneratePublicKey *operation) { + ECDHCC26X2_Object *object = handle->object; + ECDHCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (ECDHCC26X2_waitForAccess(handle) != SemaphoreP_OK) { + return ECDH_STATUS_RESOURCE_UNAVAILABLE; + } + + /* Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->operationStatus = ECDHCC26X2_STATUS_FSM_RUN_FSM; + object->operation.generatePublicKey = operation; + object->operationType = ECDH_OPERATION_TYPE_GENERATE_PUBLIC_KEY; + object->operationCanceled = false; + + /* Use the correct state chain for the curve type */ + if (operation->curve->curveType == ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS) { + object->fsmState = ECDHCC26X2_FSM_GEN_PUB_KEY_VALIDATE_PRIVATE_KEY; + } + else { + object->fsmState = ECDHCC26X2_FSM_GEN_PUB_KEY_VALIDATE_PRIVATE_KEY_MONTGOMERY; + } + + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECDHCC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Start running FSM to generate public key. The PKA interrupt is level triggered and + * will run imediately once enabled + */ + IntEnable(INT_PKA_IRQ); + + return ECDHCC26X2_waitForResult(handle); +} + +/* + * ======== ECDH_computeSharedSecret ======== + */ +int_fast16_t ECDH_computeSharedSecret(ECDH_Handle handle, ECDH_OperationComputeSharedSecret *operation) { + ECDHCC26X2_Object *object = handle->object; + ECDHCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (ECDHCC26X2_waitForAccess(handle) != SemaphoreP_OK) { + return ECDH_STATUS_RESOURCE_UNAVAILABLE; + } + + /* Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->operationStatus = ECDHCC26X2_STATUS_FSM_RUN_FSM; + object->operation.computeSharedSecret = operation; + object->operationType = ECDH_OPERATION_TYPE_COMPUTE_SHARED_SECRET; + object->operationCanceled = false; + + + /* Use the correct state chain for the curve type */ + if (operation->curve->curveType == ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS) { + object->fsmState = ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_VALIDATE_PUB_KEY; + } + else { + object->fsmState = ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_MONTGOMERY; + } + + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECDHCC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Start running FSM to generate PMSN. The PKA interrupt is level triggered and + * will run imediately once enabled + */ + IntEnable(INT_PKA_IRQ); + + return ECDHCC26X2_waitForResult(handle); +} + +/* + * ======== ECDH_cancelOperation ======== + */ +int_fast16_t ECDH_cancelOperation(ECDH_Handle handle) { + ECDHCC26X2_Object *object = handle->object; + + if(!object->operationInProgress){ + return ECDH_STATUS_ERROR; + } + + object->operationCanceled = true; + + /* Post hwi as if operation finished for cleanup */ + IntEnable(INT_PKA_IRQ); + HwiP_post(INT_PKA_IRQ); + + + return ECDH_STATUS_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdh/ECDHCC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdh/ECDHCC26X2.h new file mode 100644 index 0000000..39fcdd0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdh/ECDHCC26X2.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECDHCC26X2.h + * + * @brief ECDH driver implementation for the CC26X2 family + * + * @warning This is a beta API. It may change in future releases. + * + * This file should only be included in the board file to fill the ECDH_config + * struct. + * + * # Hardware and Implementation Details # + * + * The CC26X2 family has a dedicated public key accelerator. + * It is capable of multiple mathematical operations including dedicated ECC point addition, doubling, + * and scalar multiplication. Only one operation can be carried out on the accelerator + * at a time. Mutual exclusion is implemented at the driver level and coordinated + * between all drivers relying on the accelerator. It is transparent to the application + * and only noted ensure sensible access timeouts are set. + * + * The large number maths engine (LNME) uses a dedicated 2kB block of RAM (PKA RAM) for its operations. + * The operands of the maths operations must be copied into and results out of the PKA ram. + * This necessitates a significant number of reads and writes for each operation. + * The bus interface to the RAM only allows for word-aligned reads and writes. The CPU splits + * the reads and writes from and to general SRAM from unaligned addresses into multiple + * bus operations while accumulating the data in a register until it is full. + * The result of this hardware process is that providing buffers such as plaintext CryptoKey + * keying material to ECC APIs that are word-aligned will significantly speed up the operation and + * reduce power consumption. + * + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input parameter validation coverage is + * achieved by turning on assertions when compiling the driver. + * + * # Supported Curve Types # + * + * The driver implementation supports the following curve types for ECDH: + * + * | Curve Type | Supported | + * |-------------------|-----------| + * | Short Weierstrass | Yes | + * | Montgomery | Yes | + * | Edwards | No | + * + * # Curve25519 Private Keys # + * + * When using Montgomery Curve25519, the private key must be formatted according to cr.yp.to/ecdh.html + * by the application before passing it to the driver. The driver cannot do so itself as the memory + * location of the keying material may be in flash. + * + * For keying material uint8_t myPrivateKey[32], you must do the following: + * @code + * myPrivateKey[0] &= 0xF8; + * myPrivateKey[31] &= 0x7F; + * myPrivateKey[31] |= 0x40; + * @endcode + * + * Alternatively, you can call ECCParams_FormatCurve25519PrivateKey() in ti/drivers/cryptoutils/ecc/ECCParams.h + * + * # Public Key Validation # + * + * When performing shared secret generation, the foreign public key will always be validated + * when using short Weierstrass curves. The only explicitly supported Montgomery curve is + * Curve25519 which does not require public key validation. + * The implementation assumes that the cofactor, h, of the curve is 1. This lets us + * skip the computationally expensive step of multiplying the foreign key by the order and + * checking if it yields the point at infinity. When the cofactor is 1, this property is + * implied by validating that the point is not already the point at infinity and that it + * validates against the curve equation. + * All curves supplied by default, the NIST and Brainpool curves, have cofactor = 1. While + * the implementation can use arbitrary curves, you should verify that any other curve used + * has a cofactor of 1. + */ + +#ifndef ti_drivers_ecdh_ECDHCC26X2__include +#define ti_drivers_ecdh_ECDHCC26X2__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/pka.h) + +#include +#include +#include + +/* Exit the SWI and wait until an HWI call posts the SWI again */ +#define ECDHCC26X2_STATUS_FSM_RUN_PKA_OP ECDH_STATUS_RESERVED - 0 +/* Execute the next FSM state immediately without waiting for the next HWI */ +#define ECDHCC26X2_STATUS_FSM_RUN_FSM ECDH_STATUS_RESERVED - 1 + +/*! + * @brief ECDHCC26X2 states + * + * The ECDH operations are implemented using multiple invidividual + * PKA operations. Since state transitions for these operations are almost + * always predictable, the state transitions are encoded linearly in this enum. + * The FSM controller will increment the state counter and iterate through + * states until it is told to stop or restart. + */ +typedef enum ECDHCC26X2_FsmState_ { + ECDHCC26X2_FSM_ERROR = 0, + + ECDHCC26X2_FSM_GEN_PUB_KEY_VALIDATE_PRIVATE_KEY, + ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR, + ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR_RESULT, + ECDHCC26X2_FSM_GEN_PUB_KEY_RETURN, + + ECDHCC26X2_FSM_GEN_PUB_KEY_VALIDATE_PRIVATE_KEY_MONTGOMERY, + ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR_MONTGOMERY, + ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR_RESULT_MONTGOMERY, + ECDHCC26X2_FSM_GEN_PUB_KEY_RETURN_MONTGOMERY, + + ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_VALIDATE_PUB_KEY, + ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY, + ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_RESULT, + ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_RETURN, + + ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_MONTGOMERY, + ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_RESULT_MONTGOMERY, + ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_RETURN_MONTGOMERY, +} ECDHCC26X2_FsmState; + +/*! + * @brief ECDHCC26X2 Hardware Attributes + * + * ECC26XX hardware attributes should be included in the board file + * and pointed to by the ECDH_config struct. + */ +typedef struct ECDHCC26X2_HWAttrs_ { + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; +} ECDHCC26X2_HWAttrs; + +/*! + * @brief ECDHCC26X2 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct ECDHCC26X2_Object_ { + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t operationStatus; + ECDH_CallbackFxn callbackFxn; + ECDH_ReturnBehavior returnBehavior; + ECDH_Operation operation; + ECDH_OperationType operationType; + ECDHCC26X2_FsmState fsmState; + uint32_t semaphoreTimeout; + uint32_t resultAddress; +} ECDHCC26X2_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecdh_ECDHCC26X2__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdsa/ECDSACC26X2.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdsa/ECDSACC26X2.c new file mode 100644 index 0000000..01805cc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdsa/ECDSACC26X2.c @@ -0,0 +1,900 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_pka.h) +#include DeviceFamily_constructPath(inc/hw_pka_ram.h) +#include DeviceFamily_constructPath(driverlib/pka.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) + +#define ECDSACC26X2_SCRATCH_BUFFER_SIZE 256 + +/* Since we only support <= 384-bit curves, we can allocate two temporary buffers + * at the midway address in PKA_RAM. This leaves us with 1024 bytes of RAM + * to work with. That should be sufficient for our needs. Multiplications will + * take up to 3x the curve param length of 384 bits or 48 bytes. ECC addition + * requires 8x the curve param length in RAM. 1024 bytes would even suffice + * for 384-bit curves. + */ +#define ECDSACC26X2_SCRATCH_BUFFER ((uint8_t *)(PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE / 2)) +#define ECDSACC26X2_SCRATCH_BUFFER_2 ((uint8_t *)(PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE / 2 + ECDSACC26X2_SCRATCH_BUFFER_SIZE)) + +/* Forward declarations */ +static void ECDSACC26X2_hwiFxn (uintptr_t arg0); +static void ECDSACC26X2_internalCallbackFxn (ECDSA_Handle handle, + int_fast16_t returnStatus, + ECDSA_Operation operation, + ECDSA_OperationType operationType); +static int_fast16_t ECDSACC26X2_waitForAccess(ECDSA_Handle handle); +static int_fast16_t ECDSACC26X2_waitForResult(ECDSA_Handle handle); +static int_fast16_t ECDSACC26X2_runSignFSM(ECDSA_Handle handle); +static int_fast16_t ECDSACC26X2_runVerifyFSM(ECDSA_Handle handle); +static int_fast16_t ECDSACC26X2_convertReturnValue(uint32_t pkaResult); + +/* Extern globals */ +extern const ECDSA_Config ECDSA_config[]; +extern const uint_least8_t ECDSA_count; +extern const ECDSA_Params ECDSA_defaultParams; + +/* Static globals */ +static bool isInitialized = false; +static uint32_t resultAddress; + +static uint32_t scratchBufferSize = ECDSACC26X2_SCRATCH_BUFFER_SIZE; +static uint32_t scratchBuffer2Size = ECDSACC26X2_SCRATCH_BUFFER_SIZE; + + +/* + * ======== ECDSACC26X2_internalCallbackFxn ======== + */ +static void ECDSACC26X2_internalCallbackFxn (ECDSA_Handle handle, + int_fast16_t returnStatus, + ECDSA_Operation operation, + ECDSA_OperationType operationType) { + ECDSACC26X2_Object *object = handle->object; + + /* This function is only ever registered when in ECDSA_RETURN_BEHAVIOR_BLOCKING + * or ECDSA_RETURN_BEHAVIOR_POLLING. + */ + if (object->returnBehavior == ECDSA_RETURN_BEHAVIOR_BLOCKING) { + SemaphoreP_post(&PKAResourceCC26XX_operationSemaphore); + } + else { + PKAResourceCC26XX_pollingFlag = 1; + } +} + +/* + * ======== ECDSACC26X2_hwiFxn ======== + */ +static void ECDSACC26X2_hwiFxn (uintptr_t arg0) { + ECDSACC26X2_Object *object = ((ECDSA_Handle)arg0)->object; + uint32_t key; + + /* Disable interrupt again */ + IntDisable(INT_PKA_IRQ); + + /* Execute next states */ + do { + object->operationStatus = object->fsmFxn((ECDSA_Handle)arg0); + object->fsmState++; + } while (object->operationStatus == ECDSACC26X2_STATUS_FSM_RUN_FSM); + + /* We need a critical section here in case the operation is canceled + * asynchronously. + */ + key = HwiP_disable(); + + if(object->operationCanceled) { + /* Set function register to 0. This should stop the current operation */ + HWREG(PKA_BASE + PKA_O_FUNCTION) = 0; + + object->operationStatus = ECDSA_STATUS_CANCELED; + } + + switch (object->operationStatus) { + case ECDSACC26X2_STATUS_FSM_RUN_PKA_OP: + + HwiP_restore(key); + + /* Do nothing. The PKA hardware + * will execute in the background and post + * this SWI when it is done. + */ + break; + case ECDSA_STATUS_SUCCESS: + /* Intentional fall through */ + case ECDSA_STATUS_ERROR: + /* Intentional fall through */ + case ECDSA_STATUS_CANCELED: + /* Intentional fall through */ + default: + + /* Mark this operation as complete */ + object->operationInProgress = false; + + /* Clear any pending interrupt in case a transaction kicked off + * above already finished + */ + IntDisable(INT_PKA_IRQ); + IntPendClear(INT_PKA_IRQ); + + /* We can end the critical section since the operation may no + * longer be canceled + */ + HwiP_restore(key); + + /* Make sure there is no keying material remaining in PKA RAM */ + PKAClearPkaRam(); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&PKAResourceCC26XX_accessSemaphore); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->callbackFxn((ECDSA_Handle)arg0, + object->operationStatus, + object->operation, + object->operationType); + } +} + +/* + * ======== ECDSACC26X2_runSignFSM ======== + */ +static int_fast16_t ECDSACC26X2_runSignFSM(ECDSA_Handle handle) { + ECDSACC26X2_Object *object = handle->object; + uint32_t pkaResult; + + switch (object->fsmState) { + case ECDSACC26X2_FSM_SIGN_VALIDATE_PMSN: + if (PKAArrayAllZeros(object->operation.sign->pmsn->u.plaintext.keyMaterial, + object->operation.sign->curve->length)) { + return ECDSA_STATUS_INVALID_PMSN; + } + + PKABigNumCmpStart(object->operation.sign->pmsn->u.plaintext.keyMaterial, + object->operation.sign->curve->order, + object->operation.sign->curve->length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return ECDSA_STATUS_INVALID_PMSN; + } + else { + return ECDSACC26X2_STATUS_FSM_RUN_FSM; + } + + case ECDSACC26X2_FSM_SIGN_COMPUTE_R: + + PKAEccMultiplyStart(object->operation.sign->pmsn->u.plaintext.keyMaterial, + object->operation.sign->curve->generatorX, + object->operation.sign->curve->generatorY, + object->operation.sign->curve->prime, + object->operation.sign->curve->a, + object->operation.sign->curve->b, + object->operation.sign->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_SIGN_COMPUTE_R_RESULT: + + pkaResult = PKAEccMultiplyGetResult(object->operation.sign->r, + NULL, + resultAddress, + object->operation.sign->curve->length); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_SIGN_R_MOD_N: + + PKABigNumModStart(object->operation.sign->r, + object->operation.sign->curve->length, + object->operation.sign->curve->order, + object->operation.sign->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_SIGN_R_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult(object->operation.sign->r, + object->operation.sign->curve->length, + resultAddress); + + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_SIGN_COMPUTE_PMSN_INVERSE: + + PKABigNumInvModStart(object->operation.sign->pmsn->u.plaintext.keyMaterial, + object->operation.sign->curve->length, + object->operation.sign->curve->order, + object->operation.sign->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_SIGN_COMPUTE_PMSN_INVERSE_RESULT: + + pkaResult = PKABigNumInvModGetResult(object->operation.sign->s, + object->operation.sign->curve->length, + resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_SIGN_COMPUTE_PRIVATE_KEY_X_R: + + PKABigNumMultiplyStart(object->operation.sign->myPrivateKey->u.plaintext.keyMaterial, + object->operation.sign->curve->length, + object->operation.sign->r, + object->operation.sign->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_SIGN_COMPUTE_PRIVATE_KEY_X_R_RESULT: + + scratchBufferSize = ECDSACC26X2_SCRATCH_BUFFER_SIZE; + + pkaResult = PKABigNumMultGetResult(ECDSACC26X2_SCRATCH_BUFFER, + &scratchBufferSize, + resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_SIGN_ADD_HASH: + + PKABigNumAddStart(ECDSACC26X2_SCRATCH_BUFFER, + scratchBufferSize, + object->operation.sign->hash, + object->operation.sign->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_SIGN_ADD_HASH_RESULT: + + scratchBufferSize = ECDSACC26X2_SCRATCH_BUFFER_SIZE; + + pkaResult = PKABigNumAddGetResult(ECDSACC26X2_SCRATCH_BUFFER, + &scratchBufferSize, + resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_SIGN_MULT_BY_PMSN_INVERSE: + + PKABigNumMultiplyStart(ECDSACC26X2_SCRATCH_BUFFER, + scratchBufferSize, + object->operation.sign->s, + object->operation.sign->curve->length, + &resultAddress); + + break; + + + case ECDSACC26X2_FSM_SIGN_MULT_BY_PMSN_INVERSE_RESULT: + + scratchBufferSize = ECDSACC26X2_SCRATCH_BUFFER_SIZE; + + pkaResult = PKABigNumMultGetResult(ECDSACC26X2_SCRATCH_BUFFER, + &scratchBufferSize, + resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_SIGN_MOD_N: + + PKABigNumModStart(ECDSACC26X2_SCRATCH_BUFFER, + scratchBufferSize, + object->operation.sign->curve->order, + object->operation.sign->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_SIGN_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult(object->operation.sign->s, + object->operation.sign->curve->length, + resultAddress); + + if (pkaResult == PKA_STATUS_SUCCESS) { + return ECDSA_STATUS_SUCCESS; + } + else { + return ECDSA_STATUS_ERROR; + } + + default: + return ECDSA_STATUS_ERROR; + } + + // If we get to this point, we want to perform another PKA operation + IntPendClear(INT_PKA_IRQ); + IntEnable(INT_PKA_IRQ); + + return ECDSACC26X2_STATUS_FSM_RUN_PKA_OP; +} + +/* + * ======== ECDSACC26X2_runVerifyFSM ======== + */ +static int_fast16_t ECDSACC26X2_runVerifyFSM(ECDSA_Handle handle) { + ECDSACC26X2_Object *object = handle->object; + uint32_t pkaResult; + + switch (object->fsmState) { + case ECDSACC26X2_FSM_VERIFY_R_S_IN_RANGE: + + PKABigNumCmpStart(object->operation.verify->r, + object->operation.verify->curve->order, + object->operation.verify->curve->length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return ECDSA_STATUS_R_LARGER_THAN_ORDER; + } + + PKABigNumCmpStart(object->operation.verify->s, + object->operation.verify->curve->order, + object->operation.verify->curve->length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult == PKA_STATUS_A_LESS_THAN_B) { + return ECDSACC26X2_STATUS_FSM_RUN_FSM; + } + else { + return ECDSA_STATUS_S_LARGER_THAN_ORDER; + } + + case ECDSACC26X2_FSM_VERIFY_VALIDATE_PUBLIC_KEY: + + pkaResult = PKAEccVerifyPublicKeyWeierstrassStart(object->operation.verify->theirPublicKey->u.plaintext.keyMaterial, + object->operation.verify->theirPublicKey->u.plaintext.keyMaterial + + object->operation.verify->curve->length, + object->operation.verify->curve->prime, + object->operation.verify->curve->a, + object->operation.verify->curve->b, + object->operation.verify->curve->order, + object->operation.verify->curve->length); + + // Break out early since no PKA operation was started by the verify fxn + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_COMPUTE_S_INV: + + PKABigNumInvModStart(object->operation.verify->s, + object->operation.verify->curve->length, + object->operation.verify->curve->order, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_COMPUTE_S_INV_RESULT: + + pkaResult = PKABigNumInvModGetResult(ECDSACC26X2_SCRATCH_BUFFER_2, + object->operation.verify->curve->length, + resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_MULT_S_INV_HASH: + + PKABigNumMultiplyStart(ECDSACC26X2_SCRATCH_BUFFER_2, + object->operation.verify->curve->length, + object->operation.verify->hash, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_MULT_S_INV_HASH_RESULT: + + scratchBufferSize = ECDSACC26X2_SCRATCH_BUFFER_SIZE; + + pkaResult = PKABigNumMultGetResult(ECDSACC26X2_SCRATCH_BUFFER, + &scratchBufferSize, + resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_S_INV_MULT_HASH_MOD_N: + + PKABigNumModStart(ECDSACC26X2_SCRATCH_BUFFER, + scratchBufferSize, + object->operation.verify->curve->order, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_S_INV_MULT_HASH_MOD_N_RESULT: + // Check previous result + pkaResult = PKABigNumModGetResult(ECDSACC26X2_SCRATCH_BUFFER, + object->operation.verify->curve->length, + resultAddress); + + scratchBufferSize = object->operation.verify->curve->length; + + return ECDSACC26X2_convertReturnValue(pkaResult); + + + case ECDSACC26X2_FSM_VERIFY_MULT_G: + + PKAEccMultiplyStart(ECDSACC26X2_SCRATCH_BUFFER, + object->operation.verify->curve->generatorX, + object->operation.verify->curve->generatorY, + object->operation.verify->curve->prime, + object->operation.verify->curve->a, + object->operation.verify->curve->b, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_MULT_G_RESULT: + + pkaResult = PKAEccMultiplyGetResult(ECDSACC26X2_SCRATCH_BUFFER, + ECDSACC26X2_SCRATCH_BUFFER + object->operation.verify->curve->length, + resultAddress, + object->operation.verify->curve->length); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R: + + PKABigNumMultiplyStart(ECDSACC26X2_SCRATCH_BUFFER_2, + object->operation.verify->curve->length, + object->operation.verify->r, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R_RESULT: + + scratchBuffer2Size = ECDSACC26X2_SCRATCH_BUFFER_SIZE; + + pkaResult = PKABigNumMultGetResult(ECDSACC26X2_SCRATCH_BUFFER_2, + &scratchBuffer2Size, + resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R_MOD_N: + + PKABigNumModStart(ECDSACC26X2_SCRATCH_BUFFER_2, + scratchBuffer2Size, + object->operation.verify->curve->order, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult(ECDSACC26X2_SCRATCH_BUFFER_2, + object->operation.verify->curve->length, + resultAddress); + + scratchBuffer2Size = object->operation.verify->curve->length; + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_MULT_PUB_KEY: + + PKAEccMultiplyStart(ECDSACC26X2_SCRATCH_BUFFER_2, + object->operation.verify->theirPublicKey->u.plaintext.keyMaterial, + object->operation.verify->theirPublicKey->u.plaintext.keyMaterial + object->operation.verify->curve->length, + object->operation.verify->curve->prime, + object->operation.verify->curve->a, + object->operation.verify->curve->b, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_MULT_PUB_KEY_RESULT: + + pkaResult = PKAEccMultiplyGetResult(ECDSACC26X2_SCRATCH_BUFFER_2, + ECDSACC26X2_SCRATCH_BUFFER_2 + object->operation.verify->curve->length, + resultAddress, + object->operation.verify->curve->length); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_ADD_MULT_RESULTS: + + PKAEccAddStart(ECDSACC26X2_SCRATCH_BUFFER, + ECDSACC26X2_SCRATCH_BUFFER + object->operation.verify->curve->length, + ECDSACC26X2_SCRATCH_BUFFER_2, + ECDSACC26X2_SCRATCH_BUFFER_2 + object->operation.verify->curve->length, + object->operation.verify->curve->prime, + object->operation.verify->curve->a, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_ADD_MULT_RESULTS_RESULT: + + pkaResult = PKAEccAddGetResult(ECDSACC26X2_SCRATCH_BUFFER, + NULL, + resultAddress, + object->operation.verify->curve->length); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_POINTX_MOD_N: + + PKABigNumModStart(ECDSACC26X2_SCRATCH_BUFFER, + object->operation.verify->curve->length, + object->operation.verify->curve->order, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_POINTX_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult(ECDSACC26X2_SCRATCH_BUFFER, + object->operation.verify->curve->length, + resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_COMPARE_RESULT_R: + + PKABigNumCmpStart(object->operation.verify->r, + ECDSACC26X2_SCRATCH_BUFFER, + object->operation.verify->curve->length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult == PKA_STATUS_EQUAL) { + return ECDSA_STATUS_SUCCESS; + } + else { + return ECDSA_STATUS_ERROR; + } + + + default: + return ECDSA_STATUS_ERROR; + } + + // If we get to this point, we want to perform another PKA operation + IntPendClear(INT_PKA_IRQ); + IntEnable(INT_PKA_IRQ); + + return ECDSACC26X2_STATUS_FSM_RUN_PKA_OP; +} + +/* + * ======== ECDSACC26X2_convertReturnValue ======== + */ +static int_fast16_t ECDSACC26X2_convertReturnValue(uint32_t pkaResult) { + switch (pkaResult) { + case PKA_STATUS_SUCCESS: + + return ECDSACC26X2_STATUS_FSM_RUN_FSM; + + case PKA_STATUS_X_ZERO: + case PKA_STATUS_Y_ZERO: + case PKA_STATUS_RESULT_0: + /* Theoretically, PKA_STATUS_RESULT_0 might be caused by other + * operations failing but the only one that really should yield + * 0 is ECC multiplication with invalid inputs that yield the + * point at infinity. + */ + return ECDSA_STATUS_POINT_AT_INFINITY; + + case PKA_STATUS_X_LARGER_THAN_PRIME: + case PKA_STATUS_Y_LARGER_THAN_PRIME: + + return ECDSA_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME; + + case PKA_STATUS_POINT_NOT_ON_CURVE: + + return ECDSA_STATUS_PUBLIC_KEY_NOT_ON_CURVE; + + default: + return ECDSA_STATUS_ERROR; + } +} + +/* + * ======== ECDSACC26X2_waitForAccess ======== + */ +static int_fast16_t ECDSACC26X2_waitForAccess(ECDSA_Handle handle) { + ECDSACC26X2_Object *object = handle->object; + uint32_t timeout; + + /* Set to SemaphoreP_NO_WAIT to start operations from SWI or HWI context */ + timeout = object->returnBehavior == ECDSA_RETURN_BEHAVIOR_BLOCKING ? object->semaphoreTimeout : SemaphoreP_NO_WAIT; + + return SemaphoreP_pend(&PKAResourceCC26XX_accessSemaphore, timeout); +} + +/* + * ======== ECDSACC26X2_waitForResult ======== + */ +static int_fast16_t ECDSACC26X2_waitForResult(ECDSA_Handle handle){ + ECDSACC26X2_Object *object = handle->object; + + object->operationInProgress = true; + + switch (object->returnBehavior) { + case ECDSA_RETURN_BEHAVIOR_POLLING: + while(!PKAResourceCC26XX_pollingFlag); + return object->operationStatus; + case ECDSA_RETURN_BEHAVIOR_BLOCKING: + SemaphoreP_pend(&PKAResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + return object->operationStatus; + case ECDSA_RETURN_BEHAVIOR_CALLBACK: + return ECDSA_STATUS_SUCCESS; + default: + return ECDSA_STATUS_ERROR; + } +} + + +/* + * ======== ECDSA_init ======== + */ +void ECDSA_init(void) { + PKAResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + + +/* + * ======== ECDSA_close ======== + */ +void ECDSA_close(ECDSA_Handle handle) { + ECDSACC26X2_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on PKA Module. */ + Power_releaseDependency(PowerCC26X2_PERIPH_PKA); +} + + +/* + * ======== ECDSA_open ======== + */ +ECDSA_Handle ECDSA_open(uint_least8_t index, ECDSA_Params *params) { + ECDSA_Handle handle; + ECDSACC26X2_Object *object; + uint_fast8_t key; + + handle = (ECDSA_Handle)&(ECDSA_config[index]); + object = handle->object; + + DebugP_assert(index < ECDSA_count); + + /* If params are NULL, use defaults */ + if (params == NULL) { + params = (ECDSA_Params *)&ECDSA_defaultParams; + } + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + DebugP_assert((params->returnBehavior == ECDSA_RETURN_BEHAVIOR_CALLBACK) ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->returnBehavior == ECDSA_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : ECDSACC26X2_internalCallbackFxn; + object->semaphoreTimeout = params->timeout; + + /* Set power dependency - i.e. power up and enable clock for PKA (PKAResourceCC26XX) module. */ + Power_setDependency(PowerCC26X2_PERIPH_PKA); + + return handle; +} + +/* + * ======== ECDSA_sign ======== + */ +int_fast16_t ECDSA_sign(ECDSA_Handle handle, ECDSA_OperationSign *operation) { + ECDSACC26X2_Object *object = handle->object; + ECDSACC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + DebugP_assert(handle); + DebugP_assert(operation); + DebugP_assert(operation->eccParams); + DebugP_assert(operation->eccParams->length == myPrivateKey->u.plaintext.keyLength); + DebugP_assert(operation->myPrivateKey->encoding == CryptoKey_PLAINTEXT); + DebugP_assert(operation->hash); + DebugP_assert(operation->r); + DebugP_assert(operation->s); + DebugP_assert(operation->pmsn); + + if (ECDSACC26X2_waitForAccess(handle) != SemaphoreP_OK) { + return ECDSA_STATUS_RESOURCE_UNAVAILABLE; + } + + object->operation.sign = operation; + object->operationType = ECDSA_OPERATION_TYPE_SIGN; + object->fsmState = ECDSACC26X2_FSM_SIGN_VALIDATE_PMSN; + object->fsmFxn = ECDSACC26X2_runSignFSM; + object->operationStatus = ECDSA_STATUS_ERROR; + object->operationCanceled = false; + scratchBufferSize = ECDSACC26X2_SCRATCH_BUFFER_SIZE; + scratchBuffer2Size = ECDSACC26X2_SCRATCH_BUFFER_SIZE; + + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECDSACC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return ECDSACC26X2_waitForResult(handle); +} + +/* + * ======== ECDSA_verify ======== + */ +int_fast16_t ECDSA_verify(ECDSA_Handle handle, ECDSA_OperationVerify *operation) { + ECDSACC26X2_Object *object = handle->object; + ECDSACC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + DebugP_assert(handle); + DebugP_assert(operation); + DebugP_assert(operation->eccParams); + DebugP_assert(operation->eccParams->length == theirPublicKey->u.plaintext.keyLength / 2); + DebugP_assert(operation->theirPublicKey->encoding == CryptoKey_PLAINTEXT); + DebugP_assert(operation->hash); + DebugP_assert(operation->r); + DebugP_assert(operation->s); + + + if (ECDSACC26X2_waitForAccess(handle) != SemaphoreP_OK) { + return ECDSA_STATUS_RESOURCE_UNAVAILABLE; + } + + + object->operation.verify = operation; + object->operationType = ECDSA_OPERATION_TYPE_VERIFY; + object->fsmState = ECDSACC26X2_FSM_VERIFY_R_S_IN_RANGE; + object->fsmFxn = ECDSACC26X2_runVerifyFSM; + object->operationStatus = ECDSA_STATUS_ERROR; + object->operationCanceled = false; + scratchBufferSize = ECDSACC26X2_SCRATCH_BUFFER_SIZE; + scratchBuffer2Size = ECDSACC26X2_SCRATCH_BUFFER_SIZE; + + + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECDSACC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return ECDSACC26X2_waitForResult(handle); +} + +/* + * ======== ECDSA_cancelOperation ======== + */ +int_fast16_t ECDSA_cancelOperation(ECDSA_Handle handle) { + ECDSACC26X2_Object *object = handle->object; + + if(!object->operationInProgress){ + return ECDSA_STATUS_ERROR; + } + + object->operationCanceled = true; + + /* Post hwi as if operation finished for cleanup */ + IntEnable(INT_PKA_IRQ); + HwiP_post(INT_PKA_IRQ); + + + return ECDSA_STATUS_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdsa/ECDSACC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdsa/ECDSACC26X2.h new file mode 100644 index 0000000..64aa1ec --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdsa/ECDSACC26X2.h @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECDSACC26X2.h + * + * @brief ECDSA driver implementation for the CC26X2 family + * + * This file should only be included in the board file to fill the ECDSA_config + * struct. + * + * # Hardware and Implementation Details # + * + * The CC26X2 family has a dedicated public key accelerator. + * It is capable of multiple mathematical operations including dedicated ECC point addition, doubling, + * and scalar multiplication. Only one operation can be carried out on the accelerator + * at a time. Mutual exclusion is implemented at the driver level and coordinated + * between all drivers relying on the accelerator. It is transparent to the application + * and only noted ensure sensible access timeouts are set. + * + * The large number maths engine (LNME) uses a dedicated 2kB block of RAM (PKA RAM) for its operations. + * The operands of the maths operations must be copied into and results out of the PKA ram. + * This necessitates a significant number of reads and writes for each operation. + * The bus interface to the RAM only allows for word-aligned reads and writes. The CPU splits + * the reads and writes from and to general SRAM from unaligned addresses into multiple + * bus operations while accumulating the data in a register until it is full. + * The result of this hardware process is that providing buffers such as plaintext CryptoKey + * keying material to ECC APIs that are word-aligned will significantly speed up the operation and + * reduce power consumption. + * + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + * + * # Supported Curve Types # + * + * The driver implementation supports the following curve types for ECDSA: + * + * | Curve Type | Supported | + * |-------------------|-----------| + * | Short Weierstrass | Yes | + * | Montgomery | No | + * | Edwards | No | + * + * # Public Key Validation # + * + * When performing signature verification, the foreign public key will always be validated. + * However, the implementation assumes that the cofactor, h, of the curve is 1. This lets us + * skip the computationally expensive step of multiplying the foreign key by the order and + * checking if it yields the point at infinity. When the cofactor is 1, this property is + * implied by validating that the point is not already the point at infinity and that it + * validates against the curve equation. + * All curves supplied by default, the NIST and Brainpool curves, have cofactor = 1. While + * the implementation can use arbitrary curves, you should verify that any other curve used + * has a cofactor of 1. + */ + +#ifndef ti_drivers_ecdsa_ECDSACC26X2__include +#define ti_drivers_ecdsa_ECDSACC26X2__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +/* Exit the SWI and wait until an HWI call posts the SWI again */ +#define ECDSACC26X2_STATUS_FSM_RUN_PKA_OP ECDSA_STATUS_RESERVED - 0 +/* Execute the next FSM state immediately without waiting for the next HWI */ +#define ECDSACC26X2_STATUS_FSM_RUN_FSM ECDSA_STATUS_RESERVED - 1 + +/*! + * @brief ECDSACC26X2 Sign and Verify states + * + * The sign and verify operations are implemented using multiple invidividual + * PKA operations. Since state transitions for these operations are almost + * always predictable, the state transitions are encoded linearly in this enum. + * The FSM controller will increment the state counter and iterate through + * states until it is told to stop or restart. + */ +typedef enum ECDSACC26X2_FsmState_ { + ECDSACC26X2_FSM_ERROR = 0, + + ECDSACC26X2_FSM_SIGN_VALIDATE_PMSN, + ECDSACC26X2_FSM_SIGN_COMPUTE_R, + ECDSACC26X2_FSM_SIGN_COMPUTE_R_RESULT, + ECDSACC26X2_FSM_SIGN_R_MOD_N, + ECDSACC26X2_FSM_SIGN_R_MOD_N_RESULT, + ECDSACC26X2_FSM_SIGN_COMPUTE_PMSN_INVERSE, + ECDSACC26X2_FSM_SIGN_COMPUTE_PMSN_INVERSE_RESULT, + ECDSACC26X2_FSM_SIGN_COMPUTE_PRIVATE_KEY_X_R, + ECDSACC26X2_FSM_SIGN_COMPUTE_PRIVATE_KEY_X_R_RESULT, + ECDSACC26X2_FSM_SIGN_ADD_HASH, + ECDSACC26X2_FSM_SIGN_ADD_HASH_RESULT, + ECDSACC26X2_FSM_SIGN_MULT_BY_PMSN_INVERSE, + ECDSACC26X2_FSM_SIGN_MULT_BY_PMSN_INVERSE_RESULT, + ECDSACC26X2_FSM_SIGN_MOD_N, + ECDSACC26X2_FSM_SIGN_MOD_N_RESULT, + + ECDSACC26X2_FSM_VERIFY_R_S_IN_RANGE, + ECDSACC26X2_FSM_VERIFY_VALIDATE_PUBLIC_KEY, + ECDSACC26X2_FSM_VERIFY_COMPUTE_S_INV, + ECDSACC26X2_FSM_VERIFY_COMPUTE_S_INV_RESULT, + ECDSACC26X2_FSM_VERIFY_MULT_S_INV_HASH, + ECDSACC26X2_FSM_VERIFY_MULT_S_INV_HASH_RESULT, + ECDSACC26X2_FSM_VERIFY_S_INV_MULT_HASH_MOD_N, + ECDSACC26X2_FSM_VERIFY_S_INV_MULT_HASH_MOD_N_RESULT, + ECDSACC26X2_FSM_VERIFY_MULT_G, + ECDSACC26X2_FSM_VERIFY_MULT_G_RESULT, + ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R, + ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R_RESULT, + ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R_MOD_N, + ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R_MOD_N_RESULT, + ECDSACC26X2_FSM_VERIFY_MULT_PUB_KEY, + ECDSACC26X2_FSM_VERIFY_MULT_PUB_KEY_RESULT, + ECDSACC26X2_FSM_VERIFY_ADD_MULT_RESULTS, + ECDSACC26X2_FSM_VERIFY_ADD_MULT_RESULTS_RESULT, + ECDSACC26X2_FSM_VERIFY_POINTX_MOD_N, + ECDSACC26X2_FSM_VERIFY_POINTX_MOD_N_RESULT, + ECDSACC26X2_FSM_VERIFY_COMPARE_RESULT_R, + +} ECDSACC26X2_FsmState; + +/*! + * @brief ECDSACC26X2 state machine function prototype + * + * The FSM controller in the ECDSACC26X2 SWI executes a state machine function + * containing a switch statement that governs state execution. This function + * pointer is stored in the object at the beginning of the transaction. + * This way, unused state machines are removed at link time. + */ +typedef int_fast16_t (*ECDSACC26X2_stateMachineFxn) (ECDSA_Handle handle); + +/*! + * @brief ECDSACC26X2 Hardware Attributes + * + * ECDSACC26X2 hardware attributes should be included in the board file + * and pointed to by the ECDSA_config struct. + */ +typedef struct ECDSACC26X2_HWAttrs_ { + /*! @brief PKA Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; +} ECDSACC26X2_HWAttrs; + +/*! + * @brief ECDSACC26X2 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct ECDSACC26X2_Object_ { + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t operationStatus; + ECDSA_Operation operation; + ECDSA_OperationType operationType; + ECDSA_CallbackFxn callbackFxn; + ECDSACC26X2_stateMachineFxn fsmFxn; + ECDSA_ReturnBehavior returnBehavior; + ECDSACC26X2_FsmState fsmState; + uint32_t semaphoreTimeout; + uint32_t resultAddress; + uint32_t *scratchNumber1; + uint32_t *scratchNumber2; +} ECDSACC26X2_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecdsa_ECDSACC26X2__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecjpake/ECJPAKECC26X2.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecjpake/ECJPAKECC26X2.c new file mode 100644 index 0000000..7592dab --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecjpake/ECJPAKECC26X2.c @@ -0,0 +1,1324 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_pka.h) +#include DeviceFamily_constructPath(inc/hw_pka_ram.h) +#include DeviceFamily_constructPath(driverlib/pka.h) +#include DeviceFamily_constructPath(driverlib/trng.h) + +#define ECJPAKECC26X2_SCRATCH_BUFFER_SIZE 256 + +/* Since we only support <= 384-bit curves, we can allocate two temporary buffers + * at the midway address in PKA_RAM. This leaves us with 1024 bytes of RAM + * to work with. That should be sufficient for our needs. Multiplications will + * take up to 3x the curve param length of 384 bits or 48 bytes. ECC addition + * requires 8x the curve param length in RAM. 1024 bytes would even suffice + * for 384-bit curves. + */ +#define ECJPAKECC26X2_SCRATCH_BUFFER ((uint8_t *)(PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE / 2)) +#define ECJPAKECC26X2_SCRATCH_BUFFER_2 ((uint8_t *)(PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE / 2 + ECJPAKECC26X2_SCRATCH_BUFFER_SIZE)) + +#define MAX(x,y) (((x) > (y)) ? (x) : (y)) + +/* Forward declarations */ +static void ECJPAKECC26X2_hwiFxn (uintptr_t arg0); +static void ECJPAKECC26X2_internalCallbackFxn (ECJPAKE_Handle handle, + int_fast16_t returnStatus, + ECJPAKE_Operation operation, + ECJPAKE_OperationType operationType); +static int_fast16_t ECJPAKECC26X2_waitForAccess(ECJPAKE_Handle handle); +static int_fast16_t ECJPAKECC26X2_waitForResult(ECJPAKE_Handle handle); +static int_fast16_t ECJPAKECC26X2_runFSM(ECJPAKE_Handle handle); +static int_fast16_t ECJPAKECC26X2_convertReturnValue(uint32_t pkaResult); + +/* Extern globals */ +extern const ECJPAKE_Config ECJPAKE_config[]; +extern const uint_least8_t ECJPAKE_count; +extern const ECJPAKE_Params ECJPAKE_defaultParams; + +/* Static globals */ +static bool isInitialized = false; + +static uint32_t scratchBufferSize = ECJPAKECC26X2_SCRATCH_BUFFER_SIZE; + + +/* + * ======== ECJPAKECC26X2_internalCallbackFxn ======== + */ +static void ECJPAKECC26X2_internalCallbackFxn (ECJPAKE_Handle handle, + int_fast16_t returnStatus, + ECJPAKE_Operation operation, + ECJPAKE_OperationType operationType) { + ECJPAKECC26X2_Object *object = handle->object; + + /* This function is only ever registered when in ECJPAKE_RETURN_BEHAVIOR_BLOCKING + * or ECJPAKE_RETURN_BEHAVIOR_POLLING. + */ + if (object->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_BLOCKING) { + SemaphoreP_post(&PKAResourceCC26XX_operationSemaphore); + } + else { + PKAResourceCC26XX_pollingFlag = 1; + } +} + +/* + * ======== ECJPAKECC26X2_hwiFxn ======== + */ +static void ECJPAKECC26X2_hwiFxn (uintptr_t arg0) { + ECJPAKECC26X2_Object *object = ((ECJPAKE_Handle)arg0)->object; + uint32_t key; + + /* Disable interrupt again */ + IntDisable(INT_PKA_IRQ); + + do { + object->operationStatus = ECJPAKECC26X2_runFSM((ECJPAKE_Handle)arg0); + object->fsmState++; + } while (object->operationStatus == ECJPAKECC26X2_STATUS_FSM_RUN_FSM); + + /* We need a critical section here in case the operation is canceled + * asynchronously. + */ + key = HwiP_disable(); + + if(object->operationCanceled) { + /* Set function register to 0. This should stop the current operation */ + HWREG(PKA_BASE + PKA_O_FUNCTION) = 0; + + object->operationStatus = ECJPAKE_STATUS_CANCELED; + } + + switch (object->operationStatus) { + case ECJPAKECC26X2_STATUS_FSM_RUN_PKA_OP: + + HwiP_restore(key); + + /* Do nothing. The PKA hardware + * will execute in the background and post + * this SWI when it is done. + */ + break; + case ECJPAKE_STATUS_SUCCESS: + /* Intentional fall through */ + case ECJPAKE_STATUS_ERROR: + /* Intentional fall through */ + case ECJPAKE_STATUS_CANCELED: + /* Intentional fall through */ + default: + + /* Mark this operation as complete */ + object->operationInProgress = false; + + /* Clear any pending interrupt in case a transaction kicked off + * above already finished + */ + IntDisable(INT_PKA_IRQ); + IntPendClear(INT_PKA_IRQ); + + /* We can end the critical section since the operation may no + * longer be canceled + */ + HwiP_restore(key); + + /* Make sure there is no keying material remaining in PKA RAM */ + PKAClearPkaRam(); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&PKAResourceCC26XX_accessSemaphore); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->callbackFxn((ECJPAKE_Handle)arg0, + object->operationStatus, + object->operation, + object->operationType); + } +} + +/* + * ======== ECJPAKECC26X2_runSignFSM ======== + */ +static int_fast16_t ECJPAKECC26X2_runFSM(ECJPAKE_Handle handle) { + static uint32_t resultAddress; + ECJPAKECC26X2_Object *object = handle->object; + uint32_t pkaResult; + uint32_t i; + + switch (object->fsmState) { + /* ==================================================================== + * ROUND ONE KEY GENERATION FSM STATE IMPLEMENTATIONS + * ==================================================================== + */ + case ECJPAKECC26X2_FSM_ROUND_ONE_VALIDATE_MYPRIVATEKEY1: + + if (PKAArrayAllZeros(object->operation.generateRoundOneKeys->myPrivateKey1->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->curve->length)) { + return ECJPAKE_STATUS_INVALID_PRIVATE_KEY; + } + + PKABigNumCmpStart(object->operation.generateRoundOneKeys->myPrivateKey1->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->curve->order, + object->operation.generateRoundOneKeys->curve->length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return ECJPAKE_STATUS_INVALID_PRIVATE_KEY; + } + else { + return ECJPAKECC26X2_STATUS_FSM_RUN_FSM; + } + + case ECJPAKECC26X2_FSM_ROUND_ONE_VALIDATE_MYPRIVATEKEY2: + + if (PKAArrayAllZeros(object->operation.generateRoundOneKeys->myPrivateKey2->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->curve->length)) { + return ECJPAKE_STATUS_INVALID_PRIVATE_KEY; + } + + PKABigNumCmpStart(object->operation.generateRoundOneKeys->myPrivateKey2->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->curve->order, + object->operation.generateRoundOneKeys->curve->length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return ECJPAKE_STATUS_INVALID_PRIVATE_KEY; + } + else { + return ECJPAKECC26X2_STATUS_FSM_RUN_FSM; + } + + case ECJPAKECC26X2_FSM_ROUND_ONE_VALIDATE_MYPRIVATEV1: + + if (PKAArrayAllZeros(object->operation.generateRoundOneKeys->myPrivateV1->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->curve->length)) { + return ECJPAKE_STATUS_INVALID_PRIVATE_V; + } + + PKABigNumCmpStart(object->operation.generateRoundOneKeys->myPrivateV1->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->curve->order, + object->operation.generateRoundOneKeys->curve->length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return ECJPAKE_STATUS_INVALID_PRIVATE_V; + } + else { + return ECJPAKECC26X2_STATUS_FSM_RUN_FSM; + } + + + case ECJPAKECC26X2_FSM_ROUND_ONE_VALIDATE_MYPRIVATEV2: + + if (PKAArrayAllZeros(object->operation.generateRoundOneKeys->myPrivateV2->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->curve->length)) { + return ECJPAKE_STATUS_INVALID_PRIVATE_V; + } + + PKABigNumCmpStart(object->operation.generateRoundOneKeys->myPrivateV2->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->curve->order, + object->operation.generateRoundOneKeys->curve->length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return ECJPAKE_STATUS_INVALID_PRIVATE_V; + } + else { + return ECJPAKECC26X2_STATUS_FSM_RUN_FSM; + } + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY1: + + PKAEccMultiplyStart(object->operation.generateRoundOneKeys->myPrivateKey1->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->curve->generatorX, + object->operation.generateRoundOneKeys->curve->generatorY, + object->operation.generateRoundOneKeys->curve->prime, + object->operation.generateRoundOneKeys->curve->a, + object->operation.generateRoundOneKeys->curve->b, + object->operation.generateRoundOneKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY1_RESULT: + + pkaResult = PKAEccMultiplyGetResult(object->operation.generateRoundOneKeys->myPublicKey1->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->myPublicKey1->u.plaintext.keyMaterial + + object->operation.generateRoundOneKeys->curve->length, + resultAddress, + object->operation.generateRoundOneKeys->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY2: + + PKAEccMultiplyStart(object->operation.generateRoundOneKeys->myPrivateKey2->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->curve->generatorX, + object->operation.generateRoundOneKeys->curve->generatorY, + object->operation.generateRoundOneKeys->curve->prime, + object->operation.generateRoundOneKeys->curve->a, + object->operation.generateRoundOneKeys->curve->b, + object->operation.generateRoundOneKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY2_RESULT: + + pkaResult = PKAEccMultiplyGetResult(object->operation.generateRoundOneKeys->myPublicKey2->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->myPublicKey2->u.plaintext.keyMaterial + + object->operation.generateRoundOneKeys->curve->length, + resultAddress, + object->operation.generateRoundOneKeys->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV1: + + PKAEccMultiplyStart(object->operation.generateRoundOneKeys->myPrivateV1->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->curve->generatorX, + object->operation.generateRoundOneKeys->curve->generatorY, + object->operation.generateRoundOneKeys->curve->prime, + object->operation.generateRoundOneKeys->curve->a, + object->operation.generateRoundOneKeys->curve->b, + object->operation.generateRoundOneKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV1_RESULT: + + pkaResult = PKAEccMultiplyGetResult(object->operation.generateRoundOneKeys->myPublicV1->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->myPublicV1->u.plaintext.keyMaterial + + object->operation.generateRoundOneKeys->curve->length, + resultAddress, + object->operation.generateRoundOneKeys->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV2: + + PKAEccMultiplyStart(object->operation.generateRoundOneKeys->myPrivateV2->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->curve->generatorX, + object->operation.generateRoundOneKeys->curve->generatorY, + object->operation.generateRoundOneKeys->curve->prime, + object->operation.generateRoundOneKeys->curve->a, + object->operation.generateRoundOneKeys->curve->b, + object->operation.generateRoundOneKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV2_RESULT: + + pkaResult = PKAEccMultiplyGetResult(object->operation.generateRoundOneKeys->myPublicV2->u.plaintext.keyMaterial, + object->operation.generateRoundOneKeys->myPublicV2->u.plaintext.keyMaterial + + object->operation.generateRoundOneKeys->curve->length, + resultAddress, + object->operation.generateRoundOneKeys->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + /* ==================================================================== + * GENERATE ZKP FSM STATE IMPLEMENTATIONS + * ==================================================================== + */ + case ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH: + + PKABigNumMultiplyStart(object->operation.generateZKP->myPrivateKey->u.plaintext.keyMaterial, + object->operation.generateZKP->curve->length, + object->operation.generateZKP->hash, + object->operation.generateZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH_RESULT: + + pkaResult = PKABigNumMultGetResult(ECJPAKECC26X2_SCRATCH_BUFFER, + &scratchBufferSize, + resultAddress); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH_MOD_N: + + /* Zero out the buffer up to the curve length. The PKA hardware cannot + * handle modulus operations where the byte-length of the dividend is smaller + * than the divisor. + */ + if (object->operation.generateZKP->curve->length > scratchBufferSize) { + PKAZeroOutArray(ECJPAKECC26X2_SCRATCH_BUFFER + scratchBufferSize, + object->operation.generateZKP->curve->length - scratchBufferSize); + } + + /* The scratch buffer content has a real length of scratchBufferSize but is + * zero-extended until curve->length. We cannot start a modulo operation on + * the PKA where dividend length < divisor length. Hence, the buffer size + * always needs to be >= curve->length. + */ + PKABigNumModStart(ECJPAKECC26X2_SCRATCH_BUFFER, + MAX(scratchBufferSize, object->operation.generateZKP->curve->length), + object->operation.generateZKP->curve->order, + object->operation.generateZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult(object->operation.generateZKP->r, + object->operation.generateZKP->curve->length, + resultAddress); + + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_ADD_V_TO_N: + + PKABigNumAddStart(object->operation.generateZKP->myPrivateV->u.plaintext.keyMaterial, + object->operation.generateZKP->curve->length, + object->operation.generateZKP->curve->order, + object->operation.generateZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_ADD_V_TO_N_RESULT: + + scratchBufferSize = ECJPAKECC26X2_SCRATCH_BUFFER_SIZE; + + pkaResult = PKABigNumAddGetResult(ECJPAKECC26X2_SCRATCH_BUFFER, + &scratchBufferSize, + resultAddress); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULTS: + + PKABigNumSubStart(ECJPAKECC26X2_SCRATCH_BUFFER, + scratchBufferSize, + object->operation.generateZKP->r, + object->operation.generateZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULTS_RESULT: + + scratchBufferSize = ECJPAKECC26X2_SCRATCH_BUFFER_SIZE; + + pkaResult = PKABigNumSubGetResult(ECJPAKECC26X2_SCRATCH_BUFFER, + &scratchBufferSize, + resultAddress); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULT_MOD_N: + + /* Zero out the buffer up to the curve length. The PKA hardware cannot + * handle modulus operations where the byte-length of the dividend is smaller + * than the divisor. + */ + if (object->operation.generateZKP->curve->length > scratchBufferSize) { + PKAZeroOutArray(ECJPAKECC26X2_SCRATCH_BUFFER + scratchBufferSize, + object->operation.generateZKP->curve->length - scratchBufferSize); + } + + /* The scratch buffer content has a real length of scratchBufferSize but is + * zero-extended until curve->length. We cannot start a modulo operation on + * the PKA where dividend length < divisor length. Hence, the buffer size + * always needs to be >= curve->length. + */ + PKABigNumModStart(ECJPAKECC26X2_SCRATCH_BUFFER, + MAX(scratchBufferSize, object->operation.generateZKP->curve->length), + object->operation.generateZKP->curve->order, + object->operation.generateZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULT_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult(object->operation.generateZKP->r, + object->operation.generateZKP->curve->length, + resultAddress); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + /* ==================================================================== + * VERIFY ZKP FSM STATE IMPLEMENTATIONS + * ==================================================================== + */ + case ECJPAKECC26X2_FSM_VERIFY_ZKP_VALIDATE_PUBLIC_KEY: + + pkaResult = PKAEccVerifyPublicKeyWeierstrassStart(object->operation.verifyZKP->theirPublicKey->u.plaintext.keyMaterial, + object->operation.verifyZKP->theirPublicKey->u.plaintext.keyMaterial + + object->operation.verifyZKP->curve->length, + object->operation.verifyZKP->curve->prime, + object->operation.verifyZKP->curve->a, + object->operation.verifyZKP->curve->b, + object->operation.verifyZKP->curve->order, + object->operation.verifyZKP->curve->length); + + // Break out early since no PKA operation was started by the verify fxn + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_G_BY_R: + + PKAEccMultiplyStart(object->operation.verifyZKP->r, + object->operation.verifyZKP->theirGenerator->u.plaintext.keyMaterial, + object->operation.verifyZKP->theirGenerator->u.plaintext.keyMaterial + + object->operation.verifyZKP->curve->length, + object->operation.verifyZKP->curve->prime, + object->operation.verifyZKP->curve->a, + object->operation.verifyZKP->curve->b, + object->operation.verifyZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_G_BY_R_RESULT: + + pkaResult = PKAEccMultiplyGetResult(ECJPAKECC26X2_SCRATCH_BUFFER, + ECJPAKECC26X2_SCRATCH_BUFFER + object->operation.verifyZKP->curve->length, + resultAddress, + object->operation.verifyZKP->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_HASH_MOD_N: + + PKABigNumModStart(object->operation.verifyZKP->hash, + object->operation.verifyZKP->curve->length, + object->operation.verifyZKP->curve->order, + object->operation.verifyZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_HASH_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult(ECJPAKECC26X2_SCRATCH_BUFFER_2, + object->operation.verifyZKP->curve->length, + resultAddress); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_X_BY_HASH: + + PKAEccMultiplyStart(ECJPAKECC26X2_SCRATCH_BUFFER_2, + object->operation.verifyZKP->theirPublicKey->u.plaintext.keyMaterial, + object->operation.verifyZKP->theirPublicKey->u.plaintext.keyMaterial + + object->operation.verifyZKP->curve->length, + object->operation.verifyZKP->curve->prime, + object->operation.verifyZKP->curve->a, + object->operation.verifyZKP->curve->b, + object->operation.verifyZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_X_BY_HASH_RESULT: + + pkaResult = PKAEccMultiplyGetResult(ECJPAKECC26X2_SCRATCH_BUFFER_2, + ECJPAKECC26X2_SCRATCH_BUFFER_2 + object->operation.verifyZKP->curve->length, + resultAddress, + object->operation.verifyZKP->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_ADD_RESULTS: + + PKAEccAddStart(ECJPAKECC26X2_SCRATCH_BUFFER, + ECJPAKECC26X2_SCRATCH_BUFFER + object->operation.verifyZKP->curve->length, + ECJPAKECC26X2_SCRATCH_BUFFER_2, + ECJPAKECC26X2_SCRATCH_BUFFER_2 + object->operation.verifyZKP->curve->length, + object->operation.verifyZKP->curve->prime, + object->operation.verifyZKP->curve->a, + object->operation.verifyZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_ADD_RESULTS_RESULT: + + pkaResult = PKAEccAddGetResult(ECJPAKECC26X2_SCRATCH_BUFFER, + ECJPAKECC26X2_SCRATCH_BUFFER + object->operation.verifyZKP->curve->length, + resultAddress, + object->operation.verifyZKP->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_COMPARE_AGAINST_V: + + /* Compare 2 * curve length since we wish to check the entire point not just the X coordinate */ + for (i = 0; i < (2 * object->operation.verifyZKP->curve->length) / sizeof(uint32_t); i++) { + if (((uint32_t *)object->operation.verifyZKP->theirPublicV->u.plaintext.keyMaterial)[i] != ((uint32_t *)ECJPAKECC26X2_SCRATCH_BUFFER)[i]) { + return ECJPAKE_STATUS_ERROR; + } + } + + return ECJPAKE_STATUS_SUCCESS; + + /* ==================================================================== + * ROUND TWO KEY GENERATION FSM STATE IMPLEMENTATIONS + * ==================================================================== + */ + case ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYPRIVATEKEY2_BY_PRESHAREDSECRET: + + PKABigNumMultiplyStart(object->operation.generateRoundTwoKeys->myPrivateKey2->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->curve->length, + object->operation.generateRoundTwoKeys->preSharedSecret->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->preSharedSecret->u.plaintext.keyLength, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYPRIVATEKEY2_BY_PRESHAREDSECRET_RESULT: + + pkaResult = PKABigNumMultGetResult(ECJPAKECC26X2_SCRATCH_BUFFER, + &scratchBufferSize, + resultAddress); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_ROUND_TWO_MYCOMBINEDPRIVATEKEY_MOD_N: + + /* Zero out the buffer up to the curve length. The PKA hardware cannot + * handle modulus operations where the byte-length of the dividend is smaller + * than the divisor. + */ + if (object->operation.generateRoundTwoKeys->curve->length > scratchBufferSize) { + PKAZeroOutArray(ECJPAKECC26X2_SCRATCH_BUFFER + scratchBufferSize, + object->operation.generateRoundTwoKeys->curve->length - scratchBufferSize); + } + + /* The scratch buffer content has a real length of scratchBufferSize but is + * zero-extended until curve->length. We cannot start a modulo operation on + * the PKA where dividend length < divisor length. Hence, the buffer size + * always needs to be >= curve->length. + */ + PKABigNumModStart(ECJPAKECC26X2_SCRATCH_BUFFER, + MAX(scratchBufferSize, object->operation.generateRoundTwoKeys->curve->length), + object->operation.generateRoundTwoKeys->curve->order, + object->operation.generateRoundTwoKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_MYCOMBINEDPRIVATEKEY_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult(object->operation.generateRoundTwoKeys->myCombinedPrivateKey->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->curve->length, + resultAddress); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + + case ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY1_TO_THEIRPUBLICKEY1: + + PKAEccAddStart(object->operation.generateRoundTwoKeys->myPublicKey1->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->myPublicKey1->u.plaintext.keyMaterial + + object->operation.generateRoundTwoKeys->curve->length, + object->operation.generateRoundTwoKeys->theirPublicKey1->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->theirPublicKey1->u.plaintext.keyMaterial + + object->operation.generateRoundTwoKeys->curve->length, + object->operation.generateRoundTwoKeys->curve->prime, + object->operation.generateRoundTwoKeys->curve->a, + object->operation.generateRoundTwoKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY1_TO_THEIRPUBLICKEY1_RESULT: + + pkaResult = PKAEccAddGetResult(ECJPAKECC26X2_SCRATCH_BUFFER, + ECJPAKECC26X2_SCRATCH_BUFFER + object->operation.generateRoundTwoKeys->curve->length, + resultAddress, + object->operation.generateRoundTwoKeys->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_ROUND_TWO_ADD_THEIRPUBLICKEY2: + + PKAEccAddStart(ECJPAKECC26X2_SCRATCH_BUFFER, + ECJPAKECC26X2_SCRATCH_BUFFER + object->operation.generateRoundTwoKeys->curve->length, + object->operation.generateRoundTwoKeys->theirPublicKey2->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->theirPublicKey2->u.plaintext.keyMaterial + + object->operation.generateRoundTwoKeys->curve->length, + object->operation.generateRoundTwoKeys->curve->prime, + object->operation.generateRoundTwoKeys->curve->a, + object->operation.generateRoundTwoKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_ADD_THEIRPUBLICKEY2_RESULT: + + pkaResult = PKAEccAddGetResult(object->operation.generateRoundTwoKeys->myNewGenerator->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->myNewGenerator->u.plaintext.keyMaterial + + object->operation.generateRoundTwoKeys->curve->length, + resultAddress, + object->operation.generateRoundTwoKeys->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY2: + + PKAEccAddStart(ECJPAKECC26X2_SCRATCH_BUFFER, + ECJPAKECC26X2_SCRATCH_BUFFER + object->operation.generateRoundTwoKeys->curve->length, + object->operation.generateRoundTwoKeys->myPublicKey2->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->myPublicKey2->u.plaintext.keyMaterial + + object->operation.generateRoundTwoKeys->curve->length, + object->operation.generateRoundTwoKeys->curve->prime, + object->operation.generateRoundTwoKeys->curve->a, + object->operation.generateRoundTwoKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY2_RESULT: + + pkaResult = PKAEccAddGetResult(object->operation.generateRoundTwoKeys->theirNewGenerator->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->theirNewGenerator->u.plaintext.keyMaterial + + object->operation.generateRoundTwoKeys->curve->length, + resultAddress, + object->operation.generateRoundTwoKeys->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + + case ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYCOMBINEDPRIVATEKEY_BY_MYNEWGENERATOR: + + PKAEccMultiplyStart(object->operation.generateRoundTwoKeys->myCombinedPrivateKey->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->myNewGenerator->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->myNewGenerator->u.plaintext.keyMaterial + + object->operation.generateRoundTwoKeys->curve->length, + object->operation.generateRoundTwoKeys->curve->prime, + object->operation.generateRoundTwoKeys->curve->a, + object->operation.generateRoundTwoKeys->curve->b, + object->operation.generateRoundTwoKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYCOMBINEDPRIVATEKEY_BY_MYNEWGENERATOR_RESULT: + + pkaResult = PKAEccMultiplyGetResult(object->operation.generateRoundTwoKeys->myCombinedPublicKey->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->myCombinedPublicKey->u.plaintext.keyMaterial + + object->operation.generateRoundTwoKeys->curve->length, + resultAddress, + object->operation.generateRoundTwoKeys->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_ROUND_TWO_VALIDATE_MYPRIVATEV: + + if (PKAArrayAllZeros(object->operation.generateRoundTwoKeys->myPrivateV->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->curve->length)) { + return ECJPAKE_STATUS_INVALID_PRIVATE_KEY; + } + + PKABigNumCmpStart(object->operation.generateRoundTwoKeys->myPrivateV->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->curve->order, + object->operation.generateRoundTwoKeys->curve->length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return ECJPAKE_STATUS_INVALID_PRIVATE_KEY; + } + else { + return ECJPAKECC26X2_STATUS_FSM_RUN_FSM; + } + + case ECJPAKECC26X2_FSM_ROUND_TWO_GENERATE_MYPUBLICV: + + PKAEccMultiplyStart(object->operation.generateRoundTwoKeys->myPrivateV->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->myNewGenerator->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->myNewGenerator->u.plaintext.keyMaterial + + object->operation.generateRoundTwoKeys->curve->length, + object->operation.generateRoundTwoKeys->curve->prime, + object->operation.generateRoundTwoKeys->curve->a, + object->operation.generateRoundTwoKeys->curve->b, + object->operation.generateRoundTwoKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_GENERATE_MYPUBLICV_RESULT: + + pkaResult = PKAEccMultiplyGetResult(object->operation.generateRoundTwoKeys->myPublicV->u.plaintext.keyMaterial, + object->operation.generateRoundTwoKeys->myPublicV->u.plaintext.keyMaterial + + object->operation.generateRoundTwoKeys->curve->length, + resultAddress, + object->operation.generateRoundTwoKeys->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + + /* ==================================================================== + * GENERATE SHARED SECRET FSM STATE IMPLEMENTATIONS + * ==================================================================== + */ + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_THEIRPUBLICKEY2_BY_MYCOMBINEDPRIVATEKEY: + + PKAEccMultiplyStart(object->operation.computeSharedSecret->myCombinedPrivateKey->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->theirPublicKey2->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->theirPublicKey2->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length, + object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->a, + object->operation.computeSharedSecret->curve->b, + object->operation.computeSharedSecret->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_THEIRPUBLICKEY2_BY_MYCOMBINEDPRIVATEKEY_RESULT: + + pkaResult = PKAEccMultiplyGetResult(object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length, + resultAddress, + object->operation.computeSharedSecret->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_SUB_YCOORDINATE_FROM_PRIME: + + PKABigNumSubStart(object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->length, + object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length, + object->operation.computeSharedSecret->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_SUB_YCOORDINATE_FROM_PRIME_RESULT: + + /* Use scratchBufferSize as a dummy length variable since we will not copy the + * result into the ECJPAKECC26X2_SCRATCH_BUFFER + */ + scratchBufferSize = object->operation.computeSharedSecret->curve->length; + + pkaResult = PKABigNumSubGetResult(object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length, + &scratchBufferSize, + resultAddress); + + /* Zero out the private key buffer up to the curve length. Otherwise, we may + * have rubbish floating around the buffer instead of being zero sign-extended. + */ + if (object->operation.computeSharedSecret->curve->length > scratchBufferSize) { + PKAZeroOutArray(object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length + scratchBufferSize, + object->operation.computeSharedSecret->curve->length - scratchBufferSize); + } + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_ADD_THEIRCOMBINEDPUBLICKEY: + + PKAEccAddStart(object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length, + object->operation.computeSharedSecret->theirCombinedPublicKey->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->theirCombinedPublicKey->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length, + object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->a, + object->operation.computeSharedSecret->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_ADD_THEIRCOMBINEDPUBLICKEY_RESULT: + + pkaResult = PKAEccAddGetResult(object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length, + resultAddress, + object->operation.computeSharedSecret->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_BY_MYPRIVATEKEY2: + + PKAEccMultiplyStart(object->operation.computeSharedSecret->myPrivateKey2->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length, + object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->a, + object->operation.computeSharedSecret->curve->b, + object->operation.computeSharedSecret->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_BY_MYPRIVATEKEY2_RESULT: + + pkaResult = PKAEccMultiplyGetResult(object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial, + object->operation.computeSharedSecret->sharedSecret->u.plaintext.keyMaterial + + object->operation.computeSharedSecret->curve->length, + resultAddress, + object->operation.computeSharedSecret->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_RETURN: + case ECJPAKECC26X2_FSM_ROUND_TWO_GENERATE_RETURN: + case ECJPAKECC26X2_FSM_ZKP_GENERATE_RETURN: + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_RETURN: + return ECJPAKE_STATUS_SUCCESS; + default: + return ECJPAKE_STATUS_ERROR; + } + + // If we get to this point, we want to perform another PKA operation + IntPendClear(INT_PKA_IRQ); + IntEnable(INT_PKA_IRQ); + + return ECJPAKECC26X2_STATUS_FSM_RUN_PKA_OP; +} + +/* + * ======== ECJPAKECC26X2_convertReturnValue ======== + */ +static int_fast16_t ECJPAKECC26X2_convertReturnValue(uint32_t pkaResult) { + switch (pkaResult) { + case PKA_STATUS_SUCCESS: + case PKA_STATUS_A_LESS_THAN_B: + case PKA_STATUS_EQUAL: + /* A less than B and equal only come up when checking private + * key values. They indicate a key within the correct range. + */ + return ECJPAKECC26X2_STATUS_FSM_RUN_FSM; + + case PKA_STATUS_X_ZERO: + case PKA_STATUS_Y_ZERO: + case PKA_STATUS_RESULT_0: + /* Theoretically, PKA_STATUS_RESULT_0 might be caused by other + * operations failing but the only one that really should yield + * 0 is ECC multiplication with invalid inputs that yield the + * point at infinity. + */ + return ECJPAKE_STATUS_POINT_AT_INFINITY; + + case PKA_STATUS_X_LARGER_THAN_PRIME: + case PKA_STATUS_Y_LARGER_THAN_PRIME: + return ECJPAKE_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME; + + case PKA_STATUS_POINT_NOT_ON_CURVE: + return ECJPAKE_STATUS_PUBLIC_KEY_NOT_ON_CURVE; + + default: + return ECJPAKE_STATUS_ERROR; + } +} + +/* + * ======== ECJPAKECC26X2_waitForAccess ======== + */ +static int_fast16_t ECJPAKECC26X2_waitForAccess(ECJPAKE_Handle handle) { + ECJPAKECC26X2_Object *object = handle->object; + uint32_t timeout; + + /* Set to SemaphoreP_NO_WAIT to start operations from SWI or HWI context */ + timeout = object->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_BLOCKING ? object->semaphoreTimeout : SemaphoreP_NO_WAIT; + + return SemaphoreP_pend(&PKAResourceCC26XX_accessSemaphore, timeout); +} + +/* + * ======== ECJPAKECC26X2_waitForResult ======== + */ +static int_fast16_t ECJPAKECC26X2_waitForResult(ECJPAKE_Handle handle){ + ECJPAKECC26X2_Object *object = handle->object; + + object->operationInProgress = true; + + switch (object->returnBehavior) { + case ECJPAKE_RETURN_BEHAVIOR_POLLING: + while(!PKAResourceCC26XX_pollingFlag); + return object->operationStatus; + + case ECJPAKE_RETURN_BEHAVIOR_BLOCKING: + SemaphoreP_pend(&PKAResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + return object->operationStatus; + + case ECJPAKE_RETURN_BEHAVIOR_CALLBACK: + return ECJPAKE_STATUS_SUCCESS; + + default: + return ECJPAKE_STATUS_ERROR; + } +} + + +/* + * ======== ECJPAKE_init ======== + */ +void ECJPAKE_init(void) { + PKAResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + + +/* + * ======== ECJPAKE_close ======== + */ +void ECJPAKE_close(ECJPAKE_Handle handle) { + ECJPAKECC26X2_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object */ + object = handle->object; + + /* Release power dependency on PKA Module. */ + Power_releaseDependency(PowerCC26X2_PERIPH_PKA); + + /* Mark the module as available */ + object->isOpen = false; +} + + +/* + * ======== ECJPAKE_open ======== + */ +ECJPAKE_Handle ECJPAKE_open(uint_least8_t index, ECJPAKE_Params *params) { + ECJPAKE_Handle handle; + ECJPAKECC26X2_Object *object; + uint_fast8_t key; + + handle = (ECJPAKE_Handle)&(ECJPAKE_config[index]); + object = handle->object; + + /* If params are NULL, use defaults */ + if (params == NULL) { + params = (ECJPAKE_Params *)&ECJPAKE_defaultParams; + } + + DebugP_assert(index < ECJPAKE_count); + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + DebugP_assert((params->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_CALLBACK) ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : ECJPAKECC26X2_internalCallbackFxn; + object->semaphoreTimeout = params->timeout; + + /* Set power dependency - i.e. power up and enable clock for PKA (PKAResourceCC26XX) module. */ + Power_setDependency(PowerCC26X2_PERIPH_PKA); + + return handle; +} + +/* + * ======== ECJPAKE_roundOneGenerateKeys ======== + */ +int_fast16_t ECJPAKE_roundOneGenerateKeys(ECJPAKE_Handle handle, ECJPAKE_OperationRoundOneGenerateKeys *operation) { + ECJPAKECC26X2_Object *object = handle->object; + ECJPAKECC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (ECJPAKECC26X2_waitForAccess(handle) != SemaphoreP_OK) { + return ECJPAKE_STATUS_RESOURCE_UNAVAILABLE; + } + + /* Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->fsmState = ECJPAKECC26X2_FSM_ROUND_ONE_VALIDATE_MYPRIVATEKEY1; + object->operationStatus = ECJPAKE_STATUS_ERROR; + object->operation.generateRoundOneKeys = operation; + object->operationType = ECJPAKE_OPERATION_TYPE_ROUND_ONE_GENERATE_KEYS; + object->operationCanceled = false; + scratchBufferSize = ECJPAKECC26X2_SCRATCH_BUFFER_SIZE; + + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECJPAKECC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return ECJPAKECC26X2_waitForResult(handle); +} + +/* + * ======== ECJPAKE_generateZKP ======== + */ +int_fast16_t ECJPAKE_generateZKP(ECJPAKE_Handle handle, ECJPAKE_OperationGenerateZKP *operation) { + ECJPAKECC26X2_Object *object = handle->object; + ECJPAKECC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (ECJPAKECC26X2_waitForAccess(handle) != SemaphoreP_OK) { + return ECJPAKE_STATUS_RESOURCE_UNAVAILABLE; + } + + /* Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->fsmState = ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH; + object->operationStatus = ECJPAKE_STATUS_ERROR; + object->operation.generateZKP = operation; + object->operationType = ECJPAKE_OPERATION_TYPE_GENERATE_ZKP; + object->operationCanceled = false; + scratchBufferSize = ECJPAKECC26X2_SCRATCH_BUFFER_SIZE; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECJPAKECC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return ECJPAKECC26X2_waitForResult(handle); +} + +/* + * ======== ECJPAKE_verifyZKP ======== + */ +int_fast16_t ECJPAKE_verifyZKP(ECJPAKE_Handle handle, ECJPAKE_OperationVerifyZKP *operation) { + ECJPAKECC26X2_Object *object = handle->object; + ECJPAKECC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (ECJPAKECC26X2_waitForAccess(handle) != SemaphoreP_OK) { + return ECJPAKE_STATUS_RESOURCE_UNAVAILABLE; + } + + /* Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->fsmState = ECJPAKECC26X2_FSM_VERIFY_ZKP_VALIDATE_PUBLIC_KEY; + object->operationStatus = ECJPAKE_STATUS_ERROR; + object->operation.verifyZKP = operation; + object->operationType = ECJPAKE_OPERATION_TYPE_VERIFY_ZKP; + object->operationCanceled = false; + scratchBufferSize = ECJPAKECC26X2_SCRATCH_BUFFER_SIZE; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECJPAKECC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return ECJPAKECC26X2_waitForResult(handle); +} + +/* + * ======== ECJPAKE_roundTwoGenerateKeys ======== + */ +int_fast16_t ECJPAKE_roundTwoGenerateKeys(ECJPAKE_Handle handle, ECJPAKE_OperationRoundTwoGenerateKeys *operation) { + ECJPAKECC26X2_Object *object = handle->object; + ECJPAKECC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (ECJPAKECC26X2_waitForAccess(handle) != SemaphoreP_OK) { + return ECJPAKE_STATUS_RESOURCE_UNAVAILABLE; + } + + /* Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->fsmState = ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYPRIVATEKEY2_BY_PRESHAREDSECRET; + object->operationStatus = ECJPAKE_STATUS_ERROR; + object->operation.generateRoundTwoKeys = operation; + object->operationType = ECJPAKE_OPERATION_TYPE_ROUND_TWO_GENERATE_KEYS; + object->operationCanceled = false; + scratchBufferSize = ECJPAKECC26X2_SCRATCH_BUFFER_SIZE; + + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECJPAKECC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return ECJPAKECC26X2_waitForResult(handle); +} + +/* + * ======== ECJPAKE_computeSharedSecret ======== + */ +int_fast16_t ECJPAKE_computeSharedSecret(ECJPAKE_Handle handle, ECJPAKE_OperationComputeSharedSecret *operation) { + ECJPAKECC26X2_Object *object = handle->object; + ECJPAKECC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (ECJPAKECC26X2_waitForAccess(handle) != SemaphoreP_OK) { + return ECJPAKE_STATUS_RESOURCE_UNAVAILABLE; + } + + /* Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->fsmState = ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_THEIRPUBLICKEY2_BY_MYCOMBINEDPRIVATEKEY; + object->operationStatus = ECJPAKE_STATUS_ERROR; + object->operation.computeSharedSecret = operation; + object->operationType = ECJPAKE_OPERATION_TYPE_COMPUTE_SHARED_SECRET; + object->operationCanceled = false; + scratchBufferSize = ECJPAKECC26X2_SCRATCH_BUFFER_SIZE; + + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECJPAKECC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return ECJPAKECC26X2_waitForResult(handle); +} + +/* + * ======== ECJPAKE_cancelOperation ======== + */ +int_fast16_t ECJPAKE_cancelOperation(ECJPAKE_Handle handle) { + ECJPAKECC26X2_Object *object = handle->object; + + if(!object->operationInProgress){ + return ECJPAKE_STATUS_ERROR; + } + + object->operationCanceled = true; + + /* Post hwi as if operation finished for cleanup */ + IntEnable(INT_PKA_IRQ); + HwiP_post(INT_PKA_IRQ); + + + return ECJPAKE_STATUS_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecjpake/ECJPAKECC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecjpake/ECJPAKECC26X2.h new file mode 100644 index 0000000..75f153f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecjpake/ECJPAKECC26X2.h @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECJPAKECC26X2.h + * + * @brief ECJPAKE driver implementation for the CC26X2 family + * + * This file should only be included in the board file to fill the ECJPAKE_config + * struct. + * + * # Hardware and Implementation Details # + * + * The CC26X2 family has a dedicated public key accelerator. + * It is capable of multiple mathematical operations including dedicated ECC point addition, doubling, + * and scalar multiplication. Only one operation can be carried out on the accelerator + * at a time. Mutual exclusion is implemented at the driver level and coordinated + * between all drivers relying on the accelerator. It is transparent to the application + * and only noted ensure sensible access timeouts are set. + * + * The large number maths engine (LNME) uses a dedicated 2kB block of RAM (PKA RAM) for its operations. + * The operands of the maths operations must be copied into and results out of the PKA ram. + * This necessitates a significant number of reads and writes for each operation. + * The bus interface to the RAM only allows for word-aligned reads and writes. The CPU splits + * the reads and writes from and to general SRAM from unaligned addresses into multiple + * bus operations while accumulating the data in a register until it is full. + * The result of this hardware process is that providing buffers such as plaintext CryptoKey + * keying material to ECC APIs that are word-aligned will significantly speed up the operation and + * reduce power consumption. + * + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + * + * # Supported Curve Types # + * + * The driver implementation supports the following curve types for ECJPAKE: + * + * | Curve Type | Supported | + * |-------------------|-----------| + * | Short Weierstrass | Yes | + * | Montgomery | No | + * | Edwards | No | + * + * # Public Key Validation # + * + * When performing Schnorr-ZKP verification, the foreign public key will always be validated. + * The public V is validated implicitly during the operation. + * The implementation assumes that the cofactor, h, of the curve is 1. This lets us + * skip the computationally expensive step of multiplying the foreign key by the order and + * checking if it yields the point at infinity. When the cofactor is 1, this property is + * implied by validating that the point is not already the point at infinity and that it + * validates against the curve equation. + * All curves supplied by default, the NIST and Brainpool curves, have cofactor = 1. While + * the implementation can use arbitrary curves, you should verify that any other curve used + * has a cofactor of 1. + */ + +#ifndef ti_drivers_ecjpake_ECJPAKECC26X2__include +#define ti_drivers_ecjpake_ECJPAKECC26X2__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +/* Exit the SWI and wait until an HWI call posts the SWI again */ +#define ECJPAKECC26X2_STATUS_FSM_RUN_PKA_OP ECJPAKE_STATUS_RESERVED - 0 +/* Execute the next FSM state immediately without waiting for the next HWI */ +#define ECJPAKECC26X2_STATUS_FSM_RUN_FSM ECJPAKE_STATUS_RESERVED - 1 + +/*! + * @brief ECJPAKECC26X2 states + * + * The EC-JPAKE operations are implemented using multiple invidividual + * PKA operations. Since state transitions for these operations are almost + * always predictable, the state transitions are encoded linearly in this enum. + * The FSM controller will increment the state counter and iterate through + * states until it is told to stop or restart. + */ +typedef enum ECJPAKECC26X2_FsmState_ { + ECJPAKECC26X2_FSM_ERROR = 0, + + ECJPAKECC26X2_FSM_ROUND_ONE_VALIDATE_MYPRIVATEKEY1, + ECJPAKECC26X2_FSM_ROUND_ONE_VALIDATE_MYPRIVATEKEY2, + ECJPAKECC26X2_FSM_ROUND_ONE_VALIDATE_MYPRIVATEV1, + ECJPAKECC26X2_FSM_ROUND_ONE_VALIDATE_MYPRIVATEV2, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY1, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY1_RESULT, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY2, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY2_RESULT, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV1, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV1_RESULT, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV2, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV2_RESULT, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_RETURN, + + ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH, + ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH_RESULT, + ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH_MOD_N, + ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH_MOD_N_RESULT, + ECJPAKECC26X2_FSM_GENERATE_ZKP_ADD_V_TO_N, + ECJPAKECC26X2_FSM_GENERATE_ZKP_ADD_V_TO_N_RESULT, + ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULTS, + ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULTS_RESULT, + ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULT_MOD_N, + ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULT_MOD_N_RESULT, + ECJPAKECC26X2_FSM_ZKP_GENERATE_RETURN, + + ECJPAKECC26X2_FSM_VERIFY_ZKP_VALIDATE_PUBLIC_KEY, + ECJPAKECC26X2_FSM_VERIFY_ZKP_HASH_MOD_N, + ECJPAKECC26X2_FSM_VERIFY_ZKP_HASH_MOD_N_RESULT, + ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_G_BY_R, + ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_G_BY_R_RESULT, + ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_X_BY_HASH, + ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_X_BY_HASH_RESULT, + ECJPAKECC26X2_FSM_VERIFY_ZKP_ADD_RESULTS, + ECJPAKECC26X2_FSM_VERIFY_ZKP_ADD_RESULTS_RESULT, + ECJPAKECC26X2_FSM_VERIFY_ZKP_COMPARE_AGAINST_V, + + ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYPRIVATEKEY2_BY_PRESHAREDSECRET, + ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYPRIVATEKEY2_BY_PRESHAREDSECRET_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_MYCOMBINEDPRIVATEKEY_MOD_N, + ECJPAKECC26X2_FSM_ROUND_TWO_MYCOMBINEDPRIVATEKEY_MOD_N_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY1_TO_THEIRPUBLICKEY1, + ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY1_TO_THEIRPUBLICKEY1_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_ADD_THEIRPUBLICKEY2, + ECJPAKECC26X2_FSM_ROUND_TWO_ADD_THEIRPUBLICKEY2_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY2, + ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY2_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYCOMBINEDPRIVATEKEY_BY_MYNEWGENERATOR, + ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYCOMBINEDPRIVATEKEY_BY_MYNEWGENERATOR_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_VALIDATE_MYPRIVATEV, + ECJPAKECC26X2_FSM_ROUND_TWO_GENERATE_MYPUBLICV, + ECJPAKECC26X2_FSM_ROUND_TWO_GENERATE_MYPUBLICV_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_GENERATE_RETURN, + + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_THEIRPUBLICKEY2_BY_MYCOMBINEDPRIVATEKEY, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_THEIRPUBLICKEY2_BY_MYCOMBINEDPRIVATEKEY_RESULT, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_SUB_YCOORDINATE_FROM_PRIME, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_SUB_YCOORDINATE_FROM_PRIME_RESULT, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_ADD_THEIRCOMBINEDPUBLICKEY, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_ADD_THEIRCOMBINEDPUBLICKEY_RESULT, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_BY_MYPRIVATEKEY2, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_BY_MYPRIVATEKEY2_RESULT, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_RETURN, + +} ECJPAKECC26X2_FsmState; + +/*! + * @brief ECJPAKECC26X2 Hardware Attributes + * + * ECJPAKECC26X2 hardware attributes should be included in the board file + * and pointed to by the ECJPAKE_config struct. + */ +typedef struct ECJPAKECC26X2_HWAttrs_ { + /*! @brief PKA Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; +} ECJPAKECC26X2_HWAttrs; + +/*! + * @brief ECJPAKECC26X2 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct ECJPAKECC26X2_Object_ { + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t operationStatus; + ECJPAKE_CallbackFxn callbackFxn; + ECJPAKE_ReturnBehavior returnBehavior; + ECJPAKECC26X2_FsmState fsmState; + ECJPAKE_Operation operation; + ECJPAKE_OperationType operationType; + uint32_t semaphoreTimeout; + uint32_t resultAddress; +} ECJPAKECC26X2_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecjpake_ECJPAKECC26X2__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/gpio/GPIOCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/gpio/GPIOCC26XX.c new file mode 100644 index 0000000..1274c0f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/gpio/GPIOCC26XX.c @@ -0,0 +1,629 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/gpio.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) + +#if defined(__IAR_SYSTEMS_ICC__) +#include +#define PIN2IOID(pin) (31 - __CLZ(pin)) +#define IOID2PIN(ioid) (1 << ioid) +#endif + +#if defined(__TI_COMPILER_VERSION__) +#define PIN2IOID(pin) (31 - __clz(pin)) +#define IOID2PIN(ioid) (1 << ioid) +#endif + +#if defined(__GNUC__) && !defined(__TI_COMPILER_VERSION__) +#define PIN2IOID(pin) (31 - __builtin_clz(pin)) +#define IOID2PIN(ioid) (1 << ioid) +#endif + +/* + * By default disable both asserts and log for this module. + * This must be done before DebugP.h is included. + */ +#ifndef DebugP_ASSERT_ENABLED +#define DebugP_ASSERT_ENABLED 0 +#endif +#ifndef DebugP_LOG_ENABLED +#define DebugP_LOG_ENABLED 0 +#endif + +static PIN_State gpioPinState; +static PIN_Handle gpioPinHandle; +static PIN_Config gpioPinTable[] = { + PIN_TERMINATE +}; + +/* + * Map GPIO_INT types to corresponding PIN interrupt options + */ +static const uint32_t interruptType[] = { + 0, /* Undefined interrupt type */ + PIN_IRQ_NEGEDGE, /* Interrupt on falling edge */ + PIN_IRQ_POSEDGE, /* Interrupt on rising edge */ + PIN_IRQ_BOTHEDGES, /* Interrupt on both edges */ + 0, /* Interrupt on low level, not supported */ + 0 /* Interrupt on high level, not supported */ +}; + +/* + * EDGE_IRQ_EN_MASK is used to strip the EDGE_IRQ_EN bit (bit 18) + * of an updateMask argument to prevent auto-enabling of interrupt + * by PIN_setConfig(). + */ +#define EDGE_IRQ_EN_MASK (0xFFFBFFFF) + +/* Table of GPIO input types */ +const uint32_t inPinTypes [] = { + PIN_INPUT_EN | PIN_NOPULL, /* GPIO_CFG_IN_NOPULL */ + PIN_INPUT_EN | PIN_PULLUP, /* GPIO_CFG_IN_PU */ + PIN_INPUT_EN | PIN_PULLDOWN /* GPIO_CFG_IN_PD */ +}; + +/* Table of GPIO output types */ +const uint32_t outPinTypes [] = { + PIN_GPIO_OUTPUT_EN | PIN_PUSHPULL, /* GPIO_CFG_OUT_STD */ + PIN_GPIO_OUTPUT_EN | PIN_OPENDRAIN | PIN_NOPULL, /* GPIO_CFG_OUT_OD_NOPULL */ + PIN_GPIO_OUTPUT_EN | PIN_OPENDRAIN | PIN_PULLUP, /* GPIO_CFG_OUT_OD_PU */ + PIN_GPIO_OUTPUT_EN | PIN_OPENDRAIN | PIN_PULLDOWN /* GPIO_CFG_OUT_OD_PD */ +}; + +/* Table of GPIO drive strengths */ +const uint32_t outPinStrengths [] = { + PIN_DRVSTR_MIN, /* GPIO_CFG_OUT_STR_LOW */ + PIN_DRVSTR_MED, /* GPIO_CFG_OUT_STR_MED */ + PIN_DRVSTR_MAX /* GPIO_CFG_OUT_STR_HIGH */ +}; + +#define NUM_PORTS 1 +#define NUM_PINS_PER_PORT 32 + +/* + * Extracts the GPIO interrupt type from the pinConfig. Value to index into the + * interruptType table. + */ +#define getIntTypeNumber(pinConfig) \ + ((pinConfig & GPIO_CFG_INT_MASK) >> GPIO_CFG_INT_LSB) + +/* Uninitialized callbackInfo pinIndex */ +#define CALLBACK_INDEX_NOT_CONFIGURED 0xFF + +/* + * Device specific interpretation of the GPIO_PinConfig content + */ +typedef struct PinConfig { + uint8_t ioid; + uint8_t added; /* 0 = pin has not been added to gpioPinState */ + uint16_t config; +} PinConfig; + +/* + * User defined pin indexes assigned to a port's pins. + * Used by pin callback function to locate callback assigned + * to a pin. + */ +typedef struct PortCallbackInfo { + /* + * the port's corresponding + * user defined pinId indices + */ + uint8_t pinIndex[NUM_PINS_PER_PORT]; +} PortCallbackInfo; + +/* + * Only one PortCallbackInfo object is needed for CC26xx since the 32 pins + * are all on one port. + */ +static PortCallbackInfo gpioCallbackInfo; + +/* + * Bit mask used to keep track of which pins (IOIDs) of the GPIO objects + * in the config structure have interrupts enabled. + */ +static uint32_t configIntsEnabledMask = 0; + +/* + * Internal boolean to confirm that GPIO_init() has been called. + */ +static bool initCalled = false; + +extern const GPIOCC26XX_Config GPIOCC26XX_config; + +/* + * ======== getInPinTypesIndex ======== + */ +static inline uint32_t getInPinTypesIndex(uint32_t pinConfig) +{ + uint32_t index; + + index = (pinConfig & GPIO_CFG_IN_TYPE_MASK) >> GPIO_CFG_IN_TYPE_LSB; + + /* + * If index is out-of-range, default to 0. This should never + * happen, but it's needed to keep Klocwork checker happy. + */ + if (index >= sizeof(inPinTypes) / sizeof(inPinTypes[0])) { + index = 0; + } + + return (index); +} + +/* + * ======== getInterruptTypeIndex ======== + */ +static inline uint32_t getInterruptTypeIndex(uint32_t pinConfig) +{ + uint32_t index; + + index = (pinConfig & GPIO_CFG_INT_MASK) >> GPIO_CFG_INT_LSB; + + /* + * If index is out-of-range, default to 0. This should never + * happen, but it's needed to keep Klocwork checker happy. + */ + if (index >= sizeof(interruptType) / sizeof(interruptType[0])) { + index = 0; + } + + return (index); +}; + +/* + * ======== getOutPinTypesIndex ======== + */ +static inline uint32_t getOutPinTypesIndex(uint32_t pinConfig) +{ + uint32_t index; + + index = (pinConfig & GPIO_CFG_OUT_TYPE_MASK) >> GPIO_CFG_OUT_TYPE_LSB; + + /* + * If index is out-of-range, default to 0. This should never + * happen, but it's needed to keep Klocwork checker happy. + */ + if (index >= sizeof(outPinTypes) / sizeof(outPinTypes[0])) { + index = 0; + } + + return (index); +} + +/* + * ======== getOutPinStrengthsIndex ======== + */ +static inline uint32_t getOutPinStrengthsIndex(uint32_t pinConfig) +{ + uint32_t index; + + index = (pinConfig & GPIO_CFG_OUT_STRENGTH_MASK) >> + GPIO_CFG_OUT_STRENGTH_LSB; + + /* + * If index is out-of-range, default to 0. This should never + * happen, but it's needed to keep Klocwork checker happy. + */ + if (index >= sizeof(outPinStrengths) / sizeof(outPinStrengths[0])) { + index = 0; + } + + return (index); +} + +/* + * ======== getPinNumber ======== + * + * Internal function to efficiently find the index of the right most set bit. + */ +static inline uint32_t getPinNumber(uint32_t x) { + return(x); /* ioid is the same as the pinNumber */ +} + +/* + * ======== GPIO_clearInt ======== + */ +void GPIO_clearInt(uint_least8_t index) +{ + PinConfig *config = (PinConfig *) &GPIOCC26XX_config.pinConfigs[index]; + + /* Clear interrupt flag */ + PIN_clrPendInterrupt(gpioPinHandle, config->ioid); +} + +/* + * ======== GPIO_disableInt ======== + */ +void GPIO_disableInt(uint_least8_t index) +{ + unsigned int key; + PinConfig *config = (PinConfig *) &GPIOCC26XX_config.pinConfigs[index]; + + /* Make atomic update */ + key = HwiP_disable(); + + /* Disable interrupt. */ + PIN_setInterrupt(gpioPinHandle, config->ioid | PIN_IRQ_DIS); + + configIntsEnabledMask &= ~(1 << config->ioid); + + HwiP_restore(key); +} + +/* + * ======== GPIO_enableInt ======== + */ +void GPIO_enableInt(uint_least8_t index) +{ + unsigned int key; + PinConfig *config = (PinConfig *) &GPIOCC26XX_config.pinConfigs[index]; + uint32_t intTypeNum; + + /* Make atomic update */ + key = HwiP_disable(); + + /* Get the index into the interruptType array */ + intTypeNum = getIntTypeNumber((config->config << 16)); + + /* Enable interrupt. */ + PIN_setInterrupt(gpioPinHandle, (config->ioid | interruptType[intTypeNum])); + + configIntsEnabledMask |= (1 << config->ioid); + + HwiP_restore(key); +} + +/* + * ======== GPIO_getConfig ======== + */ +void GPIO_getConfig(uint_least8_t index, GPIO_PinConfig *pinConfig) +{ + *pinConfig = GPIOCC26XX_config.pinConfigs[index]; +} + +/* + * ======== GPIO_hwiIntFxn ======== + * Hwi function that processes GPIO interrupts. + */ +void GPIO_hwiIntFxn(PIN_Handle pinHandle, PIN_Id pinId) +{ + unsigned int pinIndex; + + pinIndex = gpioCallbackInfo.pinIndex[pinId]; + + /* only call plugged callbacks */ + if (pinIndex != CALLBACK_INDEX_NOT_CONFIGURED) { + /* PIN_swi() will call callback even if interrupt is disabled */ + if ((1 << pinId) & configIntsEnabledMask) { + GPIOCC26XX_config.callbacks[pinIndex](pinIndex); + } + } +} + +/* + * ======== GPIO_init ======== + */ +void GPIO_init() +{ + unsigned int i, hwiKey; + SemaphoreP_Handle sem; + static SemaphoreP_Handle initSem; + + /* speculatively create a binary semaphore */ + sem = SemaphoreP_createBinary(1); + + /* There is no way to inform user of this fatal error. */ + if (sem == NULL) return; + + hwiKey = HwiP_disable(); + + if (initSem == NULL) { + initSem = sem; + HwiP_restore(hwiKey); + } + else { + /* init already called */ + HwiP_restore(hwiKey); + /* delete unused Semaphore */ + if (sem) SemaphoreP_delete(sem); + } + + /* now use the semaphore to protect init code */ + SemaphoreP_pend(initSem, SemaphoreP_WAIT_FOREVER); + + /* Only perform init once */ + if (initCalled) { + SemaphoreP_post(initSem); + return; + } + + gpioPinHandle = PIN_open(&gpioPinState, gpioPinTable); + + /* install our Hwi callback function */ + PIN_registerIntCb(gpioPinHandle, GPIO_hwiIntFxn); + + for (i = 0; i < NUM_PINS_PER_PORT; i++) { + gpioCallbackInfo.pinIndex[i] = CALLBACK_INDEX_NOT_CONFIGURED; + } + + /* + * Configure pins and create Hwis per static array content + */ + for (i = 0; i < GPIOCC26XX_config.numberOfPinConfigs; i++) { + if (!(GPIOCC26XX_config.pinConfigs[i] & GPIO_DO_NOT_CONFIG)) { + GPIO_setConfig(i, GPIOCC26XX_config.pinConfigs[i]); + } + if (i < GPIOCC26XX_config.numberOfCallbacks) { + if (GPIOCC26XX_config.callbacks[i] != NULL) { + /* create Hwi as necessary */ + GPIO_setCallback(i, GPIOCC26XX_config.callbacks[i]); + } + } + } + + initCalled = true; + + SemaphoreP_post(initSem); +} + +/* + * ======== GPIO_read ======== + */ +uint_fast8_t GPIO_read(uint_least8_t index) +{ + unsigned int value; + + PinConfig *config = (PinConfig *) &GPIOCC26XX_config.pinConfigs[index]; + + value = GPIO_readMultiDio(IOID2PIN(config->ioid)); + + value = value & (IOID2PIN(config->ioid)) ? 1 : 0; + + return (value); +} + +/* + * ======== GPIO_setCallback ======== + */ +void GPIO_setCallback(uint_least8_t index, GPIO_CallbackFxn callback) +{ + uint32_t pinNum; + PinConfig *config = (PinConfig *) &GPIOCC26XX_config.pinConfigs[index]; + + /* + * Ignore bogus callback indexes. + * Required to prevent out-of-range callback accesses if + * there are configured pins without callbacks + */ + if (index >= GPIOCC26XX_config.numberOfCallbacks) { + return; + } + + /* + * plug the pin index into the corresponding + * port's callbackInfo pinIndex entry + */ + pinNum = getPinNumber(config->ioid); + + if (callback == NULL) { + gpioCallbackInfo.pinIndex[pinNum] = + CALLBACK_INDEX_NOT_CONFIGURED; + } + else { + gpioCallbackInfo.pinIndex[pinNum] = index; + } + + /* + * Only update callBackFunctions entry if different. + * This allows the callBackFunctions array to be in flash for static systems. + */ + if (GPIOCC26XX_config.callbacks[index] != callback) { + GPIOCC26XX_config.callbacks[index] = callback; + } +} + +/* + * ======== GPIO_setConfig ======== + */ +int_fast16_t GPIO_setConfig(uint_least8_t index, GPIO_PinConfig pinConfig) +{ + unsigned int key; + uint16_t direction; + GPIO_PinConfig gpioPinConfig; + PIN_Config pinPinConfig = 0; /* PIN driver PIN_config ! */ + PinConfig *config = (PinConfig *) &GPIOCC26XX_config.pinConfigs[index]; + + if (pinPinConfig & GPIO_DO_NOT_CONFIG) { + return (GPIO_STATUS_SUCCESS); + } + + if ((pinConfig & GPIO_CFG_IN_INT_ONLY) == 0) { + if (pinConfig & GPIO_CFG_INPUT) { + /* configure input */ + direction = GPIO_OUTPUT_DISABLE; + pinPinConfig = inPinTypes[getInPinTypesIndex(pinConfig)]; + } + else { + /* configure output */ + direction = GPIO_OUTPUT_ENABLE; + pinPinConfig = outPinTypes[getOutPinTypesIndex(pinConfig)]; + pinPinConfig |= + outPinStrengths[getOutPinStrengthsIndex(pinConfig)]; + } + + key = HwiP_disable(); + + /* Set output value */ + if (direction == GPIO_OUTPUT_ENABLE) { + pinPinConfig |= ((pinConfig & GPIO_CFG_OUT_HIGH) ? PIN_GPIO_HIGH : PIN_GPIO_LOW); + } + + /* + * Update pinConfig with the latest GPIO configuration and + * clear the GPIO_DO_NOT_CONFIG bit if it was set. + */ + gpioPinConfig = GPIOCC26XX_config.pinConfigs[index]; + gpioPinConfig &= ~(GPIO_CFG_IO_MASK | GPIO_DO_NOT_CONFIG); + gpioPinConfig |= (pinConfig & GPIO_CFG_IO_MASK); + GPIOCC26XX_config.pinConfigs[index] = gpioPinConfig; + + HwiP_restore(key); + } + + /* Set type of interrupt and then clear it */ + if (pinConfig & GPIO_CFG_INT_MASK) { + key = HwiP_disable(); + + /* + * Update pinConfig with the latest interrupt configuration and + * clear the GPIO_DO_NOT_CONFIG bit if it was set. + */ + gpioPinConfig = GPIOCC26XX_config.pinConfigs[index]; + gpioPinConfig &= ~(GPIO_CFG_INT_MASK | GPIO_DO_NOT_CONFIG); + gpioPinConfig |= (pinConfig & GPIO_CFG_INT_MASK); + GPIOCC26XX_config.pinConfigs[index] = gpioPinConfig; + + pinPinConfig |= interruptType[getInterruptTypeIndex(pinConfig)]; + HwiP_restore(key); + } + + /* or in the pin ID */ + pinPinConfig |= (uint32_t)config->ioid; + + if (config->added == 0) { + if (PIN_add(gpioPinHandle, pinPinConfig) != PIN_SUCCESS) { + return (GPIO_STATUS_ERROR); + } + config->added = 1; + } + else { + uint32_t bmMask; + if (pinConfig & GPIO_CFG_IN_INT_ONLY) { + bmMask = PIN_BM_IRQ; + } + else { + bmMask = PIN_BM_ALL; + } + if (PIN_setConfig(gpioPinHandle, bmMask & EDGE_IRQ_EN_MASK, + pinPinConfig) != PIN_SUCCESS) { + return (GPIO_STATUS_ERROR); + } + } + + return (GPIO_STATUS_SUCCESS); +} + +/* + * ======== GPIO_toggle ======== + */ +void GPIO_toggle(uint_least8_t index) +{ + unsigned int key; + PinConfig *config = (PinConfig *) &GPIOCC26XX_config.pinConfigs[index]; + + /* Make atomic update */ + key = HwiP_disable(); + + GPIO_toggleDio(config->ioid); + + /* Update config table entry with value written */ + GPIOCC26XX_config.pinConfigs[index] ^= GPIO_CFG_OUT_HIGH; + + HwiP_restore(key); +} + +/* + * ======== GPIO_write ======== + */ +void GPIO_write(uint_least8_t index, unsigned int value) +{ + unsigned int key; + PinConfig *config = (PinConfig *) &GPIOCC26XX_config.pinConfigs[index]; + + key = HwiP_disable(); + + if (value) { + /* Set the pinConfig output bit to high */ + GPIOCC26XX_config.pinConfigs[index] |= GPIO_CFG_OUT_HIGH; + } + else { + /* Clear output from pinConfig */ + GPIOCC26XX_config.pinConfigs[index] &= ~GPIO_CFG_OUT_HIGH; + } + + value = value ? IOID2PIN(config->ioid) : 0; + + GPIO_writeMultiDio(IOID2PIN(config->ioid), value); + + HwiP_restore(key); +} + +/* + * ======== GPIOCC26xx_release ======== + */ +void GPIOCC26xx_release(int index) +{ + PinConfig *config = (PinConfig *) &GPIOCC26XX_config.pinConfigs[index]; + unsigned int key; + + key = HwiP_disable(); + + if (config->added) { + /* disable the pin's interrupt */ + GPIO_disableInt(index); + + /* remove its callback */ + GPIO_setCallback(index, NULL); + + config->added = 0; + + PIN_remove(gpioPinHandle, config->ioid); + } + + HwiP_restore(key); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/gpio/GPIOCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/gpio/GPIOCC26XX.h new file mode 100644 index 0000000..b22ad1e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/gpio/GPIOCC26XX.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file GPIOCC26XX.h + * + * @brief GPIO driver implementation for CC26xx/CC13xx devices + * + * The GPIO header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref GPIO.h for a complete description of the GPIO + * driver APIs provided and examples of their use. + * + * ### CC26XX GPIO Driver Configuration # + * + * In order to use the GPIO APIs, the application is required + * to provide 3 structures in the Board.c file: + * + * 1. An array of @ref GPIO_PinConfig elements that defines the + * initial configuration of each pin used by the application. A + * pin is referenced in the application by its corresponding index in this + * array. The pin type (that is, INPUT/OUTPUT), its initial state (that is + * OUTPUT_HIGH or LOW), interrupt behavior (RISING/FALLING edge, etc.) + * (see @ref GPIO_PinConfigSettings), and + * device specific pin identification (see @ref GPIOCC26XX_PinConfigIds) + * are configured in each element of this array. + * Below is an CC26XX device specific example of the GPIO_PinConfig array: + * @code + * // + * // Array of Pin configurations + * // NOTE: The order of the pin configurations must coincide with what was + * // defined in CC2650_LAUNCH.h + * // NOTE: Pins not used for interrupts should be placed at the end of the + * // array. Callback entries can be omitted from callbacks array to + * // reduce memory usage. + * // + * GPIO_PinConfig gpioPinConfigs[] = { + * // Input pins + * GPIOCC26XX_DIO_13 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_RISING, // Button 0 + * GPIOCC26XX_DIO_14 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_RISING, // Button 1 + * + * // Output pins + * GPIOCC26XX_DIO_07 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, // Green LED + * GPIOCC26XX_DIO_06 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, // Red LED + * }; + * @endcode + * + * 2. An array of @ref GPIO_CallbackFxn elements that is used to store + * callback function pointers for GPIO pins configured with interrupts. + * The indexes for these array elements correspond to the pins defined + * in the @ref GPIO_PinConfig array. These function pointers can be defined + * statically by referencing the callback function name in the array + * element, or dynamically, by setting the array element to NULL and using + * GPIO_setCallback() at runtime to plug the callback entry. + * Pins not used for interrupts can be omitted from the callback array to + * reduce memory usage (if they are placed at the end of the @ref + * GPIO_PinConfig array). The callback function syntax should match the + * following: + * @code + * void (*GPIO_CallbackFxn)(unsigned int index); + * @endcode + * The index parameter is the same index that was passed to + * GPIO_setCallback(). This allows the same callback function to be used + * for multiple GPIO interrupts, by using the index to identify the GPIO + * that caused the interrupt. + * Below is an CC26XX device specific example of the @ref GPIO_CallbackFxn + * array: + * @code + * // + * // Array of callback function pointers + * // NOTE: The order of the pin configurations must coincide with what was + * // defined in CC2650_LAUNCH.h + * // NOTE: Pins not used for interrupts can be omitted from callbacks array to + * // reduce memory usage (if placed at end of gpioPinConfigs array). + * // + * GPIO_CallbackFxn gpioCallbackFunctions[] = { + * NULL, // Button 0 + * NULL, // Button 1 + * }; + * @endcode + * + * 3. The device specific GPIOCC26XX_Config structure that tells the GPIO + * driver where the two aforementioned arrays are and the number of elements + * in each. The interrupt priority of all pins configured to generate + * interrupts is also specified here. Values for the interrupt priority are + * device-specific. You should be well-acquainted with the interrupt + * controller used in your device before setting this parameter to a + * non-default value. The sentinel value of (~0) (the default value) is + * used to indicate that the lowest possible priority should be used. + * Below is an example of an initialized GPIOCC26XX_Config + * structure: + * @code + * const GPIOCC26XX_Config GPIOCC26XX_config = { + * .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, + * .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, + * .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig), + * .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), + * .intPriority = (~0) + * }; + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_GPIOCC26XX__include +#define ti_drivers_GPIOCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#include +#include + +#include DeviceFamily_constructPath(driverlib/ioc.h) + + + +/*! + * @brief GPIO device specific driver configuration structure + * + * The device specific GPIOCC26XX_Config structure that tells the GPIO + * driver where the two aforementioned arrays are and the number of elements + * in each. The interrupt priority of all pins configured to generate + * interrupts is also specified here. Values for the interrupt priority are + * device-specific. You should be well-acquainted with the interrupt + * controller used in your device before setting this parameter to a + * non-default value. The sentinel value of (~0) (the default value) is + * used to indicate that the lowest possible priority should be used. + * + * Below is an example of an initialized GPIOCC26XX_Config + * structure: + * @code + * const GPIOCC26XX_Config GPIOCC26XX_config = { + * .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, + * .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, + * .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig), + * .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), + * .intPriority = (~0) + * }; + * @endcode + */ +typedef struct GPIOCC26XX_Config { + /*! Pointer to the board's GPIO_PinConfig array */ + GPIO_PinConfig *pinConfigs; + + /*! Pointer to the board's GPIO_CallbackFxn array */ + GPIO_CallbackFxn *callbacks; + + /*! Number of GPIO_PinConfigs defined */ + uint32_t numberOfPinConfigs; + + /*! Number of GPIO_Callbacks defined */ + uint32_t numberOfCallbacks; + + /*! + * Interrupt priority used for call back interrupts. + * + * intPriority is the interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's + * interrupt handler creation code, so you need to refer to the OS + * documentation for usage. If the driver uses the ti.dpl + * interface instead of making OS calls directly, then the HwiP port + * handles the interrupt priority in an OS specific way. In the case + * of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create(). + * + * Setting ~0 will configure the lowest possible priority + */ + uint32_t intPriority; +} GPIOCC26XX_Config; + +/*! + * \defgroup GPIOCC26XX_PinConfigIds GPIO pin identification macros used to configure GPIO pins + * @{ + */ +/** + * @name Device specific GPIO port/pin identifiers to be used within the board's GPIO_PinConfig table. + * @{ +*/ +#define GPIOCC26XX_EMPTY_PIN 0xffff /*!< @hideinitializer */ + +#define GPIOCC26XX_DIO_00 IOID_0 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_01 IOID_1 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_02 IOID_2 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_03 IOID_3 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_04 IOID_4 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_05 IOID_5 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_06 IOID_6 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_07 IOID_7 /*!< @hideinitializer */ + +#define GPIOCC26XX_DIO_08 IOID_8 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_09 IOID_9 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_10 IOID_10 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_11 IOID_11 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_12 IOID_12 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_13 IOID_13 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_14 IOID_14 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_15 IOID_15 /*!< @hideinitializer */ + +#define GPIOCC26XX_DIO_16 IOID_16 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_17 IOID_17 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_18 IOID_18 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_19 IOID_19 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_20 IOID_20 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_21 IOID_21 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_22 IOID_22 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_23 IOID_23 /*!< @hideinitializer */ + +#define GPIOCC26XX_DIO_24 IOID_24 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_25 IOID_25 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_26 IOID_26 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_27 IOID_27 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_28 IOID_28 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_29 IOID_29 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_30 IOID_30 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_31 IOID_31 /*!< @hideinitializer */ + +/** @} */ +/** @} end of GPIOCC26XX_PinConfigIds group */ + +/*! + * @brief Un-oonfigure a GPIO pin + * + * Disables pin interrupt, clears callback, restores pin to default setting, + * removes pin from PIN object + * + * @param index GPIO index + */ +extern void GPIOCC26xx_release(int index); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_GPIOCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2c/I2CCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2c/I2CCC26XX.c new file mode 100644 index 0000000..4e1a6c7 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2c/I2CCC26XX.c @@ -0,0 +1,1079 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * =============================== Includes =================================== + */ +/* STD header files */ +#include +#include +#include + +/* RTOS driver header files */ +#include +#include + +#include +#include +#include +#include + +#include +#include + +/* Driverlib header files */ +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/i2c.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) + +/* + * =============================== Macros ===================================== + * + * Specific I2C CMD MACROs that are not defined in I2C.h are defined here. Their + * equivalent values are taken from the existing MACROs in I2C.h + * + */ +#ifndef I2C_MASTER_CMD_BURST_RECEIVE_START_NACK +#define I2C_MASTER_CMD_BURST_RECEIVE_START_NACK I2C_MASTER_CMD_BURST_SEND_START +#endif + +#ifndef I2C_MASTER_CMD_BURST_RECEIVE_STOP +#define I2C_MASTER_CMD_BURST_RECEIVE_STOP I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +#endif + +#ifndef I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK I2C_MASTER_CMD_BURST_SEND_CONT +#endif + +/* + * =============================== Prototypes ================================= + */ +void I2CCC26XX_init(I2C_Handle handle); +I2C_Handle I2CCC26XX_open(I2C_Handle handle, I2C_Params *params); +bool I2CCC26XX_transfer(I2C_Handle handle, I2C_Transaction *transaction); +void I2CCC26XX_cancel(I2C_Handle handle); +void I2CCC26XX_close(I2C_Handle handle); +int_fast16_t I2CCC26XX_control(I2C_Handle handle, uint_fast16_t cmd, void *arg); + +/* + * ========================== Local Prototypes ================================ + */ +static int I2CCC26XX_primeTransfer(I2C_Handle handle, I2C_Transaction *transferMessage); +static void I2CCC26XX_blockingCallback(I2C_Handle handle, I2C_Transaction *msg, bool transferStatus); +static void I2CCC26XX_initHw(I2C_Handle handle); +static int I2CCC26XX_initIO(I2C_Handle handle, void *pinCfg); +static int i2cPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg); + +/* + * ============================== Constants =================================== + */ +/* I2C function table for I2CCC26XX implementation */ +const I2C_FxnTable I2CCC26XX_fxnTable = { + I2CCC26XX_cancel, + I2CCC26XX_close, + I2CCC26XX_control, + I2CCC26XX_init, + I2CCC26XX_open, + I2CCC26XX_transfer +}; + +static const uint32_t bitRate[] = { + false, /* I2C_100kHz = 0 */ + true /* I2C_400kHz = 1 */ +}; + + +/* + * ============================= Functions ==================================== + */ + +/*! + * @brief Function to cancel any in progress or queued transactions. + * + * After calling the cancel function, the I2C is enabled. + * + * @pre I2CCC26XX_transfer() should have been called first. + * Calling context: Task + * + * @param handle An I2C_Handle returned by I2C_open() + * + * @note The generic I2C API should be used when accessing the I2CCC26XX. + * + * ======== I2CCC26XX_cancel ======== + */ +void I2CCC26XX_cancel(I2C_Handle handle) +{ + unsigned int key; + I2CCC26XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; + I2CCC26XX_Object *object = handle->object; + + /* just return if no transfer is in progress */ + if (!object->headPtr) { + return; + } + + /* disable interrupts, send STOP to try to complete all transfers */ + key = HwiP_disable(); + I2CMasterIntDisable(hwAttrs->baseAddr); + I2CMasterControl(hwAttrs->baseAddr, I2C_MASTER_CMD_BURST_SEND_ERROR_STOP); + + /* call the transfer callback for the current transfer, indicate failure */ + object->transferCallbackFxn(handle, object->currentTransaction, false); + + /* release the constraint to disallow standby */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* also dequeue and call the transfer callbacks for any queued transfers */ + while (object->headPtr != object->tailPtr) { + object->headPtr = object->headPtr->nextPtr; + object->transferCallbackFxn(handle, object->headPtr, false); + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* clean up object */ + object->mode = I2CCC26XX_IDLE_MODE; + object->currentTransaction = NULL; + object->headPtr = NULL; + object->tailPtr = NULL; + + /* re-initialize the I2C peripheral */ + I2CMasterDisable(hwAttrs->baseAddr); + I2CCC26XX_initHw(handle); + + HwiP_restore(key); +} + +/*! + * @brief Function to close a given CC26XX I2C peripheral specified by the + * I2C handle. + * + * After calling the close function, the I2C is disabled. + * + * @pre I2CCC26XX_open() has to be called first. + * Calling context: Task + * + * @param handle An I2C_Handle returned by I2C_open() + * + * @note The generic I2C API should be used when accessing the I2CCC26XX. + * + * @sa I2CCC26XX_open(), I2C_close(), I2C_open() + */ +void I2CCC26XX_close(I2C_Handle handle) +{ + I2CCC26XX_Object *object; + I2CCC26XX_HWAttrsV1 const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Check to see if a I2C transaction is in progress */ + DebugP_assert(object->headPtr == NULL); + + /* Mask I2C interrupts */ + I2CMasterIntDisable(hwAttrs->baseAddr); + + /* Disable the I2C Master */ + I2CMasterDisable(hwAttrs->baseAddr); + + /* Deallocate pins */ + PIN_close(object->hPin); + + /* Power off the I2C module */ + Power_releaseDependency(hwAttrs->powerMngrId); + + /* Desctruct modules used in driver */ + HwiP_destruct(&(object->hwi)); + SwiP_destruct(&(object->swi)); + SemaphoreP_destruct(&(object->mutex)); + if (object->transferMode == I2C_MODE_BLOCKING) { + SemaphoreP_destruct(&(object->transferComplete)); + } + + /* Unregister power post notification object */ + Power_unregisterNotify(&object->i2cPostObj); + + /* Mark the module as available */ + object->isOpen = false; + + DebugP_log1("I2C: Object closed 0x%x", hwAttrs->baseAddr); + + return; +} + +/*! + * @brief Function for setting control parameters of the I2C driver + * after it has been opened. + * + * @note Currently not in use. + */ +int_fast16_t I2CCC26XX_control(I2C_Handle handle, uint_fast16_t cmd, void *arg) +{ + /* No implementation */ + return (I2C_STATUS_UNDEFINEDCMD); +} + + +/* + * ======== I2CCC26XX_hwiFxn ======== + * Hwi interrupt handler to service the I2C peripheral + * + * The handler is a generic handler for a I2C object. + */ +static void I2CCC26XX_hwiFxn(uintptr_t arg) +{ + I2CDataType errStatus; + I2CCC26XX_Object *object; + I2CCC26XX_HWAttrsV1 const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = ((I2C_Handle)arg)->object; + hwAttrs = ((I2C_Handle)arg)->hwAttrs; + + /* Get the interrupt status of the I2C controller */ + errStatus = I2CMasterErr(hwAttrs->baseAddr); + + /* Clear interrupt source to avoid additional interrupts */ + I2CMasterIntClear(hwAttrs->baseAddr); + + /* Check for I2C Errors */ + if ((errStatus == I2C_MASTER_ERR_NONE) || + (object->mode == I2CCC26XX_ERROR)) { + + /* No errors, now check what we need to do next */ + switch (object->mode) { + + /* + * ERROR case : Error detected and STOP bit sent in previous interrupt; + * this interrupt triggered by stop condition on bus. + * Post SWI to complete the transfer + */ + case I2CCC26XX_ERROR: + case I2CCC26XX_IDLE_MODE: + SwiP_post(&(object->swi)); + break; + + case I2CCC26XX_WRITE_MODE: + /* Decrement write Counter */ + object->writeCountIdx--; + + /* Check if more data needs to be sent */ + if (object->writeCountIdx) { + DebugP_log3( + "I2C:(%p) ISR I2CCC26XX_WRITE_MODE: Data to write: 0x%x; " + "To slave: 0x%x", + hwAttrs->baseAddr, + *(object->writeBufIdx), + object->currentTransaction->slaveAddress); + + /* Write data contents into data register */ + I2CMasterDataPut(hwAttrs->baseAddr, + *(object->writeBufIdx)); + object->writeBufIdx++; + + if ((object->writeCountIdx < 2) && !(object->readCountIdx)) { + /* Everything has been sent, nothing to receive */ + /* Next state: Idle mode */ + object->mode = I2CCC26XX_IDLE_MODE; + + /* Send last byte with STOP bit */ + I2CMasterControl(hwAttrs->baseAddr, + I2C_MASTER_CMD_BURST_SEND_FINISH); + + DebugP_log1( + "I2C:(%p) ISR I2CCC26XX_WRITE_MODE: ACK received; " + "Writing w/ STOP bit", + hwAttrs->baseAddr); + } + else { + /* + * Either there is more date to be transmitted or some + * data needs to be received next + */ + I2CMasterControl(hwAttrs->baseAddr, + I2C_MASTER_CMD_BURST_SEND_CONT); + + DebugP_log1( + "I2C:(%p) ISR I2CCC26XX_WRITE_MODE: ACK received; Writing", + hwAttrs->baseAddr); + } + } + + /* At this point, we know that we need to receive data */ + else { + /* + * We need to check after we are done transmitting data, if + * we need to receive any data. + * In a corner case when we have only one byte transmitted + * and no data to receive, the I2C will automatically send + * the STOP bit. In other words, here we only need to check + * if data needs to be received. If so, how much. + */ + if (object->readCountIdx) { + /* Next state: Receive mode */ + object->mode = I2CCC26XX_READ_MODE; + + /* Switch into Receive mode */ + I2CMasterSlaveAddrSet(hwAttrs->baseAddr, + object->currentTransaction->slaveAddress, true); + + if (object->readCountIdx > 1) { + /* Send a repeated START */ + I2CMasterControl(hwAttrs->baseAddr, + I2C_MASTER_CMD_BURST_RECEIVE_START); + + DebugP_log1( + "I2C:(%p) ISR I2CCC26XX_WRITE_MODE: -> I2CCC26XX_READ_MODE; " + "Reading w/ RESTART and ACK", + hwAttrs->baseAddr); + } + else { + /* + * Send a repeated START with a NACK since it's the + * last byte to be received. + * I2C_MASTER_CMD_BURST_RECEIVE_START_NACK is + * is locally defined because there is no macro to + * receive data and send a NACK after sending a + * start bit (0x00000003) + */ + I2CMasterControl(hwAttrs->baseAddr, + I2C_MASTER_CMD_BURST_RECEIVE_START_NACK); + + DebugP_log1( + "I2C:(%p) ISR I2CCC26XX_WRITE_MODE: -> I2CCC26XX_READ_MODE; " + "Reading w/ RESTART and NACK", + hwAttrs->baseAddr); + } + } + else { + /* Done with all transmissions */ + object->mode = I2CCC26XX_IDLE_MODE; + /* + * No more data needs to be received, so follow up with + * a STOP bit + * Again, there is no equivalent macro (0x00000004) so + * I2C_MASTER_CMD_BURST_RECEIVE_STOP is used. + */ + I2CMasterControl(hwAttrs->baseAddr, + I2C_MASTER_CMD_BURST_RECEIVE_STOP); + + DebugP_log1( + "I2C:(%p) ISR I2CCC26XX_WRITE_MODE: -> I2CCC26XX_IDLE_MODE; " + "Sending STOP bit", + hwAttrs->baseAddr); + + } + } + break; + + case I2CCC26XX_READ_MODE: + /* Save the received data */ + *(object->readBufIdx) = + I2CMasterDataGet(hwAttrs->baseAddr); + + DebugP_log2( + "I2C:(%p) ISR I2CCC26XX_READ_MODE: Read data byte: 0x%x", + hwAttrs->baseAddr, + *(object->readBufIdx)); + + object->readBufIdx++; + + /* Check if any data needs to be received */ + object->readCountIdx--; + if (object->readCountIdx) { + if (object->readCountIdx > 1) { + /* More data to be received */ + I2CMasterControl(hwAttrs->baseAddr, + I2C_MASTER_CMD_BURST_RECEIVE_CONT); + + DebugP_log1( + "I2C:(%p) ISR I2CCC26XX_READ_MODE: Reading w/ ACK", + hwAttrs->baseAddr); + } + else { + /* + * Send NACK because it's the last byte to be received + * There is no NACK macro equivalent (0x00000001) so + * I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK is used + */ + I2CMasterControl(hwAttrs->baseAddr, + I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK); + + DebugP_log1( + "I2C:(%p) ISR I2CCC26XX_READ_MODE: Reading w/ NACK", + hwAttrs->baseAddr); + } + } + else { + /* Next state: Idle mode */ + object->mode = I2CCC26XX_IDLE_MODE; + + /* + * No more data needs to be received, so follow up with a + * STOP bit + * Again, there is no equivalent macro (0x00000004) so + * I2C_MASTER_CMD_BURST_RECEIVE_STOP is used + */ + I2CMasterControl(hwAttrs->baseAddr, + I2C_MASTER_CMD_BURST_RECEIVE_STOP); + + DebugP_log1( + "I2C:(%p) ISR I2CCC26XX_READ_MODE: -> I2CCC26XX_IDLE_MODE; " + "Sending STOP bit", + hwAttrs->baseAddr); + + } + + break; + + default: + object->mode = I2CCC26XX_ERROR; + break; + } + + } + else { + /* Error Handling */ + if ((errStatus & (I2C_MASTER_ERR_ARB_LOST | I2C_MASTER_ERR_ADDR_ACK)) || + (object->mode == I2CCC26XX_IDLE_MODE)) { + + if (errStatus & I2C_MASTER_ERR_ADDR_ACK) { + + /* + * The CC26XX I2C hardware ignores the NACK condition + * for the slave address. Therefore, it sends an additional + * byte instead of generating a STOP condition. + */ + I2CMasterControl(hwAttrs->baseAddr, + I2C_MASTER_CMD_BURST_SEND_ERROR_STOP); + } + + /* STOP condition already occurred, complete transfer */ + object->mode = I2CCC26XX_ERROR; + SwiP_post(&(object->swi)); + } + else { + + /* Error occurred during a transfer, send a STOP condition */ + object->mode = I2CCC26XX_ERROR; + I2CMasterControl(hwAttrs->baseAddr, + I2C_MASTER_CMD_BURST_SEND_ERROR_STOP); + } + + DebugP_log2("I2C:(%p) ISR I2C Bus fault (Status Reg: 0x%x)", + hwAttrs->baseAddr, errStatus); + } + + return; +} + +/* + * ======== I2CCC26XX_swiFxn ======== + * SWI interrupt handler to service the I2C peripheral + * + * Takes care of cleanup and the callback in SWI context after an I2C transfer + */ +static void I2CCC26XX_swiFxn(uintptr_t arg0, uintptr_t arg1){ + I2C_Handle handle = ((I2C_Handle)arg0); + I2CCC26XX_Object *object = handle->object; + int32_t status; + + DebugP_log1("I2C:(%p) ISR Transfer Complete", + ((I2CCC26XX_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); + + /* See if we need to process any other transactions */ + if (object->headPtr == object->tailPtr) { + + /* No other transactions need to occur */ + object->headPtr = NULL; + object->tailPtr = NULL; + + /* + * Allow callback to run. If in CALLBACK mode, the application + * may initiate a transfer in the callback which will call + * primeTransfer(). + */ + object->transferCallbackFxn(handle, object->currentTransaction, + (object->mode == I2CCC26XX_IDLE_MODE)); + + /* Release standby disallow constraint. */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + DebugP_log1( + "I2C:(%p) ISR No other I2C transaction in queue", + ((I2CCC26XX_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); + } + else { + /* Another transfer needs to take place */ + object->headPtr = object->headPtr->nextPtr; + + /* + * Allow application callback to run. The application may + * initiate a transfer in the callback which will add an + * additional transfer to the queue. + */ + object->transferCallbackFxn(handle, object->currentTransaction, + (object->mode == I2CCC26XX_IDLE_MODE)); + + DebugP_log2( + "I2C:(%p) ISR Priming next I2C transaction " + "(%p) from queue", + ((I2CCC26XX_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr, + (uintptr_t)object->headPtr); + + status = I2CCC26XX_primeTransfer(handle, object->headPtr); + + /* Call back now if not able to start transfer */ + if (status == I2C_STATUS_ERROR) { + object->mode = I2CCC26XX_BUSBUSY_MODE; + SwiP_post(&(object->swi)); + } + } +} + +/*! + * @brief I2C CC26XX initialization + * + * @param handle An I2C_Handle + * + * @pre Calling context: Hwi, Swi, Task, Main + * + * @note The generic I2C API should be used when accessing the I2CCC26XX. + */ +void I2CCC26XX_init(I2C_Handle handle) +{ + I2CCC26XX_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Initially the drivers is not open */ + object->isOpen = false; + +} + +/*! + * @brief Function to initialize a given I2C CC26XX peripheral specified by the + * particular handle. The parameter specifies which mode the I2C + * will operate. + * + * After calling the open function, the I2C is enabled. If there is no active + * I2C transactions, the device can enter standby. + * + * @pre The I2CCC26XX_Config structure must exist and be persistent before this + * function can be called. I2CCC26XX has been initialized with I2CCC26XX_init(). + * Calling context: Task + * + * @param handle An I2C_Handle + * + * @param params Pointer to a parameter block, if NULL it will use default values. + * + * @return A I2C_Handle on success, or a NULL on an error or if it has been + * already opened. + * + * @note The generic I2C API should be used when accessing the I2CCC26XX. + * + * @sa I2CCC26XX_close(), I2CCC26XX_init(), I2C_open(), I2C_init() + */ +I2C_Handle I2CCC26XX_open(I2C_Handle handle, I2C_Params *params) +{ + union { + HwiP_Params hwiParams; + SwiP_Params swiParams; + } paramsUnion; + uintptr_t key; + I2CCC26XX_Object *object; + I2CCC26XX_HWAttrsV1 const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Check for valid bit rate */ + DebugP_assert(params->bitRate <= I2C_400kHz); + + /* Determine if the device index was already opened */ + key = HwiP_disable(); + if(object->isOpen == true){ + HwiP_restore(key); + return (NULL); + } + + /* Mark the handle as being used */ + object->isOpen = true; + HwiP_restore(key); + + /* Save parameters */ + object->transferMode = params->transferMode; + object->transferCallbackFxn = params->transferCallbackFxn; + object->bitRate = params->bitRate; + + /* Power on the I2C module */ + Power_setDependency(hwAttrs->powerMngrId); + + /* Initialize the I2C hardware module */ + I2CCC26XX_initHw(handle); + + /* Configure the IOs.*/ + if (I2CCC26XX_initIO(handle, params->custom)) { + /* Trying to use I2C driver when pins are already used for something else, error! */ + DebugP_log1("I2C: Pin allocation failed, open did not succeed (baseAddr:0x%x)", hwAttrs->baseAddr); + /* Disable I2C module */ + I2CMasterDisable(hwAttrs->baseAddr); + /* Release power dependency - i.e. potentially power down serial domain. */ + Power_releaseDependency(hwAttrs->powerMngrId); + /* Mark the module as available */ + key = HwiP_disable(); + object->isOpen = false; + HwiP_restore(key); + /* Signal back to application that I2C driver was not succesfully opened */ + return (NULL); + } + + /* Create Hwi object for this I2C peripheral */ + HwiP_Params_init(¶msUnion.hwiParams); + paramsUnion.hwiParams.arg = (uintptr_t)handle; + paramsUnion.hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), hwAttrs->intNum, I2CCC26XX_hwiFxn, ¶msUnion.hwiParams); + + /* Create Swi object for this I2C peripheral */ + SwiP_Params_init(&(paramsUnion.swiParams)); + paramsUnion.swiParams.arg0 = (uintptr_t)handle; + paramsUnion.swiParams.priority = hwAttrs->swiPriority; + SwiP_construct(&(object->swi), I2CCC26XX_swiFxn, &(paramsUnion.swiParams)); + + /* + * Create thread safe handles for this I2C peripheral + * Semaphore to provide exclusive access to the I2C peripheral + */ + SemaphoreP_constructBinary(&(object->mutex), 1); + + /* + * Store a callback function that posts the transfer complete + * semaphore for synchronous mode + */ + if (object->transferMode == I2C_MODE_BLOCKING) { + /* Semaphore to cause the waiting task to block for the I2C to finish */ + SemaphoreP_constructBinary(&(object->transferComplete), 0); + /* Store internal callback function */ + object->transferCallbackFxn = I2CCC26XX_blockingCallback; + } + else { + /* Check to see if a callback function was defined for async mode */ + DebugP_assert(object->transferCallbackFxn != NULL); + } + + /* Specify the idle state for this I2C peripheral */ + object->mode = I2CCC26XX_IDLE_MODE; + + /* Clear the head pointer */ + object->headPtr = NULL; + object->tailPtr = NULL; + + /* Register notification functions */ + Power_registerNotify(&object->i2cPostObj, PowerCC26XX_AWAKE_STANDBY, (Power_NotifyFxn)i2cPostNotify, (uint32_t)handle); + + /* I2C driver opened successfully */ + DebugP_log1("I2C: Object created 0x%x", hwAttrs->baseAddr); + + /* Return the address of the handle */ + return (handle); +} + +/* + * ======== I2CCC26XX_primeTransfer ======= + */ +static int I2CCC26XX_primeTransfer(I2C_Handle handle, + I2C_Transaction *transaction) +{ + I2CCC26XX_Object *object; + I2CCC26XX_HWAttrsV1 const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Store the new internal counters and pointers */ + object->currentTransaction = transaction; + + object->writeBufIdx = transaction->writeBuf; + object->writeCountIdx = transaction->writeCount; + + object->readBufIdx = transaction->readBuf; + object->readCountIdx = transaction->readCount; + + DebugP_log2( + "I2C:(%p) Starting transaction to slave: 0x%x", + hwAttrs->baseAddr, + object->currentTransaction->slaveAddress); + + /* Start transfer in Transmit mode */ + if (object->writeCountIdx) { + /* Specify the I2C slave address */ + I2CMasterSlaveAddrSet(hwAttrs->baseAddr, + object->currentTransaction->slaveAddress, false); + /* Update the I2C mode */ + object->mode = I2CCC26XX_WRITE_MODE; + + DebugP_log3( + "I2C:(%p) I2CCC26XX_IDLE_MODE: Data to write: 0x%x; To Slave: 0x%x", + hwAttrs->baseAddr, + *(object->writeBufIdx), + object->currentTransaction->slaveAddress); + + /* Write data contents into data register */ + I2CMasterDataPut(hwAttrs->baseAddr, + *((object->writeBufIdx)++)); + + /* Check bus status, return with error if busy */ + if (I2CMasterBusBusy(hwAttrs->baseAddr)) { + return I2C_STATUS_ERROR; + } + + /* Start the I2C transfer in master transmit mode */ + I2CMasterControl(hwAttrs->baseAddr, I2C_MASTER_CMD_BURST_SEND_START); + + DebugP_log1( + "I2C:(%p) I2CCC26XX_IDLE_MODE: -> I2CCC26XX_WRITE_MODE; " + "Writing w/ START", + hwAttrs->baseAddr); + } + + /* Start transfer in Receive mode */ + else { + /* Specify the I2C slave address */ + I2CMasterSlaveAddrSet(hwAttrs->baseAddr, + object->currentTransaction->slaveAddress, true); + + /* Update the I2C mode */ + object->mode = I2CCC26XX_READ_MODE; + + /* Check bus status, return with error if busy */ + if (I2CMasterBusBusy(hwAttrs->baseAddr)) { + return I2C_STATUS_ERROR; + } + + if (object->readCountIdx < 2) { + /* Start the I2C transfer in master receive mode */ + I2CMasterControl(hwAttrs->baseAddr, + I2C_MASTER_CMD_BURST_SEND_START); + + DebugP_log1( + "I2C:(%p) I2CCC26XX_IDLE_MODE: -> I2CCC26XX_READ_MODE; " + "Reading w/ NACK", + hwAttrs->baseAddr); + } + else { + /* Start the I2C transfer in master receive mode */ + I2CMasterControl(hwAttrs->baseAddr, + I2C_MASTER_CMD_BURST_RECEIVE_START); + + DebugP_log1( + "I2C:(%p) I2CCC26XX_IDLE_MODE: -> I2CCC26XX_READ_MODE; " + "Reading w/ ACK", + hwAttrs->baseAddr); + } + } + + return I2C_STATUS_SUCCESS; +} + +/*! + * @brief Function to start a transfer from the CC26XX I2C peripheral specified + * by the I2C handle. + * + * This function is used for both transmitting and receiving data. If the I2C + * is configured in ::I2C_MODE_CALLBACK mode, it is possible to chain transactions + * together and receive a callback when all transactions are done. + * When active I2C transactions exist, the device might enter idle, not standby. + * + * @pre I2CCC26XX_open() has to be called first. + * Calling context: Hwi and Swi (only if using ::I2C_MODE_CALLBACK), Task + * + * @param handle An I2C_Handle returned by I2C_open() + * + * @param transaction Pointer to a I2C transaction object + * + * @return true on successful transfer. + * false on an error, such as a I2C bus fault. + * + * @note The generic I2C API should be used when accessing the I2CCC26XX. + * + * @sa I2CCC26XX_open(), I2C_transfer() + */ +bool I2CCC26XX_transfer(I2C_Handle handle, + I2C_Transaction *transaction) +{ + bool ret = false; + uintptr_t key; + I2CCC26XX_Object *object; + I2CCC26XX_HWAttrsV1 const *hwAttrs; + int status; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Check if anything needs to be written or read */ + if ((!transaction->writeCount) && (!transaction->readCount)) { + /* Nothing to write or read */ + return (ret); + } + + key = HwiP_disable(); + + if (object->transferMode == I2C_MODE_CALLBACK) { + /* Check if a transfer is in progress */ + if (object->headPtr) { + /* Transfer in progress */ + + /* + * Update the message pointed by the tailPtr to point to the next + * message in the queue + */ + object->tailPtr->nextPtr = transaction; + + /* Update the tailPtr to point to the last message */ + object->tailPtr = transaction; + + /* I2C is still being used */ + HwiP_restore(key); + return (true); + } + } + + /* Store the headPtr indicating I2C is in use */ + object->headPtr = transaction; + object->tailPtr = transaction; + + HwiP_restore(key); + + /* Get the lock for this I2C handle */ + if (SemaphoreP_pend(&(object->mutex), SemaphoreP_NO_WAIT) == SemaphoreP_TIMEOUT) { + + /* An I2C_transfer() may complete before the calling thread post the + * mutex due to preemption. We must not block in this case. */ + if (object->transferMode == I2C_MODE_CALLBACK) { + return (false); + } + + SemaphoreP_pend(&(object->mutex), SemaphoreP_WAIT_FOREVER); + } + + /* Set standby disallow constraint. */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * I2CCC26XX_primeTransfer is a longer process and + * protection is needed from the I2C interrupt + */ + + HwiP_disableInterrupt(hwAttrs->intNum); + status = I2CCC26XX_primeTransfer(handle, transaction); + HwiP_enableInterrupt(hwAttrs->intNum); + + if (object->transferMode == I2C_MODE_BLOCKING) { + if (status == I2C_STATUS_ERROR) { + DebugP_log1( + "I2C:(%p) Bus busy, transaction not started", + hwAttrs->baseAddr); + object->mode = I2CCC26XX_BUSBUSY_MODE; + ret = false; + + /* Release standby disallow constraint. */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + else { + DebugP_log1( + "I2C:(%p) Pending on transferComplete semaphore", + hwAttrs->baseAddr); + /* + * Wait for the transfer to complete here. + * It's OK to block from here because the I2C's Hwi will unblock + * upon errors + */ + SemaphoreP_pend(&(object->transferComplete), SemaphoreP_WAIT_FOREVER); + + /* No need to release standby disallow constraint here - done in swi */ + + DebugP_log1( + "I2C:(%p) Transaction completed", + hwAttrs->baseAddr); + + /* Hwi handle has posted a 'transferComplete' check for Errors */ + if (object->mode == I2CCC26XX_IDLE_MODE) { + DebugP_log1( + "I2C:(%p) Transfer OK", + hwAttrs->baseAddr); + ret = true; + } + } + } + else { + /* Call back now if not able to start transfer */ + if (status == I2C_STATUS_ERROR) { + object->mode = I2CCC26XX_BUSBUSY_MODE; + SwiP_post(&(object->swi)); + ret = false; + } + else { + /* Return true if transaction is started */ + ret = true; + } + } + + /* Release the lock for this particular I2C handle */ + SemaphoreP_post(&(object->mutex)); + + /* Return status */ + return (ret); +} + +/* + * ======== I2CCC26XX_blockingCallback ======== + */ +static void I2CCC26XX_blockingCallback(I2C_Handle handle, + I2C_Transaction *msg, + bool transferStatus) +{ + I2CCC26XX_Object *object; + + DebugP_log1("I2C:(%p) posting transferComplete semaphore", + ((I2CCC26XX_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); + + /* Get the pointer to the object */ + object = handle->object; + + /* Indicate transfer complete */ + SemaphoreP_post(&(object->transferComplete)); +} + +/* + * ======== I2CCC26XX_hwInit ======== + * This functions initializes the I2C hardware module. + * + * @pre Function assumes that the I2C handle is pointing to a hardware + * module which has already been opened. + */ +static void I2CCC26XX_initHw(I2C_Handle handle) { + I2CCC26XX_Object *object; + I2CCC26XX_HWAttrsV1 const *hwAttrs; + ClockP_FreqHz freq; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Set the I2C configuration */ + ClockP_getCpuFreq(&freq); + I2CMasterInitExpClk(hwAttrs->baseAddr, freq.lo, bitRate[object->bitRate]); + + /* Clear any pending interrupts */ + I2CMasterIntClear(hwAttrs->baseAddr); + + /* Enable the I2C Master for operation */ + I2CMasterEnable(hwAttrs->baseAddr); + + /* Unmask I2C interrupts */ + I2CMasterIntEnable(hwAttrs->baseAddr); +} + +/* + * ======== I2CCC26XX_initIO ======== + * This functions initializes the I2C IOs. + * + * @pre Function assumes that the I2C handle is pointing to a hardware + * module which has already been opened. + */ +static int I2CCC26XX_initIO(I2C_Handle handle, void *pinCfg) { + I2CCC26XX_Object *object; + I2CCC26XX_HWAttrsV1 const *hwAttrs; + I2CCC26XX_I2CPinCfg i2cPins; + PIN_Config i2cPinTable[3]; + uint32_t i=0; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* If the pinCfg pointer is NULL, use hwAttrs pins */ + if (pinCfg == NULL) { + i2cPins.pinSDA = hwAttrs->sdaPin; + i2cPins.pinSCL = hwAttrs->sclPin; + } else { + i2cPins.pinSDA = ((I2CCC26XX_I2CPinCfg *)pinCfg)->pinSDA; + i2cPins.pinSCL = ((I2CCC26XX_I2CPinCfg *)pinCfg)->pinSCL; + } + + /* Handle error */ + if(i2cPins.pinSDA == PIN_UNASSIGNED || i2cPins.pinSCL == PIN_UNASSIGNED) { + return I2C_STATUS_ERROR; + } + /* Configure I2C pins SDA and SCL*/ + i2cPinTable[i++] = i2cPins.pinSDA | PIN_INPUT_EN | PIN_PULLUP | PIN_OPENDRAIN; + i2cPinTable[i++] = i2cPins.pinSCL | PIN_INPUT_EN | PIN_PULLUP | PIN_OPENDRAIN; + i2cPinTable[i++] = PIN_TERMINATE; + /* Allocate pins*/ + object->hPin = PIN_open(&object->pinState, i2cPinTable); + + if (!object->hPin) { + return I2C_STATUS_ERROR; + } + + /* Set IO muxing for the UART pins */ + PINCC26XX_setMux(object->hPin, i2cPins.pinSDA, IOC_PORT_MCU_I2C_MSSDA); + PINCC26XX_setMux(object->hPin, i2cPins.pinSCL, IOC_PORT_MCU_I2C_MSSCL); + return I2C_STATUS_SUCCESS; +} + +/* + * ======== i2cPostNotify ======== + * This functions is called to notify the I2C driver of an ongoing transition + * out of sleep mode. + * + * @pre Function assumes that the I2C handle (clientArg) is pointing to a + * hardware module which has already been opened. + */ +static int i2cPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg) +{ + /* Return value */ + int res; + + /* reconfigure the hardware if returning from sleep*/ + if (eventType == PowerCC26XX_AWAKE_STANDBY) { + I2CCC26XX_initHw((I2C_Handle)clientArg); + } + + res = Power_NOTIFYDONE; + return res; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2c/I2CCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2c/I2CCC26XX.h new file mode 100644 index 0000000..d5269b6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2c/I2CCC26XX.h @@ -0,0 +1,519 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file I2CCC26XX.h + * + * @brief I2C driver implementation for a CC26XX I2C controller. + * + * # Driver Include # + * The I2C header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref I2C.h for a complete description of APIs. + * + * # Overview # + * The general I2C API is normally used in application code, e.g. I2C_open() + * is used instead of I2CCC26XX_open(). The board file will define the device + * specific config, and casting in the general API will ensure that the correct + * device specific functions are called. + * This is also reflected in the example code in [Use Cases](@ref I2C_USE_CASES). + * + * ## General Behavior # + * Before using the I2C in CC26XX: + * - The I2C driver is initialized by calling I2C_init(). + * - The I2C HW is configured and system dependencies are declared (e.g. IOs, + * power, etc.) by calling I2C_open(). + * . + * The following is true for receive operation: + * - RX is enabled by calling I2C_transfer(). + * The readCount of the ::I2C_Transaction must be set to a non-zero value. + * - If the I2C_transfer() succeeds, the I2C remains enabled. + * - The application must check the return value from I2C_transfer() + * to verify that the transfer succeeded. + * . + * The following apply for transmit operation: + * - TX is enabled by calling I2C_transfer(). + * The writeCount of the ::I2C_Transaction must be set to a non-zero value. + * - If the I2C_transfer() succeeds, the I2C remains enabled. + * - The application must check the return value from I2C_transfer() + * to verify that the transfer succeeded. + * . + * After I2C operation has ended: + * - Release system dependencies for I2C by calling I2C_close(). + * + * ### Known Issue # + * @warning The I2C may transmit a single data byte in the event that the + * I2C slave address is not acknowledged (NACK'd). This is due to a known + * hardware bug. + * + * ## Error handling # + * If an error occurs during operation: + * - The I2C Master transmits a stop bit and remains enabled. + * . + * + * ## Power Management # + * The I2CCC26XX driver sets a power constraint during transactions to keep + * the device out of standby; so when all tasks are blocked, the device will + * enter idle mode instead of standby. When the transactions have finished, + * the power constraint to prohibit standby is released. + * The following statements are valid: + * - After I2C_open() call: I2C is enabled, there are no active I2C + * transactions, the device can enter standby. + * - After I2C_transfer() call: active I2C transactions exist, the device + * might enter idle, but not standby. + * - When I2C_transfer() completes, either after success or error, I2C + * remains enabled, and the device can enter standby. + * - After I2C_close() call: I2C is disabled + * - If the device goes into idle during a transaction, the state of + * SDA is undefined in the time between the transaction completing and + * the device waking up. SCL will go low until the device wakes up and + * starts another transaction or releases the bus. If this is a problem + * for another device on the I2C bus, you can set a power constraint for + * #PowerCC26XX_DISALLOW_IDLE before the transaction and release it + * when the transaction completes. + * + * ## Supported Functions ## + * | Generic API Function | API Function | Description | + * |--------------------- |------------------------- |---------------------------------------------------| + * | I2C_init() | I2CCC26XX_init() | Initialize I2C driver | + * | I2C_open() | I2CCC26XX_open() | Initialize I2C HW and set system dependencies | + * | I2C_close() | I2CCC26XX_close() | Disable I2C HW and release system dependencies | + * | I2C_transfer() | I2CCC26XX_transfer() | Start I2C transfer | + * + * @note All calls should go through the generic API. + * + * ## Supported Bit Rates ## + * - #I2C_100kHz + * - #I2C_400kHz + * + * ## Unsupported Functionality # + * The CC26XX I2C driver currently does not support: + * - Multi-master mode + * - I2C slave mode + * + * ## Use Cases @anchor I2C_USE_CASES ## + * ### Basic Receive # + * Receive 10 bytes over I2C in ::I2C_MODE_BLOCKING. + * @code + * // Locals + * I2C_Handle handle; + * I2C_Params params; + * I2C_Transaction i2cTrans; + * uint8_t rxBuf[32]; // Receive buffer + * uint8_t txBuf[32]; // Transmit buffer + * + * // Configure I2C parameters. + * I2C_Params_init(¶ms); + * + * // Initialize master I2C transaction structure + * i2cTrans.writeCount = 0; + * i2cTrans.writeBuf = txBuf; + * i2cTrans.readCount = 10; + * i2cTrans.readBuf = rxBuf; + * i2cTrans.slaveAddress = 0x3C; + * + * // Open I2C + * handle = I2C_open(Board_I2C, ¶ms); + * + * // Do I2C transfer receive + * I2C_transfer(handle, &i2cTrans); + * @endcode + * + * ### Basic Transmit # + * Transmit 16 bytes over I2C in ::I2C_MODE_CALLBACK. + * @code + * uint8_t rxBuffer[32]; // Receive buffer + * uint8_t txBuffer[32]; // Transmit buffer + * bool transferDone = false; + * + * static void transferCallback(I2C_Handle handle, I2C_Transaction *transac, bool result) + * { + * // Set length bytes + * if (result) { + * transferDone = true; + * } else { + * // Transaction failed, act accordingly... + * . + * . + * } + * } + * + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * // Locals + * I2C_Handle handle; + * I2C_Params params; + * I2C_Transaction i2cTrans; + * + * // Configure I2C parameters. + * I2C_Params_init(¶ms); + * params.transferMode = I2C_MODE_CALLBACK; + * params.transferCallbackFxn = transferCallback; + * + * // Prepare data to send, send 0x00, 0x01, 0x02, ...0xFF, 0x00, 0x01... + * for(uint32_t i = 0; i < numTxBytes; i++) + * txBuffer[i] = (uint8_t) i; + * + * // Initialize master I2C transaction structure + * i2cTrans.writeCount = 16; + * i2cTrans.writeBuf = txBuffer; + * i2cTrans.readCount = 0; + * i2cTrans.readBuf = rxBuffer; + * i2cTrans.slaveAddress = 0x3C; + * + * // Open I2C + * handle = I2C_open(Board_I2C, ¶ms); + * + * // Do I2C transfer (in callback mode) + * I2C_transfer(handle, &i2cTrans); + * + * // Do other stuff while I2C is handling the transfer + * . + * . + * + * // Do something if I2C transfer is finished + * if(transferDone) { + * . + * . + * } + * + * // Continue... + * . + * . + * } + * @endcode + * + * ### Chained Transactions # + * Transmit 10 bytes and then 32 bytes over I2C in ::I2C_MODE_CALLBACK. + * @code + * uint8_t rxBuffer[32]; // Receive buffer + * uint8_t txBuffer[32]; // Transmit buffer + * uint8_t rxBuffer2[64]; // Receive buffer 2 + * uint8_t txBuffer2[64]; // Transmit buffer 2 + * bool transferDone = false; + * + * static void writeCallbackDefault(I2C_Handle handle, I2C_Transaction *transac, bool result) + * { + * // Set length bytes + * if (result) { + * transferDone = true; + * } else { + * // Transaction failed, act accordingly... + * . + * . + * } + * } + * + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * // Locals + * I2C_Handle handle; + * I2C_Params params; + * I2C_Transaction i2cTrans; + * I2C_Transaction i2cTrans2; + * + * // Configure I2C parameters. + * I2C_Params_init(¶ms); + * params.transferMode = I2C_MODE_CALLBACK; + * params.transferCallbackFxn = writeCallbackDefault; + * + * // Prepare data to send, send 0x00, 0x01, 0x02, ...0xFF, 0x00, 0x01... + * for(uint32_t i = 0; i < numTxBytes; i++) + * txBuffer[i] = (uint8_t) i; + * + * // Initialize first master I2C transaction structure + * i2cTrans.writeCount = 10; + * i2cTrans.writeBuf = txBuffer; + * i2cTrans.readCount = 0; + * i2cTrans.readBuf = rxBuffer; + * i2cTrans.slaveAddress = 0x3C; + * + * // Second transaction + * i2cTrans2.writeCount = 32; + * i2cTrans2.writeBuf = txBuffer2; + * i2cTrans2.readCount = 0; + * i2cTrans2.readBuf = rxBuffer2; + * i2cTrans2.slaveAddress = 0x2E; + * + * // Open I2C + * handle = I2C_open(Board_I2C, ¶ms); + * + * // Do chained I2C transfers (in callback mode). + * I2C_transfer(handle, &i2cTrans); + * I2C_transfer(handle, &i2cTrans2); + * + * // Do other stuff while I2C is handling the transfers + * . + * . + * + * // Do something if I2C transfers are finished + * if(transferDone) { + * . + * . + * } + * + * // Continue... + * . + * . + * } + * @endcode + * + * # Instrumentation # + * The I2C driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic I2C operations performed | + * Diags_USER2 | detailed I2C operations performed | + * + ****************************************************************************** + */ + +#ifndef ti_drivers_i2c_I2CCC26XX__include +#define ti_drivers_i2c_I2CCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include + +#include +#include +#include + +/** + * @addtogroup I2C_STATUS + * I2CCC26XX_STATUS_* macros are command codes only defined in the + * I2CCC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add I2CCC26XX_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup I2C_CMD + * I2CCC26XX_CMD_* macros are command codes only defined in the + * I2CCC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add I2CCC26XX_CMD_* macros here */ + +/** @}*/ + +/*! I2C Base Address type.*/ +typedef unsigned long I2CBaseAddrType; +/* \cond */ +typedef unsigned long I2CDataType; +/* \endcond */ + +/*! @internal @brief I2C function table pointer */ +extern const I2C_FxnTable I2CCC26XX_fxnTable; + +/*! + * @brief I2CCC26XX Pin Configuration + * + * Pin configuration that holds non-default pins. The default pin configuration + * is typically defined in ::I2CCC26XX_HWAttrsV1 placed in the board file. + * The pin configuration structure is used by setting the custom void + * pointer in the ::I2C_Params to point to this struct. If the custom + * void pointer is NULL, the ::I2CCC26XX_HWAttrsV1 pin mapping will be used. + * @code + * I2C_Handle handle; + * I2C_Params i2cParams; + * I2CCC26XX_I2CPinCfg pinCfg; + * + * I2C_Params_init(&i2cParams); // sets custom to NULL + * pinCfg.pinSDA = Board_I2C0_SDA1; + * pinCfg.pinSCL = Board_I2C0_SCL1; + * i2cParams.custom = &pinCfg; + * + * handle = I2C_open(Board_I2C, &i2cParams); + * @endcode + */ +typedef struct I2CCC26XX_I2CPinCfg { + uint8_t pinSDA; + uint8_t pinSCL; +} I2CCC26XX_I2CPinCfg; + +/*! + * @cond NODOC + * I2CCC26XX mode + * + * This enum defines the state of the I2C driver's state-machine. Do not + * modify. + */ +typedef enum I2CCC26XX_Mode { + I2CCC26XX_IDLE_MODE = 0, /* I2C is not performing a transaction */ + I2CCC26XX_WRITE_MODE, /* I2C is currently performing write operations */ + I2CCC26XX_READ_MODE, /* I2C is currently performing read operations */ + I2CCC26XX_BUSBUSY_MODE, /* I2C Bus is currently busy */ + I2CCC26XX_ERROR = 0xFF /* I2C error has occurred, exit gracefully */ +} I2CCC26XX_Mode; +/*! @endcond */ + +/*! + * @brief I2CCC26XX Hardware attributes + * + * The baseAddr and intNum fields define the base address and the interrupt + * number of the I2C peripheral. These values are passed to driverlib APIs + * and therefore must be populated by driverlib macro definitions. These + * macros are found in the header files: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * The powerMngrId is the Power driver resource ID for the I2C peripheral. + * These macros are defined in PowerCC26XX.h + + * intPriority is the I2C peripheral's interrupt priority, as defined by the + * TI-RTOS kernel. This value is passed unmodified to Hwi_create(). + * + * swiPriority is the priority of a TI-RTOS kernel Swi that the I2C driver + * creates to finalize I2C transfers. See the documentation for the + * ti.sysbios.knl.Swi module for a description of Swi priorities. + * + * sdaPin and sclPin define the SDA and SCL pin mapping, respectively. These + * are typically defined with a macro in a header file, which maps to an + * IOID. For example, CC1350_LAUNCHXL.h defines BOARD_I2C0_SDA0 to be IOID_5. + * + * A sample structure is shown below: + * @code + * const I2CCC26XX_HWAttrsV1 i2cCC26xxHWAttrs[CC1350_LAUNCHXL_I2CCOUNT] = { + * { + * .baseAddr = I2C0_BASE, + * .powerMngrId = PowerCC26XX_PERIPH_I2C0, + * .intNum = INT_I2C_IRQ, + * .intPriority = ~0, + * .swiPriority = 0, + * .sdaPin = Board_I2C0_SDA0, + * .sclPin = Board_I2C0_SCL0, + * }, + * }; + * @endcode + */ +typedef struct I2CCC26XX_HWAttrsV1 { + /*! I2C peripheral's base address */ + I2CBaseAddrType baseAddr; + /*! I2C peripheral's Power driver ID */ + unsigned long powerMngrId; + /*! I2C peripheral's interrupt number */ + int intNum; + /*! @brief I2C Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + Hwi's with priority 0 ignore the Hwi dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief I2C Swi priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! I2C SDA pin mapping */ + uint8_t sdaPin; + /*! I2C SCL pin mapping */ + uint8_t sclPin; +} I2CCC26XX_HWAttrsV1; + +/*! + * @cond NODOC + * I2CCC26XX Object. The application must not access any member variables + * of this structure! + */ +typedef struct I2CCC26XX_Object { + /* I2C control variables */ + I2C_TransferMode transferMode; /*!< Blocking or Callback mode */ + I2C_CallbackFxn transferCallbackFxn; /*!< Callback function pointer */ + volatile I2CCC26XX_Mode mode; /*!< Stores the I2C state */ + uint32_t bitRate; /*!< Bitrate of the I2C module */ + + /* I2C SYS/BIOS objects */ + HwiP_Struct hwi;/*!< Hwi object handle */ + SwiP_Struct swi; /*!< Swi object */ + SemaphoreP_Struct mutex; /*!< Grants exclusive access to I2C */ + SemaphoreP_Struct transferComplete; /*!< Signal I2C transfer complete */ + + /* PIN driver state object and handle */ + PIN_State pinState; + PIN_Handle hPin; + + /* I2C current transaction */ + I2C_Transaction *currentTransaction; /*!< Ptr to current I2C transaction */ + uint8_t *writeBufIdx; /*!< Internal inc. writeBuf index */ + unsigned int writeCountIdx; /*!< Internal dec. writeCounter */ + uint8_t *readBufIdx; /*!< Internal inc. readBuf index */ + unsigned int readCountIdx; /*!< Internal dec. readCounter */ + + /* I2C transaction pointers for I2C_MODE_CALLBACK */ + I2C_Transaction *headPtr; /*!< Head ptr for queued transactions */ + I2C_Transaction *tailPtr; /*!< Tail ptr for queued transactions */ + + /* I2C power notification */ + void *i2cPostFxn; /*!< I2C post-notification Function pointer */ + Power_NotifyObj i2cPostObj; /*!< I2C post-notification object */ + + bool isOpen; /*!< flag to indicate module is open */ +} I2CCC26XX_Object; + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_i2c_I2CCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2s/I2SCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2s/I2SCC26XX.c new file mode 100644 index 0000000..50320b3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2s/I2SCC26XX.c @@ -0,0 +1,958 @@ +/* + * Copyright (c) 2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include + +#include +#include DeviceFamily_constructPath(driverlib/i2s.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) + +#include +#include +#include +#include +#include + +#define I2S_CLOCK_DIVIDER_MAX 1024U +#define I2S_CLOCK_DIVIDER_MIN 2U +#define I2S_NB_CHANNELS_MAX 8U +#define I2S_RAW_CLOCK_48MHZ 48000000U /* Clock if not divided (48 MHz) */ + +#define I2S_MEMORY_LENGTH_16BITS_CC26XX 0U /* Internally used to set memory length to 16 bits */ +#define I2S_MEMORY_LENGTH_24BITS_CC26XX 1U /* Internally used to set memory length to 24 bits */ + +/* Forward declarations */ +static bool initObject(I2S_Handle handle, I2S_Params *params); +static bool initIO(I2S_Handle handle); +static void initHw(I2S_Handle handle); +static void I2S_hwiIntFxn(uintptr_t arg); +static int i2sPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg); + +static void configSerialFormat(I2S_Handle handle); +static void configChannels(I2S_Handle handle); +static void configClocks(I2S_Handle handle); +static void enableClocks(I2S_Handle handle); + +static bool computeSCKDivider(I2S_Handle handle, const I2S_Params *params, uint16_t *result); +static bool computeWSDivider(I2S_Handle handle, const I2S_Params *params, uint16_t *result); +static uint8_t getNumberOfChannels(const uint8_t channelsList); +static uint32_t getBitRate(I2S_Handle handle, const I2S_Params *params); +static uint16_t computeMemoryStep(I2S_Handle handle, I2S_DataInterfaceUse expectedUseSD0, I2S_DataInterfaceUse expectedUseSD1); +static void updatePointer(I2S_Handle handle, I2SCC26XX_Interface *interface); + +/* Extern globals */ +extern I2S_Config I2S_config[]; +extern const uint_least8_t I2S_count; + +/* Static globals */ +static bool isInitialized = (bool)false; + +/* + * ======== I2S_init ======== + */ +void I2S_init(void) { + uint_least8_t i; + + if (!isInitialized) { + /* Call each instances' driver init function */ + for (i = 0; i < I2S_count; i++) { + I2S_Handle handle = (I2S_Handle)&(I2S_config[i]); + I2SCC26XX_Object *object = (I2SCC26XX_Object *)handle->object; + object->isOpen = (bool)false; + } + + isInitialized = (bool)true; + } +} + +/* + * ======== I2S_open ======== + */ +I2S_Handle I2S_open(uint_least8_t index, I2S_Params *params) { + I2S_Handle handle; + I2SCC26XX_Object *object; + + handle = (I2S_Handle)&(I2S_config[index]); + object = handle->object; + + DebugP_assert(index < I2S_count); + + /* Check if module is initialized. */ + if (!isInitialized || object->isOpen) { + handle = NULL; + } + + /* Initialization of the I2S-object and verification of the parameters. */ + else if (!initObject(handle, params)) { + /* The parameters provided are not correct. */ + handle = NULL; + } + + /* Configure IOs, make sure it was successful. */ + else if (!initIO(handle)) { + /* Another driver or application already using these pins. */ + handle = NULL; + } + + /* Set Power and register interrupts */ + else { + + object->isOpen = (bool)true; + + /* Register power dependency - i.e. power up and enable clock for I2S. */ + Power_setDependency(PowerCC26XX_PERIPH_I2S); + + /* Register notification functions */ + Power_registerNotify(&object->i2sPostObj, PowerCC26XX_AWAKE_STANDBY, (Power_NotifyFxn)i2sPostNotify, (uintptr_t)handle); + + HwiP_Params hwiParams; + I2SCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Register HW interrupt */ + HwiP_Params_init(&hwiParams); + hwiParams.arg = (uintptr_t)handle; + hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), INT_I2S_IRQ, (HwiP_Fxn)I2S_hwiIntFxn, &hwiParams); + + HwiP_clearInterrupt(INT_I2S_IRQ); + } + + return handle; +} + +/* + * ======== I2S_close ======== + */ +void I2S_close(I2S_Handle handle) +{ + I2SCC26XX_Object *object = handle->object; + + /* Disable I2S interrupts. */ + I2SIntDisable(I2S0_BASE, I2S_INT_ALL); + HwiP_destruct(&(object->hwi)); + + /* Wait for end of started transactions */ + while((I2SInPointerNextGet(I2S0_BASE) != 0U) || + (I2SOutPointerNextGet(I2S0_BASE) != 0U)){} + + while((I2SInPointerGet(I2S0_BASE) != 0U) || + (I2SOutPointerGet(I2S0_BASE) != 0U)){} + + I2SInPointerSet(I2S0_BASE, 0U); + I2SOutPointerSet(I2S0_BASE, 0U); + I2SSampleStampInConfigure(I2S0_BASE, 0xFFFFU); + I2SSampleStampOutConfigure(I2S0_BASE, 0xFFFFU); + + /* Disable I2S module */ + I2SStop(I2S0_BASE); + I2SSampleStampDisable(I2S0_BASE); + + /* Disable internal clocks */ + PRCMAudioClockDisable(); + + /* Deallocate pins */ + PIN_close(object->hPin); + + /* Unregister power notification objects */ + Power_unregisterNotify(&object->i2sPostObj); + + /* Release power dependency - i.e. potentially power down serial domain. */ + Power_releaseDependency(PowerCC26XX_PERIPH_I2S); + + /* Mark the module as available */ + object->isOpen = (bool)false; +} + +/* + * ======== I2S_setReadQueueHead ======== + */ +void I2S_setReadQueueHead(I2S_Handle handle, I2S_Transaction *transaction){ + + DebugP_assert(&transaction != 0x0); + + I2SCC26XX_Object *object = handle->object; + I2SCC26XX_Interface *interface = &object->read; + + interface->activeTransfer = transaction; +} + +/* + * ======== I2S_setWriteQueueHead ======== + */ +void I2S_setWriteQueueHead(I2S_Handle handle, I2S_Transaction *transaction){ + + DebugP_assert(&transaction != 0x0); + + I2SCC26XX_Object *object = handle->object; + I2SCC26XX_Interface *interface = &object->write; + + interface->activeTransfer = transaction; +} + +/* + * ======== I2S_startClocks ======== + */ +void I2S_startClocks(I2S_Handle handle) { + + Power_setConstraint(PowerCC26XX_SB_DISALLOW); + + initHw(handle); + enableClocks(handle); + + /* Configuring sample stamp generator will trigger the audio stream to start */ + I2SSampleStampInConfigure(I2S0_BASE, 0); + I2SSampleStampOutConfigure(I2S0_BASE, 0); +} + +/* + * ======== I2S_stopClocks ======== + */ +void I2S_stopClocks(I2S_Handle handle) { + + I2SIntClear(I2S0_BASE, I2S_INT_ALL); + + I2SIntDisable(I2S0_BASE, (uint32_t)I2S_INT_TIMEOUT | + (uint32_t)I2S_INT_BUS_ERR | + (uint32_t)I2S_INT_WCLK_ERR | + (uint32_t)I2S_INT_PTR_ERR); + + I2SStop(I2S0_BASE); + I2SSampleStampDisable(I2S0_BASE); + + PRCMAudioClockDisable(); + PRCMLoadSet(); + + Power_releaseConstraint(PowerCC26XX_SB_DISALLOW); +} + +/* + * ======== I2S_startRead ======== + */ +void I2S_startRead(I2S_Handle handle) { + + I2SCC26XX_Object *object = handle->object; + + /* If a read interface is activated */ + if(object->read.memoryStep != 0){ + + /* Enable I2S Hardware Interrupts */ + I2SIntEnable(I2S0_BASE, (uint32_t)I2S_INT_DMA_IN | + (uint32_t)I2S_INT_TIMEOUT | + (uint32_t)I2S_INT_BUS_ERR | + (uint32_t)I2S_INT_WCLK_ERR | + (uint32_t)I2S_INT_PTR_ERR); + + /* At startup, INPTRNEXT must be written twice. The first value will be directly copy to INPTR */ + object->ptrUpdateFxn(handle, &object->read); + object->ptrUpdateFxn(handle, &object->read); + + /* Configuring sample stamp generator will trigger the audio stream to start */ + if(object->read.delay != 0U) { + + I2SSampleStampInConfigure(I2S0_BASE, object->read.delay); + I2SWclkCounterReset(I2S0_BASE); + } + } +} + +/* + * ======== I2S_startWrite ======== + */ +void I2S_startWrite(I2S_Handle handle) { + + I2SCC26XX_Object *object = handle->object; + + /* If a write interface is activated */ + if(object->write.memoryStep != 0){ + + /* Enable I2S Hardware Interrupts */ + I2SIntEnable(I2S0_BASE, (uint32_t)I2S_INT_DMA_OUT | + (uint32_t)I2S_INT_TIMEOUT | + (uint32_t)I2S_INT_BUS_ERR | + (uint32_t)I2S_INT_WCLK_ERR | + (uint32_t)I2S_INT_PTR_ERR); + + /* At startup, OUTPTRNEXT must be written twice. The first value will be directly copy to OUTPTR */ + object->ptrUpdateFxn(handle, &object->write); + object->ptrUpdateFxn(handle, &object->write); + + /* Configuring sample stamp generator will trigger the audio stream to start */ + if(object->write.delay != 0U) { + + I2SSampleStampOutConfigure(I2S0_BASE, object->write.delay); + I2SWclkCounterReset(I2S0_BASE); + } + } +} + +/* + * ======== I2S_stopRead ======== + */ +void I2S_stopRead(I2S_Handle handle) { + + I2SCC26XX_Object *object = handle->object; + + /* If a read interface is activated */ + if(object->read.memoryStep != 0){ + + /* Disable DMA_IN interrupts: we do not need anymore to refresh IN_PTR */ + I2SIntDisable(I2S0_BASE, I2S_INT_DMA_IN); + + /* Wait for end of started transfers */ + while(I2SInPointerNextGet(I2S0_BASE) != 0U){} + while(I2SInPointerGet(I2S0_BASE) != 0U){} + + I2SIntClear(I2S0_BASE, I2S_INT_DMA_IN); + I2SIntClear(I2S0_BASE, I2S_INT_PTR_ERR); + + I2SSampleStampInConfigure(I2S0_BASE, 0xFFFFU); + + I2SInPointerSet(I2S0_BASE, 0U); + } +} + +/* + * ======== I2S_stopWrite ======== + */ +void I2S_stopWrite(I2S_Handle handle) { + + I2SCC26XX_Object *object = handle->object; + + /* If a write interface is activated */ + if(object->write.memoryStep != 0){ + + /* Disable DMA_OUT interrupts: we do not need anymore to refresh OUT_PTR */ + I2SIntDisable(I2S0_BASE, I2S_INT_DMA_OUT); + + /* Wait for end of started transactions */ + while(I2SOutPointerNextGet(I2S0_BASE) != 0U){} + while(I2SOutPointerGet(I2S0_BASE) != 0U){} + + I2SIntClear(I2S0_BASE, I2S_INT_DMA_OUT); + I2SIntClear(I2S0_BASE, I2S_INT_PTR_ERR); + + I2SSampleStampOutConfigure(I2S0_BASE, 0xFFFFU); + + I2SOutPointerSet(I2S0_BASE, 0U); + } +} + +/* + * ======== I2S_hwiIntFxn ======== + * Hwi function that processes I2S interrupts. + */ +static void I2S_hwiIntFxn(uintptr_t arg) { + + I2S_Handle handle = (I2S_Handle)arg; + I2SCC26XX_Object *object = handle->object; + uint16_t errStatus = 0U; + + uint32_t interruptStatus = I2SIntStatus(I2S0_BASE, (bool)true); + + /* I2S_INT_PTR_ERR flag should be consider if and only if I2S_INT_DMA_IN or I2S_INT_DMA_OUT is raised at the same time */ + if((((interruptStatus & (uint32_t)I2S_INT_PTR_ERR) != 0U) && (((interruptStatus & (uint32_t)I2S_INT_DMA_IN) != 0U)) || + ((interruptStatus & (uint32_t)I2S_INT_DMA_OUT) != 0U))) { + + if((interruptStatus & (uint32_t)I2S_INT_DMA_IN) != 0U) { + /* Try to update IN_PTR */ + object->ptrUpdateFxn(handle, &object->read); + /* Check if we could clear I2S_INT_DMA_IN flag */ + interruptStatus = I2SIntStatus(I2S0_BASE, (bool)true); + /* I2S_INT_PTR_ERR is confirmed if we could not clear I2S_INT_DMA_IN flag */ + if(((interruptStatus & (uint32_t)I2S_INT_PTR_ERR) != 0U) && ((interruptStatus & (uint32_t)I2S_INT_DMA_IN) != 0U)) { + I2SIntClear(I2S0_BASE, I2S_INT_PTR_ERR); + errStatus = errStatus | I2S_PTR_READ_ERROR; + } + } + + if((interruptStatus & (uint32_t)I2S_INT_DMA_OUT) != 0U) { + /* Try to update OUT_PTR */ + object->ptrUpdateFxn(handle, &object->write); + /* Check if we could clear I2S_INT_DMA_OUT flag */ + interruptStatus = I2SIntStatus(I2S0_BASE, (bool)true); + /* I2S_INT_PTR_ERR is confirmed if we could not clear I2S_INT_DMA_OUT flag */ + if(((interruptStatus & (uint32_t)I2S_INT_PTR_ERR) != 0U) && ((interruptStatus & (uint32_t)I2S_INT_DMA_OUT) != 0U)) { + I2SIntClear(I2S0_BASE, I2S_INT_PTR_ERR); + errStatus = errStatus | I2S_PTR_WRITE_ERROR; + } + } + } + else if((interruptStatus & (uint32_t)I2S_INT_PTR_ERR) != 0U) { + /* I2S_INT_PTR_ERR must not be considered as no I2S_INT_DMA_xxx flag is set */ + I2SIntClear(I2S0_BASE, I2S_INT_PTR_ERR); + } + + if((interruptStatus & (uint32_t)I2S_INT_DMA_IN) != 0U) { + object->ptrUpdateFxn(handle, &object->read); + } + + if((interruptStatus & (uint32_t)I2S_INT_DMA_OUT) != 0U) { + object->ptrUpdateFxn(handle, &object->write); + } + + if((interruptStatus & (uint32_t)I2S_INT_TIMEOUT) != 0U) { + I2SIntClear(I2S0_BASE, I2S_INT_TIMEOUT); + errStatus = errStatus | I2S_TIMEOUT_ERROR; + } + + if((interruptStatus & (uint32_t)I2S_INT_BUS_ERR) != 0U) { + I2SIntClear(I2S0_BASE, I2S_INT_BUS_ERR); + errStatus = errStatus | I2S_BUS_ERROR; + } + + if((interruptStatus & (uint32_t)I2S_INT_WCLK_ERR) != 0U) { + I2SIntClear(I2S0_BASE, I2S_INT_WCLK_ERR); + errStatus = errStatus | I2S_WS_ERROR; + } + + if(errStatus != 0U) { + object->errorCallback(handle, errStatus, NULL); + } +} + +/* +* ======== initHw ======== +* This functions initializes the I2S hardware module. +* +* @pre Function assumes that the I2S handle is pointing to a hardware +* module which has already been opened. +*/ +static void initHw(I2S_Handle handle) { + + /* Configure serial format. */ + configSerialFormat(handle); + /* Configure the channels used on each data interface. */ + configChannels(handle); + /* Configure the clocks for the MCLK, SCK and WS signals. */ + configClocks(handle); +} + +/* + * ======== updatePointer ======== + */ +static void updatePointer(I2S_Handle handle, I2SCC26XX_Interface *interface) { + + I2S_Transaction *transaction = interface->activeTransfer; + + if(transaction != NULL) { + + /* Critical section to prevent any modification or deletion of the current transaction */ + uintptr_t key; + key = HwiP_disable(); + + /* Transaction */ + if((transaction->bytesTransferred + interface->memoryStep) > transaction->bufSize){ + /* The current transaction is over */ + I2S_Transaction *transactionFinished = transaction; + transaction = (I2S_Transaction*)List_next(&transactionFinished->queueElement); + interface->activeTransfer = transaction; + + transactionFinished->numberOfCompletions ++; + transactionFinished->untransferredBytes = transactionFinished->bufSize - transactionFinished->bytesTransferred; + transactionFinished->bytesTransferred = 0; + + if(transaction != NULL){ + interface->pointerSet(I2S0_BASE, ((uint32_t)transaction->bufPtr + transaction->bytesTransferred)); + transaction->bytesTransferred += interface->memoryStep; + interface->callback(handle, I2S_TRANSACTION_SUCCESS, transactionFinished); + } + else { + /* Not anymore transaction */ + interface->callback(handle, I2S_ALL_TRANSACTIONS_SUCCESS, transactionFinished); + } + } + else { + interface->pointerSet(I2S0_BASE, ((uint32_t)transaction->bufPtr + transaction->bytesTransferred)); + transaction->bytesTransferred += interface->memoryStep; + } + + HwiP_restore(key); + } + else { + /* No element in the queue: do nothing */ + } +} + +/* + * ======== initObject ======== + */ +static bool initObject(I2S_Handle handle, I2S_Params *params) { + + I2SCC26XX_Object *object = handle->object; + I2SCC26XX_DataInterface *SD0; + I2SCC26XX_DataInterface *SD1; + + bool retVal = (bool)true; + + /* Get the pointer to the SD0 and SD1 interfaces*/ + SD0 = &object->dataInterfaceSD0; + SD1 = &object->dataInterfaceSD1; + + if(params == NULL) { + /* This module cannot be open if the user does not provide the expected pointers callback */ + /* So it is no point to try to load the default value here. */ + retVal = (bool)false; + } + else { + object->moduleRole = params->moduleRole; + object->invertWS = params->invertWS; + object->samplingEdge = params->samplingEdge; + object->beforeWordPadding = params->beforeWordPadding; + object->afterWordPadding = params->afterWordPadding; + object->phaseType = params->phaseType; + object->bitsPerWord = params->bitsPerWord; + object->startUpDelay = params->startUpDelay; + object->read.delay = 1; + object->write.delay = 1; + + if(params->memorySlotLength == I2S_MEMORY_LENGTH_16BITS) {object->memorySlotLength = I2S_MEMORY_LENGTH_16BITS_CC26XX;} + else if(params->memorySlotLength == I2S_MEMORY_LENGTH_24BITS) {object->memorySlotLength = I2S_MEMORY_LENGTH_24BITS_CC26XX;} + else {retVal = (bool)false;} + object->read.pointerSet = I2SInPointerSet; + object->write.pointerSet = I2SOutPointerSet; + object->ptrUpdateFxn = updatePointer; + + SD0->interfaceConfig = params->SD0Use; + SD0->channelsUsed = params->SD0Channels; + SD0->numberOfChannelsUsed = getNumberOfChannels((uint8_t)SD0->channelsUsed); + SD1->interfaceConfig = params->SD1Use; + SD1->channelsUsed = params->SD1Channels; + SD1->numberOfChannelsUsed = getNumberOfChannels((uint8_t)SD1->channelsUsed); + + if(params->MCLKDivider == 1U) {retVal = (bool)false;} + object->MCLKDivider = params->MCLKDivider; + uint16_t SCKDivider = 0U; + if (!computeSCKDivider(handle, params, &SCKDivider)) {retVal = (bool)false;} + object->SCKDivider = SCKDivider; + uint16_t WSDivider = 0U; + if (!computeWSDivider(handle, params, &WSDivider)) {retVal = (bool)false;} + object->WSDivider = WSDivider; + + object->read.memoryStep = computeMemoryStep(handle, I2S_SD0_INPUT, I2S_SD1_INPUT); + object->write.memoryStep = computeMemoryStep(handle, I2S_SD0_OUTPUT, I2S_SD1_OUTPUT); + + /* If the user set a fixed length of the buffers, we can optimize the runtime by setting the DMA buffer length */ + if(params->fixedBufferLength == 0U){retVal = (bool)false;} + else{ + if(params->fixedBufferLength != 1U) + { + uint16_t memoryStep = ((object->read.memoryStep > object->write.memoryStep)?object->read.memoryStep:object->write.memoryStep); + if(memoryStep != 0U){ + uint8_t dmaBuffSizeDivider = 1U; + uint16_t dmaBuffSizeConfig = (uint16_t)(((((params->fixedBufferLength) / memoryStep ) * 2U) - 1U) / dmaBuffSizeDivider); + + /* The value of the DMA buffer size is limited to 255 */ + while(dmaBuffSizeConfig > 255U) { + dmaBuffSizeDivider = dmaBuffSizeDivider * 2; + dmaBuffSizeConfig = (uint16_t)(((((params->fixedBufferLength) / memoryStep ) * 2U) - 1U) / dmaBuffSizeDivider); + } + + object->dmaBuffSizeConfig = (uint8_t)dmaBuffSizeConfig; /* dmaBuffSizeConfig < 255 */ + + object->read.memoryStep = (object->read.memoryStep!=0U)? (uint16_t)(params->fixedBufferLength/dmaBuffSizeDivider) :0U; + object->write.memoryStep = (object->write.memoryStep!=0U)? (uint16_t)(params->fixedBufferLength/dmaBuffSizeDivider) :0U; + } + } + else { + object->dmaBuffSizeConfig = 1U; + } + } + + object->read.callback = params->readCallback; + if((object->read.callback == NULL) && (object->read.memoryStep != 0U)) {retVal = (bool)false;} + object->write.callback = params->writeCallback; + if((object->write.callback == NULL) && (object->write.memoryStep != 0U)) {retVal = (bool)false;} + object->errorCallback = params->errorCallback; + if((object->errorCallback == NULL)) {retVal = (bool)false;} + + object->read.activeTransfer = NULL; + object->write.activeTransfer = NULL; + } + + return retVal; +} + +/* + * ======== initIO ======== + */ +static bool initIO(I2S_Handle handle) { + + I2SCC26XX_Object *object; + I2SCC26XX_HWAttrs const *hwAttrs; + PIN_Config i2sPinTable[6]; + + bool retVal = (bool)true; + + uint32_t pinCLKstatus; + uint32_t pinSD0status; + uint32_t pinSD1status; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + if(object->moduleRole == I2S_MASTER) {pinCLKstatus = (uint32_t)IOC_STD_OUTPUT;} + else {pinCLKstatus = (uint32_t)IOC_STD_INPUT;} + + if(object->dataInterfaceSD0.interfaceConfig == I2S_SD0_INPUT) {pinSD0status = (uint32_t)IOC_STD_INPUT;} + else {pinSD0status = (uint32_t)IOC_STD_OUTPUT;} + + if(object->dataInterfaceSD1.interfaceConfig == I2S_SD1_INPUT) {pinSD1status = (uint32_t)IOC_STD_INPUT;} + else {pinSD1status = (uint32_t)IOC_STD_OUTPUT;} + + i2sPinTable[0] = hwAttrs->pinMCLK | pinCLKstatus; + i2sPinTable[1] = hwAttrs->pinWS | pinCLKstatus; + i2sPinTable[2] = hwAttrs->pinSCK | pinCLKstatus; + i2sPinTable[3] = hwAttrs->pinSD0 | pinSD0status; + i2sPinTable[4] = hwAttrs->pinSD1 | pinSD1status; + i2sPinTable[5] = PIN_TERMINATE; + object->hPin = PIN_open(&object->pinState, i2sPinTable); + + if(hwAttrs->pinMCLK <= (PIN_Id)PINCC26XX_DIO30){ + if(PIN_setOutputEnable(object->hPin, hwAttrs->pinMCLK, (bool)true) != (PIN_SUCCESS)) {retVal = (bool)false;} + if(PINCC26XX_setMux(object->hPin, hwAttrs->pinMCLK, IOC_PORT_MCU_I2S_MCLK) != (PIN_SUCCESS)) {retVal = (bool)false;} + } + if(hwAttrs->pinWS <= (PIN_Id)PINCC26XX_DIO30){ + if(PIN_setOutputEnable(object->hPin, hwAttrs->pinWS, (bool)true) != (PIN_SUCCESS)) {retVal = (bool)false;} + if(PINCC26XX_setMux(object->hPin, hwAttrs->pinWS, IOC_PORT_MCU_I2S_WCLK) != (PIN_SUCCESS)) {retVal = (bool)false;} + } + if(hwAttrs->pinSCK <= (PIN_Id)PINCC26XX_DIO30){ + if(PIN_setOutputEnable(object->hPin, hwAttrs->pinSCK, (bool)true) != (PIN_SUCCESS)) {retVal = (bool)false;} + if(PINCC26XX_setMux(object->hPin, hwAttrs->pinSCK, IOC_PORT_MCU_I2S_BCLK) != (PIN_SUCCESS)) {retVal = (bool)false;} + } + if(hwAttrs->pinSD0 <= (PIN_Id)PINCC26XX_DIO30){ + if(PIN_setOutputEnable(object->hPin, hwAttrs->pinSD0, (bool)true) != (PIN_SUCCESS)) {retVal = (bool)false;} + if(PINCC26XX_setMux(object->hPin, hwAttrs->pinSD0, IOC_PORT_MCU_I2S_AD0) != (PIN_SUCCESS)) {retVal = (bool)false;} + } + if(hwAttrs->pinSD1 <= (PIN_Id)PINCC26XX_DIO30){ + if(PIN_setOutputEnable(object->hPin, hwAttrs->pinSD1, (bool)true) != (PIN_SUCCESS)) {retVal = (bool)false;} + if(PINCC26XX_setMux(object->hPin, hwAttrs->pinSD1, IOC_PORT_MCU_I2S_AD1) != (PIN_SUCCESS)) {retVal = (bool)false;} + } + + return retVal; +} + +/* + * ======== getNumberOfChannels ======== + */ +static uint8_t getNumberOfChannels(const uint8_t channelsList) { + + uint8_t i = 0; + uint8_t nbChannelsUsed = 0; + for(i=0; i<=(I2S_NB_CHANNELS_MAX-1U); i++) { + if(((channelsList >> i) & 1U) == 1U) { + nbChannelsUsed ++; + } + } + return nbChannelsUsed; +} + +/* + * ======== computeSCKDivider ======== + */ +static bool computeSCKDivider(I2S_Handle handle, const I2S_Params *params, uint16_t *result){ + + uint32_t expectedBitRate = getBitRate(handle, params); + uint32_t freqDividerSCK = 0U; + + bool retVal = (bool)true; + + *result = 0; + + if (expectedBitRate == 0U) { + retVal = (bool)false; + } + else { + /* We want to round the integer division: ROUND(a/b)=(a+b/2)/b */ + freqDividerSCK = ((I2S_RAW_CLOCK_48MHZ + expectedBitRate/2) / expectedBitRate); + + if ((freqDividerSCK < I2S_CLOCK_DIVIDER_MIN) || (freqDividerSCK > I2S_CLOCK_DIVIDER_MAX)) { + retVal = (bool)false; + } + else { + /* If we reach this code it means we have freqDividerSCK <= 1024 */ + uint16_t u16FreqDividerSCK = (uint16_t)freqDividerSCK; + *result = u16FreqDividerSCK; + } + } + return retVal; +} + +/* + * ======== computeWSDivider ======== + */ +static bool computeWSDivider(I2S_Handle handle, const I2S_Params *params, uint16_t *result){ + + I2SCC26XX_Object const *object; + I2SCC26XX_DataInterface const *SD0; + I2SCC26XX_DataInterface const *SD1; + + bool retVal = (bool)true; + uint8_t numbOfChannels = 0U; + + /* Get the pointer to the SD0 and SD1 interfaces*/ + object = handle->object; + SD0 = &object->dataInterfaceSD0; + SD1 = &object->dataInterfaceSD1; + + *result = 0x0000; + + if(SD0->interfaceConfig) { + numbOfChannels = (numbOfChannels > SD0->numberOfChannelsUsed)? numbOfChannels : SD0->numberOfChannelsUsed; + } + else { + numbOfChannels = (numbOfChannels > SD1->numberOfChannelsUsed)? numbOfChannels : SD1->numberOfChannelsUsed; + } + + + uint16_t sampleLength = 0U; + sampleLength += object->beforeWordPadding; + sampleLength += object->bitsPerWord; + sampleLength += object->afterWordPadding; + /* No overflow risk as sampleLength<255+255+255 and numbOfChannels<=8 */ + uint16_t numOfSCKCyles = (sampleLength * numbOfChannels); + + switch(object->phaseType) { + + case(I2S_PHASE_TYPE_DUAL) : + /* WS is high for WDIV[9:0] (1 to 1023) SCK periods and low for WDIV[9:0] (1 to 1023) SCK periods. + * WS frequency = SCK frequency / (2 x WDIV[9:0]) + * Dual phase protocols don't accept more than two channels + */ + if (numbOfChannels <= 2U) { + *result = sampleLength; + } + else { + retVal = (bool)false; + } + break; + + case(I2S_PHASE_TYPE_SINGLE) : + /* WS is high for 1 SCK period and low for WDIV[9:0] (1 to 1023) SCK periods. + * WS frequency = SCK frequency / (1 + PRCM:I2SWCLKDIV.WDIV[9:0]) + */ + *result = (numOfSCKCyles - 1U); + break; + + default : + retVal = (bool)false; + } + return retVal; +} + +/* + * ======== getBitRate ======== + */ +static uint32_t getBitRate(I2S_Handle handle, const I2S_Params *params) { + + I2SCC26XX_Object const *object; + I2SCC26XX_DataInterface const *SD0; + I2SCC26XX_DataInterface const *SD1; + uint32_t dataLength = 0U; + + /* Get the pointer to the SD0 and SD1 interfaces*/ + object = handle->object; + SD0 = &object->dataInterfaceSD0; + SD1 = &object->dataInterfaceSD1; + + uint16_t sampleLength = 0U; + sampleLength += object->beforeWordPadding; + sampleLength += object->bitsPerWord; + sampleLength += object->afterWordPadding; + + uint32_t samplePerChannelPerSecond = params->samplingFrequency; + uint8_t numbOfChannels = 0U; + if(SD0->interfaceConfig) { + numbOfChannels = (object->phaseType == I2S_PHASE_TYPE_DUAL)? 2U : SD0->numberOfChannelsUsed; + } + else { + numbOfChannels = (object->phaseType == I2S_PHASE_TYPE_DUAL)? 2U : SD1->numberOfChannelsUsed; + } + + /* No risk of overflow: highest possible value is 24 000 000 (any higher value has no sense) */ + dataLength = (uint32_t)((uint32_t)numbOfChannels * (uint32_t)sampleLength); + return (dataLength * samplePerChannelPerSecond); +} + +/* + * ======== configSerialFormat ======== + */ +static void configSerialFormat(I2S_Handle handle) { + + I2SCC26XX_Object const *object; + + /* Get the pointer to the object*/ + object = handle->object; + + I2SFormatConfigure(I2S0_BASE, object->beforeWordPadding, + (uint8_t)object->memorySlotLength, + (uint8_t)object->samplingEdge, + (bool) (object->phaseType == I2S_PHASE_TYPE_DUAL), + (object->bitsPerWord + object->afterWordPadding), + object->startUpDelay); + + /* Prevent DMA start by setting an unreachable trigger */ + I2SSampleStampInConfigure(I2S0_BASE, (uint16_t)((uint16_t)object->bitsPerWord + (uint16_t)object->afterWordPadding)); + I2SSampleStampOutConfigure(I2S0_BASE, (uint16_t)((uint16_t)object->bitsPerWord + (uint16_t)object->afterWordPadding)); +} + +/* + * ======== configChannels ======== + */ +static void configChannels(I2S_Handle handle) { + + I2SCC26XX_Object const *object; + I2SCC26XX_DataInterface const *SD0; + I2SCC26XX_DataInterface const *SD1; + + /* Get the pointer to the SD0 and SD1 interfaces*/ + object = handle->object; + SD0 = &object->dataInterfaceSD0; + SD1 = &object->dataInterfaceSD1; + + I2SFrameConfigure(I2S0_BASE, (uint8_t)SD0->interfaceConfig, (uint8_t)SD0->channelsUsed, + (uint8_t)SD1->interfaceConfig, (uint8_t)SD1->channelsUsed); +} + +/* + * ======== configClocks ======== + */ +static void configClocks(I2S_Handle handle) { + + I2SCC26XX_Object const *object; + + /* Get the pointer to the object*/ + object = handle->object; + + I2SWclkConfigure(I2S0_BASE, (bool)object->moduleRole, + object->invertWS); + + /* Set internal audio clock source */ + if(object->moduleRole) { + + PRCMAudioClockInternalSource(); + PRCMAudioClockConfigOverride((uint8_t)object->samplingEdge, + (uint8_t)object->phaseType, + (uint32_t)object->MCLKDivider, + (uint32_t)object->SCKDivider, + (uint32_t)object->WSDivider); + } + + /* Set external audio clock source */ + else { + PRCMAudioClockExternalSource(); + } +} + +/* + * ======== enableClocks ======== + */ +static void enableClocks(I2S_Handle handle) { + + I2SCC26XX_Object const *object; + + /* Get the pointer to the object*/ + object = handle->object; + + /* Enable internal clocks */ + PRCMAudioClockEnable(); + + /* Enable sample stamps */ + I2SSampleStampEnable(I2S0_BASE); + + I2SStart(I2S0_BASE, object->dmaBuffSizeConfig); + + /* Activate clocks (no clock is running before this call) + * (clocks must be correctly set before) + */ + PRCMLoadSet(); +} + +/* + * ======== computeMemoryStep ======== + */ +static uint16_t computeMemoryStep(I2S_Handle handle, I2S_DataInterfaceUse expectedUseSD0, I2S_DataInterfaceUse expectedUseSD1) { + + I2SCC26XX_Object const *object; + uint8_t numbOfChannels = 0; + uint8_t sampleMemoryLength = 16; + uint16_t memoryNeeded = 0; + I2SCC26XX_DataInterface const *SD0; + I2SCC26XX_DataInterface const *SD1; + + const uint8_t byteLength = 8U; + + /* Get the pointer to the object*/ + object = handle->object; + SD0 = &object->dataInterfaceSD0; + SD1 = &object->dataInterfaceSD1; + + if(SD0->interfaceConfig == expectedUseSD0) { + numbOfChannels += SD0->numberOfChannelsUsed; + } + + if(SD1->interfaceConfig == expectedUseSD1) { + numbOfChannels += SD1->numberOfChannelsUsed; + } + + if(object->memorySlotLength == I2S_MEMORY_LENGTH_24BITS_CC26XX) { + sampleMemoryLength = 24; + } + + /*In the worst case we have 16x24x2=768 < 2^16 */ + memoryNeeded = (uint16_t)((uint16_t)numbOfChannels * (uint16_t)sampleMemoryLength * (uint16_t)2U); + + /* bits to byte conversion: we manage to have full bytes */ + if((memoryNeeded % byteLength) != 0U) { + memoryNeeded += (byteLength - (memoryNeeded % byteLength)); + } + memoryNeeded = memoryNeeded / byteLength; + + return memoryNeeded; +} + +/* + * ======== i2sPostNotify ======== + * This functions is called to notify the I2S driver of an ongoing transition + * out of sleep mode. + * + * @pre Function assumes that the I2S handle (clientArg) is pointing to a + * hardware module which has already been opened. + */ +static int i2sPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg) { + + /* Reconfigure the hardware if returning from sleep */ + if (eventType == (uint32_t)PowerCC26XX_AWAKE_STANDBY) { + initHw((I2S_Handle)clientArg); + } + + return Power_NOTIFYDONE; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2s/I2SCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2s/I2SCC26XX.h new file mode 100644 index 0000000..d279615 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2s/I2SCC26XX.h @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file I2SCC26XX.h + * + * @brief I2S driver implementation for a CC26XX I2S controller + * + * ============================================================================ + */ +#ifndef ti_drivers_i2s_I2SCC26XX__include +#define ti_drivers_i2s_I2SCC26XX__include + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief I2S Hardware attributes + * + * intPriority is the I2S peripheral's interrupt priority, as defined by the + * TI-RTOS kernel. This value is passed unmodified to Hwi_create(). + * + * pinSD1 and pinSD0 define the SD0 and SD1 data pin mapping, respectively. + * pinSCK, pinMCLK and pinWS define the SCK, MCLK and WS clock pin mapping, respectively. + * All these pins are typically defined with a macro in a header file, which maps to an IOID. + * + * A sample structure is shown below: + * @code + * const I2SCC26XX_HWAttrs i2sHWAttrs[CC26X2R1_LAUNCHXL_I2SCOUNT] = { + * { + * .pinSD1 = Board_I2S_ADI, + * .pinSD0 = Board_I2S_ADO, + * .pinSCK = Board_I2S_BCLK, + * .pinMCLK = Board_I2S_MCLK, + * .pinWS = Board_I2S_WCLK, + * .intPriority = ~0, + * }, + * }; + * @endcode + */ +typedef struct I2SCC26XX_HWAttrs_ { + PIN_Id pinSD1; /*!< Pin used for SD1 signal. */ + PIN_Id pinSD0; /*!< Pin used for SD0 signal. */ + PIN_Id pinSCK; /*!< Pin used for SCK signal. */ + PIN_Id pinMCLK; /*!< Pin used for MCLK signal. Non used in most of the applications. */ + PIN_Id pinWS; /*!< Pin used for WS signal. */ + uint8_t intPriority; /*!< I2S Peripheral's interrupt priority. */ + +}I2SCC26XX_HWAttrs; + +/*! + * @cond NODOC + * I2S data-interface + * + * This enum defines how the physical I2S interface (SD0/SD1) behaves. + * Do not modify. + */ +typedef struct I2SCC26XX_DataInterface_ { + uint8_t numberOfChannelsUsed; /*!< Number of channels used on SDx. */ + I2S_ChannelConfig channelsUsed; /*!< List of the used channels. */ + I2S_DataInterfaceUse interfaceConfig; /*!< IN / OUT / UNUSED */ +}I2SCC26XX_DataInterface; +/*! @endcond */ + +/*! + * @cond NODOC + * I2S interface + * + * This enum defines one of the interfaces (READ or WRITE) of the I2S module. + * Do not modify. + */ +typedef struct I2SCC26XX_Interface_ { + uint16_t memoryStep; /*!< Size of the memory step to access the following sample */ + uint16_t delay; /*!< Number of WS cycles to wait before starting the first transfer. This value is mostly used when performing constant latency transfers. */ + I2S_Callback callback; /*!< Pointer to callback */ + I2S_RegUpdate pointerSet; /*!< Pointer on the function used to update PTR-NEXT */ + I2S_Transaction *activeTransfer; /*!< Pointer on the ongoing transfer */ +}I2SCC26XX_Interface; +/*! @endcond */ + +/*! + * @brief The definition of a function used by the I2S driver + * to refresh the pointer + * + * @param I2S_Handle I2S_Handle + * + * @param I2SCC26XX_Interface *interface Pointer on the interface to update + * + */ +typedef void (*I2SCC26XX_PtrUpdate)(I2S_Handle handle, I2SCC26XX_Interface *interface); + +/*! + * @cond NODOC + * I2S Object. The application must not access any member variables + * of this structure! + */ +typedef struct I2SCC26XX_Object_ { + + bool isOpen; /*!< To avoid multiple openings of the I2S. */ + bool invertWS; /*!< WS inversion. + false: The WS signal is not internally inverted. + true: The WS signal is internally inverted. */ + uint8_t memorySlotLength; /*!< Select the size of the memory used. The two options are 16 bits and 24 bits. Any value can be selected, whatever the value of ::i2sBitsPerWord. + I2S_MEMORY_LENGTH_16BITS_CC26XX: Memory length is 16 bits. + I2S_MEMORY_LENGTH_24BITS_CC26XX: Memory length is 24 bits.*/ + uint8_t bitsPerWord; /*!< Number of bits per word (must be between 8 and 24 bits). */ + uint8_t beforeWordPadding; /*!< Number of SCK periods between the first WS edge and the MSB of the first audio channel data transferred during the phase.*/ + uint8_t afterWordPadding; /*!< Number of SCK periods between the LSB of the last audio channel data transferred during the phase and the following WS edge.*/ + uint8_t dmaBuffSizeConfig; /*!< Number of consecutive bytes of the samples buffers. This field must be set to a value x between 1 and 255. All the data buffers used must contain N*x bytes (with N an intger verifying N>0). */ + I2S_SamplingEdge samplingEdge; /*!< Select edge sampling type. + I2S_SAMPLING_EDGE_FALLING: Sampling on falling edges. + I2S_SAMPLING_EDGE_RISING: Sampling on raising edges. */ + I2S_Role moduleRole; /*!< Select if the current device is a Slave or a Master. + I2S_SLAVE: The device is a slave (clocks are generated externally). + I2S_MASTER: The device is a master (clocks are generated internally). */ + I2S_PhaseType phaseType; /*!< Select phase type. + I2S_PHASE_TYPE_SINGLE: Single phase. + I2S_PHASE_TYPE_DUAL: Dual phase.*/ + uint16_t MCLKDivider; /*!< Frequency divider for the MCLK signal. */ + uint16_t SCKDivider; /*!< Frequency divider for the SCK signal. */ + uint16_t WSDivider; /*!< Frequency divider for the WS signal. */ + uint16_t startUpDelay; /*!< Time (in number of WS cycles) to wait before the first transfer. */ + I2SCC26XX_DataInterface dataInterfaceSD0; /*!< Structure to describe the SD0 interface */ + I2SCC26XX_DataInterface dataInterfaceSD1; /*!< Structure to describe the SD1 interface */ + + /* PIN driver state object and handle */ + PIN_State pinState; /*!< Pin state for the used pins */ + PIN_Handle hPin; /*!< Handle on the used pins */ + + /* I2S SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object for interrupts */ + I2SCC26XX_PtrUpdate ptrUpdateFxn; /*!< Pointer on the function used to update IN and OUT PTR-NEXT */ + I2SCC26XX_Interface read; /*!< Structure to describe the read (in) interface */ + I2SCC26XX_Interface write; /*!< Structure to describe the write (out) interface */ + I2S_Callback errorCallback; /*!< Pointer to error callback */ + + /* I2S pre and post notification functions */ + void *i2sPreFxn; /*!< I2S pre-notification function pointer */ + void *i2sPostFxn; /*!< I2S post-notification function pointer */ + Power_NotifyObj i2sPreObj; /*!< I2S pre-notification object */ + Power_NotifyObj i2sPostObj; /*!< I2S post-notification object */ + volatile bool i2sPowerConstraint; /*!< I2S power constraint flag, guard to avoid power constraints getting out of sync */ + +} I2SCC26XX_Object; +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_i2s_I2SCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc13x0.am3g b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc13x0.am3g new file mode 100644 index 0000000..6da26ce Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc13x0.am3g differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc13x0.arm3 b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc13x0.arm3 new file mode 100644 index 0000000..f08718c Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc13x0.arm3 differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc13x2.am4fg b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc13x2.am4fg new file mode 100644 index 0000000..f90ab36 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc13x2.am4fg differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc13x2.arm4f b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc13x2.arm4f new file mode 100644 index 0000000..e64a0e0 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc13x2.arm4f differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc26x0.am3g b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc26x0.am3g new file mode 100644 index 0000000..27cb751 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc26x0.am3g differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc26x0.arm3 b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc26x0.arm3 new file mode 100644 index 0000000..b1656bb Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc26x0.arm3 differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc26x2.am4fg b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc26x2.am4fg new file mode 100644 index 0000000..0138419 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc26x2.am4fg differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc26x2.arm4f b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc26x2.arm4f new file mode 100644 index 0000000..e605935 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/lib/drivers_cc26x2.arm4f differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSCC26XX.c new file mode 100644 index 0000000..841afca --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSCC26XX.c @@ -0,0 +1,557 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== NVSCC26XX.c ======== + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/flash.h) +#include DeviceFamily_constructPath(driverlib/vims.h) +#include DeviceFamily_constructPath(driverlib/aon_batmon.h) + +/* max number of bytes to write at a time to minimize interrupt latency */ +#define MAX_WRITE_INCREMENT 8 + +/* Max number of writes per row of memory */ +#define MAX_WRITES_PER_FLASH_ROW (83) + +static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, + size_t size); +static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size); +static uint8_t disableFlashCache(void); +static void restoreFlashCache(uint8_t mode); + +extern NVS_Config NVS_config[]; +extern const uint8_t NVS_count; + +/* NVS function table for NVSCC26XX implementation */ +const NVS_FxnTable NVSCC26XX_fxnTable = { + NVSCC26XX_close, + NVSCC26XX_control, + NVSCC26XX_erase, + NVSCC26XX_getAttrs, + NVSCC26XX_init, + NVSCC26XX_lock, + NVSCC26XX_open, + NVSCC26XX_read, + NVSCC26XX_unlock, + NVSCC26XX_write +}; + +/* + * Semaphore to synchronize access to flash region. + */ +static SemaphoreP_Handle writeSem; + +static size_t sectorSize; /* fetched during init() */ +static size_t sectorBaseMask; /* for efficient argument checking */ + +/* + * ======== NVSCC26XX_close ======== + */ +void NVSCC26XX_close(NVS_Handle handle) +{ + NVSCC26XX_Object *object; + + object = handle->object; + object->opened = false; +} + +/* + * ======== NVSCC26XX_control ======== + */ +int_fast16_t NVSCC26XX_control(NVS_Handle handle, uint_fast16_t cmd, + uintptr_t arg) +{ + return (NVS_STATUS_UNDEFINEDCMD); +} + +/* + * ======== NVSCC26XX_erase ======== + */ +int_fast16_t NVSCC26XX_erase(NVS_Handle handle, size_t offset, size_t size) +{ + int_fast16_t status; + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + status = doErase(handle, offset, size); + + SemaphoreP_post(writeSem); + + return (status); +} + +/* + * ======== NVSCC26XX_getAttrs ======== + */ +void NVSCC26XX_getAttrs(NVS_Handle handle, NVS_Attrs *attrs) +{ + NVSCC26XX_HWAttrs const *hwAttrs; + + hwAttrs = handle->hwAttrs; + + /* FlashSectorSizeGet() returns the size of a flash sector in bytes. */ + attrs->regionBase = hwAttrs->regionBase; + attrs->regionSize = hwAttrs->regionSize; + attrs->sectorSize = FlashSectorSizeGet(); +} + +/* + * ======== NVSCC26XX_init ======== + */ +void NVSCC26XX_init() +{ + unsigned int key; + SemaphoreP_Handle sem; + + /* initialize energy saving variables */ + sectorSize = FlashSectorSizeGet(); + sectorBaseMask = ~(sectorSize - 1); + + /* speculatively create a binary semaphore for thread safety */ + sem = SemaphoreP_createBinary(1); + /* sem == NULL will be detected in 'open' */ + + key = HwiP_disable(); + + if (writeSem == NULL) { + /* use the binary sem created above */ + writeSem = sem; + HwiP_restore(key); + } + else { + /* init already called */ + HwiP_restore(key); + /* delete unused Semaphore */ + if (sem) SemaphoreP_delete(sem); + } +} + +/* + * ======== NVSCC26XX_lock ======= + */ +int_fast16_t NVSCC26XX_lock(NVS_Handle handle, uint32_t timeout) +{ + if (SemaphoreP_pend(writeSem, timeout) != SemaphoreP_OK) { + return (NVS_STATUS_TIMEOUT); + } + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== NVSCC26XX_open ======= + */ +NVS_Handle NVSCC26XX_open(uint_least8_t index, NVS_Params *params) +{ + NVSCC26XX_Object *object; + NVSCC26XX_HWAttrs const *hwAttrs; + NVS_Handle handle; + + /* Confirm that 'init' has successfully completed */ + if (writeSem == NULL) { + NVSCC26XX_init(); + if (writeSem == NULL) { + return (NULL); + } + } + + /* verify NVS region index */ + if (index >= NVS_count) { + return (NULL); + } + + handle = &NVS_config[index]; + object = NVS_config[index].object; + hwAttrs = NVS_config[index].hwAttrs; + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + if (object->opened == true) { + SemaphoreP_post(writeSem); + return (NULL); + } + + /* The regionBase must be aligned on a flash page boundary */ + if ((size_t)(hwAttrs->regionBase) & (sectorSize - 1)) { + SemaphoreP_post(writeSem); + return (NULL); + } + + /* The region cannot be smaller than a sector size */ + if (hwAttrs->regionSize < sectorSize) { + SemaphoreP_post(writeSem); + return (NULL); + } + + /* The region size must be a multiple of sector size */ + if (hwAttrs->regionSize != (hwAttrs->regionSize & sectorBaseMask)) { + SemaphoreP_post(writeSem); + return (NULL); + } + +#if defined(NVSCC26XX_INSTRUMENTED) + /* Check scoreboard parameters are defined & correct */ + if (hwAttrs->scoreboard && + (hwAttrs->flashPageSize == 0 || hwAttrs->scoreboardSize < + (hwAttrs->regionSize / hwAttrs->flashPageSize))) { + SemaphoreP_post(writeSem); + return (NULL); + } +#endif + + object->opened = true; + + SemaphoreP_post(writeSem); + + return (handle); +} + +/* + * ======== NVSCC26XX_read ======= + */ +int_fast16_t NVSCC26XX_read(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize) +{ + NVSCC26XX_HWAttrs const *hwAttrs; + + hwAttrs = handle->hwAttrs; + + /* Validate offset and bufferSize */ + if (offset + bufferSize > hwAttrs->regionSize) { + return (NVS_STATUS_INV_OFFSET); + } + + /* + * Get exclusive access to the region. We don't want someone + * else to erase the region while we are reading it. + */ + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + memcpy(buffer, (char *)(hwAttrs->regionBase) + offset, bufferSize); + + SemaphoreP_post(writeSem); + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== NVSCC26XX_unlock ======= + */ +void NVSCC26XX_unlock(NVS_Handle handle) +{ + SemaphoreP_post(writeSem); +} + +/* + * ======== NVSCC26XX_write ======= + */ +int_fast16_t NVSCC26XX_write(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize, uint_fast16_t flags) +{ + NVSCC26XX_HWAttrs const *hwAttrs; + unsigned int key; + unsigned int size; + uint32_t status = 0; + int i; + uint8_t mode; + uint8_t *srcBuf, *dstBuf; + size_t writeIncrement; + int retval = NVS_STATUS_SUCCESS; + +#if defined(NVSCC26XX_INSTRUMENTED) + size_t bytesWritten; + uint32_t sbIndex, writeOffset; +#endif + + hwAttrs = handle->hwAttrs; + + /* Validate offset and bufferSize */ + if (offset + bufferSize > hwAttrs->regionSize) { + return (NVS_STATUS_INV_OFFSET); + } + + /* Get exclusive access to the Flash region */ + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + /* If erase is set, erase destination sector(s) first */ + if (flags & NVS_WRITE_ERASE) { + size = bufferSize & sectorBaseMask; + if (bufferSize & (~sectorBaseMask)) { + size += sectorSize; + } + + retval = doErase(handle, offset & sectorBaseMask, size); + if (retval != NVS_STATUS_SUCCESS) { + SemaphoreP_post(writeSem); + return (retval); + } + } + else if (flags & NVS_WRITE_PRE_VERIFY) { + /* + * If pre-verify, each destination byte must be able to be changed to the + * source byte (1s to 0s, not 0s to 1s). + * this is satisfied by the following test: + * src == (src & dst) + */ + dstBuf = (uint8_t *)((uint32_t)(hwAttrs->regionBase) + offset); + srcBuf = buffer; + for (i = 0; i < bufferSize; i++) { + if (srcBuf[i] != (srcBuf[i] & dstBuf[i])) { + SemaphoreP_post(writeSem); + return (NVS_STATUS_INV_WRITE); + } + } + } + + srcBuf = buffer; + size = bufferSize; + dstBuf = (uint8_t *)((uint32_t)(hwAttrs->regionBase) + offset); + + mode = disableFlashCache(); + + while (size) { + if (size > MAX_WRITE_INCREMENT) { + writeIncrement = MAX_WRITE_INCREMENT; + } + else { + writeIncrement = size; + } + key = HwiP_disable(); + status = FlashProgram((uint8_t*)srcBuf, (uint32_t)dstBuf, + writeIncrement); + HwiP_restore(key); + + if (status != 0) { + break; + } + else { + size -= writeIncrement; + srcBuf += writeIncrement; + dstBuf += writeIncrement; + } + } + + restoreFlashCache(mode); + +#if defined(NVSCC26XX_INSTRUMENTED) + if (hwAttrs->scoreboard) { + /* + * Write counts are updated even if an error occurs & not all data was + * written. + */ + bytesWritten = bufferSize - size; + writeOffset = offset; + + while (bytesWritten) { + if (bytesWritten > MAX_WRITE_INCREMENT) { + writeIncrement = MAX_WRITE_INCREMENT; + } + else { + writeIncrement = bytesWritten; + } + + sbIndex = writeOffset / hwAttrs->flashPageSize; + hwAttrs->scoreboard[sbIndex]++; + + /* Spin forever if the write limit is exceeded */ + if (hwAttrs->scoreboard[sbIndex] > MAX_WRITES_PER_FLASH_ROW) { + while (1); + } + + writeOffset += writeIncrement; + bytesWritten -= writeIncrement; + } + } +#endif + + if (status != 0) { + retval = NVS_STATUS_ERROR; + } + else if (flags & NVS_WRITE_POST_VERIFY) { + /* + * Note: This validates the entire region even on erase mode. + */ + dstBuf = (uint8_t *)((uint32_t)(hwAttrs->regionBase) + offset); + srcBuf = buffer; + + for (i = 0; i < bufferSize; i++) { + if (srcBuf[i] != dstBuf[i]) { + retval = NVS_STATUS_ERROR; + break; + } + } + } + + SemaphoreP_post(writeSem); + + return (retval); +} + +/* + * ======== checkEraseRange ======== + */ +static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, + size_t size) +{ + NVSCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (offset != (offset & sectorBaseMask)) { + return (NVS_STATUS_INV_ALIGNMENT); /* poorly aligned start */ + /* address */ + } + + if (offset >= hwAttrs->regionSize) { + return (NVS_STATUS_INV_OFFSET); /* offset is past end of region */ + } + + if (offset + size > hwAttrs->regionSize) { + return (NVS_STATUS_INV_SIZE); /* size is too big */ + } + + if (size != (size & sectorBaseMask)) { + return (NVS_STATUS_INV_SIZE); /* size is not a multiple of */ + /* sector size */ + } + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== doErase ======== + */ +static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size) +{ + NVSCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + unsigned int key; + uint8_t mode; + uint32_t status = 0; + uint32_t sectorBase; + int_fast16_t rangeStatus; + +#if defined(NVSCC26XX_INSTRUMENTED) + uint32_t i; + uint32_t sbIndex; +#endif + + /* sanity test the erase args */ + rangeStatus = checkEraseRange(handle, offset, size); + + if (rangeStatus != NVS_STATUS_SUCCESS) { + return (rangeStatus); + } + + sectorBase = (uint32_t)hwAttrs->regionBase + offset; + + mode = disableFlashCache(); + + while (size) { + key = HwiP_disable(); + status = FlashSectorErase(sectorBase); + HwiP_restore(key); + + if (status != FAPI_STATUS_SUCCESS) { + break; + } + +#if defined(NVSCC26XX_INSTRUMENTED) + if (hwAttrs->scoreboard) { + /* + * Sector successfully erased; now we must clear scoreboard write + * counts for all pages in the sector. + */ + sbIndex = (sectorBase - (uint32_t) hwAttrs->regionBase) / + hwAttrs->flashPageSize; + + for (i = 0; i < (sectorSize / hwAttrs->flashPageSize); i++) { + hwAttrs->scoreboard[sbIndex + i] = 0; + } + } +#endif + + sectorBase += sectorSize; + size -= sectorSize; + } + + restoreFlashCache(mode); + + if (status != FAPI_STATUS_SUCCESS) { + return (NVS_STATUS_ERROR); + } + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== disableFlashCache ======== + * When updating the Flash, the VIMS (Vesatile Instruction Memory System) + * mode must be set to GPRAM or OFF, before programming, and both VIMS + * flash line buffers must be set to disabled. + */ +static uint8_t disableFlashCache(void) +{ + uint8_t mode = VIMSModeGet(VIMS_BASE); + + VIMSLineBufDisable(VIMS_BASE); + + if (mode != VIMS_MODE_DISABLED) { + VIMSModeSet(VIMS_BASE, VIMS_MODE_DISABLED); + while (VIMSModeGet(VIMS_BASE) != VIMS_MODE_DISABLED); + } + + return (mode); +} + +/* + * ======== restoreFlashCache ======== + */ +static void restoreFlashCache(uint8_t mode) +{ + if (mode != VIMS_MODE_DISABLED) { + VIMSModeSet(VIMS_BASE, VIMS_MODE_ENABLED); + } + + VIMSLineBufEnable(VIMS_BASE); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSCC26XX.h new file mode 100644 index 0000000..8ec0506 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSCC26XX.h @@ -0,0 +1,359 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file NVSCC26XX.h + * @brief Non-Volatile Storage driver for CC13XX/CC26XX devices. + * + * ## Interrupt Latency During Flash Operations # + * + * When writing or erasing flash, interrupts must be disabled to avoid + * executing code in flash while the flash is being reprogrammed. This + * constraint is handled by the driver. Application code does not need + * to safeguard against this. + * + * Additionally, to avoid extremely large interrupt latencies that would be + * incurred if entire blocks were written with interrupts disabled, block + * writes to flash are broken into multiple smaller sizes. + * + * Even with this scheme in place, latencies of roughly 64 microseconds will + * be incurred while flash is being written to. + * + * A similar caveat applies to flash erase operations. Erasing an entire + * flash sector (the minimal amount that can be erased at a time) can take + * roughly 8 milliseconds. This entire operation must be performed with + * interrupts disabled. Here again, this requirement is met internally + * by the driver and flash region erases are performed one sector at a + * time to minimize this significant latency impact. + * + * Care must be taken by the user to not perform flash write or erase + * operations during latency critical phases of an application. See the + * NVS_lock() and NVS_unlock() API descriptions for more information. + * + * ## Maximum flash writes before erase # + * + * On CC13XX & CC26XX memory rows can be 128 or 256 bytes in length; refer to + * the device datasheet for the exact size. A maximum of 83 write operations + * can be performed on a memory row. Once the limit is reached, the row must + * be erased before it is written to again. It is the developer's + * responsibility to ensure that this limit is not exceeded in their + * applications. The developer may also opt to use the third party SPIFFS + * library implementation supported by TIRTOS which does track writes. + * + * \note The 83 write limit persists through device reset & power cycles. + * If 60 write operations were performed on a memory row & the device is + * reset; the page can still only be written to 23 more times before it must + * be erased. + * + * A write "Scoreboard" can be enabled in this driver; the scoreboard keeps + * track of how many times a page has been written to. It is provided as a + * debug tool to ensure the 83 write limit is not exceeded. If a page is + * written to more than 83 times, the NVSCC26XX driver will spin forever. + * Each byte in the scoreboard corresponds to a memory page in the NVS region. + * The byte is incremented when the memory is written to & set to 0 when + * erased. + * + * To enable the "scoreboard" the "NVSCC26XX_INSTRUMENTED" symbol must be + * defined when the driver is compiled. Three new fields are added to the + * #NVSCC26XX_HWAttrs structure: + * * scoreboard - a buffer provided by the application where each byte + * represents how many times a page has been written to. + * * scoreboardSize - number of bytes in the scoreboard. + * * flashPageSize - number of bytes in a flash page (i.e. 128 or 256) + * + * When configured correctly, the scoreboard can be viewed in a memory browser. + * + * \note The scoreboard will only keep track of writes to flash within a + * NVS region using a NVS driver. Writes performed outside the NVS + * region or without the NVS driver are untracked. + * + * \note The scoreboard is in RAM & will be lost on reset or power cycle. + * + * + * ============================================================================ + */ + +#ifndef ti_drivers_nvs_NVSCC26XX__include +#define ti_drivers_nvs_NVSCC26XX__include + +#include +#include + +#if defined (__cplusplus) +extern "C" { +#endif + +/*! + * @brief Error status code returned by NVS_erase(), NVS_write(). + * + * This error status is returned if the system voltage is too low to safely + * perform the flash operation. Voltage must be 1.5V or greater. + */ +#define NVSCC26XX_STATUS_LOW_VOLTAGE (NVS_STATUS_RESERVED - 1) + +/*! + * @internal @brief NVS function pointer table + * + * 'NVSCC26XX_fxnTable' is a fully populated function pointer table + * that can be referenced in the NVS_config[] array entries. + * + * Users can minimize their application code size by providing their + * own custom NVS function pointer table that contains only those APIs + * used by the application. + * + * An example of a custom NVS function table is shown below: + * @code + * // + * // Since the application does not use the + * // NVS_control(), NVS_lock(), and NVS_unlock() APIs, + * // these APIs are removed from the function + * // pointer table and replaced with NULL + * // + * const NVS_FxnTable myNVS_fxnTable = { + * NVSCC26XX_close, + * NULL, // remove NVSCC26XX_control(), + * NVSCC26XX_erase, + * NVSCC26XX_getAttrs, + * NVSCC26XX_init, + * NULL, // remove NVSCC26XX_lock(), + * NVSCC26XX_open, + * NVSCC26XX_read, + * NULL, // remove NVSCC26XX_unlock(), + * NVSCC26XX_write + * }; + * @endcode + */ +extern const NVS_FxnTable NVSCC26XX_fxnTable; + +/*! + * @brief NVSCC26XX hardware attributes + * + * The NVSCC26XX hardware attributes define hardware specific settings + * for a NVS driver instance. + * + * \note Care must be taken to ensure that the linker does not place application + * content (such as .text or .const) in the flash regions defined by the + * this hardware attributes structure. + * + * For CCS and IAR tools, defining and reserving flash memory regions can + * be done entirely within the Board.c file. For GCC, additional content is + * required in the application's linker script to achieve the same + * result. + * + * The example below defines a char array @p flashBuf. Preprocessor logic is + * used so that this example will work with either the TI, IAR or GCC tools. + * For the TI and IAR tools, pragmas are used to place @p flashBuf at the + * flash location specified by #NVSCC26XX_HWAttrs.regionBase. + * + * For the GCC tool, the @p flashBuf array is placed into a named linker output + * section, @p .nvs. This section is defined in the application's linker + * script. The section placement command is carefully chosen to only RESERVE + * space for the @p flashBuf array, and not to actually initialize it during + * the application load process, thus preserving the content of flash. + * + * Regardless of tool chain, the @p flashBuf array in the example below is + * placed at the @p NVS_REGIONS_BASE address and has an overall size of + * @p REGIONSIZE bytes. Theoretically, the memory reserved by @p flashBuf can + * be divided into four separate regions, each having a size of @p SECTORSIZE + * bytes. Each region must always be aligned to the flash sector size, + * @p SECTORSIZE. This example below shows two regions defined. + * + * An array of two #NVSCC26XX_HWAttrs structures is defined. Each index + * of this structure defines a region of on-chip flash memory. Both regions + * utilize memory reserved by the @p flashBuf array. The two regions do not + * overlap or share the same physical memory locations. The two regions do + * however exist adjacent to each other in physical memory. The first + * region is defined as starting at the @p NVS_REGIONS_BASE address and has a + * size equal to the flash sector size, as defined by @p SECTORSIZE. The second + * region is defined as starting at (NVS_REGIONS_BASE + SECTORSIZE), that is, + * the @p NVS_REGIONS_BASE address offset by @p SECTORSIZE bytes. The second region + * has a size equal to (3 * SECTORSIZE) bytes. These regions together fully + * occupy @p REGIONSIZE bytes of physical on-chip flash memory as reserved by + * the @p flashBuf array. + * + * @code + * #define NVS_REGIONS_BASE 0x1B000 + * #define SECTORSIZE 0x1000 + * #define REGIONSIZE (SECTORSIZE * 4) + * + * // + * // Reserve flash sectors for NVS driver use + * // by placing an uninitialized byte array + * // at the desired flash address. + * // + * #if defined(__TI_COMPILER_VERSION__) + * + * // + * // Place uninitialized array at FLASH_REGION_BASE + * // + * #pragma LOCATION(flashBuf, FLASH_REGION_BASE); + * #pragma NOINIT(flashBuf); + * char flashBuf[REGIONSIZE]; + * + * #elif defined(__IAR_SYSTEMS_ICC__) + * + * // + * // Place uninitialized array at FLASH_REGION_BASE + * // + * __no_init char flashBuf[REGIONSIZE] @ FLASH_REGION_BASE; + * + * #elif defined(__GNUC__) + * + * // + * // Place the flash buffers in the .nvs section created in the gcc linker file. + * // The .nvs section enforces alignment on a sector boundary but may + * // be placed anywhere in flash memory. If desired the .nvs section can be set + * // to a fixed address by changing the following in the gcc linker file: + * // + * // .nvs (FIXED_FLASH_ADDR) (NOLOAD) : AT (FIXED_FLASH_ADDR) { + * // *(.nvs) + * // } > REGION_TEXT + * // + * + * __attribute__ ((section (".nvs"))) + * char flashBuf[REGIONSIZE]; + * + * #endif + * + * NVSCC26XX_HWAttrs nvsCC26XXHWAttrs[2] = { + * // + * // region 0 is 1 flash sector in length. + * // + * { + * .regionBase = (void *)flashBuf, + * .regionSize = SECTORSIZE, + * }, + * // + * // region 1 is 3 flash sectors in length. + * // + * { + * .regionBase = (void *)(flashBuf + SECTORSIZE), + * .regionSize = SECTORSIZE * 3, + * } + * }; + * @endcode + * + * Example GCC linker script file content. This example places an output + * section, @p .nvs, at the memory address @p 0x1B000. The @p NOLOAD directive + * is used so that this memory is not initialized during program load to the + * target. + * + * @code + * MEMORY + * { + * FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x0001ffa8 + * FLASH_CCFG (RX) : ORIGIN = 0x0001ffa8, LENGTH = 0x00000058 + * SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00005000 + * } + * + * .nvs (0x1b000) (NOLOAD) : AT (0x1b000) { + * *(.nvs) + * } > REGION_TEXT + * @endcode + * + * If the write "scoreboard" is enabled, three new fields are added to the + * NVSCC26XX_HWAttrs structure: + * * scoreboard - a buffer provided by the application where each byte + * represents how many times a page has been written to. It is important + * that this buffer be large enough such that there is a byte for each + * page of memory in the NVS region. For example: + * - 64k NVS region + * - 256 byte page size + * - 64k / 256 = 256; the scoreboard buffer must be 256 bytes in length + * + * * scoreboardSize - number of bytes in the scoreboard. + * + * * flashPageSize - number of bytes in a flash page (i.e. 128 or 256) + */ +typedef struct +{ + void *regionBase; /*!< The regionBase field specifies the base + address of the on-chip flash memory to be + managed. The regionBase must be aligned + to the flash sector size. This memory + cannot be shared and must be for exclusive + use by one NVS driver instance. */ + + size_t regionSize; /*!< The regionSize field specifies the + overall size of the on-chip flash memory + to be managed. The regionSize must be at + least 1 flash sector size AND an integer + multiple of the flash sector size. For most + CC26XX/CC13XX devices, the flash sector + size is 4096 bytes. The NVSCC26XX driver + will determine the device's actual sector + size by reading internal system + configuration registers. */ + +#if defined(NVSCC26XX_INSTRUMENTED) + uint8_t *scoreboard; /*!< Pointer to scoreboard */ + size_t scoreboardSize; /*!< Scoreboard size in bytes */ + uint32_t flashPageSize; /*!< Size of a memory page in bytes */ +#endif +} NVSCC26XX_HWAttrs; + +/* + * @brief NVSCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + bool opened; /* Has this region been opened */ +} NVSCC26XX_Object; + +/*! + * @cond NODOC + * NVSCC26XX driver public APIs + */ + +extern void NVSCC26XX_close(NVS_Handle handle); +extern int_fast16_t NVSCC26XX_control(NVS_Handle handle, uint_fast16_t cmd, + uintptr_t arg); +extern int_fast16_t NVSCC26XX_erase(NVS_Handle handle, size_t offset, + size_t size); +extern void NVSCC26XX_getAttrs(NVS_Handle handle, NVS_Attrs *attrs); +extern void NVSCC26XX_init(); +extern int_fast16_t NVSCC26XX_lock(NVS_Handle handle, uint32_t timeout); +extern NVS_Handle NVSCC26XX_open(uint_least8_t index, NVS_Params *params); +extern int_fast16_t NVSCC26XX_read(NVS_Handle handle, size_t offset, + void *buffer, size_t bufferSize); +extern void NVSCC26XX_unlock(NVS_Handle handle); +extern int_fast16_t NVSCC26XX_write(NVS_Handle handle, size_t offset, + void *buffer, size_t bufferSize, uint_fast16_t flags); +/*! @endcond */ + +#if defined (__cplusplus) +} +#endif /* defined (__cplusplus) */ + +/*@}*/ +#endif /* ti_drivers_nvs_NVSCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSRAM.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSRAM.c new file mode 100644 index 0000000..008358f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSRAM.c @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== NVSRAM.c ======== + */ + +#include +#include +#include + +#include +#include + +#include +#include + +static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size); +static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size); + +extern NVS_Config NVS_config[]; +extern const uint8_t NVS_count; + +/* NVS function table for NVSRAM implementation */ +const NVS_FxnTable NVSRAM_fxnTable = { + NVSRAM_close, + NVSRAM_control, + NVSRAM_erase, + NVSRAM_getAttrs, + NVSRAM_init, + NVSRAM_lock, + NVSRAM_open, + NVSRAM_read, + NVSRAM_unlock, + NVSRAM_write +}; + +/* + * Semaphore to synchronize access to the region. + */ +static SemaphoreP_Handle writeSem; + +/* + * ======== NVSRAM_close ======== + */ +void NVSRAM_close(NVS_Handle handle) +{ + ((NVSRAM_Object *) handle->object)->isOpen = false; +} + +/* + * ======== NVSRAM_control ======== + */ +int_fast16_t NVSRAM_control(NVS_Handle handle, uint_fast16_t cmd, + uintptr_t arg) +{ + return (NVS_STATUS_UNDEFINEDCMD); +} + +/* + * ======== NVSRAM_erase ======== + */ +int_fast16_t NVSRAM_erase(NVS_Handle handle, size_t offset, size_t size) +{ + int_fast16_t status; + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + status = doErase(handle, offset, size); + + SemaphoreP_post(writeSem); + + return (status); +} + +/* + * ======== NVSRAM_getAttrs ======== + */ +void NVSRAM_getAttrs(NVS_Handle handle, NVS_Attrs *attrs) +{ + NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; + + attrs->regionBase = hwAttrs->regionBase; + attrs->regionSize = hwAttrs->regionSize; + attrs->sectorSize = hwAttrs->sectorSize; +} + +/* + * ======== NVSRAM_init ======== + */ +void NVSRAM_init() +{ + uintptr_t key; + SemaphoreP_Handle sem; + + /* speculatively create a binary semaphore for thread safety */ + sem = SemaphoreP_createBinary(1); + /* sem == NULL will be detected in 'open' */ + + key = HwiP_disable(); + + if (writeSem == NULL) { + /* use the binary sem created above */ + writeSem = sem; + HwiP_restore(key); + } + else { + /* init already called */ + HwiP_restore(key); + + /* delete unused Semaphore */ + if (sem) { + SemaphoreP_delete(sem); + } + } +} + +/* + * ======== NVSRAM_lock ======= + */ +int_fast16_t NVSRAM_lock(NVS_Handle handle, uint32_t timeout) +{ + if (SemaphoreP_pend(writeSem, timeout) != SemaphoreP_OK) { + return (NVS_STATUS_TIMEOUT); + } + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== NVSRAM_open ======= + */ +NVS_Handle NVSRAM_open(uint_least8_t index, NVS_Params *params) +{ + NVS_Handle handle; + NVSRAM_Object *object; + NVSRAM_HWAttrs const *hwAttrs; + + /* Confirm that 'init' has successfully completed */ + if (writeSem == NULL) { + NVSRAM_init(); + if (writeSem == NULL) { + return (NULL); + } + } + + /* verify NVS region index */ + if (index >= NVS_count) { + return (NULL); + } + + handle = &NVS_config[index]; + object = NVS_config[index].object; + hwAttrs = NVS_config[index].hwAttrs; + + /* for efficient argument checking */ + object->sectorBaseMask = ~(hwAttrs->sectorSize - 1); + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + if (object->isOpen) { + SemaphoreP_post(writeSem); + + return (NULL); + } + + /* The regionBase must be aligned on a page boundary */ + if ((size_t) (hwAttrs->regionBase) & (hwAttrs->sectorSize - 1)) { + SemaphoreP_post(writeSem); + + return (NULL); + } + + /* The region cannot be smaller than a sector size */ + if (hwAttrs->regionSize < hwAttrs->sectorSize) { + SemaphoreP_post(writeSem); + + return (NULL); + } + + /* The region size must be a multiple of sector size */ + if (hwAttrs->regionSize != + (hwAttrs->regionSize & object->sectorBaseMask)) { + SemaphoreP_post(writeSem); + return (NULL); + } + + object->isOpen = true; + + SemaphoreP_post(writeSem); + + return (handle); +} + +/* + * ======== NVSRAM_read ======= + */ +int_fast16_t NVSRAM_read(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize) +{ + NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Validate offset and bufferSize */ + if (offset + bufferSize > hwAttrs->regionSize) { + return (NVS_STATUS_INV_OFFSET); + } + + /* + * Get exclusive access to the region. We don't want someone + * else to erase the region while we are reading it. + */ + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + memcpy(buffer, (char *)(hwAttrs->regionBase) + offset, bufferSize); + + SemaphoreP_post(writeSem); + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== NVSRAM_unlock ======= + */ +void NVSRAM_unlock(NVS_Handle handle) +{ + SemaphoreP_post(writeSem); +} + +/* + * ======== NVSRAM_write ======= + */ +int_fast16_t NVSRAM_write(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize, uint_fast16_t flags) +{ + size_t i; + uint8_t *dstBuf; + uint8_t *srcBuf; + int_fast16_t result; + size_t size; + NVSRAM_Object *object = handle->object; + NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Validate offset and bufferSize */ + if (offset + bufferSize > hwAttrs->regionSize) { + return (NVS_STATUS_INV_OFFSET); + } + + /* Get exclusive access to the Flash region */ + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + /* If erase is set, erase destination sector(s) first */ + if (flags & NVS_WRITE_ERASE) { + size = bufferSize & object->sectorBaseMask; + if (bufferSize & (~object->sectorBaseMask)) { + size += hwAttrs->sectorSize; + } + + result = doErase(handle, offset & object->sectorBaseMask, size); + if (result != NVS_STATUS_SUCCESS) { + SemaphoreP_post(writeSem); + + return (result); + } + } + else if (flags & NVS_WRITE_PRE_VERIFY) { + /* + * If pre-verify, each destination byte must be able to be changed to the + * source byte (1s to 0s, not 0s to 1s). + * this is satisfied by the following test: + * src == (src & dst) + */ + dstBuf = (uint8_t *)((uint32_t)(hwAttrs->regionBase) + offset); + srcBuf = buffer; + for (i = 0; i < bufferSize; i++) { + if (srcBuf[i] != (srcBuf[i] & dstBuf[i])) { + SemaphoreP_post(writeSem); + return (NVS_STATUS_INV_WRITE); + } + } + } + + dstBuf = (uint8_t *)((uint32_t)(hwAttrs->regionBase) + offset); + srcBuf = buffer; + memcpy((void *) dstBuf, (void *) srcBuf, bufferSize); + + SemaphoreP_post(writeSem); + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== checkEraseRange ======== + */ +static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size) +{ + NVSRAM_Object *object = handle->object; + NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (offset != (offset & object->sectorBaseMask)) { + /* poorly aligned start address */ + return (NVS_STATUS_INV_ALIGNMENT); + } + + if (offset >= hwAttrs->regionSize) { + /* offset is past end of region */ + return (NVS_STATUS_INV_OFFSET); + } + + if (offset + size > hwAttrs->regionSize) { + /* size is too big */ + return (NVS_STATUS_INV_SIZE); + } + + if (size != (size & object->sectorBaseMask)) { + /* size is not a multiple of sector size */ + return (NVS_STATUS_INV_SIZE); + } + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== doErase ======== + */ +static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size) +{ + void * sectorBase; + int_fast16_t rangeStatus; + NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* sanity test the erase args */ + rangeStatus = checkEraseRange(handle, offset, size); + if (rangeStatus != NVS_STATUS_SUCCESS) { + return (rangeStatus); + } + + sectorBase = (void *) ((uint32_t) hwAttrs->regionBase + offset); + + memset(sectorBase, 0xFF, size); + + return (NVS_STATUS_SUCCESS); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSRAM.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSRAM.h new file mode 100644 index 0000000..fe1b183 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSRAM.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file NVSRAM.h + * + * @brief RAM implementation of the NVS driver + * + * This NVS driver implementation makes use of RAM instead of FLASH memory. + * It can be used for developing code which relies the NVS driver without + * wearing down FLASH memory. + * + * The NVS header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_nvs_NVSRAM__include +#define ti_drivers_nvs_NVSRAM__include + +#include +#include + +#if defined (__cplusplus) +extern "C" { +#endif + +/*! + * @internal @brief NVS function pointer table + * + * 'NVSRAM_fxnTable' is a fully populated function pointer table + * that can be referenced in the NVS_config[] array entries. + * + * Users can minimize their application code size by providing their + * own custom NVS function pointer table that contains only those APIs + * used by the application. + * + * An example of a custom NVS function table is shown below: + * @code + * // + * // Since the application does not use the + * // NVS_control(), NVS_lock(), and NVS_unlock() APIs, + * // these APIs are removed from the function + * // pointer table and replaced with NULL + * // + * const NVS_FxnTable myNVS_fxnTable = { + * NVSRAM_close, + * NULL, // remove NVSRAM_control(), + * NVSRAM_erase, + * NVSRAM_getAttrs, + * NVSRAM_init, + * NULL, // remove NVSRAM_lock(), + * NVSRAM_open, + * NVSRAM_read, + * NULL, // remove NVSRAM_unlock(), + * NVSRAM_write + * }; + * @endcode + */ +extern const NVS_FxnTable NVSRAM_fxnTable; + +/*! + * @brief NVSRAM Hardware Attributes + * + * The 'sectorSize' is the minimal amount of data to that is cleared on an + * erase operation. Devices which feature internal FLASH memory usually + * have a 4096 byte sector size (refer to device specific documentation). It + * is recommended that the 'sectorSize' used match the FLASH memory sector + * size. + * + * The 'regionBase' field must point to the base address of the region + * to be managed. It is also required that the region be aligned on a + * sectorSize boundary (example below to demonstrate how to do this). + * + * The 'regionSize' must be an integer multiple of the 'sectorSize'. + * + * Defining and reserving RAM memory regions can be done entirely within the + * Board.c file. + * + * The example below defines a char array, 'ramBuf' and uses compiler + * pragmas to place 'ramBuf' at an aligned address within RAM. + * + * @code + * #define SECTORSIZE (4096) + * + * static char ramBuf[SECTORSIZE * 4] __attribute__ ((aligned (4096))); + * + * NVSRAM_HWAttrs NVSRAMHWAttrs[1] = { + * { + * .regionBase = (void *) ramBuf, + * .regionSize = SECTORSIZE * 4, + * .sectorSize = SECTORSIZE + * } + * }; + * + * + * @endcode + */ +typedef struct +{ + void *regionBase; /*!< Base address of RAM region */ + size_t regionSize; /*!< The size of the region in bytes */ + size_t sectorSize; /*!< Sector size in bytes */ +} NVSRAM_HWAttrs; + +/* + * @brief NVSRAM Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + size_t sectorBaseMask; + bool isOpen; +} NVSRAM_Object; + +/* + * @cond NODOC + * NVSRAM driver public APIs + */ + +extern void NVSRAM_close(NVS_Handle handle); +extern int_fast16_t NVSRAM_control(NVS_Handle handle, uint_fast16_t cmd, + uintptr_t arg); +extern int_fast16_t NVSRAM_erase(NVS_Handle handle, size_t offset, + size_t size); +extern void NVSRAM_getAttrs(NVS_Handle handle, NVS_Attrs *attrs); +extern void NVSRAM_init(); +extern int_fast16_t NVSRAM_lock(NVS_Handle handle, uint32_t timeout); +extern NVS_Handle NVSRAM_open(uint_least8_t index, NVS_Params *params); +extern int_fast16_t NVSRAM_read(NVS_Handle handle, size_t offset, + void *buffer, size_t bufferSize); +extern void NVSRAM_unlock(NVS_Handle handle); +extern int_fast16_t NVSRAM_write(NVS_Handle handle, size_t offset, + void *buffer, size_t bufferSize, uint_fast16_t flags); + +/*! @endcond */ + +#if defined (__cplusplus) +} +#endif /* defined (__cplusplus) */ + +/*@}*/ +#endif /* ti_drivers_nvs_NVSRAM__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSSPI25X.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSSPI25X.c new file mode 100644 index 0000000..7a8c33e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSSPI25X.c @@ -0,0 +1,976 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== NVSSPI25X.c ======== + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include + +/* Instruction codes */ +#define SPIFLASH_WRITE 0x02 /**< Page Program */ +#define SPIFLASH_READ 0x03 /**< Read Data */ +#define SPIFLASH_READ_STATUS 0x05 /**< Read Status Register */ +#define SPIFLASH_WRITE_ENABLE 0x06 /**< Write Enable */ +#define SPIFLASH_SUBSECTOR_ERASE 0x20 /**< SubSector (4K Byte) Erase */ +#define SPIFLASH_SECTOR_ERASE 0xD8 /**< Sector (64K Byte) Erase */ +#define SPIFLASH_MASS_ERASE 0xC7 /**< Erase entire flash */ + +#define SPIFLASH_RDP 0xAB /**< Release from Deep Power Down */ +#define SPIFLASH_DP 0xB9 /**< Deep Power Down */ + +/* Bitmasks of the status register */ +#define SPIFLASH_STATUS_BIT_BUSY 0x01 /**< Busy bit of status register */ + +/* Write page size assumed by this driver */ +#define SPIFLASH_PROGRAM_PAGE_SIZE 256 + +/* Highest supported SPI instance index */ +#define MAX_SPI_INDEX 3 + +/* Size of hardware sector erased by SPIFLASH_SECTOR_ERASE */ +#define SPIFLASH_SECTOR_SIZE 0x10000 + +static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size); +static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size); +static int_fast16_t doRead(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize); +static int_fast16_t doWriteVerify(NVS_Handle handle, size_t offset, + void *src, size_t srcBufSize, void *dst, + size_t dstBufSize, bool preFlag); + +static int_fast16_t extFlashSpiWrite(const uint8_t *buf, size_t len); +static int_fast16_t extFlashSpiRead(uint8_t *buf, size_t len); +static int_fast16_t extFlashPowerDown(NVS_Handle nvsHandle); +static int_fast16_t extFlashPowerStandby(NVS_Handle nvsHandle); +static int_fast16_t extFlashWaitReady(NVS_Handle nvsHandle); +static int_fast16_t extFlashWriteEnable(NVS_Handle nvsHandle); +static int_fast16_t extFlashMassErase(NVS_Handle nvsHandle); + +extern NVS_Config NVS_config[]; +extern const uint8_t NVS_count; + +/* NVS function table for NVSSPI25X implementation */ +const NVS_FxnTable NVSSPI25X_fxnTable = { + NVSSPI25X_close, + NVSSPI25X_control, + NVSSPI25X_erase, + NVSSPI25X_getAttrs, + NVSSPI25X_init, + NVSSPI25X_lock, + NVSSPI25X_open, + NVSSPI25X_read, + NVSSPI25X_unlock, + NVSSPI25X_write +}; + +/* Manage SPI indexes */ +static SPI_Handle spiHandles[MAX_SPI_INDEX + 1]; +static uint8_t spiHandleUsers[MAX_SPI_INDEX + 1]; + +/* + * Currently active (protected within Semaphore_pend() block) + * SPI handle, and CSN pin + */ +static SPI_Handle spiHandle; +static uint32_t spiCsnGpioIndex; + +/* + * Semaphore to synchronize access to flash region. + */ +static SemaphoreP_Handle writeSem; + +/* + * ======== NVSSPI25X_close ======== + */ +void NVSSPI25X_close(NVS_Handle handle) +{ + NVSSPI25X_HWAttrs const *hwAttrs; + NVSSPI25X_Object *object; + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + hwAttrs = handle->hwAttrs; + object = handle->object; + + spiHandle = object->spiHandle; + spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; + + /* Close the SPI if we opened it */ + if (hwAttrs->spiHandle == NULL) { + spiHandleUsers[hwAttrs->spiIndex] -= 1; + + /* Close SPI if this is the last region that uses it */ + if (spiHandleUsers[hwAttrs->spiIndex] == 0) { + /* Ensure part is responsive */ + extFlashWaitReady(handle); + + /* Put the part in low power mode */ + extFlashPowerDown(handle); + + SPI_close(object->spiHandle); + spiHandles[hwAttrs->spiIndex] = NULL; + } + } + + NVSSPI25X_deinitSpiCs(handle, spiCsnGpioIndex); + + object->opened = false; + + SemaphoreP_post(writeSem); +} + +/* + * ======== NVSSPI25X_control ======== + */ +int_fast16_t NVSSPI25X_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg) +{ + NVSSPI25X_HWAttrs const *hwAttrs; + NVSSPI25X_Object *object; + + if (cmd != NVSSPI25X_CMD_MASS_ERASE) return (NVS_STATUS_UNDEFINEDCMD); + + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Set protected global variables */ + spiHandle = object->spiHandle; + spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; + + return (extFlashMassErase(handle)); +} + +/* + * ======== NVSSPI25X_erase ======== + */ +int_fast16_t NVSSPI25X_erase(NVS_Handle handle, size_t offset, size_t size) +{ + int_fast16_t status; + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + status = doErase(handle, offset, size); + + SemaphoreP_post(writeSem); + + return (status); +} + +/* + * ======== NVSSPI25X_getAttrs ======== + */ +void NVSSPI25X_getAttrs(NVS_Handle handle, NVS_Attrs *attrs) +{ + NVSSPI25X_HWAttrs const *hwAttrs; + + hwAttrs = handle->hwAttrs; + + /* FlashSectorSizeGet() returns the size of a flash sector in bytes. */ + attrs->regionBase = NVS_REGION_NOT_ADDRESSABLE; + attrs->regionSize = hwAttrs->regionSize; + attrs->sectorSize = hwAttrs->sectorSize; +} + +/* + * ======== NVSSPI25X_init ======== + */ +void NVSSPI25X_init() +{ + unsigned int key; + SemaphoreP_Handle tempSem; + + SPI_init(); + + /* Speculatively create semaphore so critical section is faster */ + tempSem = SemaphoreP_createBinary(1); + /* tempSem == NULL will be detected in 'open' */ + + key = HwiP_disable(); + + if (writeSem == NULL) { + /* First time init, assign handle */ + writeSem = tempSem; + + HwiP_restore(key); + } + else { + /* Init already called */ + HwiP_restore(key); + + /* Delete unused Semaphores */ + if (tempSem) { + SemaphoreP_delete(tempSem); + } + } +} + +/* + * ======== NVSSPI25X_lock ======= + */ +int_fast16_t NVSSPI25X_lock(NVS_Handle handle, uint32_t timeout) +{ + if (SemaphoreP_pend(writeSem, timeout) != SemaphoreP_OK) { + return (NVS_STATUS_TIMEOUT); + } + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== NVSSPI25X_open ======= + */ +NVS_Handle NVSSPI25X_open(uint_least8_t index, NVS_Params *params) +{ + NVSSPI25X_Object *object; + NVSSPI25X_HWAttrs const *hwAttrs; + size_t sectorSize; + NVS_Handle handle; + SPI_Params spiParams; + + /* Confirm that 'init' has successfully completed */ + if (writeSem == NULL) { + NVSSPI25X_init(); + if (writeSem == NULL) { + return (NULL); + } + } + + /* Verify NVS region index */ + if (index >= NVS_count) { + return (NULL); + } + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + handle = &NVS_config[index]; + object = NVS_config[index].object; + hwAttrs = NVS_config[index].hwAttrs; + + if (object->opened == true) { + SemaphoreP_post(writeSem); + return (NULL); + } + + sectorSize = hwAttrs->sectorSize; + object->sectorBaseMask = ~(sectorSize - 1); + + /* The regionBase must be aligned on a flash page boundary */ + if ((hwAttrs->regionBaseOffset) & (sectorSize - 1)) { + SemaphoreP_post(writeSem); + return (NULL); + } + + /* The region cannot be smaller than a sector size */ + if (hwAttrs->regionSize < sectorSize) { + SemaphoreP_post(writeSem); + return (NULL); + } + + /* The region size must be a multiple of sector size */ + if (hwAttrs->regionSize != (hwAttrs->regionSize & object->sectorBaseMask)) { + SemaphoreP_post(writeSem); + return (NULL); + } + + if (hwAttrs->spiHandle) { + /* Use the provided SPI Handle */ + object->spiHandle = *hwAttrs->spiHandle; + } + else { + if (hwAttrs->spiIndex > MAX_SPI_INDEX) { + SemaphoreP_post(writeSem); + return (NULL); + } + /* Open SPI if this driver hasn't already opened this SPI instance */ + if (spiHandles[hwAttrs->spiIndex] == NULL) { + SPI_Handle spi; + + SPI_Params_init(&spiParams); + spiParams.bitRate = hwAttrs->spiBitRate; + spiParams.mode = SPI_MASTER; + spiParams.transferMode = SPI_MODE_BLOCKING; + + /* Attempt to open SPI. */ + spi = SPI_open(hwAttrs->spiIndex, &spiParams); + + if (spi == NULL) { + SemaphoreP_post(writeSem); + return (NULL); + } + + spiHandles[hwAttrs->spiIndex] = spi; + } + object->spiHandle = spiHandles[hwAttrs->spiIndex]; + /* Keep track of how many regions use the same SPI handle */ + spiHandleUsers[hwAttrs->spiIndex] += 1; + } + + /* Set protected global variables */ + spiHandle = object->spiHandle; + spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; + + + /* Initialize chip select output */ + NVSSPI25X_initSpiCs(handle, spiCsnGpioIndex); + + object->opened = true; + + /* Put the part in standby mode */ + extFlashPowerStandby(handle); + + SemaphoreP_post(writeSem); + + return (handle); +} + +/* + * ======== NVSSPI25X_read ======= + */ +int_fast16_t NVSSPI25X_read(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize) +{ + NVSSPI25X_HWAttrs const *hwAttrs; + int retval = NVS_STATUS_SUCCESS; + + hwAttrs = handle->hwAttrs; + + /* Validate offset and bufferSize */ + if (offset + bufferSize > hwAttrs->regionSize) { + return (NVS_STATUS_INV_OFFSET); + } + + /* + * Get exclusive access to the region. We don't want someone + * else to erase the region while we are reading it. + */ + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + retval = doRead(handle, offset, buffer, bufferSize); + + SemaphoreP_post(writeSem); + + return (retval); +} + +/* + * ======== NVSSPI25X_unlock ======= + */ +void NVSSPI25X_unlock(NVS_Handle handle) +{ + SemaphoreP_post(writeSem); +} + +/* + * ======== NVSSPI25X_write ======= + */ +int_fast16_t NVSSPI25X_write(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize, uint_fast16_t flags) +{ + NVSSPI25X_Object *object; + NVSSPI25X_HWAttrs const *hwAttrs; + size_t length, foffset; + uint32_t status = true; + uint8_t *srcBuf; + int retval = NVS_STATUS_SUCCESS; + uint8_t wbuf[4]; + + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Validate offset and bufferSize */ + if (offset + bufferSize > hwAttrs->regionSize) { + return (NVS_STATUS_INV_OFFSET); + } + + /* Get exclusive access to the Flash region */ + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + /* Set protected global variables */ + spiHandle = object->spiHandle; + spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; + + /* If erase is set, erase destination sector(s) first */ + if (flags & NVS_WRITE_ERASE) { + length = bufferSize & object->sectorBaseMask; + if (bufferSize & (~object->sectorBaseMask)) { + length += hwAttrs->sectorSize; + } + + retval = doErase(handle, offset & object->sectorBaseMask, length); + if (retval != NVS_STATUS_SUCCESS) { + SemaphoreP_post(writeSem); + return (retval); + } + } + else if (flags & NVS_WRITE_PRE_VERIFY) { + if ((hwAttrs->verifyBuf == NULL) || (hwAttrs->verifyBufSize == 0)) { + SemaphoreP_post(writeSem); + return (NVS_STATUS_ERROR); + } + + retval = doWriteVerify(handle, offset, buffer, bufferSize, + hwAttrs->verifyBuf, hwAttrs->verifyBufSize, true); + + if (retval != NVS_STATUS_SUCCESS) { + SemaphoreP_post(writeSem); + return (retval); + } + } + + srcBuf = buffer; + length = bufferSize; + foffset = (size_t)hwAttrs->regionBaseOffset + offset; + + while (length > 0) + { + size_t ilen; /* Interim length per instruction */ + + /* Wait till previous erase/program operation completes */ + int ret = extFlashWaitReady(handle); + + if (ret) { + status = false; + break; + } + + ret = extFlashWriteEnable(handle); + + if (ret) { + status = false; + break; + } + + ilen = SPIFLASH_PROGRAM_PAGE_SIZE - (foffset % SPIFLASH_PROGRAM_PAGE_SIZE); + if (length < ilen) { + ilen = length; + } + + wbuf[0] = SPIFLASH_WRITE; + wbuf[1] = (foffset >> 16) & 0xff; + wbuf[2] = (foffset >> 8) & 0xff; + wbuf[3] = foffset & 0xff; + + foffset += ilen; + length -= ilen; + + /* + * Up to 100ns CS hold time (which is not clear + * whether it's application only in between reads) + * is not imposed here since above instructions + * should be enough to delay + * as much. + */ + NVSSPI25X_assertSpiCs(handle, spiCsnGpioIndex); + + if (extFlashSpiWrite(wbuf, sizeof(wbuf)) != NVS_STATUS_SUCCESS) { + status = false; + break; + } + + if (extFlashSpiWrite(srcBuf, ilen) != NVS_STATUS_SUCCESS) { + status = false; + break; + } + + srcBuf += ilen; + NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); + } + + if (status == false) { + retval = NVS_STATUS_ERROR; + } + else if (flags & NVS_WRITE_POST_VERIFY) { + if ((hwAttrs->verifyBuf == NULL) || (hwAttrs->verifyBufSize == 0)) { + SemaphoreP_post(writeSem); + return (NVS_STATUS_ERROR); + } + + retval = doWriteVerify(handle, offset, buffer, bufferSize, + hwAttrs->verifyBuf, hwAttrs->verifyBufSize, false); + } + + SemaphoreP_post(writeSem); + + return (retval); +} + +/* + * ======== doWriteVerify ======= + */ +static int_fast16_t doWriteVerify(NVS_Handle handle, size_t offset, void *src, + size_t srcBufSize, void *dst, size_t dstBufSize, bool preFlag) +{ + size_t i, j; + uint8_t *srcBuf, *dstBuf; + bool bad; + int_fast16_t retval; + + srcBuf = src; + dstBuf = dst; + + j = dstBufSize; + + for (i = 0; i < srcBufSize; i++, j++) { + if (j == dstBufSize) { + retval = doRead(handle, offset + i, dstBuf, j); + if (retval != NVS_STATUS_SUCCESS) { + break; + } + j = 0; + } + if (preFlag) { + bad = srcBuf[i] != (srcBuf[i] & dstBuf[j]); + } + else { + bad = srcBuf[i] != dstBuf[j]; + } + if (bad) return (NVS_STATUS_INV_WRITE); + } + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== checkEraseRange ======== + */ +static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size) +{ + NVSSPI25X_Object *object; + NVSSPI25X_HWAttrs const *hwAttrs; + + object = handle->object; + hwAttrs = handle->hwAttrs; + + if (offset != (offset & object->sectorBaseMask)) { + return (NVS_STATUS_INV_ALIGNMENT); /* Poorly aligned start address */ + } + + if (offset >= hwAttrs->regionSize) { + return (NVS_STATUS_INV_OFFSET); /* Offset is past end of region */ + } + + if (offset + size > hwAttrs->regionSize) { + return (NVS_STATUS_INV_SIZE); /* Size is too big */ + } + + if (size != (size & object->sectorBaseMask)) { + return (NVS_STATUS_INV_SIZE); /* Size is not a multiple of sector size */ + } + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== doErase ======== + */ +static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size) +{ + NVSSPI25X_HWAttrs const *hwAttrs; + NVSSPI25X_Object *object; + uint32_t sectorBase; + size_t eraseSize; + int_fast16_t rangeStatus; + uint8_t wbuf[4]; + + /* Sanity test the erase args */ + rangeStatus = checkEraseRange(handle, offset, size); + + if (rangeStatus != NVS_STATUS_SUCCESS) { + return (rangeStatus); + } + + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Set protected global variables */ + spiHandle = object->spiHandle; + spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; + + /* Start erase at this address */ + sectorBase = (uint32_t)hwAttrs->regionBaseOffset + offset; + + while (size) { + /* Wait till previous erase/program operation completes */ + int ret = extFlashWaitReady(handle); + if (ret) { + return (NVS_STATUS_ERROR); + } + + ret = extFlashWriteEnable(handle); + if (ret) { + return (NVS_STATUS_ERROR); + } + + + /* Determine which erase command to use */ + if (size >= SPIFLASH_SECTOR_SIZE && + ((sectorBase & (SPIFLASH_SECTOR_SIZE - 1)) == 0)){ + /* Erase size is one sector (64kB) */ + eraseSize = SPIFLASH_SECTOR_SIZE; + wbuf[0] = SPIFLASH_SECTOR_ERASE; + } + else{ + /* Erase size is one sub-sector (4kB)*/ + eraseSize = hwAttrs->sectorSize; + wbuf[0] = SPIFLASH_SUBSECTOR_ERASE; + } + + + /* Format command to send over SPI */ + wbuf[1] = (sectorBase >> 16) & 0xff; + wbuf[2] = (sectorBase >> 8) & 0xff; + wbuf[3] = sectorBase & 0xff; + + /* Send erase command to external flash */ + NVSSPI25X_assertSpiCs(handle, spiCsnGpioIndex); + if (extFlashSpiWrite(wbuf, sizeof(wbuf))) { + NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); + return (NVS_STATUS_ERROR); + } + NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); + + sectorBase += eraseSize; + size -= eraseSize; + } + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== doRead ======= + */ +static int_fast16_t doRead(NVS_Handle handle, size_t offset, void *buffer, + size_t bufferSize) +{ + NVSSPI25X_Object *object; + NVSSPI25X_HWAttrs const *hwAttrs; + size_t loffset; + uint8_t wbuf[4]; + int retval = NVS_STATUS_SUCCESS; + + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Set protected global variables */ + spiHandle = object->spiHandle; + spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; + + loffset = offset + hwAttrs->regionBaseOffset; + + /* Wait till previous erase/program operation completes */ + retval = extFlashWaitReady(handle); + if (retval) { + return (retval); + } + + /* + * SPI is driven with very low frequency (1MHz < 33MHz fR spec) + * in this temporary implementation. + * and hence it is not necessary to use fast read. + */ + wbuf[0] = SPIFLASH_READ; + wbuf[1] = (loffset >> 16) & 0xff; + wbuf[2] = (loffset >> 8) & 0xff; + wbuf[3] = loffset & 0xff; + + NVSSPI25X_assertSpiCs(handle, spiCsnGpioIndex); + + if (extFlashSpiWrite(wbuf, sizeof(wbuf))) { + NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); + return (NVS_STATUS_ERROR); + } + + retval = extFlashSpiRead(buffer, bufferSize); + + NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); + + return (retval); +} + +/* + * ======== extFlashPowerDown ======= + * Issue power down command + */ +static int_fast16_t extFlashPowerDown(NVS_Handle nvsHandle) +{ + uint8_t cmd; + int_fast16_t status; + + cmd = SPIFLASH_DP; + NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); + status = extFlashSpiWrite(&cmd,sizeof(cmd)); + NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); + + return (status); +} + +/* + * ======== extFlashPowerStandby ======= + * Issue standby command + */ +static int_fast16_t extFlashPowerStandby(NVS_Handle nvsHandle) +{ + uint8_t cmd; + int_fast16_t status; + + cmd = SPIFLASH_RDP; + NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); + status = extFlashSpiWrite(&cmd, sizeof(cmd)); + NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); + + if (status == NVS_STATUS_SUCCESS) { + status = extFlashWaitReady(nvsHandle); + } + + return (status); +} + +/* + * ======== extFlashMassErase ======= + * Issue mass erase command + */ +static int_fast16_t extFlashMassErase(NVS_Handle nvsHandle) +{ + uint8_t cmd; + int_fast16_t status; + + /* Wait for previous operation to complete */ + if (extFlashWaitReady(nvsHandle)) { + return (NVS_STATUS_ERROR); + } + + cmd = SPIFLASH_MASS_ERASE; + NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); + status = extFlashSpiWrite(&cmd,sizeof(cmd)); + NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); + + if (status != NVS_STATUS_SUCCESS) { + return (status); + } + + /* Wait for mass erase to complete */ + return (extFlashWaitReady(nvsHandle)); +} + +/* + * ======== extFlashWaitReady ======= + * Wait for any previous job to complete. + */ +static int_fast16_t extFlashWaitReady(NVS_Handle nvsHandle) +{ + const uint8_t wbuf[1] = { SPIFLASH_READ_STATUS }; + int_fast16_t ret; + uint8_t buf; + + NVSSPI25X_HWAttrs const *hwAttrs; + hwAttrs = nvsHandle->hwAttrs; + + for (;;) { + NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); + extFlashSpiWrite(wbuf, sizeof(wbuf)); + ret = extFlashSpiRead(&buf,sizeof(buf)); + NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); + + if (ret != NVS_STATUS_SUCCESS) { + /* Error */ + return (ret); + } + if (!(buf & SPIFLASH_STATUS_BIT_BUSY)) { + /* Now ready */ + break; + } + if (hwAttrs->statusPollDelayUs){ + /* Sleep to avoid excessive polling and starvation */ + ClockP_usleep(hwAttrs->statusPollDelayUs); + } + } + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== extFlashWriteEnable ======= + * Issue SPIFLASH_WRITE_ENABLE command + */ +static int_fast16_t extFlashWriteEnable(NVS_Handle nvsHandle) +{ + const uint8_t wbuf[] = { SPIFLASH_WRITE_ENABLE }; + int_fast16_t ret; + + NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); + ret = extFlashSpiWrite(wbuf,sizeof(wbuf)); + NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); + + return (ret); +} + +/* + * ======== extFlashSpiWrite ======= + */ +static int_fast16_t extFlashSpiWrite(const uint8_t *buf, size_t len) +{ + SPI_Transaction masterTransaction; + + masterTransaction.rxBuf = NULL; + + /* + * Work around SPI transfer from address 0x0 + * transfer first byte from local buffer + */ + if (buf == NULL) { + uint8_t byte0; + byte0 = *buf++; + masterTransaction.count = 1; + masterTransaction.txBuf = (void*)&byte0; + if (!SPI_transfer(spiHandle, &masterTransaction)) { + return (NVS_STATUS_ERROR); + } + len = len - 1; + if (len == 0) { + return (NVS_STATUS_SUCCESS); + } + } + + masterTransaction.count = len; + masterTransaction.txBuf = (void*)buf; + + return (SPI_transfer(spiHandle, &masterTransaction) ? NVS_STATUS_SUCCESS : NVS_STATUS_ERROR); +} + + +/* + * ======== extFlashSpiRead ======= + */ +static int_fast16_t extFlashSpiRead(uint8_t *buf, size_t len) +{ + SPI_Transaction masterTransaction; + + masterTransaction.txBuf = NULL; + masterTransaction.count = len; + masterTransaction.rxBuf = buf; + + return (SPI_transfer(spiHandle, &masterTransaction) ? NVS_STATUS_SUCCESS : NVS_STATUS_ERROR); +} + +/* + * Below are the default (weak) GPIO-driver based implementations of: + * NVSSPI25X_initSpiCs() + * NVSSPI25X_deinitSpiCs() + * NVSSPI25X_assertSpiCs() + * NVSSPI25X_deassertSpiCs() + */ + +/* + * ======== NVSSPI25X_initSpiCs ======= + */ +#if defined(__IAR_SYSTEMS_ICC__) +__weak void NVSSPI25X_initSpiCs(NVS_Handle nvsHandle, uint16_t csId) +#elif defined(__GNUC__) && !defined(__ti__) +void __attribute__((weak)) NVSSPI25X_initSpiCs(NVS_Handle nvsHandle, uint16_t csId) +#else +#pragma WEAK (NVSSPI25X_initSpiCs) +void NVSSPI25X_initSpiCs(NVS_Handle nvsHandle, uint16_t csId) +#endif +{ + if (csId != NVSSPI25X_SPI_MANAGES_CS) { + GPIO_init(); + + /* + * Make SPI Chip Select GPIO an output, and set it high. + * Since the same device may be used for multiple regions, configuring + * the same Chip Select pin may be done multiple times. No harm done. + */ + GPIO_setConfig(csId, GPIO_CFG_OUT_STD | GPIO_CFG_OUT_HIGH); + } +} + +/* + * ======== NVSSPI25X_deinitSpiCs ======= + */ +#if defined(__IAR_SYSTEMS_ICC__) +__weak void NVSSPI25X_deinitSpiCs(NVS_Handle nvsHandle, uint16_t csId) +#elif defined(__GNUC__) && !defined(__ti__) +void __attribute__((weak)) NVSSPI25X_deinitSpiCs(NVS_Handle nvsHandle, uint16_t csId) +#else +#pragma WEAK (NVSSPI25X_deinitSpiCs) +void NVSSPI25X_deinitSpiCs(NVS_Handle nvsHandle, uint16_t csId) +#endif +{ +} + +/* + * ======== NVSSPI25X_assertSpiCs ======= + * Assert SPI flash /CS + */ +#if defined(__IAR_SYSTEMS_ICC__) +__weak void NVSSPI25X_assertSpiCs(NVS_Handle nvsHandle, uint16_t csId) +#elif defined(__GNUC__) && !defined(__ti__) +void __attribute__((weak)) NVSSPI25X_assertSpiCs(NVS_Handle nvsHandle, uint16_t csId) +#else +#pragma WEAK (NVSSPI25X_assertSpiCs) +void NVSSPI25X_assertSpiCs(NVS_Handle nvsHandle, uint16_t csId) +#endif +{ + if (csId != NVSSPI25X_SPI_MANAGES_CS) { + GPIO_write(csId, 0); + } +} + +/* + * ======== NVSSPI25X_deassertSpiCs ======= + * De-assert SPI flash /CS + */ +#if defined(__IAR_SYSTEMS_ICC__) +__weak void NVSSPI25X_deassertSpiCs(NVS_Handle nvsHandle, uint16_t csId) +#elif defined(__GNUC__) && !defined(__ti__) +void __attribute__((weak)) NVSSPI25X_deassertSpiCs(NVS_Handle nvsHandle, uint16_t csId) +#else +#pragma WEAK (NVSSPI25X_deassertSpiCs) +void NVSSPI25X_deassertSpiCs(NVS_Handle nvsHandle, uint16_t csId) +#endif +{ + if (csId != NVSSPI25X_SPI_MANAGES_CS) { + GPIO_write(csId, 1); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSSPI25X.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSSPI25X.h new file mode 100644 index 0000000..219e167 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSSPI25X.h @@ -0,0 +1,369 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!***************************************************************************** + * @file NVSSPI25X.h + * @brief Non-Volatile Storage driver implementation + * for SPI flash peripherals + * + * # Overview # + * + * The NVSSPI25X module allows you to manage SPI flash memory. + * This driver works with most 256 byte/page SPI flash memory devices + * such as: + * + * Winbond W25xx family + * Macronics MX25Rxx family + * Micron N25Qxx family + * + * The SPI flash commands used by this driver are as follows: + * + * @code + * #define SPIFLASH_PAGE_WRITE 0x02 // Page Program (up to 256 bytes) + * #define SPIFLASH_READ 0x03 // Read Data + * #define SPIFLASH_READ_STATUS 0x05 // Read Status Register + * #define SPIFLASH_WRITE_ENABLE 0x06 // Write Enable + * #define SPIFLASH_SUBSECTOR_ERASE 0x20 // SubSector (4K bytes) Erase + * #define SPIFLASH_SECTOR_ERASE 0xD8 // Sector (usually 64K bytes) Erase + * #define SPIFLASH_RDP 0xAB // Release from Deep Power Down + * #define SPIFLASH_DP 0xB9 // Deep Power Down + * #define SPIFLASH_MASS_ERASE 0xC7 // Erase entire flash. + * @endcode + * + * It is assumed that the SPI flash device used by this driver supports + * the byte programmability of the SPIFLASH_PAGE_WRITE command and that + * write page size is 256 bytes. The erase sector and subsector sizes are + * assumed to be 64K and 4K respectively. + * + * The NVS_erase() command will issue a sector or subsector erase command + * based on the input size and offset. + * + * The driver must query the SPI flash to ensure that the part is ready before + * commands are issued. If the part responds as busy, the poll function sleeps + * for a number of microseconds determined by the + * #NVSSPI25X_HWAttrs.statusPollDelayUs field. A value of 0 means that the + * driver will continuously poll the external flash until it is ready, which + * may affect other threads ability to execute. + * + * ## SPI Interface Management ## + * + * For each managed flash region, a corresponding SPI instance must be + * provided to the NVSSPI25X driver. + * + * The SPI instance can be opened and closed + * internally by the NVSSPI25X driver, or alternatively, a SPI handle can be + * provided to the NVSSPI25X driver, indicating that the SPI instance is being + * opened and closed elsewhere within the application. This mode is useful + * when the SPI bus is share by more than just the SPI flash device. + * + * If the SPI instance is to be managed internally by the NVSSPI25X driver, a SPI + * instance index and bit rate must be configured in the region's HWAttrs. + * If the same SPI instance is referenced by multiple flash regions + * the driver will ensure that SPI_open() is invoked only once, and that + * SPI_close() will only be invoked when all flash regions using the SPI + * instance have been closed. + * + * If the SPI bus that the SPI flash device is on is shared with other + * devices accessed by an application, then the SPI handle used to manage + * a SPI flash region can be provided in the region's HWAttrs "spiHandle" + * field. Keep in mind that the "spiHandle" field is a POINTER to a + * SPI Handle, NOT a SPI Handle. This allows the user to simply initialize + * this field with the name of the global variable used for the SPI handle. + * In this mode, the user MUST open the SPI instance prior to opening the NVS + * region instance so that the referenced spiHandle is valid. + * + * By default, the "spiHandle" field is set to NULL, indicating that the user + * expects the NVS driver to open and close the SPI instance internally using + * the 'spiIndex' and 'spiBitRate' provided in the HWAttrs. + * + * ## @anchor SPI_CS_MGMT SPI Flash Chip Select Management ## + * + * ### Option 1: NVSSPI25X Driver Manages Chip Select ### + * By default, the NVSSPI25X driver will assert and de-assert a GPIO + * driver managed pin to select the SPI flash device before and after + * each SPI transfer to and from the device. + * + * To enable this behavior, a valid GPIO driver instance index must be + * provided in the NVS region's [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) field of the + * NVSSPI25X_HWAttrs structure. The corresponding GPIO pin will be + * configured at runtime by the NVSSPI25X driver as "GPIO_CFG_OUT_STD" + * and assertion of this pin is assumed to be active LOW. + * + * ### Option 2: SPI Driver Manages Chip Select ### + * Some SPI peripherals can be configured to manage their own chip + * select. Setting the [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) field of the NVSSPI25X_HWAttrs + * structure to #NVSSPI25X_SPI_MANAGES_CS informs the NVSSPI25X driver + * that the SPI peripheral used by the NVS driver has been configured + * that way. + * + * ### Option 3: User Manages Chip Select ### + * Alternatively, the user can manage the assertion and de-assertion of + * the SPI flash chip select entirely themselves by providing implementations + * of the following 4 APIs in their application code: + * + * @code + * void NVSSPI25X_initSpiCs(NVS_Handle nvsHandle, uint16_t csId); + * @endcode + * - This function is invoked within the NVS_open() API and is where the + * user should do whatever is required to initialize the hardware + * used for asserting and de-assering the SPI chip select signal. + * - The 'nvsHandle` argument is the NVS handle associated with the + * corresponding NVS region. + * - The 'csId' argument passed to this API is a copy of the [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) + * field of the corresponding NVS region's NVSSPI25X_HWAttrs structure. + * + * @code + * void NVSSPI25X_deinitSpiCs(NVS_Handle nvsHandle, uint16_t csId); + * @endcode + * - This function is invoked within the NVS_close() API and is where the + * user should do whatever is required to de-initialize the hardware + * used for asserting and de-assering the SPI chip select signal. + * - The 'nvsHandle` argument is the NVS handle associated with the + * corresponding NVS region. + * - The 'csId' argument passed to this API is a copy of the [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) + * field of the corresponding NVS region's NVSSPI25X_HWAttrs structure. + * + * @code + * void NVSSPI25X_assertSpiCs(NVS_Handle nvsHandle, uint16_t csId); + * @endcode + * - This function is called PRIOR to every SPI transfer to and from the SPI + * flash device performed by the NVSSPI25X driver. The user code should + * perform the corresponding action required to select the SPI flash + * device to prepare for the SPI transfer. + * - The 'nvsHandle` argument is the NVS handle associated with the + * corresponding NVS region. + * - The 'csId' argument passed to this API is a copy of the [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) + * field of the corresponding NVS region's NVSSPI25X_HWAttrs structure. + * + * @code + * void NVSSPI25X_deassertSpiCs(NVS_Handle nvsHandle, uint16_t csId); + * @endcode + * - This function is called AFTER every SPI transfer to and from the SPI + * flash device performed by the NVSSPI25X driver. The user code should + * perform the corresponding action required to de-select the SPI flash + * device. + * following the SPI transfer. + * - The 'nvsHandle` argument is the NVS handle associated with the + * corresponding NVS region. + * - The 'csId' argument passed to this API is a copy of the [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) + * field of the corresponding NVS region's NVSSPI25X_HWAttrs structure. + * + * @warning All 4 of the above APIs must be provided by the user if this + * option is used, otherwise default internal implementations of the APIs + * will be called that will likely lead to application failure. + */ + +#ifndef ti_drivers_nvs_NVSSPI25X__include +#define ti_drivers_nvs_NVSSPI25X__include + +#include +#include + +#include + +#if defined (__cplusplus) +extern "C" { +#endif + +/*! + * @brief Command to perform mass erase of entire flash + * + * As this command can erase flash memory outside the region associated + * with the NVS_Handle passed to the control command, the user must + * carefully orchestrate the use of the command. + * + * Mass Erase is the only control command supported. + */ +#define NVSSPI25X_CMD_MASS_ERASE (NVS_CMD_RESERVED + 0) + +/*! + * @brief Disable internal management of SPI chip select + * + * Some SPI peripherals can be configured to manage their own chip + * select. Setting the [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) field of the NVSSPI25X_HWAttrs + * structure to #NVSSPI25X_SPI_MANAGES_CS informs the NVSSPI25X driver + * that the SPI peripheral used by the NVS driver is configured + * to manage its own chip select signal. + */ +#define NVSSPI25X_SPI_MANAGES_CS ((uint16_t)(~0)) + +/*! + * @internal @brief NVS function pointer table + * + * 'NVSSPI25X_fxnTable' is a fully populated function pointer table + * that can be referenced in the NVS_config[] array entries. + * + * Users can minimize their application code size by providing their + * own custom NVS function pointer table that contains only those APIs + * used by the application. + */ +extern const NVS_FxnTable NVSSPI25X_fxnTable; + +/*! + * @brief NVSSPI25X attributes + * + * The 'regionBaseOffset' is the offset, in bytes, from the base of the + * SPI flash, of the flash region to be managed. + * + * The 'regionSize' must be an integer multiple of the flash sector size. + * + * The 'sectorSize' is SPI flash device specific. This parameter should + * correspond to the number of bytes erased when the + * 'SPIFLASH_SUBSECTOR_ERASE' (0x20) command is issued to the device. + * + * The 'verifyBuf' and 'verifyBufSize' parameters are used by the + * NVS_write() command when either 'NVS_WRITE_PRE_VERIFY' or + * 'NVS_WRITE_POST_VERIFY' functions are requested in the 'flags' + * argument. The 'verifyBuf' is used to successively read back portions + * of the flash to compare with the data being written to it. + * + * @code + * // + * // Only one region write operation is performed at a time + * // so a single verifyBuf can be shared by all the regions. + * // + * uint8_t verifyBuf[256]; + * + * NVSSPI25X_HWAttrs nvsSPIHWAttrs[2] = { + * // + * // region 0 is 1 flash sector in length. + * // + * { + * .regionBaseOffset = 0, + * .regionSize = 4096, + * .sectorSize = 4096, + * .verifyBuf = verifyBuf; + * .verifyBufSize = 256; + * .spiHandle = NULL, + * .spiIndex = 0, + * .spiBitRate = 40000000, + * .spiCsnGpioIndex = 12, + * }, + * // + * // region 1 is 3 flash sectors in length. + * // + * { + * .regionBaseOffset = 4096, + * .regionSize = 4096 * 3, + * .sectorSize = 4096, + * .verifyBuf = verifyBuf; // use shared verifyBuf + * .verifyBufSize = 256; + * .spiHandle = NULL, + * .spiIndex = 0, + * .spiBitRate = 40000000, + * .spiCsnGpioIndex = 12, + * } + * }; + * @endcode + */ +typedef struct +{ + size_t regionBaseOffset; /*!< Offset from base of SPI flash */ + size_t regionSize; /*!< The size of the region in bytes */ + size_t sectorSize; /*!< Erase sector size */ + uint8_t *verifyBuf; /*!< Write Pre/Post verify buffer */ + size_t verifyBufSize; /*!< Write Pre/Post verify buffer size */ + SPI_Handle *spiHandle; /*!< ptr to SPI handle if provided by user. */ + uint16_t spiIndex; /*!< SPI instance index from Board file */ + uint32_t spiBitRate; /*!< SPI bit rate in Hz */ + /*! @brief SPI Flash Chip Select GPIO index + + This field should be set to either an index within the + GPIO driver's GPIO_Config table, or to #NVSSPI25X_SPI_MANAGES_CS. + see [SPI Flash Chip Select Management] (@ref SPI_CS_MGMT) for more + details. + */ + uint16_t spiCsnGpioIndex; + /*! @brief External Flash Status Poll Delay + * + * This field determines how many microseconds the driver waits after + * querying the external flash status. Increasing this value can help + * mitigate CPU starvation if the external flash is busy for long periods + * of time, but may also result in increased latency. + */ + uint32_t statusPollDelayUs; +} NVSSPI25X_HWAttrs; + +/* + * @brief NVSSPI25X Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + bool opened; /* Has this region been opened */ + SPI_Handle spiHandle; + size_t sectorBaseMask; +} NVSSPI25X_Object; + +/* + * @cond NODOC + * NVSSPI25X driver public APIs + */ + +extern void NVSSPI25X_close(NVS_Handle handle); +extern int_fast16_t NVSSPI25X_control(NVS_Handle handle, uint_fast16_t cmd, + uintptr_t arg); +extern int_fast16_t NVSSPI25X_erase(NVS_Handle handle, size_t offset, + size_t size); +extern void NVSSPI25X_getAttrs(NVS_Handle handle, NVS_Attrs *attrs); +extern void NVSSPI25X_init(); +extern int_fast16_t NVSSPI25X_lock(NVS_Handle handle, uint32_t timeout); +extern NVS_Handle NVSSPI25X_open(uint_least8_t index, NVS_Params *params); +extern int_fast16_t NVSSPI25X_read(NVS_Handle handle, size_t offset, + void *buffer, size_t bufferSize); +extern void NVSSPI25X_unlock(NVS_Handle handle); +extern int_fast16_t NVSSPI25X_write(NVS_Handle handle, size_t offset, + void *buffer, size_t bufferSize, uint_fast16_t flags); +/* + * Weakly defined APIs that can be overridden by the user + */ +extern void NVSSPI25X_initSpiCs(NVS_Handle spiHandle, uint16_t csId); +extern void NVSSPI25X_deinitSpiCs(NVS_Handle spiHandle, uint16_t csId); +extern void NVSSPI25X_assertSpiCs(NVS_Handle spiHandle, uint16_t csId); +extern void NVSSPI25X_deassertSpiCs(NVS_Handle spiHandle, uint16_t csId); + +/*! @endcond */ + +#if defined (__cplusplus) +} +#endif /* defined (__cplusplus) */ + +/** @}*/ +#endif /* ti_drivers_nvs_NVSSPI25X__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pin/PINCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pin/PINCC26XX.c new file mode 100644 index 0000000..4763f51 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pin/PINCC26XX.c @@ -0,0 +1,684 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_aon_event.h) +#include DeviceFamily_constructPath(inc/hw_aon_ioc.h) +#include DeviceFamily_constructPath(inc/hw_gpio.h) +#include DeviceFamily_constructPath(inc/hw_ioc.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_ccfg.h) +#include DeviceFamily_constructPath(driverlib/driverlib_release.h) +#include DeviceFamily_constructPath(driverlib/chipinfo.h) + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) + #include DeviceFamily_constructPath(inc/hw_aon_sysctl.h) +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) + #include DeviceFamily_constructPath(inc/hw_aon_pmctl.h) +#endif + +/*!***************************************************************************** + * @file PINCC26XX.c + * @brief Device-specific PIN & GPIO driver for CC26xx family [impl] + * + * # Overview # + * This is the device-specific implementation of the generic PIN driver for the + * CC26xx family of devices. + * + ******************************************************************************* + */ + +// Maximum number of pins (# available depends on package configuration) +#define MAX_NUM_PINS 31 + +/// Last DIO number available on package + device combination +uint32_t pinUpperBound = 0; + +/// First DIO number available on package + device combination +uint32_t pinLowerBound = 0; + +/// Array of handles, one per pin (pin id is index) +PIN_Handle pinHandleTable[MAX_NUM_PINS]; + +/// Pointer to GPIO configuration set by PIN_init(...), save state in order to revert when PIN_close(...) +static const PIN_Config *defaultPinConfig; + +/// Array of indexes into GPIO configuration defaultPinConfig, one per pin (pin id is index) +static uint8_t pinGpioConfigTable[MAX_NUM_PINS]; + +/// HW interrupt structure for I/O interrupt handler +static HwiP_Struct pinHwi; + +/// SWI structure for the followup of the I/O interrupt handler +static SwiP_Struct pinSwi; + +/// PIN driver semaphore used to implement synchronicity for PIN_open() +static SemaphoreP_Struct pinSemaphore; + +/// Hardware attribute structure populated in board.c to set HWI and SWI priorities +extern const PINCC26XX_HWAttrs PINCC26XX_hwAttrs; + +// I/O SWI service routine that posts the callback in a SWI context +static void PIN_swi(uintptr_t arg0, uintptr_t arg1){ + + uint32_t eventMask; + unsigned char eventCounter; + PIN_Handle handle; + PIN_IntCb callbackFxn; + + // Get the OR'd trigger value representing all events values prior to running the SWI + eventMask = SwiP_getTrigger(); + + // eventCounter cycles through all pins on the device up to the max number of pins + for(eventCounter = 0; eventCounter <= pinUpperBound; eventCounter++){ + // Check if current eventCounter bit is set in eventMask + if(eventMask & (1 << eventCounter)){ + // Get pin handle and registered callback function + // Double paranthesis to supress GCC warning + // Intentional assignment is intended, not the equality comparison + if((handle = pinHandleTable[eventCounter])) { + if((callbackFxn = handle->callbackFxn)) { + // Event from existing pin, with an associated handle and a + // registered callback -> call callback + // Run the callback function in a SWI context. + callbackFxn(handle, eventCounter); + } + } + } + } +} + +// I/O HWI service routine +static void PIN_hwi(uintptr_t arg) { + uint32_t eventMask; + + // Get event flag with lowest index (also pin ID) + eventMask = HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0); + + // Clear this event flag + HWREG(GPIO_NONBUF_BASE + GPIO_O_EVFLAGS31_0) = eventMask; + + // Include all GPIO's currently triggered in the SWI + SwiP_or(&(pinSwi), eventMask); +} + +// Internal utility function for setting IOCFG register for pin +static void PINCC26XX_setIoCfg(PIN_Config updateMask, PIN_Config pinCfg) { + uint32_t tmpConfig; + PIN_Id pinId = PIN_ID(pinCfg); + bool invertChanges; + + if (pinCfg & PIN_GEN) { + // Translate from device-independent to device-specific PIN_Config values + pinCfg ^= PIN_GEN | PIN_BM_INPUT_EN | PIN_BM_PULLING; + } + // Get existing IOCFG, determine whether inversion changes, mask away what will be updated + tmpConfig = HWREG(IOC_BASE + IOC_O_IOCFG0 + 4 * pinId); + invertChanges = (tmpConfig ^ pinCfg) & updateMask & PINCC26XX_INV_INOUT; + tmpConfig &= ~updateMask; + + // Insert what we want to update, possibly revert IRQ edges, write back to IOCFG + tmpConfig |= (pinCfg & updateMask & PINCC26XX_BM_IOCFG); + if ((updateMask & PINCC26XX_BM_IRQ) == PINCC26XX_BM_IRQ && (tmpConfig & PINCC26XX_INV_INOUT) == 0) { + // We're changing IRQ options but inversion will not be enabled -> keep IRQ options + } else if ((updateMask & PINCC26XX_BM_IRQ) == 0 && !invertChanges) { + // We're not changing IRQ options and inversion remains unchanged -> keep IRQ options + } else { + // We're updating IRQ options and inversion will be enabled, OR + // we're not updating IRQ options but inversion settings change + // -> reverse polarity of edge detection when positive-only or negative-only + switch (tmpConfig & PINCC26XX_BM_IRQ) { + case PINCC26XX_IRQ_POSEDGE: + tmpConfig &= ~PINCC26XX_BM_IRQ; + tmpConfig |= PINCC26XX_IRQ_NEGEDGE; + break; + case PINCC26XX_IRQ_NEGEDGE: + tmpConfig &= ~PINCC26XX_BM_IRQ; + tmpConfig |= PINCC26XX_IRQ_POSEDGE; + break; + default: + break; + } + } + + /* Clear any pending events from the previous pin configuration before we write the new interrupt settings */ + PINCC26XX_clrPendInterrupt(pinId); + HWREG(IOC_BASE + IOC_O_IOCFG0 + 4 * pinId) = tmpConfig; + + // Update GPIO output value and enable depending on previous output mode (enabled or disabled) + { + bool outputEnabled = (HWREG(GPIO_BASE + GPIO_O_DOE31_0) & (1 << pinId)) ? true : false; + + if(!outputEnabled) { + if (updateMask & PINCC26XX_BM_GPIO_OUTPUT_VAL) { + // Set GPIO output value + HWREGB(GPIO_BASE + GPIO_O_DOUT3_0 + pinId) = (pinCfg & PINCC26XX_BM_GPIO_OUTPUT_VAL) ? 1 : 0; + } + } + + if (updateMask & PINCC26XX_BM_GPIO_OUTPUT_EN) { + // Set GPIO output enable + uint32_t key = HwiP_disable(); + HWREG(GPIO_BASE + GPIO_O_DOE31_0) = + (HWREG(GPIO_BASE + GPIO_O_DOE31_0) & ~(1 << pinId)) | + ((pinCfg&PINCC26XX_BM_GPIO_OUTPUT_EN) ? (1 << pinId) : 0); + HwiP_restore(key); + } + + if(outputEnabled) { + if (updateMask & PINCC26XX_BM_GPIO_OUTPUT_VAL) { + // Set GPIO output value + HWREGB(GPIO_BASE + GPIO_O_DOUT3_0 + pinId) = (pinCfg & PINCC26XX_BM_GPIO_OUTPUT_VAL) ? 1 : 0; + } + } + } + + /* Clear any events from pin value changes as a result of the new configuration */ + PINCC26XX_clrPendInterrupt(pinId); +} + + + +// Internal utility function for setting mux setting in IOCFG register for pin +static void PINCC26XX_setIoCfgMux(PIN_Id pinId, int32_t mux) { + // Read in existing value in IOCFG register and update with supplied mux value + if (mux < 0) { + mux = PINCC26XX_MUX_GPIO; + } + uint32_t tmpConfig; + tmpConfig = HWREG(IOC_BASE + IOC_O_IOCFG0 + 4 * pinId); + tmpConfig &= ~IOC_IOCFG0_PORT_ID_M; + tmpConfig |= mux & IOC_IOCFG0_PORT_ID_M; + HWREG(IOC_BASE + IOC_O_IOCFG0 + 4 * pinId) = tmpConfig; +} + +uint32_t PINCC26XX_getPinCount(){ + // Get number of pins available on device (from HW register) + uint32_t pinCount = (( HWREG( FCFG1_BASE + FCFG1_O_IOCONF ) & + FCFG1_IOCONF_GPIO_CNT_M ) >> + FCFG1_IOCONF_GPIO_CNT_S ) ; + + return pinCount; +} + +PIN_Status PIN_init(const PIN_Config pinConfig[]) { + uint32_t i; + uint32_t pinConfigMask = 0; // Works as long as # pins <=32 + HwiP_Params hwiParams; + SwiP_Params swiParams; + uint32_t reservedPinMask = 0; + + // Its ok if Power init has already been called. + Power_init(); + + // Make sure we are using correct version of Driverlib + DRIVERLIB_ASSERT_CURR_RELEASE(); + + /* pinLowerBound is initialized to 0 by default. + * All cases where this is not the case are handled here. + */ + switch (ChipInfo_GetChipType()) { + case CHIP_TYPE_CC1310: + case CHIP_TYPE_CC1350: + case CHIP_TYPE_CC1312: + if (ChipInfo_GetPackageType() == PACKAGE_7x7) { + pinLowerBound = 1; + reservedPinMask |= 0x01; + } + break; + case CHIP_TYPE_CC1352: + pinLowerBound = 3; + reservedPinMask |= 0x07; + break; + case CHIP_TYPE_CC1352P: + pinLowerBound = 5; + reservedPinMask |= 0x1F; + break; + } + + if ((HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & CCFG_MODE_CONF_SCLK_LF_OPTION_M) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S == 0x1) { + // An IO is used for LF clock input + reservedPinMask |= (1 << ((HWREG(CCFG_BASE+CCFG_O_EXT_LF_CLK) & CCFG_EXT_LF_CLK_DIO_M) >> CCFG_EXT_LF_CLK_DIO_S)); + } + + // Get the last addressable DIO number + pinUpperBound = pinLowerBound + PINCC26XX_getPinCount() - 1; + + // Initialize table of pins that have default GPIO configuration + for (i = 0; i <= pinUpperBound; i++) { + pinGpioConfigTable[i] = PIN_UNASSIGNED; + } + + + // Read in pinConfig list and create bitmask of which IOs to initialize to + // default values and which to initialize from pinConfig + for (i = 0, pinConfigMask = 0; PIN_ID(pinConfig[i]) != PIN_TERMINATE; i++) { + // Ignore unassigned pins + if (PIN_ID(pinConfig[i]) == PIN_UNASSIGNED) { + continue; + } + // Check that pin exists and is available + if (PIN_ID(pinConfig[i]) > pinUpperBound || PIN_ID(pinConfig[i]) < pinLowerBound || reservedPinMask & (1 << PIN_ID(pinConfig[i]))) { + return PIN_NO_ACCESS; + } + // Mark pin as being in pinConfig + pinConfigMask |= (1 << PIN_ID(pinConfig[i])); + // For quick reference, store index i in table + pinGpioConfigTable[PIN_ID(pinConfig[i])] = i; + } + + // Set Power dependecies & constraints + Power_setDependency(PowerCC26XX_PERIPH_GPIO); + + // Save GPIO default setup + defaultPinConfig = pinConfig; + + // Setup semaphore for sequencing accesses to PIN_open() + SemaphoreP_constructBinary(&pinSemaphore, 1); + + // Loop thru all pins and configure + for (i = 0; i <= pinUpperBound; i++) { + if (reservedPinMask & (1 << i)) { + // Pin is reserved for other purposes -> setup dummy handle + pinHandleTable[i] = (PIN_State*)0x00000004; + } + else { + if (pinConfigMask & (1 << i)) { + // Setup all pins in pinConfig as instructed + PINCC26XX_setIoCfg(PIN_BM_ALL, pinConfig[pinGpioConfigTable[i]]); + } + else { + // Setup all pins not in pinConfig to default configuration: + // GPIO, input buffer disable, GPIO output disable, low GPIO output, no pull, no IRQ, no wakeup + PINCC26XX_setIoCfg(PIN_BM_ALL, PIN_ID(i) | PINCC26XX_NOPULL); + } + // Set pin as GPIO and clear pin handle + PINCC26XX_setIoCfgMux(PIN_ID(i), -1); + pinHandleTable[i] = NULL; + } + } + + // Setup HWI handler + HwiP_Params_init(&hwiParams); + hwiParams.priority = PINCC26XX_hwAttrs.intPriority; + HwiP_construct(&pinHwi, INT_AON_GPIO_EDGE, PIN_hwi, &hwiParams); + + // Setup SWI handler + SwiP_Params_init(&(swiParams)); + swiParams.priority = PINCC26XX_hwAttrs.swiPriority; + swiParams.trigger = 0; + SwiP_construct(&pinSwi, PIN_swi, &(swiParams)); + + // Setup interrupts so that they wake up from standby (use MCU_WU1) + HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) = + (HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) & (~AON_EVENT_MCUWUSEL_WU1_EV_M)) | + AON_EVENT_MCUWUSEL_WU1_EV_PAD; + + // Open latches out to I/Os + // This might be unnecessary, but isn't when you start from debugger + HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = AON_IOC_IOCLATCH_EN; + + // If we boot from shutdown, the IOs are latched, this opens the latches again +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) + HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_SLEEPCTL) = AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS; +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL) = AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS; +#endif + + return PIN_SUCCESS; +} + + + +PIN_Handle PIN_open(PIN_State* state, const PIN_Config pinList[]) { + uint32_t i; + bool pinsAllocated = true; + uint32_t portMask = 0; + PIN_Id pinId; + + if ((state == NULL) || (pinList == NULL)) { + return (NULL); + } + + // Ensure that only one client at a time can call PIN_open() or PIN_add() + SemaphoreP_pend(&pinSemaphore, SemaphoreP_WAIT_FOREVER); + + // Check whether all pins in pinList are valid and available first + for (i = 0; (pinId = PIN_ID(pinList[i])) != PIN_TERMINATE; i++) { + /* Unassigned pins is allowed, but cannot generate a bitmask. */ + if (pinId != PIN_UNASSIGNED) { + if ((pinId > pinUpperBound) || + (pinId >= MAX_NUM_PINS) || // For Klocwork + pinHandleTable[pinId]) { + pinsAllocated = false; + break; + } else { + // Generate bitmask for port operations (always one port on CC26xx) + portMask |= (1 << pinId); + } + } + } + + if (!pinsAllocated) { + // Indicate that the pins were not allocatable + state = NULL; + } else { + // Setup state object + state->callbackFxn = NULL; + state->portMask = 0; + state->userArg = 0; + + // Configure I/O pins according to pinList + for (i = 0; (pinId = PIN_ID(pinList[i])) != PIN_TERMINATE; i++) { + // Check pinId < MAX_NUM_PINS for Klocwork + if ((pinId != PIN_UNASSIGNED) && (pinId < MAX_NUM_PINS)) { + pinHandleTable[pinId] = state; + state->portMask |= (1 << pinId); + PIN_setConfig(state, PIN_BM_ALL, pinList[i]); + } + } + } + + SemaphoreP_post(&pinSemaphore); + return state; +} + + + +PIN_Status PIN_add(PIN_Handle handle, PIN_Config pinCfg) { + PIN_Status returnStatus; + PIN_Id pinId = PIN_ID(pinCfg); + + // Check that handle and pinId is valid + if (!handle || (pinId > pinUpperBound) || (pinId >= MAX_NUM_PINS)) { + return PIN_NO_ACCESS; + } + + // Ensure that only one client at a time can call PIN_open() or PIN_add() + SemaphoreP_pend(&pinSemaphore, SemaphoreP_WAIT_FOREVER); + + // Check whether pin is available + if (pinHandleTable[pinId]) { + // Pin already allocated -> do nothing + returnStatus = PIN_ALREADY_ALLOCATED; + } else { + // Allocate pin + pinHandleTable[pinId] = handle; + handle->portMask |= (1 << pinId); + PIN_setConfig(handle, PIN_BM_ALL, pinCfg); + returnStatus = PIN_SUCCESS; + } + + SemaphoreP_post(&pinSemaphore); + return returnStatus; +} + + + +PIN_Status PIN_remove(PIN_Handle handle, PIN_Id pinId) { + if (handle && (handle->portMask & (1 << pinId))) { + // Deallocate pin + handle->portMask &= ~(1 << pinId); + pinHandleTable[pinId] = NULL; + // Find GPIO default value and revert to it + if (pinGpioConfigTable[pinId] == PIN_UNASSIGNED) { + // Revert pin to default configuration: + // GPIO, input buffer disable, GPIO output disable, low GPIO output, no pull, no IRQ, no wakeup + PINCC26XX_setIoCfg(PIN_BM_ALL, PIN_ID(pinId) | PIN_INPUT_DIS); + } else { + // Revert pin to previous GPIO configuration + PINCC26XX_setIoCfg(PIN_BM_ALL, defaultPinConfig[pinGpioConfigTable[pinId]]); + } + // Revert to GPIO + PINCC26XX_setIoCfgMux(PIN_ID(pinId), -1); + return PIN_SUCCESS; + } else { + return PIN_NO_ACCESS; + } +} + + + +void PIN_close(PIN_Handle handle) { + uint32_t i; + + // No need for sequencing accesses to PIN_close() + // For each pin in port bitmask + while (handle->portMask) { + // Find lowest index pin + i = PIN_ctz(handle->portMask); + // Deallocate pin + PIN_remove(handle, i); + } +} + + + +uint32_t PIN_getInputValue(PIN_Id pinId) { + return PINCC26XX_getInputValue(pinId); +} + + + +PIN_Status PIN_setOutputEnable(PIN_Handle handle, PIN_Id pinId, bool outputEnable) { + if (PIN_CHKEN && (pinId > pinUpperBound || pinHandleTable[pinId] != handle)) { + // Non-existing pin or pin is not allocated to this client + return PIN_NO_ACCESS; + } + PINCC26XX_setOutputEnable(pinId, outputEnable); + return PIN_SUCCESS; +} + + + +PIN_Status PIN_setOutputValue(PIN_Handle handle, PIN_Id pinId, uint32_t val) { + if (PIN_CHKEN && (pinId > pinUpperBound || pinHandleTable[pinId] != handle)) { + // Non-existing pin or pin is not allocated to this client + return PIN_NO_ACCESS; + } + PINCC26XX_setOutputValue(pinId, val); + return PIN_SUCCESS; +} + + + +uint32_t PIN_getOutputValue(PIN_Id pinId) { + return PINCC26XX_getOutputValue(pinId); +} + + + +PIN_Status PIN_setInterrupt(PIN_Handle handle, PIN_Config pinCfg) { + if (PIN_CHKEN && ((PIN_ID(pinCfg) > pinUpperBound) || + (PIN_ID(pinCfg) >= MAX_NUM_PINS) || + (pinHandleTable[PIN_ID(pinCfg)] != handle))) { + // Non-existing pin or pin is not allocated to this client + return PIN_NO_ACCESS; + } + PIN_setConfig(handle, PIN_BM_IRQ, pinCfg); + return PIN_SUCCESS; +} + + + +PIN_Status PIN_clrPendInterrupt(PIN_Handle handle, PIN_Id pinId) { + if (PIN_CHKEN && ((pinId > pinUpperBound) || + (pinId >= MAX_NUM_PINS) || + (pinHandleTable[pinId] != handle))) { + // Non-existing pin or pin is not allocated to this client + return PIN_NO_ACCESS; + } + PINCC26XX_clrPendInterrupt(pinId); + return PIN_SUCCESS; +} + + + +PIN_Status PIN_registerIntCb(PIN_Handle handle, PIN_IntCb pCb) { + if (handle) { + handle->callbackFxn = pCb; + return PIN_SUCCESS; + } else { + return PIN_NO_ACCESS; + } +} + + + +PIN_Config PIN_getConfig(PIN_Id pinId) { + // Translate from device-specific to device independent PIN_Config values + return PIN_GEN | (PINCC26XX_getConfig(pinId) ^ (PIN_BM_INPUT_EN | PIN_BM_PULLING)); +} + + + +PIN_Status PIN_setConfig(PIN_Handle handle, PIN_Config updateMask, PIN_Config pinCfg) { + if (PIN_CHKEN && (PIN_ID(pinCfg) > pinUpperBound || + (PIN_ID(pinCfg) >= MAX_NUM_PINS) || + (pinHandleTable[PIN_ID(pinCfg)] != handle))) { + // Non-existing pin or pin is not allocated to this client + return PIN_NO_ACCESS; + } + PINCC26XX_setIoCfg(updateMask, pinCfg); + return PIN_SUCCESS; +} + + + +PIN_Config PINCC26XX_getConfig(PIN_Id pinId) { + // Get IOCFG register value and add in some extras: + // * pinId + // * pin GPIO output enable + // * pin GPIO output value + uint32_t tmpConfig; + + tmpConfig = HWREG(IOC_BASE + IOC_O_IOCFG0 + 4 * pinId); + tmpConfig &= PINCC26XX_BM_IOCFG; + tmpConfig |= PIN_ID(pinId); + tmpConfig |= (PINCC26XX_getOutputValue(pinId)) ? PINCC26XX_GPIO_HIGH : PINCC26XX_GPIO_LOW; + tmpConfig |= (HWREG(GPIO_BASE + GPIO_O_DOE31_0) & (1 << pinId)) ? PINCC26XX_GPIO_OUTPUT_EN : 0; + return tmpConfig; +} + + + +int32_t PINCC26XX_getMux(PIN_Id pinId) { + if (PIN_CHKEN && pinId > pinUpperBound) { + // Non-existing pin + return PIN_NO_ACCESS; + } + int32_t tmpConfig; + tmpConfig = HWREG(IOC_BASE + IOC_O_IOCFG0 + 4 * pinId); + tmpConfig &= IOC_IOCFG0_PORT_ID_M; + if (tmpConfig == PINCC26XX_MUX_GPIO) { + tmpConfig = -1; + } + return tmpConfig; +} + + + +PIN_Status PINCC26XX_setMux(PIN_Handle handle, PIN_Id pinId, int32_t mux) { + // Add check for pinId >= MAX_NUM_PINS for Klocwork + if (PIN_CHKEN && ((pinId > pinUpperBound) || + (pinId >= MAX_NUM_PINS) || + (pinHandleTable[pinId] != handle))) { + // Non-existing pin or pin is not allocated to this client + return PIN_NO_ACCESS; + } + PINCC26XX_setIoCfgMux(pinId, mux); + return PIN_SUCCESS; +} + + + +PIN_Status PINCC26XX_setWakeup(const PIN_Config pinConfig[]) { + uint32_t i; + // TODO: is this enough? + + for (i = 0; PIN_ID(pinConfig[i]) != PIN_TERMINATE; i++) { + PINCC26XX_setIoCfg(PINCC26XX_BM_ALL, pinConfig[i]); + } + return PIN_SUCCESS; +} + + + +uint32_t PIN_getPortMask(PIN_Handle handle) { + // On CC26xx there is only one port encompassing all pins + if (handle) { + return handle->portMask; + } else { + return 0; + } +} + + + +uint32_t PIN_getPortInputValue(PIN_Handle handle) { + return PINCC26XX_getPortInputValue(handle); +} + + + +uint32_t PIN_getPortOutputValue(PIN_Handle handle) { + return PINCC26XX_getPortOutputValue(handle); +} + + + +PIN_Status PIN_setPortOutputValue(PIN_Handle handle, uint32_t bmOutVal) { + if (PIN_CHKEN && (handle == NULL || pinHandleTable[PIN_ctz(handle->portMask)] != handle)) { + return PIN_NO_ACCESS; + } + PINCC26XX_setPortOutputValue(handle, bmOutVal); + return PIN_SUCCESS; +} + + + +PIN_Status PIN_setPortOutputEnable(PIN_Handle handle, uint32_t bmOutEn) { + if (PIN_CHKEN && (handle == NULL || pinHandleTable[PIN_ctz(handle->portMask)] != handle)) { + return PIN_NO_ACCESS; + } + PINCC26XX_setPortOutputEnable(handle, bmOutEn); + return PIN_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pin/PINCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pin/PINCC26XX.h new file mode 100644 index 0000000..e014af2 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pin/PINCC26XX.h @@ -0,0 +1,443 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!***************************************************************************** + * @file PINCC26XX.h + * @brief Device-specific pin & GPIO driver for CC26xx family [def] + * + * # Overview # + * This is the device-specific implementation of the generic PIN driver for the + * CC26xx family of devices. + * + * Refer to @ref PIN.h for a complete description of APIs & example of use. + * + ******************************************************************************* + */ + +#ifndef ti_drivers_PINCC26XX__include +#define ti_drivers_PINCC26XX__include +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include + +#include + +#include +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/gpio.h) + +//------------------------------------------------------------------------------ +// Internal function used to find the index of the rightmost set bit in +// efficient way +#if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN) + #include +#endif + +__STATIC_INLINE uint32_t PIN_ctz(uint32_t x) { +#if defined(codered) || defined(gcc) || defined(sourcerygxx) || defined(__GNUC__) + return __builtin_ctz(x); +#elif defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN) + return __CLZ(__RBIT(x)); +#elif defined(rvmdk) || defined(__ARMCC_VERSION) + return __clz(__rbit(x)); +#elif defined(__TI_COMPILER_VERSION__) + return __clz(__rbit(x)); +#else + #error "Unsupported compiler used" +#endif +} + +//------------------------------------------------------------------------------ + +// Constant that can be used to remove run-time checks for improved efficiency +// Activate through preprocessor define PIN_DISABLE_RUNTIME_CHECKS +#ifdef PIN_DISABLE_RUNTIME_CHECKS + #define PIN_CHKEN 0 +#else + #define PIN_CHKEN 1 +#endif + +/** @anchor PINCC26XX_FLAGS + * @name Device-specific PIN_Config flags/fields for CC26xx family + * \{ + * CC26XX-specific I/O configuration fields/flags for use in #PIN_Config + * entries. These fields flags/for the most part map directly to the values + * used in the @c IOCFG hardware registers for efficiency. May not be mixed + * with @ref PIN_GENERIC_FLAGS "device-independent I/O options". + */ +#define PINCC26XX_INPUT_EN (1 << 29) ///< Enable input buffer +#define PINCC26XX_HYSTERESIS (1 << 30) ///< Enable input buffer hysteresis +#define PINCC26XX_NOPULL (0x3 << 13) ///< No pull-up or pull-down resistor +#define PINCC26XX_PULLUP (0x2 << 13) ///< ~20k pull-up resistor enabled +#define PINCC26XX_PULLDOWN (0x1 << 13) ///< ~20k pull-down resistor enabled +#define PINCC26XX_BM_INPUT_EN (0x01 << 29) ///< Bitmask for input enable option +#define PINCC26XX_BM_HYSTERESIS (0x01 << 30) ///< Bitmask for all input mode options +#define PINCC26XX_BM_PULLING (0x03 << 13) ///< Bitmask for pull-up/pull-down options +/// Bitmask for all input mode options +#define PINCC26XX_BM_INPUT_MODE (PINCC26XX_BM_INPUT_EN | PINCC26XX_BM_HYSTERESIS | \ + PINCC26XX_BM_PULLING) + +#define PINCC26XX_GPIO_OUTPUT_EN (1 << 23) ///< Enable output buffer when GPIO +#define PINCC26XX_GPIO_LOW (0 << 22) ///< Output buffer drives to VSS when GPIO +#define PINCC26XX_GPIO_HIGH (1 << 22) ///< Output buffer drives to VDD when GPIO +#define PINCC26XX_PUSHPULL (0x0 << 25) ///< Output buffer mode: push/pull +#define PINCC26XX_OPENDRAIN (0x2 << 25) ///< Output buffer mode: open drain +#define PINCC26XX_OPENSOURCE (0x3 << 25) ///< Output buffer mode: open source +#define PINCC26XX_SLEWCTRL (1 << 12) ///< Enable output buffer slew control +#define PINCC26XX_DRVSTR_MIN (0x0 << 8) ///< Drive strength is 2/2 mA +#define PINCC26XX_DRVSTR_MED (0x4 << 8) ///< Drive strength is 4/4 mA +#define PINCC26XX_DRVSTR_MAX (0x8 << 8) ///< Drive strength is 4/8 mA +#define PINCC26XX_BM_GPIO_OUTPUT_EN (1 << 23) ///< Bitmask for output enable option +#define PINCC26XX_BM_GPIO_OUTPUT_VAL (1 << 22) ///< Bitmask for output value option +#define PINCC26XX_BM_OUTPUT_BUF (3 << 25) ///< Bitmask for output buffer options +#define PINCC26XX_BM_SLEWCTRL (1 << 12) ///< Bitmask for slew control options +#define PINCC26XX_BM_DRVSTR (0xF << 8) ///< Bitmask for drive strength options +/// Bitmask for all GPIO output mode options +#define PINCC26XX_BM_GPIO_OUTPUT_MODE (PINCC26XX_BM_GPIO_OUTPUT_EN | PINCC26XX_BM_GPIO_OUTPUT_VAL) +/// Bitmask for all output mode options +#define PINCC26XX_BM_OUTPUT_MODE (PINCC26XX_BM_GPIO_OUTPUT_MODE | PINCC26XX_BM_OUTPUT_BUF | \ + PINCC26XX_BM_SLEWCTRL | PINCC26XX_BM_DRVSTR) + +#define PINCC26XX_INV_INOUT (1 << 24) ///< Logically invert input and output +#define PINCC26XX_IRQ_DIS (0x0 << 16) ///< Enable IRQ on pin +#define PINCC26XX_IRQ_NEGEDGE (0x5 << 16) ///< IRQ on negative edge +#define PINCC26XX_IRQ_POSEDGE (0x6 << 16) ///< IRQ on positive edge +#define PINCC26XX_IRQ_BOTHEDGES (0x7 << 16) ///< IRQ on both edges +#define PINCC26XX_BM_INV_INOUT (1 << 24) ///< Bitmask for input/output inversion option +#define PINCC26XX_BM_IRQ (0x7 << 16) ///< Bitmask for pin interrupt option + +#define PINCC26XX_NO_WAKEUP (0 << 27) ///< No wakeup from shutdown for this pin +#define PINCC26XX_WAKEUP_POSEDGE (3 << 27) ///< Wakeup from shutdown on positive edge +#define PINCC26XX_WAKEUP_NEGEDGE (2 << 27) ///< Wakeup from shutdown on negative edge +#define PINCC26XX_BM_WAKEUP (3 << 27) ///< Bitmask for pin wakeup from shutdown option + +/// Bitmask for all pin options in IOCFG register +#define PINCC26XX_BM_IOCFG (PINCC26XX_BM_INPUT_MODE|PINCC26XX_BM_OUTPUT_BUF | \ + PINCC26XX_BM_SLEWCTRL | PINCC26XX_BM_DRVSTR | \ + PINCC26XX_BM_INV_INOUT | PINCC26XX_BM_IRQ | PINCC26XX_BM_WAKEUP) +/// Bitmask for all pin options +#define PINCC26XX_BM_ALL (PINCC26XX_BM_IOCFG | PINCC26XX_BM_GPIO_OUTPUT_MODE) + +/** \} (PINCC26XX_FLAGS) + */ + +/** @anchor PINCC26XX_IONAMES + * @name PIN names for the CC26xx family + * \{ + * The digital I/O pins in the CC26xx family are named DIOx, where x is from + * 0 to IO_MAX. Numeric IO indexes for x can be used directly, i.e. 5 or + * PIN_ID(5). For convenience and readability aliases are defined below for + * all DIOs. + */ +#define PINCC26XX_DIO0 0 +#define PINCC26XX_DIO1 1 +#define PINCC26XX_DIO2 2 +#define PINCC26XX_DIO3 3 +#define PINCC26XX_DIO4 4 +#define PINCC26XX_DIO5 5 +#define PINCC26XX_DIO6 6 +#define PINCC26XX_DIO7 7 +#define PINCC26XX_DIO8 8 +#define PINCC26XX_DIO9 9 +#define PINCC26XX_DIO10 10 +#define PINCC26XX_DIO11 11 +#define PINCC26XX_DIO12 12 +#define PINCC26XX_DIO13 13 +#define PINCC26XX_DIO14 14 +#define PINCC26XX_DIO15 15 +#define PINCC26XX_DIO16 16 +#define PINCC26XX_DIO17 17 +#define PINCC26XX_DIO18 18 +#define PINCC26XX_DIO19 19 +#define PINCC26XX_DIO20 20 +#define PINCC26XX_DIO21 21 +#define PINCC26XX_DIO22 22 +#define PINCC26XX_DIO23 23 +#define PINCC26XX_DIO24 24 +#define PINCC26XX_DIO25 25 +#define PINCC26XX_DIO26 26 +#define PINCC26XX_DIO27 27 +#define PINCC26XX_DIO28 28 +#define PINCC26XX_DIO29 29 +#define PINCC26XX_DIO30 30 +#define PINCC26XX_DIO31 31 +/** \} (PINCC26XX_IONAMES) + */ + +/// @brief Fast/efficient version of #PIN_getInputValue() +__STATIC_INLINE uint32_t PINCC26XX_getInputValue(PIN_Id pinId) { + return (HWREG(GPIO_BASE + GPIO_O_DIN31_0) >> pinId) & 1; +} + + +/* @brief Fast/efficient version of #PIN_setOutputEnable() + * @note Does not include any checks on handle for efficiency reasons, + * use #PIN_setOutputEnable() for checked version + */ +__STATIC_INLINE void PINCC26XX_setOutputEnable(PIN_Id pinId, bool outputEnable) { + uint32_t key = HwiP_disable(); + HWREG(GPIO_BASE + GPIO_O_DOE31_0) = + ((HWREG(GPIO_BASE + GPIO_O_DOE31_0) & ~(1 << pinId)) | (outputEnable << pinId)); + HwiP_restore(key); +} + + +/* @brief Fast/efficient version of #PIN_setOutputValue() + * @note Does not include any checks on handle for efficiency reasons, + * use #PIN_setOutputValue() for checked version + */ +__STATIC_INLINE void PINCC26XX_setOutputValue(PIN_Id pinId, uint32_t val) { + HWREGB(GPIO_BASE + GPIO_O_DOUT3_0 + pinId) = (val) ? 1 : 0; +} + + +/// @brief Fast/efficient version of #PIN_getOutputValue() +__STATIC_INLINE uint32_t PINCC26XX_getOutputValue(PIN_Id pinId) { + return (HWREG(GPIO_BASE + GPIO_O_DOUT31_0) >> pinId) & 1; +} + + +__STATIC_INLINE void PINCC26XX_clrPendInterrupt(PIN_Id pinId) { + HWREG(GPIO_NONBUF_BASE + GPIO_O_EVFLAGS31_0) = (1 << pinId); +} + + +/// @brief Fast/efficient version of #PIN_getPortInputValue() +__STATIC_INLINE uint32_t PINCC26XX_getPortInputValue(PIN_Handle handle) { + // Only a single port on CC26xx + return HWREG(GPIO_BASE + GPIO_O_DIN31_0); +} + + +/// @brief Fast/efficient version of #PIN_getPortOutputValue() +__STATIC_INLINE uint32_t PINCC26XX_getPortOutputValue(PIN_Handle handle) { + // Only a single port on CC26xx + return HWREG(GPIO_BASE + GPIO_O_DOUT31_0); +} + + +/* @brief Fast/efficient version of #PIN_setPortOutputValue() + * @note Does not include any checks on handle for efficiency reasons, + * use #PIN_setPortOutputValue() for checked version + */ +__STATIC_INLINE void PINCC26XX_setPortOutputValue(PIN_Handle handle, uint32_t outputValueMask) { + // Only a single port on CC26xx + HWREG(GPIO_BASE + GPIO_O_DOUTTGL31_0) = + (HWREG(GPIO_BASE + GPIO_O_DOUT31_0) ^ outputValueMask) & handle->portMask; +} + + +/* @brief Fast/efficient version of #PIN_setPortOutputEnable() + * @note Does not include any checks on handle for efficiency reasons, + * use #PIN_setPortOutputEnable() for checked version + */ +__STATIC_INLINE void PINCC26XX_setPortOutputEnable(PIN_Handle handle, uint32_t outputEnableMask) { + // Only a single port on CC26xx + uint32_t key = HwiP_disable(); + HWREG(GPIO_BASE + GPIO_O_DOE31_0) = + (HWREG(GPIO_BASE + GPIO_O_DOE31_0) & (~handle->portMask)) | (outputEnableMask & handle->portMask); + HwiP_restore(key); +} + + +/** @brief Returns CC26xx device-specific pin configuration + * + * @param pinId Pin ID + * @return Current pin configuration as a #PIN_Config value + * @note The pin ID is embedded in return value. + * @note Return value uses @ref PINCC26XX_FLAGS "CC26xx specific I/O options" + */ +extern PIN_Config PINCC26XX_getConfig(PIN_Id pinId); + + +/** @brief Configure wakeup (from shutdown) on pins + * + * @param aPinCfg #PIN_Config list identifying pin ID and relevant pin + * configuration as one of: + * - #PINCC26XX_NO_WAKEUP (default) + * - #PINCC26XX_WAKEUP_POSEDGE + * - #PINCC26XX_WAKEUP_NEGEDGE + * @return #PIN_SUCCESS if successful, else error code + * + * @par Usage + * @code + * PIN_setWakeup(NULL, PIN_ID(9)|PIN_WAKEUP_NEGEDGE); + * Power_shutdown(0, 0); + * @endcode + * + * @note A wake-up event to wake up from shutdown is not detected until + * the device reaches shutdown. Wake-up events happening after a shutdown + * is initiated but before actual shutdown are not captured and thus will + * not cause the device to wake up. + */ +extern PIN_Status PINCC26XX_setWakeup(const PIN_Config aPinCfg[]); + + +/** @brief Get device-specific pin mapping to GPIO, HW peripheral or HW signal + * + * @param pinId Pin ID + * @return Device-specific pin mapping index for connection to hardware + * peripheral or hardware signal, -1 if pin is used for GPIO + * @note Mostly used by driver code + * @par Usage + * @code + * if (PINCC26XX_getMux(PIN_ID(16)) < 0) { + * // Pin is GPIO + * } + * @endcode + */ +extern int32_t PINCC26XX_getMux(PIN_Id pinId); + +/** @brief Get device-specific count of how many pins are available on this device and package + * + * @return Device and package specific pin count + * @note Mostly used by driver code + */ +extern uint32_t PINCC26XX_getPinCount(); + +/** @brief Connect pin to HW peripheral, signal or to GPIO + * + * @param handle Handle provided by previous call to PIN_open() + * @param pinId Pin ID + * @param nMux Device-specific index of peripheral port or hardware signal. + * A value of -1 reverts the pin to GPIO mapping + * @return #PIN_SUCCESS if successful, else error code + * @note Mostly used by driver code or for diagnostics + * @par Usage + * @code + * PIN_setMux(hPins, PIN_ID(16), PINCC26XX_UART_TX); + * @endcode + */ +extern PIN_Status PINCC26XX_setMux(PIN_Handle handle, PIN_Id pinId, int32_t nMux); + +/*! + * @brief PINCC26XX Hardware attributes + * + * intPriority is the PIN driver's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * + * swiPriority defines the priority of the SWI the registered callback function + * will be called in. + * + */ +typedef struct PINCC26XX_HWAttrs{ + /*! @brief SPI CC26XXDMA Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief SPI SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; +} PINCC26XX_HWAttrs; + +/** @anchor PINCC26XX_MUX_VALS + * @name Device-specific pin mux values for CC26xx family + * \deprecated Use IOC_PORT_* defines from driverlib/ioc.h directly instead + * \{ + * CC26XX-specific mux vakues used in conjunction with #PINCC26XX_setMux() to + * map hardware peripheral ports, GPIO or observation signals to pins. + */ +#define PINCC26XX_MUX_GPIO IOC_PORT_GPIO // Default general purpose IO usage +#define PINCC26XX_MUX_AON_CLK32K IOC_PORT_AON_CLK32K // AON External 32kHz clock +#define PINCC26XX_MUX_AUX_IO IOC_PORT_AUX_IO // AUX IO Pin +#define PINCC26XX_MUX_MCU_SSI0_RX IOC_PORT_MCU_SSI0_RX // MCU SSI0 Receive Pin +#define PINCC26XX_MUX_MCU_SSI0_TX IOC_PORT_MCU_SSI0_TX // MCU SSI0 Transmit Pin +#define PINCC26XX_MUX_MCU_SSI0_FSS IOC_PORT_MCU_SSI0_FSS // MCU SSI0 FSS Pin +#define PINCC26XX_MUX_MCU_SSI0_CLK IOC_PORT_MCU_SSI0_CLK // MCU SSI0 Clock Pin +#define PINCC26XX_MUX_MCU_I2C_MSSDA IOC_PORT_MCU_I2C_MSSDA // MCU I2C Data Pin +#define PINCC26XX_MUX_MCU_I2C_MSSCL IOC_PORT_MCU_I2C_MSSCL // MCU I2C Clock Pin +#define PINCC26XX_MUX_MCU_UART0_RX IOC_PORT_MCU_UART0_RX // MCU UART0 Receive Pin +#define PINCC26XX_MUX_MCU_UART0_TX IOC_PORT_MCU_UART0_TX // MCU UART0 Transmit Pin +#define PINCC26XX_MUX_MCU_UART0_CTS IOC_PORT_MCU_UART0_CTS // MCU UART0 Clear To Send Pin +#define PINCC26XX_MUX_MCU_UART0_RTS IOC_PORT_MCU_UART0_RTS // MCU UART0 Request To Send Pin +#define PINCC26XX_MUX_MCU_PORT_EV_0 IOC_PORT_MCU_PORT_EVENT0 // MCU power event 0 +#define PINCC26XX_MUX_MCU_PORT_EV_1 IOC_PORT_MCU_PORT_EVENT1 // MCU power event 1 +#define PINCC26XX_MUX_MCU_PORT_EV_2 IOC_PORT_MCU_PORT_EVENT2 // MCU power event 2 +#define PINCC26XX_MUX_MCU_PORT_EV_3 IOC_PORT_MCU_PORT_EVENT3 // MCU power event 3 +#define PINCC26XX_MUX_MCU_PORT_EV_4 IOC_PORT_MCU_PORT_EVENT4 // MCU power event 4 +#define PINCC26XX_MUX_MCU_PORT_EV_5 IOC_PORT_MCU_PORT_EVENT5 // MCU power event 5 +#define PINCC26XX_MUX_MCU_PORT_EV_6 IOC_PORT_MCU_PORT_EVENT6 // MCU power event 6 +#define PINCC26XX_MUX_MCU_PORT_EV_7 IOC_PORT_MCU_PORT_EVENT7 // MCU power event 7 +#define PINCC26XX_MUX_SWV IOC_PORT_MCU_SWV // MCU serial wire viewer +#define PINCC26XX_MUX_MCU_SSI1_RX IOC_PORT_MCU_SSI1_RX // MCU SSI1 Receive Pin +#define PINCC26XX_MUX_MCU_SSI1_TX IOC_PORT_MCU_SSI1_TX // MCU SSI1 Transmit Pin +#define PINCC26XX_MUX_MCU_SSI1_FSS IOC_PORT_MCU_SSI1_FSS // MCU SSI1 FSS Pin +#define PINCC26XX_MUX_MCU_SSI1_CLK IOC_PORT_MCU_SSI1_CLK // MCU SSI1 Clock Pin +#define PINCC26XX_MUX_MCU_I2S_AD0 IOC_PORT_MCU_I2S_AD0 // MCU I2S Data Pin 0 +#define PINCC26XX_MUX_MCU_I2S_AD1 IOC_PORT_MCU_I2S_AD1 // MCU I2S Data Pin 1 +#define PINCC26XX_MUX_MCU_I2S_WCLK IOC_PORT_MCU_I2S_WCLK // MCU I2S Frame/Word Clock +#define PINCC26XX_MUX_MCU_I2S_BCLK IOC_PORT_MCU_I2S_BCLK // MCU I2S Bit Clock +#define PINCC26XX_MUX_MCU_I2S_MCLK IOC_PORT_MCU_I2S_MCLK // MCU I2S Master clock 2 +#define PINCC26XX_MUX_RFC_TRC IOC_PORT_RFC_TRC // RF Core Tracer +#define PINCC26XX_MUX_RFC_GPO0 IOC_PORT_RFC_GPO0 // RC Core Data Out Pin 0 +#define PINCC26XX_MUX_RFC_GPO1 IOC_PORT_RFC_GPO1 // RC Core Data Out Pin 1 +#define PINCC26XX_MUX_RFC_GPO2 IOC_PORT_RFC_GPO2 // RC Core Data Out Pin 2 +#define PINCC26XX_MUX_RFC_GPO3 IOC_PORT_RFC_GPO3 // RC Core Data Out Pin 3 +#define PINCC26XX_MUX_RFC_GPI0 IOC_PORT_RFC_GPI0 // RC Core Data In Pin 0 +#define PINCC26XX_MUX_RFC_GPI1 IOC_PORT_RFC_GPI1 // RC Core Data In Pin 1 +#define PINCC26XX_MUX_RFC_SMI_DL_OUT IOC_PORT_RFC_SMI_DL_OUT // RF Core SMI Data Link Out +#define PINCC26XX_MUX_RFC_SMI_DL_IN IOC_PORT_RFC_SMI_DL_IN // RF Core SMI Data Link in +#define PINCC26XX_MUX_RFC_SMI_CL_OUT IOC_PORT_RFC_SMI_CL_OUT // RF Core SMI Command Link Out +#define PINCC26XX_MUX_RFC_SMI_CL_IN IOC_PORT_RFC_SMI_CL_IN // RF Core SMI Command Link In +/** \} (PINCC26XX_MUX_VALS) + */ + + +#ifdef __cplusplus +} +#endif +#endif /* ti_drivers_PINCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26X2.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26X2.c new file mode 100644 index 0000000..ca6beb5 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26X2.c @@ -0,0 +1,1317 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC26X2.c ======== + */ + +#include + +#include +#include +#include +#include + +#include +#include + +/* driverlib header files */ +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_prcm.h) +#include DeviceFamily_constructPath(inc/hw_nvic.h) +#include DeviceFamily_constructPath(inc/hw_aux_sysif.h) +#include DeviceFamily_constructPath(inc/hw_aon_rtc.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ccfg.h) +#include DeviceFamily_constructPath(inc/hw_rfc_pwr.h) +#include DeviceFamily_constructPath(inc/hw_aon_pmctl.h) +#include DeviceFamily_constructPath(inc/hw_fcfg1.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/pwr_ctrl.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_rtc.h) +#include DeviceFamily_constructPath(driverlib/aon_event.h) +#include DeviceFamily_constructPath(driverlib/osc.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/vims.h) +#include DeviceFamily_constructPath(driverlib/rfc.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/driverlib_release.h) +#include DeviceFamily_constructPath(driverlib/setup.h) +#include DeviceFamily_constructPath(driverlib/ccfgread.h) + +static unsigned int configureXOSCHF(unsigned int action); +static unsigned int nopResourceHandler(unsigned int action); +static unsigned int configureRFCoreClocks(unsigned int action); +static void switchXOSCHF(void); +static void disableLFClockQualifiers(void); +static void emptyClockFunc(uintptr_t arg); +static int_fast16_t notify(uint_fast16_t eventType); +static void oscillatorISR(uintptr_t arg); + +/* RCOSC calibration functions functions */ +extern void PowerCC26X2_calibrate(void); +extern bool PowerCC26X2_initiateCalibration(void); +extern void PowerCC26X2_auxISR(uintptr_t arg); +extern void PowerCC26X2_RCOSC_clockFunc(uintptr_t arg); + +/* Externs */ +extern const PowerCC26X2_Config PowerCC26X2_config; + +/* Module_State */ +PowerCC26X2_ModuleState PowerCC26X2_module = { + .notifyList = {0}, /* list of registered notifications */ + .constraintMask = 0, /* the constraint mask */ + .clockObj = {0}, /* Clock object for scheduling wakeups */ + .tdcHwi = {0}, /* hwi object for calibration */ + .oscHwi = {0}, /* hwi object for oscillators */ + .nDeltaFreqCurr = 0, /* RCOSC calibration variable */ + .nCtrimCurr = 0, /* RCOSC calibration variable */ + .nCtrimFractCurr = 0, /* RCOSC calibration variable */ + .nCtrimNew = 0, /* RCOSC calibration variable */ + .nCtrimFractNew = 0, /* RCOSC calibration variable */ + .nRtrimNew = 0, /* RCOSC calibration variable */ + .nRtrimCurr = 0, /* RCOSC calibration variable */ + .nDeltaFreqNew = 0, /* RCOSC calibration variable */ + .bRefine = false, /* RCOSC calibration variable */ + .state = Power_ACTIVE, /* current transition state */ + .xoscPending = false, /* is XOSC_HF activation in progress? */ + .calLF = false, /* calibrate RCOSC_LF? */ + .auxHwiState = 0, /* calibration AUX ISR state */ + .busyCal = false, /* already busy calibrating */ + .calStep = 0, /* current calibration step */ + .firstLF = true, /* is this first LF calibration? */ + .enablePolicy = false, /* default value is false */ + .initialized = false, /* whether Power_init has been called */ + .constraintCounts = { 0, 0, 0, 0, 0, 0, 0 }, + .resourceCounts = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + .resourceHandlers = { + configureRFCoreClocks, + configureXOSCHF, + nopResourceHandler + }, /* special resource handler functions */ + .policyFxn = 0 /* power policyFxn */ +}; + +/* resource database */ +const PowerCC26XX_ResourceRecord resourceDB[PowerCC26X2_NUMRESOURCES] = { + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER0}, /* PERIPH_GPT0 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER1}, /* PERIPH_GPT1 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER2}, /* PERIPH_GPT2 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER3}, /* PERIPH_GPT3 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_SERIAL, PRCM_PERIPH_SSI0}, /* PERIPH_SSI0 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_SSI1}, /* PERIPH_SSI1 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_SERIAL, PRCM_PERIPH_UART0}, /* PERIPH_UART0 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_SERIAL, PRCM_PERIPH_I2C0}, /* PERIPH_I2C0 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TRNG}, /* PERIPH_TRNG */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_GPIO}, /* PERIPH_GPIO */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_UDMA}, /* PERIPH_UDMA */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_CRYPTO}, /* PERIPH_CRYPTO */ + {PowerCC26XX_PERIPH | PowerCC26XX_PERIPH_UDMA, PRCM_PERIPH_I2S}, /* PERIPH_I2S */ + {PowerCC26XX_SPECIAL | PowerCC26XX_DOMAIN_RFCORE, 0}, /* PERIPH_RFCORE */ + {PowerCC26XX_SPECIAL | PowerCC26XX_NOPARENT, 1}, /* XOSC_HF */ + {PowerCC26XX_DOMAIN | PowerCC26XX_NOPARENT, PRCM_DOMAIN_PERIPH}, /* DOMAIN_PERIPH */ + {PowerCC26XX_DOMAIN | PowerCC26XX_NOPARENT, PRCM_DOMAIN_SERIAL}, /* DOMAIN_SERIAL */ + {PowerCC26XX_DOMAIN | PowerCC26XX_NOPARENT, PRCM_DOMAIN_RFCORE}, /* DOMAIN_RFCORE */ + {PowerCC26XX_SPECIAL | PowerCC26XX_NOPARENT, 2}, /* DOMAIN_SYSBUS */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_PKA}, /* PERIPH_PKA */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_UART1}, /* PERIPH_UART1 */ +}; + + +/* ****************** Power APIs ******************** */ + +/* + * ======== Power_disablePolicy ======== + * Do not run the configured policy + */ +bool Power_disablePolicy(void) +{ + bool enablePolicy = PowerCC26X2_module.enablePolicy; + PowerCC26X2_module.enablePolicy = false; + + return (enablePolicy); +} + +/* + * ======== Power_enablePolicy ======== + * Run the configured policy + */ +void Power_enablePolicy(void) +{ + PowerCC26X2_module.enablePolicy = true; +} + +/* + * ======== Power_getConstraintMask ======== + * Get a bitmask indicating the constraints that have been registered with + * Power. + */ +uint_fast32_t Power_getConstraintMask(void) +{ + return (PowerCC26X2_module.constraintMask); +} + +/* + * ======== Power_getDependencyCount ======== + * Get the count of dependencies that are currently declared upon a resource. + */ +int_fast16_t Power_getDependencyCount(uint_fast16_t resourceId) +{ + DebugP_assert(resourceId < PowerCC26X2_NUMRESOURCES); + + return ((int_fast16_t)PowerCC26X2_module.resourceCounts[resourceId]); +} + +/* + * ======== Power_getTransitionLatency ======== + * Get the transition latency for a sleep state. The latency is reported + * in units of microseconds. + */ +uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, + uint_fast16_t type) +{ + uint32_t latency = 0; + + if (type == Power_RESUME) { + if (sleepState == PowerCC26XX_STANDBY) { + latency = PowerCC26X2_RESUMETIMESTANDBY; + } + } + else { + if (sleepState == PowerCC26XX_STANDBY) { + latency = PowerCC26X2_TOTALTIMESTANDBY; + } + } + + return (latency); +} + +/* + * ======== Power_getTransitionState ======== + * Get the current sleep transition state. + */ +uint_fast16_t Power_getTransitionState(void) +{ + return (PowerCC26X2_module.state); +} + +/* + * ======== Power_idleFunc ======== + * Function needs to be plugged into the idle loop. + * It calls the configured policy function if the + * 'enablePolicy' flag is set. + */ +void Power_idleFunc() +{ + if (PowerCC26X2_module.enablePolicy) { + if (PowerCC26X2_module.policyFxn != NULL) { + (*(PowerCC26X2_module.policyFxn))(); + } + } +} + +/* + * ======== Power_init ======== + */ +int_fast16_t Power_init() +{ + ClockP_Params clockParams; + uint32_t ccfgLfClkSrc; + + /* CC26X2 PG1.0 trap. If we are running on PG1.0, spin forever. + * This hardware revision is no longer supported. This trap is + * provided to aid in automatically identifying PG1.0 devices + * in circulation and will be removed later in the year. + */ + if (!((HWREG(FCFG1_BASE + FCFG1_O_TFW_FT) % 10000) >= 683)) { + while (1); + } + + /* if this function has already been called, just return */ + if (PowerCC26X2_module.initialized) { + return (Power_SOK); + } + + /* set module state field 'initialized' to true */ + PowerCC26X2_module.initialized = true; + + /* set the module state enablePolicy field */ + PowerCC26X2_module.enablePolicy = PowerCC26X2_config.enablePolicy; + + /* copy the Power policy function to module state */ + PowerCC26X2_module.policyFxn = PowerCC26X2_config.policyFxn; + + /* construct the Clock object for scheduling of wakeups */ + /* initiated and started by the power policy */ + ClockP_Params_init(&clockParams); + clockParams.period = 0; + clockParams.startFlag = false; + clockParams.arg = 0; + ClockP_construct(&PowerCC26X2_module.clockObj, + &emptyClockFunc, + 0, + &clockParams); + + /* + * If RCOSC calibration is enabled, construct a Clock object for + * delays. Set timeout to 8 Clock tick periods to get + * ceil(8x10us/30.5us/SCLK_LF_period)*30.5us/SCLK_LF_period = ~90us. + * The total time we need to wait for AUX_SYSIF_TDCREFCLKCTL_ACK + * is about 105us and the ClockP_start() call needs about 21us. + * All together, that makes ~111us. A decent approximation of the + * ideal wait duration. + * In practice, the COMPARE_MARGIN that is currently still in + * the kernel Timer.c implementation may make it take longer + * than 90us to time out. + */ + ClockP_Params_init(&clockParams); + clockParams.period = 0; + clockParams.startFlag = false; + clockParams.arg = 0; + ClockP_construct(&PowerCC26X2_module.calibrationClock, + &PowerCC26X2_RCOSC_clockFunc, + 8, + &clockParams); + + HwiP_construct(&PowerCC26X2_module.oscHwi, + INT_OSC_COMB, + oscillatorISR, NULL); + HWREG(PRCM_BASE + PRCM_O_OSCIMSC) = 0; + + /* construct the TDC hwi */ + HwiP_construct(&PowerCC26X2_module.tdcHwi, + INT_AUX_COMB, + PowerCC26X2_auxISR, NULL); + + DRIVERLIB_ASSERT_CURR_RELEASE(); + + /* read the LF clock source from CCFG */ + ccfgLfClkSrc = CCFGRead_SCLK_LF_OPTION(); + + /* check if should calibrate RCOSC_LF */ + if (PowerCC26X2_config.calibrateRCOSC_LF) { + /* verify RCOSC_LF is the LF clock source */ + if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_RCOSC_LF) { + PowerCC26X2_module.calLF = true; + } + } + + /* + * if LF source is RCOSC_LF or XOSC_LF: assert DISALLOW_STANDBY constraint + * and start a timeout to check for activation + */ + if ((ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_RCOSC_LF) || + (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_XOSC_LF)) { + + /* Turn on oscillator interrupt for SCLK_LF switching */ + HWREG(PRCM_BASE + PRCM_O_OSCIMSC) |= PRCM_OSCIMSC_LFSRCDONEIM_M; + + /* disallow STANDBY pending LF clock quailifier disabling */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + else if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF) { + /* + * else, if the LF clock source is external, can disable clock qualifiers + * now; no need to assert DISALLOW_STANDBY or start the Clock object + */ + + /* yes, disable the LF clock qualifiers */ + DDI16BitfieldWrite( + AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M| + DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M, + DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S, + 0x3); + + /* enable clock loss detection */ + OSCClockLossEventEnable(); + } + else if(ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF) { + /* else, user has requested LF to be derived from XOSC_HF */ + + /* Turn on oscillator interrupt for SCLK_LF switching. + * When using HPOSC, the LF clock will already have switched + * and the interrupt will fire once interrupts are enabled + * again when the OS starts. + * When using a regular HF crystal, it may take a little + * time for the crystal to start up + */ + HWREG(PRCM_BASE + PRCM_O_OSCIMSC) |= PRCM_OSCIMSC_LFSRCDONEIM_M; + + /* disallow standby since we cannot go into standby with + * an HF derived LF clock + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* if VIMS RAM is configured as GPRAM: set retention constraint */ + if (!CCFGRead_DIS_GPRAM()) { + Power_setConstraint(PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY); + } + + return (Power_SOK); +} + +/* + * ======== Power_registerNotify ======== + * Register a function to be called on a specific power event. + * + */ +int_fast16_t Power_registerNotify(Power_NotifyObj * pNotifyObj, + uint_fast16_t eventTypes, Power_NotifyFxn notifyFxn, uintptr_t clientArg) +{ + int_fast16_t status = Power_SOK; + + /* check for NULL pointers */ + if ((pNotifyObj == NULL) || (notifyFxn == NULL)) { + status = Power_EINVALIDPOINTER; + } + + else { + /* fill in notify object elements */ + pNotifyObj->eventTypes = eventTypes; + pNotifyObj->notifyFxn = notifyFxn; + pNotifyObj->clientArg = clientArg; + + /* place notify object on event notification queue */ + List_put(&PowerCC26X2_module.notifyList, (List_Elem*)pNotifyObj); + } + + return (status); +} + +/* + * ======== Power_releaseConstraint ======== + * Release a previously declared constraint. + */ +int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId) +{ + unsigned int key; + uint8_t count; + + /* assert constraintId is valid */ + DebugP_assert(constraintId < PowerCC26X2_NUMCONSTRAINTS); + + key = HwiP_disable(); + + /* get the count of the constraint */ + count = PowerCC26X2_module.constraintCounts[constraintId]; + + DebugP_assert(count != 0); + + count--; + + /* save the updated count */ + PowerCC26X2_module.constraintCounts[constraintId] = count; + + if (count == 0) { + PowerCC26X2_module.constraintMask &= ~(1 << constraintId); + } + + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_releaseDependency ======== + * Release a previously declared dependency. + */ +int_fast16_t Power_releaseDependency(uint_fast16_t resourceId) +{ + uint8_t parent; + uint8_t count; + uint32_t id; + unsigned int key; + + /* assert resourceId is valid */ + DebugP_assert(resourceId < PowerCC26X2_NUMRESOURCES); + + /* disable interrupts */ + key = HwiP_disable(); + + /* read and decrement the reference count */ + count = PowerCC26X2_module.resourceCounts[resourceId]; + + DebugP_assert(count != 0); + + count--; + + /* save the reference count */ + PowerCC26X2_module.resourceCounts[resourceId] = count; + + /* if this was the last dependency being released.., */ + if (count == 0) { + /* deactivate this resource ... */ + id = resourceDB[resourceId].driverlibID; + + /* is resource a peripheral?... */ + if (resourceDB[resourceId].flags & PowerCC26XX_PERIPH) { + PRCMPeripheralRunDisable(id); + PRCMPeripheralSleepDisable(id); + PRCMPeripheralDeepSleepDisable(id); + PRCMLoadSet(); + while (!PRCMLoadGet()) { + ; + } + } + /* else, does resource require a special handler?... */ + else if (resourceDB[resourceId].flags & PowerCC26XX_SPECIAL) { + /* call the special handler */ + PowerCC26X2_module.resourceHandlers[id](PowerCC26XX_DISABLE); + } + + /* else resource is a power domain */ + else { + PRCMPowerDomainOff(id); + while (PRCMPowerDomainStatus(id) != PRCM_DOMAIN_POWER_OFF) { + ; + } + } + + /* propagate release up the dependency tree ... */ + + /* check for a first parent */ + parent = resourceDB[resourceId].flags & PowerCC26XX_PARENTMASK; + + /* if 1st parent, make recursive call to release that dependency */ + if (parent < PowerCC26X2_NUMRESOURCES) { + Power_releaseDependency(parent); + } + } + + /* re-enable interrupts */ + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_setConstraint ======== + * Declare an operational constraint. + */ +int_fast16_t Power_setConstraint(uint_fast16_t constraintId) +{ + unsigned int key; + + /* assert constraint id is valid */ + DebugP_assert(constraintId < PowerCC26X2_NUMCONSTRAINTS); + + /* disable interrupts */ + key = HwiP_disable(); + + /* set the specified constraint in the constraintMask */ + PowerCC26X2_module.constraintMask |= 1 << constraintId; + + /* increment the specified constraint count */ + PowerCC26X2_module.constraintCounts[constraintId]++; + + /* re-enable interrupts */ + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_setDependency ======== + * Declare a dependency upon a resource. + */ +int_fast16_t Power_setDependency(uint_fast16_t resourceId) +{ + uint8_t parent; + uint8_t count; + uint32_t id; + unsigned int key; + + /* assert resourceId is valid */ + DebugP_assert(resourceId < PowerCC26X2_NUMRESOURCES); + + /* disable interrupts */ + key = HwiP_disable(); + + /* read and increment reference count */ + count = PowerCC26X2_module.resourceCounts[resourceId]++; + + /* if resource was NOT activated previously ... */ + if (count == 0) { + /* propagate set up the dependency tree ... */ + + /* check for a first parent */ + parent = resourceDB[resourceId].flags & PowerCC26XX_PARENTMASK; + + /* if first parent, make recursive call to set that dependency */ + if (parent < PowerCC26X2_NUMRESOURCES) { + Power_setDependency(parent); + } + + /* now activate this resource ... */ + id = resourceDB[resourceId].driverlibID; + + /* is resource a peripheral?... */ + if (resourceDB[resourceId].flags & PowerCC26XX_PERIPH) { + PRCMPeripheralRunEnable(id); + PRCMPeripheralSleepEnable(id); + PRCMPeripheralDeepSleepEnable(id); + PRCMLoadSet(); + while (!PRCMLoadGet()) { + ; + } + } + /* else, does resource require a special handler?... */ + else if (resourceDB[resourceId].flags & PowerCC26XX_SPECIAL) { + /* call the special handler */ + PowerCC26X2_module.resourceHandlers[id](PowerCC26XX_ENABLE); + } + /* else resource is a power domain */ + else { + PRCMPowerDomainOn(id); + while (PRCMPowerDomainStatus(id) != PRCM_DOMAIN_POWER_ON) { + ; + } + } + } + + /* re-enable interrupts */ + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_setPolicy ======== + * Set the Power policy function + */ +void Power_setPolicy(Power_PolicyFxn policy) +{ + PowerCC26X2_module.policyFxn = policy; +} + +/* + * ======== Power_shutdown ======== + */ +int_fast16_t Power_shutdown(uint_fast16_t shutdownState, + uint_fast32_t shutdownTime) +{ + int_fast16_t status = Power_EFAIL; + unsigned int constraints; + unsigned int hwiKey; + + /* disable interrupts */ + hwiKey = HwiP_disable(); + + /* check if there is a constraint to prohibit shutdown */ + constraints = Power_getConstraintMask(); + if (constraints & (1 << PowerCC26XX_DISALLOW_SHUTDOWN)) { + status = Power_ECHANGE_NOT_ALLOWED; + } + + /* OK to shutdown ... */ + else if (PowerCC26X2_module.state == Power_ACTIVE) { + /* set new transition state to entering shutdown */ + PowerCC26X2_module.state = Power_ENTERING_SHUTDOWN; + + /* signal all clients registered for pre-shutdown notification */ + status = notify(PowerCC26XX_ENTERING_SHUTDOWN); + + /* check for any error */ + if (status != Power_SOK) { + PowerCC26X2_module.state = Power_ACTIVE; + HwiP_restore(hwiKey); + return (status); + } + + /* Ensure the JTAG domain is turned off + * otherwise MCU domain can't be turned off. + */ + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_JTAGCFG) = 0; + + SysCtrlAonSync(); + + /* now proceed with shutdown sequence ... */ + SysCtrlShutdownWithAbort(); + } + else { + status = Power_EBUSY; + } + + /* NOTE: if shutdown succeeded, should never get here */ + + /* return failure status */ + PowerCC26X2_module.state = Power_ACTIVE; + + /* re-enable interrupts */ + HwiP_restore(hwiKey); + + /* if get here, failed to shutdown, return error code */ + return (status); +} + +/* + * ======== Power_sleep ======== + */ +int_fast16_t Power_sleep(uint_fast16_t sleepState) +{ + int_fast16_t status = Power_SOK; + int_fast16_t notifyStatus = Power_SOK; + int_fast16_t lateNotifyStatus = Power_SOK; + unsigned int xosc_hf_active = false; + uint_fast16_t postEventLate; + uint32_t poweredDomains = 0; + uint_fast16_t preEvent; + uint_fast16_t postEvent; + unsigned int constraints; + bool retainCache = false; + uint32_t modeVIMS; + unsigned int swiKey; + + /* first validate the sleep code */ + if (sleepState != PowerCC26XX_STANDBY) { + status = Power_EINVALIDINPUT; + } + + else { + + /* check to make sure Power is not busy with another transition */ + if (PowerCC26X2_module.state == Power_ACTIVE) { + /* set transition state to entering sleep */ + PowerCC26X2_module.state = Power_ENTERING_SLEEP; + } + else { + status = Power_EBUSY; + } + + if (status == Power_SOK) { + + /* setup sleep vars */ + preEvent = PowerCC26XX_ENTERING_STANDBY; + postEvent = PowerCC26XX_AWAKE_STANDBY; + postEventLate = PowerCC26XX_AWAKE_STANDBY_LATE; + + /* disable Task scheduling */ + PowerCC26XX_schedulerDisable(); + + /* signal all clients registered for pre-sleep notification */ + status = notify(preEvent); + + /* check for any error */ + if (status != Power_SOK) { + PowerCC26X2_module.state = Power_ACTIVE; + PowerCC26XX_schedulerRestore(); + return (status); + } + + /* now disable Swi scheduling */ + swiKey = SwiP_disable(); + + /* 1. Query and save domain states before powering them off */ + if (Power_getDependencyCount(PowerCC26XX_DOMAIN_RFCORE)) { + poweredDomains |= PRCM_DOMAIN_RFCORE; + } + if (Power_getDependencyCount(PowerCC26XX_DOMAIN_SERIAL)){ + poweredDomains |= PRCM_DOMAIN_SERIAL; + } + if (Power_getDependencyCount(PowerCC26XX_DOMAIN_PERIPH)) { + poweredDomains |= PRCM_DOMAIN_PERIPH; + } + + /* 2. If XOSC_HF is active or we are waiting to switch + * to it, force it off. Otherwise, the XOSC_HF may be + * automatically turned on by the hardware without + * a call to configureXOSCHF(PowerCC26XX_ENABLE) + * This is not necessarily a problem. However exactly + * what the cutoff point is where the hardware considers + * the XOSC_HF "on" without having switched to is not + * considered by this driver. + */ + if (OSCClockSourceGet(OSC_SRC_CLK_HF) == OSC_XOSC_HF || + PowerCC26X2_module.xoscPending == true) { + xosc_hf_active = true; + configureXOSCHF(PowerCC26XX_DISABLE); + } + + /* query constraints to determine if cache should be retained */ + constraints = Power_getConstraintMask(); + if (constraints & (1 << PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY)) { + retainCache = true; + } + else { + retainCache = false; + + // Get the current VIMS mode + do { + modeVIMS = VIMSModeGet(VIMS_BASE); + } while (modeVIMS == VIMS_MODE_CHANGING); + } + + /* 3. + * - Freeze the IOs on the boundary between MCU and AON + * - Make sure AON writes take effect + * - Request power off of every PD in the MCU voltage domain + * - Ensure that no clocks are forced on in Crypto, DMA and I2S + * - Gate running deep sleep clocks for Crypto, DMA and I2S + * - Load the new clock settings + * - Configure the VIMS power domain mode to power up flash + * again after coming out of standby. + * - Request uLDO during standby + * - Use recharge comparator + * - Ensure all writes have taken effect + * - Ensure UDMA, Crypto and I2C clocks are turned off + * - Ensure all non-CPU power domains are turned off + * - Turn off cache retention if requested + * - Invoke deep sleep to go to standby + */ + SysCtrlStandby(retainCache, + VIMS_ON_CPU_ON_MODE, + SYSCTRL_PREFERRED_RECHARGE_MODE); + + /* 4. If didn't retain VIMS in standby, re-enable retention now */ + if (retainCache == false) { + + /* 5.1 If previously in a cache mode, restore the mode now */ + if (modeVIMS == VIMS_MODE_ENABLED) { + VIMSModeSet(VIMS_BASE, modeVIMS); + } + + /* 5.2 Re-enable retention */ + PRCMCacheRetentionEnable(); + } + + /* 6. Start re-powering power domains */ + PRCMPowerDomainOn(poweredDomains); + + /* 7. Restore deep sleep clocks of Crypto and DMA */ + if (Power_getDependencyCount(PowerCC26XX_PERIPH_CRYPTO)) { + PRCMPeripheralDeepSleepEnable( + resourceDB[PowerCC26XX_PERIPH_CRYPTO].driverlibID); + } + if (Power_getDependencyCount(PowerCC26XX_PERIPH_UDMA)) { + PRCMPeripheralDeepSleepEnable( + resourceDB[PowerCC26XX_PERIPH_UDMA].driverlibID); + } + + /* 8. Make sure clock settings take effect */ + PRCMLoadSet(); + + /* 9. Release request for uLDO */ + PRCMMcuUldoConfigure(false); + + /* 10. Set transition state to EXITING_SLEEP */ + PowerCC26X2_module.state = Power_EXITING_SLEEP; + + /* 11. Wait until all power domains are back on */ + while (PRCMPowerDomainStatus(poweredDomains) != PRCM_DOMAIN_POWER_ON); + + /* 12. Wait for the RTC shadow values to be updated so that + * the early notification callbacks can read out valid RTC values. + * This can likely be removed as the 2MHz MF clock will have ticked by now. + */ + SysCtrlAonSync(); + + /* + * 13. Signal clients registered for early post-sleep notification; + * this should be used to initialize any timing critical or IO + * dependent hardware + */ + notifyStatus = notify(postEvent); + + /* 14. Disable IO freeze and ensure RTC shadow value is updated */ + AONIOCFreezeDisable(); + SysCtrlAonSync(); + + /* 15. If XOSC_HF was forced off above, initiate switch back */ + if (xosc_hf_active == true) { + configureXOSCHF(PowerCC26XX_ENABLE); + } + + /* 16. Re-enable interrupts */ + CPUcpsie(); + + /* + * 17. Signal all clients registered for late post-sleep + * notification + */ + lateNotifyStatus = notify(postEventLate); + + /* + * 18. Now clear the transition state before re-enabling + * scheduler + */ + PowerCC26X2_module.state = Power_ACTIVE; + + /* Re-enable Swi scheduling */ + SwiP_restore(swiKey); + + /* re-enable Task scheduling */ + PowerCC26XX_schedulerRestore(); + + /* if there was a notification error, set return status */ + if ((notifyStatus != Power_SOK) || + (lateNotifyStatus != Power_SOK)) { + status = Power_EFAIL; + } + } + } + + return (status); +} + +/* + * ======== Power_unregisterNotify ======== + * Unregister for a power notification. + * + */ +void Power_unregisterNotify(Power_NotifyObj * pNotifyObj) +{ + unsigned int key; + + /* remove notify object from its event queue */ + key = HwiP_disable(); + + /* remove notify object from its event queue */ + List_remove(&PowerCC26X2_module.notifyList, (List_Elem *)pNotifyObj); + + HwiP_restore(key); +} + +/* ****************** CC26XX specific APIs ******************** */ + +/* + * ======== PowerCC26XX_calibrate ======== + * Plug this function into the PowerCC26X2_Config structure + * if calibration is needed. + */ +bool PowerCC26XX_calibrate(unsigned int arg) +{ + bool retVal = false; + + switch (arg) { + case PowerCC26X2_INITIATE_CALIBRATE: + retVal = PowerCC26X2_initiateCalibration(); + break; + + case PowerCC26X2_DO_CALIBRATE: + PowerCC26X2_calibrate(); + break; + default: + while (1); + } + + return (retVal); +} + +/* + * ======== PowerCC26XX_doWFI ======== + */ +void PowerCC26XX_doWFI(void) +{ + __asm(" wfi"); +} + +/* + * ======== PowerCC26X2_getClockHandle ======== + */ +ClockP_Handle PowerCC26XX_getClockHandle() +{ + return ((ClockP_Handle)&PowerCC26X2_module.clockObj); +} + +/* + * ======== PowerCC26XX_noCalibrate ======== + * Plug this function into the PowerCC26X2 config structure if calibration + * is not needed. + */ +bool PowerCC26XX_noCalibrate(unsigned int arg) +{ + return (0); +} + +/* + * ======== PowerCC26XX_getXoscStartupTime ======== + * Get the estimated crystal oscillator startup time + */ +uint32_t PowerCC26XX_getXoscStartupTime(uint32_t timeUntilWakeupInMs) +{ + return (OSCHF_GetStartupTime(timeUntilWakeupInMs)); +} + +/* + * ======== PowerCC26X2_injectCalibration ======== + * Explicitly trigger RCOSC calibration + */ +bool PowerCC26XX_injectCalibration(void) +{ + if ((*(PowerCC26X2_config.calibrateFxn))(PowerCC26X2_INITIATE_CALIBRATE)) { + /* here if AUX SMPH was available, start calibration now ... */ + (*(PowerCC26X2_config.calibrateFxn))(PowerCC26X2_DO_CALIBRATE); + return (true); + } + + return (false); +} + +/* + * ======== PowerCC26XX_isStableXOSC_HF ======== + * Check if XOSC_HF has stabilized. + */ +bool PowerCC26XX_isStableXOSC_HF(void) +{ + bool ready = true; + unsigned int key; + + key = HwiP_disable(); + + /* only query if HF source is ready if there is a pending change */ + if (PowerCC26X2_module.xoscPending) { + ready = OSCHfSourceReady(); + } + + HwiP_restore(key); + + return (ready); +} + +/* + * ======== PowerCC26XX_switchXOSC_HF ======== + * Switch to enable XOSC_HF. + * May only be called when using the PowerCC26XX_SWITCH_XOSC_HF_MANUALLY + * constraint. + * May only be called after ensuring the XOSC_HF is stable by calling + * PowerCC26XX_isStableXOSC_HF(). + */ +void PowerCC26XX_switchXOSC_HF(void) +{ + bool readyToCal; + unsigned int key; + + key = HwiP_disable(); + + /* Since PowerCC26X2_isStableXOSC_HF() should have been called before this + * function, we can just switch without handling the case when the XOSC_HF + * is not ready or PowerCC26X2_module.xoscPending is not true. + */ + OSCHF_AttemptToSwitchToXosc(); + + /* Since configureXOSCHF() was called prior to this function to turn + * on the XOSC_HF, PowerCC26X2_module.xoscPending will be true and + * we can safely set it to false. + */ + PowerCC26X2_module.xoscPending = false; + + /* Allow going into IDLE again since we sucessfully switched + * to XOSC_HF + */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_IDLE); + + HwiP_restore(key); + + /* initiate RCOSC calibration */ + readyToCal = (*(PowerCC26X2_config.calibrateFxn))(PowerCC26X2_INITIATE_CALIBRATE); + + /* now notify clients that were waiting for a switch notification */ + notify(PowerCC26XX_XOSC_HF_SWITCHED); + + /* if ready to start first cal measurment, do it now */ + if (readyToCal == true) { + (*(PowerCC26X2_config.calibrateFxn))(PowerCC26X2_DO_CALIBRATE); + } +} + +/* * * * * * * * * * * internal and support functions * * * * * * * * * * */ + +/* + * ======== oscillatorISR ======== + */ +static void oscillatorISR(uintptr_t arg) +{ + uint32_t rawStatus = HWREG(PRCM_BASE + PRCM_O_OSCRIS); + uint32_t intStatusMask = HWREG(PRCM_BASE + PRCM_O_OSCIMSC); + + /* Turn off mask for all flags we will handle */ + HWREG(PRCM_BASE + PRCM_O_OSCIMSC) = intStatusMask & ~rawStatus; + + /* XOSC_LF or RCOSC_LF qualified */ + if (rawStatus & PRCM_OSCRIS_LFSRCDONERIS_M & intStatusMask) { + disableLFClockQualifiers(); + } + + /* XOSC_HF ready to switch to */ + if (rawStatus & PRCM_OSCIMSC_HFSRCPENDIM_M & intStatusMask) { + switchXOSCHF(); + } + + /* Clear flags we will handle. Does not really work as expected as + * the flags seem to level-detect and not edge-detect. Until the + * underlying trigger is taken care of, the flag will not deassert + * even when cleared. + * We're clearing at the end in order to prevent the flag from + * immediately asserting again if the underlying trigger was + * not handled yet. + * SCLK_LF switched can never be cleared after triggering + * only masked out. XOSC_HF ready to switch can be cleared + * after switching to XOSC_HF. + */ + HWREG(PRCM_BASE + PRCM_O_OSCICR) = intStatusMask & rawStatus; +} + +/* + * ======== emptyClockFunc ======== + * Clock function used by power policy to schedule early wakeups. + */ +static void emptyClockFunc(uintptr_t arg) +{ +} + +/* + * ======== disableLFClockQualifiers ======== + * Clock function used for delayed disable of LF clock qualifiers. + */ +static void disableLFClockQualifiers(void) +{ + uint32_t sourceLF; + + /* query LF clock source */ + sourceLF = OSCClockSourceGet(OSC_SRC_CLK_LF); + + /* is LF source either RCOSC_LF or XOSC_LF yet? */ + if ((sourceLF == OSC_RCOSC_LF) || (sourceLF == OSC_XOSC_LF)) { + + /* yes, disable the LF clock qualifiers */ + DDI16BitfieldWrite( + AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M| + DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M, + DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S, + 0x3 + ); + + /* enable clock loss detection */ + OSCClockLossEventEnable(); + + /* now finish by releasing the standby disallow constraint */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + else if(sourceLF == OSC_XOSC_HF) { + /* yes, disable the LF clock qualifiers */ + DDI16BitfieldWrite( + AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M| + DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M, + DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S, + 0x3 + ); + + /* enable clock loss detection */ + OSCClockLossEventEnable(); + + /* do not allow standby since the LF clock is HF derived */ + } + +} + +/* + * ======== nopResourceFunc ======== + * special resource handler + */ +static unsigned int nopResourceHandler(unsigned int action) +{ + return (0); +} + +/* + * ======== notify ======== + * Send notifications to registered clients. + * Note: Task scheduling is disabled when this function is called. + */ +static int_fast16_t notify(uint_fast16_t eventType) +{ + int_fast16_t notifyStatus; + Power_NotifyFxn notifyFxn; + uintptr_t clientArg; + List_Elem *elem; + + /* if queue is empty, return immediately */ + if (!List_empty(&PowerCC26X2_module.notifyList)) { + /* point to first client notify object */ + elem = List_head(&PowerCC26X2_module.notifyList); + + /* walk the queue and notify each registered client of the event */ + do { + if (((Power_NotifyObj *)elem)->eventTypes & eventType) { + /* pull params from notify object */ + notifyFxn = ((Power_NotifyObj *)elem)->notifyFxn; + clientArg = ((Power_NotifyObj *)elem)->clientArg; + + /* call the client's notification function */ + notifyStatus = (int_fast16_t)(*(Power_NotifyFxn)notifyFxn)( + eventType, 0, clientArg); + + /* if client declared error stop all further notifications */ + if (notifyStatus != Power_NOTIFYDONE) { + return (Power_EFAIL); + } + } + + /* get next element in the notification queue */ + elem = List_next(elem); + + } while (elem != NULL); + } + + return (Power_SOK); +} + +/* + * ======== configureRFCoreClocks ======== + * Special dependency function for controlling RF core clocks. + */ +static unsigned int configureRFCoreClocks(unsigned int action) +{ + if (action == PowerCC26XX_ENABLE) { + RFCClockEnable(); + } + else { + RFCClockDisable(); + } + + return (0); +} + +/* + * ======== switchXOSCHF ======== + * Switching to XOSC_HF when it has stabilized. + */ +static void switchXOSCHF(void) +{ + bool readyToCal; + unsigned int key; + + key = HwiP_disable(); + + /* Switch to the XOSC_HF. Since this function is only called + * after we get an interrupt signifying it is ready to switch, + * it should always succeed. + * If it does not succeed, try again. It is fine if we spin, + * there is no sensible recovery mechanism from such an error. + */ + while (!OSCHF_AttemptToSwitchToXosc()); + + /* The only time we should get here is when PowerCC26X2_module.xoscPending == true + * holds. + * Allow going into IDLE again since we sucessfully switched + * to XOSC_HF + */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_IDLE); + + PowerCC26X2_module.xoscPending = false; + + + HwiP_restore(key); + + /* initiate RCOSC calibration */ + readyToCal = (*(PowerCC26X2_config.calibrateFxn))(PowerCC26X2_INITIATE_CALIBRATE); + + /* now notify clients that were waiting for a switch notification */ + notify(PowerCC26XX_XOSC_HF_SWITCHED); + + /* if ready to start first cal measurment, do it now */ + if (readyToCal == true) { + (*(PowerCC26X2_config.calibrateFxn))(PowerCC26X2_DO_CALIBRATE); + } +} + +/* + * ======== configureXOSCHF ======== + */ +static unsigned int configureXOSCHF(unsigned int action) +{ + /* By checking action == PowerCC26XX_ENABLE and PowerCC26X2_module.xoscPending + * carefully, the function should be idempotent. Calling it with the same + * action more than once will not have any effect until the hardware triggers + * a software state change. + */ + if (action == PowerCC26XX_ENABLE && + OSCClockSourceGet(OSC_SRC_CLK_HF) != OSC_XOSC_HF && + PowerCC26X2_module.xoscPending == false) { + + OSCHF_TurnOnXosc(); + + PowerCC26X2_module.xoscPending = true; + + /* Unless it is disallowed, unmask the XOSC_HF ready to switch flag */ + if (!(Power_getConstraintMask() & (1 << PowerCC26XX_SWITCH_XOSC_HF_MANUALLY))) { + + /* Clearing the flag in the ISR does not always work. Clear it again just in case */ + HWREG(PRCM_BASE + PRCM_O_OSCICR) = PRCM_OSCICR_HFSRCPENDC_M; + + /* Turn on oscillator interrupt for SCLK_HF switching */ + HWREG(PRCM_BASE + PRCM_O_OSCIMSC) |= PRCM_OSCIMSC_HFSRCPENDIM_M; + } + + /* If the device goes into IDLE in between turning on XOSC_HF and + * and switching SCLK_HF to XOSC_HF, the INT_OSC_COMB HFSRCPEND + * trigger will be suppressed. + * The DISALLOW_IDLE constraint should only ever be set whenever + * we transition from xoscPending == false to true. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_IDLE); + } + + /* when release XOSC_HF, auto switch to RCOSC_HF */ + else if (action == PowerCC26XX_DISABLE) { + OSCHF_SwitchToRcOscTurnOffXosc(); + + /* If we have not actually switched to XOSC_HF yet, we need to + * undo what we did above when turning on XOSC_HF. Otherwise, + * we may not balance the constraints correctly or get + * unexpected interrupts. + */ + if (PowerCC26X2_module.xoscPending) { + /* Remove HFSRCPEND from the OSC_COMB interrupt mask */ + uint32_t oscMask = HWREG(PRCM_BASE + PRCM_O_OSCIMSC); + HWREG(PRCM_BASE + PRCM_O_OSCIMSC) = oscMask & ~ PRCM_OSCIMSC_HFSRCPENDIM_M; + + /* Clear any residual trigger for HFSRCPEND */ + HWREG(PRCM_BASE + PRCM_O_OSCICR) = PRCM_OSCICR_HFSRCPENDC; + + Power_releaseConstraint(PowerCC26XX_DISALLOW_IDLE); + + PowerCC26X2_module.xoscPending = false; + } + } + return (0); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26X2.h new file mode 100644 index 0000000..8804cad --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26X2.h @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQueueNTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file PowerCC26X2.h + * + * @brief Power manager interface for CC26X2 + * + * The Power header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref Power.h for a complete description of APIs. + * + * ## Implementation # + * This header file defines the power resources, constraints, events, sleep + * states and transition latencies for CC26X2. + * + * ============================================================================ + */ + +#ifndef ti_drivers_power_PowerCC26X2_ +#define ti_drivers_power_PowerCC26X2_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +/*! The latency to reserve for resume from STANDBY (usec). */ +#define PowerCC26X2_RESUMETIMESTANDBY 750 + +/*! The total latency to reserve for entry to and exit from STANDBY (usec). */ +#define PowerCC26X2_TOTALTIMESTANDBY 1000 + +/*! The initial delay when waking from STANDBY (usec). */ +#define PowerCC26X2_WAKEDELAYSTANDBY 240 + +/*! The initial wait time (usec) before checking if RCOSC_LF is stable. */ +#define PowerCC26X2_INITIALWAITRCOSC_LF 1000 + +/*! The retry wait time (usec) when checking to see if RCOSC_LF is stable. */ +#define PowerCC26X2_RETRYWAITRCOSC_LF 1000 + +/*! The initial wait time (usec) before checking if XOSC_HF is stable. */ +#define PowerCC26X2_INITIALWAITXOSC_HF 50 + +/*! The retry wait time (usec) when checking to see if XOSC_HF is stable. */ +#define PowerCC26X2_RETRYWAITXOSC_HF 50 + +/*! The initial wait time (usec) before checking if XOSC_LF is stable. */ +#define PowerCC26X2_INITIALWAITXOSC_LF 10000 + +/*! The retry wait time (usec) when checking to see if XOSC_LF is stable. */ +#define PowerCC26X2_RETRYWAITXOSC_LF 5000 + +#define PowerCC26X2_PERIPH_PKA PowerCC26XX_NUMRESOURCES /*!< Resource ID: PKA Module */ + +#define PowerCC26X2_PERIPH_UART1 PowerCC26XX_NUMRESOURCES + 1 /*!< Resource ID: UART1 */ + +/* \cond */ +#define PowerCC26X2_NUMRESOURCES (PowerCC26XX_NUMRESOURCES + 2) /* Number of resources in database */ +/* \endcond */ + +/* \cond */ +#define PowerCC26X2_NUMCONSTRAINTS (PowerCC26XX_NUMCONSTRAINTS + 0) /* Number of constraints supported */ +/* \endcond */ + +/* \cond */ +/* + * Calibration stages + */ +#define PowerCC26X2_SETUP_CALIBRATE 1 +#define PowerCC26X2_INITIATE_CALIBRATE 2 +#define PowerCC26X2_DO_CALIBRATE 3 +/* \endcond */ + + +/*! @brief Global configuration structure */ +typedef struct PowerCC26X2_Config { + /*! + * @brief The Power Policy's initialization function + * + * If the policy does not have an initialization function, 'NULL' + * should be specified. + */ + Power_PolicyInitFxn policyInitFxn; + /*! + * @brief The Power Policy function + * + * When enabled, this function is invoked in the idle loop, to + * opportunistically select and activate sleep states. + * + * Two reference policies are provided: + * + * PowerCC26X2_doWFI() - a simple policy that invokes CPU wait for + * interrupt (WFI) + * + * PowerCC26X2_standbyPolicy() - an agressive policy that considers + * constraints, time until next scheduled work, and sleep state + * latencies, and optionally puts the device into the STANDBY state, + * the IDLE state, or as a minimum, WFI. + * + * Custom policies can be written, and specified via this function pointer. + * + * In addition to this static selection, the Power Policy can be + * dynamically changed at runtime, via the Power_setPolicy() API. + */ + Power_PolicyFxn policyFxn; + /*! + * @brief The function to be used for activating RC Oscillator (RCOSC) + * calibration + * + * Calibration is normally enabled, via specification of the function + * PowerCC26X2_calibrate(). This enables high accuracy operation, and + * faster high frequency crystal oscillator (XOSC_HF) startups. + * + * To disable RCOSC calibration, the function PowerCC26X2_noCalibrate() + * should be specified. + */ + bool (*calibrateFxn)(unsigned int); + /*! + * @brief Boolean specifying if the Power Policy function is enabled + * + * If 'true', the policy function will be invoked once for each pass + * of the idle loop. + * + * If 'false', the policy will not be invoked. + * + * In addition to this static setting, the power policy can be dynamically + * enabled and disabled at runtime, via the Power_enablePolicy() and + * Power_disablePolicy() functions, respectively. + */ + bool enablePolicy; + /*! + * @brief Boolean specifying whether the low frequency RC oscillator + * (RCOSC_LF) should be calibrated. + * + * If RCOSC calibration is enabled (above, via specification of + * an appropriate calibrateFxn), this Boolean specifies whether + * RCOSC_LF should be calibrated. + */ + bool calibrateRCOSC_LF; + /*! + * @brief Boolean specifying whether the high frequency RC oscillator + * (RCOSC_HF) should be calibrated. + * + * If RCOSC calibration is enabled (above, via specification of + * an appropriate calibrateFxn), this Boolean specifies whether + * RCOSC_HF should be calibrated. + */ + bool calibrateRCOSC_HF; +} PowerCC26X2_Config; + +/*! + * @brief PowerCC26X2_ModuleState + * + * Power manager state structure. The application must not access any members + * of this structure! + */ +typedef struct PowerCC26X2_ModuleState { + List_List notifyList; /*!< Event notification list */ + uint32_t constraintMask; /*!< Aggregate constraints mask */ + ClockP_Struct clockObj; /*!< Clock object for scheduling wakeups */ + ClockP_Struct calibrationClock; /*!< Clock object for scheduling wakeups */ + HwiP_Struct oscHwi; /*!< Hwi object for oscillator stabilisation */ + HwiP_Struct tdcHwi; /*!< Hwi object for RCOSC calibration */ + int32_t nDeltaFreqCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimFractCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimNew; /*!< RCOSC calibration variable */ + int32_t nCtrimFractNew; /*!< RCOSC calibration variable */ + int32_t nRtrimNew; /*!< RCOSC calibration variable */ + int32_t nRtrimCurr; /*!< RCOSC calibration variable */ + int32_t nDeltaFreqNew; /*!< RCOSC calibration variable */ + bool bRefine; /*!< RCOSC calibration variable */ + uint32_t state; /*!< Current transition state */ + bool xoscPending; /*!< Is XOSC_HF activation in progress? */ + bool calLF; /*!< Calibrate RCOSC_LF? */ + uint8_t auxHwiState; /*!< The AUX ISR calibration state */ + bool busyCal; /*!< Already busy calibrating? */ + uint32_t calStep; /*!< The current calibration step */ + bool firstLF; /*!< Is this the first LF calibration? */ + bool enablePolicy; /*!< Is the Power policy enabled? */ + bool initialized; /*!< Has Power_init() been called? */ + uint8_t constraintCounts[PowerCC26X2_NUMCONSTRAINTS]; + /*!< Array to maintain constraint reference counts */ + uint8_t resourceCounts[PowerCC26X2_NUMRESOURCES]; + /*!< Array to maintain resource dependency reference counts */ + unsigned int (*resourceHandlers[3])(unsigned int); + /*!< Array of special dependency handler functions */ + Power_PolicyFxn policyFxn; /*!< The Power policy function */ +} PowerCC26X2_ModuleState; + + +#ifdef __cplusplus +} +#endif + +#endif /* POWER_CC26X2_ */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26X2_calibrateRCOSC.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26X2_calibrateRCOSC.c new file mode 100644 index 0000000..45f6bb3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26X2_calibrateRCOSC.c @@ -0,0 +1,791 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQueueNTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC26X2_calibrateRCOSC.c ======== + */ + +#include + +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_aux_evctl.h) +#include DeviceFamily_constructPath(inc/hw_aux_smph.h) +#include DeviceFamily_constructPath(inc/hw_aux_sysif.h) +#include DeviceFamily_constructPath(inc/hw_aux_tdc.h) +#include DeviceFamily_constructPath(inc/hw_ddi_0_osc.h) +#include DeviceFamily_constructPath(inc/hw_ddi.h) +#include DeviceFamily_constructPath(driverlib/aon_batmon.h) +#include DeviceFamily_constructPath(driverlib/ddi.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/osc.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) + +#define AUX_TDC_SEMAPHORE_NUMBER 1 /* semaphore 1 protects TDC */ +#define NUM_RCOSC_LF_PERIODS_TO_MEASURE 32 /* x RCOSC_LF periods vs XOSC_HF */ +#define NUM_RCOSC_HF_PERIODS_TO_MEASURE 1 /* x RCOSC_HF periods vs XOSC_HF */ +#define ACLK_REF_SRC_RCOSC_HF 0 /* Use RCOSC_HF for ACLK REF */ +#define ACLK_REF_SRC_RCOSC_LF 2 /* Use RCOSC_LF for ACLK REF */ +#define SCLK_LF_OPTION_RCOSC_LF 3 /* defined in cc26_ccfg.xls */ +#define RCOSC_HF_LOW_THRESHOLD_TDC_VALUE 1535 /* If TDC value is within threshold range, no need for another TDC measurement */ +#define RCOSC_HF_PERFECT_TDC_VALUE 1536 /* RCOSC_HF runs at perfect 48 MHz when ending up with this TDC value */ +#define RCOSC_HF_HIGH_THRESHOLD_TDC_VALUE 1537 /* If TDC value is within threshold range, no need for another TDC measurement */ + +#define DDI_0_OSC_O_CTL1_LOCAL 0x00000004 /* offset */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M 0x007C0000 /* mask */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S 18 /* shift */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_M 0x00020000 /* mask */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_S 17 /* shift */ +#define DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M 0x00000C00 /* offset */ +#define DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S 10 /* shift */ + +/* AUX ISR states */ +#define WAIT_SMPH 0 /* just took SMPH, start RCOSC_LF */ +#define CAL_RCOSC_LF 1 /* just finished RCOSC_LF, start first RCOSC_HF */ +#define CAL_RCOSC_HF1 2 /* just finished 1st RCOSC_HF, start 2nd */ +#define CAL_RCOSC_HF2 3 /* just finished 2nd RCOSC_HF, decide best */ + +/* calibration states */ +#define PowerCC26X2_STATE_TDC_INIT 0 +#define PowerCC26X2_STATE_CAL_LF_1 1 +#define PowerCC26X2_STATE_CAL_LF_2 2 +#define PowerCC26X2_STATE_CAL_HF1_1 3 +#define PowerCC26X2_STATE_CAL_HF1_2 4 +#define PowerCC26X2_STATE_CAL_HF2 5 +#define PowerCC26X2_STATE_CLEANUP 6 + +/* FSM results */ +typedef enum PowerCC26X2_FsmResult_ { + PowerCC26X2_FSM_RESULT_RUN_FSM, + PowerCC26X2_FSM_RESULT_WAIT_FOR_TDC, + PowerCC26X2_FSM_RESULT_DONE, + PowerCC26X2_FSM_RESULT_ERROR, +} PowerCC26X2_FsmResult; + +/* macros */ +#define Min(a,b) (((a)<(b))?(a):(b)) +#define Max(a,b) (((a)>(b))?(a):(b)) +#define Abs(x) ((x) < 0 ? -(x) : (x)) +#define Scale_rndInf(x) ((3 * (x) + (((x) < 0) ? -2 : 2)) / 4) + +#ifndef PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + #define PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION 0 +#endif + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION +volatile unsigned int gotSEM = 0; +volatile unsigned int calLFi = 0; +volatile unsigned int calHF1i = 0; +volatile unsigned int calHF2i = 0; +volatile bool doneCal = false; +unsigned int tdcResult_LF = 0; +unsigned int tdcResult_HF1 = 0; +unsigned int tdcResult_HF2 = 0; +unsigned int numISRs = 0; +#endif + +/* Forward declarations */ +static bool getTdcSemaphore(); +static void updateSubSecInc(uint32_t tdcResult); +static void calibrateRcoscHf1(int32_t tdcResult); +static void calibrateRcoscHf2(int32_t tdcResult); +static PowerCC26X2_FsmResult runCalibrateFsm(void); +void PowerCC26X2_calibrate(void); +void PowerCC26X2_RCOSC_clockFunc(uintptr_t arg); + +/* Externs */ +extern PowerCC26X2_ModuleState PowerCC26X2_module; +extern const PowerCC26X2_Config PowerCC26X2_config; + +/* + * ======== PowerCC26X2_initiateCalibration ======== + * Initiate calibration of RCOSC_LF and RCOSCHF + */ +bool PowerCC26X2_initiateCalibration() +{ + unsigned int hwiKey; + bool busy = false; + bool status; + bool gotSem; + + if ((PowerCC26X2_module.calLF == false) && + (PowerCC26X2_config.calibrateRCOSC_HF == false)) { + return (false); + } + + /* make sure calibration is not already in progress */ + hwiKey = HwiP_disable(); + + if (PowerCC26X2_module.busyCal == false) { + PowerCC26X2_module.busyCal = true; + } + else { + busy = true; + } + + HwiP_restore(hwiKey); + + if (busy == true) { + return (false); + } + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + gotSEM = 0; + calLFi = 0; + calHF1i = 0; + calHF2i = 0; + doneCal = false; +#endif + + /* set contraint to prohibit standby during calibration sequence */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* set dependency to keep XOSC_HF active during calibration sequence */ + Power_setDependency(PowerCC26XX_XOSC_HF); + + /* initiate acquisition of semaphore protecting TDC */ + gotSem = getTdcSemaphore(); + + /* if didn't acquire semaphore, must wait for autotake ISR */ + if (gotSem == false) { + PowerCC26X2_module.auxHwiState = WAIT_SMPH; + status = false; /* false: don't do anything else until acquire SMPH */ + } + + /* else, semaphore acquired, OK to proceed with first measurement */ + else { +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + gotSEM = 1; +#endif + status = true; /* true: OK to start first measurement */ + } + + return (status); +} + +/* + * ======== PowerCC26X2_auxISR ======== + * ISR for the AUX combo interrupt event. Implements Hwi state machine to + * step through the RCOSC calibration steps. + */ +void PowerCC26X2_auxISR(uintptr_t arg) +{ + uint32_t tdcResult; + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + numISRs++; +#endif + + /* + * disable all events that are part of AUX_COMBINED_INTERRUPT. + * This interrupt is reserved for use during RCOSC calibration. + * Other AUX perihperals that want to generate interrupts to CM3 + * must use dedicated interrupt lines or go through AON combined. + */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = 0; + + /* ****** state = WAIT_SMPH: arrive here if just took the SMPH ****** */ + if (PowerCC26X2_module.auxHwiState == WAIT_SMPH) { +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + gotSEM = 1; +#endif + } + + /* **** state = CAL_RCOSC_LF: here when just finished LF counting **** */ + else if (PowerCC26X2_module.auxHwiState == CAL_RCOSC_LF) { + + tdcResult = HWREG(AUX_TDC_BASE + AUX_TDC_O_RESULT); + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + tdcResult_LF = tdcResult; +#endif + /* update the RTC SUBSECINC register based on LF measurement result */ + updateSubSecInc(tdcResult); +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + calLFi = 1; +#endif + /* if doing HF calibration initiate it now */ + if (PowerCC26X2_config.calibrateRCOSC_HF) { + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CAL_LF_2; /* next: trigger LF */ + } + + /* else, start cleanup */ + else { + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CLEANUP; /* next: cleanup */ + } + } + + /* ****** state = CAL_RCOSC_HF1: here when just finished 1st RCOSC_HF */ + else if (PowerCC26X2_module.auxHwiState == CAL_RCOSC_HF1) { + + tdcResult = HWREG(AUX_TDC_BASE + AUX_TDC_O_RESULT); + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + tdcResult_HF1 = tdcResult; + calHF1i = 1; +#endif + + /* use first HF measurement to setup new trim values */ + calibrateRcoscHf1(tdcResult); + + /* if HF setting perfect, nothing more to do, calibration is done */ + if ((tdcResult >= RCOSC_HF_LOW_THRESHOLD_TDC_VALUE) && + (tdcResult <= RCOSC_HF_HIGH_THRESHOLD_TDC_VALUE)) { + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CLEANUP; /* next: cleanup */ + } + + /* else, tweak trims, initiate another HF measurement */ + else { + + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CAL_HF1_2; /* next: HF meas. #2 */ + } + } + + /* ****** state = just finished second RCOSC_HF measurement ****** */ + else if (PowerCC26X2_module.auxHwiState == CAL_RCOSC_HF2) { + + tdcResult = HWREG(AUX_TDC_BASE + AUX_TDC_O_RESULT); + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + tdcResult_HF2 = tdcResult; +#endif + /* look for improvement on #2, else revert to previous trim values */ + calibrateRcoscHf2(tdcResult); + + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CLEANUP; /* next: cleanup */ + } + + /* do the next calibration step... */ + PowerCC26X2_calibrate(); +} + +/* + * ======== PowerCC26X2_calibrate ======== + */ +void PowerCC26X2_calibrate(void) +{ + PowerCC26X2_FsmResult fsmResult; + + do { + fsmResult = runCalibrateFsm(); + } while (fsmResult == PowerCC26X2_FSM_RESULT_RUN_FSM); + + switch (fsmResult) { + case PowerCC26X2_FSM_RESULT_WAIT_FOR_TDC: + /* Intentional fall-through */ + case PowerCC26X2_FSM_RESULT_DONE: + /* Do nothing. Calibration is complete or the + * TDC harware will execute in the background + * and continue the operation. */ + break; + default: + /* Something went wrong. No good way to recover. */ + while(1); + } +} + +/* + * ======== runCalibrateFsm ======== + * Execute one state of the clock calibration FSM. + */ +static PowerCC26X2_FsmResult runCalibrateFsm(void) { + + switch (PowerCC26X2_module.calStep) { + + case PowerCC26X2_STATE_TDC_INIT: + + /* Turn on TDC clock */ + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCCLKCTL) = AUX_SYSIF_TDCCLKCTL_REQ; + + /* set saturation config to 2^24 */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_SATCFG) = AUX_TDC_SATCFG_LIMIT_R24; + + /* set start and stop trigger sources and polarity */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGSRC) = + (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF | + AUX_TDC_TRIGSRC_STOP_POL_HIGH) | + (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF | + AUX_TDC_TRIGSRC_START_POL_HIGH); + + /* set TDC_SRC clock to be XOSC_HF/2 = 24 MHz */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S, 2); + + /* read back to ensure no race condition between OSC_DIG and AUX_SYSIF */ + DDI16BitfieldRead(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S); + + /* set AUX_SYSIF:TDCCLKCTL.REQ... */ + HWREG(AUX_SYSIF_BASE +AUX_SYSIF_O_TDCCLKCTL) = AUX_SYSIF_TDCCLKCTL_REQ; + + /* finish wait for AUX_SYSIF:TDCCLKCTL.ACK to be set ... */ + while(!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCCLKCTL) & + AUX_SYSIF_TDCCLKCTL_ACK)); + + /* Enable trig count */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGCNTCFG) = AUX_TDC_TRIGCNTCFG_EN; + + /* if LF calibration enabled start LF measurement */ + if (PowerCC26X2_module.calLF) { + + /* clear UPD_REQ, new sub-second increment is NOT available */ + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL) = 0; + + /* set next Swi state */ + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CAL_LF_1; + } + + /* else, start first HF measurement */ + else { + /* set next Swi state */ + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CAL_HF1_1; + } + + /* abort TDC */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_ABORT; + + /* clear AUX_SYSIFTDCREFCLKCTL.REQ... */ + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCREFCLKCTL) = 0; + + /* finish wait for AUX_SYSIFTDCREFCLKCTL.ACK to be cleared ... */ + while(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCREFCLKCTL) & AUX_SYSIF_TDCREFCLKCTL_ACK); + + return PowerCC26X2_FSM_RESULT_RUN_FSM; + + case PowerCC26X2_STATE_CAL_LF_1: + + /* set next Hwi state before triggering TDC */ + PowerCC26X2_module.auxHwiState = CAL_RCOSC_LF; + + /* set the ACLK reference clock */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S, + ACLK_REF_SRC_RCOSC_LF); + + /* set AUX_SYSIFTDCREFCLKCTL.REQ */ + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCREFCLKCTL) = AUX_SYSIF_TDCREFCLKCTL_REQ; + + /* Delay for ~110us total until TDCRECLKCTL_ACK is ready */ + ClockP_start(ClockP_handle(&PowerCC26X2_module.calibrationClock)); + + return PowerCC26X2_FSM_RESULT_WAIT_FOR_TDC; + + case PowerCC26X2_STATE_CAL_LF_2: + + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CAL_HF1_1; + + /* clear AUX_SYSIFTDCREFCLKCTL.REQ... */ + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCREFCLKCTL) = 0; + + /* wait for AUX_SYSIFTDCREFCLKCTL.ACK to be cleared ... */ + while(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCREFCLKCTL) & AUX_SYSIF_TDCREFCLKCTL_ACK); + + return PowerCC26X2_FSM_RESULT_RUN_FSM; + + case PowerCC26X2_STATE_CAL_HF1_1: + + PowerCC26X2_module.auxHwiState = CAL_RCOSC_HF1; + + /* set the ACLK reference clock */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S, + ACLK_REF_SRC_RCOSC_HF); + + /* read back to ensure no race condition between OSC_DIG and AUX_SYSIF */ + DDI16BitfieldRead(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M); + + /* set AUX_SYSIFTDCREFCLKCTL.REQ */ + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCREFCLKCTL) = AUX_SYSIF_TDCREFCLKCTL_REQ; + + /* Delay for ~110us total until TDCRECLKCTL_ACK is ready */ + ClockP_start(ClockP_handle(&PowerCC26X2_module.calibrationClock)); + + return PowerCC26X2_FSM_RESULT_WAIT_FOR_TDC; + + case PowerCC26X2_STATE_CAL_HF1_2: + + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CAL_HF2; + + /* clear AUX_SYSIFTDCREFCLKCTL.REQ... */ + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCREFCLKCTL) = 0; + + /* wait for AUX_SYSIFTDCREFCLKCTL.ACK to be cleared ... */ + while(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCREFCLKCTL) & AUX_SYSIF_TDCREFCLKCTL_ACK); + + return PowerCC26X2_FSM_RESULT_RUN_FSM; + + case PowerCC26X2_STATE_CAL_HF2: + + PowerCC26X2_module.auxHwiState = CAL_RCOSC_HF2; + + /* set the ACLK reference clock */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S, + ACLK_REF_SRC_RCOSC_HF); + + /* read back to ensure no race condition between OSC_DIG and AUX_SYSIF */ + DDI16BitfieldRead(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M); + + /* set AUX_SYSIFTDCREFCLKCTL.REQ */ + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCREFCLKCTL) = AUX_SYSIF_TDCREFCLKCTL_REQ; + + /* Delay for ~110us total until TDCRECLKCTL_ACK is ready */ + ClockP_start(ClockP_handle(&PowerCC26X2_module.calibrationClock)); + + return PowerCC26X2_FSM_RESULT_WAIT_FOR_TDC; + + case PowerCC26X2_STATE_CLEANUP: + + /* release the TDC clock request */ + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCCLKCTL) = 0; + + /* release the TDC reference clock request */ + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCREFCLKCTL) = 0; + + /* wait for AUX_SYSIF:TDCCLKCTL.ACK to be cleared ... */ + while ((HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCCLKCTL) & + AUX_SYSIF_TDCCLKCTL_ACK)); + /* wait for AUX_SYSIFTDCREFCLKCTL.ACK to be cleared ... */ + while(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCREFCLKCTL) & + AUX_SYSIF_TDCREFCLKCTL_ACK); + + /* + * Disable all interrupts as part of AUX_COMBINED interrupt + * Once we release semaphore, the sensor controller is allowed + * to use the TDC. When it does, we must ensure that this + * does not cause any unexpected interrupts to the CM3. + */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = 0; + + /* release AUX semaphore */ + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH1) = 1; + + /* release the power down constraints and XOSC_HF dependency */ + Power_releaseDependency(PowerCC26XX_XOSC_HF); + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* set next state */ + PowerCC26X2_module.calStep = PowerCC26X2_STATE_TDC_INIT; + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + doneCal = true; + calHF2i = 1; +#endif + PowerCC26X2_module.busyCal = false; + + return PowerCC26X2_FSM_RESULT_DONE; + + default: + return PowerCC26X2_FSM_RESULT_ERROR; + } +} + +void PowerCC26X2_RCOSC_clockFunc(uintptr_t arg) { + + /* Wait any remaining time for TDCREFCLKCTL_ACK. Should not spin here at all. */ + while(!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_TDCREFCLKCTL) & AUX_SYSIF_TDCREFCLKCTL_ACK)); + + /* Set number of periods of ACLK to count */ + if (PowerCC26X2_module.calStep == PowerCC26X2_STATE_CAL_LF_1) { + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGCNTLOAD) = NUM_RCOSC_LF_PERIODS_TO_MEASURE; + } + else { + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGCNTLOAD) = NUM_RCOSC_HF_PERIODS_TO_MEASURE; + } + + /* Reset/clear result of TDC */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_CLR_RESULT; + + /* Clear possible pending interrupt source */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE; + + /* Enable TDC done interrupt as part of AUX_COMBINED interrupt */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE; + + /* Run TDC (start synchronously) */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_RUN_SYNC_START; +} + +/* + * ======== getTdcSemaphore ======== + * Get TDC semaphore (number 1) + */ +static bool getTdcSemaphore() +{ + unsigned int own; + + /* try to acquire SMPH */ + own = HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH1); + + /* if acquired SMPH: done */ + if (own != 0) { + return (true); + } + + /* clear the interrupt source, can only be cleared when we don't have semaphore */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE; + + /* + * else, did not acquire the semaphore, enable SMPH_AUTOTAKE_DONE event + * (don't OR, write entire register, no other interrupts can be enabled!) + */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE; + + /* start AUTOTAKE of semaphore for TDC access */ + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_AUTOTAKE) = AUX_TDC_SEMAPHORE_NUMBER; + + return (false); +} + +/* + * ======== updateSubSecInc ======== + * Update the SUBSECINC register based on measured RCOSC_LF frequency + */ +static void updateSubSecInc(uint32_t tdcResult) +{ + int32_t newSubSecInc; + uint32_t oldSubSecInc; + uint32_t subSecInc; + int32_t hposcOffset; + int32_t hposcOffsetInv; + + /* + * Calculate the new SUBSECINC + * Here's the formula: AON_RTC:SUBSECINC = (45813 * NR) / 256 + * Based on measuring 32 LF clock periods + */ + newSubSecInc = (45813 * tdcResult) / 256; + + /* Compensate HPOSC drift if HPOSC is in use */ + if(OSC_IsHPOSCEnabled()) { + /* Get the HPOSC relative offset at this temperature */ + hposcOffset = OSC_HPOSCRelativeFrequencyOffsetGet(AONBatMonTemperatureGetDegC()); + /* Convert to RF core format */ + hposcOffsetInv = OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(hposcOffset); + /* Adjust SUBSECINC */ + newSubSecInc += (((newSubSecInc >> 4) * (hposcOffsetInv >> 3)) >> 15); + } + + /* Apply filter, but not for first calibration */ + if (PowerCC26X2_module.firstLF) { + /* Don't apply filter first time, to converge faster */ + subSecInc = newSubSecInc; + /* No longer first measurement */ + PowerCC26X2_module.firstLF = false; + } + else { + /* Read old SUBSECINC value */ + oldSubSecInc = HWREG(AON_RTC_BASE + AON_RTC_O_SUBSECINC) & 0x00FFFFFF; + /* Apply filter, 0.5 times old value, 0.5 times new value */ + subSecInc = (oldSubSecInc * 1 + newSubSecInc * 1) / 2; + } + + /* Update SUBSECINC values */ + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC0) = subSecInc; + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC1) = subSecInc >> 16; + + /* update to use new values */ + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL) = AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ; +} + +/* + * ======== PowerCC26X2_calibrateRcoscHf1 ======== + * Calibrate RCOSC_HF agains XOSC_HF: compute and setup new trims + */ +static void calibrateRcoscHf1(int32_t tdcResult) +{ + /* *** STEP 1: Find RCOSC_HF-XOSC_HF frequency offset with current trim settings */ + /* Read in current trim settings */ + PowerCC26X2_module.nCtrimCurr = + (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RCOSCHFCTL) & + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M) >> + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S; + + PowerCC26X2_module.nCtrimFractCurr = + (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL1_LOCAL) + & DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M) >> + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S; + + PowerCC26X2_module.nRtrimCurr = + (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ATESTCTL) + & DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M) >> + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S; + + + /* + * Find RCOSC_HF-XOSC_HF frequency offset with current trim settings + * Positive value => RCOSC_HF runs slow, CTRIM(FRACT) should be increased + * Negative value => RCOSC_HF runs fast, CTRIM(FRACT) should be decreased + * Resolution: 31.25 kHz; CTRIMFRACT resolution ~30 kHz + */ + PowerCC26X2_module.nDeltaFreqCurr = (int32_t) tdcResult - RCOSC_HF_PERFECT_TDC_VALUE; + + /* *** STEP 2: Attempt to calculate more optimal settings */ + if (PowerCC26X2_module.nDeltaFreqCurr == 0) { + /* If perfect, don't perform second measurement and keep current settings */ + PowerCC26X2_module.bRefine = false; + return; + } + if (PowerCC26X2_module.bRefine) { + /* + * Trying to find better match across CTRIM/RTRIM. Due to mismatches the + * first try might not have been more optimal than the current setting. + * Continue refining, starting from stored values + */ + } else { + /* Start from current values */ + PowerCC26X2_module.nCtrimFractNew = PowerCC26X2_module.nCtrimFractCurr; + PowerCC26X2_module.nCtrimNew = PowerCC26X2_module.nCtrimCurr; + PowerCC26X2_module.nRtrimNew = PowerCC26X2_module.nRtrimCurr; + PowerCC26X2_module.nDeltaFreqNew = PowerCC26X2_module.nDeltaFreqCurr; + } + + /* + * Calculate change to CTRIMFRACT with safe assumptions of gain, + * apply delta to current CTRIMFRACT and convert to valid CTRIM/CTRIMFRACT + */ + PowerCC26X2_module.nCtrimFractNew = PowerCC26X2_module.nCtrimFractNew + + Scale_rndInf(PowerCC26X2_module.nDeltaFreqNew); + PowerCC26X2_module.nCtrimNew = PowerCC26X2_module.nCtrimCurr; + + /* One step of CTRIM is about 500 kHz, so limit to one CTRIM step */ + if (PowerCC26X2_module.nCtrimFractNew < 1) { + if (PowerCC26X2_module.nRtrimNew == 3) { + /* We try the slow RTRIM in this CTRIM first */ + PowerCC26X2_module.nCtrimFractNew = Max(1, PowerCC26X2_module.nCtrimFractNew + 21); + PowerCC26X2_module.nRtrimNew = 0; + } + else { + /* Step down one CTRIM and use fast RTRIM */ + PowerCC26X2_module.nCtrimFractNew = Max(1, PowerCC26X2_module.nCtrimFractNew + 32 - 21); + PowerCC26X2_module.nCtrimNew = Max(0, PowerCC26X2_module.nCtrimNew - 1); + PowerCC26X2_module.nRtrimNew = 3; + } + } + else if (PowerCC26X2_module.nCtrimFractNew > 30) { + if (PowerCC26X2_module.nRtrimNew == 0) { + /* We try the slow RTRIM in this CTRIM first */ + PowerCC26X2_module.nCtrimFractNew = Min(30, PowerCC26X2_module.nCtrimFractNew - 21); + PowerCC26X2_module.nRtrimNew = 3; + } + else { + /* Step down one CTRIM and use fast RTRIM */ + PowerCC26X2_module.nCtrimFractNew = Min(30, PowerCC26X2_module.nCtrimFractNew - 32 + 21); + PowerCC26X2_module.nCtrimNew = Min(0x3F, PowerCC26X2_module.nCtrimNew + 1); + PowerCC26X2_module.nRtrimNew = 0; + } + } + else + { + /* We're within sweet spot of current CTRIM => no change */ + } + + /* Find RCOSC_HF vs XOSC_HF frequency offset with new trim settings */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RCOSCHFCTL, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S, + PowerCC26X2_module.nCtrimNew); + + /* Enable RCOSCHFCTRIMFRACT_EN */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL1_LOCAL, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_M, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_S, + 1); + + /* Modify CTRIM_FRACT */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL1_LOCAL, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S, + PowerCC26X2_module.nCtrimFractNew); + + /* Modify RTRIM */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ATESTCTL, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S, + PowerCC26X2_module.nRtrimNew); +} + +/* + * ======== Power_calibrateRcoscHf2 ======== + * Calibrate RCOSC_HF agains XOSC_HF: determine better result, set new trims + */ +static void calibrateRcoscHf2(int32_t tdcResult) +{ + + PowerCC26X2_module.nDeltaFreqNew = (int32_t) tdcResult - RCOSC_HF_PERFECT_TDC_VALUE; + /* Calculate new delta freq */ + + /* *** STEP 4: Determine whether the new settings are better or worse */ + if (Abs(PowerCC26X2_module.nDeltaFreqNew) <= Abs(PowerCC26X2_module.nDeltaFreqCurr)) { + /* New settings are better or same -> make current by keeping in registers */ + PowerCC26X2_module.bRefine = false; + } + else { + /* First measurement was better than second, restore current settings */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RCOSCHFCTL, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S, + PowerCC26X2_module.nCtrimCurr); + + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL1_LOCAL, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S, + PowerCC26X2_module.nCtrimFractCurr); + + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ATESTCTL, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S, + PowerCC26X2_module.nRtrimCurr); + + /* Enter a refinement mode where we keep searching for better matches */ + PowerCC26X2_module.bRefine = true; + } + +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26XX.c new file mode 100644 index 0000000..0cfa419 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26XX.c @@ -0,0 +1,1394 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC26XX.c ======== + */ + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_prcm.h) +#include DeviceFamily_constructPath(inc/hw_nvic.h) +#include DeviceFamily_constructPath(inc/hw_aon_wuc.h) +#include DeviceFamily_constructPath(inc/hw_aon_rtc.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ccfg.h) +#include DeviceFamily_constructPath(inc/hw_rfc_pwr.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/pwr_ctrl.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/aon_wuc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_rtc.h) +#include DeviceFamily_constructPath(driverlib/aon_event.h) +#include DeviceFamily_constructPath(driverlib/aux_wuc.h) +#include DeviceFamily_constructPath(driverlib/osc.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/vims.h) +#include DeviceFamily_constructPath(driverlib/rfc.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/driverlib_release.h) +#include DeviceFamily_constructPath(driverlib/setup.h) +#include DeviceFamily_constructPath(driverlib/ccfgread.h) + +static unsigned int configureXOSCHF(unsigned int action); +static unsigned int nopResourceHandler(unsigned int action); +static unsigned int configureRFCoreClocks(unsigned int action); +static void switchXOSCHFclockFunc(uintptr_t arg0); +static void lfClockReadyCallback(uintptr_t arg); +static void disableLfClkQualifiersEnableClkLoss(); +static void emptyClockFunc(uintptr_t arg); +static int_fast16_t notify(uint_fast16_t eventType); + +/* RCOSC calibration functions functions */ +extern void PowerCC26XX_doCalibrate(void); +extern bool PowerCC26XX_initiateCalibration(void); +extern void PowerCC26XX_auxISR(uintptr_t arg); +extern void PowerCC26XX_RCOSC_clockFunc(uintptr_t arg); + +/* Externs */ +extern const PowerCC26XX_Config PowerCC26XX_config; + +/* Module_State */ +PowerCC26XX_ModuleState PowerCC26XX_module = { + .notifyList = { NULL }, /* list of registered notifications */ + .constraintMask = 0, /* the constraint mask */ + .clockObj = { 0 }, /* Clock object for scheduling wakeups */ + .xoscClockObj = { 0 }, /* Clock object for XOSC_HF switching */ + .lfClockObj = { 0 }, /* Clock object for LF clock check */ + .calClockStruct = { 0 }, /* Clock object for RCOSC calibration */ + .hwiStruct = { 0 }, /* hwi object for calibration */ + .nDeltaFreqCurr = 0, /* RCOSC calibration variable */ + .nCtrimCurr = 0, /* RCOSC calibration variable */ + .nCtrimFractCurr = 0, /* RCOSC calibration variable */ + .nCtrimNew = 0, /* RCOSC calibration variable */ + .nCtrimFractNew = 0, /* RCOSC calibration variable */ + .nRtrimNew = 0, /* RCOSC calibration variable */ + .nRtrimCurr = 0, /* RCOSC calibration variable */ + .nDeltaFreqNew = 0, /* RCOSC calibration variable */ + .bRefine = false, /* RCOSC calibration variable */ + .state = Power_ACTIVE, /* current transition state */ + .xoscPending = false, /* is XOSC_HF activation in progress? */ + .calLF = false, /* calibrate RCOSC_LF? */ + .hwiState = 0, /* calibration AUX ISR state */ + .busyCal = false, /* already busy calibrating */ + .calStep = 1, /* current calibration step */ + .firstLF = true, /* is this first LF calibration? */ + .enablePolicy = false, /* default value is false */ + .initialized = false, /* whether Power_init has been called */ +#if defined(DeviceFamily_CC26X0R2) + .emulatorAttached = false, /* emulator attached during boot */ +#endif + .constraintCounts = { 0, 0, 0, 0, 0, 0, 0 }, + .resourceCounts = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + .resourceHandlers = { + configureRFCoreClocks, + configureXOSCHF, + nopResourceHandler + }, /* special resource handler functions */ + .policyFxn = NULL /* power policyFxn */ +}; + +/* resource database */ +const PowerCC26XX_ResourceRecord resourceDB[PowerCC26XX_NUMRESOURCES] = { + { PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER0 }, /* PERIPH_GPT0 */ + { PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER1 }, /* PERIPH_GPT1 */ + { PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER2 }, /* PERIPH_GPT2 */ + { PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER3 }, /* PERIPH_GPT3 */ + { PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_SERIAL, PRCM_PERIPH_SSI0 }, /* PERIPH_SSI0 */ + { PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_SSI1 }, /* PERIPH_SSI1 */ + { PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_SERIAL, PRCM_PERIPH_UART0 }, /* PERIPH_UART0 */ + { PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_SERIAL, PRCM_PERIPH_I2C0 }, /* PERIPH_I2C0 */ + { PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TRNG }, /* PERIPH_TRNG */ + { PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_GPIO }, /* PERIPH_GPIO */ + { PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_UDMA }, /* PERIPH_UDMA */ + { PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_CRYPTO }, /* PERIPH_CRYPTO */ + { PowerCC26XX_PERIPH | PowerCC26XX_PERIPH_UDMA, PRCM_PERIPH_I2S }, /* PERIPH_I2S */ + { PowerCC26XX_SPECIAL | PowerCC26XX_DOMAIN_RFCORE, 0 }, /* PERIPH_RFCORE */ + { PowerCC26XX_SPECIAL | PowerCC26XX_NOPARENT, 1 }, /* XOSC_HF */ + { PowerCC26XX_DOMAIN | PowerCC26XX_NOPARENT, PRCM_DOMAIN_PERIPH }, /* DOMAIN_PERIPH */ + { PowerCC26XX_DOMAIN | PowerCC26XX_NOPARENT, PRCM_DOMAIN_SERIAL }, /* DOMAIN_SERIAL */ + { PowerCC26XX_DOMAIN | PowerCC26XX_NOPARENT, PRCM_DOMAIN_RFCORE }, /* DOMAIN_RFCORE */ + { PowerCC26XX_SPECIAL | PowerCC26XX_NOPARENT, 2 } /* DOMAIN_SYSBUS */ +}; + + +/* ****************** Power APIs ******************** */ + +/* + * ======== Power_disablePolicy ======== + * Do not run the configured policy + */ +bool Power_disablePolicy(void) +{ + bool enablePolicy = PowerCC26XX_module.enablePolicy; + PowerCC26XX_module.enablePolicy = false; + + return (enablePolicy); +} + +/* + * ======== Power_enablePolicy ======== + * Run the configured policy + */ +void Power_enablePolicy(void) +{ + PowerCC26XX_module.enablePolicy = true; +} + +/* + * ======== Power_getConstraintMask ======== + * Get a bitmask indicating the constraints that have been registered with + * Power. + */ +uint_fast32_t Power_getConstraintMask(void) +{ + return (PowerCC26XX_module.constraintMask); +} + +/* + * ======== Power_getDependencyCount ======== + * Get the count of dependencies that are currently declared upon a resource. + */ +int_fast16_t Power_getDependencyCount(uint_fast16_t resourceId) +{ + DebugP_assert(resourceId < PowerCC26XX_NUMRESOURCES); + + return ((int_fast16_t)PowerCC26XX_module.resourceCounts[resourceId]); +} + +/* + * ======== Power_getTransitionLatency ======== + * Get the transition latency for a sleep state. The latency is reported + * in units of microseconds. + */ +uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, + uint_fast16_t type) +{ + uint32_t latency = 0; + + if (type == Power_RESUME) { + if (sleepState == PowerCC26XX_STANDBY) { + latency = PowerCC26XX_RESUMETIMESTANDBY; + } + } + else { + if (sleepState == PowerCC26XX_STANDBY) { + latency = PowerCC26XX_TOTALTIMESTANDBY; + } + } + + return (latency); +} + +/* + * ======== Power_getTransitionState ======== + * Get the current sleep transition state. + */ +uint_fast16_t Power_getTransitionState(void) +{ + return (PowerCC26XX_module.state); +} + +/* + * ======== Power_idleFunc ======== + * Function needs to be plugged into the idle loop. + * It calls the configured policy function if the + * 'enablePolicy' flag is set. + */ +void Power_idleFunc() +{ + if (PowerCC26XX_module.enablePolicy) { + if (PowerCC26XX_module.policyFxn != NULL) { + (*(PowerCC26XX_module.policyFxn))(); + } + } +} + +/* + * ======== Power_init ======== + */ +int_fast16_t Power_init() +{ + ClockP_Params clockParams; + uint32_t ccfgLfClkSrc; + uint32_t timeout; + + /* if this function has already been called, just return */ + if (PowerCC26XX_module.initialized) { + return (Power_SOK); + } + +#if defined(DeviceFamily_CC26X0R2) + /* check to see if the JTAG_PD is on, meaning the emulator was attached during boot and */ + /* that the user is in an active debug session */ + PowerCC26XX_module.emulatorAttached = (HWREG(AON_WUC_BASE + AON_WUC_O_PWRSTAT) & AON_WUC_PWRSTAT_JTAG_PD_ON) == AON_WUC_PWRSTAT_JTAG_PD_ON; +#endif + + /* set module state field 'initialized' to true */ + PowerCC26XX_module.initialized = true; + + /* set the module state enablePolicy field */ + PowerCC26XX_module.enablePolicy = PowerCC26XX_config.enablePolicy; + + /* copy the Power policy function to module state */ + PowerCC26XX_module.policyFxn = PowerCC26XX_config.policyFxn; + + /* construct the Clock object for scheduling of wakeups */ + /* initiated and started by the power policy */ + ClockP_Params_init(&clockParams); + clockParams.period = 0; + clockParams.startFlag = false; + clockParams.arg = 0; + ClockP_construct(&PowerCC26XX_module.clockObj, &emptyClockFunc, + 0, &clockParams); + + /* construct the Clock object for XOSC_HF switching */ + /* initiated and started by Power module when activating XOSC_HF */ + ClockP_construct(&PowerCC26XX_module.xoscClockObj, &switchXOSCHFclockFunc, + 0, &clockParams); + + /* construct the Clock object for disabling LF clock quailifiers */ + /* one shot, auto start, first expires at 100 msec */ + ClockP_construct(&PowerCC26XX_module.lfClockObj, &lfClockReadyCallback, + 0, &clockParams); + + (*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_SETUP_CALIBRATE); + + DRIVERLIB_ASSERT_CURR_RELEASE(); + + /* read the LF clock source from CCFG */ + ccfgLfClkSrc = CCFGRead_SCLK_LF_OPTION(); + + /* check if should calibrate RCOSC_LF */ + if (PowerCC26XX_config.calibrateRCOSC_LF) { + /* verify RCOSC_LF is the LF clock source */ + if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_RCOSC_LF) { + PowerCC26XX_module.calLF = true; + } + } + + /* + * if LF source is RCOSC_LF or XOSC_LF: assert DISALLOW_STANDBY constraint + * and start a timeout to check for activation + */ + if ((ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_RCOSC_LF) || + (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_XOSC_LF)) { + + /* disallow STANDBY pending LF clock quailifier disabling */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* determine timeout */ + if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_RCOSC_LF) { + timeout = PowerCC26XX_INITIALWAITRCOSC_LF; + } + else { + timeout = PowerCC26XX_INITIALWAITXOSC_LF; + } + + /* start the Clock object */ + ClockP_setTimeout(ClockP_handle(&PowerCC26XX_module.lfClockObj), + (timeout / ClockP_tickPeriod)); + ClockP_start(ClockP_handle(&PowerCC26XX_module.lfClockObj)); + } + + /* + * else, if the LF clock source is external, can disable clock qualifiers + * now; no need to assert DISALLOW_STANDBY or start the Clock object + */ + else if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF) { + + /* Disable clock qualifiers and enable clock loss */ + disableLfClkQualifiersEnableClkLoss(); + } + /* + * else, user has requested LF to be derived from XOSC_HF + */ + else if(ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF) + { + /* disallow standby */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* wait for the XOSC_HF to power up if it's not ready.. */ + if(OSCClockSourceGet(OSC_SRC_CLK_LF) == OSC_XOSC_HF) + { + /* XOSC_HF is ready. Simply disable clock qualifiers and enable clock loss */ + disableLfClkQualifiersEnableClkLoss(NULL); + } + else + { + /* XOSC_HF is not ready yet, schedule clock to check again later */ + timeout = PowerCC26XX_INITIALWAITXOSC_HF / ClockP_tickPeriod; + /* start the Clock object */ + ClockP_setTimeout(ClockP_handle(&PowerCC26XX_module.lfClockObj), + (timeout / ClockP_tickPeriod)); + ClockP_start(ClockP_handle(&PowerCC26XX_module.lfClockObj)); + } + } + + /* if VIMS RAM is configured as GPRAM: set retention constraint */ + if (!CCFGRead_DIS_GPRAM()) { + Power_setConstraint(PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY); + } + + return (Power_SOK); +} + +/* + * ======== Power_registerNotify ======== + * Register a function to be called on a specific power event. + * + */ +int_fast16_t Power_registerNotify(Power_NotifyObj * pNotifyObj, + uint_fast16_t eventTypes, Power_NotifyFxn notifyFxn, uintptr_t clientArg) +{ + int_fast16_t status = Power_SOK; + + /* check for NULL pointers */ + if ((pNotifyObj == NULL) || (notifyFxn == NULL)) { + status = Power_EINVALIDPOINTER; + } + + else { + /* fill in notify object elements */ + pNotifyObj->eventTypes = eventTypes; + pNotifyObj->notifyFxn = notifyFxn; + pNotifyObj->clientArg = clientArg; + + /* place notify object on event notification queue */ + List_put(&PowerCC26XX_module.notifyList, (List_Elem*)pNotifyObj); + } + + return (status); +} + +/* + * ======== Power_releaseConstraint ======== + * Release a previously declared constraint. + */ +int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId) +{ + unsigned int key; + uint8_t count; + + DebugP_assert(constraintId < PowerCC26XX_NUMCONSTRAINTS); + + key = HwiP_disable(); + + /* get the count of the constraint */ + count = PowerCC26XX_module.constraintCounts[constraintId]; + + DebugP_assert(count != 0); + + count--; + + /* save the updated count */ + PowerCC26XX_module.constraintCounts[constraintId] = count; + + if (count == 0) { + PowerCC26XX_module.constraintMask &= ~(1 << constraintId); + } + + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_releaseDependency ======== + * Release a previously declared dependency. + */ +int_fast16_t Power_releaseDependency(uint_fast16_t resourceId) +{ + uint8_t parent; + uint8_t count; + uint32_t id; + unsigned int key; + + /* assert resourceId is valid */ + DebugP_assert(resourceId < PowerCC26XX_NUMRESOURCES); + + /* disable interrupts */ + key = HwiP_disable(); + + /* read and decrement the reference count */ + count = PowerCC26XX_module.resourceCounts[resourceId]; + + DebugP_assert(count != 0); + + count--; + + /* save the reference count */ + PowerCC26XX_module.resourceCounts[resourceId] = count; + + /* if this was the last dependency being released.., */ + if (count == 0) { + /* deactivate this resource ... */ + id = resourceDB[resourceId].driverlibID; + + /* is resource a peripheral?... */ + if (resourceDB[resourceId].flags & PowerCC26XX_PERIPH) { + PRCMPeripheralRunDisable(id); + PRCMPeripheralSleepDisable(id); + PRCMPeripheralDeepSleepDisable(id); + PRCMLoadSet(); + while (!PRCMLoadGet()) { + ; + } + } + /* else, does resource require a special handler?... */ + else if (resourceDB[resourceId].flags & PowerCC26XX_SPECIAL) { + /* call the special handler */ + PowerCC26XX_module.resourceHandlers[id](PowerCC26XX_DISABLE); + } + + /* else resource is a power domain */ + else { + PRCMPowerDomainOff(id); + while (PRCMPowerDomainStatus(id) != PRCM_DOMAIN_POWER_OFF) { + ; + } + } + + /* propagate release up the dependency tree ... */ + + /* check for a first parent */ + parent = resourceDB[resourceId].flags & PowerCC26XX_PARENTMASK; + + /* if 1st parent, make recursive call to release that dependency */ + if (parent < PowerCC26XX_NUMRESOURCES) { + Power_releaseDependency(parent); + } + } + + /* re-enable interrupts */ + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_setConstraint ======== + * Declare an operational constraint. + */ +int_fast16_t Power_setConstraint(uint_fast16_t constraintId) +{ + unsigned int key; + + DebugP_assert(constraintId < PowerCC26XX_NUMCONSTRAINTS); + + /* disable interrupts */ + key = HwiP_disable(); + + /* set the specified constraint in the constraintMask */ + PowerCC26XX_module.constraintMask |= 1 << constraintId; + + /* increment the specified constraint count */ + PowerCC26XX_module.constraintCounts[constraintId]++; + + /* re-enable interrupts */ + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_setDependency ======== + * Declare a dependency upon a resource. + */ +int_fast16_t Power_setDependency(uint_fast16_t resourceId) +{ + uint8_t parent; + uint8_t count; + uint32_t id; + unsigned int key; + + DebugP_assert(resourceId < PowerCC26XX_NUMRESOURCES); + + /* disable interrupts */ + key = HwiP_disable(); + + /* read and increment reference count */ + count = PowerCC26XX_module.resourceCounts[resourceId]++; + + /* if resource was NOT activated previously ... */ + if (count == 0) { + /* propagate set up the dependency tree ... */ + + /* check for a first parent */ + parent = resourceDB[resourceId].flags & PowerCC26XX_PARENTMASK; + + /* if first parent, make recursive call to set that dependency */ + if (parent < PowerCC26XX_NUMRESOURCES) { + Power_setDependency(parent); + } + + /* now activate this resource ... */ + id = resourceDB[resourceId].driverlibID; + + /* is resource a peripheral?... */ + if (resourceDB[resourceId].flags & PowerCC26XX_PERIPH) { + PRCMPeripheralRunEnable(id); + PRCMPeripheralSleepEnable(id); + PRCMPeripheralDeepSleepEnable(id); + PRCMLoadSet(); + while (!PRCMLoadGet()) { + ; + } + } + /* else, does resource require a special handler?... */ + else if (resourceDB[resourceId].flags & PowerCC26XX_SPECIAL) { + /* call the special handler */ + PowerCC26XX_module.resourceHandlers[id](PowerCC26XX_ENABLE); + } + /* else resource is a power domain */ + else { + PRCMPowerDomainOn(id); + while (PRCMPowerDomainStatus(id) != PRCM_DOMAIN_POWER_ON) { + ; + } + } + } + + /* re-enable interrupts */ + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_setPolicy ======== + * Set the Power policy function + */ +void Power_setPolicy(Power_PolicyFxn policy) +{ + PowerCC26XX_module.policyFxn = policy; +} + +/* + * ======== Power_shutdown ======== + */ +int_fast16_t Power_shutdown(uint_fast16_t shutdownState, + uint_fast32_t shutdownTime) +{ + int_fast16_t status = Power_EFAIL; + unsigned int constraints; + unsigned int hwiKey; + + /* disable interrupts */ + hwiKey = HwiP_disable(); + + /* check if there is a constraint to prohibit shutdown */ + constraints = Power_getConstraintMask(); + if (constraints & (1 << PowerCC26XX_DISALLOW_SHUTDOWN)) { + status = Power_ECHANGE_NOT_ALLOWED; + } + + /* OK to shutdown ... */ + else if (PowerCC26XX_module.state == Power_ACTIVE) { + /* set new transition state to entering shutdown */ + PowerCC26XX_module.state = Power_ENTERING_SHUTDOWN; + + /* signal all clients registered for pre-shutdown notification */ + status = notify(PowerCC26XX_ENTERING_SHUTDOWN); + + /* check for any error */ + if (status != Power_SOK) { + PowerCC26XX_module.state = Power_ACTIVE; + HwiP_restore(hwiKey); + return (status); + } + + /* now proceed with shutdown sequence ... */ + + /* If the JTAG_PD is on, make sure that the DUT reboots without + * stopping for halt-in-boot when it enters shutdown. */ +#if defined(DeviceFamily_CC26X0R2) + uint32_t aonSysctrlResetctl; + + if((HWREG(AON_WUC_BASE + AON_WUC_O_PWRSTAT) & AON_WUC_PWRSTAT_JTAG_PD_ON) && + (!PowerCC26XX_module.emulatorAttached)) { + /* set BOOT_DET = b10. + * The next time the device enters shutdown the + * device will start booting immediately because the JTAG_PD is already on. + * However since since BOOT_DET == b10, the boot code will run not wait + * for a GPIO interrupt, but rather run to completion and branch to the + * flash image with the JTAG_PD turned off. + */ + aonSysctrlResetctl = HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) & + ~( AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M | + AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M ); + /* To get BOOT_DET = b10, set BOOT_DET_1_SET and BOOT_DET_0_CLR*/ + HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL) = aonSysctrlResetctl | + (AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR | AON_SYSCTL_RESETCTL_BOOT_DET_1_SET); + } +#endif + + /* 1. Switch HF, MF, and LF clocks to source from RCOSC_HF */ + if (OSCClockSourceGet(OSC_SRC_CLK_HF) != OSC_RCOSC_HF) { + /* 1.1. Source HF and MF from RCOSC_HF */ + OSCClockSourceSet(OSC_SRC_CLK_HF | OSC_SRC_CLK_MF, OSC_RCOSC_HF); + while (!OSCHfSourceReady()); + OSCHfSourceSwitch(); + } + /* 1.2. Source LF from RCOSC_LF */ + OSCClockSourceSet(OSC_SRC_CLK_LF, OSC_RCOSC_LF); + while (OSCClockSourceGet(OSC_SRC_CLK_LF) != OSC_RCOSC_LF); + + /* 2. Make sure DMA and CRYTO clocks are off in deep-sleep */ + PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_CRYPTO); + PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_UDMA); + PRCMLoadSet(); + while (!PRCMLoadGet()) { + ; + } + + /* 3. Power OFF AUX and disconnect from bus */ + AUXWUCPowerCtrl(AUX_WUC_POWER_OFF); + + /* 4. Remove AUX force ON */ + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) &= + ~AON_WUC_AUXCTL_AUX_FORCE_ON; + + /* + * 5. Reset AON event source IDs to avoid pending events powering + * on MCU/AUX + */ + HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) = 0x3F3F3F3F; + HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL) = 0x003F3F3F; + + /* sync AON */ + SysCtrlAonSync(); + + /* + * 6. Enable shutdown - this latches the IOs, so configuration of + * IOCFGx registers must be done prior to this + */ + AONWUCShutDownEnable(); + + /* 7. Sync AON */ + SysCtrlAonSync(); + + /* 8. Wait until AUX powered off */ + while (AONWUCPowerStatusGet() & AONWUC_AUX_POWER_ON); + + /* 9. Request to power off MCU when go to deep sleep */ + PRCMMcuPowerOff(); + + /* + * 10. Turn off power domains inside MCU VD (BUS, FL_BUS, RFC, + * CPU) + */ + PRCMPowerDomainOff(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL | + PRCM_DOMAIN_PERIPH | PRCM_DOMAIN_CPU | PRCM_DOMAIN_VIMS); + + /* 11. Deep sleep to activate shutdown */ + PRCMDeepSleep(); + } + else { + status = Power_EBUSY; + } + + /* NOTE: if shutdown succeeded, should never get here */ + + /* return failure status */ + PowerCC26XX_module.state = Power_ACTIVE; + + /* re-enable interrupts */ + HwiP_restore(hwiKey); + + /* if get here, failed to shutdown, return error code */ + return (status); +} + +/* + * ======== Power_sleep ======== + */ +int_fast16_t Power_sleep(uint_fast16_t sleepState) +{ + int_fast16_t status = Power_SOK; + int_fast16_t notifyStatus = Power_SOK; + int_fast16_t lateNotifyStatus = Power_SOK; + unsigned int xosc_hf_active = false; + uint_fast16_t postEventLate; + uint32_t poweredDomains = 0; + uint_fast16_t preEvent; + uint_fast16_t postEvent; + unsigned int constraints; + bool retainCache = false; + uint32_t modeVIMS; + unsigned int swiKey; + +#if defined(DeviceFamily_CC26X0R2) + /* has JTAG_PD been turned AFTER boot due to TCK noise? */ + if((HWREG(AON_WUC_BASE + AON_WUC_O_PWRSTAT) & AON_WUC_PWRSTAT_JTAG_PD_ON) && (!PowerCC26XX_module.emulatorAttached)) + { + /* notify all subscribers */ + notify(PowerCC26XX_JTAG_PD_TURNED_ON); + } +#endif + + /* first validate the sleep code */ + if (sleepState != PowerCC26XX_STANDBY) { + status = Power_EINVALIDINPUT; + } + + else { + + /* check to make sure Power is not busy with another transition */ + if (PowerCC26XX_module.state == Power_ACTIVE) { + /* set transition state to entering sleep */ + PowerCC26XX_module.state = Power_ENTERING_SLEEP; + } + else { + status = Power_EBUSY; + } + + if (status == Power_SOK) { + + /* setup sleep vars */ + preEvent = PowerCC26XX_ENTERING_STANDBY; + postEvent = PowerCC26XX_AWAKE_STANDBY; + postEventLate = PowerCC26XX_AWAKE_STANDBY_LATE; + + /* disable Task scheduling; allow Swis and Hwis for notifications */ + PowerCC26XX_schedulerDisable(); + + /* signal all clients registered for pre-sleep notification */ + status = notify(preEvent); + + /* check for any error */ + if (status != Power_SOK) { + PowerCC26XX_module.state = Power_ACTIVE; + PowerCC26XX_schedulerRestore(); + return (status); + } + + /* now disable Swi scheduling */ + swiKey = SwiP_disable(); + + /* 1. Freeze the IOs on the boundary between MCU and AON */ + AONIOCFreezeEnable(); + + /* 2. If XOSC_HF is active, force it off */ + if(OSCClockSourceGet(OSC_SRC_CLK_HF) == OSC_XOSC_HF) { + xosc_hf_active = true; + configureXOSCHF(PowerCC26XX_DISABLE); + } + + /* 3. Allow AUX to power down */ + AONWUCAuxWakeupEvent(AONWUC_AUX_ALLOW_SLEEP); + + /* 4. Make sure writes take effect */ + SysCtrlAonSync(); + + /* now proceed to transition to Power_STANDBY ... */ + + /* 5. Query and save domain states before powering them off */ + if (Power_getDependencyCount(PowerCC26XX_DOMAIN_RFCORE)) { + poweredDomains |= PRCM_DOMAIN_RFCORE; + } + if (Power_getDependencyCount(PowerCC26XX_DOMAIN_SERIAL)){ + poweredDomains |= PRCM_DOMAIN_SERIAL; + } + if (Power_getDependencyCount(PowerCC26XX_DOMAIN_PERIPH)) { + poweredDomains |= PRCM_DOMAIN_PERIPH; + } + + /* 6. Gate running deep sleep clocks for Crypto and DMA */ + if (Power_getDependencyCount(PowerCC26XX_PERIPH_CRYPTO)) { + PRCMPeripheralDeepSleepDisable( + resourceDB[PowerCC26XX_PERIPH_CRYPTO].driverlibID); + } + if (Power_getDependencyCount(PowerCC26XX_PERIPH_UDMA)) { + PRCMPeripheralDeepSleepDisable( + resourceDB[PowerCC26XX_PERIPH_UDMA].driverlibID); + } + /* 7. Make sure clock settings take effect */ + PRCMLoadSet(); + + /* 8. Request power off of domains in the MCU voltage domain */ + PRCMPowerDomainOff(poweredDomains | PRCM_DOMAIN_CPU); + + /* 9. Request uLDO during standby */ + PRCMMcuUldoConfigure(true); + + /* query constraints to determine if cache should be retained */ + constraints = Power_getConstraintMask(); + if (constraints & (1 << PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY)) { + retainCache = true; + } + + /* 10. If don't want VIMS retention in standby, disable it now... */ + if (retainCache == false) { + + /* 10.1 Get the current VIMS mode */ + do { + modeVIMS = VIMSModeGet(VIMS_BASE); + } while (modeVIMS == VIMS_MODE_CHANGING); + + /* 10.2 If in a cache mode, turn VIMS off */ + if (modeVIMS == VIMS_MODE_ENABLED) { + + /* 10.3 Now turn off the VIMS */ + VIMSModeSet(VIMS_BASE, VIMS_MODE_OFF); + } + + /* 10.4 Now disable retention */ + PRCMCacheRetentionDisable(); + } + + /* 11. Setup recharge parameters */ + SysCtrlSetRechargeBeforePowerDown(XOSC_IN_HIGH_POWER_MODE); + + /* 12. Make sure all writes have taken effect */ + SysCtrlAonSync(); + + /* 13. Invoke deep sleep to go to STANDBY */ + PRCMDeepSleep(); + + /* 14. If didn't retain VIMS in standby, re-enable retention now */ + if (retainCache == false) { + + /* 14.1 If previously in a cache mode, restore the mode now */ + if (modeVIMS == VIMS_MODE_ENABLED) { + VIMSModeSet(VIMS_BASE, modeVIMS); + } + + /* 14.2 Re-enable retention */ + PRCMCacheRetentionEnable(); + } + + /* 15. Start forcing on power to AUX */ + AONWUCAuxWakeupEvent(AONWUC_AUX_WAKEUP); + + /* 16. Start re-powering power domains */ + PRCMPowerDomainOn(poweredDomains); + + /* 17. Restore deep sleep clocks of Crypto and DMA */ + if (Power_getDependencyCount(PowerCC26XX_PERIPH_CRYPTO)) { + PRCMPeripheralDeepSleepEnable( + resourceDB[PowerCC26XX_PERIPH_CRYPTO].driverlibID); + } + if (Power_getDependencyCount(PowerCC26XX_PERIPH_UDMA)) { + PRCMPeripheralDeepSleepEnable( + resourceDB[PowerCC26XX_PERIPH_UDMA].driverlibID); + } + + /* 18. Make sure clock settings take effect */ + PRCMLoadSet(); + + /* 19. Release request for uLDO */ + PRCMMcuUldoConfigure(false); + + /* 20. Set transition state to EXITING_SLEEP */ + PowerCC26XX_module.state = Power_EXITING_SLEEP; + + /* 21. Wait until all power domains are back on */ + while (PRCMPowerDomainStatus(poweredDomains) != + PRCM_DOMAIN_POWER_ON) { + ; + } + + /* 22. Wait for the RTC shadow values to be updated so that + * the early notification callbacks can read out valid RTC values + */ + SysCtrlAonSync(); + + /* + * 23. Signal clients registered for early post-sleep notification; + * this should be used to initialize any timing critical or IO + * dependent hardware + */ + notifyStatus = notify(postEvent); + + /* 24. Disable IO freeze and ensure RTC shadow value is updated */ + AONIOCFreezeDisable(); + SysCtrlAonSync(); + + /* 25. Wait for AUX to power up */ + while(!(AONWUCPowerStatusGet() & AONWUC_AUX_POWER_ON)) {}; + + /* 26. If XOSC_HF was forced off above, initiate switch back */ + if (xosc_hf_active == true) { + configureXOSCHF(PowerCC26XX_ENABLE); + } + + /* 27. Re-enable interrupts */ + CPUcpsie(); + + /* + * 28. Signal all clients registered for late post-sleep + * notification + */ + lateNotifyStatus = notify(postEventLate); + + /* + * 29. Now clear the transition state before re-enabling + * scheduler + */ + PowerCC26XX_module.state = Power_ACTIVE; + + /* 30. Re-enable Swi scheduling */ + SwiP_restore(swiKey); + + /* 31. Adjust recharge parameters */ + SysCtrlAdjustRechargeAfterPowerDown(PowerCC26XX_config.vddrRechargeMargin); + + /* re-enable Task scheduling */ + PowerCC26XX_schedulerRestore(); + + /* if there was a notification error, set return status */ + if ((notifyStatus != Power_SOK) || + (lateNotifyStatus != Power_SOK)) { + status = Power_EFAIL; + } + } + } + + return (status); +} + +/* + * ======== Power_unregisterNotify ======== + * Unregister for a power notification. + * + */ +void Power_unregisterNotify(Power_NotifyObj * pNotifyObj) +{ + unsigned int key; + + /* remove notify object from its event queue */ + key = HwiP_disable(); + + /* remove notify object from its event queue */ + List_remove(&PowerCC26XX_module.notifyList, (List_Elem *)pNotifyObj); + + HwiP_restore(key); +} + +/* ****************** CC26XX specific APIs ******************** */ + +/* + * ======== PowerCC26XX_calibrate ======== + * Plug this function into the PowerCC26XX_Config structure + * if calibration is needed. + */ +bool PowerCC26XX_calibrate(unsigned int arg) +{ + bool retVal = false; + ClockP_Params clockParams; + + switch (arg) { + case PowerCC26XX_SETUP_CALIBRATE: + /* + * If RCOSC calibration is enabled, construct a Clock object for + * delays. Set timeout to '1' Clock tick period for the minimal + * delay. The object will explicitly started by Power module when + * appropriate + */ + ClockP_Params_init(&clockParams); + clockParams.period = 0; + clockParams.startFlag = false; + clockParams.arg = 0; + ClockP_construct(&PowerCC26XX_module.calClockStruct, + &PowerCC26XX_RCOSC_clockFunc, 1, &clockParams); + + /* construct the Hwi */ + HwiP_construct(&PowerCC26XX_module.hwiStruct, + 44, PowerCC26XX_auxISR, NULL); + + break; + + case PowerCC26XX_INITIATE_CALIBRATE: + retVal = PowerCC26XX_initiateCalibration(); + break; + + case PowerCC26XX_DO_CALIBRATE: + PowerCC26XX_doCalibrate(); + break; + } + + return (retVal); +} + +/* + * ======== PowerCC26XX_doWFI ======== + */ +void PowerCC26XX_doWFI(void) +{ + __asm(" wfi"); +} + +/* + * ======== PowerCC26XX_getClockHandle ======== + */ +ClockP_Handle PowerCC26XX_getClockHandle() +{ + return ((ClockP_Handle)&PowerCC26XX_module.clockObj); +} + +/* + * ======== PowerCC26XX_noCalibrate ======== + * Plug this function into the PowerCC26XX config structure if calibration + * is not needed. + */ +bool PowerCC26XX_noCalibrate(unsigned int arg) +{ + return (0); +} + +/* + * ======== PowerCC26XX_getXoscStartupTime ======== + * Get the estimated crystal oscillator startup time + */ +uint32_t PowerCC26XX_getXoscStartupTime(uint32_t timeUntilWakeupInMs) +{ + return (OSCHF_GetStartupTime(timeUntilWakeupInMs)); +} + +/* + * ======== PowerCC26XX_injectCalibration ======== + * Explicitly trigger RCOSC calibration + */ +bool PowerCC26XX_injectCalibration(void) +{ + if ((*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_INITIATE_CALIBRATE)) { + /* here if AUX SMPH was available, start calibration now ... */ + (*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_DO_CALIBRATE); + return (true); + } + + return (false); +} + +/* + * ======== PowerCC26XX_isStableXOSC_HF ======== + * Check if XOSC_HF has stabilized. + */ +bool PowerCC26XX_isStableXOSC_HF(void) +{ + bool ready = true; + unsigned int key; + + key = HwiP_disable(); + + /* only query if HF source is ready if there is a pending change */ + if (PowerCC26XX_module.xoscPending) { + ready = OSCHfSourceReady(); + } + + HwiP_restore(key); + + return (ready); +} + +/* + * ======== PowerCC26XX_switchXOSC_HF ======== + * Switch to enable XOSC_HF. + * May only be called when using the PowerCC26XX_SWITCH_XOSC_HF_MANUALLY + * constraint. + * May only be called after ensuring the XOSC_HF is stable by calling + * PowerCC26XX_isStableXOSC_HF(). + */ +void PowerCC26XX_switchXOSC_HF(void) +{ + /* This function is just a veneer to call the static callback function for + * the XOSC_HF clock. This way, if the switching does fail because a constraint + * stopped it from switching, a clock will be scheduled into the future to try + * again. This could happen if there is an ongoing operation from another bus + * master that reads from flash such as SPI or AES DMA operations. + */ + switchXOSCHFclockFunc((uintptr_t) NULL); +} + +/* * * * * * * * * * * internal and support functions * * * * * * * * * * */ + +/* + * ======== emptyClockFunc ======== + * Clock function used by power policy to schedule early wakeups. + */ +static void emptyClockFunc(uintptr_t arg) +{ +} + +/* + * ======== disableLfClkQualifiersEnableClkLoss ======== + * Function used to disable LF clock qualifiers and enable clock loss + */ +static void disableLfClkQualifiersEnableClkLoss() +{ + /* Disable the LF clock qualifiers */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M | + DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M, + DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S, 0x3); + + /* Enable clock loss detection */ + OSCClockLossEventEnable(); +} + +/* + * ======== lfClockReadyCallback ======== + * Clock function callback used to check if the LF clock is ready + */ +static void lfClockReadyCallback(uintptr_t arg) +{ + uint32_t ccfgLfClkSrc; + uint32_t sourceLF; + uint32_t timeout; + + /* query LF clock source */ + sourceLF = OSCClockSourceGet(OSC_SRC_CLK_LF); + + /* is LF source either RCOSC_LF or XOSC_LF yet? */ + if ((sourceLF == OSC_RCOSC_LF) || (sourceLF == OSC_XOSC_LF)) { + + /* Disable clock qualifiers and enable clock loss */ + disableLfClkQualifiersEnableClkLoss(); + + /* now finish by releasing the standby disallow constraint */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + /* is LF source XOSC_HF yet? */ + else if(sourceLF == OSC_XOSC_HF) + { + /* Disable clock qualifiers and enable clock loss */ + disableLfClkQualifiersEnableClkLoss(); + + /* Keep PowerCC26XX_DISALLOW_STANDBY set, not allowed to enter standby + * when LF clock is sourced from from XOSC_HF + */ + } + + /* not yet, LF still derived from RCOSC_HF, restart clock to check back later */ + else { + + /* read the LF clock source from CCFG */ + ccfgLfClkSrc = CCFGRead_SCLK_LF_OPTION(); + + /* determine retry timeout */ + if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_RCOSC_LF) { + timeout = PowerCC26XX_RETRYWAITRCOSC_LF; + } + else if(ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_XOSC_LF){ + timeout = PowerCC26XX_RETRYWAITXOSC_LF; + } + else { + /* ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF */ + timeout = PowerCC26XX_RETRYWAITXOSC_HF; + } + /* retrigger LF Clock to fire again */ + ClockP_setTimeout(ClockP_handle(&PowerCC26XX_module.lfClockObj), + (timeout / ClockP_tickPeriod)); + ClockP_start(ClockP_handle(&PowerCC26XX_module.lfClockObj)); + } +} + +/* + * ======== nopResourceFunc ======== + * special resource handler + */ +static unsigned int nopResourceHandler(unsigned int action) +{ + return (0); +} + +/* + * ======== notify ======== + * Send notifications to registered clients. + * Note: Task scheduling is disabled when this function is called. + */ +static int_fast16_t notify(uint_fast16_t eventType) +{ + int_fast16_t notifyStatus; + Power_NotifyFxn notifyFxn; + uintptr_t clientArg; + List_Elem *elem; + + /* if queue is empty, return immediately */ + if (!List_empty(&PowerCC26XX_module.notifyList)) { + /* point to first client notify object */ + elem = List_head(&PowerCC26XX_module.notifyList); + + /* walk the queue and notify each registered client of the event */ + do { + if (((Power_NotifyObj *)elem)->eventTypes & eventType) { + /* pull params from notify object */ + notifyFxn = ((Power_NotifyObj *)elem)->notifyFxn; + clientArg = ((Power_NotifyObj *)elem)->clientArg; + + /* call the client's notification function */ + notifyStatus = (int_fast16_t)(*(Power_NotifyFxn)notifyFxn)( + eventType, 0, clientArg); + + /* if client declared error stop all further notifications */ + if (notifyStatus != Power_NOTIFYDONE) { + return (Power_EFAIL); + } + } + + /* get next element in the notification queue */ + elem = List_next(elem); + + } while (elem != NULL); + } + + return (Power_SOK); +} + +/* + * ======== configureRFCoreClocks ======== + * Special dependency function for controlling RF core clocks. + */ +static unsigned int configureRFCoreClocks(unsigned int action) +{ + if (action == PowerCC26XX_ENABLE) { + RFCClockEnable(); + } + else { + RFCClockDisable(); + } + + return (0); +} + +/* + * ======== switchXOSCHFclockFunc ======== + * Clock function used for delayed switching to XOSC_HF. + */ +static void switchXOSCHFclockFunc(uintptr_t arg0) +{ + bool readyToCal; + uint32_t timeout; + unsigned int key; + + key = HwiP_disable(); + + /* if pending switch has already been made, just send out notifications */ + if (PowerCC26XX_module.xoscPending == false) { + + /* initiate RCOSC calibration */ + readyToCal = (*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_INITIATE_CALIBRATE); + + /* notify clients that were waiting for a switch notification */ + notify(PowerCC26XX_XOSC_HF_SWITCHED); + + /* if ready to start first cal measurment, do it now */ + if (readyToCal == true) { + (*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_DO_CALIBRATE); + } + } + + /* else, if HF ready to switch and we are allowed to, do it now ... */ + else if (!(Power_getConstraintMask() & (1 << PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING)) && OSCHfSourceReady()) { + OSCHF_AttemptToSwitchToXosc(); + + PowerCC26XX_module.xoscPending = false; + + /* initiate RCOSC calibration */ + readyToCal = (*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_INITIATE_CALIBRATE); + + /* now notify clients that were waiting for a switch notification */ + notify(PowerCC26XX_XOSC_HF_SWITCHED); + + /* if ready to start first cal measurment, do it now */ + if (readyToCal == true) { + (*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_DO_CALIBRATE); + } + } + + /* else, wait some more, then see if can switch ... */ + else { + /* calculate wait timeout in units of ticks */ + timeout = PowerCC26XX_RETRYWAITXOSC_HF / ClockP_tickPeriod; + if (timeout == 0) { + timeout = 1; /* wait at least 1 tick */ + } + + /* re-start Clock object with retry timeout */ + ClockP_setTimeout( + ClockP_handle(&PowerCC26XX_module.xoscClockObj), timeout); + ClockP_start(ClockP_handle(&PowerCC26XX_module.xoscClockObj)); + } + + HwiP_restore(key); +} + +/* + * ======== configureXOSCHF ======== + */ +static unsigned int configureXOSCHF(unsigned int action) +{ + uint32_t timeout; + + if (action == PowerCC26XX_ENABLE && OSCClockSourceGet(OSC_SRC_CLK_HF) != OSC_XOSC_HF) { + OSCHF_TurnOnXosc(); + + PowerCC26XX_module.xoscPending = true; + + /* Unless it is disallowed, estimate the required stabilisation + * time and start a clock. + * When the clock times out, the callback will try and switch to + * the XOSC_HF. If the XOSC_HF is not ready yet, the callback + * will start a new clock to try again. + */ + if (!(Power_getConstraintMask() & (1 << PowerCC26XX_SWITCH_XOSC_HF_MANUALLY))) { + /* calculate wait timeout in units of ticks */ + timeout = PowerCC26XX_INITIALWAITXOSC_HF / ClockP_tickPeriod; + if (timeout == 0) { + timeout = 1; /* wait at least 1 tick */ + } + + /* start Clock object with initial timeout */ + ClockP_stop(ClockP_handle(&PowerCC26XX_module.xoscClockObj)); + ClockP_setTimeout(ClockP_handle(&PowerCC26XX_module.xoscClockObj), + timeout); + ClockP_start(ClockP_handle(&PowerCC26XX_module.xoscClockObj)); + } + } + + /* when release XOSC_HF, auto switch to RCOSC_HF */ + else { + OSCHF_SwitchToRcOscTurnOffXosc(); + } + return (0); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26XX.h new file mode 100644 index 0000000..da601fc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26XX.h @@ -0,0 +1,650 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQueueNTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file PowerCC26XX.h + * + * @brief Power manager interface for CC26XX/CC13XX + * + * The Power header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref Power.h for a complete description of APIs. + * + * ## Implementation # + * This header file defines the power resources, constraints, events, sleep + * states and transition latencies for CC26XX/CC13XX. + * + * ============================================================================ + */ + +#ifndef ti_drivers_power_PowerCC26XX_ +#define ti_drivers_power_PowerCC26XX_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/* \cond */ +typedef uint8_t PowerCC26XX_Resource; /* Resource identifier */ +/* \endcond */ + +/*! The latency to reserve for resume from STANDBY (usec). */ +#define PowerCC26XX_RESUMETIMESTANDBY 750 + +/*! The total latency to reserve for entry to and exit from STANDBY (usec). */ +#define PowerCC26XX_TOTALTIMESTANDBY 1000 + +/*! The initial delay when waking from STANDBY (usec). */ +#define PowerCC26XX_WAKEDELAYSTANDBY 240 + +/*! The initial wait time (usec) before checking if RCOSC_LF is stable. */ +#define PowerCC26XX_INITIALWAITRCOSC_LF 1000 + +/*! The retry wait time (usec) when checking to see if RCOSC_LF is stable. */ +#define PowerCC26XX_RETRYWAITRCOSC_LF 1000 + +/*! The initial wait time (usec) before checking if XOSC_HF is stable. */ +#define PowerCC26XX_INITIALWAITXOSC_HF 50 + +/*! The retry wait time (usec) when checking to see if XOSC_HF is stable. */ +#define PowerCC26XX_RETRYWAITXOSC_HF 50 + +/*! The initial wait time (usec) before checking if XOSC_LF is stable. */ +#define PowerCC26XX_INITIALWAITXOSC_LF 10000 + +/*! The retry wait time (usec) when checking to see if XOSC_LF is stable. */ +#define PowerCC26XX_RETRYWAITXOSC_LF 5000 + +/* resource IDs */ +#define PowerCC26XX_PERIPH_GPT0 0 +/*!< Resource ID: General Purpose Timer 0 */ + +#define PowerCC26XX_PERIPH_GPT1 1 +/*!< Resource ID: General Purpose Timer 1 */ + +#define PowerCC26XX_PERIPH_GPT2 2 +/*!< Resource ID: General Purpose Timer 2 */ + +#define PowerCC26XX_PERIPH_GPT3 3 +/*!< Resource ID: General Purpose Timer 3 */ + +#define PowerCC26XX_PERIPH_SSI0 4 +/*!< Resource ID: Synchronous Serial Interface 0 */ + +#define PowerCC26XX_PERIPH_SSI1 5 +/*!< Resource ID: Synchronous Serial Interface 1 */ + +#define PowerCC26XX_PERIPH_UART0 6 /*!< Resource ID: UART 0 */ + +#define PowerCC26XX_PERIPH_I2C0 7 /*!< Resource ID: I2C 0 */ + +#define PowerCC26XX_PERIPH_TRNG 8 +/*!< Resource ID: True Random Number Generator */ + +#define PowerCC26XX_PERIPH_GPIO 9 /*!< Resource ID: General Purpose I/Os */ + +#define PowerCC26XX_PERIPH_UDMA 10 /*!< Resource ID: uDMA Controller */ + +#define PowerCC26XX_PERIPH_CRYPTO 11 /*!< Resource ID: AES Security Module */ + +#define PowerCC26XX_PERIPH_I2S 12 /*!< Resource ID: I2S */ + +#define PowerCC26XX_PERIPH_RFCORE 13 /*!< Resource ID: RF Core Module */ + +#define PowerCC26XX_XOSC_HF 14 +/*!< Resource ID: High Frequency Crystal Oscillator */ + +#define PowerCC26XX_DOMAIN_PERIPH 15 +/*!< Resource ID: Peripheral Power Domain */ + +#define PowerCC26XX_DOMAIN_SERIAL 16 +/*!< Resource ID: Serial Power Domain */ + +#define PowerCC26XX_DOMAIN_RFCORE 17 +/*!< Resource ID: RF Core Power Domain */ + +#define PowerCC26XX_DOMAIN_SYSBUS 18 +/*!< Resource ID: System Bus Power Domain */ + +/* \cond */ +#define PowerCC26XX_NUMRESOURCES 19 /* Number of resources in database */ +/* \endcond */ + +/* \cond */ +/* resource record bitmasks */ +#define PowerCC26XX_PERIPH 0x80 /* resource is a peripheral */ +#define PowerCC26XX_SPECIAL 0x40 /* resource requires special handler */ +#define PowerCC26XX_DOMAIN 0x00 /* resource is a domain */ +#define PowerCC26XX_PARENTMASK 0x3F /* parent resource mask */ +#define PowerCC26XX_NOPARENT 0x3F /* if resource has no parent */ +/* \endcond */ + +#define PowerCC26XX_STANDBY 0x1 /*!< The STANDBY sleep state */ +/* \cond */ +/* internal flags for enabling/disabling resources */ +#define PowerCC26XX_ENABLE 1 +#define PowerCC26XX_DISABLE 0 +/* \endcond */ + +/* constraints */ +#define PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY 0 +/*!< Constraint: VIMS RAM must be retained while in STANDBY */ + +#define PowerCC26XX_DISALLOW_SHUTDOWN 1 +/*!< Constraint: Disallow a transition to the SHUTDOWN state */ + +#define PowerCC26XX_DISALLOW_STANDBY 2 +/*!< Constraint: Disallow a transition to the STANDBY sleep state */ + +#define PowerCC26XX_DISALLOW_IDLE 3 +/*!< Constraint: Disallow a transition to the IDLE sleep state */ + +#define PowerCC26XX_NEED_FLASH_IN_IDLE 4 +/*!< Constraint: Flash memory needs to enabled during IDLE */ + +#define PowerCC26XX_SWITCH_XOSC_HF_MANUALLY 5 +/*!< Constraint: Prevent power driver from starting an RTOS clock and + * automatically switching to the XOSC_HF when it is ready. The power + * driver will turn on the XOSC_HF and return control to the application. + * The application must poll the status of the XOSC_HF and make sure that it + * is stable before manually switching to it. + * If the constraint is released before the application has switched to the + * XOSC_HF, the application is still responsible for switching to the + * XOSC_HF. + * Failing to do so may cause an undefined internal state in the power + * driver. + */ + +#define PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING 6 +/*!< Constraint: Prevent power driver from switching to XOSC_HF when the crystal is + * ready. The RTOS clock will be rescheduled to try again in the future. + * This is a workaround to prevent the flash from being accessed by a bus master + * other than the CPU while switching to XOSC_HF. This would cause a bus stall. + * This functionality is only implemented on CC26X0, CC26X0R2, and CC13X0 as the + * bug was fixed in hardware on later devices. + */ + +/* \cond */ +#define PowerCC26XX_NUMCONSTRAINTS 7 /* Number of constraints supported */ +/* \endcond */ + +/* \cond */ +/* Deprecated constraint names */ +#define PowerCC26XX_SD_DISALLOW PowerCC26XX_DISALLOW_SHUTDOWN +#define PowerCC26XX_SB_DISALLOW PowerCC26XX_DISALLOW_STANDBY +#define PowerCC26XX_IDLE_PD_DISALLOW PowerCC26XX_DISALLOW_IDLE +#define PowerCC26XX_XOSC_HF_SWITCHING_DISALLOW PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING +#define PowerCC26XX_SB_VIMS_CACHE_RETAIN PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY +/* \endcond */ + +/* + * Events + * + * Each event must be a power of two and must be sequential + * without any gaps. + */ +#define PowerCC26XX_ENTERING_STANDBY 0x1 +/*!< Power event: The device is entering the STANDBY sleep state */ + +#define PowerCC26XX_ENTERING_SHUTDOWN 0x2 +/*!< Power event: The device is entering the SHUTDOWN state */ + +#define PowerCC26XX_AWAKE_STANDBY 0x4 +/*!< Power event: The device is waking up from the STANDBY sleep state */ + +#define PowerCC26XX_AWAKE_STANDBY_LATE 0x8 +/*!< Power event: The device is waking up from STANDBY (this event is sent later during wakeup, after interrupts are re-enabled) */ + +#define PowerCC26XX_XOSC_HF_SWITCHED 0x10 +/*!< Power event: The high frequency (HF) clock source has been switched to XOSC_HF */ + +#define PowerCC26XX_JTAG_PD_TURNED_ON 0x20 +/*!< \warning Note that this power event is only supported by the CC2640R2 device! + * + * The JTAG subsystem on the CC26xx devices is automatically enabled after receiving + * 8 pulses on the TCK pin. This will cause the device to draw more power in all + * power modes (Active, Idle, Standby, Shutdown). + * The ::PowerCC26XX_JTAG_PD_TURNED_ON power event will + * let you know when this has happened outside of a debug session due to noise on the pin. + * This allows the application to do a reset of the device when it's convenient in order + * disable the JTAG subsystem and conserve power. + * + * In order to turn off the JTAG_PD the application should subscribe to this event. + * In the callback function the application can call Power_shutdown() and + * this will force a reset of the device. + * Alternatively the the callback function can post another event so that the application can + * reset the device when it's more convenient to do so. + * + * When Power_shutdown() is called when the JTAG subsystem is on, + * the device will reset and branch to the flash image again, + * only now with the JTAG_PD turned off, thus the excess power is gone. + * The wakeup source as read through the SysCtrlResetSourceGet() will in this case + * return RSTSRC_WAKEUP_FROM_SHUTDOWN. + * + * The power driver will, each time before entering standby, check to see if the + * JTAG_PD has been turned on after boot. If so, it will notify all subscribers to the + * ::PowerCC26XX_JTAG_PD_TURNED_ON event. + * If the JTAG_PD was turned on during boot, which is the case when + * using the debugger, the notification will NOT be sent even if the event is registered. + * This is because when actively developing code with an IDE and emulator, the user typically + * wants to be able to debug their code through standby without the device resetting. + * + * Summary of when the ::PowerCC26XX_JTAG_PD_TURNED_ON notification function will be called. + * + * | JTAG_PD state | Notification function registered | Notification function called | + * |----------------------|----------------------------------|------------------------ + * | Off | Don't care | No + * | Turned on during boot| Don't care | No + * | Turned on after boot | No | No + * | Turned on after boot | Yes | Yes + * + * \warning If the ::PowerCC26XX_JTAG_PD_TURNED_ON event is registered, and the notification + * callback function calls Power_shutdown() it will not be possible to attach + * an emulator to a running target. This is becasue the device will reset as soon as the + * emulator turns on the JTAG_PD as part of the connect sequence. + * + * Code snippet on how to register the notification and the callback function: + * @code + * void jtagPdTurnedOnCallbackFxn() + * { + * // Optionally save any critical application information + * // gracefullyShutdownApplication(); + * // Call shutdown, this will reset device, and the application will reboot with JTAG_PD off. + * Power_shutdown(NULL, NULL); + * // Power_shutdown(...) should never return, device will reset. + * } + * + * void taskFxn(UArg a0, UArg a1) + * { + * ... + * // Register "JTAG power domain turned on" notification function + * // Everytime the device is about to enter standby, the power driver will check + * // to see if the JTAG_PD has been turned on after boot. If so, the notification + * // function will be called before entering standby... + * Power_registerNotify(&jtagPdTurnedOnNotifyObj, PowerCC26XX_JTAG_PD_TURNED_ON, (Fxn)jtagPdTurnedOnCallbackFxn, NULL); + * ... + * } + * @endcode + */ + + +/* \cond */ +#define PowerCC26XX_NUMEVENTS 6 /* Number of events supported */ +/* \endcond */ + +/* \cond */ +/* + * Calibration stages + */ +#define PowerCC26XX_SETUP_CALIBRATE 1 +#define PowerCC26XX_INITIATE_CALIBRATE 2 +#define PowerCC26XX_DO_CALIBRATE 3 +/* \endcond */ + +/* \cond */ +/*! @brief Power resource database record format */ +typedef struct PowerCC26XX_ResourceRecord { + uint8_t flags; /* resource type | first parent */ + uint16_t driverlibID; /* corresponding driverlib ID for this resource */ +} PowerCC26XX_ResourceRecord; +/* \endcond */ + +/*! @brief Global configuration structure */ +typedef struct PowerCC26XX_Config { + /*! + * @brief The Power Policy's initialization function + * + * If the policy does not have an initialization function, 'NULL' + * should be specified. + */ + Power_PolicyInitFxn policyInitFxn; + /*! + * @brief The Power Policy function + * + * When enabled, this function is invoked in the idle loop, to + * opportunistically select and activate sleep states. + * + * Two reference policies are provided: + * + * PowerCC26XX_doWFI() - a simple policy that invokes CPU wait for + * interrupt (WFI) + * + * PowerCC26XX_standbyPolicy() - an agressive policy that considers + * constraints, time until next scheduled work, and sleep state + * latencies, and optionally puts the device into the STANDBY state, + * the IDLE state, or as a minimum, WFI. + * + * Custom policies can be written, and specified via this function pointer. + * + * In addition to this static selection, the Power Policy can be + * dynamically changed at runtime, via the Power_setPolicy() API. + */ + Power_PolicyFxn policyFxn; + /*! + * @brief The function to be used for activating RC Oscillator (RCOSC) + * calibration + * + * Calibration is normally enabled, via specification of the function + * PowerCC26XX_calibrate(). This enables high accuracy operation, and + * faster high frequency crystal oscillator (XOSC_HF) startups. + * + * To disable RCOSC calibration, the function PowerCC26XX_noCalibrate() + * should be specified. + */ + bool (*calibrateFxn)(unsigned int); + /*! + * @brief Time in system ticks that specifies the maximum duration the device + * may spend in standby. + * + * When the power driver tries to put the device into standby and determines + * the next wakeup should usually be further into the future than + * maxStandbyDuration system ticks, the power driver will schedule a wakeup + * maxStandbyDuration into the future. When the device wakes up after + * being in standby for maxStandbyDuration ticks, the power driver will + * repeat this process and go back into standby if the state of the system + * allows it. + * + * Inserting such periodic wakeups can be used to automatically calibrate + * the RCOSC with a maximum period between calibrations or to force the + * recalculation of the initial VDDR recharge period. This assumes that + * the constraint to prohibit standby is not set and that periods of + * inactivity are long enough for the power driver to put the device + * into standby. + * + * The value 0 is invalid. When PowerCC26XX_Config.enableMaxStandbyDuration is + * set to false, any value (including 0) is ignored and the feature is + * disabled. + * This feature should not be used to disallow entering standby; + * the PowerCC26XX_DISALLOW_STANDBY constraint should be used for + * this purpose. + */ + uint32_t maxStandbyDuration; + /*! + * @brief Margin in SCLK_LF periods subtracted from previous longest + * VDDR recharge period. + * + * As the device comes out of standby, it updated its previous initial + * VDDR recharge period to be closer to the longest recharge period + * experienced during the time spent in standby before waking up. + * + * vddrRechargeMargin is subtracted from the longest VDDR recharge + * period in SysCtrlAdjustRechargeAfterPowerDown to ensure there is + * some margin between the new initial and converged VDDR recharge + * period. The converged recharge period at a certain temperature + * is board and device dependent. + * + * The default value of 0 disables this feature. + */ + uint16_t vddrRechargeMargin; + /*! + * @brief Boolean that enables limiting the duration spent in standby + * + * If false, the power driver will put the device into standby as + * appropriate without duration restrictions. + * + * If true, the the power driver will force a wakeup every + * PowerCC26XX_Config.maxStandbyDuration system ticks before reevaluating + * the state of the system. + * + * This is set to false by default. + */ + bool enableMaxStandbyDuration; + /*! + * @brief Boolean specifying if the Power Policy function is enabled + * + * If 'true', the policy function will be invoked once for each pass + * of the idle loop. + * + * If 'false', the policy will not be invoked. + * + * In addition to this static setting, the power policy can be dynamically + * enabled and disabled at runtime, via the Power_enablePolicy() and + * Power_disablePolicy() functions, respectively. + */ + bool enablePolicy; + /*! + * @brief Boolean specifying whether the low frequency RC oscillator + * (RCOSC_LF) should be calibrated. + * + * If RCOSC calibration is enabled (above, via specification of + * an appropriate calibrateFxn), this Boolean specifies whether + * RCOSC_LF should be calibrated. + */ + bool calibrateRCOSC_LF; + /*! + * @brief Boolean specifying whether the high frequency RC oscillator + * (RCOSC_HF) should be calibrated. + * + * If RCOSC calibration is enabled (above, via specification of + * an appropriate calibrateFxn), this Boolean specifies whether + * RCOSC_HF should be calibrated. + */ + bool calibrateRCOSC_HF; +} PowerCC26XX_Config; + +/*! + * @brief PowerCC26XX_ModuleState + * + * Power manager state structure. The application must not access any members + * of this structure! + */ +typedef struct PowerCC26XX_ModuleState { + List_List notifyList; /*!< Event notification list */ + uint32_t constraintMask; /*!< Aggregate constraints mask */ + ClockP_Struct clockObj; /*!< Clock object for scheduling wakeups */ + ClockP_Struct xoscClockObj; /*!< Clock object for XOSC_HF switching */ + ClockP_Struct lfClockObj; /*!< Clock object for LF clock checking */ + ClockP_Struct calClockStruct; /*!< Clock object for RCOSC calibration */ + HwiP_Struct hwiStruct; /*!< Hwi object for RCOSC calibration */ + int32_t nDeltaFreqCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimFractCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimNew; /*!< RCOSC calibration variable */ + int32_t nCtrimFractNew; /*!< RCOSC calibration variable */ + int32_t nRtrimNew; /*!< RCOSC calibration variable */ + int32_t nRtrimCurr; /*!< RCOSC calibration variable */ + int32_t nDeltaFreqNew; /*!< RCOSC calibration variable */ + bool bRefine; /*!< RCOSC calibration variable */ + uint32_t state; /*!< Current transition state */ + bool xoscPending; /*!< Is XOSC_HF activation in progress? */ + bool calLF; /*!< Calibrate RCOSC_LF? */ + uint8_t hwiState; /*!< The AUX ISR calibration state */ + bool busyCal; /*!< Already busy calibrating? */ + uint8_t calStep; /*!< The current calibration step */ + bool firstLF; /*!< Is this the first LF calibration? */ + bool enablePolicy; /*!< Is the Power policy enabled? */ + bool initialized; /*!< Has Power_init() been called? */ +#if defined(DeviceFamily_CC26X0R2) + bool emulatorAttached; /*!< Was an emulator detected during boot? */ +#endif + uint8_t constraintCounts[PowerCC26XX_NUMCONSTRAINTS]; + /*!< Array to maintain constraint reference counts */ + uint8_t resourceCounts[PowerCC26XX_NUMRESOURCES]; + /*!< Array to maintain resource dependency reference counts */ + unsigned int (*resourceHandlers[3])(unsigned int); + /*!< Array of special dependency handler functions */ + Power_PolicyFxn policyFxn; /*!< The Power policy function */ +} PowerCC26XX_ModuleState; + +/*! + * @brief The RC Oscillator (RCOSC) calibration function + * + * The function to be used for performing RCOSC calibation. This is the + * default calibration function, and is specified via the calibrateFxn + * pointer in the PowerCC26XX_Config structure. + * + * @param arg used internally + * + * @return used internally + */ +bool PowerCC26XX_calibrate(unsigned int arg); + +/*! + * @brief The Wait for interrupt (WFI) policy + * + * This is a lightweight Power Policy which simply invokes CPU wait for + * interrupt. + * + * This policy can be selected statically via the policyFxn pointer in the + * PowerCC26XX_Config structure, or dynamically at runtime, via + * Power_setPolicy(). + */ +void PowerCC26XX_doWFI(void); + +/*! + * @brief Get the handle of the Clock object used for scheduling device + * wakeups + * + * During initialization, the Power Manager creates a Clock object that a + * Power Policy can use to schedule device wakeups. This function can + * be called by a policy function to get the handle of this pre-allocated + * Clock object. + * + * @return The handle of the Clock object + */ +ClockP_Handle PowerCC26XX_getClockHandle(void); + +/*! + * @brief Get the estimated HF crystal oscillator (XOSC_HF) startup delay, + * for a given delay from now, until startup is initiated + * + * @param timeUntilWakeupInMs The estimated time until the next wakeup + * event, in units of milliseconds + * + * @return The estimated HF crystal oscillator startup latency, in + * units of microseconds. + */ +uint32_t PowerCC26XX_getXoscStartupTime(uint32_t timeUntilWakeupInMs); + +/*! + * @brief Explicitly trigger RC oscillator calibration + * + * When enabled, RCOSC calibration is normally triggered upon each device + * wakeup from STANDBY. To trigger more frequent calibration, an application + * can explicitly call this function, to initiate an immediate calibration + * cycle. + * + * @return true if calibration was actually initiated otherwise false + */ +bool PowerCC26XX_injectCalibration(void); + +/*! + * @brief Function to specify when RCOSC calibration is to be disabled + * + * This function should be specified as the 'calibrateFxn' in the + * PowerCC26XX_Config structure when RCOSC calibration is to be disabled. + * + * Note that the reason a function pointer is used here (versus a simple + * Boolean) is so that references to internal calibration subroutines can be + * removed, to eliminate pulling the calibration code into the application + * image; this enables a significant reduction in memory footprint when + * calibration is disabled. + * + * @param arg used internally + * + * @return used internally + */ +bool PowerCC26XX_noCalibrate(unsigned int arg); + +/*! + * @brief Check if the XOSC_HF is stable and ready to be switched to + * + * @pre Set PowerCC26XX_SWITCH_XOSC_HF_MANUALLY in the early standby + * wakeup notification. + * + * This function should be called when using the + * PowerCC26XX_SWITCH_XOSC_HF_MANUALLY power constraint to ensure that + * the XOSC_HF is stable before switching to it. + * + * \sa PowerCC26XX_switchXOSC_HF() + */ +bool PowerCC26XX_isStableXOSC_HF(void); + +/*! + * @brief Switch the HF clock source to XOSC_HF + * + * @pre PowerCC26XX_switchXOSC_HF() returns true. + * + * This function should only be called when using the + * PowerCC26XX_SWITCH_XOSC_HF_MANUALLY power constraint after ensuring + * the XOSC_HF is stable. + * If the driver cannot switch to the XOSC_HF despite the crystal being + * stable, a clock will be scheduled in the future and the callback will + * try to switch again. + * + * \sa PowerCC26XX_isStableXOSC_HF() + */ +void PowerCC26XX_switchXOSC_HF(void); + +/*! + * @brief The STANDBY Power Policy + * + * This is an agressive Power Policy, which considers active constraints, + * sleep state transition latencies, and time until the next scheduled + * work, and automatically transitions the device into the deepest sleep state + * possible. + * + * The first goal is to enter STANDBY; if that is not appropriate + * given current conditions (e.g., the sleep transition latency is greater + * greater than the time until the next scheduled Clock event), then + * the secondary goal is the IDLE state; if that is disallowed (e.g., if + * the PowerCC26XX_DISALLOW_IDLE constraint is declared), then the policy + * will fallback and simply invoke WFI, to clock gate the CPU until the next + * interrupt. + * + * In order for this policy to run, it must be selected as the Power + * Policy (either by being specified as the 'policyFxn' in the + * PowerCC26XX_Config structure, or specified at runtime with + * Power_setPolicy()), and the Power Policy must be enabled (either via + * 'enablePolicy' in the PowerCC26XX_Config structure, or via a call to + * Power_enablePolicy() at runtime). + */ +void PowerCC26XX_standbyPolicy(void); + +void PowerCC26XX_schedulerDisable(void); +void PowerCC26XX_schedulerRestore(void); + +#define Power_getPerformanceLevel(void) 0 +#define Power_setPerformanceLevel(level) Power_EFAIL + +#ifdef __cplusplus +} +#endif + +#endif /* POWER_CC26XX_ */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26XX_calibrateRCOSC.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26XX_calibrateRCOSC.c new file mode 100644 index 0000000..3ec874e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26XX_calibrateRCOSC.c @@ -0,0 +1,820 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQueueNTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC26XX_calibrateRCOSC.c ======== + */ + +#include + +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_aux_evctl.h) +#include DeviceFamily_constructPath(inc/hw_aux_smph.h) +#include DeviceFamily_constructPath(inc/hw_aux_wuc.h) +#include DeviceFamily_constructPath(inc/hw_aux_tdc.h) +#include DeviceFamily_constructPath(inc/hw_ddi_0_osc.h) +#include DeviceFamily_constructPath(inc/hw_ddi.h) +#include DeviceFamily_constructPath(inc/hw_ccfg.h) +#include DeviceFamily_constructPath(driverlib/aon_batmon.h) +#include DeviceFamily_constructPath(driverlib/ddi.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/osc.h) +#include DeviceFamily_constructPath(driverlib/gpio.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/aux_wuc.h) + +#define AUX_TDC_SEMAPHORE_NUMBER 1 /* semaphore 1 protects TDC */ +#define NUM_RCOSC_LF_PERIODS_TO_MEASURE 32 /* x RCOSC_LF periods vs XOSC_HF */ +#define NUM_RCOSC_HF_PERIODS_TO_MEASURE 1 /* x RCOSC_HF periods vs XOSC_HF */ +#define ACLK_REF_SRC_RCOSC_HF 0 /* Use RCOSC_HF for ACLK REF */ +#define ACLK_REF_SRC_RCOSC_LF 2 /* Use RCOSC_LF for ACLK REF */ +#define SCLK_LF_OPTION_RCOSC_LF 3 /* defined in cc26_ccfg.xls */ +#define RCOSC_HF_LOW_THRESHOLD_TDC_VALUE 1535 /* If TDC value is within threshold range, no need for another TDC measurement */ +#define RCOSC_HF_PERFECT_TDC_VALUE 1536 /* RCOSC_HF runs at perfect 48 MHz when ending up with this TDC value */ +#define RCOSC_HF_HIGH_THRESHOLD_TDC_VALUE 1537 /* If TDC value is within threshold range, no need for another TDC measurement */ + +#define DDI_0_OSC_O_CTL1_LOCAL 0x00000004 /* offset */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M 0x007C0000 /* mask */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S 18 /* shift */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_M 0x00020000 /* mask */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_S 17 /* shift */ +#define DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M 0x00000C00 /* offset */ +#define DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S 10 /* shift */ + +/* AUX ISR states */ +#define WAIT_SMPH 0 /* just took SMPH, start RCOSC_LF */ +#define CAL_RCOSC_LF 1 /* just finished RCOSC_LF, start first RCOSC_HF */ +#define CAL_RCOSC_HF1 2 /* just finished 1st RCOSC_HF, start 2nd */ +#define CAL_RCOSC_HF2 3 /* just finished 2nd RCOSC_HF, decide best */ + +/* calibration steps */ +#define STEP_TDC_INIT_1 1 +#define STEP_TDC_INIT_2 2 +#define STEP_CAL_LF_1 3 +#define STEP_CAL_LF_2 4 +#define STEP_CAL_LF_3 5 +#define STEP_CAL_HF1_1 6 +#define STEP_CAL_HF1_2 7 +#define STEP_CAL_HF1_3 8 +#define STEP_CAL_HF2_1 9 +#define STEP_CAL_HF2_2 10 +#define STEP_CLEANUP_1 11 +#define STEP_CLEANUP_2 12 + +/* macros */ +#define Min(a,b) (((a)<(b))?(a):(b)) +#define Max(a,b) (((a)>(b))?(a):(b)) +#define Abs(x) ((x) < 0 ? -(x) : (x)) +#define Scale_rndInf(x) ((3 * (x) + (((x) < 0) ? -2 : 2)) / 4) + +#define INSTRUMENT 0 + +#if INSTRUMENT +volatile unsigned int gotSEM = 0; +volatile unsigned int calLFi = 0; +volatile unsigned int calHF1i = 0; +volatile unsigned int calHF2i = 0; +volatile bool doneCal = false; +unsigned int tdcResult_LF = 0; +unsigned int tdcResult_HF1 = 0; +unsigned int tdcResult_HF2 = 0; +unsigned int numISRs = 0; +unsigned int calClocks = 0; +#endif + +/* Forward declarations */ +static bool getTdcSemaphore(); +static void updateSubSecInc(uint32_t tdcResult); +static void calibrateRcoscHf1(int32_t tdcResult); +static void calibrateRcoscHf2(int32_t tdcResult); +void PowerCC26XX_doCalibrate(void); + +/* Externs */ +extern PowerCC26XX_ModuleState PowerCC26XX_module; +extern const PowerCC26XX_Config PowerCC26XX_config; + +/* + * ======== PowerCC26XX_initiateCalibration ======== + * Initiate calibration of RCOSC_LF and RCOSCHF + */ +bool PowerCC26XX_initiateCalibration() +{ + unsigned int hwiKey; + bool busy = false; + bool status; + bool gotSem; + + if ((PowerCC26XX_module.calLF == false) && + (PowerCC26XX_config.calibrateRCOSC_HF == false)) { + return (false); + } + + /* make sure calibration is not already in progress */ + hwiKey = HwiP_disable(); + + if (PowerCC26XX_module.busyCal == false) { + PowerCC26XX_module.busyCal = true; + } + else { + busy = true; + } + + HwiP_restore(hwiKey); + + if (busy == true) { + return (false); + } + +#if INSTRUMENT + gotSEM = 0; + calLFi = 0; + calHF1i = 0; + calHF2i = 0; + doneCal = false; +#endif + + /* set contraint to prohibit standby during calibration sequence */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* set dependency to keep XOSC_HF active during calibration sequence */ + Power_setDependency(PowerCC26XX_XOSC_HF); + + /* initiate acquisition of semaphore protecting TDC */ + gotSem = getTdcSemaphore(); + + /* if didn't acquire semaphore, must wait for autotake ISR */ + if (gotSem == false) { + PowerCC26XX_module.hwiState = WAIT_SMPH; + status = false; /* false: don't do anything else until acquire SMPH */ + } + + /* else, semaphore acquired, OK to proceed with first measurement */ + else { +#if INSTRUMENT + gotSEM = 1; +#endif + status = true; /* true: OK to start first measurement */ + } + + return (status); +} + +/* + * ======== PowerCC26XX_auxISR ======== + * ISR for the AUX combo interrupt event. Implements Hwi state machine to + * step through the RCOSC calibration steps. + */ +void PowerCC26XX_auxISR(uintptr_t arg) +{ + uint32_t tdcResult; + +#if INSTRUMENT + numISRs++; +#endif + + /* + * disable all events that are part of AUX_COMBINED_INTERRUPT. + * This interrupt is reserved for use during RCOSC calibration. + * Other AUX perihperals that want to generate interrupts to CM3 + * must use dedicated interrupt lines or go through AON combined. + */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = 0; + + /* ****** state = WAIT_SMPH: arrive here if just took the SMPH ****** */ + if (PowerCC26XX_module.hwiState == WAIT_SMPH) { +#if INSTRUMENT + gotSEM = 1; +#endif + } + + /* **** state = CAL_RCOSC_LF: here when just finished LF counting **** */ + else if (PowerCC26XX_module.hwiState == CAL_RCOSC_LF) { + + tdcResult = HWREG(AUX_TDC_BASE + AUX_TDC_O_RESULT); + +#if INSTRUMENT + tdcResult_LF = tdcResult; +#endif + /* update the RTC SUBSECINC register based on LF measurement result */ + updateSubSecInc(tdcResult); +#if INSTRUMENT + calLFi = 1; +#endif + /* if doing HF calibration initiate it now */ + if (PowerCC26XX_config.calibrateRCOSC_HF) { + PowerCC26XX_module.calStep = STEP_CAL_LF_3; /* next: trigger LF */ + } + + /* else, start cleanup */ + else { + PowerCC26XX_module.calStep = STEP_CLEANUP_1; /* next: cleanup */ + } + } + + /* ****** state = CAL_RCOSC_HF1: here when just finished 1st RCOSC_HF */ + else if (PowerCC26XX_module.hwiState == CAL_RCOSC_HF1) { + + tdcResult = HWREG(AUX_TDC_BASE + AUX_TDC_O_RESULT); + +#if INSTRUMENT + tdcResult_HF1 = tdcResult; + calHF1i = 1; +#endif + + /* use first HF measurement to setup new trim values */ + calibrateRcoscHf1(tdcResult); + + /* if HF setting perfect, nothing more to do, calibration is done */ + if ((tdcResult >= RCOSC_HF_LOW_THRESHOLD_TDC_VALUE) && + (tdcResult <= RCOSC_HF_HIGH_THRESHOLD_TDC_VALUE)) { + PowerCC26XX_module.calStep = STEP_CLEANUP_1; /* next: cleanup */ + } + + /* else, tweak trims, initiate another HF measurement */ + else { + + PowerCC26XX_module.calStep = STEP_CAL_HF1_3; /* next: HF meas. #2 */ + } + } + + /* ****** state = just finished second RCOSC_HF measurement ****** */ + else if (PowerCC26XX_module.hwiState == CAL_RCOSC_HF2) { + + tdcResult = HWREG(AUX_TDC_BASE + AUX_TDC_O_RESULT); + +#if INSTRUMENT + tdcResult_HF2 = tdcResult; +#endif + /* look for improvement on #2, else revert to previous trim values */ + calibrateRcoscHf2(tdcResult); + + PowerCC26XX_module.calStep = STEP_CLEANUP_1; /* next: cleanup */ + } + + /* do the next calibration step... */ + PowerCC26XX_doCalibrate(); +} + +/* + * ======== PowerCC26XX_doCalibrate ======== + */ +void PowerCC26XX_doCalibrate(void) +{ + switch (PowerCC26XX_module.calStep) { + + case STEP_TDC_INIT_1: + + /* turn on clock to TDC module */ + AUXWUCClockEnable(AUX_WUC_TDCIF_CLOCK); + + /* set saturation config to 2^24 */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_SATCFG) = + AUX_TDC_SATCFG_LIMIT_R24; + + /* set start and stop trigger sources and polarity */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGSRC) = + (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF | + AUX_TDC_TRIGSRC_STOP_POL_HIGH) | + (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF | + AUX_TDC_TRIGSRC_START_POL_HIGH); + + /* set TDC_SRC clock to be XOSC_HF/2 = 24 MHz */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S, 2); + + /* read back to ensure no race condition between OSC_DIG and AUX_WUC */ + DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M, DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S); + + /* set AUX_WUC:TDCCLKCTL.REQ... */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) = AUX_WUC_TDCCLKCTL_REQ; + + /* set next state */ + PowerCC26XX_module.calStep = STEP_TDC_INIT_2; + + /* start Clock object to delay while wait for ACK */ + ClockP_start(ClockP_handle(&PowerCC26XX_module.calClockStruct)); + + break; + + case STEP_TDC_INIT_2: + + /* Enable trig count */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGCNTCFG) = + AUX_TDC_TRIGCNTCFG_EN; + + /* if LF calibration enabled start LF measurement */ + if (PowerCC26XX_module.calLF) { + + /* clear UPD_REQ, new sub-second increment is NOT available */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL) = 0; + + /* set next Swi state */ + PowerCC26XX_module.calStep = STEP_CAL_LF_1; + } + + /* else, start first HF measurement */ + else { + /* set next Swi state */ + PowerCC26XX_module.calStep = STEP_CAL_HF1_1; + } + + /* abort TDC */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_ABORT; + + /* clear AUX_WUC:REFCLKCTL.REQ... */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = 0; + + /* if not ready, start Clock object to delay while wait for ACK */ + if (HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) & + AUX_WUC_REFCLKCTL_ACK) { + + /* start Clock object to delay while wait for ACK */ + ClockP_start(ClockP_handle(&PowerCC26XX_module.calClockStruct)); + + break; + } + + /* else, if ready now, fall thru to next step ... */ + + + case STEP_CAL_LF_1: + case STEP_CAL_HF1_1: + case STEP_CAL_HF2_1: + + if (PowerCC26XX_module.calStep == STEP_CAL_LF_1) { + + /* set the ACLK reference clock */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S, + ACLK_REF_SRC_RCOSC_LF); + + /* set next Swi state */ + PowerCC26XX_module.calStep = STEP_CAL_LF_2; + } + else { + + /* set the ACLK reference clock */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S, + ACLK_REF_SRC_RCOSC_HF); + + /* set next Swi state */ + if (PowerCC26XX_module.calStep == STEP_CAL_HF1_1) { + PowerCC26XX_module.calStep = STEP_CAL_HF1_2; + } + else { + PowerCC26XX_module.calStep = STEP_CAL_HF2_2; + } + } + + /* set AUX_WUC:REFCLKCTL.REQ */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = AUX_WUC_REFCLKCTL_REQ; + + /* start Clock object to delay while wait for ACK */ + ClockP_start(ClockP_handle(&PowerCC26XX_module.calClockStruct)); + + break; + + case STEP_CAL_LF_2: + case STEP_CAL_HF1_2: + case STEP_CAL_HF2_2: + + if (PowerCC26XX_module.calStep == STEP_CAL_LF_2) { + + /* Set number of periods of ACLK to count */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGCNTLOAD) = + NUM_RCOSC_LF_PERIODS_TO_MEASURE; + + /* set next Hwi state before triggering TDC */ + PowerCC26XX_module.hwiState = CAL_RCOSC_LF; + } + else { + + /* Set number of periods of ACLK to count */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGCNTLOAD) = + NUM_RCOSC_HF_PERIODS_TO_MEASURE; + + /* set next Hwi state before triggering TDC */ + if (PowerCC26XX_module.calStep == STEP_CAL_HF2_2) { + PowerCC26XX_module.hwiState = CAL_RCOSC_HF2; + } + else { + PowerCC26XX_module.hwiState = CAL_RCOSC_HF1; + } + } + + /* Reset/clear result of TDC */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_CLR_RESULT; + + /* Clear possible pending interrupt source */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = + AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE; + + /* Enable TDC done interrupt as part of AUX_COMBINED interrupt */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = + AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE; + + /* Run TDC (start synchronously) */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_CTL) = + AUX_TDC_CTL_CMD_RUN_SYNC_START; + + break; + + case STEP_CAL_LF_3: + case STEP_CAL_HF1_3: + + /* set next Swi state */ + if (PowerCC26XX_module.calStep == STEP_CAL_LF_3) { + PowerCC26XX_module.calStep = STEP_CAL_HF1_1; + } + else { + PowerCC26XX_module.calStep = STEP_CAL_HF2_1; + } + + /* clear AUX_WUC:REFCLKCTL.REQ... */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = 0; + + /* start Clock object to delay while wait for ACK */ + ClockP_start(ClockP_handle(&PowerCC26XX_module.calClockStruct)); + + break; + + case STEP_CLEANUP_1: + + /* release the TDC clock request */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) = 0; + + /* release the TDC reference clock request */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = 0; + + /* set next state */ + PowerCC26XX_module.calStep = STEP_CLEANUP_2; + + /* start Clock object to delay while wait for ACK */ + ClockP_start(ClockP_handle(&PowerCC26XX_module.calClockStruct)); + + break; + + case STEP_CLEANUP_2: + + /* + * Disable all interrupts as part of AUX_COMBINED interrupt + * Once we release semaphore, the sensor controller is allowed + * to use the TDC. When it does, we must ensure that this + * does not cause any unexpected interrupts to the CM3. + */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = 0; + + /* release AUX semaphore */ + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH1) = 1; + + /* release the power down constraints and XOSC_HF dependency */ + Power_releaseDependency(PowerCC26XX_XOSC_HF); + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* set next state */ + PowerCC26XX_module.calStep = STEP_TDC_INIT_1; + +#if INSTRUMENT + doneCal = true; + calHF2i = 1; +#endif + PowerCC26XX_module.busyCal = false; + break; + + default: + for (;;) { + } + } +} + +/* + * ======== PowerCC26XX_RCOSC_clockFunc ======== + */ +void PowerCC26XX_RCOSC_clockFunc(uintptr_t arg) +{ +#if INSTRUMENT + calClocks++; +#endif + + switch (PowerCC26XX_module.calStep) { + + case STEP_TDC_INIT_2: + /* finish wait for AUX_WUC:TDCCLKCTL.ACK to be set ... */ + while(!(HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) & + AUX_WUC_TDCCLKCTL_ACK)); + break; + + case STEP_CAL_LF_1: + case STEP_CAL_HF1_1: + case STEP_CAL_HF2_1: + /* finish wait for AUX_WUC:REFCLKCTL.ACK to be cleared ... */ + while(HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) & + AUX_WUC_REFCLKCTL_ACK); + break; + + case STEP_CAL_LF_2: + case STEP_CAL_HF1_2: + case STEP_CAL_HF2_2: + /* finish wait for AUX_WUC:REFCLKCTL.ACK to be set ... */ + while(!(HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) & + AUX_WUC_REFCLKCTL_ACK)); + break; + + case STEP_CLEANUP_2: + /* finish wait for AUX_WUC:TDCCLKCTL.ACK to be cleared ... */ + while ((HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) & + AUX_WUC_TDCCLKCTL_ACK)); + /* finish wait for AUX_WUC:REFCLKCTL.ACK to be cleared ... */ + while(HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) & + AUX_WUC_REFCLKCTL_ACK); + break; + + default: + for (;;) { + } + } + + PowerCC26XX_doCalibrate(); +} + +/* + * ======== getTdcSemaphore ======== + * Get TDC semaphore (number 1) + */ +static bool getTdcSemaphore() +{ + unsigned int own; + + /* try to acquire SMPH */ + own = HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH1); + + /* if acquired SMPH: done */ + if (own != 0) { + return (true); + } + + /* clear the interrupt source, can only be cleared when we don't have semaphore */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = + AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE; + + /* + * else, did not acquire the semaphore, enable SMPH_AUTOTAKE_DONE event + * (don't OR, write entire register, no other interrupts can be enabled!) + */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = + AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE; + + /* start AUTOTAKE of semaphore for TDC access */ + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_AUTOTAKE) = AUX_TDC_SEMAPHORE_NUMBER; + + return (false); +} + +/* + * ======== updateSubSecInc ======== + * Update the SUBSECINC register based on measured RCOSC_LF frequency + */ +static void updateSubSecInc(uint32_t tdcResult) +{ + int32_t newSubSecInc; + uint32_t oldSubSecInc; + uint32_t subSecInc; + uint32_t ccfgModeConfReg; + int32_t hposcOffset; + int32_t hposcOffsetInv; + + /* + * Calculate the new SUBSECINC + * Here's the formula: AON_RTC:SUBSECINC = (45813 * NR) / 256 + * Based on measuring 32 LF clock periods + */ + newSubSecInc = (45813 * tdcResult) / 256; + + /* TODO: Replace with ccfgread driverlib call */ + ccfgModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + /* Compensate HPOSC drift if HPOSC is in use */ + if(((ccfgModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S) == 1) { + /* Get the HPOSC relative offset at this temperature */ + hposcOffset = OSC_HPOSCRelativeFrequencyOffsetGet(AONBatMonTemperatureGetDegC()); + /* Convert to RF core format */ + hposcOffsetInv = OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(hposcOffset); + /* Adjust SUBSECINC */ + newSubSecInc += (((newSubSecInc >> 4) * (hposcOffsetInv >> 3)) >> 15); + } + + /* Apply filter, but not for first calibration */ + if (PowerCC26XX_module.firstLF) { + /* Don't apply filter first time, to converge faster */ + subSecInc = newSubSecInc; + /* No longer first measurement */ + PowerCC26XX_module.firstLF = false; + } + else { + /* Read old SUBSECINC value */ + oldSubSecInc = HWREG(AON_RTC_BASE + AON_RTC_O_SUBSECINC) & 0x00FFFFFF; + /* Apply filter, 0.5 times old value, 0.5 times new value */ + subSecInc = (oldSubSecInc * 1 + newSubSecInc * 1) / 2; + } + + /* Update SUBSECINC values */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC0) = subSecInc; + HWREG(AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC1) = subSecInc >> 16; + + /* update to use new values */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL) = + AUX_WUC_RTCSUBSECINCCTL_UPD_REQ; +} + +/* + * ======== PowerCC26XX_calibrateRcoscHf1 ======== + * Calibrate RCOSC_HF agains XOSC_HF: compute and setup new trims + */ +static void calibrateRcoscHf1(int32_t tdcResult) +{ + /* *** STEP 1: Find RCOSC_HF-XOSC_HF frequency offset with current trim settings */ + /* Read in current trim settings */ + PowerCC26XX_module.nCtrimCurr = + (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RCOSCHFCTL) & + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M) >> + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S; + + PowerCC26XX_module.nCtrimFractCurr = + (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL1_LOCAL) + & DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M) >> + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S; + + PowerCC26XX_module.nRtrimCurr = + (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ATESTCTL) + & DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M) >> + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S; + + + /* + * Find RCOSC_HF-XOSC_HF frequency offset with current trim settings + * Positive value => RCOSC_HF runs slow, CTRIM(FRACT) should be increased + * Negative value => RCOSC_HF runs fast, CTRIM(FRACT) should be decreased + * Resolution: 31.25 kHz; CTRIMFRACT resolution ~30 kHz + */ + PowerCC26XX_module.nDeltaFreqCurr = (int32_t) tdcResult - RCOSC_HF_PERFECT_TDC_VALUE; + + /* *** STEP 2: Attempt to calculate more optimal settings */ + if (PowerCC26XX_module.nDeltaFreqCurr == 0) { + /* If perfect, don't perform second measurement and keep current settings */ + PowerCC26XX_module.bRefine = false; + return; + } + if (PowerCC26XX_module.bRefine) { + /* + * Trying to find better match across CTRIM/RTRIM. Due to mismatches the + * first try might not have been more optimal than the current setting. + * Continue refining, starting from stored values + */ + } else { + /* Start from current values */ + PowerCC26XX_module.nCtrimFractNew = PowerCC26XX_module.nCtrimFractCurr; + PowerCC26XX_module.nCtrimNew = PowerCC26XX_module.nCtrimCurr; + PowerCC26XX_module.nRtrimNew = PowerCC26XX_module.nRtrimCurr; + PowerCC26XX_module.nDeltaFreqNew = PowerCC26XX_module.nDeltaFreqCurr; + } + + /* + * Calculate change to CTRIMFRACT with safe assumptions of gain, + * apply delta to current CTRIMFRACT and convert to valid CTRIM/CTRIMFRACT + */ + PowerCC26XX_module.nCtrimFractNew = PowerCC26XX_module.nCtrimFractNew + + Scale_rndInf(PowerCC26XX_module.nDeltaFreqNew); + PowerCC26XX_module.nCtrimNew = PowerCC26XX_module.nCtrimCurr; + + /* One step of CTRIM is about 500 kHz, so limit to one CTRIM step */ + if (PowerCC26XX_module.nCtrimFractNew < 1) { + if (PowerCC26XX_module.nRtrimNew == 3) { + /* We try the slow RTRIM in this CTRIM first */ + PowerCC26XX_module.nCtrimFractNew = Max(1, PowerCC26XX_module.nCtrimFractNew + 21); + PowerCC26XX_module.nRtrimNew = 0; + } + else { + /* Step down one CTRIM and use fast RTRIM */ + PowerCC26XX_module.nCtrimFractNew = Max(1, PowerCC26XX_module.nCtrimFractNew + 32 - 21); + PowerCC26XX_module.nCtrimNew = Max(0, PowerCC26XX_module.nCtrimNew - 1); + PowerCC26XX_module.nRtrimNew = 3; + } + } + else if (PowerCC26XX_module.nCtrimFractNew > 30) { + if (PowerCC26XX_module.nRtrimNew == 0) { + /* We try the slow RTRIM in this CTRIM first */ + PowerCC26XX_module.nCtrimFractNew = Min(30, PowerCC26XX_module.nCtrimFractNew - 21); + PowerCC26XX_module.nRtrimNew = 3; + } + else { + /* Step down one CTRIM and use fast RTRIM */ + PowerCC26XX_module.nCtrimFractNew = Min(30, PowerCC26XX_module.nCtrimFractNew - 32 + 21); + PowerCC26XX_module.nCtrimNew = Min(0x3F, PowerCC26XX_module.nCtrimNew + 1); + PowerCC26XX_module.nRtrimNew = 0; + } + } + else + { + /* We're within sweet spot of current CTRIM => no change */ + } + + /* Find RCOSC_HF vs XOSC_HF frequency offset with new trim settings */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RCOSCHFCTL, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S, + PowerCC26XX_module.nCtrimNew); + + /* Enable RCOSCHFCTRIMFRACT_EN */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL1_LOCAL, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_M, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_S, + 1); + + /* Modify CTRIM_FRACT */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL1_LOCAL, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S, + PowerCC26XX_module.nCtrimFractNew); + + /* Modify RTRIM */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ATESTCTL, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S, + PowerCC26XX_module.nRtrimNew); +} + +/* + * ======== Power_calibrateRcoscHf2 ======== + * Calibrate RCOSC_HF agains XOSC_HF: determine better result, set new trims + */ +static void calibrateRcoscHf2(int32_t tdcResult) +{ + + PowerCC26XX_module.nDeltaFreqNew = (int32_t) tdcResult - RCOSC_HF_PERFECT_TDC_VALUE; + /* Calculate new delta freq */ + + /* *** STEP 4: Determine whether the new settings are better or worse */ + if (Abs(PowerCC26XX_module.nDeltaFreqNew) <= Abs(PowerCC26XX_module.nDeltaFreqCurr)) { + /* New settings are better or same -> make current by keeping in registers */ + PowerCC26XX_module.bRefine = false; + } + else { + /* First measurement was better than second, restore current settings */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RCOSCHFCTL, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S, + PowerCC26XX_module.nCtrimCurr); + + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL1_LOCAL, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S, + PowerCC26XX_module.nCtrimFractCurr); + + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ATESTCTL, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S, + PowerCC26XX_module.nRtrimCurr); + + /* Enter a refinement mode where we keep searching for better matches */ + PowerCC26XX_module.bRefine = true; + } + +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pwm/PWMTimerCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pwm/PWMTimerCC26XX.c new file mode 100644 index 0000000..ec8a943 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pwm/PWMTimerCC26XX.c @@ -0,0 +1,494 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file PWMTimerCC26XX.c + * @brief CC26XX/CC13XX implementation of ti/drivers/PWM.h + * + * # Overview # + * CC26XX/CC13XX PWM driver using the built-in GPTimer. + * + * # Note # + * The driver requires the GPTimer bit GPT.TnMR.TnPLO to be set. + * Using this, the PWM output will be always low when load=match and always + * high when match>load. Setting match > load is used for 100% duty cycle + * + ******************************************************************************* + */ + +#include +#include + +#include +#include + +#include "ti/drivers/PWM.h" +#include "ti/drivers/pwm/PWMTimerCC26XX.h" +#include "ti/drivers/timer/GPTimerCC26XX.h" + +/* PWMTimerCC26XX defines */ +#define PWM_COUNT_MAX 0xFFFFFE /* GPTimer has maximum 24 bits incl prescaler. + Max count is set to (2^24 - 2) to allow for + a glitch free 100% duty cycle at max period count.*/ + +/*! + * @brief If the PWM period is lower than this value, setDutyAndPeriod + * will briefly disable the PWM channel to set the new values. + * + * This is to prevent the case where the period, but not the duty, is + * applied before the timeout and the next cycle is in an undetermined state. + */ +#define PWM_PERIOD_FOR_GLITCH_PROTECTION 0xF + +/* PWMTimerCC26XX functions */ +void PWMTimerCC26XX_close(PWM_Handle handle); +int_fast16_t PWMTimerCC26XX_control(PWM_Handle handle, uint_fast16_t cmd, + void * arg); +void PWMTimerCC26XX_init(PWM_Handle handle); +PWM_Handle PWMTimerCC26XX_open(PWM_Handle handle, PWM_Params *params); +int_fast16_t PWMTimerCC26XX_setDuty(PWM_Handle handle, uint32_t dutyValue); +int_fast16_t PWMTimerCC26XX_setPeriod(PWM_Handle handle, uint32_t periodValue); +int_fast16_t PWMTimerCC26XX_setDutyAndPeriod(PWM_Handle handle, uint32_t dutyValue, uint32_t periodValue); +void PWMTimerCC26XX_start(PWM_Handle handle); +void PWMTimerCC26XX_stop(PWM_Handle handle); + +/* PWMTimerCC26XX internal functions */ +static uint32_t PWMTimerCC26XX_getperiodCounts(PWM_Period_Units periodUnit, uint32_t periodValue); +static int32_t PWMTimerCC26XX_getdutyCounts(uint32_t periodCounts, PWM_Duty_Units dutyUnit, uint32_t dutyValue); + +/* PWM function table for PWMTimerCC26XX implementation */ +const PWM_FxnTable PWMTimerCC26XX_fxnTable = +{ + PWMTimerCC26XX_close, + PWMTimerCC26XX_control, + PWMTimerCC26XX_init, + PWMTimerCC26XX_open, + PWMTimerCC26XX_setDuty, + PWMTimerCC26XX_setPeriod, + PWMTimerCC26XX_setDutyAndPeriod, + PWMTimerCC26XX_start, + PWMTimerCC26XX_stop, +}; + + +/* PIN configuration used for PWMTimerCC26XX implementation. Handle is shared + across all PWM peripherals + */ +static PIN_Handle hPins = NULL; +static PIN_State pinState; + +/*! + * @brief PWM CC26XX initialization + * + * This is a dummy function since driver implementation assumes + * the handle->object->isOpen flag is set to 0 at boot + * + * @pre Calling context: Hwi, Swi, Task, Main + * + * @param handle A SPI_Handle + * + */ +void PWMTimerCC26XX_init(PWM_Handle handle) +{ +} + + +/* Open the specific PWM peripheral with the settings given in params. + Will return a PWM handle if successfull, NULL if failed. + PWM will output configured idle level when opened. + Function sets a dependency on the underlying timer and adds the PWM pin to + its internal PIN handle. + */ +PWM_Handle PWMTimerCC26XX_open(PWM_Handle handle, PWM_Params *params) +{ + PWMTimerCC26XX_HwAttrs const *hwAttrs = handle->hwAttrs; + PWMTimerCC26XX_Object *object = handle->object; + + /* Check if PWM already open */ + uint32_t key = HwiP_disable(); + if (object->isOpen) + { + HwiP_restore(key); + DebugP_log1("PWM_open(%x): Unit already in use.", (uintptr_t) handle); + return NULL; + } + object->isOpen = 1; + HwiP_restore(key); + + /* Open timer resource */ + GPTimerCC26XX_Params timerParams; + GPTimerCC26XX_Params_init(&timerParams); + timerParams.width = GPT_CONFIG_16BIT; + timerParams.mode = GPT_MODE_PWM; + timerParams.debugStallMode = GPTimerCC26XX_DEBUG_STALL_OFF; + timerParams.matchTiming = GPTimerCC26XX_SET_MATCH_ON_TIMEOUT; + GPTimerCC26XX_Handle hTimer = GPTimerCC26XX_open(hwAttrs->gpTimerUnit, &timerParams); + + /* Fail if cannot open timer */ + if (hTimer == NULL) + { + DebugP_log2("PWM_open(%x): Timer unit (%d) already in use.", (uintptr_t) handle, hwAttrs->gpTimerUnit); + object->isOpen = false; + return NULL; + } + + /* Open pin resource */ + PIN_Config pinConfig; + + /* Initial open of pin handle with no pins in it. Should never fail. */ + if (hPins == NULL) + { + pinConfig = PIN_TERMINATE; + hPins = PIN_open(&pinState, &pinConfig); + } + + uint32_t idleLevel = PIN_GPIO_HIGH; + if (params->idleLevel == PWM_IDLE_LOW) + { + idleLevel = PIN_GPIO_LOW; + } + + /* Generate pin config for PWM pin. */ + pinConfig = hwAttrs->pwmPin | PIN_INPUT_DIS | PIN_GPIO_OUTPUT_EN | idleLevel | + PIN_PUSHPULL | PIN_DRVSTR_MAX; + + /* Fail if cannot add pin */ + if (PIN_add(hPins, pinConfig) != PIN_SUCCESS) + { + DebugP_log2("PWM_open(%x): PIN (%d) already in use.", (uintptr_t) handle, hwAttrs->pwmPin); + GPTimerCC26XX_close(hTimer); + object->isOpen = false; + return NULL; + } + + /* Store configuration to object */ + object->periodUnit = params->periodUnits; + object->periodValue = params->periodValue; + object->dutyUnit = params->dutyUnits; + object->dutyValue = params->dutyValue; + object->idleLevel = params->idleLevel; + object->hTimer = hTimer; + + /* Configure PWM period*/ + uint32_t period = object->periodValue; + + /* This will also set the duty cycle */ + if (PWMTimerCC26XX_setPeriod(handle, period) != PWM_STATUS_SUCCESS) + { + DebugP_log1("PWM_open(%x): Failed setting period", (uintptr_t) handle); + PIN_remove(hPins, hwAttrs->pwmPin); + GPTimerCC26XX_close(hTimer); + object->isOpen = false; + return NULL; + } + + DebugP_log1("PWM_open(%x): Opened with great success!", (uintptr_t) handle); + return handle; +} + + +/* PWMTimerCC26XX_setPeriod - + Sets / update PWM period. Unit must already be defined in object. + Also updates duty cycle. + */ +int_fast16_t PWMTimerCC26XX_setPeriod(PWM_Handle handle, uint32_t periodValue) +{ + PWMTimerCC26XX_Object *object = handle->object; + /* Copy current duty value and store new period */ + uint32_t dutyValue = object->dutyValue; + uint32_t newperiodCounts = PWMTimerCC26XX_getperiodCounts(object->periodUnit, periodValue); + int32_t newdutyCounts = PWMTimerCC26XX_getdutyCounts(newperiodCounts, object->dutyUnit, dutyValue); + + /* Fail if period is out of range */ + if ((newperiodCounts > PWM_COUNT_MAX) || + (newperiodCounts == 0)) + { + DebugP_log2("PWM(%x): Period (%d) is out of range", (uintptr_t) handle, periodValue); + return PWM_STATUS_INVALID_PERIOD; + } + + /* Compare to new period and fail if invalid */ + if (newperiodCounts < (newdutyCounts - 1) || (newdutyCounts < 0)) + { + DebugP_log2("PWM(%x): Period is shorter than duty (%d)", (uintptr_t) handle, periodValue); + return PWM_STATUS_INVALID_PERIOD; + } + + /* Store new period and update timer */ + object->periodValue = periodValue; + object->periodCounts = newperiodCounts; + GPTimerCC26XX_setLoadValue(object->hTimer, newperiodCounts); + + /* Store new duty cycle and update timer */ + object->dutyValue = dutyValue; + object->dutyCounts = newdutyCounts; + + GPTimerCC26XX_setMatchValue(object->hTimer, newdutyCounts); + + DebugP_log1("PWM_setPeriod(%x): Period set with great success!", (uintptr_t) handle); + return PWM_STATUS_SUCCESS; +} + +/* PWMTimerCC26XX_setDuty - + Sets / update PWM duty. Unit must already be defined in object. + Period must already be configured in object before calling this API. + */ +int_fast16_t PWMTimerCC26XX_setDuty(PWM_Handle handle, uint32_t dutyValue) +{ + PWMTimerCC26XX_Object *object = handle->object; + /* Copy current duty unit and store new period */ + PWM_Duty_Units dutyUnit = object->dutyUnit; + int32_t newdutyCounts = PWMTimerCC26XX_getdutyCounts(object->periodCounts, dutyUnit, dutyValue); + + /* Fail if duty cycle count is out of range. */ + if (newdutyCounts > PWM_COUNT_MAX) + { + DebugP_log2("PWM(%x): Duty (%d) is out of range", (uintptr_t) handle, dutyValue); + return PWM_STATUS_INVALID_DUTY; + } + + /* Error checking: + * Unit PWM_DUTY_FRACTION will always be within range + * Unit PWM_DUTY_US with value 0 will always be correct(set by getdutyCounts) + * Unit PWM_DUTY_US value != 0 needs error checking + * Unit PWM_DUTY_COUNTS needs error checking + */ + if (((newdutyCounts > (object->periodCounts + 1)) && + ((dutyUnit == PWM_DUTY_US) || (dutyUnit == PWM_DUTY_COUNTS))) || + (newdutyCounts < 0)) + { + DebugP_log2("PWM(%x): Duty (%d) is larger than period", (uintptr_t) handle, dutyValue); + return PWM_STATUS_INVALID_DUTY; + } + + /* Store new duty cycle and update timer */ + object->dutyValue = dutyValue; + object->dutyCounts = newdutyCounts; + + GPTimerCC26XX_setMatchValue(object->hTimer, newdutyCounts); + + DebugP_log1("PWM_setDuty(%x): Duty set with great success!", (uintptr_t) handle); + return PWM_STATUS_SUCCESS; +} + +/* ======== PWMTimerCC26XX_setDutyAndPeriod ======== + Sets / update PWM duty and period. Unit must already be defined in object. + */ +int_fast16_t PWMTimerCC26XX_setDutyAndPeriod (PWM_Handle handle, uint32_t dutyValue, uint32_t periodValue) +{ + uint32_t key; + bool stopped = false; + PWMTimerCC26XX_Object *object = handle->object; + + uint32_t oldPeriod = object->periodValue; + uint32_t newperiodCounts = PWMTimerCC26XX_getperiodCounts(object->periodUnit, periodValue); + int32_t newdutyCounts = PWMTimerCC26XX_getdutyCounts(newperiodCounts, object->dutyUnit, dutyValue); + + /* Fail if period is out of range or incompatible with new duty */ + if ((newperiodCounts > PWM_COUNT_MAX) || (newperiodCounts == 0) + || (newperiodCounts < (newdutyCounts - 1))) { + return PWM_STATUS_INVALID_PERIOD; + } + + /* Fail if duty cycle count is out of range. */ + if ((newdutyCounts > PWM_COUNT_MAX) || (newdutyCounts < 0)) { + return PWM_STATUS_INVALID_DUTY; + } + + /* Store new period */ + object->periodValue = periodValue; + object->periodCounts = newperiodCounts; + + /* Store new duty cycle */ + object->dutyValue = dutyValue; + object->dutyCounts = newdutyCounts; + + // Disable interrupts for register update + key = HwiP_disable(); + + if (object->isRunning && (oldPeriod <= PWM_PERIOD_FOR_GLITCH_PROTECTION || GPTimerCC26XX_getValue(object->hTimer) <= PWM_PERIOD_FOR_GLITCH_PROTECTION)) { + stopped = true; + GPTimerCC26XX_stop(object->hTimer); + } + + /* Update timer */ + GPTimerCC26XX_setLoadValue(object->hTimer, newperiodCounts); + GPTimerCC26XX_setMatchValue(object->hTimer, newdutyCounts); + + if (stopped) { + GPTimerCC26XX_start(object->hTimer); + } + + // Restore interrupts + HwiP_restore(key); + return PWM_STATUS_SUCCESS; +} + +/* Return period in timer counts */ +static uint32_t PWMTimerCC26XX_getperiodCounts(PWM_Period_Units periodUnit, uint32_t periodValue) +{ + ClockP_FreqHz freq; + ClockP_getCpuFreq(&freq); + + uint32_t periodCounts; + + switch (periodUnit) + { + case PWM_PERIOD_US: + periodCounts = ((uint64_t)freq.lo * (uint64_t)periodValue / 1000000) - 1; + break; + case PWM_PERIOD_HZ: + periodCounts = (freq.lo / periodValue) - 1; + break; + case PWM_PERIOD_COUNTS: + /* Fall through */ + default: + periodCounts = periodValue; + break; + } + return periodCounts; +} + +/* Return duty cycle in timer counts */ +static int32_t PWMTimerCC26XX_getdutyCounts(uint32_t periodCounts, PWM_Duty_Units dutyUnit, uint32_t dutyValue) +{ + ClockP_FreqHz freq; + ClockP_getCpuFreq(&freq); + + uint32_t dutyCounts; + + /* Corner case, 0% duty cycle. Set timer count to period count */ + if (dutyValue == 0) + { + dutyCounts = periodCounts; + } + else + { + /* Invert the duty cycle count to get the expected PWM signal output. */ + switch (dutyUnit) + { + case PWM_DUTY_US: + dutyCounts = periodCounts - (((uint64_t)freq.lo * (uint64_t)dutyValue / 1000000) - 1); + break; + case PWM_DUTY_FRACTION: + dutyCounts = periodCounts - ((uint64_t)dutyValue * (uint64_t)periodCounts / + PWM_DUTY_FRACTION_MAX); + break; + case PWM_DUTY_COUNTS: + /* Fall through */ + default: + dutyCounts = periodCounts - dutyValue; + break; + } + + /* Corner case: If 100% duty cycle, the resulting dutyCount will be 0, set new dutyCounts to periodCounts + 1 to create a glitch free signal. */ + if (dutyCounts == 0) + { + dutyCounts = periodCounts + 1; + } + } + return dutyCounts; +} + +/* Stop PWM output for given PWM peripheral. PWM pin will be routed + to the GPIO module to provide Idle level and timer is stopped + */ +void PWMTimerCC26XX_stop(PWM_Handle handle) +{ + PWMTimerCC26XX_HwAttrs const *hwAttrs = handle->hwAttrs; + PWMTimerCC26XX_Object *object = handle->object; + + uint32_t key = HwiP_disable(); + object->isRunning = 0; + HwiP_restore(key); + + GPTimerCC26XX_stop(object->hTimer); + /* Route PWM pin to GPIO module */ + PINCC26XX_setMux(hPins, hwAttrs->pwmPin, IOC_PORT_GPIO); +} + +/* Start PWM output for given PWM peripheral. + PWM pin will be routed to the Timer module and timer is started + */ +void PWMTimerCC26XX_start(PWM_Handle handle) +{ + PWMTimerCC26XX_HwAttrs const *hwAttrs = handle->hwAttrs; + PWMTimerCC26XX_Object *object = handle->object; + + uint32_t key = HwiP_disable(); + object->isRunning = 1; + HwiP_restore(key); + + /* Route PWM pin to timer output */ + GPTimerCC26XX_PinMux pinMux = GPTimerCC26XX_getPinMux(object->hTimer); + PINCC26XX_setMux(hPins, hwAttrs->pwmPin, pinMux); + GPTimerCC26XX_start(object->hTimer); +} + +/* Close the specific PWM peripheral. A running PWM must be stopped first. + PWM output will revert to output value given in PIN_init if any is defined. + */ +void PWMTimerCC26XX_close(PWM_Handle handle) +{ + PWMTimerCC26XX_HwAttrs const *hwAttrs = handle->hwAttrs; + PWMTimerCC26XX_Object *object = handle->object; + + /* Restore PWM pin to GPIO module with default configuration from PIN_init */ + PIN_remove(hPins, hwAttrs->pwmPin); + /* Close and delete timer handle */ + GPTimerCC26XX_close(object->hTimer); + object->hTimer = NULL; + + /* Clear isOpen flag */ + uint32_t key = HwiP_disable(); + object->isOpen = 0; + HwiP_restore(key); +} + +/* Driver specific control options. PWM peripheral must be opened before + using this API */ +int_fast16_t PWMTimerCC26XX_control(PWM_Handle handle, uint_fast16_t cmd, + void * arg) +{ + PWMTimerCC26XX_Object *object = handle->object; + int stat = PWM_STATUS_SUCCESS; + + switch (cmd) + { + case PWMTimerCC26XX_CMD_DEBUG_STALL: + GPTimerCC26XX_configureDebugStall(object->hTimer, *(GPTimerCC26XX_DebugMode *)arg); + break; + default: + stat = PWM_STATUS_UNDEFINEDCMD; + break; + } + return stat; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pwm/PWMTimerCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pwm/PWMTimerCC26XX.h new file mode 100644 index 0000000..08b74e9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pwm/PWMTimerCC26XX.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file PWMTimerCC26XX.h + * @brief PWM driver implementation for CC26XX/CC13XX + * + * # Overview # + * The general PWM API should be used in application code, i.e. PWM_open() + * should be used instead of PWMTimerCC26XX_open(). The board file will define the device + * specific config, and casting in the general API will ensure that the correct + * device specific functions are called. + * + * # General Behavior # + * Before using PWM on CC26XX: + * - The Timer HW is configured and system dependencies (for example IOs, + * power, etc.) are set by calling PWM_open(). + * + * # Error handling # + * If unsupported arguments are provided to an API returning an error code, the + * PWM configuration will *not* be updated and PWM will stay in the mode it + * was already configured to. + * + * # Power Management # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * The PWMTimerCC26XX.h driver is not explicitly setting a power constraint when the + * PWM is running to prevent standby as this is assumed to be done in the + * underlying GPTimer driver. + * The following statements are valid: + * - After PWM_open(): The device is still allowed to enter Standby. When the + * device is active the underlying GPTimer peripheral will + * be enabled and clocked. + * - After PWM_start(): The device can only go to Idle power mode since the + * high-frequency clock is needed for PWM operation: + * - After PWM_stop(): Conditions are equal as for after PWM_open + * - After PWM_close(): The underlying GPTimer is turned off and the device + * is allowed to go to standby. + * + * # Accuracy # + * The PWM output period and duty cycle are limited by the underlying timer. + * In PWM mode the timer is effectively 24 bits which results in a minimum + * frequency of 48MHz / (2^24-1) = 2.86Hz (349.525ms) + * The driver will round off the configured duty and period to a value limited + * by the timer resolution and the application is responsible for selecting + * duty and period that works with the underlying timer if high accuracy is + * needed. + * + * The effect of this is most visible when using high output frequencies as the + * available duty cycle resolution is reduced correspondingly. For a 24MHz PWM + * only a 0%/50%/100% duty is available as the timer uses only counts 0 and 1. + * Similarly for a 12MHz period the duty cycle will be limited to a 12.5% + * resolution. + * + * @note The PWM signals are generated using the high-frequency clock as + * a source. The internal RC oscillator is the source of the high frequency + * clock, but may not be accurate enough for certain applications. If very + * high-accuracy outputs are needed, the application should request using + * the external HF crystal: + * @code + * #include + * #include + * Power_setDependency(PowerCC26XX_XOSC_HF); + * @endcode + * + * # Limitations # + * - The PWM output can currently not be synchronized with other PWM outputs + * - The PWM driver does not support updating duty and period using DMA. + * - Changes to the timer period are applied immediately, which can cause + * pulses to be too long or short unless period changes are applied close + * to a timeout. Does not apply to duty cycle, which is applied on timeout. + * # PWM usage # + * + * ## Basic PWM output ## + * The below example will output a 8MHz PWM signal with 50% duty cycle. + * @code + * PWM_Handle pwmHandle; + * PWM_Params params; + * + * PWM_Params_init(¶ms); + * params.idleLevel = PWM_IDLE_LOW; + * params.periodUnits = PWM_PERIOD_HZ; + * params.periodValue = 8e6; + * params.dutyUnits = PWM_DUTY_FRACTION; + * params.dutyValue = PWM_DUTY_FRACTION_MAX / 2; + * + * pwmHandle = PWM_open(Board_PWM0, ¶ms); + * if(pwmHandle == NULL) { + * Log_error0("Failed to open PWM"); + * Task_exit(); + * } + * PWM_start(pwmHandle); + * @endcode + * + * + ******************************************************************************* + */ +#ifndef ti_drivers_pwm__PWMTimerCC26XX_include +#define ti_drivers_pwm__PWMTimerCC26XX_include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include + + +/*! + * @name PWMTimerCC26XX specific control commands and arguments + * @{ +*/ + +/*! Timer debug stall mode (stop PWM output debugger halts CPU) + When enabled, PWM output will be HIGH when CPU is halted + */ +#define PWMTimerCC26XX_CMD_DEBUG_STALL PWM_CMD_RESERVED + 0 /*!< @hideinitializer */ +/*! + * @name Arguments for PWMTimerCC26XX_CMD_DEBUG_STALL + * @{ + */ +#define CMD_ARG_DEBUG_STALL_OFF (uint32_t)GPTimerCC26XX_DEBUG_STALL_OFF /*!< @hideinitializer */ +#define CMD_ARG_DEBUG_STALL_ON (uint32_t)GPTimerCC26XX_DEBUG_STALL_ON /*!< @hideinitializer */ +/* @} */ + +/* @} */ + +/* PWM function table pointer */ +extern const PWM_FxnTable PWMTimerCC26XX_fxnTable; + +/*! + * @brief PWMTimer26XX Hardware attributes + * + * These fields are used by the driver to set up underlying PIN and GPTimer + * driver statically. A sample structure is shown below: + * + * @code + * // PWM configuration, one per PWM output + * PWMTimerCC26XX_HwAttrs pwmtimerCC26xxHWAttrs[CC2650_PWMCOUNT] = { + * { .pwmPin = CC2650_LAUNCHXL_PWMPIN0, .gpTimerUnit = CC2650_LAUNCHXL_GPTIMER0A } , + * { .pwmPin = CC2650_LAUNCHXL_PWMPIN1, .gpTimerUnit = CC2650_LAUNCHXL_GPTIMER0B } , + * { .pwmPin = CC2650_LAUNCHXL_PWMPIN2, .gpTimerUnit = CC2650_LAUNCHXL_GPTIMER1A } , + * { .pwmPin = CC2650_LAUNCHXL_PWMPIN3, .gpTimerUnit = CC2650_LAUNCHXL_GPTIMER1B } , + * { .pwmPin = CC2650_LAUNCHXL_PWMPIN4, .gpTimerUnit = CC2650_LAUNCHXL_GPTIMER2A } , + * { .pwmPin = CC2650_LAUNCHXL_PWMPIN5, .gpTimerUnit = CC2650_LAUNCHXL_GPTIMER2B } , + * { .pwmPin = CC2650_LAUNCHXL_PWMPIN6, .gpTimerUnit = CC2650_LAUNCHXL_GPTIMER3A } , + * { .pwmPin = CC2650_LAUNCHXL_PWMPIN7, .gpTimerUnit = CC2650_LAUNCHXL_GPTIMER3B } , + * }; + * @endcode + */ +typedef struct PWMTimerCC26XX_HwAttrs +{ + PIN_Id pwmPin; /*!< PIN to output PWM signal on */ + uint8_t gpTimerUnit; /*!< GPTimer unit index (0A, 0B, 1A..) */ +} PWMTimerCC26XX_HwAttrs; + +/*! + * @brief PWMTimer26XX Object + * + * These fields are used by the driver to store and modify PWM configuration + * during run-time. + * The application must not edit any member variables of this structure. + * Appplications should also not access member variables of this structure + * as backwards compatibility is not guaranteed. + * A sample structure is shown below: + * @code + * // PWM object, one per PWM output + * PWMTimerCC26XX_Object pwmtimerCC26xxObjects[CC2650_PWMCOUNT]; + * @endcode + */ +typedef struct PWMTimerCC26XX_Object +{ + bool isOpen; /*!< open flag used to check if PWM is opened */ + bool isRunning; /*!< running flag, set if the output is active */ + PWM_Period_Units periodUnit; /*!< Current period unit */ + uint32_t periodValue; /*!< Current period value in unit */ + uint32_t periodCounts; /*!< Current period in raw timer counts */ + PWM_Duty_Units dutyUnit; /*!< Current duty cycle unit */ + uint32_t dutyValue; /*!< Current duty cycle value in unit */ + uint32_t dutyCounts; /*!< Current duty in raw timer counts */ + PWM_IdleLevel idleLevel; /*!< PWM idle level when stopped / not started */ + GPTimerCC26XX_Handle hTimer; /*!< Handle to underlying GPTimer peripheral */ +} PWMTimerCC26XX_Object; + +#ifdef __cplusplus +} +#endif +#endif /* ti_driver_pwm_PWMTimerCC26XX_include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RF.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RF.h new file mode 100644 index 0000000..52ceaba --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RF.h @@ -0,0 +1,2458 @@ +/* + * Copyright (c) 2016-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** +@file RF.h +@brief Radio Frequency (RF) Core Driver for the CC13XX and CC26XX device + family. + +To use the RF driver, ensure that the correct driver library for your device +is linked in and include this header file as follows: + +@code +#include +@endcode + +
+@anchor rf_overview +Overview +======== + +The RF driver provides access to the radio core on the CC13xx/CC26xx device +family. It offers a high-level interface for command execution and to the +radio timer (RAT). The RF driver ensures the lowest possible power consumption +by providing automatic power management that is fully transparent for the +application. + +@note This document describes the features and usage of the RF driver API. For a +detailed explanation of the RF core, please refer to the +Technical +Reference Manual or the +Proprietary +RF User Guide. + +Key features are: + +@li @ref rf_command_execution "Synchronous execution of direct and immediate radio commands" +@li @ref rf_command_execution "Synchronous and asynchronous execution of radio operation commands" +@li Various @ref rf_event_callbacks "event hooks" to interact with RF commands and the RF driver +@li Automatic @ref rf_power_management "power management" +@li @ref rf_scheduling "Preemptive scheduler for RF operations" of different RF driver instances +@li Convenient @ref rf_rat "Access to the radio timer" (RAT) +@li @ref rf_tx_power "Programming the TX power level" + +@anchor rf_setup_and_configuration +Setup and configuration +======================= + +The RF driver can be configured at 4 different places: + +1. In the build configuration by choosing either the single-client or + multi-client driver version. + +2. At compile-time by setting hardware and software interrupt priorities + in the board support file. + +3. During run-time initialization by setting #RF_Params when calling + #RF_open(). + +4. At run-time via #RF_control(). + + +Build configuration +------------------- + +The RF driver comes in two versions: single-client and multi-client. The +single-client version allows only one driver instance to access the RF core at +a time. The multi-client driver version allows concurrent access to the RF +core with different RF settings. The multi-client driver has a slightly larger +footprint and is not needed for many proprietary applications. The driver +version can be selected in the build configuration by linking either against a +RFCC26XX_singleMode or RFCC26XX_multiMode pre-built library. When using the +single-client driver, `RF_SINGLEMODE` has to be defined globally in the build +configuration. The multi-client driver is the default configuration in the +SimpleLink SDKs. + + +Board configuration +------------------- + +The RF driver handles RF core hardware interrupts and uses software interrupts +for its internal state machine. For managing the interrupt priorities, it +expects the existence of a global #RFCC26XX_HWAttrsV2 object. This is +usually defined in the board support file, for example `CC1310_LAUNCHXL.c`, +but when developing on custom boards, it might be kept anywhere in the +application. By default, the priorities are set to the lowest possible value: + +@code +const RFCC26XX_HWAttrsV2 RFCC26XX_hwAttrs = { + .hwiPriority = INT_PRI_LEVEL7, // Lowest HWI priority: INT_PRI_LEVEL7 + // Highest HWI priority: INT_PRI_LEVEL1 + + .swiPriority = 0, // Lowest SWI priority: 0 + // Highest SWI priority: Swi.numPriorities - 1 + + .xoscHfAlwaysNeeded = true // Power driver always starts XOSC-HF: true + // RF driver will request XOSC-HF if needed: false +}; +@endcode + + +Initialization +-------------- + +When initiating an RF driver instance, the function #RF_open() accepts a +pointer to a #RF_Params object which might set several driver parameters. In +addition, it expects an #RF_Mode object and a setup command which is usually +generated by SmartRF Studio: + +@code +RF_Params rfParams; +RF_Params_init(&rfParams); +rfParams.nInactivityTimeout = 2000; + +RF_Handle rfHandle = RF_open(&rfObject, &RF_prop, + (RF_RadioSetup*)&RF_cmdPropRadioDivSetup, &rfParams); +@endcode + +The function #RF_open() returns a driver handle that is used for accessing the +correct driver instance. Please note that the first RF operation command +before an RX or TX operation command must be a `CMD_FS` to set the synthesizer +frequency. The RF driver caches both, the pointer to the setup command and the +physical `CMD_FS` for automatic power management. + + +Run-time configuration +---------------------- + +While a driver instance is opened, it can be re-configured with the function +#RF_control(). Various configuration parameters @ref RF_CTRL are available. +Example: + +@code +uint32_t timeoutUs = 2000; +RF_control(rfHandle, RF_CTRL_SET_INACTIVITY_TIMEOUT, &timeoutUs); +@endcode + +
+@anchor rf_command_execution +Command execution +================= + +The RF core supports 3 different kinds of commands: + +1. Direct commands +2. Immediate commands +3. Radio operation commands + +Direct and immediate commands are dispatched via #RF_runDirectCmd() and +#RF_runImmediateCmd() respectively. These functions block until the command +has completed and return a status code of the type #RF_Stat when done. + +@code +#include + +RF_Stat status = RF_runDirectCmd(rfHandle, CMD_ABORT); +assert(status == RF_StatCmdDoneSuccess); +@endcode + +Radio operation commands are potentially long-running commands and support +different triggers as well as conditional execution. Only one command can be +executed at a time, but the RF driver provides an internal queue that stores +commands until the RF core is free. Two interfaces are provided for radio +operation commands: + +1. Asynchronous: #RF_postCmd() and #RF_pendCmd() +2. Synchronous: #RF_runCmd() + +The asynchronous function #RF_postCmd() posts a radio operation into the +driver's internal command queue and returns a command handle of the type +#RF_CmdHandle which is an index in the command queue. The command is +dispatched as soon as the RF core has completed any previous radio operation +command. + +@code +#include + +RF_Callback callback = NULL; +RF_EventMask subscribedEvents = 0; +RF_CmdHandle rxCommandHandle = RF_postCmd(rfHandle, (RF_Op*)&RF_cmdRx, + RF_PriorityNormal, callback, subscribedEvents); + +assert(rxCommandHandle != RF_ALLOC_ERROR); // The command queue is full. +@endcode + +Command execution happens in background. The calling task may proceed with +other work or execute direct and immediate commands to interact with the +posted radio operation. But beware that the posted command might not have +started, yet. By calling the function #RF_pendCmd() and subscribing events of +the type #RF_EventMask, it is possible to re-synchronize to a posted command: + +@code +// RF_EventRxEntryDone must have been subscribed in RF_postCmd(). +RF_EventMask events = RF_pendCmd(rfHandle, rxCommandHandle, + RF_EventRxEntryDone); + +// Program proceeds after RF_EventRxEntryDone or after a termination event. +@endcode + +The function #RF_runCmd() is a combination of both, #RF_postCmd() and +#RF_pendCmd() and allows synchronous execution. + +A pending or already running command might be aborted at any time by calling +the function #RF_cancelCmd() or #RF_flushCmd(). These functions take command +handles as parameters, but can also just abort anything in the RF driver's +queue: + +@code +uint8_t abortGraceful = 1; + +// Abort a single command +RF_cancelCmd(rfHandle, rxCommandHandle, abortGraceful); + +// Abort anything +RF_flushCmd(rfHandle, RF_CMDHANDLE_FLUSH_ALL, abortGraceful); +@endcode + +When aborting a command, the return value of #RF_runCmd() or #RF_pendCmd() +will contain the termination reason in form of event flags. If the command is +in the RF driver queue, but has not yet start, the #RF_EventCmdCancelled event is +raised. + +
+@anchor rf_event_callbacks +Event callbacks +=============== + +The RF core generates multiple interrupts during command execution. The RF +driver maps these interrupts 1:1 to callback events of the type #RF_EventMask. +Hence, it is unnecessary to implement own interrupt handlers. Callback events +are divided into 3 groups: + +- Command-specific events, documented for each radio operation command. An example + is the #RF_EventRxEntryDone for the `CMD_PROP_RX`. + +- Generic events, defined for all radio operations and originating on the RF core. + These are for instance #RF_EventCmdDone and #RF_EventLastCmdDone. Both events + indicate the termination of one or more RF operations. + +- Generic events, defined for all radio operations and originating in the RF driver, + for instance #RF_EventCmdCancelled. + +@sa @ref RF_Core_Events, @ref RF_Driver_Events. + +How callback events are subscribed was shown in the previous section. The +following snippet shows a typical event handler callback for a proprietary RX +operation: + +@code +void rxCallback(RF_Handle handle, RF_CmdHandle command, RF_EventMask events) +{ + if (events & RF_EventRxEntryDone) + { + Semaphore_post(rxPacketSemaphore); + } + if (events & RF_EventLastCmdDone) + { + // ... + } +} +@endcode + +In addition, the RF driver can generate error and power-up events that do not +relate directly to the execution of a radio command. Such events can be +subscribed by specifying the callback function pointers #RF_Params::pErrCb and +#RF_Params::pPowerCb. + +All callback functions run in software interrupt (SWI) context. Therefore, +only a minimum amount of code should be executed. When using absolute timed +commands with tight timing constraints, then it is recommended to set the RF +driver SWIs to a high priority. +See @ref rf_setup_and_configuration "Setup and configuration" for more details. + +
+@anchor rf_power_management +Power management +================ + +The RF core is a hardware peripheral and can be switched on and off. The RF +driver handles that automatically and provides the following power +optimization features: + +- Lazy power-up and radio setup caching +- Power-down on inactivity +- Deferred dispatching of commands with absolute timing + + +Lazy power-up and radio setup caching +------------------------------------- + +The RF core optimizes the power consumption by enabling the RF core as late as +possible. For instance does #RF_open() not power up the RF core immediately. +Instead, it waits until the first radio operation command is dispatched by +#RF_postCmd() or #RF_runCmd(). + +The function #RF_open() takes a radio setup command as parameter and expects a +`CMD_FS` command to follow. The pointer to the radio setup command and the +whole `CMD_FS` command are cached internally in the RF driver. They will be +used for every proceeding power-up procedure. Whenever the client re-runs a +setup command or a `CMD_FS` command, the driver updates its internal cache +with the new settings. + +By default, the RF driver measures the time that it needs for the power-up +procedure and uses that as an estimate for the next power cycle. On the +CC13x0/CC26x0 devices, power-up takes usually 1.6 ms. Automatic measurement +can be suppressed by specifying a custom power-up time with +#RF_Params::nPowerUpDuration. In addition, the client might set +#RF_Params::nPowerUpDurationMargin to cover any uncertainty when doing +automatic measurements. This is necessary in applications with a high hardware +interrupt load which can delay the RF driver's internal state machine +execution. + + +Power-down on inactivity +------------------------ + +Whenever a radio operation completes and there is no other radio operation in +the queue, the RF core might be powered down. There are two options in the RF +driver: + +- **Automatic power-down** by setting the parameter + #RF_Params::nInactivityTimeout. The RF core will then start a timer after + the last command in the queue has completed. The default timeout is "forever" + and this feature is disabled. + +- **Manual power-down** by calling #RF_yield(). The client should do this + whenever it knows that no further radio operation will be executed for a + couple of milliseconds. + +During the power-down procedure the RF driver stops the radio timer and saves +a synchronization timestamp for the next power-up. This keeps the radio timer +virtually in sync with the RTC even though it is not running all the time. The +synchronization is done in hardware. + + +Deferred dispatching of commands with absolute timing +----------------------------------------------------- + +When dispatching a radio operation command with an absolute start trigger that +is ahead in the future, the RF driver defers the execution and powers the RF +core down until the command is due. It does that only, when: + +1. `cmd.startTrigger.triggerType` is set to `TRIG_ABSTIME` + +2. The difference between #RF_getCurrentTime() and `cmd.startTime` + is at not more than 3/4 of a full RAT cycle. Otherwise the driver assumes + that `cmd.startTime` is in the past. + +3. There is enough time to run a full power cycle before `cmd.startTime` is + due. That includes: + + - the power-down time (fixed value, 1 ms) if the RF core is already + powered up, + + - the measured power-up duration or the value specified by + #RF_Params::nPowerUpDuration, + + - the power-up safety margin #RF_Params::nPowerUpDurationMargin + (the default is 282 microseconds). + +If one of the conditions are not fulfilled, the RF core is kept up and +running and the command is dispatched immediately. This ensures, that the +command will execute on-time and not miss the configured start trigger. + +
+@anchor rf_scheduling +Preemptive scheduling of RF commands in multi-client applications +================================================================= + +Schedule BLE and proprietary radio commands. + +@code +RF_Object rfObject_ble; +RF_Object rfObject_prop; + +RF_Handle rfHandle_ble, rfHandle_prop; +RF_Params rfParams_ble, rfParams_prop; +RF_ScheduleCmdParams schParams_ble, schParams_prop; + +RF_Mode rfMode_ble = +{ + .rfMode = RF_MODE_MULTIPLE, // rfMode for dual mode + .cpePatchFxn = &rf_patch_cpe_ble, + .mcePatchFxn = 0, + .rfePatchFxn = &rf_patch_rfe_ble, +}; + +RF_Mode rfMode_prop = +{ + .rfMode = RF_MODE_MULTIPLE, // rfMode for dual mode + .cpePatchFxn = &rf_patch_cpe_genfsk, + .mcePatchFxn = 0, + .rfePatchFxn = 0, +}; + +// Init RF and specify non-default parameters +RF_Params_init(&rfParams_ble); +rfParams_ble.nInactivityTimeout = 200; // 200us + +RF_Params_init(&rfParams_prop); +rfParams_prop.nInactivityTimeout = 200; // 200us + +// Configure RF schedule command parameters directly. +schParams_ble.priority = RF_PriorityNormal; +schParams_ble.endTime = 0; +schParams_ble.allowDelay = RF_AllowDelayAny; + +// Alternatively, use the helper function to configure the default behavior +RF_ScheduleCmdParams_init(&schParams_prop); + +// Open BLE and proprietary RF handles +rfHandle_ble = RF_open(rfObj_ble, &rfMode_ble, (RF_RadioSetup*)&RF_cmdRadioSetup, &rfParams_ble); +rfHandle_prop = RF_open(rfObj_prop, &rfMode_prop, (RF_RadioSetup*)&RF_cmdPropRadioDivSetup, &rfParams_prop); + +// Run a proprietary Fs command +RF_runCmd(rfHandle_pro, (RF_Op*)&RF_cmdFs, RF_PriorityNormal, NULL, NULL); + +// Schedule a proprietary RX command +RF_scheduleCmd(rfHandle_pro, (RF_Op*)&RF_cmdPropRx, &schParams_prop, &prop_callback, RF_EventRxOk); + +// Schedule a BLE advertiser command +RF_scheduleCmd(rfHandle_ble, (RF_Op*)&RF_cmdBleAdv, &schParams_ble, &ble_callback, + (RF_EventLastCmdDone | RF_EventRxEntryDone | RF_EventTxEntryDone)); + +@endcode + +Get dual mode schedule map including timing and priority information for access requests and commands. + +@code + +RF_ScheduleMap rfSheduleMap; +RF_InfoVal rfGetInfoVal; + +// Get schedule map +rfGetInfoVal.pScheduleMap = &rfScheduleMap; +RF_getInfo(NULL, RF_GET_SCHEDULE_MAP, &rfGetInfoVal); + +// RF_scheduleMap includes the following information: +// (RF_NUM_SCHEDULE_ACCESS_ENTRIES (default = 2)) entries of access request information +// (RF_NUM_SCHEDULE_COMMAND_ENTRIES (default = 8)) entries of radio command information +// Each entry has the type of RF_ScheduleMapElement. + +@endcode + +
+@anchor rf_rat +Accessing the Radio Timer (RAT) +============================== + +The Radio Timer on the RF core is an independent 32 bit timer running at a +tick rate of 4 ticks per microsecond. It is only physically active while the +RF core is on. But because the RF driver resynchronizes the RAT to the RTC on +every power-up, it appears to the application as the timer is always running. +The RAT accuracy depends on the system HF clock while the RF core is active +and on the LF clock while the RF core is powered down. + +The current RAT time stamp can be obtained by #RF_getCurrentTime(): + +@code +uint32_t now = RF_getCurrentTime(); +@endcode + +The RAT has 8 independent channels that can be set up in capture and compare +mode by #RF_ratCapture() and #RF_ratCompare() respectively. Three of these +channels are accessible by the RF driver. Each channel may be connected to +physical hardware signals for input and output or may trigger a callback +function. + +In order to allocate a RAT channel and trigger a callback function at a +certain time stamp, use #RF_ratCompare(): + +@code +RF_Handle rfDriver; +RF_RatConfigCompare config; +RF_RatConfigCompare_init(&config); +config.callback = &onRatTriggered; +config.channel = RF_RatChannelAny; +config.timeout = RF_getCurrentTime() + RF_convertMsToRatTicks(1701); + +RF_RatHandle ratHandle = RF_ratCompare(rfDriver, &config, nullptr); +assert(ratHandle != RF_ALLOC_ERROR); + +void onRatTriggered(RF_Handle h, RF_RatHandle rh, RF_EventMask e, uint32_t compareCaptureTime) +{ + if (e & RF_EventError) + { + // RF driver failed to trigger the callback on time. + } + printf("RAT has triggered at %u.", compareCaptureTime); + + // Trigger precisely with the same period again + config.timeout = compareCaptureTime + RF_convertMsToRatTicks(1701); + ratHandle = RF_ratCompare(rfDriver, &config, nullptr); + assert(ratHandle != RF_ALLOC_ERROR); +} +@endcode + +The RAT may be used to capture a time stamp on an edge of a physical pin. This +can be achieved with #RF_ratCapture(). + +@code +#include +// Map IO 26 to RFC_GPI0 +PINCC26XX_setMux(pinHandle, IOID_26, PINCC26XX_MUX_RFC_GPI0); + +RF_Handle rfDriver; +RF_RatConfigCapture config; +RF_RatConfigCapture_init(&config); +config.callback = &onSignalTriggered; +config.channel = RF_RatChannelAny; +config.source = RF_RatCaptureSourceRfcGpi0; +config.captureMode = RF_RatCaptureModeRising; +config.repeat = RF_RatCaptureRepeat; + +RF_RatHandle ratHandle = RF_ratCapture(rfDriver, &config, nullptr); +assert(ratHandle != RF_ALLOC_ERROR); + +void onSignalTriggered(RF_Handle h, RF_RatHandle rh, RF_EventMask e, uint32_t compareCaptureTime) +{ + if (e & RF_EventError) + { + // An internal error has occurred + } + printf("Rising edge detected on IO 26 at %u.", compareCaptureTime); +} +@endcode + +In both cases, the RAT may generate an output signal when being triggered. The +signal can be routed to a physical IO pin: + +@code +// Generate a pulse on an internal RAT output signal +RF_RatConfigOutput output; +RF_RatConfigOutput_init(&output); +output.mode = RF_RatOutputModePulse; +output.select = RF_RatOutputSelectRatGpo3; +RF_ratCompare(...); + +// Map RatGpo3 to one of four intermediate doorbell signals. +// This has to be done in the override list in order to take permanent effect. +// The override list can be found in the RF settings .c file exported from +// SmartRF Studio. +// Attention: This will change the default mapping of the PA and LNA signal as well. +#include +static uint32_t pOverrides[] = +{ + HW_REG_OVERRIDE(0x1110, RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3), + // ... +} + +// Finally, route the intermediate doorbell signal to a physical pin. +#include +PINCC26XX_setMux(pinHandle, IOID_17, PINCC26XX_MUX_RFC_GPO2); +@endcode + +
+@anchor rf_tx_power +Programming the TX power level +============================== + +The application can program a TX power level for each RF client with the function +#RF_setTxPower(). The new value takes immediate effect if the RF core is up and +running. Otherwise, it is stored in the RF driver client configuration. + +TX power may be stored in a lookup table in ascending order. This table is usually +generated and exported from SmartRF Studio together with the rest of the PHY configuration. +A typical power table my look as follows: +@code +RF_TxPowerTable_Entry txPowerTable[] = { + { .power = 11, .value = { 0x1233, RF_TxPowerTable_DefaultPA }}, + { .power = 13, .value = { 0x1234, RF_TxPowerTable_DefaultPA }}, + // ... + RF_TxPowerTable_TERMINATION_ENTRY +}; +@endcode + +@note Some devices offer a high-power PA in addition to the default PA. +A client must not mix configuration values in the same power table and must +not hop from a default PA configuration to a high-power PA configuration unless it +can guarantee that the RF setup command is re-executed in between. + +Given this power table format, the application may program a new power level in multiple +ways. It can use convenience functions to search a certain power level +in the power table or may access the table index-based: +@code +// Set a certain power level. Search a matching level. +RF_setTxPower(h, RF_TxPowerTable_findValue(txPowerTable, 17)); + +// Set a certain power level with a known level. +RF_setTxPower(h, txPowerTable[3].value); + +// Set a certain power without using a human readable level. +RF_setTxPower(h, value); + +// Set maximum power. Search the value. +RF_setTxPower(h, RF_TxPowerTable_findValue(txPowerTable, RF_TxPowerTable_MAX_DBM)); + +// Set minimum power without searching. +RF_setTxPower(h, txPowerTable[0].value); + +// Set minimum power. Search the value. +RF_setTxPower(h, RF_TxPowerTable_findValue(txPowerTable, RF_TxPowerTable_MIN_DBM)); + +// Set maximum power without searching. +int32_t lastIndex = sizeof(txPowerTable) / sizeof(RF_TxPowerTable_Entry) - 2; +RF_setTxPower(h, txPowerTable[lastIndex].value); +@endcode + +The current configured power level for a client can be retrieved by #RF_getTxPower(). +@code +// Get the current configured power level. +int8_t power = RF_TxPowerTable_findPowerLevel(txPowerTable, RF_getTxPower(h)); +@endcode + +
+@anchor rf_convenience_features +Convenience features +==================== + +The RF driver simplifies often needed tasks and provides additional functions. +For instance, it can read the RSSI while the RF core is in RX mode using the +function :tidrivers_api:`RF_getRssi`: + +@code +int8_t rssi = RF_getRssi(rfHandle); +assert (rssi != RF_GET_RSSI_ERROR_VAL); // Could not read the RSSI +@endcode + +
+ ****************************************************************************** + */ + +#ifndef ti_drivers_rf__include +#define ti_drivers_rf__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h) +#include DeviceFamily_constructPath(driverlib/rf_prop_cmd.h) +#include DeviceFamily_constructPath(driverlib/rf_ble_cmd.h) + +/** + * @name RF Core Events + * @anchor RF_Core_Events + * + * Events originating on the RF core and caused during command execution. + * They are aliases for the corresponding interrupt flags. + * RF Core Events are command-specific and are explained in the Technical Reference Manual. + * + * @sa RF_postCmd(), RF_pendCmd(), RF_runCmd() + * @{ + */ +#define RF_EventCmdDone (1 << 0) ///< A radio operation command in a chain finished. +#define RF_EventLastCmdDone (1 << 1) ///< A stand-alone radio operation command or the last radio operation command in a chain finished. +#define RF_EventFGCmdDone (1 << 2) ///< A IEEE-mode radio operation command in a chain finished. +#define RF_EventLastFGCmdDone (1 << 3) ///< A stand-alone IEEE-mode radio operation command or the last command in a chain finished. +#define RF_EventTxDone (1 << 4) ///< Packet transmitted +#define RF_EventTXAck (1 << 5) ///< ACK packet transmitted +#define RF_EventTxCtrl (1 << 6) ///< Control packet transmitted +#define RF_EventTxCtrlAck (1 << 7) ///< Acknowledgement received on a transmitted control packet +#define RF_EventTxCtrlAckAck (1 << 8) ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet +#define RF_EventTxRetrans (1 << 9) ///< Packet retransmitted +#define RF_EventTxEntryDone (1 << 10) ///< Tx queue data entry state changed to Finished +#define RF_EventTxBufferChange (1 << 11) ///< A buffer change is complete +#define RF_EventPaChanged (1 << 14) ///< The PA was reconfigured on the fly. +#define RF_EventRxOk (1 << 16) ///< Packet received with CRC OK, payload, and not to be ignored +#define RF_EventRxNOk (1 << 17) ///< Packet received with CRC error +#define RF_EventRxIgnored (1 << 18) ///< Packet received with CRC OK, but to be ignored +#define RF_EventRxEmpty (1 << 19) ///< Packet received with CRC OK, not to be ignored, no payload +#define RF_EventRxCtrl (1 << 20) ///< Control packet received with CRC OK, not to be ignored +#define RF_EventRxCtrlAck (1 << 21) ///< Control packet received with CRC OK, not to be ignored, then ACK sent +#define RF_EventRxBufFull (1 << 22) ///< Packet received that did not fit in the Rx queue +#define RF_EventRxEntryDone (1 << 23) ///< Rx queue data entry changing state to Finished +#define RF_EventDataWritten (1 << 24) ///< Data written to partial read Rx buffer +#define RF_EventNDataWritten (1 << 25) ///< Specified number of bytes written to partial read Rx buffer +#define RF_EventRxAborted (1 << 26) ///< Packet reception stopped before packet was done +#define RF_EventRxCollisionDetected (1 << 27) ///< A collision was indicated during packet reception +#define RF_EventModulesUnlocked (1 << 29) ///< As part of the boot process, the CM0 has opened access to RF core modules and memories +#define RF_EventInternalError (uint32_t)(1 << 31) ///< Internal error observed +#define RF_EventMdmSoft 0x0000002000000000 ///< Synchronization word detected (MDMSOFT interrupt flag) +/** @}*/ + +/** + * @name RF Driver Events + * @anchor RF_Driver_Events + * + * Event flags generated by the RF Driver. + * @{ + */ +#define RF_EventCmdCancelled 0x1000000000000000 ///< Command canceled before it was started. +#define RF_EventCmdAborted 0x2000000000000000 ///< Abrupt command termination caused by RF_cancelCmd() or RF_flushCmd(). +#define RF_EventCmdStopped 0x4000000000000000 ///< Graceful command termination caused by RF_cancelCmd() or RF_flushCmd(). +#define RF_EventRatCh 0x0800000000000000 ///< A user-programmable RAT channel triggered an event. +#define RF_EventPowerUp 0x0400000000000000 ///< RF power up event. \deprecated This event is deprecated. Use #RF_ClientEventPowerUpFinished instead. +#define RF_EventError 0x0200000000000000 ///< Event flag used for error callback functions to indicate an error. See RF_Params::pErrCb. +#define RF_EventCmdPreempted 0x0100000000000000 ///< Command preempted by another command with higher priority. Applies only to multi-client applications. +/** @}*/ + +/** + * @name Control codes for driver configuration + * @anchor RF_CTRL + * + * Control codes are used in RF_control(). + * + * @{ + */ + +/*! + * @brief Control code used by RF_control to set inactivity timeout + * + * Setting this control allows RF to power down the radio upon completion of a radio + * command after a specified timeout period (in us) + * With this control code @b arg is a pointer to the timeout variable and returns RF_StatSuccess. + */ +#define RF_CTRL_SET_INACTIVITY_TIMEOUT 0 +/*! + * @brief Control code used by RF_control to update setup command + * + * Setting this control notifies RF that the setup command is to be updated, so that RF will take + * proper actions when executing the next setup command. + * Note the updated setup command will take effect in the next power up cycle when RF executes the + * setup command. Prior to updating the setup command, user should make sure all pending commands + * have completed. + */ +#define RF_CTRL_UPDATE_SETUP_CMD 1 +/*! + * @brief Control code used by RF_control to set powerup duration margin + * + * Setting this control updates the powerup duration margin. Default is RF_DEFAULT_POWER_UP_MARGIN. + */ +#define RF_CTRL_SET_POWERUP_DURATION_MARGIN 2 +/*! + * @brief Control code used by RF_control to set the phy switching margin + * + * Setting this control updates the phy switching duration margin, which is used to calculate when + * run-time conflicts shall be evaluated in case of colliding radio operations issued from two + * different clients. Default is RF_DEFAULT_PHY_SWITCHING_MARGIN. + */ +#define RF_CTRL_SET_PHYSWITCHING_DURATION_MARGIN 3 +/*! + * @brief Control code used by RF_control to set max error tolerance for RAT/RTC + * + * Setting this control updates the error tol for how frequently the CMD_RAT_SYNC_STOP is sent. + * Default is RF_DEFAULT_RAT_RTC_ERR_TOL_IN_US (5 us) + * Client is recommeneded to change this setting before sending any commands. + */ +#define RF_CTRL_SET_RAT_RTC_ERR_TOL_VAL 4 +/*! + * @brief Control code used by RF_control to set power management + * + * Setting this control configures RF driver to enable or disable power management. + * By default power management is enabled. + * If disabled, once RF core wakes up, RF driver will not go to standby and will not power down RF core. + * To configure power management, use this control to pass a parameter value of 0 to disable power management, + * and pass a parameter value of 1 to re-enable power management. + * This control is valid for dual-mode code only. Setting this control when using single-mode code has no effect + * (power management always enabled). + */ +#define RF_CTRL_SET_POWER_MGMT 5 +/*! + * @brief Control code used by RF_control to set the hardware interrupt priority level of the RF driver. + * + * This control code sets the hardware interrupt priority level that is used by the RF driver. Valid + * values are INT_PRI_LEVEL1 (highest) until INT_PRI_LEVEL7 (lowest). The default interrupt priority is + * set in the board support file. The default value is -1 which means "lowest possible priority". + * + * When using the TI-RTOS kernel, INT_PRI_LEVEL0 is reserved for zero-latency interrupts and must not be used. + * + * Execute this control code only while the RF core is powered down and the RF driver command queue is empty. + * This is usually the case after calling RF_open(). Changing the interrupt priority level while the RF driver + * is active will result in RF_StatBusyError being returned. + * + * Example: + * @code + * #include DeviceFamily_constructPath(driverlib/interrupt.h) + * + * int32_t hwiPriority = INT_PRI_LEVEL5; + * RF_control(rfHandle, RF_CTRL_SET_HWI_PRIORITY, &hwiPriority); + * @endcode + */ +#define RF_CTRL_SET_HWI_PRIORITY 6 +/*! + * @brief Control code used by RF_control to set the software interrupt priority level of the RF driver. + * + * This control code sets the software interrupt priority level that is used by the RF driver. Valid + * values are integers starting at 0 (lowest) until Swi_numPriorities - 1 (highest). The default + * interrupt priority is set in the board support file. The default value is 0 which means means + * "lowest possible priority". + * + * Execute this control code only while the RF core is powered down and the RF driver command queue is empty. + * This is usually the case after calling RF_open(). Changing the interrupt priority level while the RF driver + * is active will result in RF_StatBusyError being returned. + * + * Example: + * @code + * #include + * + * // Set highest possible priority + * uint32_t swiPriority = ~0; + * RF_control(rfHandle, RF_CTRL_SET_SWI_PRIORITY, &swiPriority); + * @endcode + */ +#define RF_CTRL_SET_SWI_PRIORITY 7 +/*! + * @brief Control code used by RF_control to mask the available RAT channels manually. + * + * This control code can be used to manually disallow/allow access to certain RAT channels from the RAT APIs. + * A typical use case is when a RAT channel is programmed through chained radio operations, and hence is + * used outside the scope of the RF driver. By disallowing access to this channel one can prevent collision + * between the automatic channel allocation through #RF_ratCompare()/#RF_ratCapture() and the direct + * configuration through #RF_postCmd(). + */ +#define RF_CTRL_SET_AVAILABLE_RAT_CHANNELS_MASK 8 +/** @}*/ + +/** + * @name TX Power Table defines + * @{ + */ + +/** + * Refers to the the minimum available power in dBm when accessing a power + * table. + * + * \sa #RF_TxPowerTable_findValue() + */ +#define RF_TxPowerTable_MIN_DBM -128 + +/** + * Refers to the the maximum available power in dBm when accessing a power + * table. + * + * \sa #RF_TxPowerTable_findValue() + */ +#define RF_TxPowerTable_MAX_DBM 126 + +/** + * Refers to an invalid power level in a TX power table. + * + * \sa #RF_TxPowerTable_findPowerLevel() + */ +#define RF_TxPowerTable_INVALID_DBM 127 + +/** + * Refers to an invalid power value in a TX power table. + * + * This is the raw value part of a TX power configuration. In order to check + * whether a given power configuration is valid, do: + * + * @code + * RF_TxPowerTable_Value value = ...; + * if (value.rawValue == RF_TxPowerTable_INVALID_VALUE) { + * // error, value not valid + * } + * @endcode + * + * A TX power table is always terminated by an invalid power configuration. + * + * \sa #RF_getTxPower(), RF_TxPowerTable_findValue + */ +#define RF_TxPowerTable_INVALID_VALUE 0x3fffff + +/** + * Marks the last entry in a TX power table. + * + * In order to use #RF_TxPowerTable_findValue() and #RF_TxPowerTable_findPowerLevel(), + * every power table must be terminated by a %RF_TxPowerTable_TERMINATION_ENTRY: + * + * @code + * RF_TxPowerTable_Entry txPowerTable[] = + * { + * { 20, RF_TxPowerTable_HIGH_PA_ENTRY(1, 2, 3) }, + * // ... , + * RF_TxPowerTable_TERMINATION_ENTRY + * }; + * @endcode + */ +#define RF_TxPowerTable_TERMINATION_ENTRY \ + { .power = RF_TxPowerTable_INVALID_DBM, .value = { .rawValue = RF_TxPowerTable_INVALID_VALUE, .paType = RF_TxPowerTable_DefaultPA } } + +/** + * Creates a TX power table entry for the default PA. + * + * The values for \a bias, \a gain, \a boost and \a coefficient are usually measured by Texas Instruments + * for a specific front-end configuration. They can then be obtained from SmartRFStudio. + */ +#define RF_TxPowerTable_DEFAULT_PA_ENTRY(bias, gain, boost, coefficient) \ + { .rawValue = ((bias) << 0) | ((gain) << 6) | ((boost) << 8) | ((coefficient) << 9), .paType = RF_TxPowerTable_DefaultPA } + +/** + * Creates a TX power table entry for the High-power PA. + * + * The values for \a bias, \a ibboost, \a boost, \a coefficient and \a ldoTrim are usually measured by Texas Instruments + * for a specific front-end configuration. They can then be obtained from SmartRFStudio. + */ +#define RF_TxPowerTable_HIGH_PA_ENTRY(bias, ibboost, boost, coefficient, ldotrim) \ + { .rawValue = ((bias) << 0) | ((ibboost) << 6) | ((boost) << 8) | ((coefficient) << 9) | ((ldotrim) << 16), .paType = RF_TxPowerTable_HighPA } + + +/** @} */ + +/** + * @name Other defines + * @{ + */ +#define RF_GET_RSSI_ERROR_VAL (-128) ///< Error return value for RF_getRssi() +#define RF_CMDHANDLE_FLUSH_ALL (-1) ///< RF command handle to flush all RF commands +#define RF_ALLOC_ERROR (-2) ///< RF command or RAT channel allocation error +#define RF_SCHEDULE_CMD_ERROR (-3) ///< RF command schedule error +#define RF_ERROR_RAT_PROG (-255) ///< A rat channel could not be programmed. +#define RF_ERROR_INVALID_RFMODE (-256) ///< Invalid RF_Mode. Used in error callback. +#define RF_ERROR_CMDFS_SYNTH_PROG (-257) ///< Synthesizer error with CMD_FS. Used in error callback. If this error occurred in error callback, user needs to resend CMD_FS to recover. See the device's errata for more details. + +#define RF_NUM_SCHEDULE_ACCESS_ENTRIES 2 ///< Number of access request entries +#define RF_NUM_SCHEDULE_COMMAND_ENTRIES 8 ///< Number of scheduled command entries +#define RF_NUM_SCHEDULE_MAP_ENTRIES (RF_NUM_SCHEDULE_ACCESS_ENTRIES + RF_NUM_SCHEDULE_COMMAND_ENTRIES) ///< Number of schedule map entries. This is the sum of access request and scheduled command entries +#define RF_SCH_MAP_CURRENT_CMD_OFFSET RF_NUM_SCHEDULE_ACCESS_ENTRIES ///< Offset of the current command entry in the schedule map +#define RF_SCH_MAP_PENDING_CMD_OFFSET (RF_SCH_MAP_CURRENT_CMD_OFFSET + 2) ///< Offset of the first pending command entry in the schedule map + +#define RF_ABORT_PREEMPTION (1<<2) ///< Used with RF_cancelCmd() to provoke subscription to RadioFreeCallback +#define RF_ABORT_GRACEFULLY (1<<0) ///< Used with RF_cancelCmd() for graceful command termination + +#define RF_SCH_CMD_EXECUTION_TIME_UNKNOWN 0 ///< For unknown execution time for RF scheduler + +#define RF_RAT_ANY_CHANNEL (-1) ///< To be used within the channel configuration structure. Allocate any of the available channels. +#define RF_RAT_TICKS_PER_US 4 ///< Radio timer (RAT) ticks per microsecond. + +#define RF_LODIVIDER_MASK 0x7F ///< Mask to be used to determine the effective value of the setup command's loDivider field. + +/*! +\brief Converts a duration given in \a microseconds into radio timer (RAT) ticks. +*/ +#define RF_convertUsToRatTicks(microseconds) \ + ((microseconds) * (RF_RAT_TICKS_PER_US)) + +/*! +\brief Converts a duration given in \a milliseconds into radio timer (RAT) ticks. +*/ +#define RF_convertMsToRatTicks(milliseconds) \ + ((milliseconds) * 1000 * (RF_RAT_TICKS_PER_US)) + +/*! +\brief Converts a duration given in radio timer (RAT) \a ticks into microseconds. +*/ +#define RF_convertRatTicksToUs(ticks) \ + ((ticks) / (RF_RAT_TICKS_PER_US)) + +/*! +\brief Converts a duration given in radio timer (RAT) \a ticks into milliseconds. +*/ +#define RF_convertRatTicksToMs(ticks) \ + ((ticks) / (1000 * (RF_RAT_TICKS_PER_US))) + + +/** @}*/ + + +/** + * \brief PA configuration value for a certain power level. + * + * A %RF_TxPowerTable_Value contains the power amplifier (PA) configuration for a certain power level. + * It encodes the PA type as well as a raw configuration value for the RF core hardware. + * + * \sa #RF_getTxPower(), #RF_setTxPower(), #RF_TxPowerTable_Entry, #RF_TxPowerTable_PAType. + */ +typedef struct { + uint32_t rawValue:22; ///< Hardware configuration value. + ///< + ///< - \c [15:0] used for default PA, + ///< - \c [21:0] used for High-power PA + uint32_t __dummy:9; + uint32_t paType:1; ///< Selects the PA type to be used. + ///< + ///< - 0: #RF_TxPowerTable_DefaultPA + ///< - 1: #RF_TxPowerTable_HighPA +} RF_TxPowerTable_Value; + +/** + * \brief TX power configuration entry in a TX power table. + * + * A %RF_TxPowerTable_Entry defines an entry in a lookup table. Each entry contains a + * human-readable power level \a power as key and a hardware configuration \a value. + * + * Example of a typical power table: + * \code + * RF_TxPowerTable_Entry txPowerTable[] = { + * { .power = 20, .value = { .rawValue = 0x1234, .paType = RF_TxPowerTable_HighPA }}, + * { .power = 19, .value = { .rawValue = 0x1233, .paType = RF_TxPowerTable_HighPA }}, + * // ... + * RF_TxPowerTable_TERMINATION_ENTRY + * }; + * \endcode + * + * \sa #RF_TxPowerTable_findPowerLevel(), #RF_TxPowerTable_findPowerLevel() + */ +typedef struct +{ + int8_t power; ///< Human readable power value representing + ///< the output in dBm. + + RF_TxPowerTable_Value value; ///< PA hardware configuration for that power level. +} __attribute__((packed)) RF_TxPowerTable_Entry; + + +/** + * \brief Selects a power amplifier path in a TX power value. + * + * %RF_TxPowerTable_PAType selects one of the available power amplifiers + * on the RF core. It is usually included in a #RF_TxPowerTable_Value. + */ +typedef enum { + RF_TxPowerTable_DefaultPA = 0, ///< Default PA + RF_TxPowerTable_HighPA = 1, ///< High-power PA +} RF_TxPowerTable_PAType; + + +/** @brief Base type for all radio operation commands. + * + * All radio operation commands share a common part. + * That includes the command id, a status field, chaining properties + * and a start trigger. + * Whenever an RF operation command is used with the RF driver, it needs + * to be casted to an RF_Op. + * + * More information about RF operation commands can be found in the Proprietary RF + * User's Guide. + * + * @sa RF_runCmd(), RF_postCmd(), RF_pendCmd() + */ +typedef rfc_radioOp_t RF_Op; + + +/** @brief Specifies a RF core firmware configuration. + * + * %RF_Mode selects a mode of operation and points to firmware patches for the RF core. + * There exists one instance per radio PHY configuration, usually generated by + * SmartRF Studio. + * After assigning %RF_Mode configuration to the RF driver via RF_open(), the + * driver caches the containing information and re-uses it on every power-up. + */ +typedef struct { + uint8_t rfMode; ///< Specifies which PHY modes should be activated. Must be set to RF_MODE_MULTIPLE for dual-mode operation. + void (*cpePatchFxn)(void); ///< Pointer to CPE patch function + void (*mcePatchFxn)(void); ///< Pointer to MCE patch function + void (*rfePatchFxn)(void); ///< Pointer to RFE patch function +} RF_Mode; + +/** @brief Scheduling priority of RF operation commands. + * + * When multiple RF driver instances are used at the same time, + * commands from different clients may overlap. + * If an RF operation with a higher priority than the currently + * running operation is scheduled by RF_scheduleCmd(), then the + * running operation is interrupted. + * + * In single-client applications, %RF_PriorityNormal should be used. + */ +typedef enum { + RF_PriorityHighest = 2, ///< Highest priority. Only use this for urgent commands. + RF_PriorityHigh = 1, ///< High priority. Use this for time-critical commands in synchronous protocols. + RF_PriorityNormal = 0, ///< Default priority. Use this in single-client applications. +} RF_Priority; + +/** @brief Status codes for various RF driver functions. + * + * RF_Stat is reported as return value for RF driver functions which + * execute direct and immediate commands. + * Such commands are executed by RF_runDirectCmd() and RF_runImmediateCmd() in the + * first place, but also by some convenience functions like RF_cancelCmd(), + * RF_flushCmd(), RF_getInfo() and others. + */ +typedef enum { + RF_StatBusyError, ///< Command not executed because RF driver is busy. + RF_StatRadioInactiveError, ///< Command not executed because RF core is powered down. + RF_StatCmdDoneError, ///< Command finished with an error. + RF_StatInvalidParamsError, ///< Function was called with an invalid parameter. + RF_StatCmdEnded, ///< Cmd is found in the pool but was already ended. + RF_StatError = 0x80, ///< General error specifier. + RF_StatCmdDoneSuccess, ///< Command finished with success. + RF_StatCmdSch, ///< Command successfully scheduled for execution. + RF_StatSuccess ///< Function finished with success. +} RF_Stat; + +/** @brief Data type for events during command execution. + * + * Possible event flags are listed in @ref RF_Core_Events and @ref RF_Driver_Events. + */ +typedef uint64_t RF_EventMask; + +/** @brief A unified type for radio setup commands of different PHYs. + * + * Radio setup commands are used to initialize a PHY on the RF core. + * Various partially similar commands exist, each one represented + * by a different data type. + * RF_RadioSetup is a generic container for all types. + * A specific setup command is usually exported from SmartRF Studio + * and then passed to the RF driver in RF_open(). + */ +typedef union { + rfc_command_t commandId; ///< Generic command identifier. This is the first field + ///< in every radio operation command. + rfc_CMD_RADIO_SETUP_t common; ///< Radio setup command for BLE and IEEE modes + rfc_CMD_BLE5_RADIO_SETUP_t ble5; ///< Radio setup command for BLE5 mode + rfc_CMD_PROP_RADIO_SETUP_t prop; ///< Radio setup command for PROPRIETARY mode on 2.4 GHz + rfc_CMD_PROP_RADIO_DIV_SETUP_t prop_div; ///< Radio setup command for PROPRIETARY mode on Sub-1 Ghz + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) + rfc_CMD_RADIO_SETUP_PA_t common_pa; ///< Radio setup command for BLE and IEEE modes with High Gain PA + rfc_CMD_BLE5_RADIO_SETUP_PA_t ble5_pa; ///< Radio setup command for BLE5 mode with High Gain PA + rfc_CMD_PROP_RADIO_SETUP_PA_t prop_pa; ///< Radio setup command for PROPRIETARY mode on 2.4 GHz with High Gain PA + rfc_CMD_PROP_RADIO_DIV_SETUP_PA_t prop_div_pa; ///< Radio setup command for PROPRIETARY mode on Sub-1 Ghz with High Gain PA +#endif +} RF_RadioSetup; + +/** @brief Client-related RF driver events. + * + * Events originating in the RF driver but not directly related to a specific radio command, + * are called client events. + * Clients may subscribe to these events by specifying a callback function RF_Params::pClientEventCb. + * Events are activated by specifying a bitmask RF_Params::nClientEventMask. + * The callback is called separately for every event providing an optional argument. + * + * @code + * void onClientEvent(RF_Handle h, RF_ClientEvent event, void* arg) + * { + * switch (event) + * { + * case RF_ClientEventPowerUpFinished: + * // Set output port + * break; + * default: + * // Unsubscribed events must not be issued. + * assert(false); + * } + * } + * + * RF_Params params; + * params.pClientEventCb = &onClientEvent; + * params.nClientEventMask = RF_ClientEventPowerUpFinished; + * RF_open(...); + * @endcode + */ +typedef enum { + RF_ClientEventPowerUpFinished = (1 << 0), ///< The RF core has been powered up the radio setup has been finished. + RF_ClientEventRadioFree = (1 << 1), ///< Radio becomes free after a command has been preempted by a high-priority command of another client. + ///< This event is only triggered on a client that has been preempted. + ///< Clients may use this event to retry running their low-priority RF operation. + + RF_ClientEventSwitchClientEntered = (1 << 2) ///< Signals the client that the RF driver is about to switch over from another client. +} RF_ClientEvent; + +/** @brief Global RF driver events. + * + * The RF driver provides an interface through the global \c RFCC26XX_hwAttrs + * struct to register a global, client independent callback. This callback is + * typically used to control board related configurations such as antenna + * switches. + * + * @code + * void globalCallback(RF_Handle h, RF_GlobalEvent event, void* arg) + * { + * switch (event) + * { + * case RF_GlobalEventRadioSetup: + * { + * RF_RadioSetup* setupCommand = (RF_RadioSetup*)arg; + * // Select antenna path + * if (setupCommand->common.commandNo == CMD_PROP_RADIO_DIV_SETUP) { + * // Sub-1 GHz ... + * } else { + * // 2.4 GHz ... + * } + * } + * break; + * + * case RF_GlobalEventRadioPowerDown: + * // Disable antenna switch + * break; + * + * default: + * // Unsubscribed events must not be issued. + * assert(false); + * } + * } + * @endcode + * + * \sa #RF_GlobalCallback + */ +typedef enum { + RF_GlobalEventRadioSetup = (1 << 0), ///< The RF core is being reconfigured through a setup command. + ///< The \a arg argument is a pointer to the setup command. + ///< HWI context. + + RF_GlobalEventRadioPowerDown = (1 << 1), ///< The RF core is being powered down. + ///< The \a arg argument is empty. + ///< SWI context. +} RF_GlobalEvent; + + +/** @brief Event mask for combining #RF_ClientEvent event flags in #RF_Params::nClientEventMask. + * + */ +typedef uint32_t RF_ClientEventMask; + +/** @brief Event mask for combining #RF_GlobalEvent event flags in #RFCC26XX_HWAttrsV2::globalEventMask. + * + */ +typedef uint32_t RF_GlobalEventMask; + +/** @brief Command handle that is returned by RF_postCmd(). + * + * A command handle is an integer number greater equals zero and identifies + * a command container in the RF driver's internal command queue. A client + * can dispatch a command with RF_postCmd() and use the command handle + * later on to make the RF driver interact with the command. + * + * A negative value has either a special meaning or indicates an error. + * + * @sa RF_pendCmd(), RF_flushCmd(), RF_cancelCmd(), ::RF_ALLOC_ERROR, + * ::RF_CMDHANDLE_FLUSH_ALL + */ +typedef int16_t RF_CmdHandle; + +/** @struct RF_Object + * @brief Stores the client's internal configuration and states. + * + * Before RF_open() can be called, an instance of RF_Object must be created where + * the RF driver can store its internal configuration and states. + * This object must remain persistent throughout application run-time and must not be + * modified by the application. + * + * The size of #RF_Object can be optimized for single-mode applications by providing a + * `RF_SINGLEMODE` symbol at compilation time. The pre-built single-mode archive was generated + * with this symbol defined, hence any project using this archive must also define `RF_SINGLEMODE` + * on project level. + * + * @note Except configuration fields before call to RF_open(), modification of + * any field in %RF_Object is forbidden. + */ + + +/** @cond */ + +#if defined (RF_SINGLEMODE) + typedef struct RF_ObjectSingleMode RF_Object; +#else + typedef struct RF_ObjectMultiMode RF_Object; +#endif + +/* Definition of the RF_Object structure for single-mode applications. + * It is applicable with the single-mode RF driver through the #RF_Object common type. + */ +struct RF_ObjectSingleMode{ + /// Configuration + struct { + uint32_t nInactivityTimeout; ///< Inactivity timeout in us. + RF_Mode* pRfMode; ///< Mode of operation. + RF_RadioSetup* pRadioSetup; ///< Pointer to the setup command to be executed at power up. + uint32_t nPowerUpDuration; ///< Radio power up time to be used to calculate future wake-up events. + bool bMeasurePowerUpDuration; ///< Indicates if nPowerUpDuration holds a fix value or being measured and updated at every power up. + bool bUpdateSetup; ///< Indicates if an analog configuration update should be performed at the next setup command execution. + uint16_t nPowerUpDurationMargin; ///< Power up duration margin in us. + void* pPowerCb; ///< \deprecated Power up callback, will go away in future versions, see clientConfig::pClienteventCb instead. + void* pErrCb; ///< Error callback. + } clientConfig; + /// State & variables + struct { + struct { + rfc_CMD_FS_t cmdFs; ///< FS command to be executed when the radio is powered up. + } mode_state; ///< (Mode-specific) state structure + SemaphoreP_Struct semSync; ///< Semaphore used by RF_runCmd(), RF_pendCmd() and power down sequence. + RF_EventMask volatile eventSync; ///< Event mask/value used by RF_runCmd() and RF_pendCmd(). + void* pCbSync; ///< Internal storage of user callbacks when RF_runCmd() is used. + RF_EventMask unpendCause; ///< Internal storage of the return value of RF_pendCmd(). + bool bYielded; ///< Flag indicates that the radio can be powered down at the earliest convenience. + } state; +}; + +/** Definition of the RF_Object structure for multi mode applications. + * It is applicable with the multi mode RF driver through the #RF_Object common type. + */ +struct RF_ObjectMultiMode{ + /// Configuration + struct { + uint32_t nInactivityTimeout; ///< Inactivity timeout in us. + RF_Mode* pRfMode; ///< Mode of operation. + RF_RadioSetup* pRadioSetup; ///< Pointer to the setup command to be executed at power up. + uint32_t nPhySwitchingDuration; ///< Radio reconfiguration time to this client's phy and protocol. + uint32_t nPowerUpDuration; ///< Radio power up time to be used to calculate future wake-up events. + bool bMeasurePowerUpDuration; ///< Indicates if nPowerUpDuration holds a fix value or being measured and updated at every power up. + bool bUpdateSetup; ///< Indicates if an analog configuration update should be performed at the next setup command execution. + uint16_t nPowerUpDurationMargin; ///< Power up duration margin in us. + void* pPowerCb; ///< \deprecated Power up callback, will go away in future versions, see clientConfig::pClienteventCb instead + void* pErrCb; ///< Error callback. + void* pClientEventCb; ///< Client event callback. + RF_ClientEventMask nClientEventMask; ///< Client event mask to activate client event callback. + uint16_t nPhySwitchingDurationMargin; ///< Phy switching duration margin in us. It is used to calculate when run-time conflicts shall be resolved. + } clientConfig; + /// State & variables + struct { + struct { + rfc_CMD_FS_t cmdFs; ///< FS command to be executed when the radio is powered up. + } mode_state; ///< (Mode-specific) state structure + SemaphoreP_Struct semSync; ///< Semaphore used by RF_runCmd(), RF_pendCmd() and power down sequence. + RF_EventMask volatile eventSync; ///< Event mask/value used by RF_runCmd() and RF_pendCmd(). + void* pCbSync; ///< Internal storage of user callbacks when RF_runCmd() is used. + RF_EventMask unpendCause; ///< Internal storage of the return value of RF_pendCmd(). + ClockP_Struct clkReqAccess; ///< Clock used for request access timeout. + bool bYielded; ///< Flag indicates that the radio can be powered down at the earliest convenience. + } state; +}; + +/** @endcond */ + +/** @brief A handle that is returned by to RF_open(). + * + * %RF_Handle is used for further RF client interaction with the RF driver. + * An invalid handle has the value NULL. + */ +typedef RF_Object* RF_Handle; + + +/** @brief RAT handle that is returned by RF_ratCompare() or RF_ratCapture(). + * + * An %RF_RatHandle is an integer number with value greater than or equal to zero and identifies + * a Radio Timer Channel in the RF driver's internal RAT module. A client can interact with the + * RAT module through the RF_ratCompare(), RF_ratCapture() or RF_ratDisableChannel() APIs. + * + * A negative value indicates an error. A typical example when RF_ratCompare() returns with RF_ALLOC_ERROR. + */ +typedef int8_t RF_RatHandle; + +/** @brief Selects the entry of interest in RF_getInfo(). + * + */ +typedef enum { + RF_GET_CURR_CMD, ///< Retrieve a command handle of the current command. + RF_GET_AVAIL_RAT_CH, ///< Create a bitmask showing available RAT channels. + RF_GET_RADIO_STATE, ///< Show the current RF core power state. 0: Radio OFF, 1: Radio ON. + RF_GET_SCHEDULE_MAP, ///< Provide a timetable of all scheduled commands. + RF_GET_CLIENT_LIST, ///< Provide the client list. + RF_GET_CLIENT_SWITCHING_TIME, ///< Provide the client to client switching times +} RF_InfoType; + +/** @brief Stores output parameters for RF_getInfo(). + * + * This union structure holds one out of multiple data types. + * The contained value is selected by #RF_InfoType. + */ +typedef union { + RF_CmdHandle ch; ///< Command handle (#RF_GET_CURR_CMD). + uint16_t availRatCh; ///< Available RAT channels (RF_GET_AVAIL_RAT_CH). + bool bRadioState; ///< Current RF core power state (#RF_GET_RADIO_STATE). + RF_Handle pClientList[2]; ///< Client pointer list, [0]: client 1, [1]: client 2. + uint32_t phySwitchingTimeInUs[2]; ///< Phy switching time 0: client 1 -> 2, 1 : client 2 -> 1. + void *pScheduleMap; ///< Pointer to scheduling map (#RF_GET_SCHEDULE_MAP). +} RF_InfoVal; + +/** @brief RF schedule map entry structure. + * + */ +typedef struct { + RF_CmdHandle ch; ///< Command handle + RF_Handle pClient; ///< Pointer to client object + uint32_t startTime; ///< Start time (in RAT tick) of the command or access request + uint32_t endTime; ///< End time (in RAT tick) of the command or access request + RF_Priority priority; ///< Priority of the command or access request +} RF_ScheduleMapElement; + +/** @brief RF schedule map structure. + * + */ +typedef struct { + RF_ScheduleMapElement accessMap[RF_NUM_SCHEDULE_ACCESS_ENTRIES]; ///< Access request schedule map + RF_ScheduleMapElement commandMap[RF_NUM_SCHEDULE_COMMAND_ENTRIES]; ///< Command schedule map +} RF_ScheduleMap; + +/** @brief Handles events related to RF command execution. + * + * RF command callbacks notify the application of any events happening during RF command execution. + * Events may either refer to RF core interrupts (@ref RF_Core_Events) or may be generated by the RF driver + * (@ref RF_Driver_Events). + * + * RF command callbacks are set up as parameter to RF_postCmd() or RF_runCmd() and provide: + * + * - the relevant driver client handle \a h which was returned by RF_open(), + * - the relevant radio operation command handle \a ch, + * - an event mask \a e containing the occurred events. + * + * RF command callbacks are executed in Software Interrupt (SWI) context and must not perform any + * blocking operation. + * The priority is configurable via #RFCC26XX_HWAttrsV2 in the board file or #RF_CTRL_SET_SWI_PRIORITY in RF_control(). + * + * The %RF_Callback function type is also used for signaling power events and + * errors. + * These are set in #RF_Params::pPowerCb and #RF_Params::pErrCb respectively. + * In case of a power event, \a ch can be ignored and \a e has #RF_EventPowerUp set. + * In case of an error callback, \a ch contains an error code instead of a command handle and + * \a e has the #RF_EventError flag set. + * + * @note Error and power callbacks will be replaced by #RF_ClientCallback in future releases. + */ +typedef void (*RF_Callback)(RF_Handle h, RF_CmdHandle ch, RF_EventMask e); + +/** @brief Handles events related to the Radio Timer (RAT). + * + * The RF driver provides an interface to the Radio Timer through RF_ratCompare(), RF_ratCapture() and + * RF_ratDisableChannel() APIs. Each API call receives an optional input argument of the type + * RF_RatCallback. When a timer event occurs (compare, capture or error events), the registered + * callback is invoked. + * + * The RF_RatCallback provides the following argument: + * - the relevant driver client handle \a h which was returned by RF_open(), + * - the relevant rat timer handle \a rh which the event is caused by, + * - an event mask \a e containing the occurred event (RF_EventRatCh or RF_EventError) + * - the captured value or the compare time \a compareCaptureTime read from the Radio Timer channel. + */ +typedef void (*RF_RatCallback)(RF_Handle h, RF_RatHandle rh, RF_EventMask e, uint32_t compareCaptureTime); + +/** + * @brief Handles events related to a driver instance. + * + * The RF driver produces additional events that are not directly related to the execution of a certain command, but + * happen during general RF driver operations. + * This includes power-up events, client switching events and others. + * + * A client callback provides the following arguments: + * - the relevant driver client handle \a h which was returned by RF_open(), + * - an event identifier \a event, + * - an optional argument \a arg depending on the event. + * + * RF client callbacks are executed in Software Interrupt (SWI) context and must not perform any blocking operation. + * The priority is configurable via #RFCC26XX_HWAttrsV2 in the board file or #RF_CTRL_SET_SWI_PRIORITY in RF_control(). + */ +typedef void (*RF_ClientCallback)(RF_Handle h, RF_ClientEvent event, void* arg); + +/** + * @brief Handles global events as part of PHY configuration. + * + * The RF driver serves additional global, client independent events by invoking the #RF_GlobalCallback function + * registered through #RFCC26XX_HWAttrsV2::globalCallback in the board file. The function can subscribe to + * particular events through the #RFCC26XX_HWAttrsV2::globalEventMask, and receives the following arguments: + * - the relevant driver client handle \a h which was returned by RF_open(), + * - an event identifier \a event, + * - an optional argument \a arg depending on the event. + * + * If multiple events happen at the same time, the callback is always invoked separately for each event. + * Depending on the event, the callback might be invoked in SWI or HWI context. + */ +typedef void (*RF_GlobalCallback)(RF_Handle h, RF_GlobalEvent event, void* arg); + +/** @brief RF driver configuration parameters. + * + * %RF_Params is used for initial RF driver configuration. + * It is initialized by RF_Params_init() and used by RF_open(). + * Each client has its own set of parameters. + * They are reconfigured on a client switch. + * Some of the parameters can be changed during run-time using RF_control(). + */ +typedef struct { + uint32_t nInactivityTimeout; ///< Inactivity timeout in microseconds. + ///< The default value is 0xFFFFFFFF (infinite). + + uint32_t nPowerUpDuration; ///< A custom power-up duration in microseconds. + ///< If 0, the RF driver will start with a conservative value and measure the actual time during the first power-up. + ///< The default value is 0. + + RF_Callback pPowerCb; ///< \deprecated Power up callback, will be removed future versions, see RF_Params::pClienteventCb instead. + ///< The default value is NULL. + + RF_Callback pErrCb; ///< \deprecated Callback function for driver error events. + + uint16_t nPowerUpDurationMargin; ///< An additional safety margin to be added to #RF_Params::nPowerUpDuration. + ///< This is necessary because of other hardware and software interrupts + ///< preempting the RF driver interrupt handlers and state machine. + ///< The default value is platform-dependent. + + uint16_t nPhySwitchingDurationMargin; ///< An additional safety margin to be used to calculate when conflicts shall be evaluated run-time. + + RF_ClientCallback pClientEventCb; ///< Callback function for client-related events. + ///< The default value is NULL. + + RF_ClientEventMask nClientEventMask; ///< Event mask used to subscribe certain client events. + ///< The purpose is to keep the number of callback executions small. +} RF_Params; + +/* RF command. */ +typedef struct RF_Cmd_s RF_Cmd; + +/* RF command . */ +struct RF_Cmd_s { + List_Elem _elem; /* Pointer to next and previous elements. */ + RF_Callback volatile pCb; /* Pointer to callback function */ + RF_Op* pOp; /* Pointer to (chain of) RF operations(s) */ + RF_Object* pClient; /* Pointer to client */ + RF_EventMask bmEvent; /* Enable mask for interrupts from the command */ + RF_EventMask pastifg; /* Accumulated value of events happened within a command chain */ + RF_EventMask rfifg; /* Return value for callback 0:31 - RF_CPE0_INT, 32:63 - RF_HW_INT */ + uint32_t startTime; /* Command start time (in RAT ticks) */ + uint32_t endTime; /* Command end time (in RAT ticks) */ + uint32_t allowDelay; /* Delay allowed if the start time cannot be met. */ + RF_CmdHandle ch; /* Command handle */ + RF_Priority ePri; /* Priority of RF command */ + uint8_t volatile flags; /* [0: Aborted, 1: Stopped, 2: canceled] */ +}; + +/** @brief RF Hardware attributes. + * + * This data structure contains platform-specific driver configuration. + * It is usually defined globally in a board support file. + */ +typedef struct { + uint8_t hwiPriority; ///< Priority for HWIs belong to the RF driver. + uint8_t swiPriority; ///< Priority for SWIs belong to the RF driver. + bool xoscHfAlwaysNeeded; ///< Indicate that the XOSC HF should be turned on by the power driver + RF_GlobalCallback globalCallback; ///< Pointer to a callback function serving client independent events listed in #RF_GlobalEvent. + RF_GlobalEventMask globalEventMask; ///< Event mask which the globalCallback is invoked upon. +} RFCC26XX_HWAttrsV2; + +/** @brief Controls the behavior of the state machine of the RF driver when a conflict is identified + * run-time between the commands waiting on the pend queue and the commands being actively executed + * by the radio. + */ +typedef enum +{ + RF_ConflictNone = 0, + RF_ConflictReject = 1, + RF_ConflictAbort = 2, +} RF_Conflict; + +/** @brief Describes the location within the pend queue where the new command was inserted by the scheduler. + */ +typedef enum +{ + RF_ScheduleStatusError = -3, + RF_ScheduleStatusNone = 0, + RF_ScheduleStatusTop = 1, + RF_ScheduleStatusMiddle = 2, + RF_ScheduleStatusTail = 4, + RF_ScheduleStatusPreempt = 8 +} RF_ScheduleStatus; + +/** + * @brief Handles the queue sorting algorithm when a new command is submitted to the driver from any of + * the active clients. + * + * The function is invoked within the RF_scheduleCmd API. + * + * The default algorithm is subscribed through the #RFCC26XX_SchedulerPolicy::submitHook and implemented + * in the RF driver. The arguments are: + * - \a pCmdNew points to the command to be submitted. + * - \a pCmdBg is the running background command. + * - \a pCmdFg is the running foreground command. + * - \a pPendQueue points to the head structure of pend queue. + * - \a pDoneQueue points to the head structure of done queue. + * + * In case the radio APIs do not distinguish between background and foreground contexts, the active operation + * will be returned within the pCmdBg pointer. If there are no commands being executed, both the + * pCmdBg and pCmdFg pointers are returned as NULL. + */ +typedef RF_ScheduleStatus (*RF_SubmitHook)(RF_Cmd* pCmdNew, RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue); + +/** + * @brief Defines the conflict resolution in runtime. + * + * The function is invoked if a conflict is identified before the start-time of the next radio command in + * the pending queue. The return value of type #RF_Conflict determines the policy to be followed by the RF driver. + * + * The arguments are: + * - \a pCmdBg is the running background command. + * - \a pCmdFg is the running foreground command. + * - \a pPendQueue points to the head structure of pend queue. + * - \a pDoneQueue points to the head structure of done queue. + */ +typedef RF_Conflict (*RF_ConflictHook)(RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue); + +/** @brief RF scheduler policy. + * + * This data structure contains function hooks which implements the scheduling + * algorithm used to inter-align one or more independent protocol stacks. + */ +typedef struct { + RF_SubmitHook submitHook; ///< Function hook implements the scheduling policy to be executed at the time of RF_scheduleCmd API call. + RF_ConflictHook conflictHook; ///< Function hook implements the runtime conflict resolution, if any identified at the start time of next command. +} RFCC26XX_SchedulerPolicy; + +/** @brief Controls the behavior of the RF_scheduleCmd() API. + * + */ +typedef enum { + RF_AllowDelayNone = 0, + RF_AllowDelayAny = UINT32_MAX +} RF_AllowDelay; + +/* @brief RF schedule command parameter struct + * + * RF schedule command parameters are used with the RF_scheduleCmd() call. + */ +typedef struct { + uint32_t endTime; ///< End time in RAT Ticks for the radio command + RF_Priority priority; ///< Intra client priority + uint32_t allowDelay; ///< Control word to define the policy of the scheduler if the timing of a command cannot be met. + ///< Only applicable on CC13x2 and CC26x2 devices. + ///< RF_AllowDelayNone: Reject the command. + ///< RF_AllowDelayAny: Append the command to the end of the queue. +} RF_ScheduleCmdParams; + +/** @brief RF request access parameter struct + * + * RF request access command parameters are used with the RF_requestAccess() call. + */ +typedef struct { + uint32_t duration; ///< Radio access duration in RAT Ticks requested by the client + uint32_t startTime; ///< Start time window in RAT Time for radio access + RF_Priority priority; ///< Access priority +} RF_AccessParams; + +/** @brief Select the preferred RAT channel through the configuration of #RF_ratCompare() or #RF_ratCapture(). + * + * If RF_RatChannelAny is provided within the channel configuration (default), the API will + * allocate the first available channel. Otherwise, it tries to allocate the requested channel, + * and if it is not available, returns with #RF_ALLOC_ERROR. + */ +typedef enum { + RF_RatChannelAny = -1, ///< Chose the first available channel. + RF_RatChannel0 = 0, ///< Use RAT user channel 0. + RF_RatChannel1 = 1, ///< Use RAT user channel 1. + RF_RatChannel2 = 2, ///< Use RAT user channel 2. +} RF_RatSelectChannel; + +/** @brief Selects the source signal for #RF_ratCapture(). + * + * The source of a capture event can be selected through the source field of the + * #RF_RatConfigCapture configuration structure. + */ +typedef enum { + RF_RatCaptureSourceRtcUpdate = 20, ///< Selects the RTC update signal source. + RF_RatCaptureSourceEventGeneric = 21, ///< Selects the Generic event of Event Fabric as source. + RF_RatCaptureSourceRfcGpi0 = 22, ///< Selects the RFC_GPI[0] as source. This can be used i.e. + ///< to capture events on a GPIO. This requires that the GPIO + ///< is connected to RFC_GPO[0] from the GPIO driver. + RF_RatCaptureSourceRfcGpi1 = 23 ///< Selects the RFC_GPO[1] as source. This can be used i.e. + ///< to capture events on a GPIO. This requires that the GPIO + ///< is connected to RFC_GPO[1] from the GPIO driver. +} RF_RatCaptureSource; + +/** @brief Selects the mode of #RF_ratCapture(). + * + * The trigger mode of a capture event can be selected through the mode field of + * #RF_RatConfigCapture configuration structure. + */ +typedef enum { + RF_RatCaptureModeRising = 0, ///< Rising edge of the selected source will trigger a capture event. + RF_RatCaptureModeFalling = 1, ///< Falling edge of the selected source will trigger a capture event. + RF_RatCaptureModeBoth = 2 ///< Both rising and falling edges of the selected source will generate + ///< capture events. +} RF_RatCaptureMode; + +/** @brief Selects the repetition of #RF_ratCapture(). + * + * The configuration of a capture channel also defines whether the channel should be + * freed or automatically rearmed after a capture event occurred. In the latter case, the + * user needs to free the channel manually through the #RF_ratDisableChannel() API. + */ +typedef enum { + RF_RatCaptureSingle = 0, ///< Free the channel after the first capture event. + RF_RatCaptureRepeat = 1 ///< Rearm the channel after each capture events. +} RF_RatCaptureRepetition; + +/** @brief Selects the mode of the RAT_GPO[x] for #RF_ratCompare() or #RF_ratCapture(). + * + * In case of compare mode, the channel can generate an output signal of the selected + * mode on the configured RAT_GPO[x] interface, and can be interconnected with + * other subsystems through the RFC_GPO[x] or Event Fabric. An example use case is + * to generate a pulse on a GPIO. + * + * In case of capture mode, the channel can also generate an output signal of the + * selected mode on the configured RAT_GPO[x] interface. Note that the configuration + * of this output event is independent of the source signal of the capture event. + * An example use case is to generate a pulse on a GPIO on each raising edge of another + * GPIO source. + * + */ +typedef enum { + RF_RatOutputModePulse = 0, ///< Generates a one-clock period width pulse. + RF_RatOutputModeSet = 1, ///< Sets the output high on a RAT event. + RF_RatOutputModeClear = 2, ///< Sets the output low on a RAT event. + RF_RatOutputModeToggle = 3, ///< Inverts the polarity of the output. + RF_RatOutputModeAlwaysZero = 4, ///< Sets the output low independently of any RAT events. + RF_RatOutputModeAlwaysOne = 5, ///< Sets the output high independently of any RAT events. +} RF_RatOutputMode; + +/** @brief Selects GPO to be used with #RF_ratCompare() or #RF_ratCapture(). + * + * RAT_GPO[0] - Reserved by the RF core. User shall not modify the configuration, + * but can observe the signal through any of RFC_GPO[0:3]. + * RAT_GPO[1] - Reserved by the RF core only if sync word detection is enabled. + * Otherwise can be used through RFC_GPO[0:3]. + * RAT_GPO[2:3] - Available and can be used through any of the RFC_GPO[0:3]. + * RAT_GPO[4:7] - Available and can be used through the Event fabric. + */ +typedef enum { + RF_RatOutputSelectRatGpo1 = 1, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[1] + RF_RatOutputSelectRatGpo2 = 2, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[2] + RF_RatOutputSelectRatGpo3 = 3, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[3] + RF_RatOutputSelectRatGpo4 = 4, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[4] + RF_RatOutputSelectRatGpo5 = 5, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[5] + RF_RatOutputSelectRatGpo6 = 6, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[6] + RF_RatOutputSelectRatGpo7 = 7, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[7] +} RF_RatOutputSelect; + +/** @brief RF_ratCapture parameter structure. + * + * %RF_RatCapture parameters are used with the #RF_ratCapture() call. + */ +typedef struct { + RF_RatCallback callback; ///< Callback function to be invoked upon a capture event (optional). + RF_RatHandle channel; ///< RF_RatHandle identifies the channel to be allocated. + RF_RatCaptureSource source; ///< Configuration of the event source to cause a capture event. + RF_RatCaptureMode captureMode; ///< Configuration of the mode of event to cause a capture event. + RF_RatCaptureRepetition repeat; ///< Configuration of the channel to be used in single or repeated mode. +} RF_RatConfigCapture; + +/** @brief RF_ratCompare parameter structure. + * + * %RF_RatCompare parameters are used with the #RF_ratCompare() call. + */ +typedef struct { + RF_RatCallback callback; ///< Callback function to be invoked upon a capture event (optional). + RF_RatHandle channel; ///< RF_RatHandle identifies the channel to be allocated. + uint32_t timeout; ///< Timeout value in RAT ticks to be programmed in the timer as the + ///< trigger of compare event. +} RF_RatConfigCompare; + +/** @brief RAT related IO parameter structure. + * + * These parameters are used with the #RF_ratCompare() or #RF_ratCapture() calls. + */ +typedef struct { + RF_RatOutputMode mode; ///< The mode the GPO should operate in. + RF_RatOutputSelect select; ///< The signal which shall be connected to the GPO. +} RF_RatConfigOutput; + +/** @brief Creates a a new client instance of the RF driver. + * + * This function initializes an RF driver client instance using \a pObj as storage. + * It does not power up the RF core. + * Once the client starts the first RF operation command later in the application, + * the RF core is powered up and set into a PHY mode specified by \a pRfMode. + * The chosen PHY is then configured by a radio setup command \a pRadioSetup. + * Whenever the RF core is powered up, the RF driver re-executes the radio setup command \a pRadioSetup. + * Additional driver behavior may be set by an optional \a params. + * + * @code + * // Define parameters + * RF_Params rfParams; + * rfParams.nInactivityTimeout = 4; + * RF_Params_init(&rfParams); + * rfParams.nInactivityTimeout = 1701; // microseconds + * + * RF_Handle rfHandle = RF_open(&rfObject, &RF_prop, (RF_RadioSetup*)&RF_cmdPropRadioDivSetup, &rfParams); + * @endcode + * + * @note Calling context : Task + * + * @param pObj Pointer to a #RF_Object that will hold the state for this + * RF client. The object must be in persistent and writable + * memory. + * @param pRfMode Pointer to a #RF_Mode struct holding PHY information + * @param pRadioSetup Pointer to the radio setup command used for this client. + * This is re-executed by the RF Driver on each power-up. + * @param params Pointer to an RF_Params object with the desired driver configuration. + * A NULL pointer results in the default configuration being loaded. + * @return A handle for further RF driver calls on success. Otherwise NULL. + */ +extern RF_Handle RF_open(RF_Object *pObj, RF_Mode *pRfMode, RF_RadioSetup *pRadioSetup, RF_Params *params); + +/** + * @brief Close client connection to RF driver + * + * Allows a RF client (high-level driver or application) to close its connection + * to the RF driver. + * + * @note Calling context : Task + * + * @param h Handle previously returned by RF_open() + */ +extern void RF_close(RF_Handle h); + +/** + * @brief Return current radio timer value + * + * If the radio is powered returns the current radio timer value, if not returns + * a conservative estimate of the current radio timer value + * + * @note Calling context : Task/SWI/HWI + * + * @return Current radio timer value + */ +extern uint32_t RF_getCurrentTime(void); + +/** + * @brief Appends RF operation commands to the driver's command queue and returns a + * command handle. + * + * The RF operation \a pOp may either represent a single operation or may be the first + * operation in a chain. + * If the command queue is empty, the \a pCmd is dispatched immediately. If there are + * other operations pending, then \a pCmd is processed after all other commands have been + * finished. + * The RF operation command must be compatible to the RF_Mode selected by RF_open(), e.g. + * proprietary commands can only be used when the RF core is configured for proprietary mode. + * + * The returned command handle is an identifier that can be used to control command execution + * later on, for instance with RF_pendCmd() or RF_cancelCmd(). + * It is a 16 Bit signed integer value, incremented on every new command. + * If the RF driver runs out of command containers, RF_ALLOC_ERROR is returned. + * + * The priority \a ePri is only relevant in multi-client applications where commands of distinct + * clients may interrupt each other. + * Only commands started by RF_scheduleCmd() can preempt + * running commands. #RF_postCmd() or RF_runCmd() do never interrupt a running command. + * In single-client applications, \a ePri is ignored and should be set to ::RF_PriorityNormal. + * + * A callback function \a pCb might be specified to get notified about events during command + * execution. Events are subscribed by the bit mask \a bmEvent. + * Valid event flags are specified in @ref RF_Core_Events and @ref RF_Driver_Events. + * If no callback is set, RF_pendCmd() can be used to synchronize the current task to command + * execution. For this it is necessary to subscribe all relevant events. + * The termination events ::RF_EventLastCmdDone, ::RF_EventCmdCancelled, ::RF_EventCmdAborted and + * ::RF_EventCmdStopped are always implicitly subscribed. + * + * The following limitations apply to the execution of command chains: + * + * - If TRIG_ABSTIME is used as a start trigger for the first command, TRIG_REL_FIRST_START + * can not be used for any other command. This is because the RF driver may insert a + * frequency-select command (CMD_FS) at the front of the chain when it performs an + * automatic power-up. + * - Having more than one CMD_FS in a chain may lead to unexpected behavior. + * If a chain contains a CMD_FS and the command can be reached by iterating over the pNextOp + * field, then RF driver will always update the cached CMD_FS with the new settings. On the + * next automatic power-up, the RF driver will use the updated frequency. + * + * @note Calling context : Task/SWI + * + * @sa RF_pendCmd(), RF_runCmd(), RF_scheduleCmd(), RF_RF_cancelCmd(), RF_flushCmd(), RF_getCmdOp() + * + * @param h Driver handle previously returned by RF_open() + * @param pOp Pointer to the RF operation command. + * @param ePri Priority of this RF command (used for arbitration in multi-client systems) + * @param pCb Callback function called during command execution and upon completion. + * If RF_postCmd() fails, no callback is made. + * @param bmEvent Bitmask of events that will trigger the callback or that can be pended on. + * @return A handle to the RF command. Return value of RF_ALLOC_ERROR indicates error. + */ +extern RF_CmdHandle RF_postCmd(RF_Handle h, RF_Op *pOp, RF_Priority ePri, RF_Callback pCb, RF_EventMask bmEvent); + +/** + * @brief Sorts and adds commands to the RF driver internal command queue. + * + * @param pCmdNew Pointer to the command to be submitted. + * @param pCmdBg Running background command. + * @param pCmdFg Running foreground command. + * @param pPendQueue Pointer to the head structure of pend queue. + * @param pDoneQueue Pointer to the head structure of done queue.. + * @return RF_defaultSubmitPolicy identifies the success or failure of queuing. + */ +extern RF_ScheduleStatus RF_defaultSubmitPolicy(RF_Cmd* pCmdNew, RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue); + +/** + * @brief Makes a final decision when a conflict in run-time is identified. + * + * @param pCmdBg Running background command. + * @param pCmdFg Running foreground command. + * @param pPendQueue Pointer to the head structure of pend queue. + * @param pDoneQueue Pointer to the head structure of done queue.. + * @return RF_defaultSubmitPolicy identifies the success or failure of queuing. + */ +extern RF_Conflict RF_defaultConflictPolicy(RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue); + + +/** + * @brief Initialize the configuration structure to default values to be used with the RF_scheduleCmd() API. + * + * @note Calling context : Task/SWI/HWI + * + * @param pSchParams Pointer to the configuration structure. + * @return none + */ +extern void RF_ScheduleCmdParams_init(RF_ScheduleCmdParams *pSchParams); + +/** + * @brief Schedule an RF operation (chain) to the command queue. + * + * Schedule an #RF_Op to the RF command queue of the client with handle h.
+ * The command can be the first in a chain of RF operations or a standalone RF operation. + * If a chain of operations are posted they are treated atomically, i.e. either all + * or none of the chained operations are run.
+ * All operations must be posted in strictly increasing chronological order. Function returns + * immediately.
+ * + * Limitations apply to the operations posted: + * - The operation must be in the set supported in the chosen radio mode when + * RF_open() was called + * - Only a subset of radio operations are supported + * - Only some of the trigger modes are supported with potential power saving (TRIG_NOW, TRIG_ABSTIME) + * + * @note Calling context : Task/SWI + * + * @param h Handle previously returned by RF_open() + * @param pOp Pointer to the #RF_Op. Must normally be in persistent and writable memory + * @param pSchParams Pointer to the schedule command parameter structure + * @param pCb Callback function called upon command completion (and some other events). + * If RF_scheduleCmd() fails no callback is made + * @param bmEvent Bitmask of events that will trigger the callback. + * @return A handle to the RF command. Return value of RF_ALLOC_ERROR indicates error. + */ +extern RF_CmdHandle RF_scheduleCmd(RF_Handle h, RF_Op *pOp, RF_ScheduleCmdParams *pSchParams, RF_Callback pCb, RF_EventMask bmEvent); + +/** + * @brief Synchronizes the calling task to an RF operation command \a ch and + * returns accumulated event flags. + * + * After having dispatched an RF operation represented by \a ch with RF_postCmd(), the + * command is running in parallel on the RF core. Thus, it might be desirable to synchronize + * the calling task to the execution of the command. + * With #RF_pendCmd(), the application can block until one of the events specified in + * \a bmEvent occurs or until the command finishes. + * The function consumes and returns all accumulated event flags that occurred during + * execution if they have been previously subscribed by RF_postCmd(). + * Possible events are specified in @ref RF_Core_Events and @ref RF_Driver_Events. + * The termination events ::RF_EventLastCmdDone, ::RF_EventCmdCancelled, + * ::RF_EventCmdAborted and ::RF_EventCmdStopped are always implicitly subscribed and + * can not be masked. + * + * #RF_pendCmd() may be called multiple times for the same command. + * + * If #RF_pendCmd() is called for a command handle representing a finished command, + * then only the ::RF_EventLastCmdDone flag is returned, regardless of how the command + * finished. + * + * If the command has also a callback set, the callback is executed before #RF_pendCmd() + * returns. + * + * Example: + * @code + * // Dispatch a command to the RF driver's command queue + * RF_CmdHandle ch = RF_postCmd(driver, (RF_Op*)&CMD_PROP_RX, RF_PriorityNormal, NULL, RF_EventRxEntryDone); + * assert(ch != RF_ALLOC_ERROR); + * + * bool finished = false; + * while (finished == false) + * { + * // Synchronize to events during command execution. + * uint32_t events = RF_pendCmd(driver, ch, RF_EventRxEntryDone); + * // Check events that happen during execution + * if (events & RF_EventRxEntryDone) + * { + * // Process packet + * } + * if (events & (RF_EventLastCmdDone | RF_EventCmdStopped | RF_EventCmdAborted | RF_EventCmdCancelled)) + * { + * finished = true; + * } + * // ... + * } + * @endcode + * + * @note Calling context : Task + * + * @param h Driver handle previously returned by RF_open() + * @param ch Command handle previously returned by RF_postCmd(). + * @param bmEvent Bitmask of events that make RF_pendCmd() return. Termination events + * are always implicitly subscribed. + * @return Event flags accumulated during command execution. + * + * @sa RF_postCmd() + */ +extern RF_EventMask RF_pendCmd(RF_Handle h, RF_CmdHandle ch, RF_EventMask bmEvent); + +/** + * @brief Runs synchronously an RF operation command or a chain of commands and returns + * the termination reason. + * + * This function appends an RF operation command or a chain of commands to the RF driver's + * command queue and then waits for it to complete. + * A command is completed if one of the termination events ::RF_EventLastCmdDone, + * ::RF_EventCmdCancelled, ::RF_EventCmdAborted, ::RF_EventCmdStopped occurred. + * + * This function is a combination of RF_postCmd() and RF_pendCmd(). + * All options and limitations for RF_postCmd() apply here as well. + * + * An application should always ensure that the command completed in the expected way and + * with an expected status code. + * + * @note Calling context : Task + * + * @param h Driver handle previously returned by RF_open() + * @param pOp Pointer to the RF operation command. + * @param ePri Priority of this RF command (used for arbitration in multi-client systems) + * @param pCb Callback function called during command execution and upon completion. + * If RF_runCmd() fails, no callback is made. + * @param bmEvent Bitmask of events that will trigger the callback or that can be pended on. + * @return The relevant termination event. + * + * @sa RF_postCmd(), RF_pendCmd(), RF_cancelCmd(), RF_flushCmd() + */ +extern RF_EventMask RF_runCmd(RF_Handle h, RF_Op *pOp, RF_Priority ePri, RF_Callback pCb, RF_EventMask bmEvent); + +/** + * @brief Runs synchronously a (chain of) RF operation(s) for dual or single-mode. + * + * Allows a (chain of) operation(s) to be scheduled to the command queue and then waits + * for it to complete.
A command is completed if one of the RF_EventLastCmdDone, + * RF_EventCmdCancelled, RF_EventCmdAborted, RF_EventCmdStopped occurred. + * + * @note Calling context : Task + * @note Only one call to RF_pendCmd() or RF_runScheduleCmd() can be made at a time for + * each client + * + * @param h Handle previously returned by RF_open() + * @param pOp Pointer to the #RF_Op. Must normally be in persistent and writable memory + * @param pSchParams Pointer to the schedule command parameter structure + * @param pCb Callback function called upon command completion (and some other events). + * If RF_runScheduleCmd() fails, no callback is made. + * @param bmEvent Bitmask of events that will trigger the callback. + * @return The relevant command completed event. + */ +extern RF_EventMask RF_runScheduleCmd(RF_Handle h, RF_Op *pOp, RF_ScheduleCmdParams *pSchParams, RF_Callback pCb, RF_EventMask bmEvent); + +/** + * @brief Abort/stop/cancel single command in command queue. + * + * If command is running, aborts/stops it and posts callback for the + * aborted/stopped command.
+ * If command has not yet run, cancels it it and posts callback for the + * canceled command.
+ * If command has already run or been aborted/stopped/canceled, has no effect.
+ * If RF_cancelCmd is called from a Swi context with same or higher priority + * than RF Driver Swi, when the RF core is powered OFF -> the cancel callback will be delayed + * until the next power-up cycle.
+ * + * @note Calling context : Task/SWI + * + * @param h Handle previously returned by RF_open() + * @param ch Command handle previously returned by RF_postCmd(). + * @param mode 1: Stop gracefully, 0: abort abruptly + * @return RF_Stat indicates if command was successfully completed + */ +extern RF_Stat RF_cancelCmd(RF_Handle h, RF_CmdHandle ch, uint8_t mode); + +/** + * @brief Abort/stop/cancel command and any subsequent commands in command queue. + * + * If command is running, aborts/stops it and then cancels all later commands in queue.
+ * If command has not yet run, cancels it and all later commands in queue.
+ * If command has already run or been aborted/stopped/canceled, has no effect.
+ * The callbacks for all canceled commands are issued in chronological order.
+ * If RF_flushCmd is called from a Swi context with same or higher priority + * than RF Driver Swi, when the RF core is powered OFF -> the cancel callback will be delayed + * until the next power-up cycle.
+ * + * @note Calling context : Task/SWI + * + * @param h Handle previously returned by RF_open() + * @param ch Command handle previously returned by RF_postCmd(). + * @param mode 1: Stop gracefully, 0: abort abruptly + * @return RF_Stat indicates if command was successfully completed + */ +extern RF_Stat RF_flushCmd(RF_Handle h, RF_CmdHandle ch, uint8_t mode); + +/** + * @brief Send any Immediate command.
+ * + * Immediate Command is send to RDBELL, if radio is active and the RF_Handle points + * to the current client.
+ * In other appropriate RF_Stat values are returned.
+ * + * @note Calling context : Task/SWI/HWI + * + * @param h Handle previously returned by RF_open() + * @param pCmdStruct Pointer to the immediate command structure + * @return RF_Stat indicates if command was successfully completed + */ +extern RF_Stat RF_runImmediateCmd(RF_Handle h, uint32_t *pCmdStruct); + +/** + * @brief Send any Direct command.
+ * + * Direct Command value is send to RDBELL immediately, if radio is active and + * the RF_Handle point to the current client.
+ * In other appropriate RF_Stat values are returned.
+ * + * @note Calling context : Task/SWI/HWI + * + * @param h Handle previously returned by RF_open() + * @param cmd Direct command value. + * @return RF_Stat indicates if command was successfully completed. + */ +extern RF_Stat RF_runDirectCmd(RF_Handle h, uint32_t cmd); + +/** + * @brief Signal that radio client is not going to issue more commands in a while.
+ * + * Hint to RF driver that, irrespective of inactivity timeout, no new further + * commands will be issued for a while and thus the radio can be powered down at + * the earliest convenience. In case the RF_yield() is called within a callback, + * the callback will need to finish and return before the power down sequence is + * initiated. Posting new commands to the queue will cancel any pending RF_yield() + * request.
+ * + * @note Calling context : Task + * + * @param h Handle previously returned by RF_open() + */ +extern void RF_yield(RF_Handle h); + +/** + * @brief Function to initialize the RF_Params struct to its defaults. + * + * @param params An pointer to RF_Params structure for + * initialization + * + * Defaults values are: + * nInactivityTimeout = BIOS_WAIT_FOREVER + * nPowerUpDuration = RF_DEFAULT_POWER_UP_TIME + */ +extern void RF_Params_init(RF_Params *params); + +/** + * @brief Get value for some RF driver parameters.
+ * + * @note Calling context : Task/SWI/HWI + * + * @param h Handle previously returned by RF_open() + * @param type Request value parameter defined by RF_InfoType + * @param pValue Pointer to return parameter values specified by RF_InfoVal + * @return RF_Stat indicates if command was successfully completed + */ +extern RF_Stat RF_getInfo(RF_Handle h, RF_InfoType type, RF_InfoVal *pValue); + +/** + * @brief Get RSSI value. + * + * @note Calling context : Task/SWI/HWI + * + * @param h Handle previously returned by RF_open() + * @return RSSI value. Return value of RF_GET_RSSI_ERROR_VAL indicates error case. + */ +extern int8_t RF_getRssi(RF_Handle h); + +/** + * @brief Get command structure pointer. + * + * @note Calling context : Task/SWI/HWI + * + * @param h Handle previously returned by RF_open() + * @param cmdHnd Command handle returned by RF_postCmd() + * @return Pointer to the command structure. + */ +extern RF_Op* RF_getCmdOp(RF_Handle h, RF_CmdHandle cmdHnd); + +/** + * @brief Initialize the configuration structure to be used to set up a RAT compare event. + * + * @note Calling context : Task/SWI/HWI + * + * @param channelConfig Pointer to the compare configuration structure. + * @return none + */ +extern void RF_RatConfigCompare_init(RF_RatConfigCompare* channelConfig); + +/** + * @brief Initialize the configuration structure to be used to set up a RAT capture event. + * + * @note Calling context : Task/SWI/HWI + * + * @param channelConfig Pointer to the capture configuration structure. + * @return none + */ +extern void RF_RatConfigCapture_init(RF_RatConfigCapture* channelConfig); + +/** + * @brief Initialize the configuration structure to be used to set up a RAT IO. + * + * @note Calling context : Task/SWI/HWI + * + * @param ioConfig Pointer to the IO configuration structure. + * @return none + */ +extern void RF_RatConfigOutput_init(RF_RatConfigOutput* ioConfig); + +/** + * @brief Setup a Radio Timer (RAT) channel in compare mode. + * + * The %RF_ratCompare() API sets up one of the three available RAT channels in compare mode. + * When the compare event happens at the given compare time, the registered callback + * is invoked. + * + * The RF driver handles power management. If the provided compare time is far into the future + * (and there is no other constraint set i.e. due to radio command execution), the RF core will be + * powered OFF and the device will enter the lowest possible power state. The RF core will be + * automatically powered ON just before the registered compare event. The callback function is + * served upon expiration of the allocated channel. The function is invoked with event type + * #RF_EventRatCh and runs in SWI context. + * + * The API generates a "one-shot" compare event. Since the channel is automatically freed before + * the callback is served, the same channel can be reallocated from the callback itself through a + * new API call. + * + * In case there were no available channels at the time of API call, the function returns with + * #RF_ALLOC_ERROR and no callback is invoked. + * + * In case a runtime error occurs after the API successfully allocated a channel, the registered + * callback is invoked with event type #RF_EventError. A typical example is when the provided compare + * time is in the past and rejected by the RF core itself. + * + * The events issued by the RAT timer can be output from the timer module through the RAT_GPO + * interface, and can be interconnected with other parts of the system through the RFC_GPO or + * the Event Fabric. The mapping between the allocated RAT channel and the selected RAT_GPO + * can be controlled through the optional ioConfig argument of %RF_ratCompare(). The possible + * RAT_GPO[x] are defined in #RF_RatOutputSelect. + * + * @note Calling context : Task/SWI + * + * @param rfHandle Handle previously returned by RF_open(). + * @param channelConfig Pointer to configuration structure needed to set up a channel in compare mode. + * @param ioConfig Pointer to a configuration structure to set up the RAT_GPOs for the allocated + * channel (optional). + * @return Allocated RAT channel. If allocation fails, #RF_ALLOC_ERROR is returned. + * + * \sa #RF_RatConfigCompare_init(), #RF_RatConfigOutput_init(), #RF_ratDisableChannel(), #RF_ratCapture() + */ +extern RF_RatHandle RF_ratCompare(RF_Handle rfHandle, RF_RatConfigCompare* channelConfig, RF_RatConfigOutput* ioConfig); + +/** + * @brief Setup a Radio Timer (RAT) channel in capture mode. + * + * The %RF_ratCapture() API sets up one of the three available RAT channels in capture mode. + * The registered callback is invoked on the capture event. + * + * The RF driver handles power management. If the RF core is OFF when the %RF_ratCapture() is called, + * it will be powered ON immediately and the RAT channel will be configured to capture mode. As long as + * at least one of the three RAT channels are in capture mode, the RF core will be kept ON. The callback + * function is served upon a capture event occurs. The function is invoked with event type RF_EventRatCh + * and runs in SWI context. + * + * In case the channel is configured into single capture mode, the channel is automatically freed before + * the callback is called. In repeated capture mode, the channel remains allocated and automatically rearmed. + * + * In case there were no available channels at the time of API call, the function returns with + * #RF_ALLOC_ERROR and no callback is invoked. + * + * In case a runtime error occurs after the API successfully allocated a channel, the registered + * callback is invoked with event type #RF_EventError. A typical example is when the provided compare + * time is in the past and rejected by the RF core itself. + * + * The events issued by the RAT timer can be output from the timer module through the RAT_GPO + * interface, and can be interconnected with other parts of the system through the RFC_GPO or + * the Event Fabric. The mapping between the allocated RAT channel and the selected RAT_GPO + * can be controlled through the optional ioConfig argument of %RF_ratCapture(). The possible + * RAT_GPO[x] are defined in #RF_RatOutputSelect. Note that this configuration is independent of + * the source signal of the capture event. + * + * @note Calling context : Task/SWI + * + * @param rfHandle Handle previously returned by RF_open(). + * @param channelConfig Pointer to configuration structure needed to set up a channel in compare mode. + * @param ioConfig Pointer to a configuration structure to set up the RAT_GPO for the allocated + * channel (optional). + * @return Allocated RAT channel. If allocation fails, #RF_ALLOC_ERROR is returned. + * + * \sa #RF_RatConfigCapture_init(), #RF_RatConfigOutput_init() , #RF_ratDisableChannel(), #RF_ratCompare() + */ +extern RF_RatHandle RF_ratCapture(RF_Handle rfHandle, RF_RatConfigCapture* channelConfig, RF_RatConfigOutput* ioConfig); + +/** + * @brief Disable a RAT channel. + * + * The #RF_RatHandle returned by the #RF_ratCompare() or #RF_ratCapture() APIs can be used for further interaction with the + * Radio Timer. Passing the handle to %RF_ratDisableChannel() will abort a compare/capture event, and the provided channel + * is deallocated. No callback is invoked. This API can be called both if the RF core is ON or OFF. After the channel is + * freed, the next radio event will be rescheduled. A typical use case if a channel is configured in repeated capture mode, + * and the application decides to abort this operation. + * + * @note Calling context : Task/SWI + * + * @param rfHandle Handle previously returned by RF_open(). + * @param ratHandle #RF_RatHandle returned by #RF_ratCompare() or #RF_ratCapture(). + * @return #RF_Stat indicates if command was successfully completed. + * + * \sa #RF_ratCompare(), #RF_ratCapture() + */ +extern RF_Stat RF_ratDisableChannel(RF_Handle rfHandle, RF_RatHandle ratHandle); + +/** + * @brief Set RF control parameters. + * + * @note Calling context : Task + * + * @param h Handle previously returned by RF_open() + * @param ctrl Control codes + * @param args Pointer to control arguments + * @return RF_Stat indicates if API call was successfully completed. + */ +extern RF_Stat RF_control(RF_Handle h, int8_t ctrl, void *args); + +/** + * @brief Request radio access.
+ * + * Scope: + * 1. Only supports request access which start immediately.
+ * 2. The #RF_AccessParams duration should be less than a pre-defined value + * RF_REQ_ACCESS_MAX_DUR_US in RFCC26XX_multiMode.c.
+ * 3. The #RF_AccessParams priority should be set RF_PriorityHighest.
+ * 4. Single request for a client at anytime.
+ * 5. Command from different client are blocked until the radio access + * period is completed.
+ * + * @note Calling context : Task + * + * @param h Handle previously returned by RF_open() + * @param pParams Pointer to RF_AccessRequest parameters + * @return RF_Stat indicates if API call was successfully completed. + */ +extern RF_Stat RF_requestAccess(RF_Handle h, RF_AccessParams *pParams); + +/** + * @brief Returns the currently configured transmit power configuration. + * + * This function returns the currently configured transmit power configuration under the assumption + * that it has been previously set by #RF_setTxPower(). The value might be used for reverse + * lookup in a TX power table. If no power has been programmed, it returns an invalid value. + * + * @code + * RF_TxPowerTable_Value value = RF_getTxPower(handle); + * if (value.rawValue == RF_TxPowerTable_INVALID_VALUE) { + * // error, value not valid + * } + * @endcode + * + * @param h Handle previously returned by #RF_open() + * @return PA configuration struct + * + * @sa #RF_setTxPower(), #RF_TxPowerTable_findPowerLevel() + */ +extern RF_TxPowerTable_Value RF_getTxPower(RF_Handle h); + +/** + * @brief Updates the transmit power configuration of the RF core. + * + * This function programs a new TX power \a value and returns a status code. The API will return + * with RF_StatBusyError if there are still pending commands in the internal queue. In case of + * success, RF_StatSuccess is returned and the new configuration becomes effective from the next + * radio operation. + * + * Some devices provide an integrated high-power PA in addition to the Default PA. On these devices + * the API accepts configurations for both, and if \a value selects a different PA, the + * \a globalCallback is invoked. The implementation of \a globalCallback is board specific and can + * be used to reconfigure the external RF switches (if any). + * + * @param h Handle previously returned by #RF_open() + * @param value TX power configuration value. + * @return #RF_StatSuccess on success, otherwise an error code. + * + * @sa #RF_getTxPower(), #RF_TxPowerTable_Value, #RF_TxPowerTable_findValue() + */ +extern RF_Stat RF_setTxPower(RF_Handle h, RF_TxPowerTable_Value value); + +/** + * @brief Retrieves a power level in dBm for a given power configuration value. + * + * \c %RF_TxPowerTable_findPowerLevel() searches in a lookup \a table for a given transmit power + * configuration \a value and returns the power level in dBm if a matching configuration is found. + * If \a value can not be found, #RF_TxPowerTable_INVALID_DBM is returned. + * + * This function does a reverse lookup compared to #RF_TxPowerTable_findValue() and has + * O(n). It is assumed that \a table is terminated by a #RF_TxPowerTable_TERMINATION_ENTRY. + * + * @param table List of #RF_TxPowerTable_Entry entries, + * terminated by #RF_TxPowerTable_TERMINATION_ENTRY. + * + * @param value Power configuration value. + * + * @return Human readable power level in dBm on success, + * otherwise #RF_TxPowerTable_INVALID_DBM. + */ +extern int8_t RF_TxPowerTable_findPowerLevel(RF_TxPowerTable_Entry table[], RF_TxPowerTable_Value value); + +/** + * @brief Retrieves a power configuration value for a given power level in dBm. + * + * \c %RF_TxPowerTable_findValue() searches in a lookup \a table for a given transmit power level + * \a powerLevel in dBm and returns a matching power configuration. If \a powerLevel can not be + * found, #RF_TxPowerTable_INVALID_VALUE is returned. + * + * This function performs a linear search in \a table and has O(n). + * It is assumed that \a table is defined in ascending order and is terminated by a + * #RF_TxPowerTable_TERMINATION_ENTRY. + * + * The following special values for \a powerLevel are also accepted: + * + * - #RF_TxPowerTable_MIN_DBM which returns always the lowest power value in the table + * - #RF_TxPowerTable_MAX_DBM which returns always the highest power value in the table + * + * @param table List of #RF_TxPowerTable_Entry entries, + * terminated by #RF_TxPowerTable_TERMINATION_ENTRY. + * + * @param powerLevel Human-readable power level in dBm. + * + * @return PA configuration value on success. + * otherwise #RF_TxPowerTable_INVALID_VALUE. + */ +extern RF_TxPowerTable_Value RF_TxPowerTable_findValue(RF_TxPowerTable_Entry table[], int8_t powerLevel); + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_rf__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RFCC26X2_multiMode.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RFCC26X2_multiMode.c new file mode 100644 index 0000000..acfd12e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RFCC26X2_multiMode.c @@ -0,0 +1,5714 @@ +/* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_rfc_rat.h) +#include DeviceFamily_constructPath(inc/hw_rfc_dbell.h) +#include DeviceFamily_constructPath(driverlib/rfc.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) +#include DeviceFamily_constructPath(driverlib/rf_mailbox.h) +#include DeviceFamily_constructPath(driverlib/adi.h) +#include DeviceFamily_constructPath(driverlib/aon_rtc.h) +#include DeviceFamily_constructPath(driverlib/chipinfo.h) +#include DeviceFamily_constructPath(driverlib/aon_batmon.h) +#include DeviceFamily_constructPath(driverlib/osc.h) + +#if defined(__IAR_SYSTEMS_ICC__) +#pragma diag_remark=Pa082 +#endif + +#if defined(RF_SINGLEMODE) +#error "An incompatible symbol (RF_SINGLEMODE) is defined in the project. \ + To build with this driver, remove the RF_SINGLEMODE token definition." +#endif + +/*-------------- Typedefs, structures & defines ---------------*/ + +/* Definition of internal state-machine events. */ +typedef enum RF_FsmEvent_ { + RF_FsmEventLastCommandDone = (1UL << 1), /* Indicates that a radio command is finished. */ + RF_FsmEventWakeup = (1UL << 2), /* Used to initiate the power up sequence of the RF core. */ + RF_FsmEventPowerDown = (1UL << 3), /* Used to initiate the power down sequence of the RF core. */ + RF_FsmEventInitChangePhy = (1UL << 10), /* Used to initiate the PHY change sequence. */ + RF_FsmEventFinishChangePhy = (1UL << 11), /* Used to finalize the PHY change sequence. */ + RF_FsmEventCpeInt = (1UL << 14), /* Generated during command execution. */ + RF_FsmEventPowerStep = (1UL << 29), /* Generated during the power up sequence of RF core. */ + RF_FsmEventRunScheduler = (1UL << 30) /* Used to invoke the scheduler again to check for conflicts. */ +} RF_FsmEvent; + +/* Definition of states of RF core. */ +typedef enum RF_CoreStatus_ { + RF_CoreStatusIdle = 0, /* The RF core is OFF. */ + RF_CoreStatusPoweringUp = 1, /* The RF core is being powered up. */ + RF_CoreStatusActive = 2, /* The RF core is ON. */ + RF_CoreStatusPoweringDown = 3, /* The RF core is being powered down. */ + RF_CoreStatusPhySwitching = 4 /* The RF core is being reconfigured. */ +} RF_CoreStatus; + +/* Definition of internal power constraints. Note that the physical RAT channels in the RF core are + not a one-to-one map to the constraint values here. */ +typedef enum RF_PowerConstraintSrc_ { + RF_PowerConstraintNone = 0, + RF_PowerConstraintRatCh0 = (1U << 0), /* Indicates that the Channel 0 of RAT timer is running. */ + RF_PowerConstraintRatCh1 = (1U << 1), /* Indicates that the Channel 1 of RAT timer is running. */ + RF_PowerConstraintRatCh2 = (1U << 2), /* Indicates that the Channel 2 of RAT timer is running. */ + RF_PowerConstraintCmdQ = (1U << 3), /* Indicates that the RF core executing a radio command. */ + RF_PowerConstraintDisallow = (1U << 7) /* Disable automatic power management. */ +} RF_PowerConstraintSrc; + +/* Definition of internal Radio Timer (RAT) modes. */ +typedef enum RF_RatMode_ { + RF_RatModeUndefined = 0, /* Indicates that the RAT channel is not configured. */ + RF_RatModeCompare = 1, /* Indicates that the RAT channel is configured to compare mode. */ + RF_RatModeCapture = 2 /* Indicates that the RAT channel is configured to capture mode. */ +} RF_RatMode; + +/* Definition of internal Radio Timer (RAT) states. */ +typedef enum RF_RatStatus_ { + RF_RatStatusIdle = 0, /* Indicates that the RAT channel is not used. */ + RF_RatStatusPending = 1, /* Indicates that the RAT channel is configured, but the RAT timer is not running (i.e. RF core is OFF). */ + RF_RatStatusRunning = 2 /* Indicates that the RAT channel is configured, and the RAT timer is running. */ +} RF_RatStatus; + +/* Definition of internal status codes of command shceduling. */ +typedef enum RF_ScheduleCmdStatus_ { + RF_ScheduleCmdSuccess = 0, /* Schedule command success. */ + RF_ScheduleCmdAllocError = 1, /* Schedule command allocation error (such as queue is full). */ + RF_ScheduleCmdSchError = 2 /* SChedule command scheduler error (timing or priority conflict). */ +} RF_ScheduleCmdStatus; + +/*-------------- Macros ---------------*/ + +#define ABS(x) (((x) < 0) ? -(x) : (x)) +#define MAX(x,y) (((x) > (y)) ? (x) : (y)) +#define MIN(x,y) (((x) < (y)) ? (x) : (y)) +#define UDIFF(x,y) (((y) > (x)) ? ((y) - (x)) : ((~0) + (y) - (x) + (1))) +#define ADD(x,y) ((x > ((~0) - (y))) ? (~0) : ((x) + (y))) + +/*-------------- Defines ---------------*/ + +/* Max # of RF driver clients */ +#define N_MAX_CLIENTS 2 +/* 8 RF_Cmds in pool */ +#define N_CMD_POOL 8 +/* Modulus mask used for RF_CmdHandle calculations */ +#define N_CMD_MODMASK 0xFFF + +/*-------------- Internal RF constants ---------------*/ + +#define RF_CMD0 0x0607 +#define RF_BOOT0 0xE0000011 +#define RF_BOOT1 0x00000080 +/* Accessible RF Core interrupts mask MSB 32 bits : RFHW int, LSB 32 bits : RF CPE int */ +#define RF_INTERNAL_IFG_MASK 0xFFFFFFDF60001000 +#define RF_TERMINATION_EVENT_MASK (RF_EventLastCmdDone | RF_EventLastFGCmdDone | RF_EventCmdAborted | RF_EventCmdStopped | RF_EventCmdCancelled) +#define RF_CMD_FG_CMD_FLAG (1 << 4) +#define RF_CMD_ALLOC_FLAG (1 << 7) +#define RF_CMD_TERMINATED (DONE_OK | ERROR_PAST_START) +#define RF_HW_INT_RAT_CH_MASK (RFC_DBELL_RFHWIFG_RATCH7 | RFC_DBELL_RFHWIFG_RATCH6 | RFC_DBELL_RFHWIFG_RATCH5) +#define RF_RAT_CH_CNT 3 +#define RF_HW_INT_CPE_MASK RFC_DBELL_RFHWIFG_MDMSOFT +#define RF_CPE0_INT_MASK 0xFFFFFFFF +/* Default value for power up duration (in us) used before first power cycle */ +#define RF_DEFAULT_POWER_UP_TIME 2500 +/* Default minimum power up duration (in us) */ +#define RF_DEFAULT_MIN_POWER_UP_TIME 300 +/* Default power-up margin (in us) to account for wake-up sequence outside the RF power state machine */ +#define RF_DEFAULT_POWER_UP_MARGIN 314 +/* Default phy-switching margin (in us) to account for overhead of processing time on the system MCU. */ +#define RF_DEFAULT_PHY_SWITCHING_MARGIN 314 +/* Default power down duration in us */ +#define RF_DEFAULT_POWER_DOWN_TIME 1000 +#define RF_MAX_CHAIN_CMD_LEN 8 +/* RAT channel (0-4) are used by RF Core. Only 5,6,7 are available for application */ +#define RF_RAT_CH_LOWEST 5 +#define RF_SEND_RAT_STOP_RATIO 7 +#define RF_RTC_CONV_TO_US_SHIFT 12 +#define RF_SHIFT_4_BITS 4 +#define RF_SHIFT_8_BITS 8 +#define RF_SHIFT_16_BITS 16 +#define RF_SHIFT_32_BITS 32 +#define RF_RTC_TICK_INC (0x100000000LL/32768) +#define RF_SCALE_RTC_TO_4MHZ 4000000 +#define RF_NUM_RAT_TICKS_IN_1_US 4 +/* (3/4)th of a full RAT cycle, in us */ +#define RF_DISPATCH_MAX_TIME_US (UINT32_MAX / RF_NUM_RAT_TICKS_IN_1_US * 3 / 4) +/* (1/4)th of a full RAT cycle, in us */ +#define RF_DISPATCH_MAX_TIME_WRAPAROUND_US (int32_t)(RF_DISPATCH_MAX_TIME_US - UINT32_MAX / RF_NUM_RAT_TICKS_IN_1_US) +#define RF_DISPATCH_INFINIT_TIME (UINT32_MAX) +#define RF_XOSC_HF_SWITCH_CHECK_PERIOD_US 50 +#define RF_DEFAULT_AVAILRATCH_VAL 0x7 +#define RF_ABORT_FLUSH_ALL 0x2 +#define RF_CMDSTA_REG_VAL_MASK 0xFF +#define RF_RAT_CAPTURE_REPEAT_MODE 0x10000000 +#define RF_RAT_INTERRUPT_BASE_INDEX 0x01 +#define RF_RAT_ERROR_BASE_INDEX 0x10 +#define RF_RAT_COMPENSATION_TIME_US 25 +#define RF_PHY_SWITCHING_MODE 1 +#define RF_PHY_BOOTUP_MODE 0 +#define RF_SCH_CMD_TIMING_INSERT 0x4 +#define RF_REQ_ACCESS_MAX_DUR_US 1000000 +/* Additional analog config time for setup command */ +#define RF_ANALOG_CFG_TIME_US 96 +/* Update analog configuration in setup */ +#define RF_SETUP_ANALOGCFG_UPDATE 0 +/* Don't update analog configuration in setup */ +#define RF_SETUP_ANALOGCFG_NOUPDATE 0x2D +#define RF_SCH_CMD_STARTTIME_NOW 0 +#define RF_SCH_CMD_ENDTIME_IGNORE 0 +#define RF_DEFAULT_PHY_SWITCHING_TIME 500 +#define RF_RADIOFREECB_PREEMPT_FLAG 0x1 +#define RF_RADIOFREECB_REQACCESS_FLAG 0x2 +#define RF_RADIOFREECB_CMDREJECT_FLAG 0x4 +#define RF_DEFAULT_RAT_RTC_ERR_TOL_IN_US 5 +/* Approx for 1e6 / 500. XTAL drift is 500 ppm */ +#define RF_DEFAULT_COMB_XTAL_DRIFT_BITS_SHIFT 11 +/* Window (in us) to decide if wakeup was from RF power up clock */ +#define RF_WAKEUP_DETECTION_WINDOW_IN_US 300 +/* Ieee context mask and background value */ +#define RF_IEEE_ID_MASK 0xFC00 +#define RF_IEEE_FG_CMD 0x2C00 +/* Defines for to mask High-PA overrides. */ +#define RF_TX20_ENABLED 0xFFFF +#define RF_TX20_PATYPE_ADDRESS 0x21000345 +#define RF_TX20_PATYPE_MASK 0x04 +#define RF_TX20_GAIN_ADDRESS 0x2100034C +#define RF_TX20_GAIN_MASK 0x003FFFFF +#define RF_TX20_PATTERN TX20_POWER_OVERRIDE(0) +#define RF_TXSTD_PATTERN TX_STD_POWER_OVERRIDE(0) +#define RF_TX_OVERRIDE_MASK 0x000003FF +#define RF_TX_OVERRIDE_SHIFT 10 +#define RF_TX_OVERRIDE_INVALID_OFFSET 0xFF +/* Defines for update of the HPOSC override */ +#define RF_HPOSC_OVERRIDE_PATTERN HPOSC_OVERRIDE(0) +#define RF_HPOSC_OVERRIDE_MASK 0xFFFF +/* Common defines for override handling*/ +#define RF_OVERRIDE_SEARCH_DEPTH 80 + +/*-------------- Structures and definitions ---------------*/ + +/* FSM typedef. */ +typedef void (*RF_FsmStateFxn)(RF_Object*, RF_FsmEvent const); + +/* Rat channel configuration. */ +typedef struct RF_RatChannel_s RF_RatChannel; + +/* Rat channel configuration. */ +struct RF_RatChannel_s { + RF_Handle pClient; /* Pointer to current client. NULL means the channel is free. */ + RF_RatCallback pCb; /* Callback pointer of the channel. */ + RF_RatMode mode; /* Mode of this RAT channel: RF_RatModeCompare, etc. */ + RF_RatHandle handle; /* Channel number: 0,1,2. */ + RF_RatStatus status; /* Status of the channel: RF_RatStatusIdle, RF_RatStatusPending, RF_RatStatusRunning */ + uint64_t chCmd; /* Generic storage for the command structure itself. */ + uint32_t ioCmd; /* Raw binary to be sent to the CM0 to set up the GPOs. This is optional. */ +}; + +/* Rat module configuration. */ +typedef struct RF_RatModule_s RF_RatModule; + +/* Rat module configuration. */ +struct RF_RatModule_s { + RF_RatChannel channel[RF_RAT_CH_CNT]; /* Container of channel configurations. */ + uint8_t availableRatChannels; /* Storage of available RAT channels read from the RF core. */ + uint8_t volatile pendingInt; /* Pending interrupt flags to be served. */ + uint8_t numActiveChannels; /* Counter of active channels. This is used to compensate the + overhead of programming the channels.*/ +}; + +/* RF core configuration. */ +typedef struct RF_CoreState_s RF_CoreState; + +/* RF core configuration. */ +struct RF_CoreState_s +{ + RF_CoreStatus volatile status; + RF_FsmStateFxn fxn; + uint32_t activeTimeUs; + bool init; + bool manualXoscHfSelect; +}; + +/* RAT synchronization. */ +typedef union RF_RatSyncCmd_u RF_RatSyncCmd; + +/* RAT synchronization. */ +union RF_RatSyncCmd_u +{ + rfc_CMD_SYNC_START_RAT_t start; + rfc_CMD_SYNC_STOP_RAT_t stop; +}; + +/* Reconfigure the PA settings. */ +typedef union RF_ConfigurePaCmd_u RF_ConfigurePaCmd; + +/* Reconfigure the PA settings. */ +union RF_ConfigurePaCmd_u { + rfc_CMD_SET_TX_POWER_t tuneTxPower; + rfc_CMD_SET_TX20_POWER_t tuneTx20Power; + rfc_CMD_CHANGE_PA_t changePa; +}; + +/* Command queue. */ +typedef struct RF_CmdQ_s RF_CmdQ; + +/* Command queue. */ +struct RF_CmdQ_s{ + List_List pPend; /* List of pending commands to be dispatched. */ + List_List pDone; /* List of executed commands to be served. */ + RF_Cmd* volatile pCurrCmdBg; /* Currently running command. */ + RF_Cmd* volatile pCurrCmdFg; /* Currently running foreground command. */ + RF_Cmd* volatile pCurrCmdCb; /* Command which callback to be invoked. */ + RF_CmdHandle volatile nSeqPost; /* Sequence # for previously posted command. */ + RF_CmdHandle volatile nSeqDone; /* Sequence # for last done command. */ +}; + +/* RF scheduler. */ +typedef struct RF_Sch_s RF_Sch_t; + +/* RF scheduler. */ +struct RF_Sch_s { + RF_Handle clientHnd[N_MAX_CLIENTS]; /* Client handle for each registered client. */ + RF_AccessParams accReq[N_MAX_CLIENTS]; /* Input parameters from any RF_requestAccess API calls. */ + RF_Handle clientHndRadioFreeCb; /* Client handle for the radio callback. */ + uint8_t issueRadioFreeCbFlags; /* Indicate if driver needs to issue RF_EventRadioFree callback {0:pre-emption, 1:requestAccess running, 2: reject command}. */ + uint8_t cmdInsertFlags; /* Indicate if the command was inserted based on timing information. */ +}; + +/*-------------- RTOS objects ---------------*/ + +/* RF core software interrupts */ +static SwiP_Struct RF_swiFsmObj; +static void RF_swiFsm(uintptr_t a, uintptr_t b); + +/* RF core hardware interrupts */ +static HwiP_Struct RF_hwiCpe0Obj; +static void RF_hwiCpe0Active(uintptr_t a); +static void RF_hwiCpe0PowerFsm(uintptr_t a); + +/* RF core HW software interrupts */ +static SwiP_Struct RF_swiHwObj; +static void RF_swiHw(uintptr_t a, uintptr_t b); + +/* RF core HW hardware interrupts */ +static HwiP_Struct RF_hwiHwObj; +static void RF_hwiHw(uintptr_t a); + +/* Clock used for triggering power-up sequences */ +static ClockP_Struct RF_clkPowerUpObj; +static void RF_clkPowerUp(uintptr_t a); + +/* Common inactivity timeout clock callback */ +static ClockP_Struct RF_clkInactivityObj; +static void RF_clkInactivityCallback(uintptr_t a); + +/* Common request access timeout clock callback */ +static void RF_clkReqAccess(uintptr_t a); + + +/*-------------- Static structures ---------------*/ + +/* Default RF parameters structure */ +static const RF_Params RF_defaultParams = { + .nInactivityTimeout = SemaphoreP_WAIT_FOREVER, + .nPowerUpDuration = 0, + .pPowerCb = NULL, + .pErrCb = NULL, + .nPowerUpDurationMargin = RF_DEFAULT_POWER_UP_MARGIN, + .nPhySwitchingDurationMargin = RF_DEFAULT_PHY_SWITCHING_MARGIN, + .pClientEventCb = NULL, + .nClientEventMask = 0, +}; + +/*-------------- Global variables ---------------*/ + +/* RF_Cmd container pool. Containers with extra information about RF commands. */ +static RF_Cmd RF_cmdPool[N_CMD_POOL]; + +/* Command queue top level structure. It contains pointers to the different queues. */ +static RF_CmdQ RF_cmdQ; + +/* Static object used to subscribe from early notification in the power driver */ +static Power_NotifyObj RF_wakeupNotifyObj; + +/* Power constraints set by the RF driver */ +static volatile uint8_t RF_powerConstraint; + +/* Pointer to current radio client (indicates also whether the radio is powered) */ +static RF_Object* RF_currClient; + +/* Current state of the RF core. */ +static RF_CoreState RF_core; + +/* Static container of a direct/immediate commands */ +static RF_RatModule RF_ratModule; + +/* Commands used to synchronize the RTC and the RAT timer. */ +static volatile RF_RatSyncCmd RF_ratSyncCmd; + +/* Top level structure of the shceduler unit. */ +static RF_Sch_t RF_Sch; + +/* Variables used for powerUpDuration, phySwitchingTime and RAT sync time calculation. */ +static uint32_t RF_rtcTimestampA; /* RTC timer value power-up and active time calculation. */ +static uint32_t RF_rtcBeginSequence; /* RTC timer value for switching time calculation. */ +static uint32_t RF_errTolValInUs; /* max allowed error between RAT/RTC drift to enable resync at power-down (in us). */ + +/* Counter of radio clients */ +static uint8_t RF_numClients; + +/*-------------- Externs ---------------*/ + +/* Hardware attribute structure populated in board file. */ +extern const RFCC26XX_HWAttrsV2 RFCC26XX_hwAttrs; + +/* Software policy set in the board file and implements the distributed scheduling algorithm. */ +__attribute__((weak)) const RFCC26XX_SchedulerPolicy RFCC26XX_schedulerPolicy = { + .submitHook = RF_defaultSubmitPolicy, + .conflictHook = RF_defaultConflictPolicy +}; + +/*-------------- Booleans ---------------*/ + +/* variable to indicate with the FLASH is disable during the power up */ +static bool bDisableFlashInIdleConstraint; + +/*-------------- State machine functions ---------------*/ + +/* FSM state functions */ +static void RF_fsmPowerUpState(RF_Object *pObj, RF_FsmEvent e); +static void RF_fsmSetupState(RF_Object *pObj, RF_FsmEvent e); +static void RF_fsmActiveState(RF_Object *pObj, RF_FsmEvent e); +static void RF_fsmXOSCState(RF_Object *pObj, RF_FsmEvent e); + +/*-------------- Helper functions ---------------*/ + +/* Command queue handling */ +static RF_Cmd* RF_queueEnd(RF_Handle h, List_List* pHead); + +/* Command handling*/ +static bool RF_isClientOwner(RF_Handle h, RF_Cmd* pCmd); +static RF_Cmd* RF_cmdAlloc(void); +static RF_Cmd* RF_cmdGet(RF_Handle h, RF_CmdHandle ch, uint8_t mask); +static void RF_cmdStoreEvents(RF_Cmd* pCmd, RF_EventMask events); +static bool RF_cmdDispatchTime(uint32_t* dispatchTimeClockTicks, bool conflict, RF_Cmd** pAbsCmd); +static RF_Stat RF_abortCmd(RF_Handle h, RF_CmdHandle ch, bool graceful, bool flush, bool preempt); +static bool RF_checkCmdFsError(void); +static void RF_cacheFsCmd(RF_Cmd* pCmd); +static uint32_t RF_discardPendCmd(RF_Handle h, RF_Cmd* pCmd, bool bFlushAll, bool bPreempt); + +/* Scheduler */ +static void RF_issueRadioFreeCb(uint8_t src); +static bool RF_verifyGap(RF_Cmd* newCmd, RF_Cmd* prevCmd, RF_Cmd* nextCmd); +static RF_ScheduleStatus RF_howToSchedule(RF_Cmd* newCmd, RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue, RF_Cmd** pInsertLocation); + +/* RAT module */ +static RF_RatChannel* RF_ratGetChannel(uint8_t ch); +static RF_RatChannel* RF_ratAllocChannel(RF_RatHandle ratChannel); +static uint32_t RF_ratGetChannelValue(RF_RatHandle ratHandle); +static uint32_t RF_ratGetValue(void); +static void RF_ratGenerateChCmd(RF_RatChannel* ratCh, void* ratConfig); +static void RF_ratGenerateIoCmd(RF_RatChannel* ratCh, RF_RatConfigOutput* ioConfig); +static RF_RatHandle RF_ratSetupChannel(RF_Handle ratClient, RF_RatMode ratMode, RF_RatCallback ratCallback, RF_RatHandle ratChannel, void* ratConfig, RF_RatConfigOutput* ioConfig); +static void RF_ratRestartChannels(void); +static RF_Stat RF_ratArmChannel(RF_RatChannel* ratCh); +static void RF_ratFreeChannel(RF_RatChannel* ratCh); +static void RF_ratSuspendChannels(void); +static bool RF_ratReleaseChannels(void); +static bool RF_ratDispatchTime(uint32_t* dispatchTimeClockTicks); +static bool RF_ratIsRunning(void); + +/* Time management */ +static uint32_t RF_calculateDeltaTimeUs(uint32_t absTime, uint32_t nTotalPowerUpDuration); +static bool RF_calculateDispatchTime(uint32_t* dispatchTimeClockTicks); +static void RF_dispatchNextEvent(void); +static void RF_dispatchNextCmd(void); +static void RF_restartClockTimeout(ClockP_Handle clock, uint32_t timeout); + +/* Power management */ +static void RF_corePowerDown(void); +void RF_powerConstraintRelease(RF_PowerConstraintSrc src); +void RF_powerConstraintSet(RF_PowerConstraintSrc src); +RF_PowerConstraintSrc RF_powerConstraintGet(RF_PowerConstraintSrc src); +static void RF_setInactivityTimeout(void); + +/* Others */ +static void RF_init(void); +static void RF_defaultCallback(RF_Handle h, RF_CmdHandle ch, RF_EventMask e); +static RF_Stat RF_runDirectImmediateCmd(RF_Handle h, uint32_t pCmd, uint32_t* rawStatus); +static RF_Stat RF_executeDirectImmediateCmd(uint32_t pCmd, uint32_t* rawStatus); +static void RF_invokeGlobalCallback(RF_GlobalEvent event, void* arg); +static void RF_dbellSubmitCmdAsync(uint32_t rawCmd); +static void RF_dbellSyncOnAck(void); +static bool RF_isRadioSetup(RF_Op* pOp); +static void RF_initRadioSetup(RF_Handle handle); +static void RF_radioOpDoneCb(void); +static RF_Op* RF_findEndOfChain(RF_Op* pOp); +static void RF_applyRfCorePatch(bool mode); +static bool RF_isStateTransitionAllowed(void); + +/* PA management */ +static RF_Stat RF_updatePaConfiguration(RF_RadioSetup* radioSetup, RF_TxPowerTable_Value newValue, RF_ConfigurePaCmd* configurePaCmd); +static void RF_extractPaConfiguration(RF_Handle handle); +static bool RF_decodeOverridePointers(RF_RadioSetup* radioSetup, uint16_t** pTxPower, uint32_t** pRegOverride, uint32_t** pRegOverrideTxStd, uint32_t** pRegOverrideTx20); +static void RF_attachOverrides(uint32_t* baseOverride, uint32_t* newOverride); +static void RF_detachOverrides(uint32_t* baseOverride, uint32_t* newOverride); + +/* HPOSC management */ +static void RF_updateHpOscOverride(uint32_t *pRegOverride); + +/*-------------- Command queue internal functions ---------------*/ + +/* + * Compares the client of a command. + * + * Input: h - Client to check against. + * pCmd - Command to check. + * Return: true - If the client owns the command. + * false - Otherwise. + */ +static bool RF_isClientOwner(RF_Handle h, RF_Cmd* pCmd) +{ + if (pCmd && (pCmd->pClient == h)) + { + return(true); + } + else + { + return(false); + } +} + +/* + * Search last entry in simple queue for particular client. + * + * Input: h - Client handle. + * list - List to search within. + * Return: RF_Cmd if found any + */ +static RF_Cmd* RF_queueEnd(RF_Handle h, List_List* list) +{ + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Local variables */ + List_Elem* pTail = NULL; + List_Elem* pHead = List_head(list); + + /* Start at the head of queue */ + while (pHead) + { + if (RF_isClientOwner(h, (RF_Cmd*)pHead)) + { + pTail = pHead; + } + + pHead = List_next(pHead); + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with the last entry belongs to the client */ + return((RF_Cmd*)pTail); +} + +/* + * Allocate a command buffer from the command pool. + * + * Input: none + * Return: RF command + */ +static RF_Cmd* RF_cmdAlloc(void) +{ + uint32_t i; + for (i = 0; i < N_CMD_POOL; i++) + { + /* Find the first available entry in the command pool */ + if (!(RF_cmdPool[i].flags & RF_CMD_ALLOC_FLAG)) + { + return(&RF_cmdPool[i]); + } + } + return(NULL); +} + +/* + * Search command in the command pool. + * + * Input: h - Handle to the client which the command should belong to. + * ch - Handle to the command to search for. + * mask - Optional mask of flags to compare to. + * Return: RF command + */ +static RF_Cmd* RF_cmdGet(RF_Handle h, RF_CmdHandle ch, uint8_t mask) +{ + uint32_t i; + for (i = 0; i < N_CMD_POOL; i++) + { + /* Find the allocated command pool entry corresponding to ch */ + if (RF_cmdPool[i].ch == ch) + { + if (RF_isClientOwner(h, &RF_cmdPool[i])) + { + /* If a mask is provided, check the flags too */ + if (!mask || (RF_cmdPool[i].flags & mask)) + { + return(&RF_cmdPool[i]); + } + } + } + } + return(NULL); +} + +/* + * Atomic storage of radio events happened during the execution of a command. + * + * Input: pCmd - Command the events belogn to. + * events - The radio events to be store within the context of the command. + * Return: none + */ +static void RF_cmdStoreEvents(RF_Cmd* pCmd, RF_EventMask events) +{ + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Store the events within the context of the command. */ + if (pCmd) + { + /* The field rfifg store the events for the next callback. + The field pastifg accumulates the events in case an + RF_pendCmd() API call happens. */ + pCmd->rfifg |= events; + pCmd->pastifg |= events; + } + + /* Exit critical section. */ + HwiP_restore(key); +} + +/* + * Reconfigure and restart a particular clock object. + * + * Input: clockObj - A pointer to a clock object. + * timeoutClockTicks - The timeout to be set in unit of clock ticks. + * Return: none + */ +static void RF_restartClockTimeout(ClockP_Handle clockHandle, uint32_t timeoutClockTicks) +{ + /* Ceil the value at minimum 1 clock tick. */ + timeoutClockTicks = MAX(timeoutClockTicks, 1); + + /* Reprogram the clock object. */ + ClockP_setTimeout(clockHandle, timeoutClockTicks); + ClockP_start(clockHandle); +} + +/* + * Calculate the delta time to an RF event including the overhead of powering up + * and down. + * + * Input: abstime - The timestamp the event will need to happen. + * nTotalPowerUpDuration - The duration we need to compensate with. + * Return: deltaTime - The time left until the RF core need to be trigged. + */ +static uint32_t RF_calculateDeltaTimeUs(uint32_t absTime, uint32_t nTotalPowerUpDuration) +{ + /* Local variables. */ + uint32_t deltaTimeUs; + + /* Read the timestamp to calculate difference from. */ + uint32_t currentTime = RF_getCurrentTime(); + + /* Calculate the difference with the current timestamp. */ + deltaTimeUs = UDIFF(currentTime, absTime); + deltaTimeUs /= RF_NUM_RAT_TICKS_IN_1_US; + + /* Check if delta time is greater than (powerup duration + power down duration) for a + power cycle, and is less than 3/4 of a RAT cycle (~17 minutes) */ + if ((deltaTimeUs > (int32_t)(nTotalPowerUpDuration + RF_DEFAULT_POWER_DOWN_TIME)) && + (deltaTimeUs <= RF_DISPATCH_MAX_TIME_US)) + { + /* Dispatch command in the future */ + return(MAX((deltaTimeUs - nTotalPowerUpDuration), 1)); + } + else + { + /* Dispatch immediately */ + return(0); + } +} + +/* + * Calculate the wakeup time of next command in the queue. + * + * Input: dispatchTimeClockTicks - Location where the calculated time is being stored. + * conflict - true: compare to the first command which have TRIG_ABSTIME trigger type. + * false: compare to the first command in the queue + * pAbsCmd - Pointer to the first command which has an absolute start time. + * Return: validTime - Indicates if the returned time is valid. + */ +static bool RF_cmdDispatchTime(uint32_t* dispatchTimeClockTicks, bool conflict, RF_Cmd** pAbsCmd) +{ + /* By default, there is no command in the queue. */ + RF_Cmd* pCmd = NULL; + bool validTime = false; + + /* The input argument determines which command to use as a reference. This is to be able to + reuse the calculation for both power management and conflict resolution. */ + if (conflict == true) + { + /* Start from the beginning of queue. */ + RF_Cmd* pTempCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + /* Walk the queue and find the first command contains an absolute start time. */ + while (pTempCmd) + { + /* Finish the search upon the first match. This assumes that commands with + absolute start times are in order. */ + if (pTempCmd->pOp->startTrigger.triggerType == TRIG_ABSTIME) + { + pCmd = pTempCmd; + break; + } + else + { + /* Continue the search if no match. */ + pTempCmd = (RF_Cmd*)List_next((List_Elem*)pTempCmd); + } + } + } + else + { + /* The next command in the queue independently of its type determines the timing. */ + pCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + } + + /* Only recognizes TRIG_ABSTIME triggers, everything else gets dispatched immediately. */ + if (pCmd) + { + /* If there is at least one pending command, we can calculate a legit dispatch time. */ + validTime = true; + + /* Return with the command which we calculate the remained time against. */ + if (pAbsCmd) + { + *pAbsCmd = pCmd; + } + + /* If the start trigger is absolute, we can calculate the time difference. */ + if (pCmd->pOp->startTrigger.triggerType == TRIG_ABSTIME) + { + uint32_t nTotalDuration = 0; + + /* Calculate the sum of overhead it takes to start up and configure the RF core. */ + if (conflict == true) + { + nTotalDuration = pCmd->pClient->clientConfig.nPhySwitchingDuration + + pCmd->pClient->clientConfig.nPhySwitchingDurationMargin; + } + else + { + nTotalDuration = pCmd->pClient->clientConfig.nPowerUpDuration + + pCmd->pClient->clientConfig.nPowerUpDurationMargin + + (RF_RAT_COMPENSATION_TIME_US * RF_ratModule.numActiveChannels); + } + + /* Calculate the remained time until this absolute event. The calculation takes + into account the minimum power cycle time. */ + *dispatchTimeClockTicks = RF_calculateDeltaTimeUs(pCmd->pOp->startTime, nTotalDuration); + + /* Scale the value to clock ticks*/ + *dispatchTimeClockTicks /= ClockP_tickPeriod; + } + else + { + /* Dispatch immediately. */ + *dispatchTimeClockTicks = 0; + } + } + else + { + /* This value will not be used. */ + *dispatchTimeClockTicks = 0; + } + + /* If the returned timestamp represents a valid dispatch time, return with true. */ + return(validTime); +} + +/* + * Determines if the RAT timer is running (clock is not gated) or not. + * This is used to determine if any RAT related command can be execured. + * + * Input: none + * Return: PWMCLK_EN_RAT - RAT timer is running. + * 0 - RAT timer is not running. + */ +static bool RF_ratIsRunning(void) +{ + /* Assume by default that the RAT is not available. */ + bool status = false; + + /* If the RF core power domain is ON, read the clock of the RAT. */ + if (HWREG(PRCM_BASE + PRCM_O_PDSTAT0) & PRCM_PDSTAT0_RFC_ON) + { + status = (bool)(HWREG(RFC_PWR_BASE + RFC_PWR_O_PWMCLKEN) & RFC_PWR_PWMCLKEN_RAT_M); + } + + /* Return with the status of RAT. */ + return(status); +} + +/* + * Allocate a RAT channel from the three slots available + * for the user. + * + * Input: ratChannel - Pointer to a user provided RF_RatHandle. + * Return: RF_RatChannel* - Pointer to the allocated channel if success. + * NULL - If failure. + */ +static RF_RatChannel* RF_ratAllocChannel(RF_RatHandle ratChannel) +{ + /* Walk the RAT channel indexes. */ + uint32_t i; + for (i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Calculate the bit representing this channel within the available channels. */ + uint32_t bitMask = (1 << i); + + /* Verify that no one is using this channel (from outside the scope of RF driver). */ + if (RF_ratModule.availableRatChannels & bitMask) + { + /* Mask the possible channels if a user handle is provided, otherwise find the + the first available channel. */ + if ((ratChannel == RF_RatChannelAny) || (ratChannel == i)) + { + /* Decode the fields of a channel. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* If an available channel is found. */ + if (ratCh && (ratCh->status == RF_RatStatusIdle)) + { + /* Mark the channel as occupied. */ + RF_ratModule.availableRatChannels &= ~bitMask; + + /* Put the channel into pending state. */ + ratCh->status = RF_RatStatusPending; + ratCh->handle = i; + + /* Increment the counter of active channels. This is used to compensate the + power up time with the overhead of programming these channels. */ + RF_ratModule.numActiveChannels += 1; + + /* Return with a pointer to the channel. */ + return(ratCh); + } + } + } + } + + /* Return with an invalid channel pointer in case of error. */ + return(NULL); +} + +/* + * Free a given RAT channel. + * + * Input: ratCh - Pointer to a RAT channel in RF_ratModule. + * Return: none + */ +static void RF_ratFreeChannel(RF_RatChannel* ratCh) +{ + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* If a valid pointer is provided */ + if (ratCh && ratCh->status) + { + /* Precalculate the contraint ID of this channel. */ + RF_PowerConstraintSrc powerConstraint = (RF_PowerConstraintSrc)(1 << ratCh->handle); + + /* If the RF core power domain is ON. */ + if (RF_ratIsRunning()) + { + /* Calculate the channel index based on the handle. */ + uint32_t ratChIntFlag = (1 << (RFC_DBELL_RFHWIFG_RATCH5_BITN + ratCh->handle)); + + /* Disable the RAT channel interrupt source. */ + RFCHwIntDisable(ratChIntFlag); + RFCHwIntClear(ratChIntFlag); + } + + /* Reset the status of the channel. */ + ratCh->status = RF_RatStatusIdle; + ratCh->mode = RF_RatModeUndefined; + ratCh->pClient = NULL; + ratCh->pCb = NULL; + ratCh->chCmd = 0; + ratCh->ioCmd = 0; + + /* Mark the channel as available. */ + RF_ratModule.availableRatChannels |= (1 << ratCh->handle); + + /* Decrement the counter of active channels. To avoid underflow, check its value first. */ + if (RF_ratModule.numActiveChannels) + { + RF_ratModule.numActiveChannels -= 1; + } + + /* Notify the state machine that the RF core can be possibly powered down. */ + RF_powerConstraintRelease(powerConstraint); + } + + /* Exit critical section */ + HwiP_restore(key); +} + +/* + * Returns with a pointer to a RAT channel based on it's handle. + * + * Input: ch - Channel handle. + * Return: ratCh - Pointer to a RAT channel in RF_ratModule. + */ +static RF_RatChannel* RF_ratGetChannel(uint8_t ch) +{ + /* Convert a valid index into a pointer of a RAT channel configuration. */ + if (ch < RF_RAT_CH_CNT) + { + return((RF_RatChannel*)&RF_ratModule.channel[ch]); + } + + /* Return with NULL in case of invalid input argument. */ + return(NULL); +} + +/* + * Suspend the running channels and potentially initiate a power down. + * + * Input: none + * Return: true - All RAT channel is suspended. + * false - Otherwise. + */ +static bool RF_ratReleaseChannels(void) +{ + /* Only try to release the RAT channels if there is no other dependencies set. */ + if (!RF_powerConstraintGet(RF_PowerConstraintCmdQ) && + !RF_powerConstraintGet(RF_PowerConstraintDisallow)) + { + /* Calculate if there is enough time to power down and up. */ + uint32_t dispatchTimeClockTicks; + bool validTime = RF_calculateDispatchTime(&dispatchTimeClockTicks); + + /* If the next event is sufficiently far into the future. */ + if (!validTime || (validTime && dispatchTimeClockTicks)) + { + /* Suspend all RAT channels. */ + RF_ratSuspendChannels(); + + /* RAT channels were suspended. */ + return(true); + } + } + + /* RAT channels were not suspended. */ + return(false); +} + +/* + * Calculate the timeout of closest RAT event. + * + * Input: dispatchTimeClockTicks - Location where the calculated time is being stored. + * Return: validTime - Indicates if the returned time is valid. + */ +static bool RF_ratDispatchTime(uint32_t* dispatchTimeClockTicks) +{ + /* By default, there is no RAT running. */ + bool validTime = false; + + /* Initialize the return value. */ + *dispatchTimeClockTicks = RF_DISPATCH_INFINIT_TIME; + + /* Iterate through the RAT containers and calculate the remained time until + the closest RAT event. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Use a local pointer to have easier access to member fields. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* If the channel is either in PENDING or RUNNING state, meaning it is in use. */ + if (ratCh && ratCh->status) + { + /* There is at least one active channel, we can calculate a legit timestamp. */ + validTime = true; + + /* If there is at least one channel in Capture mode, we need to power + up immediately. */ + if (ratCh->mode == RF_RatModeCapture) + { + /* Use immediate timeout orcing the RF core to be powered up. */ + *dispatchTimeClockTicks = 0; + + /* No point to look to the other RAT channels.*/ + break; + } + else + { + /* Decode the compareTime field. */ + uint32_t compareTime = ((rfc_CMD_SET_RAT_CMP_t*)&ratCh->chCmd)->compareTime; + + /* Calculate the remained time until this RAT event. The calculation takes + into account the minimum power cycle time. */ + uint32_t deltaTimeUs = RF_calculateDeltaTimeUs(compareTime, + RF_currClient->clientConfig.nPowerUpDuration + + RF_currClient->clientConfig.nPowerUpDurationMargin + + (RF_RAT_COMPENSATION_TIME_US * RF_ratModule.numActiveChannels)); + + /* Scale the value to clock ticks. */ + uint32_t deltaTimeClockTicks = deltaTimeUs / ClockP_tickPeriod; + + /* If this is the closest RAT event, update the timer. */ + if (deltaTimeClockTicks < (*dispatchTimeClockTicks)) + { + *dispatchTimeClockTicks = deltaTimeClockTicks; + } + } + } + } + + /* Return with true if the dispatchTime represents a valid timestamp. */ + return(validTime); +} + +/* + * Arms a given RAT channel. The mode of the channel will define which mode + * it is being configured to. The cmd variable contains the raw word to be + * sent to the RF core. + * + * Input: ratCh - Pointer to a RAT channel. + * Return: status - Status code based on the response of RF core. + * + */ +static RF_Stat RF_ratArmChannel(RF_RatChannel* ratCh) +{ + /* Local variable */ + RF_Stat status = RF_StatError; + + /* Only those channels can be programmed which are in pending state. */ + if (ratCh && (ratCh->status == RF_RatStatusPending)) + { + /* Calculate the channel interrupt flag on the handle. */ + uint32_t ratChIntFlag = (1 << (RFC_DBELL_RFHWIFG_RATCH5_BITN + ratCh->handle)); + + /* Clear and enable the interrupt source for that particular channel. */ + RFCHwIntClear(ratChIntFlag); + RFCHwIntEnable(ratChIntFlag); + + /* Set the power constraint on this channel to keep the RF core ON. */ + RF_powerConstraintSet((RF_PowerConstraintSrc)(1 << ratCh->handle)); + + /* Send the command to the RF core. */ + status = RF_executeDirectImmediateCmd((uint32_t)&ratCh->chCmd, NULL); + + /* If the channel configuration is succesfull. */ + if (status == RF_StatCmdDoneSuccess) + { + /* Send the IO command to the RF core if there is any configured. */ + if (ratCh->ioCmd) + { + status = RF_executeDirectImmediateCmd((uint32_t)ratCh->ioCmd, NULL); + } + + /* If both the channel and io configuration is succesfull. */ + if (status == RF_StatCmdDoneSuccess) + { + ratCh->status = RF_RatStatusRunning; + } + } + } + + /* Return with the status code. */ + return(status); +} + +/* + * Restarts any RAT channels which are in pending state at the moment of + * invoking this method. This is used to automatically restore the rat module + * right after the RF core is powered up. This is essential for power management. + * + * Input: none + * Return: none + * + */ +static void RF_ratRestartChannels(void) +{ + /* Iterate through the RAT containers and restore the channels + which were in running state before we entered Standby mode. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Convert the index to a pointer. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* If the channel is in pending state, program it. */ + if (ratCh && (ratCh->status == RF_RatStatusPending)) + { + /* Try to program the RAT channel. */ + RF_Stat status = RF_ratArmChannel(ratCh); + + /* Execute error handling if programming fails, i.e. due to past timestamp. + This is done in SWI context. */ + if (status != RF_StatCmdDoneSuccess) + { + /* Mark the event as an error by setting also a shadow bit. */ + RF_ratModule.pendingInt |= ((RF_RAT_INTERRUPT_BASE_INDEX | RF_RAT_ERROR_BASE_INDEX) << ratCh->handle); + + /* Post the SWI handler to serve the callback. */ + SwiP_or(&RF_swiHwObj, 0); + } + } + } +} + +/* + * Suspends any RAT channel which are in RUNNING state. + * This is used to force all RAT channels into pending state allowing the power + * management to power off the RF core power domain and resynchronize the RAT channels + * on next power up. + * + * Input: none + * Return: none + */ +static void RF_ratSuspendChannels(void) +{ + /* Iterate through the RAT containers and suspend the active channels. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Set a pointer to the channel. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* Only actively running channles can be suspended. */ + if (ratCh && ratCh->status) + { + /* Set the status to be suspended. */ + ratCh->status = RF_RatStatusPending; + + /* Clear the power constraint of this channel */ + RF_powerConstraintRelease((RF_PowerConstraintSrc)(1 << ratCh->handle)); + } + } +} + +/* + * Read the counter value from the RAT timer. + * + * Input: none + * Return: time - The value found in the RATCNT running register. + */ +static uint32_t RF_ratGetValue(void) +{ + return(HWREG(RFC_RAT_BASE + RFC_RAT_O_RATCNT)); +} + +/* + * Read the channel value from the RAT timer. + * + * Input: ratHandle - The handle to the channel. + * Return: timeout - The value found in the RATCHxVAL register. + */ +static uint32_t RF_ratGetChannelValue(RF_RatHandle ratHandle) +{ + /* Read the channel value. */ + return(HWREG(RFC_RAT_BASE + RFC_RAT_O_RATCH5VAL + ratHandle * sizeof(uint32_t))); +} + +/* + * Generate a command which can be used to configure a RAT channel into COMPARE mode. + * + * Input: ratCh - Pointer to the channel. + * ratConfig - Configuration structure holding the channel setup. + * Return: none + */ +static void RF_ratGenerateChCmd(RF_RatChannel* ratCh, void* ratConfig) +{ + /* Generate a command based on the mode. */ + if (ratCh->mode == RF_RatModeCompare) + { + /* Local pointer to cast the configuration to the proper type. */ + RF_RatConfigCompare* ratCompareConfig = (RF_RatConfigCompare*) ratConfig; + + /* Point a pointer to the generic command field within the channels context. */ + rfc_CMD_SET_RAT_CMP_t* pCmd = (rfc_CMD_SET_RAT_CMP_t*)&ratCh->chCmd; + + /* Populate the command structure properly. */ + pCmd->commandNo = CMD_SET_RAT_CMP; /* Instruct the RF core to use COMPARE mode. */ + pCmd->ratCh = RF_RAT_CH_LOWEST + ratCh->handle; /* Encode the selected channel number. */ + pCmd->compareTime = ratCompareConfig->timeout; /* Select the compare timeout. */ + } + else if (ratCh->mode == RF_RatModeCapture) + { + /* Local pointer to cast the configuration to the proper type. */ + RF_RatConfigCapture* ratCaptureConfig = (RF_RatConfigCapture*) ratConfig; + + /* Point a pointer to the generic command field within the channels context. */ + rfc_CMD_SET_RAT_CPT_t* pCmd = (rfc_CMD_SET_RAT_CPT_t*)&ratCh->chCmd; + + /* Calculate the direct command to be sent to the RF core.*/ + pCmd->commandNo = CMD_SET_RAT_CPT; /* Instruct the RF core to use CAPTURE mode. */ + pCmd->config.ratCh = RF_RAT_CH_LOWEST + ratCh->handle; /* Encode the selected channel number. */ + pCmd->config.inputSrc = ratCaptureConfig->source; /* Select the source to be captured. */ + pCmd->config.inputMode = ratCaptureConfig->captureMode; /* Select the mode of capture: raising, falling, etc*/ + pCmd->config.bRepeated = ratCaptureConfig->repeat; /* Select if we should re-arm the channel after a capture event. */ + } +} + +/* + * Generate a command which can be used to configure an IO for a particular RAT channel. + * + * Input: ratCh - Pointer to the channel. + * ioConfig - Configuration channel for the IO. + * Return: cmdToDoorbell - Return with the command structure. It is casted to uint32_t as it is + * stored in a generic variable. + */ +static void RF_ratGenerateIoCmd(RF_RatChannel* ratCh, RF_RatConfigOutput* ioConfig) +{ + /* Local variable. */ + uint32_t cmdToDoorbell = 0; + + /* If there is an IO configuration. */ + if (ioConfig) + { + cmdToDoorbell |= ioConfig->select << 2; + cmdToDoorbell |= ioConfig->mode << 5; + cmdToDoorbell |= (uint32_t)(RF_RAT_CH_LOWEST + ratCh->handle) << 8; + + cmdToDoorbell = (uint32_t)CMDR_DIR_CMD_2BYTE(CMD_SET_RAT_OUTPUT, cmdToDoorbell); + } + + /* Return with the raw command to be sent to the doorbell. */ + ratCh->ioCmd = cmdToDoorbell; +} + +/* + * Wrapper function to setup a RAT channel into the selected mode. + * + * Input: ratClient - Handle previously returned by RF_open(). + * ratMode - Identifies the mode the channel is being set up: RF_RatModeCompare or RF_RatModeCapture. + * ratCallback - Callback function to be registered to the RAT channel. + * ratChannel - Preferred channel to be allocated. If RF_RatChannelAny is provided, allocatethe first available channel. + * ratConfig - Configuration structure holding the setup of the particulare channel. + * ioConfig - Configuration strucutre of the assosiated GPO setup. + * Return: ratHandle - RF_RatHandle to the allocated channel. If allocation fails, RF_ALLOC_ERROR is returned. + */ +static RF_RatHandle RF_ratSetupChannel(RF_Handle ratClient, RF_RatMode ratMode, RF_RatCallback ratCallback, RF_RatHandle ratChannel, void* ratConfig, RF_RatConfigOutput* ioConfig) +{ + /* Return with an error. Either we couldn't allocate any RAT + channel, or the RAT module declined our configuration. */ + RF_RatHandle ratHandle = (RF_RatHandle)RF_ALLOC_ERROR; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Find and allocate a RAT channel (if any is available) */ + RF_RatChannel* ratCh = RF_ratAllocChannel(ratChannel); + + /* If we could allocate a RAT channel */ + if (ratCh) + { + /* Populate the container. Use the default "do nothing" callback + if no user callback is provided and generate the command based + on the mode of the channel. */ + ratCh->pClient = ratClient; + ratCh->mode = ratMode; + ratCh->pCb = (RF_RatCallback)RF_defaultCallback; + RF_ratGenerateChCmd(ratCh, ratConfig); + RF_ratGenerateIoCmd(ratCh, ioConfig); + + /* If there is a user callback provided, override the default callback. */ + if (ratCallback) + { + ratCh->pCb = ratCallback; + } + + /* Decide which PHY should be used upon first start up. */ + if (RF_currClient == NULL) + { + RF_currClient = ratCh->pClient; + } + + /* Calculate the RAT/RTC timestamp to be used to wake the RF core. */ + RF_dispatchNextEvent(); + + /* Return with the handle upon success. */ + ratHandle = (RF_RatHandle)ratCh->handle; + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with either an error OR a handle to a RAT channel. */ + return(ratHandle); +} + +/* + * Poll the RFACKIFG and clear the flag afterwards. This is used during the power up sequence + * of the RF core where interlaying processing is implemented. + * + * Input: none + * Return: none + */ +static void RF_dbellSyncOnAck(void) +{ + while (!HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG)); + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0; +} + +/* + * Submit a command to the doorbell without blocking command execution. This is used during the + * power up sequence where the system CPU can continue with processing data while the RF core + * executes the submitted command. + * + * Input: rawCmd - The raw command to be written to the doorbell. This can be a pointer or a + * a direct/immediate command. + * Return: none + */ +static void RF_dbellSubmitCmdAsync(uint32_t rawCmd) +{ + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0; + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) = rawCmd; +} + +/* + * Wake up notification callback from the power driver. If the callback is from RF wakeup + * set constraint to let RF Driver control the XOSC switching else do nothing in the + * callback. + * + * Input: eventType - The type of event when the notification is invoked + * eventArg - Not used. + * clientArg - Not used. + * Return: Power_NOTIFYDONE + */ +static uint8_t RF_wakeupNotification(uint8_t eventType, uint32_t *eventArg, uint32_t *clientArg) +{ + /* Check if the callback is for wakeup from standby and if power up clock is running */ + if ((eventType == PowerCC26XX_AWAKE_STANDBY) && (ClockP_isActive(&RF_clkPowerUpObj))) + { + /* Calculate time (in us) until next trigger (assume next trigger is max ~70 min away) */ + uint32_t timeInUsUntilNextTrig = ClockP_tickPeriod * ClockP_getTimeout(&RF_clkPowerUpObj); + + /* Check if the next trig time is close enough to the actual power up */ + if (timeInUsUntilNextTrig < RF_WAKEUP_DETECTION_WINDOW_IN_US) + { + /* Stop power up clock */ + ClockP_stop(&RF_clkPowerUpObj); + + /* Setup RF Driver to do the XOSC_HF switching */ + Power_setConstraint(PowerCC26XX_SWITCH_XOSC_HF_MANUALLY); + + /* Set variable to indicate RF Driver will do the XOSC_HF switching */ + RF_core.manualXoscHfSelect = true; + + /* Start the RF Core power up */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventWakeup); + } + } + + return(Power_NOTIFYDONE); +} + +/*-------------- Scheduler internal functions --------------------------------*/ + +/* + * Issue RF_EventRadioFree callback to the client. The callback is issued - + * 1. After pre-emption is complete + * 2. Dedicated request access period expires or released + * 3. command reject because of other high priority command running + * + * Input: src - Flag indicating the source of callback request. + * Return: none + */ +static void RF_issueRadioFreeCb(uint8_t src) +{ + /* Enter critical section*/ + uint32_t key = HwiP_disable(); + + /* Clear the reason why the callback is being invoked */ + RF_Sch.issueRadioFreeCbFlags &= ~src; + + /* Local variable */ + bool isReqAccessActive = false; + + /* If any of the clients has active request access, indicate it */ + if (RF_Sch.clientHnd[0]) + { + isReqAccessActive |= ClockP_isActive(&RF_Sch.clientHnd[0]->state.clkReqAccess); + } + if (RF_Sch.clientHnd[1]) + { + isReqAccessActive |= ClockP_isActive(&RF_Sch.clientHnd[1]->state.clkReqAccess); + } + + /* If we cleared all the potential sources and there is no request access*/ + if ((RF_Sch.issueRadioFreeCbFlags == 0) && !isReqAccessActive) + { + /* If a valid client handle is provided through the global pointer */ + if (RF_Sch.clientHndRadioFreeCb && (RF_Sch.clientHndRadioFreeCb->clientConfig.nClientEventMask & RF_ClientEventRadioFree)) + { + /* Get a pointer to the client event callback */ + RF_ClientCallback pClientEventCb = (RF_ClientCallback)RF_Sch.clientHndRadioFreeCb->clientConfig.pClientEventCb; + + /* Exit critical section */ + HwiP_restore(key); + + /* Invoek the client event callback */ + pClientEventCb(RF_Sch.clientHndRadioFreeCb, RF_ClientEventRadioFree, NULL); + + /* Clear the client pointer in any case */ + RF_Sch.clientHndRadioFreeCb = NULL; + } + else + { + /* Exit critical section */ + HwiP_restore(key); + } + } + else + { + /* Exit critical section */ + HwiP_restore(key); + } +} + +/* + * Decode how much time it will take to switch protocol/phy configuration. + * + * Input: prevCmd - The command switching from. + * nextCmd - The command switching to. + * Return: switchingTime - The time it takes to switch the PHY. + */ +static int32_t RF_getSwitchingTimeInUs(RF_Cmd* prevCmd, RF_Cmd* nextCmd) +{ + int32_t switchingTime = 0; + + /* If otherCmd and newCmd are from different client then there is a switching time + related to moving between the two commands. */ + if (prevCmd->pClient != nextCmd->pClient) + { + switchingTime = nextCmd->pClient->clientConfig.nPhySwitchingDuration; + } + + /* Return the switching time related to moving between the two clients. */ + return(switchingTime); +} + +/* + * Check if new request can inserted between the previous and next command in the + * current queue. + * + * Input: newCmd - RF_Cmd pointer for the new command request + * prevCmd - RF_Cmd pointer for the previous cmd in the queue + * nextCmd - RF_Cmd pointer for the next cmd in the queue + * Return: true - If command can be inserted in the queue else + * false - Otherwise. + */ +static bool RF_verifyGap(RF_Cmd* newCmd, RF_Cmd* prevCmd, RF_Cmd* nextCmd) +{ + /* Initialize local variables. */ + bool insertNewCmdAfterPrev = prevCmd ? false : true; + bool insertNewCmdBeforeNext = nextCmd ? false : true; + int32_t deltaInUs = 0; + + /* Step 1 - The newCmd must have an endTime in order to be placed anywhere + else than the end. Or if there are no commands behind. */ + if ((newCmd) && (insertNewCmdBeforeNext || (newCmd->endTime != RF_SCH_CMD_ENDTIME_IGNORE))) + { + /* If there is a prevCmd and it have an endTime, we could potentially + put the new command behind it. */ + if ((prevCmd) && (prevCmd->endTime != RF_SCH_CMD_ENDTIME_IGNORE)) + { + /* Take the start time of the command located later in the timeline. */ + deltaInUs = (int32_t)RF_convertRatTicksToUs(newCmd->startTime); + + /* Substract the time earlier in the timeline. The result is the gap in between. */ + deltaInUs -= (int32_t)RF_convertRatTicksToUs(prevCmd->endTime); + + /* Substract the switching time needed to move between prevCmd and newCmd. */ + deltaInUs -= RF_getSwitchingTimeInUs(prevCmd, newCmd); + + /* Handle timer overflow with the assumption that the difference between the startTime + and endTime is less than ~8 min. */ + if ((deltaInUs < ((int32_t)RF_DISPATCH_MAX_TIME_WRAPAROUND_US)) || (deltaInUs > 0)) + { + /* Allow insertion if startTime has wrapped around or no wrap around and we can insert the command */ + insertNewCmdAfterPrev = true; + } + } + + /* If there is a nextCmd, and it has an aboslute startTime, we could potentially put the new command in front of it. + If we already have evaluated that we can't be behind the prevCmd, there is no need to evalue this. */ + if ((insertNewCmdAfterPrev) && (nextCmd) && (nextCmd->pOp->startTrigger.triggerType == TRIG_ABSTIME)) + { + /* Take the start time of the command located later in the timeline. */ + deltaInUs = (int32_t)RF_convertRatTicksToUs(nextCmd->startTime); + + /* Substract the time earlier in the timeline. The result is the gap in between. */ + deltaInUs -= (int32_t)RF_convertRatTicksToUs(newCmd->endTime); + + /* Substract the switching time needed to move between newCmd and nextCmd. */ + deltaInUs -= RF_getSwitchingTimeInUs(newCmd, nextCmd); + + /* Handle timer overflow with the assumption that the difference between the startTime + and endTime is less than ~8 min. */ + if ((deltaInUs < ((int32_t)RF_DISPATCH_MAX_TIME_WRAPAROUND_US)) || (deltaInUs > 0)) + { + /* Allow insertion if startTime has wrapped around or no wrap around and we can insert the command. */ + insertNewCmdBeforeNext = true; + } + } + } + + /* Return with true if the command can be inserted into the queue (both before or after criteria met). */ + return(insertNewCmdBeforeNext & insertNewCmdAfterPrev); +} + +/* + * Check what scheduling strategy that can be used to schedule the requesting command. + * + * Input: newCmd - Points to the newly submitted radio command, + * pCmdBg - Points to the active background command (if any). + * pCmdFg - Points to the active foreground command (if any). + * pPendQueue - Points to the queue holding the commands to be executed. + * pDoneQueue - Points to the queue holding the commands which has been exeuted. + * pInsertLocation - Reference to command which the newCmd shall be inserted behind. + * + * Return: RF_ScheduleStatus - Returning status containing the scheduling decision. + */ +static RF_ScheduleStatus RF_howToSchedule(RF_Cmd* newCmd, RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue, RF_Cmd** pInsertLocation) +{ + /* By default, reject any new request. */ + volatile RF_ScheduleStatus status = RF_ScheduleStatusError; + + /* Typecast the arguments to RF commands. */ + RF_Cmd* pHead = (RF_Cmd*)List_head(pPendQueue); + + /* Load list head as the start point of the iterator. */ + RF_Cmd* it = pHead; + + /* Step 1 - Check if new command can be inserted based on the timing information + at the top of the pending queue. */ + if (RF_verifyGap(newCmd, pCmdBg, pHead)) + { + /* Indicate that the command was put on the top of the queue.ss */ + status = RF_ScheduleStatusTop; + } + + /* Step 2 - Check if new command can be inserted based on the timing information + in the middle/end of the pending queue. This require the new command + to have an ABSOLUTE startTrigger type. */ + if ((status == RF_ScheduleStatusError) && (newCmd->pOp->startTrigger.triggerType == TRIG_ABSTIME)) + { + /* Walk the queue.*/ + while (it) + { + /* Check if we can insert the new command in between. */ + if (RF_verifyGap(newCmd, it, (RF_Cmd*)List_next((List_Elem*)it))) + { + /* Set the return value that the new command should be + inserted in between it and it->pNext. */ + status = RF_ScheduleStatusMiddle; + break; + } + else + { + it = (RF_Cmd*)List_next((List_Elem*)it); + } + } + } + + /* Step 3 - If step 1) or 2) fails, reject or append the command to the end of the queue + based on the allowDelay argument of RF_scheduleCmd() API call. */ + if ((status == RF_ScheduleStatusError) && (newCmd->allowDelay)) + { + status = RF_ScheduleStatusTail; + } + + /* Set pInsertLocation to mark where to insert the new command. */ + *pInsertLocation = it; + + /* Return with the scheduling method. */ + return(status); +} + +/** + * Sorts and adds command to the RF driver internal command queue. + * + * Input: pCmdNew - Pointer to the command to be submitted. + * pCmdBg - Running background command. + * pCmdFg - Running foreground command. + * pPendQueue - Pointer to the head structure of pend queue. + * pDoneQueue - Pointer to the head structure of done queue. + * Return: RF_ScheduleStatus - Identifies the success or failure of enquing. + */ +RF_ScheduleStatus RF_defaultSubmitPolicy(RF_Cmd* pCmdNew, RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue) +{ + /* Local pointer to a command which will be used if insertition + is selected as a method. */ + RF_Cmd* pInsertLocation = NULL; + + /* Check the method how the new command should be scheduled. */ + RF_ScheduleStatus status = RF_howToSchedule(pCmdNew, pCmdBg, pCmdFg, pPendQueue, pDoneQueue, &pInsertLocation); + + /* Step 1 - If the new command is placed to the top of the pend queue. */ + if (status == RF_ScheduleStatusTop) + { + /* Insert command at the beginning of the queue */ + List_putHead(pPendQueue, (List_Elem*)pCmdNew); + } + + /* Step 2 - If the new command is inserted behind a particular command. */ + if (status == RF_ScheduleStatusMiddle) + { + /* Insert command between pInsertLocation and pInsertLocation->pNext. */ + if (List_next((List_Elem*)pInsertLocation)) + { + /* Insert command before pInsertLocation->next. */ + List_insert(pPendQueue, (List_Elem*)pCmdNew, List_next((List_Elem*)pInsertLocation)); + } + else + { + /* Append command to the end of the queue (if next does not exist). */ + List_put(pPendQueue, (List_Elem*)pCmdNew); + } + } + + /* Step 3 - Append command to the end of the queue. */ + if (status == RF_ScheduleStatusTail) + { + List_put(pPendQueue, (List_Elem*)pCmdNew); + } + + /* Return command with the method we used to schedule the command. + Might be RF_ScheduleStatusError if none of the above rules applied. */ + return(status); +} + +/** + * Sorts and adds command to the RF driver internal command queue. + * + * Input: pCmdBg - Running background command. + * pCmdFg - Running foreground command. + * pPendQueue - Pointer to the head structure of pend queue. + * pDoneQueue - Pointer to the head structure of done queue. + * Return: RF_ScheduleStatus - Identifies the success or failure of enquing. + */ +RF_Conflict RF_defaultConflictPolicy(RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue) +{ + return(RF_ConflictNone); +} + +/* + * Execute RF power down sequence. + * + * Input: none + * Return: none + */ +static void RF_corePowerDown(void) +{ + /* Local variables to calculate active time in current window. */ + uint32_t deltaTimeInUs = 0; + + /* Disable all CPE and HW interrupts as we are about to power down the core. + Clearing is not important as content will be lost anyway. */ + RFCCpeIntDisable(~0); + RFCHwIntDisable(~0); + + /* Remap HWI to the startup function (preparing for next wake up) */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0PowerFsm, (uintptr_t)NULL); + + /* Take wake up timestamp and the current timestamp */ + uint32_t rtcTimestampB = (uint32_t) AONRTCCurrent64BitValueGet(); + + /* Find the radio core active delta time since the last power up. */ + deltaTimeInUs = UDIFF(RF_rtcTimestampA, rtcTimestampB); + deltaTimeInUs >>= RF_RTC_CONV_TO_US_SHIFT; + + /* Accumulate the delta time with the previous active time windows. Avoid overflow. */ + RF_core.activeTimeUs = ADD(RF_core.activeTimeUs, deltaTimeInUs); + + /* Decide whether to send the CMD_SYNC_STOP_RAT command. If this is first power down (.init) or active time (activeTimeInUs) + is longer than the time that can cause maximum allowed error between RAT and RTC clocks. Yielding will automatically fulfill + the latter. */ + if (!(RF_core.init) || + (RF_core.activeTimeUs > (RF_errTolValInUs << RF_DEFAULT_COMB_XTAL_DRIFT_BITS_SHIFT))) + { + /* Stop and synchronize the RAT if it is running */ + if (RF_ratIsRunning()) + { + /* Setup RAT_SYNC command to follow powerdown. */ + RF_ratSyncCmd.stop.commandNo = CMD_SYNC_STOP_RAT; + RF_ratSyncCmd.stop.status = IDLE; + RF_ratSyncCmd.stop.condition.rule = COND_NEVER; + RF_ratSyncCmd.stop.startTrigger.triggerType = TRIG_NOW; + RF_ratSyncCmd.stop.pNextOp = NULL; + + /* Send RAT Stop command and synchronously wait until it run. */ + RF_dbellSubmitCmdAsync((uint32_t)&RF_ratSyncCmd.stop); + while (!(RF_ratSyncCmd.stop.status & RF_CMD_TERMINATED)); + } + + /* The RF core is now initialized and RAT is synchronized. */ + RF_core.init = true; + RF_core.activeTimeUs = 0; + } + + /* Turn off Synth */ + RFCSynthPowerDown(); + + /* Turn off the RF core by gating its clock. This is a quick way to have it shut off. */ + RFCClockDisable(); +} + +/*-------------- Power constraints internal functions ------------------------*/ + +/* + * Set RF power constraints. + * + * Input: src - RF_PowerConstraintSrc (Source: Queue or RAT) + * Return: none + */ +void RF_powerConstraintSet(RF_PowerConstraintSrc src) +{ + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Set constraint based on source */ + RF_powerConstraint |= src; + + /* Exit critical section */ + HwiP_restore(key); +} + +/* + * Release RF power constraints. + * + * Input: src - RF_PowerConstraintSrc (Source: Queue or RAT) + * Return: none + */ +void RF_powerConstraintRelease(RF_PowerConstraintSrc src) +{ + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Release this constraint. */ + RF_powerConstraint &= ~src; + + /* Check if all constraints are clear. */ + if (!(RF_powerConstraint & RF_PowerConstraintCmdQ)) + { + /* Initiate power down if the above criterion is met. + The RAT timer though might will prevent us to proceed. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventPowerDown); + } + + /* Exit critical section. */ + HwiP_restore(key); +} + +/* + * Get RF power constraints. + * + * Input: src - Mask of constraints we requesting + * Return: Bitwise-OR of the power constraints set and the input argument + */ +RF_PowerConstraintSrc RF_powerConstraintGet(RF_PowerConstraintSrc src) +{ + /* Set constraint based on source */ + return((RF_PowerConstraintSrc)(RF_powerConstraint & (uint8_t)src)); +} + +/* + * It calculates and returns the closest RF event in time if any. + * + * Calling context: Hwi, Swi + * + * Input: dispatchTime - pointer to a container where the calculated time can be returned + * Return: ticks - If command is far away in future. + * 0 - If command is too close and should be scheduled now. + */ +static bool RF_calculateDispatchTime(uint32_t* dispatchTimeClockTicks) +{ + /* Local variables. */ + uint32_t deltaTimeCmdClockTicks; + uint32_t deltaTimeRatClockTicks; + + /* Initialize return value. */ + *dispatchTimeClockTicks = 0; + + /* Calculate the timestamp of the next command in the command queue. */ + bool validCmdTime = RF_cmdDispatchTime(&deltaTimeCmdClockTicks, false, NULL); + + /* If any of the RAT timers expire before the command should be dispatched, + reprogram the power up clock to the RAT event instead. */ + bool validRatTime = RF_ratDispatchTime(&deltaTimeRatClockTicks); + + if (validCmdTime && validRatTime) + { + /* Determine if command execution or RAT event comes first. */ + *dispatchTimeClockTicks = MIN(deltaTimeCmdClockTicks, deltaTimeRatClockTicks); + } + else if (validCmdTime) + { + /* Command queue determines the next event. */ + *dispatchTimeClockTicks = deltaTimeCmdClockTicks; + } + else if (validRatTime) + { + /* RAT timer determines the next event. */ + *dispatchTimeClockTicks = deltaTimeRatClockTicks; + } + + /* If any of them valid, return with true indicating a valid dispatch time. */ + return(validCmdTime || validRatTime); +} + +/* + * Dispatch the closest event generated either by a command or the RAT timer. + * If the RF core is powered, it triggs the HWI to execute the dispatcher. + * If the RF core is not powered, it decides if it should be powered ON immediately, or + * the execution can be deferred to a later timestamp. In the latter case, the RTC is used to keep + * track of proper timing. + * + * Input: none + * Return: status - Status of the command execution. + * + */ +static void RF_dispatchNextEvent(void) +{ + if (RF_core.status == RF_CoreStatusActive) + { + /* Kick the HWI to dispatch the next pending event. */ + HwiP_post(INT_RFC_CPE_0); + } + else if ((RF_core.status == RF_CoreStatusPoweringUp) || + (RF_core.status == RF_CoreStatusPhySwitching)) + { + /* Do nothing. We will dispatch the next event at the end + of power-up/phy-switching sequence naturally. */ + } + else + { + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Calculate dispatch time. */ + uint32_t dispatchTimeClockTicks; + bool validTime = RF_calculateDispatchTime(&dispatchTimeClockTicks); + + if (validTime) + { + /* Decide whether the command should be dispatched. */ + if (dispatchTimeClockTicks) + { + /* Dispatch command in the future. */ + RF_restartClockTimeout(&RF_clkPowerUpObj, dispatchTimeClockTicks); + } + else + { + /* Dispatch the event immediately. Clock is not needed anymore. */ + ClockP_stop(&RF_clkPowerUpObj); + + /* Initiate powering up the RF core. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventWakeup); + } + } + else + { + /* There is no event to be dispatched. */ + ClockP_stop(&RF_clkPowerUpObj); + } + + /* Exit critical section. */ + HwiP_restore(key); + } +} + +/* + * Update the cached FS command within the client's context. + * + * Calling context: Hwi, Swi + * + * Input: pCmd - Pointer to radio operation command. + * Return: none + */ +static void RF_cacheFsCmd(RF_Cmd* pCmd) +{ + /* Upper limit of the number of operations in a chain */ + uint8_t nCmdChainMax = RF_MAX_CHAIN_CMD_LEN; + + /* Traverse the chain */ + RF_Op* pOp = pCmd->pOp; + while (pOp && nCmdChainMax) + { + /* If the operation is a CMD_FS or CMD_FS_OFF */ + if ((pOp->commandNo == CMD_FS) || (pOp->commandNo == CMD_FS_OFF)) + { + /* Create a copy of the first CMD_FS command (or CMD_FS_OFF) for later power up */ + memcpy(&pCmd->pClient->state.mode_state.cmdFs, pOp, sizeof(pCmd->pClient->state.mode_state.cmdFs)); + break; + } + + /* Step the chain */ + pOp = pOp->pNextOp; + + /* Avoid infinit loop (in case of closed loops) */ + --nCmdChainMax; + } +} + +/* + * Find the last radio operation within a chain. + * + * Calling context: Task, Hwi, Swi + * + * Input: pOp - Pointer to the first radio operation. + * Return: RF_Op* - Pointer to the last radio operation. + */ +static RF_Op* RF_findEndOfChain(RF_Op* pOp) +{ + /* Upper limit of the number of operations in a chain. */ + uint8_t nCmdChainMax = RF_MAX_CHAIN_CMD_LEN; + + /* Traverse the chain. */ + while (pOp->pNextOp && nCmdChainMax) + { + /* Step the chain. */ + pOp = pOp->pNextOp; + + /* Avoid infinit loop (in case of closed loops). */ + --nCmdChainMax; + } + + /* Return with the last radio operation. */ + return(pOp); +} + +/* + * Verify if the given command is a setup command. + * + * Calling context: Hwi, Swi + * + * Input: pOp - Pointer to radio operation. + * Return: true - The given command is a setup command. + * false - The given command is not a setup command. + */ +static bool RF_isRadioSetup(RF_Op* pOp) +{ + /* Verify the command ID against the known setup commands. */ + switch(pOp->commandNo) + { + case (CMD_RADIO_SETUP): + case (CMD_BLE5_RADIO_SETUP): + case (CMD_PROP_RADIO_SETUP): + case (CMD_PROP_RADIO_DIV_SETUP): + /* The given radio operation is indead a setup command. */ + return(true); + default: + /* Do nothing. */ + return(false); + } +} + +/* + * Ensure that the setup command is properly initialized. + * + * Input: handle - Pointer to the client. + * Return: None + */ +static void RF_initRadioSetup(RF_Handle handle) +{ + /* Local variables. */ + uint16_t* pTxPower = NULL; + uint32_t* pRegOverride = NULL; + uint32_t* pRegOverrideTxStd = NULL; + uint32_t* pRegOverrideTx20 = NULL; + bool tx20FeatureAvailable = false; + bool update = handle->clientConfig.bUpdateSetup; + bool hposcAvailable = OSC_IsHPOSCEnabled(); + + /* Decode the setup command. */ + RF_RadioSetup* radioSetup = handle->clientConfig.pRadioSetup; + radioSetup->common.status = IDLE; + + /* Adjust the setup command if needed. */ + switch (radioSetup->common.commandNo) + { + case (CMD_RADIO_SETUP): + case (CMD_BLE5_RADIO_SETUP): + /* Configure that the frequency synthetizer should be powered up */ + radioSetup->common.config.bNoFsPowerUp = 0; + + /* If requested, also change the analog configuration during power up */ + if (update) + { + radioSetup->common.config.analogCfgMode = RF_SETUP_ANALOGCFG_UPDATE; + } + else + { + radioSetup->common.config.analogCfgMode = RF_SETUP_ANALOGCFG_NOUPDATE; + } + break; + + case (CMD_PROP_RADIO_SETUP): + case (CMD_PROP_RADIO_DIV_SETUP): + /* Configure that the frequency synthetizer should be powered ON */ + radioSetup->prop.config.bNoFsPowerUp = 0; + + /* If requested, also change the analog configuration during power up */ + if (update) + { + radioSetup->prop.config.analogCfgMode = RF_SETUP_ANALOGCFG_UPDATE; + } + else + { + radioSetup->prop.config.analogCfgMode = RF_SETUP_ANALOGCFG_NOUPDATE; + } + break; + default: + break; + } + + /* Clear the update request flag as it was handled by now. */ + handle->clientConfig.bUpdateSetup = false; + + /* Decode if High Gain PA is available. */ + tx20FeatureAvailable = RF_decodeOverridePointers(radioSetup, &pTxPower, &pRegOverride, &pRegOverrideTxStd, &pRegOverrideTx20); + + /* Ensure that overrides are in sync with the selected PA. */ + if (tx20FeatureAvailable && (*pTxPower == RF_TX20_ENABLED)) + { + /* Attach the High Gain overrides. It does nothing if the extra overrides are NULL. */ + RF_attachOverrides(pRegOverride, pRegOverrideTx20); + } + else + { + /* Detach the High Gain overrides. It does nothing if it is not present. */ + RF_detachOverrides(pRegOverride, pRegOverrideTx20); + } + + /* Compensate HPOSC drift if HPOSC functionality is enabled. */ + if(hposcAvailable==true) + { + RF_updateHpOscOverride(pRegOverride); + } +} + +/* + * Submit the pending command to the RF Core. + * + * Input: none + * Return: none + */ +static void RF_dispatchNextCmd(void) +{ + /* First element in the pend queue */ + bool doDispatchNow = false; + RF_Cmd* pNextCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + /* Decide whether to schedule the next command or not. */ + if (pNextCmd) + { + if (RF_cmdQ.pCurrCmdFg) + { + ; /* Do nothing. */ + } + else if (RF_cmdQ.pCurrCmdBg) + { + if ((RF_cmdQ.pCurrCmdBg->pClient == pNextCmd->pClient) + && (pNextCmd->flags & RF_CMD_FG_CMD_FLAG)) + { + /* Be sure that the background command is started within the RF core. + This is to avoid race condition. */ + while ((RF_cmdQ.pCurrCmdBg->pOp->status == IDLE) || + (RF_cmdQ.pCurrCmdBg->pOp->status == PENDING)); + + /* Try to execute the foreground command. */ + doDispatchNow = true; + } + else + { + /* The command which we calculated the remained timing upon. It is the + first command having an absolute start time, and can locate anywhere + in the queue. */ + RF_Cmd* pAbsCmd = NULL; + + /* Calculate the timestamp of the next command in the command queue. */ + uint32_t dispatchTimeClockTicks; + bool validTime = RF_cmdDispatchTime(&dispatchTimeClockTicks, true, &pAbsCmd); + + if (validTime) + { + /* There is a conflict identified with the running command. */ + if (dispatchTimeClockTicks == 0) + { + /* Invoke the registered hook to resolve the conflict. */ + if(RFCC26XX_schedulerPolicy.conflictHook) + { + /* Invoke the conflit hook to determine what action we shall take. */ + RF_Conflict conflict = + RFCC26XX_schedulerPolicy.conflictHook(RF_cmdQ.pCurrCmdBg, + RF_cmdQ.pCurrCmdFg, + &RF_cmdQ.pPend, + &RF_cmdQ.pDone); + + /* Handle the conflict. */ + if (conflict == RF_ConflictAbort) + { + RF_abortCmd(RF_cmdQ.pCurrCmdBg->pClient, RF_cmdQ.pCurrCmdBg->ch, false, true, true); + } + else if (conflict == RF_ConflictReject) + { + RF_abortCmd(pAbsCmd->pClient, pAbsCmd->ch, false, false, true); + } + } + } + else + { + /* The conflict is in the future, and might resolve naturarly. + Revisit the issue again before the execution should start. */ + RF_restartClockTimeout(&RF_clkPowerUpObj, dispatchTimeClockTicks); + } + } + } + } + else + { + /* The RF core is available, dispatch the next command. */ + doDispatchNow = true; + } + } + else + { + /* There is nothing to do, serve the last callbacks. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventLastCommandDone); + } + + /* We need to evaluate and handle the next command. */ + if (doDispatchNow) + { + if (pNextCmd->pClient != RF_currClient) + { + /* We need to change radio client, signal to FSM. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventInitChangePhy); + } + else + { + /* Calculate the timestamp of the next command in the command queue. */ + uint32_t dispatchTimeClockTicks; + bool validTime = RF_cmdDispatchTime(&dispatchTimeClockTicks, false, NULL); + + /* Dispatch command in the future */ + if (validTime && dispatchTimeClockTicks && !RF_cmdQ.pCurrCmdBg && !RF_cmdQ.pCurrCmdFg) + { + /* Command sufficiently far into future that it shouldn't be dispatched yet + Release RF power constraint and potentially power down radio */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + } + else + { + /* Set power constraint on the command queue, since there is now a running command. */ + RF_powerConstraintSet(RF_PowerConstraintCmdQ); + + /* Move the command from the pending queue to the current command. */ + if (pNextCmd->flags & RF_CMD_FG_CMD_FLAG) + { + RF_cmdQ.pCurrCmdFg = (RF_Cmd*)List_get(&RF_cmdQ.pPend); + } + else + { + RF_cmdQ.pCurrCmdBg = (RF_Cmd*)List_get(&RF_cmdQ.pPend); + } + + /* Clear and enable the requested interrupt sources of the command. */ + RFCCpeIntClear((uint32_t) (pNextCmd->bmEvent)); + RFCCpeIntEnable((uint32_t)(pNextCmd->bmEvent)); + RFCHwIntClear((uint32_t) (pNextCmd->bmEvent >> RF_SHIFT_32_BITS)); + RFCHwIntEnable((uint32_t) (pNextCmd->bmEvent >> RF_SHIFT_32_BITS)); + + /* Decode the radio operation itself. */ + RF_Op* pOp = (RF_Op*)pNextCmd->pOp; + + /* Send the radio operation to the RF core. */ + RFCDoorbellSendTo((uint32_t)pOp); + + /* If the command is a new setup command, notify the board file. */ + if (RF_isRadioSetup(pOp)) + { + /* Invoke the global callback if the setup command changed. This is needed to + adjust the front-end configuration according to the new PHY. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioSetup, (void*)pOp); + } + + /* Check the pending queue for any foreground command (IEEE 15.4 mode) */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventRunScheduler); + } + } + } +} + +/* + * Check if there was an error with the synth while running CMD_FS + * error callback is not issued in this function. + * + * Input: none + * Return: true - If there was an error. + * false - If there was no error. + */ +static bool RF_checkCmdFsError(void) +{ + /* Take the handle of the current client */ + RF_Handle pObj = RF_currClient; + + /* Find the FS command stored in the context of the client */ + RF_Op *tmp1 = (RF_Op*)&pObj->clientConfig.pRadioSetup->prop; + while (tmp1->pNextOp && tmp1->pNextOp != (RF_Op*)&pObj->state.mode_state.cmdFs) + { + tmp1 = tmp1->pNextOp; + } + + /* Evaluate if the FS command succeeded */ + if ((tmp1->condition.rule == COND_ALWAYS) && + (pObj->state.mode_state.cmdFs.status == ERROR_SYNTH_PROG)) + { + /* CMD_FS completed with error so return true */ + return(true); + } + else + { + /* There is no synth error so return false */ + return(false); + } +} + +/* + * RF HW ISR when radio is active. + * + * Input: a - Not used. + * Return: none + */ +static void RF_hwiHw(uintptr_t a) +{ + /* Prepare a direct command */ + RF_Cmd* pCmd = RF_cmdQ.pCurrCmdBg; + + /* Read and clear the interrupt flags */ + uint32_t rfchwifg = RFCHwIntGetAndClear(RF_HW_INT_CPE_MASK | RF_HW_INT_RAT_CH_MASK); + uint32_t rfchwien = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) & RF_HW_INT_CPE_MASK; + uint32_t rathwien = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) & RF_HW_INT_RAT_CH_MASK; + + if (rfchwifg & rfchwien) + { + /* Post SWI_FSM if MODEM_SOFT event occured and the interrupt was enabled */ + if (pCmd) + { + /* Store the command which callback need to be served */ + RF_cmdQ.pCurrCmdCb = pCmd; + + /* Decode the event numeber. */ + RF_EventMask events = ((RF_EventMask)(rfchwifg & rfchwien) << RF_SHIFT_32_BITS); + + /* Store the events within the context of the command for the callback. */ + RF_cmdStoreEvents(pCmd, events); + + /* Trig the state machine to handle this event */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventCpeInt); + } + } + + /* Post the SWI_HW if any RAT channel event occured */ + if (rfchwifg & rathwien) + { + /* Store the channel which cause the interrupt */ + RF_ratModule.pendingInt |= (rfchwifg & rathwien) >> RFC_DBELL_RFHWIFG_RATCH5_BITN; + + /* Post the swi to handle its callback */ + SwiP_or(&RF_swiHwObj, 0); + } +} + +/* + * Software interrupt handler which servers Radio Timer (RAT) related events. + * + * Input: a - Generic argument. Not used. + * b - Generic argument. Not used. + * Return: none + */ +static void RF_swiHw(uintptr_t a, uintptr_t b) +{ + /* Local variable */ + bool error = false; + + /* If the interrupt was trigged due to one of the RAT channels. */ + if (RF_ratModule.pendingInt) + { + /* Process lower channel first and allow multiple interrupt flags to be processed sequentially. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + if (RF_ratModule.pendingInt & (RF_RAT_INTERRUPT_BASE_INDEX << i)) + { + /* If there is also a bit indicating that the interrupt is due to an error. */ + if (RF_ratModule.pendingInt & (RF_RAT_ERROR_BASE_INDEX << i)) + { + error = true; + } + + /* Enter critical section. */ + uint32_t key= HwiP_disable(); + + /* Atomic read-modify-write instruction of the interrupt flags. + Knowing that this is the only place when such a flag can be cleared, it is safe to only guard this + operation. Additional flags (which have been raised in the meantime) will be reserved and served in the + next iteration. */ + RF_ratModule.pendingInt &= ~((RF_RAT_INTERRUPT_BASE_INDEX | RF_RAT_ERROR_BASE_INDEX) << i); + + /* Exit critical section. */ + HwiP_restore(key); + + /* Convert the channel index to a pointer of rat configuration. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* Serve the interrupt if it is from an active channel. This is to avoid decoding function + pointers from invalid containers due to fantom interrupts. */ + if (ratCh && ratCh->status) + { + /* Read the channel counter from the RAT timer. In capture mode this is the captured value, + in compare mode this is the compare timestamp.*/ + uint32_t compareCaptureValue = RF_ratGetChannelValue(ratCh->handle); + + /* Temporarily store the callback handler and the channel offset. + This is necessary in order to be able to free and reallocate the + same channel within the context of the callback itself. */ + RF_Handle ratClient = (RF_Handle) ratCh->pClient; + RF_RatHandle ratHandle = (RF_CmdHandle) ratCh->handle; + RF_RatCallback ratCallback = (RF_RatCallback) ratCh->pCb; + + /* Only free the channel if it is NOT in repeated capture mode, or an error occured. */ + if (error || !(ratCh->mode == RF_RatModeCapture) || !(ratCh->chCmd & RF_RAT_CAPTURE_REPEAT_MODE)) + { + /* Free RAT channel. If this is the last channel, it might delay with 1 LF edge to + calculate the next wake up event. */ + RF_ratFreeChannel(ratCh); + } + + /* Serve the user callback with Error or Compare/Capture Event. */ + if (error) + { + ratCallback(ratClient, ratHandle, RF_EventError, 0); + } + else + { + ratCallback(ratClient, ratHandle, RF_EventRatCh, compareCaptureValue); + } + } + + /* Only serve one channel at a time. */ + break; + } + } + } + + /* Repost the SWI again if multiple interrupt flags are still set. */ + if (RF_ratModule.pendingInt) + { + SwiP_or(&RF_swiHwObj, 0); + } +} + +/* + * RF CPE0 ISR when radio is active. Assume that all IRQs relevant to command + * dispatcher are mapped here. Furthermore, assume that there is no need for + * critical sections here (i.e. that this ISR has higher priority than + * any HWI calling a RF API function or that HWIs can't call the RF API). + * + * Input: a - Not used. + * Return: none + */ +static void RF_hwiCpe0Active(uintptr_t a) +{ + /* Local variables. */ + RF_Cmd* volatile* ppActiveCmd = NULL; + RF_Cmd* volatile* activeCmd[2] = {&RF_cmdQ.pCurrCmdBg, &RF_cmdQ.pCurrCmdFg}; + uint32_t rfcpeifgMask = 0; + uint32_t rfcpeifg = 0; + uint32_t nextEvent = 0; + + /* Handle PA switching. */ + if (RFCCpeIntGetAndClear(RF_EventPaChanged)) + { + /* The PA was changed during a chain of radio operation. We need to extract the current configuration + and propagate it back to the setup command. This is to reserve the change after power cycle. */ + RF_extractPaConfiguration(RF_currClient); + + /* Invoke the board file to reconfigure the external front-end configuration. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioSetup, (void*) RF_currClient->clientConfig.pRadioSetup); + } + + /* Iterate through the possible active commands. */ + uint32_t i; + for(i = 0; i < sizeof(activeCmd)/sizeof(uint32_t); i++) + { + /* Decode the active command. */ + ppActiveCmd = activeCmd[i]; + + /* If there was a command running (handles both foreground and background context). */ + if (*ppActiveCmd) + { + /* Decode the events the active command subscribed to. */ + rfcpeifgMask = (*ppActiveCmd)->bmEvent; + + /* Read the interrupt flags which belong to the active command (including the mandatory termination events). */ + rfcpeifg = RFCCpeIntGetAndClear(rfcpeifgMask); + + /* Save the events happened and to be passed to the callback. */ + RF_cmdStoreEvents((*ppActiveCmd), rfcpeifg); + + /* Look for termination events. */ + if (rfcpeifg & (RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M | RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M)) + { + /* Disable interrupt sources which were subsribed by the command. Since the LAST_CMD_DONE is + is shared with the state machine, it cannot be disabled. */ + RFCCpeIntDisable((uint32_t)((*ppActiveCmd)->bmEvent & ~(RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M | RFC_DBELL_RFCPEIEN_IRQ14_M))); + RFCHwIntDisable((uint32_t) ((*ppActiveCmd)->bmEvent >> RF_SHIFT_32_BITS)); + + /* Move active command to done queue. */ + List_put(&RF_cmdQ.pDone, (List_Elem*)(*ppActiveCmd)); + + /* Retire the command, it is not running anymore. */ + (*ppActiveCmd) = NULL; + + /* We will invoke the callback and deallocate the command. */ + nextEvent |= RF_FsmEventLastCommandDone; + } + else if (rfcpeifg) + { + /* The interrupt is just an ordinary event without termination. */ + RF_cmdQ.pCurrCmdCb = (*ppActiveCmd); + + /* We will just invoke the callback. */ + nextEvent |= RF_FsmEventCpeInt; + } + } + } + + /* Post SWI to handle registered callbacks if there is any. */ + if (nextEvent) + { + SwiP_or(&RF_swiFsmObj, nextEvent); + } + + /* Restart pending rat channels. */ + RF_ratRestartChannels(); + + /* Dispatch the next pending command if exists. */ + RF_dispatchNextCmd(); +} + +/* + * Clock callback due to inactivity timeout. + * + * Input: pObj - Not used. + * Return: none + */ +static void RF_clkInactivityCallback(uintptr_t a) +{ + /* If there are no pending commands in the queue */ + if (RF_cmdQ.nSeqPost == RF_cmdQ.nSeqDone) + { + /* Release the constraint on the command queue and if nothing prevents, power down the radio */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + } +} + +/* + * Clock callback due to request access timeout. + * + * Input: a - Not used. + * Return: none + */ +static void RF_clkReqAccess(uintptr_t a) +{ + RF_issueRadioFreeCb(RF_RADIOFREECB_REQACCESS_FLAG | + RF_RADIOFREECB_PREEMPT_FLAG | + RF_RADIOFREECB_CMDREJECT_FLAG); +} + +/* + * Callback used to post semaphore for runCmd() and pendCmd(). + * + * Input: h - Handle to the client. + * ch - Handle to the command which callback to be invoked. + * e - Events causing the function call. + * Return: none + */ +static void RF_syncCb(RF_Handle h, RF_CmdHandle ch, RF_EventMask e) +{ + /* Local variables */ + RF_Cmd* pCmd; + + /* If there is a user callback provided. */ + if (h->state.pCbSync) + { + /* Invoke the user callback with the events fired. */ + ((RF_Callback)h->state.pCbSync)(h, ch, e); + } + + /* Mask the possible causes of releasing the semaphore */ + RF_EventMask maskedEvents = (e & h->state.eventSync); + + /* Release the semaphore on any of the reasons: last command done, + subscribed event happened, last FG command is done in IEEE mode */ + if (maskedEvents) + { + /* Find the command. We do it here within the SWI context. */ + pCmd = RF_cmdGet(h, ch, RF_CMD_ALLOC_FLAG); + + /* Store the events in the context of the client */ + h->state.unpendCause = maskedEvents; + + /* Find the command. We do it here within the SWI context. */ + if (pCmd) + { + /* Clear the handled past events so it is possible to pend again */ + pCmd->pastifg &= ~h->state.unpendCause; + + /* Exhange the callback function: use the user callback from this point */ + pCmd->pCb = (RF_Callback)h->state.pCbSync; + } + + /* Clear temporary storage of user callback (it was restored and served at this point) */ + h->state.pCbSync = NULL; + + /* Post the semaphore to release the RF_pendCmd() */ + SemaphoreP_post(&h->state.semSync); + } +} + +/* + * Invoke the global callback registered through the RFCC26XX_hwAttrs. + * + * Input: e - Events causing the function call. + * Return: none + */ +static void RF_invokeGlobalCallback(RF_GlobalEvent event, void* arg) +{ + /* Decode the global callback and it's mask from the board file. */ + RF_GlobalCallback callback = RFCC26XX_hwAttrs.globalCallback; + RF_GlobalEventMask eventMask = RFCC26XX_hwAttrs.globalEventMask; + + /* If the board has subscribed to this event, invoke the callback. */ + if (callback && (eventMask & event)) + { + callback(RF_currClient, event, arg); + } +} + +/* + * Default callback function. + * + * Input: h - Handle to the client. + * ch - Handle to the command which callback to be invoked. + * e - Events causing the function call. + * Return: none + */ +static void RF_defaultCallback(RF_Handle h, RF_CmdHandle ch, RF_EventMask e) +{ + /* Do nothing */; +} + +/*-------------- RF powerup/powerdown FSM functions ---------------*/ + +/* + * The SWI handler for FSM events. + * + * Input: a0 - Not used. + * a1 - Not used. + * Return: none + */ +static void RF_swiFsm(uintptr_t a0, uintptr_t a1) +{ + RF_core.fxn(RF_currClient, (RF_FsmEvent)SwiP_getTrigger()); +} + +/* + * Clock callback called upon powerup. + * + * Input: a - Not used. + * Return: none + */ +static void RF_clkPowerUp(uintptr_t a) +{ + if (RF_core.fxn == RF_fsmActiveState) + { + /* Dispatch the next RF core event. */ + RF_dispatchNextEvent(); + } + else + { + /* Trigger FSM SWI to start the wake up sequence of the radio. + This is important when we poll the XOSC_HF. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventWakeup); + } +} + +/* + * RF CPE0 ISR during FSM powerup/powerdown. + * + * Input: a0 - Not used. + * Return: none + */ +static void RF_hwiCpe0PowerFsm(uintptr_t a0) +{ + /* Read all IRQ flags in doorbell and then clear them */ + uint32_t rfcpeifg = RFCCpeIntGetAndClear(RF_CPE0_INT_MASK); + + /* If the radio is active */ + if (RF_core.fxn == RF_fsmActiveState) + { + /* Change HWI handler to the correct one */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0Active, (uintptr_t)NULL); + + /* Mark radio and client as being active */ + RF_core.status = RF_CoreStatusActive; + + /* No synth error */ + if (!RF_checkCmdFsError()) + { + /* Restart pending rat channels. */ + RF_ratRestartChannels(); + + /* Dispatch the next command */ + RF_dispatchNextCmd(); + } + } + + /* Handle special events as boot, etc */ + if (rfcpeifg & (RFC_DBELL_RFCPEIFG_BOOT_DONE_M | RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M)) + { + SwiP_or(&RF_swiFsmObj, RF_FsmEventPowerStep); + } +} + +/* + * RF CPE0 ISR during Change PHY switching. + * + * Input: a0 - Not used. + * Return: none + */ +static void RF_hwiCpe0ChangePhy(uintptr_t a0) +{ + /* Clear all IRQ flags in doorbell and then clear them */ + uint32_t rfcpeifg = RFCCpeIntGetAndClear(RF_CPE0_INT_MASK); + + if (rfcpeifg & IRQ_LAST_COMMAND_DONE) + { + /* Proceed to the second phase of the phy switching process */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventFinishChangePhy); + } +} + +/*-------------- Power management state functions ---------------*/ +/* + * Handles RF Core patching for CPE, MCE, RFE (if required) in setup state during power-up. + * + * Input: mode - RF_PHY_BOOTUP_MODE: First boot of the RF core. + * - RF_PHY_SWITCHING_MODE: Switching between two phys. + * Return: none + */ +static void RF_applyRfCorePatch(bool mode) +{ + /* Local reference to the patches. */ + void (*cpePatchFxn)(void) = RF_currClient->clientConfig.pRfMode->cpePatchFxn; + void (*mcePatchFxn)(void) = RF_currClient->clientConfig.pRfMode->mcePatchFxn; + void (*rfePatchFxn)(void) = RF_currClient->clientConfig.pRfMode->rfePatchFxn; + + if (mode == RF_PHY_SWITCHING_MODE) + { + /* If patches are provided, enable RFE and MCE clocks. */ + if ((mcePatchFxn != NULL) || (rfePatchFxn != NULL)) + { + RF_dbellSubmitCmdAsync((uint32_t)CMDR_DIR_CMD_2BYTE(RF_CMD0, RFC_PWR_PWMCLKEN_MDMRAM | RFC_PWR_PWMCLKEN_RFERAM)); + } + + /* Clear the previous patch. */ + if (cpePatchFxn != NULL) + { + RFCCpePatchReset(); + } + } + + /* Load the patches if relevant for this phy. */ + if (cpePatchFxn != NULL) + { + if (mode == RF_PHY_BOOTUP_MODE) + { + cpePatchFxn(); + } + } + + if ((mcePatchFxn != NULL) || (rfePatchFxn != NULL)) + { + /* Wait for clocks to be turned ON */ + RF_dbellSyncOnAck(); + + /* Patch MCE if relevant */ + if (mcePatchFxn != NULL) + { + mcePatchFxn(); + } + + /* Patch RFE if relevant */ + if (rfePatchFxn != NULL) + { + rfePatchFxn(); + } + + /* Turn off additional clocks */ + RFCDoorbellSendTo(CMDR_DIR_CMD_2BYTE(RF_CMD0, 0)); + } +} + +/* + * Arms the inactivity timer and hence postpones the decision whether + * power management shall take place or not. + * + * Input: none + * Return: none + */ +static void RF_setInactivityTimeout(void) +{ + /* Local variables to be used to find the correct timeout value. */ + uint32_t inactivityTimeUsA = 0; + uint32_t inactivityTimeUsB = 0; + RF_Handle handleA = RF_Sch.clientHnd[0]; + RF_Handle handleB = RF_Sch.clientHnd[1]; + + /* Issue radio free callback after pre-emption if required */ + uint8_t tmp = RF_RADIOFREECB_PREEMPT_FLAG | RF_RADIOFREECB_CMDREJECT_FLAG; + + /* If the radio was yielded, add the flag */ + if (RF_currClient->state.bYielded) + { + tmp |= RF_RADIOFREECB_REQACCESS_FLAG; + } + + /* Call the radio free callback */ + RF_issueRadioFreeCb(tmp); + + if (handleA) + { + if (handleA->state.bYielded == false) + { + inactivityTimeUsA = handleA->clientConfig.nInactivityTimeout; + } + handleA->state.bYielded = false; + } + + if (handleB) + { + if (handleB->state.bYielded == false) + { + inactivityTimeUsB = handleB->clientConfig.nInactivityTimeout; + } + handleB->state.bYielded = false; + } + + /* Set the inactivity time to the max between the two clients */ + uint32_t inactivityTimeUs = MAX(inactivityTimeUsA, inactivityTimeUsB); + + /* If immediate power down is reuqested */ + if (inactivityTimeUs == SemaphoreP_NO_WAIT) + { + /* We can powerdown immediately */ + RF_clkInactivityCallback((uintptr_t)NULL); + } + else if (inactivityTimeUs != SemaphoreP_WAIT_FOREVER) + { + /* Reprogram and start inactivity timer */ + RF_restartClockTimeout(&RF_clkInactivityObj, inactivityTimeUs/ClockP_tickPeriod); + } +} + + +/* + * Handle callback to client for RF_EventLastCmdDone and issue radio free callback if required. + * + * Input: none + * Return: none + */ +static void RF_radioOpDoneCb(void) +{ + /* Serve the first entry in the done queue */ + RF_Cmd* pCmd = (RF_Cmd*)List_head(&RF_cmdQ.pDone); + + /* Radio command done */ + if (pCmd) + { + /* Update implicit radio state (chained FS command if any) */ + RF_cacheFsCmd(pCmd); + + /* Read and clear the events */ + RF_EventMask events = pCmd->rfifg; + pCmd->rfifg = 0; + + /* Issue callback, free container and dequeue */ + if (pCmd->pCb) + { + /* If any of the cancel events are set, mask out the other events. */ + RF_EventMask exclusiveEvents = (RF_EventCmdCancelled + | RF_EventCmdAborted + | RF_EventCmdStopped + | RF_EventCmdPreempted); + + /* Mask out the other events if any of the above is set. */ + if (events & exclusiveEvents) + { + events &= exclusiveEvents; + } + + /* Invoke the use callback */ + pCmd->pCb(pCmd->pClient, pCmd->ch, events); + } + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Update num of radio command done */ + RF_cmdQ.nSeqDone = (RF_cmdQ.nSeqDone+1) & N_CMD_MODMASK; + + /* Commmand completed reset command flags */ + pCmd->flags = 0; + + /* Invalidate the command handle. This is to avoid having duplicate + handles in the pool. */ + pCmd->ch = RF_SCHEDULE_CMD_ERROR; + + /* Command completed, free command queue container */ + List_get(&RF_cmdQ.pDone); + + /* Exit critical section */ + HwiP_restore(key); + + /* Check if there are any more pending commands */ + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + RF_setInactivityTimeout(); + } + } +} + +/* + * Verify if reconiguring or powering down the radio is allowed. + * + * Input: none + * Return: none + */ +static bool RF_isStateTransitionAllowed(void) +{ + /* Local variable. */ + bool status = false; + + /* If we are not performing RF core state changes. */ + if (RF_core.status == RF_CoreStatusActive) + { + if(RF_cmdQ.pCurrCmdBg == NULL && + RF_cmdQ.pCurrCmdFg == NULL) + { + status = true; + } + } + + /* Return with the decision. */ + return(status); +} + +/* + * RF state machine function during power up state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmPowerUpState(RF_Object *pObj, RF_FsmEvent e) +{ + /* Note: pObj is NULL in this state */ + if (e & RF_FsmEventLastCommandDone) + { + /* Invoke the user provided callback function */ + RF_radioOpDoneCb(); + + /* Retrig the SWI if there are more commands in the done queue. */ + if (List_head(&RF_cmdQ.pDone)) + { + /* Trigger self if there are more commands in callback queue */ + SwiP_or(&RF_swiFsmObj, (e | RF_FsmEventLastCommandDone)); + } + else + { + /* We've handled this event now */ + e &= ~RF_FsmEventLastCommandDone; + + /* Schedule the next event based on the state of the command queue + and the RAT module. */ + RF_dispatchNextEvent(); + } + } + else if (e & RF_FsmEventWakeup) + { + /* Notify the power driver that FLASH is needed in IDLE */ + bDisableFlashInIdleConstraint = true; + Power_setConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + + /* Store the current RTC tick for nPowerUpDuration calculation */ + RF_rtcTimestampA = AONRTCCurrent64BitValueGet(); + + /* Set current client from first command in command queue */ + RF_Cmd* pNextCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + if (pNextCmd) + { + RF_Object* pNextClient = pNextCmd->pClient; + + /* If the next command belongs to another client, initiate PHY switching */ + if ((RF_currClient) && (RF_currClient != pNextClient)) + { + /* Invoke the client switch callback if it was provided */ + if (pNextClient->clientConfig.nClientEventMask & RF_ClientEventSwitchClientEntered) + { + RF_ClientCallback pClientEventCb = (RF_ClientCallback)pNextClient->clientConfig.pClientEventCb; + pClientEventCb(pNextClient, RF_ClientEventSwitchClientEntered, NULL); + } + + /* Due to client switching, update the analogCfg field of setup command. */ + pNextClient->clientConfig.bUpdateSetup = true; + } + + /* Set the current client to be the next client */ + RF_currClient = pNextClient; + } + + /* Set the RF mode in the PRCM register (RF_open already verified that it is valid) */ + HWREG(PRCM_BASE + PRCM_O_RFCMODESEL) = RF_currClient->clientConfig.pRfMode->rfMode; + + /* Notiy the power driver that Standby is not allowed and RF core need to be powered */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + Power_setDependency(PowerCC26XX_DOMAIN_RFCORE); + + /* Indicate that the power-up sequence is being started */ + RF_core.status = RF_CoreStatusPoweringUp; + + /* If the configuration on board level requires to set the dependency every time. */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == false) + { + Power_setDependency(PowerCC26XX_XOSC_HF); + } + + /* If there are RFE and MCE patches, turn on their clocks */ + if ((RF_currClient->clientConfig.pRfMode->mcePatchFxn != NULL) || + (RF_currClient->clientConfig.pRfMode->rfePatchFxn != NULL)) + { + RF_dbellSubmitCmdAsync((uint32_t)CMDR_DIR_CMD_2BYTE(RF_CMD0, RFC_PWR_PWMCLKEN_MDMRAM | RFC_PWR_PWMCLKEN_RFERAM)); + } + + /* Turn on the clock to the RF core. Registers can be accessed afterwards. */ + RFCClockEnable(); + + /* Reconfigure the CPE interrupt lines to a start up value on a controlled way. */ + RFCCpeIntDisable(RF_CPE0_INT_MASK); + RFCCpe0IntSelect(RF_CPE0_INT_MASK); + + /* Enable some of the interrupt sources. */ + RFCCpeIntEnable(RFC_DBELL_RFCPEIEN_BOOT_DONE_M + | RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M + | RFC_DBELL_RFCPEIEN_IRQ14_M); + + /* Set the next state. */ + RF_core.fxn = RF_fsmSetupState; + + /* Enable interrupts: continue when boot is done */ + HwiP_enableInterrupt(INT_RFC_HW_COMB); + HwiP_enableInterrupt(INT_RFC_CPE_0); + } +} + +/* + * RF state machine function during setup state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmSetupState(RF_Object *pObj, RF_FsmEvent e) +{ + if (e & RF_FsmEventPowerStep) + { + /* Apply RF Core patches (if required) */ + RF_applyRfCorePatch(RF_PHY_BOOTUP_MODE); + + /* Initialize system bus request */ + RF_dbellSubmitCmdAsync((uint32_t)CMDR_DIR_CMD_1BYTE(CMD_BUS_REQUEST, 1)); + + /* Configure the RAT_SYNC command which will follow SETUP command */ + RF_ratSyncCmd.start.commandNo = CMD_SYNC_START_RAT; + RF_ratSyncCmd.start.status = IDLE; + RF_ratSyncCmd.start.startTrigger.triggerType = TRIG_NOW; + RF_ratSyncCmd.start.pNextOp = NULL; + RF_ratSyncCmd.start.condition.rule = COND_NEVER; + + /* Init the content of setup command. */ + RF_initRadioSetup(pObj); + + /* Configure the SETUP command. */ + RF_RadioSetup* pRadioSetup = pObj->clientConfig.pRadioSetup; + + /* Search for specific commands in the command chain. */ + RF_Op* tmp = (RF_Op*)&pRadioSetup->prop; + while ((tmp->pNextOp) && (tmp->pNextOp->commandNo != CMD_SYNC_START_RAT) && + (tmp->pNextOp->commandNo != CMD_FS) && + (tmp->pNextOp->commandNo != CMD_FS_OFF)) + { + /* Trace to the end of chain */ + tmp = tmp->pNextOp; + } + + /* Add the CMD_RAT_SYNC to the end of chain */ + tmp->pNextOp = (RF_Op*)&RF_ratSyncCmd.start; + tmp->condition.rule = COND_ALWAYS; + + /* Setup FS command to follow SETUP command */ + RF_Cmd* pCmdFirstPend = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + if (pCmdFirstPend && ((pCmdFirstPend->pOp->commandNo == CMD_FS) || (pCmdFirstPend->pOp->commandNo == CMD_FS_OFF))) + { + /* First command is FS command so no need to chain an implicit FS command -> Reset nRtc1 */ + RF_rtcTimestampA = 0; + } + else + { + if (pObj->state.mode_state.cmdFs.commandNo) + { + /* Chain in the implicit FS command */ + rfc_CMD_FS_t* pOpFs = &pObj->state.mode_state.cmdFs; + pOpFs->status = IDLE; + pOpFs->pNextOp = NULL; + pOpFs->startTrigger.triggerType = TRIG_NOW; + pOpFs->condition.rule = COND_NEVER; + RF_ratSyncCmd.start.pNextOp = (RF_Op*)pOpFs; + RF_ratSyncCmd.start.condition.rule = COND_ALWAYS; + } + } + + /* Make sure system bus request is done by now */ + RF_dbellSyncOnAck(); + + /* Set the next state. */ + RF_core.fxn = RF_fsmActiveState; + + /* Run the XOSC_HF switching if the pre-notify function setup the power + constraint PowerCC26XX_SWITCH_XOSC_HF_MANUALLY */ + if (RF_core.manualXoscHfSelect) + { + /* Wait until the XOSC_HF is stable */ + while (!PowerCC26XX_isStableXOSC_HF()); + + /* Invoke the XOSC_HF switching */ + PowerCC26XX_switchXOSC_HF(); + } + else if (OSCClockSourceGet(OSC_SRC_CLK_HF) != OSC_XOSC_HF) + { + /* If the XOSC_HF is not ready yet, only execute the first hal of the chain*/ + tmp->condition.rule = COND_NEVER; + + /* Next state: RF_fsmXOSCState (polling XOSC_HF)*/ + RF_core.fxn = RF_fsmXOSCState; + } + + /* Send the setup chain to the RF core */ + RF_dbellSubmitCmdAsync((uint32_t)pRadioSetup); + + /* Invoke the global callback. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioSetup, (void*)pRadioSetup); + } +} + +/* + * RF state machine function during XOSC state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmXOSCState(RF_Object *pObj, RF_FsmEvent e) +{ + if ((e & RF_FsmEventPowerStep) || (e & RF_FsmEventWakeup)) + { + /* If XOSC_HF is now ready */ + if (OSCClockSourceGet(OSC_SRC_CLK_HF) == OSC_XOSC_HF) + { + /* Next state: RF_fsmActiveState */ + RF_core.fxn = RF_fsmActiveState; + + /* Continue with the CMD_RAT_SYNC and the rest of the chain. */ + RF_dbellSubmitCmdAsync((uint32_t)&RF_ratSyncCmd.start); + } + else + { + /* Clock source not yet switched to XOSC_HF: schedule new polling */ + RF_restartClockTimeout(&RF_clkPowerUpObj, RF_XOSC_HF_SWITCH_CHECK_PERIOD_US/ClockP_tickPeriod); + } + } +} + +/* + * RF state machine function during active state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmActiveState(RF_Object *pObj, RF_FsmEvent e) +{ + volatile RF_Cmd* pCmd; + uint32_t rtcValTmp1; + uint32_t rtcValTmp2; + RF_EventMask events; + bool transitionAllowed; + uint32_t key; + + if (e & RF_FsmEventCpeInt) + { + /* Enter critical section */ + key = HwiP_disable(); + + /* Dereference the command which requested the callback*/ + pCmd = (RF_Cmd*)RF_cmdQ.pCurrCmdCb; + + /* If this is due to other event than LastCmdDone */ + if (pCmd && !(pCmd->rfifg & RF_TERMINATION_EVENT_MASK)) + { + /* Temporarily store the reason of callback */ + events = pCmd->rfifg; + + /* Clear the events which are handled here */ + pCmd->rfifg &= (~events); + + /* Exit critical section */ + HwiP_restore(key); + + /* Invoke the user callback if it is provided */ + if (pCmd->pCb && events) + { + pCmd->pCb(pCmd->pClient, pCmd->ch, events); + } + } + else + { + /* Exit critical section */ + HwiP_restore(key); + } + + /* We've handled this event now */ + e &= ~RF_FsmEventCpeInt; + } + /* Coming from powerup states */ + else if (e & RF_FsmEventPowerStep) + { + /* RF core boot process is now finished */ + HWREG(PRCM_BASE + PRCM_O_RFCBITS) |= RF_BOOT1; + + /* Release the constraint on the FLASH in IDLE */ + if (bDisableFlashInIdleConstraint) + { + Power_releaseConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + bDisableFlashInIdleConstraint = false; + } + + /* Enter critical section */ + key = HwiP_disable(); + + /* Update power up duration if coming from the clkPowerUpFxn. Skip the calcualtion + if coming from boot, since the LF clock is derived from RCOSC_HF without calibration. */ + if ((OSCClockSourceGet(OSC_SRC_CLK_LF) != OSC_RCOSC_HF) + && pObj->clientConfig.bMeasurePowerUpDuration + && RF_rtcTimestampA) + { + /* Temporary storage to be able to compare the new value to the old measurement */ + uint32_t prevPowerUpDuration = pObj->clientConfig.nPowerUpDuration; + + /* Take wake up timestamp and the current timestamp */ + rtcValTmp1 = (uint32_t) RF_rtcTimestampA; + rtcValTmp2 = (uint32_t) AONRTCCurrent64BitValueGet(); + + /* Calculate the difference of the timestamps and convert it to us units */ + pObj->clientConfig.nPowerUpDuration = UDIFF(rtcValTmp1, rtcValTmp2); + pObj->clientConfig.nPowerUpDuration >>= RF_RTC_CONV_TO_US_SHIFT; + + /* Low pass filter on power up durations less than in the previous cycle */ + if (prevPowerUpDuration > pObj->clientConfig.nPowerUpDuration) + { + /* Expect that the values are small and the calculation can be done in 32 bits */ + pObj->clientConfig.nPowerUpDuration = (prevPowerUpDuration + pObj->clientConfig.nPowerUpDuration)/2; + } + + /* Power up duration should be within certain upper and lower bounds */ + if ((pObj->clientConfig.nPowerUpDuration > RF_DEFAULT_POWER_UP_TIME) || + (pObj->clientConfig.nPowerUpDuration < RF_DEFAULT_MIN_POWER_UP_TIME)) + { + pObj->clientConfig.nPowerUpDuration = RF_DEFAULT_POWER_UP_TIME; + } + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Check the status of the CMD_FS, if it was sent (chained) to the setup command. + If it failed, return an error callback to the client. + The client can either resend the CMD_FS or ignore the error as per Errata on PG2.1 */ + if (RF_checkCmdFsError()) + { + /* Invoke the error callback: deault is do nothing */ + RF_Callback pErrCb = (RF_Callback)pObj->clientConfig.pErrCb; + pErrCb(pObj, RF_ERROR_CMDFS_SYNTH_PROG, RF_EventError); + + /* Check if there is pending command */ + if (List_head(&RF_cmdQ.pPend)) + { + /* Make sure the next pending command gets dispatched by issuing CPE0 IRQ */ + RF_dispatchNextEvent(); + } + else + { + /* No pending command */ + e |= RF_FsmEventLastCommandDone; + } + } + + /* Issue power up callback: the RF core is active */ + RF_Callback pPowerCb = (RF_Callback)pObj->clientConfig.pPowerCb; + pPowerCb(pObj, 0, RF_EventPowerUp); + + /* We've handled this event now */ + e &= ~RF_FsmEventPowerStep; + } + else if (e & RF_FsmEventLastCommandDone) + { + /* Issue radio operation done callback */ + RF_radioOpDoneCb(); + + /* Take the next command in the done queue if any left */ + if (List_empty(&RF_cmdQ.pDone)) + { + /* We've handled this event now */ + e &= ~RF_FsmEventLastCommandDone; + } + } + else if (e & RF_FsmEventInitChangePhy) + { + /* Enter critical section */ + key = HwiP_disable(); + + /* We only continue with phy switching if the RF core is still available. + This check is important since the queues might have changed in the meantime + of servicing the SWI. */ + transitionAllowed = RF_isStateTransitionAllowed(); + + /* Take the next command from the pend queue */ + RF_Cmd* pNextCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + if ((transitionAllowed == true) && (pNextCmd != NULL)) + { + /* Indicate that we are changing phy on the RF core. */ + RF_core.status = RF_CoreStatusPhySwitching; + + /* Change HWI handler while switching the phy */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0ChangePhy, (uintptr_t)NULL); + + /* Exit critical section */ + HwiP_restore(key); + + /* Stop inactivity clock of the current client if running */ + ClockP_stop(&RF_clkInactivityObj); + + /* Store the timestamp or measurement of the switching time */ + RF_rtcBeginSequence = AONRTCCurrent64BitValueGet(); + + /* Notify the power driver that FLASH is needed in IDLE */ + bDisableFlashInIdleConstraint = true; + Power_setConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + + /* Switch the current client to the commands client */ + RF_currClient = pNextCmd->pClient; + + /* Do client switch callback if provided */ + if (RF_currClient->clientConfig.nClientEventMask & RF_ClientEventSwitchClientEntered) + { + RF_ClientCallback pClientEventCb = (RF_ClientCallback)RF_currClient->clientConfig.pClientEventCb; + pClientEventCb(RF_currClient, RF_ClientEventSwitchClientEntered, NULL); + } + + /* Apply the new RF Core patch */ + RF_applyRfCorePatch(RF_PHY_SWITCHING_MODE); + + /* Ensure that the analog domain is updated. */ + RF_currClient->clientConfig.bUpdateSetup = true; + + /* Ensure that the overrides are correct. */ + RF_initRadioSetup(RF_currClient); + + /* Configure the SETUP command */ + RF_RadioSetup* pRadioSetup = RF_currClient->clientConfig.pRadioSetup; + + /* Walk the chain and search or specific commands */ + RF_Op* tmp = (RF_Op*)&pRadioSetup->prop; + while ((tmp->pNextOp) && (tmp->pNextOp->commandNo != CMD_SYNC_START_RAT) && + (tmp->pNextOp->commandNo != CMD_FS) && + (tmp->pNextOp->commandNo != CMD_FS_OFF)) + { + tmp = tmp->pNextOp; + } + + /* Clear any of the found specific command */ + tmp->pNextOp = NULL; + tmp->condition.rule = COND_NEVER; + + /* Setup FS command to follow SETUP command */ + RF_Op* pOpFirstPend = pNextCmd->pOp; + if ((pOpFirstPend->commandNo == CMD_FS) || (pOpFirstPend->commandNo == CMD_FS_OFF)) + { + /* First command is FS command so no need to chain an implicit FS command -> reset nRtc2 */ + RF_rtcBeginSequence = 0; + } + else + { + if (RF_currClient->state.mode_state.cmdFs.commandNo) + { + /* Chain in the implicit FS command */ + rfc_CMD_FS_t* pOpFs = &RF_currClient->state.mode_state.cmdFs; + pOpFs->status = IDLE; + pOpFs->pNextOp = NULL; + pOpFs->startTrigger.triggerType = TRIG_NOW; + pOpFs->condition.rule = COND_NEVER; + tmp->pNextOp = (RF_Op*)pOpFs; + tmp->condition.rule = COND_ALWAYS; + } + } + + /* Send the command chain */ + RF_dbellSubmitCmdAsync((uint32_t)pRadioSetup); + + /* Invoke the global callback. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioSetup, (void*)pRadioSetup); + } + else + { + /* Exit critical section */ + HwiP_restore(key); + } + + /* We've handled this event now */ + e &= ~RF_FsmEventInitChangePhy; + } + else if (e & RF_FsmEventFinishChangePhy) + { + /* Release the constraint on the FLASH in IDLE */ + if (bDisableFlashInIdleConstraint) + { + Power_releaseConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + bDisableFlashInIdleConstraint = false; + } + + /* Check the status of the CMD_FS, if it was sent (chained) to the setup command. + If it failed, invoke the error callback of the client. + The client can either resend the CMD_FS or ignore the error. */ + if (RF_checkCmdFsError()) + { + RF_Callback pErrCb = (RF_Callback)RF_currClient->clientConfig.pErrCb; + pErrCb(RF_currClient, RF_ERROR_CMDFS_SYNTH_PROG, RF_EventError); + } + + /* Only compute PHY switching time if rtcValTmp1 is not zero (was initialized) */ + if (RF_rtcBeginSequence) + { + /* Record the timestamp for switching time measurement. */ + rtcValTmp2 = (uint32_t) AONRTCCurrent64BitValueGet(); + + /* Calculate how long it took to reconfigure the radio to a new phy. */ + RF_currClient->clientConfig.nPhySwitchingDuration = UDIFF(RF_rtcBeginSequence, rtcValTmp2); + RF_currClient->clientConfig.nPhySwitchingDuration >>= RF_RTC_CONV_TO_US_SHIFT; + + /* Reset RF_rtcBeginSequence value at the end of phy switching sequence. */ + RF_rtcBeginSequence = 0; + } + + /* Change HWI handler */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0Active, (uintptr_t)NULL); + + /* Mark radio and client as being active */ + RF_core.status = RF_CoreStatusActive; + + /* Serve the callbacks if the queue was rearranged while PHY switching was performed. */ + if (List_head(&RF_cmdQ.pDone)) + { + SwiP_or(&RF_swiFsmObj, RF_FsmEventLastCommandDone); + } + + /* Run the scheduler again. */ + RF_dispatchNextEvent(); + + /* We have handled this event now */ + e &= ~RF_FsmEventFinishChangePhy; + } + else if (e & RF_FsmEventPowerDown) + { + /* Enter critical section. */ + key = HwiP_disable(); + + /* Verify if the decision has not been reverted in the meantime. */ + transitionAllowed = RF_isStateTransitionAllowed(); + + /* If possible, put the running RAT channels into pending state allowing to + power down the RF core. */ + if (transitionAllowed) + { + transitionAllowed = RF_ratReleaseChannels(); + } + + /* If there is nothing prevent us to power down, proceed. */ + if (transitionAllowed) + { + /* Indicate that the RF core is being powered down from now */ + RF_core.status = RF_CoreStatusPoweringDown; + + /* Stop inactivity timer. */ + ClockP_stop(&RF_clkInactivityObj); + + /* Exit ritical setion. */ + HwiP_restore(key); + + /* Execute power down sequence of the RF core */ + RF_corePowerDown(); + + /* Invoke the global callback. At this point the clock of RF core is OFF, but the + power domain is still powered (hence the doorbell signals are still active. + We do the callback here to save some power. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioPowerDown, NULL); + + /* Notify the power driver that Standby mode is allowed and the RF core can be powered down. */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + Power_releaseDependency(PowerCC26XX_DOMAIN_RFCORE); + + /* Closing all handles */ + if (!RF_numClients) + { + /* Release the semaphore to be sure no one is pending on it */ + SemaphoreP_post(&RF_currClient->state.semSync); + } + + /* If there is no specific client request or the XOSC, release the dependency */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == false) + { + Power_releaseDependency(PowerCC26XX_XOSC_HF); + } + + /* Release constraint of switching XOSC_HF from the RF driver itself */ + if (RF_core.manualXoscHfSelect) + { + RF_core.manualXoscHfSelect = false; + Power_releaseConstraint(PowerCC26XX_SWITCH_XOSC_HF_MANUALLY); + } + + /* Next state: RF_fsmPowerUpState */ + RF_core.fxn = RF_fsmPowerUpState; + + /* Indicate that the RF core is now powered down */ + RF_core.status = RF_CoreStatusIdle; + + /* Issue radio available callback if RF_yield was called with no + pending commands in the queue */ + uint8_t tmp = RF_RADIOFREECB_REQACCESS_FLAG; + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + tmp |= RF_RADIOFREECB_PREEMPT_FLAG | RF_RADIOFREECB_CMDREJECT_FLAG; + } + RF_issueRadioFreeCb(tmp); + } + else + { + /* Exit ritical setion. */ + HwiP_restore(key); + } + + /* Reschedule the next event based on the state of the command queue + and the RAT module. We do it here as future commands need to work even if + power management is disabled manually. */ + RF_dispatchNextEvent(); + + /* We've handled this event now */ + e &= ~RF_FsmEventPowerDown; + } + else if (e & RF_FsmEventRunScheduler) + { + /* Run the scheduler again. */ + RF_dispatchNextEvent(); + + /* We've handled this event now */ + e &= ~RF_FsmEventRunScheduler; + } + + /* Call self again if there are outstanding events to be processed */ + if (e) + { + /* Trig the SWI with the remained/unhandled events */ + SwiP_or(&RF_swiFsmObj, e); + } +} + +/*-------------- Initialization & helper functions ---------------*/ + +/* + * Initialize RF driver. + * + * Input: none + * Return: none + */ +static void RF_init(void) +{ + union { + HwiP_Params hp; + SwiP_Params sp; + } params; + + /* Power init */ + Power_init(); + + /* Enable output RTC clock for Radio Timer Synchronization */ + HWREG(AON_RTC_BASE + AON_RTC_O_CTL) |= AON_RTC_CTL_RTC_UPD_EN_M; + + /* Set the automatic bus request */ + HWREG(PRCM_BASE + PRCM_O_RFCBITS) = RF_BOOT0; + + /* Initialize SWI used by the RF driver. */ + SwiP_Params_init(¶ms.sp); + params.sp.priority = RFCC26XX_hwAttrs.swiPriority; + SwiP_construct(&RF_swiFsmObj, RF_swiFsm, ¶ms.sp); + SwiP_construct(&RF_swiHwObj, RF_swiHw, ¶ms.sp); + + /* Initialize HWI used by the RF driver. */ + HwiP_Params_init(¶ms.hp); + params.hp.priority = RFCC26XX_hwAttrs.hwiPriority; + HwiP_construct(&RF_hwiCpe0Obj, INT_RFC_CPE_0, RF_hwiCpe0PowerFsm, ¶ms.hp); + HwiP_construct(&RF_hwiHwObj, INT_RFC_HW_COMB, RF_hwiHw, ¶ms.hp); + + /* Initialize clock object used as power-up trigger */ + ClockP_construct(&RF_clkPowerUpObj, &RF_clkPowerUp, 0, NULL); + ClockP_construct(&RF_clkInactivityObj, &RF_clkInactivityCallback, 0, NULL); + + /* Subscribe to wakeup notification from the Power driver */ + Power_registerNotify(&RF_wakeupNotifyObj, /* Object to register */ + PowerCC26XX_AWAKE_STANDBY, /* Event the notification to be invoked upon */ + (Power_NotifyFxn) RF_wakeupNotification, /* Function to be invoked */ + (uintptr_t) NULL); /* Parameters */ + + /* Set the XOSC_HF dependency if the HW attributes say so. This will ensure + that the XOSC_HF is turned on by the power driver as soon as possible when + coming out of standby. */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == true) + { + Power_setDependency(PowerCC26XX_XOSC_HF); + } + + /* Initialized the queues. */ + List_clearList(&RF_cmdQ.pDone); + List_clearList(&RF_cmdQ.pPend); + + /* Initialize global variables */ + RF_core.status = RF_CoreStatusIdle; + RF_core.init = false; + RF_core.activeTimeUs = 0; + RF_core.manualXoscHfSelect = false; + RF_ratModule.availableRatChannels = RF_DEFAULT_AVAILRATCH_VAL; + RF_rtcTimestampA = 0; + RF_rtcBeginSequence = 0; + RF_errTolValInUs = RF_DEFAULT_RAT_RTC_ERR_TOL_IN_US; + RF_powerConstraint = 0; + + /* Set FSM state to power up */ + RF_core.fxn = RF_fsmPowerUpState; +} + +/* + * Trace through the pending queue and flush the command(s). + * + * Input: h - Handle to the client calling this function. + * pCmd - Pointer to the command where the cancelling should start with. + * bFlushAll - Decides weather one or more commands should be aborted. + * Return: Number of commands was terminated. + */ +static uint32_t RF_discardPendCmd(RF_Handle h, RF_Cmd* pCmd, bool bFlushAll, bool bPreempt) +{ + /* Local variables, start from the head of queue. */ + uint32_t numDiscardedCmd = 0; + RF_Cmd* pElem = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + /* Find the first command to be cancelled. */ + while (pElem && (pElem != pCmd)) + { + pElem = (RF_Cmd*)List_next((List_Elem*)pElem); + } + + /* If we found the command to be cancelled. */ + while (pElem) + { + /* Temporarly store the next element, since we will need + to continue from there. */ + RF_Cmd* pNextElem = (RF_Cmd*)List_next((List_Elem*)pElem); + + if (RF_isClientOwner(h, pElem)) + { + /* Mark the command that it was cancelled. */ + RF_cmdStoreEvents(pElem, RF_EventCmdCancelled); + + if (bPreempt) + { + /* Mark the command as being preempted. */ + RF_cmdStoreEvents(pElem, RF_EventCmdPreempted); + + /* Subscribe the client for RadioFree callback. */ + RF_Sch.clientHndRadioFreeCb = pCmd->pClient; + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_PREEMPT_FLAG; + } + + /* Remove the command from the pend queue and place it to + the done queue. */ + List_remove(&RF_cmdQ.pPend, (List_Elem*)pElem); + List_put(&RF_cmdQ.pDone, (List_Elem*)pElem); + + /* Increment the counter of cancelled commands. */ + numDiscardedCmd += 1; + } + + /* Break the loop if only single cancel was requested. + Step the queue otherwise. */ + if (bFlushAll) + { + pElem = pNextElem; + } + else + { + break; + } + } + + /* Return with the number of cancelled commands. */ + return(numDiscardedCmd); +} + +/* + * Process cancel commands. It is used by RF_cancelCmd, RF_flushCmd API. + * + * Input: h - Handle to the client calling this function. + * ch - Handle to the command where the cancelling should start with. + * graceful - true: stop the command + * false: abort the command + * flush - true: flush all commands of this client + * false: only cancel the given command + * preempt - mark the command as the reason of aborting is preemption + * Return: status + */ +static RF_Stat RF_abortCmd(RF_Handle h, RF_CmdHandle ch, bool graceful, bool flush, bool preempt) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Initialize local variables */ + RF_Cmd* pCmd = NULL; + RF_Stat status = RF_StatInvalidParamsError; + RF_EventMask event = graceful ? RF_EventCmdStopped : RF_EventCmdAborted; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Handle FLUSH_ALL request */ + if (ch == RF_CMDHANDLE_FLUSH_ALL) + { + /* Start to cancel the commands from the actively running onces if it belongs to this client. */ + if (RF_isClientOwner(h, RF_cmdQ.pCurrCmdBg)) + { + pCmd = RF_cmdQ.pCurrCmdBg; + } + else if (RF_isClientOwner(h, RF_cmdQ.pCurrCmdFg)) + { + pCmd = RF_cmdQ.pCurrCmdFg; + } + else + { + /* Start to walk the pending queue from its head. */ + pCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + } + } + else + { + /* Search for the command in the command pool based on its handle. The command can + locate on any of the queues at this point. */ + pCmd = RF_cmdGet(h, ch, 0x00); + } + + /* If command handle is valid, proceed to cancel. */ + if (pCmd) + { + /* If the command is still allocated. */ + if (pCmd->flags & RF_CMD_ALLOC_FLAG) + { + /* If the command we want to cancel is actively running. */ + if ((pCmd == RF_cmdQ.pCurrCmdBg) || (pCmd == RF_cmdQ.pCurrCmdFg)) + { + /* Flag that the command has been aborted. In IEEE 15.4 mode, this means + aborting both the background and foreground commands. */ + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdBg, event); + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdFg, event); + + /* Decode what method to use to terminate the ongoing radio operation. */ + uint32_t directCmd = (graceful) ? CMDR_DIR_CMD(CMD_STOP) : CMDR_DIR_CMD(CMD_ABORT); + + /* Send the abort/stop command through the doorbell to the RF core. */ + RFCDoorbellSendTo(directCmd); + + if (preempt) + { + /* Mark the command as being preempted. */ + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdBg, RF_EventCmdPreempted); + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdFg, RF_EventCmdPreempted); + + /* Subscribe the client for RadioFree callback. */ + RF_Sch.clientHndRadioFreeCb = pCmd->pClient; + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_PREEMPT_FLAG; + } + + /* Remove all commands from the pend queue belong to this client. Only do it + if it was explicitely requested through the flush argument. */ + if (flush) + { + RF_discardPendCmd(h, (RF_Cmd*)List_head(&RF_cmdQ.pPend), flush, preempt); + } + + /* Return with success as we cancelled at least the currently running command. */ + status = RF_StatSuccess; + } + else + { + /* Remove one/all commands from the pend queue based on the flush argument. + If at least one command is cancelled the operation was succesful. Otherwise, + either the pend queue is empty or pCmd have terminated earlier */ + if (RF_discardPendCmd(h, pCmd, flush, preempt)) + { + /* Kick the state machine to handle the done queue and re-execute the scheduler. + This is not necessary when the RF is currently performing a power-up. */ + if ((RF_core.status != RF_CoreStatusPoweringUp) && + (RF_core.status != RF_CoreStatusPhySwitching)) + { + SwiP_or(&RF_swiFsmObj, (RF_FsmEventLastCommandDone | RF_FsmEventRunScheduler)); + } + + /* At least one command was cancelled. */ + status = RF_StatSuccess; + } + else + { + /* The command is not running and is not in the pend queue. It is located on the + done queue, hence return RF_StatCmdEnded. */ + status = RF_StatCmdEnded; + } + } + } + else + { /* If command is still in the pool but it is not allocated anymore, i.e. it was already served. */ + status = RF_StatCmdEnded; + } + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with the result: + - RF_StatSuccess if at least one command was cancelled. + - RF_StatCmdEnded, when the command already finished. + - RF_StatInvalidParamsError otherwise. */ + return(status); +} + +/* + * Execute a direct or immediate command in the RF Core if possible. + * + * Input: pCmd - Pointer to the command which shall be sent to the RF core. + * rawStatus - Return address of the raw status byte read from the CMDSTA register. + * Return: The return value interprets and converts the result of command execution to and RF_Stat value. + * RF_StatCmdDoneSuccess - If the command was sent and accepted by the RF core. + * RF_StatCmdDoneError - Command was rejected by the RF core. + * RF_StatRadioInactiveError - The RF core is OFF. + */ +static RF_Stat RF_executeDirectImmediateCmd(uint32_t pCmd, uint32_t* rawStatus) +{ + /* If the RF core is ON, we can send the command */ + if (RF_core.status == RF_CoreStatusActive) + { + /* Submit the command to the doorbell */ + uint32_t localStatus = RFCDoorbellSendTo(pCmd); + + /* Pass the rawStatus to the callee if possible. */ + if (rawStatus) + { + *rawStatus = localStatus; + } + + /* Check the return value of the RF core through the CMDSTA register within the doorbell */ + if ((localStatus & RF_CMDSTA_REG_VAL_MASK) == CMDSTA_Done) + { + /* The command was accepted */ + return(RF_StatCmdDoneSuccess); + } + else + { + /* The command was rejected */ + return(RF_StatCmdDoneError); + } + } + else + { + /* The RF core is not capable of receiving the command */ + return(RF_StatRadioInactiveError); + } +} + +/* + * Send a direct or immediate command to the RF core. The command is rejected + * if the RF core is configured to a different PHY (client). + * + * Input: h - Handle to the client calling this function. + * pCmd - Pointer to the command which shall be sent to the RF core. + * rawStatus - Return address of raw status byte read from CMDSTA register. + * Return: RF_StatCmdDoneSuccess - If the command was sent and accepted by the RF core. + * RF_StatCmdDoneError - Command was rejected by the RF core. + * RF_StatInvalidParamsError - Client do not have the right to send commands now. + * RF_StatRadioInactiveError - The RF core is OFF. + */ +static RF_Stat RF_runDirectImmediateCmd(RF_Handle h, uint32_t pCmd, uint32_t* rawStatus) +{ + /* Local variable. */ + RF_Stat status; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Only the current client is allowed to send direct commands */ + if (h != RF_currClient) + { + /* Return with an error code it is a different client */ + status = RF_StatInvalidParamsError; + } + else + { + /* Execute the direct or immediate command. */ + status = RF_executeDirectImmediateCmd(pCmd, rawStatus); + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with the status information about the success of command execution. */ + return(status); +} + +/* + * Helper function to find the first override representing a High PA value (CC13x2P devices). + * + * Input: pOverride - Pointer to an override list to be searched. + * overridePattern - Pattern o override to search for. + * currentValue - Reference where the current value can be returned. + * Return: paOffset - Offset of the High PA override. + * RF_TX_OVERRIDE_INVALID_OFFSET - No override was found in the list. + */ +static uint8_t RF_getPAOverrideOffsetAndValue(uint32_t* pOverride, uint32_t overridePattern, uint32_t* currentValue) +{ + /* Search for the particular override. */ + uint8_t paOffset = RFCOverrideSearch(pOverride, overridePattern, RF_TX_OVERRIDE_MASK, RF_OVERRIDE_SEARCH_DEPTH); + + /* If the override was found. */ + if (currentValue) + { + *currentValue = pOverride[paOffset] >> RF_TX_OVERRIDE_SHIFT; + } + + /* Return with an invalid value. */ + return(paOffset); +} + +/* + * Helper function to find and replace the first override representing a High PA value. + * + * Input: pOverride - Pointer to an override list to be searched. + * overridePattern - Mask of override type to searh for. + * newValue - The new raw value the PA to be set to. + * Return: paOffset - Offset of the High PA override. + * RF_TX_OVERRIDE_INVALID_OFFSET - No override was found in the list. Hence nothing to replace. + */ +static uint8_t RF_searchAndReplacePAOverride(uint32_t* pOverride, uint32_t overridePattern, uint32_t newValue) +{ + /* Search for the particular override. */ + uint8_t paOffset = RF_getPAOverrideOffsetAndValue(pOverride, overridePattern, NULL); + + /* If the override was found. */ + if (paOffset != RF_TX_OVERRIDE_INVALID_OFFSET) + { + if (overridePattern == RF_TX20_PATTERN) + { + /* Replace the high PA gain with the new value. */ + pOverride[paOffset] = TX20_POWER_OVERRIDE(newValue); + } + else + { + /* Replace the default PA gain with the new value. */ + pOverride[paOffset] = TX_STD_POWER_OVERRIDE(newValue); + } + } + + /* Return with the offset of the PA override. */ + return(paOffset); +} + +/* + * Appends the PA specific override list to the end of given overrides. + * + * Input: baseOverride - Override list to append the applicable segment to. + * newOverride - Override segment to be appended. + * Return: none + */ +static void RF_attachOverrides(uint32_t* baseOverride, uint32_t* newOverride) +{ + if (newOverride != NULL) + { + /* Search for the attached override list. */ + uint32_t maskOverride = NEW_OVERRIDE_SEGMENT(newOverride); + + /* Search for the end of the base override list. We also look for new segment vectors. */ + while ((*baseOverride != END_OVERRIDE) && (*baseOverride != maskOverride)) + { + baseOverride++; + } + + /* Append the second override list. */ + *baseOverride = maskOverride; + } +} + +/* + * Terminate the override list at the first match of a jump to the given newOverride. + * The function assumes that there are no other jump vectors before. + * + * Input: baseOverride - Override list to append the applicable segment to. + * newOverride - Override segment to be appended. + * Return: none + */ +static void RF_detachOverrides(uint32_t* baseOverride, uint32_t* newOverride) +{ + if (newOverride != NULL) + { + /* Search for the attached override list. */ + uint32_t maskOverride = NEW_OVERRIDE_SEGMENT(newOverride); + + /* Search for the end of the base override list. We also look for new segment vectors. */ + while ((*baseOverride != END_OVERRIDE) && (*baseOverride != maskOverride)) + { + baseOverride++; + } + + /* Append the second override list if exists. */ + *baseOverride = END_OVERRIDE; + } +} + +/* + * Decode all the override pointers according to the type of the setup command. + * + * Input: radioSetup - Pointer to the setup command to be evaluated. + * Return: tx20FeatureAvailable - true if the High Gain PA is available. + * pTxPower - Pointer to the txPower field of setup command. + * pRegOverride - Pointer to the base override list. + * pRegOverrideTxStd - Pointer to the Default PA override list. + * pRegOverrideTx20 - Pointer to the High PA override list. + */ +static bool RF_decodeOverridePointers(RF_RadioSetup* radioSetup, uint16_t** pTxPower, uint32_t** pRegOverride, uint32_t** pRegOverrideTxStd, uint32_t** pRegOverrideTx20) +{ + /* Decode if High Gain PA is even available. */ + bool tx20FeatureAvailable = (ChipInfo_GetChipType() == CHIP_TYPE_CC1352P); + + /* Only decode the offset of those fields which exist on this device. */ + if (tx20FeatureAvailable) + { + /* Local variables. */ + uint8_t loDivider; + uint8_t frontEndMode; + uint8_t index; + + /* Decode the offset of txPower field and all the override pointers + available on the CC1352P device. */ + switch (radioSetup->commandId.commandNo) + { + case (CMD_RADIO_SETUP): + *pTxPower = &radioSetup->common_pa.txPower; + *pRegOverride = radioSetup->common_pa.pRegOverride; + *pRegOverrideTxStd = radioSetup->common_pa.pRegOverrideTxStd; + *pRegOverrideTx20 = radioSetup->common_pa.pRegOverrideTx20; + + /* Input to recalculation of overrides. */ + loDivider = radioSetup->common_pa.loDivider; + frontEndMode = radioSetup->common_pa.config.frontEndMode; + + break; + case (CMD_BLE5_RADIO_SETUP): + *pTxPower = &radioSetup->ble5_pa.txPower; + *pRegOverride = radioSetup->ble5_pa.pRegOverrideCommon; + *pRegOverrideTxStd = radioSetup->ble5_pa.pRegOverrideTxStd; + *pRegOverrideTx20 = radioSetup->ble5_pa.pRegOverrideTx20; + + /* Input to recalculation of overrides. */ + loDivider = radioSetup->ble5_pa.loDivider; + frontEndMode = radioSetup->ble5_pa.config.frontEndMode; + + break; + case (CMD_PROP_RADIO_SETUP): + *pTxPower = &radioSetup->prop_pa.txPower; + *pRegOverride = radioSetup->prop_pa.pRegOverride; + *pRegOverrideTxStd = radioSetup->prop_pa.pRegOverrideTxStd; + *pRegOverrideTx20 = radioSetup->prop_pa.pRegOverrideTx20; + + /* Input to recalculation of overrides. */ + loDivider = 0; + frontEndMode = radioSetup->prop_pa.config.frontEndMode; + break; + default: + *pTxPower = &radioSetup->prop_div_pa.txPower; + *pRegOverride = radioSetup->prop_div_pa.pRegOverride; + *pRegOverrideTxStd = radioSetup->prop_div_pa.pRegOverrideTxStd; + *pRegOverrideTx20 = radioSetup->prop_div_pa.pRegOverrideTx20; + + /* Input to recalculation of overrides. */ + loDivider = radioSetup->prop_div_pa.loDivider; + frontEndMode = radioSetup->prop_div_pa.config.frontEndMode; + break; + } + + /* Modify the divider and front-end specific override. This is to keep the override + list and the setup command in sync, even if the setup command was changed runtime + due to the changing stack configuration. */ + if (*pRegOverrideTxStd) + { + index = RFCOverrideSearch(*pRegOverrideTxStd, RFC_FE_OVERRIDE_ADDRESS, RFC_FE_OVERRIDE_MASK, RFC_MAX_SEARCH_DEPTH); + + if (index < RFC_MAX_SEARCH_DEPTH) + { + (*pRegOverrideTxStd)[index] = RFCAnaDivTxOverride(loDivider, frontEndMode); + } + } + + if (*pRegOverrideTx20) + { + index = RFCOverrideSearch(*pRegOverrideTx20, RFC_FE_OVERRIDE_ADDRESS, RFC_FE_OVERRIDE_MASK, RFC_MAX_SEARCH_DEPTH); + + if (index < RFC_MAX_SEARCH_DEPTH) + { + (*pRegOverrideTx20)[index] = RFCAnaDivTxOverride(loDivider, RFC_FE_MODE_ESCAPE_VALUE); + } + } + } + else + { + /* Decode the offset of txPower field and the only relevant override pointer + available on all other devices. */ + switch (radioSetup->commandId.commandNo) + { + case (CMD_RADIO_SETUP): + *pTxPower = &radioSetup->common.txPower; + *pRegOverride = radioSetup->common.pRegOverride; + break; + case (CMD_BLE5_RADIO_SETUP): + *pTxPower = &radioSetup->ble5.txPower; + *pRegOverride = radioSetup->ble5.pRegOverrideCommon; + break; + case (CMD_PROP_RADIO_SETUP): + *pTxPower = &radioSetup->prop.txPower; + *pRegOverride = radioSetup->prop.pRegOverride; + break; + default: + *pTxPower = &radioSetup->prop_div.txPower; + *pRegOverride = radioSetup->prop_div.pRegOverride; + break; + } + + /* Force the value of non-existing pointers to be NULL. */ + *pRegOverrideTxStd = NULL; + *pRegOverrideTx20 = NULL; + } + + /* Return if the High Gain PA feature is available or not. */ + return (tx20FeatureAvailable); +} + +/* + * In case the PA configuration changes during the execution of a chain, this function + * propagates the change back to the setup command. This is to reserve the change even + * after a power cycle + * + * Input: handle - Radio handle the change should be stored within + * Return: none + */ +static void RF_extractPaConfiguration(RF_Handle handle) +{ + /* Local variable to store the return value of function call. It is not used here. */ + RF_ConfigurePaCmd configurePaCmd; + + /* Retrieve the PA configuration from the RF core itself. */ + RF_TxPowerTable_Value value; + value.rawValue = RFCGetPaGain(); + value.paType = (RF_TxPowerTable_PAType) RFCGetPaType(); + + /* Update the setup command with the new settings. The change is now permanent + and will be kept even if the RF core is powered off. */ + RF_updatePaConfiguration(handle->clientConfig.pRadioSetup, value, &configurePaCmd); +} + +/* + * Helper function to find the HPOSC_OVERRIDE in provided override list and modify the HPOSC frequency offset. + * + * Input: pRegOverride - Pointer to override list. + * Return: None + */ +static void RF_updateHpOscOverride(uint32_t *pRegOverride) +{ + /* Local variables. */ + int32_t tempDegC; + int32_t relFreqOffset; + int16_t relFreqOffsetConverted; + + /* Find override for HPOSC frequency offset. */ + if (pRegOverride) + { + uint8_t index; + index = RFCOverrideSearch(pRegOverride, RF_HPOSC_OVERRIDE_PATTERN, RF_HPOSC_OVERRIDE_MASK, RF_OVERRIDE_SEARCH_DEPTH); + + if (index < RF_OVERRIDE_SEARCH_DEPTH) + { + /* Get temperature dependent HPOSC frequency offset */ + tempDegC = AONBatMonTemperatureGetDegC(); + relFreqOffset = OSC_HPOSCRelativeFrequencyOffsetGet(tempDegC); + relFreqOffsetConverted = OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(relFreqOffset); + + /* Update override with the HPOSC frequency offset */ + pRegOverride[index] = HPOSC_OVERRIDE(relFreqOffsetConverted); + + /* Adjust the RTC increment if the LF clock is derived from the HF clock of the HPOSC */ + if(OSC_IsHPOSCEnabledWithHfDerivedLfClock()) + { + OSC_HPOSCRtcCompensate(relFreqOffset); + } + } + } + else + { + /* Hange here if HPOSC_OVERRIDE override is not available. */ + while(1); + } +} + +/* + * Helper function to find and modify the PA selection and gain of the provided setup command. + * + * Input: radioSetup - Setup command belong to the client. + * newValue - The new value the PA to be set to. + * configurePaCmd - The immediate command to be used to apply the changes if the RF core is active. + * Return: RF_StatSuccess - The setup command was reconfigured. + * Otherwise - An error occured. + */ +static RF_Stat RF_updatePaConfiguration(RF_RadioSetup* radioSetup, RF_TxPowerTable_Value newValue, RF_ConfigurePaCmd* configurePaCmd) +{ + /* Set the default return value to indicate success. */ + RF_Stat status = RF_StatSuccess; + + /* Local variables. */ + uint16_t* pTxPower = NULL; + uint32_t* pRegOverride = NULL; + uint32_t* pRegOverrideTxStd = NULL; + uint32_t* pRegOverrideTx20 = NULL; + + /* Decode if High Gain PA is available. */ + bool tx20FeatureAvailable = RF_decodeOverridePointers(radioSetup, &pTxPower, &pRegOverride, &pRegOverrideTxStd, &pRegOverrideTx20); + + /* The new value requires the deault PA. */ + if (newValue.paType == RF_TxPowerTable_DefaultPA) + { + /* On CC1352P devices with the correct override lists. */ + if (tx20FeatureAvailable && pRegOverrideTxStd && pRegOverrideTx20) + { + /* Store the new value in the setup command. */ + *pTxPower = (uint16_t) newValue.rawValue; + + /* Ensure that the gain within the overrides are also updated. */ + RF_searchAndReplacePAOverride(pRegOverrideTxStd, RF_TXSTD_PATTERN, newValue.rawValue); + + /* Detach the High Gain overrides. It does nothing if the overrides are not attached. */ + RF_detachOverrides(pRegOverride, pRegOverrideTx20); + + /* Return with the immediate command in the argument. */ + configurePaCmd->changePa.commandNo = CMD_CHANGE_PA; + configurePaCmd->changePa.pRegOverride = pRegOverrideTxStd; + } + else if (tx20FeatureAvailable) + { + /* Limited backward compatibility on CC1352P devices without the + proper override lists. Only gain tuning on the Default PA is available. */ + if (*pTxPower != RF_TX20_ENABLED) + { + /* Store the new value in the setup command. */ + *pTxPower = (uint16_t) newValue.rawValue; + + /* Use the dedicated command to tune the gain */ + configurePaCmd->tuneTxPower.commandNo = CMD_SET_TX_POWER; + configurePaCmd->tuneTxPower.txPower = newValue.rawValue; + } + else + { + /* PA swithing is not allowed due to the missing overrides. */ + status = RF_StatInvalidParamsError; + } + } + else + { + /* On any other devices, just accept the new gain. */ + *pTxPower = (uint16_t) newValue.rawValue; + + /* Use the dedicated command to tune the gain. */ + configurePaCmd->tuneTxPower.commandNo = CMD_SET_TX_POWER; + configurePaCmd->tuneTxPower.txPower = newValue.rawValue; + } + } + else + { + /* On CC1352P devices with the correct override lists. */ + if (tx20FeatureAvailable && pRegOverrideTxStd && pRegOverrideTx20) + { + /* If the High Gain PA is available store the escape value in the setup + command and update the overrides. */ + *pTxPower = (uint16_t) RF_TX20_ENABLED; + + /* Change the gain to the new value. */ + RF_searchAndReplacePAOverride(pRegOverrideTx20, RF_TX20_PATTERN, newValue.rawValue); + + /* Attach the High Gain overrides. */ + RF_attachOverrides(pRegOverride, pRegOverrideTx20); + + /* Return with the command argument to be used. */ + configurePaCmd->changePa.commandNo = CMD_CHANGE_PA; + configurePaCmd->changePa.pRegOverride = pRegOverrideTx20; + } + else if (tx20FeatureAvailable) + { + /* Limited backward compatibility on CC1352P devices without the + proper override lists. Only gain tuning on the High PA is available + if the gain override is present within the base override list.*/ + if (RF_searchAndReplacePAOverride(pRegOverride, RF_TX20_PATTERN, newValue.rawValue) == RF_TX_OVERRIDE_INVALID_OFFSET) + { + /* Cannot use the high gain PA without a proper override list + that contains at least a placeholder gain entry. */ + status = RF_StatInvalidParamsError; + } + else + { + /* If updating the override list with the gain value was succesful, + set the escape value in the setup command. */ + *pTxPower = (uint16_t) RF_TX20_ENABLED; + + /* Use the dedicated command to tune the gain. */ + configurePaCmd->tuneTx20Power.commandNo = CMD_SET_TX20_POWER; + configurePaCmd->tuneTx20Power.tx20Power = newValue.rawValue; + } + } + else + { + /* Do not accept any high gain PA values on devices which do not support it. */ + status = RF_StatInvalidParamsError; + } + } + + /* Return with the status. */ + return(status); +} + +/*-------------- API functions ---------------*/ +/* + * ======== RF_open ======== + * Open an RF handle + */ +RF_Handle RF_open(RF_Object *pObj, RF_Mode* pRfMode, RF_RadioSetup* pRadioSetup, RF_Params *params) +{ + /* Assert */ + DebugP_assert(pObj != NULL); + + /* Read available RF modes from the PRCM register */ + uint32_t availableRfModes = HWREG(PRCM_BASE + PRCM_O_RFCMODEHWOPT); + + /* Verify that the provided configuration is supported by this device. + Reject any request which is not compliant. */ + if (pRfMode && pRadioSetup && (availableRfModes & (1 << pRfMode->rfMode))) + { + /* Trim the override list; The implementation of RFCOverrideUpdate is device specific */ + RFCOverrideUpdate((RF_Op*)pRadioSetup, NULL); + + /* Register the setup command to the client */ + pObj->clientConfig.pRadioSetup = pRadioSetup; + + /* Register the mode to the client */ + pObj->clientConfig.pRfMode = pRfMode; + } + else + { + /* Return with null if the device do not support the requested configuration */ + return(NULL); + } + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Check whether RF driver is accepting more clients */ + if (RF_numClients < N_MAX_CLIENTS) + { + /* Initialize shared objects on first client opening */ + if (RF_numClients == 0) RF_init(); + + /* Save the new RF_Handle */ + RF_Sch.clientHnd[RF_numClients++] = pObj; + + /* Exit critical section */ + HwiP_restore(key); + + /* Populate default RF parameters if not provided */ + RF_Params rfParams; + if (params == NULL) + { + RF_Params_init(&rfParams); + params = &rfParams; + } + + /* Initialize RF_Object configuration */ + pObj->clientConfig.nInactivityTimeout = params->nInactivityTimeout; + pObj->clientConfig.nPhySwitchingDuration = RF_DEFAULT_PHY_SWITCHING_TIME; + pObj->clientConfig.nClientEventMask = params->nClientEventMask; + pObj->clientConfig.nPowerUpDurationMargin = params->nPowerUpDurationMargin; + pObj->clientConfig.bUpdateSetup = true; + + /* Decide if automatic adjustment should be used. */ + if (params->nPowerUpDuration) + { + pObj->clientConfig.nPowerUpDuration = params->nPowerUpDuration; + pObj->clientConfig.bMeasurePowerUpDuration = false; + } + else + { + pObj->clientConfig.nPowerUpDuration = RF_DEFAULT_POWER_UP_TIME; + pObj->clientConfig.bMeasurePowerUpDuration = true; + } + + /* Set all the callbacks to the default (do nothing) callback */ + pObj->clientConfig.pErrCb = (void*) RF_defaultCallback; + pObj->clientConfig.pClientEventCb = (void*) RF_defaultCallback; + pObj->clientConfig.pPowerCb = (void*) RF_defaultCallback; + + /* If a user specified callback is provided, overwrite the default */ + if (params->pErrCb) + { + pObj->clientConfig.pErrCb = (void *)params->pErrCb; + } + if (params->pClientEventCb) + { + pObj->clientConfig.pClientEventCb = (void *)params->pClientEventCb; + } + if (params->pPowerCb) + { + pObj->clientConfig.pPowerCb = (void *)params->pPowerCb; + } + + /* Initialize client state & variables to zero */ + memset((void*)&pObj->state, 0, sizeof(pObj->state)); + + /* Initialize client specific semaphore object */ + SemaphoreP_constructBinary(&pObj->state.semSync, 0); + + /* Initialize client specific clock objects */ + ClockP_construct(&pObj->state.clkReqAccess, RF_clkReqAccess, 0, NULL); + + /* Return with the RF handle. */ + return(pObj); + } + else + { + /* Exit critical section */ + HwiP_restore(key); + + /* Return with null if no more clients are accepted */ + return(NULL); + } +} + +/* + * ======== RF_close ======== + * Close an RF handle + */ +void RF_close(RF_Handle h) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* If there is at least one active client */ + if (RF_numClients) + { + /* Wait for all issued commands to finish before freeing the resources */ + if (RF_cmdQ.nSeqPost != RF_cmdQ.nSeqDone) + { + /* There are commands which not even dispatched yet. */ + RF_Cmd* pCmd = RF_queueEnd(h, &RF_cmdQ.pPend); + + /* There is no pending commmand, determine if there are items on the + other queues. */ + if (!pCmd) + { + /* If the client is executing a command running. */ + if (RF_isClientOwner(h, RF_cmdQ.pCurrCmdBg)) + { + /* The currentlty running command is the last. */ + pCmd = RF_cmdQ.pCurrCmdBg; + } + else + { + /* All commands has been dispatched, some just need to be served. This also + can return with NULL if nothing to be done. */ + pCmd = RF_queueEnd(h, &RF_cmdQ.pDone); + } + } + + /* Pend until the running command terminates */ + if (pCmd) + { + RF_pendCmd(h, pCmd->ch, RF_TERMINATION_EVENT_MASK); + } + } + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Clear the RF_sch client handle */ + if (h == RF_Sch.clientHnd[0]) + { + RF_Sch.clientHnd[0] = NULL; + } + else + { + RF_Sch.clientHnd[1] = NULL; + } + + /* Check whether this is the last client */ + if (--RF_numClients == 0) + { + /* If this is the last client, set it to be the active client */ + RF_currClient = h; + + if (RF_core.status == RF_CoreStatusActive) + { + /* Release the constraint on the RF resources */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + + /* Exit critical section */ + HwiP_restore(key); + + /* Wait until the radio is powered down (outside critical section) */ + SemaphoreP_pend(&h->state.semSync, SemaphoreP_WAIT_FOREVER); + + /* Enter critical section */ + key = HwiP_disable(); + } + + /* Unregister shared RTOS objects initalized during RF_init by the first client */ + SwiP_destruct(&RF_swiFsmObj); + HwiP_destruct(&RF_hwiCpe0Obj); + SwiP_destruct(&RF_swiHwObj); + HwiP_destruct(&RF_hwiHwObj); + ClockP_destruct(&RF_clkPowerUpObj); + ClockP_destruct(&RF_clkInactivityObj); + + /* Unregister the wakeup notify callback */ + Power_unregisterNotify(&RF_wakeupNotifyObj); + + /* Release XOSC_HF dependency if it was set on board level. */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == true) + { + Power_releaseDependency(PowerCC26XX_XOSC_HF); + } + } + + /* If we're the current RF client, stop being it */ + if (RF_currClient == h) + { + RF_currClient = NULL; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Unregister client specific RTOS objects (these are not shared between clients) */ + SemaphoreP_destruct(&h->state.semSync); + ClockP_destruct(&h->state.clkReqAccess); + } +} + +/* + * ======== RF_getCurrentTime ======== + * Get current time in RAT ticks + */ +uint32_t RF_getCurrentTime(void) +{ + /* Local variable */ + uint64_t nCurrentTime = 0; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* If radio is active, read the RAT */ + if (RF_core.status == RF_CoreStatusActive) + { + /* Read the RAT timer through register access */ + nCurrentTime = RF_ratGetValue(); + + /* Exit critical section */ + HwiP_restore(key); + } + else + { + /* Exit critical section */ + HwiP_restore(key); + + /* The radio is inactive, read the RTC instead */ + nCurrentTime = AONRTCCurrent64BitValueGet(); + + /* Conservatively assume that we are just about to increment the RTC + Scale with the 4 MHz that the RAT is running + Add the RAT offset for RTC==0 */ + nCurrentTime += RF_RTC_TICK_INC; + nCurrentTime *= RF_SCALE_RTC_TO_4MHZ; + nCurrentTime += ((uint64_t)RF_ratSyncCmd.start.rat0) << RF_SHIFT_32_BITS; + nCurrentTime >>= RF_SHIFT_32_BITS; + } + + /* Return with the current value */ + return((uint32_t) nCurrentTime); +} + +/* + * ======== RF_postCmd ======== + * Post radio command + */ +RF_CmdHandle RF_postCmd(RF_Handle h, RF_Op* pOp, RF_Priority ePri, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + DebugP_assert(pOp != NULL); + + /* Local pointer to a radio commands */ + RF_CmdHandle cmdHandle = (RF_CmdHandle)RF_ALLOC_ERROR; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Try to allocate container */ + RF_Cmd* pCmd = RF_cmdAlloc(); + + /* If allocation failed */ + if (pCmd) + { + /* Stop inactivity clock if running */ + ClockP_stop(&RF_clkInactivityObj); + + /* Increment the sequence number and mask the value */ + RF_cmdQ.nSeqPost = (RF_cmdQ.nSeqPost + 1) & N_CMD_MODMASK; + + /* Populate container with reset values */ + pCmd->pOp = pOp; + pCmd->ePri = ePri; + pCmd->pCb = pCb; + pCmd->ch = RF_cmdQ.nSeqPost; + pCmd->pClient = h; + pCmd->bmEvent = (bmEvent | RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M) & ~RF_INTERNAL_IFG_MASK; + pCmd->pastifg = 0; + pCmd->flags = RF_CMD_ALLOC_FLAG; + + /* Cancel ongoing yielding */ + h->state.bYielded = false; + + /* Submit to pending command to the queue. */ + List_put(&RF_cmdQ.pPend, (List_Elem*)pCmd); + + /* Trigger dispatcher if the timings need to be reconsidered. */ + if (List_head(&RF_cmdQ.pPend) == (List_Elem*)pCmd) + { + RF_dispatchNextEvent(); + } + + /* Return with the command handle as success */ + cmdHandle = pCmd->ch; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with an error code */ + return(cmdHandle); +} + +/* + * ==================== RF_ScheduleCmdParams_init ============================ + * Initialize the parameter structure to be used with RF_scheduleCmd(). + */ +void RF_ScheduleCmdParams_init(RF_ScheduleCmdParams *pSchParams) +{ + /* Assert */ + DebugP_assert(pSchParams != NULL); + + /* Set the configuration to use the default values. */ + pSchParams->priority = RF_PriorityNormal; + pSchParams->endTime = 0; + pSchParams->allowDelay = RF_AllowDelayAny; +} + +/* + * ==================== RF_scheduleCmd ============================ + * Process request to schedule new command from a particular client + */ +RF_CmdHandle RF_scheduleCmd(RF_Handle h, RF_Op* pOp, RF_ScheduleCmdParams *pSchParams, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Local variable declaration. */ + RF_Cmd* pCmd; + RF_Handle h2; + RF_ScheduleStatus status; + + /* Assert. */ + DebugP_assert(h != NULL); + DebugP_assert(pOp != NULL); + + /* Local pointer to a radio commands. */ + RF_CmdHandle cmdHandle = (RF_CmdHandle)RF_ALLOC_ERROR; + + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Assign h2 to client that is not issuing the new command. + The client h is issuing the new command. */ + if (h == RF_Sch.clientHnd[0]) + { + h2 = RF_Sch.clientHnd[1]; + } + else + { + h2 = RF_Sch.clientHnd[0]; + } + + /* If client h2 already has, reject any new commands from h. */ + if (h2 && (ClockP_isActive(&h2->state.clkReqAccess))) + { + /* Set the status value to schedule_error if we could not allocate space. */ + cmdHandle = (RF_CmdHandle) RF_ScheduleStatusError; + + /* Store the reason and the handle why the callback is being invoked. */ + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_CMDREJECT_FLAG; + RF_Sch.clientHndRadioFreeCb = h; + } + else + { + /* Check if command queue has free entries and allocate RF_Op* container + if command queue is full reject the command. */ + pCmd = RF_cmdAlloc(); + + /* If allocation was successful. */ + if (pCmd) + { + /* Stop inactivity clock if running. */ + ClockP_stop(&RF_clkInactivityObj); + + /* Increment the sequence number and mask the value. */ + RF_cmdQ.nSeqPost = (RF_cmdQ.nSeqPost + 1) & N_CMD_MODMASK; + + /* Cache meta-data. */ + pCmd->pOp = pOp; + pCmd->ePri = pSchParams->priority; + pCmd->pCb = pCb; + pCmd->ch = RF_cmdQ.nSeqPost; + pCmd->pClient = h; + pCmd->bmEvent = bmEvent & ~RF_INTERNAL_IFG_MASK; + pCmd->flags = 0; + pCmd->pastifg = 0; + pCmd->endTime = RF_SCH_CMD_ENDTIME_IGNORE; + pCmd->startTime = RF_SCH_CMD_STARTTIME_NOW; + pCmd->allowDelay = pSchParams->allowDelay; + + /* Update the default endTime based on the scheduling parameters. */ + if (pSchParams->endTime) + { + pCmd->endTime = pSchParams->endTime; + } + + /* Update the default startTime based on the command parameters. */ + if (pOp->startTrigger.triggerType == TRIG_ABSTIME) + { + pCmd->startTime = pOp->startTime; + } + + /* Find the last radio operation within the chain. */ + RF_Op* pEndOfChain = RF_findEndOfChain(pOp); + + /* Mark the context of the command based on it's ID and subscribe it + to the expected termination event. */ + if ((pEndOfChain->commandNo & RF_IEEE_ID_MASK) == RF_IEEE_FG_CMD) + { + pCmd->flags |= RF_CMD_FG_CMD_FLAG; + pCmd->bmEvent |= RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M; + } + else + { + pCmd->bmEvent |= RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M; + } + + /* Cancel the radio free callback if new command is from the same client. */ + if ((RF_Sch.clientHndRadioFreeCb == h) && + (RF_Sch.issueRadioFreeCbFlags & RF_RADIOFREECB_PREEMPT_FLAG)) + { + RF_Sch.issueRadioFreeCbFlags &= ~RF_RADIOFREECB_PREEMPT_FLAG; + } + + /* Invoke the submit policy which shall identify where exactly the new command is being + inserted based on the application level prioritization table. */ + if (RFCC26XX_schedulerPolicy.submitHook == NULL) + { + status = RF_ScheduleStatusError; + } + else + { + /* Execute the scheduling logic and queue management. */ + status = RFCC26XX_schedulerPolicy.submitHook(pCmd, + RF_cmdQ.pCurrCmdBg, + RF_cmdQ.pCurrCmdFg, + &RF_cmdQ.pPend, + &RF_cmdQ.pDone); + + /* In case of rescheduling (re-entering the same command), the assigned handle will + not match and the counter need to be corrected. */ + if ((status != RF_ScheduleStatusError) && (RF_cmdQ.nSeqPost != pCmd->ch)) + { + /* Decrement the sequence number and mask the value. */ + RF_cmdQ.nSeqPost = (RF_cmdQ.nSeqPost - 1) & N_CMD_MODMASK; + } + } + + /* Command was rejected. Either there was no slot available, or the timing did not fit. */ + if ((status == RF_ALLOC_ERROR) || (status == RF_ScheduleStatusError)) + { + /* Decrement the sequence number and mask the value. */ + RF_cmdQ.nSeqPost = (RF_cmdQ.nSeqPost - 1) & N_CMD_MODMASK; + + /* Store the reason and the handle why the callback is being invoked. */ + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_CMDREJECT_FLAG; + RF_Sch.clientHndRadioFreeCb = h; + + /* Ensure that the error code reflects the reason of rejection. */ + cmdHandle = (RF_CmdHandle) status; + } + else + { + /* Command was inserted. Return with the valid handle. */ + cmdHandle = pCmd->ch; + + /* Mark the command as being allocated. */ + pCmd->flags |= RF_CMD_ALLOC_FLAG; + + /* Cancel previous yielding. */ + h->state.bYielded = false; + + /* Trigger dispatcher if the timings need to be reconsidered. */ + if (List_head(&RF_cmdQ.pPend) == (List_Elem*)pCmd) + { + RF_dispatchNextEvent(); + } + } + } + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with the command handle. */ + return(cmdHandle); +} + +/* + * ======== RF_pendCmd ======== + * Pend on radio command + */ +RF_EventMask RF_pendCmd(RF_Handle h, RF_CmdHandle ch, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* If the command handle is invalid (i.e. RF_ALLOC_ERROR) */ + if (ch < 0) + { + /* Return with zero means the command was rejected earlier */ + return(0); + } + + /* Enter critical section */ + uint32_t key = SwiP_disable(); + + /* Find the command based on its handle in the command pool */ + RF_Cmd* pCmd = RF_cmdGet(h, ch, RF_CMD_ALLOC_FLAG); + + /* If the command was already disposed */ + if (!pCmd || !(pCmd->flags & RF_CMD_ALLOC_FLAG)) + { + /* Exit critical section */ + SwiP_restore(key); + + /* Return with last command done event */ + return(RF_EventLastCmdDone); + } + + /* Expand the pend mask to accept RF_EventLastCmdDone and RF_EventLastFGCmdDone events even if it is not given explicitely */ + bmEvent = (bmEvent | RF_TERMINATION_EVENT_MASK); + + /* If the command is being executed, but the event we pending on has already happend (i.e. in a chain), + return the past events */ + if (pCmd->pastifg & bmEvent) + { + /* Exit critical section */ + SwiP_restore(key); + + /* Store the cause of returning */ + h->state.unpendCause = pCmd->pastifg & bmEvent; + + /* Clear the handled past events so it is possible to pend again */ + pCmd->pastifg &= ~h->state.unpendCause; + + /* Return with the events */ + return(h->state.unpendCause); + } + + /* Command has still not finished, override user callback with one that calls the user callback then posts to semaphore */ + if (pCmd->pCb != RF_syncCb) + { + /* Temporarily store the callback function */ + h->state.pCbSync = (void*)pCmd->pCb; + + /* Exhange the callback function: this will invoke the user callback and post to the semaphore if needed */ + pCmd->pCb = RF_syncCb; + } + + /* Store the event subscriptions in the clients context. This can only be one of the already enabled + interrupt sources by RF_postCmd (including RF_EventLastCmdDone) */ + h->state.eventSync = bmEvent; + + /* Exit critical section */ + SwiP_restore(key); + + /* Wait for semaphore */ + SemaphoreP_pend(&h->state.semSync, SemaphoreP_WAIT_FOREVER); + + /* Return the events that resulted in releasing the RF_pend() call */ + return(h->state.unpendCause); +} + +/* + * ======== RF_runCmd ======== + * Run to completion a posted command + */ +RF_EventMask RF_runCmd(RF_Handle h, RF_Op* pOp, RF_Priority ePri, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Post the requested command */ + RF_CmdHandle ch = RF_postCmd(h, pOp, ePri, pCb, bmEvent); + + /* If the command was accepted, pend until one of the special events occur */ + return(RF_pendCmd(h, ch, RF_TERMINATION_EVENT_MASK)); +} + +/* + * ======== RF_runScheduleCmd ======== + * Run to completion a scheduled command + */ +RF_EventMask RF_runScheduleCmd(RF_Handle h, RF_Op* pOp, RF_ScheduleCmdParams *pSchParams, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Post the requested command */ + RF_CmdHandle ch = RF_scheduleCmd(h, pOp, pSchParams, pCb, bmEvent); + + /* If the command was accepted, pend until one of the special events occur */ + return(RF_pendCmd(h, ch, RF_TERMINATION_EVENT_MASK)); +} + +/* + * ======== RF_yieldCmd ======== + * Release client access + */ +void RF_yield(RF_Handle h) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Request the synchronization of RTC and RAT at next power down. This is trigged + by ceiling the active time to the maximum value. */ + RF_core.activeTimeUs = UINT32_MAX; + + /* Stop ongoing request access and issue callback if the radio is off */ + ClockP_stop((&h->state.clkReqAccess)); + + /* If all commands are done */ + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + if ((RF_core.status != RF_CoreStatusActive) && RF_Sch.issueRadioFreeCbFlags) + { + /* Exit critical section. */ + HwiP_restore(key); + + /* Invoke the radio free callback provided by the user. */ + RF_issueRadioFreeCb(RF_RADIOFREECB_REQACCESS_FLAG | + RF_RADIOFREECB_PREEMPT_FLAG | + RF_RADIOFREECB_CMDREJECT_FLAG); + + /* Enter critical section. */ + key = HwiP_disable(); + } + } + + /* If the radioFreeCb did not post new commands. */ + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + /* All commands are done. Stop inactivity timer. */ + ClockP_stop(&RF_clkInactivityObj); + + /* Potentially power down the RF core. */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + } + else + { + /* There are still client commands that haven't finished. + Set flag to indicate immediate powerdown when last command is done. */ + h->state.bYielded = true; + } + + /* Exit critical section */ + HwiP_restore(key); +} + +/* + * ======== RF_cancelCmd ======== + * Cancel single radio command + */ +RF_Stat RF_cancelCmd(RF_Handle h, RF_CmdHandle ch, uint8_t mode) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Decode what method to be used for terminating the commands. */ + bool graceful = (bool)(mode & RF_ABORT_GRACEFULLY); + bool flush = (bool)(mode & RF_ABORT_FLUSH_ALL); + bool preempt = (bool)(mode & RF_ABORT_PREEMPTION); + + /* Invoke the aborting process with the input arguments on a single command */ + return(RF_abortCmd(h, ch, graceful, flush, preempt)); +} + +/* + * ======== RF_flushCmd ======== + * Cancel multiple radio commands from a client + */ +RF_Stat RF_flushCmd(RF_Handle h, RF_CmdHandle ch, uint8_t mode) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Decode what method to be used for terminating the commands. */ + bool graceful = (bool)(mode & RF_ABORT_GRACEFULLY); + bool flush = true; + bool preempt = (bool)(mode & RF_ABORT_PREEMPTION); + + /* Abort multiple radio commands implicitly */ + return(RF_abortCmd(h, ch, graceful, flush, preempt)); +} + +/* + * ======== RF_Params_init ======== + * Initialize the RF_params to default value + */ +void RF_Params_init(RF_Params *params) +{ + /* Assert */ + DebugP_assert(params != NULL); + + /* Assign default values for RF_params */ + *params = RF_defaultParams; +} + +/* + * ======== RF_runImmediateCmd ======== + * Run immediate command + */ +RF_Stat RF_runImmediateCmd(RF_Handle h, uint32_t* pCmd) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Submit the command to the RF core */ + return(RF_runDirectImmediateCmd(h, (uint32_t)pCmd, NULL)); +} + +/* + * ======== RF_runDirectCmd ======== + * Run direct command + */ +RF_Stat RF_runDirectCmd(RF_Handle h, uint32_t cmd) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Submit the command to the RF core */ + return(RF_runDirectImmediateCmd(h, cmd, NULL)); +} + +/* + * ======== RF_getRssi ======== + * Get RSSI value + */ +int8_t RF_getRssi(RF_Handle h) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Local variable. */ + uint32_t rawRssi; + + /* Read the RSSI value if possible. */ + RF_Stat status = RF_runDirectImmediateCmd(h, CMDR_DIR_CMD(CMD_GET_RSSI), &rawRssi); + + /* Decode the RSSI value if possible. */ + if (status == RF_StatCmdDoneSuccess) + { + return((int8_t)((rawRssi >> RF_SHIFT_16_BITS) & RF_CMDSTA_REG_VAL_MASK)); + } + else + { + return((int8_t)RF_GET_RSSI_ERROR_VAL); + } +} + +/* + * ======== RF_getInfo ======== + * Get RF driver info + */ +RF_Stat RF_getInfo(RF_Handle h, RF_InfoType type, RF_InfoVal *pValue) +{ + /* Local variables */ + int8_t i = 0; + RF_Cmd* pCmd; + RF_ScheduleMapElement *pScheduleMap; + + /* Prepare the default status value */ + RF_Stat status = RF_StatSuccess; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Serve the different flavor of requests */ + switch (type) + { + case RF_GET_CURR_CMD: + /* Get the handle of the currently running command. It can be conerted + to a pointer through the RF_getCmdOp() API. */ + if (RF_cmdQ.pCurrCmdBg) + { + pValue->ch = RF_cmdQ.pCurrCmdBg->ch; + } + else + { + status = RF_StatError; + } + break; + + case RF_GET_AVAIL_RAT_CH: + /* Get available user channels within the RAT timer. + These channels can be allocated and used by the application. */ + pValue->availRatCh = RF_ratModule.availableRatChannels; + break; + + case RF_GET_RADIO_STATE: + /* Get current radio state */ + pValue->bRadioState = (RF_core.status == RF_CoreStatusActive) ? true : false; + break; + + case RF_GET_CLIENT_LIST: + /* Copy the client pointer list ([0] -> client 1, [1] -> client 2) */ + pValue->pClientList[0] = RF_Sch.clientHnd[0]; + pValue->pClientList[1] = RF_Sch.clientHnd[1]; + break; + + case RF_GET_CLIENT_SWITCHING_TIME: + /* Copy the phy switching times to the RF_InfoVal structure */ + pValue->phySwitchingTimeInUs[0] = RF_Sch.clientHnd[0] ? RF_Sch.clientHnd[0]->clientConfig.nPhySwitchingDuration : 0; + pValue->phySwitchingTimeInUs[1] = RF_Sch.clientHnd[1] ? RF_Sch.clientHnd[1]->clientConfig.nPhySwitchingDuration : 0; + break; + + case RF_GET_SCHEDULE_MAP: + /* Get scheduler timing map. This can be used to determine the recent + time slots which are occupied by posted commands; and can help to + find out if a command can be inserted to the queue or not. In dual-mode + applications, this can help to sync the two protocol. */ + pScheduleMap = (RF_ScheduleMapElement *)pValue->pScheduleMap; + memset(pScheduleMap, 0, sizeof(RF_ScheduleMapElement) * RF_NUM_SCHEDULE_MAP_ENTRIES); + + for (i = 0; i < RF_NUM_SCHEDULE_ACCESS_ENTRIES; i++) + { + /* Copy access request info to schedule map */ + pScheduleMap[i].pClient = RF_Sch.clientHnd[i]; + pScheduleMap[i].priority = RF_Sch.accReq[i].priority; + uint32_t startTime = RF_Sch.accReq[i].startTime; + pScheduleMap[i].startTime = startTime; + pScheduleMap[i].endTime = startTime + RF_Sch.accReq[i].duration; + } + + /* Check if there is current command running */ + if (RF_cmdQ.pCurrCmdBg) + { + /* Copy current command info to schedule map */ + pScheduleMap[i].pClient = RF_cmdQ.pCurrCmdBg->pClient; + pScheduleMap[i].ch = RF_cmdQ.pCurrCmdBg->ch; + pScheduleMap[i].priority = RF_cmdQ.pCurrCmdBg->ePri; + pScheduleMap[i].startTime = RF_cmdQ.pCurrCmdBg->startTime; + pScheduleMap[i].endTime = RF_cmdQ.pCurrCmdBg->endTime; + } + + /* Increment the index to ensure a fixed location for the background command. */ + i++; + + /* Check if there is current command running */ + if (RF_cmdQ.pCurrCmdFg) + { + /* Copy current command info to schedule map */ + pScheduleMap[i].pClient = RF_cmdQ.pCurrCmdFg->pClient; + pScheduleMap[i].ch = RF_cmdQ.pCurrCmdFg->ch; + pScheduleMap[i].priority = RF_cmdQ.pCurrCmdFg->ePri; + pScheduleMap[i].startTime = RF_cmdQ.pCurrCmdFg->startTime; + pScheduleMap[i].endTime = RF_cmdQ.pCurrCmdFg->endTime; + } + + /* Increment the index to ensure a fixed location for the foreground command. */ + i++; + + /* Check pending commands */ + pCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + /* Loop until end of command queue or number of entries exceed */ + while (pCmd) + { + if (i < RF_NUM_SCHEDULE_MAP_ENTRIES) + { + /* Copy pending command info to schedule map */ + pScheduleMap[i].pClient = pCmd->pClient; + pScheduleMap[i].ch = pCmd->ch; + pScheduleMap[i].priority = pCmd->ePri; + pScheduleMap[i].startTime = pCmd->startTime; + pScheduleMap[i].endTime = pCmd->endTime; + i++; + } + else + { + /* Number of entries exceeded, get out of loop */ + break; + } + + /* Walk the queue. */ + pCmd = (RF_Cmd*)List_next((List_Elem*)pCmd); + } + break; + + default: + status = RF_StatInvalidParamsError; + break; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with a status code */ + return(status); +} + +/* + * ======== RF_getCmdOp ======== + * Get RF command + */ +RF_Op* RF_getCmdOp(RF_Handle h, RF_CmdHandle ch) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Find the command in the command pool based on its handle */ + RF_Cmd* pCmd = RF_cmdGet(h, ch, RF_CMD_ALLOC_FLAG); + + /* If the command is found */ + if (pCmd) + { + /* Return with the first operation in the command */ + return(pCmd->pOp); + } + else + { + /* Return with null in case of error */ + return(NULL); + } +} + +/* + * ======== RF_RatConfigCompare_init ======== + * Initialize RAT compare configuration + */ +void RF_RatConfigCompare_init(RF_RatConfigCompare* channelConfig) +{ + /* Assert */ + DebugP_assert(channelConfig != NULL); + + /* Set the values to default. */ + memset((void*)channelConfig, 0, sizeof(RF_RatConfigCompare)); + + /* Set the default allocation method to use any channel. */ + channelConfig->channel = RF_RatChannelAny; +} + +/* + * ======== RF_RatConfigCapture_init ======== + * Initialize RAT capture configuration + */ +void RF_RatConfigCapture_init(RF_RatConfigCapture* channelConfig) +{ + /* Assert */ + DebugP_assert(channelConfig != NULL); + + /* Set the values to default. */ + memset((void*)channelConfig, 0, sizeof(RF_RatConfigCapture)); + + /* Set the default allocation method to use any channel. */ + channelConfig->channel = RF_RatChannelAny; +} + +/* + * ======== RF_RatConfigOutput_init ======== + * Initialize RAT IO configuration + */ +void RF_RatConfigOutput_init(RF_RatConfigOutput* ioConfig) +{ + /* Assert */ + DebugP_assert(ioConfig != NULL); + + /* Set the values to default. */ + memset((void*)ioConfig, 0, sizeof(RF_RatConfigOutput)); +} + +/* + * ======== RF_ratCompare ======== + * Set RAT compare + */ +RF_RatHandle RF_ratCompare(RF_Handle rfHandle, RF_RatConfigCompare* channelConfig, RF_RatConfigOutput* ioConfig) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Configure the RAT channel into COMPARE mode. */ + return(RF_ratSetupChannel(rfHandle, RF_RatModeCompare, channelConfig->callback, channelConfig->channel, (void*) channelConfig, ioConfig)); +} + +/* + * ======== RF_ratCapture ======== + * Set RAT capture + */ +RF_RatHandle RF_ratCapture(RF_Handle rfHandle, RF_RatConfigCapture* channelConfig, RF_RatConfigOutput* ioConfig) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Configure the RAT channel into CAPTURE mode. */ + return(RF_ratSetupChannel(rfHandle, RF_RatModeCapture, channelConfig->callback, channelConfig->channel, (void*) channelConfig, ioConfig)); +} + +/* + * ======== RF_ratDisableChannel ======== + * Disable RAT channel + */ +RF_Stat RF_ratDisableChannel(RF_Handle h, RF_RatHandle ratHandle) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Default return value */ + RF_Stat status = RF_StatError; + + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Find the pointer to the RAT channel configuration. */ + RF_RatChannel* ratCh = RF_ratGetChannel(ratHandle); + + /* If the provided handler is valid. */ + if (ratCh && ratCh->status) + { + /* If the RF core is active, abort the RAT event. */ + if (RF_core.status == RF_CoreStatusActive) + { + /* Calculate the configuration field of command (the channel we disable). */ + uint16_t config = (uint16_t)(RF_RAT_CH_LOWEST + ratCh->handle) << RF_SHIFT_8_BITS; + + /* Disable the channel within the RF core. */ + status = RF_runDirectImmediateCmd(h, ((uint32_t)CMDR_DIR_CMD_2BYTE(CMD_DISABLE_RAT_CH, config)), NULL); + + /* Free the container for further use. We do it after the direct command to be sure it is not powered down. + This will implicitely schedule the next event and run the power management accordingly. */ + RF_ratFreeChannel(ratCh); + } + else + { + /* Set status to be successful. */ + status = RF_StatCmdDoneSuccess; + + /* Free the container for further use. If possible, power down the radio. */ + RF_ratFreeChannel(ratCh); + + /* Recalculate the next wakeup event if the radio was off. */ + RF_dispatchNextEvent(); + } + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with the status code */ + return(status); +} + +/* + * ======== RF_control ======== + * RF control + */ +RF_Stat RF_control(RF_Handle h, int8_t ctrl, void *args) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Prepare the return value for worst case scenario */ + RF_Stat status = RF_StatSuccess; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Serve the different requests */ + switch (ctrl) + { + case RF_CTRL_SET_INACTIVITY_TIMEOUT: + /* Update the inactivity timeout of the client. + This can be used if the value given at RF_open + need to be updated */ + h->clientConfig.nInactivityTimeout = *(uint32_t *)args; + break; + + case RF_CTRL_UPDATE_SETUP_CMD: + /* Enable a special boot process which can be controlled + through the config field of the radio setup command. + This will influence only the next power up sequence + and will be reset automatically afterwards. The special + power up process will require longer power up time, hence + the nPowerUpDuration need to be increased */ + h->clientConfig.bUpdateSetup = true; + h->clientConfig.nPowerUpDuration += RF_ANALOG_CFG_TIME_US; + break; + + case RF_CTRL_SET_POWERUP_DURATION_MARGIN: + /* Configure the margin which is added to the measured + nPowerUpDuration. This can ensure that the commands + are executed on time, depending on the load of the + cpu */ + h->clientConfig.nPowerUpDurationMargin = *(uint32_t *)args; + break; + + case RF_CTRL_SET_PHYSWITCHING_DURATION_MARGIN: + /* Configure the margin which is added to the measured + nPowerUpDuration. This can ensure that the commands + are executed on time, depending on the load of the + cpu */ + h->clientConfig.nPhySwitchingDurationMargin = *(uint32_t *)args; + break; + + case RF_CTRL_SET_RAT_RTC_ERR_TOL_VAL: + /* Configure the tolerance value which is used to determine + the period when the RAT need to be syncronized to the RTC + due to the frequency offset */ + RF_errTolValInUs = *(uint32_t*)args; + break; + + case RF_CTRL_SET_POWER_MGMT: + /* The RF drivers power management can be enabled/disabled by + directly setting the power constraints from the application. + It is important that the order of actions align. */ + if (*(uint32_t*)args == 0) + { + RF_powerConstraintSet(RF_PowerConstraintDisallow); + } + else if (*(uint32_t*)args == 1) + { + RF_powerConstraintRelease(RF_PowerConstraintDisallow); + } + else + { + status = RF_StatInvalidParamsError; + } + break; + + case RF_CTRL_SET_HWI_PRIORITY: + /* Changing priorities during run-time has constraints. + To not mess up with the RF driver, we require the RF + driver to be inactive. */ + if (RF_core.status || (List_head(&RF_cmdQ.pPend))) + { + status = RF_StatBusyError; + } + else + { + HwiP_setPriority(INT_RFC_CPE_0, *(uint32_t *)args); + HwiP_setPriority(INT_RFC_HW_COMB, *(uint32_t *)args); + } + break; + + case RF_CTRL_SET_SWI_PRIORITY: + /* Changing priorities during run-time has constraints. + To not mess up with the RF driver, we require the RF + driver to be inactive. */ + if (RF_core.status || (List_head(&RF_cmdQ.pPend))) + { + status = RF_StatBusyError; + } + else + { + SwiP_setPriority(&RF_swiFsmObj, *(uint32_t *)args); + SwiP_setPriority(&RF_swiHwObj, *(uint32_t *)args); + } + break; + + case RF_CTRL_SET_AVAILABLE_RAT_CHANNELS_MASK: + /* Mask the available RAT channels manually. This can be used when + a particular RAT channel is used through oridnary radio operations + instead of the dedicated RAT APIs. */ + RF_ratModule.availableRatChannels = *(uint8_t *)args; + break; + + default: + /* Request can not be served */ + status = RF_StatInvalidParamsError; + break; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with the status code */ + return(status); +} + +/* + * ======== RF_requestAccess ======== + * RF request access + */ +RF_Stat RF_requestAccess(RF_Handle h, RF_AccessParams *pParams) +{ + /* Assert. */ + DebugP_assert(h != NULL); + DebugP_assert(pParams != NULL); + + /* By default, the status is set to busy. */ + RF_Stat status = RF_StatBusyError; + + /* Convert the requested duration to us. */ + uint32_t durationInUs = RF_convertRatTicksToUs(pParams->duration); + + /* Check if the requested period is within the acceptable range. */ + if (durationInUs > RF_REQ_ACCESS_MAX_DUR_US) + { + /* Reject the request if not. */ + status = RF_StatInvalidParamsError; + } + + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Determine the ID of the requesting client. */ + uint8_t clientIdx = 0; + if (h == RF_Sch.clientHnd[1]) + { + clientIdx = 1; + } + + /* Get handle to the other client. */ + RF_Handle h2 = RF_Sch.clientHnd[clientIdx ^ 0x1]; + + /* Check if the radio is free and if request can be served. + If possible update the RF_Sch structure and start the timer (RTC) + for the request access duration, else, return RF_StatBusyError. */ + if (!(h && ClockP_isActive(&h->state.clkReqAccess)) && + !(h2 && ClockP_isActive(&h2->state.clkReqAccess))) + { + /* Update the scheduler. */ + RF_Sch.accReq[clientIdx].duration = pParams->duration; + RF_Sch.accReq[clientIdx].priority = pParams->priority; + + /* Start timeout of the request. */ + RF_restartClockTimeout(&h->state.clkReqAccess, durationInUs/ClockP_tickPeriod); + + /* Set status to success after the access was granted. */ + status = RF_StatSuccess; + } + else + { + /* In case the request can not be served, prepare for a notification + callback when the radio becomes available. */ + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_REQACCESS_FLAG; + RF_Sch.clientHndRadioFreeCb = h; + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return the status. */ + return(status); +} + +/* + * ======== RF_setTxPower ======== + * Set the TX power of the client + */ +RF_Stat RF_setTxPower(RF_Handle handle, RF_TxPowerTable_Value value) +{ + /* Local variable stores the return value. */ + RF_Stat status; + + /* Placeholder of the command to be used to update the PA configuration within the RF core immediately. */ + RF_ConfigurePaCmd configurePaCmd; + + /* Update the setup command to make the changes permanent. */ + status = RF_updatePaConfiguration(handle->clientConfig.pRadioSetup, value, &configurePaCmd); + + /* If we managed to decode and cache the changes in the setup command. */ + if (status == RF_StatSuccess) + { + /* Execute the necessary command to apply the changes. It only takes effect if the RF core + is active and we configure the current client. The IO configuration can be re-evaluated when + the RF core issues the PA_CHANGED interrupt. */ + RF_runDirectImmediateCmd(handle, (uint32_t)&configurePaCmd, NULL); + } + + /* Return with the status. */ + return(status); +} + +/* + * ======== RF_getTxPower ======== + * Get the current TX power value + */ +RF_TxPowerTable_Value RF_getTxPower(RF_Handle handle) +{ + /* Default return value. */ + RF_TxPowerTable_Value value = { .rawValue = RF_TxPowerTable_INVALID_VALUE, + .paType = RF_TxPowerTable_DefaultPA}; + + /* Local variables. */ + uint16_t* pTxPower = NULL; + uint32_t* pRegOverride = NULL; + uint32_t* pRegOverrideTxStd = NULL; + uint32_t* pRegOverrideTx20 = NULL; + + /* Decode if High Gain PA is available. */ + bool tx20FeatureAvailable = RF_decodeOverridePointers(handle->clientConfig.pRadioSetup, &pTxPower, &pRegOverride, &pRegOverrideTxStd, &pRegOverrideTx20); + + /* Continue the search for the poper value if the High PA is used. */ + if (*pTxPower == RF_TX20_ENABLED) + { + /* Local variable. */ + uint32_t rawValue; + + /* Returning the High Gain PA gain is only possible if the P device is in use. */ + if (tx20FeatureAvailable && pRegOverrideTxStd && pRegOverrideTx20) + { + if (RF_getPAOverrideOffsetAndValue(pRegOverrideTx20, RF_TX20_PATTERN, &rawValue) != RF_TX_OVERRIDE_INVALID_OFFSET) + { + /* Return the value found in the gain related list. */ + value.rawValue = rawValue; + value.paType = RF_TxPowerTable_HighPA; + } + } + else if (tx20FeatureAvailable) + { + if (RF_getPAOverrideOffsetAndValue(pRegOverride, RF_TX20_PATTERN, &rawValue) != RF_TX_OVERRIDE_INVALID_OFFSET) + { + /* As a backup option, parse the common list too. This is or backward compatibility + and new software shall not rely on this feature. */ + value.rawValue = rawValue; + value.paType = RF_TxPowerTable_HighPA; + } + } + } + else + { + /* The value in the .txPower field represents the output power.*/ + value.rawValue = *pTxPower; + } + + /* Return with the decoded value. */ + return(value); +} + +/* + * ======== RF_TxPowerTable_findPowerLevel ======== + * Retrieves a power level in dBm for a given power configuration value. + */ +int8_t RF_TxPowerTable_findPowerLevel(RF_TxPowerTable_Entry table[], RF_TxPowerTable_Value value) +{ + /* Iterate through the power table. We do not verify against nullptr. */ + uint32_t i; + for (i=0; (table[i].power != RF_TxPowerTable_INVALID_DBM) && + (table[i].value.rawValue != RF_TxPowerTable_INVALID_VALUE); i++) + { + if (((uint32_t)table[i].value.paType == (uint32_t)value.paType) && + ((uint32_t)table[i].value.rawValue == (uint32_t)value.rawValue)) + { + /* Break the loop on the first entry which satisfies + the lower-or-equal criterion toward the input argument. */ + break; + } + } + + /* Return with the power level in dBm or with the + termination value RF_TxPowerTable_INVALID_DBM. */ + return(table[i].power); +} + +/* + * ======== RF_TxPowerTable_findValue ======== + * Retrieves a power configuration value for a given power level in dBm. + */ +RF_TxPowerTable_Value RF_TxPowerTable_findValue(RF_TxPowerTable_Entry table[], int8_t powerLevel) +{ + /* Local variable stores an invalid value. */ + RF_TxPowerTable_Value invalidValue = { .rawValue = RF_TxPowerTable_INVALID_VALUE, + .paType = RF_TxPowerTable_DefaultPA }; + + /* Handle special input argument. */ + if (powerLevel == RF_TxPowerTable_MIN_DBM) + { + return(table[0].value); + } + else + { + /* Iterate through the power table. We do not verify against nullptr. */ + uint32_t i; + for (i=0; ((int8_t)table[i].power != (int8_t)RF_TxPowerTable_INVALID_DBM) && + ((uint32_t)table[i].value.rawValue != (uint32_t)RF_TxPowerTable_INVALID_VALUE); i++) + { + if (table[i].power > powerLevel) + { + /* Break the loop on the first entry which satisfies + the lower-or-equal criterion toward the input argument. */ + break; + } + } + + if (i == 0) + { + /* If the first entry is already larger, then the requested + power level is invalid. */ + return(invalidValue); + } + else + { + /* Return with a valid RF_TxPowerTable_Value or with the + maximum value in the table. */ + return(table[i-1].value); + } + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RFCC26XX_multiMode.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RFCC26XX_multiMode.c new file mode 100644 index 0000000..3e3dd81 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RFCC26XX_multiMode.c @@ -0,0 +1,5248 @@ +/* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_rfc_rat.h) +#include DeviceFamily_constructPath(inc/hw_rfc_dbell.h) +#include DeviceFamily_constructPath(driverlib/rfc.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) +#include DeviceFamily_constructPath(driverlib/rf_mailbox.h) +#include DeviceFamily_constructPath(driverlib/adi.h) +#include DeviceFamily_constructPath(driverlib/aon_rtc.h) +#include DeviceFamily_constructPath(driverlib/chipinfo.h) + +#if defined(__IAR_SYSTEMS_ICC__) +#pragma diag_remark=Pa082 +#endif + +#if defined(RF_SINGLEMODE) +#error "An incompatible symbol (RF_SINGLEMODE) is defined in the project. \ + Either remove the RF_SINGLEMODE token definition OR switch to the \ + RFCC26XX_singleMode.c driver." +#endif + +/*-------------- Typedefs, structures & defines ---------------*/ + +/* Definition of internal state-machine events. */ +typedef enum RF_FsmEvent_ { + RF_FsmEventLastCommandDone = (1UL << 1), /* Indicates that a radio command is finished. */ + RF_FsmEventWakeup = (1UL << 2), /* Used to initiate the power up sequence of the RF core. */ + RF_FsmEventPowerDown = (1UL << 3), /* Used to initiate the power down sequence of the RF core. */ + RF_FsmEventInitChangePhy = (1UL << 10), /* Used to initiate the PHY change sequence. */ + RF_FsmEventFinishChangePhy = (1UL << 11), /* Used to finalize the PHY change sequence. */ + RF_FsmEventCpeInt = (1UL << 14), /* Generated during command execution. */ + RF_FsmEventPowerStep = (1UL << 29), /* Generated during the power up sequence of RF core. */ + RF_FsmEventRunScheduler = (1UL << 30) /* Used to invoke the scheduler again to check for conflicts. */ +} RF_FsmEvent; + +/* Definition of states of RF core. */ +typedef enum RF_CoreStatus_ { + RF_CoreStatusIdle = 0, /* The RF core is OFF. */ + RF_CoreStatusPoweringUp = 1, /* The RF core is being powered up. */ + RF_CoreStatusActive = 2, /* The RF core is ON. */ + RF_CoreStatusPoweringDown = 3, /* The RF core is being powered down. */ + RF_CoreStatusPhySwitching = 4 /* The RF core is being reconfigured. */ +} RF_CoreStatus; + +/* Definition of internal power constraints. Note that the physical RAT channels in the RF core are + not a one-to-one map to the constraint values here. */ +typedef enum RF_PowerConstraintSrc_ { + RF_PowerConstraintNone = 0, + RF_PowerConstraintRatCh0 = (1U << 0), /* Indicates that the Channel 0 of RAT timer is running. */ + RF_PowerConstraintRatCh1 = (1U << 1), /* Indicates that the Channel 1 of RAT timer is running. */ + RF_PowerConstraintRatCh2 = (1U << 2), /* Indicates that the Channel 2 of RAT timer is running. */ + RF_PowerConstraintCmdQ = (1U << 3), /* Indicates that the RF core executing a radio command. */ + RF_PowerConstraintDisallow = (1U << 7) /* Disable automatic power management. */ +} RF_PowerConstraintSrc; + +/* Definition of internal Radio Timer (RAT) modes. */ +typedef enum RF_RatMode_ { + RF_RatModeUndefined = 0, /* Indicates that the RAT channel is not configured. */ + RF_RatModeCompare = 1, /* Indicates that the RAT channel is configured to compare mode. */ + RF_RatModeCapture = 2 /* Indicates that the RAT channel is configured to capture mode. */ +} RF_RatMode; + +/* Definition of internal Radio Timer (RAT) states. */ +typedef enum RF_RatStatus_ { + RF_RatStatusIdle = 0, /* Indicates that the RAT channel is not used. */ + RF_RatStatusPending = 1, /* Indicates that the RAT channel is configured, but the RAT timer is not running (i.e. RF core is OFF). */ + RF_RatStatusRunning = 2 /* Indicates that the RAT channel is configured, and the RAT timer is running. */ +} RF_RatStatus; + +/* Definition of internal status codes of command shceduling. */ +typedef enum RF_ScheduleCmdStatus_ { + RF_ScheduleCmdSuccess = 0, /* Schedule command success. */ + RF_ScheduleCmdAllocError = 1, /* Schedule command allocation error (such as queue is full). */ + RF_ScheduleCmdSchError = 2 /* SChedule command scheduler error (timing or priority conflict). */ +} RF_ScheduleCmdStatus; + +/*-------------- Macros ---------------*/ + +#define ABS(x) (((x) < 0) ? -(x) : (x)) +#define MAX(x,y) (((x) > (y)) ? (x) : (y)) +#define MIN(x,y) (((x) < (y)) ? (x) : (y)) +#define UDIFF(x,y) (((y) > (x)) ? ((y) - (x)) : ((~0) + (y) - (x) + (1))) +#define ADD(x,y) ((x > ((~0) - (y))) ? (~0) : ((x) + (y))) + +/*-------------- Defines ---------------*/ + +/* Max # of RF driver clients */ +#define N_MAX_CLIENTS 2 +/* 8 RF_Cmds in pool */ +#define N_CMD_POOL 8 +/* Modulus mask used for RF_CmdHandle calculations */ +#define N_CMD_MODMASK 0xFFF + +/*-------------- Internal RF constants ---------------*/ + +#define RF_CMD0 0x0607 +/* Accessible RF Core interrupts mask MSB 32 bits : RFHW int, LSB 32 bits : RF CPE int */ +#define RF_INTERNAL_IFG_MASK 0xFFFFFFDF60001000 +#define RF_TERMINATION_EVENT_MASK (RF_EventLastCmdDone | RF_EventLastFGCmdDone | RF_EventCmdAborted | RF_EventCmdStopped | RF_EventCmdCancelled) +#define RF_CMD_FG_CMD_FLAG (1 << 4) +#define RF_CMD_ALLOC_FLAG (1 << 7) +#define RF_CMD_TERMINATED (DONE_OK | ERROR_PAST_START) +#define RF_HW_INT_RAT_CH_MASK (RFC_DBELL_RFHWIFG_RATCH7 | RFC_DBELL_RFHWIFG_RATCH6 | RFC_DBELL_RFHWIFG_RATCH5) +#define RF_RAT_CH_CNT 3 +#define RF_HW_INT_CPE_MASK RFC_DBELL_RFHWIFG_MDMSOFT +#define RF_CPE0_INT_MASK 0xFFFFFFFF +/* Default value for power up duration (in us) used before first power cycle */ +#define RF_DEFAULT_POWER_UP_TIME 2500 +/* Default minimum power up duration (in us) */ +#define RF_DEFAULT_MIN_POWER_UP_TIME 300 +/* Default power-up margin (in us) to account for wake-up sequence outside the RF power state machine */ +#define RF_DEFAULT_POWER_UP_MARGIN 314 +/* Default power down duration in us */ +#define RF_DEFAULT_POWER_DOWN_TIME 1000 +#define RF_MAX_CHAIN_CMD_LEN 8 +/* RAT channel (0-4) are used by RF Core. Only 5,6,7 are available for application */ +#define RF_RAT_CH_LOWEST 5 +#define RF_SEND_RAT_STOP_RATIO 7 +#define RF_RTC_CONV_TO_US_SHIFT 12 +#define RF_SHIFT_4_BITS 4 +#define RF_SHIFT_8_BITS 8 +#define RF_SHIFT_16_BITS 16 +#define RF_SHIFT_32_BITS 32 +#define RF_RTC_TICK_INC (0x100000000LL/32768) +#define RF_SCALE_RTC_TO_4MHZ 4000000 +#define RF_NUM_RAT_TICKS_IN_1_US 4 +/* (3/4)th of a full RAT cycle, in us */ +#define RF_DISPATCH_MAX_TIME_US (UINT32_MAX / RF_NUM_RAT_TICKS_IN_1_US * 3 / 4) +/* (1/4)th of a full RAT cycle, in us */ +#define RF_DISPATCH_MAX_TIME_WRAPAROUND_US (int32_t)(RF_DISPATCH_MAX_TIME_US - UINT32_MAX / RF_NUM_RAT_TICKS_IN_1_US) +#define RF_DISPATCH_INFINIT_TIME (UINT32_MAX) +#define RF_XOSC_HF_SWITCH_CHECK_PERIOD_US 50 +#define RF_DEFAULT_AVAILRATCH_VAL 0x7 +#define RF_ABORT_FLUSH_ALL 0x2 +#define RF_CMDSTA_REG_VAL_MASK 0xFF +#define RF_RAT_CAPTURE_REPEAT_MODE 0x10000000 +#define RF_RAT_INTERRUPT_BASE_INDEX 0x01 +#define RF_RAT_ERROR_BASE_INDEX 0x10 +#define RF_RAT_COMPENSATION_TIME_US 25 +#define RF_PHY_SWITCHING_MODE 1 +#define RF_PHY_BOOTUP_MODE 0 +#define RF_SCH_CMD_PRI_PREEMPT_STOP 0x1 +#define RF_SCH_CMD_PRI_PREEMPT_ABORT 0x2 +#define RF_SCH_CMD_PRI_PREEMPT_ADD 0x3 +#define RF_SCH_CMD_TIMING_INSERT 0x4 +#define RF_REQ_ACCESS_MAX_DUR_US 1000000 +/* Additional analog config time for setup command */ +#define RF_ANALOG_CFG_TIME_US 96 +/* Update analog configuration in setup */ +#define RF_SETUP_ANALOGCFG_UPDATE 0 +/* Don't update analog configuration in setup */ +#define RF_SETUP_ANALOGCFG_NOUPDATE 0x2D +#define RF_SCH_CMD_STARTTIME_NOW 0 +#define RF_SCH_CMD_ENDTIME_IGNORE 0 +#define RF_DEFAULT_PHY_SWITCHING_TIME 500 +#define RF_RADIOFREECB_PREEMPT_FLAG 0x1 +#define RF_RADIOFREECB_REQACCESS_FLAG 0x2 +#define RF_RADIOFREECB_CMDREJECT_FLAG 0x4 +#define RF_SCH_CMD_INSERT_QUEUE_TOP 0x1 +#define RF_SCH_CMD_INSERT_QUEUE_LATER 0x2 +#define RF_SCH_CMD_PREEMPT 0x4 +#define RF_DEFAULT_RAT_RTC_ERR_TOL_IN_US 5 +/* Approx for 1e6 / 500. XTAL drift is 500 ppm */ +#define RF_DEFAULT_COMB_XTAL_DRIFT_BITS_SHIFT 11 +/* Window (in us) to decide if wakeup was from RF power up clock */ +#define RF_WAKEUP_DETECTION_WINDOW_IN_US 300 +/* Ieee context mask and background value */ +#define RF_IEEE_ID_MASK 0xFC00 +#define RF_IEEE_FG_CMD 0x2C00 + +/*-------------- Structures and definitions ---------------*/ + +/* FSM typedef. */ +typedef void (*RF_FsmStateFxn)(RF_Object* obj, RF_FsmEvent const e); + +/* Rat channel configuration. */ +typedef struct RF_RatChannel_s RF_RatChannel; + +/* Rat channel configuration. */ +struct RF_RatChannel_s { + RF_Handle pClient; /* Pointer to current client. NULL means the channel is free. */ + RF_RatCallback pCb; /* Callback pointer of the channel. */ + RF_RatMode mode; /* Mode of this RAT channel: RF_RatModeCompare, etc. */ + RF_RatHandle handle; /* Channel number: 0,1,2. */ + RF_RatStatus status; /* Status of the channel: RF_RatStatusIdle, RF_RatStatusPending, RF_RatStatusRunning */ + uint64_t chCmd; /* Generic storage for the command structure itself. */ + uint32_t ioCmd; /* Raw binary to be sent to the CM0 to set up the GPOs. This is optional. */ +}; + +/* Rat module configuration. */ +typedef struct RF_RatModule_s RF_RatModule; + +/* Rat module configuration. */ +struct RF_RatModule_s { + RF_RatChannel channel[RF_RAT_CH_CNT]; /* Container of channel configurations. */ + uint8_t availableRatChannels; /* Storage of available RAT channels read from the RF core. */ + uint8_t volatile pendingInt; /* Pending interrupt flags to be served. */ + uint8_t numActiveChannels; /* Counter of active channels. This is used to compensate the + overhead of programming the channels.*/ +}; + +/* RF core configuration. */ +typedef struct RF_CoreState_s RF_CoreState; + +/* RF core configuration. */ +struct RF_CoreState_s +{ + RF_CoreStatus volatile status; + RF_FsmStateFxn fxn; + uint32_t activeTimeUs; + bool init; + bool manualXoscHfSelect; +}; + +/* RAT synchronization. */ +typedef union RF_RatSyncCmd_u RF_RatSyncCmd; + +/* RAT synchronization. */ +union RF_RatSyncCmd_u +{ + rfc_CMD_SYNC_START_RAT_t start; + rfc_CMD_SYNC_STOP_RAT_t stop; +}; + +/* Command queue. */ +typedef struct RF_CmdQ_s RF_CmdQ; + +/* Command queue. */ +struct RF_CmdQ_s{ + List_List pPend; /* List of pending commands to be dispatched. */ + List_List pDone; /* List of executed commands to be served. */ + RF_Cmd* volatile pCurrCmdBg; /* Currently running command. */ + RF_Cmd* volatile pCurrCmdFg; /* Currently running foreground command. */ + RF_Cmd* volatile pCurrCmdCb; /* Command which callback to be invoked. */ + RF_CmdHandle volatile nSeqPost; /* Sequence # for previously posted command. */ + RF_CmdHandle volatile nSeqDone; /* Sequence # for last done command. */ +}; + +/* RF scheduler. */ +typedef struct RF_Sch_s RF_Sch_t; + +/* RF scheduler. */ +struct RF_Sch_s { + RF_Handle clientHnd[N_MAX_CLIENTS]; /* client handles for each registered client */ + RF_AccessParams accReq[N_MAX_CLIENTS]; /* input parameters from any RF_requestAccess API calls */ + RF_Handle clientHndRadioFreeCb; /* client handle for the radio callback */ + /* structure to store items when scheduling results in preemption */ + struct { + RF_Handle client; /* RF_Handle for the preempted client */ + RF_CmdHandle cancelStartCmdHandle; /* RF_CmdHandle of the preemption start */ + bool cancelType; /* 1: flush gracefully, 0: flush abort */ + } preemptCmd; + uint8_t issueRadioFreeCbFlags; /* indicate if driver needs to issue RF_EventRadioFree callback {0:pre-emption, 1:requestAccess running, 2: reject command} */ + uint8_t cmdInsertFlags; /* indicate if the command was inserted based on timing information */ +}; + +/*-------------- RTOS objects ---------------*/ + +/* RF core software interrupts */ +static SwiP_Struct RF_swiFsmObj; +static void RF_swiFsm(uintptr_t a, uintptr_t b); + +/* RF core hardware interrupts */ +static HwiP_Struct RF_hwiCpe0Obj; +static void RF_hwiCpe0Active(uintptr_t a); +static void RF_hwiCpe0PowerFsm(uintptr_t a); + +/* RF core HW software interrupts */ +static SwiP_Struct RF_swiHwObj; +static void RF_swiHw(uintptr_t a, uintptr_t b); + +/* RF core HW hardware interrupts */ +static HwiP_Struct RF_hwiHwObj; +static void RF_hwiHw(uintptr_t a); + +/* Clock used for triggering power-up sequences */ +static ClockP_Struct RF_clkPowerUpObj; +static void RF_clkPowerUp(uintptr_t a); + +/* Common inactivity timeout clock callback */ +static ClockP_Struct RF_clkInactivityObj; +static void RF_clkInactivityCallback(uintptr_t a); + +/* Common request access timeout clock callback */ +static void RF_clkReqAccess(uintptr_t a); + + +/*-------------- Static structures ---------------*/ + +/* Default RF parameters structure */ +static const RF_Params RF_defaultParams = { + .nInactivityTimeout = SemaphoreP_WAIT_FOREVER, + .nPowerUpDuration = 0, + .pPowerCb = NULL, + .pErrCb = NULL, + .nPowerUpDurationMargin = RF_DEFAULT_POWER_UP_MARGIN, + .pClientEventCb = NULL, + .nClientEventMask = 0, +}; + +/*-------------- Global variables ---------------*/ + +/* RF_Cmd container pool. Containers with extra information about RF commands. */ +static RF_Cmd RF_cmdPool[N_CMD_POOL]; + +/* Command queue top level structure. It contains pointers to the different queues. */ +static RF_CmdQ RF_cmdQ; + +/* Static object used to subscribe from early notification in the power driver */ +static Power_NotifyObj RF_wakeupNotifyObj; + +/* Power constraints set by the RF driver */ +static volatile uint8_t RF_powerConstraint; + +/* Pointer to current radio client (indicates also whether the radio is powered) */ +static RF_Object* RF_currClient; + +/* Current state of the RF core. */ +static RF_CoreState RF_core; + +/* Static container of a direct/immediate commands */ +static RF_RatModule RF_ratModule; + +/* Commands used to synchronize the RTC and the RAT timer. */ +static volatile RF_RatSyncCmd RF_ratSyncCmd; + +/* Top level structure of the shceduler unit. */ +static RF_Sch_t RF_Sch; + +/* Variables used for powerUpDuration, phySwitchingTime and RAT sync time calculation. */ +static uint32_t RF_rtcTimestampA; /* RTC timer value power-up and active time calculation. */ +static uint32_t RF_rtcBeginSequence; /* RTC timer value for switching time calculation. */ +static uint32_t RF_errTolValInUs; /* max allowed error between RAT/RTC drift to enable resync at power-down (in us). */ + +/* Counter of radio clients */ +static uint8_t RF_numClients; + +/*-------------- Externs ---------------*/ + +/* Hardware attribute structure populated in board file. */ +extern const RFCC26XX_HWAttrsV2 RFCC26XX_hwAttrs; + +/*-------------- State machine functions ---------------*/ + +/* FSM state functions */ +static void RF_fsmPowerUpState(RF_Object *pObj, RF_FsmEvent e); +static void RF_fsmSetupState(RF_Object *pObj, RF_FsmEvent e); +static void RF_fsmActiveState(RF_Object *pObj, RF_FsmEvent e); +static void RF_fsmXOSCState(RF_Object *pObj, RF_FsmEvent e); + +/*-------------- Helper functions ---------------*/ + +/* Command queue handling */ +static RF_Cmd* RF_queueEnd(RF_Handle h, List_List* pHead); + +/* Command handling*/ +static bool RF_isClientOwner(RF_Handle h, RF_Cmd* pCmd); +static RF_Cmd* RF_cmdAlloc(void); +static RF_Cmd* RF_cmdGet(RF_Handle h, RF_CmdHandle ch, uint8_t mask); +static void RF_cmdStoreEvents(RF_Cmd* pCmd, RF_EventMask events); +static bool RF_cmdDispatchTime(uint32_t* dispatchTimeClockTicks); +static RF_Stat RF_abortCmd(RF_Handle h, RF_CmdHandle ch, bool graceful, bool flush, bool preempt); +static bool RF_checkCmdFsError(void); +static void RF_cacheFsCmd(RF_Cmd* pCmd); +static uint32_t RF_discardPendCmd(RF_Handle h, RF_Cmd* pCmd, bool bFlushAll, bool bPreempt); + +/* Scheduler */ +static void RF_issueRadioFreeCb(uint8_t src); +static bool RF_verifyGap(RF_Cmd* newCmd, RF_Cmd* prevCmd, RF_Cmd* nextCmd); +static bool RF_schResolveConflict(RF_Cmd* new, RF_Cmd* old); +static RF_Cmd* RF_checkForPreemption(RF_Handle h2, RF_Cmd* pCmd); +static RF_Stat RF_preemptClient(RF_Cmd* pCmd, RF_Priority prio); +static RF_ScheduleStatus RF_howToSchedule(RF_Handle h1, RF_Handle h2, RF_Cmd* pCmd, RF_Cmd** pTmp); +static RF_ScheduleStatus RF_schCmdRunInsertPreempt(RF_Handle h1, RF_Handle h2, RF_Cmd* pCmd); + +/* RAT module */ +static RF_RatChannel* RF_ratGetChannel(uint8_t ch); +static RF_RatChannel* RF_ratAllocChannel(RF_RatHandle ratChannel); +static uint32_t RF_ratGetChannelValue(RF_RatHandle ratHandle); +static uint32_t RF_ratGetValue(void); +static void RF_ratGenerateChCmd(RF_RatChannel* ratCh, void* ratConfig); +static void RF_ratGenerateIoCmd(RF_RatChannel* ratCh, RF_RatConfigOutput* ioConfig); +static RF_RatHandle RF_ratSetupChannel(RF_Handle ratClient, RF_RatMode ratMode, RF_RatCallback ratCallback, RF_RatHandle ratChannel, void* ratConfig, RF_RatConfigOutput* ioConfig); +static void RF_ratRestartChannels(void); +static RF_Stat RF_ratArmChannel(RF_RatChannel* ratCh); +static void RF_ratFreeChannel(RF_RatChannel* ratCh); +static void RF_ratSuspendChannels(void); +static bool RF_ratReleaseChannels(void); +static bool RF_ratDispatchTime(uint32_t* dispatchTimeClockTicks); +static bool RF_ratIsRunning(void); + +/* Time management */ +static uint32_t RF_calculateDeltaTimeUs(uint32_t absTime, uint32_t nTotalPowerUpDuration); +static bool RF_calculateDispatchTime(uint32_t* dispatchTimeClockTicks); +static void RF_dispatchNextEvent(void); +static void RF_dispatchNextCmd(void); +static void RF_restartClockTimeout(ClockP_Handle clock, uint32_t timeout); + +/* Power management */ +static void RF_corePowerDown(void); +void RF_powerConstraintRelease(RF_PowerConstraintSrc src); +void RF_powerConstraintSet(RF_PowerConstraintSrc src); +RF_PowerConstraintSrc RF_powerConstraintGet(RF_PowerConstraintSrc src); +static void RF_setInactivityTimeout(void); + +/* Others */ +static void RF_init(void); +static void RF_defaultCallback(RF_Handle h, RF_CmdHandle ch, RF_EventMask e); +static RF_Stat RF_runDirectImmediateCmd(RF_Handle h, uint32_t pCmd, uint32_t* rawStatus); +static RF_Stat RF_executeDirectImmediateCmd(uint32_t pCmd, uint32_t* rawStatus); +static void RF_invokeGlobalCallback(RF_GlobalEvent event, void* arg); +static void RF_dbellSubmitCmdAsync(uint32_t rawCmd); +static void RF_dbellSyncOnAck(void); +static bool RF_isRadioSetup(RF_Op* pOp); +static void RF_initRadioSetup(RF_Handle handle); +static void RF_radioOpDoneCb(void); +static RF_Op* RF_findEndOfChain(RF_Op* pOp); +static void RF_applyRfCorePatch(bool mode); +static bool RF_isStateTransitionAllowed(void); + +/* PA management */ +static RF_Stat RF_updatePaConfiguration(RF_RadioSetup* radioSetup, RF_TxPowerTable_Value newValue); + +/*-------------- Command queue internal functions ---------------*/ + +/* + * Compares the client of a command. + * + * Input: h - Client to check against. + * pCmd - Command to check. + * Return: true - If the client owns the command. + * false - Otherwise. + */ +static bool RF_isClientOwner(RF_Handle h, RF_Cmd* pCmd) +{ + if (pCmd && (pCmd->pClient == h)) + { + return(true); + } + else + { + return(false); + } +} + +/* + * Search last entry in simple queue for particular client. + * + * Input: h - Client handle. + * list - List to search within. + * Return: RF_Cmd if found any + */ +static RF_Cmd* RF_queueEnd(RF_Handle h, List_List* list) +{ + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Local variables */ + List_Elem* pTail = NULL; + List_Elem* pHead = List_head(list); + + /* Start at the head of queue */ + while (pHead) + { + if (RF_isClientOwner(h, (RF_Cmd*)pHead)) + { + pTail = pHead; + } + + pHead = List_next(pHead); + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with the last entry belongs to the client */ + return((RF_Cmd*)pTail); +} + +/* + * Allocate a command buffer from the command pool. + * + * Input: none + * Return: RF command + */ +static RF_Cmd* RF_cmdAlloc(void) +{ + uint32_t i; + for (i = 0; i < N_CMD_POOL; i++) + { + /* Find the first available entry in the command pool */ + if (!(RF_cmdPool[i].flags & RF_CMD_ALLOC_FLAG)) + { + return(&RF_cmdPool[i]); + } + } + return(NULL); +} + +/* + * Search command in the command pool. + * + * Input: h - Handle to the client which the command should belong to. + * ch - Handle to the command to search for. + * mask - Optional mask of flags to compare to. + * Return: RF command + */ +static RF_Cmd* RF_cmdGet(RF_Handle h, RF_CmdHandle ch, uint8_t mask) +{ + uint32_t i; + for (i = 0; i < N_CMD_POOL; i++) + { + /* Find the allocated command pool entry corresponding to ch */ + if (RF_cmdPool[i].ch == ch) + { + if (RF_isClientOwner(h, &RF_cmdPool[i])) + { + /* If a mask is provided, check the flags too */ + if (!mask || (RF_cmdPool[i].flags & mask)) + { + return(&RF_cmdPool[i]); + } + } + } + } + return(NULL); +} + +/* + * Atomic storage of radio events happened during the execution of a command. + * + * Input: pCmd - Command the events belogn to. + * events - The radio events to be store within the context of the command. + * Return: none + */ +static void RF_cmdStoreEvents(RF_Cmd* pCmd, RF_EventMask events) +{ + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Store the events within the context of the command. */ + if (pCmd) + { + /* The field rfifg store the events for the next callback. + The field pastifg accumulates the events in case an + RF_pendCmd() API call happens. */ + pCmd->rfifg |= events; + pCmd->pastifg |= events; + } + + /* Exit critical section. */ + HwiP_restore(key); +} + +/* + * Reconfigure and restart a particular clock object. + * + * Input: clockObj - A pointer to a clock object. + * timeoutClockTicks - The timeout to be set in unit of clock ticks. + * Return: none + */ +static void RF_restartClockTimeout(ClockP_Handle clockHandle, uint32_t timeoutClockTicks) +{ + /* Ceil the value at minimum 1 clock tick. */ + timeoutClockTicks = MAX(timeoutClockTicks, 1); + + /* Reprogram the clock object. */ + ClockP_setTimeout(clockHandle, timeoutClockTicks); + ClockP_start(clockHandle); +} + +/* + * Calculate the delta time to an RF event including the overhead of powering up + * and down. + * + * Input: abstime - The timestamp the event will need to happen. + * nTotalPowerUpDuration - The duration we need to compensate with. + * Return: deltaTime - The time left until the RF core need to be trigged. + */ +static uint32_t RF_calculateDeltaTimeUs(uint32_t absTime, uint32_t nTotalPowerUpDuration) +{ + /* Local variables. */ + uint32_t deltaTimeUs; + + /* Read the timestamp to calculate difference from. */ + uint32_t currentTime = RF_getCurrentTime(); + + /* Calculate the difference with the current timestamp. */ + deltaTimeUs = UDIFF(currentTime, absTime); + deltaTimeUs /= RF_NUM_RAT_TICKS_IN_1_US; + + /* Check if delta time is greater than (powerup duration + power down duration) for a + power cycle, and is less than 3/4 of a RAT cycle (~17 minutes) */ + if ((deltaTimeUs > (int32_t)(nTotalPowerUpDuration + RF_DEFAULT_POWER_DOWN_TIME)) && + (deltaTimeUs <= RF_DISPATCH_MAX_TIME_US)) + { + /* Dispatch command in the future */ + return(MAX((deltaTimeUs - nTotalPowerUpDuration), 1)); + } + else + { + /* Dispatch immediately */ + return(0); + } +} + +/* + * Calculate the wakeup time of next command in the queue. + * + * Input: dispatchTimeClockTicks - Location where the calculated time is being stored. + * Return: validTime - Indicates if the returned time is valid. + */ +static bool RF_cmdDispatchTime(uint32_t* dispatchTimeClockTicks) +{ + /* By default, there is no command in the queue. */ + bool validTime = false; + + /* The next command in the queue determines the timing. */ + RF_Cmd* pCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + /* Only recognizes TRIG_ABSTIME triggers, everything else gets dispatched immediately. */ + if (pCmd) + { + /* If there is at least one pending command, we can calculate a legit dispatch time. */ + validTime = true; + + if (pCmd->pOp->startTrigger.triggerType == TRIG_ABSTIME) + { + /* Calculate the remained time until this absolute event. The calculation takes + into account the minimum power cycle time. */ + *dispatchTimeClockTicks = RF_calculateDeltaTimeUs(pCmd->pOp->startTime, + pCmd->pClient->clientConfig.nPowerUpDuration + + pCmd->pClient->clientConfig.nPowerUpDurationMargin + + (RF_RAT_COMPENSATION_TIME_US * RF_ratModule.numActiveChannels)); + + /* Scale the value to clock ticks*/ + *dispatchTimeClockTicks /= ClockP_tickPeriod; + } + else + { + /* Dispatch immediately. */ + *dispatchTimeClockTicks = 0; + } + } + else + { + /* This value will not be used. */ + *dispatchTimeClockTicks = 0; + } + + /* If the returned timestamp represents a valid dispatch time, return with true. */ + return(validTime); +} + +/*-------------- RAT internal functions ---------------*/ + +/* + * Determines if the RAT timer is running (clock is not gated) or not. + * This is used to determine if any RAT related command can be execured. + * + * Input: none + * Return: PWMCLK_EN_RAT - RAT timer is running. + * 0 - RAT timer is not running. + */ +static bool RF_ratIsRunning(void) +{ + /* Assume by default that the RAT is not available. */ + bool status = false; + + /* If the RF core power domain is ON, read the clock of the RAT. */ + if (HWREG(PRCM_BASE + PRCM_O_PDSTAT0) & PRCM_PDSTAT0_RFC_ON) + { + status = (bool)(HWREG(RFC_PWR_BASE + RFC_PWR_O_PWMCLKEN) & RFC_PWR_PWMCLKEN_RAT_M); + } + + /* Return with the status of RAT. */ + return(status); +} + +/* + * Allocate a RAT channel from the three slots available + * for the user. + * + * Input: ratChannel - Pointer to a user provided RF_RatHandle. + * Return: RF_RatChannel* - Pointer to the allocated channel if success. + * NULL - If failure. + */ +static RF_RatChannel* RF_ratAllocChannel(RF_RatHandle ratChannel) +{ + /* Walk the RAT channel indexes. */ + uint32_t i; + for (i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Calculate the bit representing this channel within the available channels. */ + uint32_t bitMask = (1 << i); + + /* Verify that no one is using this channel (from outside the scope of RF driver). */ + if (RF_ratModule.availableRatChannels & bitMask) + { + /* Mask the possible channels if a user handle is provided, otherwise find the + the first available channel. */ + if ((ratChannel == RF_RatChannelAny) || (ratChannel == i)) + { + /* Decode the fields of a channel. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* If an available channel is found. */ + if (ratCh && (ratCh->status == RF_RatStatusIdle)) + { + /* Mark the channel as occupied. */ + RF_ratModule.availableRatChannels &= ~bitMask; + + /* Put the channel into pending state. */ + ratCh->status = RF_RatStatusPending; + ratCh->handle = i; + + /* Increment the counter of active channels. This is used to compensate the + power up time with the overhead of programming these channels. */ + RF_ratModule.numActiveChannels += 1; + + /* Return with a pointer to the channel. */ + return(ratCh); + } + } + } + } + + /* Return with an invalid channel pointer in case of error. */ + return(NULL); +} + +/* + * Free a given RAT channel. + * + * Input: ratCh - Pointer to a RAT channel in RF_ratModule. + * Return: none + */ +static void RF_ratFreeChannel(RF_RatChannel* ratCh) +{ + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* If a valid pointer is provided */ + if (ratCh && ratCh->status) + { + /* Precalculate the contraint ID of this channel. */ + RF_PowerConstraintSrc powerConstraint = (RF_PowerConstraintSrc)(1 << ratCh->handle); + + /* If the RF core power domain is ON. */ + if (RF_ratIsRunning()) + { + /* Calculate the channel index based on the handle. */ + uint32_t ratChIntFlag = (1 << (RFC_DBELL_RFHWIFG_RATCH5_BITN + ratCh->handle)); + + /* Disable the RAT channel interrupt source. */ + RFCHwIntDisable(ratChIntFlag); + RFCHwIntClear(ratChIntFlag); + } + + /* Reset the status of the channel. */ + ratCh->status = RF_RatStatusIdle; + ratCh->mode = RF_RatModeUndefined; + ratCh->pClient = NULL; + ratCh->pCb = NULL; + ratCh->chCmd = 0; + ratCh->ioCmd = 0; + + /* Mark the channel as available. */ + RF_ratModule.availableRatChannels |= (1 << ratCh->handle); + + /* Decrement the counter of active channels. To avoid underflow, check its value first. */ + if (RF_ratModule.numActiveChannels) + { + RF_ratModule.numActiveChannels -= 1; + } + + /* Notify the state machine that the RF core can be possibly powered down. */ + RF_powerConstraintRelease(powerConstraint); + } + + /* Exit critical section */ + HwiP_restore(key); +} + +/* + * Returns with a pointer to a RAT channel based on it's handle. + * + * Input: ch - Channel handle. + * Return: ratCh - Pointer to a RAT channel in RF_ratModule. + */ +static RF_RatChannel* RF_ratGetChannel(uint8_t ch) +{ + /* Convert a valid index into a pointer of a RAT channel configuration. */ + if (ch < RF_RAT_CH_CNT) + { + return((RF_RatChannel*)&RF_ratModule.channel[ch]); + } + + /* Return with NULL in case of invalid input argument. */ + return(NULL); +} + +/* + * Suspend the running channels and potentially initiate a power down. + * + * Input: none + * Return: true - All RAT channel is suspended. + * false - Otherwise. + */ +static bool RF_ratReleaseChannels(void) +{ + /* Only try to release the RAT channels if there is no other dependencies set. */ + if (!RF_powerConstraintGet(RF_PowerConstraintCmdQ) && + !RF_powerConstraintGet(RF_PowerConstraintDisallow)) + { + /* Calculate if there is enough time to power down and up. */ + uint32_t dispatchTimeClockTicks; + bool validTime = RF_calculateDispatchTime(&dispatchTimeClockTicks); + + /* If the next event is sufficiently far into the future. */ + if (!validTime || (validTime && dispatchTimeClockTicks)) + { + /* Suspend all RAT channels. */ + RF_ratSuspendChannels(); + + /* RAT channels were suspended. */ + return(true); + } + } + + /* RAT channels were not suspended. */ + return(false); +} + +/* + * Calculate the timeout of closest RAT event. + * + * Input: dispatchTimeClockTicks - Location where the calculated time is being stored. + * Return: validTime - Indicates if the returned time is valid. + */ +static bool RF_ratDispatchTime(uint32_t* dispatchTimeClockTicks) +{ + /* By default, there is no RAT running. */ + bool validTime = false; + + /* Initialize the return value. */ + *dispatchTimeClockTicks = RF_DISPATCH_INFINIT_TIME; + + /* Iterate through the RAT containers and calculate the remained time until + the closest RAT event. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Use a local pointer to have easier access to member fields. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* If the channel is either in PENDING or RUNNING state, meaning it is in use. */ + if (ratCh && ratCh->status) + { + /* There is at least one active channel, we can calculate a legit timestamp. */ + validTime = true; + + /* If there is at least one channel in Capture mode, we need to power + up immediately. */ + if (ratCh->mode == RF_RatModeCapture) + { + /* Use immediate timeout orcing the RF core to be powered up. */ + *dispatchTimeClockTicks = 0; + + /* No point to look to the other RAT channels.*/ + break; + } + else + { + /* Decode the compareTime field. */ + uint32_t compareTime = ((rfc_CMD_SET_RAT_CMP_t*)&ratCh->chCmd)->compareTime; + + /* Calculate the remained time until this RAT event. The calculation takes + into account the minimum power cycle time. */ + uint32_t deltaTimeUs = RF_calculateDeltaTimeUs(compareTime, + RF_currClient->clientConfig.nPowerUpDuration + + RF_currClient->clientConfig.nPowerUpDurationMargin + + (RF_RAT_COMPENSATION_TIME_US * RF_ratModule.numActiveChannels)); + + /* Scale the value to clock ticks. */ + uint32_t deltaTimeClockTicks = deltaTimeUs / ClockP_tickPeriod; + + /* If this is the closest RAT event, update the timer. */ + if (deltaTimeClockTicks < (*dispatchTimeClockTicks)) + { + *dispatchTimeClockTicks = deltaTimeClockTicks; + } + } + } + } + + /* Return with true if the dispatchTime represents a valid timestamp. */ + return(validTime); +} + +/* + * Arms a given RAT channel. The mode of the channel will define which mode + * it is being configured to. The cmd variable contains the raw word to be + * sent to the RF core. + * + * Input: ratCh - Pointer to a RAT channel. + * Return: status - Status code based on the response of RF core. + * + */ +static RF_Stat RF_ratArmChannel(RF_RatChannel* ratCh) +{ + /* Local variable */ + RF_Stat status = RF_StatError; + + /* Only those channels can be programmed which are in pending state. */ + if (ratCh && (ratCh->status == RF_RatStatusPending)) + { + /* Calculate the channel interrupt flag on the handle. */ + uint32_t ratChIntFlag = (1 << (RFC_DBELL_RFHWIFG_RATCH5_BITN + ratCh->handle)); + + /* Clear and enable the interrupt source for that particular channel. */ + RFCHwIntClear(ratChIntFlag); + RFCHwIntEnable(ratChIntFlag); + + /* Set the power constraint on this channel to keep the RF core ON. */ + RF_powerConstraintSet((RF_PowerConstraintSrc)(1 << ratCh->handle)); + + /* Send the command to the RF core. */ + status = RF_executeDirectImmediateCmd((uint32_t)&ratCh->chCmd, NULL); + + /* If the channel configuration is succesfull. */ + if (status == RF_StatCmdDoneSuccess) + { + /* Send the IO command to the RF core if there is any configured. */ + if (ratCh->ioCmd) + { + status = RF_executeDirectImmediateCmd((uint32_t)ratCh->ioCmd, NULL); + } + + /* If both the channel and io configuration is succesfull. */ + if (status == RF_StatCmdDoneSuccess) + { + ratCh->status = RF_RatStatusRunning; + } + } + } + + /* Return with the status code. */ + return(status); +} + +/* + * Restarts any RAT channels which are in pending state at the moment of + * invoking this method. This is used to automatically restore the rat module + * right after the RF core is powered up. This is essential for power management. + * + * Input: none + * Return: none + * + */ +static void RF_ratRestartChannels(void) +{ + /* Iterate through the RAT containers and restore the channels + which were in running state before we entered Standby mode. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Convert the index to a pointer. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* If the channel is in pending state, program it. */ + if (ratCh && (ratCh->status == RF_RatStatusPending)) + { + /* Try to program the RAT channel. */ + RF_Stat status = RF_ratArmChannel(ratCh); + + /* Execute error handling if programming fails, i.e. due to past timestamp. + This is done in SWI context. */ + if (status != RF_StatCmdDoneSuccess) + { + /* Mark the event as an error by setting also a shadow bit. */ + RF_ratModule.pendingInt |= ((RF_RAT_INTERRUPT_BASE_INDEX | RF_RAT_ERROR_BASE_INDEX) << ratCh->handle); + + /* Post the SWI handler to serve the callback. */ + SwiP_or(&RF_swiHwObj, 0); + } + } + } +} + +/* + * Suspends any RAT channel which are in RUNNING state. + * This is used to force all RAT channels into pending state allowing the power + * management to power off the RF core power domain and resynchronize the RAT channels + * on next power up. + * + * Input: none + * Return: none + */ +static void RF_ratSuspendChannels(void) +{ + /* Iterate through the RAT containers and suspend the active channels. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Set a pointer to the channel. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* Only actively running channles can be suspended. */ + if (ratCh && ratCh->status) + { + /* Set the status to be suspended. */ + ratCh->status = RF_RatStatusPending; + + /* Clear the power constraint of this channel */ + RF_powerConstraintRelease((RF_PowerConstraintSrc)(1 << ratCh->handle)); + } + } +} + +/* + * Read the counter value from the RAT timer. + * + * Input: none + * Return: time - The value found in the RATCNT running register. + */ +static uint32_t RF_ratGetValue(void) +{ + return(HWREG(RFC_RAT_BASE + RFC_RAT_O_RATCNT)); +} + +/* + * Read the channel value from the RAT timer. + * + * Input: ratHandle - The handle to the channel. + * Return: timeout - The value found in the RATCHxVAL register. + */ +static uint32_t RF_ratGetChannelValue(RF_RatHandle ratHandle) +{ + /* Read the channel value. */ + return(HWREG(RFC_RAT_BASE + RFC_RAT_O_RATCH5VAL + ratHandle * sizeof(uint32_t))); +} + +/* + * Generate a command which can be used to configure a RAT channel into COMPARE mode. + * + * Input: ratCh - Pointer to the channel. + * ratConfig - Configuration structure holding the channel setup. + * Return: none + */ +static void RF_ratGenerateChCmd(RF_RatChannel* ratCh, void* ratConfig) +{ + /* Generate a command based on the mode. */ + if (ratCh->mode == RF_RatModeCompare) + { + /* Local pointer to cast the configuration to the proper type. */ + RF_RatConfigCompare* ratCompareConfig = (RF_RatConfigCompare*) ratConfig; + + /* Point a pointer to the generic command field within the channels context. */ + rfc_CMD_SET_RAT_CMP_t* pCmd = (rfc_CMD_SET_RAT_CMP_t*)&ratCh->chCmd; + + /* Populate the command structure properly. */ + pCmd->commandNo = CMD_SET_RAT_CMP; /* Instruct the RF core to use COMPARE mode. */ + pCmd->ratCh = RF_RAT_CH_LOWEST + ratCh->handle; /* Encode the selected channel number. */ + pCmd->compareTime = ratCompareConfig->timeout; /* Select the compare timeout. */ + } + else if (ratCh->mode == RF_RatModeCapture) + { + /* Local pointer to cast the configuration to the proper type. */ + RF_RatConfigCapture* ratCaptureConfig = (RF_RatConfigCapture*) ratConfig; + + /* Point a pointer to the generic command field within the channels context. */ + rfc_CMD_SET_RAT_CPT_t* pCmd = (rfc_CMD_SET_RAT_CPT_t*)&ratCh->chCmd; + + /* Calculate the direct command to be sent to the RF core.*/ + pCmd->commandNo = CMD_SET_RAT_CPT; /* Instruct the RF core to use CAPTURE mode. */ + pCmd->config.ratCh = RF_RAT_CH_LOWEST + ratCh->handle; /* Encode the selected channel number. */ + pCmd->config.inputSrc = ratCaptureConfig->source; /* Select the source to be captured. */ + pCmd->config.inputMode = ratCaptureConfig->captureMode; /* Select the mode of capture: raising, falling, etc*/ + pCmd->config.bRepeated = ratCaptureConfig->repeat; /* Select if we should re-arm the channel after a capture event. */ + } +} + +/* + * Generate a command which can be used to configure an IO for a particular RAT channel. + * + * Input: ratCh - Pointer to the channel. + * ioConfig - Configuration channel for the IO. + * Return: cmdToDoorbell - Return with the command structure. It is casted to uint32_t as it is + * stored in a generic variable. + */ +static void RF_ratGenerateIoCmd(RF_RatChannel* ratCh, RF_RatConfigOutput* ioConfig) +{ + /* Local variable. */ + uint32_t cmdToDoorbell = 0; + + /* If there is an IO configuration. */ + if (ioConfig) + { + cmdToDoorbell |= ioConfig->select << 2; + cmdToDoorbell |= ioConfig->mode << 5; + cmdToDoorbell |= (uint32_t)(RF_RAT_CH_LOWEST + ratCh->handle) << 8; + + cmdToDoorbell = (uint32_t)CMDR_DIR_CMD_2BYTE(CMD_SET_RAT_OUTPUT, cmdToDoorbell); + } + + /* Return with the raw command to be sent to the doorbell. */ + ratCh->ioCmd = cmdToDoorbell; +} + +/* + * Wrapper function to setup a RAT channel into the selected mode. + * + * Input: ratClient - Handle previously returned by RF_open(). + * ratMode - Identifies the mode the channel is being set up: RF_RatModeCompare or RF_RatModeCapture. + * ratCallback - Callback function to be registered to the RAT channel. + * ratChannel - Preferred channel to be allocated. If RF_RatChannelAny is provided, allocatethe first available channel. + * ratConfig - Configuration structure holding the setup of the particulare channel. + * ioConfig - Configuration strucutre of the assosiated GPO setup. + * Return: ratHandle - RF_RatHandle to the allocated channel. If allocation fails, RF_ALLOC_ERROR is returned. + */ +static RF_RatHandle RF_ratSetupChannel(RF_Handle ratClient, RF_RatMode ratMode, RF_RatCallback ratCallback, RF_RatHandle ratChannel, void* ratConfig, RF_RatConfigOutput* ioConfig) +{ + /* Return with an error. Either we couldn't allocate any RAT + channel, or the RAT module declined our configuration. */ + RF_RatHandle ratHandle = (RF_RatHandle)RF_ALLOC_ERROR; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Find and allocate a RAT channel (if any is available) */ + RF_RatChannel* ratCh = RF_ratAllocChannel(ratChannel); + + /* If we could allocate a RAT channel */ + if (ratCh) + { + /* Populate the container. Use the default "do nothing" callback + if no user callback is provided and generate the command based + on the mode of the channel. */ + ratCh->pClient = ratClient; + ratCh->mode = ratMode; + ratCh->pCb = (RF_RatCallback)RF_defaultCallback; + RF_ratGenerateChCmd(ratCh, ratConfig); + RF_ratGenerateIoCmd(ratCh, ioConfig); + + /* If there is a user callback provided, override the default callback. */ + if (ratCallback) + { + ratCh->pCb = ratCallback; + } + + /* Decide which PHY should be used upon first start up. */ + if (RF_currClient == NULL) + { + RF_currClient = ratCh->pClient; + } + + /* Calculate the RAT/RTC timestamp to be used to wake the RF core. */ + RF_dispatchNextEvent(); + + /* Return with the handle upon success. */ + ratHandle = (RF_RatHandle)ratCh->handle; + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with either an error OR a handle to a RAT channel. */ + return(ratHandle); +} + +/* + * Poll the RFACKIFG and clear the flag afterwards. This is used during the power up sequence + * of the RF core where interlaying processing is implemented. + * + * Input: none + * Return: none + */ +static void RF_dbellSyncOnAck(void) +{ + while (!HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG)); + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0; +} + +/* + * Submit a command to the doorbell without blocking command execution. This is used during the + * power up sequence where the system CPU can continue with processing data while the RF core + * executes the submitted command. + * + * Input: rawCmd - The raw command to be written to the doorbell. This can be a pointer or a + * a direct/immediate command. + * Return: none + */ +static void RF_dbellSubmitCmdAsync(uint32_t rawCmd) +{ + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0; + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) = rawCmd; +} + +/* + * Wake up notification callback from the power driver. If the callback is from RF wakeup + * set constraint to let RF Driver control the XOSC switching else do nothing in the + * callback. + * + * Input: eventType - The type of event when the notification is invoked + * eventArg - Not used. + * clientArg - Not used. + * Return: Power_NOTIFYDONE + */ +static uint8_t RF_wakeupNotification(uint8_t eventType, uint32_t *eventArg, uint32_t *clientArg) +{ + /* Check if the callback is for wakeup from standby and if power up clock is running */ + if ((eventType == PowerCC26XX_AWAKE_STANDBY) && (ClockP_isActive(&RF_clkPowerUpObj))) + { + /* Calculate time (in us) until next trigger (assume next trigger is max ~70 min away) */ + uint32_t timeInUsUntilNextTrig = ClockP_tickPeriod * ClockP_getTimeout(&RF_clkPowerUpObj); + + /* Check if the next trig time is close enough to the actual power up */ + if (timeInUsUntilNextTrig < RF_WAKEUP_DETECTION_WINDOW_IN_US) + { + /* Stop power up clock */ + ClockP_stop(&RF_clkPowerUpObj); + + /* Setup RF Driver to do the XOSC_HF switching */ + Power_setConstraint(PowerCC26XX_SWITCH_XOSC_HF_MANUALLY); + + /* Set variable to indicate RF Driver will do the XOSC_HF switching */ + RF_core.manualXoscHfSelect = true; + + /* Start the RF Core power up */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventWakeup); + } + } + + return(Power_NOTIFYDONE); +} + +/*-------------- Scheduler internal functions --------------------------------*/ + +/* + * Issue RF_EventRadioFree callback to the client. The callback is issued - + * 1. After pre-emption is complete + * 2. Dedicated request access period expires or released + * 3. command reject because of other high priority command running + * + * Input: src - Flag indicating the source of callback request. + * Return: none + */ +static void RF_issueRadioFreeCb(uint8_t src) +{ + /* Enter critical section*/ + uint32_t key = HwiP_disable(); + + /* Clear the reason why the callback is being invoked */ + RF_Sch.issueRadioFreeCbFlags &= ~src; + + /* Local variable */ + bool isReqAccessActive = false; + + /* If any of the clients has active request access, indicate it */ + if (RF_Sch.clientHnd[0]) + { + isReqAccessActive |= ClockP_isActive(&RF_Sch.clientHnd[0]->state.clkReqAccess); + } + if (RF_Sch.clientHnd[1]) + { + isReqAccessActive |= ClockP_isActive(&RF_Sch.clientHnd[1]->state.clkReqAccess); + } + + /* If we cleared all the potential sources and there is no request access*/ + if ((RF_Sch.issueRadioFreeCbFlags == 0) && !isReqAccessActive) + { + /* If a valid client handle is provided through the global pointer */ + if (RF_Sch.clientHndRadioFreeCb && (RF_Sch.clientHndRadioFreeCb->clientConfig.nClientEventMask & RF_ClientEventRadioFree)) + { + /* Get a pointer to the client event callback */ + RF_ClientCallback pClientEventCb = (RF_ClientCallback)RF_Sch.clientHndRadioFreeCb->clientConfig.pClientEventCb; + + /* Exit critical section */ + HwiP_restore(key); + + /* Invoek the client event callback */ + pClientEventCb(RF_Sch.clientHndRadioFreeCb, RF_ClientEventRadioFree, NULL); + + /* Clear the client pointer in any case */ + RF_Sch.clientHndRadioFreeCb = NULL; + } + else + { + /* Exit critical section */ + HwiP_restore(key); + } + } + else + { + /* Exit critical section */ + HwiP_restore(key); + } +} + +/* + * Decode how much time it will take to switch protocol/phy configuration. + * + * Input: prevCmd - The command switching from. + * nextCmd - The command switching to. + * Return: switchingTime - The time it takes to switch the PHY. + */ +static int32_t RF_getSwitchingTimeInUs(RF_Cmd* prevCmd, RF_Cmd* nextCmd) +{ + int32_t switchingTime = 0; + + /* If otherCmd and newCmd are from different client then there is a switching time + related to moving between the two commands. */ + if (prevCmd->pClient != nextCmd->pClient) + { + switchingTime = nextCmd->pClient->clientConfig.nPhySwitchingDuration; + } + + /* Return the switching time related to moving between the two clients. */ + return(switchingTime); +} + +/* + * Check if new request can inserted between the previous and next command in the + * current queue. + * + * Input: newCmd - RF_Cmd pointer for the new command request + * prevCmd - RF_Cmd pointer for the previous cmd in the queue + * nextCmd - RF_Cmd pointer for the next cmd in the queue + * Return: true - If command can be inserted in the queue else + * false - Otherwise. + */ +static bool RF_verifyGap(RF_Cmd* newCmd, RF_Cmd* prevCmd, RF_Cmd* nextCmd) +{ + /* Initialize local variables. */ + bool insertNewCmdAfterPrev = prevCmd ? false : true; + bool insertNewCmdBeforeNext = nextCmd ? false : true; + int32_t deltaInUs = 0; + + /* Step 1 - The newCmd must have an endTime in order to be placed anywhere + else than the end. Or if there are no commands behind. */ + if ((newCmd) && (insertNewCmdBeforeNext || (newCmd->endTime != RF_SCH_CMD_ENDTIME_IGNORE))) + { + /* If there is a prevCmd and it have an endTime, we could potentially + put the new command behind it. */ + if ((prevCmd) && (prevCmd->endTime != RF_SCH_CMD_ENDTIME_IGNORE)) + { + /* Take the start time of the command located later in the timeline. */ + deltaInUs = (int32_t)RF_convertRatTicksToUs(newCmd->startTime); + + /* Substract the time earlier in the timeline. The result is the gap in between. */ + deltaInUs -= (int32_t)RF_convertRatTicksToUs(prevCmd->endTime); + + /* Substract the switching time needed to move between prevCmd and newCmd. */ + deltaInUs -= RF_getSwitchingTimeInUs(prevCmd, newCmd); + + /* Handle timer overflow with the assumption that the difference between the startTime + and endTime is less than ~8 min. */ + if ((deltaInUs < ((int32_t)RF_DISPATCH_MAX_TIME_WRAPAROUND_US)) || (deltaInUs > 0)) + { + /* Allow insertion if startTime has wrapped around or no wrap around and we can insert the command */ + insertNewCmdAfterPrev = true; + } + } + + /* If there is a nextCmd, and it has an aboslute startTime, we could potentially put the new command in front of it. + If we already have evaluated that we can't be behind the prevCmd, there is no need to evalue this. */ + if ((insertNewCmdAfterPrev) && (nextCmd) && (nextCmd->pOp->startTrigger.triggerType == TRIG_ABSTIME)) + { + /* Take the start time of the command located later in the timeline. */ + deltaInUs = (int32_t)RF_convertRatTicksToUs(nextCmd->startTime); + + /* Substract the time earlier in the timeline. The result is the gap in between. */ + deltaInUs -= (int32_t)RF_convertRatTicksToUs(newCmd->endTime); + + /* Substract the switching time needed to move between newCmd and nextCmd. */ + deltaInUs -= RF_getSwitchingTimeInUs(newCmd, nextCmd); + + /* Handle timer overflow with the assumption that the difference between the startTime + and endTime is less than ~8 min. */ + if ((deltaInUs < ((int32_t)RF_DISPATCH_MAX_TIME_WRAPAROUND_US)) || (deltaInUs > 0)) + { + /* Allow insertion if startTime has wrapped around or no wrap around and we can insert the command. */ + insertNewCmdBeforeNext = true; + } + } + } + + /* Return with true if the command can be inserted into the queue (both before or after criteria met). */ + return(insertNewCmdBeforeNext & insertNewCmdAfterPrev); +} + +/* + * Check if the requesting command can preempt the conflicting command. + * + * Input: new - RF_Cmd pointer to the requesting command + * old - RF_Cmd pointer to the conflicting command + * Return: bool - Indicate if the requesting command can preempt the conflicting + * command. + */ +static bool RF_schResolveConflict(RF_Cmd* new, RF_Cmd* old) +{ + return ((new->ePri > old->ePri ? true : false)); +} + +/* + * Check if the requesting command can be scheduled by preempting the running command + * or any of the commands in the queue belonging to the other client. + * + * Input: h2 - RF_Handle to the other client + * pCmd - RF_Cmd pointer to the requesting command + * Return: RF_Cmd* - RF_Cmd pointer to the first command to be preempted. + * Return pointer to the requesting command if there is + * no commands from the other client running/queued. + */ +static RF_Cmd* RF_checkForPreemption(RF_Handle h2, RF_Cmd* pCmd) +{ + RF_Cmd* it = (RF_Cmd*) List_head(&RF_cmdQ.pPend); + RF_Cmd* preemptCmd = NULL; + bool canBePreempted = NULL; + + /* Per default, no commands belonging to h2 is found in the queue */ + bool noH2Cmd = true; + + /* Check if we can preempt the running command */ + if (RF_isClientOwner(h2, RF_cmdQ.pCurrCmdBg)) + { + noH2Cmd = false; + canBePreempted = RF_schResolveConflict(pCmd, RF_cmdQ.pCurrCmdBg); + if (canBePreempted) + { + preemptCmd = RF_cmdQ.pCurrCmdBg; + } + } + + /* Check if it is possible to preempt any of the + commands in the queue */ + while (it) + { + if (RF_isClientOwner(h2, it)) + { + noH2Cmd = false; + + canBePreempted = RF_schResolveConflict(pCmd, it); + if (canBePreempted && !preemptCmd) + { + preemptCmd = it; + } + + /* Any individual command found in the queue which fails on + the preemption criterion will clear the preemption pointer. */ + if (!canBePreempted) + { + preemptCmd = NULL; + } + } + it = (RF_Cmd*)List_next((List_Elem*)it); + } + + /* If there was no commands belonging to h2 in the queue, + return with the requesting command */ + if (noH2Cmd) + { + preemptCmd = pCmd; + } + + return(preemptCmd); +} + +/* + * Preempts the the given command and any of the following commands that belongs to the owner. + * + * Input: pCmd - RF_Cmd pointer to the command that is the first to be preempted. + * prio - Priority of the preempting command. + * + * Return: RF_Stat - Returning the abortCmd status code. + */ +static RF_Stat RF_preemptClient(RF_Cmd* pCmd, RF_Priority prio) +{ + /* Abort the running command per default*/ + bool graceful = false; + + /* If the priority of the preempting command is Normal, we shouldn't get here. + If it is High, use the STOP method to terminate the running command. + If it is Highest, use the ABORT method to terminate the running command. */ + if (prio == RF_PriorityHigh) + { + graceful = true; + } + + /* Abort multiple radio commands implicitly, mark them as preempted */ + return (RF_abortCmd(pCmd->pClient, pCmd->ch, graceful, true, true)); +} + +/* + * Check what scheduling strategy that can be used to schedule the requesting command. + * + * Input: h1 - RF_Handle to the requesting client + * h2 - RF_Handle to the other client + * pCmd - RF_Cmd pointer to the requesting command + * pTmp - RF_Cmd pointer to the existing command which the new command will be scheduled against. + * + * Return: RF_ScheduleStatus - Returning schStatus containing the schduling decision. + */ +static RF_ScheduleStatus RF_howToSchedule(RF_Handle h1, RF_Handle h2, RF_Cmd* pCmd, RF_Cmd** pTmp) +{ + /* Local variable. */ + RF_ScheduleStatus status = RF_ScheduleStatusNone; + + /* Set the iterator to the top of the pend queue. */ + RF_Cmd* it = (RF_Cmd*) List_head(&RF_cmdQ.pPend); + + /* Step 1a - Check if new command can be inserted based on the timing information + at the top of the pending queue .*/ + RF_Cmd* tmp = RF_queueEnd(h1, &RF_cmdQ.pPend); + if (!tmp && List_head(&RF_cmdQ.pPend)) + { + if (RF_verifyGap(pCmd, RF_cmdQ.pCurrCmdBg, (RF_Cmd*) List_head(&RF_cmdQ.pPend))) + { + /* Indicate that the command was put on the top of the queue */ + status = RF_ScheduleStatusTop; + it = NULL; + } + } + + /* Step 1b - Check if new command can be inserted based on the timing information + in the middle/end of the pending queue.*/ + if (status == RF_ScheduleStatusNone) + { + if (tmp) + { + it = tmp; + } + + while (it) + { + if (RF_verifyGap(pCmd, it, (RF_Cmd*)List_next((List_Elem*)it))) + { + /* Insert command between pTmp and pTmp->pNext */ + status = RF_ScheduleStatusMiddle; + break; + } + else + { + it = (RF_Cmd*)List_next((List_Elem*)it); + } + } + } + + /* Step 2 - Check if new command can preempt existing commands based on priority.*/ + if (status == RF_ScheduleStatusNone) + { + it = RF_checkForPreemption(h2, pCmd); + if (it && (it != pCmd)) + { + status = RF_ScheduleStatusPreempt; + } + } + + /* Step 4 - Check if new command can be appended to the end of pending queue. */ + if (status == RF_ScheduleStatusNone && (it == NULL)) + { + /* Traverse to the end of the command queue */ + it = (RF_Cmd*)List_tail(&RF_cmdQ.pPend); + + /* If new command has TRIG_ABSTIME triggerType and pastTrig = 0 -> + check if the timing can be meet to append to command to the end of the queue, + reject command is cannot be appended */ + if ((pCmd->pOp->startTrigger.triggerType == TRIG_ABSTIME) && !pCmd->pOp->startTrigger.pastTrig) + { + if (it || (!it && RF_cmdQ.pCurrCmdBg && !RF_verifyGap(pCmd, RF_cmdQ.pCurrCmdBg, NULL))) + { + /* Return with status schedule error */ + return(RF_ScheduleStatusError); + } + } + } + + /* Return it via pTmp */ + *pTmp = it; + + /* Return with the scheduling method. */ + return(status); +} + +/* + * Check if new command can be scheduled based on to the current command queue + * and the request access. + * + * Input: h1 - RF_Handle of requesting command. + * h2 - RF_Handle of the client not requesting the new command. + * pCmd - Pointer to the requesting command. + * + * Return: NULL - If new command request cannot be met. + * int8_t - Schedule method invoked. + */ +static int8_t RF_schCmdRunInsertPreempt(RF_Handle h1, RF_Handle h2, RF_Cmd* pCmd) +{ + RF_Cmd* pTmp = NULL; + int8_t schStatus = 0; + + /* + * Based on the assumption that all commands are posted in chronological order + * (and with fitting timings), if there is no h2, just put it on the end. + */ + if (h2) + { + /* Check how the new command should be scheduled */ + schStatus = RF_howToSchedule(h1, h2, pCmd, &pTmp); + } + + /* + Insert as specified by status: + 1a. Insert at top of the queue. + 1b. Insert in between two commands in the queue. + 2. Preempt the other client from the given point in the queue. + 2-3. Append the command to the end of the queue + */ + + /* Step 1a */ + if (schStatus == RF_ScheduleStatusTop) + { + /* Insert command at the beginning of the queue */ + List_putHead(&RF_cmdQ.pPend, (List_Elem*)pCmd); + } + + /* Step 1b */ + if (schStatus == RF_ScheduleStatusMiddle) + { + /* Insert command between pTmp and pTmp->pNext */ + if (List_next((List_Elem*)pTmp)) + { + /* Insert command before pTmp->next */ + List_insert(&RF_cmdQ.pPend, (List_Elem*)pCmd, List_next((List_Elem*)pTmp)); + } + else + { + List_put(&RF_cmdQ.pPend, (List_Elem*)pCmd); + } + } + + /* Step 2 */ + if (schStatus == RF_ScheduleStatusPreempt) + { + /* Mark the other clients commands as preempted, starting from pTmp */ + RF_preemptClient(pTmp, pCmd->ePri); + } + + + /* Step 2-3 */ + if ((schStatus == RF_ScheduleStatusPreempt) || schStatus == RF_ScheduleStatusNone) + { + List_put(&RF_cmdQ.pPend, (List_Elem*) pCmd); + } + + /* Return command with the method we used to schedule the command. + Might be RF_SCH_ERROR if none of the above applied. */ + return(schStatus); +} + +/* + * Execute RF power down sequence. + * + * Input: none + * Return: none + */ +static void RF_corePowerDown(void) +{ + /* Local variables to calculate active time in current window. */ + uint32_t deltaTimeInUs = 0; + + /* Disable all CPE and HW interrupts as we are about to power down the core. + Clearing is not important as content will be lost anyway. */ + RFCCpeIntDisable(~0); + RFCHwIntDisable(~0); + + /* Remap HWI to the startup function (preparing for next wake up) */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0PowerFsm, (uintptr_t)NULL); + + /* Set VCOLDO reference */ + RFCAdi3VcoLdoVoltageMode(false); + + /* Take wake up timestamp and the current timestamp */ + uint32_t rtcTimestampB = (uint32_t) AONRTCCurrent64BitValueGet(); + + /* Find the radio core active delta time since the last power up. */ + deltaTimeInUs = UDIFF(RF_rtcTimestampA, rtcTimestampB); + deltaTimeInUs >>= RF_RTC_CONV_TO_US_SHIFT; + + /* Accumulate the delta time with the previous active time windows. Avoid overflow. */ + RF_core.activeTimeUs = ADD(RF_core.activeTimeUs, deltaTimeInUs); + + /* Decide whether to send the CMD_SYNC_STOP_RAT command. If this is first power down (.init) or active time (activeTimeInUs) + is longer than the time that can cause maximum allowed error between RAT and RTC clocks. Yielding will automatically fulfill + the latter. */ + if (!(RF_core.init) || + (RF_core.activeTimeUs > (RF_errTolValInUs << RF_DEFAULT_COMB_XTAL_DRIFT_BITS_SHIFT))) + { + /* Stop and synchronize the RAT if it is running */ + if (RF_ratIsRunning()) + { + /* Setup RAT_SYNC command to follow powerdown. */ + RF_ratSyncCmd.stop.commandNo = CMD_SYNC_STOP_RAT; + RF_ratSyncCmd.stop.status = IDLE; + RF_ratSyncCmd.stop.condition.rule = COND_NEVER; + RF_ratSyncCmd.stop.startTrigger.triggerType = TRIG_NOW; + RF_ratSyncCmd.stop.pNextOp = NULL; + + /* Send RAT Stop command and synchronously wait until it run. */ + RF_dbellSubmitCmdAsync((uint32_t)&RF_ratSyncCmd.stop); + while (!(RF_ratSyncCmd.stop.status & RF_CMD_TERMINATED)); + } + + /* The RF core is now initialized and RAT is synchronized. */ + RF_core.init = true; + RF_core.activeTimeUs = 0; + } + + /* Turn off Synth */ + RFCSynthPowerDown(); + + /* Turn off the RF core by gating its clock. This is a quick way to have it shut off. */ + RFCClockDisable(); +} + +/*-------------- Power constraints internal functions ------------------------*/ + +/* + * Set RF power constraints. + * + * Input: src - RF_PowerConstraintSrc (Source: Queue or RAT) + * Return: none + */ +void RF_powerConstraintSet(RF_PowerConstraintSrc src) +{ + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Set constraint based on source */ + RF_powerConstraint |= src; + + /* Exit critical section */ + HwiP_restore(key); +} + +/* + * Release RF power constraints. + * + * Input: src - RF_PowerConstraintSrc (Source: Queue or RAT) + * Return: none + */ +void RF_powerConstraintRelease(RF_PowerConstraintSrc src) +{ + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Release this constraint. */ + RF_powerConstraint &= ~src; + + /* Check if all constraints are clear. */ + if (!(RF_powerConstraint & RF_PowerConstraintCmdQ)) + { + /* Initiate power down if the above criterion is met. + The RAT timer though might will prevent us to proceed. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventPowerDown); + } + + /* Exit critical section. */ + HwiP_restore(key); +} + +/* + * Get RF power constraints. + * + * Input: src - Mask of constraints we requesting + * Return: Bitwise-OR of the power constraints set and the input argument + */ +RF_PowerConstraintSrc RF_powerConstraintGet(RF_PowerConstraintSrc src) +{ + /* Set constraint based on source */ + return((RF_PowerConstraintSrc)(RF_powerConstraint & (uint8_t)src)); +} + +/* + * It calculates and returns the closest RF event in time if any. + * + * Calling context: Hwi, Swi + * + * Input: dispatchTime - pointer to a container where the calculated time can be returned + * Return: ticks - If command is far away in future. + * 0 - If command is too close and should be scheduled now. + */ +static bool RF_calculateDispatchTime(uint32_t* dispatchTimeClockTicks) +{ + /* Local variables. */ + uint32_t deltaTimeCmdClockTicks; + uint32_t deltaTimeRatClockTicks; + + /* Initialize return value. */ + *dispatchTimeClockTicks = 0; + + /* Calculate the timestamp of the next command in the command queue. */ + bool validCmdTime = RF_cmdDispatchTime(&deltaTimeCmdClockTicks); + + /* If any of the RAT timers expire before the command should be dispatched, + reprogram the power up clock to the RAT event instead. */ + bool validRatTime = RF_ratDispatchTime(&deltaTimeRatClockTicks); + + if (validCmdTime && validRatTime) + { + /* Determine if command execution or RAT event comes first. */ + *dispatchTimeClockTicks = MIN(deltaTimeCmdClockTicks, deltaTimeRatClockTicks); + } + else if (validCmdTime) + { + /* Command queue determines the next event. */ + *dispatchTimeClockTicks = deltaTimeCmdClockTicks; + } + else if (validRatTime) + { + /* RAT timer determines the next event. */ + *dispatchTimeClockTicks = deltaTimeRatClockTicks; + } + + /* If any of them valid, return with true indicating a valid dispatch time. */ + return(validCmdTime || validRatTime); +} + +/* + * Dispatch the closest event generated either by a command or the RAT timer. + * If the RF core is powered, it triggs the HWI to execute the dispatcher. + * If the RF core is not powered, it decides if it should be powered ON immediately, or + * the execution can be deferred to a later timestamp. In the latter case, the RTC is used to keep + * track of proper timing. + * + * Input: none + * Return: status - Status of the command execution. + * + */ +static void RF_dispatchNextEvent(void) +{ + if (RF_core.status == RF_CoreStatusActive) + { + /* Kick the HWI to dispatch the next pending event. */ + HwiP_post(INT_RFC_CPE_0); + } + else if ((RF_core.status == RF_CoreStatusPoweringUp) || + (RF_core.status == RF_CoreStatusPhySwitching)) + { + /* Do nothing. We will dispatch the next event at the end + of power-up/phy-switching sequence naturally. */ + } + else + { + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Calculate dispatch time. */ + uint32_t dispatchTimeClockTicks; + bool validTime = RF_calculateDispatchTime(&dispatchTimeClockTicks); + + if (validTime) + { + /* Decide whether the command should be dispatched. */ + if (dispatchTimeClockTicks) + { + /* Dispatch command in the future. */ + RF_restartClockTimeout(&RF_clkPowerUpObj, dispatchTimeClockTicks); + } + else + { + /* Dispatch the event immediately. Clock is not needed anymore. */ + ClockP_stop(&RF_clkPowerUpObj); + + /* Initiate powering up the RF core. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventWakeup); + } + } + else + { + /* There is no event to be dispatched. */ + ClockP_stop(&RF_clkPowerUpObj); + } + + /* Exit critical section. */ + HwiP_restore(key); + } +} + +/* + * Update the cached FS command within the client's context. + * + * Calling context: Hwi, Swi + * + * Input: pCmd - Pointer to radio operation command. + * Return: none + */ +static void RF_cacheFsCmd(RF_Cmd* pCmd) +{ + /* Upper limit of the number of operations in a chain */ + uint8_t nCmdChainMax = RF_MAX_CHAIN_CMD_LEN; + + /* Traverse the chain */ + RF_Op* pOp = pCmd->pOp; + while (pOp && nCmdChainMax) + { + /* If the operation is a CMD_FS or CMD_FS_OFF */ + if ((pOp->commandNo == CMD_FS) || (pOp->commandNo == CMD_FS_OFF)) + { + /* Create a copy of the first CMD_FS command (or CMD_FS_OFF) for later power up */ + memcpy(&pCmd->pClient->state.mode_state.cmdFs, pOp, sizeof(pCmd->pClient->state.mode_state.cmdFs)); + break; + } + + /* Step the chain */ + pOp = pOp->pNextOp; + + /* Avoid infinit loop (in case of closed loops) */ + --nCmdChainMax; + } +} + +/* + * Find the last radio operation within a chain. + * + * Calling context: Task, Hwi, Swi + * + * Input: pOp - Pointer to the first radio operation. + * Return: RF_Op* - Pointer to the last radio operation. + */ +static RF_Op* RF_findEndOfChain(RF_Op* pOp) +{ + /* Upper limit of the number of operations in a chain. */ + uint8_t nCmdChainMax = RF_MAX_CHAIN_CMD_LEN; + + /* Traverse the chain. */ + while (pOp->pNextOp && nCmdChainMax) + { + /* Step the chain. */ + pOp = pOp->pNextOp; + + /* Avoid infinit loop (in case of closed loops). */ + --nCmdChainMax; + } + + /* Return with the last radio operation. */ + return(pOp); +} + +/* + * Verify if the given command is a setup command. + * + * Calling context: Hwi, Swi + * + * Input: pOp - Pointer to radio operation. + * Return: true - The given command is a setup command. + * false - The given command is not a setup command. + */ +static bool RF_isRadioSetup(RF_Op* pOp) +{ + /* Verify the command ID against the known setup commands. */ + switch(pOp->commandNo) + { + case (CMD_RADIO_SETUP): + case (CMD_BLE5_RADIO_SETUP): + case (CMD_PROP_RADIO_SETUP): + case (CMD_PROP_RADIO_DIV_SETUP): + /* The given radio operation is indead a setup command. */ + return(true); + default: + /* Do nothing. */ + return(false); + } +} + +/* + * Ensure that the setup command is properly initialized. + * + * Input: handle - Pointer to the client. + * Return: None + */ +static void RF_initRadioSetup(RF_Handle handle) +{ + /* Local variables. */ + bool update = handle->clientConfig.bUpdateSetup; + + /* Decode the setup command. */ + RF_RadioSetup* radioSetup = handle->clientConfig.pRadioSetup; + radioSetup->common.status = IDLE; + + /* Adjust the setup command if needed. */ + switch (radioSetup->common.commandNo) + { + case (CMD_RADIO_SETUP): + case (CMD_BLE5_RADIO_SETUP): + /* Configure that the frequency synthetizer should be powered up */ + radioSetup->common.config.bNoFsPowerUp = 0; + + /* If requested, also change the analog configuration during power up */ + if (update) + { + radioSetup->common.config.analogCfgMode = RF_SETUP_ANALOGCFG_UPDATE; + } + else + { + radioSetup->common.config.analogCfgMode = RF_SETUP_ANALOGCFG_NOUPDATE; + } + break; + + case (CMD_PROP_RADIO_SETUP): + case (CMD_PROP_RADIO_DIV_SETUP): + /* Configure that the frequency synthetizer should be powered ON */ + radioSetup->prop.config.bNoFsPowerUp = 0; + + /* If requested, also change the analog configuration during power up */ + if (update) + { + radioSetup->prop.config.analogCfgMode = RF_SETUP_ANALOGCFG_UPDATE; + } + else + { + radioSetup->prop.config.analogCfgMode = RF_SETUP_ANALOGCFG_NOUPDATE; + } + break; + default: + break; + } + + /* Clear the update request flag as it was handled by now. */ + handle->clientConfig.bUpdateSetup = false; +} + + +/* + * Submit the pending command to the RF Core. + * + * Input: none + * Return: none + */ +static void RF_dispatchNextCmd(void) +{ + /* First element in the pend queue */ + bool doDispatchNow = false; + RF_Cmd* pNextCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + /* Decide whether to schedule the next command or not. */ + if (pNextCmd) + { + if (RF_cmdQ.pCurrCmdFg) + { + ; /* Do nothing. */ + } + else if (RF_cmdQ.pCurrCmdBg) + { + if ((RF_cmdQ.pCurrCmdBg->pClient == pNextCmd->pClient) + && (pNextCmd->flags & RF_CMD_FG_CMD_FLAG)) + { + /* Be sure that the background command is started within the RF core. + This is to avoid race condition. */ + while ((RF_cmdQ.pCurrCmdBg->pOp->status == IDLE) || + (RF_cmdQ.pCurrCmdBg->pOp->status == PENDING)); + + /* Try to execute the foreground command. */ + doDispatchNow = true; + } + } + else + { + /* The RF core is available, dispatch the next command. */ + doDispatchNow = true; + } + } + else + { + /* There is nothing to do, serve the last callbacks. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventLastCommandDone); + } + + /* We need to evaluate and handle the next command. */ + if (doDispatchNow) + { + if (pNextCmd->pClient != RF_currClient) + { + /* We need to change radio client, signal to FSM. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventInitChangePhy); + } + else + { + /* Calculate the timestamp of the next command in the command queue. */ + uint32_t dispatchTimeClockTicks; + bool validTime = RF_cmdDispatchTime(&dispatchTimeClockTicks); + + /* Dispatch command in the future */ + if (validTime && dispatchTimeClockTicks && !RF_cmdQ.pCurrCmdBg && !RF_cmdQ.pCurrCmdFg) + { + /* Command sufficiently far into future that it shouldn't be dispatched yet + Release RF power constraint and potentially power down radio */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + } + else + { + /* Set power constraint on the command queue, since there is now a running command. */ + RF_powerConstraintSet(RF_PowerConstraintCmdQ); + + /* Move the command from the pending queue to the current command. */ + if (pNextCmd->flags & RF_CMD_FG_CMD_FLAG) + { + RF_cmdQ.pCurrCmdFg = (RF_Cmd*)List_get(&RF_cmdQ.pPend); + } + else + { + RF_cmdQ.pCurrCmdBg = (RF_Cmd*)List_get(&RF_cmdQ.pPend); + } + + /* Clear and enable the requested interrupt sources of the command. */ + RFCCpeIntClear((uint32_t) (pNextCmd->bmEvent)); + RFCCpeIntEnable((uint32_t)(pNextCmd->bmEvent)); + RFCHwIntClear((uint32_t) (pNextCmd->bmEvent >> RF_SHIFT_32_BITS)); + RFCHwIntEnable((uint32_t) (pNextCmd->bmEvent >> RF_SHIFT_32_BITS)); + + /* Decode the radio operation itself. */ + RF_Op* pOp = (RF_Op*)pNextCmd->pOp; + + /* Send the radio operation to the RF core. */ + RFCDoorbellSendTo((uint32_t)pOp); + + /* If the command is a new setup command, notify the board file. */ + if (RF_isRadioSetup(pOp)) + { + /* Invoke the global callback if the setup command changed. This is needed to + adjust the front-end configuration according to the new PHY. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioSetup, (void*)pOp); + } + + /* Check the pending queue for any foreground command (IEEE 15.4 mode) */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventRunScheduler); + } + } + } +} + +/* + * Check if there was an error with the synth while running CMD_FS + * error callback is not issued in this function. + * + * Input: none + * Return: true - If there was an error. + * false - If there was no error. + */ +static bool RF_checkCmdFsError(void) +{ + /* Take the handle of the current client */ + RF_Handle pObj = RF_currClient; + + /* Find the FS command stored in the context of the client */ + RF_Op *tmp1 = (RF_Op*)&pObj->clientConfig.pRadioSetup->prop; + while (tmp1->pNextOp && tmp1->pNextOp != (RF_Op*)&pObj->state.mode_state.cmdFs) + { + tmp1 = tmp1->pNextOp; + } + + /* Evaluate if the FS command succeeded */ + if ((tmp1->condition.rule == COND_ALWAYS) && + (pObj->state.mode_state.cmdFs.status == ERROR_SYNTH_PROG)) + { + /* CMD_FS completed with error so return true */ + return(true); + } + else + { + /* There is no synth error so return false */ + return(false); + } +} + +/* + * RF HW ISR when radio is active. + * + * Input: a - Not used. + * Return: none + */ +static void RF_hwiHw(uintptr_t a) +{ + /* Prepare a direct command */ + RF_Cmd* pCmd = RF_cmdQ.pCurrCmdBg; + + /* Read and clear the interrupt flags */ + uint32_t rfchwifg = RFCHwIntGetAndClear(RF_HW_INT_CPE_MASK | RF_HW_INT_RAT_CH_MASK); + uint32_t rfchwien = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) & RF_HW_INT_CPE_MASK; + uint32_t rathwien = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) & RF_HW_INT_RAT_CH_MASK; + + if (rfchwifg & rfchwien) + { + /* Post SWI_FSM if MODEM_SOFT event occured and the interrupt was enabled */ + if (pCmd) + { + /* Store the command which callback need to be served */ + RF_cmdQ.pCurrCmdCb = pCmd; + + /* Decode the event numeber. */ + RF_EventMask events = ((RF_EventMask)(rfchwifg & rfchwien) << RF_SHIFT_32_BITS); + + /* Store the events within the context of the command for the callback. */ + RF_cmdStoreEvents(pCmd, events); + + /* Trig the state machine to handle this event */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventCpeInt); + } + } + + /* Post the SWI_HW if any RAT channel event occured */ + if (rfchwifg & rathwien) + { + /* Store the channel which cause the interrupt */ + RF_ratModule.pendingInt |= (rfchwifg & rathwien) >> RFC_DBELL_RFHWIFG_RATCH5_BITN; + + /* Post the swi to handle its callback */ + SwiP_or(&RF_swiHwObj, 0); + } +} + +/* + * Software interrupt handler which servers Radio Timer (RAT) related events. + * + * Input: a - Generic argument. Not used. + * b - Generic argument. Not used. + * Return: none + */ +static void RF_swiHw(uintptr_t a, uintptr_t b) +{ + /* Local variable */ + bool error = false; + + /* If the interrupt was trigged due to one of the RAT channels. */ + if (RF_ratModule.pendingInt) + { + /* Process lower channel first and allow multiple interrupt flags to be processed sequentially. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + if (RF_ratModule.pendingInt & (RF_RAT_INTERRUPT_BASE_INDEX << i)) + { + /* If there is also a bit indicating that the interrupt is due to an error. */ + if (RF_ratModule.pendingInt & (RF_RAT_ERROR_BASE_INDEX << i)) + { + error = true; + } + + /* Enter critical section. */ + uint32_t key= HwiP_disable(); + + /* Atomic read-modify-write instruction of the interrupt flags. + Knowing that this is the only place when such a flag can be cleared, it is safe to only guard this + operation. Additional flags (which have been raised in the meantime) will be reserved and served in the + next iteration. */ + RF_ratModule.pendingInt &= ~((RF_RAT_INTERRUPT_BASE_INDEX | RF_RAT_ERROR_BASE_INDEX) << i); + + /* Exit critical section. */ + HwiP_restore(key); + + /* Convert the channel index to a pointer of rat configuration. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* Serve the interrupt if it is from an active channel. This is to avoid decoding function + pointers from invalid containers due to fantom interrupts. */ + if (ratCh && ratCh->status) + { + /* Read the channel counter from the RAT timer. In capture mode this is the captured value, + in compare mode this is the compare timestamp.*/ + uint32_t compareCaptureValue = RF_ratGetChannelValue(ratCh->handle); + + /* Temporarily store the callback handler and the channel offset. + This is necessary in order to be able to free and reallocate the + same channel within the context of the callback itself. */ + RF_Handle ratClient = (RF_Handle) ratCh->pClient; + RF_RatHandle ratHandle = (RF_CmdHandle) ratCh->handle; + RF_RatCallback ratCallback = (RF_RatCallback) ratCh->pCb; + + /* Only free the channel if it is NOT in repeated capture mode, or an error occured. */ + if (error || !(ratCh->mode == RF_RatModeCapture) || !(ratCh->chCmd & RF_RAT_CAPTURE_REPEAT_MODE)) + { + /* Free RAT channel. If this is the last channel, it might delay with 1 LF edge to + calculate the next wake up event. */ + RF_ratFreeChannel(ratCh); + } + + /* Serve the user callback with Error or Compare/Capture Event. */ + if (error) + { + ratCallback(ratClient, ratHandle, RF_EventError, 0); + } + else + { + ratCallback(ratClient, ratHandle, RF_EventRatCh, compareCaptureValue); + } + } + + /* Only serve one channel at a time. */ + break; + } + } + } + + /* Repost the SWI again if multiple interrupt flags are still set. */ + if (RF_ratModule.pendingInt) + { + SwiP_or(&RF_swiHwObj, 0); + } +} + +/* + * RF CPE0 ISR when radio is active. Assume that all IRQs relevant to command + * dispatcher are mapped here. Furthermore, assume that there is no need for + * critical sections here (i.e. that this ISR has higher priority than + * any HWI calling a RF API function or that HWIs can't call the RF API). + * + * Input: a - Not used. + * Return: none + */ +static void RF_hwiCpe0Active(uintptr_t a) +{ + /* Local variables. */ + RF_Cmd* volatile* ppActiveCmd = NULL; + RF_Cmd* volatile* activeCmd[2] = {&RF_cmdQ.pCurrCmdBg, &RF_cmdQ.pCurrCmdFg}; + uint32_t rfcpeifgMask = 0; + uint32_t rfcpeifg = 0; + uint32_t nextEvent = 0; + + /* Iterate through the possible active commands. */ + uint32_t i; + for(i = 0; i < sizeof(activeCmd)/sizeof(uint32_t); i++) + { + /* Decode the active command. */ + ppActiveCmd = activeCmd[i]; + + /* If there was a command running (handles both foreground and background context). */ + if (*ppActiveCmd) + { + /* Decode the events the active command subscribed to. */ + rfcpeifgMask = (*ppActiveCmd)->bmEvent; + + /* Read the interrupt flags which belong to the active command (including the mandatory termination events). */ + rfcpeifg = RFCCpeIntGetAndClear(rfcpeifgMask); + + /* Save the events happened and to be passed to the callback. */ + RF_cmdStoreEvents((*ppActiveCmd), rfcpeifg); + + /* Look for termination events. */ + if (rfcpeifg & (RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M | RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M)) + { + /* Disable interrupt sources which were subsribed by the command. Since the LAST_CMD_DONE is + is shared with the state machine, it cannot be disabled. */ + RFCCpeIntDisable((uint32_t)((*ppActiveCmd)->bmEvent & ~RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M)); + RFCHwIntDisable((uint32_t) ((*ppActiveCmd)->bmEvent >> RF_SHIFT_32_BITS)); + + /* Move active command to done queue. */ + List_put(&RF_cmdQ.pDone, (List_Elem*)(*ppActiveCmd)); + + /* Retire the command, it is not running anymore. */ + (*ppActiveCmd) = NULL; + + /* We will invoke the callback and deallocate the command. */ + nextEvent |= RF_FsmEventLastCommandDone; + } + else if (rfcpeifg) + { + /* The interrupt is just an ordinary event without termination. */ + RF_cmdQ.pCurrCmdCb = (*ppActiveCmd); + + /* We will just invoke the callback. */ + nextEvent |= RF_FsmEventCpeInt; + } + } + } + + /* Post SWI to handle registered callbacks if there is any. */ + if (nextEvent) + { + SwiP_or(&RF_swiFsmObj, nextEvent); + } + + /* Restart pending rat channels. */ + RF_ratRestartChannels(); + + /* Dispatch the next pending command if exists. */ + RF_dispatchNextCmd(); +} + +/* + * Clock callback due to inactivity timeout. + * + * Input: pObj - Not used. + * Return: none + */ +static void RF_clkInactivityCallback(uintptr_t a) +{ + /* If there are no pending commands in the queue */ + if (RF_cmdQ.nSeqPost == RF_cmdQ.nSeqDone) + { + /* Release the constraint on the command queue and if nothing prevents, power down the radio */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + } +} + +/* + * Clock callback due to request access timeout. + * + * Input: a - Not used. + * Return: none + */ +static void RF_clkReqAccess(uintptr_t a) +{ + RF_issueRadioFreeCb(RF_RADIOFREECB_REQACCESS_FLAG | + RF_RADIOFREECB_PREEMPT_FLAG | + RF_RADIOFREECB_CMDREJECT_FLAG); +} + +/* + * Callback used to post semaphore for runCmd() and pendCmd(). + * + * Input: h - Handle to the client. + * ch - Handle to the command which callback to be invoked. + * e - Events causing the function call. + * Return: none + */ +static void RF_syncCb(RF_Handle h, RF_CmdHandle ch, RF_EventMask e) +{ + /* Local variables */ + RF_Cmd* pCmd; + + /* If there is a user callback provided. */ + if (h->state.pCbSync) + { + /* Invoke the user callback with the events fired. */ + ((RF_Callback)h->state.pCbSync)(h, ch, e); + } + + /* Mask the possible causes of releasing the semaphore */ + RF_EventMask maskedEvents = (e & h->state.eventSync); + + /* Release the semaphore on any of the reasons: last command done, + subscribed event happened, last FG command is done in IEEE mode */ + if (maskedEvents) + { + /* Find the command. We do it here within the SWI context. */ + pCmd = RF_cmdGet(h, ch, RF_CMD_ALLOC_FLAG); + + /* Store the events in the context of the client */ + h->state.unpendCause = maskedEvents; + + /* Find the command. We do it here within the SWI context. */ + if (pCmd) + { + /* Clear the handled past events so it is possible to pend again */ + pCmd->pastifg &= ~h->state.unpendCause; + + /* Exhange the callback function: use the user callback from this point */ + pCmd->pCb = (RF_Callback)h->state.pCbSync; + } + + /* Clear temporary storage of user callback (it was restored and served at this point) */ + h->state.pCbSync = NULL; + + /* Post the semaphore to release the RF_pendCmd() */ + SemaphoreP_post(&h->state.semSync); + } +} + +/* + * Invoke the global callback registered through the RFCC26XX_hwAttrs. + * + * Input: e - Events causing the function call. + * Return: none + */ +static void RF_invokeGlobalCallback(RF_GlobalEvent event, void* arg) +{ + /* Decode the global callback and it's mask from the board file. */ + RF_GlobalCallback callback = RFCC26XX_hwAttrs.globalCallback; + RF_GlobalEventMask eventMask = RFCC26XX_hwAttrs.globalEventMask; + + /* If the board has subscribed to this event, invoke the callback. */ + if (callback && (eventMask & event)) + { + callback(RF_currClient, event, arg); + } +} + +/* + * Default callback function. + * + * Input: h - Handle to the client. + * ch - Handle to the command which callback to be invoked. + * e - Events causing the function call. + * Return: none + */ +static void RF_defaultCallback(RF_Handle h, RF_CmdHandle ch, RF_EventMask e) +{ + /* Do nothing */; +} + +/*-------------- RF powerup/powerdown FSM functions ---------------*/ + +/* + * The SWI handler for FSM events. + * + * Input: a0 - Not used. + * a1 - Not used. + * Return: none + */ +static void RF_swiFsm(uintptr_t a0, uintptr_t a1) +{ + RF_core.fxn(RF_currClient, (RF_FsmEvent)SwiP_getTrigger()); +} + +/* + * Clock callback called upon powerup. + * + * Input: a - Not used. + * Return: none + */ +static void RF_clkPowerUp(uintptr_t a) +{ + if (RF_core.fxn == RF_fsmActiveState) + { + /* Dispatch the next RF core event. */ + RF_dispatchNextEvent(); + } + else + { + /* Trigger FSM SWI to start the wake up sequence of the radio. + This is important when we poll the XOSC_HF. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventWakeup); + } +} + +/* + * RF CPE0 ISR during FSM powerup/powerdown. + * + * Input: a0 - Not used. + * Return: none + */ +static void RF_hwiCpe0PowerFsm(uintptr_t a0) +{ + /* Read all IRQ flags in doorbell and then clear them */ + uint32_t rfcpeifg = RFCCpeIntGetAndClear(RF_CPE0_INT_MASK); + + /* If the radio is active */ + if (RF_core.fxn == RF_fsmActiveState) + { + /* Change HWI handler to the correct one */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0Active, (uintptr_t)NULL); + + /* Mark radio and client as being active */ + RF_core.status = RF_CoreStatusActive; + + /* No synth error */ + if (!RF_checkCmdFsError()) + { + /* Restart pending rat channels. */ + RF_ratRestartChannels(); + + /* Dispatch the next command */ + RF_dispatchNextCmd(); + } + } + + /* Handle special events as boot, etc */ + if (rfcpeifg & (RFC_DBELL_RFCPEIFG_BOOT_DONE_M | RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M)) + { + SwiP_or(&RF_swiFsmObj, RF_FsmEventPowerStep); + } +} + +/* + * RF CPE0 ISR during Change PHY switching. + * + * Input: a0 - Not used. + * Return: none + */ +static void RF_hwiCpe0ChangePhy(uintptr_t a0) +{ + /* Clear all IRQ flags in doorbell and then clear them */ + uint32_t rfcpeifg = RFCCpeIntGetAndClear(RF_CPE0_INT_MASK); + + if (rfcpeifg & IRQ_LAST_COMMAND_DONE) + { + /* Proceed to the second phase of the phy switching process */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventFinishChangePhy); + } +} + +/*-------------- Power management state functions ---------------*/ +/* + * Handles RF Core patching for CPE, MCE, RFE (if required) in setup state during power-up. + * + * Input: mode - RF_PHY_BOOTUP_MODE: First boot of the RF core. + * - RF_PHY_SWITCHING_MODE: Switching between two phys. + * Return: none + */ +static void RF_applyRfCorePatch(bool mode) +{ + /* Local reference to the patches. */ + void (*cpePatchFxn)(void) = RF_currClient->clientConfig.pRfMode->cpePatchFxn; + void (*mcePatchFxn)(void) = RF_currClient->clientConfig.pRfMode->mcePatchFxn; + void (*rfePatchFxn)(void) = RF_currClient->clientConfig.pRfMode->rfePatchFxn; + + if (mode == RF_PHY_SWITCHING_MODE) + { + /* If patches are provided, enable RFE and MCE clocks. */ + if ((mcePatchFxn != NULL) || (rfePatchFxn != NULL)) + { + RF_dbellSubmitCmdAsync((uint32_t)CMDR_DIR_CMD_2BYTE(RF_CMD0, RFC_PWR_PWMCLKEN_MDMRAM | RFC_PWR_PWMCLKEN_RFERAM)); + } + + /* Clear the previous patch. */ + if (cpePatchFxn != NULL) + { + RFCCpePatchReset(); + } + } + + /* Load the patches if relevant for this phy. */ + if (cpePatchFxn != NULL) + { + cpePatchFxn(); + } + + if ((mcePatchFxn != NULL) || (rfePatchFxn != NULL)) + { + /* Wait for clocks to be turned ON */ + RF_dbellSyncOnAck(); + + /* Patch MCE if relevant */ + if (mcePatchFxn != NULL) + { + mcePatchFxn(); + } + + /* Patch RFE if relevant */ + if (rfePatchFxn != NULL) + { + rfePatchFxn(); + } + + /* Turn off additional clocks */ + RFCDoorbellSendTo(CMDR_DIR_CMD_2BYTE(RF_CMD0, 0)); + } +} + +/* + * Arms the inactivity timer and hence postpones the decision whether + * power management shall take place or not. + * + * Input: none + * Return: none + */ +static void RF_setInactivityTimeout(void) +{ + /* Local variables to be used to find the correct timeout value. */ + uint32_t inactivityTimeUsA = 0; + uint32_t inactivityTimeUsB = 0; + RF_Handle handleA = RF_Sch.clientHnd[0]; + RF_Handle handleB = RF_Sch.clientHnd[1]; + + /* Issue radio free callback after pre-emption if required */ + uint8_t tmp = RF_RADIOFREECB_PREEMPT_FLAG | RF_RADIOFREECB_CMDREJECT_FLAG; + + /* If the radio was yielded, add the flag */ + if (RF_currClient->state.bYielded) + { + tmp |= RF_RADIOFREECB_REQACCESS_FLAG; + } + + /* Call the radio free callback */ + RF_issueRadioFreeCb(tmp); + + if (handleA) + { + if (handleA->state.bYielded == false) + { + inactivityTimeUsA = handleA->clientConfig.nInactivityTimeout; + } + handleA->state.bYielded = false; + } + + if (handleB) + { + if (handleB->state.bYielded == false) + { + inactivityTimeUsB = handleB->clientConfig.nInactivityTimeout; + } + handleB->state.bYielded = false; + } + + /* Set the inactivity time to the max between the two clients */ + uint32_t inactivityTimeUs = MAX(inactivityTimeUsA, inactivityTimeUsB); + + /* If immediate power down is reuqested */ + if (inactivityTimeUs == SemaphoreP_NO_WAIT) + { + /* We can powerdown immediately */ + RF_clkInactivityCallback((uintptr_t)NULL); + } + else if (inactivityTimeUs != SemaphoreP_WAIT_FOREVER) + { + /* Reprogram and start inactivity timer */ + RF_restartClockTimeout(&RF_clkInactivityObj, inactivityTimeUs/ClockP_tickPeriod); + } +} + +/* + * Handle callback to client for RF_EventLastCmdDone and issue radio free callback if required. + * + * Input: none + * Return: none + */ +static void RF_radioOpDoneCb(void) +{ + /* Serve the first entry in the done queue */ + RF_Cmd* pCmd = (RF_Cmd*)List_head(&RF_cmdQ.pDone); + + /* Radio command done */ + if (pCmd) + { + /* Update implicit radio state (chained FS command if any) */ + RF_cacheFsCmd(pCmd); + + /* Read and clear the events */ + RF_EventMask events = pCmd->rfifg; + pCmd->rfifg = 0; + + /* Issue callback, free container and dequeue */ + if (pCmd->pCb) + { + /* If any of the cancel events are set, mask out the other events. */ + RF_EventMask exclusiveEvents = (RF_EventCmdCancelled + | RF_EventCmdAborted + | RF_EventCmdStopped + | RF_EventCmdPreempted); + + /* Mask out the other events if any of the above is set. */ + if (events & exclusiveEvents) + { + events &= exclusiveEvents; + } + + /* Invoke the use callback */ + pCmd->pCb(pCmd->pClient, pCmd->ch, events); + } + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Update num of radio command done */ + RF_cmdQ.nSeqDone = (RF_cmdQ.nSeqDone+1) & N_CMD_MODMASK; + + /* Commmand completed reset command flags */ + pCmd->flags = 0; + + /* Command completed, free command queue container */ + List_get(&RF_cmdQ.pDone); + + /* Exit critical section */ + HwiP_restore(key); + + /* Check if there are any more pending commands */ + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + RF_setInactivityTimeout(); + } + } +} + +/* + * Verify if reconiguring or powering down the radio is allowed. + * + * Input: none + * Return: none + */ +static bool RF_isStateTransitionAllowed(void) +{ + /* Local variable. */ + bool status = false; + + /* If we are not performing RF core state changes. */ + if (RF_core.status == RF_CoreStatusActive) + { + if(RF_cmdQ.pCurrCmdBg == NULL && + RF_cmdQ.pCurrCmdFg == NULL) + { + status = true; + } + } + + /* Return with the decision. */ + return(status); +} + +/* + * RF state machine function during power up state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmPowerUpState(RF_Object *pObj, RF_FsmEvent e) +{ + /* Note: pObj is NULL in this state */ + if (e & RF_FsmEventLastCommandDone) + { + /* Invoke the user provided callback function */ + RF_radioOpDoneCb(); + + /* Retrig the SWI if there are more commands in the done queue. */ + if (List_head(&RF_cmdQ.pDone)) + { + /* Trigger self if there are more commands in callback queue */ + SwiP_or(&RF_swiFsmObj, (e | RF_FsmEventLastCommandDone)); + } + else + { + /* We've handled this event now */ + e &= ~RF_FsmEventLastCommandDone; + + /* Schedule the next event based on the state of the command queue + and the RAT module. */ + RF_dispatchNextEvent(); + } + } + else if (e & RF_FsmEventWakeup) + { + /* Store the current RTC tick for nPowerUpDuration calculation */ + RF_rtcTimestampA = AONRTCCurrent64BitValueGet(); + + /* Set current client from first command in command queue */ + RF_Cmd* pNextCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + if (pNextCmd) + { + RF_Object* pNextClient = pNextCmd->pClient; + + /* If the next command belongs to another client, initiate PHY switching */ + if ((RF_currClient) && (RF_currClient != pNextClient)) + { + /* Invoke the client switch callback if it was provided */ + if (pNextClient->clientConfig.nClientEventMask & RF_ClientEventSwitchClientEntered) + { + RF_ClientCallback pClientEventCb = (RF_ClientCallback)pNextClient->clientConfig.pClientEventCb; + pClientEventCb(pNextClient, RF_ClientEventSwitchClientEntered, NULL); + } + + /* Due to client switching, update the analogCfg field of setup command. */ + pNextClient->clientConfig.bUpdateSetup = true; + } + + /* Set the current client to be the next client */ + RF_currClient = pNextClient; + } + + /* Set the RF mode in the PRCM register (RF_open already verified that it is valid) */ + HWREG(PRCM_BASE + PRCM_O_RFCMODESEL) = RF_currClient->clientConfig.pRfMode->rfMode; + + /* Notiy the power driver that Standby is not allowed and RF core need to be powered */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + Power_setDependency(PowerCC26XX_DOMAIN_RFCORE); + + /* Indicate that the power-up sequence is being started */ + RF_core.status = RF_CoreStatusPoweringUp; + + /* If the configuration on board level requires to set the dependency every time. */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == false) + { + Power_setDependency(PowerCC26XX_XOSC_HF); + } + + /* If there are RFE and MCE patches, turn on their clocks */ + if ((RF_currClient->clientConfig.pRfMode->mcePatchFxn != NULL) || + (RF_currClient->clientConfig.pRfMode->rfePatchFxn != NULL)) + { + RF_dbellSubmitCmdAsync((uint32_t)CMDR_DIR_CMD_2BYTE(RF_CMD0, RFC_PWR_PWMCLKEN_MDMRAM | RFC_PWR_PWMCLKEN_RFERAM)); + } + + /* Turn on the clock to the RF core. Registers can be accessed afterwards. */ + RFCClockEnable(); + + /* Reconfigure the CPE interrupt lines to a start up value on a controlled way. */ + RFCCpeIntDisable(RF_CPE0_INT_MASK); + RFCCpe0IntSelect(RF_CPE0_INT_MASK); + + /* Enable some of the interrupt sources. */ + RFCCpeIntEnable(RFC_DBELL_RFCPEIEN_BOOT_DONE_M + | RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M); + + /* Set the next state. */ + RF_core.fxn = RF_fsmSetupState; + + /* Enable interrupts: continue when boot is done */ + HwiP_enableInterrupt(INT_RFC_HW_COMB); + HwiP_enableInterrupt(INT_RFC_CPE_0); + } +} + +/* + * RF state machine function during setup state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmSetupState(RF_Object *pObj, RF_FsmEvent e) +{ + if (e & RF_FsmEventPowerStep) + { + /* Apply RF Core patches (if required) */ + RF_applyRfCorePatch(RF_PHY_BOOTUP_MODE); + + /* Initialize system bus request */ + RF_dbellSubmitCmdAsync((uint32_t)CMDR_DIR_CMD_1BYTE(CMD_BUS_REQUEST, 1)); + + /* Set VCOLDO reference to true */ + RFCAdi3VcoLdoVoltageMode(true); + + /* Configure the RAT_SYNC command which will follow SETUP command */ + RF_ratSyncCmd.start.commandNo = CMD_SYNC_START_RAT; + RF_ratSyncCmd.start.status = IDLE; + RF_ratSyncCmd.start.startTrigger.triggerType = TRIG_NOW; + RF_ratSyncCmd.start.pNextOp = NULL; + RF_ratSyncCmd.start.condition.rule = COND_NEVER; + + /* Init the content of setup command. */ + RF_initRadioSetup(pObj); + + /* Configure the SETUP command. */ + RF_RadioSetup* pRadioSetup = pObj->clientConfig.pRadioSetup; + + /* Search for specific commands in the command chain. */ + RF_Op* tmp = (RF_Op*)&pRadioSetup->prop; + while ((tmp->pNextOp) && (tmp->pNextOp->commandNo != CMD_SYNC_START_RAT) && + (tmp->pNextOp->commandNo != CMD_FS) && + (tmp->pNextOp->commandNo != CMD_FS_OFF)) + { + /* Trace to the end of chain */ + tmp = tmp->pNextOp; + } + + /* Add the CMD_RAT_SYNC to the end of chain */ + tmp->pNextOp = (RF_Op*)&RF_ratSyncCmd.start; + tmp->condition.rule = COND_ALWAYS; + + /* Setup FS command to follow SETUP command */ + RF_Cmd* pCmdFirstPend = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + if (pCmdFirstPend && ((pCmdFirstPend->pOp->commandNo == CMD_FS) || (pCmdFirstPend->pOp->commandNo == CMD_FS_OFF))) + { + /* First command is FS command so no need to chain an implicit FS command -> Reset nRtc1 */ + RF_rtcTimestampA = 0; + } + else + { + if (pObj->state.mode_state.cmdFs.commandNo) + { + /* Chain in the implicit FS command */ + rfc_CMD_FS_t* pOpFs = &pObj->state.mode_state.cmdFs; + pOpFs->status = IDLE; + pOpFs->pNextOp = NULL; + pOpFs->startTrigger.triggerType = TRIG_NOW; + pOpFs->condition.rule = COND_NEVER; + RF_ratSyncCmd.start.pNextOp = (RF_Op*)pOpFs; + RF_ratSyncCmd.start.condition.rule = COND_ALWAYS; + } + } + + /* Trim directly the radio register values based on the ID of setup command. */ + rfTrim_t rfTrim; + RFCRfTrimRead((rfc_radioOp_t*)pRadioSetup, (rfTrim_t*)&rfTrim); + RFCRfTrimSet((rfTrim_t*)&rfTrim); + + /* Make sure system bus request is done by now */ + RF_dbellSyncOnAck(); + + /* Set the next state. */ + RF_core.fxn = RF_fsmActiveState; + + /* Run the XOSC_HF switching if the pre-notify function setup the power + constraint PowerCC26XX_SWITCH_XOSC_HF_MANUALLY */ + if (RF_core.manualXoscHfSelect) + { + /* Wait until the XOSC_HF is stable */ + while (!PowerCC26XX_isStableXOSC_HF()); + + /* Invoke the XOSC_HF switching */ + PowerCC26XX_switchXOSC_HF(); + } + else if (OSCClockSourceGet(OSC_SRC_CLK_HF) != OSC_XOSC_HF) + { + /* If the XOSC_HF is not ready yet, only execute the first hal of the chain*/ + tmp->condition.rule = COND_NEVER; + + /* Next state: RF_fsmXOSCState (polling XOSC_HF)*/ + RF_core.fxn = RF_fsmXOSCState; + } + + /* Send the setup chain to the RF core */ + RF_dbellSubmitCmdAsync((uint32_t)pRadioSetup); + + /* Invoke the global callback. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioSetup, (void*)pRadioSetup); + } +} + +/* + * RF state machine function during XOSC state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmXOSCState(RF_Object *pObj, RF_FsmEvent e) +{ + if ((e & RF_FsmEventPowerStep) || (e & RF_FsmEventWakeup)) + { + /* If XOSC_HF is now ready */ + if (OSCClockSourceGet(OSC_SRC_CLK_HF) == OSC_XOSC_HF) + { + /* Next state: RF_fsmActiveState */ + RF_core.fxn = RF_fsmActiveState; + + /* Continue with the CMD_RAT_SYNC and the rest of the chain. */ + RF_dbellSubmitCmdAsync((uint32_t)&RF_ratSyncCmd.start); + } + else + { + /* Clock source not yet switched to XOSC_HF: schedule new polling */ + RF_restartClockTimeout(&RF_clkPowerUpObj, RF_XOSC_HF_SWITCH_CHECK_PERIOD_US/ClockP_tickPeriod); + } + } +} + +/* + * RF state machine function during active state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmActiveState(RF_Object *pObj, RF_FsmEvent e) +{ + volatile RF_Cmd* pCmd; + uint32_t rtcValTmp1; + uint32_t rtcValTmp2; + RF_EventMask events; + bool transitionAllowed; + uint32_t key; + + if (e & RF_FsmEventCpeInt) + { + /* Enter critical section */ + key = HwiP_disable(); + + /* Dereference the command which requested the callback*/ + pCmd = (RF_Cmd*)RF_cmdQ.pCurrCmdCb; + + /* If this is due to other event than LastCmdDone */ + if (pCmd && !(pCmd->rfifg & RF_TERMINATION_EVENT_MASK)) + { + /* Temporarily store the reason of callback */ + events = pCmd->rfifg; + + /* Clear the events which are handled here */ + pCmd->rfifg &= (~events); + + /* Exit critical section */ + HwiP_restore(key); + + /* Invoke the user callback if it is provided */ + if (pCmd->pCb && events) + { + pCmd->pCb(pCmd->pClient, pCmd->ch, events); + } + } + else + { + /* Exit critical section */ + HwiP_restore(key); + } + + /* We've handled this event now */ + e &= ~RF_FsmEventCpeInt; + } + /* Coming from powerup states */ + else if (e & RF_FsmEventPowerStep) + { + /* Enter critical section */ + key = HwiP_disable(); + + /* Update power up duration if coming from the clkPowerUpFxn. Skip the calcualtion + if coming from boot, since the LF clock is derived from RCOSC_HF without calibration. */ + if ((OSCClockSourceGet(OSC_SRC_CLK_LF) != OSC_RCOSC_HF) + && pObj->clientConfig.bMeasurePowerUpDuration + && RF_rtcTimestampA) + { + /* Temporary storage to be able to compare the new value to the old measurement */ + uint32_t prevPowerUpDuration = pObj->clientConfig.nPowerUpDuration; + + /* Take wake up timestamp and the current timestamp */ + rtcValTmp1 = (uint32_t) RF_rtcTimestampA; + rtcValTmp2 = (uint32_t) AONRTCCurrent64BitValueGet(); + + /* Calculate the difference of the timestamps and convert it to us units */ + pObj->clientConfig.nPowerUpDuration = UDIFF(rtcValTmp1, rtcValTmp2); + pObj->clientConfig.nPowerUpDuration >>= RF_RTC_CONV_TO_US_SHIFT; + + /* Low pass filter on power up durations less than in the previous cycle */ + if (prevPowerUpDuration > pObj->clientConfig.nPowerUpDuration) + { + /* Expect that the values are small and the calculation can be done in 32 bits */ + pObj->clientConfig.nPowerUpDuration = (prevPowerUpDuration + pObj->clientConfig.nPowerUpDuration)/2; + } + + /* Power up duration should be within certain upper and lower bounds */ + if ((pObj->clientConfig.nPowerUpDuration > RF_DEFAULT_POWER_UP_TIME) || + (pObj->clientConfig.nPowerUpDuration < RF_DEFAULT_MIN_POWER_UP_TIME)) + { + pObj->clientConfig.nPowerUpDuration = RF_DEFAULT_POWER_UP_TIME; + } + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Check the status of the CMD_FS, if it was sent (chained) to the setup command. + If it failed, return an error callback to the client. + The client can either resend the CMD_FS or ignore the error as per Errata on PG2.1 */ + if (RF_checkCmdFsError()) + { + /* Invoke the error callback: deault is do nothing */ + RF_Callback pErrCb = (RF_Callback)pObj->clientConfig.pErrCb; + pErrCb(pObj, RF_ERROR_CMDFS_SYNTH_PROG, RF_EventError); + + /* Check if there is pending command */ + if (List_head(&RF_cmdQ.pPend)) + { + /* Make sure the next pending command gets dispatched by issuing CPE0 IRQ */ + RF_dispatchNextEvent(); + } + else + { + /* No pending command */ + e |= RF_FsmEventLastCommandDone; + } + } + + /* Issue power up callback: the RF core is active */ + RF_Callback pPowerCb = (RF_Callback)pObj->clientConfig.pPowerCb; + pPowerCb(pObj, 0, RF_EventPowerUp); + + /* We've handled this event now */ + e &= ~RF_FsmEventPowerStep; + } + else if (e & RF_FsmEventLastCommandDone) + { + /* Issue radio operation done callback */ + RF_radioOpDoneCb(); + + /* Take the next command in the done queue if any left */ + if (List_empty(&RF_cmdQ.pDone)) + { + /* We've handled this event now */ + e &= ~RF_FsmEventLastCommandDone; + } + } + else if (e & RF_FsmEventInitChangePhy) + { + /* Enter critical section */ + key = HwiP_disable(); + + /* We only continue with phy switching if the RF core is still available. + This check is important since the queues might have changed in the meantime + of servicing the SWI. */ + transitionAllowed = RF_isStateTransitionAllowed(); + + /* Take the next command from the pend queue */ + RF_Cmd* pNextCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + if ((transitionAllowed == true) && (pNextCmd != NULL)) + { + /* Indicate that we are changing phy on the RF core. */ + RF_core.status = RF_CoreStatusPhySwitching; + + /* Change HWI handler while switching the phy */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0ChangePhy, (uintptr_t)NULL); + + /* Exit critical section */ + HwiP_restore(key); + + /* Stop inactivity clock of the current client if running */ + ClockP_stop(&RF_clkInactivityObj); + + /* Store the timestamp or measurement of the switching time */ + RF_rtcBeginSequence = AONRTCCurrent64BitValueGet(); + + /* Switch the current client to the commands client */ + RF_currClient = pNextCmd->pClient; + + /* Do client switch callback if provided */ + if (RF_currClient->clientConfig.nClientEventMask & RF_ClientEventSwitchClientEntered) + { + RF_ClientCallback pClientEventCb = (RF_ClientCallback)RF_currClient->clientConfig.pClientEventCb; + pClientEventCb(RF_currClient, RF_ClientEventSwitchClientEntered, NULL); + } + + /* Apply the new RF Core patch */ + RF_applyRfCorePatch(RF_PHY_SWITCHING_MODE); + + /* Request the system bus */ + RF_dbellSubmitCmdAsync((uint32_t)CMDR_DIR_CMD_1BYTE(CMD_BUS_REQUEST, 1)); + + /* Ensure that the analog domain is updated. */ + RF_currClient->clientConfig.bUpdateSetup = true; + + /* Ensure that the overrides are correct. */ + RF_initRadioSetup(RF_currClient); + + /* Configure the SETUP command */ + RF_RadioSetup* pRadioSetup = RF_currClient->clientConfig.pRadioSetup; + + /* Walk the chain and search or specific commands */ + RF_Op* tmp = (RF_Op*)&pRadioSetup->prop; + while ((tmp->pNextOp) && (tmp->pNextOp->commandNo != CMD_SYNC_START_RAT) && + (tmp->pNextOp->commandNo != CMD_FS) && + (tmp->pNextOp->commandNo != CMD_FS_OFF)) + { + tmp = tmp->pNextOp; + } + + /* Clear any of the found specific command */ + tmp->pNextOp = NULL; + tmp->condition.rule = COND_NEVER; + + /* Setup FS command to follow SETUP command */ + RF_Op* pOpFirstPend = pNextCmd->pOp; + if ((pOpFirstPend->commandNo == CMD_FS) || (pOpFirstPend->commandNo == CMD_FS_OFF)) + { + /* First command is FS command so no need to chain an implicit FS command -> reset nRtc2 */ + RF_rtcBeginSequence = 0; + } + else + { + if (RF_currClient->state.mode_state.cmdFs.commandNo) + { + /* Chain in the implicit FS command */ + rfc_CMD_FS_t* pOpFs = &RF_currClient->state.mode_state.cmdFs; + pOpFs->status = IDLE; + pOpFs->pNextOp = NULL; + pOpFs->startTrigger.triggerType = TRIG_NOW; + pOpFs->condition.rule = COND_NEVER; + tmp->pNextOp = (RF_Op*)pOpFs; + tmp->condition.rule = COND_ALWAYS; + } + } + + /* Trim directly the radio register values based on the ID of setup command */ + rfTrim_t rfTrim; + RFCRfTrimRead((rfc_radioOp_t*)pRadioSetup, (rfTrim_t*)&rfTrim); + RFCRfTrimSet((rfTrim_t*)&rfTrim); + + /* Make sure the system bus is available now */ + RF_dbellSyncOnAck(); + + /* Send the command chain */ + RF_dbellSubmitCmdAsync((uint32_t)pRadioSetup); + + /* Invoke the global callback. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioSetup, (void*)pRadioSetup); + } + else + { + /* Exit critical section */ + HwiP_restore(key); + } + + /* We've handled this event now */ + e &= ~RF_FsmEventInitChangePhy; + } + else if (e & RF_FsmEventFinishChangePhy) + { + /* Check the status of the CMD_FS, if it was sent (chained) to the setup command. + If it failed, invoke the error callback of the client. + The client can either resend the CMD_FS or ignore the error. */ + if (RF_checkCmdFsError()) + { + RF_Callback pErrCb = (RF_Callback)RF_currClient->clientConfig.pErrCb; + pErrCb(RF_currClient, RF_ERROR_CMDFS_SYNTH_PROG, RF_EventError); + } + + /* Only compute PHY switching time if rtcValTmp1 is not zero (was initialized) */ + if (RF_rtcBeginSequence) + { + /* Record the timestamp for switching time measurement. */ + rtcValTmp2 = (uint32_t) AONRTCCurrent64BitValueGet(); + + /* Calculate how long it took to reconfigure the radio to a new phy. */ + RF_currClient->clientConfig.nPhySwitchingDuration = UDIFF(RF_rtcBeginSequence, rtcValTmp2); + RF_currClient->clientConfig.nPhySwitchingDuration >>= RF_RTC_CONV_TO_US_SHIFT; + + /* Reset RF_rtcBeginSequence value at the end of phy switching sequence. */ + RF_rtcBeginSequence = 0; + } + + /* Change HWI handler */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0Active, (uintptr_t)NULL); + + /* Mark radio and client as being active */ + RF_core.status = RF_CoreStatusActive; + + /* Run the scheduler again. */ + RF_dispatchNextEvent(); + + /* We have handled this event now */ + e &= ~RF_FsmEventFinishChangePhy; + } + else if (e & RF_FsmEventPowerDown) + { + /* Enter critical section. */ + key = HwiP_disable(); + + /* Verify if the decision has not been reverted in the meantime. */ + transitionAllowed = RF_isStateTransitionAllowed(); + + /* If possible, put the running RAT channels into pending state allowing to + power down the RF core. */ + if (transitionAllowed) + { + transitionAllowed = RF_ratReleaseChannels(); + } + + /* If there is nothing prevent us to power down, proceed. */ + if (transitionAllowed) + { + /* Indicate that the RF core is being powered down from now */ + RF_core.status = RF_CoreStatusPoweringDown; + + /* Stop inactivity timer. */ + ClockP_stop(&RF_clkInactivityObj); + + /* Exit ritical setion. */ + HwiP_restore(key); + + /* Execute power down sequence of the RF core */ + RF_corePowerDown(); + + /* Invoke the global callback. At this point the clock of RF core is OFF, but the + power domain is still powered (hence the doorbell signals are still active. + We do the callback here to save some power. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioPowerDown, NULL); + + /* Notify the power driver that Standby mode is allowed and the RF core can be powered down. */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + Power_releaseDependency(PowerCC26XX_DOMAIN_RFCORE); + + /* Closing all handles */ + if (!RF_numClients) + { + /* Release the semaphore to be sure no one is pending on it */ + SemaphoreP_post(&RF_currClient->state.semSync); + } + + /* If there is no specific client request or the XOSC, release the dependency */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == false) + { + Power_releaseDependency(PowerCC26XX_XOSC_HF); + } + + /* Release constraint of switching XOSC_HF from the RF driver itself */ + if (RF_core.manualXoscHfSelect) + { + RF_core.manualXoscHfSelect = false; + Power_releaseConstraint(PowerCC26XX_SWITCH_XOSC_HF_MANUALLY); + } + + /* Next state: RF_fsmPowerUpState */ + RF_core.fxn = RF_fsmPowerUpState; + + /* Indicate that the RF core is now powered down */ + RF_core.status = RF_CoreStatusIdle; + + /* Issue radio available callback if RF_yield was called with no + pending commands in the queue */ + uint8_t tmp = RF_RADIOFREECB_REQACCESS_FLAG; + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + tmp |= RF_RADIOFREECB_PREEMPT_FLAG | RF_RADIOFREECB_CMDREJECT_FLAG; + } + RF_issueRadioFreeCb(tmp); + } + else + { + /* Exit ritical setion. */ + HwiP_restore(key); + } + + /* Reschedule the next event based on the state of the command queue + and the RAT module. We do it here as future commands need to work even if + power management is disabled manually. */ + RF_dispatchNextEvent(); + + /* We've handled this event now */ + e &= ~RF_FsmEventPowerDown; + } + else if (e & RF_FsmEventRunScheduler) + { + /* Run the scheduler again. */ + RF_dispatchNextEvent(); + + /* We've handled this event now */ + e &= ~RF_FsmEventRunScheduler; + } + + /* Call self again if there are outstanding events to be processed */ + if (e) + { + /* Trig the SWI with the remained/unhandled events */ + SwiP_or(&RF_swiFsmObj, e); + } +} + +/*-------------- Initialization & helper functions ---------------*/ + +/* + * Initialize RF driver. + * + * Input: none + * Return: none + */ +static void RF_init(void) +{ + union { + HwiP_Params hp; + SwiP_Params sp; + } params; + + /* Power init */ + Power_init(); + + /* Enable output RTC clock for Radio Timer Synchronization */ + HWREG(AON_RTC_BASE + AON_RTC_O_CTL) |= AON_RTC_CTL_RTC_UPD_EN_M; + + /* Initialize SWI used by the RF driver. */ + SwiP_Params_init(¶ms.sp); + params.sp.priority = RFCC26XX_hwAttrs.swiPriority; + SwiP_construct(&RF_swiFsmObj, RF_swiFsm, ¶ms.sp); + SwiP_construct(&RF_swiHwObj, RF_swiHw, ¶ms.sp); + + /* Initialize HWI used by the RF driver. */ + HwiP_Params_init(¶ms.hp); + params.hp.priority = RFCC26XX_hwAttrs.hwiPriority; + HwiP_construct(&RF_hwiCpe0Obj, INT_RFC_CPE_0, RF_hwiCpe0PowerFsm, ¶ms.hp); + HwiP_construct(&RF_hwiHwObj, INT_RFC_HW_COMB, RF_hwiHw, ¶ms.hp); + + /* Initialize clock object used as power-up trigger */ + ClockP_construct(&RF_clkPowerUpObj, &RF_clkPowerUp, 0, NULL); + ClockP_construct(&RF_clkInactivityObj, &RF_clkInactivityCallback, 0, NULL); + + /* Subscribe to wakeup notification from the Power driver */ + Power_registerNotify(&RF_wakeupNotifyObj, /* Object to register */ + PowerCC26XX_AWAKE_STANDBY, /* Event the notification to be invoked upon */ + (Power_NotifyFxn) RF_wakeupNotification, /* Function to be invoked */ + (uintptr_t) NULL); /* Parameters */ + + /* Set the XOSC_HF dependency if the HW attributes say so. This will ensure + that the XOSC_HF is turned on by the power driver as soon as possible when + coming out of standby. */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == true) + { + Power_setDependency(PowerCC26XX_XOSC_HF); + } + + /* Initialized the queues. */ + List_clearList(&RF_cmdQ.pDone); + List_clearList(&RF_cmdQ.pPend); + + /* Initialize global variables */ + RF_core.status = RF_CoreStatusIdle; + RF_core.init = false; + RF_core.activeTimeUs = 0; + RF_core.manualXoscHfSelect = false; + RF_ratModule.availableRatChannels = RF_DEFAULT_AVAILRATCH_VAL; + RF_rtcTimestampA = 0; + RF_rtcBeginSequence = 0; + RF_errTolValInUs = RF_DEFAULT_RAT_RTC_ERR_TOL_IN_US; + RF_powerConstraint = 0; + + /* Set FSM state to power up */ + RF_core.fxn = RF_fsmPowerUpState; +} + +/* + * Trace through the pending queue and flush the command(s). + * + * Input: h - Handle to the client calling this function. + * pCmd - Pointer to the command where the cancelling should start with. + * bFlushAll - Decides weather one or more commands should be aborted. + * Return: Number of commands was terminated. + */ +static uint32_t RF_discardPendCmd(RF_Handle h, RF_Cmd* pCmd, bool bFlushAll, bool bPreempt) +{ + /* Local variables, start from the head of queue. */ + uint32_t numDiscardedCmd = 0; + RF_Cmd* pElem = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + /* Find the first command to be cancelled. */ + while (pElem && (pElem != pCmd)) + { + pElem = (RF_Cmd*)List_next((List_Elem*)pElem); + } + + /* If we found the command to be cancelled. */ + while (pElem) + { + /* Temporarly store the next element, since we will need + to continue from there. */ + RF_Cmd* pNextElem = (RF_Cmd*)List_next((List_Elem*)pElem); + + if (RF_isClientOwner(h, pElem)) + { + /* Mark the command that it was cancelled. */ + RF_cmdStoreEvents(pElem, RF_EventCmdCancelled); + + if (bPreempt) + { + /* Mark the command as being preempted. */ + RF_cmdStoreEvents(pElem, RF_EventCmdPreempted); + + /* Subscribe the client for RadioFree callback. */ + RF_Sch.clientHndRadioFreeCb = pCmd->pClient; + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_PREEMPT_FLAG; + } + + /* Remove the command from the pend queue and place it to + the done queue. */ + List_remove(&RF_cmdQ.pPend, (List_Elem*)pElem); + List_put(&RF_cmdQ.pDone, (List_Elem*)pElem); + + /* Increment the counter of cancelled commands. */ + numDiscardedCmd += 1; + } + + /* Break the loop if only single cancel was requested. + Step the queue otherwise. */ + if (bFlushAll) + { + pElem = pNextElem; + } + else + { + break; + } + } + + /* Return with the number of cancelled commands. */ + return(numDiscardedCmd); +} + +/* + * Process cancel commands. It is used by RF_cancelCmd, RF_flushCmd API. + * + * Input: h - Handle to the client calling this function. + * ch - Handle to the command where the cancelling should start with. + * graceful - true: stop the command + * false: abort the command + * flush - true: flush all commands of this client + * false: only cancel the given command + * preempt - mark the command as the reason of aborting is preemption + * Return: status + */ +static RF_Stat RF_abortCmd(RF_Handle h, RF_CmdHandle ch, bool graceful, bool flush, bool preempt) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Initialize local variables */ + RF_Cmd* pCmd = NULL; + RF_Stat status = RF_StatInvalidParamsError; + RF_EventMask event = graceful ? RF_EventCmdStopped : RF_EventCmdAborted; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Handle FLUSH_ALL request */ + if (ch == RF_CMDHANDLE_FLUSH_ALL) + { + /* Start to cancel the commands from the actively running onces if it belongs to this client. */ + if (RF_isClientOwner(h, RF_cmdQ.pCurrCmdBg)) + { + pCmd = RF_cmdQ.pCurrCmdBg; + } + else if (RF_isClientOwner(h, RF_cmdQ.pCurrCmdFg)) + { + pCmd = RF_cmdQ.pCurrCmdFg; + } + else + { + /* Start to walk the pending queue from its head. */ + pCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + } + } + else + { + /* Search for the command in the command pool based on its handle. The command can + locate on any of the queues at this point. */ + pCmd = RF_cmdGet(h, ch, 0x00); + } + + /* If command handle is valid, proceed to cancel. */ + if (pCmd) + { + /* If the command is still allocated. */ + if (pCmd->flags & RF_CMD_ALLOC_FLAG) + { + /* If the command we want to cancel is actively running. */ + if ((pCmd == RF_cmdQ.pCurrCmdBg) || (pCmd == RF_cmdQ.pCurrCmdFg)) + { + /* Flag that the command has been aborted. In IEEE 15.4 mode, this means + aborting both the background and foreground commands. */ + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdBg, event); + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdFg, event); + + /* Decode what method to use to terminate the ongoing radio operation. */ + uint32_t directCmd = (graceful) ? CMDR_DIR_CMD(CMD_STOP) : CMDR_DIR_CMD(CMD_ABORT); + + /* Send the abort/stop command through the doorbell to the RF core. */ + RFCDoorbellSendTo(directCmd); + + if (preempt) + { + /* Mark the command as being preempted. */ + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdBg, RF_EventCmdPreempted); + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdFg, RF_EventCmdPreempted); + + /* Subscribe the client for RadioFree callback. */ + RF_Sch.clientHndRadioFreeCb = pCmd->pClient; + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_PREEMPT_FLAG; + } + + /* Remove all commands from the pend queue belong to this client. Only do it + if it was explicitely requested through the flush argument. */ + if (flush) + { + RF_discardPendCmd(h, (RF_Cmd*)List_head(&RF_cmdQ.pPend), flush, preempt); + } + + /* Return with success as we cancelled at least the currently running command. */ + status = RF_StatSuccess; + } + else + { + /* Remove one/all commands from the pend queue based on the flush argument. + If at least one command is cancelled the operation was succesful. Otherwise, + either the pend queue is empty or pCmd have terminated earlier */ + if (RF_discardPendCmd(h, pCmd, flush, preempt)) + { + /* Kick the state machine to handle the done queue and re-execute the scheduler. + This is not necessary when the RF is currently performing a power-up. */ + if ((RF_core.status != RF_CoreStatusPoweringUp) && + (RF_core.status != RF_CoreStatusPhySwitching)) + { + SwiP_or(&RF_swiFsmObj, (RF_FsmEventLastCommandDone | RF_FsmEventRunScheduler)); + } + + /* At least one command was cancelled. */ + status = RF_StatSuccess; + } + else + { + /* The command is not running and is not in the pend queue. It is located on the + done queue, hence return RF_StatCmdEnded. */ + status = RF_StatCmdEnded; + } + } + } + else + { /* If command is still in the pool but it is not allocated anymore, i.e. it was already served. */ + status = RF_StatCmdEnded; + } + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with the result: + - RF_StatSuccess if at least one command was cancelled. + - RF_StatCmdEnded, when the command already finished. + - RF_StatInvalidParamsError otherwise. */ + return(status); +} + +/* + * Execute a direct or immediate command in the RF Core if possible. + * + * Input: pCmd - Pointer to the command which shall be sent to the RF core. + * rawStatus - Return address of the raw status byte read from the CMDSTA register. + * Return: The return value interprets and converts the result of command execution to and RF_Stat value. + * RF_StatCmdDoneSuccess - If the command was sent and accepted by the RF core. + * RF_StatCmdDoneError - Command was rejected by the RF core. + * RF_StatRadioInactiveError - The RF core is OFF. + */ +static RF_Stat RF_executeDirectImmediateCmd(uint32_t pCmd, uint32_t* rawStatus) +{ + /* If the RF core is ON, we can send the command */ + if (RF_core.status == RF_CoreStatusActive) + { + /* Submit the command to the doorbell */ + uint32_t localStatus = RFCDoorbellSendTo(pCmd); + + /* Pass the rawStatus to the callee if possible. */ + if (rawStatus) + { + *rawStatus = localStatus; + } + + /* Check the return value of the RF core through the CMDSTA register within the doorbell */ + if ((localStatus & RF_CMDSTA_REG_VAL_MASK) == CMDSTA_Done) + { + /* The command was accepted */ + return(RF_StatCmdDoneSuccess); + } + else + { + /* The command was rejected */ + return(RF_StatCmdDoneError); + } + } + else + { + /* The RF core is not capable of receiving the command */ + return(RF_StatRadioInactiveError); + } +} + +/* + * Send a direct or immediate command to the RF core. The command is rejected + * if the RF core is configured to a different PHY (client). + * + * Input: h - Handle to the client calling this function. + * pCmd - Pointer to the command which shall be sent to the RF core. + * rawStatus - Return address of raw status byte read from CMDSTA register. + * Return: RF_StatCmdDoneSuccess - If the command was sent and accepted by the RF core. + * RF_StatCmdDoneError - Command was rejected by the RF core. + * RF_StatInvalidParamsError - Client do not have the right to send commands now. + * RF_StatRadioInactiveError - The RF core is OFF. + */ +static RF_Stat RF_runDirectImmediateCmd(RF_Handle h, uint32_t pCmd, uint32_t* rawStatus) +{ + /* Local variable. */ + RF_Stat status; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Only the current client is allowed to send direct commands */ + if (h != RF_currClient) + { + /* Return with an error code it is a different client */ + status = RF_StatInvalidParamsError; + } + else + { + /* Execute the direct or immediate command. */ + status = RF_executeDirectImmediateCmd(pCmd, rawStatus); + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with the status information about the success of command execution. */ + return(status); +} + +/* + * Helper function to find and modify the PA selection and gain of the provided setup command. + * + * Input: radioConfiguration - Radio configuration to be updated. + * newValue - The new value the PA to be set to. + * Return: RF_StatSuccess - The setup command was reconfigured. + * Otherwise - An error occured. + */ +static RF_Stat RF_updatePaConfiguration(RF_RadioSetup* radioSetup, RF_TxPowerTable_Value newValue) +{ + /* By default, reject the new configuration. */ + RF_Stat status = RF_StatInvalidParamsError; + + /* Determine if the new value is for the default-PA. */ + if (newValue.paType == RF_TxPowerTable_DefaultPA) + { + /* Calculate the offset of the txPower field and store the new value. */ + switch(radioSetup->commandId.commandNo) + { + case (CMD_RADIO_SETUP): + case (CMD_BLE5_RADIO_SETUP): + /* Set the new power value. */ + radioSetup->common.txPower = (uint16_t) newValue.rawValue; + break; + default: + /* Set the new power value. */ + radioSetup->prop.txPower = (uint16_t) newValue.rawValue; + break; + } + + /* Update the return value as the new configuration was accepted. */ + status = RF_StatSuccess; + } + + /* Return with the status. */ + return(status); +} + +/*-------------- API functions ---------------*/ +/* + * ======== RF_open ======== + * Open an RF handle + */ +RF_Handle RF_open(RF_Object *pObj, RF_Mode* pRfMode, RF_RadioSetup* pRadioSetup, RF_Params *params) +{ + /* Assert */ + DebugP_assert(pObj != NULL); + + /* Read available RF modes from the PRCM register */ + uint32_t availableRfModes = HWREG(PRCM_BASE + PRCM_O_RFCMODEHWOPT); + + /* Verify that the provided configuration is supported by this device. + Reject any request which is not compliant. */ + if (pRfMode && pRadioSetup && (availableRfModes & (1 << pRfMode->rfMode))) + { + /* Trim the override list; The implementation of RFCOverrideUpdate is device specific */ + RFCOverrideUpdate((RF_Op*)pRadioSetup, NULL); + + /* Register the setup command to the client */ + pObj->clientConfig.pRadioSetup = pRadioSetup; + + /* Register the mode to the client */ + pObj->clientConfig.pRfMode = pRfMode; + } + else + { + /* Return with null if the device do not support the requested configuration */ + return(NULL); + } + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Check whether RF driver is accepting more clients */ + if (RF_numClients < N_MAX_CLIENTS) + { + /* Initialize shared objects on first client opening */ + if (RF_numClients == 0) RF_init(); + + /* Save the new RF_Handle */ + RF_Sch.clientHnd[RF_numClients++] = pObj; + + /* Exit critical section */ + HwiP_restore(key); + + /* Populate default RF parameters if not provided */ + RF_Params rfParams; + if (params == NULL) + { + RF_Params_init(&rfParams); + params = &rfParams; + } + + /* Initialize RF_Object configuration */ + pObj->clientConfig.nInactivityTimeout = params->nInactivityTimeout; + pObj->clientConfig.nPhySwitchingDuration = RF_DEFAULT_PHY_SWITCHING_TIME; + pObj->clientConfig.nClientEventMask = params->nClientEventMask; + pObj->clientConfig.nPowerUpDurationMargin = params->nPowerUpDurationMargin; + pObj->clientConfig.bUpdateSetup = true; + + /* Decide if automatic adjustment should be used. */ + if (params->nPowerUpDuration) + { + pObj->clientConfig.nPowerUpDuration = params->nPowerUpDuration; + pObj->clientConfig.bMeasurePowerUpDuration = false; + } + else + { + pObj->clientConfig.nPowerUpDuration = RF_DEFAULT_POWER_UP_TIME; + pObj->clientConfig.bMeasurePowerUpDuration = true; + } + + /* Set all the callbacks to the default (do nothing) callback */ + pObj->clientConfig.pErrCb = (void*) RF_defaultCallback; + pObj->clientConfig.pClientEventCb = (void*) RF_defaultCallback; + pObj->clientConfig.pPowerCb = (void*) RF_defaultCallback; + + /* If a user specified callback is provided, overwrite the default */ + if (params->pErrCb) + { + pObj->clientConfig.pErrCb = (void *)params->pErrCb; + } + if (params->pClientEventCb) + { + pObj->clientConfig.pClientEventCb = (void *)params->pClientEventCb; + } + if (params->pPowerCb) + { + pObj->clientConfig.pPowerCb = (void *)params->pPowerCb; + } + + /* Initialize client state & variables to zero */ + memset((void*)&pObj->state, 0, sizeof(pObj->state)); + + /* Initialize client specific semaphore object */ + SemaphoreP_constructBinary(&pObj->state.semSync, 0); + + /* Initialize client specific clock objects */ + ClockP_construct(&pObj->state.clkReqAccess, RF_clkReqAccess, 0, NULL); + + /* Return with the RF handle. */ + return(pObj); + } + else + { + /* Exit critical section */ + HwiP_restore(key); + + /* Return with null if no more clients are accepted */ + return(NULL); + } +} + +/* + * ======== RF_close ======== + * Close an RF handle + */ +void RF_close(RF_Handle h) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* If there is at least one active client */ + if (RF_numClients) + { + /* Wait for all issued commands to finish before freeing the resources */ + if (RF_cmdQ.nSeqPost != RF_cmdQ.nSeqDone) + { + /* There are commands which not even dispatched yet. */ + RF_Cmd* pCmd = RF_queueEnd(h, &RF_cmdQ.pPend); + + /* There is no pending commmand, determine if there are items on the + other queues. */ + if (!pCmd) + { + /* If the client is executing a command running. */ + if (RF_isClientOwner(h, RF_cmdQ.pCurrCmdBg)) + { + /* The currentlty running command is the last. */ + pCmd = RF_cmdQ.pCurrCmdBg; + } + else + { + /* All commands has been dispatched, some just need to be served. This also + can return with NULL if nothing to be done. */ + pCmd = RF_queueEnd(h, &RF_cmdQ.pDone); + } + } + + /* Pend until the running command terminates */ + if (pCmd) + { + RF_pendCmd(h, pCmd->ch, RF_TERMINATION_EVENT_MASK); + } + } + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Clear the RF_sch client handle */ + if (h == RF_Sch.clientHnd[0]) + { + RF_Sch.clientHnd[0] = NULL; + } + else + { + RF_Sch.clientHnd[1] = NULL; + } + + /* Check whether this is the last client */ + if (--RF_numClients == 0) + { + /* If this is the last client, set it to be the active client */ + RF_currClient = h; + + if (RF_core.status == RF_CoreStatusActive) + { + /* Release the constraint on the RF resources */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + + /* Exit critical section */ + HwiP_restore(key); + + /* Wait until the radio is powered down (outside critical section) */ + SemaphoreP_pend(&h->state.semSync, SemaphoreP_WAIT_FOREVER); + + /* Enter critical section */ + key = HwiP_disable(); + } + + /* Unregister shared RTOS objects initalized during RF_init by the first client */ + SwiP_destruct(&RF_swiFsmObj); + HwiP_destruct(&RF_hwiCpe0Obj); + SwiP_destruct(&RF_swiHwObj); + HwiP_destruct(&RF_hwiHwObj); + ClockP_destruct(&RF_clkPowerUpObj); + ClockP_destruct(&RF_clkInactivityObj); + + /* Unregister the wakeup notify callback */ + Power_unregisterNotify(&RF_wakeupNotifyObj); + + /* Release XOSC_HF dependency if it was set on board level. */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == true) + { + Power_releaseDependency(PowerCC26XX_XOSC_HF); + } + } + + /* If we're the current RF client, stop being it */ + if (RF_currClient == h) + { + RF_currClient = NULL; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Unregister client specific RTOS objects (these are not shared between clients) */ + SemaphoreP_destruct(&h->state.semSync); + ClockP_destruct(&h->state.clkReqAccess); + } +} + +/* + * ======== RF_getCurrentTime ======== + * Get current time in RAT ticks + */ +uint32_t RF_getCurrentTime(void) +{ + /* Local variable */ + uint64_t nCurrentTime = 0; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* If radio is active, read the RAT */ + if (RF_core.status == RF_CoreStatusActive) + { + /* Read the RAT timer through register access */ + nCurrentTime = RF_ratGetValue(); + + /* Exit critical section */ + HwiP_restore(key); + } + else + { + /* Exit critical section */ + HwiP_restore(key); + + /* The radio is inactive, read the RTC instead */ + nCurrentTime = AONRTCCurrent64BitValueGet(); + + /* Conservatively assume that we are just about to increment the RTC + Scale with the 4 MHz that the RAT is running + Add the RAT offset for RTC==0 */ + nCurrentTime += RF_RTC_TICK_INC; + nCurrentTime *= RF_SCALE_RTC_TO_4MHZ; + nCurrentTime += ((uint64_t)RF_ratSyncCmd.start.rat0) << RF_SHIFT_32_BITS; + nCurrentTime >>= RF_SHIFT_32_BITS; + } + + /* Return with the current value */ + return((uint32_t) nCurrentTime); +} + +/* + * ======== RF_postCmd ======== + * Post radio command + */ +RF_CmdHandle RF_postCmd(RF_Handle h, RF_Op* pOp, RF_Priority ePri, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + DebugP_assert(pOp != NULL); + + /* Local pointer to a radio commands */ + RF_CmdHandle cmdHandle = (RF_CmdHandle)RF_ALLOC_ERROR; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Try to allocate container */ + RF_Cmd* pCmd = RF_cmdAlloc(); + + /* If allocation failed */ + if (pCmd) + { + /* Stop inactivity clock if running */ + ClockP_stop(&RF_clkInactivityObj); + + /* Increment the sequence number and mask the value */ + RF_cmdQ.nSeqPost = (RF_cmdQ.nSeqPost + 1) & N_CMD_MODMASK; + + /* Populate container with reset values */ + pCmd->pOp = pOp; + pCmd->ePri = ePri; + pCmd->pCb = pCb; + pCmd->ch = RF_cmdQ.nSeqPost; + pCmd->pClient = h; + pCmd->bmEvent = (bmEvent | RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M) & ~RF_INTERNAL_IFG_MASK; + pCmd->pastifg = 0; + pCmd->flags = RF_CMD_ALLOC_FLAG; + + /* Cancel ongoing yielding */ + h->state.bYielded = false; + + /* Submit to pending command to the queue. */ + List_put(&RF_cmdQ.pPend, (List_Elem*)pCmd); + + /* Trigger dispatcher if the timings need to be reconsidered. */ + if(List_head(&RF_cmdQ.pPend) == (List_Elem*)pCmd) + { + RF_dispatchNextEvent(); + } + + /* Return with the command handle as success */ + cmdHandle = pCmd->ch; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with an error code */ + return(cmdHandle); +} + +/* + * ==================== RF_ScheduleCmdParams_init ============================ + * Initialize the parameter structure to be used with RF_scheduleCmd(). + */ +void RF_ScheduleCmdParams_init(RF_ScheduleCmdParams *pSchParams) +{ + /* Assert */ + DebugP_assert(pSchParams != NULL); + + /* Set the configuration to use the default values. */ + pSchParams->priority = RF_PriorityNormal; + pSchParams->endTime = 0; +} + +/* + * ==================== RF_scheduleCmd ============================ + * Process request to schedule new command from a particular client + */ +RF_CmdHandle RF_scheduleCmd(RF_Handle h, RF_Op* pOp, RF_ScheduleCmdParams *pSchParams, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Local variable declaration. */ + RF_Cmd* pCmd; + RF_Handle h2; + int8_t status; + + /* Assert. */ + DebugP_assert(h != NULL); + DebugP_assert(pOp != NULL); + + /* Local pointer to a radio commands. */ + RF_CmdHandle cmdHandle = (RF_CmdHandle)RF_ALLOC_ERROR; + + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Assign h2 to client that is not issuing the new command. + The client h is issuing the new command. */ + if (h == RF_Sch.clientHnd[0]) + { + h2 = RF_Sch.clientHnd[1]; + } + else + { + h2 = RF_Sch.clientHnd[0]; + } + + /* If client h2 already has, reject any new commands from h. */ + if (h2 && (ClockP_isActive(&h2->state.clkReqAccess))) + { + /* Set the status value to schedule_error if we could not allocate space. */ + cmdHandle = (RF_CmdHandle) RF_SCHEDULE_CMD_ERROR; + + /* Store the reason and the handle why the callback is being invoked. */ + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_CMDREJECT_FLAG; + RF_Sch.clientHndRadioFreeCb = h; + } + else + { + /* Check if command queue has free entries and allocate RF_Op* container + if command queue is full reject the command. */ + pCmd = RF_cmdAlloc(); + + /* If allocation was succesful. */ + if (pCmd) + { + /* Stop inactivity clock if running. */ + ClockP_stop(&RF_clkInactivityObj); + + /* Increment the sequence number and mask the value. */ + RF_cmdQ.nSeqPost = (RF_cmdQ.nSeqPost + 1) & N_CMD_MODMASK; + + /* Cache meta-data. */ + pCmd->pOp = pOp; + pCmd->ePri = pSchParams->priority; + pCmd->pCb = pCb; + pCmd->ch = RF_cmdQ.nSeqPost; + pCmd->pClient = h; + pCmd->bmEvent = bmEvent & ~RF_INTERNAL_IFG_MASK; + pCmd->flags = 0; + pCmd->pastifg = 0; + pCmd->endTime = RF_SCH_CMD_ENDTIME_IGNORE; + pCmd->startTime = RF_SCH_CMD_STARTTIME_NOW; + + /* Update the default endTime based on the scheduling parameters. */ + if (pSchParams->endTime) + { + pCmd->endTime = pSchParams->endTime; + } + + /* Update the default startTime based on the command parameters. */ + if (pOp->startTrigger.triggerType == TRIG_ABSTIME) + { + pCmd->startTime = pOp->startTime; + } + + /* Find the last radio operation within the chain. */ + RF_Op* pEndOfChain = RF_findEndOfChain(pOp); + + /* Mark the context of the command based on it's ID and subscribe it + to the expected termination event. */ + if ((pEndOfChain->commandNo & RF_IEEE_ID_MASK) == RF_IEEE_FG_CMD) + { + pCmd->flags |= RF_CMD_FG_CMD_FLAG; + pCmd->bmEvent |= RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M; + } + else + { + pCmd->bmEvent |= RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M; + } + + /* Cancel the radio free callback if new command is from the same client. */ + if ((RF_Sch.clientHndRadioFreeCb == h) && + (RF_Sch.issueRadioFreeCbFlags & RF_RADIOFREECB_PREEMPT_FLAG)) + { + RF_Sch.issueRadioFreeCbFlags &= ~RF_RADIOFREECB_PREEMPT_FLAG; + } + + /* + * Try to schedule the new command. Returns with command handle in case of success. + * Returns RF_ALLOC_ERROR or RF_SCHEDULE_CMD_ERROR if the command it rejected. + */ + status = RF_schCmdRunInsertPreempt(h, h2, pCmd); + + /* Command was rejected. Either there was no slot available, or the timing did not fit. */ + if ((status == RF_ALLOC_ERROR) || (status == RF_SCHEDULE_CMD_ERROR)) + { + /* Decrement the sequence number and mask the value. */ + RF_cmdQ.nSeqPost = (RF_cmdQ.nSeqPost - 1) & N_CMD_MODMASK; + + /* Store the reason and the handle why the callback is being invoked. */ + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_CMDREJECT_FLAG; + RF_Sch.clientHndRadioFreeCb = h; + + /* Ensure that the error code reflects the reason of rejection. */ + cmdHandle = (RF_CmdHandle) status; + } + else + { + /* Command was inserted. Return with the valid handle. */ + cmdHandle = pCmd->ch; + + /* Mark the command as being allocated. */ + pCmd->flags |= RF_CMD_ALLOC_FLAG; + + /* Cancel previous yielding. */ + h->state.bYielded = false; + + /* Trigger dispatcher if the timings need to be reconsidered. */ + if(List_head(&RF_cmdQ.pPend) == (List_Elem*)pCmd) + { + RF_dispatchNextEvent(); + } + } + } + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with the command handle. */ + return(cmdHandle); +} + +/* + * ======== RF_pendCmd ======== + * Pend on radio command + */ +RF_EventMask RF_pendCmd(RF_Handle h, RF_CmdHandle ch, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* If the command handle is invalid (i.e. RF_ALLOC_ERROR) */ + if (ch < 0) + { + /* Return with zero means the command was rejected earlier */ + return(0); + } + + /* Enter critical section */ + uint32_t key = SwiP_disable(); + + /* Find the command based on its handle in the command pool */ + RF_Cmd* pCmd = RF_cmdGet(h, ch, RF_CMD_ALLOC_FLAG); + + /* If the command was already disposed */ + if (!pCmd || !(pCmd->flags & RF_CMD_ALLOC_FLAG)) + { + /* Exit critical section */ + SwiP_restore(key); + + /* Return with last command done event */ + return(RF_EventLastCmdDone); + } + + /* Expand the pend mask to accept RF_EventLastCmdDone and RF_EventLastFGCmdDone events even if it is not given explicitely */ + bmEvent = (bmEvent | RF_TERMINATION_EVENT_MASK); + + /* If the command is being executed, but the event we pending on has already happend (i.e. in a chain), + return the past events */ + if (pCmd->pastifg & bmEvent) + { + /* Exit critical section */ + SwiP_restore(key); + + /* Store the cause of returning */ + h->state.unpendCause = pCmd->pastifg & bmEvent; + + /* Clear the handled past events so it is possible to pend again */ + pCmd->pastifg &= ~h->state.unpendCause; + + /* Return with the events */ + return(h->state.unpendCause); + } + + /* Command has still not finished, override user callback with one that calls the user callback then posts to semaphore */ + if (pCmd->pCb != RF_syncCb) + { + /* Temporarily store the callback function */ + h->state.pCbSync = (void*)pCmd->pCb; + + /* Exhange the callback function: this will invoke the user callback and post to the semaphore if needed */ + pCmd->pCb = RF_syncCb; + } + + /* Store the event subscriptions in the clients context. This can only be one of the already enabled + interrupt sources by RF_postCmd (including RF_EventLastCmdDone) */ + h->state.eventSync = bmEvent; + + /* Exit critical section */ + SwiP_restore(key); + + /* Wait for semaphore */ + SemaphoreP_pend(&h->state.semSync, SemaphoreP_WAIT_FOREVER); + + /* Return the events that resulted in releasing the RF_pend() call */ + return(h->state.unpendCause); +} + +/* + * ======== RF_runCmd ======== + * Run to completion a posted command + */ +RF_EventMask RF_runCmd(RF_Handle h, RF_Op* pOp, RF_Priority ePri, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Post the requested command */ + RF_CmdHandle ch = RF_postCmd(h, pOp, ePri, pCb, bmEvent); + + /* If the command was accepted, pend until one of the special events occur */ + return(RF_pendCmd(h, ch, RF_TERMINATION_EVENT_MASK)); +} + +/* + * ======== RF_runScheduleCmd ======== + * Run to completion a scheduled command + */ +RF_EventMask RF_runScheduleCmd(RF_Handle h, RF_Op* pOp, RF_ScheduleCmdParams *pSchParams, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Post the requested command */ + RF_CmdHandle ch = RF_scheduleCmd(h, pOp, pSchParams, pCb, bmEvent); + + /* If the command was accepted, pend until one of the special events occur */ + return(RF_pendCmd(h, ch, RF_TERMINATION_EVENT_MASK)); +} + +/* + * ======== RF_yieldCmd ======== + * Release client access + */ +void RF_yield(RF_Handle h) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Request the synchronization of RTC and RAT at next power down. This is trigged + by ceiling the active time to the maximum value. */ + RF_core.activeTimeUs = UINT32_MAX; + + /* Stop ongoing request access and issue callback if the radio is off */ + ClockP_stop((&h->state.clkReqAccess)); + + /* If all commands are done */ + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + if ((RF_core.status != RF_CoreStatusActive) && RF_Sch.issueRadioFreeCbFlags) + { + /* Exit critical section. */ + HwiP_restore(key); + + /* Invoke the radio free callback provided by the user. */ + RF_issueRadioFreeCb(RF_RADIOFREECB_REQACCESS_FLAG | + RF_RADIOFREECB_PREEMPT_FLAG | + RF_RADIOFREECB_CMDREJECT_FLAG); + + /* Enter critical section. */ + key = HwiP_disable(); + } + } + + /* If the radioFreeCb did not post new commands. */ + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + /* All commands are done. Stop inactivity timer. */ + ClockP_stop(&RF_clkInactivityObj); + + /* Potentially power down the RF core. */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + } + else + { + /* There are still client commands that haven't finished. + Set flag to indicate immediate powerdown when last command is done. */ + h->state.bYielded = true; + } + + /* Exit critical section */ + HwiP_restore(key); +} + +/* + * ======== RF_cancelCmd ======== + * Cancel single radio command + */ +RF_Stat RF_cancelCmd(RF_Handle h, RF_CmdHandle ch, uint8_t mode) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Decode what method to be used for terminating the commands. */ + bool graceful = (bool)(mode & RF_ABORT_GRACEFULLY); + bool flush = (bool)(mode & RF_ABORT_FLUSH_ALL); + bool preempt = (bool)(mode & RF_ABORT_PREEMPTION); + + /* Invoke the aborting process with the input arguments on a single command */ + return(RF_abortCmd(h, ch, graceful, flush, preempt)); +} + +/* + * ======== RF_flushCmd ======== + * Cancel multiple radio commands from a client + */ +RF_Stat RF_flushCmd(RF_Handle h, RF_CmdHandle ch, uint8_t mode) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Decode what method to be used for terminating the commands. */ + bool graceful = (bool)(mode & RF_ABORT_GRACEFULLY); + bool flush = true; + bool preempt = (bool)(mode & RF_ABORT_PREEMPTION); + + /* Abort multiple radio commands implicitly */ + return(RF_abortCmd(h, ch, graceful, flush, preempt)); +} + +/* + * ======== RF_Params_init ======== + * Initialize the RF_params to default value + */ +void RF_Params_init(RF_Params *params) +{ + /* Assert */ + DebugP_assert(params != NULL); + + /* Assign default values for RF_params */ + *params = RF_defaultParams; +} + +/* + * ======== RF_runImmediateCmd ======== + * Run immediate command + */ +RF_Stat RF_runImmediateCmd(RF_Handle h, uint32_t* pCmd) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Submit the command to the RF core */ + return(RF_runDirectImmediateCmd(h, (uint32_t)pCmd, NULL)); +} + +/* + * ======== RF_runDirectCmd ======== + * Run direct command + */ +RF_Stat RF_runDirectCmd(RF_Handle h, uint32_t cmd) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Submit the command to the RF core */ + return(RF_runDirectImmediateCmd(h, cmd, NULL)); +} + +/* + * ======== RF_getRssi ======== + * Get RSSI value + */ +int8_t RF_getRssi(RF_Handle h) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Local variable. */ + uint32_t rawRssi; + + /* Read the RSSI value if possible. */ + RF_Stat status = RF_runDirectImmediateCmd(h, CMDR_DIR_CMD(CMD_GET_RSSI), &rawRssi); + + /* Decode the RSSI value if possible. */ + if (status == RF_StatCmdDoneSuccess) + { + return((int8_t)((rawRssi >> RF_SHIFT_16_BITS) & RF_CMDSTA_REG_VAL_MASK)); + } + else + { + return((int8_t)RF_GET_RSSI_ERROR_VAL); + } +} + +/* + * ======== RF_getInfo ======== + * Get RF driver info + */ +RF_Stat RF_getInfo(RF_Handle h, RF_InfoType type, RF_InfoVal *pValue) +{ + /* Local variables */ + int8_t i = 0; + RF_Cmd* pCmd; + RF_ScheduleMapElement *pScheduleMap; + + /* Prepare the default status value */ + RF_Stat status = RF_StatSuccess; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Serve the different flavor of requests */ + switch (type) + { + case RF_GET_CURR_CMD: + /* Get the handle of the currently running command. It can be conerted + to a pointer through the RF_getCmdOp() API. */ + if (RF_cmdQ.pCurrCmdBg) + { + pValue->ch = RF_cmdQ.pCurrCmdBg->ch; + } + else + { + status = RF_StatError; + } + break; + + case RF_GET_AVAIL_RAT_CH: + /* Get available user channels within the RAT timer. + These channels can be allocated and used by the application. */ + pValue->availRatCh = RF_ratModule.availableRatChannels; + break; + + case RF_GET_RADIO_STATE: + /* Get current radio state */ + pValue->bRadioState = (RF_core.status == RF_CoreStatusActive) ? true : false; + break; + + case RF_GET_CLIENT_LIST: + /* Copy the client pointer list ([0] -> client 1, [1] -> client 2) */ + pValue->pClientList[0] = RF_Sch.clientHnd[0]; + pValue->pClientList[1] = RF_Sch.clientHnd[1]; + break; + + case RF_GET_CLIENT_SWITCHING_TIME: + /* Copy the phy switching times to the RF_InfoVal structure */ + pValue->phySwitchingTimeInUs[0] = RF_Sch.clientHnd[0] ? RF_Sch.clientHnd[0]->clientConfig.nPhySwitchingDuration : 0; + pValue->phySwitchingTimeInUs[1] = RF_Sch.clientHnd[1] ? RF_Sch.clientHnd[1]->clientConfig.nPhySwitchingDuration : 0; + break; + + case RF_GET_SCHEDULE_MAP: + /* Get scheduler timing map. This can be used to determine the recent + time slots which are occupied by posted commands; and can help to + find out if a command can be inserted to the queue or not. In dual-mode + applications, this can help to sync the two protocol. */ + pScheduleMap = (RF_ScheduleMapElement *)pValue->pScheduleMap; + memset(pScheduleMap, 0, sizeof(RF_ScheduleMapElement) * RF_NUM_SCHEDULE_MAP_ENTRIES); + + for (i = 0; i < RF_NUM_SCHEDULE_ACCESS_ENTRIES; i++) + { + /* Copy access request info to schedule map */ + pScheduleMap[i].pClient = RF_Sch.clientHnd[i]; + pScheduleMap[i].priority = RF_Sch.accReq[i].priority; + uint32_t startTime = RF_Sch.accReq[i].startTime; + pScheduleMap[i].startTime = startTime; + pScheduleMap[i].endTime = startTime + RF_Sch.accReq[i].duration; + } + + /* Check if there is current command running */ + if (RF_cmdQ.pCurrCmdBg) + { + /* Copy current command info to schedule map */ + pScheduleMap[i].pClient = RF_cmdQ.pCurrCmdBg->pClient; + pScheduleMap[i].ch = RF_cmdQ.pCurrCmdBg->ch; + pScheduleMap[i].priority = RF_cmdQ.pCurrCmdBg->ePri; + pScheduleMap[i].startTime = RF_cmdQ.pCurrCmdBg->startTime; + pScheduleMap[i].endTime = RF_cmdQ.pCurrCmdBg->endTime; + } + + /* Increment the index to ensure a fixed location for the background command. */ + i++; + + /* Check if there is current command running */ + if (RF_cmdQ.pCurrCmdFg) + { + /* Copy current command info to schedule map */ + pScheduleMap[i].pClient = RF_cmdQ.pCurrCmdFg->pClient; + pScheduleMap[i].ch = RF_cmdQ.pCurrCmdFg->ch; + pScheduleMap[i].priority = RF_cmdQ.pCurrCmdFg->ePri; + pScheduleMap[i].startTime = RF_cmdQ.pCurrCmdFg->startTime; + pScheduleMap[i].endTime = RF_cmdQ.pCurrCmdFg->endTime; + } + + /* Increment the index to ensure a fixed location for the foreground command. */ + i++; + + /* Check pending commands */ + pCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + /* Loop until end of command queue or number of entries exceed */ + while (pCmd) + { + if (i < RF_NUM_SCHEDULE_MAP_ENTRIES) + { + /* Copy pending command info to schedule map */ + pScheduleMap[i].pClient = pCmd->pClient; + pScheduleMap[i].ch = pCmd->ch; + pScheduleMap[i].priority = pCmd->ePri; + pScheduleMap[i].startTime = pCmd->startTime; + pScheduleMap[i].endTime = pCmd->endTime; + i++; + } + else + { + /* Number of entries exceeded, get out of loop */ + break; + } + + /* Walk the queue. */ + pCmd = (RF_Cmd*)List_next((List_Elem*)pCmd); + } + break; + + default: + status = RF_StatInvalidParamsError; + break; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with a status code */ + return(status); +} + +/* + * ======== RF_getCmdOp ======== + * Get RF command + */ +RF_Op* RF_getCmdOp(RF_Handle h, RF_CmdHandle ch) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Find the command in the command pool based on its handle */ + RF_Cmd* pCmd = RF_cmdGet(h, ch, RF_CMD_ALLOC_FLAG); + + /* If the command is found */ + if (pCmd) + { + /* Return with the first operation in the command */ + return(pCmd->pOp); + } + else + { + /* Return with null in case of error */ + return(NULL); + } +} + +/* + * ======== RF_RatConfigCompare_init ======== + * Initialize RAT compare configuration + */ +void RF_RatConfigCompare_init(RF_RatConfigCompare* channelConfig) +{ + /* Assert */ + DebugP_assert(channelConfig != NULL); + + /* Set the values to default. */ + memset((void*)channelConfig, 0, sizeof(RF_RatConfigCompare)); + + /* Set the default allocation method to use any channel. */ + channelConfig->channel = RF_RatChannelAny; +} + +/* + * ======== RF_RatConfigCapture_init ======== + * Initialize RAT capture configuration + */ +void RF_RatConfigCapture_init(RF_RatConfigCapture* channelConfig) +{ + /* Assert */ + DebugP_assert(channelConfig != NULL); + + /* Set the values to default. */ + memset((void*)channelConfig, 0, sizeof(RF_RatConfigCapture)); + + /* Set the default allocation method to use any channel. */ + channelConfig->channel = RF_RatChannelAny; +} + +/* + * ======== RF_RatConfigOutput_init ======== + * Initialize RAT IO configuration + */ +void RF_RatConfigOutput_init(RF_RatConfigOutput* ioConfig) +{ + /* Assert */ + DebugP_assert(ioConfig != NULL); + + /* Set the values to default. */ + memset((void*)ioConfig, 0, sizeof(RF_RatConfigOutput)); +} + +/* + * ======== RF_ratCompare ======== + * Set RAT compare + */ +RF_RatHandle RF_ratCompare(RF_Handle rfHandle, RF_RatConfigCompare* channelConfig, RF_RatConfigOutput* ioConfig) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Configure the RAT channel into COMPARE mode. */ + return(RF_ratSetupChannel(rfHandle, RF_RatModeCompare, channelConfig->callback, channelConfig->channel, (void*) channelConfig, ioConfig)); +} + +/* + * ======== RF_ratCapture ======== + * Set RAT capture + */ +RF_RatHandle RF_ratCapture(RF_Handle rfHandle, RF_RatConfigCapture* channelConfig, RF_RatConfigOutput* ioConfig) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Configure the RAT channel into CAPTURE mode. */ + return(RF_ratSetupChannel(rfHandle, RF_RatModeCapture, channelConfig->callback, channelConfig->channel, (void*) channelConfig, ioConfig)); +} + +/* + * ======== RF_ratDisableChannel ======== + * Disable RAT channel + */ +RF_Stat RF_ratDisableChannel(RF_Handle h, RF_RatHandle ratHandle) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Default return value */ + RF_Stat status = RF_StatError; + + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Find the pointer to the RAT channel configuration. */ + RF_RatChannel* ratCh = RF_ratGetChannel(ratHandle); + + /* If the provided handler is valid. */ + if (ratCh && ratCh->status) + { + /* If the RF core is active, abort the RAT event. */ + if (RF_core.status == RF_CoreStatusActive) + { + /* Calculate the configuration field of command (the channel we disable). */ + uint16_t config = (uint16_t)(RF_RAT_CH_LOWEST + ratCh->handle) << RF_SHIFT_8_BITS; + + /* Disable the channel within the RF core. */ + status = RF_runDirectImmediateCmd(h, ((uint32_t)CMDR_DIR_CMD_2BYTE(CMD_DISABLE_RAT_CH, config)), NULL); + + /* Free the container for further use. We do it after the direct command to be sure it is not powered down. + This will implicitely schedule the next event and run the power management accordingly. */ + RF_ratFreeChannel(ratCh); + } + else + { + /* Set status to be successful. */ + status = RF_StatCmdDoneSuccess; + + /* Free the container for further use. If possible, power down the radio. */ + RF_ratFreeChannel(ratCh); + + /* Recalculate the next wakeup event if the radio was off. */ + RF_dispatchNextEvent(); + } + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with the status code */ + return(status); +} + +/* + * ======== RF_control ======== + * RF control + */ +RF_Stat RF_control(RF_Handle h, int8_t ctrl, void *args) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Prepare the return value for worst case scenario */ + RF_Stat status = RF_StatSuccess; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Serve the different requests */ + switch (ctrl) + { + case RF_CTRL_SET_INACTIVITY_TIMEOUT: + /* Update the inactivity timeout of the client. + This can be used if the value given at RF_open + need to be updated */ + h->clientConfig.nInactivityTimeout = *(uint32_t *)args; + break; + + case RF_CTRL_UPDATE_SETUP_CMD: + /* Enable a special boot process which can be controlled + through the config field of the radio setup command. + This will influence only the next power up sequence + and will be reset automatically afterwards. The special + power up process will require longer power up time, hence + the nPowerUpDuration need to be increased */ + h->clientConfig.bUpdateSetup = true; + h->clientConfig.nPowerUpDuration += RF_ANALOG_CFG_TIME_US; + break; + + case RF_CTRL_SET_POWERUP_DURATION_MARGIN: + /* Configure the margin which is added to the measured + nPowerUpDuration. This can ensure that the commands + are executed on time, depending on the load of the + cpu */ + h->clientConfig.nPowerUpDurationMargin = *(uint32_t *)args; + break; + + case RF_CTRL_SET_RAT_RTC_ERR_TOL_VAL: + /* Configure the tolerance value which is used to determine + the period when the RAT need to be syncronized to the RTC + due to the frequency offset */ + RF_errTolValInUs = *(uint32_t*)args; + break; + + case RF_CTRL_SET_POWER_MGMT: + /* The RF drivers power management can be enabled/disabled by + directly setting the power constraints from the application. + It is important that the order of actions align. */ + if (*(uint32_t*)args == 0) + { + RF_powerConstraintSet(RF_PowerConstraintDisallow); + } + else if (*(uint32_t*)args == 1) + { + RF_powerConstraintRelease(RF_PowerConstraintDisallow); + } + else + { + status = RF_StatInvalidParamsError; + } + break; + + case RF_CTRL_SET_HWI_PRIORITY: + /* Changing priorities during run-time has constraints. + To not mess up with the RF driver, we require the RF + driver to be inactive. */ + if (RF_core.status || (List_head(&RF_cmdQ.pPend))) + { + status = RF_StatBusyError; + } + else + { + HwiP_setPriority(INT_RFC_CPE_0, *(uint32_t *)args); + HwiP_setPriority(INT_RFC_HW_COMB, *(uint32_t *)args); + } + break; + + case RF_CTRL_SET_SWI_PRIORITY: + /* Changing priorities during run-time has constraints. + To not mess up with the RF driver, we require the RF + driver to be inactive. */ + if (RF_core.status || (List_head(&RF_cmdQ.pPend))) + { + status = RF_StatBusyError; + } + else + { + SwiP_setPriority(&RF_swiFsmObj, *(uint32_t *)args); + SwiP_setPriority(&RF_swiHwObj, *(uint32_t *)args); + } + break; + + case RF_CTRL_SET_AVAILABLE_RAT_CHANNELS_MASK: + /* Mask the available RAT channels manually. This can be used when + a particular RAT channel is used through oridnary radio operations + instead of the dedicated RAT APIs. */ + RF_ratModule.availableRatChannels = *(uint8_t *)args; + break; + + default: + /* Request can not be served */ + status = RF_StatInvalidParamsError; + break; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with the status code */ + return(status); +} + +/* + * ======== RF_requestAccess ======== + * RF request access + */ +RF_Stat RF_requestAccess(RF_Handle h, RF_AccessParams *pParams) +{ + /* Assert. */ + DebugP_assert(h != NULL); + DebugP_assert(pParams != NULL); + + /* Convert the requested duration to us */ + uint32_t durationInUs = (pParams->duration >> 2); + + /* Check if RF_AccessParams are within the acceptable range. + Only PriorityHighest can be served */ + if ((durationInUs > RF_REQ_ACCESS_MAX_DUR_US) || + (pParams->priority != RF_PriorityHighest)) + { + return(RF_StatInvalidParamsError); + } + + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Determine the ID of the requesting client. */ + uint8_t clientIdx = 0; + if (h == RF_Sch.clientHnd[1]) + { + clientIdx = 1; + } + + /* Get handle to the other client. */ + RF_Handle h2 = RF_Sch.clientHnd[clientIdx ^ 0x1]; + + /* Check if, dedicated request can be served. + If possible update the RF_Sch structure and start the timer (RTC) for the request access duration. + else, return RF_StatBusyError */ + + /* Reject request if there is an ongoing request */ + if (!(h && ClockP_isActive(&h->state.clkReqAccess)) && + !(h2 && ClockP_isActive(&h2->state.clkReqAccess))) + { + /* Dummy RF_Cmd to use when checking for preemption, only priority is set */ + RF_Cmd dummy; + dummy.ePri = pParams->priority; + + /* If there is a client 2, check if we can preempt it */ + RF_Cmd* preemptCmd = &dummy; + if (h2) + { + dummy.ePri = pParams->priority; + preemptCmd = RF_checkForPreemption(h2, &dummy); + } + + /* If the request can be served */ + if (preemptCmd) + { + /* Update the scheduler */ + RF_Sch.accReq[clientIdx].duration = pParams->duration; + RF_Sch.accReq[clientIdx].priority = pParams->priority; + + /* Start timeout of the request */ + RF_restartClockTimeout(&h->state.clkReqAccess, durationInUs/ClockP_tickPeriod); + + /* Exit critical section */ + HwiP_restore(key); + + /* If the request resulted in the preemption of the other client (preemptCmd != dummy) */ + if (preemptCmd != &dummy) + { + /* Preempt the other client */ + RF_preemptClient(preemptCmd, dummy.ePri); + } + + /* Return with success after the access was granted */ + return(RF_StatSuccess); + } + } + + /* In case the request can not be served, prepare for a notification + callback when the radio becomes available */ + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_REQACCESS_FLAG; + RF_Sch.clientHndRadioFreeCb = h; + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with an error code */ + return(RF_StatBusyError); +} + +/* + * ======== RF_setTxPower ======== + * Set the TX power of the client + */ +RF_Stat RF_setTxPower(RF_Handle handle, RF_TxPowerTable_Value value) +{ + /* Set the default return value to be an error. */ + RF_Stat status = RF_StatInvalidParamsError; + + /* Update the setup command to make the changes permanent. */ + status = RF_updatePaConfiguration(handle->clientConfig.pRadioSetup, value); + + /* If we managed to decode and cache the changes in the setup command. */ + if (status == RF_StatSuccess) + { + /* Create an immediate command to be used to update the output power immediately. */ + rfc_CMD_SET_TX_POWER_t txPowerCmd = {.commandNo = CMD_SET_TX_POWER, + .txPower = (uint16_t) value.rawValue}; + + /* Update the TX power by executing a direct command. It only takes effect if both + the client is correct and the RF core is active at the time of call. + The RF core will blindly accept any value, hence no error checking is necessay. */ + RF_runDirectImmediateCmd(handle, (uint32_t)&txPowerCmd, NULL); + } + + /* Return with the status. */ + return(status); +} + +/* + * ======== RF_getTxPower ======== + * Get the current TX power value + */ +RF_TxPowerTable_Value RF_getTxPower(RF_Handle handle) +{ + /* Default return value. */ + RF_TxPowerTable_Value value = { .rawValue = RF_TxPowerTable_INVALID_VALUE, + .paType = RF_TxPowerTable_DefaultPA}; + + /* Decode the setup command associated with the provided handle. */ + RF_RadioSetup* setupCmd = handle->clientConfig.pRadioSetup; + + /* Decode the power setting in the setup command. */ + switch(setupCmd->commandId.commandNo) + { + case (CMD_RADIO_SETUP): + case (CMD_BLE5_RADIO_SETUP): + /* Decode the default PA value. */ + value.rawValue = setupCmd->common.txPower; + break; + default: + /* Decode the default PA value. */ + value.rawValue = setupCmd->prop.txPower; + break; + } + + /* Return with the decoded value. */ + return(value); +} + +/* + * ======== RF_TxPowerTable_findPowerLevel ======== + * Retrieves a power level in dBm for a given power configuration value. + */ +int8_t RF_TxPowerTable_findPowerLevel(RF_TxPowerTable_Entry table[], RF_TxPowerTable_Value value) +{ + /* Iterate through the power table. We do not verify against nullptr. */ + uint32_t i; + for (i=0; (table[i].power != RF_TxPowerTable_INVALID_DBM) && + (table[i].value.rawValue != RF_TxPowerTable_INVALID_VALUE); i++) + { + if (((uint32_t)table[i].value.paType == (uint32_t)value.paType) && + ((uint32_t)table[i].value.rawValue == (uint32_t)value.rawValue)) + { + /* Break the loop on the first entry which satisfies + the lower-or-equal criterion toward the input argument. */ + break; + } + } + + /* Return with the power level in dBm or with the + termination value RF_TxPowerTable_INVALID_DBM. */ + return(table[i].power); +} + +/* + * ======== RF_TxPowerTable_findValue ======== + * Retrieves a power configuration value for a given power level in dBm. + */ +RF_TxPowerTable_Value RF_TxPowerTable_findValue(RF_TxPowerTable_Entry table[], int8_t powerLevel) +{ + /* Local variable stores an invalid value. */ + RF_TxPowerTable_Value invalidValue = { .rawValue = RF_TxPowerTable_INVALID_VALUE, + .paType = RF_TxPowerTable_DefaultPA }; + + /* Handle special input argument. */ + if (powerLevel == RF_TxPowerTable_MIN_DBM) + { + return(table[0].value); + } + else + { + /* Iterate through the power table. We do not verify against nullptr. */ + uint32_t i; + for (i=0; ((int8_t)table[i].power != (int8_t)RF_TxPowerTable_INVALID_DBM) && + ((uint32_t)table[i].value.rawValue != (uint32_t)RF_TxPowerTable_INVALID_VALUE); i++) + { + if (table[i].power > powerLevel) + { + /* Break the loop on the first entry which satisfies + the lower-or-equal criterion toward the input argument. */ + break; + } + } + + if (i == 0) + { + /* If the first entry is already larger, then the requested + power level is invalid. */ + return(invalidValue); + } + else + { + /* Return with a valid RF_TxPowerTable_Value or with the + maximum value in the table. */ + return(table[i-1].value); + } + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RFCC26XX_singleMode.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RFCC26XX_singleMode.c new file mode 100644 index 0000000..af2b63d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RFCC26XX_singleMode.c @@ -0,0 +1,3869 @@ +/* +* Copyright (c) 2015-2018, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_rfc_rat.h) +#include DeviceFamily_constructPath(inc/hw_rfc_dbell.h) +#include DeviceFamily_constructPath(driverlib/rfc.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) +#include DeviceFamily_constructPath(driverlib/rf_mailbox.h) +#include DeviceFamily_constructPath(driverlib/adi.h) +#include DeviceFamily_constructPath(driverlib/aon_rtc.h) +#include DeviceFamily_constructPath(driverlib/chipinfo.h) + +#if defined(__IAR_SYSTEMS_ICC__) +#pragma diag_remark=Pa082 +#endif + +#if !defined(RF_SINGLEMODE) +#error "A required symbol (RF_SINGLEMODE) is missing." +#endif + +/*-------------- Typedefs, structures & defines ---------------*/ + +/* Definition of internal state-machine events. */ +typedef enum RF_FsmEvent_ { + RF_FsmEventLastCommandDone = (1UL << 1), /* Indicates that a radio command is finished. */ + RF_FsmEventWakeup = (1UL << 2), /* Used to initiate the power up sequence of the RF core. */ + RF_FsmEventPowerDown = (1UL << 3), /* Used to initiate the power down sequence of the RF core. */ + RF_FsmEventCpeInt = (1UL << 14), /* Generated during command execution. */ + RF_FsmEventPowerStep = (1UL << 29) /* Generated during the power up sequence of RF core. */ +} RF_FsmEvent; + +/* Definition of states of RF core. */ +typedef enum RF_CoreStatus_ { + RF_CoreStatusIdle = 0, /* The RF core is OFF. */ + RF_CoreStatusPoweringUp = 1, /* The RF core is being powered up. */ + RF_CoreStatusActive = 2, /* The RF core is ON. */ + RF_CoreStatusPoweringDown = 3, /* The RF core is being powered down. */ +} RF_CoreStatus; + +/* Definition of internal power constraints. Note that the physical RAT channels in the RF core are + not a one-to-one map to the constraint values here. */ +typedef enum RF_PowerConstraintSrc_ { + RF_PowerConstraintNone = 0, + RF_PowerConstraintRatCh0 = (1U << 0), /* Indicates that the Channel 0 of RAT timer is running. */ + RF_PowerConstraintRatCh1 = (1U << 1), /* Indicates that the Channel 1 of RAT timer is running. */ + RF_PowerConstraintRatCh2 = (1U << 2), /* Indicates that the Channel 2 of RAT timer is running. */ + RF_PowerConstraintCmdQ = (1U << 3), /* Indicates that the RF core executing a radio command. */ + RF_PowerConstraintDisallow = (1U << 7) /* Disable automatic power management. */ +} RF_PowerConstraintSrc; + +/* Definition of internal Radio Timer (RAT) modes. */ +typedef enum RF_RatMode_ { + RF_RatModeUndefined = 0, /* Indicates that the RAT channel is not configured. */ + RF_RatModeCompare = 1, /* Indicates that the RAT channel is configured to compare mode. */ + RF_RatModeCapture = 2 /* Indicates that the RAT channel is configured to capture mode. */ +} RF_RatMode; + +/* Definition of internal Radio Timer (RAT) states. */ +typedef enum RF_RatStatus_ { + RF_RatStatusIdle = 0, /* Indicates that the RAT channel is not used. */ + RF_RatStatusPending = 1, /* Indicates that the RAT channel is configured, but the RAT timer is not running (i.e. RF core is OFF). */ + RF_RatStatusRunning = 2 /* Indicates that the RAT channel is configured, and the RAT timer is running. */ +} RF_RatStatus; + +/*-------------- Macros ---------------*/ + +#define ABS(x) (((x) < 0) ? -(x) : (x)) +#define MAX(x,y) (((x) > (y)) ? (x) : (y)) +#define MIN(x,y) (((x) < (y)) ? (x) : (y)) +#define UDIFF(x,y) (((y) > (x)) ? ((y) - (x)) : ((~0) + (y) - (x) + (1))) +#define ADD(x,y) ((x > ((~0) - (y))) ? (~0) : ((x) + (y))) + +/*-------------- Defines ---------------*/ + +/* Max # of RF driver clients */ +#define N_MAX_CLIENTS 1 +/* 8 RF_Cmds in pool */ +#define N_CMD_POOL 8 +/* Modulus mask used for RF_CmdHandle calculations */ +#define N_CMD_MODMASK 0xFFF + +/*-------------- Internal RF constants ---------------*/ + +#define RF_CMD0 0x0607 +/* Accessible RF Core interrupts mask MSB 32 bits : RFHW int, LSB 32 bits : RF CPE int */ +#define RF_INTERNAL_IFG_MASK 0xFFFFFFDF60001000 +#define RF_TERMINATION_EVENT_MASK (RF_EventLastCmdDone | RF_EventLastFGCmdDone | RF_EventCmdAborted | RF_EventCmdStopped | RF_EventCmdCancelled) +#define RF_CMD_FG_CMD_FLAG (1 << 4) +#define RF_CMD_ALLOC_FLAG (1 << 7) +#define RF_CMD_TERMINATED (DONE_OK | ERROR_PAST_START) +#define RF_HW_INT_RAT_CH_MASK (RFC_DBELL_RFHWIFG_RATCH7 | RFC_DBELL_RFHWIFG_RATCH6 | RFC_DBELL_RFHWIFG_RATCH5) +#define RF_RAT_CH_CNT 3 +#define RF_HW_INT_CPE_MASK RFC_DBELL_RFHWIFG_MDMSOFT +#define RF_CPE0_INT_MASK 0xFFFFFFFF +/* Default value for power up duration (in us) used before first power cycle */ +#define RF_DEFAULT_POWER_UP_TIME 2500 +/* Default minimum power up duration (in us) */ +#define RF_DEFAULT_MIN_POWER_UP_TIME 500 +/* Default power-up margin (in us) to account for wake-up sequence outside the RF power state machine */ +#define RF_DEFAULT_POWER_UP_MARGIN 314 +/* Default power down duration in us */ +#define RF_DEFAULT_POWER_DOWN_TIME 1000 +#define RF_MAX_CHAIN_CMD_LEN 8 +/* RAT channel (0-4) are used by RF Core. Only 5,6,7 are available for application */ +#define RF_RAT_CH_LOWEST 5 +#define RF_SEND_RAT_STOP_RATIO 7 +#define RF_RTC_CONV_TO_US_SHIFT 12 +#define RF_SHIFT_4_BITS 4 +#define RF_SHIFT_8_BITS 8 +#define RF_SHIFT_16_BITS 16 +#define RF_SHIFT_32_BITS 32 +#define RF_RTC_TICK_INC (0x100000000LL/32768) +#define RF_SCALE_RTC_TO_4MHZ 4000000 +#define RF_NUM_RAT_TICKS_IN_1_US 4 +/* (3/4)th of a full RAT cycle, in us */ +#define RF_DISPATCH_MAX_TIME_US (UINT32_MAX / RF_NUM_RAT_TICKS_IN_1_US * 3 / 4) +/* (1/4)th of a full RAT cycle, in us */ +#define RF_DISPATCH_MAX_TIME_WRAPAROUND_US (int32_t)(RF_DISPATCH_MAX_TIME_US - UINT32_MAX / RF_NUM_RAT_TICKS_IN_1_US) +#define RF_DISPATCH_INFINIT_TIME (UINT32_MAX) +#define RF_XOSC_HF_SWITCH_CHECK_PERIOD_US 50 +#define RF_DEFAULT_AVAILRATCH_VAL 0x7 +#define RF_ABORT_FLUSH_ALL 0x2 +#define RF_CMDSTA_REG_VAL_MASK 0xFF +#define RF_RAT_CAPTURE_REPEAT_MODE 0x10000000 +#define RF_RAT_INTERRUPT_BASE_INDEX 0x01 +#define RF_RAT_ERROR_BASE_INDEX 0x10 +#define RF_RAT_COMPENSATION_TIME_US 25 +#define RF_PHY_SWITCHING_MODE 1 +#define RF_PHY_BOOTUP_MODE 0 +/* Additional analog config time for setup command */ +#define RF_ANALOG_CFG_TIME_US 96 +/* Update analog configuration in setup */ +#define RF_SETUP_ANALOGCFG_UPDATE 0 +/* Don't update analog configuration in setup */ +#define RF_SETUP_ANALOGCFG_NOUPDATE 0x2D +#define RF_DEFAULT_RAT_RTC_ERR_TOL_IN_US 5 +/* Approx for 1e6 / 500. XTAL drift is 500 ppm */ +#define RF_DEFAULT_COMB_XTAL_DRIFT_BITS_SHIFT 11 +/* Window (in us) to decide if wakeup was from RF power up clock */ +#define RF_WAKEUP_DETECTION_WINDOW_IN_US 300 +/* Ieee context mask and background value */ +#define RF_IEEE_ID_MASK 0xFC00 +#define RF_IEEE_FG_CMD 0x2C00 + +/*-------------- Structures and definitions ---------------*/ + +/* FSM typedef. */ +typedef void (*RF_FsmStateFxn)(RF_Object* obj, RF_FsmEvent const e); + +/* Rat channel configuration. */ +typedef struct RF_RatChannel_s RF_RatChannel; + +/* Rat channel configuration. */ +struct RF_RatChannel_s { + RF_Handle pClient; /* Pointer to current client. NULL means the channel is free. */ + RF_RatCallback pCb; /* Callback pointer of the channel. */ + RF_RatMode mode; /* Mode of this RAT channel: RF_RatModeCompare, etc. */ + RF_RatHandle handle; /* Channel number: 0,1,2. */ + RF_RatStatus status; /* Status of the channel: RF_RatStatusIdle, RF_RatStatusPending, RF_RatStatusRunning */ + uint64_t chCmd; /* Generic storage for the command structure itself. */ + uint32_t ioCmd; /* Raw binary to be sent to the CM0 to set up the GPOs. This is optional. */ +}; + +/* Rat module configuration. */ +typedef struct RF_RatModule_s RF_RatModule; + +/* Rat module configuration. */ +struct RF_RatModule_s { + RF_RatChannel channel[RF_RAT_CH_CNT]; /* Container of channel configurations. */ + uint8_t availableRatChannels; /* Storage of available RAT channels read from the RF core. */ + uint8_t volatile pendingInt; /* Pending interrupt flags to be served. */ + uint8_t numActiveChannels; /* Counter of active channels. This is used to compensate the + overhead of programming the channels.*/ +}; + +/* RF core configuration. */ +typedef struct RF_CoreState_s RF_CoreState; + +/* RF core configuration. */ +struct RF_CoreState_s +{ + RF_CoreStatus volatile status; + RF_FsmStateFxn fxn; + uint32_t activeTimeUs; + bool init; + bool manualXoscHfSelect; +}; + +/* RAT synchronization. */ +typedef union RF_RatSyncCmd_u RF_RatSyncCmd; + +/* RAT synchronization. */ +union RF_RatSyncCmd_u +{ + rfc_CMD_SYNC_START_RAT_t start; + rfc_CMD_SYNC_STOP_RAT_t stop; +}; + +/* Command queue. */ +typedef struct RF_CmdQ_s RF_CmdQ; + +/* Command queue. */ +struct RF_CmdQ_s{ + List_List pPend; /* List of pending commands to be dispatched. */ + List_List pDone; /* List of executed commands to be served. */ + RF_Cmd* volatile pCurrCmd; /* Currently running command. */ + RF_Cmd* volatile pCurrCmdCb;/* Command which callback to be invoked. */ + RF_CmdHandle volatile nSeqPost; /* Sequence # for previously posted command. */ + RF_CmdHandle volatile nSeqDone; /* Sequence # for last done command. */ +}; + +/*-------------- RTOS objects ---------------*/ + +/* RF core software interrupts */ +static SwiP_Struct RF_swiFsmObj; +static void RF_swiFsm(uintptr_t a, uintptr_t b); + +/* RF core hardware interrupts */ +static HwiP_Struct RF_hwiCpe0Obj; +static void RF_hwiCpe0Active(uintptr_t a); +static void RF_hwiCpe0PowerFsm(uintptr_t a); + +/* RF core HW software interrupts */ +static SwiP_Struct RF_swiHwObj; +static void RF_swiHw(uintptr_t a, uintptr_t b); + +/* RF core HW hardware interrupts */ +static HwiP_Struct RF_hwiHwObj; +static void RF_hwiHw(uintptr_t a); + +/* Clock used for triggering power-up sequences */ +static ClockP_Struct RF_clkPowerUpObj; +static void RF_clkPowerUp(uintptr_t a); + +/* Common inactivity timeout clock callback */ +static ClockP_Struct RF_clkInactivityObj; +static void RF_clkInactivityCallback(uintptr_t a); + + +/*-------------- Static structures ---------------*/ + +/* Default RF parameters structure */ +static const RF_Params RF_defaultParams = { + .nInactivityTimeout = SemaphoreP_WAIT_FOREVER, + .nPowerUpDuration = 0, + .pPowerCb = NULL, + .pErrCb = NULL, + .nPowerUpDurationMargin = RF_DEFAULT_POWER_UP_MARGIN, +}; + +/*-------------- Global variables ---------------*/ + +/* RF_Cmd container pool. Containers with extra information about RF commands. */ +static RF_Cmd RF_cmdPool[N_CMD_POOL]; + +/* Command queue top level structure. It contains pointers to the different queues. */ +static RF_CmdQ RF_cmdQ; + +/* Static object used to subscribe from early notification in the power driver */ +static Power_NotifyObj RF_wakeupNotifyObj; + +/* Power constraints set by the RF driver */ +static volatile uint8_t RF_powerConstraint; + +/* Pointer to current radio client (indicates also whether the radio is powered) */ +static RF_Object* RF_currClient; + +/* Current state of the RF core. */ +static RF_CoreState RF_core; + +/* Static container of a direct/immediate commands */ +static RF_RatModule RF_ratModule; + +/* Commands used to synchronize the RTC and the RAT timer. */ +static volatile RF_RatSyncCmd RF_ratSyncCmd; + +/* Variables used for powerUpDuration, phySwitchingTime and RAT sync time calculation */ +static uint32_t RF_rtcTimestampA; +static uint32_t RF_errTolValInUs; + +/* Counter of radio clients */ +static uint8_t RF_numClients; + +/*-------------- Externs ---------------*/ + +/* Hardware attribute structure populated in board.c file to set HWI and SWI priorities */ +extern const RFCC26XX_HWAttrsV2 RFCC26XX_hwAttrs; + +/*-------------- State machine functions ---------------*/ + +/* FSM state functions */ +static void RF_fsmPowerUpState(RF_Object *pObj, RF_FsmEvent e); +static void RF_fsmSetupState(RF_Object *pObj, RF_FsmEvent e); +static void RF_fsmActiveState(RF_Object *pObj, RF_FsmEvent e); +static void RF_fsmXOSCState(RF_Object *pObj, RF_FsmEvent e); + +/*-------------- Helper functions ---------------*/ + +/* Command handling*/ +static RF_Cmd* RF_cmdAlloc(void); +static RF_Cmd* RF_cmdGet(RF_CmdHandle ch, uint8_t mask); +static bool RF_cmdDispatchTime(uint32_t* dispatchTimeClockTicks); +static RF_Stat RF_abortCmd(RF_Handle h, RF_CmdHandle ch, bool graceful, bool flush); +static bool RF_checkCmdFsError(void); +static void RF_cacheFsCmd(RF_Cmd* pCmd); +static uint32_t RF_discardPendCmd(RF_Handle h, RF_Cmd* pCmd, bool bFlushAll); + +/* RAT module */ +static RF_RatChannel* RF_ratGetChannel(uint8_t ch); +static RF_RatChannel* RF_ratAllocChannel(RF_RatHandle ratChannel); +static uint32_t RF_ratGetChannelValue(RF_RatHandle ratHandle); +static uint32_t RF_ratGetValue(void); +static void RF_ratGenerateChCmd(RF_RatChannel* ratCh, void* ratConfig); +static void RF_ratGenerateIoCmd(RF_RatChannel* ratCh, RF_RatConfigOutput* ioConfig); +static RF_RatHandle RF_ratSetupChannel(RF_Handle ratClient, RF_RatMode ratMode, RF_RatCallback ratCallback, RF_RatHandle ratChannel, void* ratConfig, RF_RatConfigOutput* ioConfig); +static void RF_ratRestartChannels(void); +static RF_Stat RF_ratArmChannel(RF_RatChannel* ratCh); +static void RF_ratFreeChannel(RF_RatChannel* ratCh); +static void RF_ratSuspendChannels(void); +static bool RF_ratReleaseChannels(void); +static bool RF_ratDispatchTime(uint32_t* dispatchTimeClockTicks); +static bool RF_ratIsRunning(void); + +/* Time management */ +static uint32_t RF_calculateDeltaTimeUs(uint32_t absTime, uint32_t nTotalPowerUpDuration); +static bool RF_calculateDispatchTime(uint32_t* dispatchTimeClockTicks); +static void RF_dispatchNextEvent(void); +static void RF_dispatchNextCmd(void); +static void RF_restartClockTimeout(ClockP_Handle clock, uint32_t timeout); + +/* Power management */ +static void RF_corePowerDown(void); +void RF_powerConstraintRelease(RF_PowerConstraintSrc src); +void RF_powerConstraintSet(RF_PowerConstraintSrc src); +RF_PowerConstraintSrc RF_powerConstraintGet(RF_PowerConstraintSrc src); +static void RF_setInactivityTimeout(void); + +/* Others */ +static void RF_init(void); +static void RF_defaultCallback(RF_Handle h, RF_CmdHandle ch, RF_EventMask e); +static RF_Stat RF_runDirectImmediateCmd(RF_Handle h, uint32_t pCmd, uint32_t* rawStatus); +static RF_Stat RF_executeDirectImmediateCmd(uint32_t pCmd, uint32_t* rawStatus); +static void RF_invokeGlobalCallback(RF_GlobalEvent event, void* arg); +static void RF_dbellSubmitCmdAsync(uint32_t rawCmd); +static void RF_dbellSyncOnAck(void); +static bool RF_isRadioSetup(RF_Op* pOp); +static void RF_initRadioSetup(RF_Handle handle); +static void RF_radioOpDoneCb(void); +static void RF_applyRfCorePatch(bool mode); + +/* PA management */ +static RF_Stat RF_updatePaConfiguration(RF_RadioSetup* radioSetup, RF_TxPowerTable_Value newValue); + +/*-------------- Command queue internal functions ---------------*/ + +/* + * Allocate a command buffer from the command pool. + * + * Input: none + * Return: RF command + */ +static RF_Cmd* RF_cmdAlloc(void) +{ + uint32_t i; + for (i = 0; i < N_CMD_POOL; i++) + { + /* Find the first available entry in the command pool */ + if (!(RF_cmdPool[i].flags & RF_CMD_ALLOC_FLAG)) + { + return(&RF_cmdPool[i]); + } + } + return(NULL); +} + +/* + * Search for a command in the command pool. + * + * Input: ch - RF command handle + * Return: RF command + */ +static RF_Cmd* RF_cmdGet(RF_CmdHandle ch, uint8_t mask) +{ + uint32_t i; + for (i = 0; i < N_CMD_POOL; i++) + { + /* Find the allocated command pool entry corresponding to ch */ + if (RF_cmdPool[i].ch == ch) + { + /* If a mask is provided, check the flags too */ + if (!mask || (RF_cmdPool[i].flags & mask)) + { + return(&RF_cmdPool[i]); + } + } + } + + return(NULL); +} + +/* + * Atomic storage of radio events happened during the execution of a command. + * + * Input: pCmd - Command the events belogn to. + * events - The radio events to be store within the context of the command. + * Return: none + */ +static void RF_cmdStoreEvents(RF_Cmd* pCmd, RF_EventMask events) +{ + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Store the events within the context of the command. */ + if (pCmd) + { + /* The field rfifg store the events for the next callback. + The field pastifg accumulates the events in case an + RF_pendCmd() API call happens. */ + pCmd->rfifg |= events; + pCmd->pastifg |= events; + } + + /* Exit critical section. */ + HwiP_restore(key); +} + +/* + * Reconfigure and restart a particular clock object. + * + * Input: clockObj - A pointer to a clock object. + * timeoutClockTicks - The timeout to be set in unit of clock ticks. + * Return: none + */ +static void RF_restartClockTimeout(ClockP_Handle clockHandle, uint32_t timeoutClockTicks) +{ + /* Ceil the value at minimum 1 clock tick. */ + timeoutClockTicks = MAX(timeoutClockTicks, 1); + + /* Reprogram the clock object. */ + ClockP_setTimeout(clockHandle, timeoutClockTicks); + ClockP_start(clockHandle); +} + +/* + * Calculate the delta time to an RF event including the overhead of powering up + * and down. + * + * Input: abstime - The timestamp the event will need to happen. + * nTotalPowerUpDuration - The duration we need to compensate with. + * Return: deltaTime - The time left until the RF core need to be trigged. + */ +static uint32_t RF_calculateDeltaTimeUs(uint32_t absTime, uint32_t nTotalPowerUpDuration) +{ + /* Local variables. */ + uint32_t deltaTimeUs; + + /* Read the timestamp to calculate difference from. */ + uint32_t currentTime = RF_getCurrentTime(); + + /* Calculate the difference with the current timestamp. */ + deltaTimeUs = UDIFF(currentTime, absTime); + deltaTimeUs /= RF_NUM_RAT_TICKS_IN_1_US; + + /* Check if delta time is greater than (powerup duration + power down duration) for a + power cycle, and is less than 3/4 of a RAT cycle (~17 minutes) */ + if ((deltaTimeUs > (int32_t)(nTotalPowerUpDuration + RF_DEFAULT_POWER_DOWN_TIME)) && + (deltaTimeUs <= RF_DISPATCH_MAX_TIME_US)) + { + /* Dispatch command in the future */ + return(MAX((deltaTimeUs - nTotalPowerUpDuration), 1)); + } + else + { + /* Dispatch immediately */ + return(0); + } +} + +/* + * Calculate the wakeup time of next command in the queue. + * + * Input: dispatchTimeClockTicks - Location where the calculated time is being stored. + * Return: validTime - Indicates if the returned time is valid. + */ +static bool RF_cmdDispatchTime(uint32_t* dispatchTimeClockTicks) +{ + /* By default, there is no command in the queue. */ + bool validTime = false; + + /* The next command in the queue determines the timing. */ + RF_Cmd* pCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + /* Only recognizes TRIG_ABSTIME triggers, everything else gets dispatched immediately. */ + if (pCmd) + { + /* If there is at least one pending command, we can calculate a legit dispatch time. */ + validTime = true; + + if (pCmd->pOp->startTrigger.triggerType == TRIG_ABSTIME) + { + /* Calculate the remained time until this absolute event. The calculation takes + into account the minimum power cycle time. */ + *dispatchTimeClockTicks = RF_calculateDeltaTimeUs(pCmd->pOp->startTime, + pCmd->pClient->clientConfig.nPowerUpDuration + + pCmd->pClient->clientConfig.nPowerUpDurationMargin + + (RF_RAT_COMPENSATION_TIME_US * RF_ratModule.numActiveChannels)); + + /* Scale the value to clock ticks*/ + *dispatchTimeClockTicks /= ClockP_tickPeriod; + } + else + { + /* Dispatch immediately. */ + *dispatchTimeClockTicks = 0; + } + } + else + { + /* This value will not be used. */ + *dispatchTimeClockTicks = 0; + } + + /* If the returned timestamp represents a valid dispatch time, return with true. */ + return(validTime); +} + +/*-------------- RAT internal functions ---------------*/ + +/* + * Determines if the RAT timer is running (clock is not gated) or not. + * This is used to determine if any RAT related command can be execured. + * + * Input: none + * Return: PWMCLK_EN_RAT - RAT timer is running. + * 0 - RAT timer is not running. + */ +static bool RF_ratIsRunning(void) +{ + /* Assume by default that the RAT is not available. */ + bool status = false; + + /* If the RF core power domain is ON, read the clock of the RAT. */ + if (HWREG(PRCM_BASE + PRCM_O_PDSTAT0) & PRCM_PDSTAT0_RFC_ON) + { + status = (bool)(HWREG(RFC_PWR_BASE + RFC_PWR_O_PWMCLKEN) & RFC_PWR_PWMCLKEN_RAT_M); + } + + /* Return with the status of RAT. */ + return(status); +} + +/* + * Allocate a RAT channel from the three slots available + * for the user. + * + * Input: ratChannel - Pointer to a user provided RF_RatHandle. + * Return: RF_RatChannel* - Pointer to the allocated channel if success. + * NULL - If failure. + */ +static RF_RatChannel* RF_ratAllocChannel(RF_RatHandle ratChannel) +{ + /* Walk the RAT channel indexes. */ + uint32_t i; + for (i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Calculate the bit representing this channel within the available channels. */ + uint32_t bitMask = (1 << i); + + /* Verify that no one is using this channel (from outside the scope of RF driver). */ + if (RF_ratModule.availableRatChannels & bitMask) + { + /* Mask the possible channels if a user handle is provided, otherwise find the + the first available channel. */ + if ((ratChannel == RF_RatChannelAny) || (ratChannel == i)) + { + /* Decode the fields of a channel. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* If an available channel is found. */ + if (ratCh && (ratCh->status == RF_RatStatusIdle)) + { + /* Mark the channel as occupied. */ + RF_ratModule.availableRatChannels &= ~bitMask; + + /* Put the channel into pending state. */ + ratCh->status = RF_RatStatusPending; + ratCh->handle = i; + + /* Increment the counter of active channels. This is used to compensate the + power up time with the overhead of programming these channels. */ + RF_ratModule.numActiveChannels += 1; + + /* Return with a pointer to the channel. */ + return(ratCh); + } + } + } + } + + /* Return with an invalid channel pointer in case of error. */ + return(NULL); +} + + +/* + * Free a given RAT channel. + * + * Input: ratCh - Pointer to a RAT channel in RF_ratModule. + * Return: none + */ +static void RF_ratFreeChannel(RF_RatChannel* ratCh) +{ + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* If a valid pointer is provided */ + if (ratCh && ratCh->status) + { + /* Precalculate the contraint ID of this channel. */ + RF_PowerConstraintSrc powerConstraint = (RF_PowerConstraintSrc)(1 << ratCh->handle); + + /* If the RF core power domain is ON. */ + if (RF_ratIsRunning()) + { + /* Calculate the channel index based on the handle. */ + uint32_t ratChIntFlag = (1 << (RFC_DBELL_RFHWIFG_RATCH5_BITN + ratCh->handle)); + + /* Disable the RAT channel interrupt source. */ + RFCHwIntDisable(ratChIntFlag); + RFCHwIntClear(ratChIntFlag); + } + + /* Reset the status of the channel. */ + ratCh->status = RF_RatStatusIdle; + ratCh->mode = RF_RatModeUndefined; + ratCh->pClient = NULL; + ratCh->pCb = NULL; + ratCh->chCmd = 0; + ratCh->ioCmd = 0; + + /* Mark the channel as available. */ + RF_ratModule.availableRatChannels |= (1 << ratCh->handle); + + /* Decrement the counter of active channels. To avoid underflow, check its value first. */ + if (RF_ratModule.numActiveChannels) + { + RF_ratModule.numActiveChannels -= 1; + } + + /* Notify the state machine that the RF core can be possibly powered down. */ + RF_powerConstraintRelease(powerConstraint); + } + + /* Exit critical section */ + HwiP_restore(key); +} + +/* + * Returns with a pointer to a RAT channel based on it's handle. + * + * Input: ch - Channel handle. + * Return: ratCh - Pointer to a RAT channel in RF_ratModule. + */ +static RF_RatChannel* RF_ratGetChannel(uint8_t ch) +{ + /* Convert a valid index into a pointer of a RAT channel configuration. */ + if (ch < RF_RAT_CH_CNT) + { + return((RF_RatChannel*)&RF_ratModule.channel[ch]); + } + + /* Return with NULL in case of invalid input argument. */ + return(NULL); +} + +/* + * Suspend the running channels and potentially initiate a power down. + * + * Input: none + * Return: true - All RAT channel is suspended. + * false - Otherwise. + */ +static bool RF_ratReleaseChannels(void) +{ + /* Only try to release the RAT channels if there is no other dependencies set. */ + if (!RF_powerConstraintGet(RF_PowerConstraintCmdQ) && + !RF_powerConstraintGet(RF_PowerConstraintDisallow)) + { + /* Calculate if there is enough time to power down and up. */ + uint32_t dispatchTimeClockTicks; + bool validTime = RF_calculateDispatchTime(&dispatchTimeClockTicks); + + /* If the next event is sufficiently far into the future. */ + if (!validTime || (validTime && dispatchTimeClockTicks)) + { + /* Suspend all RAT channels. */ + RF_ratSuspendChannels(); + + /* RAT channels were suspended. */ + return(true); + } + } + + /* RAT channels were not suspended. */ + return(false); +} + +/* + * Calculate the timeout of closest RAT event. + * + * Input: dispatchTimeClockTicks - Location where the calculated time is being stored. + * Return: validTime - Indicates if the returned time is valid. + */ +static bool RF_ratDispatchTime(uint32_t* dispatchTimeClockTicks) +{ + /* By default, there is no RAT running. */ + bool validTime = false; + + /* Initialize the return value. */ + *dispatchTimeClockTicks = RF_DISPATCH_INFINIT_TIME; + + /* Iterate through the RAT containers and calculate the remained time until + the closest RAT event. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Use a local pointer to have easier access to member fields. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* If the channel is either in PENDING or RUNNING state, meaning it is in use. */ + if (ratCh && ratCh->status) + { + /* There is at least one active channel, we can calculate a legit timestamp. */ + validTime = true; + + /* If there is at least one channel in Capture mode, we need to power + up immediately. */ + if (ratCh->mode == RF_RatModeCapture) + { + /* Use immediate timeout orcing the RF core to be powered up. */ + *dispatchTimeClockTicks = 0; + + /* No point to look to the other RAT channels.*/ + break; + } + else + { + /* Decode the compareTime field. */ + uint32_t compareTime = ((rfc_CMD_SET_RAT_CMP_t*)&ratCh->chCmd)->compareTime; + + /* Calculate the remained time until this RAT event. The calculation takes + into account the minimum power cycle time. */ + uint32_t deltaTimeUs = RF_calculateDeltaTimeUs(compareTime, + RF_currClient->clientConfig.nPowerUpDuration + + RF_currClient->clientConfig.nPowerUpDurationMargin + + (RF_RAT_COMPENSATION_TIME_US * RF_ratModule.numActiveChannels)); + + /* Scale the value to clock ticks. */ + uint32_t deltaTimeClockTicks = deltaTimeUs / ClockP_tickPeriod; + + /* If this is the closest RAT event, update the timer. */ + if (deltaTimeClockTicks < (*dispatchTimeClockTicks)) + { + *dispatchTimeClockTicks = deltaTimeClockTicks; + } + + } + } + } + + /* Return with true if the dispatchTime represents a valid timestamp. */ + return(validTime); +} + +/* + * Arms a given RAT channel. The mode of the channel will define which mode + * it is being configured to. The cmd variable contains the raw word to be + * sent to the RF core. + * + * Input: ratCh - Pointer to a RAT channel. + * Return: status - Status code based on the response of RF core. + * + */ +static RF_Stat RF_ratArmChannel(RF_RatChannel* ratCh) +{ + /* Local variable */ + RF_Stat status = RF_StatError; + + /* Only those channels can be programmed which are in pending state. */ + if (ratCh && (ratCh->status == RF_RatStatusPending)) + { + /* Calculate the channel interrupt flag based on the handle. */ + uint32_t ratChIntFlag = (1 << (RFC_DBELL_RFHWIFG_RATCH5_BITN + ratCh->handle)); + + /* Clear and enable the interrupt source for that particular channel. */ + RFCHwIntClear(ratChIntFlag); + RFCHwIntEnable(ratChIntFlag); + + /* Set the power constraint on this channel to keep the RF core ON. */ + RF_powerConstraintSet((RF_PowerConstraintSrc)(1 << ratCh->handle)); + + /* Send the command to the RF core. */ + status = RF_executeDirectImmediateCmd((uint32_t)&ratCh->chCmd, NULL); + + /* If the channel configuration is succesfull. */ + if (status == RF_StatCmdDoneSuccess) + { + /* Send the IO command to the RF core if there is any configured. */ + if (ratCh->ioCmd) + { + status = RF_executeDirectImmediateCmd((uint32_t)ratCh->ioCmd, NULL); + } + + /* If both the channel and io configuration is succesfull. */ + if (status == RF_StatCmdDoneSuccess) + { + ratCh->status = RF_RatStatusRunning; + } + } + } + + /* Return with the status code. */ + return(status); +} + +/* + * Restarts any RAT channels which are in pending state at the moment of + * invoking this method. This is used to automatically restore the rat module + * right after the RF core is powered up. This is essential for power management. + * + * Input: none + * Return: none + * + */ +static void RF_ratRestartChannels(void) +{ + /* Iterate through the RAT containers and restore the channels + which were in running state before we entered Standby mode. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Convert the index to a pointer. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* If the channel is in pending state, program it. */ + if (ratCh && (ratCh->status == RF_RatStatusPending)) + { + /* Try to program the RAT channel. */ + RF_Stat status = RF_ratArmChannel(ratCh); + + /* Execute error handling if programming fails, i.e. due to past timestamp. + This is done in SWI context. */ + if (status != RF_StatCmdDoneSuccess) + { + /* Mark the event as an error by setting also a shadow bit. */ + RF_ratModule.pendingInt |= ((RF_RAT_INTERRUPT_BASE_INDEX | RF_RAT_ERROR_BASE_INDEX) << ratCh->handle); + + /* Post the SWI handler to serve the callback. */ + SwiP_or(&RF_swiHwObj, 0); + } + } + } +} + +/* + * Suspends any RAT channel which are in RUNNING state. + * This is used to force all RAT channels into pending state allowing the power + * management to power off the RF core power domain and resynchronize the RAT channels + * on next power up. + * + * Input: none + * Return: none + */ +static void RF_ratSuspendChannels(void) +{ + /* Iterate through the RAT containers and suspend the active channels. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Set a pointer to the channel. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* Only actively running channles can be suspended. */ + if (ratCh && ratCh->status) + { + /* Set the status to be suspended. */ + ratCh->status = RF_RatStatusPending; + + /* Clear the power constraint of this channel */ + RF_powerConstraintRelease((RF_PowerConstraintSrc)(1 << ratCh->handle)); + } + } +} + +/* + * Read the counter value from the RAT timer. + * + * Input: none + * Return: time - The value found in the RATCNT running register. + */ +static uint32_t RF_ratGetValue(void) +{ + return(HWREG(RFC_RAT_BASE + RFC_RAT_O_RATCNT)); +} + +/* + * Read the channel value from the RAT timer. + * + * Input: ratHandle - The handle to the channel. + * Return: timeout - The value found in the RATCHxVAL register. + */ +static uint32_t RF_ratGetChannelValue(RF_RatHandle ratHandle) +{ + /* Read the channel value. */ + return(HWREG(RFC_RAT_BASE + RFC_RAT_O_RATCH5VAL + ratHandle * sizeof(uint32_t))); +} + +/* + * Generate a command which can be used to configure a RAT channel into COMPARE mode. + * + * Input: ratCh - Pointer to the channel. + * ratConfig - Configuration structure holding the channel setup. + * Return: none + */ +static void RF_ratGenerateChCmd(RF_RatChannel* ratCh, void* ratConfig) +{ + /* Generate a command based on the mode. */ + if (ratCh->mode == RF_RatModeCompare) + { + /* Local pointer to cast the configuration to the proper type. */ + RF_RatConfigCompare* ratCompareConfig = (RF_RatConfigCompare*) ratConfig; + + /* Point a pointer to the generic command field within the channels context. */ + rfc_CMD_SET_RAT_CMP_t* pCmd = (rfc_CMD_SET_RAT_CMP_t*)&ratCh->chCmd; + + /* Populate the command structure properly. */ + pCmd->commandNo = CMD_SET_RAT_CMP; /* Instruct the RF core to use COMPARE mode. */ + pCmd->ratCh = RF_RAT_CH_LOWEST + ratCh->handle; /* Encode the selected channel number. */ + pCmd->compareTime = ratCompareConfig->timeout; /* Select the compare timeout. */ + } + else if (ratCh->mode == RF_RatModeCapture) + { + /* Local pointer to cast the configuration to the proper type. */ + RF_RatConfigCapture* ratCaptureConfig = (RF_RatConfigCapture*) ratConfig; + + /* Point a pointer to the generic command field within the channels context. */ + rfc_CMD_SET_RAT_CPT_t* pCmd = (rfc_CMD_SET_RAT_CPT_t*)&ratCh->chCmd; + + /* Calculate the direct command to be sent to the RF core.*/ + pCmd->commandNo = CMD_SET_RAT_CPT; /* Instruct the RF core to use CAPTURE mode. */ + pCmd->config.ratCh = RF_RAT_CH_LOWEST + ratCh->handle; /* Encode the selected channel number. */ + pCmd->config.inputSrc = ratCaptureConfig->source; /* Select the source to be captured. */ + pCmd->config.inputMode = ratCaptureConfig->captureMode; /* Select the mode of capture: raising, falling, etc*/ + pCmd->config.bRepeated = ratCaptureConfig->repeat; /* Select if we should re-arm the channel after a capture event. */ + } +} + +/* + * Generate a command which can be used to configure an IO for a particular RAT channel. + * + * Input: ratCh - Pointer to the channel. + * ioConfig - Configuration channel for the IO. + * Return: cmdToDoorbell - Return with the command structure. It is casted to uint32_t as it is + * stored in a generic variable. + */ +static void RF_ratGenerateIoCmd(RF_RatChannel* ratCh, RF_RatConfigOutput* ioConfig) +{ + /* Local variable. */ + uint32_t cmdToDoorbell = 0; + + /* If there is an IO configuration. */ + if (ioConfig) + { + cmdToDoorbell |= ioConfig->select << 2; + cmdToDoorbell |= ioConfig->mode << 5; + cmdToDoorbell |= (uint32_t)(RF_RAT_CH_LOWEST + ratCh->handle) << 8; + + cmdToDoorbell = (uint32_t)CMDR_DIR_CMD_2BYTE(CMD_SET_RAT_OUTPUT, cmdToDoorbell); + } + + /* Return with the raw command to be sent to the doorbell. */ + ratCh->ioCmd = cmdToDoorbell; +} + +/* + * Wrapper function to setup a RAT channel into the selected mode. + * + * Input: ratClient - Handle previously returned by RF_open(). + * ratMode - Identifies the mode the channel is being set up: RF_RatModeCompare or RF_RatModeCapture. + * ratCallback - Callback function to be registered to the RAT channel. + * ratChannel - Preferred channel to be allocated. If RF_RatChannelAny is provided, allocatethe first available channel. + * ratConfig - Configuration structure holding the setup of the particulare channel. + * ioConfig - Configuration strucutre of the assosiated GPO setup. + * Return: ratHandle - RF_RatHandle to the allocated channel. If allocation fails, RF_ALLOC_ERROR is returned. + */ +static RF_RatHandle RF_ratSetupChannel(RF_Handle ratClient, RF_RatMode ratMode, RF_RatCallback ratCallback, RF_RatHandle ratChannel, void* ratConfig, RF_RatConfigOutput* ioConfig) +{ + /* Return with an error. Either we couldn't allocate any RAT + channel, or the RAT module declined our configuration. */ + RF_RatHandle ratHandle = (RF_RatHandle)RF_ALLOC_ERROR; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Find and allocate a RAT channel (if any is available) */ + RF_RatChannel* ratCh = RF_ratAllocChannel(ratChannel); + + /* If we could allocate a RAT channel */ + if (ratCh) + { + /* Populate the container. Use the default "do nothing" callback + if no user callback is provided and generate the command based + on the mode of the channel. */ + ratCh->pClient = ratClient; + ratCh->mode = ratMode; + ratCh->pCb = (RF_RatCallback)RF_defaultCallback; + RF_ratGenerateChCmd(ratCh, ratConfig); + RF_ratGenerateIoCmd(ratCh, ioConfig); + + /* If there is a user callback provided, override the default callback. */ + if (ratCallback) + { + ratCh->pCb = ratCallback; + } + + /* Decide which PHY should be used upon first start up. */ + if (RF_currClient == NULL) + { + RF_currClient = ratCh->pClient; + } + + /* Calculate the RAT/RTC timestamp to be used to wake the RF core. */ + RF_dispatchNextEvent(); + + /* Return with the handle upon success. */ + ratHandle = (RF_RatHandle)ratCh->handle; + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with either an error OR a handle to a RAT channel. */ + return ratHandle; +} + +/* + * Poll the RFACKIFG and clear the flag afterwards. This is used during the power up sequence + * of the RF core where interlaying processing is implemented. + * + * Input: none + * Return: none + */ +static void RF_dbellSyncOnAck(void) +{ + while (!HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG)); + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0; +} + +/* + * Submit a command to the doorbell without blocking command execution. This is used during the + * power up sequence where the system CPU can continue with processing data while the RF core + * executes the submitted command. + * + * Input: rawCmd - The raw command to be written to the doorbell. This can be a pointer or a + * a direct/immediate command. + * Return: none + */ +static void RF_dbellSubmitCmdAsync(uint32_t rawCmd) +{ + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0; + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) = rawCmd; +} + +/* + * Wake up notification callback from the power driver. If the callback is from RF wakeup + * set constraint to let RF Driver control the XOSC switching else do nothing in the + * callback. + * + * Input: eventType - The type of event when the notification is invoked + * eventArg - Not used. + * clientArg - Not used. + * Return: Power_NOTIFYDONE + */ +static uint8_t RF_wakeupNotification(uint8_t eventType, uint32_t *eventArg, uint32_t *clientArg) +{ + /* Check if the callback is for wakeup from standby and if power up clock is running */ + if ((eventType == PowerCC26XX_AWAKE_STANDBY) && (ClockP_isActive(&RF_clkPowerUpObj))) + { + /* Calculate time (in us) until next trigger (assume next trigger is max ~70 min away) */ + uint32_t timeInUsUntilNextTrig = ClockP_tickPeriod * ClockP_getTimeout(&RF_clkPowerUpObj); + + /* Check if the next trig time is close enough to the actual power up */ + if (timeInUsUntilNextTrig < RF_WAKEUP_DETECTION_WINDOW_IN_US) + { + /* Stop power up clock */ + ClockP_stop(&RF_clkPowerUpObj); + + /* Setup RF Driver to do the XOSC_HF switching */ + Power_setConstraint(PowerCC26XX_SWITCH_XOSC_HF_MANUALLY); + + /* Set variable to indicate RF Driver will do the XOSC_HF switching */ + RF_core.manualXoscHfSelect = true; + + /* Start the RF Core power up */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventWakeup); + } + } + + return(Power_NOTIFYDONE); +} + +/* + * Execute RF power down sequence. + * + * Input: none + * Return: none + */ +static void RF_corePowerDown(void) +{ + /* Local variables to calculate active time in current window. */ + uint32_t deltaTimeInUs = 0; + + /* Disable all CPE and HW interrupts as we are about to power down the core. + Clearing is not important as content will be lost anyway. */ + RFCCpeIntDisable(~0); + RFCHwIntDisable(~0); + + /* Exchange the hwi service routine. */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0PowerFsm, (uintptr_t)NULL); + + /* Set VCOLDO reference */ + RFCAdi3VcoLdoVoltageMode(false); + + /* Take wake up timestamp and the current timestamp */ + uint32_t rtcTimestampB = (uint32_t) AONRTCCurrent64BitValueGet(); + + /* Find the radio core active delta time since the last power up. */ + deltaTimeInUs = UDIFF(RF_rtcTimestampA, rtcTimestampB); + deltaTimeInUs >>= RF_RTC_CONV_TO_US_SHIFT; + + /* Accumulate the delta time with the previous active time windows. Avoid overflow by using saturation. */ + RF_core.activeTimeUs = ADD(RF_core.activeTimeUs, deltaTimeInUs); + + /* Decide whether to send the CMD_SYNC_STOP_RAT command. If this is first power down (.init) or active time (activeTimeInUs) + is longer than the time that can cause maximum allowed error between RAT and RTC clocks. Yielding will automatically fulfill + the latter. */ + if (!(RF_core.init) || + (RF_core.activeTimeUs > (RF_errTolValInUs << RF_DEFAULT_COMB_XTAL_DRIFT_BITS_SHIFT))) + { + /* Stop and synchronize the RAT if it is running */ + if (RF_ratIsRunning()) + { + /* Setup RAT_SYNC command to follow powerdown. */ + RF_ratSyncCmd.stop.commandNo = CMD_SYNC_STOP_RAT; + RF_ratSyncCmd.stop.status = IDLE; + RF_ratSyncCmd.stop.condition.rule = COND_NEVER; + RF_ratSyncCmd.stop.startTrigger.triggerType = TRIG_NOW; + RF_ratSyncCmd.stop.pNextOp = NULL; + + /* Send RAT Stop command and synchronously wait until it run. */ + RF_dbellSubmitCmdAsync((uint32_t)&RF_ratSyncCmd.stop); + while (!(RF_ratSyncCmd.stop.status & RF_CMD_TERMINATED)); + } + + /* The RF core is now initialized and RAT is synchronized. */ + RF_core.init = true; + RF_core.activeTimeUs = 0; + } + + /* Turn off Synth */ + RFCSynthPowerDown(); + + /* Turn off the RF core by gating its clock. This is a quick way to have it shut off. */ + RFCClockDisable(); +} + +/*-------------- Power constraints internal functions ------------------------*/ + +/* + * Set RF power constraints. + * + * Input: src - RF_PowerConstraintSrc (Source: Queue or RAT) + * Return: none + */ +void RF_powerConstraintSet(RF_PowerConstraintSrc src) +{ + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Set constraint based on source */ + RF_powerConstraint |= src; + + /* Exit critical section */ + HwiP_restore(key); +} + +/* + * Release RF power constraints. + * + * Input: src - RF_PowerConstraintSrc (Source: Queue or RAT) + * Return: none + */ +void RF_powerConstraintRelease(RF_PowerConstraintSrc src) +{ + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Release this constraint. */ + RF_powerConstraint &= ~src; + + /* Check if all constraints are clear. */ + if (!(RF_powerConstraint & RF_PowerConstraintCmdQ)) + { + /* Initiate power down if the above criterion is met. + The RAT timer though might will prevent us to proceed. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventPowerDown); + } + + /* Exit critical section. */ + HwiP_restore(key); +} + +/* + * Get RF power constraints. + * + * Input: src - Mask of constraints we requesting + * Return: Bitwise-OR of the power constraints set and the input argument + */ +RF_PowerConstraintSrc RF_powerConstraintGet(RF_PowerConstraintSrc src) +{ + /* Set constraint based on source */ + return (RF_PowerConstraintSrc)(RF_powerConstraint & (uint8_t)src); +} + +/* + * It calculates and returns the closest RF event in time if any. + * + * Calling context: Hwi, Swi + * + * Input: dispatchTime - pointer to a container where the calculated time can be returned + * Return: ticks - If command is far away in future. + * 0 - If command is too close and should be scheduled now. + */ +static bool RF_calculateDispatchTime(uint32_t* dispatchTimeClockTicks) +{ + /* Local variables. */ + uint32_t deltaTimeCmdClockTicks; + uint32_t deltaTimeRatClockTicks; + + /* Initialize return value. */ + *dispatchTimeClockTicks = 0; + + /* Calculate the timestamp of the next command in the command queue. */ + bool validCmdTime = RF_cmdDispatchTime(&deltaTimeCmdClockTicks); + + /* If any of the RAT timers expire before the command should be dispatched, + reprogram the power up clock to the RAT event instead. */ + bool validRatTime = RF_ratDispatchTime(&deltaTimeRatClockTicks); + + if (validCmdTime && validRatTime) + { + /* Determine if command execution or RAT event comes first. */ + *dispatchTimeClockTicks = MIN(deltaTimeCmdClockTicks, deltaTimeRatClockTicks); + } + else if (validCmdTime) + { + /* Command queue determines the next event. */ + *dispatchTimeClockTicks = deltaTimeCmdClockTicks; + } + else if (validRatTime) + { + /* RAT timer determines the next event. */ + *dispatchTimeClockTicks = deltaTimeRatClockTicks; + } + + /* If any of them valid, return with true indicating a valid dispatch time. */ + return (validCmdTime || validRatTime); +} + +/* + * Dispatch the closest event generated either by a command or the RAT timer. + * If the RF core is powered, it triggs the HWI to execute the dispatcher. + * If the RF core is not powered, it decides if it should be powered ON immediately, or + * the execution can be deferred to a later timestamp. In the latter case, the RTC is used to keep + * track of proper timing. + * + * Input: none + * Return: none + * + */ +static void RF_dispatchNextEvent(void) +{ + if (RF_core.status == RF_CoreStatusActive) + { + /* Kick the HWI to dispatch the next pending event. */ + HwiP_post(INT_RFC_CPE_0); + } + else if (RF_core.status == RF_CoreStatusPoweringUp) + { + /* Do nothing. We will dispatch the next event at the end + of power-up sequence naturally. */ + } + else + { + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Calculate dispatch time. */ + uint32_t dispatchTimeClockTicks; + bool validTime = RF_calculateDispatchTime(&dispatchTimeClockTicks); + + if (validTime) + { + /* Decide whether the command should be dispatched. */ + if (dispatchTimeClockTicks) + { + /* Dispatch command in the future. */ + RF_restartClockTimeout(&RF_clkPowerUpObj, dispatchTimeClockTicks); + } + else + { + /* Dispatch the event immediately. Clock is not needed anymore. */ + ClockP_stop(&RF_clkPowerUpObj); + + /* Initiate powering up the RF core. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventWakeup); + } + } + else + { + /* There is no event to be dispatched. */ + ClockP_stop(&RF_clkPowerUpObj); + } + + /* Exit critical section. */ + HwiP_restore(key); + } +} + +/* + * Update the cached FS command. + * + * Calling context: Hwi, Swi + * + * Input: pCmd - Pointer to radio operation command + * Return: none + */ +static void RF_cacheFsCmd(RF_Cmd* pCmd) +{ + /* Upper limit of the number of operations in a chain */ + uint8_t nCmdChainMax = RF_MAX_CHAIN_CMD_LEN; + + /* Traverse the chain */ + RF_Op* pOp = pCmd->pOp; + while (pOp && nCmdChainMax) + { + /* If the operation is a CMD_FS or CMD_FS_OFF */ + if ((pOp->commandNo == CMD_FS) || (pOp->commandNo == CMD_FS_OFF)) + { + /* Create a copy of the first CMD_FS command (or CMD_FS_OFF) for later power up */ + memcpy(&pCmd->pClient->state.mode_state.cmdFs, pOp, sizeof(pCmd->pClient->state.mode_state.cmdFs)); + break; + } + + /* Step the chain */ + pOp = pOp->pNextOp; + + /* Avoid infinit loop (in case of closed loops) */ + --nCmdChainMax; + } +} + +/* + * Verify if the given command is a setup command. + * + * Calling context: Hwi, Swi + * + * Input: pOp - Pointer to radio operation. + * Return: true - The given command is a setup command. + * false - The given command is not a setup command. + */ +static bool RF_isRadioSetup(RF_Op* pOp) +{ + /* Verify the command ID against the known setup commands. */ + switch(pOp->commandNo) + { + case (CMD_RADIO_SETUP): + case (CMD_BLE5_RADIO_SETUP): + case (CMD_PROP_RADIO_SETUP): + case (CMD_PROP_RADIO_DIV_SETUP): + /* The given radio operation is indead a setup command. */ + return(true); + default: + /* Do nothing. */ + return(false); + } +} + +/* + * Ensure that the setup command is properly initialized. + * + * Input: handle - Pointer to the client. + * Return: None + */ +static void RF_initRadioSetup(RF_Handle handle) +{ + /* Local variables. */ + bool update = handle->clientConfig.bUpdateSetup; + + /* Decode the setup command. */ + RF_RadioSetup* radioSetup = handle->clientConfig.pRadioSetup; + radioSetup->common.status = IDLE; + + /* Adjust the setup command if needed. */ + switch (radioSetup->common.commandNo) + { + case (CMD_RADIO_SETUP): + case (CMD_BLE5_RADIO_SETUP): + /* Configure that the frequency synthetizer should be powered up */ + radioSetup->common.config.bNoFsPowerUp = 0; + + /* If requested, also change the analog configuration during power up */ + if (update) + { + radioSetup->common.config.analogCfgMode = RF_SETUP_ANALOGCFG_UPDATE; + } + else + { + radioSetup->common.config.analogCfgMode = RF_SETUP_ANALOGCFG_NOUPDATE; + } + break; + + case (CMD_PROP_RADIO_SETUP): + case (CMD_PROP_RADIO_DIV_SETUP): + /* Configure that the frequency synthetizer should be powered ON */ + radioSetup->prop.config.bNoFsPowerUp = 0; + + /* If requested, also change the analog configuration during power up */ + if (update) + { + radioSetup->prop.config.analogCfgMode = RF_SETUP_ANALOGCFG_UPDATE; + } + else + { + radioSetup->prop.config.analogCfgMode = RF_SETUP_ANALOGCFG_NOUPDATE; + } + break; + default: + break; + } + + /* Clear the update request flag as it was handled by now. */ + handle->clientConfig.bUpdateSetup = false; +} + +/* + * Submit the pending command to the RF Core. + * + * Input: none + * Return: none + */ +static void RF_dispatchNextCmd(void) +{ + /* First element in the pend queue */ + RF_Cmd* pNextCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + /* If there is no running command, dispatch the next pending in the queue */ + if (!RF_cmdQ.pCurrCmd) + { + if (pNextCmd) + { + /* Calculate the timestamp of the next command in the command queue. */ + uint32_t dispatchTimeClockTicks; + bool validTime = RF_cmdDispatchTime(&dispatchTimeClockTicks); + + /* Dispatch command in the future, if there is a command and the dispatch time is not 0 (immediate) */ + if (validTime && dispatchTimeClockTicks) + { + /* Command sufficiently far into future that it shouldn't be dispatched yet. + Release RF power constraint and potentially power down radio */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + } + else + { + /* Set power constraint on the command queue, since there is now a running command. */ + RF_powerConstraintSet(RF_PowerConstraintCmdQ); + + /* Command now sent to the RF Core. Move it from pending queue to the current command */ + RF_cmdQ.pCurrCmd = (RF_Cmd*)List_get(&RF_cmdQ.pPend); + + /* Dispatch command immediately. Clear and enable the requested interrupt sources of the command */ + RFCCpeIntClear((uint32_t) (pNextCmd->bmEvent)); + RFCCpeIntEnable((uint32_t)(pNextCmd->bmEvent)); + RFCHwIntClear((uint32_t) (pNextCmd->bmEvent >> RF_SHIFT_32_BITS)); + RFCHwIntEnable((uint32_t) (pNextCmd->bmEvent >> RF_SHIFT_32_BITS)); + + /* Decode the radio operation itself. */ + RF_Op* pOp = (RF_Op*)pNextCmd->pOp; + + /* Dispatch immediately, set command to current and remove from pending queue */ + RFCDoorbellSendTo((uint32_t)pOp); + + /* If the command is a new setup command, notify the board file. */ + if (RF_isRadioSetup((RF_Op*)pOp)) + { + /* Invoke the global callback if the setup command changed. This is needed to + adjust front-end according to the new PHY. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioSetup, (void*)pOp); + } + } + } + else + { + /* No more pending command in the queue */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventLastCommandDone); + } + } +} + +/* + * Check if there was an error with the synth while running CMD_FS + * error callback is not issued in this function. + * + * Input: none + * Return: true - If there was an error. + * false - If there was no error. + */ +static bool RF_checkCmdFsError(void) +{ + /* Take the handle of the current client */ + RF_Handle pObj = RF_currClient; + + /* Find the FS command stored in the context of the client */ + RF_Op *tmp1 = (RF_Op*)&pObj->clientConfig.pRadioSetup->prop; + while (tmp1->pNextOp && tmp1->pNextOp != (RF_Op*)&pObj->state.mode_state.cmdFs) + { + tmp1 = tmp1->pNextOp; + } + + /* Evaluate if the FS command succeeded */ + if ((tmp1->condition.rule == COND_ALWAYS) && + (pObj->state.mode_state.cmdFs.status == ERROR_SYNTH_PROG)) + { + /* CMD_FS completed with error so return true */ + return(true); + } + else + { + /* There is no synth error so return false */ + return(false); + } +} + +/* + * RF HW ISR when radio is active. + * + * Input: a - Not used. + * Return: none + */ +static void RF_hwiHw(uintptr_t a) +{ + /* Prepare a direct command. */ + RF_Cmd* pCmd = RF_cmdQ.pCurrCmd; + + /* Read and clear the interrupt flags. */ + uint32_t rfchwifg = RFCHwIntGetAndClear(RF_HW_INT_CPE_MASK | RF_HW_INT_RAT_CH_MASK); + uint32_t rfchwien = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) & RF_HW_INT_CPE_MASK; + uint32_t rathwien = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) & RF_HW_INT_RAT_CH_MASK; + + /* Check for CPE interrupts. These belong to the FSM statem-achine. */ + if (rfchwifg & rfchwien) + { + if (pCmd) + { + /* Store the command which callback need to be served */ + RF_cmdQ.pCurrCmdCb = pCmd; + + /* Decode the event numeber. */ + RF_EventMask events = ((RF_EventMask)(rfchwifg & rfchwien) << RF_SHIFT_32_BITS); + + /* Store the events within the context of the command for the callback. */ + RF_cmdStoreEvents(pCmd, events); + + /* Trig the state machine to handle this event */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventCpeInt); + } + } + + /* Check for RAT channel events. These belong to the HW SWI. */ + if (rfchwifg & rathwien) + { + /* Store the channel which cause the interrupt */ + RF_ratModule.pendingInt |= (rfchwifg & rathwien) >> RFC_DBELL_RFHWIFG_RATCH5_BITN; + + /* Post the swi to handle its callback */ + SwiP_or(&RF_swiHwObj, 0); + } +} + + +/* + * Software interrupt handler which servers Radio Timer (RAT) related events. + * + * Input: a - Generic argument. Not used. + * b - Generic argument. Not used. + * Return: none + */ +static void RF_swiHw(uintptr_t a, uintptr_t b) +{ + /* Local variable */ + bool error = false; + + /* If the interrupt was trigged due to one of the RAT channels. */ + if (RF_ratModule.pendingInt) + { + /* Process lower channel first and allow multiple interrupt flags to be processed sequentially. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + if (RF_ratModule.pendingInt & (RF_RAT_INTERRUPT_BASE_INDEX << i)) + { + /* If there is also a bit indicating that the interrupt is due to an error. */ + if (RF_ratModule.pendingInt & (RF_RAT_ERROR_BASE_INDEX << i)) + { + error = true; + } + + /* Enter critical section. */ + uint32_t key= HwiP_disable(); + + /* Atomic read-modify-write instruction of the interrupt flags. + Knowing that this is the only place when such a flag can be cleared, it is safe to only guard this + operation. Additional flags (which have been raised in the meantime) will be reserved and served in the + next iteration. */ + RF_ratModule.pendingInt &= ~((RF_RAT_INTERRUPT_BASE_INDEX | RF_RAT_ERROR_BASE_INDEX) << i); + + /* Exit critical section. */ + HwiP_restore(key); + + /* Convert the channel index to a pointer of rat configuration. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* Serve the interrupt if it is from an active channel. This is to avoid decoding function + pointers from invalid containers due to fantom interrupts. */ + if (ratCh && ratCh->status) + { + /* Read the channel counter from the RAT timer. In capture mode this is the captured value, + in compare mode this is the compare timestamp.*/ + uint32_t compareCaptureValue = RF_ratGetChannelValue(ratCh->handle); + + /* Temporarily store the callback handler and the channel offset. + This is necessary in order to be able to free and reallocate the + same channel within the context of the callback itself. */ + RF_Handle ratClient = (RF_Handle) ratCh->pClient; + RF_CmdHandle ratHandle = (RF_CmdHandle) ratCh->handle; + RF_RatCallback ratCallback = (RF_RatCallback) ratCh->pCb; + + /* Only free the channel if it is NOT in repeated capture mode, or an error occured. */ + if (error || !(ratCh->mode == RF_RatModeCapture) || !(ratCh->chCmd & RF_RAT_CAPTURE_REPEAT_MODE)) + { + /* Free RAT channel. If this is the last channel, it might delay with 1 LF edge to + calculate the next wake up event. */ + RF_ratFreeChannel(ratCh); + } + + /* Serve the user callback with Error or Compare/Capture Event. */ + if (error) + { + ratCallback(ratClient, ratHandle, RF_EventError, 0); + } + else + { + ratCallback(ratClient, ratHandle, RF_EventRatCh, compareCaptureValue); + } + } + + /* Only serve one channel at a time. */ + break; + } + } + } + + /* Repost the SWI again if multiple interrupt flags are still set. */ + if (RF_ratModule.pendingInt) + { + SwiP_or(&RF_swiHwObj, 0); + } +} + +/* + * The CPE0 ISR when radio is active. Assume that all IRQs relevant to command + * dispatcher are mapped here. Furthermore, assume that there is no need for + * critical sections here (i.e. that this ISR has higher priority than + * any HWI calling a RF API function or that HWIs can't call the RF API). + * + * Input: a - Not used. + * Return: none + */ +static void RF_hwiCpe0Active(uintptr_t a) +{ + /* Local variables. */ + RF_Cmd* volatile* ppActiveCmd = &RF_cmdQ.pCurrCmd; + uint32_t rfcpeifgMask = 0; + uint32_t rfcpeifg = 0; + uint32_t nextEvent = 0; + + /* If there was a command running (handles both foreground and background context). */ + if (*ppActiveCmd) + { + /* Decode the events the active command subscribed to. */ + rfcpeifgMask = (*ppActiveCmd)->bmEvent; + + /* Read the interrupt flags which belong to the active command (including the mandatory termination events). */ + rfcpeifg = RFCCpeIntGetAndClear(rfcpeifgMask); + + /* Save the events happened and to be passed to the callback. */ + RF_cmdStoreEvents((*ppActiveCmd), rfcpeifg); + + /* Look for termination events. */ + if (rfcpeifg & RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M) + { + /* Disable interrupt sources which were subsribed by the command. Since the LAST_CMD_DONE is + is shared with the state machine, it cannot be disabled. */ + RFCCpeIntDisable((uint32_t)((*ppActiveCmd)->bmEvent & ~RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M)); + RFCHwIntDisable((uint32_t) ((*ppActiveCmd)->bmEvent >> RF_SHIFT_32_BITS)); + + /* Move active command to done queue. */ + List_put(&RF_cmdQ.pDone, (List_Elem*)(*ppActiveCmd)); + + /* Retire the command, it is not running anymore. */ + (*ppActiveCmd) = NULL; + + /* We will invoke the callback and deallocate the command. */ + nextEvent |= RF_FsmEventLastCommandDone; + } + else if (rfcpeifg) + { + /* The interrupt is just an ordinary event without termination. */ + RF_cmdQ.pCurrCmdCb = (*ppActiveCmd); + + /* We will just invoke the callback. */ + nextEvent |= RF_FsmEventCpeInt; + } + } + + /* Post SWI to handle registered callbacks if there is any. */ + if (nextEvent) + { + SwiP_or(&RF_swiFsmObj, nextEvent); + } + + /* Restart pending rat channels. */ + RF_ratRestartChannels(); + + /* Dispatch the next pending command if exists. */ + RF_dispatchNextCmd(); +} + +/* + * Clock callback due to inactivity timeout. + * + * Input: pObj - Not used. + * Return: none + */ +static void RF_clkInactivityCallback(uintptr_t a) +{ + /* If there are no pending commands in the queue */ + if (RF_cmdQ.nSeqPost == RF_cmdQ.nSeqDone) + { + /* Release the constraint on the command queue and if nothing prevents, power down the radio */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + } +} + +/* + * Callback used to post semaphore for runCmd() and pendCmd(). + * + * Input: h - Handle to the client. + * ch - Handle to the command which callback to be invoked. + * e - Events causing the function call. + * Return: none + */ +static void RF_syncCb(RF_Handle h, RF_CmdHandle ch, RF_EventMask e) +{ + /* Local variables */ + RF_Cmd* pCmd; + + /* If there is a user callback provided. */ + if (h->state.pCbSync) + { + /* Invoke the user callback with the events fired. */ + ((RF_Callback)h->state.pCbSync)(h, ch, e); + } + + /* Mask the possible causes of releasing the semaphore */ + RF_EventMask maskedEvents = (e & h->state.eventSync); + + /* Release the semaphore on any of the reasons: last command done, + subscribed event happened, last FG command is done in IEEE mode */ + if (maskedEvents) + { + /* Find the command. We do it here within the SWI context. */ + pCmd = RF_cmdGet(ch, RF_CMD_ALLOC_FLAG); + + /* Store the events in the context of the client */ + h->state.unpendCause = maskedEvents; + + /* Find the command. We do it here within the SWI context. */ + if (pCmd) + { + /* Clear the handled past events so it is possible to pend again */ + pCmd->pastifg &= ~h->state.unpendCause; + + /* Exhange the callback function: use the user callback from this point */ + pCmd->pCb = (RF_Callback)h->state.pCbSync; + } + + /* Clear temporary storage of user callback (it was restored and served at this point) */ + h->state.pCbSync = NULL; + + /* Post the semaphore to release the RF_pendCmd() */ + SemaphoreP_post(&h->state.semSync); + } +} + +/* + * Invoke the global callback registered through the RFCC26XX_hwAttrs. + * + * Input: e - Events causing the function call. + * Return: none + */ +static void RF_invokeGlobalCallback(RF_GlobalEvent event, void* arg) +{ + /* Decode the global callback and it's mask ro mthe board file. */ + RF_GlobalCallback callback = RFCC26XX_hwAttrs.globalCallback; + RF_GlobalEventMask eventMask = RFCC26XX_hwAttrs.globalEventMask; + + /* If the board has subscribed to this event, invoke the callback. */ + if (callback && (eventMask & event)) + { + callback(RF_currClient, event, arg); + } +} + +/* + * Default callback function. + * + * Input: h - Handle to the client. + * ch - Handle to the command which callback to be invoked. + * e - Events causing the function call. + * Return: none + */ +static void RF_defaultCallback(RF_Handle h, RF_CmdHandle ch, RF_EventMask e) +{ + /* Do nothing */; +} + +/*-------------- RF powerup/powerdown FSM functions ---------------*/ + +/* + * The SWI handler for FSM events. + * + * Input: a0 - Not used. + * a1 - Not used. + * Return: none + */ +static void RF_swiFsm(uintptr_t a0, uintptr_t a1) +{ + RF_core.fxn(RF_currClient, (RF_FsmEvent)SwiP_getTrigger()); +} + +/* + * Clock callback called upon powerup. + * + * Input: a - Not used. + * Return: none + */ +static void RF_clkPowerUp(uintptr_t a) +{ + if (RF_core.fxn == RF_fsmActiveState) + { + /* Dispatch the next RF core event. */ + RF_dispatchNextEvent(); + } + else + { + /* Trigger FSM SWI to start the wake up sequence of the radio. + This is important when we poll the XOSC_HF. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventWakeup); + } +} + +/* + * RF CPE0 ISR during FSM powerup/powerdown. + * + * Input: a0 - Not used. + * Return: none + */ +static void RF_hwiCpe0PowerFsm(uintptr_t a0) +{ + /* Read all IRQ flags in doorbell and then clear them */ + uint32_t rfcpeifg = RFCCpeIntGetAndClear(RF_CPE0_INT_MASK); + + /* If the radio is active */ + if (RF_core.fxn == RF_fsmActiveState) + { + /* Change HWI handler to the correct one */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0Active, (uintptr_t)NULL); + + /* Mark radio and client as being active */ + RF_core.status = RF_CoreStatusActive; + + /* No synth error */ + if (!RF_checkCmdFsError()) + { + /* Restart pending rat channels. */ + RF_ratRestartChannels(); + + /* Dispatch the next command */ + RF_dispatchNextCmd(); + } + } + + /* Handle special events as boot, etc */ + if (rfcpeifg & (RFC_DBELL_RFCPEIFG_BOOT_DONE_M | RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M)) + { + SwiP_or(&RF_swiFsmObj, RF_FsmEventPowerStep); + } +} + +/*-------------- Power management state functions ---------------*/ +/* + * Handles RF Core patching for CPE, MCE, RFE (if required) in setup state during power-up. + * + * Input: mode - Not used. + * Return: none + */ +static void RF_applyRfCorePatch(bool mode) +{ + /* Local reference to the patches. */ + void (*cpePatchFxn)(void) = RF_currClient->clientConfig.pRfMode->cpePatchFxn; + void (*mcePatchFxn)(void) = RF_currClient->clientConfig.pRfMode->mcePatchFxn; + void (*rfePatchFxn)(void) = RF_currClient->clientConfig.pRfMode->rfePatchFxn; + + /* Load the patches if relevant for this phy. */ + if (cpePatchFxn != NULL) + { + cpePatchFxn(); + } + + if ((mcePatchFxn != NULL) || (rfePatchFxn != NULL)) + { + /* Wait for clocks to be turned ON */ + RF_dbellSyncOnAck(); + + /* Patch MCE if relevant */ + if (mcePatchFxn != NULL) + { + mcePatchFxn(); + } + + /* Patch RFE if relevant */ + if (rfePatchFxn != NULL) + { + rfePatchFxn(); + } + + /* Turn off additional clocks */ + RFCDoorbellSendTo(CMDR_DIR_CMD_2BYTE(RF_CMD0, 0)); + } +} + +/* + * Arms the inactivity timer and hence postpones the decision whether + * power management shall take place or not. + * + * Input: none + * Return: none + */ +static void RF_setInactivityTimeout(void) +{ + /* Local variables to be used to find the correct timeout value. */ + uint32_t inactivityTimeUs = 0; + + if (RF_currClient->state.bYielded == false) + { + inactivityTimeUs = RF_currClient->clientConfig.nInactivityTimeout; + } + RF_currClient->state.bYielded = false; + + /* If immediate power down is reuqested */ + if (inactivityTimeUs == SemaphoreP_NO_WAIT) + { + /* We can powerdown immediately */ + RF_clkInactivityCallback((uintptr_t)NULL); + } + else if (inactivityTimeUs != SemaphoreP_WAIT_FOREVER) + { + /* Reprogram and start inactivity timer */ + RF_restartClockTimeout(&RF_clkInactivityObj, inactivityTimeUs/ClockP_tickPeriod); + } +} + +/* + * Handle callback to client for RF_EventLastCmdDone and issue radio free callback if required. + * + * Input: none + * Return: none + */ +static void RF_radioOpDoneCb(void) +{ + /* Serve the first entry in the done queue */ + RF_Cmd* pCmd = (RF_Cmd*)List_head(&RF_cmdQ.pDone); + + /* Radio command done */ + if (pCmd) + { + /* Update implicit radio state (chained FS command if any) */ + RF_cacheFsCmd(pCmd); + + /* Read and clear the events */ + RF_EventMask events = pCmd->rfifg; + pCmd->rfifg = 0; + + /* Issue callback, free container and dequeue */ + if (pCmd->pCb) + { + /* If any of the cancel events are set, mask out the other events. */ + RF_EventMask exclusiveEvents = (RF_EventCmdCancelled + | RF_EventCmdAborted + | RF_EventCmdStopped + | RF_EventCmdPreempted); + + /* All other events are masked out if any of the above is present. */ + if (events & exclusiveEvents) + { + events &= exclusiveEvents; + } + + /* Invoke the use callback */ + pCmd->pCb(pCmd->pClient, pCmd->ch, events); + } + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Update num of radio command done */ + RF_cmdQ.nSeqDone = (RF_cmdQ.nSeqDone+1) & N_CMD_MODMASK; + + /* Commmand completed reset command flags */ + pCmd->flags = 0; + + /* Command completed, free command queue container */ + List_get(&RF_cmdQ.pDone); + + /* Exit critical section */ + HwiP_restore(key); + + /* Check if there are any more pending commands */ + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + RF_setInactivityTimeout(); + } + } +} + +/* + * RF state machine function during power up state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmPowerUpState(RF_Object *pObj, RF_FsmEvent e) +{ + /* Note: pObj is NULL in this state */ + if (e & RF_FsmEventLastCommandDone) + { + /* Serve the registered callback function */ + RF_radioOpDoneCb(); + + /* Retrig the SWI if there are more commands in the done queue. */ + if (List_head(&RF_cmdQ.pDone)) + { + /* Trigger self again to serve the callbacks. */ + SwiP_or(&RF_swiFsmObj, (e | RF_FsmEventLastCommandDone)); + } + else + { + /* We've handled this event now */ + e &= ~RF_FsmEventLastCommandDone; + + /* Schedule the next event based on the state of the command queue + and the RAT module. */ + RF_dispatchNextEvent(); + } + } + else if (e & RF_FsmEventWakeup) + { + /* Record a timestamp to be able to calculate the power up duration. */ + RF_rtcTimestampA = AONRTCCurrent64BitValueGet(); + + /* Set current client from first command in command queue */ + RF_Cmd* pNextCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + if (pNextCmd) + { + RF_currClient = pNextCmd->pClient; + } + + /* Set the RF mode in the PRCM register */ + HWREG(PRCM_BASE + PRCM_O_RFCMODESEL) = RF_currClient->clientConfig.pRfMode->rfMode; + + /* Power up RF core power domain. */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + Power_setDependency(PowerCC26XX_DOMAIN_RFCORE); + + /* Start power-up sequence */ + RF_core.status = RF_CoreStatusPoweringUp; + + /* If the configuration on board level requires to set the dependency every time. */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == false) + { + Power_setDependency(PowerCC26XX_XOSC_HF); + } + + /* If there are RFE and MCE patches, turn on their clocks */ + if ((RF_currClient->clientConfig.pRfMode->mcePatchFxn != NULL) || + (RF_currClient->clientConfig.pRfMode->rfePatchFxn != NULL)) + { + RF_dbellSubmitCmdAsync((uint32_t)CMDR_DIR_CMD_2BYTE(RF_CMD0, RFC_PWR_PWMCLKEN_MDMRAM | RFC_PWR_PWMCLKEN_RFERAM)); + } + + /* Turn on clock to RF core */ + RFCClockEnable(); + + /* Reconfigure the CPE interrupt lines to a start up value on a controlled way. */ + RFCCpeIntDisable(RF_CPE0_INT_MASK); + RFCCpe0IntSelect(RF_CPE0_INT_MASK); + + /* Enable some of the interrupt sources. */ + RFCCpeIntEnable(RFC_DBELL_RFCPEIEN_BOOT_DONE_M + | RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M); + + /* Set the next state. */ + RF_core.fxn = RF_fsmSetupState; + + /* Enable interrupts and let BOOT_DONE interrupt kick things off. */ + HwiP_enableInterrupt(INT_RFC_HW_COMB); + HwiP_enableInterrupt(INT_RFC_CPE_0); + } +} + +/* + * RF state machine function during setup state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmSetupState(RF_Object *pObj, RF_FsmEvent e) +{ + if (e & RF_FsmEventPowerStep) + { + /* Apply RF Core patch (if required) */ + RF_applyRfCorePatch(RF_PHY_BOOTUP_MODE); + + /* Initialize bus request */ + RF_dbellSubmitCmdAsync((uint32_t)CMDR_DIR_CMD_1BYTE(CMD_BUS_REQUEST, 1)); + + /* Set VCOLDO reference */ + RFCAdi3VcoLdoVoltageMode(true); + + /* Setup RAT_SYNC command to follow SETUP command */ + RF_ratSyncCmd.start.commandNo = CMD_SYNC_START_RAT; + RF_ratSyncCmd.start.status = IDLE; + RF_ratSyncCmd.start.startTrigger.triggerType = TRIG_NOW; + RF_ratSyncCmd.start.pNextOp = NULL; + RF_ratSyncCmd.start.condition.rule = COND_NEVER; /* Default: don't chain */ + + /* Init the content of setup command. */ + RF_initRadioSetup(pObj); + + /* Configure the SETUP command. */ + RF_RadioSetup* pRadioSetup = pObj->clientConfig.pRadioSetup; + + /* Clear the update request flag as it was handled by now. */ + pObj->clientConfig.bUpdateSetup = false; + + RF_Op* tmp = (RF_Op*)&pRadioSetup->prop; + while ((tmp->pNextOp) && (tmp->pNextOp->commandNo != CMD_SYNC_START_RAT)) + { + tmp = tmp->pNextOp; + } + tmp->pNextOp = (RF_Op*)&RF_ratSyncCmd.start; + tmp->condition.rule = COND_ALWAYS; + + /* Setup FS command to follow SETUP command */ + RF_Cmd* pCmdFirstPend = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + if (pCmdFirstPend && ((pCmdFirstPend->pOp->commandNo == CMD_FS) || (pCmdFirstPend->pOp->commandNo == CMD_FS_OFF))) + { + /* First command is FS command so no need to chain an implicit FS command + Reset nRtc1 */ + RF_rtcTimestampA = 0; + } + else + { + if (pObj->state.mode_state.cmdFs.commandNo) + { + /* Chain in the implicit FS command */ + rfc_CMD_FS_t* pOpFs = &pObj->state.mode_state.cmdFs; + pOpFs->status = IDLE; + pOpFs->pNextOp = NULL; + pOpFs->startTrigger.triggerType = TRIG_NOW; + pOpFs->condition.rule = COND_NEVER; + RF_ratSyncCmd.start.pNextOp = (RF_Op*)pOpFs; + RF_ratSyncCmd.start.condition.rule = COND_ALWAYS; + } + } + + /* Trim directly the radio register values based on the ID of setup command */ + rfTrim_t rfTrim; + RFCRfTrimRead((rfc_radioOp_t*)pRadioSetup, (rfTrim_t*)&rfTrim); + RFCRfTrimSet((rfTrim_t*)&rfTrim); + + /* Make sure BUS_REQUEST is done */ + RF_dbellSyncOnAck(); + + /* Set the next state. */ + RF_core.fxn = RF_fsmActiveState; + + /* Run the XOSC_HF switching if the pre-notify function setup the power + constraint PowerCC26XX_SWITCH_XOSC_HF_MANUALLY */ + if (RF_core.manualXoscHfSelect) + { + /* Wait until the XOSC_HF is stable */ + while (!PowerCC26XX_isStableXOSC_HF()); + + /* Run the XOSC_HF switch */ + PowerCC26XX_switchXOSC_HF(); + } + else if (OSCClockSourceGet(OSC_SRC_CLK_HF) != OSC_XOSC_HF) + { + tmp->condition.rule = COND_NEVER; + RF_core.fxn = RF_fsmXOSCState; + } + + /* Send the setup chain to the RF core */ + RF_dbellSubmitCmdAsync((uint32_t)pRadioSetup); + + /* Invoke the global callback. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioSetup, (void*)pRadioSetup); + } +} + +/* + * RF state machine function during XOSC state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmXOSCState(RF_Object *pObj, RF_FsmEvent e) +{ + if ((e & RF_FsmEventPowerStep) || (e & RF_FsmEventWakeup)) + { + /* If XOSC_HF is now ready */ + if (OSCClockSourceGet(OSC_SRC_CLK_HF) == OSC_XOSC_HF) + { + /* Next state: fsmActiveState */ + RF_core.fxn = RF_fsmActiveState; + + /* Continue with the CMD_RAT_SYNC */ + RF_dbellSubmitCmdAsync((uint32_t)&RF_ratSyncCmd.start); + } + else + { + /* Clock source not yet switched to XOSC_HF: schedule new polling */ + RF_restartClockTimeout(&RF_clkPowerUpObj, RF_XOSC_HF_SWITCH_CHECK_PERIOD_US/ClockP_tickPeriod); + } + } +} + +/* + * RF state machine function during active state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmActiveState(RF_Object *pObj, RF_FsmEvent e) +{ + volatile RF_Cmd* pCmd; + uint32_t rtcValTmp1; + uint32_t rtcValTmp2; + RF_EventMask events; + uint32_t key; + + if (e & RF_FsmEventCpeInt) + { + /* Enter critical section */ + key = HwiP_disable(); + + /* Dereference the command which requested the callback*/ + pCmd = (RF_Cmd*)RF_cmdQ.pCurrCmdCb; + + /* If this is due to other event than LastCmdDone */ + if (pCmd && !(pCmd->rfifg & RF_TERMINATION_EVENT_MASK)) + { + /* Temporarily store the reason of callback */ + events = pCmd->rfifg; + + /* Clear the events which are handled here */ + pCmd->rfifg &= (~events); + + /* Exit critical section */ + HwiP_restore(key); + + /* Invoke the user callback if it is provided */ + if (pCmd->pCb && events) + { + pCmd->pCb(pCmd->pClient, pCmd->ch, events); + } + } + else + { + /* Exit critical section */ + HwiP_restore(key); + } + + /* We've handled this event now */ + e &= ~RF_FsmEventCpeInt; + } + + else if (e & RF_FsmEventPowerStep) + { + /* Enter critical section */ + key = HwiP_disable(); + + /* Update power up duration if coming from the clkPowerUpFxn. Skip the calcualtion + if coming from boot, since the LF clock is derived from RCOSC_HF without calibration. */ + if ((OSCClockSourceGet(OSC_SRC_CLK_LF) != OSC_RCOSC_HF) + && pObj->clientConfig.bMeasurePowerUpDuration + && RF_rtcTimestampA) + { + /* Temporary storage to be able to compare the new value to the old measurement */ + uint32_t prevPowerUpDuration = pObj->clientConfig.nPowerUpDuration; + + /* Take wake up timestamp and the current timestamp */ + rtcValTmp1 = (uint32_t) RF_rtcTimestampA; + rtcValTmp2 = (uint32_t) AONRTCCurrent64BitValueGet(); + + /* Calculate the difference of the timestamps and convert it to us units */ + pObj->clientConfig.nPowerUpDuration = UDIFF(rtcValTmp1, rtcValTmp2); + pObj->clientConfig.nPowerUpDuration >>= RF_RTC_CONV_TO_US_SHIFT; + + /* Low pass filter on power up durations less than in the previous cycle */ + if (prevPowerUpDuration > pObj->clientConfig.nPowerUpDuration) + { + /* Expect that the values are small and the calculation can be done in 32 bits */ + pObj->clientConfig.nPowerUpDuration = (prevPowerUpDuration + pObj->clientConfig.nPowerUpDuration)/2; + } + + /* Power up duration should be within certain upper and lower bounds */ + if ((pObj->clientConfig.nPowerUpDuration > RF_DEFAULT_POWER_UP_TIME) || + (pObj->clientConfig.nPowerUpDuration < RF_DEFAULT_MIN_POWER_UP_TIME)) + { + pObj->clientConfig.nPowerUpDuration = RF_DEFAULT_POWER_UP_TIME; + } + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Check the status of the CMD_FS, if it was sent (chained) to the setup command. + If it failed, return an error callback to the client. + The client can either resend the CMD_FS or ignore the error as per Errata on PG2.1 */ + if (RF_checkCmdFsError()) + { + /* Invoke the error callback: deault is do nothing */ + RF_Callback pErrCb = (RF_Callback)pObj->clientConfig.pErrCb; + pErrCb(pObj, RF_ERROR_CMDFS_SYNTH_PROG, RF_EventError); + + /* Check if there is pending command */ + if (List_head(&RF_cmdQ.pPend)) + { + /* Make sure the next pending command gets dispatched by issuing CPE0 IRQ */ + RF_dispatchNextEvent(); + } + else + { + /* No pending command */ + e |= RF_FsmEventLastCommandDone; + } + } + + /* Issue power up callback: the RF core is active */ + RF_Callback pPowerCb = (RF_Callback)pObj->clientConfig.pPowerCb; + pPowerCb(pObj, 0, RF_EventPowerUp); + + /* We've handled this event now */ + e &= ~RF_FsmEventPowerStep; + } + else if (e & RF_FsmEventLastCommandDone) + { + /* Issue radio operation done callback */ + RF_radioOpDoneCb(); + + /* If there is more entries left in the done queue */ + if (List_empty(&RF_cmdQ.pDone)) + { + /* We've handled this event now */ + e &= ~RF_FsmEventLastCommandDone; + } + } + else if (e & RF_FsmEventPowerDown) + { + /* If possible, put the running RAT channels into pending state allowing to + power down the RF core. */ + if (RF_ratReleaseChannels()) + { + /* Indicate that the RF core is being powered down from now */ + RF_core.status = RF_CoreStatusPoweringDown; + + /* Stop inactivity timer. */ + ClockP_stop(&RF_clkInactivityObj); + + /* Execute power down sequence of the RF core */ + RF_corePowerDown(); + + /* Invoke the global callback. At this point the clock of RF core is OFF, but the + power domain is still powered (hence the doorbell signals are still active. + We do the callback here to save some power. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioPowerDown, NULL); + + /* Notify the power driver that Standby mode is allowed and the RF core can be powered down. */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + Power_releaseDependency(PowerCC26XX_DOMAIN_RFCORE); + + /* Closing all handles */ + if (!RF_numClients) + { + /* Release the semaphore to be sure no one is pending on it */ + SemaphoreP_post(&RF_currClient->state.semSync); + } + + /* If there is no specific client request or the XOSC, release the dependency */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == false) + { + Power_releaseDependency(PowerCC26XX_XOSC_HF); + } + + /* Release constraint of switching XOSC_HF from the RF driver itself */ + if (RF_core.manualXoscHfSelect) + { + RF_core.manualXoscHfSelect = false; + Power_releaseConstraint(PowerCC26XX_SWITCH_XOSC_HF_MANUALLY); + } + + /* Next state: RF_fsmPowerUpState */ + RF_core.fxn = RF_fsmPowerUpState; + + /* Indicate that the RF core is now powered down */ + RF_core.status = RF_CoreStatusIdle; + } + + /* Reschedule the next event based on the state of the command queue + and the RAT module. We do it here as future commands need to work even if + power management is disabled manually. */ + RF_dispatchNextEvent(); + + /* We've handled this event now */ + e &= ~RF_FsmEventPowerDown; + } + + /* Call self again if there are outstanding events to be processed */ + if (e) + { + SwiP_or(&RF_swiFsmObj, e); + } +} + +/*-------------- Initialization & helper functions ---------------*/ + +/* + * Initialize RF driver. + * + * Input: none + * Return: none + */ +static void RF_init(void) +{ + union { + HwiP_Params hp; + SwiP_Params sp; + } params; + + /* Power init */ + Power_init(); + + /* Enable output RTC clock for Radio Timer Synchronization */ + HWREG(AON_RTC_BASE + AON_RTC_O_CTL) |= AON_RTC_CTL_RTC_UPD_EN_M; + + /* Initialize SWI used by the RF driver. */ + SwiP_Params_init(¶ms.sp); + params.sp.priority = RFCC26XX_hwAttrs.swiPriority; + SwiP_construct(&RF_swiFsmObj, RF_swiFsm, ¶ms.sp); + SwiP_construct(&RF_swiHwObj, RF_swiHw, ¶ms.sp); + + /* Initialize HWI used by the RF driver. */ + HwiP_Params_init(¶ms.hp); + params.hp.priority = RFCC26XX_hwAttrs.hwiPriority; + HwiP_construct(&RF_hwiCpe0Obj, INT_RFC_CPE_0, RF_hwiCpe0PowerFsm, ¶ms.hp); + HwiP_construct(&RF_hwiHwObj, INT_RFC_HW_COMB, RF_hwiHw, ¶ms.hp); + + /* Initialize clock object used as power-up trigger */ + ClockP_construct(&RF_clkPowerUpObj, &RF_clkPowerUp, 0, NULL); + ClockP_construct(&RF_clkInactivityObj, &RF_clkInactivityCallback, 0, NULL); + + /* Subscribe to wakeup notification from the Power driver */ + Power_registerNotify(&RF_wakeupNotifyObj, /* Object to register */ + PowerCC26XX_AWAKE_STANDBY, /* Event the notification to be invoked upon */ + (Power_NotifyFxn) RF_wakeupNotification, /* Function to be invoked */ + (uintptr_t) NULL); /* Parameters */ + + /* Set the XOSC_HF dependency if the HW attributes say so. This will ensure + that the XOSC_HF is turned on by the power driver as soon as possible when + coming out of standby. */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == true) + { + Power_setDependency(PowerCC26XX_XOSC_HF); + } + + /* Initialized the queues. */ + List_clearList(&RF_cmdQ.pDone); + List_clearList(&RF_cmdQ.pPend); + + /* Initialize global variables */ + RF_core.status = RF_CoreStatusIdle; + RF_core.init = false; + RF_core.activeTimeUs = 0; + RF_core.manualXoscHfSelect = false; + RF_ratModule.availableRatChannels = RF_DEFAULT_AVAILRATCH_VAL; + RF_rtcTimestampA = 0; + RF_errTolValInUs = RF_DEFAULT_RAT_RTC_ERR_TOL_IN_US; + RF_powerConstraint = 0; + + /* Set FSM state to power up */ + RF_core.fxn = RF_fsmPowerUpState; +} + +/* + * Trace through the pending queue and flush the command(s). + * + * Input: h - Handle to the client calling this function. + * pCmd - Pointer to the command where the cancelling should start with. + * bFlushAll - Decides weather one or more commands should be aborted. + * Return: Number of commands was terminated. + */ +static uint32_t RF_discardPendCmd(RF_Handle h, RF_Cmd* pCmd, bool bFlushAll) +{ + /* Local variables, start from the head of queue. */ + uint32_t numDiscardedCmd = 0; + RF_Cmd* pElem = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + /* Find the first command to be cancelled. */ + while (pElem && (pElem != pCmd)) + { + pElem = (RF_Cmd*)List_next((List_Elem*)pElem); + } + + /* If we found the command to be cancelled. */ + while (pElem) + { + /* Temporarly store the next element, since we will need + to continue from there. */ + RF_Cmd* pNextElem = (RF_Cmd*)List_next((List_Elem*)pElem); + + if (pElem) + { + /* Mark the command that it was cancelled. */ + RF_cmdStoreEvents(pElem, RF_EventCmdCancelled); + + /* Remove the command from the pend queue and place it to + the done queue. */ + List_remove(&RF_cmdQ.pPend, (List_Elem*)pElem); + List_put(&RF_cmdQ.pDone, (List_Elem*)pElem); + + /* Increment the counter of cancelled commands. */ + numDiscardedCmd += 1; + } + + /* Break the loop if only single cancel was requested. + Step the queue otherwise. */ + if (bFlushAll) + { + pElem = pNextElem; + } + else + { + break; + } + } + + /* Return with the number of cancelled commands. */ + return(numDiscardedCmd); +} + +/* + * Process cancel commands. It is used by RF_cancelCmd, RF_flushCmd API. + * + * Input: h - Handle to the client calling this function. + * ch - Handle to the command where the cancelling should start with. + * graceful - true: stop the command + * false: abort the command + * flush - true: flush all commands of this client + * false: only cancel the given command + * Retrun: status + */ +static RF_Stat RF_abortCmd(RF_Handle h, RF_CmdHandle ch, bool graceful, bool flush) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Initialize local variables */ + RF_Cmd* pCmd = NULL; + RF_Stat status = RF_StatInvalidParamsError; + RF_EventMask event = graceful ? RF_EventCmdStopped : RF_EventCmdAborted; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Handle FLUSH_ALL request */ + if (ch == RF_CMDHANDLE_FLUSH_ALL) + { + /* If the current command belongs to this client, cancel it first. + Otherwise, walk the pend queue and cancel commands belong to this client. */ + pCmd = (RF_cmdQ.pCurrCmd ? RF_cmdQ.pCurrCmd : (RF_Cmd*)List_head(&RF_cmdQ.pPend)); + } + else + { + /* Search for the command in the command pool based on its handle. The command can + locate on any of the queues at this point. */ + pCmd = RF_cmdGet(ch, 0x00); + } + + /* If command handle is valid, proceed to cancel. */ + if (pCmd) + { + /* If the command is still allocated. */ + if (pCmd->flags & RF_CMD_ALLOC_FLAG) + { + /* If the command we want to cancel is actively running. */ + if (pCmd == RF_cmdQ.pCurrCmd) + { + /* Flag that the command has been aborted. */ + RF_cmdStoreEvents(pCmd, event); + + /* Decode what method to use to terminate the ongoing radio operation. */ + uint32_t directCmd = (graceful) ? CMDR_DIR_CMD(CMD_STOP) : CMDR_DIR_CMD(CMD_ABORT); + + /* Send the abort/stop command through the doorbell to the RF core. */ + RFCDoorbellSendTo(directCmd); + + /* Remove all commands from the pend queue belong to this client. Only do it + if it was explicitely requested through the flush argument. */ + if (flush) + { + RF_discardPendCmd(h, (RF_Cmd*)List_head(&RF_cmdQ.pPend), flush); + } + + /* Return with success as we cancelled at least the currently running command. */ + status = RF_StatSuccess; + } + else + { + /* Remove one/all commands from the pend queue based on the flush argument. + If at least one command is cancelled the operation was succesful. Otherwise, + either the pend queue is empty or pCmd have terminated earlier */ + if (RF_discardPendCmd(h, pCmd, flush)) + { + /* Kick the state machine to handle the done queue. This is not necessary + when the RF is currently performing a power-up. */ + if (RF_core.status != RF_CoreStatusPoweringUp) + { + SwiP_or(&RF_swiFsmObj, RF_FsmEventLastCommandDone); + } + + /* At least one command was cancelled. */ + status = RF_StatSuccess; + } + else + { + /* The command is not running and is not in the pend queue. It is located on the + done queue, hence return RF_StatCmdEnded. */ + status = RF_StatCmdEnded; + } + } + } + else + { /* If command is still in the pool but it is not allocated anymore, i.e. it was already served. */ + status = RF_StatCmdEnded; + } + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with the result: + - RF_StatSuccess if at least one command was cancelled. + - RF_StatCmdEnded, when the command already finished. + - RF_StatInvalidParamsError otherwise. */ + return(status); +} + +/* + * Execute a direct or immediate command in the RF Core if possible. + * + * Input: pCmd - Pointer to the command which shall be sent to the RF core. + * rawStatus - Return address of the raw status byte read from the CMDSTA register. + * Return: The return value interprets and converts the result of command execution to and RF_Stat value. + * RF_StatCmdDoneSuccess - If the command was sent and accepted by the RF core. + * RF_StatCmdDoneError - Command was rejected by the RF core. + * RF_StatRadioInactiveError - The RF core is OFF. + */ +static RF_Stat RF_executeDirectImmediateCmd(uint32_t pCmd, uint32_t* rawStatus) +{ + /* If the RF core is ON, we can send the command */ + if (RF_core.status == RF_CoreStatusActive) + { + /* Submit the command to the doorbell */ + uint32_t localStatus = RFCDoorbellSendTo(pCmd); + + /* Pass the rawStatus to the callee if possible. */ + if (rawStatus) + { + *rawStatus = localStatus; + } + + /* Check the return value of the RF core through the CMDSTA register within the doorbell */ + if ((localStatus & RF_CMDSTA_REG_VAL_MASK) == CMDSTA_Done) + { + /* The command was accepted */ + return(RF_StatCmdDoneSuccess); + } + else + { + /* The command was rejected */ + return(RF_StatCmdDoneError); + } + } + else + { + /* The RF core is not capable of receiving the command */ + return(RF_StatRadioInactiveError); + } +} + +/* + * Send a direct or immediate command to the RF core. The command is rejected + * if the RF core is configured to a different PHY (client). + * + * Input: h - Handle to the client calling this function. + * pCmd - Pointer to the command which shall be sent to the RF core. + * rawStatus - Return address of raw status byte read from CMDSTA register. + * Return: RF_StatCmdDoneSuccess - If the command was sent and accepted by the RF core. + * RF_StatCmdDoneError - Command was rejected by the RF core. + * RF_StatInvalidParamsError - Client do not have the right to send commands now. + * RF_StatRadioInactiveError - The RF core is OFF. + */ +static RF_Stat RF_runDirectImmediateCmd(RF_Handle h, uint32_t pCmd, uint32_t* rawStatus) +{ + /* Local variable. */ + RF_Stat status; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Only the current client is allowed to send direct commands */ + if (h != RF_currClient) + { + /* Return with an error code it is a different client */ + status = RF_StatInvalidParamsError; + } + else + { + /* Execute the direct or immediate command. */ + status = RF_executeDirectImmediateCmd(pCmd, rawStatus); + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with the status information about the success of command execution. */ + return(status); +} + +/* + * Helper function to find and modify the PA selection and gain of the provided setup command. + * + * Input: radioConfiguration - Radio configuration to be updated. + * newValue - The new value the PA to be set to. + * Return: RF_StatSuccess - The setup command was reconfigured. + * Otherwise - An error occured. + */ +static RF_Stat RF_updatePaConfiguration(RF_RadioSetup* radioSetup, RF_TxPowerTable_Value newValue) +{ + /* By default, reject the new configuration. */ + RF_Stat status = RF_StatInvalidParamsError; + + /* Determine if the new value is for the default-PA. */ + if (newValue.paType == RF_TxPowerTable_DefaultPA) + { + /* Calculate the offset of the txPower field and store the new value. */ + switch(radioSetup->commandId.commandNo) + { + case (CMD_RADIO_SETUP): + case (CMD_BLE5_RADIO_SETUP): + /* Set the new power value. */ + radioSetup->common.txPower = (uint16_t) newValue.rawValue; + break; + default: + /* Set the new power value. */ + radioSetup->prop.txPower = (uint16_t) newValue.rawValue; + break; + } + + /* Update the return value as the new configuration was accepted. */ + status = RF_StatSuccess; + } + + /* Return the status. */ + return(status); +} + +/*-------------- API functions ---------------*/ + +/* + * ======== RF_open ======== + * Open an RF handle + */ +RF_Handle RF_open(RF_Object *pObj, RF_Mode *pRfMode, RF_RadioSetup *pRadioSetup, RF_Params *params) +{ + /* Assert */ + DebugP_assert(pObj != NULL); + DebugP_assert(pRfMode != NULL); + DebugP_assert(pRadioSetup != NULL); + + /* Read available RF modes from the PRCM register */ + uint32_t availableRfModes = HWREG(PRCM_BASE + PRCM_O_RFCMODEHWOPT); + + /* Verify that the provided configuration is supported by this device. + Reject any request which is not compliant. */ + if (pRfMode && pRadioSetup && (availableRfModes & (1 << pRfMode->rfMode))) + { + /* Trim the override list; The implementation of RFCOverrideUpdate is device specific */ + RFCOverrideUpdate((RF_Op*)pRadioSetup, NULL); + + /* Register the (valid) RF mode to the client */ + pObj->clientConfig.pRfMode = pRfMode; + + /* Register the setup command to the client */ + pObj->clientConfig.pRadioSetup = pRadioSetup; + } + else + { + /* Return with null if the device do not support the requested configuration */ + return(NULL); + } + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Check whether RF driver is accepting more clients */ + if (RF_numClients < N_MAX_CLIENTS) + { + /* Initialize shared objects on first client */ + if (RF_numClients == 0) RF_init(); + + /* Register the new client */ + RF_numClients++; + + /* Restore the key */ + HwiP_restore(key); + + /* Populate default params if not provided */ + RF_Params rfParams; + if (params == NULL) + { + RF_Params_init(&rfParams); + params = &rfParams; + } + + /* Initialize RF_Object configuration */ + pObj->clientConfig.nInactivityTimeout = params->nInactivityTimeout; + pObj->clientConfig.nPowerUpDurationMargin = params->nPowerUpDurationMargin; + pObj->clientConfig.bUpdateSetup = true; + + /* Decide if automatic adjustment should be used. */ + if (params->nPowerUpDuration) + { + pObj->clientConfig.nPowerUpDuration = params->nPowerUpDuration; + pObj->clientConfig.bMeasurePowerUpDuration = false; + } + else + { + pObj->clientConfig.nPowerUpDuration = RF_DEFAULT_POWER_UP_TIME; + pObj->clientConfig.bMeasurePowerUpDuration = true; + } + + /* Set all the callbacks to default (do nothing)*/ + pObj->clientConfig.pErrCb = (void*) RF_defaultCallback; + pObj->clientConfig.pPowerCb = (void*) RF_defaultCallback; + + /* If a user specified callback is provided, overwrite the default */ + if (params->pErrCb) + { + pObj->clientConfig.pErrCb = (void *)params->pErrCb; + } + if (params->pPowerCb) + { + pObj->clientConfig.pPowerCb = (void *)params->pPowerCb; + } + + /* Initialize client state & variables */ + memset((void*)&pObj->state, 0, sizeof(pObj->state)); + + /* Initialize client semaphore and clock object */ + SemaphoreP_constructBinary(&pObj->state.semSync, 0); + + /* Set the current client to be the one opened the driver. */ + RF_currClient = pObj; + + /* Return with and RF handle (RF_Obj*) */ + return(pObj); + } + else + { + /* Restore the key and return if the new client request can not be served */ + HwiP_restore(key); + + /* Return with null if no more clients are accepted */ + return(NULL); + } +} + +/* + * ======== RF_close ======== + * Close an RF handle + */ +void RF_close(RF_Handle h) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Wait for all issued commands to finish */ + if (RF_numClients) + { + /* Wait for all issued commands to finish before freeing the resources */ + if (RF_cmdQ.nSeqPost != RF_cmdQ.nSeqDone) + { + /* There are commands which not even dispatched yet. */ + RF_Cmd* pCmd = (RF_Cmd*)List_tail(&RF_cmdQ.pPend); + + /* There is no pending commmand, determine if there are items on the + other queues. */ + if (!pCmd) + { + /* If the client is executing a command running. */ + if (RF_cmdQ.pCurrCmd) + { + /* The currentlty running command is the last. */ + pCmd = RF_cmdQ.pCurrCmd; + } + else + { + /* All commands has been dispatched, some just need to be served. This also + can return with NULL if nothing to be done. */ + pCmd = (RF_Cmd*)List_tail(&RF_cmdQ.pDone); + } + } + + /* Pend until the running command terminates */ + if (pCmd) + { + RF_pendCmd(h, pCmd->ch, RF_TERMINATION_EVENT_MASK); + } + } + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Check weather this is the last client */ + if (--RF_numClients == 0) + { + if (RF_core.status == RF_CoreStatusActive) + { + /* Release the constraint on the RF resources */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + + /* Exit critical section */ + HwiP_restore(key); + + /* Wait until the radio is powered down (outside critical section) */ + SemaphoreP_pend(&h->state.semSync, SemaphoreP_WAIT_FOREVER); + + /* Enter critical section */ + key = HwiP_disable(); + } + + /* Unregister shared RTOS objects */ + SwiP_destruct(&RF_swiFsmObj); + HwiP_destruct(&RF_hwiCpe0Obj); + SwiP_destruct(&RF_swiHwObj); + HwiP_destruct(&RF_hwiHwObj); + ClockP_destruct(&RF_clkPowerUpObj); + ClockP_destruct(&RF_clkInactivityObj); + + /* Unregister the wakeup notify callback */ + Power_unregisterNotify(&RF_wakeupNotifyObj); + + /* Release XOSC_HF dependency if it was set on board level. */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == true) + { + Power_releaseDependency(PowerCC26XX_XOSC_HF); + } + } + + /* If we're the current RF client, stop being it */ + if (RF_currClient == h) + { + RF_currClient = NULL; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Unregister client specific RTOS objects (these are not shared between clients) */ + SemaphoreP_destruct(&h->state.semSync); + } +} + +/* + * ======== RF_getCurrentTime ======== + * Get current time in RAT ticks + */ +uint32_t RF_getCurrentTime(void) +{ + /* Local variable */ + uint64_t nCurrentTime = 0; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* If radio is active, read the RAT */ + if (RF_core.status == RF_CoreStatusActive) + { + /* Read the RAT timer through register access */ + nCurrentTime = RF_ratGetValue(); + + /* Exit critical section */ + HwiP_restore(key); + } + else + { + /* Exit critical section */ + HwiP_restore(key); + + /* The radio is inactive, read the RTC instead */ + nCurrentTime = AONRTCCurrent64BitValueGet(); + + /* Conservatively assume that we are just about to increment the RTC + Scale with the 4 MHz that the RAT is running + Add the RAT offset for RTC==0 */ + nCurrentTime += RF_RTC_TICK_INC; + nCurrentTime *= RF_SCALE_RTC_TO_4MHZ; + nCurrentTime += ((uint64_t)RF_ratSyncCmd.start.rat0) << RF_SHIFT_32_BITS; + nCurrentTime >>= RF_SHIFT_32_BITS; + } + + /* Return with the current value */ + return((uint32_t) nCurrentTime); +} + +/* + * ======== RF_postCmd ======== + * Post radio command + */ +RF_CmdHandle RF_postCmd(RF_Handle h, RF_Op* pOp, RF_Priority ePri, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + DebugP_assert(pOp != NULL); + + /* Local command handle to be used for return value. */ + RF_CmdHandle cmdHandle = (RF_CmdHandle)RF_ALLOC_ERROR; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Try to allocate container */ + RF_Cmd* pCmd = RF_cmdAlloc(); + + /* If allocation was succesfull. */ + if (pCmd) + { + /* Stop inactivity clock if running */ + ClockP_stop(&RF_clkInactivityObj); + + /* Increment the sequence number and mask the value */ + RF_cmdQ.nSeqPost = (RF_cmdQ.nSeqPost + 1) & N_CMD_MODMASK; + + /* Populate container with reset values */ + pCmd->pOp = pOp; + pCmd->ePri = ePri; + pCmd->pCb = pCb; + pCmd->ch = RF_cmdQ.nSeqPost; + pCmd->pClient = h; + pCmd->bmEvent = (bmEvent | RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M) & ~RF_INTERNAL_IFG_MASK; + pCmd->pastifg = 0; + pCmd->flags = RF_CMD_ALLOC_FLAG; + + /* Cancel ongoing yielding */ + h->state.bYielded = false; + + /* Submit to pending command to the queue. */ + List_put(&RF_cmdQ.pPend, (List_Elem*)pCmd); + + /* Trigger dispatcher if the timings need to be reconsidered. */ + if(List_head(&RF_cmdQ.pPend) == (List_Elem*)pCmd) + { + RF_dispatchNextEvent(); + } + + /* Return with the command handle as success */ + cmdHandle = pCmd->ch; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with an error code */ + return(cmdHandle); +} + +/* + * ======== RF_pendCmd ======== + * Pend on radio command + */ +RF_EventMask RF_pendCmd(RF_Handle h, RF_CmdHandle ch, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* If the command handle is invalid (i.e. RF_ALLOC_ERROR) */ + if (ch < 0) + { + /* Return with zero means the command was rejected earlier */ + return(0); + } + + /* Enter critical section */ + uint32_t key = SwiP_disable(); + + /* Find the command based on its handle in the command pool */ + RF_Cmd* pCmd = RF_cmdGet(ch, RF_CMD_ALLOC_FLAG); + + /* If the command was already disposed */ + if (!pCmd || !(pCmd->flags & RF_CMD_ALLOC_FLAG)) + { + /* Exit critical section */ + SwiP_restore(key); + + /* Return with last command done event */ + return(RF_EventLastCmdDone); + } + + /* Expand the pend mask to accept RF_EventLastCmdDone and RF_EventLastFGCmdDone events even if it is not given explicitely */ + bmEvent = (bmEvent | RF_TERMINATION_EVENT_MASK); + + /* If the command is being executed, but the event we pending on has already happend (i.e. in a chain), + return the past events */ + if (pCmd->pastifg & bmEvent) + { + /* Exit critical section */ + SwiP_restore(key); + + /* Store the cause of returning */ + h->state.unpendCause = pCmd->pastifg & bmEvent; + + /* Clear the handled past events so it is possible to pend again */ + pCmd->pastifg &= ~h->state.unpendCause; + + /* Return with the events */ + return h->state.unpendCause; + } + + /* Command has still not finished, override user callback with one that calls the user callback then posts to semaphore */ + if (pCmd->pCb != RF_syncCb) + { + /* Temporarily store the callback function */ + h->state.pCbSync = (void*)pCmd->pCb; + + /* Exhange the callback funtion: this will invoke the user callback and post to the semaphore if needed */ + pCmd->pCb = RF_syncCb; + } + + /* Store the event subscriptions in the clients context. This can only be one of the already enabled + interrupt sources by RF_postCmd (including RF_EventLastCmdDone) */ + h->state.eventSync = bmEvent; + + /* Exit critical section */ + SwiP_restore(key); + + /* Wait for semaphore */ + SemaphoreP_pend(&h->state.semSync, SemaphoreP_WAIT_FOREVER); + + /* Return the events that resulted in releasing the RF_pend() call */ + return(h->state.unpendCause); +} + +/* + * ======== RF_runCmd ======== + * Run to completion a posted command + */ +RF_EventMask RF_runCmd(RF_Handle h, RF_Op* pOp, RF_Priority ePri, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Post the requested command */ + RF_CmdHandle ch = RF_postCmd(h, pOp, ePri, pCb, bmEvent); + + /* If the command was accepted, pend until one of the special events occur */ + return(RF_pendCmd(h, ch, RF_TERMINATION_EVENT_MASK)); +} + +/* + * ======== RF_yieldCmd ======== + * Release client access + */ +void RF_yield(RF_Handle h) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Request the synchronization of RTC and RAT at next power down. This is trigged + by ceiling the active time to the maximum value. */ + RF_core.activeTimeUs = UINT32_MAX; + + /* If all previously posted command was served. */ + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + /* All commands are done. Stop inactivity timer. */ + ClockP_stop(&RF_clkInactivityObj); + + /* Potentially power down the RF core. */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + } + else + { + /* There are still client commands that haven't finished. + Set flag to indicate immediate powerdown when last command is done. */ + h->state.bYielded = true; + } + + /* Exit critical section. */ + HwiP_restore(key); +} + + +/* + * ======== RF_cancelCmd ======== + * Cancel single radio command + */ +RF_Stat RF_cancelCmd(RF_Handle h, RF_CmdHandle ch, uint8_t mode) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Decode what method to be used for terminating the commands. */ + bool graceful = (bool)(mode & RF_ABORT_GRACEFULLY); + bool flush = (bool)(mode & RF_ABORT_FLUSH_ALL); + + /* Invoke the aborting process with the input arguments on a single command */ + return(RF_abortCmd(h, ch, graceful, flush)); +} + +/* + * ======== RF_flushCmd ======== + * Cancel multiple radio commands from a client + */ +RF_Stat RF_flushCmd(RF_Handle h, RF_CmdHandle ch, uint8_t mode) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Decode what method to be used for terminating the commands. */ + bool graceful = (bool)(mode & RF_ABORT_GRACEFULLY); + bool flush = true; + + /* Invoke the aborting process with the input arguments on a single command */ + return(RF_abortCmd(h, ch, graceful, flush)); +} + +/* + * ======== RF_Params_init ======== + * Initialize the RF_params to default value + */ +void RF_Params_init(RF_Params *params) +{ + /* Assert */ + DebugP_assert(params != NULL); + + /* Assign default values for RF_params */ + *params = RF_defaultParams; +} + +/* + * ======== RF_runImmediateCmd ======== + * Run immediate command + */ +RF_Stat RF_runImmediateCmd(RF_Handle h, uint32_t* pCmd) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Submit the command to the RF core */ + return(RF_runDirectImmediateCmd(h, (uint32_t)pCmd, NULL)); +} + +/* + * ======== RF_runDirectCmd ======== + * Run direct command + */ +RF_Stat RF_runDirectCmd(RF_Handle h, uint32_t cmd) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Submit the command to the RF core */ + return(RF_runDirectImmediateCmd(h, cmd, NULL)); +} + +/* + * ======== RF_getRssi ======== + * Get RSSI value + */ +int8_t RF_getRssi(RF_Handle h) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Local variable. */ + uint32_t rawRssi; + + /* Read the RSSI value if possible. */ + RF_Stat status = RF_runDirectImmediateCmd(h, CMDR_DIR_CMD(CMD_GET_RSSI), &rawRssi); + + /* Decode the RSSI value if possible. */ + if (status == RF_StatCmdDoneSuccess) + { + return((int8_t)((rawRssi >> RF_SHIFT_16_BITS) & RF_CMDSTA_REG_VAL_MASK)); + } + else + { + return((int8_t)RF_GET_RSSI_ERROR_VAL); + } +} + +/* + * ======== RF_getInfo ======== + * Get RF driver info + */ +RF_Stat RF_getInfo(RF_Handle h, RF_InfoType type, RF_InfoVal *pValue) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Prepare the default status value */ + RF_Stat status = RF_StatSuccess; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Serve the different flavor of requests */ + switch (type) + { + case RF_GET_CURR_CMD: + /* Get the handle of the currently running command. It can be conerted + to a pointer through the RF_getCmdOp() API. */ + if (RF_cmdQ.pCurrCmd) + { + pValue->ch = ((RF_Cmd*)RF_cmdQ.pCurrCmd)->ch; + } + else + { + status = RF_StatError; + } + break; + + case RF_GET_AVAIL_RAT_CH: + /* Get available user channels within the RAT timer. + These channels can be allocated and used by the application. */ + pValue->availRatCh = RF_ratModule.availableRatChannels; + break; + + case RF_GET_RADIO_STATE: + /* Get current radio state */ + pValue->bRadioState = (RF_core.status == RF_CoreStatusActive) ? true : false; + break; + + default: + status = RF_StatInvalidParamsError; + break; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with a status code */ + return(status); +} + +/* + * ======== RF_getCmdOp ======== + * Get RF command + */ +RF_Op* RF_getCmdOp(RF_Handle h, RF_CmdHandle ch) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Find the command based on its handle */ + RF_Cmd* pCmd = RF_cmdGet(ch, RF_CMD_ALLOC_FLAG); + + /* If the command exists, return with a pointer to its radio operation. + Otherwise, return a null pointer */ + if (pCmd) + { + return(pCmd->pOp); + } + else + { + return(NULL); + } +} + +/* + * ======== RF_RatConfigCompare_init ======== + * Initialize RAT compare configuration + */ +void RF_RatConfigCompare_init(RF_RatConfigCompare* channelConfig) +{ + /* Assert */ + DebugP_assert(channelConfig != NULL); + + /* Set the values to default. */ + memset((void*)channelConfig, 0, sizeof(RF_RatConfigCompare)); + + /* Set the default allocation method to use any channel. */ + channelConfig->channel = RF_RatChannelAny; +} + +/* + * ======== RF_RatConfigCapture_init ======== + * Initialize RAT capture configuration + */ +void RF_RatConfigCapture_init(RF_RatConfigCapture* channelConfig) +{ + /* Assert */ + DebugP_assert(channelConfig != NULL); + + /* Set the values to default. */ + memset((void*)channelConfig, 0, sizeof(RF_RatConfigCapture)); + + /* Set the default allocation method to use any channel. */ + channelConfig->channel = RF_RatChannelAny; +} + +/* + * ======== RF_RatConfigOutput_init ======== + * Initialize RAT IO configuration + */ +void RF_RatConfigOutput_init(RF_RatConfigOutput* ioConfig) +{ + /* Assert */ + DebugP_assert(ioConfig != NULL); + + /* Set the values to default. */ + memset((void*)ioConfig, 0, sizeof(RF_RatConfigOutput)); +} + +/* + * ======== RF_ratCompare ======== + * Set RAT compare + */ +RF_RatHandle RF_ratCompare(RF_Handle rfHandle, RF_RatConfigCompare* channelConfig, RF_RatConfigOutput* ioConfig) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Configure the RAT channel into COMPARE mode. */ + return(RF_ratSetupChannel(rfHandle, RF_RatModeCompare, channelConfig->callback, channelConfig->channel, (void*) channelConfig, ioConfig)); +} + +/* + * ======== RF_ratCapture ======== + * Set RAT capture + */ +RF_RatHandle RF_ratCapture(RF_Handle rfHandle, RF_RatConfigCapture* channelConfig, RF_RatConfigOutput* ioConfig) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Configure the RAT channel into CAPTURE mode. */ + return(RF_ratSetupChannel(rfHandle, RF_RatModeCapture, channelConfig->callback, channelConfig->channel, (void*) channelConfig, ioConfig)); +} + +/* + * ======== RF_ratDisableChannel ======== + * Disable RAT channel + */ +RF_Stat RF_ratDisableChannel(RF_Handle h, RF_RatHandle ratHandle) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Default return value */ + RF_Stat status = RF_StatError; + + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Find the pointer to the RAT channel configuration. */ + RF_RatChannel* ratCh = RF_ratGetChannel(ratHandle); + + /* Disable the channel if it is in use. */ + if (ratCh && ratCh->status) + { + /* If the RF core is active, abort the RAT event. */ + if (RF_core.status == RF_CoreStatusActive) + { + /* Calculate the configuration field of command (the channel we disable). */ + uint16_t config = (uint16_t)(RF_RAT_CH_LOWEST + ratCh->handle) << RF_SHIFT_8_BITS; + + /* Disable the channel within the RF core. */ + status = RF_runDirectImmediateCmd(h, ((uint32_t)CMDR_DIR_CMD_2BYTE(CMD_DISABLE_RAT_CH, config)), NULL); + + /* Free the container for further use. We do it after the direct command to be sure it is not powered down. + This will implicitely schedule the next event and run the power management accordingly. */ + RF_ratFreeChannel(ratCh); + } + else + { + /* Set status to be successful. */ + status = RF_StatCmdDoneSuccess; + + /* Free the container for further use. */ + RF_ratFreeChannel(ratCh); + + /* Recalculate the next wakeup event. */ + RF_dispatchNextEvent(); + } + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with the status code */ + return(status); +} + +/* + * ======== RF_control ======== + * RF control + */ +RF_Stat RF_control(RF_Handle h, int8_t ctrl, void *args) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Prepare the return value for worst case scenario */ + RF_Stat status = RF_StatSuccess; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Serve the different requests */ + switch (ctrl) + { + case RF_CTRL_SET_INACTIVITY_TIMEOUT: + /* Update the inactivity timeout of the client. + This can be used if the value given at RF_open + need to be updated */ + h->clientConfig.nInactivityTimeout = *(uint32_t *)args; + break; + + case RF_CTRL_UPDATE_SETUP_CMD: + /* Enable a special boot process which can be controlled + through the config field of the radio setup command. + This will influence only the next power up sequence + and will be reset automatically afterwards. The special + power up process will require longer power up time, hence + the nPowerUpDuration need to be increased */ + h->clientConfig.bUpdateSetup = true; + h->clientConfig.nPowerUpDuration += RF_ANALOG_CFG_TIME_US; + break; + + case RF_CTRL_SET_POWERUP_DURATION_MARGIN: + /* Configure the margin which is added to the measured + nPowerUpDuration. This can ensure that the commands + are executed on time, depending on the load of the + cpu */ + h->clientConfig.nPowerUpDurationMargin = *(uint32_t *)args; + break; + + case RF_CTRL_SET_RAT_RTC_ERR_TOL_VAL: + /* Configure the tolerance value which is used to determine + the period when the RAT need to be syncronized to the RTC + due to the frequency offset */ + RF_errTolValInUs = *(uint32_t*)args; + break; + + case RF_CTRL_SET_POWER_MGMT: + /* The RF drivers power management can be enabled/disabled by + directly setting the power constraints from the application. + It is important that the order of actions align. */ + if (*(uint32_t*)args == 0) + { + RF_powerConstraintSet(RF_PowerConstraintDisallow); + } + else if (*(uint32_t*)args == 1) + { + RF_powerConstraintRelease(RF_PowerConstraintDisallow); + } + else + { + status = RF_StatInvalidParamsError; + } + break; + + case RF_CTRL_SET_HWI_PRIORITY: + /* Changing priorities during run-time has constraints. + To not mess up with the RF driver, we require the RF + driver to be inactive. */ + if (RF_core.status || (!List_empty(&RF_cmdQ.pPend))) + { + status = RF_StatBusyError; + } + else + { + HwiP_setPriority(INT_RFC_CPE_0, *(uint32_t *)args); + HwiP_setPriority(INT_RFC_HW_COMB, *(uint32_t *)args); + } + break; + + case RF_CTRL_SET_SWI_PRIORITY: + /* Changing priorities during run-time has constraints. + To not mess up with the RF driver, we require the RF + driver to be inactive. */ + if (RF_core.status || (!List_empty(&RF_cmdQ.pPend))) + { + status = RF_StatBusyError; + } + else + { + SwiP_setPriority(&RF_swiFsmObj, *(uint32_t *)args); + SwiP_setPriority(&RF_swiHwObj, *(uint32_t *)args); + } + break; + + case RF_CTRL_SET_AVAILABLE_RAT_CHANNELS_MASK: + /* Mask the available RAT channels manually. This can be used when + a particular RAT channel is used through oridnary radio operations + instead of the dedicated RAT APIs. */ + RF_ratModule.availableRatChannels = *(uint8_t *)args; + break; + + default: + /* Request can not be served */ + status = RF_StatInvalidParamsError; + break; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with the status code */ + return(status); +} + +/* + * ======== RF_setTxPower ======== + * Set the TX power of the client + */ +RF_Stat RF_setTxPower(RF_Handle handle, RF_TxPowerTable_Value value) +{ + /* Set the default return value to be an error. */ + RF_Stat status = RF_StatInvalidParamsError; + + /* Update the setup command to make the changes permanent. */ + status = RF_updatePaConfiguration(handle->clientConfig.pRadioSetup, value); + + /* If we managed to decode and cache the changes in the setup command. */ + if (status == RF_StatSuccess) + { + /* Create an immediate command to be used to update the output power immediately. */ + rfc_CMD_SET_TX_POWER_t txPowerCmd = {.commandNo = CMD_SET_TX_POWER, + .txPower = (uint16_t) value.rawValue}; + + /* Update the TX power by executing a direct command. It only takes effect if both + the client is correct and the RF core is active at the time of call. + The RF core will blindly accept any value, hence no error checking is necessay. */ + RF_runDirectImmediateCmd(handle, (uint32_t)&txPowerCmd, NULL); + } + + /* Return with the status. */ + return(status); +} + +/* + * ======== RF_getTxPower ======== + * Get the current TX power value + */ +RF_TxPowerTable_Value RF_getTxPower(RF_Handle handle) +{ + /* Default return value. */ + RF_TxPowerTable_Value value = { .rawValue = RF_TxPowerTable_INVALID_VALUE, + .paType = RF_TxPowerTable_DefaultPA}; + + /* Decode the setup command associated with the provided handle. */ + RF_RadioSetup* setupCmd = handle->clientConfig.pRadioSetup; + + /* Decode the power setting in the setup command. */ + switch(setupCmd->commandId.commandNo) + { + case (CMD_RADIO_SETUP): + case (CMD_BLE5_RADIO_SETUP): + /* Decode the default PA value. */ + value.rawValue = setupCmd->common.txPower; + break; + default: + /* Decode the default PA value. */ + value.rawValue = setupCmd->prop.txPower; + break; + } + + /* Return with the value. */ + return(value); +} + +/* + * ======== RF_TxPowerTable_findPowerLevel ======== + * Retrieves a power level in dBm for a given power configuration value. + */ +int8_t RF_TxPowerTable_findPowerLevel(RF_TxPowerTable_Entry table[], RF_TxPowerTable_Value value) +{ + /* Iterate through the power table. We do not verify against nullptr. */ + uint32_t i; + for (i=0; (table[i].power != RF_TxPowerTable_INVALID_DBM) && + (table[i].value.rawValue != RF_TxPowerTable_INVALID_VALUE); i++) + { + if (((uint32_t)table[i].value.paType == (uint32_t)value.paType) && + ((uint32_t)table[i].value.rawValue == (uint32_t)value.rawValue)) + { + /* Break the loop on the first entry which satisfies + the lower-or-equal criterion toward the input argument. */ + break; + } + } + + /* Return with the power level in dBm or with the + termination value RF_TxPowerTable_INVALID_DBM. */ + return(table[i].power); +} + +/* + * ======== RF_TxPowerTable_findValue ======== + * Retrieves a power configuration value for a given power level in dBm. + */ +RF_TxPowerTable_Value RF_TxPowerTable_findValue(RF_TxPowerTable_Entry table[], int8_t powerLevel) +{ + /* Local variable stores an invalid value. */ + RF_TxPowerTable_Value invalidValue = { .rawValue = RF_TxPowerTable_INVALID_VALUE, + .paType = RF_TxPowerTable_DefaultPA }; + + /* Handle special input argument. */ + if (powerLevel == RF_TxPowerTable_MIN_DBM) + { + return(table[0].value); + } + else + { + /* Iterate through the power table. We do not verify against nullptr. */ + uint32_t i; + for (i=0; ((int8_t)table[i].power != (int8_t)RF_TxPowerTable_INVALID_DBM) && + ((uint32_t)table[i].value.rawValue != (uint32_t)RF_TxPowerTable_INVALID_VALUE); i++) + { + if (table[i].power > powerLevel) + { + /* Break the loop on the first entry which satisfies + the lower-or-equal criterion toward the input argument. */ + break; + } + } + + if (i == 0) + { + /* If the first entry is already larger, then the requested + power level is invalid. */ + return(invalidValue); + } + else + { + /* Return with a valid RF_TxPowerTable_Value or with the + maximum value in the table. */ + return(table[i-1].value); + } + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/lib/rf_multiMode_cc13x0.am3g b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/lib/rf_multiMode_cc13x0.am3g new file mode 100644 index 0000000..2773c90 Binary files /dev/null and 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b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/lib/rf_singleMode_cc26x0.am3g differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/lib/rf_singleMode_cc26x0.arm3 b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/lib/rf_singleMode_cc26x0.arm3 new file mode 100644 index 0000000..d281701 Binary files /dev/null and b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/lib/rf_singleMode_cc26x0.arm3 differ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sd/SDSPI.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sd/SDSPI.c new file mode 100644 index 0000000..85bc675 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sd/SDSPI.c @@ -0,0 +1,785 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== SDSPI.c ======== + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* Definitions for MMC/SDC command */ +#define CMD0 (0x40+0) /* GO_IDLE_STATE */ +#define CMD1 (0x40+1) /* SEND_OP_COND */ +#define CMD8 (0x40+8) /* SEND_IF_COND */ +#define CMD9 (0x40+9) /* SEND_CSD */ +#define CMD10 (0x40+10) /* SEND_CID */ +#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ +#define CMD16 (0x40+16) /* SET_BLOCKLEN */ +#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ +#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ +#define CMD23 (0x40+23) /* SET_BLOCK_COUNT */ +#define CMD24 (0x40+24) /* WRITE_BLOCK */ +#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ +#define CMD41 (0x40+41) /* SEND_OP_COND (ACMD) */ +#define CMD55 (0x40+55) /* APP_CMD */ +#define CMD58 (0x40+58) /* READ_OCR */ +#define START_BLOCK_TOKEN (0xFE) +#define START_MULTIBLOCK_TOKEN (0xFC) +#define STOP_MULTIBLOCK_TOKEN (0xFD) + +#define SD_SECTOR_SIZE (512) + +#define DRIVE_NOT_MOUNTED ((uint16_t) ~0) + +void SDSPI_close(SD_Handle handle); +int_fast16_t SDSPI_control(SD_Handle handle, uint_fast16_t cmd, + void *arg); +uint_fast32_t SDSPI_getNumSectors(SD_Handle handle); +uint_fast32_t SDSPI_getSectorSize(SD_Handle handle); +int_fast16_t SDSPI_initialize(SD_Handle handle); +void SDSPI_init(SD_Handle handle); +SD_Handle SDSPI_open(SD_Handle handle, SD_Params *params); +int_fast16_t SDSPI_read(SD_Handle handle, void *buf, + int_fast32_t sector, uint_fast32_t sectorCount); +int_fast16_t SDSPI_write(SD_Handle handle, const void *buf, + int_fast32_t sector, uint_fast32_t sectorCount); + +static inline void assertCS(SDSPI_HWAttrs const *hwAttrs); +static inline void deassertCS(SDSPI_HWAttrs const *hwAttrs); +static bool recvDataBlock(SPI_Handle handle, void *buf, uint32_t count); +static uint8_t sendCmd(SPI_Handle handle, uint8_t cmd, uint32_t arg); +static int_fast16_t sendInitialClockTrain(SPI_Handle handle); +static int_fast16_t spiTransfer(SPI_Handle handle, void *rxBuf, + void *txBuf, size_t count); +static bool waitUntilReady(SPI_Handle handle); +static bool transmitDataBlock(SPI_Handle handle, void *buf, uint32_t count, + uint8_t token); + +/* SDSPI function table for SDSPIMSP432 implementation */ +const SD_FxnTable SDSPI_fxnTable = { + SDSPI_close, + SDSPI_control, + SDSPI_getNumSectors, + SDSPI_getSectorSize, + SDSPI_init, + SDSPI_initialize, + SDSPI_open, + SDSPI_read, + SDSPI_write +}; + +/* + * ======== SDSPI_close ======== + */ +void SDSPI_close(SD_Handle handle) +{ + SDSPI_Object *object = handle->object; + + if (object->spiHandle) { + SPI_close(object->spiHandle); + object->spiHandle = NULL; + } + + if (object->lockSem) { + SemaphoreP_delete(object->lockSem); + object->lockSem = NULL; + } + + object->cardType = SD_NOCARD; + object->isOpen = false; +} + +/* + * ======== SDSPI_control ======== + */ +int_fast16_t SDSPI_control(SD_Handle handle, uint_fast16_t cmd, + void *arg) +{ + return (SD_STATUS_UNDEFINEDCMD); +} + +/* + * ======== SDSPI_getNumSectors ======== + */ +uint_fast32_t SDSPI_getNumSectors(SD_Handle handle) +{ + uint8_t n; + uint8_t csd[16]; + uint16_t csize; + uint32_t sectors = 0; + SDSPI_Object *object = handle->object; + SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; + + SemaphoreP_pend(object->lockSem, SemaphoreP_WAIT_FOREVER); + + assertCS(hwAttrs); + + /* Get number of sectors on the disk (uint32_t) */ + if ((sendCmd(object->spiHandle, CMD9, 0) == 0) && + recvDataBlock(object->spiHandle, csd, 16)) { + /* SDC ver 2.00 */ + if ((csd[0] >> 6) == 1) { + csize = csd[9] + (csd[8] << 8) + 1; + sectors = csize << 10; + } + /* MMC or SDC ver 1.XX */ + else { + n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + + ((csd[9] & 3) << 1) + 2; + + csize = (csd[8] >> 6) + ((uint16_t) csd[7] << 2) + + ((uint16_t) (csd[6] & 3) << 10) + 1; + sectors = (uint32_t)csize << (n - 9); + } + } + + deassertCS(hwAttrs); + + SemaphoreP_post(object->lockSem); + + return (sectors); +} + +/* + * ======== SDSPI_getSectorSize ======== + */ +uint_fast32_t SDSPI_getSectorSize(SD_Handle handle) +{ + return (SD_SECTOR_SIZE); +} + +/* + * ======== SDSPI_init ======== + */ +void SDSPI_init(SD_Handle handle) +{ + GPIO_init(); + SPI_init(); +} + +/* + * ======== SDSPI_initialize ======== + */ +int_fast16_t SDSPI_initialize(SD_Handle handle) +{ + SD_CardType cardType = SD_NOCARD; + uint8_t i; + uint8_t ocr[4]; + uint8_t txDummy[4] = {0xFF, 0xFF, 0xFF, 0xFF}; + int_fast16_t status; + uint32_t currentTime; + uint32_t startTime; + uint32_t timeout; + SPI_Params spiParams; + SDSPI_Object *object = handle->object; + SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; + + SemaphoreP_pend(object->lockSem, SemaphoreP_WAIT_FOREVER); + + /* + * Part of the process to initialize the SD Card to SPI mode - Do not + * assert CS during this time + */ + sendInitialClockTrain(object->spiHandle); + + /* Now select the SD Card's chip select to send CMD0 command */ + assertCS(hwAttrs); + + /* + * Send CMD0 to put the SD card in idle SPI mode. Some SD cards may not + * respond correctly to CMD0 on the first attempt; so we will try for up + * to 10 attempts (cards will usually respond correctly on the 3rd or 4th + * attempt). Failure is returned if the card does not return the correct + * response with the 10 attempts. + */ + i = 10; + do { + status = sendCmd(object->spiHandle, CMD0, 0); + } while ((status != 1) && (--i)); + + /* Proceed with initialization only if SD Card is in "Idle" state */ + if (status == 1) { + /* + * Determine what SD Card version we are dealing with + * Depending on which SD Card version, we need to send different SD + * commands to the SD Card, which will have different response fields. + */ + if (sendCmd(object->spiHandle, CMD8, 0x1AA) == 1) { + /* SD Version 2.0 or higher */ + status = spiTransfer(object->spiHandle, &ocr, &txDummy, 4); + if (status == SD_STATUS_SUCCESS) { + /* + * Ensure that the card's voltage range is valid + * The card can work at VDD range of 2.7-3.6V + */ + if ((ocr[2] == 0x01) && (ocr[3] == 0xAA)) { + /* + * Wait for data packet in timeout of 1s - status used to + * indicate if a timeout occurred before operation + * completed. + */ + status = SD_STATUS_ERROR; + timeout = 1000000/ClockP_getSystemTickPeriod(); + startTime = ClockP_getSystemTicks(); + + do { + /* ACMD41 with HCS bit */ + if ((sendCmd(object->spiHandle, CMD55, 0) <= 1) && + (sendCmd(object->spiHandle, CMD41, 1UL << 30) == 0)) { + status = SD_STATUS_SUCCESS; + break; + } + currentTime = ClockP_getSystemTicks(); + } while ((currentTime - startTime) < timeout); + + /* + * Check CCS bit to determine which type of capacity we are + * dealing with + */ + if ((status == SD_STATUS_SUCCESS) && + sendCmd(object->spiHandle, CMD58, 0) == 0) { + status = spiTransfer(object->spiHandle, &ocr, &txDummy, 4); + if (status == SD_STATUS_SUCCESS) { + cardType = (ocr[0] & 0x40) ? SD_SDHC : SD_SDSC; + } + } + } + } + } + else { + /* SDC Ver1 or MMC */ + /* + * The card version is not SDC V2+ so check if we are dealing with a + * SDC or MMC card + */ + if ((sendCmd(object->spiHandle, CMD55, 0) <= 1) && + (sendCmd(object->spiHandle, CMD41, 0) <= 1)) { + cardType = SD_SDSC; + } + else { + cardType = SD_MMC; + } + + /* + * Wait for data packet in timeout of 1s - status used to + * indicate if a timeout occurred before operation + * completed. + */ + status = SD_STATUS_ERROR; + timeout = 1000000/ClockP_getSystemTickPeriod(); + startTime = ClockP_getSystemTicks(); + do { + if (cardType == SD_SDSC) { + /* ACMD41 */ + if ((sendCmd(object->spiHandle, CMD55, 0) <= 1) && + (sendCmd(object->spiHandle, CMD41, 0) == 0)) { + status = SD_STATUS_SUCCESS; + break; + } + } + else { + /* CMD1 */ + if (sendCmd(object->spiHandle, CMD1, 0) == 0) { + status = SD_STATUS_SUCCESS; + break; + } + } + currentTime = ClockP_getSystemTicks(); + } while ((currentTime - startTime) < timeout); + + /* Select R/W block length */ + if ((status == SD_STATUS_ERROR) || + (sendCmd(object->spiHandle, CMD16, SD_SECTOR_SIZE) != 0)) { + cardType = SD_NOCARD; + } + } + } + + object->cardType = cardType; + + deassertCS(hwAttrs); + + /* Check to see if a card type was determined */ + if (cardType == SD_NOCARD) { + status = SD_STATUS_ERROR; + } + else { + /* Reconfigure the SPI to operate @ 2.5 MHz */ + SPI_close(object->spiHandle); + + SPI_Params_init(&spiParams); + spiParams.bitRate = 2500000; + object->spiHandle = SPI_open(hwAttrs->spiIndex, &spiParams); + status = (object->spiHandle == NULL) ? SD_STATUS_ERROR : + SD_STATUS_SUCCESS; + } + + SemaphoreP_post(object->lockSem); + + return (status); +} + +/* + * ======== SDSPI_open ======== + */ +SD_Handle SDSPI_open(SD_Handle handle, SD_Params *params) +{ + uintptr_t key; + SPI_Params spiParams; + SDSPI_Object *object = handle->object; + SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; + + key = HwiP_disable(); + + if (object->isOpen) { + HwiP_restore(key); + + return (NULL); + } + object->isOpen = true; + + HwiP_restore(key); + + object->lockSem = SemaphoreP_createBinary(1); + if (object->lockSem == NULL) { + object->isOpen = false; + + return (NULL); + } + + /* + * SPI is initially set to 400 kHz to perform SD initialization. This is + * is done to ensure compatibility with older SD cards. Once the card has + * been initialized (in SPI mode) the SPI peripheral will be closed & + * reopened at 2.5 MHz. + */ + SPI_Params_init(&spiParams); + spiParams.bitRate = 400000; + object->spiHandle = SPI_open(hwAttrs->spiIndex, &spiParams); + if (object->spiHandle == NULL) { + SDSPI_close(handle); + + return (NULL); + } + + /* Configure the SPI CS pin as output set high */ + GPIO_setConfig(hwAttrs->spiCsGpioIndex, + GPIO_CFG_OUT_STD | GPIO_CFG_OUT_HIGH); + + return (handle); +} + +/* + * ======== SDSPI_read ======== + */ +int_fast16_t SDSPI_read(SD_Handle handle, void *buf, int_fast32_t sector, + uint_fast32_t sectorCount) +{ + int_fast16_t status = SD_STATUS_ERROR; + SDSPI_Object *object = handle->object; + SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (sectorCount == 0) { + return (SD_STATUS_ERROR); + } + + SemaphoreP_pend(object->lockSem, SemaphoreP_WAIT_FOREVER); + + /* + * On a SDSC card, the sector address is a byte address on the SD Card + * On a SDHC card, the sector addressing is via sector blocks + */ + if (object->cardType != SD_SDHC) { + /* Convert to byte address */ + sector *= SD_SECTOR_SIZE; + } + + assertCS(hwAttrs); + + /* Single block read */ + if (sectorCount == 1) { + if ((sendCmd(object->spiHandle, CMD17, sector) == 0) && + recvDataBlock(object->spiHandle, buf, SD_SECTOR_SIZE)) { + status = SD_STATUS_SUCCESS; + } + } + /* Multiple block read */ + else { + if (sendCmd(object->spiHandle, CMD18, sector) == 0) { + do { + if (!recvDataBlock(object->spiHandle, buf, SD_SECTOR_SIZE)) { + break; + } + buf = (void *) (((uint32_t) buf) + SD_SECTOR_SIZE); + } while (--sectorCount); + + /* + * STOP_TRANSMISSION - order is important; always want to send + * stop signal + */ + if (sendCmd(object->spiHandle, CMD12, 0) == 0 && sectorCount == 0) { + status = SD_STATUS_SUCCESS; + } + } + } + + deassertCS(hwAttrs); + + SemaphoreP_post(object->lockSem); + + return (status); +} + +/* + * ======== SDSPI_write ======== + */ +int_fast16_t SDSPI_write(SD_Handle handle, const void *buf, + int_fast32_t sector, uint_fast32_t sectorCount) +{ + int_fast16_t status = SD_STATUS_SUCCESS; + SDSPI_Object *object = handle->object; + SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (sectorCount == 0) { + return (SD_STATUS_ERROR); + } + + SemaphoreP_pend(object->lockSem, SemaphoreP_WAIT_FOREVER); + + /* + * On a SDSC card, the sector address is a byte address on the SD Card + * On a SDHC card, the sector addressing is via sector blocks + */ + if (object->cardType != SD_SDHC) { + /* Convert to byte address if needed */ + sector *= SD_SECTOR_SIZE; + } + + assertCS(hwAttrs); + + /* Single block write */ + if (sectorCount == 1) { + if ((sendCmd(object->spiHandle, CMD24, sector) == 0) && + transmitDataBlock(object->spiHandle, (void *) buf, SD_SECTOR_SIZE, + START_BLOCK_TOKEN)) { + sectorCount = 0; + } + } + /* Multiple block write */ + else { + if ((object->cardType == SD_SDSC) || (object->cardType == SD_SDHC)) { + if (sendCmd(object->spiHandle, CMD55, 0) != 0) { + status = SD_STATUS_ERROR; + } + + /* ACMD23 */ + if ((status == SD_STATUS_SUCCESS) && + (sendCmd(object->spiHandle, CMD23, sectorCount) != 0)) { + status = SD_STATUS_ERROR; + } + } + + /* WRITE_MULTIPLE_BLOCK command */ + if ((status == SD_STATUS_SUCCESS) && + (sendCmd(object->spiHandle, CMD25, sector) == 0)) { + do { + if (!transmitDataBlock(object->spiHandle, (void *) buf, + SD_SECTOR_SIZE, START_MULTIBLOCK_TOKEN)) { + break; + } + buf = (void *) (((uint32_t) buf) + SD_SECTOR_SIZE); + } while (--sectorCount); + + /* STOP_TRAN token */ + if (!transmitDataBlock(object->spiHandle, NULL, 0, + STOP_MULTIBLOCK_TOKEN)) { + sectorCount = 1; + } + } + } + + deassertCS(hwAttrs); + + SemaphoreP_post(object->lockSem); + + return ((sectorCount) ? SD_STATUS_ERROR : SD_STATUS_SUCCESS); +} + +/* + * ======== assertCS ======== + */ +static inline void assertCS(SDSPI_HWAttrs const *hwAttrs) +{ + GPIO_write(hwAttrs->spiCsGpioIndex, 0); +} + +/* + * ======== deassertCS ======== + */ +static inline void deassertCS(SDSPI_HWAttrs const *hwAttrs) +{ + GPIO_write(hwAttrs->spiCsGpioIndex, 1); +} + +/* + * ======== recvDataBlock ======== + * Function to receive a block of data from the SDCard + */ +static bool recvDataBlock(SPI_Handle handle, void *buf, uint32_t count) +{ + uint8_t rxBuf[2]; + uint8_t txBuf[2] = {0xFF, 0xFF}; + int_fast16_t status; + uint32_t currentTime; + uint32_t startTime; + uint32_t timeout; + + /* + * Wait for SD card to be ready up to 1s. SD card is ready when the + * START_BLOCK_TOKEN is received. + */ + timeout = 1000000/ClockP_getSystemTickPeriod(); + startTime = ClockP_getSystemTicks(); + do { + status = spiTransfer(handle, &rxBuf, &txBuf, 1); + currentTime = ClockP_getSystemTicks(); + } while ((status == SD_STATUS_SUCCESS) && (rxBuf[0] == 0xFF) && + (currentTime - startTime) < timeout); + + if (rxBuf[0] != START_BLOCK_TOKEN) { + /* Return error if valid data token was not received */ + return (false); + } + + /* Receive the data block into buffer */ + if (spiTransfer(handle, buf, NULL, count) != SD_STATUS_SUCCESS) { + return (false); + } + + /* Read the 16 bit CRC, but discard it */ + if (spiTransfer(handle, &rxBuf, &txBuf, 2) != SD_STATUS_SUCCESS) { + return (false); + } + + /* Return with success */ + return (true); +} + +/* + * ======== sendCmd ======== + * Function to send a command to the SD card. Command responses from + * SD card are returned. (0xFF) is returned on failures. + */ +static uint8_t sendCmd(SPI_Handle handle, uint8_t cmd, uint32_t arg) +{ + uint8_t i; + uint8_t rxBuf; + uint8_t txBuf[6]; + int_fast16_t status; + + if ((cmd != CMD0) && !waitUntilReady(handle)) { + return (0xFF); + } + + /* Setup SPI transaction */ + txBuf[0] = cmd; /* Command */ + txBuf[1] = (uint8_t)(arg >> 24); /* Argument[31..24] */ + txBuf[2] = (uint8_t)(arg >> 16); /* Argument[23..16] */ + txBuf[3] = (uint8_t)(arg >> 8); /* Argument[15..8] */ + txBuf[4] = (uint8_t) arg; /* Argument[7..0] */ + + if (cmd == CMD0) { + /* CRC for CMD0(0) */ + txBuf[5] = 0x95; + } + else if (cmd == CMD8) { + /* CRC for CMD8(0x1AA) */ + txBuf[5] = 0x87; + } + else { + /* Default CRC should be at least 0x01 */ + txBuf[5] = 0x01; + } + + if (spiTransfer(handle, NULL, &txBuf, 6) != SD_STATUS_SUCCESS) { + return (0xFF); + } + + /* Prepare to receive SD card response (send 0xFF) */ + txBuf[0] = 0xFF; + + /* + * CMD 12 has R1b response which transfers an additional + * "busy" byte + */ + if ((cmd == CMD12) && + (spiTransfer(handle, &rxBuf, &txBuf, 1) != SD_STATUS_SUCCESS)) { + return (0xFF); + } + + /* Wait for a valid response; 10 attempts */ + i = 10; + do { + status = spiTransfer(handle, &rxBuf, &txBuf, 1); + } while ((status == SD_STATUS_SUCCESS) && (rxBuf & 0x80) && (--i)); + + /* Return with the response value */ + return (rxBuf); +} + +/* + * ======== sendInitialClockTrain ======== + * Function to get the SDCard into SPI mode + */ +static int_fast16_t sendInitialClockTrain(SPI_Handle handle) +{ + uint8_t txBuf[10] = { + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF + }; + + /* + * To put the SD card in SPI mode we must keep the TX line high while + * toggling the clock line several times. To do this we transmit 0xFF + * 10 times. + */ + return (spiTransfer(handle, NULL, &txBuf, 10)); +} + +/* + * ======== spiTransfer ======== + * Returns SD_STATUS_SUCCESS when transfer is completed; + * SD_STATUS_ERROR otherwise. + */ +static int_fast16_t spiTransfer(SPI_Handle handle, void *rxBuf, + void *txBuf, size_t count) { + int_fast16_t status; + SPI_Transaction transaction; + + transaction.rxBuf = rxBuf; + transaction.txBuf = txBuf; + transaction.count = count; + + status = (SPI_transfer(handle, &transaction)) ? + SD_STATUS_SUCCESS : SD_STATUS_ERROR; + + return (status); +} + +/* + * ======== transmitDataBlock ======== + * Function to transmit a block of data to the SD card. A valid command + * token must be sent to the SD card prior to sending the data block. + * The available tokens are: + * START_BLOCK_TOKEN + * START_MULTIBLOCK_TOKEN + * STOP_MULTIBLOCK_TOKEN + */ +static bool transmitDataBlock(SPI_Handle handle, void *buf, uint32_t count, + uint8_t token) +{ + uint8_t rxBuf; + uint8_t txBuf[2] = {0xFF, 0xFF}; + + if (!waitUntilReady(handle)) { + return (false); + } + + /* transmit data token */ + txBuf[0] = token; + if (spiTransfer(handle, NULL, &txBuf, 1) != SD_STATUS_SUCCESS) { + return (false); + } + + /* Send data only when token != STOP_MULTIBLOCK_TOKEN */ + if (token != STOP_MULTIBLOCK_TOKEN) { + /* Write data to the SD card */ + if (spiTransfer(handle, NULL, buf, count) != SD_STATUS_SUCCESS) { + return (false); + } + + /* Receive the 16 bit CRC, but discard it */ + txBuf[0] = (0xFF); + if (spiTransfer(handle, NULL, &txBuf, 2) != SD_STATUS_SUCCESS) { + return (false); + } + + /* Receive data response token from SD card */ + if (spiTransfer(handle, &rxBuf, &txBuf, 1) != SD_STATUS_SUCCESS) { + return (false); + } + + /* Check data response; return error if data was rejected */ + if ((rxBuf & 0x1F) != 0x05) { + return (false); + } + } + + return (true); +} + +/* + * ======== waitUntilReady ======== + * Function to check if the SD card is busy. + * + * Returns true if SD card is ready; false indicates the SD card is still busy + * & a timeout occurred. + */ +static bool waitUntilReady(SPI_Handle handle) +{ + uint8_t rxDummy; + uint8_t txDummy = 0xFF; + int_fast16_t status; + uint32_t currentTime; + uint32_t startTime; + uint32_t timeout; + + /* Wait up to 1s for data packet */ + timeout = 1000000/ClockP_getSystemTickPeriod(); + startTime = ClockP_getSystemTicks(); + do { + status = spiTransfer(handle, &rxDummy, &txDummy, 1); + currentTime = ClockP_getSystemTicks(); + } while ((status == SD_STATUS_SUCCESS) && (rxDummy != 0xFF) && + (currentTime - startTime) < timeout); + + return (rxDummy == 0xFF); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sd/SDSPI.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sd/SDSPI.h new file mode 100644 index 0000000..cb135d6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sd/SDSPI.h @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!*************************************************************************** + * @file SDSPI.h + * + * @brief SD driver implementation built on the TI SPI driver. + * + * The SDSPI header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref SD.h for a complete description of APIs & example of use. + * + * This SD driver implementation can be used to communicate with SD cards + * via a SPI peripheral. This driver leverages the TI SPI driver to transfer + * data to/from the host processor to the SD card. The SD card chip select + * is also handled by this driver via the TI GPIO driver. Both the SPI + * driver instance & the GPIO pin (used as chip select) must be specified + * in the SDSPI hardware attributes. + * + * Note: This driver requires that the 'defaultTxBufValue' field in the SPI + * driver hardware attributes be set to '0xFF'. + * + * ## Data location & alignment # + * + * This driver relies on the TI SPI driver to configure the SPI peripheral & + * perform data transfers. This means that data to be transferred must comply + * with rules & restrictions set SPI driver (memory alignment & DMA + * accessibility requirements). Refer to @ref SPI.h & the device specific + * SPI implementation header files for details. + * + *
+ */ + +#ifndef ti_drivers_sd_SDSPI__include +#define ti_drivers_sd_SDSPI__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +/* SDSPI function table */ +extern const SD_FxnTable SDSPI_fxnTable; + +/*! + * @brief SDSPI Hardware attributes + * + * The #SDSPI_HWAttrs configuration structure contains the index of the SPI + * peripheral to be used for data transfers & the index of the GPIO Pin which + * will act as chip select. This driver uses this information to: + * - configure & open the SPI driver instance for data transfers + * - select the SD card (via chip select) when performing data transfers + * + * @struct SDSPI_HWAttrs + * An example configuration structure could look as the following: + * @code + * const SDSPI_HWAttrs sdspiHWAttrs[1] = { + * { + * // SPI driver index + * .spiIndex = 0, + * + * // GPIO driver pin index + * .spiCsGpioIndex = 3 + * } + * }; + * @endcode + */ +typedef struct SDSPI_HWAttrs_ { + uint_least8_t spiIndex; + uint16_t spiCsGpioIndex; +} SDSPI_HWAttrs; + +/*! + * @brief SDSPI Object + * + * The application must not access any member variables of this structure! + */ +typedef struct SDSPI_Object_ { + SemaphoreP_Handle lockSem; + SPI_Handle spiHandle; + SD_CardType cardType; + bool isOpen; +} SDSPI_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_sd_SDSPI__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sha2/SHA2CC26X2.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sha2/SHA2CC26X2.c new file mode 100644 index 0000000..584c3ad --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sha2/SHA2CC26X2.c @@ -0,0 +1,706 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/sha2.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/smph.h) + +/* Defines and enumerations */ +#define SHA2_UNUSED(value) ((void)(value)) + +typedef enum { + SHA2_OperationType_SingleStep, + SHA2_OperationType_MultiStep, + SHA2_OperationType_Finalize, +} SHA2_OperationType; + +/* Forward declarations */ +static uint32_t floorUint32(uint32_t value, uint32_t divider); +static void SHA2_hwiFxn (uintptr_t arg0); +static int_fast16_t SHA2_waitForAccess(SHA2_Handle handle); +static int_fast16_t SHA2_waitForResult(SHA2_Handle handle); + +/* Static globals */ +static const uint32_t hashModeTable[] = { + SHA2_MODE_SELECT_SHA224, + SHA2_MODE_SELECT_SHA256, + SHA2_MODE_SELECT_SHA384, + SHA2_MODE_SELECT_SHA512 +}; + +static const uint8_t blockSizeTable[] = { + SHA2_BLOCK_SIZE_BYTES_224, + SHA2_BLOCK_SIZE_BYTES_256, + SHA2_BLOCK_SIZE_BYTES_384, + SHA2_BLOCK_SIZE_BYTES_512 +}; + +static const uint8_t digestSizeTable[] = { + SHA2_DIGEST_LENGTH_BYTES_224, + SHA2_DIGEST_LENGTH_BYTES_256, + SHA2_DIGEST_LENGTH_BYTES_384, + SHA2_DIGEST_LENGTH_BYTES_512 +}; + +static const uint8_t *SHA2_data; + +static uint32_t SHA2_dataBytesRemaining; + +static SHA2_OperationType SHA2_operationType; + +static bool isInitialized = false; + +/* + * ======== floorUint32 helper ======== + */ +uint32_t floorUint32(uint32_t value, uint32_t divider) { + return (value / divider) * divider; +} + +/* + * ======== SHA2_hwiFxn ======== + */ +static void SHA2_hwiFxn (uintptr_t arg0) { + SHA2CC26X2_Object *object = ((SHA2_Handle)arg0)->object; + uint32_t blockSize = blockSizeTable[object->hashType];; + uint32_t irqStatus; + uint32_t key; + + irqStatus = SHA2IntStatusRaw(); + SHA2IntClear(SHA2_RESULT_RDY | SHA2_DMA_IN_DONE | SHA2_DMA_BUS_ERR); + + /* + * Prevent the following section from being interrupted by SHA2_cancelOperation(). + */ + key = HwiP_disable(); + + if (object->operationCanceled) { + /* + * If the operation has been canceled we can end here. + * Cleanup is done by SHA2_cancelOperation() + */ + HwiP_restore(key); + return; + + } else if (irqStatus & SHA2_DMA_BUS_ERR) { + /* + * In the unlikely event of an error we can stop here. + */ + object->returnStatus = SHA2_STATUS_ERROR; + + } else if (SHA2_dataBytesRemaining == 0) { + /* + * Last transaction has finished. Nothing to do. + */ + + } else if (SHA2_dataBytesRemaining >= blockSize) { + /* + * Start another transaction + */ + uint32_t transactionLength = floorUint32(SHA2_dataBytesRemaining, blockSize); + + SHA2ComputeIntermediateHash(SHA2_data, + object->digest, + hashModeTable[object->hashType], + transactionLength); + + SHA2_dataBytesRemaining -= transactionLength; + SHA2_data += transactionLength; + object->bytesProcessed += transactionLength; + + HwiP_restore(key); + return; + + } else if (SHA2_dataBytesRemaining > 0) { + /* + * Copy remaining data into buffer + */ + memcpy(object->buffer, SHA2_data, SHA2_dataBytesRemaining); + object->bytesInBuffer += SHA2_dataBytesRemaining; + SHA2_dataBytesRemaining = 0; + } + + /* + * Since we got here, every transaction has been finished + */ + object->operationInProgress = false; + + /* + * Reset byte counter if a hash has been finalized + */ + if (SHA2_operationType != SHA2_OperationType_MultiStep) { + object->bytesProcessed = 0; + object->bytesInBuffer = 0; + } + + HwiP_restore(key); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK) + { + if (object->callbackFxn) { + object->callbackFxn((SHA2_Handle)arg0, object->returnStatus); + } + } +} + + +/* + * ======== SHA2_waitForAccess ======== + */ +static int_fast16_t SHA2_waitForAccess(SHA2_Handle handle) { + SHA2CC26X2_Object *object = handle->object; + + return SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->accessTimeout); +} + +/* + * ======== SHA2_waitForResult ======== + */ +static int_fast16_t SHA2_waitForResult(SHA2_Handle handle){ + SHA2CC26X2_Object *object = handle->object; + + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_POLLING) { + do { + SHA2WaitForIRQFlags(SHA2_RESULT_RDY | SHA2_DMA_BUS_ERR); + SHA2_hwiFxn((uintptr_t)handle); + } while (object->operationInProgress); + + return object->returnStatus; + } + else if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, (uint32_t)SemaphoreP_WAIT_FOREVER); + + return object->returnStatus; + } + else { + return SHA2_STATUS_SUCCESS; + } + +} + +/* + * ======== SHA2_init ======== + */ +void SHA2_init(void) { + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== SHA2_open ======== + */ +SHA2_Handle SHA2_open(uint_least8_t index, const SHA2_Params *params) { + DebugP_assert(index < SHA2_count); + + SHA2_Config *config = (SHA2_Config*)&SHA2_config[index]; + return SHA2CC26X2_construct(config, params); +} + +/* + * ======== SHA2_construct ======== + */ +SHA2_Handle SHA2CC26X2_construct(SHA2_Config *config, const SHA2_Params *params) { + SHA2_Handle handle; + SHA2CC26X2_Object *object; + uint_fast8_t key; + + handle = (SHA2_Config*)config; + object = handle->object; + + key = HwiP_disable(); + + if (object->isOpen || !isInitialized) { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + object->operationInProgress = false; + object->operationCanceled = false; + + HwiP_restore(key); + + if (params == NULL) { + params = &SHA2_defaultParams; + } + + DebugP_assert(params->returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + object->bytesInBuffer = 0; + object->bytesProcessed = 0; + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + object->hashType = params->hashType; + + if (params->returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) { + object->accessTimeout = params->timeout; + } else { + object->accessTimeout = SemaphoreP_NO_WAIT; + } + + /* Set power dependency - i.e. power up and enable clock for Crypto (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== SHA2_close ======== + */ +void SHA2_close(SHA2_Handle handle) { + SHA2CC26X2_Object *object; + uintptr_t key; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* If there is still an operation ongoing, abort it now. */ + key = HwiP_disable(); + if (object->operationInProgress) { + SHA2_cancelOperation(handle); + } + object->isOpen = false; + HwiP_restore(key); + + /* Release power dependency on Crypto Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== SHA2_startHash ======== + */ +int_fast16_t SHA2_addData(SHA2_Handle handle, const void* data, size_t length) { + SHA2CC26X2_Object *object = handle->object; + SHA2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t blockSize = blockSizeTable[object->hashType]; + uintptr_t key; + + /* Try and obtain access to the crypto module */ + if (SHA2_waitForAccess(handle) != SemaphoreP_OK) { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* If we are in SHA2_RETURN_BEHAVIOR_POLLING, we do not want an interrupt to trigger. + * We need to disable it before kicking off the operation. + */ + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_POLLING) { + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + else { + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, SHA2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + object->returnStatus = SHA2_STATUS_SUCCESS; + object->operationCanceled = false; + SHA2_operationType = SHA2_OperationType_MultiStep; + + if ((object->bytesInBuffer + length) >= blockSize) { + /* We have accumulated enough data to start a transaction. Now the question + * remains whether we have to merge bytes from the data stream into the + * buffer first. If so, we do that now, then start a transaction. + * If the buffer is empty, we can start a transaction on the data stream. + * Once the transaction is finished, we will decide how to follow up, + * i.e. copy remaining data into the buffer. + */ + uint32_t transactionLength; + const uint8_t* transactionStartAddress; + + if (object->bytesInBuffer > 0) { + uint8_t *bufferTail = &object->buffer[object->bytesInBuffer]; + uint32_t bytesToCopyToBuffer = blockSize - object->bytesInBuffer; + memcpy(bufferTail, data, bytesToCopyToBuffer); + + /* We reset the value already. That saves a comparison + * in the ISR handler + */ + object->bytesInBuffer = 0; + + transactionStartAddress = object->buffer; + transactionLength = blockSize; + + SHA2_data = (const uint8_t*)data + bytesToCopyToBuffer; + SHA2_dataBytesRemaining = length - bytesToCopyToBuffer; + } else { + transactionStartAddress = data; + transactionLength = floorUint32(length, blockSize); + + SHA2_data = (const uint8_t*)data + transactionLength; + SHA2_dataBytesRemaining = length - transactionLength; + } + + /* + * Starting the accelerator and setting the operationInProgress + * flag must be atomic. + */ + key = HwiP_disable(); + + /* + * Finally we need to decide whether this is the first hash + * operation or a follow-up from a previous one. + */ + if (object->bytesProcessed > 0) { + SHA2ComputeIntermediateHash(transactionStartAddress, + object->digest, + hashModeTable[object->hashType], + transactionLength); + } else { + SHA2ComputeInitialHash(transactionStartAddress, + object->digest, + hashModeTable[object->hashType], + transactionLength); + } + + object->bytesProcessed += transactionLength; + object->operationInProgress = true; + HwiP_restore(key); + + } else { + /* There is no action required by the hardware. But we kick the + * interrupt in order to follow the same code path as the other + * operations. + */ + uint8_t *bufferTail = &object->buffer[object->bytesInBuffer]; + memcpy(bufferTail, data, length); + object->bytesInBuffer += length; + SHA2_dataBytesRemaining = 0; + + /* + * Asserting the IRQ and setting the operationInProgress + * flag must be atomic. + */ + key = HwiP_disable(); + object->operationInProgress = true; + SHA2IntEnable(SHA2_RESULT_RDY); + HWREG(CRYPTO_BASE + CRYPTO_O_IRQSET) = SHA2_RESULT_RDY; + HwiP_restore(key); + } + + return SHA2_waitForResult(handle); +} + +/* + * ======== SHA2_finalize ======== + */ +int_fast16_t SHA2_finalize(SHA2_Handle handle, void *digest) { + SHA2CC26X2_Object *object = handle->object; + SHA2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + + /* Try and obtain access to the crypto module */ + if (SHA2_waitForAccess(handle) != SemaphoreP_OK) { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* If we are in SHA2_RETURN_BEHAVIOR_POLLING, we do not want an interrupt to trigger. + * We need to disable it before kicking off the operation. + */ + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_POLLING) { + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + else { + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, SHA2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + object->returnStatus = SHA2_STATUS_SUCCESS; + object->operationCanceled = false; + SHA2_operationType = SHA2_OperationType_Finalize; + + /* + * Starting the accelerator and setting the operationInProgress + * flag must be atomic. + */ + key = HwiP_disable(); + object->operationInProgress = true; + + if (object->bytesProcessed == 0) { + /* + * Since no hash operation has been performed yet and no intermediate + * digest is available, we have to perform a full hash operation + */ + SHA2ComputeHash(object->buffer, + digest, + object->bytesInBuffer, + hashModeTable[object->hashType]); + } + else if (object->bytesInBuffer > 0) { + uint32_t totalLength = object->bytesProcessed + object->bytesInBuffer; + uint32_t chunkLength = object->bytesInBuffer; + + SHA2ComputeFinalHash(object->buffer, + digest, + object->digest, + totalLength, + chunkLength, + hashModeTable[object->hashType]); + } else { + /* + * The hardware is incapable of finalizing an empty partial message, + * but we can trick it by pretending this to be an intermediate block. + * + * Calculate the length in bits and put it at the end of the dummy + * finalization block in big endian order + */ + uint64_t lengthInBits = object->bytesProcessed * 8; + uint32_t blockSize = blockSizeTable[object->hashType]; + uint8_t *lengthBytes = (uint8_t*)&lengthInBits; + + /* + * Use the existing buffer as scratch pad + */ + memset(object->buffer, 0, blockSize); + + /* + * Final block starts with '10000000'. + */ + object->buffer[0] = 0x80; + + /* + * The length is written into the end of the finalization block + * in big endian order. We always write only the last 8 bytes. + */ + uint32_t i = 0; + for (i = 0; i < 4; i++) { + object->buffer[blockSize - 8 + i] = lengthBytes[7 - i]; + object->buffer[blockSize - 4 + i] = lengthBytes[3 - i]; + } + + /* + * SHA2ComputeIntermediateHash uses the same digest location for + * both input and output. Instead of copying the final digest result + * we use the final location as input and output. + */ + memcpy(digest, object->digest, digestSizeTable[object->hashType]); + + SHA2ComputeIntermediateHash(object->buffer, + digest, + hashModeTable[object->hashType], + blockSize); + } + + HwiP_restore(key); + + return SHA2_waitForResult(handle); +} + +/* + * ======== SHA2_hashData ======== + */ +int_fast16_t SHA2_hashData(SHA2_Handle handle, const void *data, size_t length, void *digest) { + SHA2CC26X2_Object *object = handle->object; + SHA2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + + /* Try and obtain access to the crypto module */ + if (SHA2_waitForAccess(handle) != SemaphoreP_OK) { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* If we are in SHA2_RETURN_BEHAVIOR_POLLING, we do not want an interrupt to trigger. + * We need to disable it before kicking off the operation. + */ + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_POLLING) { + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + else { + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, SHA2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + SHA2_operationType = SHA2_OperationType_SingleStep; + SHA2_dataBytesRemaining = 0; + + object->returnStatus = SHA2_STATUS_SUCCESS; + object->operationCanceled = false; + object->bytesInBuffer = 0; + object->bytesProcessed = 0; + + /* + * Starting the accelerator and setting the operationInProgress + * flag must be atomic. + */ + key = HwiP_disable(); + SHA2ComputeHash(data, + digest, + length, + hashModeTable[object->hashType]); + + object->operationInProgress = true; + HwiP_restore(key); + + return SHA2_waitForResult(handle); +} + +/* + * ======== SHA2_reset ======== + */ +void SHA2_reset(SHA2_Handle handle) +{ + SHA2CC26X2_Object *object = (SHA2CC26X2_Object*)handle->object; + + uint32_t key = HwiP_disable(); + + if (object->operationInProgress == true) + { + SHA2_cancelOperation(handle); + } + + object->bytesInBuffer = 0; + object->bytesProcessed = 0; + + HwiP_restore(key); +} + +/* + * ======== SHA2_cancelOperation ======== + */ +int_fast16_t SHA2_cancelOperation(SHA2_Handle handle) { + SHA2CC26X2_Object *object = handle->object; + uint32_t key; + + key = HwiP_disable(); + + if (!object->operationInProgress) { + HwiP_restore(key); + return SHA2_STATUS_ERROR; + } + + /* Reset the accelerator. Immediately stops ongoing operations. */ + HWREG(CRYPTO_BASE + CRYPTO_O_SWRESET) = CRYPTO_SWRESET_SW_RESET; + + /* Consume any outstanding interrupts we may have accrued + * since disabling interrupts. + */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->bytesInBuffer = 0; + object->bytesProcessed = 0; + object->operationCanceled = true; + object->returnStatus = SHA2_STATUS_CANCELED; + + HwiP_restore(key); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, SHA2_STATUS_CANCELED); + } + + return SHA2_STATUS_SUCCESS; +} + +int_fast16_t SHA2_setHashType(SHA2_Handle handle, SHA2_HashType type) { + + SHA2CC26X2_Object *object = (SHA2CC26X2_Object*)handle->object; + + if (object->operationInProgress) { + return SHA2_STATUS_ERROR; + } + + object->hashType = type; + + return SHA2_STATUS_SUCCESS; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sha2/SHA2CC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sha2/SHA2CC26X2.h new file mode 100644 index 0000000..15adef0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sha2/SHA2CC26X2.h @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SHA2CC26X2.h + * + * @brief SHA2 driver implementation for the CC26X2 family + * + * @warning This is a beta API. It may change in future releases. + * + * This file should only be included in the board file to fill the SHA2_config + * struct. + * + * The CC26XX family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation as well as SHA2 operations. + * Only one operation can be carried out on the accerator at a time. Mutual + * exclusion is implemented at the driver level and coordinated between all + * drivers relying onthe accelerator. It is transparent to the application + * and only noted ensure sensible access timeouts are set. + * + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + * + */ + +#ifndef ti_drivers_sha2_SHA2CC26X2__include +#define ti_drivers_sha2_SHA2CC26X2__include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/*! + * @brief Hardware-specific configuration attributes + * + * SHA2CC26X2 hardware attributes are used in the board file by the + * #SHA2_Config struct. + */ +typedef struct { + uint8_t intPriority; /*!< Hardware interrupt priority of the Hash accelerator. + * + * The CC26XX provides 8 interrupt priority levels encoded in three bits: + * + * Value | Description + * ------------ | ----------------------- + * (~0) | Special value: always lowest priority across all OS kernels. + * (7 << 5) | Priority level 7: lowest, but rather use ~0 instead. + * .. | .. + * (0 << 5) | Priority level 0: highest, not supported by this driver + * + * Hardware interrupts with priority level 0 ignore the hardware interrupt dispatcher + * for minimum latency. This is not supported by this driver. + */ +} SHA2CC26X2_HWAttrs; + + +/*! \cond Internal APIs */ + +#define SHA2CC26X2_MAX_BLOCK_SIZE_BYTES (SHA2_BLOCK_SIZE_BYTES_512) +#define SHA2CC26X2_MAX_DIGEST_LENGTH_BYTES (SHA2_DIGEST_LENGTH_BYTES_512) + +/* + * SHACC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct { + bool isOpen; + volatile bool operationInProgress; + bool operationCanceled; + SHA2_ReturnBehavior returnBehavior; + int_fast16_t returnStatus; + uint32_t accessTimeout; + SHA2_CallbackFxn callbackFxn; + SHA2_HashType hashType; + uint16_t bytesInBuffer; + uint32_t bytesProcessed; + uint8_t buffer[SHA2CC26X2_MAX_BLOCK_SIZE_BYTES]; + uint32_t digest[SHA2CC26X2_MAX_DIGEST_LENGTH_BYTES / 4]; +} SHA2CC26X2_Object; + +/* + * This function exists only because of mbedTLS. It is not a + * top-level function for now. + * + * Use it like this: + * + * SHA2CC26X2_Object object; + * const SHA2CC26X2_HWAttrs attrs = { + * .intPriority = 0xFF; + * }; + * + * SHA2_Config config = { + * .object = &object, + * .hwAttrs = &hwAttrs + * }; + * + * SHA2_Handle handle = SHA2_construct(&config, ...); + * + */ +SHA2_Handle SHA2CC26X2_construct(SHA2_Config *config, const SHA2_Params *params); + +/*! \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_sha2_SHA2CC26X2__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26X2DMA.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26X2DMA.c new file mode 100644 index 0000000..32b9b77 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26X2DMA.c @@ -0,0 +1,1556 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/ssi.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/udma.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/rom.h) + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_DMA_TRANSFER_AMOUNT (1024) + +/* SPI test control register */ +#define SSI_O_TCR (0x00000080) +#define SSI_TCR_TESTFIFO_ENABLE (0x2) +#define SSI_TCR_TESTFIFO_DISABLE (0x0) +/* SPI test data register */ +#define SSI_O_TDR (0x0000008C) + +#define PARAMS_DATASIZE_MIN (4) +#define PARAMS_DATASIZE_MAX (16) + +/* Allocate space for DMA control table entries */ +ALLOCATE_CONTROL_TABLE_ENTRY(dmaSpi0TxControlTableEntry, UDMA_CHAN_SSI0_TX); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaSpi0RxControlTableEntry, UDMA_CHAN_SSI0_RX); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaSpi1TxControlTableEntry, UDMA_CHAN_SSI1_TX); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaSpi1RxControlTableEntry, UDMA_CHAN_SSI1_RX); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaSpi0TxAltControlTableEntry, + (UDMA_CHAN_SSI0_TX | UDMA_ALT_SELECT)); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaSpi0RxAltControlTableEntry, + (UDMA_CHAN_SSI0_RX | UDMA_ALT_SELECT)); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaSpi1TxAltControlTableEntry, + (UDMA_CHAN_SSI1_TX | UDMA_ALT_SELECT)); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaSpi1RxAltControlTableEntry, + (UDMA_CHAN_SSI1_RX | UDMA_ALT_SELECT)); + +/* API Function Prototypes */ +void SPICC26X2DMA_close(SPI_Handle handle); +int_fast16_t SPICC26X2DMA_control(SPI_Handle handle, + uint_fast16_t cmd, + void *arg); +void SPICC26X2DMA_init(SPI_Handle handle); +SPI_Handle SPICC26X2DMA_open(SPI_Handle handle, SPI_Params *params); +static void SPICC26X2DMA_swiFxn (uintptr_t arg0, uintptr_t arg1); +bool SPICC26X2DMA_transfer(SPI_Handle handle, SPI_Transaction *transaction); +void SPICC26X2DMA_transferCancel(SPI_Handle handle); + +/* Local Function Prototypes */ +static void blockingTransferCallback(SPI_Handle handle, + SPI_Transaction *msg); +static void configNextTransfer(SPICC26X2DMA_Object *object, + SPICC26X2DMA_HWAttrs const *hwAttrs); +static void csnCallback(PIN_Handle handle, PIN_Id pinId); +static void flushFifos(SPICC26X2DMA_HWAttrs const *hwAttrs); +static inline uint32_t getDmaChannelNumber(uint32_t x); +static void initHw(SPI_Handle handle); +static bool initIO(SPI_Handle handle); +static inline void primeTransfer(SPICC26X2DMA_Object *object, + SPICC26X2DMA_HWAttrs const *hwAttrs); +static inline void releaseConstraint(uint32_t txBufAddr); +static inline void setConstraint(uint32_t txBufAddr); +static inline void spiPollingTransfer(SPICC26X2DMA_Object *object, + SPICC26X2DMA_HWAttrs const *hwAttrs, + SPI_Transaction *transaction); +static int spiPostNotify(unsigned int eventType, + uintptr_t eventArg, + uintptr_t clientArg); +static inline bool spiBusy(SPICC26X2DMA_Object *object, + SPICC26X2DMA_HWAttrs const *hwAttrs); + +/* SPI function table for SPICC26X2DMA implementation */ +const SPI_FxnTable SPICC26X2DMA_fxnTable = { + SPICC26X2DMA_close, + SPICC26X2DMA_control, + SPICC26X2DMA_init, + SPICC26X2DMA_open, + SPICC26X2DMA_transfer, + SPICC26X2DMA_transferCancel +}; + +/* Mapping SPI frame format from generic driver to CC26XX driverlib */ +static const uint32_t frameFormat[] = { + SSI_FRF_MOTO_MODE_0, /* SPI_POLO_PHA0 */ + SSI_FRF_MOTO_MODE_1, /* SPI_POLO_PHA1 */ + SSI_FRF_MOTO_MODE_2, /* SPI_POL1_PHA0 */ + SSI_FRF_MOTO_MODE_3, /* SPI_POL1_PHA1 */ + SSI_FRF_TI, /* SPI_TI */ + SSI_FRF_NMW /* SPI_MW */ +}; + +/* + * These lookup tables are used to configure the DMA channels for the + * appropriate (8bit or 16bit) transfer sizes. + */ +static const uint32_t dmaTxConfig[] = { + UDMA_MODE_PINGPONG | UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | + UDMA_ARB_4, + UDMA_MODE_PINGPONG | UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE | + UDMA_ARB_4 +}; + +static const uint32_t dmaRxConfig[] = { + UDMA_MODE_PINGPONG | UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | + UDMA_ARB_4, + UDMA_MODE_PINGPONG | UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | + UDMA_ARB_4 +}; + +static const uint32_t dmaNullConfig[] = { + UDMA_MODE_PINGPONG | UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | + UDMA_ARB_4, + UDMA_MODE_PINGPONG | UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | + UDMA_ARB_4 +}; + +/* + * ======== SPICC26X2DMA_close ======== + */ +void SPICC26X2DMA_close(SPI_Handle handle) +{ + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + SSIDisable(hwAttrs->baseAddr); + + HwiP_destruct(&(object->hwi)); + + UDMACC26XX_close(object->udmaHandle); + + SwiP_destruct(&(object->swi)); + + if (object->transferMode == SPI_MODE_BLOCKING) { + SemaphoreP_destruct(&(object->transferComplete)); + } + + PIN_close(object->pinHandle); + + Power_releaseDependency(hwAttrs->powerMngrId); + + Power_unregisterNotify(&object->spiPostObj); + + object->isOpen = false; +} + +/*! + * @brief Function for setting control parameters of the SPI driver + * after it has been opened. + * + * @pre SPICC26X2DMA_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A SPI handle returned from SPICC26X2DMA_open() + * + * @param cmd The command to execute, supported commands are: + * | Command | Description | + * |-------------------------------------------|------------------------------| + * | ::SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE | Enable RETURN_PARTIAL | + * | ::SPICC26X2DMA_CMD_RETURN_PARTIAL_DISABLE | Disable RETURN_PARTIAL | + * | ::SPICC26X2DMA_CMD_SET_CSN_PIN | Re-configure chip select pin | + * | ::SPICC26X2DMA_CMD_SET_MANUAL | Enable manual start mode | + * | ::SPICC26X2DMA_CMD_CLR_MANUAL | Disable manual start mode | + * | ::SPICC26X2DMA_CMD_MANUAL_START | Perform a manual start | + * + * @param *arg Pointer to command arguments. + * + * @return ::SPI_STATUS_SUCCESS if success, or error code if error. + */ +int_fast16_t SPICC26X2DMA_control(SPI_Handle handle, + uint_fast16_t cmd, + void *arg) +{ + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + PIN_Config pinConfig; + PIN_Id pinId; + + /* Initialize return value*/ + int ret = SPI_STATUS_ERROR; + + /* Perform command */ + switch(cmd) { + case SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE: + /* Enable RETURN_PARTIAL if slave mode is enabled */ + + if(object->mode == SPI_SLAVE){ + object->returnPartial = SPICC26X2DMA_retPartEnabledIntNotSet; + ret = SPI_STATUS_SUCCESS; + } + else{ + /* Partial return not available in master mode. */ + ret = SPI_STATUS_ERROR; + } + break; + + case SPICC26X2DMA_CMD_RETURN_PARTIAL_DISABLE: + /* Disable RETURN_PARTIAL */ + PIN_setInterrupt(object->pinHandle, object->csnPin); + object->returnPartial = SPICC26X2DMA_retPartDisabled; + ret = SPI_STATUS_SUCCESS; + break; + + case SPICC26X2DMA_CMD_SET_CSN_PIN: + pinId = ((*(PIN_Id *) arg)); + + /* Configure CSN pin and remap PIN_ID to new CSN pin specified by + arg */ + if (object->mode == SPI_SLAVE) { + pinConfig = PIN_INPUT_EN | PIN_PULLUP | pinId; + } + else { + pinConfig = PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH | PIN_PUSHPULL | + PIN_INPUT_DIS | PIN_DRVSTR_MED | pinId; + } + + if (pinId != PIN_UNASSIGNED) { + /* Attempt to add the new pin */ + if (PIN_add(object->pinHandle, pinConfig) == PIN_SUCCESS) { + /* Configure pin mux */ + PINCC26XX_setMux(object->pinHandle, + pinId, + (hwAttrs->baseAddr == SSI0_BASE ? + IOC_PORT_MCU_SSI0_FSS : + IOC_PORT_MCU_SSI1_FSS)); + + /* Remove old pin and revert to default setting + * specified in the board file */ + PIN_remove(object->pinHandle, object->csnPin); + + /* Keep track of current CSN pin */ + object->csnPin = pinId; + + /* Set return value to indicate success */ + ret = SPI_STATUS_SUCCESS; + } + } + else { + /* We want to use software ctrl CSN. Hence, undo any prior + * hardware CSN pin muxing. Remove old pin and revert to default + * setting specified in the board file (implicitly sets IO + * muxing to GPIO mode) */ + PIN_remove(object->pinHandle, object->csnPin); + + /* Keep track of current CSN pin */ + object->csnPin = pinId; + + /* Set return value to indicate success */ + ret = SPI_STATUS_SUCCESS; + } + break; + case SPICC26X2DMA_CMD_SET_MANUAL: + /* If a transaction is queued, do not modify */ + if (object->headPtr == NULL) { + object->manualStart = true; + ret = SPI_STATUS_SUCCESS; + } + break; + case SPICC26X2DMA_CMD_CLR_MANUAL: + /* If a transaction is queued, do not modify */ + if (object->headPtr == NULL) { + object->manualStart = false; + ret = SPI_STATUS_SUCCESS; + } + break; + case SPICC26X2DMA_CMD_MANUAL_START: + if (object->headPtr != NULL && + object->manualStart) { + SSIDMAEnable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX); + UDMACC26XX_channelEnable(object->udmaHandle, + hwAttrs->rxChannelBitMask | + hwAttrs->txChannelBitMask); + SSIEnable(hwAttrs->baseAddr); + ret = SPI_STATUS_SUCCESS; + } + break; + default: + /* This command is not defined */ + ret = SPI_STATUS_UNDEFINEDCMD; + break; + } + + return (ret); +} + +/* + * ======== SPICC26X2DMA_hwiFxn ======== + */ +static void SPICC26X2DMA_hwiFxn (uintptr_t arg) +{ + uint32_t freeChannel; + uint32_t intStatus; + uintptr_t key; + SPI_Transaction *completedList; + size_t *transferSize; + volatile tDMAControlTable *rxDmaTableEntry; + volatile tDMAControlTable *txDmaTableEntry; + SPICC26X2DMA_Object *object = ((SPI_Handle) arg)->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = ((SPI_Handle) arg)->hwAttrs; + uint8_t i; + + intStatus = SSIIntStatus(hwAttrs->baseAddr, true); + SSIIntClear(hwAttrs->baseAddr, intStatus); + + if (intStatus & SSI_RXOR) { + key = HwiP_disable(); + + if (object->headPtr != NULL) { + /* + * RX overrun during a transfer; mark the current transfer + * as failed & cancel all remaining transfers. + */ + object->headPtr->status = SPI_TRANSFER_FAILED; + + HwiP_restore(key); + + SPICC26X2DMA_transferCancel((SPI_Handle) arg); + } + else { + SSIDisable(hwAttrs->baseAddr); + + /* Disable DMA and clear DMA interrupts */ + SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX); + UDMACC26XX_channelDisable(object->udmaHandle, + hwAttrs->rxChannelBitMask | + hwAttrs->txChannelBitMask); + UDMACC26XX_clearInterrupt(object->udmaHandle, + hwAttrs->rxChannelBitMask | + hwAttrs->txChannelBitMask); + SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR); + SSIIntClear(hwAttrs->baseAddr, SSI_RXOR); + + /* Clear out the FIFO by resetting SPI module and re-initting */ + flushFifos(hwAttrs); + + HwiP_restore(key); + } + } + else { + UDMACC26XX_clearInterrupt(object->udmaHandle, + hwAttrs->rxChannelBitMask | + hwAttrs->txChannelBitMask); + + /* + * We check both channels for completion; this is done in case the + * second channel finishes while we are still configuring the first. + */ + for (i = 0; i < 2; i++) { + if (object->headPtr == NULL){ + /* When i was 0, we finished the last transaction */ + break; + } + + if (object->activeChannel == UDMA_PRI_SELECT) { + transferSize = &object->priTransferSize; + + rxDmaTableEntry = (hwAttrs->baseAddr == SSI0_BASE) ? + &dmaSpi0RxControlTableEntry : + &dmaSpi1RxControlTableEntry; + + txDmaTableEntry = (hwAttrs->baseAddr == SSI0_BASE) ? + &dmaSpi0TxControlTableEntry : + &dmaSpi1TxControlTableEntry; + } + else { + transferSize = &object->altTransferSize; + + rxDmaTableEntry = (hwAttrs->baseAddr == SSI0_BASE) ? + &dmaSpi0RxAltControlTableEntry : + &dmaSpi1RxAltControlTableEntry; + + txDmaTableEntry = (hwAttrs->baseAddr == SSI0_BASE) ? + &dmaSpi0TxAltControlTableEntry : + &dmaSpi1TxAltControlTableEntry; + } + + /* + * The SPI TX FIFO continuously requests the DMA to fill it if there + * is space available. If there are no more frames to put in the + * FIFO we run into a situation where DMA TX will cause undesired + * interrupts. To prevent many undesired interrupts disable DMA_TX + * uf there are no more frames to load into the FIFO & there are no + * pending queued transactions. + */ + if (UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->txChannelBitMask) && + (txDmaTableEntry->ui32Control & UDMA_MODE_M) == UDMA_MODE_STOP && + object->framesQueued == object->headPtr->count && + object->headPtr->nextPtr == NULL){ + SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX); + UDMACC26XX_clearInterrupt(object->udmaHandle, + hwAttrs->txChannelBitMask); + } + + if((rxDmaTableEntry->ui32Control & UDMA_MODE_M) == UDMA_MODE_STOP && + *transferSize != 0) { + key = HwiP_disable(); + + object->framesTransferred += *transferSize; + freeChannel = object->activeChannel; + object->activeChannel = (freeChannel == UDMA_PRI_SELECT) ? + UDMA_ALT_SELECT : UDMA_PRI_SELECT; + + /* + * Set the channel's transfer size to 0; 0 lets + * configNextTransfer() know that there is a free channel. + */ + *transferSize = 0; + + if ((object->framesQueued) < (object->headPtr->count) || + (object->framesTransferred) < (object->headPtr->count)) { + /* + * In this case we need to reconfigure the channel to + * continue transferring frames. configNextTransfer() will + * continue queuing frames for the current transfer or + * start the following transaction if necessary. + */ + configNextTransfer(object, hwAttrs); + + if (object->manualStart && + UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->txChannelBitMask)) { + /* Ping pong flow was broken, restart */ + UDMACC26XX_channelEnable(object->udmaHandle, + hwAttrs->txChannelBitMask); + } + + HwiP_restore(key); + } + else { + /* + * All data has been transferred for the current + * transaction. Set status & move the transaction to + * object->completedList. This is required because + * object->headPtr is moved to the following transaction. + * Also, transaction callbacks are executed in the driver + * SWI which will be posted later. + */ + object->headPtr->status = SPI_TRANSFER_COMPLETED; + + if (object->completedTransfers == NULL) { + /* List is empty; just add the transaction */ + object->completedTransfers = object->headPtr; + completedList = object->completedTransfers; + } + else { + /* Traverse to the last element */ + completedList = object->completedTransfers; + while (completedList->nextPtr != NULL) { + completedList = completedList->nextPtr; + } + + /* Store the completed transaction at end of list */ + completedList->nextPtr = object->headPtr; + + /* + * Make sure we are pointing to the end of the list; + * we need to clear references in completed transfer + * after we move object->headPtr forward. + */ + completedList = completedList->nextPtr; + } + + /* Move the object->headPtr to the next transaction */ + object->headPtr = object->headPtr->nextPtr; + + /* Clear references in completed transfer */ + completedList->nextPtr = NULL; + + /* Update object variables for the following transfer. */ + object->framesQueued = + (object->activeChannel == UDMA_PRI_SELECT) ? + object->priTransferSize : object->altTransferSize; + object->framesTransferred = 0; + + if (object->headPtr != NULL) { + /* Reconfigure channel for following transaction */ + configNextTransfer(object, hwAttrs); + + if (object->manualStart && + UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->txChannelBitMask)) { + /* Ping pong flow was broken, restart */ + UDMACC26XX_channelEnable(object->udmaHandle, + hwAttrs->txChannelBitMask); + } + } + else { + /* No more queued transfers; disable DMA & SPI */ + SSIDMADisable(hwAttrs->baseAddr, + SSI_DMA_TX | + SSI_DMA_RX); + + /* + * For this driver implementation the peripheral is kept + * active until either a FIFO-overrun occurs or + * SPI_transferCancel() is executed. + */ + } + + HwiP_restore(key); + + /* Post driver SWI to execute transaction callbacks */ + SwiP_post(&(object->swi)); + } + } + } + } +} + +/* + * ======== SPICC26X2DMA_init ======== + */ +void SPICC26X2DMA_init(SPI_Handle handle) +{ + ((SPICC26X2DMA_Object *) handle->object)->isOpen = false; +} + +/* + * ======== SPICC26X2DMA_open ======== + */ +SPI_Handle SPICC26X2DMA_open(SPI_Handle handle, SPI_Params *params) +{ + union { + HwiP_Params hwiParams; + SwiP_Params swiParams; + } paramsUnion; + uint32_t key; + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + key = HwiP_disable(); + + /* Failure conditions */ + if (object->isOpen || + params->dataSize > PARAMS_DATASIZE_MAX || + params->dataSize < PARAMS_DATASIZE_MIN) { + HwiP_restore(key); + + return (NULL); + } + object->isOpen = true; + + HwiP_restore(key); + + DebugP_assert((params->dataSize >= 4) && (params->dataSize <= 16)); + + object->bitRate = params->bitRate; + object->dataSize = params->dataSize; + object->mode = params->mode; + object->transferMode = params->transferMode; + object->transferTimeout = params->transferTimeout; + object->returnPartial = SPICC26X2DMA_retPartDisabled; + object->headPtr = NULL; + object->tailPtr = NULL; + object->completedTransfers = NULL; + object->format = frameFormat[params->frameFormat]; + object->txScratchBuf = hwAttrs->defaultTxBufValue; + object->busyBit = (params->mode == SPI_MASTER ? SSI_SR_BSY : SSI_SR_TFE); + object->manualStart = false; + + Power_setDependency(hwAttrs->powerMngrId); + + initHw(handle); + + /* CSN is initialized using hwAttrs, but can be re-configured later */ + object->csnPin = hwAttrs->csnPin; + + /* + * Configure IOs after hardware has been initialized so that IOs aren't + * toggled unnecessary + */ + if (!initIO(handle)) { + /* + * Trying to use SPI driver when some other driver or application + * has already allocated these pins, error! + */ + + Power_releaseDependency(hwAttrs->powerMngrId); + + object->isOpen = false; + + return (NULL); + } + + HwiP_Params_init(¶msUnion.hwiParams); + paramsUnion.hwiParams.arg = (uintptr_t) handle; + paramsUnion.hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), + (int) hwAttrs->intNum, SPICC26X2DMA_hwiFxn, + ¶msUnion.hwiParams); + + SwiP_Params_init(¶msUnion.swiParams); + paramsUnion.swiParams.arg0 = (uintptr_t)handle; + paramsUnion.swiParams.priority = hwAttrs->swiPriority; + SwiP_construct(&(object->swi), + SPICC26X2DMA_swiFxn, + &(paramsUnion.swiParams)); + + object->udmaHandle = UDMACC26XX_open(); + + /* + * Configure PIN driver for CSN callback in optional RETURN_PARTIAL + * slave mode + */ + if (object->mode == SPI_SLAVE) { + PIN_registerIntCb(object->pinHandle, csnCallback); + PIN_setUserArg(object->pinHandle, (uintptr_t) handle); + } + + Power_registerNotify(&object->spiPostObj, + PowerCC26XX_AWAKE_STANDBY, + (Power_NotifyFxn) spiPostNotify, + (uint32_t) handle); + + if (object->transferMode == SPI_MODE_BLOCKING) { + /* + * Create a semaphore to block task execution for the duration of the + * SPI transfer + */ + SemaphoreP_constructBinary(&(object->transferComplete), 0); + object->transferCallbackFxn = blockingTransferCallback; + } + else { + DebugP_assert(params->transferCallbackFxn != NULL); + object->transferCallbackFxn = params->transferCallbackFxn; + } + + return (handle); +} + +/* + * ======== SPICC26X2DMA_swiFxn ======== + */ +static void SPICC26X2DMA_swiFxn(uintptr_t arg0, uintptr_t arg1) { + SPI_Transaction *transaction; + SPICC26X2DMA_Object *object = ((SPI_Handle) arg0)->object; + + while (object->completedTransfers != NULL) { + transaction = object->completedTransfers; + + /* Move object->completedTransfers to the next transaction */ + object->completedTransfers = object->completedTransfers->nextPtr; + + transaction->nextPtr = NULL; + + /* Transaction complete; release power constraints */ + releaseConstraint((uint32_t) transaction->txBuf); + + /* Execute callback function for completed transfer */ + object->transferCallbackFxn((SPI_Handle) arg0, transaction); + } +} + +/* + * ======== SPICC26X2DMA_transfer ======== + */ +bool SPICC26X2DMA_transfer(SPI_Handle handle, SPI_Transaction *transaction) +{ + uint8_t alignMask; + bool buffersAligned; + uintptr_t key; + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (transaction->count == 0) { + return (false); + } + + key = HwiP_disable(); + + /* + * Make sure that the buffers are aligned properly. + * alignMask is used to check if the RX/TX buffers addresses + * are aligned to the frameSize. + */ + alignMask = (object->dataSize < 9) ? 0x0 : 0x01; + buffersAligned = ((((uint32_t) transaction->rxBuf & alignMask) == 0) && + (((uint32_t) transaction->txBuf & alignMask) == 0)); + + if (!buffersAligned || + (object->headPtr && object->transferMode == SPI_MODE_BLOCKING)) { + transaction->status = SPI_TRANSFER_FAILED; + + HwiP_restore(key); + + return (false); + } + else { + if (object->headPtr) { + object->tailPtr->nextPtr = transaction; + object->tailPtr = transaction; + object->tailPtr->status = SPI_TRANSFER_QUEUED; + } + else { + object->headPtr = transaction; + object->tailPtr = transaction; + + object->framesQueued = 0; + object->framesTransferred = 0; + object->priTransferSize = 0; + object->altTransferSize = 0; + object->tailPtr->status = + (object->returnPartial != SPICC26X2DMA_retPartDisabled) ? + SPI_TRANSFER_PEND_CSN_ASSERT : + SPI_TRANSFER_STARTED; + } + + object->tailPtr->nextPtr = NULL; + } + + /* In slave mode, optionally enable callback on CSN de-assert */ + if (object->returnPartial == SPICC26X2DMA_retPartEnabledIntNotSet) { + object->returnPartial = SPICC26X2DMA_retPartEnabledIntSet; + PIN_setInterrupt(object->pinHandle, object->csnPin | PIN_IRQ_BOTHEDGES); + } + + /* Set constraints to guarantee transaction */ + setConstraint((uint32_t)transaction->txBuf); + + /* + * Polling transfer if BLOCKING mode & transaction->count < threshold + * Slaves not allowed to use polling unless timeout is disabled + */ + if (object->transferMode == SPI_MODE_BLOCKING && + transaction->count < hwAttrs->minDmaTransferSize && + (object->mode == SPI_MASTER || + object->transferTimeout == SPI_WAIT_FOREVER)) { + HwiP_restore(key); + + spiPollingTransfer(object, hwAttrs, transaction); + + /* Release constraint since transaction is done */ + releaseConstraint((uint32_t) transaction->txBuf); + + /* Transaction completed; set status & mark SPI ready */ + object->headPtr->status = SPI_TRANSFER_COMPLETED; + object->headPtr = NULL; + object->tailPtr = NULL; + } + else { + /* + * Perform a DMA backed SPI transfer; we need exclusive access while + * priming the transfer to prevent race conditions with + * SPICC26X2DMA_transferCancel(). + */ + primeTransfer(object, hwAttrs); + + /* Enable the RX overrun interrupt in the SSI module */ + SSIIntEnable(hwAttrs->baseAddr, SSI_RXOR); + + HwiP_restore(key); + + if (object->transferMode == SPI_MODE_BLOCKING) { + if (SemaphoreP_OK != SemaphoreP_pend(&(object->transferComplete), + object->transferTimeout)) { + /* Timeout occurred; cancel the transfer */ + object->headPtr->status = SPI_TRANSFER_FAILED; + SPICC26X2DMA_transferCancel(handle); + + /* + * SPICC26X2DMA_transferCancel() performs callback which posts + * transferComplete semaphore. This call consumes this extra + * post. + */ + SemaphoreP_pend(&(object->transferComplete), + SemaphoreP_NO_WAIT); + + return (false); + } + } + } + return (true); +} + +/* + * ======== SPICC26X2DMA_transferCancel ======== + */ +void SPICC26X2DMA_transferCancel(SPI_Handle handle) { + uintptr_t key; + uint32_t temp; + SPI_Transaction *tempPtr; + volatile tDMAControlTable *rxDmaTableEntry; + volatile tDMAControlTable *rxDmaTableAltEntry; + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* + * Acquire exclusive access to the driver. Required to prevent race + * conditions if preempted by code trying to configure another transfer. + */ + key = HwiP_disable(); + + if (object->headPtr == NULL) { + HwiP_restore(key); + + return; + } + + /* + * There are 2 use cases in which to call transferCancel(): + * 1. The driver is in CALLBACK mode. + * 2. The driver is in BLOCKING mode & there has been a transfer timeout. + */ + if (object->transferMode != SPI_MODE_BLOCKING || + object->headPtr->status == SPI_TRANSFER_FAILED || + object->headPtr->status == SPI_TRANSFER_CSN_DEASSERT) { + + /* Prevent interrupt while canceling the transfer */ + HwiP_disableInterrupt(hwAttrs->intNum); + + /* + * Disable the TX DMA channel first to stop feeding more frames to + * the FIFO. Next, wait until the TX FIFO is empty (all frames in + * FIFO have been sent). RX DMA channel is disabled later to allow + * the DMA to move all frames already in FIFO to memory. + */ + UDMACC26XX_channelDisable(object->udmaHandle, + hwAttrs->txChannelBitMask); + + if (object->mode == SPI_MASTER) { + /* + * Wait until the TX FIFO is empty; this is to make sure the + * chip select is deasserted before disabling the SPI. + */ + while (SSIBusy(hwAttrs->baseAddr)) {} + } + + SSIDisable(hwAttrs->baseAddr); + + /* Now disable the RX, DMA & interrupts */ + UDMACC26XX_channelDisable(object->udmaHandle, + hwAttrs->rxChannelBitMask); + SSIDMADisable(hwAttrs->baseAddr, + SSI_DMA_TX | SSI_DMA_RX); + UDMACC26XX_clearInterrupt(object->udmaHandle, + hwAttrs->rxChannelBitMask | + hwAttrs->txChannelBitMask); + SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR); + SSIIntClear(hwAttrs->baseAddr, SSI_RXOR); + + /* + * Update transaction->count with the amount of frames which have + * been transferred. + */ + if (hwAttrs->baseAddr == SSI0_BASE) { + rxDmaTableEntry = &dmaSpi0RxControlTableEntry; + rxDmaTableAltEntry = &dmaSpi0RxAltControlTableEntry; + } + else { + rxDmaTableEntry = &dmaSpi1RxControlTableEntry; + rxDmaTableAltEntry = &dmaSpi1RxAltControlTableEntry; + } + + object->headPtr->count = object->framesTransferred; + if (object->priTransferSize) { + temp = UDMACC26XX_GET_TRANSFER_SIZE(rxDmaTableEntry->ui32Control); + + if (temp <= object->priTransferSize) { + object->headPtr->count += (object->priTransferSize - temp); + } + } + + if (object->altTransferSize) { + temp = + UDMACC26XX_GET_TRANSFER_SIZE(rxDmaTableAltEntry->ui32Control); + + if (temp <= object->altTransferSize) { + object->headPtr->count += (object->altTransferSize - temp); + } + } + + /* + * Disables peripheral, clears all registers & reinitializes it to + * parameters used in SPI_open() + */ + initHw(handle); + + HwiP_clearInterrupt(hwAttrs->intNum); + HwiP_enableInterrupt(hwAttrs->intNum); + + /* + * Go through all queued transfers; set status CANCELED (if we did + * not cancel due to timeout). The object->headPtr->count is + * stored/restored temporarily. + */ + temp = object->headPtr->count; + tempPtr = object->headPtr; + + while (tempPtr != NULL) { + if (tempPtr->status != SPI_TRANSFER_FAILED && + tempPtr->status != SPI_TRANSFER_CSN_DEASSERT) { + tempPtr->status = SPI_TRANSFER_CANCELED; + } + + tempPtr->count = 0; + tempPtr = tempPtr->nextPtr; + } + object->headPtr->count = temp; + + /* Add all cancelled transactions to object->completedTransfers */ + tempPtr = object->completedTransfers; + if (tempPtr == NULL) { + /* Empty list; just add all of the cancelled transactions */ + object->completedTransfers = object->headPtr; + } + else { + /* Move through the list until we reach the last element */ + while (tempPtr->nextPtr != NULL) { + tempPtr = tempPtr->nextPtr; + } + + /* Add all of the cancelled transactions */ + tempPtr->nextPtr = object->headPtr; + } + + /* Clear all driver object variables*/ + object->headPtr = NULL; + object->tailPtr = NULL; + object->framesQueued = 0; + object->framesTransferred = 0; + object->priTransferSize = 0; + object->altTransferSize = 0; + + HwiP_restore(key); + + /* + * All transactions have been marked as cancelled & added to + * object->completedTransfers. Post the driver SWI to execute + * callback functions. + */ + SwiP_post(&(object->swi)); + + /* Must return here; do not call HwiP_restore() twice */ + return; + } + + HwiP_restore(key); +} + +/* + * ======== blockingTransferCallback ======== + */ +static void blockingTransferCallback(SPI_Handle handle, SPI_Transaction *msg) +{ + SPICC26X2DMA_Object *object = handle->object; + + SemaphoreP_post(&(object->transferComplete)); +} + +/* + * ======== configNextTransfer ======== + * This function must be executed with interrupts disabled. + */ +static void configNextTransfer(SPICC26X2DMA_Object *object, + SPICC26X2DMA_HWAttrs const *hwAttrs) +{ + size_t framesQueued; + uint32_t transferAmt; + SPI_Transaction *transaction; + volatile tDMAControlTable *rxDmaTableEntry; + volatile tDMAControlTable *txDmaTableEntry; + uint8_t optionsIndex; + + /* + * The DMA options vary according to data frame size; options for 8-bit + * data (or smaller) are in index 0. Options for larger frame sizes are + * in index 1. + * + * optionsIndex was originally calculated by: + * optionsIndex = (object->dataSize < 9) ? 0x00 : 0x01; + * + * However, the IAR compiler generated incorrect assembly: + * + * configNextTransfer: + * 0x5140: 0xe92d 0x41fc PUSH.W {R2-R8, LR} + * optionsIndex = (object->dataSize < 9) ? 0x00 : 0x01; + * 0x5144: 0xf100 0x0594 ADD.W R5, R0, #148 ; 0x94 + * 0x5148: 0x6aaa LDR R2, [R5, #0x28] + * 0x514a: 0x2a08 CMP R2, #8 + * 0x514c: 0x419b SBCS R3, R3, R3 + * 0x514e: 0x43db MVNS R3, R3 + * 0x5150: 0x0fdb LSRS R3, R3, #31 + * + * To work around this issue is calculated as follows: + */ + optionsIndex = ((int32_t)(object->dataSize - 0x08) > 0) ? 0x01 : 0x00; + + /* + * object->framesQueued keeps track of how many frames (of the current + * transaction) have been configured for DMA transfer. If + * object->framesQueued == transaction->count; all frames have been queued + * & we should configure the free DMA channel to send the next transaction. + * When the current transaction has completed; object->framesQueued + * will be updated (in the ISR) to reflect the amount of frames queued + * of the following transaction. + */ + transaction = object->headPtr; + if (object->framesQueued < transaction->count) { + framesQueued = object->framesQueued; + } + else { + transaction = object->headPtr->nextPtr; + if (transaction == NULL) { + /* There are no queued transactions */ + return; + } + + framesQueued = 0; + transaction->status = SPI_TRANSFER_STARTED; + } + + /* + * The DMA has a max transfer amount of 1024. If the transaction is + * greater; we must transfer it in chunks. framesQueued keeps track of + * how much data has been queued for transfer. + */ + if ((transaction->count - framesQueued) > MAX_DMA_TRANSFER_AMOUNT) { + transferAmt = MAX_DMA_TRANSFER_AMOUNT; + } + else { + transferAmt = transaction->count - framesQueued; + } + + /* Determine free channel & mark it as used by setting transfer size */ + if (object->priTransferSize == 0) { + object->priTransferSize = transferAmt; + + if (hwAttrs->baseAddr == SSI0_BASE) { + rxDmaTableEntry = &dmaSpi0RxControlTableEntry; + txDmaTableEntry = &dmaSpi0TxControlTableEntry; + } + else { + rxDmaTableEntry = &dmaSpi1RxControlTableEntry; + txDmaTableEntry = &dmaSpi1TxControlTableEntry; + } + } + else { + object->altTransferSize = transferAmt; + + if (hwAttrs->baseAddr == SSI0_BASE) { + rxDmaTableEntry = &dmaSpi0RxAltControlTableEntry; + txDmaTableEntry = &dmaSpi0TxAltControlTableEntry; + } + else { + rxDmaTableEntry = &dmaSpi1RxAltControlTableEntry; + txDmaTableEntry = &dmaSpi1TxAltControlTableEntry; + } + } + + /* Setup the TX transfer buffers & characteristics */ + if (transaction->txBuf) { + txDmaTableEntry->ui32Control = dmaTxConfig[optionsIndex]; + + /* + * Add an offset for the amount of data transfered. The offset is + * calculated by: object->framesQueued * (optionsIndex + 1). This + * accounts for 8 or 16-bit sized transfers. + */ + txDmaTableEntry->pvSrcEndAddr = + (void *)((uint32_t) transaction->txBuf + + (uint32_t) (framesQueued * (optionsIndex + 1)) + + (transferAmt << optionsIndex) - 1); + } + else { + txDmaTableEntry->ui32Control = dmaNullConfig[optionsIndex]; + txDmaTableEntry->pvSrcEndAddr = (void *) &(object->txScratchBuf); + } + txDmaTableEntry->pvDstEndAddr = (void *) (hwAttrs->baseAddr + SSI_O_DR); + txDmaTableEntry->ui32Control |= + UDMACC26XX_SET_TRANSFER_SIZE((uint16_t) transferAmt); + + /* Setup the RX transfer buffers & characteristics */ + if (transaction->rxBuf) { + rxDmaTableEntry->ui32Control = dmaRxConfig[optionsIndex]; + + /* + * Add an offset for the amount of data transfered. The offset is + * calculated by: object->framesQueued * (optionsIndex + 1). This + * accounts for 8 or 16-bit sized transfers. + */ + + rxDmaTableEntry->pvDstEndAddr = + (void *) ((uint32_t) transaction->rxBuf + + (uint32_t) (framesQueued * (optionsIndex+ 1)) + + (transferAmt << optionsIndex) - 1); + } + else { + rxDmaTableEntry->ui32Control = dmaNullConfig[optionsIndex]; + rxDmaTableEntry->pvDstEndAddr = &object->rxScratchBuf; + } + rxDmaTableEntry->pvSrcEndAddr = (void *) (hwAttrs->baseAddr + SSI_O_DR); + rxDmaTableEntry->ui32Control |= + UDMACC26XX_SET_TRANSFER_SIZE((uint16_t) transferAmt); + + if (transaction == object->headPtr) { + /* + * Only update object->framesQueued if we are configuring a DMA + * channel for the current transaction. + */ + object->framesQueued += transferAmt; + } + + if (!object->manualStart) { + /* Enable DMA to generate interrupt on SPI peripheral */ + SSIDMAEnable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX); + UDMACC26XX_channelEnable(object->udmaHandle, + hwAttrs->rxChannelBitMask | + hwAttrs->txChannelBitMask); + } + + return; +} + +/* + * ======== csnCallback ======== + * Slave mode optional callback function for when the CSN is asserted & + * deasserted. + */ +static void csnCallback(PIN_Handle handle, PIN_Id pinId) +{ + uintptr_t key; + SPICC26X2DMA_Object *object; + SPI_Handle spiHandle; + + spiHandle = (SPI_Handle) PIN_getUserArg(handle); + object = spiHandle->object; + + /* Transfer started if CSN low */ + if (!PIN_getInputValue(object->csnPin)) { + key = HwiP_disable(); + + if (object->headPtr != NULL) { + /* Indicate transaction started */ + object->headPtr->status = SPI_TRANSFER_STARTED; + } + else { + /* Disable all interrupts */ + PIN_setInterrupt(handle, object->csnPin); + object->returnPartial = SPICC26X2DMA_retPartEnabledIntNotSet; + } + + HwiP_restore(key); + } + + /* Cancel transfer if CSN high */ + if (PIN_getInputValue(object->csnPin)) { + key = HwiP_disable(); + + /* Disable all interrupts */ + PIN_setInterrupt(handle, object->csnPin); + object->returnPartial = SPICC26X2DMA_retPartEnabledIntNotSet; + + /* Indicate why the transaction completed */ + if (object->headPtr != NULL) { + object->headPtr->status = SPI_TRANSFER_CSN_DEASSERT; + } + + HwiP_restore(key); + + /* Cancel the current transaction */ + SPICC26X2DMA_transferCancel(spiHandle); + } +} + +/* + * ======== flushFifos ======== + */ +static void flushFifos(SPICC26X2DMA_HWAttrs const *hwAttrs) +{ + /* Flush RX FIFO */ + while(HWREG(hwAttrs->baseAddr + SSI_O_SR) & SSI_RX_NOT_EMPTY) { + /* Read element from RX FIFO and discard */ + HWREG(hwAttrs->baseAddr + SSI_O_DR); + } + + /* Enable TESTFIFO mode */ + HWREG(hwAttrs->baseAddr + SSI_O_TCR) = SSI_TCR_TESTFIFO_ENABLE; + + /* Flush TX FIFO */ + while(!(HWREG(hwAttrs->baseAddr + SSI_O_SR) & SSI_TX_EMPTY)) { + /* Read element from TX FIFO and discard */ + HWREG(hwAttrs->baseAddr + SSI_O_TDR); + } + + /* Disable TESTFIFO mode */ + HWREG(hwAttrs->baseAddr + SSI_O_TCR) = SSI_TCR_TESTFIFO_DISABLE; +} + +/* + * ======== getDmaChannelNumber ======== + */ +static inline uint32_t getDmaChannelNumber(uint32_t x) { +#if defined(__TI_COMPILER_VERSION__) + return ((uint32_t) __clz(__rbit(x))); +#elif defined(__GNUC__) + return ((uint32_t) __builtin_ctz(x)); +#elif defined(__IAR_SYSTEMS_ICC__) + return ((uint32_t) __CLZ(__RBIT(x))); +#else + #error "Unsupported compiler" +#endif +} + +/* + * ======== initHw ======== + */ +static void initHw(SPI_Handle handle) { + ClockP_FreqHz freq; + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + flushFifos(hwAttrs); + + /* Disable SSI operation */ + SSIDisable(hwAttrs->baseAddr); + + /* Disable SPI module interrupts */ + SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR | SSI_RXFF | SSI_RXTO | SSI_TXFF); + SSIIntClear(hwAttrs->baseAddr, SSI_RXOR | SSI_RXTO); + + /* Set the SPI configuration */ + ClockP_getCpuFreq(&freq); + SSIConfigSetExpClk(hwAttrs->baseAddr, + freq.lo, + object->format, + object->mode, + object->bitRate, + object->dataSize); +} + +/* +* ======== initIO ======== +* This functions initializes the SPI IOs. +* +* @pre Function assumes that the SPI handle is pointing to a hardware +* module which has already been opened. +*/ +static bool initIO(SPI_Handle handle) { + uint32_t i = 0; + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + PIN_Config spiPinTable[5]; + + /* Build local list of pins, allocate through PIN driver and map HW ports */ + if (object->mode == SPI_SLAVE) { + spiPinTable[i++] = hwAttrs->mosiPin | PIN_INPUT_EN; + spiPinTable[i++] = hwAttrs->misoPin | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | + PIN_PUSHPULL | PIN_INPUT_DIS | PIN_DRVSTR_MED; + spiPinTable[i++] = hwAttrs->clkPin | PIN_INPUT_EN; + spiPinTable[i++] = object->csnPin | PIN_INPUT_EN | PIN_PULLUP; + } + else { + spiPinTable[i++] = hwAttrs->mosiPin | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | + PIN_PUSHPULL | PIN_INPUT_DIS | PIN_DRVSTR_MED; + spiPinTable[i++] = hwAttrs->misoPin | PIN_INPUT_EN | PIN_PULLDOWN; + + /* Output low signal on SCLK until SPI module drives signal if clock + * polarity is configured to '0'. Output high signal on SCLK until SPI + * module drives signal if clock polarity is configured to '1' */ + if (object->format == SSI_FRF_MOTO_MODE_0 || + object->format == SSI_FRF_MOTO_MODE_1) { + spiPinTable[i++] = hwAttrs->clkPin | PIN_GPIO_OUTPUT_EN | + PIN_GPIO_LOW | PIN_PUSHPULL | PIN_INPUT_DIS | + PIN_DRVSTR_MED; + } + else { + spiPinTable[i++] = hwAttrs->clkPin | PIN_GPIO_OUTPUT_EN | + PIN_GPIO_HIGH | PIN_PUSHPULL | PIN_INPUT_DIS | + PIN_DRVSTR_MED; + } + + /* If CSN isn't SW controlled, drive it high until SPI module drives + * signal to avoid glitches */ + if(object->csnPin != PIN_UNASSIGNED) { + spiPinTable[i++] = object->csnPin | PIN_GPIO_OUTPUT_EN | + PIN_GPIO_HIGH | PIN_PUSHPULL | PIN_INPUT_DIS | + PIN_DRVSTR_MED; + } + } + spiPinTable[i++] = PIN_TERMINATE; + + /* Open and assign pins through pin driver */ + if (!(object->pinHandle = PIN_open(&(object->pinState), spiPinTable))) { + return false; + } + + /* Set IO muxing for the SPI pins */ + if (object->mode == SSI_MODE_SLAVE) { + /* Configure IOs for slave mode */ + PINCC26XX_setMux(object->pinHandle, + hwAttrs->mosiPin, + (hwAttrs->baseAddr == SSI0_BASE ? + IOC_PORT_MCU_SSI0_RX : IOC_PORT_MCU_SSI1_RX)); + PINCC26XX_setMux(object->pinHandle, + hwAttrs->misoPin, + (hwAttrs->baseAddr == SSI0_BASE ? + IOC_PORT_MCU_SSI0_TX : IOC_PORT_MCU_SSI1_TX)); + PINCC26XX_setMux(object->pinHandle, + hwAttrs->clkPin, + (hwAttrs->baseAddr == SSI0_BASE ? + IOC_PORT_MCU_SSI0_CLK : IOC_PORT_MCU_SSI1_CLK)); + PINCC26XX_setMux(object->pinHandle, + object->csnPin, + (hwAttrs->baseAddr == SSI0_BASE ? + IOC_PORT_MCU_SSI0_FSS : IOC_PORT_MCU_SSI1_FSS)); + } + else { + /* Configure IOs for master mode */ + PINCC26XX_setMux(object->pinHandle, + hwAttrs->mosiPin, + (hwAttrs->baseAddr == SSI0_BASE ? + IOC_PORT_MCU_SSI0_TX : IOC_PORT_MCU_SSI1_TX)); + PINCC26XX_setMux(object->pinHandle, + hwAttrs->misoPin, + (hwAttrs->baseAddr == SSI0_BASE ? + IOC_PORT_MCU_SSI0_RX : IOC_PORT_MCU_SSI1_RX)); + PINCC26XX_setMux(object->pinHandle, + hwAttrs->clkPin, + (hwAttrs->baseAddr == SSI0_BASE ? + IOC_PORT_MCU_SSI0_CLK : IOC_PORT_MCU_SSI1_CLK)); + if(object->csnPin != PIN_UNASSIGNED) { + PINCC26XX_setMux(object->pinHandle, + object->csnPin, + (hwAttrs->baseAddr == SSI0_BASE ? + IOC_PORT_MCU_SSI0_FSS : IOC_PORT_MCU_SSI1_FSS)); + } + } + + return (true); +} + +/* + * ======== primeTransfer ======== + * Function must be executed with interrupts disabled. + */ +static inline void primeTransfer(SPICC26X2DMA_Object *object, + SPICC26X2DMA_HWAttrs const *hwAttrs) +{ + if (object->priTransferSize != 0 && object->altTransferSize != 0) { + /* + * Both primary & alternate channels are configured for a transfer. + * In this case no work is required; the Hwi will configure channels + * as transfers continue & complete. + */ + } + else if (object->priTransferSize == 0 && object->altTransferSize == 0) { + /* + * Primary & alternate channels are disabled; no active transfer, + * configure a new transfer. + * + * DMA based transfers use the DMA in ping-pong mode. If the transfer is + * larger than what the primary channel can handle; alternate channel is + * configured to continue where the primary channel left off. Channels + * are continuously reconfigured until the transfer is completed. + * + * We disable the alternate channel initially. This however causes an + * undesired interrupt to be triggered; so we need to + * disable/clear/re-enable the interrupt. + */ + HwiP_disableInterrupt(hwAttrs->intNum); + + /* Set the primary DMA structure as active */ + UDMACC26XX_disableAttribute(object->udmaHandle, + getDmaChannelNumber(hwAttrs->rxChannelBitMask), + UDMA_ATTR_ALTSELECT); + UDMACC26XX_disableAttribute(object->udmaHandle, + getDmaChannelNumber(hwAttrs->txChannelBitMask), + UDMA_ATTR_ALTSELECT); + + HwiP_clearInterrupt(hwAttrs->intNum); + HwiP_enableInterrupt(hwAttrs->intNum); + + /* Configure RX & TX DMA transfers */ + configNextTransfer(object, hwAttrs); + object->activeChannel = UDMA_PRI_SELECT; + if (object->headPtr->count > MAX_DMA_TRANSFER_AMOUNT) { + configNextTransfer(object, hwAttrs); + } + + /* Enable DMA to generate interrupt on SPI peripheral */ + if (!object->manualStart) { + SSIEnable(hwAttrs->baseAddr); + } + } + else { + /* One of the channels is active; configure the other channel */ + configNextTransfer(object, hwAttrs); + } +} + +/* + * ======== releaseConstraint ======== + */ +static inline void releaseConstraint(uint32_t txBufAddr) +{ + /* Release need flash if buffer was in flash. */ + if (((txBufAddr & 0xF0000000) == 0x0) && (txBufAddr)) { + Power_releaseConstraint(PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING); + Power_releaseConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + } + + /* Release standby constraint since operation is done. */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/* + * ======== setConstraint ======== + */ +static inline void setConstraint(uint32_t txBufAddr) +{ + /* + * Ensure flash is available if TX buffer is in flash. + * Flash starts with 0x0.. + */ + if (((txBufAddr & 0xF0000000) == 0x0) && (txBufAddr)) { + Power_setConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + Power_setConstraint(PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING); + } + + /* Set constraints to guarantee operation */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/* + * ======== spiPollingTransfer ======== + */ +static inline void spiPollingTransfer(SPICC26X2DMA_Object *object, + SPICC26X2DMA_HWAttrs const *hwAttrs, + SPI_Transaction *transaction) +{ + uint8_t increment; + uint32_t dummyBuffer; + size_t transferCount; + void *rxBuf; + void *txBuf; + + if (transaction->rxBuf) { + rxBuf = transaction->rxBuf; + } + else { + rxBuf = &(object->rxScratchBuf); + } + + if (transaction->txBuf) { + txBuf = transaction->txBuf; + } + else { + txBuf = (void *) &(object->txScratchBuf); + } + + increment = (object->dataSize < 9) ? sizeof(uint8_t) : sizeof(uint16_t); + transferCount = transaction->count; + + SSIEnable(hwAttrs->baseAddr); + + while (transferCount--) { + if (object->dataSize < 9) { + SSIDataPut(hwAttrs->baseAddr, *((uint8_t *) txBuf)); + SSIDataGet(hwAttrs->baseAddr, &dummyBuffer); + *((uint8_t *) rxBuf) = (uint8_t) dummyBuffer; + } + else { + SSIDataPut(hwAttrs->baseAddr, *((uint16_t *) txBuf)); + SSIDataGet(hwAttrs->baseAddr, &dummyBuffer); + *((uint16_t *) rxBuf) = (uint16_t) dummyBuffer; + } + + /* Only increment source & destination if buffers were provided */ + if (transaction->rxBuf) { + rxBuf = (void *) (((uint32_t) rxBuf) + increment); + } + if (transaction->txBuf) { + txBuf = (void *) (((uint32_t) txBuf) + increment); + } + } + + while (spiBusy(object, hwAttrs)) {} + + /* + * For this driver implementation the peripheral is kept active until + * either a FIFO-overrun occurs or SPI_transferCancel() is executed. + * + * SSIDisable(hwAttrs->baseAddr); + */ +} + +/* + * ======== spiPostNotify ======== + */ +static int spiPostNotify(unsigned int eventType, uintptr_t eventArg, + uintptr_t clientArg) +{ + initHw((SPI_Handle) clientArg); + + return (Power_NOTIFYDONE); +} + +/* + * ======== spiBusy ======== + * HW is busy when in master mode and BSY bit is set, or when in slave mode + * and TFE bit is not set. + */ +static inline bool spiBusy(SPICC26X2DMA_Object *object, + SPICC26X2DMA_HWAttrs const *hwAttrs) +{ + bool registerBit = (bool)(HWREG(hwAttrs->baseAddr + SSI_O_SR) & (object->busyBit)); + if (object->busyBit == SSI_SR_BSY){ + return(registerBit); + } + else + { + return(!registerBit); + } +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26X2DMA.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26X2DMA.h new file mode 100644 index 0000000..c0c1618 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26X2DMA.h @@ -0,0 +1,988 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file SPICC26X2DMA.h + * + * @brief SPI driver implementation for a CC26XX SPI controller using + * the UDMA controller. + * + * # Driver include # + * The SPI header file should be included in an application as follows: + * @code + * #include + * #include + * #include + * @endcode + * + * Refer to @ref SPI.h for a complete description of APIs. + * + * Note that the user also needs to include the UDMACC26XX.h driver since the + * SPI uses uDMA in order to improve throughput. + * + * # Overview # + * The general SPI API should be used in application code, i.e. SPI_open() + * should be used instead of SPICC26X2DMA_open(). The board file will define the device + * specific config, and casting in the general API will ensure that the correct + * device specific functions are called. + * This is also reflected in the example code in [Use Cases](@ref USE_CASES_SPI_X2). + * + * # General Behavior # + * Before using SPI on CC26XX: + * - The SPI driver is initialized by calling SPI_init(). + * - The SPI HW is configured and flags system dependencies (e.g. IOs, + * power, etc.) by calling SPI_open(). + * - The SPI driver makes use of DMA in order to optimize throughput. + * This is handled directly by the SPI driver, so the application should never + * to make any calls directly to the UDMACC26XX.h driver. + * - This implementation supports queueing multiple transactions in callback + * mode. See the @ref USE_CASE_QUEUE "queueing example." + * - When queueing multiple transactions that should transfer one after the + * other, it is recommended to use the driver in 'manual start' mode by using + * the #SPICC26X2DMA_CMD_SET_MANUAL command. In this mode, the driver will + * not start any queued transfers until SPI_control() is called with the + * #SPICC26X2DMA_CMD_MANUAL_START command. This mode is off by default and + * can be disabled by using command #SPICC26X2DMA_CMD_CLR_MANUAL. See the + * @ref USE_CASE_MANUAL_START "Manual Start Example". + * + * The following is true for slave operation: + * - RX overrun IRQ, SPI and UDMA modules are enabled by calling SPI_transfer(). + * - All received bytes are ignored after SPI_open() is called, until + * the first SPI_transfer(). + * - If an RX overrun occur or if SPI_transferCancel() is called, RX overrun IRQ, SPI and UDMA + * modules are disabled, TX and RX FIFOs are flushed and all bytes are ignored. + * - After a successful transfer, RX overrun IRQ and SPI module remains enabled and UDMA module is disabled. + * SPI_transfer() must be called again before RX FIFO goes full in order to + * avoid overflow. If the TX buffer is underflowed, zeros will be output. + * It is safe to call another SPI_transfer() from the transfer callback, + * see [Continuous Slave Transfer] (@ref USE_CASE_CST_X2) use case below. + * - The SPI driver supports partial return, that can be used if the + * transfer size is unknown. If #SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE is + * passed to SPI_control(), the transfer will end when chip select is + * deasserted. The #SPI_Transaction.status and the #SPI_Transaction.count + * will be updated to indicate whether the transfer ended due to a chip + * select deassertion and how many bytes were transferred. See + * [Slave Mode With Return Partial] (@ref USE_CASE_RP_X2) use case below. + * - When queueing several transactions if the first is a 'short' + * transaction (8 or fewer frames), it is required to use + * @ref USE_CASE_MANUAL_START "Manual Start mode." + * + * @warning The SPI modules on the CC13x0, CC26x0, and CC26x0R2 devices have a + * bug which may result in TX data being lost when operating in SPI slave + * mode. Please refer to the device errata sheet for full details. The SPI + * protocol should therefore include a data integrity check, such as + * appending a CRC to the payload to ensure all the data was transmitted + * correctly by the SPI slave. + * + * The following apply for master operation: + * - SPI and UDMA modules are enabled by calling SPI_transfer(). + * - If the SPI_transfer() succeeds, SPI module is enabled and UDMA module is disabled. + * - If SPI_transferCancel() is called, SPI and UDMA modules are disabled and + * TX and RX FIFOs are flushed. + * . + * After SPI operation has ended: + * - Release system dependencies for SPI by calling SPI_close(). + * . + * The callback function is always called in a SWI context. + * + * @warning The application should avoid transmitting data stored in flash via SPI if the application + * might switch to the XOSC_HF, the high frequency external oscillator, during this transfer. + * + * # Error handling # + * If an RX overrun occurs during slave operation: + * - If a transfer is ongoing, all bytes received up until the error occurs will be returned, with the + * error signaled in the #SPI_Transaction.status field. RX overrun IRQ, SPI and UDMA modules are then disabled, + * TX and RX FIFOs are flushed and all bytes will be ignored until a new transfer is issued. + * - If a transfer is not ongoing, RX overrun IRQ, SPI and UDMA modules are disabled, + * TX and RX FIFOs are flushed and all bytes will be ignored until a new transfer is issued. + * + * # Timeout # + * Timeout can occur in #SPI_MODE_BLOCKING, there's no timeout in #SPI_MODE_CALLBACK. + * When in #SPI_MODE_CALLBACK, the transfer must be cancelled by calling SPI_transferCancel().@n + * If a timeout happens in either #SPI_SLAVE or #SPI_MASTER mode, + * the receive buffer will contain the bytes received up until the timeout occurred. + * The SPI transaction status will be set to #SPI_TRANSFER_FAILED. + * The SPI transaction count will be set to the number of bytes sent/received before timeout. + * The remaining bytes will be flushed from the TX FIFO so that the subsequent transfer + * can be executed correctly. Note that specifying a timeout prevents the + * driver from performing a polling transfer when in slave mode. + * + * # Power Management # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * The SPICC26X2DMA.h driver is setting a power constraint during transfers to keep + * the device out of standby. When the transfer has finished, the power + * constraint is released. + * The following statements are valid: + * - After SPI_open(): the device is still allowed to enter standby. + * - In slave mode: + * - During SPI_transfer(): the device cannot enter standby, only idle. + * - After an RX overflow: device is allowed to enter standby. + * - After a successful SPI_transfer(): the device is allowed + * to enter standby, but SPI module remains enabled. + * - _Note_: In slave mode, the device might enter standby while a byte is being + * transferred if SPI_transfer() is not called again after a successful + * transfer. This could result in corrupt data being transferred. + * - Application thread should typically either issue another transfer after + * SPI_transfer() completes successfully, or call + * SPI_transferCancel() to disable the SPI module and thus assuring that no data + * is received while entering standby. + * . + * - In master mode: + * - During SPI_transfer(): the device cannot enter standby, only idle. + * - After SPI_transfer() succeeds: the device can enter standby. + * - If SPI_transferCancel() is called: the device can enter standby. + * + * @note The external hardware connected to the SPI might have some pull configured on the + * SPI lines. When the SPI is inactive, this might cause leakage on the IO and the + * current consumption to increase. The application must configure a pull configuration + * that aligns with the external hardware. + * See [Ensure low power during inactive periods] (@ref USE_CASE_LPWR_X2) for code example. + * + * # SPI details # + * ## Chip Select # + * This SPI controller supports a hardware chip select pin. Refer to the + * user manual on how this hardware chip select pin behaves in regards + * to the SPI frame format. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Chip select typeSPI_MASTER modeSPI_SLAVE mode
Hardware chip selectNo action is needed by the application to select the peripheral.See the device documentation on it's chip select requirements.
Software chip selectThe application is responsible to ensure that correct SPI slave is + * selected before performing a SPI_transfer().See the device documentation on it's chip select requirements.
+ * + * ### Multiple slaves when operating in master mode # + * In a scenario where the SPI module is operating in master mode with multiple + * SPI slaves, the chip select pin can be reallocated at runtime to select the + * appropriate slave device. See [Master Mode With Multiple Slaves](@ref USE_CASE_MMMS_X2) use case below. + * This is only relevant when chip select is a hardware chip select. Otherwise the application + * can control the chip select pins directly using the PIN driver. + * + * ## Data Frames # + * + * SPI data frames can be any size from 4-bits to 16-bits. If the dataSize in + * #SPI_Params is greater that 8-bits, then the SPICC26X2DMA driver + * implementation will assume that the #SPI_Transaction txBuf and rxBuf + * point to an array of 16-bit uint16_t elements. + * + * dataSize | buffer element size | + * -------- | ------------------- | + * 4-8 bits | uint8_t | + * 9-16 bits | uint16_t | + * + * ## Bit Rate ## + * When the SPI is configured as SPI slave, the maximum bit rate is 4MHz. + * + * When the SPI is configured as SPI master, the maximum bit rate is 12MHz. + * + * + * ## UDMA # + * ### Interrupts # + * The UDMA module generates IRQs on the SPI interrupt vector. This driver automatically + * installs a UDMA aware Hwi (interrupt) to service the assigned UDMA channels. + * + * ### Transfer Size Limit # + * + * The UDMA controller only supports data transfers of up to 1024 data frames. + * A transfer with more than 1024 frames will be transmitted/received in + * multiple 1024 sized portions until all data has been transmitted/received. + * A data frame can be 4 to 16 bits in length. + * + * ### Scratch Buffers # + * A uint16_t scratch buffer is used to allow SPI_transfers where txBuf or rxBuf + * are NULL. Rather than requiring txBuf or rxBuf to have a dummy buffer of size + * of the transfer count, a single-word UDMA accessible uint16_t scratch buffer is used. + * When rxBuf is NULL, the UDMA will transfer all the received SPI data into the + * scratch buffer as a "bit-bucket". + * When txBuf is NULL, the scratch buffer is initialized to defaultTxBufValue + * so the uDMA will send some known value. + * Each SPI driver instance uses its own scratch buffer. + * + * ### TX and RX buffers # + * Before SPI_transfer, txBuf should be filled with the outgoing SPI data. These + * data are sent out during the transfer, while the incoming data are received + * into rxBuf. To save memory space, txBuf and rxBuf can be assigned to the same + * buffer location. At the beginning of the transfer, this buffer holds outgoing + * data. At the end of the transfer, the outgoing data are overwritten and + * the buffer holds the received SPI data. + * + * ## Polling SPI transfers # + * When used in blocking mode small SPI transfers are can be done by polling + * the peripheral & sending data frame-by-frame. A master device can perform + * the transfer immediately and return, but a slave will block until it + * receives the number of frames specified in the SPI_Transfer() call. + * The minDmaTransferSize field in the hardware attributes is + * the threshold; if the transaction count is below the threshold a polling + * transfer is performed; otherwise a DMA transfer is done. This is intended + * to reduce the overhead of setting up a DMA transfer to only send a few + * data frames. + * + * Notes: + * - Specifying a timeout prevents slave devices from using polling transfers. + * - Keep in mind that during polling transfers the current task + * is still being executed; there is no context switch to another task. + * + * # Supported Functions # + * | Generic API function | API function | Description | + * |-----------------------|------------------------------- |-------------------------------------------------------------| + * | SPI_init() | SPICC26X2DMA_init() | Initialize SPI driver | + * | SPI_open() | SPICC26X2DMA_open() | Initialize SPI HW and set system dependencies | + * | SPI_close() | SPICC26X2DMA_close() | Disable SPI and UDMA HW and release system dependencies | + * | SPI_control() | SPICC26X2DMA_control() | Configure an already opened SPI handle | + * | SPI_transfer() | SPICC26X2DMA_transfer() | Start transfer from SPI | + * | SPI_transferCancel() | SPICC26X2DMA_transferCancel() | Cancel ongoing transfer from SPI | + * + * @note All calls should go through the generic API + * + * ## Use Cases @anchor USE_CASES_SPI_X2 ## + * ### Basic Slave Mode # + * Receive 100 bytes over SPI in #SPI_MODE_BLOCKING. + * @code + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t rxBuf[100]; // Receive buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_SLAVE; + * + * // Configure the transaction + * transaction.count = 100; + * transaction.txBuf = NULL; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and perform the transfer + * handle = SPI_open(Board_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * @endcode + * + * ### Slave Mode With Return Partial @anchor USE_CASE_RP_X2 # + * This use case will perform a transfer in #SPI_MODE_BLOCKING until the wanted amount of bytes is + * transferred or until chip select is deasserted by the SPI master. + * This SPI_transfer() call can be used when unknown amount of bytes shall + * be transferred. Note: The partial return is also possible in #SPI_MODE_CALLBACK mode. + * @code + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t rxBuf[100]; // Receive buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_SLAVE; + * + * // Configure the transaction + * transaction.count = 100; + * transaction.txBuf = NULL; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and initiate the partial read + * handle = SPI_open(Board_SPI, ¶ms); + * + * // Enable RETURN_PARTIAL + * SPI_control(handle, SPICC26X2DMA_RETURN_PARTIAL_ENABLE, NULL); + * + * // Begin transfer + * SPI_transfer(handle, &transaction); + * @endcode + * + * ### Continuous Slave Transfer In #SPI_MODE_CALLBACK @anchor USE_CASE_CST_X2 # + * This use case will configure the SPI driver to transfer continuously in + * #SPI_MODE_CALLBACK, 16 bytes at the time and echoing received data after every + * 16 bytes. + * @code + * // Callback function + * static void transferCallback(SPI_Handle handle, SPI_Transaction *transaction) + * { + * // Start another transfer + * SPI_transfer(handle, transaction); + * } + * + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t buf[16]; // Receive and transmit buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_SLAVE; + * params.transferMode = SPI_MODE_CALLBACK; + * params.transferCallbackFxn = transferCallback; + * + * // Configure the transaction + * transaction.count = 16; + * transaction.txBuf = buf; + * transaction.rxBuf = buf; + * + * // Open the SPI and initiate the first transfer + * handle = SPI_open(Board_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * + * // Wait forever + * while(true); + * } + * @endcode + * + * ### Basic Master Mode # + * This use case will configure a SPI master to send the data in txBuf while receiving data to rxBuf in + * BLOCKING_MODE. + * @code + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t txBuf[] = "Hello World"; // Transmit buffer + * uint8_t rxBuf[11]; // Receive buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_MASTER; + * + * // Configure the transaction + * transaction.count = sizeof(txBuf); + * transaction.txBuf = txBuf; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and perform the transfer + * handle = SPI_open(Board_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * @endcode + * + * ### Master Mode With Multiple Slaves @anchor USE_CASE_MMMS_X2 # + * This use case will configure a SPI master to send data to one slave and then to another in + * BLOCKING_MODE. It is assumed that the board file is configured so that the two chip select + * pins have a default setting of a high output and that the #SPICC26X2DMA_HWAttrs used points + * to one of them since the SPI driver will revert to this default setting when switching the + * chip select pin. + * + * @code + * // From board.c + * PIN_Config BoardGpioInitTable[] = { + * Board_CSN_0 | PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH | PIN_PUSHPULL, // Ensure SPI slave 0 is not selected + * Board_CSN_1 | PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH | PIN_PUSHPULL // Ensure SPI slave 1 is not selected + * } + * + * const SPICC26X2DMA_HWAttrs SPICC26X2DMAHWAttrs[CC2650_SPICOUNT] = { + * { // Use SPI0 module with default chip select on Board_CSN_0 + * .baseAddr = SSI0_BASE, + * .intNum = INT_SSI0, + * .intPriority = ~0, + * .swiPriority = 0, + * .defaultTxBufValue = 0, + * .powerMngrId = PERIPH_SSI0, + * .rxChannelIndex = UDMA_CHAN_SSI0_RX, + * .txChannelIndex = UDMA_CHAN_SSI0_TX, + * .mosiPin = Board_SPI0_MOSI, + * .misoPin = Board_SPI0_MISO, + * .clkPin = Board_SPI0_CLK, + * .csnPin = Board_CSN_0 + * } + * + * // From your_application.c + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * PIN_Id csnPin1 = PIN_ID(Board_CSN_1); + * uint8_t txBuf[] = "Hello World"; // Transmit buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_MASTER; + * + * // Configure the transaction + * transaction.count = sizeof(txBuf); + * transaction.txBuf = txBuf; + * transaction.rxBuf = NULL; + * + * // Open the SPI and perform transfer to the first slave + * handle = SPI_open(Board_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * + * // Then switch chip select pin and perform transfer to the second slave + * SPI_control(handle, SPICC26X2DMA_SET_CSN_PIN, &csnPin1); + * SPI_transfer(handle, &transaction); + * } + * @endcode + * + * ### Queueing Transactions in Callback Mode # + * @anchor USE_CASE_QUEUE + * Below is an example of queueing three transactions + * @code + * // SPI already opened in callback mode + * SPI_Transaction t0, t1, t2; + * + * t0.txBuf = txBuff0; + * t0.rxBuf = rxBuff0; + * t0.count = 2000; + * + * t1.txBuf = txBuff1; + * t1.rxBuf = rxBuff1; + * t1.count = 1000; + * + * t2.txBuf = txBuff2; + * t2.rxBuf = NULL; + * t2.count = 1000; + * + * bool transferOk = false; + * + * if (SPI_transfer(spiHandle, &t0)) { + * if (SPI_transfer(spiHandle, &t1)) { + * transferOk = SPI_transfer(spiHandle, &t2); + * } + * } + * } + * @endcode + * + * ### Queueing in Manual Start Mode# + * This example shows a slave device queueing two transactions that will + * complete one after the other. From the master's perspective there will be + * one long transfer. + * @note Manual mode also works while the device is in #SPI_MASTER mode. The + * control call to MANUAL_START will start the transfers. + * + * @warning Manual start mode should not be enabled or disabled while a + * transaction is in progress. + * + * @anchor USE_CASE_MANUAL_START + * @code + * SPI_Handle spi; + * SPI_Params params; + * SPI_Transaction t0, t1; + * uint8_t status = SPI_STATUS_SUCCESS; + * + * SPI_Params_init(¶ms); + * params.mode = SPI_SLAVE; + * spi = SPI_open(Board_SPI, ¶ms); + * + * if (spi == NULL) { + * exit(0); + * } + * + * // Enable manual start mode + * SPI_control(spi, SPICC26X2DMA_CMD_SET_MANUAL, NULL); + * + * // Queue transactions + * t0.txBuf = txBuff0; + * t0.rxBuf = rxBuff0; + * t0.count = 2000; + * if (!SPI_transfer(spi, &t0)) { + * status = SPI_STATUS_FAIL; + * } + * + * t1.txBuf = txBuff1; + * t1.rxBuf = rxBuff1; + * t1.count = 1000; + * if (!SPI_transfer(spi, &t1)) { + * status = SPI_STATUS_FAIL; + * } + * + * // Enable the transfers + * if (status == SPI_STATUS_SUCCESS) { + * SPI_control(spi, SPICC26X2DMA_CMD_MANUAL_START, NULL); + * } + * else { + * status = SPI_STATUS_FAILURE; + * } + * + * // At this point the slave is ready for the master to start the transfer + * // Assume the callback implementation (not shown) posts a semaphore when + * // the last transaction completes + * sem_wait(&spiSemaphore); + * + * // Disable manual start mode + * SPI_control(spi, SPICC26X2DMA_CMD_CLR_MANUAL, NULL); + * + * @endcode + * + * ### Ensure low power during inactive periods @anchor USE_CASE_LPWR_X2 # + * External hardware connected on the SPI, i.e. SPI host/slave, might have configured + * a pull on one or more of the SPI lines. Dependent on the hardware, it might conflict + * with the pull used for the CC26XX SPI. To avoid increased leakage and ensure the lowest + * possible power consumption when the SPI is inactive, the application must configure a + * matching pull on the SPI IOs. An example of how this can be done is shown below. + * + * @code + * PIN_Handle pinHandle; + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t txBuf[] = "Heartbeat"; // Transmit buffer + * uint8_t rxBuf[9]; // Receive buffer + * PIN_Id misoPinId; + * uint32_t standbyDurationMs = 100; + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_MASTER; + * + * // Configure the transaction + * transaction.count = sizeof(txBuf); + * transaction.txBuf = txBuf; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and perform the transfer + * handle = SPI_open(Board_SPI, ¶ms); + * // Get pinHandle + * pinHandle = ((SPICC26X2DMA_Object *)spiHandle->object)->pinHandle; + * // Get miso pin id + * misoPinId = ((SPICC26X2DMA_HWAttrs *)spiHandle->hwAttrs)->misoPin; + * + * // Apply low power sleep pull config for MISO + * PIN_setConfig(pinHandle, PIN_BM_PULLING, PIN_PULLUP | misoPinId); + * + * // Do forever + * while(1) { + * // Transfer data + * SPI_transfer(handle, &transaction); + * // Sleep + * Task_sleep(standbyDurationMs*100); + * } + * @endcode + * + * ### Wake Up On Chip Select Deassertion In Slave Mode Using #SPI_MODE_CALLBACK # + * To wake the SPI slave device up on deassertion of the chip select, the chip select + * pin must be controled outside of the SPI driver in between SPI transfers. + * The example below show how this can be implemented by registering the chip select pin + * with the PIN driver and configuring a callback on a falling edge. + * In the PIN callback, the chip select pin is released from the PIN driver, + * the SPI driver is opened, and a transaction started. During the SPI callback, the SPI + * driver is closed again and the chip select pin is reconfigured to trigger a callback on + * a falling edge again. + * + * *Note: The SPI master must allow enough time between deasserting the chip select and the + * start of the transaction for the SPI slave to wake up and open up the SPI driver. + * + * @code + * // Global variables + * SPI_Handle spiHandle + * SPI_Params spiParams; + * SPI_Transaction spiTransaction; + * const uint8_t transferSize = 8; + * uint8_t txBuf[8]; + * PIN_Handle pinHandle; + * PIN_Config pinConfig[] = { + * PIN_INPUT_EN | PIN_PULLUP | PIN_IRQ_NEGEDGE | CS_PIN_ID, + * PIN_TERMINATE // Terminate list + * }; + * + * // Chip select callback + * static void chipSelectCallback(PIN_Handle handle, PIN_Id pinId) + * { + * // Release the chip select pin + * PIN_remove(handle, pinId); + * + * // Open SPI driver + * spiHandle = SPI_open(Board_SPI, &spiParams); + * + * // Issue echo transfer + * SPI_transfer(spiHandle, &spiTransaction); + * } + * + * // SPI transfer callback + * static void transferCallback(SPI_Handle handle, SPI_Transaction *transaction) + * { + * // Close the SPI driver + * SPI_close(handle); + * + * // Add chip select back to the PIN driver + * PIN_add(pinHandle, pinConfig[0]); + * + * // Register chip select callback + * PIN_registerIntCb(pinHandle, chipSelectCallback); + * } + * + * // From your_application.c + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * uint8_t i; + * PIN_State pinState; + * + * // Setup SPI params + * SPI_Params_init(&spiParams); + * spiParams.bitRate = 1000000; + * spiParams.frameFormat = SPI_POL1_PHA1; + * spiParams.mode = SPI_SLAVE; + * spiParams.dataSize = transferSize; + * spiParams.transferMode = SPI_MODE_CALLBACK; + * spiParams.transferCallbackFxn = transferCallback; + * + * // Setup SPI transaction + * spiTransaction.arg = NULL; + * spiTransaction.count = transferSize; + * spiTransaction.txBuf = txBuf; + * spiTransaction.rxBuf = txBuf; + * + * // First echo message + * for (i = 0; i < transferSize; i++) { + * txBuf[i] = i; + * } + * + * // Open PIN driver and configure chip select pin callback + * pinHandle = PIN_open(&pinState, pinConfig); + * PIN_registerIntCb(pinHandle, chipSelectCallback); + * + * // Wait forever + * while(true); + * } + * @endcode + * + *
+ */ + +#ifndef ti_drivers_spi_SPICC26X2DMA__include +#define ti_drivers_spi_SPICC26X2DMA__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/** + * @addtogroup SPI_STATUS + * SPICC26X2DMA_STATUS_* macros are command codes only defined in the + * SPICC26X2DMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add SPICC26X2DMA_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup SPI_CMD + * SPICC26X2DMA_CMD_* macros are command codes only defined in the + * SPICC26X2DMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/*! + * @brief Command used by SPI_control() to enable partial return + * + * Enabling this command allows SPI_transfer() to return partial data if data + * reception is inactive for a given 32-bit period. With this command @b arg + * is @a don't @a care and it returns #SPI_STATUS_SUCCESS. + */ +#define SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE (SPI_CMD_RESERVED + 0) + +/*! + * @brief Command used by SPI_control() to disable partial return + * + * Disabling this command returns the SPICC26X2DMA to the default blocking + * behavior where SPI_transfer blocks until all data bytes were received. With + * this comand @b arg is @a don't @a care and it returns #SPI_STATUS_SUCCESS. + */ +#define SPICC26X2DMA_CMD_RETURN_PARTIAL_DISABLE (SPI_CMD_RESERVED + 1) + +/*! + * @brief Command used by SPI_control() to re-configure chip select pin + * + * This command specifies a chip select pin + * With this command @b arg is of type @c PIN_Id and it return + * #SPI_STATUS_SUCCESS + */ +#define SPICC26X2DMA_CMD_SET_CSN_PIN (SPI_CMD_RESERVED + 2) + +/*! + * @brief Command used by SPI_control() to enable manual start mode + * + * Manual start mode can only be used when in callback mode. In manual start + * mode, calls to SPI_transfer() queue the transaction but does not start the + * transfer until another control call is made with + * #SPICC26X2DMA_CMD_MANUAL_START. This allows multiple transactions to be + * queued and executed seamlessly using the DMA's ping pong mechanism. This + * mode is MANDATORY for slaves queueing multiple short transactions. Manual + * start mode can only be enabled or disabled when no transactions are queued. + * + * Returns #SPI_STATUS_SUCCESS or #SPI_STATUS_ERROR. + */ +#define SPICC26X2DMA_CMD_SET_MANUAL (SPI_CMD_RESERVED + 3) + +/*! + * @brief Command used by SPI_control() to disable manual start mode + * + * Manual start mode is disabled by default. Enabling and disabling manual mode + * can only be done if no transactions are currently queued. + * + * Returns #SPI_STATUS_SUCCESS or #SPI_STATUS_ERROR. + * + */ +#define SPICC26X2DMA_CMD_CLR_MANUAL (SPI_CMD_RESERVED + 4) + +/*! + * @brief Command used by SPI_control() to enable manual start mode + * + * This command is used with manual start mode enabled. If transactions have + * been queued and the driver is in manual mode, this command will enable the + * SSI and DMA. For master devices, the transfer will start. For slave devices, + * the transfer will start when the master initiates. + * + * Returns #SPI_STATUS_SUCCESS or #SPI_STATUS_ERROR. + */ +#define SPICC26X2DMA_CMD_MANUAL_START (SPI_CMD_RESERVED + 5) + +/** @}*/ + +/* BACKWARDS COMPATIBILITY */ +#define SPICC26X2DMA_RETURN_PARTIAL_ENABLE SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE +#define SPICC26X2DMA_RETURN_PARTIAL_DISABLE SPICC26X2DMA_CMD_RETURN_PARTIAL_DISABLE +#define SPICC26X2DMA_SET_CSN_PIN SPICC26X2DMA_CMD_SET_CSN_PIN +/* END BACKWARDS COMPATIBILITY */ + +/*! + * @internal + * @brief + * SPI function table pointer + */ +extern const SPI_FxnTable SPICC26X2DMA_fxnTable; + +/*! + * @internal + * @brief + * SPICC26X2DMA data frame size is used to determine how to configure the + * UDMA data transfers. This field is to be only used internally. + * + * - SPICC26X2DMA_8bit: txBuf and rxBuf are arrays of uint8_t elements + * - SPICC26X2DMA_16bit: txBuf and rxBuf are arrays of uint16_t elements + */ +typedef enum SPICC26X2DMA_FrameSize { + SPICC26X2DMA_8bit = 0, + SPICC26X2DMA_16bit = 1 +} SPICC26X2DMA_FrameSize; + +/*! + * @internal + * @brief + * SPICC26X2DMA return partial field indicates the status of the return + * partial mode and the associated pin interrupt. This field is for internal + * use only. + */ +typedef enum SPICC26X2DMA_ReturnPartial { + SPICC26X2DMA_retPartDisabled = 0, + SPICC26X2DMA_retPartEnabledIntNotSet = 1, + SPICC26X2DMA_retPartEnabledIntSet = 2 +} SPICC26X2DMA_ReturnPartial; + +/*! + * @brief SPICC26X2DMA Hardware attributes + * + * These fields, with the exception of intPriority, + * are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC26xxWare these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * - driverlib/udma.h + * + * intPriority is the SPI peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * + * A sample structure is shown below: + * @code + * const SPICC26X2DMA_HWAttrs SPICC26X2DMAobjects[] = { + * { + * .baseAddr = SSI0_BASE, + * .intNum = INT_SPI0, + * .intPriority = ~0, + * .swiPriority = 0, + * .powerMngrId = PERIPH_SPI0, + * .defaultTxBufValue = 0, + * .rxChannelBitMask = UDMA_CHAN_SPI0_RX, + * .txChannelBitMask = UDMA_CHAN_SPI0_TX, + * .mosiPin = Board_SPI0_MISO, + * .misoPin = Board_SPI0_MOSI, + * .clkPin = Board_SPI0_CLK, + * .csnPin = Board_SPI0_CSN + * }, + * { + * .baseAddr = SSI1_BASE, + * .intNum = INT_SPI1, + * .intPriority = ~0, + * .swiPriority = 0, + * .powerMngrId = PERIPH_SPI1, + * .defaultTxBufValue = 0, + * .rxChannelBitMask = UDMA_CHAN_SPI1_RX, + * .txChannelBitMask = UDMA_CHAN_SPI1_TX, + * .mosiPin = Board_SPI1_MISO, + * .misoPin = Board_SPI1_MOSI, + * .clkPin = Board_SPI1_CLK, + * .csnPin = Board_SPI1_CSN + * }, + * }; + * @endcode + */ +typedef struct SPICC26X2DMA_HWAttrs { + /*! @brief SPI Peripheral's base address */ + uint32_t baseAddr; + /*! SPI CC26XXDMA Peripheral's interrupt vector */ + uint8_t intNum; + /*! @brief SPI CC26XXDMA Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief SPI SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying + Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! SPI Peripheral's power manager ID */ + PowerCC26XX_Resource powerMngrId; + /*! Default TX value if txBuf == NULL */ + uint16_t defaultTxBufValue; + /*! uDMA controlTable channel index */ + uint32_t rxChannelBitMask; + /*! uDMA controlTable channel index */ + uint32_t txChannelBitMask; + /*! SPI MOSI pin */ + PIN_Id mosiPin; + /*! SPI MISO pin */ + PIN_Id misoPin; + /*! SPI CLK pin */ + PIN_Id clkPin; + /*! SPI CSN pin */ + PIN_Id csnPin; + + /*! Minimum transfer size for DMA based transfer */ + uint32_t minDmaTransferSize; +} SPICC26X2DMA_HWAttrs; + +/*! + * @brief SPICC26X2DMA Object + * + * The application must not access any member variables of this structure! + */ +typedef struct SPICC26X2DMA_Object { + HwiP_Struct hwi; + PIN_Handle pinHandle; + PIN_State pinState; + Power_NotifyObj spiPostObj; + SwiP_Struct swi; + SemaphoreP_Struct transferComplete; + + SPI_CallbackFxn transferCallbackFxn; + SPI_Transaction *headPtr; + SPI_Transaction *tailPtr; + SPI_Transaction *completedTransfers; + UDMACC26XX_Handle udmaHandle; + + size_t framesQueued; + size_t framesTransferred; + size_t priTransferSize; + size_t altTransferSize; + + uint32_t activeChannel; + uint32_t bitRate; + uint32_t dataSize; + uint32_t transferTimeout; + uint32_t busyBit; + + uint16_t rxScratchBuf; + uint16_t txScratchBuf; + + SPI_TransferMode transferMode; + SPI_Mode mode; + uint8_t format; + PIN_Id csnPin; + SPICC26X2DMA_ReturnPartial returnPartial; + bool isOpen; + bool manualStart; +} SPICC26X2DMA_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_spi_SPICC26X2DMA__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26XXDMA.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26XXDMA.c new file mode 100644 index 0000000..653f706 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26XXDMA.c @@ -0,0 +1,1196 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/ssi.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/udma.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/rom.h) + +#include +#include +#include +#include + +#include +#include + +#include +#include + + +#define MAX_DMA_TRANSFER_AMOUNT (1024) + +/* SPI test control register */ +#define SSI_O_TCR 0x00000080 +#define SSI_TCR_TESTFIFO_ENABLE 0x2 +#define SSI_TCR_TESTFIFO_DISABLE 0x0 +/* SPI test data register */ +#define SSI_O_TDR 0x0000008C + +/* Local typedef only. Used to easily migrate hwattrs versions */ +typedef SPICC26XXDMA_HWAttrsV1 SPICC26XXDMA_HWAttrs; + +/* Allocate space for DMA control table entries */ +ALLOCATE_CONTROL_TABLE_ENTRY(dmaSpi0TxControlTableEntry, UDMA_CHAN_SSI0_TX); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaSpi0RxControlTableEntry, UDMA_CHAN_SSI0_RX); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaSpi1TxControlTableEntry, UDMA_CHAN_SSI1_TX); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaSpi1RxControlTableEntry, UDMA_CHAN_SSI1_RX); + +/* SPICC26XX functions */ +void SPICC26XXDMA_close(SPI_Handle handle); +int_fast16_t SPICC26XXDMA_control(SPI_Handle handle, uint_fast16_t cmd, void *arg); +void SPICC26XXDMA_init(SPI_Handle handle); +SPI_Handle SPICC26XXDMA_open(SPI_Handle handle, SPI_Params *params); +bool SPICC26XXDMA_transfer(SPI_Handle handle, SPI_Transaction *transaction); +void SPICC26XXDMA_transferCancel(SPI_Handle handle); + +/* SPICC26XX internal functions */ +static void SPICC26XXDMA_transferCallback(SPI_Handle handle, SPI_Transaction *msg); +static void SPICC26XXDMA_csnCallback(PIN_Handle handle, PIN_Id pinId); +static void SPICC26XXDMA_initHw(SPI_Handle handle); +static bool SPICC26XXDMA_initIO(SPI_Handle handle); +static void SPICC26XXDMA_flushFifos(SPI_Handle handle); + +/* Internal status macro */ +static inline bool txFifoEmpty(SPICC26XXDMA_HWAttrs const *hwAttrs); + +/* Internal power functions */ +static int spiPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg); + +/* SPI function table for SPICC26XXDMA implementation */ +const SPI_FxnTable SPICC26XXDMA_fxnTable = { + SPICC26XXDMA_close, + SPICC26XXDMA_control, + SPICC26XXDMA_init, + SPICC26XXDMA_open, + SPICC26XXDMA_transfer, + SPICC26XXDMA_transferCancel +}; + +/* Mapping SPI mode from generic driver to CC26XX driverlib */ +static const uint32_t mode[] = { + SSI_MODE_MASTER, /* SPI_MASTER */ + SSI_MODE_SLAVE /* SPI_SLAVE */ +}; + +/* Mapping SPI frame format from generic driver to CC26XX driverlib */ +static const uint32_t frameFormat[] = { + SSI_FRF_MOTO_MODE_0, /* SPI_POLO_PHA0 */ + SSI_FRF_MOTO_MODE_1, /* SPI_POLO_PHA1 */ + SSI_FRF_MOTO_MODE_2, /* SPI_POL1_PHA0 */ + SSI_FRF_MOTO_MODE_3, /* SPI_POL1_PHA1 */ + SSI_FRF_TI, /* SPI_TI */ + SSI_FRF_NMW /* SPI_MW */ +}; + +/* + * This lookup table is used to configure the DMA channels for the appropriate + * (8bit or 16bit) transfer sizes. + * Table for an SPI DMA TX channel + */ +static const unsigned long dmaTxConfig[] = { + UDMA_MODE_BASIC | UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_4, /* 8bit */ + UDMA_MODE_BASIC | UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE | UDMA_ARB_4 /* 16bit */ +}; + +/* + * This lookup table is used to configure the DMA channels for the appropriate + * (8bit or 16bit) transfer sizes. + * Table for an SPI DMA RX channel + */ +static const unsigned long dmaRxConfig[] = { + UDMA_MODE_BASIC | UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | UDMA_ARB_4, /* 8bit */ + UDMA_MODE_BASIC | UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_4 /* 16bit */ +}; + +/* + * This lookup table is used to configure the DMA channels for the appropriate + * (8bit or 16bit) transfer sizes when either txBuf or rxBuf are NULL + */ +static const uint32_t dmaNullConfig[] = { + UDMA_MODE_BASIC | UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_4, /* 8bit */ + UDMA_MODE_BASIC | UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_4 /* 16bit */ +}; + +/* + * Ensure safe setting of the standby disallow constraint. + */ +static inline void threadSafeConstraintSet(uint32_t txBufAddr, SPICC26XXDMA_Object *object) { + unsigned int key; + + /* Disable interrupts */ + key = HwiP_disable(); + + if (!object->spiPowerConstraint) { + /* Ensure flash is available if TX buffer is in flash. Flash starts with 0x0..*/ + if (((txBufAddr & 0xF0000000) == 0x0) && (txBufAddr)) { + Power_setConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + Power_setConstraint(PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING); + } + /* Set constraints to guarantee operation */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->spiPowerConstraint = true; + } + + /* Re-enable interrupts */ + HwiP_restore(key); +} + +/* + * Ensure safe releasing of the standby disallow constraint. + */ +static inline void threadSafeConstraintRelease(uint32_t txBufAddr, SPICC26XXDMA_Object *object) { + unsigned int key; + + /* Disable interrupts */ + key = HwiP_disable(); + + if (object->spiPowerConstraint) { + /* Release need flash if buffer was in flash. */ + if (((txBufAddr & 0xF0000000) == 0x0) && (txBufAddr)) { + Power_releaseConstraint(PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING); + Power_releaseConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + } + /* Release standby constraint since operation is done. */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + object->spiPowerConstraint = false; + } + + /* Re-enable interrupts */ + HwiP_restore(key); +} + +/* + * ======== spiPollingTransfer ======== + */ +static inline void spiPollingTransfer(SPICC26XXDMA_Object *object, + SPICC26XXDMA_HWAttrsV1 const *hwAttrs, SPI_Transaction *transaction) +{ + uint8_t increment; + uint32_t dummyBuffer; + size_t transferCount; + void *rxBuf; + void *txBuf; + + if (transaction->rxBuf) { + rxBuf = transaction->rxBuf; + } + else { + rxBuf = &(object->scratchBuf); + } + + if (transaction->txBuf) { + txBuf = transaction->txBuf; + } + else { + object->scratchBuf = hwAttrs->defaultTxBufValue; + txBuf = &(object->scratchBuf); + } + + increment = (object->dataSize < 9) ? sizeof(uint8_t) : sizeof(uint16_t); + transferCount = transaction->count; + + while (transferCount--) { + if (object->dataSize < 9) { + SSIDataPut(hwAttrs->baseAddr, *((uint8_t *) txBuf)); + SSIDataGet(hwAttrs->baseAddr, &dummyBuffer); + *((uint8_t *) rxBuf) = (uint8_t) dummyBuffer; + } + else { + SSIDataPut(hwAttrs->baseAddr, *((uint16_t *) txBuf)); + SSIDataGet(hwAttrs->baseAddr, &dummyBuffer); + *((uint16_t *) rxBuf) = (uint16_t) dummyBuffer; + } + + /* Only increment source & destination if buffers were provided */ + if (transaction->rxBuf) { + rxBuf = (void *) (((uint32_t) rxBuf) + increment); + } + if (transaction->txBuf) { + txBuf = (void *) (((uint32_t) txBuf) + increment); + } + } + + while (!txFifoEmpty(hwAttrs)) {} +} + +/*! + * @brief Function to close a given CC26XX SPI peripheral specified by the + * SPI handle. + * + * Will disable the SPI, disable all SPI interrupts and release the + * dependency on the corresponding power domain. + * + * @pre SPICC26XXDMA_open() has to be called first. + * Calling context: Task + * + * @param handle A SPI_Handle returned from SPI_open() + * + * @sa SPICC26XXDMA_open + */ +void SPICC26XXDMA_close(SPI_Handle handle) +{ + SPICC26XXDMA_Object *object; + SPICC26XXDMA_HWAttrs const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Release the uDMA dependency and potentially power down uDMA. */ + UDMACC26XX_close(object->udmaHandle); + + /* Deallocate pins */ + PIN_close(object->pinHandle); + + /* Disable the SPI */ + SSIDisable(hwAttrs->baseAddr); + + /* Destroy the Hwi */ + HwiP_destruct(&(object->hwi)); + + /* Destroy the Swi */ + SwiP_destruct(&(object->swi)); + + /* Release power dependency on SPI. */ + Power_releaseDependency(hwAttrs->powerMngrId); + + if (object->transferMode == SPI_MODE_BLOCKING) { + SemaphoreP_destruct(&(object->transferComplete)); + } + + /* Unregister power notification objects */ + Power_unregisterNotify(&object->spiPostObj); + + /* Mark the module as available */ + object->isOpen = false; +} + +/*! + * @brief Function for setting control parameters of the SPI driver + * after it has been opened. + * + * @pre SPICC26XXDMA_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A SPI handle returned from SPICC26XXDMA_open() + * + * @param cmd The command to execute, supported commands are: + * | Command | Description | + * |-------------------------------------- |-------------------------| + * | ::SPICC26XXDMA_CMD_RETURN_PARTIAL_ENABLE | Enable RETURN_PARTIAL | + * | ::SPICC26XXDMA_CMD_RETURN_PARTIAL_DISABLE | Disable RETURN_PARTIAL | + * | ::SPICC26XXDMA_CMD_SET_CSN_PIN | Re-configure chip select pin | + * + * @param *arg Pointer to command arguments. + * + * @return ::SPI_STATUS_SUCCESS if success, or error code if error. + */ +int_fast16_t SPICC26XXDMA_control(SPI_Handle handle, uint_fast16_t cmd, void *arg) +{ + SPICC26XXDMA_Object *object; + SPICC26XXDMA_HWAttrs const *hwAttrs; + PIN_Config pinConfig; + PIN_Id pinId; + + /* Get the pointer to the object and hwAttr */ + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Initialize return value*/ + int ret = SPI_STATUS_ERROR; + + /* Perform command */ + switch(cmd) { + case SPICC26XXDMA_CMD_RETURN_PARTIAL_ENABLE: + /* Enable RETURN_PARTIAL if slave mode is enabled */ + + if(object->mode == SPI_SLAVE){ + object->returnPartial = true; + ret = SPI_STATUS_SUCCESS; + } + else{ + /* Partial return not available in master mode. */ + ret = SPI_STATUS_ERROR; + } + break; + + case SPICC26XXDMA_CMD_RETURN_PARTIAL_DISABLE: + /* Disable RETURN_PARTIAL */ + object->returnPartial = false; + ret = SPI_STATUS_SUCCESS; + break; + + case SPICC26XXDMA_CMD_SET_CSN_PIN: + pinId = ((*(PIN_Id *) arg)); + + /* Configure CSN pin and remap PIN_ID to new CSN pin specified by arg */ + if (object->mode == SPI_SLAVE) { + pinConfig = PIN_INPUT_EN | PIN_PULLUP | pinId; + } + else { + pinConfig = PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH | PIN_PUSHPULL | PIN_INPUT_DIS | PIN_DRVSTR_MED | pinId; + } + + if (pinId != PIN_UNASSIGNED) { + /* Attempt to add the new pin */ + if (PIN_add(object->pinHandle, pinConfig) == PIN_SUCCESS) { + /* Configure pin mux */ + PINCC26XX_setMux(object->pinHandle, pinId, (hwAttrs->baseAddr == SSI0_BASE ? IOC_PORT_MCU_SSI0_FSS : IOC_PORT_MCU_SSI1_FSS)); + + /* Remove old pin and revert to default setting specified in the board file */ + PIN_remove(object->pinHandle, object->csnPin); + + /* Keep track of current CSN pin */ + object->csnPin = pinId; + + /* Set return value to indicate success */ + ret = SPI_STATUS_SUCCESS; + } + } + else { + /* We want to use software ctrl CSN. Hence, undo any prior hardware CSN pin muxing */ + /* Remove old pin and revert to default setting specified in the board file (implicitly sets IO muxing to GPIO mode) */ + PIN_remove(object->pinHandle, object->csnPin); + + /* Keep track of current CSN pin */ + object->csnPin = pinId; + + /* Set return value to indicate success */ + ret = SPI_STATUS_SUCCESS; + } + break; + + default: + /* This command is not defined */ + ret = SPI_STATUS_UNDEFINEDCMD; + break; + } + + return (ret); +} + +/* + * ======== SPICC26XXDMA_configDMA ======== + * This functions configures the transmit and receive DMA channels for a given + * SPI_Handle and SPI_Transaction + * + * @pre Function assumes that the handle and transaction is not NULL + */ +static void SPICC26XXDMA_configDMA(SPICC26XXDMA_Object *object, + SPICC26XXDMA_HWAttrs const *hwAttrs) +{ + volatile tDMAControlTable *dmaControlTableEntry; + uint16_t numberOfBytes; + + /* + * The DMA has a max transfer amount of 1024. If the transaction is + * greater; we must transfer it in chunks. object->amtDataXferred has + * how much data has already been sent. + */ + if ((object->currentTransaction->count - object->amtDataXferred) > + MAX_DMA_TRANSFER_AMOUNT) { + object->currentXferAmt = MAX_DMA_TRANSFER_AMOUNT; + } + else { + object->currentXferAmt = (object->currentTransaction->count - + object->amtDataXferred); + } + + /* Calculate the number of bytes for the transfer */ + numberOfBytes = ((uint16_t) object->currentXferAmt) << (object->frameSize); + + /* Setup RX side */ + /* Set pointer to Rx control table entry */ + dmaControlTableEntry = (hwAttrs->baseAddr == SSI0_BASE ? &dmaSpi0RxControlTableEntry : &dmaSpi1RxControlTableEntry); + if (object->currentTransaction->rxBuf) { + dmaControlTableEntry->ui32Control = dmaRxConfig[object->frameSize]; + + /* + * Add an offset for the amount of data transfered. The offset is + * calculated by: object->amtDataXferred * (object->frameSize + 1). + * This accounts for 8 or 16-bit sized transfers. + */ + dmaControlTableEntry->pvDstEndAddr = + (void *)((uint32_t) object->currentTransaction->rxBuf + + ((uint32_t) object->amtDataXferred * (object->frameSize + 1)) + + numberOfBytes - 1); + } + else { + dmaControlTableEntry->ui32Control = dmaNullConfig[object->frameSize]; + dmaControlTableEntry->pvDstEndAddr = (void *) &(object->scratchBuf); + } + dmaControlTableEntry->pvSrcEndAddr = (void *)(hwAttrs->baseAddr + SSI_O_DR); + dmaControlTableEntry->ui32Control |= UDMACC26XX_SET_TRANSFER_SIZE((uint16_t) object->currentXferAmt); + + /* Setup TX side */ + /* Set pointer to Tx control table entry */ + dmaControlTableEntry = (hwAttrs->baseAddr == SSI0_BASE ? &dmaSpi0TxControlTableEntry : &dmaSpi1TxControlTableEntry); + if (object->currentTransaction->txBuf) { + dmaControlTableEntry->ui32Control = dmaTxConfig[object->frameSize]; + + /* + * Add an offset for the amount of data transfered. The offset is + * calculated by: object->amtDataXferred * (object->frameSize + 1). + * This accounts for 8 or 16-bit sized transfers. + */ + dmaControlTableEntry->pvSrcEndAddr = + (void *)((uint32_t) object->currentTransaction->txBuf + + ((uint32_t) object->amtDataXferred * (object->frameSize + 1)) + + numberOfBytes - 1); + } + else { + object->scratchBuf = hwAttrs->defaultTxBufValue; + dmaControlTableEntry->ui32Control = dmaNullConfig[object->frameSize]; + dmaControlTableEntry->pvSrcEndAddr = (void *) &(object->scratchBuf); + } + dmaControlTableEntry->pvDstEndAddr = (void *)(hwAttrs->baseAddr + SSI_O_DR); + dmaControlTableEntry->ui32Control |= UDMACC26XX_SET_TRANSFER_SIZE((uint16_t) object->currentXferAmt); + + /* Enable the channels */ + UDMACC26XX_channelEnable(object->udmaHandle, (hwAttrs->rxChannelBitMask) | (hwAttrs->txChannelBitMask)); + + /* Enable the required DMA channels in the SPI module to start the transaction */ + SSIDMAEnable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX); +} + +/* + * ======== SPICC26XXDMA_hwiFxn ======== + * HWI ISR for the SPI when we use the UDMA + */ +static void SPICC26XXDMA_hwiFxn (uintptr_t arg) { + SPICC26XXDMA_Object *object; + SPICC26XXDMA_HWAttrs const *hwAttrs; + uint32_t intStatus; + + /* Get the pointer to the object and hwAttrs */ + object = ((SPI_Handle)arg)->object; + hwAttrs = ((SPI_Handle)arg)->hwAttrs; + + /* Get the interrupt status of the SPI controller + */ + intStatus = SSIIntStatus(hwAttrs->baseAddr, true); + SSIIntClear(hwAttrs->baseAddr, intStatus); + + /* Error handling: + * Overrun in the RX Fifo -> at least one sample in the shift + * register has been discarded */ + if (intStatus & SSI_RXOR) { + /* disable the interrupt */ + SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR); + + /* If the RX overrun occurred during a transfer */ + if (object->currentTransaction) { + /* Then cancel the ongoing transfer */ + SPICC26XXDMA_transferCancel((SPI_Handle)arg); + } + else { + /* Otherwise disable the SPI and DMA modules and flush FIFOs */ + SSIDisable(hwAttrs->baseAddr); + + /* Disable SPI TX/RX DMA and clear DMA done interrupt just in case it finished */ + SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX); + UDMACC26XX_clearInterrupt(object->udmaHandle, (hwAttrs->rxChannelBitMask) | (hwAttrs->txChannelBitMask)); + + /* Clear out the FIFO by resetting SPI module and re-initting */ + SPICC26XXDMA_flushFifos((SPI_Handle)arg); + } + } + else { + /* + * Determine if the TX DMA channel has completed... In SPI slave mode + * this interrupt may occur immediately (without the RX DMA channel). + * + * All transfers will set up both TX and RX DMA channels and both will finish. + * Even if the transaction->rxBuf == NULL, it will setup a dummy RX transfer to + * a scratch memory location which is then discarded. + */ + if (UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->txChannelBitMask)) { + /* Disable SPI TX DMA and clear DMA done interrupt. */ + SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX); + UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->txChannelBitMask); + } + + /* + * Determine if the RX DMA channel has completed... In slave mode this interrupt + * occurrence depends on when the SPI master starts sending data. + */ + if (UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->rxChannelBitMask)) { + /* Disable SPI RX DMA and clear DMA done interrupt. */ + SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_RX); + UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->rxChannelBitMask); + + /* Post SWI to handle remaining clean up and invocation of callback */ + SwiP_post(&(object->swi)); + } + } +} + +/* + * ======== SPICC26XXDMA_swiFxn ======== + * SWI ISR for the SPI when we use the UDMA + * Determine if the RX DMA channel has completed... In slave mode this interrupt + * occurrence depends on when the SPI master starts sending data. + */ +static void SPICC26XXDMA_swiFxn (uintptr_t arg0, uintptr_t arg1) { + SPI_Transaction *transaction; + SPICC26XXDMA_Object *object; + SPICC26XXDMA_HWAttrs const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = ((SPI_Handle) arg0)->object; + hwAttrs = ((SPI_Handle) arg0)->hwAttrs; + + /* Check if there is an active transaction */ + if (object->currentTransaction == NULL) { + /* If the currentTransaction is NULL, this SWI was posted already by either the ISR or transferCancel. + * Do nothing and return. + * There is no need to disable interrupts and set up a temporary pointer for this fxn. The only place + * currentTransaction can be set after initialization is in this function and this swi cannot preempt + * itself to cause a race condition in the middle of it. + */ + return; + } + + if (object->currentTransaction->count - object->amtDataXferred > + MAX_DMA_TRANSFER_AMOUNT) { + /* Data still remaining, configure another DMA transfer */ + object->amtDataXferred += object->currentXferAmt; + + SPICC26XXDMA_configDMA(object, hwAttrs); + } + else { + /* Transaction is complete */ + if (object->currentTransaction->status == SPI_TRANSFER_STARTED) { + object->currentTransaction->status = SPI_TRANSFER_COMPLETED; + } + + /* Use a temporary transaction pointer in case the callback function + * attempts to perform another SPI_transfer call + */ + transaction = object->currentTransaction; + + /* Indicate we are done with this transfer */ + object->currentTransaction = NULL; + + /* Release constraint since transaction is done */ + threadSafeConstraintRelease((uint32_t)(transaction->txBuf), object); + + /* Perform callback */ + object->transferCallbackFxn((SPI_Handle)arg0, transaction); + } +} + +/* + * ======== SPICC26XXDMA_flushTxFifo ======== + */ +void SPICC26XXDMA_flushFifos(SPI_Handle handle) { + + /* Locals */ + SPICC26XXDMA_HWAttrs const *hwAttrs; + + /* Get the pointer to the hwAttrs */ + hwAttrs = handle->hwAttrs; + + /* Flush RX FIFO */ + while(HWREG(hwAttrs->baseAddr + SSI_O_SR) & SSI_RX_NOT_EMPTY) { + /* Read element from RX FIFO and discard */ + HWREG(hwAttrs->baseAddr + SSI_O_DR); + } + + /* Enable TESTFIFO mode */ + HWREG(hwAttrs->baseAddr + SSI_O_TCR) = SSI_TCR_TESTFIFO_ENABLE; + + /* Flush TX FIFO */ + while(!(HWREG(hwAttrs->baseAddr + SSI_O_SR) & SSI_TX_EMPTY)) { + /* Read element from TX FIFO and discard */ + HWREG(hwAttrs->baseAddr + SSI_O_TDR); + } + + /* Disable TESTFIFO mode */ + HWREG(hwAttrs->baseAddr + SSI_O_TCR) = SSI_TCR_TESTFIFO_DISABLE; +} + +/*! + * @brief SPI CC26XX initialization + * + * The function will set the isOpen flag to false. + * + * @pre Calling context: Hwi, Swi, Task, Main + * + * @param handle A SPI_Handle + * + */ +void SPICC26XXDMA_init(SPI_Handle handle) +{ + SPICC26XXDMA_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Mark the object as available */ + object->isOpen = false; + + /* Init power constraint flag. */ + object->spiPowerConstraint = false; +} + +/*! + * @brief Function to initialize the CC26XX SPI peripheral specified by the + * particular handle. The parameter specifies which mode the SPI + * will operate. + * + * The function will set a dependency on it power domain, i.e. power up the + * module and enable the clock. The IOs are allocated. Neither the SPI nor UDMA module + * will be enabled. + * + * @pre SPI controller has been initialized. + * Calling context: Task + * + * @param handle A SPI_Handle + * + * @param params Pointer to a parameter block, if NULL it will use + * default values + * + * @return A SPI_Handle on success or a NULL on an error or if it has been + * already opened + * + * @sa SPICC26XXDMA_close() + */ +SPI_Handle SPICC26XXDMA_open(SPI_Handle handle, SPI_Params *params) +{ + /* Use union to save on stack allocation */ + union { + HwiP_Params hwiParams; + SwiP_Params swiParams; + } paramsUnion; + SPICC26XXDMA_Object *object; + SPICC26XXDMA_HWAttrs const *hwAttrs; + unsigned int key; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable preemption while checking if the SPI is open. */ + key = HwiP_disable(); + + /* Check if the SPI is open already with the base addr. */ + if (object->isOpen) { + HwiP_restore(key); + + return (NULL); + } + + /* Mark the handle as being used */ + object->isOpen = true; + + HwiP_restore(key); + + DebugP_assert((params->dataSize >= 4) && (params->dataSize <= 16)); + + /* Initialize the SPI object */ + object->currentTransaction = NULL; + object->bitRate = params->bitRate; + object->dataSize = params->dataSize; + object->frameFormat = params->frameFormat; + object->mode = params->mode; + object->transferMode = params->transferMode; + object->transferTimeout = params->transferTimeout; + object->returnPartial = false; + + /* Determine if we need to use an 8-bit or 16-bit framesize for the DMA */ + object->frameSize = (params->dataSize < 9) ? SPICC26XXDMA_8bit : SPICC26XXDMA_16bit; + + /* Register power dependency - i.e. power up and enable clock for SPI. */ + Power_setDependency(hwAttrs->powerMngrId); + + /* Configure the hardware module */ + SPICC26XXDMA_initHw(handle); + + /* CSN is initialized using hwAttrs initially, but can be re-configured later */ + object->csnPin = hwAttrs->csnPin; + + /* Configure IOs after hardware has been initialized so that IOs aren't */ + /* toggled unnecessary and make sure it was successful */ + if (!SPICC26XXDMA_initIO(handle)) { + /* Trying to use SPI driver when some other driver or application + * has already allocated these pins, error! */ + + /* Release power dependency - i.e. potentially power down serial domain. */ + Power_releaseDependency(hwAttrs->powerMngrId); + + object->isOpen = false; + + /* Signal back to application that SPI driver was not successfully opened */ + return (NULL); + } + + /* Create the Hwi for this SPI peripheral. */ + HwiP_Params_init(¶msUnion.hwiParams); + paramsUnion.hwiParams.arg = (uintptr_t) handle; + paramsUnion.hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), (int) hwAttrs->intNum, SPICC26XXDMA_hwiFxn, ¶msUnion.hwiParams); + + /* Create Swi object for this SPI peripheral */ + SwiP_Params_init(¶msUnion.swiParams); + paramsUnion.swiParams.arg0 = (uintptr_t)handle; + paramsUnion.swiParams.priority = hwAttrs->swiPriority; + SwiP_construct(&(object->swi), SPICC26XXDMA_swiFxn, &(paramsUnion.swiParams)); + + /* Declare the dependency on the UDMA driver */ + object->udmaHandle = UDMACC26XX_open(); + + /* Configure PIN driver for CSN callback in optional RETURN_PARTIAL slave mode */ + if (object->mode == SPI_SLAVE) { + PIN_registerIntCb(object->pinHandle, SPICC26XXDMA_csnCallback); + PIN_setUserArg(object->pinHandle, (uintptr_t) handle); + } + + /* Register notification functions */ + Power_registerNotify(&object->spiPostObj, PowerCC26XX_AWAKE_STANDBY, (Power_NotifyFxn)spiPostNotify, (uint32_t)handle); + + /* Check the transfer mode */ + if (object->transferMode == SPI_MODE_BLOCKING) { + /* Create a semaphore to block task execution for the duration of the + * SPI transfer */ + SemaphoreP_constructBinary(&(object->transferComplete), 0); + + /* Store internal callback function */ + object->transferCallbackFxn = SPICC26XXDMA_transferCallback; + } + else { + /* Check to see if a callback function was defined for async mode */ + DebugP_assert(params->transferCallbackFxn != NULL); + + /* Save the callback function pointer */ + object->transferCallbackFxn = params->transferCallbackFxn; + } + + return (handle); +} + +/*! + * @brief Function for transferring using the SPI interface. + * + * The function will enable the SPI and UDMA modules and disallow + * the device from going into standby. + * + * In ::SPI_MODE_BLOCKING, SPI_transfer will block task execution until the transfer + * has ended. + * + * In ::SPI_MODE_CALLBACK, SPI_transfer does not block task execution, but calls a + * callback function specified by transferCallback when the transfer has ended. + * + * @pre SPICC26XXDMA_open() has to be called first. + * Calling context: Hwi and Swi (only if using ::SPI_MODE_CALLBACK), Task + * + * @param handle A SPI handle returned from SPICC26XXDMA_open() + * + * @param *transaction Pointer to transaction struct + * + * @return True if transfer is successful and false if not + * + * @sa SPICC26XXDMA_open(), SPICC26XXDMA_transferCancel() + */ +bool SPICC26XXDMA_transfer(SPI_Handle handle, SPI_Transaction *transaction) +{ + unsigned int key; + uint8_t alignMask; + bool buffersAligned; + SPICC26XXDMA_Object *object; + SPICC26XXDMA_HWAttrs const *hwAttrs; + + /* Get the pointer to the object and hwAttr*/ + object = handle->object; + hwAttrs = handle->hwAttrs; + + if (transaction->count == 0 || + (transaction->rxBuf == NULL && transaction->txBuf == NULL)) { + return (false); + } + + /* + * Make sure that the buffers are aligned properly. + * alignMask is used to check if the RX/TX buffers addresses + * are aligned to the frameSize. + */ + alignMask = (object->frameSize == SPICC26XXDMA_16bit) ? 0x1 : 0x0; + buffersAligned = ((((uint32_t) transaction->rxBuf & alignMask) == 0) && + (((uint32_t) transaction->txBuf & alignMask) == 0)); + + if (!buffersAligned) { + return (false); + } + + /* Disable preemption while checking if a transfer is in progress */ + key = HwiP_disable(); + + if (object->currentTransaction) { + HwiP_restore(key); + + /* Flag that the transfer failed to start */ + transaction->status = SPI_TRANSFER_FAILED; + + /* Transfer is in progress */ + return (false); + } + + /* Make sure to flag that a transaction is now active */ + transaction->status = SPI_TRANSFER_STARTED; + object->currentTransaction = transaction; + object->amtDataXferred = 0; + object->currentXferAmt = 0; + + HwiP_restore(key); + + /* In slave mode, optionally enable callback on CSN de-assert */ + if (object->returnPartial) { + PIN_setInterrupt(object->pinHandle, object->csnPin | PIN_IRQ_POSEDGE); + } + + /* Set constraints to guarantee transaction */ + threadSafeConstraintSet((uint32_t)(transaction->txBuf), object); + + /* Enable the SPI module */ + SSIEnable(hwAttrs->baseAddr); + + /* + * Polling transfer if BLOCKING mode & transaction->count < threshold + * Slaves not allowed to use polling unless timeout is disabled + */ + if (object->transferMode == SPI_MODE_BLOCKING && + transaction->count < hwAttrs->minDmaTransferSize && + (object->mode == SPI_MASTER || + object->transferTimeout == SPI_WAIT_FOREVER)) { + HwiP_restore(key); + + spiPollingTransfer(object, hwAttrs, transaction); + + /* Disable the SPI */ + SSIDisable(hwAttrs->baseAddr); + + /* Release constraint since transaction is done */ + threadSafeConstraintRelease((uint32_t)(transaction->txBuf), object); + + /* Transaction completed; set status & mark SPI ready */ + object->currentTransaction->status = SPI_TRANSFER_COMPLETED; + object->currentTransaction = NULL; + + return (true); + } + + /* Setup DMA transfer. */ + SPICC26XXDMA_configDMA(object, hwAttrs); + + /* Enable the RX overrun interrupt in the SSI module */ + SSIIntEnable(hwAttrs->baseAddr, SSI_RXOR); + + if (object->transferMode == SPI_MODE_BLOCKING) { + if (SemaphoreP_OK != SemaphoreP_pend(&(object->transferComplete), + object->transferTimeout)) { + /* Mark the transfer as failed. Otherwise SPICC26XXDMA_transferCancel will set it to canceled. */ + if (object->currentTransaction->status == SPI_TRANSFER_STARTED) { + object->currentTransaction->status = SPI_TRANSFER_FAILED; + } + /* Cancel the transfer, if we experience a timeout */ + SPICC26XXDMA_transferCancel(handle); + /* + * SPICC26XXDMA_transferCancel performs a callback which posts a + * transferComplete semaphore. This call consumes this extra post. + */ + SemaphoreP_pend(&(object->transferComplete), SemaphoreP_NO_WAIT); + return (false); + } + } + return (true); +} + +/*! + * @brief Function that cancels a SPI transfer. Will disable SPI and UDMA modules + * and allow standby. + * + * @pre SPICC26XXDMA_open() has to be called first. + * Calling context: Task + * + * @param handle The SPI_Handle for ongoing transaction. + */ +void SPICC26XXDMA_transferCancel(SPI_Handle handle) { + SPICC26XXDMA_Object *object; + SPICC26XXDMA_HWAttrs const *hwAttrs; + SPI_Transaction *transaction; + volatile tDMAControlTable *dmaControlTableEntry; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable interrupts to ensure that this function is not interrupted. The calls to SPICC26XXDMA_transferCancel + * within the driver are safe. However, this function may be called by the application in callback mode. + * Hence, it might be preempted by the SPI hwi and swi or the PIN hwi and swi. + */ + uint32_t key = HwiP_disable(); + + /* Check if there is an active transaction */ + if(object->currentTransaction == NULL) { + HwiP_restore(key); + + return; + } + + transaction = object->currentTransaction; + + HwiP_restore(key); + + /* Disable the SPI module */ + SSIDisable(hwAttrs->baseAddr); + + /* Disable SPI TX/RX DMA and clear DMA done interrupt just in case it finished */ + SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX); + UDMACC26XX_clearInterrupt(object->udmaHandle, (hwAttrs->rxChannelBitMask) | (hwAttrs->txChannelBitMask)); + + /* Disable and clear any pending interrupts */ + SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR); + SSIIntClear(hwAttrs->baseAddr, SSI_RXOR); + + /* Flush the FIFOs and re-initialize module */ + SPICC26XXDMA_flushFifos(handle); + + /* Release constraint since transaction is done */ + threadSafeConstraintRelease((uint32_t)(transaction->txBuf), object); + + /* Mark the transaction as failed if we didn't end up here due to a CSN deassertion */ + if (transaction->status == SPI_TRANSFER_STARTED) { + transaction->status = SPI_TRANSFER_CANCELED; + } + + /* Disable the UDMA channels */ + UDMACC26XX_channelDisable(object->udmaHandle, (hwAttrs->rxChannelBitMask) | (hwAttrs->txChannelBitMask)); + + /* Update the SPI_Transaction.count parameter */ + /* rxChannel always finishes after txChannel so remaining bytes of the rxChannel is used to update count */ + dmaControlTableEntry = (hwAttrs->baseAddr == SSI0_BASE ? &dmaSpi0RxControlTableEntry : &dmaSpi1RxControlTableEntry); + transaction->count = object->amtDataXferred + (object->currentXferAmt - + UDMACC26XX_GET_TRANSFER_SIZE(dmaControlTableEntry->ui32Control)); + + /* Post SWI to handle remaining clean up and invocation of callback */ + SwiP_post(&(object->swi)); +} + +/* + * ======== SPICC26XXDMA_transferCallback ======== + * Callback function for when the SPI is in SPI_MODE_BLOCKING + * + * @pre Function assumes that the handle is not NULL + */ +static void SPICC26XXDMA_transferCallback(SPI_Handle handle, SPI_Transaction *msg) +{ + SPICC26XXDMA_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Post the semaphore */ + SemaphoreP_post(&(object->transferComplete)); +} + +/* + * ======== SPICC26XXDMA_csnDeassertCallback ======== + * Slave mode optional callback function for when the CSN is deasserted + * + * @pre Function assumes that the handle is not NULL + */ +static void SPICC26XXDMA_csnCallback(PIN_Handle handle, PIN_Id pinId) +{ + SPICC26XXDMA_Object *object; + SPI_Handle spiHandle; + PIN_Config csnConfig; + + /* Get the pointer to the SPI object */ + spiHandle = (SPI_Handle) PIN_getUserArg(handle); + object = spiHandle->object; + + /* Get current CSN config */ + csnConfig = PIN_getConfig(object->csnPin); + + /* Disable all interrupts */ + PIN_setInterrupt(handle, object->csnPin); + + /* Cancel transfer if POSEDGE interrupt */ + /* TODO: Consider doing this in a SWI */ + if ((csnConfig & PIN_IRQ_POSEDGE) == PIN_IRQ_POSEDGE) { + /* Indicate why the transaction completed */ + if ((object->currentTransaction != NULL) && (object->currentTransaction->status == SPI_TRANSFER_STARTED)) { + object->currentTransaction->status = SPI_TRANSFER_CSN_DEASSERT; + } + /* Cancel the current transaction */ + SPICC26XXDMA_transferCancel(spiHandle); + } +} + +/* +* ======== SPICC26XXDMA_hwInit ======== +* This functions initializes the SPI hardware module. +* +* @pre Function assumes that the SPI handle is pointing to a hardware +* module which has already been opened. +*/ +static void SPICC26XXDMA_initHw(SPI_Handle handle) { + SPICC26XXDMA_Object *object; + SPICC26XXDMA_HWAttrs const *hwAttrs; + ClockP_FreqHz freq; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable SSI operation */ + SSIDisable(hwAttrs->baseAddr); + + /* Disable SPI module interrupts */ + SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR | SSI_RXFF | SSI_RXTO | SSI_TXFF); + SSIIntClear(hwAttrs->baseAddr, SSI_RXOR | SSI_RXTO); + + /* Set the SPI configuration */ + ClockP_getCpuFreq(&freq); + SSIConfigSetExpClk(hwAttrs->baseAddr, freq.lo, frameFormat[object->frameFormat], + mode[object->mode], object->bitRate, object->dataSize); +} + +/* +* ======== SPICC26XXDMA_hwInit ======== +* This functions initializes the SPI IOs. +* +* @pre Function assumes that the SPI handle is pointing to a hardware +* module which has already been opened. +*/ +static bool SPICC26XXDMA_initIO(SPI_Handle handle) { + SPICC26XXDMA_Object *object; + SPICC26XXDMA_HWAttrs const *hwAttrs; + PIN_Config spiPinTable[5]; + uint32_t i = 0; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Configure IOs */ + /* Build local list of pins, allocate through PIN driver and map HW ports */ + if (object->mode == SPI_SLAVE) { + /* Configure IOs for slave mode */ + spiPinTable[i++] = hwAttrs->mosiPin | PIN_INPUT_EN; + spiPinTable[i++] = hwAttrs->misoPin | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_INPUT_DIS | PIN_DRVSTR_MED; + spiPinTable[i++] = hwAttrs->clkPin | PIN_INPUT_EN; + spiPinTable[i++] = object->csnPin | PIN_INPUT_EN | PIN_PULLUP; + } + else { + /* Configure IOs for master mode */ + spiPinTable[i++] = hwAttrs->mosiPin | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_INPUT_DIS | PIN_DRVSTR_MED; + spiPinTable[i++] = hwAttrs->misoPin | PIN_INPUT_EN | PIN_PULLDOWN; + + /* Output low signal on SCLK until SPI module drives signal if clock polarity is configured to '0' */ + /* Output high signal on SCLK until SPI module drives signal if clock polarity is configured to '1' */ + if (object->frameFormat == SPI_POL0_PHA0 || object->frameFormat == SPI_POL0_PHA1) { + spiPinTable[i++] = hwAttrs->clkPin | PIN_GPIO_OUTPUT_EN | PIN_GPIO_LOW | PIN_PUSHPULL | PIN_INPUT_DIS | PIN_DRVSTR_MED; + } + else { + spiPinTable[i++] = hwAttrs->clkPin | PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH | PIN_PUSHPULL | PIN_INPUT_DIS | PIN_DRVSTR_MED; + } + + /* If CSN isn't SW controlled, drive it high until SPI module drives signal to avoid glitches */ + if(object->csnPin != PIN_UNASSIGNED) { + spiPinTable[i++] = object->csnPin | PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH | PIN_PUSHPULL | PIN_INPUT_DIS | PIN_DRVSTR_MED; + } + } + spiPinTable[i++] = PIN_TERMINATE; + + /* Open and assign pins through pin driver */ + if (!(object->pinHandle = PIN_open(&(object->pinState), spiPinTable))) { + return false; + } + + /* Set IO muxing for the SPI pins */ + if (mode[object->mode] == SSI_MODE_SLAVE) { + /* Configure IOs for slave mode */ + PINCC26XX_setMux(object->pinHandle, hwAttrs->mosiPin, (hwAttrs->baseAddr == SSI0_BASE ? IOC_PORT_MCU_SSI0_RX : IOC_PORT_MCU_SSI1_RX)); + PINCC26XX_setMux(object->pinHandle, hwAttrs->misoPin, (hwAttrs->baseAddr == SSI0_BASE ? IOC_PORT_MCU_SSI0_TX : IOC_PORT_MCU_SSI1_TX)); + PINCC26XX_setMux(object->pinHandle, hwAttrs->clkPin, (hwAttrs->baseAddr == SSI0_BASE ? IOC_PORT_MCU_SSI0_CLK : IOC_PORT_MCU_SSI1_CLK)); + PINCC26XX_setMux(object->pinHandle, object->csnPin, (hwAttrs->baseAddr == SSI0_BASE ? IOC_PORT_MCU_SSI0_FSS : IOC_PORT_MCU_SSI1_FSS)); + } + else { + /* Configure IOs for master mode */ + PINCC26XX_setMux(object->pinHandle, hwAttrs->mosiPin, (hwAttrs->baseAddr == SSI0_BASE ? IOC_PORT_MCU_SSI0_TX : IOC_PORT_MCU_SSI1_TX)); + PINCC26XX_setMux(object->pinHandle, hwAttrs->misoPin, (hwAttrs->baseAddr == SSI0_BASE ? IOC_PORT_MCU_SSI0_RX : IOC_PORT_MCU_SSI1_RX)); + PINCC26XX_setMux(object->pinHandle, hwAttrs->clkPin, (hwAttrs->baseAddr == SSI0_BASE ? IOC_PORT_MCU_SSI0_CLK : IOC_PORT_MCU_SSI1_CLK)); + if(object->csnPin != PIN_UNASSIGNED) { + PINCC26XX_setMux(object->pinHandle, object->csnPin, (hwAttrs->baseAddr == SSI0_BASE ? IOC_PORT_MCU_SSI0_FSS : IOC_PORT_MCU_SSI1_FSS)); + } + } + + return true; +} + +/* + * ======== spiPostNotify ======== + * This functions is called to notify the SPI driver of an ongoing transition + * out of sleep mode. + * + * @pre Function assumes that the SPI handle (clientArg) is pointing to a + * hardware module which has already been opened. + */ +static int spiPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg) +{ + SPI_Handle spiHandle; + + /* Get the pointers to SPI objects */ + spiHandle = (SPI_Handle) clientArg; + + /* Reconfigure the hardware when returning from standby */ + SPICC26XXDMA_initHw(spiHandle); + + return Power_NOTIFYDONE; +} + +/* + * ======== txFifoEmpty ======== + */ +static inline bool txFifoEmpty(SPICC26XXDMA_HWAttrs const *hwAttrs) +{ + return(HWREG(hwAttrs->baseAddr + SSI_O_SR) & SSI_SR_TFE); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26XXDMA.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26XXDMA.h new file mode 100644 index 0000000..2ca2441 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26XXDMA.h @@ -0,0 +1,868 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file SPICC26XXDMA.h + * + * @brief SPI driver implementation for a CC26XX SPI controller using + * the UDMA controller. + * + * # Driver include # + * The SPI header file should be included in an application as follows: + * @code + * #include + * #include + * #include + * @endcode + * + * Refer to @ref SPI.h for a complete description of APIs. + * + * Note that the user also needs to include the UDMACC26XX.h driver since the + * SPI uses uDMA in order to improve throughput. + * + * # Overview # + * The general SPI API should be used in application code, i.e. SPI_open() + * should be used instead of SPICC26XXDMA_open(). The board file will define the device + * specific config, and casting in the general API will ensure that the correct + * device specific functions are called. + * This is also reflected in the example code in [Use Cases](@ref USE_CASES_SPI). + * + * # General Behavior # + * Before using SPI on CC26XX: + * - The SPI driver is initialized by calling SPI_init(). + * - The SPI HW is configured and flags system dependencies (e.g. IOs, + * power, etc.) by calling SPI_open(). + * - The SPI driver makes use of DMA in order to optimize throughput. + * This is handled directly by the SPI driver, so the application should never + * to make any calls directly to the UDMACC26XX.h driver. + * + * The following is true for slave operation: + * - RX overrun IRQ, SPI and UDMA modules are enabled by calling SPI_transfer(). + * - All received bytes are ignored after SPI_open() is called, until + * the first SPI_transfer(). + * - If an RX overrun occur or if SPI_transferCancel() is called, RX overrun IRQ, SPI and UDMA + * modules are disabled, TX and RX FIFOs are flushed and all bytes are ignored. + * - After a successful transfer, RX overrun IRQ and SPI module remains enabled and UDMA module is disabled. + * SPI_transfer() must be called again before RX FIFO goes full in order to + * avoid overflow. If the TX buffer is underflowed, zeros will be output. + * It is safe to call another SPI_transfer() from the transfer callback, + * see [Continuous Slave Transfer] (@ref USE_CASE_CST) use case below. + * - The SPI driver supports partial return, that can be used if the + * passed to SPI_control(), the transfer will end when chip select is + * deasserted. The #SPI_Transaction.status and the #SPI_Transaction.count + * will be updated to indicate whether the transfer ended due to a chip + * select deassertion and how many bytes were transferred. See + * [Slave Mode With Return Partial] (@ref USE_CASE_RP_X2) use case below. + * + * @warning The SPI modules on the CC13x0, CC26x0, and CC26x0R2 devices have a + * bug which may result in TX data being lost when operating in SPI slave + * mode. Please refer to the device errata sheet for full details. The SPI + * protocol should therefore include a data integrity check, such as + * appending a CRC to the payload to ensure all the data was transmitted + * correctly by the SPI slave. + * + * @warning This driver does not support queueing multiple SPI transactions. + * + * The following apply for master operation: + * - SPI and UDMA modules are enabled by calling SPI_transfer(). + * - If the SPI_transfer() succeeds, SPI module is enabled and UDMA module is disabled. + * - If SPI_transferCancel() is called, SPI and UDMA modules are disabled and + * TX and RX FIFOs are flushed. + * . + * After SPI operation has ended: + * - Release system dependencies for SPI by calling SPI_close(). + * . + * The callback function is called in the following context: + * - When an error occurs, the callback function is called in a HWI context. + * - When no error occurs, the callback function is called in a SWI context. + * + * @warning The application should avoid transmitting data stored in flash via SPI if the application + * might switch to the XOSC_HF, the high frequency external oscillator, during this transfer. + * + * # Error handling # + * If an RX overrun occurs during slave operation: + * - If a transfer is ongoing, all bytes received up until the error occurs will be returned, with the + * error signaled in the #SPI_Transaction.status field. RX overrun IRQ, SPI and UDMA modules are then disabled, + * TX and RX FIFOs are flushed and all bytes will be ignored until a new transfer is issued. + * - If a transfer is not ongoing, RX overrun IRQ, SPI and UDMA modules are disabled, + * TX and RX FIFOs are flushed and all bytes will be ignored until a new transfer is issued. + * + * # Timeout # + * Timeout can occur in #SPI_MODE_BLOCKING, there's no timeout in #SPI_MODE_CALLBACK. + * When in #SPI_MODE_CALLBACK, the transfer must be cancelled by calling SPI_transferCancel().\n + * If a timeout happens in either #SPI_SLAVE or #SPI_MASTER mode, + * the receive buffer will contain the bytes received up until the timeout occurred. + * The SPI transaction status will be set to #SPI_TRANSFER_FAILED. + * The SPI transaction count will be set to the number of bytes sent/received before timeout. + * The remaining bytes will be flushed from the TX FIFO so that the subsequent transfer + * can be executed correctly. Note that specifying a timeout prevents the + * driver from performing a polling transfer when in slave mode. + * + * # Power Management # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * The SPICC26XXDMA.h driver is setting a power constraint during transfers to keep + * the device out of standby. When the transfer has finished, the power + * constraint is released. + * The following statements are valid: + * - After SPI_open(): the device is still allowed to enter standby. + * - In slave mode: + * - During SPI_transfer(): the device cannot enter standby, only idle. + * - After an RX overflow: device is allowed to enter standby. + * - After a successful SPI_transfer(): the device is allowed + * to enter standby, but SPI module remains enabled. + * - _Note_: In slave mode, the device might enter standby while a byte is being + * transferred if SPI_transfer() is not called again after a successful + * transfer. This could result in corrupt data being transferred. + * - Application thread should typically either issue another transfer after + * SPI_transfer() completes successfully, or call + * SPI_transferCancel() to disable the SPI module and thus assuring that no data + * is received while entering standby. + * . + * - In master mode: + * - During SPI_transfer(): the device cannot enter standby, only idle. + * - After SPI_transfer() succeeds: the device can enter standby. + * - If SPI_transferCancel() is called: the device can enter standby. + * + * @note The external hardware connected to the SPI might have some pull configured on the + * SPI lines. When the SPI is inactive, this might cause leakage on the IO and the + * current consumption to increase. The application must configure a pull configuration + * that aligns with the external hardware. + * See [Ensure low power during inactive periods] (@ref USE_CASE_LPWR) for code example. + * + * # SPI details # + * ## Chip Select # + * This SPI controller supports a hardware chip select pin. Refer to the + * user manual on how this hardware chip select pin behaves in regards + * to the SPI frame format. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Chip select typeSPI_MASTER modeSPI_SLAVE mode
Hardware chip selectNo action is needed by the application to select the peripheral.See the device documentation on it's chip select requirements.
Software chip selectThe application is responsible to ensure that correct SPI slave is + * selected before performing a SPI_transfer().See the device documentation on it's chip select requirements.
+ * + * ### Multiple slaves when operating in master mode # + * In a scenario where the SPI module is operating in master mode with multiple + * SPI slaves, the chip select pin can be reallocated at runtime to select the + * appropriate slave device. See [Master Mode With Multiple Slaves](@ref USE_CASE_MMMS) use case below. + * This is only relevant when chip select is a hardware chip select. Otherwise the application + * can control the chip select pins directly using the PIN driver. + * + * ## Data Frames # + * + * SPI data frames can be any size from 4-bits to 16-bits. If the dataSize in + * #SPI_Params is greater that 8-bits, then the SPICC26XXDMA driver + * implementation will assume that the #SPI_Transaction txBuf and rxBuf + * point to an array of 16-bit uint16_t elements. + * + * dataSize | buffer element size | + * -------- | ------------------- | + * 4-8 bits | uint8_t | + * 9-16 bits | uint16_t | + * + * ## Bit Rate ## + * When the SPI is configured as SPI slave, the maximum bit rate is 4MHz. + * + * When the SPI is configured as SPI master, the maximum bit rate is 12MHz. + * + * + * ## UDMA # + * ### Interrupts # + * The UDMA module generates IRQs on the SPI interrupt vector. This driver automatically + * installs a UDMA aware Hwi (interrupt) to service the assigned UDMA channels. + * + * ### Transfer Size Limit # + * + * The UDMA controller only supports data transfers of up to 1024 data frames. + * A transfer with more than 1024 frames will be transmitted/received in + * multiple 1024 sized portions until all data has been transmitted/received. + * A data frame can be 4 to 16 bits in length. + * + * ### Scratch Buffers # + * A uint16_t scratch buffer is used to allow SPI_transfers where txBuf or rxBuf + * are NULL. Rather than requiring txBuf or rxBuf to have a dummy buffer of size + * of the transfer count, a single-word UDMA accessible uint16_t scratch buffer is used. + * When rxBuf is NULL, the UDMA will transfer all the received SPI data into the + * scratch buffer as a "bit-bucket". + * When txBuf is NULL, the scratch buffer is initialized to defaultTxBufValue + * so the uDMA will send some known value. + * Each SPI driver instance uses its own scratch buffer. + * + * ### TX and RX buffers # + * Before SPI_transfer, txBuf should be filled with the outgoing SPI data. These + * data are sent out during the transfer, while the incoming data are received + * into rxBuf. To save memory space, txBuf and rxBuf can be assigned to the same + * buffer location. At the beginning of the transfer, this buffer holds outgoing + * data. At the end of the transfer, the outgoing data are overwritten and + * the buffer holds the received SPI data. + * + * ## Polling SPI transfers # + * When used in blocking mode small SPI transfers are can be done by polling + * the peripheral & sending data frame-by-frame. A master device can perform + * the transfer immediately and return, but a slave will block until it + * receives the number of frames specified in the SPI_Transfer() call. + * The minDmaTransferSize field in the hardware attributes is + * the threshold; if the transaction count is below the threshold a polling + * transfer is performed; otherwise a DMA transfer is done. This is intended + * to reduce the overhead of setting up a DMA transfer to only send a few + * data frames. + * + * Notes: + * - Specifying a timeout prevents slave devices from using polling transfers. + * - Keep in mind that during polling transfers the current task + * is still being executed; there is no context switch to another task. + + * + * # Supported Functions # + * | Generic API function | API function | Description | + * |-----------------------|------------------------------- |-------------------------------------------------------------| + * | SPI_init() | SPICC26XXDMA_init() | Initialize SPI driver | + * | SPI_open() | SPICC26XXDMA_open() | Initialize SPI HW and set system dependencies | + * | SPI_close() | SPICC26XXDMA_close() | Disable SPI and UDMA HW and release system dependencies | + * | SPI_control() | SPICC26XXDMA_control() | Configure an already opened SPI handle | + * | SPI_transfer() | SPICC26XXDMA_transfer() | Start transfer from SPI | + * | SPI_transferCancel() | SPICC26XXDMA_transferCancel() | Cancel ongoing transfer from SPI | + * + * @note All calls should go through the generic API + * + * ## Unsupported Functionality # + * The CC26XX SPI driver does not support: + * - SPICC26XXDMA_serviceISR() + * + * ## Use Cases @anchor USE_CASES_SPI ## + * ### Basic Slave Mode # + * Receive 100 bytes over SPI in #SPI_MODE_BLOCKING. + * @code + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t rxBuf[100]; // Receive buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_SLAVE; + * + * // Configure the transaction + * transaction.count = 100; + * transaction.txBuf = NULL; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and perform the transfer + * handle = SPI_open(Board_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * @endcode + * + * ### Slave Mode With Return Partial @anchor USE_CASE_RP # + * This use case will perform a transfer in #SPI_MODE_BLOCKING until the wanted amount of bytes is + * transferred or until chip select is deasserted by the SPI master. + * This SPI_transfer() call can be used when unknown amount of bytes shall + * be transferred. Note: The partial return is also possible in #SPI_MODE_CALLBACK mode. + * @code + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t rxBuf[100]; // Receive buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_SLAVE; + * + * // Configure the transaction + * transaction.count = 100; + * transaction.txBuf = NULL; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and initiate the partial read + * handle = SPI_open(Board_SPI, ¶ms); + * + * // Enable RETURN_PARTIAL + * SPI_control(handle, SPICC26XXDMA_RETURN_PARTIAL_ENABLE, NULL); + * + * // Begin transfer + * SPI_transfer(handle, &transaction); + * @endcode + * + * ### Continuous Slave Transfer In #SPI_MODE_CALLBACK @anchor USE_CASE_CST # + * This use case will configure the SPI driver to transfer continuously in + * #SPI_MODE_CALLBACK, 16 bytes at the time and echoing received data after every + * 16 bytes. + * @code + * // Callback function + * static void transferCallback(SPI_Handle handle, SPI_Transaction *transaction) + * { + * // Start another transfer + * SPI_transfer(handle, transaction); + * } + * + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t buf[16]; // Receive and transmit buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_SLAVE; + * params.transferMode = SPI_MODE_CALLBACK; + * params.transferCallbackFxn = transferCallback; + * + * // Configure the transaction + * transaction.count = 16; + * transaction.txBuf = buf; + * transaction.rxBuf = buf; + * + * // Open the SPI and initiate the first transfer + * handle = SPI_open(Board_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * + * // Wait forever + * while(true); + * } + * @endcode + * + * ### Basic Master Mode # + * This use case will configure a SPI master to send the data in txBuf while receiving data to rxBuf in + * BLOCKING_MODE. + * @code + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t txBuf[] = "Hello World"; // Transmit buffer + * uint8_t rxBuf[11]; // Receive buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_MASTER; + * + * // Configure the transaction + * transaction.count = sizeof(txBuf); + * transaction.txBuf = txBuf; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and perform the transfer + * handle = SPI_open(Board_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * @endcode + * + * ### Master Mode With Multiple Slaves @anchor USE_CASE_MMMS # + * This use case will configure a SPI master to send data to one slave and then to another in + * BLOCKING_MODE. It is assumed that the board file is configured so that the two chip select + * pins have a default setting of a high output and that the #SPICC26XXDMA_HWAttrsV1 used points + * to one of them since the SPI driver will revert to this default setting when switching the + * chip select pin. + * + * @code + * // From board.c + * PIN_Config BoardGpioInitTable[] = { + * Board_CSN_0 | PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH | PIN_PUSHPULL, // Ensure SPI slave 0 is not selected + * Board_CSN_1 | PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH | PIN_PUSHPULL // Ensure SPI slave 1 is not selected + * } + * + * const SPICC26XXDMA_HWAttrsV1 spiCC26XXDMAHWAttrs[CC2650_SPICOUNT] = { + * { // Use SPI0 module with default chip select on Board_CSN_0 + * .baseAddr = SSI0_BASE, + * .intNum = INT_SSI0, + * .intPriority = ~0, + * .swiPriority = 0, + * .defaultTxBufValue = 0, + * .powerMngrId = PERIPH_SSI0, + * .rxChannelIndex = UDMA_CHAN_SSI0_RX, + * .txChannelIndex = UDMA_CHAN_SSI0_TX, + * .mosiPin = Board_SPI0_MOSI, + * .misoPin = Board_SPI0_MISO, + * .clkPin = Board_SPI0_CLK, + * .csnPin = Board_CSN_0 + * } + * + * // From your_application.c + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * PIN_Id csnPin1 = PIN_ID(Board_CSN_1); + * uint8_t txBuf[] = "Hello World"; // Transmit buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_MASTER; + * + * // Configure the transaction + * transaction.count = sizeof(txBuf); + * transaction.txBuf = txBuf; + * transaction.rxBuf = NULL; + * + * // Open the SPI and perform transfer to the first slave + * handle = SPI_open(Board_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * + * // Then switch chip select pin and perform transfer to the second slave + * SPI_control(handle, SPICC26XXDMA_SET_CSN_PIN, &csnPin1); + * SPI_transfer(handle, &transaction); + * } + * @endcode + * + * ### Ensure low power during inactive periods @anchor USE_CASE_LPWR # + * External hardware connected on the SPI, i.e. SPI host/slave, might have configured + * a pull on one or more of the SPI lines. Dependent on the hardware, it might conflict + * with the pull used for the CC26XX SPI. To avoid increased leakage and ensure the lowest + * possible power consumption when the SPI is inactive, the application must configure a + * matching pull on the SPI IOs. An example of how this can be done is shown below. + * + * @code + * PIN_Handle pinHandle; + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t txBuf[] = "Heartbeat"; // Transmit buffer + * uint8_t rxBuf[9]; // Receive buffer + * PIN_Id misoPinId; + * uint32_t standbyDurationMs = 100; + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_MASTER; + * + * // Configure the transaction + * transaction.count = sizeof(txBuf); + * transaction.txBuf = txBuf; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and perform the transfer + * handle = SPI_open(Board_SPI, ¶ms); + * // Get pinHandle + * pinHandle = ((SPICC26XXDMA_Object *)spiHandle->object)->pinHandle; + * // Get miso pin id + * misoPinId = ((SPICC26XXDMA_HWAttrsV1 *)spiHandle->hwAttrs)->misoPin; + * + * // Apply low power sleep pull config for MISO + * PIN_setConfig(pinHandle, PIN_BM_PULLING, PIN_PULLUP | misoPinId); + * + * // Do forever + * while(1) { + * // Transfer data + * SPI_transfer(handle, &transaction); + * // Sleep + * Task_sleep(standbyDurationMs*100); + * } + * @endcode + * + * ### Wake Up On Chip Select Deassertion In Slave Mode Using #SPI_MODE_CALLBACK # + * To wake the SPI slave device up on deassertion of the chip select, the chip select + * pin must be controled outside of the SPI driver in between SPI transfers. + * The example below show how this can be implemented by registering the chip select pin + * with the PIN driver and configuring a callback on a falling edge. + * In the PIN callback, the chip select pin is released from the PIN driver, + * the SPI driver is opened, and a transaction started. During the SPI callback, the SPI + * driver is closed again and the chip select pin is reconfigured to trigger a callback on + * a falling edge again. + * + * *Note: The SPI master must allow enough time between deasserting the chip select and the + * start of the transaction for the SPI slave to wake up and open up the SPI driver. + * + * @code + * // Global variables + * SPI_Handle spiHandle + * SPI_Params spiParams; + * SPI_Transaction spiTransaction; + * const uint8_t transferSize = 8; + * uint8_t txBuf[8]; + * PIN_Handle pinHandle; + * PIN_Config pinConfig[] = { + * PIN_INPUT_EN | PIN_PULLUP | PIN_IRQ_NEGEDGE | CS_PIN_ID, + * PIN_TERMINATE // Terminate list + * }; + * + * // Chip select callback + * static void chipSelectCallback(PIN_Handle handle, PIN_Id pinId) + * { + * // Release the chip select pin + * PIN_remove(handle, pinId); + * + * // Open SPI driver + * spiHandle = SPI_open(Board_SPI, &spiParams); + * + * // Issue echo transfer + * SPI_transfer(spiHandle, &spiTransaction); + * } + * + * // SPI transfer callback + * static void transferCallback(SPI_Handle handle, SPI_Transaction *transaction) + * { + * // Close the SPI driver + * SPI_close(handle); + * + * // Add chip select back to the PIN driver + * PIN_add(pinHandle, pinConfig[0]); + * + * // Register chip select callback + * PIN_registerIntCb(pinHandle, chipSelectCallback); + * } + * + * // From your_application.c + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * uint8_t i; + * PIN_State pinState; + * + * // Setup SPI params + * SPI_Params_init(&spiParams); + * spiParams.bitRate = 1000000; + * spiParams.frameFormat = SPI_POL1_PHA1; + * spiParams.mode = SPI_SLAVE; + * spiParams.dataSize = transferSize; + * spiParams.transferMode = SPI_MODE_CALLBACK; + * spiParams.transferCallbackFxn = transferCallback; + * + * // Setup SPI transaction + * spiTransaction.arg = NULL; + * spiTransaction.count = transferSize; + * spiTransaction.txBuf = txBuf; + * spiTransaction.rxBuf = txBuf; + * + * // First echo message + * for (i = 0; i < transferSize; i++) { + * txBuf[i] = i; + * } + * + * // Open PIN driver and configure chip select pin callback + * pinHandle = PIN_open(&pinState, pinConfig); + * PIN_registerIntCb(pinHandle, chipSelectCallback); + * + * // Wait forever + * while(true); + * } + * @endcode + * + * # Instrumentation # + * The SPI driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic SPI operations performed | + * Diags_USER2 | detailed SPI operations performed | + * + * ============================================================================ + */ + +#ifndef ti_drivers_spi_SPICC26XXDMA__include +#define ti_drivers_spi_SPICC26XXDMA__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/** + * @addtogroup SPI_STATUS + * SPICC26XXDMA_STATUS_* macros are command codes only defined in the + * SPICC26XXDMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add SPICC26XXDMA_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup SPI_CMD + * SPICC26XXDMA_CMD_* macros are command codes only defined in the + * SPICC26XXDMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/*! + * @brief Command used by SPI_control to enable partial return + * + * Enabling this command allows SPI_transfer to return partial data if data + * reception is inactive for a given 32-bit period. With this command @b arg + * is @a don't @a care and it returns SPI_STATUS_SUCCESS. + */ +#define SPICC26XXDMA_CMD_RETURN_PARTIAL_ENABLE (SPI_CMD_RESERVED + 0) + +/*! + * @brief Command used by SPI_control to disable partial return + * + * Disabling this command returns the SPICC26XXDMA to the default blocking + * behavior where SPI_transfer blocks until all data bytes were received. With + * this comand @b arg is @a don't @a care and it returns SPI_STATUS_SUCCESS. + */ +#define SPICC26XXDMA_CMD_RETURN_PARTIAL_DISABLE (SPI_CMD_RESERVED + 1) + +/*! + * @brief Command used by SPI_control to re-configure chip select pin + * + * This command specifies a chip select pin + * With this command @b arg is of type @c PIN_Id and it return SPI_STATUS_SUCCESS + */ +#define SPICC26XXDMA_CMD_SET_CSN_PIN (SPI_CMD_RESERVED + 2) +/** @}*/ + +/* BACKWARDS COMPATIBILITY */ +#define SPICC26XXDMA_RETURN_PARTIAL_ENABLE SPICC26XXDMA_CMD_RETURN_PARTIAL_ENABLE +#define SPICC26XXDMA_RETURN_PARTIAL_DISABLE SPICC26XXDMA_CMD_RETURN_PARTIAL_DISABLE +#define SPICC26XXDMA_SET_CSN_PIN SPICC26XXDMA_CMD_SET_CSN_PIN +/* END BACKWARDS COMPATIBILITY */ + +/*! + * @internal + * @brief + * SPI function table pointer + */ +extern const SPI_FxnTable SPICC26XXDMA_fxnTable; + +/*! + * @internal + * @brief + * SPICC26XXDMA data frame size is used to determine how to configure the + * UDMA data transfers. This field is to be only used internally. + * + * - SPICC26XXDMA_8bit: txBuf and rxBuf are arrays of uint8_t elements + * - SPICC26XXDMA_16bit: txBuf and rxBuf are arrays of uint16_t elements + */ +typedef enum SPICC26XXDMA_FrameSize { + SPICC26XXDMA_8bit = 0, + SPICC26XXDMA_16bit = 1 +} SPICC26XXDMA_FrameSize; + +/*! + * @brief SPICC26XXDMA Hardware attributes + * + * These fields, with the exception of intPriority, + * are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC26xxWare these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * - driverlib/udma.h + * + * intPriority is the SPI peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * + * A sample structure is shown below: + * @code + * const SPICC26XXDMA_HWAttrsV1 spiCC26XXDMAobjects[] = { + * { + * .baseAddr = SSI0_BASE, + * .intNum = INT_SPI0, + * .intPriority = ~0, + * .swiPriority = 0, + * .powerMngrId = PERIPH_SPI0, + * .defaultTxBufValue = 0, + * .rxChannelBitMask = UDMA_CHAN_SPI0_RX, + * .txChannelBitMask = UDMA_CHAN_SPI0_TX, + * .mosiPin = Board_SPI0_MISO, + * .misoPin = Board_SPI0_MOSI, + * .clkPin = Board_SPI0_CLK, + * .csnPin = Board_SPI0_CSN + * }, + * { + * .baseAddr = SSI1_BASE, + * .intNum = INT_SPI1, + * .intPriority = ~0, + * .swiPriority = 0, + * .powerMngrId = PERIPH_SPI1, + * .defaultTxBufValue = 0, + * .rxChannelBitMask = UDMA_CHAN_SPI1_RX, + * .txChannelBitMask = UDMA_CHAN_SPI1_TX, + * .mosiPin = Board_SPI1_MISO, + * .misoPin = Board_SPI1_MOSI, + * .clkPin = Board_SPI1_CLK, + * .csnPin = Board_SPI1_CSN + * }, + * }; + * @endcode + */ +typedef struct SPICC26XXDMA_HWAttrsV1 { + /*! SPI Peripheral's base address */ + uint32_t baseAddr; + /*! SPI CC26XXDMA Peripheral's interrupt vector */ + uint8_t intNum; + /*! @brief SPI CC26XXDMA Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief SPI SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! SPI Peripheral's power manager ID */ + PowerCC26XX_Resource powerMngrId; + /*! Default TX value if txBuf == NULL */ + uint16_t defaultTxBufValue; + /*! uDMA controlTable channel index */ + uint32_t rxChannelBitMask; + /*! uDMA controlTable channel index */ + uint32_t txChannelBitMask; + /*! SPI MOSI pin */ + PIN_Id mosiPin; + /*! SPI MISO pin */ + PIN_Id misoPin; + /*! SPI CLK pin */ + PIN_Id clkPin; + /*! SPI CSN pin */ + PIN_Id csnPin; + + /*! Minimum transfer size for DMA based transfer */ + uint32_t minDmaTransferSize; +} SPICC26XXDMA_HWAttrsV1; + +/*! + * @brief SPICC26XXDMA Object + * + * The application must not access any member variables of this structure! + */ +typedef struct SPICC26XXDMA_Object { + /* SPI control variables */ + SPI_TransferMode transferMode; /*!< Blocking or Callback mode */ + unsigned int transferTimeout; /*!< Timeout for the transfer when in blocking mode */ + SPI_CallbackFxn transferCallbackFxn; /*!< Callback function pointer */ + SPI_Mode mode; /*!< Master or Slave mode */ + /*! @brief SPI bit rate in Hz. + * + * When the SPI is configured as SPI slave, the maximum bitrate is 4MHz. + * + * When the SPI is configured as SPI master, the maximum bitrate is 12MHz. + */ + unsigned int bitRate; + unsigned int dataSize; /*!< SPI data frame size in bits */ + SPI_FrameFormat frameFormat; /*!< SPI frame format */ + + /* SPI SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object handle */ + SwiP_Struct swi; /*!< Swi object */ + SemaphoreP_Struct transferComplete; /*!< Notify finished SPICC26XXDMA transfer */ + + /* SPI current transaction */ + SPI_Transaction *currentTransaction; /*!< Ptr to the current transaction*/ + size_t amtDataXferred; /*!< Number of frames transferred */ + size_t currentXferAmt; /*!< Size of current DMA transfer */ + SPICC26XXDMA_FrameSize frameSize; /*!< Data frame size variable */ + + /* Support for dynamic CSN pin allocation */ + PIN_Id csnPin; /*!< SPI CSN pin */ + + /* PIN driver state object and handle */ + PIN_State pinState; + PIN_Handle pinHandle; + + /* UDMA driver handle */ + UDMACC26XX_Handle udmaHandle; + + /* Optional slave mode features */ + bool returnPartial; /*!< Optional slave mode return partial on CSN deassert */ + + /* Scratch buffer of size uint32_t */ + uint16_t scratchBuf; + + /* SPI pre- and post notification functions */ + void *spiPreFxn; /*!< SPI pre-notification function pointer */ + void *spiPostFxn; /*!< SPI post-notification function pointer */ + Power_NotifyObj spiPreObj; /*!< SPI pre-notification object */ + Power_NotifyObj spiPostObj; /*!< SPI post-notification object */ + + volatile bool spiPowerConstraint; /*!< SPI power constraint flag, guard to avoid power constraints getting out of sync */ + + bool isOpen; /*!< Has the object been opened */ +} SPICC26XXDMA_Object, *SPICC26XXDMA_Handle; + + + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_spi_SPICC26XXDMA__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/timer/GPTimerCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/timer/GPTimerCC26XX.c new file mode 100644 index 0000000..160e2db --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/timer/GPTimerCC26XX.c @@ -0,0 +1,782 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file GPTimerCC26XX.c + * @brief CC26XX/CC13XX driver implementation for GPTimer peripheral + * + * + ******************************************************************************* + */ + + +#include +#include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_gpt.h) +#include DeviceFamily_constructPath(driverlib/timer.h) + + +/* GPTimer configuration array from application */ +extern const GPTimerCC26XX_Config GPTimerCC26XX_config[]; + +/* Register masks used by GPTimerCC26XX_resetHw */ +#define GPT_CTL_MASK (GPT_CTL_TASTALL_M | GPT_CTL_TAEVENT_M | GPT_CTL_TAPWML_M) + + +/* GPTimerCC26XX internal functions */ +static void GPTimerCC26XX_initHw(GPTimerCC26XX_Handle handle, const GPTimerCC26XX_Params *params); +static void GPTimerCC26XX_resetHw(GPTimerCC26XX_Handle handle); +static void GPTimerCC26XXThreadsafeConstraintClr(GPTimerCC26XX_Handle handle); +static void GPTimerCC26XXThreadsafeConstraintSet(GPTimerCC26XX_Handle handle); +static void GPTimerCC26XXHwiFxn(uintptr_t a0); +static void GPTimerCC26XXSetLoadMatch(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Value loadMatchVal, uint32_t regPre, uint32_t regLoadMatch); +static GPTimerCC26XX_Value GPTimerCC26XX_getTimerValue(GPTimerCC26XX_Handle handle, uint32_t reg); + +/* GPTimerCC26XX temporary internal functions. + Will be removed once they are added to driverlib + */ +static inline void TimerSetConfig(uint32_t ui32Base, uint32_t ui32Config); +static inline void TimerSetMode(uint32_t ui32Base, uint32_t timer, uint32_t mode); + + +/* Lookup table definition for interfacing driverlib and register fields. + Used to simplify code and to easily look up register fields as several fields + are not symmetric across timer A and timer B registers (interrupts & dma) + */ +typedef struct GPTimerCC26XX_LUT +{ + uint16_t map; /* Timer argument in driverlib (TIMER_A / TIMER_B) */ + uint16_t shift; /* Bit shift for registers shared between GPT_A / GPT_B */ + uint16_t offset; /* Byte offset for registers sequentially in memory map for GPT_A/GPT_B */ + uint16_t interrupts[GPT_NUM_INTS]; /* Interrupt bitfields for GPTA/B. Order must match GPTimerCC26XX_Interrupt */ +} const GPTimerCC26XX_LUT; + +/* Lookup table definition for interfacing driverlib and register fields. */ +static const GPTimerCC26XX_LUT GPT_LUT[GPT_PARTS_COUNT] = +{ + { + .map = TIMER_A, + .shift = 0, + .offset = 0, + .interrupts ={ GPT_MIS_TATOMIS, GPT_MIS_CAMMIS, GPT_MIS_CAEMIS, GPT_MIS_TAMMIS }, + }, + { + .map = TIMER_B, + .shift = 8, + .offset = 4, + .interrupts ={ GPT_MIS_TBTOMIS, GPT_MIS_CBMMIS, GPT_MIS_CBEMIS, GPT_MIS_TBMMIS }, + }, +}; + +/* Default GPTimer parameters */ +static const GPTimerCC26XX_Params GPT_DefaultParams = +{ + .width = GPT_CONFIG_32BIT, + .mode = GPT_MODE_PERIODIC, + .matchTiming = GPTimerCC26XX_SET_MATCH_NEXT_CLOCK, + .direction = GPTimerCC26XX_DIRECTION_UP, + .debugStallMode = GPTimerCC26XX_DEBUG_STALL_OFF, +}; + + +/*! + * @brief Generic bit vector to lookup table vector implementation + * + * Parses generic lookup table and checks whether inputs exists in lookup table. + * + * @param pLookup pointer to look-up table + * @param inputVector Input vector + * @param length Number of bits in lookup table + * + * @return A bit vector containing set fields in lookup table + */ +static uint16_t GPTimerCC26XXLookupMask(const uint16_t *pLookup, uint16_t inputVector, uint8_t length) +{ + uint16_t maskLookup = 0; + uint32_t i; + /* Fetch data from lookup table */ + for (i = 0; i < length; i++) + { + /* Check if current index of lookup table is in input vector */ + if (inputVector & pLookup[i]) + { + /* Add vector input to looked up mask. */ + maskLookup |= 1 << i; + } + } + return maskLookup; +} + +/*! + * @brief Generic lookup table to bit vector implementation + * + * Parses input vector and checks which input fields are set + * + * @param pLookup pointer to look-up table + * @param inputVector Input vector + * @param length Number of bits in lookup table + * + * @return A bit vector mapped from lookup table + */ +static uint16_t GPTimerCC26XXReverseLookupMask(const uint16_t *pLookup, uint16_t inputVector, uint8_t length) +{ + uint16_t revMaskLookup = 0; + uint32_t i; + for (i = 0; i < length; i++) + { + /* Check if current index is set in input vector */ + if (inputVector & (1 << i)) + { + /* Add data from lookup table */ + revMaskLookup |= pLookup[i]; + } + } + return revMaskLookup; +} + +/*! + * @brief Function to initialize the GPTimerCC26XX_Params struct to default + * values + * + * @param params An pointer to GPTimerCC26XX_Params structure for + * initialization + * + * Defaults values are: + * Timer width : 32 bits, + * Timer mode : Periodic mode counting upwards + * Timer debug stall mode: Disabled + */ +void GPTimerCC26XX_Params_init(GPTimerCC26XX_Params *params) +{ + *params = GPT_DefaultParams; +} + +/*! + * @brief This function opens the given GPTimer peripheral. It will set a + * dependency on the timer, configure the timer mode and set timer + * as open. If params is NULL default values will be used. + * + * @return A GPTimerCC26XX_Handle on success or NULL on error or if timer is + * already open. If NULL is returned further GPTimer API calls will + * result in undefined behaviour. + * + * @sa GPTimerCC26XX_close() + */ +GPTimerCC26XX_Handle GPTimerCC26XX_open(unsigned int index, const GPTimerCC26XX_Params *params) +{ + unsigned int key; + GPTimerCC26XX_Handle handle = (GPTimerCC26XX_Handle) & GPTimerCC26XX_config[index]; + + /* Get the pointer to the object and hwAttrs and timer*/ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + + + /* + * Input argument checks + */ + + /* Fail if no params supplied */ + if (params == NULL) + { + DebugP_log1("Timer:(%p): No params supplied, using default.", hwAttrs->baseAddr); + params = &GPT_DefaultParams; + } + + if (params->width == GPT_CONFIG_32BIT) + { + /* Fail if invalid combination of mode and configuration + 32-bit config are only valid for periodic / oneshot modes */ + if (params->mode != GPT_MODE_ONESHOT_UP && + params->mode != GPT_MODE_PERIODIC_UP) + { + DebugP_log1("Timer:(%p): Invalid combination of mode and configuration", hwAttrs->baseAddr); + return(NULL); + } + /* Fail if invalid combination of timer unit and configuration. + 32-bit config is only valid in combination with GPT A */ + if (handle->timerPart != GPT_A) + { + DebugP_log1("Timer:(%p): Invalid combination of configuration and timer unit", hwAttrs->baseAddr); + return(NULL); + } + } + + /* + * Check if Timer is already opened + */ + + /* Disable preemption while checking */ + key = HwiP_disable(); + + bool isOpen; + /* If trying to open a 32-bit mode timer then both A and B must be available */ + if (params->width == GPT_CONFIG_32BIT) + { + /* Timer already opened if one unit opened */ + isOpen = object->isOpen[GPT_A] | object->isOpen[GPT_B]; + } + else + { + isOpen = object->isOpen[handle->timerPart]; + } + /* Fail if corresponding timer is already open or if one of the two + units needed is taken for 32-bit mode */ + if (isOpen) + { + HwiP_restore(key); + DebugP_log2("Timer:(%p), Unit: (%u): Already in use.", hwAttrs->baseAddr, handle->timerPart); + return NULL; + } + + /* + * Open timer + */ + if (params->width == GPT_CONFIG_32BIT) + { + object->isOpen[GPT_A] = true; + object->isOpen[GPT_B] = true; + } + else + { + object->isOpen[handle->timerPart] = true; + } + /* Restore preemption again */ + HwiP_restore(key); + + /* Configure timer object */ + object->width = params->width; + + /* Register power dependency - i.e. power up and enable clock for GPTimer. + If both GPT_A and GPT_B is used then two dependencies will be set on GPTimer */ + Power_setDependency(hwAttrs->powerMngrId); + + /* Initialize HW */ + GPTimerCC26XX_initHw(handle, params); + + return handle; +} + +/*! + * @brief This function closes an opened GPTimer peripheral defined by the + * handle. It will remove the dependency on the timer and write all + * configured timer registers to its default values. Timer must be + * stopped beforing closing it. + * + * @sa GPTimerCC26XX_stop() + * @sa GPTimerCC26XX_close() + */ +void GPTimerCC26XX_close(GPTimerCC26XX_Handle handle) +{ + /* Get the pointer to the object and hwAttrs */ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + + /* Stop and reset timer */ + GPTimerCC26XX_resetHw(handle); + + /* Release dependency for timer */ + Power_releaseDependency(hwAttrs->powerMngrId); + + /* Mark the Timer unit as available */ + uint32_t key = HwiP_disable(); + + /* Close Timer(s) */ + if (object->width == GPT_CONFIG_32BIT) + { + object->isOpen[GPT_A] = false; + object->isOpen[GPT_B] = false; + } + else + { + object->isOpen[handle->timerPart] = false; + } + HwiP_restore(key); +} + +/*! + * @brief This function will start a GPTimer defined by the handle. + * @sa GPTimerCC26XX_stop() + */ +void GPTimerCC26XX_start(GPTimerCC26XX_Handle handle) +{ + /* Get the pointer to the object and hwAttrs */ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Enable timer */ + uint32_t timer = GPT_LUT[handle->timerPart].map; + TimerEnable(hwAttrs->baseAddr, timer); + + /* Set constraint to disallow standby while running */ + GPTimerCC26XXThreadsafeConstraintSet(handle); +} + +/*! + * @brief This function will stop a running GPTimer defined by the handle + * @sa GPTimerCC26XX_start() + */ +void GPTimerCC26XX_stop(GPTimerCC26XX_Handle handle) +{ + /* Get the pointer to the object and hwAttrs */ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Disable timer */ + uint32_t timer = GPT_LUT[handle->timerPart].map; + TimerDisable(hwAttrs->baseAddr, timer); + + /* Clear constraint to allow standby again */ + GPTimerCC26XXThreadsafeConstraintClr(handle); +} + +/*! + * @brief Shared code to be used by GPTimerCC26XX_setLoadValue / GPTimerCC26XX_setMatchValue + * Sets load/match values using input value and register offset for + * prescaler and load/match register + * Functions calling this should specifiy which the register offset + * within the module base to the corresponding timer A register. + */ +static void GPTimerCC26XXSetLoadMatch(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Value loadMatchVal, uint32_t regPre, uint32_t regLoadMatch) +{ + /* Get the pointer to the object and hwAttrs */ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + uint32_t offset = GPT_LUT[handle->timerPart].offset; + + /* Split value into correct timer and prescaler register for 16 bit modes. */ + if (object->width == GPT_CONFIG_16BIT) + { + /* Upper byte is used by prescaler */ + uint8_t prescaleValue = 0xFF & (loadMatchVal >> 16); + /* Discard upper byte (24 bits max) */ + loadMatchVal &= 0xFFFF; + + /* Set prescale value */ + HWREG(hwAttrs->baseAddr + offset + regPre) = prescaleValue; + } + + /* Set load / match value */ + HWREG(hwAttrs->baseAddr + offset + regLoadMatch) = loadMatchVal; +} + +/*! + * @brief Set GPTimer load value. For 32-bit configuration all 32 bits can + * be used. For split mode / 16-bit mode maximum value is 24 bits. + * Function concatenates prescaler functionality automatically + */ +void GPTimerCC26XX_setLoadValue(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Value loadValue) +{ + GPTimerCC26XXSetLoadMatch(handle, loadValue, GPT_O_TAPR, GPT_O_TAILR); +} + +/*! + * @brief Set GPTimer match value. For 32-bit configuration all 32 bits can + * be used. For split mode / 16-bit mode maximum value is 24 bits. + * Function concatenates prescaler functionality automatically + */ +void GPTimerCC26XX_setMatchValue(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Value matchValue) +{ + GPTimerCC26XXSetLoadMatch(handle, matchValue, GPT_O_TAPMR, GPT_O_TAMATCHR); +} + + +/*! + * @brief Function to set which input event edge the GPTimer capture should + * use. Applies to edge-count and edge-time modes + * be called while GPTimer is running. + */ +void GPTimerCC26XX_setCaptureEdge(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Edge event) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + uint32_t shift = GPT_LUT[handle->timerPart].shift; + + /* Disable interrupts during RMW operation */ + uint32_t key = HwiP_disable(); + + uint32_t ctl = HWREG(hwAttrs->baseAddr + GPT_O_CTL); + /* Clear old setting */ + ctl &= ~(GPT_CTL_TAEVENT_M << shift); + /* Apply new setting */ + HWREG(hwAttrs->baseAddr + GPT_O_CTL) = ctl | (event << shift); + /* Restore HW interrupts */ + HwiP_restore(key); +} + +/*! + * @brief Shared code used to retrieve timer values by + * GPTimerCC26XX_getFreeRunValue and GPTimerCC26XX_getValue + * Functions calling this should specifiy which the register offset + * within the module base to the corresponding timer A register. + */ +static GPTimerCC26XX_Value GPTimerCC26XX_getTimerValue(GPTimerCC26XX_Handle handle, uint32_t reg) +{ + /* Get the pointer to the object and hwAttrs */ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + uint32_t offset = GPT_LUT[handle->timerPart].offset; + + uint32_t value = HWREG(hwAttrs->baseAddr + offset + reg); + + /* Correct for 16-bit mode (remove bits 31:24) + Supported 16-bit modes uses prescaler as timer extension only. + In 16-bit mode, current prescaler value is found in bits 23:16 of the timer value register + */ + + if (object->width == GPT_CONFIG_16BIT) + { + /* Discard any upper byte */ + value = value & 0xFFFFFF; + } + return (GPTimerCC26XX_Value)value; +} + + +/*! + * @brief Retrieve current free-running value from GPTimer + * In 16-bit modes the function will return a 24-bit word where the + * 8-bit prescaler value is included. + */ +GPTimerCC26XX_Value GPTimerCC26XX_getFreeRunValue(GPTimerCC26XX_Handle handle) +{ + return GPTimerCC26XX_getTimerValue(handle, GPT_O_TAV); +} + +/*! + * @brief Retrieve the current value of timer + * This returns the value of the timer in all modes except for + * input edge count and input edge time mode. + * In edge count mode, this register contains the number of edges that + * have occurred. In input edge time, this register contains the + * timer value at which the last edge event took place. + * In 16-bit modes the function will return a 24-bit word where the + * 8-bit prescaler value is included. + */ +GPTimerCC26XX_Value GPTimerCC26XX_getValue(GPTimerCC26XX_Handle handle) +{ + return GPTimerCC26XX_getTimerValue(handle, GPT_O_TAR); +} + +/*! + * @brief Register interrupts for timer handle. + * This function must only be called once after opening a timer. + * Interrupts should be unregistered again before closing + * the timer resource. + */ +void GPTimerCC26XX_registerInterrupt(GPTimerCC26XX_Handle handle, GPTimerCC26XX_HwiFxn callback, GPTimerCC26XX_IntMask intMask) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + + /* Store callback function */ + object->hwiCallbackFxn[handle->timerPart] = callback; + /* Construct RTOS HWI */ + HwiP_Struct *pHwi = &object->hwi[handle->timerPart]; + HwiP_Params hp; + HwiP_Params_init(&hp); + hp.arg = (uintptr_t)handle; + hp.enableInt = true; + hp.priority = hwAttrs->intPriority; + HwiP_construct(pHwi, hwAttrs->intNum, GPTimerCC26XXHwiFxn, &hp); + + GPTimerCC26XX_enableInterrupt(handle, intMask); +} + +/*! + * @brief Destruct interrupt for timer handle. + * This function must only be called once after opening a timer and + * should not be called before calling GPTimerCC26XX_registerInterrupt + */ +void GPTimerCC26XX_unregisterInterrupt(GPTimerCC26XX_Handle handle) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + + uint32_t ui32Base = hwAttrs->baseAddr; + uint32_t timer = GPT_LUT[handle->timerPart].map; + + /* Disable all timer unit interrupts, use "timer" variable as mask */ + TimerIntDisable(ui32Base, timer); + + /* Destroy callback function */ + object->hwiCallbackFxn[handle->timerPart] = NULL; + /* Destruct HWI */ + HwiP_Struct *pHwi = &object->hwi[handle->timerPart]; + HwiP_destruct(pHwi); +} + +/*! + * @brief Enable interrupt source for current GPTimer unit. CPU interrupt + * for timer will not be enabled before calling + * GPTimerCC26XX_registerInterrupt + */ +void GPTimerCC26XX_enableInterrupt(GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask intMask) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t ui32Base = hwAttrs->baseAddr; + + /* Interrupt registers are shared by TA and TB but bit fields are not symmetric + Fetch mask from lookup table.*/ + uint32_t intMaskLookup = GPTimerCC26XXReverseLookupMask(GPT_LUT[handle->timerPart].interrupts, intMask, GPT_NUM_INTS); + + /* Enable interrupts in timer unit */ + TimerIntEnable(ui32Base, intMaskLookup); +} + +/*! + * @brief Disable interrupt source for current GPTimer unit. CPU interrupt + * for timer will not be disabled before calling GPTimerCC26XX_unregisterInterrupt + */ +void GPTimerCC26XX_disableInterrupt(GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask intMask) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t ui32Base = hwAttrs->baseAddr; + + /* Interrupt registers are shared by TA and TB but bit fields are not symmetric + Fetch mask from lookup table. */ + uint32_t intMaskLookup = GPTimerCC26XXReverseLookupMask(GPT_LUT[handle->timerPart].interrupts, intMask, GPT_NUM_INTS); + + /* Enable interrupts in timer unit */ + TimerIntDisable(ui32Base, intMaskLookup); +} + +static void GPTimerCC26XX_initHw(GPTimerCC26XX_Handle handle, const GPTimerCC26XX_Params *params) +{ + /* Get the pointer to the object and hwAttrs */ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object const *object = handle->object; + + TimerSetConfig(hwAttrs->baseAddr, object->width); + uint32_t timer = GPT_LUT[handle->timerPart].map; + + uint32_t mode = (uint32_t) params->mode; + + if (params->matchTiming == GPTimerCC26XX_SET_MATCH_ON_TIMEOUT) + { + /* Same bit position is also valid for timer B in the TBMR register. */ + mode |= GPT_TAMR_TAMRSU_TOUPDATE; + } + else + { + /* Same bit position is also valid for timer B in the TBMR register. */ + mode |= GPT_TAMR_TAMRSU_CYCLEUPDATE; + } + + if (params->direction == GPTimerCC26XX_DIRECTION_UP) + { + /* Same bit position also valid for timer B in the TBMR register. */ + mode |= GPT_TAMR_TACDIR_UP; + } + else + { + /* Same bit position also valid for timer B in the TBMR register. */ + mode |= GPT_TAMR_TACDIR_DOWN; + } + + TimerSetMode(hwAttrs->baseAddr, timer, mode); + + GPTimerCC26XX_configureDebugStall(handle, params->debugStallMode); +} + +/*! + * @brief Restore GPTimer unit registers back to reset values. + * Needed since module does not have reset functionality. + */ +static void GPTimerCC26XX_resetHw(GPTimerCC26XX_Handle handle) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t ui32Base = hwAttrs->baseAddr; + + uint32_t timer = GPT_LUT[handle->timerPart].map; + uint32_t regMask; + /* Some registers are shared by TA and TB. + Shift bit fields by 1 byte for timer B. */ + uint32_t shift = GPT_LUT[handle->timerPart].shift; + /* Some registers are offset by one word (4 bytes) for Timer B. */ + uint32_t offset = GPT_LUT[handle->timerPart].offset; + + /* Disable timer before configuring */ + TimerDisable(ui32Base, timer); + + /* Reset control regs for timer N (CTL) */ + regMask = ~(GPT_CTL_MASK << shift); + HWREG(ui32Base + GPT_O_CTL) &= regMask; + + /* Reset interrupt mask for Timer N (IMR). + Equivalent to TimerIntDisable(ui32Base, regMask) */ + regMask = 0; + uint8_t i; + for (i = 0; i < GPT_NUM_INTS; i++) + { + regMask |= (uint32_t)(GPT_LUT[handle->timerPart].interrupts[i]); + } + HWREG(ui32Base + GPT_O_IMR) &= ~regMask; + + + /* Clear interrupts for Timer N ( ICLR). Same regMask as GPT_O_IMR. + Equivalent to TimerIntClear(ui32Base, regMask) */ + HWREG(ui32Base + GPT_O_ICLR) = regMask; + + /* Reset load register for timer N. + Equivalent to TimerLoadSet(ui32Base, timer, 0xFFFFFFF) */ + HWREG(ui32Base + offset + GPT_O_TAILR) = 0xFFFFFFFF; + + /* Reset match register for timer N. + Equivalent to TimerMatchSet(ui32Base, timer, 0xFFFFFFFF) */ + HWREG(ui32Base + offset + GPT_O_TAMATCHR) = 0xFFFFFFFF; + + /* Reset pre-scale register for timer N. + Equivalent to TimerPrescaleSet(ui32Base, timer, 0) */ + HWREG(ui32Base + offset + GPT_O_TAPR) = 0; + + /* Reset pre-scale match register for timer N. + Equivalent to TimerPrescaleMatchSet(ui32Base, timer, 0) */ + HWREG(ui32Base + offset + GPT_O_TAPMR) = 0; +} + + +/*! + * @brief GPTimer interrupt handler - Clears corresponding interrupt(s) + * and calls callback function with handle and bitmask argument + * as given in implementation header file. + */ +static void GPTimerCC26XXHwiFxn(uintptr_t a0) +{ + GPTimerCC26XX_Handle handle = (GPTimerCC26XX_Handle)a0; + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + + GPTimerCC26XX_HwiFxn callbackFxn = object->hwiCallbackFxn[handle->timerPart]; + uint32_t timer = GPT_LUT[handle->timerPart].map; + + /* Full width raw interrupt status */ + uint32_t interrupts = HWREG(hwAttrs->baseAddr + GPT_O_MIS); + /* Interrupt mask to clear (byte 0 or 1) */ + uint32_t interruptClr = timer & interrupts; + /* Clear interrupts */ + HWREG(hwAttrs->baseAddr + GPT_O_ICLR) = interruptClr; + + /* Interrupt registers are shared by TA and TB but bit fields are not + symmetric. Need to go through LUT and fetch bit vector based on interrupts + */ + uint16_t intMaskLookup = GPTimerCC26XXLookupMask(GPT_LUT[handle->timerPart].interrupts, interrupts, GPT_NUM_INTS); + + if (callbackFxn != NULL) + { + callbackFxn(handle, intMaskLookup); + } +} + +/*! + * @brief Set Standby constraint while using timer to avoid TI RTOS + * going into standby when timer is running. As constraints are + * counting, store constraint status and access atomically and only + * once per timer resource. + */ +static inline void GPTimerCC26XXThreadsafeConstraintSet(GPTimerCC26XX_Handle handle) +{ + GPTimerCC26XX_Object *object = handle->object; + + uint32_t key = HwiP_disable(); + /* Only set if not already set */ + if (object->powerConstraint[handle->timerPart]) + { + HwiP_restore(key); + return; + } + object->powerConstraint[handle->timerPart] = true; + HwiP_restore(key); + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/*! + * @brief Clear Standby constraint while using timer to avoid TI RTOS + * going into standby when timer is running. As constraints are + * counting, store constraint status and access atomically and only + * once per timer resource. + */ +static inline void GPTimerCC26XXThreadsafeConstraintClr(GPTimerCC26XX_Handle handle) +{ + GPTimerCC26XX_Object *object = handle->object; + + uint32_t key = HwiP_disable(); + /* Only release if constraint set */ + if (!object->powerConstraint[handle->timerPart]) + { + HwiP_restore(key); + return; + } + object->powerConstraint[handle->timerPart] = false; + HwiP_restore(key); + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/*! + * @brief Configure debug stall mode in timer. When enabled the timer will + * stop when the CPU is halted by the debugger. + */ +void GPTimerCC26XX_configureDebugStall(GPTimerCC26XX_Handle handle, GPTimerCC26XX_DebugMode mode) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t timer = GPT_LUT[handle->timerPart].map; + TimerStallControl(hwAttrs->baseAddr, timer, mode); +} + +/*! + * @brief Set timer configuration. Will be moved to driverlib. + */ +static inline void TimerSetConfig(uint32_t ui32Base, uint32_t ui32Config) +{ + HWREG(ui32Base + GPT_O_CFG) = ui32Config; +} +/*! + * @brief Set timer mode. Will be moved to driverlib. + */ +static inline void TimerSetMode(uint32_t ui32Base, uint32_t timer, uint32_t mode) +{ + uint32_t addr = ui32Base; + + if (timer == TIMER_B) + { + addr += GPT_O_TBMR; + } + else + { + addr += GPT_O_TAMR; + } + HWREG(addr) = mode; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/timer/GPTimerCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/timer/GPTimerCC26XX.h new file mode 100644 index 0000000..723a2f4 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/timer/GPTimerCC26XX.h @@ -0,0 +1,686 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file GPTimerCC26XX.h + * @brief GPTimer driver implementation for CC26XX/CC13XX + * + * # Overview # + * This TI RTOS driver can be used to configure GPTimer modules to the modes + * supported by the GPTimer. The board file or application must define the device + * specific configuration before using the driver. + * # Configuration # + * The GPTimer can be used in two different configurations. In 32-bit mode the + * timer will act as a full-width timer and is controlled using the Timer A unit. + * In split (16-bit) mode the timer is split into 2x 16-bit timers. In 16-bit mode + * a prescaler is available for each timer unit, effectively increasing the + * resolution in this mode to 24-bit. All supported modes by driver in split + * configuration uses prescaler as timer extension. + * + * # Modes # + * The GPTimer driver supports the following timer modes: + * - Oneshot mode counting upwards. When timer reaches load value, the timer + * is stopped automatically. Supported in both 16 and 32-bit configuration. + * - Periodic mode counting upwards. When timer reaches load value it wraps and + * starts counting from 0 again. Supported in both 16 and 32-bit configuration. + * - Input edge-count. Timer counts the number of events on its input capture port + * upwards from 0. Events can be rising-edge, falling-edge, or both. + * Supported only in 16-bit mode. + * - Input edge-time. Timer counts upwards from 0 and captures the time of an + * event on its input capture port. This can be used to count the time + * between events. Events can be rising-edge, falling-edge or both. + * Supported only in 16-bit mode. + * - PWM mode. Timer counts downwards from load value. CCP is set to 1 when + * reaching timeout (0) and toggles when reaching match value. + * + * # Power Management # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * The GPTimerCC26XX driver will set constraints on disallowed power modes when + * needed, removing the need for the application to handle this. + * The following statements are valid: + * - After GPTimerCC26XX_open(): + * The device is still allowed to enter Standby. When the device is + * active the corresponding GPTimer peripheral will be enabled and clocked. + * - After GPTimerCC26XX_start(): + * The device will only go to Idle power mode since the high-frequency + * clock is needed for timer operation. + * - After GPTimerCC26XX_stop(): + * Conditions are equal as for after GPTimerCC26XX_open + * - After GPTimerCC26XX_close(): + * The underlying GPTimer is turned off and the device is allowed to go + * to standby. + * + * # Accuracy # + * The GPTimer clock is dependent on the MCU system clock. + * If very high-accuracy outputs are needed, the application should request + * using the external HF crystal: + * @code + * #include + * #include + * Power_setDependency(XOSC_HF); + * @endcode + * + * # Limitations # + * - DMA usage is not supported + * - Timer synchronization is not supported + * - Down counting modes (except for PWM) are not supported by driver + * + * # GPTimerCC26XX usage # + * + * ## Periodic timer ## + * The example below will generate an interrupt using the GPTimer every 1 ms. + * + * @code + * GPTimerCC26XX_Handle hTimer; + * void timerCallback(GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask interruptMask) { + * // interrupt callback code goes here. Minimize processing in interrupt. + * } + * + * void taskFxn(uintptr_t a0, uintptr_t a1) { + * GPTimerCC26XX_Params params; + * GPTimerCC26XX_Params_init(¶ms); + * params.width = GPT_CONFIG_16BIT; + * params.mode = GPT_MODE_PERIODIC; + * params.direction = GPTimerCC26XX_DIRECTION_UP; + * params.debugStallMode = GPTimerCC26XX_DEBUG_STALL_OFF; + * hTimer = GPTimerCC26XX_open(CC2650_GPTIMER0A, ¶ms); + * if(hTimer == NULL) { + * Log_error0("Failed to open GPTimer"); + * Task_exit(); + * } + * + * Types_FreqHz freq; + * BIOS_getCpuFreq(&freq); + * GPTimerCC26XX_Value loadVal = freq.lo / 1000 - 1; //47999 + * GPTimerCC26XX_setLoadValue(hTimer, loadVal); + * GPTimerCC26XX_registerInterrupt(hTimer, timerCallback, GPT_INT_TIMEOUT); + * + * GPTimerCC26XX_start(hTimer); + * + * while(1) { + * Task_sleep(BIOS_WAIT_FOREVER); + * } + * } + * @endcode + * + * + * ## PWM output ## + * See the PWM2TimerCC26XX driver + ******************************************************************************* + */ + +#ifndef ti_drivers_timer_GPTIMERCC26XX__include +#define ti_drivers_timer_GPTIMERCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_gpt.h) +#include DeviceFamily_constructPath(driverlib/event.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/timer.h) + +/* Backwards compatibility - old timer modes. New behaviour is count-up by default but configurable. */ +#define GPT_MODE_ONESHOT_UP GPT_MODE_ONESHOT +#define GPT_MODE_PERIODIC_UP GPT_MODE_PERIODIC +#define GPT_MODE_EDGE_COUNT_UP GPT_MODE_EDGE_COUNT +#define GPT_MODE_EDGE_TIME_UP GPT_MODE_EDGE_TIME + +/*! + * @brief + * Definitions for specifying the GPTimer configuration (width) + */ +typedef enum GPTimerCC26XX_Width +{ + GPT_CONFIG_32BIT = GPT_CFG_CFG_32BIT_TIMER, + GPT_CONFIG_16BIT = GPT_CFG_CFG_16BIT_TIMER, +} GPTimerCC26XX_Width; + +/*! + * @brief + * Definitions for supported GPTimer modes. Driver code assumes only modes + * using prescaler as timer extension in 16-bit configuration are used. + * Therefore new modes must not be added to the below description without + * also updating driver. + * + */ +typedef enum GPTimerCC26XX_Mode +{ + /* One shot mode counting upwards */ + GPT_MODE_ONESHOT = GPT_TAMR_TAMR_ONE_SHOT | GPT_TAMR_TAMIE, + /* Periodic mode counting upwards */ + GPT_MODE_PERIODIC = GPT_TAMR_TAMR_PERIODIC | GPT_TAMR_TAMIE, + /* Edge count mode counting upwards */ + GPT_MODE_EDGE_COUNT = GPT_TAMR_TAMR_CAPTURE | GPT_TAMR_TACM_EDGCNT, + /* Edge count mode counting upwards */ + GPT_MODE_EDGE_TIME = GPT_TAMR_TAMR_CAPTURE | GPT_TAMR_TACM_EDGTIME, + /* PWM mode counting downwards. This specific configuration is used by the + PWM2TimerCC26XX driver */ + GPT_MODE_PWM = GPT_TAMR_TAMR_PERIODIC | GPT_TAMR_TAPWMIE_EN | \ + GPT_TAMR_TAAMS_PWM | GPT_TAMR_TACM_EDGCNT | \ + GPT_TAMR_TAPLO_CCP_ON_TO, +} GPTimerCC26XX_Mode; + +/*! + * @brief + * Definitions for supported GPTimer interrupts. GPTimerCC26XX_IntMask + * arguments should be a bit vector containing these definitions. + * See description in Technical Reference + */ +typedef enum GPTimerCC26XX_Interrupt +{ + GPT_INT_TIMEOUT = 1 << 0, + GPT_INT_CAPTURE_MATCH = 1 << 1, + GPT_INT_CAPTURE = 1 << 2, + GPT_INT_MATCH = 1 << 3, +} GPTimerCC26XX_Interrupt; + +/* Number of entries in GPTimerCC26XX_Interrupt */ +#define GPT_NUM_INTS 4 + +/*! + * @brief + * Definitions for GPTimer parts (Timer A / Timer B). + * Used in GPTimer configuration structure GPTimerCC26XX_config to + * configure the corresponding timer unit. + */ +typedef enum GPTimerCC26XX_Part +{ + GPT_A = 0, + GPT_B, +} GPTimerCC26XX_Part; + +#define GPT_PARTS_COUNT 2 + +/*! + * @brief + * Definitions for input / output ports in IO controller to connect GPTimer + * to a pin. Used in gptimerCC26xxHWAttrs for static timer configuration + * PIN driver is used to mux a pin to the timer. + * @sa PINCC26XX_setMux + * @sa GPTimerCC26XX_getPinMux + */ +typedef enum GPTimerCC26XX_PinMux +{ + GPT_PIN_0A = IOC_PORT_MCU_PORT_EVENT0, + GPT_PIN_0B = IOC_PORT_MCU_PORT_EVENT1, + GPT_PIN_1A = IOC_PORT_MCU_PORT_EVENT2, + GPT_PIN_1B = IOC_PORT_MCU_PORT_EVENT3, + GPT_PIN_2A = IOC_PORT_MCU_PORT_EVENT4, + GPT_PIN_2B = IOC_PORT_MCU_PORT_EVENT5, + GPT_PIN_3A = IOC_PORT_MCU_PORT_EVENT6, + GPT_PIN_3B = IOC_PORT_MCU_PORT_EVENT7, +} GPTimerCC26XX_PinMux; + +/*! + * @brief + * Definitions for controlling timer debug stall mode + */ +typedef enum GPTimerCC26XX_DebugMode +{ + GPTimerCC26XX_DEBUG_STALL_OFF = 0, + GPTimerCC26XX_DEBUG_STALL_ON, +} GPTimerCC26XX_DebugMode; + +/*! + * @brief + * Definitions for controlling timer counting direction. + * Setting the Direction for PWM operation has no effect (always counts down). + */ +typedef enum GPTimerCC26XX_Direction +{ + GPTimerCC26XX_DIRECTION_DOWN = 0, + GPTimerCC26XX_DIRECTION_UP, +} GPTimerCC26XX_Direction; + +/*! + * @brief + * Definitions for new value loading behaviour. + * + * If set to NEXT_CLOCK, then the new match value is updated immediately. + * If set to ON_TIMEOUT the new match will only be applied to the next timer cycle. + * + * Only match setting is affected by this option. Load setting is always applied immediately. + */ +typedef enum GPTimerCC26XX_SetMatchTiming +{ + GPTimerCC26XX_SET_MATCH_NEXT_CLOCK = 0, + GPTimerCC26XX_SET_MATCH_ON_TIMEOUT, +} GPTimerCC26XX_SetMatchTiming; + +/*! + * @brief + * Definitions for controlling edges used for timer capture. + * Used in GPTimer edge-time and edge-count modes. + */ +typedef enum GPTimerCC26XX_Edge +{ + GPTimerCC26XX_POS_EDGE = GPT_CTL_TAEVENT_POS, + GPTimerCC26XX_NEG_EDGE = GPT_CTL_TAEVENT_NEG, + GPTimerCC26XX_BOTH_EDGES = GPT_CTL_TAEVENT_BOTH, +} GPTimerCC26XX_Edge; + + +/* Forward declaration of GPTimer configuration */ +typedef struct GPTimerCC26XX_Config GPTimerCC26XX_Config; + +/* GPTimer handle is pointer to configuration structure */ +typedef GPTimerCC26XX_Config * GPTimerCC26XX_Handle; + +/* Interrupt bit vector. See GPTimerCC26XX_Interrupt for available interrupts */ +typedef uint16_t GPTimerCC26XX_IntMask; + +/* Timer value */ +typedef uint32_t GPTimerCC26XX_Value; + +/* Function prototype for interrupt callbacks */ +typedef void (*GPTimerCC26XX_HwiFxn) (GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask interruptMask); + +/*! + * @brief GPTimer26XX Hardware attributes + * + * These fields are used by the driver to set up underlying GPTimer + * driver statically. A sample structure is shown below: + * + * @code + * // GPTimer hardware attributes, one per timer unit (Timer 0A, 0B, 1A, 1B..) + * const GPTimerCC26XX_HWAttrs gptimerCC26xxHWAttrs[CC2650_GPTIMERPARTSCOUNT] = { + * {.baseAddr = GPT0_BASE, .intNum = INT_TIMER0A, .powerMngrId = PERIPH_GPT0, .pinMux = GPT_PIN_0A, }, + * {.baseAddr = GPT0_BASE, .intNum = INT_TIMER0B, .powerMngrId = PERIPH_GPT0, .pinMux = GPT_PIN_0B, }, + * {.baseAddr = GPT1_BASE, .intNum = INT_TIMER1A, .powerMngrId = PERIPH_GPT1, .pinMux = GPT_PIN_1A, }, + * {.baseAddr = GPT1_BASE, .intNum = INT_TIMER1B, .powerMngrId = PERIPH_GPT1, .pinMux = GPT_PIN_1B, }, + * {.baseAddr = GPT2_BASE, .intNum = INT_TIMER2A, .powerMngrId = PERIPH_GPT2, .pinMux = GPT_PIN_2A, }, + * {.baseAddr = GPT2_BASE, .intNum = INT_TIMER2B, .powerMngrId = PERIPH_GPT2, .pinMux = GPT_PIN_2B, }, + * {.baseAddr = GPT3_BASE, .intNum = INT_TIMER3A, .powerMngrId = PERIPH_GPT3, .pinMux = GPT_PIN_3A, }, + * {.baseAddr = GPT3_BASE, .intNum = INT_TIMER3B, .powerMngrId = PERIPH_GPT3, .pinMux = GPT_PIN_3B, }, + * }; + * @endcode + */ +typedef struct GPTimerCC26XX_HWAttrs +{ + /*! GPTimer peripheral base address */ + uint32_t baseAddr; + /*! GPTimer peripheral interrupt vector */ + uint8_t intNum; + /*! GPTimer peripheral's interrupt priority. + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + (7 << 5) will apply the lowest priority. + (1 << 5) will apply the highest priority. + Setting the priority to 0 is not supported by this driver. + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! GPTimer peripheral's power manager ID */ + uint8_t powerMngrId; + /*! GPTimer half timer unit */ + GPTimerCC26XX_Part timer; + /*! PIN driver MUX */ + GPTimerCC26XX_PinMux pinMux; +} GPTimerCC26XX_HWAttrs; + +/*! + * @brief GPTimer26XX Object + * + * These fields are used by the driver to store and modify GPTimer configuration + * during run-time. + * The application must not edit any member variables of this structure. + * Appplications should also not access member variables of this structure + * as backwards compatibility is not guaranteed. An example structure is shown + * below: + * @code + * // GPTimer objects, one per full-width timer (A+B) (Timer 0, Timer 1..) + * GPTimerCC26XX_Object gptimerCC26XXObjects[CC2650_GPTIMERCOUNT]; + * @endcode + */ +typedef struct GPTimerCC26XX_Object +{ + GPTimerCC26XX_Width width; /*!< Timer width configuration (16/32bit)*/ + bool isOpen[GPT_PARTS_COUNT]; /*!< Object is opened flag */ + HwiP_Struct hwi[GPT_PARTS_COUNT]; /*!< Hardware interrupt struct */ + GPTimerCC26XX_HwiFxn hwiCallbackFxn[GPT_PARTS_COUNT]; /*!< Hardware interrupt callback function */ + volatile bool powerConstraint[GPT_PARTS_COUNT]; /*!< Standby power constraint flag */ +} GPTimerCC26XX_Object; + + +/*! + * @brief GPTimer Global configuration + * + * The GPTimerCC26XX_Config structure contains a set of pointers + * used to characterize the GPTimer driver implementation. + * An example structure is shown below: + * @code + * // GPTimer configuration (used as GPTimer_Handle by driver and application) + * const GPTimerCC26XX_Config GPTimerCC26XX_config[CC2650_GPTIMERPARTSCOUNT] = { + * { &gptimerCC26XXObjects[0], &gptimerCC26xxHWAttrs[0], GPT_A}, + * { &gptimerCC26XXObjects[0], &gptimerCC26xxHWAttrs[1], GPT_B}, + * { &gptimerCC26XXObjects[1], &gptimerCC26xxHWAttrs[2], GPT_A}, + * { &gptimerCC26XXObjects[1], &gptimerCC26xxHWAttrs[3], GPT_B}, + * { &gptimerCC26XXObjects[2], &gptimerCC26xxHWAttrs[4], GPT_A}, + * { &gptimerCC26XXObjects[2], &gptimerCC26xxHWAttrs[5], GPT_B}, + * { &gptimerCC26XXObjects[3], &gptimerCC26xxHWAttrs[6], GPT_A}, + * { &gptimerCC26XXObjects[3], &gptimerCC26xxHWAttrs[7], GPT_B}, + * }; + * @endcode + */ +struct GPTimerCC26XX_Config +{ + GPTimerCC26XX_Object *object; + const GPTimerCC26XX_HWAttrs *hwAttrs; + GPTimerCC26XX_Part timerPart; +}; + +/*! + * @brief GPTimerCC26XX Parameters + * + * GPTimer parameters are used to with the GPTimerCC26XX_open() call. + * Default values for these parameters are set using GPTimerCC26XX_Params_init(). + * + * @sa GPTimerCC26XX_Params_init() + */ +typedef struct GPTimerCC26XX_Params +{ + GPTimerCC26XX_Width width; /*!< Timer configuration (32/16-bit) */ + GPTimerCC26XX_Mode mode; /*!< Timer mode */ + GPTimerCC26XX_SetMatchTiming matchTiming; /*!< Set new match values on next timeout or next cycle */ + GPTimerCC26XX_Direction direction; /*!< Count up or down */ + GPTimerCC26XX_DebugMode debugStallMode; /*!< Timer debug stall mode */ +} GPTimerCC26XX_Params; + + +/*! + * @brief Function to initialize the GPTimerCC26XX_Params struct to + * its default values + * + * @param params An pointer to GPTimerCC26XX_Params structure for + * initialization + * + * Defaults values are: + * - 32-bit configuration + * - Periodic mode counting upwards + * - Debug stall mode disabled + */ +extern void GPTimerCC26XX_Params_init(GPTimerCC26XX_Params *params); + +/*! + * @brief This function opens a given GPTimer peripheral. Will set dependency + * on timer and configure it into specified mode. + * + * @param index Logical peripheral number for the GPTimer indexed into + * the GPTimerCC26XX_config table + * + * @param params Pointer to a parameter block. If NULL, it will use + * default values. + * + * @return A GPTimerCC26XX_Handle on success or a NULL on an error or if it has been + * opened already. If NULL is returned, further GPTimerCC26XX API calls will + * result in undefined behaviour. + * + * @sa GPTimerCC26XX_close() + */ +extern GPTimerCC26XX_Handle GPTimerCC26XX_open(unsigned int index, const GPTimerCC26XX_Params *params); + +/*! + * @brief Function to close a GPTimer peripheral specified by the GPTimer handle. + * Closing timer will releae dependency on timer and clear configuration + * + * @pre GPTimerCC26XX_open() has to be called first. + * @pre GPTimerCC26XX_stop() should to be called first if GPTimer is started + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open() + * + * @sa GPTimerCC26XX_open() + * @sa GPTimerCC26XX_start() + * @sa GPTimerCC26XX_stop() + */ +extern void GPTimerCC26XX_close(GPTimerCC26XX_Handle handle); + +/*! + * @brief Function to start the specified GPTimer with current settings + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open() + * + * @sa GPTimerCC26XX_open() + * @sa GPTimerCC26XX_stop() + */ +extern void GPTimerCC26XX_start(GPTimerCC26XX_Handle handle); + +/*! + * @brief Function to stop the specified GPTimer. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open() + * + * @sa GPTimerCC26XX_open() + * @sa GPTimerCC26XX_start() + */ +extern void GPTimerCC26XX_stop(GPTimerCC26XX_Handle handle); + +/*! + * @brief Function to set load value of the specified GPTimer. Function can + * be called while GPTimer is running. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param loadValue Load value to set the GPTimer to. + * + * @sa GPTimerCC26XX_open() + */ +extern void GPTimerCC26XX_setLoadValue(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Value loadValue); + +/*! + * @brief Function to set match value of the specified GPTimer. Function can + * be called while GPTimer is running. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param matchValue Match value to set the GPTimer to. + * + * @sa GPTimerCC26XX_open() + */ +extern void GPTimerCC26XX_setMatchValue(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Value matchValue); + + +/*! + * @brief Function to set which input edge the GPTimer capture should + * use. Applies to edge-count and edge-time modes + * Function can be called while GPTimer is running. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param edge The edge that should trigger a capture + * + * @sa GPTimerCC26XX_open() + */ +extern void GPTimerCC26XX_setCaptureEdge(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Edge edge); + +/*! + * @brief Function to retrieve the current free-running value of timer + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * + * @return Current free-running timer value for all modes + * + * @sa GPTimerCC26XX_open() + */ +extern GPTimerCC26XX_Value GPTimerCC26XX_getFreeRunValue(GPTimerCC26XX_Handle handle); + +/*! + * @brief Function to retrieve the current value of timer + * This returns the value of the timer in all modes except for + * input edge count and input edge time mode. + * In edge count mode, this register contains the number of edges that + * have occurred. In input edge time, this register contains the + * timer value at which the last edge event took place. + * + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * + * @return Current free-running timer value for all modes + * + * @sa GPTimerCC26XX_open() + */ +extern GPTimerCC26XX_Value GPTimerCC26XX_getValue(GPTimerCC26XX_Handle handle); + + +/*! + * @brief Function to register a CPU interrupt for a given timer handle and + * enable a set of timer interrupt sources. The interrupt to the CPU + * will be a bitwise OR of the enabled interrupt sources. + * When an interrupt occurs, the driver will clear the + * interrupt source and call the application provided callback. + * The callback is executed in HW interrupt context and processing in + * callback should be minimized. + * + * Interrupt sources can also be individually disabled and enabled by + * using GPTimerCC26XX_enableInterrupt / GPTimerCC26XX_disableInterrupt. + * + * This function should only be called once for a handle after opening + * the timer. + * If closing a GPTimer, interrupts for the timer should be + * unregistered first using GPTimerCC26XX_unregisterInterrupt. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param callback An application provided callback function + * @param intMask A bit vector mask containing values from GPTimerCC26XX_Interrupt + * + * @sa GPTimerCC26XX_open + * @sa GPTimerCC26XX_enableInterrupt + * @sa GPTimerCC26XX_disableInterrupt + */ +extern void GPTimerCC26XX_registerInterrupt(GPTimerCC26XX_Handle handle, GPTimerCC26XX_HwiFxn callback, GPTimerCC26XX_IntMask intMask); + +/*! + * @brief Function to disable a CPU interrupt for a given timer handle and + * disable all interrupt sources for corresponding GPTimer unit. + * + * This function should only be called once for a handle after opening + * the timer and registering the interrupt. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * @pre GPTimerCC26XX_registerInterrupt() has to be called first + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * + * @sa GPTimerCC26XX_open + * @sa GPTimerCC26XX_registerInterrupt + */ +extern void GPTimerCC26XX_unregisterInterrupt(GPTimerCC26XX_Handle handle); + +/*! + * @brief Function to enable a set of GPTimer interrupt sources. + * The interrupt to the CPU must be enabled using + * GPTimerCC26XX_registerInterrupt. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param interruptMask A bit vector mask containing values from GPTimerCC26XX_Interrupt + * + * @sa GPTimerCC26XX_open + * @sa GPTimerCC26XX_disableInterrupt + */ +extern void GPTimerCC26XX_enableInterrupt(GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask interruptMask); +/*! + * @brief Function to disable a set of GPTimer interrupt sources. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param interruptMask A bit vector mask containing values from GPTimerCC26XX_Interrupt + * + * @sa GPTimerCC26XX_open + * @sa GPTimerCC26XX_enableInterrupt + */ +extern void GPTimerCC26XX_disableInterrupt(GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask interruptMask); + +/*! + * @brief Function to control timer debug stall mode. + * When enabled, the timer will stop when the debugger halts the CPU. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param mode Configuration for debug stall mode (enable/disable) + * + * @sa GPTimerCC26XX_open + */ +extern void GPTimerCC26XX_configureDebugStall(GPTimerCC26XX_Handle handle, GPTimerCC26XX_DebugMode mode); + +/*! + * @brief Function to return the PIN mux used by the GPTimer identified by + * handle. This is used to connect a GPTimer capture/compare port to + * a device DIO using PINCC26XX_setMux. + * This is typically used in PWM mode and Timer Edge-Count / Edge-Time + * modes. + * Function assumes correct pinMux is set up in device specific + * GPTimerCC26XX_HWAttrs. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * + * @sa GPTimerCC26XX_open + */ +static inline GPTimerCC26XX_PinMux GPTimerCC26XX_getPinMux(GPTimerCC26XX_Handle handle) +{ + return handle->hwAttrs->pinMux; +} + + +#ifdef __cplusplus +} +#endif +#endif /* ti_drivers_timer_GPTIMERCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/trng/TRNGCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/trng/TRNGCC26XX.c new file mode 100644 index 0000000..9875046 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/trng/TRNGCC26XX.c @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/trng.h) + +/* Macros */ +#define MAX(x,y) (((x) > (y)) ? (x) : (y)) +#define MIN(x,y) (((x) < (y)) ? (x) : (y)) + +/* Forward declarations */ +static void TRNGCC26XX_basicHwiFxn (uintptr_t arg0); +static int_fast16_t TRNGCC26XX_waitForAccess(TRNG_Handle handle); +static int_fast16_t TRNGCC26XX_waitForResult(TRNG_Handle handle); +static void TRNGCC26XX_copyEntropy(uint32_t interruptStatus, TRNGCC26XX_Object *object); +static void TRNG_restartFRO(uint32_t interruptStatus); + +/* Extern globals */ +extern const TRNG_Config TRNG_config[]; +extern const uint_least8_t TRNG_count; + +/* TRNG driver semaphore used to synchronize accesses to the TRNG module */ +static SemaphoreP_Struct TRNGCC26XX_accessSemaphore; +static SemaphoreP_Struct TRNGCC26XX_operationSemaphore; + +static HwiP_Struct TRNGCC26XX_hwi; + +static bool isInitialized = false; + +static void errorSpin(uintptr_t arg) { + while(1); +} + +static void TRNGCC26XX_copyEntropy(uint32_t interruptStatus, TRNGCC26XX_Object *object) { + uint8_t tmpEntropyBuf[TRNGCC26XX_MIN_BYTES_PER_ITERATION]; + size_t bytesToCopy = 0; + + if (interruptStatus & TRNG_IRQFLAGSTAT_RDY_M) { + ((uint32_t *)tmpEntropyBuf)[0] = TRNGNumberGet(TRNG_LOW_WORD); + ((uint32_t *)tmpEntropyBuf)[1] = TRNGNumberGet(TRNG_HI_WORD); + + bytesToCopy = MIN(object->entropyRequested - object->entropyGenerated, sizeof(tmpEntropyBuf)); + + memcpy(object->entropyBuffer + object->entropyGenerated, + tmpEntropyBuf, + bytesToCopy); + + object->entropyGenerated += bytesToCopy; + } +} + +static void TRNG_restartFRO(uint32_t interruptStatus) { + if (interruptStatus & TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M) { + uint32_t froAlarmMask; + + froAlarmMask = HWREG(TRNG_BASE + TRNG_O_ALARMSTOP); + + /* Clear alarms for FROs that exhibited repeating pattern */ + HWREG(TRNG_BASE + TRNG_O_ALARMMASK) = 0; + + /* Clear alarms for FROs that stopped */ + HWREG(TRNG_BASE + TRNG_O_ALARMSTOP) = 0; + + /* De-tune the FROs that had an alarm to attempt to */ + /* break their lock-in on SCLK_HF */ + HWREG(TRNG_BASE + TRNG_O_FRODETUNE) = froAlarmMask; + + /* Re-enable the FROs */ + HWREG(TRNG_BASE + TRNG_O_FROEN) |= froAlarmMask; + } +} + +/* + * ======== TRNGCC26XX_basicHwiFxn ======== + */ +static void TRNGCC26XX_basicHwiFxn (uintptr_t arg0) { + TRNGCC26XX_Object *object = ((TRNG_Handle)arg0)->object; + uint32_t interruptStatus; + + interruptStatus = TRNGStatusGet(); + TRNGIntClear(TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN); + + TRNGCC26XX_copyEntropy(interruptStatus, object); + + TRNG_restartFRO(interruptStatus); + + if (object->entropyGenerated >= object->entropyRequested) { + + TRNGDisable(); + + object->returnStatus = TRNG_STATUS_SUCCESS; + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&TRNGCC26XX_accessSemaphore); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* This function is only ever registered when in TRNG_RETURN_BEHAVIOR_BLOCKING + * or TRNG_RETURN_BEHAVIOR_POLLING. + */ + if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_BLOCKING) { + SemaphoreP_post(&TRNGCC26XX_operationSemaphore); + } + else if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_CALLBACK) { + object->callbackFxn((TRNG_Handle)arg0, + object->returnStatus, + object->entropyKey); + } + } +} + +/* + * ======== TRNG_init ======== + */ +void TRNG_init(void) { + uint_fast8_t key; + + key = HwiP_disable(); + + if (!isInitialized) { + /* Construct the common Hwi with a dummy ISR function. This should not matter as the function is set + * whenever we start an operation after pending on TRNGCC26XX_accessSemaphore + */ + HwiP_construct(&(TRNGCC26XX_hwi), INT_TRNG_IRQ, errorSpin, NULL); + + SemaphoreP_constructBinary(&TRNGCC26XX_accessSemaphore, 1); + SemaphoreP_constructBinary(&TRNGCC26XX_operationSemaphore, 0); + + isInitialized = true; + } + + HwiP_restore(key); +} + +/* + * ======== TRNG_open ======== + */ +TRNG_Handle TRNG_open(uint_least8_t index, TRNG_Params *params) { + DebugP_assert(index <= TRNG_count); + + TRNG_Config *config = (TRNG_Config*)&TRNG_config[index]; + + return TRNGCC26XX_construct(config, params); +} + +/* + * ======== TRNGCC26XX_construct ======== + */ +TRNG_Handle TRNGCC26XX_construct(TRNG_Config *config, const TRNG_Params *params) { + TRNG_Handle handle; + TRNGCC26XX_Object *object; + TRNGCC26XX_HWAttrs const *hwAttrs; + uintptr_t key; + + handle = config; + object = handle->object; + hwAttrs = handle->hwAttrs; + + + key = HwiP_disable(); + + if (object->isOpen || !isInitialized) { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* If params are NULL, use defaults */ + if (params == NULL) { + params = (TRNG_Params *)&TRNG_defaultParams; + } + + object->returnBehavior = params->returnBehavior; + object->semaphoreTimeout = params->timeout; + object->callbackFxn = params->callbackFxn; + + if (hwAttrs->samplesPerCycle >= TRNGCC26XX_SAMPLES_PER_CYCLE_MIN && + hwAttrs->samplesPerCycle <= TRNGCC26XX_SAMPLES_PER_CYCLE_MAX) { + + object->samplesPerCycle = hwAttrs->samplesPerCycle; + + } else { + object->samplesPerCycle = TRNGCC26XX_SAMPLES_PER_CYCLE_DEFAULT; + } + + /* Set power dependency - i.e. power up and enable clock for TRNG (TRNGCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_TRNG); + + return handle; +} + +/* + * ======== TRNG_close ======== + */ +void TRNG_close(TRNG_Handle handle) { + TRNGCC26XX_Object *object; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on TRNG Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_TRNG); + + +} + +/* + * ======== TRNGCC26XX_waitForAccess ======== + */ +static int_fast16_t TRNGCC26XX_waitForAccess(TRNG_Handle handle) { + TRNGCC26XX_Object *object = handle->object; + uint32_t timeout; + + /* Set to SemaphoreP_NO_WAIT to start operations from SWI or HWI context */ + timeout = object->returnBehavior == TRNG_RETURN_BEHAVIOR_BLOCKING ? object->semaphoreTimeout : SemaphoreP_NO_WAIT; + + return SemaphoreP_pend(&TRNGCC26XX_accessSemaphore, timeout); +} + +/* + * ======== TRNGCC26XX_waitForResult ======== + */ +static int_fast16_t TRNGCC26XX_waitForResult(TRNG_Handle handle){ + TRNGCC26XX_Object *object = handle->object; + + if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_POLLING) { + + /* Repeat until we have generated enough entropy. */ + while(object->entropyGenerated < object->entropyRequested) { + /* Wait until the TRNG has generated 64 bits of entropy */ + do { + CPUdelay(1); + } + while(!(TRNGStatusGet() & (TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN))); + + TRNGCC26XX_basicHwiFxn((uintptr_t)handle); + } + + return object->returnStatus; + } + else if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_BLOCKING) { + + SemaphoreP_pend(&TRNGCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + return object->returnStatus; + } + else { + return TRNG_STATUS_SUCCESS; + } +} + +/* + * ======== TRNGCC26XX_setSamplesPerCycle ======== + * samplesPerCycle must be between 2^8 and 2^24 (256 and 16777216) + */ +int_fast16_t TRNGCC26XX_setSamplesPerCycle(TRNG_Handle handle, uint32_t samplesPerCycle) { + TRNGCC26XX_Object *object = handle->object; + + object->samplesPerCycle = samplesPerCycle; + return TRNG_STATUS_SUCCESS; +} + +/* + * ======== TRNG_generateEntropy ======== + */ +int_fast16_t TRNG_generateEntropy(TRNG_Handle handle, CryptoKey *entropy) { + TRNGCC26XX_Object *object = handle->object; + TRNGCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Try and obtain access to the crypto module */ + if (TRNGCC26XX_waitForAccess(handle) != SemaphoreP_OK) { + return TRNG_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->entropyGenerated = 0; + object->entropyKey = entropy; + object->entropyBuffer = entropy->u.plaintext.keyMaterial; + object->entropyRequested = entropy->u.plaintext.keyLength; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&TRNGCC26XX_hwi, TRNGCC26XX_basicHwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_TRNG_IRQ, hwAttrs->intPriority); + + if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_POLLING) { + TRNGIntDisable(TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN); + } + else { + TRNGIntEnable(TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN); + } + + /* The first argument copies arg2 when set to zero - this instructs + * the TRNG to sample exactly samplesPerCycle times. The final argument + * causes the samples to happen each clock cycle. + */ + TRNGConfigure(0, object->samplesPerCycle, 0); + TRNGEnable(); + + return TRNGCC26XX_waitForResult(handle); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/trng/TRNGCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/trng/TRNGCC26XX.h new file mode 100644 index 0000000..beb2d80 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/trng/TRNGCC26XX.h @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file TRNGCC26XX.h + * + * @brief TRNG driver implementation for the CC26XX family + * + * @warning This is a beta API. It may change in future releases. + * + * This file should only be included in the board file to fill the TRNG_config + * struct. + + * The CC26XX family has a dedicated hardware TRNG based on sampling multiple + * free running oscillators. With all FROs enabled, the TRNG hardware generates + * 64 bits of entropy approximately every 5ms. The driver implementation + * chains multiple 64-bit entropy generation operations together to generate + * an arbitrary amount of entropy. + * + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + * + */ + +#ifndef ti_drivers_TRNG_TRNGCC26XX__include +#define ti_drivers_TRNG_TRNGCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include + +#include +#include +#include + +/*! @brief Minimum random samples for each entropy generation call */ +#define TRNGCC26XX_SAMPLES_PER_CYCLE_MIN 256 +/*! @brief Default random samples for each entropy generation call + * + * Set to generate 64 bits of randomness in 5ms with all FROs active. */ +#define TRNGCC26XX_SAMPLES_PER_CYCLE_DEFAULT 240000 +/*! @brief Maximum random samples for each entropy generation call */ +#define TRNGCC26XX_SAMPLES_PER_CYCLE_MAX 16777216 +/*! @brief Minimum number of bytes provided by the TRNG hardware + * in one go. Smaller amounts can by requested in driver + * calls but the full number will always be generated. + * Part of the generated entropy will simply not be copied + * back to the target buffer if the requested length is not + * a multiple of TRNGCC26XX_MIN_BYTES_PER_ISR. + */ +#define TRNGCC26XX_MIN_BYTES_PER_ITERATION 8 + +/*! + * @brief TRNGCC26XX Hardware Attributes + * + * TRNG26X0 hardware attributes should be included in the board file + * and pointed to by the TRNG_config struct. + */ +typedef struct TRNGCC26XX_HWAttrs { + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief TRNG SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! @brief TRNG Maximum Samples per Cycle. + Changes the maximum number of randomness samples in each entropy generation cycle before dump and interrupt. + The minimum is 2^8 (256) and the maximum is 2^24 (16777216). + The default is 240000 - enough to generate 64 bits of randomness at 5MHz. + */ + uint32_t samplesPerCycle; +} TRNGCC26XX_HWAttrs; + +/*! + * @brief TRNGCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct TRNGCC26XX_Object { + bool isOpen; + TRNG_ReturnBehavior returnBehavior; + int_fast16_t returnStatus; + size_t entropyGenerated; + size_t entropyRequested; + uint32_t semaphoreTimeout; + uint8_t *entropyBuffer; + CryptoKey *entropyKey; + uint32_t samplesPerCycle; + TRNG_CallbackFxn callbackFxn; +} TRNGCC26XX_Object; + +/*! + * @brief Sets the number of entropy generation cycles before + * the results are returned. + * + * The default value is set to generate 64 bits of entropy. + * + * @pre TRNG_open() has to be called first successfully + * + * @param handle A TRNGCC26XX handle returned from TRNGCC26XX_open + * @param samplesPerCycle Number of 48MHz clock cycles to sample. Must be between 2^8 and 2^24. + * + * @sa TRNG_open() + */ +extern int_fast16_t TRNGCC26XX_setSamplesPerCycle(TRNG_Handle handle, uint32_t samplesPerCycle); + +/* + * This function exists for internal use only. It is not a + * top-level function for now. + * + * Use it like this: + * + * TRNGCC26XX_Object object = {0}; + * const TRNGCC26XX_HWAttrs hwAttrs = { + * .intPriority = 0xFF + * }; + * + * TRNG_Config config = { + * .object = &object, + * .hwAttrs = &hwAttrs + * }; + * + * TRNG_Handle handle = TRNG_construct(&config, ...); + * + */ +extern TRNG_Handle TRNGCC26XX_construct(TRNG_Config *config, const TRNG_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_TRNG_TRNGCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X0.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X0.c new file mode 100644 index 0000000..fbfe40a --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X0.c @@ -0,0 +1,1507 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/* + * By default disable both asserts and log for this module. + * This must be done before DebugP.h is included. + */ +#ifndef DebugP_ASSERT_ENABLED +#define DebugP_ASSERT_ENABLED 0 +#endif +#ifndef DebugP_LOG_ENABLED +#define DebugP_LOG_ENABLED 0 +#endif + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/uart.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) + +#define MIN(a,b) (((a)<(b))?(a):(b)) +#define MAX(a,b) (((a)>(b))?(a):(b)) +#define UNIT_DIV_ROUNDUP(x,d) ((x + ((d) - 1)) / (d)) + +/* Size of the TX and RX FIFOs is 32 items */ +#define FIFO_SIZE 32 + +#define READTIMEDOUT 0x10 +#define UART_BE_PE_FE 0x700 /* Break, parity, or framing error */ + +#define UARTCC26X0_RXERROR (UART_RXERROR_OVERRUN | UART_RXERROR_BREAK | \ + UART_RXERROR_PARITY | UART_RXERROR_FRAMING) + +#define READ_DONE 0x1 /* Mask to trigger Swi on a read complete */ +#define WRITE_DONE 0x2 /* Mask to trigger Swi on a write complete */ + +/* UARTCC26X0 functions */ +void UARTCC26X0_close(UART_Handle handle); +int_fast16_t UARTCC26X0_control(UART_Handle handle, uint_fast16_t cmd, + void *arg); +void UARTCC26X0_init(UART_Handle handle); +UART_Handle UARTCC26X0_open(UART_Handle handle, UART_Params *params); +int_fast32_t UARTCC26X0_read(UART_Handle handle, void *buffer, size_t size); +int_fast32_t UARTCC26X0_readPolling(UART_Handle handle, void *buf, + size_t size); +int_fast32_t UARTCC26X0_readPollingNotImpl(UART_Handle handle, void *buf, + size_t size); +void UARTCC26X0_readCancel(UART_Handle handle); +int_fast32_t UARTCC26X0_write(UART_Handle handle, const void *buffer, + size_t size); +int_fast32_t UARTCC26X0_writePolling(UART_Handle handle, const void *buf, + size_t size); +int_fast32_t UARTCC26X0_writePollingNotImpl(UART_Handle handle, + const void *buf, size_t size); +void UARTCC26X0_writeCancel(UART_Handle handle); + +/* Static functions */ +static void UARTCC26X0_hwiIntFxn(uintptr_t arg); +static void disableRX(UART_Handle handle); +static void enableRX(UART_Handle handle); +static void initHw(UART_Handle handle); +static bool initIO(UART_Handle handle); +static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + uintptr_t clientArg); +static void readBlockingTimeout(uintptr_t arg); +static void readIsr(UART_Handle handle, uint32_t status); +static void readSemCallback(UART_Handle handle, void *buffer, size_t count); +static int readTaskBlocking(UART_Handle handle); +static int readTaskCallback(UART_Handle handle); +static int ringBufGet(UART_Handle handle, unsigned char *data); +static void startTxFifoEmptyClk(UART_Handle handle, uint32_t numDataInFifo); +static void swiCallback(uintptr_t arg0, uintptr_t arg1); +static void writeData(UART_Handle handle, bool inISR); +static void writeFinishedDoCallback(UART_Handle handle); +static void writeSemCallback(UART_Handle handle, void *buffer, size_t count); + +/* + * Function for checking whether flow control is enabled. + */ +static inline bool isFlowControlEnabled(UARTCC26X0_HWAttrs const *hwAttrs) { + return ((hwAttrs->flowControl == UARTCC26X0_FLOWCTRL_HARDWARE) && + (hwAttrs->ctsPin != PIN_UNASSIGNED) && (hwAttrs->rtsPin != PIN_UNASSIGNED)); +} + +/* UART function table for UARTCC26X0 implementation */ +const UART_FxnTable UARTCC26X0_fxnTable = { + UARTCC26X0_close, + UARTCC26X0_control, + UARTCC26X0_init, + UARTCC26X0_open, + UARTCC26X0_read, + UARTCC26X0_readPollingNotImpl, + UARTCC26X0_readCancel, + UARTCC26X0_write, + UARTCC26X0_writePollingNotImpl, + UARTCC26X0_writeCancel +}; + +static const uint32_t dataLength[] = { + UART_CONFIG_WLEN_5, /* UART_LEN_5 */ + UART_CONFIG_WLEN_6, /* UART_LEN_6 */ + UART_CONFIG_WLEN_7, /* UART_LEN_7 */ + UART_CONFIG_WLEN_8 /* UART_LEN_8 */ +}; + +static const uint32_t stopBits[] = { + UART_CONFIG_STOP_ONE, /* UART_STOP_ONE */ + UART_CONFIG_STOP_TWO /* UART_STOP_TWO */ +}; + +static const uint32_t parityType[] = { + UART_CONFIG_PAR_NONE, /* UART_PAR_NONE */ + UART_CONFIG_PAR_EVEN, /* UART_PAR_EVEN */ + UART_CONFIG_PAR_ODD, /* UART_PAR_ODD */ + UART_CONFIG_PAR_ZERO, /* UART_PAR_ZERO */ + UART_CONFIG_PAR_ONE /* UART_PAR_ONE */ +}; + +/* + * Array for mapping of FIFO threshold defines selected by board files to + * TX FIFO threshold define used by driverlib FIFO threshold defines + * (enum UARTCC26X0_FifoThreshold) must be used as the array index. + * Index 0 handles backward compatibility with legacy board files that + * don't select any FIFO thresholds. + */ +static const uint8_t txFifoThreshold[6] = { + UART_FIFO_TX1_8, /* UARTCC26X0_FIFO_THRESHOLD_DEFAULT */ + UART_FIFO_TX1_8, /* UARTCC26X0_FIFO_THRESHOLD_1_8 */ + UART_FIFO_TX2_8, /* UARTCC26X0_FIFO_THRESHOLD_2_8 */ + UART_FIFO_TX4_8, /* UARTCC26X0_FIFO_THRESHOLD_4_8 */ + UART_FIFO_TX6_8, /* UARTCC26X0_FIFO_THRESHOLD_6_8 */ + UART_FIFO_TX7_8 /* UARTCC26X0_FIFO_THRESHOLD_7_8 */ +}; + +/* + * Array for mapping of FIFO threshold defines selected by board files to + * RX FIFO threshold define used by driverlib FIFO threshold defines + * (enum UARTCC26X0_FifoThreshold) must be used as the array index. + * Index 0 handles backward compatibility with legacy board files that + * don't select any FIFO thresholds. + */ +static const uint8_t rxFifoThreshold[6] = { + UART_FIFO_RX4_8, /* UARTCC26X0_FIFO_THRESHOLD_DEFAULT */ + UART_FIFO_RX1_8, /* UARTCC26X0_FIFO_THRESHOLD_1_8 */ + UART_FIFO_RX2_8, /* UARTCC26X0_FIFO_THRESHOLD_2_8 */ + UART_FIFO_RX4_8, /* UARTCC26X0_FIFO_THRESHOLD_4_8 */ + UART_FIFO_RX6_8, /* UARTCC26X0_FIFO_THRESHOLD_6_8 */ + UART_FIFO_RX7_8 /* UARTCC26X0_FIFO_THRESHOLD_7_8 */ +}; + +/* + * Array for mapping of FIFO threshold defines selected by board files to + * number of bytes in the RX FIFO threshold. + */ +static const uint8_t rxFifoBytes[6] = { + 16, /* UARTCC26X0_FIFO_THRESHOLD_DEFAULT */ + 4, /* UARTCC26X0_FIFO_THRESHOLD_1_8 */ + 8, /* UARTCC26X0_FIFO_THRESHOLD_2_8 */ + 16, /* UARTCC26X0_FIFO_THRESHOLD_4_8 */ + 24, /* UARTCC26X0_FIFO_THRESHOLD_6_8 */ + 28 /* UARTCC26X0_FIFO_THRESHOLD_7_8 */ +}; + +/* + * Array for mapping of FIFO threshold defines selected by board files to + * number of bytes in TX write FIFO threshold. + * Used for determining the timeout for the FIFO empty clock. + */ +static const uint8_t txFifoBytes[6] = { + 4, /* UARTCC26X0_FIFO_THRESHOLD_DEFAULT */ + 4, /* UARTCC26X0_FIFO_THRESHOLD_1_8 */ + 8, /* UARTCC26X0_FIFO_THRESHOLD_2_8 */ + 16, /* UARTCC26X0_FIFO_THRESHOLD_4_8 */ + 24, /* UARTCC26X0_FIFO_THRESHOLD_6_8 */ + 28 /* UARTCC26X0_FIFO_THRESHOLD_7_8 */ +}; + +/* + * ======== UARTCC26X0_close ======== + */ +void UARTCC26X0_close(UART_Handle handle) +{ + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Deallocate pins */ + PIN_close(object->hPin); + + /* Disable UART and interrupts. */ + UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX | UART_INT_RX | + UART_INT_RT | UART_INT_OE | UART_INT_BE | UART_INT_PE | + UART_INT_FE | UART_INT_CTS); + + /* Set to false to allow UARTCC26X0_readCancel() to release constraint */ + object->state.ctrlRxEnabled = false; + + object->state.opened = false; + + /* Cancel any possible ongoing reads/writes */ + UARTCC26X0_writeCancel(handle); + UARTCC26X0_readCancel(handle); + + /* + * Disable the UART. Do not call driverlib function + * UARTDisable() since it polls for BUSY bit to clear + * before disabling the UART FIFO and module. + */ + /* Disable UART FIFO */ + HWREG(hwAttrs->baseAddr + UART_O_LCRH) &= ~(UART_LCRH_FEN); + /* Disable UART module */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); + + HwiP_destruct(&(object->hwi)); + if (object->state.writeMode == UART_MODE_BLOCKING) { + SemaphoreP_destruct(&(object->writeSem)); + } + if (object->state.readMode == UART_MODE_BLOCKING) { + SemaphoreP_destruct(&(object->readSem)); + ClockP_destruct(&(object->timeoutClk)); + } + SwiP_destruct(&(object->swi)); + ClockP_destruct(&(object->txFifoEmptyClk)); + + /* Unregister power notification objects */ + Power_unregisterNotify(&object->postNotify); + + /* Release power dependency - i.e. potentially power down serial domain. */ + Power_releaseDependency(PowerCC26XX_PERIPH_UART0); + + DebugP_log1("UART:(%p) closed", hwAttrs->baseAddr); +} + + +/* + * ======== UARTCC26X0_control ======== + */ +int_fast16_t UARTCC26X0_control(UART_Handle handle, uint_fast16_t cmd, + void *arg) +{ + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + unsigned char data; + int bufferCount; + uintptr_t key; + + bufferCount = RingBuf_peek(&object->ringBuffer, &data); + + switch (cmd) { + /* Common UART CMDs */ + case (UART_CMD_PEEK): + *(int *)arg = (bufferCount) ? data : UART_ERROR; + DebugP_log2("UART:(%p) UART_CMD_PEEK: %d", hwAttrs->baseAddr, + *(uintptr_t*)arg); + return (UART_STATUS_SUCCESS); + + case (UART_CMD_ISAVAILABLE): + *(bool *)arg = (bufferCount != 0); + DebugP_log2("UART:(%p) UART_CMD_ISAVAILABLE: %d", + hwAttrs->baseAddr, *(uintptr_t*)arg); + return (UART_STATUS_SUCCESS); + + case (UART_CMD_GETRXCOUNT): + *(int *)arg = bufferCount; + DebugP_log2("UART:(%p) UART_CMD_GETRXCOUNT: %d", hwAttrs->baseAddr, + *(uintptr_t*)arg); + return (UART_STATUS_SUCCESS); + + case (UART_CMD_RXENABLE): + object->state.ctrlRxEnabled = true; + enableRX(handle); + return (UART_STATUS_SUCCESS); + + case (UART_CMD_RXDISABLE): + object->state.ctrlRxEnabled = false; + disableRX(handle); + return (UART_STATUS_SUCCESS); + + /* Specific UART CMDs */ + case UARTCC26X0_CMD_RETURN_PARTIAL_ENABLE: + /* Enable RETURN_PARTIAL */ + object->readRetPartial = true; + return (UART_STATUS_SUCCESS); + + case UARTCC26X0_CMD_RETURN_PARTIAL_DISABLE: + /* Disable RETURN_PARTIAL */ + object->readRetPartial = false; + return (UART_STATUS_SUCCESS); + + case UARTCC26X0_CMD_RX_FIFO_FLUSH: + /* Flush RX FIFO */ + /* Disable interrupts to avoid reading data while changing state */ + key = HwiP_disable(); + + /* Read RX FIFO until empty */ + while (((int32_t)UARTCharGetNonBlocking(hwAttrs->baseAddr)) != -1); + + /* Reset RingBuf */ + object->ringBuffer.count = 0; + object->ringBuffer.head = object->ringBuffer.length - 1; + object->ringBuffer.tail = 0; + + /* Set size = 0 to prevent reading and restore interrupts. */ + object->readSize = 0; + HwiP_restore(key); + + return (UART_STATUS_SUCCESS); + + default: + return (UART_STATUS_UNDEFINEDCMD); + } +} + +/* + * ======== UARTCC26X0_hwiIntFxn ======== + * Hwi function that processes UART interrupts. + */ +static void UARTCC26X0_hwiIntFxn(uintptr_t arg) +{ + uint32_t status; + UARTCC26X0_HWAttrs const *hwAttrs = ((UART_Handle)arg)->hwAttrs; + + /* Clear interrupts */ + status = UARTIntStatus(hwAttrs->baseAddr, true); + UARTIntClear(hwAttrs->baseAddr, status); + + if (status & (UART_INT_RX | UART_INT_RT | UART_INT_OE | UART_INT_BE | + UART_INT_PE | UART_INT_FE)) { + readIsr((UART_Handle)arg, status); + } + + if (status & UART_INT_TX) { + writeData((UART_Handle)arg, true); + } +} + +/* + * ======== UARTCC26X0_init ======== + */ +void UARTCC26X0_init(UART_Handle handle) +{ +} + +/* + * ======== UARTCC26X0_open ======== + */ +UART_Handle UARTCC26X0_open(UART_Handle handle, UART_Params *params) +{ + uintptr_t key; + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + /* Use union to save on stack allocation */ + union { + HwiP_Params hwiParams; + ClockP_Params clkParams; + SwiP_Params swiParams; + } paramsUnion; + + + /* Check for callback when in UART_MODE_CALLBACK */ + DebugP_assert((params->readMode != UART_MODE_CALLBACK) || + (params->readCallback != NULL)); + DebugP_assert((params->writeMode != UART_MODE_CALLBACK) || + (params->writeCallback != NULL)); + + key = HwiP_disable(); + + if (object->state.opened == true) { + HwiP_restore(key); + + DebugP_log1("UART:(%p) already in use.", hwAttrs->baseAddr); + return (NULL); + } + object->state.opened = true; + + HwiP_restore(key); + + object->state.readMode = params->readMode; + object->state.writeMode = params->writeMode; + object->state.readReturnMode = params->readReturnMode; + object->state.readDataMode = params->readDataMode; + object->state.writeDataMode = params->writeDataMode; + object->state.readEcho = params->readEcho; + object->readTimeout = params->readTimeout; + object->writeTimeout = params->writeTimeout; + object->readCallback = params->readCallback; + object->writeCallback = params->writeCallback; + object->baudRate = params->baudRate; + object->stopBits = params->stopBits; + object->dataLength = params->dataLength; + object->parityType = params->parityType; + + /* Set UART transaction variables to defaults. */ + object->writeBuf = NULL; + object->readBuf = NULL; + object->writeCount = 0; + object->readCount = 0; + object->writeSize = 0; + object->readSize = 0; + object->status = 0; + object->readRetPartial = false; + object->state.rxEnabled = false; + object->state.ctrlRxEnabled = false; + object->state.txEnabled = false; + object->state.drainByISR = false; + + /* Create circular buffer object to be used for read buffering */ + RingBuf_construct(&object->ringBuffer, hwAttrs->ringBufPtr, + hwAttrs->ringBufSize); + + /* Register power dependency - i.e. power up and enable clock for UART. */ + Power_setDependency(PowerCC26XX_PERIPH_UART0); + + UARTDisable(hwAttrs->baseAddr); + + /* Configure IOs, make sure it was successful */ + if (!initIO(handle)) { + /* Another driver or application already using these pins. */ + DebugP_log0("Could not allocate pins, already in use."); + /* Release power dependency */ + Power_releaseDependency(PowerCC26XX_PERIPH_UART0); + /* Mark the module as available */ + object->state.opened = false; + return (NULL); + } + + /* Initialize the UART hardware module */ + initHw(handle); + + /* Register notification function */ + Power_registerNotify(&object->postNotify, PowerCC26XX_AWAKE_STANDBY, + postNotifyFxn, (uintptr_t)handle); + + /* Create Hwi object for this UART peripheral. */ + HwiP_Params_init(&(paramsUnion.hwiParams)); + paramsUnion.hwiParams.arg = (uintptr_t)handle; + paramsUnion.hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), hwAttrs->intNum, UARTCC26X0_hwiIntFxn, + &(paramsUnion.hwiParams)); + + SwiP_Params_init(&(paramsUnion.swiParams)); + paramsUnion.swiParams.arg0 = (uintptr_t)handle; + paramsUnion.swiParams.priority = hwAttrs->swiPriority; + SwiP_construct(&(object->swi), swiCallback, &(paramsUnion.swiParams)); + + /* Create clock object to be used for write FIFO empty callback */ + ClockP_Params_init(¶msUnion.clkParams); + paramsUnion.clkParams.period = 0; + paramsUnion.clkParams.startFlag = false; + paramsUnion.clkParams.arg = (uintptr_t)handle; + ClockP_construct(&(object->txFifoEmptyClk), + (ClockP_Fxn)&writeFinishedDoCallback, + 10, &(paramsUnion.clkParams)); // TODO: timeout = 10? + + /* If read mode is blocking create a semaphore and set callback. */ + if (object->state.readMode == UART_MODE_BLOCKING) { + /* Timeout clock for reads */ + ClockP_construct(&(object->timeoutClk), + (ClockP_Fxn)&readBlockingTimeout, 0 /* timeout */, + &(paramsUnion.clkParams)); + + SemaphoreP_constructBinary(&(object->readSem), 0); + object->readCallback = &readSemCallback; + } + + /* If write mode is blocking create a semaphore and set callback. */ + if (object->state.writeMode == UART_MODE_BLOCKING) { + SemaphoreP_constructBinary(&(object->writeSem), 0); + object->writeCallback = &writeSemCallback; + } + + /* UART opened successfully */ + DebugP_log1("UART:(%p) opened", hwAttrs->baseAddr); + + /* Return the handle */ + return (handle); +} + +/* + * ======== UARTCC26X0_read ======== + */ +int_fast32_t UARTCC26X0_read(UART_Handle handle, void *buffer, size_t size) +{ + uintptr_t key; + UARTCC26X0_Object *object = handle->object; + int32_t bytesRead; + + key = HwiP_disable(); + + if (!object->state.opened || + ((object->state.readMode == UART_MODE_CALLBACK) && + object->readSize)) { + HwiP_restore(key); + return (UART_ERROR); + } + + /* Save the data to be read and restore interrupts. */ + object->readBuf = buffer; + object->readSize = size; + object->readCount = size; + object->status = 0; /* Clear read timeout or other errors */ + + HwiP_restore(key); + + enableRX(handle); + + if (object->state.readMode == UART_MODE_CALLBACK) { + /* Return value of readTaskCallback() should be 0 */ + bytesRead = readTaskCallback(handle); + } + else { + bytesRead = readTaskBlocking(handle); + /* + * Set the readCount to 0 so as not to trigger a read timeout + * interrupt in case more data comes in. + */ + object->readCount = 0; + } + + return (bytesRead); +} + +/* + * ======== UARTCC26X0_readCancel ======== + */ +void UARTCC26X0_readCancel(UART_Handle handle) +{ + uintptr_t key; + UARTCC26X0_Object *object = handle->object; + + disableRX(handle); + + if ((object->state.readMode != UART_MODE_CALLBACK) || + (object->readSize == 0)) { + return; + } + + key = HwiP_disable(); + + object->state.drainByISR = false; + /* + * Indicate that what we've currently received is what we asked for so that + * the existing logic handles the completion. + */ + object->readSize -= object->readCount; + object->readCount = 0; + + HwiP_restore(key); + + /* + * Trigger the RX callback function, even if no data is in the + * buffer. The ISR might not have been triggered yet because the + * FIFO trigger level has not been reached. + */ + SwiP_or(&(object->swi), READ_DONE); +} + +/* + * ======== UARTCC26X0_readPolling ======== + */ +int_fast32_t UARTCC26X0_readPolling(UART_Handle handle, void *buf, size_t size) +{ + int32_t count = 0; + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + unsigned char *buffer = (unsigned char *)buf; + uintptr_t key; + + /* Read characters. */ + while (size) { + /* Grab data from the RingBuf before getting it from the RX data reg */ + key = HwiP_disable(); + UARTIntDisable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT); + HwiP_restore(key); + + if (RingBuf_get(&object->ringBuffer, buffer) == -1) { + *buffer = UARTCharGet(hwAttrs->baseAddr); + } + + key = HwiP_disable(); + if (object->state.rxEnabled) { + UARTIntEnable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT); + } + HwiP_restore(key); + + DebugP_log2("UART:(%p) Read character 0x%x", hwAttrs->baseAddr, + *buffer); + count++; + size--; + + if (object->state.readDataMode == UART_DATA_TEXT && *buffer == '\r') { + /* Echo character if enabled. */ + if (object->state.readEcho) { + UARTCharPut(hwAttrs->baseAddr, '\r'); + } + *buffer = '\n'; + } + + /* Echo character if enabled. */ + if (object->state.readDataMode == UART_DATA_TEXT && + object->state.readEcho) { + UARTCharPut(hwAttrs->baseAddr, *buffer); + } + + /* If read return mode is newline, finish if a newline was received. */ + if (object->state.readDataMode == UART_DATA_TEXT && + object->state.readReturnMode == UART_RETURN_NEWLINE && + *buffer == '\n') { + return (count); + } + + buffer++; + } + + DebugP_log2("UART:(%p) Read polling finished, %d bytes read", + hwAttrs->baseAddr, count); + + return (count); +} + +/* + * ======== UARTCC26X0_readPollingNotImpl ======== + */ +int_fast32_t UARTCC26X0_readPollingNotImpl(UART_Handle handle, void *buf, + size_t size) +{ + /* Not supported */ + return (UART_ERROR); +} + +/* + * ======== UARTCC26X0_write ======== + */ +int_fast32_t UARTCC26X0_write(UART_Handle handle, const void *buffer, + size_t size) +{ + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + + if (size == 0) { + return (0); + } + + key = HwiP_disable(); + + /* + * Make sure any previous write has fininshed. If TX is still + * enabled, then writeFinishedDoCallback() has not yet been called. + */ + if (!object->state.opened || object->state.txEnabled) { + HwiP_restore(key); + DebugP_log1("UART:(%p) Could not write data, uart closed or in use.", + hwAttrs->baseAddr); + + return (UART_ERROR); + } + + /* Save the data to be written and restore interrupts. */ + object->writeBuf = buffer; + object->writeSize = size; + object->writeCount = size; + + object->state.txEnabled = true; + + /* Set constraints to guarantee transaction */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Enable TX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_TXE; + + DebugP_log1("UART:(%p) UART_write set write power constraint", + hwAttrs->baseAddr); + + HwiP_restore(key); + + if (!(UARTIntStatus(hwAttrs->baseAddr, false) & UART_INT_TX)) { + /* + * Start the transfer going if the raw interrupt status TX bit + * is 0. This will cause the ISR to fire when we enable + * UART_INT_TX. If the RIS TX bit is not cleared, we don't + * need to call writeData(), since the ISR will fire once we + * enable the interrupt, causing the transfer to start. + */ + writeData(handle, false); + } + if (object->writeCount) { + key = HwiP_disable(); + UARTIntEnable(hwAttrs->baseAddr, UART_INT_TX); + HwiP_restore(key); + } + + /* If writeMode is blocking, block and get the state. */ + if (object->state.writeMode == UART_MODE_BLOCKING) { + /* Pend on semaphore and wait for Hwi to finish. */ + if (SemaphoreP_OK != SemaphoreP_pend(&(object->writeSem), + object->writeTimeout)) { + /* Semaphore timed out, make the write empty and log the write. */ + key = HwiP_disable(); + UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX); + UARTIntClear(hwAttrs->baseAddr, UART_INT_TX); + + if (object->state.txEnabled) { + + /* Disable TX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_TXE); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + object->state.txEnabled = false; + } + HwiP_restore(key); + + DebugP_log2("UART:(%p) Write timed out, %d bytes written", + hwAttrs->baseAddr, object->writeCount); + } + return (object->writeSize - object->writeCount); + } + + return (0); +} + +/* + * ======== UARTCC26X0_writeCancel ======== + */ +void UARTCC26X0_writeCancel(UART_Handle handle) +{ + uintptr_t key; + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + + key = HwiP_disable(); + + /* Return if there is no write. */ + if (!object->state.txEnabled) { + HwiP_restore(key); + return; + } + + UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX); + UARTIntClear(hwAttrs->baseAddr, UART_INT_TX); + + /* Release constraint since transaction is done */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + object->state.txEnabled = false; + + /* Disable TX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_TXE); + + HwiP_restore(key); + + object->writeCallback(handle, (void *)object->writeBuf, + object->writeSize - object->writeCount); + + DebugP_log2("UART:(%p) Write canceled, %d bytes written", + hwAttrs->baseAddr, object->writeSize - object->writeCount); +} + +/* + * ======== UARTCC26X0_writePolling ======== + */ +int_fast32_t UARTCC26X0_writePolling(UART_Handle handle, const void *buf, + size_t size) +{ + int32_t count = 0; + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + unsigned char *buffer = (unsigned char *)buf; + uintptr_t key; + + /* Enable TX */ + key = HwiP_disable(); + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_TXE; + HwiP_restore(key); + + /* Write characters. */ + while (size) { + if (object->state.writeDataMode == UART_DATA_TEXT && *buffer == '\n') { + UARTCharPut(hwAttrs->baseAddr, '\r'); + count++; + } + UARTCharPut(hwAttrs->baseAddr, *buffer); + + DebugP_log2("UART:(%p) Wrote character 0x%x", hwAttrs->baseAddr, + *buffer); + buffer++; + count++; + size--; + } + + while (UARTBusy(hwAttrs->baseAddr)) { + ; + } + + /* Disable TX */ + key = HwiP_disable(); + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_TXE); + HwiP_restore(key); + + DebugP_log2("UART:(%p) Write polling finished, %d bytes written", + hwAttrs->baseAddr, count); + + return (count); +} + +/* + * ======== UARTCC26X0_writePollingNotImpl ======== + */ +int_fast32_t UARTCC26X0_writePollingNotImpl(UART_Handle handle, + const void *buf, size_t size) +{ + /* Not supported */ + return (UART_ERROR); +} + +/* + * ======== disableRX ======== + */ +static void disableRX(UART_Handle handle) +{ + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + + if (!object->state.ctrlRxEnabled) { + key = HwiP_disable(); + if (object->state.rxEnabled) { + UARTIntDisable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT | + UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE); + /* Disable RX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_RXE); + + object->state.rxEnabled = false; + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + HwiP_restore(key); + } +} + +/* + * ======== enableRX ======== + */ +static void enableRX(UART_Handle handle) +{ + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + + key = HwiP_disable(); + if (!object->state.rxEnabled) { + /* Set constraint for sleep to guarantee transaction */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Enable RX and receive interrupts */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_RXE; + UARTIntEnable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT | + UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE); + + object->state.rxEnabled = true; + } + HwiP_restore(key); +} + +/* + * ======== initHw ======== + */ +static void initHw(UART_Handle handle) +{ + ClockP_FreqHz freq; + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* + * Configure frame format and baudrate. UARTConfigSetExpClk() disables + * the UART and does not re-enable it, so call this function first. + */ + ClockP_getCpuFreq(&freq); + UARTConfigSetExpClk(hwAttrs->baseAddr, freq.lo, object->baudRate, + dataLength[object->dataLength] | + stopBits[object->stopBits] | + parityType[object->parityType]); + + /* Clear all UART interrupts */ + UARTIntClear(hwAttrs->baseAddr, UART_INT_OE | UART_INT_BE | UART_INT_PE | + UART_INT_FE | UART_INT_RT | UART_INT_TX | + UART_INT_RX | UART_INT_CTS); + + /* Set TX interrupt FIFO level and RX interrupt FIFO level */ + UARTFIFOLevelSet(hwAttrs->baseAddr, txFifoThreshold[hwAttrs->txIntFifoThr], + rxFifoThreshold[hwAttrs->rxIntFifoThr]); + + /* If Flow Control is enabled, configure hardware flow control */ + if (isFlowControlEnabled(hwAttrs)) { + UARTHwFlowControlEnable(hwAttrs->baseAddr); + } + else { + UARTHwFlowControlDisable(hwAttrs->baseAddr); + } + + /* Enable UART FIFOs */ + HWREG(hwAttrs->baseAddr + UART_O_LCRH) |= UART_LCRH_FEN; + + /* Enable the UART module */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_UARTEN; + + if (object->state.ctrlRxEnabled) { + /* Enable RX */ + enableRX(handle); + } +} + +/* + * ======== initIO ======== + */ +static bool initIO(UART_Handle handle) +{ + /* Locals */ + UARTCC26X0_Object *object; + UARTCC26X0_HWAttrs const *hwAttrs; + PIN_Config uartPinTable[5]; + uint32_t pinCount = 0; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Build local list of pins, allocate through PIN driver and map ports */ + uartPinTable[pinCount++] = hwAttrs->rxPin | PIN_INPUT_EN; + /* + * Make sure UART_TX pin is driven high after calling PIN_open(...) until + * we've set the correct peripheral muxing in PINCC26XX_setMux(...). + * This is to avoid falling edge glitches when configuring the + * UART_TX pin. + */ + uartPinTable[pinCount++] = hwAttrs->txPin | PIN_INPUT_DIS | PIN_PUSHPULL | + PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH; + + if (isFlowControlEnabled(hwAttrs)) { + uartPinTable[pinCount++] = hwAttrs->ctsPin | PIN_INPUT_EN; + /* Avoiding glitches on the RTS, see comment for TX pin above. */ + uartPinTable[pinCount++] = hwAttrs->rtsPin | PIN_INPUT_DIS | + PIN_PUSHPULL | PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH; + } + + /* Terminate pin list */ + uartPinTable[pinCount] = PIN_TERMINATE; + + /* Open and assign pins through pin driver */ + object->hPin = PIN_open(&object->pinState, uartPinTable); + + /* Are pins already allocated */ + if (!object->hPin) { + return (false); + } + + /* Set IO muxing for the UART pins */ + PINCC26XX_setMux(object->hPin, hwAttrs->rxPin, IOC_PORT_MCU_UART0_RX); + PINCC26XX_setMux(object->hPin, hwAttrs->txPin, IOC_PORT_MCU_UART0_TX); + + if (isFlowControlEnabled(hwAttrs)) { + PINCC26XX_setMux(object->hPin, hwAttrs->ctsPin, + IOC_PORT_MCU_UART0_CTS); + PINCC26XX_setMux(object->hPin, hwAttrs->rtsPin, + IOC_PORT_MCU_UART0_RTS); + } + /* Success */ + return (true); +} + +/* + * ======== postNotifyFxn ======== + * Called by Power module when waking up from LPDS. + */ +static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + uintptr_t clientArg) +{ + /* Reconfigure the hardware if returning from sleep */ + if (eventType == PowerCC26XX_AWAKE_STANDBY) { + initHw((UART_Handle) clientArg); + } + + return (Power_NOTIFYDONE); +} + +/* + * ======== readBlockingTimeout ======== + */ +static void readBlockingTimeout(uintptr_t arg) +{ + UARTCC26X0_Object *object = ((UART_Handle)arg)->object; + object->state.bufTimeout = true; + SemaphoreP_post(&(object->readSem)); +} + +/* + * ======== readIsr ======== + */ +static void readIsr(UART_Handle handle, uint32_t status) +{ + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + int readIn; + int maxBytesToRead = FIFO_SIZE; + size_t rxFifoThresholdBytes; + int bytesRead; + uint32_t errStatus = 0; + + if (status & UART_INT_OE) { + /* Fifo overrun error - will read all data in the fifo */ + errStatus = UARTRxErrorGet(hwAttrs->baseAddr); + UARTRxErrorClear(hwAttrs->baseAddr); + object->status = errStatus; + } + else if (status & (UART_INT_RT)) { + object->status = READTIMEDOUT; + } + else if (object->readRetPartial && (status & UART_INT_RX)) { + rxFifoThresholdBytes = rxFifoBytes[hwAttrs->rxIntFifoThr]; + if (object->readCount > rxFifoThresholdBytes) { + /* Will leave one byte in the FIFO to trigger the RT interrupt */ + maxBytesToRead = rxFifoThresholdBytes - 1; + } + } + + bytesRead = 0; + + while (UARTCharsAvail(hwAttrs->baseAddr)) { + /* + * If the Ring buffer is full, leave the data in the FIFO. + * This will allow flow control to work, if it is enabled. + */ + if (RingBuf_isFull(&object->ringBuffer)) { + break; + } + + readIn = UARTCharGetNonBlocking(hwAttrs->baseAddr); + if (readIn & UART_BE_PE_FE) { + errStatus = UARTRxErrorGet(hwAttrs->baseAddr); + UARTRxErrorClear(hwAttrs->baseAddr); + object->status = errStatus; + break; + } + + bytesRead++; + + if ((object->state.readDataMode == UART_DATA_TEXT) && readIn == '\r') { + /* Echo character if enabled. */ + if (object->state.readEcho) { + UARTCharPut(hwAttrs->baseAddr, '\r'); + } + readIn = '\n'; + } + RingBuf_put(&object->ringBuffer, (unsigned char)readIn); + + if ((object->state.readDataMode == UART_DATA_TEXT) && + (object->state.readEcho)) { + UARTCharPut(hwAttrs->baseAddr, (unsigned char)readIn); + } + + if (bytesRead >= maxBytesToRead) { + break; + } + } + + if ((object->state.readMode == UART_MODE_BLOCKING) && ((bytesRead > 0) || + (errStatus != 0))) { + /* object->state.callCallback set in readTaskBlocking() */ + if (object->state.callCallback) { + object->state.callCallback = false; + object->readCallback(handle, NULL, 0); + } + } + + /* + * Check and see if a UART_read in callback mode told use to continue + * servicing the user buffer... + */ + if (object->state.drainByISR) { + /* In CALLBACK mode */ + readTaskCallback(handle); + } + + if (errStatus) { + UARTCC26X0_readCancel(handle); + if (hwAttrs->errorFxn) { + hwAttrs->errorFxn(handle, errStatus); + } + } +} + +/* + * ======== readSemCallback ======== + * Simple callback to post a semaphore for the blocking mode. + */ +static void readSemCallback(UART_Handle handle, void *buffer, size_t count) +{ + UARTCC26X0_Object *object = handle->object; + + SemaphoreP_post(&(object->readSem)); +} + +/* + * ======== readTaskBlocking ======== + */ +static int readTaskBlocking(UART_Handle handle) +{ + unsigned char readIn; + uintptr_t key; + UARTCC26X0_Object *object = handle->object; + unsigned char *buffer = object->readBuf; + + object->state.bufTimeout = false; + /* + * It is possible for the object->timeoutClk and the callback function to + * have posted the object->readSem Semaphore from the previous UART_read + * call (if the code below didn't get to stop the clock object in time). + * To clear this, we simply do a NO_WAIT pend on (binary) object->readSem + * so that it resets the Semaphore count. + */ + SemaphoreP_pend(&(object->readSem), SemaphoreP_NO_WAIT); + + if ((object->readTimeout != 0) && + (object->readTimeout != UART_WAIT_FOREVER)) { + ClockP_setTimeout(&(object->timeoutClk), object->readTimeout); + ClockP_start(&(object->timeoutClk)); + } + + while (object->readCount) { + key = HwiP_disable(); + + if (ringBufGet(handle, &readIn) < 0) { + if (object->readRetPartial) { + if (object->status == READTIMEDOUT) { + object->status = 0; + HwiP_restore(key); + break; + } + + /* If some data has been read, return */ + if (object->readCount < object->readSize) { + HwiP_restore(key); + break; + } + } + + if (object->state.bufTimeout || (object->status != 0)) { + /* Timed out or RX error waiting for read to complete */ + HwiP_restore(key); + disableRX(handle); + break; + } + + object->state.callCallback = true; + HwiP_restore(key); + + if (object->readTimeout == 0) { + break; + } + + SemaphoreP_pend(&(object->readSem), SemaphoreP_WAIT_FOREVER); + } + else { + /* Got something from the ring buffer */ + object->readCount--; + HwiP_restore(key); + + DebugP_log2("UART:(%p) read '0x%02x'", + ((UARTCC26X0_HWAttrs const *)(handle->hwAttrs))->baseAddr, + (unsigned char)readIn); + + *buffer = readIn; + buffer++; + + if (object->state.readDataMode == UART_DATA_TEXT && + object->state.readReturnMode == UART_RETURN_NEWLINE && + readIn == '\n') { + break; + } + } + } + + ClockP_stop(&(object->timeoutClk)); + return (object->readSize - object->readCount); +} + +/* + * ======== readTaskCallback ======== + * This function is called the first time by the UART_read task and tries to + * get all the data it can get from the ringBuffer. If it finished, it will + * perform the user supplied callback. If it didn't finish, the ISR must + * handle the remaining data. By setting the drainByISR flag, the UART_read + * function handed over the responsibility to get the remaining data to the + * ISR. + */ +static int readTaskCallback(UART_Handle handle) +{ + unsigned int key; + UARTCC26X0_Object *object = handle->object; + unsigned char readIn; + unsigned char *bufferEnd; + bool makeCallback = false; + + object->state.drainByISR = false; + bufferEnd = (unsigned char*) object->readBuf + object->readSize; + + while (object->readCount) { + if (ringBufGet(handle, &readIn) < 0) { + break; + } + + DebugP_log2("UART:(%p) read '0x%02x'", + ((UARTCC26X0_HWAttrs const *)(handle->hwAttrs))->baseAddr, + (unsigned char)readIn); + + *(unsigned char *) (bufferEnd - object->readCount * + sizeof(unsigned char)) = readIn; + + key = HwiP_disable(); + + object->readCount--; + + HwiP_restore(key); + + if ((object->state.readDataMode == UART_DATA_TEXT) && + (object->state.readReturnMode == UART_RETURN_NEWLINE) && + (readIn == '\n')) { + makeCallback = true; + break; + } + } + + if ((object->status & UARTCC26X0_RXERROR) && (object->readCount != 0)) { + /* An error occurred. */ + key = HwiP_disable(); + object->readSize -= object->readCount; + object->readCount = 0; + HwiP_restore(key); + } + else if ((object->readRetPartial && + (object->readCount < object->readSize)) || + (object->readCount == 0) || + makeCallback) { + SwiP_or(&(object->swi), READ_DONE); + } + else { + object->state.drainByISR = true; + } + + return (0); +} + +/* + * ======== ringBufGet ======== + */ +static int ringBufGet(UART_Handle handle, unsigned char *data) +{ + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + int32_t readIn; + int count; + + key = HwiP_disable(); + + if (RingBuf_isFull(&object->ringBuffer)) { + count = RingBuf_get(&object->ringBuffer, data); + + readIn = UARTCharGetNonBlocking(hwAttrs->baseAddr); + if (readIn != -1) { + RingBuf_put(&object->ringBuffer, (unsigned char)readIn); + count++; + } + HwiP_restore(key); + } + else { + count = RingBuf_get(&object->ringBuffer, data); + HwiP_restore(key); + } + + return (count); +} + +/* + * ======== startTxFifoEmptyClk ======== + * Last write to TX FIFO is done, but not shifted out yet. Start a clock + * which will trigger when the TX FIFO should be empty. + */ +static void startTxFifoEmptyClk(UART_Handle handle, uint32_t numDataInFifo) +{ + UARTCC26X0_Object *object = handle->object; + + /* Ensure that the clock is stopped so we can set a new timeout */ + ClockP_stop((ClockP_Handle)&(object->txFifoEmptyClk)); + + /* No more to write, but data is not shifted out properly yet. + * 1. Compute appropriate wait time for FIFO to empty out + * - 1 bit for start bit + * - 5+(object->dataLength) for total data length + * - +1 to "map" from stopBits to actual number of bits + * - 1000000 so we get 1 us resolution + * - 100 (100us) for margin + */ + unsigned int writeTimeoutUs = (numDataInFifo * + (1 + 5 + (object->dataLength) + (object->stopBits + 1)) * + 1000000) / object->baudRate + 100; + + /* 2. Configure clock object to trigger when FIFO is empty + * - + 1 in case clock module due to tick is less than one ClockP + * tick period + * - UNIT_DIV_ROUNDUP to avoid fractional part being truncated + * during division + */ + + ClockP_setTimeout((ClockP_Handle) &(object->txFifoEmptyClk), + (1 + UNIT_DIV_ROUNDUP(writeTimeoutUs, ClockP_tickPeriod))); + ClockP_start((ClockP_Handle) &(object->txFifoEmptyClk)); +} + +/* + * ======== swiCallback ======== + */ +static void swiCallback(uintptr_t arg0, uintptr_t arg1) +{ + UART_Handle handle = (UART_Handle)arg0; + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t trigger = SwiP_getTrigger(); + uintptr_t key; + size_t count; + + if (trigger & READ_DONE) { + key = HwiP_disable(); + + count = object->readSize - object->readCount; + object->readSize = 0; + + HwiP_restore(key); + + object->readCallback((UART_Handle)arg0, object->readBuf, count); + } + + if (trigger & WRITE_DONE) { + /* + * Check txEnabled before releasing Power constraint. + * UARTCC26X0_writeCancel() could have been called and released the + * constraint. + */ + key = HwiP_disable(); + if (object->state.txEnabled) { + /* Release constraint since transaction is done */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + object->state.txEnabled = false; + } + HwiP_restore(key); + + /* Disable TX interrupt */ + UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX); + + /* Disable TX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_TXE); + + /* Make callback */ + object->writeCallback(handle, (uint8_t*)object->writeBuf, + object->writeSize); + DebugP_log2("UART:(%p) Write finished, %d bytes written", + hwAttrs->baseAddr, object->writeCount); + } +} + +/* + * ======== writeData ======== + */ +static void writeData(UART_Handle handle, bool inISR) +{ + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + unsigned char *writeOffset; + uint32_t lastWriteCount = 0; + uintptr_t key; + + writeOffset = (unsigned char *)object->writeBuf + + object->writeSize * sizeof(unsigned char); + + while (object->writeCount) { + if (!UARTCharPutNonBlocking(hwAttrs->baseAddr, + *(writeOffset - object->writeCount))) { + /* TX FIFO is FULL */ + break; + } + if ((object->state.writeDataMode == UART_DATA_TEXT) && + (*(writeOffset - object->writeCount) == '\n')) { + UARTCharPut(hwAttrs->baseAddr, '\r'); + } + object->writeCount--; + lastWriteCount++; + } + + if (!object->writeCount) { + key = HwiP_disable(); + UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX); + HwiP_restore(key); + + UARTIntClear(hwAttrs->baseAddr, UART_INT_TX); + + /* + * No more to write, but data is not shifted out yet. + * Start TX FIFO Empty clock which will trigger once all the data + * has been shifted out. + * Add the FIFO threshold to account for any data in the FIFO when + * the interrupt is triggered. + */ + if (inISR) { + lastWriteCount += txFifoBytes[hwAttrs->txIntFifoThr]; + } + startTxFifoEmptyClk(handle, lastWriteCount); + + DebugP_log2("UART:(%p) Write finished, %d bytes written", + hwAttrs->baseAddr, object->writeSize - object->writeCount); + } +} + +/* + * ======== writeFinishedDoCallback ======== + * This function is called when the txFifoEmptyClk times out. The TX FIFO + * should now be empty and all bytes have been transmitted. The TX will be + * turned off, TX interrupt disabled, and standby allowed again. + */ +static void writeFinishedDoCallback(UART_Handle handle) +{ + UARTCC26X0_Object *object = handle->object; + UARTCC26X0_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* + * Function verifies that the FIFO is empty via BUSY flag + * If not yet ready start the periodic timer and wait another period + */ + if (UARTBusy(hwAttrs->baseAddr)) { + /* + * The UART is still busy. + * Wait 500 us before checking again or 1 tick period if the + * ClockP_tickPeriod is larger than 500 us. + */ + ClockP_setTimeout((ClockP_Handle)&(object->txFifoEmptyClk), + MAX((500 / ClockP_tickPeriod), 1)); + ClockP_start((ClockP_Handle)&(object->txFifoEmptyClk)); + return; + } + + /* Post the Swi that will make the callback */ + SwiP_or(&(object->swi), WRITE_DONE); +} + +/* + * ======== writeSemCallback ======== + * Simple callback to post a semaphore for the blocking mode. + */ +static void writeSemCallback(UART_Handle handle, void *buffer, size_t count) +{ + UARTCC26X0_Object *object = handle->object; + + SemaphoreP_post(&(object->writeSem)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X0.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X0.h new file mode 100644 index 0000000..31b64b3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X0.h @@ -0,0 +1,630 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file UARTCC26X0.h + * + * @brief UART driver implementation for a CC26X0 UART controller + * + * # Driver include # + * The UART header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref UART.h for a complete description of APIs. + * + * # Overview # + * The general UART API should used in application code, i.e. UART_open() + * is used instead of UARTCC26X0_open(). The board file will define the device + * specific config, and casting in the general API will ensure that the correct + * device specific functions are called. + * This is also reflected in the example code in [Use Cases](@ref USE_CASES). + * + * # General Behavior # + * Before using the UART in CC26X0: + * - The UART driver is initialized by calling UART_init(). + * - The UART HW is configured and flags system dependencies (e.g. IOs, + * power, etc.) by calling UART_open(). + * - The RX and TX can operate independently of each other. + * . + * The following is true for receive operation: + * - RX is enabled by calling UART_read(). + * - All received bytes are ignored after UART_open() is called, until + * the first UART_read(). + * - If an RX error occur, RX is turned off and all bytes received before the + * error occured are returned. + * - After a successful read, RX remains on. UART_read() must be called + * again before FIFO goes full in order to avoid overflow. It is safe to + * call another UART_read() from the read callback, See + * [Receive Continously] (@ref UARTCC26X0_USE_CASE_CB) use case below. + * - If a read times out (in ::UART_MODE_BLOCKING mode), RX will remain on. + * UART_read() must be called again before FIFO goes full in order to avoid overflow. + * - The UART_read() supports partial return, that can be used if the + * receive size is unknown. See [Use Cases](@ref USE_CASES) below. + * - The RingBuf serves as an extension of the FIFO. If data is received when + * UART_read() is not called, data will be stored in the RingBuf. The + * functionality of the RingBuf has been tested with a size of 32. This size + * can be changed to suit the application. + * . + * The following apply for transmit operation: + * - TX is enabled by calling UART_write(). + * - If the UART_write() succeeds, the TX is disabled. + * . + * If UART is no longer needed by application: + * - Release system dependencies for UART by calling UART_close(). + * . + * If the UART is configured in ::UART_MODE_CALLBACK mode: + * - The error handling callback is run in a HWI context. + * - The application's callback is run in a SWI context. + * + * # Error handling # + * ## Read errors ## + * If an error occurs during read operation: + * - All bytes received up until an error occurs will be returned, with the + * error signaled in the ::UARTCC26X0_Object.status field. The RX is then turned off + * and all bytes will be ignored until a new read is issued. Note that only + * the read is cancelled when the error occurs. If a write was active + * while the RX error occurred, it will complete. A new UART_read() will reset + * the ::UARTCC26X0_Object.status field to 0. + * - If a RX break error occurs, an extra 0 byte will also be returned by the + * UART_read(). + * . + * + * ## General timeout ## + * A timeout value can only be specified for reads and writes in ::UART_MODE_BLOCKING. + * If a timeout occurs during a read when in ::UART_MODE_BLOCKING, the number of bytes + * received will be returned. + * After a read timeout, RX will be turned off and the device allowed to enter standby. + * For more details see [Power Management](@ref POWER_MANAGEMENT) chapter below. + * + * In ::UART_MODE_CALLBACK there is no timeout and the application must call + * UART_readCancel() or UART_writeCancel() to abort the operation. + * + * ## Closing driver during an ongoing read/write ## + * It's safe to call UART_close() during an ongoing UART_read() and/or UART_write(), + * this will cancel the ongoing RX/TX immediately. + * + * The RX callback is alwyas called when you call UART_close() if there's an + * ongoing read. + * Note that if UART_close() is called during an ongoing read, the size provided + * in the RX callback function is 0 if < 16 bytes were received before calling UART_close(). + * This is because 16 bytes is the RX watermark that triggers the ISR + * to copy bytes from the internal UART FIFO to the software RX buffer. + * + * The TX callback is always called when you call UART_close() if there's an + * ongoing write. The driver does not wait until a byte is transmitted correctly, + * so if UART_close() is called in the middle of sending a byte, + * this byte will be corrupted. + * + * # Power Management @anchor UARTCC26X0_POWER_MANAGEMENT # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * The UARTCC26X0 driver sets a power constraint during operation to keep + * the device out of standby. When the operation has finished, the power + * constraint is released. + * The following statements are valid: + * - After UART_open(): the device is still allowed to enter standby. + * - During UART_read(): the device cannot enter standby. + * - After an RX error (overrun, break, parity, framing): RX is disabled and the device + * is allowed to enter standby. + * - After a successful UART_read(): + * The device is not allowed to enter standby and RX remains on. + * - _Note_: Application thread should typically either issue another read after + * UART_read() completes successfully, or call either + * UART_readCancel() or UART_control(uart, UART_CMD_RXDISABLE, 0), + * to disable RX and allow the device to enter standby. + * - After UART_read() times out in ::UART_MODE_BLOCKING: + * The device is allowed to enter standby and RX is turned off. To prevent + * RX from being disabled and disallowing standby on a read timeout or read + * error, the application can call UART_control(uart, UART_CMD_RXENABLE, 0). + * - During UART_write(): the device cannot enter standby. + * - After UART_write() succeeds: the device can enter standby. + * - If UART_writeCancel() is called: the device can enter standby. + * - After write timeout: the device can enter standby. + * + * # Flow Control # + * To enable Flow Control, the RTS and CTS pins must be assigned in the + * ::UARTCC26X0_HWAttrs and flowControl must be set to UARTCC26X0_FLOWCTRL_HARDWARE: + * @code + * const UARTCC26X0_HWAttrs uartCC26X0HWAttrs[] = { + * { + * .baseAddr = UART0_BASE, + * .intNum = INT_UART0, + * .intPriority = ~0, + * .swiPriority = 0, + * .flowControl = UARTCC26X0_FLOWCTRL_HARDWARE, + * .txPin = Board_UART_TX, + * .rxPin = Board_UART_RX, + * .ctsPin = Board_UART_CTS, + * .rtsPin = Board_UART_RTS + * .ringBufPtr = uartCC26X0RingBuffer[0], + * .ringBufSize = sizeof(uartCC26X0RingBuffer[0]), + * .txIntFifoThr= UARTCC26X0_FIFO_THRESHOLD_1_8, + * .rxIntFifoThr= UARTCC26X0_FIFO_THRESHOLD_4_8 + * } + * }; + * @endcode + * + * If the RTS and CTS pins are set to ::PIN_UNASSIGNED, or flowControl is set + * to UARTCC26X0_FLOWCONTROL_NONE, the flow control is disabled. + * An example is shown in the ::UARTCC26X0_HWAttrs description. + * + * # Supported Functions # + * | Generic API function | API function | Description | + * |----------------------|--------------------------|------------------------ + * | UART_init() | UARTCC26X0_init() | Initialize UART driver | + * | UART_open() | UARTCC26X0_open() | Initialize UART HW and set system dependencies | + * | UART_close() | UARTCC26X0_close() | Disable UART HW and release system dependencies | + * | UART_control() | UARTCC26X0_control() | Configure an already opened UART handle | + * | UART_read() | UARTCC26X0_read() | Start read from UART | + * | UART_readCancel() | UARTCC26X0_readCancel() | Cancel ongoing read from UART | + * | UART_readPolling() | UARTCC26X0_readPolling() | Polling read from UART | + * | UART_write() | UARTCC26X0_write() | Start write to UART | + * | UART_writeCancel() | UARTCC26X0_writeCancel() | Cancel ongoing write to UART | + * | UART_writePolling() | UARTCC26X0_writePolling()| Polling write to UART | + * + * @note All calls should go through the generic API + * + * # Use Cases @anchor UARTCC26X0_USE_CASES # + * ## Basic Receive # + * Receive 100 bytes over UART in ::UART_MODE_BLOCKING. + * @code + * UART_Handle handle; + * UART_Params params; + * uint8_t rxBuf[100]; // Receive buffer + * uint32_t timeoutUs = 5000; // 5ms timeout, default timeout is no timeout (BIOS_WAIT_FOREVER) + * + * // Init UART and specify non-default parameters + * UART_Params_init(¶ms); + * params.baudRate = 9600; + * params.writeDataMode = UART_DATA_BINARY; + * params.readTimeout = timeoutUs / ClockP_tickPeriod; // Default tick period is 10us + * + * // Open the UART and do the read + * handle = UART_open(Board_UART, ¶ms); + * int rxBytes = UART_read(handle, rxBuf, 100); + * @endcode + * + * ## Receive with Return Partial # + * This use case will read in ::UART_MODE_BLOCKING until the wanted amount of bytes is + * received or until a started reception is inactive for a 32-bit period. + * This UART_read() call can also be used when unknown amount of bytes shall + * be read. Note: The partial return is also possible in ::UART_MODE_CALLBACK mode. + * @code + * UART_Handle handle; + * UART_Params params; + * uint8_t rxBuf[100]; // Receive buffer + * + * // Init UART and specify non-default parameters + * UART_Params_init(¶ms); + * params.baudRate = 9600; + * params.writeDataMode = UART_DATA_BINARY; + * + * // Open the UART and initiate the partial read + * handle = UART_open(Board_UART, ¶ms); + * // Enable RETURN_PARTIAL + * UART_control(handle, UARTCC26X0_CMD_RETURN_PARTIAL_ENABLE, NULL); + * // Begin read + * int rxBytes = UART_read(handle, rxBuf, 100)); + * @endcode + * + * ## Basic Transmit # + * This case will configure the UART to send the data in txBuf in + * BLOCKING_MODE. + * @code + * UART_Handle handle; + * UART_Params params; + * uint8_t txBuf[] = "Hello World"; // Transmit buffer + * + * // Init UART and specify non-default parameters + * UART_Params_init(¶ms); + * params.baudRate = 9600; + * params.writeDataMode = UART_DATA_BINARY; + * + * // Open the UART and do the write + * handle = UART_open(Board_UART, ¶ms); + * UART_write(handle, txBuf, sizeof(txBuf)); + * @endcode + * + * ## Receive Continously in ::UART_MODE_CALLBACK @anchor UARTCC26X0_USE_CASE_CB # + * This case will configure the UART to receive and transmit continously in + * ::UART_MODE_CALLBACK, and transmit them back via UART TX. + * Note that UART_Params.readTimeout is not in use when using ::UART_MODE_CALLBACK mode. + * @code + * #define MAX_NUM_RX_BYTES 1000 // Maximum RX bytes to receive in one go + * #define MAX_NUM_TX_BYTES 1000 // Maximum TX bytes to send in one go + * + * uint32_t wantedRxBytes; // Number of bytes received so far + * uint8_t rxBuf[MAX_NUM_RX_BYTES]; // Receive buffer + * uint8_t txBuf[MAX_NUM_TX_BYTES]; // Transmit buffer + * + * // Read callback function + * static void readCallback(UART_Handle handle, void *rxBuf, size_t size) + * { + * // Make sure we received all expected bytes + * if (size == wantedRxBytes) { + * // Copy bytes from RX buffer to TX buffer + * for (size_t i = 0; i < size; i++) + * txBuf[i] = ((uint8_t*)rxBuf)[i]; + * + * // Echo the bytes received back to transmitter + * UART_write(handle, txBuf, size); + * + * // Start another read, with size the same as it was during first call to + * // UART_read() + * UART_read(handle, rxBuf, wantedRxBytes); + * } + * else { + * // Handle error or call to UART_readCancel() + * } + * } + * + * // Write callback function + * static void writeCallback(UART_Handle handle, void *rxBuf, size_t size) + * { + * // Do nothing + * } + * + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * UART_Handle handle; + * UART_Params params; + * + * // Init UART + * UART_init(); + * + * // Specify non-default parameters + * UART_Params_init(¶ms); + * params.baudRate = 9600; + * params.writeMode = UART_MODE_CALLBACK; + * params.writeDataMode = UART_DATA_BINARY; + * params.writeCallback = writeCallback; + * params.readMode = UART_MODE_CALLBACK; + * params.readDataMode = UART_DATA_BINARY; + * params.readCallback = readCallback; + * + * // Open the UART and initiate the first read + * handle = UART_open(Board_UART, ¶ms); + * wantedRxBytes = 16; + * int rxBytes = UART_read(handle, rxBuf, wantedRxBytes); + * + * while(true); // Wait forever + * } + * @endcode + * + * # Baud Rate # + * The CC26xx driver supports baud rates up to 3Mbaud. + * However, when receiving more than 32 bytes back-to-back the baud + * rate is limited to approximately 2Mbaud. + * The throughput is also dependent on the user application. + * + * # Stack requirements # + * There are no additional stack requirements for calling UART_read() within + * its own callback. + * + * ============================================================================ + */ + +#ifndef ti_drivers_uart_UARTCC26X0__include +#define ti_drivers_uart_UARTCC26X0__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + + +/*! + * @brief No hardware flow control + */ +#define UARTCC26X0_FLOWCTRL_NONE 0 + +/*! + * @brief Hardware flow control + */ +#define UARTCC26X0_FLOWCTRL_HARDWARE 1 + +/** + * @addtogroup UART_STATUS + * UARTCC26X0_STATUS_* macros are command codes only defined in the + * UARTCC26X0.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add UARTCC26X0_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup UART_CMD + * UARTCC26X0_CMD_* macros are command codes only defined in the + * UARTCC26X0.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/*! + * @brief Command used by UART_control to enable partial return + * + * Enabling this command allows UART_read to return partial data if data + * reception is inactive for a given 32-bit period. With this command @b arg + * is @a don't @a care and it returns UART_STATUS_SUCCESS. + */ +#define UARTCC26X0_CMD_RETURN_PARTIAL_ENABLE (UART_CMD_RESERVED + 0) + +/*! + * @brief Command used by UART_control to disable partial return + * + * Disabling this command returns the UARTCC26X0 to the default blocking + * behavior where UART_read blocks until all data bytes were received. With + * this comand @b arg is @a don't @a care and it returns UART_STATUS_SUCCESS. + */ +#define UARTCC26X0_CMD_RETURN_PARTIAL_DISABLE (UART_CMD_RESERVED + 1) + +/*! + * @brief Command used by UART_control to flush the RX FIFO + * + * This control command flushes any contents in the RX FIFO. With this command + * @b arg is @a don't @a care and it returns UART_STATUS_SUCCESS. + */ +#define UARTCC26X0_CMD_RX_FIFO_FLUSH (UART_CMD_RESERVED + 2) + + +/** @}*/ + +/*! Size of the TX and RX FIFOs is 32 items */ +#define UARTCC26X0_FIFO_SIZE 32 + +/*! + * @brief UART TX/RX interrupt FIFO threshold select + * + * Defined FIFO thresholds for generation of both TX interrupt and RX + * interrupt. The default value (UARTCC26X0_FIFO_THRESHOLD_DEFAULT) is + * defined for backwards compatibility handling. If the RX and TX FIFO + & thresholds are not set in the HwAttrs, or are set to + * UARTCC26X0_FIFO_THRESHOLD_DEFAULT, the RX interrupt FIFO threshold is + * set to 4/8 full, and the TX interrupt FIFO threshold is set to 1/8 + * full. + */ +typedef enum UARTCC26X0_FifoThreshold { + UARTCC26X0_FIFO_THRESHOLD_DEFAULT = 0, /*!< Use default FIFO threshold */ + UARTCC26X0_FIFO_THRESHOLD_1_8, /*!< FIFO threshold of 1/8 full */ + UARTCC26X0_FIFO_THRESHOLD_2_8, /*!< FIFO threshold of 2/8 full */ + UARTCC26X0_FIFO_THRESHOLD_4_8, /*!< FIFO threshold of 4/8 full */ + UARTCC26X0_FIFO_THRESHOLD_6_8, /*!< FIFO threshold of 6/8 full */ + UARTCC26X0_FIFO_THRESHOLD_7_8 /*!< FIFO threshold of 7/8 full */ +} UARTCC26X0_FifoThreshold; + +/*! + * @brief The definition of an optional callback function used by the + * UART driver to notify the application when a receive error + * (FIFO overrun, parity error, etc) occurs. + * + * @param UART_Handle UART_Handle + * + * @param error The current value of the receive + * status register. + */ +typedef void (*UARTCC26X0_ErrorCallback) (UART_Handle handle, uint32_t error); + +/* UART function table pointer */ +extern const UART_FxnTable UARTCC26X0_fxnTable; + +/*! + * @brief UARTCC26X0 Hardware attributes + * + * The fields, baseAddr and intNum are used by driverlib + * APIs and therefore must be populated by + * driverlib macro definitions. These definitions are found under the + * device family in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * - driverlib/uart.h + * + * intPriority is the UART peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * The CC26xx uses three of the priority bits, meaning ~0 has the same + * effect as (7 << 5). + * + * (7 << 5) will apply the lowest priority. + * (1 << 5) will apply the highest priority. + * + * Setting the priority to 0 is not supported by this driver. HWI's with + * priority 0 ignore the HWI dispatcher to support zero-latency interrupts, + * thus invalidating the critical sections in this driver. + * + * A sample structure is shown below: + * @code + * unsigned char uartCC26X0RingBuffer[2][32]; + * + * const UARTCC26X0_HWAttrs uartCC26X0HWAttrs[] = { + * { + * .baseAddr = UARTA0_BASE, + * .intNum = INT_UART0_COMB, + * .intPriority = (~0), + * .swiPriority = 0, + * .ringBufPtr = uartCC26X0RingBuffer[0], + * .ringBufSize = sizeof(uartCC26X0RingBuffer[0]), + * .flowControl = UARTCC26X0_FLOWCTRL_NONE, + * .rxPin = IOID_2, + * .txPin = IOID_3, + * .ctsPin = PIN_UNASSIGNED, + * .rtsPin = PIN_UNASSIGNED, + * .txIntFifoThr = UARTCC26X0_FIFO_THRESHOLD_1_8, + * .rxIntFifoThr = UARTCC26X0_FIFO_THRESHOLD_4_8, + * .errorFxn = NULL + * } + * }; + * @endcode + */ +typedef struct UARTCC26X0_HWAttrs { + /*! UART Peripheral's base address */ + uint32_t baseAddr; + /*! UART Peripheral's interrupt vector */ + int intNum; + /*! UART Peripheral's interrupt priority */ + uint8_t intPriority; + /*! + * @brief Swi priority. + * The higher the number, the higher the priority. The minimum + * priority is 0 and the maximum is defined by the underlying OS. + */ + uint32_t swiPriority; + /*! Hardware flow control setting */ + uint32_t flowControl; + /*! Pointer to an application ring buffer */ + unsigned char *ringBufPtr; + /*! Size of ringBufPtr */ + size_t ringBufSize; + /*! UART RX pin assignment */ + uint8_t rxPin; + /*! UART TX pin assignment */ + uint8_t txPin; + /*! UART clear to send (CTS) pin assignment */ + uint8_t ctsPin; + /*! UART request to send (RTS) pin assignment */ + uint8_t rtsPin; + /*! UART TX interrupt FIFO threshold select */ + UARTCC26X0_FifoThreshold txIntFifoThr; + /*! UART RX interrupt FIFO threshold select */ + UARTCC26X0_FifoThreshold rxIntFifoThr; + /*! Application error function to be called on receive errors */ + UARTCC26X0_ErrorCallback errorFxn; +} UARTCC26X0_HWAttrs; + +/*! + * @brief UARTCC26X0 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct UARTCC26X0_Object { + /* UART state variable */ + struct { + bool opened:1; /* Has the obj been opened */ + UART_Mode readMode:1; /* Mode for all read calls */ + UART_Mode writeMode:1; /* Mode for all write calls */ + UART_DataMode readDataMode:1; /* Type of data being read */ + UART_DataMode writeDataMode:1; /* Type of data being written */ + UART_ReturnMode readReturnMode:1; /* Receive return mode */ + UART_Echo readEcho:1; /* Echo received data back */ + /* + * Flag to determine if a timeout has occurred when the user called + * UART_read(). This flag is set by the timeoutClk clock object. + */ + bool bufTimeout:1; + /* + * Flag to determine when an ISR needs to perform a callback; in both + * UART_MODE_BLOCKING or UART_MODE_CALLBACK + */ + bool callCallback:1; + /* + * Flag to determine if the ISR is in control draining the ring buffer + * when in UART_MODE_CALLBACK + */ + bool drainByISR:1; + /* Keep track of RX enabled state set by app with UART_control() */ + bool ctrlRxEnabled:1; + /* Flag to keep the state of the read Power constraints */ + bool rxEnabled:1; + /* Flag to keep the state of the write Power constraints */ + bool txEnabled:1; + } state; + + HwiP_Struct hwi; /* Hwi object for interrupts */ + SwiP_Struct swi; /* Swi for read/write callbacks */ + ClockP_Struct timeoutClk; /* Clock object to for timeouts */ + ClockP_Struct txFifoEmptyClk; /* UART TX FIFO empty clock */ + uint32_t baudRate; /* Baud rate for UART */ + UART_LEN dataLength; /* Data length for UART */ + UART_STOP stopBits; /* Stop bits for UART */ + UART_PAR parityType; /* Parity bit type for UART */ + uint32_t status; /* RX status */ + + /* UART read variables */ + RingBuf_Object ringBuffer; /* local circular buffer object */ + unsigned char *readBuf; /* Buffer data pointer */ + size_t readSize; /* Desired number of bytes to read */ + size_t readCount; /* Number of bytes left to read */ + SemaphoreP_Struct readSem; /* UART read semaphore */ + unsigned int readTimeout; /* Timeout for read semaphore */ + UART_Callback readCallback; /* Pointer to read callback */ + bool readRetPartial; /* Return partial RX data if timeout occurs */ + + /* UART write variables */ + const unsigned char *writeBuf; /* Buffer data pointer */ + size_t writeSize; /* Desired number of bytes to write*/ + size_t writeCount; /* Number of bytes left to write */ + SemaphoreP_Struct writeSem; /* UART write semaphore*/ + unsigned int writeTimeout; /* Timeout for write semaphore */ + UART_Callback writeCallback; /* Pointer to write callback */ + unsigned int writeEmptyClkTimeout; /* TX FIFO timeout tick count */ + + /* PIN driver state object and handle */ + PIN_State pinState; + PIN_Handle hPin; + + /* For Power management */ + Power_NotifyObj postNotify; +} UARTCC26X0_Object, *UARTCC26X0_Handle; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_uart_UARTCC26X0__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X2.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X2.c new file mode 100644 index 0000000..70d4a56 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X2.c @@ -0,0 +1,1439 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/* + * By default disable both asserts and log for this module. + * This must be done before DebugP.h is included. + */ +#ifndef DebugP_ASSERT_ENABLED +#define DebugP_ASSERT_ENABLED 0 +#endif +#ifndef DebugP_LOG_ENABLED +#define DebugP_LOG_ENABLED 0 +#endif + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/uart.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) + +/* Size of the TX and RX FIFOs is 32 items */ +#define FIFO_SIZE 32 + +#define READTIMEDOUT 0x10 +#define UART_BE_PE_FE 0x700 /* Break, parity, or framing error */ + +#define UARTCC26X2_RXERROR (UART_RXERROR_OVERRUN | UART_RXERROR_BREAK | \ + UART_RXERROR_PARITY | UART_RXERROR_FRAMING) + +/* UARTCC26X2 functions */ +void UARTCC26X2_close(UART_Handle handle); +int_fast16_t UARTCC26X2_control(UART_Handle handle, uint_fast16_t cmd, + void *arg); +void UARTCC26X2_init(UART_Handle handle); +UART_Handle UARTCC26X2_open(UART_Handle handle, UART_Params *params); +int_fast32_t UARTCC26X2_read(UART_Handle handle, void *buffer, size_t size); +int_fast32_t UARTCC26X2_readPolling(UART_Handle handle, void *buf, + size_t size); +int_fast32_t UARTCC26X2_readPollingNotImpl(UART_Handle handle, void *buf, + size_t size); +void UARTCC26X2_readCancel(UART_Handle handle); +int_fast32_t UARTCC26X2_write(UART_Handle handle, const void *buffer, + size_t size); +int_fast32_t UARTCC26X2_writePolling(UART_Handle handle, const void *buf, + size_t size); +int_fast32_t UARTCC26X2_writePollingNotImpl(UART_Handle handle, + const void *buf, size_t size); +void UARTCC26X2_writeCancel(UART_Handle handle); + +/* Static functions */ +static void UARTCC26X2_hwiIntFxn(uintptr_t arg); +static void disableRX(UART_Handle handle); +static void enableRX(UART_Handle handle); +static uint_fast16_t getPowerMgrId(uint32_t baseAddr); +static void initHw(UART_Handle handle); +static bool initIO(UART_Handle handle); +static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + uintptr_t clientArg); +static void readBlockingTimeout(uintptr_t arg); +static void readIsr(UART_Handle handle, uint32_t status); +static void readSemCallback(UART_Handle handle, void *buffer, size_t count); +static int readTaskBlocking(UART_Handle handle); +static int readTaskCallback(UART_Handle handle); +static int ringBufGet(UART_Handle handle, unsigned char *data); +static void swiReadCallback(uintptr_t arg0, uintptr_t arg1); +static void swiWriteCallback(uintptr_t arg0, uintptr_t arg1); +static void writeData(UART_Handle handle); +static void writeSemCallback(UART_Handle handle, void *buffer, size_t count); + +/* + * Function for checking whether flow control is enabled. + */ +static inline bool isFlowControlEnabled(UARTCC26X2_HWAttrs const *hwAttrs) { + return ((hwAttrs->flowControl == UARTCC26X2_FLOWCTRL_HARDWARE) && + (hwAttrs->ctsPin != PIN_UNASSIGNED) && (hwAttrs->rtsPin != PIN_UNASSIGNED)); +} + +/* UART function table for UARTCC26X2 implementation */ +const UART_FxnTable UARTCC26X2_fxnTable = { + UARTCC26X2_close, + UARTCC26X2_control, + UARTCC26X2_init, + UARTCC26X2_open, + UARTCC26X2_read, + UARTCC26X2_readPollingNotImpl, + UARTCC26X2_readCancel, + UARTCC26X2_write, + UARTCC26X2_writePollingNotImpl, + UARTCC26X2_writeCancel +}; + +static const uint32_t dataLength[] = { + UART_CONFIG_WLEN_5, /* UART_LEN_5 */ + UART_CONFIG_WLEN_6, /* UART_LEN_6 */ + UART_CONFIG_WLEN_7, /* UART_LEN_7 */ + UART_CONFIG_WLEN_8 /* UART_LEN_8 */ +}; + +static const uint32_t stopBits[] = { + UART_CONFIG_STOP_ONE, /* UART_STOP_ONE */ + UART_CONFIG_STOP_TWO /* UART_STOP_TWO */ +}; + +static const uint32_t parityType[] = { + UART_CONFIG_PAR_NONE, /* UART_PAR_NONE */ + UART_CONFIG_PAR_EVEN, /* UART_PAR_EVEN */ + UART_CONFIG_PAR_ODD, /* UART_PAR_ODD */ + UART_CONFIG_PAR_ZERO, /* UART_PAR_ZERO */ + UART_CONFIG_PAR_ONE /* UART_PAR_ONE */ +}; + +/* + * Array for mapping of FIFO threshold defines selected by board files to + * TX FIFO threshold define used by driverlib FIFO threshold defines + * (enum UARTCC26X2_FifoThreshold) must be used as the array index. + * Index 0 handles backward compatibility with legacy board files that + * don't select any FIFO thresholds. + */ +static const uint8_t txFifoThreshold[6] = { + UART_FIFO_TX1_8, /* UARTCC26X2_FIFO_THRESHOLD_DEFAULT */ + UART_FIFO_TX1_8, /* UARTCC26X2_FIFO_THRESHOLD_1_8 */ + UART_FIFO_TX2_8, /* UARTCC26X2_FIFO_THRESHOLD_2_8 */ + UART_FIFO_TX4_8, /* UARTCC26X2_FIFO_THRESHOLD_4_8 */ + UART_FIFO_TX6_8, /* UARTCC26X2_FIFO_THRESHOLD_6_8 */ + UART_FIFO_TX7_8 /* UARTCC26X2_FIFO_THRESHOLD_7_8 */ +}; + +/* + * Array for mapping of FIFO threshold defines selected by board files to + * RX FIFO threshold define used by driverlib FIFO threshold defines + * (enum UARTCC26X2_FifoThreshold) must be used as the array index. + * Index 0 handles backward compatibility with legacy board files that + * don't select any FIFO thresholds. + */ +static const uint8_t rxFifoThreshold[6] = { + UART_FIFO_RX4_8, /* UARTCC26X2_FIFO_THRESHOLD_DEFAULT */ + UART_FIFO_RX1_8, /* UARTCC26X2_FIFO_THRESHOLD_1_8 */ + UART_FIFO_RX2_8, /* UARTCC26X2_FIFO_THRESHOLD_2_8 */ + UART_FIFO_RX4_8, /* UARTCC26X2_FIFO_THRESHOLD_4_8 */ + UART_FIFO_RX6_8, /* UARTCC26X2_FIFO_THRESHOLD_6_8 */ + UART_FIFO_RX7_8 /* UARTCC26X2_FIFO_THRESHOLD_7_8 */ +}; + +/* + * Array for mapping of FIFO threshold defines selected by board files to + * number of bytes in the RX FIFO threshold. + */ +static const uint8_t rxFifoBytes[6] = { + 16, /* UARTCC26X2_FIFO_THRESHOLD_DEFAULT */ + 4, /* UARTCC26X2_FIFO_THRESHOLD_1_8 */ + 8, /* UARTCC26X2_FIFO_THRESHOLD_2_8 */ + 16, /* UARTCC26X2_FIFO_THRESHOLD_4_8 */ + 24, /* UARTCC26X2_FIFO_THRESHOLD_6_8 */ + 28 /* UARTCC26X2_FIFO_THRESHOLD_7_8 */ +}; + +/* + * ======== UARTCC26X2_close ======== + */ +void UARTCC26X2_close(UART_Handle handle) +{ + UARTCC26X2_Object *object = handle->object; + UARTCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Deallocate pins */ + PIN_close(object->hPin); + + /* Disable UART and interrupts. */ + UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX | UART_INT_RX | + UART_INT_RT | UART_INT_OE | UART_INT_BE | UART_INT_PE | + UART_INT_FE | UART_INT_CTS); + + /* Set to false to allow UARTCC26X2_readCancel() to release constraint */ + object->state.ctrlRxEnabled = false; + + object->state.opened = false; + + /* Cancel any possible ongoing reads/writes */ + UARTCC26X2_writeCancel(handle); + UARTCC26X2_readCancel(handle); + + /* + * Disable the UART. Do not call driverlib function + * UARTDisable() since it polls for BUSY bit to clear + * before disabling the UART FIFO and module. + */ + /* Disable UART FIFO */ + HWREG(hwAttrs->baseAddr + UART_O_LCRH) &= ~(UART_LCRH_FEN); + /* Disable UART module */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); + + HwiP_destruct(&(object->hwi)); + if (object->state.writeMode == UART_MODE_BLOCKING) { + SemaphoreP_destruct(&(object->writeSem)); + } + if (object->state.readMode == UART_MODE_BLOCKING) { + SemaphoreP_destruct(&(object->readSem)); + ClockP_destruct(&(object->timeoutClk)); + } + SwiP_destruct(&(object->readSwi)); + SwiP_destruct(&(object->writeSwi)); + + /* Unregister power notification objects */ + Power_unregisterNotify(&object->postNotify); + + /* Release power dependency - i.e. potentially power down serial domain. */ + Power_releaseDependency(object->powerMgrId); + + DebugP_log1("UART:(%p) closed", hwAttrs->baseAddr); +} + + +/* + * ======== UARTCC26X2_control ======== + */ +int_fast16_t UARTCC26X2_control(UART_Handle handle, uint_fast16_t cmd, + void *arg) +{ + UARTCC26X2_Object *object = handle->object; + UARTCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + unsigned char data; + int bufferCount; + uintptr_t key; + + bufferCount = RingBuf_peek(&object->ringBuffer, &data); + + switch (cmd) { + /* Common UART CMDs */ + case (UART_CMD_PEEK): + *(int *)arg = (bufferCount) ? data : UART_ERROR; + DebugP_log2("UART:(%p) UART_CMD_PEEK: %d", hwAttrs->baseAddr, + *(uintptr_t*)arg); + return (UART_STATUS_SUCCESS); + + case (UART_CMD_ISAVAILABLE): + *(bool *)arg = (bufferCount != 0); + DebugP_log2("UART:(%p) UART_CMD_ISAVAILABLE: %d", + hwAttrs->baseAddr, *(uintptr_t*)arg); + return (UART_STATUS_SUCCESS); + + case (UART_CMD_GETRXCOUNT): + *(int *)arg = bufferCount; + DebugP_log2("UART:(%p) UART_CMD_GETRXCOUNT: %d", hwAttrs->baseAddr, + *(uintptr_t*)arg); + return (UART_STATUS_SUCCESS); + + case (UART_CMD_RXENABLE): + object->state.ctrlRxEnabled = true; + enableRX(handle); + return (UART_STATUS_SUCCESS); + + case (UART_CMD_RXDISABLE): + object->state.ctrlRxEnabled = false; + disableRX(handle); + return (UART_STATUS_SUCCESS); + + /* Specific UART CMDs */ + case UARTCC26X2_CMD_RETURN_PARTIAL_ENABLE: + /* Enable RETURN_PARTIAL */ + object->readRetPartial = true; + return (UART_STATUS_SUCCESS); + + case UARTCC26X2_CMD_RETURN_PARTIAL_DISABLE: + /* Disable RETURN_PARTIAL */ + object->readRetPartial = false; + return (UART_STATUS_SUCCESS); + + case UARTCC26X2_CMD_RX_FIFO_FLUSH: + /* Flush RX FIFO */ + /* Disable interrupts to avoid reading data while changing state */ + key = HwiP_disable(); + + /* Read RX FIFO until empty */ + while (((int32_t)UARTCharGetNonBlocking(hwAttrs->baseAddr)) != -1); + + /* Reset RingBuf */ + object->ringBuffer.count = 0; + object->ringBuffer.head = object->ringBuffer.length - 1; + object->ringBuffer.tail = 0; + + /* Set size = 0 to prevent reading and restore interrupts. */ + object->readSize = 0; + HwiP_restore(key); + + return (UART_STATUS_SUCCESS); + + default: + return (UART_STATUS_UNDEFINEDCMD); + } +} + +/* + * ======== UARTCC26X2_hwiIntFxn ======== + * Hwi function that processes UART interrupts. + */ +static void UARTCC26X2_hwiIntFxn(uintptr_t arg) +{ + uint32_t status; + UARTCC26X2_HWAttrs const *hwAttrs = ((UART_Handle)arg)->hwAttrs; + + /* Clear interrupts */ + status = UARTIntStatus(hwAttrs->baseAddr, true); + UARTIntClear(hwAttrs->baseAddr, status); + + if (status & (UART_INT_RX | UART_INT_RT | UART_INT_OE | UART_INT_BE | + UART_INT_PE | UART_INT_FE)) { + readIsr((UART_Handle)arg, status); + } + + if (status & (UART_INT_TX | UART_INT_EOT)) { + writeData((UART_Handle)arg); + } +} + +/* + * ======== UARTCC26X2_init ======== + */ +void UARTCC26X2_init(UART_Handle handle) +{ +} + +/* + * ======== UARTCC26X2_open ======== + */ +UART_Handle UARTCC26X2_open(UART_Handle handle, UART_Params *params) +{ + uintptr_t key; + UARTCC26X2_Object *object = handle->object; + UARTCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + /* Use union to save on stack allocation */ + union { + HwiP_Params hwiParams; + ClockP_Params clkParams; + SwiP_Params swiParams; + } paramsUnion; + + + /* Check for callback when in UART_MODE_CALLBACK */ + DebugP_assert((params->readMode != UART_MODE_CALLBACK) || + (params->readCallback != NULL)); + DebugP_assert((params->writeMode != UART_MODE_CALLBACK) || + (params->writeCallback != NULL)); + + key = HwiP_disable(); + + if (object->state.opened == true) { + HwiP_restore(key); + + DebugP_log1("UART:(%p) already in use.", hwAttrs->baseAddr); + return (NULL); + } + object->state.opened = true; + + HwiP_restore(key); + + object->state.readMode = params->readMode; + object->state.writeMode = params->writeMode; + object->state.readReturnMode = params->readReturnMode; + object->state.readDataMode = params->readDataMode; + object->state.writeDataMode = params->writeDataMode; + object->state.readEcho = params->readEcho; + object->readTimeout = params->readTimeout; + object->writeTimeout = params->writeTimeout; + object->readCallback = params->readCallback; + object->writeCallback = params->writeCallback; + object->baudRate = params->baudRate; + object->stopBits = params->stopBits; + object->dataLength = params->dataLength; + object->parityType = params->parityType; + + /* Set UART transaction variables to defaults. */ + object->writeBuf = NULL; + object->readBuf = NULL; + object->writeCount = 0; + object->readCount = 0; + object->writeSize = 0; + object->readSize = 0; + object->status = 0; + object->readRetPartial = false; + object->state.rxEnabled = false; + object->state.ctrlRxEnabled = false; + object->state.txEnabled = false; + object->state.drainByISR = false; + + /* Create circular buffer object to be used for read buffering */ + RingBuf_construct(&object->ringBuffer, hwAttrs->ringBufPtr, + hwAttrs->ringBufSize); + + /* Get the Power resource Id from the base address */ + object->powerMgrId = getPowerMgrId(hwAttrs->baseAddr); + if (object->powerMgrId >= PowerCC26X2_NUMRESOURCES) { + DebugP_log1("UART:(%p) Failed to determine Power resource id", + hwAttrs->baseAddr); + return (NULL); + } + + /* Register power dependency - i.e. power up and enable clock for UART. */ + Power_setDependency(object->powerMgrId); + + UARTDisable(hwAttrs->baseAddr); + + /* Configure IOs, make sure it was successful */ + if (!initIO(handle)) { + /* Another driver or application already using these pins. */ + DebugP_log0("Could not allocate pins, already in use."); + /* Release power dependency */ + Power_releaseDependency(object->powerMgrId); + /* Mark the module as available */ + object->state.opened = false; + return (NULL); + } + + /* Initialize the UART hardware module */ + initHw(handle); + + /* Register notification function */ + Power_registerNotify(&object->postNotify, PowerCC26XX_AWAKE_STANDBY, + postNotifyFxn, (uintptr_t)handle); + + /* Create Hwi object for this UART peripheral. */ + HwiP_Params_init(&(paramsUnion.hwiParams)); + paramsUnion.hwiParams.arg = (uintptr_t)handle; + paramsUnion.hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), hwAttrs->intNum, UARTCC26X2_hwiIntFxn, + &(paramsUnion.hwiParams)); + + SwiP_Params_init(&(paramsUnion.swiParams)); + paramsUnion.swiParams.arg0 = (uintptr_t)handle; + paramsUnion.swiParams.priority = hwAttrs->swiPriority; + SwiP_construct(&(object->readSwi), swiReadCallback, &(paramsUnion.swiParams)); + + SwiP_construct(&(object->writeSwi), swiWriteCallback, &(paramsUnion.swiParams)); + + /* If read mode is blocking create a semaphore and set callback. */ + if (object->state.readMode == UART_MODE_BLOCKING) { + /* Timeout clock for reads */ + ClockP_Params_init(&(paramsUnion.clkParams)); + paramsUnion.clkParams.arg = (uintptr_t)handle; + + ClockP_construct(&(object->timeoutClk), + (ClockP_Fxn)&readBlockingTimeout, 0 /* timeout */, + &(paramsUnion.clkParams)); + + SemaphoreP_constructBinary(&(object->readSem), 0); + object->readCallback = &readSemCallback; + } + + /* If write mode is blocking create a semaphore and set callback. */ + if (object->state.writeMode == UART_MODE_BLOCKING) { + SemaphoreP_constructBinary(&(object->writeSem), 0); + object->writeCallback = &writeSemCallback; + } + + /* UART opened successfully */ + DebugP_log1("UART:(%p) opened", hwAttrs->baseAddr); + + /* Return the handle */ + return (handle); +} + +/* + * ======== UARTCC26X2_read ======== + */ +int_fast32_t UARTCC26X2_read(UART_Handle handle, void *buffer, size_t size) +{ + uintptr_t key; + UARTCC26X2_Object *object = handle->object; + int32_t bytesRead; + + key = HwiP_disable(); + + if (!object->state.opened || + ((object->state.readMode == UART_MODE_CALLBACK) && + object->readSize)) { + HwiP_restore(key); + return (UART_ERROR); + } + + /* Save the data to be read and restore interrupts. */ + object->readBuf = buffer; + object->readSize = size; + object->readCount = size; + object->status = 0; /* Clear read timeout or other errors */ + + HwiP_restore(key); + + enableRX(handle); + + if (object->state.readMode == UART_MODE_CALLBACK) { + /* Return value of readTaskCallback() should be 0 */ + bytesRead = readTaskCallback(handle); + } + else { + bytesRead = readTaskBlocking(handle); + /* + * Set the readCount to 0 so as not to trigger a read timeout + * interrupt in case more data comes in. + */ + object->readCount = 0; + } + + return (bytesRead); +} + +/* + * ======== UARTCC26X2_readCancel ======== + */ +void UARTCC26X2_readCancel(UART_Handle handle) +{ + uintptr_t key; + UARTCC26X2_Object *object = handle->object; + + disableRX(handle); + + if ((object->state.readMode != UART_MODE_CALLBACK) || + (object->readSize == 0)) { + return; + } + + key = HwiP_disable(); + + object->state.drainByISR = false; + /* + * Indicate that what we've currently received is what we asked for so that + * the existing logic handles the completion. + */ + object->readSize -= object->readCount; + object->readCount = 0; + + HwiP_restore(key); + + /* + * Trigger the RX callback function, even if no data is in the + * buffer. The ISR might not have been triggered yet because the + * FIFO trigger level has not been reached. + */ + SwiP_post(&(object->readSwi)); +} + +/* + * ======== UARTCC26X2_readPolling ======== + */ +int_fast32_t UARTCC26X2_readPolling(UART_Handle handle, void *buf, size_t size) +{ + int32_t count = 0; + UARTCC26X2_Object *object = handle->object; + UARTCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + unsigned char *buffer = (unsigned char *)buf; + uintptr_t key; + + /* Read characters. */ + while (size) { + /* Grab data from the RingBuf before getting it from the RX data reg */ + key = HwiP_disable(); + UARTIntDisable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT); + HwiP_restore(key); + + if (RingBuf_get(&object->ringBuffer, buffer) == -1) { + *buffer = UARTCharGet(hwAttrs->baseAddr); + } + + key = HwiP_disable(); + if (object->state.rxEnabled) { + UARTIntEnable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT); + } + HwiP_restore(key); + + DebugP_log2("UART:(%p) Read character 0x%x", hwAttrs->baseAddr, + *buffer); + count++; + size--; + + if (object->state.readDataMode == UART_DATA_TEXT && *buffer == '\r') { + /* Echo character if enabled. */ + if (object->state.readEcho) { + UARTCharPut(hwAttrs->baseAddr, '\r'); + } + *buffer = '\n'; + } + + /* Echo character if enabled. */ + if (object->state.readDataMode == UART_DATA_TEXT && + object->state.readEcho) { + UARTCharPut(hwAttrs->baseAddr, *buffer); + } + + /* If read return mode is newline, finish if a newline was received. */ + if (object->state.readDataMode == UART_DATA_TEXT && + object->state.readReturnMode == UART_RETURN_NEWLINE && + *buffer == '\n') { + return (count); + } + + buffer++; + } + + DebugP_log2("UART:(%p) Read polling finished, %d bytes read", + hwAttrs->baseAddr, count); + + return (count); +} + +/* + * ======== UARTCC26X2_readPollingNotImpl ======== + */ +int_fast32_t UARTCC26X2_readPollingNotImpl(UART_Handle handle, void *buf, + size_t size) +{ + /* Not supported */ + return (UART_ERROR); +} + +/* + * ======== UARTCC26X2_write ======== + */ +int_fast32_t UARTCC26X2_write(UART_Handle handle, const void *buffer, + size_t size) +{ + UARTCC26X2_Object *object = handle->object; + UARTCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + + if (size == 0) { + return (0); + } + + key = HwiP_disable(); + + /* + * Make sure any previous write has fininshed. If TX is still + * enabled, then writeSwi has not yet been posted. + */ + if (!object->state.opened || object->state.txEnabled) { + HwiP_restore(key); + DebugP_log1("UART:(%p) Could not write data, uart closed or in use.", + hwAttrs->baseAddr); + + return (UART_ERROR); + } + + /* Save the data to be written and restore interrupts. */ + object->writeBuf = buffer; + object->writeSize = size; + object->writeCount = size; + + object->state.txEnabled = true; + + /* Set constraints to guarantee transaction */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Enable TX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_TXE; + + DebugP_log1("UART:(%p) UART_write set write power constraint", + hwAttrs->baseAddr); + + HwiP_restore(key); + + if (!(UARTIntStatus(hwAttrs->baseAddr, false) & UART_INT_TX)) { + /* + * Start the transfer going if the raw interrupt status TX bit + * is 0. This will cause the ISR to fire when we enable + * UART_INT_TX. If the RIS TX bit is not cleared, we don't + * need to call writeData(), since the ISR will fire once we + * enable the interrupt, causing the transfer to start. + */ + writeData(handle); + } + if (object->writeCount) { + key = HwiP_disable(); + UARTIntEnable(hwAttrs->baseAddr, UART_INT_TX); + HwiP_restore(key); + } + + /* If writeMode is blocking, block and get the state. */ + if (object->state.writeMode == UART_MODE_BLOCKING) { + /* Pend on semaphore and wait for Hwi to finish. */ + if (SemaphoreP_OK != SemaphoreP_pend(&(object->writeSem), + object->writeTimeout)) { + /* Semaphore timed out, make the write empty and log the write. */ + key = HwiP_disable(); + UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX | UART_INT_EOT); + UARTIntClear(hwAttrs->baseAddr, UART_INT_TX | UART_INT_EOT); + + if (object->state.txEnabled) { + + /* Disable TX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_TXE); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + object->state.txEnabled = false; + } + HwiP_restore(key); + + DebugP_log2("UART:(%p) Write timed out, %d bytes written", + hwAttrs->baseAddr, object->writeCount); + } + return (object->writeSize - object->writeCount); + } + + return (0); +} + +/* + * ======== UARTCC26X2_writeCancel ======== + */ +void UARTCC26X2_writeCancel(UART_Handle handle) +{ + uintptr_t key; + UARTCC26X2_Object *object = handle->object; + UARTCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + key = HwiP_disable(); + + /* Return if there is no write. */ + if (!object->state.txEnabled) { + HwiP_restore(key); + return; + } + + UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX | UART_INT_EOT); + UARTIntClear(hwAttrs->baseAddr, UART_INT_TX | UART_INT_EOT); + + /* Release constraint since transaction is done */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + object->state.txEnabled = false; + + /* Disable TX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_TXE); + + HwiP_restore(key); + + object->writeCallback(handle, (void *)object->writeBuf, + object->writeSize - object->writeCount); + + DebugP_log2("UART:(%p) Write canceled, %d bytes written", + hwAttrs->baseAddr, object->writeSize - object->writeCount); +} + +/* + * ======== UARTCC26X2_writePolling ======== + */ +int_fast32_t UARTCC26X2_writePolling(UART_Handle handle, const void *buf, + size_t size) +{ + int32_t count = 0; + UARTCC26X2_Object *object = handle->object; + UARTCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + unsigned char *buffer = (unsigned char *)buf; + uintptr_t key; + + /* Enable TX */ + key = HwiP_disable(); + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_TXE; + HwiP_restore(key); + + /* Write characters. */ + while (size) { + if (object->state.writeDataMode == UART_DATA_TEXT && *buffer == '\n') { + UARTCharPut(hwAttrs->baseAddr, '\r'); + count++; + } + UARTCharPut(hwAttrs->baseAddr, *buffer); + + DebugP_log2("UART:(%p) Wrote character 0x%x", hwAttrs->baseAddr, + *buffer); + buffer++; + count++; + size--; + } + + while (UARTBusy(hwAttrs->baseAddr)) { + ; + } + + /* Disable TX */ + key = HwiP_disable(); + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_TXE); + HwiP_restore(key); + + DebugP_log2("UART:(%p) Write polling finished, %d bytes written", + hwAttrs->baseAddr, count); + + return (count); +} + +/* + * ======== UARTCC26X2_writePollingNotImpl ======== + */ +int_fast32_t UARTCC26X2_writePollingNotImpl(UART_Handle handle, + const void *buf, size_t size) +{ + /* Not supported */ + return (UART_ERROR); +} + +/* + * ======== disableRX ======== + */ +static void disableRX(UART_Handle handle) +{ + UARTCC26X2_Object *object = handle->object; + UARTCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + + if (!object->state.ctrlRxEnabled) { + key = HwiP_disable(); + if (object->state.rxEnabled) { + UARTIntDisable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT | + UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE); + /* Disable RX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_RXE); + + object->state.rxEnabled = false; + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + HwiP_restore(key); + } +} + +/* + * ======== enableRX ======== + */ +static void enableRX(UART_Handle handle) +{ + UARTCC26X2_Object *object = handle->object; + UARTCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + + key = HwiP_disable(); + if (!object->state.rxEnabled) { + /* Set constraint for sleep to guarantee transaction */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Enable RX and receive interrupts */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_RXE; + UARTIntEnable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT | + UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE); + + object->state.rxEnabled = true; + } + HwiP_restore(key); +} + +/* + * ======== getPowerMgrId ======== + */ +static uint_fast16_t getPowerMgrId(uint32_t baseAddr) +{ + switch (baseAddr) { + case UART0_BASE: + return (PowerCC26XX_PERIPH_UART0); + case UART1_BASE: + return (PowerCC26X2_PERIPH_UART1); + default: + return ((uint_fast16_t)(~0U)); + } +} + +/* + * ======== initHw ======== + */ +static void initHw(UART_Handle handle) +{ + ClockP_FreqHz freq; + UARTCC26X2_Object *object = handle->object; + UARTCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* + * Configure frame format and baudrate. UARTConfigSetExpClk() disables + * the UART and does not re-enable it, so call this function first. + */ + ClockP_getCpuFreq(&freq); + UARTConfigSetExpClk(hwAttrs->baseAddr, freq.lo, object->baudRate, + dataLength[object->dataLength] | + stopBits[object->stopBits] | + parityType[object->parityType]); + + /* Clear all UART interrupts */ + UARTIntClear(hwAttrs->baseAddr, UART_INT_OE | UART_INT_BE | UART_INT_PE | + UART_INT_FE | UART_INT_RT | UART_INT_TX | + UART_INT_RX | UART_INT_CTS); + + /* Set TX interrupt FIFO level and RX interrupt FIFO level */ + UARTFIFOLevelSet(hwAttrs->baseAddr, txFifoThreshold[hwAttrs->txIntFifoThr], + rxFifoThreshold[hwAttrs->rxIntFifoThr]); + + /* If Flow Control is enabled, configure hardware flow control */ + if (isFlowControlEnabled(hwAttrs)) { + UARTHwFlowControlEnable(hwAttrs->baseAddr); + } + else { + UARTHwFlowControlDisable(hwAttrs->baseAddr); + } + + /* Enable UART FIFOs */ + HWREG(hwAttrs->baseAddr + UART_O_LCRH) |= UART_LCRH_FEN; + + /* Enable the UART module */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_UARTEN; + + if (object->state.ctrlRxEnabled) { + /* Enable RX */ + enableRX(handle); + } +} + +/* + * ======== initIO ======== + */ +static bool initIO(UART_Handle handle) +{ + /* Locals */ + UARTCC26X2_Object *object; + UARTCC26X2_HWAttrs const *hwAttrs; + PIN_Config uartPinTable[5]; + uint32_t pinCount = 0; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Build local list of pins, allocate through PIN driver and map ports */ + uartPinTable[pinCount++] = hwAttrs->rxPin | PIN_INPUT_EN; + /* + * Make sure UART_TX pin is driven high after calling PIN_open(...) until + * we've set the correct peripheral muxing in PINCC26XX_setMux(...). + * This is to avoid falling edge glitches when configuring the + * UART_TX pin. + */ + uartPinTable[pinCount++] = hwAttrs->txPin | PIN_INPUT_DIS | PIN_PUSHPULL | + PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH; + + if (isFlowControlEnabled(hwAttrs)) { + uartPinTable[pinCount++] = hwAttrs->ctsPin | PIN_INPUT_EN; + /* Avoiding glitches on the RTS, see comment for TX pin above. */ + uartPinTable[pinCount++] = hwAttrs->rtsPin | PIN_INPUT_DIS | + PIN_PUSHPULL | PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH; + } + + /* Terminate pin list */ + uartPinTable[pinCount] = PIN_TERMINATE; + + /* Open and assign pins through pin driver */ + object->hPin = PIN_open(&object->pinState, uartPinTable); + + /* Are pins already allocated */ + if (!object->hPin) { + return (false); + } + + /* Set IO muxing for the UART pins */ + PINCC26XX_setMux(object->hPin, hwAttrs->rxPin, + (hwAttrs->baseAddr == UART0_BASE ? + IOC_PORT_MCU_UART0_RX : IOC_PORT_MCU_UART1_RX)); + PINCC26XX_setMux(object->hPin, hwAttrs->txPin, + (hwAttrs->baseAddr == UART0_BASE ? + IOC_PORT_MCU_UART0_TX : IOC_PORT_MCU_UART1_TX)); + + if (isFlowControlEnabled(hwAttrs)) { + PINCC26XX_setMux(object->hPin, hwAttrs->ctsPin, + (hwAttrs->baseAddr == UART0_BASE ? + IOC_PORT_MCU_UART0_CTS : IOC_PORT_MCU_UART1_CTS)); + PINCC26XX_setMux(object->hPin, hwAttrs->rtsPin, + (hwAttrs->baseAddr == UART0_BASE ? + IOC_PORT_MCU_UART0_RTS : IOC_PORT_MCU_UART1_RTS)); + } + /* Success */ + return (true); +} + +/* + * ======== postNotifyFxn ======== + * Called by Power module when waking up from LPDS. + */ +static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + uintptr_t clientArg) +{ + /* Reconfigure the hardware if returning from sleep */ + if (eventType == PowerCC26XX_AWAKE_STANDBY) { + initHw((UART_Handle) clientArg); + } + + return (Power_NOTIFYDONE); +} + +/* + * ======== readBlockingTimeout ======== + */ +static void readBlockingTimeout(uintptr_t arg) +{ + UARTCC26X2_Object *object = ((UART_Handle)arg)->object; + object->state.bufTimeout = true; + SemaphoreP_post(&(object->readSem)); +} + +/* + * ======== readIsr ======== + */ +static void readIsr(UART_Handle handle, uint32_t status) +{ + UARTCC26X2_Object *object = handle->object; + UARTCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + int readIn; + int maxBytesToRead = FIFO_SIZE; + size_t rxFifoThresholdBytes; + int bytesRead; + uint32_t errStatus = 0; + + if (status & UART_INT_OE) { + /* Fifo overrun error - will read all data in the fifo */ + errStatus = UARTRxErrorGet(hwAttrs->baseAddr); + UARTRxErrorClear(hwAttrs->baseAddr); + object->status = errStatus; + } + else if (status & (UART_INT_RT)) { + object->status = READTIMEDOUT; + } + else if (object->readRetPartial && (status & UART_INT_RX)) { + rxFifoThresholdBytes = rxFifoBytes[hwAttrs->rxIntFifoThr]; + if (object->readCount > rxFifoThresholdBytes) { + /* Will leave one byte in the FIFO to trigger the RT interrupt */ + maxBytesToRead = rxFifoThresholdBytes - 1; + } + } + + bytesRead = 0; + + while (UARTCharsAvail(hwAttrs->baseAddr)) { + /* + * If the Ring buffer is full, leave the data in the FIFO. + * This will allow flow control to work, if it is enabled. + */ + if (RingBuf_isFull(&object->ringBuffer)) { + break; + } + + readIn = UARTCharGetNonBlocking(hwAttrs->baseAddr); + if (readIn & UART_BE_PE_FE) { + errStatus = UARTRxErrorGet(hwAttrs->baseAddr); + UARTRxErrorClear(hwAttrs->baseAddr); + object->status = errStatus; + break; + } + + bytesRead++; + + if ((object->state.readDataMode == UART_DATA_TEXT) && readIn == '\r') { + /* Echo character if enabled. */ + if (object->state.readEcho) { + UARTCharPut(hwAttrs->baseAddr, '\r'); + } + readIn = '\n'; + } + RingBuf_put(&object->ringBuffer, (unsigned char)readIn); + + if ((object->state.readDataMode == UART_DATA_TEXT) && + (object->state.readEcho)) { + UARTCharPut(hwAttrs->baseAddr, (unsigned char)readIn); + } + + if (bytesRead >= maxBytesToRead) { + break; + } + } + + if ((object->state.readMode == UART_MODE_BLOCKING) && ((bytesRead > 0) || + (errStatus != 0))) { + /* object->state.callCallback set in readTaskBlocking() */ + if (object->state.callCallback) { + object->state.callCallback = false; + object->readCallback(handle, NULL, 0); + } + } + + /* + * Check and see if a UART_read in callback mode told use to continue + * servicing the user buffer... + */ + if (object->state.drainByISR) { + /* In CALLBACK mode */ + readTaskCallback(handle); + } + + if (errStatus) { + UARTCC26X2_readCancel(handle); + if (hwAttrs->errorFxn) { + hwAttrs->errorFxn(handle, errStatus); + } + } +} + +/* + * ======== readSemCallback ======== + * Simple callback to post a semaphore for the blocking mode. + */ +static void readSemCallback(UART_Handle handle, void *buffer, size_t count) +{ + UARTCC26X2_Object *object = handle->object; + + SemaphoreP_post(&(object->readSem)); +} + +/* + * ======== readTaskBlocking ======== + */ +static int readTaskBlocking(UART_Handle handle) +{ + unsigned char readIn; + uintptr_t key; + UARTCC26X2_Object *object = handle->object; + unsigned char *buffer = object->readBuf; + + object->state.bufTimeout = false; + /* + * It is possible for the object->timeoutClk and the callback function to + * have posted the object->readSem Semaphore from the previous UART_read + * call (if the code below didn't get to stop the clock object in time). + * To clear this, we simply do a NO_WAIT pend on (binary) object->readSem + * so that it resets the Semaphore count. + */ + SemaphoreP_pend(&(object->readSem), SemaphoreP_NO_WAIT); + + if ((object->readTimeout != 0) && + (object->readTimeout != UART_WAIT_FOREVER)) { + ClockP_setTimeout(&(object->timeoutClk), object->readTimeout); + ClockP_start(&(object->timeoutClk)); + } + + while (object->readCount) { + key = HwiP_disable(); + + if (ringBufGet(handle, &readIn) < 0) { + if (object->readRetPartial) { + if (object->status == READTIMEDOUT) { + object->status = 0; + HwiP_restore(key); + break; + } + + /* If some data has been read, return */ + if (object->readCount < object->readSize) { + HwiP_restore(key); + break; + } + } + + if (object->state.bufTimeout || (object->status != 0)) { + /* Timed out or RX error waiting for read to complete */ + HwiP_restore(key); + disableRX(handle); + break; + } + + object->state.callCallback = true; + HwiP_restore(key); + + if (object->readTimeout == 0) { + break; + } + + SemaphoreP_pend(&(object->readSem), SemaphoreP_WAIT_FOREVER); + } + else { + /* Got something from the ring buffer */ + object->readCount--; + HwiP_restore(key); + + DebugP_log2("UART:(%p) read '0x%02x'", + ((UARTCC26X2_HWAttrs const *)(handle->hwAttrs))->baseAddr, + (unsigned char)readIn); + + *buffer = readIn; + buffer++; + + if (object->state.readDataMode == UART_DATA_TEXT && + object->state.readReturnMode == UART_RETURN_NEWLINE && + readIn == '\n') { + break; + } + } + } + + ClockP_stop(&(object->timeoutClk)); + return (object->readSize - object->readCount); +} + +/* + * ======== readTaskCallback ======== + * This function is called the first time by the UART_read task and tries to + * get all the data it can get from the ringBuffer. If it finished, it will + * perform the user supplied callback. If it didn't finish, the ISR must + * handle the remaining data. By setting the drainByISR flag, the UART_read + * function handed over the responsibility to get the remaining data to the + * ISR. + */ +static int readTaskCallback(UART_Handle handle) +{ + unsigned int key; + UARTCC26X2_Object *object = handle->object; + unsigned char readIn; + unsigned char *bufferEnd; + bool makeCallback = false; + + object->state.drainByISR = false; + bufferEnd = (unsigned char*) object->readBuf + object->readSize; + + while (object->readCount) { + if (ringBufGet(handle, &readIn) < 0) { + break; + } + + DebugP_log2("UART:(%p) read '0x%02x'", + ((UARTCC26X2_HWAttrs const *)(handle->hwAttrs))->baseAddr, + (unsigned char)readIn); + + *(unsigned char *) (bufferEnd - object->readCount * + sizeof(unsigned char)) = readIn; + + key = HwiP_disable(); + + object->readCount--; + + HwiP_restore(key); + + if ((object->state.readDataMode == UART_DATA_TEXT) && + (object->state.readReturnMode == UART_RETURN_NEWLINE) && + (readIn == '\n')) { + makeCallback = true; + break; + } + } + + if ((object->status & UARTCC26X2_RXERROR) && (object->readCount != 0)) { + /* An error occurred. */ + key = HwiP_disable(); + object->readSize -= object->readCount; + object->readCount = 0; + HwiP_restore(key); + } + else if ((object->readRetPartial && + (object->readCount < object->readSize)) || + (object->readCount == 0) || + makeCallback) { + SwiP_post(&(object->readSwi)); + } + else { + object->state.drainByISR = true; + } + + return (0); +} + +/* + * ======== ringBufGet ======== + */ +static int ringBufGet(UART_Handle handle, unsigned char *data) +{ + UARTCC26X2_Object *object = handle->object; + UARTCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + int32_t readIn; + int count; + + key = HwiP_disable(); + + if (RingBuf_isFull(&object->ringBuffer)) { + count = RingBuf_get(&object->ringBuffer, data); + + readIn = UARTCharGetNonBlocking(hwAttrs->baseAddr); + if (readIn != -1) { + RingBuf_put(&object->ringBuffer, (unsigned char)readIn); + count++; + } + HwiP_restore(key); + } + else { + count = RingBuf_get(&object->ringBuffer, data); + HwiP_restore(key); + } + + return (count); +} + +/* + * ======== swiReadCallback ======== + */ +static void swiReadCallback(uintptr_t arg0, uintptr_t arg1) +{ + UARTCC26X2_Object *object = (UARTCC26X2_Object *)(((UART_Handle)arg0)->object); + uintptr_t key; + size_t count; + + key = HwiP_disable(); + + count = object->readSize - object->readCount; + object->readSize = 0; + + HwiP_restore(key); + + object->readCallback((UART_Handle)arg0, object->readBuf, count); +} + +/* + * ======== swiWriteCallback ======== + */ +static void swiWriteCallback(uintptr_t arg0, uintptr_t arg1) +{ + UARTCC26X2_Object *object = (UARTCC26X2_Object *)(((UART_Handle)arg0)->object); + UARTCC26X2_HWAttrs *hwAttrs = (UARTCC26X2_HWAttrs *)(((UART_Handle)arg0)->hwAttrs); + uintptr_t key; + + key = HwiP_disable(); + if (object->state.txEnabled) { + /* Disable TX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_TXE); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + object->state.txEnabled = false; + } + HwiP_restore(key); + + object->writeCallback((UART_Handle)arg0, (void *)object->writeBuf, + object->writeSize); +} + +/* + * ======== writeData ======== + */ +static void writeData(UART_Handle handle) +{ + UARTCC26X2_Object *object = handle->object; + UARTCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + unsigned char *writeOffset; + uintptr_t key; + + writeOffset = (unsigned char *)object->writeBuf + + object->writeSize * sizeof(unsigned char); + + while (object->writeCount) { + if (!UARTCharPutNonBlocking(hwAttrs->baseAddr, + *(writeOffset - object->writeCount))) { + /* TX FIFO is FULL */ + break; + } + if ((object->state.writeDataMode == UART_DATA_TEXT) && + (*(writeOffset - object->writeCount) == '\n')) { + UARTCharPut(hwAttrs->baseAddr, '\r'); + } + object->writeCount--; + } + + if (!object->writeCount) { + key = HwiP_disable(); + UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX); + HwiP_restore(key); + + UARTIntClear(hwAttrs->baseAddr, UART_INT_TX); + + /* + * Set TX interrupt for end of transmission. + * The EOTRIS bit will be set only when all the data + * (including stop bits) have left the serializer. + */ + key = HwiP_disable(); + UARTIntEnable(hwAttrs->baseAddr, UART_INT_EOT); + HwiP_restore(key); + + if (!UARTBusy(hwAttrs->baseAddr)) { + key = HwiP_disable(); + UARTIntDisable(hwAttrs->baseAddr, UART_INT_EOT); + HwiP_restore(key); + UARTIntClear(hwAttrs->baseAddr, UART_INT_EOT); + + SwiP_post(&(object->writeSwi)); + } + + DebugP_log2("UART:(%p) Write finished, %d bytes written", + hwAttrs->baseAddr, object->writeSize - object->writeCount); + } +} + +/* + * ======== writeSemCallback ======== + * Simple callback to post a semaphore for the blocking mode. + */ +static void writeSemCallback(UART_Handle handle, void *buffer, size_t count) +{ + UARTCC26X2_Object *object = handle->object; + + SemaphoreP_post(&(object->writeSem)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X2.h new file mode 100644 index 0000000..e8397c6 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X2.h @@ -0,0 +1,649 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file UARTCC26X2.h + * + * @brief UART driver implementation for a CC26X2 UART controller + * + * # Driver include # + * The UART header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref UART.h for a complete description of APIs. + * + * # Overview # + * The general UART API should used in application code, i.e. UART_open() + * is used instead of UARTCC26X2_open(). The board file will define the device + * specific config, and casting in the general API will ensure that the correct + * device specific functions are called. + * This is also reflected in the example code in [Use Cases](@ref USE_CASES). + * + * # General Behavior # + * Before using the UART in CC26X2: + * - The UART driver is initialized by calling UART_init(). + * - The UART HW is configured and flags system dependencies (e.g. IOs, + * power, etc.) by calling UART_open(). + * - The RX and TX can operate independently of each other. + * . + * The following is true for receive operation: + * - RX is enabled by calling UART_read(). + * - All received bytes are ignored after UART_open() is called, until + * the first UART_read(). + * - If an RX error occur, RX is turned off and all bytes received before the + * error occured are returned. + * - After a successful read, RX remains on. UART_read() must be called + * again before FIFO goes full in order to avoid overflow. It is safe to + * call another UART_read() from the read callback, See + * [Receive Continously] (@ref USE_CASE_CB) use case below. + * - If a read times out (in ::UART_MODE_BLOCKING mode), RX will remain on. + * UART_read() must be called again before FIFO goes full in order to avoid overflow. + * - The UART_read() supports partial return, that can be used if the + * receive size is unknown. See [Use Cases](@ref USE_CASES) below. + * - The RingBuf serves as an extension of the FIFO. If data is received when + * UART_read() is not called, data will be stored in the RingBuf. The + * functionality of the RingBuf has been tested with a size of 32. This size + * can be changed to suit the application. + * . + * The following apply for transmit operation: + * - TX is enabled by calling UART_write(). + * - If the UART_write() succeeds, the TX is disabled. + * . + * If UART is no longer needed by application: + * - Release system dependencies for UART by calling UART_close(). + * . + * If the UART is configured in ::UART_MODE_CALLBACK mode: + * - The error handling callback is run in a HWI context. + * - The application's callback is run in a SWI context. + * + * # Error handling # + * ## Read errors ## + * If an error occurs during read operation: + * - All bytes received up until an error occurs will be returned, with the + * error signaled in the ::UARTCC26X2_Object.status field. The RX is then turned off + * and all bytes will be ignored until a new read is issued. Note that only + * the read is cancelled when the error occurs. If a write was active + * while the RX error occurred, it will complete. A new UART_read() will reset + * the ::UARTCC26X2_Object.status field to 0. + * - If a RX break error occurs, an extra 0 byte will also be returned by the + * UART_read(). + * . + * + * ## General timeout ## + * A timeout value can only be specified for reads and writes in ::UART_MODE_BLOCKING. + * If a timeout occurs during a read when in ::UART_MODE_BLOCKING, the number of bytes + * received will be returned. + * After a read timeout, RX will be turned off and the device allowed to enter standby. + * For more details see [Power Management](@ref POWER_MANAGEMENT) chapter below. + * + * In ::UART_MODE_CALLBACK there is no timeout and the application must call + * UART_readCancel() or UART_writeCancel() to abort the operation. + * + * ## Closing driver during an ongoing read/write ## + * It's safe to call UART_close() during an ongoing UART_read() and/or UART_write(), + * this will cancel the ongoing RX/TX immediately. + * + * The RX callback is alwyas called when you call UART_close() if there's an + * ongoing read. + * Note that if UART_close() is called during an ongoing read, the size provided + * in the RX callback function is 0 if < 16 bytes were received before calling UART_close(). + * This is because 16 bytes is the RX watermark that triggers the ISR + * to copy bytes from the internal UART FIFO to the software RX buffer. + * + * The TX callback is always called when you call UART_close() if there's an + * ongoing write. The driver does not wait until a byte is transmitted correctly, + * so if UART_close() is called in the middle of sending a byte, + * this byte will be corrupted. + * + * # Power Management @anchor UARTCC26X2_POWER_MANAGEMENT # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * The UARTCC26X2 driver sets a power constraint during operation to keep + * the device out of standby. When the operation has finished, the power + * constraint is released. + * The following statements are valid: + * - After UART_open(): the device is not allowed to enter standby. + * - During UART_read(): the device cannot enter standby. + * - After an RX error (overrun, break, parity, framing): RX is disabled and the device + * is allowed to enter standby. + * - After a successful UART_read(): + * The device is not allowed to enter standby and RX remains on. + * - _Note_: Application thread should typically either issue another read after + * UART_read() completes successfully, or call either + * UART_readCancel() or UART_control(uart, UART_CMD_RXDISABLE, 0), + * to disable RX and allow the device to enter standby. + * - After UART_read() times out in ::UART_MODE_BLOCKING: + * The device is allowed to enter standby and RX is turned off. To prevent + * RX from being disabled and disallowing standby on a read timeout or read + * error, the application can call UART_control(uart, UART_CMD_RXENABLE, 0). + * - During UART_write(): the device cannot enter standby. + * - After UART_write() succeeds: the device can enter standby. + * - If UART_writeCancel() is called: the device can enter standby. + * - After write timeout: the device can enter standby. + * + * # Flow Control # + * To enable Flow Control, the RTS and CTS pins must be assigned in the + * ::UARTCC26X2_HWAttrs and flowControl must be set to UARTCC26X2_FLOWCTRL_HARDWARE: + * @code + * const UARTCC26X2_HWAttrs uartCC26X2HWAttrs[] = { + * { + * .baseAddr = UART0_BASE, + * .powerMngrId = PERIPH_UART0, + * .intNum = INT_UART0, + * .intPriority = ~0, + * .swiPriority = 0, + * .flowControl = UARTCC26X2_FLOWCTRL_HARDWARE, + * .txPin = Board_UART_TX, + * .rxPin = Board_UART_RX, + * .ctsPin = Board_UART_CTS, + * .rtsPin = Board_UART_RTS + * .ringBufPtr = uartCC26X2RingBuffer[0], + * .ringBufSize = sizeof(uartCC26X2RingBuffer[0]), + * .txIntFifoThr= UARTCC26X2_FIFO_THRESHOLD_1_8, + * .rxIntFifoThr= UARTCC26X2_FIFO_THRESHOLD_4_8 + * } + * }; + * @endcode + * + * If the RTS and CTS pins are set to ::PIN_UNASSIGNED, or flowControl is set + * to UARTCC26X2_FLOWCONTROL_NONE, the flow control is disabled. + * An example is shown in the ::UARTCC26X2_HWAttrs description. + * + * # Supported Functions # + * | Generic API function | API function | Description | + * |----------------------|--------------------------|------------------------ + * | UART_init() | UARTCC26X2_init() | Initialize UART driver | + * | UART_open() | UARTCC26X2_open() | Initialize UART HW and set system dependencies | + * | UART_close() | UARTCC26X2_close() | Disable UART HW and release system dependencies | + * | UART_control() | UARTCC26X2_control() | Configure an already opened UART handle | + * | UART_read() | UARTCC26X2_read() | Start read from UART | + * | UART_readCancel() | UARTCC26X2_readCancel() | Cancel ongoing read from UART | + * | UART_readPolling() | UARTCC26X2_readPolling() | Polling read from UART | + * | UART_write() | UARTCC26X2_write() | Start write to UART | + * | UART_writeCancel() | UARTCC26X2_writeCancel() | Cancel ongoing write to UART | + * | UART_writePolling() | UARTCC26X2_writePolling()| Polling write to UART | + * + * @note All calls should go through the generic API + * + * # Use Cases @anchor UARTCC26X2_USE_CASES # + * ## Basic Receive # + * Receive 100 bytes over UART in ::UART_MODE_BLOCKING. + * @code + * UART_Handle handle; + * UART_Params params; + * uint8_t rxBuf[100]; // Receive buffer + * uint32_t timeoutUs = 5000; // 5ms timeout, default timeout is no timeout (BIOS_WAIT_FOREVER) + * + * // Init UART and specify non-default parameters + * UART_Params_init(¶ms); + * params.baudRate = 9600; + * params.writeDataMode = UART_DATA_BINARY; + * params.readTimeout = timeoutUs / ClockP_tickPeriod; // Default tick period is 10us + * + * // Open the UART and do the read + * handle = UART_open(Board_UART, ¶ms); + * int rxBytes = UART_read(handle, rxBuf, 100); + * @endcode + * + * ## Receive with Return Partial # + * This use case will read in ::UART_MODE_BLOCKING until the wanted amount of bytes is + * received or until a started reception is inactive for a 32-bit period. + * This UART_read() call can also be used when unknown amount of bytes shall + * be read. Note: The partial return is also possible in ::UART_MODE_CALLBACK mode. + * @code + * UART_Handle handle; + * UART_Params params; + * uint8_t rxBuf[100]; // Receive buffer + * + * // Init UART and specify non-default parameters + * UART_Params_init(¶ms); + * params.baudRate = 9600; + * params.writeDataMode = UART_DATA_BINARY; + * + * // Open the UART and initiate the partial read + * handle = UART_open(Board_UART, ¶ms); + * // Enable RETURN_PARTIAL + * UART_control(handle, UARTCC26X2_CMD_RETURN_PARTIAL_ENABLE, NULL); + * // Begin read + * int rxBytes = UART_read(handle, rxBuf, 100)); + * @endcode + * + * ## Basic Transmit # + * This case will configure the UART to send the data in txBuf in + * BLOCKING_MODE. + * @code + * UART_Handle handle; + * UART_Params params; + * uint8_t txBuf[] = "Hello World"; // Transmit buffer + * + * // Init UART and specify non-default parameters + * UART_Params_init(¶ms); + * params.baudRate = 9600; + * params.writeDataMode = UART_DATA_BINARY; + * + * // Open the UART and do the write + * handle = UART_open(Board_UART, ¶ms); + * UART_write(handle, txBuf, sizeof(txBuf)); + * @endcode + * + * ## Receive Continously in ::UART_MODE_CALLBACK @anchor UARTCC26X2_USE_CASE_CB # + * This case will configure the UART to receive and transmit continously in + * ::UART_MODE_CALLBACK, and transmit them back via UART TX. + * Note that UART_Params.readTimeout is not in use when using ::UART_MODE_CALLBACK mode. + * @code + * #define MAX_NUM_RX_BYTES 1000 // Maximum RX bytes to receive in one go + * #define MAX_NUM_TX_BYTES 1000 // Maximum TX bytes to send in one go + * + * uint32_t wantedRxBytes; // Number of bytes received so far + * uint8_t rxBuf[MAX_NUM_RX_BYTES]; // Receive buffer + * uint8_t txBuf[MAX_NUM_TX_BYTES]; // Transmit buffer + * + * // Read callback function + * static void readCallback(UART_Handle handle, void *rxBuf, size_t size) + * { + * // Make sure we received all expected bytes + * if (size == wantedRxBytes) { + * // Copy bytes from RX buffer to TX buffer + * for (size_t i = 0; i < size; i++) + * txBuf[i] = ((uint8_t*)rxBuf)[i]; + * + * // Echo the bytes received back to transmitter + * UART_write(handle, txBuf, size); + * + * // Start another read, with size the same as it was during first call to + * // UART_read() + * UART_read(handle, rxBuf, wantedRxBytes); + * } + * else { + * // Handle error or call to UART_readCancel() + * } + * } + * + * // Write callback function + * static void writeCallback(UART_Handle handle, void *rxBuf, size_t size) + * { + * // Do nothing + * } + * + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * UART_Handle handle; + * UART_Params params; + * + * // Init UART + * UART_init(); + * + * // Specify non-default parameters + * UART_Params_init(¶ms); + * params.baudRate = 9600; + * params.writeMode = UART_MODE_CALLBACK; + * params.writeDataMode = UART_DATA_BINARY; + * params.writeCallback = writeCallback; + * params.readMode = UART_MODE_CALLBACK; + * params.readDataMode = UART_DATA_BINARY; + * params.readCallback = readCallback; + * + * // Open the UART and initiate the first read + * handle = UART_open(Board_UART, ¶ms); + * wantedRxBytes = 16; + * int rxBytes = UART_read(handle, rxBuf, wantedRxBytes); + * + * while(true); // Wait forever + * } + * @endcode + * + * # Baud Rate # + * The CC26xx driver supports baud rates up to 3Mbaud. + * However, when receiving more than 32 bytes back-to-back the baud + * rate is limited to approximately 2Mbaud. + * The throughput is also dependent on the user application. + * + * # Stack requirements # + * There are no additional stack requirements for calling UART_read() within + * its own callback. + * + * ============================================================================ + */ + +#ifndef ti_drivers_uart_UARTCC26X2__include +#define ti_drivers_uart_UARTCC26X2__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + + +/*! + * @brief No hardware flow control + */ +#define UARTCC26X2_FLOWCTRL_NONE 0 + +/*! + * @brief Hardware flow control + */ +#define UARTCC26X2_FLOWCTRL_HARDWARE 1 + +/** + * @addtogroup UART_STATUS + * UARTCC26X2_STATUS_* macros are command codes only defined in the + * UARTCC26X2.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add UARTCC26X2_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup UART_CMD + * UARTCC26X2_CMD_* macros are command codes only defined in the + * UARTCC26X2.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/*! + * @brief Command used by UART_control to enable partial return + * + * Enabling this command allows UART_read to return partial data if data + * reception is inactive for a given 32-bit period. With this command @b arg + * is @a don't @a care and it returns UART_STATUS_SUCCESS. + */ +#define UARTCC26X2_CMD_RETURN_PARTIAL_ENABLE (UART_CMD_RESERVED + 0) + +/*! + * @brief Command used by UART_control to disable partial return + * + * Disabling this command returns the UARTCC26X2 to the default blocking + * behavior where UART_read blocks until all data bytes were received. With + * this comand @b arg is @a don't @a care and it returns UART_STATUS_SUCCESS. + */ +#define UARTCC26X2_CMD_RETURN_PARTIAL_DISABLE (UART_CMD_RESERVED + 1) + +/*! + * @brief Command used by UART_control to flush the RX FIFO + * + * This control command flushes any contents in the RX FIFO. With this command + * @b arg is @a don't @a care and it returns UART_STATUS_SUCCESS. + */ +#define UARTCC26X2_CMD_RX_FIFO_FLUSH (UART_CMD_RESERVED + 2) + + +/** @}*/ + +/*! Size of the TX and RX FIFOs is 32 items */ +#define UARTCC26X2_FIFO_SIZE 32 + +/*! + * @brief UART TX/RX interrupt FIFO threshold select + * + * Defined FIFO thresholds for generation of both TX interrupt and RX + * interrupt. The default value (UARTCC26X2_FIFO_THRESHOLD_DEFAULT) is + * defined for backwards compatibility handling. If the RX and TX FIFO + & thresholds are not set in the HwAttrs, or are set to + * UARTCC26X2_FIFO_THRESHOLD_DEFAULT, the RX interrupt FIFO threshold is + * set to 4/8 full, and the TX interrupt FIFO threshold is set to 1/8 + * full. + */ +typedef enum UARTCC26X2_FifoThreshold { + UARTCC26X2_FIFO_THRESHOLD_DEFAULT = 0, /*!< Use default FIFO threshold */ + UARTCC26X2_FIFO_THRESHOLD_1_8, /*!< FIFO threshold of 1/8 full */ + UARTCC26X2_FIFO_THRESHOLD_2_8, /*!< FIFO threshold of 2/8 full */ + UARTCC26X2_FIFO_THRESHOLD_4_8, /*!< FIFO threshold of 4/8 full */ + UARTCC26X2_FIFO_THRESHOLD_6_8, /*!< FIFO threshold of 6/8 full */ + UARTCC26X2_FIFO_THRESHOLD_7_8 /*!< FIFO threshold of 7/8 full */ +} UARTCC26X2_FifoThreshold; + +/*! + * @brief The definition of an optional callback function used by the + * UART driver to notify the application when a receive error + * (FIFO overrun, parity error, etc) occurs. + * + * @param UART_Handle UART_Handle + * + * @param error The current value of the receive + * status register. + */ +typedef void (*UARTCC26X2_ErrorCallback) (UART_Handle handle, uint32_t error); + +/* UART function table pointer */ +extern const UART_FxnTable UARTCC26X2_fxnTable; + +/*! + * @brief UARTCC26X2 Hardware attributes + * + * The fields, baseAddr and intNum are used by driverlib + * APIs and therefore must be populated by + * driverlib macro definitions. These definitions are found under the + * device family in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * - driverlib/uart.h + * + * intPriority is the UART peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * The CC26xx uses three of the priority bits, meaning ~0 has the same + * effect as (7 << 5). + * + * (7 << 5) will apply the lowest priority. + * (1 << 5) will apply the highest priority. + * + * Setting the priority to 0 is not supported by this driver. HWI's with + * priority 0 ignore the HWI dispatcher to support zero-latency interrupts, + * thus invalidating the critical sections in this driver. + * + * A sample structure is shown below: + * @code + * unsigned char uartCC26X2RingBuffer[2][32]; + * + * const UARTCC26X2_HWAttrs uartCC26X2HWAttrs[] = { + * { + * .baseAddr = UARTA0_BASE, + * .intNum = INT_UART0_COMB, + * .intPriority = (~0), + * .swiPriority = 0, + * .ringBufPtr = uartCC26X2RingBuffer[0], + * .ringBufSize = sizeof(uartCC26X2RingBuffer[0]), + * .flowControl = UARTCC26X2_FLOWCTRL_NONE, + * .rxPin = IOID_2, + * .txPin = IOID_3, + * .ctsPin = PIN_UNASSIGNED, + * .rtsPin = PIN_UNASSIGNED, + * .txIntFifoThr = UARTCC26X2_FIFO_THRESHOLD_1_8, + * .rxIntFifoThr = UARTCC26X2_FIFO_THRESHOLD_4_8, + * .errorFxn = NULL + * }, + * { + * .baseAddr = UART1_BASE, + * .intNum = INT_UART1_COMB, + * .intPriority = (~0), + * .swiPriority = 0, + * .ringBufPtr = uartCC26X2RingBuffer[1], + * .ringBufSize = sizeof(uartCC26X2RingBuffer[1]), + * .flowControl = UARTCC26X2_FLOWCTRL_NONE, + * .rxPin = PIN_UNASSIGNED, + * .txPin = PIN_UNASSIGNED, + * .ctsPin = PIN_UNASSIGNED, + * .rtsPin = PIN_UNASSIGNED, + * .txIntFifoThr = UARTCC26X2_FIFO_THRESHOLD_1_8, + * .rxIntFifoThr = UARTCC26X2_FIFO_THRESHOLD_4_8, + * .errorFxn = NULL + * }, + * }; + * @endcode + * + * The .ctsPin and .rtsPin must be assigned to enable flow control. + */ +typedef struct UARTCC26X2_HWAttrs { + /*! UART Peripheral's base address */ + uint32_t baseAddr; + /*! UART Peripheral's interrupt vector */ + int intNum; + /*! UART Peripheral's interrupt priority */ + uint8_t intPriority; + /*! + * @brief Swi priority. + * The higher the number, the higher the priority. The minimum + * priority is 0 and the maximum is defined by the underlying OS. + */ + uint32_t swiPriority; + /*! Hardware flow control setting */ + uint32_t flowControl; + /*! Pointer to an application ring buffer */ + unsigned char *ringBufPtr; + /*! Size of ringBufPtr */ + size_t ringBufSize; + /*! UART RX pin assignment */ + uint8_t rxPin; + /*! UART TX pin assignment */ + uint8_t txPin; + /*! UART clear to send (CTS) pin assignment */ + uint8_t ctsPin; + /*! UART request to send (RTS) pin assignment */ + uint8_t rtsPin; + /*! UART TX interrupt FIFO threshold select */ + UARTCC26X2_FifoThreshold txIntFifoThr; + /*! UART RX interrupt FIFO threshold select */ + UARTCC26X2_FifoThreshold rxIntFifoThr; + /*! Application error function to be called on receive errors */ + UARTCC26X2_ErrorCallback errorFxn; +} UARTCC26X2_HWAttrs; + +/*! + * @brief UARTCC26X2 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct UARTCC26X2_Object { + /* UART state variable */ + struct { + bool opened:1; /* Has the obj been opened */ + UART_Mode readMode:1; /* Mode for all read calls */ + UART_Mode writeMode:1; /* Mode for all write calls */ + UART_DataMode readDataMode:1; /* Type of data being read */ + UART_DataMode writeDataMode:1; /* Type of data being written */ + UART_ReturnMode readReturnMode:1; /* Receive return mode */ + UART_Echo readEcho:1; /* Echo received data back */ + /* + * Flag to determine if a timeout has occurred when the user called + * UART_read(). This flag is set by the timeoutClk clock object. + */ + bool bufTimeout:1; + /* + * Flag to determine when an ISR needs to perform a callback; in both + * UART_MODE_BLOCKING or UART_MODE_CALLBACK + */ + bool callCallback:1; + /* + * Flag to determine if the ISR is in control draining the ring buffer + * when in UART_MODE_CALLBACK + */ + bool drainByISR:1; + /* Keep track of RX enabled state set by app with UART_control() */ + bool ctrlRxEnabled:1; + /* Flag to keep the state of the read Power constraints */ + bool rxEnabled:1; + /* Flag to keep the state of the write Power constraints */ + bool txEnabled:1; + } state; + + HwiP_Struct hwi; /* Hwi object for interrupts */ + SwiP_Struct readSwi; /* Swi for read callbacks */ + SwiP_Struct writeSwi; /* Swi for write callbacks */ + ClockP_Struct timeoutClk; /* Clock object to for timeouts */ + uint32_t baudRate; /* Baud rate for UART */ + UART_LEN dataLength; /* Data length for UART */ + UART_STOP stopBits; /* Stop bits for UART */ + UART_PAR parityType; /* Parity bit type for UART */ + uint32_t status; /* RX status */ + + /* UART read variables */ + RingBuf_Object ringBuffer; /* local circular buffer object */ + unsigned char *readBuf; /* Buffer data pointer */ + size_t readSize; /* Desired number of bytes to read */ + size_t readCount; /* Number of bytes left to read */ + SemaphoreP_Struct readSem; /* UART read semaphore */ + unsigned int readTimeout; /* Timeout for read semaphore */ + UART_Callback readCallback; /* Pointer to read callback */ + bool readRetPartial; /* Return partial RX data if timeout occurs */ + + /* UART write variables */ + const unsigned char *writeBuf; /* Buffer data pointer */ + size_t writeSize; /* Desired number of bytes to write*/ + size_t writeCount; /* Number of bytes left to write */ + SemaphoreP_Struct writeSem; /* UART write semaphore*/ + unsigned int writeTimeout; /* Timeout for write semaphore */ + UART_Callback writeCallback; /* Pointer to write callback */ + + /* PIN driver state object and handle */ + PIN_State pinState; + PIN_Handle hPin; + + /* For Power management */ + Power_NotifyObj postNotify; + unsigned int powerMgrId; /* Determined from base address */ +} UARTCC26X2_Object, *UARTCC26X2_Handle; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_uart_UARTCC26X2__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26XX.c new file mode 100644 index 0000000..d0f2f8e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26XX.c @@ -0,0 +1,1683 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/uart.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) + +/* UARTCC26XX functions */ +void UARTCC26XX_close(UART_Handle handle); +int_fast16_t UARTCC26XX_control(UART_Handle handle, uint_fast16_t cmd, + void *arg); +void UARTCC26XX_init(UART_Handle handle); +UART_Handle UARTCC26XX_open(UART_Handle handle, UART_Params *params); +int_fast32_t UARTCC26XX_read(UART_Handle handle, void *buffer, size_t size); +int_fast32_t UARTCC26XX_readPolling(UART_Handle handle, void *buf, + size_t size); +void UARTCC26XX_readCancel(UART_Handle handle); +int_fast32_t UARTCC26XX_write(UART_Handle handle, const void *buffer, + size_t size); +int_fast32_t UARTCC26XX_writePolling(UART_Handle handle, const void *buf, + size_t size); +void UARTCC26XX_writeCancel(UART_Handle handle); + +/* UARTCC26XX internal functions */ +static void UARTCC26XX_initHw(UART_Handle handle); +static bool UARTCC26XX_initIO(UART_Handle handle); +static int uartPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg); + +/* UART function table for UARTCC26XX implementation */ +const UART_FxnTable UARTCC26XX_fxnTable = { + UARTCC26XX_close, + UARTCC26XX_control, + UARTCC26XX_init, + UARTCC26XX_open, + UARTCC26XX_read, + UARTCC26XX_readPolling, + UARTCC26XX_readCancel, + UARTCC26XX_write, + UARTCC26XX_writePolling, + UARTCC26XX_writeCancel +}; + +static const uint32_t dataLength[] = { + UART_CONFIG_WLEN_5, /* UART_LEN_5 */ + UART_CONFIG_WLEN_6, /* UART_LEN_6 */ + UART_CONFIG_WLEN_7, /* UART_LEN_7 */ + UART_CONFIG_WLEN_8 /* UART_LEN_8 */ +}; + +static const uint32_t stopBits[] = { + UART_CONFIG_STOP_ONE, /* UART_STOP_ONE */ + UART_CONFIG_STOP_TWO /* UART_STOP_TWO */ +}; + +static const uint32_t parityType[] = { + UART_CONFIG_PAR_NONE, /* UART_PAR_NONE */ + UART_CONFIG_PAR_EVEN, /* UART_PAR_EVEN */ + UART_CONFIG_PAR_ODD, /* UART_PAR_ODD */ + UART_CONFIG_PAR_ZERO, /* UART_PAR_ZERO */ + UART_CONFIG_PAR_ONE /* UART_PAR_ONE */ +}; + +/* Array for mapping of FIFO threshold defines selected by board files to: */ +/* - TX FIFO threshold define used by driverlib */ +/* FIFO threshold defines (enum UARTCC26XX_FifoThreshold) must be used as */ +/* array index. */ +/* Index 0 handles backward compatibility with legacy board files that don't */ +/* select any FIFO thresholds. */ +static const uint8_t txFifoThreshold[6] = { + UART_FIFO_TX1_8, /* UARTCC26XX_FIFO_THRESHOLD_DEFAULT */ + UART_FIFO_TX1_8, /* UARTCC26XX_FIFO_THRESHOLD_1_8 */ + UART_FIFO_TX2_8, /* UARTCC26XX_FIFO_THRESHOLD_2_8 */ + UART_FIFO_TX4_8, /* UARTCC26XX_FIFO_THRESHOLD_4_8 */ + UART_FIFO_TX6_8, /* UARTCC26XX_FIFO_THRESHOLD_6_8 */ + UART_FIFO_TX7_8 /* UARTCC26XX_FIFO_THRESHOLD_7_8 */ +}; + +/* Array for mapping of FIFO threshold defines selected by board files to: */ +/* - RX FIFO threshold define used by driverlib */ +/* FIFO threshold defines (enum UARTCC26XX_FifoThreshold) must be used as */ +/* array index. */ +/* Index 0 handles backward compatibility with legacy board files that don't */ +/* select any FIFO thresholds. */ +static const uint8_t rxFifoThreshold[6] = { + UART_FIFO_RX4_8, /* UARTCC26XX_FIFO_THRESHOLD_DEFAULT */ + UART_FIFO_RX1_8, /* UARTCC26XX_FIFO_THRESHOLD_1_8 */ + UART_FIFO_RX2_8, /* UARTCC26XX_FIFO_THRESHOLD_2_8 */ + UART_FIFO_RX4_8, /* UARTCC26XX_FIFO_THRESHOLD_4_8 */ + UART_FIFO_RX6_8, /* UARTCC26XX_FIFO_THRESHOLD_6_8 */ + UART_FIFO_RX7_8 /* UARTCC26XX_FIFO_THRESHOLD_7_8 */ +}; + +/* Array for mapping of FIFO threshold defines selected by board files to: */ +/* - Number of TX FIFO bytes */ +/* FIFO threshold defines (enum UARTCC26XX_FifoThreshold) must be used as */ +/* array index. */ +/* Index 0 handles backward compatibility with legacy board files that */ +/* don't select any FIFO thresholds. */ +static const uint8_t txFifoBytes[6] = { + 4, /* UARTCC26XX_FIFO_THRESHOLD_DEFAULT */ + 4, /* UARTCC26XX_FIFO_THRESHOLD_1_8 */ + 8, /* UARTCC26XX_FIFO_THRESHOLD_2_8 */ + 16, /* UARTCC26XX_FIFO_THRESHOLD_4_8 */ + 24, /* UARTCC26XX_FIFO_THRESHOLD_6_8 */ + 28 /* UARTCC26XX_FIFO_THRESHOLD_7_8 */ +}; + +/* Array for mapping of FIFO threshold defines selected by board files to: */ +/* - Number of RX FIFO bytes */ +/* FIFO threshold defines (enum UARTCC26XX_FifoThreshold) must be used as */ +/* array index. */ +/* Index 0 handles backward compatibility with legacy board files that */ +/* don't select any FIFO thresholds. */ +static const uint8_t rxFifoBytes[6] = { + 16, /* UARTCC26XX_FIFO_THRESHOLD_DEFAULT */ + 4, /* UARTCC26XX_FIFO_THRESHOLD_1_8 */ + 8, /* UARTCC26XX_FIFO_THRESHOLD_2_8 */ + 16, /* UARTCC26XX_FIFO_THRESHOLD_4_8 */ + 24, /* UARTCC26XX_FIFO_THRESHOLD_6_8 */ + 28 /* UARTCC26XX_FIFO_THRESHOLD_7_8 */ +}; + +/* + * ======================== PIN driver objects ================================ + */ + +/* + * ================================= Macro ==================================== + * TODO: Move me + */ +#define MIN(a,b) (((a)<(b))?(a):(b)) +#define MAX(a,b) (((a)>(b))?(a):(b)) +#define UNIT_DIV_ROUNDUP(x,d) ((x + ((d) - 1)) / (d)) + +#define READ_DONE 0x1 /* Mask to trigger Swi on a read complete */ +#define WRITE_DONE 0x2 /* Mask to trigger Swi on a write complete */ + +/* + * Function for checking whether flow control is enabled. + */ +static inline bool isFlowControlEnabled(UARTCC26XX_HWAttrsV2 const *hwAttrs) { + return ((hwAttrs->ctsPin != PIN_UNASSIGNED) && (hwAttrs->rtsPin != PIN_UNASSIGNED)); +} + +/* + * Ensure safe setting of the standby disallow constraint. + */ +static inline void threadSafeStdbyDisSet(volatile bool *pConstraint) { + unsigned int key; + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Only act if the current constraint is not previously set */ + if (!*pConstraint) { + /* Set constraints to guarantee operation */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + *pConstraint = true; + } + + /* Re-enable interrupts */ + HwiP_restore(key); +} + +/* + * Ensure safe releasing of the standby disallow constraint. + */ +static inline void threadSafeStdbyDisRelease(volatile bool *pConstraint) { + unsigned int key; + + /* Disable interrupts */ + key = HwiP_disable(); + + if (*pConstraint) { + /* release constraint since operation is done */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + *pConstraint = false; + } + + /* Re-enable interrupts */ + HwiP_restore(key); +} + +/* + * ======== writeSemCallback ======== + * Simple callback to post a semaphore for the blocking mode. + */ +static void writeSemCallback(UART_Handle handle, void *buffer, size_t count) +{ + UARTCC26XX_Object *object = handle->object; + + DebugP_log1("UART:(%p) posting write semaphore", + ((UARTCC26XX_HWAttrsV2 const *)(handle->hwAttrs))->baseAddr); + + SemaphoreP_post(&(object->writeSem)); +} + +/* + * ======== readSemCallback ======== + * Simple callback to post a semaphore for the blocking mode. + */ +static void readSemCallback(UART_Handle handle, void *buffer, size_t count) +{ + UARTCC26XX_Object *object = handle->object; + + DebugP_log1("UART:(%p) posting read semaphore", + ((UARTCC26XX_HWAttrsV2 const *)(handle->hwAttrs))->baseAddr); + + SemaphoreP_post(&(object->readSem)); +} + +/* + * ======== writeData ======== + * Write and process data to the UART. + */ +static int32_t writeData(UART_Handle handle, int32_t size) +{ + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Send characters until FIFO is full or done. */ + while (size) { + /* Send the next character and increment counts. */ + if (!UARTCharPutNonBlocking(hwAttrs->baseAddr, *(unsigned char *)(object->writeBuf))) { + /* Character was not sent */ + break; + } + DebugP_log2("UART:(%p) Wrote character 0x%x", + hwAttrs->baseAddr, *(unsigned char *)object->writeBuf); + object->writeBuf = (unsigned char *)object->writeBuf + 1; + size--; + object->writeCount++; + } + return (size); +} + +/* + * ======== readData ======== + * Read and process data from the UART. + * @param(size) number of bytes to be read + */ +static int32_t readData(UART_Handle handle, int32_t size) +{ + int32_t readIn; + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Receive chars until empty or done. */ + while (size && (readIn = (int32_t)UARTCharGetNonBlocking(hwAttrs->baseAddr)) != -1) { + + DebugP_log2("UART:(%p) Read character 0x%x", + hwAttrs->baseAddr, (uint8_t)readIn); + + /* Update status. */ + *((unsigned char *)object->readBuf) = (uint8_t)readIn; + object->readBuf = (unsigned char *)object->readBuf + 1; + object->readCount++; + size--; + } + return (size); +} + +/* + * ======== readData2RingBuf ======== + * Read and process data from the UART to RingBuf. + * @param(size) number of bytes to be read + */ +static int32_t readData2RingBuf(UART_Handle handle, int32_t size) +{ + int32_t readIn; + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Fill up RingBuf */ + while (size && (readIn = (int32_t)UARTCharGetNonBlocking(hwAttrs->baseAddr)) != -1) { + + DebugP_log2("UART:(%p) Read character 0x%x", + hwAttrs->baseAddr, (uint8_t)readIn); + + size--; + RingBuf_put(&object->ringBuffer, (unsigned char)readIn); + } + + return (size); +} + + +/* + * ======== startTxFifoEmptyClk ======== + * Last write to TX FIFO is done, but not shifted out yet. Start a clock + * which will trigger when the TX FIFO should be empty. + * + * @param handle The UART_Handle for ongoing write. + * @param numOfDataInFifo The number of data present in FIFO after last write + */ +static void startTxFifoEmptyClk(UART_Handle handle, unsigned int numOfDataInFifo) +{ + UARTCC26XX_Object *object; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Ensure that the clock is stopped so we can set a new timeout */ + ClockP_stop((ClockP_Handle) &(object->txFifoEmptyClk)); + + /* No more to write, but data is not shifted out properly yet. + * 1. Compute appropriate wait time for FIFO to empty out + * - 1 bit for start bit + * - 5+(object->dataLength) for total data length + * - +1 to "map" from stopBits to actual number of bits + * - 1000000 so we get 1 us resolution + * - 100 (100us) for margin + */ + unsigned int writeTimeoutUs = (numOfDataInFifo*(1+5+(object->dataLength)+(object->stopBits+1))*1000000)/object->baudRate + 100; + /* 2. Configure clock object to trigger when FIFO is empty + * - +1 in case clock module due to tick in less than one ClockP_tickPeriod + * - UNIT_DIV_ROUNDUP to avoid fractional part being truncated during division + */ + + ClockP_setTimeout((ClockP_Handle) &(object->txFifoEmptyClk), + (1 + UNIT_DIV_ROUNDUP(writeTimeoutUs, ClockP_tickPeriod))); + ClockP_start((ClockP_Handle) &(object->txFifoEmptyClk)); +} + +/* + * ======== writeFinishedDoCallback ======== + * Write finished - make callback + * + * This function is called when the txFifoEmptyClk times out. The TX FIFO + * should now be empty and all bytes have been transmitted. The TX will be + * turned off, TX interrupt is disabled and standby is allowed again. + * + * @param(handle) The UART_Handle for ongoing write. + */ +static void writeFinishedDoCallback(UART_Handle handle) +{ + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Function verifies that the FIFO is empty via BUSY flag */ + /* If not yet ready start the periodic timer and wait another period*/ + /* Return.. */ + if(UARTBusy(hwAttrs->baseAddr)){ + /* The UART is still busy. + * Wait 500 us before checking again or 1 tick period if the + * ClockP_tickPeriod is larger than 500 us. + */ + ClockP_setTimeout((ClockP_Handle) &(object->txFifoEmptyClk), MAX((500/ClockP_tickPeriod),1)); + ClockP_start((ClockP_Handle) &(object->txFifoEmptyClk)); + return; + } + + SwiP_or(&(object->swi), WRITE_DONE); +} + +/* + * ======== writeTxFifoFlush ======== + * Write cancelled or timed out, the TX FIFO must be flushed out. + * + * This function is called either from writeCancel or when a blocking write + * has timed out. The HW does not support a simple API for flushing the TX FIFO + * so a workaround is done in SW. + * + * @pre The TX FIFO empty clock must have been started in blocking mode. + * + * @param object Pointer to UART object + * @param hwAttrs Pointer to UART hwAttrs + */ +static void writeTxFifoFlush(UARTCC26XX_Object *object, UARTCC26XX_HWAttrsV2 const *hwAttrs) +{ + unsigned int key; + + /*It is not possible to flush the TX FIFO with simple write to HW, doing workaround: + * 0. Disable TX interrupt + */ + key = HwiP_disable(); + UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX); + HwiP_restore(key); + + /* 1. Ensure TX IO will stay high when connected to GPIO */ + PIN_setOutputEnable(object->hPin, hwAttrs->txPin, 1); + PIN_setOutputValue(object->hPin, hwAttrs->txPin, 1); + /* 2. Disconntect tx from IO, and set it as "GPIO" */ + PINCC26XX_setMux(object->hPin, hwAttrs->txPin, IOC_PORT_GPIO); + /* 3. Disconnect cts */ + PINCC26XX_setMux(object->hPin, hwAttrs->ctsPin, IOC_PORT_GPIO); + /*4. Wait for TX FIFO to become empty. + * CALLBACK: Idle until the TX FIFO is empty, i.e. no longer busy. + * BLOCKING: Periodically check if TX is busy emptying the FIFO. + * Must be handled at TX FIFO empty clock timeout: + * - the timeout/finish function must check the status + */ + if(object->writeMode == UART_MODE_CALLBACK) { + /* Wait until the TX FIFO is empty. CALLBACK mode can be used from + * hwi/swi context, so we cannot use semaphore.. + */ + while(UARTBusy(hwAttrs->baseAddr)); + } else { /* i.e. UART_MODE_BLOCKING */ + /* Pend on semaphore again..(this time forever since we are flushing + * TX FIFO and nothing should be able to stop it.. + */ + SemaphoreP_pend(&(object->writeSem), SemaphoreP_WAIT_FOREVER); + } + /* 5. Revert to active pins before returning */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) + PINCC26XX_setMux(object->hPin, hwAttrs->txPin, (hwAttrs->baseAddr == UART0_BASE ? IOC_PORT_MCU_UART0_TX : IOC_PORT_MCU_UART1_TX)); + if(isFlowControlEnabled(hwAttrs)) { + PINCC26XX_setMux(object->hPin, hwAttrs->ctsPin, (hwAttrs->baseAddr == UART0_BASE ? IOC_PORT_MCU_UART0_CTS : IOC_PORT_MCU_UART1_CTS)); + } +#else + PINCC26XX_setMux(object->hPin, hwAttrs->txPin, IOC_PORT_MCU_UART0_TX); + if(isFlowControlEnabled(hwAttrs)) { + PINCC26XX_setMux(object->hPin, hwAttrs->ctsPin, IOC_PORT_MCU_UART0_CTS); + } +#endif +} + +/* + * ======== UARTCC26XX_hwiIntFxn ======== + * Hwi function that processes UART interrupts. + * + * Six UART interrupts are enabled when configured for RX: Receive timeout, + * receive FIFO at configured threshold (4/8 full by default) and all four + * error interrupts. + * + * One interrupt is enabled when configured for TX: Transmit FIFO at configured + * threshold (7/8 empty by default). + * + * The RX and TX can operate independently of each other. + * + * When the read or write is finished they will + * post the semaphore or make the callback and log the transfer. + * + * @param arg The UART_Handle for this Hwi. + */ +void UARTCC26XX_hwiIntFxn(uintptr_t arg) +{ + unsigned long intStatus; + unsigned long errStatus = UART_OK; + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = ((UART_Handle)arg)->object; + hwAttrs = ((UART_Handle)arg)->hwAttrs; + + /* Clear interrupts */ + intStatus = UARTIntStatus(hwAttrs->baseAddr, true); + UARTIntClear(hwAttrs->baseAddr, intStatus); + + DebugP_log2("UART:(%p) Interrupt with mask 0x%x", + hwAttrs->baseAddr, intStatus); + + /* Record readSize */ + int32_t readSize = object->readSize; + int32_t readSize_ringBuf = object->ringBuffer.length - object->ringBuffer.count; + + /* Basic error handling */ + if (intStatus & (UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE)) { + + /* If overrun, the error bit is set immediately */ + if (intStatus & UART_INT_OE) { + /* check receive status register */ + errStatus = UARTRxErrorGet(hwAttrs->baseAddr); + UARTRxErrorClear(hwAttrs->baseAddr); + /* read out min of readsize and fifo size */ + int32_t bytesToRead = MIN(UARTCC26XX_FIFO_SIZE, readSize); + readData((UART_Handle)arg, bytesToRead); + /* read the rest into RingBuf */ + bytesToRead = MIN((UARTCC26XX_FIFO_SIZE - bytesToRead), readSize_ringBuf); + readData2RingBuf((UART_Handle)arg, bytesToRead); + } + else { + /* + * else, for break, framing and par. error bits are at error index + * (we would like to keep the "surviving" bits) + */ + /* Only if UART_read is active */ + while(object->readSize > 0) { + /* read one data */ + readData((UART_Handle)arg, 1); + /* check receive status register if byte is OK */ + errStatus = UARTRxErrorGet(hwAttrs->baseAddr); + UARTRxErrorClear(hwAttrs->baseAddr); + if(errStatus != 0) { + /* + * last read was not including data, reset data vars + * (i.e. upd readBuf pointer, decr readCount) + */ + object->readBuf = (unsigned char *)object->readBuf - 1; + object->readCount--; + /* the FIFO index with error is reached, stop reading */ + break; + } + else { + /* current read was not the problem update readSize */ + object->readSize--; + } + } + + /* If we managed to read out all bytes when checking for errors, make sure to post the Swi + * and read remaining data into the ring buffer */ + if (!object->readSize) { + /* Read succeeded. */ + SwiP_or(&(object->swi), READ_DONE); + /* Read any remaining data in the FIFO into the ring buffer. */ + readData2RingBuf((UART_Handle)arg, readSize_ringBuf); + } + } + + /* Report current error status */ + object->status = (UART_Status)errStatus; + + /* Break and clean up any ongoing transaction */ + UARTCC26XX_readCancel((UART_Handle)arg); + + /* Notify application of error */ + if (hwAttrs->errorFxn) { + hwAttrs->errorFxn((UART_Handle)arg, errStatus); + } + } + else { + /* Receive Timeout */ + if(intStatus & UART_INT_RT) { + /* if UART_read is active */ + if (readSize) { + /* Read data from FIFO. */ + object->readSize = readData((UART_Handle)arg, readSize); + + /* If return partial is set */ + if(object->readRetPartial) { + /* Partial read accepted, read succeeded by def, set + * readSize to allow callback to trigger new _read() + */ + object->readSize = 0; + /* Read succeeded */ + SwiP_or(&(object->swi), READ_DONE); + } + /* else - return when all bytes have arrived */ + else { + /* If all bytes are read */ + if(!object->readSize) { + /* Read succeeded */ + SwiP_or(&(object->swi), READ_DONE); + } + } + } + else { + /* not during UART_read, put in RingBuf */ + readData2RingBuf((UART_Handle)arg, readSize_ringBuf); + } + } + else { + /* RX interrupt, since CTS is handled by HW */ + if (intStatus & UART_INT_RX) { + if (readSize) { + /* if UART_read is active */ + + /* Read whatever is less of: + * - FIFO_THR bytes - 1 (leave one byte to trigger RT timeout) + * - object->readSize (never read more than requested from application) + * since RT timeout will only trigger if FIFO is not empty. + */ + size_t readFifoThresholdBytes = rxFifoBytes[hwAttrs->rxIntFifoThr]; + size_t bytesToRead = MIN(readFifoThresholdBytes - 1, object->readSize); + + /* Do read, all bytes we request to read, are present in FIFO */ + readData((UART_Handle)arg, bytesToRead); + + /* Decrement object->readSize with the actual number of bytes read + * There will always be at least bytesToRead number of bytes in FIFO + */ + object->readSize -= bytesToRead; + + /* If all bytes are read */ + if (!object->readSize) { + /* Read succeeded. */ + SwiP_or(&(object->swi), READ_DONE); + + /* Read any remaining data in the FIFO into the ring buffer. */ + readData2RingBuf((UART_Handle)arg, readSize_ringBuf); + } + } + else { + /* not during UART_read, put all in RingBuf */ + readData2RingBuf((UART_Handle)arg, readSize_ringBuf); + } + } + } + } + + /* Write if there are characters to be written. */ + if ((intStatus & UART_INT_TX) && object->writeSize) { + /* Using writtenLast=writeSize before last write + *(since writeSize=0 when the last finishes) + */ + uint32_t writtenLast = object->writeSize; + object->writeSize = writeData((UART_Handle)arg, object->writeSize); + if(!object->writeSize) { + /* No more to write, but data is not shifted out properly yet. + * Start TX FIFO Empty clock, which will trigger the txFifoEmptyClk + * function. + * The number of bytes left in the TX FIFO when the TX FIFO threshold + * interrupt occurs are added to writtenLast. + */ + startTxFifoEmptyClk((UART_Handle)arg, (writtenLast + txFifoBytes[hwAttrs->txIntFifoThr])); + } + } +} + +/* + * ======== UARTCC26XX_swiIntFxn ======== + * Swi function that processes UART interrupts. + * @param arg The UART_Handle for this Hwi. + */ +void UARTCC26XX_swiIntFxn(uintptr_t arg0, uintptr_t arg1) +{ + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + uint32_t trigger = SwiP_getTrigger(); + + /* Get the pointer to the object and hwAttrs */ + object = ((UART_Handle)arg0)->object; + hwAttrs = (UARTCC26XX_HWAttrsV2 const *)(((UART_Handle)arg0)->hwAttrs); + + if (trigger & READ_DONE) { + /* Release power constraint. */ + threadSafeStdbyDisRelease(&(object->uartRxPowerConstraint)); + + /* Reset the read buffer so we can pass it back */ + object->readBuf = (unsigned char *)object->readBuf - object->readCount; + + /* Do Callback */ + object->readCallback((UART_Handle)arg0, object->readBuf, + object->readCount); + + DebugP_log2("UART:(%p) Read finished, %d bytes read", + hwAttrs->baseAddr, object->readCount); + } + + if (trigger & WRITE_DONE) { + /* Release constraint since transaction is done */ + threadSafeStdbyDisRelease(&(object->uartTxPowerConstraint)); + + /* Disable TX interrupt */ + UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX); + + /* Disable TX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_TXE); + + /* Reset the write buffer so we can pass it back */ + object->writeBuf = (unsigned char *)object->writeBuf - object->writeCount; + + /* Make callback */ + object->writeCallback((UART_Handle)arg0, (uint8_t*)object->writeBuf, + object->writeCount); + DebugP_log2("UART:(%p) Write finished, %d bytes written", + hwAttrs->baseAddr, object->writeCount); + } +} + +/*! + * @brief UART CC26XX initialization + * + * @pre Calling context: Hwi, Swi, Task, Main + * + * @param handle A UART_Handle + * + */ +void UARTCC26XX_init(UART_Handle handle) +{ + UARTCC26XX_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + object->opened = false; +} + +/*! + * @brief Function to initialize the CC26XX UART peripheral specified by the + * particular handle. The parameter specifies which mode the UART + * will operate. + * + * The function will set a dependency on it power domain, i.e. power up the + * module and enable the clock. The IOs are allocated. Neither the RX nor TX + * will be enabled, and none of the interrupts are enabled. + * + * @pre UART controller has been initialized + * Calling context: Task + * + * @param handle A UART_Handle + * + * @param params Pointer to a parameter block, if NULL it will use + * default values + * + * @return A UART_Handle on success or a NULL on an error or if it has been + * already opened + * + * @sa UARTCC26XX_close() + */ +UART_Handle UARTCC26XX_open(UART_Handle handle, UART_Params *params) +{ + unsigned int key; + /* Use union to save on stack allocation */ + union { + HwiP_Params hwiParams; + SwiP_Params swiParams; + ClockP_Params clkParams; + } paramsUnion; + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable preemption while checking if the UART is open. */ + key = HwiP_disable(); + + /* Check if the UART is open already with the base addr. */ + if (object->opened == true) { + HwiP_restore(key); + + DebugP_log1("UART:(%p) already in use.", hwAttrs->baseAddr); + + return (NULL); + } + object->opened = true; + HwiP_restore(key); + + /* Check that a callback is set */ + DebugP_assert(params->readMode != UART_MODE_CALLBACK || + params->readCallback != NULL); + DebugP_assert(params->writeMode != UART_MODE_CALLBACK || + params->writeCallback != NULL); + + /* Initialize the UART object */ + object->readMode = params->readMode; + object->writeMode = params->writeMode; + object->readTimeout = params->readTimeout; + object->writeTimeout = params->writeTimeout; + object->readCallback = params->readCallback; + object->writeCallback = params->writeCallback; + object->readReturnMode = params->readReturnMode; + object->readDataMode = params->readDataMode; + object->writeDataMode = params->writeDataMode; + object->baudRate = params->baudRate; + object->dataLength = params->dataLength; + object->stopBits = params->stopBits; + object->parityType = params->parityType; + + /* Set UART transaction variables to defaults. */ + object->writeBuf = NULL; + object->readBuf = NULL; + object->writeCount = 0; + object->readCount = 0; + object->writeSize = 0; + object->readSize = 0; + object->writeCR = false; + object->readRetPartial = false; + + object->uartRxPowerConstraint = false; + object->uartTxPowerConstraint = false; + + /* Register power dependency - i.e. power up and enable clock for UART. */ + Power_setDependency(hwAttrs->powerMngrId); + + /* Initialize the UART hardware module */ + UARTCC26XX_initHw(handle); + + /* Configure IOs, make sure it was successful */ + if(!UARTCC26XX_initIO(handle)) { + /* Trying to use UART driver when some other driver or application + * has already allocated these pins, error! + */ + DebugP_log0("Could not allocate pins, already in use."); + /* Disable UART */ + UARTDisable(hwAttrs->baseAddr); + /* Release power dependency - i.e. potentially power down serial domain. */ + Power_releaseDependency(hwAttrs->powerMngrId); + /* Mark the module as available */ + key = HwiP_disable(); + object->opened = false; + HwiP_restore(key); + /* Signal back to application that UART driver was not succesfully opened */ + return (NULL); + } + + /* Create Hwi object for this UART peripheral. */ + HwiP_Params_init(&(paramsUnion.hwiParams)); + paramsUnion.hwiParams.arg = (uintptr_t)handle; + paramsUnion.hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), hwAttrs->intNum, UARTCC26XX_hwiIntFxn, + &(paramsUnion.hwiParams)); + + /* Create Swi object for this UART peripheral */ + SwiP_Params_init(&(paramsUnion.swiParams)); + paramsUnion.swiParams.arg0 = (uintptr_t)handle; + paramsUnion.swiParams.priority = hwAttrs->swiPriority; + SwiP_construct(&(object->swi), UARTCC26XX_swiIntFxn, &(paramsUnion.swiParams)); + + /* Initialize semaphore */ + + /* If write mode is blocking create a semaphore and set callback. */ + if (object->writeMode == UART_MODE_BLOCKING) { + SemaphoreP_constructBinary(&(object->writeSem), 0); + object->writeCallback = &writeSemCallback; + } + + /* If read mode is blocking create a semaphore and set callback. */ + if (object->readMode == UART_MODE_BLOCKING) { + SemaphoreP_constructBinary(&(object->readSem), 0); + object->readCallback = &readSemCallback; + } + + /* Create clock object to be used for write FIFO empty callback */ + ClockP_Params_init(¶msUnion.clkParams); + paramsUnion.clkParams.period = 0; + paramsUnion.clkParams.startFlag = false; + paramsUnion.clkParams.arg = (uintptr_t) handle; + ClockP_construct(&(object->txFifoEmptyClk), + (ClockP_Fxn) &writeFinishedDoCallback, + 10, &(paramsUnion.clkParams)); + + /* Create circular buffer object to be used for read buffering */ + RingBuf_construct(&object->ringBuffer, hwAttrs->ringBufPtr, hwAttrs->ringBufSize); + + /* Register notification function */ + Power_registerNotify(&object->uartPostObj, PowerCC26XX_AWAKE_STANDBY, (Power_NotifyFxn)uartPostNotify, (uint32_t)handle); + + /* UART opened successfully */ + DebugP_log1("UART:(%p) opened", hwAttrs->baseAddr); + + /* Return the handle */ + return (handle); +} + +/*! + * @brief Function to close a given CC26XX UART peripheral specified by the + * UART handle. + * + * Will disable the UART, disable all UART interrupts and release the + * dependency on the corresponding power domain. + * + * @pre UARTCC26XX_open() had to be called first. + * Calling context: Task + * + * @param handle A UART_Handle returned from UART_open() + * + * @sa UARTCC26XX_open + */ +void UARTCC26XX_close(UART_Handle handle) +{ + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Deallocate pins */ + PIN_close(object->hPin); + + /* Disable all UART module interrupts. */ + UARTIntDisable(hwAttrs->baseAddr, UART_INT_OE | UART_INT_BE | UART_INT_PE | + UART_INT_FE | UART_INT_RT | UART_INT_TX | + UART_INT_RX | UART_INT_CTS); + + /* Mark the module as available */ + object->opened = false; + + /* Cancel any possible ongoing reads/writes */ + UARTCC26XX_writeCancel(handle); + UARTCC26XX_readCancel(handle); + + /* Disable UART FIFO */ + HWREG(hwAttrs->baseAddr + UART_O_LCRH) &= ~(UART_LCRH_FEN); + /* Disable UART module */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); + + /* Release power dependency - i.e. potentially power down serial domain. */ + Power_releaseDependency(hwAttrs->powerMngrId); + + /* Destruct the SYS/BIOS objects. */ + HwiP_destruct(&(object->hwi)); + SwiP_destruct(&(object->swi)); + if (object->writeMode == UART_MODE_BLOCKING) { + SemaphoreP_destruct(&(object->writeSem)); + } + if (object->readMode == UART_MODE_BLOCKING) { + SemaphoreP_destruct(&(object->readSem)); + } + ClockP_destruct(&(object->txFifoEmptyClk)); + + /* Unregister power notification objects */ + Power_unregisterNotify(&object->uartPostObj); + + DebugP_log1("UART:(%p) closed", hwAttrs->baseAddr); +} + + +/*! + * @brief Function for setting control parameters of the UART + * after it has been opened. + * + * @pre UARTCC26XX_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A UART handle returned from UARTCC26XX_open() + * + * @param cmd The command to execute, supported commands are: + * | Command | Description | + * |-------------------------------------- |-------------------------| + * | ::UARTCC26XX_CMD_RETURN_PARTIAL_ENABLE | Enable RETURN_PARTIAL | + * | ::UARTCC26XX_CMD_RETURN_PARTIAL_DISABLE| Disable RETURN_PARTIAL | + * + * @param *arg Pointer to command arguments, currently not in use, set to NULL. + * + * @return ::UART_STATUS_SUCCESS if success, or error code if error. + */ +int_fast16_t UARTCC26XX_control(UART_Handle handle, uint_fast16_t cmd, + void *arg) +{ + /* Locals */ + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + unsigned int key; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Initialize return value*/ + int ret = UART_STATUS_UNDEFINEDCMD; + /* Do command*/ + switch(cmd) + { + case UARTCC26XX_CMD_RETURN_PARTIAL_ENABLE: + /* Enable RETURN_PARTIAL */ + object->readRetPartial = true; + ret = UART_STATUS_SUCCESS; + break; + + case UARTCC26XX_CMD_RETURN_PARTIAL_DISABLE: + /* Disable RETURN_PARTIAL */ + object->readRetPartial = false; + ret = UART_STATUS_SUCCESS; + break; + + case UARTCC26XX_CMD_RX_FIFO_FLUSH: + /* Flush RX FIFO */ + hwAttrs = handle->hwAttrs; + + /* Disable interrupts to avoid reading data while changing state. */ + key = HwiP_disable(); + + /* Read RX FIFO until empty */ + while (((int32_t)UARTCharGetNonBlocking(hwAttrs->baseAddr)) != -1); + + /* Reset RingBuf */ + object->ringBuffer.count = 0; + object->ringBuffer.head = object->ringBuffer.length - 1; + object->ringBuffer.tail = 0; + + /* Set size = 0 to prevent reading and restore interrupts. */ + object->readSize = 0; + HwiP_restore(key); + + ret = UART_STATUS_SUCCESS; + break; + + default: + /* This command is not defined */ + ret = UART_STATUS_UNDEFINEDCMD; + break; + } + + /* Return */ + return (ret); +} + +/*! + * @brief Function that writes data to a UART + * + * This function initiates an operation to write data to CC26XX UART + * controller. + * + * In ::UART_MODE_BLOCKING, UART_write will block task execution until all + * the data in buffer has been written. + * + * In ::UART_MODE_CALLBACK, UART_write does not block task execution, but calls a + * callback function specified by writeCallback when the data has been written. + * + * When the write function is called, TX is enabled, TX interrupt is enabled, + * and standby is not allowed. + * + * @pre UARTCC26XX_open() has to be called first. + * Calling context: Hwi and Swi (only if using ::UART_MODE_CALLBACK), Task + * + * @param handle A UART_Handle returned from UARTCC26XX_open() + * + * @param buffer A pointer to buffer containing data to be written + * + * @param size The number of bytes in buffer that should be written + * onto the UART. + * + * @return Returns the number of bytes that have been written to the UART, + * UART_ERROR on an error. + * + */ +int_fast32_t UARTCC26XX_write(UART_Handle handle, const void *buffer, + size_t size) +{ + unsigned int key; + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + + /* Get the pointer to the object */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Check that there is data to write */ + DebugP_assert(size != 0); + + /* Disable preemption while checking if the UART is in use. */ + key = HwiP_disable(); + /* The UART TX is disabled after a successful write, if it is + * still active another write is in progress, reject. */ + uint32_t writeActive = HWREG(hwAttrs->baseAddr + UART_O_CTL) & (UART_CTL_TXE); + if (!object->opened || writeActive) { + HwiP_restore(key); + DebugP_log1("UART:(%p) Could not write data, uart closed or in use.", + ((UARTCC26XX_HWAttrsV2 const *)(handle->hwAttrs))->baseAddr); + + return (UART_ERROR); + } + + /* Stop the txFifoEmpty clock in case it was running due to a previous write operation */ + ClockP_stop((ClockP_Handle) &(object->txFifoEmptyClk)); + + /* Update the status of the UART module */ + object->status = UART_OK; + + /* Save the data to be written and restore interrupts. */ + object->writeBuf = buffer; + object->writeCount = 0; + + /* Enable TX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_TXE; + + HwiP_restore(key); + + /* Set constraints to guarantee transaction */ + threadSafeStdbyDisSet(&(object->uartTxPowerConstraint)); + + uint32_t writtenLast = size; + /* Fill up TX FIFO */ + if (!(object->writeSize = writeData(handle, size))) { + /* No more data to transmit - Write is finished but all bytes + * may not have been shifted out. */ + startTxFifoEmptyClk((UART_Handle)handle, writtenLast); + + /* If writeMode is blocking, block and get the status. */ + if (object->writeMode == UART_MODE_BLOCKING) { + /* Pend on semaphore and wait for Hwi to finish. */ + if (SemaphoreP_OK != SemaphoreP_pend(&(object->writeSem), + object->writeTimeout)) { + /* Reset writeSize */ + object->writeSize = 0; + + /* Set status to TIMED_OUT */ + object->status = UART_TIMED_OUT; + + /* Workaround for flushing the TX FIFO */ + writeTxFifoFlush(object, hwAttrs); + + /* Release constraint */ + threadSafeStdbyDisRelease(&(object->uartTxPowerConstraint)); + + DebugP_log2("UART:(%p) Write timed out, %d bytes written", + ((UARTCC26XX_HWAttrsV2 const *)(handle->hwAttrs))->baseAddr, + object->writeCount); + + /* Return UART_ERROR to indicate something went wrong, object->status set to UART_TIMED_OUT*/ + return UART_ERROR; + } + return (object->writeCount); + } + } else { + + key = HwiP_disable(); + + /* Enable TX interrupts */ + UARTIntEnable(hwAttrs->baseAddr, UART_INT_TX); + + HwiP_restore(key); + + /* If writeMode is blocking, block and get the status. */ + if (object->writeMode == UART_MODE_BLOCKING) { + /* Pend on semaphore and wait for Hwi to finish. */ + if (SemaphoreP_OK != SemaphoreP_pend(&(object->writeSem), + object->writeTimeout)) { + /* Semaphore timed out, make the write empty and log the write. */ + + /* Starting a timer to enable the posting of semaphore used in writeTxFifoFlush. + * writtenLast in this case is equal to full TX FIFO. This is a conservative number as + * some of the data might have been sent. + */ + startTxFifoEmptyClk((UART_Handle)handle, writtenLast); + + /* Reset writeSize */ + object->writeSize = 0; + + /* Set status to TIMED_OUT */ + object->status = UART_TIMED_OUT; + + /* Workaround for flushing the TX FIFO */ + writeTxFifoFlush(object, hwAttrs); + + /* Release constraint */ + threadSafeStdbyDisRelease(&(object->uartTxPowerConstraint)); + + DebugP_log2("UART:(%p) Write timed out, %d bytes written", + ((UARTCC26XX_HWAttrsV2 const *)(handle->hwAttrs))->baseAddr, + object->writeCount); + + /* Return UART_ERROR to indicate something went wrong (object->status set to UART_TIMED_OUT)*/ + return UART_ERROR; + } + + /* Return the numbers of samples written */ + return (object->writeCount); + } + } + /* This return will only be active in UART_MODE_CALLBACK mode. */ + return (0); +} + +/*! + * @brief This function is NOT supported + * + * @pre UARTCC26XX_open() and has to be called first. + * Calling context: Task + * + * @param handle The UART_Handle for ongoing write. + * + * @param buf A pointer to buffer containing data to be written + * + * @param size The number of bytes in buffer that should be written + * onto the UART. + * + * @return Always ::UART_ERROR + */ +int_fast32_t UARTCC26XX_writePolling(UART_Handle handle, const void *buf, + size_t size) +{ + /* Not supported */ + return (UART_ERROR); +} + +/*! + * @brief Function that cancel UART write. Will disable TX interrupt, disable + * TX and allow standby. + * + * @pre UARTCC26XX_open() and has to be called first. + * Calling context: Task + * + * @param handle The UART_Handle for ongoing write. + */ +void UARTCC26XX_writeCancel(UART_Handle handle) +{ + unsigned int key; + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + + /* Get the pointer to the object */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable interrupts to avoid writing data while changing state. */ + key = HwiP_disable(); + + /* Return if there is nothing to write and TX FIFO is empty. */ + if (!object->writeSize && + !UARTBusy(hwAttrs->baseAddr) && + !(HWREG(hwAttrs->baseAddr + UART_O_CTL) & (UART_CTL_TXE))) { + HwiP_restore(key); + return; + } + + /* Stop the clock in case we have finished shifting out the + * tx bytes but the tx FIFO empty clock has not timed out yet. + * Otherwise the clock will timeout and behave as though the + * operation were not canceled resulting in two callbacks for + * the same operation. + */ + ClockP_stop((ClockP_Handle) &(object->txFifoEmptyClk)); + + /* Set size = 0 to prevent writing and restore interrupts. */ + object->writeSize = 0; + HwiP_restore(key); + + /* If flow control is enabled, a workaround for flushing the fifo is needed..*/ + if (isFlowControlEnabled(hwAttrs)) { + writeTxFifoFlush(object, hwAttrs); + } + + key = HwiP_disable(); + + /* Disable TX interrupt */ + UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX); + + /* Disable UART TX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_TXE); + + HwiP_restore(key); + + /* Release constraint since transaction is done */ + threadSafeStdbyDisRelease(&(object->uartTxPowerConstraint)); + + /* Reset the write buffer so we can pass it back */ + object->writeBuf = (unsigned char *)object->writeBuf - object->writeCount; + object->writeCallback(handle, (uint8_t*)object->writeBuf, + object->writeCount); + + DebugP_log2("UART:(%p) Write canceled, " + "%d bytes written", + ((UARTCC26XX_HWAttrsV2 const *)(handle->hwAttrs))->baseAddr, + object->writeCount); +} + +/*! + * @brief Function for reading from UART interface. + * + * The function will enable the RX, enable all RX interrupts and disallow + * chip from going into standby. + * + * @pre UARTCC26XX_open() has to be called first. + * Calling context: Hwi and Swi (only if using ::UART_MODE_CALLBACK), Task + * + * @param handle A UART handle returned from UARTCC26XX_open() + * + * @param *buffer Pointer to read buffer + * +* @param size Number of bytes to read. If ::UARTCC26XX_CMD_RETURN_PARTIAL_ENABLE + * has been set, the read will + * return if the reception is inactive for a 32-bit period + * (i.e. before all bytes are received). + * + * @return Number of samples read + * + * @sa UARTCC26XX_open(), UARTCC26XX_readCancel() + */ +int_fast32_t UARTCC26XX_read(UART_Handle handle, void *buffer, size_t size) +{ + unsigned char readIn; + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + size_t objectReadSize; + unsigned int key; + + /* Get the pointer to the object */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + if (!object->opened) { + DebugP_log1("UART:(%p) not opened.", hwAttrs->baseAddr); + return (UART_ERROR); + } + + if (object->readSize) { + /* Previous read is not done, return */ + DebugP_log1("UART:(%p) Could not read data, uart in use.", + ((UARTCC26XX_HWAttrsV2 const *)(handle->hwAttrs))->baseAddr); + + return (UART_ERROR); + } + + /* Set readSize */ + objectReadSize = size; + + /* Update the status of the UART module */ + object->status = UART_OK; + + /* Save the data to be read and restore interrupts. */ + object->readBuf = buffer; + object->readCount = 0; + + /* Read from RingBuf as much as is available */ + while (objectReadSize) { + int rdCount; + + /* Disable interrupts while reading from the ring buffer */ + key = HwiP_disable(); + rdCount = RingBuf_get(&object->ringBuffer, &readIn); + if (rdCount < 0) { + /* RingBuf is empty, need to read from FIFO */ + object->readSize = objectReadSize; + + /* Enable RX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_RXE; + + /* Enable RX interrupts */ + UARTIntEnable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT | + UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE); + + HwiP_restore(key); + + /* Set constraint for sleep to guarantee transaction */ + threadSafeStdbyDisSet(&(object->uartRxPowerConstraint)); + + /* If readMode is blocking, block and get the status. */ + if (object->readMode == UART_MODE_BLOCKING) { + /* + * Check for return partial case before waiting on the + * semaphore. It's possible that no more data will come + * in to post the semaphore or cause a read timeout. + */ + key = HwiP_disable(); + + if ((object->readRetPartial) && (object->readCount) + && (object->readSize)) { + /* Return partial enabled and some data has been read */ + /* Reset readSize to allow next UART_read() */ + object->readSize = 0; + HwiP_restore(key); + + /* Release the constraint */ + threadSafeStdbyDisRelease(&(object->uartRxPowerConstraint)); + + /* return the number of data read */ + return (object->readCount); + } + HwiP_restore(key); + + /* Pend on semaphore and wait for Hwi to finish. */ + if (SemaphoreP_OK != SemaphoreP_pend(&(object->readSem), + object->readTimeout)) { + + /* + * If the ISR posts the semaphore here, the count will be + * wrong, so we'll pend again with 0 timeout after setting + * the read size to 0 + */ + /* Semaphore timed out, make the read empty and log the read. */ + object->readSize = 0; + + if (SemaphoreP_OK != SemaphoreP_pend(&(object->readSem), + SemaphoreP_NO_WAIT)) { + /* + * Release constraint since transaction timed out, + * allowed to enter standby + */ + threadSafeStdbyDisRelease(&(object->uartRxPowerConstraint)); + + /* Reset the read buffer so we can pass it back */ + object->readBuf = (unsigned char *)object->readBuf - + object->readCount; + + /* Set status to TIMED_OUT */ + object->status = UART_TIMED_OUT; + + DebugP_log2("UART:(%p) Read timed out, %d bytes read", + ((UARTCC26XX_HWAttrsV2 const *)(handle->hwAttrs))->baseAddr, + object->readCount); + } + } + + /* return the number of data read */ + return (object->readCount); + } + + /* + * Post Swi for return partial case. Disable interrupts to + * ensure that the ISR does not finish the read and also post + * the Swi before we set object->readSize to 0. Check + * object->readSize in case the ISR already posted the Swi. + */ + key = HwiP_disable(); + + /* readMode is callback */ + if ((object->readRetPartial) && (object->readCount) + && (object->readSize)) { + /* Return partial enabled and some data has been read */ + /* Reset readSize to allow next UART_read() */ + object->readSize = 0; + HwiP_restore(key); + + /* Read succeeded */ + SwiP_or(&(object->swi), READ_DONE); + } + else { + HwiP_restore(key); + } + + return (0); + } + + HwiP_restore(key); + + /* save data to receive buffer */ + *((unsigned char *)object->readBuf) = (uint8_t)readIn; + object->readBuf = (unsigned char *)object->readBuf + 1; + object->readCount++; + objectReadSize--; + } + + /* Read succeeded. */ + /* Reset the read buffer so we can pass it back */ + object->readBuf = (unsigned char *)object->readBuf - object->readCount; + + /* Do Callback */ + if (object->readMode == UART_MODE_CALLBACK) { + object->readCallback(handle, object->readBuf, object->readCount); + } + + /* return the number of data read */ + return (object->readCount); +} + +/* + * ======== UARTCC26XX_readPolling ======== + */ +int_fast32_t UARTCC26XX_readPolling(UART_Handle handle, void *buf, size_t size) +{ + /* Not supported */ + return (UART_ERROR); +} + +/*! + * @brief Function that cancel UART read. Will disable all RX interrupt, + * disable + * RX and allow standby. Should also be called after a succeeding UART + * read if no more bytes are expected and standby is wanted. + * + * @pre UARTCC26XX_open() has to be called first. + * Calling context: Task + * + * @param handle The UART_Handle for ongoing write. + */ +void UARTCC26XX_readCancel(UART_Handle handle) +{ + unsigned int key; + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + + /* Get the pointer to the object */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable interrupts to avoid reading data while changing state. */ + key = HwiP_disable(); + + /* Disable RX interrupts */ + UARTIntDisable(hwAttrs->baseAddr, UART_INT_OE | UART_INT_BE | UART_INT_PE | + UART_INT_FE | UART_INT_RT | UART_INT_RX); + + /* Release constraint since transaction is done */ + threadSafeStdbyDisRelease(&(object->uartRxPowerConstraint)); + + /* Return if there is no read. */ + if (!object->readSize) { + HwiP_restore(key); + return; + } + + /* Set size = 0 to prevent reading. */ + object->readSize = 0; + + /* Reset the read buffer so we can pass it back */ + object->readBuf = (unsigned char *)object->readBuf - object->readCount; + + /* Restore interrupts */ + HwiP_restore(key); + + object->readCallback(handle, object->readBuf, object->readCount); + + DebugP_log2("UART:(%p) Read canceled, " + "%d bytes read", + ((UARTCC26XX_HWAttrsV2 const *)(handle->hwAttrs))->baseAddr, + object->readCount); +} + +/* + * ======== UARTCC26XX_initHW ======== + * This functions initializes the UART hardware module. + * + * @pre Function assumes that the UART handle is pointing to a hardware + * module which has already been opened. + */ +static void UARTCC26XX_initHw(UART_Handle handle) { + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + ClockP_FreqHz freq; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable UART function. */ + UARTDisable(hwAttrs->baseAddr); + + /* Disable all UART module interrupts. */ + UARTIntDisable(hwAttrs->baseAddr, UART_INT_OE | UART_INT_BE | UART_INT_PE | + UART_INT_FE | UART_INT_RT | UART_INT_TX | + UART_INT_RX | UART_INT_CTS); + + /* Clear all UART interrupts */ + UARTIntClear(hwAttrs->baseAddr, UART_INT_OE | UART_INT_BE | UART_INT_PE | + UART_INT_FE | UART_INT_RT | UART_INT_TX | + UART_INT_RX | UART_INT_CTS); + + /* Set TX interrupt FIFO level and RX interrupt FIFO level */ + UARTFIFOLevelSet(hwAttrs->baseAddr, txFifoThreshold[hwAttrs->txIntFifoThr], + rxFifoThreshold[hwAttrs->rxIntFifoThr]); + + /* Configure frame format and baudrate */ + ClockP_getCpuFreq(&freq); + UARTConfigSetExpClk(hwAttrs->baseAddr, + freq.lo, + object->baudRate, + (dataLength[object->dataLength] | + stopBits[object->stopBits] | + parityType[object->parityType])); + + DebugP_log3("UART:(%p) CPU freq: %d; UART baudrate to %d", + hwAttrs->baseAddr, + freq.lo, + object->baudRate); + + /* Enable UART FIFOs */ + HWREG(hwAttrs->baseAddr + UART_O_LCRH) |= UART_LCRH_FEN; + + /* Enable the UART module */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_UARTEN; + + /* If Flow Control is enabled, configure hardware controlled flow control */ + if(isFlowControlEnabled(hwAttrs)) { + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= (UART_CTL_CTSEN | UART_CTL_RTSEN); + } +} + +/* + * ======== UARTCC26XX_initIO ======== + * This functions initializes the UART IOs. + * + * @pre Function assumes that the UART handle is pointing to a hardware + * module which has already been opened. + */ +static bool UARTCC26XX_initIO(UART_Handle handle) { + /* Locals */ + UARTCC26XX_Object *object; + UARTCC26XX_HWAttrsV2 const *hwAttrs; + PIN_Config uartPinTable[5]; + uint32_t i = 0; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Build local list of pins, allocate through PIN driver and map HW ports */ + uartPinTable[i++] = hwAttrs->rxPin | PIN_INPUT_EN; + /* Make sure UART_TX pin is driven high after calling PIN_open(...) until + * we've set the correct peripheral muxing in PINCC26XX_setMux(...) + * This is to avoid falling edge glitches when configuring the UART_TX pin. + */ + uartPinTable[i++] = hwAttrs->txPin | PIN_INPUT_DIS | PIN_PUSHPULL | + PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH; + if (isFlowControlEnabled(hwAttrs)) { + uartPinTable[i++] = hwAttrs->ctsPin | PIN_INPUT_EN; + /* Avoiding glitches on the RTS, see comment for TX pin above. */ + uartPinTable[i++] = hwAttrs->rtsPin | PIN_INPUT_DIS | PIN_PUSHPULL | + PIN_GPIO_OUTPUT_EN | PIN_GPIO_HIGH; + } + /* Terminate pin list */ + uartPinTable[i++] = PIN_TERMINATE; + + /* Open and assign pins through pin driver */ + object->hPin = PIN_open(&object->pinState, uartPinTable); + + /* Are pins already allocated */ + if (!object->hPin) { + return false; + } + + /* Set IO muxing for the UART pins */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) + PINCC26XX_setMux(object->hPin, hwAttrs->rxPin, (hwAttrs->baseAddr == UART0_BASE ? IOC_PORT_MCU_UART0_RX : IOC_PORT_MCU_UART1_RX)); + PINCC26XX_setMux(object->hPin, hwAttrs->txPin, (hwAttrs->baseAddr == UART0_BASE ? IOC_PORT_MCU_UART0_TX : IOC_PORT_MCU_UART1_TX)); + if (isFlowControlEnabled(hwAttrs)) { + PINCC26XX_setMux(object->hPin, hwAttrs->ctsPin, (hwAttrs->baseAddr == UART0_BASE ? IOC_PORT_MCU_UART0_CTS : IOC_PORT_MCU_UART1_CTS)); + PINCC26XX_setMux(object->hPin, hwAttrs->rtsPin, (hwAttrs->baseAddr == UART0_BASE ? IOC_PORT_MCU_UART0_RTS : IOC_PORT_MCU_UART1_RTS)); + } +#else + PINCC26XX_setMux(object->hPin, hwAttrs->rxPin, IOC_PORT_MCU_UART0_RX); + PINCC26XX_setMux(object->hPin, hwAttrs->txPin, IOC_PORT_MCU_UART0_TX); + if (isFlowControlEnabled(hwAttrs)) { + PINCC26XX_setMux(object->hPin, hwAttrs->ctsPin, IOC_PORT_MCU_UART0_CTS); + PINCC26XX_setMux(object->hPin, hwAttrs->rtsPin, IOC_PORT_MCU_UART0_RTS); + } +#endif + /* Success */ + return true; +} + +/* + * ======== uartPostNotify ======== + * This functions is called to notify the UART driver of an ongoing transition + * out of sleep mode. + * + * @pre Function assumes that the UART handle (clientArg) is pointing to a + * hardware module which has already been opened. + */ +static int uartPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg) +{ + /* Reconfigure the hardware if returning from sleep */ + if (eventType == PowerCC26XX_AWAKE_STANDBY) { + UARTCC26XX_initHw((UART_Handle) clientArg); + } + return Power_NOTIFYDONE; +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26XX.h new file mode 100644 index 0000000..cffdab9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26XX.h @@ -0,0 +1,645 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file UARTCC26XX.h + * + * @brief UART driver implementation for a CC26XX UART controller + * + * # Driver include # + * The UART header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref UART.h for a complete description of APIs. + * + * # Overview # + * The general UART API should used in application code, i.e. UART_open() + * is used instead of UARTCC26XX_open(). The board file will define the device + * specific config, and casting in the general API will ensure that the correct + * device specific functions are called. + * This is also reflected in the example code in [Use Cases](@ref USE_CASES). + * + * # General Behavior # + * Before using the UART in CC26XX: + * - The UART driver is initialized by calling UART_init(). + * - The UART HW is configured and flags system dependencies (e.g. IOs, + * power, etc.) by calling UART_open(). + * - The RX and TX can operate independently of each other. + * . + * The following is true for receive operation: + * - RX is enabled by calling UART_read(). + * - All received bytes are ignored after UART_open() is called, until + * the first UART_read(). + * - If an RX error occur, RX is turned off and all bytes received before the + * error occured are returned. + * - After a successful read, RX remains on. UART_read() must be called + * again before FIFO goes full in order to avoid overflow. It is safe to + * call another UART_read() from the read callback, See + * [Receive Continously] (@ref USE_CASE_CB) use case below. + * - If a read times out (in ::UART_MODE_BLOCKING mode), RX will remain on. + * UART_read() must be called again before FIFO goes full in order to avoid overflow. + * - The UART_read() supports partial return, that can be used if the + * receive size is unknown. See [Use Cases](@ref USE_CASES) below. + * - The RingBuf serves as an extension of the FIFO. If data is received when + * UART_read() is not called, data will be stored in the RingBuf. The + * functionality of the RingBuf has been tested with a size of 32. This size + * can be changed to suit the application. + * . + * The following apply for transmit operation: + * - TX is enabled by calling UART_write(). + * - If the UART_write() succeeds, the TX is disabled. + * . + * If UART is no longer needed by application: + * - Release system dependencies for UART by calling UART_close(). + * . + * If the UART is configured in ::UART_MODE_CALLBACK mode: + * - The error handling callback is run in a HWI context. + * - The regular callback is run in a SWI context. + * + * # Error handling # + * ## Read errors ## + * If an error occurs during read operation: + * - All bytes received up until an error occurs will be returned, with the + * error signaled in the ::UARTCC26XX_Object.status field. The RX is then turned off + * and all bytes will be ignored until a new read is issued. Note that only + * the read is cancelled when the error occurs. If a write was active + * while the RX error occurred, it will complete. + * - If a RX break error occurs, an extra 0 byte will also be returned by the + * UART_read(). + * . + * + * ## Write errors## + * If a timeout occurs during a write, an UART_ERROR will be returned and the + * UART_Object.status will be set to ::UART_TIMED_OUT. All bytes that are not + * transmitted, will be flushed. + * If flow control is not enabled, the ::UARTCC26XX_Object.writeTimeout should + * be kept at default value, BIOS_WAIT_FOREVER. The write call will return after + * all bytes are transmitted. + * If flow control is enabled, the timeout should be set by the application in + * order to recover if the receiver gets stuck. + * + * ## General timeout ## + * A timeout value can only be specified for reads and writes in ::UART_MODE_BLOCKING. + * If a timeout occurs during a read when in ::UART_MODE_BLOCKING, the number of bytes received will be + * returned and the UART_Object.status will be set to ::UART_TIMED_OUT. + * After a read timeout, RX will remain on, but device is allowed to enter standby. + * For more details see [Power Management](@ref POWER_MANAGEMENT) chapter below. + * + * In ::UART_MODE_CALLBACK there is no timeout and the application must call + * UART_readCancel() or UART_writeCancel() to abort the operation. + * + * @note A new read or write will reset the UART_Object.status to UART_OK. + * Caution must be taken when doing parallel reads and writes. + * + * ## Closing driver during an ongoing read/write ## + * It's safe to call UART_close() during an ongoing UART_read() and/or UART_write(), + * this will cancel the ongoing RX/TX immediately. + * + * The RX callback is alwyas called when you call UART_close() if there's an + * ongoing read. + * Note that if UART_close() is called during an ongoing read, the size provided + * in the RX callback function is 0 if < 16 bytes were received before calling UART_close(). + * This is because 16 bytes is the RX watermark that triggers the ISR + * to copy bytes from the internal UART FIFO to the software RX buffer. + * + * The TX callback is always called when you call UART_close() if there's an + * ongoing write. The driver does not wait until a byte is transmitted correctly, + * so if UART_close() is called in the middle of sending a byte, + * this byte will be corrupted. + * + * # Power Management @anchor POWER_MANAGEMENT # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * The UARTCC26XX driver is setting a power constraint during operation to keep + * the device out of standby. When the operation has finished, the power + * constraint is released. + * The following statements are valid: + * - After UART_open(): the device is still allowed to enter standby. + * - During UART_read(): the device cannot enter standby. + * - After an RX error (overrun, break, parity, framing): device is allowed to enter standby. + * - After a successful UART_read(): + * The device is allowed to enter standby, but RX remains on. + * - _Note_: Device might enter standby while a byte is being + * received if UART_read() is not called again after a successful + * read. This could result in corrupt data being received. + * - _Note_: Application thread should typically either issue another read after + * UART_read() completes successfully, or call + * UART_readCancel() to disable RX and thus assuring that no data + * is received while entering standby. + * - After UART_read() times out in ::UART_MODE_BLOCKING: + * The device is allowed to enter standby, but RX remains on. + * - _Note_: Device might enter standby while a byte is being + * received if UART_read() is not called again after a timeout. + * This could result in corrupt data being received. + * - _Note_: Application thread should typically either issue another read after + * UART_read() times out to continue reception. + * . + * - During UART_write(): the device cannot enter standby. + * - After UART_write() succeeds: the device can enter standby. + * - If UART_writeCancel() is called: the device can enter standby. + * - After write timeout: the device can enter standby. + * + * # Flow Control # + * To enable Flow Control, the RTS and CTS pins must be assigned in the + * ::UARTCC26XX_HWAttrsV2: + * @code + * const UARTCC26XX_HWAttrsV2 uartCC26xxHWAttrs[] = { + * { + * .baseAddr = UART0_BASE, + * .powerMngrId = PERIPH_UART0, + * .intNum = INT_UART0, + * .intPriority = ~0, + * .swiPriority = 0, + * .txPin = Board_UART_TX, + * .rxPin = Board_UART_RX, + * .ctsPin = Board_UART_CTS, + * .rtsPin = Board_UART_RTS + * .ringBufPtr = uartCC26XXRingBuffer[0], + * .ringBufSize = sizeof(uartCC26XXRingBuffer[0]), + * .txIntFifoThr= UARTCC26XX_FIFO_THRESHOLD_1_8, + * .rxIntFifoThr= UARTCC26XX_FIFO_THRESHOLD_4_8 + * } + * }; + * @endcode + * + * If the RTS and CTS pins are set to ::PIN_UNASSIGNED, the flow control is + * disabled. An example is shown in the ::UARTCC26XX_HWAttrsV2 description. + * + * # Supported Functions # + * | Generic API function | API function | Description | + * |----------------------|--------------------------|------------------------ + * | UART_init() | UARTCC26XX_init() | Initialize UART driver | + * | UART_open() | UARTCC26XX_open() | Initialize UART HW and set system dependencies | + * | UART_close() | UARTCC26XX_close() | Disable UART HW and release system dependencies | + * | UART_control() | UARTCC26XX_control() | Configure an already opened UART handle | + * | UART_read() | UARTCC26XX_read() | Start read from UART | + * | UART_readCancel() | UARTCC26XX_readCancel() | Cancel ongoing read from UART | + * | UART_write() | UARTCC26XX_write() | Start write to UART | + * | UART_writeCancel() | UARTCC26XX_writeCancel() | Cancel ongoing write to UART | + * + * @note All calls should go through the generic API + * + * # Not Supported Functionality # + * The CC26XX UART driver currently does not support: + * - ::UART_ECHO_ON + * - ::UART_DATA_TEXT + * - UART_readPolling() + * - UART_writePolling() + * + * # Use Cases @anchor USE_CASES # + * ## Basic Receive # + * Receive 100 bytes over UART in ::UART_MODE_BLOCKING. + * @code + * UART_Handle handle; + * UART_Params params; + * uint8_t rxBuf[100]; // Receive buffer + * uint32_t timeoutUs = 5000; // 5ms timeout, default timeout is no timeout (BIOS_WAIT_FOREVER) + * + * // Init UART and specify non-default parameters + * UART_Params_init(¶ms); + * params.baudRate = 9600; + * params.writeDataMode = UART_DATA_BINARY; + * params.readTimeout = timeoutUs / ClockP_tickPeriod; // Default tick period is 10us + * + * // Open the UART and do the read + * handle = UART_open(Board_UART, ¶ms); + * int rxBytes = UART_read(handle, rxBuf, 100); + * @endcode + * + * ## Receive with Return Partial # + * This use case will read in ::UART_MODE_BLOCKING until the wanted amount of bytes is + * received or until a started reception is inactive for a 32-bit period. + * This UART_read() call can also be used when unknown amount of bytes shall + * be read. Note: The partial return is also possible in ::UART_MODE_CALLBACK mode. + * @code + * UART_Handle handle; + * UART_Params params; + * uint8_t rxBuf[100]; // Receive buffer + * + * // Init UART and specify non-default parameters + * UART_Params_init(¶ms); + * params.baudRate = 9600; + * params.writeDataMode = UART_DATA_BINARY; + * + * // Open the UART and initiate the partial read + * handle = UART_open(Board_UART, ¶ms); + * // Enable RETURN_PARTIAL + * UART_control(handle, UARTCC26XX_CMD_RETURN_PARTIAL_ENABLE, NULL); + * // Begin read + * int rxBytes = UART_read(handle, rxBuf, 100)); + * @endcode + * + * ## Basic Transmit # + * This case will configure the UART to send the data in txBuf in + * BLOCKING_MODE. + * @code + * UART_Handle handle; + * UART_Params params; + * uint8_t txBuf[] = "Hello World"; // Transmit buffer + * + * // Init UART and specify non-default parameters + * UART_Params_init(¶ms); + * params.baudRate = 9600; + * params.writeDataMode = UART_DATA_BINARY; + * + * // Open the UART and do the write + * handle = UART_open(Board_UART, ¶ms); + * UART_write(handle, txBuf, sizeof(txBuf)); + * @endcode + * + * ## Receive Continously in ::UART_MODE_CALLBACK @anchor USE_CASE_CB # + * This case will configure the UART to receive and transmit continously in + * ::UART_MODE_CALLBACK, 16 bytes at the time and transmit them back via UART TX. + * Note that UART_Params.readTimeout is not in use when using ::UART_MODE_CALLBACK mode. + * @code + * #define MAX_NUM_RX_BYTES 1000 // Maximum RX bytes to receive in one go + * #define MAX_NUM_TX_BYTES 1000 // Maximum TX bytes to send in one go + * + * uint32_t wantedRxBytes; // Number of bytes received so far + * uint8_t rxBuf[MAX_NUM_RX_BYTES]; // Receive buffer + * uint8_t txBuf[MAX_NUM_TX_BYTES]; // Transmit buffer + * + * // Read callback function + * static void readCallback(UART_Handle handle, void *rxBuf, size_t size) + * { + * // Make sure we received all expected bytes + * if (size == wantedRxBytes) { + * // Copy bytes from RX buffer to TX buffer + * for(size_t i = 0; i < size; i++) + * txBuf[i] = ((uint8_t*)rxBuf)[i]; + * + * // Echo the bytes received back to transmitter + * UART_write(handle, txBuf, size); + * + * // Start another read, with size the same as it was during first call to + * // UART_read() + * UART_read(handle, rxBuf, wantedRxBytes); + * } + * else { + * // Handle error or call to UART_readCancel() + * } + * } + * + * // Write callback function + * static void writeCallback(UART_Handle handle, void *rxBuf, size_t size) + * { + * // Do nothing + * } + * + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * UART_Handle handle; + * UART_Params params; + * + * // Init UART + * UART_init(); + * + * // Specify non-default parameters + * UART_Params_init(¶ms); + * params.baudRate = 9600; + * params.writeMode = UART_MODE_CALLBACK; + * params.writeDataMode = UART_DATA_BINARY; + * params.writeCallback = writeCallback; + * params.readMode = UART_MODE_CALLBACK; + * params.readDataMode = UART_DATA_BINARY; + * params.readCallback = readCallback; + * + * // Open the UART and initiate the first read + * handle = UART_open(Board_UART, ¶ms); + * wantedRxBytes = 16; + * int rxBytes = UART_read(handle, rxBuf, wantedRxBytes); + * + * while(true); // Wait forever + * } + * @endcode + * + * # Baud Rate # + * The CC26xx driver supports baud rates up to 3Mbaud. + * However, when receiving more than 32 bytes back-to-back the baud + * rate is limited to approximately 2Mbaud. + * The throughput is also dependent on the user application. + * + * # Stack requirements # + * There are no additional stack requirements for calling UART_read() within + * its own callback. + * + * # Instrumentation # + * The UART driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic UART operations performed | + * Diags_USER2 | detailed UART operations performed | + * + * ============================================================================ + */ + +#ifndef ti_drivers_uart_UARTCC26XX__include +#define ti_drivers_uart_UARTCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/uart.h) + +#include +#include +#include +#include + +/** + * @addtogroup UART_STATUS + * UARTCC26XX_STATUS_* macros are command codes only defined in the + * UARTCC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add UARTCC26XX_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup UART_CMD + * UARTCC26XX_CMD_* macros are command codes only defined in the UARTCC26XX.h + * driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/*! + * @brief Command used by UART_control to enable partial return + * + * Enabling this command allows UART_read to return partial data if data + * reception is inactive for a given 32-bit period. With this command @b arg + * is @a don't @a care and it returns UART_STATUS_SUCCESS. + */ +#define UARTCC26XX_CMD_RETURN_PARTIAL_ENABLE (UART_CMD_RESERVED + 0) + +/*! + * @brief Command used by UART_control to disable partial return + * + * Disabling this command returns the UARTCC26XX to the default blocking + * behavior where UART_read blocks until all data bytes were received. With + * this comand @b arg is @a don't @a care and it returns UART_STATUS_SUCCESS. + */ +#define UARTCC26XX_CMD_RETURN_PARTIAL_DISABLE (UART_CMD_RESERVED + 1) + +/*! + * @brief Command used by UART_control to flush the RX FIFO + * + * This control command flushes any contents in the RX FIFO. With this command + * @b arg is @a don't @a care and it returns UART_STATUS_SUCCESS. + */ +#define UARTCC26XX_CMD_RX_FIFO_FLUSH (UART_CMD_RESERVED + 2) +/** @}*/ + +/*! Size of the TX and RX FIFOs is 32 items */ +#define UARTCC26XX_FIFO_SIZE 32 + +/*! + * @brief UART TX/RX interrupt FIFO threshold select + * + * Defined FIFO thresholds for generation of both TX interrupt and RX interrupt. + * The default value (UARTCC26XX_FIFO_THRESHOLD_DEFAULT) is defined for backward compatibility handling. + */ +typedef enum UARTCC26XX_FifoThreshold { + UARTCC26XX_FIFO_THRESHOLD_DEFAULT = 0, /*!< Default value forces FIFO + threshold of 1/8 for TX + interrupt and 4/8 for RX + interrupt */ + UARTCC26XX_FIFO_THRESHOLD_1_8, /*!< FIFO threshold of 1/8 full */ + UARTCC26XX_FIFO_THRESHOLD_2_8, /*!< FIFO threshold of 2/8 full */ + UARTCC26XX_FIFO_THRESHOLD_4_8, /*!< FIFO threshold of 4/8 full */ + UARTCC26XX_FIFO_THRESHOLD_6_8, /*!< FIFO threshold of 6/8 full */ + UARTCC26XX_FIFO_THRESHOLD_7_8 /*!< FIFO threshold of 7/8 full */ +} UARTCC26XX_FifoThreshold; + +/* BACKWARDS COMPATIBILITY */ +#define UARTCC26XX_RETURN_PARTIAL_ENABLE UARTCC26XX_CMD_RETURN_PARTIAL_ENABLE +#define UARTCC26XX_RETURN_PARTIAL_DISABLE UARTCC26XX_CMD_RETURN_PARTIAL_DISABLE +/* END BACKWARDS COMPATIBILITY */ + +/*! + * @brief The definition of an optional callback function used by the + * UART driver to notify the application when a receive error + * (FIFO overrun, parity error, etc) occurs. + * + * @param UART_Handle UART_Handle + * + * @param error The current value of the receive + * status register. + */ +typedef void (*UARTCC26XX_ErrorCallback) (UART_Handle handle, uint32_t error); + +/* UART function table pointer */ +extern const UART_FxnTable UARTCC26XX_fxnTable; + +/*! + * @brief UARTCC26XX Hardware attributes + * + * These fields, with the exception of intPriority, txIntFifoThr and + * rxIntFifoThr, are used by driverlib APIs and therefore must be populated + * by driverlib macro definitions. + * For CC26xxWare these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * intPriority is the UART peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * + * A sample structure is shown below: + * @code + * const UARTCC26XX_HWAttrsV2 uartCC26xxHWAttrs[] = { + * { + * .baseAddr = UART0_BASE, + * .powerMngrId = PERIPH_UART0, + * .intNum = INT_UART0, + * .intPriority = ~0, + * .swiPriority = 0, + * .txPin = Board_UART_TX, + * .rxPin = Board_UART_RX, + * .ctsPin = PIN_UNASSIGNED, + * .rtsPin = PIN_UNASSIGNED, + * .ringBufPtr = uartCC26XXRingBuffer[0], + * .ringBufSize = sizeof(uartCC26XXRingBuffer[0]), + * .txIntFifoThr= UARTCC26XX_FIFO_THRESHOLD_1_8, + * .rxIntFifoThr= UARTCC26XX_FIFO_THRESHOLD_4_8 + * } + * }; + * @endcode + * + * The .ctsPin and .rtsPin must be assigned to enable flow control. + */ +typedef struct UARTCC26XX_HWAttrsV2 { + uint32_t baseAddr; /*!< UART Peripheral's base address */ + uint32_t powerMngrId; /*!< UART Peripheral's power manager ID */ + int intNum; /*!< UART Peripheral's interrupt vector */ + /*! @brief UART Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief SPI SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + uint8_t txPin; /*!< UART TX pin */ + uint8_t rxPin; /*!< UART RX pin */ + uint8_t ctsPin; /*!< UART CTS pin */ + uint8_t rtsPin; /*!< UART RTS pin */ + unsigned char *ringBufPtr; /*!< Pointer to an application ring buffer */ + size_t ringBufSize; /*!< Size of ringBufPtr */ + UARTCC26XX_FifoThreshold txIntFifoThr; /*!< UART TX interrupt FIFO threshold select */ + UARTCC26XX_FifoThreshold rxIntFifoThr; /*!< UART RX interrupt FIFO threshold select */ + /*! Application error function to be called on receive errors */ + UARTCC26XX_ErrorCallback errorFxn; +} UARTCC26XX_HWAttrsV2; + +/*! + * @brief UART status + * + * The UART Status is used to flag the different Receive Errors. + */ +typedef enum UART_Status { + UART_TIMED_OUT = 0x10, /*!< UART timed out */ + UART_PARITY_ERROR = UART_RXERROR_PARITY, /*!< UART Parity error */ + UART_BRAKE_ERROR = UART_RXERROR_BREAK, /*!< UART Break error */ + UART_OVERRUN_ERROR = UART_RXERROR_OVERRUN, /*!< UART overrun error */ + UART_FRAMING_ERROR = UART_RXERROR_FRAMING, /*!< UART Framing error */ + UART_OK = 0x0 /*!< UART OK */ +} UART_Status; + +/*! + * @brief UARTCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct UARTCC26XX_Object { + /* UART control variables */ + bool opened; /*!< Has the obj been opened */ + UART_Mode readMode; /*!< Mode for all read calls */ + UART_Mode writeMode; /*!< Mode for all write calls */ + unsigned int readTimeout; /*!< Timeout for read semaphore in BLOCKING mode*/ + unsigned int writeTimeout; /*!< Timeout for write semaphore in BLOCKING mode*/ + UART_Callback readCallback; /*!< Pointer to read callback */ + UART_Callback writeCallback; /*!< Pointer to write callback */ + UART_ReturnMode readReturnMode; /*!< Receive return mode */ + UART_DataMode readDataMode; /*!< Type of data being read */ + UART_DataMode writeDataMode; /*!< Type of data being written */ + /*! @brief Baud rate for CC26xx UART + * + * The CC26xx driver supports baud rates up to 3Mbaud. + * However, when receiving more than 32 bytes back-to-back the baud + * rate is limited to approx. 2Mbaud. + * The throughput is also dependent on the user application. + */ + uint32_t baudRate; + UART_LEN dataLength; /*!< Data length for UART */ + UART_STOP stopBits; /*!< Stop bits for UART */ + UART_PAR parityType; /*!< Parity bit type for UART */ + UART_Status status; /*!< Status variable */ + + /* UART write variables */ + const void *writeBuf; /*!< Buffer data pointer */ + size_t writeCount; /*!< Number of Chars sent */ + size_t writeSize; /*!< Chars remaining in buffer */ + bool writeCR; /*!< Write a return character */ + + /* UART receive variables */ + bool readRetPartial; /*!< Return partial RX data if timeout occurs */ + void *readBuf; /*!< Buffer data pointer */ + size_t readCount; /*!< Number of Chars read */ + size_t readSize; /*!< Chars remaining in buffer */ + RingBuf_Object ringBuffer; /*!< local circular buffer object */ + + /* PIN driver state object and handle */ + PIN_State pinState; + PIN_Handle hPin; + + /*! UART post-notification function pointer */ + void *uartPostFxn; + /*! UART post-notification object */ + Power_NotifyObj uartPostObj; + + /* UART SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object */ + SwiP_Struct swi; /*!< Swi object */ + SemaphoreP_Struct writeSem; /*!< UART write semaphore*/ + SemaphoreP_Struct readSem; /*!< UART read semaphore */ + ClockP_Struct txFifoEmptyClk; /*!< UART TX FIFO empty clock */ + + bool uartRxPowerConstraint; + bool uartTxPowerConstraint; +} UARTCC26XX_Object, *UARTCC26XX_Handle; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_uart_UARTCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/List.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/List.c new file mode 100644 index 0000000..970ae16 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/List.c @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2015, 2017 Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== List.c ======== + */ +#include +#include + +#include +#include +#include + +/* + * ======== List_clearList ======== + */ +void List_clearList(List_List *list) +{ + uintptr_t key; + + key = HwiP_disable(); + + list->head = list->tail = NULL; + + HwiP_restore(key); +} + + + +/* + * ======== List_get ======== + */ +List_Elem *List_get(List_List *list) +{ + List_Elem *elem; + uintptr_t key; + + key = HwiP_disable(); + + elem = list->head; + + /* See if the List was empty */ + if (elem != NULL) { + list->head = elem->next; + if (elem->next != NULL) { + elem->next->prev = NULL; + } + else { + list->tail = NULL; + } + } + + HwiP_restore(key); + + return (elem); +} + + +/* + * ======== List_insert ======== + */ +void List_insert(List_List *list, List_Elem *newElem, List_Elem *curElem) +{ + uintptr_t key; + + key = HwiP_disable(); + + newElem->next = curElem; + newElem->prev = curElem->prev; + if (curElem->prev != NULL) { + curElem->prev->next = newElem; + } + else { + list->head = newElem; + } + curElem->prev = newElem; + + HwiP_restore(key); +} + + +/* + * ======== List_put ======== + */ +void List_put(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->next = NULL; + elem->prev = list->tail; + if (list->tail != NULL) { + list->tail->next = elem; + } + else { + list->head = elem; + } + + list->tail = elem; + + HwiP_restore(key); +} + +/* + * ======== List_putHead ======== + */ +void List_putHead(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->next = list->head; + elem->prev = NULL; + if (list->head != NULL) { + list->head->prev = elem; + } + else { + list->tail = elem; + } + + list->head = elem; + + HwiP_restore(key); +} + +/* + * ======== List_remove ======== + */ +void List_remove(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + /* Handle the case where the elem to remove is the last one */ + if (elem->next == NULL) { + list->tail = elem->prev; + } + else { + elem->next->prev = elem->prev; + } + + /* Handle the case where the elem to remove is the first one */ + if (elem->prev == NULL) { + list->head = elem->next; + } + else { + elem->prev->next = elem->next; + } + + HwiP_restore(key); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/List.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/List.h new file mode 100644 index 0000000..db99729 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/List.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2015-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file List.h + * + * @brief Linked List interface for use in drivers + * + * This module provides simple doubly-link list implementation. There are two + * main structures: + * - ::List_List: The structure that holds the start of a linked list. There + * is no API to create one. It is up to the driver to provide the structure + * itself. + * - ::List_Elem: The structure that must be in the structure that is placed + * onto a linked list. Generally it is the first field in the structure. For + * example: + * @code + * typedef struct MyStruct { + * List_Elem elem; + * void *buffer; + * } MyStruct; + * @endcode + * + * The following shows how to create a linked list with three elements. + * + * @code + * + denotes null-terminated + * _______ _______ _______ _______ + * |_______|----->|_______|----->|_______|--->|_______|--//---, + * ,----|_______| ,-|_______|<-----|_______|<---|_______|<-//-, + + * | List + elem elem elem | + * |_____________________________________________________________| + * @endcode + * + * The APIs ::List_get, ::List_put, and ::List_putHead are + * atomic. The other APIs are not necessarily atomic. In other words, when + * traversing a linked list, it is up to the application to provide + * thread-safety (e.g. HwiP_disable/restore or MutexP_pend/post). + * + * Initializing and adding an element to the tail and removing it + * @code + * typedef struct MyStruct { + * List_Elem elem; + * void *buffer; + * } MyStruct; + * + * List_List list; + * MyStruct foo; + * MyStruct *bar; + * + * List_clearList(&list); + * List_put(&list, (List_Elem *)&foo); + * bar = (MyStruct *)List_get(&list); + * @endcode + * + * The ::List_put and ::List_get APIs are used to maintain a first-in first-out + * (FIFO) linked list. + * + * The ::List_putHead and ::List_get APIs are used to maintain a last-in first-out + * (LIFO) linked list. + * + * Traversing a list from head to tail. Note: thread-safety calls are + * not shown here. + * @code + * List_List list; + * List_Elem *temp; + * + * for (temp = List_head(&list); temp != NULL; temp = List_next(temp)) { + * printf("address = 0x%x\n", temp); + * } + * @endcode + * + * Traversing a list from tail to head. Note: thread-safety calls are + * not shown here. + * @code + * List_List list; + * List_Elem *temp; + * + * for (temp = List_tail(&list); temp != NULL; temp = List_prev(temp)) { + * printf("address = 0x%x\n", temp); + * } + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_utils_List__include +#define ti_drivers_utils_List__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +typedef struct List_Elem { + struct List_Elem *next; + struct List_Elem *prev; +} List_Elem; + +typedef struct List_List { + List_Elem *head; + List_Elem *tail; +} List_List; + +/*! + * @brief Function to initialize the contents of a List_List + * + * @param list Pointer to a List_List structure that will be used to + * maintain a linked list + */ +extern void List_clearList(List_List *list); + +/*! + * @brief Function to test whether a linked list is empty + * + * @param list A pointer to a linked list + * + * @return true if empty, false if not empty + */ +static inline bool List_empty(List_List *list) +{ + return (list->head == NULL); +} + +/*! + * @brief Function to atomically get the first elem in a linked list + * + * @param list A pointer to a linked list + * + * @return Pointer the first elem in the linked list or NULL if empty + */ +extern List_Elem *List_get(List_List *list); + +/*! + * @brief Function to return the head of a linked list + * + * This function does not remove the head, it simply returns a pointer to + * it. This function is typically used when traversing a linked list. + * + * @param list A pointer to the linked list + * + * @return Pointer to the first elem in the linked list or NULL if empty + */ +static inline List_Elem *List_head(List_List *list) +{ + return (list->head); +} + +/*! + * @brief Function to insert an elem into a linked list + * + * @param list A pointer to the linked list + * + * @param newElem New elem to insert + * + * @param curElem Elem to insert the newElem in front of. + * This value cannot be NULL. + */ +extern void List_insert(List_List *list, List_Elem *newElem, + List_Elem *curElem); + +/*! + * @brief Function to return the next elem in a linked list + * + * This function does not remove the elem, it simply returns a pointer to + * next one. This function is typically used when traversing a linked list. + * + * @param elem Elem in the list + * + * @return Pointer to the next elem in linked list or NULL if at the end + */ +static inline List_Elem *List_next(List_Elem *elem) +{ + return (elem->next); +} + +/*! + * @brief Function to return the prev elem in a linked list + * + * This function does not remove the elem, it simply returns a pointer to + * prev one. This function is typically used when traversing a linked list. + * + * @param elem Elem in the list + * + * @return Pointer to the prev elem in linked list or NULL if at the beginning + */ +static inline List_Elem *List_prev(List_Elem *elem) +{ + return (elem->prev); +} + +/*! + * @brief Function to atomically put an elem onto the end of a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to place onto the end of the linked list + */ +extern void List_put(List_List *list, List_Elem *elem); + +/*! + * @brief Function to atomically put an elem onto the head of a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to place onto the beginning of the linked list + */ +extern void List_putHead(List_List *list, List_Elem *elem); + +/*! + * @brief Function to remove an elem from a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to be removed from a linked list + */ +extern void List_remove(List_List *list, List_Elem *elem); + +/*! + * @brief Function to return the tail of a linked list + * + * This function does not remove the tail, it simply returns a pointer to + * it. This function is typically used when traversing a linked list. + * + * @param list A pointer to the linked list + * + * @return Pointer to the last elem in the linked list or NULL if empty + */ +static inline List_Elem *List_tail(List_List *list) +{ + return (list->tail); +} + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_utils_List__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/Random.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/Random.c new file mode 100644 index 0000000..fb6b126 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/Random.c @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2018-2019 Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== Random.c ======== + */ + +#include +#include + +#include +#include +#include +#include + +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) + + #include + #include + #include + +#elif (DeviceFamily_ID == DeviceFamily_ID_MSP432E401Y || \ + DeviceFamily_ID == DeviceFamily_ID_MSP432E411Y) + + #include DeviceFamily_constructPath(driverlib/inc/hw_sysctl.h) + #include DeviceFamily_constructPath(driverlib/types.h) + +#endif + +#define STATE_SIZE_IN_WORDS 5 + +static uint32_t state[STATE_SIZE_IN_WORDS]; + +/* + * ======== Random_seedAutomatic ======== + */ +int_fast16_t Random_seedAutomatic(void) { + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) + + TRNGCC26XX_Object object = {0}; + TRNG_Params params; + CryptoKey seedKey; + int_fast16_t status; + + /* Use minimum TRNGCC26XX_SAMPLES_PER_CYCLE_MIN since + * we do not need the full amount of entropy and only need + * to kickstart the PRNG. + */ + const TRNGCC26XX_HWAttrs hwAttrs = { + .samplesPerCycle = TRNGCC26XX_SAMPLES_PER_CYCLE_MIN + }; + + /* Allocate TRNG instance on the stack since we will not need it + * hereafter. This also helps avoid problems with hardcoded indexes. + */ + TRNG_Config config = { + .object = &object, + .hwAttrs = &hwAttrs + }; + + params.returnBehavior = TRNG_RETURN_BEHAVIOR_POLLING; + + TRNG_init(); + + TRNG_Handle handle = TRNGCC26XX_construct(&config, ¶ms); + + if (!handle) { + return Random_STATUS_ERROR; + } + + CryptoKeyPlaintext_initBlankKey(&seedKey, + (uint8_t *)state, + sizeof(state)); + + status = TRNG_generateEntropy(handle, &seedKey); + + TRNG_close(handle); + + if (status != TRNG_STATUS_SUCCESS) { + return Random_STATUS_ERROR; + } + + return Random_STATUS_SUCCESS; +#elif (DeviceFamily_ID == DeviceFamily_ID_MSP432E401Y || \ + DeviceFamily_ID == DeviceFamily_ID_MSP432E411Y) + + /* MSP432E4 has a 128-bit unique device ID that we can use */ + state[0] = HWREG(SYSCTL_UNIQUEID0); + state[1] = HWREG(SYSCTL_UNIQUEID1); + state[2] = HWREG(SYSCTL_UNIQUEID2); + state[3] = HWREG(SYSCTL_UNIQUEID3); + state[4] = 0x00000001; + + return Random_STATUS_SUCCESS; +#else + + /* If neither a TRNG nor a unique ID are available, use a constant */ + state[0] = 0x00000001; + state[1] = 0x00000002; + state[2] = 0x00000003; + state[3] = 0x00000004; + state[4] = 0x00000005; + + return Random_STATUS_SUCCESS; +#endif +} + +/* + * ======== Random_seedManual ======== + */ +void Random_seedManual(uint8_t seed[Random_SEED_LENGTH]) { + uintptr_t key; + + key = HwiP_disable(); + + memcpy(state, seed, sizeof(state)); + + HwiP_restore(key); +} + +/* + * ======== Random_getNumber ======== + */ +uint32_t Random_getNumber(void) { + uintptr_t key; + uint32_t s; + uint32_t v; + uint32_t result; + + key = HwiP_disable(); + + /* "xorwow" XOR shift PRNG from section 3.1 of Marsaglia's "Xorshift RNGs" paper */ + v = state[3]; + + v ^= v >> 2; + v ^= v << 1; + + state[3] = state[2]; + state[2] = state[1]; + state[1] = state[0]; + s = state[0]; + + v ^= s; + v ^= s << 4; + + state[0] = v; + + state[4] += 362437; + + result = v + state[4]; + + HwiP_restore(key); + + return result; +} + +/* + * ======== Random_getBytes ======== + */ +void Random_getBytes(void *buffer, size_t bufferSize) { + uint32_t i; + uint32_t randomNumber; + + for (i = 0; i < bufferSize / sizeof(uint32_t); i++){ + ((uint32_t *)buffer)[i] = Random_getNumber(); + } + + randomNumber = Random_getNumber(); + + memcpy((uint32_t *)buffer + bufferSize / sizeof(uint32_t), + &randomNumber, + bufferSize % sizeof(uint32_t)); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/Random.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/Random.h new file mode 100644 index 0000000..b7136be --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/Random.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * @file Random.h + * + * @brief Interface to generate pseudo-random numbers + * + * @warning The numbers generated by this module are not crpytographically-secure! + * Do not use this module to generate keying material or for other + * security-related purposes! + * + * This module generates non-cryptographically-secure random numbers in an + * easy to use and fast way. + * + * There is a single global state that must be initialised by calling + * Random_seedAutomatic() or Random_seedManual(). Afterwards, you can call + * Random_getNumber() or Random_getBytes() as desired. Both are thread-safe + * and protect the internal state. + * + * The pseudo-random number generator used is the "xorwow" algorithm specified in + * Marsaglia's "Xorshift RNGs" paper. It keeps 20 bytes of state that must be + * seeded and has a period of 2^160 - 2^32 before a sequence wraps. + * + * Generating a random number with this algorithm is quite fast. Random_getNumber() + * only requires 82 instructions which is 1.7us on a 48MHz Cortex M4. That includes + * disabling interrupts. + * + * @code + * + * int_fast16_t status; + * uint32_t randomNumber; + * + * status = Random_seedAutomatic(); + * + * if (status != Random_STATUS_SUCCESS) { + * while(1); + * } + * + * randomNumber = Random_getNumber(); + * + * @endcode + * + * + */ + +#ifndef ti_drivers_utils_Random__include +#define ti_drivers_utils_Random__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#define Random_STATUS_SUCCESS (0) +#define Random_STATUS_ERROR (-1) + +/*! @brief Length of the seed in bytes */ +#define Random_SEED_LENGTH (20) + +/** + * @brief Seed internal state automatically + * + * This function seeds or reseeds the internal state. + * The method for generating the seed is device dependent. + * + * If a TRNG is available, it will be used to generate the seed. + * + * If a TRNG is not available, information unique to the device running + * the code will be used. This may be a unique device identifier or other + * information such as a MAC address. + * Since the seed is constant per device for devices without a TRNG, the + * number sequence will restart after each call to Random_seedAutomatic(). + * This will usually occur after rebooting the device. + * + * If neither a TRNG nor a unique device identifier is available, + * a constant will be used. + * + * @return Returns a status code + * + * @sa Random_seedManual() + * + * @post Random_getNumber() + * + * @post Random_getBytes() + */ +extern int_fast16_t Random_seedAutomatic(void); + +/** + * @brief Set the internal state to a specified seed + * + * This function sets the internal state to the seed specified + * by the application. + * + * @param seed Seed to set the internal state to + * + * @sa Random_seedAutomatic() + * + * @post Random_getNumber() + * + * @post Random_getBytes() + */ +extern void Random_seedManual(uint8_t seed[Random_SEED_LENGTH]); + +/** + * @brief Returns a random number + * + * This function returns a random number and updates the + * internal state. + * + * @return Returns random number + * + * @pre Random_seedAutomatic() + * @pre Random_seedManual() + */ +extern uint32_t Random_getNumber(void); + +/** + * Returns a number of random bytes + * + * This is a convenience function that fills the specified + * array with random bytes by repeatedly calling Random_getNumber(). + * + * @param buffer Buffer to fill with random bytes + * + * @param bufferSize Size of buffer. Any value is permitted, including + * those that are not multiples of sizeof(uint32_t). + * + * @pre Random_seedAutomatic() + * @pre Random_seedManual() + */ +extern void Random_getBytes(void *buffer, size_t bufferSize); + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_utils_Random__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/RingBuf.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/RingBuf.c new file mode 100644 index 0000000..ace4f01 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/RingBuf.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + +/* + * ======== RingBuf_construct ======== + */ +void RingBuf_construct(RingBuf_Handle object, unsigned char *bufPtr, + size_t bufSize) +{ + object->buffer = bufPtr; + object->length = bufSize; + object->count = 0; + object->head = bufSize - 1; + object->tail = 0; + object->maxCount = 0; +} + +/* + * ======== RingBuf_get ======== + */ +int RingBuf_get(RingBuf_Handle object, unsigned char *data) +{ + unsigned int key; + + key = HwiP_disable(); + + if (!object->count) { + HwiP_restore(key); + return -1; + } + + *data = object->buffer[object->tail]; + object->tail = (object->tail + 1) % object->length; + object->count--; + + HwiP_restore(key); + + return (object->count); +} + +/* + * ======== RingBuf_getCount ======== + */ +int RingBuf_getCount(RingBuf_Handle object) +{ + return (object->count); +} + +/* + * ======== RingBuf_isFull ======== + */ +bool RingBuf_isFull(RingBuf_Handle object) +{ + return (object->count == object->length); +} + +/* + * ======== RingBuf_getMaxCount ======== + */ +int RingBuf_getMaxCount(RingBuf_Handle object) +{ + return (object->maxCount); +} + +/* + * ======== RingBuf_peek ======== + */ +int RingBuf_peek(RingBuf_Handle object, unsigned char *data) +{ + unsigned int key; + int retCount; + + key = HwiP_disable(); + + *data = object->buffer[object->tail]; + retCount = object->count; + + HwiP_restore(key); + + return (retCount); +} + +/* + * ======== RingBuf_put ======== + */ +int RingBuf_put(RingBuf_Handle object, unsigned char data) +{ + unsigned int key; + unsigned int next; + + key = HwiP_disable(); + + if (object->count != object->length) { + next = (object->head + 1) % object->length; + object->buffer[next] = data; + object->head = next; + object->count++; + object->maxCount = (object->count > object->maxCount) ? + object->count : + object->maxCount; + } + else { + + HwiP_restore(key); + return (-1); + } + + HwiP_restore(key); + + return (object->count); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/RingBuf.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/RingBuf.h new file mode 100644 index 0000000..29e8c82 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/RingBuf.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_uart_RingBuf__include +#define ti_drivers_uart_RingBuf__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +typedef struct RingBuf_Object { + unsigned char *buffer; + size_t length; + size_t count; + size_t head; + size_t tail; + size_t maxCount; +} RingBuf_Object, *RingBuf_Handle; + +/*! + * @brief Initialize circular buffer + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param bufPtr Pointer to data buffer to be used for the circular buffer. + * The buffer is NOT stored in RingBuf_Object. + * + * @param bufSize The size of bufPtr in number of unsigned chars. + */ +void RingBuf_construct(RingBuf_Handle object, unsigned char *bufPtr, + size_t bufSize); + +/*! + * @brief Get an unsigned char from the end of the circular buffer and remove + * it. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data Pointer to an unsigned char to be filled with the data from + * the front of the circular buffer. + * + * @return Number of unsigned chars on the buffer after taking it out + * of the circular buffer. If it returns -1, the circular + * buffer was already empty and data is invalid. + */ +int RingBuf_get(RingBuf_Handle object, unsigned char *data); + +/*! + * @brief Get the number of unsigned chars currently stored on the circular + * buffer. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @return Number of unsigned chars on the circular buffer. + */ +int RingBuf_getCount(RingBuf_Handle object); + +/*! + * @brief Function to determine if the circular buffer is full or not. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @return true if circular buffer is full, else false. + */ +bool RingBuf_isFull(RingBuf_Handle object); + +/*! + * @brief A high-water mark indicating the largest number of unsigned chars + * stored on the circular buffer since it was constructed. + * + * @return Get the largest number of unsigned chars that were at one + * point in the circular buffer. + */ +int RingBuf_getMaxCount(RingBuf_Handle object); + +/*! + * @brief Get an unsigned char from the end of the circular buffer without + * removing it. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data Pointer to an unsigned char to be filled with the data from + * the front of the circular buffer. This function does not + * remove the data from the circular buffer. Do not evaluate + * data if the count returned is equal to 0. + * + * @return Number of unsigned chars on the circular buffer. If the + * number != 0, then data will contain the unsigned char at the + * end of the circular buffer. + */ +int RingBuf_peek(RingBuf_Handle object, unsigned char *data); + +/*! + * @brief Put an unsigned char into the end of the circular buffer. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data unsigned char to be placed at the end of the circular + * buffer. + * + * @return Number of unsigned chars on the buffer after it was added, + * or -1 if it's already full. + */ +int RingBuf_put(RingBuf_Handle object, unsigned char data); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_uart_RingBuf__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/watchdog/WatchdogCC26XX.c b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/watchdog/WatchdogCC26XX.c new file mode 100644 index 0000000..1bf8e32 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/watchdog/WatchdogCC26XX.c @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(driverlib/watchdog.h) + +/* Function prototypes */ +void WatchdogCC26XX_clear(Watchdog_Handle handle); +void WatchdogCC26XX_close(Watchdog_Handle handle); +int_fast16_t WatchdogCC26XX_control(Watchdog_Handle handle, uint_fast16_t cmd, + void *arg); +void WatchdogCC26XX_init(Watchdog_Handle handle); +Watchdog_Handle WatchdogCC26XX_open(Watchdog_Handle handle, Watchdog_Params *params); +int_fast16_t WatchdogCC26XX_setReload(Watchdog_Handle handle, + uint32_t ticks); +uint32_t WatchdogCC26XX_convertMsToTicks(Watchdog_Handle handle, + uint32_t milliseconds); + +/* WatchdogCC26XX internal functions */ +static void WatchdogCC26XX_initHw(Watchdog_Handle handle); + +/* Watchdog function table for CC26XX implementation */ +const Watchdog_FxnTable WatchdogCC26XX_fxnTable = { + WatchdogCC26XX_clear, + WatchdogCC26XX_close, + WatchdogCC26XX_control, + WatchdogCC26XX_init, + WatchdogCC26XX_open, + WatchdogCC26XX_setReload, + WatchdogCC26XX_convertMsToTicks +}; + +/* Maximum allowable setReload value */ +#define MAX_RELOAD_VALUE 0xFFFFFFFF +#define WATCHDOG_DIV_RATIO 32 /* Watchdog division ratio */ +#define MS_RATIO 1000 /* millisecond to second ratio */ + +/* + * ======== WatchdogCC26XX_clear ======== + */ +void WatchdogCC26XX_clear(Watchdog_Handle handle) +{ + WatchdogIntClear(); +} + +/* + * ======== WatchdogCC26XX_close ======== + */ +void WatchdogCC26XX_close(Watchdog_Handle handle) +{ + /* + * Not supported for CC26XX - Once the INTEN bit of the WDTCTL + * register has been set, it can only be cleared by a hardware + * reset. + */ + DebugP_assert(false); +} + +/* + * ======== WatchdogCC26XX_control ======== + * @pre Function assumes that the handle is not NULL + */ +int_fast16_t WatchdogCC26XX_control(Watchdog_Handle handle, uint_fast16_t cmd, + void *arg) +{ + /* No implementation yet */ + return (Watchdog_STATUS_UNDEFINEDCMD); +} + +/* + * ======== Watchdog_init ======== + */ +void WatchdogCC26XX_init(Watchdog_Handle handle) +{ + WatchdogCC26XX_Object *object = handle->object; + + object->isOpen = false; +} + +/* + * ======== WatchdogCC26XX_open ======== + */ +Watchdog_Handle WatchdogCC26XX_open(Watchdog_Handle handle, Watchdog_Params *params) +{ + unsigned int key; + HwiP_Params hwiParams; + WatchdogCC26XX_Object *object; + + /* get the pointer to the object and hwAttrs */ + object = handle->object; + + /* disable preemption while checking if the WatchDog is open. */ + key = HwiP_disable(); + + /* Check if the Watchdog is open already with the HWAttrs */ + if (object->isOpen == true) { + HwiP_restore(key); + DebugP_log1("Watchdog: Handle %x already in use.", (uintptr_t)handle); + return (NULL); + } + + object->isOpen = true; + HwiP_restore(key); + + /* initialize the Watchdog object */ + object->debugStallMode = params->debugStallMode; + object->resetMode = params->resetMode; + + /* Construct Hwi object for Watchdog */ + HwiP_Params_init(&hwiParams); + hwiParams.arg = (uintptr_t)handle; + + /* setup callback function if defined */ + if (params->callbackFxn != NULL) { + HwiP_plug(INT_NMI_FAULT, (void *)params->callbackFxn); + } + + /* initialize the watchdog hardware */ + WatchdogCC26XX_initHw(handle); + + DebugP_log1("Watchdog: handle %x opened" ,(uintptr_t)handle); + + /* return handle of the Watchdog object */ + return (handle); +} + +/* + * ======== WatchdogCC26XX_setReload ======== + */ +int_fast16_t WatchdogCC26XX_setReload(Watchdog_Handle handle, uint32_t ticks) +{ + unsigned int key; + + /* disable preemption while unlocking WatchDog registers */ + key = HwiP_disable(); + + /* unlock the Watchdog configuration registers */ + WatchdogUnlock(); + + /* make sure the Watchdog is unlocked before continuing */ + while(WatchdogLockState() == WATCHDOG_LOCK_LOCKED) + { } + + /* update the reload value */ + WatchdogReloadSet(ticks); + + /* lock register access */ + WatchdogLock(); + + HwiP_restore(key); + + DebugP_log2("Watchdog: WDT with handle 0x%x has been set to " + "reload to 0x%x", (uintptr_t)handle, ticks); + + return (Watchdog_STATUS_SUCCESS); +} + +/* + * ======== WatchdogCC26XX_hwInit ======== + * This function initializes the Watchdog hardware module. + * + * @pre Function assumes that the Watchdog handle is pointing to a hardware + * module which has already been opened. + */ +static void WatchdogCC26XX_initHw(Watchdog_Handle handle) { + unsigned int key; + uint32_t tickValue; + WatchdogCC26XX_Object *object; + WatchdogCC26XX_HWAttrs const *hwAttrs; + + /* get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* convert milliseconds to watchdog timer ticks */ + tickValue = WatchdogCC26XX_convertMsToTicks(handle, hwAttrs->reloadValue); + + /* disable preemption while unlocking WatchDog registers */ + key = HwiP_disable(); + + /* unlock the Watchdog configuration registers */ + WatchdogUnlock(); + + /* make sure the Watchdog is unlocked before continuing */ + while(WatchdogLockState() == WATCHDOG_LOCK_LOCKED) + { } + + WatchdogReloadSet(tickValue); + + /* set reset mode */ + if (object->resetMode == Watchdog_RESET_ON) { + WatchdogResetEnable(); + } + else { + WatchdogResetDisable(); + } + + /* set debug stall mode */ + if (object->debugStallMode == Watchdog_DEBUG_STALL_ON) { + WatchdogStallEnable(); + } + else { + WatchdogStallDisable(); + } + + /* enable the Watchdog interrupt as a non-maskable interrupt */ + WatchdogIntTypeSet(WATCHDOG_INT_TYPE_NMI); + + /* enable the Watchdog */ + WatchdogEnable(); + + /* lock the Watchdog configuration registers */ + WatchdogLock(); + + HwiP_restore(key); +} + +/* + * ======== WatchdogCC26XX_convertMsToTicks ======== + * This function converts the input value from milliseconds to + * Watchdog clock ticks. + */ +uint32_t WatchdogCC26XX_convertMsToTicks(Watchdog_Handle handle, + uint32_t milliseconds) +{ + uint32_t tickValue; + uint32_t convertRatio; + uint32_t maxConvertMs; + ClockP_FreqHz freq; + + /* Determine milliseconds to clock ticks conversion ratio */ + /* Watchdog clock ticks/sec = CPU clock / WATCHDOG_DIV_RATIO */ + /* Watchdog clock ticks/ms = CPU clock / WATCHDOG_DIV_RATIO / 1000 */ + ClockP_getCpuFreq(&freq); + convertRatio = freq.lo / WATCHDOG_DIV_RATIO / MS_RATIO; + maxConvertMs = MAX_RELOAD_VALUE / convertRatio; + + /* convert milliseconds to watchdog timer ticks */ + /* check if value exceeds maximum */ + if (milliseconds > maxConvertMs) { + tickValue = 0; /* return zero to indicate overflow */ + } + else { + tickValue = (uint32_t)(milliseconds * convertRatio); + } + + return(tickValue); +} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/watchdog/WatchdogCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/watchdog/WatchdogCC26XX.h new file mode 100644 index 0000000..77e580d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/watchdog/WatchdogCC26XX.h @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file WatchdogCC26XX.h + * + * @brief Watchdog driver implementation for CC13XX/CC26XX + * + * # Driver include # + * The Watchdog header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref Watchdog.h for a complete description of APIs. + * + * # Overview # + * + * The general Watchdog API should be used in application code, i.e. + * #Watchdog_open() should be used instead of WatchdogCC26XX_open(). The board + * file will define the device specific config, and casting in the general API + * will ensure that the correct device specific functions are called. + * + * # General Behavior # + * This Watchdog driver implementation is designed to operate on a CC13XX/CC26XX + * device. Before using the Watchdog in CC13XX/CC26XX, the Watchdog driver is + * initialized by calling #Watchdog_init(). The Watchdog HW is configured by + * calling #Watchdog_open(). Once opened, the Watchdog will count down from + * the reload value specified in #WatchdogCC26XX_HWAttrs. If it times out, a + * non-maskable interrupt will be triggered, the Watchdog interrupt flag will + * be set, and a user-provided callback function will be called. If reset is + * enabled in the #Watchdog_Params and the Watchdog timer is allowed to time + * out again while the interrupt flag is still pending, a reset signal will be + * generated. To prevent a reset, #Watchdog_clear() must be called to clear the + * interrupt flag and to reload the timer. + * + * The Watchdog counts down at a rate of the device clock SCLK_HF (48 MHz) + * divided by a fixed-division ratio of 32, which equals to 1.5 MHz. The + * Watchdog rate will change if SCLK_HF deviates from 48 MHz. + * + * @note The Watchdog interrupt is configured as a non-maskable interrupt + * (NMI) and the user-defined callback function is called in the context of + * NMI. Because the Watchdog interrupt is non-maskable, it is not safe to call + * any BIOS APIs from the Watchdog callback function. + * + * The reload value from which the Watchdog timer counts down may be changed + * during runtime using #Watchdog_setReload(). This value should be specified + * in Watchdog clock ticks and should not exceed the maximum value of 32 bits, + * which corresponds to a timeout period of 2863.3 seconds at the Watchdog rate + * of 1.5 MHz. If the reload value is set to zero, the Watchdog interrupt is + * immediately generated. + * + * Since the device is not reset on the first Watchdog timeout, the maximum + * time lapse between the time when the device gets locked up and the time when + * it is reset can be up to two Watchdog timeout periods. + * + * Watchdog_close() is not supported by this driver implementation. Once + * started, the Watchdog timer can only be stopped by a hardware reset. + * + * No CC13XX/CC26XX specific command has been implemented. Any call to + * Watchdog_control() will receive the return code Watchdog_STATUS_UNDEFINEDCMD. + * + * By default the Watchdog driver has reset enabled. However, it may be + * disabled in the #Watchdog_Params which allows the Watchdog Timer to be used + * like another timer interrupt. This functionality is not supported by + * all platforms, refer to device specific documentation for details. + * + * # Power Management # + * Once started, the Watchdog will keep running in Active or Idle mode. When + * the device enters Standby mode, the Watchdog timer will stop counting down + * but the counter value will be preserved. When the device wakes up from + * Standby, the Watchdog timer will continue to count down from the previous + * counter value. + * + * This means that if a system goes into Standby 50% of the time and the + * Watchdog reload value is set to 1 second, the Watchdog timer will actually + * time out in 2 seconds. A system which is only in Active/Idle mode for 1% of + * the time, the Watchdog timer will time out in 100 seconds. However, if a bug + * locks up the application in Active mode, the Watchdog timer will time out in + * the configured time. + * + * + * # Supported Functions # + * | Generic API Function | API Function | Description | + * |------------------------------ |---------------------------------- |---------------------------------------------------| + * | #Watchdog_init() | WatchdogCC26XX_init() | Initialize Watchdog driver | + * | #Watchdog_open() | WatchdogCC26XX_open() | Initialize Watchdog HW and set system dependencies| + * | #Watchdog_clear() | WatchdogCC26XX_clear() | Clear Watchdog interrupt flag and reload counter | + * | #Watchdog_setReload() | WatchdogCC26XX_setReload() | Set Watchdog timer reload value in clock ticnks | + * | #Watchdog_convertMsToTicks() | WatchdogCC26XX_convertMsToTicks() | Converts milliseconds to clock ticks | + * + * @note All calls should go through the generic API. Please refer to @ref Watchdog.h for a + * complete description of the generic APIs. + * + * # Use Cases # + * ## Basic Watchdog # + * In this basic watchdog example, the application is expected to define a + * Watchdog callback function and start the Watchdog timer by calling #Watchdog_open(). + * If needed, #Watchdog_setReload() may be called to change the timeout period. + * If all monitored tasks are doing alright, #Watchdog_clear() should be called + * regularly to reload the counter so as to restart the timeout period and to + * avoid the Watchdog interrupt being triggered. If the #Watchdog_clear() is + * missed and the Watchdog timer is allowed to timeout, the user-defined + * callback function is called. In this function, the user may do whatever is + * appropriate for the application. + * Here are some suggestions: + * - do nothing so that the timer will timeout again and trigger the reset + * - immediately reset the device + * - do self-test to check the integrity of the application + * + * @note The Watchdog interrupt is configured as a non-maskable interrupt + * (NMI) and the user-defined callback function is called in NMI context. + * Therefore it is not safe to call any OS APIs from the Watchdog callback + * function. This includes any driver calls that rely on OS APIs. + * + * The following code example shows how to define the callback function and to + * start the Watchdog timer. + * @code + * void watchdogCallback(uintptr_t handle); + * + * ... + * + * Watchdog_Handle handle; + * Watchdog_Params params; + * uint32_t tickValue; + * + * Watchdog_Params_init(¶ms); + * params.callbackFxn = watchdogCallback; + * handle = Watchdog_open(Watchdog_configIndex, ¶ms); + * // set timeout period to 100 ms + * tickValue = Watchdog_convertMsToTicks(handle, 100); + * Watchdog_setReload(handle, tickValue); + * + * ... + * + * void watchdogCallback(uintptr_t handle) + * { + * // User-defined code here + * ... + * } + * + * @endcode + */ + +#ifndef ti_drivers_watchdog_WatchdogCC26XX__include +#define ti_drivers_watchdog_WatchdogCC26XX__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * @addtogroup Watchdog_STATUS + * WatchdogCC26XX_STATUS_* macros are command codes only defined in the + * WatchdogCC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add WatchdogCC26XX_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup Watchdog_CMD + * WatchdogCC26XX_CMD_* macros are command codes only defined in the + * WatchdogCC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add WatchdogCC26XX_CMD_* macros here */ + +/** @}*/ + +#include + +/*! @brief Watchdog function table for CC26XX */ +extern const Watchdog_FxnTable WatchdogCC26XX_fxnTable; + +/*! + * @brief Watchdog hardware attributes for CC26XX + */ +typedef struct WatchdogCC26XX_HWAttrs { + unsigned int baseAddr; /*!< Base adddress for Watchdog */ + unsigned long reloadValue; /*!< Reload value in milliseconds for Watchdog */ +} WatchdogCC26XX_HWAttrs; + +/*! + * @brief Watchdog Object for CC26XX + * + * Not to be accessed by the user. + */ +typedef struct WatchdogCC26XX_Object { + bool isOpen; /* Flag for open/close status */ + Watchdog_Callback callbackFxn; /* Pointer to callback. Not supported + on all targets. */ + Watchdog_ResetMode resetMode; /* Mode to enable resets. + Not supported on all targets. */ + Watchdog_DebugMode debugStallMode; /* Mode to stall Watchdog at breakpoints. + Not supported on all targets. */ + /* Watchdog SYS/BIOS objects */ + HwiP_Struct hwi; /* Hwi object */ +} WatchdogCC26XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_watchdog_WatchdogCC26XX__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/errno.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/errno.h new file mode 100644 index 0000000..74b2284 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/errno.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2017 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== errno.h ======== + */ + +#ifndef ti_posix_gcc_errno__include +#define ti_posix_gcc_errno__include + +/* compiler vendor check */ +#ifndef __GNUC__ +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#endif + +/* include toolchain's header file */ +#include <../include/errno.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* custom error codes */ +#define EFREERTOS 2001 /* FreeRTOS function failure */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_gcc_errno__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/mqueue.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/mqueue.h new file mode 100644 index 0000000..1591572 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/mqueue.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016-2017 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== mqueue.h ======== + */ + +#ifndef ti_posix_gcc_mqueue__include +#define ti_posix_gcc_mqueue__include + +/* compiler vendor check */ +#ifndef __GNUC__ +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#endif + +#include +#include + +#include "time.h" +#include "sys/types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Message queue descriptor */ +typedef void *mqd_t; + +/* + * ======== mq_attr ======== + */ +struct mq_attr { + long mq_flags; /* Message queue description flags: 0 or O_NONBLOCK. + Initialized from oflag argument of mq_open(). */ + long mq_maxmsg; /* Maximum number of messages on queue. */ + long mq_msgsize; /* Maximum message size. */ + long mq_curmsgs; /* Number of messages currently queued. */ +}; + +/* Deprecated. This typedef is for compatibility with old SDKs. It is + * not part of the POSIX standard. It will be removed in a future + * release. TIRTOS-1317 + */ +typedef struct mq_attr mq_attr; + +/* For mq_open() */ +#define O_CREAT 0x200 /* TODO: sys/fcntl.h? */ +#define O_EXCL 0x0800 /* Error on open if queue exists */ +#define O_RDONLY 0 +#define O_WRONLY 1 +#define O_RDWR 2 +#define O_NONBLOCK 0x4000 /* Fail with EAGAIN if resources unavailable */ + +typedef uint32_t mode_t; /* TODO: sys/stat.h? */ + +extern int mq_close(mqd_t mqdes); +extern int mq_getattr(mqd_t mqdes, struct mq_attr *mqstat); +extern mqd_t mq_open(const char *name, int oflags, ...); +extern ssize_t mq_receive(mqd_t mqdes, char *msg_ptr, size_t msg_len, + unsigned int *msg_prio); +extern int mq_send(mqd_t mqdes, const char *msg_ptr, size_t msg_len, + unsigned int msg_prio); +extern int mq_setattr(mqd_t mqdes, const struct mq_attr *mqstat, + struct mq_attr *omqstat); +extern ssize_t mq_timedreceive(mqd_t mqdes, char *msg_ptr, size_t msg_len, + unsigned int *msg_prio, const struct timespec *abstime); +extern int mq_timedsend(mqd_t mqdes, const char *msg_ptr, size_t msg_len, + unsigned int msg_prio, const struct timespec *abstime); +extern int mq_unlink(const char *name); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_gcc_mqueue__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/pthread.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/pthread.h new file mode 100644 index 0000000..1d8fd0f --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/pthread.h @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2015-2017 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== pthread.h ======== + */ + +#ifndef ti_posix_gcc_pthread__include +#define ti_posix_gcc_pthread__include + +/* compiler vendor check */ +#ifndef __GNUC__ +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#endif + +#include + +#include "sys/types.h" +#include "time.h" +#include "sched.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PTHREAD_BARRIER_SERIAL_THREAD -1 + +#define PTHREAD_CREATE_JOINABLE 0 +#define PTHREAD_CREATE_DETACHED 1 + +/* PThread cancellation */ +#define PTHREAD_CANCEL_ENABLE 0 +#define PTHREAD_CANCEL_DISABLE 1 +#define PTHREAD_CANCELED ((void *) -1) + +/* + * Mutex attributes - type + * + * PTHREAD_MUTEX_NORMAL: Owner of mutex cannot relock it. Attempting + * to relock will cause deadlock. + * PTHREAD_MUTEX_RECURSIVE: Owner can relock the mutex. + * PTHREAD_MUTEX_ERRORCHECK: If owner attempts to relock the mutex, an + * error is returned. + * + */ +#define PTHREAD_MUTEX_NORMAL 0 +#define PTHREAD_MUTEX_RECURSIVE 1 +#define PTHREAD_MUTEX_ERRORCHECK 2 +#define PTHREAD_MUTEX_DEFAULT PTHREAD_MUTEX_NORMAL + +/* Passed to pthread_once() */ +#define PTHREAD_ONCE_INIT 0 + +/* + * Mutex attributes - protocol + * + * PTHREAD_PRIO_NONE: Ownership of mutex does not affect priority. + * PTHREAD_PRIO_INHERIT: Owner's priority is boosted to the priority of + * highest priority thread blocked on the mutex. + * PTHREAD_PRIO_PROTECT: Mutex has a priority ceiling. The owner's + * priority is boosted to the highest priority ceiling of all mutexes + * owned (regardless of whether or not other threads are blocked on + * any of these mutexes). + */ +#define PTHREAD_PRIO_NONE 0 +#define PTHREAD_PRIO_INHERIT 1 +#define PTHREAD_PRIO_PROTECT 2 + +#define PTHREAD_PROCESS_PRIVATE 0 + +/* + ************************************************************************* + * pthread_attr + ************************************************************************* + */ +extern int pthread_attr_destroy(pthread_attr_t *attr); + +extern int pthread_attr_getdetachstate(const pthread_attr_t *attr, + int *detachstate); +extern int pthread_attr_getguardsize(const pthread_attr_t *attr, + size_t *guardsize); + +extern int pthread_attr_getschedparam(const pthread_attr_t *attr, + struct sched_param *schedparam); + +extern int pthread_attr_getstack(const pthread_attr_t *attr, + void **stackaddr, size_t *stacksize); +extern int pthread_attr_getstacksize(const pthread_attr_t *attr, + size_t *stacksize); + +extern int pthread_attr_init(pthread_attr_t *attr); + +extern int pthread_attr_setdetachstate(pthread_attr_t *attr, int detachedstate); +extern int pthread_attr_setguardsize(pthread_attr_t *attr, size_t guardsize); + +extern int pthread_attr_setschedparam(pthread_attr_t *attr, + const struct sched_param *schedparam); + +extern int pthread_attr_setstack(pthread_attr_t *attr, void *stackaddr, + size_t stacksize); +extern int pthread_attr_setstacksize(pthread_attr_t *attr, size_t stacksize); + +/* + ************************************************************************* + * pthread + ************************************************************************* + */ +extern int pthread_cancel(pthread_t pthread); +extern void _pthread_cleanup_pop(struct _pthread_cleanup_context *context, + int execute); +extern void _pthread_cleanup_push(struct _pthread_cleanup_context *context, + void (*fxn)(void *), void *arg); + +#define pthread_cleanup_push(fxn, arg) \ + do { \ + struct _pthread_cleanup_context _pthread_clup_ctx; \ + _pthread_cleanup_push(&_pthread_clup_ctx, (fxn), (arg)) + +#define pthread_cleanup_pop(execute) \ + _pthread_cleanup_pop(&_pthread_clup_ctx, (execute)); \ + } while (0) + +extern int pthread_create(pthread_t *newthread, const pthread_attr_t *attr, + void *(*startroutine)(void *), void *arg); +extern int pthread_detach(pthread_t pthread); +extern int pthread_equal(pthread_t pt1, pthread_t pt2); +extern void pthread_exit(void *ptr); +extern int pthread_getschedparam(pthread_t thread, int *policy, + struct sched_param *param); +extern int pthread_join(pthread_t th, void **thread_return); +extern int pthread_once(pthread_once_t *once, void (*initFxn)(void)); +extern pthread_t pthread_self(void); +extern int pthread_setcancelstate(int state, int *oldstate); +extern int pthread_setschedparam(pthread_t pthread, int policy, + const struct sched_param *param); + +/* + ************************************************************************* + * pthread_barrierattr + ************************************************************************* + */ +extern int pthread_barrierattr_destroy(pthread_barrierattr_t *attr); +extern int pthread_barrierattr_init(pthread_barrierattr_t *attr); + +/* + ************************************************************************* + * pthread_barrier + ************************************************************************* + */ +extern int pthread_barrier_destroy(pthread_barrier_t *barrier); +extern int pthread_barrier_init(pthread_barrier_t *barrier, + const pthread_barrierattr_t *attr, unsigned count); +extern int pthread_barrier_wait(pthread_barrier_t *barrier); + +/* + ************************************************************************* + * pthread_condattr + ************************************************************************* + */ +extern int pthread_condattr_destroy(pthread_condattr_t *attr); +extern int pthread_condattr_getclock(const pthread_condattr_t *attr, + clockid_t *clock_id); +extern int pthread_condattr_init(pthread_condattr_t * attr); +extern int pthread_condattr_setclock(pthread_condattr_t *attr, + clockid_t clock_id); + +/* + ************************************************************************* + * pthread_cond + ************************************************************************* + */ +extern int pthread_cond_broadcast(pthread_cond_t *cond); +extern int pthread_cond_destroy(pthread_cond_t *cond); +extern int pthread_cond_init(pthread_cond_t *cond, + const pthread_condattr_t *attr); +extern int pthread_cond_signal(pthread_cond_t *cond); +extern int pthread_cond_timedwait(pthread_cond_t *cond, pthread_mutex_t *mutex, + const struct timespec *abstime); +extern int pthread_cond_wait(pthread_cond_t *cond, pthread_mutex_t *mutex); + +/* + ************************************************************************* + * pthread_key + ************************************************************************* + */ +extern int pthread_key_create(pthread_key_t *key, void (*destructor)(void*)); +extern int pthread_key_delete(pthread_key_t key); +extern void *pthread_getspecific(pthread_key_t key); +extern int pthread_setspecific(pthread_key_t key, const void *value); + +/* + ************************************************************************* + * pthread_mutexattr + ************************************************************************* + */ +extern int pthread_mutexattr_destroy(pthread_mutexattr_t *attr); +extern int pthread_mutexattr_gettype(const pthread_mutexattr_t *attr, + int *type); +extern int pthread_mutexattr_getprioceiling(const pthread_mutexattr_t *attr, + int *prioceiling); +extern int pthread_mutexattr_getprotocol(const pthread_mutexattr_t *attr, + int *protocol); +extern int pthread_mutexattr_init(pthread_mutexattr_t *attr); +extern int pthread_mutexattr_setprioceiling(pthread_mutexattr_t *attr, + int prioceiling); +extern int pthread_mutexattr_setprotocol(pthread_mutexattr_t *attr, + int protocol); +extern int pthread_mutexattr_settype(pthread_mutexattr_t *attr, int type); + +/* + ************************************************************************* + * pthread_mutex + ************************************************************************* + */ +extern int pthread_mutex_destroy(pthread_mutex_t *mutex); +extern int pthread_mutex_getprioceiling(const pthread_mutex_t *mutex, + int *prioceiling); +extern int pthread_mutex_init(pthread_mutex_t *mutex, + const pthread_mutexattr_t *attr); +extern int pthread_mutex_lock(pthread_mutex_t *mutex); +extern int pthread_mutex_setprioceiling(pthread_mutex_t *mutex, + int prioceiling, int *oldceiling); +extern int pthread_mutex_timedlock(pthread_mutex_t *mutex, + const struct timespec *abstime); +extern int pthread_mutex_trylock(pthread_mutex_t *mutex); + +extern int pthread_mutex_unlock(pthread_mutex_t *mutex); + +/* + ************************************************************************* + * pthread_rwlockattr + ************************************************************************* + */ +extern int pthread_rwlockattr_destroy(pthread_rwlockattr_t *attr); +extern int pthread_rwlockattr_init(pthread_rwlockattr_t * attr); + +/* + ************************************************************************* + * pthread_rwlock + ************************************************************************* + */ +extern int pthread_rwlock_destroy(pthread_rwlock_t *rwlock); +extern int pthread_rwlock_init(pthread_rwlock_t *rwlock, + const pthread_rwlockattr_t *attr); + +extern int pthread_rwlock_rdlock(pthread_rwlock_t *rwlock); +extern int pthread_rwlock_timedrdlock(pthread_rwlock_t *rwlock, + const struct timespec *abstime); +extern int pthread_rwlock_timedwrlock(pthread_rwlock_t *rwlock, + const struct timespec *abstime); +extern int pthread_rwlock_tryrdlock(pthread_rwlock_t *rwlock); +extern int pthread_rwlock_trywrlock(pthread_rwlock_t *rwlock); +extern int pthread_rwlock_unlock(pthread_rwlock_t *rwlock); +extern int pthread_rwlock_wrlock(pthread_rwlock_t *rwlock); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_gcc_pthread__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sched.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sched.h new file mode 100644 index 0000000..185bc2d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sched.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016-2017 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== sched.h ======== + */ + +#ifndef ti_posix_gcc_sched__include +#define ti_posix_gcc_sched__include + +/* compiler vendor check */ +#ifndef __GNUC__ +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#endif + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * These defines would be in a sched.h, which TI and IAR + * toolchains don't have. + */ +#ifndef SCHED_FIFO +#define SCHED_FIFO 0 +#endif + +#ifndef SCHED_RR +#define SCHED_RR 0 +#endif + +#ifndef SCHED_OTHER +#define SCHED_OTHER 0 +#endif + +/* + * ======== sched_param ======== + * This was taken from sys/sched.h + */ +struct sched_param { + int sched_priority; /* Thread execution priority */ +}; + +/* + * GNU sched.h declares sched_get_priority_min(), + * sched_get_priority_max(), and sched_yield() inside an + * #if defined(_POSIX_PRIORITY_SCHEDULING) + * block. + */ +extern int sched_get_priority_min(int policy); +extern int sched_get_priority_max(int policy); + +extern int sched_yield(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_gcc_sched__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/semaphore.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/semaphore.h new file mode 100644 index 0000000..334b759 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/semaphore.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2015-2017 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== semaphore.h ======== + */ + +#ifndef ti_posix_gcc_semaphore__include +#define ti_posix_gcc_semaphore__include + +/* compiler vendor check */ +#ifndef __GNUC__ +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#endif + +#include +#include "sys/_internal.h" + +/* + * Include definitions of timespec and clockid_t that would + * be in sys/types.h. TI and IAR tool chains do not have a + * sys/types.h header file, while GNU toolchain does. For + * GNU, sys/types.h is included in time.h. + */ +#include "time.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef union { + struct sysbios_Semaphore sysbios; + struct freertos_Semaphore freertos; +} sem_t; + +int sem_destroy(sem_t *sem); +int sem_getvalue(sem_t *sem, int *value); +int sem_init(sem_t *sem, int pshared, unsigned value); +int sem_post(sem_t *sem); +int sem_timedwait(sem_t *sem, const struct timespec *abstime); +int sem_trywait(sem_t *sem); +int sem_wait(sem_t *sem); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_gcc_semaphore__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/signal.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/signal.h new file mode 100644 index 0000000..3656c67 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/signal.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2017 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== signal.h ======== + */ + +#ifndef ti_posix_gcc_signal__include +#define ti_posix_gcc_signal__include + +/* compiler vendor check */ +#ifndef __GNUC__ +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#endif + +#include "sys/types.h" + +/* include toolchain's header file */ +#include <../include/signal.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef SIGEV_NONE +#define SIGEV_NONE 1 +#endif + +#ifndef SIGEV_SIGNAL +#define SIGEV_SIGNAL 2 +#endif + +#ifndef SIGEV_THREAD +#define SIGEV_THREAD 3 +#endif + + +/* + ************************************************************************* + * signal types + ************************************************************************* + */ + +/* + * ======== sigval ======== + */ +union sigval { + int sival_int; /* integer signal value */ + void *sival_ptr; /* pointer signal value */ +}; + +/* Deprecated. This typedef is for compatibility with old SDKs. It is + * not part of the POSIX standard. It will be removed in a future + * release. TIRTOS-1317 + */ +typedef union sigval sigval; + +/* + * ======== sigevent ======== + */ +struct sigevent { + int sigev_notify; /* notification type */ + int sigev_signo; /* signal number */ + union sigval sigev_value; /* signal value */ + + void (*sigev_notify_function)(union sigval val); /* notify function */ + pthread_attr_t *sigev_notify_attributes; /* notify attributes */ +}; + +/* Deprecated. This typedef is for compatibility with old SDKs. It is + * not part of the POSIX standard. It will be removed in a future + * release. TIRTOS-1317 + */ +typedef struct sigevent sigevent; + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_gcc_signal__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/_internal.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/_internal.h new file mode 100644 index 0000000..15ef002 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/_internal.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2017-2018 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== sys/_internal.h ======== + * Vendor specific internal details + */ + +#ifndef ti_posix_gcc_sys__internal__include +#define ti_posix_gcc_sys__internal__include + +/* compiler vendor check */ +#ifndef __GNUC__ +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#endif + +#include /* C99 standard integer types */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* These opaque object types replicate the kernel internal object + * structures. They are used in a union when defining an opaque + * object in order to guarantee the opaque object is correctly sized + * and aligned with respect to the kernel objects. + */ +enum Opaque_Mode { + Opaque_Mode_1, + Opaque_Mode_2, + Opaque_Mode_3, + Opaque_Mode_4 +}; + +struct Opaque_Struct__; + +struct Opaque_QueueElem { + struct Opaque_QueueElem *volatile next; + struct Opaque_QueueElem *volatile prev; +}; + +struct Opaque_QueueStruct { + struct Opaque_QueueElem __f0; + struct Opaque_Struct__ *__f1; +}; + +struct sysbios_Semaphore { + struct Opaque_Struct__ *__f0; + unsigned int __f1; + enum Opaque_Mode __f2; + volatile uint_least16_t __f3; + struct Opaque_QueueStruct __f4; + struct Opaque_Struct__ *__f5; +}; + +struct freertos_Semaphore { + void *__f0; +}; + +struct sysbios_Barrier { + struct sysbios_Semaphore sem; + int count; + int pendCount; +}; + +struct freertos_Barrier { + int count; + int pendCount; + struct Opaque_Struct__ *waitList; + struct Opaque_Struct__ *last; +}; + +struct sysbios_Mutex { + struct Opaque_Struct__ *owner; + int lockCnt; + int type; + struct sysbios_Semaphore sem; + struct Opaque_Struct__ *mpo; +}; + +struct freertos_Mutex { + int protocol; + void *owner; + int type; + void *sem; /* struct freertos_Semaphore */ +}; + +struct sysbios_RWLock { + struct sysbios_Semaphore sem; + struct sysbios_Semaphore readSem; + int activeReaderCnt; + int blockedReaderCnt; + void *owner; +}; + +struct freertos_RWLock { + struct freertos_Semaphore sem; + struct freertos_Semaphore readSem; + int activeReaderCnt; + int blockedReaderCnt; + void *owner; +}; + +struct sysbios_Cond { + struct Opaque_QueueStruct waitList; + uint32_t clockId; +}; + +struct freertos_Cond { + struct Opaque_QueueElem waitList; + uint32_t clockId; +}; + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_gcc_sys__internal__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/types.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/types.h new file mode 100644 index 0000000..3f152d3 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/types.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2017-2018 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== sys/types.h ======== + */ + +#ifndef ti_posix_gcc_sys_types__include +#define ti_posix_gcc_sys_types__include + +/* compiler vendor check */ +#ifndef __GNUC__ +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#endif + +#include +#include +#include "_internal.h" + +/* include compiler sys/types.h */ +#include <../include/sys/types.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* In order to use POSIX types defined by TI-POSIX, instead of those + * defined by GCC, the user must define -std=c99 (or c++98), which will + * omit the GCC defines and avoid type collisions with TI-POSIX. This + * is new with GCC v7. In GCC v6, the compiler omitted the POSIX types + * by default. + * + * In addition, both _POSIX_SOURCE and _POSIX_C_SOURCE must be undefined. + * Previous versions of SDK examples were defining these macros. If you + * are migrating an old example, make sure to remove these macros. + * + * This check is to inform the user of these requirements. + */ +#if defined(_POSIX_SOURCE) || defined(_POSIX_C_SOURCE) +#ifdef __cplusplus +#error "When compiling with TI-POSIX, you must define -std=c++98 (or later). You must not define _POSIX_SOURCE or _POSIX_C_SOURCE." +#else +#error "When compiling with TI-POSIX, you must define -std=c99 (or later). You must not define _POSIX_SOURCE or _POSIX_C_SOURCE." +#endif +#endif + +/* + ************************************************************************* + * posix types + ************************************************************************* + */ + +/* + * ======== pthread_attr_t ======== + */ +typedef struct pthread_attr_t { + int priority; + void *stack; + size_t stacksize; + size_t guardsize; + int detachstate; +} pthread_attr_t; + +typedef uint32_t pthread_barrierattr_t; +typedef uint32_t pthread_condattr_t; + +typedef void *pthread_key_t; + +typedef struct pthread_mutexattr_t { + int type; + int protocol; + int prioceiling; +} pthread_mutexattr_t; + +typedef uint32_t pthread_rwlockattr_t; + +typedef void *pthread_t; + +typedef union { + struct sysbios_Barrier sysbios; + struct freertos_Barrier freertos; +} pthread_barrier_t; + +typedef union { + struct sysbios_Cond sysbios; + struct freertos_Cond freertos; +} pthread_cond_t; + +typedef union { + struct sysbios_Mutex sysbios; + struct freertos_Mutex freertos; +} pthread_mutex_t; + +typedef uint32_t pthread_once_t; + +typedef union { + struct sysbios_RWLock sysbios; + struct freertos_RWLock freertos; +} pthread_rwlock_t; + +struct _pthread_cleanup_context { + pthread_t thread; + void (*fxn)(void *); + void *arg; + int cancelType; + struct _pthread_cleanup_context *next; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_gcc_sys_types__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/time.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/time.h new file mode 100644 index 0000000..9b59982 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/time.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2017-2019 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== time.h ======== + */ + +#ifndef ti_posix_gcc_time__include +#define ti_posix_gcc_time__include + +/* compiler vendor check */ +#ifndef __GNUC__ +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#endif + +#include +#include + +/* include compiler time.h */ +#include <../include/time.h> + +#include "signal.h" +#include "sys/types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Timer support. + */ +/* + * CLOCK_REALTIME represents the realtime clock for the system. For this + * clock, clock_gettime() returns the time since the beginning of the + * Epoch. SYS/BIOS implements clock_gettime() and clock_settime() with + * the ti.sysbios.hal.Seconds module for CLOCK_REALTIME. + */ +#ifndef CLOCK_REALTIME +#define CLOCK_REALTIME (clockid_t)1 +#endif + +/* + * CLOCK_MONOTONIC represents a system clock that cannot be set via + * clock_settime(). For SYS/BIOS, CLOCK_MONOTONIC represents the + * ti.sysbios.knl.Clock system clock. + */ +#ifndef CLOCK_MONOTONIC +#define CLOCK_MONOTONIC (clockid_t)2 +#endif + +#ifndef TIMER_ABSTIME +#define TIMER_ABSTIME 4 +#endif + +/* + * For clockId = CLOCK_REALTIME, clock_gettime() and clock_settime() use + * the BIOS Seconds module to get/set the time. Before using clock_gettime() + * with clockId = CLOCK_REALTIME, the Seconds module must be initialized. + * This can be done by either calling clock_settime(CLOCK_REALTIME,...), + * or Seconds_set(). + * For clockId = CLOCK_MONOTONIC, clock_gettime() returns a time based on + * ti.sysbios.knl.Clock ticks. + */ +extern int clock_gettime(clockid_t clockId, struct timespec *ts); + +extern int clock_nanosleep(clockid_t clock_id, int flags, + const struct timespec *rqtp, struct timespec *rmtp); + +/* + * Only clockId = CLOCK_REALTIME is supported for clock_settime(). Only + * the value of ts->tv_sec is used is used in clock_settime(). + * Returns EINVAL if clockId = CLOCK_MONOTONIC. + */ +extern int clock_settime(clockid_t clockId, const struct timespec *ts); + +/* + * Create a timer based on the BIOS Clock module. To reduce code size, + * the clockId parameter is ignored. + */ +extern int timer_create(clockid_t clockId, struct sigevent *evp, + timer_t *timerid); +extern int timer_delete(timer_t timerid); +extern int timer_gettime(timer_t timerid, struct itimerspec *its); +extern int timer_settime(timer_t timerid, int flags, + const struct itimerspec *value, struct itimerspec *ovalue); + +extern int nanosleep(const struct timespec *rqtp, struct timespec *rmtp); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_gcc_time__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/unistd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/unistd.h new file mode 100644 index 0000000..90053f1 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/unistd.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2018 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== unistd.h ======== + */ + +#ifndef ti_posix_gcc_unistd__include +#define ti_posix_gcc_unistd__include + +/* compiler vendor check */ +#ifndef __GNUC__ +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#endif + +/* include compiler unistd.h */ +#include <../include/unistd.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* GCC v7 dropped support for this function */ +#if __GNUC__ >= 7 +extern int usleep(useconds_t useconds); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_gcc_unistd__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/errno.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/errno.h new file mode 100644 index 0000000..d40eadc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/errno.h @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2017-2018 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== errno.h ======== + */ + +#ifndef ti_posix_iar_errno__include +#define ti_posix_iar_errno__include + +/* compiler vendor check */ +#ifndef __IAR_SYSTEMS_ICC__ +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#endif + +/* include toolchain's header file */ +#if defined(__430_CORE__) || defined(__430X_CORE__) +#include <../inc/dlib/c/errno.h> +#else +#include <../inc/c/errno.h> +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* These are missing from errno.h Values match GNU ARM compiler. */ + +#ifndef EACCES +#define EACCES 13 +#endif + +#ifndef EAGAIN +#define EAGAIN 11 +#endif + +#ifndef EBADF +#define EBADF 9 +#endif + +#ifndef EBUSY +#define EBUSY 16 +#endif + +#ifndef EDEADLK +#define EDEADLK 45 +#endif + +#ifndef EEXIST +#define EEXIST 17 +#endif + +#ifndef EFAULT +#define EFAULT 14 +#endif + +#ifndef EINVAL +#define EINVAL 22 +#endif + +#ifndef EMSGSIZE +#define EMSGSIZE 122 +#endif + +#ifndef ENFILE +#define ENFILE 23 +#endif + +#ifndef ENOMEM +#define ENOMEM 12 +#endif + +#ifndef ENOENT +#define ENOENT 2 +#endif + +#ifndef ENOSPC +#define ENOSPC 28 +#endif + +#ifndef ENOSYS +#define ENOSYS 89 +#endif + +#ifndef ENOTSUP +#define ENOTSUP 48 +#endif + +#ifndef EPERM +#define EPERM 1 +#endif + +#ifndef ETIMEDOUT +#define ETIMEDOUT 145 +#endif + +#ifndef EADDRINUSE +#define EADDRINUSE 112 +#endif + +#ifndef EADDRNOTAVAIL +#define EADDRNOTAVAIL 125 +#endif + +#ifndef EAFNOSUPPORT +#define EAFNOSUPPORT 106 +#endif + +#ifndef ECONNREFUSED +#define ECONNREFUSED 111 +#endif + +#ifndef EDESTADDRREQ +#define EDESTADDRREQ 121 +#endif + +#ifndef EISCONN +#define EISCONN 127 +#endif + +#ifndef ENETDOWN +#define ENETDOWN 115 +#endif + +#ifndef ENETUNREACH +#define ENETUNREACH 114 +#endif + +#ifndef ENOBUFS +#define ENOBUFS 105 +#endif + +#ifndef ENOPROTOOPT +#define ENOPROTOOPT 109 +#endif + +#ifndef ENOTCONN +#define ENOTCONN 128 +#endif + +#ifndef EOPNOTSUPP +#define EOPNOTSUPP 95 +#endif + +#ifndef EOVERFLOW +#define EOVERFLOW 139 +#endif + +#ifndef EPROTONOSUPPORT +#define EPROTONOSUPPORT 123 +#endif + +#ifndef EPROTOTYPE +#define EPROTOTYPE 107 +#endif + +#ifndef EWOULDBLOCK +#define EWOULDBLOCK EAGAIN +#endif + +/* custom error codes */ +#define EFREERTOS 2001 /* FreeRTOS function failure */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_iar_errno__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/mqueue.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/mqueue.h new file mode 100644 index 0000000..ed794b9 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/mqueue.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016-2017 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== mqueue.h ======== + */ + +#ifndef ti_posix_iar_mqueue__include +#define ti_posix_iar_mqueue__include + +/* compiler vendor check */ +#ifndef __IAR_SYSTEMS_ICC__ +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#endif + +#include +#include + +#include "time.h" +#include "sys/types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Message queue descriptor */ +typedef void *mqd_t; + +/* + * ======== mq_attr ======== + */ +struct mq_attr { + long mq_flags; /* Message queue description flags: 0 or O_NONBLOCK. + Initialized from oflag argument of mq_open(). */ + long mq_maxmsg; /* Maximum number of messages on queue. */ + long mq_msgsize; /* Maximum message size. */ + long mq_curmsgs; /* Number of messages currently queued. */ +}; + +/* Deprecated. This typedef is for compatibility with old SDKs. It is + * not part of the POSIX standard. It will be removed in a future + * release. TIRTOS-1317 + */ +typedef struct mq_attr mq_attr; + +/* For mq_open() */ +#define O_CREAT 0x200 /* TODO: sys/fcntl.h? */ +#define O_EXCL 0x0800 /* Error on open if queue exists */ +#define O_RDONLY 0 +#define O_WRONLY 1 +#define O_RDWR 2 +#define O_NONBLOCK 0x4000 /* Fail with EAGAIN if resources unavailable */ + +typedef uint32_t mode_t; /* TODO: sys/stat.h? */ + +extern int mq_close(mqd_t mqdes); +extern int mq_getattr(mqd_t mqdes, struct mq_attr *mqstat); +extern mqd_t mq_open(const char *name, int oflags, ...); +extern ssize_t mq_receive(mqd_t mqdes, char *msg_ptr, size_t msg_len, + unsigned int *msg_prio); +extern int mq_send(mqd_t mqdes, const char *msg_ptr, size_t msg_len, + unsigned int msg_prio); +extern int mq_setattr(mqd_t mqdes, const struct mq_attr *mqstat, + struct mq_attr *omqstat); +extern ssize_t mq_timedreceive(mqd_t mqdes, char *msg_ptr, size_t msg_len, + unsigned int *msg_prio, const struct timespec *abstime); +extern int mq_timedsend(mqd_t mqdes, const char *msg_ptr, size_t msg_len, + unsigned int msg_prio, const struct timespec *abstime); +extern int mq_unlink(const char *name); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_iar_mqueue__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/pthread.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/pthread.h new file mode 100644 index 0000000..d575a9d --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/pthread.h @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2015-2017 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== pthread.h ======== + */ + +#ifndef ti_posix_iar_pthread__include +#define ti_posix_iar_pthread__include + +/* compiler vendor check */ +#ifndef __IAR_SYSTEMS_ICC__ +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#endif + +#include + +#include "sys/types.h" +#include "time.h" +#include "sched.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PTHREAD_BARRIER_SERIAL_THREAD -1 + +#define PTHREAD_CREATE_JOINABLE 0 +#define PTHREAD_CREATE_DETACHED 1 + +/* PThread cancellation */ +#define PTHREAD_CANCEL_ENABLE 0 +#define PTHREAD_CANCEL_DISABLE 1 +#define PTHREAD_CANCELED ((void *) -1) + +/* + * Mutex attributes - type + * + * PTHREAD_MUTEX_NORMAL: Owner of mutex cannot relock it. Attempting + * to relock will cause deadlock. + * PTHREAD_MUTEX_RECURSIVE: Owner can relock the mutex. + * PTHREAD_MUTEX_ERRORCHECK: If owner attempts to relock the mutex, an + * error is returned. + * + */ +#define PTHREAD_MUTEX_NORMAL 0 +#define PTHREAD_MUTEX_RECURSIVE 1 +#define PTHREAD_MUTEX_ERRORCHECK 2 +#define PTHREAD_MUTEX_DEFAULT PTHREAD_MUTEX_NORMAL + +/* Passed to pthread_once() */ +#define PTHREAD_ONCE_INIT 0 + +/* + * Mutex attributes - protocol + * + * PTHREAD_PRIO_NONE: Ownership of mutex does not affect priority. + * PTHREAD_PRIO_INHERIT: Owner's priority is boosted to the priority of + * highest priority thread blocked on the mutex. + * PTHREAD_PRIO_PROTECT: Mutex has a priority ceiling. The owner's + * priority is boosted to the highest priority ceiling of all mutexes + * owned (regardless of whether or not other threads are blocked on + * any of these mutexes). + */ +#define PTHREAD_PRIO_NONE 0 +#define PTHREAD_PRIO_INHERIT 1 +#define PTHREAD_PRIO_PROTECT 2 + +#define PTHREAD_PROCESS_PRIVATE 0 + +/* + ************************************************************************* + * pthread_attr + ************************************************************************* + */ +extern int pthread_attr_destroy(pthread_attr_t *attr); + +extern int pthread_attr_getdetachstate(const pthread_attr_t *attr, + int *detachstate); +extern int pthread_attr_getguardsize(const pthread_attr_t *attr, + size_t *guardsize); + +extern int pthread_attr_getschedparam(const pthread_attr_t *attr, + struct sched_param *schedparam); + +extern int pthread_attr_getstack(const pthread_attr_t *attr, + void **stackaddr, size_t *stacksize); +extern int pthread_attr_getstacksize(const pthread_attr_t *attr, + size_t *stacksize); + +extern int pthread_attr_init(pthread_attr_t *attr); + +extern int pthread_attr_setdetachstate(pthread_attr_t *attr, int detachedstate); +extern int pthread_attr_setguardsize(pthread_attr_t *attr, size_t guardsize); + +extern int pthread_attr_setschedparam(pthread_attr_t *attr, + const struct sched_param *schedparam); + +extern int pthread_attr_setstack(pthread_attr_t *attr, void *stackaddr, + size_t stacksize); +extern int pthread_attr_setstacksize(pthread_attr_t *attr, size_t stacksize); + +/* + ************************************************************************* + * pthread + ************************************************************************* + */ +extern int pthread_cancel(pthread_t pthread); +extern void _pthread_cleanup_pop(struct _pthread_cleanup_context *context, + int execute); +extern void _pthread_cleanup_push(struct _pthread_cleanup_context *context, + void (*fxn)(void *), void *arg); + +#define pthread_cleanup_push(fxn, arg) \ + do { \ + struct _pthread_cleanup_context _pthread_clup_ctx; \ + _pthread_cleanup_push(&_pthread_clup_ctx, (fxn), (arg)) + +#define pthread_cleanup_pop(execute) \ + _pthread_cleanup_pop(&_pthread_clup_ctx, (execute)); \ + } while (0) + +extern int pthread_create(pthread_t *newthread, const pthread_attr_t *attr, + void *(*startroutine)(void *), void *arg); +extern int pthread_detach(pthread_t pthread); +extern int pthread_equal(pthread_t pt1, pthread_t pt2); +extern void pthread_exit(void *ptr); +extern int pthread_getschedparam(pthread_t thread, int *policy, + struct sched_param *param); +extern int pthread_join(pthread_t th, void **thread_return); +extern int pthread_once(pthread_once_t *once, void (*initFxn)(void)); +extern pthread_t pthread_self(void); +extern int pthread_setcancelstate(int state, int *oldstate); +extern int pthread_setschedparam(pthread_t pthread, int policy, + const struct sched_param *param); + +/* + ************************************************************************* + * pthread_barrierattr + ************************************************************************* + */ +extern int pthread_barrierattr_destroy(pthread_barrierattr_t *attr); +extern int pthread_barrierattr_init(pthread_barrierattr_t *attr); + +/* + ************************************************************************* + * pthread_barrier + ************************************************************************* + */ +extern int pthread_barrier_destroy(pthread_barrier_t *barrier); +extern int pthread_barrier_init(pthread_barrier_t *barrier, + const pthread_barrierattr_t *attr, unsigned count); +extern int pthread_barrier_wait(pthread_barrier_t *barrier); + +/* + ************************************************************************* + * pthread_condattr + ************************************************************************* + */ +extern int pthread_condattr_destroy(pthread_condattr_t *attr); +extern int pthread_condattr_getclock(const pthread_condattr_t *attr, + clockid_t *clock_id); +extern int pthread_condattr_init(pthread_condattr_t * attr); +extern int pthread_condattr_setclock(pthread_condattr_t *attr, + clockid_t clock_id); + +/* + ************************************************************************* + * pthread_cond + ************************************************************************* + */ +extern int pthread_cond_broadcast(pthread_cond_t *cond); +extern int pthread_cond_destroy(pthread_cond_t *cond); +extern int pthread_cond_init(pthread_cond_t *cond, + const pthread_condattr_t *attr); +extern int pthread_cond_signal(pthread_cond_t *cond); +extern int pthread_cond_timedwait(pthread_cond_t *cond, pthread_mutex_t *mutex, + const struct timespec *abstime); +extern int pthread_cond_wait(pthread_cond_t *cond, pthread_mutex_t *mutex); + +/* + ************************************************************************* + * pthread_key + ************************************************************************* + */ +extern int pthread_key_create(pthread_key_t *key, void (*destructor)(void*)); +extern int pthread_key_delete(pthread_key_t key); +extern void *pthread_getspecific(pthread_key_t key); +extern int pthread_setspecific(pthread_key_t key, const void *value); + +/* + ************************************************************************* + * pthread_mutexattr + ************************************************************************* + */ +extern int pthread_mutexattr_destroy(pthread_mutexattr_t *attr); +extern int pthread_mutexattr_gettype(const pthread_mutexattr_t *attr, + int *type); +extern int pthread_mutexattr_getprioceiling(const pthread_mutexattr_t *attr, + int *prioceiling); +extern int pthread_mutexattr_getprotocol(const pthread_mutexattr_t *attr, + int *protocol); +extern int pthread_mutexattr_init(pthread_mutexattr_t *attr); +extern int pthread_mutexattr_setprioceiling(pthread_mutexattr_t *attr, + int prioceiling); +extern int pthread_mutexattr_setprotocol(pthread_mutexattr_t *attr, + int protocol); +extern int pthread_mutexattr_settype(pthread_mutexattr_t *attr, int type); + +/* + ************************************************************************* + * pthread_mutex + ************************************************************************* + */ +extern int pthread_mutex_destroy(pthread_mutex_t *mutex); +extern int pthread_mutex_getprioceiling(const pthread_mutex_t *mutex, + int *prioceiling); +extern int pthread_mutex_init(pthread_mutex_t *mutex, + const pthread_mutexattr_t *attr); +extern int pthread_mutex_lock(pthread_mutex_t *mutex); +extern int pthread_mutex_setprioceiling(pthread_mutex_t *mutex, + int prioceiling, int *oldceiling); +extern int pthread_mutex_timedlock(pthread_mutex_t *mutex, + const struct timespec *abstime); +extern int pthread_mutex_trylock(pthread_mutex_t *mutex); + +extern int pthread_mutex_unlock(pthread_mutex_t *mutex); + +/* + ************************************************************************* + * pthread_rwlockattr + ************************************************************************* + */ +extern int pthread_rwlockattr_destroy(pthread_rwlockattr_t *attr); +extern int pthread_rwlockattr_init(pthread_rwlockattr_t * attr); + +/* + ************************************************************************* + * pthread_rwlock + ************************************************************************* + */ +extern int pthread_rwlock_destroy(pthread_rwlock_t *rwlock); +extern int pthread_rwlock_init(pthread_rwlock_t *rwlock, + const pthread_rwlockattr_t *attr); + +extern int pthread_rwlock_rdlock(pthread_rwlock_t *rwlock); +extern int pthread_rwlock_timedrdlock(pthread_rwlock_t *rwlock, + const struct timespec *abstime); +extern int pthread_rwlock_timedwrlock(pthread_rwlock_t *rwlock, + const struct timespec *abstime); +extern int pthread_rwlock_tryrdlock(pthread_rwlock_t *rwlock); +extern int pthread_rwlock_trywrlock(pthread_rwlock_t *rwlock); +extern int pthread_rwlock_unlock(pthread_rwlock_t *rwlock); +extern int pthread_rwlock_wrlock(pthread_rwlock_t *rwlock); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_iar_pthread__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sched.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sched.h new file mode 100644 index 0000000..4d5e180 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sched.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016-2017 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== sched.h ======== + */ + +#ifndef ti_posix_iar_sched__include +#define ti_posix_iar_sched__include + +/* compiler vendor check */ +#ifndef __IAR_SYSTEMS_ICC__ +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#endif + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * These defines would be in a sched.h, which TI and IAR + * toolchains don't have. + */ +#ifndef SCHED_FIFO +#define SCHED_FIFO 0 +#endif + +#ifndef SCHED_RR +#define SCHED_RR 0 +#endif + +#ifndef SCHED_OTHER +#define SCHED_OTHER 0 +#endif + +/* + * ======== sched_param ======== + * This was taken from sys/sched.h + */ +struct sched_param { + int sched_priority; /* Thread execution priority */ +}; + +/* + * GNU sched.h declares sched_get_priority_min(), + * sched_get_priority_max(), and sched_yield() inside an + * #if defined(_POSIX_PRIORITY_SCHEDULING) + * block. + */ +extern int sched_get_priority_min(int policy); +extern int sched_get_priority_max(int policy); + +extern int sched_yield(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_iar_sched__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/semaphore.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/semaphore.h new file mode 100644 index 0000000..5569806 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/semaphore.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2015-2017 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== semaphore.h ======== + */ + +#ifndef ti_posix_iar_semaphore__include +#define ti_posix_iar_semaphore__include + +/* compiler vendor check */ +#ifndef __IAR_SYSTEMS_ICC__ +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#endif + +#include +#include "sys/_internal.h" + +/* + * Include definitions of timespec and clockid_t that would + * be in sys/types.h. TI and IAR tool chains do not have a + * sys/types.h header file, while GNU toolchain does. For + * GNU, sys/types.h is included in time.h. + */ +#include "time.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef union { + struct sysbios_Semaphore sysbios; + struct freertos_Semaphore freertos; +} sem_t; + +int sem_destroy(sem_t *sem); +int sem_getvalue(sem_t *sem, int *value); +int sem_init(sem_t *sem, int pshared, unsigned value); +int sem_post(sem_t *sem); +int sem_timedwait(sem_t *sem, const struct timespec *abstime); +int sem_trywait(sem_t *sem); +int sem_wait(sem_t *sem); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_iar_semaphore__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/signal.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/signal.h new file mode 100644 index 0000000..4183ca8 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/signal.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2017 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== signal.h ======== + */ + +#ifndef ti_posix_iar_signal__include +#define ti_posix_iar_signal__include + +/* compiler vendor check */ +#ifndef __IAR_SYSTEMS_ICC__ +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#endif + +#include "sys/types.h" + +/* include toolchain's header file */ +#if defined(__430_CORE__) || defined(__430X_CORE__) +#include <../inc/dlib/c/signal.h> +#else +#include <../inc/c/signal.h> +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef SIGEV_NONE +#define SIGEV_NONE 1 +#endif + +#ifndef SIGEV_SIGNAL +#define SIGEV_SIGNAL 2 +#endif + +#ifndef SIGEV_THREAD +#define SIGEV_THREAD 3 +#endif + + +/* + ************************************************************************* + * signal types + ************************************************************************* + */ + +/* + * ======== sigval ======== + */ +union sigval { + int sival_int; /* integer signal value */ + void *sival_ptr; /* pointer signal value */ +}; + +/* Deprecated. This typedef is for compatibility with old SDKs. It is + * not part of the POSIX standard. It will be removed in a future + * release. TIRTOS-1317 + */ +typedef union sigval sigval; + +/* + * ======== sigevent ======== + */ +struct sigevent { + int sigev_notify; /* notification type */ + int sigev_signo; /* signal number */ + union sigval sigev_value; /* signal value */ + + void (*sigev_notify_function)(union sigval val); /* notify function */ + pthread_attr_t *sigev_notify_attributes; /* notify attributes */ +}; + +/* Deprecated. This typedef is for compatibility with old SDKs. It is + * not part of the POSIX standard. It will be removed in a future + * release. TIRTOS-1317 + */ +typedef struct sigevent sigevent; + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_iar_signal__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/_internal.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/_internal.h new file mode 100644 index 0000000..b49f131 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/_internal.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2017-2018 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== sys/_internal.h ======== + * Vendor specific internal details + */ + +#ifndef ti_posix_iar_sys__internal__include +#define ti_posix_iar_sys__internal__include + +/* compiler vendor check */ +#ifndef __IAR_SYSTEMS_ICC__ +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#endif + +#include /* C99 standard integer types */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* These opaque object types replicate the kernel internal object + * structures. They are used in a union when defining an opaque + * object in order to guarantee the opaque object is correctly sized + * and aligned with respect to the kernel objects. + */ +enum Opaque_Mode { + Opaque_Mode_1, + Opaque_Mode_2, + Opaque_Mode_3, + Opaque_Mode_4 +}; + +struct Opaque_Struct__; + +struct Opaque_QueueElem { + struct Opaque_QueueElem *volatile next; + struct Opaque_QueueElem *volatile prev; +}; + +struct Opaque_QueueStruct { + struct Opaque_QueueElem __f0; + struct Opaque_Struct__ *__f1; +}; + +struct sysbios_Semaphore { + struct Opaque_Struct__ *__f0; + unsigned int __f1; + enum Opaque_Mode __f2; + volatile uint_least16_t __f3; + struct Opaque_QueueStruct __f4; + struct Opaque_Struct__ *__f5; +}; + +struct freertos_Semaphore { + void *__f0; +}; + +struct sysbios_Barrier { + struct sysbios_Semaphore sem; + int count; + int pendCount; +}; + +struct freertos_Barrier { + int count; + int pendCount; + struct Opaque_Struct__ *waitList; + struct Opaque_Struct__ *last; +}; + +struct sysbios_Mutex { + struct Opaque_Struct__ *owner; + int lockCnt; + int type; + struct sysbios_Semaphore sem; + struct Opaque_Struct__ *mpo; +}; + +struct freertos_Mutex { + int protocol; + void *owner; + int type; + void *sem; /* struct freertos_Semaphore */ +}; + +struct sysbios_RWLock { + struct sysbios_Semaphore sem; + struct sysbios_Semaphore readSem; + int activeReaderCnt; + int blockedReaderCnt; + void *owner; +}; + +struct freertos_RWLock { + struct freertos_Semaphore sem; + struct freertos_Semaphore readSem; + int activeReaderCnt; + int blockedReaderCnt; + void *owner; +}; + +struct sysbios_Cond { + struct Opaque_QueueStruct waitList; + uint32_t clockId; +}; + +struct freertos_Cond { + struct Opaque_QueueElem waitList; + uint32_t clockId; +}; + + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_iar_sys__internal__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/time.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/time.h new file mode 100644 index 0000000..4c554cc --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/time.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2017 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== sys/time.h ======== + */ + +#ifndef ti_posix_iar_sys_time__include +#define ti_posix_iar_sys_time__include + +/* compiler vendor check */ +#ifndef __IAR_SYSTEMS_ICC__ +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#endif + +#include +#include + +/* include compiler time.h */ +#if defined(__430_CORE__) || defined(__430X_CORE__) +#include <../inc/dlib/c/time.h> +#else +#include <../inc/c/time.h> +#endif + +#include "types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct timeval { + time_t tv_sec; + suseconds_t tv_usec; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_iar_sys_time__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/types.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/types.h new file mode 100644 index 0000000..dee0b6e --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/types.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2017-2018 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== sys/types.h ======== + */ + +#ifndef ti_posix_iar_sys_types__include +#define ti_posix_iar_sys_types__include + +/* compiler vendor check */ +#ifndef __IAR_SYSTEMS_ICC__ +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#endif + +#include +#include +#include "_internal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* IAR compiler does not define type ssize_t. However, the compiler does + * define size_t as __SIZE_T_TYPE__ for all ISAs. We define ssize_t by + * changing 'unsigned' to 'signed' for this one definition to ensure both + * types have the same bit-width. Set declaration flag using same name + * as GNU compiler, which defines both types. + */ +#ifdef __SIZE_T_TYPE__ +#define unsigned signed +typedef __SIZE_T_TYPE__ ssize_t; +#undef unsigned +#define _SSIZE_T_DECLARED +#else +#error __SIZE_T_TYPE__ not defined +#endif + +typedef uint32_t clockid_t; +typedef unsigned long useconds_t; +typedef unsigned long timer_t; +typedef long suseconds_t; +typedef unsigned short uid_t; + +/* IAR compiler defines time_t in time[32,64].h (should be in sys/types.h). + * Pull in time.h (which includes time[32,64].h) to get time_t definition. + */ +#if defined(__430_CORE__) || defined(__430X_CORE__) +#include <../inc/dlib/c/time.h> +#else +#include <../inc/c/time.h> +#endif + + +/* + ************************************************************************* + * posix types + ************************************************************************* + */ + +/* + * ======== pthread_attr_t ======== + */ +typedef struct pthread_attr_t { + int priority; + void *stack; + size_t stacksize; + size_t guardsize; + int detachstate; +} pthread_attr_t; + +typedef uint32_t pthread_barrierattr_t; +typedef uint32_t pthread_condattr_t; + +typedef void *pthread_key_t; + +typedef struct pthread_mutexattr_t { + int type; + int protocol; + int prioceiling; +} pthread_mutexattr_t; + +typedef uint32_t pthread_rwlockattr_t; + +typedef void *pthread_t; + +typedef union { + struct sysbios_Barrier sysbios; + struct freertos_Barrier freertos; +} pthread_barrier_t; + +typedef union { + struct sysbios_Cond sysbios; + struct freertos_Cond freertos; +} pthread_cond_t; + +typedef union { + struct sysbios_Mutex sysbios; + struct freertos_Mutex freertos; +} pthread_mutex_t; + +typedef uint32_t pthread_once_t; + +typedef union { + struct sysbios_RWLock sysbios; + struct freertos_RWLock freertos; +} pthread_rwlock_t; + +struct _pthread_cleanup_context { + pthread_t thread; + void (*fxn)(void *); + void *arg; + int cancelType; + struct _pthread_cleanup_context *next; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_iar_sys_types__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/time.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/time.h new file mode 100644 index 0000000..1fd1297 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/time.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2017-2019 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== time.h ======== + */ + +#ifndef ti_posix_iar_time__include +#define ti_posix_iar_time__include + +/* compiler vendor check */ +#ifndef __IAR_SYSTEMS_ICC__ +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#endif + +#include +#include + +/* include compiler time.h */ +#if defined(__430_CORE__) || defined(__430X_CORE__) +#include <../inc/dlib/c/time.h> +#else + +/* disable IAR inline definition of time() */ +#define _NO_DEFINITIONS_IN_HEADER_FILES 1 +#include <../inc/c/time.h> +#endif + +#include "signal.h" +#include "sys/types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Timer support. + */ +/* + * CLOCK_REALTIME represents the realtime clock for the system. For this + * clock, clock_gettime() returns the time since the beginning of the + * Epoch. SYS/BIOS implements clock_gettime() and clock_settime() with + * the ti.sysbios.hal.Seconds module for CLOCK_REALTIME. + */ +#ifndef CLOCK_REALTIME +#define CLOCK_REALTIME (clockid_t)1 +#endif + +/* + * CLOCK_MONOTONIC represents a system clock that cannot be set via + * clock_settime(). For SYS/BIOS, CLOCK_MONOTONIC represents the + * ti.sysbios.knl.Clock system clock. + */ +#ifndef CLOCK_MONOTONIC +#define CLOCK_MONOTONIC (clockid_t)2 +#endif + +#ifndef TIMER_ABSTIME +#define TIMER_ABSTIME 4 +#endif + +struct itimerspec { + struct timespec it_interval; /* Timer interval */ + struct timespec it_value; /* Timer expiration */ +}; + +/* + * For clockId = CLOCK_REALTIME, clock_gettime() and clock_settime() use + * the BIOS Seconds module to get/set the time. Before using clock_gettime() + * with clockId = CLOCK_REALTIME, the Seconds module must be initialized. + * This can be done by either calling clock_settime(CLOCK_REALTIME,...), + * or Seconds_set(). + * For clockId = CLOCK_MONOTONIC, clock_gettime() returns a time based on + * ti.sysbios.knl.Clock ticks. + */ +extern int clock_gettime(clockid_t clockId, struct timespec *ts); + +extern int clock_nanosleep(clockid_t clock_id, int flags, + const struct timespec *rqtp, struct timespec *rmtp); + +/* + * Only clockId = CLOCK_REALTIME is supported for clock_settime(). Only + * the value of ts->tv_sec is used is used in clock_settime(). + * Returns EINVAL if clockId = CLOCK_MONOTONIC. + */ +extern int clock_settime(clockid_t clockId, const struct timespec *ts); + +/* + * Create a timer based on the BIOS Clock module. To reduce code size, + * the clockId parameter is ignored. + */ +extern int timer_create(clockid_t clockId, struct sigevent *evp, + timer_t *timerid); +extern int timer_delete(timer_t timerid); +extern int timer_gettime(timer_t timerid, struct itimerspec *its); +extern int timer_settime(timer_t timerid, int flags, + const struct itimerspec *value, struct itimerspec *ovalue); + +extern int nanosleep(const struct timespec *rqtp, struct timespec *rmtp); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_iar_time__include */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/unistd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/unistd.h new file mode 100644 index 0000000..a1766c0 --- /dev/null +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/unistd.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2015-2017 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== unistd.h ======== + */ + +#ifndef ti_posix_iar_unistd__include +#define ti_posix_iar_unistd__include + +/* compiler vendor check */ +#ifndef __IAR_SYSTEMS_ICC__ +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#endif + +#include "sys/types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern unsigned sleep(unsigned seconds); +extern int usleep(useconds_t useconds); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_posix_iar_unistd__include */ diff --git a/examples/knx-cc1310/knx_wrapper.cpp b/examples/knx-cc1310/knx_wrapper.cpp new file mode 100644 index 0000000..5a0d964 --- /dev/null +++ b/examples/knx-cc1310/knx_wrapper.cpp @@ -0,0 +1,49 @@ +#include "knx.h" +#include + +#include "knx_wrapper.h" + +KnxFacade *pKnx = nullptr; + +void buttonUp() +{ + static uint32_t lastpressed=0; + if (millis() - lastpressed > 200) + { + KnxFacade &knx = *pKnx; + knx._toogleProgMode = true; + lastpressed = millis(); + } +} + +void setup() +{ + pKnx = new KnxFacade; + KnxFacade &knx = *pKnx; + + // see GPIO_PinConfig gpioPinConfigs[] + knx.buttonPin(0); + knx.ledPinActiveOn(HIGH); + + knx.platform().init(); + + knx.readMemory(); + + if (knx.individualAddress() == 0) + knx.progMode(true); + + if (knx.configured()) + { + printf("configured %d\n", knx.paramByte(5)); + } + else + println("not configured"); + knx.start(); +} + +void loop() +{ + KnxFacade &knx = *pKnx; + + knx.loop(); +} diff --git a/examples/knx-cc1310/knx_wrapper.h b/examples/knx-cc1310/knx_wrapper.h new file mode 100644 index 0000000..3390c77 --- /dev/null +++ b/examples/knx-cc1310/knx_wrapper.h @@ -0,0 +1,12 @@ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +extern void setup(); +extern void loop(); + +#ifdef __cplusplus +} +#endif diff --git a/examples/knx-cc1310/main_nortos.c b/examples/knx-cc1310/main_nortos.c new file mode 100644 index 0000000..089a283 --- /dev/null +++ b/examples/knx-cc1310/main_nortos.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== main_nortos.c ======== + */ +#include +#include + +#include "SEGGER_RTT.h" + +#include + +/* Example/Board Header files */ +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/driverlib_release.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/vims.h) + +#include "knx_wrapper.h" + +#define USE_32KHZ_XTAL_AS_LF_CLOCK false + +extern void *mainThread(void *arg0); + +void __cxa_pure_virtual() +{ + SEGGER_RTT_WriteString(0, "Pure virtual method called! System halted.\r\n"); + while (1); +} + +/* + * ======== mainThread ======== + */ +void *mainThread(void *arg0) +{ + setup(); + + /* Loop forever echoing */ + while (1) { + loop(); + } +} + +/* + * ======== main ======== + */ +int main(void) +{ + // Setup RTT config for debug output + SEGGER_RTT_ConfigUpBuffer(0, NULL, NULL, 0, SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL); + SEGGER_RTT_WriteString(0, "\r\nSystem startup.\r\n"); + + // Make sure that compiled objects match the linked SDK library version + DRIVERLIB_ASSERT_CURR_RELEASE(); + + // Enable flash cache + VIMSModeSet(VIMS_BASE, VIMS_MODE_ENABLED); + // Configure round robin arbitration and prefetching + VIMSConfigure(VIMS_BASE, true, true); + + /* Set config parameters for NoRTOS */ + NoRTOS_Config config; + NoRTOS_getConfig(&config); + config.idleCallback = Power_idleFunc; + NoRTOS_setConfig(&config); + + // set LF clock source needed for low power deepSleep() function further below + //OSCClockSourceSet(OSC_SRC_CLK_LF, USE_32KHZ_XTAL_AS_LF_CLOCK ? OSC_XOSC_LF : OSC_RCOSC_LF); + + // Call driver init functions before starting NoRTOS/RTOS + Board_init(); + + // Start NoRTOS (this just enables the HwI globally and returns immediately as + // we are not using RTOS here) + NoRTOS_start(); + + // Call mainThread function + mainThread(NULL); + + // Shall not be reached + while (1) {} +} diff --git a/examples/knx-cc1310/smartrf_settings/smartrf_settings.c b/examples/knx-cc1310/smartrf_settings/smartrf_settings.c new file mode 100644 index 0000000..f690809 --- /dev/null +++ b/examples/knx-cc1310/smartrf_settings/smartrf_settings.c @@ -0,0 +1,257 @@ +//********************************************************************************* +// Generated by SmartRF Studio version 2.6.0 (build #8) +// Tested for SimpleLink SDK version: CC13x0 SDK 1.30.xx.xx +// Device: CC1310 Rev. 2.1 +// +//********************************************************************************* + +//********************************************************************************* +// Parameter summary +// Address: on +// Address0: 0x44FF +// Frequency: 868.29999 MHz +// Data Format: Serial mode disable +// Deviation: 50.000 kHz +// Max Packet Length: unlimited packet length mode +// RX Filter BW: 196 kHz +// Symbol Rate: 32.76825 kBaud +// Sync Word Length: 24 Bits +// TX Power: 14 dBm (requires define CCFG_FORCE_VDDR_HH = 1 in ccfg.c, see CC13xx/CC26xx Technical Reference Manual) +// Whitening: No whitening +// FEC mode: manchester code + +#include +#include DeviceFamily_constructPath(driverlib/rf_mailbox.h) +#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h) +#include DeviceFamily_constructPath(driverlib/rf_prop_cmd.h) +#include +#include DeviceFamily_constructPath(rf_patches/rf_patch_cpe_wmbus_smode.h) +#include DeviceFamily_constructPath(rf_patches/rf_patch_mce_wmbus_smode.h) +#include DeviceFamily_constructPath(rf_patches/rf_patch_rfe_wmbus_smode.h) +#include "smartrf_settings.h" + + +// TI-RTOS RF Mode Object +RF_Mode RF_prop = +{ + .rfMode = RF_MODE_PROPRIETARY_SUB_1, + .cpePatchFxn = &rf_patch_cpe_wmbus_smode, + .mcePatchFxn = &rf_patch_mce_wmbus_smode, + .rfePatchFxn = &rf_patch_rfe_wmbus_smode, +}; + +// Overrides for CMD_PROP_RADIO_DIV_SETUP +static uint32_t pOverrides[] = +{ + // PHY: Run the MCE and RFE patches + MCE_RFE_OVERRIDE(1,0,0,1,0,0), + // override_synth_prop_863_930_div5.xml + // Synth: Set recommended RTRIM to 7 + HW_REG_OVERRIDE(0x4038,0x0037), + // Synth: Set Fref to 4 MHz + (uint32_t)0x000684A3, + // Synth: Configure fine calibration setting + HW_REG_OVERRIDE(0x4020,0x7F00), + // Synth: Configure fine calibration setting + HW_REG_OVERRIDE(0x4064,0x0040), + // Synth: Configure fine calibration setting + (uint32_t)0xB1070503, + // Synth: Configure fine calibration setting + (uint32_t)0x05330523, + // Synth: Set loop bandwidth after lock to 20 kHz + (uint32_t)0x0A480583, + // Synth: Set loop bandwidth after lock to 20 kHz + (uint32_t)0x7AB80603, + // Synth: Configure VCO LDO (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference) + ADI_REG_OVERRIDE(1,4,0x9F), + // Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1) + ADI_HALFREG_OVERRIDE(1,7,0x4,0x4), + // Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering + (uint32_t)0x02010403, + // Synth: Configure extra PLL filtering + (uint32_t)0x00108463, + // Synth: Increase synth programming timeout (0x04B0 RAT ticks = 300 us) + (uint32_t)0x04B00243, + // override_synth_disable_bias_div5.xml + // Synth: Set divider bias to disabled + HW32_ARRAY_OVERRIDE(0x405C,1), + // Synth: Set divider bias to disabled (specific for loDivider=5) + (uint32_t)0x18000200, + // override_phy_rx_aaf_bw_0xd.xml + // Rx: Set anti-aliasing filter bandwidth to 0xD (in ADI0, set IFAMPCTL3[7:4]=0xD) + ADI_HALFREG_OVERRIDE(0,61,0xF,0xD), + // override_phy_gfsk_rx.xml + // Rx: Set LNA bias current trim offset to 3 + (uint32_t)0x00038883, + // Rx: Freeze RSSI on sync found event + HW_REG_OVERRIDE(0x6084,0x35F1), + // Tx: Configure PA ramping setting (0x61). Rx: Set AGC reference level to 0x1F + HW_REG_OVERRIDE(0x6088,0x611F), + // Tx: Configure PA ramping setting and setting AGC settle wait = 21 samples + HW_REG_OVERRIDE(0x608C,0x8112), + // Rx: Set RSSI offset to adjust reported RSSI by +7 dB + (uint32_t)0x00F988A3, + // TX power override + // Tx: Set PA trim to max (in ADI0, set PACTL0=0xF8) + ADI_REG_OVERRIDE(0,12,0xF8), + // Set AGC win size = 7 samples + HW_REG_OVERRIDE(0x6064,0x1306), + (uint32_t)0xFFFFFFFF, +}; + +// CMD_PROP_RADIO_DIV_SETUP +rfc_CMD_PROP_RADIO_DIV_SETUP_t RF_cmdPropRadioDivSetup = +{ + .commandNo = 0x3807, + .status = 0x0000, + .pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx + .startTime = 0x00000000, + .startTrigger.triggerType = 0x0, + .startTrigger.bEnaCmd = 0x0, + .startTrigger.triggerNo = 0x0, + .startTrigger.pastTrig = 0x0, + .condition.rule = 0x1, + .condition.nSkip = 0x0, + .modulation.modType = 0x0, + .modulation.deviation = 0xC8, + .symbolRate.preScale = 0xF, + .symbolRate.rateWord = 0x53E3, + .rxBw = 0x27, // S2-mode (for S1-mode, rxBw = 0x29) + .preamConf.nPreamBytes = 0x3, + .preamConf.preamMode = 0x0, + .formatConf.nSwBits = 0x18, + .formatConf.bBitReversal = 0x0, + .formatConf.bMsbFirst = 0x1, + .formatConf.fecMode = 0x0a, // manchester coding + .formatConf.whitenMode = 0x0, + .config.frontEndMode = 0x0, + .config.biasMode = 0x1, + .config.analogCfgMode = 0x0, + .config.bNoFsPowerUp = 0x0, + .txPower = 0xA73F, + .pRegOverride = pOverrides, + .centerFreq = 0x0364, + .intFreq = 0x8000, + .loDivider = 0x05, +}; + +// CMD_FS +rfc_CMD_FS_t RF_cmdFs = +{ + .commandNo = 0x0803, + .status = 0x0000, + .pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx + .startTime = 0x00000000, + .startTrigger.triggerType = 0x0, + .startTrigger.bEnaCmd = 0x0, + .startTrigger.triggerNo = 0x0, + .startTrigger.pastTrig = 0x0, + .condition.rule = 0x1, + .condition.nSkip = 0x0, + .frequency = 0x0364, + .fractFreq = 0x4CCD, + .synthConf.bTxMode = 0x0, + .synthConf.refFreq = 0x0, + .__dummy0 = 0x00, + .__dummy1 = 0x00, + .__dummy2 = 0x00, + .__dummy3 = 0x0000, +}; + +// CMD_PROP_TX +rfc_CMD_PROP_TX_t RF_cmdPropTx = +{ + .commandNo = 0x3801, + .status = 0x0000, + .pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx + .startTime = 0x00000000, + .startTrigger.triggerType = 0x0, + .startTrigger.bEnaCmd = 0x0, + .startTrigger.triggerNo = 0x0, + .startTrigger.pastTrig = 0x0, + .condition.rule = 0x1, + .condition.nSkip = 0x0, + .pktConf.bFsOff = 0x0, // 0: Keep synthesizer running after end trigger + .pktConf.bUseCrc = 0x0, // CRC engine cannot be used + .pktConf.bVarLen = 0x0, // 0: Fixed length + .pktLen = 0x00, // SET APPLICATION PAYLOAD LENGTH + .syncWord = 0x547696, + .pPkt = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx +}; + +// CMD_PROP_RX_ADV +rfc_CMD_PROP_RX_ADV_t RF_cmdPropRxAdv = +{ + .commandNo = 0x3804, + .status = 0x0000, + .pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx + .startTime = 0x00000000, + .startTrigger.triggerType = 0x0, + .startTrigger.bEnaCmd = 0x0, + .startTrigger.triggerNo = 0x0, + .startTrigger.pastTrig = 0x0, + .condition.rule = 0x1, + .condition.nSkip = 0x0, + .pktConf.bFsOff = 0x0, // 0: Keep synthesizer running after end trigger + .pktConf.bRepeatOk = 0x0, + .pktConf.bRepeatNok = 0x0, + .pktConf.bUseCrc = 0x0, // CRC engine cannot be used + .pktConf.bCrcIncSw = 0x0, + .pktConf.bCrcIncHdr = 0x1, + .pktConf.endType = 0x0, + .pktConf.filterOp = 0x0, // 0: Abort packet reception and restart syncword search + .rxConf.bAutoFlushIgnored = 0x0, // Not supported for partial RX buffers + .rxConf.bAutoFlushCrcErr = 0x0, + .rxConf.bIncludeHdr = 0x1, + .rxConf.bIncludeCrc = 0x0, + .rxConf.bAppendRssi = 0x0, + .rxConf.bAppendTimestamp = 0x0, + .rxConf.bAppendStatus = 0x0, + .syncWord0 = 0x547696, // KNX-RF syncword + .syncWord1 = 0, + .maxPktLen = 0, + .hdrConf.numHdrBits = 8, // One length byte in header + .hdrConf.lenPos = 0, + .hdrConf.numLenBits = 0, // Engine shall not read the length itself. We set it later. (maxPktLen must be 0!) + .addrConf.addrType = 0, // Address bytes AFTER header + .addrConf.addrSize = 2, // use the two fixed bytes (0x44 and 0xff) after the length byte as address bytes + .addrConf.addrPos = 0, + .addrConf.numAddr = 1, // just the two fixed bytes are used as one address + .lenOffset = 0, + .endTrigger.triggerType = 0x1, + .endTrigger.bEnaCmd = 0x0, + .endTrigger.triggerNo = 0x0, + .endTrigger.pastTrig = 0x0, + .endTime = 0x00000000, + .pAddr = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx + .pQueue = 0, // INSERT APPLICABLE POINTER: (dataQueue_t*)&xxx + .pOutput = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx +}; + +// TX Power table +// The RF_TxPowerTable_DEFAULT_PA_ENTRY macro is defined in RF.h and requires the following arguments: +// RF_TxPowerTable_DEFAULT_PA_ENTRY(bias, gain, boost coefficient) +// See the Technical Reference Manual for further details about the "txPower" Command field. +// The PA settings require the CCFG_FORCE_VDDR_HH = 0 unless stated otherwise. +const RF_TxPowerTable_Entry PROP_RF_txPowerTable[] = +{ + {-10, RF_TxPowerTable_DEFAULT_PA_ENTRY(0, 3, 0, 4) }, + {0, RF_TxPowerTable_DEFAULT_PA_ENTRY(1, 1, 0, 0) }, + {1, RF_TxPowerTable_DEFAULT_PA_ENTRY(3, 3, 0, 8) }, + {2, RF_TxPowerTable_DEFAULT_PA_ENTRY(2, 1, 0, 8) }, + {3, RF_TxPowerTable_DEFAULT_PA_ENTRY(4, 3, 0, 10) }, + {4, RF_TxPowerTable_DEFAULT_PA_ENTRY(5, 3, 0, 12) }, + {5, RF_TxPowerTable_DEFAULT_PA_ENTRY(6, 3, 0, 12) }, + {6, RF_TxPowerTable_DEFAULT_PA_ENTRY(7, 3, 0, 14) }, + {7, RF_TxPowerTable_DEFAULT_PA_ENTRY(9, 3, 0, 16) }, + {8, RF_TxPowerTable_DEFAULT_PA_ENTRY(11, 3, 0, 18) }, + {9, RF_TxPowerTable_DEFAULT_PA_ENTRY(13, 3, 0, 22) }, + {10, RF_TxPowerTable_DEFAULT_PA_ENTRY(19, 3, 0, 28) }, + {11, RF_TxPowerTable_DEFAULT_PA_ENTRY(26, 3, 0, 40) }, + {12, RF_TxPowerTable_DEFAULT_PA_ENTRY(24, 0, 0, 92) }, + {13, RF_TxPowerTable_DEFAULT_PA_ENTRY(63, 0, 0, 83) }, // The original PA value (12.5 dBm) have been rounded to an integer value. + {14, RF_TxPowerTable_DEFAULT_PA_ENTRY(63, 0, 1, 83) }, // This setting requires CCFG_FORCE_VDDR_HH = 1. + RF_TxPowerTable_TERMINATION_ENTRY +}; + +const uint8_t PROP_RF_txPowerTableSize = sizeof(PROP_RF_txPowerTable)/sizeof(RF_TxPowerTable_Entry); diff --git a/examples/knx-cc1310/smartrf_settings/smartrf_settings.h b/examples/knx-cc1310/smartrf_settings/smartrf_settings.h new file mode 100644 index 0000000..c13c568 --- /dev/null +++ b/examples/knx-cc1310/smartrf_settings/smartrf_settings.h @@ -0,0 +1,30 @@ +#ifndef _SMARTRF_SETTINGS_H_ +#define _SMARTRF_SETTINGS_H_ + +//********************************************************************************* +// Generated by SmartRF Studio version 2.9.0 (build #168) +// Tested for SimpleLink SDK version: CC13x0 SDK 2.10.xx.xx +// Device: CC1310 Rev. 2.1 +// +//********************************************************************************* + +#include +#include DeviceFamily_constructPath(driverlib/rf_mailbox.h) +#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h) +#include DeviceFamily_constructPath(driverlib/rf_prop_cmd.h) +#include + +// RF Core TX power +extern const RF_TxPowerTable_Entry PROP_RF_txPowerTable[]; +extern const uint8_t PROP_RF_txPowerTableSize; + +// TI-RTOS RF Mode Object +extern RF_Mode RF_prop; + +// RF Core API commands +extern rfc_CMD_PROP_RADIO_DIV_SETUP_t RF_cmdPropRadioDivSetup; +extern rfc_CMD_FS_t RF_cmdFs; +extern rfc_CMD_PROP_TX_t RF_cmdPropTx; +extern rfc_CMD_PROP_RX_ADV_t RF_cmdPropRxAdv; + +#endif // _SMARTRF_SETTINGS_H_ diff --git a/examples/knx-cc1310/startup_cc13xx_cc26xx_gcc.c b/examples/knx-cc1310/startup_cc13xx_cc26xx_gcc.c new file mode 100644 index 0000000..6a00426 --- /dev/null +++ b/examples/knx-cc1310/startup_cc13xx_cc26xx_gcc.c @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +//***************************************************************************** +// +// Check if compiler is GNU Compiler +// +//***************************************************************************** +#if !(defined(__GNUC__)) +#error "startup_cc13xx_cc26xx_gcc.c: Unsupported compiler!" +#endif + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/setup.h) + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void resetISR(void); +static void nmiISR(void); +static void faultISR(void); +static void defaultHandler(void); +static void busFaultHandler(void); + +//***************************************************************************** +// +// External declaration for the reset handler that is to be called when the +// processor is started +// +//***************************************************************************** +extern void _c_int00(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +//***************************************************************************** +// +// linker variable that marks the top of stack. +// +//***************************************************************************** +extern unsigned long _stack_end; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".resetVecs"))) __attribute__ ((used)) +static void (* const resetVectors[16])(void) = +{ + (void (*)(void))((uint32_t)&_stack_end), + // The initial stack pointer + resetISR, // The reset handler + nmiISR, // The NMI handler + faultISR, // The hard fault handler + defaultHandler, // The MPU fault handler + busFaultHandler, // The bus fault handler + defaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + defaultHandler, // SVCall handler + defaultHandler, // Debug monitor handler + 0, // Reserved + defaultHandler, // The PendSV handler + defaultHandler // The SysTick handler +}; + +__attribute__ ((section(".ramVecs"))) +static unsigned long ramVectors[50]; + +//***************************************************************************** +// +// The following are arrays of pointers to constructor functions that need to +// be called during startup to initialize global objects. +// +//***************************************************************************** +extern void (*__init_array_start []) (void); +extern void (*__init_array_end []) (void); + +//***************************************************************************** +// +// The following global variable is required for C++ support. +// +//***************************************************************************** +void * __dso_handle = (void *) &__dso_handle; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern uint32_t __bss_start__, __bss_end__; +extern uint32_t __data_load__, __data_start__, __data_end__; + +// +//***************************************************************************** +// +// Initialize the .data and .bss sections and copy the first 16 vectors from +// the read-only/reset table to the runtime RAM table. Fill the remaining +// vectors with a stub. This vector table will be updated at runtime. +// +//***************************************************************************** +// +void localProgramStart(void) +{ + uint32_t * bs; + uint32_t * be; + uint32_t * dl; + uint32_t * ds; + uint32_t * de; + uint32_t count; + uint32_t i; + +#if defined (__ARM_ARCH_7EM__) && defined(__VFP_FP__) && !defined(__SOFTFP__) + volatile uint32_t * pui32Cpacr = (uint32_t *) 0xE000ED88; + + /* Enable Coprocessor Access Control (CPAC) */ + *pui32Cpacr |= (0xF << 20); +#endif + + IntMasterDisable(); + + /* Final trim of device */ + SetupTrimDevice(); + + /* initiailize .bss to zero */ + bs = & __bss_start__; + be = & __bss_end__; + while (bs < be) { + *bs = 0; + bs++; + } + + /* relocate the .data section */ + dl = & __data_load__; + ds = & __data_start__; + de = & __data_end__; + if (dl != ds) { + while (ds < de) { + *ds = *dl; + dl++; + ds++; + } + } + + /* Run any constructors */ + count = (uint32_t)(__init_array_end - __init_array_start); + for (i = 0; i < count; i++) { + __init_array_start[i](); + } + + /* Copy from reset vector table into RAM vector table */ + memcpy(ramVectors, resetVectors, 16*4); + + /* fill remaining vectors with default handler */ + for (i=16; i < 50; i++) { + ramVectors[i] = (unsigned long)defaultHandler; + } + + /* Call the application's entry point. */ + main(); + + /* If we ever return signal Error */ + faultISR(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void __attribute__((naked)) resetISR(void) +{ + __asm__ __volatile__ ( + " movw r0, #:lower16:resetVectors\n" + " movt r0, #:upper16:resetVectors\n" + " ldr r0, [r0]\n" + " mov sp, r0\n" + " bl localProgramStart" + ); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +nmiISR(void) +{ + /* Enter an infinite loop. */ + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +faultISR(void) +{ + /* Enter an infinite loop. */ + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** + +static void +busFaultHandler(void) +{ + /* Enter an infinite loop. */ + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +defaultHandler(void) +{ + /* Enter an infinite loop. */ + while(1) + { + } +} + +//***************************************************************************** +// +// This function is called by __libc_fini_array which gets called when exit() +// is called. In order to support exit(), an empty _fini() stub function is +// required. +// +//***************************************************************************** +void _fini(void) +{ + /* Function body left empty intentionally */ +} diff --git a/examples/knx-cc1310/vscode/launch.json.example b/examples/knx-cc1310/vscode/launch.json.example new file mode 100644 index 0000000..aa5a3a0 --- /dev/null +++ b/examples/knx-cc1310/vscode/launch.json.example @@ -0,0 +1,20 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "name": "Cortex Debug", + "cwd": "${workspaceRoot}", + "executable": "./build/knx-cc1310", + "request": "launch", + "type": "cortex-debug", + "servertype": "jlink", + "serverpath": "/opt/SEGGER/JLink/JLinkGDBServerCLExe", + "device": "CC1310F128", + "interface": "jtag", + "runToMain": false, + } + ] +} diff --git a/examples/knx-linux-coupler/CMakeLists.txt b/examples/knx-linux-coupler/CMakeLists.txt index dfbb21a..7e36926 100644 --- a/examples/knx-linux-coupler/CMakeLists.txt +++ b/examples/knx-linux-coupler/CMakeLists.txt @@ -104,7 +104,8 @@ set(SOURCES ../../src/knx/rf_data_link_layer.h ../../src/knx/rf_medium_object.cpp ../../src/knx/rf_medium_object.h - ../../src/knx/rf_physical_layer.cpp + ../../src/knx/rf_physical_layer_cc1101.cpp + ../../src/knx/rf_physical_layer_cc1101.h ../../src/knx/rf_physical_layer.h ../../src/knx/router_object.cpp ../../src/knx/router_object.h diff --git a/examples/knx-linux/CMakeLists.txt b/examples/knx-linux/CMakeLists.txt index 40d21c8..c0ef749 100644 --- a/examples/knx-linux/CMakeLists.txt +++ b/examples/knx-linux/CMakeLists.txt @@ -104,7 +104,8 @@ set(SOURCES ../../src/knx/rf_data_link_layer.h ../../src/knx/rf_medium_object.cpp ../../src/knx/rf_medium_object.h - ../../src/knx/rf_physical_layer.cpp + ../../src/knx/rf_physical_layer_cc1101.cpp + ../../src/knx/rf_physical_layer_cc1101.h ../../src/knx/rf_physical_layer.h ../../src/knx/router_object.cpp ../../src/knx/router_object.h diff --git a/examples/knxPython/CMakeLists.txt b/examples/knxPython/CMakeLists.txt index 530629c..8b67bbe 100644 --- a/examples/knxPython/CMakeLists.txt +++ b/examples/knxPython/CMakeLists.txt @@ -106,7 +106,8 @@ pybind11_add_module(knx ../../src/knx/rf_data_link_layer.h ../../src/knx/rf_medium_object.cpp ../../src/knx/rf_medium_object.h - ../../src/knx/rf_physical_layer.cpp + ../../src/knx/rf_physical_layer_cc1101.cpp + ../../src/knx/rf_physical_layer_cc1101.h ../../src/knx/rf_physical_layer.h ../../src/knx/router_object.cpp ../../src/knx/router_object.h diff --git a/src/cc1310_platform.cpp b/src/cc1310_platform.cpp new file mode 100644 index 0000000..029cdf6 --- /dev/null +++ b/src/cc1310_platform.cpp @@ -0,0 +1,559 @@ +#ifdef DeviceFamily_CC13X0 + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include + +#include "SEGGER_RTT.h" + +#include "Board.h" + +#include "knx/bits.h" +#include "cc1310_platform.h" + +//#define printf(args...) (SEGGER_RTT_printf(0, args)) +#define PRINT_RTT + +static uint8_t serialNumber[6]; +// KNX_FLASH_SIZE shall be defined in CMakeLists.txt for example. It is also used in class Memory in memory.cpp +static uint8_t NVS_buffer[KNX_FLASH_SIZE]; + +static UART_Handle uart; + +static NVS_Handle nvsHandle; + +static ClockP_Handle clk0Handle; +static ClockP_Struct clk0Struct; +static volatile uint32_t msCounter = 0; + +static void clk0Fxn(uintptr_t arg0) +{ + msCounter++; +} + +static void setupClock() +{ + ClockP_Params clkParams; + ClockP_Params_init(&clkParams); + clkParams.period = 1000/ClockP_tickPeriod; + clkParams.startFlag = true; + ClockP_construct(&clk0Struct, (ClockP_Fxn)clk0Fxn, 1000/ClockP_tickPeriod, &clkParams); + clk0Handle = ClockP_handle(&clk0Struct); +} + +static void setupGPIO() +{ + /* Configure the LED and button pins */ + GPIO_setConfig(Board_GPIO_LED0, GPIO_CFG_OUT_STD | GPIO_CFG_OUT_LOW); + GPIO_setConfig(Board_GPIO_LED1, GPIO_CFG_OUT_STD | GPIO_CFG_OUT_LOW); + GPIO_setConfig(Board_GPIO_BUTTON0, GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING); + GPIO_setConfig(Board_GPIO_BUTTON1, GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING); +} + +static void setupUART() +{ + UART_Params uartParams; + UART_Params_init(&uartParams); + uartParams.writeDataMode = UART_DATA_BINARY; + uartParams.readDataMode = UART_DATA_BINARY; + uartParams.readReturnMode = UART_RETURN_FULL; + uartParams.readEcho = UART_ECHO_OFF; + uartParams.baudRate = 115200; + uart = UART_open(Board_UART0, &uartParams); + if (uart == NULL) + { + while(true) + {} + } + } + +static void setupNVS() +{ + NVS_Params nvsParams; + NVS_Params_init(&nvsParams); + nvsHandle = NVS_open(Board_NVSINTERNAL, &nvsParams); + if (nvsHandle == NULL) + { + println("NVS_open() failed."); + return; + } + + NVS_Attrs attrs; + NVS_getAttrs(nvsHandle, &attrs); + print("NVS flash size: "); println((int)attrs.regionSize); + print("NVS flash sector size: "); println((int)attrs.sectorSize); + + if (GPIO_read(Board_GPIO_BUTTON1) == 0) + { + println("Button1 is pressed. Erasing flash..."); + int_fast16_t result = NVS_erase(nvsHandle, 0, attrs.regionSize); + if (result != NVS_STATUS_SUCCESS) + { + print("Error erasing NVS, result: "); println(result); + } + else + { + println("NVS successfully erased."); + } + } +} + +void sleep(uint32_t sec) +{ + ClockP_sleep(sec); +} + +void usleep(uint32_t usec) +{ + ClockP_usleep(usec); +} + +uint32_t millis() +{ + // we use our own ms clock because the Os tick counter has counts 10us ticks and following calculation would not wrap correctly at 32bit boundary + //return Clock_getTicks() * (uint64_t) Clock_tickPeriod / 1000; // rtos + //return ClockP_getTicks( * (uint64_t) Clock_tickPeriod / 1000); //nortos + return msCounter; +} + +void delay(uint32_t ms) +{ + ClockP_usleep(ms * 1000); + //sleep(ms * (1000 / ClockP_tickPeriod)); //rtos + //sleepTicks(millis * 1000ULL / ClockP_tickPeriod); //nortos +} + +void delayMicroseconds (unsigned int howLong) +{ + ClockP_usleep(howLong); +} + +size_t write(uint8_t c) +{ +#if defined(PRINT_UART) + uint8_t buffer[1] = {c}; + return UART_write(uart, buffer, sizeof(buffer)); +#elif defined (PRINT_RTT) + return SEGGER_RTT_PutChar(0, (char)c); +#else + return 1; +#endif +} + +#if 0 +size_t write(const uint8_t *buffer, size_t size) +{ + size_t n = 0; + while (size--) + { + if (write(*buffer++)) + { + n++; + } + else + { + break; + } + } + return n; +} +#else +size_t write(const uint8_t *buffer, size_t size) +{ +#if defined(PRINT_UART) + return UART_write(uart, buffer, size); +#elif defined (PRINT_RTT) + return SEGGER_RTT_Write(0, buffer, size); +#else + return size; +#endif +} +#endif + +size_t write(const char *buffer, size_t size) +{ + return write((const uint8_t *)buffer, size); +} + +void print(const char* s) +{ + if (s == NULL) + { + return; + } + write(s, strlen(s)); +} +void print(char c) +{ + write(c); +} + +void printUint64(uint64_t value, int base = DEC) + { + char buf[8 * sizeof(uint64_t) + 1]; + char* str = &buf[sizeof(buf) - 1]; + *str = '\0'; + + uint64_t n = value; + do { + char c = n % base; + n /= base; + + *--str = c < 10 ? c + '0' : c + 'A' - 10; + } while (n > 0); + + print(str); +} + +void print(long long num, int base) +{ + if (base == 0) + { + write(num); + return; + } + else if (base == 10) + { + if (num < 0) + { + print('-'); + num = -num; + printUint64(num, 10); + return; + } + printUint64(num, 10); + return; + } + else + { + printUint64(num, base); + return; + } +} + +void print(unsigned long long num, int base) +{ + if (base == 0) + { + write(num); + return; + } + else + { + printUint64(num, base); + return; + } +} + +void print(unsigned char num, int base) +{ + print((unsigned long long)num, base); +} + +void print(int num, int base) +{ + print((long long)num, base); +} + +void print(unsigned int num, int base) +{ + print((unsigned long long)num, base); +} + +void print(long num, int base) +{ + print((long long)num, base); +} + +void print(unsigned long num, int base) +{ + print((unsigned long long)num, base); +} + +void printFloat(double number, uint8_t digits) +{ + if (std::isnan(number)) + { + print("nan"); + return; + } + if (std::isinf(number)) + { + print("inf"); + return; + } + if (number > 4294967040.0) + { + print("ovf"); // constant determined empirically + return; + } + if (number <-4294967040.0) + { + print("ovf"); // constant determined empirically + return; + } + + // Handle negative numbers + if (number < 0.0) + { + print('-'); + number = -number; + } + + // Round correctly so that print(1.999, 2) prints as "2.00" + double rounding = 0.5; + for (uint8_t i=0; i 0) + { + print('.'); + } + + // Extract digits from the remainder one at a time + while (digits-- > 0) + { + remainder *= 10.0; + unsigned int toPrint = (unsigned int)(remainder); + printUint64(toPrint); + remainder -= toPrint; + } +} + +void print(double num, int digits = 2) +{ + printFloat(num, digits); +} + +void println(void) +{ + print("\r\n"); +} + +void println(const char* s) +{ + print(s); + println(); +} +void println(char c) +{ + print(c); + println(); +} + +void println(unsigned char num, int base) +{ + print(num, base); + println(); +} + +void println(int num, int base) +{ + print(num, base); + println(); +} + +void println(unsigned int num, int base) +{ + print(num, base); + println(); +} + +void println(long num, int base) +{ + print(num, base); + println(); +} + +void println(unsigned long num, int base) +{ + print(num, base); + println(); +} + +void println(unsigned long long num, int base) +{ + printUint64(num, base); + println(); +} + +void println(double num, int digits = 2) +{ + print(num, digits); + println(); +} + +void println(double num) +{ + // default: print 10 digits + println(num, 10); +} + +uint32_t digitalRead(uint32_t dwPin) +{ + print("ignoring digitalRead: pin: ");print(dwPin); + println(", returning 0"); + return 0; +} + +void digitalWrite(unsigned long pin, unsigned long value) +{ + if (pin == Board_GPIO_LED0) + { + if (value > 0) + { + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); + } + else + { + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + } + } + else + { + print("dummy digitalWrite: pin: ");print(pin); + print(", value: ");println(value, HEX); + } +} + +void pinMode(unsigned long pin, unsigned long mode) +{ + print("ignoring pinMode: pin: ");print(pin); + print(", mode: ");println(mode, HEX); +} + +typedef void (*IsrFuncPtr)(); +static IsrFuncPtr gpioCallback; +static void gpioButtonFxn0(uint_least8_t index) +{ + gpioCallback(); +} + +void attachInterrupt(uint32_t pin, IsrFuncPtr callback, uint32_t mode) +{ + if (pin == Board_GPIO_BUTTON0) + { + gpioCallback = callback; + /* install Button callback */ + GPIO_setCallback(Board_GPIO_BUTTON0, gpioButtonFxn0); + + /* Enable interrupts */ + GPIO_enableInt(Board_GPIO_BUTTON0); + } + else + { + print("dummy attachInterrupt: pin: ");print(pin); + print(", mode: ");println(mode, HEX); + } +} + +CC1310Platform::CC1310Platform() +{ + // build serialNumber from IEEE MAC Address (MAC is 8 bytes, serialNumber 6 bytes only) + *(uint32_t*)(serialNumber+2) = HWREG(FCFG1_BASE+FCFG1_O_MAC_15_4_0) ^ HWREG(FCFG1_BASE+FCFG1_O_MAC_15_4_1); // make a 6 byte hash from 8 bytes +} + +CC1310Platform::~CC1310Platform() +{ +} + +void CC1310Platform::init() +{ + // TI Drivers init + // According to SDK docs it is safe to call them AFTER NoRTOS_Start() + // If RTOS is used and multiple thread use the same driver, then the init shall be performed before BIOS_Start() + GPIO_init(); + UART_init(); + NVS_init(); + + // Init GPIO + setupGPIO(); + + // Init UART + setupUART(); + + // tick Period on this controller 10us so we use our own millisecond clock + setupClock(); + + // Init flash + setupNVS(); +} + +uint8_t* CC1310Platform::getEepromBuffer(uint16_t size) +{ + if(size > KNX_FLASH_SIZE) + { + fatalError(); + } + + NVS_read(nvsHandle, 0, (void *) NVS_buffer, size); + + for (int i=0; i +#include +#include + +#include "knx/platform.h" + +class CC1310Platform : public Platform +{ + public: + CC1310Platform(); + virtual ~CC1310Platform(); + + void init(); + + // basic stuff + virtual void restart() final; + virtual void fatalError() final; + + virtual uint8_t* getEepromBuffer(uint16_t size) final; + virtual void commitToEeprom() final; +}; + +#endif //DeviceFamily_CC13X0 diff --git a/src/knx.h b/src/knx.h index d53f48e..003555f 100644 --- a/src/knx.h +++ b/src/knx.h @@ -142,7 +142,7 @@ BauSystemBDevice<--KnxFacade knx-->Platform @enduml -/** \page Classdiagramm KNX coupler +* \page Classdiagramm KNX coupler * This diagramm shows the most important classes of a KNX coupler. @startuml diff --git a/src/knx/bau27B0.h b/src/knx/bau27B0.h index 8659fac..4d8b7fc 100644 --- a/src/knx/bau27B0.h +++ b/src/knx/bau27B0.h @@ -5,7 +5,11 @@ #include "bau_systemB_device.h" #include "rf_medium_object.h" -#include "rf_physical_layer.h" +#if defined(DeviceFamily_CC13X0) + #include "rf_physical_layer_cc1310.h" +#else + #include "rf_physical_layer_cc1101.h" +#endif #include "rf_data_link_layer.h" #include "cemi_server.h" #include "cemi_server_object.h" diff --git a/src/knx/bau2920.h b/src/knx/bau2920.h index 539d07e..1b4a32e 100644 --- a/src/knx/bau2920.h +++ b/src/knx/bau2920.h @@ -5,7 +5,11 @@ #include "bau_systemB_coupler.h" #include "tpuart_data_link_layer.h" -#include "rf_physical_layer.h" +#if defined(DeviceFamily_CC13X0) + #include "rf_physical_layer_cc1310.h" +#else + #include "rf_physical_layer_cc1101.h" +#endif #include "rf_data_link_layer.h" #include "rf_medium_object.h" #include "cemi_server_object.h" diff --git a/src/knx/bits.cpp b/src/knx/bits.cpp index a1e5941..0a668f7 100644 --- a/src/knx/bits.cpp +++ b/src/knx/bits.cpp @@ -8,7 +8,7 @@ const uint8_t* popByte(uint8_t& b, const uint8_t* data) return data; } -void printHex(const char* suffix, const uint8_t *data, size_t length) +void printHex(const char* suffix, const uint8_t *data, size_t length, bool newline) { print(suffix); for (size_t i = 0; i < length; i++) { @@ -16,7 +16,10 @@ void printHex(const char* suffix, const uint8_t *data, size_t length) print(data[i], HEX); print(" "); } - println(); + if (newline) + { + println(); + } } const uint8_t* popWord(uint16_t& w, const uint8_t* data) @@ -135,3 +138,24 @@ uint16_t crc16Ccitt(uint8_t* input, uint16_t length) } return result & 0xffff; } + +uint16_t crc16Dnp(uint8_t* input, uint16_t length) +{ + // CRC-16-DNP + // generator polynomial = 2^16 + 2^13 + 2^12 + 2^11 + 2^10 + 2^8 + 2^6 + 2^5 + 2^2 + 2^0 + uint32_t pn = 0x13d65; // 1 0011 1101 0110 0101 + + // for much data, using a lookup table would be a way faster CRC calculation + uint32_t crc = 0; + for (uint32_t i = 0; i < length; i++) { + uint8_t bite = input[i] & 0xff; + for (uint8_t b = 8; b --> 0;) { + bool bit = ((bite >> b) & 1) == 1; + bool one = (crc >> 15 & 1) == 1; + crc <<= 1; + if (one ^ bit) + crc ^= pn; + } + } + return (~crc) & 0xffff; +} diff --git a/src/knx/bits.h b/src/knx/bits.h index bfaea22..7f24253 100644 --- a/src/knx/bits.h +++ b/src/knx/bits.h @@ -3,9 +3,25 @@ #include #include -#ifdef __linux__ +#if defined(__linux__) #include +#elif defined(ARDUINO_ARCH_SAMD) || defined(ARDUINO_ARCH_STM32) || defined (DeviceFamily_CC13X0) +#define getbyte(x,n) (*(((uint8_t*)&(x))+n)) +#define htons(x) ( (getbyte(x,0)<<8) | getbyte(x,1) ) +#define htonl(x) ( (getbyte(x,0)<<24) | (getbyte(x,1)<<16) | (getbyte(x,2)<<8) | getbyte(x,3) ) +#define ntohs(x) htons(x) +#define ntohl(x) htonl(x) +#endif +#if defined(ARDUINO_ARCH_SAMD) || defined(ARDUINO_ARCH_STM32) +#include +#elif defined(ARDUINO_ARCH_ESP8266) +#include +#include +#elif defined(ARDUINO_ARCH_ESP32) +#include +#include +#else // Non-Arduino platforms #define lowByte(val) ((val)&255) #define highByte(val) (((val) >> ((sizeof(val) - 1) << 3)) & 255) #define bitRead(val, bitno) (((val) >> (bitno)) & 1) @@ -33,22 +49,6 @@ void digitalWrite(uint32_t dwPin, uint32_t dwVal); uint32_t digitalRead(uint32_t dwPin); typedef void (*voidFuncPtr)(void); void attachInterrupt(uint32_t pin, voidFuncPtr callback, uint32_t mode); - -#elif ARDUINO_ARCH_SAMD || ARDUINO_ARCH_STM32 -#include - -#define getbyte(x,n) (*(((uint8_t*)&(x))+n)) -#define htons(x) ( (getbyte(x,0)<<8) | getbyte(x,1) ) -#define htonl(x) ( (getbyte(x,0)<<24) | (getbyte(x,1)<<16) | (getbyte(x,2)<<8) | getbyte(x,3) ) -#define ntohs(x) htons(x) -#define ntohl(x) htonl(x) - -#elif ARDUINO_ARCH_ESP8266 -#include -#include -#elif ARDUINO_ARCH_ESP32 -#include -#include #endif void print(const char[]); @@ -58,6 +58,7 @@ void print(int, int = DEC); void print(unsigned int, int = DEC); void print(long, int = DEC); void print(unsigned long, int = DEC); +void print(long long, int = DEC); void print(unsigned long long, int = DEC); void print(double); @@ -68,13 +69,12 @@ void println(int, int = DEC); void println(unsigned int, int = DEC); void println(long, int = DEC); void println(unsigned long, int = DEC); +void println(long long, int = DEC); void println(unsigned long long, int = DEC); void println(double); void println(void); - - -void printHex(const char* suffix, const uint8_t *data, size_t length); +void printHex(const char* suffix, const uint8_t *data, size_t length, bool newline = true); const uint8_t* popByte(uint8_t& b, const uint8_t* data); const uint8_t* popWord(uint16_t& w, const uint8_t* data); @@ -86,9 +86,9 @@ uint8_t* pushInt(uint32_t i, uint8_t* data); uint8_t* pushByteArray(const uint8_t* src, uint32_t size, uint8_t* data); uint16_t getWord(const uint8_t* data); uint32_t getInt(const uint8_t* data); -void printHex(const char* suffix, const uint8_t *data, size_t length); void sixBytesFromUInt64(uint64_t num, uint8_t* toByteArray); uint64_t sixBytesToUInt64(uint8_t* data); uint16_t crc16Ccitt(uint8_t* input, uint16_t length); +uint16_t crc16Dnp(uint8_t* input, uint16_t length); \ No newline at end of file diff --git a/src/knx/rf_data_link_layer.cpp b/src/knx/rf_data_link_layer.cpp index 7dedd8f..7765736 100644 --- a/src/knx/rf_data_link_layer.cpp +++ b/src/knx/rf_data_link_layer.cpp @@ -1,7 +1,11 @@ #include "config.h" #ifdef USE_RF -#include "rf_physical_layer.h" +#if defined(DeviceFamily_CC13X0) + #include "rf_physical_layer_cc1310.h" +#else + #include "rf_physical_layer_cc1101.h" +#endif #include "rf_data_link_layer.h" #include "bits.h" @@ -81,27 +85,6 @@ RfDataLinkLayer::RfDataLinkLayer(DeviceObject& devObj, RfMediumObject& rfMediumO { } -uint16_t RfDataLinkLayer::calcCrcRF(uint8_t* buffer, uint32_t offset, uint32_t len) -{ - // CRC-16-DNP - // generator polynomial = 2^16 + 2^13 + 2^12 + 2^11 + 2^10 + 2^8 + 2^6 + 2^5 + 2^2 + 2^0 - uint32_t pn = 0x13d65; // 1 0011 1101 0110 0101 - - // for much data, using a lookup table would be a way faster CRC calculation - uint32_t crc = 0; - for (uint32_t i = offset; i < offset + len; i++) { - uint8_t bite = buffer[i] & 0xff; - for (uint8_t b = 8; b --> 0;) { - bool bit = ((bite >> b) & 1) == 1; - bool one = (crc >> 15 & 1) == 1; - crc <<= 1; - if (one ^ bit) - crc ^= pn; - } - } - return (~crc) & 0xffff; -} - void RfDataLinkLayer::frameBytesReceived(uint8_t* rfPacketBuf, uint16_t length) { // RF data link layer frame format @@ -115,16 +98,24 @@ void RfDataLinkLayer::frameBytesReceived(uint8_t* rfPacketBuf, uint16_t length) return; } +#if defined(DeviceFamily_CC13X0) + // Small optimization: + // We do not calculate the CRC16-DNP again for the first block. + // It was already done in the CC13x0 RX driver during reception. + // Also the two fixed bytes 0x44 and 0xFF are also there. + // So if we get here we can assume a valid block 1 +#else // CRC16-DNP of first block is always located here uint16_t block1Crc = rfPacketBuf[10] << 8 | rfPacketBuf[11]; - + // If the checksum was ok and the other // two constant header bytes match the KNX-RF spec. (C-field: 0x44 and ESC-field: 0xFF)... // then we seem to have a valid first block of an KNX RF frame. // The first block basically contains the RF-info field and the KNX SN/Domain address. if ((rfPacketBuf[1] == 0x44) && (rfPacketBuf[2] == 0xFF) && - (calcCrcRF(rfPacketBuf, 0, 10) == block1Crc)) + (crc16Dnp(rfPacketBuf, 10) == block1Crc)) +#endif { // bytes left from the remaining block(s) uint16_t bytesLeft = length - 12; @@ -147,7 +138,7 @@ void RfDataLinkLayer::frameBytesReceived(uint8_t* rfPacketBuf, uint16_t length) { // Get CRC16 from end of the block blockCrc = pRfPacketBuf[16] << 8 | pRfPacketBuf[17]; - if (calcCrcRF(pRfPacketBuf, 0, 16) == blockCrc) + if (crc16Dnp(pRfPacketBuf, 16) == blockCrc) { // Copy only the payload without the checksums memcpy(pBuffer, pRfPacketBuf, 16); @@ -165,7 +156,7 @@ void RfDataLinkLayer::frameBytesReceived(uint8_t* rfPacketBuf, uint16_t length) // Now process the last block blockCrc = pRfPacketBuf[bytesLeft - 2] << 8 | pRfPacketBuf[bytesLeft - 1]; - crcOk = crcOk && (calcCrcRF(&pRfPacketBuf[0], 0, bytesLeft -2) == blockCrc); + crcOk = crcOk && (crc16Dnp(&pRfPacketBuf[0], bytesLeft -2) == blockCrc); // If all checksums were ok, then... if (crcOk) @@ -286,7 +277,7 @@ void RfDataLinkLayer::fillRfFrame(CemiFrame& frame, uint8_t* data) // Generate CRC16-DNP over the first block of data pushByteArray(frame.rfSerialOrDoA(), 6, &data[4]); - crc = calcCrcRF(&data[0], 0, 10); + crc = crc16Dnp(&data[0], 10); pushWord(crc, &data[10]); // Put the complete KNX telegram into a temporary buffer @@ -300,7 +291,7 @@ void RfDataLinkLayer::fillRfFrame(CemiFrame& frame, uint8_t* data) while (bytesLeft > 16) { memcpy(pData, pBuffer, 16); - crc = calcCrcRF(pData, 0, 16); + crc = crc16Dnp(pData, 16); pushWord(crc, &pData[16]); pBuffer += 16; @@ -311,7 +302,7 @@ void RfDataLinkLayer::fillRfFrame(CemiFrame& frame, uint8_t* data) // Copy remaining bytes of last block. Could be less than 16 bytes memcpy(pData, pBuffer, bytesLeft); // And add last CRC - crc = calcCrcRF(pData, 0, bytesLeft); + crc = crc16Dnp(pData, bytesLeft); pushWord(crc, &pData[bytesLeft]); } diff --git a/src/knx/rf_data_link_layer.h b/src/knx/rf_data_link_layer.h index 849d12a..cdbd9dc 100644 --- a/src/knx/rf_data_link_layer.h +++ b/src/knx/rf_data_link_layer.h @@ -8,13 +8,15 @@ #define MAX_KNX_TELEGRAM_SIZE 263 -class RfPhysicalLayer; class RfMediumObject; class RfDataLinkLayer : public DataLinkLayer { - friend class RfPhysicalLayer; - +#if defined(DeviceFamily_CC13X0) + friend class RfPhysicalLayerCC1310; +#else + friend class RfPhysicalLayerCC1101; +#endif using DataLinkLayer::_deviceObject; using DataLinkLayer::_platform; @@ -49,15 +51,17 @@ class RfDataLinkLayer : public DataLinkLayer } _tx_queue; RfMediumObject& _rfMediumObj; - RfPhysicalLayer _rfPhy; - +#if defined(DeviceFamily_CC13X0) + RfPhysicalLayerCC1310 _rfPhy; +#else + RfPhysicalLayerCC1101 _rfPhy; +#endif void fillRfFrame(CemiFrame& frame, uint8_t* data); void addFrameTxQueue(CemiFrame& frame); bool isTxQueueEmpty(); void loadNextTxFrame(uint8_t** sendBuffer, uint16_t* sendBufferLength); bool sendFrame(CemiFrame& frame); void frameBytesReceived(uint8_t* buffer, uint16_t length); - uint16_t calcCrcRF(uint8_t* buffer, uint32_t offset, uint32_t len); }; #endif diff --git a/src/knx/rf_physical_layer.h b/src/knx/rf_physical_layer.h index ceb3196..6b2828b 100644 --- a/src/knx/rf_physical_layer.h +++ b/src/knx/rf_physical_layer.h @@ -7,237 +7,22 @@ #include "platform.h" -/*----------------------------------[standard]--------------------------------*/ -#define CC1101_TIMEOUT 2000 // Time to wait for a response from CC1101 - -#define RX_PACKET_TIMEOUT 20 // Wait 20ms for packet reception to complete -#define TX_PACKET_TIMEOUT 20 // Wait 20ms for packet reception to complete - -#ifdef __linux__ // Linux Platform -extern void delayMicroseconds (unsigned int howLong); -#endif - -/*----------------------[CC1101 - misc]---------------------------------------*/ -#define CRYSTAL_FREQUENCY 26000000 -#define CFG_REGISTER 0x2F //47 registers -#define FIFOBUFFER 0x42 //size of Fifo Buffer +2 for rssi and lqi -#define RSSI_OFFSET_868MHZ 0x4E //dec = 74 -#define TX_RETRIES_MAX 0x05 //tx_retries_max -#define ACK_TIMEOUT 250 //ACK timeout in ms -#define CC1101_COMPARE_REGISTER 0x00 //register compare 0=no compare 1=compare -#define BROADCAST_ADDRESS 0x00 //broadcast address -#define CC1101_FREQ_315MHZ 0x01 -#define CC1101_FREQ_434MHZ 0x02 -#define CC1101_FREQ_868MHZ 0x03 -#define CC1101_FREQ_915MHZ 0x04 -#define CC1101_TEMP_ADC_MV 3.225 //3.3V/1023 . mV pro digit -#define CC1101_TEMP_CELS_CO 2.47 //Temperature coefficient 2.47mV per Grad Celsius - -/*---------------------------[CC1101 - R/W offsets]---------------------------*/ -#define WRITE_SINGLE_BYTE 0x00 -#define WRITE_BURST 0x40 -#define READ_SINGLE_BYTE 0x80 -#define READ_BURST 0xC0 -/*---------------------------[END R/W offsets]--------------------------------*/ - -/*------------------------[CC1101 - FIFO commands]----------------------------*/ -#define TXFIFO_BURST 0x7F //write burst only -#define TXFIFO_SINGLE_BYTE 0x3F //write single only -#define RXFIFO_BURST 0xFF //read burst only -#define RXFIFO_SINGLE_BYTE 0xBF //read single only -#define PATABLE_BURST 0x7E //power control read/write -#define PATABLE_SINGLE_BYTE 0xFE //power control read/write -/*---------------------------[END FIFO commands]------------------------------*/ - -/*----------------------[CC1101 - config register]----------------------------*/ -#define IOCFG2 0x00 // GDO2 output pin configuration -#define IOCFG1 0x01 // GDO1 output pin configuration -#define IOCFG0 0x02 // GDO0 output pin configuration -#define FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds -#define SYNC1 0x04 // Sync word, high byte -#define SYNC0 0x05 // Sync word, low byte -#define PKTLEN 0x06 // Packet length -#define PKTCTRL1 0x07 // Packet automation control -#define PKTCTRL0 0x08 // Packet automation control -#define DEVADDR 0x09 // Device address -#define CHANNR 0x0A // Channel number -#define FSCTRL1 0x0B // Frequency synthesizer control -#define FSCTRL0 0x0C // Frequency synthesizer control -#define FREQ2 0x0D // Frequency control word, high byte -#define FREQ1 0x0E // Frequency control word, middle byte -#define FREQ0 0x0F // Frequency control word, low byte -#define MDMCFG4 0x10 // Modem configuration -#define MDMCFG3 0x11 // Modem configuration -#define MDMCFG2 0x12 // Modem configuration -#define MDMCFG1 0x13 // Modem configuration -#define MDMCFG0 0x14 // Modem configuration -#define DEVIATN 0x15 // Modem deviation setting -#define MCSM2 0x16 // Main Radio Cntrl State Machine config -#define MCSM1 0x17 // Main Radio Cntrl State Machine config -#define MCSM0 0x18 // Main Radio Cntrl State Machine config -#define FOCCFG 0x19 // Frequency Offset Compensation config -#define BSCFG 0x1A // Bit Synchronization configuration -#define AGCCTRL2 0x1B // AGC control -#define AGCCTRL1 0x1C // AGC control -#define AGCCTRL0 0x1D // AGC control -#define WOREVT1 0x1E // High byte Event 0 timeout -#define WOREVT0 0x1F // Low byte Event 0 timeout -#define WORCTRL 0x20 // Wake On Radio control -#define FREND1 0x21 // Front end RX configuration -#define FREND0 0x22 // Front end TX configuration -#define FSCAL3 0x23 // Frequency synthesizer calibration -#define FSCAL2 0x24 // Frequency synthesizer calibration -#define FSCAL1 0x25 // Frequency synthesizer calibration -#define FSCAL0 0x26 // Frequency synthesizer calibration -#define RCCTRL1 0x27 // RC oscillator configuration -#define RCCTRL0 0x28 // RC oscillator configuration -#define FSTEST 0x29 // Frequency synthesizer cal control -#define PTEST 0x2A // Production test -#define AGCTEST 0x2B // AGC test -#define TEST2 0x2C // Various test settings -#define TEST1 0x2D // Various test settings -#define TEST0 0x2E // Various test settings -/*-------------------------[END config register]------------------------------*/ - -/*------------------------[CC1101-command strobes]----------------------------*/ -#define SRES 0x30 // Reset chip -#define SFSTXON 0x31 // Enable/calibrate freq synthesizer -#define SXOFF 0x32 // Turn off crystal oscillator. -#define SCAL 0x33 // Calibrate freq synthesizer & disable -#define SRX 0x34 // Enable RX. -#define STX 0x35 // Enable TX. -#define SIDLE 0x36 // Exit RX / TX -#define SAFC 0x37 // AFC adjustment of freq synthesizer -#define SWOR 0x38 // Start automatic RX polling sequence -#define SPWD 0x39 // Enter pwr down mode when CSn goes hi -#define SFRX 0x3A // Flush the RX FIFO buffer. -#define SFTX 0x3B // Flush the TX FIFO buffer. -#define SWORRST 0x3C // Reset real time clock. -#define SNOP 0x3D // No operation. -/*-------------------------[END command strobes]------------------------------*/ - -/*----------------------[CC1101 - status register]----------------------------*/ -#define PARTNUM 0xF0 // Part number -#define VERSION 0xF1 // Current version number -#define FREQEST 0xF2 // Frequency offset estimate -#define LQI 0xF3 // Demodulator estimate for link quality -#define RSSI 0xF4 // Received signal strength indication -#define MARCSTATE 0xF5 // Control state machine state -#define WORTIME1 0xF6 // High byte of WOR timer -#define WORTIME0 0xF7 // Low byte of WOR timer -#define PKTSTATUS 0xF8 // Current GDOx status and packet status -#define VCO_VC_DAC 0xF9 // Current setting from PLL cal module -#define TXBYTES 0xFA // Underflow and # of bytes in TXFIFO -#define RXBYTES 0xFB // Overflow and # of bytes in RXFIFO -#define RCCTRL1_STATUS 0xFC //Last RC Oscillator Calibration Result -#define RCCTRL0_STATUS 0xFD //Last RC Oscillator Calibration Result -//--------------------------[END status register]------------------------------- - -/*----------------------[CC1101 - Main Radio Control State Machine states]-----*/ -#define MARCSTATE_BITMASK 0x1F -#define MARCSTATE_SLEEP 0x00 -#define MARCSTATE_IDLE 0x01 -#define MARCSTATE_XOFF 0x02 -#define MARCSTATE_VCOON_MC 0x03 -#define MARCSTATE_REGON_MC 0x04 -#define MARCSTATE_MANCAL 0x05 -#define MARCSTATE_VCOON 0x06 -#define MARCSTATE_REGON 0x07 -#define MARCSTATE_STARTCAL 0x08 -#define MARCSTATE_BWBOOST 0x09 -#define MARCSTATE_FS_LOCK 0x0A -#define MARCSTATE_IFADCON 0x0B -#define MARCSTATE_ENDCAL 0x0C -#define MARCSTATE_RX 0x0D -#define MARCSTATE_RX_END 0x0E -#define MARCSTATE_RX_RST 0x0F -#define MARCSTATE_TXRX_SWITCH 0x10 -#define MARCSTATE_RXFIFO_OVERFLOW 0x11 -#define MARCSTATE_FSTXON 0x12 -#define MARCSTATE_TX 0x13 -#define MARCSTATE_TX_END 0x14 -#define MARCSTATE_RXTX_SWITCH 0x15 -#define MARCSTATE_TXFIFO_UNDERFLOW 0x16 - -// Chip Status Byte -// Bit fields in the chip status byte -#define CHIPSTATUS_CHIP_RDYn_BITMASK 0x80 -#define CHIPSTATUS_STATE_BITMASK 0x70 -#define CHIPSTATUS_FIFO_BYTES_AVAILABLE_BITMASK 0x0F -// Chip states - #define CHIPSTATUS_STATE_IDLE 0x00 - #define CHIPSTATUS_STATE_RX 0x10 - #define CHIPSTATUS_STATE_TX 0x20 - #define CHIPSTATUS_STATE_FSTXON 0x30 - #define CHIPSTATUS_STATE_CALIBRATE 0x40 - #define CHIPSTATUS_STATE_SETTLING 0x50 - #define CHIPSTATUS_STATE_RX_OVERFLOW 0x60 - #define CHIPSTATUS_STATE_TX_UNDERFLOW 0x70 - -// loop states -#define RX_START 0 -#define RX_ACTIVE 1 -#define RX_END 2 -#define TX_START 3 -#define TX_ACTIVE 4 -#define TX_END 5 +// Calculate the real packet size out of the L-field of FT3 frame data. See KNX-RF spec. 3.2.5 Data Link Layer frame format +#define PACKET_SIZE(lField) ((((lField - 10 /*size of first pkt*/))/16 + 2 /*CRC in first pkt */) * 2 /*to bytes*/ +lField + 1 /*size of len byte*/) class RfDataLinkLayer; class RfPhysicalLayer { public: - RfPhysicalLayer(RfDataLinkLayer& rfDataLinkLayer, Platform& platform); + RfPhysicalLayer(RfDataLinkLayer& rfDataLinkLayer, Platform& platform) + : _rfDataLinkLayer(rfDataLinkLayer), _platform(platform) {} - bool InitChip(); - void showRegisterSettings(); - void stopChip(); - void loop(); - - private: - // Table for encoding 4-bit data into a 8-bit Manchester encoding. - static const uint8_t manchEncodeTab[16]; - // Table for decoding 4-bit Manchester encoded data into 2-bit - static const uint8_t manchDecodeTab[16]; - - static const uint8_t cc1101_2FSK_32_7_kb[CFG_REGISTER]; - static const uint8_t paTablePower868[8]; - - void manchEncode(uint8_t *uncodedData, uint8_t *encodedData); - bool manchDecode(uint8_t *encodedData, uint8_t *decodedData); - - void powerDownCC1101(); - void setOutputPowerLevel(int8_t dBm); - - uint16_t packetSize (uint8_t lField); - - uint8_t sIdle(); - uint8_t sReceive(); - - void spiWriteRegister(uint8_t spi_instr, uint8_t value); - uint8_t spiReadRegister(uint8_t spi_instr); - uint8_t spiWriteStrobe(uint8_t spi_instr); - void spiReadBurst(uint8_t spi_instr, uint8_t *pArr, uint8_t len); - void spiWriteBurst(uint8_t spi_instr, const uint8_t *pArr, uint8_t len); - - uint8_t _loopState = RX_START; - - bool syncStart = false; - bool packetStart = true; - bool fixedLengthMode = false; - uint8_t *sendBuffer {0}; - uint16_t sendBufferLength {0}; - uint8_t packet[512]; - uint8_t buffer[sizeof(packet)*2]; // We need twice the space due to manchester encoding - uint8_t* pByteIndex = &buffer[0]; - uint16_t pktLen {0}; - uint16_t bytesLeft = {0}; - uint8_t statusGDO0 {0}; - uint8_t statusGDO2 {0}; - uint8_t prevStatusGDO0 {0}; // for edge detection during polling - uint8_t prevStatusGDO2 {0}; // for edge detection during polling - uint32_t packetStartTime {0}; + virtual bool InitChip() = 0; + virtual void stopChip() = 0; + virtual void loop() = 0; + protected: RfDataLinkLayer& _rfDataLinkLayer; Platform& _platform; }; diff --git a/src/knx/rf_physical_layer.cpp b/src/knx/rf_physical_layer_cc1101.cpp similarity index 93% rename from src/knx/rf_physical_layer.cpp rename to src/knx/rf_physical_layer_cc1101.cpp index 2881685..a2ee581 100644 --- a/src/knx/rf_physical_layer.cpp +++ b/src/knx/rf_physical_layer_cc1101.cpp @@ -1,7 +1,9 @@ +#ifndef DeviceFamily_CC13X0 + #include "config.h" #ifdef USE_RF -#include "rf_physical_layer.h" +#include "rf_physical_layer_cc1101.h" #include "rf_data_link_layer.h" #include "bits.h" @@ -15,7 +17,7 @@ #define ABS(x) ((x > 0) ? (x) : (-x)) // Table for encoding 4-bit data into a 8-bit Manchester encoding. -const uint8_t RfPhysicalLayer::manchEncodeTab[16] = {0xAA, // 0x0 Manchester encoded +const uint8_t RfPhysicalLayerCC1101::manchEncodeTab[16] = {0xAA, // 0x0 Manchester encoded 0xA9, // 0x1 Manchester encoded 0xA6, // 0x2 Manchester encoded 0xA5, // 0x3 Manchester encoded @@ -34,7 +36,7 @@ const uint8_t RfPhysicalLayer::manchEncodeTab[16] = {0xAA, // 0x0 Manchester // Table for decoding 4-bit Manchester encoded data into 2-bit // data. 0xFF indicates invalid Manchester encoding -const uint8_t RfPhysicalLayer::manchDecodeTab[16] = {0xFF, // Manchester encoded 0x0 decoded +const uint8_t RfPhysicalLayerCC1101::manchDecodeTab[16] = {0xFF, // Manchester encoded 0x0 decoded 0xFF, // Manchester encoded 0x1 decoded 0xFF, // Manchester encoded 0x2 decoded 0xFF, // Manchester encoded 0x3 decoded @@ -78,7 +80,7 @@ const uint8_t RfPhysicalLayer::manchDecodeTab[16] = {0xFF, // Manchester encode // Device address = 0 // GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet // GDO2 signal selection = ( 0) Asserts when RX FiFO threshold -const uint8_t RfPhysicalLayer::cc1101_2FSK_32_7_kb[CFG_REGISTER] = { +const uint8_t RfPhysicalLayerCC1101::cc1101_2FSK_32_7_kb[CFG_REGISTER] = { 0x00, // IOCFG2 GDO2 Output Pin Configuration 0x2E, // IOCFG1 GDO1 Output Pin Configuration 0x06, // IOCFG0 GDO0 Output Pin Configuration @@ -129,15 +131,14 @@ const uint8_t RfPhysicalLayer::cc1101_2FSK_32_7_kb[CFG_REGISTER] = { }; //Patable index: -30 -20- -15 -10 0 5 7 10 dBm -const uint8_t RfPhysicalLayer::paTablePower868[8] = {0x03,0x17,0x1D,0x26,0x50,0x86,0xCD,0xC0}; +const uint8_t RfPhysicalLayerCC1101::paTablePower868[8] = {0x03,0x17,0x1D,0x26,0x50,0x86,0xCD,0xC0}; -RfPhysicalLayer::RfPhysicalLayer(RfDataLinkLayer& rfDataLinkLayer, Platform& platform) - : _rfDataLinkLayer(rfDataLinkLayer), - _platform(platform) +RfPhysicalLayerCC1101::RfPhysicalLayerCC1101(RfDataLinkLayer& rfDataLinkLayer, Platform& platform) + : RfPhysicalLayer(rfDataLinkLayer, platform) { } -void RfPhysicalLayer::manchEncode(uint8_t *uncodedData, uint8_t *encodedData) +void RfPhysicalLayerCC1101::manchEncode(uint8_t *uncodedData, uint8_t *encodedData) { uint8_t data0, data1; @@ -150,7 +151,7 @@ void RfPhysicalLayer::manchEncode(uint8_t *uncodedData, uint8_t *encodedData) *(encodedData + 1) = manchEncodeTab[data0]; } -bool RfPhysicalLayer::manchDecode(uint8_t *encodedData, uint8_t *decodedData) +bool RfPhysicalLayerCC1101::manchDecode(uint8_t *encodedData, uint8_t *decodedData) { uint8_t data0, data1, data2, data3; @@ -174,7 +175,7 @@ bool RfPhysicalLayer::manchDecode(uint8_t *encodedData, uint8_t *decodedData) return true; } -uint8_t RfPhysicalLayer::sIdle() +uint8_t RfPhysicalLayerCC1101::sIdle() { uint8_t marcState; uint32_t timeStart; @@ -200,7 +201,7 @@ uint8_t RfPhysicalLayer::sIdle() return true; } -uint8_t RfPhysicalLayer::sReceive() +uint8_t RfPhysicalLayerCC1101::sReceive() { uint8_t marcState; uint32_t timeStart; @@ -226,7 +227,7 @@ uint8_t RfPhysicalLayer::sReceive() return true; } -void RfPhysicalLayer::spiWriteRegister(uint8_t spi_instr, uint8_t value) +void RfPhysicalLayerCC1101::spiWriteRegister(uint8_t spi_instr, uint8_t value) { uint8_t tbuf[2] = {0}; tbuf[0] = spi_instr | WRITE_SINGLE_BYTE; @@ -237,7 +238,7 @@ void RfPhysicalLayer::spiWriteRegister(uint8_t spi_instr, uint8_t value) digitalWrite(SPI_SS_PIN, HIGH); } -uint8_t RfPhysicalLayer::spiReadRegister(uint8_t spi_instr) +uint8_t RfPhysicalLayerCC1101::spiReadRegister(uint8_t spi_instr) { uint8_t value; uint8_t rbuf[2] = {0}; @@ -252,7 +253,7 @@ uint8_t RfPhysicalLayer::spiReadRegister(uint8_t spi_instr) return value; } -uint8_t RfPhysicalLayer::spiWriteStrobe(uint8_t spi_instr) +uint8_t RfPhysicalLayerCC1101::spiWriteStrobe(uint8_t spi_instr) { uint8_t tbuf[1] = {0}; tbuf[0] = spi_instr; @@ -263,7 +264,7 @@ uint8_t RfPhysicalLayer::spiWriteStrobe(uint8_t spi_instr) return tbuf[0]; } -void RfPhysicalLayer::spiReadBurst(uint8_t spi_instr, uint8_t *pArr, uint8_t len) +void RfPhysicalLayerCC1101::spiReadBurst(uint8_t spi_instr, uint8_t *pArr, uint8_t len) { uint8_t rbuf[len + 1]; rbuf[0] = spi_instr | READ_BURST; @@ -277,7 +278,7 @@ void RfPhysicalLayer::spiReadBurst(uint8_t spi_instr, uint8_t *pArr, uint8_t len } } -void RfPhysicalLayer::spiWriteBurst(uint8_t spi_instr, const uint8_t *pArr, uint8_t len) +void RfPhysicalLayerCC1101::spiWriteBurst(uint8_t spi_instr, const uint8_t *pArr, uint8_t len) { uint8_t tbuf[len + 1]; tbuf[0] = spi_instr | WRITE_BURST; @@ -291,7 +292,7 @@ void RfPhysicalLayer::spiWriteBurst(uint8_t spi_instr, const uint8_t *pArr, uint digitalWrite(SPI_SS_PIN, HIGH); } -void RfPhysicalLayer::powerDownCC1101() +void RfPhysicalLayerCC1101::powerDownCC1101() { // Set IDLE state first sIdle(); @@ -300,7 +301,7 @@ void RfPhysicalLayer::powerDownCC1101() spiWriteStrobe(SPWD); } -void RfPhysicalLayer::setOutputPowerLevel(int8_t dBm) +void RfPhysicalLayerCC1101::setOutputPowerLevel(int8_t dBm) { uint8_t pa = 0xC0; @@ -316,7 +317,7 @@ void RfPhysicalLayer::setOutputPowerLevel(int8_t dBm) spiWriteRegister(FREND0, pa); } -bool RfPhysicalLayer::InitChip() +bool RfPhysicalLayerCC1101::InitChip() { // Setup SPI and GPIOs _platform.setupSpi(); @@ -382,14 +383,14 @@ bool RfPhysicalLayer::InitChip() return true; } -void RfPhysicalLayer::stopChip() +void RfPhysicalLayerCC1101::stopChip() { powerDownCC1101(); _platform.closeSpi(); } -void RfPhysicalLayer::showRegisterSettings() +void RfPhysicalLayerCC1101::showRegisterSettings() { uint8_t config_reg_verify[CFG_REGISTER]; uint8_t Patable_verify[CFG_REGISTER]; @@ -404,29 +405,7 @@ void RfPhysicalLayer::showRegisterSettings() printHex("", Patable_verify, 8); } -uint16_t RfPhysicalLayer::packetSize (uint8_t lField) -{ - uint16_t nrBytes; - uint8_t nrBlocks; - - // The 2 first blocks contains 25 bytes when excluding CRC and the L-field - // The other blocks contains 16 bytes when excluding the CRC-fields - // Less than 26 (15 + 10) - if ( lField < 26 ) - nrBlocks = 2; - else - nrBlocks = (((lField - 26) / 16) + 3); - - // Add all extra fields, excluding the CRC fields - nrBytes = lField + 1; - - // Add the CRC fields, each block has 2 CRC bytes - nrBytes += (2 * nrBlocks); - - return nrBytes; -} - -void RfPhysicalLayer::loop() +void RfPhysicalLayerCC1101::loop() { switch (_loopState) { @@ -452,7 +431,7 @@ void RfPhysicalLayer::loop() _rfDataLinkLayer.loadNextTxFrame(&sendBuffer, &sendBufferLength); // Calculate total number of bytes in the KNX RF packet from L-field - pktLen = packetSize(sendBuffer[0]); + pktLen = PACKET_SIZE(sendBuffer[0]); // Check for valid length if ((pktLen == 0) || (pktLen > 290)) { @@ -658,7 +637,7 @@ void RfPhysicalLayer::loop() break; } // Get bytes to receive from L-field, multiply by 2 because of manchester code - pktLen = 2 * packetSize(packet[0]); + pktLen = 2 * PACKET_SIZE(packet[0]); // - Length mode - if (pktLen < 256) @@ -751,7 +730,7 @@ void RfPhysicalLayer::loop() case RX_END: { - uint16_t pLen = packetSize(packet[0]); + uint16_t pLen = PACKET_SIZE(packet[0]); // Decode the first block (always 10 bytes + 2 bytes CRC) bool decodeOk = true; for (uint16_t i = 1; i < pLen; i++) @@ -776,4 +755,6 @@ void RfPhysicalLayer::loop() } } -#endif +#endif // USE_RF + +#endif // DeviceFamily_CC13X0 diff --git a/src/knx/rf_physical_layer_cc1101.h b/src/knx/rf_physical_layer_cc1101.h new file mode 100644 index 0000000..ff5e7ab --- /dev/null +++ b/src/knx/rf_physical_layer_cc1101.h @@ -0,0 +1,244 @@ +#pragma once + +#ifndef DeviceFamily_CC13X0 + +#include "config.h" +#ifdef USE_RF + +#include + +#include "rf_physical_layer.h" + +/*----------------------------------[standard]--------------------------------*/ +#define CC1101_TIMEOUT 2000 // Time to wait for a response from CC1101 + +#define RX_PACKET_TIMEOUT 20 // Wait 20ms for packet reception to complete +#define TX_PACKET_TIMEOUT 20 // Wait 20ms for packet reception to complete + +#ifdef __linux__ // Linux Platform +extern void delayMicroseconds (unsigned int howLong); +#endif + +/*----------------------[CC1101 - misc]---------------------------------------*/ +#define CRYSTAL_FREQUENCY 26000000 +#define CFG_REGISTER 0x2F //47 registers +#define FIFOBUFFER 0x42 //size of Fifo Buffer +2 for rssi and lqi +#define RSSI_OFFSET_868MHZ 0x4E //dec = 74 +#define TX_RETRIES_MAX 0x05 //tx_retries_max +#define ACK_TIMEOUT 250 //ACK timeout in ms +#define CC1101_COMPARE_REGISTER 0x00 //register compare 0=no compare 1=compare +#define BROADCAST_ADDRESS 0x00 //broadcast address +#define CC1101_FREQ_315MHZ 0x01 +#define CC1101_FREQ_434MHZ 0x02 +#define CC1101_FREQ_868MHZ 0x03 +#define CC1101_FREQ_915MHZ 0x04 +#define CC1101_TEMP_ADC_MV 3.225 //3.3V/1023 . mV pro digit +#define CC1101_TEMP_CELS_CO 2.47 //Temperature coefficient 2.47mV per Grad Celsius + +/*---------------------------[CC1101 - R/W offsets]---------------------------*/ +#define WRITE_SINGLE_BYTE 0x00 +#define WRITE_BURST 0x40 +#define READ_SINGLE_BYTE 0x80 +#define READ_BURST 0xC0 +/*---------------------------[END R/W offsets]--------------------------------*/ + +/*------------------------[CC1101 - FIFO commands]----------------------------*/ +#define TXFIFO_BURST 0x7F //write burst only +#define TXFIFO_SINGLE_BYTE 0x3F //write single only +#define RXFIFO_BURST 0xFF //read burst only +#define RXFIFO_SINGLE_BYTE 0xBF //read single only +#define PATABLE_BURST 0x7E //power control read/write +#define PATABLE_SINGLE_BYTE 0xFE //power control read/write +/*---------------------------[END FIFO commands]------------------------------*/ + +/*----------------------[CC1101 - config register]----------------------------*/ +#define IOCFG2 0x00 // GDO2 output pin configuration +#define IOCFG1 0x01 // GDO1 output pin configuration +#define IOCFG0 0x02 // GDO0 output pin configuration +#define FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds +#define SYNC1 0x04 // Sync word, high byte +#define SYNC0 0x05 // Sync word, low byte +#define PKTLEN 0x06 // Packet length +#define PKTCTRL1 0x07 // Packet automation control +#define PKTCTRL0 0x08 // Packet automation control +#define DEVADDR 0x09 // Device address +#define CHANNR 0x0A // Channel number +#define FSCTRL1 0x0B // Frequency synthesizer control +#define FSCTRL0 0x0C // Frequency synthesizer control +#define FREQ2 0x0D // Frequency control word, high byte +#define FREQ1 0x0E // Frequency control word, middle byte +#define FREQ0 0x0F // Frequency control word, low byte +#define MDMCFG4 0x10 // Modem configuration +#define MDMCFG3 0x11 // Modem configuration +#define MDMCFG2 0x12 // Modem configuration +#define MDMCFG1 0x13 // Modem configuration +#define MDMCFG0 0x14 // Modem configuration +#define DEVIATN 0x15 // Modem deviation setting +#define MCSM2 0x16 // Main Radio Cntrl State Machine config +#define MCSM1 0x17 // Main Radio Cntrl State Machine config +#define MCSM0 0x18 // Main Radio Cntrl State Machine config +#define FOCCFG 0x19 // Frequency Offset Compensation config +#define BSCFG 0x1A // Bit Synchronization configuration +#define AGCCTRL2 0x1B // AGC control +#define AGCCTRL1 0x1C // AGC control +#define AGCCTRL0 0x1D // AGC control +#define WOREVT1 0x1E // High byte Event 0 timeout +#define WOREVT0 0x1F // Low byte Event 0 timeout +#define WORCTRL 0x20 // Wake On Radio control +#define FREND1 0x21 // Front end RX configuration +#define FREND0 0x22 // Front end TX configuration +#define FSCAL3 0x23 // Frequency synthesizer calibration +#define FSCAL2 0x24 // Frequency synthesizer calibration +#define FSCAL1 0x25 // Frequency synthesizer calibration +#define FSCAL0 0x26 // Frequency synthesizer calibration +#define RCCTRL1 0x27 // RC oscillator configuration +#define RCCTRL0 0x28 // RC oscillator configuration +#define FSTEST 0x29 // Frequency synthesizer cal control +#define PTEST 0x2A // Production test +#define AGCTEST 0x2B // AGC test +#define TEST2 0x2C // Various test settings +#define TEST1 0x2D // Various test settings +#define TEST0 0x2E // Various test settings +/*-------------------------[END config register]------------------------------*/ + +/*------------------------[CC1101-command strobes]----------------------------*/ +#define SRES 0x30 // Reset chip +#define SFSTXON 0x31 // Enable/calibrate freq synthesizer +#define SXOFF 0x32 // Turn off crystal oscillator. +#define SCAL 0x33 // Calibrate freq synthesizer & disable +#define SRX 0x34 // Enable RX. +#define STX 0x35 // Enable TX. +#define SIDLE 0x36 // Exit RX / TX +#define SAFC 0x37 // AFC adjustment of freq synthesizer +#define SWOR 0x38 // Start automatic RX polling sequence +#define SPWD 0x39 // Enter pwr down mode when CSn goes hi +#define SFRX 0x3A // Flush the RX FIFO buffer. +#define SFTX 0x3B // Flush the TX FIFO buffer. +#define SWORRST 0x3C // Reset real time clock. +#define SNOP 0x3D // No operation. +/*-------------------------[END command strobes]------------------------------*/ + +/*----------------------[CC1101 - status register]----------------------------*/ +#define PARTNUM 0xF0 // Part number +#define VERSION 0xF1 // Current version number +#define FREQEST 0xF2 // Frequency offset estimate +#define LQI 0xF3 // Demodulator estimate for link quality +#define RSSI 0xF4 // Received signal strength indication +#define MARCSTATE 0xF5 // Control state machine state +#define WORTIME1 0xF6 // High byte of WOR timer +#define WORTIME0 0xF7 // Low byte of WOR timer +#define PKTSTATUS 0xF8 // Current GDOx status and packet status +#define VCO_VC_DAC 0xF9 // Current setting from PLL cal module +#define TXBYTES 0xFA // Underflow and # of bytes in TXFIFO +#define RXBYTES 0xFB // Overflow and # of bytes in RXFIFO +#define RCCTRL1_STATUS 0xFC //Last RC Oscillator Calibration Result +#define RCCTRL0_STATUS 0xFD //Last RC Oscillator Calibration Result +//--------------------------[END status register]------------------------------- + +/*----------------------[CC1101 - Main Radio Control State Machine states]-----*/ +#define MARCSTATE_BITMASK 0x1F +#define MARCSTATE_SLEEP 0x00 +#define MARCSTATE_IDLE 0x01 +#define MARCSTATE_XOFF 0x02 +#define MARCSTATE_VCOON_MC 0x03 +#define MARCSTATE_REGON_MC 0x04 +#define MARCSTATE_MANCAL 0x05 +#define MARCSTATE_VCOON 0x06 +#define MARCSTATE_REGON 0x07 +#define MARCSTATE_STARTCAL 0x08 +#define MARCSTATE_BWBOOST 0x09 +#define MARCSTATE_FS_LOCK 0x0A +#define MARCSTATE_IFADCON 0x0B +#define MARCSTATE_ENDCAL 0x0C +#define MARCSTATE_RX 0x0D +#define MARCSTATE_RX_END 0x0E +#define MARCSTATE_RX_RST 0x0F +#define MARCSTATE_TXRX_SWITCH 0x10 +#define MARCSTATE_RXFIFO_OVERFLOW 0x11 +#define MARCSTATE_FSTXON 0x12 +#define MARCSTATE_TX 0x13 +#define MARCSTATE_TX_END 0x14 +#define MARCSTATE_RXTX_SWITCH 0x15 +#define MARCSTATE_TXFIFO_UNDERFLOW 0x16 + +// Chip Status Byte +// Bit fields in the chip status byte +#define CHIPSTATUS_CHIP_RDYn_BITMASK 0x80 +#define CHIPSTATUS_STATE_BITMASK 0x70 +#define CHIPSTATUS_FIFO_BYTES_AVAILABLE_BITMASK 0x0F +// Chip states + #define CHIPSTATUS_STATE_IDLE 0x00 + #define CHIPSTATUS_STATE_RX 0x10 + #define CHIPSTATUS_STATE_TX 0x20 + #define CHIPSTATUS_STATE_FSTXON 0x30 + #define CHIPSTATUS_STATE_CALIBRATE 0x40 + #define CHIPSTATUS_STATE_SETTLING 0x50 + #define CHIPSTATUS_STATE_RX_OVERFLOW 0x60 + #define CHIPSTATUS_STATE_TX_UNDERFLOW 0x70 + +// loop states +#define RX_START 0 +#define RX_ACTIVE 1 +#define RX_END 2 +#define TX_START 3 +#define TX_ACTIVE 4 +#define TX_END 5 + +class RfDataLinkLayer; + +class RfPhysicalLayerCC1101 : public RfPhysicalLayer +{ + public: + RfPhysicalLayerCC1101(RfDataLinkLayer& rfDataLinkLayer, Platform& platform); + + bool InitChip(); + void showRegisterSettings(); + void stopChip(); + void loop(); + + private: + // Table for encoding 4-bit data into a 8-bit Manchester encoding. + static const uint8_t manchEncodeTab[16]; + // Table for decoding 4-bit Manchester encoded data into 2-bit + static const uint8_t manchDecodeTab[16]; + + static const uint8_t cc1101_2FSK_32_7_kb[CFG_REGISTER]; + static const uint8_t paTablePower868[8]; + + void manchEncode(uint8_t *uncodedData, uint8_t *encodedData); + bool manchDecode(uint8_t *encodedData, uint8_t *decodedData); + + void powerDownCC1101(); + void setOutputPowerLevel(int8_t dBm); + + uint8_t sIdle(); + uint8_t sReceive(); + + void spiWriteRegister(uint8_t spi_instr, uint8_t value); + uint8_t spiReadRegister(uint8_t spi_instr); + uint8_t spiWriteStrobe(uint8_t spi_instr); + void spiReadBurst(uint8_t spi_instr, uint8_t *pArr, uint8_t len); + void spiWriteBurst(uint8_t spi_instr, const uint8_t *pArr, uint8_t len); + + uint8_t _loopState = RX_START; + + bool syncStart = false; + bool packetStart = true; + bool fixedLengthMode = false; + uint8_t *sendBuffer {0}; + uint16_t sendBufferLength {0}; + uint8_t packet[512]; + uint8_t buffer[sizeof(packet)*2]; // We need twice the space due to manchester encoding + uint8_t* pByteIndex = &buffer[0]; + uint16_t pktLen {0}; + uint16_t bytesLeft = {0}; + uint8_t statusGDO0 {0}; + uint8_t statusGDO2 {0}; + uint8_t prevStatusGDO0 {0}; // for edge detection during polling + uint8_t prevStatusGDO2 {0}; // for edge detection during polling + uint32_t packetStartTime {0}; +}; + +#endif // USE_RF + +#endif // DeviceFamily_CC13X0 \ No newline at end of file diff --git a/src/knx/rf_physical_layer_cc1310.cpp b/src/knx/rf_physical_layer_cc1310.cpp new file mode 100644 index 0000000..8866479 --- /dev/null +++ b/src/knx/rf_physical_layer_cc1310.cpp @@ -0,0 +1,357 @@ +#ifdef DeviceFamily_CC13X0 + +#include "config.h" +#ifdef USE_RF + +#include +#include +#include + +#include "rf_physical_layer_cc1310.h" +#include "rf_data_link_layer.h" + +#include +#include DeviceFamily_constructPath(driverlib/rf_data_entry.h) +#include DeviceFamily_constructPath(driverlib/rf_prop_mailbox.h) +#include +#include "smartrf_settings/smartrf_settings.h" + +#include "cc1310_platform.h" +#include "Board.h" + +#include "bits.h" +#include "platform.h" + +#define RX_MAX_BUFFER_LENGTH 256 +#define RF_TERMINATION_EVENT_MASK (RF_EventLastCmdDone | RF_EventLastFGCmdDone | RF_EventCmdAborted | RF_EventCmdStopped | RF_EventCmdCancelled) + +#define DEBUG_DUMP_PACKETS + +static RF_Object rfObject; +static RF_Handle rfHandle; +static RF_CmdHandle rxCommandHandle; + +static uint8_t rxBuffer[sizeof(rfc_dataEntryPartial_t) + RX_MAX_BUFFER_LENGTH] __attribute__((aligned(4))); +static rfc_dataEntryPartial_t* pDataEntry = (rfc_dataEntryPartial_t*)&rxBuffer; +static dataQueue_t dataQueue; + +static uint8_t addrFilterTable[2] = {0x44, 0xFF}; // Do not modify the size without changing RF_cmdPropRxAdv.addrConf.addrSize! + +static rfc_propRxOutput_t rxStatistics; + +static uint8_t packetLength; +static uint8_t* packetDataPointer; +static int32_t packetStartTime = 0; + +static volatile bool rfDone = false; +static volatile int rfErr = 0; +static volatile int err; + +static void RxCallback(RF_Handle h, RF_CmdHandle ch, RF_EventMask e) +{ + /* + static uint32_t count = 0; + + print("count: ");println(count++); + print("nextIndex: ");println(pDataEntry->nextIndex); + //print("pktStatus.numElements: ");println(pDataEntry->pktStatus.numElements); + print("RF_cmdPropRxAdv.status: ");println(RF_cmdPropRxAdv.status, HEX); + print("pktStatus.bEntryOpen: ");println(pDataEntry->pktStatus.bEntryOpen, HEX); + print("RF_EventMask: ");println(e, HEX); + */ + + if (e & RF_EventNDataWritten) + { + // Make sure sure we are at the beginning of the packet + if (packetStartTime == 0) + { + packetStartTime = millis(); + + // pDataEntry->rxData contains the first byte of the received packet. + // Just get the address to get the start address of the receive buffer + uint8_t *pData = &pDataEntry->rxData; + // Make sure we have a valid first block + if (((pData[1] != addrFilterTable[0]) || (pData[2] != addrFilterTable[1])) || + (crc16Dnp(pData, 10) != ((pData[10] << 8) | pData[11]))) + { + // cancel early because it does not seem to be KNX RF packet + RF_cancelCmd(rfHandle, rxCommandHandle, 0 /* force abort RF */); + return; + } + + // First block is valid, so the length is valid + uint8_t len = pDataEntry->rxData; + struct rfc_CMD_PROP_SET_LEN_s RF_cmdPropSetLen = + { + .commandNo = CMD_PROP_SET_LEN, // command identifier + .rxLen = (uint16_t)PACKET_SIZE(len) // packet length to set + }; + + //RF_runImmediateCmd(rfHandle, (uint32_t*)&RF_cmdPropSetLen); // for length > 255 + RF_Stat status = RF_runDirectCmd(rfHandle, (uint32_t)&RF_cmdPropSetLen); + if (status != RF_StatCmdDoneSuccess) + { + println("RF CMD_PROP_SET_LEN failed!"); + } + } + } + else if (e & RF_TERMINATION_EVENT_MASK) + { + if (e & RF_EventCmdAborted) + { + packetStartTime = 0; + println("RX ABORT"); + return; + } + + rfDone = true; + rfErr = e & (RF_EventCmdStopped | RF_EventCmdAborted | RF_EventCmdCancelled); + } + else /* unknown reason - should not occur */ + { + pDataEntry->status = DATA_ENTRY_PENDING; + err++; + } +} + +RfPhysicalLayerCC1310::RfPhysicalLayerCC1310(RfDataLinkLayer& rfDataLinkLayer, Platform& platform) + : RfPhysicalLayer(rfDataLinkLayer, platform) +{ +} + +void RfPhysicalLayerCC1310::setOutputPowerLevel(int8_t dBm) +{ + RF_TxPowerTable_Entry *rfPowerTable = NULL; + RF_TxPowerTable_Value newValue; + uint8_t rfPowerTableSize = 0; + + // Search the default PA power table for the desired power level + newValue = RF_TxPowerTable_findValue((RF_TxPowerTable_Entry *)PROP_RF_txPowerTable, dBm); + if(newValue.rawValue != RF_TxPowerTable_INVALID_VALUE) + { + // Found a valid entry + rfPowerTable = (RF_TxPowerTable_Entry *)PROP_RF_txPowerTable; + rfPowerTableSize = PROP_RF_txPowerTableSize; + } + + //if max power is requested then the CCFG_FORCE_VDDR_HH must be set in + //the ccfg +#if (CCFG_FORCE_VDDR_HH != 0x1) + if((newValue.paType == RF_TxPowerTable_DefaultPA) && + (dBm == rfPowerTable[rfPowerTableSize-2].power)) + { + // The desired power level is set to the maximum supported under the + // default PA settings, but the boost mode (CCFG_FORCE_VDDR_HH) is not + // turned on + return; + } +#endif + + RF_Stat rfStatus = RF_setTxPower(rfHandle, newValue); + if(rfStatus == RF_StatSuccess) + { + print("Successfully set TX output power to: "); + println(newValue.rawValue); + } + else + { + print("Could not set TX output power to: "); + println(newValue.rawValue); + } +} + + +bool RfPhysicalLayerCC1310::InitChip() +{ + RF_Params rfParams; + RF_Params_init(&rfParams); + + pDataEntry->length = 255; + pDataEntry->config.type = DATA_ENTRY_TYPE_PARTIAL; // --> DATA_ENTRY_TYPE_PARTIAL adds a 12 Byte Header + pDataEntry-> config.irqIntv = 12; // KNX-RF first block consists of 12 bytes (one length byte, 0x44, 0xFF, one RFinfo byte, six Serial/DoA bytes, two CRC bytes) + pDataEntry-> config.lenSz = 0; // no length indicator at beginning of data entry + pDataEntry->status = DATA_ENTRY_PENDING; + pDataEntry->pNextEntry = (uint8_t*)pDataEntry; + + dataQueue.pCurrEntry = (uint8_t*)pDataEntry; + dataQueue.pLastEntry = NULL; + + // Set buffer with address. We use the two fixed bytes 0x44 and 0xFF as our address to let the + // packet engine do more filtering on itself + RF_cmdPropRxAdv.pAddr = (uint8_t*)&addrFilterTable; + // Set the Data Entity queue for received data + RF_cmdPropRxAdv.pQueue = &dataQueue; + // Set the output buffer for RX packet statistics + RF_cmdPropRxAdv.pOutput = (uint8_t*)&rxStatistics; + + // Request access to the radio + rfHandle = RF_open(&rfObject, &RF_prop, (RF_RadioSetup*)&RF_cmdPropRadioDivSetup, &rfParams); + + /* Set the frequency */ + RF_runCmd(rfHandle, (RF_Op*)&RF_cmdFs, RF_PriorityNormal, NULL, 0); + return true; +} + +void RfPhysicalLayerCC1310::stopChip() +{ + RF_cancelCmd(rfHandle, rxCommandHandle, 0 /* do not stop gracefully, instead hard abort RF */); + RF_pendCmd(rfHandle, rxCommandHandle, RF_TERMINATION_EVENT_MASK); + RF_yield(rfHandle); + RF_close(rfHandle); +} + +void RfPhysicalLayerCC1310::loop() +{ + switch (_loopState) + { + case TX_START: + { + uint8_t *sendBuffer {nullptr}; + uint16_t sendBufferLength {0}; + + //println("TX_START..."); + _rfDataLinkLayer.loadNextTxFrame(&sendBuffer, &sendBufferLength); + uint16_t pktLen = PACKET_SIZE(sendBuffer[0]); + + if (pktLen != sendBufferLength) + { + print("Error TX: SendBuffer[0]=");println(sendBuffer[0]); + print("Error TX: SendBufferLength=");println(sendBufferLength); + print("Error TX: PACKET_SIZE=");println(PACKET_SIZE(sendBuffer[0])); + } + + // Calculate total number of bytes in the KNX RF packet from L-field + // Check for valid length + if ((pktLen == 0) || (pktLen > 290)) + { + println("TX packet length error!"); + break; + } + + if (pktLen > 255) + { + println("Unhandled: TX packet > 255"); + break; + } + + RF_cmdPropTx.pktLen = pktLen; + RF_cmdPropTx.pPkt = sendBuffer; + RF_cmdPropTx.startTrigger.triggerType = TRIG_NOW; + RF_EventMask result = RF_runCmd(rfHandle, (RF_Op*)&RF_cmdPropTx, RF_PriorityNormal, NULL, RF_TERMINATION_EVENT_MASK); + //print("TX: RF_EventMask: ");println(result, HEX); + +#if defined(DEBUG_DUMP_PACKETS) + printHex("TX: ", sendBuffer, pktLen); +#endif + delete sendBuffer; + + if (result != RF_EventLastCmdDone) + { + print("Unexpected result command: ");println(result, HEX); + } + + //println("Restart RX..."); + _loopState = RX_START; + } + break; + + case RX_START: + { + packetStartTime = 0; + rfDone = false; + rfErr = 0; + err = 0; + pDataEntry->status = DATA_ENTRY_PENDING; + + rxCommandHandle = RF_postCmd(rfHandle, (RF_Op*)&RF_cmdPropRxAdv, RF_PriorityNormal, &RxCallback, RF_EventNDataWritten | RF_EventRxAborted); + if (rxCommandHandle == RF_ALLOC_ERROR) + { + println("Error: nRF_pendCmd() failed"); + return; + } + _loopState = RX_ACTIVE; + } + break; + + case RX_ACTIVE: + { + if (!_rfDataLinkLayer.isTxQueueEmpty()) + { + RF_cancelCmd(rfHandle, rxCommandHandle, RF_ABORT_GRACEFULLY); + RF_pendCmd(rfHandle, rxCommandHandle, RF_TERMINATION_EVENT_MASK); + if (RF_cmdPropTx.status != PROP_DONE_OK) + { + print("Unexpected RF_cmdPropTx.status after stopping RX: ");println(RF_cmdPropTx.status, HEX); + } + _loopState = TX_START; + break; + } + + // Check if we have an incomplete packet reception + if (!rfDone && ((packetStartTime > 0) && (millis() - packetStartTime > RX_PACKET_TIMEOUT))) + { + println("RX packet timeout!"); + RF_cancelCmd(rfHandle, rxCommandHandle, RF_ABORT_GRACEFULLY); + RF_pendCmd(rfHandle, rxCommandHandle, RF_TERMINATION_EVENT_MASK); + /* + print("nRxOk = ");println(rxStatistics.nRxOk); // Number of packets that have been received with payload, CRC OK and not ignored + print("nRxNok = ");println(rxStatistics.nRxNok); // Number of packets that have been received with CRC error + print("nRxIgnored = ");println(rxStatistics.nRxIgnored); // Number of packets that have been received with CRC OK and ignored due to address mismatch + print("nRxStopped = ");println(rxStatistics.nRxStopped); // Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1 + print("nRxBufFull = ");println(rxStatistics.nRxBufFull); // Number of packets that have been received and discarded due to lack of buffer space + */ + _loopState = RX_START; + break; + } + else if (rfDone) + { + RF_EventMask result = RF_pendCmd(rfHandle, rxCommandHandle, RF_TERMINATION_EVENT_MASK); + if ((result & RF_EventCmdCancelled) || (result & RF_EventCmdStopped) || (result & RF_EventCmdAborted)) + { + println("RF terminated because of RF_flushCmd() or RF_cancelCmd()"); + } + else if ((result & RF_EventLastCmdDone) != RF_EventLastCmdDone) + { + print("Unexpected Rx result command: ");println(result, HEX); + } + else if (rfErr) + { + println("Rx is no KNX frame"); + } + else if ((result & RF_EventLastCmdDone) == RF_EventLastCmdDone) + { + // add CRC sizes for received blocks, but do not add the length of the L-field (1 byte) itself + packetLength = PACKET_SIZE(pDataEntry->rxData); + packetDataPointer = (uint8_t *) &pDataEntry->rxData; + + // Sanity check: the partial data entry index points to the next free location in the partial RX buffer + if (packetLength != (pDataEntry->nextIndex - 1)) + { + println("Mismatch between packetLength and pDataEntry->nextIndex: "); + print("packetLength = ");print(packetLength); + print(", pDataEntry->nextIndex = ");println(pDataEntry->nextIndex); + } + /* + print("nRxOk = ");println(rxStatistics.nRxOk); // Number of packets that have been received with payload, CRC OK and not ignored + print("nRxNok = ");println(rxStatistics.nRxNok); // Number of packets that have been received with CRC error + print("nRxIgnored = ");println(rxStatistics.nRxIgnored); // Number of packets that have been received with CRC OK and ignored due to address mismatch + print("nRxStopped = ");println(rxStatistics.nRxStopped); // Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1 + print("nRxBufFull = ");println(rxStatistics.nRxBufFull); // Number of packets that have been received and discarded due to lack of buffer space + */ + +#if defined(DEBUG_DUMP_PACKETS) + printHex("RX: ", packetDataPointer, packetLength, false); + print ("- RSSI: ");println(rxStatistics.lastRssi); +#endif + _rfDataLinkLayer.frameBytesReceived(packetDataPointer, packetLength); + } + _loopState = RX_START; + } + } + break; + } +} + +#endif // USE_RF + +#endif // DeviceFamily_CC13X0 \ No newline at end of file diff --git a/src/knx/rf_physical_layer_cc1310.h b/src/knx/rf_physical_layer_cc1310.h new file mode 100644 index 0000000..80f0bd4 --- /dev/null +++ b/src/knx/rf_physical_layer_cc1310.h @@ -0,0 +1,41 @@ +#pragma once + +#ifdef DeviceFamily_CC13X0 + +#include "config.h" +#ifdef USE_RF + +#include + +#include "rf_physical_layer.h" + +#define RX_PACKET_TIMEOUT 20 // Wait 20ms for packet reception to complete + +// loop states +#define RX_START 0 +#define RX_ACTIVE 1 +#define RX_END 2 +#define TX_START 3 +#define TX_ACTIVE 4 +#define TX_END 5 + +class RfDataLinkLayer; + +class RfPhysicalLayerCC1310 : public RfPhysicalLayer +{ + public: + RfPhysicalLayerCC1310(RfDataLinkLayer& rfDataLinkLayer, Platform& platform); + + virtual bool InitChip() override; + virtual void stopChip() override; + virtual void loop() override; + + void setOutputPowerLevel(int8_t dBm); + + private: + uint8_t _loopState = RX_START; +}; + +#endif // USE_RF + +#endif // DeviceFamily_CC13X0 \ No newline at end of file diff --git a/src/knx_facade.cpp b/src/knx_facade.cpp index fb95b18..272256f 100644 --- a/src/knx_facade.cpp +++ b/src/knx_facade.cpp @@ -40,20 +40,30 @@ #else #error Mask version not supported on ARDUINO_ARCH_STM32 #endif -#elif __linux__ +#else // Non-Arduino platforms and Linux platform // no predefined global instance #endif +// Only ESP8266 and ESP32 have this define. For all other platforms this is just empty. #ifndef ICACHE_RAM_ATTR #define ICACHE_RAM_ATTR #endif + +#if (defined(ARDUINO_ARCH_STM32) || \ + defined(ARDUINO_ARCH_ESP32) || \ + defined(ARDUINO_ARCH_ESP8266) || \ + defined(ARDUINO_ARCH_SAMD)) ICACHE_RAM_ATTR void buttonUp() { - #ifndef __linux__ static uint32_t lastpressed=0; if (millis() - lastpressed > 200){ knx._toogleProgMode = true; lastpressed = millis(); } - #endif } +#elif defined(__linux__) +void buttonUp() +{ + // no de-bounce on linux platform, just satisfy the compiler +} +#endif \ No newline at end of file diff --git a/src/knx_facade.h b/src/knx_facade.h index c2a9c5d..232d37a 100644 --- a/src/knx_facade.h +++ b/src/knx_facade.h @@ -8,19 +8,23 @@ #include "knx/bau07B0.h" #include "knx/bau27B0.h" #include "knx/bau2920.h" + void buttonUp(); #elif ARDUINO_ARCH_ESP8266 #include "esp_platform.h" #include "knx/bau57B0.h" + void buttonUp(); #elif ARDUINO_ARCH_ESP32 #define LED_BUILTIN 13 #include "esp32_platform.h" #include "knx/bau07B0.h" #include "knx/bau57B0.h" #include "knx/bau091A.h" + void buttonUp(); #elif ARDUINO_ARCH_STM32 #include "stm32_platform.h" #include "knx/bau07B0.h" -#else + void buttonUp(); +#elif __linux__ #define LED_BUILTIN 0 #include "linux_platform.h" #include "knx/bau57B0.h" @@ -28,11 +32,18 @@ #include "knx/bau07B0.h" #include "knx/bau091A.h" #include "knx/bau2920.h" + void buttonUp(); +#else + #define LED_BUILTIN 5 // see GPIO_PinConfig gpioPinConfigs[] + #include "cc1310_platform.h" + #include "knx/bau27B0.h" + #include "knx/bau07B0.h" + #include "knx/bau2920.h" + extern void buttonUp(); #endif -void buttonUp(); typedef uint8_t* (*SaveRestoreCallback)(uint8_t* buffer); - + template class KnxFacade : private SaveRestore { friend void buttonUp(); @@ -357,6 +368,6 @@ template class KnxFacade : private SaveRestore #else #error Mask version not supported on ARDUINO_ARCH_STM32 #endif -#elif __linux__ +#else // Non-Arduino platforms and Linux platform // no predefined global instance #endif